diff -Nru gxemul-0.6.2/configure gxemul-0.7.0+dfsg/configure
--- gxemul-0.6.2/configure	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/configure	2021-11-27 09:42:23.000000000 +0000
@@ -1,7 +1,7 @@
 #!/bin/sh
 ###############################################################################
 #
-#  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
+#  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
 #
 #  Redistribution and use in source and binary forms, with or without
 #  modification, are permitted provided that the following conditions are met:
@@ -36,7 +36,7 @@
 #
 #
 #  To compile the emulator with profiling (during development), use
-#  CXXFLAGS="-pg", run the emulator, and then run 'gprof gxemul' and study
+#  CFLAGS="-pg", run the emulator, and then run 'gprof gxemul' and study
 #  the results.
 #
 #  Or better, using callgrind/cachegrind/kcachegrind:
@@ -50,8 +50,8 @@
 #  The main things that are detected by this script:
 #
 #    o)  special hacks for some OSes
-#    o)  which compiler(s) to use  (overridden by setting CXX)
-#    o)  which compiler flags to use  (overridden by setting CXXFLAGS)
+#    o)  which compiler to use  (overridden by setting CC)
+#    o)  which compiler flags to use  (overridden by setting CFLAGS)
 #    o)  X11 flags and libraries  (TODO: should be possible to override
 #	 via command line options?)
 #
@@ -69,8 +69,8 @@
 #
 DEFAULTPREFIX=/usr/local
 
-# Special exception for Linux systems: /usr
 if [ z`uname` = zLinux ]; then
+	# /usr is more common on Linux than /usr/local
 	DEFAULTPREFIX=/usr
 else
 	TRY=/usr/local
@@ -91,38 +91,21 @@
 
 OTHERLIBS="$LDFLAGS"
 
-UNITTESTS=YES
-
-#  Figure out if this is a stable version (0.x.x).
-X=`basename \`pwd\`|cut -d \- -f 2-|cut -c1-2`
-if [ z"$X" = z0. ]; then
-	#  Stable.
-	:
-else
-	#  Development.
-	UNSTABLE=YES
-fi
 
 if [ z"$*" != z ]; then
 	#  Parse command line options:
 	for a in $*; do
 		if [ z$a = z--disable-x ]; then
 			NOX11=YES
-		else if [ z$a = z--without-unittests ]; then
-			UNITTESTS=NO
-		else if [ z$a = z--disable-valgrind ]; then
-			DISABLEVALGRIND=YES
 		else if [ z$a = z--debug ]; then
 			DEBUG=YES
 		else if [ z$a = z--help ]; then
 			printf "usage: $0 [options]\n\n"
 			echo "  --disable-x           don't include X11 support,"\
 			    "even if the host supports it"
-			echo "  --disable-valgrind    don't use valgrind, even"\
-			    "if it is installed"
-			echo "  --without-unittests   don't include unit tests"
 			echo "  --debug               configure for a" \
-				"debug build (turn off optimizations)"
+				"debug build (turn off optimizations,"
+			echo "                        try enabling -Werror etc.)"
 			echo
 			echo "If the PREFIX environment variable is set," \
 			    "it will override the default"
@@ -134,7 +117,7 @@
 			echo "Run  $0 --help  to get a list of" \
 			    "available options."
 			exit
-		fi; fi; fi; fi; fi
+		fi; fi; fi
 	done
 fi
 
@@ -164,19 +147,8 @@
 fi
 
 
-if [ z"$UNSTABLE" = zYES ]; then
-	printf "#define UNSTABLE_DEVEL\n" >> config.h
-fi
-
-if [ z"$UNITTESTS" = zYES ]; then
-	printf "#define WITHUNITTESTS\n" >> config.h
-fi
-
 if [ z"$DEBUG" = zYES ]; then
-	echo "Building a debug version!"
-	CXXFLAGS="-D_GLIBCXX_DEBUG -D_GLIBCXX_DEBUG_PEDANTIC $CXXFLAGS"
-else
-	CXXFLAGS="-DNDEBUG $CXXFLAGS"
+	echo "Building a DEBUG version!"
 fi
 
 
@@ -216,6 +188,10 @@
 CPU_TOOLS="$CPU_TOOLS generate_arm_dpi generate_arm_r"
 CPU_TOOLS="$CPU_TOOLS generate_arm_loadstore generate_arm_multi"
 
+#  i960
+printf " add_cpu_family(i960_cpu_family_init, ARCH_I960);" >> config.h
+CPU_ARCHS="$CPU_ARCHS cpu_i960.o memory_i960.o"
+
 #  M88K
 printf " add_cpu_family(m88k_cpu_family_init, ARCH_M88K);" >> config.h
 CPU_ARCHS="$CPU_ARCHS cpu_m88k.o memory_m88k.o"
@@ -234,6 +210,10 @@
 CPU_ARCHS="$CPU_ARCHS cpu_ppc.o"
 CPU_TOOLS="$CPU_TOOLS generate_ppc_loadstore"
 
+#  RISC-V
+printf " add_cpu_family(riscv_cpu_family_init, ARCH_RISCV);" >> config.h
+CPU_ARCHS="$CPU_ARCHS cpu_riscv.o memory_riscv.o"
+
 #  SuperH
 printf " add_cpu_family(sh_cpu_family_init, ARCH_SH);" >> config.h
 CPU_ARCHS="$CPU_ARCHS cpu_sh.o memory_sh.o"
@@ -243,22 +223,6 @@
 
 ###############################################################################
 #
-#  Special hacks for some host OSes:
-#
-###############################################################################
-
-if [ z"`uname|cut -c 1-6`" = zCYGWIN ]; then
-	CYGWIN=YES
-
-	if [ z"$CXX" = z ]; then
-		#  Assume GNU C++ on Cygwin (Windows) systems.
-		CC=g++
-	fi
-fi
-
-
-###############################################################################
-#
 #  Create the Makefile header:
 #
 ###############################################################################
@@ -277,71 +241,77 @@
 #  known to be completely broken, for instance.)
 
 echo '#include <stdio.h>
+#include <stdbool.h>
 
-int main(int argc, char *argv[])
+int main(int argc, char* argv[])
 {
-        static int x = 0;
-        static int y = 1;
-        printf("%i,%i", x, y);
-        return 0;
+	static int s = 0;
+	int x = 2;	// make sure that BCPL style comments work,
+	x ++;		// that code and variable declarations can be
+	int y = -2;	// mixed, and that the bool type behaves
+	bool a = x;	// reasonably.
+	bool b = y;
+	bool c = a + b;
+	int d = a + b;
+	printf("%i,%i,%i,%i,%i", s, a, b, c, d);
+	for (int i = 0; i < 10; ++i) ;
+	return 0;
 }
-' > _testprog.cc
+' > _testprog.c
 
 
-#  Try to detect which C++ compiler to use, if CXX is not set:
-printf "checking which C++ compiler to use... "
+#  Try to detect which C compiler to use, if CC is not set:
+printf "checking which C compiler to use... "
 rm -f _testprog
-if [ z"$CXX" = z ]; then
-	#  Try g++ first:
-	printf "#!/bin/sh\ng++ $CXXFLAGS _testprog.cc -o _testprog >" > _test.sh
-	printf " /dev/null 2> /dev/null\n" >> _test.sh
-	chmod 755 _test.sh
-	./_test.sh > /dev/null 2> /dev/null
-	if [ -x _testprog ]; then
-		if [ z`./_testprog` = z0,1 ]; then
-			CXX=g++
-		else
-			printf "broken g++ detected\n"
-			printf "The test program:\n\n"
-			cat _testprog.cc
-			printf "\nshould have resulted in 0,1, but the"
-			printf " result was: "
-			./_testprog
-			printf "\n\nchecking for other C++ compilers... "
-		fi
-	fi
-	rm -f _testprog
+if [ z"$CC" = z ]; then
+	CC=cc
+fi
 
-	#  If both g++ and c++ exist, then c++ might be a vendor specific
-	#  compiler which produces faster code:
-	printf "#!/bin/sh\nc++ $CXXFLAGS _testprog.cc -o _testprog >" > _test.sh
-	printf " /dev/null 2> /dev/null\n" >> _test.sh
-	chmod 755 _test.sh
-	./_test.sh > /dev/null 2> /dev/null
-	if [ -x _testprog ]; then
-		if [ z`./_testprog` = z0,1 ]; then
-			CXX=c++
-		else
-			printf "broken c++ detected\n"
-			printf "checking for other C++ compilers... "
-		fi
+printf "#!/bin/sh\n$CC $CFLAGS _testprog.c -o _testprog >" > _test.sh
+printf " /dev/null 2> /dev/null\n" >> _test.sh
+chmod 755 _test.sh
+./_test.sh > /dev/null 2> /dev/null
+OK=0
+if [ -x _testprog ]; then
+	OK=1
+	if [ z`./_testprog` = z0,1,1,1,2 ]; then
+		OK=2
 	fi
-	rm -f _testprog
-	rm -f _test.sh
 fi
 
-rm -f _testprog
+if [ z$OK = z0 ]; then
+	printf "broken cc detected: $CC $CFLAGS\n"
+	printf "The test program:\n\n"
+	cat _testprog.c
+	printf "could not be compiled at all.\n"
+fi
 
-if [ z"$CXX" = z ]; then
-	printf "no working compiler detected\n"
-	printf "\nPlease set the CXX environment variable to a working C++ "
+if [ z$OK = z1 ]; then
+	printf "broken cc detected: $CC $CFLAGS\n"
+	printf "The test program:\n\n"
+	cat _testprog.c
+	printf "should have resulted in  0,1,1,1,2  but the result was: "
+	./_testprog
+fi
+
+if [ z$OK != z2 ]; then
+	printf "\nPlease set the CC environment variable to a working C "
 	printf "compiler before running\nthe configure script, and make"
-	printf " sure that the CXXFLAGS environment variable is\nalso valid"
-	printf " for that compiler.\n"
+	printf " sure that the CFLAGS environment variable is\nalso valid"
+	printf " for that compiler (e.g. -std=c99 if needed).\n"
 	exit
 fi
 
-echo "$CXX $CXXFLAGS"
+rm -f _testprog
+rm -f _test.sh
+
+
+echo "$CC $CFLAGS"
+
+
+if [ z"$DEBUG" != zYES ]; then
+	CFLAGS="-DNDEBUG $CFLAGS"
+fi
 
 
 if [ z$NOX11 = z ]; then
@@ -355,32 +325,51 @@
 		dis = XOpenDisplay(NULL);
 	}
 	int main(int argc, char *argv[])
-	{ return 0; }
-	" > _test_x11.cc
+	{ printf(\"1\"); return 0; }
+	" > _test_x11.c
 
 	XOK=0
 
 	XINCLUDE=-I/usr/X11R6/include
-	$CXX $CXXFLAGS _test_x11.cc -c -o _test_x11.o $XINCLUDE 2> /dev/null
+	$CC $CFLAGS _test_x11.c -c -o _test_x11.o $XINCLUDE 2> /dev/null
 
-	XLIB="-L/usr/X11R6/lib -lX11"
-	$CXX $CXXFLAGS _test_x11.o -o _test_x11 $XLIB 2> /dev/null
+	XLIB="-L/usr/X11R6/lib -lX11 -Wl,-rpath,/usr/X11R6/lib"
+	$CC $CFLAGS _test_x11.o -o _test_x11 $XLIB 2> /dev/null
 
 	if [ -x _test_x11 ]; then
-		XOK=1
+		if [ 1 = `./_test_x11` ]; then
+			XOK=1
+		fi
 	fi
 
 	rm -f _test_x11 _test_x11.o
 
 	if [ z$XOK = z0 ]; then
+		XINCLUDE=-I/usr/X11R7/include
+		$CC $CFLAGS _test_x11.c -c -o _test_x11.o $XINCLUDE 2> /dev/null
+
+		XLIB="-L/usr/X11R7/lib -lX11 -Wl,-rpath,/usr/X11R7/lib"
+		$CC $CFLAGS _test_x11.o -o _test_x11 $XLIB 2> /dev/null
+
+		if [ -x _test_x11 ]; then
+			if [ 1 = `./_test_x11` ]; then
+				XOK=1
+			fi
+		fi
+	fi
+	rm -f _test_x11 _test_x11.o
+
+	if [ z$XOK = z0 ]; then
 		XINCLUDE=-I/usr/local/include
-		$CXX $CXXFLAGS _test_x11.cc -c -o _test_x11.o $XINCLUDE 2> /dev/null
+		$CC $CFLAGS _test_x11.c -c -o _test_x11.o $XINCLUDE 2> /dev/null
 
-		XLIB="-L/usr/local/lib -lX11"
-		$CXX $CXXFLAGS _test_x11.o -o _test_x11 $XLIB 2> /dev/null
+		XLIB="-L/usr/local/lib -lX11 -Wl,-rpath,/usr/local/lib"
+		$CC $CFLAGS _test_x11.o -o _test_x11 $XLIB 2> /dev/null
 
 		if [ -x _test_x11 ]; then
-			XOK=1
+			if [ 1 = `./_test_x11` ]; then
+				XOK=1
+			fi
 		fi
 	fi
 	rm -f _test_x11 _test_x11.o
@@ -388,10 +377,10 @@
 	# MacOS:
 	if [ z$XOK = z0 ]; then
 		XINCLUDE=-I/opt/X11/include
-		$CXX $CXXFLAGS _test_x11.cc -c -o _test_x11.o $XINCLUDE 2> /dev/null
+		$CC $CFLAGS _test_x11.c -c -o _test_x11.o $XINCLUDE 2> /dev/null
 
 		XLIB="-L/opt/X11/lib -lX11"
-		$CXX $CXXFLAGS _test_x11.o -o _test_x11 $XLIB 2> /dev/null
+		$CC $CFLAGS _test_x11.o -o _test_x11 $XLIB 2> /dev/null
 
 		if [ -x _test_x11 ]; then
 			XOK=1
@@ -401,87 +390,79 @@
 
 	#  Special case for some 64-bit Linux/x86_64 systems:
 	if [ z$XOK = z0 ]; then
-		$CXX $CXXFLAGS _test_x11.cc -c -o _test_x11.o $XINCLUDE 2> /dev/null
+		$CC $CFLAGS _test_x11.c -c -o _test_x11.o $XINCLUDE 2> /dev/null
 
 		XLIB="-L/usr/X11R6/lib64 -lX11"
-		$CXX $CXXFLAGS _test_x11.o -o _test_x11 $XLIB 2> /dev/null
+		$CC $CFLAGS _test_x11.o -o _test_x11 $XLIB 2> /dev/null
 
 		if [ -x _test_x11 ]; then
-			XOK=1
+			if [ 1 = `./_test_x11` ]; then
+				XOK=1
+			fi
 		fi
 	fi
 	rm -f _test_x11 _test_x11.o
 
 	if [ z$XOK = z0 ]; then
 		XINCLUDE=""
-		$CXX $CXXFLAGS _test_x11.cc -c -o _test_x11.o $XINCLUDE 2> /dev/null
+		$CC $CFLAGS _test_x11.c -c -o _test_x11.o $XINCLUDE 2> /dev/null
 
 		#  -lsocket for Solaris
 		XLIB="-lX11 -lsocket"
-		$CXX $CXXFLAGS _test_x11.o -o _test_x11 $XLIB 2> /dev/null
+		$CC $CFLAGS _test_x11.o -o _test_x11 $XLIB 2> /dev/null
 
 		if [ -x _test_x11 ]; then
-			XOK=1
+			if [ 1 = `./_test_x11` ]; then
+				XOK=1
+			fi
 		fi
 		rm -f _test_x11 _test_x11.o
 	fi
 
-	if [ z`uname` = zNetBSD ]; then
-		echo "Using NetBSD hack for X11 libs..."
-		XLIB="$XLIB -Wl,-rpath,/usr/X11R6/lib"
-	fi
-
-	if [ z`uname` = zOpenBSD ]; then
-		if [ z`uname -m` = zarc ]; then
-			echo "Using old OpenBSD/arc hack for X11 libs..."
-			XLIB="$XLIB -Wl,-rpath,/usr/X11R6/lib"
-		fi
-	fi
-
 	if [ z$XOK = z0 ]; then
 		echo "Failed to compile X11 test program." \
 		    "Configuring without X11."
 	else
-		printf "X11 headers: $XINCLUDE\n"
-		printf "X11 libraries: $XLIB\n"
+		printf "   headers:   $XINCLUDE\n"
+		printf "   libraries: $XLIB\n"
 		echo "XINCLUDE=$XINCLUDE" >> _Makefile.header
 		echo "XLIB=$XLIB" >> _Makefile.header
 		printf "#define WITH_X11\n" >> config.h
 	fi
 
-	rm -f _test_x11.cc
+	rm -f _test_x11.c
 fi
 
 
 if [ z$HPUX = zYES ]; then
-	CXXFLAGS="-D_XOPEN_SOURCE_EXTENDED $CXXFLAGS"
+	CFLAGS="-D_XOPEN_SOURCE_EXTENDED $CFLAGS"
 	printf "#define HPUX\n" >> config.h
 fi
 
 
 if [ z$OSF1 = zYES ]; then
-	CXXFLAGS="-D_XOPEN_SOURCE=500 -D_OSF_SOURCE -D_POSIX_PII_SOCKET $CXXFLAGS"
+	CFLAGS="-D_XOPEN_SOURCE=500 -D_OSF_SOURCE -D_POSIX_PII_SOCKET $CFLAGS"
 fi
 
 
 #  CWARNINGS:
 printf "checking whether -Wall can be used... "
-$CXX $CXXFLAGS _testprog.cc -o _testprog -Wall 2> /dev/null
+$CC $CFLAGS _testprog.c -o _testprog -Wall 2> /dev/null
 if [ -x _testprog ]; then
 	printf "yes\n"
 	CWARNINGS="-Wall $CWARNINGS"
 
-	if [ z"$UNSTABLE" = zYES ]; then
+	if [ z"$DEBUG" = zYES ]; then
 		printf "checking whether -Werror can be used... "
 		rm -f _testprog
-		$CXX $CWARNINGS $CXXFLAGS _testprog.cc -o _testprog -Werror 2> _testprog.err
+		$CC $CWARNINGS $CFLAGS _testprog.c -o _testprog -Werror 2> _testprog.err
 		if [ -x _testprog ]; then
 			printf "yes\n"
-#			CWARNINGS="$CWARNINGS -Werror"
+			CWARNINGS="$CWARNINGS -Werror"
 		else
 			printf "no\n"
 			
-			#printf "CXXFLAGS = $CXXFLAGS\n"
+			#printf "CFLAGS = $CFLAGS\n"
 			#cat _testprog.err
 			#printf "\n"
 		fi
@@ -494,7 +475,7 @@
 
 #  -Wstrict-aliasing
 printf "checking whether -Wstrict-aliasing can be used... "
-$CXX $CXXFLAGS -Wstrict-aliasing _testprog.cc -o _testprog 1> _testprog.stdout 2>&1
+$CC $CFLAGS -Wstrict-aliasing _testprog.c -o _testprog 1> _testprog.stdout 2>&1
 cat _testprog.stdout >> _testprog.error
 if grep strict _testprog.error > /dev/null 2>&1; then
 	printf "no\n"
@@ -509,26 +490,9 @@
 rm -f _testprog _testprog.error _testprog.stdout
 
 
-#  -Wnon-virtual-dtor
-printf "checking whether -Wnon-virtual-dtor can be used... "
-$CXX $CXXFLAGS -Wnon-virtual-dtor _testprog.cc -o _testprog 1> _testprog.stdout 2>&1
-cat _testprog.stdout >> _testprog.error
-if grep strict _testprog.error > /dev/null 2>&1; then
-	printf "no\n"
-else
-	if [ -x _testprog ]; then
-		CWARNINGS="-Wnon-virtual-dtor $CWARNINGS"
-		printf "yes\n"
-	else
-		printf "no\n"
-	fi
-fi
-rm -f _testprog _testprog.error _testprog.stdout
-
-
 #  -Wextra -Wno-unused-parameter -Wno-cast-align
 printf "checking whether -Wextra -Wno-unused-parameter -Wno-cast-align can be used... "
-$CXX $CXXFLAGS -Wextra -Wno-unused-parameter -Wno-cast-align _testprog.cc -o _testprog 1> _testprog.stdout 2>&1
+$CC $CFLAGS -Wextra -Wno-unused-parameter -Wno-cast-align _testprog.c -o _testprog 1> _testprog.stdout 2>&1
 cat _testprog.stdout >> _testprog.error
 if grep strict _testprog.error > /dev/null 2>&1; then
 	printf "no\n"
@@ -545,7 +509,7 @@
 
 #  -Wcast-align
 printf "checking whether -Wcast-align can be used... "
-$CXX $CXXFLAGS -Wcast-align _testprog.cc -o _testprog 1> _testprog.stdout 2>&1
+$CC $CFLAGS -Wcast-align _testprog.c -o _testprog 1> _testprog.stdout 2>&1
 cat _testprog.stdout >> _testprog.error
 if grep strict _testprog.error > /dev/null 2>&1; then
 	printf "no\n"
@@ -560,26 +524,9 @@
 rm -f _testprog _testprog.error _testprog.stdout
 
 
-#  -Wcast-qual
-#printf "checking whether -Wcast-qual can be used... "
-#$CXX $CXXFLAGS -Wcast-qual _testprog.cc -o _testprog 1> _testprog.stdout 2>&1
-#cat _testprog.stdout >> _testprog.error
-#if grep strict _testprog.error > /dev/null 2>&1; then
-	#printf "no\n"
-#else
-	#if [ -x _testprog ]; then
-#		CWARNINGS="-Wcast-qual $CWARNINGS"
-		#printf "yes\n"
-#	else
-		#printf "no\n"
-#	fi
-#fi
-#rm -f _testprog _testprog.error _testprog.stdout
-
-
 #  -Wshadow
 printf "checking whether -Wshadow can be used... "
-$CXX $CXXFLAGS -Wshadow _testprog.cc -o _testprog 1> _testprog.stdout 2>&1
+$CC $CFLAGS -Wshadow _testprog.c -o _testprog 1> _testprog.stdout 2>&1
 cat _testprog.stdout >> _testprog.error
 if grep strict _testprog.error > /dev/null 2>&1; then
 	printf "no\n"
@@ -596,15 +543,20 @@
 
 #  -O optimization for non-debug builds. Try -O and -O3.
 if [ ! z"$DEBUG" = zYES ]; then
-	$CXX $CXXFLAGS -O _testprog.cc -o _testprog 2> /dev/null
+	printf "checking whether -O3 or -O can be used (non-DEBUG build)... "
+	$CC $CFLAGS -O _testprog.c -o _testprog 2> /dev/null
 	if [ -x _testprog ]; then
 		rm -f _testprog
-		$CXX $CXXFLAGS -O3 _testprog.cc -o _testprog 2> /dev/null
+		$CC $CFLAGS -O3 _testprog.c -o _testprog 2> /dev/null
 		if [ -x _testprog ]; then
-			CXXFLAGS="-O3 $CXXFLAGS"
+			CFLAGS="-O3 $CFLAGS"
+			printf "yes, -O3\n"
 		else
-			CXXFLAGS="-O $CXXFLAGS"
+			CFLAGS="-O $CFLAGS"
+			printf "yes, -O\n"
 		fi
+	else
+		printf "no\n"
 	fi
 fi
 rm -f _testprog
@@ -613,13 +565,13 @@
 #  -fpeephole
 if [ ! z"$DEBUG" = zYES ]; then
 	printf "checking whether -fpeephole can be used... "
-	$CXX $CXXFLAGS -fpeephole _testprog.cc -o _testprog > _testprog.stdout 2>&1
+	$CC $CFLAGS -fpeephole _testprog.c -o _testprog > _testprog.stdout 2>&1
 	cat _testprog.stdout >> _testprog.error
 	if grep peephole _testprog.error > /dev/null 2>&1; then
 		printf "no\n"
 	else
 		if [ -x _testprog ]; then
-			CXXFLAGS="-fpeephole $CXXFLAGS"
+			CFLAGS="-fpeephole $CFLAGS"
 			printf "yes\n"
 		else
 			printf "no\n"
@@ -632,14 +584,14 @@
 #  -fomit-frame-pointer
 if [ ! z"$DEBUG" = zYES ]; then
 	printf "checking whether -fomit-frame-pointer can be used... "
-	$CXX $CXXFLAGS -fomit-frame-pointer _testprog.cc -o \
+	$CC $CFLAGS -fomit-frame-pointer _testprog.c -o \
 	    _testprog 1> _testprog.stdout 2>&1
 	cat _testprog.stdout >> _testprog.error
 	if grep frame _testprog.error > /dev/null 2>&1; then
 		printf "no\n"
 	else
 		if [ -x _testprog ]; then
-			CXXFLAGS="-fomit-frame-pointer $CXXFLAGS"
+			CFLAGS="-fomit-frame-pointer $CFLAGS"
 			printf "yes\n"
 		else
 			printf "no\n"
@@ -652,14 +604,14 @@
 #  -fstrict-aliasing
 if [ ! z"$DEBUG" = zYES ]; then
 	printf "checking whether -fstrict-aliasing can be used... "
-	$CXX $CXXFLAGS -fstrict-aliasing _testprog.cc -o \
+	$CC $CFLAGS -fstrict-aliasing _testprog.c -o \
 	    _testprog 1> _testprog.stdout 2>&1
 	cat _testprog.stdout >> _testprog.error
 	if grep strict _testprog.error > /dev/null 2>&1; then
 		printf "no\n"
 	else
 		if [ -x _testprog ]; then
-			CXXFLAGS="-fstrict-aliasing $CXXFLAGS"
+			CFLAGS="-fstrict-aliasing $CFLAGS"
 			printf "yes\n"
 		else
 			printf "no\n"
@@ -669,32 +621,13 @@
 fi
 
 
-#  -fno-rtti
-if [ ! z"$DEBUG" = zYES ]; then
-	printf "checking whether -fno-rtti can be used... "
-	$CXX $CXXFLAGS -fno-rtti _testprog.cc -o _testprog 1> _testprog.stdout 2>&1
-	cat _testprog.stdout >> _testprog.error
-	if grep rtti _testprog.error > /dev/null 2>&1; then
-		printf "no\n"
-	else
-		if [ -x _testprog ]; then
-			CXXFLAGS="-fno-rtti $CXXFLAGS"
-			printf "yes\n"
-		else
-			printf "no\n"
-		fi
-	fi
-	rm -f _testprog _testprog.error _testprog.stdout
-fi
-
-
-#  -g, for development builds
-if [ z"$UNSTABLE" = zYES ]; then
+#  -g, for debug builds
+if [ z"$DEBUG" = zYES ]; then
 	printf "checking whether -g can be used... "
-	$CXX $CXXFLAGS -g _testprog.cc -o _testprog > _testprog.stdout 2>&1
+	$CC $CFLAGS -g _testprog.c -o _testprog > _testprog.stdout 2>&1
 	cat _testprog.stdout >> _testprog.error
 	if [ -x _testprog ]; then
-		CXXFLAGS="-g $CXXFLAGS"
+		CFLAGS="-g $CFLAGS"
 		printf "yes\n"
 	else
 		printf "no\n"
@@ -706,10 +639,10 @@
 #  -lrt for nanosleep?
 printf "checking whether -lrt is required for nanosleep... "
 printf "#include <time.h>\n#include <stdio.h>
-int main(int argc, char *argv[]){nanosleep(NULL,NULL);return 0;}\n" > _testns.cc
-$CXX $CXXFLAGS _testns.cc -o _testns 2> /dev/null
+int main(int argc, char *argv[]){nanosleep(NULL,NULL);return 0;}\n" > _testns.c
+$CC $CFLAGS _testns.c -o _testns 2> /dev/null
 if [ ! -x _testns ]; then
-	$CXX $CXXFLAGS -lrt _testns.cc -o _testns 2> /dev/null
+	$CC $CFLAGS -lrt _testns.c -o _testns 2> /dev/null
 	if [ ! -x _testns ]; then
 		printf "WARNING! COULD NOT COMPILE WITH nanosleep AT ALL!\n"
 	else
@@ -720,18 +653,18 @@
 else
 	printf "no\n"
 fi
-rm -f _testns.cc _testns
+rm -f _testns.c _testns
 
 
 #  -lresolv for inet_pton?
 printf "checking whether -lresolv is required for inet_pton... "
-printf "int inet_pton(void); int main(int argc, " > _testr.cc
-printf "char *argv[]) { return inet_pton(); }\n" >> _testr.cc
-$CXX $CXXFLAGS _testr.cc -o _testr 2> /dev/null
+printf "int inet_pton(void); int main(int argc, " > _testr.c
+printf "char *argv[]) { return inet_pton(); }\n" >> _testr.c
+$CC $CFLAGS _testr.c -o _testr 2> /dev/null
 if [ ! -x _testr ]; then
-	$CXX $CXXFLAGS _testr.cc -lresolv -o _testr 2> /dev/null
+	$CC $CFLAGS _testr.c -lresolv -o _testr 2> /dev/null
 	if [ ! -x _testr ]; then
-		$CXX $CXXFLAGS _testr.cc -lresolv -lnsl -o _testr 2> /dev/null
+		$CC $CFLAGS _testr.c -lresolv -lnsl -o _testr 2> /dev/null
 		if [ ! -x _testr ]; then
 			printf "no, using inet_aton\n"
 		else
@@ -750,18 +683,18 @@
 	printf "no\n"
 	printf "#define HAVE_INET_PTON\n" >> config.h
 fi
-rm -f _testr.cc _testr.o _testr
+rm -f _testr.c _testr.o _testr
 
 
 #  -lm?
 printf "checking for math libs..."
-printf "#include <math.h>\nint main(int argc, char *argv[]) { " > _testr.cc
-printf "double x = sqrt(sin((double)argc)); return (int)x; }\n" >> _testr.cc
-$CXX $CXXFLAGS _testr.cc -o _testr 2> /dev/null
+printf "#include <math.h>\nint main(int argc, char *argv[]) { " > _testr.c
+printf "double x = sqrt(sin((double)argc)); return (int)x; }\n" >> _testr.c
+$CC $CFLAGS _testr.c -o _testr 2> /dev/null
 if [ ! -x _testr ]; then
-	$CXX $CXXFLAGS _testr.cc -lm -o _testr 2> /dev/null
+	$CC $CFLAGS _testr.c -lm -o _testr 2> /dev/null
 	if [ ! -x _testr ]; then
-		$CXX $CXXFLAGS _testr.cc -lm -lcpml -o _testr 2> /dev/null
+		$CC $CFLAGS _testr.c -lm -lcpml -o _testr 2> /dev/null
 		if [ ! -x _testr ]; then
 			printf "\nWARNING! Could not compile math test "
 			printf "at all!\nContinuing anyway.\n\n"
@@ -778,15 +711,15 @@
 else
 	printf " none needed\n"
 fi
-rm -f _testr.cc _testr.o _testr
+rm -f _testr.c _testr.o _testr
 
 
 #  strlcpy missing?
 printf "checking for strlcpy... "
 printf "#include <string.h>
 int main(int argc, char *argv[]) { char *p; char *q; size_t x;
-  x = strlcpy(p, q, 50); return 0;}\n" > _tests.cc
-$CXX $CXXFLAGS _tests.cc -o _tests 2> /dev/null
+  x = strlcpy(p, q, 50); return 0;}\n" > _tests.c
+$CC $CFLAGS _tests.c -o _tests 2> /dev/null
 if [ ! -x _tests ]; then
 	printf "missing, using mystrlcpy\n"
 	printf "#define strlcpy mystrlcpy\n" >> config.h
@@ -795,7 +728,7 @@
 else
 	printf "found\n"
 fi
-rm -f _tests.cc _tests.o _tests
+rm -f _tests.c _tests.o _tests
 
 
 #  strtoull missing?
@@ -804,15 +737,15 @@
 #include <limits.h>
 #include <stdio.h>
 int main(int argc, char *argv[]) {
-  long long x = strtoull(argv[1], NULL, 0); return 0;}\n" > _tests.cc
-$CXX $CXXFLAGS _tests.cc -o _tests 2> /dev/null
+  long long x = strtoull(argv[1], NULL, 0); return 0;}\n" > _tests.c
+$CC $CFLAGS _tests.c -o _tests 2> /dev/null
 if [ ! -x _tests ]; then
 	printf "missing, using mystrtoull\n"
 	printf "#define strtoull mystrtoull\n" >> config.h
 else
 	printf "found\n"
 fi
-rm -f _tests.cc _tests.o _tests
+rm -f _tests.c _tests.o _tests
 
 
 #  mkstemp missing?
@@ -820,15 +753,15 @@
 printf "#include <unistd.h>
 #include <stdlib.h>
 int main(int argc, char *argv[]) { int x; char y[4] = \"abc\";
-x = mkstemp(y); return 0;}\n" > _tests.cc
-$CXX $CXXFLAGS _tests.cc -o _tests 2> /dev/null
+x = mkstemp(y); return 0;}\n" > _tests.c
+$CC $CFLAGS _tests.c -o _tests 2> /dev/null
 if [ ! -x _tests ]; then
 	printf "missing, using workaround (perhaps not working properly)\n"
 	printf "#define mkstemp mymkstemp\n" >> config.h
 else
 	printf "found\n"
 fi
-rm -f _tests.cc _tests.o _tests
+rm -f _tests.c _tests.o _tests
 
 
 #  fseeko missing?
@@ -837,12 +770,12 @@
 #include <limits.h>
 #include <stdio.h>
 #include <sys/types.h>
-int main(int argc, char *argv[]) { fseeko(NULL, 0, 0); return 0;}\n" > _tests.cc
-$CXX $CXXFLAGS $CWARNINGS _tests.cc -o _tests 2> /dev/null
+int main(int argc, char *argv[]) { fseeko(NULL, 0, 0); return 0;}\n" > _tests.c
+$CC $CFLAGS $CWARNINGS _tests.c -o _tests 2> /dev/null
 if [ ! -x _tests ]; then
 	# Try with _LARGEFILE_SOURCE (hack to make fseeko
 	# work on 64-bit Linux):
-	$CXX $CXXFLAGS -D_LARGEFILE_SOURCE $CWARNINGS _tests.cc -o _tests 2> /dev/null
+	$CC $CFLAGS -D_LARGEFILE_SOURCE $CWARNINGS _tests.c -o _tests 2> /dev/null
 	if [ ! -x _tests ]; then
 		printf "missing\n"
 		printf "WARNING! fseeko missing from libc. Using a hack, "
@@ -850,12 +783,12 @@
 		printf "#define HACK_FSEEKO\n" >> config.h
 	else
 		printf "using -D_LARGEFILE_SOURCE hack\n"
-		CXXFLAGS="$CXXFLAGS -D_LARGEFILE_SOURCE"
+		CFLAGS="$CFLAGS -D_LARGEFILE_SOURCE"
 	fi
 else
 	printf "found\n"
 fi
-rm -f _tests.cc _tests.o _tests
+rm -f _tests.c _tests.o _tests
 
 
 #  socklen_t missing?
@@ -865,15 +798,15 @@
 #include <stdio.h>
 #include <sys/types.h>
 #include <sys/socket.h>
-int main(int argc, char *argv[]) { socklen_t x; return 0;}\n" > _tests.cc
-$CXX $CXXFLAGS _tests.cc -o _tests 2> /dev/null
+int main(int argc, char *argv[]) { socklen_t x; return 0;}\n" > _tests.c
+$CC $CFLAGS _tests.c -o _tests 2> /dev/null
 if [ ! -x _tests ]; then
 	printf "no, using int\n"
-	CXXFLAGS="$CXXFLAGS -Dsocklen_t=int"
+	CFLAGS="$CFLAGS -Dsocklen_t=int"
 else
 	printf "socklen_t\n"
 fi
-rm -f _tests.cc _tests.o _tests
+rm -f _tests.c _tests.o _tests
 
 
 #  MAP_ANON missing? (On some HP-UX systems? Use MAP_ANONYMOUS instead.)
@@ -882,15 +815,15 @@
 printf "#include <stdio.h>
 #include <sys/types.h>
 #include <sys/mman.h>
-int main(int argc, char *argv[]) { int x = MAP_ANON; return 0;}\n" > _tests.cc
-$CXX $CXXFLAGS _tests.cc -o _tests 2> /dev/null
+int main(int argc, char *argv[]) { int x = MAP_ANON; return 0;}\n" > _tests.c
+$CC $CFLAGS _tests.c -o _tests 2> /dev/null
 if [ ! -x _tests ]; then
 	printf "#include <stdio.h>
 #include <sys/types.h>
 #include <sys/mman.h>
 int main(int argc, char *argv[])
-{ int x = MAP_ANONYMOUS; return 0;}\n" > _tests.cc
-	$CXX $CXXFLAGS _tests.cc -o _tests 2> /dev/null
+{ int x = MAP_ANONYMOUS; return 0;}\n" > _tests.c
+	$CC $CFLAGS _tests.c -o _tests 2> /dev/null
 	if [ ! -x _tests ]; then
 		printf "no\n\n"
 		printf "WARNING! Neither MAP_ANON nor MAP_ANONYMOUS work on "
@@ -905,14 +838,14 @@
 else
 	printf "yes\n"
 fi
-rm -f _tests.cc _tests.o _tests
+rm -f _tests.c _tests.o _tests
 
 
 #  Check for PRIx64 in inttypes.h:
 printf "checking for PRIx64 in inttypes.h... "
 printf "#include <inttypes.h>\nint main(int argc, char *argv[])\n
-{\n#ifdef PRIx64\nreturn 0;\n#else\nreturn 1;\n#endif\n}\n" > _testpri.cc
-$CXX $CXXFLAGS _testpri.cc -o _testpri 2> /dev/null
+{\n#ifdef PRIx64\nreturn 0;\n#else\nreturn 1;\n#endif\n}\n" > _testpri.c
+$CC $CFLAGS _testpri.c -o _testpri 2> /dev/null
 if [ ! -x _testpri ]; then
 	printf "\nERROR! COULD NOT COMPILE PRIx64 TEST PROGRAM AT ALL!\n"
 	exit
@@ -920,28 +853,28 @@
 	if ./_testpri; then
 		printf "yes\n"
 	else
-		$CXX $CXXFLAGS -D__STDC_FORMAT_MACROS _testpri.cc -o _testpri 2> /dev/null
+		$CC $CFLAGS -D__STDC_FORMAT_MACROS _testpri.c -o _testpri 2> /dev/null
 		if [ -x _testpri ]; then
 			printf "using __STDC_FORMAT_MACROS\n"
-			CXXFLAGS="$CXXFLAGS -D__STDC_FORMAT_MACROS"
+			CFLAGS="$CFLAGS -D__STDC_FORMAT_MACROS"
 		else
 			printf "no, using an ugly hack instead, "
 			printf "#define NO_C99_PRINTF_DEFINES\n" >> config.h
 
 			# Try llx first:
 			printf "#include <stdio.h>\n#include <inttypes.h>\nint main(int argc, char *argv[]){
-			    printf(\"%%llx\\\n\", (int64_t)128);return 0;}\n" > _testpri.cc
+			    printf(\"%%llx\\\n\", (int64_t)128);return 0;}\n" > _testpri.c
 			rm -f _testpri
-			$CXX $CXXFLAGS $CWARNINGS _testpri.cc -o _testpri 2> /dev/null
+			$CC $CFLAGS $CWARNINGS _testpri.c -o _testpri 2> /dev/null
 			if [ z`./_testpri` = z80 ]; then
 				printf "PRIx64=llx\n"
 				printf "#define NO_C99_64BIT_LONGLONG\n" >> config.h
 			else
 				# Try lx too:
 				printf "#include <stdio.h>\n#include <inttypes.h>\nint main(int argc, char *argv[]){
-				    printf(\"%%lx\\\n\", (int64_t)128);return 0;}\n" > _testpri.cc
+				    printf(\"%%lx\\\n\", (int64_t)128);return 0;}\n" > _testpri.c
 				rm -f _testpri
-				$CXX $CXXFLAGS $CWARNINGS _testpri.cc -o _testpri 2> _testpri.result
+				$CC $CFLAGS $CWARNINGS _testpri.c -o _testpri 2> _testpri.result
 				if [ z`./_testpri` = z80 ]; then
 					printf "PRIx64=lx\n"
 				else
@@ -952,30 +885,30 @@
 		fi
 	fi
 fi
-rm -f _testpri.cc _testpri _testpri.result
+rm -f _testpri.c _testpri _testpri.result
 
 
 #  Check for 64-bit off_t:
 printf "checking for 64-bit off_t... "
 printf "#include <stdio.h>\n#include <inttypes.h>\n#include <sys/types.h>\n
 int main(int argc, char *argv[]){printf(\"%%i\\\n\",
- (int)sizeof(off_t));return 0;}\n" > _testoff.cc
-$CXX $CXXFLAGS _testoff.cc -o _testoff 2> /dev/null
+ (int)sizeof(off_t));return 0;}\n" > _testoff.c
+$CC $CFLAGS _testoff.c -o _testoff 2> /dev/null
 if [ ! -x _testoff ]; then
 	printf "\nWARNING! COULD NOT COMPILE off_t TEST PROGRAM AT ALL!\n"
 else
 	if [ z`./_testoff` = z8 ]; then
 		printf "yes\n"
 	else
-		$CXX $CXXFLAGS -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE \
-		    _testoff.cc -o _testoff 2> /dev/null
+		$CC $CFLAGS -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE \
+		    _testoff.c -o _testoff 2> /dev/null
 		if [ ! -x _testoff ]; then
 			printf "\nWARNING! COULD NOT COMPILE off_t TEST "
 			printf "PROGRAM!\n"
 		else
 			if [ z`./_testoff` = z8 ]; then
-				CXXFLAGS="-D_FILE_OFFSET_BITS=64 $CXXFLAGS"
-				CXXFLAGS="-D_LARGEFILE_SOURCE $CXXFLAGS"
+				CFLAGS="-D_FILE_OFFSET_BITS=64 $CFLAGS"
+				CFLAGS="-D_LARGEFILE_SOURCE $CFLAGS"
 				printf "using -D_FILE_OFFSET_BITS=64"
 				printf " -D_LARGEFILE_SOURCE\n"
 			else
@@ -986,7 +919,7 @@
 		fi
 	fi
 fi
-rm -f _testoff.cc _testoff
+rm -f _testoff.c _testoff
 
 
 #  Check for u_int8_t etc:
@@ -995,14 +928,14 @@
 printf "checking for u_int8_t... "
 printf "#include <stdio.h>\n#include <inttypes.h>\n#include <sys/types.h>\n
 int main(int argc, char *argv[]){printf(\"%%i\\\n\",
- (int)sizeof(u_int8_t));return 0;}\n" > _testuint.cc
-$CXX $CXXFLAGS _testuint.cc -o _testuint 2> /dev/null
+ (int)sizeof(u_int8_t));return 0;}\n" > _testuint.c
+$CC $CFLAGS _testuint.c -o _testuint 2> /dev/null
 if [ ! -x _testuint ]; then
 	rm -f _testuint*
 	printf "#include <stdio.h>\n#include <inttypes.h>
 	\n#include <sys/types.h>\nint main(int argc, char *argv[])
-	{printf(\"%%i\\\n\", (int)sizeof(uint8_t));return 0;}\n" > _testuint.cc
-	$CXX $CXXFLAGS _testuint.cc -o _testuint 2> /dev/null
+	{printf(\"%%i\\\n\", (int)sizeof(uint8_t));return 0;}\n" > _testuint.c
+	$CC $CFLAGS _testuint.c -o _testuint 2> /dev/null
 	if [ ! -x _testuint ]; then
 		printf "no\n\nERROR: No u_int8_t or uint8_t. Aborting\n"
 		#  TODO: Automagically detect using various combinations
@@ -1017,19 +950,19 @@
 else
 	printf "yes\n"
 fi
-rm -f _testuint.cc _testuint
+rm -f _testuint.c _testuint
 
 printf "checking for u_int64_t... "
 printf "#include <stdio.h>\n#include <inttypes.h>\n#include <sys/types.h>\n
 int main(int argc, char *argv[]){printf(\"%%i\\\n\",
- (int)sizeof(u_int64_t));return 0;}\n" > _testuint.cc
-$CXX $CXXFLAGS _testuint.cc -o _testuint 2> /dev/null
+ (int)sizeof(u_int64_t));return 0;}\n" > _testuint.c
+$CC $CFLAGS _testuint.c -o _testuint 2> /dev/null
 if [ ! -x _testuint ]; then
 	rm -f _testuint*
 	printf "#include <stdio.h>\n#include <inttypes.h>
 	\n#include <sys/types.h>\nint main(int argc, char *argv[])
-	{printf(\"%%i\\\n\", (int)sizeof(uint64_t));return 0;}\n" > _testuint.cc
-	$CXX $CXXFLAGS _testuint.cc -o _testuint 2> /dev/null
+	{printf(\"%%i\\\n\", (int)sizeof(uint64_t));return 0;}\n" > _testuint.c
+	$CC $CFLAGS _testuint.c -o _testuint 2> /dev/null
 	if [ ! -x _testuint ]; then
 		printf "no\n\nERROR: No u_int64_t or uint64_t. Aborting\n"
 		#  TODO: Automagically detect using various combinations
@@ -1044,26 +977,10 @@
 fi
 rm -f _testuint*
 
-printf "checking for __FUNCTION__... "
-printf "#include <stdio.h>\n\nint main(int argc, char *argv[]) {
-  if (__FUNCTION__) printf(__FUNCTION__);\n  return 0;\n}\n" > _testfunction.cc
-$CXX $CXXFLAGS _testfunction.cc -o _testfunction 2> /dev/null
-if [ ! -x _testfunction ]; then
-	printf "no\n"
-else
-	if [ z`./_testfunction` = zmain ]; then
-		printf "yes\n"
-		printf "#define HAVE___FUNCTION__\n" >> config.h
-	else
-		printf "no\n"
-	fi
-fi
-rm -f _testfunction*
-
 printf "checking for __builtin_expect... "
 printf "#include <stdio.h>\n\nint main(int argc, char *argv[]) {
-  if (__builtin_expect(!!(2), 1)) return 0;\n  return 1;\n}\n" > _testexpect.cc
-$CXX $CXXFLAGS _testexpect.cc -o _testexpect 2> /dev/null
+  if (__builtin_expect(!!(2), 1)) return 0;\n  return 1;\n}\n" > _testexpect.c
+$CC $CFLAGS _testexpect.c -o _testexpect 2> /dev/null
 if [ ! -x _testexpect ]; then
 	printf "no\n"
 	printf "#define likely(x) (x)\n" >> config.h
@@ -1085,8 +1002,8 @@
 int main(int argc, char *argv[])
 {  int x = 1; void *xp = (void *)&x; char *p = (char *)xp;
 if (*p) printf("little\\\n"); else printf("big\\\n"); }
-' > _test_end.cc
-$CXX $CXXFLAGS _test_end.cc -o _test_end 2> /dev/null
+' > _test_end.c
+$CC $CFLAGS _test_end.c -o _test_end 2> /dev/null
 X=`./_test_end`
 echo $X
 if [ z$X = zlittle ]; then
@@ -1104,36 +1021,6 @@
 
 ###############################################################################
 
-printf "checking for Doxygen... "
-
-if (doxygen --version); then
-	# Version is printed, if found.
-	DOXYGEN=doxygen
-else
-	# Not found is already printed, if doxygen is not found.
-	DOXYGEN="\#"
-fi
-
-
-###############################################################################
-
-printf "checking for valgrind... "
-
-if [ z$DISABLEVALGRIND = zYES ]; then
-	echo skipped
-else
-	if (valgrind --version); then
-		# Version is printed, if found.
-		VALGRIND="valgrind -q --log-file=tmp_valgrind.out"
-	else
-		# Not found is already printed, if valgrind is not found.
-		VALGRIND=""
-	fi
-fi
-
-
-###############################################################################
-
 if [ "z$PREFIX" = z ]; then
 	PREFIX="$DEFAULTPREFIX"
 fi
@@ -1163,85 +1050,31 @@
 
 rm -f _testprog.c*
 
-echo C++ compiler flags: $CXXFLAGS $CWARNINGS
+echo C compiler flags: $CFLAGS $CWARNINGS
 echo Linker flags: $OTHERLIBS
 if [ z"$DESTDIR" != z ]; then
 	echo "Destination dir: $DESTDIR"
 fi
 echo "CWARNINGS=$CWARNINGS" >> _Makefile.header
-echo "COPTIM=$CXXFLAGS" >> _Makefile.header
+echo "COPTIM=$CFLAGS" >> _Makefile.header
 echo "INCLUDE=$INCLUDE" >> _Makefile.header
 echo "DINCLUDE=$DINCLUDE" >> _Makefile.header
 echo "INCLUDE2=$INCLUDE2" >> _Makefile.header
-echo "CXX=$CXX" >> _Makefile.header
+echo "CC=$CC" >> _Makefile.header
 echo "OTHERLIBS=$OTHERLIBS" >> _Makefile.header
 echo "CPU_ARCHS=$CPU_ARCHS" >> _Makefile.header
 echo "CPU_TOOLS=$CPU_TOOLS" >> _Makefile.header
-echo "DOXYGEN=$DOXYGEN" >> _Makefile.header
-echo "VALGRIND=$VALGRIND" >> _Makefile.header
 echo "PREFIX=$PREFIX" >> _Makefile.header
 echo "MANDIR=$MANDIR" >> _Makefile.header
 echo "DESTDIR=$DESTDIR" >> _Makefile.header
 echo "" >> _Makefile.header
 
-#  Create list of unit testable classes:
-rm -f unittest.h unittest_h.h
-printf "// DO NOT EDIT. Automagically generated by the configure script.\n" >> unittest.h
-printf "// DO NOT EDIT. Automagically generated by the configure script.\n" >> unittest_h.h
-printf "// Will be removed by  make clean_all\n\n" >> unittest.h
-printf "// Will be removed by  make clean_all\n\n" >> unittest_h.h
-for a in `find src -name "*.cc" -print`; do grep UNITTESTS\( "$a";
-	done | cut -d \( -f 2|cut -d \) -f 1 > _unittests.tmp
-for a in `cat _unittests.tmp`; do
-	if [ ! z$a = zclassName ]; then
-		cd src/include
-		HNAME=`find . -name $a.h | cut -c 3-`
-		cd ../..
-		printf "#include \"$HNAME\"\n" >> unittest_h.h
-		printf "\t$a::RunUnitTests(nSucceeded, nFailed);\n" >> unittest.h
-	fi
-done
-rm -f _unittests.tmp
-
-#  Create a list of Commands:
-rm -f commands_h.h commands.h
-printf "// DO NOT EDIT. Automagically generated by the configure script.\n" >> commands.h
-printf "// DO NOT EDIT. Automagically generated by the configure script.\n" >> commands_h.h
-printf "// Will be removed by  make clean_all\n\n" >> commands.h
-printf "// Will be removed by  make clean_all\n\n" >> commands_h.h
-for a in src/main/commands/*.cc; do echo $a|cut -d / -f 4-; done > _commands.tmp
-for a in `cat _commands.tmp`; do
-	CNAME=`echo $a|cut -d . -f 1`
-	printf "#include \"commands/$CNAME.h\"\n" >> commands_h.h
-	printf "\tAddCommand(new $CNAME);\n" >> commands.h
-done
-rm -f _commands.tmp
-
-#  Create a list of Components:
-rm -f components.h components_h.h
-printf "// DO NOT EDIT. Automagically generated by the configure script.\n" >> components.h
-printf "// DO NOT EDIT. Automagically generated by the configure script.\n" >> components_h.h
-printf "// Will be removed by  make clean_all\n\n" >> components.h
-printf "// Will be removed by  make clean_all\n\n" >> components_h.h
-grep COMPONENT\( src/include/components/*.h|cut -d \( -f 2|cut -d \) -f 1 > _components.tmp
-cd src/include/components
-for a in `cat ../../../_components.tmp`; do
-	CNAME=`grep COMPONENT\($a\) *.h|cut -d . -f 1`
-	printf "#include \"components/$CNAME.h\"\n" >> ../../../components_h.h
-	printf "\t{ \"$a\", $CNAME::Create, $CNAME::GetAttribute },\n" >> ../../../components.h
-done
-cd ../../..
-rm -f _components.tmp
-
 #  Create the Makefiles:
-D=". src src/components src/components/busses src/components/cpu"
-D="$D src/components/machines src/components/memory src/components/special"
-D="$D src/console src/cpus src/debugger src/devices src/old_main"
-D="$D src/devices/fonts src/disk src/file src/include src/machines src/main"
-D="$D src/main/commands src/main/fileloaders src/net"
-D="$D src/promemul src/symbol src/ui src/ui/console src/ui/nullui"
+D=". src src/console src/cpus src/debugger src/devices src/core"
+D="$D src/devices/fonts src/disk src/file src/include src/machines"
+D="$D src/net src/promemul src/symbol"
+echo "creating Makefiles..."
 for a in $D; do
-	echo "creating $a/Makefile"
 	touch $a/Makefile
 	cat _Makefile.header > $a/Makefile
 	cat $a/Makefile.skel >> $a/Makefile
@@ -1256,5 +1089,5 @@
 #  Remove temporary Makefile header, etc.:
 rm -f _Makefile.header _test*
 
-echo Configured. You may now run make to build gxemul.
+echo Configured. You may now run ' make ' to build gxemul.
 
diff -Nru gxemul-0.6.2/debian/changelog gxemul-0.7.0+dfsg/debian/changelog
--- gxemul-0.6.2/debian/changelog	2020-08-25 19:25:06.000000000 +0000
+++ gxemul-0.7.0+dfsg/debian/changelog	2021-11-27 12:34:13.000000000 +0000
@@ -1,3 +1,22 @@
+gxemul (0.7.0+dfsg-1) unstable; urgency=medium
+
+  * New upstream version
+  * debian/gbp.conf: Fix upstream-tag template
+  * debian/control: Update the list of supported systems
+  * debian/copyright: Update to reflect upstream changes
+  * debian/control: Mark gxemul as Multi-Arch: foreign
+  * debian/rules: Remove --disable-valgrind flag; no longer exists
+  * debian/rules: Sprinkle reproducible dust on the config
+  * debian/patches/remove_defines: Upstream patch for a build failure
+  * debian/rules: Remove -rpath flag after configuration
+  * debian/copyright: Exclude test/FileLoader*; trivial but missing source
+  * debian/watch: Add +dfsg on the repacked source
+  * debian/rules: Remove useless fiddling with CFLAGS
+  * debian/control: Remove unused doxygen build-dep
+  * debian/rules: Support cross-compilation
+
+ -- Göran Weinholt <weinholt@debian.org>  Sat, 27 Nov 2021 13:34:13 +0100
+
 gxemul (0.6.2-2) unstable; urgency=medium
 
   [ Debian Janitor ]
diff -Nru gxemul-0.6.2/debian/control gxemul-0.7.0+dfsg/debian/control
--- gxemul-0.6.2/debian/control	2020-08-25 19:23:57.000000000 +0000
+++ gxemul-0.7.0+dfsg/debian/control	2021-11-27 11:59:16.000000000 +0000
@@ -2,7 +2,7 @@
 Section: misc
 Priority: optional
 Maintainer: Göran Weinholt <weinholt@debian.org>
-Build-Depends: debhelper-compat (= 11), libx11-dev, doxygen
+Build-Depends: debhelper-compat (= 11), libx11-dev
 Standards-Version: 4.5.0
 Homepage: http://gavare.se/gxemul/
 Vcs-Browser: https://salsa.debian.org/debian/gxemul
@@ -19,28 +19,31 @@
  system:
  .
  ARM-based machines:
-  * CATS (NetBSD/cats, OpenBSD/cats)
+  * CATS (NetBSD/cats, OpenBSD/cats, Debian GNU/Linux)
   * IQ80321 (NetBSD/evbarm)
   * NetWinder (NetBSD/netwinder)
+  * Raspberry Pi (NetBSD/raspberrypi, FreeBSD, HelenOS/rpi)
  MIPS-based machines:
-  * DECstation 5000/200 (NetBSD/pmax, OpenBSD/pmax, Ultrix,
-    Linux/DECstation, Sprite)
-  * Acer Pica-61 (NetBSD/arc)
-  * NEC MobilePro 770, 780, 800, 880 (NetBSD/hpcmips)
+  * Acer Pica-61 (NetBSD/arc, Windows NT)
+  * Algorithmics P5064 (NetBSD/algor)
   * Cobalt (NetBSD/cobalt)
+  * DECstation 5000/200 (NetBSD/pmax, OpenBSD/pmax, Ultrix,
+    Linux/DECstation, Sprite), DECstation 5000/1xx (raw PROM)
   * Malta (NetBSD/evbmips, Linux/Malta)
-  * Algorithmics P5064 (NetBSD/algor)
-  * SGI O2 (aka IP32) (NetBSD/sgi)
+  * NEC MobilePro 770, 780, 800, 880 (NetBSD/hpcmips)
+  * PlayStation 2 (NetBSD/playstation2)
+  * SGI O2 (NetBSD/sgimips, OpenBSD/sgi, Linux, IRIX, raw PROM)
+  * VoCore (FreeBSD/vocore, Linux/vocore)
  Motorola 88K-based machines:
-  * Motorola MVME187 (OpenBSD/mvme88k)
   * Luna 88K (OpenBSD/luna88k)
+  * Motorola MVME187 (OpenBSD/mvme88k)
  PowerPC-based machines:
-  * IBM 6050/6070 (PReP, PowerPC Reference Platform) (NetBSD/prep)
-  * MacPPC (generic "G4" Macintosh) (NetBSD/macppc)
   * Artesyn PM/PPC (NetBSD/pmppc)
+  * IBM 6050/6070 (PReP, PowerPC Reference Platform) (NetBSD/prep)
+  * MacPPC (NetBSD/macppc, HelenOS/ppc)
  SuperH-based machines:
+  * Landisk I-O DATA USL-5P (NetBSD/landisk, OpenBSD/landisk)
   * Sega Dreamcast (NetBSD/dreamcast, Linux/dreamcast)
-  * Landisk I-O DATA USL-5P (OpenBSD/landisk)
  .
  Other machine types and architectures are emulated less completely.
  See the documentation in the gxemul-doc package for the exact details
@@ -50,6 +53,7 @@
 Section: doc
 Architecture: all
 Depends: ${misc:Depends}
+Multi-Arch: foreign
 Description: gxemul documentation
  This package contains the documentation for gxemul, the machine
  emulator for multiple architectures. Among other things, instructions
diff -Nru gxemul-0.6.2/debian/copyright gxemul-0.7.0+dfsg/debian/copyright
--- gxemul-0.6.2/debian/copyright	2019-06-24 14:06:54.000000000 +0000
+++ gxemul-0.7.0+dfsg/debian/copyright	2021-11-27 09:42:41.000000000 +0000
@@ -2,9 +2,10 @@
 Upstream-Name: GXemul
 Upstream-Contact: Anders Gavare <gavare@gmail.com>
 Source: http://gavare.se/gxemul/
+Files-Excluded: test/FileLoader*
 
 Files: *
-Copyright: 2003-2019 Anders Gavare <gavare@gmail.com>
+Copyright: 2003-2021, Anders Gavare <gavare@gmail.com>
 License: BSD-3-clause
 
 Files: demos/*
@@ -17,22 +18,25 @@
  you can reuse the code even in projects which have licenses that are
  incompatible with the BSD-style licenses used for GXemul itself.
 
-Files: doc/Doxyfile
-       doc/doxygen.css
-Copyright: 1997-2015, Dimitri van Heesch
-Comment: License extracted from the doxygen package
-License: GPL with doxygen exception
- Permission to use, copy, modify, and distribute this software and its
- documentation under the terms of the GNU General Public License is hereby
- granted. No representations are made about the suitability of this software
- for any purpose. It is provided "as is" without express or implied warranty.
- See the GNU General Public License for more details.
- .
- Documents produced by Doxygen are derivative works derived from the
- input used in their production; they are not affected by this license.
- .
- On Debian systems, the complete text of the GNU General Public
- License can be found in '/usr/share/common-licenses/GPL-2'.
+Files: src/net/net_tap.c
+Copyright: 2020, Jason R. Thorpe
+License: BSD-3-clause
+
+Files: src/net/net_ether.c
+Copyright: 2020, Jason R. Thorpe
+           1982-1993, The Regents of the University of California
+License: BSD-3-clause
+
+Files: src/include/thirdparty/bootblock.h
+Copyright: 2002-2004, The NetBSD Foundation, Inc.
+           1993, Allen K. Briggs
+           1993, Chris P. Caputo,
+           1993, Michael L. Finch
+           1993, Bradley A. Grantham
+           1993, Lawrence A. Kesteloot
+           1994-1999, Christopher G. Demetriou
+           1994, Rolf Grossmann
+License: BSD-2-clause and BSD-4-clause
 
 Files: src/include/thirdparty/crmfbreg.h
        src/include/thirdparty/impactsr-bsd.h
@@ -42,7 +46,7 @@
        src/include/thirdparty/mvme_memcreg.h
        src/include/thirdparty/sh4_pcicreg.h
 Copyright: 2007, Jared D. McNeill <jmcneill@invisible.ca>
-           1997, 1998, 2001, The NetBSD Foundation, Inc.
+           1997-2001, The NetBSD Foundation, Inc.
            1997, Manuel Bouyer
            2008, Michael Lorenz <macallan@netbsd.org>
            2005, NONAKA Kimihiro
@@ -83,6 +87,13 @@
            1990, William Jolitz
 License: BSD-3-clause
 
+Files: src/include/thirdparty/mb89352reg.h
+Copyright: 1990-1993, The Regents of the University of California
+           1996-1999, The NetBSD Foundation, Inc.
+           1996-1998, NetBSD/pc98 porting staff
+           1996-1998, Kouichi Matsuda
+License: BSD-3-clause and BSD-2-clause
+
 Files: src/include/thirdparty/adb_viareg.h
        src/include/thirdparty/algor_p5064reg.h
        src/include/thirdparty/arm_cputypes.h
@@ -358,13 +369,6 @@
            2004, Miodrag Vallat.
 License: BSD-2-clause and cmu
 
-Files: src/include/thirdparty/debug_new.h
-       src/include/thirdparty/fast_mutex.h
-       src/include/thirdparty/static_assert.h
-       src/main/debug_new.cc
-Copyright: 2004-2005, Wu Yongwei <adah@users.sourceforge.net>
-License: Zlib
-
 Files: src/include/thirdparty/dc7085.h
        src/include/thirdparty/dec_prom.h
        src/include/thirdparty/lk201.h
@@ -392,7 +396,7 @@
 Copyright: 2003-2009, Anders Gavare
 License: BSD-2-clause
 
-Files: src/promemul/dreamcast_scramble.cc
+Files: src/promemul/dreamcast_scramble.c
 Copyright: Marcus Comstedt
 License: public-domain
  The sofware in this section is in the Public Domain. This means that
@@ -423,7 +427,7 @@
  | Yes, scramble.c is also in the public domain.
 
 Files: debian/*
-Copyright: 2004-2019, Göran Weinholt <weinholt@debian.org>
+Copyright: 2004-2021, Göran Weinholt <weinholt@debian.org>
            2008-2010 Jonathan Wiltshire <debian@jwiltshire.org.uk>
 License: BSD-3-clause
 Comment: No explicit license historically; assuming 'LICENSE' applies
diff -Nru gxemul-0.6.2/debian/gbp.conf gxemul-0.7.0+dfsg/debian/gbp.conf
--- gxemul-0.6.2/debian/gbp.conf	2018-12-07 19:49:06.000000000 +0000
+++ gxemul-0.7.0+dfsg/debian/gbp.conf	2021-11-27 09:42:41.000000000 +0000
@@ -1,7 +1,7 @@
 [DEFAULT]
 pristine-tar = True
 debian-branch = debian
-upstream-tag = 'v%(version)s'
+upstream-tag = v%(version)s
 
 [buildpackage]
 upstream-branch = upstream
diff -Nru gxemul-0.6.2/debian/patches/remove_defines gxemul-0.7.0+dfsg/debian/patches/remove_defines
--- gxemul-0.6.2/debian/patches/remove_defines	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/debian/patches/remove_defines	2021-11-27 09:42:41.000000000 +0000
@@ -0,0 +1,116 @@
+From: =?utf-8?q?G=C3=B6ran_Weinholt?= <goran@weinholt.se>
+Date: Wed, 24 Nov 2021 20:57:00 +0100
+Subject: Upstream: "Removing weird defines,
+ hopefully enabling build on Linux."
+
+---
+ doc/TODO.html                        |  4 ----
+ src/include/thirdparty/bootblock.h   | 11 -----------
+ src/include/thirdparty/dp83932reg.h  | 11 -----------
+ src/include/thirdparty/pcireg.h      | 11 -----------
+ src/include/thirdparty/sgi_arcbios.h | 11 -----------
+ 5 files changed, 48 deletions(-)
+
+diff --git a/doc/TODO.html b/doc/TODO.html
+index da69628..25a34c8 100644
+--- a/doc/TODO.html
++++ b/doc/TODO.html
+@@ -49,10 +49,6 @@ implement in GXemul. Some items in this list are perhaps already fixed.
+ 		e.g. verbosity disk debug		<-- print all messages, but
+ 		     breakpoint subsystem disk warn	<-- break only for warn and error.
+ 
+-<font color="blue">Build problems:</font>
+-	o) Building a default build on my Linux machine currently fails with duplicate definitions from
+-		Linux' bits/socket.h being "extern inlined" twice? (configure --debug works fine though)
+-
+ <font color="blue">Misc.:</font>
+ 	o) Try X11 grabbing with multiple host displays? ssh with X11 forwarding from laptop?
+ 		with multiple mouse pointers, _which_ mouse pointer is grabbed?
+diff --git a/src/include/thirdparty/bootblock.h b/src/include/thirdparty/bootblock.h
+index cf70798..cc2bf7a 100644
+--- a/src/include/thirdparty/bootblock.h
++++ b/src/include/thirdparty/bootblock.h
+@@ -121,17 +121,6 @@
+ #ifndef _SYS_BOOTBLOCK_H
+ #define	_SYS_BOOTBLOCK_H
+ 
+-#ifdef __attribute__
+-#undef __attribute__
+-#endif
+-
+-#ifdef __noreturn__
+-#undef __noreturn__
+-#endif
+-
+-#define __attribute__(x)  /*  */
+-#define __noreturn__  /*  */
+-
+ #if !defined(__ASSEMBLER__)
+ #if defined(_KERNEL) || defined(_STANDALONE)
+ #include <sys/stdint.h>
+diff --git a/src/include/thirdparty/dp83932reg.h b/src/include/thirdparty/dp83932reg.h
+index 06d9298..ed2f6e0 100644
+--- a/src/include/thirdparty/dp83932reg.h
++++ b/src/include/thirdparty/dp83932reg.h
+@@ -4,17 +4,6 @@
+ #ifndef _DEV_IC_DP83932REG_H_
+ #define	_DEV_IC_DP83932REG_H_
+ 
+-#ifdef __attribute__
+-#undef __attribute__
+-#endif
+-
+-#ifdef __noreturn__
+-#undef __noreturn__
+-#endif
+-
+-#define __attribute__(x)  /*  */
+-#define __noreturn__  /*  */
+-
+ /*-
+  * Copyright (c) 2001 The NetBSD Foundation, Inc.
+  * All rights reserved.
+diff --git a/src/include/thirdparty/pcireg.h b/src/include/thirdparty/pcireg.h
+index 162a516..1c2007e 100644
+--- a/src/include/thirdparty/pcireg.h
++++ b/src/include/thirdparty/pcireg.h
+@@ -4,17 +4,6 @@
+ #ifndef _DEV_PCI_PCIREG_H_
+ #define	_DEV_PCI_PCIREG_H_
+ 
+-#ifdef __attribute__
+-#undef __attribute__
+-#endif
+-
+-#ifdef __noreturn__
+-#undef __noreturn__
+-#endif
+-
+-#define __attribute__(x)  /*  */
+-#define __noreturn__  /*  */
+-
+ /*
+  * Copyright (c) 1995, 1996, 1999, 2000
+  *     Christopher G. Demetriou.  All rights reserved.
+diff --git a/src/include/thirdparty/sgi_arcbios.h b/src/include/thirdparty/sgi_arcbios.h
+index ccd4df3..51f3e38 100644
+--- a/src/include/thirdparty/sgi_arcbios.h
++++ b/src/include/thirdparty/sgi_arcbios.h
+@@ -6,17 +6,6 @@
+ 
+ /*  It's better to not #define sgimips here, and assume generic ARC instead  */
+ 
+-#ifdef __attribute__
+-#undef __attribute__
+-#endif
+-
+-#ifdef __noreturn__
+-#undef __noreturn__
+-#endif
+-
+-#define	__attribute__(x)  /*  */
+-#define	__noreturn__  /*  */
+-
+ /*	$NetBSD: arcbios.h,v 1.3 2001/12/06 14:59:02 rafal Exp $	*/
+ 
+ /*-
diff -Nru gxemul-0.6.2/debian/patches/series gxemul-0.7.0+dfsg/debian/patches/series
--- gxemul-0.6.2/debian/patches/series	2018-12-07 19:50:49.000000000 +0000
+++ gxemul-0.7.0+dfsg/debian/patches/series	2021-11-27 09:42:41.000000000 +0000
@@ -0,0 +1 @@
+remove_defines
diff -Nru gxemul-0.6.2/debian/rules gxemul-0.7.0+dfsg/debian/rules
--- gxemul-0.6.2/debian/rules	2019-06-24 20:22:50.000000000 +0000
+++ gxemul-0.7.0+dfsg/debian/rules	2021-11-27 12:15:24.000000000 +0000
@@ -1,18 +1,26 @@
 #!/usr/bin/make -f
 # debian/rules for gxemul.
+include /usr/share/dpkg/architecture.mk
+include /usr/share/dpkg/pkg-info.mk
 
-#export DH_VERBOSE=1
-
-CFLAGS = -g
-
-ifneq (,$(findstring noopt,$(DEB_BUILD_OPTIONS)))
-  CFLAGS += -O0
+ifeq ($(origin CC),default)
+CC := $(DEB_HOST_GNU_TYPE)-gcc
 endif
 
 override_dh_auto_configure:
-	CFLAGS="${CFLAGS}" PREFIX="/usr" DESTDIR=$(shell pwd)/debian/tmp ./configure --disable-valgrind
+	CFLAGS="${CFLAGS}" PREFIX="/usr" DESTDIR=$(shell pwd)/debian/tmp ./configure
+	sed -e 's/#define VERSION.*/#define VERSION \"$(DEB_VERSION_UPSTREAM)\"/g' \
+	    -e 's/#define COMPILE_DATE.*/#define COMPILE_DATE "compiled by Debian"/' \
+	    -i config.h
+	sed -e 's/-Wl,-rpath,[^\w]*//g' -i Makefile
 	touch configure-stamp
 
+override_dh_auto_build:
+	make -C src/include
+	make -C src/devices/fonts Xconv_raw_to_c
+	make -C src/cpus generate_head generate_tail $(shell awk '/^CPU_TOOLS/{$$1="";print}' src/cpus/Makefile)
+	dh_auto_build -- CC="${CC}"
+
 override_dh_install:
 	dh_install
 	rm -rf debian/gxemul/usr/share/doc/gxemul/*
diff -Nru gxemul-0.6.2/debian/watch gxemul-0.7.0+dfsg/debian/watch
--- gxemul-0.6.2/debian/watch	2018-12-07 17:45:39.000000000 +0000
+++ gxemul-0.7.0+dfsg/debian/watch	2021-11-27 10:06:31.000000000 +0000
@@ -1,2 +1,3 @@
-version=3
-http://gavare.se/gxemul/src/gxemul-(\d+\..+)\.tar\.gz
+version=4
+opts=dversionmangle=auto,repacksuffix=+dfsg \
+  http://gavare.se/gxemul/src/gxemul-(\d+\..+)\.tar\.gz
Binary files /tmp/tmpaarp4e17/pWfV7dXnD4/gxemul-0.6.2/doc/20190715-sgi-o2-linux.png and /tmp/tmpaarp4e17/9kW3MclFqY/gxemul-0.7.0+dfsg/doc/20190715-sgi-o2-linux.png differ
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Binary files /tmp/tmpaarp4e17/pWfV7dXnD4/gxemul-0.6.2/doc/20210328-openbsd-luna88k-inside-openbsd-luna88k.png and /tmp/tmpaarp4e17/9kW3MclFqY/gxemul-0.7.0+dfsg/doc/20210328-openbsd-luna88k-inside-openbsd-luna88k.png differ
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diff -Nru gxemul-0.6.2/doc/components/component_cache.html gxemul-0.7.0+dfsg/doc/components/component_cache.html
--- gxemul-0.6.2/doc/components/component_cache.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/components/component_cache.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,34 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html>
-<head>
-  <title>GXemul: Components: cache</title>
-  <meta name="robots" content="noarchive,nofollow,noindex">
-</head>
-<body style="font-family : sans-serif;">
-
-<!-- 10 lines header.  -->
-
-<h1>GXemul: Components: <tt>cache</tt></h1>
-<p>
-
-<a href="../">Back to the index.</a>
-<p><a href="../components.html">Back to the component index.</a>
-
-
-<p><br><h2><tt>cache</tt> component</h2>
-
-The <tt>cache</tt> component represents a memory cache. Caches are usually
-connected to CPUs, between the CPU and main memory.
-
-<p>TODO.
-
-
-<p>Source code for this component can be found
-<a href="../doxygen/html/CacheComponent_8cc_source.html">here</a>
-(and Doxygen documentation
-<a href="../doxygen/html/classCacheComponent.html">here</a>).
-
-<p><br><hr>
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/components/component_cpu.html gxemul-0.7.0+dfsg/doc/components/component_cpu.html
--- gxemul-0.6.2/doc/components/component_cpu.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/components/component_cpu.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,37 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html>
-<head>
-  <title>GXemul: Components: cpu</title>
-  <meta name="robots" content="noarchive,nofollow,noindex">
-</head>
-<body style="font-family : sans-serif;">
-
-<!-- 10 lines header.  -->
-
-<h1>GXemul: Components: <tt>cpu</tt></h1>
-<p>
-
-<a href="../">Back to the index.</a>
-<p><a href="../components.html">Back to the component index.</a>
-
-
-<p><br><h2><tt>cpu</tt> component</h2>
-
-This is a base class for CPU components.
-
-<p>Examples of CPUs include:
-<ul>
-	<li><a href="component_i960_cpu.html"><tt>i960_cpu</tt></a>
-	<li><a href="component_m88k_cpu.html"><tt>m88k_cpu</tt></a>
-	<li><a href="component_mips_cpu.html"><tt>mips_cpu</tt></a>
-</ul>
-
-<p>Source code for this component can be found
-<a href="../doxygen/html/CPUComponent_8cc_source.html">here</a>
-(and Doxygen documentation
-<a href="../doxygen/html/classCPUComponent.html">here</a>).
-
-<p><br><hr>
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/components/component_dummy.html gxemul-0.7.0+dfsg/doc/components/component_dummy.html
--- gxemul-0.6.2/doc/components/component_dummy.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/components/component_dummy.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,32 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html>
-<head>
-  <title>GXemul: Components: dummy</title>
-  <meta name="robots" content="noarchive,nofollow,noindex">
-</head>
-<body style="font-family : sans-serif;">
-
-<!-- 10 lines header.  -->
-
-<h1>GXemul: Components: <tt>dummy</tt></h1>
-<p>
-
-<a href="../">Back to the index.</a>
-<p><a href="../components.html">Back to the component index.</a>
-
-
-<p><br><h2><tt>dummy</tt> component</h2>
-
-The <tt>dummy</tt> component does not do anything. It can contain
-any other components. It is also used for the emulator's internal
-unit tests.
-
-
-<p>
-Source code documentation for this component can be found
-<a href="../doxygen/html/classDummyComponent.html">here</a>.
-
-<p><br><hr>
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/components/component_i960_cpu.html gxemul-0.7.0+dfsg/doc/components/component_i960_cpu.html
--- gxemul-0.6.2/doc/components/component_i960_cpu.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/components/component_i960_cpu.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,51 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html>
-<head>
-  <title>GXemul: Components: i960_cpu</title>
-  <meta name="robots" content="noarchive,nofollow,noindex">
-</head>
-<body style="font-family : sans-serif;">
-
-<!-- 10 lines header.  -->
-
-<h1>GXemul: Components: <tt>i960_cpu</tt></h1>
-<p>
-
-<a href="../">Back to the index.</a>
-<p><a href="../components.html">Back to the component index.</a>
-
-
-<p><br><h2><tt>i960_cpu</tt> component</h2>
-
-This component represents an
-<a href="https://en.wikipedia.org/wiki/Intel_i960">Intel i960</a>-like 
-<a href="component_cpu.html">CPU component</a>.
-
-<p>Things that have been implemented:
-
-<ul>
-	<li>i960 Cx disassembly.
-</ul>
-
-<p>Things that have <b>not yet</b> been implemented: TODOs in approximate priority order:
-
-<ul>
-	<li>Disassembly of instructions for variants other than i960 CA / CF.
-	<li>Implement register dump functionality better (specifics about
-		SFRs, AC/PC/TC flags etc).
-	<li>b.out file loader: symbol support. (Not in the CPU component but related.)
-	<li>ECOFF file loader. (Not in the CPU component but related.)
-	<li>Start implementing execution of instructions.
-	<li>Implement some kind of "short diff" format for execution,
-		rather than the verbose format of today.
-</ul>
-
-
-<p>
-Source code documentation for this component can be found
-<a href="../doxygen/html/classI960__CPUComponent.html">here</a>.
-
-<p><br><hr>
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/components/component_m88k_cpu.html gxemul-0.7.0+dfsg/doc/components/component_m88k_cpu.html
--- gxemul-0.6.2/doc/components/component_m88k_cpu.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/components/component_m88k_cpu.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,40 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html>
-<head>
-  <title>GXemul: Components: m88k_cpu</title>
-  <meta name="robots" content="noarchive,nofollow,noindex">
-</head>
-<body style="font-family : sans-serif;">
-
-<!-- 10 lines header.  -->
-
-<h1>GXemul: Components: <tt>m88k_cpu</tt></h1>
-<p>
-
-<a href="../">Back to the index.</a>
-<p><a href="../components.html">Back to the component index.</a>
-
-
-<p><br><h2><tt>m88k_cpu</tt> component</h2>
-
-This component represents a
-<a href="http://en.wikipedia.org/wiki/Motorola_88000">Motorola 88000</a>-like 
-<a href="component_cpu.html">CPU component</a>.
-
-<p>Features that have been implemented:
-
-<ul>
-	<li>88100 disassembly.
-</ul>
-
-<p>TODO: Almost everything.
-
-
-<p>
-Source code documentation for this component can be found
-<a href="../doxygen/html/classM88K__CPUComponent.html">here</a>.
-
-<p><br><hr>
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/components/component_mainbus.html gxemul-0.7.0+dfsg/doc/components/component_mainbus.html
--- gxemul-0.6.2/doc/components/component_mainbus.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/components/component_mainbus.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,32 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html>
-<head>
-  <title>GXemul: Components: mainbus</title>
-  <meta name="robots" content="noarchive,nofollow,noindex">
-</head>
-<body style="font-family : sans-serif;">
-
-<!-- 10 lines header.  -->
-
-<h1>GXemul: Components: <tt>mainbus</tt></h1>
-<p>
-
-<a href="../">Back to the index.</a>
-<p><a href="../components.html">Back to the component index.</a>
-
-
-<p><br><h2><tt>mainbus</tt> component</h2>
-
-The <tt>mainbus</tt> component forwards address/data requests from
-e.g. <a href="component_cpu.html">CPUs</a> to memory mapped components.
-A typical example of a memory mapped component is <a href="component_ram.html">RAM</a>.
-
-<p>Source code for this component can be found
-<a href="../doxygen/html/MainbusComponent_8cc_source.html">here</a>
-(and Doxygen documentation
-<a href="../doxygen/html/classMainbusComponent.html">here</a>).
-
-<p><br><hr>
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/components/component_ram.html gxemul-0.7.0+dfsg/doc/components/component_ram.html
--- gxemul-0.6.2/doc/components/component_ram.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/components/component_ram.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,71 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html>
-<head>
-  <title>GXemul: Components: ram</title>
-  <meta name="robots" content="noarchive,nofollow,noindex">
-</head>
-<body style="font-family : sans-serif;">
-
-<!-- 10 lines header.  -->
-
-<h1>GXemul: Components: <tt>ram</tt></h1>
-<p>
-
-<a href="../">Back to the index.</a>
-<p><a href="../components.html">Back to the component index.</a>
-
-
-<p><br><h2><tt>ram</tt> component</h2>
-
-The <tt>ram</tt> component represents a Random Access Memory.
-
-<p>Note that also ROM (Read-Only Memory) circuits are emulated using this
-component. A ROM circuit is a RAM with <tt>writeProtect = true</tt>.
-
-<p>The following example shows how to interactively add a <tt>ram</tt>
-component to a machine:
-
-<pre>
-$ <b>gxemul -V</b>
-..
-GXemul> <b>add machine</b>
-GXemul> <b>add mainbus machine0</b>
-GXemul> <b>root</b>
-  root
-  \-- machine0
-      \-- mainbus0
-
-  accuracy = cycle
-  step     = 0
-GXemul> <b>add ram mainbus0</b>
-GXemul> <b>ram</b>
-  ram0  (0 bytes at offset 0)
-
-  data                = (custom)
-  lastDumpAddr        = 0
-  memoryMappedAddrMul = 0x1
-  memoryMappedBase    = 0
-  memoryMappedSize    = 0
-  step                = 0
-  writeProtect        = false
-GXemul> <b>ram0.memoryMappedSize = 0x400000</b>
-GXemul> <b>root</b>
-  root
-  \-- machine0
-      \-- mainbus0
-          \-- ram0  (4 MB at offset 0)
-
-  accuracy = cycle
-  step     = 0
-GXemul> 
-</pre>
-
-<p>Source code for this component can be found
-<a href="../doxygen/html/RAMComponent_8cc_source.html">here</a>
-(and Doxygen documentation
-<a href="../doxygen/html/classRAMComponent.html">here</a>).
-
-<p><br><hr>
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/configfiles.html gxemul-0.7.0+dfsg/doc/configfiles.html
--- gxemul-0.6.2/doc/configfiles.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/configfiles.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -71,6 +71,16 @@
 	are not supported on the command line.
 </ol>
 
+<p>
+Note that from a performance perspective, it is best to just have one
+machine per configuration file, and run several GXemul instances concurrently
+(with one machine per instance). The two advantages to having more than one
+machine in a single configuration file are:
+<ul>
+	<li>the network <tt>net ( )</tt> is trivially shared between the
+		specified machines, and
+	<li>breaking into the debugger will freeze all machines simultaneously.
+</ul>
 
 
 
diff -Nru gxemul-0.6.2/doc/debugging.html gxemul-0.7.0+dfsg/doc/debugging.html
--- gxemul-0.6.2/doc/debugging.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/debugging.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -71,7 +71,7 @@
 you should start by downloading the program used in the examples. It is an 
 OpenBSD kernel for LUNA 88K:
 
-<p><a href="https://ftp.eu.openbsd.org/pub/OpenBSD/6.2/luna88k/bsd.rd">https://ftp.eu.openbsd.org/pub/OpenBSD/6.2/luna88k/bsd.rd</a>.
+<p><a href="https://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/bsd.rd">https://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/bsd.rd</a>.
 
 <p>You can run <tt>file bsd.rd</tt> to check that it is of a reasonable executable file format.
 
@@ -93,10 +93,20 @@
 $ <b>gxemul -e luna-88k bsd.rd</b>
 </pre>
 
-<p>This will start the emulator, start running the kernel, and, for this particular OpenBSD kernel (at least
-at the time of writing this text), exit at the end, because the
-emulator does not fully support running that kernel on that emulated machine type. But it is
-enough to demonstrate the various commands that you can use.
+<p>This will start the emulator, start running the kernel, and stop after
+printing
+<pre>
+	Welcome to the OpenBSD/luna88k 6.8 installation program.
+	(I)nstall, (U)pgrade, (A)utoinstall or (S)hell?
+</pre>
+
+<p>Type CTRL-C to break into GXemul's command prompt. Type <tt>quit</tt>
+whenever you wish to quit from GXemul.
+<pre>
+GXemul> <b>quit</b>
+</pre>
+
+<p>(If instead you wish to send a CTRL-C to the emulated system, type CTRL-B.)
 
 <p>You really need to know what machine type you want to emulate. The emulator cannot simply load a binary
 without having a machine to load it into. There are some machine types called "testXXXX" or "bareXXXX"
@@ -104,11 +114,11 @@
 but these do not correspond to any real world machine.
 
 <p>The next very useful command line switch, when using the emulator as a debugger, is <tt>-V</tt>. This causes
-the emulator to start in a <i>paused state</i>, showing a <tt>GXemul&gt;</tt> prompt where commands can be entered.
+the emulator to start in a <i>paused state</i>, showing the command prompt.
 
 <pre>
 $ <b>gxemul -V -e luna-88k bsd.rd</b>
-GXemul (unknown version)    Copyright (C) 2003-2019  Anders Gavare
+GXemul (unknown version)    Copyright (C) 2003-2021  Anders Gavare
 Read the source code and/or documentation for other Copyright messages.
 
 Simple setup...
@@ -223,6 +233,28 @@
 
 <p>You can modify registers by typing commands such as <tt>r8 = r31 + 0x1234</tt>.
 
+<p><tt>reg</tt> takes a CPU id and coprocessor number as optional arguments.
+To view the system registers of the 88K CPU, type:
+
+<pre>
+GXemul> <b>reg ,0</b>
+cpu0:   PID=0x00000007   PSR=0x80000002  EPSR=0x00000000  SSBR=0x00000000
+cpu0:  SXIP=0x00000000  SNIP=0x00000000  SFIP=0x00000000   VBR=0x00000000
+cpu0:  DMT0=0x00000000  DMD0=0x00000000  DMA0=0x00000000  DMT1=0x00000000
+cpu0:  DMD1=0x00000000  DMA1=0x00000000  DMT2=0x00000000  DMD2=0x00000000
+cpu0:  DMA2=0x00000000   SR0=0x00000000   SR1=0x00000000   SR2=0x00000000
+cpu0:   SR3=0x00000000  CR21=0x00000000  CR22=0x00000000  CR23=0x00000000
+cpu0:  CR24=0x00000000  CR25=0x00000000  CR26=0x00000000  CR27=0x00000000
+cpu0:  CR28=0x00000000  CR29=0x00000000  CR30=0x00000000  CR31=0x00000000
+</pre>
+
+<p><tt>reg,</tt> (without any number) is a convenient shorthand for showing
+the system registers (<tt>reg ,0</tt>).
+
+<p><tt>reg ,1</tt> shows the floating point control registers.
+
+<p><tt>tlbdump</tt> dumps the CPUs TLB registers, if there are any.
+
 
 
 
@@ -314,7 +346,7 @@
 
 <pre>
 $ <b>gxemul -V -e luna-88k bsd.rd</b>
-GXemul (unknown version)    Copyright (C) 2003-2019  Anders Gavare
+GXemul (unknown version)    Copyright (C) 2003-2021  Anders Gavare
 ...
 
 GXemul> <b>breakpoint add bcopy</b>
diff -Nru gxemul-0.6.2/doc/Doxyfile gxemul-0.7.0+dfsg/doc/Doxyfile
--- gxemul-0.6.2/doc/Doxyfile	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/Doxyfile	1970-01-01 00:00:00.000000000 +0000
@@ -1,1278 +0,0 @@
-# Doxyfile 1.5.2
-
-# This file describes the settings to be used by the documentation system
-# doxygen (www.doxygen.org) for a project
-#
-# All text after a hash (#) is considered a comment and will be ignored
-# The format is:
-#       TAG = value [value, ...]
-# For lists items can also be appended using:
-#       TAG += value [value, ...]
-# Values that contain spaces should be placed between quotes (" ")
-
-#---------------------------------------------------------------------------
-# Project related configuration options
-#---------------------------------------------------------------------------
-
-# This tag specifies the encoding used for all characters in the config file that 
-# follow. The default is UTF-8 which is also the encoding used for all text before 
-# the first occurrence of this tag. Doxygen uses libiconv (or the iconv built into 
-# libc) for the transcoding. See http://www.gnu.org/software/libiconv for the list of 
-# possible encodings.
-
-DOXYFILE_ENCODING      = UTF-8
-
-# The PROJECT_NAME tag is a single word (or a sequence of words surrounded 
-# by quotes) that should identify the project.
-
-PROJECT_NAME           = GXemul
-
-# The PROJECT_NUMBER tag can be used to enter a project or revision number. 
-# This could be handy for archiving the generated documentation or 
-# if some version control system is used.
-
-PROJECT_NUMBER         = 
-
-# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) 
-# base path where the generated documentation will be put. 
-# If a relative path is entered, it will be relative to the location 
-# where doxygen was started. If left blank the current directory will be used.
-
-OUTPUT_DIRECTORY       = doc/doxygen
-
-# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 
-# 4096 sub-directories (in 2 levels) under the output directory of each output 
-# format and will distribute the generated files over these directories. 
-# Enabling this option can be useful when feeding doxygen a huge amount of 
-# source files, where putting all generated files in the same directory would 
-# otherwise cause performance problems for the file system.
-
-CREATE_SUBDIRS         = NO
-
-# The OUTPUT_LANGUAGE tag is used to specify the language in which all 
-# documentation generated by doxygen is written. Doxygen will use this 
-# information to generate all constant output in the proper language. 
-# The default language is English, other supported languages are: 
-# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, 
-# Croatian, Czech, Danish, Dutch, Finnish, French, German, Greek, Hungarian, 
-# Italian, Japanese, Japanese-en (Japanese with English messages), Korean, 
-# Korean-en, Lithuanian, Norwegian, Polish, Portuguese, Romanian, Russian, 
-# Serbian, Slovak, Slovene, Spanish, Swedish, and Ukrainian.
-
-OUTPUT_LANGUAGE        = English
-
-# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will 
-# include brief member descriptions after the members that are listed in 
-# the file and class documentation (similar to JavaDoc). 
-# Set to NO to disable this.
-
-BRIEF_MEMBER_DESC      = YES
-
-# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend 
-# the brief description of a member or function before the detailed description. 
-# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the 
-# brief descriptions will be completely suppressed.
-
-REPEAT_BRIEF           = YES
-
-# This tag implements a quasi-intelligent brief description abbreviator 
-# that is used to form the text in various listings. Each string 
-# in this list, if found as the leading text of the brief description, will be 
-# stripped from the text and the result after processing the whole list, is 
-# used as the annotated text. Otherwise, the brief description is used as-is. 
-# If left blank, the following values are used ("$name" is automatically 
-# replaced with the name of the entity): "The $name class" "The $name widget" 
-# "The $name file" "is" "provides" "specifies" "contains" 
-# "represents" "a" "an" "the"
-
-ABBREVIATE_BRIEF       = 
-
-# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then 
-# Doxygen will generate a detailed section even if there is only a brief 
-# description.
-
-ALWAYS_DETAILED_SEC    = NO
-
-# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all 
-# inherited members of a class in the documentation of that class as if those 
-# members were ordinary class members. Constructors, destructors and assignment 
-# operators of the base classes will not be shown.
-
-INLINE_INHERITED_MEMB  = NO
-
-# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full 
-# path before files name in the file list and in the header files. If set 
-# to NO the shortest path that makes the file name unique will be used.
-
-#FULL_PATH_NAMES        = YES
-FULL_PATH_NAMES        = NO
-
-# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag 
-# can be used to strip a user-defined part of the path. Stripping is 
-# only done if one of the specified strings matches the left-hand part of 
-# the path. The tag can be used to show relative paths in the file list. 
-# If left blank the directory from which doxygen is run is used as the 
-# path to strip.
-
-STRIP_FROM_PATH        = 
-
-# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of 
-# the path mentioned in the documentation of a class, which tells 
-# the reader which header file to include in order to use a class. 
-# If left blank only the name of the header file containing the class 
-# definition is used. Otherwise one should specify the include paths that 
-# are normally passed to the compiler using the -I flag.
-
-STRIP_FROM_INC_PATH    = 
-
-# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter 
-# (but less readable) file names. This can be useful is your file systems 
-# doesn't support long names like on DOS, Mac, or CD-ROM.
-
-SHORT_NAMES            = NO
-
-# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen 
-# will interpret the first line (until the first dot) of a JavaDoc-style 
-# comment as the brief description. If set to NO, the JavaDoc 
-# comments will behave just like the Qt-style comments (thus requiring an 
-# explicit @brief command for a brief description.
-
-JAVADOC_AUTOBRIEF      = NO
-
-# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen 
-# treat a multi-line C++ special comment block (i.e. a block of //! or /// 
-# comments) as a brief description. This used to be the default behaviour. 
-# The new default is to treat a multi-line C++ comment block as a detailed 
-# description. Set this tag to YES if you prefer the old behaviour instead.
-
-MULTILINE_CPP_IS_BRIEF = NO
-
-# If the DETAILS_AT_TOP tag is set to YES then Doxygen 
-# will output the detailed description near the top, like JavaDoc.
-# If set to NO, the detailed description appears after the member 
-# documentation.
-
-#DETAILS_AT_TOP         = NO
-
-# Hm :(  Apparently this has become obsolete
-#DETAILS_AT_TOP         = YES
-
-# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented 
-# member inherits the documentation from any documented member that it 
-# re-implements.
-
-INHERIT_DOCS           = YES
-
-# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce 
-# a new page for each member. If set to NO, the documentation of a member will 
-# be part of the file/class/namespace that contains it.
-
-SEPARATE_MEMBER_PAGES  = NO
-
-# The TAB_SIZE tag can be used to set the number of spaces in a tab. 
-# Doxygen uses this value to replace tabs by spaces in code fragments.
-
-TAB_SIZE               = 8
-
-# This tag can be used to specify a number of aliases that acts 
-# as commands in the documentation. An alias has the form "name=value". 
-# For example adding "sideeffect=\par Side Effects:\n" will allow you to 
-# put the command \sideeffect (or @sideeffect) in the documentation, which 
-# will result in a user-defined paragraph with heading "Side Effects:". 
-# You can put \n's in the value part of an alias to insert newlines.
-
-ALIASES                = 
-
-# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C 
-# sources only. Doxygen will then generate output that is more tailored for C. 
-# For instance, some of the names that are used will be different. The list 
-# of all members will be omitted, etc.
-
-OPTIMIZE_OUTPUT_FOR_C  = NO
-
-# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java 
-# sources only. Doxygen will then generate output that is more tailored for Java. 
-# For instance, namespaces will be presented as packages, qualified scopes 
-# will look different, etc.
-
-OPTIMIZE_OUTPUT_JAVA   = NO
-
-# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want to 
-# include (a tag file for) the STL sources as input, then you should 
-# set this tag to YES in order to let doxygen match functions declarations and 
-# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. 
-# func(std::string) {}). This also make the inheritance and collaboration 
-# diagrams that involve STL classes more complete and accurate.
-
-#BUILTIN_STL_SUPPORT    = NO
-BUILTIN_STL_SUPPORT    = YES
-
-# If you use Microsoft's C++/CLI language, you should set this option to YES to
-# enable parsing support.
-
-CPP_CLI_SUPPORT        = NO
-
-# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC 
-# tag is set to YES, then doxygen will reuse the documentation of the first 
-# member in the group (if any) for the other members of the group. By default 
-# all members of a group must be documented explicitly.
-
-DISTRIBUTE_GROUP_DOC   = NO
-
-# Set the SUBGROUPING tag to YES (the default) to allow class member groups of 
-# the same type (for instance a group of public functions) to be put as a 
-# subgroup of that type (e.g. under the Public Functions section). Set it to 
-# NO to prevent subgrouping. Alternatively, this can be done per class using 
-# the \nosubgrouping command.
-
-SUBGROUPING            = YES
-
-#---------------------------------------------------------------------------
-# Build related configuration options
-#---------------------------------------------------------------------------
-
-# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in 
-# documentation are documented, even if no documentation was available. 
-# Private class members and static file members will be hidden unless 
-# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
-
-#EXTRACT_ALL            = NO
-EXTRACT_ALL            = YES
-
-# If the EXTRACT_PRIVATE tag is set to YES all private members of a class 
-# will be included in the documentation.
-
-EXTRACT_PRIVATE        = NO
-
-# If the EXTRACT_STATIC tag is set to YES all static members of a file 
-# will be included in the documentation.
-
-EXTRACT_STATIC         = NO
-
-# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) 
-# defined locally in source files will be included in the documentation. 
-# If set to NO only classes defined in header files are included.
-
-EXTRACT_LOCAL_CLASSES  = YES
-
-# This flag is only useful for Objective-C code. When set to YES local 
-# methods, which are defined in the implementation section but not in 
-# the interface are included in the documentation. 
-# If set to NO (the default) only methods in the interface are included.
-
-EXTRACT_LOCAL_METHODS  = NO
-
-# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all 
-# undocumented members of documented classes, files or namespaces. 
-# If set to NO (the default) these members will be included in the 
-# various overviews, but no documentation section is generated. 
-# This option has no effect if EXTRACT_ALL is enabled.
-
-HIDE_UNDOC_MEMBERS     = NO
-
-# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all 
-# undocumented classes that are normally visible in the class hierarchy. 
-# If set to NO (the default) these classes will be included in the various 
-# overviews. This option has no effect if EXTRACT_ALL is enabled.
-
-HIDE_UNDOC_CLASSES     = NO
-
-# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all 
-# friend (class|struct|union) declarations. 
-# If set to NO (the default) these declarations will be included in the 
-# documentation.
-
-HIDE_FRIEND_COMPOUNDS  = NO
-
-# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any 
-# documentation blocks found inside the body of a function. 
-# If set to NO (the default) these blocks will be appended to the 
-# function's detailed documentation block.
-
-HIDE_IN_BODY_DOCS      = NO
-
-# The INTERNAL_DOCS tag determines if documentation 
-# that is typed after a \internal command is included. If the tag is set 
-# to NO (the default) then the documentation will be excluded. 
-# Set it to YES to include the internal documentation.
-
-INTERNAL_DOCS          = NO
-
-# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate 
-# file names in lower-case letters. If set to YES upper-case letters are also 
-# allowed. This is useful if you have classes or files whose names only differ 
-# in case and if your file system supports case sensitive file names. Windows 
-# and Mac users are advised to set this option to NO.
-
-CASE_SENSE_NAMES       = YES
-
-# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen 
-# will show members with their full class and namespace scopes in the 
-# documentation. If set to YES the scope will be hidden.
-
-HIDE_SCOPE_NAMES       = NO
-
-# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen 
-# will put a list of the files that are included by a file in the documentation 
-# of that file.
-
-SHOW_INCLUDE_FILES     = YES
-
-# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] 
-# is inserted in the documentation for inline members.
-
-INLINE_INFO            = YES
-
-# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen 
-# will sort the (detailed) documentation of file and class members 
-# alphabetically by member name. If set to NO the members will appear in 
-# declaration order.
-
-SORT_MEMBER_DOCS       = YES
-
-# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the 
-# brief documentation of file, namespace and class members alphabetically 
-# by member name. If set to NO (the default) the members will appear in 
-# declaration order.
-
-SORT_BRIEF_DOCS        = NO
-
-# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be 
-# sorted by fully-qualified names, including namespaces. If set to 
-# NO (the default), the class list will be sorted only by class name, 
-# not including the namespace part. 
-# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
-# Note: This option applies only to the class list, not to the 
-# alphabetical list.
-
-SORT_BY_SCOPE_NAME     = NO
-
-# The GENERATE_TODOLIST tag can be used to enable (YES) or 
-# disable (NO) the todo list. This list is created by putting \todo 
-# commands in the documentation.
-
-GENERATE_TODOLIST      = YES
-
-# The GENERATE_TESTLIST tag can be used to enable (YES) or 
-# disable (NO) the test list. This list is created by putting \test 
-# commands in the documentation.
-
-GENERATE_TESTLIST      = YES
-
-# The GENERATE_BUGLIST tag can be used to enable (YES) or 
-# disable (NO) the bug list. This list is created by putting \bug 
-# commands in the documentation.
-
-GENERATE_BUGLIST       = YES
-
-# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or 
-# disable (NO) the deprecated list. This list is created by putting 
-# \deprecated commands in the documentation.
-
-GENERATE_DEPRECATEDLIST= YES
-
-# The ENABLED_SECTIONS tag can be used to enable conditional 
-# documentation sections, marked by \if sectionname ... \endif.
-
-ENABLED_SECTIONS       = 
-
-# The MAX_INITIALIZER_LINES tag determines the maximum number of lines 
-# the initial value of a variable or define consists of for it to appear in 
-# the documentation. If the initializer consists of more lines than specified 
-# here it will be hidden. Use a value of 0 to hide initializers completely. 
-# The appearance of the initializer of individual variables and defines in the 
-# documentation can be controlled using \showinitializer or \hideinitializer 
-# command in the documentation regardless of this setting.
-
-#MAX_INITIALIZER_LINES  = 30
-MAX_INITIALIZER_LINES  = 300
-
-# Set the SHOW_USED_FILES tag to NO to disable the list of files generated 
-# at the bottom of the documentation of classes and structs. If set to YES the 
-# list will mention the files that were used to generate the documentation.
-
-SHOW_USED_FILES        = YES
-
-# If the sources in your project are distributed over multiple directories 
-# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy 
-# in the documentation. The default is NO.
-
-#SHOW_DIRECTORIES       = NO
-SHOW_DIRECTORIES       = YES
-
-# The FILE_VERSION_FILTER tag can be used to specify a program or script that 
-# doxygen should invoke to get the current version for each file (typically from the 
-# version control system). Doxygen will invoke the program by executing (via 
-# popen()) the command <command> <input-file>, where <command> is the value of 
-# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file 
-# provided by doxygen. Whatever the program writes to standard output 
-# is used as the file version. See the manual for examples.
-
-FILE_VERSION_FILTER    = 
-
-#---------------------------------------------------------------------------
-# configuration options related to warning and progress messages
-#---------------------------------------------------------------------------
-
-# The QUIET tag can be used to turn on/off the messages that are generated 
-# by doxygen. Possible values are YES and NO. If left blank NO is used.
-
-#QUIET                  = NO
-QUIET                  = YES
-
-# The WARNINGS tag can be used to turn on/off the warning messages that are 
-# generated by doxygen. Possible values are YES and NO. If left blank 
-# NO is used.
-
-WARNINGS               = YES
-
-# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings 
-# for undocumented members. If EXTRACT_ALL is set to YES then this flag will 
-# automatically be disabled.
-
-WARN_IF_UNDOCUMENTED   = YES
-
-# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for 
-# potential errors in the documentation, such as not documenting some 
-# parameters in a documented function, or documenting parameters that 
-# don't exist or using markup commands wrongly.
-
-WARN_IF_DOC_ERROR      = YES
-
-# This WARN_NO_PARAMDOC option can be abled to get warnings for 
-# functions that are documented, but have no documentation for their parameters 
-# or return value. If set to NO (the default) doxygen will only warn about 
-# wrong or incomplete parameter documentation, but not about the absence of 
-# documentation.
-
-WARN_NO_PARAMDOC       = NO
-
-# The WARN_FORMAT tag determines the format of the warning messages that 
-# doxygen can produce. The string should contain the $file, $line, and $text 
-# tags, which will be replaced by the file and line number from which the 
-# warning originated and the warning text. Optionally the format may contain 
-# $version, which will be replaced by the version of the file (if it could 
-# be obtained via FILE_VERSION_FILTER)
-
-WARN_FORMAT            = "$file:$line: $text"
-
-# The WARN_LOGFILE tag can be used to specify a file to which warning 
-# and error messages should be written. If left blank the output is written 
-# to stderr.
-
-WARN_LOGFILE           = 
-
-#---------------------------------------------------------------------------
-# configuration options related to the input files
-#---------------------------------------------------------------------------
-
-# The INPUT tag can be used to specify the files and/or directories that contain 
-# documented source files. You may enter file names like "myfile.cpp" or 
-# directories like "/usr/src/myproject". Separate the files or directories 
-# with spaces.
-
-#INPUT                  = 
-INPUT                  = src
-
-# This tag can be used to specify the character encoding of the source files that 
-# doxygen parses. Internally doxygen uses the UTF-8 encoding, which is also the default 
-# input encoding. Doxygen uses libiconv (or the iconv built into libc) for the transcoding. 
-# See http://www.gnu.org/software/libiconv for the list of possible encodings.
-
-INPUT_ENCODING         = UTF-8
-
-# If the value of the INPUT tag contains directories, you can use the 
-# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp 
-# and *.h) to filter out the source-files in the directories. If left 
-# blank the following patterns are tested: 
-# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx 
-# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py
-
-FILE_PATTERNS          = 
-
-# The RECURSIVE tag can be used to turn specify whether or not subdirectories 
-# should be searched for input files as well. Possible values are YES and NO. 
-# If left blank NO is used.
-
-#RECURSIVE              = NO
-RECURSIVE              = YES
-
-# The EXCLUDE tag can be used to specify files and/or directories that should 
-# excluded from the INPUT source files. This way you can easily exclude a 
-# subdirectory from a directory tree whose root is specified with the INPUT tag.
-
-EXCLUDE                = .svn
-
-# The EXCLUDE_SYMLINKS tag can be used select whether or not files or 
-# directories that are symbolic links (a Unix filesystem feature) are excluded 
-# from the input.
-
-EXCLUDE_SYMLINKS       = NO
-
-# If the value of the INPUT tag contains directories, you can use the 
-# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude 
-# certain files from those directories. Note that the wildcards are matched 
-# against the file with absolute path, so to exclude all test directories 
-# for example use the pattern */test/*
-
-EXCLUDE_PATTERNS       = 
-
-# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names 
-# (namespaces, classes, functions, etc.) that should be excluded from the output. 
-# The symbol name can be a fully qualified name, a word, or if the wildcard * is used, 
-# a substring. Examples: ANamespace, AClass, AClass::ANamespace, ANamespace::*Test
-
-EXCLUDE_SYMBOLS        = 
-
-# The EXAMPLE_PATH tag can be used to specify one or more files or 
-# directories that contain example code fragments that are included (see 
-# the \include command).
-
-EXAMPLE_PATH           = 
-
-# If the value of the EXAMPLE_PATH tag contains directories, you can use the 
-# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp 
-# and *.h) to filter out the source-files in the directories. If left 
-# blank all files are included.
-
-EXAMPLE_PATTERNS       = 
-
-# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be 
-# searched for input files to be used with the \include or \dontinclude 
-# commands irrespective of the value of the RECURSIVE tag. 
-# Possible values are YES and NO. If left blank NO is used.
-
-EXAMPLE_RECURSIVE      = NO
-
-# The IMAGE_PATH tag can be used to specify one or more files or 
-# directories that contain image that are included in the documentation (see 
-# the \image command).
-
-IMAGE_PATH             = 
-
-# The INPUT_FILTER tag can be used to specify a program that doxygen should 
-# invoke to filter for each input file. Doxygen will invoke the filter program 
-# by executing (via popen()) the command <filter> <input-file>, where <filter> 
-# is the value of the INPUT_FILTER tag, and <input-file> is the name of an 
-# input file. Doxygen will then use the output that the filter program writes 
-# to standard output.  If FILTER_PATTERNS is specified, this tag will be 
-# ignored.
-
-INPUT_FILTER           = 
-
-# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern 
-# basis.  Doxygen will compare the file name with each pattern and apply the 
-# filter if there is a match.  The filters are a list of the form: 
-# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further 
-# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER 
-# is applied to all files.
-
-FILTER_PATTERNS        = 
-
-# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using 
-# INPUT_FILTER) will be used to filter the input files when producing source 
-# files to browse (i.e. when SOURCE_BROWSER is set to YES).
-
-FILTER_SOURCE_FILES    = NO
-
-#---------------------------------------------------------------------------
-# configuration options related to source browsing
-#---------------------------------------------------------------------------
-
-# If the SOURCE_BROWSER tag is set to YES then a list of source files will 
-# be generated. Documented entities will be cross-referenced with these sources. 
-# Note: To get rid of all source code in the generated output, make sure also 
-# VERBATIM_HEADERS is set to NO.
-
-#SOURCE_BROWSER         = NO
-SOURCE_BROWSER         = YES
-
-# Setting the INLINE_SOURCES tag to YES will include the body 
-# of functions and classes directly in the documentation.
-
-INLINE_SOURCES         = NO
-
-# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct 
-# doxygen to hide any special comment blocks from generated source code 
-# fragments. Normal C and C++ comments will always remain visible.
-
-#STRIP_CODE_COMMENTS    = YES
-STRIP_CODE_COMMENTS    = NO
-
-# If the REFERENCED_BY_RELATION tag is set to YES (the default) 
-# then for each documented function all documented 
-# functions referencing it will be listed.
-
-REFERENCED_BY_RELATION = YES
-
-# If the REFERENCES_RELATION tag is set to YES (the default) 
-# then for each documented function all documented entities 
-# called/used by that function will be listed.
-
-REFERENCES_RELATION    = YES
-
-# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
-# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
-# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
-# link to the source code.  Otherwise they will link to the documentstion.
-
-REFERENCES_LINK_SOURCE = YES
-
-# If the USE_HTAGS tag is set to YES then the references to source code 
-# will point to the HTML generated by the htags(1) tool instead of doxygen 
-# built-in source browser. The htags tool is part of GNU's global source 
-# tagging system (see http://www.gnu.org/software/global/global.html). You 
-# will need version 4.8.6 or higher.
-
-USE_HTAGS              = NO
-
-# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen 
-# will generate a verbatim copy of the header file for each class for 
-# which an include is specified. Set to NO to disable this.
-
-VERBATIM_HEADERS       = YES
-
-#---------------------------------------------------------------------------
-# configuration options related to the alphabetical class index
-#---------------------------------------------------------------------------
-
-# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index 
-# of all compounds will be generated. Enable this if the project 
-# contains a lot of classes, structs, unions or interfaces.
-
-ALPHABETICAL_INDEX     = NO
-
-# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then 
-# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns 
-# in which this list will be split (can be a number in the range [1..20])
-
-COLS_IN_ALPHA_INDEX    = 5
-
-# In case all classes in a project start with a common prefix, all 
-# classes will be put under the same header in the alphabetical index. 
-# The IGNORE_PREFIX tag can be used to specify one or more prefixes that 
-# should be ignored while generating the index headers.
-
-IGNORE_PREFIX          = 
-
-#---------------------------------------------------------------------------
-# configuration options related to the HTML output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_HTML tag is set to YES (the default) Doxygen will 
-# generate HTML output.
-
-GENERATE_HTML          = YES
-
-# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. 
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be 
-# put in front of it. If left blank `html' will be used as the default path.
-
-HTML_OUTPUT            = html
-
-# The HTML_FILE_EXTENSION tag can be used to specify the file extension for 
-# each generated HTML page (for example: .htm,.php,.asp). If it is left blank 
-# doxygen will generate files with .html extension.
-
-HTML_FILE_EXTENSION    = .html
-
-# The HTML_HEADER tag can be used to specify a personal HTML header for 
-# each generated HTML page. If it is left blank doxygen will generate a 
-# standard header.
-
-#HTML_HEADER            = 
-HTML_HEADER            = doc/doxygen_headerFile.html
-
-# The HTML_FOOTER tag can be used to specify a personal HTML footer for 
-# each generated HTML page. If it is left blank doxygen will generate a 
-# standard footer.
-
-#HTML_FOOTER            = 
-HTML_FOOTER            = doc/doxygen_footerFile.html
-
-# The HTML_STYLESHEET tag can be used to specify a user-defined cascading 
-# style sheet that is used by each HTML page. It can be used to 
-# fine-tune the look of the HTML output. If the tag is left blank doxygen 
-# will generate a default style sheet. Note that doxygen will try to copy 
-# the style sheet file to the HTML output directory, so don't put your own 
-# stylesheet in the HTML output directory as well, or it will be erased!
-
-#HTML_STYLESHEET        = 
-HTML_STYLESHEET        = doc/doxygen.css
-
-# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, 
-# files or namespaces will be aligned in HTML using tables. If set to 
-# NO a bullet list will be used.
-
-HTML_ALIGN_MEMBERS     = YES
-
-# If the GENERATE_HTMLHELP tag is set to YES, additional index files 
-# will be generated that can be used as input for tools like the 
-# Microsoft HTML help workshop to generate a compressed HTML help file (.chm) 
-# of the generated HTML documentation.
-
-GENERATE_HTMLHELP      = NO
-
-# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can 
-# be used to specify the file name of the resulting .chm file. You 
-# can add a path in front of the file if the result should not be 
-# written to the html output directory.
-
-CHM_FILE               = 
-
-# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can 
-# be used to specify the location (absolute path including file name) of 
-# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run 
-# the HTML help compiler on the generated index.hhp.
-
-HHC_LOCATION           = 
-
-# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag 
-# controls if a separate .chi index file is generated (YES) or that 
-# it should be included in the master .chm file (NO).
-
-GENERATE_CHI           = NO
-
-# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag 
-# controls whether a binary table of contents is generated (YES) or a 
-# normal table of contents (NO) in the .chm file.
-
-BINARY_TOC             = NO
-
-# The TOC_EXPAND flag can be set to YES to add extra items for group members 
-# to the contents of the HTML help documentation and to the tree view.
-
-TOC_EXPAND             = NO
-
-# The DISABLE_INDEX tag can be used to turn on/off the condensed index at 
-# top of each HTML page. The value NO (the default) enables the index and 
-# the value YES disables it.
-
-DISABLE_INDEX          = NO
-
-# This tag can be used to set the number of enum values (range [1..20]) 
-# that doxygen will group on one line in the generated HTML documentation.
-
-ENUM_VALUES_PER_LINE   = 4
-
-# If the GENERATE_TREEVIEW tag is set to YES, a side panel will be
-# generated containing a tree-like index structure (just like the one that 
-# is generated for HTML Help). For this to work a browser that supports 
-# JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+, 
-# Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are 
-# probably better off using the HTML help feature.
-
-GENERATE_TREEVIEW      = NO
-#GENERATE_TREEVIEW      = YES
-
-# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be 
-# used to set the initial width (in pixels) of the frame in which the tree 
-# is shown.
-
-TREEVIEW_WIDTH         = 250
-
-#---------------------------------------------------------------------------
-# configuration options related to the LaTeX output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will 
-# generate Latex output.
-
-#GENERATE_LATEX         = YES
-GENERATE_LATEX         = NO
-
-# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. 
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be 
-# put in front of it. If left blank `latex' will be used as the default path.
-
-LATEX_OUTPUT           = latex
-
-# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be 
-# invoked. If left blank `latex' will be used as the default command name.
-
-LATEX_CMD_NAME         = latex
-
-# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to 
-# generate index for LaTeX. If left blank `makeindex' will be used as the 
-# default command name.
-
-MAKEINDEX_CMD_NAME     = makeindex
-
-# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact 
-# LaTeX documents. This may be useful for small projects and may help to 
-# save some trees in general.
-
-COMPACT_LATEX          = NO
-
-# The PAPER_TYPE tag can be used to set the paper type that is used 
-# by the printer. Possible values are: a4, a4wide, letter, legal and 
-# executive. If left blank a4wide will be used.
-
-PAPER_TYPE             = a4wide
-
-# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX 
-# packages that should be included in the LaTeX output.
-
-EXTRA_PACKAGES         = 
-
-# The LATEX_HEADER tag can be used to specify a personal LaTeX header for 
-# the generated latex document. The header should contain everything until 
-# the first chapter. If it is left blank doxygen will generate a 
-# standard header. Notice: only use this tag if you know what you are doing!
-
-LATEX_HEADER           = 
-
-# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated 
-# is prepared for conversion to pdf (using ps2pdf). The pdf file will 
-# contain links (just like the HTML output) instead of page references 
-# This makes the output suitable for online browsing using a pdf viewer.
-
-PDF_HYPERLINKS         = NO
-
-# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of 
-# plain latex in the generated Makefile. Set this option to YES to get a 
-# higher quality PDF documentation.
-
-USE_PDFLATEX           = NO
-
-# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. 
-# command to the generated LaTeX files. This will instruct LaTeX to keep 
-# running if errors occur, instead of asking the user for help. 
-# This option is also used when generating formulas in HTML.
-
-LATEX_BATCHMODE        = NO
-
-# If LATEX_HIDE_INDICES is set to YES then doxygen will not 
-# include the index chapters (such as File Index, Compound Index, etc.) 
-# in the output.
-
-LATEX_HIDE_INDICES     = NO
-
-#---------------------------------------------------------------------------
-# configuration options related to the RTF output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output 
-# The RTF output is optimized for Word 97 and may not look very pretty with 
-# other RTF readers or editors.
-
-GENERATE_RTF           = NO
-
-# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. 
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be 
-# put in front of it. If left blank `rtf' will be used as the default path.
-
-RTF_OUTPUT             = rtf
-
-# If the COMPACT_RTF tag is set to YES Doxygen generates more compact 
-# RTF documents. This may be useful for small projects and may help to 
-# save some trees in general.
-
-COMPACT_RTF            = NO
-
-# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated 
-# will contain hyperlink fields. The RTF file will 
-# contain links (just like the HTML output) instead of page references. 
-# This makes the output suitable for online browsing using WORD or other 
-# programs which support those fields. 
-# Note: wordpad (write) and others do not support links.
-
-RTF_HYPERLINKS         = NO
-
-# Load stylesheet definitions from file. Syntax is similar to doxygen's 
-# config file, i.e. a series of assignments. You only have to provide 
-# replacements, missing definitions are set to their default value.
-
-RTF_STYLESHEET_FILE    = 
-
-# Set optional variables used in the generation of an rtf document. 
-# Syntax is similar to doxygen's config file.
-
-RTF_EXTENSIONS_FILE    = 
-
-#---------------------------------------------------------------------------
-# configuration options related to the man page output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_MAN tag is set to YES (the default) Doxygen will 
-# generate man pages
-
-GENERATE_MAN           = NO
-
-# The MAN_OUTPUT tag is used to specify where the man pages will be put. 
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be 
-# put in front of it. If left blank `man' will be used as the default path.
-
-MAN_OUTPUT             = man
-
-# The MAN_EXTENSION tag determines the extension that is added to 
-# the generated man pages (default is the subroutine's section .3)
-
-MAN_EXTENSION          = .3
-
-# If the MAN_LINKS tag is set to YES and Doxygen generates man output, 
-# then it will generate one additional man file for each entity 
-# documented in the real man page(s). These additional files 
-# only source the real man page, but without them the man command 
-# would be unable to find the correct page. The default is NO.
-
-MAN_LINKS              = NO
-
-#---------------------------------------------------------------------------
-# configuration options related to the XML output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_XML tag is set to YES Doxygen will 
-# generate an XML file that captures the structure of 
-# the code including all documentation.
-
-GENERATE_XML           = NO
-
-# The XML_OUTPUT tag is used to specify where the XML pages will be put. 
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be 
-# put in front of it. If left blank `xml' will be used as the default path.
-
-XML_OUTPUT             = xml
-
-# The XML_SCHEMA tag can be used to specify an XML schema, 
-# which can be used by a validating XML parser to check the 
-# syntax of the XML files.
-
-XML_SCHEMA             = 
-
-# The XML_DTD tag can be used to specify an XML DTD, 
-# which can be used by a validating XML parser to check the 
-# syntax of the XML files.
-
-XML_DTD                = 
-
-# If the XML_PROGRAMLISTING tag is set to YES Doxygen will 
-# dump the program listings (including syntax highlighting 
-# and cross-referencing information) to the XML output. Note that 
-# enabling this will significantly increase the size of the XML output.
-
-XML_PROGRAMLISTING     = YES
-
-#---------------------------------------------------------------------------
-# configuration options for the AutoGen Definitions output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will 
-# generate an AutoGen Definitions (see autogen.sf.net) file 
-# that captures the structure of the code including all 
-# documentation. Note that this feature is still experimental 
-# and incomplete at the moment.
-
-GENERATE_AUTOGEN_DEF   = NO
-
-#---------------------------------------------------------------------------
-# configuration options related to the Perl module output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_PERLMOD tag is set to YES Doxygen will 
-# generate a Perl module file that captures the structure of 
-# the code including all documentation. Note that this 
-# feature is still experimental and incomplete at the 
-# moment.
-
-GENERATE_PERLMOD       = NO
-
-# If the PERLMOD_LATEX tag is set to YES Doxygen will generate 
-# the necessary Makefile rules, Perl scripts and LaTeX code to be able 
-# to generate PDF and DVI output from the Perl module output.
-
-PERLMOD_LATEX          = NO
-
-# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be 
-# nicely formatted so it can be parsed by a human reader.  This is useful 
-# if you want to understand what is going on.  On the other hand, if this 
-# tag is set to NO the size of the Perl module output will be much smaller 
-# and Perl will parse it just the same.
-
-PERLMOD_PRETTY         = YES
-
-# The names of the make variables in the generated doxyrules.make file 
-# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. 
-# This is useful so different doxyrules.make files included by the same 
-# Makefile don't overwrite each other's variables.
-
-PERLMOD_MAKEVAR_PREFIX = 
-
-#---------------------------------------------------------------------------
-# Configuration options related to the preprocessor   
-#---------------------------------------------------------------------------
-
-# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will 
-# evaluate all C-preprocessor directives found in the sources and include 
-# files.
-
-ENABLE_PREPROCESSING   = YES
-
-# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro 
-# names in the source code. If set to NO (the default) only conditional 
-# compilation will be performed. Macro expansion can be done in a controlled 
-# way by setting EXPAND_ONLY_PREDEF to YES.
-
-MACRO_EXPANSION        = NO
-
-# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES 
-# then the macro expansion is limited to the macros specified with the 
-# PREDEFINED and EXPAND_AS_DEFINED tags.
-
-EXPAND_ONLY_PREDEF     = NO
-
-# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files 
-# in the INCLUDE_PATH (see below) will be search if a #include is found.
-
-SEARCH_INCLUDES        = YES
-
-# The INCLUDE_PATH tag can be used to specify one or more directories that 
-# contain include files that are not input files but should be processed by 
-# the preprocessor.
-
-#INCLUDE_PATH           = 
-INCLUDE_PATH           = /usr/local/include/gtkmm-2.4 /usr/local/include/glibmm-2.4
-
-# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard 
-# patterns (like *.h and *.hpp) to filter out the header-files in the 
-# directories. If left blank, the patterns specified with FILE_PATTERNS will 
-# be used.
-
-INCLUDE_FILE_PATTERNS  = 
-
-# The PREDEFINED tag can be used to specify one or more macro names that 
-# are defined before the preprocessor is started (similar to the -D option of 
-# gcc). The argument of the tag is a list of macros of the form: name 
-# or name=definition (no spaces). If the definition and the = are 
-# omitted =1 is assumed. To prevent a macro definition from being 
-# undefined via #undef or recursively expanded use the := operator 
-# instead of the = operator.
-
-PREDEFINED             = 
-
-# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then 
-# this tag can be used to specify a list of macro names that should be expanded. 
-# The macro definition that is found in the sources will be used. 
-# Use the PREDEFINED tag if you want to use a different macro definition.
-
-EXPAND_AS_DEFINED      = 
-
-# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then 
-# doxygen's preprocessor will remove all function-like macros that are alone 
-# on a line, have an all uppercase name, and do not end with a semicolon. Such 
-# function macros are typically used for boiler-plate code, and will confuse 
-# the parser if not removed.
-
-SKIP_FUNCTION_MACROS   = YES
-
-#---------------------------------------------------------------------------
-# Configuration::additions related to external references   
-#---------------------------------------------------------------------------
-
-# The TAGFILES option can be used to specify one or more tagfiles. 
-# Optionally an initial location of the external documentation 
-# can be added for each tagfile. The format of a tag file without 
-# this location is as follows: 
-#   TAGFILES = file1 file2 ... 
-# Adding location for the tag files is done as follows: 
-#   TAGFILES = file1=loc1 "file2 = loc2" ... 
-# where "loc1" and "loc2" can be relative or absolute paths or 
-# URLs. If a location is present for each tag, the installdox tool 
-# does not have to be run to correct the links.
-# Note that each tag file must have a unique name
-# (where the name does NOT include the path)
-# If a tag file is not located in the directory in which doxygen 
-# is run, you must also specify the path to the tagfile here.
-
-TAGFILES               = 
-
-# When a file name is specified after GENERATE_TAGFILE, doxygen will create 
-# a tag file that is based on the input files it reads.
-
-GENERATE_TAGFILE       = 
-
-# If the ALLEXTERNALS tag is set to YES all external classes will be listed 
-# in the class index. If set to NO only the inherited external classes 
-# will be listed.
-
-ALLEXTERNALS           = NO
-
-# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed 
-# in the modules index. If set to NO, only the current project's groups will 
-# be listed.
-
-EXTERNAL_GROUPS        = YES
-
-# The PERL_PATH should be the absolute path and name of the perl script 
-# interpreter (i.e. the result of `which perl').
-
-PERL_PATH              = /usr/bin/perl
-
-#---------------------------------------------------------------------------
-# Configuration options related to the dot tool   
-#---------------------------------------------------------------------------
-
-# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will 
-# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base 
-# or super classes. Setting the tag to NO turns the diagrams off. Note that 
-# this option is superseded by the HAVE_DOT option below. This is only a 
-# fallback. It is recommended to install and use dot, since it yields more 
-# powerful graphs.
-
-CLASS_DIAGRAMS         = YES
-
-# You can define message sequence charts within doxygen comments using the \msc 
-# command. Doxygen will then run the mscgen tool (see http://www.mcternan.me.uk/mscgen/) to 
-# produce the chart and insert it in the documentation. The MSCGEN_PATH tag allows you to 
-# specify the directory where the mscgen tool resides. If left empty the tool is assumed to 
-# be found in the default search path.
-
-MSCGEN_PATH            = 
-
-# If set to YES, the inheritance and collaboration graphs will hide 
-# inheritance and usage relations if the target is undocumented 
-# or is not a class.
-
-HIDE_UNDOC_RELATIONS   = YES
-
-# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is 
-# available from the path. This tool is part of Graphviz, a graph visualization 
-# toolkit from AT&T and Lucent Bell Labs. The other options in this section 
-# have no effect if this option is set to NO (the default)
-
-HAVE_DOT               = NO
-
-# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen 
-# will generate a graph for each documented class showing the direct and 
-# indirect inheritance relations. Setting this tag to YES will force the 
-# the CLASS_DIAGRAMS tag to NO.
-
-CLASS_GRAPH            = YES
-
-# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen 
-# will generate a graph for each documented class showing the direct and 
-# indirect implementation dependencies (inheritance, containment, and 
-# class references variables) of the class with other documented classes.
-
-COLLABORATION_GRAPH    = YES
-
-# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen 
-# will generate a graph for groups, showing the direct groups dependencies
-
-GROUP_GRAPHS           = YES
-
-# If the UML_LOOK tag is set to YES doxygen will generate inheritance and 
-# collaboration diagrams in a style similar to the OMG's Unified Modeling 
-# Language.
-
-UML_LOOK               = NO
-
-# If set to YES, the inheritance and collaboration graphs will show the 
-# relations between templates and their instances.
-
-TEMPLATE_RELATIONS     = NO
-
-# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT 
-# tags are set to YES then doxygen will generate a graph for each documented 
-# file showing the direct and indirect include dependencies of the file with 
-# other documented files.
-
-INCLUDE_GRAPH          = YES
-
-# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and 
-# HAVE_DOT tags are set to YES then doxygen will generate a graph for each 
-# documented header file showing the documented files that directly or 
-# indirectly include this file.
-
-INCLUDED_BY_GRAPH      = YES
-
-# If the CALL_GRAPH and HAVE_DOT tags are set to YES then doxygen will 
-# generate a call dependency graph for every global function or class method. 
-# Note that enabling this option will significantly increase the time of a run. 
-# So in most cases it will be better to enable call graphs for selected 
-# functions only using the \callgraph command.
-
-#CALL_GRAPH             = NO
-CALL_GRAPH             = YES
-
-# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then doxygen will 
-# generate a caller dependency graph for every global function or class method. 
-# Note that enabling this option will significantly increase the time of a run. 
-# So in most cases it will be better to enable caller graphs for selected 
-# functions only using the \callergraph command.
-
-#CALLER_GRAPH           = NO
-CALLER_GRAPH           = YES
-
-# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen 
-# will graphical hierarchy of all classes instead of a textual one.
-
-GRAPHICAL_HIERARCHY    = YES
-
-# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES 
-# then doxygen will show the dependencies a directory has on other directories 
-# in a graphical way. The dependency relations are determined by the #include
-# relations between the files in the directories.
-
-DIRECTORY_GRAPH        = YES
-
-# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images 
-# generated by dot. Possible values are png, jpg, or gif
-# If left blank png will be used.
-
-DOT_IMAGE_FORMAT       = png
-
-# The tag DOT_PATH can be used to specify the path where the dot tool can be 
-# found. If left blank, it is assumed the dot tool can be found in the path.
-
-DOT_PATH               = 
-
-# The DOTFILE_DIRS tag can be used to specify one or more directories that 
-# contain dot files that are included in the documentation (see the 
-# \dotfile command).
-
-DOTFILE_DIRS           = 
-
-# The MAX_DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of 
-# nodes that will be shown in the graph. If the number of nodes in a graph 
-# becomes larger than this value, doxygen will truncate the graph, which is 
-# visualized by representing a node as a red box. Note that doxygen will always 
-# show the root nodes and its direct children regardless of this setting.
-
-DOT_GRAPH_MAX_NODES    = 50
-
-# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent 
-# background. This is disabled by default, which results in a white background. 
-# Warning: Depending on the platform used, enabling this option may lead to 
-# badly anti-aliased labels on the edges of a graph (i.e. they become hard to 
-# read).
-
-DOT_TRANSPARENT        = NO
-
-# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output 
-# files in one run (i.e. multiple -o and -T options on the command line). This 
-# makes dot run faster, but since only newer versions of dot (>1.8.10) 
-# support this, this feature is disabled by default.
-
-DOT_MULTI_TARGETS      = NO
-
-# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will 
-# generate a legend page explaining the meaning of the various boxes and 
-# arrows in the dot generated graphs.
-
-GENERATE_LEGEND        = YES
-
-# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will 
-# remove the intermediate dot files that are used to generate 
-# the various graphs.
-
-DOT_CLEANUP            = YES
-
-#---------------------------------------------------------------------------
-# Configuration::additions related to the search engine   
-#---------------------------------------------------------------------------
-
-# The SEARCHENGINE tag specifies whether or not a search engine should be 
-# used. If set to NO the values of all tags below this one will be ignored.
-
-SEARCHENGINE           = NO
diff -Nru gxemul-0.6.2/doc/doxygen.css gxemul-0.7.0+dfsg/doc/doxygen.css
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diff -Nru gxemul-0.6.2/doc/doxygen_footerFile.html gxemul-0.7.0+dfsg/doc/doxygen_footerFile.html
--- gxemul-0.6.2/doc/doxygen_footerFile.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/doxygen_footerFile.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,4 +0,0 @@
-<hr size="1"><address style="text-align: right;"><small>
-Generated on $datetime for $projectname by&nbsp;<a href="http://www.doxygen.org/index.html"><img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> $doxygenversion</small></address>
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/doxygen_headerFile.html gxemul-0.7.0+dfsg/doc/doxygen_headerFile.html
--- gxemul-0.6.2/doc/doxygen_headerFile.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/doxygen_headerFile.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,11 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><title>$title</title>
-  <meta name="robots" content="noarchive,nofollow,noindex">
-  <link href="$relpath$doxygen.css" rel="stylesheet" type="text/css">
-  <link href="$relpath$tabs.css" rel="stylesheet" type="text/css">
-</head><body style="font-family : sans-serif;">
-<h1>$title</h1><p>
-<a href="../../">Back to the index.</a>
-<!-- 10 lines.  -->
-
diff -Nru gxemul-0.6.2/doc/experiments.html gxemul-0.7.0+dfsg/doc/experiments.html
--- gxemul-0.6.2/doc/experiments.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/experiments.html	2021-11-27 09:42:23.000000000 +0000
@@ -111,7 +111,7 @@
 Run <tt>gxemul -H</tt> for an up-to-date list.
 
 
-<p>Here are some examples of guest OSes that run in the test machine modes:
+<p>Here are some examples of guest OSes that use or (have used) the test machine modes:
 
 <p>
 <ul>
@@ -124,10 +124,26 @@
 	<b>ftp <a href="http://www.helenos.org/releases/HelenOS-0.5.0-mips32-GXemul.boot">http://www.helenos.org/releases/HelenOS-0.5.0-mips32-GXemul.boot</a></b>
   	<b>gxemul -X -E testmips HelenOS-0.5.0-mips32-GXemul.boot</b></pre>
 
-	<li><p><a name="glattmumk">Glatt MU/MK:</a>
+	<p>
+	<li>FreeBSD/MIPS:
+		<br>For a while, testmips was <a href="http://web.archive.org/web/20180218123520/https://wiki.freebsd.org/FreeBSD/MipsEmulation">one of
+		the targets when developing the MIPS port of FreeBSD</a>.
+		See <a href="https://svnweb.freebsd.org/base?view=revision&revision=234920">revision 234920</a>
+		for more details. (The target was removed
+		<a href="https://reviews.freebsd.org/rS342256">in December
+		2018</a>; focus from now on is on the Malta board.)
+
+	<p>
+	<li><a name="glattmumk">Glatt MU/MK:</a>
 		<br>One of <a href="https://github.com/caladri/glatt">Glatt MU/MK</a>'s targets is <tt>testmips</tt>.
 
-	<li><p><a name="ycx5">YCX5:</a>
+	<p>
+	<li>MINIX 3.x:
+		<br><a href="http://yana.jp/20160811/computer/minix.ja.euc.html">http://yana.jp/20160811/computer/minix.ja.euc.html</a> indicates that an attempt was made
+		to port MINIX 3.x to testarm and testmips.
+
+	<p>
+	<li><a name="ycx5">YCX5:</a>
 		<br>One of <a href="http://gavare.se/ycx5/">YCX5</a>'s primary development targets is <tt>testmips</tt>.
 </ul>
 
@@ -147,13 +163,36 @@
 
   <tr>
     <td align="left" valign="top" width="200">
+	<a name="expdevices_ram"><b><tt>ram</tt>:</b></a>
+	<p>The first 256 MB of RAM.
+	<br>Physical address:&nbsp&nbsp;<font color="#0000f0">0x00000000</font>
+    </td>
+    <td align="left" valign="top" width="25">&nbsp;</td>
+    <td align="left" valign="top">
+	<table border="0">
+	  <tr>
+	    <td align="left" valign="top"><i><u>Comment:</u></i></td>
+	  </tr>
+	  <tr>
+	    <td align="left" valign="top"></td>
+	  </tr>
+	</table>
+    </td>
+  </tr>
+
+  <tr height="15">
+    <td height="15">&nbsp;</td>
+  </tr>
+
+  <tr>
+    <td align="left" valign="top" width="200">
 	<a name="expdevices_cons"><b><tt>cons</tt>:</b></a>
 	<p>A simple console device, for writing
 	characters to the controlling terminal
 	and receiving keypresses.
 	<p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_cons.c</tt></font>
 	<p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_cons.h</tt></font>
-	<br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x10000000</font>
+	<br>Physical address:&nbsp&nbsp;<font color="#0000f0">0x10000000</font>
     </td>
     <td align="left" valign="top" width="25">&nbsp;</td>
     <td align="left" valign="top">
@@ -189,7 +228,7 @@
 	multi-processor system.
 	<p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_mp.c</tt></font>
 	<p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_mp.h</tt></font>
-	<br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x11000000</font>
+	<br>Physical address:&nbsp&nbsp;<font color="#0000f0">0x11000000</font>
     </td>
     <td></td>
     <td align="left" valign="top">
@@ -291,10 +330,11 @@
     <td align="left" valign="top">
 	<a name="expdevices_fb"><b><tt>fb</tt>:</b></a>
 	<p>A simple linear framebuffer, for graphics output.
-	640 x 480 pixels, 3 bytes per pixel (red, green, blue, 8 bits each).
+	Initial resolution is 640 x 480 pixels, with 3 bytes per pixel
+	(red, green, blue, 8 bits each).
 	<p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_fb.c</tt></font>
 	<p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_fb.h</tt></font>
-	<br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x12000000</font>
+	<br>Physical address:&nbsp&nbsp;<font color="#0000f0">0x12000000</font>
     </td>
     <td></td>
     <td align="left" valign="top">
@@ -304,9 +344,17 @@
 	    <td align="left" valign="top"><i><u>Effect:</u></i></td>
 	  </tr>
 	  <tr>
-	    <td align="left" valign="top"><tt>0x00000-</tt><br><tt>0xe0fff</tt></td>
+	    <td align="left" valign="top"><tt>0x00000000</tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
 	    <td align="left" valign="top">Read: read pixel values.
-		<br>Write: write pixel values.</td>
+		Write: write pixel values.</td>
+	  </tr>
+	  <tr>
+	    <td align="left" valign="top"><tt>0x00f00000</tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td>
+	    <td align="left" valign="top">Read/Write: Control ports for changing the
+	    	resolution at runtime, etc. See <tt>dev_fb.h</tt> and
+	    	<tt>dev_fbctrl.cc</tt> for more details.
+	    	<p>If the resolution is read back as X=0 Y=0, then that
+	    	means that graphics is not used, only serial console.</td>
 	  </tr>
 	</table>
     </td>
@@ -324,7 +372,7 @@
 	write operations finish instantaneously.
 	<p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_disk.c</tt></font>
 	<p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_disk.h</tt></font>
-	<br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x13000000</font>
+	<br>Physical address:&nbsp&nbsp;<font color="#0000f0">0x13000000</font>
     </td>
     <td></td>
     <td align="left" valign="top">
@@ -378,7 +426,7 @@
 	and receive packets on a simulated network.
 	<p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_ether.c</tt></font>
 	<p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_ether.h</tt></font>
-	<br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x14000000</font>
+	<br>Physical address:&nbsp&nbsp;<font color="#0000f0">0x14000000</font>
     </td>
     <td></td>
     <td align="left" valign="top">
@@ -432,7 +480,7 @@
 	and to cause periodic interrupts.
 	<p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_rtc.c</tt></font>
 	<p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_rtc.h</tt></font>
-	<br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x15000000</font>
+	<br>Physical address:&nbsp&nbsp;<font color="#0000f0">0x15000000</font>
     </td>
     <td></td>
     <td align="left" valign="top">
@@ -479,7 +527,7 @@
 	<p>An Interrupt Controller. (Note: Not used for the MIPS test machine.)
 	<p>Source code:&nbsp;&nbsp;<font color="#0000f0"><tt>src/devices/dev_irqc.c</tt></font>
 	<p>Include file:&nbsp;&nbsp;<font color="#0000f0"><tt>dev_irqc.h</tt></font>
-	<br>Default physical address:&nbsp&nbsp;<font color="#0000f0">0x16000000</font>
+	<br>Physical address:&nbsp&nbsp;<font color="#0000f0">0x16000000</font>
     </td>
     <td></td>
     <td align="left" valign="top">
@@ -522,9 +570,9 @@
 
 <p>If the physical address is <tt>0x10000000</tt>, then for MIPS that
 means that it can be accessed at virtual address
-<tt>0xffffffffb0000000</tt>. (Actually it can be accessed at
-<tt>0xffffffff90000000</tt> too, but devices should usually be accessed in
-a non-cached manner.)
+<tt>0xffffffffb0000000</tt>. (Using virtual address
+<tt>0xffffffff90000000</tt> may work in the emulator, but should be
+avoided, since devices should in general be accessed in a non-cached manner.)
 
 <p>When using the ARM or PPC test machines, the addresses are
 <tt>0x10000000</tt>, <tt>0x11000000</tt> etc., so no need to add any
diff -Nru gxemul-0.6.2/doc/framework.html gxemul-0.7.0+dfsg/doc/framework.html
--- gxemul-0.6.2/doc/framework.html	2019-06-22 18:23:29.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/framework.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,280 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html>
-<head>
-  <title>GXemul: Description of the framework</title>
-  <meta name="robots" content="noarchive,nofollow,noindex">
-</head>
-<body style="font-family : sans-serif;">
-
-<!-- 10 lines header.  -->
-
-<h1>GXemul: Description of the framework</h1>
-<p>
-
-<a href="./">Back to the index.</a>
-
-<!--
-
-Copyright (C) 2009-2019  Anders Gavare.  All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-3. The name of the author may not be used to endorse or promote products
-   derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-SUCH DAMAGE.
-
--->
-
-<p><br>
-<ul>
-  <li><a href="#introduction">Introduction</a>
-  <li><a href="#components">Components</a>
-  <li><a href="#machinetemplates">Machine templates</a>
-</ul>
-
-
-
-<p><br>
-<a name="introduction"></a>
-<h3>Introduction:</h3>
-
-<p>Starting with GXemul 0.6.x, a completely redesigned framework is being
-worked on, compared to the 0.4.x series. The emulator thus contains two
-completely different frameworks.
-This chapter of the documentation describes the core concepts of the
-new framework. The framework is <i><b>still being designed and
-implemented</b></i>, so
-what you are reading can be considered an early draft, or a work-in-progress.
-
-<p>Almost all of the emulation modes in GXemul are implemented using the
-earlier (pre-0.6) framework, but newly implemented emulation modes may
-use the new framework instead.
-
-
-
-
-<p><br>
-<a name="components"></a>
-<h3>Components:</h3>
-
-<p>The most important concept in the new framework is that of the
-<a href="components.html"><i>component</i></a>. A component can have sub-components
-(children) and a parent, so the components make up a configuration tree:
-
-<p><center><img src="model.png"></center>
-
-<p>Component classes are registered in a <i>component registry</i>.
-
-<p>Each component in the emulation setup has a <i>path</i>, e.g.
-<tt>root.machine1.mainbus0.cpu0</tt> for the
-CPU in the right-most machine in the example above. Often, shorter paths can
-be used, such as <tt>machine1</tt> instead of <tt>root.machine1</tt>, if there
-is no ambiguity.
-
-<p>Each component has <i>state</i>, which is a collection of <i>variables</i>.
-For e.g. a CPU component, the state is usually a set of registers. Each component
-also has a set of <i>methods</i> which can be executed. A CPU may disassemble
-instructions using its <i>unassemble</i> method:
-
-<p><table border=0 width=100%><tr><td width=5%>&nbsp;</td><td><pre>
-GXemul> <b>root</b>
-  root
-  \-- machine0  [testm88k]
-      \-- mainbus0
-          |-- cpu0  (88100, 50 MHz)
-          |-- ram0  (32 MB at offset 0)
-          |-- fb_videoram0  (15 MB at offset 0x12000000)
-          \-- rom0  (4 MB at offset 0xff800000)
-
-  accuracy = cycle
-  step     = 0
-GXemul> <b>cpu0.unassemble</b>
-&lt;_f&gt;
-0x12b8 &lt;- 67ff0020   subu    r31,r31,0x20 
-0x12bc    27df0010   st      r30,r31,0x10 
-0x12c0    63df0010   addu    r30,r31,0x10 
-0x12c4    58400320   or      r2,r0,0x320  
-0x12c8    58600258   or      r3,r0,0x258  
-0x12cc    243f0014   st      r1,r31,0x14  
-0x12d0    231f0008   st.d    r24,r31,0x8  
-0x12d4    cfffffe7   bsr.n   0x1270          ; &lt;_change_resolution>
-0x12d8    f6c0201f   st.d    r22,r0,r31   
-0x12dc    cbffff89   bsr     0x1100          ; &lt;_my_random>        
-0x12e0    f6c05802   or      r22,r0,r2    
-...
-</pre></td></tr></table>
-
-<p>When single-stepping, all state change is displayed. (In the old framework,
-it was up to individual device/component implementations to print debug
-messages.)
-
-<p><table border=0 width=100%><tr><td width=5%>&nbsp;</td><td><pre>
-GXemul&gt; <b>step</b>
-step 0: cpu0: &lt;_f&gt;
-              0x12b8    67ff0020   subu   r31,r31,0x20
-        => cpu0.pc: 0x12b8 -> 0x12bc
-        => cpu0.r31: 0xff0 -> 0xfd0
-GXemul&gt; 
-step 1: cpu0: 0x12bc    27df0010   st   r30,r31,0x10
-        => cpu0.pc: 0x12bc -> 0x12c0
-GXemul&gt; 
-</pre></td></tr></table>
-
-<p>The example above may not be that interesting, but imagine that the CPU
-reads from a device which has a zero-on-read status register. Then the
-output may look something like this: (this is a made-up example, for now)
-
-<p><table border=0 width=100%><tr><td width=5%>&nbsp;</td><td><pre>
-GXemul&gt; <b>step</b>
-step 2: cpu0: 0xffffffff800101f4    12345678   lw   t3,256(a1)
-        =&gt; cpu0.pc: 0xffffffff800101f4 -&gt; 0xffffffff800101f8
-        =&gt; cpu0.t3: 0 -&gt; 0x2200
-        =&gt; intcontroller.status: 0x2200 -&gt; 0
-GXemul&gt; 
-</pre></td></tr></table>
-
-<p>Components that have a <i>frequency</i> are executed in steps. Those that
-do not have a frequency only do things if triggered by some other means (i.e.
-another component). The components' relative frequencies determine how many
-steps they will run at a time. For example, if we have component A running at
-100 MHz, and component B running at 1 MHz, then in 100 steps A will be executing
-100 cycles and B only 1. The GXemul framework makes sure that the exact sequence
-of cycles is the same nomatter if the user is single-stepping, or running
-the simulation continuously.
-
-<p>The frequency mentioned above does not have anything at all to do with how
-fast a particular host executes the simulation. The frequencies are only relative
-to each other.
-
-<p>Is the new framework <i>cycle-accurate</i>? Both yes and no. The framework
-itself aims to be step accurate, but it is up to the implementation of
-individual components to also be cycle accurate. For example,
-the CPU components that are available out-of-the-box in GXemul do not
-try to simulate out-of-order execution, or pipe-line stalls, or other
-effects that happen in a real processor, so even though the aim is that the
-implementation should be cycle accurate, it does not simulate
-any <i>existing real-world</i> processor in a cycle-accurate manner.
-
-<p>Is it theoretically <i>possible</i> to implement pipe-lined and/or
-out-of-order CPU models for GXemul's new framework? Maybe. But that has not been done.
-
-<p>Note that the component framework described on this page should not be
-confused with the <a href="translation.html">dyntrans mechanism</a> (sometimes
-referred to as "the dyntrans framework"). The dyntrans framework is a helper
-mechanism (or, to use C++ terminology, a base class) for implementing specific CPUs.
-
-
-
-
-
-
-<p><br>
-<a name="machinetemplates"></a>
-<h3>Machine templates:</h3>
-
-<p>Although the framework is generic enough to simulate/emulate many kinds of
-components, the focus is on emulating components found in electronic computers,
-such as processors, RAM, caches, graphics cards, etc. In most cases, these
-components are naturally contained in a <a href="machines.html"><i>machine</i></a>.
-
-<p>Machines are registered in a <i>machine registry</i>. The end-user can list
-the available machines in the registry by running <tt>gxemul -H</tt> (or by
-reading the documentation built by <tt>make documentation</tt>).
-
-<p>In the older framework, machines were a special type of entity in the emulator,
-which held one or more CPUs of a particular architecture, e.g.
-<a href="http://en.wikipedia.org/wiki/MIPS_architecture">MIPS</a>. In fact,
-the entire machine was of that architecture. The machine also had hardcoded RAM.
-While this worked well, it was not generic enough to support some cases that
-occur in the real world:
-<ul>
-	<li>Processors of different architectures in the same machine. An
-		example of this is the <a href="http://en.wikipedia.org/wiki/Dreamcast">Dreamcast</a>,
-		which has an <a href="http://en.wikipedia.org/wiki/SuperH">SH4</a> main
-		CPU, and an <a href="http://en.wikipedia.org/wiki/ARM_architecture">ARM</a> CPU as a sound processor. Other examples
-		could be GPUs in modern workstations being considered as CPUs.
-	<li>Hardcoded RAM required hacks for those architectures that do not
-		have RAM at offset 0, for example some <a href="http://en.wikipedia.org/wiki/Silicon_Graphics">SGI</a> machines, or
-		the Dreamcast.
-</ul>
-
-<p>The 0.6.0 framework, however, has a somewhat generalized view of what a machine
-is. Machines are simply <i>templates</i> for how components are configured.
-When adding such a template machine to the configuration tree, the result
-is a complete tree of components:
-<pre>
-	GXemul> <b>add testm88k</b>
-	GXemul> <b>root</b>
-	  root
-	  \-- machine0  [testm88k]
-	      \-- mainbus0
-	          |-- cpu0  (88100, 50 MHz)
-	          |-- ram0  (32 MB at offset 0)
-	          |-- fb_videoram0  (15 MB at offset 0x12000000)
-	          \-- rom0  (4 MB at offset 0xff800000)
-</pre>
-
-<p>
-Here, a <tt>testm88k</tt> machine template was added (to the <tt>root</tt>
-component). Adding something without specifying where to add it always assumes
-that the <tt>root</tt> component is the target. The name of the machine in the
-component tree is <tt>root.machine0</tt>. The tree dump shows that it was created using the
-<tt>testm88k</tt> template.
-
-<p>To make it easier to start a new emulation from the command line (and to be
-more or less backward compatible with pre-0.6.x command line syntax), the
-<tt>-e</tt> option can be used to start an emulation based on a template machine:
-<pre>
-	$ <b>./gxemul -V -e testm88k</b>
-	GXemul (unknown version)      Copyright (C) 2003-2019  Anders Gavare
-
-	  mainbus0
-	  |-- cpu0  (88100, 50 MHz)
-	  |-- ram0  (32 MB at offset 0)
-	  |-- fb_videoram0  (15 MB at offset 0x12000000)
-	  \-- rom0  (4 MB at offset 0xff800000)
-
-	GXemul> 
-</pre>
-
-<p>(When starting a single emulated machine from the command line, only the emulated machine is shown,
-not the entire tree from the <tt>root</tt> node.)
-
-<p>The same machine configuration can be set up by hand as well:
-
-<pre>
-	GXemul> <b>add machine root</b>
-	GXemul> <b>add mainbus machine0</b>
-	GXemul> <b>add ram mainbus0</b>
-	GXemul> <b>ram0.memoryMappedSize = 0x2000000</b>
-	GXemul> <b>add m88k_cpu mainbus0</b>
-	GXemul> <b>root</b>
-	  root
-	  \-- machine0
-	      \-- mainbus0
-	          |-- ram0  (32 MB at offset 0)
-	          \-- cpu0  (88100, 50 MHz)
-</pre>
-
-<p>(Omitting <tt>rom0</tt> and <tt>fb_videoram0</tt> for brevity.)
-
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/head.html gxemul-0.7.0+dfsg/doc/head.html
--- gxemul-0.6.2/doc/head.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/head.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,47 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html>
-<head>
-  <title>GXemul: PAGETITLE</title>
-  <meta name="robots" content="noarchive,nofollow,noindex">
-</head>
-<body style="font-family : sans-serif;">
-
-<!-- 10 lines header.  -->
-
-<h1>GXemul: PAGETITLE</h1>
-<p>
-
-<a href="./index.html">Back to the index.</a>
-
-<!--
-
-Copyright (C) 2003-2010  Anders Gavare.  All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-3. The name of the author may not be used to endorse or promote products
-   derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-SUCH DAMAGE.
-
--->
-
-<p><br>
-
diff -Nru gxemul-0.6.2/doc/index.html gxemul-0.7.0+dfsg/doc/index.html
--- gxemul-0.6.2/doc/index.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/index.html	2021-11-27 09:42:23.000000000 +0000
@@ -14,7 +14,7 @@
 
 <!--
 
-Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -95,8 +95,9 @@
   <li><a href="networking.html">Networking</a>
   <ul>
     <li><a href="networking.html#intro">Introduction</a>
+    <li><a href="networking.html#tap">Virtual Ethernet switch using a tap device</a>
     <li><a href="networking.html#multihost">Network across multiple hosts</a>
-    <li><a href="networking.html#direct_example_1">Direct-access example 1: udp_snoop</a>
+    <li><a href="networking.html#direct_example_1">UDP "Direct-access" example: udp_snoop</a>
   </ul>
 
   <p>
@@ -128,15 +129,6 @@
   </ul>
 
   <p>
-
-  <li><a href="framework.html">Description of the new framework (under development)</a>
-  <ul>
-	<li><a href="machines.html">Machines</a> <small>(new framework)</small>
-	<li><a href="components.html">Components</a> <small>(new framework)</small>
-	<li><a href="doxygen/html/index.html">Source code documentation (Doxygen)</a> <small>(new framework)</small>
-  </ul>
-
-  <p>
   
   <li><a href="TODO.html">TODO list</a>
 
diff -Nru gxemul-0.6.2/doc/intro.html gxemul-0.7.0+dfsg/doc/intro.html
--- gxemul-0.6.2/doc/intro.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/intro.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -77,7 +77,7 @@
 
 
 <p>Thanks to (in no specific order) Joachim Buss, Olivier Houchard, Juli 
-Mallett, Juan Romero Pardines, Carl van Schaik, Miod Vallat, Alec Voropay,
+Mallett, Juan Romero Pardines, Carl van Schaik, Jason Thorpe, Miod Vallat, Alec Voropay,
 G&ouml;ran Weinholt, Alexander Yurchenko, and everyone else who has provided
 feedback.
 
@@ -96,32 +96,22 @@
 </pre>
 
 <p>This should work on most Unix-like systems, with few or no modifications
-to the source code. Requirements are:
-<ul>
-	<li>A reasonably modern C++ compiler environment, including STL.
-</ul>
+to the source code. The basic requirement is a reasonably modern C compiler (C99).
 
 <p>GXemul does not <i>require</i> any additional third-party libraries to build.
 However, the following optional libraries or third-party software give
 additional functionality:
 <ul>
 	<li>X11 headers and libraries: for graphical framebuffer emulation.
-	<li><a href="http://www.doxygen.org/">Doxygen</a>: if installed, source code documentation will be generated
-		when documentation is built.
 </ul>
 
 <p>The emulator's performance is dependent on both runtime settings 
 and on compiler settings, so you might want to experiment with using 
-different <tt>CXX</tt>, <tt>CXXFLAGS</tt>, and <tt>LDFLAGS</tt> environment
+different <tt>CC</tt>, <tt>CFLAGS</tt>, and <tt>LDFLAGS</tt> environment
 variable values when running the <tt>configure</tt> script.
 
 <p>During development of the emulator: <tt><b>configure --debug</b></tt> may be used
 to enable some debugging aids and turn off optimizations.
-<tt><b>make test</b></tt>
-can be used to run unit tests (only needed if you want to experiment with <a href="framework.html">the new
-experimental framework that is under development</a>).
-<tt><b>make documentation</b></tt> generates machine and component descriptions in HTML
-for the new framework.
 If you often recompile the whole tree (<tt>make clean_all</tt>,
 followed by <tt>configure</tt> and <tt>make</tt> again), then using
 <a href="http://ccache.samba.org/">ccache</a> is recommended.
@@ -136,9 +126,9 @@
 for each individual host architecture; the intermediate representation 
 that the dyntrans system uses can be executed on any host architecture.
 
-<p>Most of the development is done on FreeBSD/amd64 using clang and/or GNU C++,
+<p>Most of the development is done on FreeBSD/amd64 using clang and/or GNU C,
 but every now and then the code is built on Linux,
-or NetBSD/OpenBSD inside GXemul itself.
+or on NetBSD or OpenBSD inside GXemul itself.
 Although it is possible that GXemul may build and run on non-Unix-like platforms,
 such as <a href="http://www.cygwin.com/">Cygwin</a> inside Windows, Unix-like
 systems are the primary platform. Some functionality may be lost or not work as
@@ -160,29 +150,36 @@
 instructions provided <a href="machine_decstation.html#netbsdpmaxinstall">here</a> should let you install 
 NetBSD/pmax in a way very similar to how it is done on a real DECstation.
 
-<p>If you are interested in using the emulator to develop code on your 
-own, then you should also read the section about <a 
-href="experiments.html#hello">Hello World</a> and the section about
-<a href="debugging.html">debugging</a>.
+<p>If you want to inspect or debug arbitrary binaries, you should read
+the section about <a href="debugging.html">debugging</a>.
+
+<p>If you are interested in developing code on your own from scratch to
+run in the emulator, then you should also read the section about <a 
+href="experiments.html#hello">Hello World</a>.
 
 <p>To exit the emulator, type CTRL-C to show the 
 single-step debugger prompt (if it is not already displayed),
-and then type <tt><b>quit</b></tt>.
+and then type <tt><b>quit</b></tt>:
+
+<p><pre>
+	...
+	GXemul&gt; <b>quit</b>
+</pre>
 
 <p>If you are starting an emulation by entering settings directly on the 
-command line, and you are not using the <tt><b>-x</b></tt> option, then 
-all terminal input and output will go to the main controlling terminal. 
-CTRL-C is used to break into the debugger, so in order to send CTRL-C to 
-the running (emulated) program, you may use CTRL-B. (This should be a 
+command line, all terminal input and output will go to the main controlling terminal. 
+CTRL-C is used to break into the debugger, so in order to send an actual CTRL-C to 
+the running (emulated) program, type CTRL-B. (This should be a 
 reasonable compromise to allow the emulator to be usable even on systems 
 without X Windows.)
 
 <p>There is no way to send CTRL-B to the emulated program, when 
-typing in the main controlling terminal window. You either need to
-use <a href="configfiles.html">configuration files</a>, or use 
-<tt><b>-x</b></tt>. Both these solutions cause new xterms to be opened for 
-each emulated serial port that is written to. CTRL-B and CTRL-C both have 
-their original meaning in those xterm windows.
+typing in the main controlling terminal window. However, by using the <tt>-x</tt>
+command line option, separate terminal windows will be launched
+for each serial I/O port being written to. (This also happens when you use
+<a href="configfiles.html">configuration files</a> with <i>more than one</i>
+machine specified.) CTRL-B and CTRL-C both have their original meaning
+in those xterm windows.
 
 
 
@@ -210,7 +207,7 @@
     	(<a href="machine_rpi.html#netbsdrpi"><font color="red">NetBSD/raspberrypi</font></a>,
     	<a href="machine_rpi.html#freebsdrpi"><font color="red">FreeBSD</font></a>,
     	<a href="machine_rpi.html#helenosrpi"><font color="red">HelenOS/rpi</font></a>)</small>
-    <li><b><a href="experiments.html#testmachines">testarm</a></b> (<a href="experiments.html#helenos">HelenOS/arm</a>)
+    <li><b><a href="experiments.html#testmachines">testarm</a></b>
   </ul>
   <p>
   <li><b><u>MIPS</u></b>
@@ -242,15 +239,14 @@
     <li><small><b><a href="machine_vocore.html"><font color="red">VoCore</font></a></b>
 	(<a href="machine_vocore.html#freebsdvocore"><font color="red">FreeBSD/vocore</font></a>,
     	<a href="machine_vocore.html#linuxvocore"><font color="red">Linux/vocore</font></a>)</small>
-    <li><b><a href="experiments.html#testmachines">testmips</a></b> (<a href="experiments.html#helenos">HelenOS/mips</a>,
-	<a href="experiments.html#glattmumk">Glatt MU/MK</a>, <a href="experiments.html#ycx5">YCX5/testmips</a>)
+    <li><b><a href="experiments.html#testmachines">testmips</a></b>
   </ul>
   <p>
   <li><b><u>Motorola 88K</u></b>
   <ul>
-    <li><small><b><a href="machine_luna88k.html"><font color="red">Luna 88K</font></a></b> (<a href="machine_luna88k.html#openbsdluna88k"><font color="red">OpenBSD/luna88k</font></a>)</small>
+    <li><b><a href="machine_luna88k.html">Luna 88K</a></b> (<a href="machine_luna88k.html#openbsdluna88k">OpenBSD/luna88k</a>)
     <li><b><a href="machine_mvme88k.html">Motorola MVME187</a></b> (<a href="machine_mvme88k.html#openbsdmvme88kinstall">OpenBSD/mvme88k</a>)
-    <li><b><a href="experiments.html#testmachines">oldtestm88k</a></b>
+    <li><b><a href="experiments.html#testmachines">testm88k</a></b>
   </ul>
   <p>
   <li><b><u>PowerPC</u></b>
diff -Nru gxemul-0.6.2/doc/machine_arc.html gxemul-0.7.0+dfsg/doc/machine_arc.html
--- gxemul-0.6.2/doc/machine_arc.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/machine_arc.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2006-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -170,7 +170,7 @@
 
 </pre>
   <li>Download the entire arc directory from the ftp server: (approx. 75 MB)<pre>
-	<b>wget -np -l 0 -r <a href="ftp://ftp.se.openbsd.org/pub/OpenBSD/2.3/arc/">ftp://ftp.se.openbsd.org/pub/OpenBSD/2.3/arc/</a></b>
+	<b>wget -np -l 0 -r <a href="https://ftp.nluug.nl/OpenBSD/2.3/arc/">https://ftp.nluug.nl/OpenBSD/2.3/arc/</a></b>
 
 </pre>
 
@@ -178,7 +178,7 @@
 	(I recommend using <tt>mkisofs</tt> for that purpose. If you don't
 	already have <tt>mkisofs</tt> installed on your system, you need
 	to install it in order to do this.)<pre>
-	<b>mkisofs -o openbsd_arc_2.3.iso ftp.se.openbsd.org/pub/OpenBSD/</b>
+	<b>mkisofs -o openbsd_arc_2.3.iso ftp.nluug.nl/OpenBSD/</b>
 
 </pre>
   <li>Start the emulator using this command line:<pre>
@@ -195,7 +195,7 @@
 
 <p>
 <pre>
-	<b>gxemul -X -e pica -d obsd_arc.img ftp.se.openbsd.org/pub/OpenBSD/2.3/arc/bsd</b>
+	<b>gxemul -X -e pica -d obsd_arc.img ftp.nluug.nl/OpenBSD/2.3/arc/bsd</b>
 
 </pre>
 
diff -Nru gxemul-0.6.2/doc/machine_cats.html gxemul-0.7.0+dfsg/doc/machine_cats.html
--- gxemul-0.6.2/doc/machine_cats.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/machine_cats.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2006-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -53,6 +53,9 @@
 perhaps run in the future.
 
 <p>Known issue: Clocks inside the emulated guest OS run at the wrong pace.
+For example, typing "<tt>date; sleep 10; date</tt>" inside NetBSD/cats takes
+10 seconds to run, but outputs dates that are over 2 minute apart (!) on
+my machine.
 
 
 
@@ -77,14 +80,14 @@
 
 </pre>
   <li>Download the NetBSD/cats ISO image and the generic and install kernels:<pre>
-	<a href="ftp://ftp.de.netbsd.org/pub/NetBSD/iso/8.0/NetBSD-8.0-cats.iso">ftp://ftp.de.netbsd.org/pub/NetBSD/iso/8.0/NetBSD-8.0-cats.iso</a>
-	<a href="ftp://ftp.de.netbsd.org/pub/NetBSD/NetBSD-8.0/cats/binary/kernel/netbsd-GENERIC.aout.gz">ftp://ftp.de.netbsd.org/pub/NetBSD/NetBSD-8.0/cats/binary/kernel/netbsd-GENERIC.aout.gz</a>
-	<a href="ftp://ftp.de.netbsd.org/pub/NetBSD/NetBSD-8.0/cats/binary/kernel/netbsd-INSTALL.aout.gz">ftp://ftp.de.netbsd.org/pub/NetBSD/NetBSD-8.0/cats/binary/kernel/netbsd-INSTALL.aout.gz</a>
+	<a href="ftp://ftp.de.netbsd.org/pub/NetBSD/iso/8.1/NetBSD-8.1-cats.iso">ftp://ftp.de.netbsd.org/pub/NetBSD/iso/8.1/NetBSD-8.1-cats.iso</a>
+	<a href="ftp://ftp.de.netbsd.org/pub/NetBSD/NetBSD-8.1/cats/binary/kernel/netbsd-GENERIC.aout.gz">ftp://ftp.de.netbsd.org/pub/NetBSD/NetBSD-8.1/cats/binary/kernel/netbsd-GENERIC.aout.gz</a>
+	<a href="ftp://ftp.de.netbsd.org/pub/NetBSD/NetBSD-8.1/cats/binary/kernel/netbsd-INSTALL.aout.gz">ftp://ftp.de.netbsd.org/pub/NetBSD/NetBSD-8.1/cats/binary/kernel/netbsd-INSTALL.aout.gz</a>
 
 </pre>
   <p>
   <li>Start the installation like this:<pre>
-	<b>gxemul -X -E cats -d nbsd_cats.img -d NetBSD-8.0-cats.iso netbsd-INSTALL.aout.gz</b>
+	<b>gxemul -X -E cats -d nbsd_cats.img -d NetBSD-8.1-cats.iso netbsd-INSTALL.aout.gz</b>
 
 </pre>
 	and proceed like you would do if you were installing NetBSD on a real
@@ -93,10 +96,14 @@
 
 <p>Note that there may be some long delays during bootup.
 
-<p>Alternatively, to install from FTP, you can skip downloading the ISO,
-and start the install without <tt>-d xxxxx.iso</tt>. Suitable network 
-settings are IP 10.0.0.1, gateway/default route 10.0.0.254, netmask 
-255.0.0.0, nameserver 10.0.0.254.
+<p>(NOTE: Older versions of NetBSD could install via FTP in older versions
+of GXemul. Right now, that seems to not be possible, resulting in ethernet
+timeouts etc. Whether it is due to bit rot in the emulator, or due to NetBSD
+having changed over time, has not been debugged.
+If you want to try an FTP install anyway, 
+start the install without <tt>-d xxxxx.iso</tt> and use
+IPv4 address 10.0.0.1, gateway/default route 10.0.0.254, netmask 
+255.0.0.0, and nameserver 10.0.0.254, when asked to configure the network.)
 
 <p>If everything worked, NetBSD should now be installed on the disk image.
 Use the following command line to boot the emulated CATS machine:<pre>
@@ -140,8 +147,6 @@
 	<b>cp ftp.nluug.nl/OpenBSD/4.0/cats/bsd.rd .</b>
 
 </pre>
-	(Replace ftp.se.openbsd.org with a server closer to you, for
-	increased download speed.)
   <p>
   <li>You now need to make an ISO image of the entire directory you downloaded.
 	(I recommend using <tt>mkisofs</tt> for that purpose. If you don't
diff -Nru gxemul-0.6.2/doc/machine_decstation.html gxemul-0.7.0+dfsg/doc/machine_decstation.html
--- gxemul-0.6.2/doc/machine_decstation.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/machine_decstation.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2006-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -113,8 +113,8 @@
 </pre>
 </ol>
 
-<p>NetBSD 8.0 can also be installed, but for some reason, the Xorg server
-is missing after installation, so 7.1.2 is preferred if you want to use X.
+<p>NetBSD 8.x and 9.x can also be installed, but <a href="https://mail-index.netbsd.org/port-mips/2019/06/28/msg000877.html">there is no X server</a>,
+so 7.1.2 is preferred if you want to use X.
 
 <p>If you do not want to use the graphical framebuffer during the 
 install, you can skip the <b><tt>-X</tt></b> command line option.
@@ -169,13 +169,13 @@
 
 </pre>
   <li>Download the entire pmax directory from the ftp server: (approx. 99 MB)<pre>
-	<b>wget -r <a href="ftp://ftp.se.openbsd.org/pub/OpenBSD/2.8/pmax/">ftp://ftp.se.openbsd.org/pub/OpenBSD/2.8/pmax/</a></b>
+	<b>wget -r <a href="https://ftp.nluug.nl/OpenBSD/2.8/pmax/">https://ftp.nluug.nl/OpenBSD/2.8/pmax/</a></b>
 
 </pre>
 
   <li>Execute the following commands:
 <p><table border="0"><tr><td><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt></td><td><pre>
-<b>mv ftp.se.openbsd.org/pub/OpenBSD/2.8/pmax/simpleroot28.fs.gz .
+<b>mv ftp.nluug.nl/OpenBSD/2.8/pmax/simpleroot28.fs.gz .
 gunzip simpleroot28.fs.gz
 chmod +w simpleroot28.fs</b>		&lt;--- make sure
 </pre></td></tr></table>
@@ -183,8 +183,8 @@
 	(I recommend using <tt>mkisofs</tt> for that purpose. If you don't
 	already have <tt>mkisofs</tt> installed on your system, you need
 	to install it in order to do this.)<pre>
-	<b>mkisofs -o openbsd_pmax_2.8.iso ftp.se.openbsd.org/pub/OpenBSD/2.8/pmax</b>
-	<b>rm -rf ftp.se.openbsd.org</b>      <i>(this directory is not needed anymore)</i>
+	<b>mkisofs -o openbsd_pmax_2.8.iso ftp.nluug.nl/OpenBSD/2.8/pmax</b>
+	<b>rm -rf ftp.nluug.nl</b>      <i>(this directory is not needed anymore)</i>
 
 </pre>
   <li>Start the emulator with all three (!) disk images:<pre>
diff -Nru gxemul-0.6.2/doc/machine_hpcmips.html gxemul-0.7.0+dfsg/doc/machine_hpcmips.html
--- gxemul-0.6.2/doc/machine_hpcmips.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/machine_hpcmips.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2006-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -85,7 +85,8 @@
 		<td></td>
 		<td>32 MB</td>
 		<td></td>
-		<td>Graphical framebuffer (-X) is broken with recent versions of NetBSD.</td>
+		<td>Graphical framebuffer (-X) is broken with NetBSD 8.0 but
+			works with 8.1.</td>
 	</tr>
 
 	<tr>
@@ -109,7 +110,8 @@
 		<td></td>
 		<td>32 MB</td>
 		<td></td>
-		<td>Graphical framebuffer (-X) is broken with recent versions of NetBSD.</td>
+		<td>Graphical framebuffer (-X) is broken with NetBSD 8.0 but
+			works with 8.1.</td>
 	</tr>
 
 	<tr>
@@ -121,7 +123,8 @@
 		<td></td>
 		<td>32 MB</td>
 		<td></td>
-		<td>Graphical framebuffer (-X) is broken with recent versions of NetBSD. Unaligned framebuffer; may run a bit slower.</td>
+		<td>Graphical framebuffer (-X) is broken with NetBSD 8.0 but
+			works with 8.1. Unaligned framebuffer; may run a bit slower.</td>
 	</tr>
 </table>
 
@@ -140,14 +143,14 @@
 </pre>
   <li>Download the NetBSD/hpcmips ISO image, a generic kernel,
 	and the installer kernel (and optional symbols):<pre>
-	<a href="ftp://ftp.netbsd.org/pub/NetBSD/iso/8.0/NetBSD-8.0-hpcmips.iso">ftp://ftp.netbsd.org/pub/NetBSD/iso/8.0/NetBSD-8.0-hpcmips.iso</a>
-	<a href="ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-8.0/hpcmips/binary/kernel/netbsd-GENERIC.gz">ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-8.0/hpcmips/binary/kernel/netbsd-GENERIC.gz</a>
-	<a href="ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-8.0/hpcmips/installation/netbsd.gz">ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-8.0/hpcmips/installation/netbsd.gz</a>
-	<a href="ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-8.0/hpcmips/installation/netbsd.symbols.gz">ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-8.0/hpcmips/installation/netbsd.symbols.gz</a>
+	<a href="ftp://ftp.netbsd.org/pub/NetBSD/iso/8.1/NetBSD-8.1-hpcmips.iso">ftp://ftp.netbsd.org/pub/NetBSD/iso/8.1/NetBSD-8.1-hpcmips.iso</a>
+	<a href="ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-8.1/hpcmips/binary/kernel/netbsd-GENERIC.gz">ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-8.1/hpcmips/binary/kernel/netbsd-GENERIC.gz</a>
+	<a href="ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-8.1/hpcmips/installation/netbsd.gz">ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-8.1/hpcmips/installation/netbsd.gz</a>
+	<a href="ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-8.1/hpcmips/installation/netbsd.symbols.gz">ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-8.1/hpcmips/installation/netbsd.symbols.gz</a>
 </pre>
   <p>
   <li>Start the installation like this:<pre>
-	<b>gxemul -X -e mobilepro780 -d nbsd_hpcmips.img -d b:NetBSD-8.0-hpcmips.iso netbsd.gz netbsd.symbols.gz</b>
+	<b>gxemul -X -e mobilepro770 -d nbsd_hpcmips.img -d b:NetBSD-8.1-hpcmips.iso netbsd.gz netbsd.symbols.gz</b>
 
 </pre>
 	and proceed like you would do if you were installing NetBSD on a real
@@ -156,24 +159,35 @@
 	the CDROM device name from <tt>cd0a</tt> to <tt>cd0d</tt>.
 </ol>
 
-<p>While it is possible to install and run NetBSD/hpcmips without the <tt>-X</tt>
-command line option (i.e. using serial console), the default
-<tt>/etc/ttys</tt> file after a full install may not have
-<tt>/dev/console</tt> enabled. In that case, you needed to edit <tt>/etc/ttys</tt>
-<b>before</b> you reboot after the install is finished, to be able to log in.
-
 <p>
 If everything worked, NetBSD should now be installed on the disk image.
 Use the following command line to boot the emulated hpcmips machine:<pre>
-	<b>gxemul -e mobilepro780 -X -d nbsd_hpcmips.img netbsd-GENERIC.gz</b>
+	<b>gxemul -e mobilepro770 -X -d nbsd_hpcmips.img netbsd-GENERIC.gz</b>
+</pre>
 
+<p>NOTE: It seems that the NetBSD installer only activates the graphical console.
+You may need to edit <tt>/etc/ttys</tt> at the end of the install,
+and enable <tt>/dev/console</tt> like this if you wish to be able to log in using serial console:
+
+<pre><i>When the installer says "Exit Install System", select that option to get to a # prompt.</i>
+
+# <b>mount /dev/wd0a /mnt</b>
+# <b>echo 'console "/usr/libexec/getty std.9600" vt100 on secure' >> /mnt/etc/ttys</b>
+# <b>umount /mnt</b>
+# <b>sync</b>
+# <b>halt -p</b>
 </pre>
 
 <p>When you have logged in as <tt>root</tt>, you can use <tt>startx</tt> to
-start X Windows, but there is no mouse or touch support yet so only keyboard input 
-is available. This makes it a bit meaningless to use X.
+start X Windows, but there is <font color="red">no mouse or touch support yet</font>,
+so only keyboard input is available. This makes it a bit meaningless to use X.
 
+<p>If you want to supply raw files such as .tar.gz files as disk images using
+the <tt>-d</tt> command line option, those are accessible as the 'd' partition
+in NetBSD/hpcmips, not c. So for example:<pre>
+	tar zxvf /dev/wd1d</pre>
 
+<p>would extract files if the disk image is a .tar.gz archive.
 
 
 <p><br>
diff -Nru gxemul-0.6.2/doc/machine_luna88k.html gxemul-0.7.0+dfsg/doc/machine_luna88k.html
--- gxemul-0.6.2/doc/machine_luna88k.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/machine_luna88k.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2006-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -45,170 +45,380 @@
 
 
 
-<p>This emulation mode attempts to emulate a Luna 88K workstation. Note that these
-were based on Motorola 88000 processors, not 68000.
+<p>This emulation mode attempts to emulate an OMRON Luna-88K workstation. Note that these
+were based on <a href="https://en.wikipedia.org/wiki/Motorola_88000">Motorola
+88000</a> processors, not 68000.
 
-<p><font color="red">NOTE:</font> The Luna 88K emulation mode is not fully working yet.
-An older OpenBSD/luna88k
-ramdisk kernel can reach userland and be interacted with, and some framebuffer
-output can be seen. Newer kernels, however, panic. Most likely, this is due
-to bugs in the emulator.
+<p>Originally, they ran OMRON's UniOS. But also of historical interest:
+<ul>
+	<li>Carnegie-Mellon University's MACH was partially
+		<a href="https://www.cbronline.com/news/omron_together_with_motorola_donate_40_workstations_to_carnegie_mellon_university/">developed
+		on these machines</a>. Some <a href="http://www.cs.cmu.edu/~jmcm/omron/luna88k.html">source code still exists (luna88k.MK84.tar.Z)</a>
+		but I have not found any ready-to-run binary distribution
+		of MACH/luna88k.
+
+	<p>
+	<li><a href="http://cap-lore.com/CapTheory/upenn/">KeyKOS</a> ran on
+		<a href="http://www.cap-lore.com/CapTheory/KK/88K.html">88K</a>,
+		and in particular
+		<a href="http://cap-lore.com/CapTheory/upenn/NanoKernel/NanoKernel.html#RTFToC21">KeyNIX</a> (a UNIX-layer on top of KeyKOS,
+		supposedly capable of running X11).
+</ul>
 
+<p>In modern times, the only still maintained and freely available operating
+system for these machines is <a href="https://www.openbsd.org/luna88k.html">OpenBSD/luna88k</a>.
 
+<p>GXemul emulates the following devices:
+<ul>
+	<li>88100 CPU  (Only a single CPU works well, up to 4 can be experimented with.)
+	<li>Interrupt controller and parts of the system board
+	<li>Serial console
+	<li>Keyboard and mouse
+	<li>Graphical monochrome framebuffer, 1280 x 1024
+	<li>Lance Ethernet
+	<li>SCSI
+</ul>
 
+<p>well enough to run OpenBSD. It is highly likely that running
+other operating systems (or the original OMRON firmware) will trigger
+bugs of various kinds in the device implementations.
 
-<p><br>
-<a name="openbsdluna88k"></a>
-<h3>OpenBSD/luna88k:</h3>
+<p><b>NOT</b> emulated yet:
+<ul>
+	<li>Front panel LCD display
+	<li>Parallel port
+	<li><i>Color</i> framebuffers
+</ul>
 
-<p><font color="#ff0000">IT DOES <b>NOT</b> WORK YET!</font>
+<!-- TODO: 64 MB luna88k, 112 MB luna88k2, max 256 MB in emulator  -->
 
-<p>These instructions are here mostly for me to remember how to debug/proceed:
+<p><a href="openbsd-luna88k-20210130.png"><img src="openbsd-luna88k-20210130-small.png"></a>
+<a href="openbsd-luna88k-20210209.png"><img src="openbsd-luna88k-20210209-small.png"></a>
+<a href="openbsd-luna88k-20210220.png"><img src="openbsd-luna88k-20210220-small.png"></a>
+<a href="20210328-openbsd-luna88k-inside-openbsd-luna88k.png"><img src="20210328-openbsd-luna88k-inside-openbsd-luna88k-small.png"></a>
+
+<p><small>The last of the screenshots above shows the OpenBSD/luna88k kernel booting
+inside GXemul, compiled inside emulated OpenBSD/luna88k running in GXemul on
+a FreeBSD/amd64 host.</small>
 
-<p>
-Download a RAMDISK kernel:
+<p>There are a couple of ways to run and/or install OpenBSD in the emulator.
 
+<p>
 <ul>
-	<li><a href="https://ftp.eu.openbsd.org/pub/OpenBSD/5.4/luna88k/bsd.rd">https://ftp.eu.openbsd.org/pub/OpenBSD/5.4/luna88k/bsd.rd</a>
-	<li><a href="https://ftp.eu.openbsd.org/pub/OpenBSD/5.9/luna88k/bsd.rd">https://ftp.eu.openbsd.org/pub/OpenBSD/5.9/luna88k/bsd.rd</a>
-	<li><a href="https://ftp.eu.openbsd.org/pub/OpenBSD/6.2/luna88k/bsd.rd">https://ftp.eu.openbsd.org/pub/OpenBSD/6.2/luna88k/bsd.rd</a>
+	<li><a href="#openbsdluna88klive">From a "live" harddisk image</a>
+	<li><a href="#openbsdluna88k">Via network installation</a>
+	<li><a href="#openbsdluna88knfs">With root-on-nfs</a>
+	<li><a href="#openbsdluna88kmp">Experimenting with the MultiProcessor kernel</a>
 </ul>
 
-<p>For 5.4 and below:
+
+
+<p><br>
+<a name="openbsdluna88klive"></a>
+<h3>OpenBSD/luna88k from a "live" harddisk image:</h3>
+
+<p>Kenji Aoyama has made available full harddisk images from a real
+OpenBSD installation. Download the latest such harddisk image and
+<tt>boot</tt> program from
+<a href="http://www.nk-home.net/~aoyama/liveimage/">http://www.nk-home.net/~aoyama/liveimage/</a>,
+and start the emulator like this:
+
+<p>
 <pre>
-	<b>gxemul -e luna-88k 0x20000:0x20:bsd.rd</b>
+	<b>gxemul -e luna-88k -d liveimage-luna88k-raw-20201206.img boot</b>
 </pre>
 
-<p>or for the newer ones:
+<p>To run with a graphical framebuffer, add <tt>-X</tt> to the command line.
 
-<pre>
-	<b>gxemul -e luna-88k bsd.rd</b>
+<p>To shut down the machine gracefully, run <tt>reboot</tt> as root.
+
+
+
+
+<p><br>
+<a name="openbsdluna88k"></a>
+<h3>OpenBSD/luna88k network installation:</h3>
+
+<p>To install OpenBSD, you first need to create an empty harddisk image
+onto which the operating system will be installed:
+
+<p><pre>
+	<b>dd if=/dev/zero of=obsd_luna88k.img bs=1024 count=1 seek=5500000</b>
 </pre>
 
-<p>From 6.0 and newer, bugs are triggered (most likely in GXemul):
+<p>Then download the ramdisk kernel, a regular kernel, and the boot program:
+<ul>
+	<li><a href="https://ftp.nluug.nl/OpenBSD/6.8/luna88k/bsd.rd">https://ftp.nluug.nl/OpenBSD/6.8/luna88k/bsd.rd</a>
+	<li><a href="https://ftp.nluug.nl/OpenBSD/6.8/luna88k/bsd">https://ftp.nluug.nl/OpenBSD/6.8/luna88k/bsd</a>
+	<li><a href="https://ftp.nluug.nl/OpenBSD/6.8/luna88k/boot">https://ftp.nluug.nl/OpenBSD/6.8/luna88k/boot</a>
+</ul>
+
+<p>Start the emulator like this, and install as if you were doing a network
+(http) install on a real machine:
 <pre>
-	panic: amap_wipeout: corrupt amap
+	<b>gxemul -e luna-88k -d obsd_luna88k.img bsd.rd</b>
 </pre>
 
-<p>The 5.9 kernel gets further than 6.0 (reaching userland) when run without graphical framebuffer:
+<p>For networking configuration, enter IPv4 address 10.0.0.1, netmask 255.0.0.0,
+and skip IPv6 configuration. Default route and DNS nameserver should both be 10.0.0.254.
 
-<pre>
-CPU0 is associated to 2 MC88200 CMMUs
-CPU1 is associated to 2 MC88200 CMMUs
-CPU2 is associated to 2 MC88200 CMMUs
-CPU3 is associated to 2 MC88200 CMMUs
-Copyright (c) 1982, 1986, 1989, 1991, 1993
-	The Regents of the University of California.  All rights reserved.
-Copyright (c) 1995-2016 OpenBSD. All rights reserved.  http://www.OpenBSD.org
-
-OpenBSD 5.9 (RAMDISK) #0: Fri Mar  4 23:48:03 JST 2016
-    aoyama@rhea.in.nk-home.net:/w1/o/5.9/src/sys/arch/luna88k/compile/RAMDISK
-real mem = 117440512 (112MB)
-avail mem = 110456832 (105MB)
-mainbus0 at root: OMRON LUNA-88K, 25MHz
-cpu0: M88100 rev 0x3, 2 CMMU
-cpu0: M88200 (16K) rev 0x9, full Icache
-cpu0: M88200 (16K) rev 0x9, full Dcache
-clock0 at mainbus0: MK48T02
-le0 at mainbus0: address 00:00:00:00:00:00
-le0: 32 receive buffers, 8 transmit buffers
-sio0 at mainbus0: 7201a
-siotty0 at sio0 channel 0 (console)
-ws0 at sio0 channel 1[ luna88k sio dev1 write data: TODO ]
-
-wskbd0 at ws0
-fb at mainbus0 not configured
-spc0 at mainbus0
-scsibus0 at spc0: 8 targets, initiator 7
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-spc0: SCSI bus reset
-boot device: &lt;unknown>
-root on rd0a swap on rd0b dump on rd0b
-WARNING: clock lost 281 days -- CHECK AND RESET THE DATE!
-erase ^?, werase ^W, kill ^U, intr ^C, status ^T
-
-Welcome to the OpenBSD/luna88k 5.9 installation program.
-(I)nstall, (U)pgrade, (A)utoinstall or (S)hell? s
-# echo $OBSD
-OpenBSD/luna88k 5.9
-# 
-</pre>
-
-<p>It seems that some versions of OpenBSD had a tiny bug in the framebuffer
-scroll up routine, so it does not contain any loads or stores.
-
-<p>Using a breakpoint
-<tt>-p om1_windowmove</tt> in both OpenBSD 5.9 and 6.2 indicates that 
-5.9 must have been optimized too heavily or had a bug; it loops when trying to copy
-pixels to scroll up the text, but the loop contains "nothing":
+<p><b>NOTE:</b> Doing a network install is currently really really slow.
+It is so slow that it will probably say "stalled" in the download progress
+reporting, but just leave it on and eventually it will have downloaded
+everything.
 
+<p>Finally, once the installation finishes, reboot the emulated machine and
+start again using either the boot loader, or using the regular kernel:
 <pre>
-s001553b8: 64e70001	subu	r7,r7,1
-s001553bc: 61270001	addu	r9,r7,1
-s001553c0: ec4c0004	bcnd.n	eq0,r12,0x001553d0	; &lt;om1_windowmove+0x3b0>
-s001553c4: 59600000 (d)	or	r11,r0,0x0
-s001553c8: f1a08832	set	r13,r0,1&lt;18>
-s001553cc: f562600d	addu	r11,r2,r13
-s001553d0: 60420004	addu	r2,r2,4
-s001553d4: eda9fff9	bcnd.n	ne0,r9,0x001553b8	; &lt;om1_windowmove+0x398>
-s001553d8: 616b0004 (d)	addu	r11,r11,4
-s001553b8: 64e70001	subu	r7,r7,1
-...
+	<b>gxemul -e luna-88k -d obsd_luna88k.img boot</b>
+
+	or
+
+	<b>gxemul -e luna-88k -d obsd_luna88k.img bsd</b>
 </pre>
 
-<p>compared to what it looks like in 6.2:
+<p>Using the boot loader mimics how a real machine would start up OpenBSD
+on the luna88k. Using the regular kernel has the advantage that it includes
+symbols, which are useful when debugging the kernel.
+
+<p>To run with a graphical framebuffer, add <tt>-X</tt> to the command line.
+
+<p>To shut down the machine gracefully, run <tt>reboot</tt> as root.
+
+
+
+
+<p><br>
+<a name="openbsdluna88knfs"></a>
+<h3>OpenBSD/luna88k with root-on-nfs:</h3>
+
+<p>Back when GXemul did not emulate the SCSI controller in the LUNA88K machine,
+the only way to run OpenBSD/luna88k was using root-on-nfs. These instructions
+can still be used, if you want to do it that way.
+
+<p>
+Another emulated machine must then be used as the nfs root server, and the
+emulated LUNA88K machine must boot as a <a href="http://man.openbsd.org/diskless">diskless</a>
+client. To make matters even more complicated, the OpenBSD/luna88k 6.8 RAMDISK
+kernel has support for Ethernet, but it does not seem to have a driver for
+nfs included or at least it doesn't work in the emulator. Therefore, a <i>separate</i>
+OpenBSD ramdisk kernel, e.g. for OpenBSD/sgi, needs to be used to run the final
+step of the root-on-nfs installation.
+
+<p>Let's get started.
+
+<p>
+<ol>
+  <li>First of all, the "<tt>nfs server</tt>" machine must be set up.
+	<a href="machine_decstation.html#netbsdpmaxinstall">Install NetBSD/pmax 8.0 from CDROM</a>,
+	perform a default install (without X11) from CDROM without configuring the
+	network, but add a 4000 MB <tt>/tftpboot</tt> partition when
+	configuring the disk!
+  <p>
+  <li>On the host, download the OpenBSD distribution:
+<p><table border="0"><tr><td><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt></td><td><pre>wget http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/base68.tgz
+wget http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/comp68.tgz
+wget http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/xbase68.tgz
+wget http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/xfont68.tgz
+wget http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/xserv68.tgz
+wget http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/xshare68.tgz
+</pre></td></tr></table>
+  <li>Start the emulation of the DECstation NFS server using this command line:
+<p><table border="0"><tr><td><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt></td><td><pre>gxemul -xe 3max -d nbsd_pmax.img -d base68.tgz -d comp68.tgz -d xbase68.tgz -d xfont68.tgz -d xserv68.tgz -d xshare68.tgz
+</pre></td></tr></table>
+and enter the following commands to configure the server for NFS serving and
+extract the OpenBSD distribution:
+<table border="0"><tr><td><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt></td><td><pre>
+<b>echo hostname=server &gt;&gt; /etc/rc.conf
+echo ifconfig_le0=\"inet 10.0.0.2\" &gt;&gt; /etc/rc.conf
+echo nameserver 10.0.0.254 &gt;&gt; /etc/resolv.conf
+echo 10.0.0.254 &gt; /etc/mygate
+echo /tftpboot -maproot=root -alldirs 10.0.0.3 &gt; /etc/exports
+echo rpcbind=YES &gt;&gt; /etc/rc.conf
+echo nfs_server=YES &gt;&gt; /etc/rc.conf
+echo mountd=YES &gt;&gt; /etc/rc.conf
+echo bootparamd=YES &gt;&gt; /etc/rc.conf
+printf "client root=10.0.0.2:/tftpboot swap=10.0.0.2:/tftpboot/swap\n" &gt; /etc/bootparams
+echo "00:00:0a:10:20:30 client" &gt; /etc/ethers
+echo 10.0.0.3 client &gt; /etc/hosts
+
+cd /tftpboot
+tar xzf /dev/sd1c
+tar xzf /dev/sd2c
+tar xzf /dev/sd3c
+tar xzf /dev/sd4c
+tar xzf /dev/sd5c
+tar xzf /dev/sd6c
+
+tar zxfv var/sysmerge/etc.tgz
+tar zxfv var/sysmerge/xetc.tgz
+
+chmod 1777 tmp
+
+dd if=/dev/zero of=swap bs=1024 count=262144
+
+echo inet 10.0.0.3 > /tftpboot/etc/hostname.le0
+chmod 640 /tftpboot/etc/hostname.le0
+echo 10.0.0.254 > /tftpboot/etc/mygate
+echo nameserver 10.0.0.254 > /tftpboot/etc/resolv.conf
+echo 127.0.0.1 client localhost > /tftpboot/etc/hosts
+
+echo 10.0.0.2:/tftpboot / nfs rw 0 0 > /tftpboot/etc/fstab
+echo 10.0.0.2:/tftpboot/swap none swap sw,nfsmntpt=/swap >> /tftpboot/etc/fstab
+
+halt</b>
+</pre></td></tr></table>
+  <li>Download the OpenBSD/luna88k GENERIC, MULTIPROCESSOR, and RAMDISK kernels:<pre>
+	<a href="http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/bsd">http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/bsd</a>
+	<a href="http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/bsd.mp">http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/bsd.mp</a>
+	<a href="http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/bsd.rd">http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/luna88k/bsd.rd</a>
 
-<pre>
-s001547a4: 64e70001	subu	r7,r7,1
-s001547a8: 61270001	addu	r9,r7,1
-s001547ac: 60420004	addu	r2,r2,4
-s001547b0: eda9fffa	bcnd.n	ne0,r9,0x00154798	; &lt;om1_windowmove+0x398>
-s001547b4: 616b0004 (d)	addu	r11,r11,4
-s00154798: edac003e	bcnd.n	ne0,r12,0x00154890	; &lt;om1_windowmove+0x490>
-s0015479c: f1208832 (d)	set	r9,r0,1&lt;18>
-s00154890: f5021409	ld	r8,r2,r9	; [0xb10c958c]
-s00154894: c7ffffc4	br.n	0x001547a4	; &lt;om1_windowmove+0x3a4>
-s00154898: f500240b (d)	st	r8,r0,r11	; [0xb1087f8c]
-s001547a4: 64e70001	subu	r7,r7,1
 </pre>
+  <li>Create a configuration file called <tt>config_client</tt>:
+<table border="0"><tr><td><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt></td><td><pre>
+<font color="#2020cf">!  Configuration file for running OpenBSD/luna88k diskless with
+!  a NetBSD/pmax machine as the nfs server.
+!
+!  This config file is for the client.</font>
+
+<b>net(
+	add_remote("localhost:12444")   </b>! the server<b>
+	local_port(12445)               </b>! the client<b>
+)
+
+machine(
+	name("client machine")
+	serial_nr(1)
+
+        type("luna88k")
+        subtype("luna-88k")
+	! use_x11(1)
+
+	! For multiprocessor experiments:
+	! ncpus(4)
+        ! load("bsd.mp")
+
+        ! load("bsd.rd")
+        load("bsd")
+)
+</b>
+</pre></td></tr></table>
+	... and another configuration file for the server,
+	<tt>config_server</tt>:
+<table border="0"><tr><td><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt></td><td><pre>
+<b>net(
+	local_port(12444)               </b>! the server<b>
+	add_remote("localhost:12445")   </b>! the client<b>
+)
+
+machine(
+	name("nfs server")
+	serial_nr(2)
+
+        type("dec")
+        subtype("5000/200")
+
+        disk("nbsd_pmax.img")
+)
+</b>
+</pre></td></tr></table>
 
-<p>Note the actual loads and stores to video ram (0xb10.....).
+  <li>Download an OpenBSD/sgi RAMDISK kernel (only used to run MAKEDEV):<pre>
+	<a href="http://ftp.eu.openbsd.org/pub/OpenBSD/6.7/sgi/bsd.rd.IP32">http://ftp.eu.openbsd.org/pub/OpenBSD/6.7/sgi/bsd.rd.IP32</a>
 
-<p>Going back all the way to an old 5.4 kernel allows the framebuffer to 
-be used:
-<pre>
-	<b>gxemul -X -e luna-88k 0x20000:0x20:bsd.rd</b>
 </pre>
 
-<p>
-<a href="20180220-openbsd-luna88k-5.4.png"><img src="20180220-openbsd-luna88k-5.4-small.png"></a>
+  <li>Create a configuration file called <tt>config_client_sgi</tt>:
+<table border="0"><tr><td><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt></td><td><pre>
+<font color="#2020cf">!  Configuration file for running OpenBSD/sgi diskless with
+!  a NetBSD/pmax machine as the nfs server.
+!
+!  This config file is for the client.</font>
+
+<b>net(
+	add_remote("localhost:12444")   </b>! the server<b>
+	local_port(12445)               </b>! the client<b>
+)
+
+machine(
+	name("client machine")
+	serial_nr(1)
+
+        type("sgi")
+        subtype("o2")
+	use_x11(1)
+	memory(1024)
+
+        load("bsd.rd.IP32")
+        ! load("bsd.IP32")
+)
+</b>
+</pre></td></tr></table>
+
+  <li>Boot the "nfs server" and the OpenBSD/sgi
+	"client machine" as two separate emulator instances:<pre>
+	in one xterm:
+	<b>gxemul @config_server</b>
 
+	and then, in another xterm:
+	<b>gxemul @config_client_sgi</b>
 
-<p>The following is not needed in order to experiment with booting OpenBSD,
-but can be interesting nonetheless: Download 
-<a href="https://ftp.eu.openbsd.org/pub/OpenBSD/6.2/luna88k/boot">https://ftp.eu.openbsd.org/pub/OpenBSD/6.2/luna88k/boot</a> and try
+</pre>
+
+  <li>In the emulated OpenBSD/sgi client, type 's' for Shell and run these commands:
+<table border="0"><tr><td><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt></td><td><pre>
+<b>ifconfig mec0 10.0.0.3; route add default 10.0.0.254
+mount -v 10.0.0.2:/tftpboot /mnt
+cd /mnt/dev; ./MAKEDEV all; cd /; umount /mnt
+halt -p</b>
+</pre></td></tr></table>
+  <li>Finally, run the luna88k client:<pre>
+	<b>gxemul @config_client</b>
 
-<pre>
-	<b>gxemul -v -e luna-88k 0x00700000:0x20:0x00700000:boot</b>
 </pre>
+	When asked about root device, enter <tt>le0</tt>.
+</ol>
+
+
+<p><br>
+If you want to run with the graphical framebuffer, uncomment the
+<tt>use_x11(1)</tt> line in <tt>config_client</tt> first.
+Unfortunately, Xorg lacks a driver for <tt>wsfb</tt> in OpenBSD/luna88k
+6.8, which is needed.
+
+<p>You can extract the files
+<pre>./usr/X11R6/lib/modules/drivers/wsfb_drv.la
+./usr/X11R6/lib/modules/drivers/wsfb_drv.so
+</pre>
+<p>from the <a href="http://ftp.eu.openbsd.org/pub/OpenBSD/6.7/luna88k/xserv67.tgz">OpenBSD
+6.7 xserver</a> distribution file, and use them even if the
+rest of the OS is version 6.8. If you have extracted the files above,
+then start X by running <tt>startx</tt>.
 
 
 
 
 
 <p><br>
+<a name="openbsdluna88kmp"></a>
+<h3>OpenBSD/luna88k MultiProcessor experiments:</h3>
+
+<p>You can experiment with the multiprocessor kernel (bsd.mp), with up to
+4 emulated CPUs. It is not as stable as running single-processor, though.
+Also, the emulator itself is not multithreaded, so all CPUs are emulated
+using a single host processor, so a higher number of emulated CPUs means
+a slower total emulation speed.
+
+<p><a href="20210222-openbsd-luna88k-mp-1.png"><img src="20210222-openbsd-luna88k-mp-1-small.png"></a>
+<a href="20210222-openbsd-luna88k-mp-2.png"><img src="20210222-openbsd-luna88k-mp-2-small.png"></a>
+
+<p>Assuming you have done the root-on-nfs setup detailed above, uncomment
+the bsd.mp file in the configuration file, and set ncpus to the
+number of cpus (1 through 4).
+
+<p>If you want to start the emulator from the command line with multiple
+processors, use the <tt>-n</tt> option.
+
 
 
 
diff -Nru gxemul-0.6.2/doc/machine_mvme88k.html gxemul-0.7.0+dfsg/doc/machine_mvme88k.html
--- gxemul-0.6.2/doc/machine_mvme88k.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/machine_mvme88k.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2006-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -44,11 +44,10 @@
 -->
 
 
-
 <p>This emulation mode attempts to emulate a Motorola MVME187 machine.
-Note that these were based on Motorola 88000 processors, not 68000.
-
-
+Note that these were based on
+<a href="https://en.wikipedia.org/wiki/Motorola_88000">Motorola 88000</a>
+processors, not 68000.
 
 
 
@@ -71,7 +70,7 @@
 
 </pre>
   <li>Download the entire mvme88k directory from the ftp server:<pre>
-	<b>wget -np -l 0 -r <a href="ftp://ftp.se.openbsd.org/pub/OpenBSD/4.5/mvme88k/">ftp://ftp.se.openbsd.org/pub/OpenBSD/4.5/mvme88k/</a></b>
+	<b>wget -np -l 0 -r <a href="https://ftp.nluug.nl/OpenBSD/4.5/mvme88k/">https://ftp.nluug.nl/OpenBSD/4.5/mvme88k/</a></b>
 
 </pre>
 
@@ -79,17 +78,17 @@
 	(I recommend using <tt>mkisofs</tt> for that purpose. If you don't
 	already have <tt>mkisofs</tt> installed on your system, you need
 	to install it in order to do this.)<pre>
-	<b>mkisofs -o openbsd_mvme88k_4.5.iso -U ftp.se.openbsd.org/pub/OpenBSD/</b>
+	<b>mkisofs -o openbsd_mvme88k_4.5.iso -U ftp.nluug.nl/OpenBSD/</b>
 
 </pre>
   <li>Copy away the kernel, we'll need it later. But remove the rest of the
 	downloaded tree.<pre>
-	<b>cp ftp.se.openbsd.org/pub/OpenBSD/4.5/mvme88k/bsd .
-	rm -rf ftp.se.openbsd.org</b>
+	<b>cp ftp.nluug.nl/OpenBSD/4.5/mvme88k/bsd .
+	rm -rf ftp.nluug.nl</b>
 </pre>
 
   <li>Start the emulator using this command line:<pre>
-	<b>gxemul -e mvme187old -d obsd_mvme88k.img -d b:openbsd_mvme88k_4.5.iso -j 4.5/mvme88k/bsd.rd</b>
+	<b>gxemul -e mvme187 -d obsd_mvme88k.img -d b:openbsd_mvme88k_4.5.iso -j 4.5/mvme88k/bsd.rd</b>
 
 </pre>
 	and proceed like you would do if you were installing OpenBSD
@@ -268,7 +267,7 @@
 Once the install has finished, the following command should let you 
 boot from the harddisk image:
 <pre>
-	<b>gxemul -e mvme187old -d obsd_mvme88k.img bsd</b>
+	<b>gxemul -e mvme187 -d obsd_mvme88k.img bsd</b>
 </pre>
 
 <p>When asked about root disk, enter <tt><b>sd0</b></tt>.
diff -Nru gxemul-0.6.2/doc/machines/machine_cyclonevh.html.SKEL gxemul-0.7.0+dfsg/doc/machines/machine_cyclonevh.html.SKEL
--- gxemul-0.6.2/doc/machines/machine_cyclonevh.html.SKEL	2019-06-22 18:23:29.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/machines/machine_cyclonevh.html.SKEL	1970-01-01 00:00:00.000000000 +0000
@@ -1,65 +0,0 @@
-
-The <tt>cyclonevh</tt> machine template tries to emulate a
-Cyclone/VH i960 evaluation board.
-
-<p>Its only purpose is to allow experiments with uClinux/i960 binaries.
-
-See <a href="https://web.archive.org/web/20010417034914/http://www.cse.ogi.edu/~kma/uClinux.html">https://web.archive.org/web/20010417034914/http://www.cse.ogi.edu/~kma/uClinux.html</a> for more info.
-
-<p><b>NOTE!</b>
-
-<p>A binary (vmlinux) can be found on this page:
-<br>
-<a href="https://web.archive.org/web/20010417034914/http://www.cse.ogi.edu/~kma/uClinux.html">https://web.archive.org/web/20010417034914/http://www.cse.ogi.edu/~kma/uClinux.html</a>
-
-<p>However, there is also a binary at
-<a href="http://www.uclinux.org/pub/uClinux/ports/i960/">http://www.uclinux.org/pub/uClinux/ports/i960/</a>, which is corrupt;
-it seems to have been uploaded/encoded with the wrong character encoding.
-(At least it is broken as of 2016-04-18.)
-
-<p><b>TODO</b>:
-<br>Everything.
-
-<p>Until there is an ECOFF file loader, the vmlinux binary image may be
-experimented with manually, using the raw file loader.
-
-<pre>
-$ ./gxemul -V -e cyclonevh raw:0xa3c08000:0xb8:0xa3c08020:vmlinux 
-
-GXemul (unknown version)      Copyright (C) 2003-2018  Anders Gavare
-
-  mainbus0
-  |-- cpu0  (25 MHz)
-  \-- ram0  (4 MB at offset 0xa3c00000)
-
-cpu0: raw:0xa3c08000:0xb8:0xa3c08020:/home/debug/emul/i960/vmlinux loaded
-      Raw file: entry point 0xa3c08020
-      loadable chunk at offset 184: vaddr 0xa3c08000, 774924 bytes
-
-GXemul> cp.u 
-0xa3c08020 <- 58a0198c            unimplemented: 88 
-0xa3c08024    64a50294            unimplemented: 100
-0xa3c08028    58a0198d            unimplemented: 88 
-0xa3c0802c    65a50294            unimplemented: 101
-0xa3c08030    09000700            unimplemented: 9  
-0xa3c08034    8c803000            lda               
-0xa3c08038    a3c08000            unimplemented: 163
-0xa3c0803c    090077a4            unimplemented: 9  
-0xa3c08040    08000000            unimplemented: 8  
-0xa3c08044    00000000            unimplemented: 0  
-0xa3c08048    00000000            unimplemented: 0  
-0xa3c0804c    00000000            unimplemented: 0  
-0xa3c08050    8cf03000            lda               
-0xa3c08054    a3c08064            unimplemented: 163
-0xa3c08058    5c80161e            unimplemented: 92 
-0xa3c0805c    5cf01e00            unimplemented: 92 
-0xa3c08060    84041000            unimplemented: 132
-0xa3c08064    0a000000            unimplemented: 10 
-0xa3c08068    74696e69            unimplemented: 116
-0xa3c0806c    00000000            unimplemented: 0  
-GXemul> quit
-</pre>
-
-<p><hr>
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/machines/machine_hp700rx.html.SKEL gxemul-0.7.0+dfsg/doc/machines/machine_hp700rx.html.SKEL
--- gxemul-0.6.2/doc/machines/machine_hp700rx.html.SKEL	2019-06-22 18:23:29.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/machines/machine_hp700rx.html.SKEL	1970-01-01 00:00:00.000000000 +0000
@@ -1,96 +0,0 @@
-
-The <tt>hp700rx</tt> machine template tries to emulate a
-HP 700/RX X-terminal, with an i960CA processor.
-
-<p><b>TODO</b>:
-<br>Everything. <font color="red">NOTHING ACTUALLY WORKS YET.</font>
-These are preliminary notes I am using during development.
-
-<h2>Alternative 1. Use the ROM from your real machine.</h2>
-
-<pre>$ gxemul -V -e hp700rx raw:0xfff80000:0:0xfff8b000:hp700rx-rom.bin
-GXemul (unknown version)      Copyright (C) 2003-2019  Anders Gavare
-
-  mainbus0
-  |-- cpu0  (i960CA, 25 MHz)
-  |-- ram0  (2 MB at offset 0x3fe00000)
-  \-- rom0  (512 KB at offset 0xfff80000)
-
-cpu0: raw:0xfff80000:0:0xfff8b000:hp700rx-rom.bin loaded
-      Raw file: entry point 0xfff8b000
-      loadable chunk: vaddr 0xfff80000, 524288 bytes
-
-GXemul> cp.u 
-0xfff8b000 <- 5c801610            mov      g0,g0        
-0xfff8b004    5c801610            mov      g0,g0        
-0xfff8b008    8c180402            lda      0x402,r3     
-0xfff8b00c    6518c483            sysctl   r3,r3,r3     
-0xfff8b010    8c180403            lda      0x403,r3     
-0xfff8b014    6518c483            sysctl   r3,r3,r3     
-0xfff8b018    8c180404            lda      0x404,r3     
-0xfff8b01c    6518c483            sysctl   r3,r3,r3     
-0xfff8b020    8c180405            lda      0x405,r3     
-0xfff8b024    6518c483            sysctl   r3,r3,r3     
-0xfff8b028    8c183000 001f0002   lda      0x001f0002,r3
-0xfff8b030    5c201e02            mov      2,r4         
-0xfff8b034    6520ca80            modpc    0,r3,r4      
-0xfff8b038    5c083e00            mov      0,sfr1       
-0xfff8b03c    5c003e00            mov      0,sfr0       
-0xfff8b040    8c203000 30000400   lda      0x30000400,r4
-0xfff8b048    5c081604            mov      r4,sp        
-0xfff8b04c    59185e0c            shlo     12,1,r3      
-0xfff8b050    6420c283            modac    r3,r3,r4     
-0xfff8b054    8c803000 c0003800   lda      0xc0003800,g0
-GXemul> quit 
-</pre>
-
-
-<h2>Alternative 2. Use the C2708A X-server binary.</h2>
-
-<pre>$ ./gxemul -V -e hp700rx C2708A 
-</pre>
-
-<p>but the entry point (according to Intel's b.out format) is 0x3fe05000,
-which is wrong. Clearly, the HP 700/RX deduces the entry point some other
-way. For now, one way to load the binary with correct entry point is
-to use the "raw" file loader and specify addresses explicitly:
-
-<pre>$ ./gxemul -V -e hp700rx raw:0x3fe05000:0x2c:0x3fe05094:C2708A 
-GXemul (unknown version)      Copyright (C) 2003-2019  Anders Gavare
-
-  mainbus0
-  |-- cpu0  (i960CA, 25 MHz)
-  |-- ram0  (2 MB at offset 0x3fe00000)
-  \-- rom0  (512 KB at offset 0xfff80000)
-
-cpu0: raw:0x3fe05000:0x2c:0x3fe05094:C2708A loaded
-      Raw file: entry point 0x3fe05094
-      loadable chunk at offset 44: vaddr 0x3fe05000, 1605668 bytes
-
-GXemul> cpu.u 
-0x3fe05094 <- 8c180100            lda      0x100,r3      
-0x3fe05098    6518c483            sysctl   r3,r3,r3      
-0x3fe0509c    5c201e06            mov      6,r4          
-0x3fe050a0    8c683000 c0003000   lda      0xc0003000,r13
-0x3fe050a8    82235000            stob     r4,(r13)      
-0x3fe050ac    5c881e08            mov      8,g1          
-0x3fe050b0    90745000            ld       (g1),r14      
-0x3fe050b4    5cf01e00            mov      0,g14         
-0x3fe050b8    8c183000 001f0002   lda      0x001f0002,r3 
-0x3fe050c0    8c203000 001f0002   lda      0x001f0002,r4 
-0x3fe050c8    6520ca80            modpc    0,r3,r4       
-0x3fe050cc    5c103e00            mov      0,sfr2        
-0x3fe050d0    5c083e00            mov      0,sfr1        
-0x3fe050d4    5c003e00            mov      0,sfr0        
-0x3fe050d8    5c001e00            mov      0,pfp         
-0x3fe050dc    8cf80040            lda      0x40,fp       
-0x3fe050e0    8c0fe040            lda      0x40(fp),sp   
-0x3fe050e4    59185e0c            shlo     12,1,r3       
-0x3fe050e8    6420c283            modac    r3,r3,r4      
-0x3fe050ec    59805e1e            shlo     30,1,g0       
-GXemul> q 
-</pre>
-
-<p><hr>
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/machines/machine_mvme187.html.SKEL gxemul-0.7.0+dfsg/doc/machines/machine_mvme187.html.SKEL
--- gxemul-0.6.2/doc/machines/machine_mvme187.html.SKEL	2019-06-22 18:23:29.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/machines/machine_mvme187.html.SKEL	1970-01-01 00:00:00.000000000 +0000
@@ -1,241 +0,0 @@
-
-The <tt>mvme187</tt> machine is a
-<a href="http://en.wikipedia.org/wiki/VMEbus">VMEbus</a> based machine with a
-<a href="../components/component_m88k_cpu.html">Motorola 88100 CPU</a>.
-
-
-<p><br>
-<a name="openbsdmvme88kinstall"></a>
-<h3>OpenBSD/mvme88k:</h3>
-
-<font color="#ff0000">NOTE: THIS DOES NOT WORK YET! These are preliminary
-instructions on how it may work when the new GXemul framework is
-complete enough.</font>
-
-<p>It is possible to run
-<a href="http://www.openbsd.org/mvme88k.html">OpenBSD/mvme88k</a>
-on the emulated Motorola MVME187 machine.
-
-<p>To install OpenBSD/mvme88k onto an emulated harddisk image, follow these
-instructions:
-
-<p>
-<ol>
-  <li>Create an empty harddisk image, which will be the root disk
-	that OpenBSD installs itself onto:<pre>
-	<b>dd if=/dev/zero of=obsd_mvme88k.img bs=1024 count=1 seek=1900000</b>
-
-</pre>
-  <li>Download the entire mvme88k directory from the ftp server:<pre>
-	<b>wget -np -l 0 -r <a href="ftp://ftp.se.openbsd.org/pub/OpenBSD/4.4/mvme88k/">ftp://ftp.se.openbsd.org/pub/OpenBSD/4.4/mvme88k/</a></b>
-
-</pre>
-
-  <li>You now need to make an ISO image of the entire directory you downloaded.
-	(I recommend using <tt>mkisofs</tt> for that purpose. If you don't
-	already have <tt>mkisofs</tt> installed on your system, you need
-	to install it in order to do this.)<pre>
-	<b>mkisofs -o openbsd_mvme88k_4.4.iso -U ftp.se.openbsd.org/pub/OpenBSD/</b>
-
-</pre>
-  <li>Copy away the kernel, we'll need it later. But remove the rest of the
-	downloaded tree.<pre>
-	<b>cp ftp.se.openbsd.org/pub/OpenBSD/4.4/mvme88k/bsd .
-	rm -rf ftp.se.openbsd.org</b>
-</pre>
-
-  <li>Start the emulator using this command line:<pre>
-	<b>gxemul -e mvme187 -d obsd_mvme88k.img -d b:openbsd_mvme88k_4.4.iso -j 4.4/mvme88k/bsd.rd</b>
-
-</pre>
-	and proceed like you would do if you were installing OpenBSD
-	on a real MVME187. There is a problem with finding the filesystem on
-	the CDROM, since there is no disklabel [and/or because the emulator
-	perhaps does not simulate CDROM TOCs well enough], but it's possible
-	to mount
-	the filesystem using manual intervention. Here is an example of what
-	an install can look like: (user input in <font color="#0000ff"><i>blue italic</i></font>)<pre>
-	CPU0 is associated to 2 MC88200 CMMUs
-	Copyright (c) 1982, 1986, 1989, 1991, 1993
-		The Regents of the University of California.  All rights reserved.
-	Copyright (c) 1995-2008 OpenBSD. All rights reserved.  http://www.OpenBSD.org
-
-	OpenBSD 4.4 (RAMDISK) #19: Sun Aug 10 21:03:44 GMT 2008
-	    root@arzon.gentiane.org:/usr/src/sys/arch/mvme88k/compile/RAMDISK
-	real mem = 67108864 (64MB)
-	avail mem = 56791040 (54MB)
-	mainbus0 at root: Motorola MVME187, 33MHz
-	cpu0: M88100 rev 0x3, 2 CMMU
-	cpu0: M88200 (16K) rev 0x9, full Icache, M88200 (16K) rev 0x9, full Dcache
-	pcctwo0 at mainbus0 addr 0xfff00000: rev 0
-	nvram0 at pcctwo0 offset 0xc0000: MK48T08
-	cl0 at pcctwo0 offset 0x45000 ipl 3: console
-	osiop0 at pcctwo0 offset 0x47000 ipl 2: NCR53C710 rev 2, 66MHz
-	scsibus0 at osiop0: 8 targets, initiator 7
-	osiop0: target 0 ignored sync request
-	osiop0: target 0 now using 8 bit asynch xfers
-	sd0 at scsibus0 targ 0 lun 0: <GXemul, obsd_mvme88k.im, 0> SCSI2 0/direct fixed
-	sd0: 1855MB, 1855 cyl, 16 head, 128 sec, 512 bytes/sec, 3800003 sec total
-	osiop0: target 1 ignored sync request
-	osiop0: target 1 now using 8 bit asynch xfers
-	cd0 at scsibus0 targ 1 lun 0: <GXemul, openbsd_mvme88k, 0> SCSI2 5/cdrom removable
-	vme0 at pcctwo0 offset 0x40000
-	vme0: using BUG parameters
-	vme0: vme to cpu irq level 1:1
-	vmes0 at vme0
-	rd0: fixed, 4096 blocks
-	boot device: <unknown>
-	root on rd0a swap on rd0b dump on rd0b
-	WARNING: clock gained 138 days -- CHECK AND RESET THE DATE!
-	erase ^?, werase ^W, kill ^U, intr ^C, status ^T
-	(I)nstall, (U)pgrade or (S)hell? <font color="#0000ff"><i>i</i></font>
-
-	Welcome to the OpenBSD/mvme88k 4.4 install program.
-
-	This program will help you install OpenBSD. At any prompt except password
-	prompts you can escape to a shell by typing '!'. Default answers are shown
-	in []'s and are selected by pressing RETURN.  At any time you can exit this
-	program by pressing Control-C, but exiting during an install can leave your
-	system in an inconsistent state.
-
-	Terminal type? [vt100] <font color="#0000ff"><i>xterm</i></font>
-
-	IS YOUR DATA BACKED UP? As with anything that modifies disk contents, this
-	program can cause SIGNIFICANT data loss.
-
-	It is often helpful to have the installation notes handy. For complex disk
-	configurations, relevant disk hardware manuals and a calculator are useful.
-
-	Proceed with install? [no] <font color="#0000ff"><i>yes</i></font>
-	Cool! Let's get to it.
-
-	You will now initialize the disk(s) that OpenBSD will use. To enable all
-	available security features you should configure the disk(s) to allow the
-	creation of separate filesystems for /, /tmp, /var, /usr, and /home.
-
-	Available disks are: sd0.
-	Which one is the root disk? (or 'done') [sd0] <font color="#0000ff"><i>sd0</i></font>
-	osiop0: target 0 ignored sync request
-	osiop0: target 0 now using 8 bit asynch xfers
-	Initial label editor (enter '?' for help at any prompt)
-	> <font color="#0000ff"><i>a a</i></font>
-	offset: [0] <font color="#0000ff"><i>63</i></font>
-	size: [3799940] <font color="#0000ff"><i>3500000</i></font>
-	FS type: [4.2BSD] 
-	mount point: [none] <font color="#0000ff"><i>/</i></font>
-	> <font color="#0000ff"><i>a b</i></font>
-	offset: [3500063] 
-	size: [299940] 
-	FS type: [swap] 
-	> <font color="#0000ff"><i>w</i></font>
-	> <font color="#0000ff"><i>q</i></font>
-	No label changes.
-	No more disks to initialize.
-
-	OpenBSD filesystems:
-	sd0a /
-
-	The next step *DESTROYS* all existing data on these partitions!
-	Are you really sure that you're ready to proceed? [no] <font color="#0000ff"><i>yes</i></font>
-	/dev/rsd0a: 1709.0MB in 3500000 sectors of 512 bytes
-	9 cylinder groups of 202.47MB, 12958 blocks, 25984 inodes each
-	/dev/sd0a on /mnt type ffs (rw, asynchronous, local, ctime=Thu Jan  1 16:29:57 2009)
-
-	System hostname? (short form, e.g. 'foo') <font color="#0000ff"><i>test</i></font>
-	Configure the network? [yes] <font color="#0000ff"><i>no</i></font>
-	Password for root account? (will not echo) 
-	Password for root account? (again) 
-
-	Let's install the sets!
-	Location of sets? (cd disk ftp http nfs or 'done') [cd] <font color="#0000ff"><i>disk</i></font>
-	Is the disk partition already mounted? [no] <font color="#0000ff"><i>!mount -t cd9660 /dev/cd0c /mnt2</i></font>
-	osiop0: target 1 ignored sync request
-	osiop0: target 1 now using 8 bit asynch xfers
-	Is the disk partition already mounted? [no] <font color="#0000ff"><i>yes</i></font>
-	Pathname to the sets? (or 'done') [4.4/mvme88k] <font color="#0000ff"><i>/mnt2/4.4/mvme88k</i></font>
-
-	Select sets by entering a set name, a file name pattern or 'all'. De-select
-	sets by prepending a '-' to the set name, file name pattern or 'all'. Selected
-	sets are labelled '[X]'.
-
-	        [X] bsd
-	        [X] bsd.rd
-	        [ ] bsd.mp
-	        [X] base44.tgz
-	        [X] etc44.tgz
-	        [X] misc44.tgz
-	        [X] comp44.tgz
-	        [X] man44.tgz
-	        [X] game44.tgz
-	        [ ] xbase44.tgz
-	        [ ] xetc44.tgz
-	        [ ] xshare44.tgz
-	        [ ] xfont44.tgz
-	        [ ] xserv44.tgz
-	Set name? (or 'done') [bsd.mp] <font color="#0000ff"><i>done</i></font>
-	Ready to install sets? [yes] <font color="#0000ff"><i>yes</i></font>
-	Getting bsd ...
-	100% |**************************************************|  2329 KB    01:21    
-	Getting bsd.rd ...
-	100% |**************************************************|  3150 KB    01:48    
-	Getting base44.tgz ...
-	100% |**************************************************| 87686 KB    11:56    
-	Getting etc44.tgz ...
-	100% |**************************************************|   629 KB    00:14    
-	Getting misc44.tgz ...
-	100% |**************************************************|  2866 KB    00:37    
-	Getting comp44.tgz ...
-	100% |**************************************************| 38869 KB    06:19    
-	Getting man44.tgz ...
-	100% |**************************************************|  6967 KB    01:50    
-	Getting game44.tgz ...
-	100% |**************************************************|  7037 KB    01:16    
-	Location of sets? (cd disk ftp http nfs or 'done') [done] <font color="#0000ff"><i>done</i></font>
-	Start sshd(8) by default? [yes] <font color="#0000ff"><i>yes</i></font>
-	Start ntpd(8) by default? [no] <font color="#0000ff"><i>no</i></font>
-	Saving configuration files...done.
-	Generating initial host.random file...done.
-	What timezone are you in? ('?' for list) [Canada/Mountain] <font color="#0000ff"><i>Europe/Stockholm</i></font>
-	Setting local timezone to 'Europe/Stockholm'...done.
-	Making all device nodes...done.
-	Installing boot block...
-	boot: /mnt/boot
-	proto: /mnt/usr/mdec/bootxx
-	device: /dev/rsd0a
-	cdevice: /dev/rsd0c
-	modifying vid.
-	/mnt/usr/mdec/bootxx: entry point 0x9f0000
-	proto bootblock size 5120
-	room for 64 filesystem blocks at 0x9f1198
-	Will load 2 blocks of size 16384 each.
-	0: 17696
-	1: 17728
-
-	CONGRATULATIONS! Your OpenBSD install has been successfully completed!
-	To boot the new system, enter halt at the command prompt. Once the
-	system has halted, reset the machine and boot from the disk.
-	# <font color="#0000ff"><i>umount /mnt</i></font>
-	# <font color="#0000ff"><i>halt</i></font>
-
-</pre>
-</ol>
-
-<p>
-Once the install has finished, the following command should let you 
-boot from the harddisk image:
-<pre>
-	<b>gxemul -e mvme187 -d obsd_mvme88k.img bsd</b>
-</pre>
-
-<p>When asked about root disk, enter <tt><b>sd0</b></tt>.
-
-<p>No NIC has been implemented yet for mvme187, so there is no network connectivity
-from within the guest OS.
-
-
-
-
-
-<p><hr>
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/machines/machine_testm88k.html.SKEL gxemul-0.7.0+dfsg/doc/machines/machine_testm88k.html.SKEL
--- gxemul-0.6.2/doc/machines/machine_testm88k.html.SKEL	2019-06-22 18:23:29.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/machines/machine_testm88k.html.SKEL	1970-01-01 00:00:00.000000000 +0000
@@ -1,161 +0,0 @@
-<p><a href="machine_testm88k.png"><img src="machine_testm88k-thumb.png"></a>
-
-<p>The <tt>testm88k</tt> machine is a GXemul-specific machine used for simple
-tests. It is based around a
-<a href="../components/component_m88k_cpu.html">Motorola 88100 CPU</a>,
-and some simple devices.
-
-<p>To start the emulator with a binary built for the testm88k machine,
-type:
-<pre>
-	gxemul -e testm88k <i>filename</i>
-</pre>
-
-<p>You may add -V to start in the paused mode, and enter the single-step
-debugger.
-
-<p>Example:
-<pre>
-$ <b>gxemul -V -e testm88k test/FileLoader_A.OUT_M88K</b>
-GXemul (unknown version)      Copyright (C) 2003-2010  Anders Gavare
-
-  mainbus0
-  |-- cpu0  (88100, 50 MHz)
-  |-- ram0  (32 MB at offset 0)
-  |-- fb_videoram0  (15 MB at offset 0x12000000)
-  \-- rom0  (4 MB at offset 0xff800000)
-
-cpu0: test/FileLoader_A.OUT_M88K loaded
-      a.out: entry point 0x000012b8
-      text + data = 4096 + 4096 bytes
-      symbols: 1260 bytes at 0x2000
-      strings: 1070 bytes at 0x24ec
-      13 symbols read
-
-GXemul&gt; <b>cpu0.unassemble</b>
-&lt;_f&gt;      
-0x12b8 &lt;- 67ff0020   subu    r31,r31,0x20 
-0x12bc    27df0010   st      r30,r31,0x10 
-0x12c0    63df0010   addu    r30,r31,0x10 
-0x12c4    58400320   or      r2,r0,0x320  
-0x12c8    58600258   or      r3,r0,0x258  
-0x12cc    243f0014   st      r1,r31,0x14  
-0x12d0    231f0008   st.d    r24,r31,0x8  
-0x12d4    cfffffe7   bsr.n   0x1270          ; &lt;_change_resolution&gt;
-0x12d8    f6c0201f   st.d    r22,r0,r31   
-0x12dc    cbffff89   bsr     0x1100          ; &lt;_my_random&gt;        
-0x12e0    f6c05802   or      r22,r0,r2    
-0x12e4    69b60320   divu    r13,r22,0x320
-0x12e8    6dad0320   mulu    r13,r13,0x320
-0x12ec    cfffff85   bsr.n   0x1100          ; &lt;_my_random&gt;        
-0x12f0    f6d6640d   subu    r22,r22,r13  
-0x12f4    f6e05802   or      r23,r0,r2    
-0x12f8    69b70258   divu    r13,r23,0x258
-0x12fc    6dad0258   mulu    r13,r13,0x258
-0x1300    cfffff80   bsr.n   0x1100          ; &lt;_my_random&gt;        
-0x1304    f6f7640d   subu    r23,r23,r13  
-GXemul&gt; <b>cpu0.registers</b>
-   pc = 0x000012b8  &lt;_f&gt;
-   r0 = 0x00000000     r1 = 0x00000000     r2 = 0x00000000     r3 = 0x00000000
-   r4 = 0x00000000     r5 = 0x00000000     r6 = 0x00000000     r7 = 0x00000000
-   r8 = 0x00000000     r9 = 0x00000000    r10 = 0x00000000    r11 = 0x00000000
-  r12 = 0x00000000    r13 = 0x00000000    r14 = 0x00000000    r15 = 0x00000000
-  r16 = 0x00000000    r17 = 0x00000000    r18 = 0x00000000    r19 = 0x00000000
-  r20 = 0x00000000    r21 = 0x00000000    r22 = 0x00000000    r23 = 0x00000000
-  r24 = 0x00000000    r25 = 0x00000000    r26 = 0x00000000    r27 = 0x00000000
-  r28 = 0x00000000    r29 = 0x00000000    r30 = 0x00000000    r31 = 0x00000ff0
-GXemul&gt; <b>step 6 </b>
-step 0: cpu0: &lt;_f&gt;      
-              0x12b8    67ff0020   subu   r31,r31,0x20
-        =&gt; cpu0.pc: 0x12b8 -&gt; 0x12bc
-        =&gt; cpu0.r31: 0xff0 -&gt; 0xfd0
-
-step 1: cpu0: 0x12bc    27df0010   st   r30,r31,0x10
-        =&gt; cpu0.pc: 0x12bc -&gt; 0x12c0
-
-step 2: cpu0: 0x12c0    63df0010   addu   r30,r31,0x10
-        =&gt; cpu0.pc: 0x12c0 -&gt; 0x12c4
-        =&gt; cpu0.r30: 0 -&gt; 0xfe0
-
-step 3: cpu0: 0x12c4    58400320   or   r2,r0,0x320
-        =&gt; cpu0.pc: 0x12c4 -&gt; 0x12c8
-        =&gt; cpu0.r2: 0 -&gt; 0x320
-
-step 4: cpu0: 0x12c8    58600258   or   r3,r0,0x258
-        =&gt; cpu0.pc: 0x12c8 -&gt; 0x12cc
-        =&gt; cpu0.r3: 0 -&gt; 0x258
-
-step 5: cpu0: 0x12cc    243f0014   st   r1,r31,0x14
-        =&gt; cpu0.pc: 0x12cc -&gt; 0x12d0
-GXemul&gt; <b>cpu0.showFunctionTraceCall = true</b>
-=&gt; cpu0.showFunctionTraceCall: false -&gt; true
-GXemul&gt; <b>continue</b>
-[ cpu0: _change_resolution(800,600,0,0,0,0,0,0,...) ]
-[ cpu0:   _fbctrl_set_x1(800,600,0,0,0,0,0,0,...) ]
-[ cpu0:     _fbctrl_write_port(1,600,0,0,0,0,0,0,...) ]
-[ cpu0:     _fbctrl_write_data(800,600,0,0,0,0,0,0x12f00000,...) ]
-[ cpu0:   _fbctrl_set_y1(600,600,0,0,0,0,0,0x12f00010,...) ]
-[ cpu0:     _fbctrl_write_port(2,600,0,0,0,0,0,0x12f00010,...) ]
-[ cpu0:     _fbctrl_write_data(600,600,0,0,0,0,0,0x12f00000,...) ]
-[ cpu0:   _fbctrl_command(1,600,0,0,0,0,0,0x12f00010,...) ]
-[ cpu0:     _fbctrl_write_port(0,600,0,0,0,0,0,0x12f00010,...) ]
-[ cpu0:     _fbctrl_write_data(1,600,0,0,0,0,0,0x12f00000,...) ]
-[ cpu0: _my_random(1,600,0,0,0,0,0,0x12f00010,...) ]
-[ cpu0: _my_random(0x8eb1badd,258,0,0,0,0,0x96219136,0xe3abd777,...) ]
-[ cpu0: _my_random(0x6c3eea31,258,0,0,0,0,0x96219136,0x9a0bfc0b,...) ]
-[ cpu0: _my_random(0x159ec14d,258,0,0,0,0,0x96219136,0xd96944e7,...) ]
-[ cpu0: _my_random(0x56fc79a1,258,0,0,0,0,0x96219136,0x30a2827b,...) ]
-[ cpu0: _draw_rectangle(381,513,109,185,0xbf37bf3d,0,0x96219136,0x1c9221d7,...) ]
-[ cpu0: _my_random(381,513,109,185,0xbf37bf3d,0,0x96219136,0x1c9221d7,...) ]
-[ cpu0: _my_random(0x93071c91,201,6d,b9,0xbf37bf3d,0,0x96219136,0x2d57546b,...) ]
-[ cpu0: _my_random(0xa2c2692d,201,6d,b9,0xbf37bf3d,0,0x96219136,0x38c76ac7,...) ]
-[ cpu0: _my_random(0xb7525781,201,6d,b9,0xbf37bf3d,0,0x96219136,0x96563e5b,...) ]
-[ cpu0: _my_random(0x19c3031d,201,6d,b9,0xbf37bf3d,0,0x96219136,0x1fd1a3b7,...) ]
-[ cpu0: _draw_rectangle(17,101,481,117,0x90449ef1,0,0x96219136,0xfe6cfccb,...) ]
-[ cpu0:   _my_memset(0x1203b313,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0xfe6cfccb,...) ]
-[ cpu0:   _my_memset(0x1203bc73,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ cpu0:   _my_memset(0x1203c5d3,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ cpu0:   _my_memset(0x1203cf33,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ cpu0:   _my_memset(0x1203d893,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ cpu0:   _my_memset(0x1203e1f3,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ cpu0:   _my_memset(0x1203eb53,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ cpu0:   _my_memset(0x1203f4b3,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-^C
-[ cpu0:   _my_memset(0x1203fe13,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ cpu0:   _my_memset(0x12040773,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ cpu0:   _my_memset(0x120410d3,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ cpu0:   _my_memset(0x12041a33,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ cpu0:   _my_memset(0x12042393,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ cpu0:   _my_memset(0x12042cf3,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ cpu0:   _my_memset(0x12043653,0x90449ef1,0x573,75,0x90449ef1,0,0x96219136,0,...) ]
-[ 100006 steps (1104 steps/second) ]
-GXemul&gt; <b>fb_videoram0.dump 0x3b300</b>
-TODO: parse address expression
-(for now, only hex immediate values are supported!)
-0003b300  00000000 00000000 00000000 00000000  ................
-0003b310  000000f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b320  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b330  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b340  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b350  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b360  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b370  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b380  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b390  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b3a0  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b3b0  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b3c0  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b3d0  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b3e0  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-0003b3f0  f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1  ................
-GXemul&gt; <b>quit</b>
-
-</pre>
-
-<p>
-Source code for this component can be found
-<a href="../doxygen/html/TestM88KMachine_8cc_source.html">here</a>.
-
-<p><br><hr>
-</body>
-</html>
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diff -Nru gxemul-0.6.2/doc/machine_sgi_o2.html gxemul-0.7.0+dfsg/doc/machine_sgi_o2.html
--- gxemul-0.6.2/doc/machine_sgi_o2.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/machine_sgi_o2.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -63,7 +63,7 @@
 	<li>Ethernet, enough to (barely) run OpenBSD and NetBSD with root-on-nfs.
 </ul>
 
-<p>Things not yet emulated include: SCSI, audio.
+<p>Things not yet emulated include: SCSI, audio/video boards, the VICE chipset, ...
 
 <p>This page contains instructions for how to install and run:
 
@@ -257,9 +257,14 @@
 <p><a href="http://www.openbsd.org/sgi.html">OpenBSD/sgi</a>
 can run in GXemul on an emulated O2 (SGI-IP32), with root on NFS.
 
+<p><a href="https://www.openbsd.org/sgi.html">https://www.openbsd.org/sgi.html</a>
+says <i>"The OpenBSD/sgi port was discontinued after the 6.7 release"</i>, but
+it seems that 6.8 is available from the official FTP site anyway.
+
 <p>
 <a href="20050617-openbsd-sgi.png"><img src="20050617-openbsd-sgi_small.png"></a>
 <a href="20181018-openbsd-sgi-o2.png"><img src="20181018-openbsd-sgi-o2-small.png"></a>
+<a href="openbsd-sgi-x-20210220.png"><img src="openbsd-sgi-x-20210220-small.png"></a>
 
 <p>GXemul does not yet emulate the AHC PCI SCSI controller in the O2,
 so it needs to boot via the emulated network.
@@ -275,29 +280,16 @@
 	network, but add a 4000 MB <tt>/tftpboot</tt> partition when
 	configuring the disk!
   <p>
-  <li>On the host, download the OpenBSD distribution, and do some fixup to
-  make it possible to treat the tar files as SCSI disk images:
-<p><table border="0"><tr><td><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt></td><td><pre>wget http://ftp.openbsd.org/pub/OpenBSD/6.4/sgi/base64.tgz
-wget http://ftp.openbsd.org/pub/OpenBSD/6.4/sgi/comp64.tgz
-wget http://ftp.openbsd.org/pub/OpenBSD/6.4/sgi/xbase64.tgz
-wget http://ftp.openbsd.org/pub/OpenBSD/6.4/sgi/xfont64.tgz
-wget http://ftp.openbsd.org/pub/OpenBSD/6.4/sgi/xserv64.tgz
-wget http://ftp.openbsd.org/pub/OpenBSD/6.4/sgi/xshare64.tgz
-gunzip base64.tgz
-gunzip comp64.tgz
-gunzip xbase64.tgz
-gunzip xfont64.tgz
-gunzip xserv64.tgz
-gunzip xshare64.tgz
-dd if=/dev/zero of=/dev/stdout bs=65536 count=1 >> base64.tar
-dd if=/dev/zero of=/dev/stdout bs=65536 count=1 >> comp64.tar
-dd if=/dev/zero of=/dev/stdout bs=65536 count=1 >> xbase64.tar
-dd if=/dev/zero of=/dev/stdout bs=65536 count=1 >> xfont64.tar
-dd if=/dev/zero of=/dev/stdout bs=65536 count=1 >> xserv64.tar
-dd if=/dev/zero of=/dev/stdout bs=65536 count=1 >> xshare64.tar
+  <li>On the host, download the OpenBSD distribution:
+<p><table border="0"><tr><td><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt></td><td><pre>wget http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/sgi/base68.tgz
+wget http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/sgi/comp68.tgz
+wget http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/sgi/xbase68.tgz
+wget http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/sgi/xfont68.tgz
+wget http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/sgi/xserv68.tgz
+wget http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/sgi/xshare68.tgz
 </pre></td></tr></table>
   <li>Start the emulation of the DECstation NFS server using this command line:
-<p><table border="0"><tr><td><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt></td><td><pre>gxemul -xe 3max -d nbsd_pmax.img -d base64.tar -d comp64.tar -d xbase64.tar -d xfont64.tar -d xserv64.tar -d xshare64.tar
+<p><table border="0"><tr><td><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</tt></td><td><pre>gxemul -xe 3max -d nbsd_pmax.img -d base68.tgz -d comp68.tgz -d xbase68.tgz -d xfont68.tgz -d xserv68.tgz -d xshare68.tgz
 </pre></td></tr></table>
 and enter the following commands to configure the server for NFS serving and
 extract the OpenBSD distribution:
@@ -306,38 +298,42 @@
 echo ifconfig_le0=\"inet 10.0.0.2\" &gt;&gt; /etc/rc.conf
 echo nameserver 10.0.0.254 &gt;&gt; /etc/resolv.conf
 echo 10.0.0.254 &gt; /etc/mygate
-echo /tftpboot -maproot=root 10.0.0.1 &gt; /etc/exports
+echo /tftpboot -maproot=root -alldirs 10.0.0.1 &gt; /etc/exports
 echo rpcbind=YES &gt;&gt; /etc/rc.conf
 echo nfs_server=YES &gt;&gt; /etc/rc.conf
 echo mountd=YES &gt;&gt; /etc/rc.conf
 echo bootparamd=YES &gt;&gt; /etc/rc.conf
-printf "client root=10.0.0.2:/tftpboot \\\n swap=10.0.0.2:/tftpboot/swap\n" &gt; /etc/bootparams
+printf "client root=10.0.0.2:/tftpboot swap=10.0.0.2:/tftpboot/swap\n" &gt; /etc/bootparams
 echo "08:20:30:00:00:10 client" &gt; /etc/ethers
 echo 10.0.0.1 client &gt; /etc/hosts
 
 cd /tftpboot
-tar xf /dev/sd1c
-tar xf /dev/sd2c
-tar xf /dev/sd3c
-tar xf /dev/sd4c
-tar xf /dev/sd5c
-tar xf /dev/sd6c
+tar xzf /dev/sd1c
+tar xzf /dev/sd2c
+tar xzf /dev/sd3c
+tar xzf /dev/sd4c
+tar xzf /dev/sd5c
+tar xzf /dev/sd6c
 
 tar zxfv var/sysmerge/etc.tgz
 tar zxfv var/sysmerge/xetc.tgz
 
+chmod 1777 tmp
+
 dd if=/dev/zero of=swap bs=1024 count=262144
 
 echo inet 10.0.0.1 > /tftpboot/etc/hostname.mec0
+chmod 640 /tftpboot/etc/hostname.mec0
+echo 10.0.0.254 > /tftpboot/etc/mygate
 echo nameserver 10.0.0.254 > /tftpboot/etc/resolv.conf
 echo 10.0.0.2:/tftpboot / nfs rw 0 0 > /tftpboot/etc/fstab
-echo 10.0.0.2:/tftpboot/swap none swap sw >> /tftpboot/etc/fstab
+echo 10.0.0.2:/tftpboot/swap none swap sw,nfsmntpt=/swap >> /tftpboot/etc/fstab
 
 halt</b>
 </pre></td></tr></table>
   <li>Download the OpenBSD/sgi GENERIC and RAMDISK kernels:<pre>
-	<a href="http://ftp.openbsd.org/pub/OpenBSD/6.4/sgi/bsd.IP32">http://ftp.openbsd.org/pub/OpenBSD/6.4/sgi/bsd.IP32</a>
-	<a href="http://ftp.openbsd.org/pub/OpenBSD/6.4/sgi/bsd.rd.IP32">http://ftp.openbsd.org/pub/OpenBSD/6.4/sgi/bsd.rd.IP32</a>
+	<a href="http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/sgi/bsd.IP32">http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/sgi/bsd.IP32</a>
+	<a href="http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/sgi/bsd.rd.IP32">http://ftp.eu.openbsd.org/pub/OpenBSD/6.8/sgi/bsd.rd.IP32</a>
 
 </pre>
   <li>Create a configuration file called <tt>config_client</tt>:
@@ -405,16 +401,15 @@
   <li>Finally, run the client again:<pre>
 	<b>gxemul @config_client</b>
 
-</pre>If the root device is not auto-detected, enter <tt>mec0</tt>.
-	Note that booting is <i>very</i> slow, so be patient.
+</pre><p>If the root device is not auto-detected, enter <tt>mec0</tt>.
+
 </ol>
 
 
-<p>Many things are not working yet, for example X11 does not start yet due
-to some bug in the keyboard emulation.
-It is also very slow, mostly due to having the file system on NFS.
-In order to self-compile GXemul under emulated OpenBSD/sgi, you need
-to run <tt>swapctl -a /swap</tt> as root.
+<p>Log in as root, with empty password.
+To start X11, type <tt>startx</tt>.
+Note that the emulation is a bit slow, mostly due to having the file
+system on NFS.
 
 
 
@@ -424,12 +419,22 @@
 <a name="linuxforo2"></a>
 <h3>Linux for O2</h3>
 
-<p><font color="red">NOTE: This does not work yet. The latest Linux r5k-ip32
-kernels die with a NULL reference during bootup. Older versions may work
-better, but I have not had the time to set up NFS netbooting so I don't know
+<p><font color="red">NOTE: This does not work yet. Some old kernels may work,
+but I have not had the time to set up NFS netbooting so I don't know
 whether that would really work, or trigger other bugs.</font>
 
-<p><a href="http://ftp.debian.org/debian/dists/Debian8.11/main/installer-mips/current/images/r5k-ip32/">Linux for O2</a>
+<p>Some kernels (Linux 2.5 and 2.6) from the years 2002 - 2004 can be found here: <a href="https://www.linux-mips.org/~glaurung/">https://www.linux-mips.org/~glaurung/</a>
+<br>Other kernels here: <a href="http://ftp.debian.org/debian/dists/Debian8.11/main/installer-mips/current/images/r5k-ip32/">Debian Linux for O2</a>
+
+<p>Example with <a href="https://www.linux-mips.org/~glaurung/O2/linux-2.5.47/kernel/vmlinux64-r10k">https://www.linux-mips.org/~glaurung/O2/linux-2.5.47/kernel/vmlinux64-r10k</a> (launced using <tt>gxemul -X -e o2 vmlinux64-r10k</tt>):
+
+<p>
+<a href="20190715-sgi-o2-linux.png"><img src="20190715-sgi-o2-linux-small.png"></a>
+
+<p>Another kernel to try could be:
+<a 
+href="http://mirrors.telepoint.bg/debian/dists/stretch/main/installer-mips/20150718/images/r5k-ip32/netboot-boot.img">http://mirrors.telepoint.bg/debian/dists/stretch/main/installer-mips/20150718/images/r5k-ip32/netboot-boot.img</a>
+
 
 
 
diff -Nru gxemul-0.6.2/doc/misc.html gxemul-0.7.0+dfsg/doc/misc.html
--- gxemul-0.6.2/doc/misc.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/misc.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -181,48 +181,52 @@
 <a name="disk"></a>
 <h3>How to start the emulator with a disk image:</h3>
 
-<p>Add <i>-d [prefixes:]diskimagefilename</i> to the command line, where prefixes
-are one or more single-character options. Run <b>gxemul -h</b>
+<p>Add <tt>-d [prefixes:]diskimagefilename</tt> to the command line, where prefixes
+are one or more single-character options. Run <tt>gxemul -h</tt>
 to get a list of possible options.
 
 <p>Here are some examples. If you want to run a <a href="http://www.netbsd.org/ports/pmax/">NetBSD/pmax</a>
 kernel on an emulated <a href="http://en.wikipedia.org/wiki/DECstation">DECstation</a>
 machine, you would use a command line such as this:
 <pre>
-	$ <b>gxemul -e 3max -d pmax_diskimage.fs netbsd-pmax-INSTALL</b>
+	$ gxemul -e 3max <b>-d pmax_diskimage.fs</b> netbsd-pmax-INSTALL
 </pre>
 
 <p>NOTE: For some emulation modes, such as the DECstation mode, you do 
-<i>not</i> actually have to specify the name of the kernel, if the disk 
-image is bootable!
+not actually have to specify the name of the kernel, if the disk 
+image is bootable! Bootblocks are then read from the disk and executed,
+as on a real machine.
 
 <p>It is possible to have more than one disk. For each -d argument, a disk
-image is added; the first will be SCSI target 0, the second will be target 1, and so on,
-unless you specify explicitly which ID number the devices should have.
+image is added; the first will usually (*) be SCSI target 0, the second will be
+target 1, and so on, unless you specify explicitly which ID number the devices should have.
 <pre>
-	$ <b>gxemul -e 3max -d disk0.raw -d disk1.raw -d 5:disk2.raw netbsd-pmax-INSTALL</b>
+	$ gxemul -e 3max <b>-d disk0.raw -d disk1.raw -d 5:disk2.raw</b> netbsd-pmax-INSTALL
 </pre>
 
 <p>Note: In the example above, disk2.raw will get scsi id 5.
 
+<p><small>(*) = One exception is that in the LUNA88K machine, if no id is specified,
+the first disk image gets id 6, the second id 5 and so on.</small>
+
 <p>If a filename has a 'c' prefix, or ends with ".iso", then it is assumed to be
 a CDROM device (this can be overridden with a 'd' prefix, to force a read/write disk).
 For example, the following command would start the emulator with two
 CDROM images, and one harddisk image:
 <pre>
-	$ <b>gxemul -e 3max -d image.iso -d disk0.img -d c:second_cdrom.img netbsd-pmax-INSTALL</b>
+	$ gxemul -e 3max <b>-d image.iso -d disk0.img -d c:second_cdrom.img</b> netbsd-pmax-INSTALL
 </pre>
 
 <p>Usually, the device with the lowest id becomes the boot device. To override
 this, add a 'b' prefix to one of the devices:
 <pre>
-	$ <b>gxemul -e 3max -d rootdisk.img -d bc:install-cd.iso name_of_kernel</b>
+	$ gxemul -e 3max <b>-d rootdisk.img -d bc:install-cd.iso</b> name_of_kernel
 </pre>
 
 <p>If you have a physical CD-ROM drive on the host machine, say /dev/cd0c, you can
 use it as a CD-ROM directly accessible from within the emulator:
 <pre>
-	$ <b>gxemul -e 3max -d rootdisk.img -d bc:/dev/cd0c name_of_kernel</b>
+	$ gxemul -e 3max <b>-d rootdisk.img -d bc:/dev/cd0c</b> name_of_kernel
 </pre>
 
 <p>It is probably possible to use harddisks as well this way, but I would not
@@ -352,6 +356,18 @@
 <p>The .map file is simply a raw bitmap telling which blocks of the 
 overlay file that are in use.
 
+<p>As a short-hand for creating overlay files, running the emulator once
+with those overlay files, and then immediately removing the overlay files,
+the disk image prefix R (uppercase) can be used instead.
+In other words, instead of typing something like:<pre>
+<font color="#4040ff"><b>touch overlay.img overlay.img.map</b>
+gxemul -e ..... -d disk.img <b>-d V0:overlay.img</b>
+<b>rm overlay.img overlay.img.map</b></font>
+</pre>
+one would type:<pre>
+<font color="#4040ff">gxemul -e ..... -d <b>R:</b>disk.img</font>
+</pre>
+
 
 
 
@@ -475,7 +491,7 @@
 	in order to see that it boots up and works, it will not automatically
 	mean that it will behave the same way when you put it back in real
 	hardware again.
-	<li>Most of the legacy modes of GXemul have been designed to
+	<li>Most of the emulation modes of GXemul have been designed to
 	run without the need for a PROM image, for example the load order
 	(or mechanism) used to boot from a CDROM or SCSI disk, so running
 	with actual machine firmware might not really be supported, more
Binary files /tmp/tmpaarp4e17/pWfV7dXnD4/gxemul-0.6.2/doc/model.png and /tmp/tmpaarp4e17/9kW3MclFqY/gxemul-0.7.0+dfsg/doc/model.png differ
diff -Nru gxemul-0.6.2/doc/networking.html gxemul-0.7.0+dfsg/doc/networking.html
--- gxemul-0.6.2/doc/networking.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/networking.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -46,8 +46,9 @@
 <p><br>
 <ul>
   <li><a href="#intro">Introduction</a>
+  <li><a href="#tap">Virtual Ethernet switch using a tap device</a>
   <li><a href="#multihost">Network across multiple hosts</a>
-  <li><a href="#direct_example_1">Direct-access example 1: udp_snoop</a>
+  <li><a href="#direct_example_1">UDP "Direct-access" example: udp_snoop</a>
 </ul>
 
 
@@ -60,10 +61,12 @@
 <a name="intro"></a>
 <h3>Introduction:</h3>
 
-<p>GXemul's current networking layer supports two modes:
+<p>GXemul's current networking layer supports three modes:
 
 <p><ol>
-  <li>A NAT-like layer, which allows guest OSes to access the outside
+  <li>A virtual Ethernet switch built on top of a <i>tap</i> device.
+  <p>
+  <li>A NAT-like emulation layer, which allows guest OSes to access the outside
 	internet world (IPv4 only, so far). When only one machine is being 
 	emulated, the following default values apply to the guest OS:<pre>
 	IPv4 address:			10.0.0.1
@@ -74,19 +77,24 @@
 	networking, since the emulator is just a normal user process
 	on the host.
   <p>
-  <li>A direct-access layer, allowing external tools to read/write raw
-	ethernet packages from/to the emulator.
+  <li>A UDP mode, allowing external tools to read/write raw
+	ethernet packages from/to the emulator via UDP.
 </ol>
 
-<p><i>NOTE:</i> Both these modes have problems. The NAT-like layer is very 
+<p><i>NOTES:</i>
+
+<p>The tap device support was contributed by Jason Thorpe.
+
+<p>The NAT-like layer is very 
 "hackish" and was only meant as a proof-of-concept, to see if networking 
 like this would work with e.g. NetBSD as a guest OS. (If you are 
 interested in the technical details, and the reasons why NAT networking is 
 implemented this way, you might want to read the <a 
 href="technical.html#net"> networking section in the technical 
-documentation</a>.) Because of the obvious limitations with the NAT 
-approach, I have also included support for direct packet access, but this 
-is not designed for security or anything like that.
+documentation</a>.)
+
+<p>The UDP mode is used to connect multiple instances of GXemul in
+an easy way, but it provides no security of any kind.
 
 <p><font color="#ff0000">Use the networking features at your own risk. 
 </font>
@@ -101,15 +109,14 @@
 	in OpenBSD, or <tt>tlp</tt> in NetBSD)
   <li><tt><b>ether</b></tt>, the "fake" experimental ethernet device
 	(documented <a href="experiments.html#expdevices_ether">here</a>)
-  <li><tt><b>le</b></tt>, <a href="http://en.wikipedia.org/wiki/TURBOchannel">Turbochannel</a>
-	Lance Ethernet, as used in DECstation 5000/200 ("3max")
-  <li><tt><b>mec</b></tt>, the SGI O2's ethernet controller
+  <li><tt><b>le</b></tt>, Lance Ethernet, as used in <a href="machine_decstation.html">DECstation 5000/200</a> ("3max") and the <a href="machine_luna88k.html">LUNA88K</a> machines
+  <li><tt><b>mec</b></tt>, the <a href="machine_sgi_o2.html">SGI O2</a>'s ethernet controller
 </ul>
 
 <p>It is not possible to simply attach any of the supported NICs into any
 of the supported emulated machines. Some machines, for example, have a 
 specific NIC in them, others may have a PCI bus where a PCI NIC can be 
-used. This is very much machine-dependent.
+used. This is very much machine-dependent, and implemented on a case-by-case basis.
 
 <p>If you are impatient, and simply want to try out networking in GXemul,
 I would recommend trying out an ftp install of <a
@@ -120,6 +127,92 @@
 
 
 
+<p><br>
+<a name="tap"></a>
+<h3>Virtual Ethernet switch using a <i>tap</i> device:</h3>
+
+<p>The simplest way to emulate a real Ethernet network is using a <i>tap</i>
+device.  In this mode, the emulator disables the simulated NAT and
+direct-access machinery and internally treats all emulated NICs as if
+they are on a single Ethernet switch.  In this mode, packets destined for
+the guest's specific MAC address as well as Ethernet multicast and broadcast
+packets are send to the individual guest instances.  Individual NIC
+emulations may also apply their own multicast filtering; multicast filtering
+is implemented for the DEC 21143 and Lance NICs.
+
+<p>The <i>tap</i> interface on the host can be thought of as an upstream
+link on the virtual Ethernet switch.  In addition to providing a "port"
+for the host, the <i>tap</i> interface can be bridged to a physical Ethernet
+port on the host, allowing the guests to access the host's connected LAN.
+
+<p>Networking services such as DHCP and DNS must be provided either by
+the host or by the host's connected LAN.
+
+<p>Support for the <i>tap</i> device was developed on NetBSD, but should
+also work on FreeBSD, OpenBSD, and Linux hosts.
+
+<p>The easiest way to enable tap device networking is to use the <tt>-L</tt>
+command line option, e.g.:
+
+<p><pre>gxemul -e 3max <b>-L /dev/tap0</b> -d nbsd_pmax.img
+</pre>
+
+<p>Here is a simple example of how to enable it when using configuration
+files:
+
+<p><pre>
+<font color="#2020cf">!  Configuration file for
+!  virtual Ethernet switch networking
+!  using a tap device.</font>
+
+<b>net(</b>
+	<b>tapdev(</b><font color="#ff003f">"/dev/tap0"</font><b>)</b>
+<b>)</b>
+<b>machine(</b>
+	<b>name(<font color="#ff003f">"guest machine"</font>)</b>
+
+	<b>type(<font color="#ff003f">"dec"</font>)</b>
+	<b>subtype(<font color="#ff003f">"5000/200"</font>)</b>
+
+	<font color="#2020cf">!  Add a disk, etc.</font>
+<b>)</b>
+</pre>
+
+<p>Before starting the emulator, you will need to create the <i>tap</i>
+interface on the host.  Here is an example for NetBSD:
+
+<p><pre>
+<b># ifconfig tap0 create up</b>
+</pre>
+
+<p>If you wish to simply network the host and the guests together, then
+simply assign an IP address to the <i>tap</i> interface on the host:
+
+<p><pre>
+<b># ifconfig tap0 10.0.0.254</b>
+</pre>
+
+<p>You can now run a DHCP server on the host for the guests, or you can
+configure the guests manually.
+
+<p>If instead you would like to bridge to the host's connected LAN,
+Here is an example for NetBSD:
+
+<p><pre>
+<b># ifconfig bridge0 create up</b>
+<b># brconfig add tap0 add wm0</b>
+</pre>
+
+<p>Although it <i>is</i> possible to have more than one machine per 
+configuration file, I strongly recommend against it. Please use one 
+configuration file for one emulated machine.  Each configuration file
+must have a unique <i>tap</i> instance, and machines in separate
+configuration files must use bridged <i>tap</i> devices if they wish
+to communicate with each other as if on the same LAN.
+
+<p><small>(The section above is written by Jason Thorpe.)</small>
+
+
 
 <p><br>
 <a name="multihost"></a>
@@ -198,7 +291,7 @@
 
 <p><br>
 <a name="direct_example_1"></a>
-<h3>Direct-access example 1: udp_snoop:</h3>
+<h3>UDP "Direct-access" example: udp_snoop:</h3>
 
 <p>The most basic example of how the simple direct-access system works is a small 
 program in the <tt>experiments/</tt> directory, <tt>udp_snoop</tt>, which simply 
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diff -Nru gxemul-0.6.2/doc/RELEASE.html gxemul-0.7.0+dfsg/doc/RELEASE.html
--- gxemul-0.6.2/doc/RELEASE.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/RELEASE.html	2021-11-27 09:42:23.000000000 +0000
@@ -9,15 +9,14 @@
 
 <!-- 10 lines header.  -->
 
-<h1>Release notes for GXemul 0.6.2</h1>
+<h1>Release notes for GXemul 0.7.0</h1>
 
-<p><i>Copyright (C) 2003-2019  Anders Gavare</i>
+<p><i>Copyright (C) 2003-2021  Anders Gavare</i>
 
 <p><br>GXemul is a framework for full-system computer architecture emulation. 
 Several processor architectures and machine types have been implemented. 
-It is working well enough to allow unmodified
-"guest" operating systems to run inside the emulator,
-as if they were running on real hardware.
+It is working well enough to allow unmodified "guest" operating systems to run
+inside the emulator, as if they were running on real hardware.
 
 <p>The emulator emulates (networks of) real machines. The machines may consist
 of ARM, MIPS, Motorola 88K, PowerPC, and SuperH processors, and various 
@@ -25,65 +24,165 @@
 controllers, ethernet controllers, disk controllers, and serial port 
 controllers.
 
-<p>The documentation <a href="intro.html#emulmodes">lists the machines and
-guest operating systems</a> that can be regarded as "working" in GXemul.
-The first guest operating system that worked in GXemul was
-<a href="machine_decstation.html#netbsdpmaxinstall">NetBSD/pmax</a> on
-an emulated DECstation 5000/200, and that is
-still one of the guest OSes that works best.
 
+<p><br>The changes between release 0.6.3.1 and 0.7.0 include:
+<ul>
+	<li>The <a href="machine_luna88k.html">LUNA-88K machine</a> now has
+		working SCSI emulation. This allows
+		OpenBSD/luna88k to be installed and run using a harddisk image.
+		(Previously, a more complicated root-on-nfs setup had to be used.)
+
+	<p>
+	<li>There is now a shorthand disk image prefix 'R' (uppercase), to reduce
+		the amount of typing when one wants to use a temporary throwaway
+		disk image overlay, that is when one does not want to allow
+		writes to a disk image. Previously, this would require
+		something like:
+<ul style="list-style: none;"><li><pre>
+<font color="#606000"><b>touch overlay.img overlay.img.map</b></font>
+<font color="#4040ff">gxemul -e ..... -d disk.img </font><font color="#606000"><b>-d V0:overlay.img</b></font>
+<font color="#606000"><b>rm overlay.img overlay.img.map</b></font>
+</pre></ul>
+		<p>which now becomes just:
+<ul style="list-style: none;"><li><pre><font color="#4040ff">gxemul -e ..... -d <font color="#008000"><b>R:</b></font>disk.img</font>
+</pre></ul>
+		<p>The difference to using an explicit V: overlay is that the
+		temporary file is
+		removed automatically when the GXemul process exits. A guest
+		operating system will still perceive the disk as writable.
+
+	<p>
+	<li>Networking using a tap device can now be enabled directly on the
+		command line using a new <tt>-L</tt> option. Previously,
+		tap devices could only be enabled when using configuration files.
+
+	<p>
+	<li>A bug has been fixed for MIPS R2000/R3000 when writing to
+		coprocessor 0's ENTRY LO register. This fixes a regression
+		introduced between 0.6.1 and 0.6.2
+		where running <tt>xinit</tt> inside Sprite (on an emulated
+		DECstation) suddenly failed.
+
+	<p>
+	<li>A "mouse grab" mechanism has been implemented for X11 framebuffer
+		windows. Previously,
+		mouse movements occuring inside a framebuffer window were always
+		forwarded to the guest OS. Interaction was akward, in particular
+		due to mouse acceleration being performed by the guest OS.
+		Now, instead, the framebuffer window needs to
+		be clicked in, in order to activate mouse pointer grabbing.
+		When the grab mode is active, mouse movements (and button clicks)
+		are forwarded to the guest OS, and the host's mouse cursor is
+		hidden. Grab mode is released when typing Left CTRL + ALT, or
+		when otherwise changing focus to another X11 window.
+
+	<p>
+	<li>Previously, the behavior when using configuration files was to
+		always start new terminal windows (xterms) for emulated serial
+		I/O ports, similar to the <tt>-x</tt> command line option. This
+		has now been changed, so that new terminal windows are only used
+		if there are <i>two or more machines</i> in the same configuration
+		file. If you still want separate terminal windows to be launched
+		when using a configuration file with a single machine in it, you
+		now need to add <tt>-x</tt> to the command line.
+
+	<p>
+	<li>Some cleanup to make the <tt>-K</tt> command line option work
+		more like it was always supposed to.
+		This option should cause the emulator to show the
+		<tt>GXemul&gt;</tt> debugger prompt whenever
+		the emulated program or guest operating system ends,
+		regardless of whether it was a normal shutdown or some form
+		of error. This is useful for example if you wish to disassemble
+		the code, or inspect register or memory content, at the point
+		of failure. Starting the emulator with <tt>-V</tt> also
+		implicitly sets <tt>-K</tt>. If neither <tt>-V</tt> nor <tt>-K</tt>
+		is used, and the guest OS halts with powerdown or "reboots", the emulator
+		should exit gracefully (for the machine modes where shutdown
+		functionality has been implemented via device support or
+		prom emulation support).
+
+		<p>(There are still many explicit <tt>exit()</tt> calls throughout the
+		code, which over time will need to be manually converted to work
+		with <tt>-K</tt>, but the most common ones are fixed.)
+
+	<p>
+	<li><tt>-T</tt> has been fixed to work the way it was always intended to
+		work, namely to abort immediately on the first load or store
+		to non-existant memory. This is useful in combination with
+		<tt>-K</tt>, for example when implementing new machine modes
+		in the emulator or trying out unsupported guest operating
+		systems that access memory or devices in a not-yet-implemented
+		way.
 
+	<p>
+	<li>Debug messages have traditionally been printed using the rather
+		course-grained <tt>debug()</tt> and <tt>fatal()</tt>
+		functions. Work has now begun to separate this into a number of
+		<i>subsystems</i>, which can have their verbosity levels be
+		individually controlled using the new <tt>verbosity</tt>
+		debugger command. This also standardizes the way debug messages
+		are formatted:
+
+<ul style="list-style: none;"><li><pre>[ machine-and-cpu-path: <font color="brown">subsystem-name</font> <font color="#4040ff">component-or-function-name</font>: text ]</pre></ul>
+
+		<p>Most of the time, not all of these are shown.
+		machine-and-cpu-path, for example, is only shown if the message comes
+		from a context where a CPU is known to cause the message,
+		and there are multiple machines or CPUs being emulated.
+		The [ ] brackets are only shown when intermixing debug messages
+		with serial I/O coming from the emulated program or guest
+		operating system.
+		<p>(There are still a huge amount of <tt>debug()</tt>
+		and <tt>fatal()</tt> calls in the code, especially in the
+		less commonly used code paths.)
 
-<p><br>The most important changes between release 0.6.1 and 0.6.2 are:
+	<p>
+	<li>Output from the emulator is now subtly colorized, to make it
+		easier to quickly interpret the text. This is enabled by
+		launching the emulator with the environment variable
+		CLICOLOR set, or by usign the <tt>-G</tt> command line option.
+		The choice of colors was done to
+		a) be reasonably subtle, and b) work
+		with both light and dark terminal backgrounds.
+		Coloring can be explicitly disabled using <tt>-A</tt> (overriding
+		the presence of CLICOLOR), and
+		it is also disabled when outputting to a non-tty.
+</ul>
 
+<p>The source code has been switched back from C++ to plain C:
 <ul>
-	<li>When writing to mirrored RAM ranges, any dyntrans translations
-		made in either the mirror or the mirrored ranges are
-		now invalidated. This means that an emulated SGI O2 can 
-		now be used with up to 1 GB of RAM when
-		running OpenBSD/sgi as a guest OS. Previously, 256 MB
-		was the maximum amount of emulated RAM possible for
-		the SGI O2.
-		
-	<p>
-	<li>A fix 2018-06-13 (between 0.6.0.1 and 0.6.0.2) for translation
-		invalidation when using larger
-		than 4 KB pages, which made HelenOS/malta run further,
-                caused a regression which broke NetBSD/hpcmips (on VR4121
-                CPUs, which have 1 KB native page size). A bit of cleanup seems
-                to have fixed this, so that both NetBSD/hpcmips and 
-                HelenOS/malta work now.
-
-	<p>
-	<li>Cleanup: The MIPS processor emulation implemented in the
-		"new framework", and the corresponding MIPS machine 
-		modes in the new framework, have been removed. (All
-		meaningful MIPS emulation is in the old framework anyway.)
+	<li>The "new" framework was removed. Instead of two different emulators
+		in the same program, there's just the traditional emulation
+		framework.
 
 	<p>
-	<li>Documentation updates:
+	<li>A C compiler supporting the C99 standard is needed in
+		order to build GXemul.
+
+	<p>
+	<li>For third parties that package GXemul (e.g. for package managing
+		systems used by operating systems or distributions),
+		build scripts may need to be modified:
 	<ul>
-		<li>Each emulated machine now has a <a href="intro.html#emulmodes">page
-			of its own</a> with the guest OSes or other software
-			that may run in that mode, rather than just having a
-			long unsorted list of guest OS installation instructions.
-		<li>Less focus on the "new framework", more focus on the
-			old framework where things actually work.
-		<li>An introduction to <a href="debugging.html">using
-			GXemul as a debugger</a>.
-		<li>A general overhaul to remove old stuff, fix errors,
-			and make things easier to read.
+		<li>The unit tests (<tt>make test</tt>) are gone.
+		<li>The (optional) dependency on Valgrind is gone. It was used for
+			running leak detection during unit test execution, but
+			the unit tests were for the C++ framework.
+		<li>The (optional) dependency on Doxygen is gone. It was used for
+			building documentation of the source code in the
+			C++ framework.
+		<li>Automatic generation of machine and component documentation
+			is gone (<tt>make documentation</tt>).
+		<li>In summary: the <tt>doc/</tt> directory is now just a
+			single level without sub-directories, containing static
+			content; nothing is generated at build time.
 	</ul>
 </ul>
 
 
-
 <p><br>Please read the HISTORY file for more details.
 
-<p>To build the emulator, run the <tt>configure</tt> script, and then run 
-<tt>make</tt>. This should hopefully work on most Unix-like systems, with few
-or no modifications to the source code.
-
 <p>Regarding files in the <tt>src/include/thirdparty/</tt> directory:
 most of these are from other open source projects such as NetBSD. See individual
 source files for details, if you plan to redistribute GXemul in binary form,
@@ -93,7 +192,5 @@
 <a href="http://gavare.se/gxemul/">http://gavare.se/gxemul/</a>.
 
 
-
 </body>
 </html>
-
diff -Nru gxemul-0.6.2/doc/tail.html gxemul-0.7.0+dfsg/doc/tail.html
--- gxemul-0.6.2/doc/tail.html	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/tail.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,5 +0,0 @@
-
-
-<p><br><hr>
-</body>
-</html>
diff -Nru gxemul-0.6.2/doc/technical.html gxemul-0.7.0+dfsg/doc/technical.html
--- gxemul-0.6.2/doc/technical.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/technical.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2004-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -62,13 +62,13 @@
 
 <p><font color="#ff0000">NOTE/TODO: This section is very old.</font>
 
-<p>Running an entire operating system under emulation is very interesting
-in itself, but for several reasons, running a modern OS without access to
-TCP/IP networking is a bit akward. Hence, I feel the need to implement
+<p>Running an entire operating system under emulation can be interesting
+in isolation, but running a modern OS without access to
+TCP/IP networking is a bit akward. Hence, there was a need to implement
 TCP/IP (networking) support in the emulator.
 
 <p>
-As far as I have understood it, there seems to be two different ways to go:
+As far as I have understood it, there seems to be two different methods to go:
 
 <ol>
   <li>Forward ethernet packets from the emulated ethernet controller to
@@ -76,24 +76,18 @@
 	packets on the host's controller, giving them back to the
 	emulated OS. Characteristics are:
 	<ul>
-	  <li>Requires <i>direct</i> access to the host's NIC, which
-		means on most platforms that the emulator cannot be
-		run as a normal user!
+	  <li>Requires access to the host's NIC, e.g. using <tt>/dev/tap</tt>.
 	  <li>Reduced portability, as not every host operating system
 		uses the same programming interface for dealing with
 		hardware ethernet controllers directly.
-	  <li>When run on a switched network, it might be problematic to
-		connect from the emulated OS to the OS running on the
-		host, as packets sent out on the host's NIC are not
-		received by itself. (?)
-	  <li>All specific networking protocols will be handled by the
-		physical network.
+	  <li>Some specific networking protocols will need to be handled by the
+		physical network (or the host).
 	</ul>
   <p>
   or
   <p>
   <li>Whenever the emulated ethernet controller wishes to send a packet,
-	the emulator looks at the packet and creates a response. Packets
+	the emulator looks at the packet and creates an emulated response. Packets
 	that can have an immediate response never go outside the emulator,
 	other packet types have to be converted into suitable other
 	connection types (UDP, TCP, etc). Characteristics:
@@ -122,9 +116,11 @@
 first and second approach, respectively.
 
 <p>
-Since I have choosen the second kind of implementation, I have to write 
-support explicitly for any kind of network protocol that should be
-supported. As of 2004-07-09, the following has been implemented and seems 
+GXemul supports both of the above methods.
+
+<p>
+For the second method mentioned above, as of 2004-07-09, the following
+types of emulated network responses have been implemented and seem 
 to work under at least NetBSD/pmax and OpenBSD/pmax under DECstation 5000/200
 emulation (-E dec -e 3max):
 
@@ -263,11 +259,6 @@
 <a name="devices"></a>
 <h3>Emulation of hardware devices</h3>
 
-<p><font color="#ff0000">NOTE: This section concerns the original ("old")
-framwork. If you are looking for information about how to implement new
-machines and devices using the <i>new framework</i>, then look at new
-<a href="doxygen/html/classComponent.html">Component</a> framework instead.</font>
-
 <p>Each file called <tt>dev_*.c</tt> in the 
 <a href="../src/devices/"><tt>src/devices/</tt></a> directory is
 responsible for one hardware device. These are used from
diff -Nru gxemul-0.6.2/doc/TODO.html gxemul-0.7.0+dfsg/doc/TODO.html
--- gxemul-0.6.2/doc/TODO.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/TODO.html	2021-11-27 09:42:23.000000000 +0000
@@ -19,805 +19,217 @@
 Here are some things, in no specific order, that I'd like to fix or
 implement in GXemul. Some items in this list are perhaps already fixed.
 
-
-
-<p><br>
-<b><a name="new">New framework</a></b>
-
-<p><pre><i>Legend:
-
-[ ] = not started yet, or just planning/thinking about it
-[/] = started, either "on paper" or actual implementation
-[X] = done  (but usually these entries are removed from the TODO list)
-
-------------------------------------------------------------------------
-</i>
-
-  [/]   Intel i960 CPU and machine modes.
-
-	[/]  i960 instruction disassembly.
-		[X]  i960CA
-		[ ]  Other variants.
-
-	[/]  i960 instruction execution.
-		[ ]  Enough to run the HP 700/RX ROM.
-		[ ]  Enough to run uClinux/i960.
-
-  	[ ]  HP 700/RX emulation:
-  		[ ]  Figure out more of the memory map by running the ROM image in the emulator.
-  		[ ]  Interrupt controller(s)?
-  		[ ]  Graphics
-  		[ ]  Serial port(s)
-  		[ ]  Keyboard, mouse, ...
-  		[ ]  Ethernet
-
-  	[ ]  Cyclone/VH i960 evaluation board emulation (for uClinux/i960).
-
-  [ ]	Use std::shared_ptr instead of my own hack (refcount_ptr)?
-
-  [/]   Cache components.
-  
-  	This is hopefully a good way to get started working on GXemul again,
-  	after the long break.
-
-	Sub-tasks: (write unit tests for EACH of these, while going along)
-
-	[/]  State consists of
-	   [/]	size (e.g. 4 KB, or 1.75 MB)
-	   [/]	associativity (1 = direct mapped, 4 = 4-way, 0 = fully associative?)
-	   [/]	cache-line length (e.g. 4 bytes, or 64 bytes, or more)
-	   [ ]	replacement policy: ?
-	   [ ]  write-policy: write-through vs write-back vs copy-back
-	   [ ]	Small memory area (the cache memory) itself, consisting of cache lines.
-		Cache lines are:
-		  [ ]	data
-		  [ ]	tag/index(offset?)
-		  [ ]	valid bit
-		  [ ]   dirty bit
-		  [ ]	PC of last writer?
-
-	[ ]  Implement the addressable data bus interface, but if data is contained
-	     in the cache (the small memory state belonging to the cache component),
-	     do not call the main memory.
-
-	[ ]  How about simulating cycle delays? A read or write in this type
-		of model is not instantaneous, but rather a "request", which may
-		take arbitrary long time to execute and return a result.
-
-	[ ]  If possible, for each cache-line, store statistics:
-		nr of hits (reads, writes)
-		nr of misses (reads, writes)
-		on writes, store the PC of the writer, so that on misses,
-			statistics can be gathered.
-
-	[ ]  Caches should be added _onto_ a cpu. The cpu should first look
-	     for a cache as an address data bus, THEN for a parent.
-
-	     [ ]  The cache must then go downwards TWO steps (../..) to get
-	          past the owning cpu, when trying to reach the mainbus/ram.
-
-	     [ ]  How about multi-level caches that are shared between
-	          CPUs/cores? Think through this.
-
-	Or:
-	
-		machine
-		  mainbus
-		    ram
-		    rom
-		    l2cache0
-		      cpu0
-		        l1icache
-		        l1dcache
-		      cpu1
-		        l1icache
-		        l1dcache
-		    l2cache1
-		      cpu2
-		        l1icache
-		        l1dcache
-		      cpu3
-		        l1icache
-		        l1dcache
-
-	if e.g. a 4-core CPU has each core having its own L1 caches (I and D),
-	but sharing L2 caches between pairs of cores.
-
-	Problem: What if there is hyperthreading, and the hyperthread "cpus"
-	share L1I _AND_ L1D? Then the L1 caches cannot be children of both
-	cpus.
-
-	[ ]  Test with caches attached to M88K and MIPS cpus.
-
-	     [ ]  How about a command line switch (or other command) to
-	     	  quickly turn caches on or off? Or maybe just an optional
-	     	  argument to the machine templates (caches=true or false),
-	     	  but that makes it hard to switch during runtime.
-	     	  (Switching during runtime from no caches to caches is
-	     	  easiest (?), but from caches to non-cached will require cache
-	     	  flushes...)
-
-
-
-  [/]	Improve dyntrans CTRL-C behavior! Abort quicker.
-  	[X]  Implement an abort instruction call
-  		[X]  sync pc should take this kind of abort into consideration.
-	[X]  Rename exceptionInDelaySlot -> exceptionOrAbortInDelaySlot
-	[X]  Get rid of abort_in_delay_slot (handled by abort).
-	[/]  Unit tests for the above (M88K).
-  	[/]  Function call trace -> abort quickly on ctrl-c.
-  		[ ]  There is still a crash bug; try interleaving continue +
-  			CTRL-C + continue + CTRL-C, with trace enabled!
-
-  [ ]  Components! instead of the planned plugin stuff?!
-
-	[ ]  Pretty print of files and disk images:
-		
-		cpu0  (5KE, 100 MHz)
-		\--  file  (netbsd-GENERIC.gz)
-
-		or
-
-		wd0  (ATAPI primary harddisk)
-		\--  image  (cow, netbsd.img)
-
-	Should these be added without digits primarily? And then
-	starting from 1. "file", "file1", "file2" etc. Or is file0
-	better? Just "file" is slightly clearer.
-
-	When adding e.g. a machine with a specific ROM, the ROM file could
-	be looked for in standard places (/usr/blah/share/gxemul/rom/therom.bin,
-	~/.gxemul/rom/therom.bin, ./therom.bin, etc) and if not found anywhere,
-	give an error unless overridden using arguments to the machine template.
-	Like:  gxemul -e "sgi_ip32(prom=my_therom.bin)" netbsd.gz
-
-	New syntax:
-
-		path_to_add_to:component(args)
-
-	or
-		path_to_add_to:filename		args is: "name=filename"
-
-	or
-		filename			cpu0 is the path to add to
-
-	I.e. DON'T make an "attach" command, just use the add command.
-
-	Maybe change it to:
-	
-		add component_type [at existing_component_path]
-	
-	and/or support the colon-style notation as well?
-	
-		add [existing_component_path:]component_type(args)
-
-	or
-	
-		add existing_component_path:filename
-
-	Think about this!!!
-
-	$ gxemul -e testmips netbsd-GENERIC.gz
-	$ gxemul -e testmips netbsd-GENERIC.gz wd0:netbsd.img fb_videoram0:sdl()
-	$ gxemul -e testmips netbsd-GENERIC.gz file(type=raw,vaddr=0xbfc00000,name=prom.bin)
-
-	Same as:
-		add file(name=netbsd-GENERIC.gz) cpu0
-		add disk(name=netbsd.img) wd0
-		add file(type=raw,vaddr=0xbfc00000,name=prom.bin) cpu0
-		add sdl() fb_videoram0
-
-	[ ] What should a component be able to do? [as a plugin]
-		[ ] Attach/load/add
-		[ ] On-early-reset  (clear memory etc)
-		[ ] On-late-reset  (fill memory with file contents etc)
-		[ ] Detach
-		[ ] Monitor changes in component(s)' state
-		[ ] Periodical updates (e.g. framebuffers)
-		[ ] Run in a different thread (pthread multithreading?)
-		[ ] Insert stuff into the event queue (e.g. keyboard keypresses
-			from a framebuffer/keyboard plugin)
-
-	[ ] The Snapshots (the clones) release the plugin connection; the plugins only
-		work on the main tree.
-
-	[ ] Plugins have to be compatible with replaying during reverse execution!
-		(Maybe they should be disconnected while re-executing?)
-
-	[ ] Think about how events should contain changes such as breakpoints,
-		added/removed plugins, etc.
-
-	[ ] Example plugins:
-		[ ] File loaders
-			[ ]  Move these from src/main/fileloaders to
-				src/components/file ...
-			[ ]  raw mode: file(raw(vaddr[,skiplen[,entry]]))
-		[ ] Disk image mappers:  src/components/image
-		[ ] Framebuffer displays
-			[ ] Think about VGA (charcell AND video framebuffer, being able
-				to switch live)
-		[ ] Keyboards (host -> emulated)
-		[ ] Serial controller -> scrollback buffer -> xterm / other window
-			or even connected to stdin/stdout or files or terminals.
-		[ ] Audio (emulated -> host)
-		[ ] Cache statistics viewer.
-
-	[ ]  com0:stdio() should not be needed, if it is the default
-	     choice. com0:null() would disconnect com0 from any output.
-	     stdio() would then have to be a plugin which handles multi-
-	     plexing of multiple outputs, and allows one input serial console.
-
-	[ ]  How about "-X" behavior of the legacy modes? I.e. a machine, which
-	     when run with -X will set up PROM emulation variables so that the
-	     guest OS uses graphics, and without -X to use serial console...
-
-  [/]	The testm88k machine.
-
-	[X]  Implement 88100 instruction disassembly.
-	[X]  Implement basic 88K instruction execution, enough to run
-	     the rectangle drawing demo.
-	[ ]  Framebuffer output?
-		[ ]  Start thinking about the plugin framework, use sdl
-		     for video output!
-
-  [ ]	SPARC64? Would be nice; multithreaded Niagara emulation etc.
-
-  [/]	STEP EXECUTIONS, REVERSE EXECUTION, SNAPSHOTTING, ...
-
-	[ ] Try to get away from using doubles for scheduling! The scheduling
-	    must be made more stable, even in the precense of rounding errors.
-	    See e.g. http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=570899
-
-	[ ] Compact mode trace in the new framework: a column to the right with
-		delta EXCEPT program counter deltas. This allows for instruction
-		trace with one instruction per line, like in the legacy modes.
-
-	[/] Continuous execution forward.
-		[ ]  "Sloppy" accuracy mode: it could be possible to
-		     interleave large chunks even when components "collide"
-		     in time. (This will cause reverse execution support to
-		     be turned off.)
-
-	[ ] step recalculation:
-		[ ] When a component is added to the tree, recalculate its nr of steps!
-		[/] "paused" cpu state, in SMP machines during bootup. (Non-executing components.)
-		    [ ] When a component changes state from paused = true to false,
-		        recalculate its number of steps!
-		[ ] Removing components (at least if the Fastest one is removed) should
-		    also trigger recalculation.
-		[ ] When a component's frequency is changed, recalculate its nr of steps!
-		    (This requires variable write handlers, including inheritance!)
-		    Frequency changes are tricky, especially when it comes to reverse
-		    execution, so think CAREFULLY about this!
-
-	[/] Reverse execution/debugging:
-		[ ]  When running in reverse, debug output should be disabled!
-			(Also, update calls to plugins (e.g. framebuffers) should
-			be disabled, until the target step is reached.)
-		[ ]  Regular saving of state, and limiting the number of such
-		     saves by logarithmic removal.
-		[ ]  Disk image overlays!
-			[ ]  Unit tests.
-		[ ]  In addition to saving state, all modifications done to the
-		     component tree, and e.g. breakpoints, need to be stored
-		     together with their time stamp ("step"). And also all
-		     "external events", of course.
-		     * I.e. if a USB storage device is connected as step 1000, and we're
-		       running in reverse to step 800 to check something, and
-		       then continue again, the default behaviour should be that
-		       at step 1000 the USB device is connected again.
-		     * Or if we run 10 steps, change cpu0.pc, and run 10 more steps,
-		       then running backwards 10 steps could work, but not more?
-		       Think about this!
-		[ ]  Simulation across multiple hosts?
-
-	[ ]  Cycle accurate slowdown? E.g. when simulating a 1 MHz microcontroller,
-		and a TV display, maybe the host is much faster than what is
-		required. The gxemul process could then yield some of its CPU time,
-		just about enough to make the process run at real-time speed.
-		(With warnings printed whenever real-time is not possible, because
-		the host is too slow.) This would be useful for some simulations
-		involving real-world Sound producing devices.
-
-  [/]	NEW DYNTRANS IMPLEMENTATION, ...
-
-	[/]  Basic run loop.
-		[X]  PC to pointers
-			[X]  Dyntrans page allocation
-		[/]  Large chunks is safe vs "single stepping" dyntrans...
-			[ ] Only "size 2" so far, i.e. delay slots. No support for
-			    longer instruction combos have been implemented yet.
-		[/]  Unit tests.
-
-	[ ]  Memory writes => invalidate corresponding dyntrans translation pages!
-	     (needed for full guest OS emulation, and self-modifying code)
-
-	[ ]  Interrupts should be cycle accurate, and affect the cpu's
-	     m_nextIC (and other state, such as processor status registers)
-	     _immediately_.
-
-	[/]  Helpers for CPU implementations:
-		[X]  dyntrans pages?
-		[ ]  pc to dyntrans page lookups? 32-bit and 64-bit
-		[ ]  memory to direct host page lookups, TLB-entry based
-
-	[ ]  For instruction combination implementations, the first thing
-	     checked is whether instr combos is allowed, if not then call
-	     the original function call instead. This makes it possible to
-	     run fast, and then "break slowly" before a hazard.
-
-	[ ]  Try variable-length ISAs early on. Maybe amd64? Or AVR32?
-
-	[ ]  Multi-encoding ISAs, such as MIPS (MIPS16), ARM (Thumb).
-
-		Commands used to compile MIPS16 test programs:
-		mips64-unknown-elf-gcc-4.3.2 -mips16 -O3 urk.c -c
-		mips64-unknown-elf-ld urk.o -o urk -e f -Ttext 0xffffffff80004000
-
-	[ ]  Optional native code generation: Probably don't have time to
-		implement this in the near future; everything else also needs
-		to be prioritized against this feature, so...
-
-	[ ] Instruction cache emulation
-		[ ]  cache component on cpus
-		[ ]  For each emulated instruction, call a stub handler with
-		     the current pc. It is responsible for updating statistics etc.
-		     (Only for cycle accurate emulation, not for sloppy emulation?)
-		     (Or should there be a separate setting for cache vs non-cache
-		     emulation?)
-
-	[ ] Generic bus load/store access:
-		[ ] Pointers to host memory pages, for fast loads and stores:
-			[ ]  host_load and host_store (as before)
-			[ ]  host_load_user and host_store_user (as before,
-			     for those archs that need it, e.g. ARM and M88K?)
-		[ ]  Pointers to handler functions, for:
-			[ ]  device access
-			[ ]  data cache emulation
-			[ ]  breakpoints
-			[ ]  Investigate: http://vm-kernel.org/blog/2009/07/10/qemu-internal-part-2-softmmu/
-			     indicates that QEMU uses similar lookup mechanisms as GXemul, but
-			     uses an additional bit in the looked up page address to indicate
-			     I/O space. Investigate whether this is faster than having a pure
-			     pointer, and a separate lookup when the pointer is NULL!
-
-	[ ] Conditional breakpoints before AND after device accesses!
-
-	[ ] Conditional breakpoints before AND after CPU instruction
-	    execution (somewhat different from generic device access).
-
-  [/]	The MVME187 machine.
-
-	[X]  Loading OpenBSD/mvme88k bsd and bsd.rd executables!
-	     I.e. implement an a.out file loader.
-	[ ]  More initial register contents upon reset: r31 isn't enough for
-	     mvme187. See old machine_mvme88k.cc for details.
-
-		[ ]  Soft PROM emulation, if no PROM file is found.
-			MAYBE implement PROM emulation as a plugin? Like
-
-				attach cpu0:mvmeprom(187)
-
-			or even just:  attach mvmeprom(187)
-			since cpu0 would be the default component.
-
-			The plugin would then be responsible for on-reset
-			behavior, AND handling of PROM calls.
-
-			If a software PROM emulation plugin is used for
-			emulating different boot loaders, then that can be
-			specified as arguments, like:  bootregs=linux or
-			bootregs=netbsd  or similar.
-
-     	[ ]  Ability to load raw files (e.g. PROM).
-	[ ]  Serial controller component.
-	[ ]  Plugin (?) for serial output (i.e. a terminal window), or
-	     posibility to connect to stdin/stdout. Should be enough to
-	     show boot messages.
-	[ ]  Separate 88200 CMMUs? So that the two are really two
-	     separate devices.
-	[ ]  Implement 88K virtual to physical memory translation.
-	[/]  Implement 88100 instruction execution (completely).
-	[ ]  Implement 88110 instruction disassembly (e.g. "graphics" instructions)
-	[ ]  Implement 88110 instruction execution.
-	[ ]  Disk bootblock boot.
-	[ ]  Reimplement everything from the old mvme187 implementation.
-	[ ]  Ethernet :)
-	[ ]  Dyntrans "user memory" implementation for M88K!
-	[ ]  xmem emulation (set transaction registers)
-	[ ]  Instruction trace by using bits of ??IP control regs.
-	[ ]  Breakpoints: How to indicate user space vs supervisor? (Also the
-	    "dump" instruction and other things need this support.)
-	[ ]  Instruction disassembly, and implementation:
-		o)  See http://www.panggih.staff.ugm.ac.id/download/GCC/info/gcc.i5
-		    for some strange cases of when "div" can fail (?)
-		o)  Floating point stuff:
-			+) Refactor all the fsub, fadd, fmul etc. They
-			   are currently quite horribly redundant.
-			+) Exceptions for overflow etc!
-
-  [ ]	Address formats?
-  	"xxxx:yyyy", "xxxx:yyyyyyyy", "zzzzzzzzzzzzzzzz" for amd64, plus i/o ports
-  	"uxxxxxxxx" vs "sxxxxxxxx" for M88K
-	most likely others for "bank select" embedded archs/microcontrollers.
-
-  [ ]	amd64/x86 emulation:
-  	a) Non-dyntrans emulation mode, as a "proof" that CPUs can be implemented
-	   using slow interpretation, and do not need to be complex dyntrans 
-	   implementations. (PC emulation isn't exactly GXemul's niche, anyway,
-	   so it is ok that it is extremely slow. There are other emulators
-	   and virtualizers for users who need a fast x86/amd64 experience.)
-	b) interesting because of mode switches (16-bit, 32-bit, and long 64-bit)
-	c) interseting because of odd address format (non-RISC style)
-	d) interesting because there are lots of guest OSes and other software
-	   to test with
-	e) how about making the name "pc" in CPUComponent overridable? on amd64,
-	   it is either ip, eip, or rip, depending on mode.
-	f) override bus reads/writes, because amd64 transparently allows
-	   unaligned loads/stores.
-
-  [ ]	Memory/bus reads in "no exception" mode (for disasm and memory dumping,
-  	and other things).
-
-  [/]	Symbol registry.
-  	[X]  Add ELF symbols (see end of FileLoader_ELF.cc).
-  	[X]  Load a.out symbols.
-  	[ ]  Include device addresses and hardware registers in the symbol
-  	     registry (as in the legacy Dreamcast mode).
-  	[ ]  Cloning a CPUComponent should also clone its symbol registry!
-  	     Think about serializing symbols...
-
-  [ ]   Make sure that BOTH old and new configuration files work!
-
-  [ ]	Niceness fixes:
-  	[/]  make refcount_ptr&lt;T&gt; support const T as well, so that e.g. code in
-  	     Component::LookupPath can be made to work without a const_cast!
-  	[ ]  avoid exceptions (better to return failure some other way)
-
-  [ ]	Call m_gxemul->GetRootComponent()->FlushCachedState(); when a component
-  	is e.g. moved or copied?  Example: cpu0 in machine0 is moved to machine1,
-  	and then cpu.dump is executed. It should then use the mainbus of machine1,
-  	not machine0!  (Maybe not necessary for interactive use; FlushCachedState
-  	is called by consoleui before very command... hm.)
-
-  [ ]	Cache short path names if evaluation/generation of them becomes too heavy.
-
-  [/]	Mainbus component:
-	[ ]  Maybe this should simply be a "Bus" base class? That way,
-	     it could be reused by PCI Busses, VME busses, and others. HOWEVER,
-	     the concept of address range and overlap may differ between
-	     bus types, or maybe not even exist in some busses.
-	[ ]  AddressDataBus should be extended to allow for direct
-	     page mapping.
-	[ ]  Unit tests for the above!
-
-  [ ]	Interrupt subsystem
-   	[ ]  Components exposing an InterruptPin interface? Think about this...
-
-  [ ]	Timers
-	[ ]  Host speed approaching timers:  a device that wishes
-	     to cause interrupts 100 times per emulated second
-	     will interrupt (approximately) 100 times per host
-	     second. This is most useful for running full guest
-	     operating systems at full speed, "virtual machine"
-	     mode.
-	[ ]  Exact emulation:  a device wishing to cause 100
-	     interrupts per emulated second may take much more
-	     or much less than one host second to execute.
-	     ("Cycle accurate" mode.)
-
-   [/]  State/model:
-        [X]  Variable write handlers.
-             [ ] root.step to move to a certain execution step!
-             	 [X] Change backward-step to set root.step = root.step - 1.
-             	 [ ] Only allow decreasing root.step if snapshots are enabled.
-             	 [ ] Allow increasing root.step always: it means to continue until
-             	     the number of steps have been executed (a kind of specia breakpoint!)
-             	 [X] Do not allow writes to *.step for non-root components!
-             	 [X] Do not check writes to *.step during deserialization!
-	     [X] cpu.model = "R4000"   <==  assigning to the "model" variable should:
-	  	[X]  handle writes specifically
-	  	[X]  lookup if R4000 is a valid model for the cpu architecture
-	  	[ ]  Better error reporting when supplying model using e.g.
-	  	     the command line   -e "testmips(cpu=R1000)"  should show
-	  	     the same error message as when running cpu.model="R1000".
-	[ ]  MIPS ABI selection now works (cpu.abi="o32" vs n32 and n64). However,
-	     only the NEW names are registered as state variable names! How should
-	     this be handled? Custom "aliasing" variables?
-	[ ]  Custom ToString variants? Useful for bit fields, control
-	     registers, etc. "Verbose tostring"?
-	[ ]  Loaded files should be part of state/model! But not part
-	     of the component tree. I.e. state = components +
-	     other configuration!
-	[ ]  Disk images: reverse execution should reverse disk contents,
-	     i.e. overlays must be used if reverse execution support is
-	     enabled.
-
-  [ ]	Serialize symbols
-
-  [ ]	Serialize breakpoints
-
-  [ ]	File loaders:
-   	[ ]  automagic .gz (and .bz2) file extraction into /tmp or $TMP or such.
-	[ ]  symbol handling, line number info, data types?
-	[ ]  argument handling! (arg count, at least)
-	[ ]  all the others (macho, ecoff, srec, ...)
-
-  [ ]  Disk images.
-	[ ]  r vs R modifier: read only disk images causes writes to
-	     fail, while R could create an implicit empty overlay
-	     in the tmp directory, so that writes within a session
-	     will succeed. At reboot/reset they'd be lost.
-	[ ]  Make sure that there is either
-		a) a sync after each write to make sure that the data is
-		   consistently written, or that
-		b) (for the test devices at least, or perhaps some others)
-		   a mechanism is available to turn off the write-after-every-access
-		   policy but then the data must be manually synched by the
-		   guest OS every now and then.
-	     (This will be a requirement for e.g. a persistent Single
-	     Storage guest OS.)
-
-  [ ]	Breakpoints
-
-	Breakpoint = some form of expression, which will be evaluated
-	after (or before?) running each cycle. (*)
-	
-	(*) Implementation-wise, it may be optimized away, but the semantics
-	should be this.
-
-	NOTE: It will not be possible to break INSIDE a component's step,
-	but only before or after all components within that step have
-	executed. I.e.:
-	o) when single-stepping, the breakpoint may simply set a flag during
-	   execution, and when all components within that step have executed,
-	   the resulting triggered breakpoints may be displayed.
-	o) when running continuously, the breakpoint may still not break immediately
-	   (?) because components may be mixed within the last step? TODO: Think
-	   about this.
-
-	TODO: Any state variable change in any component? How about RAM/custom
-	changes? How about register _READS_ or custom reads.
-
-	All Load/stores to virtual addresses?
-
-	[ ]  For all breakpoints, it should be possible to break
-	     both _before_ and _after_ a change has occurred!
-
-	[ ]  For all breakpoints/watchpoints, a Count should be kept, and the
-	     emulation should only break once the Count has reached a limit.
-	     (Usually 1, but should be possible to set to any positive value.)
-
-	[ ]  Worst case: Checked on device cycle execution, if necessary.
-
-	[ ]  Per memory-mapped/addressable device
-	     Checked on load/store device access.
-
-	[ ]  Per instruction (for CPU components)
-	     It may be easiest to simply turn off native code
-	     generation, except for stuff like "check if pc = xyz"-
-	     style breakpoints. Those can be embedded.
-
-   [/]  Function call trace etc.
-   	[ ]  string lookup for args
-   	[ ]  symbol lookup for args
-   	[ ]  Document in doc/components/component_cpu.html how to use
-   	     tracing, what the showFunction* state variables do, etc.
-   	[ ]  trace command (taking an argument: nr of calls, default is 1?)
-   		which is the same as setting a breakpoint for cpuX.nrOfFunctionCalls = Z
-   		where Z is one more than before than it was before running the command.
-   		And each function call increases that variable.
-   		trace then temporarily turns on showFunctionTraceCall and
-   		runs until the breakpoint hits (or CTRL-C), and then removes
-   		the breakpoint automatically (even if CTRL-C was hit), and
-   		restores showFunctionTraceCall.
-	     Variants:	trace on	turns on tracing for all CPUs (but doesn't
-	     				run anything)
-	     		trace off	turns off tracing for all CPUs
-	     		trace [n]	runs with trace enabled for n function calls,
-	     				n = 10 by default?
-	     showFunctionCallReturn should be false by default.
-	[ ]  -t command line option, for backward compatibility?
-
-   [ ]  Stack dump (of the emulated machine)
-   	[ ]  A method on CPU components?
-
-   [ ]	Components (general):
-	[ ]  "help" about components could show a file:/// link to
-	     the installed documentation about that component or
-	     machine! (If it exists.)
-	[ ]  Limit where components can be added. Like "drop targets"?
-		E.g. a machine can be added at the root, but a machine can not
-		be added on a pcibus. Similarly, a pcibus can not be added
-		at the root. It has to be in a machine of some kind.
-		Think about this. Perhaps as simple as a "if parent class is
-		not blah blah then disallow adding".
-			A machine can be added into a dummy component.
-			A dummy component can be added into a dummy component.
-			A pcibus can be added into a mainbus (in a machine.)
-			etc.
-		bool IsItOkToAddItToThisProposedParentComponent(propsedParent) const;
-	[ ]  Exceptions/traps to CPUs, could perhaps be generalized to sending
-	     "messages" or "interrupts" to any device/component. How should this
-	     be done manually from the command interpreter?
-	       cpu0.break              cause a breakpoint exception? if the cpu supports it
-	       cpu0.exception [args]   where args is VERY dependent on the exception
-
-  [ ]	ConsoleUI and/or CommandInterpreter: Make use of COLUMNS environment variable
-	when printing e.g. tab completion tables.
-
-  [ ]	Command interpreter:
-
-	[/]  State variable assignments:
-		[ ]  Expression evaluator, +-*/, string concatenation, type
-		     correctness (e.g. bool vs int), hex vs decimal,
-		     prefixes like M, K etc.  (4M = 4*1048576 ...)
-			(StateVariable::EvaluateExpression)
-		[ ]  Execution of _expressions_, not just variables. e.g.:
-			cpu.pc		prints the pc value
-			cpu.pc+4	should print the _expression_ pc+4
-			cpu.pc=expr	assignment
-
-	[ ]  Minimal paths ala machine0.cpu0 would be cool if they worked.
-	     I.e. if there's machine0.mainbus0.cpu0 and machine1.mainbus0.cpu0,
-	     but no mainbus1, then machineX.cpu0 would be shorter, and still
-	     uniquely identify the cpu.
-
-	[ ]  Help on methods and method arguments? E.g. cpu.unassemble [addr]
-
-	[ ]  Right now, entering a command such as "c" says "unknown command".
-	     It should say "ambigous command"!
-
-	[/]  Tab completion for everything:
-
-		[ ]  tab completion should use the Shortest Path, not the
-		     full path. E.g.:  cpu + TAB should expand to cpu0 only
-		     in a default testm88k machine, NOT root.machine0.mainbus0.cpu0!
-		     This will most likely require a change in unit tests etc.
-
-		[ ]  syntax based completion? e.g.:
-			help [cmd]   tab completes the first argument as a
-				     command
-			add component-name		-- component name
-			load [filename [component-path]]  -- filename etc.
-
-		     This will require a uniform way of describing arguments,
-		     and whether or not they should be optional. The tab
-		     completer must then parse the command line, including
-		     figuring out which arguments were optional, etc.
-
-		     Also, when such syntax is taken into account, the
-		     CommandInterpreter can check syntax _before_ running
-		     Command::Execute. That means that individual Commands
-		     do not have to do manual checking on entry that the
-		     number of arguments is correct etc.
-
-			[ ]  filename
-			[ ]  command name
-			[ ]  component path
-			[ ]  optional vs mandatory args...?
-			[ ]  scan all commands' args at startup, and have an
-				assert() in place, so that unknown arg types
-				are caught during development!
-
-	[ ]  Command aliases? e.g.
-		d = cpu0.dump
-		c = continue
-		s = step
-		u = cpu.unassemble
-	     But maybe the cpu in question may be changed with a "focus" command?
-	     Otherwise it would only work with 1 cpu.
-
-	[ ]	recursive component.var
-			Dumps a tree of the "var" variable _FROM_ the component,
-			i.e. including all children. E.g.
-			recursive mainbus0.memoryMappedAddr
-			would dump
-				mainbus0
-				|-- ram0  memoryMappedAddr = 0
-				|-- rom0  memoryMappedAddr = 0x1fc00000
-				\-- com0  memoryMappedAddr = 0x190003f8
-			or something.
-
-	[ ]	recursive component.var = value
-			would set the "var" variable in the component including
-			all sub components. Not all components may have the
-			variable, so debug output should indicate which variables
-			were set and which were not set.
-
-   [/]	RAM component:
-	[ ]  Make the save/load of state more efficient. Right now, it's a hex dump! Yuck.
-	[ ]  methods for searching for values (strings, words, etc?)
-	[ ]  methods for bulk fill/copy [from other address/data busses?]
-	[ ]  "put" command.
-
-   [ ]	Floating point helper.
-
-	Make this more complete/accurate than the old one, i.e. support
-	inf/nan, exceptions, signaling stuff, denormalized/normalized?
-
-	[ ]  non-IEEE modes (i.e. x86/vax/...)?
-	[ ]  Unit tests
-
-   [ ]	Userland emulation
-
-   	[ ]  Begin with e.g. FreeBSD/amd64, or FreeBSD/alpha, NetBSD/something,
-   	     or Linux/something.
-	[ ]  Try to prefix "/emul/mips/" or similar to all filenames,
-	     and only if that fails, try the given filename.
-             Read this setting from an environment variable, and only
-             if there is none, fall back to hardcoded string.
-	[ ]  File descriptor (0,1,2) assumptions? Think about this.
-	[ ]  Dynamic linking! (libs from /emul/xxxx etc)
-	[ ]  Initial register/stack contents (environment, command line args).
-	[ ]  Return value (from main).
-	[ ]  mmap emulation layer
-	[ ]  errno emulation layer
-	[ ]  ioctl emulation layer for all devices :-[
-	[ ]  struct conversions for many syscalls
-</pre>
-
+<ul>
+	<li><a href="#shortlist">Current "short-list" (unsorted)</a>
+	<li><a href="#cpu">CPU related</a>
+	<li><a href="#machine">Machine/device related</a>
+	<li><a href="#misc">Misc.</a>
+	<li><a href="#release">Release checklist</a>
+</ul>
 
 
 
 <p><br>
-<b><a name="original">Original/old/legacy framework</a></b>
+<b><a name="shortlist">Current "short-list" (unsorted)</a></b>
 
-<p><pre>Debugger:
-	Extend the
-		put [b|h|w|d|q] addr, data    modify emulated memory contents
-	command with a "s" (string) mode, where data is a string. Also
-	"z" which puts a nul-terminated string in memory. It should put the
-	string there one byte at a time.
-	
-		put s 0x80008000, "apa"
+<p><pre>
+<font color="blue">bool-ify stuff:</font>
+	o) int -> bool for things like cpu->running
+
+<font color="blue">debugmsg-related and non-exit(1) stuff (mostly):</font>
+	o) src/cpu/:
+		o) debugmsg:ify at least 'cpu' and 'exception' subsystem messages.
+		o) Fix some more exit(1) calls to cpu->running = false and make
+			sure that they break out of the dyntrans loop.
+	o) src/net/:
+		o) debugmsg:ify all src/net/.
+	o) Add an example of the "verbosity" command to the Debugger section of
+		the documentation?
+		Or wait until breakpoints are implemented?
+		e.g. verbosity disk debug		<-- print all messages, but
+		     breakpoint subsystem disk warn	<-- break only for warn and error.
+
+<font color="blue">Build problems:</font>
+	o) Building a default build on my Linux machine currently fails with duplicate definitions from
+		Linux' bits/socket.h being "extern inlined" twice? (configure --debug works fine though)
+
+<font color="blue">Misc.:</font>
+	o) Try X11 grabbing with multiple host displays? ssh with X11 forwarding from laptop?
+		with multiple mouse pointers, _which_ mouse pointer is grabbed?
+	o) Try all guest OSes in the documentation, cleaning up debugmsg related stuff as I go along.
+	o) Instead of doing cpu->running = 0 in some places, and foreach cpu in the machine
+		in some other places, then the main emul loop should check if ANY
+		cpu goes from running to non-running, and treat that as a reason to
+		halt the machine. there's really no reason to continue running the
+		other CPUs if there was an error in one of them.
+		ALSO: if about to enter single step, or single step, is true, then
+			abort too.
+		AND: if support for debugmsg breakpoints is to be added later,
+			then the break-out-of-dyntrans check needs to be done
+			not only on memory references, but potentially after
+			ALL debugmsg printouts!
+	o) Apply Chris Berry's patch for tap device use on Linux.
+	o) Try tap networking on FreeBSD host (e.g. using netbsd/pmax guest).
+		Performance better than when using simulated NAT?
+	o) Breakpoints etc:
+		Helper for setting/adding the break-out-of-dyntrans value to ninstr.
+			cpu_dyntrans_abort_loop(cpu)?
+		Debugmsg breakpoint should then:
+			call cpu_dyntrans_abort_loop(cpu) if cpu != NULL,
+			set about-to-enter-single-step
+			print "subsystem breakpoint" for non-errors,
+			print "aborting" for errors.
+		ABORT_DT =   ninstr & XXX
+		if (ABORT_DT) { SYNCH_PC; next ic = nothing; }
+		step/continue after hitting a breakpoint must work.
+		counts for breakpoints, only break "after x hits".
+		CTRL-T should print breakpoint counts.
+		-T can be implemented as a "warning level breakpoint" for the
+			memory subsystem.
+		-K should implicitly be set if any breakpoints (subsystem 
+			or regular) are used.
+		Always break on debugmsg errors!
+		Document the break-out-of-dyntrans mechanism.
+	o) When using e.g. "-E alpha" and there was more than one subtype, then _list_
+   	   them instead of just complaining "Maybe you forgot the -e command line option".
+	o) Try using profil() for very basic runtime profiling?
+	o) GXsatellite -- Gavare's eXperimental Stand-Alone Test Environment
+	   for Low-Level Interactive Testing of Emulators. base on YCX5; start with testmips.
+</pre></p>
 
-	or
-
-		put z 0x80008000, "apa"
 
 
-	Extend the debugger with a "find" command as well, similar to
-	put but with a range?
-
-		find [b|h|w|d|q|s|z] startaddr, endaddr, data
-
-Disk image end-of-file bug:
-	Triggered when using e.g. a tar.gz file as a disk image in NetBSD/pmax.
-	NetBSD reads beyond the end of the file. Must be fixed! (Once fixed, documentation
-	can be simplified for some guest OS installations.)
-
-GXsatellite -- Gavare's eXperimental Stand-Aline Test Environment
-	for Low-Level Interactive Testing of Emulators. Share or reuse code with YCX5?
+<p><br>
+<b><a name="cpu">CPU related</a></b>
+<pre>
+Dyntrans / general:
+	o)  Idling:
+		o)  How about showing "has_been_idling" in the status printout?
+			Consider removing has_been_idling alltogether? (now that the
+			number of cycles is kept low...)
+		o)  Turn some "chars" into "bools".
+	x)  SMP: INVALIDATION should cause translations in _all_ cpus to be
+	    invalidated in the machine, e.g. on a write to a write-protected page
+	    (containing code)
 
-Floating point:
-	More tests.
-	
-Documentation:
-	Add the Android ARM machine modes to the documentation, machine_androidarm, color red,
-	once the Linux device tree has been at least implemented enough to see some
-	boot messages or so.
+	    Horrible hack:
 
-	Add the Alpha mode too even though probably almost nothing works at all.
-	Also red. Try to include instructions for NetBSD, OpenBSD
-	and FreeBSD although the later has been discontinued.
+	                cpu_create_or_reset_tc(cpus[i]);
+			cpus[i]->invalidate_translation_caches(
+	                    cpus[i], 0, INVALIDATE_ALL);
+
+	    in machine_run() seems to make Luna88K run stable (?) with 4 CPUs.
+	    Real solution may be to just implement a loop over all CPUs in
+	    memory_rw when storing data to pages?
+
+	o)  Per-arch overrides for whether to print symbols when executing in userspace?
+		e.g. MIPS is OK since symbols are at kseg0.
+		e.g. M88K is not OK, since userland and supervisor are the same numeric values.
+	o)  Why indirection via 		cpu->cpu_family->dumpinfo(cpu, verbose);
+		why not just cpu->dumpinfo?
+	x)  Try to make the vaddr fix O(1) again instead of O(n), if it
+		is possible to see if a non-canonical address has been
+		inserted into the caches. In other words, keep track of	
+		whether a full O(n) seach is really needed or not.
+	x)  For 32-bit emulation modes, that have emulated TLBs: tlbindex
+	    arrays of mapped pages? Things to think about:
+		x)  Only 32-bit mode! (64-bit => too much code)
+		x)  One array for global pages, and one array _PER ASID_,
+		    for those archs that support that. On M88K, there should
+		    be one array for userspace, and one for supervisor, etc.
+		x)  Larger-than-4K-pages must fill several bits in the array.
+		x)  No TLB search will be necessary.
+		x)  Total host space used, for 4 KB pages: 1 MB per table,
+		    i.e. 65 MB for 32-bit MIPS, 2 MB for M88K, if one byte
+		    is used as the tlb index.
+		x)  (The index is actually +1, so that 0 means no hit.)
+	x)  "Merge" the cur_physpage and cur_ic_page variables/pointers to
+	    one? I.e. change cur_ic_page to cur_physpage.ic_page or something.
+	x)  Instruction combination collisions? How to avoid easily...
+	x)  superh -- no hostpage for e.g. 0x8c000000. devices as ram!
+	x)  Think about how to do both SHmedia and SHcompact in a reasonable
+	    way! (Or AMD64 long/protected/real, for that matter.)
+	x)  68K emulation; think about how to do variable instruction
+	    lengths across page boundaries.
+	x)  Dyntrans with valgrind-inspired memory checker. (In memory_rw,
+	    it would be reasonably simple to add; in each individual fast
+	    load/store routine = a lot more work, and it would become
+	    kludgy very fast.)
+		o)  Mark every address with bits which tell whether or not the address
+		    has been written to.
+		o)  What should happen when programs are loaded?  Text/data, bss (zero
+		    filled). But stack space and heap is uninitialized.
+		o)  Uninitialized local variables:
+			A load from a place on the stack which has not previously
+			been stored to => warning. Increasing the stack pointer using
+			any available means should reset the memory to uninitialized.
+		o)  If calls to malloc() and free() can be intercepted:
+			o)  Access to a memory area after free() => warning.
+			o)  Memory returned by malloc() is marked as not-initialized.
+			o)  Non-passive, but good to have: Change the argument
+			    given to malloc, to return a slightly larger memory
+			    area, i.e.  margin_before + size + margin_after,
+			    and return the pointer  + margin_before.
+			    Any access to the margin_before or _after space results
+			    in warnings. (free() must be modified to free the
+			    actually allocated address.)
+	x)  Dyntrans with SMP... lots of work to be done here.
+	x)  Dyntrans with cache emulation... lots of work here as well.
+	x)  Remove the concept of base RAM completely; it would be more
+	    generic to allow RAM devices to be used "anywhere".
+	o)  dev_mp doesn't work well with dyntrans yet
+	o)  In general, IPIs, CAS, LL/SC etc must be made to work with dyntrans
+	x)  Redesign/rethink the delay slot mechanism used for e.g. MIPS,
+		so that it caches a translation (that is, an instruction
+		word and the instr_call it was translated to the last
+		time), so that it doesn't need to do slow
+		to_be_translated for each end of page?
+	x)  Program Counter statistics:
+		Per machine? What about SMP? All data to the same file?
+		A debugger command should be possible to use to enable/
+		disable statistics gathering.
+		Configuration file option!
+	x)  Breakpoints:
+		o) Physical vs virtual addresses!
+		o) 32-bit vs 64-bit sign extension for MIPS, and others?
+	x)  16-bit encodings? (MIPS16, ARM Thumb, etc)
+	x)  Lots of other stuff: see src/cpus/README_DYNTRANS
+	x)  Native code generation backends... think _carefully_ about this.
+	    (Not a priority right now.)
 
-	Add FreeBSD/mips to testmips section? https://wiki.freebsd.org/FreeBSD/MipsEmulation
-	If it works.
+ARM:
+	o)  Big endian does not really work: loads and stores are little endian!
+	o)  More THUMB disassembly?
+	o)  More THUMB execution.
+	o)  0xf "condition" execution: see http://engold.ui.ac.ir/~nikmehr/Appendix_B2.pdf
+	o)  Android devices.
+	o)  See netwinder_reset() in NetBSD; the current "an internal error
+	    occured" message after reboot/halt is too ugly.
+	o)  Generic ARM "wait"-like instruction?
+	o)  try to get netbsd/evbarm 3.x or 4.x running (iq80321)
+	o)  netbsd/iyonix? the i80321 device currently tells netbsd that
+	    RAM starts at 0xa0000000, but that is perhaps not correct for the iyonix.
+	o)  make the xscale counter registers (ccnt) work
+	o)  make the ata controller usable for FreeBSD!
+	o)  Debian/cats crashes because of unimplemented coproc stuff. fix this?
 
-Disk image options:
-	'R' (uppercase): don't allow writes to the disk image file, but let
-	the guest OS think that the device is writable, by using a temporary
-	overlay (created automatically in /tmp) which is removed when the
-	emulator exits. If this is implemented, update the misc
-	documentation, and the man page.
-
-X11:
-	-y n: Command line option for taking framebuffer screen shots n times
-	per second? Look for "ppm image dumps" in dev_fb.cc.html. if 
-	implemented, add to man page.
+i960:
+	Reimplement after the C++ to C switch:
+	x. i960 CPU: Disassembly of at least i960CA instructions.
+	x. HP700/RX machine skeleton.
+	x. bout file loader?
+	x. uCLinux: CycloneVH machine for running uCLinux/i960?
+	x. uCLinux: http://www.ibiblio.org/lou/old/ViewStation/ ?
+
+M88K:
+	o)  Instruction combinations for:
+		memset, memcpy, memmove, strlen, bzero?
+	o)  OpenBSD/luna88k idle loop => detect and idle the host.
 
 MIPS:
+	o) Double-check R10000 vs R4400 TLB specifics:
+ 	   https://techpubs.jurassic.nl/manuals/hdwr/developer/R10K_UM/sgi_html/t5.Ver.2.0.book_347.html
+	o)  MIPS: ehb detection, cop0 write -> tlb instructions.
 	o)  ALU operations (typically addiu, or, etc) can be hardcoded/inlined for common
 		register pairs or even triples. Classic generate_blahblah and an array.
 		Reduces memory accesses for common ALU instructions.
@@ -855,6 +267,42 @@
 		x)  use cop0 framemask for tlb lookups [maybe already working correctly?]
 		    (http://techpubs.sgi.com/library/tpl/cgi-bin/getdoc.cgi/hdwr/bks/SGI_Developer/books/R10K_UM/sgi_html/t5.Ver.2.0.book_284.html)
 
+POWER/PowerPC:
+	x)  Fix DECR timer speed, so it matches the host.
+	x)  NetBSD/prep 3.x triggers a possible bug in the emulator:
+	    <wdc_exec_command(0xd005e514,0xd60cdd30,0,8,..)>
+	      <ata_get_xfer(0,0xd60cdd30,0,8,..)>
+	        <0x26c550(&ata_xfer_pool,2,0,8,..)>
+	        <0x35c71c(0x3f27000,0,52,8,..)>
+	      <ata_exec_xfer(0xd005e4c8,0x3f27000,0,13,..)>
+	        <atastart(0xd005e4c8,0x3f27000,0,13,..)>
+	          <__wdccommand_start(0xd005e4c8,0x3f27000,0,13,..)>
+	            <bsw1(&prep_isa_io_space_tag,0x800001f6,0,176,..)>
+		[ wdc: write to SDH: 0xb0 (sectorsize 2, lba=1, drive 1, head 0) ]
+	            <wdcwait(0xd005e4c8,72,64,0xbb8,..)>
+	              <0x198120(0xd005e4c8,72,64,0xbb8,..)>
+	                <bsr1(&prep_isa_io_space_tag,0,0,0xbb8,..)>
+	                <delay(100,0,0,0xbb8,..)>
+	    Note: <bsr1(&prep_isa_io_space_tag,0,0,0xbb8,..)>
+	x)  PPC optimizations; instr combs
+	x)  64-bit stuff: either Linux on G5, or perhaps some hobbyist
+		version of AIX? (if there exists such a thing)
+	x)  macppc: adb controller; keyboard (for framebuffer mode)
+	x)  make OpenBSD/macppc work (PCI controller stuff)
+	x)  Floating point exception correctness.
+	x)  Alignment exceptions.
+	x)  Boot args for gxemul -xeg4 -d opendarwin-6.6.2.ppc.cdr ? http://web.mit.edu/darwin/www/
+
+RISC-V:
+	Add a RISC-V skeleton again; possibly using 16-bit base encoding, treating
+		32-bit instructions as "two slots". Special case, not as
+		efficient as using full 32-bit instructions as the base case, but could work.
+		4 KB page => 2 K slots plus several at the end, since a long
+		instruction would have its 'next' instruction point way outside
+		the page.
+		Use the latest RISC-V specs, and make sure to check for
+		implementation C (Compact), I (Integer), F etc.
+
 SuperH:
 	x)  Auto-generation of loads/stores! This should get rid of at least
 	    the endianness check in each load/store.
@@ -881,6 +329,70 @@
 		See the manual about this!
 	x)  Exceptions for unaligned load/stores. OpenBSD/landisk uses
 	    this mechanism for its reboot code (machine_reset).
+</pre>
+
+
+
+<p><br>
+<b><a name="machine">Machine/device related</a></b>
+<pre>
+General:
+	o)  Go through the ,NULL arguments to dev_ram_init, 
+		and see if more suitable names can be used!
+
+Algor:
+	o)  Other models than the P5064?
+	o)  PCI interrupts... needed for stuff like the tlp NIC?
+
+ARC:
+	x)  NetBSD/arc 2.0 uses the ASC SCSI controller in a way which GXemul
+	    cannot yet handle. (NetBSD 1.6.2 works ok.) (Possibly a problem
+	    in NetBSD itself, http://mail-index.netbsd.org/source-changes/
+	    2005/11/06/0024.html suggests that.)
+	    NetBSD 4.x seems to work? :)
+
+DECstation:
+	o)  Running two Sprite machines in one emul config file fails; perhaps
+		static vars are used in the PROM emulation code. Fix this.
+		Right now, using separate config files for each machine is
+		necessary.
+	o)  Figure out how to run multiple Sprite machines and make them talk
+		to each other. Starting point for experimentation:
+
+		Set up machine a:
+			Machine name, eg 'ernie' (): a
+
+		On A: (login as root)
+
+		printf "2\tds5000\tb.my.domain\tb\n" >> /etc/spritehosts
+		printf "\tether\t10:20:30:00:00:20\t10.0.0.2\n" >> /etc/spritehosts
+		netroute -f /etc/spritehosts
+		echo "10.0.0.2 b.my.domain b" >> /etc/hosts
+		rm /etc/gateway
+		echo "gw ether 60:50:40:30:20:10 10.0.0.254" > /etc/gateway
+		sync
+		shutdown
+
+		Set up machine b:
+			Machine name, eg 'ernie' (): b
+
+		On B: (login as root)
+
+		rm /etc/spritehosts
+		printf "1\tds5000\ta.my.domain\ta\t1\n" > /etc/spritehosts
+		printf "\tether\t10:20:30:00:00:10\t10.0.0.1\n" >> /etc/spritehosts
+		printf "2\tds5000\tb.my.domain\tb\t2\n" >> /etc/spritehosts
+		printf "\tether\t10:20:30:00:00:20\t10.0.0.2\n" >> /etc/spritehosts
+		echo "10.0.0.1 a.my.domain a" >> /etc/hosts
+		cd /
+		mv ROOT ROOTrenamed
+		sync
+		shutdown
+
+		Start up machine 'a' again, wait until the login prompt is shown.
+		Then start up machine 'b'.
+
+		But it doesn't quite work yet; b does not see A's "/".
 
 Dreamcast:
 	x)  Try to make the ROM from my real Dreamcast boot correctly.
@@ -908,44 +420,54 @@
 	    http://www.maushammer.com/vmu.html for a good description of
 	    the differences between LC86104C and the one used in the VME.
 
-POWER/PowerPC:
-	x)  Fix DECR timer speed, so it matches the host.
-	x)  NetBSD/prep 3.x triggers a possible bug in the emulator:
-	    <wdc_exec_command(0xd005e514,0xd60cdd30,0,8,..)>
-	      <ata_get_xfer(0,0xd60cdd30,0,8,..)>
-	        <0x26c550(&ata_xfer_pool,2,0,8,..)>
-	        <0x35c71c(0x3f27000,0,52,8,..)>
-	      <ata_exec_xfer(0xd005e4c8,0x3f27000,0,13,..)>
-	        <atastart(0xd005e4c8,0x3f27000,0,13,..)>
-	          <__wdccommand_start(0xd005e4c8,0x3f27000,0,13,..)>
-	            <bsw1(&prep_isa_io_space_tag,0x800001f6,0,176,..)>
-		[ wdc: write to SDH: 0xb0 (sectorsize 2, lba=1, drive 1, head 0) ]
-	            <wdcwait(0xd005e4c8,72,64,0xbb8,..)>
-	              <0x198120(0xd005e4c8,72,64,0xbb8,..)>
-	                <bsr1(&prep_isa_io_space_tag,0,0,0xbb8,..)>
-	                <delay(100,0,0,0xbb8,..)>
-	    Note: <bsr1(&prep_isa_io_space_tag,0,0,0xbb8,..)>
-	x)  PPC optimizations; instr combs
-	x)  64-bit stuff: either Linux on G5, or perhaps some hobbyist
-		version of AIX? (if there exists such a thing)
-	x)  macppc: adb controller; keyboard (for framebuffer mode)
-	x)  make OpenBSD/macppc work (PCI controller stuff)
-	x)  Floating point exception correctness.
-	x)  Alignment exceptions.
+HPCmips:
+	x)  MIPS hibernate instruction => make the exit from the emulator nicer!
+	x)  Clock? Is it running at correct speed?
+	x)  Mouse/pad support! :)
+	x)  A NIC? (As a PCMCIA device?)
 
-PReP:
-	x)  Clock time! ("Bad battery blah blah")
-
-Algor:
-	o)  Other models than the P5064?
-	o)  PCI interrupts... needed for stuff like the tlp NIC?
+LUNA-88K:
+	autoboot of OpenBSD: boot_unit and boot_partition in NVRAM should be
+		set to the actual boot device; currently hardcoded to 0,0.
+	luna88k bootblock loader:
+		o load binary from UFS filesystem (i.e. a partition given by an
+			offset into a disk image).
+		o) if no bootstring (boot file) is specified, then perhaps try a few
+			from a list? "vmunix", "boot".
+	Color framebuffer
+	SCSI: OpenBSD/luna88k warns about
+		probe(spc0:0:0): Check Condition (error 0) on opcode 0x0
+		for non-connected devices. (Just a warning though.)
+	Cursor keys in the graphical framebuffer window? (Works with pckbd for SGI?)
+	separate out some devices into their own files? (reuse TOD clock for example)
+	Front-side LCD panel:
+		One idea is to make the framebuffer window taller, and show
+		the LCD text in the lower left-hand corner, in a way mimicing
+		a real machine.
+	SMP stability: possibly instabilities are related to clearing
+		translation cache on page writes (for ALL cpus, not just the
+		one doing the page write).
+	LUNA-88K2 machine: check OpenBSD source code to see where there are
+		differences in devices and registers etc.
 
 Malta:
 	o)  Try FreeBSD/malta: https://wiki.freebsd.org/FreeBSD/MipsEmulation
 	o)  Malta can perhaps have up to 2 GB RAM? Try same hack as for the SGI O2.
 	o)  Reconfigurable PCI memory space would be nice (just like SGI O2).
 
+MVME88K / mvme187:
+	OpenBSD 4.5 works ok with -x, but interrupts are lost (?) when not using -x.
+
+PReP:
+	x)  Clock time! ("Bad battery blah blah")
+
 SGI O2:
+	ARCBIOS output should go to some terminal; right now (for e.g. SGI O2), it goes to the main window.
+
+	If/when booting from SGI disk images is really meaningful (i.e. not just that it
+	   correctly loads the OSLoader, but can boot an entire OS): update the man page
+	   and other documentation regarding booting directly from SGI disk images.
+
 	differences between real hardware and NetBSD's header files?
 
 		RED/GREEN LED: 1 on real hardware turns off, not on!
@@ -1024,116 +546,67 @@
 
 	IRIX? Networking? SCSI? Currently panics due to root vfs not available.
 
-HPCmips:
-	x)  Clock? Is it running at correct speed?
-	x)  Mouse/pad support! :)
-	x)  A NIC? (As a PCMCIA device?)
-	x)  Investigate why not all MobilePro models work any longer with recent NetBSD versions.
-
-ARM:
-	o)  Big endian does not really work: loads and stores are little endian!
-	o)  More THUMB disassembly?
-	o)  More THUMB execution.
-	o)  0xf "condition" execution: see http://engold.ui.ac.ir/~nikmehr/Appendix_B2.pdf
-	o)  Android devices.
-	o)  See netwinder_reset() in NetBSD; the current "an internal error
-	    occured" message after reboot/halt is too ugly.
-	o)  Generic ARM "wait"-like instruction?
-	o)  try to get netbsd/evbarm 3.x or 4.x running (iq80321)
-	o)  netbsd/iyonix? the i80321 device currently tells netbsd that
-	    RAM starts at 0xa0000000, but that is perhaps not correct for the iyonix.
-	o)  make the xscale counter registers (ccnt) work
-	o)  make the ata controller usable for FreeBSD!
-	o)  Debian/cats crashes because of unimplemented coproc stuff. fix this?
-
 Test machines:
+	o)  Fix dev_cons.c DEV_CONS_HALT so that it halts the cpus gracefully,
+	    i.e. usage in demo code should be:
+		for (;;) {
+			halt();
+		}
+	o) testmips: Add support for more than 256 MB ram, e.g. by adding
+		"actual RAM" at the 1 GB offset. A 32 bit machine can thus use
+		3 GB, no limit on 64 bit machines. Low 256 MB can be considered
+		a mirror of first 256 MB of RAM.
 	o)  dev_fb 2D acceleration functions, to make dev_fb useful for simple graphical OSes:
 		x) block fill and copy
 		x) draw characters (from the built-in font)?
 	o)  dev_fb input device? mouse pointer coordinates and buttons
 		(allow changes in these to cause interrupts as well?)
-	o)  Redefine the halt() function so that it stops "sometimes
-	    soon", i.e. usage in demo code should be:
-		for (;;) {
-			halt();
-		}
 	o)  More demos/examples.
+</pre>
+
 
-Dyntrans:
-	x)  Try to make the vaddr fix O(1) again instead of O(n), if it
-		is possible to see if a non-canonical address has been
-		inserted into the caches. In other words, keep track of	
-		whether a full O(n) seach is really needed or not.
-	x)  For 32-bit emulation modes, that have emulated TLBs: tlbindex
-	    arrays of mapped pages? Things to think about:
-		x)  Only 32-bit mode! (64-bit => too much code)
-		x)  One array for global pages, and one array _PER ASID_,
-		    for those archs that support that. On M88K, there should
-		    be one array for userspace, and one for supervisor, etc.
-		x)  Larger-than-4K-pages must fill several bits in the array.
-		x)  No TLB search will be necessary.
-		x)  Total host space used, for 4 KB pages: 1 MB per table,
-		    i.e. 65 MB for 32-bit MIPS, 2 MB for M88K, if one byte
-		    is used as the tlb index.
-		x)  (The index is actually +1, so that 0 means no hit.)
-	x)  "Merge" the cur_physpage and cur_ic_page variables/pointers to
-	    one? I.e. change cur_ic_page to cur_physpage.ic_page or something.
-	x)  Instruction combination collisions? How to avoid easily...
-	x)  superh -- no hostpage for e.g. 0x8c000000. devices as ram!
-	x)  Think about how to do both SHmedia and SHcompact in a reasonable
-	    way! (Or AMD64 long/protected/real, for that matter.)
-	x)  68K emulation; think about how to do variable instruction
-	    lengths across page boundaries.
-	x)  Dyntrans with valgrind-inspired memory checker. (In memory_rw,
-	    it would be reasonably simple to add; in each individual fast
-	    load/store routine = a lot more work, and it would become
-	    kludgy very fast.)
-		o)  Mark every address with bits which tell whether or not the address
-		    has been written to.
-		o)  What should happen when programs are loaded?  Text/data, bss (zero
-		    filled). But stack space and heap is uninitialized.
-		o)  Uninitialized local variables:
-			A load from a place on the stack which has not previously
-			been stored to => warning. Increasing the stack pointer using
-			any available means should reset the memory to uninitialized.
-		o)  If calls to malloc() and free() can be intercepted:
-			o)  Access to a memory area after free() => warning.
-			o)  Memory returned by malloc() is marked as not-initialized.
-			o)  Non-passive, but good to have: Change the argument
-			    given to malloc, to return a slightly larger memory
-			    area, i.e.  margin_before + size + margin_after,
-			    and return the pointer  + margin_before.
-			    Any access to the margin_before or _after space results
-			    in warnings. (free() must be modified to free the
-			    actually allocated address.)
-	x)  Dyntrans with SMP... lots of work to be done here.
-	x)  Dyntrans with cache emulation... lots of work here as well.
-	x)  Remove the concept of base RAM completely; it would be more
-	    generic to allow RAM devices to be used "anywhere".
-	o)  dev_mp doesn't work well with dyntrans yet
-	o)  In general, IPIs, CAS, LL/SC etc must be made to work with dyntrans
-	x)  Redesign/rethink the delay slot mechanism used for e.g. MIPS,
-		so that it caches a translation (that is, an instruction
-		word and the instr_call it was translated to the last
-		time), so that it doesn't need to do slow
-		to_be_translated for each end of page?
-	x)  Program Counter statistics:
-		Per machine? What about SMP? All data to the same file?
-		A debugger command should be possible to use to enable/
-		disable statistics gathering.
-		Configuration file option!
-	x)  Breakpoints:
-		o) Physical vs virtual addresses!
-		o) 32-bit vs 64-bit sign extension for MIPS, and others?
-	x)  INVALIDATION should cause translations in _all_ cpus to be
-	    invalidated, e.g. on a write to a write-protected page
-	    (containing code)
-	x)  16-bit encodings? (MIPS16, ARM Thumb, etc)
-	x)  Lots of other stuff: see src/cpus/README_DYNTRANS
-	x)  Native code generation backends... think _carefully_ about this.
-	    (Not a priority right now.)
 
-Better CD Image file support:
+<p><br>
+<b><a name="misc">Misc.</a></b>
+<pre>
+Breakpoints with config files doesn't seem to work correctly? (luna88k?)
+
+Breakpoints on subsystem messages?
+	breakpoint subsystem		<- show any subsystem breakpoints
+	breakpoint subsystem disk warn	<- break on warnings and errors, but
+						not on info and debug.
+	breakpoint subsystem disk off	<- turn off breakpoint
+	Effect: enter single stepping when such a message is printed.
+		NOTE: Only check breakpoint AFTER check for "is enough"? Because
+			there may be if("is enough") spread out through the
+			code anyway.
+			In other words: when doing
+				breakpoing subsystem disk info
+			if the current verbosity level of disk is 'warn', then
+			implicitly raise it to 'info' and tell the user about it.
+	NEED TO CHECK about-to-enter-single-step and/or single-step after
+		memory_rw calls, to break out of the dyntrans loop.
+		Implement helper for these cases? cpu->running == 0 is just
+		one reason to break then.
+
+	Currently, breakpoints are just an array of string and addresses,
+	inside a machine. (Because addresses are conceptually bound to the _memory_ in
+	that machine.)
+
+	breakpoints that just print hit count, rather than break? Or better:
+		all breakpoints can keep track of hit count
+		and then there could be a setting on how long to run until
+			actually breakin. e.g.
+				1 = always break
+				inf = never break, just count
+				100 = run 100 then break.
+		implementationwise:
+			int64_t hits_until_break
+			int64_t hitcount
+			int64_t next_hitcount_to_break_on
+		CTRL-T could show breakpoint hit counts.
+
+CD Image file support:
 	x)  Support CD formats that contain more than 1 track, e.g.
 	    CDI files (?). These can then contain a mixture of e.g. sound
 	    and data tracks, and booting from an ISO filesystem path
@@ -1141,31 +614,133 @@
 	    (This would make sense for e.g. Dreamcast CD images, or
 	    possibly other live-CD formats.)
 
+Clocks and timers:
+	x)  Fix the PowerPC DECR interrupt speed! (MacPPC and PReP speed, etc.)
+	x)  DON'T HARDCODE 100 HZ IN cpu_mips_coproc.c!
+	x)  NetWinder timeofday is incorrect! Huh? grep -R for ta_rtc_read in
+	    NetBSD sources; it doesn't seem to be initialized _AT ALL_?!
+	x)  Cobalt TOD is incorrect!
+	x)  Go through all other machines, one by one, and fix them.
+
+Components:
+	_MAYBE_ it would be possibly to unify the CPU and device concepts, so
+	that they are just arbitrary components in a machine... like the C++
+	framework was. machine_run currently run a) instructions from cpus, and
+	b) ticks from devices. There is no big reason why these could not be
+	made the same concept.
+
+	Components (busses, CPUs, devices, machines) would be a tree, like
+	in the C++ framework.
+
+	Component tree dump should then be the same during startup and
+	for the emul / machine debugger commands. Compare e.g. the C++ framework's
+		  mainbus0
+		  |-- cpu0  (i960CA, 25 MHz)
+		  |   \-- cache  etc...
+		  |-- ram0  (2 MB repeated for 256 MB at offset 0x30000000)
+		  |-- ram1  (8 MB repeated for 16 MB at offset 0x40000000)
+		  \-- rom0  (512 KB at offset 0xfff80000)
+	to
+		machine: 
+		    device at 0x0030000000: ram (dyntrans R/W)
+		    device at 0x0040000000: ram (dyntrans R/W)
+		    device at 0x0041000000: ram (dyntrans R/W)
+		    device at 0x00fff80000: ram (dyntrans R/W)
+		    model: HP 700/RX
+		    cpu: i960CA
+		    memory: 1 MB
+
+	If there are multiple memories in a machine, a CPU searches for its
+	memory like in the C++ framework: first to a parent (e.g. a mainbus)
+	and then to a memory on that bus.
+
+Debugger:
+	Helpers for splitting up into arguments/words.
+
+	Helpers for using abbreviations/tab completion for arguments? Allow
+		e.g. "b sh" to mean "breakpoint show". Right now, "show" needs
+		to be written out in full.
+
+	"u pc+0x40" works but not "u pc + 0x40" with spaces!
+
+	More complex expressions, and Unit tests for them.
+
+	Extend the
+		put [b|h|w|d|q] addr, data    modify emulated memory contents
+	command with a "s" (string) mode, where data is a string. Also
+	"z" which puts a nul-terminated string in memory. It should put the
+	string there one byte at a time.
+	
+		put s 0x80008000, "apa"
+
+	or
+
+		put z 0x80008000, "apa"
+
+
+	Extend the debugger with a "find" command as well, similar to
+	put but with a range?
+
+		find [b|h|w|d|q|s|z] startaddr, endaddr, data
+
+	Command for launching a separate terminal for output from a specified subsystem?
+		(Or a flag to the verbosity command?)
+
+	"step call" ? running like single-step, but instead of one instruction, it
+		runs until the next function call (or function return)? (with implicit
+		function trace printout turned on...)
+
+	Tab completion for symbols? That would help...
+
+	CTRL-T is already supported when single-stepping.
+		o) Also support CTRL-T while executing in main emul loop?
+		Should CTRL-T be checked in console.c, or in emul.c?
+
+Disk image options:
+	Command line option for forcing fsync on each disk image write; see
+	do_fsync in src/disk/diskimage.c
+
+Documentation:
+	Dyntrans: Mention how to break out of the dyntrans loop: cpu->running = 0
+	and the nothing instruction, and how nr of instructions is counted then.
+
+	Update the man page about disk boot block loading to not explicitly list the
+	supported machine types.
+
+	Update test device section on "fb": set and read resolution
+
+	Add the Android ARM machine modes to the documentation, machine_androidarm, color red,
+	once the Linux device tree has been at least implemented enough to see some
+	boot messages or so.
+
+	Add the Alpha mode too even though probably almost nothing works at all.
+	Also red. Try to include instructions for NetBSD, OpenBSD
+	and FreeBSD although the later has been discontinued.
+
+	Add FreeBSD/mips to testmips section? https://wiki.freebsd.org/FreeBSD/MipsEmulation
+	If it works.
+
+	Add an Example in the documentation for a config file with multiple machines (and a plain net()).
+
+Floating point:
+	More tests.
+
 Networking:
-	x)  Redesign of the networking subsystem, at least the NAT translation
-		part. The current way of allowing raw ethernet frames to be
-		transfered to/from the emulator via UDP should probably be
-		extended to allow the frames to be transmitted other ways as
-		well.
+	x)  PERFORMANCE:
+		o) Fix performance problems caused by only allowing a
+		    single TCP packet to be unacked. (?)
+		o) Go through Lance Ethernet interrupt code and memory mapping, to look at
+		   performance. (Performance when downloading things from the internet is
+		   extremely poor, from inside NetBSD/pmax and OpenBSD/luna88k.)
+		   (Maybe it is not a problem with the Lance, but with the
+		   general src/net/ implementation...)
 	x)  Also adding support for connecting ttys (either to xterms, or to
 		pipes/sockets etc, or even to PPP->NAT or SLIP->NAT :-).
-	x)  Documentation updates (!) are very important, making it easier to
-		use the (already existing) network emulation features.
-	x)  Fix performance problems caused by only allowing a
-	    single TCP packet to be unacked.
-	x)  Don't hardcode offsets into packets!
 	x)  Test with lower than 100 max tcp/udp connections,
 	    to make sure that reuse works!
-	x)  Make OpenBSD work better as a guest OS!
-	x)  DHCP? Debian doesn't actually send DHCP packets, even
-		though it claims to? So it is hard to test.
 	x)  Multiple networks per emulation, and let different
 	    NICs in machines connect to different networks.
-	x)  Support VDE (vde.sf.net)? Easiest/cleanest (before a
-	    redesign of the network framework has been done) is
-	    probably to connect it using the current (udp) solution.
-	x)  Allow SLIP connections, possibly PPP, in addition to
-	    ethernet?
+	x)  Allow SLIP connections, possibly PPP, in addition to ethernet?
 
 PCI:
 	o)  Big-endian Malta access?
@@ -1185,22 +760,9 @@
 	x)  add support for address fixups
 	x)  generalize the interrupt routing stuff (lines etc)
 
-Clocks and timers:
-	x)  Fix the PowerPC DECR interrupt speed! (MacPPC and PReP speed, etc.)
-	x)  DON'T HARDCODE 100 HZ IN cpu_mips_coproc.c!
-	x)  NetWinder timeofday is incorrect! Huh? grep -R for ta_rtc_read in
-	    NetBSD sources; it doesn't seem to be initialized _AT ALL_?!
-	x)  Cobalt TOD is incorrect!
-	x)  Go through all other machines, one by one, and fix them.
-
-ASC SCSI controller:
-	x)  NetBSD/arc 2.0 uses the ASC controller in a way which GXemul
-	    cannot yet handle. (NetBSD 1.6.2 works ok.) (Possibly a problem
-	    in NetBSD itself, http://mail-index.netbsd.org/source-changes/
-	    2005/11/06/0024.html suggests that.)
-	    NetBSD 4.x seems to work? :)
-
-Better framebuffer and X-windows functionality:
+X-windows and Framebuffer functionality in general:
+	o)  Icon for X11 framebuffer windows?
+	o)  Change window title in X11 windows for machines that have all cpus halted?
 	o)  Do a complete rewrite of the framebuffer/console stuff, so that:
 		1)  It does not rely on X11 specifically.
 		2)  It is possible to interact with emulated framebuffers
@@ -1233,11 +795,10 @@
 		    emulator)
 	o)  Generalize the framebuffer stuff by moving _ALL_ X11
 		specific code to a separate module.
+	o)  Wayland? -W ?
 </pre>
 
 
-
-
 <p><br>
 <b><a name="release">Release checklist</a></b>
 
@@ -1246,7 +807,7 @@
 	<ul>
 		<li>Build on as many platforms as possible, including inside guest OSes in GXemul itself.
 		<li>If there is time: Install as many as possible of the guest OSes in the documentation;
-		the documentation may need to be updated if there are regressions.
+			the documentation may need to be updated if there are regressions.
 		<li>If there is more time: try newer versions of the officially
 			supported guest OSes (sometimes these work, sometimes not).
 		<li>If there is even more time: see what the status is for the
@@ -1258,7 +819,7 @@
 		<li>TODO updates (i.e. set goals for the <i>next</i> release, if possible,
 			or strike out things that have been fixed).
 		<li>HISTORY (mention the release).
-		<li>Tarball creation (make_release.sh)
+		<li>Tarball creation (make_release.sh and just_update.sh)
 		<li>Home page <i>Download page</i> update: version number and date.
 		<li>Home page <i>News page</i> update: new Release.
 		<li>Create subversion tag.
@@ -1272,3 +833,4 @@
 
 </body>
 </html>
+
diff -Nru gxemul-0.6.2/doc/translation.html gxemul-0.7.0+dfsg/doc/translation.html
--- gxemul-0.6.2/doc/translation.html	2019-06-22 18:23:28.000000000 +0000
+++ gxemul-0.7.0+dfsg/doc/translation.html	2021-11-27 09:42:23.000000000 +0000
@@ -16,7 +16,7 @@
 
 <!--
 
-Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
+Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
@@ -64,15 +64,20 @@
 <a name="staticvsdynamic"></a>
 <h3>Static vs. dynamic:</h3>
 
-<p>In order to support guest operating systems, which can overwrite old 
-code pages in memory with new code, it is necessary to translate code 
-<a href="http://en.wikipedia.org/wiki/Binary_translation#Dynamic_translation"><i>dynamically</i></a>.
-It is not possible to do a static (one-pass) translation.
+<p>In order to support guest operating systems, it is important to take into
+account the fact that code pages in memory can be overwritten with new code,
+e.g. when loading new programs inside the guest OS.
+Statically doing a one-time translation of the code to run will thus not work,
+it is necessary to translate code <i>dynamically</i> <sup>*</sup>.
 Self-modifying code and Just-in-Time compilers running inside 
 the emulator are other things that would not work with a static 
 translator. GXemul is a dynamic translator. However, it does not 
 necessarily translate into <a href="#native">native code</a>, like some other emulators.
 
+<p><small>* Actually this is not necessary. Instead of translating the
+code ahead of execution, the instructions could be interpreted one-at-a-time.
+But this is slow.</small>
+
 
 
 
@@ -91,13 +96,8 @@
 <p>The IR in GXemul consists of <i>arrays of pointers to functions</i>, and a few 
 arguments which are passed along to those functions. This is usually referred
 to as <a href="http://en.wikipedia.org/wiki/Threaded_code">threaded code</a>.
-The functions are implemented in either manually hand-coded C/C++, or
-generated C/C++.
-
-<p>("Generated code" in the old C dyntrans framework means generated by special
-programs at compile time, which output temporary <tt>.c</tt> files; in the C++ dyntrans
-framework, this is implemented using templates instead. In any case, this is all
-statically linked into the GXemul binary at link time.)
+The functions are implemented in either manually hand-coded C code, or
+generated C code.
 
 <p>Here is a simplified diagram of how these arrays work.
 
@@ -113,9 +113,12 @@
 executed instructions. Instead, they jump to the first instruction
 on the next virtual page (which might cause exceptions, etc).
 
+<p>(For architectures with 32-bit long instructions and 4 KB page size
+<b>without</b> a delay slot, there are 1025 entries, and for those <b>with</b>
+a delay slot there are 1026 entries.)
+
 <p>The core dyntrans loop, which executes the instructions in the
-instruction call slots, looks something like this: (Note: This is from
-pre-0.6.x.)
+instruction call slots, looks something like this:
 
 <pre>
 	<font color="#0000ff">/*  The normal instruction execution core:  */</font>
@@ -154,9 +157,19 @@
 the same place multiple times, which seems to fit with some modern CPUs'
 branch prediction mechanisms.
 
+<p>There are two important pointers: next_ic points to the next instruction
+call, and cur_ic_page points to the whole page of such instructions. Thus,
+when the main loop exits, we can check what next_ic points to. If it points
+to one of the slots inside the current page (cur_ic_page), then the program
+counter's lowest bits should be adjusted to be in sync with the next_ic
+pointer. It can also happen that the next_ic points to something else:
+a special case is when one wants to break out of the dyntrans loop, e.g.
+if there was an error. Then, next_ic does not point to any of the instruction
+slots in that page, and thus the program counter's lowest bits are not synced
+from the next_ic value.
+
 <p>The complexity of individual instructions vary. A simple example of
-what an instruction can look like is the MIPS <tt>addu</tt> instruction.
-First, as implemented in the old C dyntrans framework (pre-0.6.x):
+what an instruction can look like is the MIPS <tt>addu</tt> instruction:
 <pre>
 	<font color="#0000ff">/*
 	 *  3-register arithmetic instructions:
@@ -180,80 +193,40 @@
 in the 32-bit case. Both are compiled into the GXemul executable; no code 
 is created during run-time.
 
-<p>The C++ dyntrans implementation (in GXemul 0.6.x) is similar, except that a fixed
-<tt>REG32</tt> or <tt>REG64</tt> is used instead of <tt>reg</tt> (so it is only compiled once
-instead of twice). Also, instructions that may be reused between emulated
-architectures, such as this 32-bit signed add instruction, are in
-<a href="doxygen/html/classCPUDyntransComponent.html"><tt>CPUDyntransComopnent</tt></a>
-instead of <a href="doxygen/html/classMIPS__CPUComponent.html"><tt>MIPS_CPUComponent</tt></a>.
-
-<pre>
-	<font color="#0000ff">/*
-	 * arg 0: 64-bit register
-	 * arg 1: 64-bit register
-	 * arg 2: 64-bit register
-	 *
-	 * Adds the the registers in arg 1 and arg 2, and stores the result in arg 0
-	 * (truncated to a signed 32-bit value).
-	 */</font>
-	DYNTRANS_INSTR(CPUDyntransComponent,add_u64_u64_u64_truncS32)
-	<font color="#404040">{</font>
-		REG64(ic->arg[0]) = (int32_t) (REG64(ic->arg[1]) + REG64(ic->arg[2]));
-	<font color="#404040">}</font>
-</pre>
-
 <p>Another reasonably simple example is the M88K <tt>bsr</tt> (branch to subroutine)
 instruction. This is a branch which also sets the return address register to the
 instruction following the branch. Here is the implementation for "samepage" offsets,
 i.e. branch offsets which are inside the same dyntrans page:
 
 <pre>
-	DYNTRANS_INSTR(M88K_CPUComponent,bsr_samepage)
+	X(bsr_samepage)
 	<font color="#404040">{</font>
-		<font color="#0000ff">//  This declares a <b>cpu</b> variable of the correct type which we can use.</font>
-		DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-		<font color="#0000ff">//  Set the return address.</font>
-		cpu->m_r[M88K_RETURN_REG] = (cpu->m_pc & ~((M88K_IC_ENTRIES_PER_PAGE-1)
-		    << M88K_INSTR_ALIGNMENT_SHIFT)) + ic->arg[2].u32;
-
-		<font color="#0000ff">//  Branch.</font>
-		cpu->m_nextIC = (struct DyntransIC *) ic->arg[0].p;
+		cpu->cd.m88k.r[M88K_RETURN_REG] = (cpu->pc &
+		    ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT))
+		    + ic->arg[2];
+		cpu->cd.m88k.next_ic = (struct m88k_instr_call *) ic->arg[0];
 	<font color="#404040">}</font>
 </pre>
 
 <p>
-Here, the M88K <tt>r1</tt> register (the return register) is set to the return address
-(the current program counter plus an offset in <tt>arg[2]</tt> pointing to the next instruction)
-and then the next instruction call to execute is set to <tt>arg[0]</tt>.
-
-<p>Although it looks like the <tt>bsr_samepage</tt> code would result in quite
-a lot of host instructions, objdump reveals that the compiler was able to
-optimize it to a reasonably short sequence:
+Don't be scared by the logic operators.
+Here, the M88K <tt>r1</tt> register (the return register) is set to the
+return address, which is calculated by taking the current program counter,
+clearing the lowest bits, and adding arg[2] which is the offset within the
+page of the next instruction.
+Then the next instruction call to execute is set to <tt>arg[0]</tt>, which
+needs to be on the same page (since cur_ic_page is not updated).
 
-<pre>
-	On Alpha (compiled with GNU C++ 3.4.6):
-	<font color="#808080">&lt;_ZN17M88K_CPUComponent18instr_bsr_samepageEP20CPUDyntransComponentP10DyntransIC&gt;:</font>
-	     760:       b0 00 90 a4     ldq     t3,176(a0)
-	     764:       1f 04 ff 47     nop     
-	     768:       03 f0 bf 20     lda     t4,-4093
-	     76c:       18 00 71 a0     ldl     t2,24(a1)
-	     770:       00 00 85 44     and     t3,t4,v0
-	     774:       01 04 03 40     addq    v0,t2,t0
-	     778:       d0 01 30 b0     stl     t0,464(a0)		<i>; Set the return address</i>
-	     77c:       08 00 51 a4     ldq     t1,8(a1)
-	     780:       38 01 50 b4     stq     t1,312(a0)		<i>; ... and update nextIC.</i>
-	     784:       01 80 fa 6b     ret
-
-	On AMD64 (compiled with GNU C++ 4.2.1):
-	<font color="#808080">&lt;_ZN17M88K_CPUComponent18instr_bsr_samepageEP20CPUDyntransComponentP10DyntransIC&gt;:</font>
-	  419310:       8b 87 b0 00 00 00       mov    0xb0(%rdi),%eax
-	  419316:       25 03 f0 ff ff          and    $0xfffff003,%eax
-	  41931b:       03 46 18                add    0x18(%rsi),%eax
-	  41931e:       89 87 d0 01 00 00       mov    %eax,0x1d0(%rdi)		<i>; Set the return address</i>
-	  419324:       48 8b 46 08             mov    0x8(%rsi),%rax
-	  419328:       48 89 87 38 01 00 00    mov    %rax,0x138(%rdi)		<i>; ... and update nextIC.</i>
-	  41932f:       c3                      retq   
+<p>
+The compiled code may look like this (example from an AMD64 host):
+<pre>000000000036dac0 <m88k_instr_bsr_samepage>:
+  36dac0:       b8 03 f0 ff ff          mov    $0xfffff003,%eax
+  36dac5:       23 87 a8 00 00 00       and    0xa8(%rdi),%eax
+  36dacb:       03 46 18                add    0x18(%rsi),%eax
+  36dace:       89 87 e4 00 00 00       mov    %eax,0xe4(%rdi)
+  36dad4:       48 8b 46 08             mov    0x8(%rsi),%rax
+  36dad8:       48 89 87 e0 03 00 00    mov    %rax,0x3e0(%rdi)
+  36dadf:       c3                      retq   
 </pre>
 
 
@@ -369,7 +342,7 @@
 <p>The overhead per emulated instruction is usually around or below
 approximately 10 host instructions. This is very much dependent on your
 host architecture and what compiler and compiler switches you are using.
-Added to this instruction count is (of course) also the C/C++ code used to
+Added to this instruction count is (of course) also the C code used to
 implement each specific instruction.
 
 
@@ -473,9 +446,6 @@
 	<font color="#404040">}</font>
 </pre>
 
-<p><small>(Note: This is from the old C dyntrans system, not the 0.6.x
-dyntrans implementation.)</small>
-
 <p>For large memsets, calling the native/system <tt>memset</tt> implementation will most
 likely be a lot faster than emulating the MIPS <tt>memset</tt> one instruction at a time.
 
@@ -501,15 +471,17 @@
 <h3>Native Code Generation Back-ends:</h3>
 
 <p>Native code generation was included in GXemul before 0.4.x, but only for
-i386 and Alpha hosts, but that did not feel clean and portable enough to work
-as a long-term solution. Time has proved this right; i386 has been superseded
+i386 and Alpha hosts. That did not feel clean and portable enough to work
+as a long-term solution. Time has proved this right: i386 has been superseded
 by amd64, and the Alpha architecture has unfortunately been killed.
+
+<p>
 The current implementation instead focuses on an having an intermediate
 representation that can be executed regardless of what the native architecture
 is.
 
 <p>In theory, it would be possible to add native code generation again,
-as long as that generated code abides to the C or C++ ABI on the host.
+as long as that generated code abides to the C ABI on the host.
 
 
 
diff -Nru gxemul-0.6.2/experiments/make_index.sh gxemul-0.7.0+dfsg/experiments/make_index.sh
--- gxemul-0.6.2/experiments/make_index.sh	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/experiments/make_index.sh	2021-11-27 09:42:23.000000000 +0000
@@ -4,7 +4,7 @@
 #
 
 rm -f .index
-for a in *.cc; do
+for a in *.c; do
 	B=`grep COMMENT $a`
 	if [ z"$B" != z ]; then
 		printf "$a " >> .index
diff -Nru gxemul-0.6.2/HISTORY gxemul-0.7.0+dfsg/HISTORY
--- gxemul-0.6.2/HISTORY	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/HISTORY	2021-11-27 09:42:23.000000000 +0000
@@ -4910,3 +4910,145 @@
 
 ==============  RELEASE 0.6.2  ==============
 
+20190626	Rounding up disk image sizes to full cylinders; fixes a bug
+		where guest OSes could fail to read the end of e.g. a .tar.gz
+		file supplied as a disk image on the command line.
+20201006	Applying a rather large patch from Jason Thorpe for using
+		/dev/tap devices in addition to the existing networking modes.
+		The patch also consists of enhancements to the DEC21143 and
+		Lance ethernet devices to perform packet filtering.
+20201015	Adding support for masks for memory mapped components in the
+		new framework. Used so far by the HP 700/RX, which has 2 MB
+		RAM repeated throughout 0x30000000..0x3fffffff.
+20201101	bootblock.cc now parses SGI disk boot blocks, and tries to
+		load the OSLoader (sash), if booting without an explicitly
+		provided OS kernel.
+20201103	The ECOFF file loader can now (barely) load relocated binaries,
+		such as "sash" from an IRIX installation on my real O2.
+20201105	Some minor refactoring of arcbios environment variables etc,
+		to attempt to get emulated O2 boot-from-disk image (or cdrom
+		image) to work better.
+20210116	Include ASID and VPN2 in MIPS load/store misalignment
+		exceptions (patch from Nick Hudson).
+20210123	Adding a patch from Luchezar Georgiev for missing variant of
+		rot for 88100 (immediate argument), and for missing addu_cio
+		and subu_cio instructions.
+		Inspired by Luchezar Georgiev's patch for subu_cio, a closer
+		look at the subu borrow bit resulted in a bug fix which finally
+		allows a OpenBSD/luna88k 6.8 ramdisk to boot all the way to
+		userland.
+20210127	Writing some ugly glue code to connect the Lance Ethernet
+		device (dev_le) to the LUNA88K machine. An OpenBSD/luna88k 6.8
+		ramdisk can now (barely) reach the internet using TCP/IPv4.
+20210130	Writing guest OS install instructions for running OpenBSD/
+		luna88k with root-on-nfs, which involves using NetBSD/pmax as
+		an NFS server and OpenBSD/sgi (!) to run MAKEDEV.
+20210207	Fixing a spelling mistake in the 88K fdiv.sss instruction,
+		making self-compilation of [an older version of] GXemul inside
+		OpenBSD/luna88k get further.
+20210209	Adding keyboard support to dev_luna88k.
+20210213	Implementing exception cases in 88K xmem_slow implementation.
+20210214	Implementing the fdiv.dss 88K instruction.
+20210215	Implementing the fsub.sss 88K instruction.
+
+==============  RELEASE 0.6.3  ==============
+
+20210215	Implementing the fadd.dss 88K instruction, and working a bit
+		more on the exception cases in the xmem instruction.
+20210220	Implementing mouse emulation support for the LUNA88K machine.
+		Updating OpenBSD/sgi install instructions (6.5 -> 6.8),
+		and including a screenshot of X11 running.
+20210221	Handle return values from interrupted select() when checking
+		for available console input. (Found when using CTRL-C on Linux
+		to enter the debugger command line, and noticed that it was
+		spuriously broken.)
+20210222	Basic multiprocessor bootup of OpenBSD/luna88k now works, but
+		it is slightly unstable.
+
+==============  RELEASE 0.6.3.1  ==============
+
+20210228	Switching back from C++ to plain C.
+		Implementing a helper method for registering device addresses
+		as symbols (so that it can be used from several machines).
+20210307	Subtle colorized output when stdin/stdout are connected to a
+		tty, to make it quicker to interpret text output. Enabled with
+		-G or by setting the CLICOLOR environment variable. Can be
+		disabled with -A.
+20210309	Beginning to separate debug messages into subsystems, that have
+		individual verbosity levels.
+		Making -K work more consistently (enter the debugger at the
+		end of a run). -V implies -K.
+		Making -T work better for M88K (breaking into the debugger
+		directly on bad memory accesses, if -K is used).
+20210310	All MIPS machines now register their devices as symbols (based
+		in kseg1, i.e. 0xffffffffa0000000).
+20210311	Making -T work better for MIPS, PPC, ARM, and SuperH.
+20210314	Adding a -L command line option for enabling tap networking
+		without using configuration files.
+		-x is now needed if one wants separate xterm windows for serial
+		I/O when using configuration files with a single machine.
+20210316	debugmsg subsystems can now be registered at runtime; this is
+		so far done from the Lance Ethernet device.
+		Adding a 'verbosity' debugger command for inspecting and
+		setting the verbosity level for individual subsystems.
+20210318	Fixing an annoying 'backspace' bug in the debugger command
+		line handling, where the response sometimes could become
+		"unknown command ''".
+		Implementing CTRL-W (erase word) in the debugger.
+		Implementing CTRL-T (SIGINFO-like status line) in the debugger.
+20210320	Removing the UNSTABLE_DEVEL configure define; it was not used
+		much, and the debugmsg verbosity levels can be used in its
+		place.
+		Fixing a bug for MIPS R2000/R3000 when writing to coprocessor 0
+		"entrylo" register (if the lowest 8 bits were 0, the code took
+		the non-R2000/R3000 code path).
+20210321	Adding an empty i960 CPU skeleton [again].
+		Moving 'arch' from struct machine to struct cpu; in the future,
+		perhaps this would allow a machine to have heterogenous CPU
+		sets (such as the Dreamcast with both SuperH and ARM).
+		Removing "slow_serial_interrupts_hack_for_linux" (-U) command
+		line option, since it is not used for most guest OSes, and
+		occupied a command line option char.
+20210323	Breaking out the mb89352 SCSI Protocol Controller from the
+		luna88k device, and beginning to implement it. Works well
+		enough for OpenBSD's "boot" to read the disk and load the
+		kernel, but not well enough for the kernel to like it.
+20210324	Adding support for 00 99 01 07 variant of luna88k a.out.
+20210325	The mb89352 SCSI controller uses its own subsystem for debug
+		messages.
+20210327	Adding an empty RISC-V CPU skeleton [again].
+		Implementing enough of the mb89352 to allow OpenBSD/luna88k
+		to boot with SCSI (both the boot loader and the kernel)!
+20210401	Applying a patch from George Matsumura to make things build
+		better on Linux: __attribute__((__packed__));  in bootblock.h.
+20210405	Adding hardcoded boot_unit=0 and boot_partition=0 NVRAM
+		variables to the LUNA-88K machine, allowing OpenBSD/luna88k
+		to boot from disk without asking for root and swap partitions.
+		Adding 'R' (upper-case) disk image prefix, as a shorthand for
+		creating temporary overlays.
+20210407	Code for idling the host processor has been moved out from
+		individual CPU implementations to the main emul loop.
+		Implementing an X11 mouse pointer grab mechanism. Grab is
+		activated by clicking in a framebuffer window, and released
+		using left CTRL + ALT. When grab is active, the host mouse
+		cursor is hidden and the window caption changes to indicate
+		that grab is active.
+20210408	Implementing an unusual 88K "not_maxneg_nor_zero" bcnd
+		condition.
+20210409	Moving the LUNA88K framebuffer to its own device file.
+		Beginning to implement the LUNA88K front panel LCD.
+		Also fixing a bug where the rightmost pixel (or 8 pixels in
+		the case of monochrome) were not drawn.
+20210410	Also check for X11R7 in the configure script, in addition
+		to X11R6.
+20210417	Porting over i960CA disassembly from the C++ framework.
+20210418	More i960 stuff, including re-adding the (so far dummy)
+		Cyclone VH machine.
+		Assuming availabilty of __func__ (C99 standard).
+20210422	Enabling idle detection for OpenBSD/luna88k, which uses a
+		bcnd.n instruction. A hack, but it seems to work.
+		Fixing a bug where console input could randomly be lost when
+		idling, if there were multiple emulated serial ports.
+
+==============  RELEASE 0.7.0  ==============
+
diff -Nru gxemul-0.6.2/LICENSE gxemul-0.7.0+dfsg/LICENSE
--- gxemul-0.6.2/LICENSE	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/LICENSE	2021-11-27 09:42:23.000000000 +0000
@@ -1,5 +1,5 @@
 
-Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
+Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
diff -Nru gxemul-0.6.2/Makefile.skel gxemul-0.7.0+dfsg/Makefile.skel
--- gxemul-0.6.2/Makefile.skel	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -8,28 +8,12 @@
 all: build
 
 build: do_src
-	$(CXX) $(COPTIM) src/components/*/*.o src/console/*.o src/cpus/*.o src/debugger/*.o src/devices/*.o src/disk/*.o src/file/*.o src/machines/*.o src/main/*.o src/main/*/*.o src/net/*.o src/old_main/*.o src/promemul/*.o src/symbol/*.o src/ui/*/*.o $(LIBS) -o $(BIN)
+	$(CC) $(COPTIM) src/console/*.o src/cpus/*.o src/debugger/*.o src/devices/*.o src/disk/*.o src/file/*.o src/machines/*.o src/net/*.o src/core/*.o src/promemul/*.o src/symbol/*.o $(LIBS) -o $(BIN)
 
 do_src:
 	cd src; $(MAKE)
 
-test: build
-	test/check_delete_calls.sh
-	@rm -f tmp_valgrind.out
-	$(VALGRIND) ./$(BIN) -WW@U
-	@if [ -s tmp_valgrind.out ]; then cat tmp_valgrind.out; false; fi
-
-documentation: build
-	doc/generate_machine_doc.sh
-	sed s/PAGETITLE/Machines/g < doc/head.html > doc/machines.html
-	./$(BIN) -WW@M >> doc/machines.html
-	cat doc/tail.html >> doc/machines.html
-	sed s/PAGETITLE/Components/g < doc/head.html > doc/components.html
-	./$(BIN) -WW@C >> doc/components.html
-	cat doc/tail.html >> doc/components.html
-	$(DOXYGEN) doc/Doxyfile
-
-install: documentation
+install:
 	@echo Installing binaries, man page, and documentation...
 	mkdir -p $(DESTDIR)$(PREFIX)/bin
 	cp -f $(BIN) $(DESTDIR)$(PREFIX)/bin/
@@ -46,8 +30,6 @@
 
 clean:
 	rm -f $(BIN) *core core.* *.gmon _* *.exe ktrace.out tmp_*.out* callgrind.out* cachegrind.out*
-	rm -f unittest*.h components*.h commands*.h
-	rm -rf doc/doxygen
 	cd src; $(MAKE) clean
 
 #  experiments and demos are not cleaned on a normal clean, only on a clean_all.
@@ -56,13 +38,10 @@
 	cd experiments; $(MAKE) clean_all
 	cd demos; $(MAKE) clean
 	rm -f config.h Makefile src/Makefile src/cpus/Makefile
-	rm -f src/ui/*/Makefile src/ui/Makefile src/main/fileloaders/Makefile
-	rm -f src/main/commands/Makefile
-	rm -f src/components/Makefile src/components/*/Makefile
 	rm -f src/debugger/Makefile src/devices/Makefile
 	rm -f src/devices/fonts/Makefile src/disk/Makefile
 	rm -f src/file/Makefile src/machines/Makefile
-	rm -f src/main/Makefile src/old_main/Makefile src/net/Makefile
+	rm -f src/main/Makefile src/core/Makefile src/net/Makefile
 	rm -f src/promemul/Makefile src/include/Makefile
 	rm -f src/useremul/Makefile src/include/Makefile
 	rm -f src/console/Makefile src/symbol/Makefile
diff -Nru gxemul-0.6.2/man/gxemul.1 gxemul-0.7.0+dfsg/man/gxemul.1
--- gxemul-0.6.2/man/gxemul.1	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/man/gxemul.1	2021-11-27 09:42:23.000000000 +0000
@@ -1,5 +1,5 @@
 .\"
-.\" Copyright (C) 2004-2019  Anders Gavare.  All rights reserved.
+.\" Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
 .\"
 .\" Redistribution and use in source and binary forms, with or without
 .\" modification, are permitted provided that the following conditions are met:
@@ -29,7 +29,7 @@
 .\"
 .\"     groff -man -Tascii gxemul.1    or    nroff -man gxemul.1
 .\"
-.Dd MAY 2019
+.Dd MARCH 2021
 .Dt GXEMUL 1
 .Os
 .Sh NAME
@@ -171,6 +171,10 @@
 images, which are offset by 11702 sectors, is 23965696.
 .It r
 Read-only (don't allow changes to be written to the file).
+.It R
+Don't allow changes to the file, but add a temporary overlay for the
+disk image to allow guest operating systems to write to the disk.
+(These changes are lost when the GXemul process exits.)
 .It s
 SCSI.
 .It t
@@ -230,6 +234,8 @@
 using this file. (In some emulation modes, eg. DECstation, this name is passed 
 along to the boot program. Useful names are "bsd" for OpenBSD/pmax, 
 "vmunix" for Ultrix, or "vmsprite" for Sprite.)
+.It Fl L Ar tapdev
+Enable tap networking using device 'tapdev', on systems that support it.
 .It Fl M Ar m
 Emulate
 .Ar m
@@ -327,21 +333,8 @@
 Halt if the emulated program attempts to access non-existing memory.
 .It Fl t
 Show a trace tree of all function calls being made.
-.It Fl U
-Enable slow_serial_interrupts_hack_for_linux.
 .It Fl X
 Use X11. This option enables graphical framebuffers.
-.It Fl x
-Open up new xterms for emulated serial ports. The default behaviour is to 
-open up xterms when using configuration files, or if X11 is enabled. When 
-starting up a simple emulation session with settings directly on the 
-command line, and neither
-.Fl X
-nor
-.Fl x
-is used, then all output is confined to the terminal that
-.Nm
-started in.
 .It Fl Y Ar n
 Scale down framebuffer windows by
 .Ar n
@@ -369,6 +362,8 @@
 .Pp
 General options:
 .Bl -tag -width Ds
+.It Fl A
+Disable colorized output.
 .It Fl c Ar cmd
 Add
 .Ar cmd
@@ -382,6 +377,9 @@
 However, if the emulated machine has clocks or timer interrupt sources,
 or if user interaction is taking place (e.g. keyboard input at irregular
 intervals), then this option is meaningless.
+.It Fl G
+Enable colorized output. If the environment variable CLICOLOR is set, then
+this is the default behavior.
 .It Fl H
 Display a list of available CPU types and machine types.
 (Most of these don't work. Please read the HTML documentation included in the
@@ -394,16 +392,31 @@
 .Ar n
 MB. The default size is 96 MB.
 .It Fl K
-Force the single-step debugger to be entered at the end of a simulation.
+Show the debugger prompt instead of exiting, when a simulation ends.
 .It Fl q
 Quiet mode; this suppresses startup messages.
 .It Fl V
-Start up in the single-step debugger, paused. If this option is used,
+Start up in the interactive debugger, paused. If this option is used,
 .Fl q
-is ignored.
+is ignored. This option also sets
+.Fl K.
 .It Fl v
 Increase verbosity (show more debug messages). This option can be used
 multiple times.
+.It Fl x
+Open up separate terminal windows for emulated serial ports. The default behaviour is to 
+open up new terminals when using configuration files with more than one machine
+specified, or if X11 is enabled. When starting up a simple emulation
+session with settings directly on the command line (or when using configuration
+files with a single machine specification), and neither
+.Fl X
+nor
+.Fl x
+is used, then all output is confined to the terminal that
+.Nm
+started in.
+The default terminal to use is 'xterm', but this can be overriden by
+the XTERM environment variable.
 .El
 .Pp
 Configuration file startup:
@@ -451,88 +464,6 @@
 .Pp
 In general, however, real ROM images require much more emulation detail 
 than GXemul provides, so they can usually not run.
-.Sh SYNOPSIS (NEW FRAMEWORK, EXPERIMENTAL)
-.Nm
-.Op options
-.Fl e
-.Ar name
-.Op additional components and files Ar ...
-.Nm
-.Op options
-.Ar configfile
-.Nm
-.Fl V
-.Nm
-.Fl H
-.Sh DESCRIPTION
-The options available for the new framework are:
-.Pp
-.Bl -tag -width Ds
-.It Fl B
-Enables snapshotting (required for reverse execution/stepping).
-.It Fl e Ar name
-Start with a machine based on template 'name'. The name may be followed by
-optional arguments in parentheses, e.g.
-.Pp
-.Dl "gxemul -V -e 'testmips(cpu=R4400)'"
-.Pp
-Remember to use quotes if your shell gives special meaning to parentheses.
-.It Fl H
-Display a list of available machine templates.
-.It Fl q
-Start up in Quiet mode (i.e. suppress debug messages). If an error occurs
-during emulation which stops execution and drops the user into the debugger,
-quiet mode is turned off.
-.It Fl V
-Start up in interactive mode, paused. If this option is used,
-.Fl q
-is ignored.
-.El
-.Pp
-When using the
-.Fl e
-option, the remainder of the command line consists of zero or more additional
-files to load, or components to add to the emulation setup.
-Including these on the command line is equivalent to using the 'add' command
-(although with a different syntax) in the interactive debugger.
-A simple example is a file name to load
-into the emulated machine, but they can be more complex as well. See the
-Adding Additional Components on the Command Line section below for more details.
-.Pp
-When not using the
-.Fl e
-option, the config file should be one that was previously saved from within
-the emulator using the 'save' command.
-.Pp
-Starting the emulator with the
-.Fl V
-switch will bring you to the interactive debugger environment, without
-starting the emulation.
-.Sh ADDING ADDITIONAL COMPONENTS ON THE COMMAND LINE
-The general syntax is:
-.Pp
-.Dl "existing_component_path:component(args)"
-.Pp
-If existing_component_path part is omitted, it is assumed to be cpu0.
-The component(args) part may be written as just args, in which case the
-name of the component is autodetected, and the args is given as an
-argument called "name" to that component.
-.Pp
-For example, if the additional component/filename is just
-.Pp
-.Dl "netbsd-GENERIC"
-.Pp
-this will be equivalent to
-.Pp
-.Dl "cpu0:file(name=netbsd-GENERIC)"
-.Pp
-An attempt will be made to load the file netbsd-GENERIC
-into cpu0, which is the default component if none is specified. This will most
-likely be expanded into root.machine0.mainbus0.cpu0. If cpu0 is ambiguous,
-then this will not work; the specific cpu0 name must be supplied instead, like
-this:
-.Pp
-.Dl "machine3.mainbus0.cpu0:netbsd-GENERIC"
 .Sh BUGS
 There are many bugs. Some of the known bugs are mentioned in the TODO 
 file in the
@@ -552,11 +483,11 @@
 obviously vary, depending on the current CPU load on the host.
 .Pp
 .Nm
-is in general not secure; when used as a "virtual machine" to run
-untrusted code in a guest OS, the untrusted code may be able to crash
-the emulator, or due to bugs, take over the host.
+is in general not guaranteed to be secure; when used as a virtual machine
+to run untrusted code in the form of a guest OS, the untrusted code may
+be able to crash the emulator, or due to bugs, take over the host.
 .Sh AUTHOR
-GXemul is Copyright (C) 2003-2019  Anders Gavare <gavare@gmail.com>
+GXemul is Copyright (C) 2003-2021  Anders Gavare <gavare@gmail.com>
 .Pp
 See http://gavare.se/gxemul/ for more information. For other Copyright
 messages, see the corresponding parts of the source code and/or
diff -Nru gxemul-0.6.2/README gxemul-0.7.0+dfsg/README
--- gxemul-0.6.2/README	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/README	2021-11-27 09:42:23.000000000 +0000
@@ -1,11 +1,11 @@
 
 
           --------------------------------------------------------
-             Gavare's eXperimental Emulator   --   GXemul 0.6.2
+             Gavare's eXperimental Emulator   --   GXemul 0.7.0
           --------------------------------------------------------
 
 
-                   Copyright (C) 2003-2019  Anders Gavare
+                   Copyright (C) 2003-2021  Anders Gavare
 
 
 Overview  --  What is GXemul?
@@ -22,10 +22,10 @@
 controllers, ethernet controllers, disk controllers, and serial port
 controllers.
 
-GXemul, including the dynamic translation system, is implemented in portable
-C++, which means that the emulator will (at least in theory) run on
-practically any modern host architecture and unix-like operating system, for
-which a C++ compiler is available.
+GXemul, including the dynamic translation system, is implemented in C, which
+means that the emulator will (at least in theory) run on practically any
+modern host architecture and unix-like operating system, for which a C99
+compiler is available.
 
 The documentation lists the machines and specific guest operating systems
 that can be regarded as "working" in GXemul. The guest operating system
diff -Nru gxemul-0.6.2/src/components/busses/MainbusComponent.cc gxemul-0.7.0+dfsg/src/components/busses/MainbusComponent.cc
--- gxemul-0.6.2/src/components/busses/MainbusComponent.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/busses/MainbusComponent.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,554 +0,0 @@
-/*
- *  Copyright (C) 2008-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "components/MainbusComponent.h"
-#include "GXemul.h"
-
-
-MainbusComponent::MainbusComponent()
-	: Component("mainbus", "mainbus")
-	, m_memoryMapFailed(false)
-	, m_memoryMapValid(false)
-	, m_currentAddressDataBus(NULL)
-{
-}
-
-
-MainbusComponent::~MainbusComponent()
-{
-}
-
-
-refcount_ptr<Component> MainbusComponent::Create(const ComponentCreateArgs& args)
-{
-	return new MainbusComponent();
-}
-
-
-string MainbusComponent::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "description")
-		return "A generic main bus.";
-
-	return Component::GetAttribute(attributeName);
-}
-
-
-void MainbusComponent::FlushCachedStateForComponent()
-{
-	m_memoryMap.clear();
-	m_memoryMapValid = false;
-	m_memoryMapFailed = false;
-
-	m_currentAddressDataBus = NULL;
-	
-	Component::FlushCachedStateForComponent();
-}
-
-
-bool MainbusComponent::PreRunCheckForComponent(GXemul* gxemul)
-{
-	FlushCachedStateForComponent();
-	if (!MakeSureMemoryMapExists(gxemul)) {
-		gxemul->GetUI()->ShowDebugMessage(GenerateTreeDump(""));
-		return false;
-	}
-
-	return true;
-}
-
-
-bool MainbusComponent::MakeSureMemoryMapExists(GXemul* gxemul)
-{
-	if (m_memoryMapFailed)
-		return false;
-
-	if (m_memoryMapValid)
-		return true;
-
-	m_memoryMap.clear();
-
-	m_memoryMapValid = true;
-	m_memoryMapFailed = false;
-
-	// Build a memory map of all immediate children who implement the
-	// AddressDataBus interface:
-	Components children = GetChildren();
-	for (size_t i=0; i<children.size(); ++i) {
-		AddressDataBus* bus = children[i]->AsAddressDataBus();
-		if (bus == NULL)
-			continue;
-
-		MemoryMapEntry mmEntry;
-		mmEntry.addressDataBus = bus;
-		mmEntry.addrMul = 1;
-		mmEntry.base = 0;
-
-		const StateVariable* varBase =
-		    children[i]->GetVariable("memoryMappedBase");
-		const StateVariable* varSize =
-		    children[i]->GetVariable("memoryMappedSize");
-		const StateVariable* varAddrMul =
-		    children[i]->GetVariable("memoryMappedAddrMul");
-
-		if (varBase != NULL)
-			mmEntry.base = varBase->ToInteger();
-		if (varSize != NULL)
-			mmEntry.size = varSize->ToInteger();
-		if (varAddrMul != NULL)
-			mmEntry.addrMul = varAddrMul->ToInteger();
-
-		// No base or size? Then skip this component.
-		if (varSize == NULL || varBase == NULL)
-			continue;
-
-		// Treat the non-sensical addrMul value 0 as 1.
-		if (mmEntry.addrMul == 0)
-			mmEntry.addrMul = 1;
-
-		// Empty memory mapped region? Then skip this component.
-		if (mmEntry.size == 0)
-			continue;
-
-		// Check for overlaps against the already existing mappings.
-		//
-		// (Note: Current implementation results in O(n^2) time,
-		// but if the number of memory-mapped immediate childs are
-		// few, then this should not be a big problem.)
-		for (size_t j=0; j<m_memoryMap.size(); ++j) {
-			if (mmEntry.base+mmEntry.size <= m_memoryMap[j].base)
-				continue;
-
-			if (mmEntry.base >= m_memoryMap[j].base +
-			    m_memoryMap[j].size)
-				continue;
-		
-			// There is overlap!
-			if (gxemul != NULL)
-				gxemul->GetUI()->ShowDebugMessage(this,
-				    "Error: the base and/or size of " +
-				    children[i]->GenerateShortestPossiblePath() +
-				    " conflicts with another memory mapped "
-				    "component on this bus.\n");
-
-			m_memoryMap.clear();
-			m_memoryMapValid = false;
-			m_memoryMapFailed = true;
-			return false;
-		}
-
-		// Finally add the new mapping entry.
-		m_memoryMap.push_back(mmEntry);
-	}
-
-	return true;
-}
-
-
-AddressDataBus* MainbusComponent::AsAddressDataBus()
-{
-	return this;
-}
-
-
-void MainbusComponent::AddressSelect(uint64_t address)
-{
-	MakeSureMemoryMapExists();
-
-	m_currentAddressDataBus = NULL;
-
-	if (!m_memoryMapValid)
-		return;
-
-	// Note: This is a linear O(n) scan of the list of memory-mapped
-	// components. For small n, this should be ok.
-	//
-	// In practice, my hope is that the bulk of all memory access will be
-	// using direct-mapped pages anyway, so this should not be that much
-	// of a problem.
-
-	for (size_t i=0; i<m_memoryMap.size(); ++i) {
-		MemoryMapEntry& mmEntry = m_memoryMap[i];
-
-		// If this memory map entry contains the address we wish to
-		// select, then...
-		if (address >= mmEntry.base &&
-		    address < mmEntry.base + mmEntry.size) {
-			// ... tell the corresponding component which address
-			// within it we wish to select.
-			m_currentAddressDataBus = mmEntry.addressDataBus;
-			m_currentAddressDataBus->AddressSelect(
-			    (address - mmEntry.base) / mmEntry.addrMul);
-			break;
-		}
-	}
-}
-
-
-bool MainbusComponent::ReadData(uint8_t& data, Endianness endianness)
-{
-	if (!MakeSureMemoryMapExists())
-		return false;
-
-	if (m_currentAddressDataBus != NULL)
-		return m_currentAddressDataBus->ReadData(data, endianness);
-	else
-		return false;
-}
-
-
-bool MainbusComponent::ReadData(uint16_t& data, Endianness endianness)
-{
-	if (!MakeSureMemoryMapExists())
-		return false;
-
-	if (m_currentAddressDataBus != NULL)
-		return m_currentAddressDataBus->ReadData(data, endianness);
-	else
-		return false;
-}
-
-
-bool MainbusComponent::ReadData(uint32_t& data, Endianness endianness)
-{
-	if (!MakeSureMemoryMapExists())
-		return false;
-
-	if (m_currentAddressDataBus != NULL)
-		return m_currentAddressDataBus->ReadData(data, endianness);
-	else
-		return false;
-}
-
-
-bool MainbusComponent::ReadData(uint64_t& data, Endianness endianness)
-{
-	if (!MakeSureMemoryMapExists())
-		return false;
-
-	if (m_currentAddressDataBus != NULL)
-		return m_currentAddressDataBus->ReadData(data, endianness);
-	else
-		return false;
-}
-
-
-bool MainbusComponent::WriteData(const uint8_t& data, Endianness endianness)
-{
-	if (!MakeSureMemoryMapExists())
-		return false;
-
-	if (m_currentAddressDataBus != NULL)
-		return m_currentAddressDataBus->WriteData(data, endianness);
-	else
-		return false;
-}
-
-
-bool MainbusComponent::WriteData(const uint16_t& data, Endianness endianness)
-{
-	if (!MakeSureMemoryMapExists())
-		return false;
-
-	if (m_currentAddressDataBus != NULL)
-		return m_currentAddressDataBus->WriteData(data, endianness);
-	else
-		return false;
-}
-
-
-bool MainbusComponent::WriteData(const uint32_t& data, Endianness endianness)
-{
-	if (!MakeSureMemoryMapExists())
-		return false;
-
-	if (m_currentAddressDataBus != NULL)
-		return m_currentAddressDataBus->WriteData(data, endianness);
-	else
-		return false;
-}
-
-
-bool MainbusComponent::WriteData(const uint64_t& data, Endianness endianness)
-{
-	if (!MakeSureMemoryMapExists())
-		return false;
-
-	if (m_currentAddressDataBus != NULL)
-		return m_currentAddressDataBus->WriteData(data, endianness);
-	else
-		return false;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_MainbusComponent_Creatable()
-{
-	refcount_ptr<Component> mainbus =
-	    ComponentFactory::CreateComponent("mainbus");
-
-	UnitTest::Assert("The MainbusComponent should be "
-	    "instanciable", !mainbus.IsNULL());
-}
-
-static void Test_MainbusComponent_AddressDataBus()
-{
-	refcount_ptr<Component> mainbus =
-	    ComponentFactory::CreateComponent("mainbus");
-
-	AddressDataBus* bus = mainbus->AsAddressDataBus();
-	UnitTest::Assert("The MainbusComponent should implement the "
-	    "AddressDataBus interface", bus != NULL);
-}
-
-static void Test_MainbusComponent_Simple()
-{
-	refcount_ptr<Component> mainbus =
-	    ComponentFactory::CreateComponent("mainbus");
-	refcount_ptr<Component> ram0 =
-	    ComponentFactory::CreateComponent("ram");
-
-	mainbus->AddChild(ram0);
-	ram0->SetVariableValue("memoryMappedSize", "0x100000");
-	ram0->SetVariableValue("memoryMappedBase", "0");
-
-	AddressDataBus* bus = mainbus->AsAddressDataBus();
-
-	uint8_t dataByte = 42;
-	bus->AddressSelect(128);
-	bus->WriteData(dataByte);
-	bus->AddressSelect(129);
-	dataByte = 100;
-	bus->WriteData(dataByte);
-	bus->AddressSelect(128);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("memory wasn't written to correctly?", dataByte, 42);
-	bus->AddressSelect(129);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("memory wasn't written to correctly?", dataByte, 100);
-}
-
-static void Test_MainbusComponent_Remapping()
-{
-	refcount_ptr<Component> mainbus =
-	    ComponentFactory::CreateComponent("mainbus");
-	refcount_ptr<Component> ram0 =
-	    ComponentFactory::CreateComponent("ram");
-
-	mainbus->AddChild(ram0);
-	ram0->SetVariableValue("memoryMappedSize", "0x10000");
-	ram0->SetVariableValue("memoryMappedBase", "0x1000");
-
-	AddressDataBus* bus = mainbus->AsAddressDataBus();
-
-	uint8_t dataByte = 123;
-	bus->AddressSelect(0x1030);	// offset 0x30 of ram0
-	bus->WriteData(dataByte);
-	dataByte = 18;
-	bus->AddressSelect(0x1050);	// offset 0x50 of ram0
-	bus->WriteData(dataByte);
-
-	// Set a new base for ram0, but do _NOT_ flush cached state yet!
-	// (This is to assert that cached state is actually cached.)
-	ram0->SetVariableValue("memoryMappedBase", "0x1020");
-
-	uint8_t dataByte2 = 99;
-	bus->AddressSelect(0x1050);	// offset 0x30 of ram0
-	bus->ReadData(dataByte2);
-	UnitTest::Assert("remapping should NOT have taken place yet, "
-	    "cached state should still be in effect!", dataByte2, 18);
-
-	// Now, flush the state and make sure the new mapping takes effect:
-	mainbus->FlushCachedState();
-
-	dataByte2 = 99;
-	bus->AddressSelect(0x1050);	// offset 0x30 of ram0
-	bus->ReadData(dataByte2);
-	UnitTest::Assert("remapping failed?", dataByte2, 123);
-}
-
-static void Test_MainbusComponent_Multiple_NonOverlapping()
-{
-	refcount_ptr<Component> mainbus =
-	    ComponentFactory::CreateComponent("mainbus");
-	refcount_ptr<Component> ram0 =
-	    ComponentFactory::CreateComponent("ram");
-	refcount_ptr<Component> ram1 =
-	    ComponentFactory::CreateComponent("ram");
-	refcount_ptr<Component> ram2 =
-	    ComponentFactory::CreateComponent("ram");
-
-	mainbus->AddChild(ram0);
-	mainbus->AddChild(ram1);
-	mainbus->AddChild(ram2);
-	ram0->SetVariableValue("memoryMappedSize", "0x100");
-	ram0->SetVariableValue("memoryMappedBase", "0x000");
-	ram1->SetVariableValue("memoryMappedSize", "0x100");
-	ram1->SetVariableValue("memoryMappedBase", "0x100");
-	ram2->SetVariableValue("memoryMappedSize", "0x100");
-	ram2->SetVariableValue("memoryMappedBase", "0x200");
-
-	AddressDataBus* bus = mainbus->AsAddressDataBus();
-
-	for (size_t i = 0; i < 0x300; i += sizeof(uint16_t)) {
-		uint16_t data = (uint8_t) i;
-		bus->AddressSelect(i);
-		bus->WriteData(data, LittleEndian);
-	}
-
-	for (size_t i = 0; i < 0x300; i += sizeof(uint16_t)) {
-		uint16_t data;
-		bus->AddressSelect(i);
-		bus->ReadData(data, BigEndian);
-		UnitTest::Assert("memory wasn't written to correctly?",
-		   data, (uint16_t) (i << 8));
-	}
-}
-
-static void Test_MainbusComponent_Simple_With_AddrMul()
-{
-	refcount_ptr<Component> mainbus =
-	    ComponentFactory::CreateComponent("mainbus");
-	refcount_ptr<Component> ram0 =
-	    ComponentFactory::CreateComponent("ram");
-
-	mainbus->AddChild(ram0);
-	ram0->SetVariableValue("memoryMappedSize", "0x1000");
-	ram0->SetVariableValue("memoryMappedBase", "0x80");
-	ram0->SetVariableValue("memoryMappedAddrMul", "5");
-
-	AddressDataBus* bus = mainbus->AsAddressDataBus();
-
-	uint8_t dataByte = 42;
-	bus->AddressSelect(128);
-	bus->WriteData(dataByte);
-	bus->AddressSelect(133);
-	dataByte = 100;
-	bus->WriteData(dataByte);
-
-	bus->AddressSelect(128);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("memory wasn't written to correctly?", dataByte, 42);
-	bus->AddressSelect(133);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("memory wasn't written to correctly?", dataByte, 100);
-
-	ram0->SetVariableValue("memoryMappedAddrMul", "2");
-	mainbus->FlushCachedState();
-
-	bus->AddressSelect(128);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("addr mul strangeness?", dataByte, 42);
-	bus->AddressSelect(130);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("offset 130 should have the same value as "
-	    "offset 133 had", dataByte, 100);
-	bus->AddressSelect(133);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("offset 133 should NOT have any value "
-	    "written to it yet!", dataByte, 0);
-
-	ram0->SetVariableValue("memoryMappedAddrMul", "1");
-	mainbus->FlushCachedState();
-
-	bus->AddressSelect(128);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("addr mul strangeness [2]", dataByte, 42);
-	bus->AddressSelect(129);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("offset 129 mismatch [2]", dataByte, 100);
-	bus->AddressSelect(133);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("offset 133 should NOT have any value "
-	    "written to it yet! [2]", dataByte, 0);
-
-	// AddrMul "0" should be same as "1", because the user might think that
-	// address multiplication is "turned off" by setting it to 0.
-	ram0->SetVariableValue("memoryMappedAddrMul", "0");
-	mainbus->FlushCachedState();
-
-	bus->AddressSelect(128);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("addr mul strangeness [3]", dataByte, 42);
-	bus->AddressSelect(129);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("offset 129 mismatch [3]", dataByte, 100);
-	bus->AddressSelect(133);
-	bus->ReadData(dataByte);
-	UnitTest::Assert("offset 133 should NOT have any value "
-	    "written to it yet! [3]", dataByte, 0);
-}
-
-static void Test_MainbusComponent_PreRunCheck()
-{
-	GXemul gxemul;
-
-	gxemul.GetCommandInterpreter().RunCommand("add testm88k");
-
-	UnitTest::Assert("preruncheck should initially succeed for testm88k",
-	    gxemul.GetRootComponent()->PreRunCheck(&gxemul) == true);
-
-	// Adding a second RAM component should succeed, since the initial size
-	// is 0, and does not (yet) conflict.
-	gxemul.GetCommandInterpreter().RunCommand("add ram mainbus0");
-	UnitTest::Assert("preruncheck should still succeed",
-	    gxemul.GetRootComponent()->PreRunCheck(&gxemul) == true);
-
-	// By changing the size to 42, the new ram1 component will overlap
-	// the ram0 component (at least partially).
-	gxemul.GetCommandInterpreter().RunCommand("ram1.memoryMappedSize = 42");
-	UnitTest::Assert("preruncheck should now fail",
-	    gxemul.GetRootComponent()->PreRunCheck(&gxemul) == false);
-}
-
-UNITTESTS(MainbusComponent)
-{
-	// Construction, etc.:
-	UNITTEST(Test_MainbusComponent_Creatable);
-	UNITTEST(Test_MainbusComponent_AddressDataBus);
-
-	// Memory mapping, ranges, overlaps, addrmul, etc.:
-	UNITTEST(Test_MainbusComponent_Simple);
-	UNITTEST(Test_MainbusComponent_Remapping);
-	UNITTEST(Test_MainbusComponent_Multiple_NonOverlapping);
-	UNITTEST(Test_MainbusComponent_Simple_With_AddrMul);
-
-	// TODO: Write outside of mapped space
-	// TODO: Write PARTIALLY outside of mapped space!!! e.g. 64-bit
-	//	into a 3-byte memory area???
-
-	UNITTEST(Test_MainbusComponent_PreRunCheck);
-}
-
-#endif
-
diff -Nru gxemul-0.6.2/src/components/busses/Makefile.skel gxemul-0.7.0+dfsg/src/components/busses/Makefile.skel
--- gxemul-0.6.2/src/components/busses/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/busses/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,19 +0,0 @@
-#
-#  Makefile for GXemul src/components/busses
-#
-
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(CPEDANTIC) $(INCLUDE2)
-LIBS=$(OTHERLIBS)
-
-OBJS=MainbusComponent.o
-
-all: $(OBJS)
-
-$(OBJS): Makefile
-
-clean:
-	rm -f $(OBJS)
-
-clean_all: clean
-	rm -f Makefile
-
diff -Nru gxemul-0.6.2/src/components/cpu/CPUComponent.cc gxemul-0.7.0+dfsg/src/components/cpu/CPUComponent.cc
--- gxemul-0.6.2/src/components/cpu/CPUComponent.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/cpu/CPUComponent.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,691 +0,0 @@
-/*
- *  Copyright (C) 2008-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <iomanip>
-
-#include "AddressDataBus.h"
-#include "components/CPUComponent.h"
-#include "GXemul.h"
-
-
-CPUComponent::CPUComponent(const string& className, const string& cpuArchitecture)
-	: Component(className, "cpu")	// all cpus have "cpu" as their
-					// visible class name, regardless of
-					// their actual class name
-	, m_frequency(33.0e6)
-	, m_paused(false)
-	, m_cpuArchitecture(cpuArchitecture)
-	, m_pageSize(0)
-	, m_pc(0)
-	, m_lastDumpAddr(0)
-	, m_lastUnassembleVaddr(0)
-	, m_hasUsedUnassemble(false)
-	, m_isBigEndian(true)
-	, m_showFunctionTraceCall(false)
-	, m_showFunctionTraceReturn(false)
-	, m_functionCallTraceDepth(0)
-	, m_nrOfTracedFunctionCalls(0)
-	, m_addressDataBus(NULL)
-{
-	AddVariable("architecture", &m_cpuArchitecture);
-	AddVariable("pc", &m_pc);
-	AddVariable("lastDumpAddr", &m_lastDumpAddr);
-	AddVariable("lastUnassembleVaddr", &m_lastUnassembleVaddr);
-	AddVariable("hasUsedUnassemble", &m_hasUsedUnassemble);
-	AddVariable("frequency", &m_frequency);
-	AddVariable("paused", &m_paused);
-	AddVariable("bigendian", &m_isBigEndian);
-	AddVariable("showFunctionTraceCall", &m_showFunctionTraceCall);
-	AddVariable("showFunctionTraceReturn", &m_showFunctionTraceReturn);
-	AddVariable("functionCallTraceDepth", &m_functionCallTraceDepth);
-	AddVariable("nrOfTracedFunctionCalls", &m_nrOfTracedFunctionCalls);
-}
-
-
-double CPUComponent::GetCurrentFrequency() const
-{
-        return m_frequency;
-}
-
-
-CPUComponent * CPUComponent::AsCPUComponent()
-{
-        return this;
-}
-
-
-void CPUComponent::ResetState()
-{
-	m_hasUsedUnassemble = false;
-	m_exceptionOrAbortInDelaySlot = false;
-	m_inDelaySlot = false;
-	m_delaySlotTarget = 0;
-
-	// Don't reset m_showFunctionTraceCall and Return here?
-	m_functionCallTraceDepth = 0;
-	m_nrOfTracedFunctionCalls = 0;
-
-	m_symbolRegistry.Clear();
-
-	Component::ResetState();
-}
-
-
-bool CPUComponent::FunctionTraceCall()
-{
-	stringstream ss;
-	for (int i=0; i<m_functionCallTraceDepth; ++i)
-		ss << "  ";
-
-	string symbol = GetSymbolRegistry().LookupAddress(PCtoInstructionAddress(m_pc), true);
-	if (symbol != "")
-		ss << symbol;
-
-	ss << "(";
-	int n = FunctionTraceArgumentCount();
-	for (int i=0; i<n; ++i) {
-		int64_t arg = FunctionTraceArgument(i);
-
-		if (arg > -1000 && arg < 1000) {
-			ss << arg;
-		} else {
-			ss.flags(std::ios::hex);
-			ss << "0x" << (uint64_t)arg;
-		}
-
-		// TODO: String and/or symbol lookup!
-
-		ss << ",";
-	}
-	ss << "...)\n";
-
-	GetUI()->ShowDebugMessage(this, ss.str());
-
-	++ m_nrOfTracedFunctionCalls;
-
-	++ m_functionCallTraceDepth;
-	if (m_functionCallTraceDepth > 100)
-		m_functionCallTraceDepth = 100;
-
-	GXemul* gxemul = GetRunningGXemulInstance();
-	if (gxemul != NULL && gxemul->IsInterrupting())
-		return false;
-
-	return true;
-}
-
-
-bool CPUComponent::FunctionTraceReturn()
-{
-	-- m_functionCallTraceDepth;
-	if (m_functionCallTraceDepth < 0)
-		m_functionCallTraceDepth = 0;
-
-	if (m_showFunctionTraceReturn) {
-		int64_t retval;
-		bool traceReturnValid = FunctionTraceReturnImpl(retval);
-		if (traceReturnValid) {
-			stringstream ss;
-			for (int i=0; i<m_functionCallTraceDepth; ++i)
-				ss << "  ";
-
-			if (retval > -1000 && retval < 1000) {
-				ss << "= " << retval;
-			} else {
-				ss.flags(std::ios::hex);
-				ss << "= 0x" << (uint64_t)retval;
-			}
-
-			// TODO: String and/or symbol lookup!
-
-			GetUI()->ShowDebugMessage(this, ss.str());
-		}
-
-		GXemul* gxemul = GetRunningGXemulInstance();
-		if (gxemul != NULL && gxemul->IsInterrupting())
-			return false;
-	}
-
-	return true;
-}
-
-
-void CPUComponent::GetMethodNames(vector<string>& names) const
-{
-	// Add our method names...
-	names.push_back("dump");
-	names.push_back("registers");
-	names.push_back("unassemble");
-
-	// ... and make sure to call the base class implementation:
-	Component::GetMethodNames(names);
-}
-
-
-bool CPUComponent::MethodMayBeReexecutedWithoutArgs(const string& methodName) const
-{
-	if (methodName == "dump")
-		return true;
-
-	if (methodName == "unassemble")
-		return true;
-
-	// ... and make sure to call the base class implementation:
-	return Component::MethodMayBeReexecutedWithoutArgs(methodName);
-}
-
-
-void CPUComponent::ExecuteMethod(GXemul* gxemul, const string& methodName,
-	const vector<string>& arguments)
-{
-	if (methodName == "dump") {
-		uint64_t vaddr = m_lastDumpAddr;
-
-		if (arguments.size() > 1) {
-			gxemul->GetUI()->ShowDebugMessage("syntax: .dump [addr]\n");
-			return;
-		}
-
-		if (arguments.size() == 1) {
-			gxemul->GetUI()->ShowDebugMessage("TODO: parse address expression\n");
-			gxemul->GetUI()->ShowDebugMessage("(for now, only hex immediate values are supported!)\n");
-
-			stringstream ss;
-			ss << arguments[0];
-			ss.flags(std::ios::hex);
-			ss >> vaddr;
-		}
-
-		const int nRows = 16;
-		for (int i=0; i<nRows; i++) {
-			const size_t len = 16;
-			unsigned char data[len];
-			bool readable[len];
-
-			stringstream ss;
-			ss.flags(std::ios::hex);
-
-			if (vaddr > 0xffffffff)
-				ss << std::setw(16);
-			else
-				ss << std::setw(8);
-
-			ss << std::setfill('0') << vaddr;
-
-			size_t k;
-			for (k=0; k<len; ++k) {
-				AddressSelect(vaddr + k);
-				readable[k] = ReadData(data[k], m_isBigEndian? BigEndian : LittleEndian);
-			}
-
-			ss << " ";
-
-			for (k=0; k<len; ++k) {
-				if ((k&3) == 0)
-					ss << " ";
-
-				ss << std::setw(2) << std::setfill('0');
-				if (readable[k])
-					ss << (int)data[k];
-				else
-					ss << "--";
-			}
-
-			ss << "  ";
-
-			for (k=0; k<len; ++k) {
-				char s[2];
-				s[0] = data[k] >= 32 && data[k] < 127? data[k] : '.';
-				s[1] = '\0';
-
-				if (readable[k])
-					ss << s;
-				else
-					ss << "-";
-			}
-
-			ss << "\n";
-
-			gxemul->GetUI()->ShowDebugMessage(ss.str());
-
-			vaddr += len;
-		}
-
-		m_lastDumpAddr = vaddr;
-
-		return;
-	}
-
-	if (methodName == "registers") {
-		ShowRegisters(gxemul, arguments);
-		return;
-	}
-
-	if (methodName == "unassemble") {
-		uint64_t vaddr = m_lastUnassembleVaddr;
-		if (!m_hasUsedUnassemble)
-			vaddr = PCtoInstructionAddress(m_pc);
-
-		if (arguments.size() > 1) {
-			gxemul->GetUI()->ShowDebugMessage("syntax: .unassemble [addr]\n");
-			return;
-		}
-
-		if (arguments.size() == 1) {
-			gxemul->GetUI()->ShowDebugMessage("TODO: parse address expression\n");
-			gxemul->GetUI()->ShowDebugMessage("(for now, only hex immediate values are supported!)\n");
-
-			stringstream ss;
-			ss << arguments[0];
-			ss.flags(std::ios::hex);
-			ss >> vaddr;
-		}
-
-		const int nRows = 20;
-
-		stringstream output;
-		vaddr = Unassemble(nRows, true, vaddr, output);
-		gxemul->GetUI()->ShowDebugMessage(output.str());
-
-		m_hasUsedUnassemble = true;
-		m_lastUnassembleVaddr = vaddr;
-		return;
-	}
-
-	// Call base...
-	Component::ExecuteMethod(gxemul, methodName, arguments);
-}
-
-
-uint64_t CPUComponent::Unassemble(int nRows, bool indicatePC, uint64_t vaddr, ostream& output)
-{
-	LookupAddressDataBus();
-	
-	vector< vector<string> > outputRows;
-
-	for (int i=0; i<nRows; i++) {
-		outputRows.push_back(vector<string>());
-
-		string symbol = GetSymbolRegistry().LookupAddress(vaddr, false);
-		if (symbol != "") {
-			outputRows[outputRows.size()-1].push_back("<" + symbol + ">");
-			outputRows.push_back(vector<string>());
-		}
-
-		stringstream ss;
-		ss.flags(std::ios::hex | std::ios::showbase);
-		ss << VirtualAddressAsString(vaddr);
-
-		if (indicatePC && PCtoInstructionAddress(m_pc) == vaddr)
-			ss << " <- ";
-		else
-			ss << "    ";
-
-		outputRows[outputRows.size()-1].push_back(ss.str());
-
-		if (m_addressDataBus == NULL) {
-			outputRows[outputRows.size()-1].push_back("; no address/data bus connected to the CPU");
-		} else {
-			vector<string> result;
-
-			size_t len = DisassembleInstruction(vaddr, result);
-			vaddr += len;
-
-			for (size_t j=0; j<result.size(); ++j)
-				outputRows[outputRows.size()-1].push_back(result[j]);
-
-			if (len == 0)
-				break;
-		}
-	}
-
-	// Output the rows with equal-width columns:
-	vector<size_t> columnWidths;
-	size_t row;
-	for (row=0; row<outputRows.size(); ++row) {
-		size_t nColumns = outputRows[row].size();
-
-		// Skip lines such as "<symbol>" on empty lines, when
-		// calculating column width.
-		if (nColumns <= 1)
-			continue;
-
-		if (columnWidths.size() < nColumns)
-			columnWidths.resize(nColumns);
-
-		for (size_t col=0; col<nColumns; ++col) {
-			const string& s = outputRows[row][col];
-			if (s.length() > columnWidths[col])
-				columnWidths[col] = s.length();
-		}
-	}
-
-	for (row=0; row<outputRows.size(); ++row) {
-		const vector<string>& rowVector = outputRows[row];
-
-		for (size_t i=0; i<rowVector.size(); ++i) {
-			// Note: i>=2 because:
-			// index 0 is the first column, no spaces before that one,
-			// but also: index 1 because the spaces after the vaddr
-			// is a special case ("<-" pc indicator).
-			if (i >= 2)
-				output << "   ";
-
-			size_t len = rowVector[i].length();
-			output << rowVector[i];
-			
-			int nspaces = columnWidths[i] - len;
-			for (int j=0; j<nspaces; ++j)
-				output << " ";
-		}
-
-		output << "\n";
-	}
-
-	return vaddr;
-}
-
-
-AddressDataBus * CPUComponent::AsAddressDataBus()
-{
-        return this;
-}
-
-
-void CPUComponent::FlushCachedStateForComponent()
-{
-	m_addressDataBus = NULL;
-
-	Component::FlushCachedStateForComponent();
-}
-
-
-bool CPUComponent::PreRunCheckForComponent(GXemul* gxemul)
-{
-	// If AddressDataBus lookup fails, then the CPU fails.
-	if (!LookupAddressDataBus(gxemul)) {
-		gxemul->GetUI()->ShowDebugMessage(this, "this CPU"
-		    " has neither any child components nor any parent component"
-		    " that can act as address/data bus, so there is no place"
-		    " to read instructions from\n");
-		return false;
-	}
-
-	return true;
-}
-
-
-bool CPUComponent::LookupAddressDataBus(GXemul* gxemul)
-{
-	if (m_addressDataBus != NULL)
-		return true;
-
-	// Find a suitable address data bus.
-	AddressDataBus *bus = NULL;
-
-	// 1) A direct first-level decendant of the CPU is probably a
-	//    cache. Use this if it exists.
-	//    If there are multiple AddressDataBus capable children,
-	//    print a debug warning, and just choose any of the children
-	//    (the last one).
-	Components& children = GetChildren();
-	Component* choosenChild = NULL;
-	bool multipleChildBussesFound = false;
-	for (size_t i=0; i<children.size(); ++i) {
-		AddressDataBus *childBus = children[i]->AsAddressDataBus();
-		if (childBus != NULL) {
-			if (bus != NULL)
-				multipleChildBussesFound = true;
-			bus = childBus;
-			choosenChild = children[i];
-		}
-	}
-
-	if (multipleChildBussesFound && gxemul != NULL)
-		gxemul->GetUI()->ShowDebugMessage(this, "warning: this CPU has "
-		    "multiple child components that can act as address/data busses; "
-		    "using " + choosenChild->GenerateShortestPossiblePath() + "\n");
-
-	// 2) If no cache exists, go to a parent bus (usually a mainbus).
-	if (bus == NULL) {
-		refcount_ptr<Component> component = GetParent();
-		while (!component.IsNULL()) {
-			bus = component->AsAddressDataBus();
-			if (bus != NULL)
-				break;
-			component = component->GetParent();
-		}
-	}
-
-	m_addressDataBus = bus;
-
-	return m_addressDataBus != NULL;
-}
-
-
-void CPUComponent::ShowRegisters(GXemul* gxemul, const vector<string>& arguments) const
-{
-	gxemul->GetUI()->ShowDebugMessage("The registers method has not yet "
-	    "been implemented for this CPU type. TODO.\n");
-}
-
-
-void CPUComponent::AddressSelect(uint64_t address)
-{
-	m_addressSelect = address;
-}
-
-
-bool CPUComponent::ReadData(uint8_t& data, Endianness endianness)
-{
-	if (!LookupAddressDataBus())
-		return false;
-
-	uint64_t paddr;
-	bool writable;
-	VirtualToPhysical(m_addressSelect, paddr, writable);
-
-	m_addressDataBus->AddressSelect(paddr);
-	return m_addressDataBus->ReadData(data, endianness);
-}
-
-
-bool CPUComponent::ReadData(uint16_t& data, Endianness endianness)
-{
-	assert((m_addressSelect & 1) == 0);
-
-	if (!LookupAddressDataBus())
-		return false;
-
-	uint64_t paddr;
-	bool writable;
-	VirtualToPhysical(m_addressSelect, paddr, writable);
-
-	m_addressDataBus->AddressSelect(paddr);
-	return m_addressDataBus->ReadData(data, endianness);
-}
-
-
-bool CPUComponent::ReadData(uint32_t& data, Endianness endianness)
-{
-	assert((m_addressSelect & 3) == 0);
-
-	if (!LookupAddressDataBus())
-		return false;
-
-	uint64_t paddr;
-	bool writable;
-	VirtualToPhysical(m_addressSelect, paddr, writable);
-
-	m_addressDataBus->AddressSelect(paddr);
-	return m_addressDataBus->ReadData(data, endianness);
-}
-
-
-bool CPUComponent::ReadData(uint64_t& data, Endianness endianness)
-{
-	assert((m_addressSelect & 7) == 0);
-
-	if (!LookupAddressDataBus())
-		return false;
-
-	uint64_t paddr;
-	bool writable;
-	VirtualToPhysical(m_addressSelect, paddr, writable);
-
-	m_addressDataBus->AddressSelect(paddr);
-	return m_addressDataBus->ReadData(data, endianness);
-}
-
-
-bool CPUComponent::WriteData(const uint8_t& data, Endianness endianness)
-{
-	if (!LookupAddressDataBus())
-		return false;
-
-	uint64_t paddr;
-	bool writable;
-	VirtualToPhysical(m_addressSelect, paddr, writable);
-
-	m_addressDataBus->AddressSelect(paddr);
-	return m_addressDataBus->WriteData(data, endianness);
-}
-
-
-bool CPUComponent::WriteData(const uint16_t& data, Endianness endianness)
-{
-	assert((m_addressSelect & 1) == 0);
-
-	if (!LookupAddressDataBus())
-		return false;
-
-	uint64_t paddr;
-	bool writable;
-	VirtualToPhysical(m_addressSelect, paddr, writable);
-
-	m_addressDataBus->AddressSelect(paddr);
-	return m_addressDataBus->WriteData(data, endianness);
-}
-
-
-bool CPUComponent::WriteData(const uint32_t& data, Endianness endianness)
-{
-	assert((m_addressSelect & 3) == 0);
-
-	if (!LookupAddressDataBus())
-		return false;
-
-	uint64_t paddr;
-	bool writable;
-	VirtualToPhysical(m_addressSelect, paddr, writable);
-
-	m_addressDataBus->AddressSelect(paddr);
-	return m_addressDataBus->WriteData(data, endianness);
-}
-
-
-bool CPUComponent::WriteData(const uint64_t& data, Endianness endianness)
-{
-	assert((m_addressSelect & 7) == 0);
-
-	if (!LookupAddressDataBus())
-		return false;
-
-	uint64_t paddr;
-	bool writable;
-	VirtualToPhysical(m_addressSelect, paddr, writable);
-
-	m_addressDataBus->AddressSelect(paddr);
-	return m_addressDataBus->WriteData(data, endianness);
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_CPUComponent_HasAttributes()
-{
-	UnitTest::Assert("the CPUComponent should not have attributes",
-	    !ComponentFactory::HasAttribute("cpu", "description"));
-}
-
-static void Test_CPUComponent_Create()
-{
-	// CPUComponent is abstract, and should not be possible to create.
-	refcount_ptr<Component> cpu =
-	    ComponentFactory::CreateComponent("cpu");
-	UnitTest::Assert("component was created?", cpu.IsNULL());
-}
-
-static void Test_CPUComponent_PreRunCheck()
-{
-	GXemul gxemul;
-
-	// Attempting to run a cpu with nothing connected to it should FAIL!
-	gxemul.GetCommandInterpreter().RunCommand("add m88k_cpu");
-	UnitTest::Assert("preruncheck should fail",
-	    gxemul.GetRootComponent()->PreRunCheck(&gxemul) == false);
-
-	// Running a CPU with RAM should however succeed:
-	gxemul.GetCommandInterpreter().RunCommand("add ram cpu0");
-	UnitTest::Assert("preruncheck should succeed",
-	    gxemul.GetRootComponent()->PreRunCheck(&gxemul) == true);
-}
-
-static void Test_CPUComponent_Methods_Reexecutableness()
-{
-	refcount_ptr<Component> cpu =
-	    ComponentFactory::CreateComponent("m88k_cpu");
-
-	UnitTest::Assert("dump method SHOULD be re-executable"
-	    " without args", cpu->MethodMayBeReexecutedWithoutArgs("dump") == true);
-
-	UnitTest::Assert("registers method should NOT be re-executable"
-	    " without args", cpu->MethodMayBeReexecutedWithoutArgs("registers") == false);
-
-	UnitTest::Assert("unassemble method SHOULD be re-executable"
-	    " without args", cpu->MethodMayBeReexecutedWithoutArgs("unassemble") == true);
-
-	UnitTest::Assert("nonexistant method should NOT be re-executable"
-	    " without args", cpu->MethodMayBeReexecutedWithoutArgs("nonexistant") == false);
-}
-
-UNITTESTS(CPUComponent)
-{
-	UNITTEST(Test_CPUComponent_HasAttributes);
-	UNITTEST(Test_CPUComponent_Create);
-	UNITTEST(Test_CPUComponent_PreRunCheck);
-	UNITTEST(Test_CPUComponent_Methods_Reexecutableness);
-}
-
-#endif
-
diff -Nru gxemul-0.6.2/src/components/cpu/CPUDyntransComponent.cc gxemul-0.7.0+dfsg/src/components/cpu/CPUDyntransComponent.cc
--- gxemul-0.6.2/src/components/cpu/CPUDyntransComponent.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/cpu/CPUDyntransComponent.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,799 +0,0 @@
-/*
- *  Copyright (C) 2008-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <iomanip>
-
-#include "AddressDataBus.h"
-#include "components/CPUDyntransComponent.h"
-#include "GXemul.h"
-
-
-CPUDyntransComponent::CPUDyntransComponent(const string& className, const string& cpuArchitecture)
-	: CPUComponent(className, cpuArchitecture)
-{
-	m_abortIC.f = instr_abort;
-}
-
-
-void CPUDyntransComponent::DyntransInit()
-{
-	m_nextIC = NULL;
-	m_firstIConPage = NULL;
-
-	m_dyntransICshift = GetDyntransICshift();
-
-	m_dyntransICentriesPerPage = m_pageSize >> m_dyntransICshift;
-	m_dyntransPageMask = (m_pageSize - 1) - ((1 << m_dyntransICshift) - 1);
-
-	int pageShift = 0;
-	while (pageShift < 32 && (1 << pageShift) != m_pageSize)
-		pageShift ++;
-
-	if (pageShift >= 32) {
-		std::cerr << "Non-power-of-2 page size?\n";
-		throw std::exception();
-	}
-
-	// 32 MB translation cache (per emulated CPU):
-	m_translationCache.Reinit(32 * 1024 * 1024, m_dyntransICentriesPerPage + DYNTRANS_PAGE_NSPECIALENTRIES, pageShift);
-}
-
-
-/*
- * Dynamic translation core
- * ------------------------
- *
- * The core of GXemul's dynamic translation is a simple function call to
- * an entry in an array of pointers. Each call also moves the pointer of the
- * next function call to the next entry in the array. For most simple
- * instruction implementations, the instruction call pointer (m_nextIC) does
- * not have to be modified, because it is assumed that an instruction will
- * change the program counter to the next instruction.
- *
- * Before starting the main loop, the pc is used to look up the correct
- * m_nextIC value, by calling DyntransPCtoPointers().
- *
- * During the loop, the pc value is _not_ necessarily updated for each
- * instruction call. Instead, the low bits of the pc value should be considered
- * meaningless, and the offset of the m_nextIC pointer within the current
- * code page (pointed to by m_firstIConPage) defines the lowest pc bits.
- *
- * After completing the main loop, the pc value is resynched by calling
- * DyntransResyncPC().
- */
-int CPUDyntransComponent::Execute(GXemul* gxemul, int nrOfCycles)
-{
-	DyntransInit();
-
-	DyntransPCtoPointers();
-
-	struct DyntransIC *ic = m_nextIC;
-	if (m_nextIC == NULL || m_firstIConPage == NULL) {
-		std::cerr << "Internal error: m_nextIC or m_firstIConPage is NULL.\n";
-		throw std::exception();
-	}
-
-	if (gxemul->GetRunState() == GXemul::SingleStepping) {
-		if (nrOfCycles != 1) {
-			std::cerr << "Internal error: Single stepping,"
-			    " but nrOfCycles = " << nrOfCycles << ".\n";
-			throw std::exception();
-		}
-
-		stringstream disasm;
-		Unassemble(1, false, PCtoInstructionAddress(m_pc), disasm);
-		gxemul->GetUI()->ShowDebugMessage(this, disasm.str());
-
-		m_nextIC->f = GetDyntransToBeTranslated();
-	}
-
-	/*
-	 * The normal instruction execution core: Get the instruction call pointer
-	 * (and move the nextIC to the following instruction in advance), then
-	 * execute the instruction call by calling its f.
-	 */
-#define IC	ic = m_nextIC ++; ic->f(this, ic);
-
-	m_nrOfCyclesToExecute = nrOfCycles;
-	m_executedCycles = 0;
-
-	// Starting inside a delay slot? Then execute it carefully:
-	if (m_inDelaySlot) {
-		m_nextIC->f = GetDyntransToBeTranslated();
-		m_executedCycles = m_nrOfCyclesToExecute - 1;
-		IC
-		m_executedCycles -= (m_nrOfCyclesToExecute - 1);
-		m_executedCycles ++;
-
-		// Fault in delay slot: return immediately.
-		if (m_nextIC->f == instr_abort) {
-			m_nextIC->f = GetDyntransToBeTranslated();
-			return 0;
-		}
-	}
-
-	// If possible, do some optimized loops of multiple inlined IC calls...
-	const int ICsPerLoop = 60;
-	const int maxICcycles = 2;	// TODO: Longer when instr combos are reimplemented
-	if (nrOfCycles > ICsPerLoop * maxICcycles) {
-		int hazard = nrOfCycles - ICsPerLoop * maxICcycles;
-
-		for (;;) {
-			IC IC IC IC IC   IC IC IC IC IC
-			IC IC IC IC IC   IC IC IC IC IC
-			IC IC IC IC IC   IC IC IC IC IC
-
-			IC IC IC IC IC   IC IC IC IC IC
-			IC IC IC IC IC   IC IC IC IC IC
-			IC IC IC IC IC   IC IC IC IC IC
-
-			m_executedCycles += ICsPerLoop;
-			if (m_executedCycles >= hazard ||
-			    m_nextIC->f == instr_abort)
-				break;
-		}
-	}
-
-	// ... then slowly execute the last few instructions.
-	// Note: -1, because the last thing we execute may be an instruction
-	// with a delay slot (which is automatically executed).
-	for (; m_executedCycles<nrOfCycles-1; ) {
-		int old = m_executedCycles;
-		IC
-		m_executedCycles ++;
-		if (m_executedCycles == old)
-			break;
-	}
-
-	// If there's one instruction left (and we're not aborted), then
-	// let's execute it:
-	if (m_executedCycles<nrOfCycles && m_nextIC->f != instr_abort) {
-		m_nextIC->f = GetDyntransToBeTranslated();
-		IC
-		m_executedCycles ++;
-	}
-
-	DyntransResyncPC();
-
-	// If execution aborted, then reset the aborting instruction slot
-	// to the to-be-translated function:
-	if (m_nextIC->f == instr_abort)
-		m_nextIC->f = GetDyntransToBeTranslated();
-
-	return m_executedCycles;
-}
-
-
-void CPUDyntransComponent::DyntransClearICPage(struct DyntransIC* icpage)
-{
-	// Fill the page with "to be translated" entries, which when executed
-	// will read the instruction from memory, attempt to translate it, and
-	// then execute it.
-	DyntransIC_t f = GetDyntransToBeTranslated();
-
-	for (int i=0; i<m_dyntransICentriesPerPage; ++i)
-		icpage[i].f = f;
-
-	// ... and set the entries after the last instruction slot to
-	// special "end of page" handlers. For architectures with delay slots,
-	// there need to be two, otherwise one would suffice.
-	icpage[m_dyntransICentriesPerPage + 0].f = CPUDyntransComponent::instr_endOfPage;
-	icpage[m_dyntransICentriesPerPage + 1].f = CPUDyntransComponent::instr_endOfPage2;
-}
-
-
-struct DyntransIC *CPUDyntransComponent::DyntransGetICPage(uint64_t addr)
-{
-	bool clear = false;
-	struct DyntransIC *icpage = m_translationCache.GetICPage(
-	    addr, m_showFunctionTraceCall, clear);
-
-	if (clear) {
-		// This is either
-		//
-		// a) a completely new page (the address was not in the cache),
-		// or
-		// b) a page which was translated before, but with different
-		//    settings (e.g. m_showFunctionTraceCall).
-		//
-		// So let's fill the page with suitable to-be-translated
-		// function pointers.
-		DyntransClearICPage(icpage);
-	}
-
-	return icpage;
-}
-
-
-void CPUDyntransComponent::DyntransPCtoPointers()
-{
-	if (m_nextIC != NULL && m_nextIC->f == instr_abort) {
-		// Already aborted, let's not update m_nextIC.
-		std::cerr << "TODO: Already aborted, let's not update m_nextIC."
-		    " Is this correct behavior?\n";
-		return;
-	}
-
-	m_firstIConPage = DyntransGetICPage(m_pc);
-
-	assert(m_firstIConPage != NULL);
-
-	// Here, m_firstIConPage points to a valid page. Calculate m_nextIC from
-	// the low bits of m_pc:
-	int offsetWithinPage = (m_pc & m_dyntransPageMask) >> m_dyntransICshift;
-	m_nextIC = m_firstIConPage + offsetWithinPage;
-}
-
-
-void CPUDyntransComponent::DyntransResyncPC()
-{
-	// Special case during aborts:
-	if (m_nextIC == &m_abortIC) {
-		// The situation which caused m_nextIC to be set to an abort
-		// IC must have synched PC just before that. So we don't need
-		// to do anything here.
-		return;
-	}
-
-	std::ptrdiff_t instructionIndex = m_nextIC - m_firstIConPage;
-
-	// On a page with e.g. 1024 instruction slots, instructionIndex is usually
-	// between 0 and 1023. This means that the PC points to within this
-	// page.
-	//
-	// We synchronize the PC by clearing out the bits within the IC page,
-	// and then adding the offset to the instruction.
-	if (instructionIndex >= 0 && instructionIndex < m_dyntransICentriesPerPage) {
-		m_pc &= ~m_dyntransPageMask;
-		m_pc += (instructionIndex << m_dyntransICshift);
-		return;
-	}
-
-	// However, the instruction index may point outside the IC page.
-	// This happens when synching the PC just after the last instruction
-	// on a page has been executed. This means that we set the PC to
-	// the start of the next page.
-	if (instructionIndex == m_dyntransICentriesPerPage) {
-		m_pc &= ~m_dyntransPageMask;
-		m_pc += (m_dyntransPageMask + (1 << m_dyntransICshift));
-		return;
-	}
-
-	if (instructionIndex == m_dyntransICentriesPerPage + 1) {
-		std::cerr << "TODO: DyntransResyncPC: Second end-of-page slot.\n";
-		// This may happen for delay-slot architectures.
-		throw std::exception();
-	}
-
-	std::cerr << "TODO: DyntransResyncPC: next ic outside of page?!\n";
-	throw std::exception();
-}
-
-
-void CPUDyntransComponent::DyntransToBeTranslatedBegin(struct DyntransIC* ic)
-{
-	// Resynchronize the PC to the instruction currently being translated.
-	// (m_nextIC should already have been increased, to point to the _next_
-	// instruction slot.)
-	m_nextIC = ic;
-	DyntransResyncPC();
-
-	// TODO: Check for m_pc breakpoints etc.
-
-	// First, let's assume that the translation will fail.
-	ic->f = NULL;
-}
-
-
-bool CPUDyntransComponent::DyntransReadInstruction(uint16_t& iword, int offset)
-{
-	// TODO: Fast lookup.
-
-	AddressSelect(PCtoInstructionAddress(m_pc + offset));
-	bool readable = ReadData(iword, m_isBigEndian? BigEndian : LittleEndian);
-
-	if (!readable) {
-		UI* ui = GetUI();
-		if (ui != NULL) {
-			stringstream ss;
-			ss.flags(std::ios::hex);
-			ss << "instruction at 0x" << PCtoInstructionAddress(m_pc + offset)
-			    << " could not be read!";
-			ui->ShowDebugMessage(this, ss.str());
-		}
-
-		return false;
-	}
-
-	return true;
-}
-
-
-bool CPUDyntransComponent::DyntransReadInstruction(uint32_t& iword, int offset)
-{
-	// TODO: Fast lookup.
-
-	AddressSelect(PCtoInstructionAddress(m_pc + offset));
-	bool readable = ReadData(iword, m_isBigEndian? BigEndian : LittleEndian);
-
-	if (!readable) {
-		UI* ui = GetUI();
-		if (ui != NULL) {
-			stringstream ss;
-			ss.flags(std::ios::hex);
-			ss << "instruction at 0x" << PCtoInstructionAddress(m_pc + offset)
-			    << " could not be read!";
-			ui->ShowDebugMessage(this, ss.str());
-		}
-		return false;
-	}
-
-	return true;
-}
-
-
-void CPUDyntransComponent::DyntransToBeTranslatedDone(struct DyntransIC* ic)
-{
-	bool abort = false;
-
-	if (ic->f == NULL || ic->f == instr_abort) {
-		abort = true;
-
-		// Instruction translation failed. If we were running in
-		// quiet mode, then simply dropping into the GXemul> prompt
-		// with no good explanation would be bad, so we always turn
-		// off quiet mode on Aborts:
-		GetRunningGXemulInstance()->SetQuietMode(false);
-
-		UI* ui = GetUI();
-		if (ui != NULL) {
-			bool isSingleStepping = GetRunningGXemulInstance()->GetRunState() == GXemul::SingleStepping;
-
-			stringstream ss;
-			ss.flags(std::ios::hex);
-			ss << "instruction translation failed";
-
-			// If we were single-stepping, then the instruction
-			// disassembly has already been displayed. If we were
-			// running in continuous mode, then we need to display
-			// it now:
-			if (!isSingleStepping) {
-				ss << " at";
-
-				string symbol = GetSymbolRegistry().LookupAddress(
-				    PCtoInstructionAddress(m_pc), true);
-				if (symbol != "")
-					ss << " " << symbol;
-
-				ss << ":\n";
-
-				Unassemble(1, false, PCtoInstructionAddress(m_pc), ss);
-			}
-
-			ui->ShowDebugMessage(this, ss.str());
-		}
-
-		if (ic->f == NULL)
-			ic->f = instr_abort;
-	}
-
-	// Finally, execute the translated instruction.
-	bool ds = m_inDelaySlot;
-	bool dsExceptionOrAbort = m_exceptionOrAbortInDelaySlot;
-	bool singleInstructionLeft = m_executedCycles == m_nrOfCyclesToExecute - 1;
-
-	m_nextIC = ic + 1;
-	ic->f(this, ic);
-
-	if (m_nextIC == &m_abortIC)
-		abort = true;
-
-	if (singleInstructionLeft && !abort) {
-		// If this instruction was in the delay slot of another instruction,
-		// and we are running a single instruction, then manually branch to
-		// the branch target:
-		if (ds && !dsExceptionOrAbort) {
-			m_pc = m_delaySlotTarget;
-			DyntransPCtoPointers();
-			m_inDelaySlot = false;
-			m_exceptionOrAbortInDelaySlot = false;
-		}
-
-		// Don't leave any "single instruction left" instructions
-		// in any of the slots:
-		ic->f = GetDyntransToBeTranslated();
-	}
-}
-
-
-/*****************************************************************************/
-
-
-/*
- * A do-nothing instruction. (It still counts as a cylce, though.)
- */
-DYNTRANS_INSTR(CPUDyntransComponent,nop)
-{
-}
-
-
-/*
- * A break-out-of-dyntrans function. Setting ic->f to this function will
- * cause dyntrans execution to be aborted. The cycle counter will _not_
- * count this as executed cycles.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,abort)
-{
-	// Cycle reduction:
-	-- cpubase->m_executedCycles;
-
-	// Are we in a delay slot?
-	if (cpubase->m_inDelaySlot)
-		cpubase->m_exceptionOrAbortInDelaySlot = true;
-
-	cpubase->m_nextIC = ic;
-}
-
-
-DYNTRANS_INSTR(CPUDyntransComponent,endOfPage)
-{
-	std::cerr << "TODO: endOfPage\n";
-	throw std::exception();
-}
-
-
-DYNTRANS_INSTR(CPUDyntransComponent,endOfPage2)
-{
-	std::cerr << "TODO: endOfPage2\n";
-	throw std::exception();
-}
-
-
-/*
- * arg 0: pointer to the new IC
- *
- * Branches within a dyntrans page.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,branch_samepage)
-{
-	cpubase->m_nextIC = (struct DyntransIC *) ic->arg[0].p;
-}
-
-
-/*
- * arg 0: 64-bit register
- * arg 1: 32-bit signed immediate
- *
- * Sets the register at arg 0 to the immediate value in arg 1.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,set_u64_imms32)
-{
-	REG64(ic->arg[0]) = (int32_t) ic->arg[1].u32;
-}
-
-
-/*
- * arg 0: 64-bit register
- * arg 1: 64-bit register
- *
- * Moves (copies) the contents of arg 1 to arg 0.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,mov_u64_u64)
-{
-	REG64(ic->arg[0]) = REG64(ic->arg[1]);
-}
-
-
-/*
- * arg 0: 32-bit register
- * arg 1: 32-bit register
- * arg 2: 32-bit unsigned immediate
- *
- * Adds the unsigned immediate to arg 1, and stores the result in arg 0.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,add_u32_u32_immu32)
-{
-	REG32(ic->arg[0]) = REG32(ic->arg[1]) + (uint32_t)ic->arg[2].u32;
-}
-
-
-/*
- * arg 0: 32-bit register
- * arg 1: 32-bit register
- * arg 2: 32-bit register
- *
- * Adds arg 1 and arg 2, and stores the result in arg 0.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,add_u32_u32_u32)
-{
-	REG32(ic->arg[0]) = REG32(ic->arg[1]) + REG32(ic->arg[2]);
-}
-
-
-/*
- * arg 0: 64-bit register
- * arg 1: 64-bit register
- * arg 2: 32-bit signed immediate
- *
- * Adds the signed immediate to arg 1, and stores the result in arg 0, truncated
- * to a signed 32-bit value.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,add_u64_u64_imms32_truncS32)
-{
-	REG64(ic->arg[0]) = (int32_t) (REG64(ic->arg[1]) + (int32_t)ic->arg[2].u32);
-}
-
-
-/*
- * arg 0: 64-bit register
- * arg 1: 64-bit register
- * arg 2: 64-bit register
- *
- * Adds the the registers in arg 1 and arg 2, and stores the result in arg 0
- * (truncated to a signed 32-bit value).
- */
-DYNTRANS_INSTR(CPUDyntransComponent,add_u64_u64_u64_truncS32)
-{
-	REG64(ic->arg[0]) = (int32_t) (REG64(ic->arg[1]) + REG64(ic->arg[2]));
-}
-
-
-/*
- * arg 0: 64-bit register
- * arg 1: 64-bit register
- * arg 2: 32-bit signed immediate
- *
- * Adds the signed immediate to arg 1, and stores the result in arg 0.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,add_u64_u64_imms32)
-{
-	REG64(ic->arg[0]) = REG64(ic->arg[1]) + (int64_t)(int32_t)ic->arg[2].u32;
-}
-
-
-/*
- * arg 0: 32-bit register
- * arg 1: 32-bit register
- * arg 2: 32-bit unsigned immediate
- *
- * Subtracts the unsigned immediate from arg 1, and stores the result in arg 0.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,sub_u32_u32_immu32)
-{
-	REG32(ic->arg[0]) = REG32(ic->arg[1]) - (uint32_t)ic->arg[2].u32;
-}
-
-
-/*
- * arg 0: 32-bit register
- * arg 1: 32-bit register
- * arg 2: 32-bit register
- *
- * Subtracts arg 2 from arg 1, and stores the result in arg 0.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,sub_u32_u32_u32)
-{
-	REG32(ic->arg[0]) = REG32(ic->arg[1]) - REG32(ic->arg[2]);
-}
-
-
-/*
- * arg 0: 64-bit register
- * arg 1: 64-bit register
- * arg 2: 64-bit register
- *
- * Subtracts arg2 from arg1, and stores the result in arg0
- * (truncated to a signed 32-bit value).
- */
-DYNTRANS_INSTR(CPUDyntransComponent,sub_u64_u64_u64_truncS32)
-{
-	REG64(ic->arg[0]) = (int32_t) (REG64(ic->arg[1]) - REG64(ic->arg[2]));
-}
-
-
-/*
- * arg 0: 32-bit register
- * arg 1: 32-bit register
- * arg 2: 32-bit unsigned immediate
- *
- * ANDs the 32-bit immediate into arg 1, storing the result in arg 0.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,and_u32_u32_immu32)
-{
-	REG32(ic->arg[0]) = REG32(ic->arg[1]) & ic->arg[2].u32;
-}
-
-
-/*
- * arg 0: 64-bit register
- * arg 1: 64-bit register
- * arg 2: 32-bit unsigned immediate
- *
- * ANDs the 32-bit immediate into arg 1, storing the result in arg 0.
- *
- * Note: No sign truncation is performed, i.e. if arg 1 is 0xffffffff80001234
- * and arg 2 is 0x80001200, then arg 0 becomes 0x0000000080001200 (note: the
- * upper bits are not sign-extended from bit 31).
- */
-DYNTRANS_INSTR(CPUDyntransComponent,and_u64_u64_immu32)
-{
-	REG64(ic->arg[0]) = REG64(ic->arg[1]) & (uint32_t)ic->arg[2].u32;
-}
-
-
-/*
- * arg 0: 32-bit register
- * arg 1: 32-bit register
- * arg 2: 32-bit unsigned immediate
- *
- * ORs arg 1 and arg 2 together, and stores the result in arg 0.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,or_u32_u32_immu32)
-{
-	REG32(ic->arg[0]) = REG32(ic->arg[1]) | ic->arg[2].u32;
-}
-
-
-/*
- * arg 0: 32-bit register
- * arg 1: 32-bit register
- * arg 2: 32-bit register
- *
- * ORs arg 1 and arg 2 together, and stores the result in arg 0.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,or_u32_u32_u32)
-{
-	REG32(ic->arg[0]) = REG32(ic->arg[1]) | REG32(ic->arg[2]);
-}
-
-
-/*
- * arg 0: 64-bit register
- * arg 1: 64-bit register
- * arg 2: 32-bit unsigned immediate
- *
- * ORs the 32-bit immediate into arg 1, storing the result in arg 0.
- *
- * Note: No sign truncation is performed, i.e. if arg 1 is 0x0000000000001234
- * and arg 2 is 0x80001200, then arg 0 becomes 0x0000000080001234 (note: the
- * upper bits are not sign extended from bit 31).
- */
-DYNTRANS_INSTR(CPUDyntransComponent,or_u64_u64_immu32)
-{
-	REG64(ic->arg[0]) = REG64(ic->arg[1]) | (uint32_t)ic->arg[2].u32;
-}
-
-
-/*
- * arg 0: 32-bit register
- * arg 1: 32-bit register
- * arg 2: 32-bit unsigned immediate
- *
- * XORs arg 1 and arg 2, and stores the result in arg 0.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,xor_u32_u32_immu32)
-{
-	REG32(ic->arg[0]) = REG32(ic->arg[1]) ^ ic->arg[2].u32;
-}
-
-
-/*
- * arg 0: 32-bit register
- * arg 1: 32-bit register
- * arg 2: 32-bit register
- *
- * XORs arg 1 and arg 2, and stores the result in arg 0.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,xor_u32_u32_u32)
-{
-	REG32(ic->arg[0]) = REG32(ic->arg[1]) ^ REG32(ic->arg[2]);
-}
-
-
-/*
- * arg 0: 64-bit register
- * arg 1: 64-bit register
- * arg 2: 32-bit unsigned immediate
- *
- * XORs the 32-bit immediate into arg 1, storing the result in arg 0.
- *
- * Note: No sign truncation is performed, i.e. if arg 1 is 0xffffffff80001234
- * and arg 2 is 0x80001200, then arg 0 becomes 0xffffffff00000034 (note: the
- * upper bits are not sign-extended from bit 31).
- */
-DYNTRANS_INSTR(CPUDyntransComponent,xor_u64_u64_immu32)
-{
-	REG64(ic->arg[0]) = REG64(ic->arg[1]) ^ (uint32_t)ic->arg[2].u32;
-}
-
-
-/*
- * arg 0: 64-bit register
- * arg 1: 64-bit register
- * arg 2: 64-bit register
- *
- * XORs the arg 1 and arg 2, storing the result in arg 0.
- *
- * Note: No sign truncation is performed, i.e. if arg 1 is 0xffffffff80001234
- * and arg 2 is 0x80001200, then arg 0 becomes 0xffffffff00000034 (note: the
- * upper bits are not sign-extended from bit 31).
- */
-DYNTRANS_INSTR(CPUDyntransComponent,xor_u64_u64_u64)
-{
-	REG64(ic->arg[0]) = REG64(ic->arg[1]) ^ REG64(ic->arg[2]);
-}
-
-
-/*
- * arg 0: 64-bit register
- * arg 1: 64-bit register
- * arg 2: 5-bit immediate
- *
- * Left-shifts arg 1 the number of steps indicated by the immediate, storing
- * the result in arg 0 truncated to a signed 32-bit value.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,shift_left_u64_u64_imm5_truncS32)
-{
-	REG64(ic->arg[0]) = (int32_t)(REG64(ic->arg[1]) << (ic->arg[2].u32 & 0x1f));
-}
-
-
-/*
- * arg 0: 64-bit register
- * arg 1: 64-bit register
- * arg 2: 5-bit immediate
- *
- * Right-shifts arg 1 (truncated into an unsigned 32-bit) the number of steps
- * indicated by the immediate, storing the result in arg 0 truncated to a 
- * signed 32-bit value.
- */
-DYNTRANS_INSTR(CPUDyntransComponent,shift_right_u64_u64asu32_imm5_truncS32)
-{
-	REG64(ic->arg[0]) = (int32_t)(((uint32_t)REG64(ic->arg[1])) >> (ic->arg[2].u32 & 0x1f));
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_CPUDyntransComponent_Dyntrans_PreReq()
-{
-	UnitTest::Assert("nr of dyntrans args too few", N_DYNTRANS_IC_ARGS >= 3);
-}
-
-UNITTESTS(CPUDyntransComponent)
-{
-	UNITTEST(Test_CPUDyntransComponent_Dyntrans_PreReq);
-}
-
-#endif
-
diff -Nru gxemul-0.6.2/src/components/cpu/I960_CPUComponent.cc gxemul-0.7.0+dfsg/src/components/cpu/I960_CPUComponent.cc
--- gxemul-0.6.2/src/components/cpu/I960_CPUComponent.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/cpu/I960_CPUComponent.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1167 +0,0 @@
-/*
- *  Copyright (C) 2018-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <stdio.h>
-#include <string.h>
-#include <iomanip>
-
-#include "ComponentFactory.h"
-#include "GXemul.h"
-#include "components/I960_CPUComponent.h"
-
-
-struct reg_instruction {
-	int opcode;
-	const char* mnemonic;
-	bool has_src1;
-	bool has_src2;
-	bool has_dst;
-	bool has_src3;	// true if the dst/src field is used as a source
-};
-
-struct reg_instruction reg_instructions[] = {
-	{ 0x580, "notbit",      true,  true,  true,  false },
-	{ 0x581, "and",         true,  true,  true,  false },
-	{ 0x582, "andnot",      true,  true,  true,  false },
-	{ 0x583, "setbit",      true,  true,  true,  false },
-	{ 0x584, "notand",      true,  true,  true,  false },
-	{ 0x586, "xor",         true,  true,  true,  false },
-	{ 0x587, "or",          true,  true,  true,  false },
-	{ 0x588, "nor",         true,  true,  true,  false },
-	{ 0x589, "xnor",        true,  true,  true,  false },
-	{ 0x58a, "not",         true,  false, true,  false },
-	{ 0x58b, "ornot",       true,  true,  true,  false },
-	{ 0x58c, "clrbit",      true,  true,  true,  false },
-	{ 0x58d, "notor",       true,  true,  true,  false },
-	{ 0x58e, "nand",        true,  true,  true,  false },
-	{ 0x58f, "alterbit",    true,  true,  true,  false },
-
-	{ 0x590, "addo",        true,  true,  true,  false },
-	{ 0x591, "addi",        true,  true,  true,  false },
-	{ 0x592, "subo",        true,  true,  true,  false },
-	{ 0x593, "subi",        true,  true,  true,  false },
-	{ 0x598, "shro",        true,  true,  true,  false },
-	{ 0x59a, "shrdi",       true,  true,  true,  false },
-	{ 0x59b, "shri" ,       true,  true,  true,  false },
-	{ 0x59c, "shlo",        true,  true,  true,  false },
-	{ 0x59d, "rotate",      true,  true,  true,  false },
-	{ 0x59e, "shli",        true,  true,  true,  false },
-
-	{ 0x5a0, "cmpo",        true,  true,  false, false },
-	{ 0x5a1, "cmpi",        true,  true,  false, false },
-	{ 0x5a2, "concmpo",     true,  true,  false, false },
-	{ 0x5a3, "concmpi",     true,  true,  false, false },
-	{ 0x5a4, "cmpinco",     true,  true,  true,  false },
-	{ 0x5a5, "cmpinci",     true,  true,  true,  false },
-	{ 0x5a6, "cmpdeco",     true,  true,  true,  false },
-	{ 0x5a7, "cmpdeci",     true,  true,  true,  false },
-
-	{ 0x5ac, "scanbyte",    true,  true,  false, false },
-	{ 0x5ae, "chkbit",      true,  true,  false, false },
-
-	{ 0x5b0, "addc",        true,  true,  true,  false },
-	{ 0x5b2, "subc",        true,  true,  true,  false },
-
-	{ 0x5cc, "mov",         true,  false, true,  false },
-	{ 0x5d8, "eshro",       true,  true,  true,  false },
-	{ 0x5dc, "movl",        true,  false, true,  false },
-	{ 0x5ec, "movt",        true,  false, true,  false },
-	{ 0x5fc, "movq",        true,  false, true,  false },
-
-	{ 0x630, "sdma",        true,  true,  true,  true  },
-	{ 0x631, "udma",        false, false, false, false },
-
-	{ 0x640, "spanbit",     true,  false, true,  false },
-	{ 0x641, "scanbit",     true,  false, true,  false },
-	{ 0x645, "modac",       true,  true,  true,  true  },
-
-	{ 0x650, "modify",      true,  true,  true,  true  },
-	{ 0x651, "extract",     true,  true,  true,  true  },
-	{ 0x654, "modtc",       true,  true,  true,  true  },
-	{ 0x655, "modpc",       true,  true,  true,  true  },
-	{ 0x659, "sysctl",      true,  true,  true,  true  },
-
-	{ 0x660, "calls",       true,  false, false, false },
-	{ 0x66b, "mark",        false, false, false, false },
-	{ 0x66c, "fmark",       false, false, false, false },
-	{ 0x66d, "flushreg",    false, false, false, false },
-	{ 0x66f, "syncf",       false, false, false, false },
-
-	{ 0x670, "emul",        true,  true,  true,  false },
-	{ 0x671, "ediv",        true,  true,  true,  false },
-
-	{ 0x701, "mulo",        true,  true,  true,  false },
-	{ 0x708, "remo",        true,  true,  true,  false },
-	{ 0x70b, "divo",        true,  true,  true,  false },
-
-	{ 0x741, "muli",        true,  true,  true,  false },
-	{ 0x748, "remi",        true,  true,  true,  false },
-	{ 0x749, "modi",        true,  true,  true,  false },
-	{ 0x74b, "divi",        true,  true,  true,  false },
-
-	{ 0,     NULL,          false, false, false, false }
-};
-
-
-I960_CPUComponent::I960_CPUComponent()
-	: CPUDyntransComponent("i960_cpu", "i960")
-{
-	m_frequency = 25e6;
-	m_isBigEndian = false;
-	m_model = "i960CA";
-
-	ResetState();
-
-	AddVariable("model", &m_model);
-
-	for (size_t i = 0; i < N_I960_REGS; i++) {
-		AddVariable(i960_regnames[i], &m_r[i]);
-	}
-
-	for (size_t i = 0; i < N_I960_SFRS; i++) {
-		stringstream ss;
-		ss << "sfr" << i;
-		AddVariable(ss.str(), &m_sfr[i]);
-	}
-
-	AddVariable("i960_ac", &m_i960_ac);
-	AddVariable("i960_pc", &m_i960_pc);
-	AddVariable("i960_tc", &m_i960_tc);
-	AddVariable("nr_of_valid_sfrs", &m_nr_of_valid_sfrs);
-}
-
-
-refcount_ptr<Component> I960_CPUComponent::Create(const ComponentCreateArgs& args)
-{
-	// Defaults:
-	ComponentCreationSettings settings;
-	settings["model"] = "i960CA";
-
-	if (!ComponentFactory::GetCreationArgOverrides(settings, args))
-		return NULL;
-
-	refcount_ptr<Component> cpu = new I960_CPUComponent();
-	if (!cpu->SetVariableValue("model", "\"" + settings["model"] + "\""))
-		return NULL;
-
-	return cpu;
-}
-
-
-static string regname_or_literal(int reg, int m, int s)
-{
-	// Regular g or r registers
-	if (m == 0 && s == 0)
-		return i960_regnames[reg];
-
-	stringstream ss;
-
-	if (m != 0 && s == 0) {
-		// Literal
-		ss << reg;
-	} else if (m == 0 && s != 0) {
-		// Special Function Register
-		ss << "sfr" << reg;
-	} else {
-		ss << "reserved" << reg;
-	}
-	
-	return ss.str();
-}
-
-
-void I960_CPUComponent::ResetState()
-{
-	m_pageSize = 4096;
-
-	for (size_t i=0; i<N_I960_REGS; i++)
-		m_r[i] = 0;
-
-	for (size_t i=0; i<N_I960_SFRS; i++)
-		m_sfr[i] = 0;
-
-	m_pc = 0;
-
-	m_i960_ac = 0;
-	m_i960_pc = 0;
-	m_i960_tc = 0;
-
-	// 0 for most (?) i960 implementations. 3 for i960CA. (TODO: CF etc)
-	m_nr_of_valid_sfrs = 0;
-	if (m_model == "i960CA")
-		m_nr_of_valid_sfrs = 3;
-
-	CPUDyntransComponent::ResetState();
-}
-
-
-bool I960_CPUComponent::PreRunCheckForComponent(GXemul* gxemul)
-{
-	if (m_pc & 0x3) {
-		gxemul->GetUI()->ShowDebugMessage(this, "the pc register"
-		    " can not have bit 0 or 1 set!\n");
-		return false;
-	}
-
-	return CPUDyntransComponent::PreRunCheckForComponent(gxemul);
-}
-
-
-bool I960_CPUComponent::CheckVariableWrite(StateVariable& var, const string& oldValue)
-{
-	// UI* ui = GetUI();
-
-	return CPUDyntransComponent::CheckVariableWrite(var, oldValue);
-}
-
-
-void I960_CPUComponent::ShowRegisters(GXemul* gxemul, const vector<string>& arguments) const
-{
-	stringstream ss;
-
-	ss.flags(std::ios::hex);
-	ss << "  ip = 0x" << std::setfill('0') << std::setw(8) << (uint32_t)m_pc;
-
-	string symbol = GetSymbolRegistry().LookupAddress(m_pc, true);
-	if (symbol != "")
-		ss << " <" << symbol << ">";
-	ss << "\n";
-
-	for (size_t i = 0; i < N_I960_REGS; i++) {
-		ss << std::setfill(' ') << std::setw(4) << i960_regnames[i]
-			<< " = 0x" << std::setfill('0') << std::setw(8) << m_r[i];
-		if ((i&3) == 3)
-			ss << "\n";
-		else
-			ss << " ";
-	}
-
-	for (size_t i = 0; i < m_nr_of_valid_sfrs; i++) {
-		stringstream name;
-		name << "sfr" << i;
-		ss << std::setfill(' ') << std::setw(6) << name.str()
-			<< " = 0x" << std::setfill('0') << std::setw(8) << m_sfr[i];
-		if ((i&3) == 3)
-			ss << "\n";
-		else
-			ss << " ";
-	}
-
-	gxemul->GetUI()->ShowDebugMessage(ss.str());
-}
-
-
-int I960_CPUComponent::FunctionTraceArgumentCount()
-{
-	return 8;
-}
-
-
-int64_t I960_CPUComponent::FunctionTraceArgument(int n)
-{
-	return m_r[I960_G0 + n];
-}
-
-
-bool I960_CPUComponent::FunctionTraceReturnImpl(int64_t& retval)
-{
-	retval = m_r[I960_G0];
-	return true;
-}
-
-
-int I960_CPUComponent::GetDyntransICshift() const
-{
-	// 4 bytes per instruction means 2 bits shift.
-	return 2;
-}
-
-
-void (*I960_CPUComponent::GetDyntransToBeTranslated())(CPUDyntransComponent*, DyntransIC*)
-{
-	return instr_ToBeTranslated;
-}
-
-
-bool I960_CPUComponent::VirtualToPhysical(uint64_t vaddr, uint64_t& paddr,
-	bool& writable)
-{
-	paddr = vaddr;
-	writable = true;
-	return true;
-}
-
-
-uint64_t I960_CPUComponent::PCtoInstructionAddress(uint64_t pc)
-{
-	return pc;
-}
-
-
-size_t I960_CPUComponent::DisassembleInstruction(uint64_t vaddr, vector<string>& result)
-{
-	size_t instrSize = sizeof(uint32_t);
-	uint32_t instructionWord;
-
-	// Read the instruction word:
-	AddressSelect(vaddr);
-	bool readOk = ReadData(instructionWord, m_isBigEndian? BigEndian : LittleEndian);
-	if (!readOk)
-		return 0;
-
-	const uint32_t iword = instructionWord;
-
-	const int opcode = iword >> 24;
-	
-	const int REG_src_dst  = (iword >> 19) & 0x1f;
-	const int REG_src2     = (iword >> 14) & 0x1f;
-	const int REG_m3       = (iword >> 13) & 0x1;
-	const int REG_m2       = (iword >> 12) & 0x1;
-	const int REG_m1       = (iword >> 11) & 0x1;
-	const int REG_opcode2  = (iword >> 7) & 0xf;
-	const int REG_sfr2     = (iword >> 6) & 0x1;
-	const int REG_sfr1     = (iword >> 5) & 0x1;
-	const int REG_src1     = (iword >> 0) & 0x1f;
-	
-	const int COBR_src_dst = (iword >> 19) & 0x1f;
-	const int COBR_src_2   = (iword >> 14) & 0x1f;
-	const int COBR_m1      = (iword >> 13) & 0x1;
-	const int COBR_disp    = (iword >> 2) & 0x7ff;
-	const int COBR_t       = (iword >> 1) & 0x1;
-	const int COBR_s2      = (iword >> 0) & 0x1;
-	
-	const int CTRL_disp    = (iword >> 2) & 0x3fffff;
-	const int CTRL_t       = (iword >> 1) & 0x1;
-
-	// const int MEMA_src_dst = (iword >> 19) & 0x1f; Same as MEMB_src_dst
-	const int MEMA_abase   = (iword >> 14) & 0x1f;
-	const int MEMA_md      = (iword >> 13) & 0x1;
-	// const int MEMA_zero    = (iword >> 12) & 0x1;  0 for MEMA, 1 for MEMB
-	const int MEMA_offset  = (iword >> 0) & 0xfff;
-
-	const int MEMB_src_dst = (iword >> 19) & 0x1f;
-	const int MEMB_abase   = (iword >> 14) & 0x1f;
-	const int MEMB_mode    = (iword >> 10) & 0xf;
-	const int MEMB_scale   = (iword >> 7) & 0x7;
-	// const int MEMB_sfr     = (iword >> 5) & 0x3;  Should be 00?
-	const int MEMB_index   = (iword >> 0) & 0x1f;
-
-	bool hasDisplacementWord = false;
-
-	if (opcode >= 0x80 && iword & 0x1000) {
-		/*  Only some MEMB instructions have displacement words:  */
-		int mode = (iword >> 10) & 0xf;
-		if (mode == 0x5 || mode >= 0xc)
-			hasDisplacementWord = true;		
-	}
-
-	uint32_t displacementWord = 0;
-	if (hasDisplacementWord) {
-		instrSize += sizeof(uint32_t);
-
-		// Read the displacement word:
-		AddressSelect(vaddr + sizeof(uint32_t));
-		readOk = ReadData(displacementWord, m_isBigEndian? BigEndian : LittleEndian);
-
-		if (!readOk)
-			return 0;
-	}
-
-	stringstream ssHex;
-	ssHex.flags(std::ios::hex);
-	ssHex << std::setfill('0') << std::setw(8) << (uint32_t) iword;
-	if (hasDisplacementWord)
-		ssHex << " " << std::setfill('0') << std::setw(8) << (uint32_t) displacementWord;
-	else
-		ssHex << "         ";
-
-	result.push_back(ssHex.str());
-
-
-	stringstream ssOpcode;
-	stringstream ssArgs;
-	stringstream ssComments;
-	
-	if (opcode >= 0x08 && opcode <= 0x1f) {
-		/*  CTRL:  */
-		const char* mnemonics[] = {
-				"b",			/*  0x08  */
-				"call",			/*  0x09  */
-				"ret",			/*  0x0a  */
-				"bal",			/*  0x0b  */
-				"unknown_ctrl_0x0c",	/*  0x0c  */
-				"unknown_ctrl_0x0d",	/*  0x0d  */
-				"unknown_ctrl_0x0e",	/*  0x0e  */
-				"unknown_ctrl_0x0f",	/*  0x0f  */
-				"bno",			/*  0x10  */
-				"bg",			/*  0x11  */
-				"be",			/*  0x12  */
-				"bge",			/*  0x13  */
-				"bl",			/*  0x14  */
-				"bne",			/*  0x15  */
-				"ble",			/*  0x16  */
-				"bo",			/*  0x17  */
-				"faultno",		/*  0x18  */
-				"faultg",		/*  0x19  */
-				"faulte",		/*  0x1a  */
-				"faultge",		/*  0x1b  */
-				"faultl",		/*  0x1c  */
-				"faultne",		/*  0x1d  */
-				"faultle",		/*  0x1e  */
-				"faulto"		/*  0x1f  */
-			};
-
-		ssOpcode << mnemonics[opcode - 0x08];
-		if (CTRL_t)
-			ssOpcode << ".f";
-
-		bool hasDisplacement = opcode < 0x18 && opcode != 0x0a;
-		if (hasDisplacement) {
-			uint32_t disp = CTRL_disp << 2;
-			if (disp & 0x00800000)
-				disp |= 0xff000000;
-
-			uint32_t addr = vaddr + disp;
-			ssArgs << "0x";
-			ssArgs.flags(std::ios::hex);
-			ssArgs << std::setfill('0') << std::setw(8) << addr;
-		}
-	} else if (opcode >= 0x20 && opcode <= 0x3f) {
-		/*  COBR:  */
-		const char* mnemonics[] = {
-				"testno",		/*  0x20  */
-				"testg",		/*  0x21  */
-				"teste",		/*  0x22  */
-				"testge",		/*  0x23  */
-				"testl",		/*  0x24  */
-				"testne",		/*  0x25  */
-				"testle",		/*  0x26  */
-				"testo",		/*  0x27  */
-
-				"unknown_cobr_0x28",	/*  0x28  */
-				"unknown_cobr_0x29",	/*  0x29  */
-				"unknown_cobr_0x2a",	/*  0x2a  */
-				"unknown_cobr_0x2b",	/*  0x2b  */
-				"unknown_cobr_0x2c",	/*  0x2c  */
-				"unknown_cobr_0x2d",	/*  0x2d  */
-				"unknown_cobr_0x2e",	/*  0x2e  */
-				"unknown_cobr_0x2f",	/*  0x2f  */
-
-				"bbc",			/*  0x30  */
-				"cmpobg",		/*  0x31  */
-				"cmpobe",		/*  0x32  */
-				"cmpobge",		/*  0x33  */
-				"cmpobl",		/*  0x34  */
-				"cmpobne",		/*  0x35  */
-				"cmpobne",		/*  0x36  */
-				"bbs",			/*  0x37  */
-
-				"cmpibno",		/*  0x38  */
-				"cmpibg",		/*  0x39  */
-				"cmpibe",		/*  0x3a  */
-				"cmpibge",		/*  0x3b  */
-				"cmpibl",		/*  0x3c  */
-				"cmpibne",		/*  0x3d  */
-				"cmpible",		/*  0x3e  */
-				"cmpibo",		/*  0x3f  */
-			};
-
-		ssOpcode << mnemonics[opcode - 0x20];
-		if (COBR_t)
-			ssOpcode << ".f";
-
-		bool src1isBitpos = opcode == 0x30 || opcode == 0x37;
-
-		if (opcode <= 0x27) {
-			ssArgs << regname_or_literal(COBR_src_dst, 0, COBR_s2);
-		} else {
-			uint32_t targ = COBR_disp << 2;
-			if (targ & 0x00001000)
-				targ |= 0xffffe000;
-			targ += vaddr;
-
-			ssArgs << regname_or_literal(COBR_src_dst, src1isBitpos ? 1 : COBR_m1, 0) << ",";
-			ssArgs << regname_or_literal(COBR_src_2, 0, COBR_s2) << ",";
-			ssArgs << "0x";
-			ssArgs.flags(std::ios::hex);
-			ssArgs << std::setfill('0') << std::setw(8) << targ;
-		}
-	} else if (opcode >= 0x58 && opcode <= 0x7f) {
-		/*  REG:  */
-		struct reg_instruction *rinstr = NULL;
-		for (int i = 0; ; ++i) {
-			if (reg_instructions[i].mnemonic == NULL)
-				break;
-			if (reg_instructions[i].opcode == (opcode << 4) + REG_opcode2) {
-				rinstr = &reg_instructions[i];
-				break;
-			}
-		}
-
-		bool has_src1 = true, has_src2 = true, has_dst = true, has_src3 = false;
-
-		if (rinstr == NULL) {
-			ssOpcode << "unknown_reg_";
-			ssOpcode.flags(std::ios::hex);
-			ssOpcode << std::setfill('0') << std::setw(2) << opcode;
-			ssOpcode << ":" << std::setw(1) << REG_opcode2;
-		} else {
-			ssOpcode << rinstr->mnemonic;
-			has_src1 = rinstr->has_src1;
-			has_src2 = rinstr->has_src2;
-			has_dst = rinstr->has_dst;
-			has_src3 = rinstr->has_src3;
-		}
-
-		if (has_src1)
-			ssArgs << regname_or_literal(REG_src1, REG_m1, REG_sfr1);
-
-		if (has_src2) {
-			if (ssArgs.str().length() > 0)
-				ssArgs << ",";
-			ssArgs << regname_or_literal(REG_src2, REG_m2, REG_sfr2);
-		}
-		
-		if (has_dst) {
-			if (ssArgs.str().length() > 0)
-				ssArgs << ",";
-			if (REG_m3) {
-				/*
-				 *  The manual for i960CA says (when M3 = 1):
-				 *
-				 *  "src/dst is a literal when used as a source
-				 *   or a special function register when used
-				 *   as a destination. M3 may not be 1 when
-				 *   src/dst is used both as a source and 
-				 *   destination in an instruction (atmod,
-				 *   modify, extract, modpc)."
-				 */
-				if (has_src3)
-					ssArgs << regname_or_literal(REG_src_dst, 1, 0);
-				else
-					ssArgs << regname_or_literal(REG_src_dst, 0, 1);
-			} else
-				ssArgs << regname_or_literal(REG_src_dst, 0, 0);
-		}
-	} else if (opcode >= 0x80 && opcode <= 0xcf) {
-		/*  MEM:  */
-		
-		/*  NOTE: These are for i960CA. When implementing support for
-		    other CPU variants, include an enum indicating which CPU
-		    it is for so that a warning can be printed for instructions
-		    that will cause faults on another CPU.  */
-		const char* mnemonics[] = {
-				"ldob",			/*  0x80  */
-				"unknown_mem_0x81",	/*  0x81 BiiN ldvob  */
-				"stob",			/*  0x82  */
-				"unknown_mem_0x83",	/*  0x83 BiiN stvob  */
-				"bx",			/*  0x84  */
-				"balx",			/*  0x85  */
-				"callx",		/*  0x86  */
-				"unknown_mem_0x87",	/*  0x87  */
-
-				"ldos",			/*  0x88  */
-				"unknown_mem_0x89",	/*  0x89 BiiN ldvos  */
-				"stos",			/*  0x8a  */
-				"unknown_mem_0x8b",	/*  0x8b BiiN stvos  */
-				"lda",			/*  0x8c  */
-				"unknown_mem_0x8d",	/*  0x8d  */
-				"unknown_mem_0x8e",	/*  0x8e  */
-				"unknown_mem_0x8f",	/*  0x8f  */
-
-				"ld",			/*  0x90  */
-				"unknown_mem_0x91",	/*  0x91 BiiN ldv  */
-				"st",			/*  0x92  */
-				"unknown_mem_0x93",	/*  0x93 Biin stv  */
-				"unknown_mem_0x94",	/*  0x94  */
-				"unknown_mem_0x95",	/*  0x95  */
-				"unknown_mem_0x96",	/*  0x96  */
-				"unknown_mem_0x97",	/*  0x97  */
-
-				"ldl",			/*  0x98  */
-				"unknown_mem_0x99",	/*  0x99 BiiN ldvl  */
-				"stl",			/*  0x9a  */
-				"unknown_mem_0x9b",	/*  0x9b BiiN stvl  */
-				"unknown_mem_0x9c",	/*  0x9c  */
-				"unknown_mem_0x9d",	/*  0x9d  */
-				"unknown_mem_0x9e",	/*  0x9e  */
-				"unknown_mem_0x9f",	/*  0x9f  */
-
-				"ldt",			/*  0xa0  */
-				"unknown_mem_0xa1",	/*  0xa1 BiiN ldvt  */
-				"stt",			/*  0xa2  */
-				"unknown_mem_0xa3",	/*  0xa3 Biin stvt  */
-				"unknown_mem_0xa4",	/*  0xa4  */
-				"unknown_mem_0xa5",	/*  0xa5  */
-				"unknown_mem_0xa6",	/*  0xa6  */
-				"unknown_mem_0xa7",	/*  0xa7  */
-
-				"unknown_mem_0xa8",	/*  0xa8  */
-				"unknown_mem_0xa9",	/*  0xa9  */
-				"unknown_mem_0xaa",	/*  0xaa  */
-				"unknown_mem_0xab",	/*  0xab  */
-				"unknown_mem_0xac",	/*  0xac  */
-				"unknown_mem_0xad",	/*  0xad  */
-				"unknown_mem_0xae",	/*  0xae  */
-				"unknown_mem_0xaf",	/*  0xaf  */
-
-				"ldq",			/*  0xb0  */
-				"unknown_mem_0xb1",	/*  0xb1 BiiN ldvq  */
-				"stq",			/*  0xb2  */
-				"unknown_mem_0xb3",	/*  0xb3 BiiN stvq  */
-				"unknown_mem_0xb4",	/*  0xb4  */
-				"unknown_mem_0xb5",	/*  0xb5  */
-				"unknown_mem_0xb6",	/*  0xb6  */
-				"unknown_mem_0xb7",	/*  0xb7  */
-
-				"unknown_mem_0xb8",	/*  0xb8  */
-				"unknown_mem_0xb9",	/*  0xb9  */
-				"unknown_mem_0xba",	/*  0xba  */
-				"unknown_mem_0xbb",	/*  0xbb  */
-				"unknown_mem_0xbc",	/*  0xbc  */
-				"unknown_mem_0xbd",	/*  0xbd  */
-				"unknown_mem_0xbe",	/*  0xbe  */
-				"unknown_mem_0xbf",	/*  0xbf  */
-
-				"ldib",			/*  0xc0  */
-				"unknown_mem_0xc1",	/*  0xc1 BiiN ldvib  */
-				"stib",			/*  0xc2  */
-				"unknown_mem_0xc3",	/*  0xc3 Biin stvib  */
-				"unknown_mem_0xc4",	/*  0xc4  */
-				"unknown_mem_0xc5",	/*  0xc5  */
-				"unknown_mem_0xc6",	/*  0xc6  */
-				"unknown_mem_0xc7",	/*  0xc7  */
-
-				"ldis",			/*  0xc8  */
-				"unknown_mem_0xc9",	/*  0xc9 BiiN ldvis  */
-				"stis",			/*  0xca  */
-				"unknown_mem_0xcb",	/*  0xcb BiiN stvis  */
-				"unknown_mem_0xcc",	/*  0xcc  */
-				"unknown_mem_0xcd",	/*  0xcd  */
-				"unknown_mem_0xce",	/*  0xce  */
-				"unknown_mem_0xcf",	/*  0xcf  */
-				
-				/*  BiiN:
-					d0 = ldm
-					d1 = ldvm
-					d2 = stm
-					d3 = stvm
-					d8 = ldml
-					d9 = ldvml
-					da = stml
-					db = stvml */
-			};
-
-		ssOpcode << mnemonics[opcode - 0x80];
-
-		bool usesDst = opcode != 0x84 && opcode != 0x86;
-		bool isStore = !!(opcode & 2);
-
-		if (usesDst && isStore) {
-			ssArgs << regname_or_literal(MEMB_src_dst, 0, 0) << ",";
-		}
-
-		if (iword & 0x1000) {
-			/*  MEMB:  */
-			int scale = 1 << MEMB_scale;
-			switch (MEMB_mode) {
-			case 0x4:
-				ssArgs << "(" << regname_or_literal(MEMB_abase, 0, 0) << ")";
-				break;
-			case 0x5:
-				{
-					uint32_t offset = displacementWord + 8;
-					ssArgs << "0x";
-					ssArgs.flags(std::ios::hex);
-					ssArgs << std::setfill('0') << std::setw(8) << offset;
-					ssArgs << "(ip)";
-				}
-				break;
-			case 0x7:
-				// (reg1)[reg2 * scale]
-				ssArgs << "(" << regname_or_literal(MEMB_abase, 0, 0) << ")";
-				ssArgs << "[" << regname_or_literal(MEMB_index, 0, 0) << "*" << scale << "]";
-				break;
-			case 0xc:
-			case 0xd:
-				{
-					uint32_t offset = displacementWord;
-					ssArgs << "0x";
-					ssArgs.flags(std::ios::hex);
-					ssArgs << std::setfill('0') << std::setw(8) << offset;
-					if (MEMB_mode == 0xd)
-						ssArgs << "(" << regname_or_literal(MEMB_abase, 0, 0) << ")";
-				}
-				break;
-			case 0xe:
-			case 0xf:
-				{
-					uint32_t offset = displacementWord;
-					ssArgs << "0x";
-					ssArgs.flags(std::ios::hex);
-					ssArgs << std::setfill('0') << std::setw(8) << offset;
-					if (MEMB_mode == 0xf)
-						ssArgs << "(" << regname_or_literal(MEMB_abase, 0, 0) << ")";
-					ssArgs << "[" << regname_or_literal(MEMB_index, 0, 0) << "*" << scale << "]";
-				}
-				break;
-			default:
-				ssArgs << "unimplemented MEMB mode!";
-			}
-		} else {
-			/*  MEMA:  */
-			ssArgs << "0x";
-			ssArgs.flags(std::ios::hex);
-			ssArgs << std::setfill('0') << std::setw(1) << MEMA_offset;
-
-			if (MEMA_md)
-				ssArgs << "(" << regname_or_literal(MEMA_abase, 0, 0) << ")";
-		}
-
-		if (usesDst && !isStore) {
-			ssArgs << "," << regname_or_literal(MEMB_src_dst, 0, 0);
-		}
-	} else if (iword == 0) {
-		ssOpcode << "--";
-	} else {
-		ssOpcode << "unknown_0x";
-		ssOpcode.flags(std::ios::hex);
-		ssOpcode << std::setfill('0') << std::setw(2) << (int)opcode;
-	}
-
-	result.push_back(ssOpcode.str());
-	result.push_back(ssArgs.str());
-	string comments = ssComments.str();
-	if (comments.length() > 0)
-		result.push_back(comments);
-
-	return instrSize;
-}
-
-
-string I960_CPUComponent::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "description")
-		return "Intel i960 processor.";
-
-	return Component::GetAttribute(attributeName);
-}
-
-
-/*****************************************************************************/
-
-
-DYNTRANS_INSTR(I960_CPUComponent,b)
-{
-	DYNTRANS_INSTR_HEAD(I960_CPUComponent)
-	cpu->m_pc = ic->arg[0].u32;
-	cpu->DyntransPCtoPointers();
-}
-
-
-DYNTRANS_INSTR(I960_CPUComponent,lda_displacement)
-{
-	DYNTRANS_INSTR_HEAD(I960_CPUComponent)
-	REG32(ic->arg[2]) = ic->arg[0].u32;
-	cpu->m_nextIC = ic + 2;
-}
-
-
-DYNTRANS_INSTR(I960_CPUComponent,mov_lit_reg)
-{
-	REG32(ic->arg[2]) = ic->arg[0].u32;
-}
-
-
-DYNTRANS_INSTR(I960_CPUComponent,mov_reg_reg)
-{
-	REG32(ic->arg[2]) = REG32(ic->arg[0]);
-}
-
-
-DYNTRANS_INSTR(I960_CPUComponent,sysctl)
-{
-	DYNTRANS_INSTR_HEAD(I960_CPUComponent)
-
-	uint32_t message = REG32(ic->arg[0]);
-	int type = (message >> 8) & 0xff;
-	int field1 = message & 0xff;
-	
-	// type 0 = software interrupt, src1 = vector number
-	// type 1 = invalidate cache
-	// type 2 = configure cache, src1 = cache mode configuration, src2 = cache load address
-	// type 3 = reinitialize, src2 = first-IP, src3 = PRCB address
-	// type 4 = load control register, src1 = register group number
-	
-	if (type == 0x01) {
-		// Invalidate cache.
-		// Right now in GXemul, this is a NOP.
-		UI* ui = cpu->GetUI();
-		ui->ShowDebugMessage(cpu, "invalidating cache (no-op for now)");
-	} else if (type == 0x04) {
-		// Load control register.
-		// TODO.
-		UI* ui = cpu->GetUI();
-		stringstream ss;
-		ss << "TODO: load control register, group " << field1;
-		ui->ShowDebugMessage(cpu, ss.str());
-	} else {
-		stringstream ss;
-		
-		// We didn't actually do anything in this instruction.
-		cpu->m_executedCycles --;
-
-		// Point to this instruction...
-		DYNTRANS_SYNCH_PC;
-
-		// ... and then abort.
-		cpu->m_nextIC = &cpu->m_abortIC;
-	
-		UI* ui = cpu->GetUI();
-		ss << "unimplemented sysctl message type " << type;
-		ui->ShowDebugMessage(cpu, ss.str());
-	}
-}
-
-
-/*****************************************************************************/
-
-
-void I960_CPUComponent::Translate(uint32_t iword, uint32_t iword2, struct DyntransIC* ic)
-{
-	UI* ui = GetUI();	// for debug messages
-
-	unsigned int opcode = iword >> 24;
-
-	if (opcode >= 0x08 && opcode <= 0x1f) {
-		/*  CTRL:  */
-		const int CTRL_disp    = (iword >> 2) & 0x3fffff;
-		uint32_t disp = CTRL_disp << 2;
-		if (disp & 0x00800000)
-			disp |= 0xff000000;
-
-		ic->arg[0].u32 = disp + m_pc;
-		
-		if (opcode == 0x08) {
-			ic->f = instr_b;
-		}
-	} else if (opcode >= 0x58 && opcode <= 0x7f) {
-		/*  REG:  */
-		const int REG_src_dst  = (iword >> 19) & 0x1f;
-		const int REG_src2     = (iword >> 14) & 0x1f;
-		const int REG_m3       = (iword >> 13) & 0x1;
-		const int REG_m2       = (iword >> 12) & 0x1;
-		const int REG_m1       = (iword >> 11) & 0x1;
-		const int REG_opcode2  = (iword >> 7) & 0xf;
-		const int REG_s2       = (iword >> 6) & 0x1;
-		const int REG_s1       = (iword >> 5) & 0x1;
-		const int REG_src1     = (iword >> 0) & 0x1f;
-
-		int op3 = (opcode << 4) + REG_opcode2;
-
-		if (REG_m1)
-			ic->arg[0].u32 = REG_src1;
-		else {
-			if (REG_s1)
-				ic->arg[0].p = &m_sfr[REG_src1];
-			else
-				ic->arg[0].p = &m_r[REG_src1];
-		}
-		
-		if (REG_m2)
-			ic->arg[1].u32 = REG_src2;
-		else {
-			if (REG_s2)
-				ic->arg[1].p = &m_sfr[REG_src1];
-			else
-				ic->arg[1].p = &m_r[REG_src2];
-		}
-		
-		if (REG_m3) {
-			// TODO: write to sfr.
-			if (ui != NULL)
-				ui->ShowDebugMessage(this, "unimplemented write to sfr");
-			return;
-		} else {
-			ic->arg[2].p = &m_r[REG_src_dst];
-		}
-
-		void (*f_lit_lit_reg)(CPUDyntransComponent*, struct DyntransIC*) = NULL;
-		void (*f_lit_reg_reg)(CPUDyntransComponent*, struct DyntransIC*) = NULL;
-		void (*f_reg_lit_reg)(CPUDyntransComponent*, struct DyntransIC*) = NULL;
-		void (*f_reg_reg_reg)(CPUDyntransComponent*, struct DyntransIC*) = NULL;
-
-		if (op3 == 0x5cc) {
-			// mov		NOTE: mov does not use src2.
-			f_lit_lit_reg = instr_mov_lit_reg;
-			f_lit_reg_reg = instr_mov_lit_reg;
-			f_reg_lit_reg = instr_mov_reg_reg;
-		} else if (op3 == 0x659) {
-			// sysctl
-			f_reg_reg_reg = instr_sysctl;
-		}
-
-		if (REG_m3 == 0) {
-			if (REG_m1 && REG_m2)
-				ic->f = f_lit_lit_reg;
-			if (REG_m1 && !REG_m2)
-				ic->f = f_lit_reg_reg;
-			if (!REG_m1 && REG_m2)
-				ic->f = f_reg_lit_reg;
-			if (!REG_m1 && !REG_m2)
-				ic->f = f_reg_reg_reg;
-		} else {
-			if (ui != NULL)
-				ui->ShowDebugMessage(this, "unimplemented write to sfr");
-		}
-	} else if (opcode >= 0x80 && opcode <= 0xcf) {
-		/*  MEM:  */
-//		const int MEMA_abase   = (iword >> 14) & 0x1f;
-		const int MEMA_md      = (iword >> 13) & 0x1;
-		const int MEMA_offset  = (iword >> 0) & 0xfff;
-		const int MEMB_src_dst = (iword >> 19) & 0x1f;
-//		const int MEMB_abase   = (iword >> 14) & 0x1f;
-		const int MEMB_mode    = (iword >> 10) & 0xf;
-//		const int MEMB_scale   = (iword >> 7) & 0x7;
-//		const int MEMB_index   = (iword >> 0) & 0x1f;
-
-		ic->arg[2].p = &m_r[MEMB_src_dst];
-
-		if (iword & 0x1000) {
-			/*  MEMB:  */
-			switch (MEMB_mode) {
-			case 0xc:
-				ic->arg[0].u32 = iword2;			
-				ic->f = instr_lda_displacement;
-				break;
-			default:
-				ui->ShowDebugMessage(this, "unimplemented MEMB_mode");
-			}
-		} else {
-			/*  MEMA:  */
-			if (MEMA_md)
-				ui->ShowDebugMessage(this, "TODO: MEMA");
-			else {
-				ic->arg[0].u32 = MEMA_offset;
-				ic->f = instr_mov_lit_reg;
-			}
-		}
-	}
-
-	if (ic->f == NULL && ui != NULL) {
-		stringstream ss;
-		ss.flags(std::ios::hex);
-		ss << "unimplemented opcode 0x" << opcode;
-		if (opcode >= 0x58 && opcode <= 0x7f)
-			ss << ",0x" << ((iword >> 7) & 0xf);
-		ui->ShowDebugMessage(this, ss.str());
-	}
-}
-
-
-DYNTRANS_INSTR(I960_CPUComponent,ToBeTranslated)
-{
-	DYNTRANS_INSTR_HEAD(I960_CPUComponent)
-
-	cpu->DyntransToBeTranslatedBegin(ic);
-
-	uint32_t iword;
-	if (cpu->DyntransReadInstruction(iword)) {
-		bool readCompleteInstruction = true;
-		uint32_t iword2 = 0;
-		uint32_t opcode = iword >> 24;
-		if (opcode >= 0x80 && opcode <= 0xcf) {
-			/*  Only some MEMB instructions have displacement words:  */
-			int mode = (iword >> 10) & 0xf;
-			if (mode == 0x5 || mode >= 0xc)
-				readCompleteInstruction = cpu->DyntransReadInstruction(iword2, 4);
-			if (!readCompleteInstruction) {
-				UI* ui = cpu->GetUI();
-				ui->ShowDebugMessage(cpu, "last part of instruction could not be read: TODO");
-			}
-		}
-		
-		if (readCompleteInstruction)
-			cpu->Translate(iword, iword2, ic);
-	}
-
-	cpu->DyntransToBeTranslatedDone(ic);
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_I960_CPUComponent_Create()
-{
-	refcount_ptr<Component> cpu = ComponentFactory::CreateComponent("i960_cpu");
-	UnitTest::Assert("component was not created?", !cpu.IsNULL());
-
-	const StateVariable * p = cpu->GetVariable("pfp");
-	UnitTest::Assert("cpu has no pfp state variable?", p != NULL);
-}
-
-static GXemul SimpleMachine()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add mainbus");
-	gxemul.GetCommandInterpreter().RunCommand("add i960_cpu mainbus0");
-	gxemul.GetCommandInterpreter().RunCommand("add ram mainbus0");
-	gxemul.GetCommandInterpreter().RunCommand("ram0.memoryMappedBase = 0x3fe00000");
-	gxemul.GetCommandInterpreter().RunCommand("ram0.memoryMappedSize = 0x1000");
-	return gxemul;
-}
-
-static void Test_I960_CPUComponent_Disassembly_Basic()
-{
-	GXemul gxemul = SimpleMachine();
-	refcount_ptr<Component> i960_cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
-	CPUComponent* cpu = i960_cpu->AsCPUComponent();
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-
-	vector<string> result;
-	size_t len;
-
-	// This assumes that the default endianness is little endian...
-	bus->AddressSelect(0x3fe00048);
-	bus->WriteData((uint32_t)0x8c683000, LittleEndian);
-	bus->AddressSelect(0x3fe0004c);
-	bus->WriteData((uint32_t)0x45342301, LittleEndian);
-
-	len = cpu->DisassembleInstruction(0x3fe00048, result);
-
-	UnitTest::Assert("disassembled instruction was wrong length?", len, 8);
-	UnitTest::Assert("disassembly result incomplete?", result.size(), 3);
-	UnitTest::Assert("disassembly result[0]", result[0], "8c683000 45342301");
-	UnitTest::Assert("disassembly result[1]", result[1], "lda");
-	UnitTest::Assert("disassembly result[2]", result[2], "0x45342301,r13");
-}
-
-static void Test_I960_CPUComponent_Execute_mov()
-{
-	GXemul gxemul = SimpleMachine();
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-
-	bus->AddressSelect(0x3fe00048);
-	bus->WriteData((uint32_t)0x5c201e06, LittleEndian);	// mov   6,r4
-	bus->AddressSelect(0x3fe0004c);
-	bus->WriteData((uint32_t)0x5c201e06, LittleEndian);	// mov   6,r4
-
-	cpu->SetVariableValue("pc", "0x3fe00048");
-	cpu->SetVariableValue("r4", "0x1234");
-
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("pc should have increased", cpu->GetVariable("pc")->ToInteger(), 0x3fe0004c);
-	UnitTest::Assert("r4 should have been modified", cpu->GetVariable("r4")->ToInteger(), 6);
-
-	cpu->SetVariableValue("r4", "0x12345");
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("pc should have increased again", cpu->GetVariable("pc")->ToInteger(), 0x3fe00050);
-	UnitTest::Assert("r4 should have been modified again", cpu->GetVariable("r4")->ToInteger(), 6);
-}
-
-static void Test_I960_CPUComponent_Execute_b()
-{
-	GXemul gxemul = SimpleMachine();
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-
-	bus->AddressSelect(0x3fe00004);
-	bus->WriteData((uint32_t)0x080006c0, LittleEndian);	// b 0x3fe006c4
-
-	cpu->SetVariableValue("pc", "0x3fe00004");
-
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("pc should have changed", cpu->GetVariable("pc")->ToInteger(), 0x3fe006c4);
-
-	cpu->SetVariableValue("pc", "0x3fe00004");
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("pc should have changed again", cpu->GetVariable("pc")->ToInteger(), 0x3fe006c4);
-}
-
-static void Test_I960_CPUComponent_Execute_lda_with_offset()
-{
-	GXemul gxemul = SimpleMachine();
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-
-	bus->AddressSelect(0x3fe00010);
-	bus->WriteData((uint32_t)0x8c180f13, LittleEndian);	// lda r3, 0xf13
-
-	cpu->SetVariableValue("pc", "0x3fe00010");
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1);
-	UnitTest::Assert("lda length", cpu->GetVariable("pc")->ToInteger(), 0x3fe00014);
-	UnitTest::Assert("lda", cpu->GetVariable("r3")->ToInteger(), 0xf13);
-}
-
-static void Test_I960_CPUComponent_Execute_lda_with_displacement()
-{
-	GXemul gxemul = SimpleMachine();
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-
-	bus->AddressSelect(0x3fe00010);
-	bus->WriteData((uint32_t)0x8cf03000, LittleEndian);	// lda
-	bus->AddressSelect(0x3fe00014);
-	bus->WriteData((uint32_t)0x3fe0507c, LittleEndian);	//     0x3fe0507c, g14
-
-	cpu->SetVariableValue("pc", "0x3fe00010");
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1);
-	UnitTest::Assert("lda length", cpu->GetVariable("pc")->ToInteger(), 0x3fe00018);
-	UnitTest::Assert("lda", cpu->GetVariable("g14")->ToInteger(), 0x3fe0507c);
-}
-
-UNITTESTS(I960_CPUComponent)
-{
-	UNITTEST(Test_I960_CPUComponent_Create);
-	UNITTEST(Test_I960_CPUComponent_Disassembly_Basic);
-
-	UNITTEST(Test_I960_CPUComponent_Execute_mov);
-	UNITTEST(Test_I960_CPUComponent_Execute_b);
-	UNITTEST(Test_I960_CPUComponent_Execute_lda_with_offset);
-	UNITTEST(Test_I960_CPUComponent_Execute_lda_with_displacement);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/components/cpu/M88K_CPUComponent.cc gxemul-0.7.0+dfsg/src/components/cpu/M88K_CPUComponent.cc
--- gxemul-0.6.2/src/components/cpu/M88K_CPUComponent.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/cpu/M88K_CPUComponent.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,2876 +0,0 @@
-/*
- *  Copyright (C) 2009-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <stdio.h>
-#include <string.h>
-#include <algorithm>
-#include <iomanip>
-
-#include "ComponentFactory.h"
-#include "GXemul.h"
-#include "components/M88K_CPUComponent.h"
-
-static const char* opcode_names[] = M88K_OPCODE_NAMES;
-static const char* opcode_names_3c[] = M88K_3C_OPCODE_NAMES;
-static const char* opcode_names_3d[] = M88K_3D_OPCODE_NAMES;
-static m88k_cpu_type_def cpu_type_defs[] = M88K_CPU_TYPE_DEFS;
-
-static const char *memop[4] = { ".d", "", ".h", ".b" };
-
-static const char *m88k_cr_names[] = M88K_CR_NAMES;
-//static const char *m88k_cr_197_names[] = M88K_CR_NAMES_197;
-
-static const char *m88k_cr_name(int i)
-{
-	const char **cr_names = m88k_cr_names;
-
-	// TODO: Is this really MVME197 specific? Or 88110?
-	//if (cpu->machine->machine_subtype == MACHINE_MVME88K_197)
-	//	cr_names = m88k_cr_197_names;
-
-	return cr_names[i];
-}
-
-
-M88K_CPUComponent::M88K_CPUComponent()
-	: CPUDyntransComponent("m88k_cpu", "Motorola 88000")
-	, m_m88k_type("88100")
-{
-	m_frequency = 50e6;	// 50 MHz
-
-	// Find (and cache) the cpu type in m_type:
-	memset((void*) &m_type, 0, sizeof(m_type));
-	for (size_t j=0; cpu_type_defs[j].name != NULL; j++) {
-		if (m_m88k_type == cpu_type_defs[j].name) {
-			m_type = cpu_type_defs[j];
-			break;
-		}
-	}
-
-	if (m_type.name == NULL) {
-		std::cerr << "Internal error: Unimplemented M88K type?\n";
-		throw std::exception();
-	}
-
-	AddVariable("model", &m_m88k_type);
-
-	for (size_t i=0; i<N_M88K_REGS; i++) {
-		stringstream ss;
-		ss << "r" << i;
-		AddVariable(ss.str(), &m_r[i]);
-	}
-
-	for (size_t i=0; i<N_M88K_CONTROL_REGS; i++) {
-		stringstream ss;
-		ss << "cr" << i;
-		AddVariable(ss.str(), &m_cr[i]);
-	}
-
-	for (size_t i=0; i<N_M88K_FPU_CONTROL_REGS; i++) {
-		stringstream ss;
-		ss << "fcr" << i;
-		AddVariable(ss.str(), &m_fcr[i]);
-	}
-
-	m_initial_r31 = 0x00000000;
-	AddVariable("initial_r31", &m_initial_r31);
-
-	AddVariable("inDelaySlot", &m_inDelaySlot);
-	AddVariable("delaySlotTarget", &m_delaySlotTarget);
-
-	ResetState();
-}
-
-
-refcount_ptr<Component> M88K_CPUComponent::Create(const ComponentCreateArgs& args)
-{
-	// Defaults:
-	ComponentCreationSettings settings;
-	settings["model"] = "88100";
-	settings["r31"] = "0x00000000";
-
-	if (!ComponentFactory::GetCreationArgOverrides(settings, args))
-		return NULL;
-
-	// Create the CPU...
-	refcount_ptr<Component> cpu = new M88K_CPUComponent();
-
-	// ... and apply settings:
-	if (!cpu->SetVariableValue("model", "\"" + settings["model"] + "\""))
-		return NULL;
-
-	if (!cpu->SetVariableValue("initial_r31", settings["r31"]))
-		return NULL;
-	if (!cpu->SetVariableValue("r31", settings["r31"]))
-		return NULL;
-
-	return cpu;
-}
-
-
-void M88K_CPUComponent::ResetState()
-{
-	m_pageSize = 4096;
-
-	// r0 .. r31 and the extra "r32/r0" zero register:
-	for (size_t i=0; i<N_M88K_REGS+1; i++)
-		m_r[i] = 0;
-
-	// ... but change r31 to the initial stack pointer value:
-	m_r[M88K_STACKPOINTER_REG] = m_initial_r31;
-
-	for (size_t i=0; i<N_M88K_CONTROL_REGS; i++)
-		m_cr[i] = 0;
-
-	for (size_t i=0; i<N_M88K_FPU_CONTROL_REGS; i++)
-		m_fcr[i] = 0;
-
-	m_pc = 0;
-
-	// Set the Processor ID:
-	m_cr[M88K_CR_PID] = m_type.pid | M88K_PID_MC;
-
-	// Start in supervisor mode, with interrupts disabled.
-	m_cr[M88K_CR_PSR] = M88K_PSR_MODE | M88K_PSR_IND;
-	if (!m_isBigEndian)
-		m_cr[M88K_CR_PSR] |= M88K_PSR_BO;
-
-	CPUDyntransComponent::ResetState();
-}
-
-
-bool M88K_CPUComponent::PreRunCheckForComponent(GXemul* gxemul)
-{
-	if (m_r[M88K_ZERO_REG] != 0) {
-		gxemul->GetUI()->ShowDebugMessage(this, "the r0 register "
-		    "must contain the value 0.\n");
-		return false;
-	}
-
-	if (m_pc > (uint64_t)0xffffffff) {
-		gxemul->GetUI()->ShowDebugMessage(this, "the pc register "
-		    "must be a 32-bit value.\n");
-		return false;
-	}
-
-	if (m_pc & 0x2) {
-		gxemul->GetUI()->ShowDebugMessage(this, "the pc register must have"
-		    " its lower two bits clear!\n");
-		return false;
-	}
-
-	if (m_r[N_M88K_REGS] != 0) {
-		gxemul->GetUI()->ShowDebugMessage(this, "internal error: the "
-		    "register following r31 must mimic the r0 register.\nIf"
-		    " you encounter this message, please write a bug report!\n");
-		return false;
-	}
-
-	return CPUDyntransComponent::PreRunCheckForComponent(gxemul);
-}
-
-
-bool M88K_CPUComponent::CheckVariableWrite(StateVariable& var, const string& oldValue)
-{
-	UI* ui = GetUI();
-
-	if (m_r[M88K_ZERO_REG] != 0) {
-		if (ui != NULL) {
-			ui->ShowDebugMessage(this, "the zero register (r0) "
-			    "must contain the value 0.\n");
-		}
-		return false;
-	}
-
-	if (m_m88k_type != m_type.name) {
-		bool found = false;
-		for (size_t j=0; cpu_type_defs[j].name != NULL; j++) {
-			if (m_m88k_type == cpu_type_defs[j].name) {
-				m_type = cpu_type_defs[j];
-				found = true;
-				break;
-			}
-		}
-
-		if (!found) {
-			if (ui != NULL) {
-				stringstream ss;
-				ss << "Unknown model \"" + m_m88k_type + "\". Available types are:\n";
-				for (size_t j=0; cpu_type_defs[j].name != NULL; j++) {
-					if ((j % 6) != 0)
-						ss << "\t";
-					ss << cpu_type_defs[j].name;
-					if ((j % 6) == 5)
-						ss << "\n";
-				}
-				ui->ShowDebugMessage(this, ss.str());
-			}
-			return false;
-		}
-	}
-
-	return CPUDyntransComponent::CheckVariableWrite(var, oldValue);
-}
-
-
-void M88K_CPUComponent::ShowRegisters(GXemul* gxemul, const vector<string>& arguments) const
-{
-	bool done = false;
-
-	stringstream ss;
-	ss.flags(std::ios::hex);
-
-	if (arguments.size() == 0 ||
-	    find(arguments.begin(), arguments.end(), "r") != arguments.end()) {
-		ss << "   pc = 0x" << std::setfill('0') << std::setw(8) << m_pc;
-
-		string symbol = GetSymbolRegistry().LookupAddress(m_pc, true);
-		if (symbol != "")
-			ss << "  <" << symbol << ">";
-		ss << "\n";
-
-		for (size_t i=0; i<N_M88K_REGS; i++) {
-			stringstream regname;
-			regname << "r" << i;
-		
-			ss << std::setfill(' ');
-			ss << std::setw(5) << regname.str() << " = 0x";
-			ss << std::setfill('0') << std::setw(8) << m_r[i];
-			if ((i&3) == 3)
-				ss << "\n";
-			else
-				ss << "  ";
-		}
-
-		done = true;
-	}
-
-	if (find(arguments.begin(), arguments.end(), "cr") != arguments.end()) {
-		for (size_t i=0; i<N_M88K_CONTROL_REGS; i++) {
-			stringstream regname;
-			regname << "cr" << i;
-		
-			ss << std::setfill(' ');
-			ss << std::setw(5) << regname.str() << " = 0x";
-			ss << std::setfill('0') << std::setw(8) << m_cr[i];
-			if ((i&3) == 3)
-				ss << "\n";
-			else
-				ss << "  ";
-		}
-
-		done = true;
-	}
-
-	if (find(arguments.begin(), arguments.end(), "crn") != arguments.end()) {
-		for (size_t i=0; i<N_M88K_CONTROL_REGS; i++) {
-			ss << std::setfill(' ');
-			ss << std::setw(5) << m88k_cr_name(i) << " = 0x";
-			ss << std::setfill('0') << std::setw(8) << m_cr[i];
-			if ((i&3) == 3)
-				ss << "\n";
-			else
-				ss << "  ";
-		}
-
-		done = true;
-	}
-
-	if (find(arguments.begin(), arguments.end(), "fcr") != arguments.end()) {
-		for (size_t i=0; i<N_M88K_FPU_CONTROL_REGS; i++) {
-			stringstream regname;
-			regname << "fcr" << i;
-		
-			ss << std::setfill(' ');
-			ss << std::setw(5) << regname.str() << " = 0x";
-			ss << std::setfill('0') << std::setw(8) << m_fcr[i];
-			if ((i&3) == 3)
-				ss << "\n";
-			else
-				ss << "  ";
-		}
-
-		done = true;
-	}
-
-	if (!done) {
-		ss << "M88K usage: .registers [r] [cr] [crn] [fcr]\n"
-		    "r   = pc and general purpose registers  (default)\n"
-		    "cr  = control registers\n"
-		    "crn = control registers with symbolic names instead of crX\n"
-		    "fcr = floating point control registers\n";
-	}
-
-	gxemul->GetUI()->ShowDebugMessage(ss.str());
-}
-
-
-int M88K_CPUComponent::GetDyntransICshift() const
-{
-	// 4 bytes per instruction, i.e. shift is 2 bits.
-	return M88K_INSTR_ALIGNMENT_SHIFT;
-}
-
-
-DyntransIC_t M88K_CPUComponent::GetDyntransToBeTranslated()
-{
-	return instr_ToBeTranslated;
-}
-
-
-bool M88K_CPUComponent::VirtualToPhysical(uint64_t vaddr, uint64_t& paddr,
-	bool& writable)
-{
-	// TODO. For now, just return paddr = vaddr.
-
-	paddr = vaddr & 0xffffffff;
-	writable = true;
-	return true;
-}
-
-
-void M88K_CPUComponent::Exception(int vector, int is_trap)
-{
-	std::cerr << "TODO: M88K exception\n";
-	throw std::exception();
-}
-
-
-size_t M88K_CPUComponent::DisassembleInstruction(uint64_t vaddr, vector<string>& result)
-{
-	size_t instrSize = sizeof(uint32_t);
-	uint32_t instructionWord;
-
-	// Read the instruction word:
-	AddressSelect(vaddr);
-	bool readOk = ReadData(instructionWord, m_isBigEndian? BigEndian : LittleEndian);
-	if (!readOk)
-		return 0;
-
-	const uint32_t iw = instructionWord;
-
-	// ... and add it to the result:
-	{
-		stringstream ss;
-		ss.flags(std::ios::hex);
-		ss << std::setfill('0') << std::setw(8) << (uint32_t) iw;
-		if (m_pc == vaddr && m_inDelaySlot)
-			ss << " (delayslot)";
-		result.push_back(ss.str());
-	}
-
-	const uint32_t op26   = (iw >> 26) & 0x3f;
-	const uint32_t op11   = (iw >> 11) & 0x1f;
-	const uint32_t op10   = (iw >> 10) & 0x3f;
-	const uint32_t d      = (iw >> 21) & 0x1f;
-	const uint32_t s1     = (iw >> 16) & 0x1f;
-	const uint32_t s2     =  iw        & 0x1f;
-	const uint32_t op3d   = (iw >>  8) & 0xff;
-	const uint32_t imm16  = iw & 0xffff;
-	const uint32_t w5     = (iw >>  5) & 0x1f;
-	const uint32_t cr6    = (iw >>  5) & 0x3f;
-	const int32_t  d16    = ((int16_t) (iw & 0xffff)) * 4;
-	const int32_t  d26    = ((int32_t)((iw & 0x03ffffff) << 6)) >> 4;
-
-	switch (op26) {
-
-	case 0x00:	/*  xmem.bu  */
-	case 0x01:	/*  xmem     */
-	case 0x02:	/*  ld.hu    */
-	case 0x03:	/*  ld.bu    */
-	case 0x04:	/*  ld.d     */
-	case 0x05:	/*  ld       */
-	case 0x06:	/*  ld.h     */
-	case 0x07:	/*  ld.b     */
-	case 0x08:	/*  st.d     */
-	case 0x09:	/*  st       */
-	case 0x0a:	/*  st.h     */
-	case 0x0b:	/*  st.b     */
-	case 0x10:	/*  and     */
-	case 0x11:	/*  and.u   */
-	case 0x12:	/*  mask    */
-	case 0x13:	/*  mask.u  */
-	case 0x14:	/*  xor     */
-	case 0x15:	/*  xor.u   */
-	case 0x16:	/*  or      */
-	case 0x17:	/*  or.u    */
-	case 0x18:	/*  addu    */
-	case 0x19:	/*  subu    */
-	case 0x1a:	/*  divu    */
-	case 0x1b:	/*  mulu    */
-	case 0x1c:	/*  add    */
-	case 0x1d:	/*  sub    */
-	case 0x1e:	/*  div    */
-	case 0x1f:	/*  cmp    */
-		if (iw == 0x00000000) {
-			result.push_back("-");
-		} else {
-			// Two registers (d, s1) and an immediate.
-			result.push_back(opcode_names[op26]);
-
-			stringstream ss;
-			ss << "r" << d << ",r" << s1;
-			ss.flags(std::ios::hex | std::ios::showbase);
-			ss << "," << imm16;
-			result.push_back(ss.str());
-		}
-		break;
-
-	case 0x20:
-		if ((iw & 0x001ff81f) == 0x00004000) {
-			result.push_back("ldcr");
-			stringstream ss;
-			ss << "r" << d << ",cr" << cr6;
-			result.push_back(ss.str());
-
-			stringstream comment;
-			comment << "; cr" << cr6 << " = " << m88k_cr_name(cr6);
-			result.push_back(comment.str());
-		} else if ((iw & 0x001ff81f) == 0x00004800) {
-			result.push_back("fldcr");
-			stringstream ss;
-			ss << "r" << d << ",fcr" << cr6;
-			result.push_back(ss.str());
-		} else if ((iw & 0x03e0f800) == 0x00008000) {
-			result.push_back("stcr");
-			stringstream ss;
-			ss << "r" << s1 << ",cr" << cr6;
-			result.push_back(ss.str());
-			if (s1 != s2)
-				result.push_back("; Weird encoding: s1 != s2");
-
-			stringstream comment;
-			comment << "; cr" << cr6 << " = " << m88k_cr_name(cr6);
-			result.push_back(comment.str());
-		} else if ((iw & 0x03e0f800) == 0x00008800) {
-			result.push_back("fstcr");
-			stringstream ss;
-			ss << "r" << s1 << ",fcr" << cr6;
-			result.push_back(ss.str());
-			if (s1 != s2)
-				result.push_back("; Weird encoding: s1 != s2");
-		} else if ((iw & 0x0000f800) == 0x0000c000) {
-			result.push_back("xcr");
-			stringstream ss;
-			ss << "r" << d << ",r" << s1 << ",cr" << cr6;
-			result.push_back(ss.str());
-			if (s1 != s2)
-				result.push_back("; Weird encoding: s1 != s2");
-
-			stringstream comment;
-			comment << "; cr" << cr6 << " = " << m88k_cr_name(cr6);
-			result.push_back(comment.str());
-		} else if ((iw & 0x0000f800) == 0x0000c800) {
-			result.push_back("fxcr");
-			stringstream ss;
-			ss << "r" << d << ",r" << s1 << ",fcr" << cr6;
-			result.push_back(ss.str());
-			if (s1 != s2)
-				result.push_back("; Weird encoding: s1 != s2");
-		} else {
-			result.push_back("unimpl_0x20_variant");
-		}
-		break;
-
-	case 0x21:
-		switch (op11) {
-		case 0x00:	/*  fmul  */
-		case 0x05:	/*  fadd  */
-		case 0x06:	/*  fsub  */
-		case 0x07:	/*  fcmp  */
-		case 0x0e:	/*  fdiv  */
-			{
-				stringstream ss;
-				switch (op11) {
-				case 0x00: ss << "fmul"; break;
-				case 0x05: ss << "fadd"; break;
-				case 0x06: ss << "fsub"; break;
-				case 0x07: ss << "fcmp"; break;
-				case 0x0e: ss << "fdiv"; break;
-				}
-				ss << "." <<
-				    (((iw >> 5) & 1)? "d" : "s") <<
-				    (((iw >> 9) & 1)? "d" : "s") <<
-				    (((iw >> 7) & 1)? "d" : "s");
-				result.push_back(ss.str());
-
-				stringstream ss2;
-				ss2 << "r" << d << ",r" << s1 << ",r" << s2;
-				result.push_back(ss2.str());
-			}
-			break;
-		case 0x04:	/*  flt  */
-			{
-				stringstream ss;
-				switch (op11) {
-				case 0x04: ss << "flt"; break;
-				}
-				ss << "." << (((iw >> 5) & 1)? "d" : "s") << "s";
-				result.push_back(ss.str());
-
-				stringstream ss2;
-				ss2 << "r" << d << ",r" << s2;
-				result.push_back(ss2.str());
-			}
-			break;
-		case 0x09:	/*  int  */
-		case 0x0a:	/*  nint  */
-		case 0x0b:	/*  trnc  */
-			{
-				stringstream ss;
-				switch (op11) {
-				case 0x09: ss << "int"; break;
-				case 0x0a: ss << "nint"; break;
-				case 0x0b: ss << "trnc"; break;
-				}
-				ss << ".s" << (((iw >> 7) & 1)? "d" : "s");
-				result.push_back(ss.str());
-
-				stringstream ss2;
-				ss2 << "r" << d << ",r" << s2;
-				result.push_back(ss2.str());
-			}
-			break;
-		default:{
-				stringstream ss;
-				ss << "unimpl_0x21, op11=" << op11;
-				result.push_back(ss.str());
-			}
-		}
-		break;
-
-	case 0x30:	/*  br  */
-	case 0x31:	/*  br.n  */
-	case 0x32:	/*  bsr  */
-	case 0x33:	/*  bsr.n  */
-		{
-			result.push_back(opcode_names[op26]);
-
-			stringstream ss;
-			ss.flags(std::ios::hex | std::ios::showbase);
-			ss << ((uint32_t) (vaddr + d26));
-			result.push_back(ss.str());
-
-			string symbol = GetSymbolRegistry().LookupAddress(
-			    (uint32_t) (vaddr + d26), true);
-			if (symbol != "")
-				result.push_back("; <" + symbol + ">");
-		}
-		break;
-
-	case 0x34:	/*  bb0    */
-	case 0x35:	/*  bb0.n  */
-	case 0x36:	/*  bb1    */
-	case 0x37:	/*  bb1.n  */
-	case 0x3a:	/*  bcnd    */
-	case 0x3b:	/*  bcnd.n  */
-		{
-			result.push_back(opcode_names[op26]);
-
-			stringstream ss;
-			if (op26 == 0x3a || op26 == 0x3b) {
-				/*  Attempt to decode bcnd condition:  */
-				switch (d) {
-				case 0x1: ss << "gt0"; break;
-				case 0x2: ss << "eq0"; break;
-				case 0x3: ss << "ge0"; break;
-				case 0x7: ss << "not_maxneg"; break;
-				case 0x8: ss << "maxneg"; break;
-				case 0xc: ss << "lt0"; break;
-				case 0xd: ss << "ne0"; break;
-				case 0xe: ss << "le0"; break;
-				default:  ss << "unk_" << d;
-				}
-			} else {
-				ss << d;
-			}
-
-			ss << ",r" << s1 << ",";
-
-			ss.flags(std::ios::hex | std::ios::showbase);
-			ss << ((uint32_t) (vaddr + d16));
-			result.push_back(ss.str());
-
-			string symbol = GetSymbolRegistry().LookupAddress(
-			    (uint32_t) (vaddr + d16), true);
-			if (symbol != "")
-				result.push_back("; <" + symbol + ">");
-		}
-
-		break;
-
-	case 0x3c:
-		if ((iw & 0x0000f000)==0x1000 || (iw & 0x0000f000)==0x2000) {
-			/*  Load/store:  */
-			stringstream ss;
-			ss << ((iw & 0x0000f000) == 0x1000? "ld" : "st");
-
-			switch (iw & 0x00000c00) {
-			case 0x000: ss << ".d"; break;
-			case 0x400: break;
-			case 0x800: ss << ".x"; break;
-			default: ss << ".UNIMPLEMENTED";
-			}
-
-			if (iw & 0x100)
-				ss << ".usr";
-			if (iw & 0x80)
-				ss << ".wt";
-
-			result.push_back(ss.str());
-
-			stringstream ss2;
-			ss2 << "r" << d << ",r" << s1;
-			if (iw & 0x200)
-				ss2 << "[r" << s2 << "]";
-			else
-				ss2 << ",r" << s2;
-
-			result.push_back(ss2.str());
-		} else switch (op10) {
-		case 0x20:	/*  clr  */
-		case 0x22:	/*  set  */
-		case 0x24:	/*  ext  */
-		case 0x26:	/*  extu  */
-		case 0x28:	/*  mak  */
-		case 0x2a:	/*  rot  */
-			/*  Two-register plus bit position/length:  */
-			{
-				result.push_back(opcode_names_3c[op10]);
-
-				stringstream ss;
-				ss << "r" << d << ",r" << s1 << ",";
-
-				/*  Don't include w5 for the rot instruction:  */
-				if (op10 != 0x2a)
-					ss << w5;
-
-				/*  Note: o5 = s2:  */
-				ss << "<" << s2 << ">";
-
-				result.push_back(ss.str());
-			}
-			break;
-		case 0x34:	/*  tb0  */
-		case 0x36:	/*  tb1  */
-			/*  B5 bit index, register, plus 9-bit immediate vector:  */
-			{
-				result.push_back(opcode_names_3c[op10]);
-
-				stringstream ss;
-				ss << d << ",r" << s1 << ",";
-				ss.flags(std::ios::hex | std::ios::showbase);
-				ss << (iw & 0x1ff);
-				result.push_back(ss.str());
-			}
-			break;
-		default:{
-				stringstream ss;
-				ss << "unimpl_" << opcode_names_3c[op10];
-				result.push_back(ss.str());
-			}
-		}
-		break;
-
-	case 0x3d:
-		if ((iw & 0xf000) <= 0x3fff) {
-			/*  Load, Store, xmem, and lda:  */
-			stringstream op;
-			
-			switch (iw & 0xf000) {
-			case 0x2000: op << "st"; break;
-			case 0x3000: op << "lda"; break;
-			default:     if ((iw & 0xf800) >= 0x0800)
-					op << "ld";
-				     else
-					op << "xmem";
-			}
-			
-			if ((iw & 0xf000) >= 0x1000) {
-				/*  ld, st, lda  */
-				op << memop[(iw >> 10) & 3];
-			} else if ((iw & 0xf800) == 0x0000) {
-				/*  xmem  */
-				if (!(iw & 0x400))
-					op << ".bu";
-			} else {
-				/*  ld  */
-				if ((iw & 0xf00) < 0xc00)
-					op << ".hu";
-				else
-					op << ".bu";
-			}
-			
-			if (iw & 0x100)
-				op << ".usr";
-			if (iw & 0x80)
-				op << ".wt";
-
-			result.push_back(op.str());
-
-			stringstream ss;
-			ss << "r" << d << ",r" << s1;
-			if (iw & 0x200)
-				ss << "[r" << s2 << "]";
-			else
-				ss << ",r" << s2;
-
-			result.push_back(ss.str());
-		} else switch (op3d) {
-		case 0x40:	/*  and  */
-		case 0x44:	/*  and.c  */
-		case 0x50:	/*  xor  */
-		case 0x54:	/*  xor.c  */
-		case 0x58:	/*  or  */
-		case 0x5c:	/*  or.c  */
-		case 0x60:	/*  addu  */
-		case 0x61:	/*  addu.co  */
-		case 0x62:	/*  addu.ci  */
-		case 0x63:	/*  addu.cio  */
-		case 0x64:	/*  subu  */
-		case 0x65:	/*  subu.co  */
-		case 0x66:	/*  subu.ci  */
-		case 0x67:	/*  subu.cio  */
-		case 0x68:	/*  divu  */
-		case 0x69:	/*  divu.d  */
-		case 0x6c:	/*  mul  */
-		case 0x6d:	/*  mulu.d  */
-		case 0x6e:	/*  muls  */
-		case 0x70:	/*  add  */
-		case 0x71:	/*  add.co  */
-		case 0x72:	/*  add.ci  */
-		case 0x73:	/*  add.cio  */
-		case 0x74:	/*  sub  */
-		case 0x75:	/*  sub.co  */
-		case 0x76:	/*  sub.ci  */
-		case 0x77:	/*  sub.cio  */
-		case 0x78:	/*  div  */
-		case 0x7c:	/*  cmp  */
-		case 0x80:	/*  clr  */
-		case 0x88:	/*  set  */
-		case 0x90:	/*  ext  */
-		case 0x98:	/*  extu  */
-		case 0xa0:	/*  mak  */
-		case 0xa8:	/*  rot  */
-			/*  Three-register opcodes:  */
-			{
-				result.push_back(opcode_names_3d[op3d]);
-
-				stringstream ss;
-				ss << "r" << d << ",r" << s1 << ",r" << s2;
-				result.push_back(ss.str());
-			}
-			break;
-		case 0xc0:	/*  jmp  */
-		case 0xc4:	/*  jmp.n  */
-		case 0xc8:	/*  jsr  */
-		case 0xcc:	/*  jsr.n  */
-			/*  One-register jump opcodes:  */
-			{
-				result.push_back(opcode_names_3d[op3d]);
-
-				stringstream ss;
-				ss << "(r" << s2 << ")";
-				result.push_back(ss.str());
-			}
-			break;
-		case 0xe8:	/*  ff1  */
-		case 0xec:	/*  ff0  */
-			/*  Two-register opcodes d,s2:  */
-			{
-				result.push_back(opcode_names_3d[op3d]);
-
-				stringstream ss;
-				ss << "r" << d << ",r" << s2;
-				result.push_back(ss.str());
-			}
-			break;
-		case 0xf8:	/*  tbnd  */
-			/*  Two-register opcodes s1,s2:  */
-			{
-				result.push_back(opcode_names_3d[op3d]);
-
-				stringstream ss;
-				ss << "r" << s1 << ",r" << s2;
-				result.push_back(ss.str());
-			}
-			break;
-		case 0xfc:
-			switch (iw & 0xff) {
-			case 0x00:
-				result.push_back("rte");
-				break;
-			case 0x01:
-			case 0x02:
-			case 0x03:
-				{
-					stringstream ss;
-					ss << "illop" << (iw & 0xff);
-					result.push_back(ss.str());
-				}
-				break;
-			case (M88K_PROM_INSTR & 0xff):
-				result.push_back("gxemul_prom_call");
-				break;
-			case (M88K_FAIL_EARLY_INSTR & 0xff):
-				result.push_back("gxemul_fail_early");
-				break;
-			case (M88K_FAIL_LATE_INSTR & 0xff):
-				result.push_back("gxemul_fail_late");
-				break;
-			default:{
-					stringstream ss;
-					ss << "unimpl_3d_0xfc_" << (iw & 0xff);
-					result.push_back(ss.str());
-				}
-			}
-			break;
-		default:{
-				stringstream ss;
-				ss << "unimpl_" << opcode_names_3d[op3d];
-				result.push_back(ss.str());
-			}
-		}
-		break;
-
-	case 0x3e:	/*  tbnd  */
-		{
-			result.push_back(opcode_names[op26]);
-
-			stringstream ss;
-			ss << "r" << s1;
-			ss.flags(std::ios::hex | std::ios::showbase);
-			ss << "," << imm16;
-			result.push_back(ss.str());
-		}
-		break;
-
-	default:
-		{
-			stringstream ss;
-			ss << "unimpl_" << opcode_names[op26];
-			result.push_back(ss.str());
-		}
-		break;
-	}
-
-	return instrSize;
-}
-
-
-string M88K_CPUComponent::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "description")
-		return "Motorola 88000 processor.";
-
-	return Component::GetAttribute(attributeName);
-}
-
-
-/*****************************************************************************/
-
-
-void M88K_CPUComponent::stcr(int cr, uint32_t value, bool is_rte)
-{
-	uint32_t old = m_cr[cr];
-
-	switch (cr) {
-
-	case M88K_CR_PSR:	/*  Processor Status Regoster  */
-		if ((!m_isBigEndian && !(value & M88K_PSR_BO)) ||
-		    (m_isBigEndian && (value & M88K_PSR_BO))) {
-			std::cerr << "TODO: attempt to change endianness by flipping"
-			    " the endianness bit in the PSR. How should this"
-			    " be handled? Aborting.\n";
-			std::cerr << "TODO: abort in a nicer way\n";
-			throw std::exception();
-		}
-
-		if (!is_rte && (old & M88K_PSR_MODE) && !(value & M88K_PSR_MODE)) {
-			UI* ui = GetUI();
-			if (ui != NULL) {
-				ui->ShowDebugMessage(this, "m88k stcr: WARNING! the PSR_MODE bit is being"
-				    " cleared; this should be done using the RTE "
-				    "instruction only, according to the M88100 "
-				    "manual! Continuing anyway.\n");
-			}
-		}
-
-		if (value & M88K_PSR_MXM) {
-			std::cerr << "m88k stcr: TODO: MXM support\n";
-			std::cerr << "TODO: abort in a nicer way\n";
-			throw std::exception();
-		}
-
-		if ((old & M88K_PSR_MODE) != (value & M88K_PSR_MODE)) {
-//			cpu->invalidate_translation_caches(
-//			    cpu, 0, INVALIDATE_ALL);
-			std::cerr << "m88k stcr: TODO: PSR mode switch.\n";
-			std::cerr << "TODO: abort in a nicer way\n";
-			throw std::exception();
-		}
-
-		m_cr[cr] = value;
-		break;
-
-	case M88K_CR_EPSR:
-		m_cr[cr] = value;
-		break;
-
-	case M88K_CR_SXIP:
-	case M88K_CR_SNIP:
-	case M88K_CR_SFIP:
-		m_cr[cr] = value;
-		break;
-
-	case M88K_CR_SSBR:	/*  Shadow ScoreBoard Register  */
-		if (value & 1) {
-			UI* ui = GetUI();
-			if (ui != NULL)
-				ui->ShowDebugMessage(this, "WARNING! bit 0 non-zero when writing to SSBR\n");
-		}
-
-		m_cr[cr] = value;
-		break;
-
-	case M88K_CR_VBR:
-		if (value & 0x00000fff) {
-			UI* ui = GetUI();
-			if (ui != NULL)
-				ui->ShowDebugMessage(this, "WARNING! bits 0..11 non-zero when writing to VBR\n");
-		}
-
-		m_cr[cr] = value;
-		break;
-
-	case M88K_CR_DMT0:
-	case M88K_CR_DMT1:
-	case M88K_CR_DMT2:
-		m_cr[cr] = value;
-		break;
-
-	case M88K_CR_SR0:	/*  Supervisor Storage Registers 0..3  */
-	case M88K_CR_SR1:
-	case M88K_CR_SR2:
-	case M88K_CR_SR3:
-		m_cr[cr] = value;
-		break;
-
-	default:std::cerr << "m88k stcr: UNIMPLEMENTED cr = " << cr << "\n";
-		std::cerr << "TODO: abort in a nicer way\n";
-		throw std::exception();
-	}
-}
-
-
-/*
- *  cmp_imm:  Compare S1 with immediate value.
- *  cmp:      Compare S1 with S2.
- *
- *  arg[0] = pointer to register d
- *  arg[1] = pointer to register s1
- *  arg[2] = pointer to register s2 or imm
- */
-void M88K_CPUComponent::m88k_cmp(struct DyntransIC *ic, uint32_t y)
-{
-	uint32_t x = REG32(ic->arg[1]);
-	uint32_t r;
-
-	if (x == y) {
-		r = M88K_CMP_HS | M88K_CMP_LS | M88K_CMP_GE
-		  | M88K_CMP_LE | M88K_CMP_EQ;
-	} else {
-		if (x > y)
-			r = M88K_CMP_NE | M88K_CMP_HS | M88K_CMP_HI;
-		else
-			r = M88K_CMP_NE | M88K_CMP_LO | M88K_CMP_LS;
-		if ((int32_t)x > (int32_t)y)
-			r |= M88K_CMP_GE | M88K_CMP_GT;
-		else
-			r |= M88K_CMP_LT | M88K_CMP_LE;
-	}
-
-	REG32(ic->arg[0]) = r;
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,cmp)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-	cpu->m88k_cmp(ic, REG32(ic->arg[2]));
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,cmp_imm)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-	cpu->m88k_cmp(ic, ic->arg[2].u32);
-}
-
-
-/*
- *  extu_imm:  Extract bits, unsigned, immediate W<O>.
- *  extu:      Extract bits, unsigned, W<O> taken from register s2.
- *  ext_imm:   Extract bits, signed, immediate W<O>.
- *  ext:       Extract bits, signed, W<O> taken from register s2.
- *
- *  arg[0] = pointer to register d
- *  arg[1] = pointer to register s1
- *  arg[2] = pointer to register s2 or 10 bits wwwwwooooo
- */
-void M88K_CPUComponent::m88k_extu(struct DyntransIC *ic, int w, int o)
-{
-	uint32_t x = REG32(ic->arg[1]) >> o;
-	if (w != 0) {
-		x <<= (32-w);
-		x >>= (32-w);
-	}
-
-	REG32(ic->arg[0]) = x;
-}
-void M88K_CPUComponent::m88k_ext(struct DyntransIC *ic, int w, int o)
-{
-	int32_t x = REG32(ic->arg[1]);
-	x >>= o;	/*  signed (arithmetic) shift  */
-	if (w != 0) {
-		x <<= (32-w);
-		x >>= (32-w);
-	}
-
-	REG32(ic->arg[0]) = x;
-}
-DYNTRANS_INSTR(M88K_CPUComponent,extu_imm)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-	cpu->m88k_extu(ic, ic->arg[2].u32 >> 5, ic->arg[2].u32 & 0x1f);
-}
-DYNTRANS_INSTR(M88K_CPUComponent,extu)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-	cpu->m88k_extu(ic, (REG32(ic->arg[2]) >> 5) & 0x1f, REG32(ic->arg[2]) & 0x1f);
-}
-DYNTRANS_INSTR(M88K_CPUComponent,ext_imm)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-	cpu->m88k_ext(ic, ic->arg[2].u32 >> 5, ic->arg[2].u32 & 0x1f);
-}
-DYNTRANS_INSTR(M88K_CPUComponent,ext)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-	cpu->m88k_ext(ic, (REG32(ic->arg[2]) >> 5) & 0x1f, REG32(ic->arg[2]) & 0x1f);
-}
-
-
-/*
- *  mak:      Make bit field, W<O> taken from register s2.
- *  mak_imm:  Make bit field, immediate W<O>.
- *
- *  arg[0] = pointer to register d
- *  arg[1] = pointer to register s1
- *  arg[2] = pointer to register s2 or immediate.
- */
-void M88K_CPUComponent::m88k_mak(struct DyntransIC *ic, int w, int o)
-{
-	uint32_t x = REG32(ic->arg[1]);
-	if (w != 0) {
-		x <<= (32-w);
-		x >>= (32-w);
-	}
-
-	REG32(ic->arg[0]) = x << o;
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,mak)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-	cpu->m88k_mak(ic, (REG32(ic->arg[2]) >> 5) & 0x1f, REG32(ic->arg[2]) & 0x1f);
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,mak_imm)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-	cpu->m88k_mak(ic, ic->arg[2].u32 >> 5, ic->arg[2].u32 & 0x1f);
-}
-
-
-/*
- *  divu_imm:  d = s1 / immediate
- *  mulu_imm:  d = s1 * immediate
- *
- *  arg[0] = pointer to register d
- *  arg[1] = pointer to register s1
- *  arg[2] = immediate.
- */
-DYNTRANS_INSTR(M88K_CPUComponent,divu_imm)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	// TODO: 88100 only, not 88110:
-	if (cpu->m_cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		DYNTRANS_SYNCH_PC;
-		cpu->m_fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		cpu->Exception(M88K_EXCEPTION_SFU1_PRECISE, 0);
-	} else if (ic->arg[2].u32 == 0) {
-		DYNTRANS_SYNCH_PC;
-		cpu->Exception(M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE, 0);
-	} else {
-		REG32(ic->arg[0]) = REG32(ic->arg[1]) / ic->arg[2].u32;
-	}
-}
-DYNTRANS_INSTR(M88K_CPUComponent,mulu_imm)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	// TODO: 88100 only, not 88110:
-	if (cpu->m_cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		DYNTRANS_SYNCH_PC;
-		cpu->m_fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		cpu->Exception(M88K_EXCEPTION_SFU1_PRECISE, 0);
-	} else {
-		REG32(ic->arg[0]) = REG32(ic->arg[1]) * ic->arg[2].u32;
-	}
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,bsr)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	cpu->m_pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->m_r[M88K_RETURN_REG] = cpu->m_pc + ic->arg[2].u32;
-
-	cpu->m_pc = (uint32_t) (cpu->m_pc + ic->arg[1].u32);
-	cpu->DyntransPCtoPointers();
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,bsr_samepage)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	cpu->m_r[M88K_RETURN_REG] = (cpu->m_pc & ~((M88K_IC_ENTRIES_PER_PAGE-1)
-	    << M88K_INSTR_ALIGNMENT_SHIFT)) + ic->arg[2].u32;
-	cpu->m_nextIC = (struct DyntransIC *) ic->arg[0].p;
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,bsr_functioncalltrace)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	cpu->m_pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->m_r[M88K_RETURN_REG] = cpu->m_pc + ic->arg[2].u32;
-
-	cpu->m_pc = (uint32_t) (cpu->m_pc + ic->arg[1].u32);
-
-	bool continueExecution = cpu->FunctionTraceCall();
-	cpu->DyntransPCtoPointers();
-
-	if (!continueExecution)
-		cpu->m_nextIC = &cpu->m_abortIC;
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,bsr_n)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	uint32_t startOfPage = cpu->m_pc & ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->m_r[M88K_RETURN_REG] = startOfPage + ic->arg[2].u32;
-
-	// Prepare for the branch.
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-	cpu->m_inDelaySlot = true;
-	cpu->m_delaySlotTarget = (uint32_t) (startOfPage + ic->arg[1].u32);
-
-	// Execute the next instruction:
-	ic[1].f(cpu, ic+1);
-	cpu->m_executedCycles ++;
-
-	// If there was no exception, then branch:
-	if (!cpu->m_exceptionOrAbortInDelaySlot) {
-		cpu->m_pc = (uint32_t) (startOfPage + ic->arg[1].u32);
-		cpu->DyntransPCtoPointers();
-
-		cpu->m_inDelaySlot = false;
-	}
-
-	// The next instruction is now either the target of the branch
-	// instruction, or the first instruction of an exception handler.
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,bsr_n_functioncalltrace)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	uint32_t startOfPage = cpu->m_pc & ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->m_r[M88K_RETURN_REG] = startOfPage + ic->arg[2].u32;
-
-	// Prepare for the branch.
-	cpu->m_inDelaySlot = true;
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-
-	// Execute the next instruction:
-	ic[1].f(cpu, ic+1);
-	cpu->m_executedCycles ++;
-
-	// If there was no exception, then branch:
-	if (!cpu->m_exceptionOrAbortInDelaySlot) {
-		cpu->m_pc = (uint32_t) (startOfPage + ic->arg[1].u32);
-
-		bool continueExecution = cpu->FunctionTraceCall();
-		cpu->DyntransPCtoPointers();
-
-		cpu->m_inDelaySlot = false;
-
-		if (!continueExecution)
-			cpu->m_nextIC = &cpu->m_abortIC;
-	}
-
-	// The next instruction is now either the target of the branch
-	// instruction, or the first instruction of an exception handler.
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-}
-
-
-// Note: This IC function is used both when function call trace is enabled
-// and disabled. (Ok, since it is only used when singlestepping.)
-DYNTRANS_INSTR(M88K_CPUComponent,bsr_n_functioncalltrace_singlestep)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	// Prepare for the delayed branch.
-	cpu->m_inDelaySlot = true;
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-
-	cpu->m_pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->m_r[M88K_RETURN_REG] = cpu->m_pc + ic->arg[2].u32;
-
-	uint32_t old_pc = cpu->m_pc;
-
-	cpu->m_pc = (uint32_t) (cpu->m_pc + ic->arg[1].u32);
-
-	if (cpu->m_showFunctionTraceCall)
-		cpu->FunctionTraceCall();
-
-	cpu->m_delaySlotTarget = cpu->m_pc;
-
-	// make m_nextIC (and pc!) point to the next instruction:
-	cpu->m_nextIC = ic + 1;
-	cpu->m_pc = old_pc;	// at least the same page... not necessarily more correct than that.
-}
-
-
-/*
- *  bcnd, bcnd.n:  Branch on condition
- *
- *  arg[0] = pointer to register s1
- *  arg[2] = offset from start of current page to branch to _OR_ pointer to new instr_call
- */
-template<bool n, int op, bool singlestep> void M88K_CPUComponent::instr_bcnd(CPUDyntransComponent* cpubase, DyntransIC* ic)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	bool cond;
-	if (op == 1)		cond = ((int32_t)REG32(ic->arg[0]) > 0);		// gt0
-	else if (op == 2)	cond = ((int32_t)REG32(ic->arg[0]) == 0);		// eq0
-	else if (op == 3)	cond = ((int32_t)REG32(ic->arg[0]) >= 0);		// ge0
-	else if (op == 7)	cond = ((uint32_t)REG32(ic->arg[0]) != 0x80000000UL);	// not_maxneg
-	else if (op == 8)	cond = ((uint32_t)REG32(ic->arg[0]) == 0x80000000UL);	// maxneg
-	else if (op == 12)	cond = ((int32_t)REG32(ic->arg[0]) < 0);		// lt0
-	else if (op == 13)	cond = ((int32_t)REG32(ic->arg[0]) != 0);		// ne0
-	else /* op == 14 */	cond = ((int32_t)REG32(ic->arg[0]) <= 0);		// le0
-
-	if (n) {
-		if (singlestep) {
-			DYNTRANS_SYNCH_PC;
-		
-			// Prepare for the branch.
-			cpu->m_inDelaySlot = true;
-			cpu->m_exceptionOrAbortInDelaySlot = false;
-
-			if (cond) {
-				cpu->m_delaySlotTarget = cpu->m_pc & ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT);
-				cpu->m_delaySlotTarget = (uint32_t) (cpu->m_delaySlotTarget + ic->arg[2].u32);
-			} else {
-				cpu->m_delaySlotTarget = cpu->m_pc + 8;
-			}
-		
-			cpu->m_nextIC = ic + 1;
-		} else {
-			// Prepare for the branch.
-			cpu->m_inDelaySlot = true;
-			cpu->m_exceptionOrAbortInDelaySlot = false;
-		
-			// Execute the next instruction:
-			ic[1].f(cpu, ic+1);
-			cpu->m_executedCycles ++;
-		
-			// If there was no exception, then branch:
-			if (!cpu->m_exceptionOrAbortInDelaySlot) {
-				if (cond) {
-					cpu->m_pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT);
-					cpu->m_pc = (uint32_t) (cpu->m_pc + ic->arg[2].u32);
-					cpu->DyntransPCtoPointers();
-				} else {
-					cpu->m_nextIC = ic + 2;
-				}
-		
-				cpu->m_inDelaySlot = false;
-			}
-		
-			// The next instruction is now either the target of the branch
-			// instruction, the instruction 2 steps after this one,
-			// or the first instruction of an exception handler.
-			cpu->m_exceptionOrAbortInDelaySlot = false;
-		}
-	} else {
-		// bcnd without the .n flag:
-		if (cond) {
-			cpu->m_pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT);
-			cpu->m_pc = (uint32_t) (cpu->m_pc + ic->arg[2].u32);
-			cpu->DyntransPCtoPointers();
-		} else {
-			// m_nextIC should already point to the next ic.
-		}
-	}
-}
-
-
-/*
- *  bb0, bb1:  Branch if a bit in a register is 0 or 1
- *  bb0.n, bb1.n:  Branch if a bit in a register is 0 or 1 with delay slot
- *
- *  arg[0] = pointer to register s1
- *  arg[1] = uint32_t bitmask to test
- *  arg[2] = offset from start of current page to branch to _OR_ pointer to new instr_call
- */
-template<bool one, bool samepage> void M88K_CPUComponent::instr_bb(CPUDyntransComponent* cpubase, DyntransIC* ic)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
- 	bool bit = REG32(ic->arg[0]) & ic->arg[1].u32;
-	if (bit == one) {
-		if (samepage) {
-			cpu->m_nextIC = (DyntransIC*) ic->arg[2].p;
-		} else {
-			cpu->m_pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT);
-			cpu->m_pc = (uint32_t) (cpu->m_pc + ic->arg[2].u32);
-			cpu->DyntransPCtoPointers();
-		}
-	}
-}
-
-
-template<bool one> void M88K_CPUComponent::instr_bb_n(CPUDyntransComponent* cpubase, DyntransIC* ic)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
- 	bool bit = REG32(ic->arg[0]) & ic->arg[1].u32;
-
-	// Prepare for the branch.
-	cpu->m_inDelaySlot = true;
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-
-	// Execute the next instruction:
-	ic[1].f(cpu, ic+1);
-	cpu->m_executedCycles ++;
-
-	// If there was no exception, then branch:
-	if (!cpu->m_exceptionOrAbortInDelaySlot) {
-		if (bit == one) {
-			cpu->m_pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT);
-			cpu->m_pc = (uint32_t) (cpu->m_pc + ic->arg[2].u32);
-			cpu->DyntransPCtoPointers();
-		} else {
-			cpu->m_nextIC = ic + 2;
-		}
-
-		cpu->m_inDelaySlot = false;
-	}
-
-	// The next instruction is now either the target of the branch
-	// instruction, the instruction 2 steps after this one,
-	// or the first instruction of an exception handler.
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-}
-
-
-template<bool one> void M88K_CPUComponent::instr_bb_n_singlestep(CPUDyntransComponent* cpubase, DyntransIC* ic)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
- 	bool bit = REG32(ic->arg[0]) & ic->arg[1].u32;
-
-	DYNTRANS_SYNCH_PC;
-
-	// Prepare for the branch.
-	cpu->m_inDelaySlot = true;
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-
-	if (bit == one) {
-		cpu->m_delaySlotTarget = cpu->m_pc & ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT);
-		cpu->m_delaySlotTarget = (uint32_t) (cpu->m_delaySlotTarget + ic->arg[2].u32);
-	} else {
-		cpu->m_delaySlotTarget = cpu->m_pc + 8;
-	}
-
-	cpu->m_nextIC = ic + 1;
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,jmp)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-	bool continueExecution = true;
-
-	if (cpu->m_showFunctionTraceCall && ic->arg[2].p == &cpu->m_r[M88K_RETURN_REG])
-		continueExecution = cpu->FunctionTraceReturn();
-
-	cpu->m_pc = REG32(ic->arg[2]);
-	cpu->DyntransPCtoPointers();
-
-	if (!continueExecution)
-		cpu->m_nextIC = &cpu->m_abortIC;
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,jmp_n)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	// Prepare for the branch.
-	cpu->m_inDelaySlot = true;
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-	uint32_t branchTarget = REG32(ic->arg[2]);
-
-	// Execute the next instruction:
-	ic[1].f(cpu, ic+1);
-	cpu->m_executedCycles ++;
-
-	// If there was no exception, then branch:
-	if (!cpu->m_exceptionOrAbortInDelaySlot) {
-		cpu->m_pc = branchTarget;
-		cpu->DyntransPCtoPointers();
-
-		cpu->m_inDelaySlot = false;
-	}
-
-	// The next instruction is now either the target of the branch
-	// instruction, the instruction 2 steps after this one,
-	// or the first instruction of an exception handler.
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,jmp_n_functioncalltrace)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	// Prepare for the branch.
-	cpu->m_inDelaySlot = true;
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-	uint32_t branchTarget = REG32(ic->arg[2]);
-
-	// Execute the next instruction:
-	ic[1].f(cpu, ic+1);
-	cpu->m_executedCycles ++;
-
-	// If there was no exception, then branch:
-	if (!cpu->m_exceptionOrAbortInDelaySlot) {
-		bool continueExecution = true;
-		if (cpu->m_showFunctionTraceCall && ic->arg[2].p == &cpu->m_r[M88K_RETURN_REG])
-			continueExecution = cpu->FunctionTraceReturn();
-
-		cpu->m_pc = branchTarget;
-		cpu->DyntransPCtoPointers();
-
-		cpu->m_inDelaySlot = false;
-
-		if (!continueExecution)
-			cpu->m_nextIC = &cpu->m_abortIC;
-	}
-
-	// The next instruction is now either the target of the branch
-	// instruction, the instruction 2 steps after this one,
-	// or the first instruction of an exception handler.
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-}
-
-
-// Note: This IC function is used both when function call trace is enabled
-// and disabled. (Ok, since it is only used when singlestepping.)
-DYNTRANS_INSTR(M88K_CPUComponent,jmp_n_functioncalltrace_singlestep)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	if (cpu->m_showFunctionTraceCall && ic->arg[2].p == &cpu->m_r[M88K_RETURN_REG])
-		cpu->FunctionTraceReturn();
-
-	// Prepare for the delayed branch.
-	cpu->m_inDelaySlot = true;
-	cpu->m_exceptionOrAbortInDelaySlot = false;
-
-	cpu->m_delaySlotTarget = REG32(ic->arg[2]);
-
-	// m_nextIC already points to the next instruction
-}
-
-
-/*
- *  ldcr:   Load value from a control register, store in register d.
- *
- *  arg[0] = pointer to register d
- *  arg[1] = 6-bit control register number
- */
-DYNTRANS_INSTR(M88K_CPUComponent,ldcr)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	if (cpu->m_cr[M88K_CR_PSR] & M88K_PSR_MODE) {
-		int cr = ic->arg[1].u32;
-		REG32(ic->arg[0]) = cpu->m_cr[cr];
-	} else {
-		DYNTRANS_SYNCH_PC;
-		cpu->Exception(M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
-	}
-}
-
-
-/*
- *  stcr:   Store value from register s1 into a control register.
- *
- *  arg[0] = pointer to register s1
- *  arg[1] = 6-bit control register number
- */
-DYNTRANS_INSTR(M88K_CPUComponent,stcr)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	DYNTRANS_SYNCH_PC;
-
-	if (!(cpu->m_cr[M88K_CR_PSR] & M88K_PSR_MODE)) {
-		cpu->Exception(M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
-		return;
-	}
-
-	cpu->stcr(ic->arg[1].u32, REG32(ic->arg[0]), false);
-
-	cpu->m_nextIC = ic + 1;
-}
-
-
-/*
- *  tb0, tb1:  Trap on bit Clear/Set
- *
- *  arg[0] = bitmask to check (e.g. 0x00020000 for bit 17)
- *  arg[1] = pointer to register s1
- *  arg[2] = 9-bit vector number
- */
-template<bool one> void M88K_CPUComponent::instr_tb(CPUDyntransComponent* cpubase, DyntransIC* ic)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	if (!(cpu->m_cr[M88K_CR_PSR] & M88K_PSR_MODE)
-	    && ic->arg[2].u32 < M88K_EXCEPTION_USER_TRAPS_START) {
-		DYNTRANS_SYNCH_PC;
-		cpu->Exception(M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
-		return;
-	}
-
-	bool bit = (REG32(ic->arg[1]) & ic->arg[0].u32) > 0;
-	if (bit == one) {
-		DYNTRANS_SYNCH_PC;
-		cpu->Exception(ic->arg[2].u32, 1);
-	}
-}
-
-
-/*
- *  lda:  d = s1 + s2 * scaleFactor
- *
- *  arg[0] = pointer to register d
- *  arg[1] = pointer to register s1
- *  arg[2] = pointer to register s2
- */
-template<int scaleFactor> void M88K_CPUComponent::instr_lda(CPUDyntransComponent* cpubase, DyntransIC* ic)
-{
-	REG32(ic->arg[0]) = REG32(ic->arg[1]) + scaleFactor * REG32(ic->arg[2]);
-}
-
-
-/*
- *  Loads and stores:
- *
- *  arg[0] = pointer to register d
- *  arg[1] = pointer to register s1
- *  arg[2] = pointer to register s2  or  uint16_t offset
- */
-template<bool store, typename T, bool doubleword, bool regofs, bool scaled, bool signedLoad> void M88K_CPUComponent::instr_loadstore(CPUDyntransComponent* cpubase, DyntransIC* ic)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	// TODO: fast lookups
-	// TODO: usr access
-
-	// TODO: place in M88K's "ongoing memory transaction" registers!
-
-	uint32_t addr = REG32(ic->arg[1]) +
-	    (scaled? (doubleword? sizeof(uint64_t) : sizeof(T)) : 1) *
-	    (regofs? REG32(ic->arg[2]) : ic->arg[2].u32);
-
-	if (sizeof(T) > 1 && (addr & (sizeof(T)-1))) {
-		DYNTRANS_SYNCH_PC;
-		cpu->Exception(M88K_EXCEPTION_MISALIGNED_ACCESS, 0);
-		return;
-	}
-
-	cpu->AddressSelect(addr);
-
-	if (store) {
-		T data = REG32(ic->arg[0]);
-		if (!cpu->WriteData(data, cpu->m_isBigEndian? BigEndian : LittleEndian)) {
-			// TODO: failed to access memory was probably an exception. Handle this!
-		}
-	} else {
-		T data;
-		if (!cpu->ReadData(data, cpu->m_isBigEndian? BigEndian : LittleEndian)) {
-			// TODO: failed to access memory was probably an exception. Handle this!
-		}
-
-		if (signedLoad) {
-			if (sizeof(T) == sizeof(uint16_t))
-				data = (int16_t)data;
-			if (sizeof(T) == sizeof(uint8_t))
-				data = (int8_t)data;
-		}
-
-		REG32(ic->arg[0]) = data;
-	}
-
-	// Special handling of second word in a double-word read or write:
-	if (doubleword) {
-		if (store) {
-			uint32_t data2 = (* (((uint32_t*)(ic->arg[0].p)) + 1) );
-			cpu->AddressSelect(addr + sizeof(uint32_t));
-			if (!cpu->WriteData(data2, cpu->m_isBigEndian? BigEndian : LittleEndian)) {
-				// TODO: failed to access memory was probably an exception. Handle this!
-			}
-		} else {
-			uint32_t data2;
-			cpu->AddressSelect(addr + sizeof(uint32_t));
-			if (!cpu->ReadData(data2, cpu->m_isBigEndian? BigEndian : LittleEndian)) {
-				// TODO: failed to access memory was probably an exception. Handle this!
-			}
-
-			(* (((uint32_t*)(ic->arg[0].p)) + 1) ) = data2;
-		}
-	}
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  For unit tests:
- *
- *  fail_early: Results in an abort before doing anything.
- *  fail_late: Results in an abort after increasing r1.
- */
-DYNTRANS_INSTR(M88K_CPUComponent,fail_early)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	// Point to this instruction...
-	DYNTRANS_SYNCH_PC;
-
-	// We didn't actually do anything in this instruction.
-	cpu->m_executedCycles --;
-
-	// ... and then abort.
-	cpu->m_nextIC = &cpu->m_abortIC;
-	if (cpu->m_inDelaySlot)
-		cpu->m_exceptionOrAbortInDelaySlot = true;
-}
-
-DYNTRANS_INSTR(M88K_CPUComponent,fail_late)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	// Do something...
-	cpu->m_r[1] ++;
-
-	// Point to next instruction...
-	DYNTRANS_SYNCH_PC;
-	cpu->m_pc += sizeof(uint32_t);
-
-	// ... and abort.
-	cpu->m_nextIC = &cpu->m_abortIC;
-	if (cpu->m_inDelaySlot)
-		cpu->m_exceptionOrAbortInDelaySlot = true;
-}
-
-
-/*****************************************************************************/
-
-
-void M88K_CPUComponent::Translate(uint32_t iw, struct DyntransIC* ic)
-{
-	bool singleInstructionLeft = (m_executedCycles == m_nrOfCyclesToExecute - 1);
-	UI* ui = GetUI();	// for debug messages
-
-	uint32_t op26   = (iw >> 26) & 0x3f;
-//	uint32_t op11   = (iw >> 11) & 0x1f;
-	uint32_t op10   = (iw >> 10) & 0x3f;
-	uint32_t d      = (iw >> 21) & 0x1f;
-	uint32_t s1     = (iw >> 16) & 0x1f;
-	uint32_t s2     =  iw        & 0x1f;
-//	uint32_t op3d   = (iw >>  8) & 0xff;
-	uint32_t imm16  = iw & 0xffff;
-//	uint32_t w5     = (iw >>  5) & 0x1f;
-	uint32_t cr6    = (iw >>  5) & 0x3f;
-	int32_t  d16    = ((int16_t) (iw & 0xffff)) * 4;
-	int32_t  d26    = ((int32_t)((iw & 0x03ffffff) << 6)) >> 4;
-
-	switch (op26) {
-
-	case 0x02:	/*  ld.hu  */
-	case 0x03:	/*  ld.bu  */
-	case 0x04:	/*  ld.d   */
-	case 0x05:	/*  ld     */
-	case 0x06:	/*  ld.h   */
-	case 0x07:	/*  ld.b   */
-	case 0x08:	/*  st.d   */
-	case 0x09:	/*  st     */
-	case 0x0a:	/*  st.h   */
-	case 0x0b:	/*  st.b   */
-		{
-			bool store = op26 >= 0x08;
-			int opsize = 0;
-
-			ic->arg[0].p = &m_r[d];
-			ic->arg[1].p = &m_r[s1];
-			ic->arg[2].u32 = imm16;
-
-			switch (op26) {
-			case 0x02: ic->f = instr_loadstore<false, uint16_t, false, false, false, false>; opsize = 1; break;
-			case 0x03: ic->f = instr_loadstore<false, uint8_t,  false, false, false, false>; opsize = 0; break;
-			case 0x04: ic->f = instr_loadstore<false, uint32_t, true,  false, false, false>; opsize = 3; break;
-			case 0x05: ic->f = instr_loadstore<false, uint32_t, false, false, false, false>; opsize = 2; break;
-			case 0x06: ic->f = instr_loadstore<false, uint16_t, false, false, false, true>;  opsize = 1; break;
-			case 0x07: ic->f = instr_loadstore<false, uint8_t,  false, false, false, true>;  opsize = 0; break;
-			case 0x08: ic->f = instr_loadstore<true,  uint32_t, true,  false, false, false>; opsize = 3; break;
-			case 0x09: ic->f = instr_loadstore<true,  uint32_t, false, false, false, false>; opsize = 2; break;
-			case 0x0a: ic->f = instr_loadstore<true,  uint16_t, false, false, false, false>; opsize = 1; break;
-			case 0x0b: ic->f = instr_loadstore<true,  uint8_t,  false, false, false, false>; opsize = 0; break;
-			}
-
-			if (opsize == 3 && d == 31) {
-				// m88k load/store of register pair r31/r0 is not
-				// yet implemented: TODO: figure out how to deal with this.
-				ic->f = NULL;
-				break;
-			}
-
-			// Loads into the zero register => load into scratch register.
-			// According to the MC88110 manual: special cache operation
-			// "(touch, allocate, or flush) may be performed". (TODO)
-			if (!store && d == M88K_ZERO_REG && ic->f != NULL)
-				ic->arg[0].p = &m_zero_scratch;
-		}
-		break;
-
-	case 0x10:	/*  and    immu32  */
-	case 0x11:	/*  and.u  immu32  */
-	case 0x12:	/*  mask   immu32  */
-	case 0x13:	/*  mask.u immu32  */
-	case 0x14:	/*  xor    immu32  */
-	case 0x15:	/*  xor.u  immu32  */
-	case 0x16:	/*  or     immu32  */
-	case 0x17:	/*  or.u   immu32  */
-	case 0x18:	/*  addu   immu32  */
-	case 0x19:	/*  subu   immu32  */
-	case 0x1a:	/*  divu   immu32  */
-	case 0x1b:	/*  mulu   immu32  */
-	case 0x1f:	/*  cmp    immu32  */
-		{
-			int shift = 0;
-			switch (op26) {
-			case 0x10: ic->f = instr_and_u32_u32_immu32; break; // Note (see below): and only ands upper or lower part!
-			case 0x11: ic->f = instr_and_u32_u32_immu32; shift = 16; break;
-			case 0x12: ic->f = instr_and_u32_u32_immu32; break; // Note: mask is implemented using and
-			case 0x13: ic->f = instr_and_u32_u32_immu32; shift = 16; break;
-			case 0x14: ic->f = instr_xor_u32_u32_immu32; break;
-			case 0x15: ic->f = instr_xor_u32_u32_immu32; shift = 16; break;
-			case 0x16: ic->f = instr_or_u32_u32_immu32; break;
-			case 0x17: ic->f = instr_or_u32_u32_immu32; shift = 16; break;
-			case 0x18: ic->f = instr_add_u32_u32_immu32; break;
-			case 0x19: ic->f = instr_sub_u32_u32_immu32; break;
-			case 0x1a: ic->f = instr_divu_imm; break;
-			case 0x1b: ic->f = instr_mulu_imm; break;
-	//		case 0x1c: ic->f = instr(add_imm); break;
-	//		case 0x1d: ic->f = instr(sub_imm); break;
-	//		case 0x1e: ic->f = instr(div_imm); break;
-			case 0x1f: ic->f = instr_cmp_imm; break;
-			}
-
-			ic->arg[0].p = &m_r[d];
-			ic->arg[1].p = &m_r[s1];
-			ic->arg[2].u32 = imm16 << shift;
-
-			// The 'and' instruction only ands bits in the upper or
-			// lower parts of the word; the 'mask' instruction works
-			// on the whole register.
-			if (op26 == 0x10)
-				ic->arg[2].u32 |= 0xffff0000;
-			if (op26 == 0x11)
-				ic->arg[2].u32 |= 0x0000ffff;
-
-			if (d == M88K_ZERO_REG)
-				ic->f = instr_nop;
-		}
-		break;
-
-	case 0x20:
-		if ((iw & 0x001ff81f) == 0x00004000) {
-			ic->f = instr_ldcr;
-			ic->arg[0].p = &m_r[d];
-			ic->arg[1].u32 = cr6;
-			if (d == M88K_ZERO_REG)
-				ic->arg[0].p = &m_zero_scratch;
-//		} else if ((iword & 0x001ff81f) == 0x00004800) {
-//			ic->f = instr(fldcr);
-//			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-//			ic->arg[1] = cr6;
-//			if (d == M88K_ZERO_REG)
-//				ic->arg[0] = (size_t)
-//				    &cpu->cd.m88k.zero_scratch;
-		} else if ((iw & 0x03e0f800) == 0x00008000) {
-			ic->f = instr_stcr;
-			ic->arg[0].p = &m_r[s1];
-			ic->arg[1].u32 = cr6;
-			if (s1 != s2) {
-				ic->f = NULL;
-				if (ui != NULL) {
-					stringstream ss;
-					ss.flags(std::ios::hex);
-					ss << "stcr with s1 != s2? TODO: how "
-					    "should this be handled? s1=0x"
-					    << s1 << ", s2=0x" << s2;
-					ui->ShowDebugMessage(this, ss.str());
-				}
-			}
-//		} else if ((iword & 0x03e0f800) == 0x00008800) {
-//			ic->f = instr(fstcr);
-//			ic->arg[0] = (size_t) &cpu->cd.m88k.r[s1];
-//			ic->arg[1] = cr6;
-//			if (s1 != s2)
-//				goto bad;
-//		} else if ((iword & 0x0000f800) == 0x0000c000) {
-//			ic->f = instr(xcr);
-//			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-//			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-//			ic->arg[2] = cr6;
-//			if (s1 != s2)
-//				goto bad;
-		} else if (ui != NULL) {
-			ui->ShowDebugMessage(this, "unimplemented variant of opcode 0x20");
-		}
-		break;
-
-
-	case 0x30:	/*  br     */
-//	case 0x31:	/*  br.n   */
-	case 0x32:	/*  bsr    */
-	case 0x33:	/*  bsr.n  */
-		{
-			void (*f_singleStepping)(CPUDyntransComponent*, struct DyntransIC*) = NULL;
-			void (*samepage_function)(CPUDyntransComponent*, struct DyntransIC*) = NULL;
-
-			switch (op26) {
-			case 0x30:
-				ic->f = NULL; // instr(br);
-				samepage_function = instr_branch_samepage;
-				break;
-	//		case 0x31:
-	//			ic->f = instr(br_n);
-	//			if (cpu->translation_readahead > 2)
-	//				cpu->translation_readahead = 2;
-	//			break;
-			case 0x32:
-				ic->f = instr_bsr;
-				samepage_function = instr_bsr_samepage;
-				break;
-			case 0x33:
-				ic->f = instr_bsr_n;
-				// TODO samepage_function = instr_bsr_samepage;
-				f_singleStepping = instr_bsr_n_functioncalltrace_singlestep;
-				break;
-			}
-
-			if (singleInstructionLeft && (op26 == 0x31 || op26 == 0x33)) {
-				ic->f = f_singleStepping;
-				samepage_function = NULL;
-			}
-
-			int offset = (m_pc & 0xffc) + d26;
-
-			/*  Prepare both samepage and offset style args.
-			    (Only one will be used in the actual instruction.)  */
-			ic->arg[0].p = ( m_firstIConPage + (offset >> M88K_INSTR_ALIGNMENT_SHIFT) );
-			ic->arg[1].u32 = offset;
-
-			/*  Return offset for bsr and bsr.n (stored in m_r[M88K_RETURN_REG]):  */
-			ic->arg[2].u32 = (m_pc & 0xffc) + ((op26 & 1)? 8 : 4);
-
-			if (offset >= 0 && offset <= 0xffc && samepage_function != NULL)
-				ic->f = samepage_function;
-
-			if (m_showFunctionTraceCall) {
-				if (op26 == 0x32)
-					ic->f = instr_bsr_functioncalltrace;
-				if (op26 == 0x33) {
-					if (singleInstructionLeft)
-						ic->f = instr_bsr_n_functioncalltrace_singlestep;
-					else
-						ic->f = instr_bsr_n_functioncalltrace;
-				}
-			}
-		}
-		break;
-
-	case 0x34:	/*  bb0     */
-	case 0x35:	/*  bb0.n   */
-	case 0x36:	/*  bb1     */
-	case 0x37:	/*  bb1.n   */
-		{
-			void (*samepage_function)(CPUDyntransComponent*, struct DyntransIC*) = NULL;
-			void (*singlestep_function)(CPUDyntransComponent*, struct DyntransIC*) = NULL;
-
-			switch (op26) {
-			case 0x34:
-				ic->f = instr_bb<false,false>;
-				samepage_function = instr_bb<false,true>;
-				break;
-			case 0x35:
-				ic->f = instr_bb_n<false>;
-				singlestep_function = instr_bb_n_singlestep<false>;
-				break;
-			case 0x36:
-				ic->f = instr_bb<true,false>;
-				samepage_function = instr_bb<true,true>;
-				break;
-			case 0x37:
-				ic->f = instr_bb_n<true>;
-				singlestep_function = instr_bb_n_singlestep<true>;
-				break;
-			}
-	
-			ic->arg[0].p = &m_r[s1];
-			ic->arg[1].u32 = (1 << d);
-	
-			int offset = (m_pc & 0xffc) + d16;
-			ic->arg[2].u32 = offset;
-
-			if (singleInstructionLeft && singlestep_function != NULL)
-				ic->f = singlestep_function;
-			else if (offset >= 0 && offset <= 0xffc && samepage_function != NULL) {
-				ic->f = samepage_function;
-				ic->arg[2].p = ( m_firstIConPage + (offset >> M88K_INSTR_ALIGNMENT_SHIFT) );
-			}
-		}
-		break;
-
-	case 0x3a:	/*  bcnd    */
-	case 0x3b:	/*  bcnd.n  */
-		{
-			void (*samepage_function)(CPUDyntransComponent*, struct DyntransIC*) = NULL;
-			void (*singlestep_f)(CPUDyntransComponent*, struct DyntransIC*) = NULL;
-
-			if (op26 & 1) {
-				switch (d) {
-				case  1: ic->f = instr_bcnd<true,1, false>; singlestep_f = instr_bcnd<true,1, true>; break;
-				case  2: ic->f = instr_bcnd<true,2, false>; singlestep_f = instr_bcnd<true,2, true>; break;
-				case  3: ic->f = instr_bcnd<true,3, false>; singlestep_f = instr_bcnd<true,3, true>; break;
-				case  7: ic->f = instr_bcnd<true,7, false>; singlestep_f = instr_bcnd<true,7, true>; break;
-				case  8: ic->f = instr_bcnd<true,8, false>; singlestep_f = instr_bcnd<true,8, true>; break;
-				case 12: ic->f = instr_bcnd<true,12,false>; singlestep_f = instr_bcnd<true,12,true>; break;
-				case 13: ic->f = instr_bcnd<true,13,false>; singlestep_f = instr_bcnd<true,13,true>; break;
-				case 14: ic->f = instr_bcnd<true,14,false>; singlestep_f = instr_bcnd<true,14,true>; break;
-				}
-			} else {
-				switch (d) {
-				case  1: ic->f = instr_bcnd<false,1, false>; break;
-				case  2: ic->f = instr_bcnd<false,2, false>; break;
-				case  3: ic->f = instr_bcnd<false,3, false>; break;
-				case  7: ic->f = instr_bcnd<false,7, false>; break;
-				case  8: ic->f = instr_bcnd<false,8, false>; break;
-				case 12: ic->f = instr_bcnd<false,12,false>; break;
-				case 13: ic->f = instr_bcnd<false,13,false>; break;
-				case 14: ic->f = instr_bcnd<false,14,false>; break;
-				}
-			}
-
-			// TODO: samepage optimization: probably easiest to do using
-			// another template bit...
-			// samepage_function = m88k_bcnd[64 + d + 32 * (op26 & 1)];
-
-			if (ic->f == NULL) {
-				if (ui != NULL) {
-					stringstream ss;
-					ss.flags(std::ios::hex);
-					ss << "unimplemented bcnd condition code d = " << d;
-					ui->ShowDebugMessage(this, ss.str());
-				}
-
-				break;
-			}
-
-			ic->arg[0].p = &m_r[s1];
-
-			int offset = (m_pc & 0xffc) + d16;
-			ic->arg[2].u32 = offset;
-
-			if (singleInstructionLeft && singlestep_f != NULL) {
-				ic->f = singlestep_f;
-			} else if (offset >= 0 && offset <= 0xffc && samepage_function != NULL) {
-				ic->f = samepage_function;
-				ic->arg[2].p = ( m_firstIConPage + (offset >> M88K_INSTR_ALIGNMENT_SHIFT) );
-			}
-		}
-		break;
-
-	case 0x3c:
-		switch (op10) {
-
-//		case 0x20:	/*  clr  */
-//		case 0x22:	/*  set  */
-		case 0x24:	/*  ext  */
-		case 0x26:	/*  extu  */
-		case 0x28:	/*  mak  */
-			ic->arg[0].p = &m_r[d];
-			ic->arg[1].p = &m_r[s1];
-			ic->arg[2].u32 = iw & 0x3ff;
-
-			switch (op10) {
-//			case 0x20: ic->f = instr(mask_imm);
-//				   {
-//					int w = ic->arg[2] >> 5;
-//					int o = ic->arg[2] & 0x1f;
-//					uint32_t x = w == 0? 0xffffffff
-//					    : ((uint32_t)1 << w) - 1;
-//					x <<= o;
-//					ic->arg[2] = ~x;
-//				   }
-//				   break;
-//			case 0x22: ic->f = instr(or_imm);
-//				   {
-//					int w = ic->arg[2] >> 5;
-//					int o = ic->arg[2] & 0x1f;
-//					uint32_t x = w == 0? 0xffffffff
-//					    : ((uint32_t)1 << w) - 1;
-//					x <<= o;
-//					ic->arg[2] = x;
-//				   }
-//				   break;
-			case 0x24: ic->f = instr_ext_imm; break;
-			case 0x26: ic->f = instr_extu_imm; break;
-			case 0x28: ic->f = instr_mak_imm; break;
-			}
-
-			if (d == M88K_ZERO_REG)
-				ic->f = instr_nop;
-			break;
-
-		case 0x34:	/*  tb0  */
-		case 0x36:	/*  tb1  */
-			ic->arg[0].u32 = 1 << d;	// d is called B5 in the manual
-			ic->arg[1].p = &m_r[s1];
-			ic->arg[2].u32 = iw & 0x1ff;
-			switch (op10) {
-			case 0x34: ic->f = instr_tb<false>; break;
-			case 0x36: ic->f = instr_tb<true>; break;
-			}
-			break;
-
-		default:
-			if (ui != NULL) {
-				stringstream ss;
-				ss.flags(std::ios::hex);
-				ss << "unimplemented opcode 0x" << op26 << ",0x" << op10;
-				ui->ShowDebugMessage(this, ss.str());
-			}
-		}
-		break;
-
-	case 0x3d:
-		if ((iw & 0xf000) <= 0x3fff ) {
-			// Load, Store, xmem, and lda:
-			int op = 0, opsize, user = 0, wt = 0;
-			int signedness = 1, scaled = 0;
-
-			switch (iw & 0xf000) {
-			case 0x2000: op = 1; /* st */  break;
-			case 0x3000: op = 2; /* lda */ break;
-			default:     if ((iw & 0xf800) >= 0x0800)
-					op = 0; /* ld */
-				     else
-					op = 3; /* xmem */
-			}
-
-			/*  for (most) ld, st, lda:  */
-			opsize = (iw >> 10) & 3;
-
-			/*  Turn opsize into x, where size = 1 << x:  */
-			opsize = 3 - opsize;
-
-			if (op == 3) {
-				/*  xmem:  */
-				opsize = -1;
-				switch ((iw >> 10) & 3) {
-				case 0: opsize = 0; break;
-				case 1: opsize = 2; break;
-				default:// Weird xmem opsize/type? TODO
-					break;
-				}
-				if (opsize < 0)
-					break;
-			} else {
-				if ((iw & 0xf800) == 0x800) {
-					signedness = 0;
-					if ((iw & 0xf00) < 0xc00)
-						opsize = 1;
-					else
-						opsize = 0;
-				} else {
-					if (opsize >= 2 || op == 1)
-						signedness = 0;
-				}
-			}
-
-			if (iw & 0x100)
-				user = 1;
-			if (iw & 0x80)
-				wt = 1;
-			if (iw & 0x200)
-				scaled = 1;
-
-			if (wt) {
-				// wt bit not yet implemented! TODO
-				ic->f = NULL;
-				break;
-			}
-
-			ic->arg[0].p = &m_r[d];
-			ic->arg[1].p = &m_r[s1];
-			ic->arg[2].p = &m_r[s2];
-
-			if (op == 0 || op == 1) {
-				/*  ld or st:  */
-
-				int n = opsize +
-					((op == 1)? 4 : 0) +
-					(signedness? 8 : 0) +
-					(m_isBigEndian? 16 : 0) +
-					(scaled? 32 : 0) +
-					(user? 64 : 0);
-
-				// <bool store, typename T, bool doubleword, bool regofs, bool scaled, bool signedLoad>
-				//       4    ,   0123    ,       3        ,     true   ,      32    ,      8           , user (TODO)
-				switch (n) {
-				// load = 0
-				case 0 + 0 + 0 +  0  +  0 +  0: ic->f = instr_loadstore<false, uint8_t,  false, true, false, false>; break;
-				case 0 + 0 + 0 +  0  + 32 +  0: ic->f = instr_loadstore<false, uint8_t,  false, true, true,  false>; break;
-				case 0 + 0 + 0 + 16  +  0 +  0: ic->f = instr_loadstore<false, uint8_t,  false, true, false, false>; break;
-				case 0 + 0 + 0 + 16  + 32 +  0: ic->f = instr_loadstore<false, uint8_t,  false, true, true,  false>; break;
-				case 1 + 0 + 0 +  0  +  0 +  0: ic->f = instr_loadstore<false, uint16_t, false, true, false, false>; break;
-				case 1 + 0 + 0 +  0  + 32 +  0: ic->f = instr_loadstore<false, uint16_t, false, true, true,  false>; break;
-				case 1 + 0 + 0 + 16  +  0 +  0: ic->f = instr_loadstore<false, uint16_t, false, true, false, false>; break;
-				case 1 + 0 + 0 + 16  + 32 +  0: ic->f = instr_loadstore<false, uint16_t, false, true, true,  false>; break;
-				case 2 + 0 + 0 +  0  +  0 +  0: ic->f = instr_loadstore<false, uint32_t, false, true, false, false>; break;
-				case 2 + 0 + 0 +  0  + 32 +  0: ic->f = instr_loadstore<false, uint32_t, false, true, true,  false>; break;
-				case 2 + 0 + 0 + 16  +  0 +  0: ic->f = instr_loadstore<false, uint32_t, false, true, false, false>; break;
-				case 2 + 0 + 0 + 16  + 32 +  0: ic->f = instr_loadstore<false, uint32_t, false, true, true,  false>; break;
-				case 3 + 0 + 0 +  0  +  0 +  0: ic->f = instr_loadstore<false, uint32_t, true,  true, false, false>; break;
-				case 3 + 0 + 0 +  0  + 32 +  0: ic->f = instr_loadstore<false, uint32_t, true,  true, true,  false>; break;
-				case 3 + 0 + 0 + 16  +  0 +  0: ic->f = instr_loadstore<false, uint32_t, true,  true, false, false>; break;
-				case 3 + 0 + 0 + 16  + 32 +  0: ic->f = instr_loadstore<false, uint32_t, true,  true, true,  false>; break;
-				// store = 4
-				case 0 + 4 + 0 +  0  +  0 +  0: ic->f = instr_loadstore<true, uint8_t,  false, true, false, false>; break;
-				case 0 + 4 + 0 +  0  + 32 +  0: ic->f = instr_loadstore<true, uint8_t,  false, true, true,  false>; break;
-				case 0 + 4 + 0 + 16  +  0 +  0: ic->f = instr_loadstore<true, uint8_t,  false, true, false, false>; break;
-				case 0 + 4 + 0 + 16  + 32 +  0: ic->f = instr_loadstore<true, uint8_t,  false, true, true,  false>; break;
-				case 1 + 4 + 0 +  0  +  0 +  0: ic->f = instr_loadstore<true, uint16_t, false, true, false, false>; break;
-				case 1 + 4 + 0 +  0  + 32 +  0: ic->f = instr_loadstore<true, uint16_t, false, true, true,  false>; break;
-				case 1 + 4 + 0 + 16  +  0 +  0: ic->f = instr_loadstore<true, uint16_t, false, true, false, false>; break;
-				case 1 + 4 + 0 + 16  + 32 +  0: ic->f = instr_loadstore<true, uint16_t, false, true, true,  false>; break;
-				case 2 + 4 + 0 +  0  +  0 +  0: ic->f = instr_loadstore<true, uint32_t, false, true, false, false>; break;
-				case 2 + 4 + 0 +  0  + 32 +  0: ic->f = instr_loadstore<true, uint32_t, false, true, true,  false>; break;
-				case 2 + 4 + 0 + 16  +  0 +  0: ic->f = instr_loadstore<true, uint32_t, false, true, false, false>; break;
-				case 2 + 4 + 0 + 16  + 32 +  0: ic->f = instr_loadstore<true, uint32_t, false, true, true,  false>; break;
-				case 3 + 4 + 0 +  0  +  0 +  0: ic->f = instr_loadstore<true, uint32_t, true,  true, false, false>; break;
-				case 3 + 4 + 0 +  0  + 32 +  0: ic->f = instr_loadstore<true, uint32_t, true,  true, true,  false>; break;
-				case 3 + 4 + 0 + 16  +  0 +  0: ic->f = instr_loadstore<true, uint32_t, true,  true, false, false>; break;
-				case 3 + 4 + 0 + 16  + 32 +  0: ic->f = instr_loadstore<true, uint32_t, true,  true, true,  false>; break;
-				default:
-					std::cerr << "TODO generalize! scaled="<<scaled << " user="<<
-						user<<" signedness="<<signedness << " opsize=" << opsize << "\n";
-				}
-
-				// Loads into the zero register are changed to load into
-				// the scratch register.
-				// According to the MC88110 manual: special cache operation
-				// "(touch, allocate, or flush) may be performed". (TODO)
-				if (op == 0 && d == M88K_ZERO_REG && ic->f != NULL)
-					ic->arg[0].p = &m_zero_scratch;
-
-				if (opsize == 3 && d == 31) {
-					// m88k load/store of register pair r31/r0 is not
-					// yet implemented: TODO: figure out how to deal with this.
-					ic->f = NULL;
-					break;
-				}
-			} else if (op == 2) {
-				/*  lda:  */
-				if (scaled) {
-					switch (opsize) {
-//					case 0: // TODO: 88110 vs 88100 etc. ic->f = instr(addu); break;
-					case 1: ic->f = instr_lda<2>; break;
-					case 2: ic->f = instr_lda<4>; break;
-					case 3: ic->f = instr_lda<8>; break;
-					}
-				} else {
-					// TODO: 88110 vs 88100 etc.
-					// ic->f = instr(addu);
-				}
-
-				// TODO: Perhaps 88110 loads into 0 are not nops, but cache ops? Look in docs.
-				if (d == M88K_ZERO_REG && ic->f != NULL)
-					ic->f = instr_nop;
-			} else {
-				/*  xmem:  */
-// TODO
-//				ic->f = instr(xmem_slow);
-//				ic->arg[0] = iw;
-//				if (d == M88K_ZERO_REG)
-//					ic->f = instr(nop);
-			}
-		} else switch ((iw >> 8) & 0xff) {
-//		case 0x40:	/*  and    */
-//		case 0x44:	/*  and.c  */
-		case 0x50:	/*  xor    */
-//		case 0x54:	/*  xor.c  */
-		case 0x58:	/*  or     */
-//		case 0x5c:	/*  or.c   */
-		case 0x60:	/*  addu   */
-//		case 0x61:	/*  addu.co  */
-//		case 0x62:	/*  addu.ci  */
-		case 0x64:	/*  subu   */
-//		case 0x65:	/*  subu.co  */
-//		case 0x66:	/*  subu.ci  */
-//		case 0x68:	/*  divu   */
-//		case 0x6c:	/*  mul    */
-//		case 0x70:	/*  add    */
-//		case 0x78:	/*  div    */
-		case 0x7c:	/*  cmp    */
-//		case 0x80:	/*  clr    */
-//		case 0x88:	/*  set    */
-		case 0x90:	/*  ext    */
-		case 0x98:	/*  extu   */
-		case 0xa0:	/*  mak    */
-//		case 0xa8:	/*  rot    */
-			ic->arg[0].p = &m_r[d];
-			ic->arg[1].p = &m_r[s1];
-			ic->arg[2].p = &m_r[s2];
-
-			switch ((iw >> 8) & 0xff) {
-//			case 0x40: ic->f = instr(and);   break;
-//			case 0x44: ic->f = instr(and_c); break;
-			case 0x50: ic->f = instr_xor_u32_u32_u32; break;
-//			case 0x54: ic->f = instr(xor_c); break;
-			case 0x58: ic->f = instr_or_u32_u32_u32; break;
-//			case 0x5c: ic->f = instr(or_c);  break;
-			case 0x60: ic->f = instr_add_u32_u32_u32; break;
-//			case 0x61: ic->f = instr(addu_co); break;
-//			case 0x62: ic->f = instr(addu_ci); break;
-			case 0x64: ic->f = instr_sub_u32_u32_u32; break;
-//			case 0x65: ic->f = instr(subu_co); break;
-//			case 0x66: ic->f = instr(subu_ci); break;
-//			case 0x68: ic->f = instr(divu);  break;
-//			case 0x6c: ic->f = instr(mul);   break;
-//			case 0x70: ic->f = instr(add);   break;
-//			case 0x78: ic->f = instr(div);   break;
-			case 0x7c: ic->f = instr_cmp; break;
-//			case 0x80: ic->f = instr(clr);   break;
-//			case 0x88: ic->f = instr(set);   break;
-			case 0x90: ic->f = instr_ext;   break;
-			case 0x98: ic->f = instr_extu;  break;
-			case 0xa0: ic->f = instr_mak; break;
-//			case 0xa8: ic->f = instr(rot);   break;
-			}
-
-			/*
-			 * Handle the case when the destination register is r0:
-			 *
-			 * If there is NO SIDE-EFFECT! (i.e. no carry out, no possibility
-			 * of exceptions, etc), then replace the instruction with a nop.
-			 * If there is a possible side-effect, we still have to run the
-			 * instruction, so replace the destination register with the
-			 * scratch register.
-			 */
-			if (d == M88K_ZERO_REG && ic->f != NULL) {
-				int opc = (iw >> 8) & 0xff;
-				if (opc != 0x61 /* addu.co */ && opc != 0x63 /* addu.cio */ &&
-				    opc != 0x65 /* subu.co */ && opc != 0x67 /* subu.cio */ &&
-				    opc != 0x71 /*  add.co */ && opc != 0x73 /*  add.cio */ &&
-				    opc != 0x75 /*  sub.co */ && opc != 0x77 /*  sub.cio */ &&
-				    opc != 0x68 /*  divu   */ && opc != 0x69 /* divu.d   */ &&
-				    opc != 0x6c /*  mul    */ && opc != 0x6d /* mulu.d   */ &&
-				    opc != 0x6e /*  muls   */ && opc != 0x78 /*  div     */)
-					ic->f = instr_nop;
-				else
-					ic->arg[0].p = &m_zero_scratch;
-			}
-
-			if (ic->f == NULL && ui != NULL) {
-				stringstream ss;
-				ss.flags(std::ios::hex);
-				ss << "unimplemented opcode 0x3d,0x" << ((iw >> 8) & 0xff);
-				ui->ShowDebugMessage(this, ss.str());
-			}
-
-			break;
-		case 0xc0:	/*  jmp    */
-		case 0xc4:	/*  jmp.n  */
-//		case 0xc8:	/*  jsr    */
-//		case 0xcc:	/*  jsr.n  */
-			{
-				void (*f_ss)(CPUDyntransComponent*, struct DyntransIC*) = NULL;
-
-				switch ((iw >> 8) & 0xff) {
-				case 0xc0: ic->f = instr_jmp; break;
-				case 0xc4: ic->f = instr_jmp_n; f_ss = instr_jmp_n_functioncalltrace_singlestep; break;
-	//			case 0xc8: ic->f = instr(jsr); break;
-	//			case 0xcc: ic->f = instr(jsr_n); break;
-				}
-
-				ic->arg[1].u32 = (m_pc & 0xffc) + 4;
-				ic->arg[2].p = &m_r[s2];
-
-				if (((iw >> 8) & 0x04) == 0x04)
-					ic->arg[1].u32 = (m_pc & 0xffc) + 8;
-
-				if (m_showFunctionTraceCall && s2 == M88K_RETURN_REG) {
-					if (ic->f == instr_jmp_n) {
-						ic->f = instr_jmp_n_functioncalltrace;
-						f_ss = instr_jmp_n_functioncalltrace_singlestep;
-					}
-				}
-
-	//			if (m_showFunctionTraceCall) {
-	//				if (ic->f == instr(jsr))
-	//					ic->f = instr(jsr_trace);
-	//					TODO f_ss
-	//				if (ic->f == instr(jsr_n))
-	//					ic->f = instr(jsr_n_trace);
-	//					TODO f_ss
-	//			}
-
-				if (singleInstructionLeft && f_ss != NULL)
-					ic->f = f_ss;
-			}
-			break;
-//		case 0xe8:	/*  ff1  */
-//		case 0xec:      /*  ff0  */
-			// TODO
-		case 0xfc:
-			switch (iw & 0xff) {
-//			case 0x00:	/*  rte  */
-//			case 0x01:	/*  illop1  */
-//			case 0x02:	/*  illop2  */
-//			case 0x03:	/*  illop3  */
-//			case (M88K_PROM_INSTR & 0xff):
-			case (M88K_FAIL_EARLY_INSTR & 0xff):
-				ic->f = instr_fail_early;
-				break;
-//			case (M88K_FAIL_LATE_INSTR & 0xff):
-//				break;
-			default:if (ui != NULL) {
-					stringstream ss;
-					ss.flags(std::ios::hex);
-					ss << "unimplemented opcode 0x3d,0xfc,0x" << (iw & 0xff);
-					ui->ShowDebugMessage(this, ss.str());
-				}
-			}
-			break;
-		default:
-			if (ui != NULL) {
-				stringstream ss;
-				ss.flags(std::ios::hex);
-				ss << "unimplemented opcode 0x3d,0x" << ((iw >> 8) & 0xff);
-				ui->ShowDebugMessage(this, ss.str());
-			}
-		}
-		break;
-
-	default:
-		if (ui != NULL) {
-			stringstream ss;
-			ss.flags(std::ios::hex);
-			ss << "unimplemented opcode 0x" << op26;
-			ui->ShowDebugMessage(this, ss.str());
-		}
-	}
-}
-
-
-DYNTRANS_INSTR(M88K_CPUComponent,ToBeTranslated)
-{
-	DYNTRANS_INSTR_HEAD(M88K_CPUComponent)
-
-	cpu->DyntransToBeTranslatedBegin(ic);
-
-	uint32_t iword;
-	if (cpu->DyntransReadInstruction(iword))
-		cpu->Translate(iword, ic);
-
-	if (cpu->m_inDelaySlot && ic->f == NULL)
-		ic->f = instr_abort;
-
-	cpu->DyntransToBeTranslatedDone(ic);
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_M88K_CPUComponent_Create()
-{
-	refcount_ptr<Component> cpu =
-	    ComponentFactory::CreateComponent("m88k_cpu");
-	UnitTest::Assert("component was not created?", !cpu.IsNULL());
-
-	const StateVariable * p = cpu->GetVariable("pc");
-	UnitTest::Assert("cpu has no pc state variable?", p != NULL);
-	UnitTest::Assert("initial pc", p->ToString(), "0");
-
-	const StateVariable * r31 = cpu->GetVariable("r31");
-	UnitTest::Assert("cpu has no r31 state variable?", r31 != NULL);
-	UnitTest::Assert("initial r31", r31->ToString(), "0");
-}
-
-static void Test_M88K_CPUComponent_Create_with_r31()
-{
-	refcount_ptr<Component> cpu =
-	    ComponentFactory::CreateComponent("m88k_cpu(r31=0x12345678)");
-	UnitTest::Assert("component was not created?", !cpu.IsNULL());
-
-	const StateVariable * p = cpu->GetVariable("pc");
-	UnitTest::Assert("cpu has no pc state variable?", p != NULL);
-	UnitTest::Assert("initial pc", p->ToString(), "0");
-
-	const StateVariable * r31 = cpu->GetVariable("r31");
-	UnitTest::Assert("cpu has no r31 state variable?", r31 != NULL);
-	UnitTest::Assert("initial r31", r31->ToString(), "0x12345678");
-
-	cpu->SetVariableValue("r31", "0xf00");
-
-	const StateVariable * r31_updated = cpu->GetVariable("r31");
-	UnitTest::Assert("could not update r31?", r31_updated->ToString(), "0xf00");
-
-	cpu->Reset();
-
-	const StateVariable * r31_after_reset = cpu->GetVariable("r31");
-	UnitTest::Assert("r31 after reset should have been reset", r31_after_reset->ToString(), "0x12345678");
-}
-
-static void Test_M88K_CPUComponent_IsCPU()
-{
-	refcount_ptr<Component> m88k_cpu =
-	    ComponentFactory::CreateComponent("m88k_cpu");
-
-	CPUComponent* cpu = m88k_cpu->AsCPUComponent();
-	UnitTest::Assert("m88k_cpu is not a CPUComponent?", cpu != NULL);
-}
-
-static void Test_M88K_CPUComponent_DefaultModel()
-{
-	refcount_ptr<Component> cpu =
-	    ComponentFactory::CreateComponent("m88k_cpu");
-
-	// Suitable default models would be 88100 and 88110 (the only two
-	// implementations there were of the 88K architecture). However,
-	// right now (2009-07-27), 88110 emulation isn't implemented yet.
-	UnitTest::Assert("wrong default model",
-	    cpu->GetVariable("model")->ToString(), "88100");
-}
-
-static void Test_M88K_CPUComponent_Disassembly_Basic()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add testm88k");
-
-	refcount_ptr<Component> m88k_cpu = gxemul.GetRootComponent()->LookupPath("root.machine0.mainbus0.cpu0");
-	CPUComponent* cpu = m88k_cpu->AsCPUComponent();
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-
-	vector<string> result;
-	size_t len;
-
-	// This assumes that the default endianness is BigEndian...
-	bus->AddressSelect(512);
-	uint32_t data32 = 0x63df0010;
-	bus->WriteData(data32, BigEndian);
-	
-	len = cpu->DisassembleInstruction(512, result);
-
-	UnitTest::Assert("disassembled instruction was wrong length?", len, 4);
-	UnitTest::Assert("disassembly result incomplete?", result.size(), 3);
-	UnitTest::Assert("disassembly result[0]", result[0], "63df0010");
-	UnitTest::Assert("disassembly result[1]", result[1], "addu");
-	UnitTest::Assert("disassembly result[2]", result[2], "r30,r31,0x10");
-}
-
-static void Test_M88K_CPUComponent_Execute_Basic()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add testm88k");
-
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.machine0.mainbus0.cpu0");
-	UnitTest::Assert("huh? no cpu?", !cpu.IsNULL());
-
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-	UnitTest::Assert("cpu should be addressable", bus != NULL);
-
-	// Place a hardcoded instruction in memory, and try to execute it.
-	// addu r30, r31, 0x10
-	uint32_t data32 = 0x63df0010;
-	bus->AddressSelect(48);
-	bus->WriteData(data32, BigEndian);
-
-	bus->AddressSelect(52);
-	bus->WriteData(data32, BigEndian);
-
-	cpu->SetVariableValue("pc", "48");
-	cpu->SetVariableValue("r30", "1234");
-	cpu->SetVariableValue("r31", "5678");
-
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("pc should have increased", cpu->GetVariable("pc")->ToInteger(), 52);
-	UnitTest::Assert("r30 should have been modified", cpu->GetVariable("r30")->ToInteger(), 5678 + 0x10);
-	UnitTest::Assert("r31 should not have been modified", cpu->GetVariable("r31")->ToInteger(), 5678);
-
-	cpu->SetVariableValue("r31", "1111");
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("pc should have increased again", cpu->GetVariable("pc")->ToInteger(), 56);
-	UnitTest::Assert("r30 should have been modified again", cpu->GetVariable("r30")->ToInteger(), 1111 + 0x10);
-}
-
-static void Test_M88K_CPUComponent_Execute_DelayBranchWithValidInstruction()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add testm88k");
-
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.machine0.mainbus0.cpu0");
-	UnitTest::Assert("huh? no cpu?", !cpu.IsNULL());
-
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-	UnitTest::Assert("cpu should be addressable", bus != NULL);
-
-	uint32_t data32 = 0xcc000010;	// bsr.n 0x1000 + 10*4, i.e. 0x1040
-	bus->AddressSelect(0x1000ULL);
-	bus->WriteData(data32, BigEndian);
-
-	data32 = 0x63df0010; // Something valid, addu r30, r31, 0x10
-	bus->AddressSelect(0x1004ULL);
-	bus->WriteData(data32, BigEndian);
-
-	cpu->SetVariableValue("pc", "0x1000");
-	UnitTest::Assert("setting pc failed?", cpu->GetVariable("pc")->ToInteger(), 0x1000);
-	UnitTest::Assert("r30 before execute", cpu->GetVariable("r30")->ToInteger(), 0);
-	UnitTest::Assert("r31 before execute", cpu->GetVariable("r31")->ToInteger(), 0xff0);
-
-	// This tests that execute 2 steps will execute both the delay branch
-	// and the delay slot instruction.
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(2);
-
-	UnitTest::Assert("pc should have changed", cpu->GetVariable("pc")->ToInteger(), 0x1040);
-	UnitTest::Assert("delay slot after execute", cpu->GetVariable("inDelaySlot")->ToString(), "false");
-	UnitTest::Assert("r30 after execute", cpu->GetVariable("r30")->ToInteger(), 0x1000);
-	UnitTest::Assert("r31 after execute", cpu->GetVariable("r31")->ToInteger(), 0xff0);
-}
-
-static void Test_M88K_CPUComponent_Execute_DelayBranchWithValidInstruction_SingleStepping()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add testm88k");
-
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.machine0.mainbus0.cpu0");
-	UnitTest::Assert("huh? no cpu?", !cpu.IsNULL());
-
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-	UnitTest::Assert("cpu should be addressable", bus != NULL);
-
-	uint32_t data32 = 0xcc000010;	// bsr.n 0x1000 + 10*4, i.e. 0x1040
-	bus->AddressSelect(0x1000ULL);
-	bus->WriteData(data32, BigEndian);
-
-	data32 = 0x63df0010; // Something valid, addu r30, r31, 0x10
-	bus->AddressSelect(0x1004ULL);
-	bus->WriteData(data32, BigEndian);
-
-	cpu->SetVariableValue("pc", "0x1000");
-	UnitTest::Assert("setting pc failed?", cpu->GetVariable("pc")->ToInteger(), 0x1000);
-	UnitTest::Assert("r30 before execute", cpu->GetVariable("r30")->ToInteger(), 0);
-	UnitTest::Assert("r31 before execute", cpu->GetVariable("r31")->ToInteger(), 0xff0);
-
-	// This tests that execute 2 steps (using single-stepping) will execute both
-	// the delay branch and the delay slot instruction.
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute(1);
-
-	// Should now be in the delay slot.
-	UnitTest::Assert("pc should have changed 1", cpu->GetVariable("pc")->ToInteger(), 0x1004);
-	UnitTest::Assert("delay slot after execute 1", cpu->GetVariable("inDelaySlot")->ToString(), "true");
-	UnitTest::Assert("r30 after execute 1", cpu->GetVariable("r30")->ToInteger(), 0);
-	UnitTest::Assert("r31 after execute 1", cpu->GetVariable("r31")->ToInteger(), 0xff0);
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("delay slot after execute 2", cpu->GetVariable("inDelaySlot")->ToString(), "false");
-	UnitTest::Assert("pc should have changed 2", cpu->GetVariable("pc")->ToInteger(), 0x1040);
-	UnitTest::Assert("r30 after execute 2", cpu->GetVariable("r30")->ToInteger(), 0x1000);
-	UnitTest::Assert("r31 after execute 2", cpu->GetVariable("r31")->ToInteger(), 0xff0);
-}
-
-static void Test_M88K_CPUComponent_Execute_DelayBranchWithValidInstruction_RunTwoTimes()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add testm88k");
-
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.machine0.mainbus0.cpu0");
-	UnitTest::Assert("huh? no cpu?", !cpu.IsNULL());
-
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-	UnitTest::Assert("cpu should be addressable", bus != NULL);
-
-	uint32_t data32 = 0xcc000010;	// bsr.n 0x1000 + 10*4, i.e. 0x1040
-	bus->AddressSelect(0x1000ULL);
-	bus->WriteData(data32, BigEndian);
-
-	data32 = 0x63df0010; // Something valid, addu r30, r31, 0x10
-	bus->AddressSelect(0x1004ULL);
-	bus->WriteData(data32, BigEndian);
-
-	cpu->SetVariableValue("pc", "0x1000");
-	UnitTest::Assert("setting pc failed?", cpu->GetVariable("pc")->ToInteger(), 0x1000);
-	UnitTest::Assert("r30 before execute", cpu->GetVariable("r30")->ToInteger(), 0);
-	UnitTest::Assert("r31 before execute", cpu->GetVariable("r31")->ToInteger(), 0xff0);
-
-	// This tests that execute 2 steps (using single-stepping) will execute both
-	// the delay branch and the delay slot instruction.
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1);
-
-	// Should now be in the delay slot.
-	UnitTest::Assert("pc should have changed 1", cpu->GetVariable("pc")->ToInteger(), 0x1004);
-	UnitTest::Assert("delay slot after execute 1", cpu->GetVariable("inDelaySlot")->ToString(), "true");
-	UnitTest::Assert("r30 after execute 1", cpu->GetVariable("r30")->ToInteger(), 0);
-	UnitTest::Assert("r31 after execute 1", cpu->GetVariable("r31")->ToInteger(), 0xff0);
-
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("delay slot after execute 2", cpu->GetVariable("inDelaySlot")->ToString(), "false");
-	UnitTest::Assert("pc should have changed 2", cpu->GetVariable("pc")->ToInteger(), 0x1040);
-	UnitTest::Assert("r30 after execute 2", cpu->GetVariable("r30")->ToInteger(), 0x1000);
-	UnitTest::Assert("r31 after execute 2", cpu->GetVariable("r31")->ToInteger(), 0xff0);
-}
-
-static void Test_M88K_CPUComponent_Execute_DelayBranchWithFault()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add testm88k");
-
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.machine0.mainbus0.cpu0");
-	UnitTest::Assert("huh? no cpu?", !cpu.IsNULL());
-
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-	UnitTest::Assert("cpu should be addressable", bus != NULL);
-
-	uint32_t data32 = 0xcc000010;	// bsr.n 0x1000 + 10*4, i.e. 0x1040
-	bus->AddressSelect(0x1000ULL);
-	bus->WriteData(data32, BigEndian);
-
-	data32 = 0xffffffff; // Something invalid
-	bus->AddressSelect(0x1004ULL);
-	bus->WriteData(data32, BigEndian);
-
-	cpu->SetVariableValue("pc", "0x1000");
-	UnitTest::Assert("setting pc failed?", cpu->GetVariable("pc")->ToInteger(), 0x1000);
-	UnitTest::Assert("r30 before execute", cpu->GetVariable("r30")->ToInteger(), 0);
-	UnitTest::Assert("r31 before execute", cpu->GetVariable("r31")->ToInteger(), 0xff0);
-
-	// This tests that execute 100 steps will only execute 1, if the instruction
-	// in the delay slot fails.
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(100);
-
-	UnitTest::Assert("pc should have increased one step", cpu->GetVariable("pc")->ToInteger(), 0x1004ULL);
-	UnitTest::Assert("should be in delay slot after execution", cpu->GetVariable("inDelaySlot")->ToString(), "true");
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("pc should not have increased", cpu->GetVariable("pc")->ToInteger(), 0x1004ULL);
-	UnitTest::Assert("should still be in delay slot", cpu->GetVariable("inDelaySlot")->ToString(), "true");
-}
-
-static void Test_M88K_CPUComponent_Execute_EarlyAbortDuringRuntime_Singlestep()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add testm88k");
-
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.machine0.mainbus0.cpu0");
-	UnitTest::Assert("huh? no cpu?", !cpu.IsNULL());
-
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-	UnitTest::Assert("cpu should be addressable", bus != NULL);
-
-	uint32_t data32 = 0xcc000010;	// bsr.n 0x1000 + 10*4, i.e. 0x1040
-	bus->AddressSelect(0x1000ULL);
-	bus->WriteData(data32, BigEndian);
-
-	data32 = 0xf400fc93;	// Something which is valid during interpretation,
-				// but invalid during runtime (i.e. aborts).
-	bus->AddressSelect(0x1004ULL);
-	bus->WriteData(data32, BigEndian);
-
-	cpu->SetVariableValue("pc", "0x1000");
-	UnitTest::Assert("setting pc failed?", cpu->GetVariable("pc")->ToInteger(), 0x1000);
-
-	// This tests that execute 100 steps will only execute 1, if the
-	// instruction in the delay slot aborts early.
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute(100);
-
-	UnitTest::Assert("1 step should have executed", cpu->GetVariable("step")->ToInteger(), 1);
-	UnitTest::Assert("pc should have increased one step", cpu->GetVariable("pc")->ToInteger(), 0x1004ULL);
-	UnitTest::Assert("should be in delay slot after execution", cpu->GetVariable("inDelaySlot")->ToString(), "true");
-	UnitTest::Assert("delay target should have been updated", cpu->GetVariable("delaySlotTarget")->ToInteger(), 0x1040);
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("no more steps should have executed", cpu->GetVariable("step")->ToInteger(), 1);
-	UnitTest::Assert("pc should not have increased", cpu->GetVariable("pc")->ToInteger(), 0x1004ULL);
-	UnitTest::Assert("should still be in delay slot", cpu->GetVariable("inDelaySlot")->ToString(), "true");
-	UnitTest::Assert("delay target should not have been updated", cpu->GetVariable("delaySlotTarget")->ToInteger(), 0x1040);
-}
-
-static void Test_M88K_CPUComponent_Execute_EarlyAbortDuringRuntime_Running()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add testm88k");
-
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.machine0.mainbus0.cpu0");
-	UnitTest::Assert("huh? no cpu?", !cpu.IsNULL());
-
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-	UnitTest::Assert("cpu should be addressable", bus != NULL);
-
-	uint32_t data32 = 0xcc000010;	// bsr.n 0x1000 + 10*4, i.e. 0x1040
-	bus->AddressSelect(0x1000ULL);
-	bus->WriteData(data32, BigEndian);
-
-	data32 = 0xf400fc93;	// Something which is valid during interpretation,
-				// but invalid during runtime (i.e. aborts).
-	bus->AddressSelect(0x1004ULL);
-	bus->WriteData(data32, BigEndian);
-
-	cpu->SetVariableValue("pc", "0x1000");
-	UnitTest::Assert("setting pc failed?", cpu->GetVariable("pc")->ToInteger(), 0x1000);
-
-	// This tests that execute 100 steps will only execute 1, if the
-	// instruction in the delay slot aborts early.
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(100);
-
-	UnitTest::Assert("1 step should have executed", cpu->GetVariable("step")->ToInteger(), 1);
-	UnitTest::Assert("pc should have increased one step", cpu->GetVariable("pc")->ToInteger(), 0x1004ULL);
-	UnitTest::Assert("should be in delay slot after execution", cpu->GetVariable("inDelaySlot")->ToString(), "true");
-	UnitTest::Assert("delay target should have been updated", cpu->GetVariable("delaySlotTarget")->ToInteger(), 0x1040);
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("no more steps should have executed", cpu->GetVariable("step")->ToInteger(), 1);
-	UnitTest::Assert("pc should not have increased", cpu->GetVariable("pc")->ToInteger(), 0x1004ULL);
-	UnitTest::Assert("should still be in delay slot", cpu->GetVariable("inDelaySlot")->ToString(), "true");
-	UnitTest::Assert("delay target should not have been updated", cpu->GetVariable("delaySlotTarget")->ToInteger(), 0x1040);
-}
-
-UNITTESTS(M88K_CPUComponent)
-{
-	UNITTEST(Test_M88K_CPUComponent_Create);
-	UNITTEST(Test_M88K_CPUComponent_Create_with_r31);
-	UNITTEST(Test_M88K_CPUComponent_IsCPU);
-	UNITTEST(Test_M88K_CPUComponent_DefaultModel);
-
-	// Disassembly:
-	UNITTEST(Test_M88K_CPUComponent_Disassembly_Basic);
-
-	// Dyntrans execution:
-	UNITTEST(Test_M88K_CPUComponent_Execute_Basic);
-	UNITTEST(Test_M88K_CPUComponent_Execute_DelayBranchWithValidInstruction);
-	UNITTEST(Test_M88K_CPUComponent_Execute_DelayBranchWithValidInstruction_SingleStepping);
-	UNITTEST(Test_M88K_CPUComponent_Execute_DelayBranchWithValidInstruction_RunTwoTimes);
-	UNITTEST(Test_M88K_CPUComponent_Execute_DelayBranchWithFault);
-	UNITTEST(Test_M88K_CPUComponent_Execute_EarlyAbortDuringRuntime_Singlestep);
-	UNITTEST(Test_M88K_CPUComponent_Execute_EarlyAbortDuringRuntime_Running);
-//	UNITTEST(Test_M88K_CPUComponent_Execute_LateAbortDuringRuntime);
-}
-
-#endif
-
diff -Nru gxemul-0.6.2/src/components/cpu/Makefile.skel gxemul-0.7.0+dfsg/src/components/cpu/Makefile.skel
--- gxemul-0.6.2/src/components/cpu/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/cpu/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,22 +0,0 @@
-#
-#  Makefile for GXemul src/components/cpu
-#
-
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(CPEDANTIC) $(INCLUDE2)
-LIBS=$(OTHERLIBS)
-
-OBJS=CPUComponent.o CPUDyntransComponent.o \
-	I960_CPUComponent.o \
-	M88K_CPUComponent.o \
-	RISCV_CPUComponent.o
-
-all: $(OBJS)
-
-$(OBJS): Makefile
-
-clean:
-	rm -f $(OBJS)
-
-clean_all: clean
-	rm -f Makefile
-
diff -Nru gxemul-0.6.2/src/components/cpu/RISCV_CPUComponent.cc gxemul-0.7.0+dfsg/src/components/cpu/RISCV_CPUComponent.cc
--- gxemul-0.6.2/src/components/cpu/RISCV_CPUComponent.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/cpu/RISCV_CPUComponent.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,580 +0,0 @@
-/*
- *  Copyright (C) 2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <stdio.h>
-#include <string.h>
-#include <iomanip>
-
-#include "ComponentFactory.h"
-#include "GXemul.h"
-#include "components/RISCV_CPUComponent.h"
-
-
-RISCV_CPUComponent::RISCV_CPUComponent()
-	: CPUDyntransComponent("riscv_cpu", "RISCV")
-{
-	m_frequency = 25e6;
-	m_isBigEndian = false;
-
-	m_model = "RV64G";
-	m_extensions = RISCV_EXTENSION_I;
-
-	ResetState();
-
-	AddVariable("model", &m_model);
-
-	for (size_t i = 0; i < N_RISCV_XREGS; i++) {
-		AddVariable(RISCV_regnames[i], &m_x[i]);
-	}
-}
-
-
-refcount_ptr<Component> RISCV_CPUComponent::Create(const ComponentCreateArgs& args)
-{
-	// Defaults:
-	ComponentCreationSettings settings;
-	settings["model"] = "RV64G";
-
-	if (!ComponentFactory::GetCreationArgOverrides(settings, args))
-		return NULL;
-
-	refcount_ptr<Component> cpu = new RISCV_CPUComponent();
-	if (!cpu->SetVariableValue("model", "\"" + settings["model"] + "\""))
-		return NULL;
-
-	return cpu;
-}
-
-
-void RISCV_CPUComponent::ResetState()
-{
-	m_pageSize = 4096;
-
-	for (size_t i=0; i<N_RISCV_XREGS; i++)
-		m_x[i] = 0;
-
-	m_pc = 0;
-
-	CPUDyntransComponent::ResetState();
-}
-
-
-bool RISCV_CPUComponent::PreRunCheckForComponent(GXemul* gxemul)
-{
-	if (m_pc & 0x1) {
-		gxemul->GetUI()->ShowDebugMessage(this, "the pc register"
-		    " can not have bit 0 set!\n");
-		return false;
-	}
-
-	return CPUDyntransComponent::PreRunCheckForComponent(gxemul);
-}
-
-
-bool RISCV_CPUComponent::CheckVariableWrite(StateVariable& var, const string& oldValue)
-{
-	// UI* ui = GetUI();
-
-	return CPUDyntransComponent::CheckVariableWrite(var, oldValue);
-}
-
-
-void RISCV_CPUComponent::ShowRegisters(GXemul* gxemul, const vector<string>& arguments) const
-{
-	stringstream ss;
-
-	ss.flags(std::ios::hex);
-	ss << "  pc = 0x" << std::setfill('0') << std::setw(16) << (uint32_t)m_pc;
-
-	string symbol = GetSymbolRegistry().LookupAddress(m_pc, true);
-	if (symbol != "")
-		ss << " <" << symbol << ">";
-	ss << "\n";
-
-	for (size_t i = 0; i < N_RISCV_XREGS; i++) {
-		ss << std::setfill(' ') << std::setw(4) << RISCV_regnames[i]
-			<< " = 0x" << std::setfill('0') << std::setw(16) << m_x[i];
-		if ((i&3) == 3)
-			ss << "\n";
-		else
-			ss << " ";
-	}
-
-	gxemul->GetUI()->ShowDebugMessage(ss.str());
-}
-
-
-int RISCV_CPUComponent::FunctionTraceArgumentCount()
-{
-	return 8;
-}
-
-
-int64_t RISCV_CPUComponent::FunctionTraceArgument(int n)
-{
-	return m_x[10 + n];
-}
-
-
-bool RISCV_CPUComponent::FunctionTraceReturnImpl(int64_t& retval)
-{
-	retval = m_x[10];
-	return true;
-}
-
-
-int RISCV_CPUComponent::GetDyntransICshift() const
-{
-	// A "parcel" is 16 bits (shift = 1). Most instructions are 32 bits
-	// wide, but it varies.
-	return 1;
-}
-
-
-void (*RISCV_CPUComponent::GetDyntransToBeTranslated())(CPUDyntransComponent*, DyntransIC*)
-{
-	return instr_ToBeTranslated;
-}
-
-
-bool RISCV_CPUComponent::VirtualToPhysical(uint64_t vaddr, uint64_t& paddr,
-	bool& writable)
-{
-	paddr = vaddr;
-	writable = true;
-	return true;
-}
-
-
-uint64_t RISCV_CPUComponent::PCtoInstructionAddress(uint64_t pc)
-{
-	return pc;
-}
-
-
-size_t RISCV_CPUComponent::DisassembleInstruction(uint64_t vaddr, vector<string>& result)
-{
-	uint16_t iwords[RISCV_MAX_PARCELS];
-
-	AddressSelect(vaddr);
-	bool readOk = ReadData(iwords[0], m_isBigEndian? BigEndian : LittleEndian);
-	int nparcels = 0;
-	if (readOk) {
-		/*
-		 *  Figure out RISC-V instruction length from the first
-		 *  16-bit "parcel" (which may be a whole or a partial instruction):
-		 *
-		 *	xxxxxxxxxxxxxxaa	aa != 11	16-bit (1 parcel)
-		 *	xxxxxxxxxxxbbb11	bbb != 111	32-bit (2 parcels)
-		 *	xxxxxxxxxx011111			48-bit (3 parcels)
-		 *	xxxxxxxxx0111111			64-bit (4 parcels)
-		 *	xnnnxxxxx1111111	nnn != 111	(80+16*nnn)-bit
-		 *	x111xxxxx1111111			>= 192 bit
-		 */
-
-		int aa = iwords[0] & 3, bbb = (iwords[0] >> 2) & 7;
-
-		nparcels = 1;
-		
-		if (aa == 3) {
-			nparcels = 2;
-			if (bbb == 7) {
-				nparcels = 3;
-				if (iwords[0] & 0x20) {
-					nparcels = 4;
-					if (iwords[0] & 0x40) {
-						int nnn = (iwords[0] >> 12) & 7;
-						nparcels = 5 + nnn;
-						
-						if (nparcels > RISCV_MAX_PARCELS) {
-							result.push_back("too many parcels in instruction");
-							nparcels = 0;
-						}
-					} 
-				} 
-			}
-		}
-
-		int instructionParcelsSuccessfullyRead = 1;
-		for (int i = 1; i < nparcels; ++i) {
-			AddressSelect(vaddr + i * sizeof(uint16_t));
-			if (ReadData(iwords[i], m_isBigEndian? BigEndian : LittleEndian))
-				instructionParcelsSuccessfullyRead ++;
-		}
-
-		if (instructionParcelsSuccessfullyRead != nparcels)
-			nparcels = 0;
-	}
-
-	if (nparcels == 0) {
-		result.push_back("instruction could not be read");
-		return 0;
-	}
-
-	stringstream ssHex;
-	ssHex.flags(std::ios::hex);
-	for (int i = nparcels-1; i >= 0; --i)
-		ssHex << std::setfill('0') << std::setw(4) << (uint32_t) iwords[i];
-
-	result.push_back(ssHex.str());
-
-
-	stringstream ssOpcode;
-	stringstream ssArgs;
-	stringstream ssComments;
-
-
-	/*
-	 *  See this URL for a nice ordered list of all RISC-V instructions:
-	 *
-	 *  https://github.com/rv8-io/rv8/blob/master/doc/pdf/riscv-instructions.pdf
-	 */
-
-	int opcode = iwords[0] & 0x7f;
-	int rd = (iwords[0] >> 7) & 31;
-	uint64_t requiredExtension = 0;
-
-	/*
-	 *  RV32I Base Integer Instruction Set:
-	 */
-	// TYPE-U:
-	// TYPE-UJ:
-	if (opcode == 0x6f) {
-		//  jal
-		int32_t simm = ((iwords[1] & 0x8000) << 5);
-		simm |= ((iwords[1] & 0x7fe0) >> 4);
-		simm |= ((iwords[1] & 0x0010) << 7);
-		simm |= ((iwords[1] & 0x000f) << 16);
-		simm |= ((iwords[0] & 0xf000) << 0);
-		simm <<= 11;
-		simm >>= 11;
-		ssOpcode << (rd ? "jal" : "j");
-		if (rd)
-			ssArgs << RISCV_regnames[rd] << ",";
-		uint64_t addr = vaddr + simm;
-		ssArgs.flags(std::ios::hex | std::ios::showbase);
-		ssArgs << std::setfill('0') << addr;
-		string symbol = GetSymbolRegistry().LookupAddress(addr, true);
-		if (symbol != "")
-			ssArgs << " <" + symbol + ">";
-		requiredExtension = RISCV_EXTENSION_I;
-	}
-	// TYPE-I:
-	// TYPE-SB:
-	// TYPE-S:
-	// TYPE-R:
-	
-	else {
-		ssOpcode << "unknown main opcode 0x";
-		ssOpcode.flags(std::ios::hex);
-		ssOpcode << std::setfill('0') << std::setw(2) << (int)opcode;
-	}
-
-
-	result.push_back(ssOpcode.str());
-	result.push_back(ssArgs.str());
-
-	string comments = ssComments.str();
-	if (comments.length() > 0)
-		result.push_back(comments);
-
-	if ((m_extensions & requiredExtension) != requiredExtension) {
-		if (comments.length() == 0)
-			result.push_back("");
-	
-		result.push_back("; extension not implemented by this CPU");
-	}
-
-	return sizeof(uint16_t) * nparcels;
-}
-
-
-string RISCV_CPUComponent::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "description")
-		return "RISC-V processor.";
-
-	return Component::GetAttribute(attributeName);
-}
-
-
-/*****************************************************************************/
-
-
-/*
-DYNTRANS_INSTR(RISCV_CPUComponent,b)
-{
-	DYNTRANS_INSTR_HEAD(RISCV_CPUComponent)
-	cpu->m_pc = ic->arg[0].u32;
-	cpu->DyntransPCtoPointers();
-}
-
-
-DYNTRANS_INSTR(RISCV_CPUComponent,lda_displacement)
-{
-	DYNTRANS_INSTR_HEAD(RISCV_CPUComponent)
-	REG32(ic->arg[2]) = ic->arg[0].u32;
-	cpu->m_nextIC = ic + 2;
-}
-
-
-DYNTRANS_INSTR(RISCV_CPUComponent,mov_lit_reg)
-{
-	REG32(ic->arg[2]) = ic->arg[0].u32;
-}
-*/
-
-
-/*****************************************************************************/
-
-
-void RISCV_CPUComponent::Translate(uint16_t iwords[], int nparcels, struct DyntransIC* ic)
-{
-	UI* ui = GetUI();	// for debug messages
-
-// TODO:
-	unsigned int opcode = iwords[0];
-
-	if (ic->f == NULL && ui != NULL) {
-		stringstream ss;
-		ss.flags(std::ios::hex);
-		ss << "unimplemented opcode 0x" << opcode;
-		ui->ShowDebugMessage(this, ss.str());
-	}
-}
-
-
-DYNTRANS_INSTR(RISCV_CPUComponent,ToBeTranslated)
-{
-	DYNTRANS_INSTR_HEAD(RISCV_CPUComponent)
-
-	cpu->DyntransToBeTranslatedBegin(ic);
-
-	uint16_t iwords[RISCV_MAX_PARCELS];
-	if (cpu->DyntransReadInstruction(iwords[0])) {
-		// See DisassembleInstruction for details about the length. 
-		int aa = iwords[0] & 3, bbb = (iwords[0] >> 2) & 7;
-		int nparcels = 1;
-		if (aa == 3) {
-			nparcels = 2;
-			if (bbb == 7) {
-				nparcels = 3;
-				if (iwords[0] & 0x20) {
-					nparcels = 4;
-					if (iwords[0] & 0x40) {
-						int nnn = (iwords[0] >> 12) & 7;
-						nparcels = 5 + nnn;
-						
-						if (nparcels > RISCV_MAX_PARCELS) {
-							UI* ui = cpu->GetUI();
-							ui->ShowDebugMessage(cpu, "too many parcels in instruction");
-							nparcels = 0;
-						}
-					} 
-				} 
-			}
-		}
-
-		int instructionParcelsSuccessfullyRead = 1;
-		for (int i = 1; i < nparcels; ++i) {
-			if (cpu->DyntransReadInstruction(iwords[i], sizeof(iwords[0]) * i))
-				instructionParcelsSuccessfullyRead ++;
-		}
-
-		if (instructionParcelsSuccessfullyRead == nparcels) {
-			cpu->Translate(iwords, nparcels, ic);
-		} else {
-			UI* ui = cpu->GetUI();
-			ui->ShowDebugMessage(cpu, "last part of instruction could not be read");
-		}
-	}
-
-	cpu->DyntransToBeTranslatedDone(ic);
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_RISCV_CPUComponent_Create()
-{
-	refcount_ptr<Component> cpu = ComponentFactory::CreateComponent("riscv_cpu");
-	UnitTest::Assert("component was not created?", !cpu.IsNULL());
-
-	const StateVariable * p = cpu->GetVariable("a0");
-	UnitTest::Assert("cpu has no a0 state variable?", p != NULL);
-}
-
-#if 0
-static void Test_RISCV_CPUComponent_Disassembly_Basic()
-{
-	refcount_ptr<Component> RISCV_cpu = ComponentFactory::CreateComponent("riscv_cpu");
-	CPUComponent* cpu = RISCV_cpu->AsCPUComponent();
-
-	vector<string> result;
-	size_t len;
-	unsigned char instruction[sizeof(uint32_t) * 2];
-
-	// This assumes that the default endianness is little endian...
-	instruction[0] = 0x00;
-	instruction[1] = 0x30;
-	instruction[2] = 0x68;
-	instruction[3] = 0x8c;
-
-	instruction[4] = 0x01;
-	instruction[5] = 0x23;
-	instruction[6] = 0x34;
-	instruction[7] = 0x45;
-
-	len = cpu->DisassembleInstruction(0x12345678, sizeof(instruction), instruction, result);
-
-	UnitTest::Assert("disassembled instruction was wrong length?", len, 8);
-	UnitTest::Assert("disassembly result incomplete?", result.size(), 3);
-	UnitTest::Assert("disassembly result[0]", result[0], "8c683000 45342301");
-	UnitTest::Assert("disassembly result[1]", result[1], "lda");
-	UnitTest::Assert("disassembly result[2]", result[2], "0x45342301,r13");
-}
-
-static GXemul SimpleMachine()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add mainbus");
-	gxemul.GetCommandInterpreter().RunCommand("add riscv_cpu mainbus0");
-	gxemul.GetCommandInterpreter().RunCommand("add ram mainbus0");
-	gxemul.GetCommandInterpreter().RunCommand("ram0.memoryMappedBase = 0x3fe00000");
-	gxemul.GetCommandInterpreter().RunCommand("ram0.memoryMappedSize = 0x1000");
-	return gxemul;
-}
-
-static void Test_RISCV_CPUComponent_Execute_mov()
-{
-	GXemul gxemul = SimpleMachine();
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-
-	bus->AddressSelect(0x3fe00048);
-	bus->WriteData((uint32_t)0x5c201e06, LittleEndian);	// mov   6,r4
-	bus->AddressSelect(0x3fe0004c);
-	bus->WriteData((uint32_t)0x5c201e06, LittleEndian);	// mov   6,r4
-
-	cpu->SetVariableValue("pc", "0x3fe00048");
-	cpu->SetVariableValue("r4", "0x1234");
-
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("pc should have increased", cpu->GetVariable("pc")->ToInteger(), 0x3fe0004c);
-	UnitTest::Assert("r4 should have been modified", cpu->GetVariable("r4")->ToInteger(), 6);
-
-	cpu->SetVariableValue("r4", "0x12345");
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("pc should have increased again", cpu->GetVariable("pc")->ToInteger(), 0x3fe00050);
-	UnitTest::Assert("r4 should have been modified again", cpu->GetVariable("r4")->ToInteger(), 6);
-}
-
-static void Test_RISCV_CPUComponent_Execute_b()
-{
-	GXemul gxemul = SimpleMachine();
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-
-	bus->AddressSelect(0x3fe00004);
-	bus->WriteData((uint32_t)0x080006c0, LittleEndian);	// b 0x3fe006c4
-
-	cpu->SetVariableValue("pc", "0x3fe00004");
-
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("pc should have changed", cpu->GetVariable("pc")->ToInteger(), 0x3fe006c4);
-
-	cpu->SetVariableValue("pc", "0x3fe00004");
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute(1);
-
-	UnitTest::Assert("pc should have changed again", cpu->GetVariable("pc")->ToInteger(), 0x3fe006c4);
-}
-
-static void Test_RISCV_CPUComponent_Execute_lda_with_offset()
-{
-	GXemul gxemul = SimpleMachine();
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-
-	bus->AddressSelect(0x3fe00010);
-	bus->WriteData((uint32_t)0x8c180f13, LittleEndian);	// lda r3, 0xf13
-
-	cpu->SetVariableValue("pc", "0x3fe00010");
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1);
-	UnitTest::Assert("lda length", cpu->GetVariable("pc")->ToInteger(), 0x3fe00014);
-	UnitTest::Assert("lda", cpu->GetVariable("r3")->ToInteger(), 0xf13);
-}
-
-static void Test_RISCV_CPUComponent_Execute_lda_with_displacement()
-{
-	GXemul gxemul = SimpleMachine();
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
-	AddressDataBus* bus = cpu->AsAddressDataBus();
-
-	bus->AddressSelect(0x3fe00010);
-	bus->WriteData((uint32_t)0x8cf03000, LittleEndian);	// lda
-	bus->AddressSelect(0x3fe00014);
-	bus->WriteData((uint32_t)0x3fe0507c, LittleEndian);	//     0x3fe0507c, g14
-
-	cpu->SetVariableValue("pc", "0x3fe00010");
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1);
-	UnitTest::Assert("lda length", cpu->GetVariable("pc")->ToInteger(), 0x3fe00018);
-	UnitTest::Assert("lda", cpu->GetVariable("g14")->ToInteger(), 0x3fe0507c);
-}
-#endif
-
-UNITTESTS(RISCV_CPUComponent)
-{
-	UNITTEST(Test_RISCV_CPUComponent_Create);
-	
-#if 0
-	UNITTEST(Test_RISCV_CPUComponent_Disassembly_Basic);
-
-	UNITTEST(Test_RISCV_CPUComponent_Execute_mov);
-	UNITTEST(Test_RISCV_CPUComponent_Execute_b);
-	UNITTEST(Test_RISCV_CPUComponent_Execute_lda_with_offset);
-	UNITTEST(Test_RISCV_CPUComponent_Execute_lda_with_displacement);
-#endif
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/components/machines/CycloneVHMachine.cc gxemul-0.7.0+dfsg/src/components/machines/CycloneVHMachine.cc
--- gxemul-0.6.2/src/components/machines/CycloneVHMachine.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/machines/CycloneVHMachine.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,120 +0,0 @@
-/*
- *  Copyright (C) 2018-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  For experiments with uClinux/i960.
- *
- *  A binary (vmlinux) can be found on this page:
- *  https://web.archive.org/web/20010417034914/http://www.cse.ogi.edu/~kma/uClinux.html
- *
- *  NOTE!!! The binary at http://www.uclinux.org/pub/uClinux/ports/i960/ is corrupt;
- *          it seems to have been uploaded/encoded with the wrong character encoding.
- *          (At least it is broken as of 2016-04-18.)
- *
- *
- *  See the following link for details about the Cyclone VH board:
- *  
- *  http://www.nj7p.org/Manuals/PDFs/Intel/273194-003.PDF
- *  "EVAL80960VH Evaluation Platform Board Manual, December 1998"
- *
- *  and for the CPU:
- *
- *  http://www.nj7p.info/Manuals/PDFs/Intel/273173-001.PDF
- *  "i960 VH Processor Developer's Manual, October 1998"
- */
-
-#include "components/CycloneVHMachine.h"
-#include "ComponentFactory.h"
-#include "GXemul.h"
-
-
-refcount_ptr<Component> CycloneVHMachine::Create(const ComponentCreateArgs& args)
-{
-	// Defaults:
-	ComponentCreationSettings settings;
-	settings["cpu"] = "i960CA";	// TODO: uClinux is compiled for i960Jx
-	settings["ram"] = "0x00400000";
-
-	if (!ComponentFactory::GetCreationArgOverrides(settings, args))
-		return NULL;
-
-
-	refcount_ptr<Component> machine = ComponentFactory::CreateComponent("machine");
-	if (machine.IsNULL())
-		return NULL;
-
-	machine->SetVariableValue("template", "\"cyclonevh\"");
-
-
-	refcount_ptr<Component> mainbus =
-	    ComponentFactory::CreateComponent("mainbus");
-	if (mainbus.IsNULL())
-		return NULL;
-
-	machine->AddChild(mainbus);
-
-	// TODO: CPU frequency is perhaps 100 MHz?
-	refcount_ptr<Component> cpu =
-	    ComponentFactory::CreateComponent("i960_cpu(model=" + settings["cpu"] + ")");
-	if (cpu.IsNULL())
-		return NULL;
-
-	mainbus->AddChild(cpu);
-
-
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-	if (ram.IsNULL())
-		return NULL;
-
-	// DRAM is at a3c0 0000 - a3ff ffff according to
-	// https://groups.google.com/forum/#!topic/intel.microprocessors.i960/tgpjDcW5Dxc
-	ram->SetVariableValue("memoryMappedBase", "0xa3c00000");
-	ram->SetVariableValue("memoryMappedSize", settings["ram"]);
-	mainbus->AddChild(ram);
-
-	// There is supposed to be a LED at e0040000 too. TODO.
-	
-	return machine;
-}
-
-
-string CycloneVHMachine::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "template")
-		return "yes";
-
-	if (attributeName == "machine")
-		return "yes";
-
-	if (attributeName == "description")
-		return "Cyclone/VH i960 evaluation board machine.";
-
-	if (attributeName == "comments")
-		return "For experiments with uClinux/i960.";
-
-	return "";
-}
-
diff -Nru gxemul-0.6.2/src/components/machines/HP700RXMachine.cc gxemul-0.7.0+dfsg/src/components/machines/HP700RXMachine.cc
--- gxemul-0.6.2/src/components/machines/HP700RXMachine.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/machines/HP700RXMachine.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,119 +0,0 @@
-/*
- *  Copyright (C) 2018-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  HP 700/RX X-terminal with an i960CA CPU.
- *
- *  Bogus skeleton so far.
- *
- *  My machine says:
- *
- *  2048 KB Base RAM
- *  8192 KB Expansion RAM
- *  2048 KB Video RAM
- *
- *  The ROM seems to be 512 KB at 0xfff80000.
- */
-
-#include "components/HP700RXMachine.h"
-#include "ComponentFactory.h"
-#include "GXemul.h"
-
-
-refcount_ptr<Component> HP700RXMachine::Create(const ComponentCreateArgs& args)
-{
-	// Defaults:
-	ComponentCreationSettings settings;
-	settings["cpu"] = "i960CA";
-	settings["ram"] = "0x00200000";
-
-	if (!ComponentFactory::GetCreationArgOverrides(settings, args))
-		return NULL;
-
-
-	refcount_ptr<Component> machine = ComponentFactory::CreateComponent("machine");
-	if (machine.IsNULL())
-		return NULL;
-
-	machine->SetVariableValue("template", "\"hp700rx\"");
-
-
-	refcount_ptr<Component> mainbus =
-	    ComponentFactory::CreateComponent("mainbus");
-	if (mainbus.IsNULL())
-		return NULL;
-
-	machine->AddChild(mainbus);
-
-
-	refcount_ptr<Component> cpu =
-	    ComponentFactory::CreateComponent("i960_cpu(model=" + settings["cpu"] + ")");
-	if (cpu.IsNULL())
-		return NULL;
-
-	mainbus->AddChild(cpu);
-
-
-	// DRAM (guess)
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-	if (ram.IsNULL())
-		return NULL;
-	ram->SetVariableValue("memoryMappedBase", "0x3fe00000");
-	ram->SetVariableValue("memoryMappedSize", settings["ram"]);
-	mainbus->AddChild(ram);
-
-	// ROM
-	refcount_ptr<Component> rom = ComponentFactory::CreateComponent("ram");
-	if (rom.IsNULL())
-		return NULL;
-	rom->SetVariableValue("name", "\"rom0\"");
-	rom->SetVariableValue("memoryMappedBase", "0xfff80000");
-	rom->SetVariableValue("memoryMappedSize", "524288");
-	// rom->SetVariableValue("writeProtect", "true");
-	mainbus->AddChild(rom);
-
-	return machine;
-}
-
-
-string HP700RXMachine::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "template")
-		return "yes";
-
-	if (attributeName == "machine")
-		return "yes";
-
-	if (attributeName == "description")
-		return "HP 700/RX X-terminal (i960).";
-
-	if (attributeName == "comments")
-		return "For experiments that could eventually lead up to "
-			"running custom code on the HP 700/RX.";
-
-	return "";
-}
-
diff -Nru gxemul-0.6.2/src/components/machines/MachineComponent.cc gxemul-0.7.0+dfsg/src/components/machines/MachineComponent.cc
--- gxemul-0.6.2/src/components/machines/MachineComponent.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/machines/MachineComponent.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,74 +0,0 @@
-/*
- *  Copyright (C) 2008-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "components/MachineComponent.h"
-
-
-MachineComponent::MachineComponent()
-	: Component("machine", "machine")
-{
-}
-
-
-refcount_ptr<Component> MachineComponent::Create(const ComponentCreateArgs& args)
-{
-	return new MachineComponent();
-}
-
-
-string MachineComponent::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "machine")
-		return "yes";
-
-	if (attributeName == "description")
-		return "A generic machine container.";
-
-	return Component::GetAttribute(attributeName);
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_MachineComponent_IsMachine()
-{
-	UnitTest::Assert("the MachineComponent should be a machine",
-	    ComponentFactory::HasAttribute("machine", "machine"));
-}
-
-UNITTESTS(MachineComponent)
-{
-	UNITTEST(Test_MachineComponent_IsMachine);
-}
-
-#endif
-
diff -Nru gxemul-0.6.2/src/components/machines/Makefile.skel gxemul-0.7.0+dfsg/src/components/machines/Makefile.skel
--- gxemul-0.6.2/src/components/machines/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/machines/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,20 +0,0 @@
-#
-#  Makefile for GXemul src/components/machines
-#
-
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(CPEDANTIC) $(INCLUDE2)
-LIBS=$(OTHERLIBS)
-
-OBJS=MachineComponent.o MVME187Machine.o TestM88KMachine.o \
-	HP700RXMachine.o CycloneVHMachine.o RISCVvirtMachine.o
-
-all: $(OBJS)
-
-$(OBJS): Makefile
-
-clean:
-	rm -f $(OBJS)
-
-clean_all: clean
-	rm -f Makefile
-
diff -Nru gxemul-0.6.2/src/components/machines/MVME187Machine.cc gxemul-0.7.0+dfsg/src/components/machines/MVME187Machine.cc
--- gxemul-0.6.2/src/components/machines/MVME187Machine.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/machines/MVME187Machine.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,141 +0,0 @@
-/*
- *  Copyright (C) 2009-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "components/MVME187Machine.h"
-#include "ComponentFactory.h"
-
-
-/*
- *  This is for experiments with OpenBSD/mvme88k.
- *
- *  NOTE:
- *  =====
- *
- *  MVME88k emulation is already implemented in the old framework. The code
- *  you are looking at now is a complete rewrite using the new framework.
- *
- *
- *
- *
- *  MVME187 according to http://mcg.motorola.com/us/products/docs/pdf/187igd.pdf
- *  ("MVME187 RISC Single Board Computer Installation Guide"):
- *
- *	88100 MPU, two MC88200 or MC88204 CMMUs (one for data cache and
- *		one for instruction cache).
- *	82596CA LAN Ethernet
- *	53C710 SCSI
- *	CD2401 SCC SERIAL IO
- *	PRINTER PORT
- *	MK48T08 BBRAM & CLOCK
- *	EPROM
- *	VME bus
- *
- *  ... and more details from OpenBSD/mvme88k sources:
- *
- *	0xff800000 .. 0xffbfffff = BUG PROM
- *	0xffe00000 .. 0xffe1ffff = BUG SRAM
- *	0xfff00000               = PCCTWO
- *	  0xfff40000             = VME bus
- *	  0xfff43000             = MEMC040 (Memory controller)
- *	  0xfff45000             = CD2401 SCC SERIAL IO (cl0)
- *	  0xfff46000             = 82596 Ethernet (ie0)
- *	  0xfff47000             = 53C710 SCSI (osiop0)
- *	  0xfffc0000             = MK48T08 (nvram0)
- *
- *  Note: It may turn out to be easier to support Lance ethernet (via VME)
- *  than to support the 82596 ethernet controller.
- */
-
-
-refcount_ptr<Component> MVME187Machine::Create(const ComponentCreateArgs& args)
-{
-	// Defaults:
-	ComponentCreationSettings settings;
-	settings["ram"] = "0x2000000";
-
-	if (!ComponentFactory::GetCreationArgOverrides(settings, args))
-		return NULL;
-
-	refcount_ptr<Component> machine =
-	    ComponentFactory::CreateComponent("machine");
-	if (machine.IsNULL())
-		return NULL;
-
-	machine->SetVariableValue("template", "\"mvme187\"");
-
-	refcount_ptr<Component> mainbus =
-	    ComponentFactory::CreateComponent("mainbus");
-	if (mainbus.IsNULL())
-		return NULL;
-
-	machine->AddChild(mainbus);
-
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-	if (ram.IsNULL())
-		return NULL;
-
-	ram->SetVariableValue("memoryMappedSize", settings["ram"]);
-	mainbus->AddChild(ram);
-
-	refcount_ptr<Component> rom = ComponentFactory::CreateComponent("ram");
-	if (rom.IsNULL())
-		return NULL;
-
-	rom->SetVariableValue("name", "\"rom0\"");
-	rom->SetVariableValue("memoryMappedBase", "0xff800000");
-	rom->SetVariableValue("memoryMappedSize", "0x400000");
-	mainbus->AddChild(rom);
-
-	refcount_ptr<Component> cpu =
-	    ComponentFactory::CreateComponent("m88k_cpu(model=88100)");
-
-	if (cpu.IsNULL())
-		return NULL;
-
-	mainbus->AddChild(cpu);
-
-	return machine;
-}
-
-
-string MVME187Machine::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "template")
-		return "yes";
-
-	if (attributeName == "machine")
-		return "yes";
-
-	if (attributeName == "description")
-		return "MVME187 machine.";
-
-	if (attributeName == "comments")
-		return "For experiments with <a href=\"http://www.openbsd.org/mvme88k.html\">OpenBSD/mvme88k</a>.";
-
-	return "";
-}
-
diff -Nru gxemul-0.6.2/src/components/machines/RISCVvirtMachine.cc gxemul-0.7.0+dfsg/src/components/machines/RISCVvirtMachine.cc
--- gxemul-0.6.2/src/components/machines/RISCVvirtMachine.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/machines/RISCVvirtMachine.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,127 +0,0 @@
-/*
- *  Copyright (C) 2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  RISC-V "virt" machine
- *
- *  The idea is to mimic the "virt" machine in QEMU, to be able to run code
- *  such as FreeBSD/riscv build for that machine.
- *
- *	    [VIRT_DEBUG] =       {        0x0,         0x100 },
- *	    [VIRT_MROM] =        {     0x1000,       0x11000 },
- *	    [VIRT_TEST] =        {   0x100000,        0x1000 },
- *	    [VIRT_CLINT] =       {  0x2000000,       0x10000 },
- *	    [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
- *	    [VIRT_UART0] =       { 0x10000000,         0x100 },
- *	    [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
- *	    [VIRT_DRAM] =        { 0x80000000,           0x0 },
- *	    [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
- *	    [VIRT_PCIE_PIO] =    { 0x03000000,    0x00010000 },
- *	    [VIRT_PCIE_ECAM] =   { 0x30000000, 0x10000000 }
- */
-
-#include "components/RISCVvirtMachine.h"
-#include "ComponentFactory.h"
-#include "GXemul.h"
-
-
-refcount_ptr<Component> RISCVvirtMachine::Create(const ComponentCreateArgs& args)
-{
-	// Defaults:
-	ComponentCreationSettings settings;
-	settings["cpu"] = "RV64G";
-	settings["ram"] = "0x80000000";	// 2 GB
-	settings["ncpus"] = "1";
-
-	if (!ComponentFactory::GetCreationArgOverrides(settings, args))
-		return NULL;
-
-
-	refcount_ptr<Component> machine =
-	    ComponentFactory::CreateComponent("machine", args.gxemul);
-	if (machine.IsNULL())
-		return NULL;
-
-	machine->SetVariableValue("template", "\"riscv-virt\"");
-
-
-	refcount_ptr<Component> mainbus =
-	    ComponentFactory::CreateComponent("mainbus", args.gxemul);
-	if (mainbus.IsNULL())
-		return NULL;
-
-	machine->AddChild(mainbus);
-
-
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram", args.gxemul);
-	if (ram.IsNULL())
-		return NULL;
-
-	ram->SetVariableValue("memoryMappedSize", settings["ram"]);
-	ram->SetVariableValue("memoryMappedBase", "0x80000000");
-	mainbus->AddChild(ram);
-
-
-	int ncpus;
-	stringstream tmpss3;
-	tmpss3 << settings["ncpus"];
-	tmpss3 >> ncpus;
-	if (ncpus < 1) {
-		if (args.gxemul != NULL)
-			args.gxemul->GetUI()->ShowDebugMessage("nr of cpus must be more than 0.");
-		return NULL;
-	}
-
-	for (int i=0; i<ncpus; ++i) {
-		refcount_ptr<Component> cpu =
-		    ComponentFactory::CreateComponent("riscv_cpu(model=" + settings["cpu"] + ")", args.gxemul);
-		if (cpu.IsNULL())
-			return NULL;
-
-		if (i > 0)
-			cpu->SetVariableValue("paused", "true");
-
-		mainbus->AddChild(cpu);
-	}
-
-	return machine;
-}
-
-
-string RISCVvirtMachine::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "template")
-		return "yes";
-
-	if (attributeName == "machine")
-		return "yes";
-
-	if (attributeName == "description")
-		return "RISC-V virt machine.";
-
-	return "";
-}
-
diff -Nru gxemul-0.6.2/src/components/machines/TestM88KMachine.cc gxemul-0.7.0+dfsg/src/components/machines/TestM88KMachine.cc
--- gxemul-0.6.2/src/components/machines/TestM88KMachine.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/machines/TestM88KMachine.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,130 +0,0 @@
-/*
- *  Copyright (C) 2009-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "components/TestM88KMachine.h"
-#include "ComponentFactory.h"
-#include "GXemul.h"
-
-
-refcount_ptr<Component> TestM88KMachine::Create(const ComponentCreateArgs& args)
-{
-	// Defaults:
-	ComponentCreationSettings settings;
-	settings["cpu"] = "88100";
-	settings["ram"] = "0x2000000";
-	settings["ncpus"] = "1";
-
-	if (!ComponentFactory::GetCreationArgOverrides(settings, args))
-		return NULL;
-
-
-	refcount_ptr<Component> machine =
-	    ComponentFactory::CreateComponent("machine");
-	if (machine.IsNULL())
-		return NULL;
-
-	machine->SetVariableValue("template", "\"testm88k\"");
-
-
-	refcount_ptr<Component> mainbus =
-	    ComponentFactory::CreateComponent("mainbus");
-	if (mainbus.IsNULL())
-		return NULL;
-
-	machine->AddChild(mainbus);
-
-
-	int ncpus;
-	stringstream tmpss3;
-	tmpss3 << settings["ncpus"];
-	tmpss3 >> ncpus;
-	if (ncpus < 1) {
-		if (args.gxemul != NULL)
-			args.gxemul->GetUI()->ShowDebugMessage("nr of cpus must be more than 0.");
-		return NULL;
-	}
-
-	for (int i=0; i<ncpus; ++i) {
-		refcount_ptr<Component> cpu =
-		    ComponentFactory::CreateComponent("m88k_cpu(r31=0xff0,model=" + settings["cpu"] + ")");
-		if (cpu.IsNULL())
-			return NULL;
-
-		if (i > 0)
-			cpu->SetVariableValue("paused", "true");
-
-		mainbus->AddChild(cpu);
-	}
-
-
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-	if (ram.IsNULL())
-		return NULL;
-
-	ram->SetVariableValue("memoryMappedSize", settings["ram"]);
-	mainbus->AddChild(ram);
-
-
-	refcount_ptr<Component> fb_videoram = ComponentFactory::CreateComponent("ram");
-	if (fb_videoram.IsNULL())
-		return NULL;
-
-	fb_videoram->SetVariableValue("name", "\"fb_videoram0\"");
-	fb_videoram->SetVariableValue("memoryMappedBase", "0x12000000");
-	fb_videoram->SetVariableValue("memoryMappedSize",   "0xf00000");
-	mainbus->AddChild(fb_videoram);
-
-
-	refcount_ptr<Component> rom = ComponentFactory::CreateComponent("ram");
-	if (rom.IsNULL())
-		return NULL;
-
-	rom->SetVariableValue("name", "\"rom0\"");
-	rom->SetVariableValue("memoryMappedBase", "0xff800000");
-	rom->SetVariableValue("memoryMappedSize",   "0x400000");
-	rom->SetVariableValue("writeProtect", "true");
-	mainbus->AddChild(rom);
-
-
-	return machine;
-}
-
-
-string TestM88KMachine::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "template")
-		return "yes";
-
-	if (attributeName == "machine")
-		return "yes";
-
-	if (attributeName == "description")
-		return "Experimental M88K machine.";
-
-	return "";
-}
-
diff -Nru gxemul-0.6.2/src/components/Makefile.skel gxemul-0.7.0+dfsg/src/components/Makefile.skel
--- gxemul-0.6.2/src/components/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,36 +0,0 @@
-#
-#  Makefile for GXemul src/components
-#
-
-all: do_special do_machines do_busses do_cpu do_memory
-
-do_busses:
-	cd busses; $(MAKE)
-
-do_cpu:
-	cd cpu; $(MAKE)
-
-do_special:
-	cd special; $(MAKE)
-
-do_machines:
-	cd machines; $(MAKE)
-
-do_memory:
-	cd memory; $(MAKE)
-
-clean:
-	cd busses; $(MAKE) clean
-	cd cpu; $(MAKE) clean
-	cd special; $(MAKE) clean
-	cd machines; $(MAKE) clean
-	cd memory; $(MAKE) clean
-
-clean_all: clean
-	cd busses; $(MAKE) clean_all
-	cd cpu; $(MAKE) clean_all
-	cd special; $(MAKE) clean_all
-	cd machines; $(MAKE) clean_all
-	cd memory; $(MAKE) clean_all
-	rm -f Makefile
-
diff -Nru gxemul-0.6.2/src/components/memory/CacheComponent.cc gxemul-0.7.0+dfsg/src/components/memory/CacheComponent.cc
--- gxemul-0.6.2/src/components/memory/CacheComponent.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/memory/CacheComponent.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,444 +0,0 @@
-/*
- *  Copyright (C) 2010-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "components/CacheComponent.h"
-#include "GXemul.h"
-
-
-CacheComponent::CacheComponent(const string& visibleClassName)
-	: Component("cache", visibleClassName)
-	, m_size(0)
-	, m_lineSize(64)
-	, m_lastDumpAddr(0)
-	, m_associativity(1)
-	, m_addressSelect(0)
-{
-	AddVariable("size", &m_size);
-	AddVariable("lineSize", &m_lineSize);
-	AddVariable("lastDumpAddr", &m_lastDumpAddr);
-	AddVariable("associativity", &m_associativity);
-//	AddCustomVariable("data", &m_dataHandler);
-}
-
-
-CacheComponent::~CacheComponent()
-{
-}
-
-
-refcount_ptr<Component> CacheComponent::Create(const ComponentCreateArgs& args)
-{
-	return new CacheComponent();
-}
-
-
-string CacheComponent::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "description")
-		return "A generic memory cache component.";
-
-	return Component::GetAttribute(attributeName);
-}
-
-
-string CacheComponent::GenerateDetails() const
-{
-	stringstream ss;
-	ss << Component::GenerateDetails();
-
-	if (!ss.str().empty())
-		ss << ", ";
-
-	if (m_size >= (1 << 30))
-		ss << (m_size >> 30) << " GB";
-	else if (m_size >= (1 << 20))
-		ss << (m_size >> 20) << " MB";
-	else if (m_size >= (1 << 10))
-		ss << (m_size >> 10) << " KB";
-	else if (m_size != 1)
-		ss << m_size << " bytes";
-	else
-		ss << m_size << " byte";
-
-	if (m_associativity == 0)
-		ss << ", fully associative, ";
-	else if (m_associativity == 1)
-		ss << ", direct-mapped, ";
-	else
-		ss << ", " << m_associativity << "-way, ";
-
-	if (m_lineSize >= (1 << 30))
-		ss << (m_lineSize >> 30) << " GB";
-	else if (m_lineSize >= (1 << 20))
-		ss << (m_lineSize >> 20) << " MB";
-	else if (m_lineSize >= (1 << 10))
-		ss << (m_lineSize >> 10) << " KB";
-	else if (m_lineSize != 1)
-		ss << m_lineSize << " bytes";
-	else
-		ss << m_lineSize << " byte";
-
-	ss << " per line";
-
-	return ss.str();
-}
-
-
-void CacheComponent::ResetState()
-{
-}
-
-
-void CacheComponent::GetMethodNames(vector<string>& names) const
-{
-	// Add our method names...
-	names.push_back("dump");
-
-	// ... and make sure to call the base class implementation:
-	Component::GetMethodNames(names);
-}
-
-
-bool CacheComponent::MethodMayBeReexecutedWithoutArgs(const string& methodName) const
-{
-	if (methodName == "dump")
-		return true;
-
-	// ... and make sure to call the base class implementation:
-	return Component::MethodMayBeReexecutedWithoutArgs(methodName);
-}
-
-
-void CacheComponent::ExecuteMethod(GXemul* gxemul, const string& methodName,
-	const vector<string>& arguments)
-{
-	if (methodName == "dump") {
-		uint64_t vaddr = m_lastDumpAddr;
-
-		if (arguments.size() > 1) {
-			gxemul->GetUI()->ShowDebugMessage("syntax: .dump [addr]\n");
-			return;
-		}
-
-		if (arguments.size() == 1) {
-			gxemul->GetUI()->ShowDebugMessage("TODO: parse address expression\n");
-			gxemul->GetUI()->ShowDebugMessage("(for now, only hex immediate values are supported!)\n");
-
-			stringstream ss;
-			ss << arguments[0];
-			ss.flags(std::ios::hex);
-			ss >> vaddr;
-		}
-
-		const int nRows = 16;
-		for (int i=0; i<nRows; i++) {
-			const size_t len = 16;
-			unsigned char data[len];
-			bool readable[len];
-
-			stringstream ss;
-			ss.flags(std::ios::hex);
-
-			if (vaddr > 0xffffffff)
-				ss << std::setw(16);
-			else
-				ss << std::setw(8);
-
-			ss << std::setfill('0') << vaddr;
-
-			size_t k;
-			for (k=0; k<len; ++k) {
-				AddressSelect(vaddr + k);
-				readable[k] = ReadData(data[k], BigEndian);
-			}
-			
-			ss << " ";
-			
-			for (k=0; k<len; ++k) {
-				if ((k&3) == 0)
-					ss << " ";
-
-				ss << std::setw(2) << std::setfill('0');
-				if (readable[k])
-					ss << (int)data[k];
-				else
-					ss << "--";
-			}
-
-			ss << "  ";
-
-			for (k=0; k<len; ++k) {
-				char s[2];
-				s[0] = data[k] >= 32 && data[k] < 127? data[k] : '.';
-				s[1] = '\0';
-				
-				if (readable[k])
-					ss << s;
-				else
-					ss << "-";
-			}
-			
-			ss << "\n";
-
-			gxemul->GetUI()->ShowDebugMessage(ss.str());
-
-			vaddr += len;
-		}
-
-		m_lastDumpAddr = vaddr;
-
-		return;
-	}
-
-	// Call base...
-	Component::ExecuteMethod(gxemul, methodName, arguments);
-}
-
-
-AddressDataBus* CacheComponent::AsAddressDataBus()
-{
-	return this;
-}
-
-
-void CacheComponent::AddressSelect(uint64_t address)
-{
-#if 0
-	m_addressSelect = address;
-
-	uint64_t blockNr = address >> m_blockSizeShift;
-
-	if (blockNr+1 > m_memoryBlocks.size())
-		m_selectedHostMemoryBlock = NULL;
-	else
-		m_selectedHostMemoryBlock = m_memoryBlocks[blockNr];
-
-	m_selectedOffsetWithinBlock = address & (m_blockSize-1);
-#endif
-}
-
-
-bool CacheComponent::ReadData(uint8_t& data, Endianness endianness)
-{
-#if 0
-	if (m_selectedHostMemoryBlock == NULL)
-		data = 0;
-	else
-		data = (((uint8_t*)m_selectedHostMemoryBlock)
-		    [m_selectedOffsetWithinBlock]);
-
-	return true;
-#endif
-	return false;
-}
-
-
-bool CacheComponent::ReadData(uint16_t& data, Endianness endianness)
-{
-#if 0
-	assert((m_addressSelect & 1) == 0);
-
-	if (m_selectedHostMemoryBlock == NULL)
-		data = 0;
-	else
-		data = (((uint16_t*)m_selectedHostMemoryBlock)
-		    [m_selectedOffsetWithinBlock >> 1]);
-
-	if (endianness == BigEndian)
-		data = BE16_TO_HOST(data);
-	else
-		data = LE16_TO_HOST(data);
-
-	return true;
-#endif
-	return false;
-}
-
-
-bool CacheComponent::ReadData(uint32_t& data, Endianness endianness)
-{
-#if 0
-	assert((m_addressSelect & 3) == 0);
-
-	if (m_selectedHostMemoryBlock == NULL)
-		data = 0;
-	else
-		data = (((uint32_t*)m_selectedHostMemoryBlock)
-		    [m_selectedOffsetWithinBlock >> 2]);
-
-	if (endianness == BigEndian)
-		data = BE32_TO_HOST(data);
-	else
-		data = LE32_TO_HOST(data);
-
-	return true;
-#endif
-	return false;
-}
-
-
-bool CacheComponent::ReadData(uint64_t& data, Endianness endianness)
-{
-#if 0
-	assert((m_addressSelect & 7) == 0);
-
-	if (m_selectedHostMemoryBlock == NULL)
-		data = 0;
-	else
-		data = (((uint64_t*)m_selectedHostMemoryBlock)
-		    [m_selectedOffsetWithinBlock >> 3]);
-
-	if (endianness == BigEndian)
-		data = BE64_TO_HOST(data);
-	else
-		data = LE64_TO_HOST(data);
-
-	return true;
-#endif
-	return false;
-}
-
-
-bool CacheComponent::WriteData(const uint8_t& data, Endianness endianness)
-{
-#if 0
-	if (m_writeProtected)
-		return false;
-
-	if (m_selectedHostMemoryBlock == NULL)
-		m_selectedHostMemoryBlock = AllocateBlock();
-
-	(((uint8_t*)m_selectedHostMemoryBlock)
-	    [m_selectedOffsetWithinBlock]) = data;
-
-	return true;
-#endif
-	return false;
-}
-
-
-bool CacheComponent::WriteData(const uint16_t& data, Endianness endianness)
-{
-#if 0
-	assert((m_addressSelect & 1) == 0);
-
-	if (m_writeProtected)
-		return false;
-
-	if (m_selectedHostMemoryBlock == NULL)
-		m_selectedHostMemoryBlock = AllocateBlock();
-
-	uint16_t d;
-	if (endianness == BigEndian)
-		d = BE16_TO_HOST(data);
-	else
-		d = LE16_TO_HOST(data);
-
-	(((uint16_t*)m_selectedHostMemoryBlock)
-	    [m_selectedOffsetWithinBlock >> 1]) = d;
-
-	return true;
-#endif
-	return false;
-}
-
-
-bool CacheComponent::WriteData(const uint32_t& data, Endianness endianness)
-{
-#if 0
-	assert((m_addressSelect & 3) == 0);
-
-	if (m_writeProtected)
-		return false;
-
-	if (m_selectedHostMemoryBlock == NULL)
-		m_selectedHostMemoryBlock = AllocateBlock();
-
-	uint32_t d;
-	if (endianness == BigEndian)
-		d = BE32_TO_HOST(data);
-	else
-		d = LE32_TO_HOST(data);
-
-	(((uint32_t*)m_selectedHostMemoryBlock)
-	    [m_selectedOffsetWithinBlock >> 2]) = d;
-
-	return true;
-#endif
-	return false;
-}
-
-
-bool CacheComponent::WriteData(const uint64_t& data, Endianness endianness)
-{
-#if 0
-	assert((m_addressSelect & 7) == 0);
-
-	if (m_writeProtected)
-		return false;
-
-	if (m_selectedHostMemoryBlock == NULL)
-		m_selectedHostMemoryBlock = AllocateBlock();
-
-	uint64_t d;
-	if (endianness == BigEndian)
-		d = BE64_TO_HOST(data);
-	else
-		d = LE64_TO_HOST(data);
-
-	(((uint64_t*)m_selectedHostMemoryBlock)
-	    [m_selectedOffsetWithinBlock >> 3]) = d;
-
-	return true;
-#endif
-	return false;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_CacheComponent_AddressDataBus()
-{
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("cache");
-
-	AddressDataBus* bus = ram->AsAddressDataBus();
-	UnitTest::Assert("The CacheComponent should implement the "
-	    "AddressDataBus interface", bus != NULL);
-}
-
-UNITTESTS(CacheComponent)
-{
-	UNITTEST(Test_CacheComponent_AddressDataBus);
-}
-
-#endif
-
diff -Nru gxemul-0.6.2/src/components/memory/Makefile.skel gxemul-0.7.0+dfsg/src/components/memory/Makefile.skel
--- gxemul-0.6.2/src/components/memory/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/memory/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,19 +0,0 @@
-#
-#  Makefile for GXemul src/components/memory
-#
-
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(CPEDANTIC) $(INCLUDE2)
-LIBS=$(OTHERLIBS)
-
-OBJS=CacheComponent.o MemoryMappedComponent.o RAMComponent.o
-
-all: $(OBJS)
-
-$(OBJS): Makefile
-
-clean:
-	rm -f $(OBJS)
-
-clean_all: clean
-	rm -f Makefile
-
diff -Nru gxemul-0.6.2/src/components/memory/MemoryMappedComponent.cc gxemul-0.7.0+dfsg/src/components/memory/MemoryMappedComponent.cc
--- gxemul-0.6.2/src/components/memory/MemoryMappedComponent.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/memory/MemoryMappedComponent.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,79 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "components/MemoryMappedComponent.h"
-
-
-MemoryMappedComponent::MemoryMappedComponent(const string& className,
-		const string& visibleClassName)
-	: Component(className, visibleClassName)
-	, m_memoryMappedBase(0)
-	, m_memoryMappedSize(0)
-	, m_memoryMappedAddrMul(1)
-{
-	AddVariable("memoryMappedBase", &m_memoryMappedBase);
-	AddVariable("memoryMappedSize", &m_memoryMappedSize);
-	AddVariable("memoryMappedAddrMul", &m_memoryMappedAddrMul);
-}
-
-string MemoryMappedComponent::GenerateDetails() const
-{
-	stringstream ss;
-	ss << Component::GenerateDetails();
-
-	const StateVariable* memoryMappedBase = GetVariable("memoryMappedBase");
-	const StateVariable* memoryMappedSize = GetVariable("memoryMappedSize");
-	const StateVariable* memoryMappedAddrMul =
-	    GetVariable("memoryMappedAddrMul");
-	if (memoryMappedBase != NULL && memoryMappedSize != NULL) {
-		if (!ss.str().empty())
-			ss << ", ";
-
-		uint64_t nBytes = memoryMappedSize->ToInteger();
-		if (nBytes >= (1 << 30))
-			ss << (nBytes >> 30) << " GB";
-		else if (nBytes >= (1 << 20))
-			ss << (nBytes >> 20) << " MB";
-		else if (nBytes >= (1 << 10))
-			ss << (nBytes >> 10) << " KB";
-		else if (nBytes != 1)
-			ss << nBytes << " bytes";
-		else
-			ss << nBytes << " byte";
-
-		ss << " at offset ";
-		ss.flags(std::ios::hex | std::ios::showbase);
-		ss << memoryMappedBase->ToInteger();
-
-		if (memoryMappedAddrMul != NULL &&
-		    memoryMappedAddrMul->ToInteger() != 1)
-			ss << ", addrmul " << memoryMappedAddrMul->ToInteger();
-	}
-
-	return ss.str();
-}
-
diff -Nru gxemul-0.6.2/src/components/memory/RAMComponent.cc gxemul-0.7.0+dfsg/src/components/memory/RAMComponent.cc
--- gxemul-0.6.2/src/components/memory/RAMComponent.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/memory/RAMComponent.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,664 +0,0 @@
-/*
- *  Copyright (C) 2008-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <iomanip>
-#include <assert.h>
-#include <sys/mman.h>
-
-#include "components/RAMComponent.h"
-#include "GXemul.h"
-
-
-RAMComponent::RAMComponent(const string& visibleClassName)
-	: MemoryMappedComponent("ram", visibleClassName)
-	, m_blockSizeShift(22)		// 22 = 4 MB per block
-	, m_blockSize(1 << m_blockSizeShift)
-	, m_dataHandler(*this)
-	, m_writeProtected(false)
-	, m_lastDumpAddr(0)
-	, m_addressSelect(0)
-	, m_selectedHostMemoryBlock(NULL)
-	, m_selectedOffsetWithinBlock(0)
-{
-	AddVariable("writeProtect", &m_writeProtected);
-	AddVariable("lastDumpAddr", &m_lastDumpAddr);
-	AddCustomVariable("data", &m_dataHandler);
-}
-
-
-RAMComponent::~RAMComponent()
-{
-	ReleaseAllBlocks();
-}
-
-
-void RAMComponent::ReleaseAllBlocks()
-{
-	for (size_t i=0; i<m_memoryBlocks.size(); ++i) {
-		if (m_memoryBlocks[i] != NULL) {
-			munmap(m_memoryBlocks[i], m_blockSize);
-			m_memoryBlocks[i] = NULL;
-		}
-	}
-}
-
-
-refcount_ptr<Component> RAMComponent::Create(const ComponentCreateArgs& args)
-{
-	return new RAMComponent();
-}
-
-
-string RAMComponent::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "description")
-		return "A generic RAM component.";
-
-	return MemoryMappedComponent::GetAttribute(attributeName);
-}
-
-
-void RAMComponent::ResetState()
-{
-	ReleaseAllBlocks();
-}
-
-
-void RAMComponent::GetMethodNames(vector<string>& names) const
-{
-	// Add our method names...
-	names.push_back("dump");
-
-	// ... and make sure to call the base class implementation:
-	Component::GetMethodNames(names);
-}
-
-
-bool RAMComponent::MethodMayBeReexecutedWithoutArgs(const string& methodName) const
-{
-	if (methodName == "dump")
-		return true;
-
-	// ... and make sure to call the base class implementation:
-	return Component::MethodMayBeReexecutedWithoutArgs(methodName);
-}
-
-
-void RAMComponent::ExecuteMethod(GXemul* gxemul, const string& methodName,
-	const vector<string>& arguments)
-{
-	if (methodName == "dump") {
-		uint64_t vaddr = m_lastDumpAddr;
-
-		if (arguments.size() > 1) {
-			gxemul->GetUI()->ShowDebugMessage("syntax: .dump [addr]\n");
-			return;
-		}
-
-		if (arguments.size() == 1) {
-			gxemul->GetUI()->ShowDebugMessage("TODO: parse address expression\n");
-			gxemul->GetUI()->ShowDebugMessage("(for now, only hex immediate values are supported!)\n");
-
-			stringstream ss;
-			ss << arguments[0];
-			ss.flags(std::ios::hex);
-			ss >> vaddr;
-		}
-
-		const int nRows = 16;
-		for (int i=0; i<nRows; i++) {
-			const size_t len = 16;
-			unsigned char data[len];
-			bool readable[len];
-
-			stringstream ss;
-			ss.flags(std::ios::hex);
-
-			if (vaddr > 0xffffffff)
-				ss << std::setw(16);
-			else
-				ss << std::setw(8);
-
-			ss << std::setfill('0') << vaddr;
-
-			size_t k;
-			for (k=0; k<len; ++k) {
-				AddressSelect(vaddr + k);
-				readable[k] = ReadData(data[k], BigEndian);
-			}
-			
-			ss << " ";
-			
-			for (k=0; k<len; ++k) {
-				if ((k&3) == 0)
-					ss << " ";
-
-				ss << std::setw(2) << std::setfill('0');
-				if (readable[k])
-					ss << (int)data[k];
-				else
-					ss << "--";
-			}
-
-			ss << "  ";
-
-			for (k=0; k<len; ++k) {
-				char s[2];
-				s[0] = data[k] >= 32 && data[k] < 127? data[k] : '.';
-				s[1] = '\0';
-				
-				if (readable[k])
-					ss << s;
-				else
-					ss << "-";
-			}
-			
-			ss << "\n";
-
-			gxemul->GetUI()->ShowDebugMessage(ss.str());
-
-			vaddr += len;
-		}
-
-		m_lastDumpAddr = vaddr;
-
-		return;
-	}
-
-	// Call base...
-	Component::ExecuteMethod(gxemul, methodName, arguments);
-}
-
-
-AddressDataBus* RAMComponent::AsAddressDataBus()
-{
-	return this;
-}
-
-
-void RAMComponent::AddressSelect(uint64_t address)
-{
-	m_addressSelect = address;
-
-	uint64_t blockNr = address >> m_blockSizeShift;
-
-	if (blockNr+1 > m_memoryBlocks.size())
-		m_selectedHostMemoryBlock = NULL;
-	else
-		m_selectedHostMemoryBlock = m_memoryBlocks[blockNr];
-
-	m_selectedOffsetWithinBlock = address & (m_blockSize-1);
-}
-
-
-void* RAMComponent::AllocateBlock()
-{
-	void * p = mmap(NULL, m_blockSize, PROT_WRITE | PROT_READ,
-	    MAP_ANON | MAP_PRIVATE, -1, 0);
-
-	if (p == MAP_FAILED || p == NULL) {
-		std::cerr << "RAMComponent::AllocateBlock: Could not allocate "
-		    << m_blockSize << " bytes. Aborting.\n";
-		throw std::exception();
-	}
-
-	uint64_t blockNr = m_addressSelect >> m_blockSizeShift;
-
-	if (blockNr+1 > m_memoryBlocks.size())
-		m_memoryBlocks.resize(blockNr + 1);
-
-	m_memoryBlocks[blockNr] = p;
-
-	return p;
-}
-
-
-bool RAMComponent::ReadData(uint8_t& data, Endianness endianness)
-{
-	if (m_selectedHostMemoryBlock == NULL)
-		data = 0;
-	else
-		data = (((uint8_t*)m_selectedHostMemoryBlock)
-		    [m_selectedOffsetWithinBlock]);
-
-	return true;
-}
-
-
-bool RAMComponent::ReadData(uint16_t& data, Endianness endianness)
-{
-	assert((m_addressSelect & 1) == 0);
-
-	if (m_selectedHostMemoryBlock == NULL)
-		data = 0;
-	else
-		data = (((uint16_t*)m_selectedHostMemoryBlock)
-		    [m_selectedOffsetWithinBlock >> 1]);
-
-	if (endianness == BigEndian)
-		data = BE16_TO_HOST(data);
-	else
-		data = LE16_TO_HOST(data);
-
-	return true;
-}
-
-
-bool RAMComponent::ReadData(uint32_t& data, Endianness endianness)
-{
-	assert((m_addressSelect & 3) == 0);
-
-	if (m_selectedHostMemoryBlock == NULL)
-		data = 0;
-	else
-		data = (((uint32_t*)m_selectedHostMemoryBlock)
-		    [m_selectedOffsetWithinBlock >> 2]);
-
-	if (endianness == BigEndian)
-		data = BE32_TO_HOST(data);
-	else
-		data = LE32_TO_HOST(data);
-
-	return true;
-}
-
-
-bool RAMComponent::ReadData(uint64_t& data, Endianness endianness)
-{
-	assert((m_addressSelect & 7) == 0);
-
-	if (m_selectedHostMemoryBlock == NULL)
-		data = 0;
-	else
-		data = (((uint64_t*)m_selectedHostMemoryBlock)
-		    [m_selectedOffsetWithinBlock >> 3]);
-
-	if (endianness == BigEndian)
-		data = BE64_TO_HOST(data);
-	else
-		data = LE64_TO_HOST(data);
-
-	return true;
-}
-
-
-bool RAMComponent::WriteData(const uint8_t& data, Endianness endianness)
-{
-	if (m_writeProtected)
-		return false;
-
-	if (m_selectedHostMemoryBlock == NULL)
-		m_selectedHostMemoryBlock = AllocateBlock();
-
-	(((uint8_t*)m_selectedHostMemoryBlock)
-	    [m_selectedOffsetWithinBlock]) = data;
-
-	return true;
-}
-
-
-bool RAMComponent::WriteData(const uint16_t& data, Endianness endianness)
-{
-	assert((m_addressSelect & 1) == 0);
-
-	if (m_writeProtected)
-		return false;
-
-	if (m_selectedHostMemoryBlock == NULL)
-		m_selectedHostMemoryBlock = AllocateBlock();
-
-	uint16_t d;
-	if (endianness == BigEndian)
-		d = BE16_TO_HOST(data);
-	else
-		d = LE16_TO_HOST(data);
-
-	(((uint16_t*)m_selectedHostMemoryBlock)
-	    [m_selectedOffsetWithinBlock >> 1]) = d;
-
-	return true;
-}
-
-
-bool RAMComponent::WriteData(const uint32_t& data, Endianness endianness)
-{
-	assert((m_addressSelect & 3) == 0);
-
-	if (m_writeProtected)
-		return false;
-
-	if (m_selectedHostMemoryBlock == NULL)
-		m_selectedHostMemoryBlock = AllocateBlock();
-
-	uint32_t d;
-	if (endianness == BigEndian)
-		d = BE32_TO_HOST(data);
-	else
-		d = LE32_TO_HOST(data);
-
-	(((uint32_t*)m_selectedHostMemoryBlock)
-	    [m_selectedOffsetWithinBlock >> 2]) = d;
-
-	return true;
-}
-
-
-bool RAMComponent::WriteData(const uint64_t& data, Endianness endianness)
-{
-	assert((m_addressSelect & 7) == 0);
-
-	if (m_writeProtected)
-		return false;
-
-	if (m_selectedHostMemoryBlock == NULL)
-		m_selectedHostMemoryBlock = AllocateBlock();
-
-	uint64_t d;
-	if (endianness == BigEndian)
-		d = BE64_TO_HOST(data);
-	else
-		d = LE64_TO_HOST(data);
-
-	(((uint64_t*)m_selectedHostMemoryBlock)
-	    [m_selectedOffsetWithinBlock >> 3]) = d;
-
-	return true;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_RAMComponent_AddressDataBus()
-{
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-
-	AddressDataBus* bus = ram->AsAddressDataBus();
-	UnitTest::Assert("The RAMComponent should implement the "
-	    "AddressDataBus interface", bus != NULL);
-}
-
-static void Test_RAMComponent_InitiallyZero()
-{
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-	AddressDataBus* bus = ram->AsAddressDataBus();
-
-	bus->AddressSelect(0);
-
-	// By default, RAM should be zero-filled:
-	uint8_t data8 = 42;
-	bus->ReadData(data8);
-	UnitTest::Assert("A: memory should be zero filled (8)", data8, 0);
-
-	uint16_t data16 = 142;
-	bus->ReadData(data16, BigEndian);
-	UnitTest::Assert("A: memory should be zero filled (16)", data16, 0);
-
-	uint32_t data32 = 342;
-	bus->ReadData(data32, BigEndian);
-	UnitTest::Assert("A: memory should be zero filled (32)", data32, 0);
-
-	uint64_t data64 = 942;
-	bus->ReadData(data64, BigEndian);
-	UnitTest::Assert("A: memory should be zero filled (64)", data64, 0);
-
-	bus->AddressSelect(0x10000);
-
-	data8 = 43;
-	bus->ReadData(data8);
-	UnitTest::Assert("B: memory should be zero filled (8)", data8, 0);
-
-	data16 = 143;
-	bus->ReadData(data16, BigEndian);
-	UnitTest::Assert("B: memory should be zero filled (16)", data16, 0);
-
-	data32 = 343;
-	bus->ReadData(data32, BigEndian);
-	UnitTest::Assert("B: memory should be zero filled (32)", data32, 0);
-
-	data64 = 943;
-	bus->ReadData(data64, BigEndian);
-	UnitTest::Assert("B: memory should be zero filled (64)", data64, 0);
-}
-
-static void Test_RAMComponent_WriteThenRead()
-{
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-	AddressDataBus* bus = ram->AsAddressDataBus();
-
-	bus->AddressSelect(256);
-
-	uint64_t data64 = ((uint64_t)0x1234567 << 32) | 0x89abcdef;
-	bus->WriteData(data64, BigEndian);
-
-	uint64_t data64_b = 0;
-	bus->ReadData(data64_b, BigEndian);
-
-	UnitTest::Assert("memory should be same when read", data64_b, data64);
-
-	uint32_t data32_b = 0;
-	bus->ReadData(data32_b, BigEndian);
-
-	UnitTest::Assert("32-bit read should give top 32 bits, "
-	    "in big endian mode", data32_b, data64 >> 32);
-
-	uint16_t data16_b = 0;
-	bus->ReadData(data16_b, BigEndian);
-
-	UnitTest::Assert("16-bit read should give top 16 bits, "
-	    "in big endian mode", data16_b, data64 >> 48);
-
-	uint8_t data8_b = 0;
-	bus->ReadData(data8_b);
-
-	UnitTest::Assert("8-bit read should give top 8 bits, "
-	    "in big endian mode", data8_b, data64 >> 56);
-}
-
-static void Test_RAMComponent_WriteThenRead_ReverseEndianness()
-{
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-	AddressDataBus* bus = ram->AsAddressDataBus();
-
-	bus->AddressSelect(256);
-
-	uint64_t data64 = ((uint64_t)0x1234567 << 32) | 0x89abcdef;
-	bus->WriteData(data64, BigEndian);
-
-	bus->AddressSelect(256 + 4);
-
-	uint32_t data32_b = 0;
-	bus->ReadData(data32_b, LittleEndian);
-
-	UnitTest::Assert("32-bit read", data32_b, 0xefcdab89);
-
-	uint16_t data16_b = 0;
-	bus->ReadData(data16_b, LittleEndian);
-
-	UnitTest::Assert("16-bit read", data16_b, 0xab89);
-
-	uint8_t data8_b = 0;
-	bus->ReadData(data8_b);
-
-	UnitTest::Assert("8-bit read", data8_b, 0x89);
-}
-
-static void Test_RAMComponent_WriteProtect()
-{
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-	AddressDataBus* bus = ram->AsAddressDataBus();
-
-	uint32_t data32 = 0x89abcdef;
-	bus->AddressSelect(256);
-	UnitTest::Assert("non-writeprotected write should succeed",
-	    bus->WriteData(data32, BigEndian));
-
-	uint16_t data16_a = 0;
-	bus->AddressSelect(256 + 2);
-	bus->ReadData(data16_a, BigEndian);
-	UnitTest::Assert("16-bit read", data16_a, 0xcdef);
-
-	ram->SetVariableValue("writeProtect", "true");
-
-	data32 = 0x11223344;
-	bus->AddressSelect(256);
-	UnitTest::Assert("writeprotected write should fail",
-	    bus->WriteData(data32, BigEndian) == false);
-
-	data16_a = 0;
-	bus->AddressSelect(256 + 2);
-	bus->ReadData(data16_a, BigEndian);
-	UnitTest::Assert("16-bit read", data16_a, 0xcdef);
-
-	ram->SetVariableValue("writeProtect", "false");
-
-	data32 = 0x12345678;
-	bus->AddressSelect(256);
-	UnitTest::Assert("write should succeed again",
-	    bus->WriteData(data32, BigEndian));
-
-	data16_a = 0;
-	bus->AddressSelect(256 + 2);
-	bus->ReadData(data16_a, BigEndian);
-	UnitTest::Assert("16-bit read", data16_a, 0x5678);
-}
-
-static void Test_RAMComponent_ClearOnReset()
-{
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-	AddressDataBus* bus = ram->AsAddressDataBus();
-
-	uint32_t data32 = 0x89abcdef;
-	bus->AddressSelect(256);
-	bus->WriteData(data32, BigEndian);
-
-	uint16_t data16_a = 0;
-	bus->AddressSelect(256 + 2);
-	bus->ReadData(data16_a, BigEndian);
-	UnitTest::Assert("16-bit read", data16_a, 0xcdef);
-
-	ram->Reset();
-
-	uint16_t data16_b = 0;
-	bus->AddressSelect(256 + 2);
-	bus->ReadData(data16_b, BigEndian);
-	UnitTest::Assert("reset should have cleared RAM", data16_b, 0x0000);
-}
-
-static void Test_RAMComponent_Clone()
-{
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-	AddressDataBus* bus = ram->AsAddressDataBus();
-
-	uint32_t data32 = 0x89abcdef;
-	bus->AddressSelect(4);
-	bus->WriteData(data32, BigEndian);
-
-	uint16_t data16_a = 0x1234;
-	bus->AddressSelect(10);
-	bus->WriteData(data16_a, LittleEndian);
-
-	UnitTest::Assert("serialization/deserialization failed?", ram->CheckConsistency());
-
-	refcount_ptr<Component> clone = ram->Clone();
-	bus = clone->AsAddressDataBus();
-
-	data32 = 0x22222222;
-	bus->AddressSelect(4);
-	bus->ReadData(data32, LittleEndian);
-	UnitTest::Assert("32-bit read", data32, 0xefcdab89);
-
-	data16_a = 0xffff;
-	bus->AddressSelect(10);
-	bus->ReadData(data16_a, BigEndian);
-	UnitTest::Assert("16-bit read", data16_a, 0x3412);
-}
-
-static void Test_RAMComponent_ManualSerialization()
-{
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-	AddressDataBus* bus = ram->AsAddressDataBus();
-
-	uint32_t data32 = 0x89abcde5;
-	bus->AddressSelect(4);
-	bus->WriteData(data32, BigEndian);
-
-	uint16_t data16_a = 0x1235;
-	bus->AddressSelect(10);
-	bus->WriteData(data16_a, LittleEndian);
-
-	SerializationContext context;
-	stringstream ss;
-	ram->Serialize(ss, context);
-
-	string result = ss.str();
-	size_t pos = 0;
-	stringstream messages;
-	refcount_ptr<Component> ram2 = Component::Deserialize(messages, result, pos);
-	bus = ram2->AsAddressDataBus();
-
-	data32 = 0x22222222;
-	bus->AddressSelect(4);
-	bus->ReadData(data32, LittleEndian);
-	UnitTest::Assert("32-bit read", data32, 0xe5cdab89);
-
-	data16_a = 0xffff;
-	bus->AddressSelect(10);
-	bus->ReadData(data16_a, BigEndian);
-	UnitTest::Assert("16-bit read", data16_a, 0x3512);
-}
-
-static void Test_RAMComponent_Methods_Reexecutableness()
-{
-	refcount_ptr<Component> ram = ComponentFactory::CreateComponent("ram");
-
-	UnitTest::Assert("dump method SHOULD be re-executable"
-	    " without args", ram->MethodMayBeReexecutedWithoutArgs("dump") == true);
-
-	UnitTest::Assert("nonexistant method should NOT be re-executable"
-	    " without args", ram->MethodMayBeReexecutedWithoutArgs("nonexistant") == false);
-}
-
-UNITTESTS(RAMComponent)
-{
-	UNITTEST(Test_RAMComponent_AddressDataBus);
-	UNITTEST(Test_RAMComponent_InitiallyZero);
-	UNITTEST(Test_RAMComponent_WriteThenRead);
-	UNITTEST(Test_RAMComponent_WriteThenRead_ReverseEndianness);
-	UNITTEST(Test_RAMComponent_WriteProtect);
-	UNITTEST(Test_RAMComponent_ClearOnReset);
-	UNITTEST(Test_RAMComponent_Clone);
-	UNITTEST(Test_RAMComponent_ManualSerialization);
-	UNITTEST(Test_RAMComponent_Methods_Reexecutableness);
-}
-
-#endif
-
diff -Nru gxemul-0.6.2/src/components/README gxemul-0.7.0+dfsg/src/components/README
--- gxemul-0.6.2/src/components/README	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/README	1970-01-01 00:00:00.000000000 +0000
@@ -1,19 +0,0 @@
-How to add a new component:
----------------------------
-
-Assuming you want to implement a FooComponent class:
-
-1. Copy a reasonably similar component's .cc file, e.g.
-   M88K_CPUComponent.cc, to FooComponent.cc.
-
-2. Copy M88K_CPUComponent.h to FooComponent.h.
-
-3. Substitute all occurances of M88K_CPUComponent with
-   FooComponent in the .cc and .h files.
-
-4. Edit Makefile.skel to include FooComponent.o among the
-   OBJS to build.
-
-Then run   make clean_all   and   ./configure && make test
-
-Now you can modify the new component to suit your needs.
diff -Nru gxemul-0.6.2/src/components/special/DummyComponent.cc gxemul-0.7.0+dfsg/src/components/special/DummyComponent.cc
--- gxemul-0.6.2/src/components/special/DummyComponent.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/special/DummyComponent.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1188 +0,0 @@
-/*
- *  Copyright (C) 2007-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "components/DummyComponent.h"
-#include "Checksum.h"
-#include "ComponentFactory.h"
-
-
-DummyComponent::DummyComponent(string className)
-	: Component(className, className)
-{
-	// The dummy component should have no additional state.
-}
-
-
-refcount_ptr<Component> DummyComponent::Create(const ComponentCreateArgs& args)
-{
-	return new DummyComponent();
-}
-
-
-string DummyComponent::GetAttribute(const string& attributeName)
-{
-	if (attributeName == "description")
-		return "A dummy component, which does nothing.";
-
-	return Component::GetAttribute(attributeName);
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "GXemul.h"
-
-static void Test_DummyComponent_CreateComponent()
-{
-	refcount_ptr<Component> component;
-
-	component = ComponentFactory::CreateComponent("dummy");
-	UnitTest::Assert("creating a dummy component should be possible",
-	    component.IsNULL() == false);
-
-	UnitTest::Assert("the name should be 'dummy'",
-	    component->GetClassName() == "dummy");
-}
-
-static void Test_DummyComponent_GetSetParent()
-{
-	refcount_ptr<Component> dummyA = new DummyComponent;
-	refcount_ptr<Component> dummyB = new DummyComponent;
-
-	UnitTest::Assert("parent should initially be NULL",
-	    dummyA->GetParent() == NULL);
-
-	dummyA->SetParent(dummyB);
-
-	UnitTest::Assert("parent should be dummyB",
-	    dummyA->GetParent() == dummyB);
-
-	dummyA->SetParent(NULL);
-
-	UnitTest::Assert("parent should now be NULL",
-	    dummyA->GetParent() == NULL);
-}
-
-static void Test_DummyComponent_AddChild_Sets_Parent()
-{
-	refcount_ptr<Component> dummy = new DummyComponent;
-	refcount_ptr<Component> dummyChildA = new DummyComponent;
-
-	UnitTest::Assert("child A's parent should initially be NULL",
-	    dummyChildA->GetParent() == NULL);
-
-	dummy->AddChild(dummyChildA);
-
-	UnitTest::Assert("child A's parent should now be dummy",
-	    dummyChildA->GetParent() == dummy);
-}
-
-static void Test_DummyComponent_AddChildren_Count()
-{
-	refcount_ptr<Component> dummy = new DummyComponent;
-	refcount_ptr<Component> dummyChildA = new DummyComponent;
-	refcount_ptr<Component> dummyChildB = new DummyComponent;
-	refcount_ptr<Component> dummyChildC = new DummyComponent;
-
-	UnitTest::Assert("there should initially be no child components",
-	    dummy->GetChildren().size() == 0);
-
-	dummy->AddChild(dummyChildA);
-	dummy->AddChild(dummyChildB);
-	dummy->AddChild(dummyChildC);
-
-	UnitTest::Assert("there should be 3 child components",
-	    dummy->GetChildren().size() == 3);
-}
-
-static void Test_DummyComponent_Add_Tree_Of_Children()
-{
-	refcount_ptr<Component> dummy = new DummyComponent;
-	refcount_ptr<Component> dummyChildA = new DummyComponent;
-	refcount_ptr<Component> dummyChildB = new DummyComponent;
-	refcount_ptr<Component> dummyChildC = new DummyComponent;
-
-	dummyChildA->AddChild(dummyChildB);
-	dummyChildA->AddChild(dummyChildC);
-	dummy->AddChild(dummyChildA);
-
-	UnitTest::Assert("there should be 1 child component",
-	    dummy->GetChildren().size() == 1);
-	UnitTest::Assert("there should be 2 child components in dummyChildA",
-	    dummyChildA->GetChildren().size() == 2);
-}
-
-static void Test_DummyComponent_RemoveChild()
-{
-	refcount_ptr<Component> dummy = new DummyComponent;
-	refcount_ptr<Component> dummyChildA = new DummyComponent;
-	refcount_ptr<Component> dummyChildB = new DummyComponent;
-	refcount_ptr<Component> dummyChildC = new DummyComponent;
-
-	dummyChildA->AddChild(dummyChildB);
-	dummyChildA->AddChild(dummyChildC);
-	dummy->AddChild(dummyChildA);
-
-	UnitTest::Assert("there should be 1 child component",
-	    dummy->GetChildren().size() == 1);
-	UnitTest::Assert("child A's parent should be dummy",
-	    dummyChildA->GetParent() == dummy);
-	UnitTest::Assert("there should be 2 child components in dummyChildA",
-	    dummyChildA->GetChildren().size() == 2);
-
-	dummy->RemoveChild(dummyChildA);
-
-	UnitTest::Assert("there should now be 0 child components",
-	    dummy->GetChildren().size() == 0);
-
-	UnitTest::Assert(
-	    "there should still be 2 child components in dummyChildA",
-	    dummyChildA->GetChildren().size() == 2);
-	UnitTest::Assert("child A should have no parent",
-	    dummyChildA->GetParent() == NULL);
-}
-
-static void Test_DummyComponent_AddChild_UniqueName()
-{
-	refcount_ptr<Component> dummy = new DummyComponent;
-	refcount_ptr<Component> dummyChildA = new DummyComponent;
-	refcount_ptr<Component> dummyChildB = new DummyComponent;
-	refcount_ptr<Component> dummyChildC = new DummyComponent;
-
-	UnitTest::Assert("dummyChildA should have no initial name",
-	    dummyChildA->GetVariable("name")->ToString(), "");
-
-	dummy->AddChild(dummyChildA);
-
-	const StateVariable* name = dummyChildA->GetVariable("name");
-	UnitTest::Assert("dummyChildA's name mismatch",
-	    name->ToString(), "dummy0");
-
-	dummy->AddChild(dummyChildB);
-
-	name = dummyChildA->GetVariable("name");
-	UnitTest::Assert("dummyChildA should still have a name",
-	    name != NULL);
-	UnitTest::Assert("dummyChildA's name changed unexpectedly?",
-	    name->ToString(), "dummy0");
-
-	name = dummyChildB->GetVariable("name");
-	UnitTest::Assert("dummyChildB should have a name now",
-	    name != NULL);
-	UnitTest::Assert("dummyChildB's name mismatch",
-	    name->ToString(), "dummy1");
-
-	dummy->AddChild(dummyChildC);
-
-	name = dummyChildC->GetVariable("name");
-	UnitTest::Assert("dummyChildC should have a name now",
-	    name != NULL);
-	UnitTest::Assert("dummyChildC's name mismatch",
-	    name->ToString(), "dummy2");
-
-	dummy->RemoveChild(dummyChildA);
-
-	name = dummyChildB->GetVariable("name");
-	UnitTest::Assert("dummyChildB should still have a name, after"
-		" removing child A",
-	    name != NULL);
-	UnitTest::Assert("dummyChildB's should not have changed",
-	    name->ToString(), "dummy1");
-}
-
-static void Test_DummyComponent_GeneratePath()
-{
-	refcount_ptr<Component> dummyA = new DummyComponent;
-	refcount_ptr<Component> dummyB = new DummyComponent;
-	refcount_ptr<Component> dummyC = new DummyComponent;
-
-	UnitTest::Assert("generated path with no name",
-	    dummyA->GeneratePath(), "(dummy)");
-
-	dummyB->AddChild(dummyA);
-
-	UnitTest::Assert("generated path with default name fallback",
-	    dummyA->GeneratePath(), "(dummy).dummy0");
-
-	dummyC->AddChild(dummyB);
-
-	UnitTest::Assert("generated path with two parent levels",
-	    dummyA->GeneratePath(), "(dummy).dummy0.dummy0");
-
-	dummyC->RemoveChild(dummyB);
-
-	UnitTest::Assert("generated path with one parent level again",
-	    dummyA->GeneratePath(), "dummy0.dummy0");
-}
-
-static void Test_DummyComponent_GenerateShortestPossiblePath()
-{
-	refcount_ptr<Component> dummyA = new DummyComponent;
-	refcount_ptr<Component> dummyB = new DummyComponent;
-	refcount_ptr<Component> dummyC = new DummyComponent;
-
-	dummyA->SetVariableValue("name", "\"machine0\"");
-	dummyB->SetVariableValue("name", "\"mainbus0\"");
-	dummyC->SetVariableValue("name", "\"ram0\"");
-	dummyA->AddChild(dummyB);
-	dummyB->AddChild(dummyC);
-
-	UnitTest::Assert("shortest path first",
-	    dummyC->GenerateShortestPossiblePath(), "ram0");
-
-	refcount_ptr<Component> dummyB2 = new DummyComponent;
-	refcount_ptr<Component> dummyC2 = new DummyComponent;
-	dummyB2->SetVariableValue("name", "\"mainbus1\"");
-	dummyC2->SetVariableValue("name", "\"ram0\"");
-	dummyA->AddChild(dummyB2);
-	dummyB2->AddChild(dummyC2);
-
-	UnitTest::Assert("shortest path C",
-	    dummyC->GenerateShortestPossiblePath(), "mainbus0.ram0");
-	UnitTest::Assert("shortest path C2",
-	    dummyC2->GenerateShortestPossiblePath(), "mainbus1.ram0");
-}
-
-static void Test_DummyComponent_LookupPath()
-{
-	refcount_ptr<Component> dummyA = new DummyComponent;
-
-	dummyA->SetVariableValue("name", "\"hello\"");
-
-	refcount_ptr<Component> component1 = dummyA->LookupPath("nonsense");
-	UnitTest::Assert("nonsense lookup should fail",
-	    component1.IsNULL() == true);
-
-	refcount_ptr<Component> component2 = dummyA->LookupPath("hello");
-	UnitTest::Assert("lookup should have found the component itself",
-	    component2 == dummyA);
-
-	refcount_ptr<Component> child = new DummyComponent;
-	refcount_ptr<Component> childchild = new DummyComponent;
-	child->SetVariableValue("name", "\"x\"");
-	childchild->SetVariableValue("name", "\"y\"");
-	dummyA->AddChild(child);
-	child->AddChild(childchild);
-
-	refcount_ptr<Component> component3 = dummyA->LookupPath("hello");
-	UnitTest::Assert("lookup should still succeed, when dummyA has"
-		" children",
-	    component3 == dummyA);
-
-	refcount_ptr<Component> component4 = dummyA->LookupPath("hello.z");
-	UnitTest::Assert("lookup of nonsense child of dummyA should fail",
-	    component4.IsNULL() == true);
-
-	refcount_ptr<Component> component5 = dummyA->LookupPath("hello.x");
-	UnitTest::Assert("lookup of child of dummyA should succeed",
-	    component5 == child);
-
-	refcount_ptr<Component> component6 = dummyA->LookupPath("hello.x.y");
-	UnitTest::Assert("lookup of grandchild of dummyA should succeed",
-	    component6 == childchild);
-}
-
-static void Test_DummyComponent_FindPathByPartialMatch()
-{
-	refcount_ptr<Component> root = new DummyComponent;
-	refcount_ptr<Component> machine0 = new DummyComponent;
-	refcount_ptr<Component> machine1 = new DummyComponent;
-	refcount_ptr<Component> machine2 = new DummyComponent;
-	refcount_ptr<Component> machine3 = new DummyComponent;
-	refcount_ptr<Component> m0isabus0 = new DummyComponent;
-	refcount_ptr<Component> m1pcibus0 = new DummyComponent;
-	refcount_ptr<Component> m1pcibus1 = new DummyComponent;
-	refcount_ptr<Component> m2pcibus0 = new DummyComponent;
-	refcount_ptr<Component> m3otherpci = new DummyComponent;
-
-	root->GetVariable("name")->SetValue("\"root\"");
-	machine0->GetVariable("name")->SetValue("\"machine0\"");
-	machine1->GetVariable("name")->SetValue("\"machine1\"");
-	machine2->GetVariable("name")->SetValue("\"machine2\"");
-	machine3->GetVariable("name")->SetValue("\"machine3\"");
-	m0isabus0->GetVariable("name")->SetValue("\"isabus0\"");
-	m1pcibus0->GetVariable("name")->SetValue("\"pcibus0\"");
-	m1pcibus1->GetVariable("name")->SetValue("\"pcibus1\"");
-	m2pcibus0->GetVariable("name")->SetValue("\"pcibus0\"");
-	m3otherpci->GetVariable("name")->SetValue("\"otherpci\"");
-
-	root->AddChild(machine0);
-	root->AddChild(machine1);
-	root->AddChild(machine2);
-	root->AddChild(machine3);
-
-	machine0->AddChild(m0isabus0);
-	machine1->AddChild(m1pcibus0);
-	machine1->AddChild(m1pcibus1);
-	machine2->AddChild(m2pcibus0);
-	machine3->AddChild(m3otherpci);
-
-	vector<string> matches;
-
-	matches = root->FindPathByPartialMatch("nonsense");
-	UnitTest::Assert("there should be no nonsense matches",
-	    matches.size(), 0);
-	
-	matches = root->FindPathByPartialMatch("");
-	UnitTest::Assert("empty string should return all components",
-	    matches.size(), 10);
-
-	matches = root->FindPathByPartialMatch("pci");
-	UnitTest::Assert("pci matches mismatch",
-	    matches.size(), 3);
-	UnitTest::Assert("pci match 0 mismatch",
-	    matches[0], "root.machine1.pcibus0");
-	UnitTest::Assert("pci match 1 mismatch",
-	    matches[1], "root.machine1.pcibus1");
-	UnitTest::Assert("pci match 2 mismatch",
-	    matches[2], "root.machine2.pcibus0");
-
-	matches = root->FindPathByPartialMatch("machine1");
-	UnitTest::Assert("machine1 match mismatch",
-	    matches.size(), 1);
-	UnitTest::Assert("machine1 match 0 mismatch",
-	    matches[0], "root.machine1");
-
-	matches = root->FindPathByPartialMatch("machine2.pcibus");
-	UnitTest::Assert("machine2.pcibus match mismatch",
-	    matches.size(), 1);
-	UnitTest::Assert("machine2.pcibus match 0 mismatch",
-	    matches[0], "root.machine2.pcibus0");
-
-	matches = root->FindPathByPartialMatch("machine.pcibus");
-	UnitTest::Assert("machine.pcibus should have no matches",
-	    matches.size(), 0);
-}
-
-static void Test_DummyComponent_GetUnknownVariable()
-{
-	refcount_ptr<Component> dummy = new DummyComponent;
-
-	UnitTest::Assert("variable variablename should not be set",
-	    dummy->GetVariable("variablename") == NULL);
-}
-
-static void Test_DummyComponent_NonexistantMethodNotReexecutable()
-{
-	refcount_ptr<Component> dummy = new DummyComponent;
-
-	UnitTest::Assert("by default, methods should NOT be re-executable"
-	    " without args",
-	    dummy->MethodMayBeReexecutedWithoutArgs("nonexistant") == false);
-}
-
-static void Test_DummyComponent_Clone_Basic()
-{
-	refcount_ptr<Component> dummy = new DummyComponent;
-	refcount_ptr<Component> dummyChildA = new DummyComponent;
-	refcount_ptr<Component> dummyChildA1 = new DummyComponent;
-	refcount_ptr<Component> dummyChildA2 = new DummyComponent;
-
-	dummyChildA->AddChild(dummyChildA1);
-	dummyChildA->AddChild(dummyChildA2);
-	dummy->AddChild(dummyChildA);
-
-	Checksum originalChecksum;
-	dummy->AddChecksum(originalChecksum);
-
-	refcount_ptr<Component> clone = dummy->Clone();
-
-	Checksum cloneChecksum;
-	clone->AddChecksum(cloneChecksum);
-
-	UnitTest::Assert("clone should have same checksum",
-	    originalChecksum == cloneChecksum);
-
-	dummy->SetVariableValue("name", "\"modified\"");
-
-	Checksum originalChecksumAfterModifyingOriginal;
-	dummy->AddChecksum(originalChecksumAfterModifyingOriginal);
-	Checksum cloneChecksumAfterModifyingOriginal;
-	clone->AddChecksum(cloneChecksumAfterModifyingOriginal);
-
-	UnitTest::Assert("original should have changed checksum",
-	    originalChecksum != originalChecksumAfterModifyingOriginal);
-	UnitTest::Assert("clone should have same checksum",
-	    cloneChecksum == cloneChecksumAfterModifyingOriginal);
-
-	clone->SetVariableValue("name", "\"modified\"");
-
-	Checksum originalChecksumAfterModifyingClone;
-	dummy->AddChecksum(originalChecksumAfterModifyingClone);
-	Checksum cloneChecksumAfterModifyingClone;
-	clone->AddChecksum(cloneChecksumAfterModifyingClone);
-
-	UnitTest::Assert("original should have same checksum, after the "
-		"clone has been modified",
-	    originalChecksumAfterModifyingClone ==
-	    originalChecksumAfterModifyingOriginal);
-	UnitTest::Assert("modified clone should have same checksum as "
-		"modified original",
-	    cloneChecksumAfterModifyingClone ==
-	    originalChecksumAfterModifyingOriginal);
-}
-
-class DummyComponentWithAllVariableTypes
-	: public DummyComponent
-{
-public:
-	DummyComponentWithAllVariableTypes()
-		: DummyComponent("dummy2")
-	{
-		AddVariable("m_string", &m_string);
-		AddVariable("m_uint8",  &m_uint8);
-		AddVariable("m_uint16", &m_uint16);
-		AddVariable("m_uint32", &m_uint32);
-		AddVariable("m_uint64", &m_uint64);
-		AddVariable("m_sint8",  &m_sint8);
-		AddVariable("m_sint16", &m_sint16);
-		AddVariable("m_sint32", &m_sint32);
-		AddVariable("m_sint64", &m_sint64);
-		// TODO: Custom
-		// TODO: Bool
-
-		ResetState();
-	}
-
-	virtual void ResetState()
-	{
-		DummyComponent::ResetState();
-
-		m_string = "some value";
-		m_uint8 = 123;
-		m_uint16 = 0xf9a2;
-		m_uint32 = 0x98f8aa01;
-		m_uint64 = ((uint64_t)0xf8192929 << 32) | 0x30300a0a;
-		m_sint8 = -123;
-		m_sint16 = -400;
-		m_sint32 = -10000;
-		m_sint64 = -42;
-	}
-
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args)
-	{
-		return new DummyComponentWithAllVariableTypes();
-	}
-
-private:
-	string		m_string;
-	uint8_t		m_uint8;
-	uint16_t	m_uint16;
-	uint32_t	m_uint32;
-	uint64_t	m_uint64;
-	int8_t		m_sint8;
-	int16_t		m_sint16;
-	int32_t		m_sint32;
-	int64_t		m_sint64;
-};
-
-static void Test_DummyComponent_Clone_AllVariableTypes()
-{
-	refcount_ptr<Component> dummy = new DummyComponentWithAllVariableTypes;
-	refcount_ptr<Component> dA = new DummyComponentWithAllVariableTypes;
-	refcount_ptr<Component> dA1 = new DummyComponentWithAllVariableTypes;
-	refcount_ptr<Component> dA2 = new DummyComponentWithAllVariableTypes;
-
-	dA->AddChild(dA1);
-	dA->AddChild(dA2);
-	dummy->AddChild(dA);
-
-	Checksum originalChecksum;
-	dummy->AddChecksum(originalChecksum);
-
-	refcount_ptr<Component> clone = dummy->Clone();
-
-	Checksum cloneChecksum;
-	clone->AddChecksum(cloneChecksum);
-
-	UnitTest::Assert("clone should have same checksum",
-	    originalChecksum == cloneChecksum);
-
-	dummy->SetVariableValue("name", "\"modified\"");
-
-	Checksum originalChecksumAfterModifyingOriginal;
-	dummy->AddChecksum(originalChecksumAfterModifyingOriginal);
-	Checksum cloneChecksumAfterModifyingOriginal;
-	clone->AddChecksum(cloneChecksumAfterModifyingOriginal);
-
-	UnitTest::Assert("original should have changed checksum",
-	    originalChecksum != originalChecksumAfterModifyingOriginal);
-	UnitTest::Assert("clone should have same checksum",
-	    cloneChecksum == cloneChecksumAfterModifyingOriginal);
-
-	clone->SetVariableValue("name", "\"modified\"");
-
-	Checksum originalChecksumAfterModifyingClone;
-	dummy->AddChecksum(originalChecksumAfterModifyingClone);
-	Checksum cloneChecksumAfterModifyingClone;
-	clone->AddChecksum(cloneChecksumAfterModifyingClone);
-
-	UnitTest::Assert("original should have same checksum, after the "
-		"clone has been modified",
-	    originalChecksumAfterModifyingClone ==
-	    originalChecksumAfterModifyingOriginal);
-	UnitTest::Assert("modified clone should have same checksum as "
-		"modified original",
-	    cloneChecksumAfterModifyingClone ==
-	    originalChecksumAfterModifyingOriginal);
-}
-
-static void Test_DummyComponent_SerializeDeserialize()
-{
-	refcount_ptr<Component> dummy = new DummyComponent;
-	refcount_ptr<Component> dummyChildA = new DummyComponent;
-	refcount_ptr<Component> dummyChildA1 = new DummyComponent;
-	refcount_ptr<Component> dummyChildA2 = new DummyComponent;
-
-	dummyChildA->AddChild(dummyChildA1);
-	dummyChildA->AddChild(dummyChildA2);
-	dummy->AddChild(dummyChildA);
-
-	UnitTest::Assert("serialize/deserialize consistency failure",
-	    dummy->CheckConsistency() == true);
-}
-
-class DummyComponentWithCounter
-	: public DummyComponent
-{
-public:
-	DummyComponentWithCounter(ostream* os = NULL, char c = 'X')
-		: DummyComponent("testcounter")
-		, m_frequency(1e6)
-		, m_os(os)
-		, m_c(c)
-	{
-		ResetState();
-		AddVariable("frequency", &m_frequency);
-		AddVariable("counter", &m_counter);
-	}
-
-	virtual void ResetState()
-	{
-		DummyComponent::ResetState();
-		m_counter = 42;
-	}
-
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args)
-	{
-		return new DummyComponentWithCounter();
-	}
-
-	virtual int Execute(GXemul* gxemul, int nrOfCycles)
-	{
-		// Increase counter one per cycle.
-		m_counter += nrOfCycles;
-
-		if (m_os != NULL) {
-			for (int i=0; i<nrOfCycles; ++i)
-				(*m_os) << m_c;
-		}
-
-		return nrOfCycles;
-	}
-
-private:
-	double		m_frequency;
-	uint64_t	m_counter;
-	ostream*	m_os;
-	char		m_c;
-};
-
-static void Test_DummyComponent_Execute_SingleStep()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add testcounter");
-
-	UnitTest::Assert("the testcounter should have been added",
-	    gxemul.GetRootComponent()->GetChildren().size(), 1);
-
-	refcount_ptr<Component> counter = gxemul.GetRootComponent()->GetChildren()[0];
-
-	UnitTest::Assert("the component should be the counter",
-	    counter->GetVariable("name")->ToString(), "testcounter0");
-
-	// Step 0:
-	UnitTest::Assert("the step should initially be 0",
-	    gxemul.GetStep(), 0);
-	UnitTest::Assert("the counter should initially be 42",
-	    counter->GetVariable("counter")->ToInteger(), 42);
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute();
-
-	// Step 1:
-	UnitTest::Assert("runstate wasn't reset after step 0?",
-	    gxemul.GetRunState() == GXemul::Paused);
-	UnitTest::Assert("the step should now be 1", gxemul.GetStep(), 1);
-	UnitTest::Assert("the counter should now be 43",
-	    counter->GetVariable("counter")->ToInteger(), 43);
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute();
-
-	// Step 2:
-	UnitTest::Assert("runstate wasn't reset after step 1?",
-	    gxemul.GetRunState() == GXemul::Paused);
-	UnitTest::Assert("the step should now be 2", gxemul.GetStep(), 2);
-	UnitTest::Assert("the counter should now be 44",
-	    counter->GetVariable("counter")->ToInteger(), 44);
-}
-
-static void Test_DummyComponent_Execute_MultiSingleStep()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add testcounter");
-
-	UnitTest::Assert("the testcounter should have been added",
-	    gxemul.GetRootComponent()->GetChildren().size(), 1);
-
-	refcount_ptr<Component> counter = gxemul.GetRootComponent()->GetChildren()[0];
-
-	UnitTest::Assert("the component should be the counter",
-	    counter->GetVariable("name")->ToString(), "testcounter0");
-
-	const int nrOfStepsToRun = 23;
-	gxemul.SetNrOfSingleStepsInARow(nrOfStepsToRun);
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-
-	// Note: This should execute all nrOfStepsToRun steps, unless there
-	// was some fatal abort condition.
-	gxemul.Execute();
-
-	// Step n:
-	UnitTest::Assert("runstate wasn't reset?",
-	    gxemul.GetRunState() == GXemul::Paused);
-	UnitTest::Assert("the step should now be n", gxemul.GetStep(), nrOfStepsToRun);
-	UnitTest::Assert("the counter should now be 42+nrOfStepsToRun",
-	    counter->GetVariable("counter")->ToInteger(), 42+nrOfStepsToRun);
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute();
-
-	// Step n+1:
-	UnitTest::Assert("runstate wasn't reset after step 1?",
-	    gxemul.GetRunState() == GXemul::Paused);
-	UnitTest::Assert("the step should now be n+1", gxemul.GetStep(), nrOfStepsToRun+1);
-	UnitTest::Assert("the counter should now be 43+nrOfStepsToRun",
-	    counter->GetVariable("counter")->ToInteger(), 43+nrOfStepsToRun);
-}
-
-static void Test_DummyComponent_Execute_TwoComponentsSameSpeed()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add testcounter");
-	gxemul.GetCommandInterpreter().RunCommand("add testcounter");
-
-	UnitTest::Assert("the testcounters should have been added",
-	    gxemul.GetRootComponent()->GetChildren().size(), 2);
-
-	refcount_ptr<Component> counterA = gxemul.GetRootComponent()->GetChildren()[0];
-	refcount_ptr<Component> counterB = gxemul.GetRootComponent()->GetChildren()[1];
-
-	UnitTest::Assert("name A mismatch",
-	    counterA->GetVariable("name")->ToString(), "testcounter0");
-	UnitTest::Assert("name B mismatch",
-	    counterB->GetVariable("name")->ToString(), "testcounter1");
-
-	counterB->SetVariableValue("counter", "10042");
-
-	// Step 0:
-	UnitTest::Assert("the step should initially be 0",
-	    gxemul.GetStep(), 0);
-	UnitTest::Assert("counterA should initially be 42",
-	    counterA->GetVariable("counter")->ToInteger(), 42);
-	UnitTest::Assert("counterB should initially be 10042",
-	    counterB->GetVariable("counter")->ToInteger(), 10042);
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute();
-
-	// Step 1:
-	UnitTest::Assert("runstate wasn't reset after step 0?",
-	    gxemul.GetRunState() == GXemul::Paused);
-	UnitTest::Assert("the step should now be 1", gxemul.GetStep(), 1);
-	UnitTest::Assert("counter A should now be 43",
-	    counterA->GetVariable("counter")->ToInteger(), 43);
-	UnitTest::Assert("counter B should now be 10043",
-	    counterB->GetVariable("counter")->ToInteger(), 10043);
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute();
-
-	// Step 2:
-	UnitTest::Assert("runstate wasn't reset after step 1?",
-	    gxemul.GetRunState() == GXemul::Paused);
-	UnitTest::Assert("the step should now be 2", gxemul.GetStep(), 2);
-	UnitTest::Assert("counter A should now be 44",
-	    counterA->GetVariable("counter")->ToInteger(), 44);
-	UnitTest::Assert("counter B should now be 10044",
-	    counterB->GetVariable("counter")->ToInteger(), 10044);
-}
-
-static void Test_DummyComponent_Execute_TwoComponentsDifferentSpeed()
-{
-	GXemul gxemul;
-	stringstream os;
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'A'));
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'B'));
-
-	UnitTest::Assert("the testcounters should have been added",
-	    gxemul.GetRootComponent()->GetChildren().size(), 2);
-
-	refcount_ptr<Component> counterA = gxemul.GetRootComponent()->GetChildren()[0];
-	refcount_ptr<Component> counterB = gxemul.GetRootComponent()->GetChildren()[1];
-
-	UnitTest::Assert("name A mismatch",
-	    counterA->GetVariable("name")->ToString(), "testcounter0");
-	UnitTest::Assert("name B mismatch",
-	    counterB->GetVariable("name")->ToString(), "testcounter1");
-
-	// Counter B should run twice as fast:
-	counterA->SetVariableValue("frequency", "100000");
-	counterB->SetVariableValue("frequency", "200000");
-
-	counterB->SetVariableValue("counter", "10042");
-
-	// Step 0:
-	UnitTest::Assert("the step should initially be 0",
-	    gxemul.GetStep(), 0);
-	UnitTest::Assert("counterA should initially be 42",
-	    counterA->GetVariable("counter")->ToInteger(), 42);
-	UnitTest::Assert("counterB should initially be 10042",
-	    counterB->GetVariable("counter")->ToInteger(), 10042);
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute();
-	// B executes in the first step.
-	
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute();
-	// A,B execute in the second step.
-
-	// Step 2:
-	UnitTest::Assert("the step should now be 2", gxemul.GetStep(), 2);
-	UnitTest::Assert("counter A should now be 43",
-	    counterA->GetVariable("counter")->ToInteger(), 43);
-	UnitTest::Assert("counter B should now be 10044",
-	    counterB->GetVariable("counter")->ToInteger(), 10044);
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute();
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute();
-
-	// Step 4:
-	UnitTest::Assert("the step should now be 4", gxemul.GetStep(), 4);
-	UnitTest::Assert("counter A should now be 44",
-	    counterA->GetVariable("counter")->ToInteger(), 44);
-	UnitTest::Assert("counter B should now be 10046",
-	    counterB->GetVariable("counter")->ToInteger(), 10046);
-
-	UnitTest::Assert("output stream mismatch?",
-	    os.str(), "BABBAB");
-}
-
-static void Test_DummyComponent_Execute_Continuous_SingleComponent()
-{
-	GXemul gxemul;
-	gxemul.GetCommandInterpreter().RunCommand("add testcounter");
-	refcount_ptr<Component> counterA = gxemul.GetRootComponent()->GetChildren()[0];
-
-	counterA->SetVariableValue("counter", "10042");
-
-	// Step 0:
-	UnitTest::Assert("the step should initially be 0",
-	    gxemul.GetStep(), 0);
-	UnitTest::Assert("counterA should initially be 10042",
-	    counterA->GetVariable("counter")->ToInteger(), 10042);
-
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute();
-
-	// Step n:
-	int n = gxemul.GetStep();
-	UnitTest::Assert("counter A should now be 10042 + n",
-	    counterA->GetVariable("counter")->ToInteger(), 10042 + n);
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.Execute();
-
-	// Step n + 1:
-	UnitTest::Assert("the step should now be n + 1", gxemul.GetStep(), n + 1);
-	UnitTest::Assert("counter B should now be 10042 + n + 1",
-	    counterA->GetVariable("counter")->ToInteger(), 10042 + n + 1);
-}
-
-static void Test_DummyComponent_Execute_Continuous_TwoComponentsSameSpeed()
-{
-	GXemul gxemul;
-	stringstream os;
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'A'));
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'B'));
-
-	UnitTest::Assert("accuracy should be cycle!",
-	    gxemul.GetRootComponent()->GetVariable("accuracy")->ToString(), "cycle");
-
-	refcount_ptr<Component> counterA = gxemul.GetRootComponent()->GetChildren()[0];
-	refcount_ptr<Component> counterB = gxemul.GetRootComponent()->GetChildren()[1];
-
-	counterA->SetVariableValue("counter", "123");
-	counterB->SetVariableValue("counter", "0");
-
-	// Step 0:
-	UnitTest::Assert("counterA should initially be 123",
-	    counterA->GetVariable("counter")->ToInteger(), 123);
-	UnitTest::Assert("counterB should initially be 0",
-	    counterB->GetVariable("counter")->ToInteger(), 0);
-
-	// The two components have the same speed, which is a "worst case"
-	// for cycle accurate emulation. They have to be interleaved one
-	// cycle at a time.
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(10000);
-
-	// Step n:
-	int n = gxemul.GetStep();
-	UnitTest::Assert("n very low?", n > 100);
-	UnitTest::Assert("counter A should now be 123 + n",
-	    counterA->GetVariable("counter")->ToInteger(), 123 + n);
-	UnitTest::Assert("counter B should now be 0 + n",
-	    counterB->GetVariable("counter")->ToInteger(), 0 + n);
-
-	// After n steps, the stream should be ABABABAB... n times.
-	stringstream correct;
-	for (int i=0; i<n; ++i)
-		correct << "AB";
-
-	UnitTest::Assert("output stream mismatch?", os.str(), correct.str());
-}
-
-static void Test_DummyComponent_Execute_Continuous_TwoComponentsDifferentSpeed()
-{
-	GXemul gxemul;
-	stringstream os;
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'A'));
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'B'));
-
-	UnitTest::Assert("accuracy should be cycle!",
-	    gxemul.GetRootComponent()->GetVariable("accuracy")->ToString(), "cycle");
-
-	refcount_ptr<Component> counterA = gxemul.GetRootComponent()->GetChildren()[0];
-	refcount_ptr<Component> counterB = gxemul.GetRootComponent()->GetChildren()[1];
-
-	counterA->SetVariableValue("counter", "123");
-	counterB->SetVariableValue("counter", "0");
-
-	// Counter B should run three times as fast:
-	counterA->SetVariableValue("frequency", "100000");
-	counterB->SetVariableValue("frequency", "300000");
-
-	// Step 0:
-	UnitTest::Assert("counterA should initially be 123",
-	    counterA->GetVariable("counter")->ToInteger(), 123);
-	UnitTest::Assert("counterB should initially be 0",
-	    counterB->GetVariable("counter")->ToInteger(), 0);
-
-	// Step 0: B
-	// Step 1: B
-	// Step 2: A and B
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1000);
-
-	// Step n: B should have executed 1 per cycle
-	// but A only 1/3 of the cycles.
-	int n = gxemul.GetStep();
-	int a = counterA->GetVariable("counter")->ToInteger();
-	UnitTest::Assert("counter A should now be approximately 123 + n/3",
-	    (a >= 122 + n/3) && (a <= 123 + n/3));
-	UnitTest::Assert("counter B should now be 0 + n",
-	    counterB->GetVariable("counter")->ToInteger(), 0 + n);
-
-	// After n steps, the stream should be BBAB... n cycles.
-	stringstream correct;
-	for (int i=0; i<n; ++i) {
-		if ((i%3) <= 1)
-			correct << "B";
-		else
-			correct << "AB";
-	}
-	
-	UnitTest::Assert("output stream mismatch?", os.str(), correct.str());
-}
-
-static void Test_DummyComponent_Execute_Continuous_ThreeComponentsDifferentSpeed()
-{
-	GXemul gxemul;
-	stringstream os;
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'A'));
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'B'));
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'C'));
-
-	UnitTest::Assert("accuracy should be cycle!",
-	    gxemul.GetRootComponent()->GetVariable("accuracy")->ToString(), "cycle");
-
-	refcount_ptr<Component> counterA = gxemul.GetRootComponent()->GetChildren()[0];
-	refcount_ptr<Component> counterB = gxemul.GetRootComponent()->GetChildren()[1];
-	refcount_ptr<Component> counterC = gxemul.GetRootComponent()->GetChildren()[2];
-
-	counterA->SetVariableValue("counter", "0");
-	counterB->SetVariableValue("counter", "0");
-	counterC->SetVariableValue("counter", "0");
-
-	counterA->SetVariableValue("frequency", "1");
-	counterB->SetVariableValue("frequency", "100");
-	counterC->SetVariableValue("frequency", "10");
-
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(2000);
-
-	int n = gxemul.GetStep();
-	UnitTest::Assert("n very low?", n >= 2000);
-
-	int a = counterA->GetVariable("counter")->ToInteger();
-	UnitTest::Assert("counter A should now be approximately n / 100",
-	    (a >= n / 100 - 1) && (a <= n / 100 + 1));
-
-	UnitTest::Assert("counter B should now be n",
-	    counterB->GetVariable("counter")->ToInteger(), n);
-
-	int c = counterC->GetVariable("counter")->ToInteger();
-	UnitTest::Assert("counter C should now be approximately n / 10",
-	    (c >= n / 10 - 1) && (c <= n / 10 + 1));
-
-
-	// Compare with single-step stream:
-	{
-		GXemul gxemul2;
-		stringstream singleStepStream;
-		gxemul2.GetRootComponent()->AddChild(new DummyComponentWithCounter(&singleStepStream, 'A'));
-		gxemul2.GetRootComponent()->AddChild(new DummyComponentWithCounter(&singleStepStream, 'B'));
-		gxemul2.GetRootComponent()->AddChild(new DummyComponentWithCounter(&singleStepStream, 'C'));
-
-		counterA = gxemul2.GetRootComponent()->GetChildren()[0];
-		counterB = gxemul2.GetRootComponent()->GetChildren()[1];
-		counterC = gxemul2.GetRootComponent()->GetChildren()[2];
-
-		counterA->SetVariableValue("counter", "0");
-		counterB->SetVariableValue("counter", "0");
-		counterC->SetVariableValue("counter", "0");
-
-		counterA->SetVariableValue("frequency", "1");
-		counterB->SetVariableValue("frequency", "100");
-		counterC->SetVariableValue("frequency", "10");
-
-		for (int i=0; i<n; ++i) {
-			gxemul2.SetRunState(GXemul::SingleStepping);
-			gxemul2.Execute();
-		}
-		
-		UnitTest::Assert("output stream mismatch?", os.str() == singleStepStream.str());
-	}	
-}
-
-static void Test_DummyComponent_Execute_Continuous_ThreeComponentsDifferentSpeedWeird()
-{
-	// Same as the test above, but with horribly choosen frequencies.
-	GXemul gxemul;
-	stringstream os;
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'A'));
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'B'));
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'C'));
-
-	UnitTest::Assert("accuracy should be cycle!",
-	    gxemul.GetRootComponent()->GetVariable("accuracy")->ToString(), "cycle");
-
-	refcount_ptr<Component> counterA = gxemul.GetRootComponent()->GetChildren()[0];
-	refcount_ptr<Component> counterB = gxemul.GetRootComponent()->GetChildren()[1];
-	refcount_ptr<Component> counterC = gxemul.GetRootComponent()->GetChildren()[2];
-
-	counterA->SetVariableValue("counter", "0");
-	counterB->SetVariableValue("counter", "0");
-	counterC->SetVariableValue("counter", "0");
-
-	counterA->SetVariableValue("frequency", "7");
-	counterB->SetVariableValue("frequency", "101");
-	counterC->SetVariableValue("frequency", "18");
-
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(2000);
-
-	int n = gxemul.GetStep();
-	UnitTest::Assert("n very low?", n >= 2000);
-
-	// Compare with single-step stream:
-	{
-		GXemul gxemul2;
-		stringstream singleStepStream;
-		gxemul2.GetRootComponent()->AddChild(new DummyComponentWithCounter(&singleStepStream, 'A'));
-		gxemul2.GetRootComponent()->AddChild(new DummyComponentWithCounter(&singleStepStream, 'B'));
-		gxemul2.GetRootComponent()->AddChild(new DummyComponentWithCounter(&singleStepStream, 'C'));
-
-		counterA = gxemul2.GetRootComponent()->GetChildren()[0];
-		counterB = gxemul2.GetRootComponent()->GetChildren()[1];
-		counterC = gxemul2.GetRootComponent()->GetChildren()[2];
-
-		counterA->SetVariableValue("counter", "0");
-		counterB->SetVariableValue("counter", "0");
-		counterC->SetVariableValue("counter", "0");
-
-		counterA->SetVariableValue("frequency", "7");
-		counterB->SetVariableValue("frequency", "101");
-		counterC->SetVariableValue("frequency", "18");
-
-		for (int i=0; i<n; ++i) {
-			gxemul2.SetRunState(GXemul::SingleStepping);
-			gxemul2.Execute();
-		}
-		
-		UnitTest::Assert("output stream mismatch?", os.str() == singleStepStream.str());
-	}	
-}
-
-/*
-static void Test_DummyComponent_Execute_Continuous_ThreeComponentsDifferentSpeedWeird2()
-{
-	// Same as the test above, but with even more horribly choosen frequencies.
-	GXemul gxemul;
-	stringstream os;
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'A'));
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'B'));
-	gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&os, 'C'));
-
-	UnitTest::Assert("accuracy should be cycle!",
-	    gxemul.GetRootComponent()->GetVariable("accuracy")->ToString(), "cycle");
-
-	refcount_ptr<Component> counterA = gxemul.GetRootComponent()->GetChildren()[0];
-	refcount_ptr<Component> counterB = gxemul.GetRootComponent()->GetChildren()[1];
-	refcount_ptr<Component> counterC = gxemul.GetRootComponent()->GetChildren()[2];
-
-	counterA->SetVariableValue("counter", "0");
-	counterB->SetVariableValue("counter", "0");
-	counterC->SetVariableValue("counter", "0");
-
-	counterA->SetVariableValue("frequency", "183");
-	counterB->SetVariableValue("frequency", "191");
-	counterC->SetVariableValue("frequency", "194");
-
-	gxemul.SetRunState(GXemul::Running);
-	gxemul.Execute(1000);
-
-	int n = gxemul.GetStep();
-	UnitTest::Assert("n very low?", n >= 1000);
-
-	// Compare with single-step stream:
-	{
-		GXemul gxemul;
-		stringstream singleStepStream;
-		gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&singleStepStream, 'A'));
-		gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&singleStepStream, 'B'));
-		gxemul.GetRootComponent()->AddChild(new DummyComponentWithCounter(&singleStepStream, 'C'));
-
-		refcount_ptr<Component> counterA = gxemul.GetRootComponent()->GetChildren()[0];
-		refcount_ptr<Component> counterB = gxemul.GetRootComponent()->GetChildren()[1];
-		refcount_ptr<Component> counterC = gxemul.GetRootComponent()->GetChildren()[2];
-
-		counterA->SetVariableValue("counter", "0");
-		counterB->SetVariableValue("counter", "0");
-		counterC->SetVariableValue("counter", "0");
-
-		counterA->SetVariableValue("frequency", "183");
-		counterB->SetVariableValue("frequency", "191");
-		counterC->SetVariableValue("frequency", "194");
-
-		for (int i=0; i<n; ++i) {
-			gxemul.SetRunState(GXemul::SingleStepping);
-			gxemul.Execute();
-		}
-		
-		UnitTest::Assert("output stream mismatch?", os.str(), singleStepStream.str());
-	}	
-}
-*/
-
-UNITTESTS(DummyComponent)
-{
-	ComponentFactory::RegisterComponentClass("dummy2",
-	    DummyComponentWithAllVariableTypes::Create,
-	    DummyComponent::GetAttribute);
-
-	ComponentFactory::RegisterComponentClass("testcounter",
-	    DummyComponentWithCounter::Create,
-	    DummyComponent::GetAttribute);
-
-	// Creation using CreateComponent
-	UNITTEST(Test_DummyComponent_CreateComponent);
-
-	// Parent tests
-	UNITTEST(Test_DummyComponent_GetSetParent);
-
-	// Add/Remove children
-	UNITTEST(Test_DummyComponent_AddChild_Sets_Parent);
-	UNITTEST(Test_DummyComponent_AddChildren_Count);
-	UNITTEST(Test_DummyComponent_Add_Tree_Of_Children);
-	UNITTEST(Test_DummyComponent_RemoveChild);
-	UNITTEST(Test_DummyComponent_AddChild_UniqueName);
-
-	// Path tests
-	UNITTEST(Test_DummyComponent_GeneratePath);
-	UNITTEST(Test_DummyComponent_GenerateShortestPossiblePath);
-	UNITTEST(Test_DummyComponent_LookupPath);
-	UNITTEST(Test_DummyComponent_FindPathByPartialMatch);
-
-	// Get state variables
-	UNITTEST(Test_DummyComponent_GetUnknownVariable);
-
-	// Methods
-	UNITTEST(Test_DummyComponent_NonexistantMethodNotReexecutable);
-
-	// Clone
-	UNITTEST(Test_DummyComponent_Clone_Basic);
-	UNITTEST(Test_DummyComponent_Clone_AllVariableTypes);
-
-	// Serialization/deserialization
-	UNITTEST(Test_DummyComponent_SerializeDeserialize);
-
-	// Cycle execution
-	UNITTEST(Test_DummyComponent_Execute_SingleStep);
-	UNITTEST(Test_DummyComponent_Execute_MultiSingleStep);
-	UNITTEST(Test_DummyComponent_Execute_TwoComponentsSameSpeed);
-	UNITTEST(Test_DummyComponent_Execute_TwoComponentsDifferentSpeed);
-	UNITTEST(Test_DummyComponent_Execute_Continuous_SingleComponent);
-	UNITTEST(Test_DummyComponent_Execute_Continuous_TwoComponentsSameSpeed);
-	UNITTEST(Test_DummyComponent_Execute_Continuous_TwoComponentsDifferentSpeed);
-	UNITTEST(Test_DummyComponent_Execute_Continuous_ThreeComponentsDifferentSpeed);
-	UNITTEST(Test_DummyComponent_Execute_Continuous_ThreeComponentsDifferentSpeedWeird);
-// TODO: This currently fails!
-//	UNITTEST(Test_DummyComponent_Execute_Continuous_ThreeComponentsDifferentSpeedWeird2);
-}
-
-#endif
-
diff -Nru gxemul-0.6.2/src/components/special/Makefile.skel gxemul-0.7.0+dfsg/src/components/special/Makefile.skel
--- gxemul-0.6.2/src/components/special/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/special/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,19 +0,0 @@
-#
-#  Makefile for GXemul src/components/special
-#
-
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(CPEDANTIC) $(INCLUDE2)
-LIBS=$(OTHERLIBS)
-
-OBJS=DummyComponent.o RootComponent.o
-
-all: $(OBJS)
-
-$(OBJS): Makefile
-
-clean:
-	rm -f $(OBJS)
-
-clean_all: clean
-	rm -f Makefile
-
diff -Nru gxemul-0.6.2/src/components/special/RootComponent.cc gxemul-0.7.0+dfsg/src/components/special/RootComponent.cc
--- gxemul-0.6.2/src/components/special/RootComponent.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/components/special/RootComponent.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,133 +0,0 @@
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "components/RootComponent.h"
-#include "ComponentFactory.h"
-#include "GXemul.h"
-
-
-RootComponent::RootComponent(GXemul* owner)
-	: Component("root", "root")
-	, m_gxemul(owner)
-	, m_accuracy("cycle")
-{
-	SetVariableValue("name", "\"root\"");
-
-	AddVariable("accuracy", &m_accuracy);
-}
-
-
-bool RootComponent::PreRunCheckForComponent(GXemul* gxemul)
-{
-	if (m_accuracy != "cycle" && m_accuracy != "sloppy") {
-		gxemul->GetUI()->ShowDebugMessage(this, "accuracy must be \"cycle\" or \"sloppy\".\n");		
-		return false;
-	}
-
-	return true;
-}
-
-
-void RootComponent::SetOwner(GXemul* owner)
-{
-	m_gxemul = owner;
-}
-
-
-bool RootComponent::CheckVariableWrite(StateVariable& var, const string& oldValue)
-{
-	UI* ui = GetUI();
-	const string& name = var.GetName();
-
-	if (name == "accuracy") {
-		if (var.ToString() != "cycle" && var.ToString() != "sloppy") {
-			if (ui != NULL)
-				ui->ShowDebugMessage(this, "accuracy must be \"cycle\" or \"sloppy\".\n");
-
-			return false;
-		}
-	}
-
-	return Component::CheckVariableWrite(var, oldValue);
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_RootComponent_CreateComponent()
-{
-	refcount_ptr<Component> component;
-
-	component = ComponentFactory::CreateComponent("root");
-	UnitTest::Assert("creating a root component with CreateComponent "
-	    "should NOT be possible", component.IsNULL() == true);
-}
-
-static void Test_RootComponent_InitialVariables()
-{
-	refcount_ptr<Component> component = new RootComponent;
-
-	StateVariable* name = component->GetVariable("name");
-	StateVariable* step = component->GetVariable("step");
-	StateVariable* accuracy = component->GetVariable("accuracy");
-
-	UnitTest::Assert("name should be root", name->ToString(), "root");
-	UnitTest::Assert("step should be 0", step->ToInteger(), 0);
-	UnitTest::Assert("accuracy should be cycle", accuracy->ToString(), "cycle");
-}
-
-static void Test_RootComponent_AccuracyValues()
-{
-	GXemul dummyGXemul;
-
-	refcount_ptr<Component> component = new RootComponent;
-	StateVariable* accuracy = component->GetVariable("accuracy");
-
-	accuracy->SetValue("\"sloppy\"");
-	UnitTest::Assert("sloppy should be ok", component->PreRunCheck(&dummyGXemul));
-
-	accuracy->SetValue("\"nonsense\"");
-	UnitTest::Assert("nonsense should not be ok", !component->PreRunCheck(&dummyGXemul));
-
-	accuracy->SetValue("\"cycle\"");
-	UnitTest::Assert("cycle should be ok", component->PreRunCheck(&dummyGXemul));
-}
-
-UNITTESTS(RootComponent)
-{
-	UNITTEST(Test_RootComponent_CreateComponent);
-	UNITTEST(Test_RootComponent_InitialVariables);
-	UNITTEST(Test_RootComponent_AccuracyValues);
-
-	// TODO: Test owner
-}
-
-#endif
-
diff -Nru gxemul-0.6.2/src/console/console.c gxemul-0.7.0+dfsg/src/console/console.c
--- gxemul-0.6.2/src/console/console.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/console/console.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1049 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Generic console support functions.
+ *
+ *  This module is used by individual device drivers, for example serial
+ *  controllers, keyboards, or other devices which need to attach to the
+ *  emulator's real stdin/stdout.
+ *
+ *  The idea is that several input and output streams (console handles) are
+ *  allowed. As long as the number of input streams is <= 1, then everything
+ *  can be done in the emulator's default terminal window.
+ *
+ *  If the number of inputs is more than 1, it is necessary to open up slave
+ *  xterm windows for each input. (Otherwise the behaviour is undefined; i.e.
+ *  which of two emulated serial controllers would get keyboard input?)
+ *
+ *  (If the -x command line option is NOT used, then slaves are not opened up.
+ *  Instead, a warning message is printed, and input is not allowed.)
+ *
+ *  Note that console handles that _allow_ input but are not yet used for
+ *  output are not counted. This allows a machine to have, say, 2 serial ports
+ *  which can be used for both input and output, and it will still be possible
+ *  to run in the default terminal window as long as only one of those serial
+ *  ports is actually used.
+ *
+ *  xterms are opened up "on demand", when output is sent to them.
+ *
+ *  The MAIN console handle (fixed as handle nr 0) is the one used by the
+ *  default terminal window. A machine which registers a serial controller,
+ *  which should be used as the main way of communicating with guest operating
+ *  systems running on that machine, should set machine->main_console_handle
+ *  to the handle of the correct port on that controller.
+ *
+ *
+ *  NOTE: The code in this module is mostly non-reentrant.
+ */
+
+#include <errno.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <termios.h>
+#include <unistd.h>
+#include <sys/select.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <time.h>
+
+#include "console.h"
+#include "emul.h"
+#include "machine.h"
+#include "settings.h"
+
+
+extern char *progname;
+extern int verbose;
+extern struct settings *global_settings;
+
+
+static struct termios console_oldtermios;
+static struct termios console_curtermios;
+
+/*  For 'slave' mode:  */
+static struct termios console_slave_tios;
+static int console_slave_outputd;
+
+static int console_initialized = 0;
+static struct settings *console_settings = NULL;
+static int console_stdout_pending;
+
+#define	CONSOLE_FIFO_LEN	4096
+
+static struct timeval console_mouse_lastupdate;
+static int console_mouse_dx;		/*  relative since last call  */
+static int console_mouse_dy;		/*  relative since last call  */
+static int console_mouse_fb_nr;		/*  framebuffer number of
+					    host movement, 0-based  */
+static int console_mouse_buttons;	/*  left=4, middle=2, right=1  */
+
+static int allow_slaves = 0;
+
+struct console_handle {
+	int		in_use;
+	int		in_use_for_input;
+	int		using_xterm;
+	int		inputonly;
+	int		outputonly;
+	int		warning_printed;
+
+	char		*machine_name;
+	char		*name;
+
+	int		w_descriptor;
+	int		r_descriptor;
+
+	unsigned char	fifo[CONSOLE_FIFO_LEN];
+	int		fifo_head;
+	int		fifo_tail;
+};
+
+#define	NOT_USING_XTERM				0
+#define	USING_XTERM_BUT_NOT_YET_OPEN		1
+#define	USING_XTERM				2
+
+/*  A simple array of console_handles  */
+static struct console_handle *console_handles = NULL;
+static int n_console_handles = 0;
+
+
+/*
+ *  console_deinit_main():
+ *
+ *  Restore host's console settings.
+ */
+void console_deinit_main(void)
+{
+	if (!console_initialized)
+		return;
+
+	tcsetattr(STDIN_FILENO, TCSANOW, &console_oldtermios);
+
+	console_initialized = 0;
+}
+
+
+/*
+ *  console_sigcont():
+ *
+ *  If the user presses CTRL-Z (to stop the emulator process) and then
+ *  continues, the termios settings might have been invalidated. This
+ *  function restores them.
+ *
+ *  (This function should be set as the SIGCONT signal handler in src/emul.c.)
+ */
+void console_sigcont(int x)
+{
+	if (!console_initialized)
+		return;
+
+	/*  Make sure that the correct (current) termios setting is active:  */
+	tcsetattr(STDIN_FILENO, TCSANOW, &console_curtermios);
+
+	/*  Reset the signal handler:  */
+	signal(SIGCONT, console_sigcont);
+}
+
+
+/*
+ *  start_xterm():
+ *
+ *  When using X11 (well, when allow_slaves is set), this routine tries to
+ *  start up an xterm, with another copy of gxemul inside. The other gxemul
+ *  copy is given arguments that will cause it to run console_slave().
+ *
+ *  TODO: This is ugly and hardcoded. Clean it up.
+ */
+static void start_xterm(int handle)
+{
+	int filedes[2];
+	int filedesB[2];
+	int res;
+	size_t mlen;
+	char **a;
+	pid_t p;
+
+	res = pipe(filedes);
+	if (res) {
+		printf("[ start_xterm(): pipe(): %i ]\n", errno);
+		exit(1);
+	}
+
+	res = pipe(filedesB);
+	if (res) {
+		printf("[ start_xterm(): pipe(): %i ]\n", errno);
+		exit(1);
+	}
+
+	/*  printf("filedes = %i,%i\n", filedes[0], filedes[1]);  */
+	/*  printf("filedesB = %i,%i\n", filedesB[0], filedesB[1]);  */
+
+	/*  NOTE/warning: Hardcoded max nr of args!  */
+	CHECK_ALLOCATION(a = (char **) malloc(sizeof(char *) * 20));
+
+	a[0] = getenv("XTERM");
+	if (a[0] == NULL)
+		a[0] = strdup("xterm");
+	a[1] = strdup("-geometry");
+	a[2] = strdup("80x25");
+	a[3] = strdup("-title");
+	mlen = strlen(console_handles[handle].name) +
+	    strlen(console_handles[handle].machine_name) + 30;
+	CHECK_ALLOCATION(a[4] = (char *) malloc(mlen));
+	snprintf(a[4], mlen, "GXemul: %s %s",
+	    console_handles[handle].machine_name,
+	    console_handles[handle].name);
+	a[5] = strdup("-e");
+	a[6] = progname;
+	CHECK_ALLOCATION(a[7] = (char *) malloc(80));
+	snprintf(a[7], 80, "-WW@S%i,%i", filedes[0], filedesB[1]);
+	a[8] = NULL;
+
+	p = fork();
+	if (p == -1) {
+		printf("[ start_xterm(): ERROR while trying to "
+		    "fork(): %i ]\n", errno);
+		exit(1);
+	} else if (p == 0) {
+		close(filedes[1]);
+		close(filedesB[0]);
+
+		p = setsid();
+		if (p < 0)
+			printf("[ start_xterm(): ERROR while trying "
+			    "to do a setsid(): %i ]\n", errno);
+
+		res = execvp(a[0], a);
+		printf("[ start_xterm(): ERROR while trying to "
+		    "execvp(\"");
+		while (a[0] != NULL) {
+			printf("%s", a[0]);
+			if (a[1] != NULL)
+				printf(" ");
+			a++;
+		}
+		printf("\"): %i ]\n", errno);
+		if (errno == ENOENT)
+			printf("[ Most probably you don't have xterm"
+			    " in your PATH. Try again. ]\n");
+		exit(1);
+	}
+
+	/*  TODO: free a and a[*]  */
+
+	close(filedes[0]);
+	close(filedesB[1]);
+
+	console_handles[handle].using_xterm = USING_XTERM;
+
+	/*
+	 *  write to filedes[1], read from filedesB[0]
+	 */
+
+	console_handles[handle].w_descriptor = filedes[1];
+	console_handles[handle].r_descriptor = filedesB[0];
+}
+
+
+/*
+ *  d_avail():
+ *
+ *  Returns 1 if anything is available on a descriptor.
+ */
+static int d_avail(int d)
+{
+	fd_set rfds;
+	struct timeval tv;
+
+	FD_ZERO(&rfds);
+	FD_SET(d, &rfds);
+	tv.tv_sec = 0;
+	tv.tv_usec = 0;
+
+	for (;;) {
+		// Select may return -1 if interrupted.
+		int r = select(d+1, &rfds, NULL, NULL, &tv);
+		if (r >= 0)
+			return r;
+	}
+}
+
+
+/*
+ *  console_makeavail():
+ *
+ *  Put a character in the queue, so that it will be avaiable,
+ *  by inserting it into the char fifo.
+ */
+void console_makeavail(int handle, char ch)
+{
+	console_handles[handle].fifo[
+	    console_handles[handle].fifo_head] = ch;
+	console_handles[handle].fifo_head = (
+	    console_handles[handle].fifo_head + 1) % CONSOLE_FIFO_LEN;
+
+	if (console_handles[handle].fifo_head ==
+	    console_handles[handle].fifo_tail)
+		fatal("[ WARNING: console fifo overrun, handle %i ]\n", handle);
+}
+
+
+/*
+ *  console_stdin_avail():
+ *
+ *  Returns 1 if a char is available from a handle's read descriptor,
+ *  0 otherwise.
+ */
+static int console_stdin_avail(int handle)
+{
+	if (!console_handles[handle].in_use_for_input)
+		return 0;
+
+	if (!allow_slaves)
+		return d_avail(STDIN_FILENO);
+
+	if (console_handles[handle].using_xterm ==
+	    USING_XTERM_BUT_NOT_YET_OPEN)
+		return 0;
+
+	return d_avail(console_handles[handle].r_descriptor);
+}
+
+
+static int console_room_left_in_fifo(int handle)
+{
+	int roomLeftInFIFO = console_handles[handle].fifo_tail
+	    - console_handles[handle].fifo_head;
+	if (roomLeftInFIFO <= 0)
+		roomLeftInFIFO += CONSOLE_FIFO_LEN;
+
+	return roomLeftInFIFO;
+}
+
+
+/*
+ *  console_charavail():
+ *
+ *  Returns the number of chararacters available in the fifo.
+ */
+int console_charavail(int handle)
+{
+	while (console_stdin_avail(handle)) {
+		unsigned char ch[100];		/* = getchar(); */
+		ssize_t len;
+		int i, d;
+
+		// If adding more would lead to a full FIFO, then let's
+		// wait.
+		int roomLeftInFIFO = console_room_left_in_fifo(handle);
+		if (roomLeftInFIFO < (int)sizeof(ch) + 1)
+			break;
+
+		if (!allow_slaves)
+			d = STDIN_FILENO;
+		else
+			d = console_handles[handle].r_descriptor;
+
+		len = read(d, ch, sizeof(ch));
+
+		for (i=0; i<len; i++) {
+			/*  printf("[ %i: %i ]\n", i, ch[i]);  */
+
+			if (!allow_slaves) {
+				/*  Convert CTRL-B intro CTRL-C.  */
+				if (ch[i] == 2)
+					ch[i] = 3;
+			}
+
+			// CTRL-T (SIGINFO-like) info. This does not work
+			// well when running with -x, since noone checks
+			// for charavail at stdin then...
+			//
+			// if (ch[i] == 20 && d == STDIN_FILENO) {
+			//	printf("\n");
+			//	cpu_show_cycles(machine..., true);
+			// }
+
+			console_makeavail(handle, ch[i]);
+		}
+	}
+
+	return CONSOLE_FIFO_LEN - console_room_left_in_fifo(handle);
+}
+
+
+/*
+ *  console_any_input_available():
+ *
+ *  Return true if keyboard or mouse input is available.
+ *
+ *  TODO: Mouse buttons are not checked yet.
+ */
+bool console_any_input_available(struct emul *emul)
+{
+	bool somethingAvailable = false;
+
+	// Any non-zero mouse delta in the last second counts as input available
+	if (console_mouse_dx != 0 || console_mouse_dy != 0) {
+		struct timeval tv;
+		gettimeofday(&tv, NULL);
+
+		uint64_t t1 = console_mouse_lastupdate.tv_sec * 1000000 +
+			console_mouse_lastupdate.tv_usec;
+		uint64_t t2 = tv.tv_sec * 1000000 + tv.tv_usec;
+
+		if (t2 - t1 < 1000000)
+			somethingAvailable = true;
+	}
+
+	if (emul->n_machines == 1) {
+		if (console_charavail(emul->machines[0]->main_console_handle))
+			somethingAvailable = true;
+	}
+
+	return somethingAvailable;
+}
+
+
+/*
+ *  console_readchar():
+ *
+ *  Returns 0..255 if a char was available, -1 otherwise.
+ */
+int console_readchar(int handle)
+{
+	int ch;
+
+	if (!console_charavail(handle))
+		return -1;
+
+	ch = console_handles[handle].fifo[console_handles[handle].fifo_tail];
+	console_handles[handle].fifo_tail ++;
+	console_handles[handle].fifo_tail %= CONSOLE_FIFO_LEN;
+
+	return ch;
+}
+
+
+/*
+ *  console_putchar():
+ *
+ *  Prints a char to stdout, and sets the console_stdout_pending flag.
+ */
+void console_putchar(int handle, int ch)
+{
+	char buf[1];
+
+	if (!console_handles[handle].in_use_for_input &&
+	    !console_handles[handle].outputonly)
+		console_change_inputability(handle, 1);
+
+	if (!allow_slaves) {
+		/*  stdout:  */
+		putchar(ch);
+
+		/*  Assume flushes by OS or libc on newlines:  */
+		if (ch == '\n')
+			console_stdout_pending = 0;
+		else
+			console_stdout_pending = 1;
+
+		return;
+	}
+
+	if (!console_handles[handle].in_use) {
+		printf("[ console_putchar(): handle %i not in"
+		    " use! ]\n", handle);
+		return;
+		}
+
+	if (console_handles[handle].using_xterm ==
+	    USING_XTERM_BUT_NOT_YET_OPEN)
+		start_xterm(handle);
+
+	buf[0] = ch;
+	if (write(console_handles[handle].w_descriptor, buf, 1) != 1)
+		perror("error writing to console handle");
+}
+
+
+/*
+ *  console_flush():
+ *
+ *  Flushes stdout, if necessary, and resets console_stdout_pending to zero.
+ */
+void console_flush(void)
+{
+	if (console_stdout_pending)
+		fflush(stdout);
+
+	console_stdout_pending = 0;
+}
+
+
+/*
+ *  console_mouse_coordinate_update():
+ *
+ *  Updates mouse coordinates. Called by for example an X11 event handler.
+ *  dx and dy are relative coordinates, fb_nr is where the mouse movement
+ *  took place.
+ */
+void console_mouse_coordinate_update(int dx, int dy, int fb_nr)
+{
+	gettimeofday(&console_mouse_lastupdate, NULL);
+	console_mouse_dx += dx;
+	console_mouse_dy += dy;
+	console_mouse_fb_nr = fb_nr;
+}
+
+
+/*
+ *  console_mouse_button():
+ *
+ *  Sets a mouse button to be pressed or released. Called by for example an
+ *  X11 event handler.  button is 1 (left), 2 (middle), or 3 (right), and
+ *  pressed = 1 for pressed, 0 for not pressed.
+ */
+void console_mouse_button(int button, int pressed)
+{
+	int mask = 1 << (3-button);
+
+	if (pressed)
+		console_mouse_buttons |= mask;
+	else
+		console_mouse_buttons &= ~mask;
+}
+
+
+/*
+ *  console_getmouse():
+ *
+ *  Gets current mouse data into the variables pointed to by the arguments.
+ *  The mouse delta x and y are then cleared.
+ */
+void console_getmouse(int *dx, int *dy, int *buttons, int *fb_nr)
+{
+	*dx = console_mouse_dx;
+	*dy = console_mouse_dy;
+	*buttons = console_mouse_buttons;
+	*fb_nr = console_mouse_fb_nr;
+
+	console_mouse_dx = 0;
+	console_mouse_dy = 0;
+}
+
+
+/*
+ *  console_slave_sigint():
+ */
+static void console_slave_sigint(int x)
+{
+	char buf[1];
+
+	/*  Send a ctrl-c:  */
+	buf[0] = 3;
+	if (write(console_slave_outputd, buf, sizeof(buf)) != sizeof(buf))
+		perror("error writing to console handle");
+
+	/*  Reset the signal handler:  */
+	signal(SIGINT, console_slave_sigint);
+}
+
+
+/*
+ *  console_slave_sigcont():
+ *
+ *  See comment for console_sigcont. This is for used by console_slave().
+ */
+static void console_slave_sigcont(int x)
+{
+	/*  Make sure our 'current' termios setting is active:  */
+	tcsetattr(STDIN_FILENO, TCSANOW, &console_slave_tios);
+
+	/*  Reset the signal handler:  */
+	signal(SIGCONT, console_slave_sigcont);
+}
+
+
+/*
+ *  console_slave():
+ *
+ *  This function is used when running with X11, and gxemul opens up
+ *  separate xterms for each emulated terminal or serial port.
+ */
+void console_slave(const char *arg)
+{
+	int inputd;
+	int len;
+	const char *p;
+	char buf[16384];
+
+	/*  arg = '3,6' or similar, input and output descriptors  */
+	/*  printf("console_slave(): arg = '%s'\n", arg);  */
+
+	inputd = atoi(arg);
+	p = strchr(arg, ',');
+	if (p == NULL) {
+		printf("console_slave(): bad arg '%s'\n", arg);
+		sleep(5);
+		exit(1);
+	}
+	console_slave_outputd = atoi(p+1);
+
+	/*  Set the terminal to raw mode:  */
+	tcgetattr(STDIN_FILENO, &console_slave_tios);
+
+	console_slave_tios.c_lflag &= ~ICANON;
+	console_slave_tios.c_cc[VTIME] = 0;
+	console_slave_tios.c_cc[VMIN] = 1;
+	console_slave_tios.c_lflag &= ~ECHO;
+	console_slave_tios.c_iflag &= ~ICRNL;
+	tcsetattr(STDIN_FILENO, TCSANOW, &console_slave_tios);
+
+	signal(SIGINT, console_slave_sigint);
+	signal(SIGCONT, console_slave_sigcont);
+
+	for (;;) {
+		/*  TODO: select() on both inputd and stdin  */
+
+		if (d_avail(inputd)) {
+			len = read(inputd, buf, sizeof(buf) - 1);
+			if (len < 1)
+				exit(0);
+			buf[len] = '\0';
+			printf("%s", buf);
+			fflush(stdout);
+		}
+
+		if (d_avail(STDIN_FILENO)) {
+			len = read(STDIN_FILENO, buf, sizeof(buf));
+			if (len < 1)
+				exit(0);
+			if (write(console_slave_outputd, buf, len) != len)
+				perror("error writing to console handle");
+		}
+
+		usleep(10000);
+	}
+}
+
+
+/*
+ *  console_new_handle():
+ *
+ *  Allocates a new console_handle struct, and returns a pointer to it.
+ *
+ *  For internal use.
+ */
+static struct console_handle *console_new_handle(const char *name, int *handlep)
+{
+	struct console_handle *chp;
+	int i, n, found_free = -1;
+
+	/*  Reuse an old slot, if possible:  */
+	n = n_console_handles;
+	for (i=0; i<n; i++)
+		if (!console_handles[i].in_use) {
+			found_free = i;
+			break;
+		}
+
+	if (found_free == -1) {
+		/*  Let's realloc console_handles[], to make room
+		    for the new one:  */
+		CHECK_ALLOCATION(console_handles = (struct console_handle *)
+		    realloc(console_handles, sizeof(
+		    struct console_handle) * (n_console_handles + 1)));
+		found_free = n_console_handles;
+		n_console_handles ++;
+	}
+
+	chp = &console_handles[found_free];
+	memset(chp, 0, sizeof(struct console_handle));
+
+	chp->in_use = 1;
+	chp->machine_name = strdup("");
+	CHECK_ALLOCATION(chp->name = strdup(name));
+
+	*handlep = found_free;
+	return chp;
+}
+
+
+/*
+ *  console_start_slave():
+ *
+ *  When using X11:
+ *
+ *  This routine tries to start up an xterm, with another copy of gxemul
+ *  inside. The other gxemul copy is given arguments that will cause it
+ *  to run console_slave().
+ *
+ *  When not using X11:  Things will seem to work the same way without X11,
+ *  but no xterm will actually be started.
+ *
+ *  consolename should be something like "serial 0".
+ *
+ *  If use_for_input is 1, input is allowed right from the start. (This
+ *  can be upgraded later from 0 to 1 using the console_change_inputability()
+ *  function.)
+ *
+ *  If use_for_input is CONSOLE_OUTPUT_ONLY, then this is an output-only stream.
+ *
+ *  On success, an integer >= 0 is returned. This can then be used as a
+ *  'handle' when writing to or reading from an emulated console.
+ *
+ *  On failure, -1 is returned.
+ */
+int console_start_slave(struct machine *machine, const char *consolename,
+	int use_for_input)
+{
+	struct console_handle *chp;
+	int handle;
+
+	if (machine == NULL || consolename == NULL) {
+		printf("console_start_slave(): NULL ptr\n");
+		exit(1);
+	}
+
+	chp = console_new_handle(consolename, &handle);
+	chp->in_use_for_input = use_for_input;
+	if (use_for_input == CONSOLE_OUTPUT_ONLY) {
+		chp->outputonly = 1;
+		chp->in_use_for_input = 0;
+	}
+
+	if (machine->machine_name != NULL) {
+		CHECK_ALLOCATION(chp->machine_name =
+		    strdup(machine->machine_name));
+	} else {
+		CHECK_ALLOCATION(chp->machine_name = strdup(""));
+	}
+
+	CHECK_ALLOCATION(chp->name = strdup(consolename));
+
+	if (allow_slaves)
+		chp->using_xterm = USING_XTERM_BUT_NOT_YET_OPEN;
+
+	return handle;
+}
+
+
+/*
+ *  console_start_slave_inputonly():
+ *
+ *  Similar to console_start_slave(), but doesn't open an xterm. This is
+ *  useful for devices such as keyboard controllers, that need to have an
+ *  input queue, but no xterm window associated with it.
+ *
+ *  On success, an integer >= 0 is returned. This can then be used as a
+ *  'handle' when writing to or reading from an emulated console.
+ *
+ *  On failure, -1 is returned.
+ */
+int console_start_slave_inputonly(struct machine *machine, const char *consolename,
+	int use_for_input)
+{
+	struct console_handle *chp;
+	int handle;
+
+	if (machine == NULL || consolename == NULL) {
+		printf("console_start_slave(): NULL ptr\n");
+		exit(1);
+	}
+
+	chp = console_new_handle(consolename, &handle);
+	chp->inputonly = 1;
+	chp->in_use_for_input = use_for_input;
+
+	if (machine->name != NULL) {
+		CHECK_ALLOCATION(chp->machine_name = strdup(machine->name));
+	} else {
+		CHECK_ALLOCATION(chp->machine_name = strdup(""));
+	}
+
+	CHECK_ALLOCATION(chp->name = strdup(consolename));
+
+	return handle;
+}
+
+
+/*
+ *  console_change_inputability():
+ *
+ *  Sets whether or not a console handle can be used for input. Return value
+ *  is 1 if the change took place, 0 otherwise.
+ */
+int console_change_inputability(int handle, int inputability)
+{
+	int old;
+
+	if (handle < 0 || handle >= n_console_handles) {
+		fatal("console_change_inputability(): bad handle %i\n",
+		    handle);
+		exit(1);
+	}
+
+	old = console_handles[handle].in_use_for_input;
+	console_handles[handle].in_use_for_input = inputability;
+
+	if (inputability != 0) {
+		if (console_warn_if_slaves_are_needed(0)) {
+			console_handles[handle].in_use_for_input = old;
+			if (!console_handles[handle].warning_printed) {
+				fatal("%%\n%%  WARNING! Input to console ha"
+				    "ndle \"%s\" wasn't enabled,\n%%  because "
+				    "it", console_handles[handle].name);
+				fatal(" would interfere with other inputs,\n"
+				    "%%  and you did not use the -x command "
+				    "line option!\n%%\n");
+			}
+			console_handles[handle].warning_printed = 1;
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+
+/*
+ *  console_init_main():
+ *
+ *  Puts the host's console into single-character (non-canonical) mode.
+ */
+void console_init_main(struct emul *emul)
+{
+	int i, tra;
+
+	if (console_initialized)
+		return;
+
+	tcgetattr(STDIN_FILENO, &console_oldtermios);
+	memcpy(&console_curtermios, &console_oldtermios,
+	    sizeof (struct termios));
+
+	console_curtermios.c_lflag &= ~ICANON;
+	console_curtermios.c_cc[VTIME] = 0;
+	console_curtermios.c_cc[VMIN] = 1;
+
+	console_curtermios.c_lflag &= ~ECHO;
+
+	/*
+	 *  Most guest OSes seem to work ok without ~ICRNL, but Linux on
+	 *  DECstation requires it to be usable.  Unfortunately, clearing
+	 *  out ICRNL makes tracing with '-t ... |more' akward, as you
+	 *  might need to use CTRL-J instead of the enter key.  Hence,
+	 *  this bit is only cleared if we're not tracing:
+	 */
+	tra = 0;
+	for (i=0; i<emul->n_machines; i++)
+		if (emul->machines[i]->show_trace_tree ||
+		    emul->machines[i]->instruction_trace ||
+		    emul->machines[i]->register_dump)
+			tra = 1;
+	if (!tra)
+		console_curtermios.c_iflag &= ~ICRNL;
+
+	tcsetattr(STDIN_FILENO, TCSANOW, &console_curtermios);
+
+	console_stdout_pending = 1;
+	console_handles[MAIN_CONSOLE].fifo_head = 0;
+	console_handles[MAIN_CONSOLE].fifo_tail = 0;
+
+	console_mouse_dx = 0;
+	console_mouse_dy = 0;
+	console_mouse_buttons = 0;
+
+	console_initialized = 1;
+}
+
+
+/*
+ *  console_debug_dump():
+ *
+ *  Dump debug info, if verbose >= 2.
+ */
+void console_debug_dump(struct machine *machine)
+{
+	int i, iadd = 1, listed_main = 0;
+
+	if (verbose < 2)
+		return;
+
+	debug("console slaves (xterms): %s\n", allow_slaves?
+	    "yes" : "no");
+
+	debug("console handles:\n");
+	debug_indentation(iadd);
+
+	for (i=0; i<n_console_handles; i++) {
+		if (!console_handles[i].in_use)
+			continue;
+		debug("%i: \"%s\"", i, console_handles[i].name);
+		if (console_handles[i].using_xterm)
+			debug(" [xterm]");
+		if (console_handles[i].inputonly)
+			debug(" [inputonly]");
+		if (console_handles[i].outputonly)
+			debug(" [outputonly]");
+		if (i == machine->main_console_handle) {
+			debug(" [MAIN CONSOLE]");
+			listed_main = 1;
+		}
+		debug("\n");
+	}
+
+	debug_indentation(-iadd);
+
+	if (!listed_main)
+		fatal("WARNING! no main console handle?\n");
+}
+
+
+/*
+ *  console_allow_slaves():
+ *
+ *  This function tells the console subsystem whether or not to open up
+ *  slave xterms for each emulated serial controller.
+ */
+void console_allow_slaves(int allow)
+{
+	allow_slaves = allow;
+
+	if (allow_slaves) {
+		for (int i = 0; i < n_console_handles; i++)
+			if (i != MAIN_CONSOLE)
+				console_handles[i].using_xterm = USING_XTERM_BUT_NOT_YET_OPEN;
+	}
+}
+
+
+/*
+ *  console_are_slaves_allowed():
+ *
+ *  Returns the value of allow_slaves.
+ */
+int console_are_slaves_allowed(void)
+{
+	return allow_slaves;
+}
+
+
+/*
+ *  console_warn_if_slaves_are_needed():
+ *
+ *  Prints an error (during startup of the emulator) if slave xterms are needed
+ *  (i.e. there is more than one console handle in use which is used for
+ *  INPUT), but they are not currently allowed.
+ *
+ *  This function should be called during startup (with init = 1), and every
+ *  time a console handle changes/upgrades its in_use_for_input from 0 to 1.
+ *
+ *  If init is non-zero, this function doesn't return if there was a warning.
+ *
+ *  If init is zero, no warning is printed. 1 is returned if there were more
+ *  than one input, 0 otherwise.
+ */
+int console_warn_if_slaves_are_needed(int init)
+{
+	int i, n = 0;
+
+	if (allow_slaves)
+		return 0;
+
+	for (i=MAIN_CONSOLE+1; i<n_console_handles; i++)
+		if (console_handles[i].in_use &&
+		    console_handles[i].in_use_for_input &&
+		    !console_handles[i].using_xterm)
+			n ++;
+
+	if (n > 1) {
+		if (init) {
+			fatal("#\n#  ERROR! More than one console input is "
+			    "in use,\n#  but xterm slaves are not enabled.\n"
+			    "#\n");
+			fatal("#  Use -x to enable slave xterms.)\n#\n");
+			for (i=MAIN_CONSOLE+1; i<n_console_handles; i++)
+				if (console_handles[i].in_use &&
+				    console_handles[i].in_use_for_input &&
+				    !console_handles[i].using_xterm)
+					fatal("#  console handle %i: '%s'\n",
+					    i, console_handles[i].name);
+			fatal("#\n");
+			exit(1);
+		}
+		return 1;
+	}
+
+	return 0;
+}
+
+
+/*
+ *  console_init():
+ *
+ *  This function should be called before any other console_*() function
+ *  is used.
+ */
+void console_init(void)
+{
+	int handle;
+	struct console_handle *chp;
+
+	console_settings = settings_new();
+
+	settings_add(global_settings, "console", 1,
+            SETTINGS_TYPE_SUBSETTINGS, 0, console_settings);
+
+	settings_add(console_settings, "allow_slaves", 0,
+            SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO, (void *)&allow_slaves);
+
+	chp = console_new_handle("MAIN", &handle);
+	if (handle != MAIN_CONSOLE) {
+		printf("console_init(): fatal error: could not create"
+		    " console 0: handle = %i\n", handle);
+		exit(1);
+	}
+
+	chp->in_use_for_input = 1;
+}
+
+
+/*
+ *  console_deinit():
+ *
+ *  Unregister settings registered by console_init().
+ */
+void console_deinit(void)
+{
+	settings_remove(console_settings, "allow_slaves");
+	settings_remove(global_settings, "console");
+}
+
diff -Nru gxemul-0.6.2/src/console/console.cc gxemul-0.7.0+dfsg/src/console/console.cc
--- gxemul-0.6.2/src/console/console.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/console/console.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,992 +0,0 @@
-/*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Generic console support functions.
- *
- *  This module is used by individual device drivers, for example serial
- *  controllers, keyboards, or other devices which need to attach to the
- *  emulator's real stdin/stdout.
- *
- *  The idea is that several input and output streams (console handles) are
- *  allowed. As long as the number of input streams is <= 1, then everything
- *  can be done in the emulator's default terminal window.
- *
- *  If the number of inputs is more than 1, it is necessary to open up slave
- *  xterm windows for each input. (Otherwise the behaviour is undefined; i.e.
- *  which of two emulated serial controllers would get keyboard input?)
- *
- *  (If the -x command line option is NOT used, then slaves are not opened up.
- *  Instead, a warning message is printed, and input is not allowed.)
- *
- *  Note that console handles that _allow_ input but are not yet used for
- *  output are not counted. This allows a machine to have, say, 2 serial ports
- *  which can be used for both input and output, and it will still be possible
- *  to run in the default terminal window as long as only one of those serial
- *  ports is actually used.
- *
- *  xterms are opened up "on demand", when output is sent to them.
- *
- *  The MAIN console handle (fixed as handle nr 0) is the one used by the
- *  default terminal window. A machine which registers a serial controller,
- *  which should be used as the main way of communicating with guest operating
- *  systems running on that machine, should set machine->main_console_handle
- *  to the handle of the correct port on that controller.
- *
- *
- *  NOTE: The code in this module is mostly non-reentrant.
- */
-
-#include <errno.h>
-#include <signal.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <termios.h>
-#include <unistd.h>
-#include <sys/select.h>
-#include <sys/types.h>
-#include <time.h>
-
-#include "console.h"
-#include "emul.h"
-#include "machine.h"
-#include "settings.h"
-
-
-extern char *progname;
-extern int verbose;
-extern struct settings *global_settings;
-
-
-static struct termios console_oldtermios;
-static struct termios console_curtermios;
-
-/*  For 'slave' mode:  */
-static struct termios console_slave_tios;
-static int console_slave_outputd;
-
-static int console_initialized = 0;
-static struct settings *console_settings = NULL;
-static int console_stdout_pending;
-
-#define	CONSOLE_FIFO_LEN	4096
-
-static int console_mouse_x;		/*  absolute x, 0-based  */
-static int console_mouse_y;		/*  absolute y, 0-based  */
-static int console_mouse_fb_nr;		/*  framebuffer number of
-					    host movement, 0-based  */
-static int console_mouse_buttons;	/*  left=4, middle=2, right=1  */
-
-static int allow_slaves = 0;
-
-struct console_handle {
-	int		in_use;
-	int		in_use_for_input;
-	int		using_xterm;
-	int		inputonly;
-	int		outputonly;
-	int		warning_printed;
-
-	char		*machine_name;
-	char		*name;
-
-	int		w_descriptor;
-	int		r_descriptor;
-
-	unsigned char	fifo[CONSOLE_FIFO_LEN];
-	int		fifo_head;
-	int		fifo_tail;
-};
-
-#define	NOT_USING_XTERM				0
-#define	USING_XTERM_BUT_NOT_YET_OPEN		1
-#define	USING_XTERM				2
-
-/*  A simple array of console_handles  */
-static struct console_handle *console_handles = NULL;
-static int n_console_handles = 0;
-
-
-/*
- *  console_deinit_main():
- *
- *  Restore host's console settings.
- */
-void console_deinit_main(void)
-{
-	if (!console_initialized)
-		return;
-
-	tcsetattr(STDIN_FILENO, TCSANOW, &console_oldtermios);
-
-	console_initialized = 0;
-}
-
-
-/*
- *  console_sigcont():
- *
- *  If the user presses CTRL-Z (to stop the emulator process) and then
- *  continues, the termios settings might have been invalidated. This
- *  function restores them.
- *
- *  (This function should be set as the SIGCONT signal handler in src/emul.c.)
- */
-void console_sigcont(int x)
-{
-	if (!console_initialized)
-		return;
-
-	/*  Make sure that the correct (current) termios setting is active:  */
-	tcsetattr(STDIN_FILENO, TCSANOW, &console_curtermios);
-
-	/*  Reset the signal handler:  */
-	signal(SIGCONT, console_sigcont);
-}
-
-
-/*
- *  start_xterm():
- *
- *  When using X11 (well, when allow_slaves is set), this routine tries to
- *  start up an xterm, with another copy of gxemul inside. The other gxemul
- *  copy is given arguments that will cause it to run console_slave().
- *
- *  TODO: This is ugly and hardcoded. Clean it up.
- */
-static void start_xterm(int handle)
-{
-	int filedes[2];
-	int filedesB[2];
-	int res;
-	size_t mlen;
-	char **a;
-	pid_t p;
-
-	res = pipe(filedes);
-	if (res) {
-		printf("[ start_xterm(): pipe(): %i ]\n", errno);
-		exit(1);
-	}
-
-	res = pipe(filedesB);
-	if (res) {
-		printf("[ start_xterm(): pipe(): %i ]\n", errno);
-		exit(1);
-	}
-
-	/*  printf("filedes = %i,%i\n", filedes[0], filedes[1]);  */
-	/*  printf("filedesB = %i,%i\n", filedesB[0], filedesB[1]);  */
-
-	/*  NOTE/warning: Hardcoded max nr of args!  */
-	CHECK_ALLOCATION(a = (char **) malloc(sizeof(char *) * 20));
-
-	a[0] = getenv("XTERM");
-	if (a[0] == NULL)
-		a[0] = strdup("xterm");
-	a[1] = strdup("-geometry");
-	a[2] = strdup("80x25");
-	a[3] = strdup("-title");
-	mlen = strlen(console_handles[handle].name) +
-	    strlen(console_handles[handle].machine_name) + 30;
-	CHECK_ALLOCATION(a[4] = (char *) malloc(mlen));
-	snprintf(a[4], mlen, "GXemul: %s %s",
-	    console_handles[handle].machine_name,
-	    console_handles[handle].name);
-	a[5] = strdup("-e");
-	a[6] = progname;
-	CHECK_ALLOCATION(a[7] = (char *) malloc(80));
-	snprintf(a[7], 80, "-WW@S%i,%i", filedes[0], filedesB[1]);
-	a[8] = NULL;
-
-	p = fork();
-	if (p == -1) {
-		printf("[ start_xterm(): ERROR while trying to "
-		    "fork(): %i ]\n", errno);
-		exit(1);
-	} else if (p == 0) {
-		close(filedes[1]);
-		close(filedesB[0]);
-
-		p = setsid();
-		if (p < 0)
-			printf("[ start_xterm(): ERROR while trying "
-			    "to do a setsid(): %i ]\n", errno);
-
-		res = execvp(a[0], a);
-		printf("[ start_xterm(): ERROR while trying to "
-		    "execvp(\"");
-		while (a[0] != NULL) {
-			printf("%s", a[0]);
-			if (a[1] != NULL)
-				printf(" ");
-			a++;
-		}
-		printf("\"): %i ]\n", errno);
-		if (errno == ENOENT)
-			printf("[ Most probably you don't have xterm"
-			    " in your PATH. Try again. ]\n");
-		exit(1);
-	}
-
-	/*  TODO: free a and a[*]  */
-
-	close(filedes[0]);
-	close(filedesB[1]);
-
-	console_handles[handle].using_xterm = USING_XTERM;
-
-	/*
-	 *  write to filedes[1], read from filedesB[0]
-	 */
-
-	console_handles[handle].w_descriptor = filedes[1];
-	console_handles[handle].r_descriptor = filedesB[0];
-}
-
-
-/*
- *  d_avail():
- *
- *  Returns 1 if anything is available on a descriptor.
- */
-static int d_avail(int d)
-{
-	fd_set rfds;
-	struct timeval tv;
-
-	FD_ZERO(&rfds);
-	FD_SET(d, &rfds);
-	tv.tv_sec = 0;
-	tv.tv_usec = 0;
-	return select(d+1, &rfds, NULL, NULL, &tv);
-}
-
-
-/*
- *  console_makeavail():
- *
- *  Put a character in the queue, so that it will be avaiable,
- *  by inserting it into the char fifo.
- */
-void console_makeavail(int handle, char ch)
-{
-	console_handles[handle].fifo[
-	    console_handles[handle].fifo_head] = ch;
-	console_handles[handle].fifo_head = (
-	    console_handles[handle].fifo_head + 1) % CONSOLE_FIFO_LEN;
-
-	if (console_handles[handle].fifo_head ==
-	    console_handles[handle].fifo_tail)
-		fatal("[ WARNING: console fifo overrun, handle %i ]\n", handle);
-}
-
-
-/*
- *  console_stdin_avail():
- *
- *  Returns 1 if a char is available from a handle's read descriptor,
- *  0 otherwise.
- */
-static int console_stdin_avail(int handle)
-{
-	if (!console_handles[handle].in_use_for_input)
-		return 0;
-
-	if (!allow_slaves)
-		return d_avail(STDIN_FILENO);
-
-	if (console_handles[handle].using_xterm ==
-	    USING_XTERM_BUT_NOT_YET_OPEN)
-		return 0;
-
-	return d_avail(console_handles[handle].r_descriptor);
-}
-
-
-static int console_room_left_in_fifo(int handle)
-{
-	int roomLeftInFIFO = console_handles[handle].fifo_tail
-	    - console_handles[handle].fifo_head;
-	if (roomLeftInFIFO <= 0)
-		roomLeftInFIFO += CONSOLE_FIFO_LEN;
-
-	return roomLeftInFIFO;
-}
-
-
-/*
- *  console_charavail():
- *
- *  Returns the number of chararacters available in the fifo.
- */
-int console_charavail(int handle)
-{
-	while (console_stdin_avail(handle)) {
-		unsigned char ch[100];		/* = getchar(); */
-		ssize_t len;
-		int i, d;
-
-		// If adding more would lead to a full FIFO, then let's
-		// wait.
-		int roomLeftInFIFO = console_room_left_in_fifo(handle);
-		if (roomLeftInFIFO < (int)sizeof(ch) + 1)
-			break;
-
-		if (!allow_slaves)
-			d = STDIN_FILENO;
-		else
-			d = console_handles[handle].r_descriptor;
-
-		len = read(d, ch, sizeof(ch));
-
-		for (i=0; i<len; i++) {
-			/*  printf("[ %i: %i ]\n", i, ch[i]);  */
-
-			if (!allow_slaves) {
-				/*  Ugly hack: convert ctrl-b into ctrl-c.
-				    (TODO: fix)  */
-				if (ch[i] == 2)
-					ch[i] = 3;
-			}
-
-			console_makeavail(handle, ch[i]);
-		}
-	}
-
-	return CONSOLE_FIFO_LEN - console_room_left_in_fifo(handle);
-}
-
-
-/*
- *  console_readchar():
- *
- *  Returns 0..255 if a char was available, -1 otherwise.
- */
-int console_readchar(int handle)
-{
-	int ch;
-
-	if (!console_charavail(handle))
-		return -1;
-
-	ch = console_handles[handle].fifo[console_handles[handle].fifo_tail];
-	console_handles[handle].fifo_tail ++;
-	console_handles[handle].fifo_tail %= CONSOLE_FIFO_LEN;
-
-	return ch;
-}
-
-
-/*
- *  console_putchar():
- *
- *  Prints a char to stdout, and sets the console_stdout_pending flag.
- */
-void console_putchar(int handle, int ch)
-{
-	char buf[1];
-
-	if (!console_handles[handle].in_use_for_input &&
-	    !console_handles[handle].outputonly)
-		console_change_inputability(handle, 1);
-
-	if (!allow_slaves) {
-		/*  stdout:  */
-		putchar(ch);
-
-		/*  Assume flushes by OS or libc on newlines:  */
-		if (ch == '\n')
-			console_stdout_pending = 0;
-		else
-			console_stdout_pending = 1;
-
-		return;
-	}
-
-	if (!console_handles[handle].in_use) {
-		printf("[ console_putchar(): handle %i not in"
-		    " use! ]\n", handle);
-		return;
-		}
-
-	if (console_handles[handle].using_xterm ==
-	    USING_XTERM_BUT_NOT_YET_OPEN)
-		start_xterm(handle);
-
-	buf[0] = ch;
-	if (write(console_handles[handle].w_descriptor, buf, 1) != 1)
-		perror("error writing to console handle");
-}
-
-
-/*
- *  console_flush():
- *
- *  Flushes stdout, if necessary, and resets console_stdout_pending to zero.
- */
-void console_flush(void)
-{
-	if (console_stdout_pending)
-		fflush(stdout);
-
-	console_stdout_pending = 0;
-}
-
-
-/*
- *  console_mouse_coordinates():
- *
- *  Sets mouse coordinates. Called by for example an X11 event handler.
- *  x and y are absolute coordinates, fb_nr is where the mouse movement
- *  took place.
- */
-void console_mouse_coordinates(int x, int y, int fb_nr)
-{
-	/*  TODO: fb_nr isn't used yet.  */
-
-	console_mouse_x = x;
-	console_mouse_y = y;
-	console_mouse_fb_nr = fb_nr;
-}
-
-
-/*
- *  console_mouse_button():
- *
- *  Sets a mouse button to be pressed or released. Called by for example an
- *  X11 event handler.  button is 1 (left), 2 (middle), or 3 (right), and
- *  pressed = 1 for pressed, 0 for not pressed.
- */
-void console_mouse_button(int button, int pressed)
-{
-	int mask = 1 << (3-button);
-
-	if (pressed)
-		console_mouse_buttons |= mask;
-	else
-		console_mouse_buttons &= ~mask;
-}
-
-
-/*
- *  console_getmouse():
- *
- *  Puts current mouse data into the variables pointed to by
- *  the arguments.
- */
-void console_getmouse(int *x, int *y, int *buttons, int *fb_nr)
-{
-	*x = console_mouse_x;
-	*y = console_mouse_y;
-	*buttons = console_mouse_buttons;
-	*fb_nr = console_mouse_fb_nr;
-}
-
-
-/*
- *  console_slave_sigint():
- */
-static void console_slave_sigint(int x)
-{
-	char buf[1];
-
-	/*  Send a ctrl-c:  */
-	buf[0] = 3;
-	if (write(console_slave_outputd, buf, sizeof(buf)) != sizeof(buf))
-		perror("error writing to console handle");
-
-	/*  Reset the signal handler:  */
-	signal(SIGINT, console_slave_sigint);
-}
-
-
-/*
- *  console_slave_sigcont():
- *
- *  See comment for console_sigcont. This is for used by console_slave().
- */
-static void console_slave_sigcont(int x)
-{
-	/*  Make sure our 'current' termios setting is active:  */
-	tcsetattr(STDIN_FILENO, TCSANOW, &console_slave_tios);
-
-	/*  Reset the signal handler:  */
-	signal(SIGCONT, console_slave_sigcont);
-}
-
-
-/*
- *  console_slave():
- *
- *  This function is used when running with X11, and gxemul opens up
- *  separate xterms for each emulated terminal or serial port.
- */
-void console_slave(const char *arg)
-{
-	int inputd;
-	int len;
-	const char *p;
-	char buf[16384];
-
-	/*  arg = '3,6' or similar, input and output descriptors  */
-	/*  printf("console_slave(): arg = '%s'\n", arg);  */
-
-	inputd = atoi(arg);
-	p = strchr(arg, ',');
-	if (p == NULL) {
-		printf("console_slave(): bad arg '%s'\n", arg);
-		sleep(5);
-		exit(1);
-	}
-	console_slave_outputd = atoi(p+1);
-
-	/*  Set the terminal to raw mode:  */
-	tcgetattr(STDIN_FILENO, &console_slave_tios);
-
-	console_slave_tios.c_lflag &= ~ICANON;
-	console_slave_tios.c_cc[VTIME] = 0;
-	console_slave_tios.c_cc[VMIN] = 1;
-	console_slave_tios.c_lflag &= ~ECHO;
-	console_slave_tios.c_iflag &= ~ICRNL;
-	tcsetattr(STDIN_FILENO, TCSANOW, &console_slave_tios);
-
-	signal(SIGINT, console_slave_sigint);
-	signal(SIGCONT, console_slave_sigcont);
-
-	for (;;) {
-		/*  TODO: select() on both inputd and stdin  */
-
-		if (d_avail(inputd)) {
-			len = read(inputd, buf, sizeof(buf) - 1);
-			if (len < 1)
-				exit(0);
-			buf[len] = '\0';
-			printf("%s", buf);
-			fflush(stdout);
-		}
-
-		if (d_avail(STDIN_FILENO)) {
-			len = read(STDIN_FILENO, buf, sizeof(buf));
-			if (len < 1)
-				exit(0);
-			if (write(console_slave_outputd, buf, len) != len)
-				perror("error writing to console handle");
-		}
-
-		usleep(10000);
-	}
-}
-
-
-/*
- *  console_new_handle():
- *
- *  Allocates a new console_handle struct, and returns a pointer to it.
- *
- *  For internal use.
- */
-static struct console_handle *console_new_handle(const char *name, int *handlep)
-{
-	struct console_handle *chp;
-	int i, n, found_free = -1;
-
-	/*  Reuse an old slot, if possible:  */
-	n = n_console_handles;
-	for (i=0; i<n; i++)
-		if (!console_handles[i].in_use) {
-			found_free = i;
-			break;
-		}
-
-	if (found_free == -1) {
-		/*  Let's realloc console_handles[], to make room
-		    for the new one:  */
-		CHECK_ALLOCATION(console_handles = (struct console_handle *)
-		    realloc(console_handles, sizeof(
-		    struct console_handle) * (n_console_handles + 1)));
-		found_free = n_console_handles;
-		n_console_handles ++;
-	}
-
-	chp = &console_handles[found_free];
-	memset(chp, 0, sizeof(struct console_handle));
-
-	chp->in_use = 1;
-	chp->machine_name = strdup("");
-	CHECK_ALLOCATION(chp->name = strdup(name));
-
-	*handlep = found_free;
-	return chp;
-}
-
-
-/*
- *  console_start_slave():
- *
- *  When using X11:
- *
- *  This routine tries to start up an xterm, with another copy of gxemul
- *  inside. The other gxemul copy is given arguments that will cause it
- *  to run console_slave().
- *
- *  When not using X11:  Things will seem to work the same way without X11,
- *  but no xterm will actually be started.
- *
- *  consolename should be something like "serial 0".
- *
- *  If use_for_input is 1, input is allowed right from the start. (This
- *  can be upgraded later from 0 to 1 using the console_change_inputability()
- *  function.)
- *
- *  If use_for_input is CONSOLE_OUTPUT_ONLY, then this is an output-only stream.
- *
- *  On success, an integer >= 0 is returned. This can then be used as a
- *  'handle' when writing to or reading from an emulated console.
- *
- *  On failure, -1 is returned.
- */
-int console_start_slave(struct machine *machine, const char *consolename,
-	int use_for_input)
-{
-	struct console_handle *chp;
-	int handle;
-
-	if (machine == NULL || consolename == NULL) {
-		printf("console_start_slave(): NULL ptr\n");
-		exit(1);
-	}
-
-	chp = console_new_handle(consolename, &handle);
-	chp->in_use_for_input = use_for_input;
-	if (use_for_input == CONSOLE_OUTPUT_ONLY) {
-		chp->outputonly = 1;
-		chp->in_use_for_input = 0;
-	}
-
-	if (machine->machine_name != NULL) {
-		CHECK_ALLOCATION(chp->machine_name =
-		    strdup(machine->machine_name));
-	} else {
-		CHECK_ALLOCATION(chp->machine_name = strdup(""));
-	}
-
-	CHECK_ALLOCATION(chp->name = strdup(consolename));
-
-	if (allow_slaves)
-		chp->using_xterm = USING_XTERM_BUT_NOT_YET_OPEN;
-
-	return handle;
-}
-
-
-/*
- *  console_start_slave_inputonly():
- *
- *  Similar to console_start_slave(), but doesn't open an xterm. This is
- *  useful for devices such as keyboard controllers, that need to have an
- *  input queue, but no xterm window associated with it.
- *
- *  On success, an integer >= 0 is returned. This can then be used as a
- *  'handle' when writing to or reading from an emulated console.
- *
- *  On failure, -1 is returned.
- */
-int console_start_slave_inputonly(struct machine *machine, const char *consolename,
-	int use_for_input)
-{
-	struct console_handle *chp;
-	int handle;
-
-	if (machine == NULL || consolename == NULL) {
-		printf("console_start_slave(): NULL ptr\n");
-		exit(1);
-	}
-
-	chp = console_new_handle(consolename, &handle);
-	chp->inputonly = 1;
-	chp->in_use_for_input = use_for_input;
-
-	if (machine->name != NULL) {
-		CHECK_ALLOCATION(chp->machine_name = strdup(machine->name));
-	} else {
-		CHECK_ALLOCATION(chp->machine_name = strdup(""));
-	}
-
-	CHECK_ALLOCATION(chp->name = strdup(consolename));
-
-	return handle;
-}
-
-
-/*
- *  console_change_inputability():
- *
- *  Sets whether or not a console handle can be used for input. Return value
- *  is 1 if the change took place, 0 otherwise.
- */
-int console_change_inputability(int handle, int inputability)
-{
-	int old;
-
-	if (handle < 0 || handle >= n_console_handles) {
-		fatal("console_change_inputability(): bad handle %i\n",
-		    handle);
-		exit(1);
-	}
-
-	old = console_handles[handle].in_use_for_input;
-	console_handles[handle].in_use_for_input = inputability;
-
-	if (inputability != 0) {
-		if (console_warn_if_slaves_are_needed(0)) {
-			console_handles[handle].in_use_for_input = old;
-			if (!console_handles[handle].warning_printed) {
-				fatal("%%\n%%  WARNING! Input to console ha"
-				    "ndle \"%s\" wasn't enabled,\n%%  because "
-				    "it", console_handles[handle].name);
-				fatal(" would interfere with other inputs,\n"
-				    "%%  and you did not use the -x command "
-				    "line option!\n%%\n");
-			}
-			console_handles[handle].warning_printed = 1;
-			return 0;
-		}
-	}
-
-	return 1;
-}
-
-
-/*
- *  console_init_main():
- *
- *  Puts the host's console into single-character (non-canonical) mode.
- */
-void console_init_main(struct emul *emul)
-{
-	int i, tra;
-
-	if (console_initialized)
-		return;
-
-	tcgetattr(STDIN_FILENO, &console_oldtermios);
-	memcpy(&console_curtermios, &console_oldtermios,
-	    sizeof (struct termios));
-
-	console_curtermios.c_lflag &= ~ICANON;
-	console_curtermios.c_cc[VTIME] = 0;
-	console_curtermios.c_cc[VMIN] = 1;
-
-	console_curtermios.c_lflag &= ~ECHO;
-
-	/*
-	 *  Most guest OSes seem to work ok without ~ICRNL, but Linux on
-	 *  DECstation requires it to be usable.  Unfortunately, clearing
-	 *  out ICRNL makes tracing with '-t ... |more' akward, as you
-	 *  might need to use CTRL-J instead of the enter key.  Hence,
-	 *  this bit is only cleared if we're not tracing:
-	 */
-	tra = 0;
-	for (i=0; i<emul->n_machines; i++)
-		if (emul->machines[i]->show_trace_tree ||
-		    emul->machines[i]->instruction_trace ||
-		    emul->machines[i]->register_dump)
-			tra = 1;
-	if (!tra)
-		console_curtermios.c_iflag &= ~ICRNL;
-
-	tcsetattr(STDIN_FILENO, TCSANOW, &console_curtermios);
-
-	console_stdout_pending = 1;
-	console_handles[MAIN_CONSOLE].fifo_head = 0;
-	console_handles[MAIN_CONSOLE].fifo_tail = 0;
-
-	console_mouse_x = 0;
-	console_mouse_y = 0;
-	console_mouse_buttons = 0;
-
-	console_initialized = 1;
-}
-
-
-/*
- *  console_debug_dump():
- *
- *  Dump debug info, if verbose >= 2.
- */
-void console_debug_dump(struct machine *machine)
-{
-	int i, iadd = DEBUG_INDENTATION, listed_main = 0;
-
-	if (verbose < 2)
-		return;
-
-	debug("console slaves (xterms): %s\n", allow_slaves?
-	    "yes" : "no");
-
-	debug("console handles:\n");
-	debug_indentation(iadd);
-
-	for (i=0; i<n_console_handles; i++) {
-		if (!console_handles[i].in_use)
-			continue;
-		debug("%i: \"%s\"", i, console_handles[i].name);
-		if (console_handles[i].using_xterm)
-			debug(" [xterm]");
-		if (console_handles[i].inputonly)
-			debug(" [inputonly]");
-		if (console_handles[i].outputonly)
-			debug(" [outputonly]");
-		if (i == machine->main_console_handle) {
-			debug(" [MAIN CONSOLE]");
-			listed_main = 1;
-		}
-		debug("\n");
-	}
-
-	debug_indentation(-iadd);
-
-	if (!listed_main)
-		fatal("WARNING! no main console handle?\n");
-}
-
-
-/*
- *  console_allow_slaves():
- *
- *  This function tells the console subsystem whether or not to open up
- *  slave xterms for each emulated serial controller.
- */
-void console_allow_slaves(int allow)
-{
-	allow_slaves = allow;
-}
-
-
-/*
- *  console_are_slaves_allowed():
- *
- *  Returns the value of allow_slaves.
- */
-int console_are_slaves_allowed(void)
-{
-	return allow_slaves;
-}
-
-
-/*
- *  console_warn_if_slaves_are_needed():
- *
- *  Prints an error (during startup of the emulator) if slave xterms are needed
- *  (i.e. there is more than one console handle in use which is used for
- *  INPUT), but they are not currently allowed.
- *
- *  This function should be called during startup (with init = 1), and every
- *  time a console handle changes/upgrades its in_use_for_input from 0 to 1.
- *
- *  If init is non-zero, this function doesn't return if there was a warning.
- *
- *  If init is zero, no warning is printed. 1 is returned if there were more
- *  than one input, 0 otherwise.
- */
-int console_warn_if_slaves_are_needed(int init)
-{
-	int i, n = 0;
-
-	if (allow_slaves)
-		return 0;
-
-	for (i=MAIN_CONSOLE+1; i<n_console_handles; i++)
-		if (console_handles[i].in_use &&
-		    console_handles[i].in_use_for_input &&
-		    !console_handles[i].using_xterm)
-			n ++;
-
-	if (n > 1) {
-		if (init) {
-			fatal("#\n#  ERROR! More than one console input is "
-			    "in use,\n#  but xterm slaves are not enabled.\n"
-			    "#\n");
-			fatal("#  Use -x to enable slave xterms.)\n#\n");
-			for (i=MAIN_CONSOLE+1; i<n_console_handles; i++)
-				if (console_handles[i].in_use &&
-				    console_handles[i].in_use_for_input &&
-				    !console_handles[i].using_xterm)
-					fatal("#  console handle %i: '%s'\n",
-					    i, console_handles[i].name);
-			fatal("#\n");
-			exit(1);
-		}
-		return 1;
-	}
-
-	return 0;
-}
-
-
-/*
- *  console_init():
- *
- *  This function should be called before any other console_*() function
- *  is used.
- */
-void console_init(void)
-{
-	int handle;
-	struct console_handle *chp;
-
-	console_settings = settings_new();
-
-	settings_add(global_settings, "console", 1,
-            SETTINGS_TYPE_SUBSETTINGS, 0, console_settings);
-
-	settings_add(console_settings, "allow_slaves", 0,
-            SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO, (void *)&allow_slaves);
-
-	chp = console_new_handle("MAIN", &handle);
-	if (handle != MAIN_CONSOLE) {
-		printf("console_init(): fatal error: could not create"
-		    " console 0: handle = %i\n", handle);
-		exit(1);
-	}
-
-	chp->in_use_for_input = 1;
-}
-
-
-/*
- *  console_deinit():
- *
- *  Unregister settings registered by console_init().
- */
-void console_deinit(void)
-{
-	settings_remove(console_settings, "allow_slaves");
-	settings_remove(global_settings, "console");
-}
-
diff -Nru gxemul-0.6.2/src/console/Makefile.skel gxemul-0.7.0+dfsg/src/console/Makefile.skel
--- gxemul-0.6.2/src/console/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/console/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -5,7 +5,7 @@
 #  handling.
 #
 
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
+CFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
 
 OBJS=console.o x11.o
 
diff -Nru gxemul-0.6.2/src/console/x11.c gxemul-0.7.0+dfsg/src/console/x11.c
--- gxemul-0.6.2/src/console/x11.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/console/x11.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1004 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  X11-related functions.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "console.h"
+#include "emul.h"
+#include "machine.h"
+#include "misc.h"
+#include "x11.h"
+
+
+#ifndef	WITH_X11
+
+
+/*  Dummy functions:  */
+void x11_redraw_cursor(struct machine *m, int i) { }
+void x11_redraw(struct machine *m, int x) { }
+void x11_putpixel_fb(struct machine *m, int fb, int x, int y, int color) { }
+void x11_init(struct machine *machine) { }
+struct fb_window *x11_fb_init(int xsize, int ysize, char *name,
+	int scaledown, struct machine *machine)
+    { return NULL; }
+void x11_check_event(struct emul *emul) { }
+
+
+#else	/*  WITH_X11  */
+
+
+#include <X11/Xlib.h>
+#include <X11/Xutil.h>
+#include <X11/cursorfont.h>
+
+static bool left_ctrl = false;
+static bool left_alt = false;
+static struct fb_window *grabbed = NULL;
+static bool mouseExplicityMoved = false;
+static int mouseXbeforeGrab = 0;
+static int mouseYbeforeGrab = 0;
+static int mouseXofLastEvent = 0;
+static int mouseYofLastEvent = 0;
+
+static bool mouseCursorHidden = false;
+
+
+static void x11_unhide_cursor()
+{
+	if (!mouseCursorHidden)
+		return;
+
+	struct fb_window *fbwin = grabbed;
+
+	/*  Remove the old X11 host cursor:  */
+	XUndefineCursor(fbwin->x11_display, fbwin->x11_fb_window);
+	XFreeCursor(fbwin->x11_display, fbwin->host_cursor);
+	fbwin->host_cursor = 0;
+
+	mouseCursorHidden = false;
+}
+
+
+static void x11_hide_cursor()
+{
+	if (mouseCursorHidden)
+		return;
+
+	struct fb_window *fbwin = grabbed;
+
+	/*  Create a new "empy" X11 host cursor:  */
+	if (fbwin->host_cursor_pixmap != 0) {
+		XFreePixmap(fbwin->x11_display, fbwin->host_cursor_pixmap);
+		fbwin->host_cursor_pixmap = 0;
+	}
+
+	fbwin->host_cursor_pixmap = XCreatePixmap(fbwin->x11_display, fbwin->x11_fb_window, 1, 1, 1);
+	XSetForeground(fbwin->x11_display, fbwin->x11_fb_gc, fbwin->x11_graycolor[0].pixel);
+
+	GC tmpgc = XCreateGC(fbwin->x11_display, fbwin->host_cursor_pixmap, 0,0);
+
+	XDrawPoint(fbwin->x11_display, fbwin->host_cursor_pixmap, tmpgc, 0, 0);
+
+	XFreeGC(fbwin->x11_display, tmpgc);
+
+	fbwin->host_cursor =
+	    XCreatePixmapCursor(fbwin->x11_display,
+	    fbwin->host_cursor_pixmap,
+	    fbwin->host_cursor_pixmap,
+	    &fbwin->x11_graycolor[N_GRAYCOLORS-1],
+	    &fbwin->x11_graycolor[N_GRAYCOLORS-1],
+	    0, 0);
+
+	// For testing:
+	// fbwin->host_cursor = XCreateFontCursor(fbwin->x11_display, XC_coffee_mug);
+
+	if (fbwin->host_cursor != 0)
+		XDefineCursor(fbwin->x11_display, fbwin->x11_fb_window, fbwin->host_cursor);
+
+	mouseCursorHidden = true;
+}
+
+
+static void setMousePointerCoordinates(struct fb_window *fbwin, int x, int y)
+{
+	XWarpPointer(fbwin->x11_display, None,
+	    DefaultRootWindow(fbwin->x11_display), 0, 0, 0, 0, x, y);
+	XFlush(fbwin->x11_display);
+
+	mouseExplicityMoved = true;
+}
+
+
+static void mouseMouseToCenterOfScreen(struct fb_window *fbwin)
+{
+	Screen *screen = XDefaultScreenOfDisplay(fbwin->x11_display);
+
+	int screenWidth = XWidthOfScreen(screen);
+	int screenHeight = XHeightOfScreen(screen);
+	setMousePointerCoordinates(fbwin, screenWidth / 2, screenHeight / 2);
+}
+
+static void grab(struct fb_window *fbwin)
+{
+	if (grabbed != NULL)
+		return;
+
+	Window xqpWindow;
+	int rootx, rooty, x, y;
+	unsigned int mask;
+	int res = XQueryPointer(fbwin->x11_display,
+	    RootWindow(fbwin->x11_display, DefaultScreen(fbwin->x11_display)),
+	    &xqpWindow,
+            &xqpWindow, &rootx, &rooty, &x, &y,
+            &mask);
+        if (res != True)
+        	return;
+
+	debugmsg(SUBSYS_X11, "grab", VERBOSITY_DEBUG, "Mouse coordinates "
+	    "before grab: %i, %i", rootx, rooty);
+	mouseXbeforeGrab = rootx;
+	mouseYbeforeGrab = rooty;
+
+	res = XGrabPointer(fbwin->x11_display, fbwin->x11_fb_window, False,
+	    ButtonPressMask | ButtonReleaseMask | PointerMotionMask | FocusChangeMask |
+	    EnterWindowMask | LeaveWindowMask,
+	    GrabModeAsync, GrabModeAsync,
+	    RootWindow(fbwin->x11_display, DefaultScreen(fbwin->x11_display)),
+	    None, CurrentTime);
+
+	if (res == GrabSuccess)
+		grabbed = fbwin;
+
+	debugmsg(SUBSYS_X11, "grab", VERBOSITY_DEBUG, "Grab mouse pointer: %s",
+	    res == GrabSuccess ? "success" : "FAILURE");
+
+	if (res != GrabSuccess)
+		return;
+
+	x11_hide_cursor();
+
+	mouseMouseToCenterOfScreen(fbwin);
+
+	x11_set_standard_properties(fbwin);
+}
+
+
+static void ungrab()
+{
+	if (grabbed == NULL)
+		return;
+
+	struct fb_window *fbwin = grabbed;
+
+	x11_unhide_cursor();
+
+	grabbed = NULL;
+
+	x11_set_standard_properties(fbwin);
+
+	debugmsg(SUBSYS_X11, "grab", VERBOSITY_DEBUG, "Releasing grab.");
+
+	XUngrabPointer(fbwin->x11_display, CurrentTime);
+
+	setMousePointerCoordinates(fbwin, mouseXbeforeGrab, mouseYbeforeGrab);
+}
+
+
+/*
+ *  x11_redraw_cursor():
+ *
+ *  Redraw a framebuffer's X11 cursor.
+ *
+ *  NOTE: It is up to the caller to call XFlush.
+ */
+void x11_redraw_cursor(struct machine *m, int i)
+{
+	struct fb_window *fbwin = m->x11_md.fb_windows[i];
+
+	if (fbwin->x11_display == NULL)
+		return;
+
+	/*  Remove old cursor, if any:  */
+	if (fbwin->OLD_cursor_on) {
+		XPutImage(fbwin->x11_display, fbwin->x11_fb_window,
+		    fbwin->x11_fb_gc, fbwin->fb_ximage,
+		    fbwin->OLD_cursor_x/fbwin->scaledown,
+		    fbwin->OLD_cursor_y/fbwin->scaledown,
+		    fbwin->OLD_cursor_x/fbwin->scaledown,
+		    fbwin->OLD_cursor_y/fbwin->scaledown,
+		    fbwin->OLD_cursor_xsize/fbwin->scaledown + 1,
+		    fbwin->OLD_cursor_ysize/fbwin->scaledown + 1);
+	}
+
+	if (!fbwin->cursor_on)
+		return;
+
+	XImage *xtmp;
+	CHECK_ALLOCATION(xtmp = XSubImage(fbwin->fb_ximage,
+	    fbwin->cursor_x/fbwin->scaledown,
+	    fbwin->cursor_y/fbwin->scaledown,
+	    fbwin->cursor_xsize/fbwin->scaledown + 1,
+	    fbwin->cursor_ysize/fbwin->scaledown + 1));
+
+	for (int y = 0; y < fbwin->cursor_ysize; y += fbwin->scaledown) {
+		for (int x = 0; x < fbwin->cursor_xsize; x += fbwin->scaledown) {
+			int px = x/fbwin->scaledown;
+			int py = y/fbwin->scaledown;
+			int p = 0, n = 0, c = 0;
+			unsigned long oldcol;
+
+			for (int suby = 0; suby < fbwin->scaledown; suby++)
+				for (int subx = 0; subx < fbwin->scaledown; subx++) {
+					c = fbwin->cursor_pixels[y+suby][x+subx];
+					if (c >= 0) {
+						p += c;
+						n++;
+					}
+				}
+			if (n > 0)
+				p /= n;
+			else
+				p = c;
+
+			switch (p) {
+			case CURSOR_COLOR_TRANSPARENT:
+				break;
+
+			case CURSOR_COLOR_INVERT:
+				oldcol = XGetPixel(xtmp, px, py);
+				if (oldcol != fbwin->
+				    x11_graycolor[N_GRAYCOLORS-1].pixel)
+					oldcol = fbwin->x11_graycolor[N_GRAYCOLORS-1].pixel;
+				else
+					oldcol = fbwin->x11_graycolor[0].pixel;
+
+				XPutPixel(xtmp, px, py, oldcol);
+				break;
+
+			default:	/*  Normal grayscale:  */
+				XPutPixel(xtmp, px, py, fbwin->x11_graycolor[p].pixel);
+			}
+		}
+	}
+
+	XPutImage(fbwin->x11_display,
+	    fbwin->x11_fb_window,
+	    fbwin->x11_fb_gc,
+	    xtmp, 0, 0,
+	    fbwin->cursor_x/fbwin->scaledown,
+	    fbwin->cursor_y/fbwin->scaledown,
+	    fbwin->cursor_xsize/fbwin->scaledown,
+	    fbwin->cursor_ysize/fbwin->scaledown);
+
+	XDestroyImage(xtmp);
+
+	fbwin->OLD_cursor_on = fbwin->cursor_on;
+	fbwin->OLD_cursor_x = fbwin->cursor_x;
+	fbwin->OLD_cursor_y = fbwin->cursor_y;
+	fbwin->OLD_cursor_xsize = fbwin->cursor_xsize;
+	fbwin->OLD_cursor_ysize = fbwin->cursor_ysize;
+}
+
+
+/*
+ *  x11_redraw():
+ *
+ *  Redraw X11 windows.
+ */
+void x11_redraw(struct machine *m, int i)
+{
+	if (i < 0 || i >= m->x11_md.n_fb_windows ||
+	    m->x11_md.fb_windows[i]->x11_fb_winxsize <= 0)
+		return;
+
+	x11_putimage_fb(m, i);
+	x11_redraw_cursor(m, i);
+	XFlush(m->x11_md.fb_windows[i]->x11_display);
+}
+
+
+/*
+ *  x11_putpixel_fb():
+ *
+ *  Output a framebuffer pixel. i is the framebuffer number.
+ */
+void x11_putpixel_fb(struct machine *m, int i, int x, int y, int color)
+{
+	struct fb_window *fbwin;
+	if (i < 0 || i >= m->x11_md.n_fb_windows)
+		return;
+
+	fbwin = m->x11_md.fb_windows[i];
+
+	if (fbwin->x11_fb_winxsize <= 0)
+		return;
+
+	if (color)
+		XSetForeground(fbwin->x11_display,
+		    fbwin->x11_fb_gc, fbwin->fg_color);
+	else
+		XSetForeground(fbwin->x11_display,
+		    fbwin->x11_fb_gc, fbwin->bg_color);
+
+	XDrawPoint(fbwin->x11_display,
+	    fbwin->x11_fb_window, fbwin->x11_fb_gc, x, y);
+
+	XFlush(fbwin->x11_display);
+}
+
+
+/*
+ *  x11_putimage_fb():
+ *
+ *  Output an entire XImage to a framebuffer window. i is the
+ *  framebuffer number.
+ */
+void x11_putimage_fb(struct machine *m, int i)
+{
+	struct fb_window *fbwin;
+	if (i < 0 || i >= m->x11_md.n_fb_windows)
+		return;
+
+	fbwin = m->x11_md.fb_windows[i];
+
+	if (fbwin->x11_fb_winxsize <= 0)
+		return;
+
+	XPutImage(fbwin->x11_display,
+	    fbwin->x11_fb_window,
+	    fbwin->x11_fb_gc, fbwin->fb_ximage, 0,0, 0,0,
+	    fbwin->x11_fb_winxsize,
+	    fbwin->x11_fb_winysize);
+	XFlush(fbwin->x11_display);
+}
+
+
+/*
+ *  x11_init():
+ *
+ *  Initialize X11 stuff (but doesn't create any windows).
+ *
+ *  It is then up to individual drivers, for example framebuffer devices,
+ *  to initialize their own windows.
+ */
+void x11_init(struct machine *m)
+{
+	m->x11_md.n_fb_windows = 0;
+
+	if (m->x11_md.n_display_names > 0) {
+		int i;
+		for (i=0; i<m->x11_md.n_display_names; i++)
+			debugmsg(SUBSYS_X11, "init", VERBOSITY_INFO,
+			    "using X11 display: %s", m->x11_md.display_names[i]);
+	}
+
+	m->x11_md.current_display_name_nr = 0;
+}
+
+
+/*
+ *  x11_fb_resize():
+ *
+ *  Set a new size for an X11 framebuffer window.  (NOTE: I didn't think of
+ *  this kind of functionality during the initial design, so it is probably
+ *  buggy. It also needs some refactoring.)
+ */
+void x11_fb_resize(struct fb_window *win, int new_xsize, int new_ysize)
+{
+	int alloc_depth;
+
+	if (win == NULL) {
+		debugmsg(SUBSYS_X11, "resize", VERBOSITY_ERROR, "win == NULL");
+		return;
+	}
+
+	win->x11_fb_winxsize = new_xsize;
+	win->x11_fb_winysize = new_ysize;
+
+	alloc_depth = win->x11_screen_depth;
+	if (alloc_depth == 24)
+		alloc_depth = 32;
+	if (alloc_depth == 15)
+		alloc_depth = 16;
+
+	/*  Note: ximage_data seems to be freed by XDestroyImage below.  */
+	/*  if (win->ximage_data != NULL)
+		free(win->ximage_data);  */
+	CHECK_ALLOCATION(win->ximage_data = (unsigned char *) malloc(
+	    new_xsize * new_ysize * alloc_depth / 8));
+
+	/*  TODO: clear for non-truecolor modes  */
+	memset(win->ximage_data, 0, new_xsize * new_ysize * alloc_depth / 8);
+
+	if (win->fb_ximage != NULL)
+		XDestroyImage(win->fb_ximage);
+	win->fb_ximage = XCreateImage(win->x11_display, CopyFromParent,
+	    win->x11_screen_depth, ZPixmap, 0, (char *)win->ximage_data,
+	    new_xsize, new_ysize, 8, new_xsize * alloc_depth / 8);
+	CHECK_ALLOCATION(win->fb_ximage);
+
+	XResizeWindow(win->x11_display, win->x11_fb_window,
+	    new_xsize, new_ysize);
+}
+
+
+/*
+ *  x11_set_standard_properties():
+ *
+ *  Right now, this only sets the title of a window.
+ */
+void x11_set_standard_properties(struct fb_window *fb_window)
+{
+	size_t title_maxlen = strlen(fb_window->name) + 100;
+	char *title;
+	CHECK_ALLOCATION(title = malloc(title_maxlen));
+
+	snprintf(title, title_maxlen, "%s%s", fb_window->name,
+	    grabbed != NULL ? " (Left CTRL+ALT to ungrab)" : "");
+
+	XSetStandardProperties(fb_window->x11_display,
+	    fb_window->x11_fb_window, title, "GXemul " VERSION,
+	    None, NULL, 0, NULL);
+
+	free(title);
+}
+
+
+/*
+ *  x11_fb_init():
+ *
+ *  Initialize a framebuffer window.
+ */
+struct fb_window *x11_fb_init(int xsize, int ysize, char *name,
+	int scaledown, struct machine *m)
+{
+	Display *x11_display;
+	int x, y, fb_number = 0;
+	size_t alloclen, alloc_depth;
+	XColor tmpcolor;
+	struct fb_window *fbwin;
+	int i;
+	char fg[80], bg[80];
+	char *display_name;
+
+	fb_number = m->x11_md.n_fb_windows;
+
+	CHECK_ALLOCATION(m->x11_md.fb_windows = 
+	    (struct fb_window **) realloc(m->x11_md.fb_windows,
+	    sizeof(struct fb_window *) * (m->x11_md.n_fb_windows + 1)));
+	CHECK_ALLOCATION(fbwin = m->x11_md.fb_windows[fb_number] =
+	    (struct fb_window *) malloc(sizeof(struct fb_window)));
+
+	m->x11_md.n_fb_windows ++;
+
+	memset(fbwin, 0, sizeof(struct fb_window));
+
+	fbwin->x11_fb_winxsize = xsize;
+	fbwin->x11_fb_winysize = ysize;
+
+	/*  Which display name?  */
+	display_name = NULL;
+	if (m->x11_md.n_display_names > 0) {
+		display_name = m->x11_md.display_names[
+		    m->x11_md.current_display_name_nr];
+		m->x11_md.current_display_name_nr ++;
+		m->x11_md.current_display_name_nr %= m->x11_md.n_display_names;
+	}
+
+	if (display_name != NULL)
+		debugmsg(SUBSYS_X11, "fb_init", VERBOSITY_INFO,
+		    "framebuffer window %i, %ix%i, DISPLAY"
+		    "=%s", fb_number, xsize, ysize, display_name);
+
+	x11_display = XOpenDisplay(display_name);
+
+	if (x11_display == NULL) {
+		debugmsg(SUBSYS_X11, "fb_init", VERBOSITY_ERROR,
+		    "couldn't open display '%s'", name);
+		if (display_name != NULL)
+			debugmsg(SUBSYS_X11, "fb_init", VERBOSITY_ERROR, "display_name = '%s'", display_name);
+
+		exit(1);
+	}
+
+	fbwin->x11_screen =
+	    DefaultScreen(x11_display);
+	fbwin->x11_screen_depth =
+	    DefaultDepth(x11_display,
+	    fbwin->x11_screen);
+
+	if (fbwin->x11_screen_depth != 8 &&
+	    fbwin->x11_screen_depth != 15 &&
+	    fbwin->x11_screen_depth != 16 &&
+	    fbwin->x11_screen_depth != 24) {
+		debugmsg(SUBSYS_X11, "fb_init", VERBOSITY_WARNING,
+		    "***\n***  WARNING! Your X server is running %i-bit "
+		    "color mode. This is not really\n",
+		    "***  supported yet.  8, 15, 16, and 24 bits should "
+		    "work.\n***  24-bit server gives color.  Any other bit "
+		    "depth gives undefined result!\n***",
+		    fbwin->x11_screen_depth);
+	}
+
+	if (fbwin->x11_screen_depth <= 8)
+		debugmsg(SUBSYS_X11, "fb_init", VERBOSITY_WARNING,
+		    "screen depth is not enough for color; "
+		    "using only 16 grayscales instead");
+
+	strlcpy(bg, "Black", sizeof(bg));
+	strlcpy(fg, "White", sizeof(fg));
+
+	XParseColor(x11_display, DefaultColormap(x11_display,
+	    fbwin->x11_screen), fg, &tmpcolor);
+	XAllocColor(x11_display, DefaultColormap(x11_display,
+	    fbwin->x11_screen), &tmpcolor);
+	fbwin->fg_color = tmpcolor.pixel;
+	XParseColor(x11_display, DefaultColormap(x11_display,
+	    fbwin->x11_screen), bg, &tmpcolor);
+	XAllocColor(x11_display, DefaultColormap(x11_display,
+	    fbwin->x11_screen), &tmpcolor);
+	fbwin->bg_color = tmpcolor.pixel;
+
+	for (i=0; i<N_GRAYCOLORS; i++) {
+		char cname[8];
+		cname[0] = '#';
+		cname[1] = cname[2] = cname[3] =
+		    cname[4] = cname[5] = cname[6] =
+		    "0123456789ABCDEF"[i];
+		cname[7] = '\0';
+		XParseColor(x11_display, DefaultColormap(x11_display,
+		    fbwin->x11_screen), cname,
+		    &fbwin->x11_graycolor[i]);
+		XAllocColor(x11_display, DefaultColormap(x11_display,
+		    fbwin->x11_screen),
+		    &fbwin->x11_graycolor[i]);
+	}
+
+        XFlush(x11_display);
+
+	alloc_depth = fbwin->x11_screen_depth;
+
+	if (alloc_depth == 24)
+		alloc_depth = 32;
+	if (alloc_depth == 15)
+		alloc_depth = 16;
+
+	fbwin->x11_fb_window = XCreateWindow(
+	    x11_display, DefaultRootWindow(x11_display),
+	    0, 0, fbwin->x11_fb_winxsize,
+	    fbwin->x11_fb_winysize,
+	    0, CopyFromParent, InputOutput, CopyFromParent, 0,0);
+
+	fbwin->x11_display = x11_display;
+
+	fbwin->name = strdup(name);
+
+	x11_set_standard_properties(fbwin);
+
+	XSelectInput(x11_display,
+	    fbwin->x11_fb_window,
+	    StructureNotifyMask | ExposureMask | ButtonPressMask | FocusChangeMask |
+	    ButtonReleaseMask | PointerMotionMask | KeyPressMask | KeyReleaseMask);
+	fbwin->x11_fb_gc = XCreateGC(x11_display,
+	    fbwin->x11_fb_window, 0,0);
+
+	/*  Make sure the window is mapped:  */
+	XMapRaised(x11_display, fbwin->x11_fb_window);
+
+	XSetBackground(x11_display, fbwin->x11_fb_gc, fbwin->bg_color);
+	XSetForeground(x11_display, fbwin->x11_fb_gc, fbwin->bg_color);
+	XFillRectangle(x11_display, fbwin->x11_fb_window, fbwin->x11_fb_gc, 0,0,
+	    fbwin->x11_fb_winxsize, fbwin->x11_fb_winysize);
+
+	fbwin->scaledown   = scaledown;
+
+	fbwin->fb_number = fb_number;
+
+	alloclen = xsize * ysize * alloc_depth / 8;
+	CHECK_ALLOCATION(fbwin->ximage_data = (unsigned char *) malloc(alloclen));
+
+	fbwin->fb_ximage = XCreateImage(fbwin->x11_display, CopyFromParent,
+	    fbwin->x11_screen_depth, ZPixmap, 0, (char *)fbwin->ximage_data,
+	    xsize, ysize, 8, xsize * alloc_depth / 8);
+	CHECK_ALLOCATION(fbwin->fb_ximage);
+
+	/*  Fill the ximage with black pixels:  */
+	if (fbwin->x11_screen_depth > 8)
+		memset(fbwin->ximage_data, 0, alloclen);
+	else {
+		debugmsg(SUBSYS_X11, "fb_init", VERBOSITY_DEBUG,
+		    "clearing the XImage\n");
+		for (y=0; y<ysize; y++)
+			for (x=0; x<xsize; x++)
+				XPutPixel(fbwin->fb_ximage, x, y,
+				    fbwin->x11_graycolor[0].pixel);
+	}
+
+	x11_putimage_fb(m, fb_number);
+
+	/*  Fill the 64x64 "hardware" cursor with white pixels:  */
+	xsize = ysize = 64;
+
+	/*  Fill the cursor ximage with white pixels:  */
+	for (y=0; y<ysize; y++)
+		for (x=0; x<xsize; x++)
+			fbwin->cursor_pixels[y][x] = N_GRAYCOLORS-1;
+
+	return fbwin;
+}
+
+
+/*
+ *  x11_check_events_machine():
+ *
+ *  Check for X11 events on a specific machine.
+ *
+ *  TODO:  Yuck! This has to be rewritten. Each display should be checked,
+ *         and _then_ only those windows that are actually exposed should
+ *         be redrawn!
+ */
+static void x11_check_events_machine(struct emul *emul, struct machine *m)
+{
+	int fb_nr;
+
+	for (fb_nr = 0; fb_nr < m->x11_md.n_fb_windows; fb_nr ++) {
+		struct fb_window *fbwin = m->x11_md.fb_windows[fb_nr];
+		XEvent event;
+		bool need_redraw = false;
+
+		while (XPending(fbwin->x11_display)) {
+			XNextEvent(fbwin->x11_display, &event);
+
+			if (event.type == ConfigureNotify) {
+				need_redraw = true;
+			}
+
+			if (event.type == FocusOut)
+				ungrab();
+
+			if (event.type == Expose && event.xexpose.count == 0) {
+				/*
+				 *  TODO:  the xexpose struct has x,y,width,
+				 *  height. Those could be used to only redraw
+				 *  the part of the framebuffer that was
+				 *  exposed. Note that the (mouse) cursor must
+				 *  be redrawn too.
+				 */
+				/*  x11_winxsize = event.xexpose.width;
+				    x11_winysize = event.xexpose.height;  */
+				need_redraw = true;
+			}
+
+			if (event.type == MotionNotify && mouseExplicityMoved) {
+				// debugmsg(SUBSYS_X11, "event", VERBOSITY_WARNING,
+				//    "mouse explicitly moved to screen center; ignored.");
+
+				mouseExplicityMoved = false;
+
+				mouseXofLastEvent = event.xmotion.x;
+				mouseYofLastEvent = event.xmotion.y;
+
+			} else if (event.type == MotionNotify) {
+				// debugmsg(SUBSYS_X11, "event", VERBOSITY_WARNING,
+				//    "mouse moved to %i, %i",
+				//    event.xmotion.x, event.xmotion.y);
+
+				int dx = event.xmotion.x - mouseXofLastEvent;
+				int dy = event.xmotion.y - mouseYofLastEvent;
+
+				mouseXofLastEvent = event.xmotion.x;
+				mouseYofLastEvent = event.xmotion.y;
+
+				if (grabbed == fbwin && (dx != 0 || dy != 0)) {
+					// debugmsg(SUBSYS_X11, "event", VERBOSITY_WARNING,
+					//    "mouse moved dx %i, %i", dx, dy);
+
+					dx *= fbwin->scaledown;
+					dy *= fbwin->scaledown;
+					console_mouse_coordinate_update(dx, dy, fb_nr);
+
+					// Hack for keeping the mouse pointer away
+					// from the edges of the screen.
+					Window xqpWindow;
+					int rootx, rooty, x, y;
+					unsigned int mask;
+					int res = XQueryPointer(fbwin->x11_display,
+					    RootWindow(fbwin->x11_display, DefaultScreen(fbwin->x11_display)),
+					    &xqpWindow,
+					    &xqpWindow, &rootx, &rooty, &x, &y,
+					    &mask);
+
+					Screen *screen = XDefaultScreenOfDisplay(fbwin->x11_display);
+
+					int w = XWidthOfScreen(screen);
+					int h = XHeightOfScreen(screen);
+					int x1 = w * 1 / 5;
+					int y1 = h * 1 / 5;
+					int x2 = w * 4 / 5;
+					int y2 = h * 4 / 5;
+
+					if (res == True && (rootx < x1 || rooty < y1
+					    || rootx >= x2 || rooty >= y2))
+						mouseMouseToCenterOfScreen(fbwin);
+				}
+			}
+
+			if (event.type == ButtonPress) {
+				/*  debug("[ X11 ButtonPress: %i ]\n",
+				    event.xbutton.button);  */
+				/*  button = 1,2,3 = left,middle,right  */
+
+				// TODO: console_mouse_button with multiple machines?!
+				if (grabbed == fbwin)
+					console_mouse_button(event.xbutton.button, 1);
+			}
+
+			if (event.type == ButtonRelease) {
+				/*  debug("[ X11 ButtonRelease: %i ]\n",
+				    event.xbutton.button);  */
+				/*  button = 1,2,3 = left,middle,right  */
+
+				// TODO: console_mouse_button with multiple machines?!
+				if (grabbed == fbwin)
+					console_mouse_button(event.xbutton.button, 0);
+
+				grab(fbwin);
+			}
+
+			if (event.type==KeyRelease) {
+				XKeyPressedEvent *ke = &event.xkey;
+				int x = ke->keycode;
+				switch (x) {
+					case 37:left_ctrl = false;
+						break;
+					case 64:left_alt = false;
+						break;
+					//default:
+						// 37 = left CTRL, 64 = left ALT
+						//debugmsg(SUBSYS_X11, "event", VERBOSITY_DEBUG,
+						//    "RELEASE: unimplemented keycode %i", x);
+				}
+			}
+
+			if (event.type==KeyPress) {
+				char text[15];
+				KeySym key;
+				XKeyPressedEvent *ke = &event.xkey;
+
+				memset(text, 0, sizeof(text));
+
+				if (XLookupString(&event.xkey, text,
+				    sizeof(text), &key, 0) == 1) {
+					console_makeavail(
+					    m->main_console_handle, text[0]);
+				} else {
+					int x = ke->keycode;
+					/*
+					 *  Special key codes:
+					 *
+					 *  NOTE/TODO: I'm hardcoding these to
+					 *  work with my key map. Maybe they
+					 *  should be read from some file...
+					 *
+					 *  Important TODO 2:  It would be MUCH
+					 *  better if these were converted into
+					 *  'native scancodes', for example for
+					 *  the DECstation's keyboard or the
+					 *  PC-style 8042 controller.
+					 */
+					switch (x) {
+					case 9:	/*  Escape  */
+						console_makeavail(m->
+						    main_console_handle, 27);
+						break;
+#if 0
+					/*  TODO  */
+
+					/*  The numeric keypad:  */
+					90=Ins('0')  91=Del(',')
+
+					/*  Above the cursor keys:  */
+					106=Ins  107=Del
+#endif
+					/*  F1..F4:  */
+					case 67:	/*  F1  */
+					case 68:	/*  F2  */
+					case 69:	/*  F3  */
+					case 70:	/*  F4  */
+						console_makeavail(m->
+						    main_console_handle, 27);
+						console_makeavail(m->
+						    main_console_handle, '[');
+						console_makeavail(m->
+						    main_console_handle, 'O');
+						console_makeavail(m->
+						    main_console_handle, 'P' +
+						    x - 67);
+						break;
+					case 71:	/*  F5  */
+						console_makeavail(m->
+						    main_console_handle, 27);
+						console_makeavail(m->
+						    main_console_handle, '[');
+						console_makeavail(m->
+						    main_console_handle, '1');
+						console_makeavail(m->
+						    main_console_handle, '5');
+						break;
+					case 72:	/*  F6  */
+					case 73:	/*  F7  */
+					case 74:	/*  F8  */
+						console_makeavail(m->
+						    main_console_handle, 27);
+						console_makeavail(m->
+						    main_console_handle, '[');
+						console_makeavail(m->
+						    main_console_handle, '1');
+						console_makeavail(m->
+						    main_console_handle, '7' +
+						    x - 72);
+						break;
+					case 75:	/*  F9  */
+					case 76:	/*  F10  */
+						console_makeavail(m->
+						    main_console_handle, 27);
+						console_makeavail(m->
+						    main_console_handle, '[');
+						console_makeavail(m->
+						    main_console_handle, '2');
+						console_makeavail(m->
+						    main_console_handle, '1' +
+						    x - 68);
+						break;
+					case 95:	/*  F11  */
+					case 96:	/*  F12  */
+						console_makeavail(m->
+						    main_console_handle, 27);
+						console_makeavail(m->
+						    main_console_handle, '[');
+						console_makeavail(m->
+						    main_console_handle, '2');
+						console_makeavail(m->
+						    main_console_handle, '3' +
+						    x - 95);
+						break;
+					/*  Cursor keys:  */
+					case 98:	/*  Up  */
+					case 104:	/*  Down  */
+					case 100:	/*  Left  */
+					case 102:	/*  Right  */
+						console_makeavail(m->
+						    main_console_handle, 27);
+						console_makeavail(m->
+						    main_console_handle, '[');
+						console_makeavail(m->
+						    main_console_handle, 
+						    x == 98? 'A' : (
+						    x == 104? 'B' : (
+						    x == 102? 'C' : (
+						    'D'))));
+						break;
+					/*  Numeric keys:  */
+					case 80:	/*  Up  */
+					case 88:	/*  Down  */
+					case 83:	/*  Left  */
+					case 85:	/*  Right  */
+						console_makeavail(m->
+						    main_console_handle, 27);
+						console_makeavail(m->
+						    main_console_handle, '[');
+						console_makeavail(m->
+						    main_console_handle, 
+						    x == 80? 'A' : (
+						    x == 88? 'B' : (
+						    x == 85? 'C' : (
+						    'D'))));
+						break;
+					case 97:	/*  Cursor  Home  */
+					case 79:	/*  Numeric Home  */
+						console_makeavail(m->
+						    main_console_handle, 27);
+						console_makeavail(m->
+						    main_console_handle, '[');
+						console_makeavail(m->
+						    main_console_handle, 'H');
+						break;
+					case 103:	/*  Cursor  End  */
+					case 87:	/*  Numeric End  */
+						console_makeavail(m->
+						    main_console_handle, 27);
+						console_makeavail(m->
+						    main_console_handle, '[');
+						console_makeavail(m->
+						    main_console_handle, 'F');
+						break;
+					case 99:	/*  Cursor  PgUp  */
+					case 81:	/*  Numeric PgUp  */
+						console_makeavail(m->
+						    main_console_handle, 27);
+						console_makeavail(m->
+						    main_console_handle, '[');
+						console_makeavail(m->
+						    main_console_handle, '5');
+						console_makeavail(m->
+						    main_console_handle, '~');
+						break;
+					case 105:	/*  Cursor  PgUp  */
+					case 89:	/*  Numeric PgDn  */
+						console_makeavail(m->
+						    main_console_handle, 27);
+						console_makeavail(m->
+						    main_console_handle, '[');
+						console_makeavail(m->
+						    main_console_handle, '6');
+						console_makeavail(m->
+						    main_console_handle, '~');
+						break;
+
+					case 37:left_ctrl = true;
+						if (left_ctrl && left_alt)
+							ungrab();
+						break;
+					case 64:left_alt = true;
+						if (left_ctrl && left_alt)
+							ungrab();
+						break;
+
+					//default:
+						//debugmsg(SUBSYS_X11, "event", VERBOSITY_DEBUG,
+						//    "unimplemented keycode %i", x);
+					}
+				}
+			}
+		}
+
+		if (need_redraw)
+			x11_redraw(m, fb_nr);
+	}
+}
+
+
+/*
+ *  x11_check_event():
+ *
+ *  Check for X11 events.
+ */
+void x11_check_event(struct emul *emul)
+{
+	int i;
+
+	for (i=0; i<emul->n_machines; i++)
+		x11_check_events_machine(emul, emul->machines[i]);
+}
+
+#endif	/*  WITH_X11  */
diff -Nru gxemul-0.6.2/src/console/x11.cc gxemul-0.7.0+dfsg/src/console/x11.cc
--- gxemul-0.6.2/src/console/x11.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/console/x11.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,847 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  X11-related functions.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "emul.h"
-#include "machine.h"
-#include "misc.h"
-#include "x11.h"
-
-
-#ifndef	WITH_X11
-
-
-/*  Dummy functions:  */
-void x11_redraw_cursor(struct machine *m, int i) { }
-void x11_redraw(struct machine *m, int x) { }
-void x11_putpixel_fb(struct machine *m, int fb, int x, int y, int color) { }
-void x11_init(struct machine *machine) { }
-struct fb_window *x11_fb_init(int xsize, int ysize, char *name,
-	int scaledown, struct machine *machine)
-    { return NULL; }
-void x11_check_event(struct emul *emul) { }
-
-
-#else	/*  WITH_X11  */
-
-
-#include <X11/Xlib.h>
-#include <X11/Xutil.h>
-#include <X11/cursorfont.h>
-
-
-/*
- *  x11_redraw_cursor():
- *
- *  Redraw a framebuffer's X11 cursor.
- *
- *  NOTE: It is up to the caller to call XFlush.
- */
-void x11_redraw_cursor(struct machine *m, int i)
-{
-	int last_color_used = 0;
-	int n_colors_used = 0;
-	struct fb_window *fbwin = m->x11_md.fb_windows[i];
-
-	/*  Remove old cursor, if any:  */
-	if (fbwin->x11_display != NULL && fbwin->OLD_cursor_on) {
-		XPutImage(fbwin->x11_display, fbwin->x11_fb_window,
-		    fbwin->x11_fb_gc, fbwin->fb_ximage,
-		    fbwin->OLD_cursor_x/fbwin->scaledown,
-		    fbwin->OLD_cursor_y/fbwin->scaledown,
-		    fbwin->OLD_cursor_x/fbwin->scaledown,
-		    fbwin->OLD_cursor_y/fbwin->scaledown,
-		    fbwin->OLD_cursor_xsize/fbwin->scaledown + 1,
-		    fbwin->OLD_cursor_ysize/fbwin->scaledown + 1);
-	}
-
-	if (fbwin->x11_display != NULL && fbwin->cursor_on) {
-		int x, y, subx, suby;
-		XImage *xtmp;
-
-		CHECK_ALLOCATION(xtmp = XSubImage(fbwin->fb_ximage,
-		    fbwin->cursor_x/fbwin->scaledown,
-		    fbwin->cursor_y/fbwin->scaledown,
-		    fbwin->cursor_xsize/fbwin->scaledown + 1,
-		    fbwin->cursor_ysize/fbwin->scaledown + 1));
-
-		for (y=0; y<fbwin->cursor_ysize;
-		    y+=fbwin->scaledown)
-			for (x=0; x<fbwin->cursor_xsize;
-			    x+=fbwin->scaledown) {
-				int px = x/fbwin->scaledown;
-				int py = y/fbwin->scaledown;
-				int p = 0, n = 0, c = 0;
-				unsigned long oldcol;
-
-				for (suby=0; suby<fbwin->scaledown;
-				    suby++)
-					for (subx=0; subx<fbwin->
-					    scaledown; subx++) {
-						c = fbwin->
-						    cursor_pixels[y+suby]
-						    [x+subx];
-						if (c >= 0) {
-							p += c;
-							n++;
-						}
-					}
-				if (n > 0)
-					p /= n;
-				else
-					p = c;
-
-				if (n_colors_used == 0) {
-					last_color_used = p;
-					n_colors_used = 1;
-				} else
-					if (p != last_color_used)
-						n_colors_used = 2;
-
-				switch (p) {
-				case CURSOR_COLOR_TRANSPARENT:
-					break;
-				case CURSOR_COLOR_INVERT:
-					oldcol = XGetPixel(xtmp, px, py);
-					if (oldcol != fbwin->
-					    x11_graycolor[N_GRAYCOLORS-1].pixel)
-						oldcol = fbwin->
-						    x11_graycolor[N_GRAYCOLORS
-						    -1].pixel;
-					else
-						oldcol = fbwin->
-						    x11_graycolor[0].pixel;
-					XPutPixel(xtmp, px, py, oldcol);
-					break;
-				default:	/*  Normal grayscale:  */
-					XPutPixel(xtmp, px, py, fbwin->
-					    x11_graycolor[p].pixel);
-				}
-			}
-
-		XPutImage(fbwin->x11_display,
-		    fbwin->x11_fb_window,
-		    fbwin->x11_fb_gc,
-		    xtmp, 0, 0,
-		    fbwin->cursor_x/fbwin->scaledown,
-		    fbwin->cursor_y/fbwin->scaledown,
-		    fbwin->cursor_xsize/fbwin->scaledown,
-		    fbwin->cursor_ysize/fbwin->scaledown);
-
-		XDestroyImage(xtmp);
-
-		fbwin->OLD_cursor_on = fbwin->cursor_on;
-		fbwin->OLD_cursor_x = fbwin->cursor_x;
-		fbwin->OLD_cursor_y = fbwin->cursor_y;
-		fbwin->OLD_cursor_xsize =
-		    fbwin->cursor_xsize;
-		fbwin->OLD_cursor_ysize =
-		    fbwin->cursor_ysize;
-	}
-
-	/*  printf("n_colors_used = %i\n", n_colors_used);  */
-
-	if (fbwin->host_cursor != 0 && n_colors_used < 2) {
-		/*  Remove the old X11 host cursor:  */
-		XUndefineCursor(fbwin->x11_display,
-		    fbwin->x11_fb_window);
-		XFreeCursor(fbwin->x11_display,
-		    fbwin->host_cursor);
-		fbwin->host_cursor = 0;
-	}
-
-	if (n_colors_used >= 2 && fbwin->host_cursor == 0) {
-		GC tmpgc;
-
-		/*  Create a new X11 host cursor:  */
-		/*  cursor = XCreateFontCursor(fbwin->x11_display,
-		    XC_coffee_mug);  :-)  */
-		if (fbwin->host_cursor_pixmap != 0) {
-			XFreePixmap(fbwin->x11_display,
-			    fbwin->host_cursor_pixmap);
-			fbwin->host_cursor_pixmap = 0;
-		}
-		fbwin->host_cursor_pixmap =
-		    XCreatePixmap(fbwin->x11_display,
-		    fbwin->x11_fb_window, 1, 1, 1);
-		XSetForeground(fbwin->x11_display,
-		    fbwin->x11_fb_gc,
-		    fbwin->x11_graycolor[0].pixel);
-
-		tmpgc = XCreateGC(fbwin->x11_display,
-		    fbwin->host_cursor_pixmap, 0,0);
-
-		XDrawPoint(fbwin->x11_display,
-		    fbwin->host_cursor_pixmap,
-		    tmpgc, 0, 0);
-
-		XFreeGC(fbwin->x11_display, tmpgc);
-
-		fbwin->host_cursor =
-		    XCreatePixmapCursor(fbwin->x11_display,
-		    fbwin->host_cursor_pixmap,
-		    fbwin->host_cursor_pixmap,
-		    &fbwin->x11_graycolor[N_GRAYCOLORS-1],
-		    &fbwin->x11_graycolor[N_GRAYCOLORS-1],
-		    0, 0);
-		if (fbwin->host_cursor != 0) {
-			XDefineCursor(fbwin->x11_display,
-			    fbwin->x11_fb_window,
-			    fbwin->host_cursor);
-		}
-	}
-}
-
-
-/*
- *  x11_redraw():
- *
- *  Redraw X11 windows.
- */
-void x11_redraw(struct machine *m, int i)
-{
-	if (i < 0 || i >= m->x11_md.n_fb_windows ||
-	    m->x11_md.fb_windows[i]->x11_fb_winxsize <= 0)
-		return;
-
-	x11_putimage_fb(m, i);
-	x11_redraw_cursor(m, i);
-	XFlush(m->x11_md.fb_windows[i]->x11_display);
-}
-
-
-/*
- *  x11_putpixel_fb():
- *
- *  Output a framebuffer pixel. i is the framebuffer number.
- */
-void x11_putpixel_fb(struct machine *m, int i, int x, int y, int color)
-{
-	struct fb_window *fbwin;
-	if (i < 0 || i >= m->x11_md.n_fb_windows)
-		return;
-
-	fbwin = m->x11_md.fb_windows[i];
-
-	if (fbwin->x11_fb_winxsize <= 0)
-		return;
-
-	if (color)
-		XSetForeground(fbwin->x11_display,
-		    fbwin->x11_fb_gc, fbwin->fg_color);
-	else
-		XSetForeground(fbwin->x11_display,
-		    fbwin->x11_fb_gc, fbwin->bg_color);
-
-	XDrawPoint(fbwin->x11_display,
-	    fbwin->x11_fb_window, fbwin->x11_fb_gc, x, y);
-
-	XFlush(fbwin->x11_display);
-}
-
-
-/*
- *  x11_putimage_fb():
- *
- *  Output an entire XImage to a framebuffer window. i is the
- *  framebuffer number.
- */
-void x11_putimage_fb(struct machine *m, int i)
-{
-	struct fb_window *fbwin;
-	if (i < 0 || i >= m->x11_md.n_fb_windows)
-		return;
-
-	fbwin = m->x11_md.fb_windows[i];
-
-	if (fbwin->x11_fb_winxsize <= 0)
-		return;
-
-	XPutImage(fbwin->x11_display,
-	    fbwin->x11_fb_window,
-	    fbwin->x11_fb_gc, fbwin->fb_ximage, 0,0, 0,0,
-	    fbwin->x11_fb_winxsize,
-	    fbwin->x11_fb_winysize);
-	XFlush(fbwin->x11_display);
-}
-
-
-/*
- *  x11_init():
- *
- *  Initialize X11 stuff (but doesn't create any windows).
- *
- *  It is then up to individual drivers, for example framebuffer devices,
- *  to initialize their own windows.
- */
-void x11_init(struct machine *m)
-{
-	m->x11_md.n_fb_windows = 0;
-
-	if (m->x11_md.n_display_names > 0) {
-		int i;
-		for (i=0; i<m->x11_md.n_display_names; i++)
-			fatal("Using X11 display: %s\n",
-			    m->x11_md.display_names[i]);
-	}
-
-	m->x11_md.current_display_name_nr = 0;
-}
-
-
-/*
- *  x11_fb_resize():
- *
- *  Set a new size for an X11 framebuffer window.  (NOTE: I didn't think of
- *  this kind of functionality during the initial design, so it is probably
- *  buggy. It also needs some refactoring.)
- */
-void x11_fb_resize(struct fb_window *win, int new_xsize, int new_ysize)
-{
-	int alloc_depth;
-
-	if (win == NULL) {
-		fatal("x11_fb_resize(): win == NULL\n");
-		return;
-	}
-
-	win->x11_fb_winxsize = new_xsize;
-	win->x11_fb_winysize = new_ysize;
-
-	alloc_depth = win->x11_screen_depth;
-	if (alloc_depth == 24)
-		alloc_depth = 32;
-	if (alloc_depth == 15)
-		alloc_depth = 16;
-
-	/*  Note: ximage_data seems to be freed by XDestroyImage below.  */
-	/*  if (win->ximage_data != NULL)
-		free(win->ximage_data);  */
-	CHECK_ALLOCATION(win->ximage_data = (unsigned char *) malloc(
-	    new_xsize * new_ysize * alloc_depth / 8));
-
-	/*  TODO: clear for non-truecolor modes  */
-	memset(win->ximage_data, 0, new_xsize * new_ysize * alloc_depth / 8);
-
-	if (win->fb_ximage != NULL)
-		XDestroyImage(win->fb_ximage);
-	win->fb_ximage = XCreateImage(win->x11_display, CopyFromParent,
-	    win->x11_screen_depth, ZPixmap, 0, (char *)win->ximage_data,
-	    new_xsize, new_ysize, 8, new_xsize * alloc_depth / 8);
-	CHECK_ALLOCATION(win->fb_ximage);
-
-	XResizeWindow(win->x11_display, win->x11_fb_window,
-	    new_xsize, new_ysize);
-}
-
-
-/*
- *  x11_set_standard_properties():
- *
- *  Right now, this only sets the title of a window.
- */
-void x11_set_standard_properties(struct fb_window *fb_window, char *name)
-{
-	XSetStandardProperties(fb_window->x11_display,
-	    fb_window->x11_fb_window, name, "GXemul " VERSION,
-	    None, NULL, 0, NULL);
-}
-
-
-/*
- *  x11_fb_init():
- *
- *  Initialize a framebuffer window.
- */
-struct fb_window *x11_fb_init(int xsize, int ysize, char *name,
-	int scaledown, struct machine *m)
-{
-	Display *x11_display;
-	int x, y, fb_number = 0;
-	size_t alloclen, alloc_depth;
-	XColor tmpcolor;
-	struct fb_window *fbwin;
-	int i;
-	char fg[80], bg[80];
-	char *display_name;
-
-	fb_number = m->x11_md.n_fb_windows;
-
-	CHECK_ALLOCATION(m->x11_md.fb_windows = 
-	    (struct fb_window **) realloc(m->x11_md.fb_windows,
-	    sizeof(struct fb_window *) * (m->x11_md.n_fb_windows + 1)));
-	CHECK_ALLOCATION(fbwin = m->x11_md.fb_windows[fb_number] =
-	    (struct fb_window *) malloc(sizeof(struct fb_window)));
-
-	m->x11_md.n_fb_windows ++;
-
-	memset(fbwin, 0, sizeof(struct fb_window));
-
-	fbwin->x11_fb_winxsize = xsize;
-	fbwin->x11_fb_winysize = ysize;
-
-	/*  Which display name?  */
-	display_name = NULL;
-	if (m->x11_md.n_display_names > 0) {
-		display_name = m->x11_md.display_names[
-		    m->x11_md.current_display_name_nr];
-		m->x11_md.current_display_name_nr ++;
-		m->x11_md.current_display_name_nr %= m->x11_md.n_display_names;
-	}
-
-	if (display_name != NULL)
-		debug("[ x11_fb_init(): framebuffer window %i, %ix%i, DISPLAY"
-		    "=%s ]\n", fb_number, xsize, ysize, display_name);
-
-	x11_display = XOpenDisplay(display_name);
-
-	if (x11_display == NULL) {
-		fatal("x11_fb_init(\"%s\"): couldn't open display\n", name);
-		if (display_name != NULL)
-			fatal("display_name = '%s'\n", display_name);
-		exit(1);
-	}
-
-	fbwin->x11_screen =
-	    DefaultScreen(x11_display);
-	fbwin->x11_screen_depth =
-	    DefaultDepth(x11_display,
-	    fbwin->x11_screen);
-
-	if (fbwin->x11_screen_depth != 8 &&
-	    fbwin->x11_screen_depth != 15 &&
-	    fbwin->x11_screen_depth != 16 &&
-	    fbwin->x11_screen_depth != 24) {
-		fatal("\n***\n***  WARNING! Your X server is running %i-bit "
-		    "color mode. This is not really\n",
-		    fbwin->x11_screen_depth);
-		fatal("***  supported yet.  8, 15, 16, and 24 bits should "
-		    "work.\n***  24-bit server gives color.  Any other bit "
-		    "depth gives undefined result!\n***\n\n");
-	}
-
-	if (fbwin->x11_screen_depth <= 8)
-		debug("WARNING! X11 screen depth is not enough for color; "
-		    "using only 16 grayscales instead\n");
-
-	strlcpy(bg, "Black", sizeof(bg));
-	strlcpy(fg, "White", sizeof(fg));
-
-	XParseColor(x11_display, DefaultColormap(x11_display,
-	    fbwin->x11_screen), fg, &tmpcolor);
-	XAllocColor(x11_display, DefaultColormap(x11_display,
-	    fbwin->x11_screen), &tmpcolor);
-	fbwin->fg_color = tmpcolor.pixel;
-	XParseColor(x11_display, DefaultColormap(x11_display,
-	    fbwin->x11_screen), bg, &tmpcolor);
-	XAllocColor(x11_display, DefaultColormap(x11_display,
-	    fbwin->x11_screen), &tmpcolor);
-	fbwin->bg_color = tmpcolor.pixel;
-
-	for (i=0; i<N_GRAYCOLORS; i++) {
-		char cname[8];
-		cname[0] = '#';
-		cname[1] = cname[2] = cname[3] =
-		    cname[4] = cname[5] = cname[6] =
-		    "0123456789ABCDEF"[i];
-		cname[7] = '\0';
-		XParseColor(x11_display, DefaultColormap(x11_display,
-		    fbwin->x11_screen), cname,
-		    &fbwin->x11_graycolor[i]);
-		XAllocColor(x11_display, DefaultColormap(x11_display,
-		    fbwin->x11_screen),
-		    &fbwin->x11_graycolor[i]);
-	}
-
-        XFlush(x11_display);
-
-	alloc_depth = fbwin->x11_screen_depth;
-
-	if (alloc_depth == 24)
-		alloc_depth = 32;
-	if (alloc_depth == 15)
-		alloc_depth = 16;
-
-	fbwin->x11_fb_window = XCreateWindow(
-	    x11_display, DefaultRootWindow(x11_display),
-	    0, 0, fbwin->x11_fb_winxsize,
-	    fbwin->x11_fb_winysize,
-	    0, CopyFromParent, InputOutput, CopyFromParent, 0,0);
-
-	fbwin->x11_display = x11_display;
-
-	x11_set_standard_properties(fbwin, name);
-
-	XSelectInput(x11_display,
-	    fbwin->x11_fb_window,
-	    StructureNotifyMask | ExposureMask | ButtonPressMask |
-	    ButtonReleaseMask | PointerMotionMask | KeyPressMask);
-	fbwin->x11_fb_gc = XCreateGC(x11_display,
-	    fbwin->x11_fb_window, 0,0);
-
-	/*  Make sure the window is mapped:  */
-	XMapRaised(x11_display, fbwin->x11_fb_window);
-
-	XSetBackground(x11_display, fbwin->x11_fb_gc, fbwin->bg_color);
-	XSetForeground(x11_display, fbwin->x11_fb_gc, fbwin->bg_color);
-	XFillRectangle(x11_display, fbwin->x11_fb_window, fbwin->x11_fb_gc, 0,0,
-	    fbwin->x11_fb_winxsize, fbwin->x11_fb_winysize);
-
-	fbwin->scaledown   = scaledown;
-
-	fbwin->fb_number = fb_number;
-
-	alloclen = xsize * ysize * alloc_depth / 8;
-	CHECK_ALLOCATION(fbwin->ximage_data = (unsigned char *) malloc(alloclen));
-
-	fbwin->fb_ximage = XCreateImage(fbwin->x11_display, CopyFromParent,
-	    fbwin->x11_screen_depth, ZPixmap, 0, (char *)fbwin->ximage_data,
-	    xsize, ysize, 8, xsize * alloc_depth / 8);
-	CHECK_ALLOCATION(fbwin->fb_ximage);
-
-	/*  Fill the ximage with black pixels:  */
-	if (fbwin->x11_screen_depth > 8)
-		memset(fbwin->ximage_data, 0, alloclen);
-	else {
-		debug("x11_fb_init(): clearing the XImage\n");
-		for (y=0; y<ysize; y++)
-			for (x=0; x<xsize; x++)
-				XPutPixel(fbwin->fb_ximage, x, y,
-				    fbwin->x11_graycolor[0].pixel);
-	}
-
-	x11_putimage_fb(m, fb_number);
-
-	/*  Fill the 64x64 "hardware" cursor with white pixels:  */
-	xsize = ysize = 64;
-
-	/*  Fill the cursor ximage with white pixels:  */
-	for (y=0; y<ysize; y++)
-		for (x=0; x<xsize; x++)
-			fbwin->cursor_pixels[y][x] = N_GRAYCOLORS-1;
-
-	return fbwin;
-}
-
-
-/*
- *  x11_check_events_machine():
- *
- *  Check for X11 events on a specific machine.
- *
- *  TODO:  Yuck! This has to be rewritten. Each display should be checked,
- *         and _then_ only those windows that are actually exposed should
- *         be redrawn!
- */
-static void x11_check_events_machine(struct emul *emul, struct machine *m)
-{
-	int fb_nr;
-
-	for (fb_nr = 0; fb_nr < m->x11_md.n_fb_windows; fb_nr ++) {
-		struct fb_window *fbwin = m->x11_md.fb_windows[fb_nr];
-		XEvent event;
-		int need_redraw = 0, found, i, j;
-
-		while (XPending(fbwin->x11_display)) {
-			XNextEvent(fbwin->x11_display, &event);
-
-			if (event.type==ConfigureNotify) {
-				need_redraw = 1;
-			}
-
-			if (event.type==Expose && event.xexpose.count==0) {
-				/*
-				 *  TODO:  the xexpose struct has x,y,width,
-				 *  height. Those could be used to only redraw
-				 *  the part of the framebuffer that was
-				 *  exposed. Note that the (mouse) cursor must
-				 *  be redrawn too.
-				 */
-				/*  x11_winxsize = event.xexpose.width;
-				    x11_winysize = event.xexpose.height;  */
-				need_redraw = 1;
-			}
-
-			if (event.type == MotionNotify) {
-				/*  debug("[ X11 MotionNotify: %i,%i ]\n",
-				    event.xmotion.x, event.xmotion.y);  */
-
-				/*  Which window in which machine in
-				    which emulation?  */
-				found = -1;
-				for (j=0; j<emul->n_machines; j++) {
-					struct machine *m2 = emul->machines[j];
-					for (i=0; i<m2->x11_md.
-					    n_fb_windows; i++)
-						if (m->x11_md.
-						    fb_windows[fb_nr]->
-						    x11_display == m2->
-						    x11_md.
-						    fb_windows[i]->
-						    x11_display &&
-						    event.xmotion.
-						    window == m2->
-						    x11_md.
-						    fb_windows[i]->
-						    x11_fb_window)
-							found = i;
-				}
-				if (found < 0) {
-					printf("Internal error in x11.c.\n");
-					exit(1);
-				}
-				console_mouse_coordinates(event.xmotion.x *
-				    m->x11_md.fb_windows[found]->scaledown,
-				    event.xmotion.y * m->x11_md.fb_windows[
-				    found]->scaledown, found);
-			}
-
-			if (event.type == ButtonPress) {
-				debug("[ X11 ButtonPress: %i ]\n",
-				    event.xbutton.button);
-				/*  button = 1,2,3 = left,middle,right  */
-
-				console_mouse_button(event.xbutton.button, 1);
-			}
-
-			if (event.type == ButtonRelease) {
-				debug("[ X11 ButtonRelease: %i ]\n",
-				    event.xbutton.button);
-				/*  button = 1,2,3 = left,middle,right  */
-
-				console_mouse_button(event.xbutton.button, 0);
-			}
-
-			if (event.type==KeyPress) {
-				char text[15];
-				KeySym key;
-				XKeyPressedEvent *ke = &event.xkey;
-
-				memset(text, 0, sizeof(text));
-
-				if (XLookupString(&event.xkey, text,
-				    sizeof(text), &key, 0) == 1) {
-					console_makeavail(
-					    m->main_console_handle, text[0]);
-				} else {
-					int x = ke->keycode;
-					/*
-					 *  Special key codes:
-					 *
-					 *  NOTE/TODO: I'm hardcoding these to
-					 *  work with my key map. Maybe they
-					 *  should be read from some file...
-					 *
-					 *  Important TODO 2:  It would be MUCH
-					 *  better if these were converted into
-					 *  'native scancodes', for example for
-					 *  the DECstation's keyboard or the
-					 *  PC-style 8042 controller.
-					 */
-					switch (x) {
-					case 9:	/*  Escape  */
-						console_makeavail(m->
-						    main_console_handle, 27);
-						break;
-#if 0
-					/*  TODO  */
-
-					/*  The numeric keypad:  */
-					90=Ins('0')  91=Del(',')
-
-					/*  Above the cursor keys:  */
-					106=Ins  107=Del
-#endif
-					/*  F1..F4:  */
-					case 67:	/*  F1  */
-					case 68:	/*  F2  */
-					case 69:	/*  F3  */
-					case 70:	/*  F4  */
-						console_makeavail(m->
-						    main_console_handle, 27);
-						console_makeavail(m->
-						    main_console_handle, '[');
-						console_makeavail(m->
-						    main_console_handle, 'O');
-						console_makeavail(m->
-						    main_console_handle, 'P' +
-						    x - 67);
-						break;
-					case 71:	/*  F5  */
-						console_makeavail(m->
-						    main_console_handle, 27);
-						console_makeavail(m->
-						    main_console_handle, '[');
-						console_makeavail(m->
-						    main_console_handle, '1');
-						console_makeavail(m->
-						    main_console_handle, '5');
-						break;
-					case 72:	/*  F6  */
-					case 73:	/*  F7  */
-					case 74:	/*  F8  */
-						console_makeavail(m->
-						    main_console_handle, 27);
-						console_makeavail(m->
-						    main_console_handle, '[');
-						console_makeavail(m->
-						    main_console_handle, '1');
-						console_makeavail(m->
-						    main_console_handle, '7' +
-						    x - 72);
-						break;
-					case 75:	/*  F9  */
-					case 76:	/*  F10  */
-						console_makeavail(m->
-						    main_console_handle, 27);
-						console_makeavail(m->
-						    main_console_handle, '[');
-						console_makeavail(m->
-						    main_console_handle, '2');
-						console_makeavail(m->
-						    main_console_handle, '1' +
-						    x - 68);
-						break;
-					case 95:	/*  F11  */
-					case 96:	/*  F12  */
-						console_makeavail(m->
-						    main_console_handle, 27);
-						console_makeavail(m->
-						    main_console_handle, '[');
-						console_makeavail(m->
-						    main_console_handle, '2');
-						console_makeavail(m->
-						    main_console_handle, '3' +
-						    x - 95);
-						break;
-					/*  Cursor keys:  */
-					case 98:	/*  Up  */
-					case 104:	/*  Down  */
-					case 100:	/*  Left  */
-					case 102:	/*  Right  */
-						console_makeavail(m->
-						    main_console_handle, 27);
-						console_makeavail(m->
-						    main_console_handle, '[');
-						console_makeavail(m->
-						    main_console_handle, 
-						    x == 98? 'A' : (
-						    x == 104? 'B' : (
-						    x == 102? 'C' : (
-						    'D'))));
-						break;
-					/*  Numeric keys:  */
-					case 80:	/*  Up  */
-					case 88:	/*  Down  */
-					case 83:	/*  Left  */
-					case 85:	/*  Right  */
-						console_makeavail(m->
-						    main_console_handle, 27);
-						console_makeavail(m->
-						    main_console_handle, '[');
-						console_makeavail(m->
-						    main_console_handle, 
-						    x == 80? 'A' : (
-						    x == 88? 'B' : (
-						    x == 85? 'C' : (
-						    'D'))));
-						break;
-					case 97:	/*  Cursor  Home  */
-					case 79:	/*  Numeric Home  */
-						console_makeavail(m->
-						    main_console_handle, 27);
-						console_makeavail(m->
-						    main_console_handle, '[');
-						console_makeavail(m->
-						    main_console_handle, 'H');
-						break;
-					case 103:	/*  Cursor  End  */
-					case 87:	/*  Numeric End  */
-						console_makeavail(m->
-						    main_console_handle, 27);
-						console_makeavail(m->
-						    main_console_handle, '[');
-						console_makeavail(m->
-						    main_console_handle, 'F');
-						break;
-					case 99:	/*  Cursor  PgUp  */
-					case 81:	/*  Numeric PgUp  */
-						console_makeavail(m->
-						    main_console_handle, 27);
-						console_makeavail(m->
-						    main_console_handle, '[');
-						console_makeavail(m->
-						    main_console_handle, '5');
-						console_makeavail(m->
-						    main_console_handle, '~');
-						break;
-					case 105:	/*  Cursor  PgUp  */
-					case 89:	/*  Numeric PgDn  */
-						console_makeavail(m->
-						    main_console_handle, 27);
-						console_makeavail(m->
-						    main_console_handle, '[');
-						console_makeavail(m->
-						    main_console_handle, '6');
-						console_makeavail(m->
-						    main_console_handle, '~');
-						break;
-					default:
-						debug("[ unimplemented X11 "
-						    "keycode %i ]\n", x);
-					}
-				}
-			}
-		}
-
-		if (need_redraw)
-			x11_redraw(m, fb_nr);
-	}
-}
-
-
-/*
- *  x11_check_event():
- *
- *  Check for X11 events.
- */
-void x11_check_event(struct emul *emul)
-{
-	int i;
-
-	for (i=0; i<emul->n_machines; i++)
-		x11_check_events_machine(emul, emul->machines[i]);
-}
-
-#endif	/*  WITH_X11  */
diff -Nru gxemul-0.6.2/src/core/debugmsg.c gxemul-0.7.0+dfsg/src/core/debugmsg.c
--- gxemul-0.6.2/src/core/debugmsg.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/core/debugmsg.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,528 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Debug message functionality.
+ *
+ *  To print a debug message, use debugmsg() or debugmsg_cpu(). The _cpu
+ *  variant is if the message comes from a particular CPU. In that case, the
+ *  name of the machine and cpu id may be printed.
+ *
+ *  In addition to the actual message to be printed, a subsystem, a component
+ *  name, and a verbosity level also need to be supplied. The component name
+ *  may be empty.
+ *
+ *  If it is relatively expensive to construct the message, then it would be
+ *  a bad idea to do that every time the debugmsg is called in case it is
+ *  rarely shown anyway (due to verbosity level being higher than the current
+ *  setting). Then, the following construct may be used to quickly check before
+ *  constructing the message that it will be shown:
+ *
+ *	if (ENOUGH_VERBOSITY(SUBSYS_XXX, VERBOSITY_YYY)) {
+ *		char msg[....];
+ *		// Construct msg here...
+ *
+ *		debugmsg(SUBSYS_XXX, "component", VERBOSITY_YYY, "%s", msg);
+ *	}
+ *
+ *
+ *  TODO:
+ *	New debugger commands:
+ *		command for showing debug output in new xterms?
+ *		command for enabling breakpoints for subsystem output?
+ *
+ *	Convert existing debug() and fatal() calls to the new debugmsg() call.
+ *
+ *	Make sure that all the hardcoded subsystems are actually used, and/or
+ *	move registering to individual subsystems.
+ */
+
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "emul.h"
+#include "machine.h"
+#include "misc.h"
+
+
+int verbose = 0;
+int quiet_mode = 0;
+
+extern bool emul_executing;
+extern bool single_step;
+extern bool about_to_enter_single_step;
+
+size_t debugmsg_nr_of_subsystems = 0;
+static const char **debugmsg_subsystem_name = NULL;
+int *debugmsg_current_verbosity = NULL;
+
+static const int default_verbosity = VERBOSITY_INFO;
+
+static size_t debug_indent = 0;
+static bool debug_old_currently_at_start_of_line = true;
+
+#define	DEBUG_BUFSIZE		2048
+#define	DEBUG_INDENTATION	4
+
+
+/*
+ *  va_debug():
+ *
+ *  Used internally by the old debug() and fatal() functions.
+ */
+static void va_debug(va_list argp, const char *fmt)
+{
+	char buf[DEBUG_BUFSIZE + 1];
+	buf[0] = buf[DEBUG_BUFSIZE] = 0;
+	vsnprintf(buf, DEBUG_BUFSIZE, fmt, argp);
+
+	char* s = buf;
+	while (*s) {
+		if (debug_old_currently_at_start_of_line) {
+			for (size_t i = 0; i < debug_indent * DEBUG_INDENTATION; i++)
+				printf(" ");
+		}
+
+		printf("%c", *s);
+
+		debug_old_currently_at_start_of_line = false;
+		if (*s == '\n' || *s == '\r')
+			debug_old_currently_at_start_of_line = true;
+		s++;
+	}
+}
+
+
+/*
+ *  debugmsg_va():
+ *
+ *  Used internally by debugmsg().
+ */
+static void debugmsg_va(struct cpu* cpu, int subsystem,
+	const char *name, int verbosity, va_list argp, const char *fmt)
+{
+	if (!single_step && !ENOUGH_VERBOSITY(subsystem, verbosity))
+		return;
+
+	char buf[DEBUG_BUFSIZE];
+
+	buf[0] = buf[DEBUG_BUFSIZE - 1] = 0;
+	vsnprintf(buf, DEBUG_BUFSIZE, fmt, argp);
+
+	char* s = buf;
+	bool ss = single_step || about_to_enter_single_step;
+	bool debug_currently_at_start_of_line = true;
+	bool show_decorations = emul_executing && !ss;
+
+	if (console_are_slaves_allowed())
+		show_decorations = false;
+
+	while (true) {
+		if (debug_currently_at_start_of_line) {
+			if (show_decorations) {
+				color_normal();
+				printf("[ ");
+			} else {
+				for (size_t i = 0; i < debug_indent * DEBUG_INDENTATION; ++i)
+					printf(" ");
+			}
+
+			bool print_subsystem_name =
+			    debugmsg_subsystem_name[subsystem][0] != '\0' &&
+			    (debug_indent == 0 || (name == NULL || name[0] == '\0'));
+			bool print_colon = false;
+
+			if (cpu != NULL) {
+				// With multiple machines being emulated in the
+				// same emulation instance, print both the machine
+				// name and cpu id. If it is just one machine,
+				// only print the cpu id if there are multiple
+				// CPUs in order to not clutter the output
+				// needlessly.
+				struct emul* emul = cpu->machine->emul;
+				if (emul->n_machines > 1) {
+					printf("machine \"%s\" cpu%i: ",
+					    cpu->machine->name ? cpu->machine->name : "(no name)",
+					    cpu->cpu_id);
+					if (subsystem == SUBSYS_CPU)
+						print_subsystem_name = false;
+				} else if (cpu->machine->ncpus > 1) {
+					printf("cpu%i: ", cpu->cpu_id);
+					if (subsystem == SUBSYS_CPU)
+						print_subsystem_name = false;
+				}
+			}
+
+			if (verbosity == VERBOSITY_ERROR)
+				color_error(false);
+			else
+				color_debugmsg_subsystem();
+
+			if (print_subsystem_name) {
+				printf("%s", debugmsg_subsystem_name[subsystem]);
+				print_colon = true;
+			}
+
+			if (name != NULL && name[0] != '\0') {
+				if (print_subsystem_name)
+					printf(" ");
+
+				if (verbosity != VERBOSITY_ERROR)
+					color_debugmsg_name();
+
+				printf("%s", name);
+
+				print_colon = true;
+			}
+
+			if (print_colon)
+				printf(": ");
+
+			if (show_decorations) {
+				for (size_t i = 0; i < debug_indent * DEBUG_INDENTATION; ++i)
+					printf(" ");
+			}
+
+			if (verbosity == VERBOSITY_ERROR)
+				color_error(true);
+			else
+				color_normal();
+		}
+
+		debug_currently_at_start_of_line = false;
+
+		if (!*s)
+			break;
+
+		switch (*s) {
+		case '\n':
+			color_normal();
+			if (show_decorations) {
+				printf(" ]");
+			}
+
+			debug_currently_at_start_of_line = true;
+			printf("\n");
+			break;
+
+		default:
+			printf("%c", *s);
+		}
+
+		s++;
+	}
+
+	color_normal();
+
+	if (show_decorations)
+		printf(" ]");
+
+	if (!debug_currently_at_start_of_line)
+		printf("\n");
+}
+
+
+/*
+ *  debugmsg():
+ *
+ *  The main routine to call, when something should be printed.
+ */
+void debugmsg(int subsystem, const char *name,
+	int verbosity_required, const char *fmt, ...)
+{
+	va_list argp;
+
+	va_start(argp, fmt);
+	debugmsg_va(NULL, subsystem, name, verbosity_required, argp, fmt);
+	va_end(argp);
+}
+
+
+/*
+ *  debugmsg():
+ *
+ *  The main routine to call, when something should be printed and we are
+ *  in the context of a specific CPU.
+ */
+void debugmsg_cpu(struct cpu* cpu, int subsystem, const char *name,
+	int verbosity_required, const char *fmt, ...)
+{
+	va_list argp;
+
+	va_start(argp, fmt);
+	debugmsg_va(cpu, subsystem, name, verbosity_required, argp, fmt);
+	va_end(argp);
+}
+
+
+/*
+ *  debug_indentation():
+ *
+ *  Modify the debug indentation. diff should be +1 to increase, and -1 to
+ *  decrease after printing something.
+ *
+ *  This affects both the older debug() and fatal() functions, and the new
+ *  debugmsg/debugmsg_cpu() functions.
+ */
+void debug_indentation(int diff)
+{
+	debug_indent += diff;
+
+	if ((ssize_t)debug_indent < 0) {
+		fprintf(stderr, "WARNING: debug_indent too low!\n");
+		debug_indent = 0;
+	}
+}
+
+
+/*
+ *  debug() and fatal():
+ *
+ *  These are here because of all the legacy code that uses them. Basically,
+ *  debug() is mapped to something that is only displayed with verbosity
+ *  at the default level, and fatal() is used to always print stuff. With some
+ *  hacks to make it work reasonable with -q and when executing normally or
+ *  when executing single-stepping.
+ */
+void debug(const char *fmt, ...)
+{
+	va_list argp;
+	bool ss = single_step || about_to_enter_single_step;
+	int v = verbose;
+	if (emul_executing)
+		v--;
+	if (ss)
+		v++;
+
+	if ((quiet_mode && !ss) || v < 0)
+		return;
+
+	va_start(argp, fmt);
+	va_debug(argp, fmt);
+	va_end(argp);
+}
+
+
+void fatal(const char *fmt, ...)
+{
+	va_list argp;
+
+	va_start(argp, fmt);
+	va_debug(argp, fmt);
+	va_end(argp);
+}
+
+
+void debugmsg_set_verbosity_level(int subsystem, int verbosity)
+{
+	if (subsystem != SUBSYS_ALL)
+		debugmsg_current_verbosity[subsystem] = verbosity;
+	else
+		for (size_t i = 0; i < debugmsg_nr_of_subsystems; ++i)
+			debugmsg_current_verbosity[i] = verbosity;
+}
+
+
+void debugmsg_add_verbosity_level(int subsystem, int verbosity_delta)
+{
+	if (subsystem != SUBSYS_ALL)
+		debugmsg_current_verbosity[subsystem] += verbosity_delta;
+	else
+		for (size_t i = 0; i < debugmsg_nr_of_subsystems; ++i)
+			debugmsg_current_verbosity[i] += verbosity_delta;
+
+	for (size_t i = 0; i < debugmsg_nr_of_subsystems; ++i)
+		if (debugmsg_current_verbosity[i] < 0)
+			debugmsg_current_verbosity[i] = 0;
+}
+
+
+/*
+ *  debugmsg_register_subsystem():
+ *
+ *  Registers a new subsystem.
+ */
+int debugmsg_register_subsystem(const char* name)
+{
+	// TODO: Another way would be to support multiple names with e.g.
+	// a suffix. Such as "le0", "le1", "le2" for the name "le".
+	// But for now, simply return the same subsystem for all of them.
+	ssize_t subsys = -1;
+	for (size_t i = 0; i < debugmsg_nr_of_subsystems; ++i)
+		if (strcmp(name, debugmsg_subsystem_name[i]) == 0)
+			subsys = i;
+
+	if (subsys >= 0)
+		return subsys;
+	
+	subsys = debugmsg_nr_of_subsystems;
+
+	debugmsg_nr_of_subsystems ++;
+	debugmsg_subsystem_name = realloc(debugmsg_subsystem_name,
+	    sizeof(char*) * debugmsg_nr_of_subsystems);
+	debugmsg_current_verbosity = realloc(debugmsg_current_verbosity,
+	    sizeof(int) * debugmsg_nr_of_subsystems);;
+
+	debugmsg_subsystem_name[subsys] = strdup(name);
+	debugmsg_set_verbosity_level(subsys, default_verbosity);
+
+	return subsys;
+}
+
+
+/*
+ *  debugmsg_change_settings():
+ *
+ *  Changes the current verbosity level settings for a given setting name.
+ */
+void debugmsg_change_settings(char *subsystem_name, char *n)
+{
+	int ns = 0;
+
+	for (size_t i = 0; i < debugmsg_nr_of_subsystems; ++i) {
+		if (strcasecmp("ALL", subsystem_name) != 0) {
+			if (strcmp(subsystem_name, debugmsg_subsystem_name[i]) != 0)
+				continue;
+		}
+
+		int v = atoi(n);
+
+		switch (*n) {
+		case 'e':
+		case 'E':
+			v = 0;
+			break;
+		case 'w':
+		case 'W':
+			v = 1;
+			break;
+		case 'i':
+		case 'I':
+			v = 2;
+			break;
+		case 'd':
+		case 'D':
+			v = 3;
+			break;
+		}
+		
+		debugmsg_current_verbosity[i] = v;
+
+		++ns;
+	}
+
+	if (ns == 0)
+		printf("Unknown debugmsg subsystem name '%s'\n", subsystem_name);
+	else
+		debugmsg_print_settings(subsystem_name);
+}
+
+
+/*
+ *  debugmsg_print_settings():
+ *
+ *  Prints the current verbosity level settings.
+ */
+void debugmsg_print_settings(const char *subsystem_name)
+{
+	int n = 0;
+
+	for (size_t i = 0; i < debugmsg_nr_of_subsystems; ++i) {
+		if (subsystem_name != NULL && subsystem_name[0] != '\0' &&
+		    strcasecmp("ALL", subsystem_name) != 0) {
+			if (strcmp(subsystem_name, debugmsg_subsystem_name[i]) != 0)
+				continue;
+		}
+
+		const char* name = debugmsg_subsystem_name[i];
+		if (i == SUBSYS_STARTUP)
+			name = "(startup related)";
+
+		char buf[100];
+		switch (debugmsg_current_verbosity[i]) {
+		case VERBOSITY_ERROR:
+			snprintf(buf, sizeof(buf), "0: ERROR");
+			break;
+		case VERBOSITY_WARNING:
+			snprintf(buf, sizeof(buf), "1: WARNING");
+			break;
+		case VERBOSITY_INFO:
+			snprintf(buf, sizeof(buf), "2: INFO");
+			break;
+		case VERBOSITY_DEBUG:
+			snprintf(buf, sizeof(buf), "3: DEBUG");
+			break;
+		default:
+			snprintf(buf, sizeof(buf), "%i", debugmsg_current_verbosity[i]);
+			break;
+		}
+
+		if (n == 0)
+			printf("Subsystem:          Level:\n");
+
+		printf("%17s   %s\n", name, buf);
+
+		++n;
+	}
+
+	if (n == 0)
+		printf("Unknown debugmsg subsystem name '%s'\n", subsystem_name);
+}
+
+
+/*
+ *  debugmsg_init():
+ *
+ *  Initializes the debugmsg functionality.
+ */
+void debugmsg_init()
+{
+	debugmsg_nr_of_subsystems = 11;
+	debugmsg_subsystem_name = malloc(sizeof(char*) * debugmsg_nr_of_subsystems);
+	debugmsg_current_verbosity = malloc(sizeof(int) * debugmsg_nr_of_subsystems);;
+
+	debugmsg_subsystem_name[SUBSYS_STARTUP]   = "";
+	debugmsg_subsystem_name[SUBSYS_EMUL]      = "emul";
+	debugmsg_subsystem_name[SUBSYS_DISK]      = "disk";
+	debugmsg_subsystem_name[SUBSYS_NET]       = "net";
+	debugmsg_subsystem_name[SUBSYS_MACHINE]   = "machine";
+	debugmsg_subsystem_name[SUBSYS_DEVICE]    = "device";
+	debugmsg_subsystem_name[SUBSYS_CPU]       = "cpu";
+	debugmsg_subsystem_name[SUBSYS_MEMORY]    = "memory";
+	debugmsg_subsystem_name[SUBSYS_EXCEPTION] = "exception";
+	debugmsg_subsystem_name[SUBSYS_PROMEMUL]  = "promemul";
+	debugmsg_subsystem_name[SUBSYS_X11]       = "X11";
+
+	// Default verbosity levels.
+	debugmsg_set_verbosity_level(SUBSYS_ALL, default_verbosity);
+}
+
+
diff -Nru gxemul-0.6.2/src/core/emul.c gxemul-0.7.0+dfsg/src/core/emul.c
--- gxemul-0.6.2/src/core/emul.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/core/emul.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1001 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Emulation startup and misc. routines.
+ */
+
+#include <signal.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <limits.h>
+#include <stdarg.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "arcbios.h"
+#include "cpu.h"
+#include "emul.h"
+#include "console.h"
+#include "debugger.h"
+#include "device.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "net.h"
+#include "settings.h"
+#include "timer.h"
+#include "x11.h"
+
+
+extern int extra_argc;
+extern char **extra_argv;
+
+extern int verbose;
+extern bool debugger_enter_at_end_of_run;
+extern bool single_step;
+extern bool about_to_enter_single_step;
+
+bool emul_executing = false;
+bool emul_shutdown = false;
+
+
+/*
+ *  add_breakpoints():
+ *
+ *  Take the strings breakpoint_string[] and convert to addresses
+ *  (and store them in breakpoint_addr[]).
+ *
+ *  TODO: This function should be moved elsewhere.
+ */
+static void add_breakpoints(struct machine *m)
+{
+	int i;
+	int string_flag;
+	uint64_t dp;
+
+	for (i=0; i<m->breakpoints.n; i++) {
+		string_flag = 0;
+		dp = strtoull(m->breakpoints.string[i], NULL, 0);
+
+		/*
+		 *  If conversion resulted in 0, then perhaps it is a
+		 *  symbol:
+		 */
+		if (dp == 0) {
+			uint64_t addr;
+			int res = get_symbol_addr(&m->symbol_context,
+			    m->breakpoints.string[i], &addr);
+			if (!res) {
+				fprintf(stderr,
+				    "ERROR! Breakpoint '%s' could not be"
+					" parsed\n",
+				    m->breakpoints.string[i]);
+				exit(1);
+			} else {
+				dp = addr;
+				string_flag = 1;
+			}
+		}
+
+		/*
+		 *  TODO:  It would be nice if things like   symbolname+0x1234
+		 *  were automatically converted into the correct address.
+		 */
+
+		if (m->cpus[0]->cpu_family->arch == ARCH_MIPS) {
+			if ((dp >> 32) == 0 && ((dp >> 31) & 1))
+				dp |= 0xffffffff00000000ULL;
+		}
+
+		m->breakpoints.addr[i] = dp;
+
+		debug("breakpoint %i: 0x%" PRIx64, i, dp);
+		if (string_flag)
+			debug(" (%s)", m->breakpoints.string[i]);
+		debug("\n");
+	}
+}
+
+
+/*
+ *  fix_console():
+ */
+static void fix_console(void)
+{
+	console_deinit_main();
+}
+
+
+/*
+ *  emul_new():
+ *
+ *  Returns a reasonably initialized struct emul.
+ */
+struct emul *emul_new(char *name)
+{
+	struct emul *e;
+
+	CHECK_ALLOCATION(e = (struct emul *) malloc(sizeof(struct emul)));
+	memset(e, 0, sizeof(struct emul));
+
+	e->settings = settings_new();
+
+	settings_add(e->settings, "n_machines", 0,
+	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_DECIMAL,
+	    (void *) &e->n_machines);
+
+	/*  TODO: More settings?  */
+
+	/*  Sane default values:  */
+	e->n_machines = 0;
+	e->next_serial_nr = 1;
+
+	if (name != NULL) {
+		CHECK_ALLOCATION(e->name = strdup(name));
+		settings_add(e->settings, "name", 0,
+		    SETTINGS_TYPE_STRING, SETTINGS_FORMAT_STRING,
+		    (void *) &e->name);
+	}
+
+	return e;
+}
+
+
+/*
+ *  emul_destroy():
+ *
+ *  Destroys a previously created emul object.
+ */
+void emul_destroy(struct emul *emul)
+{
+	int i;
+
+	if (emul->name != NULL) {
+		settings_remove(emul->settings, "name");
+		free(emul->name);
+	}
+
+	for (i=0; i<emul->n_machines; i++)
+		machine_destroy(emul->machines[i]);
+
+	if (emul->machines != NULL)
+		free(emul->machines);
+
+	/*  Remove any remaining level-1 settings:  */
+	settings_remove_all(emul->settings);
+	settings_destroy(emul->settings);
+
+	free(emul);
+}
+
+
+/*
+ *  emul_add_machine():
+ *
+ *  Calls machine_new(), adds the new machine into the emul struct, and
+ *  returns a pointer to the new machine.
+ *
+ *  This function should be used instead of manually calling machine_new().
+ */
+struct machine *emul_add_machine(struct emul *e, char *name)
+{
+	struct machine *m;
+	char tmpstr[20];
+	int i;
+
+	m = machine_new(name, e, e->n_machines);
+	m->serial_nr = (e->next_serial_nr ++);
+
+	i = e->n_machines ++;
+
+	/*
+	 *  When emulating more than one machine, use separate terminal
+	 *  windows for each:
+	 */
+	if (e->n_machines > 1)
+		console_allow_slaves(1);
+
+	CHECK_ALLOCATION(e->machines = (struct machine **) realloc(e->machines,
+	    sizeof(struct machine *) * e->n_machines));
+
+	e->machines[i] = m;
+
+	snprintf(tmpstr, sizeof(tmpstr), "machine[%i]", i);
+	settings_add(e->settings, tmpstr, 1, SETTINGS_TYPE_SUBSETTINGS, 0,
+	    e->machines[i]->settings);
+
+	return m;
+}
+
+
+/*
+ *  add_arc_components():
+ *
+ *  This function adds ARCBIOS memory descriptors for the loaded program,
+ *  and ARCBIOS components for SCSI devices.
+ */
+static void add_arc_components(struct machine *m)
+{
+	struct cpu *cpu = m->cpus[m->bootstrap_cpu];
+	uint64_t start = cpu->pc & 0x1fffffff;
+	uint64_t len = 0xc00000 - start;
+	struct diskimage *d;
+	uint64_t scsicontroller, scsidevice, scsidisk;
+
+	if ((cpu->pc >> 60) != 0xf) {
+		start = cpu->pc & 0xffffffffffULL;
+		len = 0xc00000 - start;
+	}
+
+	len += 1048576 * m->memory_offset_in_mb;
+
+	/*
+	 *  NOTE/TODO: magic 12MB end of load program area
+	 *
+	 *  Hm. This breaks the old FreeBSD/MIPS snapshots...
+	 */
+#if 0
+	arcbios_add_memory_descriptor(cpu,
+	    0x60000 + m->memory_offset_in_mb * 1048576,
+	    start-0x60000 - m->memory_offset_in_mb * 1048576,
+	    ARCBIOS_MEM_FreeMemory);
+#endif
+	arcbios_add_memory_descriptor(cpu,
+	    start, len, ARCBIOS_MEM_LoadedProgram);
+
+	scsicontroller = arcbios_get_scsicontroller(m);
+	if (scsicontroller == 0)
+		return;
+
+	/*  TODO: The device 'name' should defined be somewhere else.  */
+
+	d = m->first_diskimage;
+	while (d != NULL) {
+		if (d->type == DISKIMAGE_SCSI) {
+			int a, b, flags = COMPONENT_FLAG_Input;
+			char component_string[100];
+			const char *name = "DEC     RZ58     (C) DEC2000";
+
+			/*  Read-write, or read-only?  */
+			if (d->writable)
+				flags |= COMPONENT_FLAG_Output;
+			else
+				flags |= COMPONENT_FLAG_ReadOnly;
+
+			a = COMPONENT_TYPE_DiskController;
+			b = COMPONENT_TYPE_DiskPeripheral;
+
+			if (d->is_a_cdrom) {
+				flags |= COMPONENT_FLAG_Removable;
+				a = COMPONENT_TYPE_CDROMController;
+				b = COMPONENT_TYPE_FloppyDiskPeripheral;
+				name = "NEC     CD-ROM CDR-210P 1.0 ";
+			}
+
+			scsidevice = arcbios_addchild_manual(cpu,
+			    COMPONENT_CLASS_ControllerClass,
+			    a, flags, 1, 2, d->id, 0xffffffff,
+			    name, scsicontroller, NULL, 0);
+
+			scsidisk = arcbios_addchild_manual(cpu,
+			    COMPONENT_CLASS_PeripheralClass,
+			    b, flags, 1, 2, 0, 0xffffffff, NULL,
+			    scsidevice, NULL, 0);
+
+			/*
+			 *  Add device string to component address mappings:
+			 *  "scsi(0)disk(0)rdisk(0)partition(0)"
+			 */
+
+			if (d->is_a_cdrom) {
+				snprintf(component_string,
+				    sizeof(component_string),
+				    "scsi(0)cdrom(%i)", d->id);
+				arcbios_add_string_to_component(m,
+				    component_string, scsidevice);
+
+				snprintf(component_string,
+				    sizeof(component_string),
+				    "scsi(0)cdrom(%i)fdisk(0)", d->id);
+				arcbios_add_string_to_component(m,
+				    component_string, scsidisk);
+			} else {
+				snprintf(component_string,
+				    sizeof(component_string),
+				    "scsi(0)disk(%i)", d->id);
+				arcbios_add_string_to_component(m,
+				    component_string, scsidevice);
+
+				snprintf(component_string,
+				    sizeof(component_string),
+				    "scsi(0)disk(%i)rdisk(0)", d->id);
+				arcbios_add_string_to_component(m,
+				    component_string, scsidisk);
+			}
+		}
+
+		d = d->next;
+	}
+}
+
+
+/*
+ *  emul_machine_setup():
+ *
+ *	o)  Initialize the hardware (RAM, devices, CPUs, ...) which
+ *	    will be emulated in this machine.
+ *
+ *	o)  Load ROM code and/or other programs into emulated memory.
+ *
+ *	o)  Special hacks needed after programs have been loaded.
+ *
+ *  Returns true on success, false if the machine could not be set up.
+ */
+bool emul_machine_setup(struct machine *m, int n_load, char **load_names,
+	int n_devices, char **device_names)
+{
+	struct cpu *cpu;
+	uint64_t memory_amount, entrypoint = 0, gp = 0, toc = 0;
+	int i, byte_order;
+
+	if (m->name != NULL && m->name[0])
+		debugmsg(SUBSYS_MACHINE, "", VERBOSITY_INFO, "%s", m->name);
+	else
+		debugmsg(SUBSYS_MACHINE, "", VERBOSITY_INFO, "");
+
+	debug_indentation(1);
+
+	if (m->machine_type == MACHINE_NONE) {
+		fatal("No machine type specified?\n");
+		return false;
+	}
+
+	// Hack for Alpha.
+	if (m->machine_type == MACHINE_ALPHA)
+		m->arch_pagesize = 8192;
+
+	machine_memsize_fix(m);
+
+	/*
+	 *  Create the system's base memory:
+	 */
+	char meminfo[2000];
+	snprintf(meminfo, sizeof(meminfo), "%i MB", m->physical_ram_in_mb);
+
+	memory_amount = (uint64_t)m->physical_ram_in_mb * 1048576;
+	if (m->memory_offset_in_mb > 0) {
+		/*
+		 *  A special hack is used for some SGI models,
+		 *  where memory is offset by 128MB to leave room for
+		 *  EISA space and other things.
+		 */
+		snprintf(meminfo + strlen(meminfo), sizeof(meminfo) - strlen(meminfo),
+		    " (offset by %i MB)", m->memory_offset_in_mb);
+
+		memory_amount += 1048576 * m->memory_offset_in_mb;
+	}
+
+	if (m->machine_type == MACHINE_SGI && m->machine_subtype == 32) {
+		if (memory_amount > 0x10000000) {
+			memory_amount = 0x10000000;
+			snprintf(meminfo + strlen(meminfo), sizeof(meminfo) - strlen(meminfo),
+			    " (SGI O2 hack: %i MB at offset 0)", 0x10000000 / 1048576);
+		}
+	}
+
+	if (m->random_mem_contents)
+		snprintf(meminfo + strlen(meminfo), sizeof(meminfo) - strlen(meminfo),
+		    ", randomized content");
+
+	m->memory = memory_new(memory_amount);
+
+	/*  Create CPUs:  */
+	if (m->cpu_name == NULL)
+		machine_default_cputype(m);
+	if (m->ncpus == 0)
+		m->ncpus = 1;
+
+	CHECK_ALLOCATION(m->cpus = (struct cpu **) malloc(sizeof(struct cpu *) * m->ncpus));
+	memset(m->cpus, 0, sizeof(struct cpu *) * m->ncpus);
+
+	char cpuname[200];
+	if (m->ncpus == 1)
+		snprintf(cpuname, sizeof(cpuname), "cpu0");
+	else
+		snprintf(cpuname, sizeof(cpuname), "cpu0 .. cpu%i", m->ncpus - 1);
+
+	for (i=0; i<m->ncpus; i++) {
+		m->cpus[i] = cpu_new(m->memory, m, i, m->cpu_name);
+		if (m->cpus[i] == NULL) {
+			fprintf(stderr, "Unable to create CPU object. "
+			    "Aborting.");
+			return false;
+		}
+	}
+
+	if (m->use_random_bootstrap_cpu)
+		m->bootstrap_cpu = random() % m->ncpus;
+	else
+		m->bootstrap_cpu = 0;
+
+	cpu = m->cpus[m->bootstrap_cpu];
+
+	if (m->x11_md.in_use)
+		x11_init(m);
+
+	/*  Fill the directly addressable memory with random bytes:  */
+	if (m->random_mem_contents) {
+		for (i=0; i<(int)memory_amount; i+=256) {
+			unsigned char data[256];
+			unsigned int j;
+			for (j=0; j<sizeof(data); j++)
+				data[j] = random() & 255;
+			cpu->memory_rw(cpu, m->memory, i, data, sizeof(data),
+			    MEM_WRITE, CACHE_NONE | NO_EXCEPTIONS | PHYSICAL);
+		}
+	}
+
+	for (i=0; i<n_devices; i++)
+		device_add(m, device_names[i]);
+
+	machine_setup(m);
+
+	cpu_dumpinfo(m, cpu, false);
+	debugmsg(SUBSYS_MACHINE, "memory", VERBOSITY_INFO, "%s", meminfo);
+	diskimage_dump_info(m);
+	console_debug_dump(m);
+
+	/*  Load files (ROM code, boot code, ...) into memory:  */
+	if (n_load == 0) {
+		if (m->first_diskimage != NULL) {
+			if (!load_bootblock(m, cpu, &n_load, &load_names)) {
+				fprintf(stderr, "\nNo executable files were"
+				    " specified, and booting directly from disk"
+				    " failed.\n");
+				return false;
+			}
+		} else {
+			fprintf(stderr, "No executable file(s) loaded, and "
+			    "we are not booting directly from a disk image."
+			    "\nAborting.\n");
+			return false;
+		}
+	}
+
+	while (n_load > 0) {
+		FILE *tmp_f;
+		char *name_to_load = *load_names;
+		int remove_after_load = 0;
+
+		/*  Special hack for removing temporary files:  */
+		if (name_to_load[0] == 8) {
+			name_to_load ++;
+			remove_after_load = 1;
+		}
+
+		/*
+		 *  gzipped files are automagically gunzipped:
+		 *  NOTE/TODO: This isn't secure. system() is used.
+		 */
+		tmp_f = fopen(name_to_load, "r");
+		if (tmp_f != NULL) {
+			unsigned char buf[2];		/*  gzip header  */
+			size_t res;
+
+			memset(buf, 0, sizeof(buf));
+			res = fread(buf, 1, sizeof(buf), tmp_f);
+
+			if (res == sizeof(buf) &&
+			    buf[0] == 0x1f && buf[1] == 0x8b) {
+				size_t zzlen = strlen(name_to_load)*2 + 100;
+				char *zz;
+
+				CHECK_ALLOCATION(zz = (char*) malloc(zzlen));
+				debug("gunziping %s\n", name_to_load);
+
+				/*
+				 *  gzip header found.  If this was a file
+				 *  extracted from, say, a CDROM image, then it
+				 *  already has a temporary name. Otherwise we
+				 *  have to gunzip into a temporary file.
+				 */
+				if (remove_after_load) {
+					snprintf(zz, zzlen, "mv %s %s.gz",
+					    name_to_load, name_to_load);
+					if (system(zz) != 0)
+						perror(zz);
+					snprintf(zz, zzlen, "gunzip %s.gz",
+					    name_to_load);
+					if (system(zz) != 0)
+						perror(zz);
+				} else {
+					/*  gunzip into new temp file:  */
+					int tmpfile_handle;
+					char *new_temp_name;
+					const char *tmpdir = getenv("TMPDIR");
+
+					if (tmpdir == NULL)
+						tmpdir = DEFAULT_TMP_DIR;
+
+					CHECK_ALLOCATION(new_temp_name =
+					    (char*) malloc(300));
+					snprintf(new_temp_name, 300,
+					    "%s/gxemul.XXXXXXXXXXXX", tmpdir);
+
+					tmpfile_handle = mkstemp(new_temp_name);
+					close(tmpfile_handle);
+					snprintf(zz, zzlen, "gunzip -c '%s' > "
+					    "%s", name_to_load, new_temp_name);
+					if (system(zz) != 0)
+						perror(zz);
+					name_to_load = new_temp_name;
+					remove_after_load = 1;
+				}
+				free(zz);
+			}
+			fclose(tmp_f);
+		}
+
+		byte_order = NO_BYTE_ORDER_OVERRIDE;
+
+		/*
+		 *  Load the file:  :-)
+		 */
+		file_load(m, m->memory, name_to_load, &entrypoint,
+		    cpu->cpu_family->arch, &gp, &byte_order, &toc);
+
+		if (remove_after_load) {
+			debug("removing %s\n", name_to_load);
+			unlink(name_to_load);
+		}
+
+		if (byte_order != NO_BYTE_ORDER_OVERRIDE)
+			cpu->byte_order = byte_order;
+
+		cpu->pc = entrypoint;
+
+		switch (cpu->cpu_family->arch) {
+
+		case ARCH_ALPHA:
+			/*  For position-independent code:  */
+			cpu->cd.alpha.r[ALPHA_T12] = cpu->pc;
+			break;
+
+		case ARCH_ARM:
+			if (cpu->pc & 2) {
+				fatal("ARM: misaligned pc: TODO\n");
+				return false;
+			}
+
+			cpu->pc = (uint32_t)cpu->pc;
+
+			// Lowest bit of PC indicates THUMB mode.
+			if (cpu->pc & 1)
+				cpu->cd.arm.cpsr |= ARM_FLAG_T;
+			break;
+
+		case ARCH_I960:
+			if (cpu->pc & 3) {
+				fatal("i960: lowest bits of pc set: TODO\n");
+				return false;
+			}
+			cpu->pc &= 0xfffffffc;
+			break;
+
+		case ARCH_M88K:
+			if (cpu->pc & 3) {
+				fatal("M88K: lowest bits of pc set: TODO\n");
+				return false;
+			}
+			cpu->pc &= 0xfffffffc;
+			break;
+
+		case ARCH_MIPS:
+			if ((cpu->pc >> 32) == 0 && (cpu->pc & 0x80000000ULL))
+				cpu->pc |= 0xffffffff00000000ULL;
+
+			cpu->cd.mips.gpr[MIPS_GPR_GP] = gp;
+
+			if ((cpu->cd.mips.gpr[MIPS_GPR_GP] >> 32) == 0 &&
+			    (cpu->cd.mips.gpr[MIPS_GPR_GP] & 0x80000000ULL))
+				cpu->cd.mips.gpr[MIPS_GPR_GP] |=
+				    0xffffffff00000000ULL;
+			break;
+
+		case ARCH_PPC:
+			/*  See http://www.linuxbase.org/spec/ELF/ppc64/
+			    spec/x458.html for more info.  */
+			cpu->cd.ppc.gpr[2] = toc;
+			/*  TODO  */
+			if (cpu->cd.ppc.bits == 32)
+				cpu->pc &= 0xffffffffULL;
+			break;
+
+		case ARCH_RISCV:
+			if (cpu->pc & 1) {
+				fatal("RISC-V: lowest bit of pc set: TODO\n");
+				return false;
+			}
+			cpu->pc &= ~1ULL;
+			break;
+
+		case ARCH_SH:
+			if (cpu->cd.sh.cpu_type.bits == 32)
+				cpu->pc &= 0xffffffffULL;
+			cpu->pc &= ~1;
+			break;
+
+		default:
+			debugmsg(SUBSYS_EMUL, "emul_machine_setup()", VERBOSITY_ERROR,
+			    "Internal error: Unimplemented CPU arch %i", cpu->cpu_family->arch);
+			return false;
+		}
+
+		n_load --;
+		load_names ++;
+	}
+
+	if (m->byte_order_override != NO_BYTE_ORDER_OVERRIDE)
+		cpu->byte_order = m->byte_order_override;
+
+	/*  Same byte order and entrypoint for all CPUs:  */
+	for (i=0; i<m->ncpus; i++)
+		if (i != m->bootstrap_cpu) {
+			m->cpus[i]->byte_order = cpu->byte_order;
+			m->cpus[i]->pc = cpu->pc;
+		}
+
+	/*  Startup the bootstrap CPU:  */
+	cpu->running = true;
+
+	/*  ... or pause all CPUs, if start_paused is set:  */
+	if (m->start_paused) {
+		for (i=0; i<m->ncpus; i++)
+			m->cpus[i]->running = false;
+	}
+
+	/*  Parse and add breakpoints:  */
+	add_breakpoints(m);
+
+	symbol_recalc_sizes(&m->symbol_context);
+
+	/*  Special hack for ARC/SGI emulation:  */
+	if ((m->machine_type == MACHINE_ARC ||
+	    m->machine_type == MACHINE_SGI) && m->prom_emulation)
+		add_arc_components(m);
+
+	char cpu_startinfo_cpuname[1000];
+	snprintf(cpu_startinfo_cpuname, sizeof(cpu_startinfo_cpuname),
+	    "cpu%i", m->bootstrap_cpu);
+
+	char cpu_startinfo[1000];
+	snprintf(cpu_startinfo, sizeof(cpu_startinfo), "starting at ");
+
+	if (cpu->is_32bit)
+		snprintf(cpu_startinfo + strlen(cpu_startinfo), sizeof(cpu_startinfo) - strlen(cpu_startinfo),
+		    "0x%08" PRIx32, (uint32_t) cpu->pc);
+	else
+		snprintf(cpu_startinfo + strlen(cpu_startinfo), sizeof(cpu_startinfo) - strlen(cpu_startinfo),
+		    "0x%016" PRIx64, (uint64_t) cpu->pc);
+
+	uint64_t offset;
+	int n_args;
+	char* bootaddr_symbol = get_symbol_name_and_n_args(&m->symbol_context, cpu->pc, &offset, &n_args);
+	if (bootaddr_symbol != NULL)
+		snprintf(cpu_startinfo + strlen(cpu_startinfo), sizeof(cpu_startinfo) - strlen(cpu_startinfo),
+		    " <%s>", bootaddr_symbol);
+
+	/*  Also show the GP (or equivalent):  */
+	switch (cpu->cpu_family->arch) {
+
+	case ARCH_MIPS:
+		if (cpu->cd.mips.gpr[MIPS_GPR_GP] != 0) {
+			if (cpu->is_32bit)
+				snprintf(cpu_startinfo + strlen(cpu_startinfo), sizeof(cpu_startinfo) - strlen(cpu_startinfo),
+				    " (gp=0x%08" PRIx32, (uint32_t) m->cpus[m->bootstrap_cpu]->cd.mips.gpr[MIPS_GPR_GP]);
+			else
+				snprintf(cpu_startinfo + strlen(cpu_startinfo), sizeof(cpu_startinfo) - strlen(cpu_startinfo),
+				    " (gp=0x%016" PRIx64, (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_GP]);
+
+			char* gp_symbol = get_symbol_name_and_n_args(&m->symbol_context,
+			    cpu->cd.mips.gpr[MIPS_GPR_GP], &offset, &n_args);
+			if (gp_symbol != NULL)
+				snprintf(cpu_startinfo + strlen(cpu_startinfo),
+				    sizeof(cpu_startinfo) - strlen(cpu_startinfo),
+		    		    " <%s>", gp_symbol);
+
+			snprintf(cpu_startinfo + strlen(cpu_startinfo),
+			    sizeof(cpu_startinfo) - strlen(cpu_startinfo),
+	    		    ")");
+		}
+		break;
+	}
+
+	debugmsg(SUBSYS_MACHINE, cpu_startinfo_cpuname, VERBOSITY_INFO, "%s", cpu_startinfo);
+
+	debug_indentation(-1);
+	
+	return true;
+}
+
+
+/*
+ *  emul_dumpinfo():
+ *
+ *  Dump info about the network (if any), and all machines in an emul.
+ */
+void emul_dumpinfo(struct emul *e)
+{
+	int i;
+
+	if (e->net != NULL)
+		net_dumpinfo(e->net);
+
+	for (i = 0; i < e->n_machines; i++) {
+	
+		if (e->n_machines > 1)
+			debugmsg(SUBSYS_MACHINE, "", VERBOSITY_INFO, "%s (%i)", e->machines[i]->name, i);
+		else
+			debugmsg(SUBSYS_MACHINE, "", VERBOSITY_INFO, "");
+
+		debug_indentation(1);
+		machine_dumpinfo(e->machines[i]);
+		debug_indentation(-1);
+	}
+}
+
+
+/*
+ *  emul_simple_init():
+ *
+ *  For a normal setup:
+ *
+ *	o)  Initialize a network.
+ *	o)  Initialize one machine.
+ *
+ *  Returns true if the initialization succeeded, false if it failed.
+ */
+bool emul_simple_init(struct emul *emul, char* tap_devname)
+{
+	struct machine *m;
+
+	if (emul->n_machines != 1) {
+		debugmsg(SUBSYS_STARTUP, "emul_simple_init()", VERBOSITY_ERROR,
+		    "n_machines = %i (should be 1!)", emul->n_machines);
+		return false;
+	}
+
+	m = emul->machines[0];
+
+	/*  Create a simple network:  */
+	emul->net = net_init(emul, NET_INIT_FLAG_GATEWAY,
+	    tap_devname,
+	    NET_DEFAULT_IPV4_MASK,
+	    NET_DEFAULT_IPV4_LEN,
+	    NULL, 0, 0, NULL);
+
+	if (emul->net == NULL)
+		return false;
+
+	/*  Create the machine:  */
+	return emul_machine_setup(m, extra_argc, extra_argv, 0, NULL);
+}
+
+
+/*
+ *  emul_create_from_configfile():
+ *
+ *  Create an emul struct by reading settings from a configuration file.
+ */
+struct emul *emul_create_from_configfile(char *fname)
+{
+	struct emul *e = emul_new(fname);
+
+	debugmsg(SUBSYS_EMUL, "", VERBOSITY_INFO, "using configfile \"%s\"", fname);
+
+	debug_indentation(1);
+
+	emul_parse_config(e, fname);
+
+	debug_indentation(-1);
+	return e;
+}
+
+
+/*
+ *  emul_run():
+ *
+ *	o)  Set up things needed before running an emulation.
+ *	o)  Run instructions in all machines.
+ *	o)  De-initialize things.
+ */
+void emul_run(struct emul *emul)
+{
+	atexit(fix_console);
+
+	if (emul == NULL) {
+		fatal("No emulation defined. Aborting.\n");
+		return;
+	}
+
+	if (emul->n_machines == 0) {
+		fatal("No machine(s) defined. Aborting.\n");
+		return;
+	}
+
+	/*  Initialize the interactive debugger:  */
+	debugger_init(emul);
+
+	/*  Run any additional debugger commands before starting:  */
+	if (emul->n_debugger_cmds > 0) {
+		print_separator_line();
+
+		for (int k = 0; k < emul->n_debugger_cmds; k ++) {
+			debug("> %s\n", emul->debugger_cmds[k]);
+			debugger_execute_cmd(emul->debugger_cmds[k],
+			    strlen(emul->debugger_cmds[k]));
+		}
+	}
+
+	print_separator_line();
+	debug("\n");
+
+
+	/*
+	 *  console_init_main() makes sure that the terminal is in a
+	 *  reasonable state.
+	 *
+	 *  The SIGINT handler is for CTRL-C  (enter the interactive debugger).
+	 *
+	 *  The SIGCONT handler is invoked whenever the user presses CTRL-Z
+	 *  (or sends SIGSTOP) and then continues. It makes sure that the
+	 *  terminal is in an expected state.
+	 *
+	 *  Note that CTRL-T (SIGINFO on BSD systems) cannot be handled by
+	 *  using signal(SIGINFO, ...), since the terminal is in non-canonical
+	 *  mode.
+	 */
+	console_init_main(emul);
+
+	signal(SIGINT, debugger_activate);
+	signal(SIGCONT, console_sigcont);
+
+	/*  Initialize all CPUs in all machines:  */
+	for (int j = 0; j < emul->n_machines; j++)
+		cpu_run_init(emul->machines[j]);
+
+	/*  TODO: Generalize:  */
+	if (emul->machines[0]->show_trace_tree)
+		cpu_functioncall_trace(emul->machines[0]->cpus[0],
+		    emul->machines[0]->cpus[0]->pc);
+
+	/*  Start emulated clocks:  */
+	timer_start();
+
+
+	/*
+	 *  MAIN LOOP:
+	 *
+	 *  Run instructions from each cpu in each machine.
+	 *
+	 *  TODO:
+	 *	Rewrite the X11/console flush to use a timer (?).
+	 */
+	while (!emul_shutdown) {
+		struct cpu *bootcpu = emul->machines[0]->cpus[
+		    emul->machines[0]->bootstrap_cpu];
+
+		bool any_cpu_running = false;
+		bool idling = true;
+		for (int i = 0; i < emul->n_machines; ++i) {
+			for (int j = 0; j < emul->machines[i]->ncpus; ++j) {
+				if (emul->machines[i]->cpus[j]->running) {
+					any_cpu_running = true;
+					if (!emul->machines[i]->cpus[j]->wants_to_idle)
+						idling = false;
+				}
+			}
+		}
+
+		if (any_cpu_running && idling) {
+			x11_check_event(emul);
+			console_flush();
+
+			if (console_any_input_available(emul)) {
+				debugmsg(SUBSYS_EMUL, "idle", VERBOSITY_DEBUG, "not idling; console input is available");
+			} else {
+				debugmsg(SUBSYS_EMUL, "idle", VERBOSITY_DEBUG, "idling the host processor...");
+
+				// Attempt to "idle the host", by sleeping for a short while.
+				// usleep() may return EINTR, if a signal was just delivered.
+				// In that case, naively try again once.
+				if (usleep(500) != 0) {
+					debugmsg(SUBSYS_EMUL, "idle", VERBOSITY_DEBUG, "usleep() interrupted once. retrying.");
+					if (usleep(500) != 0)
+						debugmsg(SUBSYS_EMUL, "idle", VERBOSITY_DEBUG, "usleep() interrupted twice! not retrying.");
+				}
+			}
+		}
+
+		/*  Flush X11 and serial console output every now and then:  */
+		if (bootcpu->ninstrs > bootcpu->ninstrs_flush + (1<<19)) {
+			x11_check_event(emul);
+			console_flush();
+			bootcpu->ninstrs_flush = bootcpu->ninstrs;
+		}
+
+		if (bootcpu->ninstrs > bootcpu->ninstrs_show + (1<<25)) {
+			bootcpu->ninstrs_since_gettimeofday +=
+			    (bootcpu->ninstrs - bootcpu->ninstrs_show);
+			cpu_show_cycles(emul->machines[0], false);
+			bootcpu->ninstrs_show = bootcpu->ninstrs;
+		}
+		
+		if (about_to_enter_single_step) {
+			single_step = true;
+			about_to_enter_single_step = false;
+		}
+
+		if (single_step)
+			debugger();
+
+		if (emul_shutdown)
+			break;
+
+		emul_executing = true;
+
+		bool any_machine_still_running = false;
+		for (int i = 0; i < emul->n_machines; i++)
+			any_machine_still_running |= machine_run(emul->machines[i]);
+
+		emul_executing = false;
+
+		if (!any_machine_still_running) {
+			if (debugger_enter_at_end_of_run) {
+				debugmsg(SUBSYS_EMUL, NULL, VERBOSITY_WARNING, "All machines stopped.");
+				debugger_reset();
+				single_step = true;
+			} else {
+				break;
+			}
+		}
+	}
+
+
+	/*  Stop any running timers:  */
+	timer_stop();
+
+	/*  Deinitialize all CPUs in all machines:  */
+	for (int j = 0; j <emul->n_machines; j++)
+		cpu_run_deinit(emul->machines[j]);
+
+	console_deinit_main();
+}
+
+
diff -Nru gxemul-0.6.2/src/core/emul_parse.c gxemul-0.7.0+dfsg/src/core/emul_parse.c
--- gxemul-0.6.2/src/core/emul_parse.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/core/emul_parse.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,756 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Set up an emulation by parsing a config file.
+ *
+ *  TODO: REWRITE THIS FROM SCRATCH! :-)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "diskimage.h"
+#include "emul.h"
+#include "machine.h"
+#include "misc.h"
+#include "net.h"
+
+
+#define is_word_char(ch)	( \
+	(ch >= 'a' && ch <= 'z') || (ch >= 'A' && ch <= 'Z') || \
+	ch == '_' || ch == '$' || (ch >= '0' && ch <= '9') )
+
+#define	MAX_WORD_LEN		200
+
+#define	EXPECT_WORD			1
+#define	EXPECT_LEFT_PARENTHESIS		2
+#define	EXPECT_RIGHT_PARENTHESIS	4
+
+static int parenthesis_level = 0;
+
+
+/*
+ *  read_one_word():
+ *
+ *  Reads the file f until it has read a complete word. Whitespace is ignored,
+ *  and also any exclamation mark ('!') and anything following an exclamation
+ *  mark on a line.
+ *
+ *  Used internally by emul_parse_config().
+ */
+static void read_one_word(FILE *f, char *buf, int buflen, int *line,
+	int expect)
+{
+	int ch;
+	int done = 0;
+	int curlen = 0;
+	int in_word = 0;
+
+	while (!done) {
+		if (curlen >= buflen - 1)
+			break;
+
+		ch = fgetc(f);
+		if (ch == EOF)
+			break;
+
+		if (in_word) {
+			if (is_word_char(ch)) {
+				buf[curlen++] = ch;
+				if (curlen == buflen - 1)
+					done = 1;
+				continue;
+			} else {
+				if (ungetc(ch, f) == EOF) {
+					fatal("ungetc() failed?\n");
+					exit(1);
+				}
+				break;
+			}
+		}
+
+		if (ch == '\n') {
+			(*line) ++;
+			continue;
+		}
+
+		if (ch == '\r')
+			continue;
+
+		if (ch == '!') {
+			/*  Skip until newline:  */
+			while (ch != '\n' && ch != EOF)
+				ch = fgetc(f);
+			if (ch == '\n')
+				(*line) ++;
+			continue;
+		}
+
+		if (ch == '{') {
+			int depth = 1;
+
+			/*  Skip until '}':  */
+			while (depth > 0) {
+				ch = fgetc(f);
+				if (ch == '\n')
+					(*line) ++;
+				if (ch == '{')
+					depth ++;
+				if (ch == '}')
+					depth --;
+				if (ch == EOF) {
+					fatal("line %i: unexpected EOF inside"
+					    " a nested comment\n", *line);
+					exit(1);
+				}
+			}
+			continue;
+		}
+
+		/*  Whitespace?  */
+		if (ch <= ' ')
+			continue;
+
+		if (ch == '"' || ch == '\'') {
+			/*  This is a quoted word.  */
+			int start_ch = ch;
+
+			if (expect & EXPECT_LEFT_PARENTHESIS) {
+				fatal("unexpected character '%c', line %i\n",
+				    ch, *line);
+				exit(1);
+			}
+
+			while (curlen < buflen - 1) {
+				ch = fgetc(f);
+				if (ch == '\n') {
+					fatal("line %i: newline inside"
+					    " quotes?\n", *line);
+					exit(1);
+				}
+				if (ch == EOF) {
+					fatal("line %i: EOF inside a quoted"
+					    " string?\n", *line);
+					exit(1);
+				}
+				if (ch == start_ch)
+					break;
+				buf[curlen++] = ch;
+			}
+			break;
+		}
+
+		if ((expect & EXPECT_WORD) && is_word_char(ch)) {
+			buf[curlen++] = ch;
+			in_word = 1;
+			if (curlen == buflen - 1)
+				done = 1;
+		} else {
+			if ((expect & EXPECT_LEFT_PARENTHESIS) && ch == '(') {
+				parenthesis_level ++;
+				buf[curlen++] = ch;
+				break;
+			}
+			if ((expect & EXPECT_RIGHT_PARENTHESIS) && ch == ')') {
+				parenthesis_level --;
+				buf[curlen++] = ch;
+				break;
+			}
+
+			fatal("unexpected character '%c', line %i\n",
+			    ch, *line);
+			exit(1);
+		}
+	}
+
+	buf[curlen] = '\0';
+}
+
+
+#define	PARSESTATE_NONE			0
+#define	PARSESTATE_EMUL			1
+#define	PARSESTATE_NET			2
+#define	PARSESTATE_MACHINE		3
+
+static char cur_net_tapdev[50];
+static char cur_net_ipv4net[50];
+static char cur_net_ipv4len[50];
+static char cur_net_local_port[10];
+#define	MAX_N_REMOTE		20
+#define	MAX_REMOTE_LEN		100
+static char *cur_net_remote[MAX_N_REMOTE];
+static int cur_net_n_remote;
+
+static char cur_machine_name[50];
+static char cur_machine_cpu[50];
+static char cur_machine_type[50];
+static char cur_machine_subtype[50];
+static char cur_machine_bootname[150];
+static char cur_machine_bootarg[250];
+static char cur_machine_slowsi[10];
+static char cur_machine_prom_emulation[10];
+static char cur_machine_use_x11[10];
+static char cur_machine_x11_scaledown[10];
+static char cur_machine_byte_order[20];
+static char cur_machine_random_mem[10];
+static char cur_machine_random_cpu[10];
+static char cur_machine_force_netboot[10];
+static char cur_machine_start_paused[10];
+static char cur_machine_ncpus[10];
+static char cur_machine_n_gfx_cards[10];
+static char cur_machine_serial_nr[10];
+static char cur_machine_emulated_hz[10];
+static char cur_machine_memory[10];
+#define	MAX_N_LOAD		15
+#define	MAX_LOAD_LEN		2000
+static char *cur_machine_load[MAX_N_LOAD];
+static int cur_machine_n_load;
+#define	MAX_N_DISK		10
+#define	MAX_DISK_LEN		2000
+static char *cur_machine_disk[MAX_N_DISK];
+static int cur_machine_n_disk;
+#define	MAX_N_DEVICE		20
+#define	MAX_DEVICE_LEN		400
+static char *cur_machine_device[MAX_N_DISK];
+static int cur_machine_n_device;
+#define	MAX_N_X11_DISP		5
+#define	MAX_X11_DISP_LEN	1000
+static char *cur_machine_x11_disp[MAX_N_X11_DISP];
+static int cur_machine_n_x11_disp;
+
+#define WORD(w,var) {						\
+		if (strcmp(word, w) == 0) {			\
+			read_one_word(f, word, maxbuflen,	\
+			    line, EXPECT_LEFT_PARENTHESIS);	\
+			read_one_word(f, var, sizeof(var),	\
+			    line, EXPECT_WORD);			\
+			read_one_word(f, word, maxbuflen,	\
+			    line, EXPECT_RIGHT_PARENTHESIS);	\
+			return;					\
+		}						\
+	}
+
+static void parse__machine(struct emul *e, FILE *f, int *in_emul, int *line,
+	int *parsestate, char *word, size_t maxbuflen);
+
+
+/*
+ *  parse_on_off():
+ *
+ *  Returns 1 for "on", "yes", "enable", or "1".
+ *  Returns 0 for "off", "no", "disable", or "0".
+ *  Prints a fatal warning and exit()s for other values.
+ */
+int parse_on_off(char *s)
+{
+	if (strcasecmp(s, "on") == 0 || strcasecmp(s, "yes") == 0 ||
+	    strcasecmp(s, "enable") == 0 || strcasecmp(s, "1") == 0)
+		return 1;
+	if (strcasecmp(s, "off") == 0 || strcasecmp(s, "no") == 0 ||
+	    strcasecmp(s, "disable") == 0 || strcasecmp(s, "0") == 0)
+		return 0;
+
+	fprintf(stderr, "parse_on_off(): WARNING: unknown value '%s'\n", s);
+
+	return 0;
+}
+
+
+/*
+ *  parse__emul():
+ *
+ *  name, net, machine
+ */
+static void parse__emul(struct emul *e, FILE *f, int *in_emul, int *line,
+	int *parsestate, char *word, size_t maxbuflen)
+{
+	if (word[0] == ')') {
+		*parsestate = PARSESTATE_NONE;
+		return;
+	}
+
+	if (strcmp(word, "name") == 0) {
+		char tmp[200];
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_LEFT_PARENTHESIS);
+		read_one_word(f, tmp, sizeof(tmp), line, EXPECT_WORD);
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_RIGHT_PARENTHESIS);
+		if (e->name != NULL) {
+			free(e->name);
+			e->name = NULL;
+		}
+		CHECK_ALLOCATION(e->name = strdup(tmp));
+		debug("name: \"%s\"\n", e->name);
+		return;
+	}
+
+	if (strcmp(word, "net") == 0) {
+		*parsestate = PARSESTATE_NET;
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_LEFT_PARENTHESIS);
+
+		/*  Default net:  */
+		strlcpy(cur_net_tapdev, "", sizeof(cur_net_tapdev));
+		strlcpy(cur_net_ipv4net, NET_DEFAULT_IPV4_MASK,
+		    sizeof(cur_net_ipv4net));
+		snprintf(cur_net_ipv4len, sizeof(cur_net_ipv4len), "%i",
+		    NET_DEFAULT_IPV4_LEN);
+		strlcpy(cur_net_local_port, "", sizeof(cur_net_local_port));
+		cur_net_n_remote = 0;
+		return;
+	}
+
+	if (strcmp(word, "machine") == 0) {
+		*parsestate = PARSESTATE_MACHINE;
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_LEFT_PARENTHESIS);
+
+		/*  A "zero state":  */
+		cur_machine_name[0] = '\0';
+		cur_machine_cpu[0] = '\0';
+		cur_machine_type[0] = '\0';
+		cur_machine_subtype[0] = '\0';
+		cur_machine_bootname[0] = '\0';
+		cur_machine_bootarg[0] = '\b';	// HACK
+		cur_machine_bootarg[1] = '\0';	// HACK
+		cur_machine_n_load = 0;
+		cur_machine_n_disk = 0;
+		cur_machine_n_device = 0;
+		cur_machine_n_x11_disp = 0;
+		cur_machine_slowsi[0] = '\0';
+		cur_machine_prom_emulation[0] = '\0';
+		cur_machine_use_x11[0] = '\0';
+		cur_machine_x11_scaledown[0] = '\0';
+		cur_machine_byte_order[0] = '\0';
+		cur_machine_random_mem[0] = '\0';
+		cur_machine_random_cpu[0] = '\0';
+		cur_machine_force_netboot[0] = '\0';
+		cur_machine_start_paused[0] = '\0';
+		cur_machine_ncpus[0] = '\0';
+		cur_machine_n_gfx_cards[0] = '\0';
+		cur_machine_serial_nr[0] = '\0';
+		cur_machine_emulated_hz[0] = '\0';
+		cur_machine_memory[0] = '\0';
+		return;
+	}
+
+	fatal("line %i: not expecting '%s' in an 'emul' section\n",
+	    *line, word);
+	exit(1);
+}
+
+
+/*
+ *  parse__net():
+ *
+ *  Simple words: ipv4net, ipv4len, local_port
+ *
+ *  Complex: add_remote
+ *
+ *  TODO: more words? for example an option to disable the gateway? that would
+ *  have to be implemented correctly in src/net.c first.
+ */
+static void parse__net(struct emul *e, FILE *f, int *in_emul, int *line,
+	int *parsestate, char *word, size_t maxbuflen)
+{
+	int i;
+
+	if (word[0] == ')') {
+		/*  Finished with the 'net' section. Let's create the net:  */
+		if (e->net != NULL) {
+			fatal("line %i: more than one net isn't really "
+			    "supported yet\n", *line);
+			exit(1);
+		}
+
+		if (!cur_net_local_port[0])
+			strlcpy(cur_net_local_port, "0",
+			    sizeof(cur_net_local_port));
+
+		e->net = net_init(e, NET_INIT_FLAG_GATEWAY,
+		    cur_net_tapdev[0] ? cur_net_tapdev : NULL,
+		    cur_net_ipv4net, atoi(cur_net_ipv4len),
+		    cur_net_remote, cur_net_n_remote,
+		    atoi(cur_net_local_port), NULL);
+
+		if (e->net == NULL) {
+			fatal("line %i: fatal error: could not create"
+			    " the net (?)\n", *line);
+			exit(1);
+		}
+
+		for (i=0; i<cur_net_n_remote; i++) {
+			free(cur_net_remote[i]);
+			cur_net_remote[i] = NULL;
+		}
+
+		*parsestate = PARSESTATE_EMUL;
+		return;
+	}
+
+	WORD("tapdev", cur_net_tapdev);
+	WORD("ipv4net", cur_net_ipv4net);
+	WORD("ipv4len", cur_net_ipv4len);
+	WORD("local_port", cur_net_local_port);
+
+	if (strcmp(word, "add_remote") == 0) {
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_LEFT_PARENTHESIS);
+		if (cur_net_n_remote >= MAX_N_REMOTE) {
+			fprintf(stderr, "too many remote networks\n");
+			exit(1);
+		}
+
+		CHECK_ALLOCATION(cur_net_remote[cur_net_n_remote] =
+		    (char *) malloc(MAX_REMOTE_LEN));
+		read_one_word(f, cur_net_remote[cur_net_n_remote],
+		    MAX_REMOTE_LEN, line, EXPECT_WORD);
+		cur_net_n_remote ++;
+		read_one_word(f, word, maxbuflen, line,
+		    EXPECT_RIGHT_PARENTHESIS);
+		return;
+	}
+
+	fatal("line %i: not expecting '%s' in a 'net' section\n", *line, word);
+	exit(1);
+}
+
+
+/*
+ *  parse__machine():
+ */
+static void parse__machine(struct emul *e, FILE *f, int *in_emul, int *line,
+	int *parsestate, char *word, size_t maxbuflen)
+{
+	int r, i;
+
+	if (word[0] == ')') {
+		/*  Finished with the 'machine' section.  */
+		struct machine *m;
+
+		if (!cur_machine_name[0])
+			strlcpy(cur_machine_name, "no_name",
+			    sizeof(cur_machine_name));
+
+		m = emul_add_machine(e, cur_machine_name);
+
+		r = machine_name_to_type(cur_machine_type, cur_machine_subtype,
+		    &m->machine_type, &m->machine_subtype);
+		if (!r)
+			exit(1);
+
+		if (cur_machine_cpu[0])
+			CHECK_ALLOCATION(m->cpu_name = strdup(cur_machine_cpu));
+
+		if (!cur_machine_use_x11[0])
+			strlcpy(cur_machine_use_x11, "no",
+			    sizeof(cur_machine_use_x11));
+		m->x11_md.in_use = parse_on_off(cur_machine_use_x11);
+
+		if (!cur_machine_prom_emulation[0])
+			strlcpy(cur_machine_prom_emulation, "yes",
+			    sizeof(cur_machine_prom_emulation));
+		m->prom_emulation = parse_on_off(cur_machine_prom_emulation);
+
+		if (!cur_machine_random_mem[0])
+			strlcpy(cur_machine_random_mem, "no",
+			    sizeof(cur_machine_random_mem));
+		m->random_mem_contents =
+		    parse_on_off(cur_machine_random_mem);
+
+		if (!cur_machine_random_cpu[0])
+			strlcpy(cur_machine_random_cpu, "no",
+			    sizeof(cur_machine_random_cpu));
+		m->use_random_bootstrap_cpu =
+		    parse_on_off(cur_machine_random_cpu);
+
+		m->byte_order_override = NO_BYTE_ORDER_OVERRIDE;
+		if (cur_machine_byte_order[0]) {
+			if (strncasecmp(cur_machine_byte_order, "big", 3) == 0)
+				m->byte_order_override = EMUL_BIG_ENDIAN;
+			else if (strncasecmp(cur_machine_byte_order, "little",
+			    6) == 0)
+				m->byte_order_override = EMUL_LITTLE_ENDIAN;
+			else {
+				fatal("Byte order must be big-endian or"
+				    " little-endian\n");
+				exit(1);
+			}
+		}
+
+		if (!cur_machine_force_netboot[0])
+			strlcpy(cur_machine_force_netboot, "no",
+			    sizeof(cur_machine_force_netboot));
+		m->force_netboot = parse_on_off(cur_machine_force_netboot);
+
+		if (!cur_machine_start_paused[0])
+			strlcpy(cur_machine_start_paused, "no",
+			    sizeof(cur_machine_start_paused));
+		m->start_paused = parse_on_off(cur_machine_start_paused) ? true : false;
+
+		/*  NOTE: Default nr of CPUs is 0:  */
+		if (!cur_machine_ncpus[0])
+			strlcpy(cur_machine_ncpus, "0",
+			    sizeof(cur_machine_ncpus));
+		m->ncpus = atoi(cur_machine_ncpus);
+
+		if (cur_machine_n_gfx_cards[0])
+			m->n_gfx_cards = atoi(cur_machine_n_gfx_cards);
+
+		if (cur_machine_serial_nr[0]) {
+			m->serial_nr = atoi(cur_machine_serial_nr);
+			e->next_serial_nr = m->serial_nr+1;
+		}
+
+		if (cur_machine_emulated_hz[0]) {
+			m->emulated_hz = mystrtoull(cur_machine_emulated_hz,
+			    NULL, 0);
+		}
+
+		/*  NOTE: Default nr of CPUs is 0:  */
+		if (!cur_machine_memory[0])
+			strlcpy(cur_machine_memory, "0",
+			    sizeof(cur_machine_memory));
+		m->physical_ram_in_mb = atoi(cur_machine_memory);
+
+		if (!cur_machine_x11_scaledown[0])
+			m->x11_md.scaledown = 1;
+		else {
+			m->x11_md.scaledown = atoi(cur_machine_x11_scaledown);
+			if (m->x11_md.scaledown < 0) {
+				m->x11_md.scaleup = 0 - m->x11_md.scaledown;
+				m->x11_md.scaledown = 1;
+			}
+			if (m->x11_md.scaledown < 1) {
+				fprintf(stderr, "Invalid scaledown value"
+				    " (%i)\n", m->x11_md.scaledown);
+				exit(1);
+			}
+		}
+
+		for (i=0; i<cur_machine_n_disk; i++) {
+			if (diskimage_add(m, cur_machine_disk[i]) < 0) {
+				debugmsg(SUBSYS_EMUL, "", VERBOSITY_ERROR,
+				    "TODO");
+				exit(1);
+			}
+
+			free(cur_machine_disk[i]);
+			cur_machine_disk[i] = NULL;
+		}
+
+		m->boot_kernel_filename = strdup(cur_machine_bootname);
+
+		// HACK: This allows bootarg("") to be treated as
+		// something that is explicitly set. Needed by e.g. Sprite.
+		if (cur_machine_bootarg[0] != '\b')
+			m->boot_string_argument = strdup(cur_machine_bootarg);
+
+		for (i=0; i<cur_machine_n_x11_disp; i++) {
+			m->x11_md.n_display_names ++;
+			CHECK_ALLOCATION(m->x11_md.display_names = (char **) realloc(
+			    m->x11_md.display_names, m->x11_md.n_display_names
+			    * sizeof(char *)));
+			CHECK_ALLOCATION(m->x11_md.display_names[
+			    m->x11_md.n_display_names-1] =
+			    strdup(cur_machine_x11_disp[i]));
+			free(cur_machine_x11_disp[i]);
+			cur_machine_x11_disp[i] = NULL;
+		}
+
+		emul_machine_setup(m,
+		    cur_machine_n_load, cur_machine_load,
+		    cur_machine_n_device, cur_machine_device);
+
+		for (i=0; i<cur_machine_n_device; i++) {
+			free(cur_machine_device[i]);
+			cur_machine_device[i] = NULL;
+		}
+
+		for (i=0; i<cur_machine_n_load; i++) {
+			free(cur_machine_load[i]);
+			cur_machine_load[i] = NULL;
+		}
+
+		*parsestate = PARSESTATE_EMUL;
+		return;
+	}
+
+	WORD("name", cur_machine_name);
+	WORD("cpu", cur_machine_cpu);
+	WORD("type", cur_machine_type);
+	WORD("subtype", cur_machine_subtype);
+	WORD("bootname", cur_machine_bootname);
+	WORD("bootarg", cur_machine_bootarg);
+	WORD("prom_emulation", cur_machine_prom_emulation);
+	WORD("use_x11", cur_machine_use_x11);
+	WORD("x11_scaledown", cur_machine_x11_scaledown);
+	WORD("byte_order", cur_machine_byte_order);
+	WORD("random_mem_contents", cur_machine_random_mem);
+	WORD("use_random_bootstrap_cpu", cur_machine_random_cpu);
+	WORD("force_netboot", cur_machine_force_netboot);
+	WORD("ncpus", cur_machine_ncpus);
+	WORD("serial_nr", cur_machine_serial_nr);
+	WORD("n_gfx_cards", cur_machine_n_gfx_cards);
+	WORD("emulated_hz", cur_machine_emulated_hz);
+	WORD("memory", cur_machine_memory);
+	WORD("start_paused", cur_machine_start_paused);
+
+	if (strcmp(word, "load") == 0) {
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_LEFT_PARENTHESIS);
+		if (cur_machine_n_load >= MAX_N_LOAD) {
+			fprintf(stderr, "too many loads\n");
+			exit(1);
+		}
+		CHECK_ALLOCATION(cur_machine_load[cur_machine_n_load] =
+		    (char*) malloc(MAX_LOAD_LEN));
+		read_one_word(f, cur_machine_load[cur_machine_n_load],
+		    MAX_LOAD_LEN, line, EXPECT_WORD);
+		cur_machine_n_load ++;
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_RIGHT_PARENTHESIS);
+		return;
+	}
+
+	if (strcmp(word, "disk") == 0) {
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_LEFT_PARENTHESIS);
+		if (cur_machine_n_disk >= MAX_N_DISK) {
+			fprintf(stderr, "too many disks\n");
+			exit(1);
+		}
+		CHECK_ALLOCATION(cur_machine_disk[cur_machine_n_disk] =
+		    (char*) malloc(MAX_DISK_LEN));
+		read_one_word(f, cur_machine_disk[cur_machine_n_disk],
+		    MAX_DISK_LEN, line, EXPECT_WORD);
+		cur_machine_n_disk ++;
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_RIGHT_PARENTHESIS);
+		return;
+	}
+
+	if (strcmp(word, "device") == 0) {
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_LEFT_PARENTHESIS);
+		if (cur_machine_n_device >= MAX_N_DEVICE) {
+			fprintf(stderr, "too many devices\n");
+			exit(1);
+		}
+		CHECK_ALLOCATION(cur_machine_device[cur_machine_n_device] =
+		    (char*) malloc(MAX_DEVICE_LEN));
+		read_one_word(f, cur_machine_device[cur_machine_n_device],
+		    MAX_DEVICE_LEN, line, EXPECT_WORD);
+		cur_machine_n_device ++;
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_RIGHT_PARENTHESIS);
+		return;
+	}
+
+	if (strcmp(word, "add_x11_display") == 0) {
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_LEFT_PARENTHESIS);
+		if (cur_machine_n_x11_disp >= MAX_N_X11_DISP) {
+			fprintf(stderr, "too many x11 displays\n");
+			exit(1);
+		}
+		CHECK_ALLOCATION(cur_machine_x11_disp[cur_machine_n_x11_disp] =
+		    (char*) malloc(MAX_X11_DISP_LEN));
+		read_one_word(f, cur_machine_x11_disp[cur_machine_n_x11_disp],
+		    MAX_X11_DISP_LEN, line, EXPECT_WORD);
+		cur_machine_n_x11_disp ++;
+		read_one_word(f, word, maxbuflen,
+		    line, EXPECT_RIGHT_PARENTHESIS);
+		return;
+	}
+
+	fatal("line %i: not expecting '%s' in a 'machine' section\n",
+	    *line, word);
+	exit(1);
+}
+
+
+/*
+ *  emul_parse_config():
+ *
+ *  Set up an emulation by parsing a config file.
+ */
+void emul_parse_config(struct emul *e, char *fname)
+{
+	FILE *f = fopen(fname, "r");
+	char word[MAX_WORD_LEN];
+	int in_emul = 0;
+	int line = 1;
+	int parsestate = PARSESTATE_EMUL;
+
+	/*  debug("emul_parse_config()\n");  */
+	if (f == NULL) {
+		perror(fname);
+		exit(1);
+	}
+
+	while (!feof(f)) {
+		read_one_word(f, word, sizeof(word), &line,
+		    EXPECT_WORD | EXPECT_RIGHT_PARENTHESIS);
+		if (!word[0])
+			break;
+
+		/*  debug("word = '%s'\n", word);  */
+
+		switch (parsestate) {
+		case PARSESTATE_EMUL:
+			parse__emul(e, f, &in_emul, &line, &parsestate,
+			    word, sizeof(word));
+			break;
+		case PARSESTATE_NET:
+			parse__net(e, f, &in_emul, &line, &parsestate,
+			    word, sizeof(word));
+			break;
+		case PARSESTATE_MACHINE:
+			parse__machine(e, f, &in_emul, &line, &parsestate,
+			    word, sizeof(word));
+			break;
+		case PARSESTATE_NONE:
+			break;
+		default:
+			fatal("INTERNAL ERROR in emul_parse.c ("
+			    "parsestate %i is not imlemented yet?)\n",
+			    parsestate);
+			exit(1);
+		}
+	}
+
+	if (parenthesis_level != 0) {
+		fatal("EOF but not enough right parentheses?\n");
+		exit(1);
+	}
+
+	fclose(f);
+}
+
diff -Nru gxemul-0.6.2/src/core/float_emul.c gxemul-0.7.0+dfsg/src/core/float_emul.c
--- gxemul-0.6.2/src/core/float_emul.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/core/float_emul.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,316 @@
+/*
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Floating point emulation routines.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#include "float_emul.h"
+#include "misc.h"
+
+
+/*  #define IEEE_DEBUG  */
+
+
+/*
+ *  ieee_interpret_float_value():
+ *
+ *  Interprets a float value from binary IEEE format into an ieee_float_value
+ *  struct.
+ */
+void ieee_interpret_float_value(uint64_t x, struct ieee_float_value *fvp,
+	int fmt)
+{
+	memset(fvp, 0, sizeof(struct ieee_float_value));
+
+	int n_frac = 0, n_exp = 0;
+	int i, nan, sign = 0, exponent;
+	double fraction;
+
+	/*  n_frac and n_exp:  */
+	switch (fmt) {
+	case IEEE_FMT_S:	n_frac = 23; n_exp = 8; break;
+	case IEEE_FMT_W:	n_frac = 31; n_exp = 0; break;
+	case IEEE_FMT_D:	n_frac = 52; n_exp = 11; break;
+	case IEEE_FMT_L:	n_frac = 63; n_exp = 0; break;
+	default:fatal("ieee_interpret_float_value(): "
+		    "unimplemented format %i\n", fmt);
+	}
+
+	/*  Get the Exponent:  */
+	exponent = 0;
+	switch (fmt) {
+	case IEEE_FMT_W:
+		x &= 0xffffffffULL;
+	case IEEE_FMT_L:
+		break;
+	case IEEE_FMT_S:
+		x &= 0xffffffffULL;
+		// fall through
+	case IEEE_FMT_D:
+		exponent = (x >> n_frac) & ((1 << n_exp) - 1);
+		exponent -= (1 << (n_exp-1)) - 1;
+		break;
+	default:fatal("ieee_interpret_float_value(): unimplemented "
+		    "format %i\n", fmt);
+	}
+
+	/*  Is this a Not-A-Number?  */
+	nan = 0;
+	switch (fmt) {
+	case IEEE_FMT_S:
+		sign = (x >> 31) & 1;
+		if ((x & ~0x80000000ULL) == 0x7f800000ULL) {
+			fvp->f = INFINITY;
+			goto zero_or_no_reasonable_result;
+		}
+		if ((x & 0x7f800000ULL) == 0x7f800000ULL)
+			nan = 1;
+		break;
+	case IEEE_FMT_D:
+		sign = (x >> 63) & 1;
+		if ((x & ~0x8000000000000000ULL) == 0x7ff0000000000000ULL) {
+			fvp->f = INFINITY;
+			goto zero_or_no_reasonable_result;
+		}
+		if ((x & 0x7ff0000000000000ULL) == 0x7ff0000000000000ULL)
+			nan = 1;
+		break;
+	}
+
+	if (nan) {
+		fvp->f = NAN;
+		goto no_reasonable_result;
+	}
+
+	/*  Calculate the fraction:  */
+	fraction = 0.0;
+
+	switch (fmt) {
+
+	case IEEE_FMT_W:
+		{
+			int32_t r_int = x;
+			fraction = r_int;
+		}
+		break;
+
+	case IEEE_FMT_L:
+		{
+			int64_t r_int = x;
+			fraction = r_int;
+		}
+		break;
+
+	case IEEE_FMT_S:
+	case IEEE_FMT_D:
+		if (x == 0 ||
+		    (fmt == IEEE_FMT_D && x == 0x8000000000000000ULL) ||
+		    (fmt == IEEE_FMT_S && x == 0x80000000ULL)) {
+			fvp->f = 0.0;
+			goto zero_or_no_reasonable_result;
+		}
+
+		fraction = 0.0;
+		for (i=0; i<n_frac; i++) {
+			int bit = (x >> i) & 1;
+			fraction /= 2.0;
+			if (bit)
+				fraction += 1.0;
+		}
+
+		/*  Add implicit bit 0:  */
+		fraction = (fraction / 2.0) + 1.0;
+		break;
+
+	default:fatal("ieee_interpret_float_value(): "
+		    "unimplemented format %i\n", fmt);
+	}
+
+	/*  form the value:  */
+	fvp->f = fraction;
+
+#ifdef IEEE_DEBUG
+	fatal("{ ieee: x=%016"PRIx64" => sign=%i exponent=%i frac=%f ",
+	    (uint64_t) x, sign, exponent, fraction);
+#endif
+
+	/*  TODO: this is awful for exponents of large magnitude.  */
+	if (exponent > 0) {
+		/*
+		 *  NOTE / TODO:
+		 *
+		 *  This is an ulgy workaround on Alpha, where it seems that
+		 *  multiplying by 2, 1024 times causes a floating point
+		 *  exception. (Triggered by running for example NetBSD/pmax
+		 *  2.0 emulated on an Alpha host.)
+		 */
+		if (exponent == 1024)
+			fvp->f = INFINITY;
+		else
+			while (exponent-- > 0)
+				fvp->f *= 2.0;
+	} else if (exponent < 0) {
+		while (exponent++ < 0)
+			fvp->f /= 2.0;
+	}
+
+zero_or_no_reasonable_result:
+	if (sign)
+		fvp->f = -fvp->f;
+
+no_reasonable_result:
+	fvp->nan = nan;
+
+#ifdef IEEE_DEBUG
+	fatal("nan=%i (f=%f) }\n", nan, fvp->f);
+#endif
+}
+
+
+/*
+ *  ieee_store_float_value():
+ *
+ *  Generates a 64-bit IEEE-formated value in a specific format.
+ */
+uint64_t ieee_store_float_value(double nf, int fmt)
+{
+	int n_frac = 0, n_exp = 0, signofs = 0, i, exponent;
+	uint64_t r = 0, r2;
+	int64_t r3;
+
+	/*  n_frac and n_exp:  */
+	switch (fmt) {
+	case IEEE_FMT_S:	n_frac = 23; n_exp = 8; signofs = 31; break;
+	case IEEE_FMT_W:	n_frac = 31; n_exp = 0; signofs = 31; break;
+	case IEEE_FMT_D:	n_frac = 52; n_exp = 11; signofs = 63; break;
+	case IEEE_FMT_L:	n_frac = 63; n_exp = 0; signofs = 63; break;
+	default:fatal("ieee_store_float_value(): unimplemented format"
+		    " %i\n", fmt);
+	}
+
+	switch (fmt) {
+	case IEEE_FMT_W:
+	case IEEE_FMT_L:
+		/*
+		 *  This causes an implicit conversion of double to integer.
+		 *  If nf < 0.0, then r2 will begin with a sequence of binary
+		 *  1's, which is ok.
+		 */
+		r3 = (int64_t) nf;
+		r2 = r3;
+		r |= r2;
+		break;
+	case IEEE_FMT_S:
+	case IEEE_FMT_D:
+		/*  sign bit:  */
+		if (signbit(nf)) {
+			r |= ((uint64_t)1 << signofs);
+		}
+
+		// printf("fpclassify(nf) = %i\n", fpclassify(nf));
+		switch (fpclassify(nf)) {
+		case FP_INFINITE:
+			if (fmt == IEEE_FMT_D)
+				r |= 0x7ff0000000000000ULL;
+			else
+				r |= 0x7f800000ULL;
+			break;
+		case FP_NAN:
+			if (fmt == IEEE_FMT_D)
+				r |= 0x7fffffffffffffffULL;
+			else
+				r |= 0x7fffffffULL;
+			break;
+		case FP_NORMAL:
+			if (signbit(nf))
+				nf = -nf;
+
+			/*
+			 *  How to convert back from double to exponent + fraction:
+			 *  The fraction should be 1.xxx, that is
+			 *  1.0 <= fraction < 2.0
+			 *
+			 *  This method is very slow but should work:
+			 *  (TODO: Fix the performance problem!)
+			 */
+			exponent = 0;
+			while (nf < 1.0 && exponent > -1023) {
+				nf *= 2.0;
+				exponent --;
+			}
+			while (nf >= 2.0 && exponent < 1023) {
+				nf /= 2.0;
+				exponent ++;
+			}
+
+			/*  Here:   1.0 <= nf < 2.0  */
+			nf -= 1.0;	/*  remove implicit first bit  */
+			for (i=n_frac-1; i>=0; i--) {
+				nf *= 2.0;
+				if (nf >= 1.0) {
+					r |= ((uint64_t)1 << i);
+					nf -= 1.0;
+				}
+			}
+
+			/*  Insert the exponent into the resulting word:  */
+			/*  (First bias, then make sure it's within range)  */
+			exponent += (((uint64_t)1 << (n_exp-1)) - 1);
+			if (exponent < 0)
+				exponent = 0;
+			if (exponent >= ((int64_t)1 << n_exp))
+				exponent = ((int64_t)1 << n_exp) - 1;
+			r |= (uint64_t)exponent << n_frac;
+
+			/*  Special case for 0.0:  */
+			if (exponent == 0)
+				r = 0;
+			break;
+		case FP_SUBNORMAL:
+			// TODO
+			break;
+		case FP_ZERO:
+			// r already has zeros in the lowest bits. Done.
+			break;
+		}
+		break;
+	default:/*  TODO  */
+		fatal("ieee_store_float_value(): unimplemented format %i\n",
+		    fmt);
+	}
+
+	if (fmt == IEEE_FMT_S || fmt == IEEE_FMT_W)
+		r = (uint32_t) r;
+
+	return r;
+}
+
diff -Nru gxemul-0.6.2/src/core/interrupt.c gxemul-0.7.0+dfsg/src/core/interrupt.c
--- gxemul-0.6.2/src/core/interrupt.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/core/interrupt.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,286 @@
+/*
+ *  Copyright (C) 2006-2019  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  The interrupt subsystem.
+ *
+ *  Interrupts have a "path", e.g. "machine[0].cpu.5". A device which
+ *  wishes to cause this interrupt needs to connect to it.
+ *
+ *  The possible interrupt paths are registered by CPUs, interrupt controllers,
+ *  etc., that have a way of receiving interrupt requests. The physical
+ *  version of an interrupt path is usually a "pin" on the CPU, or similar.
+ *
+ *  Once connected, the interrupt can be asserted or deasserted.
+ *
+ *  For examples on how it is used, see the various devices in src/devices/.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "interrupt.h"
+#include "misc.h"
+
+
+/*  #define INTERRUPT_DEBUG  */
+
+
+struct interrupt_handler {
+	struct interrupt	templ;
+	int			nr_of_exclusive_users;
+	int			nr_of_nonexclusive_users;
+};
+
+
+static int nr_of_interrupt_handlers = 0;
+static struct interrupt_handler *interrupt_handlers = NULL;
+
+
+/*
+ *  Dummy interrupt assert/deassert for "no interrupt" interrupts:
+ */
+static void no_interrupt_assert(struct interrupt *i) { }
+static void no_interrupt_deassert(struct interrupt *i) { }
+
+
+/*
+ *  interrupt_handler_register():
+ *
+ *  Add an interrupt handler to the interrupt subsystem. The template
+ *  needs to have all members set.
+ *
+ *  Name is of the form "machine[0].cpu[0].irq[3].isa[14]" etc.
+ *
+ *  If there already is a handler with this name, the emulator aborts.
+ */
+void interrupt_handler_register(struct interrupt *templ)
+{
+	int i;
+
+#ifdef INTERRUPT_DEBUG
+	printf("interrupt_handler_register(\"%s\")\n", templ->name);
+#endif
+
+	/*  See if the name is already registered:  */
+	for (i=0; i<nr_of_interrupt_handlers; i++) {
+		if (strcmp(templ->name,
+		    interrupt_handlers[i].templ.name) != 0)
+			continue;
+
+		fatal("\ninterrupt_handler_register(): An interrupt handler"
+		    " using the name '%s' is already registered.\n",
+		    templ->name);
+		exit(1);
+	}
+
+	nr_of_interrupt_handlers ++;
+	CHECK_ALLOCATION(interrupt_handlers = 
+	    (struct interrupt_handler *) realloc(interrupt_handlers,
+	    nr_of_interrupt_handlers * sizeof(struct interrupt_handler)));
+
+	interrupt_handlers[nr_of_interrupt_handlers-1].templ = *templ;
+	CHECK_ALLOCATION(interrupt_handlers[nr_of_interrupt_handlers-1].
+	    templ.name = strdup(templ->name));
+}
+
+
+/*
+ *  interrupt_handler_remove():
+ *
+ *  Remove an interrupt handler from the interrupt subsystem. If there are
+ *  still connected users of this interrupt, then an error message is printed
+ *  and the emulator aborts.
+ */
+void interrupt_handler_remove(const char *name)
+{
+	int i;
+
+#ifdef INTERRUPT_DEBUG
+	printf("interrupt_handler_remove(\"%s\")\n", name);
+#endif
+
+	for (i=0; i<nr_of_interrupt_handlers; i++) {
+		if (strcmp(name, interrupt_handlers[i].templ.name) != 0)
+			continue;
+
+		/*
+		 *  Remove handler i, and return:
+		 */
+		if (interrupt_handlers[i].nr_of_exclusive_users > 0 ||
+		    interrupt_handlers[i].nr_of_nonexclusive_users > 0) {
+			fatal("interrupt_handler_remove(): Attempt to "
+			    "remove interrupt handler '%s' which has %i "
+			    "exclusive and %i non-exclusive users. Aborting.\n",
+			    name, interrupt_handlers[i].nr_of_exclusive_users,
+			    interrupt_handlers[i].nr_of_nonexclusive_users);
+			exit(1);
+		}
+
+		if (i != nr_of_interrupt_handlers-1)
+			memcpy(&interrupt_handlers[i],
+			    &interrupt_handlers[i + 1],
+			    nr_of_interrupt_handlers - i - 1);
+
+		nr_of_interrupt_handlers --;
+
+		return;
+	}
+
+	fatal("interrupt_handler_remove(): '%s' not found? Aborting.\n", name);
+	exit(1);
+}
+
+
+/*
+ *  interrupt_handler_lookup():
+ *
+ *  Scans the list of registered interrupt handlers for a given name. If the
+ *  name is found, the template is filled with valid data, and 1 is returned.
+ *  If the name is not found, 0 is returned.
+ */
+int interrupt_handler_lookup(const char *name, struct interrupt *templ)
+{
+	int i;
+
+#ifdef INTERRUPT_DEBUG
+	printf("interrupt_handler_lookup(\"%s\")\n", name);
+#endif
+
+	if (name[0] == '\0') {
+		/*  No interrupt:  */
+		memset(templ, 0, sizeof(struct interrupt));
+		templ->interrupt_assert = no_interrupt_assert;
+		templ->interrupt_deassert = no_interrupt_deassert;
+	}
+
+	for (i=0; i<nr_of_interrupt_handlers; i++) {
+		if (strcmp(name, interrupt_handlers[i].templ.name) != 0)
+			continue;
+
+		*templ = interrupt_handlers[i].templ;
+		return 1;
+	}
+
+	/*  The 'if' is an ugly hack to prevent a Compaq CC warning.  */
+	if (i >= nr_of_interrupt_handlers) {
+		printf("interrupt_handler_lookup(\"%s\") failed.\n", name);
+
+		printf("Available handler paths are:\n");
+		for (i=0; i<nr_of_interrupt_handlers; i++)
+			printf("    %s\n", interrupt_handlers[i].templ.name);
+
+		printf("Aborting.\n");
+		abort();
+	}
+
+	return 0;
+}
+
+
+/*
+ *  interrupt_connect():
+ *
+ *  Increases the exclusive or nonexclusive nr or users of an interrupt.
+ */
+void interrupt_connect(struct interrupt *in, int exclusive)
+{
+	int i;
+
+#ifdef INTERRUPT_DEBUG
+	printf("interrupt_connect(\"%s\")\n", in->name);
+#endif
+
+	if (in->name == NULL || in->name[0] == '\0')
+		return;
+
+	for (i=0; i<nr_of_interrupt_handlers; i++) {
+		if (strcmp(in->name, interrupt_handlers[i].templ.name) != 0)
+			continue;
+
+		if (exclusive) {
+			interrupt_handlers[i].nr_of_exclusive_users ++;
+			if (interrupt_handlers[i].nr_of_exclusive_users > 1) {
+				fatal("Fatal error in interrupt_connect(): "
+				    "more than 1 exclusive user. Dumping "
+				    "core for backtrace.\n");
+				abort();
+			}
+		} else {
+			interrupt_handlers[i].nr_of_nonexclusive_users ++;
+		}
+
+		return;
+	}
+
+	fatal("Internal error in interrupt_connect(): name '%s' not "
+	    "found? Dumping core for debugging.\n", in->name);
+	abort();
+}
+
+
+/*
+ *  interrupt_disconnect():
+ *
+ *  Decreases the exclusive or nonexclusive nr or users of an interrupt.
+ */
+void interrupt_disconnect(struct interrupt *in, int exclusive)
+{
+	int i;
+
+	if (in->name == NULL || in->name[0] == '\0')
+		return;
+
+	for (i=0; i<nr_of_interrupt_handlers; i++) {
+		if (strcmp(in->name, interrupt_handlers[i].templ.name) != 0)
+			continue;
+
+		if (exclusive) {
+			interrupt_handlers[i].nr_of_exclusive_users --;
+			if (interrupt_handlers[i].nr_of_exclusive_users < 0) {
+				fatal("Fatal error in interrupt_disconnect():"
+				    "nr of exclusive users < 0?\n");
+				exit(1);
+			}
+		} else {
+			interrupt_handlers[i].nr_of_nonexclusive_users --;
+			if (interrupt_handlers[i].nr_of_nonexclusive_users<0) {
+				fatal("Fatal error in interrupt_disconnect():"
+				    "nr of non-exclusive users < 0?\n");
+				exit(1);
+			}
+		}
+
+		return;
+	}
+
+	fatal("Internal error in interrupt_disconnect(): name '%s' not "
+	    "found?\n", in->name);
+	exit(1);
+}
+
+
diff -Nru gxemul-0.6.2/src/core/main.c gxemul-0.7.0+dfsg/src/core/main.c
--- gxemul-0.6.2/src/core/main.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/core/main.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,780 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  GXemul's main entry point.
+ */
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <time.h>
+#include <unistd.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "debugger.h"
+#include "device.h"
+#include "diskimage.h"
+#include "emul.h"
+#include "machine.h"
+#include "misc.h"
+#include "settings.h"
+#include "timer.h"
+
+
+extern bool single_step;
+extern bool debugger_enter_at_end_of_run;
+extern bool enable_colorized_output;
+
+extern int verbose;
+extern int quiet_mode;
+
+extern int optind;
+extern char *optarg;
+
+struct settings *global_settings;
+
+int extra_argc;
+char **extra_argv;
+char *progname;
+
+size_t dyntrans_cache_size = DEFAULT_DYNTRANS_CACHE_SIZE;
+static bool skip_srandom_call = false;
+
+
+/*
+ *  internal_w():
+ *
+ *  For internal use by gxemul itself. Currently only used to launch
+ *  slave consoles.
+ */
+void internal_w(char *arg)
+{
+	if (arg == NULL || strncmp(arg, "W@", 2) != 0) {
+		fprintf(stderr, "-W is for internal use by gxemul,"
+		    " not for manual use.\n");
+		exit(1);
+	}
+
+	arg += 2;
+
+	switch (arg[0]) {
+	case 'S':
+		console_slave(arg + 1);
+		break;
+	default:
+		fprintf(stderr, "internal_w(): UNIMPLEMENTED arg = '%s'\n",
+		    arg);
+	}
+}
+
+
+/*
+ *  print_banner():
+ *
+ *  Prints program startup banner to stdout.
+ */
+static void print_banner()
+{
+	color_banner();
+	printf("GXemul " VERSION"    " COPYRIGHT_MSG"\n" SECONDARY_MSG);
+	printf("Read the source code and/or documentation for other Copyright messages.\n\n");
+	color_normal();
+}
+
+
+/*
+ *  usage():
+ *
+ *  Prints program usage to stdout.
+ */
+static void usage(bool longusage)
+{
+	print_banner();
+
+	printf("Usage: ");
+	color_prompt();
+	printf("%s [machine, other, and general options] [file [...]]\n", progname);
+	color_normal();
+	printf("   or  ");
+	color_prompt();
+	printf("%s [general options] @configfile\n", progname);
+	color_normal();
+	
+	if (!longusage) {
+		printf("\nRun  ");
+		color_prompt();
+		printf("%s -h", progname);
+		color_normal();
+		printf("  for help on command line options.\n");
+		return;
+	}
+
+	printf("\nMachine selection options:\n");
+	printf("  -E t      try to emulate machine type t. (Use -H to get "
+	    "a list of types.)\n");
+	printf("  -e st     try to emulate machine subtype st.\n");
+
+	printf("\nOther options:\n");
+	printf("  -C x      try to emulate a specific CPU. (Use -H to get a "
+	    "list of types.)\n");
+	printf("  -d fname  add fname as a disk image. You can add \"xxx:\""
+	    " as a prefix\n");
+	printf("            where xxx is one or more of the following:\n");
+	printf("                b      specifies that this is the boot"
+	    " device\n");
+	printf("                c      CD-ROM\n");
+	printf("                d      DISK\n");
+	printf("                f      FLOPPY\n");
+	printf("                gH;S;  set geometry to H heads and S"
+	    " sectors-per-track\n");
+	printf("                i      IDE\n");
+	printf("                oOFS;  set base offset to OFS (for ISO9660"
+	    " filesystems)\n");
+	printf("                r      read-only (don't allow changes to the file)\n");
+	printf("                R      don't allow changes to the file, but add a temporary\n");
+	printf("                       overlay to allow guest OS writes (which are lost when\n");
+	printf("                       the emulator exits)\n");
+	printf("                s      SCSI\n");
+	printf("                t      tape\n");
+	printf("                V      add an overlay (also requires explicit ID)\n");
+	printf("                0-7    use a specific ID\n");
+	printf("  -I hz     set the main cpu frequency to hz (not used by "
+	    "all combinations\n            of machines and guest OSes)\n");
+	printf("  -i        display each instruction as it is executed\n");
+	printf("  -J        disable dyntrans instruction combinations\n");
+	printf("  -j name   set the name of the kernel; for DECstation "
+	    "emulation, this passes\n            the name to the bootloader,"
+	    " for example:\n");
+	printf("                -j netbsd     (NetBSD/pmax)      "
+	    "-j bsd      (OpenBSD/pmax)\n");
+	printf("                -j vmsprite   (Sprite/pmax)      "
+	    "-j vmunix   (Ultrix/RISC)\n");
+	printf("            For other emulation modes, if the boot disk is an"
+	    " ISO9660\n            filesystem, -j sets the name of the"
+	    " kernel to load.\n");
+	printf("  -L tapdev enable tap networking using device 'tapdev'\n");
+	printf("  -M m      emulate m MBs of physical RAM\n");
+	printf("  -N        display nr of instructions/second average, at"
+	    " regular intervals\n");
+	printf("  -n nr     set nr of CPUs (for SMP experiments)\n");
+	printf("  -O        force netboot (tftp instead of disk), even when"
+	    " a disk image is\n"
+	    "            present (for DECstation, SGI, and ARC emulation)\n");
+	printf("  -o arg    set the boot argument, for DEC, ARC, or SGI"
+	    " emulation\n");
+	printf("            (default arg for DEC is -a, for ARC/SGI -aN)\n");
+	printf("  -p pc     add a breakpoint (remember to use the '0x' "
+	    "prefix for hex!)\n");
+	printf("  -Q        no built-in PROM emulation  (use this for "
+	    "running ROM images)\n");
+	printf("  -R        use random bootstrap cpu, instead of nr 0\n");
+	printf("  -r        register dumps before every instruction\n");
+	printf("  -S        initialize emulated RAM to random bytes, "
+	    "instead of zeroes\n");
+	printf("  -s f:name write statistics to file 'name', "
+	    "f is one or more of the following:\n");
+	printf("                v    virtual program counter\n");
+	printf("                p    physical equivalent of program counter\n");
+	printf("                i    internal ic->f representation of "
+	    "the program counter\n");
+	printf("            and optionally:\n");
+	printf("                d    disable statistics gathering at "
+	    "startup\n");
+	printf("                o    overwrite instead of append\n");
+	printf("  -T        halt on non-existant memory accesses\n");
+	printf("  -t        show function trace tree\n");
+#ifdef WITH_X11
+	printf("  -X        use X11\n");
+	printf("  -Y n      scale down framebuffer windows by n x n times\n");
+#endif /*  WITH_X11  */
+	printf("  -Z n      set nr of graphics cards, for emulating a "
+	    "dual-head or tripple-head\n"
+	    "            environment (only for DECstation emulation)\n");
+#ifdef WITH_X11
+	printf("  -z disp   add disp as an X11 display to use for framebuffers\n");
+#endif /*  WITH_X11  */
+
+	printf("\nGeneral options:\n");
+	printf("  -A        disable colorized output\n");
+	printf("  -c cmd    add cmd as a command to run before starting "
+	    "the simulation\n");
+	printf("  -D        skip the srandom call at startup\n");
+	printf("  -G        enable colorized output (same as if the CLICOLOR"
+	    " env. var is set)\n");
+	printf("  -H        display a list of possible CPU and "
+	    "machine types\n");
+	printf("  -h        display this help message\n");
+	printf("  -k n      set dyntrans translation caches to n MB (default"
+	    " size is %i MB)\n", DEFAULT_DYNTRANS_CACHE_SIZE / 1048576);
+	printf("  -K        show the debugger prompt instead of exiting, when a simulation ends\n");
+	printf("  -q        quiet mode (don't print startup messages)\n");
+	printf("  -V        start up in the interactive debugger, paused; this also sets -K\n");
+	printf("  -v        increase debug message verbosity\n");
+#ifdef WITH_X11
+	printf("  -x        open up new xterms for emulated serial ports (default is on when\n"
+	       "            using configuration files with multiple machines specified, or\n"
+	       "            when X11 is used, off otherwise)\n");
+#endif /*  WITH_X11  */
+	printf("\n");
+	printf("If you are selecting a machine type to emulate directly "
+	    "on the command line,\nthen you must specify one or more names"
+	    " of files that you wish to load into\n"
+	    "memory. Supported formats are:   ELF a.out ecoff srec syms raw\n"
+	    "where syms is the text produced by running 'nm' (or 'nm -S') "
+	    "on a binary.\n"
+	    "To load a raw binary into memory, add \"address:\" in front "
+	    "of the filename,\n"
+	    "or \"address:skiplen:\" or \"address:skiplen:initialpc:\".\n"
+	    "\nExamples:\n"
+	    "    0xbfc00000:rom.bin                    for a raw ROM image\n"
+	    "    0xbfc00000:0x100:rom.bin              for an image with "
+	    "0x100 bytes header\n"
+	    "    0xbfc00000:0x100:0xbfc00884:rom.bin   "
+	    "start with pc=0xbfc00884\n\n");
+}
+
+
+/*
+ *  get_cmd_args():
+ *
+ *  Reads command line arguments.
+ */
+int get_cmd_args(int argc, char *argv[], struct emul *emul,
+	char ***diskimagesp, int *n_diskimagesp, char **tap_devname)
+{
+	int using_switch_e = 0, using_switch_E = 0;
+	bool using_switch_Z = false;
+	bool using_switch_d = false;
+	bool machine_specific_options_used = false;
+
+	int ch, res;
+
+	char *type = NULL, *subtype = NULL;
+	struct machine *m = emul_add_machine(emul, NULL);
+
+	const char *opts =
+	    "AC:c:Dd:E:e:GHhI:iJj:k:KL:M:Nn:Oo:p:QqRrSs:TtVvW:"
+#ifdef WITH_X11
+	    "XxY:"
+#endif
+	    "Z:z:";
+
+	while ((ch = getopt(argc, argv, opts)) != -1) {
+		switch (ch) {
+		case 'A':
+			enable_colorized_output = false;
+			break;
+		case 'C':
+			CHECK_ALLOCATION(m->cpu_name = strdup(optarg));
+			machine_specific_options_used = true;
+			break;
+		case 'c':
+			emul->n_debugger_cmds ++;
+			CHECK_ALLOCATION(emul->debugger_cmds = (char **)
+			    realloc(emul->debugger_cmds,
+			    emul->n_debugger_cmds * sizeof(char *)));
+			CHECK_ALLOCATION(emul->debugger_cmds[emul->
+			    n_debugger_cmds-1] = strdup(optarg));
+			break;
+		case 'D':
+			skip_srandom_call = true;
+			break;
+		case 'd':
+			/*  diskimage_add() is called further down  */
+			(*n_diskimagesp) ++;
+			CHECK_ALLOCATION( (*diskimagesp) = (char **)
+			    realloc(*diskimagesp,
+			    sizeof(char *) * (*n_diskimagesp)) );
+			CHECK_ALLOCATION( (*diskimagesp)[(*n_diskimagesp) - 1] =
+			    strdup(optarg) );
+			using_switch_d = true;
+			machine_specific_options_used = true;
+			break;
+		case 'E':
+			if (using_switch_E ++ > 0) {
+				fprintf(stderr, "-E already used.\n");
+				exit(1);
+			}
+			type = optarg;
+			machine_specific_options_used = true;
+			break;
+		case 'e':
+			if (using_switch_e ++ > 0) {
+				fprintf(stderr, "-e already used.\n");
+				exit(1);
+			}
+			subtype = optarg;
+			machine_specific_options_used = true;
+			break;
+		case 'G':
+			enable_colorized_output = true;
+			break;
+		case 'H':
+			machine_list_available_types_and_cpus();
+			exit(1);
+		case 'h':
+			usage(true);
+			exit(1);
+		case 'I':
+			m->emulated_hz = atoi(optarg);
+			machine_specific_options_used = true;
+			break;
+		case 'i':
+			m->instruction_trace = 1;
+			machine_specific_options_used = true;
+			break;
+		case 'J':
+			m->allow_instruction_combinations = 0;
+			machine_specific_options_used = true;
+			break;
+		case 'j':
+			CHECK_ALLOCATION(m->boot_kernel_filename = strdup(optarg));
+			machine_specific_options_used = true;
+			break;
+		case 'k':
+			dyntrans_cache_size = atoi(optarg) * 1048576;
+			if (dyntrans_cache_size < 1) {
+				fprintf(stderr, "The dyntrans cache size must"
+				    " be at least 1 MB.\n");
+				exit(1);
+			}
+			break;
+		case 'K':
+			debugger_enter_at_end_of_run = true;
+			break;
+		case 'L':
+			*tap_devname = strdup(optarg);
+			break;
+		case 'M':
+			m->physical_ram_in_mb = atoi(optarg);
+			machine_specific_options_used = true;
+			break;
+		case 'N':
+			m->show_nr_of_instructions = 1;
+			machine_specific_options_used = true;
+			break;
+		case 'n':
+			m->ncpus = atoi(optarg);
+			machine_specific_options_used = true;
+			break;
+		case 'O':
+			m->force_netboot = 1;
+			machine_specific_options_used = true;
+			break;
+		case 'o':
+			CHECK_ALLOCATION(m->boot_string_argument = strdup(optarg));
+			machine_specific_options_used = true;
+			break;
+		case 'p':
+			machine_add_breakpoint_string(m, optarg);
+			machine_specific_options_used = true;
+			break;
+		case 'Q':
+			m->prom_emulation = 0;
+			machine_specific_options_used = true;
+			break;
+		case 'q':
+			quiet_mode = 1;
+			break;
+		case 'R':
+			m->use_random_bootstrap_cpu = 1;
+			machine_specific_options_used = true;
+			break;
+		case 'r':
+			m->register_dump = 1;
+			machine_specific_options_used = true;
+			break;
+		case 'S':
+			m->random_mem_contents = 1;
+			machine_specific_options_used = true;
+			break;
+		case 's':
+			machine_statistics_init(m, optarg);
+			machine_specific_options_used = true;
+			break;
+		case 'T':
+			m->halt_on_nonexistant_memaccess = 1;
+			machine_specific_options_used = true;
+			break;
+		case 't':
+			m->show_trace_tree = 1;
+			machine_specific_options_used = true;
+			break;
+		case 'V':
+			single_step = true;
+			debugger_enter_at_end_of_run = true;
+			break;
+		case 'v':
+			verbose ++;
+			break;
+		case 'W':
+			internal_w(optarg);
+			exit(0);
+		case 'X':
+			m->x11_md.in_use = 1;
+			machine_specific_options_used = true;
+			/*  FALL-THROUGH  */
+		case 'x':
+			console_allow_slaves(1);
+			break;
+		case 'Y':
+			m->x11_md.scaledown = atoi(optarg);
+			if (m->x11_md.scaledown < -1) {
+				m->x11_md.scaleup = - m->x11_md.scaledown;
+				m->x11_md.scaledown = 1;
+			}
+			if (m->x11_md.scaledown < 1) {
+				fprintf(stderr, "Invalid scaledown value.\n");
+				exit(1);
+			}
+			machine_specific_options_used = true;
+			break;
+		case 'Z':
+			m->n_gfx_cards = atoi(optarg);
+			using_switch_Z = true;
+			machine_specific_options_used = true;
+			break;
+		case 'z':
+			m->x11_md.n_display_names ++;
+			CHECK_ALLOCATION(m->x11_md.display_names = (char **) realloc(
+			    m->x11_md.display_names,
+			    m->x11_md.n_display_names * sizeof(char *)));
+			CHECK_ALLOCATION(m->x11_md.display_names[
+			    m->x11_md.n_display_names-1] = strdup(optarg));
+			machine_specific_options_used = true;
+			break;
+		default:
+			fprintf(stderr, "Run  %s -h  for help on command "
+			    "line options.\n", progname);
+			exit(1);
+		}
+	}
+
+	argc -= optind;
+	argv += optind;
+
+	extra_argc = argc;
+	extra_argv = argv;
+
+	// If -V is used, -q is ignored.
+	if (single_step && quiet_mode) {
+		fprintf(stderr, "ignoring -q, because -V is used\n");
+		quiet_mode = 0;
+	}
+
+	if (type != NULL || subtype != NULL) {
+		if (type == NULL)
+			type = strdup("");
+		if (subtype == NULL)
+			subtype = strdup("");
+
+		res = machine_name_to_type(type, subtype,
+		    &m->machine_type, &m->machine_subtype);
+		if (!res)
+			exit(1);
+	}
+
+	if (m->machine_type == MACHINE_NONE && machine_specific_options_used) {
+		fprintf(stderr, "Machine specific options used directly on "
+		    "the command line, but no machine\nemulation specified?\n");
+		exit(1);
+	}
+
+
+	/*  -i and -r are pretty verbose:  */
+
+	if (m->instruction_trace && !verbose) {
+		fprintf(stderr, "Implicitly %sturning on -v, because"
+		    " of -i\n", quiet_mode? "turning off -q and " : "");
+		verbose = 1;
+		quiet_mode = 0;
+	}
+
+	if (m->register_dump && !verbose) {
+		fprintf(stderr, "Implicitly %sturning on -v, because"
+		    " of -r\n", quiet_mode? "turning off -q and " : "");
+		verbose = 1;
+		quiet_mode = 0;
+	}
+
+
+	/*
+	 *  Usually, an executable filename must be supplied.
+	 *
+	 *  However, it is possible to boot directly from a harddisk image
+	 *  file. If no kernel is supplied, but a diskimage is being used,
+	 *  then try to boot from disk.
+	 */
+	if (extra_argc == 0) {
+		if (using_switch_d) {
+			/*  Booting directly from a disk image...  */
+		} else {
+			usage(false);
+			fprintf(stderr, "\nNo filename given. Aborting.\n");
+			exit(1);
+		}
+	} else if (m->boot_kernel_filename[0] == '\0') {
+		/*
+		 *  Default boot_kernel_filename is "", which can be overriden
+		 *  by the -j command line option.  If it is still "" here,
+		 *  and we're not booting directly from a disk image, then
+		 *  try to set it to the last part of the last file name
+		 *  given on the command line. (Last part = the stuff after
+		 *  the last slash.)
+		 */
+		char *s = extra_argv[extra_argc - 1];
+		char *s2;
+
+		s2 = strrchr(s, '/');
+		if (s2 == NULL)
+			s2 = s;
+		else
+			s2 ++;
+
+		CHECK_ALLOCATION(m->boot_kernel_filename = strdup(s2));
+	}
+
+	if (m->n_gfx_cards < 0 || m->n_gfx_cards > 3) {
+		fprintf(stderr, "Bad number of gfx cards (-Z).\n");
+		exit(1);
+	}
+
+	if (!using_switch_Z && !m->x11_md.in_use)
+		m->n_gfx_cards = 0;
+
+	return 0;
+}
+
+
+/*
+ *  main():
+ *
+ *  Two kinds of emulations are started from here:
+ *
+ *	o)  Simple emulations, using command line arguments.
+ *	o)  Emulations set up by parsing special config files. (0 or more.)
+ */
+int main(int argc, char *argv[])
+{
+	/*  Setting constants:  */
+	int constant_yes = 1;
+	int constant_true = 1;
+	int constant_no = 0;
+	int constant_false = 0;
+
+	struct emul *emul;
+	bool using_config_file = false;
+	char *tap_devname = NULL;
+	char **diskimages = NULL;
+	int n_diskimages = 0;
+	int i;
+
+
+	progname = argv[0];
+
+
+	enable_colorized_output = getenv("CLICOLOR") != NULL;
+
+	debugmsg_init();
+
+
+	/*
+	 *  Create the settings object, and add global settings to it:
+	 *
+	 *  Read-only "constants":     yes, no, true, false.
+	 *  Global emulator settings:  verbose, single_step, ...
+	 */
+	global_settings = settings_new();
+
+	settings_add(global_settings, "yes", 0, SETTINGS_TYPE_INT,
+	    SETTINGS_FORMAT_YESNO, (void *)&constant_yes);
+	settings_add(global_settings, "no", 0, SETTINGS_TYPE_INT,
+	    SETTINGS_FORMAT_YESNO, (void *)&constant_no);
+	settings_add(global_settings, "true", 0, SETTINGS_TYPE_INT,
+	    SETTINGS_FORMAT_BOOL, (void *)&constant_true);
+	settings_add(global_settings, "false", 0, SETTINGS_TYPE_INT,
+	    SETTINGS_FORMAT_BOOL, (void *)&constant_false);
+
+	/*  Read/write settings:  */
+	settings_add(global_settings, "verbose", 1,
+	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO, (void *)&verbose);
+	settings_add(global_settings, "quiet_mode", 1,
+	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO, (void *)&quiet_mode);
+
+	/*  Initialize various subsystems:  */
+	console_init();
+	cpu_init();
+	device_init();
+	machine_init();
+	timer_init();
+
+	/*  Create a simple emulation setup:  */
+	emul = emul_new(NULL);
+	settings_add(global_settings, "emul", 1,
+	    SETTINGS_TYPE_SUBSETTINGS, 0, emul->settings);
+
+	get_cmd_args(argc, argv, emul, &diskimages, &n_diskimages, &tap_devname);
+
+	if (!skip_srandom_call) {
+		struct timeval tv;
+		gettimeofday(&tv, NULL);
+		srandom(tv.tv_sec ^ getpid() ^ tv.tv_usec);
+	}
+
+	// -q means that only errors should be shown.
+	if (quiet_mode)
+		debugmsg_set_verbosity_level(SUBSYS_ALL, VERBOSITY_ERROR);
+
+	for (int k = 0; k < verbose; ++k)
+		debugmsg_add_verbosity_level(SUBSYS_ALL, 1);
+
+	if (!quiet_mode)
+		print_banner();
+
+	/*  Simple initialization, from command line arguments:  */
+	if (emul->machines[0]->machine_type != MACHINE_NONE) {
+		for (i=0; i<n_diskimages; i++) {
+			if (diskimage_add(emul->machines[0], diskimages[i]) < 0) {
+				fprintf(stderr, "Aborting.\n");
+				return 1;
+			}
+		}
+
+		/*  Make sure that there are no configuration files as well:  */
+		for (i=1; i<argc; i++)
+			if (argv[i][0] == '@') {
+				fprintf(stderr, "You can either start one "
+				    "emulation with one machine directly from "
+				    "the command\nline, or start an "
+				    "emulation using a configuration file."
+				    " Not both.\n");
+				return 1;
+			}
+
+		/*  Initialize one emul:  */
+		if (!emul_simple_init(emul, tap_devname)) {
+			fprintf(stderr, "Could not initialize the emulation.\n");
+			return 1;
+		}
+	}
+
+	/*  Initialize an emulation from a config file:  */
+	for (i=1; i<argc; i++) {
+		if (argv[i][0] == '@') {
+			char *s = argv[i] + 1;
+
+			if (using_config_file) {
+				fprintf(stderr, "More than one configuration "
+				    "file cannot be used.\n");
+				return 1;
+			}
+
+			if (strlen(s) == 0 && i+1 < argc && *argv[i+1] != '@')
+				s = argv[++i];
+
+			/*  Destroy the temporary emul, since it will
+			    be overwritten:  */
+			if (emul != NULL) {
+				emul_destroy(emul);
+				emul = NULL;
+			}
+
+			emul = emul_create_from_configfile(s);
+
+			settings_add(global_settings, "emul", 1,
+			    SETTINGS_TYPE_SUBSETTINGS, 0, emul->settings);
+
+			using_config_file = true;
+		}
+	}
+
+	if (emul->n_machines == 0) {
+		printf("No machine defined. Maybe you forgot to use ");
+		color_prompt();
+		printf("-E xx");
+		color_normal();
+		printf(" and/or ");
+		color_prompt();
+		printf("-e yy");
+		color_normal();
+		printf(", to specify\nthe machine type."
+		    " For example:\n\n    ");
+		color_prompt();
+		printf("%s -e 3max -d disk.img", progname);
+		color_normal();
+		printf("\n\n"
+		    "to boot an emulated DECstation 5000/200 with a disk "
+		    "image.\n");
+		return 1;
+	}
+
+	if (emul->machines[0]->machine_type == MACHINE_NONE) {
+		printf("No machine type specified?\nRun  ");
+		color_prompt();
+		printf("gxemul -H");
+		color_normal();
+		printf("  for a list of available machine types.\n"
+		    "Then use the ");
+		color_prompt();
+		printf("-e");
+		color_normal();
+		printf(" or ");
+		color_prompt();
+		printf("-E");
+		color_normal();
+		printf(" option(s) to specify the machine type.\n");
+		return 1;
+	}
+
+	device_set_exit_on_error(0);
+	console_warn_if_slaves_are_needed(1);
+
+	// Print "INFO" during startup, but then just "WARNINGS" by default.
+	debugmsg_add_verbosity_level(SUBSYS_ALL, -1);
+
+
+	/*  Run the emulation:  */
+	emul_run(emul);
+
+
+	/*
+	 *  Deinitialize everything:
+	 */
+
+	console_deinit();
+
+	emul_destroy(emul);
+
+	settings_remove_all(global_settings);
+	settings_destroy(global_settings);
+
+	return 0;
+}
+
diff -Nru gxemul-0.6.2/src/core/Makefile.skel gxemul-0.7.0+dfsg/src/core/Makefile.skel
--- gxemul-0.6.2/src/core/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/core/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,20 @@
+#
+#  Makefile for GXemul src/core
+#
+
+CFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
+
+OBJS=debugmsg.o emul.o emul_parse.o float_emul.o interrupt.o main.o \
+	memory.o misc.o settings.o timer.o
+
+all: $(OBJS)
+
+$(OBJS): Makefile
+
+clean:
+	rm -f $(OBJS) *core
+
+clean_all: clean
+	rm -f Makefile
+
+
diff -Nru gxemul-0.6.2/src/core/memory.c gxemul-0.7.0+dfsg/src/core/memory.c
--- gxemul-0.6.2/src/core/memory.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/core/memory.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,967 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Functions for handling the memory of an emulated machine.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/mman.h>
+
+#include "cpu.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+extern int verbose;
+extern int quiet_mode;
+
+
+/*
+ *  memory_readmax64():
+ *
+ *  Read at most 64 bits of data from a buffer.  Length is given by
+ *  len, and the byte order by cpu->byte_order.
+ *
+ *  This function should not be called with cpu == NULL.
+ */
+uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
+{
+	int i, byte_order = cpu->byte_order;
+	uint64_t x = 0;
+
+	if (len & MEM_PCI_LITTLE_ENDIAN) {
+		len &= ~MEM_PCI_LITTLE_ENDIAN;
+		byte_order = EMUL_LITTLE_ENDIAN;
+	}
+
+	/*  Switch byte order for incoming data, if necessary:  */
+	if (byte_order == EMUL_BIG_ENDIAN)
+		for (i=0; i<len; i++) {
+			x <<= 8;
+			x |= buf[i];
+		}
+	else
+		for (i=len-1; i>=0; i--) {
+			x <<= 8;
+			x |= buf[i];
+		}
+
+	return x;
+}
+
+
+/*
+ *  memory_writemax64():
+ *
+ *  Write at most 64 bits of data to a buffer.  Length is given by
+ *  len, and the byte order by cpu->byte_order.
+ *
+ *  This function should not be called with cpu == NULL.
+ */
+void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len,
+	uint64_t data)
+{
+	int i, byte_order = cpu->byte_order;
+
+	if (len & MEM_PCI_LITTLE_ENDIAN) {
+		len &= ~MEM_PCI_LITTLE_ENDIAN;
+		byte_order = EMUL_LITTLE_ENDIAN;
+	}
+
+	if (byte_order == EMUL_LITTLE_ENDIAN)
+		for (i=0; i<len; i++) {
+			buf[i] = data & 255;
+			data >>= 8;
+		}
+	else
+		for (i=0; i<len; i++) {
+			buf[len - 1 - i] = data & 255;
+			data >>= 8;
+		}
+}
+
+
+/*
+ *  zeroed_alloc():
+ *
+ *  Allocates a block of memory using mmap(), and if that fails, try
+ *  malloc() + memset(). The returned memory block contains only zeroes.
+ */
+void *zeroed_alloc(size_t s)
+{
+	void *p = mmap(NULL, s, PROT_READ | PROT_WRITE,
+	    MAP_ANON | MAP_PRIVATE, -1, 0);
+
+	if (p == NULL) {
+#if 1
+		fprintf(stderr, "zeroed_alloc(): mmap() failed. This should"
+		    " not usually happen. If you can reproduce this, then"
+		    " please contact me with details about your run-time"
+		    " environment.\n");
+		exit(1);
+#else
+		CHECK_ALLOCATION(p = malloc(s));
+		memset(p, 0, s);
+#endif
+	}
+
+	return p;
+}
+
+
+/*
+ *  memory_new():
+ *
+ *  This function creates a new memory object. An emulated machine needs one
+ *  of these.
+ */
+struct memory *memory_new(uint64_t physical_max)
+{
+	struct memory *mem;
+	int bits_per_pagetable = BITS_PER_PAGETABLE;
+	int bits_per_memblock = BITS_PER_MEMBLOCK;
+	int entries_per_pagetable = 1 << BITS_PER_PAGETABLE;
+	int max_bits = MAX_BITS;
+	size_t s;
+
+	CHECK_ALLOCATION(mem = (struct memory *) malloc(sizeof(struct memory)));
+	memset(mem, 0, sizeof(struct memory));
+
+	/*  Check bits_per_pagetable and bits_per_memblock for sanity:  */
+	if (bits_per_pagetable + bits_per_memblock != max_bits) {
+		fprintf(stderr, "memory_new(): bits_per_pagetable and "
+		    "bits_per_memblock mismatch\n");
+		exit(1);
+	}
+
+	mem->physical_max = physical_max;
+	mem->dev_dyntrans_alignment = 4095;
+
+	s = entries_per_pagetable * sizeof(void *);
+
+	mem->pagetable = (unsigned char *) mmap(NULL, s,
+	    PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
+	if (mem->pagetable == NULL) {
+		CHECK_ALLOCATION(mem->pagetable = malloc(s));
+		memset(mem->pagetable, 0, s);
+	}
+
+	mem->mmap_dev_minaddr = 0xffffffffffffffffULL;
+	mem->mmap_dev_maxaddr = 0;
+
+	return mem;
+}
+
+
+/*
+ *  memory_points_to_string():
+ *
+ *  Returns 1 if there's something string-like in emulated memory at address
+ *  addr, otherwise 0.
+ */
+int memory_points_to_string(struct cpu *cpu, struct memory *mem, uint64_t addr,
+	int min_string_length)
+{
+	int cur_length = 0;
+	unsigned char c;
+
+	for (;;) {
+		c = '\0';
+		cpu->memory_rw(cpu, mem, addr+cur_length,
+		    &c, sizeof(c), MEM_READ, CACHE_NONE | NO_EXCEPTIONS);
+		if (c=='\n' || c=='\t' || c=='\r' || (c>=' ' && c<127)) {
+			cur_length ++;
+			if (cur_length >= min_string_length)
+				return 1;
+		} else {
+			if (cur_length >= min_string_length)
+				return 1;
+			else
+				return 0;
+		}
+	}
+}
+
+
+/*
+ *  memory_conv_to_string():
+ *
+ *  Convert emulated memory contents to a string, placing it in a buffer
+ *  provided by the caller.
+ */
+char *memory_conv_to_string(struct cpu *cpu, struct memory *mem, uint64_t addr,
+	char *buf, int bufsize)
+{
+	int len = 0;
+	int output_index = 0;
+	unsigned char c, p='\0';
+
+	while (output_index < bufsize-1) {
+		c = '\0';
+		cpu->memory_rw(cpu, mem, addr+len, &c, sizeof(c), MEM_READ,
+		    CACHE_NONE | NO_EXCEPTIONS);
+		buf[output_index] = c;
+		if (c>=' ' && c<127) {
+			len ++;
+			output_index ++;
+		} else if (c=='\n' || c=='\r' || c=='\t') {
+			len ++;
+			buf[output_index] = '\\';
+			output_index ++;
+			switch (c) {
+			case '\n':	p = 'n'; break;
+			case '\r':	p = 'r'; break;
+			case '\t':	p = 't'; break;
+			}
+			if (output_index < bufsize-1) {
+				buf[output_index] = p;
+				output_index ++;
+			}
+		} else {
+			buf[output_index] = '\0';
+			return buf;
+		}
+	}
+
+	buf[bufsize-1] = '\0';
+	return buf;
+}
+
+
+/*
+ *  memory_device_dyntrans_access():
+ *
+ *  Get the lowest and highest dyntrans access since last time.
+ */
+void memory_device_dyntrans_access(struct cpu *cpu, struct memory *mem,
+	void *extra, uint64_t *low, uint64_t *high)
+{
+	size_t s;
+	int i, need_inval = 0;
+
+	/*  TODO: This is O(n), so it might be good to rewrite it some day.
+	    For now, it will be enough, as long as this function is not
+	    called too often.  */
+
+	for (i=0; i<mem->n_mmapped_devices; i++) {
+		if (mem->devices[i].extra == extra &&
+		    mem->devices[i].flags & DM_DYNTRANS_WRITE_OK &&
+		    mem->devices[i].dyntrans_data != NULL) {
+			if (mem->devices[i].dyntrans_write_low != (uint64_t) -1)
+				need_inval = 1;
+			if (low != NULL)
+				*low = mem->devices[i].dyntrans_write_low;
+			mem->devices[i].dyntrans_write_low = (uint64_t) -1;
+
+			if (high != NULL)
+				*high = mem->devices[i].dyntrans_write_high;
+			mem->devices[i].dyntrans_write_high = 0;
+
+			if (!need_inval)
+				return;
+
+			/*  Invalidate any pages of this device that might
+			    be in the dyntrans load/store cache, by marking
+			    the pages read-only.  */
+			if (cpu->invalidate_translation_caches != NULL) {
+				for (s = *low; s <= *high;
+				    s += cpu->machine->arch_pagesize)
+					cpu->invalidate_translation_caches
+					    (cpu, mem->devices[i].baseaddr + s,
+					    JUST_MARK_AS_NON_WRITABLE
+					    | INVALIDATE_PADDR);
+			}
+
+			return;
+		}
+	}
+}
+
+
+/*
+ *  memory_device_update_data():
+ *
+ *  Update a device' dyntrans data pointer.
+ *
+ *  SUPER-IMPORTANT NOTE: Anyone who changes a dyntrans data pointer while
+ *  things are running also needs to invalidate all CPUs' address translation
+ *  caches!  Otherwise, these may contain old pointers to the old data.
+ */
+void memory_device_update_data(struct memory *mem, void *extra,
+	unsigned char *data)
+{
+	int i;
+
+	for (i=0; i<mem->n_mmapped_devices; i++) {
+		if (mem->devices[i].extra != extra)
+			continue;
+
+		mem->devices[i].dyntrans_data = data;
+		mem->devices[i].dyntrans_write_low = (uint64_t)-1;
+		mem->devices[i].dyntrans_write_high = 0;
+	}
+}
+
+
+/*
+ *  memory_device_register():
+ *
+ *  Register a memory mapped device.
+ */
+void memory_device_register(struct memory *mem, const char *device_name,
+	uint64_t baseaddr, uint64_t len,
+	int (*f)(struct cpu *,struct memory *,uint64_t,unsigned char *,
+		size_t,int,void *),
+	void *extra, int flags, unsigned char *dyntrans_data)
+{
+	int i, newi = 0;
+
+	/*
+	 *  Figure out at which index to insert this device, and simultaneously
+	 *  check for collisions:
+	 */
+	newi = -1;
+	for (i=0; i<mem->n_mmapped_devices; i++) {
+		if (i == 0 && baseaddr + len <= mem->devices[i].baseaddr)
+			newi = i;
+		if (i > 0 && baseaddr + len <= mem->devices[i].baseaddr &&
+		    baseaddr >= mem->devices[i-1].endaddr)
+			newi = i;
+		if (i == mem->n_mmapped_devices - 1 &&
+		    baseaddr >= mem->devices[i].endaddr)
+			newi = i + 1;
+
+		/*  If this is not colliding with device i, then continue:  */
+		if (baseaddr + len <= mem->devices[i].baseaddr)
+			continue;
+		if (baseaddr >= mem->devices[i].endaddr)
+			continue;
+
+		fatal("\nERROR! \"%s\" collides with device %i (\"%s\")!\n",
+		    device_name, i, mem->devices[i].name);
+		exit(1);
+	}
+	if (mem->n_mmapped_devices == 0)
+		newi = 0;
+	if (newi == -1) {
+		fatal("INTERNAL ERROR\n");
+		exit(1);
+	}
+
+	if (verbose >= 2) {
+		/*  (40 bits of physical address is displayed)  */
+		debug("device at 0x%010" PRIx64": %s", (uint64_t) baseaddr,
+		    device_name);
+
+		if (flags & (DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK)
+		    && (baseaddr & mem->dev_dyntrans_alignment) != 0) {
+			fatal("\nWARNING: Device dyntrans access, but unaligned"
+			    " baseaddr 0x%" PRIx64".\n", (uint64_t) baseaddr);
+		}
+
+		if (flags & (DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK)) {
+			debug(" (dyntrans %s)",
+			    (flags & DM_DYNTRANS_WRITE_OK)? "R/W" : "R");
+		}
+		debug("\n");
+	}
+
+	for (i=0; i<mem->n_mmapped_devices; i++) {
+		if (dyntrans_data == mem->devices[i].dyntrans_data &&
+		    mem->devices[i].flags&(DM_DYNTRANS_OK|DM_DYNTRANS_WRITE_OK)
+		    && flags & (DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK)) {
+			fatal("ERROR: the data pointer used for dyntrans "
+			    "accesses must only be used once!\n");
+			fatal("(%p cannot be used by '%s'; already in use by '"
+			    "%s')\n", dyntrans_data, device_name,
+			    mem->devices[i].name);
+			exit(1);
+		}
+	}
+
+	mem->n_mmapped_devices++;
+
+	CHECK_ALLOCATION(mem->devices = (struct memory_device *) realloc(mem->devices,
+	    sizeof(struct memory_device) * mem->n_mmapped_devices));
+
+	/*  Make space for the new entry:  */
+	if (newi + 1 != mem->n_mmapped_devices)
+		memmove(&mem->devices[newi+1], &mem->devices[newi],
+		    sizeof(struct memory_device)
+		    * (mem->n_mmapped_devices - newi - 1));
+
+	CHECK_ALLOCATION(mem->devices[newi].name = strdup(device_name));
+	mem->devices[newi].baseaddr = baseaddr;
+	mem->devices[newi].endaddr = baseaddr + len;
+	mem->devices[newi].length = len;
+	mem->devices[newi].flags = flags;
+	mem->devices[newi].dyntrans_data = dyntrans_data;
+
+	if (flags & (DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK)
+	    && !(flags & DM_EMULATED_RAM) && dyntrans_data == NULL) {
+		fatal("\nERROR: Device dyntrans access, but dyntrans_data"
+		    " = NULL!\n");
+		exit(1);
+	}
+
+	if ((size_t)dyntrans_data & (sizeof(void *) - 1)) {
+		fprintf(stderr, "memory_device_register():"
+		    " dyntrans_data not aligned correctly (%p)\n",
+		    dyntrans_data);
+		abort();
+	}
+
+	mem->devices[newi].dyntrans_write_low = (uint64_t)-1;
+	mem->devices[newi].dyntrans_write_high = 0;
+	mem->devices[newi].f = f;
+	mem->devices[newi].extra = extra;
+
+	if (baseaddr < mem->mmap_dev_minaddr)
+		mem->mmap_dev_minaddr = baseaddr & ~mem->dev_dyntrans_alignment;
+	if (baseaddr + len > mem->mmap_dev_maxaddr)
+		mem->mmap_dev_maxaddr = (((baseaddr + len) - 1) |
+		    mem->dev_dyntrans_alignment) + 1;
+
+	if (newi < mem->last_accessed_device)
+		mem->last_accessed_device ++;
+}
+
+
+/*
+ *  memory_device_remove():
+ *
+ *  Unregister a memory mapped device from a memory object.
+ */
+void memory_device_remove(struct memory *mem, int i)
+{
+	if (i < 0 || i >= mem->n_mmapped_devices) {
+		fatal("memory_device_remove(): invalid device number %i\n", i);
+		exit(1);
+	}
+
+	mem->n_mmapped_devices --;
+
+	if (i == mem->n_mmapped_devices)
+		return;
+
+	memmove(&mem->devices[i], &mem->devices[i+1],
+	    sizeof(struct memory_device) * (mem->n_mmapped_devices - i));
+
+	if (i <= mem->last_accessed_device)
+		mem->last_accessed_device --;
+	if (mem->last_accessed_device < 0)
+		mem->last_accessed_device = 0;
+}
+
+
+/*
+ *  memory_paddr_to_hostaddr():
+ *
+ *  Translate a physical address into a host address. The usual way to call
+ *  this function is to make sure that paddr is page aligned, which will result
+ *  in the host _page_ corresponding to that address.
+ *
+ *  Return value is a pointer to the address in the host, or NULL on failure.
+ *  On reads, a NULL return value should be interpreted as reading all zeroes.
+ */
+unsigned char *memory_paddr_to_hostaddr(struct memory *mem,
+	uint64_t paddr, int writeflag)
+{
+	void **table;
+	int entry;
+	const int mask = (1 << BITS_PER_PAGETABLE) - 1;
+	const int shrcount = MAX_BITS - BITS_PER_PAGETABLE;
+	unsigned char *hostptr;
+
+	table = (void **) mem->pagetable;
+	entry = (paddr >> shrcount) & mask;
+
+	/*  printf("memory_paddr_to_hostaddr(): p=%16" PRIx64
+	    " w=%i => entry=0x%x\n", (uint64_t) paddr, writeflag, entry);  */
+
+	if (table[entry] == NULL) {
+		size_t alloclen;
+
+		/*
+		 *  Special case:  reading from a nonexistant memblock
+		 *  returns all zeroes, and doesn't allocate anything.
+		 *  (If any intermediate pagetable is nonexistant, then
+		 *  the same thing happens):
+		 */
+		if (writeflag == MEM_READ)
+			return NULL;
+
+		/*  Allocate a memblock:  */
+		alloclen = 1 << BITS_PER_MEMBLOCK;
+
+		/*  printf("  allocating for entry %i, len=%i\n",
+		    entry, alloclen);  */
+
+		/*  Anonymous mmap() should return zero-filled memory,
+		    try malloc + memset if mmap failed.  */
+		table[entry] = (void *) mmap(NULL, alloclen,
+		    PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
+		if (table[entry] == NULL) {
+			CHECK_ALLOCATION(table[entry] = malloc(alloclen));
+			memset(table[entry], 0, alloclen);
+		}
+	}
+
+	hostptr = (unsigned char *) table[entry];
+
+	if (hostptr != NULL)
+		hostptr += (paddr & ((1 << BITS_PER_MEMBLOCK) - 1));
+
+	return hostptr;
+}
+
+
+/*
+ *  memory_warn_about_unimplemented_addr():
+ *
+ *  Called from memory_rw whenever memory outside of the physical address space
+ *  is accessed.
+ */
+bool memory_warn_about_unimplemented_addr(struct cpu *cpu, struct memory *mem,
+	int writeflag, uint64_t paddr, size_t len)
+{
+	/*
+	 *  HACK: This allows guest OS kernels to probe memory a few KBs past
+	 *  the end of memory, without giving too many warnings.
+	 */
+	if (paddr < mem->physical_max + 0x40000)
+		return false;
+
+	int verbosity = VERBOSITY_WARNING;
+	if (cpu->machine->halt_on_nonexistant_memaccess)
+		verbosity = VERBOSITY_ERROR;
+
+	// ERROR is always "enough", so we will print in that case.
+	if (!ENOUGH_VERBOSITY(SUBSYS_MEMORY, verbosity))
+		return false;
+
+	uint64_t offset;
+	char* symbol = get_symbol_name(&cpu->machine->symbol_context, cpu->pc, &offset);
+
+	// Not the prettiest, but should work fine.
+	if (cpu->is_32bit)
+		debugmsg_cpu(cpu, SUBSYS_MEMORY,
+		    writeflag ? "WRITE" : "READ",
+		    verbosity, "%s non-existant "
+			"paddr=0x%08" PRIx32 " len=%i pc=0x%08" PRIx32 "%s%s%s",
+		    writeflag ? "to" : "from",
+		    (uint32_t) paddr,
+		    len,
+		    (uint32_t) cpu->pc,
+		    symbol ? " <" : "",
+		    symbol ? symbol : "",
+		    symbol ? ">" : "");
+	else
+		debugmsg_cpu(cpu, SUBSYS_MEMORY,
+		    writeflag ? "WRITE" : "READ",
+		    verbosity, "%s non-existant "
+			"paddr=0x%016" PRIx64 " len=%i pc=0x%016" PRIx64 "%s%s%s",
+		    writeflag ? "to" : "from",
+		    (uint64_t) paddr,
+		    len,
+		    (uint64_t) cpu->pc,
+		    symbol ? " <" : "",
+		    symbol ? symbol : "",
+		    symbol ? ">" : "");
+
+	if (cpu->machine->halt_on_nonexistant_memaccess) {
+		// Halt all CPUs, even though the bad memory access was on
+		// just one of them.
+		for (int i = 0; i < cpu->machine->ncpus; ++i)
+			cpu->machine->cpus[i]->running = 0;
+
+		return true;
+	}
+
+	return false;
+}
+
+
+/*
+ *  dump_mem_string():
+ *
+ *  Dump the contents of emulated RAM as readable text.  Bytes that aren't
+ *  readable are dumped in [xx] notation, where xx is in hexadecimal.
+ *  Dumping ends after DUMP_MEM_STRING_MAX bytes, or when a terminating
+ *  zero byte is found.
+ */
+#define DUMP_MEM_STRING_MAX	45
+void dump_mem_string(struct cpu *cpu, uint64_t addr)
+{
+	int i;
+	for (i=0; i<DUMP_MEM_STRING_MAX; i++) {
+		unsigned char ch = '\0';
+
+		cpu->memory_rw(cpu, cpu->mem, addr + i, &ch, sizeof(ch),
+		    MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
+		if (ch == '\0')
+			return;
+		if (ch >= ' ' && ch < 126)
+			debug("%c", ch);  
+		else
+			debug("[%02x]", ch);
+	}
+}
+
+
+/*
+ *  store_byte():
+ *
+ *  Stores a byte in emulated ram. (Helper function.)
+ */
+void store_byte(struct cpu *cpu, uint64_t addr, uint8_t data)
+{
+	if ((addr >> 32) == 0)
+		addr = (int64_t)(int32_t)addr;
+	cpu->memory_rw(cpu, cpu->mem,
+	    addr, &data, sizeof(data), MEM_WRITE, CACHE_DATA);
+}
+
+
+/*
+ *  store_string():
+ *
+ *  Stores chars into emulated RAM until a zero byte (string terminating
+ *  character) is found. The zero byte is also copied.
+ *  (strcpy()-like helper function, host-RAM-to-emulated-RAM.)
+ */
+void store_string(struct cpu *cpu, uint64_t addr, const char *s)
+{
+	do {
+		store_byte(cpu, addr++, *s);
+	} while (*s++);
+}
+
+
+/*
+ *  add_environment_string():
+ *
+ *  Like store_string(), but advances the pointer afterwards. The most
+ *  obvious use is to place a number of strings (such as environment variable
+ *  strings) after one-another in emulated memory.
+ */
+void add_environment_string(struct cpu *cpu, const char *s, uint64_t *addr)
+{
+	store_string(cpu, *addr, s);
+	(*addr) += strlen(s) + 1;
+}
+
+
+/*
+ *  add_environment_string_dual():
+ *
+ *  Add "dual" environment strings, one for the variable name and one for the
+ *  value, and update pointers afterwards.
+ */
+void add_environment_string_dual(struct cpu *cpu,
+	uint64_t *ptrp, uint64_t *addrp, const char *s1, const char *s2)
+{
+	uint64_t ptr = *ptrp, addr = *addrp;
+
+	store_32bit_word(cpu, ptr, addr);
+	ptr += sizeof(uint32_t);
+	if (addr != 0) {
+		store_string(cpu, addr, s1);
+		addr += strlen(s1) + 1;
+	}
+	store_32bit_word(cpu, ptr, addr);
+	ptr += sizeof(uint32_t);
+	if (addr != 0) {
+		store_string(cpu, addr, s2);
+		addr += strlen(s2) + 1;
+	}
+
+	*ptrp = ptr;
+	*addrp = addr;
+}
+
+
+/*
+ *  store_64bit_word():
+ *
+ *  Stores a 64-bit word in emulated RAM.  Byte order is taken into account.
+ *  Helper function.
+ */
+int store_64bit_word(struct cpu *cpu, uint64_t addr, uint64_t data64)
+{
+	unsigned char data[8];
+	if ((addr >> 32) == 0)
+		addr = (int64_t)(int32_t)addr;
+	data[0] = (data64 >> 56) & 255;
+	data[1] = (data64 >> 48) & 255;
+	data[2] = (data64 >> 40) & 255;
+	data[3] = (data64 >> 32) & 255;
+	data[4] = (data64 >> 24) & 255;
+	data[5] = (data64 >> 16) & 255;
+	data[6] = (data64 >> 8) & 255;
+	data[7] = (data64) & 255;
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		int tmp = data[0]; data[0] = data[7]; data[7] = tmp;
+		tmp = data[1]; data[1] = data[6]; data[6] = tmp;
+		tmp = data[2]; data[2] = data[5]; data[5] = tmp;
+		tmp = data[3]; data[3] = data[4]; data[4] = tmp;
+	}
+	return cpu->memory_rw(cpu, cpu->mem,
+	    addr, data, sizeof(data), MEM_WRITE, CACHE_DATA);
+}
+
+
+/*
+ *  store_32bit_word():
+ *
+ *  Stores a 32-bit word in emulated RAM.  Byte order is taken into account.
+ *  (This function takes a 64-bit word as argument, to suppress some
+ *  warnings, but only the lowest 32 bits are used.)
+ */
+int store_32bit_word(struct cpu *cpu, uint64_t addr, uint64_t data32)
+{
+	unsigned char data[4];
+
+	data[0] = (data32 >> 24) & 255;
+	data[1] = (data32 >> 16) & 255;
+	data[2] = (data32 >> 8) & 255;
+	data[3] = (data32) & 255;
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		int tmp = data[0]; data[0] = data[3]; data[3] = tmp;
+		tmp = data[1]; data[1] = data[2]; data[2] = tmp;
+	}
+	return cpu->memory_rw(cpu, cpu->mem,
+	    addr, data, sizeof(data), MEM_WRITE, CACHE_DATA);
+}
+
+
+/*
+ *  store_16bit_word():
+ *
+ *  Stores a 16-bit word in emulated RAM.  Byte order is taken into account.
+ *  (This function takes a 64-bit word as argument, to suppress some
+ *  warnings, but only the lowest 16 bits are used.)
+ */
+int store_16bit_word(struct cpu *cpu, uint64_t addr, uint64_t data16)
+{
+	unsigned char data[2];
+
+	data[0] = (data16 >> 8) & 255;
+	data[1] = (data16) & 255;
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		int tmp = data[0]; data[0] = data[1]; data[1] = tmp;
+	}
+	return cpu->memory_rw(cpu, cpu->mem,
+	    addr, data, sizeof(data), MEM_WRITE, CACHE_DATA);
+}
+
+
+/*
+ *  store_buf():
+ *
+ *  memcpy()-like helper function, from host RAM to emulated RAM.
+ */
+void store_buf(struct cpu *cpu, uint64_t addr, const char *s, size_t len)
+{
+	size_t psize = 1024;	/*  1024 256 64 16 4 1  */
+
+	while (len != 0) {
+		if ((addr & (psize-1)) == 0) {
+			while (len >= psize) {
+				cpu->memory_rw(cpu, cpu->mem, addr,
+				    (unsigned char *)s, psize, MEM_WRITE,
+				    CACHE_DATA);
+				addr += psize;
+				s += psize;
+				len -= psize;
+			}
+		}
+		psize >>= 2;
+	}
+
+	while (len-- != 0)
+		store_byte(cpu, addr++, *s++);
+}
+
+
+/*
+ *  store_pointer_and_advance():
+ *
+ *  Stores a 32-bit or 64-bit pointer in emulated RAM, and advances the
+ *  target address. (Useful for e.g. ARCBIOS environment initialization.)
+ */
+void store_pointer_and_advance(struct cpu *cpu, uint64_t *addrp,
+	uint64_t data, int flag64)
+{
+	uint64_t addr = *addrp;
+	if (flag64) {
+		store_64bit_word(cpu, addr, data);
+		addr += 8;
+	} else {
+		store_32bit_word(cpu, addr, data);
+		addr += 4;
+	}
+	*addrp = addr;
+}
+
+
+/*
+ *  load_64bit_word():
+ *
+ *  Helper function. Emulated byte order is taken into account.
+ */
+uint64_t load_64bit_word(struct cpu *cpu, uint64_t addr)
+{
+	unsigned char data[8];
+
+	cpu->memory_rw(cpu, cpu->mem,
+	    addr, data, sizeof(data), MEM_READ, CACHE_DATA);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		int tmp = data[0]; data[0] = data[7]; data[7] = tmp;
+		tmp = data[1]; data[1] = data[6]; data[6] = tmp;
+		tmp = data[2]; data[2] = data[5]; data[5] = tmp;
+		tmp = data[3]; data[3] = data[4]; data[4] = tmp;
+	}
+
+	return
+	    ((uint64_t)data[0] << 56) + ((uint64_t)data[1] << 48) +
+	    ((uint64_t)data[2] << 40) + ((uint64_t)data[3] << 32) +
+	    ((uint64_t)data[4] << 24) + ((uint64_t)data[5] << 16) +
+	    ((uint64_t)data[6] << 8) + (uint64_t)data[7];
+}
+
+
+/*
+ *  load_32bit_word():
+ *
+ *  Helper function. Emulated byte order is taken into account.
+ */
+uint32_t load_32bit_word(struct cpu *cpu, uint64_t addr)
+{
+	unsigned char data[4];
+
+	cpu->memory_rw(cpu, cpu->mem,
+	    addr, data, sizeof(data), MEM_READ, CACHE_DATA);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		int tmp = data[0]; data[0] = data[3]; data[3] = tmp;
+		tmp = data[1]; data[1] = data[2]; data[2] = tmp;
+	}
+
+	return (data[0] << 24) + (data[1] << 16) + (data[2] << 8) + data[3];
+}
+
+
+/*
+ *  load_16bit_word():
+ *
+ *  Helper function. Emulated byte order is taken into account.
+ */
+uint16_t load_16bit_word(struct cpu *cpu, uint64_t addr)
+{
+	unsigned char data[2];
+
+	cpu->memory_rw(cpu, cpu->mem,
+	    addr, data, sizeof(data), MEM_READ, CACHE_DATA);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		int tmp = data[0]; data[0] = data[1]; data[1] = tmp;
+	}
+
+	return (data[0] << 8) + data[1];
+}
+
+
+/*
+ *  store_64bit_word_in_host():
+ *
+ *  Stores a 64-bit word in the _host's_ RAM.  Emulated byte order is taken
+ *  into account.  This is useful when building structs in the host's RAM
+ *  which will later be copied into emulated RAM.
+ */
+void store_64bit_word_in_host(struct cpu *cpu,
+	unsigned char *data, uint64_t data64)
+{
+	data[0] = (data64 >> 56) & 255;
+	data[1] = (data64 >> 48) & 255;
+	data[2] = (data64 >> 40) & 255;
+	data[3] = (data64 >> 32) & 255;
+	data[4] = (data64 >> 24) & 255;
+	data[5] = (data64 >> 16) & 255;
+	data[6] = (data64 >> 8) & 255;
+	data[7] = (data64) & 255;
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		int tmp = data[0]; data[0] = data[7]; data[7] = tmp;
+		tmp = data[1]; data[1] = data[6]; data[6] = tmp;
+		tmp = data[2]; data[2] = data[5]; data[5] = tmp;
+		tmp = data[3]; data[3] = data[4]; data[4] = tmp;
+	}
+}
+
+
+/*
+ *  store_32bit_word_in_host():
+ *
+ *  See comment for store_64bit_word_in_host().
+ *
+ *  (Note:  The data32 parameter is a uint64_t. This is done to suppress
+ *  some warnings.)
+ */
+void store_32bit_word_in_host(struct cpu *cpu,
+	unsigned char *data, uint64_t data32)
+{
+	data[0] = (data32 >> 24) & 255;
+	data[1] = (data32 >> 16) & 255;
+	data[2] = (data32 >> 8) & 255;
+	data[3] = (data32) & 255;
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		int tmp = data[0]; data[0] = data[3]; data[3] = tmp;
+		tmp = data[1]; data[1] = data[2]; data[2] = tmp;
+	}
+}
+
+
+/*
+ *  store_16bit_word_in_host():
+ *
+ *  See comment for store_64bit_word_in_host().
+ */
+void store_16bit_word_in_host(struct cpu *cpu,
+	unsigned char *data, uint16_t data16)
+{
+	data[0] = (data16 >> 8) & 255;
+	data[1] = (data16) & 255;
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		int tmp = data[0]; data[0] = data[1]; data[1] = tmp;
+	}
+}
+
diff -Nru gxemul-0.6.2/src/core/misc.c gxemul-0.7.0+dfsg/src/core/misc.c
--- gxemul-0.6.2/src/core/misc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/core/misc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,292 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  This file contains things that don't fit anywhere else, and fake/dummy
+ *  implementations of libc functions that are missing on some systems.
+ */
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <fcntl.h>
+#include <unistd.h>
+
+#include "cpu.h"
+#include "misc.h"
+
+
+bool enable_colorized_output = true;
+
+
+static bool use_colorized_output()
+{
+	static bool isatty_initialized = false;
+	static bool r = false;
+
+	if (!isatty_initialized) {
+		r = isatty(STDIN_FILENO) && isatty(STDOUT_FILENO);
+		isatty_initialized = true;
+	}
+
+	return r && enable_colorized_output;
+}
+
+
+void color_prompt()
+{
+	if (use_colorized_output())
+		printf("\e[34;1m");
+}
+
+
+void color_normal()
+{
+	if (use_colorized_output())
+		printf("%s", color_normal_ptr());
+}
+
+void color_error(bool bold)
+{
+	if (!use_colorized_output())
+		return;
+
+	if (bold)
+		printf("\e[31;1m");
+	else
+		printf("\e[31m");
+}
+
+
+void color_debugmsg_subsystem()
+{
+	if (use_colorized_output())
+		printf("\e[33m");
+}
+
+
+void color_debugmsg_name()
+{
+	if (use_colorized_output())
+		printf("\e[34;1m");
+}
+
+
+void color_banner()
+{
+	if (use_colorized_output())
+		printf("\e[1m");
+}
+
+
+void color_pc_indicator()
+{
+	if (!use_colorized_output())
+		return;
+
+	printf("\e[31m");
+}
+
+
+const char* color_symbol_ptr()
+{
+	if (use_colorized_output())
+		return "\e[35m";
+	else
+		return "";
+}
+
+
+const char* color_normal_ptr()
+{
+	if (use_colorized_output())
+		return "\e[0m";
+	else
+		return "";
+}
+
+
+/*
+ *  mystrtoull():
+ *
+ *  This function is used on OSes that don't have strtoull() in libc.
+ */
+unsigned long long mystrtoull(const char *s, char **endp, int base)
+{
+	unsigned long long res = 0;
+	int minus_sign = 0;
+
+	if (s == NULL)
+		return 0;
+
+	/*  TODO: Implement endp?  */
+	if (endp != NULL) {
+		fprintf(stderr, "mystrtoull(): endp isn't implemented\n");
+		exit(1);
+	}
+
+	if (s[0] == '-') {
+		minus_sign = 1;
+		s++;
+	}
+
+	/*  Guess base:  */
+	if (base == 0) {
+		if (s[0] == '0') {
+			/*  Just "0"? :-)  */
+			if (!s[1])
+				return 0;
+			if (s[1] == 'x' || s[1] == 'X') {
+				base = 16;
+				s += 2;
+			} else {
+				base = 8;
+				s ++;
+			}
+		} else if (s[0] >= '1' && s[0] <= '9')
+			base = 10;
+	}
+
+	while (s[0]) {
+		int c = s[0];
+		if (c >= '0' && c <= '9')
+			c -= '0';
+		else if (c >= 'a' && c <= 'f')
+			c = c - 'a' + 10;
+		else if (c >= 'A' && c <= 'F')
+			c = c - 'A' + 10;
+		else
+			break;
+		switch (base) {
+		case 8:	res = (res << 3) | c;
+			break;
+		case 16:res = (res << 4) | c;
+			break;
+		default:res = (res * base) + c;
+		}
+		s++;
+	}
+
+	if (minus_sign)
+		res = (uint64_t) -(int64_t)res;
+	return res;
+}
+
+
+/*
+ *  mymkstemp():
+ *
+ *  mkstemp() replacement for systems that lack that function. This is NOT
+ *  really safe, but should at least allow the emulator to build and run.
+ */
+int mymkstemp(char *templ)
+{
+	int h = 0;
+	char *p = templ;
+
+	while (*p) {
+		if (*p == 'X')
+			*p = 48 + random() % 10;
+		p++;
+	}
+
+	h = open(templ, O_RDWR | O_CREAT | O_EXCL, 0600);
+	return h;
+}
+
+
+#ifdef USE_STRLCPY_REPLACEMENTS
+/*
+ *  mystrlcpy():
+ *
+ *  Quick hack strlcpy() replacement for systems that lack that function.
+ *  NOTE: No length checking is done.
+ */
+size_t mystrlcpy(char *dst, const char *src, size_t size)
+{
+	strcpy(dst, src);
+	return strlen(src);
+}
+
+
+/*
+ *  mystrlcat():
+ *
+ *  Quick hack strlcat() replacement for systems that lack that function.
+ *  NOTE: No length checking is done.
+ */
+size_t mystrlcat(char *dst, const char *src, size_t size)
+{
+	size_t orig_dst_len = strlen(dst);
+	strcat(dst, src);
+	return strlen(src) + orig_dst_len;
+}
+#endif
+
+
+/*
+ *  print_separator_line():
+ *
+ *  Prints a line of "----------".
+ */
+void print_separator_line(void)
+{
+        int i = 79; 
+        while (i-- > 0)
+                debug("-");
+        debug("\n");
+}
+
+
+/*
+ *  size_to_mask():
+ *
+ *  For e.g. 0x1000, the mask returned is 0xfff.
+ *  For e.g. 0x1400, the mask returned is 0x1fff.
+ *
+ *  In other words, the returned value is the smallest mask that can be applied
+ *  which preserves any address within the range 0..(size-1).
+ */
+uint64_t size_to_mask(uint64_t size)
+{
+	if (size == 0)
+		return 0;
+
+	size --;
+
+	uint64_t mask = 1;
+
+	while (size > 0)
+	{
+		size >>= 1;
+		mask = (mask << 1) | 1;
+	}
+
+	return mask;
+}
+
+
diff -Nru gxemul-0.6.2/src/core/settings.c gxemul-0.7.0+dfsg/src/core/settings.c
--- gxemul-0.6.2/src/core/settings.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/core/settings.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,499 @@
+/*
+ *  Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  A generic settings object. (This module should be 100% indepedent of GXemul
+ *  and hence easily reusable.)  It is basically a tree structure of nodes,
+ *  where each node has a name and a few properties. The main property is
+ *  a pointer, which can either point to other settings ("sub-settings"),
+ *  or to a variable in memory.
+ *
+ *  Appart from the pointer, the other properties are a definition of the
+ *  type being pointed to (int, int32_t, int64_t, char*, etc), how it should be
+ *  presented (e.g. it may be an int value in memory, but it should be
+ *  presented as a boolean "true/false" value), and a flag which tells us
+ *  whether the setting is directly writable or not.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+/*  Including misc.h should ONLY be necessary to work around the fact that
+    many systems don't have PRIx64 etc defined.  */
+#include "misc.h"
+
+#include "settings.h"
+
+
+struct settings {
+	struct settings		*parent;
+	char			*name_in_parent;
+
+	int			n_settings;
+
+	/*
+	 *  Each setting has a name, a writable flag, a storage type, a
+	 *  presentation format, and a pointer.
+	 *
+	 *  For subsettings, the pointer points to the subsettings object;
+	 *  for other settings, the pointer points to a variable.
+	 *
+	 *  These pointers point to simple linear arrays, containing n_settings
+	 *  entries each.
+	 */
+
+	char			**name;
+	int			*writable;
+	int			*storage_type;
+	int			*presentation_format;
+	void			**ptr;
+};
+
+
+/*
+ *  settings_new():
+ *
+ *  Create a new settings object. Return value is a pointer to the newly
+ *  created object. The function does not return on failure.
+ */
+struct settings *settings_new(void)
+{
+	struct settings *settings;
+
+	CHECK_ALLOCATION(settings = (struct settings *) malloc(sizeof(struct settings)));
+	memset(settings, 0, sizeof(struct settings));
+
+	return settings;
+}
+
+
+/*
+ *  settings_destroy():
+ *
+ *  Frees all resources occupied by a settings object. Also, if this settings
+ *  object has a parent, then remove it from the parent.
+ */
+void settings_destroy(struct settings *settings)
+{
+	int i;
+
+	if (settings == NULL) {
+		fprintf(stderr, "settings_destroy(): internal error, "
+		    "settings = NULL!\n");
+		exit(1);
+	}
+
+	if (settings->n_settings > 0)
+		debugmsg(SUBSYS_STARTUP, "settings", VERBOSITY_DEBUG,
+		    "settings_destroy(): there are remaining settings!");
+
+	if (settings->name != NULL) {
+		for (i=0; i<settings->n_settings; i++) {
+			if (settings->name[i] != NULL) {
+				debugmsg(SUBSYS_STARTUP, "settings", VERBOSITY_DEBUG,
+				    "settings_destroy(): setting '%s'"
+				    " was not properly deleted before "
+				    "exiting!", settings->name[i]);
+
+				free(settings->name[i]);
+			}
+		}
+
+		free(settings->name);
+	} else if (settings->n_settings != 0) {
+		fprintf(stderr, "settings_destroy(): internal error, "
+		    "settings->name = NULL, but there were settings?"
+		    " (n_settings = %i)\n", settings->n_settings);
+		exit(1);
+	}
+
+	if (settings->writable != NULL)
+		free(settings->writable);
+
+	if (settings->storage_type != NULL)
+		free(settings->storage_type);
+
+	if (settings->presentation_format != NULL)
+		free(settings->presentation_format);
+
+	if (settings->ptr != NULL)
+		free(settings->ptr);
+
+	if (settings->parent != NULL) {
+		settings_remove(settings->parent, settings->name_in_parent);
+		free(settings->name_in_parent);
+	}
+
+	free(settings);
+}
+
+
+/*
+ *  settings_read():
+ *
+ *  Used internally by settings_access() and settings_debugdump().
+ */
+static int settings_read(struct settings *settings, int i, uint64_t *valuep)
+{
+	*valuep = 0;
+
+	switch (settings->storage_type[i]) {
+	case SETTINGS_TYPE_INT:
+		*valuep = *((int *) settings->ptr[i]);
+		break;
+	case SETTINGS_TYPE_INT8:
+		*valuep = *((int8_t *) settings->ptr[i]);
+		break;
+	case SETTINGS_TYPE_INT16:
+		*valuep = *((int16_t *) settings->ptr[i]);
+		break;
+	case SETTINGS_TYPE_INT32:
+		*valuep = *((int32_t *) settings->ptr[i]);
+		break;
+	case SETTINGS_TYPE_INT64:
+		*valuep = *((int64_t *) settings->ptr[i]);
+		break;
+	case SETTINGS_TYPE_UINT:
+		*valuep = *((uint *) settings->ptr[i]);
+		break;
+	case SETTINGS_TYPE_UINT8:
+		*valuep = *((uint8_t *) settings->ptr[i]);
+		break;
+	case SETTINGS_TYPE_UINT16:
+		*valuep = *((uint16_t *) settings->ptr[i]);
+		break;
+	case SETTINGS_TYPE_UINT32:
+		*valuep = *((uint32_t *) settings->ptr[i]);
+		break;
+	case SETTINGS_TYPE_UINT64:
+		*valuep = *((uint64_t *) settings->ptr[i]);
+		break;
+	case SETTINGS_TYPE_STRING:
+		/*  Note: Strings cannot be read like this.  */
+		break;
+	default:printf("settings_read(): FATAL ERROR! Unknown storage type"
+		    ": %i\n", settings->storage_type[i]);
+		exit(1);
+	}
+
+	return SETTINGS_OK;
+}
+
+
+/*
+ *  settings_write():
+ *
+ *  Used internally by settings_access().
+ */
+static int settings_write(struct settings *settings, int i, uint64_t *valuep)
+{
+	if (!settings->writable[i])
+		return SETTINGS_READONLY;
+
+	switch (settings->storage_type[i]) {
+	case SETTINGS_TYPE_INT:
+	case SETTINGS_TYPE_UINT:
+		*((int *) settings->ptr[i]) = *valuep;
+		break;
+	case SETTINGS_TYPE_INT8:
+	case SETTINGS_TYPE_UINT8:
+		*((int8_t *) settings->ptr[i]) = *valuep;
+		break;
+	case SETTINGS_TYPE_INT16:
+	case SETTINGS_TYPE_UINT16:
+		*((int16_t *) settings->ptr[i]) = *valuep;
+		break;
+	case SETTINGS_TYPE_INT32:
+	case SETTINGS_TYPE_UINT32:
+		*((int32_t *) settings->ptr[i]) = *valuep;
+		break;
+	case SETTINGS_TYPE_INT64:
+	case SETTINGS_TYPE_UINT64:
+		*((int64_t *) settings->ptr[i]) = *valuep;
+		break;
+	case SETTINGS_TYPE_STRING:
+		/*  Note: Strings cannot be read like this.  */
+		printf("settings_write(): ERROR! Strings cannot be "
+		    "written like this.\n");
+		break;
+	default:printf("settings_read(): FATAL ERROR! Unknown storage type"
+		    ": %i\n", settings->storage_type[i]);
+		exit(1);
+	}
+
+	return SETTINGS_OK;
+}
+
+
+/*
+ *  settings_debugdump():
+ *
+ *  Dump settings in a settings object to stdout.
+ *  If recurse is non-zero, all subsetting objects are also dumped.
+ */
+void settings_debugdump(struct settings *settings, const char *prefix,
+	int recurse)
+{
+	size_t name_buflen = strlen(prefix) + 100;
+	char *name;
+	int i;
+	uint64_t value = 0;
+
+	CHECK_ALLOCATION(name = (char *) malloc(name_buflen));
+
+	for (i=0; i<settings->n_settings; i++) {
+		snprintf(name, name_buflen, "%s.%s", prefix, settings->name[i]);
+
+		if (settings->storage_type[i] == SETTINGS_TYPE_SUBSETTINGS) {
+			/*  Subsettings:  */
+			if (recurse)
+				settings_debugdump((struct settings *)settings->ptr[i], name, 1);
+		} else {
+			/*  Normal value:  */
+			printf("%s = ", name);
+
+			settings_read(settings, i, &value);
+
+			switch (settings->presentation_format[i]) {
+			case SETTINGS_FORMAT_DECIMAL:
+				printf("%" PRIi64, value);
+				break;
+			case SETTINGS_FORMAT_HEX8:
+				printf("0x%02" PRIx8, (int8_t) value);
+				break;
+			case SETTINGS_FORMAT_HEX16:
+				printf("0x%04" PRIx16, (int16_t) value);
+				break;
+			case SETTINGS_FORMAT_HEX32:
+				printf("0x%08" PRIx32, (int32_t) value);
+				break;
+			case SETTINGS_FORMAT_HEX64:
+				printf("0x%016" PRIx64, (int64_t) value);
+				break;
+			case SETTINGS_FORMAT_BOOL:
+				printf(value? "true" : "false");
+				break;
+			case SETTINGS_FORMAT_YESNO:
+				printf(value? "yes" : "no");
+				break;
+			case SETTINGS_FORMAT_STRING:
+				printf("\"%s\"", *((char **)settings->ptr[i]));
+				break;
+			default:printf("FATAL ERROR! Unknown presentation "
+				    "format: %i\n",
+				    settings->presentation_format[i]);
+				exit(1);
+			}
+
+			if (!settings->writable[i])
+				printf("  (R/O)");
+
+			printf("\n");
+		}
+	}
+
+	free(name);
+}
+
+
+/*
+ *  settings_add():
+ *
+ *  Add a setting to a settings object.
+ */
+void settings_add(struct settings *settings, const char *name, int writable,
+	int type, int format, void *ptr)
+{
+	int i;
+
+	for (i=0; i<settings->n_settings; i++) {
+		if (strcmp(settings->name[i], name) == 0)
+			break;
+	}
+
+	if (i < settings->n_settings) {
+		fprintf(stderr, "settings_add(): name '%s' is already"
+		    " in use\n", name);
+		exit(1);
+	}
+
+	settings->n_settings ++;
+
+	CHECK_ALLOCATION(settings->name = (char **) realloc(settings->name, 
+	    settings->n_settings * sizeof(char *)));
+	CHECK_ALLOCATION(settings->writable = (int *) realloc(settings->writable,
+	    settings->n_settings * sizeof(int)));
+	CHECK_ALLOCATION(settings->storage_type = (int *) realloc(
+	    settings->storage_type, settings->n_settings * sizeof(int)));
+	CHECK_ALLOCATION(settings->presentation_format = (int *) realloc(settings->
+	    presentation_format, settings->n_settings * sizeof(int)));
+	CHECK_ALLOCATION(settings->ptr = (void **) realloc(settings->ptr,
+	    settings->n_settings * sizeof(void *)));
+
+	CHECK_ALLOCATION(settings->name[settings->n_settings - 1] =
+	    strdup(name));
+	settings->writable[settings->n_settings - 1] = writable;
+	settings->storage_type[settings->n_settings - 1] = type;
+	settings->presentation_format[settings->n_settings - 1] = format;
+	settings->ptr[settings->n_settings - 1] = ptr;
+
+	if (type == SETTINGS_TYPE_SUBSETTINGS) {
+		((struct settings *)ptr)->parent = settings;
+		CHECK_ALLOCATION( ((struct settings *)ptr)->name_in_parent =
+		    strdup(name) );
+	}
+}
+
+
+/*
+ *  settings_remove():
+ *
+ *  Remove a setting from a settings object.
+ */
+void settings_remove(struct settings *settings, const char *name)
+{
+	int i, m;
+
+	for (i=0; i<settings->n_settings; i++) {
+		if (strcmp(settings->name[i], name) == 0)
+			break;
+	}
+
+	if (i >= settings->n_settings) {
+		debugmsg(SUBSYS_STARTUP, "settings", VERBOSITY_WARNING,
+		    "settings_remove(): attempting to remove"
+		    " non-existant setting '%s'", name);
+		return;
+	}
+
+	/*  Check subsettings specifically:  */
+	if (settings->storage_type[i] == SETTINGS_TYPE_SUBSETTINGS &&
+	    settings->ptr[i] != NULL) {
+		struct settings *subsettings = (struct settings *) settings->ptr[i];
+		if (subsettings->n_settings != 0) {
+			fprintf(stderr, "settings_remove(): attempting to "
+			    "remove non-emtpy setting '%s'\n", name);
+			fprintf(stderr, "Remaining settings are:\n");
+			for (i=0; i<subsettings->n_settings; i++)
+				fprintf(stderr, "\t%s\n", subsettings->name[i]);
+			exit(1);
+		}
+	}
+
+	settings->n_settings --;
+	free(settings->name[i]);
+
+	m = settings->n_settings - i;
+	if (m == 0)
+		return;
+
+	memmove(&settings->name[i], &settings->name[i+1],
+	    m * sizeof(settings->name[0]));
+	memmove(&settings->writable[i], &settings->writable[i+1],
+	    m * sizeof(settings->writable[0]));
+	memmove(&settings->storage_type[i], &settings->storage_type[i+1],
+	    m * sizeof(settings->storage_type[0]));
+	memmove(&settings->presentation_format[i],
+	    &settings->presentation_format[i+1],
+	    m * sizeof(settings->presentation_format[0]));
+	memmove(&settings->ptr[i], &settings->ptr[i+1],
+	    m * sizeof(settings->ptr[0]));
+}
+
+
+/*
+ *  settings_remove_all():
+ *
+ *  Remove all (level-1) settings from a settings object. By level-1, I mean
+ *  all settings that do not contain subsettings.
+ */
+void settings_remove_all(struct settings *settings)
+{
+	while (settings->n_settings > 0)
+		settings_remove(settings, settings->name[0]);
+}
+
+
+/*
+ *  settings_access():
+ *
+ *  Read or write a setting. fullname may be something like "settings.x.y".
+ *  When writing a value, valuebuf should point to a uint64_t containing the
+ *  new value (note: always a uint64_t). When reading a value, valuebuf should
+ *  point to a uint64_t where the value will be stored.
+ *
+ *  The return value is one of the following:
+ *
+ *	SETTINGS_OK
+ *		The value was read or written.
+ *
+ *	SETTINGS_NAME_NOT_FOUND
+ *		The name was not found in the settings object.
+ *
+ *	SETTINGS_READONLY
+ *		The name was found, but it was marked as read-only, and
+ *		an attempt was made to write to it.
+ */
+int settings_access(struct settings *settings, const char *fullname,
+        int writeflag, uint64_t *valuep)
+{
+	int i;
+
+	/*  printf("settings_access(fullname='%s')\n", fullname);  */
+
+	if (strncmp(fullname, GLOBAL_SETTINGS_NAME".",
+	    strlen(GLOBAL_SETTINGS_NAME) + 1) == 0)
+		fullname += strlen(GLOBAL_SETTINGS_NAME) + 1;
+
+	for (i=0; i<settings->n_settings; i++) {
+		size_t settings_name_len = strlen(settings->name[i]);
+
+		if (strncmp(fullname, settings->name[i],
+		    settings_name_len) != 0)
+			continue;
+
+		/*  Found the correct setting?  */
+		if (fullname[settings_name_len] == '\0') {
+			if (writeflag)
+				return settings_write(settings, i, valuep);
+			else
+				return settings_read(settings, i, valuep);
+		}
+
+		/*  Found a setting which has sub-settings?  */
+		if (fullname[settings_name_len] == '.') {
+			/*  Recursive search:  */
+			return settings_access(
+			    (struct settings *)settings->ptr[i],
+			    fullname + settings_name_len + 1,
+			    writeflag, valuep);
+		}
+	}
+
+	return SETTINGS_NAME_NOT_FOUND;
+}
+
diff -Nru gxemul-0.6.2/src/core/timer.c gxemul-0.7.0+dfsg/src/core/timer.c
--- gxemul-0.6.2/src/core/timer.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/core/timer.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,301 @@
+/*
+ *  Copyright (C) 2006-2019  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Timer framework. This is used by emulated clocks.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/time.h>
+
+#include "misc.h"
+#include "timer.h"
+
+
+/*  #define TEST  */
+
+
+struct timer {
+	struct timer	*next;
+
+	double		freq;
+	void		(*timer_tick)(struct timer *timer, void *extra);
+	void		*extra;
+
+	double		interval;
+	double		next_tick_at;
+};
+
+static struct timer *first_timer = NULL;
+struct timeval timer_start_tv;
+static double timer_freq;
+static int timer_countdown_to_next_gettimeofday;
+static double timer_current_time;
+static double timer_current_time_step;
+
+static int timer_is_running;
+
+#define	SECONDS_BETWEEN_GETTIMEOFDAY_SYNCH	1.65
+
+
+/*
+ *  timer_add():
+ *
+ *  Adds a virtual timer to the list of timers.
+ *
+ *  Return value is a pointer to a timer struct.
+ */
+struct timer *timer_add(double freq, void (*timer_tick)(struct timer *timer,
+	void *extra), void *extra)
+{
+	struct timer *newtimer;
+
+	CHECK_ALLOCATION(newtimer = (struct timer *) malloc(sizeof(struct timer)));
+
+	if (freq <= 0.00000001)
+		freq = 0.00000001;
+
+	newtimer->freq = freq;
+	newtimer->timer_tick = timer_tick;
+	newtimer->extra = extra;
+
+	newtimer->interval = 1.0 / freq;
+	newtimer->next_tick_at = timer_current_time + newtimer->interval;
+
+	newtimer->next = first_timer;
+	first_timer = newtimer;
+
+	return newtimer;
+}
+
+
+/*
+ *  timer_remove():
+ *
+ *  Removes a virtual timer from the list of timers.
+ */
+void timer_remove(struct timer *t)
+{
+	struct timer *prev = NULL, *cur = first_timer;
+
+	while (cur != NULL && cur != t) {
+		prev = cur;
+		cur = cur->next;
+	}
+
+	if (cur == t) {
+		if (prev == NULL)
+			first_timer = cur->next;
+		else
+			prev->next = cur->next;
+		free(cur);
+	} else {
+		fprintf(stderr, "attempt to remove timer %p which "
+		    "doesn't exist. aborting\n", t);
+		exit(1);
+	}
+}
+
+
+/*
+ *  timer_update_frequency():
+ *
+ *  Changes the frequency of an existing timer.
+ */
+void timer_update_frequency(struct timer *t, double new_freq)
+{
+	if (t->freq == new_freq)
+		return;
+
+	t->freq = new_freq;
+
+	if (new_freq <= 0.00000001)
+		new_freq = 0.00000001;
+
+	t->interval = 1.0 / new_freq;
+	t->next_tick_at = timer_current_time + t->interval;
+}
+
+
+/*
+ *  timer_tick():
+ *
+ *  Timer tick handler. This is where the interesting stuff happens.
+ */
+static void timer_tick(int signal_nr)
+{
+	struct timer *timer = first_timer;
+	struct timeval tv;
+
+	timer_current_time += timer_current_time_step;
+
+	if ((--timer_countdown_to_next_gettimeofday) < 0) {
+		gettimeofday(&tv, NULL);
+		tv.tv_sec -= timer_start_tv.tv_sec;
+		tv.tv_usec -= timer_start_tv.tv_usec;
+		if (tv.tv_usec < 0) {
+			tv.tv_usec += 1000000;
+			tv.tv_sec --;
+		}
+
+#ifdef TIMER_DEBUG
+		/*  For debugging/testing:  */
+		{
+			double diff = tv.tv_usec * 0.000001 + tv.tv_sec
+			    - timer_current_time;
+			printf("timer: lagging behind %f seconds\n", diff);
+		}
+#endif
+
+		/*  Get exponentially closer to the real time, instead of
+		    just changing to it directly:  */
+		timer_current_time = ( (tv.tv_usec * 0.000001 + tv.tv_sec) +
+		    timer_current_time ) / 2;
+
+		timer_countdown_to_next_gettimeofday = (int64_t) (timer_freq *
+		    SECONDS_BETWEEN_GETTIMEOFDAY_SYNCH);
+	}
+
+	while (timer != NULL) {
+		while (timer_current_time >= timer->next_tick_at) {
+			timer->timer_tick(timer, timer->extra);
+			timer->next_tick_at += timer->interval;
+		}
+
+		timer = timer->next;
+	}
+
+#ifdef TEST
+	printf("T"); fflush(stdout);
+#endif
+}
+
+
+/*
+ *  timer_start():
+ *
+ *  Set the interval timer to timer_freq Hz, and install the signal handler.
+ */
+void timer_start(void)
+{
+	struct timer *timer = first_timer;
+	struct itimerval val;
+	struct sigaction saction;
+
+	if (timer_is_running)
+		return;
+
+	timer_is_running = 1;
+
+	gettimeofday(&timer_start_tv, NULL);
+	timer_current_time = 0.0;
+
+	/*  Reset all timers:  */
+	while (timer != NULL) {
+		timer->next_tick_at = timer->interval;
+		timer = timer->next;
+	}
+	val.it_interval.tv_sec = 0;
+	val.it_interval.tv_usec = (int) (1000000.0 / timer_freq);
+	val.it_value.tv_sec = 0;
+	val.it_value.tv_usec = (int) (1000000.0 / timer_freq);
+
+	memset(&saction, 0, sizeof(saction));
+	saction.sa_handler = timer_tick;
+	saction.sa_flags = SA_RESTART;
+
+	sigaction(SIGALRM, &saction, NULL);
+
+	setitimer(ITIMER_REAL, &val, NULL);
+}
+
+
+/*
+ *  timer_stop():
+ *
+ *  Deinstall the signal handler, and disable the interval timer.
+ */
+void timer_stop(void)
+{
+	struct itimerval val;
+	struct sigaction saction;
+
+	if (!timer_is_running)
+		return;
+
+	timer_is_running = 0;
+
+	val.it_interval.tv_sec = 0;
+	val.it_interval.tv_usec = 0;
+	val.it_value.tv_sec = 0;
+	val.it_value.tv_usec = 0;
+
+	setitimer(ITIMER_REAL, &val, NULL);
+
+	memset(&saction, 0, sizeof(saction));
+	saction.sa_handler = NULL;
+
+	sigaction(SIGALRM, &saction, NULL);
+}
+
+
+#ifdef TEST
+static void timer_tick_test(struct timer *t, void *extra)
+{
+	printf((char *) extra); fflush(stdout);
+}
+#endif
+
+
+/*
+ *  timer_init():
+ *
+ *  Initialize the timer framework.
+ */
+void timer_init(void)
+{
+	first_timer = NULL;
+	timer_current_time = 0.0;
+	timer_is_running = 0;
+	timer_countdown_to_next_gettimeofday = 0;
+
+	timer_freq = TIMER_BASE_FREQUENCY;
+	timer_current_time_step = 1.0 / timer_freq;
+
+#ifdef TEST
+	timer_add(0.5, timer_tick_test, "X");
+	timer_add(10.0, timer_tick_test, ".");
+	timer_add(200.0, timer_tick_test, " ");
+	timer_start();
+	while (1)
+		sleep(999999);
+#endif
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_alpha.c gxemul-0.7.0+dfsg/src/cpus/cpu_alpha.c
--- gxemul-0.6.2/src/cpus/cpu_alpha.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_alpha.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,680 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Alpha CPU emulation.
+ *
+ *  TODO: Many things.
+ *
+ *  See http://www.eecs.harvard.edu/~nr/toolkit/specs/alpha.html for info
+ *  on instruction formats etc.
+ */
+
+#include <ctype.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "cpu.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "settings.h"
+#include "symbol.h"
+
+#define	DYNTRANS_8K
+#define	DYNTRANS_PAGESIZE	8192
+#include "tmp_alpha_head.c"
+
+
+/*  Alpha symbolic register names:  */
+static const char *alpha_regname[N_ALPHA_REGS] = ALPHA_REG_NAMES; 
+
+void alpha_irq_interrupt_assert(struct interrupt *interrupt);
+void alpha_irq_interrupt_deassert(struct interrupt *interrupt);
+
+
+/*
+ *  alpha_cpu_new():
+ *
+ *  Create a new Alpha CPU object by filling the CPU struct.
+ *  Return 1 on success, 0 if cpu_type_name isn't a valid Alpha processor.
+ */
+int alpha_cpu_new(struct cpu *cpu, struct memory *mem,
+	struct machine *machine, int cpu_id, char *cpu_type_name)
+{
+	int i = 0;
+	struct alpha_cpu_type_def cpu_type_defs[] = ALPHA_CPU_TYPE_DEFS;
+
+	/*  Scan the cpu_type_defs list for this cpu type:  */
+	while (cpu_type_defs[i].name != NULL) {
+		if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
+			break;
+		}
+		i++;
+	}
+	if (cpu_type_defs[i].name == NULL)
+		return 0;
+
+	cpu->is_32bit = 0;
+	cpu->byte_order = EMUL_LITTLE_ENDIAN;
+
+	cpu->memory_rw = alpha_memory_rw;
+	cpu->run_instr = alpha_run_instr;
+	cpu->translate_v2p = alpha_translate_v2p;
+	cpu->update_translation_table = alpha_update_translation_table;
+	cpu->invalidate_translation_caches =
+	    alpha_invalidate_translation_caches;
+	cpu->invalidate_code_translation = alpha_invalidate_code_translation;
+
+	cpu->cd.alpha.cpu_type = cpu_type_defs[i];
+
+	cpu->cd.alpha.r[ALPHA_SP] = 0xfffffc000000ff00ULL;
+
+	/*  Set up dummy kentry pointers to something which crashes
+	    the machine:  */
+	store_32bit_word(cpu, 0x10010, 0x3fffffc);
+	for (i=0; i<N_ALPHA_KENTRY; i++)
+		cpu->cd.alpha.kentry[i] = 0x10010;
+
+	/*  Bogus initial context (will be overwritten on first
+	    context switch):  */
+	cpu->cd.alpha.ctx = 0x10100;
+
+	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
+	for (i=0; i<N_ALPHA_REGS; i++)
+		CPU_SETTINGS_ADD_REGISTER64(alpha_regname[i],
+		    cpu->cd.alpha.r[i]);
+
+	/*  Register the CPU interrupt pin:  */
+	{
+		struct interrupt templ;
+
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 0;
+		templ.name = cpu->path;
+		templ.extra = cpu;
+		templ.interrupt_assert = alpha_irq_interrupt_assert; 
+		templ.interrupt_deassert = alpha_irq_interrupt_deassert; 
+		interrupt_handler_register(&templ);
+	}
+
+	return 1;
+}
+
+
+/*
+ *  alpha_cpu_dumpinfo():
+ */
+void alpha_cpu_dumpinfo(struct cpu *cpu, bool verbose)
+{
+	debugmsg(SUBSYS_MACHINE, "cpu", VERBOSITY_INFO, "%s", cpu->name);
+}
+
+
+/*
+ *  alpha_cpu_list_available_types():
+ *
+ *  Print a list of available Alpha CPU types.
+ */
+void alpha_cpu_list_available_types(void)
+{
+	int i, j;
+	struct alpha_cpu_type_def tdefs[] = ALPHA_CPU_TYPE_DEFS;
+
+	i = 0;
+	while (tdefs[i].name != NULL) {
+		debug("%s", tdefs[i].name);
+		for (j=13 - strlen(tdefs[i].name); j>0; j--)
+			debug(" ");
+		i++;
+		if ((i % 4) == 0 || tdefs[i].name == NULL)
+			debug("\n");
+	}
+}
+
+
+/*
+ *  alpha_cpu_register_dump():
+ *  
+ *  Dump cpu registers in a relatively readable format.
+ *  
+ *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
+ *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
+ */
+void alpha_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
+{ 
+	char *symbol;
+	uint64_t offset;
+	int i, x = cpu->cpu_id;
+
+	if (gprs) {
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    cpu->pc, &offset);
+		debug("cpu%i:\t pc = 0x%016" PRIx64, x, (uint64_t) cpu->pc);
+		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
+		for (i=0; i<N_ALPHA_REGS; i++) {
+			int r = (i >> 1) + ((i & 1) << 4);
+			if ((i % 2) == 0)
+				debug("cpu%i:\t", x);
+			if (r != ALPHA_ZERO)
+				debug("%3s = 0x%016" PRIx64, alpha_regname[r],
+				    (uint64_t) cpu->cd.alpha.r[r]);
+			if ((i % 2) == 1)
+				debug("\n");
+			else
+				debug("   ");
+		}
+	}
+}
+
+
+/*
+ *  alpha_cpu_tlbdump():
+ *
+ *  Called from the debugger to dump the TLB in a readable format.
+ *  x is the cpu number to dump, or -1 to dump all CPUs.
+ *
+ *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
+ *  just dumped.
+ */
+void alpha_cpu_tlbdump(struct cpu* cpu, int rawflag)
+{
+}
+
+
+/*
+ *  alpha_irq_interrupt_assert():
+ *  alpha_irq_interrupt_deassert():
+ */
+void alpha_irq_interrupt_assert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.alpha.irq_asserted = 1;
+}
+void alpha_irq_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.alpha.irq_asserted = 0;
+}
+
+
+/*
+ *  alpha_print_imm16_disp():
+ *
+ *  Used internally by alpha_cpu_disassemble_instr().
+ */
+static void alpha_print_imm16_disp(int imm, int rb)
+{
+	imm = (int16_t)imm;
+
+	if (imm < 0) {
+		debug("-");
+		imm = -imm;
+	}
+	if (imm <= 256)
+		debug("%i", imm);
+	else
+		debug("0x%x", imm);
+	if (rb != ALPHA_ZERO)
+		debug("(%s)", alpha_regname[rb]);
+}
+
+
+/*
+ *  alpha_cpu_disassemble_instr():
+ *
+ *  Convert an instruction word into human readable format, for instruction
+ *  tracing.
+ *              
+ *  If running is 1, cpu->pc should be the address of the instruction.
+ *
+ *  If running is 0, things that depend on the runtime environment (eg.
+ *  register contents) will not be shown, and addr will be used instead of
+ *  cpu->pc for relative addresses.
+ */                     
+int alpha_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
+        int running, uint64_t dumpaddr)
+{
+	uint32_t iw;
+	uint64_t offset, tmp;
+	int opcode, ra, rb, func, rc, imm, floating, rbrc = 0, indir = 0;
+	const char *symbol, *mnem = NULL;
+	char palcode_name[30];
+
+	if (running)
+		dumpaddr = cpu->pc;
+
+	symbol = get_symbol_name(&cpu->machine->symbol_context,
+	    dumpaddr, &offset);
+	if (symbol != NULL && offset == 0)
+		debug("<%s>\n", symbol);
+
+	if (cpu->machine->ncpus > 1 && running)
+		debug("cpu%i:\t", cpu->cpu_id);
+
+	debug("%016" PRIx64":  ", (uint64_t) dumpaddr);
+
+	iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
+	debug("%08x", (int)iw);
+
+	cpu_print_pc_indicator_in_disassembly(cpu, running, dumpaddr);
+
+	opcode = iw >> 26;
+	ra = (iw >> 21) & 31;
+	rb = (iw >> 16) & 31;
+	func = (iw >> 5) & 0x7ff;
+	rc = iw & 31;
+	imm = iw & 0xffff;
+
+	switch (opcode) {
+	case 0x00:
+		alpha_palcode_name(iw & 0x3ffffff, palcode_name,
+		    sizeof(palcode_name));
+		debug("call_pal %s\n", palcode_name);
+		break;
+	case 0x08:
+	case 0x09:
+		debug("lda%s\t%s,", opcode == 9? "h" : "", alpha_regname[ra]);
+		alpha_print_imm16_disp(imm, rb);
+		debug("\n");
+		break;
+	case 0x0a:
+	case 0x0b:
+	case 0x0c:
+	case 0x0d:
+	case 0x0e:
+	case 0x0f:
+	case 0x20:
+	case 0x21:
+	case 0x22:
+	case 0x23:
+	case 0x24:
+	case 0x25:
+	case 0x26:
+	case 0x27:
+	case 0x28:
+	case 0x29:
+	case 0x2a:
+	case 0x2b:
+	case 0x2c:
+	case 0x2d:
+	case 0x2e:
+	case 0x2f:
+		floating = 0;
+		switch (opcode) {
+		case 0x0a: mnem = "ldbu"; break;
+		case 0x0b: mnem = "ldq_u"; break;
+		case 0x0c: mnem = "ldwu"; break;
+		case 0x0d: mnem = "stw"; break;
+		case 0x0e: mnem = "stb"; break;
+		case 0x0f: mnem = "stq_u"; break;
+		case 0x20: mnem = "ldf"; floating = 1; break;
+		case 0x21: mnem = "ldg"; floating = 1; break;
+		case 0x22: mnem = "lds"; floating = 1; break;
+		case 0x23: mnem = "ldt"; floating = 1; break;
+		case 0x24: mnem = "stf"; floating = 1; break;
+		case 0x25: mnem = "stg"; floating = 1; break;
+		case 0x26: mnem = "sts"; floating = 1; break;
+		case 0x27: mnem = "stt"; floating = 1; break;
+		case 0x28: mnem = "ldl"; break;
+		case 0x29: mnem = "ldq"; break;
+		case 0x2a: mnem = "ldl_l"; break;
+		case 0x2b: mnem = "ldq_l"; break;
+		case 0x2c: mnem = "stl"; break;
+		case 0x2d: mnem = "stq"; break;
+		case 0x2e: mnem = "stl_c"; break;
+		case 0x2f: mnem = "stq_c"; break;
+		}
+		if (opcode == 0x0b && ra == ALPHA_ZERO) {
+			debug("unop");
+		} else {
+			debug("%s\t", mnem);
+			if (floating)
+				debug("f%i,", ra);
+			else
+				debug("%s,", alpha_regname[ra]);
+			alpha_print_imm16_disp(imm, rb);
+		}
+		debug("\n");
+		break;
+	case 0x10:
+		switch (func & 0x7f) {
+		case 0x00: mnem = "addl"; break;
+		case 0x02: mnem = "s4addl"; break;
+		case 0x09: mnem = "subl"; break;
+		case 0x0b: mnem = "s4subl"; break;
+		case 0x0f: mnem = "cmpbge"; break;
+		case 0x12: mnem = "s8addl"; break;
+		case 0x1b: mnem = "s8subl"; break;
+		case 0x1d: mnem = "cmpult"; break;
+		case 0x20: mnem = "addq"; break;
+		case 0x22: mnem = "s4addq"; break;
+		case 0x29: mnem = "subq"; break;
+		case 0x2b: mnem = "s4subq"; break;
+		case 0x2d: mnem = "cmpeq"; break;
+		case 0x32: mnem = "s8addq"; break;
+		case 0x3b: mnem = "s8subq"; break;
+		case 0x3d: mnem = "cmpule"; break;
+		case 0x40: mnem = "addl/v"; break;
+		case 0x49: mnem = "subl/v"; break;
+		case 0x4d: mnem = "cmplt"; break;
+		case 0x60: mnem = "addq/v"; break;
+		case 0x69: mnem = "subq/v"; break;
+		case 0x6d: mnem = "cmple"; break;
+		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
+			    opcode, func);
+		}
+		if (mnem == NULL)
+			break;
+		if (func & 0x80)
+			debug("%s\t%s,0x%x,%s\n", mnem,
+			    alpha_regname[ra], (rb << 3) + (func >> 8),
+			    alpha_regname[rc]);
+		else
+			debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra],
+			    alpha_regname[rb], alpha_regname[rc]);
+		break;
+	case 0x11:
+		switch (func & 0x7f) {
+		case 0x000: mnem = "and"; break;
+		case 0x008: mnem = "andnot"; break;
+		case 0x014: mnem = "cmovlbs"; break;
+		case 0x016: mnem = "cmovlbc"; break;
+		case 0x020: mnem = "or"; break;
+		case 0x024: mnem = "cmoveq"; break;
+		case 0x026: mnem = "cmovne"; break;
+		case 0x028: mnem = "ornot"; break;
+		case 0x040: mnem = "xor"; break;
+		case 0x044: mnem = "cmovlt"; break;
+		case 0x046: mnem = "cmovge"; break;
+		case 0x048: mnem = "eqv"; break;
+		case 0x061: mnem = "amask"; break;
+		case 0x064: mnem = "cmovle"; break;
+		case 0x066: mnem = "cmovgt"; break;
+		case 0x06c: mnem = "implver"; break;
+		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
+			    opcode, func);
+		}
+		if (mnem == NULL)
+			break;
+		/*  Special cases: "nop" etc:  */
+		if (func == 0x020 && rc == ALPHA_ZERO)
+			debug("nop\n");
+		else if (func == 0x020 && (ra == ALPHA_ZERO
+		    || rb == ALPHA_ZERO)) {
+			if (ra == ALPHA_ZERO && rb == ALPHA_ZERO)
+				debug("clr\t%s\n", alpha_regname[rc]);
+			else if (ra == ALPHA_ZERO)
+				debug("mov\t%s,%s\n", alpha_regname[rb],
+				    alpha_regname[rc]);
+			else
+				debug("mov\t%s,%s\n", alpha_regname[ra],
+				    alpha_regname[rc]);
+		} else if (func == 0x1ec) {
+			/*  implver  */
+			debug("%s\t%s\n", mnem, alpha_regname[rc]);
+		} else if (func & 0x80)
+			debug("%s\t%s,0x%x,%s\n", mnem,
+			    alpha_regname[ra], (rb << 3) + (func >> 8),
+			    alpha_regname[rc]);
+		else
+			debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra],
+			    alpha_regname[rb], alpha_regname[rc]);
+		break;
+	case 0x12:
+		switch (func & 0x7f) {
+		case 0x02: mnem = "mskbl"; break;
+		case 0x06: mnem = "extbl"; break;
+		case 0x0b: mnem = "insbl"; break;
+		case 0x12: mnem = "mskwl"; break;
+		case 0x16: mnem = "extwl"; break;
+		case 0x1b: mnem = "inswl"; break;
+		case 0x22: mnem = "mskll"; break;
+		case 0x26: mnem = "extll"; break;
+		case 0x2b: mnem = "insll"; break;
+		case 0x30: mnem = "zap"; break;
+		case 0x31: mnem = "zapnot"; break;
+		case 0x32: mnem = "mskql"; break;
+		case 0x34: mnem = "srl"; break;
+		case 0x36: mnem = "extql"; break;
+		case 0x39: mnem = "sll"; break;
+		case 0x3b: mnem = "insql"; break;
+		case 0x3c: mnem = "sra"; break;
+		case 0x52: mnem = "mskwh"; break;
+		case 0x57: mnem = "inswh"; break;
+		case 0x5a: mnem = "extwh"; break;
+		case 0x62: mnem = "msklh"; break;
+		case 0x67: mnem = "inslh"; break;
+		case 0x6a: mnem = "extlh"; break;
+		case 0x72: mnem = "mskqh"; break;
+		case 0x77: mnem = "insqh"; break;
+		case 0x7a: mnem = "extqh"; break;
+		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
+			    opcode, func);
+		}
+		if (mnem == NULL)
+			break;
+		if (func & 0x80)
+			debug("%s\t%s,0x%x,%s\n", mnem,
+			    alpha_regname[ra], (rb << 3) + (func >> 8),
+			    alpha_regname[rc]);
+		else
+			debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra],
+			    alpha_regname[rb], alpha_regname[rc]);
+		break;
+	case 0x13:
+		switch (func & 0x7f) {
+		case 0x00: mnem = "mull"; break;
+		case 0x20: mnem = "mulq"; break;
+		case 0x30: mnem = "umulh"; break;
+		case 0x40: mnem = "mull/v"; break;
+		case 0x60: mnem = "mulq/v"; break;
+		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
+			    opcode, func);
+		}
+		if (mnem == NULL)
+			break;
+		if (func & 0x80)
+			debug("%s\t%s,0x%x,%s\n", mnem,
+			    alpha_regname[ra], (rb << 3) + (func >> 8),
+			    alpha_regname[rc]);
+		else
+			debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra],
+			    alpha_regname[rb], alpha_regname[rc]);
+		break;
+	case 0x16:
+		switch (func & 0x7ff) {
+		case 0x02f: mnem = "cvttq/c"; rbrc = 1; break;
+		case 0x080: mnem = "adds"; break;
+		case 0x081: mnem = "subs"; break;
+		case 0x082: mnem = "muls"; break;
+		case 0x083: mnem = "XXXx083"; break;
+		case 0x0a0: mnem = "addt"; break;
+		case 0x0a1: mnem = "subt"; break;
+		case 0x0a2: mnem = "mult"; break;
+		case 0x0a3: mnem = "divt"; break;
+		case 0x0a5: mnem = "cmpteq"; break;
+		case 0x0a6: mnem = "cmptlt"; break;
+		case 0x0a7: mnem = "cmptle"; break;
+		case 0x0be: mnem = "cvtqt"; rbrc = 1; break;
+		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
+			    opcode, func);
+		}
+		if (mnem == NULL)
+			break;
+		if (rbrc)
+			debug("%s\tf%i,f%i\n", mnem, rb, rc);
+		else
+			debug("%s\tf%i,f%i,f%i\n", mnem, ra, rb, rc);
+		break;
+	case 0x17:
+		switch (func & 0x7ff) {
+		case 0x020: mnem = "fabs"; rbrc = 1; break;
+		case 0x021: mnem = "fneg"; rbrc = 1; break;
+		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
+			    opcode, func);
+		}
+		if (mnem == NULL)
+			break;
+		if ((func & 0x7ff) == 0x020 && ra == 31 && rb == 31)
+			debug("fclr\tf%i\n", rc);
+		else if (rbrc)
+			debug("%s\tf%i,f%i\n", mnem, rb, rc);
+		else
+			debug("%s\tf%i,f%i,f%i\n", mnem, ra, rb, rc);
+		break;
+	case 0x18:
+		switch (iw & 0xffff) {
+		case 0x0000: mnem = "trapb"; break;
+		case 0x0400: mnem = "excb"; break;
+		case 0x4000: mnem = "mb"; break;
+		case 0x4400: mnem = "wmb"; break;
+		case 0x8000: mnem = "fetch"; indir = 1; break;
+		case 0xa000: mnem = "fetch_m"; indir = 1; break;
+		case 0xc000: mnem = "rpcc"; break;
+		case 0xe000: mnem = "rc"; break;
+		case 0xe800: mnem = "ecb"; indir = 1; break;
+		case 0xf000: mnem = "rs"; break;
+		case 0xf800: mnem = "wh64"; indir = 1; break;
+		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
+			    opcode, func);
+		}
+		if (mnem == NULL)
+			break;
+		debug("%s", mnem);
+		if ((iw & 0xffff) >= 0x8000) {
+			debug("\t");
+			if (indir)
+				debug("(%s)", alpha_regname[rb]);
+			else
+				debug("%s", alpha_regname[ra]);
+		}
+		debug("\n");
+		break;
+	case 0x1a:
+		tmp = iw & 0x3fff;
+		if (tmp & 0x2000)
+			tmp |= 0xffffffffffffc000ULL;
+		tmp <<= 2;
+		tmp += dumpaddr + sizeof(uint32_t);
+		switch ((iw >> 14) & 3) {
+		case 0:
+		case 1:	if (((iw >> 14) & 3) == 0)
+				debug("jmp");
+			else
+				debug("jsr");
+			debug("\t%s,", alpha_regname[ra]);
+			debug("(%s),", alpha_regname[rb]);
+			debug("0x%" PRIx64, (uint64_t) tmp);
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    tmp, &offset);
+			if (symbol != NULL)
+				debug("\t<%s>", symbol);
+			break;
+		case 2:	debug("ret");
+			break;
+		default:fatal("unimpl JSR!");
+		}
+		debug("\n");
+		break;
+	case 0x30:
+	case 0x34:
+		tmp = iw & 0x1fffff;
+		if (tmp & 0x100000)
+			tmp |= 0xffffffffffe00000ULL;
+		tmp <<= 2;
+		tmp += dumpaddr + sizeof(uint32_t);
+		debug("%s\t", opcode==0x30? "br" : "bsr");
+		if (ra != ALPHA_ZERO)
+			debug("%s,", alpha_regname[ra]);
+		debug("0x%" PRIx64, (uint64_t) tmp);
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    tmp, &offset);
+		if (symbol != NULL)
+			debug("\t<%s>", symbol);
+		debug("\n");
+		break;
+	case 0x31:
+	case 0x35:
+	case 0x38:
+	case 0x39:
+	case 0x3a:
+	case 0x3b:
+	case 0x3c:
+	case 0x3d:
+	case 0x3e:
+	case 0x3f:
+		floating = 0;
+		switch (opcode) {
+		case 0x31: mnem = "fbeq"; floating = 1; break;
+		case 0x35: mnem = "fbne"; floating = 1; break;
+		case 0x38: mnem = "blbc"; break;
+		case 0x39: mnem = "beq"; break;
+		case 0x3a: mnem = "blt"; break;
+		case 0x3b: mnem = "ble"; break;
+		case 0x3c: mnem = "blbs"; break;
+		case 0x3d: mnem = "bne"; break;
+		case 0x3e: mnem = "bge"; break;
+		case 0x3f: mnem = "bgt"; break;
+		}
+		tmp = iw & 0x1fffff;
+		if (tmp & 0x100000)
+			tmp |= 0xffffffffffe00000ULL;
+		tmp <<= 2;
+		tmp += dumpaddr + sizeof(uint32_t);
+		debug("%s\t", mnem);
+		if (floating)
+			debug("f%i,", ra);
+		else
+			debug("%s,", alpha_regname[ra]);
+		debug("0x%" PRIx64, (uint64_t) tmp);
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    tmp, &offset);
+		if (symbol != NULL)
+			debug("\t<%s>", symbol);
+		debug("\n");
+		break;
+	default:debug("UNIMPLEMENTED opcode 0x%x\n", opcode);
+	}
+
+	return sizeof(uint32_t);
+}
+
+
+#define MEMORY_RW       alpha_userland_memory_rw
+#define MEM_ALPHA
+#define MEM_USERLAND
+#include "memory_rw.c"
+#undef MEM_USERLAND
+#undef MEM_ALPHA
+#undef MEMORY_RW
+
+
+#include "tmp_alpha_tail.c"
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_alpha.cc gxemul-0.7.0+dfsg/src/cpus/cpu_alpha.cc
--- gxemul-0.6.2/src/cpus/cpu_alpha.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_alpha.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,683 +0,0 @@
-/*
- *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Alpha CPU emulation.
- *
- *  TODO: Many things.
- *
- *  See http://www.eecs.harvard.edu/~nr/toolkit/specs/alpha.html for info
- *  on instruction formats etc.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <ctype.h>
-
-#include "cpu.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "settings.h"
-#include "symbol.h"
-
-#define	DYNTRANS_8K
-#define	DYNTRANS_PAGESIZE	8192
-#include "tmp_alpha_head.cc"
-
-
-/*  Alpha symbolic register names:  */
-static const char *alpha_regname[N_ALPHA_REGS] = ALPHA_REG_NAMES; 
-
-void alpha_irq_interrupt_assert(struct interrupt *interrupt);
-void alpha_irq_interrupt_deassert(struct interrupt *interrupt);
-
-
-/*
- *  alpha_cpu_new():
- *
- *  Create a new Alpha CPU object by filling the CPU struct.
- *  Return 1 on success, 0 if cpu_type_name isn't a valid Alpha processor.
- */
-int alpha_cpu_new(struct cpu *cpu, struct memory *mem,
-	struct machine *machine, int cpu_id, char *cpu_type_name)
-{
-	int i = 0;
-	struct alpha_cpu_type_def cpu_type_defs[] = ALPHA_CPU_TYPE_DEFS;
-
-	/*  Scan the cpu_type_defs list for this cpu type:  */
-	while (cpu_type_defs[i].name != NULL) {
-		if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
-			break;
-		}
-		i++;
-	}
-	if (cpu_type_defs[i].name == NULL)
-		return 0;
-
-	cpu->is_32bit = 0;
-	cpu->byte_order = EMUL_LITTLE_ENDIAN;
-
-	cpu->memory_rw = alpha_memory_rw;
-	cpu->run_instr = alpha_run_instr;
-	cpu->translate_v2p = alpha_translate_v2p;
-	cpu->update_translation_table = alpha_update_translation_table;
-	cpu->invalidate_translation_caches =
-	    alpha_invalidate_translation_caches;
-	cpu->invalidate_code_translation = alpha_invalidate_code_translation;
-
-	cpu->cd.alpha.cpu_type = cpu_type_defs[i];
-
-	/*  Only show name and caches etc for CPU nr 0:  */
-	if (cpu_id == 0) {
-		debug("%s", cpu->name);
-	}
-
-	cpu->cd.alpha.r[ALPHA_SP] = 0xfffffc000000ff00ULL;
-
-	/*  Set up dummy kentry pointers to something which crashes
-	    the machine:  */
-	store_32bit_word(cpu, 0x10010, 0x3fffffc);
-	for (i=0; i<N_ALPHA_KENTRY; i++)
-		cpu->cd.alpha.kentry[i] = 0x10010;
-
-	/*  Bogus initial context (will be overwritten on first
-	    context switch):  */
-	cpu->cd.alpha.ctx = 0x10100;
-
-	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
-	for (i=0; i<N_ALPHA_REGS; i++)
-		CPU_SETTINGS_ADD_REGISTER64(alpha_regname[i],
-		    cpu->cd.alpha.r[i]);
-
-	/*  Register the CPU interrupt pin:  */
-	{
-		struct interrupt templ;
-
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 0;
-		templ.name = cpu->path;
-		templ.extra = cpu;
-		templ.interrupt_assert = alpha_irq_interrupt_assert; 
-		templ.interrupt_deassert = alpha_irq_interrupt_deassert; 
-		interrupt_handler_register(&templ);
-	}
-
-	return 1;
-}
-
-
-/*
- *  alpha_cpu_dumpinfo():
- */
-void alpha_cpu_dumpinfo(struct cpu *cpu)
-{
-	/*  TODO  */
-	debug("\n");
-}
-
-
-/*
- *  alpha_cpu_list_available_types():
- *
- *  Print a list of available Alpha CPU types.
- */
-void alpha_cpu_list_available_types(void)
-{
-	int i, j;
-	struct alpha_cpu_type_def tdefs[] = ALPHA_CPU_TYPE_DEFS;
-
-	i = 0;
-	while (tdefs[i].name != NULL) {
-		debug("%s", tdefs[i].name);
-		for (j=13 - strlen(tdefs[i].name); j>0; j--)
-			debug(" ");
-		i++;
-		if ((i % 4) == 0 || tdefs[i].name == NULL)
-			debug("\n");
-	}
-}
-
-
-/*
- *  alpha_cpu_register_dump():
- *  
- *  Dump cpu registers in a relatively readable format.
- *  
- *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
- *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
- */
-void alpha_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
-{ 
-	char *symbol;
-	uint64_t offset;
-	int i, x = cpu->cpu_id;
-
-	if (gprs) {
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    cpu->pc, &offset);
-		debug("cpu%i:\t pc = 0x%016" PRIx64, x, (uint64_t) cpu->pc);
-		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
-		for (i=0; i<N_ALPHA_REGS; i++) {
-			int r = (i >> 1) + ((i & 1) << 4);
-			if ((i % 2) == 0)
-				debug("cpu%i:\t", x);
-			if (r != ALPHA_ZERO)
-				debug("%3s = 0x%016" PRIx64, alpha_regname[r],
-				    (uint64_t) cpu->cd.alpha.r[r]);
-			if ((i % 2) == 1)
-				debug("\n");
-			else
-				debug("   ");
-		}
-	}
-}
-
-
-/*
- *  alpha_cpu_tlbdump():
- *
- *  Called from the debugger to dump the TLB in a readable format.
- *  x is the cpu number to dump, or -1 to dump all CPUs.
- *
- *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
- *  just dumped.
- */
-void alpha_cpu_tlbdump(struct machine *m, int x, int rawflag)
-{
-}
-
-
-/*
- *  alpha_irq_interrupt_assert():
- *  alpha_irq_interrupt_deassert():
- */
-void alpha_irq_interrupt_assert(struct interrupt *interrupt)
-{
-	struct cpu *cpu = (struct cpu *) interrupt->extra;
-	cpu->cd.alpha.irq_asserted = 1;
-}
-void alpha_irq_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct cpu *cpu = (struct cpu *) interrupt->extra;
-	cpu->cd.alpha.irq_asserted = 0;
-}
-
-
-/*
- *  alpha_print_imm16_disp():
- *
- *  Used internally by alpha_cpu_disassemble_instr().
- */
-static void alpha_print_imm16_disp(int imm, int rb)
-{
-	imm = (int16_t)imm;
-
-	if (imm < 0) {
-		debug("-");
-		imm = -imm;
-	}
-	if (imm <= 256)
-		debug("%i", imm);
-	else
-		debug("0x%x", imm);
-	if (rb != ALPHA_ZERO)
-		debug("(%s)", alpha_regname[rb]);
-}
-
-
-/*
- *  alpha_cpu_disassemble_instr():
- *
- *  Convert an instruction word into human readable format, for instruction
- *  tracing.
- *              
- *  If running is 1, cpu->pc should be the address of the instruction.
- *
- *  If running is 0, things that depend on the runtime environment (eg.
- *  register contents) will not be shown, and addr will be used instead of
- *  cpu->pc for relative addresses.
- */                     
-int alpha_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
-        int running, uint64_t dumpaddr)
-{
-	uint32_t iw;
-	uint64_t offset, tmp;
-	int opcode, ra, rb, func, rc, imm, floating, rbrc = 0, indir = 0;
-	const char *symbol, *mnem = NULL;
-	char palcode_name[30];
-
-	if (running)
-		dumpaddr = cpu->pc;
-
-	symbol = get_symbol_name(&cpu->machine->symbol_context,
-	    dumpaddr, &offset);
-	if (symbol != NULL && offset == 0)
-		debug("<%s>\n", symbol);
-
-	if (cpu->machine->ncpus > 1 && running)
-		debug("cpu%i:\t", cpu->cpu_id);
-
-	debug("%016" PRIx64":  ", (uint64_t) dumpaddr);
-
-	iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
-	debug("%08x\t", (int)iw);
-
-	opcode = iw >> 26;
-	ra = (iw >> 21) & 31;
-	rb = (iw >> 16) & 31;
-	func = (iw >> 5) & 0x7ff;
-	rc = iw & 31;
-	imm = iw & 0xffff;
-
-	switch (opcode) {
-	case 0x00:
-		alpha_palcode_name(iw & 0x3ffffff, palcode_name,
-		    sizeof(palcode_name));
-		debug("call_pal %s\n", palcode_name);
-		break;
-	case 0x08:
-	case 0x09:
-		debug("lda%s\t%s,", opcode == 9? "h" : "", alpha_regname[ra]);
-		alpha_print_imm16_disp(imm, rb);
-		debug("\n");
-		break;
-	case 0x0a:
-	case 0x0b:
-	case 0x0c:
-	case 0x0d:
-	case 0x0e:
-	case 0x0f:
-	case 0x20:
-	case 0x21:
-	case 0x22:
-	case 0x23:
-	case 0x24:
-	case 0x25:
-	case 0x26:
-	case 0x27:
-	case 0x28:
-	case 0x29:
-	case 0x2a:
-	case 0x2b:
-	case 0x2c:
-	case 0x2d:
-	case 0x2e:
-	case 0x2f:
-		floating = 0;
-		switch (opcode) {
-		case 0x0a: mnem = "ldbu"; break;
-		case 0x0b: mnem = "ldq_u"; break;
-		case 0x0c: mnem = "ldwu"; break;
-		case 0x0d: mnem = "stw"; break;
-		case 0x0e: mnem = "stb"; break;
-		case 0x0f: mnem = "stq_u"; break;
-		case 0x20: mnem = "ldf"; floating = 1; break;
-		case 0x21: mnem = "ldg"; floating = 1; break;
-		case 0x22: mnem = "lds"; floating = 1; break;
-		case 0x23: mnem = "ldt"; floating = 1; break;
-		case 0x24: mnem = "stf"; floating = 1; break;
-		case 0x25: mnem = "stg"; floating = 1; break;
-		case 0x26: mnem = "sts"; floating = 1; break;
-		case 0x27: mnem = "stt"; floating = 1; break;
-		case 0x28: mnem = "ldl"; break;
-		case 0x29: mnem = "ldq"; break;
-		case 0x2a: mnem = "ldl_l"; break;
-		case 0x2b: mnem = "ldq_l"; break;
-		case 0x2c: mnem = "stl"; break;
-		case 0x2d: mnem = "stq"; break;
-		case 0x2e: mnem = "stl_c"; break;
-		case 0x2f: mnem = "stq_c"; break;
-		}
-		if (opcode == 0x0b && ra == ALPHA_ZERO) {
-			debug("unop");
-		} else {
-			debug("%s\t", mnem);
-			if (floating)
-				debug("f%i,", ra);
-			else
-				debug("%s,", alpha_regname[ra]);
-			alpha_print_imm16_disp(imm, rb);
-		}
-		debug("\n");
-		break;
-	case 0x10:
-		switch (func & 0x7f) {
-		case 0x00: mnem = "addl"; break;
-		case 0x02: mnem = "s4addl"; break;
-		case 0x09: mnem = "subl"; break;
-		case 0x0b: mnem = "s4subl"; break;
-		case 0x0f: mnem = "cmpbge"; break;
-		case 0x12: mnem = "s8addl"; break;
-		case 0x1b: mnem = "s8subl"; break;
-		case 0x1d: mnem = "cmpult"; break;
-		case 0x20: mnem = "addq"; break;
-		case 0x22: mnem = "s4addq"; break;
-		case 0x29: mnem = "subq"; break;
-		case 0x2b: mnem = "s4subq"; break;
-		case 0x2d: mnem = "cmpeq"; break;
-		case 0x32: mnem = "s8addq"; break;
-		case 0x3b: mnem = "s8subq"; break;
-		case 0x3d: mnem = "cmpule"; break;
-		case 0x40: mnem = "addl/v"; break;
-		case 0x49: mnem = "subl/v"; break;
-		case 0x4d: mnem = "cmplt"; break;
-		case 0x60: mnem = "addq/v"; break;
-		case 0x69: mnem = "subq/v"; break;
-		case 0x6d: mnem = "cmple"; break;
-		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
-			    opcode, func);
-		}
-		if (mnem == NULL)
-			break;
-		if (func & 0x80)
-			debug("%s\t%s,0x%x,%s\n", mnem,
-			    alpha_regname[ra], (rb << 3) + (func >> 8),
-			    alpha_regname[rc]);
-		else
-			debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra],
-			    alpha_regname[rb], alpha_regname[rc]);
-		break;
-	case 0x11:
-		switch (func & 0x7f) {
-		case 0x000: mnem = "and"; break;
-		case 0x008: mnem = "andnot"; break;
-		case 0x014: mnem = "cmovlbs"; break;
-		case 0x016: mnem = "cmovlbc"; break;
-		case 0x020: mnem = "or"; break;
-		case 0x024: mnem = "cmoveq"; break;
-		case 0x026: mnem = "cmovne"; break;
-		case 0x028: mnem = "ornot"; break;
-		case 0x040: mnem = "xor"; break;
-		case 0x044: mnem = "cmovlt"; break;
-		case 0x046: mnem = "cmovge"; break;
-		case 0x048: mnem = "eqv"; break;
-		case 0x061: mnem = "amask"; break;
-		case 0x064: mnem = "cmovle"; break;
-		case 0x066: mnem = "cmovgt"; break;
-		case 0x06c: mnem = "implver"; break;
-		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
-			    opcode, func);
-		}
-		if (mnem == NULL)
-			break;
-		/*  Special cases: "nop" etc:  */
-		if (func == 0x020 && rc == ALPHA_ZERO)
-			debug("nop\n");
-		else if (func == 0x020 && (ra == ALPHA_ZERO
-		    || rb == ALPHA_ZERO)) {
-			if (ra == ALPHA_ZERO && rb == ALPHA_ZERO)
-				debug("clr\t%s\n", alpha_regname[rc]);
-			else if (ra == ALPHA_ZERO)
-				debug("mov\t%s,%s\n", alpha_regname[rb],
-				    alpha_regname[rc]);
-			else
-				debug("mov\t%s,%s\n", alpha_regname[ra],
-				    alpha_regname[rc]);
-		} else if (func == 0x1ec) {
-			/*  implver  */
-			debug("%s\t%s\n", mnem, alpha_regname[rc]);
-		} else if (func & 0x80)
-			debug("%s\t%s,0x%x,%s\n", mnem,
-			    alpha_regname[ra], (rb << 3) + (func >> 8),
-			    alpha_regname[rc]);
-		else
-			debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra],
-			    alpha_regname[rb], alpha_regname[rc]);
-		break;
-	case 0x12:
-		switch (func & 0x7f) {
-		case 0x02: mnem = "mskbl"; break;
-		case 0x06: mnem = "extbl"; break;
-		case 0x0b: mnem = "insbl"; break;
-		case 0x12: mnem = "mskwl"; break;
-		case 0x16: mnem = "extwl"; break;
-		case 0x1b: mnem = "inswl"; break;
-		case 0x22: mnem = "mskll"; break;
-		case 0x26: mnem = "extll"; break;
-		case 0x2b: mnem = "insll"; break;
-		case 0x30: mnem = "zap"; break;
-		case 0x31: mnem = "zapnot"; break;
-		case 0x32: mnem = "mskql"; break;
-		case 0x34: mnem = "srl"; break;
-		case 0x36: mnem = "extql"; break;
-		case 0x39: mnem = "sll"; break;
-		case 0x3b: mnem = "insql"; break;
-		case 0x3c: mnem = "sra"; break;
-		case 0x52: mnem = "mskwh"; break;
-		case 0x57: mnem = "inswh"; break;
-		case 0x5a: mnem = "extwh"; break;
-		case 0x62: mnem = "msklh"; break;
-		case 0x67: mnem = "inslh"; break;
-		case 0x6a: mnem = "extlh"; break;
-		case 0x72: mnem = "mskqh"; break;
-		case 0x77: mnem = "insqh"; break;
-		case 0x7a: mnem = "extqh"; break;
-		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
-			    opcode, func);
-		}
-		if (mnem == NULL)
-			break;
-		if (func & 0x80)
-			debug("%s\t%s,0x%x,%s\n", mnem,
-			    alpha_regname[ra], (rb << 3) + (func >> 8),
-			    alpha_regname[rc]);
-		else
-			debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra],
-			    alpha_regname[rb], alpha_regname[rc]);
-		break;
-	case 0x13:
-		switch (func & 0x7f) {
-		case 0x00: mnem = "mull"; break;
-		case 0x20: mnem = "mulq"; break;
-		case 0x30: mnem = "umulh"; break;
-		case 0x40: mnem = "mull/v"; break;
-		case 0x60: mnem = "mulq/v"; break;
-		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
-			    opcode, func);
-		}
-		if (mnem == NULL)
-			break;
-		if (func & 0x80)
-			debug("%s\t%s,0x%x,%s\n", mnem,
-			    alpha_regname[ra], (rb << 3) + (func >> 8),
-			    alpha_regname[rc]);
-		else
-			debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra],
-			    alpha_regname[rb], alpha_regname[rc]);
-		break;
-	case 0x16:
-		switch (func & 0x7ff) {
-		case 0x02f: mnem = "cvttq/c"; rbrc = 1; break;
-		case 0x080: mnem = "adds"; break;
-		case 0x081: mnem = "subs"; break;
-		case 0x082: mnem = "muls"; break;
-		case 0x083: mnem = "XXXx083"; break;
-		case 0x0a0: mnem = "addt"; break;
-		case 0x0a1: mnem = "subt"; break;
-		case 0x0a2: mnem = "mult"; break;
-		case 0x0a3: mnem = "divt"; break;
-		case 0x0a5: mnem = "cmpteq"; break;
-		case 0x0a6: mnem = "cmptlt"; break;
-		case 0x0a7: mnem = "cmptle"; break;
-		case 0x0be: mnem = "cvtqt"; rbrc = 1; break;
-		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
-			    opcode, func);
-		}
-		if (mnem == NULL)
-			break;
-		if (rbrc)
-			debug("%s\tf%i,f%i\n", mnem, rb, rc);
-		else
-			debug("%s\tf%i,f%i,f%i\n", mnem, ra, rb, rc);
-		break;
-	case 0x17:
-		switch (func & 0x7ff) {
-		case 0x020: mnem = "fabs"; rbrc = 1; break;
-		case 0x021: mnem = "fneg"; rbrc = 1; break;
-		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
-			    opcode, func);
-		}
-		if (mnem == NULL)
-			break;
-		if ((func & 0x7ff) == 0x020 && ra == 31 && rb == 31)
-			debug("fclr\tf%i\n", rc);
-		else if (rbrc)
-			debug("%s\tf%i,f%i\n", mnem, rb, rc);
-		else
-			debug("%s\tf%i,f%i,f%i\n", mnem, ra, rb, rc);
-		break;
-	case 0x18:
-		switch (iw & 0xffff) {
-		case 0x0000: mnem = "trapb"; break;
-		case 0x0400: mnem = "excb"; break;
-		case 0x4000: mnem = "mb"; break;
-		case 0x4400: mnem = "wmb"; break;
-		case 0x8000: mnem = "fetch"; indir = 1; break;
-		case 0xa000: mnem = "fetch_m"; indir = 1; break;
-		case 0xc000: mnem = "rpcc"; break;
-		case 0xe000: mnem = "rc"; break;
-		case 0xe800: mnem = "ecb"; indir = 1; break;
-		case 0xf000: mnem = "rs"; break;
-		case 0xf800: mnem = "wh64"; indir = 1; break;
-		default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n",
-			    opcode, func);
-		}
-		if (mnem == NULL)
-			break;
-		debug("%s", mnem);
-		if ((iw & 0xffff) >= 0x8000) {
-			debug("\t");
-			if (indir)
-				debug("(%s)", alpha_regname[rb]);
-			else
-				debug("%s", alpha_regname[ra]);
-		}
-		debug("\n");
-		break;
-	case 0x1a:
-		tmp = iw & 0x3fff;
-		if (tmp & 0x2000)
-			tmp |= 0xffffffffffffc000ULL;
-		tmp <<= 2;
-		tmp += dumpaddr + sizeof(uint32_t);
-		switch ((iw >> 14) & 3) {
-		case 0:
-		case 1:	if (((iw >> 14) & 3) == 0)
-				debug("jmp");
-			else
-				debug("jsr");
-			debug("\t%s,", alpha_regname[ra]);
-			debug("(%s),", alpha_regname[rb]);
-			debug("0x%" PRIx64, (uint64_t) tmp);
-			symbol = get_symbol_name(&cpu->machine->symbol_context,
-			    tmp, &offset);
-			if (symbol != NULL)
-				debug("\t<%s>", symbol);
-			break;
-		case 2:	debug("ret");
-			break;
-		default:fatal("unimpl JSR!");
-		}
-		debug("\n");
-		break;
-	case 0x30:
-	case 0x34:
-		tmp = iw & 0x1fffff;
-		if (tmp & 0x100000)
-			tmp |= 0xffffffffffe00000ULL;
-		tmp <<= 2;
-		tmp += dumpaddr + sizeof(uint32_t);
-		debug("%s\t", opcode==0x30? "br" : "bsr");
-		if (ra != ALPHA_ZERO)
-			debug("%s,", alpha_regname[ra]);
-		debug("0x%" PRIx64, (uint64_t) tmp);
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    tmp, &offset);
-		if (symbol != NULL)
-			debug("\t<%s>", symbol);
-		debug("\n");
-		break;
-	case 0x31:
-	case 0x35:
-	case 0x38:
-	case 0x39:
-	case 0x3a:
-	case 0x3b:
-	case 0x3c:
-	case 0x3d:
-	case 0x3e:
-	case 0x3f:
-		floating = 0;
-		switch (opcode) {
-		case 0x31: mnem = "fbeq"; floating = 1; break;
-		case 0x35: mnem = "fbne"; floating = 1; break;
-		case 0x38: mnem = "blbc"; break;
-		case 0x39: mnem = "beq"; break;
-		case 0x3a: mnem = "blt"; break;
-		case 0x3b: mnem = "ble"; break;
-		case 0x3c: mnem = "blbs"; break;
-		case 0x3d: mnem = "bne"; break;
-		case 0x3e: mnem = "bge"; break;
-		case 0x3f: mnem = "bgt"; break;
-		}
-		tmp = iw & 0x1fffff;
-		if (tmp & 0x100000)
-			tmp |= 0xffffffffffe00000ULL;
-		tmp <<= 2;
-		tmp += dumpaddr + sizeof(uint32_t);
-		debug("%s\t", mnem);
-		if (floating)
-			debug("f%i,", ra);
-		else
-			debug("%s,", alpha_regname[ra]);
-		debug("0x%" PRIx64, (uint64_t) tmp);
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    tmp, &offset);
-		if (symbol != NULL)
-			debug("\t<%s>", symbol);
-		debug("\n");
-		break;
-	default:debug("UNIMPLEMENTED opcode 0x%x\n", opcode);
-	}
-
-	return sizeof(uint32_t);
-}
-
-
-#define MEMORY_RW       alpha_userland_memory_rw
-#define MEM_ALPHA
-#define MEM_USERLAND
-#include "memory_rw.cc"
-#undef MEM_USERLAND
-#undef MEM_ALPHA
-#undef MEMORY_RW
-
-
-#include "tmp_alpha_tail.cc"
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_alpha_instr_alu.c gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_instr_alu.c
--- gxemul-0.6.2/src/cpus/cpu_alpha_instr_alu.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_instr_alu.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,357 @@
+/*
+ *  Copyright (C) 2005-2011  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Alpha ALU instructions.  (Included from tmp_alpha_misc.c.)
+ *
+ *
+ *  Most ALU instructions have the following arguments:
+ *  
+ *  arg[0] = pointer to destination uint64_t
+ *  arg[1] = pointer to source uint64_t nr 1
+ *  arg[2] = pointer to source uint64_t nr 2
+ *
+ *  or, if ALU_IMM is set, arg[2] contains an 8-bit immediate value.
+ *
+ *  The main function groups are:
+ *
+ *	ALU_INS				inserts
+ *	ALU_EXT				extracts
+ *	ALU_MSK				masks
+ *	ALU_CMOV			conditional moves
+ *	ALU_CMP				compares
+ *	ALU_CMPBGE			byte compare
+ *	none of the above		everything else (add, sub, ...)
+ */
+
+void ALU_N(struct cpu *cpu, struct alpha_instr_call *ic)
+{
+#ifdef ALU_INS
+
+	uint64_t x = *((uint64_t *)ic->arg[1]);
+	int r = (
+#ifdef ALU_IMM
+	    ic->arg[2]
+#else
+	    (*((uint64_t *)ic->arg[2]))
+#endif
+	    & 7) * 8;
+
+#ifdef ALU_B
+	x &= 0xff;
+#endif
+#ifdef ALU_W
+	x &= 0xffff;
+#endif
+#ifdef ALU_L
+	x &= 0xffffffffULL;
+#endif
+
+#ifdef ALU_LO
+	x <<= r;
+#else
+	r = 64 - r;
+	if (r == 64)
+		x = 0;
+	else
+		x >>= r;
+#endif
+	*((uint64_t *)ic->arg[0]) = x;
+
+#else	/*  ! INS  */
+
+#ifdef ALU_EXT
+
+	uint64_t x = *((uint64_t *)ic->arg[1]);
+	int r = (
+#ifdef ALU_IMM
+	    ic->arg[2]
+#else
+	    (*((uint64_t *)ic->arg[2]))
+#endif
+	    & 7) * 8;
+#ifdef ALU_LO
+	x >>= r;
+#else
+	r = 64 - r;
+	if (r != 64)
+		x <<= r;
+#endif
+#ifdef ALU_B
+	x &= 0xff;
+#endif
+#ifdef ALU_W
+	x &= 0xffff;
+#endif
+#ifdef ALU_L
+	x &= 0xffffffffULL;
+#endif
+	*((uint64_t *)ic->arg[0]) = x;
+
+#else	/*  ! EXT  */
+
+#ifdef ALU_MSK
+
+	uint64_t x = *((uint64_t *)ic->arg[1]);
+#ifdef ALU_B
+	uint64_t mask = 0x00000000000000ffULL;
+#endif
+#ifdef ALU_W
+	uint64_t mask = 0x000000000000ffffULL;
+#endif
+#ifdef ALU_L
+	uint64_t mask = 0x00000000ffffffffULL;
+#endif
+#ifdef ALU_Q
+	uint64_t mask = 0xffffffffffffffffULL;
+#endif
+	int r = (
+#ifdef ALU_IMM
+	    ic->arg[2]
+#else
+	    (*((uint64_t *)ic->arg[2]))
+#endif
+	    & 7) * 8;
+
+#ifdef ALU_LO
+	mask <<= r;
+#else
+	if (r == 0)
+		mask = 0;
+	else
+		mask >>= (64 - r);
+#endif
+
+	*((uint64_t *)ic->arg[0]) = x & ~mask;
+
+#else	/*  !MSK  */
+
+#ifdef ALU_CMOV
+
+	if (
+#ifdef ALU_CMOV_lbc
+	    !(
+#endif
+	    (*((int64_t *)ic->arg[1]))
+#ifdef ALU_CMOV_eq
+	    == 0
+#endif
+#ifdef ALU_CMOV_ne
+	    != 0
+#endif
+#ifdef ALU_CMOV_le
+	    <= 0
+#endif
+#ifdef ALU_CMOV_lt
+	    < 0
+#endif
+#ifdef ALU_CMOV_ge
+	    >= 0
+#endif
+#ifdef ALU_CMOV_gt
+	    > 0
+#endif
+#ifdef ALU_CMOV_lbs
+	    & 1
+#endif
+#ifdef ALU_CMOV_lbc
+	    & 1)
+#endif
+	    )
+		*((uint64_t *)ic->arg[0]) =
+#ifdef ALU_IMM
+		    (uint64_t)ic->arg[2]
+#else
+		    (*((uint64_t *)ic->arg[2]))
+#endif
+		    ;
+
+#else	/*  ! CMOV  */
+
+#ifdef ALU_CMPBGE
+
+	uint64_t ra = *((uint64_t *)ic->arg[1]), rc = 0, rb =
+#ifdef ALU_IMM
+		    (uint64_t)ic->arg[2]
+#else
+		    (*((uint64_t *)ic->arg[2]))
+#endif
+		    ;
+	int i;
+	for (i=7; i>=0; i--) {
+		if ((uint8_t)ra >= (uint8_t)rb)
+			rc |= (1 << i);
+		rb >>= 8; ra >>= 8;
+	}
+
+	*((uint64_t *)ic->arg[0]) = rc;
+
+#else	/*  ! CMPBGE  */
+
+#ifdef ALU_CMP
+
+	uint64_t x;
+
+	x = (*((
+#ifdef ALU_UNSIGNED
+	    uint64_t
+#else
+	    int64_t
+#endif
+	    *)ic->arg[1]))
+
+#ifdef ALU_CMP_EQ
+	    ==
+#endif
+#ifdef ALU_CMP_LE
+	    <=
+#endif
+#ifdef ALU_CMP_LT
+	    <
+#endif
+
+#ifdef ALU_IMM
+#ifdef ALU_UNSIGNED
+	    (uint64_t)ic->arg[2]
+#else
+	    (int64_t)ic->arg[2]
+#endif
+#else
+#ifdef ALU_UNSIGNED
+	    (*((uint64_t *)ic->arg[2]))
+#else
+	    (*((int64_t *)ic->arg[2]))
+#endif
+#endif
+	    ;
+
+#else	/*  !ALU_CMP  */
+
+#ifdef ALU_LONG
+	/*  Long  */
+	int32_t x;
+#else
+	/*  Quad  */
+	int64_t x;
+#endif
+
+#ifdef ALU_ZAP
+	/*  Prepare for zapping:  */
+	uint64_t zapmask = 0xffffffffffffffffULL;
+	int zapbytes =
+#ifdef ALU_NOT
+	    ~
+#endif
+#ifdef ALU_IMM
+	    (int64_t)ic->arg[2]
+#else
+	    (*((uint64_t *)ic->arg[2]))
+#endif
+	    ;
+	if (zapbytes & 0x80)
+		zapmask &= ~0xff00000000000000ULL;
+	if (zapbytes & 0x40)
+		zapmask &= ~0xff000000000000ULL;
+	if (zapbytes & 0x20)
+		zapmask &= ~0xff0000000000ULL;
+	if (zapbytes & 0x10)
+		zapmask &= ~0xff00000000ULL;
+	if (zapbytes & 0x08)
+		zapmask &= ~0xff000000ULL;
+	if (zapbytes & 0x04)
+		zapmask &= ~0xff0000ULL;
+	if (zapbytes & 0x02)
+		zapmask &= ~0xff00ULL;
+	if (zapbytes & 0x01)
+		zapmask &= ~0xffULL;
+#endif	/*  ZAP  */
+
+	x = (
+#ifdef ALU_SRA
+	    (int64_t)
+#endif
+	    (*((uint64_t *)ic->arg[1]))
+#ifdef ALU_S4
+	    * 4
+#endif
+#ifdef ALU_S8
+	    * 8
+#endif
+	    )
+#ifdef ALU_ADD
+	    +
+#endif
+#ifdef ALU_SUB
+	    -
+#endif
+#ifdef ALU_OR
+	    |
+#endif
+#ifdef ALU_XOR
+	    ^
+#endif
+#ifdef ALU_AND
+	    &
+#endif
+#ifdef ALU_SLL
+	    <<
+#endif
+#if defined(ALU_SRA) || defined(ALU_SRL)
+	    >>
+#endif
+
+#ifdef ALU_ZAP
+	    & zapmask
+#else	/*  !ZAP  */
+	    (
+#ifdef ALU_NOT
+	    ~
+#endif
+	    (
+#ifdef ALU_IMM
+	    (int64_t)ic->arg[2]
+#else
+	    (*((uint64_t *)ic->arg[2]))
+#endif
+#if defined(ALU_SRA) || defined(ALU_SRL) || defined(ALU_SLL)
+	    & 63
+#endif
+	    )
+	    )
+#endif	/*  !ZAP  */
+
+	    ;
+
+#endif	/*  !ALU_CMP  */
+
+	*((uint64_t *)ic->arg[0]) = x;
+#endif	/*  ! CMPBGE  */
+#endif	/*  ! CMOV  */
+#endif	/*  ! MSK  */
+#endif	/*  ! EXT  */
+#endif	/*  ! INS  */
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_alpha_instr_alu.cc gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_instr_alu.cc
--- gxemul-0.6.2/src/cpus/cpu_alpha_instr_alu.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_instr_alu.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,357 +0,0 @@
-/*
- *  Copyright (C) 2005-2011  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Alpha ALU instructions.  (Included from tmp_alpha_misc.c.)
- *
- *
- *  Most ALU instructions have the following arguments:
- *  
- *  arg[0] = pointer to destination uint64_t
- *  arg[1] = pointer to source uint64_t nr 1
- *  arg[2] = pointer to source uint64_t nr 2
- *
- *  or, if ALU_IMM is set, arg[2] contains an 8-bit immediate value.
- *
- *  The main function groups are:
- *
- *	ALU_INS				inserts
- *	ALU_EXT				extracts
- *	ALU_MSK				masks
- *	ALU_CMOV			conditional moves
- *	ALU_CMP				compares
- *	ALU_CMPBGE			byte compare
- *	none of the above		everything else (add, sub, ...)
- */
-
-void ALU_N(struct cpu *cpu, struct alpha_instr_call *ic)
-{
-#ifdef ALU_INS
-
-	uint64_t x = *((uint64_t *)ic->arg[1]);
-	int r = (
-#ifdef ALU_IMM
-	    ic->arg[2]
-#else
-	    (*((uint64_t *)ic->arg[2]))
-#endif
-	    & 7) * 8;
-
-#ifdef ALU_B
-	x &= 0xff;
-#endif
-#ifdef ALU_W
-	x &= 0xffff;
-#endif
-#ifdef ALU_L
-	x &= 0xffffffffULL;
-#endif
-
-#ifdef ALU_LO
-	x <<= r;
-#else
-	r = 64 - r;
-	if (r == 64)
-		x = 0;
-	else
-		x >>= r;
-#endif
-	*((uint64_t *)ic->arg[0]) = x;
-
-#else	/*  ! INS  */
-
-#ifdef ALU_EXT
-
-	uint64_t x = *((uint64_t *)ic->arg[1]);
-	int r = (
-#ifdef ALU_IMM
-	    ic->arg[2]
-#else
-	    (*((uint64_t *)ic->arg[2]))
-#endif
-	    & 7) * 8;
-#ifdef ALU_LO
-	x >>= r;
-#else
-	r = 64 - r;
-	if (r != 64)
-		x <<= r;
-#endif
-#ifdef ALU_B
-	x &= 0xff;
-#endif
-#ifdef ALU_W
-	x &= 0xffff;
-#endif
-#ifdef ALU_L
-	x &= 0xffffffffULL;
-#endif
-	*((uint64_t *)ic->arg[0]) = x;
-
-#else	/*  ! EXT  */
-
-#ifdef ALU_MSK
-
-	uint64_t x = *((uint64_t *)ic->arg[1]);
-#ifdef ALU_B
-	uint64_t mask = 0x00000000000000ffULL;
-#endif
-#ifdef ALU_W
-	uint64_t mask = 0x000000000000ffffULL;
-#endif
-#ifdef ALU_L
-	uint64_t mask = 0x00000000ffffffffULL;
-#endif
-#ifdef ALU_Q
-	uint64_t mask = 0xffffffffffffffffULL;
-#endif
-	int r = (
-#ifdef ALU_IMM
-	    ic->arg[2]
-#else
-	    (*((uint64_t *)ic->arg[2]))
-#endif
-	    & 7) * 8;
-
-#ifdef ALU_LO
-	mask <<= r;
-#else
-	if (r == 0)
-		mask = 0;
-	else
-		mask >>= (64 - r);
-#endif
-
-	*((uint64_t *)ic->arg[0]) = x & ~mask;
-
-#else	/*  !MSK  */
-
-#ifdef ALU_CMOV
-
-	if (
-#ifdef ALU_CMOV_lbc
-	    !(
-#endif
-	    (*((int64_t *)ic->arg[1]))
-#ifdef ALU_CMOV_eq
-	    == 0
-#endif
-#ifdef ALU_CMOV_ne
-	    != 0
-#endif
-#ifdef ALU_CMOV_le
-	    <= 0
-#endif
-#ifdef ALU_CMOV_lt
-	    < 0
-#endif
-#ifdef ALU_CMOV_ge
-	    >= 0
-#endif
-#ifdef ALU_CMOV_gt
-	    > 0
-#endif
-#ifdef ALU_CMOV_lbs
-	    & 1
-#endif
-#ifdef ALU_CMOV_lbc
-	    & 1)
-#endif
-	    )
-		*((uint64_t *)ic->arg[0]) =
-#ifdef ALU_IMM
-		    (uint64_t)ic->arg[2]
-#else
-		    (*((uint64_t *)ic->arg[2]))
-#endif
-		    ;
-
-#else	/*  ! CMOV  */
-
-#ifdef ALU_CMPBGE
-
-	uint64_t ra = *((uint64_t *)ic->arg[1]), rc = 0, rb =
-#ifdef ALU_IMM
-		    (uint64_t)ic->arg[2]
-#else
-		    (*((uint64_t *)ic->arg[2]))
-#endif
-		    ;
-	int i;
-	for (i=7; i>=0; i--) {
-		if ((uint8_t)ra >= (uint8_t)rb)
-			rc |= (1 << i);
-		rb >>= 8; ra >>= 8;
-	}
-
-	*((uint64_t *)ic->arg[0]) = rc;
-
-#else	/*  ! CMPBGE  */
-
-#ifdef ALU_CMP
-
-	uint64_t x;
-
-	x = (*((
-#ifdef ALU_UNSIGNED
-	    uint64_t
-#else
-	    int64_t
-#endif
-	    *)ic->arg[1]))
-
-#ifdef ALU_CMP_EQ
-	    ==
-#endif
-#ifdef ALU_CMP_LE
-	    <=
-#endif
-#ifdef ALU_CMP_LT
-	    <
-#endif
-
-#ifdef ALU_IMM
-#ifdef ALU_UNSIGNED
-	    (uint64_t)ic->arg[2]
-#else
-	    (int64_t)ic->arg[2]
-#endif
-#else
-#ifdef ALU_UNSIGNED
-	    (*((uint64_t *)ic->arg[2]))
-#else
-	    (*((int64_t *)ic->arg[2]))
-#endif
-#endif
-	    ;
-
-#else	/*  !ALU_CMP  */
-
-#ifdef ALU_LONG
-	/*  Long  */
-	int32_t x;
-#else
-	/*  Quad  */
-	int64_t x;
-#endif
-
-#ifdef ALU_ZAP
-	/*  Prepare for zapping:  */
-	uint64_t zapmask = 0xffffffffffffffffULL;
-	int zapbytes =
-#ifdef ALU_NOT
-	    ~
-#endif
-#ifdef ALU_IMM
-	    (int64_t)ic->arg[2]
-#else
-	    (*((uint64_t *)ic->arg[2]))
-#endif
-	    ;
-	if (zapbytes & 0x80)
-		zapmask &= ~0xff00000000000000ULL;
-	if (zapbytes & 0x40)
-		zapmask &= ~0xff000000000000ULL;
-	if (zapbytes & 0x20)
-		zapmask &= ~0xff0000000000ULL;
-	if (zapbytes & 0x10)
-		zapmask &= ~0xff00000000ULL;
-	if (zapbytes & 0x08)
-		zapmask &= ~0xff000000ULL;
-	if (zapbytes & 0x04)
-		zapmask &= ~0xff0000ULL;
-	if (zapbytes & 0x02)
-		zapmask &= ~0xff00ULL;
-	if (zapbytes & 0x01)
-		zapmask &= ~0xffULL;
-#endif	/*  ZAP  */
-
-	x = (
-#ifdef ALU_SRA
-	    (int64_t)
-#endif
-	    (*((uint64_t *)ic->arg[1]))
-#ifdef ALU_S4
-	    * 4
-#endif
-#ifdef ALU_S8
-	    * 8
-#endif
-	    )
-#ifdef ALU_ADD
-	    +
-#endif
-#ifdef ALU_SUB
-	    -
-#endif
-#ifdef ALU_OR
-	    |
-#endif
-#ifdef ALU_XOR
-	    ^
-#endif
-#ifdef ALU_AND
-	    &
-#endif
-#ifdef ALU_SLL
-	    <<
-#endif
-#if defined(ALU_SRA) || defined(ALU_SRL)
-	    >>
-#endif
-
-#ifdef ALU_ZAP
-	    & zapmask
-#else	/*  !ZAP  */
-	    (
-#ifdef ALU_NOT
-	    ~
-#endif
-	    (
-#ifdef ALU_IMM
-	    (int64_t)ic->arg[2]
-#else
-	    (*((uint64_t *)ic->arg[2]))
-#endif
-#if defined(ALU_SRA) || defined(ALU_SRL) || defined(ALU_SLL)
-	    & 63
-#endif
-	    )
-	    )
-#endif	/*  !ZAP  */
-
-	    ;
-
-#endif	/*  !ALU_CMP  */
-
-	*((uint64_t *)ic->arg[0]) = x;
-#endif	/*  ! CMPBGE  */
-#endif	/*  ! CMOV  */
-#endif	/*  ! MSK  */
-#endif	/*  ! EXT  */
-#endif	/*  ! INS  */
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_alpha_instr.c gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_instr.c
--- gxemul-0.6.2/src/cpus/cpu_alpha_instr.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_instr.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1290 @@
+/*
+ *  Copyright (C) 2005-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Alpha instructions.
+ *
+ *  Individual functions should keep track of cpu->n_translated_instrs.
+ *  (If no instruction was executed, then it should be decreased. If, say, 4
+ *  instructions were combined into one function and executed, then it should
+ *  be increased by 3.)
+ */
+
+
+#include "float_emul.h"
+
+
+/*
+ *  nop:  Do nothing.
+ */
+X(nop)
+{
+}
+
+
+/*
+ *  call_pal:  PALcode call
+ *
+ *  arg[0] = pal nr
+ */
+X(call_pal)
+{
+	/*  Synchronize PC first:  */
+	uint64_t old_pc, low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
+	cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1) <<
+	    ALPHA_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
+	old_pc = cpu->pc;
+
+	alpha_palcode(cpu, ic->arg[0]);
+
+	if (!cpu->running) {
+		cpu->n_translated_instrs --;
+		cpu->cd.alpha.next_ic = &nothing_call;
+	} else if (cpu->pc != old_pc) {
+		/*  The PC value was changed by the palcode call.  */
+		/*  Find the new physical page and update the translation
+		    pointers:  */
+		alpha_pc_to_pointers(cpu);
+	}
+}
+
+
+/*
+ *  jsr:  Jump to SubRoutine
+ *
+ *  arg[0] = ptr to uint64_t where to store return PC
+ *  arg[1] = ptr to uint64_t of new PC
+ */
+X(jsr)
+{
+	uint64_t old_pc = cpu->pc, low_pc;
+	uint64_t mask_within_page = ((ALPHA_IC_ENTRIES_PER_PAGE-1)
+	    << ALPHA_INSTR_ALIGNMENT_SHIFT) |
+	    ((1 << ALPHA_INSTR_ALIGNMENT_SHIFT) - 1);
+
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
+	cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
+	    << ALPHA_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT) + 4;
+
+	*((int64_t *)ic->arg[0]) = cpu->pc;
+	cpu->pc = *((int64_t *)ic->arg[1]);
+
+	/*
+	 *  If this is a jump/return into the same code page as we were
+	 *  already in, then just set cpu->cd.alpha.next_ic.
+	 */
+	if ((old_pc & ~mask_within_page) == (cpu->pc & ~mask_within_page)) {
+		cpu->cd.alpha.next_ic = cpu->cd.alpha.cur_ic_page +
+		    ((cpu->pc & mask_within_page) >> 2);
+	} else {
+		/*  Find the new physical page and update pointers:  */
+		alpha_pc_to_pointers(cpu);
+	}
+}
+
+
+/*
+ *  jsr_trace:  Jump to SubRoutine (with function call trace enabled)
+ *
+ *  Arguments same as for jsr.
+ */
+X(jsr_trace)
+{
+	cpu_functioncall_trace(cpu, *((int64_t *)ic->arg[1]));
+	instr(jsr)(cpu, ic);
+}
+
+
+/*
+ *  jsr_0:  JSR/RET, don't store return PC.
+ *
+ *  arg[0] = ignored
+ *  arg[1] = ptr to uint64_t of new PC
+ */
+X(jsr_0)
+{
+	uint64_t old_pc = cpu->pc;
+	uint64_t mask_within_page = ((ALPHA_IC_ENTRIES_PER_PAGE-1)
+	    << ALPHA_INSTR_ALIGNMENT_SHIFT)
+	    | ((1 << ALPHA_INSTR_ALIGNMENT_SHIFT) - 1);
+
+	cpu->pc = *((int64_t *)ic->arg[1]);
+
+	/*
+	 *  If this is a jump/return into the same code page as we were
+	 *  already in, then just set cpu->cd.alpha.next_ic.
+	 */
+	if ((old_pc & ~mask_within_page) == (cpu->pc & ~mask_within_page)) {
+		cpu->cd.alpha.next_ic = cpu->cd.alpha.cur_ic_page +
+		    ((cpu->pc & mask_within_page) >> 2);
+	} else {
+		/*  Find the new physical page and update pointers:  */
+		alpha_pc_to_pointers(cpu);
+	}
+}
+
+
+/*
+ *  jsr_0_trace:  JSR/RET (with function call trace enabled)
+ *
+ *  Arguments same as for jsr_0.
+ */
+X(jsr_0_trace)
+{
+	cpu_functioncall_trace_return(cpu);
+	instr(jsr_0)(cpu, ic);
+}
+
+
+/*
+ *  br:  Branch (to a different translated page)
+ *
+ *  arg[0] = relative offset (as an int32_t)
+ */
+X(br)
+{
+	uint64_t low_pc;
+
+	/*  Calculate new PC from this instruction + arg[0]  */
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
+	cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
+	    << ALPHA_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (int32_t)ic->arg[0];
+
+	/*  Find the new physical page and update the translation pointers:  */
+	alpha_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  br:  Branch (to a different translated page), write return address
+ *
+ *  arg[0] = relative offset (as an int32_t)
+ *  arg[1] = pointer to uint64_t where to write return address
+ */
+X(br_return)
+{
+	uint64_t low_pc;
+
+	/*  Calculate new PC from this instruction + arg[0]  */
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
+	cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
+	    << ALPHA_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
+
+	/*  ... but first, save away the return address:  */
+	*((int64_t *)ic->arg[1]) = cpu->pc + 4;
+
+	cpu->pc += (int32_t)ic->arg[0];
+
+	/*  Find the new physical page and update the translation pointers:  */
+	alpha_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  beq:  Branch (to a different translated page) if Equal
+ *
+ *  arg[0] = relative offset (as an int32_t)
+ *  arg[1] = pointer to int64_t register
+ */
+X(beq)
+{
+	if (*((int64_t *)ic->arg[1]) == 0)
+		instr(br)(cpu, ic);
+}
+
+
+/*
+ *  blbs:  Branch (to a different translated page) if Low Bit Set
+ *
+ *  arg[0] = relative offset (as an int32_t)
+ *  arg[1] = pointer to int64_t register
+ */
+X(blbs)
+{
+	if (*((int64_t *)ic->arg[1]) & 1)
+		instr(br)(cpu, ic);
+}
+
+
+/*
+ *  blbc:  Branch (to a different translated page) if Low Bit Clear
+ *
+ *  arg[0] = relative offset (as an int32_t)
+ *  arg[1] = pointer to int64_t register
+ */
+X(blbc)
+{
+	if (!(*((int64_t *)ic->arg[1]) & 1))
+		instr(br)(cpu, ic);
+}
+
+
+/*
+ *  bne:  Branch (to a different translated page) if Not Equal
+ *
+ *  arg[0] = relative offset (as an int32_t)
+ *  arg[1] = pointer to int64_t register
+ */
+X(bne)
+{
+	if (*((int64_t *)ic->arg[1]) != 0)
+		instr(br)(cpu, ic);
+}
+
+
+/*
+ *  ble:  Branch (to a different translated page) if Less or Equal
+ *
+ *  arg[0] = relative offset (as an int32_t)
+ *  arg[1] = pointer to int64_t register
+ */
+X(ble)
+{
+	if (*((int64_t *)ic->arg[1]) <= 0)
+		instr(br)(cpu, ic);
+}
+
+
+/*
+ *  blt:  Branch (to a different translated page) if Less Than
+ *
+ *  arg[0] = relative offset (as an int32_t)
+ *  arg[1] = pointer to int64_t register
+ */
+X(blt)
+{
+	if (*((int64_t *)ic->arg[1]) < 0)
+		instr(br)(cpu, ic);
+}
+
+
+/*
+ *  bge:  Branch (to a different translated page) if Greater or Equal
+ *
+ *  arg[0] = relative offset (as an int32_t)
+ *  arg[1] = pointer to int64_t register
+ */
+X(bge)
+{
+	if (*((int64_t *)ic->arg[1]) >= 0)
+		instr(br)(cpu, ic);
+}
+
+
+/*
+ *  bgt:  Branch (to a different translated page) if Greater Than
+ *
+ *  arg[0] = relative offset (as an int32_t)
+ *  arg[1] = pointer to int64_t register
+ */
+X(bgt)
+{
+	if (*((int64_t *)ic->arg[1]) > 0)
+		instr(br)(cpu, ic);
+}
+
+
+/*
+ *  br_samepage:  Branch (to within the same translated page)
+ *
+ *  arg[0] = pointer to new alpha_instr_call
+ */
+X(br_samepage)
+{
+	cpu->cd.alpha.next_ic = (struct alpha_instr_call *) ic->arg[0];
+}
+
+
+/*
+ *  br_return_samepage:  Branch (to within the same translated page),
+ *                       and save return address
+ *
+ *  arg[0] = pointer to new alpha_instr_call
+ *  arg[1] = pointer to uint64_t where to store return address
+ */
+X(br_return_samepage)
+{
+	uint64_t low_pc;
+
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
+	cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
+	    << ALPHA_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
+	*((int64_t *)ic->arg[1]) = cpu->pc + 4;
+
+	cpu->cd.alpha.next_ic = (struct alpha_instr_call *) ic->arg[0];
+}
+
+
+/*
+ *  beq_samepage:  Branch (to within the same translated page) if Equal
+ *
+ *  arg[0] = pointer to new alpha_instr_call
+ *  arg[1] = pointer to int64_t register
+ */
+X(beq_samepage)
+{
+	if (*((int64_t *)ic->arg[1]) == 0)
+		instr(br_samepage)(cpu, ic);
+}
+
+
+/*
+ *  blbs_samepage:  Branch (to within the same translated page) if Low Bit Set
+ *
+ *  arg[0] = pointer to new alpha_instr_call
+ *  arg[1] = pointer to int64_t register
+ */
+X(blbs_samepage)
+{
+	if (*((int64_t *)ic->arg[1]) & 1)
+		instr(br_samepage)(cpu, ic);
+}
+
+
+/*
+ *  blbc_samepage:  Branch (to within the same translated page) if Low Bit Clear
+ *
+ *  arg[0] = pointer to new alpha_instr_call
+ *  arg[1] = pointer to int64_t register
+ */
+X(blbc_samepage)
+{
+	if (!(*((int64_t *)ic->arg[1]) & 1))
+		instr(br_samepage)(cpu, ic);
+}
+
+
+/*
+ *  bne_samepage:  Branch (to within the same translated page) if Not Equal
+ *
+ *  arg[0] = pointer to new alpha_instr_call
+ *  arg[1] = pointer to int64_t register
+ */
+X(bne_samepage)
+{
+	if (*((int64_t *)ic->arg[1]) != 0)
+		instr(br_samepage)(cpu, ic);
+}
+
+
+/*
+ *  ble_samepage:  Branch (to within the same translated page) if Less or Equal
+ *
+ *  arg[0] = pointer to new alpha_instr_call
+ *  arg[1] = pointer to int64_t register
+ */
+X(ble_samepage)
+{
+	if (*((int64_t *)ic->arg[1]) <= 0)
+		instr(br_samepage)(cpu, ic);
+}
+
+
+/*
+ *  blt_samepage:  Branch (to within the same translated page) if Less Than
+ *
+ *  arg[0] = pointer to new alpha_instr_call
+ *  arg[1] = pointer to int64_t register
+ */
+X(blt_samepage)
+{
+	if (*((int64_t *)ic->arg[1]) < 0)
+		instr(br_samepage)(cpu, ic);
+}
+
+
+/*
+ *  bge_samepage:  Branch (to within the same translated page)
+ *		   if Greater or Equal
+ *
+ *  arg[0] = pointer to new alpha_instr_call
+ *  arg[1] = pointer to int64_t register
+ */
+X(bge_samepage)
+{
+	if (*((int64_t *)ic->arg[1]) >= 0)
+		instr(br_samepage)(cpu, ic);
+}
+
+
+/*
+ *  bgt_samepage:  Branch (to within the same translated page) if Greater Than
+ *
+ *  arg[0] = pointer to new alpha_instr_call
+ *  arg[1] = pointer to int64_t register
+ */
+X(bgt_samepage)
+{
+	if (*((int64_t *)ic->arg[1]) > 0)
+		instr(br_samepage)(cpu, ic);
+}
+
+
+/*
+ *  cvttq/c:  Convert floating point to quad.
+ *
+ *  arg[0] = pointer to rc  (destination integer)
+ *  arg[2] = pointer to rb  (source float)
+ */
+X(cvttq_c)
+{
+	struct ieee_float_value fb;
+	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
+	reg(ic->arg[0]) = fb.nan? 0 : fb.f;
+}
+
+
+/*
+ *  cvtqt:  Convert quad to floating point.
+ *
+ *  arg[0] = pointer to rc  (destination float)
+ *  arg[2] = pointer to rb  (source quad integer)
+ */
+X(cvtqt)
+{
+	reg(ic->arg[0]) = ieee_store_float_value(reg(ic->arg[2]), IEEE_FMT_D);
+}
+
+
+/*
+ *  fabs, fneg:  Floating point absolute value, or negation.
+ *
+ *  arg[0] = pointer to rc  (destination float)
+ *  arg[2] = pointer to rb  (source quad integer)
+ */
+X(fabs)
+{
+	reg(ic->arg[0]) = reg(ic->arg[2]) & 0x7fffffffffffffffULL;
+}
+X(fneg)
+{
+	reg(ic->arg[0]) = reg(ic->arg[2]) ^ 0x8000000000000000ULL;
+}
+
+
+/*
+ *  addt, subt, mult, divt:  Floating point arithmetic.
+ *
+ *  arg[0] = pointer to rc  (destination)
+ *  arg[1] = pointer to ra  (source)
+ *  arg[2] = pointer to rb  (source)
+ */
+X(addt)
+{
+	struct ieee_float_value fa, fb;
+	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
+	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
+	reg(ic->arg[0]) = ieee_store_float_value(fa.f + fb.f, IEEE_FMT_D);
+}
+X(subt)
+{
+	struct ieee_float_value fa, fb;
+	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
+	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
+	reg(ic->arg[0]) = ieee_store_float_value(fa.f - fb.f, IEEE_FMT_D);
+}
+X(mult)
+{
+	struct ieee_float_value fa, fb;
+	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
+	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
+	reg(ic->arg[0]) = ieee_store_float_value(fa.f * fb.f, IEEE_FMT_D);
+}
+X(divt)
+{
+	struct ieee_float_value fa, fb;
+	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
+	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
+	reg(ic->arg[0]) = ieee_store_float_value(fa.f / fb.f, IEEE_FMT_D);
+}
+X(cmpteq)
+{
+	struct ieee_float_value fa, fb;
+	int res = 0;
+	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
+	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
+	if (fa.nan | fb.nan)
+		res = 0;
+	else
+		res = fa.f == fb.f;
+	reg(ic->arg[0]) = res;
+}
+X(cmptlt)
+{
+	struct ieee_float_value fa, fb;
+	int res = 0;
+	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
+	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
+	if (fa.nan | fb.nan)
+		res = 0;
+	else
+		res = fa.f < fb.f;
+	reg(ic->arg[0]) = res;
+}
+X(cmptle)
+{
+	struct ieee_float_value fa, fb;
+	int res = 0;
+	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
+	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
+	if (fa.nan | fb.nan)
+		res = 0;
+	else
+		res = fa.f <= fb.f;
+	reg(ic->arg[0]) = res;
+}
+
+
+/*
+ *  implver:  Return CPU implver value.
+ *
+ *  arg[0] = pointer to destination uint64_t
+ */
+X(implver)
+{
+	reg(ic->arg[0]) = cpu->cd.alpha.cpu_type.implver;
+}
+
+
+/*
+ *  mull, mull_imm:  Signed Multiply 32x32 => 32.
+ *
+ *  arg[0] = pointer to destination uint64_t
+ *  arg[1] = pointer to source uint64_t
+ *  arg[2] = pointer to source uint64_t or immediate
+ */
+X(mull)
+{
+	int32_t a = reg(ic->arg[1]);
+	int32_t b = reg(ic->arg[2]);
+	reg(ic->arg[0]) = (int64_t)(int32_t)(a * b);
+}
+X(mull_imm)
+{
+	int32_t a = reg(ic->arg[1]);
+	int32_t b = ic->arg[2];
+	reg(ic->arg[0]) = (int64_t)(int32_t)(a * b);
+}
+
+
+/*
+ *  mulq, mulq_imm:  Unsigned Multiply 64x64 => 64.
+ *
+ *  arg[0] = pointer to destination uint64_t
+ *  arg[1] = pointer to source uint64_t
+ *  arg[2] = pointer to source uint64_t or immediate
+ */
+X(mulq)
+{
+	reg(ic->arg[0]) = reg(ic->arg[1]) * reg(ic->arg[2]);
+}
+X(mulq_imm)
+{
+	reg(ic->arg[0]) = reg(ic->arg[1]) * ic->arg[2];
+}
+
+
+/*
+ *  umulh:  Unsigned Multiply 64x64 => 128. Store high part in dest reg.
+ *
+ *  arg[0] = pointer to destination uint64_t
+ *  arg[1] = pointer to source uint64_t
+ *  arg[2] = pointer to source uint64_t
+ */
+X(umulh)
+{
+	uint64_t reshi = 0, reslo = 0;
+	uint64_t s1 = reg(ic->arg[1]), s2 = reg(ic->arg[2]);
+	int i, bit;
+
+	for (i=0; i<64; i++) {
+		bit = (s1 & 0x8000000000000000ULL)? 1 : 0;
+		s1 <<= 1;
+
+		/*  If bit in s1 set, then add s2 to reshi/lo:  */
+		if (bit) {
+			uint64_t old_reslo = reslo;
+			reslo += s2;
+			if (reslo < old_reslo)
+				reshi ++;
+		}
+
+		if (i != 63) {
+			reshi <<= 1;
+			reshi += (reslo & 0x8000000000000000ULL? 1 : 0);
+			reslo <<= 1;
+		}
+	}
+
+	reg(ic->arg[0]) = reshi;
+}
+
+
+/*
+ *  lda:  Load address.
+ *
+ *  arg[0] = pointer to destination uint64_t
+ *  arg[1] = pointer to source uint64_t
+ *  arg[2] = offset (possibly as an int32_t)
+ */
+X(lda)
+{
+	reg(ic->arg[0]) = reg(ic->arg[1]) + (int64_t)(int32_t)ic->arg[2];
+}
+
+
+/*
+ *  lda_0:  Load address compared to the zero register.
+ *
+ *  arg[0] = pointer to destination uint64_t
+ *  arg[1] = ignored
+ *  arg[2] = offset (possibly as an int32_t)
+ */
+X(lda_0)
+{
+	reg(ic->arg[0]) = (int64_t)(int32_t)ic->arg[2];
+}
+
+
+/*
+ *  clear:  Clear a 64-bit register.
+ *
+ *  arg[0] = pointer to destination uint64_t
+ */
+X(clear)
+{
+	reg(ic->arg[0]) = 0;
+}
+
+
+/*
+ *  rdcc:  Read the Cycle Counter into a 64-bit register.
+ *
+ *  arg[0] = pointer to destination uint64_t
+ */
+X(rdcc)
+{
+	reg(ic->arg[0]) = cpu->cd.alpha.pcc;
+
+	/*  TODO: actually keep the pcc updated!  */
+	cpu->cd.alpha.pcc += 20;
+}
+
+
+#include "tmp_alpha_misc.c"
+
+
+/*****************************************************************************/
+
+
+X(end_of_page)
+{
+	/*  Update the PC:  (offset 0, but on the next page)  */
+	cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
+	    << ALPHA_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (ALPHA_IC_ENTRIES_PER_PAGE
+	    << ALPHA_INSTR_ALIGNMENT_SHIFT);
+
+	/*  Find the new physical page and update the translation pointers:  */
+	alpha_pc_to_pointers(cpu);
+
+	/*  end_of_page doesn't count as an executed instruction:  */
+	cpu->n_translated_instrs --;
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  alpha_instr_to_be_translated():
+ *
+ *  Translate an instruction word into an alpha_instr_call. ic is filled in with
+ *  valid data for the translated instruction, or a "nothing" instruction if
+ *  there was a translation failure. The newly translated instruction is then
+ *  executed.
+ */
+X(to_be_translated)
+{
+	uint64_t addr, low_pc;
+	uint32_t iword;
+	unsigned char *page;
+	unsigned char ib[4];
+	void (*samepage_function)(struct cpu *, struct alpha_instr_call *);
+	int opcode, ra, rb, func, rc, imm, load, loadstore_type, fp, llsc;
+
+	/*  Figure out the (virtual) address of the instruction:  */
+	low_pc = ((size_t)ic - (size_t)cpu->cd.alpha.cur_ic_page)
+	    / sizeof(struct alpha_instr_call);
+	addr = cpu->pc & ~((ALPHA_IC_ENTRIES_PER_PAGE-1) <<
+	    ALPHA_INSTR_ALIGNMENT_SHIFT);
+	addr += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
+	addr &= ~((1 << ALPHA_INSTR_ALIGNMENT_SHIFT) - 1);
+	cpu->pc = addr;
+
+	/*  Read the instruction word from memory:  */
+	{
+		const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+		const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+		const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+		uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
+		uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+		uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
+		    DYNTRANS_L3N)) & mask3;
+		struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.alpha.l1_64[x1];
+		struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
+		page = l3->host_load[x3];
+	}
+
+	if (page != NULL) {
+		/*  fatal("TRANSLATION HIT!\n");  */
+		memcpy(ib, page + (addr & 8191), sizeof(ib));
+	} else {
+		/*  fatal("TRANSLATION MISS!\n");  */
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, &ib[0],
+		    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
+			fatal("to_be_translated(): read failed: TODO\n");
+			goto bad;
+		}
+	}
+
+	/*  Alpha instruction words are always little-endian. Convert
+	    to host order:  */
+	{
+		uint32_t *p = (uint32_t *) ib;
+		iword = LE32_TO_HOST( *p );
+	}
+
+#define DYNTRANS_TO_BE_TRANSLATED_HEAD
+#include "cpu_dyntrans.c"
+#undef	DYNTRANS_TO_BE_TRANSLATED_HEAD
+
+
+	opcode = (iword >> 26) & 63;
+	ra = (iword >> 21) & 31;
+	rb = (iword >> 16) & 31;
+	func = (iword >> 5) & 0x7ff;
+	rc = iword & 31;
+	imm = iword & 0xffff;
+
+	switch (opcode) {
+	case 0x00:						/*  CALL_PAL  */
+		ic->f = instr(call_pal);
+		ic->arg[0] = (size_t) (iword & 0x3ffffff);
+		break;
+	case 0x08:						/*  LDA  */
+	case 0x09:						/*  LDAH  */
+		if (ra == ALPHA_ZERO) {
+			ic->f = instr(nop);
+			break;
+		}
+		/*  TODO: A special case which is common is to add or subtract
+		    a small offset from sp.  */
+		ic->f = instr(lda);
+		ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
+		ic->arg[1] = (size_t) &cpu->cd.alpha.r[rb];
+		if (rb == ALPHA_ZERO)
+			ic->f = instr(lda_0);
+		ic->arg[2] = (ssize_t)(int16_t)imm;
+		if (opcode == 0x09)
+			ic->arg[2] <<= 16;
+		break;
+	case 0x0b:						/*  LDQ_U  */
+	case 0x0f:						/*  STQ_U  */
+		if (ra == ALPHA_ZERO && opcode == 0x0b) {
+			ic->f = instr(nop);
+			break;
+		}
+		if (opcode == 0x0b)
+			ic->f = instr(ldq_u);
+		else
+			ic->f = instr(stq_u);
+		ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
+		ic->arg[1] = (size_t) &cpu->cd.alpha.r[rb];
+		ic->arg[2] = (ssize_t)(int16_t)imm;
+		break;
+	case 0x0a:
+	case 0x0c:
+	case 0x0d:
+	case 0x0e:
+	case 0x22:
+	case 0x23:
+	case 0x26:
+	case 0x27:
+	case 0x28:
+	case 0x29:
+	case 0x2a:
+	case 0x2b:
+	case 0x2c:
+	case 0x2d:
+	case 0x2e:
+	case 0x2f:
+		loadstore_type = 0; fp = 0; load = 0; llsc = 0;
+		switch (opcode) {
+		case 0x0a: loadstore_type = 0; load = 1; break;	/*  ldbu  */
+		case 0x0c: loadstore_type = 1; load = 1; break;	/*  ldwu  */
+		case 0x0d: loadstore_type = 1; break;		/*  stw  */
+		case 0x0e: loadstore_type = 0; break;		/*  stb  */
+		case 0x22: loadstore_type = 2; load = 1; fp = 1; break; /*lds*/
+		case 0x23: loadstore_type = 3; load = 1; fp = 1; break; /*ldt*/
+		case 0x26: loadstore_type = 2; fp = 1; break;	/*  sts  */
+		case 0x27: loadstore_type = 3; fp = 1; break;	/*  stt  */
+		case 0x28: loadstore_type = 2; load = 1; break;	/*  ldl  */
+		case 0x29: loadstore_type = 3; load = 1; break;	/*  ldq  */
+		case 0x2a: loadstore_type = 2; load = llsc = 1; break;/* ldl_l*/
+		case 0x2b: loadstore_type = 3; load = llsc = 1; break;/* ldq_l*/
+		case 0x2c: loadstore_type = 2; break;		/*  stl  */
+		case 0x2d: loadstore_type = 3; break;		/*  stq  */
+		case 0x2e: loadstore_type = 2; llsc = 1; break;	/*  stl_c  */
+		case 0x2f: loadstore_type = 3; llsc = 1; break;	/*  stq_c  */
+		}
+		ic->f = alpha_loadstore[
+		    loadstore_type + (imm==0? 4 : 0) + 8 * load
+		    + 16 * llsc];
+		/*  Load to the zero register is treated as a prefetch
+		    hint. It is ignored here.  */
+		if (load && ra == ALPHA_ZERO) {
+			ic->f = instr(nop);
+			break;
+		}
+		if (fp)
+			ic->arg[0] = (size_t) &cpu->cd.alpha.f[ra];
+		else
+			ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
+		ic->arg[1] = (size_t) &cpu->cd.alpha.r[rb];
+		ic->arg[2] = (ssize_t)(int16_t)imm;
+		break;
+	case 0x10:
+		if (rc == ALPHA_ZERO) {
+			ic->f = instr(nop);
+			break;
+		}
+		ic->arg[0] = (size_t) &cpu->cd.alpha.r[rc];
+		ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
+		if (func & 0x80)
+			ic->arg[2] = (size_t)((rb << 3) + (func >> 8));
+		else
+			ic->arg[2] = (size_t) &cpu->cd.alpha.r[rb];
+		switch (func & 0xff) {
+		case 0x00: ic->f = instr(addl); break;
+		case 0x02: ic->f = instr(s4addl); break;
+		case 0x09: ic->f = instr(subl); break;
+		case 0x0b: ic->f = instr(s4subl); break;
+		case 0x0f: ic->f = instr(cmpbge); break;
+		case 0x12: ic->f = instr(s8addl); break;
+		case 0x1b: ic->f = instr(s8subl); break;
+		case 0x1d: ic->f = instr(cmpult); break;
+		case 0x20: ic->f = instr(addq); break;
+		case 0x22: ic->f = instr(s4addq); break;
+		case 0x29: ic->f = instr(subq); break;
+		case 0x2b: ic->f = instr(s4subq); break;
+		case 0x2d: ic->f = instr(cmpeq); break;
+		case 0x32: ic->f = instr(s8addq); break;
+		case 0x3b: ic->f = instr(s8subq); break;
+		case 0x3d: ic->f = instr(cmpule); break;
+		case 0x4d: ic->f = instr(cmplt); break;
+		// case 0x69: ic->f = instr(subq_v); break;
+		case 0x6d: ic->f = instr(cmple); break;
+
+		case 0x80: ic->f = instr(addl_imm); break;
+		case 0x82: ic->f = instr(s4addl_imm); break;
+		case 0x89: ic->f = instr(subl_imm); break;
+		case 0x8b: ic->f = instr(s4subl_imm); break;
+		case 0x8f: ic->f = instr(cmpbge_imm); break;
+		case 0x92: ic->f = instr(s8addl_imm); break;
+		case 0x9b: ic->f = instr(s8subl_imm); break;
+		case 0x9d: ic->f = instr(cmpult_imm); break;
+		case 0xa0: ic->f = instr(addq_imm); break;
+		case 0xa2: ic->f = instr(s4addq_imm); break;
+		case 0xa9: ic->f = instr(subq_imm); break;
+		case 0xab: ic->f = instr(s4subq_imm); break;
+		case 0xad: ic->f = instr(cmpeq_imm); break;
+		case 0xb2: ic->f = instr(s8addq_imm); break;
+		case 0xbb: ic->f = instr(s8subq_imm); break;
+		case 0xbd: ic->f = instr(cmpule_imm); break;
+		case 0xcd: ic->f = instr(cmplt_imm); break;
+		case 0xed: ic->f = instr(cmple_imm); break;
+
+		default:if (!cpu->translation_readahead)
+				fatal("[ Alpha: unimplemented function 0x%03x "
+				    "for opcode 0x%02x ]\n", func, opcode);
+			goto bad;
+		}
+		break;
+	case 0x11:
+		if (rc == ALPHA_ZERO) {
+			ic->f = instr(nop);
+			break;
+		}
+		ic->arg[0] = (size_t) &cpu->cd.alpha.r[rc];
+		ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
+		if (func & 0x80)
+			ic->arg[2] = (size_t)((rb << 3) + (func >> 8));
+		else
+			ic->arg[2] = (size_t) &cpu->cd.alpha.r[rb];
+		switch (func & 0xff) {
+		case 0x00: ic->f = instr(and); break;
+		case 0x08: ic->f = instr(andnot); break;
+		case 0x14: ic->f = instr(cmovlbs); break;
+		case 0x16: ic->f = instr(cmovlbc); break;
+		case 0x20: ic->f = instr(or);
+			   if (ra == ALPHA_ZERO || rb == ALPHA_ZERO) {
+				if (ra == ALPHA_ZERO)
+					ra = rb;
+				ic->f = alpha_mov_r_r[ra + rc*32];
+			   }
+			   break;
+		case 0x24: ic->f = instr(cmoveq); break;
+		case 0x26: ic->f = instr(cmovne); break;
+		case 0x28: ic->f = instr(ornot); break;
+		case 0x40: ic->f = instr(xor); break;
+		case 0x44: ic->f = instr(cmovlt); break;
+		case 0x46: ic->f = instr(cmovge); break;
+		case 0x48: ic->f = instr(xornot); break;
+		case 0x64: ic->f = instr(cmovle); break;
+		case 0x66: ic->f = instr(cmovgt); break;
+		case 0x80: ic->f = instr(and_imm); break;
+		case 0x88: ic->f = instr(andnot_imm); break;
+		case 0x94: ic->f = instr(cmovlbs_imm); break;
+		case 0x96: ic->f = instr(cmovlbc_imm); break;
+		case 0xa0: ic->f = instr(or_imm); break;
+		case 0xa4: ic->f = instr(cmoveq_imm); break;
+		case 0xa6: ic->f = instr(cmovne_imm); break;
+		case 0xa8: ic->f = instr(ornot_imm); break;
+		case 0xc0: ic->f = instr(xor_imm); break;
+		case 0xc4: ic->f = instr(cmovlt_imm); break;
+		case 0xc6: ic->f = instr(cmovge_imm); break;
+		case 0xc8: ic->f = instr(xornot_imm); break;
+		case 0xe4: ic->f = instr(cmovle_imm); break;
+		case 0xe6: ic->f = instr(cmovgt_imm); break;
+		case 0xec: ic->f = instr(implver); break;
+		default:if (!cpu->translation_readahead)
+				fatal("[ Alpha: unimplemented function 0x%03x "
+				    "for opcode 0x%02x ]\n", func, opcode);
+			goto bad;
+		}
+		break;
+	case 0x12:
+		if (rc == ALPHA_ZERO) {
+			ic->f = instr(nop);
+			break;
+		}
+		ic->arg[0] = (size_t) &cpu->cd.alpha.r[rc];
+		ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
+		if (func & 0x80)
+			ic->arg[2] = (size_t)((rb << 3) + (func >> 8));
+		else
+			ic->arg[2] = (size_t) &cpu->cd.alpha.r[rb];
+		switch (func & 0xff) {
+		case 0x02: ic->f = instr(mskbl); break;
+		case 0x06: ic->f = instr(extbl); break;
+		case 0x0b: ic->f = instr(insbl); break;
+		case 0x12: ic->f = instr(mskwl); break;
+		case 0x16: ic->f = instr(extwl); break;
+		case 0x1b: ic->f = instr(inswl); break;
+		case 0x22: ic->f = instr(mskll); break;
+		case 0x26: ic->f = instr(extll); break;
+		case 0x2b: ic->f = instr(insll); break;
+		case 0x30: ic->f = instr(zap); break;
+		case 0x31: ic->f = instr(zapnot); break;
+		case 0x32: ic->f = instr(mskql); break;
+		case 0x34: ic->f = instr(srl); break;
+		case 0x36: ic->f = instr(extql); break;
+		case 0x39: ic->f = instr(sll); break;
+		case 0x3b: ic->f = instr(insql); break;
+		case 0x3c: ic->f = instr(sra); break;
+		case 0x52: ic->f = instr(mskwh); break;
+		case 0x57: ic->f = instr(inswh); break;
+		case 0x5a: ic->f = instr(extwh); break;
+		case 0x62: ic->f = instr(msklh); break;
+		case 0x67: ic->f = instr(inslh); break;
+		case 0x6a: ic->f = instr(extlh); break;
+		case 0x72: ic->f = instr(mskqh); break;
+		case 0x77: ic->f = instr(insqh); break;
+		case 0x7a: ic->f = instr(extqh); break;
+		case 0x82: ic->f = instr(mskbl_imm); break;
+		case 0x86: ic->f = instr(extbl_imm); break;
+		case 0x8b: ic->f = instr(insbl_imm); break;
+		case 0x92: ic->f = instr(mskwl_imm); break;
+		case 0x96: ic->f = instr(extwl_imm); break;
+		case 0x9b: ic->f = instr(inswl_imm); break;
+		case 0xa2: ic->f = instr(mskll_imm); break;
+		case 0xa6: ic->f = instr(extll_imm); break;
+		case 0xab: ic->f = instr(insll_imm); break;
+		case 0xb0: ic->f = instr(zap_imm); break;
+		case 0xb1: ic->f = instr(zapnot_imm); break;
+		case 0xb2: ic->f = instr(mskql_imm); break;
+		case 0xb4: ic->f = instr(srl_imm); break;
+		case 0xb6: ic->f = instr(extql_imm); break;
+		case 0xb9: ic->f = instr(sll_imm); break;
+		case 0xbb: ic->f = instr(insql_imm); break;
+		case 0xbc: ic->f = instr(sra_imm); break;
+		case 0xd2: ic->f = instr(mskwh_imm); break;
+		case 0xd7: ic->f = instr(inswh_imm); break;
+		case 0xda: ic->f = instr(extwh_imm); break;
+		case 0xe2: ic->f = instr(msklh_imm); break;
+		case 0xe7: ic->f = instr(inslh_imm); break;
+		case 0xea: ic->f = instr(extlh_imm); break;
+		case 0xf2: ic->f = instr(mskqh_imm); break;
+		case 0xf7: ic->f = instr(insqh_imm); break;
+		case 0xfa: ic->f = instr(extqh_imm); break;
+		default:if (!cpu->translation_readahead)
+				fatal("[ Alpha: unimplemented function 0x%03x "
+				    "for opcode 0x%02x ]\n", func, opcode);
+			goto bad;
+		}
+		break;
+	case 0x13:
+		if (rc == ALPHA_ZERO) {
+			ic->f = instr(nop);
+			break;
+		}
+		ic->arg[0] = (size_t) &cpu->cd.alpha.r[rc];
+		ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
+		if (func & 0x80)
+			ic->arg[2] = (size_t)((rb << 3) + (func >> 8));
+		else
+			ic->arg[2] = (size_t) &cpu->cd.alpha.r[rb];
+		// TODO: mulq/v etc? overflow detection
+		// bit 0..6 are function, but 7 is "imm" bit.
+		switch (func & 0xff) {
+		case 0x00: ic->f = instr(mull); break;
+		case 0x20: ic->f = instr(mulq); break;
+		case 0x30: ic->f = instr(umulh); break;
+		case 0x80: ic->f = instr(mull_imm); break;
+		case 0xa0: ic->f = instr(mulq_imm); break;
+		default:if (!cpu->translation_readahead)
+				fatal("[ Alpha: unimplemented function 0x%03x "
+				    "for opcode 0x%02x ]\n", func, opcode);
+			goto bad;
+		}
+		break;
+	case 0x16:
+		if (rc == ALPHA_ZERO) {
+			ic->f = instr(nop);
+			break;
+		}
+		ic->arg[0] = (size_t) &cpu->cd.alpha.f[rc];
+		ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra];
+		ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb];
+		switch (func & 0x7ff) {
+		case 0x02f: ic->f = instr(cvttq_c); break;
+		case 0x0a0: ic->f = instr(addt); break;
+		case 0x0a1: ic->f = instr(subt); break;
+		case 0x0a2: ic->f = instr(mult); break;
+		case 0x0a3: ic->f = instr(divt); break;
+		case 0x0a5: ic->f = instr(cmpteq); break;
+		case 0x0a6: ic->f = instr(cmptlt); break;
+		case 0x0a7: ic->f = instr(cmptle); break;
+		case 0x0be: ic->f = instr(cvtqt); break;
+		default:if (!cpu->translation_readahead)
+				fatal("[ Alpha: unimplemented function 0x%03x "
+				    "for opcode 0x%02x ]\n", func, opcode);
+			goto bad;
+		}
+		break;
+	case 0x17:
+		if (rc == ALPHA_ZERO) {
+			ic->f = instr(nop);
+			break;
+		}
+		ic->arg[0] = (size_t) &cpu->cd.alpha.f[rc];
+		ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra];
+		ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb];
+		switch (func & 0x7ff) {
+		case 0x020:
+			/*  fabs (or fclr):  */
+			if (ra == 31 && rb == 31)
+				ic->f = instr(clear);
+			else
+				ic->f = instr(fabs);
+			break;
+		case 0x021:
+			ic->f = instr(fneg);
+			break;
+		default:if (!cpu->translation_readahead)
+				fatal("[ Alpha: unimplemented function 0x%03x "
+				    "for opcode 0x%02x ]\n", func, opcode);
+			goto bad;
+		}
+		break;
+	case 0x18:
+		switch (iword & 0xffff) {
+		case 0x4000:	/*  mb  */
+		case 0x4400:	/*  wmb  */
+			ic->f = instr(nop);
+			break;
+		case 0xc000:	/*  rdcc  ra  */
+			if (ra == ALPHA_ZERO) {
+				ic->f = instr(nop);
+				break;
+			}
+			ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
+			ic->f = instr(rdcc);
+			break;
+		default:if (!cpu->translation_readahead)
+				fatal("[ Alpha: unimplemented function 0x%03x "
+				    "for opcode 0x%02x ]\n", func, opcode);
+			goto bad;
+		}
+		break;
+	case 0x1a:
+		switch ((iword >> 14) & 3) {
+		case 0:	/*  JMP  */
+		case 1:	/*  JSR  */
+		case 2:	/*  RET  */
+			ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
+			ic->arg[1] = (size_t) &cpu->cd.alpha.r[rb];
+			if (ra == ALPHA_ZERO) {
+				if (cpu->machine->show_trace_tree &&
+				    rb == ALPHA_RA)
+					ic->f = instr(jsr_0_trace);
+				else
+					ic->f = instr(jsr_0);
+			} else {
+				if (cpu->machine->show_trace_tree)
+					ic->f = instr(jsr_trace);
+				else
+					ic->f = instr(jsr);
+			}
+			break;
+		default:if (!cpu->translation_readahead)
+				fatal("[ Alpha: unimpl JSR type %i, ra=%i "
+				    "rb=%i ]\n", ((iword >> 14) & 3), ra, rb);
+			goto bad;
+		}
+		break;
+	case 0x30:						/*  BR    */
+	case 0x31:						/*  FBEQ  */
+	case 0x34:						/*  BSR   */
+	case 0x35:						/*  FBNE  */
+	case 0x38:						/*  BLBC  */
+	case 0x39:						/*  BEQ   */
+	case 0x3a:						/*  BLT   */
+	case 0x3b:						/*  BLE   */
+	case 0x3c:						/*  BLBS  */
+	case 0x3d:						/*  BNE   */
+	case 0x3e:						/*  BGE   */
+	case 0x3f:						/*  BGT   */
+		/*  To avoid a GCC warning:  */
+		samepage_function = instr(nop);
+		fp = 0;
+		switch (opcode) {
+		case 0x30:
+		case 0x34:
+			ic->f = instr(br);
+			samepage_function = instr(br_samepage);
+			if (ra != ALPHA_ZERO) {
+				ic->f = instr(br_return);
+				samepage_function = instr(br_return_samepage);
+			}
+			break;
+		case 0x38:
+			ic->f = instr(blbc);
+			samepage_function = instr(blbc_samepage);
+			break;
+		case 0x31:
+			fp = 1;
+			// fall through
+		case 0x39:
+			ic->f = instr(beq);
+			samepage_function = instr(beq_samepage);
+			break;
+		case 0x3a:
+			ic->f = instr(blt);
+			samepage_function = instr(blt_samepage);
+			break;
+		case 0x3b:
+			ic->f = instr(ble);
+			samepage_function = instr(ble_samepage);
+			break;
+		case 0x3c:
+			ic->f = instr(blbs);
+			samepage_function = instr(blbs_samepage);
+			break;
+		case 0x35:
+			fp = 1;
+			// fall through
+		case 0x3d:
+			ic->f = instr(bne);
+			samepage_function = instr(bne_samepage);
+			break;
+		case 0x3e:
+			ic->f = instr(bge);
+			samepage_function = instr(bge_samepage);
+			break;
+		case 0x3f:
+			ic->f = instr(bgt);
+			samepage_function = instr(bgt_samepage);
+			break;
+		}
+		if (fp)
+			ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra];
+		else
+			ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
+		ic->arg[0] = (iword & 0x001fffff) << 2;
+		/*  Sign-extend:  */
+		if (ic->arg[0] & 0x00400000)
+			ic->arg[0] |= 0xffffffffff800000ULL;
+		/*  Branches are calculated as PC + 4 + offset.  */
+		ic->arg[0] = (size_t)(ic->arg[0] + 4);
+		/*  Special case: branch within the same page:  */
+		{
+			uint64_t mask_within_page =
+			    ((ALPHA_IC_ENTRIES_PER_PAGE-1) << 2) | 3;
+			uint64_t old_pc = addr;
+			uint64_t new_pc = old_pc + (int32_t)ic->arg[0];
+			if ((old_pc & ~mask_within_page) ==
+			    (new_pc & ~mask_within_page)) {
+				ic->f = samepage_function;
+				ic->arg[0] = (size_t) (
+				    cpu->cd.alpha.cur_ic_page +
+				    ((new_pc & mask_within_page) >> 2));
+			}
+		}
+		break;
+	default:if (!cpu->translation_readahead)
+			fatal("[ UNIMPLEMENTED Alpha opcode 0x%x ]\n", opcode);
+		goto bad;
+	}
+
+
+#define DYNTRANS_TO_BE_TRANSLATED_TAIL
+#include "cpu_dyntrans.c"
+#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_alpha_instr.cc gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_instr.cc
--- gxemul-0.6.2/src/cpus/cpu_alpha_instr.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_instr.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1288 +0,0 @@
-/*
- *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Alpha instructions.
- *
- *  Individual functions should keep track of cpu->n_translated_instrs.
- *  (If no instruction was executed, then it should be decreased. If, say, 4
- *  instructions were combined into one function and executed, then it should
- *  be increased by 3.)
- */
-
-
-#include "float_emul.h"
-
-
-/*
- *  nop:  Do nothing.
- */
-X(nop)
-{
-}
-
-
-/*
- *  call_pal:  PALcode call
- *
- *  arg[0] = pal nr
- */
-X(call_pal)
-{
-	/*  Synchronize PC first:  */
-	uint64_t old_pc, low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
-	cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1) <<
-	    ALPHA_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
-	old_pc = cpu->pc;
-
-	alpha_palcode(cpu, ic->arg[0]);
-
-	if (!cpu->running) {
-		cpu->n_translated_instrs --;
-		cpu->cd.alpha.next_ic = &nothing_call;
-	} else if (cpu->pc != old_pc) {
-		/*  The PC value was changed by the palcode call.  */
-		/*  Find the new physical page and update the translation
-		    pointers:  */
-		alpha_pc_to_pointers(cpu);
-	}
-}
-
-
-/*
- *  jsr:  Jump to SubRoutine
- *
- *  arg[0] = ptr to uint64_t where to store return PC
- *  arg[1] = ptr to uint64_t of new PC
- */
-X(jsr)
-{
-	uint64_t old_pc = cpu->pc, low_pc;
-	uint64_t mask_within_page = ((ALPHA_IC_ENTRIES_PER_PAGE-1)
-	    << ALPHA_INSTR_ALIGNMENT_SHIFT) |
-	    ((1 << ALPHA_INSTR_ALIGNMENT_SHIFT) - 1);
-
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
-	cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
-	    << ALPHA_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT) + 4;
-
-	*((int64_t *)ic->arg[0]) = cpu->pc;
-	cpu->pc = *((int64_t *)ic->arg[1]);
-
-	/*
-	 *  If this is a jump/return into the same code page as we were
-	 *  already in, then just set cpu->cd.alpha.next_ic.
-	 */
-	if ((old_pc & ~mask_within_page) == (cpu->pc & ~mask_within_page)) {
-		cpu->cd.alpha.next_ic = cpu->cd.alpha.cur_ic_page +
-		    ((cpu->pc & mask_within_page) >> 2);
-	} else {
-		/*  Find the new physical page and update pointers:  */
-		alpha_pc_to_pointers(cpu);
-	}
-}
-
-
-/*
- *  jsr_trace:  Jump to SubRoutine (with function call trace enabled)
- *
- *  Arguments same as for jsr.
- */
-X(jsr_trace)
-{
-	cpu_functioncall_trace(cpu, *((int64_t *)ic->arg[1]));
-	instr(jsr)(cpu, ic);
-}
-
-
-/*
- *  jsr_0:  JSR/RET, don't store return PC.
- *
- *  arg[0] = ignored
- *  arg[1] = ptr to uint64_t of new PC
- */
-X(jsr_0)
-{
-	uint64_t old_pc = cpu->pc;
-	uint64_t mask_within_page = ((ALPHA_IC_ENTRIES_PER_PAGE-1)
-	    << ALPHA_INSTR_ALIGNMENT_SHIFT)
-	    | ((1 << ALPHA_INSTR_ALIGNMENT_SHIFT) - 1);
-
-	cpu->pc = *((int64_t *)ic->arg[1]);
-
-	/*
-	 *  If this is a jump/return into the same code page as we were
-	 *  already in, then just set cpu->cd.alpha.next_ic.
-	 */
-	if ((old_pc & ~mask_within_page) == (cpu->pc & ~mask_within_page)) {
-		cpu->cd.alpha.next_ic = cpu->cd.alpha.cur_ic_page +
-		    ((cpu->pc & mask_within_page) >> 2);
-	} else {
-		/*  Find the new physical page and update pointers:  */
-		alpha_pc_to_pointers(cpu);
-	}
-}
-
-
-/*
- *  jsr_0_trace:  JSR/RET (with function call trace enabled)
- *
- *  Arguments same as for jsr_0.
- */
-X(jsr_0_trace)
-{
-	cpu_functioncall_trace_return(cpu);
-	instr(jsr_0)(cpu, ic);
-}
-
-
-/*
- *  br:  Branch (to a different translated page)
- *
- *  arg[0] = relative offset (as an int32_t)
- */
-X(br)
-{
-	uint64_t low_pc;
-
-	/*  Calculate new PC from this instruction + arg[0]  */
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
-	cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
-	    << ALPHA_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (int32_t)ic->arg[0];
-
-	/*  Find the new physical page and update the translation pointers:  */
-	alpha_pc_to_pointers(cpu);
-}
-
-
-/*
- *  br:  Branch (to a different translated page), write return address
- *
- *  arg[0] = relative offset (as an int32_t)
- *  arg[1] = pointer to uint64_t where to write return address
- */
-X(br_return)
-{
-	uint64_t low_pc;
-
-	/*  Calculate new PC from this instruction + arg[0]  */
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
-	cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
-	    << ALPHA_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
-
-	/*  ... but first, save away the return address:  */
-	*((int64_t *)ic->arg[1]) = cpu->pc + 4;
-
-	cpu->pc += (int32_t)ic->arg[0];
-
-	/*  Find the new physical page and update the translation pointers:  */
-	alpha_pc_to_pointers(cpu);
-}
-
-
-/*
- *  beq:  Branch (to a different translated page) if Equal
- *
- *  arg[0] = relative offset (as an int32_t)
- *  arg[1] = pointer to int64_t register
- */
-X(beq)
-{
-	if (*((int64_t *)ic->arg[1]) == 0)
-		instr(br)(cpu, ic);
-}
-
-
-/*
- *  blbs:  Branch (to a different translated page) if Low Bit Set
- *
- *  arg[0] = relative offset (as an int32_t)
- *  arg[1] = pointer to int64_t register
- */
-X(blbs)
-{
-	if (*((int64_t *)ic->arg[1]) & 1)
-		instr(br)(cpu, ic);
-}
-
-
-/*
- *  blbc:  Branch (to a different translated page) if Low Bit Clear
- *
- *  arg[0] = relative offset (as an int32_t)
- *  arg[1] = pointer to int64_t register
- */
-X(blbc)
-{
-	if (!(*((int64_t *)ic->arg[1]) & 1))
-		instr(br)(cpu, ic);
-}
-
-
-/*
- *  bne:  Branch (to a different translated page) if Not Equal
- *
- *  arg[0] = relative offset (as an int32_t)
- *  arg[1] = pointer to int64_t register
- */
-X(bne)
-{
-	if (*((int64_t *)ic->arg[1]) != 0)
-		instr(br)(cpu, ic);
-}
-
-
-/*
- *  ble:  Branch (to a different translated page) if Less or Equal
- *
- *  arg[0] = relative offset (as an int32_t)
- *  arg[1] = pointer to int64_t register
- */
-X(ble)
-{
-	if (*((int64_t *)ic->arg[1]) <= 0)
-		instr(br)(cpu, ic);
-}
-
-
-/*
- *  blt:  Branch (to a different translated page) if Less Than
- *
- *  arg[0] = relative offset (as an int32_t)
- *  arg[1] = pointer to int64_t register
- */
-X(blt)
-{
-	if (*((int64_t *)ic->arg[1]) < 0)
-		instr(br)(cpu, ic);
-}
-
-
-/*
- *  bge:  Branch (to a different translated page) if Greater or Equal
- *
- *  arg[0] = relative offset (as an int32_t)
- *  arg[1] = pointer to int64_t register
- */
-X(bge)
-{
-	if (*((int64_t *)ic->arg[1]) >= 0)
-		instr(br)(cpu, ic);
-}
-
-
-/*
- *  bgt:  Branch (to a different translated page) if Greater Than
- *
- *  arg[0] = relative offset (as an int32_t)
- *  arg[1] = pointer to int64_t register
- */
-X(bgt)
-{
-	if (*((int64_t *)ic->arg[1]) > 0)
-		instr(br)(cpu, ic);
-}
-
-
-/*
- *  br_samepage:  Branch (to within the same translated page)
- *
- *  arg[0] = pointer to new alpha_instr_call
- */
-X(br_samepage)
-{
-	cpu->cd.alpha.next_ic = (struct alpha_instr_call *) ic->arg[0];
-}
-
-
-/*
- *  br_return_samepage:  Branch (to within the same translated page),
- *                       and save return address
- *
- *  arg[0] = pointer to new alpha_instr_call
- *  arg[1] = pointer to uint64_t where to store return address
- */
-X(br_return_samepage)
-{
-	uint64_t low_pc;
-
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
-	cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
-	    << ALPHA_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
-	*((int64_t *)ic->arg[1]) = cpu->pc + 4;
-
-	cpu->cd.alpha.next_ic = (struct alpha_instr_call *) ic->arg[0];
-}
-
-
-/*
- *  beq_samepage:  Branch (to within the same translated page) if Equal
- *
- *  arg[0] = pointer to new alpha_instr_call
- *  arg[1] = pointer to int64_t register
- */
-X(beq_samepage)
-{
-	if (*((int64_t *)ic->arg[1]) == 0)
-		instr(br_samepage)(cpu, ic);
-}
-
-
-/*
- *  blbs_samepage:  Branch (to within the same translated page) if Low Bit Set
- *
- *  arg[0] = pointer to new alpha_instr_call
- *  arg[1] = pointer to int64_t register
- */
-X(blbs_samepage)
-{
-	if (*((int64_t *)ic->arg[1]) & 1)
-		instr(br_samepage)(cpu, ic);
-}
-
-
-/*
- *  blbc_samepage:  Branch (to within the same translated page) if Low Bit Clear
- *
- *  arg[0] = pointer to new alpha_instr_call
- *  arg[1] = pointer to int64_t register
- */
-X(blbc_samepage)
-{
-	if (!(*((int64_t *)ic->arg[1]) & 1))
-		instr(br_samepage)(cpu, ic);
-}
-
-
-/*
- *  bne_samepage:  Branch (to within the same translated page) if Not Equal
- *
- *  arg[0] = pointer to new alpha_instr_call
- *  arg[1] = pointer to int64_t register
- */
-X(bne_samepage)
-{
-	if (*((int64_t *)ic->arg[1]) != 0)
-		instr(br_samepage)(cpu, ic);
-}
-
-
-/*
- *  ble_samepage:  Branch (to within the same translated page) if Less or Equal
- *
- *  arg[0] = pointer to new alpha_instr_call
- *  arg[1] = pointer to int64_t register
- */
-X(ble_samepage)
-{
-	if (*((int64_t *)ic->arg[1]) <= 0)
-		instr(br_samepage)(cpu, ic);
-}
-
-
-/*
- *  blt_samepage:  Branch (to within the same translated page) if Less Than
- *
- *  arg[0] = pointer to new alpha_instr_call
- *  arg[1] = pointer to int64_t register
- */
-X(blt_samepage)
-{
-	if (*((int64_t *)ic->arg[1]) < 0)
-		instr(br_samepage)(cpu, ic);
-}
-
-
-/*
- *  bge_samepage:  Branch (to within the same translated page)
- *		   if Greater or Equal
- *
- *  arg[0] = pointer to new alpha_instr_call
- *  arg[1] = pointer to int64_t register
- */
-X(bge_samepage)
-{
-	if (*((int64_t *)ic->arg[1]) >= 0)
-		instr(br_samepage)(cpu, ic);
-}
-
-
-/*
- *  bgt_samepage:  Branch (to within the same translated page) if Greater Than
- *
- *  arg[0] = pointer to new alpha_instr_call
- *  arg[1] = pointer to int64_t register
- */
-X(bgt_samepage)
-{
-	if (*((int64_t *)ic->arg[1]) > 0)
-		instr(br_samepage)(cpu, ic);
-}
-
-
-/*
- *  cvttq/c:  Convert floating point to quad.
- *
- *  arg[0] = pointer to rc  (destination integer)
- *  arg[2] = pointer to rb  (source float)
- */
-X(cvttq_c)
-{
-	struct ieee_float_value fb;
-	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
-	reg(ic->arg[0]) = fb.nan? 0 : fb.f;
-}
-
-
-/*
- *  cvtqt:  Convert quad to floating point.
- *
- *  arg[0] = pointer to rc  (destination float)
- *  arg[2] = pointer to rb  (source quad integer)
- */
-X(cvtqt)
-{
-	reg(ic->arg[0]) = ieee_store_float_value(reg(ic->arg[2]), IEEE_FMT_D);
-}
-
-
-/*
- *  fabs, fneg:  Floating point absolute value, or negation.
- *
- *  arg[0] = pointer to rc  (destination float)
- *  arg[2] = pointer to rb  (source quad integer)
- */
-X(fabs)
-{
-	reg(ic->arg[0]) = reg(ic->arg[2]) & 0x7fffffffffffffffULL;
-}
-X(fneg)
-{
-	reg(ic->arg[0]) = reg(ic->arg[2]) ^ 0x8000000000000000ULL;
-}
-
-
-/*
- *  addt, subt, mult, divt:  Floating point arithmetic.
- *
- *  arg[0] = pointer to rc  (destination)
- *  arg[1] = pointer to ra  (source)
- *  arg[2] = pointer to rb  (source)
- */
-X(addt)
-{
-	struct ieee_float_value fa, fb;
-	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
-	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
-	reg(ic->arg[0]) = ieee_store_float_value(fa.f + fb.f, IEEE_FMT_D);
-}
-X(subt)
-{
-	struct ieee_float_value fa, fb;
-	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
-	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
-	reg(ic->arg[0]) = ieee_store_float_value(fa.f - fb.f, IEEE_FMT_D);
-}
-X(mult)
-{
-	struct ieee_float_value fa, fb;
-	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
-	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
-	reg(ic->arg[0]) = ieee_store_float_value(fa.f * fb.f, IEEE_FMT_D);
-}
-X(divt)
-{
-	struct ieee_float_value fa, fb;
-	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
-	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
-	reg(ic->arg[0]) = ieee_store_float_value(fa.f / fb.f, IEEE_FMT_D);
-}
-X(cmpteq)
-{
-	struct ieee_float_value fa, fb;
-	int res = 0;
-	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
-	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
-	if (fa.nan | fb.nan)
-		res = 0;
-	else
-		res = fa.f == fb.f;
-	reg(ic->arg[0]) = res;
-}
-X(cmptlt)
-{
-	struct ieee_float_value fa, fb;
-	int res = 0;
-	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
-	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
-	if (fa.nan | fb.nan)
-		res = 0;
-	else
-		res = fa.f < fb.f;
-	reg(ic->arg[0]) = res;
-}
-X(cmptle)
-{
-	struct ieee_float_value fa, fb;
-	int res = 0;
-	ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
-	ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
-	if (fa.nan | fb.nan)
-		res = 0;
-	else
-		res = fa.f <= fb.f;
-	reg(ic->arg[0]) = res;
-}
-
-
-/*
- *  implver:  Return CPU implver value.
- *
- *  arg[0] = pointer to destination uint64_t
- */
-X(implver)
-{
-	reg(ic->arg[0]) = cpu->cd.alpha.cpu_type.implver;
-}
-
-
-/*
- *  mull, mull_imm:  Signed Multiply 32x32 => 32.
- *
- *  arg[0] = pointer to destination uint64_t
- *  arg[1] = pointer to source uint64_t
- *  arg[2] = pointer to source uint64_t or immediate
- */
-X(mull)
-{
-	int32_t a = reg(ic->arg[1]);
-	int32_t b = reg(ic->arg[2]);
-	reg(ic->arg[0]) = (int64_t)(int32_t)(a * b);
-}
-X(mull_imm)
-{
-	int32_t a = reg(ic->arg[1]);
-	int32_t b = ic->arg[2];
-	reg(ic->arg[0]) = (int64_t)(int32_t)(a * b);
-}
-
-
-/*
- *  mulq, mulq_imm:  Unsigned Multiply 64x64 => 64.
- *
- *  arg[0] = pointer to destination uint64_t
- *  arg[1] = pointer to source uint64_t
- *  arg[2] = pointer to source uint64_t or immediate
- */
-X(mulq)
-{
-	reg(ic->arg[0]) = reg(ic->arg[1]) * reg(ic->arg[2]);
-}
-X(mulq_imm)
-{
-	reg(ic->arg[0]) = reg(ic->arg[1]) * ic->arg[2];
-}
-
-
-/*
- *  umulh:  Unsigned Multiply 64x64 => 128. Store high part in dest reg.
- *
- *  arg[0] = pointer to destination uint64_t
- *  arg[1] = pointer to source uint64_t
- *  arg[2] = pointer to source uint64_t
- */
-X(umulh)
-{
-	uint64_t reshi = 0, reslo = 0;
-	uint64_t s1 = reg(ic->arg[1]), s2 = reg(ic->arg[2]);
-	int i, bit;
-
-	for (i=0; i<64; i++) {
-		bit = (s1 & 0x8000000000000000ULL)? 1 : 0;
-		s1 <<= 1;
-
-		/*  If bit in s1 set, then add s2 to reshi/lo:  */
-		if (bit) {
-			uint64_t old_reslo = reslo;
-			reslo += s2;
-			if (reslo < old_reslo)
-				reshi ++;
-		}
-
-		if (i != 63) {
-			reshi <<= 1;
-			reshi += (reslo & 0x8000000000000000ULL? 1 : 0);
-			reslo <<= 1;
-		}
-	}
-
-	reg(ic->arg[0]) = reshi;
-}
-
-
-/*
- *  lda:  Load address.
- *
- *  arg[0] = pointer to destination uint64_t
- *  arg[1] = pointer to source uint64_t
- *  arg[2] = offset (possibly as an int32_t)
- */
-X(lda)
-{
-	reg(ic->arg[0]) = reg(ic->arg[1]) + (int64_t)(int32_t)ic->arg[2];
-}
-
-
-/*
- *  lda_0:  Load address compared to the zero register.
- *
- *  arg[0] = pointer to destination uint64_t
- *  arg[1] = ignored
- *  arg[2] = offset (possibly as an int32_t)
- */
-X(lda_0)
-{
-	reg(ic->arg[0]) = (int64_t)(int32_t)ic->arg[2];
-}
-
-
-/*
- *  clear:  Clear a 64-bit register.
- *
- *  arg[0] = pointer to destination uint64_t
- */
-X(clear)
-{
-	reg(ic->arg[0]) = 0;
-}
-
-
-/*
- *  rdcc:  Read the Cycle Counter into a 64-bit register.
- *
- *  arg[0] = pointer to destination uint64_t
- */
-X(rdcc)
-{
-	reg(ic->arg[0]) = cpu->cd.alpha.pcc;
-
-	/*  TODO: actually keep the pcc updated!  */
-	cpu->cd.alpha.pcc += 20;
-}
-
-
-#include "tmp_alpha_misc.cc"
-
-
-/*****************************************************************************/
-
-
-X(end_of_page)
-{
-	/*  Update the PC:  (offset 0, but on the next page)  */
-	cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
-	    << ALPHA_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (ALPHA_IC_ENTRIES_PER_PAGE
-	    << ALPHA_INSTR_ALIGNMENT_SHIFT);
-
-	/*  Find the new physical page and update the translation pointers:  */
-	alpha_pc_to_pointers(cpu);
-
-	/*  end_of_page doesn't count as an executed instruction:  */
-	cpu->n_translated_instrs --;
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  alpha_instr_to_be_translated():
- *
- *  Translate an instruction word into an alpha_instr_call. ic is filled in with
- *  valid data for the translated instruction, or a "nothing" instruction if
- *  there was a translation failure. The newly translated instruction is then
- *  executed.
- */
-X(to_be_translated)
-{
-	uint64_t addr, low_pc;
-	uint32_t iword;
-	unsigned char *page;
-	unsigned char ib[4];
-	void (*samepage_function)(struct cpu *, struct alpha_instr_call *);
-	int opcode, ra, rb, func, rc, imm, load, loadstore_type, fp, llsc;
-
-	/*  Figure out the (virtual) address of the instruction:  */
-	low_pc = ((size_t)ic - (size_t)cpu->cd.alpha.cur_ic_page)
-	    / sizeof(struct alpha_instr_call);
-	addr = cpu->pc & ~((ALPHA_IC_ENTRIES_PER_PAGE-1) <<
-	    ALPHA_INSTR_ALIGNMENT_SHIFT);
-	addr += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
-	addr &= ~((1 << ALPHA_INSTR_ALIGNMENT_SHIFT) - 1);
-	cpu->pc = addr;
-
-	/*  Read the instruction word from memory:  */
-	{
-		const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
-		const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
-		const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
-		uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
-		uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
-		uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
-		    DYNTRANS_L3N)) & mask3;
-		struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.alpha.l1_64[x1];
-		struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
-		page = l3->host_load[x3];
-	}
-
-	if (page != NULL) {
-		/*  fatal("TRANSLATION HIT!\n");  */
-		memcpy(ib, page + (addr & 8191), sizeof(ib));
-	} else {
-		/*  fatal("TRANSLATION MISS!\n");  */
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, &ib[0],
-		    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
-			fatal("to_be_translated(): read failed: TODO\n");
-			goto bad;
-		}
-	}
-
-	/*  Alpha instruction words are always little-endian. Convert
-	    to host order:  */
-	{
-		uint32_t *p = (uint32_t *) ib;
-		iword = LE32_TO_HOST( *p );
-	}
-
-#define DYNTRANS_TO_BE_TRANSLATED_HEAD
-#include "cpu_dyntrans.cc"
-#undef	DYNTRANS_TO_BE_TRANSLATED_HEAD
-
-
-	opcode = (iword >> 26) & 63;
-	ra = (iword >> 21) & 31;
-	rb = (iword >> 16) & 31;
-	func = (iword >> 5) & 0x7ff;
-	rc = iword & 31;
-	imm = iword & 0xffff;
-
-	switch (opcode) {
-	case 0x00:						/*  CALL_PAL  */
-		ic->f = instr(call_pal);
-		ic->arg[0] = (size_t) (iword & 0x3ffffff);
-		break;
-	case 0x08:						/*  LDA  */
-	case 0x09:						/*  LDAH  */
-		if (ra == ALPHA_ZERO) {
-			ic->f = instr(nop);
-			break;
-		}
-		/*  TODO: A special case which is common is to add or subtract
-		    a small offset from sp.  */
-		ic->f = instr(lda);
-		ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
-		ic->arg[1] = (size_t) &cpu->cd.alpha.r[rb];
-		if (rb == ALPHA_ZERO)
-			ic->f = instr(lda_0);
-		ic->arg[2] = (ssize_t)(int16_t)imm;
-		if (opcode == 0x09)
-			ic->arg[2] <<= 16;
-		break;
-	case 0x0b:						/*  LDQ_U  */
-	case 0x0f:						/*  STQ_U  */
-		if (ra == ALPHA_ZERO && opcode == 0x0b) {
-			ic->f = instr(nop);
-			break;
-		}
-		if (opcode == 0x0b)
-			ic->f = instr(ldq_u);
-		else
-			ic->f = instr(stq_u);
-		ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
-		ic->arg[1] = (size_t) &cpu->cd.alpha.r[rb];
-		ic->arg[2] = (ssize_t)(int16_t)imm;
-		break;
-	case 0x0a:
-	case 0x0c:
-	case 0x0d:
-	case 0x0e:
-	case 0x22:
-	case 0x23:
-	case 0x26:
-	case 0x27:
-	case 0x28:
-	case 0x29:
-	case 0x2a:
-	case 0x2b:
-	case 0x2c:
-	case 0x2d:
-	case 0x2e:
-	case 0x2f:
-		loadstore_type = 0; fp = 0; load = 0; llsc = 0;
-		switch (opcode) {
-		case 0x0a: loadstore_type = 0; load = 1; break;	/*  ldbu  */
-		case 0x0c: loadstore_type = 1; load = 1; break;	/*  ldwu  */
-		case 0x0d: loadstore_type = 1; break;		/*  stw  */
-		case 0x0e: loadstore_type = 0; break;		/*  stb  */
-		case 0x22: loadstore_type = 2; load = 1; fp = 1; break; /*lds*/
-		case 0x23: loadstore_type = 3; load = 1; fp = 1; break; /*ldt*/
-		case 0x26: loadstore_type = 2; fp = 1; break;	/*  sts  */
-		case 0x27: loadstore_type = 3; fp = 1; break;	/*  stt  */
-		case 0x28: loadstore_type = 2; load = 1; break;	/*  ldl  */
-		case 0x29: loadstore_type = 3; load = 1; break;	/*  ldq  */
-		case 0x2a: loadstore_type = 2; load = llsc = 1; break;/* ldl_l*/
-		case 0x2b: loadstore_type = 3; load = llsc = 1; break;/* ldq_l*/
-		case 0x2c: loadstore_type = 2; break;		/*  stl  */
-		case 0x2d: loadstore_type = 3; break;		/*  stq  */
-		case 0x2e: loadstore_type = 2; llsc = 1; break;	/*  stl_c  */
-		case 0x2f: loadstore_type = 3; llsc = 1; break;	/*  stq_c  */
-		}
-		ic->f = alpha_loadstore[
-		    loadstore_type + (imm==0? 4 : 0) + 8 * load
-		    + 16 * llsc];
-		/*  Load to the zero register is treated as a prefetch
-		    hint. It is ignored here.  */
-		if (load && ra == ALPHA_ZERO) {
-			ic->f = instr(nop);
-			break;
-		}
-		if (fp)
-			ic->arg[0] = (size_t) &cpu->cd.alpha.f[ra];
-		else
-			ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
-		ic->arg[1] = (size_t) &cpu->cd.alpha.r[rb];
-		ic->arg[2] = (ssize_t)(int16_t)imm;
-		break;
-	case 0x10:
-		if (rc == ALPHA_ZERO) {
-			ic->f = instr(nop);
-			break;
-		}
-		ic->arg[0] = (size_t) &cpu->cd.alpha.r[rc];
-		ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
-		if (func & 0x80)
-			ic->arg[2] = (size_t)((rb << 3) + (func >> 8));
-		else
-			ic->arg[2] = (size_t) &cpu->cd.alpha.r[rb];
-		switch (func & 0xff) {
-		case 0x00: ic->f = instr(addl); break;
-		case 0x02: ic->f = instr(s4addl); break;
-		case 0x09: ic->f = instr(subl); break;
-		case 0x0b: ic->f = instr(s4subl); break;
-		case 0x0f: ic->f = instr(cmpbge); break;
-		case 0x12: ic->f = instr(s8addl); break;
-		case 0x1b: ic->f = instr(s8subl); break;
-		case 0x1d: ic->f = instr(cmpult); break;
-		case 0x20: ic->f = instr(addq); break;
-		case 0x22: ic->f = instr(s4addq); break;
-		case 0x29: ic->f = instr(subq); break;
-		case 0x2b: ic->f = instr(s4subq); break;
-		case 0x2d: ic->f = instr(cmpeq); break;
-		case 0x32: ic->f = instr(s8addq); break;
-		case 0x3b: ic->f = instr(s8subq); break;
-		case 0x3d: ic->f = instr(cmpule); break;
-		case 0x4d: ic->f = instr(cmplt); break;
-		// case 0x69: ic->f = instr(subq_v); break;
-		case 0x6d: ic->f = instr(cmple); break;
-
-		case 0x80: ic->f = instr(addl_imm); break;
-		case 0x82: ic->f = instr(s4addl_imm); break;
-		case 0x89: ic->f = instr(subl_imm); break;
-		case 0x8b: ic->f = instr(s4subl_imm); break;
-		case 0x8f: ic->f = instr(cmpbge_imm); break;
-		case 0x92: ic->f = instr(s8addl_imm); break;
-		case 0x9b: ic->f = instr(s8subl_imm); break;
-		case 0x9d: ic->f = instr(cmpult_imm); break;
-		case 0xa0: ic->f = instr(addq_imm); break;
-		case 0xa2: ic->f = instr(s4addq_imm); break;
-		case 0xa9: ic->f = instr(subq_imm); break;
-		case 0xab: ic->f = instr(s4subq_imm); break;
-		case 0xad: ic->f = instr(cmpeq_imm); break;
-		case 0xb2: ic->f = instr(s8addq_imm); break;
-		case 0xbb: ic->f = instr(s8subq_imm); break;
-		case 0xbd: ic->f = instr(cmpule_imm); break;
-		case 0xcd: ic->f = instr(cmplt_imm); break;
-		case 0xed: ic->f = instr(cmple_imm); break;
-
-		default:if (!cpu->translation_readahead)
-				fatal("[ Alpha: unimplemented function 0x%03x "
-				    "for opcode 0x%02x ]\n", func, opcode);
-			goto bad;
-		}
-		break;
-	case 0x11:
-		if (rc == ALPHA_ZERO) {
-			ic->f = instr(nop);
-			break;
-		}
-		ic->arg[0] = (size_t) &cpu->cd.alpha.r[rc];
-		ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
-		if (func & 0x80)
-			ic->arg[2] = (size_t)((rb << 3) + (func >> 8));
-		else
-			ic->arg[2] = (size_t) &cpu->cd.alpha.r[rb];
-		switch (func & 0xff) {
-		case 0x00: ic->f = instr(and); break;
-		case 0x08: ic->f = instr(andnot); break;
-		case 0x14: ic->f = instr(cmovlbs); break;
-		case 0x16: ic->f = instr(cmovlbc); break;
-		case 0x20: ic->f = instr(or);
-			   if (ra == ALPHA_ZERO || rb == ALPHA_ZERO) {
-				if (ra == ALPHA_ZERO)
-					ra = rb;
-				ic->f = alpha_mov_r_r[ra + rc*32];
-			   }
-			   break;
-		case 0x24: ic->f = instr(cmoveq); break;
-		case 0x26: ic->f = instr(cmovne); break;
-		case 0x28: ic->f = instr(ornot); break;
-		case 0x40: ic->f = instr(xor); break;
-		case 0x44: ic->f = instr(cmovlt); break;
-		case 0x46: ic->f = instr(cmovge); break;
-		case 0x48: ic->f = instr(xornot); break;
-		case 0x64: ic->f = instr(cmovle); break;
-		case 0x66: ic->f = instr(cmovgt); break;
-		case 0x80: ic->f = instr(and_imm); break;
-		case 0x88: ic->f = instr(andnot_imm); break;
-		case 0x94: ic->f = instr(cmovlbs_imm); break;
-		case 0x96: ic->f = instr(cmovlbc_imm); break;
-		case 0xa0: ic->f = instr(or_imm); break;
-		case 0xa4: ic->f = instr(cmoveq_imm); break;
-		case 0xa6: ic->f = instr(cmovne_imm); break;
-		case 0xa8: ic->f = instr(ornot_imm); break;
-		case 0xc0: ic->f = instr(xor_imm); break;
-		case 0xc4: ic->f = instr(cmovlt_imm); break;
-		case 0xc6: ic->f = instr(cmovge_imm); break;
-		case 0xc8: ic->f = instr(xornot_imm); break;
-		case 0xe4: ic->f = instr(cmovle_imm); break;
-		case 0xe6: ic->f = instr(cmovgt_imm); break;
-		case 0xec: ic->f = instr(implver); break;
-		default:if (!cpu->translation_readahead)
-				fatal("[ Alpha: unimplemented function 0x%03x "
-				    "for opcode 0x%02x ]\n", func, opcode);
-			goto bad;
-		}
-		break;
-	case 0x12:
-		if (rc == ALPHA_ZERO) {
-			ic->f = instr(nop);
-			break;
-		}
-		ic->arg[0] = (size_t) &cpu->cd.alpha.r[rc];
-		ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
-		if (func & 0x80)
-			ic->arg[2] = (size_t)((rb << 3) + (func >> 8));
-		else
-			ic->arg[2] = (size_t) &cpu->cd.alpha.r[rb];
-		switch (func & 0xff) {
-		case 0x02: ic->f = instr(mskbl); break;
-		case 0x06: ic->f = instr(extbl); break;
-		case 0x0b: ic->f = instr(insbl); break;
-		case 0x12: ic->f = instr(mskwl); break;
-		case 0x16: ic->f = instr(extwl); break;
-		case 0x1b: ic->f = instr(inswl); break;
-		case 0x22: ic->f = instr(mskll); break;
-		case 0x26: ic->f = instr(extll); break;
-		case 0x2b: ic->f = instr(insll); break;
-		case 0x30: ic->f = instr(zap); break;
-		case 0x31: ic->f = instr(zapnot); break;
-		case 0x32: ic->f = instr(mskql); break;
-		case 0x34: ic->f = instr(srl); break;
-		case 0x36: ic->f = instr(extql); break;
-		case 0x39: ic->f = instr(sll); break;
-		case 0x3b: ic->f = instr(insql); break;
-		case 0x3c: ic->f = instr(sra); break;
-		case 0x52: ic->f = instr(mskwh); break;
-		case 0x57: ic->f = instr(inswh); break;
-		case 0x5a: ic->f = instr(extwh); break;
-		case 0x62: ic->f = instr(msklh); break;
-		case 0x67: ic->f = instr(inslh); break;
-		case 0x6a: ic->f = instr(extlh); break;
-		case 0x72: ic->f = instr(mskqh); break;
-		case 0x77: ic->f = instr(insqh); break;
-		case 0x7a: ic->f = instr(extqh); break;
-		case 0x82: ic->f = instr(mskbl_imm); break;
-		case 0x86: ic->f = instr(extbl_imm); break;
-		case 0x8b: ic->f = instr(insbl_imm); break;
-		case 0x92: ic->f = instr(mskwl_imm); break;
-		case 0x96: ic->f = instr(extwl_imm); break;
-		case 0x9b: ic->f = instr(inswl_imm); break;
-		case 0xa2: ic->f = instr(mskll_imm); break;
-		case 0xa6: ic->f = instr(extll_imm); break;
-		case 0xab: ic->f = instr(insll_imm); break;
-		case 0xb0: ic->f = instr(zap_imm); break;
-		case 0xb1: ic->f = instr(zapnot_imm); break;
-		case 0xb2: ic->f = instr(mskql_imm); break;
-		case 0xb4: ic->f = instr(srl_imm); break;
-		case 0xb6: ic->f = instr(extql_imm); break;
-		case 0xb9: ic->f = instr(sll_imm); break;
-		case 0xbb: ic->f = instr(insql_imm); break;
-		case 0xbc: ic->f = instr(sra_imm); break;
-		case 0xd2: ic->f = instr(mskwh_imm); break;
-		case 0xd7: ic->f = instr(inswh_imm); break;
-		case 0xda: ic->f = instr(extwh_imm); break;
-		case 0xe2: ic->f = instr(msklh_imm); break;
-		case 0xe7: ic->f = instr(inslh_imm); break;
-		case 0xea: ic->f = instr(extlh_imm); break;
-		case 0xf2: ic->f = instr(mskqh_imm); break;
-		case 0xf7: ic->f = instr(insqh_imm); break;
-		case 0xfa: ic->f = instr(extqh_imm); break;
-		default:if (!cpu->translation_readahead)
-				fatal("[ Alpha: unimplemented function 0x%03x "
-				    "for opcode 0x%02x ]\n", func, opcode);
-			goto bad;
-		}
-		break;
-	case 0x13:
-		if (rc == ALPHA_ZERO) {
-			ic->f = instr(nop);
-			break;
-		}
-		ic->arg[0] = (size_t) &cpu->cd.alpha.r[rc];
-		ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
-		if (func & 0x80)
-			ic->arg[2] = (size_t)((rb << 3) + (func >> 8));
-		else
-			ic->arg[2] = (size_t) &cpu->cd.alpha.r[rb];
-		// TODO: mulq/v etc? overflow detection
-		// bit 0..6 are function, but 7 is "imm" bit.
-		switch (func & 0xff) {
-		case 0x00: ic->f = instr(mull); break;
-		case 0x20: ic->f = instr(mulq); break;
-		case 0x30: ic->f = instr(umulh); break;
-		case 0x80: ic->f = instr(mull_imm); break;
-		case 0xa0: ic->f = instr(mulq_imm); break;
-		default:if (!cpu->translation_readahead)
-				fatal("[ Alpha: unimplemented function 0x%03x "
-				    "for opcode 0x%02x ]\n", func, opcode);
-			goto bad;
-		}
-		break;
-	case 0x16:
-		if (rc == ALPHA_ZERO) {
-			ic->f = instr(nop);
-			break;
-		}
-		ic->arg[0] = (size_t) &cpu->cd.alpha.f[rc];
-		ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra];
-		ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb];
-		switch (func & 0x7ff) {
-		case 0x02f: ic->f = instr(cvttq_c); break;
-		case 0x0a0: ic->f = instr(addt); break;
-		case 0x0a1: ic->f = instr(subt); break;
-		case 0x0a2: ic->f = instr(mult); break;
-		case 0x0a3: ic->f = instr(divt); break;
-		case 0x0a5: ic->f = instr(cmpteq); break;
-		case 0x0a6: ic->f = instr(cmptlt); break;
-		case 0x0a7: ic->f = instr(cmptle); break;
-		case 0x0be: ic->f = instr(cvtqt); break;
-		default:if (!cpu->translation_readahead)
-				fatal("[ Alpha: unimplemented function 0x%03x "
-				    "for opcode 0x%02x ]\n", func, opcode);
-			goto bad;
-		}
-		break;
-	case 0x17:
-		if (rc == ALPHA_ZERO) {
-			ic->f = instr(nop);
-			break;
-		}
-		ic->arg[0] = (size_t) &cpu->cd.alpha.f[rc];
-		ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra];
-		ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb];
-		switch (func & 0x7ff) {
-		case 0x020:
-			/*  fabs (or fclr):  */
-			if (ra == 31 && rb == 31)
-				ic->f = instr(clear);
-			else
-				ic->f = instr(fabs);
-			break;
-		case 0x021:
-			ic->f = instr(fneg);
-			break;
-		default:if (!cpu->translation_readahead)
-				fatal("[ Alpha: unimplemented function 0x%03x "
-				    "for opcode 0x%02x ]\n", func, opcode);
-			goto bad;
-		}
-		break;
-	case 0x18:
-		switch (iword & 0xffff) {
-		case 0x4000:	/*  mb  */
-		case 0x4400:	/*  wmb  */
-			ic->f = instr(nop);
-			break;
-		case 0xc000:	/*  rdcc  ra  */
-			if (ra == ALPHA_ZERO) {
-				ic->f = instr(nop);
-				break;
-			}
-			ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
-			ic->f = instr(rdcc);
-			break;
-		default:if (!cpu->translation_readahead)
-				fatal("[ Alpha: unimplemented function 0x%03x "
-				    "for opcode 0x%02x ]\n", func, opcode);
-			goto bad;
-		}
-		break;
-	case 0x1a:
-		switch ((iword >> 14) & 3) {
-		case 0:	/*  JMP  */
-		case 1:	/*  JSR  */
-		case 2:	/*  RET  */
-			ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
-			ic->arg[1] = (size_t) &cpu->cd.alpha.r[rb];
-			if (ra == ALPHA_ZERO) {
-				if (cpu->machine->show_trace_tree &&
-				    rb == ALPHA_RA)
-					ic->f = instr(jsr_0_trace);
-				else
-					ic->f = instr(jsr_0);
-			} else {
-				if (cpu->machine->show_trace_tree)
-					ic->f = instr(jsr_trace);
-				else
-					ic->f = instr(jsr);
-			}
-			break;
-		default:if (!cpu->translation_readahead)
-				fatal("[ Alpha: unimpl JSR type %i, ra=%i "
-				    "rb=%i ]\n", ((iword >> 14) & 3), ra, rb);
-			goto bad;
-		}
-		break;
-	case 0x30:						/*  BR    */
-	case 0x31:						/*  FBEQ  */
-	case 0x34:						/*  BSR   */
-	case 0x35:						/*  FBNE  */
-	case 0x38:						/*  BLBC  */
-	case 0x39:						/*  BEQ   */
-	case 0x3a:						/*  BLT   */
-	case 0x3b:						/*  BLE   */
-	case 0x3c:						/*  BLBS  */
-	case 0x3d:						/*  BNE   */
-	case 0x3e:						/*  BGE   */
-	case 0x3f:						/*  BGT   */
-		/*  To avoid a GCC warning:  */
-		samepage_function = instr(nop);
-		fp = 0;
-		switch (opcode) {
-		case 0x30:
-		case 0x34:
-			ic->f = instr(br);
-			samepage_function = instr(br_samepage);
-			if (ra != ALPHA_ZERO) {
-				ic->f = instr(br_return);
-				samepage_function = instr(br_return_samepage);
-			}
-			break;
-		case 0x38:
-			ic->f = instr(blbc);
-			samepage_function = instr(blbc_samepage);
-			break;
-		case 0x31:
-			fp = 1;
-		case 0x39:
-			ic->f = instr(beq);
-			samepage_function = instr(beq_samepage);
-			break;
-		case 0x3a:
-			ic->f = instr(blt);
-			samepage_function = instr(blt_samepage);
-			break;
-		case 0x3b:
-			ic->f = instr(ble);
-			samepage_function = instr(ble_samepage);
-			break;
-		case 0x3c:
-			ic->f = instr(blbs);
-			samepage_function = instr(blbs_samepage);
-			break;
-		case 0x35:
-			fp = 1;
-		case 0x3d:
-			ic->f = instr(bne);
-			samepage_function = instr(bne_samepage);
-			break;
-		case 0x3e:
-			ic->f = instr(bge);
-			samepage_function = instr(bge_samepage);
-			break;
-		case 0x3f:
-			ic->f = instr(bgt);
-			samepage_function = instr(bgt_samepage);
-			break;
-		}
-		if (fp)
-			ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra];
-		else
-			ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
-		ic->arg[0] = (iword & 0x001fffff) << 2;
-		/*  Sign-extend:  */
-		if (ic->arg[0] & 0x00400000)
-			ic->arg[0] |= 0xffffffffff800000ULL;
-		/*  Branches are calculated as PC + 4 + offset.  */
-		ic->arg[0] = (size_t)(ic->arg[0] + 4);
-		/*  Special case: branch within the same page:  */
-		{
-			uint64_t mask_within_page =
-			    ((ALPHA_IC_ENTRIES_PER_PAGE-1) << 2) | 3;
-			uint64_t old_pc = addr;
-			uint64_t new_pc = old_pc + (int32_t)ic->arg[0];
-			if ((old_pc & ~mask_within_page) ==
-			    (new_pc & ~mask_within_page)) {
-				ic->f = samepage_function;
-				ic->arg[0] = (size_t) (
-				    cpu->cd.alpha.cur_ic_page +
-				    ((new_pc & mask_within_page) >> 2));
-			}
-		}
-		break;
-	default:if (!cpu->translation_readahead)
-			fatal("[ UNIMPLEMENTED Alpha opcode 0x%x ]\n", opcode);
-		goto bad;
-	}
-
-
-#define DYNTRANS_TO_BE_TRANSLATED_TAIL
-#include "cpu_dyntrans.cc"
-#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_alpha_instr_loadstore.c gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_instr_loadstore.c
--- gxemul-0.6.2/src/cpus/cpu_alpha_instr_loadstore.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_instr_loadstore.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,286 @@
+/*
+ *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Alpha load/store instructions.  (Included from cpu_alpha_instr_inc.c.)
+ *
+ *
+ *  Load/store instructions have the following arguments:
+ *  
+ *  arg[0] = pointer to the register to load to or store from (uint64_t)
+ *  arg[1] = pointer to the base register (uint64_t)
+ *  arg[2] = offset (as an int32_t)
+ *
+ *  NOTE:
+ *	Alpha byte and word loads (8- and 16-bit) are unsigned, while
+ *	32-bit long words are sign-extended up to 64 bits during a load!
+ */
+
+
+#ifndef LS_IGNORE_OFFSET
+static void LS_GENERIC_N(struct cpu *cpu, struct alpha_instr_call *ic)
+{
+#ifdef LS_B
+	unsigned char data[1];
+#endif
+#ifdef LS_W
+	unsigned char data[2];
+#endif
+#ifdef LS_L
+	unsigned char data[4];
+#endif
+#ifdef LS_Q
+	unsigned char data[8];
+#endif
+	uint64_t addr = *((uint64_t *)ic->arg[1]);
+	uint64_t data_x;
+
+	addr += (int32_t)ic->arg[2];
+#ifdef LS_UNALIGNED
+	addr &= ~7;
+#endif
+
+#ifdef LS_LOAD
+	/*  Load:  */
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
+	    MEM_READ, CACHE_DATA)) {
+		fatal("store failed: TODO\n");
+		exit(1);
+	}
+
+	data_x = data[0];
+#ifndef LS_B
+	data_x += (data[1] << 8);
+#ifndef LS_W
+	data_x += (data[2] << 16);
+	data_x += ((uint64_t)data[3] << 24);
+#ifdef LS_L
+	data_x = (int64_t)(int32_t)data_x;
+#endif
+#ifndef LS_L
+	data_x += ((uint64_t)data[4] << 32);
+	data_x += ((uint64_t)data[5] << 40);
+	data_x += ((uint64_t)data[6] << 48);
+	data_x += ((uint64_t)data[7] << 56);
+#endif
+#endif
+#endif
+	*((uint64_t *)ic->arg[0]) = data_x;
+#else
+	/*  Store:  */
+	data_x = *((uint64_t *)ic->arg[0]);
+	data[0] = data_x;
+#ifndef LS_B
+	data[1] = data_x >> 8;
+#ifndef LS_W
+	data[2] = data_x >> 16;
+	data[3] = data_x >> 24;
+#ifndef LS_L
+	data[4] = data_x >> 32;
+	data[5] = data_x >> 40;
+	data[6] = data_x >> 48;
+	data[7] = data_x >> 56;
+#endif
+#endif
+#endif
+
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
+	    MEM_WRITE, CACHE_DATA)) {
+		fatal("store failed: TODO\n");
+		exit(1);
+	}
+
+#ifdef LS_LLSC
+#ifndef LS_LOAD
+	*((uint64_t *)ic->arg[0]) = 1;
+#endif
+#endif
+
+#endif
+}
+#endif
+
+
+static void LS_N(struct cpu *cpu, struct alpha_instr_call *ic)
+{
+	unsigned char *page;
+	uint64_t addr = (*((uint64_t *)ic->arg[1]))
+#ifndef LS_IGNORE_OFFSET
+	    + (int32_t)ic->arg[2]
+#endif
+	    ;
+
+	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+	uint32_t x1, x2, x3, c;
+	struct DYNTRANS_L2_64_TABLE *l2;
+	struct DYNTRANS_L3_64_TABLE *l3;
+	x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
+	x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+	x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
+	/*  fatal("X3: addr=%016" PRIx64" x1=%x x2=%x x3=%x\n",
+	    (uint64_t) addr, (int) x1, (int) x2, (int) x3);  */
+	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
+	/*  fatal("  l2 = %p\n", l2);  */
+	l3 = l2->l3[x2];
+	/*  fatal("  l3 = %p\n", l3);  */
+#ifdef LS_LOAD
+	page = l3->host_load[x3];
+#else
+	page = l3->host_store[x3];
+#endif
+
+#ifdef LS_UNALIGNED
+	addr &= ~7;
+#endif
+
+#ifdef LS_LLSC
+#ifdef LS_LOAD
+	/*  TODO: cache-line size!  */
+	cpu->cd.alpha.load_linked_addr = addr & ~63;
+	cpu->cd.alpha.ll_flag = 1;
+#else
+	/*  TODO: only invalidate per cache line, not everything!  */
+	if (cpu->cd.alpha.ll_flag == 1) {
+		int i;
+		for (i=0; i<cpu->machine->ncpus; i++)
+			cpu->machine->cpus[i]->cd.alpha.ll_flag = 0;
+	} else {
+		*((uint64_t *)ic->arg[0]) = 0;
+		return;
+	}
+#endif
+#endif
+
+	c = addr & 8191;
+
+#ifndef LS_B
+	if (c &
+#ifdef LS_W
+	    1
+#endif
+#ifdef LS_L
+	    3
+#endif
+#ifdef LS_Q
+	    7
+#endif
+	    ) {
+		LS_GENERIC_N(cpu, ic);
+		return;
+	}
+	else
+#endif
+
+	if (page != NULL) {
+#ifdef LS_LOAD
+#ifdef HOST_BIG_ENDIAN
+		uint64_t data_x;
+		data_x = page[c];
+#ifndef LS_B
+		data_x += (page[c+1] << 8);
+#ifndef LS_W
+		data_x += (page[c+2] << 16);
+		data_x += ((uint64_t)page[c+3] << 24);
+#ifndef LS_L
+		data_x += ((uint64_t)page[c+4] << 32);
+		data_x += ((uint64_t)page[c+5] << 40);
+		data_x += ((uint64_t)page[c+6] << 48);
+		data_x += ((uint64_t)page[c+7] << 56);
+#endif
+#endif
+#endif
+#ifdef LS_L
+		*((uint64_t *)ic->arg[0]) = (int64_t)(int32_t)data_x;
+#else
+		*((uint64_t *)ic->arg[0]) = data_x;
+#endif
+#else
+#ifdef LS_B
+		*((uint64_t *)ic->arg[0]) = page[c];
+#endif
+#ifdef LS_W
+		uint16_t d = *((uint16_t *) (page + c));
+		*((uint64_t *)ic->arg[0]) = d;
+#endif
+#ifdef LS_L
+		int32_t d = *((int32_t *) (page + c));
+		*((uint64_t *)ic->arg[0]) = (int64_t)d;
+#endif
+#ifdef LS_Q
+		uint64_t d = *((uint64_t *) (page + c));
+		*((uint64_t *)ic->arg[0]) = d;
+#endif
+#endif
+#else
+		/*  Store:  */
+#ifdef HOST_BIG_ENDIAN
+		uint64_t data_x = *((uint64_t *)ic->arg[0]);
+		page[c] = data_x;
+#ifndef LS_B
+		page[c+1] = data_x >> 8;
+#ifndef LS_W
+		page[c+2] = data_x >> 16;
+		page[c+3] = data_x >> 24;
+#ifndef LS_L
+		page[c+4] = data_x >> 32;
+		page[c+5] = data_x >> 40;
+		page[c+6] = data_x >> 48;
+		page[c+7] = data_x >> 56;
+#endif
+#endif
+#endif
+#else
+		/*  Native byte order:  */
+#ifdef LS_B
+		page[c] = *((uint64_t *)ic->arg[0]);
+#endif
+#ifdef LS_W
+		uint32_t d = *((uint64_t *)ic->arg[0]);
+		*((uint16_t *) (page + c)) = d;
+#endif
+#ifdef LS_L
+		uint32_t d = *((uint64_t *)ic->arg[0]);
+		*((uint32_t *) (page + c)) = d;
+#endif
+#ifdef LS_Q
+		uint64_t d = *((uint64_t *)ic->arg[0]);
+		*((uint64_t *) (page + c)) = d;
+#endif
+#endif
+
+#ifdef LS_LLSC
+#ifndef LS_LOAD
+		*((uint64_t *)ic->arg[0]) = 1;
+#endif
+#endif
+
+#endif	/*  !LS_LOAD  */
+	} else
+		LS_GENERIC_N(cpu, ic);
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_alpha_instr_loadstore.cc gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_instr_loadstore.cc
--- gxemul-0.6.2/src/cpus/cpu_alpha_instr_loadstore.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_instr_loadstore.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,286 +0,0 @@
-/*
- *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Alpha load/store instructions.  (Included from cpu_alpha_instr_inc.c.)
- *
- *
- *  Load/store instructions have the following arguments:
- *  
- *  arg[0] = pointer to the register to load to or store from (uint64_t)
- *  arg[1] = pointer to the base register (uint64_t)
- *  arg[2] = offset (as an int32_t)
- *
- *  NOTE:
- *	Alpha byte and word loads (8- and 16-bit) are unsigned, while
- *	32-bit long words are sign-extended up to 64 bits during a load!
- */
-
-
-#ifndef LS_IGNORE_OFFSET
-static void LS_GENERIC_N(struct cpu *cpu, struct alpha_instr_call *ic)
-{
-#ifdef LS_B
-	unsigned char data[1];
-#endif
-#ifdef LS_W
-	unsigned char data[2];
-#endif
-#ifdef LS_L
-	unsigned char data[4];
-#endif
-#ifdef LS_Q
-	unsigned char data[8];
-#endif
-	uint64_t addr = *((uint64_t *)ic->arg[1]);
-	uint64_t data_x;
-
-	addr += (int32_t)ic->arg[2];
-#ifdef LS_UNALIGNED
-	addr &= ~7;
-#endif
-
-#ifdef LS_LOAD
-	/*  Load:  */
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
-	    MEM_READ, CACHE_DATA)) {
-		fatal("store failed: TODO\n");
-		exit(1);
-	}
-
-	data_x = data[0];
-#ifndef LS_B
-	data_x += (data[1] << 8);
-#ifndef LS_W
-	data_x += (data[2] << 16);
-	data_x += ((uint64_t)data[3] << 24);
-#ifdef LS_L
-	data_x = (int64_t)(int32_t)data_x;
-#endif
-#ifndef LS_L
-	data_x += ((uint64_t)data[4] << 32);
-	data_x += ((uint64_t)data[5] << 40);
-	data_x += ((uint64_t)data[6] << 48);
-	data_x += ((uint64_t)data[7] << 56);
-#endif
-#endif
-#endif
-	*((uint64_t *)ic->arg[0]) = data_x;
-#else
-	/*  Store:  */
-	data_x = *((uint64_t *)ic->arg[0]);
-	data[0] = data_x;
-#ifndef LS_B
-	data[1] = data_x >> 8;
-#ifndef LS_W
-	data[2] = data_x >> 16;
-	data[3] = data_x >> 24;
-#ifndef LS_L
-	data[4] = data_x >> 32;
-	data[5] = data_x >> 40;
-	data[6] = data_x >> 48;
-	data[7] = data_x >> 56;
-#endif
-#endif
-#endif
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
-	    MEM_WRITE, CACHE_DATA)) {
-		fatal("store failed: TODO\n");
-		exit(1);
-	}
-
-#ifdef LS_LLSC
-#ifndef LS_LOAD
-	*((uint64_t *)ic->arg[0]) = 1;
-#endif
-#endif
-
-#endif
-}
-#endif
-
-
-static void LS_N(struct cpu *cpu, struct alpha_instr_call *ic)
-{
-	unsigned char *page;
-	uint64_t addr = (*((uint64_t *)ic->arg[1]))
-#ifndef LS_IGNORE_OFFSET
-	    + (int32_t)ic->arg[2]
-#endif
-	    ;
-
-	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
-	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
-	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
-	uint32_t x1, x2, x3, c;
-	struct DYNTRANS_L2_64_TABLE *l2;
-	struct DYNTRANS_L3_64_TABLE *l3;
-	x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
-	x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
-	x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
-	/*  fatal("X3: addr=%016" PRIx64" x1=%x x2=%x x3=%x\n",
-	    (uint64_t) addr, (int) x1, (int) x2, (int) x3);  */
-	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
-	/*  fatal("  l2 = %p\n", l2);  */
-	l3 = l2->l3[x2];
-	/*  fatal("  l3 = %p\n", l3);  */
-#ifdef LS_LOAD
-	page = l3->host_load[x3];
-#else
-	page = l3->host_store[x3];
-#endif
-
-#ifdef LS_UNALIGNED
-	addr &= ~7;
-#endif
-
-#ifdef LS_LLSC
-#ifdef LS_LOAD
-	/*  TODO: cache-line size!  */
-	cpu->cd.alpha.load_linked_addr = addr & ~63;
-	cpu->cd.alpha.ll_flag = 1;
-#else
-	/*  TODO: only invalidate per cache line, not everything!  */
-	if (cpu->cd.alpha.ll_flag == 1) {
-		int i;
-		for (i=0; i<cpu->machine->ncpus; i++)
-			cpu->machine->cpus[i]->cd.alpha.ll_flag = 0;
-	} else {
-		*((uint64_t *)ic->arg[0]) = 0;
-		return;
-	}
-#endif
-#endif
-
-	c = addr & 8191;
-
-#ifndef LS_B
-	if (c &
-#ifdef LS_W
-	    1
-#endif
-#ifdef LS_L
-	    3
-#endif
-#ifdef LS_Q
-	    7
-#endif
-	    ) {
-		LS_GENERIC_N(cpu, ic);
-		return;
-	}
-	else
-#endif
-
-	if (page != NULL) {
-#ifdef LS_LOAD
-#ifdef HOST_BIG_ENDIAN
-		uint64_t data_x;
-		data_x = page[c];
-#ifndef LS_B
-		data_x += (page[c+1] << 8);
-#ifndef LS_W
-		data_x += (page[c+2] << 16);
-		data_x += ((uint64_t)page[c+3] << 24);
-#ifndef LS_L
-		data_x += ((uint64_t)page[c+4] << 32);
-		data_x += ((uint64_t)page[c+5] << 40);
-		data_x += ((uint64_t)page[c+6] << 48);
-		data_x += ((uint64_t)page[c+7] << 56);
-#endif
-#endif
-#endif
-#ifdef LS_L
-		*((uint64_t *)ic->arg[0]) = (int64_t)(int32_t)data_x;
-#else
-		*((uint64_t *)ic->arg[0]) = data_x;
-#endif
-#else
-#ifdef LS_B
-		*((uint64_t *)ic->arg[0]) = page[c];
-#endif
-#ifdef LS_W
-		uint16_t d = *((uint16_t *) (page + c));
-		*((uint64_t *)ic->arg[0]) = d;
-#endif
-#ifdef LS_L
-		int32_t d = *((int32_t *) (page + c));
-		*((uint64_t *)ic->arg[0]) = (int64_t)d;
-#endif
-#ifdef LS_Q
-		uint64_t d = *((uint64_t *) (page + c));
-		*((uint64_t *)ic->arg[0]) = d;
-#endif
-#endif
-#else
-		/*  Store:  */
-#ifdef HOST_BIG_ENDIAN
-		uint64_t data_x = *((uint64_t *)ic->arg[0]);
-		page[c] = data_x;
-#ifndef LS_B
-		page[c+1] = data_x >> 8;
-#ifndef LS_W
-		page[c+2] = data_x >> 16;
-		page[c+3] = data_x >> 24;
-#ifndef LS_L
-		page[c+4] = data_x >> 32;
-		page[c+5] = data_x >> 40;
-		page[c+6] = data_x >> 48;
-		page[c+7] = data_x >> 56;
-#endif
-#endif
-#endif
-#else
-		/*  Native byte order:  */
-#ifdef LS_B
-		page[c] = *((uint64_t *)ic->arg[0]);
-#endif
-#ifdef LS_W
-		uint32_t d = *((uint64_t *)ic->arg[0]);
-		*((uint16_t *) (page + c)) = d;
-#endif
-#ifdef LS_L
-		uint32_t d = *((uint64_t *)ic->arg[0]);
-		*((uint32_t *) (page + c)) = d;
-#endif
-#ifdef LS_Q
-		uint64_t d = *((uint64_t *)ic->arg[0]);
-		*((uint64_t *) (page + c)) = d;
-#endif
-#endif
-
-#ifdef LS_LLSC
-#ifndef LS_LOAD
-		*((uint64_t *)ic->arg[0]) = 1;
-#endif
-#endif
-
-#endif	/*  !LS_LOAD  */
-	} else
-		LS_GENERIC_N(cpu, ic);
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_alpha_palcode.c gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_palcode.c
--- gxemul-0.6.2/src/cpus/cpu_alpha_palcode.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_palcode.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,393 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Alpha PALcode-related functionality.
+ *
+ *  (See http://www.alphalinux.org/docs/alphaahb.html for good descriptions
+ *  of many PALcode functions.)
+ */
+
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "symbol.h"
+
+#include "thirdparty/alpha_prom.h"
+
+
+/*
+ *  alpha_palcode_name():
+ *
+ *  Return the name of a PALcode number, as a string.
+ */
+void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen)
+{
+	switch (palcode) {
+	case 0x00: snprintf(buf, buflen, "PAL_halt"); break;
+	case 0x01: snprintf(buf, buflen, "PAL_cflush"); break;
+	case 0x02: snprintf(buf, buflen, "PAL_draina"); break;
+	case 0x09: snprintf(buf, buflen, "PAL_cserve"); break;
+	case 0x0a: snprintf(buf, buflen, "PAL_swppal"); break;
+	case 0x0d: snprintf(buf, buflen, "PAL_ipir"); break;
+	case 0x10: snprintf(buf, buflen, "PAL_OSF1_rdmces"); break;
+	case 0x11: snprintf(buf, buflen, "PAL_OSF1_wrmces"); break;
+	case 0x2b: snprintf(buf, buflen, "PAL_OSF1_wrfen"); break;
+	case 0x2d: snprintf(buf, buflen, "PAL_OSF1_wrvptptr"); break;
+	case 0x30: snprintf(buf, buflen, "PAL_OSF1_swpctx"); break;
+	case 0x31: snprintf(buf, buflen, "PAL_OSF1_wrval"); break;
+	case 0x32: snprintf(buf, buflen, "PAL_OSF1_rdval"); break;
+	case 0x33: snprintf(buf, buflen, "PAL_OSF1_tbi"); break;
+	case 0x34: snprintf(buf, buflen, "PAL_OSF1_wrent"); break;
+	case 0x35: snprintf(buf, buflen, "PAL_OSF1_swpipl"); break;
+	case 0x36: snprintf(buf, buflen, "PAL_rdps"); break;
+	case 0x37: snprintf(buf, buflen, "PAL_OSF1_wrkgp"); break;
+	case 0x38: snprintf(buf, buflen, "PAL_OSF1_wrusp"); break;
+	case 0x39: snprintf(buf, buflen, "PAL_OSF1_wrperfmon"); break;
+	case 0x3a: snprintf(buf, buflen, "PAL_OSF1_rdusp"); break;
+	case 0x3c: snprintf(buf, buflen, "PAL_whami"); break;
+	case 0x3d: snprintf(buf, buflen, "PAL_OSF1_retsys"); break;
+	case 0x3e: snprintf(buf, buflen, "PAL_wtint"); break;
+	case 0x3f: snprintf(buf, buflen, "PAL_OSF1_rti"); break;
+	case 0x80: snprintf(buf, buflen, "PAL_bpt"); break;
+	case 0x81: snprintf(buf, buflen, "PAL_bugchk"); break;
+	case 0x83: snprintf(buf, buflen, "PAL_OSF1_callsys"); break;
+	case 0x86: snprintf(buf, buflen, "PAL_imb"); break;
+	case 0x92: snprintf(buf, buflen, "PAL_OSF1_urti"); break;
+	case 0x9e: snprintf(buf, buflen, "PAL_rdunique"); break;
+	case 0x9f: snprintf(buf, buflen, "PAL_wrunique"); break;
+	case 0xaa: snprintf(buf, buflen, "PAL_gentrap"); break;
+	case 0xae: snprintf(buf, buflen, "PAL_clrfen"); break;
+	case 0x3fffffe: snprintf(buf, buflen, "GXemul_PROM"); break;
+	default:snprintf(buf, buflen, "UNKNOWN 0x%" PRIx32, palcode);
+	}
+}
+
+
+/*
+ *  alpha_prom_call():
+ */
+void alpha_prom_call(struct cpu *cpu)
+{
+	uint64_t addr, a1 = cpu->cd.alpha.r[ALPHA_A1];
+	uint64_t a2 = cpu->cd.alpha.r[ALPHA_A2], a3 = cpu->cd.alpha.r[ALPHA_A3];
+	uint64_t len;
+	const char *s = "";
+
+	switch (cpu->cd.alpha.r[ALPHA_A0]) {
+
+	case PROM_R_PUTS:
+		/*  a1 = channel, a2 = ptr to buf, a3 = len  */
+		for (addr = a2; addr < a2 + a3; addr ++) {
+			unsigned char ch;
+			cpu->memory_rw(cpu, cpu->mem, addr, &ch, sizeof(ch),
+			    MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
+			console_putchar(cpu->machine->main_console_handle, ch);
+		}
+		cpu->cd.alpha.r[ALPHA_V0] = a3;
+		break;
+
+	case PROM_R_GETENV:
+		/*  a1 = variable id, a2 = char *buf, a3 = bufsize  */
+		switch (a1) {
+		case PROM_E_BOOTED_DEV:
+			s = "";		/*  TODO  */
+			break;
+		case PROM_E_BOOTED_FILE:
+			s = cpu->machine->boot_kernel_filename;
+			break;
+		case PROM_E_BOOTED_OSFLAGS:
+			s = cpu->machine->boot_string_argument;
+			break;
+		case PROM_E_TTY_DEV:
+			s = "";		/*  TODO  */
+			break;
+		default:fatal("[ Alpha PALcode: GXemul PROM getenv %i: TODO "
+			    "]\n", cpu->cd.alpha.r[ALPHA_A1]);
+			cpu->running = 0;
+		}
+		/*  Copy at most a3 bytes.  */
+		len = a3;
+		if (strlen(s) < len)
+			len = strlen(s) + 1;
+		store_buf(cpu, a2, s, len);
+		break;
+
+	default:fatal("[ Alpha PALcode: GXemul PROM call, a0=0x%" PRIx64" ]\n",
+		    (uint64_t) cpu->cd.alpha.r[ALPHA_A0]);
+		cpu->running = 0;
+	}
+
+	/*  Return from the PROM call.  */
+	cpu->pc = cpu->cd.alpha.r[ALPHA_RA];
+}
+
+
+/*
+ *  alpha_palcode():
+ *
+ *  Execute an Alpha PALcode instruction. (Most of these correspond to
+ *  OSF1 palcodes, used by for example NetBSD/alpha.)
+ */
+void alpha_palcode(struct cpu *cpu, uint32_t palcode)
+{
+	uint64_t a0 = cpu->cd.alpha.r[ALPHA_A0], a1 = cpu->cd.alpha.r[ALPHA_A1];
+	uint64_t userMode = cpu->cd.alpha.ps & ALPHA_PSL_USERMODE;
+
+	/*
+	 *  Only these are unprivileged, i.e. can be invoked in user mode,
+	 *  according to the manual:
+	 *
+	 *	bpt		kernel and user
+	 *	bugchk		kernel and user
+	 *	callsys		user
+	 *	clrfen		user
+	 *	gentrap		kernel and user
+	 *	imb		kernel and user
+	 *	rdunique	kernel and user
+	 *	urti		user
+	 *	wrunique	kernel and user
+	 */
+
+	if (userMode && !(
+	    palcode == 0x80 || palcode == 0x81 || palcode == 0x83 ||
+	    palcode == 0xae || palcode == 0xaa || palcode == 0x86 ||
+	    palcode == 0x9e || palcode == 0x92 || palcode == 0x9f)) {
+		// opDec fault.
+		fatal("[ Privileged Alpha PALcode called from user mode: TODO ]");
+		cpu->running = 0;
+		return;
+	}
+
+	switch (palcode) {
+#if 0
+TODO: Uncomment more again, as I progress with the emulation...
+Make sure they are correct, as documented in the Manual.
+
+	case 0x02:	/*  PAL_draina  */
+		/*  TODO?  */
+		break;
+#endif
+	case 0x10:	/*  PAL_OSF1_rdmces  */
+		/*  Return Machine Check status in v0.  */
+		cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.mces;
+		break;
+	case 0x11:	/*  PAL_OSF1_wrmces  */
+		/*  Clear bits 0, 1, and 2 of the Machine Check and Error status.  */
+		cpu->cd.alpha.mces = ~(cpu->cd.alpha.r[ALPHA_A0] & 7);
+
+		/*  Set bits 3 and 4 of the Machine Check and Error status.  */
+		cpu->cd.alpha.mces &= ~0x18;
+		cpu->cd.alpha.mces |= (cpu->cd.alpha.r[ALPHA_A0] & 0x18);
+		break;
+	case 0x2b:	/*  PAL_OSF1_wrfen  */
+		/*  Floating point enable: a0 = 1 or 0.  */
+		/*  TODO. Since clrfen is documented as:
+			FEN ← 0
+			(PCBB+40)<0> ← 0
+		    then most likely wrfen should do the reverse.
+		 */
+		cpu->cd.alpha.pcb.apcb_flags = cpu->cd.alpha.r[ALPHA_A0];
+		store_64bit_word(cpu, cpu->cd.alpha.ctx + 40,
+		    cpu->cd.alpha.pcb.apcb_flags);
+		break;
+	case 0x2d:	/*  PAL_OSF1_wrvptptr  */
+		/*  Write Virtual Page Table Pointer. a0 = value  */
+		cpu->cd.alpha.vptptr = a0;
+		break;
+	case 0x30:	/*  PAL_OSF1_swpctx  */
+		/*  Save old context:  */
+		store_64bit_word(cpu, cpu->cd.alpha.ctx + 0,
+		    cpu->cd.alpha.pcb.apcb_ksp);
+		store_64bit_word(cpu, cpu->cd.alpha.ctx + 8,
+		    cpu->cd.alpha.pcb.apcb_usp);
+		store_64bit_word(cpu, cpu->cd.alpha.ctx + 16,
+		    cpu->cd.alpha.pcb.apcb_ptbr);
+		store_32bit_word(cpu, cpu->cd.alpha.ctx + 24,
+		    cpu->cd.alpha.pcb.apcb_cpc);
+		store_32bit_word(cpu, cpu->cd.alpha.ctx + 28,
+		    cpu->cd.alpha.pcb.apcb_asn);
+		store_64bit_word(cpu, cpu->cd.alpha.ctx + 32,
+		    cpu->cd.alpha.pcb.apcb_unique);
+		store_64bit_word(cpu, cpu->cd.alpha.ctx + 40,
+		    cpu->cd.alpha.pcb.apcb_flags);
+		store_64bit_word(cpu, cpu->cd.alpha.ctx + 48,
+		    cpu->cd.alpha.pcb.apcb_decrsv0);
+		store_64bit_word(cpu, cpu->cd.alpha.ctx + 56,
+		    cpu->cd.alpha.pcb.apcb_decrsv1);
+
+		/*  Return old context in v0.  */
+		cpu->cd.alpha.r[ALPHA_A0] = cpu->cd.alpha.ctx;
+
+		/*  Load new context:  */
+		{
+			cpu->cd.alpha.ctx = a0;
+			uint64_t new_ksp =
+			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 0);
+			uint64_t new_usp =
+			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 8);
+			uint64_t new_ptbr =
+			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 16);
+			uint64_t new_cpc =
+			    load_32bit_word(cpu, cpu->cd.alpha.ctx + 24);
+			uint64_t new_asn =
+			    load_32bit_word(cpu, cpu->cd.alpha.ctx + 28);
+			uint64_t new_unique =
+			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 32);
+			uint64_t new_flags =
+			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 40);
+			uint64_t new_decrsv0 =
+			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 48);
+			uint64_t new_decrsv1 =
+			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 56);
+
+			// Update all variables in the pcb simultaneously:
+			cpu->cd.alpha.pcb.apcb_ksp = new_ksp;
+			cpu->cd.alpha.pcb.apcb_usp = new_usp;
+			cpu->cd.alpha.pcb.apcb_ptbr = new_ptbr;
+			cpu->cd.alpha.pcb.apcb_cpc = new_cpc;
+			cpu->cd.alpha.pcb.apcb_asn = new_asn;
+			cpu->cd.alpha.pcb.apcb_unique = new_unique;
+			cpu->cd.alpha.pcb.apcb_ptbr = new_flags;
+			cpu->cd.alpha.pcb.apcb_decrsv0 = new_decrsv0;
+			cpu->cd.alpha.pcb.apcb_decrsv1 = new_decrsv1;
+
+			// TODO: Don't invalidate EVERYTHING!
+			cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
+		}
+		break;
+#if 0
+	case 0x31:	/*  PAL_OSF1_wrval  */
+		/*  a0 = value  */
+		cpu->cd.alpha.sysvalue = a0;
+		break;
+	case 0x32:	/*  PAL_OSF1_rdval  */
+		/*  return: v0 = value  */
+		cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.sysvalue;
+		break;
+#endif
+	case 0x33:	/*  PAL_OSF1_tbi  */
+		/*
+		 *  a0 = op, a1 = vaddr
+		 *  a0 is ignored for now. TODO.
+		 *	a0 = 1: ITB invalidate
+		 *	a0 = 2: DTB invalidate
+		 *	a0 = 3: both ITB and DTB
+		 *	a0 = -1: invalidate everything with ASM=0.
+		 *	a0 = -2: invalidate everything
+		 */
+		// debug("[ Alpha PALcode: PAL_OSF1_tbi: a0=%" PRIi64" a1=0x%"
+		//    PRIx64" ]\n", (int64_t)a0, (uint64_t)a1);
+		if (a0 >= 1)
+			cpu->invalidate_translation_caches(cpu, a1, INVALIDATE_VADDR);
+		else
+			cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
+		break;
+	case 0x34:	/*  PAL_OSF1_wrent (Write System Entry Address)  */
+		/*  a0 = new vector, a1 = vector selector  */
+		if (a1 < N_ALPHA_KENTRY)
+			cpu->cd.alpha.kentry[a1] = a0;
+		else {
+			fatal("[ Alpha PALcode: PAL_OSF1_wrent: attempt to "
+			    "write to non-implemented selector %i ]\n",
+			    (int)a1);
+			cpu->running = 0;
+		}
+		break;
+	case 0x35:	/*  PAL_OSF1_swpipl  */
+		/*  a0 = new ipl, v0 = return old ipl  */
+		cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.ps & ALPHA_PSL_IPL_MASK;
+		cpu->cd.alpha.ps &= ~ALPHA_PSL_IPL_MASK;
+		cpu->cd.alpha.ps |= (a0 & ALPHA_PSL_IPL_MASK);
+		break;
+	case 0x36:	/*  PAL_rdps  */
+		cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.ps;
+		break;
+	case 0x37:	/*  PAL_OSF1_wrkgp  */
+		cpu->cd.alpha.kgp = a0;
+		break;
+#if 0
+	case 0x38:	/*  PAL_OSF1_wrusp  */
+		/*  a0 = value  */
+		cpu->cd.alpha.pcb.apcb_usp = a0;
+		break;
+	case 0x3a:	/*  PAL_OSF1_rdusp  */
+		/*  return: v0 = value  */
+		cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.pcb.apcb_usp;
+		break;
+#endif
+	case 0x3c:	/*  PAL_whami  */
+		/*  Returns CPU id in v0:  */
+		cpu->cd.alpha.r[ALPHA_V0] = cpu->cpu_id;
+		break;
+#if 0
+	case 0x81:	/*  PAL_bugchk  */
+		cpu->running = 0;
+		break;
+	case 0x83:	/*  PAL_OSF1_syscall  */
+		fatal("[ Alpha PALcode: syscall, but no syscall handler ]\n");
+		cpu->running = 0;
+		break;
+#endif
+	case 0x86:	/*  PAL_imb  */
+		/*  TODO  */
+		break;
+#if 0
+	case 0x3fffffc:
+		fatal("[ Alpha: KENTRY not set! Halting. ]");
+		cpu->running = 0;
+		break;
+	case 0x3fffffd:
+		fatal("[ Alpha PALcode: Fixup: TODO ]\n");
+		/*  Return from the fixup call.  */
+		cpu->cd.alpha.r[ALPHA_V0] = 0;	/*  Success?  */
+		cpu->pc = cpu->cd.alpha.r[ALPHA_RA];
+		break;
+#endif
+	case 0x3fffffe:
+		alpha_prom_call(cpu);
+		break;
+	default:fatal("[ Alpha PALcode 0x%x unimplemented! ]\n", palcode);
+		cpu->running = 0;
+	}
+
+	/*
+	 *  Many PALcode instructions in the Alpha manual (and in NetBSD/Alpha
+	 *  source code) are described with "clobbers t0, t8-t11", some also
+	 *  with a0, and some also with a1 included.
+	 *
+	 *  However, it's easier to just leave the registers as they are.
+	 */
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_alpha_palcode.cc gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_palcode.cc
--- gxemul-0.6.2/src/cpus/cpu_alpha_palcode.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_alpha_palcode.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,393 +0,0 @@
-/*
- *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Alpha PALcode-related functionality.
- *
- *  (See http://www.alphalinux.org/docs/alphaahb.html for good descriptions
- *  of many PALcode functions.)
- */
-
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <ctype.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "symbol.h"
-
-#include "thirdparty/alpha_prom.h"
-
-
-/*
- *  alpha_palcode_name():
- *
- *  Return the name of a PALcode number, as a string.
- */
-void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen)
-{
-	switch (palcode) {
-	case 0x00: snprintf(buf, buflen, "PAL_halt"); break;
-	case 0x01: snprintf(buf, buflen, "PAL_cflush"); break;
-	case 0x02: snprintf(buf, buflen, "PAL_draina"); break;
-	case 0x09: snprintf(buf, buflen, "PAL_cserve"); break;
-	case 0x0a: snprintf(buf, buflen, "PAL_swppal"); break;
-	case 0x0d: snprintf(buf, buflen, "PAL_ipir"); break;
-	case 0x10: snprintf(buf, buflen, "PAL_OSF1_rdmces"); break;
-	case 0x11: snprintf(buf, buflen, "PAL_OSF1_wrmces"); break;
-	case 0x2b: snprintf(buf, buflen, "PAL_OSF1_wrfen"); break;
-	case 0x2d: snprintf(buf, buflen, "PAL_OSF1_wrvptptr"); break;
-	case 0x30: snprintf(buf, buflen, "PAL_OSF1_swpctx"); break;
-	case 0x31: snprintf(buf, buflen, "PAL_OSF1_wrval"); break;
-	case 0x32: snprintf(buf, buflen, "PAL_OSF1_rdval"); break;
-	case 0x33: snprintf(buf, buflen, "PAL_OSF1_tbi"); break;
-	case 0x34: snprintf(buf, buflen, "PAL_OSF1_wrent"); break;
-	case 0x35: snprintf(buf, buflen, "PAL_OSF1_swpipl"); break;
-	case 0x36: snprintf(buf, buflen, "PAL_rdps"); break;
-	case 0x37: snprintf(buf, buflen, "PAL_OSF1_wrkgp"); break;
-	case 0x38: snprintf(buf, buflen, "PAL_OSF1_wrusp"); break;
-	case 0x39: snprintf(buf, buflen, "PAL_OSF1_wrperfmon"); break;
-	case 0x3a: snprintf(buf, buflen, "PAL_OSF1_rdusp"); break;
-	case 0x3c: snprintf(buf, buflen, "PAL_whami"); break;
-	case 0x3d: snprintf(buf, buflen, "PAL_OSF1_retsys"); break;
-	case 0x3e: snprintf(buf, buflen, "PAL_wtint"); break;
-	case 0x3f: snprintf(buf, buflen, "PAL_OSF1_rti"); break;
-	case 0x80: snprintf(buf, buflen, "PAL_bpt"); break;
-	case 0x81: snprintf(buf, buflen, "PAL_bugchk"); break;
-	case 0x83: snprintf(buf, buflen, "PAL_OSF1_callsys"); break;
-	case 0x86: snprintf(buf, buflen, "PAL_imb"); break;
-	case 0x92: snprintf(buf, buflen, "PAL_OSF1_urti"); break;
-	case 0x9e: snprintf(buf, buflen, "PAL_rdunique"); break;
-	case 0x9f: snprintf(buf, buflen, "PAL_wrunique"); break;
-	case 0xaa: snprintf(buf, buflen, "PAL_gentrap"); break;
-	case 0xae: snprintf(buf, buflen, "PAL_clrfen"); break;
-	case 0x3fffffe: snprintf(buf, buflen, "GXemul_PROM"); break;
-	default:snprintf(buf, buflen, "UNKNOWN 0x%" PRIx32, palcode);
-	}
-}
-
-
-/*
- *  alpha_prom_call():
- */
-void alpha_prom_call(struct cpu *cpu)
-{
-	uint64_t addr, a1 = cpu->cd.alpha.r[ALPHA_A1];
-	uint64_t a2 = cpu->cd.alpha.r[ALPHA_A2], a3 = cpu->cd.alpha.r[ALPHA_A3];
-	uint64_t len;
-	const char *s = "";
-
-	switch (cpu->cd.alpha.r[ALPHA_A0]) {
-
-	case PROM_R_PUTS:
-		/*  a1 = channel, a2 = ptr to buf, a3 = len  */
-		for (addr = a2; addr < a2 + a3; addr ++) {
-			unsigned char ch;
-			cpu->memory_rw(cpu, cpu->mem, addr, &ch, sizeof(ch),
-			    MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
-			console_putchar(cpu->machine->main_console_handle, ch);
-		}
-		cpu->cd.alpha.r[ALPHA_V0] = a3;
-		break;
-
-	case PROM_R_GETENV:
-		/*  a1 = variable id, a2 = char *buf, a3 = bufsize  */
-		switch (a1) {
-		case PROM_E_BOOTED_DEV:
-			s = "";		/*  TODO  */
-			break;
-		case PROM_E_BOOTED_FILE:
-			s = cpu->machine->boot_kernel_filename;
-			break;
-		case PROM_E_BOOTED_OSFLAGS:
-			s = cpu->machine->boot_string_argument;
-			break;
-		case PROM_E_TTY_DEV:
-			s = "";		/*  TODO  */
-			break;
-		default:fatal("[ Alpha PALcode: GXemul PROM getenv %i: TODO "
-			    "]\n", cpu->cd.alpha.r[ALPHA_A1]);
-			cpu->running = 0;
-		}
-		/*  Copy at most a3 bytes.  */
-		len = a3;
-		if (strlen(s) < len)
-			len = strlen(s) + 1;
-		store_buf(cpu, a2, s, len);
-		break;
-
-	default:fatal("[ Alpha PALcode: GXemul PROM call, a0=0x%" PRIx64" ]\n",
-		    (uint64_t) cpu->cd.alpha.r[ALPHA_A0]);
-		cpu->running = 0;
-	}
-
-	/*  Return from the PROM call.  */
-	cpu->pc = cpu->cd.alpha.r[ALPHA_RA];
-}
-
-
-/*
- *  alpha_palcode():
- *
- *  Execute an Alpha PALcode instruction. (Most of these correspond to
- *  OSF1 palcodes, used by for example NetBSD/alpha.)
- */
-void alpha_palcode(struct cpu *cpu, uint32_t palcode)
-{
-	uint64_t a0 = cpu->cd.alpha.r[ALPHA_A0], a1 = cpu->cd.alpha.r[ALPHA_A1];
-	bool userMode = cpu->cd.alpha.ps & ALPHA_PSL_USERMODE;
-
-	/*
-	 *  Only these are unprivileged, i.e. can be invoked in user mode,
-	 *  according to the manual:
-	 *
-	 *	bpt		kernel and user
-	 *	bugchk		kernel and user
-	 *	callsys		user
-	 *	clrfen		user
-	 *	gentrap		kernel and user
-	 *	imb		kernel and user
-	 *	rdunique	kernel and user
-	 *	urti		user
-	 *	wrunique	kernel and user
-	 */
-
-	if (userMode && !(
-	    palcode == 0x80 || palcode == 0x81 || palcode == 0x83 ||
-	    palcode == 0xae || palcode == 0xaa || palcode == 0x86 ||
-	    palcode == 0x9e || palcode == 0x92 || palcode == 0x9f)) {
-		// opDec fault.
-		fatal("[ Privileged Alpha PALcode called from user mode: TODO ]");
-		cpu->running = 0;
-		return;
-	}
-
-	switch (palcode) {
-#if 0
-TODO: Uncomment more again, as I progress with the emulation...
-Make sure they are correct, as documented in the Manual.
-
-	case 0x02:	/*  PAL_draina  */
-		/*  TODO?  */
-		break;
-#endif
-	case 0x10:	/*  PAL_OSF1_rdmces  */
-		/*  Return Machine Check status in v0.  */
-		cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.mces;
-		break;
-	case 0x11:	/*  PAL_OSF1_wrmces  */
-		/*  Clear bits 0, 1, and 2 of the Machine Check and Error status.  */
-		cpu->cd.alpha.mces = ~(cpu->cd.alpha.r[ALPHA_A0] & 7);
-
-		/*  Set bits 3 and 4 of the Machine Check and Error status.  */
-		cpu->cd.alpha.mces &= ~0x18;
-		cpu->cd.alpha.mces |= (cpu->cd.alpha.r[ALPHA_A0] & 0x18);
-		break;
-	case 0x2b:	/*  PAL_OSF1_wrfen  */
-		/*  Floating point enable: a0 = 1 or 0.  */
-		/*  TODO. Since clrfen is documented as:
-			FEN ← 0
-			(PCBB+40)<0> ← 0
-		    then most likely wrfen should do the reverse.
-		 */
-		cpu->cd.alpha.pcb.apcb_flags = cpu->cd.alpha.r[ALPHA_A0];
-		store_64bit_word(cpu, cpu->cd.alpha.ctx + 40,
-		    cpu->cd.alpha.pcb.apcb_flags);
-		break;
-	case 0x2d:	/*  PAL_OSF1_wrvptptr  */
-		/*  Write Virtual Page Table Pointer. a0 = value  */
-		cpu->cd.alpha.vptptr = a0;
-		break;
-	case 0x30:	/*  PAL_OSF1_swpctx  */
-		/*  Save old context:  */
-		store_64bit_word(cpu, cpu->cd.alpha.ctx + 0,
-		    cpu->cd.alpha.pcb.apcb_ksp);
-		store_64bit_word(cpu, cpu->cd.alpha.ctx + 8,
-		    cpu->cd.alpha.pcb.apcb_usp);
-		store_64bit_word(cpu, cpu->cd.alpha.ctx + 16,
-		    cpu->cd.alpha.pcb.apcb_ptbr);
-		store_32bit_word(cpu, cpu->cd.alpha.ctx + 24,
-		    cpu->cd.alpha.pcb.apcb_cpc);
-		store_32bit_word(cpu, cpu->cd.alpha.ctx + 28,
-		    cpu->cd.alpha.pcb.apcb_asn);
-		store_64bit_word(cpu, cpu->cd.alpha.ctx + 32,
-		    cpu->cd.alpha.pcb.apcb_unique);
-		store_64bit_word(cpu, cpu->cd.alpha.ctx + 40,
-		    cpu->cd.alpha.pcb.apcb_flags);
-		store_64bit_word(cpu, cpu->cd.alpha.ctx + 48,
-		    cpu->cd.alpha.pcb.apcb_decrsv0);
-		store_64bit_word(cpu, cpu->cd.alpha.ctx + 56,
-		    cpu->cd.alpha.pcb.apcb_decrsv1);
-
-		/*  Return old context in v0.  */
-		cpu->cd.alpha.r[ALPHA_A0] = cpu->cd.alpha.ctx;
-
-		/*  Load new context:  */
-		{
-			cpu->cd.alpha.ctx = a0;
-			uint64_t new_ksp =
-			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 0);
-			uint64_t new_usp =
-			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 8);
-			uint64_t new_ptbr =
-			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 16);
-			uint64_t new_cpc =
-			    load_32bit_word(cpu, cpu->cd.alpha.ctx + 24);
-			uint64_t new_asn =
-			    load_32bit_word(cpu, cpu->cd.alpha.ctx + 28);
-			uint64_t new_unique =
-			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 32);
-			uint64_t new_flags =
-			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 40);
-			uint64_t new_decrsv0 =
-			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 48);
-			uint64_t new_decrsv1 =
-			    load_64bit_word(cpu, cpu->cd.alpha.ctx + 56);
-
-			// Update all variables in the pcb simultaneously:
-			cpu->cd.alpha.pcb.apcb_ksp = new_ksp;
-			cpu->cd.alpha.pcb.apcb_usp = new_usp;
-			cpu->cd.alpha.pcb.apcb_ptbr = new_ptbr;
-			cpu->cd.alpha.pcb.apcb_cpc = new_cpc;
-			cpu->cd.alpha.pcb.apcb_asn = new_asn;
-			cpu->cd.alpha.pcb.apcb_unique = new_unique;
-			cpu->cd.alpha.pcb.apcb_ptbr = new_flags;
-			cpu->cd.alpha.pcb.apcb_decrsv0 = new_decrsv0;
-			cpu->cd.alpha.pcb.apcb_decrsv1 = new_decrsv1;
-
-			// TODO: Don't invalidate EVERYTHING!
-			cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
-		}
-		break;
-#if 0
-	case 0x31:	/*  PAL_OSF1_wrval  */
-		/*  a0 = value  */
-		cpu->cd.alpha.sysvalue = a0;
-		break;
-	case 0x32:	/*  PAL_OSF1_rdval  */
-		/*  return: v0 = value  */
-		cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.sysvalue;
-		break;
-#endif
-	case 0x33:	/*  PAL_OSF1_tbi  */
-		/*
-		 *  a0 = op, a1 = vaddr
-		 *  a0 is ignored for now. TODO.
-		 *	a0 = 1: ITB invalidate
-		 *	a0 = 2: DTB invalidate
-		 *	a0 = 3: both ITB and DTB
-		 *	a0 = -1: invalidate everything with ASM=0.
-		 *	a0 = -2: invalidate everything
-		 */
-		// debug("[ Alpha PALcode: PAL_OSF1_tbi: a0=%" PRIi64" a1=0x%"
-		//    PRIx64" ]\n", (int64_t)a0, (uint64_t)a1);
-		if (a0 >= 1)
-			cpu->invalidate_translation_caches(cpu, a1, INVALIDATE_VADDR);
-		else
-			cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
-		break;
-	case 0x34:	/*  PAL_OSF1_wrent (Write System Entry Address)  */
-		/*  a0 = new vector, a1 = vector selector  */
-		if (a1 < N_ALPHA_KENTRY)
-			cpu->cd.alpha.kentry[a1] = a0;
-		else {
-			fatal("[ Alpha PALcode: PAL_OSF1_wrent: attempt to "
-			    "write to non-implemented selector %i ]\n",
-			    (int)a1);
-			cpu->running = 0;
-		}
-		break;
-	case 0x35:	/*  PAL_OSF1_swpipl  */
-		/*  a0 = new ipl, v0 = return old ipl  */
-		cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.ps & ALPHA_PSL_IPL_MASK;
-		cpu->cd.alpha.ps &= ~ALPHA_PSL_IPL_MASK;
-		cpu->cd.alpha.ps |= (a0 & ALPHA_PSL_IPL_MASK);
-		break;
-	case 0x36:	/*  PAL_rdps  */
-		cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.ps;
-		break;
-	case 0x37:	/*  PAL_OSF1_wrkgp  */
-		cpu->cd.alpha.kgp = a0;
-		break;
-#if 0
-	case 0x38:	/*  PAL_OSF1_wrusp  */
-		/*  a0 = value  */
-		cpu->cd.alpha.pcb.apcb_usp = a0;
-		break;
-	case 0x3a:	/*  PAL_OSF1_rdusp  */
-		/*  return: v0 = value  */
-		cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.pcb.apcb_usp;
-		break;
-#endif
-	case 0x3c:	/*  PAL_whami  */
-		/*  Returns CPU id in v0:  */
-		cpu->cd.alpha.r[ALPHA_V0] = cpu->cpu_id;
-		break;
-#if 0
-	case 0x81:	/*  PAL_bugchk  */
-		cpu->running = 0;
-		break;
-	case 0x83:	/*  PAL_OSF1_syscall  */
-		fatal("[ Alpha PALcode: syscall, but no syscall handler ]\n");
-		cpu->running = 0;
-		break;
-#endif
-	case 0x86:	/*  PAL_imb  */
-		/*  TODO  */
-		break;
-#if 0
-	case 0x3fffffc:
-		fatal("[ Alpha: KENTRY not set! Halting. ]");
-		cpu->running = 0;
-		break;
-	case 0x3fffffd:
-		fatal("[ Alpha PALcode: Fixup: TODO ]\n");
-		/*  Return from the fixup call.  */
-		cpu->cd.alpha.r[ALPHA_V0] = 0;	/*  Success?  */
-		cpu->pc = cpu->cd.alpha.r[ALPHA_RA];
-		break;
-#endif
-	case 0x3fffffe:
-		alpha_prom_call(cpu);
-		break;
-	default:fatal("[ Alpha PALcode 0x%x unimplemented! ]\n", palcode);
-		cpu->running = 0;
-	}
-
-	/*
-	 *  Many PALcode instructions in the Alpha manual (and in NetBSD/Alpha
-	 *  source code) are described with "clobbers t0, t8-t11", some also
-	 *  with a0, and some also with a1 included.
-	 *
-	 *  However, it's easier to just leave the registers as they are.
-	 */
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_arm.c gxemul-0.7.0+dfsg/src/cpus/cpu_arm.c
--- gxemul-0.6.2/src/cpus/cpu_arm.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_arm.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,2560 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  ARM CPU emulation.
+ *
+ *  A good source of quick info on ARM instruction encoding:
+ *  http://www.pinknoise.demon.co.uk/ARMinstrs/ARMinstrs.html
+ *
+ *  Another one, with details about THUMB:
+ *  http://engold.ui.ac.ir/~nikmehr/Appendix_B2.pdf
+ *
+ *  and yet another one, with descriptions about THUMB semantics:
+ *  https://web.eecs.umich.edu/~prabal/teaching/eecs373-f10/readings/ARM_QRC0006_UAL16.pdf
+ *
+ *  And one with the newer ARM v7 instructions:
+ *  http://vision.gel.ulaval.ca/~jflalonde/cours/1001/h17/docs/ARM_v7.pdf
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <unistd.h>
+
+#include "arm_cpu_types.h"
+#include "cpu.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "of.h"
+#include "settings.h"
+#include "symbol.h"
+
+#define DYNTRANS_32
+#include "tmp_arm_head.c"
+
+
+/*  ARM symbolic register names and condition strings:  */
+static const char *arm_regname[N_ARM_REGS] = ARM_REG_NAMES;
+static const char *arm_condition_string[16] = ARM_CONDITION_STRINGS;
+
+/*  Data Processing Instructions:  */
+static const char *arm_dpiname[16] = ARM_DPI_NAMES;
+static int arm_dpi_uses_d[16] = { 1,1,1,1,1,1,1,1,0,0,0,0,1,1,1,1 };
+static int arm_dpi_uses_n[16] = { 1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,0 };
+
+static const char *arm_thumb_dpiname[16] = ARM_THUMB_DPI_NAMES;
+
+static int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE;
+
+extern uint8_t condition_hi[16];
+extern uint8_t condition_ge[16];
+extern uint8_t condition_gt[16];
+
+/*  For quick_pc_to_pointers():  */
+void arm_pc_to_pointers(struct cpu *cpu);
+#include "quick_pc_to_pointers.h"
+
+void arm_irq_interrupt_assert(struct interrupt *interrupt);
+void arm_irq_interrupt_deassert(struct interrupt *interrupt);
+
+
+/*
+ *  arm_cpu_new():
+ *
+ *  Create a new ARM cpu object by filling the CPU struct.
+ *  Return 1 on success, 0 if cpu_type_name isn't a valid ARM processor.
+ */
+int arm_cpu_new(struct cpu *cpu, struct memory *mem,
+	struct machine *machine, int cpu_id, char *cpu_type_name)
+{
+	int i, found;
+	struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS;
+
+	/*  Scan the list for this cpu type:  */
+	i = 0; found = -1;
+	while (i >= 0 && cpu_type_defs[i].name != NULL) {
+		if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
+			found = i;
+			break;
+		}
+		i++;
+	}
+	if (found == -1)
+		return 0;
+
+	cpu->run_instr = arm_run_instr;
+	cpu->memory_rw = arm_memory_rw;
+	cpu->update_translation_table = arm_update_translation_table;
+	cpu->invalidate_translation_caches =
+	    arm_invalidate_translation_caches;
+	cpu->invalidate_code_translation = arm_invalidate_code_translation;
+	cpu->translate_v2p = arm_translate_v2p;
+
+	cpu->cd.arm.cpu_type = cpu_type_defs[found];
+	cpu->name            = strdup(cpu->cd.arm.cpu_type.name);
+	cpu->is_32bit        = 1;
+	cpu->byte_order      = EMUL_LITTLE_ENDIAN;
+
+	cpu->vaddr_mask = 0x00000000ffffffffULL;
+
+	cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F;
+	cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32
+	    | ARM_CONTROL_CACHE | ARM_CONTROL_ICACHE | ARM_CONTROL_ALIGN;
+	/*  TODO: default auxctrl contents  */
+
+	if (cpu->machine->prom_emulation) {
+		cpu->cd.arm.cpsr |= ARM_MODE_SVC32;
+		cpu->cd.arm.control |= ARM_CONTROL_S;
+	} else {
+		cpu->cd.arm.cpsr |= ARM_MODE_SVC32;
+		cpu->cd.arm.control |= ARM_CONTROL_R;
+	}
+
+	/*  TODO: Some of these values (iway and dway) aren't used yet:  */
+	cpu->cd.arm.cachetype =
+	      (5 << ARM_CACHETYPE_CLASS_SHIFT)
+	    | (1 << ARM_CACHETYPE_HARVARD_SHIFT)
+	    | ((cpu->cd.arm.cpu_type.dcache_shift - 9) <<
+		ARM_CACHETYPE_DSIZE_SHIFT)
+	    | (5 << ARM_CACHETYPE_DASSOC_SHIFT)		/*  32-way  */
+	    | (2 << ARM_CACHETYPE_DLINE_SHIFT)		/*  8 words/line  */
+	    | ((cpu->cd.arm.cpu_type.icache_shift - 9) <<
+		ARM_CACHETYPE_ISIZE_SHIFT)
+	    | (5 << ARM_CACHETYPE_IASSOC_SHIFT)		/*  32-way  */
+	    | (2 << ARM_CACHETYPE_ILINE_SHIFT);		/*  8 words/line  */
+
+	/*  Coprocessor 15 = the system control coprocessor.  */
+	cpu->cd.arm.coproc[15] = arm_coproc_15;
+
+	/*  Coprocessor 14 for XScale:  */
+	if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE)
+		cpu->cd.arm.coproc[14] = arm_coproc_xscale_14;
+
+	/*
+	 *  NOTE/TODO: Ugly hack for OpenFirmware emulation:
+	 */
+	if (cpu->machine->prom_emulation) {
+		cpu->cd.arm.of_emul_addr = cpu->machine->physical_ram_in_mb
+		    * 1048576 - 8;
+		store_32bit_word(cpu, cpu->cd.arm.of_emul_addr, 0xef8c64be);
+	}
+
+	cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28;
+
+	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
+	for (i=0; i<N_ARM_REGS - 1; i++)
+		CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]);
+
+	CPU_SETTINGS_ADD_REGISTER32("cpsr", cpu->cd.arm.cpsr);
+
+	/*  Register the CPU's "IRQ" and "FIQ" interrupts:  */
+	{
+		struct interrupt templ;
+		char name[50];
+		snprintf(name, sizeof(name), "%s.irq", cpu->path);
+
+                memset(&templ, 0, sizeof(templ));
+                templ.line = 0;
+                templ.name = name;
+                templ.extra = cpu;
+                templ.interrupt_assert = arm_irq_interrupt_assert;
+                templ.interrupt_deassert = arm_irq_interrupt_deassert;
+                interrupt_handler_register(&templ);
+
+		/*  FIQ: TODO  */
+        }
+
+	return 1;
+}
+
+
+/*
+ *  arm_setup_initial_translation_table():
+ *
+ *  When booting kernels (such as OpenBSD or NetBSD) directly, it is assumed
+ *  that the MMU is already enabled by the boot-loader. This function tries
+ *  to emulate that.
+ */
+void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr)
+{
+	unsigned char nothing[16384];
+	unsigned int i, j;
+
+	cpu->cd.arm.control |= ARM_CONTROL_MMU;
+	cpu->translate_v2p = arm_translate_v2p_mmu;
+	cpu->cd.arm.dacr |= 0x00000003;
+	cpu->cd.arm.ttb = ttb_addr;
+
+	memset(nothing, 0, sizeof(nothing));
+	cpu->memory_rw(cpu, cpu->mem, cpu->cd.arm.ttb, nothing,
+	    sizeof(nothing), MEM_WRITE, PHYSICAL | NO_EXCEPTIONS);
+	for (i=0; i<256; i++)
+		for (j=0x0; j<=0xf; j++) {
+			unsigned char descr[4];
+			uint32_t addr = cpu->cd.arm.ttb +
+			    (((j << 28) + (i << 20)) >> 18);
+			uint32_t d = (1048576*i) | 0xc02;
+
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+				descr[0] = d;       descr[1] = d >> 8;
+				descr[2] = d >> 16; descr[3] = d >> 24;
+			} else {
+				descr[3] = d;       descr[2] = d >> 8;
+				descr[1] = d >> 16; descr[0] = d >> 24;
+			}
+			cpu->memory_rw(cpu, cpu->mem, addr, &descr[0],
+			    sizeof(descr), MEM_WRITE, PHYSICAL | NO_EXCEPTIONS);
+		}
+}
+
+
+/*
+ *  arm_translation_table_set_l1():
+ */
+void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
+	uint32_t paddr)
+{
+	unsigned int i, j, vhigh = vaddr >> 28, phigh = paddr >> 28;
+
+	for (i=0; i<256; i++)
+		for (j=vhigh; j<=vhigh; j++) {
+			unsigned char descr[4];
+			uint32_t addr = cpu->cd.arm.ttb +
+			    (((j << 28) + (i << 20)) >> 18);
+			uint32_t d = ((phigh << 28) + 1048576*i) | 0xc02;
+
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+				descr[0] = d;       descr[1] = d >> 8;
+				descr[2] = d >> 16; descr[3] = d >> 24;
+			} else {
+				descr[3] = d;       descr[2] = d >> 8;
+				descr[1] = d >> 16; descr[0] = d >> 24;
+			}
+			cpu->memory_rw(cpu, cpu->mem, addr, &descr[0],
+			    sizeof(descr), MEM_WRITE, PHYSICAL | NO_EXCEPTIONS);
+		}
+}
+
+
+/*
+ *  arm_translation_table_set_l1_b():
+ */
+void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
+	uint32_t paddr)
+{
+	unsigned int i, j, vhigh = vaddr >> 24, phigh = paddr >> 24;
+
+	for (i=0; i<16; i++)
+		for (j=vhigh; j<=vhigh; j++) {
+			unsigned char descr[4];
+			uint32_t addr = cpu->cd.arm.ttb +
+			    (((j << 24) + (i << 20)) >> 18);
+			uint32_t d = ((phigh << 24) + 1048576*i) | 0xc02;
+
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+				descr[0] = d;       descr[1] = d >> 8;
+				descr[2] = d >> 16; descr[3] = d >> 24;
+			} else {
+				descr[3] = d;       descr[2] = d >> 8;
+				descr[1] = d >> 16; descr[0] = d >> 24;
+			}
+			cpu->memory_rw(cpu, cpu->mem, addr, &descr[0],
+			    sizeof(descr), MEM_WRITE, PHYSICAL | NO_EXCEPTIONS);
+		}
+}
+
+
+/*
+ *  arm_cpu_dumpinfo():
+ */
+void arm_cpu_dumpinfo(struct cpu *cpu, bool verbose)
+{
+	struct arm_cpu_type_def *ct = &cpu->cd.arm.cpu_type;
+
+	debugmsg(SUBSYS_MACHINE, "cpu", VERBOSITY_INFO, "%s (I+D = %i+%i KB)",
+	    cpu->name,
+	    (1 << ct->icache_shift) / 1024,
+	    (1 << ct->dcache_shift) / 1024);
+}
+
+
+/*
+ *  arm_cpu_list_available_types():
+ *
+ *  Print a list of available ARM CPU types.
+ */
+void arm_cpu_list_available_types(void)
+{
+	int i, j;
+	struct arm_cpu_type_def tdefs[] = ARM_CPU_TYPE_DEFS;
+
+	i = 0;
+	while (tdefs[i].name != NULL) {
+		debug("%s", tdefs[i].name);
+		for (j=13 - strlen(tdefs[i].name); j>0; j--)
+			debug(" ");
+		i++;
+		if ((i % 5) == 0 || tdefs[i].name == NULL)
+			debug("\n");
+	}
+}
+
+
+/*
+ *  arm_cpu_register_dump():
+ *
+ *  Dump cpu registers in a relatively readable format.
+ *  
+ *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
+ *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
+ */
+void arm_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
+{
+	char *symbol;
+	uint64_t offset;
+	int mode = cpu->cd.arm.cpsr & ARM_FLAG_MODE;
+	int i, x = cpu->cpu_id;
+
+	cpu->cd.arm.cpsr &= 0x0fffffff;
+	cpu->cd.arm.cpsr |= (cpu->cd.arm.flags << 28);
+
+	if (gprs) {
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    cpu->pc, &offset);
+		debug("cpu%i:  cpsr = ", x);
+		debug("%s%s%s%s%s%s%s%s%s%s%s",
+		    (cpu->cd.arm.cpsr & ARM_FLAG_N)? "N" : "n",
+		    (cpu->cd.arm.cpsr & ARM_FLAG_Z)? "Z" : "z",
+		    (cpu->cd.arm.cpsr & ARM_FLAG_C)? "C" : "c",
+		    (cpu->cd.arm.cpsr & ARM_FLAG_V)? "V" : "v",
+		    (cpu->cd.arm.cpsr & ARM_FLAG_Q)? "Q" : "q",
+		    (cpu->cd.arm.cpsr & ARM_FLAG_J)? "J" : "j",
+		    (cpu->cd.arm.cpsr & ARM_FLAG_E)? "E" : "e",
+		    (cpu->cd.arm.cpsr & ARM_FLAG_A)? "A" : "a",
+		    (cpu->cd.arm.cpsr & ARM_FLAG_I)? "I" : "i",
+		    (cpu->cd.arm.cpsr & ARM_FLAG_F)? "F" : "f",
+    		    (cpu->cd.arm.cpsr & ARM_FLAG_T)? "T" : "t");
+		if (mode < ARM_MODE_USR32)
+			debug("   pc =  0x%07x", (int)(cpu->pc & 0x03ffffff));
+		else
+			debug("   pc = 0x%08x", (int)cpu->pc);
+
+		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
+
+		for (i=0; i<N_ARM_REGS; i++) {
+			if ((i % 4) == 0)
+				debug("cpu%i:", x);
+			if (i != ARM_PC)
+				debug("  %s = 0x%08x", arm_regname[i],
+				    (int)cpu->cd.arm.r[i]);
+			if ((i % 4) == 3)
+				debug("\n");
+		}
+	}
+
+	if (coprocs & 1) {
+		int m = cpu->cd.arm.cpsr & ARM_FLAG_MODE;
+		debug("cpu%i:  cpsr = 0x%08x (", x, cpu->cd.arm.cpsr);
+		switch (m) {
+		case ARM_MODE_USR32:
+			debug("USR32)\n"); break;
+		case ARM_MODE_SYS32:
+			debug("SYS32)\n"); break;
+		case ARM_MODE_FIQ32:
+			debug("FIQ32)\n"); break;
+		case ARM_MODE_IRQ32:
+			debug("IRQ32)\n"); break;
+		case ARM_MODE_SVC32:
+			debug("SVC32)\n"); break;
+		case ARM_MODE_ABT32:
+			debug("ABT32)\n"); break;
+		case ARM_MODE_UND32:
+			debug("UND32)\n"); break;
+		default:debug("unimplemented)\n");
+		}
+
+		if (m != ARM_MODE_USR32 && m != ARM_MODE_SYS32) {
+			debug("cpu%i:  usr r8-14:", x);
+			for (i=0; i<7; i++)
+				debug(" %08x", cpu->cd.arm.default_r8_r14[i]);
+			debug("\n");
+		}
+
+		if (m != ARM_MODE_FIQ32) {
+			debug("cpu%i:  fiq r8-14:", x);
+			for (i=0; i<7; i++)
+				debug(" %08x", cpu->cd.arm.fiq_r8_r14[i]);
+			debug("\n");
+		}
+
+		if (m != ARM_MODE_IRQ32) {
+			debug("cpu%i:  irq r13-14:", x);
+			for (i=0; i<2; i++)
+				debug(" %08x", cpu->cd.arm.irq_r13_r14[i]);
+			debug("\n");
+		}
+
+		if (m != ARM_MODE_SVC32) {
+			debug("cpu%i:  svc r13-14:", x);
+			for (i=0; i<2; i++)
+				debug(" %08x", cpu->cd.arm.svc_r13_r14[i]);
+			debug("\n");
+		}
+
+		if (m != ARM_MODE_ABT32) {
+			debug("cpu%i:  abt r13-14:", x);
+			for (i=0; i<2; i++)
+				debug(" %08x", cpu->cd.arm.abt_r13_r14[i]);
+			debug("\n");
+		}
+
+		if (m != ARM_MODE_UND32) {
+			debug("cpu%i:  und r13-14:", x);
+			for (i=0; i<2; i++)
+				debug(" %08x", cpu->cd.arm.und_r13_r14[i]);
+			debug("\n");
+		}
+	}
+
+	if (coprocs & 2) {
+		debug("cpu%i:  control = 0x%08x\n", x, cpu->cd.arm.control);
+		debug("cpu%i:      MMU:               %s\n", x,
+		    cpu->cd.arm.control &
+		    ARM_CONTROL_MMU? "enabled" : "disabled");
+		debug("cpu%i:      alignment checks:  %s\n", x,
+		    cpu->cd.arm.control &
+		    ARM_CONTROL_ALIGN? "enabled" : "disabled");
+		debug("cpu%i:      [data] cache:      %s\n", x,
+		    cpu->cd.arm.control &
+		    ARM_CONTROL_CACHE? "enabled" : "disabled");
+		debug("cpu%i:      instruction cache: %s\n", x,
+		    cpu->cd.arm.control &
+		    ARM_CONTROL_ICACHE? "enabled" : "disabled");
+		debug("cpu%i:      write buffer:      %s\n", x,
+		    cpu->cd.arm.control &
+		    ARM_CONTROL_WBUFFER? "enabled" : "disabled");
+		debug("cpu%i:      prog32:            %s\n", x,
+		    cpu->cd.arm.control &
+		    ARM_CONTROL_PROG32? "yes" : "no (using prog26)");
+		debug("cpu%i:      data32:            %s\n", x,
+		    cpu->cd.arm.control &
+		    ARM_CONTROL_DATA32? "yes" : "no (using data26)");
+		debug("cpu%i:      endianness:        %s\n", x,
+		    cpu->cd.arm.control &
+		    ARM_CONTROL_BIG? "big endian" : "little endian");
+		debug("cpu%i:      high vectors:      %s\n", x,
+		    cpu->cd.arm.control &
+		    ARM_CONTROL_V? "yes (0xffff0000)" : "no");
+
+		/*  TODO: auxctrl on which CPU types?  */
+		if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) {
+			debug("cpu%i:  auxctrl = 0x%08x\n", x,
+			    cpu->cd.arm.auxctrl);
+			debug("cpu%i:      minidata cache attr = 0x%x\n", x,
+			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_MD)
+			    >> ARM_AUXCTRL_MD_SHIFT);
+			debug("cpu%i:      page table memory attr: %i\n", x,
+			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_P)? 1 : 0);
+			debug("cpu%i:      write buffer coalescing: %s\n", x,
+			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_K)?
+			    "disabled" : "enabled");
+		}
+
+		debug("cpu%i:  ttb = 0x%08x  dacr = 0x%08x\n", x,
+		    cpu->cd.arm.ttb, cpu->cd.arm.dacr);
+		debug("cpu%i:  fsr = 0x%08x  far = 0x%08x\n", x,
+		    cpu->cd.arm.fsr, cpu->cd.arm.far);
+	}
+}
+
+
+/*
+ *  arm_save_register_bank():
+ */
+void arm_save_register_bank(struct cpu *cpu)
+{
+	/*  Save away current registers:  */
+	switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
+	case ARM_MODE_USR32:
+	case ARM_MODE_SYS32:
+		memcpy(cpu->cd.arm.default_r8_r14,
+		    &cpu->cd.arm.r[8], sizeof(uint32_t) * 7);
+		break;
+	case ARM_MODE_FIQ32:
+		memcpy(cpu->cd.arm.fiq_r8_r14,
+		    &cpu->cd.arm.r[8], sizeof(uint32_t) * 7);
+		break;
+	case ARM_MODE_IRQ32:
+		memcpy(cpu->cd.arm.default_r8_r14,
+		    &cpu->cd.arm.r[8], sizeof(uint32_t) * 5);
+		cpu->cd.arm.irq_r13_r14[0] = cpu->cd.arm.r[13];
+		cpu->cd.arm.irq_r13_r14[1] = cpu->cd.arm.r[14];
+		break;
+	case ARM_MODE_SVC32:
+		memcpy(cpu->cd.arm.default_r8_r14,
+		    &cpu->cd.arm.r[8], sizeof(uint32_t) * 5);
+		cpu->cd.arm.svc_r13_r14[0] = cpu->cd.arm.r[13];
+		cpu->cd.arm.svc_r13_r14[1] = cpu->cd.arm.r[14];
+		break;
+	case ARM_MODE_ABT32:
+		memcpy(cpu->cd.arm.default_r8_r14,
+		    &cpu->cd.arm.r[8], sizeof(uint32_t) * 5);
+		cpu->cd.arm.abt_r13_r14[0] = cpu->cd.arm.r[13];
+		cpu->cd.arm.abt_r13_r14[1] = cpu->cd.arm.r[14];
+		break;
+	case ARM_MODE_UND32:
+		memcpy(cpu->cd.arm.default_r8_r14,
+		    &cpu->cd.arm.r[8], sizeof(uint32_t) * 5);
+		cpu->cd.arm.und_r13_r14[0] = cpu->cd.arm.r[13];
+		cpu->cd.arm.und_r13_r14[1] = cpu->cd.arm.r[14];
+		break;
+	default:fatal("arm_save_register_bank: unimplemented mode %i\n",
+		    cpu->cd.arm.cpsr & ARM_FLAG_MODE);
+		exit(1);
+	}
+}
+
+
+/*
+ *  arm_load_register_bank():
+ */
+void arm_load_register_bank(struct cpu *cpu)
+{
+	/*  Load new registers:  */
+	switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
+	case ARM_MODE_USR32:
+	case ARM_MODE_SYS32:
+		memcpy(&cpu->cd.arm.r[8],
+		    cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 7);
+		break;
+	case ARM_MODE_FIQ32:
+		memcpy(&cpu->cd.arm.r[8], cpu->cd.arm.fiq_r8_r14,
+		    sizeof(uint32_t) * 7);
+		break;
+	case ARM_MODE_IRQ32:
+		memcpy(&cpu->cd.arm.r[8],
+		    cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5);
+		cpu->cd.arm.r[13] = cpu->cd.arm.irq_r13_r14[0];
+		cpu->cd.arm.r[14] = cpu->cd.arm.irq_r13_r14[1];
+		break;
+	case ARM_MODE_SVC32:
+		memcpy(&cpu->cd.arm.r[8],
+		    cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5);
+		cpu->cd.arm.r[13] = cpu->cd.arm.svc_r13_r14[0];
+		cpu->cd.arm.r[14] = cpu->cd.arm.svc_r13_r14[1];
+		break;
+	case ARM_MODE_ABT32:
+		memcpy(&cpu->cd.arm.r[8],
+		    cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5);
+		cpu->cd.arm.r[13] = cpu->cd.arm.abt_r13_r14[0];
+		cpu->cd.arm.r[14] = cpu->cd.arm.abt_r13_r14[1];
+		break;
+	case ARM_MODE_UND32:
+		memcpy(&cpu->cd.arm.r[8],
+		    cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5);
+		cpu->cd.arm.r[13] = cpu->cd.arm.und_r13_r14[0];
+		cpu->cd.arm.r[14] = cpu->cd.arm.und_r13_r14[1];
+		break;
+	default:fatal("arm_load_register_bank: unimplemented mode %i\n",
+		    cpu->cd.arm.cpsr & ARM_FLAG_MODE);
+		exit(1);
+	}
+}
+
+
+/*
+ *  arm_exception():
+ */
+void arm_exception(struct cpu *cpu, int exception_nr)
+{
+	int oldmode, newmode;
+	uint32_t retaddr;
+
+	if (exception_nr < 0 || exception_nr >= N_ARM_EXCEPTIONS) {
+		fatal("arm_exception(): exception_nr = %i\n", exception_nr);
+		exit(1);
+	}
+
+	retaddr = cpu->pc;
+
+	if (!quiet_mode) {
+		debug("[ arm_exception(): ");
+		switch (exception_nr) {
+		case ARM_EXCEPTION_RESET:
+			fatal("RESET: TODO");
+			break;
+		case ARM_EXCEPTION_UND:
+			debug("UNDEFINED");
+			break;
+		case ARM_EXCEPTION_SWI:
+			debug("SWI");
+			break;
+		case ARM_EXCEPTION_PREF_ABT:
+			debug("PREFETCH ABORT");
+			break;
+		case ARM_EXCEPTION_IRQ:
+			debug("IRQ");
+			break;
+		case ARM_EXCEPTION_FIQ:
+			debug("FIQ");
+			break;
+		case ARM_EXCEPTION_DATA_ABT:
+			debug("DATA ABORT, far=0x%08x fsr=0x%02x",
+			    cpu->cd.arm.far, cpu->cd.arm.fsr);
+			break;
+		}
+		debug(" ]\n");
+	}
+
+	switch (exception_nr) {
+	case ARM_EXCEPTION_RESET:
+		cpu->running = 0;
+		fatal("ARM RESET: TODO");
+		exit(1);
+	case ARM_EXCEPTION_DATA_ABT:
+		retaddr += 4;
+		break;
+	}
+
+	retaddr += (cpu->cd.arm.cpsr & ARM_FLAG_T ? 2 : 4);
+
+	arm_save_register_bank(cpu);
+
+	cpu->cd.arm.cpsr &= 0x0fffffff;
+	cpu->cd.arm.cpsr |= (cpu->cd.arm.flags << 28);
+
+	switch (arm_exception_to_mode[exception_nr]) {
+	case ARM_MODE_SVC32:
+		cpu->cd.arm.spsr_svc = cpu->cd.arm.cpsr; break;
+	case ARM_MODE_ABT32:
+		cpu->cd.arm.spsr_abt = cpu->cd.arm.cpsr; break;
+	case ARM_MODE_UND32:
+		cpu->cd.arm.spsr_und = cpu->cd.arm.cpsr; break;
+	case ARM_MODE_IRQ32:
+		cpu->cd.arm.spsr_irq = cpu->cd.arm.cpsr; break;
+	case ARM_MODE_FIQ32:
+		cpu->cd.arm.spsr_fiq = cpu->cd.arm.cpsr; break;
+	default:fatal("arm_exception(): unimplemented exception nr\n");
+		exit(1);
+	}
+
+	/*
+	 *  Disable Thumb mode (because exception handlers always execute
+	 *  in ARM mode), set the exception mode, and disable interrupts:
+	 */
+	cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
+
+	oldmode = cpu->cd.arm.cpsr & ARM_FLAG_MODE;
+
+	cpu->cd.arm.cpsr &= ~ARM_FLAG_MODE;
+	cpu->cd.arm.cpsr |= arm_exception_to_mode[exception_nr];
+
+	/*
+	 *  Usually, an exception should change modes (so that saved status
+	 *  bits don't get lost). However, Linux on ARM seems to use floating
+	 *  point instructions in the kernel (!), and it emulates those using
+	 *  its own fp emulation code. This leads to a situation where we
+	 *  sometimes change from SVC32 to SVC32.
+	 */
+	newmode = cpu->cd.arm.cpsr & ARM_FLAG_MODE;
+	if (oldmode == newmode && oldmode != ARM_MODE_SVC32) {
+		fatal("[ WARNING! Exception caused no mode change? "
+		    "mode 0x%02x (pc=0x%x) ]\n", newmode, (int)cpu->pc);
+		/*  exit(1);  */
+	}
+
+	cpu->cd.arm.cpsr |= ARM_FLAG_I;
+	if (exception_nr == ARM_EXCEPTION_RESET ||
+	    exception_nr == ARM_EXCEPTION_FIQ)
+		cpu->cd.arm.cpsr |= ARM_FLAG_F;
+
+	/*  Load the new register bank, if we switched:  */
+	arm_load_register_bank(cpu);
+
+	/*
+	 *  Set the return address and new PC.
+	 *
+	 *  NOTE: r[ARM_PC] is also set; see cpu_arm_instr_loadstore.c for
+	 *  details. (If an exception occurs during a load into the pc
+	 *  register, the code in that file assumes that the r[ARM_PC]
+	 *  was changed to the address of the exception handler.)
+	 */
+	cpu->cd.arm.r[ARM_LR] = retaddr;
+	cpu->pc = cpu->cd.arm.r[ARM_PC] = exception_nr * 4 +
+	    ((cpu->cd.arm.control & ARM_CONTROL_V)? 0xffff0000 : 0);
+	quick_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  arm_cpu_tlbdump():
+ *
+ *  Called from the debugger to dump the TLB in a readable format.
+ *
+ *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
+ *  just dumped.
+ */
+void arm_cpu_tlbdump(struct cpu *cpu, int rawflag)
+{
+}
+
+
+/*
+ *  arm_irq_interrupt_assert():
+ *  arm_irq_interrupt_deassert():
+ */
+void arm_irq_interrupt_assert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.arm.irq_asserted = 1;
+}
+void arm_irq_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.arm.irq_asserted = 0;
+}
+
+
+/*
+ *  arm_cpu_disassemble_instr_thumb():
+ *
+ *  Like arm_cpu_disassemble_instr below, but for THUMB encodings.
+ *  Note that the disassbmly uses regular ARM mnemonics, not "THUMB
+ *  assembly language".
+ */                     
+int arm_cpu_disassemble_instr_thumb(struct cpu *cpu, unsigned char *ib,
+        int running, uint64_t dumpaddr)
+{
+	uint16_t iw;
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iw = ib[0] + (ib[1]<<8);
+	else
+		iw = ib[1] + (ib[0]<<8);
+	debug("%04x    \t", (int)iw);
+
+	int main_opcode = (iw >> 12) & 15;
+	int r6 = (iw >> 6) & 7;
+	int rs_rb = (iw >> 3) & 7;
+	int rd = iw & 7;
+	int offset5 = (iw >> 6) & 0x1f;
+	int b_bit = (iw >> 12) & 1;
+	int l_bit = (iw >> 11) & 1;
+	int addsub_op = (iw >> 9) & 1;
+	int addsub_immediate = (iw >> 10) & 1;
+	int op11 = (iw >> 11) & 3;
+	int op10 = (iw >> 10) & 3;
+	int rd8 = (iw >> 8) & 7;
+	int op8 = (iw >> 8) & 3;
+	int h1 = (iw >> 7) & 1;
+	int h2 = (iw >> 6) & 1;
+	int condition_code = (iw >> 8) & 15;
+	const char* condition = arm_condition_string[condition_code];
+	const char* symbol;
+	uint64_t offset;
+	int tmp;
+	uint32_t tmp32;
+	
+	switch (main_opcode)
+	{
+	case 0x0:
+	case 0x1:
+		if (op11 <= 2) {
+			// Move shifted register.
+			debug("%ss\tr%i,r%i,#%i\n",
+				op11 & 1 ? "lsr" : (op11 & 2 ? "asr" : "lsl"),
+				rd,
+				rs_rb,				
+				offset5);
+		} else {
+			// Add/subtract.
+			debug("%s\tr%i,r%i,%s%i\n",
+				addsub_op ? "subs" : "adds",
+				rd,
+				rs_rb,
+				addsub_immediate ? "#" : "r",
+				r6);
+		}
+		break;
+
+	case 0x2:
+	case 0x3:
+		// Move/compare/add/subtract immediate.
+		rd = (iw >> 8) & 7;
+		if (op11 & 2) {
+			debug("%s\tr%i,r%i,#%i\n",
+				op11 & 1 ? "subs" : "adds",
+				rd, rd,
+				iw & 0xff);
+		} else {
+			debug("%s\tr%i,#%i\n",
+				op11 & 1 ? "cmp" : "movs",
+				rd,
+				iw & 0xff);
+		}
+		break;
+
+	case 0x4:
+		switch (op10) {
+		case 0:
+			// ALU operations.
+			debug("%s\t%s,%s",
+				arm_thumb_dpiname[(iw >> 6) & 15],
+				arm_regname[rd],
+				arm_regname[rs_rb]);
+			
+			if (running) {
+				debug("\t\t; %s = 0x%x", arm_regname[rd], cpu->cd.arm.r[rd]);
+				debug(", %s = 0x%x", arm_regname[rs_rb], cpu->cd.arm.r[rs_rb]);
+			}
+
+			debug("\n");
+			break;
+
+		case 1:
+			// Hi register operations / branch exchange.
+			if (h1)
+				rd += 8;
+			if (h2)
+				rs_rb += 8;
+			switch (op8) {
+			case 0:
+			case 1:
+			case 2:
+				if (h1 == 0 && h2 == 0) {
+					debug("TODO main_opcode = %i, op10 = %i, h1 AND h2 are zero?!\n", main_opcode, op10);
+				} else {
+					if (op8 == 0)
+						debug("add\tr%i,r%i,r%i\n", rd, rd, rs_rb);
+					else {
+						if (op8 == 2 && rd == rs_rb)
+							debug("nop\n");	// mov rX,rX
+						else {
+							debug("%s\t%s,%s",
+							    op8 == 1 ? "cmp" : "mov",
+							    	arm_regname[rd],
+							    	arm_regname[rs_rb]);
+							if (running) {
+								debug("\t\t; %s = 0x%x", arm_regname[rd], cpu->cd.arm.r[rd]);
+								debug(", %s = 0x%x", arm_regname[rs_rb], cpu->cd.arm.r[rs_rb]);
+							}
+							debug("\n");
+						}
+					}
+				}
+				break;
+			case 3:
+				if (h1 == 1) {
+					debug("TODO main_opcode = %i, op10 = %i, h1 set for BX?!\n", main_opcode, op10);
+				} else {
+					debug("bx\t%s\n", arm_regname[rs_rb]);
+
+					// Extra newline when returning from function.
+					// if (running && rs_rb == ARM_LR)
+					//	debug("\n");
+				}
+				break;
+			}
+			break;
+
+		case 2:
+		case 3:
+			// PC-relative load.
+			debug("ldr\t%s,[pc,#%i]\t; ",
+				arm_regname[rd8],
+				(iw & 0xff) * 4);
+
+			// Is this address calculation correct?
+			// It works with real code, but is not the same as that of
+			// http://engold.ui.ac.ir/~nikmehr/Appendix_B2.pdf
+			tmp = (dumpaddr & ~3) + 4 + (iw & 0xff) * 4;
+			debug("0x%x", (int)tmp);
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    tmp, &offset);
+			if (symbol != NULL)
+				debug(" <%s>", symbol);
+			debug("\n");
+			break;
+		}
+		break;
+
+	case 0x5:
+		// Load/Store with register offset.
+		switch ((iw >> 9) & 7) {
+		case 0:	debug("str"); break;
+		case 1:	debug("strh"); break;
+		case 2:	debug("strb"); break;
+		case 3:	debug("ldrsb"); break;
+		case 4:	debug("ldr"); break;
+		case 5:	debug("ldrh"); break;
+		case 6:	debug("ldrb"); break;
+		case 7:	debug("ldrsh"); break;
+		}
+		debug("\t%s,[%s,%s]\n",
+			arm_regname[rd],
+			arm_regname[rs_rb],
+			arm_regname[r6]);
+		break;
+		
+	case 0x6:
+	case 0x7:
+		// Load/Store with immediate offset.
+		debug("%s%s\tr%i,[r%i,#%i]\n",
+			l_bit ? "ldr" : "str",
+			b_bit ? "b" : "",
+			rd,
+			rs_rb,
+			offset5 * (b_bit ? sizeof(uint8_t) : sizeof(uint32_t)));
+		break;
+
+	case 0x8:
+		// Load/Store halfword.
+		debug("%sh\tr%i,[r%i,#%i]\n",
+			l_bit ? "ldr" : "str",
+			rd,
+			rs_rb,
+			offset5 * sizeof(uint16_t));
+		break;
+
+	case 0x9:
+		// Load/Store stack pointer relative.
+		debug("%s\t%s,[sp,#%i]\n",
+			l_bit ? "ldr" : "str",
+			arm_regname[rd8],
+			4 * (iw & 0xff));
+		break;
+
+	case 0xa:
+		// add rx, sp or pc plus imm
+		debug("add\t%s,%s,#%i\n",
+			arm_regname[rd8],
+			iw & 0x0800 ? "sp" : "pc",
+			4 * (iw & 0xff));
+		break;
+
+	case 0xb:
+		/*  Bits 11..8:  */
+		switch (condition_code) {
+		case 0x0:
+			tmp = (iw & 0x7f) << 2;
+			debug(iw & 0x80 ? "sub" : "add");
+			debug("\tsp,#%i\n", tmp);
+			break;
+		case 0x4:
+		case 0x5:
+		case 0xc:
+		case 0xd:
+			debug(condition_code & 8 ? "pop" : "push");
+			debug("\t{");
+			for (tmp=0; tmp<8; ++tmp) {
+				if (iw & (1 << tmp))
+					debug("%s,", arm_regname[tmp]);
+			}
+			if (condition_code & 1) {			
+				if (condition_code & 8)
+					debug("pc");
+				else
+					debug("lr");
+			}
+			debug("}\n");
+
+			// Extra newline when returning from function.
+			// if (running && (condition_code & 8) && (condition_code & 1))
+			//	debug("\n");
+			break;
+		default:
+			debug("TODO: unimplemented opcode 0x%x,0x%x\n", main_opcode, condition_code);
+		}
+		break;
+		
+	case 0xd:
+		if (condition_code < 0xe) {
+			// Conditional branch.
+			debug("b%s\t", condition);
+			tmp = (iw & 0xff) << 1;
+			if (tmp & 0x100)
+				tmp |= 0xfffffe00;
+			tmp = (int32_t)(dumpaddr + 4 + tmp);
+			debug("0x%x", (int)tmp);
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    tmp, &offset);
+			if (symbol != NULL)
+				debug(" \t<%s>", symbol);
+			debug("\n");
+		} else if (condition_code == 0xf) {
+			debug("swi\t#0x%x\n", iw & 0xff);
+		} else {
+			debug("UNIMPLEMENTED\n");
+		}
+		break;
+
+	case 0xe:
+		// Unconditional branch.
+		if (iw & 0x0800) {
+			uint32_t addr = (dumpaddr + 4 + (cpu->cd.arm.tmp_branch + (((iw >> 1) & 0x3ff) << 2))) & ~3;
+			
+			debug("blx\t");
+			if (running) {
+				debug("0x%x", addr);
+				symbol = get_symbol_name(&cpu->machine->symbol_context, addr, &offset);
+				if (symbol != NULL)
+					debug(" \t<%s>", symbol);
+				debug("\n");
+			} else
+				debug("offset depending on prefix at runtime\n");
+		} else {
+			tmp = (iw & 0x7ff) << 1;
+			if (tmp & 0x800)
+				tmp |= 0xfffff000;
+			tmp = (int32_t)(dumpaddr + 4 + tmp);
+			debug("b\t0x%x", (int)tmp);
+			symbol = get_symbol_name(&cpu->machine->symbol_context, tmp, &offset);
+			if (symbol != NULL)
+				debug(" \t<%s>", symbol);
+			debug("\n");
+		}
+		break;
+
+	case 0xf:
+		if (iw & 0x0800) {
+			uint32_t addr = (dumpaddr + 2 + (cpu->cd.arm.tmp_branch + ((iw & 0x7ff) << 1)));
+			
+			debug("bl\t");
+			if (running) {
+				debug("0x%x", addr);
+				symbol = get_symbol_name(&cpu->machine->symbol_context, addr, &offset);
+				if (symbol != NULL)
+					debug(" \t<%s>", symbol);
+				debug("\n");
+			} else
+				debug("offset depending on prefix at runtime\n");
+		} else {
+			tmp32 = iw & 0x07ff;
+			if (tmp32 & 0x0400)
+				tmp32 |= 0xfffff800;
+			tmp32 <<= 12;
+			debug("bprefix\t0x%x\n", tmp32);
+		}
+		break;
+
+	default:
+		debug("TODO: unimplemented opcode 0x%x\n", main_opcode);
+	}
+
+	return sizeof(uint16_t);
+}
+
+
+/*
+ *  arm_cpu_interpret_thumb_SLOW():
+ *
+ *  Slow interpretation of THUMB instructions.
+ *
+ *  TODO: Either replace this with dyntrans or
+ *  implement ARM (including THUMB) in the new framework. :-)
+ *  For now, this is better than nothing.
+ */
+int arm_cpu_interpret_thumb_SLOW(struct cpu *cpu)
+{
+	uint16_t iw;
+	uint8_t ib[sizeof(uint16_t)];
+	uint32_t addr = cpu->pc & ~1;
+
+	if (!(cpu->pc & 1) || !(cpu->cd.arm.cpsr & ARM_FLAG_T)) {
+		fatal("arm_cpu_interpret_thumb_SLOW called when not in "
+			"THUMB mode?\n");
+		cpu->running = 0;
+		return 0;
+	}
+
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, &ib[0],
+			sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
+		fatal("arm_cpu_interpret_thumb_SLOW(): could not read "
+			"the instruction\n");
+		cpu->running = 0;
+		return 0;
+	}
+	
+	if (cpu->machine->instruction_trace) {
+		uint64_t offset;
+		char* symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    addr, &offset);
+		if (symbol != NULL && offset == 0)
+			debug("<%s>\n", symbol);
+
+		if (cpu->machine->ncpus > 1)
+			debug("cpu%i:\t", cpu->cpu_id);
+
+		debug("%08x:  ", (int)addr & ~1);
+		arm_cpu_disassemble_instr_thumb(cpu, ib, 1, cpu->pc);
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iw = ib[0] + (ib[1]<<8);
+	else
+		iw = ib[1] + (ib[0]<<8);
+
+	cpu->ninstrs ++;
+
+	int main_opcode = (iw >> 12) & 15;
+	int condition_code = (iw >> 8) & 15;
+	int op10 = (iw >> 10) & 3;
+	int op11_8 = (iw >> 8) & 15;
+	int rd8 = (iw >> 8) & 7;
+	int r6 = (iw >> 6) & 7;
+	int r3 = (iw >> 3) & 7;
+	int rd = (iw >> 0) & 7;
+	int hd = (iw >> 7) & 1;
+	int hm = (iw >> 6) & 1;
+	int imm6 = (iw >> 6) & 31;
+	uint8_t word[sizeof(uint32_t)];
+	uint32_t tmp;
+	int t, len, isLoad;
+
+	switch (main_opcode)
+	{
+	case 0x0:
+		if (iw & 0x0800) {
+			// lsr
+			tmp = cpu->cd.arm.r[r3];
+			if (imm6 > 1)
+				tmp >>= (imm6 - 1);
+			cpu->cd.arm.r[rd] = cpu->cd.arm.r[r3] >> imm6;
+			tmp &= 1;
+		} else {
+			// lsl
+			tmp = cpu->cd.arm.r[r3];
+			if (imm6 > 1)
+				tmp <<= (imm6 - 1);
+			cpu->cd.arm.r[rd] = cpu->cd.arm.r[r3] << imm6;
+			tmp >>= 31;
+		}
+		cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+		if (cpu->cd.arm.r[rd] == 0)
+			cpu->cd.arm.flags |= ARM_F_Z;
+		if ((int32_t)cpu->cd.arm.r[rd] < 0)
+			cpu->cd.arm.flags |= ARM_F_N;
+		if (imm6 != 0) {
+			// tmp is "last bit shifted out"
+			cpu->cd.arm.flags &= ~ARM_F_C;
+			if (tmp)
+				cpu->cd.arm.flags |= ARM_F_C;
+		}
+		break;
+
+	case 0x1:
+		if (!(iw & 0x0800)) {
+			// asr
+			tmp = cpu->cd.arm.r[r3];
+			if (imm6 > 1)
+				tmp = (int32_t)tmp >> (imm6 - 1);
+			cpu->cd.arm.r[rd] = (int32_t)cpu->cd.arm.r[r3] >> imm6;
+			tmp &= 1;
+			cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+			if (cpu->cd.arm.r[rd8] == 0)
+				cpu->cd.arm.flags |= ARM_F_Z;
+			if ((int32_t)cpu->cd.arm.r[rd8] < 0)
+				cpu->cd.arm.flags |= ARM_F_N;
+			if (imm6 != 0) {
+				// tmp is "last bit shifted out"
+				cpu->cd.arm.flags &= ~ARM_F_C;
+				if (tmp)
+					cpu->cd.arm.flags |= ARM_F_C;
+			}
+		} else {
+			// add or sub
+			int isSub = iw & 0x0200;
+			int isImm3 = iw & 0x0400;
+			uint64_t old = cpu->cd.arm.r[r3];
+			uint64_t tmp64 = isImm3 ? (uint64_t)r6 : cpu->cd.arm.r[r6];
+			tmp64 = (uint32_t)(isSub ? -tmp64 : tmp64);
+			uint64_t result = old + tmp64;
+			cpu->cd.arm.r[rd] = result;
+			cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N | ARM_F_C | ARM_F_V);
+			if (result == 0)
+				cpu->cd.arm.flags |= ARM_F_Z;
+			if ((int32_t)result < 0)
+				cpu->cd.arm.flags |= ARM_F_N;
+			if (result & 0x100000000ULL)
+				cpu->cd.arm.flags |= ARM_F_C;
+			if (result & 0x80000000) {
+				if ((tmp64 & 0x80000000) == 0 && (old & 0x80000000) == 0)
+					cpu->cd.arm.flags |= ARM_F_V;
+			} else {
+				if ((tmp64 & 0x80000000) != 0 && (old & 0x80000000) != 0)
+					cpu->cd.arm.flags |= ARM_F_V;
+			}
+		}
+		break;
+
+	case 0x2:
+		// movs or cmp
+		if (iw & 0x0800) {
+			uint64_t old = cpu->cd.arm.r[rd8];
+			uint64_t tmp64 = (uint32_t)(-(iw & 0xff));
+			uint64_t result = old + tmp64;
+			cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N | ARM_F_C | ARM_F_V);
+			if (result == 0)
+				cpu->cd.arm.flags |= ARM_F_Z;
+			if ((int32_t)result < 0)
+				cpu->cd.arm.flags |= ARM_F_N;
+			if (result & 0x100000000ULL)
+				cpu->cd.arm.flags |= ARM_F_C;
+			if (result & 0x80000000) {
+				if ((tmp64 & 0x80000000) == 0 && (old & 0x80000000) == 0)
+					cpu->cd.arm.flags |= ARM_F_V;
+			} else {
+				if ((tmp64 & 0x80000000) != 0 && (old & 0x80000000) != 0)
+					cpu->cd.arm.flags |= ARM_F_V;
+			}
+		} else {
+			cpu->cd.arm.r[rd8] = iw & 0xff;
+			cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+			if (cpu->cd.arm.r[rd8] == 0)
+				cpu->cd.arm.flags |= ARM_F_Z;
+		}
+		break;
+
+	case 0x3:
+		// adds or sub
+		{
+			uint64_t old = cpu->cd.arm.r[rd8];
+			uint64_t tmp64 = iw & 0xff;
+			
+			if (iw & 0x0800)
+				tmp64 = (uint32_t)(-tmp64);
+
+			uint64_t result = old + tmp64;
+			cpu->cd.arm.r[rd8] = result;
+
+			cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N | ARM_F_C | ARM_F_V);
+			if (result == 0)
+				cpu->cd.arm.flags |= ARM_F_Z;
+			if ((int32_t)result < 0)
+				cpu->cd.arm.flags |= ARM_F_N;
+			if (result & 0x100000000ULL)
+				cpu->cd.arm.flags |= ARM_F_C;
+			if (result & 0x80000000) {
+				if ((tmp64 & 0x80000000) == 0 && (old & 0x80000000) == 0)
+					cpu->cd.arm.flags |= ARM_F_V;
+			} else {
+				if ((tmp64 & 0x80000000) != 0 && (old & 0x80000000) != 0)
+					cpu->cd.arm.flags |= ARM_F_V;
+			}
+		}
+		break;
+
+	case 0x4:
+		switch (op10) {
+		case 0:
+			// "DPIs":
+			switch ((iw >> 6) & 15) {
+			case 0:// ands
+				cpu->cd.arm.r[rd] &= cpu->cd.arm.r[r3];
+				cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+				if (cpu->cd.arm.r[rd] == 0)
+					cpu->cd.arm.flags |= ARM_F_Z;
+				if ((int32_t)cpu->cd.arm.r[rd] < 0)
+					cpu->cd.arm.flags |= ARM_F_N;
+				break;
+			case 1:// eors
+				cpu->cd.arm.r[rd] ^= cpu->cd.arm.r[r3];
+				cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+				if (cpu->cd.arm.r[rd] == 0)
+					cpu->cd.arm.flags |= ARM_F_Z;
+				if ((int32_t)cpu->cd.arm.r[rd] < 0)
+					cpu->cd.arm.flags |= ARM_F_N;
+				break;
+			case 7:// rors
+				{
+					int amount = cpu->cd.arm.r[r3] & 0xff;
+					for (int i = 0; i < (amount & 31); ++i) {
+						int c = cpu->cd.arm.r[rd] & 1;
+						cpu->cd.arm.r[rd] >>= 1;
+						cpu->cd.arm.flags &= ~ARM_F_C;
+						if (c) {
+							cpu->cd.arm.flags |= ARM_F_C;
+							cpu->cd.arm.r[rd] |= 0x80000000;
+						}
+					}
+					
+					// Rotating right by e.g. 32 means that the C flag
+					// should be updated, but the register isn't
+					// really rotated.
+					if (amount != 0 && (amount & 31) == 0) {
+						cpu->cd.arm.flags &= ~ARM_F_C;
+						if (cpu->cd.arm.r[rd] & 0x80000000)
+							cpu->cd.arm.flags |= ARM_F_C;
+					}
+					
+					if (cpu->cd.arm.r[rd] == 0)
+						cpu->cd.arm.flags |= ARM_F_Z;
+					if ((int32_t)cpu->cd.arm.r[rd] < 0)
+						cpu->cd.arm.flags |= ARM_F_N;
+				}
+				break;
+			case 8:// tst
+				tmp = cpu->cd.arm.r[rd] & cpu->cd.arm.r[r3];
+				cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+				if (tmp == 0)
+					cpu->cd.arm.flags |= ARM_F_Z;
+				if ((int32_t)tmp < 0)
+					cpu->cd.arm.flags |= ARM_F_N;
+				break;
+			case 10:	// cmp
+				{
+					uint64_t old = cpu->cd.arm.r[rd];
+					uint64_t tmp64 = (uint32_t) (-cpu->cd.arm.r[r3]);
+					uint64_t result = old + tmp64;
+					cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N | ARM_F_C | ARM_F_V);
+					if (result == 0)
+						cpu->cd.arm.flags |= ARM_F_Z;
+					if ((int32_t)result < 0)
+						cpu->cd.arm.flags |= ARM_F_N;
+					if (result & 0x100000000ULL)
+						cpu->cd.arm.flags |= ARM_F_C;
+					if (result & 0x80000000) {
+						if ((tmp64 & 0x80000000) == 0 && (old & 0x80000000) == 0)
+							cpu->cd.arm.flags |= ARM_F_V;
+					} else {
+						if ((tmp64 & 0x80000000) != 0 && (old & 0x80000000) != 0)
+							cpu->cd.arm.flags |= ARM_F_V;
+					}
+				}
+				break;
+			case 12:// orrs
+				cpu->cd.arm.r[rd] |= cpu->cd.arm.r[r3];
+				cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+				if (cpu->cd.arm.r[rd] == 0)
+					cpu->cd.arm.flags |= ARM_F_Z;
+				if ((int32_t)cpu->cd.arm.r[rd] < 0)
+					cpu->cd.arm.flags |= ARM_F_N;
+				break;
+			case 13:// muls
+				cpu->cd.arm.r[rd] *= cpu->cd.arm.r[r3];
+				cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+				if (cpu->cd.arm.r[rd] == 0)
+					cpu->cd.arm.flags |= ARM_F_Z;
+				if ((int32_t)cpu->cd.arm.r[rd] < 0)
+					cpu->cd.arm.flags |= ARM_F_N;
+				break;
+			default:
+				debug("TODO: unimplemented DPI %i at pc 0x%08x\n", (iw >> 6) & 15, (int)cpu->pc);
+				cpu->running = 0;
+				return 0;
+			}
+			break;
+		case 1:
+			switch (op11_8) {
+			case 6:
+				if (hd)
+					rd += 8;
+				if (hm)
+					r3 += 8;
+				cpu->cd.arm.r[rd] = cpu->cd.arm.r[r3];
+				if (r3 == ARM_PC) {
+					if (cpu->pc & 1) {
+						debug("TODO: double check with manual whether it is correct to use old pc + 8 here; at pc 0x%08x\n", (int)cpu->pc);
+						cpu->running = 0;
+						return 0;
+					}
+					cpu->cd.arm.r[rd] = cpu->pc + 8;
+				}
+				if (rd == ARM_PC) {
+					cpu->pc = cpu->cd.arm.r[rd];
+					cpu->cd.arm.cpsr |= ARM_FLAG_T;
+					if (!(cpu->pc & 1))
+						cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
+					cpu->pc = addr - sizeof(uint16_t);
+				}
+				break;
+			case 7:
+				if ((iw & 0xff87) == 0x4700) {
+					//  bx
+					int rm = (iw >> 3) & 15;
+					//  Note: pc will be increased by 2 further down!
+					cpu->pc = cpu->cd.arm.r[rm] - sizeof(uint16_t);
+					if (!(cpu->pc & 1))
+						cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
+					if (rm == ARM_LR && cpu->machine->show_trace_tree)
+						cpu_functioncall_trace_return(cpu);
+				} else {
+					debug("TODO: unimplemented opcode 0x%x,%i at pc 0x%08x\n", main_opcode, op11_8, (int)cpu->pc);
+					cpu->running = 0;
+					return 0;
+				}
+				break;
+			default:
+				debug("TODO: unimplemented opcode 0x%x,%i at pc 0x%08x\n", main_opcode, op11_8, (int)cpu->pc);
+				cpu->running = 0;
+				return 0;
+			}
+			break;
+
+		case 2:
+		case 3:
+			// PC-relative load.
+			// Is this address calculation correct?
+			// It works with real code, but is not the same as that of
+			// http://engold.ui.ac.ir/~nikmehr/Appendix_B2.pdf
+			tmp = (addr & ~3) + 4 + (iw & 0xff) * 4;
+
+			if (!cpu->memory_rw(cpu, cpu->mem, tmp, &word[0],
+					sizeof(word), MEM_READ, CACHE_INSTRUCTION)) {
+				fatal("arm_cpu_interpret_thumb_SLOW(): could not load pc-relative word\n");
+				cpu->running = 0;
+				return 0;
+			}
+
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+				tmp = word[0] + (word[1]<<8) + (word[2]<<16) + (word[3]<<24);
+			else
+				tmp = word[3] + (word[2]<<8) + (word[1]<<16) + (word[0]<<24);
+
+			cpu->cd.arm.r[rd8] = tmp;
+			break;
+
+		default:
+			debug("TODO: unimplemented opcode 0x%x,%i at pc 0x%08x\n", main_opcode, op10, (int)cpu->pc);
+			cpu->running = 0;
+			return 0;
+		}
+		break;
+
+	case 0x6:
+	case 0x7:
+	case 0x8:
+		// Load/Store with immediate offset.
+		len = main_opcode == 6 ? 4 : (main_opcode == 7 ? 1 : 2);
+		isLoad = iw & 0x0800;
+		addr = (cpu->cd.arm.r[r3] + imm6 * len) & ~(len - 1);
+		tmp = 0;
+
+		if (!isLoad) {
+			tmp = cpu->cd.arm.r[rd];
+
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+				for (int i = 0; i < len; ++i)
+					word[i] = (tmp >> (8*i));
+			} else {
+				for (int i = 0; i < len; ++i)
+					word[len - 1 - i] = (tmp >> (8*i));
+			}
+		}
+
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
+				len, isLoad ? MEM_READ : MEM_WRITE, CACHE_DATA)) {
+			fatal("arm_cpu_interpret_thumb_SLOW(): could not load with immediate offset\n");
+			cpu->running = 0;
+			return 0;
+		}
+
+		if (isLoad) {
+			tmp = 0;
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+				for (int i = 0; i < len; ++i) {
+					tmp <<= 8;
+					tmp |= word[len - 1 - i];
+				}
+			} else {
+				for (int i = 0; i < len; ++i) {
+					tmp <<= 8;
+					tmp |= word[i];
+				}
+			}
+
+			cpu->cd.arm.r[rd] = tmp;
+		}
+		break;
+
+	case 0x9:
+		// sp-relative load or store
+		if (iw & 0x0800) {
+			addr = (cpu->cd.arm.r[ARM_SP] + (iw & 0xff) * 4) & ~3;
+			if (!cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
+					sizeof(word), MEM_READ, CACHE_DATA)) {
+				fatal("arm_cpu_interpret_thumb_SLOW(): could not load sp-relative word\n");
+				cpu->running = 0;
+				return 0;
+			}
+
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+				tmp = word[0] + (word[1]<<8) + (word[2]<<16) + (word[3]<<24);
+			else
+				tmp = word[3] + (word[2]<<8) + (word[1]<<16) + (word[0]<<24);
+
+			cpu->cd.arm.r[rd8] = tmp;
+		} else {
+			tmp = cpu->cd.arm.r[rd8];
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+				for (size_t i = 0; i < sizeof(word); ++i)
+					word[i] = (tmp >> (8*i));
+			} else {
+				for (size_t i = 0; i < sizeof(word); ++i)
+					word[sizeof(word) - 1 - i] = (tmp >> (8*i));
+			}
+
+			addr = (cpu->cd.arm.r[ARM_SP] + (iw & 0xff) * 4) & ~3;
+			if (!cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
+					sizeof(word), MEM_WRITE, CACHE_DATA)) {
+				fatal("arm_cpu_interpret_thumb_SLOW(): could not store sp-relative word\n");
+				cpu->running = 0;
+				return 0;
+			}
+		}
+		break;
+
+	case 0xb:
+		switch (op11_8) {
+		case 0:
+			if (iw & 0x0080)
+				cpu->cd.arm.r[ARM_SP] -= ((iw & 0x7f) << 2);
+			else
+				cpu->cd.arm.r[ARM_SP] += ((iw & 0x7f) << 2);
+			break;
+		case 4:
+		case 5:
+			/*  push, i.e. stmdb sp!, reglist  */
+			arm_push(cpu, &cpu->cd.arm.r[ARM_SP], 1, 0, 0, 1, (iw & 0xff) |
+				(iw & 0x100 ? (1 << ARM_LR) : 0));
+			break;
+		case 12:
+		case 13:
+			/*  pop, i.e. ldmia sp!, reglist  */
+			cpu->cd.arm.r[ARM_PC] = cpu->pc;
+			arm_pop(cpu, &cpu->cd.arm.r[ARM_SP], 0, 1, 0, 1, (iw & 0xff) |
+				(iw & 0x100 ? (1 << ARM_PC) : 0));
+			cpu->pc = cpu->cd.arm.r[ARM_PC];
+			if (cpu->pc & 1)
+				cpu->cd.arm.cpsr |= ARM_FLAG_T;
+			else
+				cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
+			// If not popping pc, make sure to move to the next instruction:
+			if (!(iw & 0x100))
+				cpu->pc += sizeof(uint16_t);
+			return 1;
+		default:
+			debug("TODO: unimplemented opcode 0x%x,%i at pc 0x%08x\n", main_opcode, op11_8, (int)cpu->pc);
+			cpu->running = 0;
+			return 0;
+		}
+		break;
+
+	case 0xd:
+		if (condition_code < 0xe) {
+			// Conditional branch.
+			tmp = (iw & 0xff) << 1;
+			if (tmp & 0x100)
+				tmp |= 0xfffffe00;
+			tmp = (int32_t)(cpu->pc + 4 + tmp);
+
+			switch (condition_code) {
+			case 0x0:	// eq:
+					t = cpu->cd.arm.flags & ARM_F_Z;
+					break;
+			case 0x1:	// ne:
+					t = !(cpu->cd.arm.flags & ARM_F_Z);
+					break;
+			case 0x2:	// cs:
+					t = cpu->cd.arm.flags & ARM_F_C;
+					break;
+			case 0x3:	// cc:
+					t = !(cpu->cd.arm.flags & ARM_F_C);
+					break;
+			case 0x4:	// mi:
+					t = cpu->cd.arm.flags & ARM_F_N;
+					break;
+			case 0x5:	// pl:
+					t = !(cpu->cd.arm.flags & ARM_F_N);
+					break;
+			case 0x6:	// vs:
+					t = cpu->cd.arm.flags & ARM_F_V;
+					break;
+			case 0x7:	// vc:
+					t = !(cpu->cd.arm.flags & ARM_F_V);
+					break;
+			case 0x8:	// hi:
+					t = condition_hi[cpu->cd.arm.flags];
+					break;
+			case 0x9:	// ls:
+					t = !condition_hi[cpu->cd.arm.flags];
+					break;
+			case 0xa:	// ge:
+					t = condition_ge[cpu->cd.arm.flags];
+					break;
+			case 0xb:	// lt:
+					t = !condition_ge[cpu->cd.arm.flags];
+					break;
+			case 0xc:	// gt:
+					t = condition_gt[cpu->cd.arm.flags];
+					break;
+			case 0xd:	// le:
+					t = !condition_gt[cpu->cd.arm.flags];
+					break;
+			}
+
+			if (t) {
+				cpu->pc = tmp;
+				return 1;
+			}
+		} else if (condition_code == 0xf) {
+			arm_exception(cpu, ARM_EXCEPTION_SWI);
+			return 1;
+		} else {
+			debug("TODO: unimplemented opcode 0x%x, non-branch, at pc 0x%08x\n", main_opcode, (int)cpu->pc);
+			cpu->running = 0;
+			return 0;
+		}
+		break;
+
+	case 0xe:
+		if (iw & 0x0800) {
+			// blx
+			addr = (cpu->pc + 4 + (cpu->cd.arm.tmp_branch + (((iw >> 1) & 0x3ff) << 2))) & ~3;
+
+			if (iw & 1) {
+				fatal("lowest bit set in thumb blx instruction?\n");
+				cpu->running = 0;
+				return 0;
+			}
+
+			cpu->cd.arm.r[ARM_LR] = cpu->pc + 2;
+			cpu->pc = addr;
+			if (cpu->machine->show_trace_tree)
+				cpu_functioncall_trace(cpu, cpu->pc);
+			cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
+			return 1;
+		} else {
+			// b
+			tmp = (iw & 0x7ff) << 1;
+			if (tmp & 0x800)
+				tmp |= 0xfffff000;
+			cpu->pc = (int32_t)(cpu->pc + 4 + tmp);
+			return 1;
+		}
+		break;
+
+	case 0xf:
+		if (iw & 0x0800) {
+			// bl
+			addr = (cpu->pc + 2 + (cpu->cd.arm.tmp_branch + ((iw & 0x7ff) << 1)));
+			cpu->cd.arm.r[ARM_LR] = cpu->pc + 2;
+			cpu->pc = addr;
+			if (cpu->machine->show_trace_tree)
+				cpu_functioncall_trace(cpu, cpu->pc);
+			return 1;
+		} else {
+			// "branch prefix".
+			uint32_t tmp32 = iw & 0x07ff;
+			if (tmp32 & 0x0400)
+				tmp32 |= 0xfffff800;
+			tmp32 <<= 12;
+			cpu->cd.arm.tmp_branch = tmp32;
+		}
+		break;
+
+	default:
+		debug("TODO: unimplemented opcode 0x%x at pc 0x%08x\n", main_opcode, (int)cpu->pc);
+		cpu->running = 0;
+		return 0;
+	}
+
+	cpu->pc += sizeof(uint16_t);
+
+	return 1;
+}
+
+
+/*
+ *  arm_cpu_disassemble_instr():
+ *
+ *  Convert an instruction word into human readable format, for instruction
+ *  tracing.
+ *              
+ *  If running is 1, cpu->pc should be the address of the instruction.
+ *
+ *  If running is 0, things that depend on the runtime environment (eg.
+ *  register contents) will not be shown, and addr will be used instead of
+ *  cpu->pc for relative addresses.
+ */                     
+int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
+        int running, uint64_t dumpaddr)
+{
+	uint32_t iw, tmp;
+	int main_opcode, secondary_opcode, s_bit, r16, r12, r8;
+	int i, n, p_bit, u_bit, b_bit, w_bit, l_bit;
+	const char *symbol, *condition;
+	uint64_t offset;
+
+	if (running)
+		dumpaddr = cpu->pc;
+
+	symbol = get_symbol_name(&cpu->machine->symbol_context,
+	    dumpaddr, &offset);
+	if (symbol != NULL && offset == 0)
+		debug("<%s>\n", symbol);
+
+	if (cpu->machine->ncpus > 1 && running)
+		debug("cpu%i:\t", cpu->cpu_id);
+
+	debug("%08x:  ", (int)dumpaddr & ~1);
+
+	if (dumpaddr & 1)
+		return arm_cpu_disassemble_instr_thumb(cpu, ib, running, dumpaddr);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
+	else
+		iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);
+	debug("%08x", (int)iw);
+
+	cpu_print_pc_indicator_in_disassembly(cpu, running, dumpaddr);
+
+	condition = arm_condition_string[iw >> 28];
+	main_opcode = (iw >> 24) & 15;
+	secondary_opcode = (iw >> 21) & 15;
+	u_bit = (iw >> 23) & 1;
+	b_bit = (iw >> 22) & 1;
+	w_bit = (iw >> 21) & 1;
+	s_bit = l_bit = (iw >> 20) & 1;
+	r16 = (iw >> 16) & 15;
+	r12 = (iw >> 12) & 15;
+	r8 = (iw >> 8) & 15;
+
+	if (iw == 0xf10c0040) {
+		debug("cpsid\tf\n");
+		return sizeof(uint32_t);
+	} else if (iw == 0xf10c0080) {
+		debug("cpsid\ti\n");
+		return sizeof(uint32_t);
+	} else if (iw == 0xf57ff04f) {
+		debug("dsb\tsy\n");
+		return sizeof(uint32_t);
+	} else if (iw == 0xf57ff05f) {
+		debug("dmb\tsy\n");
+		return sizeof(uint32_t);
+	} else if (iw == 0xf57ff06f) {
+		debug("isb\tsy\n");
+		return sizeof(uint32_t);
+	} else if ((iw >> 28) == 0xf) {
+		switch (main_opcode) {
+		case 0xa:
+		case 0xb:
+			tmp = (iw & 0xffffff);
+			if (tmp & 0x800000)
+				tmp |= 0xff000000;
+			tmp = (int32_t)(dumpaddr + 8 + 4*tmp + (main_opcode == 0xb? 2 : 0)) + 1;
+			debug("blx\t0x%x", (int)tmp);
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    tmp, &offset);
+			if (symbol != NULL)
+				debug(" \t<%s>", symbol);
+			debug("\n");
+			break;
+		default:debug("UNIMPLEMENTED\n");
+		}
+		return sizeof(uint32_t);
+	}
+
+	switch (main_opcode) {
+	case 0x0:
+	case 0x1:
+	case 0x2:
+	case 0x3:
+		/*
+		 *  Special cases first:
+		 */
+
+		/*
+		 *  ldrex: Load Register Exclusive
+		 *  strex: Store Register Exclusive
+		 */
+		if ((iw & 0x0ff00fff) == 0x01900f9f) {
+			/*  ldrex rt[,rn]:  */
+			debug("ldrex%s\t%s,%s",
+				condition,
+				arm_regname[r12],
+				arm_regname[r16]);
+			debug("\n");
+			break;
+		}
+		if ((iw & 0x0ff00ff0) == 0x01800f90) {
+			/*  strex rd,rt[,rn]:  */
+			debug("strex%s\t%s,%s,%s",
+				condition,
+				arm_regname[r12],
+				arm_regname[iw & 15],
+				arm_regname[r16]);
+			debug("\n");
+			break;
+		}
+
+		/*
+		 *  Multiplication:
+		 *  xxxx0000 0110dddd aaaammmm 1001nnnn  mls rd,rn,rm,ra
+		 */
+		if ((iw & 0x0ff000f0) == 0x00600090) {
+			debug("mls%s\t", condition);
+			debug("%s,", arm_regname[r16]);
+			debug("%s,", arm_regname[iw & 15]);
+			debug("%s,", arm_regname[r8]);
+			debug("%s", arm_regname[r12]);
+			debug("\n");
+			break;
+		}
+
+		/*
+		 *  Multiplication:
+		 *  xxxx0000 00ASdddd nnnnssss 1001mmmm  (Rd, Rm, Rs [,Rn])
+		 */
+		if ((iw & 0x0fc000f0) == 0x00000090) {
+			int a_bit = (iw >> 21) & 1;
+			debug("%s%s%s\t", a_bit? "mla" : "mul",
+			    condition, s_bit? "s" : "");
+			debug("%s,", arm_regname[r16]);
+			debug("%s,", arm_regname[iw & 15]);
+			debug("%s", arm_regname[r8]);
+			if (a_bit)
+				debug(",%s", arm_regname[r12]);
+			debug("\n");
+			break;
+		}
+
+		/*
+		 *  Long multiplication:
+		 *  xxxx0000 1UAShhhh llllssss 1001mmmm  (Rl,Rh,Rm,Rs)
+		 */
+		if ((iw & 0x0f8000f0) == 0x00800090) {
+			int a_bit = (iw >> 21) & 1;
+			u_bit = (iw >> 22) & 1;
+			debug("%s%sl%s%s\t", u_bit? "s" : "u",
+			    a_bit? "mla" : "mul", condition, s_bit? "s" : "");
+			debug("%s,%s,", arm_regname[r12], arm_regname[r16]);
+			debug("%s,%s\n", arm_regname[iw&15], arm_regname[r8]);
+			break;
+		}
+
+		/*
+		 *  xxxx0001 0000nnnn dddd0000 0101mmmm  qadd Rd,Rm,Rn
+		 *  xxxx0001 0010nnnn dddd0000 0101mmmm  qsub Rd,Rm,Rn
+		 *  xxxx0001 0100nnnn dddd0000 0101mmmm  qdadd Rd,Rm,Rn
+		 *  xxxx0001 0110nnnn dddd0000 0101mmmm  qdsub Rd,Rm,Rn
+		 */
+		if ((iw & 0x0f900ff0) == 0x01000050) {
+			debug("q%s%s%s\t", iw & 0x400000? "d" : "",
+			    iw & 0x200000? "sub" : "add", condition);
+			debug("%s,%s,%s\n", arm_regname[r12],
+			    arm_regname[iw&15], arm_regname[r16]);
+			break;
+		}
+
+		/*
+		 *  xxxx0001 0010.... ........ 00L1mmmm  bx/blx rm
+		 */
+		if ((iw & 0x0ff000d0) == 0x01200010) {
+			l_bit = iw & 0x20;
+			debug("b%sx%s\t%s\n", l_bit? "l" : "", condition,
+			    arm_regname[iw & 15]);
+			break;
+		}
+
+		/*
+		 *  xxxx0001 0s10aaaa 11110000 0000mmmm  MSR  Regform
+		 *  xxxx0011 0s10aaaa 1111rrrr bbbbbbbb  MSR  Immform
+		 *  xxxx0001 0s001111 dddd0000 00000000  MRS
+		 */
+		if ((iw & 0x0fb0fff0) == 0x0120f000 ||
+		    (iw & 0x0fb0f000) == 0x0320f000) {
+			debug("msr%s\t%s", condition, (iw&0x400000)? "S":"C");
+			debug("PSR_");
+			if (iw & (1<<19)) debug("f");
+			if (iw & (1<<18)) debug("s");
+			if (iw & (1<<17)) debug("x");
+			if (iw & (1<<16)) debug("c");
+			if (iw & 0x02000000) {
+				int r = (iw >> 7) & 30;
+				uint32_t b = iw & 0xff;
+				while (r-- > 0)
+					b = (b >> 1) | ((b & 1) << 31);
+				debug(",#0x%x\n", b);
+			} else
+				debug(",%s\n", arm_regname[iw & 15]);
+			break;
+		}
+		if ((iw & 0x0fbf0fff) == 0x010f0000) {
+			debug("mrs%s\t", condition);
+			debug("%s,%sPSR\n", arm_regname[r12],
+			    (iw&0x400000)? "S":"C");
+			break;
+		}
+
+		/*
+		 *  xxxx0001 0B00nnnn dddd0000 1001mmmm    SWP Rd,Rm,[Rn]
+		 */
+		if ((iw & 0x0fb00ff0) == 0x01000090) {
+			debug("swp%s%s\t", condition, (iw&0x400000)? "b":"");
+			debug("%s,%s,[%s]\n", arm_regname[r12],
+			    arm_regname[iw & 15], arm_regname[r16]);
+			break;
+		}
+
+		/*
+		 *  xxxx0001 0010iiii iiiiiiii 0111iiii    BKPT immed16
+		 */
+		if ((iw & 0x0ff000f0) == 0x01200070) {
+			debug("bkpt%s\t0x%04x\n", condition,
+			    ((iw & 0x000fff00) >> 4) + (iw & 0xf));
+			break;
+		}
+
+		/*
+		 *  xxxx0001 01101111 dddd1111 0001mmmm    CLZ Rd,Rm
+		 */
+		if ((iw & 0x0fff0ff0) == 0x016f0f10) {
+			debug("clz%s\t", condition);
+			debug("%s,%s\n", arm_regname[r12], arm_regname[iw&15]);
+			break;
+		}
+
+		/*
+		 *  xxxx0011 0000mmm ddddmmm mmmmmmm    MOVW Rd,imm
+		 */
+		if ((iw & 0x0ff00000) == 0x03000000) {
+			debug("movw%s\t", condition);
+			debug("%s,#%i\n", arm_regname[r12],
+				((iw & 0xf0000) >> 4) | (iw & 0xfff));
+			break;
+		}
+
+		/*
+		 *  xxxx0011 0100mmm ddddmmm mmmmmmm    MOVT Rd,imm
+		 */
+		if ((iw & 0x0ff00000) == 0x03400000) {
+			debug("movt%s\t", condition);
+			debug("%s,#%i\n", arm_regname[r12],
+				((iw & 0xf0000) >> 4) | (iw & 0xfff));
+			break;
+		}
+
+		/*
+		 *  xxxx0001 0000dddd nnnnssss 1yx0mmmm  SMLAxy Rd,Rm,Rs,Rn
+		 *  xxxx0001 0100dddd DDDDssss 1yx0mmmm  SMLALxy RdL,RdH,Rm,Rs
+		 *  xxxx0001 0010dddd nnnnssss 1y00mmmm  SMLAWy Rd,Rm,Rs,Rn
+		 *  xxxx0001 0110dddd 0000ssss 1yx0mmmm  SMULxy Rd,Rm,Rs
+		 *  xxxx0001 0010dddd 0000ssss 1y10mmmm  SMULWy Rd,Rm,Rs
+		 */
+		if ((iw & 0x0ff00090) == 0x01000080) {
+			debug("smla%s%s%s\t",
+			    iw & 0x20? "t" : "b", iw & 0x40? "t" : "b",
+			    condition);
+			debug("%s,%s,%s,%s\n", arm_regname[r16],
+			    arm_regname[iw&15], arm_regname[r8],
+			    arm_regname[r12]);
+			break;
+		}
+		if ((iw & 0x0ff00090) == 0x01400080) {
+			debug("smlal%s%s%s\t",
+			    iw & 0x20? "t" : "b", iw & 0x40? "t" : "b",
+			    condition);
+			debug("%s,%s,%s,%s\n", arm_regname[r12],
+			    arm_regname[r16], arm_regname[iw&15],
+			    arm_regname[r8]);
+			break;
+		}
+		if ((iw & 0x0ff000b0) == 0x01200080) {
+			debug("smlaw%s%s\t", iw & 0x40? "t" : "b",
+			    condition);
+			debug("%s,%s,%s,%s\n", arm_regname[r16],
+			    arm_regname[iw&15], arm_regname[r8],
+			    arm_regname[r12]);
+			break;
+		}
+		if ((iw & 0x0ff0f090) == 0x01600080) {
+			debug("smul%s%s%s\t",
+			    iw & 0x20? "t" : "b", iw & 0x40? "t" : "b",
+			    condition);
+			debug("%s,%s,%s\n", arm_regname[r16],
+			    arm_regname[iw&15], arm_regname[r8]);
+			break;
+		}
+		if ((iw & 0x0ff0f0b0) == 0x012000a0) {
+			debug("smulw%s%s\t", iw & 0x40? "t" : "b",
+			    condition);
+			debug("%s,%s,%s\n", arm_regname[r16],
+			    arm_regname[iw&15], arm_regname[r8]);
+			break;
+		}
+
+		/*
+		 *  xxxx000P U1WLnnnn ddddHHHH 1SH1LLLL load/store rd,imm(rn)
+		 */
+		if ((iw & 0x0e000090) == 0x00000090) {
+			const char *op = "st";
+			int imm = ((iw >> 4) & 0xf0) | (iw & 0xf);
+			int regform = !(iw & 0x00400000);
+			p_bit = main_opcode & 1;
+			/*
+			 *  TODO: detect some illegal variants:
+			 *  signed store,  or  unsigned byte load/store
+			 */
+			if (!l_bit && (iw & 0xd0) == 0xd0 && (r12 & 1)) {
+				debug("TODO: r12 odd, not load/store\n");
+				break;
+			}
+			/*  Semi-generic case:  */
+			if (iw & 0x00100000)
+				op = "ld";
+			if (!l_bit && (iw & 0xd0) == 0xd0) {
+				if (iw & 0x20)
+					op = "st";
+				else
+					op = "ld";
+			}
+			debug("%sr%s", op, condition);
+			if (!l_bit && (iw & 0xd0) == 0xd0) {
+				debug("d");		/*  Double-register  */
+			} else {
+				if (iw & 0x40)
+					debug("s");	/*  signed  */
+				if (iw & 0x20)
+					debug("h");	/*  half-word  */
+				else
+					debug("b");	/*  byte  */
+			}
+			debug("\t%s,[%s", arm_regname[r12], arm_regname[r16]);
+			if (p_bit) {
+				/*  Pre-index:  */
+				if (regform)
+					debug(",%s%s", u_bit? "" : "-",
+					    arm_regname[iw & 15]);
+				else {
+					if (imm != 0)
+						debug(",#%s%i", u_bit? "" : "-",
+						    imm);
+				}
+				debug("]%s\n", w_bit? "!" : "");
+			} else {
+				/*  Post-index:  */
+				debug("],");
+				if (regform)
+					debug("%s%s\n", u_bit? "" : "-",
+					    arm_regname[iw & 15]);
+				else
+					debug("#%s%i\n", u_bit? "" : "-", imm);
+			}
+			break;
+		}
+
+		/*  Other special cases:  */
+		if (iw & 0x80 && !(main_opcode & 2) && iw & 0x10) {
+			debug("UNIMPLEMENTED reg (c!=0), t odd\n");
+			break;
+		}
+
+		/*
+		 *  Generic Data Processing Instructions:
+		 *
+		 *  xxxx000a aaaSnnnn ddddcccc ctttmmmm  Register form
+		 *  xxxx001a aaaSnnnn ddddrrrr bbbbbbbb  Immediate form
+		 */
+
+		debug("%s%s%s\t", arm_dpiname[secondary_opcode],
+		    condition, s_bit? "s" : "");
+		if (arm_dpi_uses_d[secondary_opcode])
+			debug("%s,", arm_regname[r12]);
+		if (arm_dpi_uses_n[secondary_opcode])
+			debug("%s,", arm_regname[r16]);
+
+		if (main_opcode & 2) {
+			/*  Immediate form:  */
+			int r = (iw >> 7) & 30;
+			uint32_t b = iw & 0xff;
+			while (r-- > 0)
+				b = (b >> 1) | ((b & 1) << 31);
+			if (b < 15)
+				debug("#%i", b);
+			else
+				debug("#0x%x", b);
+		} else {
+			/*  Register form:  */
+			int t = (iw >> 4) & 7;
+			int c = (iw >> 7) & 31;
+			debug("%s", arm_regname[iw & 15]);
+			switch (t) {
+			case 0:	if (c != 0)
+					debug(", lsl #%i", c);
+				break;
+			case 1:	debug(", lsl %s", arm_regname[c >> 1]);
+				break;
+			case 2:	debug(", lsr #%i", c? c : 32);
+				break;
+			case 3:	debug(", lsr %s", arm_regname[c >> 1]);
+				break;
+			case 4:	debug(", asr #%i", c? c : 32);
+				break;
+			case 5:	debug(", asr %s", arm_regname[c >> 1]);
+				break;
+			case 6:	if (c != 0)
+					debug(", ror #%i", c);
+				else
+					debug(", rrx");
+				break;
+			case 7:	debug(", ror %s", arm_regname[c >> 1]);
+				break;
+			}
+
+			/*  mov pc,reg:  */
+			if (running && t == 0 && c == 0 && secondary_opcode
+			    == 0xd && r12 == ARM_PC && (iw&15)!=ARM_PC) {
+				symbol = get_symbol_name(&cpu->machine->
+				    symbol_context, cpu->cd.arm.r[iw & 15],
+				    &offset);
+				if (symbol != NULL)
+					debug(" \t<%s>", symbol);
+			}
+		}
+		debug("\n");
+		break;
+	case 0x4:				/*  Single Data Transfer  */
+	case 0x5:
+	case 0x6:
+	case 0x7:
+		/*  Special cases first:  */
+		if ((iw & 0xfc70f000) == 0xf450f000) {
+			/*  Preload:  */
+			debug("pld\t[%s]\n", arm_regname[r16]);
+			break;
+		}
+
+		if ((iw & 0x0fff0ff0) == 0x06bf0f30) {
+			/*  rev rd,rm:  */
+			debug("rev%s\t%s,%s",
+				condition,
+				arm_regname[r12],
+				arm_regname[iw & 15]);
+			debug("\n");
+			break;
+		}
+
+		if ((iw & 0x0fff03f0) == 0x06bf0070) {
+			/*  sxth rd,rm[,rot]:  */
+			debug("sxth%s\t%s,%s",
+				condition,
+				arm_regname[r12],
+				arm_regname[iw & 15]);
+			int rot = ((iw & 0xc00) >> 10) << 3;
+			if (rot != 0)
+				debug(",%i", rot);
+			debug("\n");
+			break;
+		}
+
+		if ((iw & 0x0fff03f0) == 0x06ef0070) {
+			/*  uxtb rd,rm[,rot]:  */
+			debug("uxtb%s\t%s,%s",
+				condition,
+				arm_regname[r12],
+				arm_regname[iw & 15]);
+			int rot = ((iw & 0xc00) >> 10) << 3;
+			if (rot != 0)
+				debug(",%i", rot);
+			debug("\n");
+			break;
+		}
+
+		// Note: uxtab is decoded AFTER uxtb.
+		if ((iw & 0x0ff003f0) == 0x06e00070) {
+			/*  uxtab rd,rn,rm[,rot]:  */
+			debug("uxtab%s\t%s,%s,%s",
+				condition,
+				arm_regname[r12],
+				arm_regname[r16],
+				arm_regname[iw & 15]);
+			int rot = ((iw & 0xc00) >> 10) << 3;
+			if (rot != 0)
+				debug(",%i", rot);
+			debug("\n");
+			break;
+		}
+
+		if ((iw & 0x0fff03f0) == 0x06ff0070) {
+			/*  uxth rd,rm[,rot]:  */
+			debug("uxth%s\t%s,%s",
+				condition,
+				arm_regname[r12],
+				arm_regname[iw & 15]);
+			int rot = ((iw & 0xc00) >> 10) << 3;
+			if (rot != 0)
+				debug(",%i", rot);
+			debug("\n");
+			break;
+		}
+
+		// Note: uxtah is decoded AFTER uxth.
+		if ((iw & 0x0ff003f0) == 0x06f00070) {
+			/*  uxtah rd,rn,rm[,rot]:  */
+			debug("uxtah%s\t%s,%s,%s",
+				condition,
+				arm_regname[r12],
+				arm_regname[r16],
+				arm_regname[iw & 15]);
+			int rot = ((iw & 0xc00) >> 10) << 3;
+			if (rot != 0)
+				debug(",%i", rot);
+			debug("\n");
+			break;
+		}
+
+		if ((iw & 0x0fe00070) == 0x07c00010) {
+			/*  bfi rd,rn,#lsb,#width:  */
+			debug("bfi%s\t%s,%s",
+				condition,
+				arm_regname[r12],
+				arm_regname[iw & 15]);
+			int lsb = (iw >> 7) & 31;
+			int msb = (iw >> 16) & 31;
+			int width = msb - lsb + 1;
+			debug(",%i", lsb);
+			debug(",%i", width);
+			debug("\n");
+			break;
+		}
+
+		if ((iw & 0x0fe00070) == 0x07e00050) {
+			/*  ubfx rd,rn,#lsb,#width:  */
+			debug("ubfx%s\t%s,%s",
+				condition,
+				arm_regname[r12],
+				arm_regname[iw & 15]);
+			debug(",%i", (iw >> 7) & 31);
+			debug(",%i", 1 + ((iw >> 16) & 31));
+			debug("\n");
+			break;
+		}
+
+		if ((iw & 0x0fe00070) == 0x07a00050) {
+			/*  sbfx rd,rn,#lsb,#width:  */
+			debug("sbfx%s\t%s,%s",
+				condition,
+				arm_regname[r12],
+				arm_regname[iw & 15]);
+			debug(",%i", (iw >> 7) & 31);
+			debug(",%i", 1 + ((iw >> 16) & 31));
+			debug("\n");
+			break;
+		}
+
+		if ((iw & 0x0fffffff) == 0x07f001f2) {
+			debug("linux_bug%s\t; see https://github.com/torvalds/linux/blob/master/arch/arm/include/asm/bug.h\n",
+				condition);
+			break;
+		}
+
+
+		/*
+		 *  xxxx010P UBWLnnnn ddddoooo oooooooo  Immediate form
+		 *  xxxx011P UBWLnnnn ddddcccc ctt0mmmm  Register form
+		 */
+		p_bit = main_opcode & 1;
+		if (main_opcode >= 6 && iw & 0x10) {
+			debug("TODO: single data transf. but 0x10\n");
+			break;
+		}
+		debug("%s%s%s", l_bit? "ldr" : "str",
+		    condition, b_bit? "b" : "");
+		if (!p_bit && w_bit)
+			debug("t");
+		debug("\t%s,[%s", arm_regname[r12], arm_regname[r16]);
+		if ((iw & 0x0e000000) == 0x04000000) {
+			/*  Immediate form:  */
+			uint32_t imm = iw & 0xfff;
+			if (!p_bit)
+				debug("]");
+			if (imm != 0)
+				debug(",#%s%i", u_bit? "" : "-", imm);
+			if (p_bit)
+				debug("]");
+		} else if ((iw & 0x0e000010) == 0x06000000) {
+			/*  Register form:  */
+			if (!p_bit)
+				debug("]");
+			if ((iw & 0xfff) != 0)
+				debug(",%s%s", u_bit? "" : "-",
+				    arm_regname[iw & 15]);
+			if ((iw & 0xff0) != 0x000) {
+				int c = (iw >> 7) & 31;
+				int t = (iw >> 4) & 7;
+				switch (t) {
+				case 0:	if (c != 0)
+						debug(", lsl #%i", c);
+					break;
+				case 2:	debug(", lsr #%i", c? c : 32);
+					break;
+				case 4:	debug(", asr #%i", c? c : 32);
+					break;
+				case 6:	if (c != 0)
+						debug(", ror #%i", c);
+					else
+						debug(", rrx");
+					break;
+				}
+			}
+			if (p_bit)
+				debug("]");
+		} else {
+			debug("UNKNOWN\n");
+			break;
+		}
+		debug("%s", (p_bit && w_bit)? "!" : "");
+		if ((iw & 0x0f000000) == 0x05000000 &&
+		    (r16 == ARM_PC || running)) {
+			unsigned char tmpw[4];
+			uint32_t imm = iw & 0xfff;
+			uint32_t addr = (u_bit? imm : -imm);
+			if (r16 == ARM_PC)
+				addr += dumpaddr + 8;
+			else
+				addr += cpu->cd.arm.r[r16];
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    addr, &offset);
+			if (symbol != NULL)
+				debug(" \t<%s", symbol);
+			else
+				debug(" \t<0x%08x", addr);
+			if ((l_bit && cpu->memory_rw(cpu, cpu->mem, addr, tmpw,
+			    b_bit? 1 : sizeof(tmpw), MEM_READ, NO_EXCEPTIONS))
+			    || (!l_bit && running)) {
+				if (l_bit) {
+					if (cpu->byte_order ==
+					    EMUL_LITTLE_ENDIAN)
+						addr = tmpw[0] +(tmpw[1] << 8) +
+						    (tmpw[2]<<16)+(tmpw[3]<<24);
+					else
+						addr = tmpw[3] + (tmpw[2]<<8) +
+						    (tmpw[1]<<16)+(tmpw[0]<<24);
+				} else {
+					tmpw[0] = addr = cpu->cd.arm.r[r12];
+					if (r12 == ARM_PC)
+						addr = cpu->pc + 8;
+				}
+				debug(": ");
+				if (b_bit)
+					debug("%i", tmpw[0]);
+				else {
+					symbol = get_symbol_name(&cpu->machine->
+					    symbol_context, addr, &offset);
+					if (symbol != NULL)
+						debug("%s", symbol);
+					else if ((int32_t)addr > -256 &&
+						    (int32_t)addr < 256)
+						debug("%i", addr);
+					else
+						debug("0x%x", addr);
+				}
+			}
+			debug(">");
+		}
+		debug("\n");
+		break;
+	case 0x8:				/*  Block Data Transfer  */
+	case 0x9:
+		/*  xxxx100P USWLnnnn llllllll llllllll  */
+		p_bit = main_opcode & 1;
+		s_bit = b_bit;
+		debug("%s%s", l_bit? "ldm" : "stm", condition);
+		switch (u_bit * 2 + p_bit) {
+		case 0:	debug("da"); break;
+		case 1:	debug("db"); break;
+		case 2:	debug("ia"); break;
+		case 3:	debug("ib"); break;
+		}
+		debug("\t%s", arm_regname[r16]);
+		if (w_bit)
+			debug("!");
+		debug(",{");
+		n = 0;
+		for (i=0; i<16; i++)
+			if ((iw >> i) & 1) {
+				debug("%s%s", (n > 0)? ",":"", arm_regname[i]);
+				n++;
+			}
+		debug("}");
+		if (s_bit)
+			debug("^");
+		debug("\n");
+		break;
+	case 0xa:				/*  B: branch  */
+	case 0xb:				/*  BL: branch and link  */
+		debug("b%s%s\t", main_opcode == 0xa? "" : "l", condition);
+		tmp = (iw & 0x00ffffff) << 2;
+		if (tmp & 0x02000000)
+			tmp |= 0xfc000000;
+		tmp = (int32_t)(dumpaddr + tmp + 8);
+		debug("0x%x", (int)tmp);
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    tmp, &offset);
+		if (symbol != NULL)
+			debug(" \t<%s>", symbol);
+		debug("\n");
+		break;
+	case 0xc:				/*  Coprocessor  */
+	case 0xd:				/*  LDC/STC  */
+		/*
+		 *  xxxx1100 0100nnnn ddddcccc oooommmm    MCRR c,op,Rd,Rn,CRm
+		 *  xxxx1100 0101nnnn ddddcccc oooommmm    MRRC c,op,Rd,Rn,CRm
+		 */
+		if ((iw & 0x0fe00fff) == 0x0c400000) {
+			debug("%s%s\t", iw & 0x100000? "mra" : "mar",
+			    condition);
+			if (iw & 0x100000)
+				debug("%s,%s,acc0\n",
+				    arm_regname[r12], arm_regname[r16]);
+			else
+				debug("acc0,%s,%s\n",
+				    arm_regname[r12], arm_regname[r16]);
+			break;
+		}
+		if ((iw & 0x0fe00000) == 0x0c400000) {
+			debug("%s%s\t", iw & 0x100000? "mrrc" : "mcrr",
+			    condition);
+			debug("%i,%i,%s,%s,cr%i\n", r8, (iw >> 4) & 15,
+			    arm_regname[r12], arm_regname[r16], iw & 15);
+			break;
+		}
+
+		/*  xxxx110P UNWLnnnn DDDDpppp oooooooo LDC/STC  */
+		debug("TODO: coprocessor LDC/STC\n");
+		break;
+	case 0xe:				/*  CDP (Coprocessor Op)  */
+		/*				    or MRC/MCR!
+		 *  xxxx1110 oooonnnn ddddpppp qqq0mmmm		CDP
+		 *  xxxx1110 oooLNNNN ddddpppp qqq1MMMM		MRC/MCR
+		 */
+		if ((iw & 0x0ff00ff0) == 0x0e200010) {
+			/*  Special case: mia* DSP instructions  */
+			switch ((iw >> 16) & 0xf) {
+			case  0: debug("mia"); break;
+			case  8: debug("miaph"); break;
+			case 12: debug("miaBB"); break;
+			case 13: debug("miaTB"); break;
+			case 14: debug("miaBT"); break;
+			case 15: debug("miaTT"); break;
+			default: debug("UNKNOWN mia vector instruction?");
+			}
+			debug("%s\t", condition);
+			debug("acc%i,%s,%s\n", ((iw >> 5) & 7),
+			    arm_regname[iw & 15], arm_regname[r12]);
+			break;
+		}
+		if (iw & 0x10) {
+			debug("%s%s\t",
+			    (iw & 0x00100000)? "mrc" : "mcr", condition);
+			debug("%i,%i,r%i,cr%i,cr%i,%i",
+			    (int)((iw >> 8) & 15), (int)((iw >>21) & 7),
+			    (int)((iw >>12) & 15), (int)((iw >>16) & 15),
+			    (int)((iw >> 0) & 15), (int)((iw >> 5) & 7));
+		} else {
+			debug("cdp%s\t", condition);
+			debug("%i,%i,cr%i,cr%i,cr%i",
+			    (int)((iw >> 8) & 15),
+			    (int)((iw >>20) & 15),
+			    (int)((iw >>12) & 15),
+			    (int)((iw >>16) & 15),
+			    (int)((iw >> 0) & 15));
+			if ((iw >> 5) & 7)
+				debug(",0x%x", (int)((iw >> 5) & 7));
+		}
+		debug("\n");
+		break;
+	case 0xf:				/*  SWI  */
+		debug("swi%s\t", condition);
+		debug("0x%x\n", (int)(iw & 0x00ffffff));
+		break;
+	default:debug("UNIMPLEMENTED\n");
+	}
+
+	return sizeof(uint32_t);
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  arm_mcr_mrc():
+ *
+ *  Coprocessor register move.
+ *
+ *  The program counter should be synched before calling this function (to
+ *  make debug output with the correct PC value possible).
+ */
+void arm_mcr_mrc(struct cpu *cpu, uint32_t iword)
+{
+	int opcode1 = (iword >> 21) & 7;
+	int l_bit = (iword >> 20) & 1;
+	int crn = (iword >> 16) & 15;
+	int rd = (iword >> 12) & 15;
+	int cp_num = (iword >> 8) & 15;
+	int opcode2 = (iword >> 5) & 7;
+	int crm = iword & 15;
+
+	if (cpu->cd.arm.coproc[cp_num] != NULL)
+		cpu->cd.arm.coproc[cp_num](cpu, opcode1, opcode2, l_bit,
+		    crn, crm, rd);
+	else {
+		fatal("[ TODO: arm_mcr_mrc: pc=0x%08x, iword=0x%08x: "
+		    "cp_num=%i ]\n", (int)cpu->pc, iword, cp_num);
+
+		// arm_exception(cpu, ARM_EXCEPTION_UND);
+		/*  exit(1);  */
+	}
+}
+
+
+/*
+ *  arm_cdp():
+ *
+ *  Coprocessor operations.
+ *
+ *  The program counter should be synched before calling this function (to
+ *  make debug output with the correct PC value possible).
+ */
+void arm_cdp(struct cpu *cpu, uint32_t iword)
+{
+	fatal("[ arm_cdp: pc=0x%08x, iword=0x%08x ]\n", (int)cpu->pc, iword);
+	arm_exception(cpu, ARM_EXCEPTION_UND);
+	/*  exit(1);  */
+}
+
+
+/*****************************************************************************/
+
+
+#include "tmp_arm_tail.c"
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_arm.cc gxemul-0.7.0+dfsg/src/cpus/cpu_arm.cc
--- gxemul-0.6.2/src/cpus/cpu_arm.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_arm.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,2572 +0,0 @@
-/*
- *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  ARM CPU emulation.
- *
- *  A good source of quick info on ARM instruction encoding:
- *  http://www.pinknoise.demon.co.uk/ARMinstrs/ARMinstrs.html
- *
- *  Another one, with details about THUMB:
- *  http://engold.ui.ac.ir/~nikmehr/Appendix_B2.pdf
- *
- *  and yet another one, with descriptions about THUMB semantics:
- *  https://web.eecs.umich.edu/~prabal/teaching/eecs373-f10/readings/ARM_QRC0006_UAL16.pdf
- *
- *  And one with the newer ARM v7 instructions:
- *  http://vision.gel.ulaval.ca/~jflalonde/cours/1001/h17/docs/ARM_v7.pdf
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <ctype.h>
-#include <unistd.h>
-
-#include "arm_cpu_types.h"
-#include "cpu.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "of.h"
-#include "settings.h"
-#include "symbol.h"
-
-#define DYNTRANS_32
-#include "tmp_arm_head.cc"
-
-
-/*  ARM symbolic register names and condition strings:  */
-static const char *arm_regname[N_ARM_REGS] = ARM_REG_NAMES;
-static const char *arm_condition_string[16] = ARM_CONDITION_STRINGS;
-
-/*  Data Processing Instructions:  */
-static const char *arm_dpiname[16] = ARM_DPI_NAMES;
-static int arm_dpi_uses_d[16] = { 1,1,1,1,1,1,1,1,0,0,0,0,1,1,1,1 };
-static int arm_dpi_uses_n[16] = { 1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,0 };
-
-static const char *arm_thumb_dpiname[16] = ARM_THUMB_DPI_NAMES;
-
-static int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE;
-
-extern uint8_t condition_hi[16];
-extern uint8_t condition_ge[16];
-extern uint8_t condition_gt[16];
-
-/*  For quick_pc_to_pointers():  */
-void arm_pc_to_pointers(struct cpu *cpu);
-#include "quick_pc_to_pointers.h"
-
-void arm_irq_interrupt_assert(struct interrupt *interrupt);
-void arm_irq_interrupt_deassert(struct interrupt *interrupt);
-
-
-/*
- *  arm_cpu_new():
- *
- *  Create a new ARM cpu object by filling the CPU struct.
- *  Return 1 on success, 0 if cpu_type_name isn't a valid ARM processor.
- */
-int arm_cpu_new(struct cpu *cpu, struct memory *mem,
-	struct machine *machine, int cpu_id, char *cpu_type_name)
-{
-	int i, found;
-	struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS;
-
-	/*  Scan the list for this cpu type:  */
-	i = 0; found = -1;
-	while (i >= 0 && cpu_type_defs[i].name != NULL) {
-		if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
-			found = i;
-			break;
-		}
-		i++;
-	}
-	if (found == -1)
-		return 0;
-
-	cpu->run_instr = arm_run_instr;
-	cpu->memory_rw = arm_memory_rw;
-	cpu->update_translation_table = arm_update_translation_table;
-	cpu->invalidate_translation_caches =
-	    arm_invalidate_translation_caches;
-	cpu->invalidate_code_translation = arm_invalidate_code_translation;
-	cpu->translate_v2p = arm_translate_v2p;
-
-	cpu->cd.arm.cpu_type = cpu_type_defs[found];
-	cpu->name            = strdup(cpu->cd.arm.cpu_type.name);
-	cpu->is_32bit        = 1;
-	cpu->byte_order      = EMUL_LITTLE_ENDIAN;
-
-	cpu->vaddr_mask = 0x00000000ffffffffULL;
-
-	cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F;
-	cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32
-	    | ARM_CONTROL_CACHE | ARM_CONTROL_ICACHE | ARM_CONTROL_ALIGN;
-	/*  TODO: default auxctrl contents  */
-
-	if (cpu->machine->prom_emulation) {
-		cpu->cd.arm.cpsr |= ARM_MODE_SVC32;
-		cpu->cd.arm.control |= ARM_CONTROL_S;
-	} else {
-		cpu->cd.arm.cpsr |= ARM_MODE_SVC32;
-		cpu->cd.arm.control |= ARM_CONTROL_R;
-	}
-
-	/*  Only show name and caches etc for CPU nr 0:  */
-	if (cpu_id == 0) {
-		debug("%s", cpu->name);
-		if (cpu->cd.arm.cpu_type.icache_shift != 0 ||
-		    cpu->cd.arm.cpu_type.dcache_shift != 0) {
-			int isize = cpu->cd.arm.cpu_type.icache_shift;
-			int dsize = cpu->cd.arm.cpu_type.dcache_shift;
-			if (isize != 0)
-				isize = 1 << (isize - 10);
-			if (dsize != 0)
-				dsize = 1 << (dsize - 10);
-			debug(" (I+D = %i+%i KB)", isize, dsize);
-		}
-	}
-
-	/*  TODO: Some of these values (iway and dway) aren't used yet:  */
-	cpu->cd.arm.cachetype =
-	      (5 << ARM_CACHETYPE_CLASS_SHIFT)
-	    | (1 << ARM_CACHETYPE_HARVARD_SHIFT)
-	    | ((cpu->cd.arm.cpu_type.dcache_shift - 9) <<
-		ARM_CACHETYPE_DSIZE_SHIFT)
-	    | (5 << ARM_CACHETYPE_DASSOC_SHIFT)		/*  32-way  */
-	    | (2 << ARM_CACHETYPE_DLINE_SHIFT)		/*  8 words/line  */
-	    | ((cpu->cd.arm.cpu_type.icache_shift - 9) <<
-		ARM_CACHETYPE_ISIZE_SHIFT)
-	    | (5 << ARM_CACHETYPE_IASSOC_SHIFT)		/*  32-way  */
-	    | (2 << ARM_CACHETYPE_ILINE_SHIFT);		/*  8 words/line  */
-
-	/*  Coprocessor 15 = the system control coprocessor.  */
-	cpu->cd.arm.coproc[15] = arm_coproc_15;
-
-	/*  Coprocessor 14 for XScale:  */
-	if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE)
-		cpu->cd.arm.coproc[14] = arm_coproc_xscale_14;
-
-	/*
-	 *  NOTE/TODO: Ugly hack for OpenFirmware emulation:
-	 */
-	if (cpu->machine->prom_emulation) {
-		cpu->cd.arm.of_emul_addr = cpu->machine->physical_ram_in_mb
-		    * 1048576 - 8;
-		store_32bit_word(cpu, cpu->cd.arm.of_emul_addr, 0xef8c64be);
-	}
-
-	cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28;
-
-	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
-	for (i=0; i<N_ARM_REGS - 1; i++)
-		CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]);
-
-	CPU_SETTINGS_ADD_REGISTER32("cpsr", cpu->cd.arm.cpsr);
-
-	/*  Register the CPU's "IRQ" and "FIQ" interrupts:  */
-	{
-		struct interrupt templ;
-		char name[50];
-		snprintf(name, sizeof(name), "%s.irq", cpu->path);
-
-                memset(&templ, 0, sizeof(templ));
-                templ.line = 0;
-                templ.name = name;
-                templ.extra = cpu;
-                templ.interrupt_assert = arm_irq_interrupt_assert;
-                templ.interrupt_deassert = arm_irq_interrupt_deassert;
-                interrupt_handler_register(&templ);
-
-		/*  FIQ: TODO  */
-        }
-
-	return 1;
-}
-
-
-/*
- *  arm_setup_initial_translation_table():
- *
- *  When booting kernels (such as OpenBSD or NetBSD) directly, it is assumed
- *  that the MMU is already enabled by the boot-loader. This function tries
- *  to emulate that.
- */
-void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr)
-{
-	unsigned char nothing[16384];
-	unsigned int i, j;
-
-	cpu->cd.arm.control |= ARM_CONTROL_MMU;
-	cpu->translate_v2p = arm_translate_v2p_mmu;
-	cpu->cd.arm.dacr |= 0x00000003;
-	cpu->cd.arm.ttb = ttb_addr;
-
-	memset(nothing, 0, sizeof(nothing));
-	cpu->memory_rw(cpu, cpu->mem, cpu->cd.arm.ttb, nothing,
-	    sizeof(nothing), MEM_WRITE, PHYSICAL | NO_EXCEPTIONS);
-	for (i=0; i<256; i++)
-		for (j=0x0; j<=0xf; j++) {
-			unsigned char descr[4];
-			uint32_t addr = cpu->cd.arm.ttb +
-			    (((j << 28) + (i << 20)) >> 18);
-			uint32_t d = (1048576*i) | 0xc02;
-
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-				descr[0] = d;       descr[1] = d >> 8;
-				descr[2] = d >> 16; descr[3] = d >> 24;
-			} else {
-				descr[3] = d;       descr[2] = d >> 8;
-				descr[1] = d >> 16; descr[0] = d >> 24;
-			}
-			cpu->memory_rw(cpu, cpu->mem, addr, &descr[0],
-			    sizeof(descr), MEM_WRITE, PHYSICAL | NO_EXCEPTIONS);
-		}
-}
-
-
-/*
- *  arm_translation_table_set_l1():
- */
-void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
-	uint32_t paddr)
-{
-	unsigned int i, j, vhigh = vaddr >> 28, phigh = paddr >> 28;
-
-	for (i=0; i<256; i++)
-		for (j=vhigh; j<=vhigh; j++) {
-			unsigned char descr[4];
-			uint32_t addr = cpu->cd.arm.ttb +
-			    (((j << 28) + (i << 20)) >> 18);
-			uint32_t d = ((phigh << 28) + 1048576*i) | 0xc02;
-
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-				descr[0] = d;       descr[1] = d >> 8;
-				descr[2] = d >> 16; descr[3] = d >> 24;
-			} else {
-				descr[3] = d;       descr[2] = d >> 8;
-				descr[1] = d >> 16; descr[0] = d >> 24;
-			}
-			cpu->memory_rw(cpu, cpu->mem, addr, &descr[0],
-			    sizeof(descr), MEM_WRITE, PHYSICAL | NO_EXCEPTIONS);
-		}
-}
-
-
-/*
- *  arm_translation_table_set_l1_b():
- */
-void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
-	uint32_t paddr)
-{
-	unsigned int i, j, vhigh = vaddr >> 24, phigh = paddr >> 24;
-
-	for (i=0; i<16; i++)
-		for (j=vhigh; j<=vhigh; j++) {
-			unsigned char descr[4];
-			uint32_t addr = cpu->cd.arm.ttb +
-			    (((j << 24) + (i << 20)) >> 18);
-			uint32_t d = ((phigh << 24) + 1048576*i) | 0xc02;
-
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-				descr[0] = d;       descr[1] = d >> 8;
-				descr[2] = d >> 16; descr[3] = d >> 24;
-			} else {
-				descr[3] = d;       descr[2] = d >> 8;
-				descr[1] = d >> 16; descr[0] = d >> 24;
-			}
-			cpu->memory_rw(cpu, cpu->mem, addr, &descr[0],
-			    sizeof(descr), MEM_WRITE, PHYSICAL | NO_EXCEPTIONS);
-		}
-}
-
-
-/*
- *  arm_cpu_dumpinfo():
- */
-void arm_cpu_dumpinfo(struct cpu *cpu)
-{
-	struct arm_cpu_type_def *ct = &cpu->cd.arm.cpu_type;
-
-	debug(" (I+D = %i+%i KB)\n",
-	    (1 << ct->icache_shift) / 1024, (1 << ct->dcache_shift) / 1024);
-}
-
-
-/*
- *  arm_cpu_list_available_types():
- *
- *  Print a list of available ARM CPU types.
- */
-void arm_cpu_list_available_types(void)
-{
-	int i, j;
-	struct arm_cpu_type_def tdefs[] = ARM_CPU_TYPE_DEFS;
-
-	i = 0;
-	while (tdefs[i].name != NULL) {
-		debug("%s", tdefs[i].name);
-		for (j=13 - strlen(tdefs[i].name); j>0; j--)
-			debug(" ");
-		i++;
-		if ((i % 5) == 0 || tdefs[i].name == NULL)
-			debug("\n");
-	}
-}
-
-
-/*
- *  arm_cpu_register_dump():
- *
- *  Dump cpu registers in a relatively readable format.
- *  
- *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
- *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
- */
-void arm_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
-{
-	char *symbol;
-	uint64_t offset;
-	int mode = cpu->cd.arm.cpsr & ARM_FLAG_MODE;
-	int i, x = cpu->cpu_id;
-
-	cpu->cd.arm.cpsr &= 0x0fffffff;
-	cpu->cd.arm.cpsr |= (cpu->cd.arm.flags << 28);
-
-	if (gprs) {
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    cpu->pc, &offset);
-		debug("cpu%i:  cpsr = ", x);
-		debug("%s%s%s%s%s%s%s%s%s%s%s",
-		    (cpu->cd.arm.cpsr & ARM_FLAG_N)? "N" : "n",
-		    (cpu->cd.arm.cpsr & ARM_FLAG_Z)? "Z" : "z",
-		    (cpu->cd.arm.cpsr & ARM_FLAG_C)? "C" : "c",
-		    (cpu->cd.arm.cpsr & ARM_FLAG_V)? "V" : "v",
-		    (cpu->cd.arm.cpsr & ARM_FLAG_Q)? "Q" : "q",
-		    (cpu->cd.arm.cpsr & ARM_FLAG_J)? "J" : "j",
-		    (cpu->cd.arm.cpsr & ARM_FLAG_E)? "E" : "e",
-		    (cpu->cd.arm.cpsr & ARM_FLAG_A)? "A" : "a",
-		    (cpu->cd.arm.cpsr & ARM_FLAG_I)? "I" : "i",
-		    (cpu->cd.arm.cpsr & ARM_FLAG_F)? "F" : "f",
-    		    (cpu->cd.arm.cpsr & ARM_FLAG_T)? "T" : "t");
-		if (mode < ARM_MODE_USR32)
-			debug("   pc =  0x%07x", (int)(cpu->pc & 0x03ffffff));
-		else
-			debug("   pc = 0x%08x", (int)cpu->pc);
-
-		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
-
-		for (i=0; i<N_ARM_REGS; i++) {
-			if ((i % 4) == 0)
-				debug("cpu%i:", x);
-			if (i != ARM_PC)
-				debug("  %s = 0x%08x", arm_regname[i],
-				    (int)cpu->cd.arm.r[i]);
-			if ((i % 4) == 3)
-				debug("\n");
-		}
-	}
-
-	if (coprocs & 1) {
-		int m = cpu->cd.arm.cpsr & ARM_FLAG_MODE;
-		debug("cpu%i:  cpsr = 0x%08x (", x, cpu->cd.arm.cpsr);
-		switch (m) {
-		case ARM_MODE_USR32:
-			debug("USR32)\n"); break;
-		case ARM_MODE_SYS32:
-			debug("SYS32)\n"); break;
-		case ARM_MODE_FIQ32:
-			debug("FIQ32)\n"); break;
-		case ARM_MODE_IRQ32:
-			debug("IRQ32)\n"); break;
-		case ARM_MODE_SVC32:
-			debug("SVC32)\n"); break;
-		case ARM_MODE_ABT32:
-			debug("ABT32)\n"); break;
-		case ARM_MODE_UND32:
-			debug("UND32)\n"); break;
-		default:debug("unimplemented)\n");
-		}
-
-		if (m != ARM_MODE_USR32 && m != ARM_MODE_SYS32) {
-			debug("cpu%i:  usr r8-14:", x);
-			for (i=0; i<7; i++)
-				debug(" %08x", cpu->cd.arm.default_r8_r14[i]);
-			debug("\n");
-		}
-
-		if (m != ARM_MODE_FIQ32) {
-			debug("cpu%i:  fiq r8-14:", x);
-			for (i=0; i<7; i++)
-				debug(" %08x", cpu->cd.arm.fiq_r8_r14[i]);
-			debug("\n");
-		}
-
-		if (m != ARM_MODE_IRQ32) {
-			debug("cpu%i:  irq r13-14:", x);
-			for (i=0; i<2; i++)
-				debug(" %08x", cpu->cd.arm.irq_r13_r14[i]);
-			debug("\n");
-		}
-
-		if (m != ARM_MODE_SVC32) {
-			debug("cpu%i:  svc r13-14:", x);
-			for (i=0; i<2; i++)
-				debug(" %08x", cpu->cd.arm.svc_r13_r14[i]);
-			debug("\n");
-		}
-
-		if (m != ARM_MODE_ABT32) {
-			debug("cpu%i:  abt r13-14:", x);
-			for (i=0; i<2; i++)
-				debug(" %08x", cpu->cd.arm.abt_r13_r14[i]);
-			debug("\n");
-		}
-
-		if (m != ARM_MODE_UND32) {
-			debug("cpu%i:  und r13-14:", x);
-			for (i=0; i<2; i++)
-				debug(" %08x", cpu->cd.arm.und_r13_r14[i]);
-			debug("\n");
-		}
-	}
-
-	if (coprocs & 2) {
-		debug("cpu%i:  control = 0x%08x\n", x, cpu->cd.arm.control);
-		debug("cpu%i:      MMU:               %s\n", x,
-		    cpu->cd.arm.control &
-		    ARM_CONTROL_MMU? "enabled" : "disabled");
-		debug("cpu%i:      alignment checks:  %s\n", x,
-		    cpu->cd.arm.control &
-		    ARM_CONTROL_ALIGN? "enabled" : "disabled");
-		debug("cpu%i:      [data] cache:      %s\n", x,
-		    cpu->cd.arm.control &
-		    ARM_CONTROL_CACHE? "enabled" : "disabled");
-		debug("cpu%i:      instruction cache: %s\n", x,
-		    cpu->cd.arm.control &
-		    ARM_CONTROL_ICACHE? "enabled" : "disabled");
-		debug("cpu%i:      write buffer:      %s\n", x,
-		    cpu->cd.arm.control &
-		    ARM_CONTROL_WBUFFER? "enabled" : "disabled");
-		debug("cpu%i:      prog32:            %s\n", x,
-		    cpu->cd.arm.control &
-		    ARM_CONTROL_PROG32? "yes" : "no (using prog26)");
-		debug("cpu%i:      data32:            %s\n", x,
-		    cpu->cd.arm.control &
-		    ARM_CONTROL_DATA32? "yes" : "no (using data26)");
-		debug("cpu%i:      endianness:        %s\n", x,
-		    cpu->cd.arm.control &
-		    ARM_CONTROL_BIG? "big endian" : "little endian");
-		debug("cpu%i:      high vectors:      %s\n", x,
-		    cpu->cd.arm.control &
-		    ARM_CONTROL_V? "yes (0xffff0000)" : "no");
-
-		/*  TODO: auxctrl on which CPU types?  */
-		if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) {
-			debug("cpu%i:  auxctrl = 0x%08x\n", x,
-			    cpu->cd.arm.auxctrl);
-			debug("cpu%i:      minidata cache attr = 0x%x\n", x,
-			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_MD)
-			    >> ARM_AUXCTRL_MD_SHIFT);
-			debug("cpu%i:      page table memory attr: %i\n", x,
-			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_P)? 1 : 0);
-			debug("cpu%i:      write buffer coalescing: %s\n", x,
-			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_K)?
-			    "disabled" : "enabled");
-		}
-
-		debug("cpu%i:  ttb = 0x%08x  dacr = 0x%08x\n", x,
-		    cpu->cd.arm.ttb, cpu->cd.arm.dacr);
-		debug("cpu%i:  fsr = 0x%08x  far = 0x%08x\n", x,
-		    cpu->cd.arm.fsr, cpu->cd.arm.far);
-	}
-}
-
-
-/*
- *  arm_save_register_bank():
- */
-void arm_save_register_bank(struct cpu *cpu)
-{
-	/*  Save away current registers:  */
-	switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
-	case ARM_MODE_USR32:
-	case ARM_MODE_SYS32:
-		memcpy(cpu->cd.arm.default_r8_r14,
-		    &cpu->cd.arm.r[8], sizeof(uint32_t) * 7);
-		break;
-	case ARM_MODE_FIQ32:
-		memcpy(cpu->cd.arm.fiq_r8_r14,
-		    &cpu->cd.arm.r[8], sizeof(uint32_t) * 7);
-		break;
-	case ARM_MODE_IRQ32:
-		memcpy(cpu->cd.arm.default_r8_r14,
-		    &cpu->cd.arm.r[8], sizeof(uint32_t) * 5);
-		cpu->cd.arm.irq_r13_r14[0] = cpu->cd.arm.r[13];
-		cpu->cd.arm.irq_r13_r14[1] = cpu->cd.arm.r[14];
-		break;
-	case ARM_MODE_SVC32:
-		memcpy(cpu->cd.arm.default_r8_r14,
-		    &cpu->cd.arm.r[8], sizeof(uint32_t) * 5);
-		cpu->cd.arm.svc_r13_r14[0] = cpu->cd.arm.r[13];
-		cpu->cd.arm.svc_r13_r14[1] = cpu->cd.arm.r[14];
-		break;
-	case ARM_MODE_ABT32:
-		memcpy(cpu->cd.arm.default_r8_r14,
-		    &cpu->cd.arm.r[8], sizeof(uint32_t) * 5);
-		cpu->cd.arm.abt_r13_r14[0] = cpu->cd.arm.r[13];
-		cpu->cd.arm.abt_r13_r14[1] = cpu->cd.arm.r[14];
-		break;
-	case ARM_MODE_UND32:
-		memcpy(cpu->cd.arm.default_r8_r14,
-		    &cpu->cd.arm.r[8], sizeof(uint32_t) * 5);
-		cpu->cd.arm.und_r13_r14[0] = cpu->cd.arm.r[13];
-		cpu->cd.arm.und_r13_r14[1] = cpu->cd.arm.r[14];
-		break;
-	default:fatal("arm_save_register_bank: unimplemented mode %i\n",
-		    cpu->cd.arm.cpsr & ARM_FLAG_MODE);
-		exit(1);
-	}
-}
-
-
-/*
- *  arm_load_register_bank():
- */
-void arm_load_register_bank(struct cpu *cpu)
-{
-	/*  Load new registers:  */
-	switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
-	case ARM_MODE_USR32:
-	case ARM_MODE_SYS32:
-		memcpy(&cpu->cd.arm.r[8],
-		    cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 7);
-		break;
-	case ARM_MODE_FIQ32:
-		memcpy(&cpu->cd.arm.r[8], cpu->cd.arm.fiq_r8_r14,
-		    sizeof(uint32_t) * 7);
-		break;
-	case ARM_MODE_IRQ32:
-		memcpy(&cpu->cd.arm.r[8],
-		    cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5);
-		cpu->cd.arm.r[13] = cpu->cd.arm.irq_r13_r14[0];
-		cpu->cd.arm.r[14] = cpu->cd.arm.irq_r13_r14[1];
-		break;
-	case ARM_MODE_SVC32:
-		memcpy(&cpu->cd.arm.r[8],
-		    cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5);
-		cpu->cd.arm.r[13] = cpu->cd.arm.svc_r13_r14[0];
-		cpu->cd.arm.r[14] = cpu->cd.arm.svc_r13_r14[1];
-		break;
-	case ARM_MODE_ABT32:
-		memcpy(&cpu->cd.arm.r[8],
-		    cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5);
-		cpu->cd.arm.r[13] = cpu->cd.arm.abt_r13_r14[0];
-		cpu->cd.arm.r[14] = cpu->cd.arm.abt_r13_r14[1];
-		break;
-	case ARM_MODE_UND32:
-		memcpy(&cpu->cd.arm.r[8],
-		    cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5);
-		cpu->cd.arm.r[13] = cpu->cd.arm.und_r13_r14[0];
-		cpu->cd.arm.r[14] = cpu->cd.arm.und_r13_r14[1];
-		break;
-	default:fatal("arm_load_register_bank: unimplemented mode %i\n",
-		    cpu->cd.arm.cpsr & ARM_FLAG_MODE);
-		exit(1);
-	}
-}
-
-
-/*
- *  arm_exception():
- */
-void arm_exception(struct cpu *cpu, int exception_nr)
-{
-	int oldmode, newmode;
-	uint32_t retaddr;
-
-	if (exception_nr < 0 || exception_nr >= N_ARM_EXCEPTIONS) {
-		fatal("arm_exception(): exception_nr = %i\n", exception_nr);
-		exit(1);
-	}
-
-	retaddr = cpu->pc;
-
-	if (!quiet_mode) {
-		debug("[ arm_exception(): ");
-		switch (exception_nr) {
-		case ARM_EXCEPTION_RESET:
-			fatal("RESET: TODO");
-			break;
-		case ARM_EXCEPTION_UND:
-			debug("UNDEFINED");
-			break;
-		case ARM_EXCEPTION_SWI:
-			debug("SWI");
-			break;
-		case ARM_EXCEPTION_PREF_ABT:
-			debug("PREFETCH ABORT");
-			break;
-		case ARM_EXCEPTION_IRQ:
-			debug("IRQ");
-			break;
-		case ARM_EXCEPTION_FIQ:
-			debug("FIQ");
-			break;
-		case ARM_EXCEPTION_DATA_ABT:
-			debug("DATA ABORT, far=0x%08x fsr=0x%02x",
-			    cpu->cd.arm.far, cpu->cd.arm.fsr);
-			break;
-		}
-		debug(" ]\n");
-	}
-
-	switch (exception_nr) {
-	case ARM_EXCEPTION_RESET:
-		cpu->running = 0;
-		fatal("ARM RESET: TODO");
-		exit(1);
-	case ARM_EXCEPTION_DATA_ABT:
-		retaddr += 4;
-		break;
-	}
-
-	retaddr += (cpu->cd.arm.cpsr & ARM_FLAG_T ? 2 : 4);
-
-	arm_save_register_bank(cpu);
-
-	cpu->cd.arm.cpsr &= 0x0fffffff;
-	cpu->cd.arm.cpsr |= (cpu->cd.arm.flags << 28);
-
-	switch (arm_exception_to_mode[exception_nr]) {
-	case ARM_MODE_SVC32:
-		cpu->cd.arm.spsr_svc = cpu->cd.arm.cpsr; break;
-	case ARM_MODE_ABT32:
-		cpu->cd.arm.spsr_abt = cpu->cd.arm.cpsr; break;
-	case ARM_MODE_UND32:
-		cpu->cd.arm.spsr_und = cpu->cd.arm.cpsr; break;
-	case ARM_MODE_IRQ32:
-		cpu->cd.arm.spsr_irq = cpu->cd.arm.cpsr; break;
-	case ARM_MODE_FIQ32:
-		cpu->cd.arm.spsr_fiq = cpu->cd.arm.cpsr; break;
-	default:fatal("arm_exception(): unimplemented exception nr\n");
-		exit(1);
-	}
-
-	/*
-	 *  Disable Thumb mode (because exception handlers always execute
-	 *  in ARM mode), set the exception mode, and disable interrupts:
-	 */
-	cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
-
-	oldmode = cpu->cd.arm.cpsr & ARM_FLAG_MODE;
-
-	cpu->cd.arm.cpsr &= ~ARM_FLAG_MODE;
-	cpu->cd.arm.cpsr |= arm_exception_to_mode[exception_nr];
-
-	/*
-	 *  Usually, an exception should change modes (so that saved status
-	 *  bits don't get lost). However, Linux on ARM seems to use floating
-	 *  point instructions in the kernel (!), and it emulates those using
-	 *  its own fp emulation code. This leads to a situation where we
-	 *  sometimes change from SVC32 to SVC32.
-	 */
-	newmode = cpu->cd.arm.cpsr & ARM_FLAG_MODE;
-	if (oldmode == newmode && oldmode != ARM_MODE_SVC32) {
-		fatal("[ WARNING! Exception caused no mode change? "
-		    "mode 0x%02x (pc=0x%x) ]\n", newmode, (int)cpu->pc);
-		/*  exit(1);  */
-	}
-
-	cpu->cd.arm.cpsr |= ARM_FLAG_I;
-	if (exception_nr == ARM_EXCEPTION_RESET ||
-	    exception_nr == ARM_EXCEPTION_FIQ)
-		cpu->cd.arm.cpsr |= ARM_FLAG_F;
-
-	/*  Load the new register bank, if we switched:  */
-	arm_load_register_bank(cpu);
-
-	/*
-	 *  Set the return address and new PC.
-	 *
-	 *  NOTE: r[ARM_PC] is also set; see cpu_arm_instr_loadstore.c for
-	 *  details. (If an exception occurs during a load into the pc
-	 *  register, the code in that file assumes that the r[ARM_PC]
-	 *  was changed to the address of the exception handler.)
-	 */
-	cpu->cd.arm.r[ARM_LR] = retaddr;
-	cpu->pc = cpu->cd.arm.r[ARM_PC] = exception_nr * 4 +
-	    ((cpu->cd.arm.control & ARM_CONTROL_V)? 0xffff0000 : 0);
-	quick_pc_to_pointers(cpu);
-}
-
-
-/*
- *  arm_cpu_tlbdump():
- *
- *  Called from the debugger to dump the TLB in a readable format.
- *  x is the cpu number to dump, or -1 to dump all CPUs.
- *
- *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
- *  just dumped.
- */
-void arm_cpu_tlbdump(struct machine *m, int x, int rawflag)
-{
-}
-
-
-/*
- *  arm_irq_interrupt_assert():
- *  arm_irq_interrupt_deassert():
- */
-void arm_irq_interrupt_assert(struct interrupt *interrupt)
-{
-	struct cpu *cpu = (struct cpu *) interrupt->extra;
-	cpu->cd.arm.irq_asserted = 1;
-}
-void arm_irq_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct cpu *cpu = (struct cpu *) interrupt->extra;
-	cpu->cd.arm.irq_asserted = 0;
-}
-
-
-/*
- *  arm_cpu_disassemble_instr_thumb():
- *
- *  Like arm_cpu_disassemble_instr below, but for THUMB encodings.
- *  Note that the disassbmly uses regular ARM mnemonics, not "THUMB
- *  assembly language".
- */                     
-int arm_cpu_disassemble_instr_thumb(struct cpu *cpu, unsigned char *ib,
-        int running, uint64_t dumpaddr)
-{
-	uint16_t iw;
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		iw = ib[0] + (ib[1]<<8);
-	else
-		iw = ib[1] + (ib[0]<<8);
-	debug("%04x    \t", (int)iw);
-
-	int main_opcode = (iw >> 12) & 15;
-	int r6 = (iw >> 6) & 7;
-	int rs_rb = (iw >> 3) & 7;
-	int rd = iw & 7;
-	int offset5 = (iw >> 6) & 0x1f;
-	int b_bit = (iw >> 12) & 1;
-	int l_bit = (iw >> 11) & 1;
-	int addsub_op = (iw >> 9) & 1;
-	int addsub_immediate = (iw >> 10) & 1;
-	int op11 = (iw >> 11) & 3;
-	int op10 = (iw >> 10) & 3;
-	int rd8 = (iw >> 8) & 7;
-	int op8 = (iw >> 8) & 3;
-	int h1 = (iw >> 7) & 1;
-	int h2 = (iw >> 6) & 1;
-	int condition_code = (iw >> 8) & 15;
-	const char* condition = arm_condition_string[condition_code];
-	const char* symbol;
-	uint64_t offset;
-	int tmp;
-	uint32_t tmp32;
-	
-	switch (main_opcode)
-	{
-	case 0x0:
-	case 0x1:
-		if (op11 <= 2) {
-			// Move shifted register.
-			debug("%ss\tr%i,r%i,#%i\n",
-				op11 & 1 ? "lsr" : (op11 & 2 ? "asr" : "lsl"),
-				rd,
-				rs_rb,				
-				offset5);
-		} else {
-			// Add/subtract.
-			debug("%s\tr%i,r%i,%s%i\n",
-				addsub_op ? "subs" : "adds",
-				rd,
-				rs_rb,
-				addsub_immediate ? "#" : "r",
-				r6);
-		}
-		break;
-
-	case 0x2:
-	case 0x3:
-		// Move/compare/add/subtract immediate.
-		rd = (iw >> 8) & 7;
-		if (op11 & 2) {
-			debug("%s\tr%i,r%i,#%i\n",
-				op11 & 1 ? "subs" : "adds",
-				rd, rd,
-				iw & 0xff);
-		} else {
-			debug("%s\tr%i,#%i\n",
-				op11 & 1 ? "cmp" : "movs",
-				rd,
-				iw & 0xff);
-		}
-		break;
-
-	case 0x4:
-		switch (op10) {
-		case 0:
-			// ALU operations.
-			debug("%s\t%s,%s",
-				arm_thumb_dpiname[(iw >> 6) & 15],
-				arm_regname[rd],
-				arm_regname[rs_rb]);
-			
-			if (running) {
-				debug("\t\t; %s = 0x%x", arm_regname[rd], cpu->cd.arm.r[rd]);
-				debug(", %s = 0x%x", arm_regname[rs_rb], cpu->cd.arm.r[rs_rb]);
-			}
-
-			debug("\n");
-			break;
-
-		case 1:
-			// Hi register operations / branch exchange.
-			if (h1)
-				rd += 8;
-			if (h2)
-				rs_rb += 8;
-			switch (op8) {
-			case 0:
-			case 1:
-			case 2:
-				if (h1 == 0 && h2 == 0) {
-					debug("TODO main_opcode = %i, op10 = %i, h1 AND h2 are zero?!\n", main_opcode, op10);
-				} else {
-					if (op8 == 0)
-						debug("add\tr%i,r%i,r%i\n", rd, rd, rs_rb);
-					else {
-						if (op8 == 2 && rd == rs_rb)
-							debug("nop\n");	// mov rX,rX
-						else {
-							debug("%s\t%s,%s",
-							    op8 == 1 ? "cmp" : "mov",
-							    	arm_regname[rd],
-							    	arm_regname[rs_rb]);
-							if (running) {
-								debug("\t\t; %s = 0x%x", arm_regname[rd], cpu->cd.arm.r[rd]);
-								debug(", %s = 0x%x", arm_regname[rs_rb], cpu->cd.arm.r[rs_rb]);
-							}
-							debug("\n");
-						}
-					}
-				}
-				break;
-			case 3:
-				if (h1 == 1) {
-					debug("TODO main_opcode = %i, op10 = %i, h1 set for BX?!\n", main_opcode, op10);
-				} else {
-					debug("bx\t%s\n", arm_regname[rs_rb]);
-
-					// Extra newline when returning from function.
-					// if (running && rs_rb == ARM_LR)
-					//	debug("\n");
-				}
-				break;
-			}
-			break;
-
-		case 2:
-		case 3:
-			// PC-relative load.
-			debug("ldr\t%s,[pc,#%i]\t; ",
-				arm_regname[rd8],
-				(iw & 0xff) * 4);
-
-			// Is this address calculation correct?
-			// It works with real code, but is not the same as that of
-			// http://engold.ui.ac.ir/~nikmehr/Appendix_B2.pdf
-			tmp = (dumpaddr & ~3) + 4 + (iw & 0xff) * 4;
-			debug("0x%x", (int)tmp);
-			symbol = get_symbol_name(&cpu->machine->symbol_context,
-			    tmp, &offset);
-			if (symbol != NULL)
-				debug(" <%s>", symbol);
-			debug("\n");
-			break;
-		}
-		break;
-
-	case 0x5:
-		// Load/Store with register offset.
-		switch ((iw >> 9) & 7) {
-		case 0:	debug("str"); break;
-		case 1:	debug("strh"); break;
-		case 2:	debug("strb"); break;
-		case 3:	debug("ldrsb"); break;
-		case 4:	debug("ldr"); break;
-		case 5:	debug("ldrh"); break;
-		case 6:	debug("ldrb"); break;
-		case 7:	debug("ldrsh"); break;
-		}
-		debug("\t%s,[%s,%s]\n",
-			arm_regname[rd],
-			arm_regname[rs_rb],
-			arm_regname[r6]);
-		break;
-		
-	case 0x6:
-	case 0x7:
-		// Load/Store with immediate offset.
-		debug("%s%s\tr%i,[r%i,#%i]\n",
-			l_bit ? "ldr" : "str",
-			b_bit ? "b" : "",
-			rd,
-			rs_rb,
-			offset5 * (b_bit ? sizeof(uint8_t) : sizeof(uint32_t)));
-		break;
-
-	case 0x8:
-		// Load/Store halfword.
-		debug("%sh\tr%i,[r%i,#%i]\n",
-			l_bit ? "ldr" : "str",
-			rd,
-			rs_rb,
-			offset5 * sizeof(uint16_t));
-		break;
-
-	case 0x9:
-		// Load/Store stack pointer relative.
-		debug("%s\t%s,[sp,#%i]\n",
-			l_bit ? "ldr" : "str",
-			arm_regname[rd8],
-			4 * (iw & 0xff));
-		break;
-
-	case 0xa:
-		// add rx, sp or pc plus imm
-		debug("add\t%s,%s,#%i\n",
-			arm_regname[rd8],
-			iw & 0x0800 ? "sp" : "pc",
-			4 * (iw & 0xff));
-		break;
-
-	case 0xb:
-		/*  Bits 11..8:  */
-		switch (condition_code) {
-		case 0x0:
-			tmp = (iw & 0x7f) << 2;
-			debug(iw & 0x80 ? "sub" : "add");
-			debug("\tsp,#%i\n", tmp);
-			break;
-		case 0x4:
-		case 0x5:
-		case 0xc:
-		case 0xd:
-			debug(condition_code & 8 ? "pop" : "push");
-			debug("\t{");
-			for (tmp=0; tmp<8; ++tmp) {
-				if (iw & (1 << tmp))
-					debug("%s,", arm_regname[tmp]);
-			}
-			if (condition_code & 1) {			
-				if (condition_code & 8)
-					debug("pc");
-				else
-					debug("lr");
-			}
-			debug("}\n");
-
-			// Extra newline when returning from function.
-			// if (running && (condition_code & 8) && (condition_code & 1))
-			//	debug("\n");
-			break;
-		default:
-			debug("TODO: unimplemented opcode 0x%x,0x%x\n", main_opcode, condition_code);
-		}
-		break;
-		
-	case 0xd:
-		if (condition_code < 0xe) {
-			// Conditional branch.
-			debug("b%s\t", condition);
-			tmp = (iw & 0xff) << 1;
-			if (tmp & 0x100)
-				tmp |= 0xfffffe00;
-			tmp = (int32_t)(dumpaddr + 4 + tmp);
-			debug("0x%x", (int)tmp);
-			symbol = get_symbol_name(&cpu->machine->symbol_context,
-			    tmp, &offset);
-			if (symbol != NULL)
-				debug(" \t<%s>", symbol);
-			debug("\n");
-		} else if (condition_code == 0xf) {
-			debug("swi\t#0x%x\n", iw & 0xff);
-		} else {
-			debug("UNIMPLEMENTED\n");
-		}
-		break;
-
-	case 0xe:
-		// Unconditional branch.
-		if (iw & 0x0800) {
-			uint32_t addr = (dumpaddr + 4 + (cpu->cd.arm.tmp_branch + (((iw >> 1) & 0x3ff) << 2))) & ~3;
-			
-			debug("blx\t");
-			if (running) {
-				debug("0x%x", addr);
-				symbol = get_symbol_name(&cpu->machine->symbol_context, addr, &offset);
-				if (symbol != NULL)
-					debug(" \t<%s>", symbol);
-				debug("\n");
-			} else
-				debug("offset depending on prefix at runtime\n");
-		} else {
-			tmp = (iw & 0x7ff) << 1;
-			if (tmp & 0x800)
-				tmp |= 0xfffff000;
-			tmp = (int32_t)(dumpaddr + 4 + tmp);
-			debug("b\t0x%x", (int)tmp);
-			symbol = get_symbol_name(&cpu->machine->symbol_context, tmp, &offset);
-			if (symbol != NULL)
-				debug(" \t<%s>", symbol);
-			debug("\n");
-		}
-		break;
-
-	case 0xf:
-		if (iw & 0x0800) {
-			uint32_t addr = (dumpaddr + 2 + (cpu->cd.arm.tmp_branch + ((iw & 0x7ff) << 1)));
-			
-			debug("bl\t");
-			if (running) {
-				debug("0x%x", addr);
-				symbol = get_symbol_name(&cpu->machine->symbol_context, addr, &offset);
-				if (symbol != NULL)
-					debug(" \t<%s>", symbol);
-				debug("\n");
-			} else
-				debug("offset depending on prefix at runtime\n");
-		} else {
-			tmp32 = iw & 0x07ff;
-			if (tmp32 & 0x0400)
-				tmp32 |= 0xfffff800;
-			tmp32 <<= 12;
-			debug("bprefix\t0x%x\n", tmp32);
-		}
-		break;
-
-	default:
-		debug("TODO: unimplemented opcode 0x%x\n", main_opcode);
-	}
-
-	return sizeof(uint16_t);
-}
-
-
-/*
- *  arm_cpu_interpret_thumb_SLOW():
- *
- *  Slow interpretation of THUMB instructions.
- *
- *  TODO: Either replace this with dyntrans in the old framework, or
- *  implement ARM (including THUMB) in the new framework. :-)
- *  For now, this is better than nothing.
- */
-int arm_cpu_interpret_thumb_SLOW(struct cpu *cpu)
-{
-	uint16_t iw;
-	uint8_t ib[sizeof(uint16_t)];
-	uint32_t addr = cpu->pc & ~1;
-
-	if (!(cpu->pc & 1) || !(cpu->cd.arm.cpsr & ARM_FLAG_T)) {
-		fatal("arm_cpu_interpret_thumb_SLOW called when not in "
-			"THUMB mode?\n");
-		cpu->running = 0;
-		return 0;
-	}
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, &ib[0],
-			sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
-		fatal("arm_cpu_interpret_thumb_SLOW(): could not read "
-			"the instruction\n");
-		cpu->running = 0;
-		return 0;
-	}
-	
-	if (cpu->machine->instruction_trace) {
-		uint64_t offset;
-		char* symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    addr, &offset);
-		if (symbol != NULL && offset == 0)
-			debug("<%s>\n", symbol);
-
-		if (cpu->machine->ncpus > 1)
-			debug("cpu%i:\t", cpu->cpu_id);
-
-		debug("%08x:  ", (int)addr & ~1);
-		arm_cpu_disassemble_instr_thumb(cpu, ib, 1, cpu->pc);
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		iw = ib[0] + (ib[1]<<8);
-	else
-		iw = ib[1] + (ib[0]<<8);
-
-	cpu->ninstrs ++;
-
-	int main_opcode = (iw >> 12) & 15;
-	int condition_code = (iw >> 8) & 15;
-	int op10 = (iw >> 10) & 3;
-	int op11_8 = (iw >> 8) & 15;
-	int rd8 = (iw >> 8) & 7;
-	int r6 = (iw >> 6) & 7;
-	int r3 = (iw >> 3) & 7;
-	int rd = (iw >> 0) & 7;
-	int hd = (iw >> 7) & 1;
-	int hm = (iw >> 6) & 1;
-	int imm6 = (iw >> 6) & 31;
-	uint8_t word[sizeof(uint32_t)];
-	uint32_t tmp;
-	int t, len, isLoad;
-
-	switch (main_opcode)
-	{
-	case 0x0:
-		if (iw & 0x0800) {
-			// lsr
-			tmp = cpu->cd.arm.r[r3];
-			if (imm6 > 1)
-				tmp >>= (imm6 - 1);
-			cpu->cd.arm.r[rd] = cpu->cd.arm.r[r3] >> imm6;
-			tmp &= 1;
-		} else {
-			// lsl
-			tmp = cpu->cd.arm.r[r3];
-			if (imm6 > 1)
-				tmp <<= (imm6 - 1);
-			cpu->cd.arm.r[rd] = cpu->cd.arm.r[r3] << imm6;
-			tmp >>= 31;
-		}
-		cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-		if (cpu->cd.arm.r[rd] == 0)
-			cpu->cd.arm.flags |= ARM_F_Z;
-		if ((int32_t)cpu->cd.arm.r[rd] < 0)
-			cpu->cd.arm.flags |= ARM_F_N;
-		if (imm6 != 0) {
-			// tmp is "last bit shifted out"
-			cpu->cd.arm.flags &= ~ARM_F_C;
-			if (tmp)
-				cpu->cd.arm.flags |= ARM_F_C;
-		}
-		break;
-
-	case 0x1:
-		if (!(iw & 0x0800)) {
-			// asr
-			tmp = cpu->cd.arm.r[r3];
-			if (imm6 > 1)
-				tmp = (int32_t)tmp >> (imm6 - 1);
-			cpu->cd.arm.r[rd] = (int32_t)cpu->cd.arm.r[r3] >> imm6;
-			tmp &= 1;
-			cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-			if (cpu->cd.arm.r[rd8] == 0)
-				cpu->cd.arm.flags |= ARM_F_Z;
-			if ((int32_t)cpu->cd.arm.r[rd8] < 0)
-				cpu->cd.arm.flags |= ARM_F_N;
-			if (imm6 != 0) {
-				// tmp is "last bit shifted out"
-				cpu->cd.arm.flags &= ~ARM_F_C;
-				if (tmp)
-					cpu->cd.arm.flags |= ARM_F_C;
-			}
-		} else {
-			// add or sub
-			int isSub = iw & 0x0200;
-			int isImm3 = iw & 0x0400;
-			uint64_t old = cpu->cd.arm.r[r3];
-			uint64_t tmp64 = isImm3 ? r6 : cpu->cd.arm.r[r6];
-			tmp64 = (uint32_t)(isSub ? -tmp64 : tmp64);
-			uint64_t result = old + tmp64;
-			cpu->cd.arm.r[rd] = result;
-			cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N | ARM_F_C | ARM_F_V);
-			if (result == 0)
-				cpu->cd.arm.flags |= ARM_F_Z;
-			if ((int32_t)result < 0)
-				cpu->cd.arm.flags |= ARM_F_N;
-			if (result & 0x100000000ULL)
-				cpu->cd.arm.flags |= ARM_F_C;
-			if (result & 0x80000000) {
-				if ((tmp64 & 0x80000000) == 0 && (old & 0x80000000) == 0)
-					cpu->cd.arm.flags |= ARM_F_V;
-			} else {
-				if ((tmp64 & 0x80000000) != 0 && (old & 0x80000000) != 0)
-					cpu->cd.arm.flags |= ARM_F_V;
-			}
-		}
-		break;
-
-	case 0x2:
-		// movs or cmp
-		if (iw & 0x0800) {
-			uint64_t old = cpu->cd.arm.r[rd8];
-			uint64_t tmp64 = (uint32_t)(-(iw & 0xff));
-			uint64_t result = old + tmp64;
-			cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N | ARM_F_C | ARM_F_V);
-			if (result == 0)
-				cpu->cd.arm.flags |= ARM_F_Z;
-			if ((int32_t)result < 0)
-				cpu->cd.arm.flags |= ARM_F_N;
-			if (result & 0x100000000ULL)
-				cpu->cd.arm.flags |= ARM_F_C;
-			if (result & 0x80000000) {
-				if ((tmp64 & 0x80000000) == 0 && (old & 0x80000000) == 0)
-					cpu->cd.arm.flags |= ARM_F_V;
-			} else {
-				if ((tmp64 & 0x80000000) != 0 && (old & 0x80000000) != 0)
-					cpu->cd.arm.flags |= ARM_F_V;
-			}
-		} else {
-			cpu->cd.arm.r[rd8] = iw & 0xff;
-			cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-			if (cpu->cd.arm.r[rd8] == 0)
-				cpu->cd.arm.flags |= ARM_F_Z;
-		}
-		break;
-
-	case 0x3:
-		// adds or sub
-		{
-			uint64_t old = cpu->cd.arm.r[rd8];
-			uint64_t tmp64 = iw & 0xff;
-			
-			if (iw & 0x0800)
-				tmp64 = (uint32_t)(-tmp64);
-
-			uint64_t result = old + tmp64;
-			cpu->cd.arm.r[rd8] = result;
-
-			cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N | ARM_F_C | ARM_F_V);
-			if (result == 0)
-				cpu->cd.arm.flags |= ARM_F_Z;
-			if ((int32_t)result < 0)
-				cpu->cd.arm.flags |= ARM_F_N;
-			if (result & 0x100000000ULL)
-				cpu->cd.arm.flags |= ARM_F_C;
-			if (result & 0x80000000) {
-				if ((tmp64 & 0x80000000) == 0 && (old & 0x80000000) == 0)
-					cpu->cd.arm.flags |= ARM_F_V;
-			} else {
-				if ((tmp64 & 0x80000000) != 0 && (old & 0x80000000) != 0)
-					cpu->cd.arm.flags |= ARM_F_V;
-			}
-		}
-		break;
-
-	case 0x4:
-		switch (op10) {
-		case 0:
-			// "DPIs":
-			switch ((iw >> 6) & 15) {
-			case 0:// ands
-				cpu->cd.arm.r[rd] &= cpu->cd.arm.r[r3];
-				cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-				if (cpu->cd.arm.r[rd] == 0)
-					cpu->cd.arm.flags |= ARM_F_Z;
-				if ((int32_t)cpu->cd.arm.r[rd] < 0)
-					cpu->cd.arm.flags |= ARM_F_N;
-				break;
-			case 1:// eors
-				cpu->cd.arm.r[rd] ^= cpu->cd.arm.r[r3];
-				cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-				if (cpu->cd.arm.r[rd] == 0)
-					cpu->cd.arm.flags |= ARM_F_Z;
-				if ((int32_t)cpu->cd.arm.r[rd] < 0)
-					cpu->cd.arm.flags |= ARM_F_N;
-				break;
-			case 7:// rors
-				{
-					int amount = cpu->cd.arm.r[r3] & 0xff;
-					for (int i = 0; i < (amount & 31); ++i) {
-						int c = cpu->cd.arm.r[rd] & 1;
-						cpu->cd.arm.r[rd] >>= 1;
-						cpu->cd.arm.flags &= ~ARM_F_C;
-						if (c) {
-							cpu->cd.arm.flags |= ARM_F_C;
-							cpu->cd.arm.r[rd] |= 0x80000000;
-						}
-					}
-					
-					// Rotating right by e.g. 32 means that the C flag
-					// should be updated, but the register isn't
-					// really rotated.
-					if (amount != 0 && (amount & 31) == 0) {
-						cpu->cd.arm.flags &= ~ARM_F_C;
-						if (cpu->cd.arm.r[rd] & 0x80000000)
-							cpu->cd.arm.flags |= ARM_F_C;
-					}
-					
-					if (cpu->cd.arm.r[rd] == 0)
-						cpu->cd.arm.flags |= ARM_F_Z;
-					if ((int32_t)cpu->cd.arm.r[rd] < 0)
-						cpu->cd.arm.flags |= ARM_F_N;
-				}
-				break;
-			case 8:// tst
-				tmp = cpu->cd.arm.r[rd] & cpu->cd.arm.r[r3];
-				cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-				if (tmp == 0)
-					cpu->cd.arm.flags |= ARM_F_Z;
-				if ((int32_t)tmp < 0)
-					cpu->cd.arm.flags |= ARM_F_N;
-				break;
-			case 10:	// cmp
-				{
-					uint64_t old = cpu->cd.arm.r[rd];
-					uint64_t tmp64 = (uint32_t) (-cpu->cd.arm.r[r3]);
-					uint64_t result = old + tmp64;
-					cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N | ARM_F_C | ARM_F_V);
-					if (result == 0)
-						cpu->cd.arm.flags |= ARM_F_Z;
-					if ((int32_t)result < 0)
-						cpu->cd.arm.flags |= ARM_F_N;
-					if (result & 0x100000000ULL)
-						cpu->cd.arm.flags |= ARM_F_C;
-					if (result & 0x80000000) {
-						if ((tmp64 & 0x80000000) == 0 && (old & 0x80000000) == 0)
-							cpu->cd.arm.flags |= ARM_F_V;
-					} else {
-						if ((tmp64 & 0x80000000) != 0 && (old & 0x80000000) != 0)
-							cpu->cd.arm.flags |= ARM_F_V;
-					}
-				}
-				break;
-			case 12:// orrs
-				cpu->cd.arm.r[rd] |= cpu->cd.arm.r[r3];
-				cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-				if (cpu->cd.arm.r[rd] == 0)
-					cpu->cd.arm.flags |= ARM_F_Z;
-				if ((int32_t)cpu->cd.arm.r[rd] < 0)
-					cpu->cd.arm.flags |= ARM_F_N;
-				break;
-			case 13:// muls
-				cpu->cd.arm.r[rd] *= cpu->cd.arm.r[r3];
-				cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-				if (cpu->cd.arm.r[rd] == 0)
-					cpu->cd.arm.flags |= ARM_F_Z;
-				if ((int32_t)cpu->cd.arm.r[rd] < 0)
-					cpu->cd.arm.flags |= ARM_F_N;
-				break;
-			default:
-				debug("TODO: unimplemented DPI %i at pc 0x%08x\n", (iw >> 6) & 15, (int)cpu->pc);
-				cpu->running = 0;
-				return 0;
-			}
-			break;
-		case 1:
-			switch (op11_8) {
-			case 6:
-				if (hd)
-					rd += 8;
-				if (hm)
-					r3 += 8;
-				cpu->cd.arm.r[rd] = cpu->cd.arm.r[r3];
-				if (r3 == ARM_PC) {
-					if (cpu->pc & 1) {
-						debug("TODO: double check with manual whether it is correct to use old pc + 8 here; at pc 0x%08x\n", (int)cpu->pc);
-						cpu->running = 0;
-						return 0;
-					}
-					cpu->cd.arm.r[rd] = cpu->pc + 8;
-				}
-				if (rd == ARM_PC) {
-					cpu->pc = cpu->cd.arm.r[rd];
-					cpu->cd.arm.cpsr |= ARM_FLAG_T;
-					if (!(cpu->pc & 1))
-						cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
-					cpu->pc = addr - sizeof(uint16_t);
-				}
-				break;
-			case 7:
-				if ((iw & 0xff87) == 0x4700) {
-					//  bx
-					int rm = (iw >> 3) & 15;
-					//  Note: pc will be increased by 2 further down!
-					cpu->pc = cpu->cd.arm.r[rm] - sizeof(uint16_t);
-					if (!(cpu->pc & 1))
-						cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
-					if (rm == ARM_LR && cpu->machine->show_trace_tree)
-						cpu_functioncall_trace_return(cpu);
-				} else {
-					debug("TODO: unimplemented opcode 0x%x,%i at pc 0x%08x\n", main_opcode, op11_8, (int)cpu->pc);
-					cpu->running = 0;
-					return 0;
-				}
-				break;
-			default:
-				debug("TODO: unimplemented opcode 0x%x,%i at pc 0x%08x\n", main_opcode, op11_8, (int)cpu->pc);
-				cpu->running = 0;
-				return 0;
-			}
-			break;
-
-		case 2:
-		case 3:
-			// PC-relative load.
-			// Is this address calculation correct?
-			// It works with real code, but is not the same as that of
-			// http://engold.ui.ac.ir/~nikmehr/Appendix_B2.pdf
-			tmp = (addr & ~3) + 4 + (iw & 0xff) * 4;
-
-			if (!cpu->memory_rw(cpu, cpu->mem, tmp, &word[0],
-					sizeof(word), MEM_READ, CACHE_INSTRUCTION)) {
-				fatal("arm_cpu_interpret_thumb_SLOW(): could not load pc-relative word\n");
-				cpu->running = 0;
-				return 0;
-			}
-
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-				tmp = word[0] + (word[1]<<8) + (word[2]<<16) + (word[3]<<24);
-			else
-				tmp = word[3] + (word[2]<<8) + (word[1]<<16) + (word[0]<<24);
-
-			cpu->cd.arm.r[rd8] = tmp;
-			break;
-
-		default:
-			debug("TODO: unimplemented opcode 0x%x,%i at pc 0x%08x\n", main_opcode, op10, (int)cpu->pc);
-			cpu->running = 0;
-			return 0;
-		}
-		break;
-
-	case 0x6:
-	case 0x7:
-	case 0x8:
-		// Load/Store with immediate offset.
-		len = main_opcode == 6 ? 4 : (main_opcode == 7 ? 1 : 2);
-		isLoad = iw & 0x0800;
-		addr = (cpu->cd.arm.r[r3] + imm6 * len) & ~(len - 1);
-		tmp = 0;
-
-		if (!isLoad) {
-			tmp = cpu->cd.arm.r[rd];
-
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-				for (int i = 0; i < len; ++i)
-					word[i] = (tmp >> (8*i));
-			} else {
-				for (int i = 0; i < len; ++i)
-					word[len - 1 - i] = (tmp >> (8*i));
-			}
-		}
-
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
-				len, isLoad ? MEM_READ : MEM_WRITE, CACHE_DATA)) {
-			fatal("arm_cpu_interpret_thumb_SLOW(): could not load with immediate offset\n");
-			cpu->running = 0;
-			return 0;
-		}
-
-		if (isLoad) {
-			tmp = 0;
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-				for (int i = 0; i < len; ++i) {
-					tmp <<= 8;
-					tmp |= word[len - 1 - i];
-				}
-			} else {
-				for (int i = 0; i < len; ++i) {
-					tmp <<= 8;
-					tmp |= word[i];
-				}
-			}
-
-			cpu->cd.arm.r[rd] = tmp;
-		}
-		break;
-
-	case 0x9:
-		// sp-relative load or store
-		if (iw & 0x0800) {
-			addr = (cpu->cd.arm.r[ARM_SP] + (iw & 0xff) * 4) & ~3;
-			if (!cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
-					sizeof(word), MEM_READ, CACHE_DATA)) {
-				fatal("arm_cpu_interpret_thumb_SLOW(): could not load sp-relative word\n");
-				cpu->running = 0;
-				return 0;
-			}
-
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-				tmp = word[0] + (word[1]<<8) + (word[2]<<16) + (word[3]<<24);
-			else
-				tmp = word[3] + (word[2]<<8) + (word[1]<<16) + (word[0]<<24);
-
-			cpu->cd.arm.r[rd8] = tmp;
-		} else {
-			tmp = cpu->cd.arm.r[rd8];
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-				for (size_t i = 0; i < sizeof(word); ++i)
-					word[i] = (tmp >> (8*i));
-			} else {
-				for (size_t i = 0; i < sizeof(word); ++i)
-					word[sizeof(word) - 1 - i] = (tmp >> (8*i));
-			}
-
-			addr = (cpu->cd.arm.r[ARM_SP] + (iw & 0xff) * 4) & ~3;
-			if (!cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
-					sizeof(word), MEM_WRITE, CACHE_DATA)) {
-				fatal("arm_cpu_interpret_thumb_SLOW(): could not store sp-relative word\n");
-				cpu->running = 0;
-				return 0;
-			}
-		}
-		break;
-
-	case 0xb:
-		switch (op11_8) {
-		case 0:
-			if (iw & 0x0080)
-				cpu->cd.arm.r[ARM_SP] -= ((iw & 0x7f) << 2);
-			else
-				cpu->cd.arm.r[ARM_SP] += ((iw & 0x7f) << 2);
-			break;
-		case 4:
-		case 5:
-			/*  push, i.e. stmdb sp!, reglist  */
-			arm_push(cpu, &cpu->cd.arm.r[ARM_SP], 1, 0, 0, 1, (iw & 0xff) |
-				(iw & 0x100 ? (1 << ARM_LR) : 0));
-			break;
-		case 12:
-		case 13:
-			/*  pop, i.e. ldmia sp!, reglist  */
-			cpu->cd.arm.r[ARM_PC] = cpu->pc;
-			arm_pop(cpu, &cpu->cd.arm.r[ARM_SP], 0, 1, 0, 1, (iw & 0xff) |
-				(iw & 0x100 ? (1 << ARM_PC) : 0));
-			cpu->pc = cpu->cd.arm.r[ARM_PC];
-			if (cpu->pc & 1)
-				cpu->cd.arm.cpsr |= ARM_FLAG_T;
-			else
-				cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
-			// If not popping pc, make sure to move to the next instruction:
-			if (!(iw & 0x100))
-				cpu->pc += sizeof(uint16_t);
-			return 1;
-		default:
-			debug("TODO: unimplemented opcode 0x%x,%i at pc 0x%08x\n", main_opcode, op11_8, (int)cpu->pc);
-			cpu->running = 0;
-			return 0;
-		}
-		break;
-
-	case 0xd:
-		if (condition_code < 0xe) {
-			// Conditional branch.
-			tmp = (iw & 0xff) << 1;
-			if (tmp & 0x100)
-				tmp |= 0xfffffe00;
-			tmp = (int32_t)(cpu->pc + 4 + tmp);
-
-			switch (condition_code) {
-			case 0x0:	// eq:
-					t = cpu->cd.arm.flags & ARM_F_Z;
-					break;
-			case 0x1:	// ne:
-					t = !(cpu->cd.arm.flags & ARM_F_Z);
-					break;
-			case 0x2:	// cs:
-					t = cpu->cd.arm.flags & ARM_F_C;
-					break;
-			case 0x3:	// cc:
-					t = !(cpu->cd.arm.flags & ARM_F_C);
-					break;
-			case 0x4:	// mi:
-					t = cpu->cd.arm.flags & ARM_F_N;
-					break;
-			case 0x5:	// pl:
-					t = !(cpu->cd.arm.flags & ARM_F_N);
-					break;
-			case 0x6:	// vs:
-					t = cpu->cd.arm.flags & ARM_F_V;
-					break;
-			case 0x7:	// vc:
-					t = !(cpu->cd.arm.flags & ARM_F_V);
-					break;
-			case 0x8:	// hi:
-					t = condition_hi[cpu->cd.arm.flags];
-					break;
-			case 0x9:	// ls:
-					t = !condition_hi[cpu->cd.arm.flags];
-					break;
-			case 0xa:	// ge:
-					t = condition_ge[cpu->cd.arm.flags];
-					break;
-			case 0xb:	// lt:
-					t = !condition_ge[cpu->cd.arm.flags];
-					break;
-			case 0xc:	// gt:
-					t = condition_gt[cpu->cd.arm.flags];
-					break;
-			case 0xd:	// le:
-					t = !condition_gt[cpu->cd.arm.flags];
-					break;
-			}
-
-			if (t) {
-				cpu->pc = tmp;
-				return 1;
-			}
-		} else if (condition_code == 0xf) {
-			arm_exception(cpu, ARM_EXCEPTION_SWI);
-			return 1;
-		} else {
-			debug("TODO: unimplemented opcode 0x%x, non-branch, at pc 0x%08x\n", main_opcode, (int)cpu->pc);
-			cpu->running = 0;
-			return 0;
-		}
-		break;
-
-	case 0xe:
-		if (iw & 0x0800) {
-			// blx
-			addr = (cpu->pc + 4 + (cpu->cd.arm.tmp_branch + (((iw >> 1) & 0x3ff) << 2))) & ~3;
-
-			if (iw & 1) {
-				fatal("lowest bit set in thumb blx instruction?\n");
-				cpu->running = 0;
-				return 0;
-			}
-
-			cpu->cd.arm.r[ARM_LR] = cpu->pc + 2;
-			cpu->pc = addr;
-			if (cpu->machine->show_trace_tree)
-				cpu_functioncall_trace(cpu, cpu->pc);
-			cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
-			return 1;
-		} else {
-			// b
-			tmp = (iw & 0x7ff) << 1;
-			if (tmp & 0x800)
-				tmp |= 0xfffff000;
-			cpu->pc = (int32_t)(cpu->pc + 4 + tmp);
-			return 1;
-		}
-		break;
-
-	case 0xf:
-		if (iw & 0x0800) {
-			// bl
-			addr = (cpu->pc + 2 + (cpu->cd.arm.tmp_branch + ((iw & 0x7ff) << 1)));
-			cpu->cd.arm.r[ARM_LR] = cpu->pc + 2;
-			cpu->pc = addr;
-			if (cpu->machine->show_trace_tree)
-				cpu_functioncall_trace(cpu, cpu->pc);
-			return 1;
-		} else {
-			// "branch prefix".
-			uint32_t tmp32 = iw & 0x07ff;
-			if (tmp32 & 0x0400)
-				tmp32 |= 0xfffff800;
-			tmp32 <<= 12;
-			cpu->cd.arm.tmp_branch = tmp32;
-		}
-		break;
-
-	default:
-		debug("TODO: unimplemented opcode 0x%x at pc 0x%08x\n", main_opcode, (int)cpu->pc);
-		cpu->running = 0;
-		return 0;
-	}
-
-	cpu->pc += sizeof(uint16_t);
-
-	return 1;
-}
-
-
-/*
- *  arm_cpu_disassemble_instr():
- *
- *  Convert an instruction word into human readable format, for instruction
- *  tracing.
- *              
- *  If running is 1, cpu->pc should be the address of the instruction.
- *
- *  If running is 0, things that depend on the runtime environment (eg.
- *  register contents) will not be shown, and addr will be used instead of
- *  cpu->pc for relative addresses.
- */                     
-int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
-        int running, uint64_t dumpaddr)
-{
-	uint32_t iw, tmp;
-	int main_opcode, secondary_opcode, s_bit, r16, r12, r8;
-	int i, n, p_bit, u_bit, b_bit, w_bit, l_bit;
-	const char *symbol, *condition;
-	uint64_t offset;
-
-	if (running)
-		dumpaddr = cpu->pc;
-
-	symbol = get_symbol_name(&cpu->machine->symbol_context,
-	    dumpaddr, &offset);
-	if (symbol != NULL && offset == 0)
-		debug("<%s>\n", symbol);
-
-	if (cpu->machine->ncpus > 1 && running)
-		debug("cpu%i:\t", cpu->cpu_id);
-
-	debug("%08x:  ", (int)dumpaddr & ~1);
-
-	if (dumpaddr & 1)
-		return arm_cpu_disassemble_instr_thumb(cpu, ib, running, dumpaddr);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
-	else
-		iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);
-	debug("%08x\t", (int)iw);
-
-	condition = arm_condition_string[iw >> 28];
-	main_opcode = (iw >> 24) & 15;
-	secondary_opcode = (iw >> 21) & 15;
-	u_bit = (iw >> 23) & 1;
-	b_bit = (iw >> 22) & 1;
-	w_bit = (iw >> 21) & 1;
-	s_bit = l_bit = (iw >> 20) & 1;
-	r16 = (iw >> 16) & 15;
-	r12 = (iw >> 12) & 15;
-	r8 = (iw >> 8) & 15;
-
-	if (iw == 0xf10c0040) {
-		debug("cpsid\tf\n");
-		return sizeof(uint32_t);
-	} else if (iw == 0xf10c0080) {
-		debug("cpsid\ti\n");
-		return sizeof(uint32_t);
-	} else if (iw == 0xf57ff04f) {
-		debug("dsb\tsy\n");
-		return sizeof(uint32_t);
-	} else if (iw == 0xf57ff05f) {
-		debug("dmb\tsy\n");
-		return sizeof(uint32_t);
-	} else if (iw == 0xf57ff06f) {
-		debug("isb\tsy\n");
-		return sizeof(uint32_t);
-	} else if ((iw >> 28) == 0xf) {
-		switch (main_opcode) {
-		case 0xa:
-		case 0xb:
-			tmp = (iw & 0xffffff);
-			if (tmp & 0x800000)
-				tmp |= 0xff000000;
-			tmp = (int32_t)(dumpaddr + 8 + 4*tmp + (main_opcode == 0xb? 2 : 0)) + 1;
-			debug("blx\t0x%x", (int)tmp);
-			symbol = get_symbol_name(&cpu->machine->symbol_context,
-			    tmp, &offset);
-			if (symbol != NULL)
-				debug(" \t<%s>", symbol);
-			debug("\n");
-			break;
-		default:debug("UNIMPLEMENTED\n");
-		}
-		return sizeof(uint32_t);
-	}
-
-	switch (main_opcode) {
-	case 0x0:
-	case 0x1:
-	case 0x2:
-	case 0x3:
-		/*
-		 *  Special cases first:
-		 */
-
-		/*
-		 *  ldrex: Load Register Exclusive
-		 *  strex: Store Register Exclusive
-		 */
-		if ((iw & 0x0ff00fff) == 0x01900f9f) {
-			/*  ldrex rt[,rn]:  */
-			debug("ldrex%s\t%s,%s",
-				condition,
-				arm_regname[r12],
-				arm_regname[r16]);
-			debug("\n");
-			break;
-		}
-		if ((iw & 0x0ff00ff0) == 0x01800f90) {
-			/*  strex rd,rt[,rn]:  */
-			debug("strex%s\t%s,%s,%s",
-				condition,
-				arm_regname[r12],
-				arm_regname[iw & 15],
-				arm_regname[r16]);
-			debug("\n");
-			break;
-		}
-
-		/*
-		 *  Multiplication:
-		 *  xxxx0000 0110dddd aaaammmm 1001nnnn  mls rd,rn,rm,ra
-		 */
-		if ((iw & 0x0ff000f0) == 0x00600090) {
-			debug("mls%s\t", condition);
-			debug("%s,", arm_regname[r16]);
-			debug("%s,", arm_regname[iw & 15]);
-			debug("%s,", arm_regname[r8]);
-			debug("%s", arm_regname[r12]);
-			debug("\n");
-			break;
-		}
-
-		/*
-		 *  Multiplication:
-		 *  xxxx0000 00ASdddd nnnnssss 1001mmmm  (Rd, Rm, Rs [,Rn])
-		 */
-		if ((iw & 0x0fc000f0) == 0x00000090) {
-			int a_bit = (iw >> 21) & 1;
-			debug("%s%s%s\t", a_bit? "mla" : "mul",
-			    condition, s_bit? "s" : "");
-			debug("%s,", arm_regname[r16]);
-			debug("%s,", arm_regname[iw & 15]);
-			debug("%s", arm_regname[r8]);
-			if (a_bit)
-				debug(",%s", arm_regname[r12]);
-			debug("\n");
-			break;
-		}
-
-		/*
-		 *  Long multiplication:
-		 *  xxxx0000 1UAShhhh llllssss 1001mmmm  (Rl,Rh,Rm,Rs)
-		 */
-		if ((iw & 0x0f8000f0) == 0x00800090) {
-			int a_bit = (iw >> 21) & 1;
-			u_bit = (iw >> 22) & 1;
-			debug("%s%sl%s%s\t", u_bit? "s" : "u",
-			    a_bit? "mla" : "mul", condition, s_bit? "s" : "");
-			debug("%s,%s,", arm_regname[r12], arm_regname[r16]);
-			debug("%s,%s\n", arm_regname[iw&15], arm_regname[r8]);
-			break;
-		}
-
-		/*
-		 *  xxxx0001 0000nnnn dddd0000 0101mmmm  qadd Rd,Rm,Rn
-		 *  xxxx0001 0010nnnn dddd0000 0101mmmm  qsub Rd,Rm,Rn
-		 *  xxxx0001 0100nnnn dddd0000 0101mmmm  qdadd Rd,Rm,Rn
-		 *  xxxx0001 0110nnnn dddd0000 0101mmmm  qdsub Rd,Rm,Rn
-		 */
-		if ((iw & 0x0f900ff0) == 0x01000050) {
-			debug("q%s%s%s\t", iw & 0x400000? "d" : "",
-			    iw & 0x200000? "sub" : "add", condition);
-			debug("%s,%s,%s\n", arm_regname[r12],
-			    arm_regname[iw&15], arm_regname[r16]);
-			break;
-		}
-
-		/*
-		 *  xxxx0001 0010.... ........ 00L1mmmm  bx/blx rm
-		 */
-		if ((iw & 0x0ff000d0) == 0x01200010) {
-			l_bit = iw & 0x20;
-			debug("b%sx%s\t%s\n", l_bit? "l" : "", condition,
-			    arm_regname[iw & 15]);
-			break;
-		}
-
-		/*
-		 *  xxxx0001 0s10aaaa 11110000 0000mmmm  MSR  Regform
-		 *  xxxx0011 0s10aaaa 1111rrrr bbbbbbbb  MSR  Immform
-		 *  xxxx0001 0s001111 dddd0000 00000000  MRS
-		 */
-		if ((iw & 0x0fb0fff0) == 0x0120f000 ||
-		    (iw & 0x0fb0f000) == 0x0320f000) {
-			debug("msr%s\t%s", condition, (iw&0x400000)? "S":"C");
-			debug("PSR_");
-			if (iw & (1<<19)) debug("f");
-			if (iw & (1<<18)) debug("s");
-			if (iw & (1<<17)) debug("x");
-			if (iw & (1<<16)) debug("c");
-			if (iw & 0x02000000) {
-				int r = (iw >> 7) & 30;
-				uint32_t b = iw & 0xff;
-				while (r-- > 0)
-					b = (b >> 1) | ((b & 1) << 31);
-				debug(",#0x%x\n", b);
-			} else
-				debug(",%s\n", arm_regname[iw & 15]);
-			break;
-		}
-		if ((iw & 0x0fbf0fff) == 0x010f0000) {
-			debug("mrs%s\t", condition);
-			debug("%s,%sPSR\n", arm_regname[r12],
-			    (iw&0x400000)? "S":"C");
-			break;
-		}
-
-		/*
-		 *  xxxx0001 0B00nnnn dddd0000 1001mmmm    SWP Rd,Rm,[Rn]
-		 */
-		if ((iw & 0x0fb00ff0) == 0x01000090) {
-			debug("swp%s%s\t", condition, (iw&0x400000)? "b":"");
-			debug("%s,%s,[%s]\n", arm_regname[r12],
-			    arm_regname[iw & 15], arm_regname[r16]);
-			break;
-		}
-
-		/*
-		 *  xxxx0001 0010iiii iiiiiiii 0111iiii    BKPT immed16
-		 */
-		if ((iw & 0x0ff000f0) == 0x01200070) {
-			debug("bkpt%s\t0x%04x\n", condition,
-			    ((iw & 0x000fff00) >> 4) + (iw & 0xf));
-			break;
-		}
-
-		/*
-		 *  xxxx0001 01101111 dddd1111 0001mmmm    CLZ Rd,Rm
-		 */
-		if ((iw & 0x0fff0ff0) == 0x016f0f10) {
-			debug("clz%s\t", condition);
-			debug("%s,%s\n", arm_regname[r12], arm_regname[iw&15]);
-			break;
-		}
-
-		/*
-		 *  xxxx0011 0000mmm ddddmmm mmmmmmm    MOVW Rd,imm
-		 */
-		if ((iw & 0x0ff00000) == 0x03000000) {
-			debug("movw%s\t", condition);
-			debug("%s,#%i\n", arm_regname[r12],
-				((iw & 0xf0000) >> 4) | (iw & 0xfff));
-			break;
-		}
-
-		/*
-		 *  xxxx0011 0100mmm ddddmmm mmmmmmm    MOVT Rd,imm
-		 */
-		if ((iw & 0x0ff00000) == 0x03400000) {
-			debug("movt%s\t", condition);
-			debug("%s,#%i\n", arm_regname[r12],
-				((iw & 0xf0000) >> 4) | (iw & 0xfff));
-			break;
-		}
-
-		/*
-		 *  xxxx0001 0000dddd nnnnssss 1yx0mmmm  SMLAxy Rd,Rm,Rs,Rn
-		 *  xxxx0001 0100dddd DDDDssss 1yx0mmmm  SMLALxy RdL,RdH,Rm,Rs
-		 *  xxxx0001 0010dddd nnnnssss 1y00mmmm  SMLAWy Rd,Rm,Rs,Rn
-		 *  xxxx0001 0110dddd 0000ssss 1yx0mmmm  SMULxy Rd,Rm,Rs
-		 *  xxxx0001 0010dddd 0000ssss 1y10mmmm  SMULWy Rd,Rm,Rs
-		 */
-		if ((iw & 0x0ff00090) == 0x01000080) {
-			debug("smla%s%s%s\t",
-			    iw & 0x20? "t" : "b", iw & 0x40? "t" : "b",
-			    condition);
-			debug("%s,%s,%s,%s\n", arm_regname[r16],
-			    arm_regname[iw&15], arm_regname[r8],
-			    arm_regname[r12]);
-			break;
-		}
-		if ((iw & 0x0ff00090) == 0x01400080) {
-			debug("smlal%s%s%s\t",
-			    iw & 0x20? "t" : "b", iw & 0x40? "t" : "b",
-			    condition);
-			debug("%s,%s,%s,%s\n", arm_regname[r12],
-			    arm_regname[r16], arm_regname[iw&15],
-			    arm_regname[r8]);
-			break;
-		}
-		if ((iw & 0x0ff000b0) == 0x01200080) {
-			debug("smlaw%s%s\t", iw & 0x40? "t" : "b",
-			    condition);
-			debug("%s,%s,%s,%s\n", arm_regname[r16],
-			    arm_regname[iw&15], arm_regname[r8],
-			    arm_regname[r12]);
-			break;
-		}
-		if ((iw & 0x0ff0f090) == 0x01600080) {
-			debug("smul%s%s%s\t",
-			    iw & 0x20? "t" : "b", iw & 0x40? "t" : "b",
-			    condition);
-			debug("%s,%s,%s\n", arm_regname[r16],
-			    arm_regname[iw&15], arm_regname[r8]);
-			break;
-		}
-		if ((iw & 0x0ff0f0b0) == 0x012000a0) {
-			debug("smulw%s%s\t", iw & 0x40? "t" : "b",
-			    condition);
-			debug("%s,%s,%s\n", arm_regname[r16],
-			    arm_regname[iw&15], arm_regname[r8]);
-			break;
-		}
-
-		/*
-		 *  xxxx000P U1WLnnnn ddddHHHH 1SH1LLLL load/store rd,imm(rn)
-		 */
-		if ((iw & 0x0e000090) == 0x00000090) {
-			const char *op = "st";
-			int imm = ((iw >> 4) & 0xf0) | (iw & 0xf);
-			int regform = !(iw & 0x00400000);
-			p_bit = main_opcode & 1;
-			/*
-			 *  TODO: detect some illegal variants:
-			 *  signed store,  or  unsigned byte load/store
-			 */
-			if (!l_bit && (iw & 0xd0) == 0xd0 && (r12 & 1)) {
-				debug("TODO: r12 odd, not load/store\n");
-				break;
-			}
-			/*  Semi-generic case:  */
-			if (iw & 0x00100000)
-				op = "ld";
-			if (!l_bit && (iw & 0xd0) == 0xd0) {
-				if (iw & 0x20)
-					op = "st";
-				else
-					op = "ld";
-			}
-			debug("%sr%s", op, condition);
-			if (!l_bit && (iw & 0xd0) == 0xd0) {
-				debug("d");		/*  Double-register  */
-			} else {
-				if (iw & 0x40)
-					debug("s");	/*  signed  */
-				if (iw & 0x20)
-					debug("h");	/*  half-word  */
-				else
-					debug("b");	/*  byte  */
-			}
-			debug("\t%s,[%s", arm_regname[r12], arm_regname[r16]);
-			if (p_bit) {
-				/*  Pre-index:  */
-				if (regform)
-					debug(",%s%s", u_bit? "" : "-",
-					    arm_regname[iw & 15]);
-				else {
-					if (imm != 0)
-						debug(",#%s%i", u_bit? "" : "-",
-						    imm);
-				}
-				debug("]%s\n", w_bit? "!" : "");
-			} else {
-				/*  Post-index:  */
-				debug("],");
-				if (regform)
-					debug("%s%s\n", u_bit? "" : "-",
-					    arm_regname[iw & 15]);
-				else
-					debug("#%s%i\n", u_bit? "" : "-", imm);
-			}
-			break;
-		}
-
-		/*  Other special cases:  */
-		if (iw & 0x80 && !(main_opcode & 2) && iw & 0x10) {
-			debug("UNIMPLEMENTED reg (c!=0), t odd\n");
-			break;
-		}
-
-		/*
-		 *  Generic Data Processing Instructions:
-		 *
-		 *  xxxx000a aaaSnnnn ddddcccc ctttmmmm  Register form
-		 *  xxxx001a aaaSnnnn ddddrrrr bbbbbbbb  Immediate form
-		 */
-
-		debug("%s%s%s\t", arm_dpiname[secondary_opcode],
-		    condition, s_bit? "s" : "");
-		if (arm_dpi_uses_d[secondary_opcode])
-			debug("%s,", arm_regname[r12]);
-		if (arm_dpi_uses_n[secondary_opcode])
-			debug("%s,", arm_regname[r16]);
-
-		if (main_opcode & 2) {
-			/*  Immediate form:  */
-			int r = (iw >> 7) & 30;
-			uint32_t b = iw & 0xff;
-			while (r-- > 0)
-				b = (b >> 1) | ((b & 1) << 31);
-			if (b < 15)
-				debug("#%i", b);
-			else
-				debug("#0x%x", b);
-		} else {
-			/*  Register form:  */
-			int t = (iw >> 4) & 7;
-			int c = (iw >> 7) & 31;
-			debug("%s", arm_regname[iw & 15]);
-			switch (t) {
-			case 0:	if (c != 0)
-					debug(", lsl #%i", c);
-				break;
-			case 1:	debug(", lsl %s", arm_regname[c >> 1]);
-				break;
-			case 2:	debug(", lsr #%i", c? c : 32);
-				break;
-			case 3:	debug(", lsr %s", arm_regname[c >> 1]);
-				break;
-			case 4:	debug(", asr #%i", c? c : 32);
-				break;
-			case 5:	debug(", asr %s", arm_regname[c >> 1]);
-				break;
-			case 6:	if (c != 0)
-					debug(", ror #%i", c);
-				else
-					debug(", rrx");
-				break;
-			case 7:	debug(", ror %s", arm_regname[c >> 1]);
-				break;
-			}
-
-			/*  mov pc,reg:  */
-			if (running && t == 0 && c == 0 && secondary_opcode
-			    == 0xd && r12 == ARM_PC && (iw&15)!=ARM_PC) {
-				symbol = get_symbol_name(&cpu->machine->
-				    symbol_context, cpu->cd.arm.r[iw & 15],
-				    &offset);
-				if (symbol != NULL)
-					debug(" \t<%s>", symbol);
-			}
-		}
-		debug("\n");
-		break;
-	case 0x4:				/*  Single Data Transfer  */
-	case 0x5:
-	case 0x6:
-	case 0x7:
-		/*  Special cases first:  */
-		if ((iw & 0xfc70f000) == 0xf450f000) {
-			/*  Preload:  */
-			debug("pld\t[%s]\n", arm_regname[r16]);
-			break;
-		}
-
-		if ((iw & 0x0fff0ff0) == 0x06bf0f30) {
-			/*  rev rd,rm:  */
-			debug("rev%s\t%s,%s",
-				condition,
-				arm_regname[r12],
-				arm_regname[iw & 15]);
-			debug("\n");
-			break;
-		}
-
-		if ((iw & 0x0fff03f0) == 0x06bf0070) {
-			/*  sxth rd,rm[,rot]:  */
-			debug("sxth%s\t%s,%s",
-				condition,
-				arm_regname[r12],
-				arm_regname[iw & 15]);
-			int rot = ((iw & 0xc00) >> 10) << 3;
-			if (rot != 0)
-				debug(",%i", rot);
-			debug("\n");
-			break;
-		}
-
-		if ((iw & 0x0fff03f0) == 0x06ef0070) {
-			/*  uxtb rd,rm[,rot]:  */
-			debug("uxtb%s\t%s,%s",
-				condition,
-				arm_regname[r12],
-				arm_regname[iw & 15]);
-			int rot = ((iw & 0xc00) >> 10) << 3;
-			if (rot != 0)
-				debug(",%i", rot);
-			debug("\n");
-			break;
-		}
-
-		// Note: uxtab is decoded AFTER uxtb.
-		if ((iw & 0x0ff003f0) == 0x06e00070) {
-			/*  uxtab rd,rn,rm[,rot]:  */
-			debug("uxtab%s\t%s,%s,%s",
-				condition,
-				arm_regname[r12],
-				arm_regname[r16],
-				arm_regname[iw & 15]);
-			int rot = ((iw & 0xc00) >> 10) << 3;
-			if (rot != 0)
-				debug(",%i", rot);
-			debug("\n");
-			break;
-		}
-
-		if ((iw & 0x0fff03f0) == 0x06ff0070) {
-			/*  uxth rd,rm[,rot]:  */
-			debug("uxth%s\t%s,%s",
-				condition,
-				arm_regname[r12],
-				arm_regname[iw & 15]);
-			int rot = ((iw & 0xc00) >> 10) << 3;
-			if (rot != 0)
-				debug(",%i", rot);
-			debug("\n");
-			break;
-		}
-
-		// Note: uxtah is decoded AFTER uxth.
-		if ((iw & 0x0ff003f0) == 0x06f00070) {
-			/*  uxtah rd,rn,rm[,rot]:  */
-			debug("uxtah%s\t%s,%s,%s",
-				condition,
-				arm_regname[r12],
-				arm_regname[r16],
-				arm_regname[iw & 15]);
-			int rot = ((iw & 0xc00) >> 10) << 3;
-			if (rot != 0)
-				debug(",%i", rot);
-			debug("\n");
-			break;
-		}
-
-		if ((iw & 0x0fe00070) == 0x07c00010) {
-			/*  bfi rd,rn,#lsb,#width:  */
-			debug("bfi%s\t%s,%s",
-				condition,
-				arm_regname[r12],
-				arm_regname[iw & 15]);
-			int lsb = (iw >> 7) & 31;
-			int msb = (iw >> 16) & 31;
-			int width = msb - lsb + 1;
-			debug(",%i", lsb);
-			debug(",%i", width);
-			debug("\n");
-			break;
-		}
-
-		if ((iw & 0x0fe00070) == 0x07e00050) {
-			/*  ubfx rd,rn,#lsb,#width:  */
-			debug("ubfx%s\t%s,%s",
-				condition,
-				arm_regname[r12],
-				arm_regname[iw & 15]);
-			debug(",%i", (iw >> 7) & 31);
-			debug(",%i", 1 + ((iw >> 16) & 31));
-			debug("\n");
-			break;
-		}
-
-		if ((iw & 0x0fe00070) == 0x07a00050) {
-			/*  sbfx rd,rn,#lsb,#width:  */
-			debug("sbfx%s\t%s,%s",
-				condition,
-				arm_regname[r12],
-				arm_regname[iw & 15]);
-			debug(",%i", (iw >> 7) & 31);
-			debug(",%i", 1 + ((iw >> 16) & 31));
-			debug("\n");
-			break;
-		}
-
-		if ((iw & 0x0fffffff) == 0x07f001f2) {
-			debug("linux_bug%s\t; see https://github.com/torvalds/linux/blob/master/arch/arm/include/asm/bug.h\n",
-				condition);
-			break;
-		}
-
-
-		/*
-		 *  xxxx010P UBWLnnnn ddddoooo oooooooo  Immediate form
-		 *  xxxx011P UBWLnnnn ddddcccc ctt0mmmm  Register form
-		 */
-		p_bit = main_opcode & 1;
-		if (main_opcode >= 6 && iw & 0x10) {
-			debug("TODO: single data transf. but 0x10\n");
-			break;
-		}
-		debug("%s%s%s", l_bit? "ldr" : "str",
-		    condition, b_bit? "b" : "");
-		if (!p_bit && w_bit)
-			debug("t");
-		debug("\t%s,[%s", arm_regname[r12], arm_regname[r16]);
-		if ((iw & 0x0e000000) == 0x04000000) {
-			/*  Immediate form:  */
-			uint32_t imm = iw & 0xfff;
-			if (!p_bit)
-				debug("]");
-			if (imm != 0)
-				debug(",#%s%i", u_bit? "" : "-", imm);
-			if (p_bit)
-				debug("]");
-		} else if ((iw & 0x0e000010) == 0x06000000) {
-			/*  Register form:  */
-			if (!p_bit)
-				debug("]");
-			if ((iw & 0xfff) != 0)
-				debug(",%s%s", u_bit? "" : "-",
-				    arm_regname[iw & 15]);
-			if ((iw & 0xff0) != 0x000) {
-				int c = (iw >> 7) & 31;
-				int t = (iw >> 4) & 7;
-				switch (t) {
-				case 0:	if (c != 0)
-						debug(", lsl #%i", c);
-					break;
-				case 2:	debug(", lsr #%i", c? c : 32);
-					break;
-				case 4:	debug(", asr #%i", c? c : 32);
-					break;
-				case 6:	if (c != 0)
-						debug(", ror #%i", c);
-					else
-						debug(", rrx");
-					break;
-				}
-			}
-			if (p_bit)
-				debug("]");
-		} else {
-			debug("UNKNOWN\n");
-			break;
-		}
-		debug("%s", (p_bit && w_bit)? "!" : "");
-		if ((iw & 0x0f000000) == 0x05000000 &&
-		    (r16 == ARM_PC || running)) {
-			unsigned char tmpw[4];
-			uint32_t imm = iw & 0xfff;
-			uint32_t addr = (u_bit? imm : -imm);
-			if (r16 == ARM_PC)
-				addr += dumpaddr + 8;
-			else
-				addr += cpu->cd.arm.r[r16];
-			symbol = get_symbol_name(&cpu->machine->symbol_context,
-			    addr, &offset);
-			if (symbol != NULL)
-				debug(" \t<%s", symbol);
-			else
-				debug(" \t<0x%08x", addr);
-			if ((l_bit && cpu->memory_rw(cpu, cpu->mem, addr, tmpw,
-			    b_bit? 1 : sizeof(tmpw), MEM_READ, NO_EXCEPTIONS))
-			    || (!l_bit && running)) {
-				if (l_bit) {
-					if (cpu->byte_order ==
-					    EMUL_LITTLE_ENDIAN)
-						addr = tmpw[0] +(tmpw[1] << 8) +
-						    (tmpw[2]<<16)+(tmpw[3]<<24);
-					else
-						addr = tmpw[3] + (tmpw[2]<<8) +
-						    (tmpw[1]<<16)+(tmpw[0]<<24);
-				} else {
-					tmpw[0] = addr = cpu->cd.arm.r[r12];
-					if (r12 == ARM_PC)
-						addr = cpu->pc + 8;
-				}
-				debug(": ");
-				if (b_bit)
-					debug("%i", tmpw[0]);
-				else {
-					symbol = get_symbol_name(&cpu->machine->
-					    symbol_context, addr, &offset);
-					if (symbol != NULL)
-						debug("%s", symbol);
-					else if ((int32_t)addr > -256 &&
-						    (int32_t)addr < 256)
-						debug("%i", addr);
-					else
-						debug("0x%x", addr);
-				}
-			}
-			debug(">");
-		}
-		debug("\n");
-		break;
-	case 0x8:				/*  Block Data Transfer  */
-	case 0x9:
-		/*  xxxx100P USWLnnnn llllllll llllllll  */
-		p_bit = main_opcode & 1;
-		s_bit = b_bit;
-		debug("%s%s", l_bit? "ldm" : "stm", condition);
-		switch (u_bit * 2 + p_bit) {
-		case 0:	debug("da"); break;
-		case 1:	debug("db"); break;
-		case 2:	debug("ia"); break;
-		case 3:	debug("ib"); break;
-		}
-		debug("\t%s", arm_regname[r16]);
-		if (w_bit)
-			debug("!");
-		debug(",{");
-		n = 0;
-		for (i=0; i<16; i++)
-			if ((iw >> i) & 1) {
-				debug("%s%s", (n > 0)? ",":"", arm_regname[i]);
-				n++;
-			}
-		debug("}");
-		if (s_bit)
-			debug("^");
-		debug("\n");
-		break;
-	case 0xa:				/*  B: branch  */
-	case 0xb:				/*  BL: branch and link  */
-		debug("b%s%s\t", main_opcode == 0xa? "" : "l", condition);
-		tmp = (iw & 0x00ffffff) << 2;
-		if (tmp & 0x02000000)
-			tmp |= 0xfc000000;
-		tmp = (int32_t)(dumpaddr + tmp + 8);
-		debug("0x%x", (int)tmp);
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    tmp, &offset);
-		if (symbol != NULL)
-			debug(" \t<%s>", symbol);
-		debug("\n");
-		break;
-	case 0xc:				/*  Coprocessor  */
-	case 0xd:				/*  LDC/STC  */
-		/*
-		 *  xxxx1100 0100nnnn ddddcccc oooommmm    MCRR c,op,Rd,Rn,CRm
-		 *  xxxx1100 0101nnnn ddddcccc oooommmm    MRRC c,op,Rd,Rn,CRm
-		 */
-		if ((iw & 0x0fe00fff) == 0x0c400000) {
-			debug("%s%s\t", iw & 0x100000? "mra" : "mar",
-			    condition);
-			if (iw & 0x100000)
-				debug("%s,%s,acc0\n",
-				    arm_regname[r12], arm_regname[r16]);
-			else
-				debug("acc0,%s,%s\n",
-				    arm_regname[r12], arm_regname[r16]);
-			break;
-		}
-		if ((iw & 0x0fe00000) == 0x0c400000) {
-			debug("%s%s\t", iw & 0x100000? "mrrc" : "mcrr",
-			    condition);
-			debug("%i,%i,%s,%s,cr%i\n", r8, (iw >> 4) & 15,
-			    arm_regname[r12], arm_regname[r16], iw & 15);
-			break;
-		}
-
-		/*  xxxx110P UNWLnnnn DDDDpppp oooooooo LDC/STC  */
-		debug("TODO: coprocessor LDC/STC\n");
-		break;
-	case 0xe:				/*  CDP (Coprocessor Op)  */
-		/*				    or MRC/MCR!
-		 *  xxxx1110 oooonnnn ddddpppp qqq0mmmm		CDP
-		 *  xxxx1110 oooLNNNN ddddpppp qqq1MMMM		MRC/MCR
-		 */
-		if ((iw & 0x0ff00ff0) == 0x0e200010) {
-			/*  Special case: mia* DSP instructions  */
-			switch ((iw >> 16) & 0xf) {
-			case  0: debug("mia"); break;
-			case  8: debug("miaph"); break;
-			case 12: debug("miaBB"); break;
-			case 13: debug("miaTB"); break;
-			case 14: debug("miaBT"); break;
-			case 15: debug("miaTT"); break;
-			default: debug("UNKNOWN mia vector instruction?");
-			}
-			debug("%s\t", condition);
-			debug("acc%i,%s,%s\n", ((iw >> 5) & 7),
-			    arm_regname[iw & 15], arm_regname[r12]);
-			break;
-		}
-		if (iw & 0x10) {
-			debug("%s%s\t",
-			    (iw & 0x00100000)? "mrc" : "mcr", condition);
-			debug("%i,%i,r%i,cr%i,cr%i,%i",
-			    (int)((iw >> 8) & 15), (int)((iw >>21) & 7),
-			    (int)((iw >>12) & 15), (int)((iw >>16) & 15),
-			    (int)((iw >> 0) & 15), (int)((iw >> 5) & 7));
-		} else {
-			debug("cdp%s\t", condition);
-			debug("%i,%i,cr%i,cr%i,cr%i",
-			    (int)((iw >> 8) & 15),
-			    (int)((iw >>20) & 15),
-			    (int)((iw >>12) & 15),
-			    (int)((iw >>16) & 15),
-			    (int)((iw >> 0) & 15));
-			if ((iw >> 5) & 7)
-				debug(",0x%x", (int)((iw >> 5) & 7));
-		}
-		debug("\n");
-		break;
-	case 0xf:				/*  SWI  */
-		debug("swi%s\t", condition);
-		debug("0x%x\n", (int)(iw & 0x00ffffff));
-		break;
-	default:debug("UNIMPLEMENTED\n");
-	}
-
-	return sizeof(uint32_t);
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  arm_mcr_mrc():
- *
- *  Coprocessor register move.
- *
- *  The program counter should be synched before calling this function (to
- *  make debug output with the correct PC value possible).
- */
-void arm_mcr_mrc(struct cpu *cpu, uint32_t iword)
-{
-	int opcode1 = (iword >> 21) & 7;
-	int l_bit = (iword >> 20) & 1;
-	int crn = (iword >> 16) & 15;
-	int rd = (iword >> 12) & 15;
-	int cp_num = (iword >> 8) & 15;
-	int opcode2 = (iword >> 5) & 7;
-	int crm = iword & 15;
-
-	if (cpu->cd.arm.coproc[cp_num] != NULL)
-		cpu->cd.arm.coproc[cp_num](cpu, opcode1, opcode2, l_bit,
-		    crn, crm, rd);
-	else {
-		fatal("[ TODO: arm_mcr_mrc: pc=0x%08x, iword=0x%08x: "
-		    "cp_num=%i ]\n", (int)cpu->pc, iword, cp_num);
-
-		// arm_exception(cpu, ARM_EXCEPTION_UND);
-		/*  exit(1);  */
-	}
-}
-
-
-/*
- *  arm_cdp():
- *
- *  Coprocessor operations.
- *
- *  The program counter should be synched before calling this function (to
- *  make debug output with the correct PC value possible).
- */
-void arm_cdp(struct cpu *cpu, uint32_t iword)
-{
-	fatal("[ arm_cdp: pc=0x%08x, iword=0x%08x ]\n", (int)cpu->pc, iword);
-	arm_exception(cpu, ARM_EXCEPTION_UND);
-	/*  exit(1);  */
-}
-
-
-/*****************************************************************************/
-
-
-#include "tmp_arm_tail.cc"
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_arm_coproc.c gxemul-0.7.0+dfsg/src/cpus/cpu_arm_coproc.c
--- gxemul-0.6.2/src/cpus/cpu_arm_coproc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_arm_coproc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,520 @@
+/*
+ *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  ARM coprocessor emulation.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <ctype.h>
+
+#include "cpu.h"
+#include "machine.h"
+#include "misc.h"
+#include "symbol.h"
+
+#include "thirdparty/i80321reg.h"
+
+
+/*
+ *  arm_coproc_15():
+ *
+ *  The system control coprocessor.
+ */
+void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
+	int crn, int crm, int rd)
+{
+	uint32_t old_control;
+
+	/*  Some sanity checks:  */
+	if (opcode1 != 0) {
+		fatal("[ TODO: arm_coproc_15: opcode1 = %i, should be 0 ]\n", opcode1);
+		// exit(1);
+	}
+	if (rd == ARM_PC) {
+		fatal("[ TODO: arm_coproc_15: rd = PC ]\n");
+		exit(1);
+	}
+
+	switch (crn) {
+
+	case 0:	/*
+		 *  Main ID register (and Cache Type register, on XScale)
+		 *
+		 *  Writes are supposed to be ignored, according to Intel docs.
+		 */
+		switch (opcode2) {
+		case 0:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.cpu_type.cpu_id;
+			else
+				fatal("[ TODO: arm_coproc_15: attempt to write "
+				    "to the Main ID register? ]\n");
+			break;
+		case 1:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.cachetype;
+			else
+				fatal("[ TODO: arm_coproc_15: attempt to write "
+				    "to the Cache Type register? ]\n");
+			break;
+		default:fatal("[ TODO: arm_coproc_15: cr0, opcode2=%i ]\n",
+			    opcode2);
+			// exit(1);
+		}
+		break;
+
+	case 1:	/*  Control Register:  */
+		if (l_bit) {
+			/*  Load from the normal/aux control register:  */
+			switch (opcode2) {
+			case 0:	cpu->cd.arm.r[rd] = cpu->cd.arm.control;
+				break;
+			case 1:	cpu->cd.arm.r[rd] = cpu->cd.arm.auxctrl;
+				break;
+			default:fatal("[ TODO: Unimplemented opcode2 = %i ", opcode2);
+				fatal("(opcode1=%i crn=%i crm=%i rd=%i l=%i) ]\n",
+				    opcode1, crn, crm, rd, l_bit);
+				// exit(1);
+			}
+			return;
+		}
+
+		if (opcode2 == 1) {
+			/*  Write to auxctrl:  */
+			old_control = cpu->cd.arm.auxctrl;
+			cpu->cd.arm.auxctrl = cpu->cd.arm.r[rd];
+			if ((old_control & ARM_AUXCTRL_MD) !=
+			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_MD)) {
+				debug("[ setting the minidata cache attribute"
+				    " to 0x%x ]\n", (cpu->cd.arm.auxctrl &
+				    ARM_AUXCTRL_MD) >> ARM_AUXCTRL_MD_SHIFT);
+			}
+			if ((old_control & ARM_AUXCTRL_K) !=
+			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_K)) {
+				debug("[ %s write buffer coalescing ]\n",
+				    cpu->cd.arm.auxctrl & ARM_AUXCTRL_K?
+				    "Disabling" : "Enabling");
+			}
+			return;
+		} else if (opcode2 != 0) {
+			fatal("[ Unimplemented write, opcode2 = %i ", opcode2);
+			fatal("(opcode1=%i crn=%i crm=%i rd=%i l=%i)]\n",
+			    opcode1, crn, crm, rd, l_bit);
+			// exit(1);
+		}
+			
+		/*
+		 *  Write to control:  Check each bit individually:
+		 */
+		old_control = cpu->cd.arm.control;
+		cpu->cd.arm.control = cpu->cd.arm.r[rd];
+		if ((old_control & ARM_CONTROL_MMU) !=
+		    (cpu->cd.arm.control & ARM_CONTROL_MMU)) {
+			debug("[ %s the MMU ]\n", cpu->cd.arm.control &
+			    ARM_CONTROL_MMU? "enabling" : "disabling");
+			cpu->translate_v2p =
+			    cpu->cd.arm.control & ARM_CONTROL_MMU?
+			    arm_translate_v2p_mmu : arm_translate_v2p;
+		}
+		if ((old_control & ARM_CONTROL_ALIGN) !=
+		    (cpu->cd.arm.control & ARM_CONTROL_ALIGN))
+			debug("[ %s alignment checks ]\n", cpu->cd.arm.control &
+			    ARM_CONTROL_ALIGN? "enabling" : "disabling");
+		if ((old_control & ARM_CONTROL_CACHE) !=
+		    (cpu->cd.arm.control & ARM_CONTROL_CACHE))
+			debug("[ %s the [data] cache ]\n", cpu->cd.arm.control &
+			    ARM_CONTROL_CACHE? "enabling" : "disabling");
+		if ((old_control & ARM_CONTROL_WBUFFER) !=
+		    (cpu->cd.arm.control & ARM_CONTROL_WBUFFER))
+			debug("[ %s the write buffer ]\n", cpu->cd.arm.control &
+			    ARM_CONTROL_WBUFFER? "enabling" : "disabling");
+
+		old_control &= ~ARM_CONTROL_BIG;
+		if (cpu->byte_order == EMUL_BIG_ENDIAN)
+			old_control |= ARM_CONTROL_BIG;
+
+		if ((old_control & ARM_CONTROL_BIG) !=
+		    (cpu->cd.arm.control & ARM_CONTROL_BIG)) {
+			fatal("ERROR: Trying to switch endianness. Not "
+			    "supported yet.\n");
+			exit(1);
+		}
+		if ((old_control & ARM_CONTROL_ICACHE) !=
+		    (cpu->cd.arm.control & ARM_CONTROL_ICACHE))
+			debug("[ %s the icache ]\n", cpu->cd.arm.control &
+			    ARM_CONTROL_ICACHE? "enabling" : "disabling");
+		/*  TODO: More bits.  */
+		break;
+
+	case 2:	/*  Translation Table Base register:  */
+		/*  NOTE: 16 KB aligned.  */
+		if (l_bit)
+			cpu->cd.arm.r[rd] = cpu->cd.arm.ttb & 0xffffc000;
+		else {
+			cpu->cd.arm.ttb = cpu->cd.arm.r[rd];
+			if (cpu->cd.arm.ttb & 0x3fff)
+				fatal("[ WARNING! low bits of new TTB non-"
+				    "zero? 0x%08x ]\n", cpu->cd.arm.ttb);
+			cpu->cd.arm.ttb &= 0xffffc000;
+		}
+		break;
+
+	case 3:	/*  Domain Access Control Register:  */
+		if (l_bit)
+			cpu->cd.arm.r[rd] = cpu->cd.arm.dacr;
+		else
+			cpu->cd.arm.dacr = cpu->cd.arm.r[rd];
+		break;
+
+	case 5:	/*  Fault Status Register:  */
+		/*  Note: Only the lowest 8 bits are defined.  */
+		if (l_bit)
+			cpu->cd.arm.r[rd] = cpu->cd.arm.fsr & 0xff;
+		else
+			cpu->cd.arm.fsr = cpu->cd.arm.r[rd] & 0xff;
+		break;
+
+	case 6:	/*  Fault Address Register:  */
+		if (l_bit)
+			cpu->cd.arm.r[rd] = cpu->cd.arm.far;
+		else
+			cpu->cd.arm.far = cpu->cd.arm.r[rd];
+		break;
+
+	case 7:	/*  Cache functions:  */
+		if (l_bit) {
+			fatal("[ arm_coproc_15: attempt to read cr7? ]\n");
+			return;
+		}
+		/*  debug("[ arm_coproc_15: cache op: TODO ]\n");  */
+		/*  TODO:  */
+		break;
+
+	case 8:	/*  TLB functions:  */
+		if (l_bit) {
+			fatal("[ arm_coproc_15: attempt to read cr8? ]\n");
+			return;
+		}
+		/*  fatal("[ arm_coproc_15: TLB: op2=%i crm=%i rd=0x%08x ]\n",
+		    opcode2, crm, cpu->cd.arm.r[rd]);  */
+		if (opcode2 == 0)
+			cpu->invalidate_translation_caches(cpu, 0,
+			    INVALIDATE_ALL);
+		else
+			cpu->invalidate_translation_caches(cpu,
+			    cpu->cd.arm.r[rd], INVALIDATE_VADDR);
+		break;
+
+	case 9:	/*  Cache lockdown:  */
+		fatal("[ arm_coproc_15: cache lockdown: TODO ]\n");
+		/*  TODO  */
+		break;
+
+	case 13:/*  Process ID Register:  */
+		if (opcode2 != 0)
+			debug("[ arm_coproc_15: PID access, but opcode2 "
+			    "= %i? (should be 0) ]\n", opcode2);
+		if (crm != 0)
+			fatal("[ arm_coproc_15: PID access, but crm "
+			    "= %i? (should be 0) ]\n", crm);
+		if (l_bit)
+			cpu->cd.arm.r[rd] = cpu->cd.arm.pid;
+		else
+			cpu->cd.arm.pid = cpu->cd.arm.r[rd];
+		if (cpu->cd.arm.pid != 0) {
+			fatal("ARM TODO: pid!=0. Fast Context Switch"
+			    " Extension not implemented yet\n");
+			exit(1);
+		}
+		break;
+
+	/*  case 14:  */
+		/*  Breakpoint registers on XScale (possibly others?)  */
+		/*  TODO  */
+		/*  break;  */
+
+	case 15:/*  IMPLEMENTATION DEPENDENT!  */
+		switch (crm) {
+		case 1:	/*
+			 *  On XScale (and others? TODO), this is the
+			 *  CoProcessor Access Register.  Note/TODO: This isn't
+			 *  really used throughout the rest of the code yet.
+			 */
+			if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.cpar;
+			else
+				cpu->cd.arm.cpar = cpu->cd.arm.r[rd];
+			break;
+		default:fatal("[ TODO: arm_coproc_15: IMPLEMENTATION "
+			    "DEPENDENT! ]\n");
+			// exit(1);
+		}
+		break;
+
+	default:fatal("[ TODO: arm_coproc_15: unimplemented crn = %i ", crn);
+		fatal("(opcode1=%i opcode2=%i crm=%i rd=%i l=%i) ]\n",
+		    opcode1, opcode2, crm, rd, l_bit);
+		// exit(1);
+	}
+}
+
+
+/*
+ *  arm_coproc_i80321_6():
+ *
+ *  Intel 80321 coprocessor 6.
+ */
+void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
+	int crn, int crm, int rd)
+{
+	switch (crm) {
+
+	case 0:	switch (crn) {
+		case 0:	if (l_bit) {
+				cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_inten;
+				fatal("TODO: XScale read from inten?\n");
+				exit(1);
+			} else
+				cpu->cd.arm.i80321_inten = cpu->cd.arm.r[rd];
+			break;
+		case 4:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_isteer;
+			else {
+				cpu->cd.arm.i80321_isteer = cpu->cd.arm.r[rd];
+				if (cpu->cd.arm.r[rd] != 0) {
+					fatal("ARM xscale interrupt steering"
+					    " is not yet implemented\n");
+					exit(1);
+				}
+			}
+			break;
+		case 8:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_isrc;
+			else {
+				cpu->cd.arm.i80321_isrc = cpu->cd.arm.r[rd];
+				fatal("TODO: XScale int ack?\n");
+				exit(1);
+			}
+			break;
+		default:goto unknown;
+		}
+		break;
+
+	case 1:	/*  fatal("TIMER opcode1=%i opcode2=%i crn="
+    "%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn, crm, rd, l_bit);  */
+
+		switch (crn) {
+		case 0:	/*  tmr0:  */
+			if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.tmr0;
+			else
+				cpu->cd.arm.tmr0 = cpu->cd.arm.r[rd];
+			break;
+		case 1:	/*  tmr1:  */
+			if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.tmr1;
+			else
+				cpu->cd.arm.tmr1 = cpu->cd.arm.r[rd];
+			break;
+		case 2:	/*  tcr0:  */
+			if (l_bit) {
+				/*  NOTE/TODO: Ugly hack: timer increment  */
+				cpu->cd.arm.tcr0 ++;
+				cpu->cd.arm.r[rd] = cpu->cd.arm.tcr0;
+			} else {
+				cpu->cd.arm.tcr0 = cpu->cd.arm.r[rd];
+			}
+			break;
+		case 3:	/*  tcr1:  */
+			if (l_bit) {
+				/*  NOTE/TODO: Ugly hack: timer increment  */
+				cpu->cd.arm.tcr1 ++;
+				cpu->cd.arm.r[rd] = cpu->cd.arm.tcr1;
+			} else {
+				cpu->cd.arm.tcr1 = cpu->cd.arm.r[rd];
+			}
+			break;
+		case 4:	/*  trr0:  */
+			if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.trr0;
+			else
+				cpu->cd.arm.trr0 = cpu->cd.arm.r[rd];
+			break;
+		case 5:	/*  trr1:  */
+			if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.trr1;
+			else
+				cpu->cd.arm.trr1 = cpu->cd.arm.r[rd];
+			break;
+		case 6:	/*  tisr:  */
+			if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.tisr;
+			else {
+				/*  Writing clears interrupts:  */
+				cpu->cd.arm.tisr &= ~cpu->cd.arm.r[rd];
+
+				if (!(cpu->cd.arm.tisr & TISR_TMR0))
+					INTERRUPT_DEASSERT(
+					    cpu->cd.arm.tmr0_irq);
+				if (!(cpu->cd.arm.tisr & TISR_TMR1))
+					INTERRUPT_DEASSERT(
+					    cpu->cd.arm.tmr1_irq);
+			}
+			break;
+		case 7:	/*  wdtcr:  */
+			if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.wdtcr;
+			else
+				cpu->cd.arm.wdtcr = cpu->cd.arm.r[rd];
+			break;
+		default:goto unknown;
+		}
+		break;
+
+	default:goto unknown;
+	}
+
+	return;
+
+unknown:
+	fatal("arm_coproc_i80321_6: unimplemented opcode1=%i opcode2=%i crn="
+	    "%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn, crm, rd, l_bit);
+	exit(1);
+}
+
+
+/*
+ *  arm_coproc_xscale_14():
+ *
+ *  XScale coprocessor 14, Performance Monitoring Unit.
+ */
+void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
+	int crn, int crm, int rd)
+{
+	if (opcode2 != 0) {
+		fatal("TODO: opcode2 = %i\n", opcode2);
+		goto unknown;
+	}
+
+	switch (crm) {
+
+	case 0:	switch (crn) {
+		case 0:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_pmnc;
+			else
+				cpu->cd.arm.xsc1_pmnc = cpu->cd.arm.r[rd];
+			break;
+		case 1:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_ccnt;
+			else
+				cpu->cd.arm.xsc1_ccnt = cpu->cd.arm.r[rd];
+			break;
+		case 2:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_pmn0;
+			else
+				cpu->cd.arm.xsc1_pmn0 = cpu->cd.arm.r[rd];
+			break;
+		case 3:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_pmn1;
+			else
+				cpu->cd.arm.xsc1_pmn1 = cpu->cd.arm.r[rd];
+			break;
+		case 7:	/*  UNIMPLEMENTED!!! TODO  */
+			/*  Possibly some kind of idle or sleep function.  */
+			break;
+		default:goto unknown;
+		}
+		break;
+
+	case 1:	switch (crn) {
+		case 0:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmnc;
+			else
+				cpu->cd.arm.xsc2_pmnc = cpu->cd.arm.r[rd];
+			break;
+		case 1:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_ccnt;
+			else
+				cpu->cd.arm.xsc2_ccnt = cpu->cd.arm.r[rd];
+			break;
+		case 4:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_inten;
+			else
+				cpu->cd.arm.xsc2_inten = cpu->cd.arm.r[rd];
+			break;
+		case 5:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_flag;
+			else
+				cpu->cd.arm.xsc2_flag = cpu->cd.arm.r[rd];
+			break;
+		case 8:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_evtsel;
+			else
+				cpu->cd.arm.xsc2_evtsel = cpu->cd.arm.r[rd];
+			break;
+		default:goto unknown;
+		}
+		break;
+
+	case 2:	switch (crn) {
+		case 0:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn0;
+			else
+				cpu->cd.arm.xsc2_pmn0 = cpu->cd.arm.r[rd];
+			break;
+		case 1:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn1;
+			else
+				cpu->cd.arm.xsc2_pmn1 = cpu->cd.arm.r[rd];
+			break;
+		case 2:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn2;
+			else
+				cpu->cd.arm.xsc2_pmn2 = cpu->cd.arm.r[rd];
+			break;
+		case 3:	if (l_bit)
+				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn3;
+			else
+				cpu->cd.arm.xsc2_pmn3 = cpu->cd.arm.r[rd];
+			break;
+		default:goto unknown;
+		}
+		break;
+
+	default:goto unknown;
+	}
+
+	return;
+
+unknown:
+	fatal("arm_coproc_xscale_14: unimplemented opcode1=%i opcode2="
+	    "%i crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn,
+	    crm, rd, l_bit);
+	exit(1);
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_arm_coproc.cc gxemul-0.7.0+dfsg/src/cpus/cpu_arm_coproc.cc
--- gxemul-0.6.2/src/cpus/cpu_arm_coproc.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_arm_coproc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,520 +0,0 @@
-/*
- *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  ARM coprocessor emulation.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <ctype.h>
-
-#include "cpu.h"
-#include "machine.h"
-#include "misc.h"
-#include "symbol.h"
-
-#include "thirdparty/i80321reg.h"
-
-
-/*
- *  arm_coproc_15():
- *
- *  The system control coprocessor.
- */
-void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
-	int crn, int crm, int rd)
-{
-	uint32_t old_control;
-
-	/*  Some sanity checks:  */
-	if (opcode1 != 0) {
-		fatal("[ TODO: arm_coproc_15: opcode1 = %i, should be 0 ]\n", opcode1);
-		// exit(1);
-	}
-	if (rd == ARM_PC) {
-		fatal("[ TODO: arm_coproc_15: rd = PC ]\n");
-		exit(1);
-	}
-
-	switch (crn) {
-
-	case 0:	/*
-		 *  Main ID register (and Cache Type register, on XScale)
-		 *
-		 *  Writes are supposed to be ignored, according to Intel docs.
-		 */
-		switch (opcode2) {
-		case 0:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.cpu_type.cpu_id;
-			else
-				fatal("[ TODO: arm_coproc_15: attempt to write "
-				    "to the Main ID register? ]\n");
-			break;
-		case 1:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.cachetype;
-			else
-				fatal("[ TODO: arm_coproc_15: attempt to write "
-				    "to the Cache Type register? ]\n");
-			break;
-		default:fatal("[ TODO: arm_coproc_15: cr0, opcode2=%i ]\n",
-			    opcode2);
-			// exit(1);
-		}
-		break;
-
-	case 1:	/*  Control Register:  */
-		if (l_bit) {
-			/*  Load from the normal/aux control register:  */
-			switch (opcode2) {
-			case 0:	cpu->cd.arm.r[rd] = cpu->cd.arm.control;
-				break;
-			case 1:	cpu->cd.arm.r[rd] = cpu->cd.arm.auxctrl;
-				break;
-			default:fatal("[ TODO: Unimplemented opcode2 = %i ", opcode2);
-				fatal("(opcode1=%i crn=%i crm=%i rd=%i l=%i) ]\n",
-				    opcode1, crn, crm, rd, l_bit);
-				// exit(1);
-			}
-			return;
-		}
-
-		if (opcode2 == 1) {
-			/*  Write to auxctrl:  */
-			old_control = cpu->cd.arm.auxctrl;
-			cpu->cd.arm.auxctrl = cpu->cd.arm.r[rd];
-			if ((old_control & ARM_AUXCTRL_MD) !=
-			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_MD)) {
-				debug("[ setting the minidata cache attribute"
-				    " to 0x%x ]\n", (cpu->cd.arm.auxctrl &
-				    ARM_AUXCTRL_MD) >> ARM_AUXCTRL_MD_SHIFT);
-			}
-			if ((old_control & ARM_AUXCTRL_K) !=
-			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_K)) {
-				debug("[ %s write buffer coalescing ]\n",
-				    cpu->cd.arm.auxctrl & ARM_AUXCTRL_K?
-				    "Disabling" : "Enabling");
-			}
-			return;
-		} else if (opcode2 != 0) {
-			fatal("[ Unimplemented write, opcode2 = %i ", opcode2);
-			fatal("(opcode1=%i crn=%i crm=%i rd=%i l=%i)]\n",
-			    opcode1, crn, crm, rd, l_bit);
-			// exit(1);
-		}
-			
-		/*
-		 *  Write to control:  Check each bit individually:
-		 */
-		old_control = cpu->cd.arm.control;
-		cpu->cd.arm.control = cpu->cd.arm.r[rd];
-		if ((old_control & ARM_CONTROL_MMU) !=
-		    (cpu->cd.arm.control & ARM_CONTROL_MMU)) {
-			debug("[ %s the MMU ]\n", cpu->cd.arm.control &
-			    ARM_CONTROL_MMU? "enabling" : "disabling");
-			cpu->translate_v2p =
-			    cpu->cd.arm.control & ARM_CONTROL_MMU?
-			    arm_translate_v2p_mmu : arm_translate_v2p;
-		}
-		if ((old_control & ARM_CONTROL_ALIGN) !=
-		    (cpu->cd.arm.control & ARM_CONTROL_ALIGN))
-			debug("[ %s alignment checks ]\n", cpu->cd.arm.control &
-			    ARM_CONTROL_ALIGN? "enabling" : "disabling");
-		if ((old_control & ARM_CONTROL_CACHE) !=
-		    (cpu->cd.arm.control & ARM_CONTROL_CACHE))
-			debug("[ %s the [data] cache ]\n", cpu->cd.arm.control &
-			    ARM_CONTROL_CACHE? "enabling" : "disabling");
-		if ((old_control & ARM_CONTROL_WBUFFER) !=
-		    (cpu->cd.arm.control & ARM_CONTROL_WBUFFER))
-			debug("[ %s the write buffer ]\n", cpu->cd.arm.control &
-			    ARM_CONTROL_WBUFFER? "enabling" : "disabling");
-
-		old_control &= ~ARM_CONTROL_BIG;
-		if (cpu->byte_order == EMUL_BIG_ENDIAN)
-			old_control |= ARM_CONTROL_BIG;
-
-		if ((old_control & ARM_CONTROL_BIG) !=
-		    (cpu->cd.arm.control & ARM_CONTROL_BIG)) {
-			fatal("ERROR: Trying to switch endianness. Not "
-			    "supported yet.\n");
-			exit(1);
-		}
-		if ((old_control & ARM_CONTROL_ICACHE) !=
-		    (cpu->cd.arm.control & ARM_CONTROL_ICACHE))
-			debug("[ %s the icache ]\n", cpu->cd.arm.control &
-			    ARM_CONTROL_ICACHE? "enabling" : "disabling");
-		/*  TODO: More bits.  */
-		break;
-
-	case 2:	/*  Translation Table Base register:  */
-		/*  NOTE: 16 KB aligned.  */
-		if (l_bit)
-			cpu->cd.arm.r[rd] = cpu->cd.arm.ttb & 0xffffc000;
-		else {
-			cpu->cd.arm.ttb = cpu->cd.arm.r[rd];
-			if (cpu->cd.arm.ttb & 0x3fff)
-				fatal("[ WARNING! low bits of new TTB non-"
-				    "zero? 0x%08x ]\n", cpu->cd.arm.ttb);
-			cpu->cd.arm.ttb &= 0xffffc000;
-		}
-		break;
-
-	case 3:	/*  Domain Access Control Register:  */
-		if (l_bit)
-			cpu->cd.arm.r[rd] = cpu->cd.arm.dacr;
-		else
-			cpu->cd.arm.dacr = cpu->cd.arm.r[rd];
-		break;
-
-	case 5:	/*  Fault Status Register:  */
-		/*  Note: Only the lowest 8 bits are defined.  */
-		if (l_bit)
-			cpu->cd.arm.r[rd] = cpu->cd.arm.fsr & 0xff;
-		else
-			cpu->cd.arm.fsr = cpu->cd.arm.r[rd] & 0xff;
-		break;
-
-	case 6:	/*  Fault Address Register:  */
-		if (l_bit)
-			cpu->cd.arm.r[rd] = cpu->cd.arm.far;
-		else
-			cpu->cd.arm.far = cpu->cd.arm.r[rd];
-		break;
-
-	case 7:	/*  Cache functions:  */
-		if (l_bit) {
-			fatal("[ arm_coproc_15: attempt to read cr7? ]\n");
-			return;
-		}
-		/*  debug("[ arm_coproc_15: cache op: TODO ]\n");  */
-		/*  TODO:  */
-		break;
-
-	case 8:	/*  TLB functions:  */
-		if (l_bit) {
-			fatal("[ arm_coproc_15: attempt to read cr8? ]\n");
-			return;
-		}
-		/*  fatal("[ arm_coproc_15: TLB: op2=%i crm=%i rd=0x%08x ]\n",
-		    opcode2, crm, cpu->cd.arm.r[rd]);  */
-		if (opcode2 == 0)
-			cpu->invalidate_translation_caches(cpu, 0,
-			    INVALIDATE_ALL);
-		else
-			cpu->invalidate_translation_caches(cpu,
-			    cpu->cd.arm.r[rd], INVALIDATE_VADDR);
-		break;
-
-	case 9:	/*  Cache lockdown:  */
-		fatal("[ arm_coproc_15: cache lockdown: TODO ]\n");
-		/*  TODO  */
-		break;
-
-	case 13:/*  Process ID Register:  */
-		if (opcode2 != 0)
-			debug("[ arm_coproc_15: PID access, but opcode2 "
-			    "= %i? (should be 0) ]\n", opcode2);
-		if (crm != 0)
-			fatal("[ arm_coproc_15: PID access, but crm "
-			    "= %i? (should be 0) ]\n", crm);
-		if (l_bit)
-			cpu->cd.arm.r[rd] = cpu->cd.arm.pid;
-		else
-			cpu->cd.arm.pid = cpu->cd.arm.r[rd];
-		if (cpu->cd.arm.pid != 0) {
-			fatal("ARM TODO: pid!=0. Fast Context Switch"
-			    " Extension not implemented yet\n");
-			exit(1);
-		}
-		break;
-
-	/*  case 14:  */
-		/*  Breakpoint registers on XScale (possibly others?)  */
-		/*  TODO  */
-		/*  break;  */
-
-	case 15:/*  IMPLEMENTATION DEPENDENT!  */
-		switch (crm) {
-		case 1:	/*
-			 *  On XScale (and others? TODO), this is the
-			 *  CoProcessor Access Register.  Note/TODO: This isn't
-			 *  really used throughout the rest of the code yet.
-			 */
-			if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.cpar;
-			else
-				cpu->cd.arm.cpar = cpu->cd.arm.r[rd];
-			break;
-		default:fatal("[ TODO: arm_coproc_15: IMPLEMENTATION "
-			    "DEPENDENT! ]\n");
-			// exit(1);
-		}
-		break;
-
-	default:fatal("[ TODO: arm_coproc_15: unimplemented crn = %i ", crn);
-		fatal("(opcode1=%i opcode2=%i crm=%i rd=%i l=%i) ]\n",
-		    opcode1, opcode2, crm, rd, l_bit);
-		// exit(1);
-	}
-}
-
-
-/*
- *  arm_coproc_i80321_6():
- *
- *  Intel 80321 coprocessor 6.
- */
-void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
-	int crn, int crm, int rd)
-{
-	switch (crm) {
-
-	case 0:	switch (crn) {
-		case 0:	if (l_bit) {
-				cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_inten;
-				fatal("TODO: XScale read from inten?\n");
-				exit(1);
-			} else
-				cpu->cd.arm.i80321_inten = cpu->cd.arm.r[rd];
-			break;
-		case 4:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_isteer;
-			else {
-				cpu->cd.arm.i80321_isteer = cpu->cd.arm.r[rd];
-				if (cpu->cd.arm.r[rd] != 0) {
-					fatal("ARM xscale interrupt steering"
-					    " is not yet implemented\n");
-					exit(1);
-				}
-			}
-			break;
-		case 8:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_isrc;
-			else {
-				cpu->cd.arm.i80321_isrc = cpu->cd.arm.r[rd];
-				fatal("TODO: XScale int ack?\n");
-				exit(1);
-			}
-			break;
-		default:goto unknown;
-		}
-		break;
-
-	case 1:	/*  fatal("TIMER opcode1=%i opcode2=%i crn="
-    "%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn, crm, rd, l_bit);  */
-
-		switch (crn) {
-		case 0:	/*  tmr0:  */
-			if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.tmr0;
-			else
-				cpu->cd.arm.tmr0 = cpu->cd.arm.r[rd];
-			break;
-		case 1:	/*  tmr1:  */
-			if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.tmr1;
-			else
-				cpu->cd.arm.tmr1 = cpu->cd.arm.r[rd];
-			break;
-		case 2:	/*  tcr0:  */
-			if (l_bit) {
-				/*  NOTE/TODO: Ugly hack: timer increment  */
-				cpu->cd.arm.tcr0 ++;
-				cpu->cd.arm.r[rd] = cpu->cd.arm.tcr0;
-			} else {
-				cpu->cd.arm.tcr0 = cpu->cd.arm.r[rd];
-			}
-			break;
-		case 3:	/*  tcr1:  */
-			if (l_bit) {
-				/*  NOTE/TODO: Ugly hack: timer increment  */
-				cpu->cd.arm.tcr1 ++;
-				cpu->cd.arm.r[rd] = cpu->cd.arm.tcr1;
-			} else {
-				cpu->cd.arm.tcr1 = cpu->cd.arm.r[rd];
-			}
-			break;
-		case 4:	/*  trr0:  */
-			if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.trr0;
-			else
-				cpu->cd.arm.trr0 = cpu->cd.arm.r[rd];
-			break;
-		case 5:	/*  trr1:  */
-			if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.trr1;
-			else
-				cpu->cd.arm.trr1 = cpu->cd.arm.r[rd];
-			break;
-		case 6:	/*  tisr:  */
-			if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.tisr;
-			else {
-				/*  Writing clears interrupts:  */
-				cpu->cd.arm.tisr &= ~cpu->cd.arm.r[rd];
-
-				if (!(cpu->cd.arm.tisr & TISR_TMR0))
-					INTERRUPT_DEASSERT(
-					    cpu->cd.arm.tmr0_irq);
-				if (!(cpu->cd.arm.tisr & TISR_TMR1))
-					INTERRUPT_DEASSERT(
-					    cpu->cd.arm.tmr1_irq);
-			}
-			break;
-		case 7:	/*  wdtcr:  */
-			if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.wdtcr;
-			else
-				cpu->cd.arm.wdtcr = cpu->cd.arm.r[rd];
-			break;
-		default:goto unknown;
-		}
-		break;
-
-	default:goto unknown;
-	}
-
-	return;
-
-unknown:
-	fatal("arm_coproc_i80321_6: unimplemented opcode1=%i opcode2=%i crn="
-	    "%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn, crm, rd, l_bit);
-	exit(1);
-}
-
-
-/*
- *  arm_coproc_xscale_14():
- *
- *  XScale coprocessor 14, Performance Monitoring Unit.
- */
-void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
-	int crn, int crm, int rd)
-{
-	if (opcode2 != 0) {
-		fatal("TODO: opcode2 = %i\n", opcode2);
-		goto unknown;
-	}
-
-	switch (crm) {
-
-	case 0:	switch (crn) {
-		case 0:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_pmnc;
-			else
-				cpu->cd.arm.xsc1_pmnc = cpu->cd.arm.r[rd];
-			break;
-		case 1:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_ccnt;
-			else
-				cpu->cd.arm.xsc1_ccnt = cpu->cd.arm.r[rd];
-			break;
-		case 2:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_pmn0;
-			else
-				cpu->cd.arm.xsc1_pmn0 = cpu->cd.arm.r[rd];
-			break;
-		case 3:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_pmn1;
-			else
-				cpu->cd.arm.xsc1_pmn1 = cpu->cd.arm.r[rd];
-			break;
-		case 7:	/*  UNIMPLEMENTED!!! TODO  */
-			/*  Possibly some kind of idle or sleep function.  */
-			break;
-		default:goto unknown;
-		}
-		break;
-
-	case 1:	switch (crn) {
-		case 0:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmnc;
-			else
-				cpu->cd.arm.xsc2_pmnc = cpu->cd.arm.r[rd];
-			break;
-		case 1:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_ccnt;
-			else
-				cpu->cd.arm.xsc2_ccnt = cpu->cd.arm.r[rd];
-			break;
-		case 4:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_inten;
-			else
-				cpu->cd.arm.xsc2_inten = cpu->cd.arm.r[rd];
-			break;
-		case 5:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_flag;
-			else
-				cpu->cd.arm.xsc2_flag = cpu->cd.arm.r[rd];
-			break;
-		case 8:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_evtsel;
-			else
-				cpu->cd.arm.xsc2_evtsel = cpu->cd.arm.r[rd];
-			break;
-		default:goto unknown;
-		}
-		break;
-
-	case 2:	switch (crn) {
-		case 0:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn0;
-			else
-				cpu->cd.arm.xsc2_pmn0 = cpu->cd.arm.r[rd];
-			break;
-		case 1:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn1;
-			else
-				cpu->cd.arm.xsc2_pmn1 = cpu->cd.arm.r[rd];
-			break;
-		case 2:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn2;
-			else
-				cpu->cd.arm.xsc2_pmn2 = cpu->cd.arm.r[rd];
-			break;
-		case 3:	if (l_bit)
-				cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn3;
-			else
-				cpu->cd.arm.xsc2_pmn3 = cpu->cd.arm.r[rd];
-			break;
-		default:goto unknown;
-		}
-		break;
-
-	default:goto unknown;
-	}
-
-	return;
-
-unknown:
-	fatal("arm_coproc_xscale_14: unimplemented opcode1=%i opcode2="
-	    "%i crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn,
-	    crm, rd, l_bit);
-	exit(1);
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_arm_instr.c gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr.c
--- gxemul-0.6.2/src/cpus/cpu_arm_instr.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,3822 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  ARM instructions.
+ *
+ *  Individual functions should keep track of cpu->n_translated_instrs.
+ *  (If no instruction was executed, then it should be decreased. If, say, 4
+ *  instructions were combined into one function and executed, then it should
+ *  be increased by 3.)
+ *
+ *  Note: cpu->pc is prefered over r[ARM_PC]. r[ARM_PC] is only used in a
+ *        few places, and should always be kept in synch with the real
+ *        program counter.
+ */
+
+
+/*  #define GATHER_BDT_STATISTICS  */
+
+
+#ifdef GATHER_BDT_STATISTICS
+/*
+ *  update_bdt_statistics():
+ *
+ *  Gathers statistics about load/store multiple instructions.
+ *
+ *  NOTE/TODO: Perhaps it would be more memory efficient to swap the high
+ *  and low parts of the instruction word, so that the lllllll bits become
+ *  the high bits; this would cause fewer host pages to be used. Anyway, the
+ *  current implementation works on hosts with lots of RAM.
+ *
+ *  The resulting file, bdt_statistics.txt, should then be processed like
+ *  this to give a new cpu_arm_multi.txt:
+ *
+ *  uniq -c bdt_statistics.txt|sort -nr|head -256|cut -f 2 > cpu_arm_multi.txt
+ */
+static void update_bdt_statistics(uint32_t iw)
+{
+	static FILE *f = NULL;
+	static long long *counts;
+	static char *counts_used;
+	static long long n = 0;
+
+	if (f == NULL) {
+		size_t s = (1 << 24) * sizeof(long long);
+		f = fopen("bdt_statistics.txt", "w");
+		if (f == NULL) {
+			fprintf(stderr, "update_bdt_statistics(): :-(\n");
+			exit(1);
+		}
+		counts = zeroed_alloc(s);
+		counts_used = zeroed_alloc(65536);
+	}
+
+	/*  Drop the s-bit: xxxx100P USWLnnnn llllllll llllllll  */
+	iw = ((iw & 0x01800000) >> 1) | (iw & 0x003fffff);
+
+	counts_used[iw & 0xffff] = 1;
+	counts[iw] ++;
+
+	n ++;
+	if ((n % 500000) == 0) {
+		int i;
+		long long j;
+		fatal("[ update_bdt_statistics(): n = %lli ]\n", (long long) n);
+		fseek(f, 0, SEEK_SET);
+		for (i=0; i<0x1000000; i++)
+			if (counts_used[i & 0xffff] && counts[i] != 0) {
+				/*  Recreate the opcode:  */
+				uint32_t opcode = ((i & 0x00c00000) << 1)
+				    | (i & 0x003fffff) | 0x08000000;
+				for (j=0; j<counts[i]; j++)
+					fprintf(f, "0x%08x\n", opcode);
+			}
+		fflush(f);
+	}
+}
+#endif
+
+
+/*****************************************************************************/
+
+
+/*
+ *  Helper definitions:
+ *
+ *  Each instruction is defined like this:
+ *
+ *	X(foo)
+ *	{
+ *		code for foo;
+ *	}
+ *	Y(foo)
+ *
+ *  The Y macro defines 14 copies of the instruction, one for each possible
+ *  condition code. (The NV condition code is not included, and the AL code
+ *  uses the main foo function.)  Y also defines an array with pointers to
+ *  all of these functions.
+ *
+ *  If the compiler is good enough (i.e. allows long enough code sequences
+ *  to be inlined), then the Y functions will be compiled as full (inlined)
+ *  functions, otherwise they will simply call the X function.
+ */
+
+uint8_t condition_hi[16] = { 0,0,1,1, 0,0,0,0, 0,0,1,1, 0,0,0,0 };
+uint8_t condition_ge[16] = { 1,0,1,0, 1,0,1,0, 0,1,0,1, 0,1,0,1 };
+uint8_t condition_gt[16] = { 1,0,1,0, 0,0,0,0, 0,1,0,1, 0,0,0,0 };
+
+#define Y(n) void arm_instr_ ## n ## __eq(struct cpu *cpu,		\
+			struct arm_instr_call *ic)			\
+	{  if (cpu->cd.arm.flags & ARM_F_Z)				\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __ne(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (!(cpu->cd.arm.flags & ARM_F_Z))				\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __cs(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (cpu->cd.arm.flags & ARM_F_C)				\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __cc(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (!(cpu->cd.arm.flags & ARM_F_C))				\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __mi(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (cpu->cd.arm.flags & ARM_F_N)				\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __pl(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (!(cpu->cd.arm.flags & ARM_F_N))				\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __vs(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (cpu->cd.arm.flags & ARM_F_V)				\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __vc(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (!(cpu->cd.arm.flags & ARM_F_V))				\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __hi(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (condition_hi[cpu->cd.arm.flags])				\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __ls(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (!condition_hi[cpu->cd.arm.flags])			\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __ge(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (condition_ge[cpu->cd.arm.flags])				\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __lt(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (!condition_ge[cpu->cd.arm.flags])			\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __gt(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (condition_gt[cpu->cd.arm.flags])				\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void arm_instr_ ## n ## __le(struct cpu *cpu,			\
+			struct arm_instr_call *ic)			\
+	{  if (!condition_gt[cpu->cd.arm.flags])			\
+		arm_instr_ ## n (cpu, ic);		}		\
+	void (*arm_cond_instr_ ## n  [16])(struct cpu *,		\
+			struct arm_instr_call *) = {			\
+		arm_instr_ ## n ## __eq, arm_instr_ ## n ## __ne,	\
+		arm_instr_ ## n ## __cs, arm_instr_ ## n ## __cc,	\
+		arm_instr_ ## n ## __mi, arm_instr_ ## n ## __pl,	\
+		arm_instr_ ## n ## __vs, arm_instr_ ## n ## __vc,	\
+		arm_instr_ ## n ## __hi, arm_instr_ ## n ## __ls,	\
+		arm_instr_ ## n ## __ge, arm_instr_ ## n ## __lt,	\
+		arm_instr_ ## n ## __gt, arm_instr_ ## n ## __le,	\
+		arm_instr_ ## n , arm_instr_never };
+
+#define cond_instr(n)	( arm_cond_instr_ ## n  [condition_code] )
+
+
+/*****************************************************************************/
+
+
+/*
+ *  invalid:  Invalid instructions end up here.
+ */
+X(invalid) {
+	uint32_t low_pc;
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1)
+	    << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+
+	fatal("FATAL ERROR: An internal error occured in the ARM"
+	    " dyntrans code. This could be due to an unimplemented instruction"
+	    " encoding. pc = 0x%08" PRIx32"\n",
+	    (uint32_t)cpu->pc);
+
+	cpu->cd.arm.next_ic = &nothing_call;
+}
+
+
+/*
+ *  never:  So far unimplemented "never" instructions end up here.
+ *  (Those are the ones using the "0xf" condition prefix.)
+ */
+X(never) {
+	uint32_t low_pc;
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1)
+	    << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+
+	fatal("[ ARM: unimplemented 0xf instruction at pc = 0x%08" PRIx32" ]\n", (uint32_t)cpu->pc);
+
+	cpu->cd.arm.next_ic = &nothing_call;
+}
+
+
+/*
+ *  nop:  Do nothing.
+ */
+X(nop)
+{
+}
+
+
+/*
+ *  b:  Branch (to a different translated page)
+ *
+ *  arg[0] = relative offset from start of page
+ */
+X(b)
+{
+	cpu->pc = (uint32_t)((cpu->pc & 0xfffff000) + (int32_t)ic->arg[0]);
+
+	/*  Find the new physical page and update the translation pointers:  */
+	quick_pc_to_pointers_arm(cpu);
+}
+Y(b)
+
+
+/*
+ *  b_samepage:  Branch (to within the same translated page)
+ *
+ *  arg[0] = pointer to new arm_instr_call
+ *  arg[1] = pointer to the next instruction.
+ *
+ *  NOTE: This instruction is manually inlined.
+ */
+X(b_samepage) {
+	cpu->cd.arm.next_ic = (struct arm_instr_call *) ic->arg[0];
+}
+X(b_samepage__eq) {
+	cpu->cd.arm.next_ic = (struct arm_instr_call *)
+	    ic->arg[cpu->cd.arm.flags & ARM_F_Z? 0 : 1];
+}
+X(b_samepage__ne) {
+	cpu->cd.arm.next_ic = (struct arm_instr_call *)
+	    ic->arg[cpu->cd.arm.flags & ARM_F_Z? 1 : 0];
+}
+X(b_samepage__cs) {
+	cpu->cd.arm.next_ic = (struct arm_instr_call *)
+	    ic->arg[cpu->cd.arm.flags & ARM_F_C? 0 : 1];
+}
+X(b_samepage__cc) {
+	cpu->cd.arm.next_ic = (struct arm_instr_call *)
+	    ic->arg[cpu->cd.arm.flags & ARM_F_C? 1 : 0];
+}
+X(b_samepage__mi) {
+	cpu->cd.arm.next_ic = (struct arm_instr_call *)
+	    ic->arg[cpu->cd.arm.flags & ARM_F_N? 0 : 1];
+}
+X(b_samepage__pl) {
+	cpu->cd.arm.next_ic = (struct arm_instr_call *)
+	    ic->arg[cpu->cd.arm.flags & ARM_F_N? 1 : 0];
+}
+X(b_samepage__vs) {
+	cpu->cd.arm.next_ic = (struct arm_instr_call *)
+	    ic->arg[cpu->cd.arm.flags & ARM_F_V? 0 : 1];
+}
+X(b_samepage__vc) {
+	cpu->cd.arm.next_ic = (struct arm_instr_call *)
+	    ic->arg[cpu->cd.arm.flags & ARM_F_V? 1 : 0];
+}
+X(b_samepage__hi) {
+	cpu->cd.arm.next_ic = (condition_hi[cpu->cd.arm.flags])?
+	    (struct arm_instr_call *) ic->arg[0] :
+	    (struct arm_instr_call *) ic->arg[1];
+}
+X(b_samepage__ls) {
+	cpu->cd.arm.next_ic = (struct arm_instr_call *)
+	    ic->arg[condition_hi[cpu->cd.arm.flags]];
+}
+X(b_samepage__ge) {
+	cpu->cd.arm.next_ic = (condition_ge[cpu->cd.arm.flags])?
+	    (struct arm_instr_call *) ic->arg[0] :
+	    (struct arm_instr_call *) ic->arg[1];
+}
+X(b_samepage__lt) {
+	cpu->cd.arm.next_ic = (struct arm_instr_call *)
+	    ic->arg[condition_ge[cpu->cd.arm.flags]];
+}
+X(b_samepage__gt) {
+	cpu->cd.arm.next_ic = (condition_gt[cpu->cd.arm.flags])?
+	    (struct arm_instr_call *) ic->arg[0] :
+	    (struct arm_instr_call *) ic->arg[1];
+}
+X(b_samepage__le) {
+	cpu->cd.arm.next_ic = (struct arm_instr_call *)
+	    ic->arg[condition_gt[cpu->cd.arm.flags]];
+}
+void (*arm_cond_instr_b_samepage[16])(struct cpu *,
+	struct arm_instr_call *) = {
+	arm_instr_b_samepage__eq, arm_instr_b_samepage__ne,
+	arm_instr_b_samepage__cs, arm_instr_b_samepage__cc,
+	arm_instr_b_samepage__mi, arm_instr_b_samepage__pl,
+	arm_instr_b_samepage__vs, arm_instr_b_samepage__vc,
+	arm_instr_b_samepage__hi, arm_instr_b_samepage__ls,
+	arm_instr_b_samepage__ge, arm_instr_b_samepage__lt,
+	arm_instr_b_samepage__gt, arm_instr_b_samepage__le,
+	arm_instr_b_samepage, arm_instr_nop };
+
+
+/*
+ *  bx:  Branch, potentially exchanging Thumb/ARM encoding
+ *
+ *  arg[0] = ptr to rm
+ */
+X(bx)
+{
+	uint32_t old_cpsr = cpu->cd.arm.cpsr;
+	cpu->pc = reg(ic->arg[0]);
+	if (cpu->pc & 1)
+		cpu->cd.arm.cpsr |= ARM_FLAG_T;
+	else
+		cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
+
+	if (cpu->cd.arm.cpsr != old_cpsr)
+		cpu->cd.arm.next_ic = &nothing_call;
+
+	if (cpu->pc & 2 && ((cpu->pc & 1) == 0)) {
+		fatal("[ ARM pc misaligned? 0x%08x ]\n", (int)cpu->pc);
+		cpu->running = 0;
+		cpu->n_translated_instrs --;
+		cpu->cd.arm.next_ic = &nothing_call;
+		return;
+	}
+
+	/*  Find the new physical page and update the translation pointers:  */
+	quick_pc_to_pointers_arm(cpu);
+}
+Y(bx)
+
+
+/*
+ *  bx_trace:  As bx, but with trace enabled, arg[0] = the link register.
+ *
+ *  arg[0] = ignored
+ */
+X(bx_trace)
+{
+	uint32_t old_cpsr = cpu->cd.arm.cpsr;
+	cpu->pc = cpu->cd.arm.r[ARM_LR];
+	if (cpu->pc & 1)
+		cpu->cd.arm.cpsr |= ARM_FLAG_T;
+	else
+		cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
+
+	if (cpu->cd.arm.cpsr != old_cpsr)
+		cpu->cd.arm.next_ic = &nothing_call;
+
+	if (cpu->pc & 2 && ((cpu->pc & 1) == 0)) {
+		fatal("[ ARM pc misaligned? 0x%08x ]\n", (int)cpu->pc);
+		cpu->running = 0;
+		cpu->n_translated_instrs --;
+		cpu->cd.arm.next_ic = &nothing_call;
+		return;
+	}
+
+	cpu_functioncall_trace_return(cpu);
+
+	/*  Find the new physical page and update the translation pointers:  */
+	quick_pc_to_pointers_arm(cpu);
+}
+Y(bx_trace)
+
+
+/*
+ *  bl:  Branch and Link (to a different translated page)
+ *
+ *  arg[0] = relative address
+ *  arg[1] = offset within current page to the instruction
+ */
+X(bl)
+{
+	uint32_t pc = ((uint32_t)cpu->pc & 0xfffff000) + (int32_t)ic->arg[1];
+	cpu->cd.arm.r[ARM_LR] = pc + 4;
+
+	/*  Calculate new PC from this instruction + arg[0]  */
+	cpu->pc = pc + (int32_t)ic->arg[0];
+
+	/*  Find the new physical page and update the translation pointers:  */
+	quick_pc_to_pointers_arm(cpu);
+}
+Y(bl)
+
+
+/*
+ *  blx_imm:  Branch and Link, always switching to THUMB encoding
+ *
+ *  arg[0] = relative address
+ *  arg[1] = offset within current page to the current instruction
+ */
+X(blx_imm)
+{
+	uint32_t pc = ((uint32_t)cpu->pc & 0xfffff000) + (int32_t)ic->arg[1];
+	uint32_t old_cpsr = cpu->cd.arm.cpsr;
+	cpu->cd.arm.r[ARM_LR] = pc + 4;
+
+	/*  Calculate new PC from this instruction + arg[0]  */
+	cpu->pc = pc + (int32_t)ic->arg[0];
+
+	if (cpu->pc & 1)
+		cpu->cd.arm.cpsr |= ARM_FLAG_T;
+	else {
+		fatal("[ blx_imm internal error. Should have switched to THUMB! 0x%08x ]\n", (int)cpu->pc);
+		cpu->running = 0;
+		cpu->n_translated_instrs --;
+		cpu->cd.arm.next_ic = &nothing_call;
+		return;
+	}
+
+	if (cpu->cd.arm.cpsr != old_cpsr)
+		cpu->cd.arm.next_ic = &nothing_call;
+
+	if (cpu->pc & 2 && ((cpu->pc & 1) == 0)) {
+		fatal("[ ARM pc misaligned? 0x%08x ]\n", (int)cpu->pc);
+		cpu->running = 0;
+		cpu->n_translated_instrs --;
+		cpu->cd.arm.next_ic = &nothing_call;
+		return;
+	}
+
+	if (cpu->machine->show_trace_tree)
+		cpu_functioncall_trace(cpu, cpu->pc);
+
+	/*  Find the new physical page and update the translation pointers:  */
+	quick_pc_to_pointers_arm(cpu);
+}
+
+
+/*
+ *  blx_reg:  Branch and Link, potentially exchanging Thumb/ARM encoding
+ *
+ *  arg[0] = ptr to rm
+ *  arg[2] = offset within current page to the instruction to return to
+ */
+X(blx_reg)
+{
+	uint32_t lr = ((uint32_t)cpu->pc & 0xfffff000) + (int32_t)ic->arg[2];
+	cpu->cd.arm.r[ARM_LR] = lr;
+	cpu->pc = reg(ic->arg[0]);
+
+	uint32_t old_cpsr = cpu->cd.arm.cpsr;
+	if (cpu->pc & 1)
+		cpu->cd.arm.cpsr |= ARM_FLAG_T;
+	else
+		cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
+
+	if (cpu->cd.arm.cpsr != old_cpsr)
+		cpu->cd.arm.next_ic = &nothing_call;
+
+	if (cpu->pc & 2 && ((cpu->pc & 1) == 0)) {
+		fatal("[ ARM pc misaligned? 0x%08x ]\n", (int)cpu->pc);
+		cpu->running = 0;
+		cpu->n_translated_instrs --;
+		cpu->cd.arm.next_ic = &nothing_call;
+		return;
+	}
+
+	/*  Find the new physical page and update the translation pointers:  */
+	quick_pc_to_pointers_arm(cpu);
+}
+Y(blx_reg)
+
+
+/*
+ *  bl_trace:  Branch and Link (to a different translated page), with trace
+ *
+ *  Same as for bl.
+ */
+X(bl_trace)
+{
+	uint32_t pc = ((uint32_t)cpu->pc & 0xfffff000) + (int32_t)ic->arg[1];
+	cpu->cd.arm.r[ARM_LR] = pc + 4;
+
+	/*  Calculate new PC from this instruction + arg[0]  */
+	cpu->pc = pc + (int32_t)ic->arg[0];
+
+	cpu_functioncall_trace(cpu, cpu->pc);
+
+	/*  Find the new physical page and update the translation pointers:  */
+	quick_pc_to_pointers_arm(cpu);
+}
+Y(bl_trace)
+
+
+/*
+ *  bl_samepage:  A branch + link within the same page
+ *
+ *  arg[0] = pointer to new arm_instr_call
+ */
+X(bl_samepage)
+{
+	cpu->cd.arm.r[ARM_LR] =
+	    ((uint32_t)cpu->pc & 0xfffff000) + (int32_t)ic->arg[2];
+	cpu->cd.arm.next_ic = (struct arm_instr_call *) ic->arg[0];
+}
+Y(bl_samepage)
+
+
+/*
+ *  bl_samepage_trace:  Branch and Link (to the same page), with trace
+ *
+ *  Same as for bl_samepage.
+ */
+X(bl_samepage_trace)
+{
+	uint32_t low_pc, lr = (cpu->pc & 0xfffff000) + ic->arg[2];
+
+	/*  Link and branch:  */
+	cpu->cd.arm.r[ARM_LR] = lr;
+	cpu->cd.arm.next_ic = (struct arm_instr_call *) ic->arg[0];
+
+	/*  Synchronize the program counter:  */
+	low_pc = ((size_t)cpu->cd.arm.next_ic - (size_t)
+	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1)
+	    << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+
+	/*  ... and show trace:  */
+	cpu_functioncall_trace(cpu, cpu->pc);
+}
+Y(bl_samepage_trace)
+
+
+/*
+ *  clz: Count leading zeroes.
+ *
+ *  arg[0] = ptr to rm
+ *  arg[1] = ptr to rd
+ */
+X(clz)
+{
+	uint32_t rm = reg(ic->arg[0]);
+	int i = 32, n = 0, j;
+	while (i>0) {
+		if (rm & 0xff000000) {
+			for (j=0; j<8; j++) {
+				if (rm & 0x80000000)
+					break;
+				n ++;
+				rm <<= 1;
+			}
+			break;
+		} else {
+			rm <<= 8;
+			i -= 8;
+			n += 8;
+		}
+	}
+	reg(ic->arg[1]) = n;
+}
+Y(clz)
+
+
+/*
+ *  mul: Multiplication
+ *
+ *  arg[0] = ptr to rd
+ *  arg[1] = ptr to rm
+ *  arg[2] = ptr to rs
+ */
+X(mul)
+{
+	reg(ic->arg[0]) = reg(ic->arg[1]) * reg(ic->arg[2]);
+}
+Y(mul)
+X(muls)
+{
+	uint32_t result;
+	result = reg(ic->arg[1]) * reg(ic->arg[2]);
+	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+	if (result == 0)
+		cpu->cd.arm.flags |= ARM_F_Z;
+	if (result & 0x80000000)
+		cpu->cd.arm.flags |= ARM_F_N;
+	reg(ic->arg[0]) = result;
+}
+Y(muls)
+
+
+/*
+ *  mla: Multiplication with addition
+ *
+ *  arg[0] = copy of instruction word
+ */
+X(mla)
+{
+	/*  xxxx0000 00ASdddd nnnnssss 1001mmmm (Rd,Rm,Rs[,Rn])  */
+	uint32_t iw = ic->arg[0];
+	int rd, rs, rn, rm;
+	rd = (iw >> 16) & 15; rn = (iw >> 12) & 15,
+	rs = (iw >> 8) & 15;  rm = iw & 15;
+	cpu->cd.arm.r[rd] = cpu->cd.arm.r[rm] * cpu->cd.arm.r[rs]
+	    + cpu->cd.arm.r[rn];
+}
+Y(mla)
+X(mlas)
+{
+	/*  xxxx0000 00ASdddd nnnnssss 1001mmmm (Rd,Rm,Rs[,Rn])  */
+	uint32_t iw = ic->arg[0];
+	int rd, rs, rn, rm;
+	rd = (iw >> 16) & 15; rn = (iw >> 12) & 15,
+	rs = (iw >> 8) & 15;  rm = iw & 15;
+	cpu->cd.arm.r[rd] = cpu->cd.arm.r[rm] * cpu->cd.arm.r[rs]
+	    + cpu->cd.arm.r[rn];
+	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+	if (cpu->cd.arm.r[rd] == 0)
+		cpu->cd.arm.flags |= ARM_F_Z;
+	if (cpu->cd.arm.r[rd] & 0x80000000)
+		cpu->cd.arm.flags |= ARM_F_N;
+}
+Y(mlas)
+
+
+/*
+ *  mla: Multiplication with subtraction
+ *
+ *  arg[0] = copy of instruction word
+ */
+X(mls)
+{
+	/*  xxxx0000 0110dddd aaaammmm 1001nnnn  mls Rd,Rn,Rm,Ra  */
+	uint32_t iw = ic->arg[0];
+	int rd = (iw >> 16) & 15;
+	int rn = (iw >>  0) & 15;
+	int rm = (iw >>  8) & 15;
+	int ra = (iw >> 12) & 15;
+
+	cpu->cd.arm.r[rd] = cpu->cd.arm.r[ra] -
+	    cpu->cd.arm.r[rn] * cpu->cd.arm.r[rm];
+}
+Y(mls)
+
+
+/*
+ *  mull: Long multiplication
+ *
+ *  arg[0] = copy of instruction word
+ */
+X(mull)
+{
+	/*  xxxx0000 1UAShhhh llllssss 1001mmmm  */
+	uint32_t iw; uint64_t tmp; int u_bit, a_bit;
+	iw = ic->arg[0];
+	u_bit = iw & 0x00400000; a_bit = iw & 0x00200000;
+	tmp = cpu->cd.arm.r[iw & 15];
+	if (u_bit)
+		tmp = (int64_t)(int32_t)tmp
+		    * (int64_t)(int32_t)cpu->cd.arm.r[(iw >> 8) & 15];
+	else
+		tmp *= (uint64_t)cpu->cd.arm.r[(iw >> 8) & 15];
+	if (a_bit) {
+		uint64_t x = ((uint64_t)cpu->cd.arm.r[(iw >> 16) & 15] << 32)
+		    | cpu->cd.arm.r[(iw >> 12) & 15];
+		x += tmp;
+		cpu->cd.arm.r[(iw >> 16) & 15] = (x >> 32);
+		cpu->cd.arm.r[(iw >> 12) & 15] = x;
+	} else {
+		cpu->cd.arm.r[(iw >> 16) & 15] = (tmp >> 32);
+		cpu->cd.arm.r[(iw >> 12) & 15] = tmp;
+	}
+}
+Y(mull)
+
+
+/*
+ *  smulXY:  16-bit * 16-bit multiplication (32-bit result)
+ *
+ *  arg[0] = ptr to rm
+ *  arg[1] = ptr to rs
+ *  arg[2] = ptr to rd
+ */
+X(smulbb)
+{
+	reg(ic->arg[2]) = (int32_t)(int16_t)reg(ic->arg[0]) *
+	    (int32_t)(int16_t)reg(ic->arg[1]);
+}
+Y(smulbb)
+X(smultb)
+{
+	reg(ic->arg[2]) = (int32_t)(int16_t)(reg(ic->arg[0]) >> 16) *
+	    (int32_t)(int16_t)reg(ic->arg[1]);
+}
+Y(smultb)
+X(smulbt)
+{
+	reg(ic->arg[2]) = (int32_t)(int16_t)reg(ic->arg[0]) *
+	    (int32_t)(int16_t)(reg(ic->arg[1]) >> 16);
+}
+Y(smulbt)
+X(smultt)
+{
+	reg(ic->arg[2]) = (int32_t)(int16_t)(reg(ic->arg[0]) >> 16) *
+	    (int32_t)(int16_t)(reg(ic->arg[1]) >> 16);
+}
+Y(smultt)
+
+
+/*
+ *  mov_reg_reg:  Move a register to another.
+ *
+ *  arg[0] = ptr to source register
+ *  arg[1] = ptr to destination register
+ */
+X(mov_reg_reg)
+{
+	reg(ic->arg[1]) = reg(ic->arg[0]);
+}
+Y(mov_reg_reg)
+
+
+/*
+ *  mov_reg_pc:  Move the PC register to a normal register.
+ *
+ *  arg[0] = offset compared to start of current page + 8
+ *  arg[1] = ptr to destination register
+ */
+X(mov_reg_pc)
+{
+	reg(ic->arg[1]) = ((uint32_t)cpu->pc&0xfffff000) + (int32_t)ic->arg[0];
+}
+Y(mov_reg_pc)
+
+
+/*
+ *  ret_trace:  "mov pc,lr" with trace enabled
+ *  ret:  "mov pc,lr" without trace enabled
+ *
+ *  arg[0] = ignored
+ */
+X(ret_trace)
+{
+	uint32_t old_pc, mask_within_page;
+	old_pc = cpu->pc;
+	mask_within_page = ((ARM_IC_ENTRIES_PER_PAGE-1)
+	    << ARM_INSTR_ALIGNMENT_SHIFT) |
+	    ((1 << ARM_INSTR_ALIGNMENT_SHIFT) - 1);
+
+	/*  Update the PC register:  */
+	cpu->pc = cpu->cd.arm.r[ARM_LR];
+
+	cpu_functioncall_trace_return(cpu);
+
+	/*
+	 *  Is this a return to code within the same page? Then there is no
+	 *  need to update all pointers, just next_ic.
+	 */
+	if ((old_pc & ~mask_within_page) == (cpu->pc & ~mask_within_page)) {
+		cpu->cd.arm.next_ic = cpu->cd.arm.cur_ic_page +
+		    ((cpu->pc & mask_within_page) >> ARM_INSTR_ALIGNMENT_SHIFT);
+	} else {
+		/*  Find the new physical page and update pointers:  */
+		quick_pc_to_pointers_arm(cpu);
+	}
+}
+Y(ret_trace)
+X(ret)
+{
+	cpu->pc = cpu->cd.arm.r[ARM_LR];
+	quick_pc_to_pointers_arm(cpu);
+}
+Y(ret)
+
+
+/*
+ *  msr: Move to status register from a normal register or immediate value.
+ *
+ *  arg[0] = immediate value
+ *  arg[1] = mask
+ *  arg[2] = pointer to rm
+ *
+ *  msr_imm and msr_imm_spsr use arg[1] and arg[0].
+ *  msr and msr_spsr use arg[1] and arg[2].
+ */
+X(msr_imm)
+{
+	uint32_t mask = ic->arg[1];
+
+	if ((cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32) {
+		mask &= 0xff000000;
+	}
+
+	int switch_register_banks = (mask & ARM_FLAG_MODE) &&
+	    ((cpu->cd.arm.cpsr & ARM_FLAG_MODE) !=
+	    (ic->arg[0] & ARM_FLAG_MODE));
+	uint32_t new_value = ic->arg[0];
+
+	cpu->cd.arm.cpsr &= 0x0fffffff;
+	cpu->cd.arm.cpsr |= (cpu->cd.arm.flags << 28);
+
+	if (switch_register_banks)
+		arm_save_register_bank(cpu);
+
+	cpu->cd.arm.cpsr &= ~mask;
+	cpu->cd.arm.cpsr |= (new_value & mask);
+
+	cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28;
+
+	if (switch_register_banks)
+		arm_load_register_bank(cpu);
+}
+Y(msr_imm)
+X(msr)
+{
+	ic->arg[0] = reg(ic->arg[2]);
+	instr(msr_imm)(cpu, ic);
+}
+Y(msr)
+X(msr_imm_spsr)
+{
+	uint32_t mask = ic->arg[1];
+	uint32_t new_value = ic->arg[0];
+	switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
+	case ARM_MODE_FIQ32:
+		cpu->cd.arm.spsr_fiq &= ~mask;
+		cpu->cd.arm.spsr_fiq |= (new_value & mask);
+		break;
+	case ARM_MODE_ABT32:
+		cpu->cd.arm.spsr_abt &= ~mask;
+		cpu->cd.arm.spsr_abt |= (new_value & mask);
+		break;
+	case ARM_MODE_UND32:
+		cpu->cd.arm.spsr_und &= ~mask;
+		cpu->cd.arm.spsr_und |= (new_value & mask);
+		break;
+	case ARM_MODE_IRQ32:
+		cpu->cd.arm.spsr_irq &= ~mask;
+		cpu->cd.arm.spsr_irq |= (new_value & mask);
+		break;
+	case ARM_MODE_SVC32:
+		cpu->cd.arm.spsr_svc &= ~mask;
+		cpu->cd.arm.spsr_svc |= (new_value & mask);
+		break;
+	default:fatal("msr_spsr: unimplemented mode %i\n",
+		    cpu->cd.arm.cpsr & ARM_FLAG_MODE);
+		{
+			/*  Synchronize the program counter:  */
+			uint32_t old_pc, low_pc = ((size_t)ic - (size_t)
+			    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+			cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+			old_pc = cpu->pc;
+			printf("msr_spsr: old pc = 0x%08" PRIx32"\n", old_pc);
+		}
+		cpu->running = 0;
+		cpu->cd.arm.next_ic = &nothing_call;
+	}
+}
+Y(msr_imm_spsr)
+X(msr_spsr)
+{
+	ic->arg[0] = reg(ic->arg[2]);
+	instr(msr_imm_spsr)(cpu, ic);
+}
+Y(msr_spsr)
+
+
+/*
+ *  mrs: Move from status/flag register to a normal register.
+ *
+ *  arg[0] = pointer to rd
+ */
+X(mrs)
+{
+	cpu->cd.arm.cpsr &= 0x0fffffff;
+	cpu->cd.arm.cpsr |= (cpu->cd.arm.flags << 28);
+	reg(ic->arg[0]) = cpu->cd.arm.cpsr;
+}
+Y(mrs)
+
+
+/*
+ *  mrs: Move from saved status/flag register to a normal register.
+ *
+ *  arg[0] = pointer to rd
+ */
+X(mrs_spsr)
+{
+	switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
+	case ARM_MODE_FIQ32: reg(ic->arg[0]) = cpu->cd.arm.spsr_fiq; break;
+	case ARM_MODE_ABT32: reg(ic->arg[0]) = cpu->cd.arm.spsr_abt; break;
+	case ARM_MODE_UND32: reg(ic->arg[0]) = cpu->cd.arm.spsr_und; break;
+	case ARM_MODE_IRQ32: reg(ic->arg[0]) = cpu->cd.arm.spsr_irq; break;
+	case ARM_MODE_SVC32: reg(ic->arg[0]) = cpu->cd.arm.spsr_svc; break;
+	case ARM_MODE_USR32:
+	case ARM_MODE_SYS32: reg(ic->arg[0]) = 0; break;
+	default:fatal("mrs_spsr: unimplemented mode %i\n", cpu->cd.arm.cpsr & ARM_FLAG_MODE);
+		cpu->running = 0;
+		cpu->cd.arm.next_ic = &nothing_call;
+	}
+}
+Y(mrs_spsr)
+
+
+/*
+ *  mcr_mrc:  Coprocessor move
+ *  cdp:      Coprocessor operation
+ *
+ *  arg[0] = copy of the instruction word
+ */
+X(mcr_mrc) {
+	uint32_t low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+	arm_mcr_mrc(cpu, ic->arg[0]);
+}
+Y(mcr_mrc)
+X(cdp) {
+	uint32_t low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+	arm_cdp(cpu, ic->arg[0]);
+}
+Y(cdp)
+
+
+/*
+ *  openfirmware:
+ */
+X(openfirmware)
+{
+	/*  TODO: sync pc?  */
+	of_emul(cpu);
+	cpu->pc = cpu->cd.arm.r[ARM_LR];
+	if (cpu->machine->show_trace_tree)
+		cpu_functioncall_trace_return(cpu);
+	quick_pc_to_pointers_arm(cpu);
+}
+
+
+/*
+ *  reboot:
+ */
+X(reboot)
+{
+	cpu->running = 0;
+	cpu->n_translated_instrs --;
+	cpu->cd.arm.next_ic = &nothing_call;
+}
+
+
+/*
+ *  swi:  Software interrupt.
+ */
+X(swi)
+{
+	/*  Synchronize the program counter first:  */
+	cpu->pc &= 0xfffff000;
+	cpu->pc += ic->arg[0];
+	arm_exception(cpu, ARM_EXCEPTION_SWI);
+}
+Y(swi)
+
+
+/*
+ * bkpt:  Breakpoint instruction.
+ */
+X(bkpt)
+{
+	/*  Synchronize the program counter first:  */
+	cpu->pc &= 0xfffff000;
+	cpu->pc += ic->arg[0];
+	arm_exception(cpu, ARM_EXCEPTION_PREF_ABT);
+}
+Y(bkpt)
+
+
+/*
+ *  und:  Undefined instruction.
+ */
+X(und)
+{
+	/*  Synchronize the program counter first:  */
+	cpu->pc &= 0xfffff000;
+	cpu->pc += ic->arg[0];
+	arm_exception(cpu, ARM_EXCEPTION_UND);
+}
+Y(und)
+
+
+/*
+ *  movt:  Move Top.
+ *
+ *  arg[1] = 32-bit immediate value. Top 16 bits are those of interest.
+ *  arg[2] = ptr to rd
+ */
+X(movt)
+{
+	reg(ic->arg[2]) &= 0xffff;
+	reg(ic->arg[2]) |= ic->arg[1];
+}
+Y(movt)
+
+
+/*
+ *  movw:  Move (Word).
+ *
+ *  arg[1] = 32-bit immediate value.
+ *  arg[2] = ptr to rd
+ */
+X(movw)
+{
+	reg(ic->arg[2]) = ic->arg[1];
+}
+Y(movw)
+
+
+/*
+ *  rev:  Reverse endian.
+ *
+ *  arg[0] = ptr to rd
+ *  arg[1] = ptr to rm
+ */
+X(rev)
+{
+	uint32_t v = reg(ic->arg[1]);
+
+	reg(ic->arg[0]) = (v >> 24) | ((v & 0x00ff0000) >> 8)
+		| ((v & 0x0000ff00) << 8) | ((v & 0xff) << 24);
+}
+Y(rev)
+
+
+/*
+ *  uxtb:  Unsigned Extend Byte.
+ *
+ *  arg[0] = ptr to rd
+ *  arg[1] = ptr to rm
+ *  arg[2] = rotation amount (shift works too)
+ */
+X(uxtb)
+{
+	uint32_t x = reg(ic->arg[1]);
+	reg(ic->arg[0]) = (uint8_t)(x >> ic->arg[2]);
+}
+Y(uxtb)
+
+
+/*
+ *  sxth:  Signed Extend Halfword.
+ *
+ *  TODO: Could be optimized so that the rotation amount is "inlined".
+ *
+ *  arg[0] = ptr to rd
+ *  arg[1] = ptr to rm
+ *  arg[2] = rotation amount
+ */
+X(sxth)
+{
+	uint32_t x = reg(ic->arg[1]);
+
+	switch (ic->arg[2]) {
+	case 0:	break;
+	case 8: x >>= 8; break;
+	case 16: x >>= 16; break;
+	case 24: x = (x >> 24) | ((x & 255) << 8); break;
+	}
+
+	int16_t rotated = x;
+	reg(ic->arg[0]) = (int32_t)rotated;
+}
+Y(sxth)
+
+
+/*
+ *  uxth:  Unsigned Extend Halfword.
+ *
+ *  TODO: Could be optimized so that the rotation amount is "inlined".
+ *
+ *  arg[0] = ptr to rd
+ *  arg[1] = ptr to rm
+ *  arg[2] = rotation amount
+ */
+X(uxth)
+{
+	uint32_t x = reg(ic->arg[1]);
+
+	switch (ic->arg[2]) {
+	case 0:	break;
+	case 8: x >>= 8; break;
+	case 16: x >>= 16; break;
+	case 24: x = (x >> 24) | ((x & 255) << 8); break;
+	}
+
+	uint16_t rotated = x;
+	reg(ic->arg[0]) = (uint32_t)rotated;
+}
+Y(uxth)
+
+
+/*
+ *  uxtah:  Unsigned Extend and Add Byte.
+ *
+ *  arg[0] = ptr to rd
+ *  arg[1] = ptr to rn
+ *  arg[2] = ptr to rm
+ */
+X(uxtab)
+{
+	reg(ic->arg[0]) = reg(ic->arg[1]) + (uint8_t)reg(ic->arg[2]);
+}
+Y(uxtab)
+
+
+/*
+ *  uxtah:  Unsigned Extend and Add Halfword.
+ *
+ *  arg[0] = ptr to rd
+ *  arg[1] = ptr to rn
+ *  arg[2] = ptr to rm
+ */
+X(uxtah)
+{
+	reg(ic->arg[0]) = reg(ic->arg[1]) + (uint16_t)reg(ic->arg[2]);
+}
+Y(uxtah)
+
+
+/*
+ *  ubfx:  Unsigned Bit-Field Extract.
+ *
+ *  arg[0] = ptr to rd
+ *  arg[1] = ptr to rn
+ *  arg[2] = (width << 16) + lsb
+ */
+X(ubfx)
+{
+	uint32_t x = reg(ic->arg[1]);
+
+	int lsb = (uint8_t)ic->arg[2];
+	int width = ic->arg[2] >> 16;
+
+	uint32_t mask = (1 << width) - 1;
+
+	x >>= lsb;
+	x &= mask;
+
+	reg(ic->arg[0]) = x;
+}
+Y(ubfx)
+
+
+/*
+ *  sbfx:  Signed Bit-Field Extract.
+ *
+ *  arg[0] = ptr to rd
+ *  arg[1] = ptr to rn
+ *  arg[2] = (width << 16) + lsb
+ */
+X(sbfx)
+{
+	uint32_t x = reg(ic->arg[1]);
+
+	int lsb = (uint8_t)ic->arg[2];
+	int width = ic->arg[2] >> 16;
+
+	uint32_t mask = (1 << width) - 1;
+	x >>= lsb;
+	x &= mask;
+
+	uint32_t topBitMask = 1 << (width-1);
+	if (x & topBitMask && width < 32)
+		x |= ~mask;
+
+	reg(ic->arg[0]) = x;
+}
+Y(sbfx)
+
+
+/*
+ *  bfi:  Bit-Field Insert.
+ *
+ *  arg[0] = ptr to rd
+ *  arg[1] = ptr to rn
+ *  arg[2] = (msb << 16) + lsb
+ */
+X(bfi)
+{
+	uint32_t x = reg(ic->arg[1]);
+
+	int lsb = (uint8_t)ic->arg[2];
+	int msb = ic->arg[2] >> 16;
+	int width = msb - lsb + 1;
+
+	x <<= lsb;
+
+	uint32_t mask = (1 << width) - 1;
+
+	mask <<= lsb;
+
+	reg(ic->arg[0]) &= ~mask;
+	reg(ic->arg[0]) |= (x & mask);
+}
+Y(bfi)
+
+
+/*
+ *  swp, swpb:  Swap (word or byte).
+ *
+ *  arg[0] = ptr to rd
+ *  arg[1] = ptr to rm
+ *  arg[2] = ptr to rn
+ */
+X(swp)
+{
+	uint32_t addr = reg(ic->arg[2]), data, data2;
+	unsigned char d[4];
+
+	/*  Synchronize the program counter:  */
+	uint32_t low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, d, sizeof(d), MEM_READ,
+	    CACHE_DATA)) {
+		fatal("swp: load failed\n");
+		return;
+	}
+	data = d[0] + (d[1] << 8) + (d[2] << 16) + (d[3] << 24);
+	data2 = reg(ic->arg[1]);
+	d[0] = data2; d[1] = data2 >> 8; d[2] = data2 >> 16; d[3] = data2 >> 24;
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, d, sizeof(d), MEM_WRITE,
+	    CACHE_DATA)) {
+		fatal("swp: store failed\n");
+		return;
+	}
+	reg(ic->arg[0]) = data;
+}
+Y(swp)
+X(swpb)
+{
+	uint32_t addr = reg(ic->arg[2]), data;
+	unsigned char d[1];
+
+	/*  Synchronize the program counter:  */
+	uint32_t low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, d, sizeof(d), MEM_READ,
+	    CACHE_DATA)) {
+		fatal("swp: load failed\n");
+		return;
+	}
+	data = d[0];
+	d[0] = reg(ic->arg[1]);
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, d, sizeof(d), MEM_WRITE,
+	    CACHE_DATA)) {
+		fatal("swp: store failed\n");
+		return;
+	}
+	reg(ic->arg[0]) = data;
+}
+Y(swpb)
+
+
+extern void (*arm_load_store_instr[1024])(struct cpu *,
+	struct arm_instr_call *);
+X(store_w1_word_u1_p0_imm);
+X(store_w0_byte_u1_p0_imm);
+X(store_w0_word_u1_p0_imm);
+X(store_w0_word_u1_p1_imm);
+X(load_w0_word_u1_p0_imm);
+X(load_w0_word_u1_p1_imm);
+X(load_w1_word_u1_p0_imm);
+X(load_w0_byte_u1_p1_imm);
+X(load_w0_byte_u1_p1_reg);
+X(load_w1_byte_u1_p1_imm);
+
+extern void (*arm_load_store_instr_pc[1024])(struct cpu *,
+	struct arm_instr_call *);
+
+extern void (*arm_load_store_instr_3[2048])(struct cpu *,
+	struct arm_instr_call *);
+
+extern void (*arm_load_store_instr_3_pc[2048])(struct cpu *,
+	struct arm_instr_call *);
+
+extern uint32_t (*arm_r[8192])(struct cpu *, struct arm_instr_call *);
+extern uint32_t arm_r_r3_t0_c0(struct cpu *cpu, struct arm_instr_call *ic);
+
+extern void (*arm_dpi_instr[2 * 2 * 2 * 16 * 16])(struct cpu *,
+	struct arm_instr_call *);
+extern void (*arm_dpi_instr_regshort[2 * 16 * 16])(struct cpu *,
+	struct arm_instr_call *);
+X(cmps);
+X(teqs);
+X(tsts);
+X(sub);
+X(add);
+X(subs);
+X(eor_regshort);
+X(cmps_regshort);
+
+
+#include "cpu_arm_instr_misc.c"
+
+
+/*
+ *  Shared between regular ARM and the THUMB encoded 'pop'.
+ */
+void arm_pop(struct cpu* cpu, uint32_t* np, int p_bit, int u_bit, int s_bit, int w_bit, uint32_t iw)
+{
+	uint32_t addr = *np;
+	unsigned char data[4];
+	unsigned char *page;
+	int i, return_flag = 0;
+	uint32_t new_values[16];
+
+	if (s_bit) {
+		/*  Load to USR registers:  */
+		if ((cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32) {
+			fatal("[ bdt_load: s-bit: in usermode? ]\n");
+			s_bit = 0;
+		}
+		if (iw & 0x8000) {
+			s_bit = 0;
+			return_flag = 1;
+		}
+	}
+
+	for (i=(u_bit? 0 : 15); i>=0 && i<=15; i+=(u_bit? 1 : -1)) {
+		uint32_t value;
+
+		if (!((iw >> i) & 1)) {
+			/*  Skip register i:  */
+			continue;
+		}
+
+		if (p_bit) {
+			if (u_bit)
+				addr += sizeof(uint32_t);
+			else
+				addr -= sizeof(uint32_t);
+		}
+
+		page = cpu->cd.arm.host_load[addr >> 12];
+		if (page != NULL) {
+			uint32_t *p32 = (uint32_t *) page;
+			value = p32[(addr & 0xfff) >> 2];
+			/*  Change byte order of value if
+			    host and emulated endianness differ:  */
+#ifdef HOST_LITTLE_ENDIAN
+			if (cpu->byte_order == EMUL_BIG_ENDIAN)
+#else
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+#endif
+				value = ((value & 0xff) << 24) |
+				    ((value & 0xff00) << 8) |
+				    ((value & 0xff0000) >> 8) |
+				    ((value & 0xff000000) >> 24);
+		} else {
+			if (!cpu->memory_rw(cpu, cpu->mem, addr, data,
+			    sizeof(data), MEM_READ, CACHE_DATA)) {
+				/*  load failed  */
+				return;
+			}
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+				value = data[0] +
+				    (data[1] << 8) + (data[2] << 16)
+				    + (data[3] << 24);
+			} else {
+				value = data[3] +
+				    (data[2] << 8) + (data[1] << 16)
+				    + (data[0] << 24);
+			}
+		}
+
+		new_values[i] = value;
+
+		if (!p_bit) {
+			if (u_bit)
+				addr += sizeof(uint32_t);
+			else
+				addr -= sizeof(uint32_t);
+		}
+	}
+
+	for (i=(u_bit? 0 : 15); i>=0 && i<=15; i+=(u_bit? 1 : -1)) {
+		if (!((iw >> i) & 1)) {
+			/*  Skip register i:  */
+			continue;
+		}
+
+		if (!s_bit) {
+			cpu->cd.arm.r[i] = new_values[i];
+		} else {
+			switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
+			case ARM_MODE_USR32:
+			case ARM_MODE_SYS32:
+				cpu->cd.arm.r[i] = new_values[i];
+				break;
+			case ARM_MODE_FIQ32:
+				if (i >= 8 && i <= 14)
+					cpu->cd.arm.default_r8_r14[i-8] =
+					    new_values[i];
+				else
+					cpu->cd.arm.r[i] = new_values[i];
+				break;
+			case ARM_MODE_SVC32:
+			case ARM_MODE_ABT32:
+			case ARM_MODE_UND32:
+			case ARM_MODE_IRQ32:
+				if (i >= 13 && i <= 14)
+					cpu->cd.arm.default_r8_r14[i-8] =
+					    new_values[i];
+				else
+					cpu->cd.arm.r[i] = new_values[i];
+				break;
+			}
+		}
+	}
+
+	if (w_bit)
+		*np = addr;
+
+	if (return_flag) {
+		uint32_t new_cpsr;
+		int switch_register_banks;
+
+		switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
+		case ARM_MODE_FIQ32:
+			new_cpsr = cpu->cd.arm.spsr_fiq; break;
+		case ARM_MODE_ABT32:
+			new_cpsr = cpu->cd.arm.spsr_abt; break;
+		case ARM_MODE_UND32:
+			new_cpsr = cpu->cd.arm.spsr_und; break;
+		case ARM_MODE_IRQ32:
+			new_cpsr = cpu->cd.arm.spsr_irq; break;
+		case ARM_MODE_SVC32:
+			new_cpsr = cpu->cd.arm.spsr_svc; break;
+		default:fatal("bdt_load: unimplemented mode %i\n",
+			    cpu->cd.arm.cpsr & ARM_FLAG_MODE);
+			cpu->running = 0;
+			cpu->cd.arm.next_ic = &nothing_call;
+			return;
+		}
+
+		switch_register_banks = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) !=
+		    (new_cpsr & ARM_FLAG_MODE);
+
+		if (switch_register_banks)
+			arm_save_register_bank(cpu);
+
+		cpu->cd.arm.cpsr = new_cpsr;
+		cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28;
+
+		if (switch_register_banks)
+			arm_load_register_bank(cpu);
+	}
+
+	/*  NOTE: Special case: Loading the PC  */
+	if (iw & 0x8000) {
+		cpu->pc = cpu->cd.arm.r[ARM_PC] & 0xfffffffc;
+		if (cpu->machine->show_trace_tree)
+			cpu_functioncall_trace_return(cpu);
+		/*  TODO: There is no need to update the
+		    pointers if this is a return to the
+		    same page!  */
+		/*  Find the new physical page and update the
+		    translation pointers:  */
+		quick_pc_to_pointers_arm(cpu);
+	}
+}
+
+
+/*
+ *  Shared between regular ARM and the THUMB encoded 'push'.
+ */
+void arm_push(struct cpu* cpu, uint32_t* np, int p_bit, int u_bit, int s_bit, int w_bit, uint16_t regs)
+{
+	int i;
+	uint32_t value, addr = *np;
+	unsigned char data[4];
+	unsigned char *page;
+
+	for (i=(u_bit? 0 : 15); i>=0 && i<=15; i+=(u_bit? 1 : -1)) {
+		if (!((regs >> i) & 1)) {
+			/*  Skip register i:  */
+			continue;
+		}
+
+		value = cpu->cd.arm.r[i];
+
+		if (s_bit) {
+			switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
+			case ARM_MODE_FIQ32:
+				if (i >= 8 && i <= 14)
+					value = cpu->cd.arm.default_r8_r14[i-8];
+				break;
+			case ARM_MODE_ABT32:
+			case ARM_MODE_UND32:
+			case ARM_MODE_IRQ32:
+			case ARM_MODE_SVC32:
+				if (i >= 13 && i <= 14)
+					value = cpu->cd.arm.default_r8_r14[i-8];
+				break;
+			case ARM_MODE_USR32:
+			case ARM_MODE_SYS32:
+				break;
+			}
+		}
+
+		/*  NOTE/TODO: 8 vs 12 on some ARMs  */
+		if (i == ARM_PC)
+			value = cpu->pc + 12;
+
+		if (p_bit) {
+			if (u_bit)
+				addr += sizeof(uint32_t);
+			else
+				addr -= sizeof(uint32_t);
+		}
+
+		page = cpu->cd.arm.host_store[addr >> 12];
+		if (page != NULL) {
+			uint32_t *p32 = (uint32_t *) page;
+			/*  Change byte order of value if
+			    host and emulated endianness differ:  */
+#ifdef HOST_LITTLE_ENDIAN
+			if (cpu->byte_order == EMUL_BIG_ENDIAN)
+#else
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+#endif
+				value = ((value & 0xff) << 24) |
+				    ((value & 0xff00) << 8) |
+				    ((value & 0xff0000) >> 8) |
+				    ((value & 0xff000000) >> 24);
+			p32[(addr & 0xfff) >> 2] = value;
+		} else {
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+				data[0] = value;
+				data[1] = value >> 8;
+				data[2] = value >> 16;
+				data[3] = value >> 24;
+			} else {
+				data[0] = value >> 24;
+				data[1] = value >> 16;
+				data[2] = value >> 8;
+				data[3] = value;
+			}
+			if (!cpu->memory_rw(cpu, cpu->mem, addr, data,
+			    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+				/*  store failed  */
+				return;
+			}
+		}
+
+		if (!p_bit) {
+			if (u_bit)
+				addr += sizeof(uint32_t);
+			else
+				addr -= sizeof(uint32_t);
+		}
+	}
+
+	if (w_bit)
+		*np = addr;
+}
+
+
+/*
+ *  bdt_load:  Block Data Transfer, Load
+ *
+ *  arg[0] = pointer to uint32_t in host memory, pointing to the base register
+ *  arg[1] = 32-bit instruction word. Most bits are read from this.
+ */
+X(bdt_load)
+{
+	uint32_t *np = (uint32_t *)ic->arg[0];
+	uint32_t low_pc;
+	uint32_t iw = ic->arg[1];  /*  xxxx100P USWLnnnn llllllll llllllll  */
+	int p_bit = iw & 0x01000000;
+	int u_bit = iw & 0x00800000;
+	int s_bit = iw & 0x00400000;
+	int w_bit = iw & 0x00200000;
+
+#ifdef GATHER_BDT_STATISTICS
+	if (!s_bit)
+		update_bdt_statistics(iw);
+#endif
+
+	/*  Synchronize the program counter:  */
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+
+	arm_pop(cpu, np, p_bit, u_bit, s_bit, w_bit, (uint16_t)iw);
+}
+Y(bdt_load)
+
+
+/*
+ *  bdt_store:  Block Data Transfer, Store
+ *
+ *  arg[0] = pointer to uint32_t in host memory, pointing to the base register
+ *  arg[1] = 32-bit instruction word. Most bits are read from this.
+ */
+X(bdt_store)
+{
+	uint32_t *np = (uint32_t *)ic->arg[0];
+	uint32_t low_pc;
+	uint32_t iw = ic->arg[1];  /*  xxxx100P USWLnnnn llllllll llllllll  */
+	int p_bit = iw & 0x01000000;
+	int u_bit = iw & 0x00800000;
+	int s_bit = iw & 0x00400000;
+	int w_bit = iw & 0x00200000;
+
+#ifdef GATHER_BDT_STATISTICS
+	if (!s_bit)
+		update_bdt_statistics(iw);
+#endif
+
+	/*  Synchronize the program counter:  */
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+
+	arm_push(cpu, np, p_bit, u_bit, s_bit, w_bit, (uint16_t)iw);
+}
+Y(bdt_store)
+
+
+/*
+ *  Load Register Exclusive (ARM "load linked"):
+ *
+ *  A Load Register Exclusive instruction initiates a RMW (read-modify-write)
+ *  sequence.
+ *
+ *  A Store Register Exclusive instruction ends the sequence.
+ *
+ *  arg[0] = ptr to rt
+ *  arg[1] = ptr to rn
+ *  arg[2] = int32_t imm offset
+ */
+X(ldrex)
+{
+	uint32_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
+	int low_pc;
+	uint8_t word[sizeof(uint32_t)];
+
+	/*  Synchronize the program counter:  */
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+
+	if (addr & (sizeof(word)-1)) {
+		fatal("TODO: ldrex unaligned access: exception\n");
+		cpu->running = 0;
+		cpu->cd.arm.next_ic = &nothing_call;
+		return;
+	}
+
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, word,
+	    sizeof(word), MEM_READ, CACHE_DATA)) {
+		/*  An exception occurred.  */
+		return;
+	}
+
+	cpu->cd.arm.rmw = 1;
+	cpu->cd.arm.rmw_addr = addr;
+	cpu->cd.arm.rmw_len = sizeof(word);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		reg(ic->arg[0]) = word[0] + (word[1] << 8)
+		    + (word[2] << 16) + (word[3] << 24);
+	else
+		reg(ic->arg[0]) = word[3] + (word[2] << 8)
+		    + (word[1] << 16) + (word[0] << 24);
+}
+Y(ldrex)
+/*
+ *  Store Register Exclusive
+ *
+ *  arg[0] = ptr to rd
+ *  arg[1] = ptr to rn
+ *  arg[2] = ptr to rt
+ */
+X(strex)
+{
+	uint32_t addr = reg(ic->arg[1]);
+	uint64_t r = reg(ic->arg[2]);
+	int low_pc, i;
+	uint8_t word[sizeof(uint32_t)];
+	
+	/*  Synchronize the program counter:  */
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+
+	if (addr & (sizeof(word)-1)) {
+		fatal("TODO: strex unaligned access: exception\n");
+		cpu->running = 0;
+		cpu->cd.arm.next_ic = &nothing_call;
+		return;
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		word[0]=r; word[1]=r>>8; word[2]=r>>16; word[3]=r>>24;
+	} else {
+		word[3]=r; word[2]=r>>8; word[1]=r>>16; word[0]=r>>24;
+	}
+
+	/*  If rmw is 0, then the store failed.  (This cache-line was written
+	    to by someone else.)  */
+	if (cpu->cd.arm.rmw == 0 || cpu->cd.arm.rmw_addr != addr
+	    || cpu->cd.arm.rmw_len != sizeof(word)) {
+		reg(ic->arg[0]) = 1;	// 1 = fail.
+		cpu->cd.arm.rmw = 0;
+		return;
+	}
+
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, word,
+	    sizeof(word), MEM_WRITE, CACHE_DATA)) {
+		/*  An exception occurred.  */
+		return;
+	}
+
+	/*  We succeeded. Let's invalidate everybody else's store to this
+	    cache line:  */
+	for (i=0; i<cpu->machine->ncpus; i++) {
+		if (cpu->machine->cpus[i]->cd.arm.rmw) {
+			uint64_t yaddr = addr, xaddr = cpu->machine->cpus[i]->
+			    cd.arm.rmw_addr;
+
+			/*  8-2048 bytes, implementation dependent :-(  */			
+			/*  https://stackoverflow.com/questions/11383125/do-the-arm-instructions-ldrex-strex-have-to-operate-on-cache-aligned-data  */
+			uint64_t mask = 2047;
+
+			xaddr &= mask;
+			yaddr &= mask;
+			if (xaddr == yaddr)
+				cpu->machine->cpus[i]->cd.arm.rmw = 0;
+		}
+	}
+
+	reg(ic->arg[0]) = 0;	// 0 = success
+	cpu->cd.arm.rmw = 0;
+}
+Y(strex)
+
+
+/*  Various load/store multiple instructions:  */
+extern uint32_t *multi_opcode[256];
+extern void (**multi_opcode_f[256])(struct cpu *, struct arm_instr_call *);
+X(multi_0x08b15018);
+X(multi_0x08ac000c__ge);
+X(multi_0x08a05018);
+
+
+/*****************************************************************************/
+
+
+/*
+ *  netbsd_memset:
+ *
+ *  The core of a NetBSD/arm memset.
+ *
+ *  f01bc420:  e25XX080     subs    rX,rX,#0x80
+ *  f01bc424:  a8ac000c     stmgeia ip!,{r2,r3}   (16 of these)
+ *  ..
+ *  f01bc464:  caffffed     bgt     0xf01bc420      <memset+0x38>
+ */
+X(netbsd_memset)
+{
+	unsigned char *page;
+	uint32_t addr;
+
+	do {
+		addr = cpu->cd.arm.r[ARM_IP];
+
+		instr(subs)(cpu, ic);
+
+		if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
+		    ((cpu->cd.arm.flags & ARM_F_V)?1:0)) {
+			cpu->n_translated_instrs += 16;
+			/*  Skip the store multiples:  */
+			cpu->cd.arm.next_ic = &ic[17];
+			return;
+		}
+
+		/*  Crossing a page boundary? Then continue non-combined.  */
+		if ((addr & 0xfff) + 128 > 0x1000)
+			return;
+
+		/*  R2/R3 non-zero? Not allowed here.  */
+		if (cpu->cd.arm.r[2] != 0 || cpu->cd.arm.r[3] != 0)
+			return;
+
+		/*  printf("addr = 0x%08x\n", addr);  */
+
+		page = cpu->cd.arm.host_store[addr >> 12];
+		/*  No page translation? Continue non-combined.  */
+		if (page == NULL)
+			return;
+
+		/*  Clear:  */
+		memset(page + (addr & 0xfff), 0, 128);
+		cpu->cd.arm.r[ARM_IP] = addr + 128;
+		cpu->n_translated_instrs += 16;
+
+		/*  Branch back if greater:  */
+		cpu->n_translated_instrs += 1;
+	} while (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
+	    ((cpu->cd.arm.flags & ARM_F_V)?1:0) &&
+	    !(cpu->cd.arm.flags & ARM_F_Z));
+
+	/*  Continue at the instruction after the bgt:  */
+	cpu->cd.arm.next_ic = &ic[18];
+}
+
+
+/*
+ *  netbsd_memcpy:
+ *
+ *  The core of a NetBSD/arm memcpy.
+ *
+ *  f01bc530:  e8b15018     ldmia   r1!,{r3,r4,ip,lr}
+ *  f01bc534:  e8a05018     stmia   r0!,{r3,r4,ip,lr}
+ *  f01bc538:  e8b15018     ldmia   r1!,{r3,r4,ip,lr}
+ *  f01bc53c:  e8a05018     stmia   r0!,{r3,r4,ip,lr}
+ *  f01bc540:  e2522020     subs    r2,r2,#0x20
+ *  f01bc544:  aafffff9     bge     0xf01bc530
+ */
+X(netbsd_memcpy)
+{
+	unsigned char *page_0, *page_1;
+	uint32_t addr_r0, addr_r1;
+
+	do {
+		addr_r0 = cpu->cd.arm.r[0];
+		addr_r1 = cpu->cd.arm.r[1];
+
+		/*  printf("addr_r0 = %08x  r1 = %08x\n", addr_r0, addr_r1);  */
+
+		/*  Crossing a page boundary? Then continue non-combined.  */
+		if ((addr_r0 & 0xfff) + 32 > 0x1000 ||
+		    (addr_r1 & 0xfff) + 32 > 0x1000) {
+			instr(multi_0x08b15018)(cpu, ic);
+			return;
+		}
+
+		page_0 = cpu->cd.arm.host_store[addr_r0 >> 12];
+		page_1 = cpu->cd.arm.host_store[addr_r1 >> 12];
+
+		/*  No page translations? Continue non-combined.  */
+		if (page_0 == NULL || page_1 == NULL) {
+			instr(multi_0x08b15018)(cpu, ic);
+			return;
+		}
+
+		memcpy(page_0 + (addr_r0 & 0xfff),
+		    page_1 + (addr_r1 & 0xfff), 32);
+		cpu->cd.arm.r[0] = addr_r0 + 32;
+		cpu->cd.arm.r[1] = addr_r1 + 32;
+
+		cpu->n_translated_instrs += 4;
+
+		instr(subs)(cpu, ic + 4);
+		cpu->n_translated_instrs ++;
+
+		/*  Loop while greater or equal:  */
+		cpu->n_translated_instrs ++;
+	} while (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
+	    ((cpu->cd.arm.flags & ARM_F_V)?1:0));
+
+	/*  Continue at the instruction after the bge:  */
+	cpu->cd.arm.next_ic = &ic[6];
+	cpu->n_translated_instrs --;
+}
+
+
+/*
+ *  netbsd_cacheclean:
+ *
+ *  The core of a NetBSD/arm cache clean routine, variant 1:
+ *
+ *  f015f88c:  e4902020     ldr     r2,[r0],#32
+ *  f015f890:  e2511020     subs    r1,r1,#0x20
+ *  f015f894:  1afffffc     bne     0xf015f88c
+ *  f015f898:  ee070f9a     mcr     15,0,r0,cr7,cr10,4
+ */
+X(netbsd_cacheclean)
+{
+	uint32_t r1 = cpu->cd.arm.r[1];
+	cpu->n_translated_instrs += ((r1 >> 5) * 3);
+	cpu->cd.arm.r[0] += r1;
+	cpu->cd.arm.r[1] = 0;
+	cpu->cd.arm.next_ic = &ic[4];
+}
+
+
+/*
+ *  netbsd_cacheclean2:
+ *
+ *  The core of a NetBSD/arm cache clean routine, variant 2:
+ *
+ *  f015f93c:  ee070f3a     mcr     15,0,r0,cr7,cr10,1
+ *  f015f940:  ee070f36     mcr     15,0,r0,cr7,cr6,1
+ *  f015f944:  e2800020     add     r0,r0,#0x20
+ *  f015f948:  e2511020     subs    r1,r1,#0x20
+ *  f015f94c:  8afffffa     bhi     0xf015f93c
+ */
+X(netbsd_cacheclean2)
+{
+	cpu->n_translated_instrs += ((cpu->cd.arm.r[1] >> 5) * 5) - 1;
+	cpu->cd.arm.next_ic = &ic[5];
+}
+
+
+/*
+ *  netbsd_scanc:
+ *
+ *  f01bccbc:  e5d13000     ldrb    r3,[r1]
+ *  f01bccc0:  e7d23003     ldrb    r3,[r2,r3]
+ *  f01bccc4:  e113000c     tsts    r3,ip
+ */
+X(netbsd_scanc)
+{
+	unsigned char *page = cpu->cd.arm.host_load[cpu->cd.arm.r[1] >> 12];
+	uint32_t t;
+
+	if (page == NULL) {
+		instr(load_w0_byte_u1_p1_imm)(cpu, ic);
+		return;
+	}
+
+	t = page[cpu->cd.arm.r[1] & 0xfff];
+	t += cpu->cd.arm.r[2];
+	page = cpu->cd.arm.host_load[t >> 12];
+
+	if (page == NULL) {
+		instr(load_w0_byte_u1_p1_imm)(cpu, ic);
+		return;
+	}
+
+	cpu->cd.arm.r[3] = page[t & 0xfff];
+
+	t = cpu->cd.arm.r[3] & cpu->cd.arm.r[ARM_IP];
+	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+	if (t == 0)
+		cpu->cd.arm.flags |= ARM_F_Z;
+
+	cpu->n_translated_instrs += 2;
+	cpu->cd.arm.next_ic = &ic[3];
+}
+
+
+/*
+ *  netbsd_idle:
+ *
+ *  L:	ldr     rX,[rY]
+ *	teqs    rX,#0
+ *	bne     X (samepage)
+ *	teqs    rZ,#0
+ *	beq     L (samepage)
+ *	....
+ *	X:  somewhere else on the same page
+ */
+X(netbsd_idle)
+{
+	uint32_t rY = reg(ic[0].arg[0]);
+	uint32_t rZ = reg(ic[3].arg[0]);
+	uint32_t *p;
+	uint32_t rX;
+
+	p = (uint32_t *) cpu->cd.arm.host_load[rY >> 12];
+	if (p == NULL) {
+		instr(load_w0_word_u1_p1_imm)(cpu, ic);
+		return;
+	}
+
+	rX = p[(rY & 0xfff) >> 2];
+	/*  No need to convert endianness, since it's only a 0-test.  */
+
+	/*  This makes execution continue on the first teqs instruction,
+	    which is fine.  */
+	if (rX != 0) {
+		instr(load_w0_word_u1_p1_imm)(cpu, ic);
+		return;
+	}
+
+	if (rZ == 0) {
+		/*  Synch the program counter.  */
+		uint32_t low_pc = ((size_t)ic - (size_t)
+		    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+		cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1)
+		    << ARM_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+
+		cpu->wants_to_idle = true;
+		cpu->n_translated_instrs += N_DYNTRANS_IDLE_BREAK;
+		cpu->cd.arm.next_ic = &nothing_call;
+		return;
+	}
+
+	cpu->cd.arm.next_ic = &ic[5];
+}
+
+
+/*
+ *  strlen:
+ *
+ *  S: e5f03001   ldrb  rY,[rX,#1]!
+ *     e3530000   cmps  rY,#0
+ *     1afffffc   bne   S
+ */
+X(strlen)
+{
+	unsigned int n_loops = 0;
+	uint32_t rY, rX = reg(ic[0].arg[0]);
+	unsigned char *p;
+
+	do {
+		rX ++;
+		p = cpu->cd.arm.host_load[rX >> 12];
+		if (p == NULL) {
+			cpu->n_translated_instrs += (n_loops * 3);
+			instr(load_w1_byte_u1_p1_imm)(cpu, ic);
+			return;
+		}
+
+		rY = reg(ic[0].arg[2]) = p[rX & 0xfff];	/*  load  */
+		reg(ic[0].arg[0]) = rX;			/*  writeback  */
+		n_loops ++;
+
+		/*  Compare rY to zero:  */
+		cpu->cd.arm.flags = ARM_F_C;
+		if (rY == 0)
+			cpu->cd.arm.flags |= ARM_F_Z;
+	} while (rY != 0);
+
+	cpu->n_translated_instrs += (n_loops * 3) - 1;
+	cpu->cd.arm.next_ic = &ic[3];
+}
+
+
+/*
+ *  xchg:
+ *
+ *  e02YX00X     eor     rX,rY,rX
+ *  e02XY00Y     eor     rY,rX,rY
+ *  e02YX00X     eor     rX,rY,rX
+ */
+X(xchg)
+{
+	uint32_t tmp = reg(ic[0].arg[0]);
+	cpu->n_translated_instrs += 2;
+	cpu->cd.arm.next_ic = &ic[3];
+	reg(ic[0].arg[0]) = reg(ic[1].arg[0]);
+	reg(ic[1].arg[0]) = tmp;
+}
+
+
+/*
+ *  netbsd_copyin:
+ *
+ *  e4b0a004     ldrt    sl,[r0],#4
+ *  e4b0b004     ldrt    fp,[r0],#4
+ *  e4b06004     ldrt    r6,[r0],#4
+ *  e4b07004     ldrt    r7,[r0],#4
+ *  e4b08004     ldrt    r8,[r0],#4
+ *  e4b09004     ldrt    r9,[r0],#4
+ */
+X(netbsd_copyin)
+{
+	uint32_t r0 = cpu->cd.arm.r[0], ofs = (r0 & 0xffc), index = r0 >> 12;
+	unsigned char *p = cpu->cd.arm.host_load[index];
+	uint32_t *p32 = (uint32_t *) p, *q32;
+	int ok = cpu->cd.arm.is_userpage[index >> 5] & (1 << (index & 31));
+
+	if (ofs > 0x1000 - 6*4 || !ok || p == NULL) {
+		instr(load_w1_word_u1_p0_imm)(cpu, ic);
+		return;
+	}
+	q32 = &cpu->cd.arm.r[6];
+	ofs >>= 2;
+	q32[0] = p32[ofs+2];
+	q32[1] = p32[ofs+3];
+	q32[2] = p32[ofs+4];
+	q32[3] = p32[ofs+5];
+	q32[4] = p32[ofs+0];
+	q32[5] = p32[ofs+1];
+	cpu->cd.arm.r[0] = r0 + 24;
+	cpu->n_translated_instrs += 5;
+	cpu->cd.arm.next_ic = &ic[6];
+}
+
+
+/*
+ *  netbsd_copyout:
+ *
+ *  e4a18004     strt    r8,[r1],#4
+ *  e4a19004     strt    r9,[r1],#4
+ *  e4a1a004     strt    sl,[r1],#4
+ *  e4a1b004     strt    fp,[r1],#4
+ *  e4a16004     strt    r6,[r1],#4
+ *  e4a17004     strt    r7,[r1],#4
+ */
+X(netbsd_copyout)
+{
+	uint32_t r1 = cpu->cd.arm.r[1], ofs = (r1 & 0xffc), index = r1 >> 12;
+	unsigned char *p = cpu->cd.arm.host_store[index];
+	uint32_t *p32 = (uint32_t *) p, *q32;
+	int ok = cpu->cd.arm.is_userpage[index >> 5] & (1 << (index & 31));
+
+	if (ofs > 0x1000 - 6*4 || !ok || p == NULL) {
+		instr(store_w1_word_u1_p0_imm)(cpu, ic);
+		return;
+	}
+	q32 = &cpu->cd.arm.r[6];
+	ofs >>= 2;
+	p32[ofs  ] = q32[2];
+	p32[ofs+1] = q32[3];
+	p32[ofs+2] = q32[4];
+	p32[ofs+3] = q32[5];
+	p32[ofs+4] = q32[0];
+	p32[ofs+5] = q32[1];
+	cpu->cd.arm.r[1] = r1 + 24;
+	cpu->n_translated_instrs += 5;
+	cpu->cd.arm.next_ic = &ic[6];
+}
+
+
+/*
+ *  cmps by 0, followed by beq (inside the same page):
+ */
+X(cmps0_beq_samepage)
+{
+	uint32_t a = reg(ic->arg[0]);
+	cpu->n_translated_instrs ++;
+	if (a == 0) {
+		cpu->cd.arm.flags = ARM_F_Z | ARM_F_C;
+	} else {
+		/*  Semi-ugly hack which sets the negative-bit if a < 0:  */
+		cpu->cd.arm.flags = ARM_F_C | ((a >> 28) & 8);
+	}
+	if (a == 0)
+		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
+	else
+		cpu->cd.arm.next_ic = &ic[2];
+}
+
+
+/*
+ *  cmps followed by beq (inside the same page):
+ */
+X(cmps_beq_samepage)
+{
+	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
+	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
+	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
+		cpu->cd.arm.flags |= ARM_F_V;
+	if (c == 0) {
+		cpu->cd.arm.flags |= ARM_F_Z;
+		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
+	} else {
+		cpu->cd.arm.next_ic = &ic[2];
+		if (c & 0x80000000)
+			cpu->cd.arm.flags |= ARM_F_N;
+	}
+}
+
+
+/*
+ *  cmps followed by beq (not the same page):
+ */
+X(cmps_0_beq)
+{
+	uint32_t a = reg(ic->arg[0]);
+	cpu->n_translated_instrs ++;
+	if (a == 0) {
+		cpu->cd.arm.flags = ARM_F_Z | ARM_F_C;
+		cpu->pc = (uint32_t)(((uint32_t)cpu->pc & 0xfffff000)
+		    + (int32_t)ic[1].arg[0]);
+		quick_pc_to_pointers_arm(cpu);
+	} else {
+		/*  Semi-ugly hack which sets the negative-bit if a < 0:  */
+		cpu->cd.arm.flags = ARM_F_C | ((a >> 28) & 8);
+		cpu->cd.arm.next_ic = &ic[2];
+	}
+}
+X(cmps_pos_beq)
+{
+	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
+	if ((int32_t)a < 0 && (int32_t)c >= 0)
+		cpu->cd.arm.flags |= ARM_F_V;
+	if (c == 0) {
+		cpu->cd.arm.flags |= ARM_F_Z;
+		cpu->pc = (uint32_t)(((uint32_t)cpu->pc & 0xfffff000)
+		    + (int32_t)ic[1].arg[0]);
+		quick_pc_to_pointers_arm(cpu);
+	} else {
+		cpu->cd.arm.next_ic = &ic[2];
+		if (c & 0x80000000)
+			cpu->cd.arm.flags |= ARM_F_N;
+	}
+}
+X(cmps_neg_beq)
+{
+	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
+	if ((int32_t)a >= 0 && (int32_t)c < 0)
+		cpu->cd.arm.flags |= ARM_F_V;
+	if (c == 0) {
+		cpu->cd.arm.flags |= ARM_F_Z;
+		cpu->pc = (uint32_t)(((uint32_t)cpu->pc & 0xfffff000)
+		    + (int32_t)ic[1].arg[0]);
+		quick_pc_to_pointers_arm(cpu);
+	} else {
+		cpu->cd.arm.next_ic = &ic[2];
+		if (c & 0x80000000)
+			cpu->cd.arm.flags |= ARM_F_N;
+	}
+}
+
+
+/*
+ *  cmps by 0, followed by bne (inside the same page):
+ */
+X(cmps0_bne_samepage)
+{
+	uint32_t a = reg(ic->arg[0]);
+	cpu->n_translated_instrs ++;
+	if (a == 0) {
+		cpu->cd.arm.flags = ARM_F_Z | ARM_F_C;
+	} else {
+		/*  Semi-ugly hack which sets the negative-bit if a < 0:  */
+		cpu->cd.arm.flags = ARM_F_C | ((a >> 28) & 8);
+	}
+	if (a == 0)
+		cpu->cd.arm.next_ic = &ic[2];
+	else
+		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
+}
+
+
+/*
+ *  cmps followed by bne (inside the same page):
+ */
+X(cmps_bne_samepage)
+{
+	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
+	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
+	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
+		cpu->cd.arm.flags |= ARM_F_V;
+	if (c == 0) {
+		cpu->cd.arm.flags |= ARM_F_Z;
+		cpu->cd.arm.next_ic = &ic[2];
+	} else {
+		if (c & 0x80000000)
+			cpu->cd.arm.flags |= ARM_F_N;
+		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
+	}
+}
+
+
+/*
+ *  cmps followed by bcc (inside the same page):
+ */
+X(cmps_bcc_samepage)
+{
+	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
+	if (c & 0x80000000)
+		cpu->cd.arm.flags |= ARM_F_N;
+	else if (c == 0)
+		cpu->cd.arm.flags |= ARM_F_Z;
+	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
+	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
+		cpu->cd.arm.flags |= ARM_F_V;
+	if (a >= b)
+		cpu->cd.arm.next_ic = &ic[2];
+	else
+		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
+}
+
+
+/*
+ *  cmps (reg) followed by bcc (inside the same page):
+ */
+X(cmps_reg_bcc_samepage)
+{
+	uint32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]), c = a - b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
+	if (c & 0x80000000)
+		cpu->cd.arm.flags |= ARM_F_N;
+	else if (c == 0)
+		cpu->cd.arm.flags |= ARM_F_Z;
+	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
+	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
+		cpu->cd.arm.flags |= ARM_F_V;
+	if (a >= b)
+		cpu->cd.arm.next_ic = &ic[2];
+	else
+		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
+}
+
+
+/*
+ *  cmps followed by bhi (inside the same page):
+ */
+X(cmps_bhi_samepage)
+{
+	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
+	if (c & 0x80000000)
+		cpu->cd.arm.flags |= ARM_F_N;
+	else if (c == 0)
+		cpu->cd.arm.flags |= ARM_F_Z;
+	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
+	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
+		cpu->cd.arm.flags |= ARM_F_V;
+	if (a > b)
+		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
+	else
+		cpu->cd.arm.next_ic = &ic[2];
+}
+
+
+/*
+ *  cmps (reg) followed by bhi (inside the same page):
+ */
+X(cmps_reg_bhi_samepage)
+{
+	uint32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]), c = a - b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
+	if (c & 0x80000000)
+		cpu->cd.arm.flags |= ARM_F_N;
+	else if (c == 0)
+		cpu->cd.arm.flags |= ARM_F_Z;
+	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
+	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
+		cpu->cd.arm.flags |= ARM_F_V;
+	if (a > b)
+		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
+	else
+		cpu->cd.arm.next_ic = &ic[2];
+}
+
+
+/*
+ *  cmps followed by bgt (inside the same page):
+ */
+X(cmps_bgt_samepage)
+{
+	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
+	if (c & 0x80000000)
+		cpu->cd.arm.flags |= ARM_F_N;
+	else if (c == 0)
+		cpu->cd.arm.flags |= ARM_F_Z;
+	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
+	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
+		cpu->cd.arm.flags |= ARM_F_V;
+	if ((int32_t)a > (int32_t)b)
+		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
+	else
+		cpu->cd.arm.next_ic = &ic[2];
+}
+
+
+/*
+ *  cmps followed by ble (inside the same page):
+ */
+X(cmps_ble_samepage)
+{
+	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
+	if (c & 0x80000000)
+		cpu->cd.arm.flags |= ARM_F_N;
+	else if (c == 0)
+		cpu->cd.arm.flags |= ARM_F_Z;
+	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
+	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
+		cpu->cd.arm.flags |= ARM_F_V;
+	if ((int32_t)a <= (int32_t)b)
+		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
+	else
+		cpu->cd.arm.next_ic = &ic[2];
+}
+
+
+/*
+ *  teqs followed by beq (inside the same page):
+ */
+X(teqs_beq_samepage)
+{
+	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a ^ b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+	if (c == 0) {
+		cpu->cd.arm.flags |= ARM_F_Z;
+		cpu->cd.arm.next_ic = (struct arm_instr_call *)
+		    ic[1].arg[0];
+	} else {
+		if (c & 0x80000000)
+			cpu->cd.arm.flags |= ARM_F_N;
+		cpu->cd.arm.next_ic = &ic[2];
+	}
+}
+
+
+/*
+ *  tsts followed by beq (inside the same page):
+ *  (arg[1] must not have its highest bit set))
+ */
+X(tsts_lo_beq_samepage)
+{
+	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a & b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+	if (c == 0)
+		cpu->cd.arm.flags |= ARM_F_Z;
+	if (c == 0)
+		cpu->cd.arm.next_ic = (struct arm_instr_call *)
+		    ic[1].arg[0];
+	else
+		cpu->cd.arm.next_ic = &ic[2];
+}
+
+
+/*
+ *  teqs followed by bne (inside the same page):
+ */
+X(teqs_bne_samepage)
+{
+	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a ^ b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+	if (c == 0) {
+		cpu->cd.arm.flags |= ARM_F_Z;
+	} else {
+		if (c & 0x80000000)
+			cpu->cd.arm.flags |= ARM_F_N;
+	}
+	if (c == 0)
+		cpu->cd.arm.next_ic = &ic[2];
+	else
+		cpu->cd.arm.next_ic = (struct arm_instr_call *)
+		    ic[1].arg[0];
+}
+
+
+/*
+ *  tsts followed by bne (inside the same page):
+ *  (arg[1] must not have its highest bit set))
+ */
+X(tsts_lo_bne_samepage)
+{
+	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a & b;
+	cpu->n_translated_instrs ++;
+	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
+	if (c == 0)
+		cpu->cd.arm.flags |= ARM_F_Z;
+	if (c == 0)
+		cpu->cd.arm.next_ic = &ic[2];
+	else
+		cpu->cd.arm.next_ic = (struct arm_instr_call *)
+		    ic[1].arg[0];
+}
+
+
+/*****************************************************************************/
+
+
+X(end_of_page)
+{
+	/*  Update the PC:  (offset 0, but on the next page)  */
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (ARM_IC_ENTRIES_PER_PAGE << ARM_INSTR_ALIGNMENT_SHIFT);
+
+	/*  Find the new physical page and update the translation pointers:  */
+	quick_pc_to_pointers_arm(cpu);
+
+	/*  end_of_page doesn't count as an executed instruction:  */
+	cpu->n_translated_instrs --;
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  Combine: netbsd_memset():
+ *
+ *  Check for the core of a NetBSD/arm memset; large memsets use a sequence
+ *  of 16 store-multiple instructions, each storing 2 registers at a time.
+ */
+void COMBINE(netbsd_memset)(struct cpu *cpu,
+	struct arm_instr_call *ic, int low_addr)
+{
+#ifdef HOST_LITTLE_ENDIAN
+	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
+	    & (ARM_IC_ENTRIES_PER_PAGE-1);
+
+	if (n_back >= 17) {
+		int i;
+		for (i=-16; i<=-1; i++)
+			if (ic[i].f != instr(multi_0x08ac000c__ge))
+				return;
+		if (ic[-17].f == instr(subs) &&
+		    ic[-17].arg[0]==ic[-17].arg[2] && ic[-17].arg[1] == 128 &&
+		    ic[ 0].f == instr(b_samepage__gt) &&
+		    ic[ 0].arg[0] == (size_t)&ic[-17]) {
+			ic[-17].f = instr(netbsd_memset);
+		}
+	}
+#endif
+}
+
+
+/*
+ *  Combine: netbsd_memcpy():
+ *
+ *  Check for the core of a NetBSD/arm memcpy; large memcpys use a
+ *  sequence of ldmia instructions.
+ */
+void COMBINE(netbsd_memcpy)(struct cpu *cpu, struct arm_instr_call *ic,
+	int low_addr)
+{
+#ifdef HOST_LITTLE_ENDIAN
+	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
+	    & (ARM_IC_ENTRIES_PER_PAGE-1);
+
+	if (n_back >= 5) {
+		if (ic[-5].f==instr(multi_0x08b15018) &&
+		    ic[-4].f==instr(multi_0x08a05018) &&
+		    ic[-3].f==instr(multi_0x08b15018) &&
+		    ic[-2].f==instr(multi_0x08a05018) &&
+		    ic[-1].f == instr(subs) &&
+		    ic[-1].arg[0]==ic[-1].arg[2] && ic[-1].arg[1] == 0x20 &&
+		    ic[ 0].f == instr(b_samepage__ge) &&
+		    ic[ 0].arg[0] == (size_t)&ic[-5]) {
+			ic[-5].f = instr(netbsd_memcpy);
+		}
+	}
+#endif
+}
+
+
+/*
+ *  Combine: netbsd_cacheclean():
+ *
+ *  Check for the core of a NetBSD/arm cache clean. (There are two variants.)
+ */
+void COMBINE(netbsd_cacheclean)(struct cpu *cpu,
+	struct arm_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
+	    & (ARM_IC_ENTRIES_PER_PAGE-1);
+
+	if (n_back >= 3) {
+		if (ic[-3].f==instr(load_w0_word_u1_p0_imm) &&
+		    ic[-2].f == instr(subs) &&
+		    ic[-2].arg[0]==ic[-2].arg[2] && ic[-2].arg[1] == 0x20 &&
+		    ic[-1].f == instr(b_samepage__ne) &&
+		    ic[-1].arg[0] == (size_t)&ic[-3]) {
+			ic[-3].f = instr(netbsd_cacheclean);
+		}
+	}
+}
+
+
+/*
+ *  Combine: netbsd_cacheclean2():
+ *
+ *  Check for the core of a NetBSD/arm cache clean. (Second variant.)
+ */
+void COMBINE(netbsd_cacheclean2)(struct cpu *cpu,
+	struct arm_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
+	    & (ARM_IC_ENTRIES_PER_PAGE-1);
+
+	if (n_back >= 4) {
+		if (ic[-4].f == instr(mcr_mrc) && ic[-4].arg[0] == 0xee070f3a &&
+		    ic[-3].f == instr(mcr_mrc) && ic[-3].arg[0] == 0xee070f36 &&
+		    ic[-2].f == instr(add) &&
+		    ic[-2].arg[0]==ic[-2].arg[2] && ic[-2].arg[1] == 0x20 &&
+		    ic[-1].f == instr(subs) &&
+		    ic[-1].arg[0]==ic[-1].arg[2] && ic[-1].arg[1] == 0x20) {
+			ic[-4].f = instr(netbsd_cacheclean2);
+		}
+	}
+}
+
+
+/*
+ *  Combine: netbsd_scanc():
+ */
+void COMBINE(netbsd_scanc)(struct cpu *cpu,
+	struct arm_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
+	    & (ARM_IC_ENTRIES_PER_PAGE-1);
+
+	if (n_back < 2)
+		return;
+
+	if (ic[-2].f == instr(load_w0_byte_u1_p1_imm) &&
+	    ic[-2].arg[0] == (size_t)(&cpu->cd.arm.r[1]) &&
+	    ic[-2].arg[1] == 0 &&
+	    ic[-2].arg[2] == (size_t)(&cpu->cd.arm.r[3]) &&
+	    ic[-1].f == instr(load_w0_byte_u1_p1_reg) &&
+	    ic[-1].arg[0] == (size_t)(&cpu->cd.arm.r[2]) &&
+	    ic[-1].arg[1] == (size_t)arm_r_r3_t0_c0 &&
+	    ic[-1].arg[2] == (size_t)(&cpu->cd.arm.r[3])) {
+		ic[-2].f = instr(netbsd_scanc);
+	}
+}
+
+
+/*
+ *  Combine: strlen():
+ */
+void COMBINE(strlen)(struct cpu *cpu,
+	struct arm_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
+	    & (ARM_IC_ENTRIES_PER_PAGE-1);
+
+	if (n_back < 2)
+		return;
+
+	if (ic[-2].f == instr(load_w1_byte_u1_p1_imm) &&
+	    ic[-2].arg[1] == 1 &&
+	    ic[-2].arg[2] == (size_t)(&cpu->cd.arm.r[3]) &&
+	    ic[-1].f == instr(cmps) &&
+	    ic[-1].arg[0] == (size_t)(&cpu->cd.arm.r[3]) &&
+	    ic[-1].arg[1] == 0) {
+		ic[-2].f = instr(strlen);
+	}
+}
+
+
+/*
+ *  Combine: xchg():
+ */
+void COMBINE(xchg)(struct cpu *cpu,
+	struct arm_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
+	    & (ARM_IC_ENTRIES_PER_PAGE-1);
+	size_t a, b;
+
+	if (n_back < 2)
+		return;
+
+	a = ic[-2].arg[0]; b = ic[-1].arg[0];
+
+	if (ic[-2].f == instr(eor_regshort) &&
+	    ic[-1].f == instr(eor_regshort) &&
+	    ic[-2].arg[0] == a && ic[-2].arg[1] == b && ic[-2].arg[2] == b &&
+	    ic[-1].arg[0] == b && ic[-1].arg[1] == a && ic[-1].arg[2] == a &&
+	    ic[ 0].arg[0] == a && ic[ 0].arg[1] == b && ic[ 0].arg[2] == b) {
+		ic[-2].f = instr(xchg);
+	}
+}
+
+
+/*
+ *  Combine: netbsd_copyin():
+ */
+void COMBINE(netbsd_copyin)(struct cpu *cpu,
+	struct arm_instr_call *ic, int low_addr)
+{
+#ifdef HOST_LITTLE_ENDIAN
+	int i, n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
+	    & (ARM_IC_ENTRIES_PER_PAGE-1);
+
+	if (n_back < 5)
+		return;
+
+	for (i=-5; i<0; i++) {
+		if (ic[i].f != instr(load_w1_word_u1_p0_imm) ||
+		    ic[i].arg[0] != (size_t)(&cpu->cd.arm.r[0]) ||
+		    ic[i].arg[1] != 4)
+			return;
+	}
+
+	if (ic[-5].arg[2] == (size_t)(&cpu->cd.arm.r[10]) &&
+	    ic[-4].arg[2] == (size_t)(&cpu->cd.arm.r[11]) &&
+	    ic[-3].arg[2] == (size_t)(&cpu->cd.arm.r[6]) &&
+	    ic[-2].arg[2] == (size_t)(&cpu->cd.arm.r[7]) &&
+	    ic[-1].arg[2] == (size_t)(&cpu->cd.arm.r[8])) {
+		ic[-5].f = instr(netbsd_copyin);
+	}
+#endif
+}
+
+
+/*
+ *  Combine: netbsd_copyout():
+ */
+void COMBINE(netbsd_copyout)(struct cpu *cpu,
+	struct arm_instr_call *ic, int low_addr)
+{
+#ifdef HOST_LITTLE_ENDIAN
+	int i, n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
+	    & (ARM_IC_ENTRIES_PER_PAGE-1);
+
+	if (n_back < 5)
+		return;
+
+	for (i=-5; i<0; i++) {
+		if (ic[i].f != instr(store_w1_word_u1_p0_imm) ||
+		    ic[i].arg[0] != (size_t)(&cpu->cd.arm.r[1]) ||
+		    ic[i].arg[1] != 4)
+			return;
+	}
+
+	if (ic[-5].arg[2] == (size_t)(&cpu->cd.arm.r[8]) &&
+	    ic[-4].arg[2] == (size_t)(&cpu->cd.arm.r[9]) &&
+	    ic[-3].arg[2] == (size_t)(&cpu->cd.arm.r[10]) &&
+	    ic[-2].arg[2] == (size_t)(&cpu->cd.arm.r[11]) &&
+	    ic[-1].arg[2] == (size_t)(&cpu->cd.arm.r[6])) {
+		ic[-5].f = instr(netbsd_copyout);
+	}
+#endif
+}
+
+
+/*
+ *  Combine: cmps + beq, etc:
+ */
+void COMBINE(beq_etc)(struct cpu *cpu,
+	struct arm_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
+	    & (ARM_IC_ENTRIES_PER_PAGE-1);
+	if (n_back < 1)
+		return;
+	if (ic[0].f == instr(b__eq)) {
+		if (ic[-1].f == instr(cmps)) {
+			if (ic[-1].arg[1] == 0)
+				ic[-1].f = instr(cmps_0_beq);
+			else if (ic[-1].arg[1] & 0x80000000)
+				ic[-1].f = instr(cmps_neg_beq);
+			else
+				ic[-1].f = instr(cmps_pos_beq);
+		}
+		return;
+	}
+	if (ic[0].f == instr(b_samepage__eq)) {
+		if (ic[-1].f == instr(cmps)) {
+			if (ic[-1].arg[1] == 0)
+				ic[-1].f = instr(cmps0_beq_samepage);
+			else
+				ic[-1].f = instr(cmps_beq_samepage);
+		}
+		if (ic[-1].f == instr(tsts) &&
+		    !(ic[-1].arg[1] & 0x80000000)) {
+			ic[-1].f = instr(tsts_lo_beq_samepage);
+		}
+		if (n_back >= 4 &&
+		    ic[-4].f == instr(load_w0_word_u1_p1_imm) &&
+		    ic[-4].arg[0] != ic[-4].arg[2] &&
+		    ic[-4].arg[1] == 0 &&
+		    ic[-4].arg[2] == ic[-3].arg[0] &&
+		    /*  Note: The teqs+bne is already combined!  */
+		    ic[-3].f == instr(teqs_bne_samepage) &&
+		    ic[-3].arg[1] == 0 &&
+		    ic[-2].f == instr(b_samepage__ne) &&
+		    ic[-1].f == instr(teqs) &&
+		    ic[-1].arg[0] != ic[-4].arg[0] &&
+		    ic[-1].arg[1] == 0) {
+			ic[-4].f = instr(netbsd_idle);
+		}
+		if (ic[-1].f == instr(teqs)) {
+			ic[-1].f = instr(teqs_beq_samepage);
+		}
+		return;
+	}
+	if (ic[0].f == instr(b_samepage__ne)) {
+		if (ic[-1].f == instr(cmps)) {
+			if (ic[-1].arg[1] == 0)
+				ic[-1].f = instr(cmps0_bne_samepage);
+			else
+				ic[-1].f = instr(cmps_bne_samepage);
+		}
+		if (ic[-1].f == instr(tsts) &&
+		    !(ic[-1].arg[1] & 0x80000000)) {
+			ic[-1].f = instr(tsts_lo_bne_samepage);
+		}
+		if (ic[-1].f == instr(teqs)) {
+			ic[-1].f = instr(teqs_bne_samepage);
+		}
+		return;
+	}
+	if (ic[0].f == instr(b_samepage__cc)) {
+		if (ic[-1].f == instr(cmps)) {
+			ic[-1].f = instr(cmps_bcc_samepage);
+		}
+		if (ic[-1].f == instr(cmps_regshort)) {
+			ic[-1].f = instr(cmps_reg_bcc_samepage);
+		}
+		return;
+	}
+	if (ic[0].f == instr(b_samepage__hi)) {
+		if (ic[-1].f == instr(cmps)) {
+			ic[-1].f = instr(cmps_bhi_samepage);
+		}
+		if (ic[-1].f == instr(cmps_regshort)) {
+			ic[-1].f = instr(cmps_reg_bhi_samepage);
+		}
+		return;
+	}
+	if (ic[0].f == instr(b_samepage__gt)) {
+		if (ic[-1].f == instr(cmps)) {
+			ic[-1].f = instr(cmps_bgt_samepage);
+		}
+		return;
+	}
+	if (ic[0].f == instr(b_samepage__le)) {
+		if (ic[-1].f == instr(cmps)) {
+			ic[-1].f = instr(cmps_ble_samepage);
+		}
+		return;
+	}
+}
+
+
+/*****************************************************************************/
+
+
+static void arm_switch_clear(struct arm_instr_call *ic, int rd,
+	int condition_code)
+{
+	switch (rd) {
+	case  0: ic->f = cond_instr(clear_r0); break;
+	case  1: ic->f = cond_instr(clear_r1); break;
+	case  2: ic->f = cond_instr(clear_r2); break;
+	case  3: ic->f = cond_instr(clear_r3); break;
+	case  4: ic->f = cond_instr(clear_r4); break;
+	case  5: ic->f = cond_instr(clear_r5); break;
+	case  6: ic->f = cond_instr(clear_r6); break;
+	case  7: ic->f = cond_instr(clear_r7); break;
+	case  8: ic->f = cond_instr(clear_r8); break;
+	case  9: ic->f = cond_instr(clear_r9); break;
+	case 10: ic->f = cond_instr(clear_r10); break;
+	case 11: ic->f = cond_instr(clear_r11); break;
+	case 12: ic->f = cond_instr(clear_r12); break;
+	case 13: ic->f = cond_instr(clear_r13); break;
+	case 14: ic->f = cond_instr(clear_r14); break;
+	}
+}
+
+
+static void arm_switch_mov1(struct arm_instr_call *ic, int rd,
+	int condition_code)
+{
+	switch (rd) {
+	case  0: ic->f = cond_instr(mov1_r0); break;
+	case  1: ic->f = cond_instr(mov1_r1); break;
+	case  2: ic->f = cond_instr(mov1_r2); break;
+	case  3: ic->f = cond_instr(mov1_r3); break;
+	case  4: ic->f = cond_instr(mov1_r4); break;
+	case  5: ic->f = cond_instr(mov1_r5); break;
+	case  6: ic->f = cond_instr(mov1_r6); break;
+	case  7: ic->f = cond_instr(mov1_r7); break;
+	case  8: ic->f = cond_instr(mov1_r8); break;
+	case  9: ic->f = cond_instr(mov1_r9); break;
+	case 10: ic->f = cond_instr(mov1_r10); break;
+	case 11: ic->f = cond_instr(mov1_r11); break;
+	case 12: ic->f = cond_instr(mov1_r12); break;
+	case 13: ic->f = cond_instr(mov1_r13); break;
+	case 14: ic->f = cond_instr(mov1_r14); break;
+	}
+}
+
+
+static void arm_switch_add1(struct arm_instr_call *ic, int rd,
+	int condition_code)
+{
+	switch (rd) {
+	case  0: ic->f = cond_instr(add1_r0); break;
+	case  1: ic->f = cond_instr(add1_r1); break;
+	case  2: ic->f = cond_instr(add1_r2); break;
+	case  3: ic->f = cond_instr(add1_r3); break;
+	case  4: ic->f = cond_instr(add1_r4); break;
+	case  5: ic->f = cond_instr(add1_r5); break;
+	case  6: ic->f = cond_instr(add1_r6); break;
+	case  7: ic->f = cond_instr(add1_r7); break;
+	case  8: ic->f = cond_instr(add1_r8); break;
+	case  9: ic->f = cond_instr(add1_r9); break;
+	case 10: ic->f = cond_instr(add1_r10); break;
+	case 11: ic->f = cond_instr(add1_r11); break;
+	case 12: ic->f = cond_instr(add1_r12); break;
+	case 13: ic->f = cond_instr(add1_r13); break;
+	case 14: ic->f = cond_instr(add1_r14); break;
+	}
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  arm_instr_to_be_translated():
+ *
+ *  Translate an instruction word into an arm_instr_call. ic is filled in with
+ *  valid data for the translated instruction, or a "nothing" instruction if
+ *  there was a translation failure. The newly translated instruction is then
+ *  executed.
+ */
+X(to_be_translated)
+{
+	uint32_t addr, low_pc, iword, imm = 0;
+	unsigned char *page;
+	unsigned char ib[4];
+	int condition_code, main_opcode, secondary_opcode, s_bit, rn, rd, r8;
+	int p_bit, u_bit, w_bit, l_bit, regform, rm, any_pc_reg; // , c, t
+	void (*samepage_function)(struct cpu *, struct arm_instr_call *);
+
+	/*  Figure out the address of the instruction:  */
+	low_pc = ((size_t)ic - (size_t)cpu->cd.arm.cur_ic_page)
+	    / sizeof(struct arm_instr_call);
+	addr = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) <<
+	    ARM_INSTR_ALIGNMENT_SHIFT);
+	addr += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc = addr;
+	addr &= ~((1 << ARM_INSTR_ALIGNMENT_SHIFT) - 1);
+
+	/*  Read the instruction word from memory:  */
+	page = cpu->cd.arm.host_load[addr >> 12];
+
+	if (page != NULL) {
+		/*  fatal("TRANSLATION HIT! 0x%08x\n", addr);  */
+		memcpy(ib, page + (addr & 0xfff), sizeof(ib));
+	} else {
+		/*  fatal("TRANSLATION MISS! 0x%08x\n", addr);  */
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, &ib[0],
+		    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
+			fatal("to_be_translated(): "
+			    "read failed: TODO\n");
+			return;
+		}
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iword = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
+	else
+		iword = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);
+
+
+#define DYNTRANS_TO_BE_TRANSLATED_HEAD
+#include "cpu_dyntrans.c"
+#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD
+
+
+	/*  The idea of taking bits 27..24 was found here:
+	    http://armphetamine.sourceforge.net/oldinfo.html  */
+	condition_code = iword >> 28;
+	main_opcode = (iword >> 24) & 15;
+	secondary_opcode = (iword >> 21) & 15;
+	u_bit = iword & 0x00800000;
+	w_bit = iword & 0x00200000;
+	s_bit = l_bit = iword & 0x00100000;
+	rn    = (iword >> 16) & 15;
+	rd    = (iword >> 12) & 15;
+	r8    = (iword >> 8) & 15;
+	// c     = (iword >> 7) & 31;
+	// t     = (iword >> 4) & 7;
+	rm    = iword & 15;
+
+	/*
+	 *  Translate the instruction:
+	 */
+
+	if ((iword >> 28) == 0xf) {
+		/*  The "never" condition is nowadays used for special encodings.  */
+		if ((iword & 0xfc70f000) == 0xf450f000) {
+			/*  Preload:  TODO.  Treat as NOP for now.  */
+			ic->f = instr(nop);
+			goto okay;
+		}
+
+		if (iword == 0xf10c0040) {
+			/*  cpsid f. Treat as NOP for now.  */
+			ic->f = instr(nop);
+			goto okay;
+		}
+
+		if (iword == 0xf10c0080) {
+			/*  cpsid i. Treat as NOP for now.  */
+			ic->f = instr(nop);
+			goto okay;
+		}
+
+		if (iword == 0xf57ff04f) {
+			/*  dsb sy. Treat as NOP for now.  */
+			ic->f = instr(nop);
+			goto okay;
+		}
+
+		if (iword == 0xf57ff05f) {
+			/*  dmb sy. Treat as NOP for now.  */
+			ic->f = instr(nop);
+			goto okay;
+		}
+
+		if (iword == 0xf57ff06f) {
+			/*  isb sy. Treat as NOP for now.  */
+			ic->f = instr(nop);
+			goto okay;
+		}
+
+		switch (main_opcode) {
+		case 0xa:
+		case 0xb:
+			ic->f = instr(blx_imm);
+
+			/*  arg 1 = offset of current instruction  */
+			ic->arg[1] = addr & 0xffc;
+
+			/*  arg 0 = relative jump distance + 1 (to enable THUMB)  */
+			ic->arg[0] = (iword & 0x00ffffff) << 2;
+			/*  Sign-extend:  */
+			if (ic->arg[0] & 0x02000000)
+				ic->arg[0] |= 0xfc000000;
+			if (main_opcode == 0xb)
+				ic->arg[0] += 2;
+			ic->arg[0] = (int32_t)(ic->arg[0] + 8 + 1);
+			break;
+		default:
+			goto bad;
+		}
+		goto okay;
+	}
+
+	switch (main_opcode) {
+
+	case 0x0:
+	case 0x1:
+	case 0x2:
+	case 0x3:
+		/*  Check special cases first:  */
+		if ((iword & 0x0ff00fff) == 0x01900f9f) {
+			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+			ic->arg[1] = (size_t)(&cpu->cd.arm.r[rn]);
+			ic->arg[2] = 0;
+
+			if (rd == ARM_PC || rn == ARM_PC) {
+				if (!cpu->translation_readahead)
+					fatal("ldrex with pc register: TODO\n");
+				goto bad;
+			}
+			
+			ic->f = cond_instr(ldrex);
+			break;
+		}
+
+		if ((iword & 0x0ff00ff0) == 0x01800f90) {
+			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+			ic->arg[1] = (size_t)(&cpu->cd.arm.r[rn]);
+			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rm]);
+
+			if (rd == ARM_PC || rm == ARM_PC || rn == ARM_PC ||
+			    rd == rm || rd == rn) {
+				if (!cpu->translation_readahead)
+					fatal("strex with bad register: TODO\n");
+				goto bad;
+			}
+			
+			ic->f = cond_instr(strex);
+			break;
+		}
+
+		if ((iword & 0x0ff000f0) == 0x00600090) {
+			ic->arg[0] = iword;
+			ic->f = cond_instr(mls);
+			break;
+		}
+		
+		if ((iword & 0x0fc000f0) == 0x00000090) {
+			/*
+			 *  Multiplication:
+			 *  xxxx0000 00ASdddd nnnnssss 1001mmmm (Rd,Rm,Rs[,Rn])
+			 */
+			if (iword & 0x00200000) {
+				if (s_bit)
+					ic->f = cond_instr(mlas);
+				else
+					ic->f = cond_instr(mla);
+				ic->arg[0] = iword;
+			} else {
+				if (s_bit)
+					ic->f = cond_instr(muls);
+				else
+					ic->f = cond_instr(mul);
+				/*  NOTE: rn means rd in this case:  */
+				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
+				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
+				ic->arg[2] = (size_t)(&cpu->cd.arm.r[r8]);
+			}
+			break;
+		}
+		if ((iword & 0x0f8000f0) == 0x00800090) {
+			/*  Long multiplication:  */
+			if (s_bit) {
+				if (!cpu->translation_readahead)
+					fatal("TODO: sbit mull\n");
+				goto bad;
+			}
+			ic->f = cond_instr(mull);
+			ic->arg[0] = iword;
+			break;
+		}
+		if ((iword & 0x0f900ff0) == 0x01000050) {
+			if (!cpu->translation_readahead)
+				fatal("TODO: q{,d}{add,sub}\n");
+			goto bad;
+		}
+		if ((iword & 0x0ff000d0) == 0x01200010) {
+			/*  bx or blx  */
+			if (iword & 0x20)
+				ic->f = cond_instr(blx_reg);
+			else {
+				if (cpu->machine->show_trace_tree &&
+				    rm == ARM_LR)
+					ic->f = cond_instr(bx_trace);
+				else
+					ic->f = cond_instr(bx);
+			}
+			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rm]);
+			ic->arg[2] = (addr & 0xffc) + 4;
+                        break;
+                }
+		if ((iword & 0x0fb00ff0) == 0x1000090) {
+			if (iword & 0x00400000)
+				ic->f = cond_instr(swpb);
+			else
+				ic->f = cond_instr(swp);
+			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+			ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
+			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rn]);
+			break;
+		}
+		if ((iword & 0x0fff0ff0) == 0x016f0f10) {
+			ic->f = cond_instr(clz);
+			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rm]);
+			ic->arg[1] = (size_t)(&cpu->cd.arm.r[rd]);
+			break;
+		}
+		if ((iword & 0x0ff00090) == 0x01000080) {
+			/*  TODO: smlaXX  */
+			goto bad;
+		}
+		if ((iword & 0x0ff00090) == 0x01400080) {
+			/*  TODO: smlalY  */
+			goto bad;
+		}
+		if ((iword & 0x0ff000b0) == 0x01200080) {
+			/*  TODO: smlawY  */
+			goto bad;
+		}
+		if ((iword & 0x0ff0f090) == 0x01600080) {
+			/*  smulXY (16-bit * 16-bit => 32-bit)  */
+			switch (iword & 0x60) {
+			case 0x00: ic->f = cond_instr(smulbb); break;
+			case 0x20: ic->f = cond_instr(smultb); break;
+			case 0x40: ic->f = cond_instr(smulbt); break;
+			default:   ic->f = cond_instr(smultt); break;
+			}
+			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rm]);
+			ic->arg[1] = (size_t)(&cpu->cd.arm.r[r8]);
+			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rn]); /*  Rd  */
+			break;
+		}
+		if ((iword & 0x0ff0f0b0) == 0x012000a0) {
+			/*  TODO: smulwY  */
+			goto bad;
+		}
+		if ((iword & 0x0fb0fff0) == 0x0120f000 ||
+		    (iword & 0x0fb0f000) == 0x0320f000) {
+			/*  msr: move to [S|C]PSR from a register or
+			    immediate value  */
+			if (iword & 0x02000000) {
+				if (iword & 0x00400000)
+					ic->f = cond_instr(msr_imm_spsr);
+				else
+					ic->f = cond_instr(msr_imm);
+			} else {
+				if (rm == ARM_PC) {
+					if (!cpu->translation_readahead)
+						fatal("msr PC?\n");
+					goto bad;
+				}
+				if (iword & 0x00400000)
+					ic->f = cond_instr(msr_spsr);
+				else
+					ic->f = cond_instr(msr);
+			}
+			imm = iword & 0xff;
+			while (r8-- > 0)
+				imm = (imm >> 2) | ((imm & 3) << 30);
+			ic->arg[0] = imm;
+			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rm]);
+			{
+				uint32_t arg1 = 0;
+				if (iword & (1<<16)) arg1 |= 0x000000ff;
+				if (iword & (1<<17)) arg1 |= 0x0000ff00;
+				if (iword & (1<<18)) arg1 |= 0x00ff0000;
+				if (iword & (1<<19)) arg1 |= 0xff000000;
+				ic->arg[1] = arg1;
+				if (arg1 == 0)
+					ic->f = instr(nop);
+			}
+			break;
+		}
+		if ((iword & 0x0fbf0fff) == 0x010f0000) {
+			/*  mrs: move from CPSR/SPSR to a register:  */
+			if (rd == ARM_PC) {
+				if (!cpu->translation_readahead)
+					fatal("mrs PC?\n");
+				goto bad;
+			}
+			if (iword & 0x00400000)
+				ic->f = cond_instr(mrs_spsr);
+			else
+				ic->f = cond_instr(mrs);
+			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+			break;
+		}
+		if ((iword & 0x0e000090) == 0x00000090) {
+			regform = !(iword & 0x00400000);
+			imm = ((iword >> 4) & 0xf0) | (iword & 0xf);
+			p_bit = main_opcode & 1;
+			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
+			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rd]);
+			if (rd == ARM_PC || rn == ARM_PC) {
+				ic->f = arm_load_store_instr_3_pc[
+				    condition_code + (l_bit? 16 : 0)
+				    + (iword & 0x40? 32 : 0)
+				    + (w_bit? 64 : 0)
+				    + (iword & 0x20? 128 : 0)
+				    + (u_bit? 256 : 0) + (p_bit? 512 : 0)
+				    + (regform? 1024 : 0)];
+				if (rn == ARM_PC)
+					ic->arg[0] = (size_t)
+					    (&cpu->cd.arm.tmp_pc);
+				if (!l_bit && rd == ARM_PC)
+					ic->arg[2] = (size_t)
+					    (&cpu->cd.arm.tmp_pc);
+			} else
+				ic->f = arm_load_store_instr_3[
+				    condition_code + (l_bit? 16 : 0)
+				    + (iword & 0x40? 32 : 0)
+				    + (w_bit? 64 : 0)
+				    + (iword & 0x20? 128 : 0)
+				    + (u_bit? 256 : 0) + (p_bit? 512 : 0)
+				    + (regform? 1024 : 0)];
+			if (regform)
+				ic->arg[1] = (size_t)(void *)arm_r[iword & 0xf];
+			else
+				ic->arg[1] = imm;
+			break;
+		}
+
+		if (iword & 0x80 && !(main_opcode & 2) && iword & 0x10) {
+			if (!cpu->translation_readahead)
+				fatal("reg form blah blah\n");
+			goto bad;
+		}
+
+		/*  "bkpt", ARMv5 and above  */
+		if ((iword & 0x0ff000f0) == 0x01200070) {
+			ic->f = cond_instr(bkpt);
+			ic->arg[0] = addr & 0xfff;
+			break;
+		}
+
+		/*  "mov pc,lr":  */
+		if ((iword & 0x0fffffff) == 0x01a0f00e) {
+			if (cpu->machine->show_trace_tree)
+				ic->f = cond_instr(ret_trace);
+			else
+				ic->f = cond_instr(ret);
+			break;
+		}
+
+		/*  "mov reg,reg" or "mov reg,pc":  */
+		if ((iword & 0x0fff0ff0) == 0x01a00000 && rd != ARM_PC) {
+			if (rm != ARM_PC) {
+				ic->f = cond_instr(mov_reg_reg);
+				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rm]);
+			} else {
+				ic->f = cond_instr(mov_reg_pc);
+				ic->arg[0] = (addr & 0xfff) + 8;
+			}
+			ic->arg[1] = (size_t)(&cpu->cd.arm.r[rd]);
+			break;
+		}
+
+		/*  "mov reg,#0":  */
+		if ((iword & 0x0fff0fff) == 0x03a00000 && rd != ARM_PC) {
+			arm_switch_clear(ic, rd, condition_code);
+			break;
+		}
+
+		/*  "mov reg,#1":  */
+		if ((iword & 0x0fff0fff) == 0x03a00001 && rd != ARM_PC) {
+			arm_switch_mov1(ic, rd, condition_code);
+			break;
+		}
+
+		/*  "add reg,reg,#1":  */
+		if ((iword & 0x0ff00fff) == 0x02800001 && rd != ARM_PC
+		    && rn == rd) {
+			arm_switch_add1(ic, rd, condition_code);
+			break;
+		}
+
+		if ((iword & 0x0ff00000) == 0x03000000) {
+			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
+			ic->arg[1] = (((iword & 0xf0000) >> 4) | (iword & 0xfff));
+			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rd]);
+			ic->f = cond_instr(movw);
+			if (rd == ARM_PC) {
+				if (!cpu->translation_readahead)
+					fatal("movw with rd = pc?\n");
+				goto bad;
+			}
+			break;
+		} else if ((iword & 0x0ff00000) == 0x03400000) {
+			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
+			ic->arg[1] = (((iword & 0xf0000) >> 4) | (iword & 0xfff)) << 16;
+			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rd]);
+			ic->f = cond_instr(movt);
+			if (rd == ARM_PC) {
+				if (!cpu->translation_readahead)
+					fatal("movt with rd = pc?\n");
+				goto bad;
+			}
+			break;
+		}
+
+		/*
+		 *  Generic Data Processing Instructions:
+		 */
+		if ((main_opcode & 2) == 0)
+			regform = 1;
+		else
+			regform = 0;
+
+		if (regform) {
+			/*  0x1000 signifies Carry bit update on rotation,
+			    which is not necessary for add,adc,sub,sbc,
+			    rsb,rsc,cmp, or cmn, because they update the
+			    Carry bit manually anyway.  */
+			int q = 0x1000;
+			if (s_bit == 0)
+				q = 0;
+			if ((secondary_opcode >= 2 && secondary_opcode <= 7)
+			    || secondary_opcode==0xa || secondary_opcode==0xb)
+				q = 0;
+			ic->arg[1] = (size_t)(void *)arm_r[(iword & 0xfff) + q];
+		} else {
+			int steps = r8;
+
+			imm = iword & 0xff;
+			
+			while (r8-- > 0)
+				imm = (imm >> 2) | ((imm & 3) << 30);
+
+			if (steps != 0 && (imm != 0 && imm < 256)) {
+				if (!cpu->translation_readahead)
+					fatal("TODO: see cpu_arm_instr_dpi; non-zero steps but still under 256 is not implemented yet\n");
+				goto bad;
+			}
+
+			ic->arg[1] = imm;
+		}
+
+		/*  mvn #imm ==> mov #~imm  */
+		if (secondary_opcode == 0xf && !regform) {
+			secondary_opcode = 0xd;
+			ic->arg[1] = ~ic->arg[1];
+		}
+
+		ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
+		ic->arg[2] = (size_t)(&cpu->cd.arm.r[rd]);
+		any_pc_reg = 0;
+		if (rn == ARM_PC || rd == ARM_PC)
+			any_pc_reg = 1;
+
+		if (!any_pc_reg && regform && (iword & 0xfff) < ARM_PC) {
+			ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
+			ic->f = arm_dpi_instr_regshort[condition_code +
+			    16 * secondary_opcode + (s_bit? 256 : 0)];
+		} else
+			ic->f = arm_dpi_instr[condition_code +
+			    16 * secondary_opcode + (s_bit? 256 : 0) +
+			    (any_pc_reg? 512 : 0) + (regform? 1024 : 0)];
+
+		if (ic->f == instr(eor_regshort))
+			cpu->cd.arm.combination_check = COMBINE(xchg);
+		if (iword == 0xe113000c)
+			cpu->cd.arm.combination_check = COMBINE(netbsd_scanc);
+		break;
+
+	case 0x4:	/*  Load and store...  */
+	case 0x5:	/*  xxxx010P UBWLnnnn ddddoooo oooooooo  Immediate  */
+	case 0x6:	/*  xxxx011P UBWLnnnn ddddcccc ctt0mmmm  Register  */
+	case 0x7:
+		// Special non-loadstore encodings:
+		if (main_opcode >= 6 && iword & 0x10) {
+			if ((iword & 0x0fff0ff0) == 0x06bf0f30) {
+				ic->f = cond_instr(rev);
+				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
+			} else if ((iword & 0x0fff03f0) == 0x06bf0070) {
+				ic->f = cond_instr(sxth);
+				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
+				ic->arg[2] = ((iword & 0xc00) >> 10) << 3;
+			} else if ((iword & 0x0fff03f0) == 0x06ef0070) {
+				ic->f = cond_instr(uxtb);
+				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
+				ic->arg[2] = ((iword & 0xc00) >> 10) << 3;
+			} else if ((iword & 0x0ff003f0) == 0x06e00070) {
+				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rn]);
+				ic->arg[2] = (size_t)(&cpu->cd.arm.r[rm]);
+				ic->f = cond_instr(uxtab);
+				if (iword & 0xc00) {
+					if (!cpu->translation_readahead)
+						fatal("unimplemented uxtab with rotate != 0\n");
+					goto bad;
+				}
+			} else if ((iword & 0x0fff03f0) == 0x06ff0070) {
+				ic->f = cond_instr(uxth);
+				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
+				ic->arg[2] = ((iword & 0xc00) >> 10) << 3;
+			} else if ((iword & 0x0ff003f0) == 0x06f00070) {
+				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rn]);
+				ic->arg[2] = (size_t)(&cpu->cd.arm.r[rm]);
+				ic->f = cond_instr(uxtah);
+				if (iword & 0xc00) {
+					if (!cpu->translation_readahead)
+						fatal("unimplemented uxtah with rotate != 0\n");
+					goto bad;
+				}
+			} else if ((iword & 0x0fe00070) == 0x07c00010) {
+				ic->f = cond_instr(bfi);
+				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
+				int lsb = (iword >> 7) & 31;
+				int msb = (iword >> 16) & 31;
+				ic->arg[2] = (msb << 16) + lsb;
+			} else if ((iword & 0x0fe00070) == 0x07e00050) {
+				ic->f = cond_instr(ubfx);
+				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
+				int lsb = (iword >> 7) & 31;
+				int width = 1 + ((iword >> 16) & 31);
+				ic->arg[2] = (width << 16) + lsb;
+			} else if ((iword & 0x0fe00070) == 0x07a00050) {
+				ic->f = cond_instr(sbfx);
+				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
+				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
+				int lsb = (iword >> 7) & 31;
+				int width = 1 + ((iword >> 16) & 31);
+				ic->arg[2] = (width << 16) + lsb;
+			} else {
+				if (!cpu->translation_readahead)
+					fatal("unimplemented special non-loadstore encoding!\n");
+				goto bad;
+			}
+			break;
+		}
+	
+		ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
+		ic->arg[2] = (size_t)(&cpu->cd.arm.r[rd]);
+		if (rd == ARM_PC || rn == ARM_PC) {
+			ic->f = arm_load_store_instr_pc[((iword >> 16)
+			    & 0x3f0) + condition_code];
+			if (rn == ARM_PC)
+				ic->arg[0] = (size_t)(&cpu->cd.arm.tmp_pc);
+			if (!l_bit && rd == ARM_PC)
+				ic->arg[2] = (size_t)(&cpu->cd.arm.tmp_pc);
+		} else {
+			ic->f = arm_load_store_instr[((iword >> 16) &
+			    0x3f0) + condition_code];
+		}
+		imm = iword & 0xfff;
+		if (main_opcode < 6)
+			ic->arg[1] = imm;
+		else
+			ic->arg[1] = (size_t)(void *)arm_r[iword & 0xfff];
+		if ((iword & 0x0e000010) == 0x06000010) {
+			/*  GDB uses this for breakpoints.  */
+			ic->f = cond_instr(und);
+			ic->arg[0] = addr & 0xfff;
+		}
+		/*  Special case: pc-relative load within the same page:  */
+		if (rn == ARM_PC && rd != ARM_PC && main_opcode < 6 && l_bit) {
+			unsigned char *p = page;
+			int ofs = (addr & 0xfff) + 8, max = 0xffc;
+			int b_bit = iword & 0x00400000;
+			if (b_bit)
+				max = 0xfff;
+			if (u_bit)
+				ofs += (iword & 0xfff);
+			else
+				ofs -= (iword & 0xfff);
+			/*  NOTE/TODO: This assumes 4KB pages,
+			    it will not work with 1KB pages.  */
+			if (ofs >= 0 && ofs <= max && p != NULL) {
+				unsigned char cbuf[4];
+				int len = b_bit? 1 : 4;
+				uint32_t x, a = (addr & 0xfffff000) | ofs;
+				/*  ic->f = cond_instr(mov);  */
+				ic->f = arm_dpi_instr[condition_code + 16*0xd];
+				ic->arg[2] = (size_t)(&cpu->cd.arm.r[rd]);
+
+				memcpy(cbuf, p + (a & 0xfff), len);
+
+				if (b_bit) {
+					x = cbuf[0];
+				} else {
+					if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+						x = cbuf[0] + (cbuf[1]<<8) +
+						    (cbuf[2]<<16) + (cbuf[3]<<24);
+					else
+						x = cbuf[3] + (cbuf[2]<<8) +
+						    (cbuf[1]<<16) + (cbuf[0]<<24);
+				}
+				
+				ic->arg[1] = x;
+			}
+		}
+		if (iword == 0xe4b09004)
+			cpu->cd.arm.combination_check = COMBINE(netbsd_copyin);
+		if (iword == 0xe4a17004)
+			cpu->cd.arm.combination_check = COMBINE(netbsd_copyout);
+		break;
+
+	case 0x8:	/*  Multiple load/store...  (Block data transfer)  */
+	case 0x9:	/*  xxxx100P USWLnnnn llllllll llllllll  */
+		ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
+		ic->arg[1] = (size_t)iword;
+		/*  Generic case:  */
+		if (l_bit)
+			ic->f = cond_instr(bdt_load);
+		else
+			ic->f = cond_instr(bdt_store);
+#if defined(HOST_LITTLE_ENDIAN) && !defined(GATHER_BDT_STATISTICS)
+		/*
+		 *  Check for availability of optimized implementation:
+		 *  xxxx100P USWLnnnn llllllll llllllll
+		 *           ^  ^ ^ ^        ^  ^ ^ ^   (0x00950154)
+		 *  These bits are used to select which list to scan, and then
+		 *  the list is scanned linearly.
+		 *
+		 *  The optimized functions do not support show_trace_tree,
+		 *  but it's ok to use the unoptimized version in that case.
+		 */
+		if (!cpu->machine->show_trace_tree) {
+			int i = 0, j = iword;
+			j = ((j & 0x00800000) >> 16) | ((j & 0x00100000) >> 14)
+			  | ((j & 0x00040000) >> 13) | ((j & 0x00010000) >> 12)
+			  | ((j & 0x00000100) >>  5) | ((j & 0x00000040) >>  4)
+			  | ((j & 0x00000010) >>  3) | ((j & 0x00000004) >>  2);
+			while (multi_opcode[j][i] != 0) {
+				if ((iword & 0x0fffffff) ==
+				    multi_opcode[j][i]) {
+					ic->f = multi_opcode_f[j]
+					    [i*16 + condition_code];
+					break;
+				}
+				i ++;
+			}
+		}
+#endif
+		if (rn == ARM_PC) {
+			if (!cpu->translation_readahead)
+				fatal("TODO: bdt with PC as base\n");
+			goto bad;
+		}
+		break;
+
+	case 0xa:					/*  B: branch  */
+	case 0xb:					/*  BL: branch+link  */
+		if (main_opcode == 0x0a) {
+			ic->f = cond_instr(b);
+			samepage_function = cond_instr(b_samepage);
+
+			/*  Abort read-ahead on unconditional branches:  */
+			if (condition_code == 0xe &&
+			    cpu->translation_readahead > 1)
+                                cpu->translation_readahead = 1;
+
+			if (iword == 0xcaffffed)
+				cpu->cd.arm.combination_check =
+				    COMBINE(netbsd_memset);
+			if (iword == 0xaafffff9)
+				cpu->cd.arm.combination_check =
+				    COMBINE(netbsd_memcpy);
+		} else {
+			if (cpu->machine->show_trace_tree) {
+				ic->f = cond_instr(bl_trace);
+				samepage_function =
+				    cond_instr(bl_samepage_trace);
+			} else {
+				ic->f = cond_instr(bl);
+				samepage_function = cond_instr(bl_samepage);
+			}
+		}
+
+		/*  arg 1 = offset of current instruction  */
+		/*  arg 2 = offset of the following instruction  */
+		ic->arg[1] = addr & 0xffc;
+		ic->arg[2] = (addr & 0xffc) + 4;
+
+		ic->arg[0] = (iword & 0x00ffffff) << 2;
+		/*  Sign-extend:  */
+		if (ic->arg[0] & 0x02000000)
+			ic->arg[0] |= 0xfc000000;
+		/*
+		 *  Branches are calculated as PC + 8 + offset.
+		 */
+		ic->arg[0] = (int32_t)(ic->arg[0] + 8);
+
+		/*
+		 *  Special case: branch within the same page:
+		 *
+		 *  arg[0] = addr of the arm_instr_call of the target
+		 *  arg[1] = addr of the next arm_instr_call.
+		 */
+		{
+			uint32_t mask_within_page =
+			    ((ARM_IC_ENTRIES_PER_PAGE-1) <<
+			    ARM_INSTR_ALIGNMENT_SHIFT) |
+			    ((1 << ARM_INSTR_ALIGNMENT_SHIFT) - 1);
+			uint32_t old_pc = addr;
+			uint32_t new_pc = old_pc + (int32_t)ic->arg[0];
+			if ((old_pc & ~mask_within_page) ==
+			    (new_pc & ~mask_within_page)) {
+				ic->f = samepage_function;
+				ic->arg[0] = (size_t) (
+				    cpu->cd.arm.cur_ic_page +
+				    ((new_pc & mask_within_page) >>
+				    ARM_INSTR_ALIGNMENT_SHIFT));
+				ic->arg[1] = (size_t) (
+				    cpu->cd.arm.cur_ic_page +
+				    (((addr & mask_within_page) + 4) >>
+				    ARM_INSTR_ALIGNMENT_SHIFT));
+			} else if (main_opcode == 0x0a) {
+				/*  Special hack for a plain "b":  */
+				ic->arg[0] += ic->arg[1];
+			}
+		}
+
+		if (main_opcode == 0xa && (condition_code <= 1
+		    || condition_code == 3 || condition_code == 8
+		    || condition_code == 12 || condition_code == 13))
+			cpu->cd.arm.combination_check = COMBINE(beq_etc);
+
+		if (iword == 0x1afffffc)
+			cpu->cd.arm.combination_check = COMBINE(strlen);
+
+		/*  Hm. Does this really increase performance?  */
+		if (iword == 0x8afffffa)
+			cpu->cd.arm.combination_check =
+			    COMBINE(netbsd_cacheclean2);
+		break;
+
+	case 0xc:
+	case 0xd:
+		/*
+		 *  xxxx1100 0100nnnn ddddcccc oooommmm    MCRR c,op,Rd,Rn,CRm
+		 *  xxxx1100 0101nnnn ddddcccc oooommmm    MRRC c,op,Rd,Rn,CRm
+		 */
+		if ((iword & 0x0fe00fff) == 0x0c400000) {
+			/*  Special case: mar/mra DSP instructions  */
+			if (!cpu->translation_readahead)
+				fatal("TODO: mar/mra DSP instructions!\n");
+			/*  Perhaps these are actually identical to MCRR/MRRC */
+			goto bad;
+		}
+
+		if ((iword & 0x0fe00000) == 0x0c400000) {
+			if (!cpu->translation_readahead)
+				fatal("MCRR/MRRC: TODO\n");
+			goto bad;
+		}
+
+		/*
+		 *  TODO: LDC/STC
+		 *
+		 *  For now, treat as Undefined instructions. This causes e.g.
+		 *  Linux/ARM to emulate these instructions (floating point).
+		 */
+#if 1
+		ic->f = cond_instr(und);
+		ic->arg[0] = addr & 0xfff;
+#else
+		if (!cpu->translation_readahead)
+			fatal("LDC/STC: TODO\n");
+		goto bad;
+#endif
+		break;
+
+	case 0xe:
+		if ((iword & 0x0ff00ff0) == 0x0e200010) {
+			/*  Special case: mia* DSP instructions  */
+			/*  See Intel's 27343601.pdf, page 16-20  */
+			if (!cpu->translation_readahead)
+				fatal("TODO: mia* DSP instructions!\n");
+			goto bad;
+		}
+		if (iword & 0x10) {
+			/*  xxxx1110 oooLNNNN ddddpppp qqq1MMMM  MCR/MRC  */
+			ic->arg[0] = iword;
+			ic->f = cond_instr(mcr_mrc);
+		} else {
+			/*  xxxx1110 oooonnnn ddddpppp qqq0mmmm  CDP  */
+			ic->arg[0] = iword;
+			ic->f = cond_instr(cdp);
+		}
+		if (iword == 0xee070f9a)
+			cpu->cd.arm.combination_check =
+			    COMBINE(netbsd_cacheclean);
+		break;
+
+	case 0xf:
+		/*  SWI:  */
+		/*  Default handler:  */
+		ic->f = cond_instr(swi);
+		ic->arg[0] = addr & 0xfff;
+		if (iword == 0xef8c64eb) {
+			/*  Hack for rebooting a machine:  */
+			ic->f = instr(reboot);
+		} else if (iword == 0xef8c64be) {
+			/*  Hack for openfirmware prom emulation:  */
+			ic->f = instr(openfirmware);
+		}
+		break;
+
+	default:goto bad;
+	}
+
+okay:
+
+#define	DYNTRANS_TO_BE_TRANSLATED_TAIL
+#include "cpu_dyntrans.c" 
+#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_arm_instr.cc gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr.cc
--- gxemul-0.6.2/src/cpus/cpu_arm_instr.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,3823 +0,0 @@
-/*
- *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  ARM instructions.
- *
- *  Individual functions should keep track of cpu->n_translated_instrs.
- *  (If no instruction was executed, then it should be decreased. If, say, 4
- *  instructions were combined into one function and executed, then it should
- *  be increased by 3.)
- *
- *  Note: cpu->pc is prefered over r[ARM_PC]. r[ARM_PC] is only used in a
- *        few places, and should always be kept in synch with the real
- *        program counter.
- */
-
-
-/*  #define GATHER_BDT_STATISTICS  */
-
-
-#ifdef GATHER_BDT_STATISTICS
-/*
- *  update_bdt_statistics():
- *
- *  Gathers statistics about load/store multiple instructions.
- *
- *  NOTE/TODO: Perhaps it would be more memory efficient to swap the high
- *  and low parts of the instruction word, so that the lllllll bits become
- *  the high bits; this would cause fewer host pages to be used. Anyway, the
- *  current implementation works on hosts with lots of RAM.
- *
- *  The resulting file, bdt_statistics.txt, should then be processed like
- *  this to give a new cpu_arm_multi.txt:
- *
- *  uniq -c bdt_statistics.txt|sort -nr|head -256|cut -f 2 > cpu_arm_multi.txt
- */
-static void update_bdt_statistics(uint32_t iw)
-{
-	static FILE *f = NULL;
-	static long long *counts;
-	static char *counts_used;
-	static long long n = 0;
-
-	if (f == NULL) {
-		size_t s = (1 << 24) * sizeof(long long);
-		f = fopen("bdt_statistics.txt", "w");
-		if (f == NULL) {
-			fprintf(stderr, "update_bdt_statistics(): :-(\n");
-			exit(1);
-		}
-		counts = zeroed_alloc(s);
-		counts_used = zeroed_alloc(65536);
-	}
-
-	/*  Drop the s-bit: xxxx100P USWLnnnn llllllll llllllll  */
-	iw = ((iw & 0x01800000) >> 1) | (iw & 0x003fffff);
-
-	counts_used[iw & 0xffff] = 1;
-	counts[iw] ++;
-
-	n ++;
-	if ((n % 500000) == 0) {
-		int i;
-		long long j;
-		fatal("[ update_bdt_statistics(): n = %lli ]\n", (long long) n);
-		fseek(f, 0, SEEK_SET);
-		for (i=0; i<0x1000000; i++)
-			if (counts_used[i & 0xffff] && counts[i] != 0) {
-				/*  Recreate the opcode:  */
-				uint32_t opcode = ((i & 0x00c00000) << 1)
-				    | (i & 0x003fffff) | 0x08000000;
-				for (j=0; j<counts[i]; j++)
-					fprintf(f, "0x%08x\n", opcode);
-			}
-		fflush(f);
-	}
-}
-#endif
-
-
-/*****************************************************************************/
-
-
-/*
- *  Helper definitions:
- *
- *  Each instruction is defined like this:
- *
- *	X(foo)
- *	{
- *		code for foo;
- *	}
- *	Y(foo)
- *
- *  The Y macro defines 14 copies of the instruction, one for each possible
- *  condition code. (The NV condition code is not included, and the AL code
- *  uses the main foo function.)  Y also defines an array with pointers to
- *  all of these functions.
- *
- *  If the compiler is good enough (i.e. allows long enough code sequences
- *  to be inlined), then the Y functions will be compiled as full (inlined)
- *  functions, otherwise they will simply call the X function.
- */
-
-uint8_t condition_hi[16] = { 0,0,1,1, 0,0,0,0, 0,0,1,1, 0,0,0,0 };
-uint8_t condition_ge[16] = { 1,0,1,0, 1,0,1,0, 0,1,0,1, 0,1,0,1 };
-uint8_t condition_gt[16] = { 1,0,1,0, 0,0,0,0, 0,1,0,1, 0,0,0,0 };
-
-#define Y(n) void arm_instr_ ## n ## __eq(struct cpu *cpu,		\
-			struct arm_instr_call *ic)			\
-	{  if (cpu->cd.arm.flags & ARM_F_Z)				\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __ne(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (!(cpu->cd.arm.flags & ARM_F_Z))				\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __cs(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (cpu->cd.arm.flags & ARM_F_C)				\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __cc(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (!(cpu->cd.arm.flags & ARM_F_C))				\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __mi(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (cpu->cd.arm.flags & ARM_F_N)				\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __pl(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (!(cpu->cd.arm.flags & ARM_F_N))				\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __vs(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (cpu->cd.arm.flags & ARM_F_V)				\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __vc(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (!(cpu->cd.arm.flags & ARM_F_V))				\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __hi(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (condition_hi[cpu->cd.arm.flags])				\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __ls(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (!condition_hi[cpu->cd.arm.flags])			\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __ge(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (condition_ge[cpu->cd.arm.flags])				\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __lt(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (!condition_ge[cpu->cd.arm.flags])			\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __gt(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (condition_gt[cpu->cd.arm.flags])				\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void arm_instr_ ## n ## __le(struct cpu *cpu,			\
-			struct arm_instr_call *ic)			\
-	{  if (!condition_gt[cpu->cd.arm.flags])			\
-		arm_instr_ ## n (cpu, ic);		}		\
-	void (*arm_cond_instr_ ## n  [16])(struct cpu *,		\
-			struct arm_instr_call *) = {			\
-		arm_instr_ ## n ## __eq, arm_instr_ ## n ## __ne,	\
-		arm_instr_ ## n ## __cs, arm_instr_ ## n ## __cc,	\
-		arm_instr_ ## n ## __mi, arm_instr_ ## n ## __pl,	\
-		arm_instr_ ## n ## __vs, arm_instr_ ## n ## __vc,	\
-		arm_instr_ ## n ## __hi, arm_instr_ ## n ## __ls,	\
-		arm_instr_ ## n ## __ge, arm_instr_ ## n ## __lt,	\
-		arm_instr_ ## n ## __gt, arm_instr_ ## n ## __le,	\
-		arm_instr_ ## n , arm_instr_never };
-
-#define cond_instr(n)	( arm_cond_instr_ ## n  [condition_code] )
-
-
-/*****************************************************************************/
-
-
-/*
- *  invalid:  Invalid instructions end up here.
- */
-X(invalid) {
-	uint32_t low_pc;
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1)
-	    << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-
-	fatal("FATAL ERROR: An internal error occured in the ARM"
-	    " dyntrans code. This could be due to an unimplemented instruction"
-	    " encoding. pc = 0x%08" PRIx32"\n",
-	    (uint32_t)cpu->pc);
-
-	cpu->cd.arm.next_ic = &nothing_call;
-}
-
-
-/*
- *  never:  So far unimplemented "never" instructions end up here.
- *  (Those are the ones using the "0xf" condition prefix.)
- */
-X(never) {
-	uint32_t low_pc;
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1)
-	    << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-
-	fatal("[ ARM: unimplemented 0xf instruction at pc = 0x%08" PRIx32" ]\n", (uint32_t)cpu->pc);
-
-	cpu->cd.arm.next_ic = &nothing_call;
-}
-
-
-/*
- *  nop:  Do nothing.
- */
-X(nop)
-{
-}
-
-
-/*
- *  b:  Branch (to a different translated page)
- *
- *  arg[0] = relative offset from start of page
- */
-X(b)
-{
-	cpu->pc = (uint32_t)((cpu->pc & 0xfffff000) + (int32_t)ic->arg[0]);
-
-	/*  Find the new physical page and update the translation pointers:  */
-	quick_pc_to_pointers_arm(cpu);
-}
-Y(b)
-
-
-/*
- *  b_samepage:  Branch (to within the same translated page)
- *
- *  arg[0] = pointer to new arm_instr_call
- *  arg[1] = pointer to the next instruction.
- *
- *  NOTE: This instruction is manually inlined.
- */
-X(b_samepage) {
-	cpu->cd.arm.next_ic = (struct arm_instr_call *) ic->arg[0];
-}
-X(b_samepage__eq) {
-	cpu->cd.arm.next_ic = (struct arm_instr_call *)
-	    ic->arg[cpu->cd.arm.flags & ARM_F_Z? 0 : 1];
-}
-X(b_samepage__ne) {
-	cpu->cd.arm.next_ic = (struct arm_instr_call *)
-	    ic->arg[cpu->cd.arm.flags & ARM_F_Z? 1 : 0];
-}
-X(b_samepage__cs) {
-	cpu->cd.arm.next_ic = (struct arm_instr_call *)
-	    ic->arg[cpu->cd.arm.flags & ARM_F_C? 0 : 1];
-}
-X(b_samepage__cc) {
-	cpu->cd.arm.next_ic = (struct arm_instr_call *)
-	    ic->arg[cpu->cd.arm.flags & ARM_F_C? 1 : 0];
-}
-X(b_samepage__mi) {
-	cpu->cd.arm.next_ic = (struct arm_instr_call *)
-	    ic->arg[cpu->cd.arm.flags & ARM_F_N? 0 : 1];
-}
-X(b_samepage__pl) {
-	cpu->cd.arm.next_ic = (struct arm_instr_call *)
-	    ic->arg[cpu->cd.arm.flags & ARM_F_N? 1 : 0];
-}
-X(b_samepage__vs) {
-	cpu->cd.arm.next_ic = (struct arm_instr_call *)
-	    ic->arg[cpu->cd.arm.flags & ARM_F_V? 0 : 1];
-}
-X(b_samepage__vc) {
-	cpu->cd.arm.next_ic = (struct arm_instr_call *)
-	    ic->arg[cpu->cd.arm.flags & ARM_F_V? 1 : 0];
-}
-X(b_samepage__hi) {
-	cpu->cd.arm.next_ic = (condition_hi[cpu->cd.arm.flags])?
-	    (struct arm_instr_call *) ic->arg[0] :
-	    (struct arm_instr_call *) ic->arg[1];
-}
-X(b_samepage__ls) {
-	cpu->cd.arm.next_ic = (struct arm_instr_call *)
-	    ic->arg[condition_hi[cpu->cd.arm.flags]];
-}
-X(b_samepage__ge) {
-	cpu->cd.arm.next_ic = (condition_ge[cpu->cd.arm.flags])?
-	    (struct arm_instr_call *) ic->arg[0] :
-	    (struct arm_instr_call *) ic->arg[1];
-}
-X(b_samepage__lt) {
-	cpu->cd.arm.next_ic = (struct arm_instr_call *)
-	    ic->arg[condition_ge[cpu->cd.arm.flags]];
-}
-X(b_samepage__gt) {
-	cpu->cd.arm.next_ic = (condition_gt[cpu->cd.arm.flags])?
-	    (struct arm_instr_call *) ic->arg[0] :
-	    (struct arm_instr_call *) ic->arg[1];
-}
-X(b_samepage__le) {
-	cpu->cd.arm.next_ic = (struct arm_instr_call *)
-	    ic->arg[condition_gt[cpu->cd.arm.flags]];
-}
-void (*arm_cond_instr_b_samepage[16])(struct cpu *,
-	struct arm_instr_call *) = {
-	arm_instr_b_samepage__eq, arm_instr_b_samepage__ne,
-	arm_instr_b_samepage__cs, arm_instr_b_samepage__cc,
-	arm_instr_b_samepage__mi, arm_instr_b_samepage__pl,
-	arm_instr_b_samepage__vs, arm_instr_b_samepage__vc,
-	arm_instr_b_samepage__hi, arm_instr_b_samepage__ls,
-	arm_instr_b_samepage__ge, arm_instr_b_samepage__lt,
-	arm_instr_b_samepage__gt, arm_instr_b_samepage__le,
-	arm_instr_b_samepage, arm_instr_nop };
-
-
-/*
- *  bx:  Branch, potentially exchanging Thumb/ARM encoding
- *
- *  arg[0] = ptr to rm
- */
-X(bx)
-{
-	uint32_t old_cpsr = cpu->cd.arm.cpsr;
-	cpu->pc = reg(ic->arg[0]);
-	if (cpu->pc & 1)
-		cpu->cd.arm.cpsr |= ARM_FLAG_T;
-	else
-		cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
-
-	if (cpu->cd.arm.cpsr != old_cpsr)
-		cpu->cd.arm.next_ic = &nothing_call;
-
-	if (cpu->pc & 2 && ((cpu->pc & 1) == 0)) {
-		fatal("[ ARM pc misaligned? 0x%08x ]\n", (int)cpu->pc);
-		cpu->running = 0;
-		cpu->n_translated_instrs --;
-		cpu->cd.arm.next_ic = &nothing_call;
-		return;
-	}
-
-	/*  Find the new physical page and update the translation pointers:  */
-	quick_pc_to_pointers_arm(cpu);
-}
-Y(bx)
-
-
-/*
- *  bx_trace:  As bx, but with trace enabled, arg[0] = the link register.
- *
- *  arg[0] = ignored
- */
-X(bx_trace)
-{
-	uint32_t old_cpsr = cpu->cd.arm.cpsr;
-	cpu->pc = cpu->cd.arm.r[ARM_LR];
-	if (cpu->pc & 1)
-		cpu->cd.arm.cpsr |= ARM_FLAG_T;
-	else
-		cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
-
-	if (cpu->cd.arm.cpsr != old_cpsr)
-		cpu->cd.arm.next_ic = &nothing_call;
-
-	if (cpu->pc & 2 && ((cpu->pc & 1) == 0)) {
-		fatal("[ ARM pc misaligned? 0x%08x ]\n", (int)cpu->pc);
-		cpu->running = 0;
-		cpu->n_translated_instrs --;
-		cpu->cd.arm.next_ic = &nothing_call;
-		return;
-	}
-
-	cpu_functioncall_trace_return(cpu);
-
-	/*  Find the new physical page and update the translation pointers:  */
-	quick_pc_to_pointers_arm(cpu);
-}
-Y(bx_trace)
-
-
-/*
- *  bl:  Branch and Link (to a different translated page)
- *
- *  arg[0] = relative address
- *  arg[1] = offset within current page to the instruction
- */
-X(bl)
-{
-	uint32_t pc = ((uint32_t)cpu->pc & 0xfffff000) + (int32_t)ic->arg[1];
-	cpu->cd.arm.r[ARM_LR] = pc + 4;
-
-	/*  Calculate new PC from this instruction + arg[0]  */
-	cpu->pc = pc + (int32_t)ic->arg[0];
-
-	/*  Find the new physical page and update the translation pointers:  */
-	quick_pc_to_pointers_arm(cpu);
-}
-Y(bl)
-
-
-/*
- *  blx_imm:  Branch and Link, always switching to THUMB encoding
- *
- *  arg[0] = relative address
- *  arg[1] = offset within current page to the current instruction
- */
-X(blx_imm)
-{
-	uint32_t pc = ((uint32_t)cpu->pc & 0xfffff000) + (int32_t)ic->arg[1];
-	uint32_t old_cpsr = cpu->cd.arm.cpsr;
-	cpu->cd.arm.r[ARM_LR] = pc + 4;
-
-	/*  Calculate new PC from this instruction + arg[0]  */
-	cpu->pc = pc + (int32_t)ic->arg[0];
-
-	if (cpu->pc & 1)
-		cpu->cd.arm.cpsr |= ARM_FLAG_T;
-	else {
-		fatal("[ blx_imm internal error. Should have switched to THUMB! 0x%08x ]\n", (int)cpu->pc);
-		cpu->running = 0;
-		cpu->n_translated_instrs --;
-		cpu->cd.arm.next_ic = &nothing_call;
-		return;
-	}
-
-	if (cpu->cd.arm.cpsr != old_cpsr)
-		cpu->cd.arm.next_ic = &nothing_call;
-
-	if (cpu->pc & 2 && ((cpu->pc & 1) == 0)) {
-		fatal("[ ARM pc misaligned? 0x%08x ]\n", (int)cpu->pc);
-		cpu->running = 0;
-		cpu->n_translated_instrs --;
-		cpu->cd.arm.next_ic = &nothing_call;
-		return;
-	}
-
-	if (cpu->machine->show_trace_tree)
-		cpu_functioncall_trace(cpu, cpu->pc);
-
-	/*  Find the new physical page and update the translation pointers:  */
-	quick_pc_to_pointers_arm(cpu);
-}
-
-
-/*
- *  blx_reg:  Branch and Link, potentially exchanging Thumb/ARM encoding
- *
- *  arg[0] = ptr to rm
- *  arg[2] = offset within current page to the instruction to return to
- */
-X(blx_reg)
-{
-	uint32_t lr = ((uint32_t)cpu->pc & 0xfffff000) + (int32_t)ic->arg[2];
-	cpu->cd.arm.r[ARM_LR] = lr;
-	cpu->pc = reg(ic->arg[0]);
-
-	uint32_t old_cpsr = cpu->cd.arm.cpsr;
-	if (cpu->pc & 1)
-		cpu->cd.arm.cpsr |= ARM_FLAG_T;
-	else
-		cpu->cd.arm.cpsr &= ~ARM_FLAG_T;
-
-	if (cpu->cd.arm.cpsr != old_cpsr)
-		cpu->cd.arm.next_ic = &nothing_call;
-
-	if (cpu->pc & 2 && ((cpu->pc & 1) == 0)) {
-		fatal("[ ARM pc misaligned? 0x%08x ]\n", (int)cpu->pc);
-		cpu->running = 0;
-		cpu->n_translated_instrs --;
-		cpu->cd.arm.next_ic = &nothing_call;
-		return;
-	}
-
-	/*  Find the new physical page and update the translation pointers:  */
-	quick_pc_to_pointers_arm(cpu);
-}
-Y(blx_reg)
-
-
-/*
- *  bl_trace:  Branch and Link (to a different translated page), with trace
- *
- *  Same as for bl.
- */
-X(bl_trace)
-{
-	uint32_t pc = ((uint32_t)cpu->pc & 0xfffff000) + (int32_t)ic->arg[1];
-	cpu->cd.arm.r[ARM_LR] = pc + 4;
-
-	/*  Calculate new PC from this instruction + arg[0]  */
-	cpu->pc = pc + (int32_t)ic->arg[0];
-
-	cpu_functioncall_trace(cpu, cpu->pc);
-
-	/*  Find the new physical page and update the translation pointers:  */
-	quick_pc_to_pointers_arm(cpu);
-}
-Y(bl_trace)
-
-
-/*
- *  bl_samepage:  A branch + link within the same page
- *
- *  arg[0] = pointer to new arm_instr_call
- */
-X(bl_samepage)
-{
-	cpu->cd.arm.r[ARM_LR] =
-	    ((uint32_t)cpu->pc & 0xfffff000) + (int32_t)ic->arg[2];
-	cpu->cd.arm.next_ic = (struct arm_instr_call *) ic->arg[0];
-}
-Y(bl_samepage)
-
-
-/*
- *  bl_samepage_trace:  Branch and Link (to the same page), with trace
- *
- *  Same as for bl_samepage.
- */
-X(bl_samepage_trace)
-{
-	uint32_t low_pc, lr = (cpu->pc & 0xfffff000) + ic->arg[2];
-
-	/*  Link and branch:  */
-	cpu->cd.arm.r[ARM_LR] = lr;
-	cpu->cd.arm.next_ic = (struct arm_instr_call *) ic->arg[0];
-
-	/*  Synchronize the program counter:  */
-	low_pc = ((size_t)cpu->cd.arm.next_ic - (size_t)
-	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1)
-	    << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-
-	/*  ... and show trace:  */
-	cpu_functioncall_trace(cpu, cpu->pc);
-}
-Y(bl_samepage_trace)
-
-
-/*
- *  clz: Count leading zeroes.
- *
- *  arg[0] = ptr to rm
- *  arg[1] = ptr to rd
- */
-X(clz)
-{
-	uint32_t rm = reg(ic->arg[0]);
-	int i = 32, n = 0, j;
-	while (i>0) {
-		if (rm & 0xff000000) {
-			for (j=0; j<8; j++) {
-				if (rm & 0x80000000)
-					break;
-				n ++;
-				rm <<= 1;
-			}
-			break;
-		} else {
-			rm <<= 8;
-			i -= 8;
-			n += 8;
-		}
-	}
-	reg(ic->arg[1]) = n;
-}
-Y(clz)
-
-
-/*
- *  mul: Multiplication
- *
- *  arg[0] = ptr to rd
- *  arg[1] = ptr to rm
- *  arg[2] = ptr to rs
- */
-X(mul)
-{
-	reg(ic->arg[0]) = reg(ic->arg[1]) * reg(ic->arg[2]);
-}
-Y(mul)
-X(muls)
-{
-	uint32_t result;
-	result = reg(ic->arg[1]) * reg(ic->arg[2]);
-	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-	if (result == 0)
-		cpu->cd.arm.flags |= ARM_F_Z;
-	if (result & 0x80000000)
-		cpu->cd.arm.flags |= ARM_F_N;
-	reg(ic->arg[0]) = result;
-}
-Y(muls)
-
-
-/*
- *  mla: Multiplication with addition
- *
- *  arg[0] = copy of instruction word
- */
-X(mla)
-{
-	/*  xxxx0000 00ASdddd nnnnssss 1001mmmm (Rd,Rm,Rs[,Rn])  */
-	uint32_t iw = ic->arg[0];
-	int rd, rs, rn, rm;
-	rd = (iw >> 16) & 15; rn = (iw >> 12) & 15,
-	rs = (iw >> 8) & 15;  rm = iw & 15;
-	cpu->cd.arm.r[rd] = cpu->cd.arm.r[rm] * cpu->cd.arm.r[rs]
-	    + cpu->cd.arm.r[rn];
-}
-Y(mla)
-X(mlas)
-{
-	/*  xxxx0000 00ASdddd nnnnssss 1001mmmm (Rd,Rm,Rs[,Rn])  */
-	uint32_t iw = ic->arg[0];
-	int rd, rs, rn, rm;
-	rd = (iw >> 16) & 15; rn = (iw >> 12) & 15,
-	rs = (iw >> 8) & 15;  rm = iw & 15;
-	cpu->cd.arm.r[rd] = cpu->cd.arm.r[rm] * cpu->cd.arm.r[rs]
-	    + cpu->cd.arm.r[rn];
-	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-	if (cpu->cd.arm.r[rd] == 0)
-		cpu->cd.arm.flags |= ARM_F_Z;
-	if (cpu->cd.arm.r[rd] & 0x80000000)
-		cpu->cd.arm.flags |= ARM_F_N;
-}
-Y(mlas)
-
-
-/*
- *  mla: Multiplication with subtraction
- *
- *  arg[0] = copy of instruction word
- */
-X(mls)
-{
-	/*  xxxx0000 0110dddd aaaammmm 1001nnnn  mls Rd,Rn,Rm,Ra  */
-	uint32_t iw = ic->arg[0];
-	int rd = (iw >> 16) & 15;
-	int rn = (iw >>  0) & 15;
-	int rm = (iw >>  8) & 15;
-	int ra = (iw >> 12) & 15;
-
-	cpu->cd.arm.r[rd] = cpu->cd.arm.r[ra] -
-	    cpu->cd.arm.r[rn] * cpu->cd.arm.r[rm];
-}
-Y(mls)
-
-
-/*
- *  mull: Long multiplication
- *
- *  arg[0] = copy of instruction word
- */
-X(mull)
-{
-	/*  xxxx0000 1UAShhhh llllssss 1001mmmm  */
-	uint32_t iw; uint64_t tmp; int u_bit, a_bit;
-	iw = ic->arg[0];
-	u_bit = iw & 0x00400000; a_bit = iw & 0x00200000;
-	tmp = cpu->cd.arm.r[iw & 15];
-	if (u_bit)
-		tmp = (int64_t)(int32_t)tmp
-		    * (int64_t)(int32_t)cpu->cd.arm.r[(iw >> 8) & 15];
-	else
-		tmp *= (uint64_t)cpu->cd.arm.r[(iw >> 8) & 15];
-	if (a_bit) {
-		uint64_t x = ((uint64_t)cpu->cd.arm.r[(iw >> 16) & 15] << 32)
-		    | cpu->cd.arm.r[(iw >> 12) & 15];
-		x += tmp;
-		cpu->cd.arm.r[(iw >> 16) & 15] = (x >> 32);
-		cpu->cd.arm.r[(iw >> 12) & 15] = x;
-	} else {
-		cpu->cd.arm.r[(iw >> 16) & 15] = (tmp >> 32);
-		cpu->cd.arm.r[(iw >> 12) & 15] = tmp;
-	}
-}
-Y(mull)
-
-
-/*
- *  smulXY:  16-bit * 16-bit multiplication (32-bit result)
- *
- *  arg[0] = ptr to rm
- *  arg[1] = ptr to rs
- *  arg[2] = ptr to rd
- */
-X(smulbb)
-{
-	reg(ic->arg[2]) = (int32_t)(int16_t)reg(ic->arg[0]) *
-	    (int32_t)(int16_t)reg(ic->arg[1]);
-}
-Y(smulbb)
-X(smultb)
-{
-	reg(ic->arg[2]) = (int32_t)(int16_t)(reg(ic->arg[0]) >> 16) *
-	    (int32_t)(int16_t)reg(ic->arg[1]);
-}
-Y(smultb)
-X(smulbt)
-{
-	reg(ic->arg[2]) = (int32_t)(int16_t)reg(ic->arg[0]) *
-	    (int32_t)(int16_t)(reg(ic->arg[1]) >> 16);
-}
-Y(smulbt)
-X(smultt)
-{
-	reg(ic->arg[2]) = (int32_t)(int16_t)(reg(ic->arg[0]) >> 16) *
-	    (int32_t)(int16_t)(reg(ic->arg[1]) >> 16);
-}
-Y(smultt)
-
-
-/*
- *  mov_reg_reg:  Move a register to another.
- *
- *  arg[0] = ptr to source register
- *  arg[1] = ptr to destination register
- */
-X(mov_reg_reg)
-{
-	reg(ic->arg[1]) = reg(ic->arg[0]);
-}
-Y(mov_reg_reg)
-
-
-/*
- *  mov_reg_pc:  Move the PC register to a normal register.
- *
- *  arg[0] = offset compared to start of current page + 8
- *  arg[1] = ptr to destination register
- */
-X(mov_reg_pc)
-{
-	reg(ic->arg[1]) = ((uint32_t)cpu->pc&0xfffff000) + (int32_t)ic->arg[0];
-}
-Y(mov_reg_pc)
-
-
-/*
- *  ret_trace:  "mov pc,lr" with trace enabled
- *  ret:  "mov pc,lr" without trace enabled
- *
- *  arg[0] = ignored
- */
-X(ret_trace)
-{
-	uint32_t old_pc, mask_within_page;
-	old_pc = cpu->pc;
-	mask_within_page = ((ARM_IC_ENTRIES_PER_PAGE-1)
-	    << ARM_INSTR_ALIGNMENT_SHIFT) |
-	    ((1 << ARM_INSTR_ALIGNMENT_SHIFT) - 1);
-
-	/*  Update the PC register:  */
-	cpu->pc = cpu->cd.arm.r[ARM_LR];
-
-	cpu_functioncall_trace_return(cpu);
-
-	/*
-	 *  Is this a return to code within the same page? Then there is no
-	 *  need to update all pointers, just next_ic.
-	 */
-	if ((old_pc & ~mask_within_page) == (cpu->pc & ~mask_within_page)) {
-		cpu->cd.arm.next_ic = cpu->cd.arm.cur_ic_page +
-		    ((cpu->pc & mask_within_page) >> ARM_INSTR_ALIGNMENT_SHIFT);
-	} else {
-		/*  Find the new physical page and update pointers:  */
-		quick_pc_to_pointers_arm(cpu);
-	}
-}
-Y(ret_trace)
-X(ret)
-{
-	cpu->pc = cpu->cd.arm.r[ARM_LR];
-	quick_pc_to_pointers_arm(cpu);
-}
-Y(ret)
-
-
-/*
- *  msr: Move to status register from a normal register or immediate value.
- *
- *  arg[0] = immediate value
- *  arg[1] = mask
- *  arg[2] = pointer to rm
- *
- *  msr_imm and msr_imm_spsr use arg[1] and arg[0].
- *  msr and msr_spsr use arg[1] and arg[2].
- */
-X(msr_imm)
-{
-	uint32_t mask = ic->arg[1];
-
-	if ((cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32) {
-		mask &= 0xff000000;
-	}
-
-	int switch_register_banks = (mask & ARM_FLAG_MODE) &&
-	    ((cpu->cd.arm.cpsr & ARM_FLAG_MODE) !=
-	    (ic->arg[0] & ARM_FLAG_MODE));
-	uint32_t new_value = ic->arg[0];
-
-	cpu->cd.arm.cpsr &= 0x0fffffff;
-	cpu->cd.arm.cpsr |= (cpu->cd.arm.flags << 28);
-
-	if (switch_register_banks)
-		arm_save_register_bank(cpu);
-
-	cpu->cd.arm.cpsr &= ~mask;
-	cpu->cd.arm.cpsr |= (new_value & mask);
-
-	cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28;
-
-	if (switch_register_banks)
-		arm_load_register_bank(cpu);
-}
-Y(msr_imm)
-X(msr)
-{
-	ic->arg[0] = reg(ic->arg[2]);
-	instr(msr_imm)(cpu, ic);
-}
-Y(msr)
-X(msr_imm_spsr)
-{
-	uint32_t mask = ic->arg[1];
-	uint32_t new_value = ic->arg[0];
-	switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
-	case ARM_MODE_FIQ32:
-		cpu->cd.arm.spsr_fiq &= ~mask;
-		cpu->cd.arm.spsr_fiq |= (new_value & mask);
-		break;
-	case ARM_MODE_ABT32:
-		cpu->cd.arm.spsr_abt &= ~mask;
-		cpu->cd.arm.spsr_abt |= (new_value & mask);
-		break;
-	case ARM_MODE_UND32:
-		cpu->cd.arm.spsr_und &= ~mask;
-		cpu->cd.arm.spsr_und |= (new_value & mask);
-		break;
-	case ARM_MODE_IRQ32:
-		cpu->cd.arm.spsr_irq &= ~mask;
-		cpu->cd.arm.spsr_irq |= (new_value & mask);
-		break;
-	case ARM_MODE_SVC32:
-		cpu->cd.arm.spsr_svc &= ~mask;
-		cpu->cd.arm.spsr_svc |= (new_value & mask);
-		break;
-	default:fatal("msr_spsr: unimplemented mode %i\n",
-		    cpu->cd.arm.cpsr & ARM_FLAG_MODE);
-		{
-			/*  Synchronize the program counter:  */
-			uint32_t old_pc, low_pc = ((size_t)ic - (size_t)
-			    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-			cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-			old_pc = cpu->pc;
-			printf("msr_spsr: old pc = 0x%08" PRIx32"\n", old_pc);
-		}
-		exit(1);
-	}
-}
-Y(msr_imm_spsr)
-X(msr_spsr)
-{
-	ic->arg[0] = reg(ic->arg[2]);
-	instr(msr_imm_spsr)(cpu, ic);
-}
-Y(msr_spsr)
-
-
-/*
- *  mrs: Move from status/flag register to a normal register.
- *
- *  arg[0] = pointer to rd
- */
-X(mrs)
-{
-	cpu->cd.arm.cpsr &= 0x0fffffff;
-	cpu->cd.arm.cpsr |= (cpu->cd.arm.flags << 28);
-	reg(ic->arg[0]) = cpu->cd.arm.cpsr;
-}
-Y(mrs)
-
-
-/*
- *  mrs: Move from saved status/flag register to a normal register.
- *
- *  arg[0] = pointer to rd
- */
-X(mrs_spsr)
-{
-	switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
-	case ARM_MODE_FIQ32: reg(ic->arg[0]) = cpu->cd.arm.spsr_fiq; break;
-	case ARM_MODE_ABT32: reg(ic->arg[0]) = cpu->cd.arm.spsr_abt; break;
-	case ARM_MODE_UND32: reg(ic->arg[0]) = cpu->cd.arm.spsr_und; break;
-	case ARM_MODE_IRQ32: reg(ic->arg[0]) = cpu->cd.arm.spsr_irq; break;
-	case ARM_MODE_SVC32: reg(ic->arg[0]) = cpu->cd.arm.spsr_svc; break;
-	case ARM_MODE_USR32:
-	case ARM_MODE_SYS32: reg(ic->arg[0]) = 0; break;
-	default:fatal("mrs_spsr: unimplemented mode %i\n",
-		    cpu->cd.arm.cpsr & ARM_FLAG_MODE);
-		exit(1);
-	}
-}
-Y(mrs_spsr)
-
-
-/*
- *  mcr_mrc:  Coprocessor move
- *  cdp:      Coprocessor operation
- *
- *  arg[0] = copy of the instruction word
- */
-X(mcr_mrc) {
-	uint32_t low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-	arm_mcr_mrc(cpu, ic->arg[0]);
-}
-Y(mcr_mrc)
-X(cdp) {
-	uint32_t low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-	arm_cdp(cpu, ic->arg[0]);
-}
-Y(cdp)
-
-
-/*
- *  openfirmware:
- */
-X(openfirmware)
-{
-	/*  TODO: sync pc?  */
-	of_emul(cpu);
-	cpu->pc = cpu->cd.arm.r[ARM_LR];
-	if (cpu->machine->show_trace_tree)
-		cpu_functioncall_trace_return(cpu);
-	quick_pc_to_pointers_arm(cpu);
-}
-
-
-/*
- *  reboot:
- */
-X(reboot)
-{
-	cpu->running = 0;
-	cpu->n_translated_instrs --;
-	cpu->cd.arm.next_ic = &nothing_call;
-}
-
-
-/*
- *  swi:  Software interrupt.
- */
-X(swi)
-{
-	/*  Synchronize the program counter first:  */
-	cpu->pc &= 0xfffff000;
-	cpu->pc += ic->arg[0];
-	arm_exception(cpu, ARM_EXCEPTION_SWI);
-}
-Y(swi)
-
-
-/*
- * bkpt:  Breakpoint instruction.
- */
-X(bkpt)
-{
-	/*  Synchronize the program counter first:  */
-	cpu->pc &= 0xfffff000;
-	cpu->pc += ic->arg[0];
-	arm_exception(cpu, ARM_EXCEPTION_PREF_ABT);
-}
-Y(bkpt)
-
-
-/*
- *  und:  Undefined instruction.
- */
-X(und)
-{
-	/*  Synchronize the program counter first:  */
-	cpu->pc &= 0xfffff000;
-	cpu->pc += ic->arg[0];
-	arm_exception(cpu, ARM_EXCEPTION_UND);
-}
-Y(und)
-
-
-/*
- *  movt:  Move Top.
- *
- *  arg[1] = 32-bit immediate value. Top 16 bits are those of interest.
- *  arg[2] = ptr to rd
- */
-X(movt)
-{
-	reg(ic->arg[2]) &= 0xffff;
-	reg(ic->arg[2]) |= ic->arg[1];
-}
-Y(movt)
-
-
-/*
- *  movw:  Move (Word).
- *
- *  arg[1] = 32-bit immediate value.
- *  arg[2] = ptr to rd
- */
-X(movw)
-{
-	reg(ic->arg[2]) = ic->arg[1];
-}
-Y(movw)
-
-
-/*
- *  rev:  Reverse endian.
- *
- *  arg[0] = ptr to rd
- *  arg[1] = ptr to rm
- */
-X(rev)
-{
-	uint32_t v = reg(ic->arg[1]);
-
-	reg(ic->arg[0]) = (v >> 24) | ((v & 0x00ff0000) >> 8)
-		| ((v & 0x0000ff00) << 8) | ((v & 0xff) << 24);
-}
-Y(rev)
-
-
-/*
- *  uxtb:  Unsigned Extend Byte.
- *
- *  arg[0] = ptr to rd
- *  arg[1] = ptr to rm
- *  arg[2] = rotation amount (shift works too)
- */
-X(uxtb)
-{
-	uint32_t x = reg(ic->arg[1]);
-	reg(ic->arg[0]) = (uint8_t)(x >> ic->arg[2]);
-}
-Y(uxtb)
-
-
-/*
- *  sxth:  Signed Extend Halfword.
- *
- *  TODO: Could be optimized so that the rotation amount is "inlined".
- *
- *  arg[0] = ptr to rd
- *  arg[1] = ptr to rm
- *  arg[2] = rotation amount
- */
-X(sxth)
-{
-	uint32_t x = reg(ic->arg[1]);
-
-	switch (ic->arg[2]) {
-	case 0:	break;
-	case 8: x >>= 8; break;
-	case 16: x >>= 16; break;
-	case 24: x = (x >> 24) | ((x & 255) << 8); break;
-	}
-
-	int16_t rotated = x;
-	reg(ic->arg[0]) = (int32_t)rotated;
-}
-Y(sxth)
-
-
-/*
- *  uxth:  Unsigned Extend Halfword.
- *
- *  TODO: Could be optimized so that the rotation amount is "inlined".
- *
- *  arg[0] = ptr to rd
- *  arg[1] = ptr to rm
- *  arg[2] = rotation amount
- */
-X(uxth)
-{
-	uint32_t x = reg(ic->arg[1]);
-
-	switch (ic->arg[2]) {
-	case 0:	break;
-	case 8: x >>= 8; break;
-	case 16: x >>= 16; break;
-	case 24: x = (x >> 24) | ((x & 255) << 8); break;
-	}
-
-	uint16_t rotated = x;
-	reg(ic->arg[0]) = (uint32_t)rotated;
-}
-Y(uxth)
-
-
-/*
- *  uxtah:  Unsigned Extend and Add Byte.
- *
- *  arg[0] = ptr to rd
- *  arg[1] = ptr to rn
- *  arg[2] = ptr to rm
- */
-X(uxtab)
-{
-	reg(ic->arg[0]) = reg(ic->arg[1]) + (uint8_t)reg(ic->arg[2]);
-}
-Y(uxtab)
-
-
-/*
- *  uxtah:  Unsigned Extend and Add Halfword.
- *
- *  arg[0] = ptr to rd
- *  arg[1] = ptr to rn
- *  arg[2] = ptr to rm
- */
-X(uxtah)
-{
-	reg(ic->arg[0]) = reg(ic->arg[1]) + (uint16_t)reg(ic->arg[2]);
-}
-Y(uxtah)
-
-
-/*
- *  ubfx:  Unsigned Bit-Field Extract.
- *
- *  arg[0] = ptr to rd
- *  arg[1] = ptr to rn
- *  arg[2] = (width << 16) + lsb
- */
-X(ubfx)
-{
-	uint32_t x = reg(ic->arg[1]);
-
-	int lsb = (uint8_t)ic->arg[2];
-	int width = ic->arg[2] >> 16;
-
-	uint32_t mask = (1 << width) - 1;
-
-	x >>= lsb;
-	x &= mask;
-
-	reg(ic->arg[0]) = x;
-}
-Y(ubfx)
-
-
-/*
- *  sbfx:  Signed Bit-Field Extract.
- *
- *  arg[0] = ptr to rd
- *  arg[1] = ptr to rn
- *  arg[2] = (width << 16) + lsb
- */
-X(sbfx)
-{
-	uint32_t x = reg(ic->arg[1]);
-
-	int lsb = (uint8_t)ic->arg[2];
-	int width = ic->arg[2] >> 16;
-
-	uint32_t mask = (1 << width) - 1;
-	x >>= lsb;
-	x &= mask;
-
-	uint32_t topBitMask = 1 << (width-1);
-	if (x & topBitMask && width < 32)
-		x |= ~mask;
-
-	reg(ic->arg[0]) = x;
-}
-Y(sbfx)
-
-
-/*
- *  bfi:  Bit-Field Insert.
- *
- *  arg[0] = ptr to rd
- *  arg[1] = ptr to rn
- *  arg[2] = (msb << 16) + lsb
- */
-X(bfi)
-{
-	uint32_t x = reg(ic->arg[1]);
-
-	int lsb = (uint8_t)ic->arg[2];
-	int msb = ic->arg[2] >> 16;
-	int width = msb - lsb + 1;
-
-	x <<= lsb;
-
-	uint32_t mask = (1 << width) - 1;
-
-	mask <<= lsb;
-
-	reg(ic->arg[0]) &= ~mask;
-	reg(ic->arg[0]) |= (x & mask);
-}
-Y(bfi)
-
-
-/*
- *  swp, swpb:  Swap (word or byte).
- *
- *  arg[0] = ptr to rd
- *  arg[1] = ptr to rm
- *  arg[2] = ptr to rn
- */
-X(swp)
-{
-	uint32_t addr = reg(ic->arg[2]), data, data2;
-	unsigned char d[4];
-
-	/*  Synchronize the program counter:  */
-	uint32_t low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, d, sizeof(d), MEM_READ,
-	    CACHE_DATA)) {
-		fatal("swp: load failed\n");
-		return;
-	}
-	data = d[0] + (d[1] << 8) + (d[2] << 16) + (d[3] << 24);
-	data2 = reg(ic->arg[1]);
-	d[0] = data2; d[1] = data2 >> 8; d[2] = data2 >> 16; d[3] = data2 >> 24;
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, d, sizeof(d), MEM_WRITE,
-	    CACHE_DATA)) {
-		fatal("swp: store failed\n");
-		return;
-	}
-	reg(ic->arg[0]) = data;
-}
-Y(swp)
-X(swpb)
-{
-	uint32_t addr = reg(ic->arg[2]), data;
-	unsigned char d[1];
-
-	/*  Synchronize the program counter:  */
-	uint32_t low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, d, sizeof(d), MEM_READ,
-	    CACHE_DATA)) {
-		fatal("swp: load failed\n");
-		return;
-	}
-	data = d[0];
-	d[0] = reg(ic->arg[1]);
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, d, sizeof(d), MEM_WRITE,
-	    CACHE_DATA)) {
-		fatal("swp: store failed\n");
-		return;
-	}
-	reg(ic->arg[0]) = data;
-}
-Y(swpb)
-
-
-extern void (*arm_load_store_instr[1024])(struct cpu *,
-	struct arm_instr_call *);
-X(store_w1_word_u1_p0_imm);
-X(store_w0_byte_u1_p0_imm);
-X(store_w0_word_u1_p0_imm);
-X(store_w0_word_u1_p1_imm);
-X(load_w0_word_u1_p0_imm);
-X(load_w0_word_u1_p1_imm);
-X(load_w1_word_u1_p0_imm);
-X(load_w0_byte_u1_p1_imm);
-X(load_w0_byte_u1_p1_reg);
-X(load_w1_byte_u1_p1_imm);
-
-extern void (*arm_load_store_instr_pc[1024])(struct cpu *,
-	struct arm_instr_call *);
-
-extern void (*arm_load_store_instr_3[2048])(struct cpu *,
-	struct arm_instr_call *);
-
-extern void (*arm_load_store_instr_3_pc[2048])(struct cpu *,
-	struct arm_instr_call *);
-
-extern uint32_t (*arm_r[8192])(struct cpu *, struct arm_instr_call *);
-extern uint32_t arm_r_r3_t0_c0(struct cpu *cpu, struct arm_instr_call *ic);
-
-extern void (*arm_dpi_instr[2 * 2 * 2 * 16 * 16])(struct cpu *,
-	struct arm_instr_call *);
-extern void (*arm_dpi_instr_regshort[2 * 16 * 16])(struct cpu *,
-	struct arm_instr_call *);
-X(cmps);
-X(teqs);
-X(tsts);
-X(sub);
-X(add);
-X(subs);
-X(eor_regshort);
-X(cmps_regshort);
-
-
-#include "cpu_arm_instr_misc.cc"
-
-
-/*
- *  Shared between regular ARM and the THUMB encoded 'pop'.
- */
-void arm_pop(struct cpu* cpu, uint32_t* np, int p_bit, int u_bit, int s_bit, int w_bit, uint32_t iw)
-{
-	uint32_t addr = *np;
-	unsigned char data[4];
-	unsigned char *page;
-	int i, return_flag = 0;
-	uint32_t new_values[16];
-
-	if (s_bit) {
-		/*  Load to USR registers:  */
-		if ((cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32) {
-			fatal("[ bdt_load: s-bit: in usermode? ]\n");
-			s_bit = 0;
-		}
-		if (iw & 0x8000) {
-			s_bit = 0;
-			return_flag = 1;
-		}
-	}
-
-	for (i=(u_bit? 0 : 15); i>=0 && i<=15; i+=(u_bit? 1 : -1)) {
-		uint32_t value;
-
-		if (!((iw >> i) & 1)) {
-			/*  Skip register i:  */
-			continue;
-		}
-
-		if (p_bit) {
-			if (u_bit)
-				addr += sizeof(uint32_t);
-			else
-				addr -= sizeof(uint32_t);
-		}
-
-		page = cpu->cd.arm.host_load[addr >> 12];
-		if (page != NULL) {
-			uint32_t *p32 = (uint32_t *) page;
-			value = p32[(addr & 0xfff) >> 2];
-			/*  Change byte order of value if
-			    host and emulated endianness differ:  */
-#ifdef HOST_LITTLE_ENDIAN
-			if (cpu->byte_order == EMUL_BIG_ENDIAN)
-#else
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-#endif
-				value = ((value & 0xff) << 24) |
-				    ((value & 0xff00) << 8) |
-				    ((value & 0xff0000) >> 8) |
-				    ((value & 0xff000000) >> 24);
-		} else {
-			if (!cpu->memory_rw(cpu, cpu->mem, addr, data,
-			    sizeof(data), MEM_READ, CACHE_DATA)) {
-				/*  load failed  */
-				return;
-			}
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-				value = data[0] +
-				    (data[1] << 8) + (data[2] << 16)
-				    + (data[3] << 24);
-			} else {
-				value = data[3] +
-				    (data[2] << 8) + (data[1] << 16)
-				    + (data[0] << 24);
-			}
-		}
-
-		new_values[i] = value;
-
-		if (!p_bit) {
-			if (u_bit)
-				addr += sizeof(uint32_t);
-			else
-				addr -= sizeof(uint32_t);
-		}
-	}
-
-	for (i=(u_bit? 0 : 15); i>=0 && i<=15; i+=(u_bit? 1 : -1)) {
-		if (!((iw >> i) & 1)) {
-			/*  Skip register i:  */
-			continue;
-		}
-
-		if (!s_bit) {
-			cpu->cd.arm.r[i] = new_values[i];
-		} else {
-			switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
-			case ARM_MODE_USR32:
-			case ARM_MODE_SYS32:
-				cpu->cd.arm.r[i] = new_values[i];
-				break;
-			case ARM_MODE_FIQ32:
-				if (i >= 8 && i <= 14)
-					cpu->cd.arm.default_r8_r14[i-8] =
-					    new_values[i];
-				else
-					cpu->cd.arm.r[i] = new_values[i];
-				break;
-			case ARM_MODE_SVC32:
-			case ARM_MODE_ABT32:
-			case ARM_MODE_UND32:
-			case ARM_MODE_IRQ32:
-				if (i >= 13 && i <= 14)
-					cpu->cd.arm.default_r8_r14[i-8] =
-					    new_values[i];
-				else
-					cpu->cd.arm.r[i] = new_values[i];
-				break;
-			}
-		}
-	}
-
-	if (w_bit)
-		*np = addr;
-
-	if (return_flag) {
-		uint32_t new_cpsr;
-		int switch_register_banks;
-
-		switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
-		case ARM_MODE_FIQ32:
-			new_cpsr = cpu->cd.arm.spsr_fiq; break;
-		case ARM_MODE_ABT32:
-			new_cpsr = cpu->cd.arm.spsr_abt; break;
-		case ARM_MODE_UND32:
-			new_cpsr = cpu->cd.arm.spsr_und; break;
-		case ARM_MODE_IRQ32:
-			new_cpsr = cpu->cd.arm.spsr_irq; break;
-		case ARM_MODE_SVC32:
-			new_cpsr = cpu->cd.arm.spsr_svc; break;
-		default:fatal("bdt_load: unimplemented mode %i\n",
-			    cpu->cd.arm.cpsr & ARM_FLAG_MODE);
-			exit(1);
-		}
-
-		switch_register_banks = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) !=
-		    (new_cpsr & ARM_FLAG_MODE);
-
-		if (switch_register_banks)
-			arm_save_register_bank(cpu);
-
-		cpu->cd.arm.cpsr = new_cpsr;
-		cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28;
-
-		if (switch_register_banks)
-			arm_load_register_bank(cpu);
-	}
-
-	/*  NOTE: Special case: Loading the PC  */
-	if (iw & 0x8000) {
-		cpu->pc = cpu->cd.arm.r[ARM_PC] & 0xfffffffc;
-		if (cpu->machine->show_trace_tree)
-			cpu_functioncall_trace_return(cpu);
-		/*  TODO: There is no need to update the
-		    pointers if this is a return to the
-		    same page!  */
-		/*  Find the new physical page and update the
-		    translation pointers:  */
-		quick_pc_to_pointers_arm(cpu);
-	}
-}
-
-
-/*
- *  Shared between regular ARM and the THUMB encoded 'push'.
- */
-void arm_push(struct cpu* cpu, uint32_t* np, int p_bit, int u_bit, int s_bit, int w_bit, uint16_t regs)
-{
-	int i;
-	uint32_t value, addr = *np;
-	unsigned char data[4];
-	unsigned char *page;
-
-	for (i=(u_bit? 0 : 15); i>=0 && i<=15; i+=(u_bit? 1 : -1)) {
-		if (!((regs >> i) & 1)) {
-			/*  Skip register i:  */
-			continue;
-		}
-
-		value = cpu->cd.arm.r[i];
-
-		if (s_bit) {
-			switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
-			case ARM_MODE_FIQ32:
-				if (i >= 8 && i <= 14)
-					value = cpu->cd.arm.default_r8_r14[i-8];
-				break;
-			case ARM_MODE_ABT32:
-			case ARM_MODE_UND32:
-			case ARM_MODE_IRQ32:
-			case ARM_MODE_SVC32:
-				if (i >= 13 && i <= 14)
-					value = cpu->cd.arm.default_r8_r14[i-8];
-				break;
-			case ARM_MODE_USR32:
-			case ARM_MODE_SYS32:
-				break;
-			}
-		}
-
-		/*  NOTE/TODO: 8 vs 12 on some ARMs  */
-		if (i == ARM_PC)
-			value = cpu->pc + 12;
-
-		if (p_bit) {
-			if (u_bit)
-				addr += sizeof(uint32_t);
-			else
-				addr -= sizeof(uint32_t);
-		}
-
-		page = cpu->cd.arm.host_store[addr >> 12];
-		if (page != NULL) {
-			uint32_t *p32 = (uint32_t *) page;
-			/*  Change byte order of value if
-			    host and emulated endianness differ:  */
-#ifdef HOST_LITTLE_ENDIAN
-			if (cpu->byte_order == EMUL_BIG_ENDIAN)
-#else
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-#endif
-				value = ((value & 0xff) << 24) |
-				    ((value & 0xff00) << 8) |
-				    ((value & 0xff0000) >> 8) |
-				    ((value & 0xff000000) >> 24);
-			p32[(addr & 0xfff) >> 2] = value;
-		} else {
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-				data[0] = value;
-				data[1] = value >> 8;
-				data[2] = value >> 16;
-				data[3] = value >> 24;
-			} else {
-				data[0] = value >> 24;
-				data[1] = value >> 16;
-				data[2] = value >> 8;
-				data[3] = value;
-			}
-			if (!cpu->memory_rw(cpu, cpu->mem, addr, data,
-			    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-				/*  store failed  */
-				return;
-			}
-		}
-
-		if (!p_bit) {
-			if (u_bit)
-				addr += sizeof(uint32_t);
-			else
-				addr -= sizeof(uint32_t);
-		}
-	}
-
-	if (w_bit)
-		*np = addr;
-}
-
-
-/*
- *  bdt_load:  Block Data Transfer, Load
- *
- *  arg[0] = pointer to uint32_t in host memory, pointing to the base register
- *  arg[1] = 32-bit instruction word. Most bits are read from this.
- */
-X(bdt_load)
-{
-	uint32_t *np = (uint32_t *)ic->arg[0];
-	uint32_t low_pc;
-	uint32_t iw = ic->arg[1];  /*  xxxx100P USWLnnnn llllllll llllllll  */
-	int p_bit = iw & 0x01000000;
-	int u_bit = iw & 0x00800000;
-	int s_bit = iw & 0x00400000;
-	int w_bit = iw & 0x00200000;
-
-#ifdef GATHER_BDT_STATISTICS
-	if (!s_bit)
-		update_bdt_statistics(iw);
-#endif
-
-	/*  Synchronize the program counter:  */
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-
-	arm_pop(cpu, np, p_bit, u_bit, s_bit, w_bit, (uint16_t)iw);
-}
-Y(bdt_load)
-
-
-/*
- *  bdt_store:  Block Data Transfer, Store
- *
- *  arg[0] = pointer to uint32_t in host memory, pointing to the base register
- *  arg[1] = 32-bit instruction word. Most bits are read from this.
- */
-X(bdt_store)
-{
-	uint32_t *np = (uint32_t *)ic->arg[0];
-	uint32_t low_pc;
-	uint32_t iw = ic->arg[1];  /*  xxxx100P USWLnnnn llllllll llllllll  */
-	int p_bit = iw & 0x01000000;
-	int u_bit = iw & 0x00800000;
-	int s_bit = iw & 0x00400000;
-	int w_bit = iw & 0x00200000;
-
-#ifdef GATHER_BDT_STATISTICS
-	if (!s_bit)
-		update_bdt_statistics(iw);
-#endif
-
-	/*  Synchronize the program counter:  */
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-
-	arm_push(cpu, np, p_bit, u_bit, s_bit, w_bit, (uint16_t)iw);
-}
-Y(bdt_store)
-
-
-/*
- *  Load Register Exclusive (ARM "load linked"):
- *
- *  A Load Register Exclusive instruction initiates a RMW (read-modify-write)
- *  sequence.
- *
- *  A Store Register Exclusive instruction ends the sequence.
- *
- *  arg[0] = ptr to rt
- *  arg[1] = ptr to rn
- *  arg[2] = int32_t imm offset
- */
-X(ldrex)
-{
-	uint32_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
-	int low_pc;
-	uint8_t word[sizeof(uint32_t)];
-
-	/*  Synchronize the program counter:  */
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-
-	if (addr & (sizeof(word)-1)) {
-		fatal("TODO: ldrex unaligned access: exception\n");
-		exit(1);
-	}
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, word,
-	    sizeof(word), MEM_READ, CACHE_DATA)) {
-		/*  An exception occurred.  */
-		return;
-	}
-
-	cpu->cd.arm.rmw = 1;
-	cpu->cd.arm.rmw_addr = addr;
-	cpu->cd.arm.rmw_len = sizeof(word);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		reg(ic->arg[0]) = word[0] + (word[1] << 8)
-		    + (word[2] << 16) + (word[3] << 24);
-	else
-		reg(ic->arg[0]) = word[3] + (word[2] << 8)
-		    + (word[1] << 16) + (word[0] << 24);
-}
-Y(ldrex)
-/*
- *  Store Register Exclusive
- *
- *  arg[0] = ptr to rd
- *  arg[1] = ptr to rn
- *  arg[2] = ptr to rt
- */
-X(strex)
-{
-	uint32_t addr = reg(ic->arg[1]);
-	uint64_t r = reg(ic->arg[2]);
-	int low_pc, i;
-	uint8_t word[sizeof(uint32_t)];
-	
-	/*  Synchronize the program counter:  */
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-
-	if (addr & (sizeof(word)-1)) {
-		fatal("TODO: strex unaligned access: exception\n");
-		exit(1);
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		word[0]=r; word[1]=r>>8; word[2]=r>>16; word[3]=r>>24;
-	} else {
-		word[3]=r; word[2]=r>>8; word[1]=r>>16; word[0]=r>>24;
-	}
-
-	/*  If rmw is 0, then the store failed.  (This cache-line was written
-	    to by someone else.)  */
-	if (cpu->cd.arm.rmw == 0 || cpu->cd.arm.rmw_addr != addr
-	    || cpu->cd.arm.rmw_len != sizeof(word)) {
-		reg(ic->arg[0]) = 1;	// 1 = fail.
-		cpu->cd.arm.rmw = 0;
-		return;
-	}
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, word,
-	    sizeof(word), MEM_WRITE, CACHE_DATA)) {
-		/*  An exception occurred.  */
-		return;
-	}
-
-	/*  We succeeded. Let's invalidate everybody else's store to this
-	    cache line:  */
-	for (i=0; i<cpu->machine->ncpus; i++) {
-		if (cpu->machine->cpus[i]->cd.arm.rmw) {
-			uint64_t yaddr = addr, xaddr = cpu->machine->cpus[i]->
-			    cd.arm.rmw_addr;
-
-			/*  8-2048 bytes, implementation dependent :-(  */			
-			/*  https://stackoverflow.com/questions/11383125/do-the-arm-instructions-ldrex-strex-have-to-operate-on-cache-aligned-data  */
-			uint64_t mask = 2047;
-
-			xaddr &= mask;
-			yaddr &= mask;
-			if (xaddr == yaddr)
-				cpu->machine->cpus[i]->cd.arm.rmw = 0;
-		}
-	}
-
-	reg(ic->arg[0]) = 0;	// 0 = success
-	cpu->cd.arm.rmw = 0;
-}
-Y(strex)
-
-
-/*  Various load/store multiple instructions:  */
-extern uint32_t *multi_opcode[256];
-extern void (**multi_opcode_f[256])(struct cpu *, struct arm_instr_call *);
-X(multi_0x08b15018);
-X(multi_0x08ac000c__ge);
-X(multi_0x08a05018);
-
-
-/*****************************************************************************/
-
-
-/*
- *  netbsd_memset:
- *
- *  The core of a NetBSD/arm memset.
- *
- *  f01bc420:  e25XX080     subs    rX,rX,#0x80
- *  f01bc424:  a8ac000c     stmgeia ip!,{r2,r3}   (16 of these)
- *  ..
- *  f01bc464:  caffffed     bgt     0xf01bc420      <memset+0x38>
- */
-X(netbsd_memset)
-{
-	unsigned char *page;
-	uint32_t addr;
-
-	do {
-		addr = cpu->cd.arm.r[ARM_IP];
-
-		instr(subs)(cpu, ic);
-
-		if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
-		    ((cpu->cd.arm.flags & ARM_F_V)?1:0)) {
-			cpu->n_translated_instrs += 16;
-			/*  Skip the store multiples:  */
-			cpu->cd.arm.next_ic = &ic[17];
-			return;
-		}
-
-		/*  Crossing a page boundary? Then continue non-combined.  */
-		if ((addr & 0xfff) + 128 > 0x1000)
-			return;
-
-		/*  R2/R3 non-zero? Not allowed here.  */
-		if (cpu->cd.arm.r[2] != 0 || cpu->cd.arm.r[3] != 0)
-			return;
-
-		/*  printf("addr = 0x%08x\n", addr);  */
-
-		page = cpu->cd.arm.host_store[addr >> 12];
-		/*  No page translation? Continue non-combined.  */
-		if (page == NULL)
-			return;
-
-		/*  Clear:  */
-		memset(page + (addr & 0xfff), 0, 128);
-		cpu->cd.arm.r[ARM_IP] = addr + 128;
-		cpu->n_translated_instrs += 16;
-
-		/*  Branch back if greater:  */
-		cpu->n_translated_instrs += 1;
-	} while (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
-	    ((cpu->cd.arm.flags & ARM_F_V)?1:0) &&
-	    !(cpu->cd.arm.flags & ARM_F_Z));
-
-	/*  Continue at the instruction after the bgt:  */
-	cpu->cd.arm.next_ic = &ic[18];
-}
-
-
-/*
- *  netbsd_memcpy:
- *
- *  The core of a NetBSD/arm memcpy.
- *
- *  f01bc530:  e8b15018     ldmia   r1!,{r3,r4,ip,lr}
- *  f01bc534:  e8a05018     stmia   r0!,{r3,r4,ip,lr}
- *  f01bc538:  e8b15018     ldmia   r1!,{r3,r4,ip,lr}
- *  f01bc53c:  e8a05018     stmia   r0!,{r3,r4,ip,lr}
- *  f01bc540:  e2522020     subs    r2,r2,#0x20
- *  f01bc544:  aafffff9     bge     0xf01bc530
- */
-X(netbsd_memcpy)
-{
-	unsigned char *page_0, *page_1;
-	uint32_t addr_r0, addr_r1;
-
-	do {
-		addr_r0 = cpu->cd.arm.r[0];
-		addr_r1 = cpu->cd.arm.r[1];
-
-		/*  printf("addr_r0 = %08x  r1 = %08x\n", addr_r0, addr_r1);  */
-
-		/*  Crossing a page boundary? Then continue non-combined.  */
-		if ((addr_r0 & 0xfff) + 32 > 0x1000 ||
-		    (addr_r1 & 0xfff) + 32 > 0x1000) {
-			instr(multi_0x08b15018)(cpu, ic);
-			return;
-		}
-
-		page_0 = cpu->cd.arm.host_store[addr_r0 >> 12];
-		page_1 = cpu->cd.arm.host_store[addr_r1 >> 12];
-
-		/*  No page translations? Continue non-combined.  */
-		if (page_0 == NULL || page_1 == NULL) {
-			instr(multi_0x08b15018)(cpu, ic);
-			return;
-		}
-
-		memcpy(page_0 + (addr_r0 & 0xfff),
-		    page_1 + (addr_r1 & 0xfff), 32);
-		cpu->cd.arm.r[0] = addr_r0 + 32;
-		cpu->cd.arm.r[1] = addr_r1 + 32;
-
-		cpu->n_translated_instrs += 4;
-
-		instr(subs)(cpu, ic + 4);
-		cpu->n_translated_instrs ++;
-
-		/*  Loop while greater or equal:  */
-		cpu->n_translated_instrs ++;
-	} while (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
-	    ((cpu->cd.arm.flags & ARM_F_V)?1:0));
-
-	/*  Continue at the instruction after the bge:  */
-	cpu->cd.arm.next_ic = &ic[6];
-	cpu->n_translated_instrs --;
-}
-
-
-/*
- *  netbsd_cacheclean:
- *
- *  The core of a NetBSD/arm cache clean routine, variant 1:
- *
- *  f015f88c:  e4902020     ldr     r2,[r0],#32
- *  f015f890:  e2511020     subs    r1,r1,#0x20
- *  f015f894:  1afffffc     bne     0xf015f88c
- *  f015f898:  ee070f9a     mcr     15,0,r0,cr7,cr10,4
- */
-X(netbsd_cacheclean)
-{
-	uint32_t r1 = cpu->cd.arm.r[1];
-	cpu->n_translated_instrs += ((r1 >> 5) * 3);
-	cpu->cd.arm.r[0] += r1;
-	cpu->cd.arm.r[1] = 0;
-	cpu->cd.arm.next_ic = &ic[4];
-}
-
-
-/*
- *  netbsd_cacheclean2:
- *
- *  The core of a NetBSD/arm cache clean routine, variant 2:
- *
- *  f015f93c:  ee070f3a     mcr     15,0,r0,cr7,cr10,1
- *  f015f940:  ee070f36     mcr     15,0,r0,cr7,cr6,1
- *  f015f944:  e2800020     add     r0,r0,#0x20
- *  f015f948:  e2511020     subs    r1,r1,#0x20
- *  f015f94c:  8afffffa     bhi     0xf015f93c
- */
-X(netbsd_cacheclean2)
-{
-	cpu->n_translated_instrs += ((cpu->cd.arm.r[1] >> 5) * 5) - 1;
-	cpu->cd.arm.next_ic = &ic[5];
-}
-
-
-/*
- *  netbsd_scanc:
- *
- *  f01bccbc:  e5d13000     ldrb    r3,[r1]
- *  f01bccc0:  e7d23003     ldrb    r3,[r2,r3]
- *  f01bccc4:  e113000c     tsts    r3,ip
- */
-X(netbsd_scanc)
-{
-	unsigned char *page = cpu->cd.arm.host_load[cpu->cd.arm.r[1] >> 12];
-	uint32_t t;
-
-	if (page == NULL) {
-		instr(load_w0_byte_u1_p1_imm)(cpu, ic);
-		return;
-	}
-
-	t = page[cpu->cd.arm.r[1] & 0xfff];
-	t += cpu->cd.arm.r[2];
-	page = cpu->cd.arm.host_load[t >> 12];
-
-	if (page == NULL) {
-		instr(load_w0_byte_u1_p1_imm)(cpu, ic);
-		return;
-	}
-
-	cpu->cd.arm.r[3] = page[t & 0xfff];
-
-	t = cpu->cd.arm.r[3] & cpu->cd.arm.r[ARM_IP];
-	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-	if (t == 0)
-		cpu->cd.arm.flags |= ARM_F_Z;
-
-	cpu->n_translated_instrs += 2;
-	cpu->cd.arm.next_ic = &ic[3];
-}
-
-
-/*
- *  netbsd_idle:
- *
- *  L:	ldr     rX,[rY]
- *	teqs    rX,#0
- *	bne     X (samepage)
- *	teqs    rZ,#0
- *	beq     L (samepage)
- *	....
- *	X:  somewhere else on the same page
- */
-X(netbsd_idle)
-{
-	uint32_t rY = reg(ic[0].arg[0]);
-	uint32_t rZ = reg(ic[3].arg[0]);
-	uint32_t *p;
-	uint32_t rX;
-
-	p = (uint32_t *) cpu->cd.arm.host_load[rY >> 12];
-	if (p == NULL) {
-		instr(load_w0_word_u1_p1_imm)(cpu, ic);
-		return;
-	}
-
-	rX = p[(rY & 0xfff) >> 2];
-	/*  No need to convert endianness, since it's only a 0-test.  */
-
-	/*  This makes execution continue on the first teqs instruction,
-	    which is fine.  */
-	if (rX != 0) {
-		instr(load_w0_word_u1_p1_imm)(cpu, ic);
-		return;
-	}
-
-	if (rZ == 0) {
-		static int x = 0;
-
-		/*  Synch the program counter.  */
-		uint32_t low_pc = ((size_t)ic - (size_t)
-		    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-		cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1)
-		    << ARM_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-
-		/*  Quasi-idle for a while:  */
-		cpu->has_been_idling = 1;
-	        if (cpu->machine->ncpus == 1 && (++x) == 100) {
-			usleep(50);
-			x = 0;
-		}
-
-		cpu->n_translated_instrs += N_SAFE_DYNTRANS_LIMIT / 6;
-		cpu->cd.arm.next_ic = &nothing_call;
-		return;
-	}
-
-	cpu->cd.arm.next_ic = &ic[5];
-}
-
-
-/*
- *  strlen:
- *
- *  S: e5f03001   ldrb  rY,[rX,#1]!
- *     e3530000   cmps  rY,#0
- *     1afffffc   bne   S
- */
-X(strlen)
-{
-	unsigned int n_loops = 0;
-	uint32_t rY, rX = reg(ic[0].arg[0]);
-	unsigned char *p;
-
-	do {
-		rX ++;
-		p = cpu->cd.arm.host_load[rX >> 12];
-		if (p == NULL) {
-			cpu->n_translated_instrs += (n_loops * 3);
-			instr(load_w1_byte_u1_p1_imm)(cpu, ic);
-			return;
-		}
-
-		rY = reg(ic[0].arg[2]) = p[rX & 0xfff];	/*  load  */
-		reg(ic[0].arg[0]) = rX;			/*  writeback  */
-		n_loops ++;
-
-		/*  Compare rY to zero:  */
-		cpu->cd.arm.flags = ARM_F_C;
-		if (rY == 0)
-			cpu->cd.arm.flags |= ARM_F_Z;
-	} while (rY != 0);
-
-	cpu->n_translated_instrs += (n_loops * 3) - 1;
-	cpu->cd.arm.next_ic = &ic[3];
-}
-
-
-/*
- *  xchg:
- *
- *  e02YX00X     eor     rX,rY,rX
- *  e02XY00Y     eor     rY,rX,rY
- *  e02YX00X     eor     rX,rY,rX
- */
-X(xchg)
-{
-	uint32_t tmp = reg(ic[0].arg[0]);
-	cpu->n_translated_instrs += 2;
-	cpu->cd.arm.next_ic = &ic[3];
-	reg(ic[0].arg[0]) = reg(ic[1].arg[0]);
-	reg(ic[1].arg[0]) = tmp;
-}
-
-
-/*
- *  netbsd_copyin:
- *
- *  e4b0a004     ldrt    sl,[r0],#4
- *  e4b0b004     ldrt    fp,[r0],#4
- *  e4b06004     ldrt    r6,[r0],#4
- *  e4b07004     ldrt    r7,[r0],#4
- *  e4b08004     ldrt    r8,[r0],#4
- *  e4b09004     ldrt    r9,[r0],#4
- */
-X(netbsd_copyin)
-{
-	uint32_t r0 = cpu->cd.arm.r[0], ofs = (r0 & 0xffc), index = r0 >> 12;
-	unsigned char *p = cpu->cd.arm.host_load[index];
-	uint32_t *p32 = (uint32_t *) p, *q32;
-	int ok = cpu->cd.arm.is_userpage[index >> 5] & (1 << (index & 31));
-
-	if (ofs > 0x1000 - 6*4 || !ok || p == NULL) {
-		instr(load_w1_word_u1_p0_imm)(cpu, ic);
-		return;
-	}
-	q32 = &cpu->cd.arm.r[6];
-	ofs >>= 2;
-	q32[0] = p32[ofs+2];
-	q32[1] = p32[ofs+3];
-	q32[2] = p32[ofs+4];
-	q32[3] = p32[ofs+5];
-	q32[4] = p32[ofs+0];
-	q32[5] = p32[ofs+1];
-	cpu->cd.arm.r[0] = r0 + 24;
-	cpu->n_translated_instrs += 5;
-	cpu->cd.arm.next_ic = &ic[6];
-}
-
-
-/*
- *  netbsd_copyout:
- *
- *  e4a18004     strt    r8,[r1],#4
- *  e4a19004     strt    r9,[r1],#4
- *  e4a1a004     strt    sl,[r1],#4
- *  e4a1b004     strt    fp,[r1],#4
- *  e4a16004     strt    r6,[r1],#4
- *  e4a17004     strt    r7,[r1],#4
- */
-X(netbsd_copyout)
-{
-	uint32_t r1 = cpu->cd.arm.r[1], ofs = (r1 & 0xffc), index = r1 >> 12;
-	unsigned char *p = cpu->cd.arm.host_store[index];
-	uint32_t *p32 = (uint32_t *) p, *q32;
-	int ok = cpu->cd.arm.is_userpage[index >> 5] & (1 << (index & 31));
-
-	if (ofs > 0x1000 - 6*4 || !ok || p == NULL) {
-		instr(store_w1_word_u1_p0_imm)(cpu, ic);
-		return;
-	}
-	q32 = &cpu->cd.arm.r[6];
-	ofs >>= 2;
-	p32[ofs  ] = q32[2];
-	p32[ofs+1] = q32[3];
-	p32[ofs+2] = q32[4];
-	p32[ofs+3] = q32[5];
-	p32[ofs+4] = q32[0];
-	p32[ofs+5] = q32[1];
-	cpu->cd.arm.r[1] = r1 + 24;
-	cpu->n_translated_instrs += 5;
-	cpu->cd.arm.next_ic = &ic[6];
-}
-
-
-/*
- *  cmps by 0, followed by beq (inside the same page):
- */
-X(cmps0_beq_samepage)
-{
-	uint32_t a = reg(ic->arg[0]);
-	cpu->n_translated_instrs ++;
-	if (a == 0) {
-		cpu->cd.arm.flags = ARM_F_Z | ARM_F_C;
-	} else {
-		/*  Semi-ugly hack which sets the negative-bit if a < 0:  */
-		cpu->cd.arm.flags = ARM_F_C | ((a >> 28) & 8);
-	}
-	if (a == 0)
-		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
-	else
-		cpu->cd.arm.next_ic = &ic[2];
-}
-
-
-/*
- *  cmps followed by beq (inside the same page):
- */
-X(cmps_beq_samepage)
-{
-	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
-	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
-	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
-		cpu->cd.arm.flags |= ARM_F_V;
-	if (c == 0) {
-		cpu->cd.arm.flags |= ARM_F_Z;
-		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
-	} else {
-		cpu->cd.arm.next_ic = &ic[2];
-		if (c & 0x80000000)
-			cpu->cd.arm.flags |= ARM_F_N;
-	}
-}
-
-
-/*
- *  cmps followed by beq (not the same page):
- */
-X(cmps_0_beq)
-{
-	uint32_t a = reg(ic->arg[0]);
-	cpu->n_translated_instrs ++;
-	if (a == 0) {
-		cpu->cd.arm.flags = ARM_F_Z | ARM_F_C;
-		cpu->pc = (uint32_t)(((uint32_t)cpu->pc & 0xfffff000)
-		    + (int32_t)ic[1].arg[0]);
-		quick_pc_to_pointers_arm(cpu);
-	} else {
-		/*  Semi-ugly hack which sets the negative-bit if a < 0:  */
-		cpu->cd.arm.flags = ARM_F_C | ((a >> 28) & 8);
-		cpu->cd.arm.next_ic = &ic[2];
-	}
-}
-X(cmps_pos_beq)
-{
-	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
-	if ((int32_t)a < 0 && (int32_t)c >= 0)
-		cpu->cd.arm.flags |= ARM_F_V;
-	if (c == 0) {
-		cpu->cd.arm.flags |= ARM_F_Z;
-		cpu->pc = (uint32_t)(((uint32_t)cpu->pc & 0xfffff000)
-		    + (int32_t)ic[1].arg[0]);
-		quick_pc_to_pointers_arm(cpu);
-	} else {
-		cpu->cd.arm.next_ic = &ic[2];
-		if (c & 0x80000000)
-			cpu->cd.arm.flags |= ARM_F_N;
-	}
-}
-X(cmps_neg_beq)
-{
-	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
-	if ((int32_t)a >= 0 && (int32_t)c < 0)
-		cpu->cd.arm.flags |= ARM_F_V;
-	if (c == 0) {
-		cpu->cd.arm.flags |= ARM_F_Z;
-		cpu->pc = (uint32_t)(((uint32_t)cpu->pc & 0xfffff000)
-		    + (int32_t)ic[1].arg[0]);
-		quick_pc_to_pointers_arm(cpu);
-	} else {
-		cpu->cd.arm.next_ic = &ic[2];
-		if (c & 0x80000000)
-			cpu->cd.arm.flags |= ARM_F_N;
-	}
-}
-
-
-/*
- *  cmps by 0, followed by bne (inside the same page):
- */
-X(cmps0_bne_samepage)
-{
-	uint32_t a = reg(ic->arg[0]);
-	cpu->n_translated_instrs ++;
-	if (a == 0) {
-		cpu->cd.arm.flags = ARM_F_Z | ARM_F_C;
-	} else {
-		/*  Semi-ugly hack which sets the negative-bit if a < 0:  */
-		cpu->cd.arm.flags = ARM_F_C | ((a >> 28) & 8);
-	}
-	if (a == 0)
-		cpu->cd.arm.next_ic = &ic[2];
-	else
-		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
-}
-
-
-/*
- *  cmps followed by bne (inside the same page):
- */
-X(cmps_bne_samepage)
-{
-	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
-	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
-	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
-		cpu->cd.arm.flags |= ARM_F_V;
-	if (c == 0) {
-		cpu->cd.arm.flags |= ARM_F_Z;
-		cpu->cd.arm.next_ic = &ic[2];
-	} else {
-		if (c & 0x80000000)
-			cpu->cd.arm.flags |= ARM_F_N;
-		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
-	}
-}
-
-
-/*
- *  cmps followed by bcc (inside the same page):
- */
-X(cmps_bcc_samepage)
-{
-	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
-	if (c & 0x80000000)
-		cpu->cd.arm.flags |= ARM_F_N;
-	else if (c == 0)
-		cpu->cd.arm.flags |= ARM_F_Z;
-	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
-	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
-		cpu->cd.arm.flags |= ARM_F_V;
-	if (a >= b)
-		cpu->cd.arm.next_ic = &ic[2];
-	else
-		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
-}
-
-
-/*
- *  cmps (reg) followed by bcc (inside the same page):
- */
-X(cmps_reg_bcc_samepage)
-{
-	uint32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]), c = a - b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
-	if (c & 0x80000000)
-		cpu->cd.arm.flags |= ARM_F_N;
-	else if (c == 0)
-		cpu->cd.arm.flags |= ARM_F_Z;
-	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
-	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
-		cpu->cd.arm.flags |= ARM_F_V;
-	if (a >= b)
-		cpu->cd.arm.next_ic = &ic[2];
-	else
-		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
-}
-
-
-/*
- *  cmps followed by bhi (inside the same page):
- */
-X(cmps_bhi_samepage)
-{
-	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
-	if (c & 0x80000000)
-		cpu->cd.arm.flags |= ARM_F_N;
-	else if (c == 0)
-		cpu->cd.arm.flags |= ARM_F_Z;
-	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
-	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
-		cpu->cd.arm.flags |= ARM_F_V;
-	if (a > b)
-		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
-	else
-		cpu->cd.arm.next_ic = &ic[2];
-}
-
-
-/*
- *  cmps (reg) followed by bhi (inside the same page):
- */
-X(cmps_reg_bhi_samepage)
-{
-	uint32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]), c = a - b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
-	if (c & 0x80000000)
-		cpu->cd.arm.flags |= ARM_F_N;
-	else if (c == 0)
-		cpu->cd.arm.flags |= ARM_F_Z;
-	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
-	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
-		cpu->cd.arm.flags |= ARM_F_V;
-	if (a > b)
-		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
-	else
-		cpu->cd.arm.next_ic = &ic[2];
-}
-
-
-/*
- *  cmps followed by bgt (inside the same page):
- */
-X(cmps_bgt_samepage)
-{
-	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
-	if (c & 0x80000000)
-		cpu->cd.arm.flags |= ARM_F_N;
-	else if (c == 0)
-		cpu->cd.arm.flags |= ARM_F_Z;
-	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
-	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
-		cpu->cd.arm.flags |= ARM_F_V;
-	if ((int32_t)a > (int32_t)b)
-		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
-	else
-		cpu->cd.arm.next_ic = &ic[2];
-}
-
-
-/*
- *  cmps followed by ble (inside the same page):
- */
-X(cmps_ble_samepage)
-{
-	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a - b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags = ((uint32_t)a >= (uint32_t)b)? ARM_F_C : 0;
-	if (c & 0x80000000)
-		cpu->cd.arm.flags |= ARM_F_N;
-	else if (c == 0)
-		cpu->cd.arm.flags |= ARM_F_Z;
-	if (((int32_t)a >= 0 && (int32_t)b < 0 && (int32_t)c < 0) ||
-	    ((int32_t)a < 0 && (int32_t)b >= 0 && (int32_t)c >= 0))
-		cpu->cd.arm.flags |= ARM_F_V;
-	if ((int32_t)a <= (int32_t)b)
-		cpu->cd.arm.next_ic = (struct arm_instr_call *) ic[1].arg[0];
-	else
-		cpu->cd.arm.next_ic = &ic[2];
-}
-
-
-/*
- *  teqs followed by beq (inside the same page):
- */
-X(teqs_beq_samepage)
-{
-	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a ^ b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-	if (c == 0) {
-		cpu->cd.arm.flags |= ARM_F_Z;
-		cpu->cd.arm.next_ic = (struct arm_instr_call *)
-		    ic[1].arg[0];
-	} else {
-		if (c & 0x80000000)
-			cpu->cd.arm.flags |= ARM_F_N;
-		cpu->cd.arm.next_ic = &ic[2];
-	}
-}
-
-
-/*
- *  tsts followed by beq (inside the same page):
- *  (arg[1] must not have its highest bit set))
- */
-X(tsts_lo_beq_samepage)
-{
-	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a & b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-	if (c == 0)
-		cpu->cd.arm.flags |= ARM_F_Z;
-	if (c == 0)
-		cpu->cd.arm.next_ic = (struct arm_instr_call *)
-		    ic[1].arg[0];
-	else
-		cpu->cd.arm.next_ic = &ic[2];
-}
-
-
-/*
- *  teqs followed by bne (inside the same page):
- */
-X(teqs_bne_samepage)
-{
-	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a ^ b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-	if (c == 0) {
-		cpu->cd.arm.flags |= ARM_F_Z;
-	} else {
-		if (c & 0x80000000)
-			cpu->cd.arm.flags |= ARM_F_N;
-	}
-	if (c == 0)
-		cpu->cd.arm.next_ic = &ic[2];
-	else
-		cpu->cd.arm.next_ic = (struct arm_instr_call *)
-		    ic[1].arg[0];
-}
-
-
-/*
- *  tsts followed by bne (inside the same page):
- *  (arg[1] must not have its highest bit set))
- */
-X(tsts_lo_bne_samepage)
-{
-	uint32_t a = reg(ic->arg[0]), b = ic->arg[1], c = a & b;
-	cpu->n_translated_instrs ++;
-	cpu->cd.arm.flags &= ~(ARM_F_Z | ARM_F_N);
-	if (c == 0)
-		cpu->cd.arm.flags |= ARM_F_Z;
-	if (c == 0)
-		cpu->cd.arm.next_ic = &ic[2];
-	else
-		cpu->cd.arm.next_ic = (struct arm_instr_call *)
-		    ic[1].arg[0];
-}
-
-
-/*****************************************************************************/
-
-
-X(end_of_page)
-{
-	/*  Update the PC:  (offset 0, but on the next page)  */
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (ARM_IC_ENTRIES_PER_PAGE << ARM_INSTR_ALIGNMENT_SHIFT);
-
-	/*  Find the new physical page and update the translation pointers:  */
-	quick_pc_to_pointers_arm(cpu);
-
-	/*  end_of_page doesn't count as an executed instruction:  */
-	cpu->n_translated_instrs --;
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  Combine: netbsd_memset():
- *
- *  Check for the core of a NetBSD/arm memset; large memsets use a sequence
- *  of 16 store-multiple instructions, each storing 2 registers at a time.
- */
-void COMBINE(netbsd_memset)(struct cpu *cpu,
-	struct arm_instr_call *ic, int low_addr)
-{
-#ifdef HOST_LITTLE_ENDIAN
-	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
-	    & (ARM_IC_ENTRIES_PER_PAGE-1);
-
-	if (n_back >= 17) {
-		int i;
-		for (i=-16; i<=-1; i++)
-			if (ic[i].f != instr(multi_0x08ac000c__ge))
-				return;
-		if (ic[-17].f == instr(subs) &&
-		    ic[-17].arg[0]==ic[-17].arg[2] && ic[-17].arg[1] == 128 &&
-		    ic[ 0].f == instr(b_samepage__gt) &&
-		    ic[ 0].arg[0] == (size_t)&ic[-17]) {
-			ic[-17].f = instr(netbsd_memset);
-		}
-	}
-#endif
-}
-
-
-/*
- *  Combine: netbsd_memcpy():
- *
- *  Check for the core of a NetBSD/arm memcpy; large memcpys use a
- *  sequence of ldmia instructions.
- */
-void COMBINE(netbsd_memcpy)(struct cpu *cpu, struct arm_instr_call *ic,
-	int low_addr)
-{
-#ifdef HOST_LITTLE_ENDIAN
-	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
-	    & (ARM_IC_ENTRIES_PER_PAGE-1);
-
-	if (n_back >= 5) {
-		if (ic[-5].f==instr(multi_0x08b15018) &&
-		    ic[-4].f==instr(multi_0x08a05018) &&
-		    ic[-3].f==instr(multi_0x08b15018) &&
-		    ic[-2].f==instr(multi_0x08a05018) &&
-		    ic[-1].f == instr(subs) &&
-		    ic[-1].arg[0]==ic[-1].arg[2] && ic[-1].arg[1] == 0x20 &&
-		    ic[ 0].f == instr(b_samepage__ge) &&
-		    ic[ 0].arg[0] == (size_t)&ic[-5]) {
-			ic[-5].f = instr(netbsd_memcpy);
-		}
-	}
-#endif
-}
-
-
-/*
- *  Combine: netbsd_cacheclean():
- *
- *  Check for the core of a NetBSD/arm cache clean. (There are two variants.)
- */
-void COMBINE(netbsd_cacheclean)(struct cpu *cpu,
-	struct arm_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
-	    & (ARM_IC_ENTRIES_PER_PAGE-1);
-
-	if (n_back >= 3) {
-		if (ic[-3].f==instr(load_w0_word_u1_p0_imm) &&
-		    ic[-2].f == instr(subs) &&
-		    ic[-2].arg[0]==ic[-2].arg[2] && ic[-2].arg[1] == 0x20 &&
-		    ic[-1].f == instr(b_samepage__ne) &&
-		    ic[-1].arg[0] == (size_t)&ic[-3]) {
-			ic[-3].f = instr(netbsd_cacheclean);
-		}
-	}
-}
-
-
-/*
- *  Combine: netbsd_cacheclean2():
- *
- *  Check for the core of a NetBSD/arm cache clean. (Second variant.)
- */
-void COMBINE(netbsd_cacheclean2)(struct cpu *cpu,
-	struct arm_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
-	    & (ARM_IC_ENTRIES_PER_PAGE-1);
-
-	if (n_back >= 4) {
-		if (ic[-4].f == instr(mcr_mrc) && ic[-4].arg[0] == 0xee070f3a &&
-		    ic[-3].f == instr(mcr_mrc) && ic[-3].arg[0] == 0xee070f36 &&
-		    ic[-2].f == instr(add) &&
-		    ic[-2].arg[0]==ic[-2].arg[2] && ic[-2].arg[1] == 0x20 &&
-		    ic[-1].f == instr(subs) &&
-		    ic[-1].arg[0]==ic[-1].arg[2] && ic[-1].arg[1] == 0x20) {
-			ic[-4].f = instr(netbsd_cacheclean2);
-		}
-	}
-}
-
-
-/*
- *  Combine: netbsd_scanc():
- */
-void COMBINE(netbsd_scanc)(struct cpu *cpu,
-	struct arm_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
-	    & (ARM_IC_ENTRIES_PER_PAGE-1);
-
-	if (n_back < 2)
-		return;
-
-	if (ic[-2].f == instr(load_w0_byte_u1_p1_imm) &&
-	    ic[-2].arg[0] == (size_t)(&cpu->cd.arm.r[1]) &&
-	    ic[-2].arg[1] == 0 &&
-	    ic[-2].arg[2] == (size_t)(&cpu->cd.arm.r[3]) &&
-	    ic[-1].f == instr(load_w0_byte_u1_p1_reg) &&
-	    ic[-1].arg[0] == (size_t)(&cpu->cd.arm.r[2]) &&
-	    ic[-1].arg[1] == (size_t)arm_r_r3_t0_c0 &&
-	    ic[-1].arg[2] == (size_t)(&cpu->cd.arm.r[3])) {
-		ic[-2].f = instr(netbsd_scanc);
-	}
-}
-
-
-/*
- *  Combine: strlen():
- */
-void COMBINE(strlen)(struct cpu *cpu,
-	struct arm_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
-	    & (ARM_IC_ENTRIES_PER_PAGE-1);
-
-	if (n_back < 2)
-		return;
-
-	if (ic[-2].f == instr(load_w1_byte_u1_p1_imm) &&
-	    ic[-2].arg[1] == 1 &&
-	    ic[-2].arg[2] == (size_t)(&cpu->cd.arm.r[3]) &&
-	    ic[-1].f == instr(cmps) &&
-	    ic[-1].arg[0] == (size_t)(&cpu->cd.arm.r[3]) &&
-	    ic[-1].arg[1] == 0) {
-		ic[-2].f = instr(strlen);
-	}
-}
-
-
-/*
- *  Combine: xchg():
- */
-void COMBINE(xchg)(struct cpu *cpu,
-	struct arm_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
-	    & (ARM_IC_ENTRIES_PER_PAGE-1);
-	size_t a, b;
-
-	if (n_back < 2)
-		return;
-
-	a = ic[-2].arg[0]; b = ic[-1].arg[0];
-
-	if (ic[-2].f == instr(eor_regshort) &&
-	    ic[-1].f == instr(eor_regshort) &&
-	    ic[-2].arg[0] == a && ic[-2].arg[1] == b && ic[-2].arg[2] == b &&
-	    ic[-1].arg[0] == b && ic[-1].arg[1] == a && ic[-1].arg[2] == a &&
-	    ic[ 0].arg[0] == a && ic[ 0].arg[1] == b && ic[ 0].arg[2] == b) {
-		ic[-2].f = instr(xchg);
-	}
-}
-
-
-/*
- *  Combine: netbsd_copyin():
- */
-void COMBINE(netbsd_copyin)(struct cpu *cpu,
-	struct arm_instr_call *ic, int low_addr)
-{
-#ifdef HOST_LITTLE_ENDIAN
-	int i, n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
-	    & (ARM_IC_ENTRIES_PER_PAGE-1);
-
-	if (n_back < 5)
-		return;
-
-	for (i=-5; i<0; i++) {
-		if (ic[i].f != instr(load_w1_word_u1_p0_imm) ||
-		    ic[i].arg[0] != (size_t)(&cpu->cd.arm.r[0]) ||
-		    ic[i].arg[1] != 4)
-			return;
-	}
-
-	if (ic[-5].arg[2] == (size_t)(&cpu->cd.arm.r[10]) &&
-	    ic[-4].arg[2] == (size_t)(&cpu->cd.arm.r[11]) &&
-	    ic[-3].arg[2] == (size_t)(&cpu->cd.arm.r[6]) &&
-	    ic[-2].arg[2] == (size_t)(&cpu->cd.arm.r[7]) &&
-	    ic[-1].arg[2] == (size_t)(&cpu->cd.arm.r[8])) {
-		ic[-5].f = instr(netbsd_copyin);
-	}
-#endif
-}
-
-
-/*
- *  Combine: netbsd_copyout():
- */
-void COMBINE(netbsd_copyout)(struct cpu *cpu,
-	struct arm_instr_call *ic, int low_addr)
-{
-#ifdef HOST_LITTLE_ENDIAN
-	int i, n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
-	    & (ARM_IC_ENTRIES_PER_PAGE-1);
-
-	if (n_back < 5)
-		return;
-
-	for (i=-5; i<0; i++) {
-		if (ic[i].f != instr(store_w1_word_u1_p0_imm) ||
-		    ic[i].arg[0] != (size_t)(&cpu->cd.arm.r[1]) ||
-		    ic[i].arg[1] != 4)
-			return;
-	}
-
-	if (ic[-5].arg[2] == (size_t)(&cpu->cd.arm.r[8]) &&
-	    ic[-4].arg[2] == (size_t)(&cpu->cd.arm.r[9]) &&
-	    ic[-3].arg[2] == (size_t)(&cpu->cd.arm.r[10]) &&
-	    ic[-2].arg[2] == (size_t)(&cpu->cd.arm.r[11]) &&
-	    ic[-1].arg[2] == (size_t)(&cpu->cd.arm.r[6])) {
-		ic[-5].f = instr(netbsd_copyout);
-	}
-#endif
-}
-
-
-/*
- *  Combine: cmps + beq, etc:
- */
-void COMBINE(beq_etc)(struct cpu *cpu,
-	struct arm_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> ARM_INSTR_ALIGNMENT_SHIFT)
-	    & (ARM_IC_ENTRIES_PER_PAGE-1);
-	if (n_back < 1)
-		return;
-	if (ic[0].f == instr(b__eq)) {
-		if (ic[-1].f == instr(cmps)) {
-			if (ic[-1].arg[1] == 0)
-				ic[-1].f = instr(cmps_0_beq);
-			else if (ic[-1].arg[1] & 0x80000000)
-				ic[-1].f = instr(cmps_neg_beq);
-			else
-				ic[-1].f = instr(cmps_pos_beq);
-		}
-		return;
-	}
-	if (ic[0].f == instr(b_samepage__eq)) {
-		if (ic[-1].f == instr(cmps)) {
-			if (ic[-1].arg[1] == 0)
-				ic[-1].f = instr(cmps0_beq_samepage);
-			else
-				ic[-1].f = instr(cmps_beq_samepage);
-		}
-		if (ic[-1].f == instr(tsts) &&
-		    !(ic[-1].arg[1] & 0x80000000)) {
-			ic[-1].f = instr(tsts_lo_beq_samepage);
-		}
-		if (n_back >= 4 &&
-		    ic[-4].f == instr(load_w0_word_u1_p1_imm) &&
-		    ic[-4].arg[0] != ic[-4].arg[2] &&
-		    ic[-4].arg[1] == 0 &&
-		    ic[-4].arg[2] == ic[-3].arg[0] &&
-		    /*  Note: The teqs+bne is already combined!  */
-		    ic[-3].f == instr(teqs_bne_samepage) &&
-		    ic[-3].arg[1] == 0 &&
-		    ic[-2].f == instr(b_samepage__ne) &&
-		    ic[-1].f == instr(teqs) &&
-		    ic[-1].arg[0] != ic[-4].arg[0] &&
-		    ic[-1].arg[1] == 0) {
-			ic[-4].f = instr(netbsd_idle);
-		}
-		if (ic[-1].f == instr(teqs)) {
-			ic[-1].f = instr(teqs_beq_samepage);
-		}
-		return;
-	}
-	if (ic[0].f == instr(b_samepage__ne)) {
-		if (ic[-1].f == instr(cmps)) {
-			if (ic[-1].arg[1] == 0)
-				ic[-1].f = instr(cmps0_bne_samepage);
-			else
-				ic[-1].f = instr(cmps_bne_samepage);
-		}
-		if (ic[-1].f == instr(tsts) &&
-		    !(ic[-1].arg[1] & 0x80000000)) {
-			ic[-1].f = instr(tsts_lo_bne_samepage);
-		}
-		if (ic[-1].f == instr(teqs)) {
-			ic[-1].f = instr(teqs_bne_samepage);
-		}
-		return;
-	}
-	if (ic[0].f == instr(b_samepage__cc)) {
-		if (ic[-1].f == instr(cmps)) {
-			ic[-1].f = instr(cmps_bcc_samepage);
-		}
-		if (ic[-1].f == instr(cmps_regshort)) {
-			ic[-1].f = instr(cmps_reg_bcc_samepage);
-		}
-		return;
-	}
-	if (ic[0].f == instr(b_samepage__hi)) {
-		if (ic[-1].f == instr(cmps)) {
-			ic[-1].f = instr(cmps_bhi_samepage);
-		}
-		if (ic[-1].f == instr(cmps_regshort)) {
-			ic[-1].f = instr(cmps_reg_bhi_samepage);
-		}
-		return;
-	}
-	if (ic[0].f == instr(b_samepage__gt)) {
-		if (ic[-1].f == instr(cmps)) {
-			ic[-1].f = instr(cmps_bgt_samepage);
-		}
-		return;
-	}
-	if (ic[0].f == instr(b_samepage__le)) {
-		if (ic[-1].f == instr(cmps)) {
-			ic[-1].f = instr(cmps_ble_samepage);
-		}
-		return;
-	}
-}
-
-
-/*****************************************************************************/
-
-
-static void arm_switch_clear(struct arm_instr_call *ic, int rd,
-	int condition_code)
-{
-	switch (rd) {
-	case  0: ic->f = cond_instr(clear_r0); break;
-	case  1: ic->f = cond_instr(clear_r1); break;
-	case  2: ic->f = cond_instr(clear_r2); break;
-	case  3: ic->f = cond_instr(clear_r3); break;
-	case  4: ic->f = cond_instr(clear_r4); break;
-	case  5: ic->f = cond_instr(clear_r5); break;
-	case  6: ic->f = cond_instr(clear_r6); break;
-	case  7: ic->f = cond_instr(clear_r7); break;
-	case  8: ic->f = cond_instr(clear_r8); break;
-	case  9: ic->f = cond_instr(clear_r9); break;
-	case 10: ic->f = cond_instr(clear_r10); break;
-	case 11: ic->f = cond_instr(clear_r11); break;
-	case 12: ic->f = cond_instr(clear_r12); break;
-	case 13: ic->f = cond_instr(clear_r13); break;
-	case 14: ic->f = cond_instr(clear_r14); break;
-	}
-}
-
-
-static void arm_switch_mov1(struct arm_instr_call *ic, int rd,
-	int condition_code)
-{
-	switch (rd) {
-	case  0: ic->f = cond_instr(mov1_r0); break;
-	case  1: ic->f = cond_instr(mov1_r1); break;
-	case  2: ic->f = cond_instr(mov1_r2); break;
-	case  3: ic->f = cond_instr(mov1_r3); break;
-	case  4: ic->f = cond_instr(mov1_r4); break;
-	case  5: ic->f = cond_instr(mov1_r5); break;
-	case  6: ic->f = cond_instr(mov1_r6); break;
-	case  7: ic->f = cond_instr(mov1_r7); break;
-	case  8: ic->f = cond_instr(mov1_r8); break;
-	case  9: ic->f = cond_instr(mov1_r9); break;
-	case 10: ic->f = cond_instr(mov1_r10); break;
-	case 11: ic->f = cond_instr(mov1_r11); break;
-	case 12: ic->f = cond_instr(mov1_r12); break;
-	case 13: ic->f = cond_instr(mov1_r13); break;
-	case 14: ic->f = cond_instr(mov1_r14); break;
-	}
-}
-
-
-static void arm_switch_add1(struct arm_instr_call *ic, int rd,
-	int condition_code)
-{
-	switch (rd) {
-	case  0: ic->f = cond_instr(add1_r0); break;
-	case  1: ic->f = cond_instr(add1_r1); break;
-	case  2: ic->f = cond_instr(add1_r2); break;
-	case  3: ic->f = cond_instr(add1_r3); break;
-	case  4: ic->f = cond_instr(add1_r4); break;
-	case  5: ic->f = cond_instr(add1_r5); break;
-	case  6: ic->f = cond_instr(add1_r6); break;
-	case  7: ic->f = cond_instr(add1_r7); break;
-	case  8: ic->f = cond_instr(add1_r8); break;
-	case  9: ic->f = cond_instr(add1_r9); break;
-	case 10: ic->f = cond_instr(add1_r10); break;
-	case 11: ic->f = cond_instr(add1_r11); break;
-	case 12: ic->f = cond_instr(add1_r12); break;
-	case 13: ic->f = cond_instr(add1_r13); break;
-	case 14: ic->f = cond_instr(add1_r14); break;
-	}
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  arm_instr_to_be_translated():
- *
- *  Translate an instruction word into an arm_instr_call. ic is filled in with
- *  valid data for the translated instruction, or a "nothing" instruction if
- *  there was a translation failure. The newly translated instruction is then
- *  executed.
- */
-X(to_be_translated)
-{
-	uint32_t addr, low_pc, iword, imm = 0;
-	unsigned char *page;
-	unsigned char ib[4];
-	int condition_code, main_opcode, secondary_opcode, s_bit, rn, rd, r8;
-	int p_bit, u_bit, w_bit, l_bit, regform, rm, any_pc_reg; // , c, t
-	void (*samepage_function)(struct cpu *, struct arm_instr_call *);
-
-	/*  Figure out the address of the instruction:  */
-	low_pc = ((size_t)ic - (size_t)cpu->cd.arm.cur_ic_page)
-	    / sizeof(struct arm_instr_call);
-	addr = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) <<
-	    ARM_INSTR_ALIGNMENT_SHIFT);
-	addr += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc = addr;
-	addr &= ~((1 << ARM_INSTR_ALIGNMENT_SHIFT) - 1);
-
-	/*  Read the instruction word from memory:  */
-	page = cpu->cd.arm.host_load[addr >> 12];
-
-	if (page != NULL) {
-		/*  fatal("TRANSLATION HIT! 0x%08x\n", addr);  */
-		memcpy(ib, page + (addr & 0xfff), sizeof(ib));
-	} else {
-		/*  fatal("TRANSLATION MISS! 0x%08x\n", addr);  */
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, &ib[0],
-		    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
-			fatal("to_be_translated(): "
-			    "read failed: TODO\n");
-			return;
-		}
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		iword = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
-	else
-		iword = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);
-
-
-#define DYNTRANS_TO_BE_TRANSLATED_HEAD
-#include "cpu_dyntrans.cc"
-#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD
-
-
-	/*  The idea of taking bits 27..24 was found here:
-	    http://armphetamine.sourceforge.net/oldinfo.html  */
-	condition_code = iword >> 28;
-	main_opcode = (iword >> 24) & 15;
-	secondary_opcode = (iword >> 21) & 15;
-	u_bit = iword & 0x00800000;
-	w_bit = iword & 0x00200000;
-	s_bit = l_bit = iword & 0x00100000;
-	rn    = (iword >> 16) & 15;
-	rd    = (iword >> 12) & 15;
-	r8    = (iword >> 8) & 15;
-	// c     = (iword >> 7) & 31;
-	// t     = (iword >> 4) & 7;
-	rm    = iword & 15;
-
-	/*
-	 *  Translate the instruction:
-	 */
-
-	if ((iword >> 28) == 0xf) {
-		/*  The "never" condition is nowadays used for special encodings.  */
-		if ((iword & 0xfc70f000) == 0xf450f000) {
-			/*  Preload:  TODO.  Treat as NOP for now.  */
-			ic->f = instr(nop);
-			goto okay;
-		}
-
-		if (iword == 0xf10c0040) {
-			/*  cpsid f. Treat as NOP for now.  */
-			ic->f = instr(nop);
-			goto okay;
-		}
-
-		if (iword == 0xf10c0080) {
-			/*  cpsid i. Treat as NOP for now.  */
-			ic->f = instr(nop);
-			goto okay;
-		}
-
-		if (iword == 0xf57ff04f) {
-			/*  dsb sy. Treat as NOP for now.  */
-			ic->f = instr(nop);
-			goto okay;
-		}
-
-		if (iword == 0xf57ff05f) {
-			/*  dmb sy. Treat as NOP for now.  */
-			ic->f = instr(nop);
-			goto okay;
-		}
-
-		if (iword == 0xf57ff06f) {
-			/*  isb sy. Treat as NOP for now.  */
-			ic->f = instr(nop);
-			goto okay;
-		}
-
-		switch (main_opcode) {
-		case 0xa:
-		case 0xb:
-			ic->f = instr(blx_imm);
-
-			/*  arg 1 = offset of current instruction  */
-			ic->arg[1] = addr & 0xffc;
-
-			/*  arg 0 = relative jump distance + 1 (to enable THUMB)  */
-			ic->arg[0] = (iword & 0x00ffffff) << 2;
-			/*  Sign-extend:  */
-			if (ic->arg[0] & 0x02000000)
-				ic->arg[0] |= 0xfc000000;
-			if (main_opcode == 0xb)
-				ic->arg[0] += 2;
-			ic->arg[0] = (int32_t)(ic->arg[0] + 8 + 1);
-			break;
-		default:
-			goto bad;
-		}
-		goto okay;
-	}
-
-	switch (main_opcode) {
-
-	case 0x0:
-	case 0x1:
-	case 0x2:
-	case 0x3:
-		/*  Check special cases first:  */
-		if ((iword & 0x0ff00fff) == 0x01900f9f) {
-			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-			ic->arg[1] = (size_t)(&cpu->cd.arm.r[rn]);
-			ic->arg[2] = 0;
-
-			if (rd == ARM_PC || rn == ARM_PC) {
-				if (!cpu->translation_readahead)
-					fatal("ldrex with pc register: TODO\n");
-				goto bad;
-			}
-			
-			ic->f = cond_instr(ldrex);
-			break;
-		}
-
-		if ((iword & 0x0ff00ff0) == 0x01800f90) {
-			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-			ic->arg[1] = (size_t)(&cpu->cd.arm.r[rn]);
-			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rm]);
-
-			if (rd == ARM_PC || rm == ARM_PC || rn == ARM_PC ||
-			    rd == rm || rd == rn) {
-				if (!cpu->translation_readahead)
-					fatal("strex with bad register: TODO\n");
-				goto bad;
-			}
-			
-			ic->f = cond_instr(strex);
-			break;
-		}
-
-		if ((iword & 0x0ff000f0) == 0x00600090) {
-			ic->arg[0] = iword;
-			ic->f = cond_instr(mls);
-			break;
-		}
-		
-		if ((iword & 0x0fc000f0) == 0x00000090) {
-			/*
-			 *  Multiplication:
-			 *  xxxx0000 00ASdddd nnnnssss 1001mmmm (Rd,Rm,Rs[,Rn])
-			 */
-			if (iword & 0x00200000) {
-				if (s_bit)
-					ic->f = cond_instr(mlas);
-				else
-					ic->f = cond_instr(mla);
-				ic->arg[0] = iword;
-			} else {
-				if (s_bit)
-					ic->f = cond_instr(muls);
-				else
-					ic->f = cond_instr(mul);
-				/*  NOTE: rn means rd in this case:  */
-				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
-				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
-				ic->arg[2] = (size_t)(&cpu->cd.arm.r[r8]);
-			}
-			break;
-		}
-		if ((iword & 0x0f8000f0) == 0x00800090) {
-			/*  Long multiplication:  */
-			if (s_bit) {
-				if (!cpu->translation_readahead)
-					fatal("TODO: sbit mull\n");
-				goto bad;
-			}
-			ic->f = cond_instr(mull);
-			ic->arg[0] = iword;
-			break;
-		}
-		if ((iword & 0x0f900ff0) == 0x01000050) {
-			if (!cpu->translation_readahead)
-				fatal("TODO: q{,d}{add,sub}\n");
-			goto bad;
-		}
-		if ((iword & 0x0ff000d0) == 0x01200010) {
-			/*  bx or blx  */
-			if (iword & 0x20)
-				ic->f = cond_instr(blx_reg);
-			else {
-				if (cpu->machine->show_trace_tree &&
-				    rm == ARM_LR)
-					ic->f = cond_instr(bx_trace);
-				else
-					ic->f = cond_instr(bx);
-			}
-			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rm]);
-			ic->arg[2] = (addr & 0xffc) + 4;
-                        break;
-                }
-		if ((iword & 0x0fb00ff0) == 0x1000090) {
-			if (iword & 0x00400000)
-				ic->f = cond_instr(swpb);
-			else
-				ic->f = cond_instr(swp);
-			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-			ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
-			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rn]);
-			break;
-		}
-		if ((iword & 0x0fff0ff0) == 0x016f0f10) {
-			ic->f = cond_instr(clz);
-			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rm]);
-			ic->arg[1] = (size_t)(&cpu->cd.arm.r[rd]);
-			break;
-		}
-		if ((iword & 0x0ff00090) == 0x01000080) {
-			/*  TODO: smlaXX  */
-			goto bad;
-		}
-		if ((iword & 0x0ff00090) == 0x01400080) {
-			/*  TODO: smlalY  */
-			goto bad;
-		}
-		if ((iword & 0x0ff000b0) == 0x01200080) {
-			/*  TODO: smlawY  */
-			goto bad;
-		}
-		if ((iword & 0x0ff0f090) == 0x01600080) {
-			/*  smulXY (16-bit * 16-bit => 32-bit)  */
-			switch (iword & 0x60) {
-			case 0x00: ic->f = cond_instr(smulbb); break;
-			case 0x20: ic->f = cond_instr(smultb); break;
-			case 0x40: ic->f = cond_instr(smulbt); break;
-			default:   ic->f = cond_instr(smultt); break;
-			}
-			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rm]);
-			ic->arg[1] = (size_t)(&cpu->cd.arm.r[r8]);
-			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rn]); /*  Rd  */
-			break;
-		}
-		if ((iword & 0x0ff0f0b0) == 0x012000a0) {
-			/*  TODO: smulwY  */
-			goto bad;
-		}
-		if ((iword & 0x0fb0fff0) == 0x0120f000 ||
-		    (iword & 0x0fb0f000) == 0x0320f000) {
-			/*  msr: move to [S|C]PSR from a register or
-			    immediate value  */
-			if (iword & 0x02000000) {
-				if (iword & 0x00400000)
-					ic->f = cond_instr(msr_imm_spsr);
-				else
-					ic->f = cond_instr(msr_imm);
-			} else {
-				if (rm == ARM_PC) {
-					if (!cpu->translation_readahead)
-						fatal("msr PC?\n");
-					goto bad;
-				}
-				if (iword & 0x00400000)
-					ic->f = cond_instr(msr_spsr);
-				else
-					ic->f = cond_instr(msr);
-			}
-			imm = iword & 0xff;
-			while (r8-- > 0)
-				imm = (imm >> 2) | ((imm & 3) << 30);
-			ic->arg[0] = imm;
-			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rm]);
-			{
-				uint32_t arg1 = 0;
-				if (iword & (1<<16)) arg1 |= 0x000000ff;
-				if (iword & (1<<17)) arg1 |= 0x0000ff00;
-				if (iword & (1<<18)) arg1 |= 0x00ff0000;
-				if (iword & (1<<19)) arg1 |= 0xff000000;
-				ic->arg[1] = arg1;
-				if (arg1 == 0)
-					ic->f = instr(nop);
-			}
-			break;
-		}
-		if ((iword & 0x0fbf0fff) == 0x010f0000) {
-			/*  mrs: move from CPSR/SPSR to a register:  */
-			if (rd == ARM_PC) {
-				if (!cpu->translation_readahead)
-					fatal("mrs PC?\n");
-				goto bad;
-			}
-			if (iword & 0x00400000)
-				ic->f = cond_instr(mrs_spsr);
-			else
-				ic->f = cond_instr(mrs);
-			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-			break;
-		}
-		if ((iword & 0x0e000090) == 0x00000090) {
-			regform = !(iword & 0x00400000);
-			imm = ((iword >> 4) & 0xf0) | (iword & 0xf);
-			p_bit = main_opcode & 1;
-			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
-			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rd]);
-			if (rd == ARM_PC || rn == ARM_PC) {
-				ic->f = arm_load_store_instr_3_pc[
-				    condition_code + (l_bit? 16 : 0)
-				    + (iword & 0x40? 32 : 0)
-				    + (w_bit? 64 : 0)
-				    + (iword & 0x20? 128 : 0)
-				    + (u_bit? 256 : 0) + (p_bit? 512 : 0)
-				    + (regform? 1024 : 0)];
-				if (rn == ARM_PC)
-					ic->arg[0] = (size_t)
-					    (&cpu->cd.arm.tmp_pc);
-				if (!l_bit && rd == ARM_PC)
-					ic->arg[2] = (size_t)
-					    (&cpu->cd.arm.tmp_pc);
-			} else
-				ic->f = arm_load_store_instr_3[
-				    condition_code + (l_bit? 16 : 0)
-				    + (iword & 0x40? 32 : 0)
-				    + (w_bit? 64 : 0)
-				    + (iword & 0x20? 128 : 0)
-				    + (u_bit? 256 : 0) + (p_bit? 512 : 0)
-				    + (regform? 1024 : 0)];
-			if (regform)
-				ic->arg[1] = (size_t)(void *)arm_r[iword & 0xf];
-			else
-				ic->arg[1] = imm;
-			break;
-		}
-
-		if (iword & 0x80 && !(main_opcode & 2) && iword & 0x10) {
-			if (!cpu->translation_readahead)
-				fatal("reg form blah blah\n");
-			goto bad;
-		}
-
-		/*  "bkpt", ARMv5 and above  */
-		if ((iword & 0x0ff000f0) == 0x01200070) {
-			ic->f = cond_instr(bkpt);
-			ic->arg[0] = addr & 0xfff;
-			break;
-		}
-
-		/*  "mov pc,lr":  */
-		if ((iword & 0x0fffffff) == 0x01a0f00e) {
-			if (cpu->machine->show_trace_tree)
-				ic->f = cond_instr(ret_trace);
-			else
-				ic->f = cond_instr(ret);
-			break;
-		}
-
-		/*  "mov reg,reg" or "mov reg,pc":  */
-		if ((iword & 0x0fff0ff0) == 0x01a00000 && rd != ARM_PC) {
-			if (rm != ARM_PC) {
-				ic->f = cond_instr(mov_reg_reg);
-				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rm]);
-			} else {
-				ic->f = cond_instr(mov_reg_pc);
-				ic->arg[0] = (addr & 0xfff) + 8;
-			}
-			ic->arg[1] = (size_t)(&cpu->cd.arm.r[rd]);
-			break;
-		}
-
-		/*  "mov reg,#0":  */
-		if ((iword & 0x0fff0fff) == 0x03a00000 && rd != ARM_PC) {
-			arm_switch_clear(ic, rd, condition_code);
-			break;
-		}
-
-		/*  "mov reg,#1":  */
-		if ((iword & 0x0fff0fff) == 0x03a00001 && rd != ARM_PC) {
-			arm_switch_mov1(ic, rd, condition_code);
-			break;
-		}
-
-		/*  "add reg,reg,#1":  */
-		if ((iword & 0x0ff00fff) == 0x02800001 && rd != ARM_PC
-		    && rn == rd) {
-			arm_switch_add1(ic, rd, condition_code);
-			break;
-		}
-
-		if ((iword & 0x0ff00000) == 0x03000000) {
-			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
-			ic->arg[1] = (((iword & 0xf0000) >> 4) | (iword & 0xfff));
-			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rd]);
-			ic->f = cond_instr(movw);
-			if (rd == ARM_PC) {
-				if (!cpu->translation_readahead)
-					fatal("movw with rd = pc?\n");
-				goto bad;
-			}
-			break;
-		} else if ((iword & 0x0ff00000) == 0x03400000) {
-			ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
-			ic->arg[1] = (((iword & 0xf0000) >> 4) | (iword & 0xfff)) << 16;
-			ic->arg[2] = (size_t)(&cpu->cd.arm.r[rd]);
-			ic->f = cond_instr(movt);
-			if (rd == ARM_PC) {
-				if (!cpu->translation_readahead)
-					fatal("movt with rd = pc?\n");
-				goto bad;
-			}
-			break;
-		}
-
-		/*
-		 *  Generic Data Processing Instructions:
-		 */
-		if ((main_opcode & 2) == 0)
-			regform = 1;
-		else
-			regform = 0;
-
-		if (regform) {
-			/*  0x1000 signifies Carry bit update on rotation,
-			    which is not necessary for add,adc,sub,sbc,
-			    rsb,rsc,cmp, or cmn, because they update the
-			    Carry bit manually anyway.  */
-			int q = 0x1000;
-			if (s_bit == 0)
-				q = 0;
-			if ((secondary_opcode >= 2 && secondary_opcode <= 7)
-			    || secondary_opcode==0xa || secondary_opcode==0xb)
-				q = 0;
-			ic->arg[1] = (size_t)(void *)arm_r[(iword & 0xfff) + q];
-		} else {
-			int steps = r8;
-
-			imm = iword & 0xff;
-			
-			while (r8-- > 0)
-				imm = (imm >> 2) | ((imm & 3) << 30);
-
-			if (steps != 0 && (imm != 0 && imm < 256)) {
-				if (!cpu->translation_readahead)
-					fatal("TODO: see cpu_arm_instr_dpi; non-zero steps but still under 256 is not implemented yet\n");
-				goto bad;
-			}
-
-			ic->arg[1] = imm;
-		}
-
-		/*  mvn #imm ==> mov #~imm  */
-		if (secondary_opcode == 0xf && !regform) {
-			secondary_opcode = 0xd;
-			ic->arg[1] = ~ic->arg[1];
-		}
-
-		ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
-		ic->arg[2] = (size_t)(&cpu->cd.arm.r[rd]);
-		any_pc_reg = 0;
-		if (rn == ARM_PC || rd == ARM_PC)
-			any_pc_reg = 1;
-
-		if (!any_pc_reg && regform && (iword & 0xfff) < ARM_PC) {
-			ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
-			ic->f = arm_dpi_instr_regshort[condition_code +
-			    16 * secondary_opcode + (s_bit? 256 : 0)];
-		} else
-			ic->f = arm_dpi_instr[condition_code +
-			    16 * secondary_opcode + (s_bit? 256 : 0) +
-			    (any_pc_reg? 512 : 0) + (regform? 1024 : 0)];
-
-		if (ic->f == instr(eor_regshort))
-			cpu->cd.arm.combination_check = COMBINE(xchg);
-		if (iword == 0xe113000c)
-			cpu->cd.arm.combination_check = COMBINE(netbsd_scanc);
-		break;
-
-	case 0x4:	/*  Load and store...  */
-	case 0x5:	/*  xxxx010P UBWLnnnn ddddoooo oooooooo  Immediate  */
-	case 0x6:	/*  xxxx011P UBWLnnnn ddddcccc ctt0mmmm  Register  */
-	case 0x7:
-		// Special non-loadstore encodings:
-		if (main_opcode >= 6 && iword & 0x10) {
-			if ((iword & 0x0fff0ff0) == 0x06bf0f30) {
-				ic->f = cond_instr(rev);
-				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
-			} else if ((iword & 0x0fff03f0) == 0x06bf0070) {
-				ic->f = cond_instr(sxth);
-				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
-				ic->arg[2] = ((iword & 0xc00) >> 10) << 3;
-			} else if ((iword & 0x0fff03f0) == 0x06ef0070) {
-				ic->f = cond_instr(uxtb);
-				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
-				ic->arg[2] = ((iword & 0xc00) >> 10) << 3;
-			} else if ((iword & 0x0ff003f0) == 0x06e00070) {
-				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rn]);
-				ic->arg[2] = (size_t)(&cpu->cd.arm.r[rm]);
-				ic->f = cond_instr(uxtab);
-				if (iword & 0xc00) {
-					if (!cpu->translation_readahead)
-						fatal("unimplemented uxtab with rotate != 0\n");
-					goto bad;
-				}
-			} else if ((iword & 0x0fff03f0) == 0x06ff0070) {
-				ic->f = cond_instr(uxth);
-				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
-				ic->arg[2] = ((iword & 0xc00) >> 10) << 3;
-			} else if ((iword & 0x0ff003f0) == 0x06f00070) {
-				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rn]);
-				ic->arg[2] = (size_t)(&cpu->cd.arm.r[rm]);
-				ic->f = cond_instr(uxtah);
-				if (iword & 0xc00) {
-					if (!cpu->translation_readahead)
-						fatal("unimplemented uxtah with rotate != 0\n");
-					goto bad;
-				}
-			} else if ((iword & 0x0fe00070) == 0x07c00010) {
-				ic->f = cond_instr(bfi);
-				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
-				int lsb = (iword >> 7) & 31;
-				int msb = (iword >> 16) & 31;
-				ic->arg[2] = (msb << 16) + lsb;
-			} else if ((iword & 0x0fe00070) == 0x07e00050) {
-				ic->f = cond_instr(ubfx);
-				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
-				int lsb = (iword >> 7) & 31;
-				int width = 1 + ((iword >> 16) & 31);
-				ic->arg[2] = (width << 16) + lsb;
-			} else if ((iword & 0x0fe00070) == 0x07a00050) {
-				ic->f = cond_instr(sbfx);
-				ic->arg[0] = (size_t)(&cpu->cd.arm.r[rd]);
-				ic->arg[1] = (size_t)(&cpu->cd.arm.r[rm]);
-				int lsb = (iword >> 7) & 31;
-				int width = 1 + ((iword >> 16) & 31);
-				ic->arg[2] = (width << 16) + lsb;
-			} else {
-				if (!cpu->translation_readahead)
-					fatal("unimplemented special non-loadstore encoding!\n");
-				goto bad;
-			}
-			break;
-		}
-	
-		ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
-		ic->arg[2] = (size_t)(&cpu->cd.arm.r[rd]);
-		if (rd == ARM_PC || rn == ARM_PC) {
-			ic->f = arm_load_store_instr_pc[((iword >> 16)
-			    & 0x3f0) + condition_code];
-			if (rn == ARM_PC)
-				ic->arg[0] = (size_t)(&cpu->cd.arm.tmp_pc);
-			if (!l_bit && rd == ARM_PC)
-				ic->arg[2] = (size_t)(&cpu->cd.arm.tmp_pc);
-		} else {
-			ic->f = arm_load_store_instr[((iword >> 16) &
-			    0x3f0) + condition_code];
-		}
-		imm = iword & 0xfff;
-		if (main_opcode < 6)
-			ic->arg[1] = imm;
-		else
-			ic->arg[1] = (size_t)(void *)arm_r[iword & 0xfff];
-		if ((iword & 0x0e000010) == 0x06000010) {
-			/*  GDB uses this for breakpoints.  */
-			ic->f = cond_instr(und);
-			ic->arg[0] = addr & 0xfff;
-		}
-		/*  Special case: pc-relative load within the same page:  */
-		if (rn == ARM_PC && rd != ARM_PC && main_opcode < 6 && l_bit) {
-			unsigned char *p = page;
-			int ofs = (addr & 0xfff) + 8, max = 0xffc;
-			int b_bit = iword & 0x00400000;
-			if (b_bit)
-				max = 0xfff;
-			if (u_bit)
-				ofs += (iword & 0xfff);
-			else
-				ofs -= (iword & 0xfff);
-			/*  NOTE/TODO: This assumes 4KB pages,
-			    it will not work with 1KB pages.  */
-			if (ofs >= 0 && ofs <= max && p != NULL) {
-				unsigned char cbuf[4];
-				int len = b_bit? 1 : 4;
-				uint32_t x, a = (addr & 0xfffff000) | ofs;
-				/*  ic->f = cond_instr(mov);  */
-				ic->f = arm_dpi_instr[condition_code + 16*0xd];
-				ic->arg[2] = (size_t)(&cpu->cd.arm.r[rd]);
-
-				memcpy(cbuf, p + (a & 0xfff), len);
-
-				if (b_bit) {
-					x = cbuf[0];
-				} else {
-					if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-						x = cbuf[0] + (cbuf[1]<<8) +
-						    (cbuf[2]<<16) + (cbuf[3]<<24);
-					else
-						x = cbuf[3] + (cbuf[2]<<8) +
-						    (cbuf[1]<<16) + (cbuf[0]<<24);
-				}
-				
-				ic->arg[1] = x;
-			}
-		}
-		if (iword == 0xe4b09004)
-			cpu->cd.arm.combination_check = COMBINE(netbsd_copyin);
-		if (iword == 0xe4a17004)
-			cpu->cd.arm.combination_check = COMBINE(netbsd_copyout);
-		break;
-
-	case 0x8:	/*  Multiple load/store...  (Block data transfer)  */
-	case 0x9:	/*  xxxx100P USWLnnnn llllllll llllllll  */
-		ic->arg[0] = (size_t)(&cpu->cd.arm.r[rn]);
-		ic->arg[1] = (size_t)iword;
-		/*  Generic case:  */
-		if (l_bit)
-			ic->f = cond_instr(bdt_load);
-		else
-			ic->f = cond_instr(bdt_store);
-#if defined(HOST_LITTLE_ENDIAN) && !defined(GATHER_BDT_STATISTICS)
-		/*
-		 *  Check for availability of optimized implementation:
-		 *  xxxx100P USWLnnnn llllllll llllllll
-		 *           ^  ^ ^ ^        ^  ^ ^ ^   (0x00950154)
-		 *  These bits are used to select which list to scan, and then
-		 *  the list is scanned linearly.
-		 *
-		 *  The optimized functions do not support show_trace_tree,
-		 *  but it's ok to use the unoptimized version in that case.
-		 */
-		if (!cpu->machine->show_trace_tree) {
-			int i = 0, j = iword;
-			j = ((j & 0x00800000) >> 16) | ((j & 0x00100000) >> 14)
-			  | ((j & 0x00040000) >> 13) | ((j & 0x00010000) >> 12)
-			  | ((j & 0x00000100) >>  5) | ((j & 0x00000040) >>  4)
-			  | ((j & 0x00000010) >>  3) | ((j & 0x00000004) >>  2);
-			while (multi_opcode[j][i] != 0) {
-				if ((iword & 0x0fffffff) ==
-				    multi_opcode[j][i]) {
-					ic->f = multi_opcode_f[j]
-					    [i*16 + condition_code];
-					break;
-				}
-				i ++;
-			}
-		}
-#endif
-		if (rn == ARM_PC) {
-			if (!cpu->translation_readahead)
-				fatal("TODO: bdt with PC as base\n");
-			goto bad;
-		}
-		break;
-
-	case 0xa:					/*  B: branch  */
-	case 0xb:					/*  BL: branch+link  */
-		if (main_opcode == 0x0a) {
-			ic->f = cond_instr(b);
-			samepage_function = cond_instr(b_samepage);
-
-			/*  Abort read-ahead on unconditional branches:  */
-			if (condition_code == 0xe &&
-			    cpu->translation_readahead > 1)
-                                cpu->translation_readahead = 1;
-
-			if (iword == 0xcaffffed)
-				cpu->cd.arm.combination_check =
-				    COMBINE(netbsd_memset);
-			if (iword == 0xaafffff9)
-				cpu->cd.arm.combination_check =
-				    COMBINE(netbsd_memcpy);
-		} else {
-			if (cpu->machine->show_trace_tree) {
-				ic->f = cond_instr(bl_trace);
-				samepage_function =
-				    cond_instr(bl_samepage_trace);
-			} else {
-				ic->f = cond_instr(bl);
-				samepage_function = cond_instr(bl_samepage);
-			}
-		}
-
-		/*  arg 1 = offset of current instruction  */
-		/*  arg 2 = offset of the following instruction  */
-		ic->arg[1] = addr & 0xffc;
-		ic->arg[2] = (addr & 0xffc) + 4;
-
-		ic->arg[0] = (iword & 0x00ffffff) << 2;
-		/*  Sign-extend:  */
-		if (ic->arg[0] & 0x02000000)
-			ic->arg[0] |= 0xfc000000;
-		/*
-		 *  Branches are calculated as PC + 8 + offset.
-		 */
-		ic->arg[0] = (int32_t)(ic->arg[0] + 8);
-
-		/*
-		 *  Special case: branch within the same page:
-		 *
-		 *  arg[0] = addr of the arm_instr_call of the target
-		 *  arg[1] = addr of the next arm_instr_call.
-		 */
-		{
-			uint32_t mask_within_page =
-			    ((ARM_IC_ENTRIES_PER_PAGE-1) <<
-			    ARM_INSTR_ALIGNMENT_SHIFT) |
-			    ((1 << ARM_INSTR_ALIGNMENT_SHIFT) - 1);
-			uint32_t old_pc = addr;
-			uint32_t new_pc = old_pc + (int32_t)ic->arg[0];
-			if ((old_pc & ~mask_within_page) ==
-			    (new_pc & ~mask_within_page)) {
-				ic->f = samepage_function;
-				ic->arg[0] = (size_t) (
-				    cpu->cd.arm.cur_ic_page +
-				    ((new_pc & mask_within_page) >>
-				    ARM_INSTR_ALIGNMENT_SHIFT));
-				ic->arg[1] = (size_t) (
-				    cpu->cd.arm.cur_ic_page +
-				    (((addr & mask_within_page) + 4) >>
-				    ARM_INSTR_ALIGNMENT_SHIFT));
-			} else if (main_opcode == 0x0a) {
-				/*  Special hack for a plain "b":  */
-				ic->arg[0] += ic->arg[1];
-			}
-		}
-
-		if (main_opcode == 0xa && (condition_code <= 1
-		    || condition_code == 3 || condition_code == 8
-		    || condition_code == 12 || condition_code == 13))
-			cpu->cd.arm.combination_check = COMBINE(beq_etc);
-
-		if (iword == 0x1afffffc)
-			cpu->cd.arm.combination_check = COMBINE(strlen);
-
-		/*  Hm. Does this really increase performance?  */
-		if (iword == 0x8afffffa)
-			cpu->cd.arm.combination_check =
-			    COMBINE(netbsd_cacheclean2);
-		break;
-
-	case 0xc:
-	case 0xd:
-		/*
-		 *  xxxx1100 0100nnnn ddddcccc oooommmm    MCRR c,op,Rd,Rn,CRm
-		 *  xxxx1100 0101nnnn ddddcccc oooommmm    MRRC c,op,Rd,Rn,CRm
-		 */
-		if ((iword & 0x0fe00fff) == 0x0c400000) {
-			/*  Special case: mar/mra DSP instructions  */
-			if (!cpu->translation_readahead)
-				fatal("TODO: mar/mra DSP instructions!\n");
-			/*  Perhaps these are actually identical to MCRR/MRRC */
-			goto bad;
-		}
-
-		if ((iword & 0x0fe00000) == 0x0c400000) {
-			if (!cpu->translation_readahead)
-				fatal("MCRR/MRRC: TODO\n");
-			goto bad;
-		}
-
-		/*
-		 *  TODO: LDC/STC
-		 *
-		 *  For now, treat as Undefined instructions. This causes e.g.
-		 *  Linux/ARM to emulate these instructions (floating point).
-		 */
-#if 1
-		ic->f = cond_instr(und);
-		ic->arg[0] = addr & 0xfff;
-#else
-		if (!cpu->translation_readahead)
-			fatal("LDC/STC: TODO\n");
-		goto bad;
-#endif
-		break;
-
-	case 0xe:
-		if ((iword & 0x0ff00ff0) == 0x0e200010) {
-			/*  Special case: mia* DSP instructions  */
-			/*  See Intel's 27343601.pdf, page 16-20  */
-			if (!cpu->translation_readahead)
-				fatal("TODO: mia* DSP instructions!\n");
-			goto bad;
-		}
-		if (iword & 0x10) {
-			/*  xxxx1110 oooLNNNN ddddpppp qqq1MMMM  MCR/MRC  */
-			ic->arg[0] = iword;
-			ic->f = cond_instr(mcr_mrc);
-		} else {
-			/*  xxxx1110 oooonnnn ddddpppp qqq0mmmm  CDP  */
-			ic->arg[0] = iword;
-			ic->f = cond_instr(cdp);
-		}
-		if (iword == 0xee070f9a)
-			cpu->cd.arm.combination_check =
-			    COMBINE(netbsd_cacheclean);
-		break;
-
-	case 0xf:
-		/*  SWI:  */
-		/*  Default handler:  */
-		ic->f = cond_instr(swi);
-		ic->arg[0] = addr & 0xfff;
-		if (iword == 0xef8c64eb) {
-			/*  Hack for rebooting a machine:  */
-			ic->f = instr(reboot);
-		} else if (iword == 0xef8c64be) {
-			/*  Hack for openfirmware prom emulation:  */
-			ic->f = instr(openfirmware);
-		}
-		break;
-
-	default:goto bad;
-	}
-
-okay:
-
-#define	DYNTRANS_TO_BE_TRANSLATED_TAIL
-#include "cpu_dyntrans.cc" 
-#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_arm_instr_dpi.c gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr_dpi.c
--- gxemul-0.6.2/src/cpus/cpu_arm_instr_dpi.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr_dpi.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,341 @@
+/*
+ *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  ARM Data Processing Instructions
+ *  --------------------------------
+ *
+ *  xxxx000a aaaSnnnn ddddcccc ctttmmmm  Register form
+ *  xxxx001a aaaSnnnn ddddrrrr bbbbbbbb  Immediate form
+ *
+ *  4 bits to select which instruction, one of the following:
+ *
+ *	0000	and		1000	tst
+ *	0001	eor		1001	teq
+ *	0010	sub		1010	cmp
+ *	0011	rsb		1011	cmn
+ *	0100	add		1100	orr
+ *	0101	adc		1101	mov
+ *	0110	sbc		1110	bic
+ *	0111	rsc		1111	mvn
+ *
+ *  1 bit to select Status flag update.
+ *
+ *  1 bit to select Register form or Immediate form.
+ *
+ *  1 bit to select if the PC register is used.
+ *
+ *  Each function must also (as always) be repeated for each possible ARM
+ *  condition code (15 in total).  Total: 1920 functions.
+ *
+ *  NOTE: This does not include any special common cases, which might be
+ *        nice to have. Examples: comparing against zero, moving common
+ *        constants.
+ *
+ *  See src/tools/generate_arm_dpi.c for more details.
+ */
+
+
+#ifndef NOTHING
+#define NOTHING
+// Used to break out of dyntrans. TODO: Duplicate of arm_instr_nothing
+// code in tmp_arm_head.cc.
+void abortdyntrans(struct cpu* cpu, struct arm_instr_call* ic) { cpu->cd.arm.next_ic --; }
+static struct arm_instr_call abortdyntrans_call = { abortdyntrans, {0,0,0} };
+#endif	// NOTHING
+
+
+/*
+ *  arg[0] = pointer to rn
+ *  arg[1] = int32_t immediate value   OR  ptr to a reg_func() function
+ *  arg[2] = pointer to rd
+ */
+void A__NAME(struct cpu *cpu, struct arm_instr_call *ic)
+{
+#if defined(A__RSB) || defined(A__RSC)
+#define VAR_A  b
+#define VAR_B  a
+#else
+#define VAR_A  a
+#define VAR_B  b
+#endif
+
+#ifdef A__REG
+	uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *)
+	    = (uint32_t (*)(struct cpu *, struct arm_instr_call *))
+	      (void *)(size_t)ic->arg[1];
+#endif
+
+#ifdef A__S
+	uint32_t c32;
+#endif
+#if defined(A__CMP) || defined(A__CMN) || defined(A__ADC) || defined(A__ADD) \
+ || defined(A__RSC) || defined(A__RSB) || defined(A__SBC) || defined(A__SUB)
+#ifdef A__S
+	uint64_t
+#else
+	uint32_t
+#endif
+#else
+	uint32_t
+#endif
+	    VAR_B =
+#ifdef A__REG
+	    reg_func(cpu, ic)
+#else
+#ifdef A__REGSHORT
+	    reg(ic->arg[1])
+#else
+	    ic->arg[1]
+#endif
+#endif
+	    , c64
+#if !defined(A__MOV) && !defined(A__MVN)
+	    , VAR_A = reg(ic->arg[0])
+#endif
+	    ;
+
+#if defined(A__MOV) || defined(A__MVN) || defined(A__TST) || defined(A__TEQ) \
+ || defined(A__AND) || defined(A__BIC) || defined(A__EOR) || defined(A__ORR)
+#if !defined(A__REG) && !defined(A__REGSHORT) && defined(A__S)
+	/*
+	 *  TODO: This is not 100% correct, but should work with "recommended"
+	 *  ARM code: Immediate values larger than 255 are encoded with
+	 *  rotation. If the S-bit is set, then the carry bit is set to the
+	 *  highest bit of the operand.
+	 *
+	 *  TODO 2: Perhaps this check should be moved out from here, and into
+	 *  cpu_arm_instr.c. (More correct, and higher performance.)
+	 */
+	if (VAR_B > 255) {
+		if (VAR_B & 0x80000000)
+			cpu->cd.arm.flags |= ARM_F_C;
+		else
+			cpu->cd.arm.flags &= ~ARM_F_C;
+	}
+#endif
+#endif
+
+
+#if !defined(A__MOV) && !defined(A__MVN)
+#ifdef A__PC
+	if (ic->arg[0] == (size_t)&cpu->cd.arm.r[ARM_PC]) {
+		uint32_t low_pc = ((size_t)ic - (size_t)
+		    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
+		VAR_A = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1)
+		    << ARM_INSTR_ALIGNMENT_SHIFT);
+		VAR_A += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT) + 8;
+	}
+#endif
+#endif
+
+	/*
+	 *  Perform the operation:
+	 */
+#if defined(A__AND) || defined(A__TST)
+	c64 = a & b;
+#endif
+#if defined(A__EOR) || defined(A__TEQ)
+	c64 = a ^ b;
+#endif
+#if defined(A__SUB) || defined(A__CMP) || defined(A__RSB)
+	c64 = a - b;
+#endif
+#if defined(A__ADD) || defined(A__CMN)
+	c64 = a + b;
+#endif
+#if defined(A__ADC)
+	c64 = a + b + (cpu->cd.arm.flags & ARM_F_C? 1 : 0);
+#endif
+#if defined(A__SBC) || defined(A__RSC)
+	c64 = a - b - (cpu->cd.arm.flags & ARM_F_C? 0 : 1);
+#endif
+#if defined(A__ORR)
+	c64 = a | b;
+#endif
+#if defined(A__MOV)
+	c64 = b;
+#endif
+#if defined(A__BIC)
+	c64 = a & ~b;
+#endif
+#if defined(A__MVN)
+	c64 = ~b;
+#endif
+
+
+#if defined(A__CMP) || defined(A__CMN) || defined(A__TST) || defined(A__TEQ)
+	/*  No write to rd for compare/test.  */
+#else
+#ifdef A__PC
+	if (ic->arg[2] == (size_t)&cpu->cd.arm.r[ARM_PC]) {
+#ifndef A__S
+		uint32_t old_pc = cpu->pc;
+		uint32_t mask_within_page = ((ARM_IC_ENTRIES_PER_PAGE-1)
+		    << ARM_INSTR_ALIGNMENT_SHIFT) |
+		    ((1 << ARM_INSTR_ALIGNMENT_SHIFT) - 1);
+#endif
+		cpu->pc = (uint32_t)c64;
+#ifdef A__S
+		/*  Copy the right SPSR into CPSR:  */
+		arm_save_register_bank(cpu);
+		switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
+		case ARM_MODE_FIQ32:
+			cpu->cd.arm.cpsr = cpu->cd.arm.spsr_fiq; break;
+		case ARM_MODE_IRQ32:
+			cpu->cd.arm.cpsr = cpu->cd.arm.spsr_irq; break;
+		case ARM_MODE_SVC32:
+			cpu->cd.arm.cpsr = cpu->cd.arm.spsr_svc; break;
+		case ARM_MODE_ABT32:
+			cpu->cd.arm.cpsr = cpu->cd.arm.spsr_abt; break;
+		case ARM_MODE_UND32:
+			cpu->cd.arm.cpsr = cpu->cd.arm.spsr_und; break;
+		}
+		cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28;
+		arm_load_register_bank(cpu);
+#else
+		if ((old_pc & ~mask_within_page) ==
+		    ((uint32_t)cpu->pc & ~mask_within_page)) {
+			cpu->cd.arm.next_ic = cpu->cd.arm.cur_ic_page +
+			    ((cpu->pc & mask_within_page) >>
+			    ARM_INSTR_ALIGNMENT_SHIFT);
+		} else
+#endif
+			quick_pc_to_pointers(cpu);
+
+		if (cpu->pc & 1) {
+			// Switch to THUMB and break out of the dyntrans loop.
+			cpu->cd.arm.cpsr |= ARM_FLAG_T;
+			cpu->cd.arm.next_ic = &abortdyntrans_call;
+		}
+		return;
+	} else
+		reg(ic->arg[2]) = c64;
+#else
+	reg(ic->arg[2]) = c64;
+#endif
+#endif
+
+
+	/*
+	 *  Status flag update (if the S-bit is set):
+	 */
+#ifdef A__S
+	c32 = c64;
+	cpu->cd.arm.flags
+#if defined(A__CMP) || defined(A__CMN) || defined(A__ADC) || defined(A__ADD) \
+ || defined(A__RSB) || defined(A__RSC) || defined(A__SBC) || defined(A__SUB)
+	    &= ~(ARM_F_V | ARM_F_C | ARM_F_Z | ARM_F_N);
+#else
+	    &= ~(ARM_F_Z | ARM_F_N);
+#endif
+
+#if defined(A__CMP) || defined(A__RSB) || defined(A__SUB) || \
+    defined(A__RSC) || defined(A__SBC)
+	if ((uint32_t)a >= (uint32_t)b)
+		cpu->cd.arm.flags |= ARM_F_C;
+#else
+#if defined(A__ADC) || defined(A__ADD) || defined(A__CMN)
+	if (c32 != c64)
+		cpu->cd.arm.flags |= ARM_F_C;
+#endif
+#endif
+
+	if (c32 == 0)
+		cpu->cd.arm.flags |= ARM_F_Z;
+
+	if ((int32_t)c32 < 0)
+		cpu->cd.arm.flags |= ARM_F_N;
+
+	/*  Calculate the Overflow bit:  */
+#if defined(A__CMP) || defined(A__CMN) || defined(A__ADC) || defined(A__ADD) \
+ || defined(A__RSB) || defined(A__RSC) || defined(A__SBC) || defined(A__SUB)
+	{
+		int v = 0;
+#if defined(A__ADD) || defined(A__CMN)
+		if (((int32_t)a >= 0 && (int32_t)b >= 0 &&
+		    (int32_t)c32 < 0) ||
+		    ((int32_t)a < 0 && (int32_t)b < 0 &&
+		    (int32_t)c32 >= 0))
+			v = 1;
+#else
+#if defined(A__SUB) || defined(A__RSB) || defined(A__CMP) || \
+    defined(A__RSC) || defined(A__SBC)
+		if (((int32_t)a >= 0 && (int32_t)b < 0 &&
+		    (int32_t)c32 < 0) ||
+		    ((int32_t)a < 0 && (int32_t)b >= 0 &&
+		    (int32_t)c32 >= 0))
+			v = 1;
+#endif
+#endif
+		if (v)
+			cpu->cd.arm.flags |= ARM_F_V;
+	}
+#endif
+#endif	/*  A__S  */
+
+#undef VAR_A
+#undef VAR_B
+}
+
+
+void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_Z) A__NAME(cpu, ic); }
+void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
+void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_C) A__NAME(cpu, ic); }
+void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); }
+void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_N) A__NAME(cpu, ic); }
+void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME(cpu, ic); }
+void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_V) A__NAME(cpu, ic); }
+void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME(cpu, ic); }
+
+#ifndef BLAHURG
+#define BLAHURG
+extern uint8_t condition_hi[16];
+extern uint8_t condition_ge[16];
+extern uint8_t condition_gt[16];
+#endif
+
+void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (condition_hi[cpu->cd.arm.flags]) A__NAME(cpu, ic); }
+void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!condition_hi[cpu->cd.arm.flags]) A__NAME(cpu, ic); }
+void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (condition_ge[cpu->cd.arm.flags]) A__NAME(cpu, ic); }
+void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!condition_ge[cpu->cd.arm.flags]) A__NAME(cpu, ic); }
+void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (condition_gt[cpu->cd.arm.flags]) A__NAME(cpu, ic); }
+void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!condition_gt[cpu->cd.arm.flags]) A__NAME(cpu, ic); }
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_arm_instr_dpi.cc gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr_dpi.cc
--- gxemul-0.6.2/src/cpus/cpu_arm_instr_dpi.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr_dpi.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,341 +0,0 @@
-/*
- *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  ARM Data Processing Instructions
- *  --------------------------------
- *
- *  xxxx000a aaaSnnnn ddddcccc ctttmmmm  Register form
- *  xxxx001a aaaSnnnn ddddrrrr bbbbbbbb  Immediate form
- *
- *  4 bits to select which instruction, one of the following:
- *
- *	0000	and		1000	tst
- *	0001	eor		1001	teq
- *	0010	sub		1010	cmp
- *	0011	rsb		1011	cmn
- *	0100	add		1100	orr
- *	0101	adc		1101	mov
- *	0110	sbc		1110	bic
- *	0111	rsc		1111	mvn
- *
- *  1 bit to select Status flag update.
- *
- *  1 bit to select Register form or Immediate form.
- *
- *  1 bit to select if the PC register is used.
- *
- *  Each function must also (as always) be repeated for each possible ARM
- *  condition code (15 in total).  Total: 1920 functions.
- *
- *  NOTE: This does not include any special common cases, which might be
- *        nice to have. Examples: comparing against zero, moving common
- *        constants.
- *
- *  See src/tools/generate_arm_dpi.c for more details.
- */
-
-
-#ifndef NOTHING
-#define NOTHING
-// Used to break out of dyntrans. TODO: Duplicate of arm_instr_nothing
-// code in tmp_arm_head.cc.
-void abortdyntrans(struct cpu* cpu, struct arm_instr_call* ic) { cpu->cd.arm.next_ic --; }
-static struct arm_instr_call abortdyntrans_call = { abortdyntrans, {0,0,0} };
-#endif	// NOTHING
-
-
-/*
- *  arg[0] = pointer to rn
- *  arg[1] = int32_t immediate value   OR  ptr to a reg_func() function
- *  arg[2] = pointer to rd
- */
-void A__NAME(struct cpu *cpu, struct arm_instr_call *ic)
-{
-#if defined(A__RSB) || defined(A__RSC)
-#define VAR_A  b
-#define VAR_B  a
-#else
-#define VAR_A  a
-#define VAR_B  b
-#endif
-
-#ifdef A__REG
-	uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *)
-	    = (uint32_t (*)(struct cpu *, struct arm_instr_call *))
-	      (void *)(size_t)ic->arg[1];
-#endif
-
-#ifdef A__S
-	uint32_t c32;
-#endif
-#if defined(A__CMP) || defined(A__CMN) || defined(A__ADC) || defined(A__ADD) \
- || defined(A__RSC) || defined(A__RSB) || defined(A__SBC) || defined(A__SUB)
-#ifdef A__S
-	uint64_t
-#else
-	uint32_t
-#endif
-#else
-	uint32_t
-#endif
-	    VAR_B =
-#ifdef A__REG
-	    reg_func(cpu, ic)
-#else
-#ifdef A__REGSHORT
-	    reg(ic->arg[1])
-#else
-	    ic->arg[1]
-#endif
-#endif
-	    , c64
-#if !defined(A__MOV) && !defined(A__MVN)
-	    , VAR_A = reg(ic->arg[0])
-#endif
-	    ;
-
-#if defined(A__MOV) || defined(A__MVN) || defined(A__TST) || defined(A__TEQ) \
- || defined(A__AND) || defined(A__BIC) || defined(A__EOR) || defined(A__ORR)
-#if !defined(A__REG) && !defined(A__REGSHORT) && defined(A__S)
-	/*
-	 *  TODO: This is not 100% correct, but should work with "recommended"
-	 *  ARM code: Immediate values larger than 255 are encoded with
-	 *  rotation. If the S-bit is set, then the carry bit is set to the
-	 *  highest bit of the operand.
-	 *
-	 *  TODO 2: Perhaps this check should be moved out from here, and into
-	 *  cpu_arm_instr.c. (More correct, and higher performance.)
-	 */
-	if (VAR_B > 255) {
-		if (VAR_B & 0x80000000)
-			cpu->cd.arm.flags |= ARM_F_C;
-		else
-			cpu->cd.arm.flags &= ~ARM_F_C;
-	}
-#endif
-#endif
-
-
-#if !defined(A__MOV) && !defined(A__MVN)
-#ifdef A__PC
-	if (ic->arg[0] == (size_t)&cpu->cd.arm.r[ARM_PC]) {
-		uint32_t low_pc = ((size_t)ic - (size_t)
-		    cpu->cd.arm.cur_ic_page) / sizeof(struct arm_instr_call);
-		VAR_A = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1)
-		    << ARM_INSTR_ALIGNMENT_SHIFT);
-		VAR_A += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT) + 8;
-	}
-#endif
-#endif
-
-	/*
-	 *  Perform the operation:
-	 */
-#if defined(A__AND) || defined(A__TST)
-	c64 = a & b;
-#endif
-#if defined(A__EOR) || defined(A__TEQ)
-	c64 = a ^ b;
-#endif
-#if defined(A__SUB) || defined(A__CMP) || defined(A__RSB)
-	c64 = a - b;
-#endif
-#if defined(A__ADD) || defined(A__CMN)
-	c64 = a + b;
-#endif
-#if defined(A__ADC)
-	c64 = a + b + (cpu->cd.arm.flags & ARM_F_C? 1 : 0);
-#endif
-#if defined(A__SBC) || defined(A__RSC)
-	c64 = a - b - (cpu->cd.arm.flags & ARM_F_C? 0 : 1);
-#endif
-#if defined(A__ORR)
-	c64 = a | b;
-#endif
-#if defined(A__MOV)
-	c64 = b;
-#endif
-#if defined(A__BIC)
-	c64 = a & ~b;
-#endif
-#if defined(A__MVN)
-	c64 = ~b;
-#endif
-
-
-#if defined(A__CMP) || defined(A__CMN) || defined(A__TST) || defined(A__TEQ)
-	/*  No write to rd for compare/test.  */
-#else
-#ifdef A__PC
-	if (ic->arg[2] == (size_t)&cpu->cd.arm.r[ARM_PC]) {
-#ifndef A__S
-		uint32_t old_pc = cpu->pc;
-		uint32_t mask_within_page = ((ARM_IC_ENTRIES_PER_PAGE-1)
-		    << ARM_INSTR_ALIGNMENT_SHIFT) |
-		    ((1 << ARM_INSTR_ALIGNMENT_SHIFT) - 1);
-#endif
-		cpu->pc = (uint32_t)c64;
-#ifdef A__S
-		/*  Copy the right SPSR into CPSR:  */
-		arm_save_register_bank(cpu);
-		switch (cpu->cd.arm.cpsr & ARM_FLAG_MODE) {
-		case ARM_MODE_FIQ32:
-			cpu->cd.arm.cpsr = cpu->cd.arm.spsr_fiq; break;
-		case ARM_MODE_IRQ32:
-			cpu->cd.arm.cpsr = cpu->cd.arm.spsr_irq; break;
-		case ARM_MODE_SVC32:
-			cpu->cd.arm.cpsr = cpu->cd.arm.spsr_svc; break;
-		case ARM_MODE_ABT32:
-			cpu->cd.arm.cpsr = cpu->cd.arm.spsr_abt; break;
-		case ARM_MODE_UND32:
-			cpu->cd.arm.cpsr = cpu->cd.arm.spsr_und; break;
-		}
-		cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28;
-		arm_load_register_bank(cpu);
-#else
-		if ((old_pc & ~mask_within_page) ==
-		    ((uint32_t)cpu->pc & ~mask_within_page)) {
-			cpu->cd.arm.next_ic = cpu->cd.arm.cur_ic_page +
-			    ((cpu->pc & mask_within_page) >>
-			    ARM_INSTR_ALIGNMENT_SHIFT);
-		} else
-#endif
-			quick_pc_to_pointers(cpu);
-
-		if (cpu->pc & 1) {
-			// Switch to THUMB and break out of the dyntrans loop.
-			cpu->cd.arm.cpsr |= ARM_FLAG_T;
-			cpu->cd.arm.next_ic = &abortdyntrans_call;
-		}
-		return;
-	} else
-		reg(ic->arg[2]) = c64;
-#else
-	reg(ic->arg[2]) = c64;
-#endif
-#endif
-
-
-	/*
-	 *  Status flag update (if the S-bit is set):
-	 */
-#ifdef A__S
-	c32 = c64;
-	cpu->cd.arm.flags
-#if defined(A__CMP) || defined(A__CMN) || defined(A__ADC) || defined(A__ADD) \
- || defined(A__RSB) || defined(A__RSC) || defined(A__SBC) || defined(A__SUB)
-	    &= ~(ARM_F_V | ARM_F_C | ARM_F_Z | ARM_F_N);
-#else
-	    &= ~(ARM_F_Z | ARM_F_N);
-#endif
-
-#if defined(A__CMP) || defined(A__RSB) || defined(A__SUB) || \
-    defined(A__RSC) || defined(A__SBC)
-	if ((uint32_t)a >= (uint32_t)b)
-		cpu->cd.arm.flags |= ARM_F_C;
-#else
-#if defined(A__ADC) || defined(A__ADD) || defined(A__CMN)
-	if (c32 != c64)
-		cpu->cd.arm.flags |= ARM_F_C;
-#endif
-#endif
-
-	if (c32 == 0)
-		cpu->cd.arm.flags |= ARM_F_Z;
-
-	if ((int32_t)c32 < 0)
-		cpu->cd.arm.flags |= ARM_F_N;
-
-	/*  Calculate the Overflow bit:  */
-#if defined(A__CMP) || defined(A__CMN) || defined(A__ADC) || defined(A__ADD) \
- || defined(A__RSB) || defined(A__RSC) || defined(A__SBC) || defined(A__SUB)
-	{
-		int v = 0;
-#if defined(A__ADD) || defined(A__CMN)
-		if (((int32_t)a >= 0 && (int32_t)b >= 0 &&
-		    (int32_t)c32 < 0) ||
-		    ((int32_t)a < 0 && (int32_t)b < 0 &&
-		    (int32_t)c32 >= 0))
-			v = 1;
-#else
-#if defined(A__SUB) || defined(A__RSB) || defined(A__CMP) || \
-    defined(A__RSC) || defined(A__SBC)
-		if (((int32_t)a >= 0 && (int32_t)b < 0 &&
-		    (int32_t)c32 < 0) ||
-		    ((int32_t)a < 0 && (int32_t)b >= 0 &&
-		    (int32_t)c32 >= 0))
-			v = 1;
-#endif
-#endif
-		if (v)
-			cpu->cd.arm.flags |= ARM_F_V;
-	}
-#endif
-#endif	/*  A__S  */
-
-#undef VAR_A
-#undef VAR_B
-}
-
-
-void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_Z) A__NAME(cpu, ic); }
-void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
-void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_C) A__NAME(cpu, ic); }
-void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); }
-void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_N) A__NAME(cpu, ic); }
-void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME(cpu, ic); }
-void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_V) A__NAME(cpu, ic); }
-void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME(cpu, ic); }
-
-#ifndef BLAHURG
-#define BLAHURG
-extern uint8_t condition_hi[16];
-extern uint8_t condition_ge[16];
-extern uint8_t condition_gt[16];
-#endif
-
-void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (condition_hi[cpu->cd.arm.flags]) A__NAME(cpu, ic); }
-void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!condition_hi[cpu->cd.arm.flags]) A__NAME(cpu, ic); }
-void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (condition_ge[cpu->cd.arm.flags]) A__NAME(cpu, ic); }
-void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!condition_ge[cpu->cd.arm.flags]) A__NAME(cpu, ic); }
-void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (condition_gt[cpu->cd.arm.flags]) A__NAME(cpu, ic); }
-void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!condition_gt[cpu->cd.arm.flags]) A__NAME(cpu, ic); }
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_arm_instr_loadstore.c gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr_loadstore.c
--- gxemul-0.6.2/src/cpus/cpu_arm_instr_loadstore.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr_loadstore.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,490 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  TODO:  Many things...
+ *
+ *	o)  Big-endian Double-Word loads/stores are likely INCORRECT.
+ *
+ *	o)  "Base Updated Abort Model", which updates the base register
+ *	    even if the memory access failed.
+ *
+ *	o)  Some ARM implementations use pc+8, some use pc+12 for stores?
+ *
+ *	o)  All load/store variants with the PC register are not really
+ *	    valid. (E.g. a byte load into the PC register. What should that
+ *	    accomplish?)
+ *
+ *	o)  Perhaps an optimization for the case when offset = 0, because
+ *	    that's quite common, and also when the Reg expression is just
+ *	    a simple, non-rotated register (0..14).
+ */
+
+
+#if defined(A__SIGNED) && !defined(A__H) && !defined(A__L)
+#define A__LDRD
+#endif
+#if defined(A__SIGNED) && defined(A__H) && !defined(A__L)
+#define A__STRD
+#endif
+
+
+#ifndef NOTHING_CALL
+#define NOTHING_CALL
+static struct arm_instr_call nothing_call = { arm_instr_nothing, {0,0,0} };
+#endif
+
+
+/*
+ *  General load/store, by using memory_rw(). If at all possible, memory_rw()
+ *  then inserts the page into the translation array, so that the fast
+ *  load/store routine below can be used for further accesses.
+ */
+void A__NAME__general(struct cpu *cpu, struct arm_instr_call *ic)
+{
+#if !defined(A__P) && defined(A__W)
+	const int memory_rw_flags = CACHE_DATA | MEMORY_USER_ACCESS;
+#else
+	const int memory_rw_flags = CACHE_DATA;
+#endif
+
+#ifdef A__REG
+	uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *)
+	    = (uint32_t (*)(struct cpu *, struct arm_instr_call *))
+	      (void *)(size_t)ic->arg[1];
+#endif
+
+#if defined(A__STRD) || defined(A__LDRD)
+	unsigned char data[8];
+	const int datalen = 8;
+#else
+#ifdef A__B
+	unsigned char data[1];
+	const int datalen = 1;
+#else
+#ifdef A__H
+	unsigned char data[2];
+	const int datalen = 2;
+#else
+	const int datalen = 4;
+#ifdef HOST_LITTLE_ENDIAN
+	unsigned char *data = (unsigned char *) ic->arg[2];
+#else
+	unsigned char data[4];
+#endif
+#endif
+#endif
+#endif
+
+	uint32_t addr, low_pc, offset =
+#ifndef A__U
+	    -
+#endif
+#ifdef A__REG
+	    reg_func(cpu, ic);
+#else
+	    ic->arg[1];
+#endif
+
+	low_pc = ((size_t)ic - (size_t)cpu->cd.arm.
+	    cur_ic_page) / sizeof(struct arm_instr_call);
+	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1)
+	    << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+
+	addr = reg(ic->arg[0])
+#ifdef A__P
+	    + offset
+#endif
+	    ;
+
+	addr &= ~(datalen - 1);
+
+#if defined(A__L) || defined(A__LDRD)
+	/*  Load:  */
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, datalen,
+	    MEM_READ, memory_rw_flags)) {
+		/*  load failed, an exception was generated  */
+		if (!cpu->running)
+			cpu->cd.arm.next_ic = &nothing_call;
+		return;
+	}
+#if defined(A__B) && !defined(A__LDRD)
+	reg(ic->arg[2]) =
+#ifdef A__SIGNED
+	    (int32_t)(int8_t)
+#endif
+	    data[0];
+#else
+#if defined(A__H) && !defined(A__LDRD)
+	reg(ic->arg[2]) =
+#ifdef A__SIGNED
+	    (int32_t)(int16_t)
+#endif
+	    (cpu->byte_order == EMUL_LITTLE_ENDIAN
+	    ? (data[0] + (data[1] << 8))
+	    : (data[1] + (data[0] << 8)));
+#else
+#ifndef A__LDRD
+	reg(ic->arg[2]) =
+		cpu->byte_order == EMUL_LITTLE_ENDIAN
+		? data[0] + (data[1] << 8) + (data[2] << 16) + (data[3] << 24)
+		: data[3] + (data[2] << 8) + (data[1] << 16) + (data[0] << 24);
+#else
+	// TODO: Double-check if this is correct
+	reg(ic->arg[2]) =
+		cpu->byte_order == EMUL_LITTLE_ENDIAN
+		? data[0] + (data[1] << 8) + (data[2] << 16) + (data[3] << 24)
+		: data[7] + (data[1] << 6) + (data[5] << 16) + (data[4] << 24);
+	reg(((uint32_t *)ic->arg[2]) + 1) =
+		cpu->byte_order == EMUL_LITTLE_ENDIAN
+		? data[4] + (data[5] << 8) + (data[6] << 16) + (data[7] << 24)
+		: data[0] + (data[1] << 8) + (data[2] << 16) + (data[3] << 24);
+#endif
+#endif
+#endif
+#else
+	/*  Store:  */
+#if !defined(A__B) && !defined(A__H) && defined(HOST_LITTLE_ENDIAN)
+#ifdef A__STRD
+	*(uint32_t *)data = reg(ic->arg[2]);
+	*(uint32_t *)(data + 4) = reg(ic->arg[2] + 4);
+#endif
+#else
+	int i = cpu->byte_order == EMUL_LITTLE_ENDIAN ? 0 : datalen - 1;
+	data[i] = reg(ic->arg[2]);
+	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
+#ifndef A__B
+	data[i] = reg(ic->arg[2]) >> 8;
+	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
+#if !defined(A__H) || defined(A__STRD)
+	data[i] = reg(ic->arg[2]) >> 16;
+	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
+	data[i] = reg(ic->arg[2]) >> 24;
+	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
+#ifdef A__STRD
+	// TODO: Double-check if this is correct
+	data[i] = reg(ic->arg[2] + 4);
+	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
+	data[i] = reg(ic->arg[2] + 4) >> 8;
+	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
+	data[i] = reg(ic->arg[2] + 4) >> 16;
+	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
+	data[i] = reg(ic->arg[2] + 4) >> 24;
+	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
+#endif
+#endif
+#endif
+#endif
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, datalen,
+	    MEM_WRITE, memory_rw_flags)) {
+		/*  store failed, an exception was generated  */
+		if (!cpu->running)
+			cpu->cd.arm.next_ic = &nothing_call;
+		return;
+	}
+#endif
+
+#ifdef A__P
+#ifdef A__W
+	reg(ic->arg[0]) = addr;
+#endif
+#else	/*  post-index writeback  */
+	reg(ic->arg[0]) = addr + offset;
+#endif
+}
+
+
+/*
+ *  Fast load/store, if the page is in the translation array.
+ */
+void A__NAME(struct cpu *cpu, struct arm_instr_call *ic)
+{
+#if defined(A__LDRD) || defined(A__STRD)
+	/*  Chicken out, let's do this unoptimized for now:  */
+	A__NAME__general(cpu, ic);
+#else
+#ifdef A__REG
+	uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *)
+	    = (uint32_t (*)(struct cpu *, struct arm_instr_call *))
+	      (void *)(size_t)ic->arg[1];
+#endif
+	uint32_t offset =
+#ifndef A__U
+	    -
+#endif
+#ifdef A__REG
+	    reg_func(cpu, ic);
+#else
+	    ic->arg[1];
+#endif
+	uint32_t addr = reg(ic->arg[0])
+#ifdef A__P
+	    + offset
+#endif
+	    ;
+	unsigned char *page = cpu->cd.arm.
+#ifdef A__L
+	    host_load
+#else
+	    host_store
+#endif
+	    [addr >> 12];
+
+
+#if !defined(A__P) && defined(A__W)
+	/*
+	 *  T-bit: userland access: check the corresponding bit in the
+	 *  is_userpage array. If it is set, then we're ok. Otherwise: use the
+	 *  generic function.
+	 */
+	uint32_t x = cpu->cd.arm.is_userpage[addr >> 17];
+	if (!(x & (1 << ((addr >> 12) & 31))))
+		A__NAME__general(cpu, ic);
+	else
+#endif
+
+
+	if (page == NULL) {
+		A__NAME__general(cpu, ic);
+	} else {
+#ifdef A__L
+#ifdef A__B
+		reg(ic->arg[2]) =
+#ifdef A__SIGNED
+		    (int32_t)(int8_t)
+#endif
+		    page[addr & 0xfff];
+#else
+#ifdef A__H
+		addr &= ~1;
+		reg(ic->arg[2]) =
+#ifdef A__SIGNED
+		    (int32_t)(int16_t)
+#endif
+		    (cpu->byte_order == EMUL_LITTLE_ENDIAN
+		    ? (page[addr & 0xfff] + (page[(addr & 0xfff) + 1] << 8))
+		    : ((page[addr & 0xfff] << 8) + page[(addr & 0xfff) + 1]));
+#else
+		addr &= ~3;
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			reg(ic->arg[2]) = page[addr & 0xfff] +
+			    (page[(addr & 0xfff) + 1] << 8) +
+			    (page[(addr & 0xfff) + 2] << 16) +
+			    (page[(addr & 0xfff) + 3] << 24);
+		else
+			reg(ic->arg[2]) = page[(addr & 0xfff) + 3] +
+			    (page[(addr & 0xfff) + 2] << 8) +
+			    (page[(addr & 0xfff) + 1] << 16) +
+			    (page[(addr & 0xfff) + 0] << 24);
+#endif
+#endif
+#else
+#ifdef A__B
+		page[addr & 0xfff] = reg(ic->arg[2]);
+#else
+#ifdef A__H
+		addr &= ~1;
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)  {
+			page[addr & 0xfff] = reg(ic->arg[2]);
+			page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8;
+		} else {
+			page[addr & 0xfff] = reg(ic->arg[2]) >> 8;
+			page[(addr & 0xfff)+1] = reg(ic->arg[2]);
+		}
+#else
+		addr &= ~3;
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)  {
+			page[addr & 0xfff] = reg(ic->arg[2]);
+			page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8;
+			page[(addr & 0xfff)+2] = reg(ic->arg[2]) >> 16;
+			page[(addr & 0xfff)+3] = reg(ic->arg[2]) >> 24;
+		} else {
+			page[addr & 0xfff] = reg(ic->arg[2]) >> 24;
+			page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 16;
+			page[(addr & 0xfff)+2] = reg(ic->arg[2]) >> 8;
+			page[(addr & 0xfff)+3] = reg(ic->arg[2]);
+		}
+#endif
+#endif
+#endif
+
+		/*  Index Write-back:  */
+#ifdef A__P
+#ifdef A__W
+		reg(ic->arg[0]) = addr;
+#endif
+#else
+		/*  post-index writeback  */
+		reg(ic->arg[0]) = addr + offset;
+#endif
+	}
+#endif	/*  not STRD  */
+}
+
+
+/*
+ *  Special case when loading or storing the ARM's PC register, or when the PC
+ *  register is used as the base address register.
+ *
+ *  o)	Loads into the PC register cause a branch. If an exception occured
+ *	during the load, then the PC register should already point to the
+ *	exception handler, in which case we simply recalculate the pointers a
+ *	second time (no harm is done by doing that).
+ *
+ *	TODO: A tiny performance optimization would be to separate the two
+ *	cases: a load where arg[0] = PC, and the case where arg[2] = PC.
+ *
+ *  o)	Stores store "PC of the current instruction + 12". The solution I have
+ *	choosen is to calculate this value and place it into a temporary
+ *	variable (tmp_pc), which is then used for the store.
+ */
+void A__NAME_PC(struct cpu *cpu, struct arm_instr_call *ic)
+{
+#ifdef A__L
+	/*  Load:  */
+	if (ic->arg[0] == (size_t)(&cpu->cd.arm.tmp_pc)) {
+		/*  tmp_pc = current PC + 8:  */
+		uint32_t low_pc, tmp;
+		low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) /
+		    sizeof(struct arm_instr_call);
+		tmp = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) <<
+		    ARM_INSTR_ALIGNMENT_SHIFT);
+		tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+		cpu->cd.arm.tmp_pc = tmp + 8;
+	}
+	A__NAME(cpu, ic);
+	if (ic->arg[2] == (size_t)(&cpu->cd.arm.r[ARM_PC])) {
+		cpu->pc = cpu->cd.arm.r[ARM_PC];
+		quick_pc_to_pointers(cpu);
+		if (cpu->machine->show_trace_tree)
+			cpu_functioncall_trace(cpu, cpu->pc);
+	}
+#else
+	/*  Store:  */
+	uint32_t low_pc, tmp;
+	/*  Calculate tmp from this instruction's PC + 12  */
+	low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) /
+	    sizeof(struct arm_instr_call);
+	tmp = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) <<
+	    ARM_INSTR_ALIGNMENT_SHIFT);
+	tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.arm.tmp_pc = tmp + 12;
+	A__NAME(cpu, ic);
+#endif
+}
+
+
+#ifndef A__NOCONDITIONS
+/*  Load/stores with all registers except the PC register:  */
+void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_Z) A__NAME(cpu, ic); }
+void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
+void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_C) A__NAME(cpu, ic); }
+void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); }
+void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_N) A__NAME(cpu, ic); }
+void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME(cpu, ic); }
+void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_V) A__NAME(cpu, ic); }
+void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME(cpu, ic); }
+
+void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_C &&
+!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
+void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_Z ||
+!(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); }
+void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
+((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME(cpu, ic); }
+void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
+((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME(cpu, ic); }
+void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
+((cpu->cd.arm.flags & ARM_F_V)?1:0) &&
+!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
+void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
+((cpu->cd.arm.flags & ARM_F_V)?1:0) ||
+(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
+
+
+/*  Load/stores with the PC register:  */
+void A__NAME_PC__eq(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_Z) A__NAME_PC(cpu, ic); }
+void A__NAME_PC__ne(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); }
+void A__NAME_PC__cs(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_C) A__NAME_PC(cpu, ic); }
+void A__NAME_PC__cc(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME_PC(cpu, ic); }
+void A__NAME_PC__mi(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_N) A__NAME_PC(cpu, ic); }
+void A__NAME_PC__pl(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME_PC(cpu, ic); }
+void A__NAME_PC__vs(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_V) A__NAME_PC(cpu, ic); }
+void A__NAME_PC__vc(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME_PC(cpu, ic); }
+
+void A__NAME_PC__hi(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_C &&
+!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); }
+void A__NAME_PC__ls(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (cpu->cd.arm.flags & ARM_F_Z ||
+!(cpu->cd.arm.flags & ARM_F_C)) A__NAME_PC(cpu, ic); }
+void A__NAME_PC__ge(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
+((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME_PC(cpu, ic); }
+void A__NAME_PC__lt(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
+((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME_PC(cpu, ic); }
+void A__NAME_PC__gt(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
+((cpu->cd.arm.flags & ARM_F_V)?1:0) &&
+!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); }
+void A__NAME_PC__le(struct cpu *cpu, struct arm_instr_call *ic)
+{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
+((cpu->cd.arm.flags & ARM_F_V)?1:0) ||
+(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); }
+#endif
+
+
+#ifdef A__LDRD
+#undef A__LDRD
+#endif
+
+#ifdef A__STRD
+#undef A__STRD
+#endif
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_arm_instr_loadstore.cc gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr_loadstore.cc
--- gxemul-0.6.2/src/cpus/cpu_arm_instr_loadstore.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr_loadstore.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,480 +0,0 @@
-/*
- *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  TODO:  Many things...
- *
- *	o)  Big-endian Double-Word loads/stores are likely INCORRECT.
- *
- *	o)  "Base Updated Abort Model", which updates the base register
- *	    even if the memory access failed.
- *
- *	o)  Some ARM implementations use pc+8, some use pc+12 for stores?
- *
- *	o)  All load/store variants with the PC register are not really
- *	    valid. (E.g. a byte load into the PC register. What should that
- *	    accomplish?)
- *
- *	o)  Perhaps an optimization for the case when offset = 0, because
- *	    that's quite common, and also when the Reg expression is just
- *	    a simple, non-rotated register (0..14).
- */
-
-
-#if defined(A__SIGNED) && !defined(A__H) && !defined(A__L)
-#define A__LDRD
-#endif
-#if defined(A__SIGNED) && defined(A__H) && !defined(A__L)
-#define A__STRD
-#endif
-
-
-/*
- *  General load/store, by using memory_rw(). If at all possible, memory_rw()
- *  then inserts the page into the translation array, so that the fast
- *  load/store routine below can be used for further accesses.
- */
-void A__NAME__general(struct cpu *cpu, struct arm_instr_call *ic)
-{
-#if !defined(A__P) && defined(A__W)
-	const int memory_rw_flags = CACHE_DATA | MEMORY_USER_ACCESS;
-#else
-	const int memory_rw_flags = CACHE_DATA;
-#endif
-
-#ifdef A__REG
-	uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *)
-	    = (uint32_t (*)(struct cpu *, struct arm_instr_call *))
-	      (void *)(size_t)ic->arg[1];
-#endif
-
-#if defined(A__STRD) || defined(A__LDRD)
-	unsigned char data[8];
-	const int datalen = 8;
-#else
-#ifdef A__B
-	unsigned char data[1];
-	const int datalen = 1;
-#else
-#ifdef A__H
-	unsigned char data[2];
-	const int datalen = 2;
-#else
-	const int datalen = 4;
-#ifdef HOST_LITTLE_ENDIAN
-	unsigned char *data = (unsigned char *) ic->arg[2];
-#else
-	unsigned char data[4];
-#endif
-#endif
-#endif
-#endif
-
-	uint32_t addr, low_pc, offset =
-#ifndef A__U
-	    -
-#endif
-#ifdef A__REG
-	    reg_func(cpu, ic);
-#else
-	    ic->arg[1];
-#endif
-
-	low_pc = ((size_t)ic - (size_t)cpu->cd.arm.
-	    cur_ic_page) / sizeof(struct arm_instr_call);
-	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1)
-	    << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-
-	addr = reg(ic->arg[0])
-#ifdef A__P
-	    + offset
-#endif
-	    ;
-
-	addr &= ~(datalen - 1);
-
-#if defined(A__L) || defined(A__LDRD)
-	/*  Load:  */
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, datalen,
-	    MEM_READ, memory_rw_flags)) {
-		/*  load failed, an exception was generated  */
-		return;
-	}
-#if defined(A__B) && !defined(A__LDRD)
-	reg(ic->arg[2]) =
-#ifdef A__SIGNED
-	    (int32_t)(int8_t)
-#endif
-	    data[0];
-#else
-#if defined(A__H) && !defined(A__LDRD)
-	reg(ic->arg[2]) =
-#ifdef A__SIGNED
-	    (int32_t)(int16_t)
-#endif
-	    (cpu->byte_order == EMUL_LITTLE_ENDIAN
-	    ? (data[0] + (data[1] << 8))
-	    : (data[1] + (data[0] << 8)));
-#else
-#ifndef A__LDRD
-	reg(ic->arg[2]) =
-		cpu->byte_order == EMUL_LITTLE_ENDIAN
-		? data[0] + (data[1] << 8) + (data[2] << 16) + (data[3] << 24)
-		: data[3] + (data[2] << 8) + (data[1] << 16) + (data[0] << 24);
-#else
-	// TODO: Double-check if this is correct
-	reg(ic->arg[2]) =
-		cpu->byte_order == EMUL_LITTLE_ENDIAN
-		? data[0] + (data[1] << 8) + (data[2] << 16) + (data[3] << 24)
-		: data[7] + (data[1] << 6) + (data[5] << 16) + (data[4] << 24);
-	reg(((uint32_t *)ic->arg[2]) + 1) =
-		cpu->byte_order == EMUL_LITTLE_ENDIAN
-		? data[4] + (data[5] << 8) + (data[6] << 16) + (data[7] << 24)
-		: data[0] + (data[1] << 8) + (data[2] << 16) + (data[3] << 24);
-#endif
-#endif
-#endif
-#else
-	/*  Store:  */
-#if !defined(A__B) && !defined(A__H) && defined(HOST_LITTLE_ENDIAN)
-#ifdef A__STRD
-	*(uint32_t *)data = reg(ic->arg[2]);
-	*(uint32_t *)(data + 4) = reg(ic->arg[2] + 4);
-#endif
-#else
-	int i = cpu->byte_order == EMUL_LITTLE_ENDIAN ? 0 : datalen - 1;
-	data[i] = reg(ic->arg[2]);
-	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
-#ifndef A__B
-	data[i] = reg(ic->arg[2]) >> 8;
-	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
-#if !defined(A__H) || defined(A__STRD)
-	data[i] = reg(ic->arg[2]) >> 16;
-	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
-	data[i] = reg(ic->arg[2]) >> 24;
-	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
-#ifdef A__STRD
-	// TODO: Double-check if this is correct
-	data[i] = reg(ic->arg[2] + 4);
-	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
-	data[i] = reg(ic->arg[2] + 4) >> 8;
-	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
-	data[i] = reg(ic->arg[2] + 4) >> 16;
-	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
-	data[i] = reg(ic->arg[2] + 4) >> 24;
-	i += cpu->byte_order == EMUL_LITTLE_ENDIAN ? 1 : -1;
-#endif
-#endif
-#endif
-#endif
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, datalen,
-	    MEM_WRITE, memory_rw_flags)) {
-		/*  store failed, an exception was generated  */
-		return;
-	}
-#endif
-
-#ifdef A__P
-#ifdef A__W
-	reg(ic->arg[0]) = addr;
-#endif
-#else	/*  post-index writeback  */
-	reg(ic->arg[0]) = addr + offset;
-#endif
-}
-
-
-/*
- *  Fast load/store, if the page is in the translation array.
- */
-void A__NAME(struct cpu *cpu, struct arm_instr_call *ic)
-{
-#if defined(A__LDRD) || defined(A__STRD)
-	/*  Chicken out, let's do this unoptimized for now:  */
-	A__NAME__general(cpu, ic);
-#else
-#ifdef A__REG
-	uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *)
-	    = (uint32_t (*)(struct cpu *, struct arm_instr_call *))
-	      (void *)(size_t)ic->arg[1];
-#endif
-	uint32_t offset =
-#ifndef A__U
-	    -
-#endif
-#ifdef A__REG
-	    reg_func(cpu, ic);
-#else
-	    ic->arg[1];
-#endif
-	uint32_t addr = reg(ic->arg[0])
-#ifdef A__P
-	    + offset
-#endif
-	    ;
-	unsigned char *page = cpu->cd.arm.
-#ifdef A__L
-	    host_load
-#else
-	    host_store
-#endif
-	    [addr >> 12];
-
-
-#if !defined(A__P) && defined(A__W)
-	/*
-	 *  T-bit: userland access: check the corresponding bit in the
-	 *  is_userpage array. If it is set, then we're ok. Otherwise: use the
-	 *  generic function.
-	 */
-	uint32_t x = cpu->cd.arm.is_userpage[addr >> 17];
-	if (!(x & (1 << ((addr >> 12) & 31))))
-		A__NAME__general(cpu, ic);
-	else
-#endif
-
-
-	if (page == NULL) {
-		A__NAME__general(cpu, ic);
-	} else {
-#ifdef A__L
-#ifdef A__B
-		reg(ic->arg[2]) =
-#ifdef A__SIGNED
-		    (int32_t)(int8_t)
-#endif
-		    page[addr & 0xfff];
-#else
-#ifdef A__H
-		addr &= ~1;
-		reg(ic->arg[2]) =
-#ifdef A__SIGNED
-		    (int32_t)(int16_t)
-#endif
-		    (cpu->byte_order == EMUL_LITTLE_ENDIAN
-		    ? (page[addr & 0xfff] + (page[(addr & 0xfff) + 1] << 8))
-		    : ((page[addr & 0xfff] << 8) + page[(addr & 0xfff) + 1]));
-#else
-		addr &= ~3;
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			reg(ic->arg[2]) = page[addr & 0xfff] +
-			    (page[(addr & 0xfff) + 1] << 8) +
-			    (page[(addr & 0xfff) + 2] << 16) +
-			    (page[(addr & 0xfff) + 3] << 24);
-		else
-			reg(ic->arg[2]) = page[(addr & 0xfff) + 3] +
-			    (page[(addr & 0xfff) + 2] << 8) +
-			    (page[(addr & 0xfff) + 1] << 16) +
-			    (page[(addr & 0xfff) + 0] << 24);
-#endif
-#endif
-#else
-#ifdef A__B
-		page[addr & 0xfff] = reg(ic->arg[2]);
-#else
-#ifdef A__H
-		addr &= ~1;
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)  {
-			page[addr & 0xfff] = reg(ic->arg[2]);
-			page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8;
-		} else {
-			page[addr & 0xfff] = reg(ic->arg[2]) >> 8;
-			page[(addr & 0xfff)+1] = reg(ic->arg[2]);
-		}
-#else
-		addr &= ~3;
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)  {
-			page[addr & 0xfff] = reg(ic->arg[2]);
-			page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8;
-			page[(addr & 0xfff)+2] = reg(ic->arg[2]) >> 16;
-			page[(addr & 0xfff)+3] = reg(ic->arg[2]) >> 24;
-		} else {
-			page[addr & 0xfff] = reg(ic->arg[2]) >> 24;
-			page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 16;
-			page[(addr & 0xfff)+2] = reg(ic->arg[2]) >> 8;
-			page[(addr & 0xfff)+3] = reg(ic->arg[2]);
-		}
-#endif
-#endif
-#endif
-
-		/*  Index Write-back:  */
-#ifdef A__P
-#ifdef A__W
-		reg(ic->arg[0]) = addr;
-#endif
-#else
-		/*  post-index writeback  */
-		reg(ic->arg[0]) = addr + offset;
-#endif
-	}
-#endif	/*  not STRD  */
-}
-
-
-/*
- *  Special case when loading or storing the ARM's PC register, or when the PC
- *  register is used as the base address register.
- *
- *  o)	Loads into the PC register cause a branch. If an exception occured
- *	during the load, then the PC register should already point to the
- *	exception handler, in which case we simply recalculate the pointers a
- *	second time (no harm is done by doing that).
- *
- *	TODO: A tiny performance optimization would be to separate the two
- *	cases: a load where arg[0] = PC, and the case where arg[2] = PC.
- *
- *  o)	Stores store "PC of the current instruction + 12". The solution I have
- *	choosen is to calculate this value and place it into a temporary
- *	variable (tmp_pc), which is then used for the store.
- */
-void A__NAME_PC(struct cpu *cpu, struct arm_instr_call *ic)
-{
-#ifdef A__L
-	/*  Load:  */
-	if (ic->arg[0] == (size_t)(&cpu->cd.arm.tmp_pc)) {
-		/*  tmp_pc = current PC + 8:  */
-		uint32_t low_pc, tmp;
-		low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) /
-		    sizeof(struct arm_instr_call);
-		tmp = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) <<
-		    ARM_INSTR_ALIGNMENT_SHIFT);
-		tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-		cpu->cd.arm.tmp_pc = tmp + 8;
-	}
-	A__NAME(cpu, ic);
-	if (ic->arg[2] == (size_t)(&cpu->cd.arm.r[ARM_PC])) {
-		cpu->pc = cpu->cd.arm.r[ARM_PC];
-		quick_pc_to_pointers(cpu);
-		if (cpu->machine->show_trace_tree)
-			cpu_functioncall_trace(cpu, cpu->pc);
-	}
-#else
-	/*  Store:  */
-	uint32_t low_pc, tmp;
-	/*  Calculate tmp from this instruction's PC + 12  */
-	low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) /
-	    sizeof(struct arm_instr_call);
-	tmp = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) <<
-	    ARM_INSTR_ALIGNMENT_SHIFT);
-	tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.arm.tmp_pc = tmp + 12;
-	A__NAME(cpu, ic);
-#endif
-}
-
-
-#ifndef A__NOCONDITIONS
-/*  Load/stores with all registers except the PC register:  */
-void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_Z) A__NAME(cpu, ic); }
-void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
-void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_C) A__NAME(cpu, ic); }
-void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); }
-void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_N) A__NAME(cpu, ic); }
-void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME(cpu, ic); }
-void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_V) A__NAME(cpu, ic); }
-void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME(cpu, ic); }
-
-void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_C &&
-!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
-void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_Z ||
-!(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); }
-void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
-((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME(cpu, ic); }
-void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
-((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME(cpu, ic); }
-void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
-((cpu->cd.arm.flags & ARM_F_V)?1:0) &&
-!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
-void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
-((cpu->cd.arm.flags & ARM_F_V)?1:0) ||
-(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
-
-
-/*  Load/stores with the PC register:  */
-void A__NAME_PC__eq(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_Z) A__NAME_PC(cpu, ic); }
-void A__NAME_PC__ne(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); }
-void A__NAME_PC__cs(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_C) A__NAME_PC(cpu, ic); }
-void A__NAME_PC__cc(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME_PC(cpu, ic); }
-void A__NAME_PC__mi(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_N) A__NAME_PC(cpu, ic); }
-void A__NAME_PC__pl(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME_PC(cpu, ic); }
-void A__NAME_PC__vs(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_V) A__NAME_PC(cpu, ic); }
-void A__NAME_PC__vc(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME_PC(cpu, ic); }
-
-void A__NAME_PC__hi(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_C &&
-!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); }
-void A__NAME_PC__ls(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (cpu->cd.arm.flags & ARM_F_Z ||
-!(cpu->cd.arm.flags & ARM_F_C)) A__NAME_PC(cpu, ic); }
-void A__NAME_PC__ge(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
-((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME_PC(cpu, ic); }
-void A__NAME_PC__lt(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
-((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME_PC(cpu, ic); }
-void A__NAME_PC__gt(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
-((cpu->cd.arm.flags & ARM_F_V)?1:0) &&
-!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); }
-void A__NAME_PC__le(struct cpu *cpu, struct arm_instr_call *ic)
-{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
-((cpu->cd.arm.flags & ARM_F_V)?1:0) ||
-(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); }
-#endif
-
-
-#ifdef A__LDRD
-#undef A__LDRD
-#endif
-
-#ifdef A__STRD
-#undef A__STRD
-#endif
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_arm_instr_misc.c gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr_misc.c
--- gxemul-0.6.2/src/cpus/cpu_arm_instr_misc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr_misc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,91 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Misc ARM instructions. Included from cpu_arm_instr.c.
+ */
+
+
+/*
+ *  clear_rX: Move #0 into a register. (Optimization hack.)
+ */
+X(clear_r0)  { cpu->cd.arm.r[ 0] = 0; } Y(clear_r0)
+X(clear_r1)  { cpu->cd.arm.r[ 1] = 0; } Y(clear_r1)
+X(clear_r2)  { cpu->cd.arm.r[ 2] = 0; } Y(clear_r2)
+X(clear_r3)  { cpu->cd.arm.r[ 3] = 0; } Y(clear_r3)
+X(clear_r4)  { cpu->cd.arm.r[ 4] = 0; } Y(clear_r4)
+X(clear_r5)  { cpu->cd.arm.r[ 5] = 0; } Y(clear_r5)
+X(clear_r6)  { cpu->cd.arm.r[ 6] = 0; } Y(clear_r6)
+X(clear_r7)  { cpu->cd.arm.r[ 7] = 0; } Y(clear_r7)
+X(clear_r8)  { cpu->cd.arm.r[ 8] = 0; } Y(clear_r8)
+X(clear_r9)  { cpu->cd.arm.r[ 9] = 0; } Y(clear_r9)
+X(clear_r10) { cpu->cd.arm.r[10] = 0; } Y(clear_r10)
+X(clear_r11) { cpu->cd.arm.r[11] = 0; } Y(clear_r11)
+X(clear_r12) { cpu->cd.arm.r[12] = 0; } Y(clear_r12)
+X(clear_r13) { cpu->cd.arm.r[13] = 0; } Y(clear_r13)
+X(clear_r14) { cpu->cd.arm.r[14] = 0; } Y(clear_r14)
+
+
+/*
+ *  mov1_rX: Move #1 into a register. (Optimization hack.)
+ */
+X(mov1_r0)  { cpu->cd.arm.r[ 0] = 1; } Y(mov1_r0)
+X(mov1_r1)  { cpu->cd.arm.r[ 1] = 1; } Y(mov1_r1)
+X(mov1_r2)  { cpu->cd.arm.r[ 2] = 1; } Y(mov1_r2)
+X(mov1_r3)  { cpu->cd.arm.r[ 3] = 1; } Y(mov1_r3)
+X(mov1_r4)  { cpu->cd.arm.r[ 4] = 1; } Y(mov1_r4)
+X(mov1_r5)  { cpu->cd.arm.r[ 5] = 1; } Y(mov1_r5)
+X(mov1_r6)  { cpu->cd.arm.r[ 6] = 1; } Y(mov1_r6)
+X(mov1_r7)  { cpu->cd.arm.r[ 7] = 1; } Y(mov1_r7)
+X(mov1_r8)  { cpu->cd.arm.r[ 8] = 1; } Y(mov1_r8)
+X(mov1_r9)  { cpu->cd.arm.r[ 9] = 1; } Y(mov1_r9)
+X(mov1_r10) { cpu->cd.arm.r[10] = 1; } Y(mov1_r10)
+X(mov1_r11) { cpu->cd.arm.r[11] = 1; } Y(mov1_r11)
+X(mov1_r12) { cpu->cd.arm.r[12] = 1; } Y(mov1_r12)
+X(mov1_r13) { cpu->cd.arm.r[13] = 1; } Y(mov1_r13)
+X(mov1_r14) { cpu->cd.arm.r[14] = 1; } Y(mov1_r14)
+
+
+/*
+ *  add1_rX: Add #1 to a register. (Optimization hack.)
+ */
+X(add1_r0)  { cpu->cd.arm.r[ 0] ++; } Y(add1_r0)
+X(add1_r1)  { cpu->cd.arm.r[ 1] ++; } Y(add1_r1)
+X(add1_r2)  { cpu->cd.arm.r[ 2] ++; } Y(add1_r2)
+X(add1_r3)  { cpu->cd.arm.r[ 3] ++; } Y(add1_r3)
+X(add1_r4)  { cpu->cd.arm.r[ 4] ++; } Y(add1_r4)
+X(add1_r5)  { cpu->cd.arm.r[ 5] ++; } Y(add1_r5)
+X(add1_r6)  { cpu->cd.arm.r[ 6] ++; } Y(add1_r6)
+X(add1_r7)  { cpu->cd.arm.r[ 7] ++; } Y(add1_r7)
+X(add1_r8)  { cpu->cd.arm.r[ 8] ++; } Y(add1_r8)
+X(add1_r9)  { cpu->cd.arm.r[ 9] ++; } Y(add1_r9)
+X(add1_r10) { cpu->cd.arm.r[10] ++; } Y(add1_r10)
+X(add1_r11) { cpu->cd.arm.r[11] ++; } Y(add1_r11)
+X(add1_r12) { cpu->cd.arm.r[12] ++; } Y(add1_r12)
+X(add1_r13) { cpu->cd.arm.r[13] ++; } Y(add1_r13)
+X(add1_r14) { cpu->cd.arm.r[14] ++; } Y(add1_r14)
+
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_arm_instr_misc.cc gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr_misc.cc
--- gxemul-0.6.2/src/cpus/cpu_arm_instr_misc.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_arm_instr_misc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,91 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Misc ARM instructions. Included from cpu_arm_instr.c.
- */
-
-
-/*
- *  clear_rX: Move #0 into a register. (Optimization hack.)
- */
-X(clear_r0)  { cpu->cd.arm.r[ 0] = 0; } Y(clear_r0)
-X(clear_r1)  { cpu->cd.arm.r[ 1] = 0; } Y(clear_r1)
-X(clear_r2)  { cpu->cd.arm.r[ 2] = 0; } Y(clear_r2)
-X(clear_r3)  { cpu->cd.arm.r[ 3] = 0; } Y(clear_r3)
-X(clear_r4)  { cpu->cd.arm.r[ 4] = 0; } Y(clear_r4)
-X(clear_r5)  { cpu->cd.arm.r[ 5] = 0; } Y(clear_r5)
-X(clear_r6)  { cpu->cd.arm.r[ 6] = 0; } Y(clear_r6)
-X(clear_r7)  { cpu->cd.arm.r[ 7] = 0; } Y(clear_r7)
-X(clear_r8)  { cpu->cd.arm.r[ 8] = 0; } Y(clear_r8)
-X(clear_r9)  { cpu->cd.arm.r[ 9] = 0; } Y(clear_r9)
-X(clear_r10) { cpu->cd.arm.r[10] = 0; } Y(clear_r10)
-X(clear_r11) { cpu->cd.arm.r[11] = 0; } Y(clear_r11)
-X(clear_r12) { cpu->cd.arm.r[12] = 0; } Y(clear_r12)
-X(clear_r13) { cpu->cd.arm.r[13] = 0; } Y(clear_r13)
-X(clear_r14) { cpu->cd.arm.r[14] = 0; } Y(clear_r14)
-
-
-/*
- *  mov1_rX: Move #1 into a register. (Optimization hack.)
- */
-X(mov1_r0)  { cpu->cd.arm.r[ 0] = 1; } Y(mov1_r0)
-X(mov1_r1)  { cpu->cd.arm.r[ 1] = 1; } Y(mov1_r1)
-X(mov1_r2)  { cpu->cd.arm.r[ 2] = 1; } Y(mov1_r2)
-X(mov1_r3)  { cpu->cd.arm.r[ 3] = 1; } Y(mov1_r3)
-X(mov1_r4)  { cpu->cd.arm.r[ 4] = 1; } Y(mov1_r4)
-X(mov1_r5)  { cpu->cd.arm.r[ 5] = 1; } Y(mov1_r5)
-X(mov1_r6)  { cpu->cd.arm.r[ 6] = 1; } Y(mov1_r6)
-X(mov1_r7)  { cpu->cd.arm.r[ 7] = 1; } Y(mov1_r7)
-X(mov1_r8)  { cpu->cd.arm.r[ 8] = 1; } Y(mov1_r8)
-X(mov1_r9)  { cpu->cd.arm.r[ 9] = 1; } Y(mov1_r9)
-X(mov1_r10) { cpu->cd.arm.r[10] = 1; } Y(mov1_r10)
-X(mov1_r11) { cpu->cd.arm.r[11] = 1; } Y(mov1_r11)
-X(mov1_r12) { cpu->cd.arm.r[12] = 1; } Y(mov1_r12)
-X(mov1_r13) { cpu->cd.arm.r[13] = 1; } Y(mov1_r13)
-X(mov1_r14) { cpu->cd.arm.r[14] = 1; } Y(mov1_r14)
-
-
-/*
- *  add1_rX: Add #1 to a register. (Optimization hack.)
- */
-X(add1_r0)  { cpu->cd.arm.r[ 0] ++; } Y(add1_r0)
-X(add1_r1)  { cpu->cd.arm.r[ 1] ++; } Y(add1_r1)
-X(add1_r2)  { cpu->cd.arm.r[ 2] ++; } Y(add1_r2)
-X(add1_r3)  { cpu->cd.arm.r[ 3] ++; } Y(add1_r3)
-X(add1_r4)  { cpu->cd.arm.r[ 4] ++; } Y(add1_r4)
-X(add1_r5)  { cpu->cd.arm.r[ 5] ++; } Y(add1_r5)
-X(add1_r6)  { cpu->cd.arm.r[ 6] ++; } Y(add1_r6)
-X(add1_r7)  { cpu->cd.arm.r[ 7] ++; } Y(add1_r7)
-X(add1_r8)  { cpu->cd.arm.r[ 8] ++; } Y(add1_r8)
-X(add1_r9)  { cpu->cd.arm.r[ 9] ++; } Y(add1_r9)
-X(add1_r10) { cpu->cd.arm.r[10] ++; } Y(add1_r10)
-X(add1_r11) { cpu->cd.arm.r[11] ++; } Y(add1_r11)
-X(add1_r12) { cpu->cd.arm.r[12] ++; } Y(add1_r12)
-X(add1_r13) { cpu->cd.arm.r[13] ++; } Y(add1_r13)
-X(add1_r14) { cpu->cd.arm.r[14] ++; } Y(add1_r14)
-
-
diff -Nru gxemul-0.6.2/src/cpus/cpu.c gxemul-0.7.0+dfsg/src/cpus/cpu.c
--- gxemul-0.6.2/src/cpus/cpu.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,576 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Common routines for CPU emulation. (Not specific to any CPU type.)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/types.h>
+#include <sys/mman.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "machine.h"
+#include "memory.h"
+#include "settings.h"
+#include "timer.h"
+
+
+extern size_t dyntrans_cache_size;
+
+static struct cpu_family *first_cpu_family = NULL;
+
+
+/*
+ *  cpu_new():
+ *
+ *  Create a new cpu object.  Each family is tried in sequence until a
+ *  CPU family recognizes the cpu_type_name.
+ *
+ *  If there was no match, NULL is returned. Otherwise, a pointer to an
+ *  initialized cpu struct is returned.
+ */
+struct cpu *cpu_new(struct memory *mem, struct machine *machine,
+        int cpu_id, char *name)
+{
+	char *cpu_type_name;
+	char tmpstr[30];
+
+	if (name == NULL) {
+		debugmsg(SUBSYS_CPU, "", VERBOSITY_ERROR, "cpu name = NULL?");
+		return NULL;
+	}
+
+	CHECK_ALLOCATION(cpu_type_name = strdup(name));
+
+	struct cpu *cpu = (struct cpu *) zeroed_alloc(sizeof(struct cpu));
+
+	CHECK_ALLOCATION(cpu->path = (char *) malloc(strlen(machine->path) + 15));
+	snprintf(cpu->path, strlen(machine->path) + 15,
+	    "%s.cpu[%i]", machine->path, cpu_id);
+
+	cpu->memory_rw  = NULL;
+	cpu->name       = cpu_type_name;
+	cpu->mem        = mem;
+	cpu->machine    = machine;
+	cpu->cpu_id     = cpu_id;
+	cpu->byte_order = EMUL_UNDEFINED_ENDIAN;
+	cpu->running    = 0;
+
+	/*  Create settings, and attach to the machine:  */
+	cpu->settings = settings_new();
+	snprintf(tmpstr, sizeof(tmpstr), "cpu[%i]", cpu_id);
+	settings_add(machine->settings, tmpstr, 1,
+	    SETTINGS_TYPE_SUBSETTINGS, 0, cpu->settings);
+
+	settings_add(cpu->settings, "name", 0, SETTINGS_TYPE_STRING,
+	    SETTINGS_FORMAT_STRING, (void *) &cpu->name);
+	settings_add(cpu->settings, "running", 0, SETTINGS_TYPE_UINT8,
+	    SETTINGS_FORMAT_YESNO, (void *) &cpu->running);
+
+	cpu_create_or_reset_tc(cpu);
+
+	struct cpu_family *fp = first_cpu_family;
+
+	while (fp != NULL) {
+		if (fp->cpu_new != NULL) {
+			if (fp->cpu_new(cpu, mem, machine, cpu_id, cpu_type_name))
+				break;
+		}
+
+		fp = fp->next;
+	}
+
+	if (fp == NULL) {
+		debugmsg(SUBSYS_CPU, "", VERBOSITY_ERROR,
+		    "unknown cpu type '%s'", cpu_type_name);
+		free(cpu);
+		return NULL;
+	}
+
+	cpu->cpu_family = fp;
+
+	if (cpu->memory_rw == NULL) {
+		debugmsg_cpu(cpu, SUBSYS_CPU, "", VERBOSITY_ERROR,
+		    "memory_rw == NULL");
+		free(cpu);
+		return NULL;
+	}
+
+	fp->init_tables(cpu);
+
+	if (cpu->byte_order == EMUL_UNDEFINED_ENDIAN) {
+		debugmsg_cpu(cpu, SUBSYS_CPU, "endianness", VERBOSITY_ERROR,
+		    "Internal bug: Endianness not set!");
+		free(cpu);
+		return NULL;
+	}
+	
+	if (cpu->vaddr_mask == 0) {
+		if (cpu->is_32bit)
+			cpu->vaddr_mask = 0x00000000ffffffffULL;
+		else
+			cpu->vaddr_mask = (int64_t)-1;
+
+		debugmsg_cpu(cpu, SUBSYS_CPU, "vaddr_mask", VERBOSITY_DEBUG,
+		    "Warning: vaddr_mask should be set in the CPU family's "
+		    "cpu_new()! Assuming 0x%16llx", (long long)cpu->vaddr_mask);
+	}
+
+	return cpu;
+}
+
+
+/*
+ *  cpu_destroy():
+ *
+ *  Destroy a cpu object.
+ */
+void cpu_destroy(struct cpu *cpu)
+{
+	settings_remove(cpu->settings, "name");
+	settings_remove(cpu->settings, "running");
+
+	/*  Remove any remaining level-1 settings:  */
+	settings_remove_all(cpu->settings);
+
+	settings_destroy(cpu->settings);
+
+	if (cpu->path != NULL)
+		free(cpu->path);
+
+	/*  TODO: This assumes that zeroed_alloc() actually succeeded
+	    with using mmap(), and not malloc()!  */
+	munmap((void *)cpu, sizeof(struct cpu));
+}
+
+
+/*
+ *  cpu_tlbdump():
+ *
+ *  Called from the debugger to dump the TLB in a readable format.
+ *  x is the cpu number to dump, or -1 to dump all CPUs.
+ *                                              
+ *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
+ *  just dumped.
+ */
+void cpu_tlbdump(struct cpu *cpu, int rawflag)
+{
+	if (cpu->cpu_family == NULL || cpu->cpu_family->tlbdump == NULL)
+		fatal("cpu_tlbdump(): NULL\n");
+	else
+		cpu->cpu_family->tlbdump(cpu, rawflag);
+}
+
+
+/*
+ *  cpu_disassemble_instr():
+ *
+ *  Convert an instruction word into human readable format, for instruction
+ *  tracing.
+ */
+int cpu_disassemble_instr(struct machine *m, struct cpu *cpu,
+	unsigned char *instr, int running, uint64_t addr)
+{
+	if (cpu->cpu_family == NULL || cpu->cpu_family->disassemble_instr == NULL) {
+		fatal("cpu_disassemble_instr(): NULL\n");
+		return 0;
+	} else
+		return cpu->cpu_family->disassemble_instr(cpu, instr,
+		    running, addr);
+}
+
+
+/*                       
+ *  cpu_register_dump():
+ *
+ *  Dump cpu registers in a relatively readable format.
+ *
+ *  gprs: set to non-zero to dump GPRs. (CPU dependent.)
+ *  coprocs: set bit 0..x to dump registers in coproc 0..x. (CPU dependent.)
+ */
+void cpu_register_dump(struct machine *m, struct cpu *cpu,
+	int gprs, int coprocs)
+{
+	if (cpu->cpu_family == NULL || cpu->cpu_family->register_dump == NULL)
+		fatal("cpu_register_dump(): NULL\n");
+	else
+		cpu->cpu_family->register_dump(cpu, gprs, coprocs);
+}
+
+
+/*
+ *  cpu_functioncall_trace():
+ *
+ *  This function should be called if machine->show_trace_tree is enabled, and
+ *  a function call is being made. f contains the address of the function.
+ */
+void cpu_functioncall_trace(struct cpu *cpu, uint64_t f)
+{
+	int show_symbolic_function_name = 1;
+	int i, n_args = -1;
+	char *symbol;
+	uint64_t offset;
+
+	/*  Special hack for M88K userspace:  */
+	if (cpu->cpu_family->arch == ARCH_M88K &&
+	    !(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE))
+		show_symbolic_function_name = 0;
+
+	if (cpu->machine->ncpus > 1)
+		fatal("cpu%i:\t", cpu->cpu_id);
+
+	if (cpu->trace_tree_depth > 100)
+		cpu->trace_tree_depth = 100;
+	for (i=0; i<cpu->trace_tree_depth; i++)
+		fatal("  ");
+
+	cpu->trace_tree_depth ++;
+
+	fatal("<");
+	symbol = get_symbol_name_and_n_args(&cpu->machine->symbol_context,
+	    f, &offset, &n_args);
+	if (symbol != NULL && show_symbolic_function_name && offset == 0)
+		fatal("%s", symbol);
+	else {
+		if (cpu->is_32bit)
+			fatal("0x%" PRIx32, (uint32_t) f);
+		else
+			fatal("0x%" PRIx64, (uint64_t) f);
+	}
+	fatal("(");
+
+	if (cpu->cpu_family->functioncall_trace != NULL)
+		cpu->cpu_family->functioncall_trace(cpu, n_args);
+
+	fatal(")>\n");
+}
+
+
+/*
+ *  cpu_functioncall_trace_return():
+ *
+ *  This function should be called if machine->show_trace_tree is enabled, and
+ *  a function is being returned from.
+ *
+ *  TODO: Print return value? This could be implemented similar to the
+ *  cpu->functioncall_trace function call above.
+ */
+void cpu_functioncall_trace_return(struct cpu *cpu)
+{
+	cpu->trace_tree_depth --;
+	if (cpu->trace_tree_depth < 0)
+		cpu->trace_tree_depth = 0;
+}
+
+
+/*
+ *  cpu_create_or_reset_tc():
+ *
+ *  Create the translation cache in memory (ie allocate memory for it), if
+ *  necessary, and then reset it to an initial state.
+ */
+void cpu_create_or_reset_tc(struct cpu *cpu)
+{
+	size_t s = dyntrans_cache_size + DYNTRANS_CACHE_MARGIN;
+
+	if (cpu->translation_cache == NULL)
+		cpu->translation_cache = (unsigned char *) zeroed_alloc(s);
+
+	/*  Create an empty table at the beginning of the translation cache:  */
+	memset(cpu->translation_cache, 0, sizeof(uint32_t)
+	    * N_BASE_TABLE_ENTRIES);
+
+	cpu->translation_cache_cur_ofs =
+	    N_BASE_TABLE_ENTRIES * sizeof(uint32_t);
+
+	/*
+	 *  There might be other translation pointers that still point to
+	 *  within the translation_cache region. Let's invalidate those too:
+	 */
+	if (cpu->invalidate_code_translation != NULL)
+		cpu->invalidate_code_translation(cpu, 0, INVALIDATE_ALL);
+}
+
+
+/*
+ *  cpu_dumpinfo():
+ *
+ *  Dumps info about a CPU using debug(). "cpu0: CPUNAME, running" (or similar)
+ *  is outputed, and it is up to CPU dependent code to complete the line.
+ */
+void cpu_dumpinfo(struct machine *m, struct cpu *cpu, bool verbose)
+{
+	char cpuname[100];
+	snprintf(cpuname, sizeof(cpuname), "cpu%i", cpu->cpu_id);
+
+	if (verbose)
+		debugmsg(SUBSYS_MACHINE, cpuname, VERBOSITY_INFO,
+		    "%s", cpu->running? "running" : "stopped");
+
+	if (cpu->cpu_family == NULL || cpu->cpu_family->dumpinfo == NULL) {
+		debugmsg(SUBSYS_MACHINE, cpuname, VERBOSITY_ERROR,
+		    "cpu_dumpinfo(): NULL");
+	} else {
+		if (verbose)
+			debug_indentation(1);
+
+		cpu->cpu_family->dumpinfo(cpu, verbose);
+
+		if (verbose)
+			debug_indentation(-1);
+	}
+}
+
+
+/*
+ *  cpu_list_available_types():
+ *
+ *  Print a list of available CPU types for each cpu family.
+ */
+void cpu_list_available_types(void)
+{
+	struct cpu_family *fp = first_cpu_family;
+
+	if (fp == NULL) {
+		debug("No CPUs defined!\n");
+		return;
+	}
+
+	while (fp != NULL) {
+		debug("%s:\n", fp->name);
+		debug_indentation(1);
+		if (fp->list_available_types != NULL)
+			fp->list_available_types();
+		else
+			debug("(internal error: list_available_types"
+			    " = NULL)\n");
+		debug_indentation(-1);
+
+		fp = fp->next;
+	}
+}
+
+
+/*
+ *  cpu_run_deinit():
+ *
+ *  Shuts down all CPUs in a machine when ending a simulation. (This function
+ *  should only need to be called once for each machine.)
+ */
+void cpu_run_deinit(struct machine *machine)
+{
+	int te;
+
+	/*
+	 *  Two last ticks of every hardware device.  This will allow e.g.
+	 *  framebuffers to draw the last updates to the screen before halting.
+	 *
+	 *  TODO: This should be refactored when redesigning the mainbus
+	 *        concepts!
+	 */
+        for (te=0; te<machine->tick_functions.n_entries; te++) {
+		machine->tick_functions.f[te](machine->cpus[0],
+		    machine->tick_functions.extra[te]);
+		machine->tick_functions.f[te](machine->cpus[0],
+		    machine->tick_functions.extra[te]);
+	}
+
+	if (machine->show_nr_of_instructions)
+		cpu_show_cycles(machine, true);
+
+	fflush(stdout);
+}
+
+
+/*
+ *  cpu_print_pc_indicator_in_disassembly():
+ *
+ *  Helper which shows an arrow indicating the current instruction, during
+ *  disassembly.
+ */
+void cpu_print_pc_indicator_in_disassembly(struct cpu *cpu, int running, uint64_t dumpaddr)
+{
+	if (!running && cpu->pc == dumpaddr) {
+		color_pc_indicator();
+		debug(" <- ");
+		color_normal();
+	} else {
+		debug("    ");
+	}
+}
+
+
+/*
+ *  cpu_show_cycles():
+ *
+ *  If show_nr_of_instructions is on, then print a line to stdout about how
+ *  many instructions/cycles have been executed so far.
+ */
+void cpu_show_cycles(struct machine *machine, bool forced)
+{
+	uint64_t offset, pc;
+	char *symbol;
+	int64_t mseconds, ninstrs, is, avg;
+	struct timeval tv;
+	struct cpu *cpu = machine->cpus[machine->bootstrap_cpu];
+
+	static int64_t mseconds_last = 0;
+	static int64_t ninstrs_last = -1;
+
+	pc = cpu->pc;
+
+	gettimeofday(&tv, NULL);
+	mseconds = (tv.tv_sec - cpu->starttime.tv_sec) * 1000
+	         + (tv.tv_usec - cpu->starttime.tv_usec) / 1000;
+
+	if (mseconds == 0)
+		mseconds = 1;
+
+	if (mseconds - mseconds_last == 0)
+		mseconds ++;
+
+	ninstrs = cpu->ninstrs_since_gettimeofday;
+
+	/*  RETURN here, unless show_nr_of_instructions (-N) is turned on:  */
+	if (!machine->show_nr_of_instructions && !forced)
+		goto do_return;
+
+	printf("[ %" PRIi64" instrs", (int64_t) cpu->ninstrs);
+
+	/*  Instructions per second, and average so far:  */
+	is = 1000 * (ninstrs-ninstrs_last) / (mseconds-mseconds_last);
+	avg = (long long)1000 * ninstrs / mseconds;
+	if (is < 0)
+		is = 0;
+	if (avg < 0)
+		avg = 0;
+
+	if (cpu->has_been_idling) {
+		printf("; idling");
+		cpu->has_been_idling = false;
+	} else
+		printf("; i/s=%" PRIi64" avg=%" PRIi64, is, avg);
+
+	symbol = get_symbol_name(&machine->symbol_context, pc, &offset);
+
+	if (machine->ncpus == 1) {
+		if (cpu->is_32bit)
+			printf("; pc=0x%08" PRIx32, (uint32_t) pc);
+		else
+			printf("; pc=0x%016" PRIx64, (uint64_t) pc);
+	}
+
+	/*  Special hack for M88K userland:  (Don't show symbols.)  */
+	if (cpu->cpu_family->arch == ARCH_M88K &&
+	    !(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE))
+		symbol = NULL;
+
+	if (symbol != NULL)
+		printf(" <%s>", symbol);
+	printf(" ]\n");
+
+do_return:
+	ninstrs_last = ninstrs;
+	mseconds_last = mseconds;
+}
+
+
+/*
+ *  cpu_run_init():
+ *
+ *  Prepare to run instructions on all CPUs in this machine. (This function
+ *  should only need to be called once for each machine.)
+ */
+void cpu_run_init(struct machine *machine)
+{
+	int i;
+
+	if (machine->ncpus == 0) {
+		printf("Machine with no CPUs? TODO.\n");
+		exit(1);
+	}
+
+	for (i=0; i<machine->ncpus; i++) {
+		struct cpu *cpu = machine->cpus[i];
+
+		cpu->ninstrs_flush = 0;
+		cpu->ninstrs = 0;
+		cpu->ninstrs_show = 0;
+
+		/*  For performance measurement:  */
+		gettimeofday(&cpu->starttime, NULL);
+		cpu->ninstrs_since_gettimeofday = 0;
+	}
+}
+
+
+/*
+ *  add_cpu_family():
+ *
+ *  Allocates a cpu_family struct and calls an init function for the
+ *  family to fill in reasonable data and pointers.
+ */
+static void add_cpu_family(void (*family_init)(struct cpu_family *), int arch)
+{
+	struct cpu_family *fp;
+
+	CHECK_ALLOCATION(fp = (struct cpu_family *) malloc(sizeof(struct cpu_family)));
+	memset(fp, 0, sizeof(struct cpu_family));
+
+	family_init(fp);
+
+	fp->arch = arch;
+	fp->next = NULL;
+
+	/*  Add last in family chain:  */
+	struct cpu_family* tmp = first_cpu_family;
+	if (tmp == NULL) {
+		first_cpu_family = fp;
+	} else {
+		while (tmp->next != NULL)
+			tmp = tmp->next;
+		tmp->next = fp;
+	}
+}
+
+
+/*
+ *  cpu_init():
+ *
+ *  Should be called before any other cpu_*() function.
+ *
+ *  This function calls add_cpu_family() for each processor architecture.
+ *  ADD_ALL_CPU_FAMILIES is defined in the config.h file generated by the
+ *  configure script.
+ */
+void cpu_init(void)
+{
+	ADD_ALL_CPU_FAMILIES;
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu.cc gxemul-0.7.0+dfsg/src/cpus/cpu.cc
--- gxemul-0.6.2/src/cpus/cpu.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,580 +0,0 @@
-/*
- *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Common routines for CPU emulation. (Not specific to any CPU type.)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/types.h>
-#include <sys/mman.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "machine.h"
-#include "memory.h"
-#include "settings.h"
-#include "timer.h"
-
-
-extern size_t dyntrans_cache_size;
-
-static struct cpu_family *first_cpu_family = NULL;
-
-
-/*
- *  cpu_new():
- *
- *  Create a new cpu object.  Each family is tried in sequence until a
- *  CPU family recognizes the cpu_type_name.
- *
- *  If there was no match, NULL is returned. Otherwise, a pointer to an
- *  initialized cpu struct is returned.
- */
-struct cpu *cpu_new(struct memory *mem, struct machine *machine,
-        int cpu_id, char *name)
-{
-	struct cpu *cpu;
-	struct cpu_family *fp;
-	char *cpu_type_name;
-	char tmpstr[30];
-
-	if (name == NULL) {
-		fprintf(stderr, "cpu_new(): cpu name = NULL?\n");
-		exit(1);
-	}
-
-	CHECK_ALLOCATION(cpu_type_name = strdup(name));
-
-	cpu = (struct cpu *) zeroed_alloc(sizeof(struct cpu));
-
-	CHECK_ALLOCATION(cpu->path = (char *) malloc(strlen(machine->path) + 15));
-	snprintf(cpu->path, strlen(machine->path) + 15,
-	    "%s.cpu[%i]", machine->path, cpu_id);
-
-	cpu->memory_rw  = NULL;
-	cpu->name       = cpu_type_name;
-	cpu->mem        = mem;
-	cpu->machine    = machine;
-	cpu->cpu_id     = cpu_id;
-	cpu->byte_order = EMUL_UNDEFINED_ENDIAN;
-	cpu->running    = 0;
-
-	/*  Create settings, and attach to the machine:  */
-	cpu->settings = settings_new();
-	snprintf(tmpstr, sizeof(tmpstr), "cpu[%i]", cpu_id);
-	settings_add(machine->settings, tmpstr, 1,
-	    SETTINGS_TYPE_SUBSETTINGS, 0, cpu->settings);
-
-	settings_add(cpu->settings, "name", 0, SETTINGS_TYPE_STRING,
-	    SETTINGS_FORMAT_STRING, (void *) &cpu->name);
-	settings_add(cpu->settings, "running", 0, SETTINGS_TYPE_UINT8,
-	    SETTINGS_FORMAT_YESNO, (void *) &cpu->running);
-
-	cpu_create_or_reset_tc(cpu);
-
-	fp = first_cpu_family;
-
-	while (fp != NULL) {
-		if (fp->cpu_new != NULL) {
-			if (fp->cpu_new(cpu, mem, machine, cpu_id,
-			    cpu_type_name)) {
-				/*  Sanity check:  */
-				if (cpu->memory_rw == NULL) {
-					fatal("\ncpu_new(): memory_rw == "
-					    "NULL\n");
-					exit(1);
-				}
-				break;
-			}
-		}
-
-		fp = fp->next;
-	}
-
-	if (fp == NULL) {
-		fatal("\ncpu_new(): unknown cpu type '%s'\n", cpu_type_name);
-		return NULL;
-	}
-
-	fp->init_tables(cpu);
-
-	if (cpu->byte_order == EMUL_UNDEFINED_ENDIAN) {
-		fatal("\ncpu_new(): Internal bug: Endianness not set.\n");
-		exit(1);
-	}
-	
-	if (cpu->vaddr_mask == 0) {
-		if (cpu->is_32bit)
-			cpu->vaddr_mask = 0x00000000ffffffffULL;
-		else
-			cpu->vaddr_mask = (int64_t)-1;
-
-		// debug("\n\ncpu_new(): Warning: vaddr_mask should be set in the CPU family's cpu_new()! Assuming 0x%16llx\n\n", (long long)cpu->vaddr_mask);
-	}
-
-	return cpu;
-}
-
-
-/*
- *  cpu_destroy():
- *
- *  Destroy a cpu object.
- */
-void cpu_destroy(struct cpu *cpu)
-{
-	settings_remove(cpu->settings, "name");
-	settings_remove(cpu->settings, "running");
-
-	/*  Remove any remaining level-1 settings:  */
-	settings_remove_all(cpu->settings);
-
-	settings_destroy(cpu->settings);
-
-	if (cpu->path != NULL)
-		free(cpu->path);
-
-	/*  TODO: This assumes that zeroed_alloc() actually succeeded
-	    with using mmap(), and not malloc()!  */
-	munmap((void *)cpu, sizeof(struct cpu));
-}
-
-
-/*
- *  cpu_tlbdump():
- *
- *  Called from the debugger to dump the TLB in a readable format.
- *  x is the cpu number to dump, or -1 to dump all CPUs.
- *                                              
- *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
- *  just dumped.
- */
-void cpu_tlbdump(struct machine *m, int x, int rawflag)
-{
-	if (m->cpu_family == NULL || m->cpu_family->tlbdump == NULL)
-		fatal("cpu_tlbdump(): NULL\n");
-	else
-		m->cpu_family->tlbdump(m, x, rawflag);
-}
-
-
-/*
- *  cpu_disassemble_instr():
- *
- *  Convert an instruction word into human readable format, for instruction
- *  tracing.
- */
-int cpu_disassemble_instr(struct machine *m, struct cpu *cpu,
-	unsigned char *instr, int running, uint64_t addr)
-{
-	if (m->cpu_family == NULL || m->cpu_family->disassemble_instr == NULL) {
-		fatal("cpu_disassemble_instr(): NULL\n");
-		return 0;
-	} else
-		return m->cpu_family->disassemble_instr(cpu, instr,
-		    running, addr);
-}
-
-
-/*                       
- *  cpu_register_dump():
- *
- *  Dump cpu registers in a relatively readable format.
- *
- *  gprs: set to non-zero to dump GPRs. (CPU dependent.)
- *  coprocs: set bit 0..x to dump registers in coproc 0..x. (CPU dependent.)
- */
-void cpu_register_dump(struct machine *m, struct cpu *cpu,
-	int gprs, int coprocs)
-{
-	if (m->cpu_family == NULL || m->cpu_family->register_dump == NULL)
-		fatal("cpu_register_dump(): NULL\n");
-	else
-		m->cpu_family->register_dump(cpu, gprs, coprocs);
-}
-
-
-/*
- *  cpu_functioncall_trace():
- *
- *  This function should be called if machine->show_trace_tree is enabled, and
- *  a function call is being made. f contains the address of the function.
- */
-void cpu_functioncall_trace(struct cpu *cpu, uint64_t f)
-{
-	int show_symbolic_function_name = 1;
-	int i, n_args = -1;
-	char *symbol;
-	uint64_t offset;
-
-	/*  Special hack for M88K userspace:  */
-	if (cpu->machine->arch == ARCH_M88K &&
-	    !(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE))
-		show_symbolic_function_name = 0;
-
-	if (cpu->machine->ncpus > 1)
-		fatal("cpu%i:\t", cpu->cpu_id);
-
-	if (cpu->trace_tree_depth > 100)
-		cpu->trace_tree_depth = 100;
-	for (i=0; i<cpu->trace_tree_depth; i++)
-		fatal("  ");
-
-	cpu->trace_tree_depth ++;
-
-	fatal("<");
-	symbol = get_symbol_name_and_n_args(&cpu->machine->symbol_context,
-	    f, &offset, &n_args);
-	if (symbol != NULL && show_symbolic_function_name && offset == 0)
-		fatal("%s", symbol);
-	else {
-		if (cpu->is_32bit)
-			fatal("0x%" PRIx32, (uint32_t) f);
-		else
-			fatal("0x%" PRIx64, (uint64_t) f);
-	}
-	fatal("(");
-
-	if (cpu->machine->cpu_family->functioncall_trace != NULL)
-		cpu->machine->cpu_family->functioncall_trace(cpu, n_args);
-
-	fatal(")>\n");
-
-#ifdef PRINT_MEMORY_CHECKSUM
-	/*  Temporary hack for finding bugs:  */
-	fatal("call chksum=%016" PRIx64"\n", memory_checksum(cpu->mem));
-#endif
-}
-
-
-/*
- *  cpu_functioncall_trace_return():
- *
- *  This function should be called if machine->show_trace_tree is enabled, and
- *  a function is being returned from.
- *
- *  TODO: Print return value? This could be implemented similar to the
- *  cpu->functioncall_trace function call above.
- */
-void cpu_functioncall_trace_return(struct cpu *cpu)
-{
-	cpu->trace_tree_depth --;
-	if (cpu->trace_tree_depth < 0)
-		cpu->trace_tree_depth = 0;
-}
-
-
-/*
- *  cpu_create_or_reset_tc():
- *
- *  Create the translation cache in memory (ie allocate memory for it), if
- *  necessary, and then reset it to an initial state.
- */
-void cpu_create_or_reset_tc(struct cpu *cpu)
-{
-	size_t s = dyntrans_cache_size + DYNTRANS_CACHE_MARGIN;
-
-	if (cpu->translation_cache == NULL)
-		cpu->translation_cache = (unsigned char *) zeroed_alloc(s);
-
-	/*  Create an empty table at the beginning of the translation cache:  */
-	memset(cpu->translation_cache, 0, sizeof(uint32_t)
-	    * N_BASE_TABLE_ENTRIES);
-
-	cpu->translation_cache_cur_ofs =
-	    N_BASE_TABLE_ENTRIES * sizeof(uint32_t);
-
-	/*
-	 *  There might be other translation pointers that still point to
-	 *  within the translation_cache region. Let's invalidate those too:
-	 */
-	if (cpu->invalidate_code_translation != NULL)
-		cpu->invalidate_code_translation(cpu, 0, INVALIDATE_ALL);
-}
-
-
-/*
- *  cpu_dumpinfo():
- *
- *  Dumps info about a CPU using debug(). "cpu0: CPUNAME, running" (or similar)
- *  is outputed, and it is up to CPU dependent code to complete the line.
- */
-void cpu_dumpinfo(struct machine *m, struct cpu *cpu)
-{
-	debug("cpu%i: %s, %s", cpu->cpu_id, cpu->name,
-	    cpu->running? "running" : "stopped");
-
-	if (m->cpu_family == NULL || m->cpu_family->dumpinfo == NULL)
-		fatal("cpu_dumpinfo(): NULL\n");
-	else
-		m->cpu_family->dumpinfo(cpu);
-}
-
-
-/*
- *  cpu_list_available_types():
- *
- *  Print a list of available CPU types for each cpu family.
- */
-void cpu_list_available_types(void)
-{
-	struct cpu_family *fp;
-	int iadd = DEBUG_INDENTATION;
-
-	fp = first_cpu_family;
-
-	if (fp == NULL) {
-		debug("No CPUs defined!\n");
-		return;
-	}
-
-	while (fp != NULL) {
-		debug("%s:\n", fp->name);
-		debug_indentation(iadd);
-		if (fp->list_available_types != NULL)
-			fp->list_available_types();
-		else
-			debug("(internal error: list_available_types"
-			    " = NULL)\n");
-		debug_indentation(-iadd);
-
-		fp = fp->next;
-	}
-}
-
-
-/*
- *  cpu_run_deinit():
- *
- *  Shuts down all CPUs in a machine when ending a simulation. (This function
- *  should only need to be called once for each machine.)
- */
-void cpu_run_deinit(struct machine *machine)
-{
-	int te;
-
-	/*
-	 *  Two last ticks of every hardware device.  This will allow e.g.
-	 *  framebuffers to draw the last updates to the screen before halting.
-	 *
-	 *  TODO: This should be refactored when redesigning the mainbus
-	 *        concepts!
-	 */
-        for (te=0; te<machine->tick_functions.n_entries; te++) {
-		machine->tick_functions.f[te](machine->cpus[0],
-		    machine->tick_functions.extra[te]);
-		machine->tick_functions.f[te](machine->cpus[0],
-		    machine->tick_functions.extra[te]);
-	}
-
-	if (machine->show_nr_of_instructions)
-		cpu_show_cycles(machine, 1);
-
-	fflush(stdout);
-}
-
-
-/*
- *  cpu_show_cycles():
- *
- *  If show_nr_of_instructions is on, then print a line to stdout about how
- *  many instructions/cycles have been executed so far.
- */
-void cpu_show_cycles(struct machine *machine, int forced)
-{
-	uint64_t offset, pc;
-	char *symbol;
-	int64_t mseconds, ninstrs, is, avg;
-	struct timeval tv;
-	struct cpu *cpu = machine->cpus[machine->bootstrap_cpu];
-
-	static int64_t mseconds_last = 0;
-	static int64_t ninstrs_last = -1;
-
-	pc = cpu->pc;
-
-	gettimeofday(&tv, NULL);
-	mseconds = (tv.tv_sec - cpu->starttime.tv_sec) * 1000
-	         + (tv.tv_usec - cpu->starttime.tv_usec) / 1000;
-
-	if (mseconds == 0)
-		mseconds = 1;
-
-	if (mseconds - mseconds_last == 0)
-		mseconds ++;
-
-	ninstrs = cpu->ninstrs_since_gettimeofday;
-
-	/*  RETURN here, unless show_nr_of_instructions (-N) is turned on:  */
-	if (!machine->show_nr_of_instructions && !forced)
-		goto do_return;
-
-	printf("[ %" PRIi64" instrs", (int64_t) cpu->ninstrs);
-
-	/*  Instructions per second, and average so far:  */
-	is = 1000 * (ninstrs-ninstrs_last) / (mseconds-mseconds_last);
-	avg = (long long)1000 * ninstrs / mseconds;
-	if (is < 0)
-		is = 0;
-	if (avg < 0)
-		avg = 0;
-
-	if (cpu->has_been_idling) {
-		printf("; idling");
-		cpu->has_been_idling = 0;
-	} else
-		printf("; i/s=%" PRIi64" avg=%" PRIi64, is, avg);
-
-	symbol = get_symbol_name(&machine->symbol_context, pc, &offset);
-
-	if (machine->ncpus == 1) {
-		if (cpu->is_32bit)
-			printf("; pc=0x%08" PRIx32, (uint32_t) pc);
-		else
-			printf("; pc=0x%016" PRIx64, (uint64_t) pc);
-	}
-
-	/*  Special hack for M88K userland:  (Don't show symbols.)  */
-	if (cpu->machine->arch == ARCH_M88K &&
-	    !(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE))
-		symbol = NULL;
-
-	if (symbol != NULL)
-		printf(" <%s>", symbol);
-	printf(" ]\n");
-
-do_return:
-	ninstrs_last = ninstrs;
-	mseconds_last = mseconds;
-}
-
-
-/*
- *  cpu_run_init():
- *
- *  Prepare to run instructions on all CPUs in this machine. (This function
- *  should only need to be called once for each machine.)
- */
-void cpu_run_init(struct machine *machine)
-{
-	int i;
-
-	if (machine->ncpus == 0) {
-		printf("Machine with no CPUs? TODO.\n");
-		exit(1);
-	}
-
-	for (i=0; i<machine->ncpus; i++) {
-		struct cpu *cpu = machine->cpus[i];
-
-		cpu->ninstrs_flush = 0;
-		cpu->ninstrs = 0;
-		cpu->ninstrs_show = 0;
-
-		/*  For performance measurement:  */
-		gettimeofday(&cpu->starttime, NULL);
-		cpu->ninstrs_since_gettimeofday = 0;
-	}
-}
-
-
-/*
- *  add_cpu_family():
- *
- *  Allocates a cpu_family struct and calls an init function for the
- *  family to fill in reasonable data and pointers.
- */
-static void add_cpu_family(int (*family_init)(struct cpu_family *), int arch)
-{
-	struct cpu_family *fp, *tmp;
-	int res;
-
-	CHECK_ALLOCATION(fp = (struct cpu_family *) malloc(sizeof(struct cpu_family)));
-	memset(fp, 0, sizeof(struct cpu_family));
-
-	/*
-	 *  family_init() returns 1 if the struct has been filled with
-	 *  valid data, 0 if suppor for the cpu family isn't compiled
-	 *  into the emulator.
-	 */
-	res = family_init(fp);
-	if (!res) {
-		free(fp);
-		return;
-	}
-	fp->arch = arch;
-	fp->next = NULL;
-
-	/*  Add last in family chain:  */
-	tmp = first_cpu_family;
-	if (tmp == NULL) {
-		first_cpu_family = fp;
-	} else {
-		while (tmp->next != NULL)
-			tmp = tmp->next;
-		tmp->next = fp;
-	}
-}
-
-
-/*
- *  cpu_family_ptr_by_number():
- *
- *  Returns a pointer to a CPU family based on the ARCH_* integers.
- */
-struct cpu_family *cpu_family_ptr_by_number(int arch)
-{
-	struct cpu_family *fp;
-	fp = first_cpu_family;
-
-	/*  YUCK! This is too hardcoded! TODO  */
-
-	while (fp != NULL) {
-		if (arch == fp->arch)
-			return fp;
-		fp = fp->next;
-	}
-
-	return NULL;
-}
-
-
-/*
- *  cpu_init():
- *
- *  Should be called before any other cpu_*() function.
- *
- *  This function calls add_cpu_family() for each processor architecture.
- *  ADD_ALL_CPU_FAMILIES is defined in the config.h file generated by the
- *  configure script.
- */
-void cpu_init(void)
-{
-	ADD_ALL_CPU_FAMILIES;
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_dyntrans.c gxemul-0.7.0+dfsg/src/cpus/cpu_dyntrans.c
--- gxemul-0.6.2/src/cpus/cpu_dyntrans.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_dyntrans.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1997 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Common dyntrans routines. Included from cpu_*.c.
+ *
+ *  Note: This might be a bit hard to follow, if you are reading this source
+ *  code for the first time. It is basically a hack to implement "templates"
+ *  with normal C code, by using suitable defines/macros, and then including
+ *  this file.
+ */
+
+
+#ifndef STATIC_STUFF
+#define	STATIC_STUFF
+/*
+ *  gather_statistics():
+ */
+static void gather_statistics(struct cpu *cpu)
+{
+	char ch, buf[60];
+	struct DYNTRANS_IC *ic = cpu->cd.DYNTRANS_ARCH.next_ic;
+	int i = 0;
+	uint64_t a;
+	int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - (size_t)
+	    cpu->cd.DYNTRANS_ARCH.cur_ic_page) / sizeof(struct DYNTRANS_IC);
+
+	if (cpu->machine->statistics.file == NULL) {
+		fatal("statistics gathering with no filename set is"
+		    " meaningless\n");
+		return;
+	}
+
+	/*  low_pc must be within the page!  */
+	if (low_pc < 0 || low_pc > DYNTRANS_IC_ENTRIES_PER_PAGE)
+		return;
+
+	buf[0] = '\0';
+
+	while ((ch = cpu->machine->statistics.fields[i]) != '\0') {
+		if (i != 0)
+			strlcat(buf, " ", sizeof(buf));
+
+		switch (ch) {
+		case 'i':
+			snprintf(buf + strlen(buf), sizeof(buf),
+			    "%p", (void *)ic->f);
+			break;
+		case 'p':
+			/*  Physical program counter address:  */
+			cpu->cd.DYNTRANS_ARCH.cur_physpage = (struct DYNTRANS_TC_PHYSPAGE *)
+			    cpu->cd.DYNTRANS_ARCH.cur_ic_page;
+			a = cpu->cd.DYNTRANS_ARCH.cur_physpage->physaddr;
+			a &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) <<
+			    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
+			a += low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT;
+			if (cpu->is_32bit)
+				snprintf(buf + strlen(buf), sizeof(buf),
+				    "0x%08" PRIx32, (uint32_t)a);
+			else
+				snprintf(buf + strlen(buf), sizeof(buf),
+				    "0x%016" PRIx64, (uint64_t)a);
+			break;
+		case 'v':
+			/*  Virtual program counter address:  */
+			a = cpu->pc;
+			a &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) <<
+			    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
+			a += low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT;
+			if (cpu->is_32bit)
+				snprintf(buf + strlen(buf), sizeof(buf),
+				    "0x%08" PRIx32, (uint32_t)a);
+			else
+				snprintf(buf + strlen(buf), sizeof(buf),
+				    "0x%016" PRIx64, (uint64_t)a);
+			break;
+		}
+		i++;
+	}
+
+	fprintf(cpu->machine->statistics.file, "%s\n", buf);
+}
+
+
+#define S		gather_statistics(cpu)
+
+
+#if 1
+
+/*  The normal instruction execution core:  */
+#define I	ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; ic->f(cpu, ic);
+
+#else
+
+/*  For heavy debugging:  */
+#define I	ic = cpu->cd.DYNTRANS_ARCH.next_ic ++;	\
+		{	\
+			int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - \
+			    (size_t)cpu->cd.DYNTRANS_ARCH.cur_ic_page) / \
+			    sizeof(struct DYNTRANS_IC);			\
+			printf("cur_ic_page=%p ic=%p (low_pc=0x%x)\n",	\
+			    cpu->cd.DYNTRANS_ARCH.cur_ic_page,		\
+			    ic, low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT); \
+		} \
+		ic->f(cpu, ic);
+
+#endif
+
+/*  static long long nr_of_I_calls = 0;  */
+
+/*  Temporary hack for finding NULL bugs:  */
+/*  #define I	ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; 			\
+		nr_of_I_calls ++;					\
+		if (ic->f == NULL) {					\
+			int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - \
+			    (size_t)cpu->cd.DYNTRANS_ARCH.cur_ic_page) / \
+			    sizeof(struct DYNTRANS_IC);			\
+			cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << \
+			    DYNTRANS_INSTR_ALIGNMENT_SHIFT);		\
+			cpu->pc += (low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT);\
+			printf("Crash at %016" PRIx64"\n", cpu->pc);	\
+			printf("nr of I calls: %lli\n", nr_of_I_calls);	\
+			printf("Next ic = %p\n", cpu->cd.		\
+				DYNTRANS_ARCH.next_ic);			\
+			printf("cur ic page = %p\n", cpu->cd.		\
+				DYNTRANS_ARCH.cur_ic_page);		\
+			cpu->running = 0;				\
+			return 0;					\
+		}							\
+		ic->f(cpu, ic);  */
+
+/*  Temporary hack for MIPS, to hunt for 32-bit/64-bit sign-extension bugs:  */
+/*  #define I		{ int k; for (k=1; k<=31; k++)	\
+	cpu->cd.mips.gpr[k] = (int32_t)cpu->cd.mips.gpr[k];\
+	if (cpu->cd.mips.gpr[0] != 0) {			\
+		fatal("NOOOOOO\n"); exit(1);		\
+	}						\
+	ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; ic->f(cpu, ic); }
+*/
+#endif	/*  STATIC STUFF  */
+
+
+
+#ifdef	DYNTRANS_RUN_INSTR_DEF
+/*
+ *  XXX_run_instr():
+ *
+ *  Execute one or more instructions on a specific CPU, using dyntrans.
+ *  (For dualmode archs, this function is included twice.)
+ *
+ *  Return value is the number of instructions executed during this call,
+ *  0 if no instructions were executed.
+ */
+int DYNTRANS_RUN_INSTR_DEF(struct cpu *cpu)
+{
+	MODE_uint_t cached_pc;
+	int low_pc, n_instrs;
+
+	/*  Ugly... fix this some day.  */
+#ifdef DYNTRANS_DUALMODE_32
+#ifdef MODE32
+	DYNTRANS_PC_TO_POINTERS32(cpu);
+#else
+	DYNTRANS_PC_TO_POINTERS(cpu);
+#endif
+#else
+	DYNTRANS_PC_TO_POINTERS(cpu);
+#endif
+
+	cpu->wants_to_idle = false;
+
+	/*
+	 *  Interrupt assertion?  (This is _below_ the initial PC to pointer
+	 *  conversion; if the conversion caused an exception of some kind
+	 *  then interrupts are probably disabled, and the exception will get
+	 *  priority over device interrupts.)
+	 *
+	 *  TODO: Turn this into a family-specific function somewhere...
+ 	 */
+
+	/*  Note: Do not cause interrupts while single-stepping. It is
+	    so horribly annoying.  */
+	if (!single_step) {
+#ifdef DYNTRANS_ARM
+		if (cpu->cd.arm.irq_asserted && !(cpu->cd.arm.cpsr & ARM_FLAG_I))
+			arm_exception(cpu, ARM_EXCEPTION_IRQ);
+#endif
+#ifdef DYNTRANS_M88K
+		if (cpu->cd.m88k.irq_asserted &&
+		    !(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_IND))
+			m88k_exception(cpu, M88K_EXCEPTION_INTERRUPT, 0);
+#endif
+#ifdef DYNTRANS_MIPS
+		int enabled, mask;
+		int status = cpu->cd.mips.coproc[0]->reg[COP0_STATUS];
+		if (cpu->cd.mips.cpu_type.exc_model == EXC3K) {
+			/*  R3000:  */
+			enabled = status & MIPS_SR_INT_IE;
+		} else {
+			/*  R4000 and others:  */
+			enabled = (status & STATUS_IE)
+			    && !(status & STATUS_EXL) && !(status & STATUS_ERL);
+			/*  Special case for R5900/C790/TX79:  */
+			if (cpu->cd.mips.cpu_type.rev == MIPS_R5900 &&
+			    !(status & R5900_STATUS_EIE))
+				enabled = 0;
+		}
+		mask = status & cpu->cd.mips.coproc[0]->reg[COP0_CAUSE]
+		    & STATUS_IM_MASK;
+
+		if (enabled && mask)
+			mips_cpu_exception(cpu, EXCEPTION_INT, 0, 0, 0, 0, 0,0);
+#endif
+#ifdef DYNTRANS_PPC
+		if (cpu->cd.ppc.dec_intr_pending && cpu->cd.ppc.msr & PPC_MSR_EE) {
+			if (!(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC))
+				ppc_exception(cpu, PPC_EXCEPTION_DEC);
+			cpu->cd.ppc.dec_intr_pending = 0;
+		}
+		if (cpu->cd.ppc.irq_asserted && cpu->cd.ppc.msr & PPC_MSR_EE)
+			ppc_exception(cpu, PPC_EXCEPTION_EI);
+#endif
+#ifdef DYNTRANS_SH
+		if (cpu->cd.sh.int_to_assert > 0 && !(cpu->cd.sh.sr & SH_SR_BL)
+		    && ((cpu->cd.sh.sr & SH_SR_IMASK) >> SH_SR_IMASK_SHIFT)
+		    < cpu->cd.sh.int_level)
+			sh_exception(cpu, 0, cpu->cd.sh.int_to_assert, 0);
+#endif
+	}
+
+#ifdef DYNTRANS_ARM
+	if (cpu->cd.arm.cpsr & ARM_FLAG_T) {
+		// fatal("THUMB execution not implemented.\n");
+		// cpu->running = false;
+		// return 0;
+		
+		arm_cpu_interpret_thumb_SLOW(cpu);
+		return 1;
+	}
+#endif
+
+	cached_pc = cpu->pc;
+
+	cpu->n_translated_instrs = 0;
+
+	cpu->cd.DYNTRANS_ARCH.cur_physpage = (struct DYNTRANS_TC_PHYSPAGE *)
+	    cpu->cd.DYNTRANS_ARCH.cur_ic_page;
+
+	if (single_step || cpu->machine->instruction_trace
+	    || cpu->machine->register_dump) {
+		/*
+		 *  Single-step:
+		 */
+		struct DYNTRANS_IC *ic = cpu->cd.DYNTRANS_ARCH.next_ic;
+		if (cpu->machine->register_dump) {
+			debug("\n");
+			cpu_register_dump(cpu->machine, cpu, 1, 0x1);
+		}
+		if (single_step || cpu->machine->instruction_trace) {
+			/*  TODO/Note: This must be large enough to hold
+			    any instruction for any ISA:  */
+			unsigned char instr[1 <<
+			    DYNTRANS_INSTR_ALIGNMENT_SHIFT];
+			if (!cpu->memory_rw(cpu, cpu->mem, cached_pc, &instr[0],
+			    sizeof(instr), MEM_READ, CACHE_INSTRUCTION)) {
+				fatal("XXX_run_instr(): could not read "
+				    "the instruction\n");
+			} else {
+#ifdef DYNTRANS_DELAYSLOT
+				int len =
+#endif
+				    cpu_disassemble_instr(
+				    cpu->machine, cpu, instr, 1, cpu->pc);
+#ifdef DYNTRANS_DELAYSLOT
+				/*  Show the instruction in the delay slot,
+				    if any:  */
+				if (cpu->instruction_has_delayslot == NULL)
+					fatal("WARNING: ihd func not yet"
+					    " implemented?\n");
+				else if (cpu->instruction_has_delayslot(cpu,
+				    instr)) {
+					int saved_delayslot = cpu->delay_slot;
+					cpu->memory_rw(cpu, cpu->mem, cached_pc
+					    + len, &instr[0],
+					    sizeof(instr), MEM_READ,
+					    CACHE_INSTRUCTION);
+					cpu->delay_slot = DELAYED;
+					cpu->pc += len;
+					cpu_disassemble_instr(cpu->machine,
+					    cpu, instr, 1, cpu->pc);
+					cpu->delay_slot = saved_delayslot;
+					cpu->pc -= len;
+				}
+#endif
+			}
+		}
+
+		if (cpu->machine->statistics.enabled)
+			S;
+
+		/*  Execute just one instruction:  */
+		I;
+
+		n_instrs = 1;
+	} else if (cpu->machine->statistics.enabled) {
+		/*  Gather statistics while executing multiple instructions:  */
+		n_instrs = 0;
+		for (;;) {
+			struct DYNTRANS_IC *ic;
+
+			S; I; S; I; S; I; S; I; S; I; S; I;
+			S; I; S; I; S; I; S; I; S; I; S; I;
+			S; I; S; I; S; I; S; I; S; I; S; I;
+			S; I; S; I; S; I; S; I; S; I; S; I;
+
+			cpu->n_translated_instrs += 24;
+			if (cpu->n_translated_instrs >= N_SAFE_DYNTRANS_LIMIT)
+				break;
+		}
+	} else {
+		/*
+		 *  Execute multiple instructions:
+		 *
+		 *  (This is the core dyntrans loop.)
+		 */
+		n_instrs = 0;
+
+		for (;;) {
+			struct DYNTRANS_IC *ic;
+
+			I; I; I; I; I;   I; I; I; I; I;
+			I; I; I; I; I;   I; I; I; I; I;
+			I; I; I; I; I;   I; I; I; I; I;
+			I; I; I; I; I;   I; I; I; I; I;
+			I; I; I; I; I;   I; I; I; I; I;
+
+			I; I; I; I; I;   I; I; I; I; I;
+
+			I; I; I; I; I;   I; I; I; I; I;
+			I; I; I; I; I;   I; I; I; I; I;
+			I; I; I; I; I;   I; I; I; I; I;
+			I; I; I; I; I;   I; I; I; I; I;
+			I; I; I; I; I;   I; I; I; I; I;
+
+			I; I; I; I; I;   I; I; I; I; I;
+
+			cpu->n_translated_instrs += 120;
+			if (cpu->n_translated_instrs >= N_SAFE_DYNTRANS_LIMIT)
+				break;
+		}
+	}
+
+	if (cpu->wants_to_idle) {
+		cpu->n_translated_instrs -= N_DYNTRANS_IDLE_BREAK;
+
+		// TODO: More arch specific interrupt checks
+		if (false
+#ifdef DYNTRANS_M88K
+		    || (cpu->cd.m88k.irq_asserted && !(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_IND))
+#endif
+		    ) {
+			debugmsg_cpu(cpu, SUBSYS_CPU, "idle", VERBOSITY_DEBUG, "not idling; exception");
+			cpu->wants_to_idle = false;
+		}
+
+		cpu->has_been_idling = true;
+	}
+
+	n_instrs += cpu->n_translated_instrs;
+
+	/*  Synchronize the program counter:  */
+	low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - (size_t)
+	    cpu->cd.DYNTRANS_ARCH.cur_ic_page) / sizeof(struct DYNTRANS_IC);
+	if (low_pc >= 0 && low_pc < DYNTRANS_IC_ENTRIES_PER_PAGE) {
+		cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) <<
+		    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT);
+	} else if (low_pc == DYNTRANS_IC_ENTRIES_PER_PAGE) {
+		/*  Switch to next page:  */
+		cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) <<
+		    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (DYNTRANS_IC_ENTRIES_PER_PAGE <<
+		    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
+	} else if (low_pc == DYNTRANS_IC_ENTRIES_PER_PAGE + 1) {
+		/*  Switch to next page and skip an instruction which was
+		    already executed (in a delay slot):  */
+		cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) <<
+		    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += ((DYNTRANS_IC_ENTRIES_PER_PAGE + 1) <<
+		    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
+	}
+
+#ifdef DYNTRANS_MIPS
+	/*  Update the count register (on everything except EXC3K):  */
+	if (cpu->cd.mips.cpu_type.exc_model != EXC3K) {
+		uint32_t old;
+		int32_t diff1, diff2;
+		cpu->cd.mips.coproc[0]->reg[COP0_COUNT] -= cpu->cd.mips.count_register_read_count;
+		cpu->cd.mips.count_register_read_count = 0;
+		old = cpu->cd.mips.coproc[0]->reg[COP0_COUNT];
+		diff1 = cpu->cd.mips.coproc[0]->reg[COP0_COMPARE] - old;
+		cpu->cd.mips.coproc[0]->reg[COP0_COUNT] =
+		    (int32_t) (old + n_instrs);
+		diff2 = cpu->cd.mips.coproc[0]->reg[COP0_COMPARE] -
+		    cpu->cd.mips.coproc[0]->reg[COP0_COUNT];
+
+		if (cpu->cd.mips.compare_register_set) {
+#if 1
+/*  Not yet.  TODO  */
+			if (cpu->machine->emulated_hz > 0) {
+				if (cpu->cd.mips.compare_interrupts_pending > 0)
+					INTERRUPT_ASSERT(
+					    cpu->cd.mips.irq_compare);
+			} else
+#endif
+			{
+				if (diff1 > 0 && diff2 <= 0)
+					INTERRUPT_ASSERT(
+					    cpu->cd.mips.irq_compare);
+			}
+		}
+	}
+#endif
+#ifdef DYNTRANS_PPC
+	/*  Update the Decrementer and Time base registers:  */
+	{
+		uint32_t old = cpu->cd.ppc.spr[SPR_DEC];
+		cpu->cd.ppc.spr[SPR_DEC] = (uint32_t) (old - n_instrs);
+		if ((old >> 31) == 0 && (cpu->cd.ppc.spr[SPR_DEC] >> 31) == 1
+		    && !(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC))
+			cpu->cd.ppc.dec_intr_pending = 1;
+		old = cpu->cd.ppc.spr[SPR_TBL];
+		cpu->cd.ppc.spr[SPR_TBL] += n_instrs;
+		if ((old >> 31) == 1 && (cpu->cd.ppc.spr[SPR_TBL] >> 31) == 0)
+			cpu->cd.ppc.spr[SPR_TBU] ++;
+	}
+#endif
+
+	cpu->ninstrs += n_instrs;
+
+	/*  Return the nr of instructions executed:  */
+	return n_instrs;
+}
+#endif	/*  DYNTRANS_RUN_INSTR  */
+
+
+
+#ifdef DYNTRANS_FUNCTION_TRACE_DEF
+/*
+ *  XXX_cpu_functioncall_trace():
+ *
+ *  Without this function, the main trace tree function prints something
+ *  like    <f()>  or  <0x1234()>   on a function call. It is up to this
+ *  function to print the arguments passed.
+ */
+void DYNTRANS_FUNCTION_TRACE_DEF(struct cpu *cpu, int n_args)
+{
+	int show_symbolic_function_name = 1;
+        char strbuf[55];
+	char *symbol;
+	uint64_t ot;
+	int x, print_dots = 1, n_args_to_print =
+#if defined(DYNTRANS_ALPHA)
+	    6
+#else
+#if defined(DYNTRANS_SH) || defined(DYNTRANS_M88K) || defined(DYNTRANS_RISCV) || defined(DYNTRANS_I960)
+	    8	/*  For 32-bit and 64-bit SuperH, M88K, i960, and RISC-V  */
+#else
+	    4	/*  Default value for most archs  */
+#endif
+#endif
+	    ;
+
+	if (n_args >= 0 && n_args <= n_args_to_print) {
+		print_dots = 0;
+		n_args_to_print = n_args;
+	}
+
+#ifdef DYNTRANS_M88K
+	/*  Special hack for M88K userspace:  */
+	if (!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE))
+		show_symbolic_function_name = 0;
+#endif
+
+
+	/*
+	 *  TODO: The type of each argument should be taken from the symbol
+	 *  table, in some way.
+	 *
+	 *  The code here does a kind of "heuristic guess" regarding what the
+	 *  argument values might mean. Sometimes the output looks weird, but
+	 *  usually it looks good enough.
+	 *
+	 *  Print ".." afterwards to show that there might be more arguments
+	 *  than were passed in register.
+	 */
+	for (x=0; x<n_args_to_print; x++) {
+		int64_t d = cpu->cd.DYNTRANS_ARCH.
+#ifdef DYNTRANS_ALPHA
+		    r[ALPHA_A0
+#endif
+#ifdef DYNTRANS_ARM
+		    r[0
+#endif
+#ifdef DYNTRANS_I960
+		    r[I960_G0
+#endif
+#ifdef DYNTRANS_MIPS
+		    gpr[MIPS_GPR_A0
+#endif
+#ifdef DYNTRANS_M88K
+		    r[2		/*  r2..r9  */
+#endif
+#ifdef DYNTRANS_PPC
+		    gpr[3
+#endif
+#ifdef DYNTRANS_RISCV
+		    x[10
+#endif
+#ifdef DYNTRANS_SH
+		    r[4		/*  NetBSD seems to use 4? But 2 seems
+					to be used by other code? TODO  */
+#endif
+		    + x];
+
+		symbol = get_symbol_name(&cpu->machine->symbol_context, d, &ot);
+
+		if (d > -256 && d < 256)
+			fatal("%i", (int)d);
+		else if (memory_points_to_string(cpu, cpu->mem, d, 1)) {
+			memset(strbuf, 0, sizeof(strbuf));
+			memory_conv_to_string(cpu,
+			    cpu->mem, d, strbuf, sizeof(strbuf));
+			fatal("\"%s\"", strbuf);
+			// TODO: This shows "..." when the string is longer
+			// _or exactly the max length_. An improvement would
+			// be to detect the case where the string is exactly
+			// the max length and not show "..." then.
+			if (strlen(strbuf) >= sizeof(strbuf)-1)
+				fatal("...");
+		} else if (symbol != NULL && ot == 0 &&
+		    show_symbolic_function_name)
+			fatal("&%s", symbol);
+		else {
+			if (cpu->is_32bit)
+				fatal("0x%" PRIx32, (uint32_t)d);
+			else
+				fatal("0x%" PRIx64, (uint64_t)d);
+		}
+
+		if (x < n_args_to_print - 1)
+			fatal(",");
+	}
+
+	if (print_dots)
+		fatal(",..");
+}
+#endif	/*  DYNTRANS_FUNCTION_TRACE_DEF  */
+
+
+
+#ifdef DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE_DEF
+/*
+ *  XXX_tc_allocate_default_page():
+ *
+ *  Create a default page (with just pointers to instr(to_be_translated)
+ *  at cpu->translation_cache_cur_ofs.
+ */
+static void DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE_DEF(struct cpu *cpu,
+	uint64_t physaddr)
+{ 
+	struct DYNTRANS_TC_PHYSPAGE *ppp;
+
+	ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache
+	    + cpu->translation_cache_cur_ofs);
+
+	/*  Copy the entire template page first:  */
+	memcpy(ppp, cpu->cd.DYNTRANS_ARCH.physpage_template, sizeof(
+	    struct DYNTRANS_TC_PHYSPAGE));
+
+	ppp->physaddr = physaddr & ~(DYNTRANS_PAGESIZE - 1);
+
+	cpu->translation_cache_cur_ofs += sizeof(struct DYNTRANS_TC_PHYSPAGE);
+
+	cpu->translation_cache_cur_ofs --;
+	cpu->translation_cache_cur_ofs |= 63;
+	cpu->translation_cache_cur_ofs ++;
+}
+#endif	/*  DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE_DEF  */
+
+
+
+#ifdef DYNTRANS_PC_TO_POINTERS_FUNC
+/*
+ *  XXX_pc_to_pointers_generic():
+ *
+ *  Generic case. See DYNTRANS_PC_TO_POINTERS_FUNC below.
+ */
+void DYNTRANS_PC_TO_POINTERS_GENERIC(struct cpu *cpu)
+{
+#ifdef MODE32
+	uint32_t
+#else
+	uint64_t
+#endif
+	    cached_pc = cpu->pc, physaddr = 0;
+	uint32_t physpage_ofs;
+	int ok, pagenr, table_index;
+	uint32_t *physpage_entryp;
+	struct DYNTRANS_TC_PHYSPAGE *ppp;
+
+#ifdef MODE32
+	int index = DYNTRANS_ADDR_TO_PAGENR(cached_pc);
+#else
+	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+	uint32_t x1, x2, x3;
+	struct DYNTRANS_L2_64_TABLE *l2;
+	struct DYNTRANS_L3_64_TABLE *l3;
+
+	x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1;
+	x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+	x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
+	/*  fatal("X3: cached_pc=%016" PRIx64" x1=%x x2=%x x3=%x\n",
+	    (uint64_t)cached_pc, (int)x1, (int)x2, (int)x3);  */
+	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
+	/*  fatal("  l2 = %p\n", l2);  */
+	l3 = l2->l3[x2];
+	/*  fatal("  l3 = %p\n", l3);  */
+#endif
+
+	/*  Virtual to physical address translation:  */
+	ok = 0;
+#ifdef MODE32
+	if (cpu->cd.DYNTRANS_ARCH.host_load[index] != NULL) {
+		physaddr = cpu->cd.DYNTRANS_ARCH.phys_addr[index];
+		ok = 1;
+	}
+#else
+	if (l3->host_load[x3] != NULL) {
+		physaddr = l3->phys_addr[x3];
+		ok = 1;
+	}
+#endif
+
+	if (!ok) {
+		uint64_t paddr;
+		if (cpu->translate_v2p != NULL) {
+			uint64_t vaddr =
+#if defined(MODE32) && defined(DYNTRANS_MIPS)
+			/*  32-bit MIPS is _sign_ extend, not zero.  */
+			    (int32_t)
+#endif
+			    cached_pc;
+			ok = cpu->translate_v2p(
+			    cpu, vaddr, &paddr, FLAG_INSTR);
+		} else {
+			paddr = cached_pc;
+			ok = 1;
+		}
+		if (!ok) {
+			/*
+			 *  The PC is now set to the exception handler.
+			 *  Try to find the paddr in the translation arrays,
+			 *  or if that fails, call translate_v2p for the
+			 *  exception handler.
+			 */
+			/*  fatal("TODO: instruction vaddr=>paddr translation "
+			    "failed. vaddr=0x%" PRIx64"\n", (uint64_t)cached_pc);
+			fatal("!! cpu->pc=0x%" PRIx64"\n", (uint64_t)cpu->pc); */
+
+			/*  If there was an exception, the PC has changed.
+			    Update cached_pc:  */
+			cached_pc = cpu->pc;
+
+#ifdef MODE32
+			index = DYNTRANS_ADDR_TO_PAGENR(cached_pc);
+			if (cpu->cd.DYNTRANS_ARCH.host_load[index] != NULL) {
+				paddr = cpu->cd.DYNTRANS_ARCH.phys_addr[index];
+				ok = 1;
+			}
+#else
+			x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1;
+			x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N))
+			    & mask2;
+			x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N
+			    - DYNTRANS_L3N)) & mask3;
+			l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
+			l3 = l2->l3[x2];
+			if (l3->host_load[x3] != NULL) {
+				paddr = l3->phys_addr[x3];
+				ok = 1;
+			}
+#endif
+
+			if (!ok) {
+				ok = cpu->translate_v2p(cpu, cpu->pc, &paddr,
+				    FLAG_INSTR);
+			}
+
+			/*  printf("EXCEPTION HANDLER: vaddr = 0x%x ==> "
+			    "paddr = 0x%x\n", (int)cpu->pc, (int)paddr);
+			fatal("!? cpu->pc=0x%" PRIx64"\n", (uint64_t)cpu->pc); */
+
+			if (!ok) {
+				fatal("FATAL: could not find physical"
+				    " address of the exception handler?");
+				exit(1);
+			}
+		}
+
+		physaddr = paddr;
+	}
+
+	physaddr &= ~(DYNTRANS_PAGESIZE - 1);
+
+#ifdef MODE32
+	if (cpu->cd.DYNTRANS_ARCH.host_load[index] == NULL) {
+#else
+	if (l3->host_load[x3] == NULL) {
+#endif
+		int q = DYNTRANS_PAGESIZE - 1;
+		unsigned char *host_page = memory_paddr_to_hostaddr(cpu->mem,
+		    physaddr, MEM_READ);
+		if (host_page != NULL) {
+			cpu->update_translation_table(cpu, cached_pc & ~q,
+			    host_page, 0, physaddr);
+		}
+	}
+
+	if (cpu->translation_cache_cur_ofs >= dyntrans_cache_size) {
+		debugmsg(SUBSYS_CPU, "dyntrans", VERBOSITY_INFO,
+		    "resetting the translation cache");
+
+		cpu_create_or_reset_tc(cpu);
+	}
+
+	pagenr = DYNTRANS_ADDR_TO_PAGENR(physaddr);
+	table_index = PAGENR_TO_TABLE_INDEX(pagenr);
+
+	physpage_entryp = &(((uint32_t *)cpu->translation_cache)[table_index]);
+	physpage_ofs = *physpage_entryp;
+	ppp = NULL;
+
+	/*  Traverse the physical page chain:  */
+	while (physpage_ofs != 0) {
+		ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache
+		    + physpage_ofs);
+
+		/*  If we found the page in the cache, then we're done:  */
+		if (ppp->physaddr == physaddr)
+			break;
+
+		/*  Try the next page in the chain:  */
+		physpage_ofs = ppp->next_ofs;
+	}
+
+	/*
+	 *  If the offset is 0, then no translation exists yet for this
+	 *  physical address. Let's create a new page, and add it first in
+	 *  the chain.
+	 */
+	if (physpage_ofs == 0) {
+		uint32_t previous_first_page_in_chain;
+
+		/*  fatal("CREATING page %lli (physaddr 0x%" PRIx64"), table "
+		    "index %i\n", (long long)pagenr, (uint64_t)physaddr,
+		    (int)table_index);  */
+
+		previous_first_page_in_chain = *physpage_entryp;
+
+		/*  Insert the new page first in the chain:  */
+		*physpage_entryp = physpage_ofs =
+		    cpu->translation_cache_cur_ofs;
+
+		/*  Allocate a default page, with to_be_translated entries:  */
+		DYNTRANS_TC_ALLOCATE(cpu, physaddr);
+
+		ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache
+		    + physpage_ofs);
+
+		/*  Point to the other pages in the same chain:  */
+		ppp->next_ofs = previous_first_page_in_chain;
+	}
+
+	/*  Here, ppp points to a valid physical page struct.  */
+
+#ifdef MODE32
+	if (cpu->cd.DYNTRANS_ARCH.host_load[index] != NULL)
+		cpu->cd.DYNTRANS_ARCH.phys_page[index] = ppp;
+#else
+	if (l3->host_load[x3] != NULL)
+		l3->phys_page[x3] = ppp;
+#endif
+
+	/*
+	 *  If there are no translations yet on this page, then mark it
+	 *  as non-writable. If there are already translations, then it
+	 *  should already have been marked as non-writable.
+	 */
+	if (ppp->translations_bitmap == 0) {
+		cpu->invalidate_translation_caches(cpu, physaddr,
+		    JUST_MARK_AS_NON_WRITABLE | INVALIDATE_PADDR);
+	}
+
+	cpu->cd.DYNTRANS_ARCH.cur_ic_page = &ppp->ics[0];
+
+	cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page +
+	    DYNTRANS_PC_TO_IC_ENTRY(cached_pc);
+
+	/*  printf("cached_pc=0x%016" PRIx64"  pagenr=%lli  table_index=%lli, "
+	    "physpage_ofs=0x%016" PRIx64"\n", (uint64_t)cached_pc, (long long)
+	    pagenr, (long long)table_index, (uint64_t)physpage_ofs);  */
+}
+
+
+/*
+ *  XXX_pc_to_pointers():
+ *
+ *  This function uses the current program counter (a virtual address) to
+ *  find out which physical translation page to use, and then sets the current
+ *  translation page pointers to that page.
+ *
+ *  If there was no translation page for that physical page, then an empty
+ *  one is created.
+ *
+ *  NOTE: This is the quick lookup version. See
+ *  DYNTRANS_PC_TO_POINTERS_GENERIC above for the generic case.
+ */
+void DYNTRANS_PC_TO_POINTERS_FUNC(struct cpu *cpu)
+{
+#ifdef MODE32
+	uint32_t
+#else
+	uint64_t
+#endif
+	    cached_pc = cpu->pc;
+	struct DYNTRANS_TC_PHYSPAGE *ppp;
+
+#ifdef MODE32
+	int index;
+	index = DYNTRANS_ADDR_TO_PAGENR(cached_pc);
+	ppp = cpu->cd.DYNTRANS_ARCH.phys_page[index];
+	if (ppp != NULL)
+		goto have_it;
+#else
+	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+	uint32_t x1, x2, x3;
+	struct DYNTRANS_L2_64_TABLE *l2;
+	struct DYNTRANS_L3_64_TABLE *l3;
+
+	x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1;
+	x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+	x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
+	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
+	l3 = l2->l3[x2];
+	ppp = l3->phys_page[x3];
+	if (ppp != NULL)
+		goto have_it;
+#endif
+
+	DYNTRANS_PC_TO_POINTERS_GENERIC(cpu);
+	return;
+
+	/*  Quick return path:  */
+have_it:
+	cpu->cd.DYNTRANS_ARCH.cur_ic_page = &ppp->ics[0];
+	cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page +
+	    DYNTRANS_PC_TO_IC_ENTRY(cached_pc);
+
+	/*  printf("cached_pc=0x%016" PRIx64"  pagenr=%lli  table_index=%lli, "
+	    "physpage_ofs=0x%016" PRIx64"\n", (uint64_t)cached_pc, (long long)
+	    pagenr, (long long)table_index, (uint64_t)physpage_ofs);  */
+}
+#endif	/*  DYNTRANS_PC_TO_POINTERS_FUNC  */
+
+
+
+#ifdef DYNTRANS_INIT_TABLES
+
+/*  forward declaration of to_be_translated and end_of_page:  */
+static void instr(to_be_translated)(struct cpu *, struct DYNTRANS_IC *);
+static void instr(end_of_page)(struct cpu *,struct DYNTRANS_IC *);
+#ifdef DYNTRANS_DUALMODE_32
+static void instr32(to_be_translated)(struct cpu *, struct DYNTRANS_IC *);
+static void instr32(end_of_page)(struct cpu *,struct DYNTRANS_IC *);
+#endif
+
+#ifdef DYNTRANS_DUALMODE_32
+#define TO_BE_TRANSLATED    ( cpu->is_32bit? instr32(to_be_translated) : \
+			      instr(to_be_translated) )
+#else
+#define TO_BE_TRANSLATED    ( instr(to_be_translated) )
+#endif
+
+#ifdef DYNTRANS_DELAYSLOT
+static void instr(end_of_page2)(struct cpu *,struct DYNTRANS_IC *);
+#ifdef DYNTRANS_DUALMODE_32
+static void instr32(end_of_page2)(struct cpu *,struct DYNTRANS_IC *);
+#endif
+#endif
+
+/*
+ *  XXX_init_tables():
+ *
+ *  Initializes the default translation page (for newly allocated pages), and
+ *  for 64-bit emulation it also initializes 64-bit dummy tables and pointers.
+ */
+void DYNTRANS_INIT_TABLES(struct cpu *cpu)
+{
+#ifndef MODE32
+	struct DYNTRANS_L2_64_TABLE *dummy_l2;
+	struct DYNTRANS_L3_64_TABLE *dummy_l3;
+	int x1, x2;
+#endif
+	int i;
+	struct DYNTRANS_TC_PHYSPAGE *ppp;
+
+	CHECK_ALLOCATION(ppp =
+	    (struct DYNTRANS_TC_PHYSPAGE *) malloc(sizeof(struct DYNTRANS_TC_PHYSPAGE)));
+
+	ppp->next_ofs = 0;
+	ppp->translations_bitmap = 0;
+	ppp->translation_ranges_ofs = 0;
+	/*  ppp->physaddr is filled in by the page allocator  */
+
+	for (i=0; i<DYNTRANS_IC_ENTRIES_PER_PAGE; i++)
+		ppp->ics[i].f = TO_BE_TRANSLATED;
+
+	/*  End-of-page:  */
+	ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE + 0].f =
+#ifdef DYNTRANS_DUALMODE_32
+	    cpu->is_32bit? instr32(end_of_page) :
+#endif
+	    instr(end_of_page);
+
+	/*  End-of-page-2, for delay-slot architectures:  */
+#ifdef DYNTRANS_DELAYSLOT
+	ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE + 1].f =
+#ifdef DYNTRANS_DUALMODE_32
+	    cpu->is_32bit? instr32(end_of_page2) :
+#endif
+	    instr(end_of_page2);
+#endif
+
+	cpu->cd.DYNTRANS_ARCH.physpage_template = ppp;
+
+
+	/*  Prepare 64-bit virtual address translation tables:  */
+#ifndef MODE32
+	if (cpu->is_32bit)
+		return;
+
+	dummy_l2 = (struct DYNTRANS_L2_64_TABLE *) zeroed_alloc(sizeof(struct DYNTRANS_L2_64_TABLE));
+	dummy_l3 = (struct DYNTRANS_L3_64_TABLE *) zeroed_alloc(sizeof(struct DYNTRANS_L3_64_TABLE));
+
+	cpu->cd.DYNTRANS_ARCH.l2_64_dummy = dummy_l2;
+	cpu->cd.DYNTRANS_ARCH.l3_64_dummy = dummy_l3;
+
+	for (x1 = 0; x1 < (1 << DYNTRANS_L1N); x1 ++)
+		cpu->cd.DYNTRANS_ARCH.l1_64[x1] = dummy_l2;
+
+	for (x2 = 0; x2 < (1 << DYNTRANS_L2N); x2 ++)
+		dummy_l2->l3[x2] = dummy_l3;
+#endif
+}
+#endif	/*  DYNTRANS_INIT_TABLES  */
+
+
+
+#ifdef DYNTRANS_INVAL_ENTRY
+/*
+ *  XXX_invalidate_tlb_entry():
+ *
+ *  Invalidate one translation entry (based on virtual address).
+ *
+ *  If the JUST_MARK_AS_NON_WRITABLE flag is set, then the translation entry
+ *  is just downgraded to non-writable (ie the host store page is set to
+ *  NULL). Otherwise, the entire translation is removed.
+ */
+static void DYNTRANS_INVALIDATE_TLB_ENTRY(struct cpu *cpu,
+#ifdef MODE32
+	uint32_t
+#else
+	uint64_t
+#endif
+	vaddr_page, int flags)
+{
+#ifdef MODE32
+	uint32_t index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page);
+
+#ifdef DYNTRANS_ARM
+	cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 5] &= ~(1 << (index & 31));
+#endif
+
+	if (flags & JUST_MARK_AS_NON_WRITABLE) {
+		/*  printf("JUST MARKING NON-W: vaddr 0x%08x\n",
+		    (int)vaddr_page);  */
+		cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL;
+	} else {
+		int tlbi = cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index];
+		cpu->cd.DYNTRANS_ARCH.host_load[index] = NULL;
+		cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL;
+		cpu->cd.DYNTRANS_ARCH.phys_addr[index] = 0;
+		cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL;
+		if (tlbi > 0)
+			cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[tlbi-1].valid = 0;
+		cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index] = 0;
+	}
+#else
+	// 64-bit:
+	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+	uint32_t x1, x2, x3;
+	struct DYNTRANS_L2_64_TABLE *l2;
+	struct DYNTRANS_L3_64_TABLE *l3;
+
+	x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1;
+	x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+	x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N))& mask3;
+
+	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
+	if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy)
+		return;
+
+	l3 = l2->l3[x2];
+	if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy)
+		return;
+
+	if (flags & JUST_MARK_AS_NON_WRITABLE) {
+		l3->host_store[x3] = NULL;
+		return;
+	}
+
+#ifdef BUGHUNT
+
+{
+	/*  Consistency check, for debugging:  */
+	int x1, x1b; // x2, x3;
+	struct DYNTRANS_L2_64_TABLE *l2;
+	//struct DYNTRANS_L3_64_TABLE *l3;
+
+	for (x1 = 0; x1 <= mask1; x1 ++) {
+		l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
+		if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy)
+			continue;
+		/*  Make sure that this l2 isn't used more than 1 time!  */
+		for (x1b = 0; x1b <= mask1; x1b ++)
+			if (x1 != x1b &&
+			    l2 == cpu->cd.DYNTRANS_ARCH.l1_64[x1b]) {
+				fatal("L2 reuse: %p\n", l2);
+				exit(1);
+			}
+	}
+}
+
+/*  Count how many pages are actually in use:  */
+{
+	int n=0, i;
+	for (i=0; i<=mask3; i++)
+		if (l3->vaddr_to_tlbindex[i])
+			n++;
+	if (n != l3->refcount) {
+		printf("Z: %i in use, but refcount = %i!\n", n, l3->refcount);
+		exit(1);
+	}
+
+	n = 0;
+	for (i=0; i<=mask3; i++)
+		if (l3->host_load[i] != NULL)
+			n++;
+	if (n != l3->refcount) {
+		printf("ZHL: %i in use, but refcount = %i!\n", n, l3->refcount);
+		exit(1);
+	}
+}
+#endif
+
+/*
+	int found = -1;
+	for (int q = 0; q < 192; ++q)
+	{
+		if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[q].vaddr_page == vaddr_page &&
+			cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[q].valid)
+		{
+			if (found >= 0)
+			{
+				printf("ALREADY FOUND = %i\n", found);
+				int zz = found;
+				printf("%03i: ", zz);
+				printf("vaddr=%016llx\n", (long long)cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[zz].vaddr_page);
+				printf("valid=%i\n", cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[zz].valid);
+
+				zz = q;
+				printf("%03i: ", zz);
+				printf("vaddr=%016llx\n", (long long)cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[zz].vaddr_page);
+				printf("valid=%i\n", cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[zz].valid);
+
+				exit(1);
+			}
+			
+			found = q;
+		}
+	}
+*/
+
+	l3->host_load[x3] = NULL;
+	l3->host_store[x3] = NULL;
+	l3->phys_addr[x3] = 0;
+	l3->phys_page[x3] = NULL;
+	if (l3->vaddr_to_tlbindex[x3] != 0) {
+		cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[
+		    l3->vaddr_to_tlbindex[x3] - 1].valid = 0;
+		l3->refcount --;
+	} else {/*
+		printf("APA: vaddr_page=%016llx l3->refcount = %i\n", (long long)vaddr_page, l3->refcount);
+		for (int zz = 0; zz < 128; ++zz)
+		{
+			printf("%03i: ", zz);
+			printf("vaddr=%016llx\n", (long long)cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[zz].vaddr_page);
+			printf("valid=%i\n", cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[zz].valid);
+		}
+		
+		exit(1);*/
+	}
+	l3->vaddr_to_tlbindex[x3] = 0;
+
+	if (l3->refcount < 0) {
+		fatal("xxx_invalidate_tlb_entry(): huh? Refcount bug.\n");
+		exit(1);
+	}
+
+	if (l3->refcount == 0) {
+		l3->next = cpu->cd.DYNTRANS_ARCH.next_free_l3;
+		cpu->cd.DYNTRANS_ARCH.next_free_l3 = l3;
+		l2->l3[x2] = cpu->cd.DYNTRANS_ARCH.l3_64_dummy;
+
+#ifdef BUGHUNT
+/*  Make sure that we're placing a CLEAN page on the
+    freelist:  */
+{
+	int i;
+	for (i=0; i<=mask3; i++)
+		if (l3->host_load[i] != NULL) {
+			fatal("TRYING TO RETURN A NON-CLEAN L3 PAGE!\n");
+			exit(1);
+		}
+}
+#endif
+		l2->refcount --;
+		if (l2->refcount < 0) {
+			fatal("xxx_invalidate_tlb_entry(): Refcount bug L2.\n");
+			exit(1);
+		}
+		if (l2->refcount == 0) {
+			l2->next = cpu->cd.DYNTRANS_ARCH.next_free_l2;
+			cpu->cd.DYNTRANS_ARCH.next_free_l2 = l2;
+			cpu->cd.DYNTRANS_ARCH.l1_64[x1] =
+			    cpu->cd.DYNTRANS_ARCH.l2_64_dummy;
+		}
+	}
+#endif
+}
+#endif
+
+
+#ifdef DYNTRANS_INVALIDATE_TC
+/*
+ *  XXX_invalidate_translation_caches():
+ *
+ *  Invalidate all entries matching a specific physical address, a specific
+ *  virtual address, or ALL entries.
+ *
+ *  flags should be one of
+ *	INVALIDATE_PADDR  INVALIDATE_VADDR  or  INVALIDATE_ALL
+ *
+ *  In addition, for INVALIDATE_ALL, INVALIDATE_VADDR_UPPER4 may be set and
+ *  bit 31..28 of addr are used to select the virtual addresses to invalidate.
+ *  (This is useful for PowerPC emulation, when segment registers are updated.)
+ *
+ *  In the case when all translations are invalidated, paddr doesn't need
+ *  to be supplied.
+ *
+ *  NOTE/TODO: When invalidating a virtual address, it is only cleared from
+ *             the quick translation array, not from the linear
+ *             vph_tlb_entry[] array.  Hopefully this is enough anyway.
+ */
+void DYNTRANS_INVALIDATE_TC(struct cpu *cpu, uint64_t addr, int flags)
+{
+	int r;
+#ifdef MODE32
+	uint32_t
+#else
+	uint64_t
+#endif
+	    addr_page = addr & ~(DYNTRANS_PAGESIZE - 1);
+
+	/*  fatal("invalidate(): ");  */
+
+	/*  Quick case for _one_ virtual addresses: see note above.  */
+	if (flags & INVALIDATE_VADDR) {
+		/*  fatal("vaddr 0x%08x\n", (int)addr_page);  */
+
+#ifdef MODE32
+		DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, addr_page, flags);
+#else
+		// In principle, there can be multiple entries, and they must
+		// be invalidated based on the bits that matter. For example,
+		// using vaddr 0x00A0000012345678 and 0x00B000001234567c
+		// actually point to the same physical page, and if then
+		// the virtual address 0x0000000012345000 is to be invalidated,
+		// then both of those should be invalidated!
+		int n = 0;
+		for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++)
+			if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid &&
+			    (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page
+			    & cpu->vaddr_mask) == (addr_page & cpu->vaddr_mask)) {
+				DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page, flags);
+				n ++;
+			}
+
+		if (n > 1)
+			debug("[ DYNTRANS_INVALIDATE_TC: CACHE COLLISION vaddr 0x%016llx! ]\n",
+				(long long)addr_page);
+#endif
+
+		return;
+	}
+
+	/*  Invalidate everything:  */
+#ifdef DYNTRANS_PPC
+	if (flags & INVALIDATE_ALL && flags & INVALIDATE_VADDR_UPPER4) {
+		/*  fatal("all, upper4 (PowerPC segment)\n");  */
+		for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++) {
+			if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid &&
+			    (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page
+			    & 0xf0000000) == addr_page) {
+				DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, cpu->cd.
+				    DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page,
+				    0);
+				// Not needed: DYNTRANS_INVALIDATE_TLB_ENTRY should
+				// set valid to 0 anyway.
+				// cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid=0;
+			}
+		}
+		return;
+	}
+#endif
+	if (flags & INVALIDATE_ALL) {
+		/*  fatal("all\n");  */
+		for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++) {
+			if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) {
+				DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, cpu->cd.
+				    DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page,
+				    0);
+				// Not needed: DYNTRANS_INVALIDATE_TLB_ENTRY should
+				// set valid to 0 anyway.
+				// cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid=0;
+			}
+		}
+		return;
+	}
+
+	/*  Invalidate a physical page:  */
+
+	if (!(flags & INVALIDATE_PADDR))
+		fatal("HUH? Invalidate: Not vaddr, all, or paddr?\n");
+
+	/*  fatal("addr 0x%08x\n", (int)addr_page);  */
+
+	for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++) {
+		if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid && addr_page
+		    == cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].paddr_page) {
+			DYNTRANS_INVALIDATE_TLB_ENTRY(cpu,
+			    cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page,
+			    flags);
+			if (flags & JUST_MARK_AS_NON_WRITABLE)
+				cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r]
+				    .writeflag = 0;
+			else
+				cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r]
+				    .valid = 0;
+		}
+	}
+}
+#endif	/*  DYNTRANS_INVALIDATE_TC  */
+
+
+
+#ifdef DYNTRANS_INVALIDATE_TC_CODE
+/*
+ *  XXX_invalidate_code_translation():
+ *
+ *  Invalidate code translations for a specific physical address, a specific
+ *  virtual address, or for all entries in the cache.
+ */
+void DYNTRANS_INVALIDATE_TC_CODE(struct cpu *cpu, uint64_t addr, int flags)
+{
+	int r;
+#ifdef MODE32
+	uint32_t
+#else
+	uint64_t
+#endif
+	    vaddr_page, paddr_page;
+
+	addr &= ~(DYNTRANS_PAGESIZE-1);
+
+	/*  printf("DYNTRANS_INVALIDATE_TC_CODE addr=0x%08x flags=%i\n",
+	    (int)addr, flags);  */
+
+	if (flags & INVALIDATE_PADDR) {
+		int pagenr, table_index;
+		uint32_t physpage_ofs, *physpage_entryp;
+		struct DYNTRANS_TC_PHYSPAGE *ppp, *prev_ppp;
+
+		pagenr = DYNTRANS_ADDR_TO_PAGENR(addr);
+		table_index = PAGENR_TO_TABLE_INDEX(pagenr);
+
+		physpage_entryp = &(((uint32_t *)cpu->
+		    translation_cache)[table_index]);
+		physpage_ofs = *physpage_entryp;
+
+		/*  Return immediately if there is no code translation
+		    for this page.  */
+		if (physpage_ofs == 0)
+			return;
+
+		prev_ppp = ppp = NULL;
+
+		/*  Traverse the physical page chain:  */
+		while (physpage_ofs != 0) {
+			prev_ppp = ppp;
+			ppp = (struct DYNTRANS_TC_PHYSPAGE *)
+			    (cpu->translation_cache + physpage_ofs);
+
+			/*  If we found the page in the cache,
+			    then we're done:  */
+			if (ppp->physaddr == addr)
+				break;
+
+			/*  Try the next page in the chain:  */
+			physpage_ofs = ppp->next_ofs;
+		}
+
+		/*  If there is no translation, there is no need to go
+		    on and try to remove it from the vph_tlb_entry array:  */
+		if (physpage_ofs == 0)
+			return;
+
+#if 0
+		/*
+		 *  "Bypass" the page, removing it from the code cache.
+		 *
+		 *  NOTE/TODO: This gives _TERRIBLE_ performance with self-
+		 *  modifying code, or when a single page is used for both
+		 *  code and (writable) data.
+		 */
+		if (ppp != NULL) {
+			if (prev_ppp != NULL)
+				prev_ppp->next_ofs = ppp->next_ofs;
+			else
+				*physpage_entryp = ppp->next_ofs;
+		}
+#else
+		(void)prev_ppp;	// shut up compiler warning
+
+		/*
+		 *  Instead of removing the page from the code cache, each
+		 *  entry can be set to "to_be_translated". This is slow in
+		 *  the general case, but in the case of self-modifying code,
+		 *  it might be faster since we don't risk wasting cache
+		 *  memory as quickly (which would force unnecessary Restarts).
+		 */
+		if (ppp != NULL && ppp->translations_bitmap != 0) {
+			uint32_t x = ppp->translations_bitmap;	/*  TODO:
+				urk Should be same type as the bitmap */
+			int i, j, n, m;
+
+#ifdef DYNTRANS_ARM
+			/*
+			 *  Note: On ARM, PC-relative load instructions are
+			 *  implemented as immediate mov instructions. When
+			 *  setting parts of the page to "to be translated",
+			 *  we cannot keep track of which of the immediate
+			 *  movs that were affected, so we need to clear
+			 *  the entire page. (ARM only; not for the general
+			 *  case.)
+			 */
+			x = 0xffffffff;
+#endif
+			n = 8 * sizeof(x);
+			m = DYNTRANS_IC_ENTRIES_PER_PAGE / n;
+
+			for (i=0; i<n; i++) {
+				if (x & 1) {
+					for (j=0; j<m; j++)
+						ppp->ics[i*m + j].f =
+						    TO_BE_TRANSLATED;
+				}
+
+				x >>= 1;
+			}
+
+			ppp->translations_bitmap = 0;
+
+			/*  Clear the list of translatable ranges:  */
+			if (ppp->translation_ranges_ofs != 0) {
+				struct physpage_ranges *physpage_ranges =
+				    (struct physpage_ranges *)
+				    (cpu->translation_cache +
+				    ppp->translation_ranges_ofs);
+				physpage_ranges->next_ofs = 0;
+				physpage_ranges->n_entries_used = 0;
+			}
+		}
+#endif
+	}
+
+	/*  Invalidate entries in the VPH table:  */
+	for (r = 0; r < DYNTRANS_MAX_VPH_TLB_ENTRIES; r ++) {
+		if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) {
+			vaddr_page = cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r]
+			    .vaddr_page & ~(DYNTRANS_PAGESIZE-1);
+			paddr_page = cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r]
+			    .paddr_page & ~(DYNTRANS_PAGESIZE-1);
+
+			if (flags & INVALIDATE_ALL ||
+			    (flags & INVALIDATE_PADDR && paddr_page == addr) ||
+			    (flags & INVALIDATE_VADDR && vaddr_page == addr)) {
+#ifdef MODE32
+				uint32_t index =
+				    DYNTRANS_ADDR_TO_PAGENR(vaddr_page);
+				cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL;
+#else
+				const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+				const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+				const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+				uint32_t x1, x2, x3;
+				struct DYNTRANS_L2_64_TABLE *l2;
+				struct DYNTRANS_L3_64_TABLE *l3;
+
+				x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1;
+				x2 = (vaddr_page >> (64-DYNTRANS_L1N -
+				    DYNTRANS_L2N)) & mask2;
+				x3 = (vaddr_page >> (64-DYNTRANS_L1N -
+				    DYNTRANS_L2N - DYNTRANS_L3N)) & mask3;
+				l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
+				l3 = l2->l3[x2];
+				l3->phys_page[x3] = NULL;
+#endif
+			}
+		}
+	}
+}
+#endif	/*  DYNTRANS_INVALIDATE_TC_CODE  */
+
+
+
+#ifdef DYNTRANS_UPDATE_TRANSLATION_TABLE
+/*
+ *  XXX_update_translation_table():
+ *
+ *  Update the virtual memory translation tables.
+ */
+void DYNTRANS_UPDATE_TRANSLATION_TABLE(struct cpu *cpu, uint64_t vaddr_page,
+	unsigned char *host_page, int writeflag, uint64_t paddr_page)
+{
+	int found, r, useraccess = 0;
+
+#ifdef MODE32
+	uint32_t index;
+	vaddr_page &= 0xffffffffULL;
+
+	if (paddr_page > 0xffffffffULL) {
+		fatal("update_translation_table(): v=0x%016" PRIx64", h=%p w=%i"
+		    " p=0x%016" PRIx64"\n", vaddr_page, host_page, writeflag,
+		    paddr_page);
+		exit(1);
+	}
+
+	/*  fatal("update_translation_table(): v=0x%x, h=%p w=%i"
+	    " p=0x%x\n", (int)vaddr_page, host_page, writeflag,
+	    (int)paddr_page);  */
+#else	/*  !MODE32  */
+	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+	uint32_t x1, x2, x3;
+	struct DYNTRANS_L2_64_TABLE *l2;
+	struct DYNTRANS_L3_64_TABLE *l3;
+
+	/*  fatal("update_translation_table(): v=0x%016" PRIx64", h=%p w=%i"
+	    " p=0x%016" PRIx64"\n", (uint64_t)vaddr_page, host_page, writeflag,
+	    (uint64_t)paddr_page);  */
+#endif
+
+	assert((vaddr_page & (DYNTRANS_PAGESIZE-1)) == 0);
+	assert((paddr_page & (DYNTRANS_PAGESIZE-1)) == 0);
+
+	if (writeflag & MEMORY_USER_ACCESS) {
+		writeflag &= ~MEMORY_USER_ACCESS;
+		useraccess = 1;
+	}
+
+	(void)useraccess;  // shut up compiler warning about unused var
+
+#ifdef DYNTRANS_M88K
+	/*  TODO  */
+	if (useraccess)
+		return;
+#endif
+
+	/*  Scan the current TLB entries:  */
+
+#ifdef MODE32
+	/*
+	 *  NOTE 1: vaddr_to_tlbindex is one more than the index, so that
+	 *          0 becomes -1, which means a miss.
+	 *
+	 *  NOTE 2: When a miss occurs, instead of scanning the entire tlb
+	 *          for the entry with the lowest time stamp, just choosing
+	 *          one at random will work as well.
+	 */
+	found = (int)cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[
+	    DYNTRANS_ADDR_TO_PAGENR(vaddr_page)] - 1;
+#else
+	x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1;
+	x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+	x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N))
+	    & mask3;
+
+	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
+	if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy)
+		found = -1;
+	else {
+		l3 = l2->l3[x2];
+		if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy)
+			found = -1;
+		else
+			found = (int)l3->vaddr_to_tlbindex[x3] - 1;
+	}
+#endif
+
+	if (found < 0) {
+		/*  Create the new TLB entry, overwriting a "random" entry:  */
+		static unsigned int x = 0;
+		r = (x++) % DYNTRANS_MAX_VPH_TLB_ENTRIES;
+
+		if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) {
+			/*  This one has to be invalidated first:  */
+			DYNTRANS_INVALIDATE_TLB_ENTRY(cpu,
+			    cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page,
+			    0);
+		}
+
+		cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid = 1;
+		cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].host_page = host_page;
+		cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].paddr_page = paddr_page;
+		cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page = vaddr_page;
+		cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag =
+		    writeflag & MEM_WRITE;
+
+		/*  Add the new translation to the table:  */
+#ifdef MODE32
+		index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page);
+		cpu->cd.DYNTRANS_ARCH.host_load[index] = host_page;
+		cpu->cd.DYNTRANS_ARCH.host_store[index] =
+		    writeflag? host_page : NULL;
+		cpu->cd.DYNTRANS_ARCH.phys_addr[index] = paddr_page;
+		cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL;
+		cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index] = r + 1;
+#ifdef DYNTRANS_ARM
+		if (useraccess)
+			cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 5]
+			    |= 1 << (index & 31);
+#endif
+#else	/* !MODE32  */
+		l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
+		if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) {
+			if (cpu->cd.DYNTRANS_ARCH.next_free_l2 != NULL) {
+				l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1] =
+				    cpu->cd.DYNTRANS_ARCH.next_free_l2;
+				cpu->cd.DYNTRANS_ARCH.next_free_l2 = l2->next;
+			} else {
+				int i;
+				CHECK_ALLOCATION(l2 =
+				    cpu->cd.DYNTRANS_ARCH.l1_64[x1] =
+				    (struct DYNTRANS_L2_64_TABLE *) malloc(
+				    sizeof(struct DYNTRANS_L2_64_TABLE)));
+				l2->refcount = 0;
+				for (i=0; i<(1 << DYNTRANS_L2N); i++)
+					l2->l3[i] = cpu->cd.DYNTRANS_ARCH.
+					    l3_64_dummy;
+			}
+			if (l2->refcount != 0) {
+				fatal("Huh? l2 Refcount problem.\n");
+				exit(1);
+			}
+		}
+		if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) {
+			fatal("INTERNAL ERROR L2 reuse\n");
+			exit(1);
+		}
+		l3 = l2->l3[x2];
+		if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy) {
+			if (cpu->cd.DYNTRANS_ARCH.next_free_l3 != NULL) {
+				l3 = l2->l3[x2] =
+				    cpu->cd.DYNTRANS_ARCH.next_free_l3;
+				cpu->cd.DYNTRANS_ARCH.next_free_l3 = l3->next;
+			} else {
+				l3 = l2->l3[x2] = (struct DYNTRANS_L3_64_TABLE *)
+				    zeroed_alloc(sizeof(
+				    struct DYNTRANS_L3_64_TABLE));
+			}
+			if (l3->refcount != 0) {
+				fatal("Huh? l3 Refcount problem.\n");
+				exit(1);
+			}
+			l2->refcount ++;
+		}
+		if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy) {
+			fatal("INTERNAL ERROR L3 reuse\n");
+			exit(1);
+		}
+
+		l3->host_load[x3] = host_page;
+		l3->host_store[x3] = writeflag? host_page : NULL;
+		l3->phys_addr[x3] = paddr_page;
+		l3->phys_page[x3] = NULL;
+		l3->vaddr_to_tlbindex[x3] = r + 1;
+		l3->refcount ++;
+
+#ifdef BUGHUNT
+/*  Count how many pages are actually in use:  */
+{
+	int n=0, i;
+	for (i=0; i<=mask3; i++)
+		if (l3->vaddr_to_tlbindex[i])
+			n++;
+	if (n != l3->refcount) {
+		printf("X: %i in use, but refcount = %i!\n", n, l3->refcount);
+		exit(1);
+	}
+
+	n = 0;
+	for (i=0; i<=mask3; i++)
+		if (l3->host_load[i] != NULL)
+			n++;
+	if (n != l3->refcount) {
+		printf("XHL: %i in use, but refcount = %i!\n", n, l3->refcount);
+		exit(1);
+	}
+}
+#endif
+
+#endif	/* !MODE32  */
+	} else {
+		/*
+		 *  The translation was already in the TLB.
+		 *	Writeflag = 0:  Do nothing.
+		 *	Writeflag = 1:  Make sure the page is writable.
+		 *	Writeflag = MEM_DOWNGRADE: Downgrade to readonly.
+		 */
+		r = found;
+		if (writeflag & MEM_WRITE)
+			cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 1;
+		if (writeflag & MEM_DOWNGRADE)
+			cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 0;
+#ifdef MODE32
+		index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page);
+		cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL;
+#ifdef DYNTRANS_ARM
+		cpu->cd.DYNTRANS_ARCH.is_userpage[index>>5] &= ~(1<<(index&31));
+		if (useraccess)
+			cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 5]
+			    |= 1 << (index & 31);
+#endif
+		if (cpu->cd.DYNTRANS_ARCH.phys_addr[index] == paddr_page) {
+			if (writeflag & MEM_WRITE)
+				cpu->cd.DYNTRANS_ARCH.host_store[index] =
+				    host_page;
+			if (writeflag & MEM_DOWNGRADE)
+				cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL;
+		} else {
+			/*  Change the entire physical/host mapping:  */
+			cpu->cd.DYNTRANS_ARCH.host_load[index] = host_page;
+			cpu->cd.DYNTRANS_ARCH.host_store[index] =
+			    writeflag? host_page : NULL;
+			cpu->cd.DYNTRANS_ARCH.phys_addr[index] = paddr_page;
+		}
+#else	/*  !MODE32  */
+		x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1;
+		x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+		x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N))
+		    & mask3;
+		l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
+		l3 = l2->l3[x2];
+		if (l3->phys_addr[x3] == paddr_page) {
+			if (writeflag & MEM_WRITE)
+				l3->host_store[x3] = host_page;
+			if (writeflag & MEM_DOWNGRADE)
+				l3->host_store[x3] = NULL;
+		} else {
+			/*  Change the entire physical/host mapping:  */
+			l3->host_load[x3] = host_page;
+			l3->host_store[x3] = writeflag? host_page : NULL;
+			l3->phys_addr[x3] = paddr_page;
+		}
+		
+		/*  HM!  /2013-11-17  */
+		/*  Should this be here?  2014-08-02  */
+		//l3->phys_page[x3] = NULL;
+
+#ifdef BUGHUNT
+/*  Count how many pages are actually in use:  */
+{
+	int n=0, i;
+	for (i=0; i<=mask3; i++)
+		if (l3->vaddr_to_tlbindex[i])
+			n++;
+	if (n != l3->refcount) {
+		printf("Y: %i in use, but refcount = %i!\n", n, l3->refcount);
+		exit(1);
+	}
+
+	n = 0;
+	for (i=0; i<=mask3; i++)
+		if (l3->host_load[i] != NULL)
+			n++;
+	if (n != l3->refcount) {
+		printf("YHL: %i in use, but refcount = %i!\n", n, l3->refcount);
+		printf("Entry r = %i\n", r);
+		printf("Valid = %i\n",
+cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid);
+		exit(1);
+	}
+}
+#endif
+
+#endif	/*  !MODE32  */
+	}
+}
+#endif	/*  DYNTRANS_UPDATE_TRANSLATION_TABLE  */
+
+
+/*****************************************************************************/
+
+
+#ifdef DYNTRANS_TO_BE_TRANSLATED_HEAD
+	/*
+	 *  Check for breakpoints.
+	 */
+	if (!single_step_breakpoint && !cpu->translation_readahead) {
+		MODE_uint_t curpc = cpu->pc;
+		int i;
+		for (i=0; i<cpu->machine->breakpoints.n; i++)
+			if (curpc == (MODE_uint_t)
+			    cpu->machine->breakpoints.addr[i]) {
+				if (!cpu->machine->instruction_trace) {
+					int tmp_old_quiet_mode = quiet_mode;
+					quiet_mode = 0;
+					DISASSEMBLE(cpu, ib, 1, 0);
+					quiet_mode = tmp_old_quiet_mode;
+				}
+#ifdef MODE32
+				fatal("BREAKPOINT: pc = 0x%" PRIx32"\n(The "
+				    "instruction has not yet executed.)\n",
+				    (uint32_t)cpu->pc);
+#else
+				fatal("BREAKPOINT: pc = 0x%" PRIx64"\n(The "
+				    "instruction has not yet executed.)\n",
+				    (uint64_t)cpu->pc);
+#endif
+#ifdef DYNTRANS_DELAYSLOT
+				if (cpu->delay_slot != NOT_DELAYED)
+					fatal("ERROR! Breakpoint in a delay"
+					    " slot! Not yet supported.\n");
+#endif
+				single_step_breakpoint = 1;
+				single_step = true;
+				goto stop_running_translated;
+			}
+	}
+#endif	/*  DYNTRANS_TO_BE_TRANSLATED_HEAD  */
+
+
+/*****************************************************************************/
+
+
+#ifdef DYNTRANS_TO_BE_TRANSLATED_TAIL
+	/*
+	 *  If we end up here, then an instruction was translated. Let's mark
+	 *  the page as containing a translation at this part of the page.
+	 */
+
+	/*  Make sure cur_physpage is in synch:  */
+	cpu->cd.DYNTRANS_ARCH.cur_physpage = (struct DYNTRANS_TC_PHYSPAGE *)
+	    cpu->cd.DYNTRANS_ARCH.cur_ic_page;
+
+	{
+		int x = addr & (DYNTRANS_PAGESIZE - 1);
+		int addr_per_translation_range = DYNTRANS_PAGESIZE / (8 *
+		    sizeof(cpu->cd.DYNTRANS_ARCH.cur_physpage->
+		    translations_bitmap));
+		x /= addr_per_translation_range;
+
+		cpu->cd.DYNTRANS_ARCH.cur_physpage->
+		    translations_bitmap |= (1 << x);
+	}
+
+
+	/*
+	 *  Now it is time to check for combinations of instructions that can
+	 *  be converted into a single function call.
+	 *
+	 *  Note: Single-stepping or instruction tracing doesn't work with
+	 *  instruction combinations. For architectures with delay slots,
+	 *  we also ignore combinations if the delay slot is across a page
+	 *  boundary.
+	 */
+	if (!single_step && !cpu->machine->instruction_trace
+#ifdef DYNTRANS_DELAYSLOT
+	    && !in_crosspage_delayslot
+#endif
+	    && cpu->cd.DYNTRANS_ARCH.combination_check != NULL
+	    && cpu->machine->allow_instruction_combinations) {
+		cpu->cd.DYNTRANS_ARCH.combination_check(cpu, ic,
+		    addr & (DYNTRANS_PAGESIZE - 1));
+	}
+
+	cpu->cd.DYNTRANS_ARCH.combination_check = NULL;
+
+	/*  An additional check, to catch some bugs:  */
+	if (ic->f == TO_BE_TRANSLATED) {
+		fatal("INTERNAL ERROR: ic->f not set!\n");
+		goto bad;
+	}
+	if (ic->f == NULL) {
+		fatal("INTERNAL ERROR: ic->f == NULL!\n");
+		goto bad;
+	}
+
+
+	/*
+	 *  ... and finally execute the translated instruction:
+	 */
+
+	/*  (Except when doing read-ahead!)  */
+	if (cpu->translation_readahead)
+		return;
+
+	/*
+	 *  Special case when single-stepping: Execute the translated
+	 *  instruction, but then replace it with a "to be translated"
+	 *  directly afterwards.
+	 */
+	if ((single_step_breakpoint && cpu->delay_slot == NOT_DELAYED)
+#ifdef DYNTRANS_DELAYSLOT
+	    || in_crosspage_delayslot
+#endif
+	    ) {
+		single_step_breakpoint = 0;
+		ic->f(cpu, ic);
+		ic->f = TO_BE_TRANSLATED;
+		return;
+	}
+
+
+	/*  Translation read-ahead:  */
+	if (!single_step && !cpu->machine->instruction_trace &&
+	    cpu->machine->breakpoints.n == 0) {
+		uint64_t baseaddr = cpu->pc;
+		uint64_t pagenr = DYNTRANS_ADDR_TO_PAGENR(baseaddr);
+		int i = 1;
+
+		cpu->translation_readahead = MAX_DYNTRANS_READAHEAD;
+
+		while (DYNTRANS_ADDR_TO_PAGENR(baseaddr +
+		    (i << DYNTRANS_INSTR_ALIGNMENT_SHIFT)) == pagenr &&
+		    cpu->translation_readahead > 0) {
+			void (*old_f)(struct cpu *,
+			    struct DYNTRANS_IC *) = ic[i].f;
+
+			/*  Already translated? Then abort:  */
+			if (old_f != TO_BE_TRANSLATED)
+				break;
+
+			/*  Translate the instruction:  */
+			ic[i].f(cpu, ic+i);
+
+			/*  Translation failed? Then abort.  */
+			if (ic[i].f == old_f)
+				break;
+
+			cpu->translation_readahead --;
+			++i;
+		}
+
+		cpu->translation_readahead = 0;
+	}
+
+
+	/*
+	 *  Finally finally :-), execute the instruction.
+	 *
+	 *  Note: The instruction might have changed during read-ahead, if
+	 *  instruction combinations are used.
+	 */
+
+	ic->f(cpu, ic);
+
+	return;
+
+
+bad:	/*
+	 *  Nothing was translated. (Unimplemented or illegal instruction.)
+	 */
+
+	/*  Clear the translation, in case it was "half-way" done:  */
+	ic->f = TO_BE_TRANSLATED;
+
+	if (cpu->translation_readahead)
+		return;
+
+
+	/*
+	 *  Abort the emulation.  In principle, it may have been more accurate
+	 *  to treat invalid/unimplemented instructions as something that
+	 *  should cause e.g. an exception (depending on how the particular
+	 *  CPU works), but chances are that this is an unimplemented
+	 *  instruction that should be implemented for real.
+	 */
+
+	about_to_enter_single_step = true;
+
+	if (cpu->is_32bit)
+		debugmsg_cpu(cpu, SUBSYS_CPU, "", VERBOSITY_ERROR,
+		    "UNIMPLEMENTED instruction at 0x%" PRIx32, (uint32_t)cpu->pc);
+	else
+		debugmsg_cpu(cpu, SUBSYS_CPU, "", VERBOSITY_ERROR,
+		    "UNIMPLEMENTED instruction at 0x%" PRIx64, (uint64_t)cpu->pc);
+
+	if (!(single_step || cpu->machine->instruction_trace))
+		DISASSEMBLE(cpu, ib, 1, 0);
+
+	cpu->running = 0;
+
+	/*  Note: Single-stepping can jump here.  */
+stop_running_translated:
+
+	// This makes sure that we stop in the debugger, even if e.g.
+	// "step 100" was executing and 50 steps remained.
+	debugger_reset();
+
+	ic = cpu->cd.DYNTRANS_ARCH.next_ic = &nothing_call;
+	cpu->cd.DYNTRANS_ARCH.next_ic ++;
+
+#ifdef DYNTRANS_DELAYSLOT
+	/*  Special hack: If the bad instruction was in a delay slot,
+	    make sure that execution does not continue anyway:  */
+	if (cpu->delay_slot)
+		cpu->delay_slot |= EXCEPTION_IN_DELAY_SLOT;
+#endif
+
+	/*  Execute the "nothing" instruction:  */
+	ic->f(cpu, ic);
+
+#endif	/*  DYNTRANS_TO_BE_TRANSLATED_TAIL  */
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_dyntrans.cc gxemul-0.7.0+dfsg/src/cpus/cpu_dyntrans.cc
--- gxemul-0.6.2/src/cpus/cpu_dyntrans.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_dyntrans.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1965 +0,0 @@
-/*
- *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Common dyntrans routines. Included from cpu_*.c.
- *
- *  Note: This might be a bit hard to follow, if you are reading this source
- *  code for the first time. It is basically a hack to implement "templates"
- *  with normal C code, by using suitable defines/macros, and then including
- *  this file.
- */
-
-
-#ifndef STATIC_STUFF
-#define	STATIC_STUFF
-/*
- *  gather_statistics():
- */
-static void gather_statistics(struct cpu *cpu)
-{
-	char ch, buf[60];
-	struct DYNTRANS_IC *ic = cpu->cd.DYNTRANS_ARCH.next_ic;
-	int i = 0;
-	uint64_t a;
-	int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - (size_t)
-	    cpu->cd.DYNTRANS_ARCH.cur_ic_page) / sizeof(struct DYNTRANS_IC);
-
-	if (cpu->machine->statistics.file == NULL) {
-		fatal("statistics gathering with no filename set is"
-		    " meaningless\n");
-		return;
-	}
-
-	/*  low_pc must be within the page!  */
-	if (low_pc < 0 || low_pc > DYNTRANS_IC_ENTRIES_PER_PAGE)
-		return;
-
-	buf[0] = '\0';
-
-	while ((ch = cpu->machine->statistics.fields[i]) != '\0') {
-		if (i != 0)
-			strlcat(buf, " ", sizeof(buf));
-
-		switch (ch) {
-		case 'i':
-			snprintf(buf + strlen(buf), sizeof(buf),
-			    "%p", (void *)ic->f);
-			break;
-		case 'p':
-			/*  Physical program counter address:  */
-			cpu->cd.DYNTRANS_ARCH.cur_physpage = (struct DYNTRANS_TC_PHYSPAGE *)
-			    cpu->cd.DYNTRANS_ARCH.cur_ic_page;
-			a = cpu->cd.DYNTRANS_ARCH.cur_physpage->physaddr;
-			a &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) <<
-			    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
-			a += low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT;
-			if (cpu->is_32bit)
-				snprintf(buf + strlen(buf), sizeof(buf),
-				    "0x%08" PRIx32, (uint32_t)a);
-			else
-				snprintf(buf + strlen(buf), sizeof(buf),
-				    "0x%016" PRIx64, (uint64_t)a);
-			break;
-		case 'v':
-			/*  Virtual program counter address:  */
-			a = cpu->pc;
-			a &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) <<
-			    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
-			a += low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT;
-			if (cpu->is_32bit)
-				snprintf(buf + strlen(buf), sizeof(buf),
-				    "0x%08" PRIx32, (uint32_t)a);
-			else
-				snprintf(buf + strlen(buf), sizeof(buf),
-				    "0x%016" PRIx64, (uint64_t)a);
-			break;
-		}
-		i++;
-	}
-
-	fprintf(cpu->machine->statistics.file, "%s\n", buf);
-}
-
-
-#define S		gather_statistics(cpu)
-
-
-#if 1
-
-/*  The normal instruction execution core:  */
-#define I	ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; ic->f(cpu, ic);
-
-#else
-
-/*  For heavy debugging:  */
-#define I	ic = cpu->cd.DYNTRANS_ARCH.next_ic ++;	\
-		{	\
-			int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - \
-			    (size_t)cpu->cd.DYNTRANS_ARCH.cur_ic_page) / \
-			    sizeof(struct DYNTRANS_IC);			\
-			printf("cur_ic_page=%p ic=%p (low_pc=0x%x)\n",	\
-			    cpu->cd.DYNTRANS_ARCH.cur_ic_page,		\
-			    ic, low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT); \
-		} \
-		ic->f(cpu, ic);
-
-#endif
-
-/*  static long long nr_of_I_calls = 0;  */
-
-/*  Temporary hack for finding NULL bugs:  */
-/*  #define I	ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; 			\
-		nr_of_I_calls ++;					\
-		if (ic->f == NULL) {					\
-			int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - \
-			    (size_t)cpu->cd.DYNTRANS_ARCH.cur_ic_page) / \
-			    sizeof(struct DYNTRANS_IC);			\
-			cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << \
-			    DYNTRANS_INSTR_ALIGNMENT_SHIFT);		\
-			cpu->pc += (low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT);\
-			printf("Crash at %016" PRIx64"\n", cpu->pc);	\
-			printf("nr of I calls: %lli\n", nr_of_I_calls);	\
-			printf("Next ic = %p\n", cpu->cd.		\
-				DYNTRANS_ARCH.next_ic);			\
-			printf("cur ic page = %p\n", cpu->cd.		\
-				DYNTRANS_ARCH.cur_ic_page);		\
-			cpu->running = 0;				\
-			return 0;					\
-		}							\
-		ic->f(cpu, ic);  */
-
-/*  Temporary hack for MIPS, to hunt for 32-bit/64-bit sign-extension bugs:  */
-/*  #define I		{ int k; for (k=1; k<=31; k++)	\
-	cpu->cd.mips.gpr[k] = (int32_t)cpu->cd.mips.gpr[k];\
-	if (cpu->cd.mips.gpr[0] != 0) {			\
-		fatal("NOOOOOO\n"); exit(1);		\
-	}						\
-	ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; ic->f(cpu, ic); }
-*/
-#endif	/*  STATIC STUFF  */
-
-
-
-#ifdef	DYNTRANS_RUN_INSTR_DEF
-/*
- *  XXX_run_instr():
- *
- *  Execute one or more instructions on a specific CPU, using dyntrans.
- *  (For dualmode archs, this function is included twice.)
- *
- *  Return value is the number of instructions executed during this call,
- *  0 if no instructions were executed.
- */
-int DYNTRANS_RUN_INSTR_DEF(struct cpu *cpu)
-{
-	MODE_uint_t cached_pc;
-	int low_pc, n_instrs;
-
-	/*  Ugly... fix this some day.  */
-#ifdef DYNTRANS_DUALMODE_32
-#ifdef MODE32
-	DYNTRANS_PC_TO_POINTERS32(cpu);
-#else
-	DYNTRANS_PC_TO_POINTERS(cpu);
-#endif
-#else
-	DYNTRANS_PC_TO_POINTERS(cpu);
-#endif
-
-	/*
-	 *  Interrupt assertion?  (This is _below_ the initial PC to pointer
-	 *  conversion; if the conversion caused an exception of some kind
-	 *  then interrupts are probably disabled, and the exception will get
-	 *  priority over device interrupts.)
-	 *
-	 *  TODO: Turn this into a family-specific function somewhere...
- 	 */
-
-	/*  Note: Do not cause interrupts while single-stepping. It is
-	    so horribly annoying.  */
-	if (!single_step) {
-#ifdef DYNTRANS_ARM
-		if (cpu->cd.arm.irq_asserted && !(cpu->cd.arm.cpsr & ARM_FLAG_I))
-			arm_exception(cpu, ARM_EXCEPTION_IRQ);
-#endif
-#ifdef DYNTRANS_M88K
-		if (cpu->cd.m88k.irq_asserted &&
-		    !(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_IND))
-			m88k_exception(cpu, M88K_EXCEPTION_INTERRUPT, 0);
-#endif
-#ifdef DYNTRANS_MIPS
-		int enabled, mask;
-		int status = cpu->cd.mips.coproc[0]->reg[COP0_STATUS];
-		if (cpu->cd.mips.cpu_type.exc_model == EXC3K) {
-			/*  R3000:  */
-			enabled = status & MIPS_SR_INT_IE;
-		} else {
-			/*  R4000 and others:  */
-			enabled = (status & STATUS_IE)
-			    && !(status & STATUS_EXL) && !(status & STATUS_ERL);
-			/*  Special case for R5900/C790/TX79:  */
-			if (cpu->cd.mips.cpu_type.rev == MIPS_R5900 &&
-			    !(status & R5900_STATUS_EIE))
-				enabled = 0;
-		}
-		mask = status & cpu->cd.mips.coproc[0]->reg[COP0_CAUSE]
-		    & STATUS_IM_MASK;
-
-		if (enabled && mask)
-			mips_cpu_exception(cpu, EXCEPTION_INT, 0, 0, 0, 0, 0,0);
-#endif
-#ifdef DYNTRANS_PPC
-		if (cpu->cd.ppc.dec_intr_pending && cpu->cd.ppc.msr & PPC_MSR_EE) {
-			if (!(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC))
-				ppc_exception(cpu, PPC_EXCEPTION_DEC);
-			cpu->cd.ppc.dec_intr_pending = 0;
-		}
-		if (cpu->cd.ppc.irq_asserted && cpu->cd.ppc.msr & PPC_MSR_EE)
-			ppc_exception(cpu, PPC_EXCEPTION_EI);
-#endif
-#ifdef DYNTRANS_SH
-		if (cpu->cd.sh.int_to_assert > 0 && !(cpu->cd.sh.sr & SH_SR_BL)
-		    && ((cpu->cd.sh.sr & SH_SR_IMASK) >> SH_SR_IMASK_SHIFT)
-		    < cpu->cd.sh.int_level)
-			sh_exception(cpu, 0, cpu->cd.sh.int_to_assert, 0);
-#endif
-	}
-
-#ifdef DYNTRANS_ARM
-	if (cpu->cd.arm.cpsr & ARM_FLAG_T) {
-		// fatal("THUMB execution not implemented.\n");
-		// cpu->running = false;
-		// return 0;
-		
-		arm_cpu_interpret_thumb_SLOW(cpu);
-		return 1;
-	}
-#endif
-
-	cached_pc = cpu->pc;
-
-	cpu->n_translated_instrs = 0;
-
-	cpu->cd.DYNTRANS_ARCH.cur_physpage = (struct DYNTRANS_TC_PHYSPAGE *)
-	    cpu->cd.DYNTRANS_ARCH.cur_ic_page;
-
-	if (single_step || cpu->machine->instruction_trace
-	    || cpu->machine->register_dump) {
-		/*
-		 *  Single-step:
-		 */
-		struct DYNTRANS_IC *ic = cpu->cd.DYNTRANS_ARCH.next_ic;
-		if (cpu->machine->register_dump) {
-			debug("\n");
-			cpu_register_dump(cpu->machine, cpu, 1, 0x1);
-		}
-		if (cpu->machine->instruction_trace) {
-			/*  TODO/Note: This must be large enough to hold
-			    any instruction for any ISA:  */
-			unsigned char instr[1 <<
-			    DYNTRANS_INSTR_ALIGNMENT_SHIFT];
-			if (!cpu->memory_rw(cpu, cpu->mem, cached_pc, &instr[0],
-			    sizeof(instr), MEM_READ, CACHE_INSTRUCTION)) {
-				fatal("XXX_run_instr(): could not read "
-				    "the instruction\n");
-			} else {
-#ifdef DYNTRANS_DELAYSLOT
-				int len =
-#endif
-				    cpu_disassemble_instr(
-				    cpu->machine, cpu, instr, 1, cpu->pc);
-#ifdef DYNTRANS_DELAYSLOT
-				/*  Show the instruction in the delay slot,
-				    if any:  */
-				if (cpu->instruction_has_delayslot == NULL)
-					fatal("WARNING: ihd func not yet"
-					    " implemented?\n");
-				else if (cpu->instruction_has_delayslot(cpu,
-				    instr)) {
-					int saved_delayslot = cpu->delay_slot;
-					cpu->memory_rw(cpu, cpu->mem, cached_pc
-					    + len, &instr[0],
-					    sizeof(instr), MEM_READ,
-					    CACHE_INSTRUCTION);
-					cpu->delay_slot = DELAYED;
-					cpu->pc += len;
-					cpu_disassemble_instr(cpu->machine,
-					    cpu, instr, 1, cpu->pc);
-					cpu->delay_slot = saved_delayslot;
-					cpu->pc -= len;
-				}
-#endif
-			}
-		}
-
-		if (cpu->machine->statistics.enabled)
-			S;
-
-		/*  Execute just one instruction:  */
-		I;
-
-		n_instrs = 1;
-	} else if (cpu->machine->statistics.enabled) {
-		/*  Gather statistics while executing multiple instructions:  */
-		n_instrs = 0;
-		for (;;) {
-			struct DYNTRANS_IC *ic;
-
-			S; I; S; I; S; I; S; I; S; I; S; I;
-			S; I; S; I; S; I; S; I; S; I; S; I;
-			S; I; S; I; S; I; S; I; S; I; S; I;
-			S; I; S; I; S; I; S; I; S; I; S; I;
-
-			n_instrs += 24;
-
-			if (n_instrs + cpu->n_translated_instrs >=
-			    N_SAFE_DYNTRANS_LIMIT)
-				break;
-		}
-	} else {
-		/*
-		 *  Execute multiple instructions:
-		 *
-		 *  (This is the core dyntrans loop.)
-		 */
-		n_instrs = 0;
-
-		for (;;) {
-			struct DYNTRANS_IC *ic;
-
-			I; I; I; I; I;   I; I; I; I; I;
-			I; I; I; I; I;   I; I; I; I; I;
-			I; I; I; I; I;   I; I; I; I; I;
-			I; I; I; I; I;   I; I; I; I; I;
-			I; I; I; I; I;   I; I; I; I; I;
-
-			I; I; I; I; I;   I; I; I; I; I;
-
-			I; I; I; I; I;   I; I; I; I; I;
-			I; I; I; I; I;   I; I; I; I; I;
-			I; I; I; I; I;   I; I; I; I; I;
-			I; I; I; I; I;   I; I; I; I; I;
-			I; I; I; I; I;   I; I; I; I; I;
-
-			I; I; I; I; I;   I; I; I; I; I;
-
-			cpu->n_translated_instrs += 120;
-			if (cpu->n_translated_instrs >= N_SAFE_DYNTRANS_LIMIT)
-				break;
-		}
-	}
-
-	n_instrs += cpu->n_translated_instrs;
-
-	/*  Synchronize the program counter:  */
-	low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - (size_t)
-	    cpu->cd.DYNTRANS_ARCH.cur_ic_page) / sizeof(struct DYNTRANS_IC);
-	if (low_pc >= 0 && low_pc < DYNTRANS_IC_ENTRIES_PER_PAGE) {
-		cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) <<
-		    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT);
-	} else if (low_pc == DYNTRANS_IC_ENTRIES_PER_PAGE) {
-		/*  Switch to next page:  */
-		cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) <<
-		    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (DYNTRANS_IC_ENTRIES_PER_PAGE <<
-		    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
-	} else if (low_pc == DYNTRANS_IC_ENTRIES_PER_PAGE + 1) {
-		/*  Switch to next page and skip an instruction which was
-		    already executed (in a delay slot):  */
-		cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) <<
-		    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += ((DYNTRANS_IC_ENTRIES_PER_PAGE + 1) <<
-		    DYNTRANS_INSTR_ALIGNMENT_SHIFT);
-	}
-
-#ifdef DYNTRANS_MIPS
-	/*  Update the count register (on everything except EXC3K):  */
-	if (cpu->cd.mips.cpu_type.exc_model != EXC3K) {
-		uint32_t old;
-		int32_t diff1, diff2;
-		cpu->cd.mips.coproc[0]->reg[COP0_COUNT] -= cpu->cd.mips.count_register_read_count;
-		cpu->cd.mips.count_register_read_count = 0;
-		old = cpu->cd.mips.coproc[0]->reg[COP0_COUNT];
-		diff1 = cpu->cd.mips.coproc[0]->reg[COP0_COMPARE] - old;
-		cpu->cd.mips.coproc[0]->reg[COP0_COUNT] =
-		    (int32_t) (old + n_instrs);
-		diff2 = cpu->cd.mips.coproc[0]->reg[COP0_COMPARE] -
-		    cpu->cd.mips.coproc[0]->reg[COP0_COUNT];
-
-		if (cpu->cd.mips.compare_register_set) {
-#if 1
-/*  Not yet.  TODO  */
-			if (cpu->machine->emulated_hz > 0) {
-				if (cpu->cd.mips.compare_interrupts_pending > 0)
-					INTERRUPT_ASSERT(
-					    cpu->cd.mips.irq_compare);
-			} else
-#endif
-			{
-				if (diff1 > 0 && diff2 <= 0)
-					INTERRUPT_ASSERT(
-					    cpu->cd.mips.irq_compare);
-			}
-		}
-	}
-#endif
-#ifdef DYNTRANS_PPC
-	/*  Update the Decrementer and Time base registers:  */
-	{
-		uint32_t old = cpu->cd.ppc.spr[SPR_DEC];
-		cpu->cd.ppc.spr[SPR_DEC] = (uint32_t) (old - n_instrs);
-		if ((old >> 31) == 0 && (cpu->cd.ppc.spr[SPR_DEC] >> 31) == 1
-		    && !(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC))
-			cpu->cd.ppc.dec_intr_pending = 1;
-		old = cpu->cd.ppc.spr[SPR_TBL];
-		cpu->cd.ppc.spr[SPR_TBL] += n_instrs;
-		if ((old >> 31) == 1 && (cpu->cd.ppc.spr[SPR_TBL] >> 31) == 0)
-			cpu->cd.ppc.spr[SPR_TBU] ++;
-	}
-#endif
-
-	cpu->ninstrs += n_instrs;
-
-	/*  Return the nr of instructions executed:  */
-	return n_instrs;
-}
-#endif	/*  DYNTRANS_RUN_INSTR  */
-
-
-
-#ifdef DYNTRANS_FUNCTION_TRACE_DEF
-/*
- *  XXX_cpu_functioncall_trace():
- *
- *  Without this function, the main trace tree function prints something
- *  like    <f()>  or  <0x1234()>   on a function call. It is up to this
- *  function to print the arguments passed.
- */
-void DYNTRANS_FUNCTION_TRACE_DEF(struct cpu *cpu, int n_args)
-{
-	int show_symbolic_function_name = 1;
-        char strbuf[55];
-	char *symbol;
-	uint64_t ot;
-	int x, print_dots = 1, n_args_to_print =
-#if defined(DYNTRANS_ALPHA)
-	    6
-#else
-#if defined(DYNTRANS_SH) || defined(DYNTRANS_M88K)
-	    8	/*  Both for 32-bit and 64-bit SuperH, and M88K  */
-#else
-	    4	/*  Default value for most archs  */
-#endif
-#endif
-	    ;
-
-	if (n_args >= 0 && n_args <= n_args_to_print) {
-		print_dots = 0;
-		n_args_to_print = n_args;
-	}
-
-#ifdef DYNTRANS_M88K
-	/*  Special hack for M88K userspace:  */
-	if (!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE))
-		show_symbolic_function_name = 0;
-#endif
-
-
-	/*
-	 *  TODO: The type of each argument should be taken from the symbol
-	 *  table, in some way.
-	 *
-	 *  The code here does a kind of "heuristic guess" regarding what the
-	 *  argument values might mean. Sometimes the output looks weird, but
-	 *  usually it looks good enough.
-	 *
-	 *  Print ".." afterwards to show that there might be more arguments
-	 *  than were passed in register.
-	 */
-	for (x=0; x<n_args_to_print; x++) {
-		int64_t d = cpu->cd.DYNTRANS_ARCH.
-#ifdef DYNTRANS_ALPHA
-		    r[ALPHA_A0
-#endif
-#ifdef DYNTRANS_ARM
-		    r[0
-#endif
-#ifdef DYNTRANS_MIPS
-		    gpr[MIPS_GPR_A0
-#endif
-#ifdef DYNTRANS_M88K
-		    r[2		/*  r2..r9  */
-#endif
-#ifdef DYNTRANS_PPC
-		    gpr[3
-#endif
-#ifdef DYNTRANS_SH
-		    r[4		/*  NetBSD seems to use 4? But 2 seems
-					to be used by other code? TODO  */
-#endif
-		    + x];
-
-		symbol = get_symbol_name(&cpu->machine->symbol_context, d, &ot);
-
-		if (d > -256 && d < 256)
-			fatal("%i", (int)d);
-		else if (memory_points_to_string(cpu, cpu->mem, d, 1)) {
-			memset(strbuf, 0, sizeof(strbuf));
-			memory_conv_to_string(cpu,
-			    cpu->mem, d, strbuf, sizeof(strbuf));
-			fatal("\"%s\"", strbuf);
-			// TODO: This shows "..." when the string is longer
-			// _or exactly the max length_. An improvement would
-			// be to detect the case where the string is exactly
-			// the max length and not show "..." then.
-			if (strlen(strbuf) >= sizeof(strbuf)-1)
-				fatal("...");
-		} else if (symbol != NULL && ot == 0 &&
-		    show_symbolic_function_name)
-			fatal("&%s", symbol);
-		else {
-			if (cpu->is_32bit)
-				fatal("0x%" PRIx32, (uint32_t)d);
-			else
-				fatal("0x%" PRIx64, (uint64_t)d);
-		}
-
-		if (x < n_args_to_print - 1)
-			fatal(",");
-	}
-
-	if (print_dots)
-		fatal(",..");
-}
-#endif	/*  DYNTRANS_FUNCTION_TRACE_DEF  */
-
-
-
-#ifdef DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE_DEF
-/*
- *  XXX_tc_allocate_default_page():
- *
- *  Create a default page (with just pointers to instr(to_be_translated)
- *  at cpu->translation_cache_cur_ofs.
- */
-static void DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE_DEF(struct cpu *cpu,
-	uint64_t physaddr)
-{ 
-	struct DYNTRANS_TC_PHYSPAGE *ppp;
-
-	ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache
-	    + cpu->translation_cache_cur_ofs);
-
-	/*  Copy the entire template page first:  */
-	memcpy(ppp, cpu->cd.DYNTRANS_ARCH.physpage_template, sizeof(
-	    struct DYNTRANS_TC_PHYSPAGE));
-
-	ppp->physaddr = physaddr & ~(DYNTRANS_PAGESIZE - 1);
-
-	cpu->translation_cache_cur_ofs += sizeof(struct DYNTRANS_TC_PHYSPAGE);
-
-	cpu->translation_cache_cur_ofs --;
-	cpu->translation_cache_cur_ofs |= 63;
-	cpu->translation_cache_cur_ofs ++;
-}
-#endif	/*  DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE_DEF  */
-
-
-
-#ifdef DYNTRANS_PC_TO_POINTERS_FUNC
-/*
- *  XXX_pc_to_pointers_generic():
- *
- *  Generic case. See DYNTRANS_PC_TO_POINTERS_FUNC below.
- */
-void DYNTRANS_PC_TO_POINTERS_GENERIC(struct cpu *cpu)
-{
-#ifdef MODE32
-	uint32_t
-#else
-	uint64_t
-#endif
-	    cached_pc = cpu->pc, physaddr = 0;
-	uint32_t physpage_ofs;
-	int ok, pagenr, table_index;
-	uint32_t *physpage_entryp;
-	struct DYNTRANS_TC_PHYSPAGE *ppp;
-
-#ifdef MODE32
-	int index = DYNTRANS_ADDR_TO_PAGENR(cached_pc);
-#else
-	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
-	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
-	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
-	uint32_t x1, x2, x3;
-	struct DYNTRANS_L2_64_TABLE *l2;
-	struct DYNTRANS_L3_64_TABLE *l3;
-
-	x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1;
-	x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
-	x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
-	/*  fatal("X3: cached_pc=%016" PRIx64" x1=%x x2=%x x3=%x\n",
-	    (uint64_t)cached_pc, (int)x1, (int)x2, (int)x3);  */
-	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
-	/*  fatal("  l2 = %p\n", l2);  */
-	l3 = l2->l3[x2];
-	/*  fatal("  l3 = %p\n", l3);  */
-#endif
-
-	/*  Virtual to physical address translation:  */
-	ok = 0;
-#ifdef MODE32
-	if (cpu->cd.DYNTRANS_ARCH.host_load[index] != NULL) {
-		physaddr = cpu->cd.DYNTRANS_ARCH.phys_addr[index];
-		ok = 1;
-	}
-#else
-	if (l3->host_load[x3] != NULL) {
-		physaddr = l3->phys_addr[x3];
-		ok = 1;
-	}
-#endif
-
-	if (!ok) {
-		uint64_t paddr;
-		if (cpu->translate_v2p != NULL) {
-			uint64_t vaddr =
-#if defined(MODE32) && defined(DYNTRANS_MIPS)
-			/*  32-bit MIPS is _sign_ extend, not zero.  */
-			    (int32_t)
-#endif
-			    cached_pc;
-			ok = cpu->translate_v2p(
-			    cpu, vaddr, &paddr, FLAG_INSTR);
-		} else {
-			paddr = cached_pc;
-			ok = 1;
-		}
-		if (!ok) {
-			/*
-			 *  The PC is now set to the exception handler.
-			 *  Try to find the paddr in the translation arrays,
-			 *  or if that fails, call translate_v2p for the
-			 *  exception handler.
-			 */
-			/*  fatal("TODO: instruction vaddr=>paddr translation "
-			    "failed. vaddr=0x%" PRIx64"\n", (uint64_t)cached_pc);
-			fatal("!! cpu->pc=0x%" PRIx64"\n", (uint64_t)cpu->pc); */
-
-			/*  If there was an exception, the PC has changed.
-			    Update cached_pc:  */
-			cached_pc = cpu->pc;
-
-#ifdef MODE32
-			index = DYNTRANS_ADDR_TO_PAGENR(cached_pc);
-			if (cpu->cd.DYNTRANS_ARCH.host_load[index] != NULL) {
-				paddr = cpu->cd.DYNTRANS_ARCH.phys_addr[index];
-				ok = 1;
-			}
-#else
-			x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1;
-			x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N))
-			    & mask2;
-			x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N
-			    - DYNTRANS_L3N)) & mask3;
-			l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
-			l3 = l2->l3[x2];
-			if (l3->host_load[x3] != NULL) {
-				paddr = l3->phys_addr[x3];
-				ok = 1;
-			}
-#endif
-
-			if (!ok) {
-				ok = cpu->translate_v2p(cpu, cpu->pc, &paddr,
-				    FLAG_INSTR);
-			}
-
-			/*  printf("EXCEPTION HANDLER: vaddr = 0x%x ==> "
-			    "paddr = 0x%x\n", (int)cpu->pc, (int)paddr);
-			fatal("!? cpu->pc=0x%" PRIx64"\n", (uint64_t)cpu->pc); */
-
-			if (!ok) {
-				fatal("FATAL: could not find physical"
-				    " address of the exception handler?");
-				exit(1);
-			}
-		}
-
-		physaddr = paddr;
-	}
-
-	physaddr &= ~(DYNTRANS_PAGESIZE - 1);
-
-#ifdef MODE32
-	if (cpu->cd.DYNTRANS_ARCH.host_load[index] == NULL) {
-#else
-	if (l3->host_load[x3] == NULL) {
-#endif
-		int q = DYNTRANS_PAGESIZE - 1;
-		unsigned char *host_page = memory_paddr_to_hostaddr(cpu->mem,
-		    physaddr, MEM_READ);
-		if (host_page != NULL) {
-			cpu->update_translation_table(cpu, cached_pc & ~q,
-			    host_page, 0, physaddr);
-		}
-	}
-
-	if (cpu->translation_cache_cur_ofs >= dyntrans_cache_size) {
-#ifdef UNSTABLE_DEVEL
-		fatal("[ dyntrans: resetting the translation cache ]\n");
-#endif
-		cpu_create_or_reset_tc(cpu);
-	}
-
-	pagenr = DYNTRANS_ADDR_TO_PAGENR(physaddr);
-	table_index = PAGENR_TO_TABLE_INDEX(pagenr);
-
-	physpage_entryp = &(((uint32_t *)cpu->translation_cache)[table_index]);
-	physpage_ofs = *physpage_entryp;
-	ppp = NULL;
-
-	/*  Traverse the physical page chain:  */
-	while (physpage_ofs != 0) {
-		ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache
-		    + physpage_ofs);
-
-		/*  If we found the page in the cache, then we're done:  */
-		if (ppp->physaddr == physaddr)
-			break;
-
-		/*  Try the next page in the chain:  */
-		physpage_ofs = ppp->next_ofs;
-	}
-
-	/*
-	 *  If the offset is 0, then no translation exists yet for this
-	 *  physical address. Let's create a new page, and add it first in
-	 *  the chain.
-	 */
-	if (physpage_ofs == 0) {
-		uint32_t previous_first_page_in_chain;
-
-		/*  fatal("CREATING page %lli (physaddr 0x%" PRIx64"), table "
-		    "index %i\n", (long long)pagenr, (uint64_t)physaddr,
-		    (int)table_index);  */
-
-		previous_first_page_in_chain = *physpage_entryp;
-
-		/*  Insert the new page first in the chain:  */
-		*physpage_entryp = physpage_ofs =
-		    cpu->translation_cache_cur_ofs;
-
-		/*  Allocate a default page, with to_be_translated entries:  */
-		DYNTRANS_TC_ALLOCATE(cpu, physaddr);
-
-		ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache
-		    + physpage_ofs);
-
-		/*  Point to the other pages in the same chain:  */
-		ppp->next_ofs = previous_first_page_in_chain;
-	}
-
-	/*  Here, ppp points to a valid physical page struct.  */
-
-#ifdef MODE32
-	if (cpu->cd.DYNTRANS_ARCH.host_load[index] != NULL)
-		cpu->cd.DYNTRANS_ARCH.phys_page[index] = ppp;
-#else
-	if (l3->host_load[x3] != NULL)
-		l3->phys_page[x3] = ppp;
-#endif
-
-	/*
-	 *  If there are no translations yet on this page, then mark it
-	 *  as non-writable. If there are already translations, then it
-	 *  should already have been marked as non-writable.
-	 */
-	if (ppp->translations_bitmap == 0) {
-		cpu->invalidate_translation_caches(cpu, physaddr,
-		    JUST_MARK_AS_NON_WRITABLE | INVALIDATE_PADDR);
-	}
-
-	cpu->cd.DYNTRANS_ARCH.cur_ic_page = &ppp->ics[0];
-
-	cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page +
-	    DYNTRANS_PC_TO_IC_ENTRY(cached_pc);
-
-	/*  printf("cached_pc=0x%016" PRIx64"  pagenr=%lli  table_index=%lli, "
-	    "physpage_ofs=0x%016" PRIx64"\n", (uint64_t)cached_pc, (long long)
-	    pagenr, (long long)table_index, (uint64_t)physpage_ofs);  */
-}
-
-
-/*
- *  XXX_pc_to_pointers():
- *
- *  This function uses the current program counter (a virtual address) to
- *  find out which physical translation page to use, and then sets the current
- *  translation page pointers to that page.
- *
- *  If there was no translation page for that physical page, then an empty
- *  one is created.
- *
- *  NOTE: This is the quick lookup version. See
- *  DYNTRANS_PC_TO_POINTERS_GENERIC above for the generic case.
- */
-void DYNTRANS_PC_TO_POINTERS_FUNC(struct cpu *cpu)
-{
-#ifdef MODE32
-	uint32_t
-#else
-	uint64_t
-#endif
-	    cached_pc = cpu->pc;
-	struct DYNTRANS_TC_PHYSPAGE *ppp;
-
-#ifdef MODE32
-	int index;
-	index = DYNTRANS_ADDR_TO_PAGENR(cached_pc);
-	ppp = cpu->cd.DYNTRANS_ARCH.phys_page[index];
-	if (ppp != NULL)
-		goto have_it;
-#else
-	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
-	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
-	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
-	uint32_t x1, x2, x3;
-	struct DYNTRANS_L2_64_TABLE *l2;
-	struct DYNTRANS_L3_64_TABLE *l3;
-
-	x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1;
-	x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
-	x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
-	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
-	l3 = l2->l3[x2];
-	ppp = l3->phys_page[x3];
-	if (ppp != NULL)
-		goto have_it;
-#endif
-
-	DYNTRANS_PC_TO_POINTERS_GENERIC(cpu);
-	return;
-
-	/*  Quick return path:  */
-have_it:
-	cpu->cd.DYNTRANS_ARCH.cur_ic_page = &ppp->ics[0];
-	cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page +
-	    DYNTRANS_PC_TO_IC_ENTRY(cached_pc);
-
-	/*  printf("cached_pc=0x%016" PRIx64"  pagenr=%lli  table_index=%lli, "
-	    "physpage_ofs=0x%016" PRIx64"\n", (uint64_t)cached_pc, (long long)
-	    pagenr, (long long)table_index, (uint64_t)physpage_ofs);  */
-}
-#endif	/*  DYNTRANS_PC_TO_POINTERS_FUNC  */
-
-
-
-#ifdef DYNTRANS_INIT_TABLES
-
-/*  forward declaration of to_be_translated and end_of_page:  */
-static void instr(to_be_translated)(struct cpu *, struct DYNTRANS_IC *);
-static void instr(end_of_page)(struct cpu *,struct DYNTRANS_IC *);
-#ifdef DYNTRANS_DUALMODE_32
-static void instr32(to_be_translated)(struct cpu *, struct DYNTRANS_IC *);
-static void instr32(end_of_page)(struct cpu *,struct DYNTRANS_IC *);
-#endif
-
-#ifdef DYNTRANS_DUALMODE_32
-#define TO_BE_TRANSLATED    ( cpu->is_32bit? instr32(to_be_translated) : \
-			      instr(to_be_translated) )
-#else
-#define TO_BE_TRANSLATED    ( instr(to_be_translated) )
-#endif
-
-#ifdef DYNTRANS_DELAYSLOT
-static void instr(end_of_page2)(struct cpu *,struct DYNTRANS_IC *);
-#ifdef DYNTRANS_DUALMODE_32
-static void instr32(end_of_page2)(struct cpu *,struct DYNTRANS_IC *);
-#endif
-#endif
-
-/*
- *  XXX_init_tables():
- *
- *  Initializes the default translation page (for newly allocated pages), and
- *  for 64-bit emulation it also initializes 64-bit dummy tables and pointers.
- */
-void DYNTRANS_INIT_TABLES(struct cpu *cpu)
-{
-#ifndef MODE32
-	struct DYNTRANS_L2_64_TABLE *dummy_l2;
-	struct DYNTRANS_L3_64_TABLE *dummy_l3;
-	int x1, x2;
-#endif
-	int i;
-	struct DYNTRANS_TC_PHYSPAGE *ppp;
-
-	CHECK_ALLOCATION(ppp =
-	    (struct DYNTRANS_TC_PHYSPAGE *) malloc(sizeof(struct DYNTRANS_TC_PHYSPAGE)));
-
-	ppp->next_ofs = 0;
-	ppp->translations_bitmap = 0;
-	ppp->translation_ranges_ofs = 0;
-	/*  ppp->physaddr is filled in by the page allocator  */
-
-	for (i=0; i<DYNTRANS_IC_ENTRIES_PER_PAGE; i++)
-		ppp->ics[i].f = TO_BE_TRANSLATED;
-
-	/*  End-of-page:  */
-	ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE + 0].f =
-#ifdef DYNTRANS_DUALMODE_32
-	    cpu->is_32bit? instr32(end_of_page) :
-#endif
-	    instr(end_of_page);
-
-	/*  End-of-page-2, for delay-slot architectures:  */
-#ifdef DYNTRANS_DELAYSLOT
-	ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE + 1].f =
-#ifdef DYNTRANS_DUALMODE_32
-	    cpu->is_32bit? instr32(end_of_page2) :
-#endif
-	    instr(end_of_page2);
-#endif
-
-	cpu->cd.DYNTRANS_ARCH.physpage_template = ppp;
-
-
-	/*  Prepare 64-bit virtual address translation tables:  */
-#ifndef MODE32
-	if (cpu->is_32bit)
-		return;
-
-	dummy_l2 = (struct DYNTRANS_L2_64_TABLE *) zeroed_alloc(sizeof(struct DYNTRANS_L2_64_TABLE));
-	dummy_l3 = (struct DYNTRANS_L3_64_TABLE *) zeroed_alloc(sizeof(struct DYNTRANS_L3_64_TABLE));
-
-	cpu->cd.DYNTRANS_ARCH.l2_64_dummy = dummy_l2;
-	cpu->cd.DYNTRANS_ARCH.l3_64_dummy = dummy_l3;
-
-	for (x1 = 0; x1 < (1 << DYNTRANS_L1N); x1 ++)
-		cpu->cd.DYNTRANS_ARCH.l1_64[x1] = dummy_l2;
-
-	for (x2 = 0; x2 < (1 << DYNTRANS_L2N); x2 ++)
-		dummy_l2->l3[x2] = dummy_l3;
-#endif
-}
-#endif	/*  DYNTRANS_INIT_TABLES  */
-
-
-
-#ifdef DYNTRANS_INVAL_ENTRY
-/*
- *  XXX_invalidate_tlb_entry():
- *
- *  Invalidate one translation entry (based on virtual address).
- *
- *  If the JUST_MARK_AS_NON_WRITABLE flag is set, then the translation entry
- *  is just downgraded to non-writable (ie the host store page is set to
- *  NULL). Otherwise, the entire translation is removed.
- */
-static void DYNTRANS_INVALIDATE_TLB_ENTRY(struct cpu *cpu,
-#ifdef MODE32
-	uint32_t
-#else
-	uint64_t
-#endif
-	vaddr_page, int flags)
-{
-#ifdef MODE32
-	uint32_t index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page);
-
-#ifdef DYNTRANS_ARM
-	cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 5] &= ~(1 << (index & 31));
-#endif
-
-	if (flags & JUST_MARK_AS_NON_WRITABLE) {
-		/*  printf("JUST MARKING NON-W: vaddr 0x%08x\n",
-		    (int)vaddr_page);  */
-		cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL;
-	} else {
-		int tlbi = cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index];
-		cpu->cd.DYNTRANS_ARCH.host_load[index] = NULL;
-		cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL;
-		cpu->cd.DYNTRANS_ARCH.phys_addr[index] = 0;
-		cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL;
-		if (tlbi > 0)
-			cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[tlbi-1].valid = 0;
-		cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index] = 0;
-	}
-#else
-	// 64-bit:
-	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
-	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
-	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
-	uint32_t x1, x2, x3;
-	struct DYNTRANS_L2_64_TABLE *l2;
-	struct DYNTRANS_L3_64_TABLE *l3;
-
-	x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1;
-	x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
-	x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N))& mask3;
-
-	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
-	if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy)
-		return;
-
-	l3 = l2->l3[x2];
-	if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy)
-		return;
-
-	if (flags & JUST_MARK_AS_NON_WRITABLE) {
-		l3->host_store[x3] = NULL;
-		return;
-	}
-
-#ifdef BUGHUNT
-
-{
-	/*  Consistency check, for debugging:  */
-	int x1, x1b; // x2, x3;
-	struct DYNTRANS_L2_64_TABLE *l2;
-	//struct DYNTRANS_L3_64_TABLE *l3;
-
-	for (x1 = 0; x1 <= mask1; x1 ++) {
-		l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
-		if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy)
-			continue;
-		/*  Make sure that this l2 isn't used more than 1 time!  */
-		for (x1b = 0; x1b <= mask1; x1b ++)
-			if (x1 != x1b &&
-			    l2 == cpu->cd.DYNTRANS_ARCH.l1_64[x1b]) {
-				fatal("L2 reuse: %p\n", l2);
-				exit(1);
-			}
-	}
-}
-
-/*  Count how many pages are actually in use:  */
-{
-	int n=0, i;
-	for (i=0; i<=mask3; i++)
-		if (l3->vaddr_to_tlbindex[i])
-			n++;
-	if (n != l3->refcount) {
-		printf("Z: %i in use, but refcount = %i!\n", n, l3->refcount);
-		exit(1);
-	}
-
-	n = 0;
-	for (i=0; i<=mask3; i++)
-		if (l3->host_load[i] != NULL)
-			n++;
-	if (n != l3->refcount) {
-		printf("ZHL: %i in use, but refcount = %i!\n", n, l3->refcount);
-		exit(1);
-	}
-}
-#endif
-
-/*
-	int found = -1;
-	for (int q = 0; q < 192; ++q)
-	{
-		if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[q].vaddr_page == vaddr_page &&
-			cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[q].valid)
-		{
-			if (found >= 0)
-			{
-				printf("ALREADY FOUND = %i\n", found);
-				int zz = found;
-				printf("%03i: ", zz);
-				printf("vaddr=%016llx\n", (long long)cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[zz].vaddr_page);
-				printf("valid=%i\n", cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[zz].valid);
-
-				zz = q;
-				printf("%03i: ", zz);
-				printf("vaddr=%016llx\n", (long long)cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[zz].vaddr_page);
-				printf("valid=%i\n", cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[zz].valid);
-
-				exit(1);
-			}
-			
-			found = q;
-		}
-	}
-*/
-
-	l3->host_load[x3] = NULL;
-	l3->host_store[x3] = NULL;
-	l3->phys_addr[x3] = 0;
-	l3->phys_page[x3] = NULL;
-	if (l3->vaddr_to_tlbindex[x3] != 0) {
-		cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[
-		    l3->vaddr_to_tlbindex[x3] - 1].valid = 0;
-		l3->refcount --;
-	} else {/*
-		printf("APA: vaddr_page=%016llx l3->refcount = %i\n", (long long)vaddr_page, l3->refcount);
-		for (int zz = 0; zz < 128; ++zz)
-		{
-			printf("%03i: ", zz);
-			printf("vaddr=%016llx\n", (long long)cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[zz].vaddr_page);
-			printf("valid=%i\n", cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[zz].valid);
-		}
-		
-		exit(1);*/
-	}
-	l3->vaddr_to_tlbindex[x3] = 0;
-
-	if (l3->refcount < 0) {
-		fatal("xxx_invalidate_tlb_entry(): huh? Refcount bug.\n");
-		exit(1);
-	}
-
-	if (l3->refcount == 0) {
-		l3->next = cpu->cd.DYNTRANS_ARCH.next_free_l3;
-		cpu->cd.DYNTRANS_ARCH.next_free_l3 = l3;
-		l2->l3[x2] = cpu->cd.DYNTRANS_ARCH.l3_64_dummy;
-
-#ifdef BUGHUNT
-/*  Make sure that we're placing a CLEAN page on the
-    freelist:  */
-{
-	int i;
-	for (i=0; i<=mask3; i++)
-		if (l3->host_load[i] != NULL) {
-			fatal("TRYING TO RETURN A NON-CLEAN L3 PAGE!\n");
-			exit(1);
-		}
-}
-#endif
-		l2->refcount --;
-		if (l2->refcount < 0) {
-			fatal("xxx_invalidate_tlb_entry(): Refcount bug L2.\n");
-			exit(1);
-		}
-		if (l2->refcount == 0) {
-			l2->next = cpu->cd.DYNTRANS_ARCH.next_free_l2;
-			cpu->cd.DYNTRANS_ARCH.next_free_l2 = l2;
-			cpu->cd.DYNTRANS_ARCH.l1_64[x1] =
-			    cpu->cd.DYNTRANS_ARCH.l2_64_dummy;
-		}
-	}
-#endif
-}
-#endif
-
-
-#ifdef DYNTRANS_INVALIDATE_TC
-/*
- *  XXX_invalidate_translation_caches():
- *
- *  Invalidate all entries matching a specific physical address, a specific
- *  virtual address, or ALL entries.
- *
- *  flags should be one of
- *	INVALIDATE_PADDR  INVALIDATE_VADDR  or  INVALIDATE_ALL
- *
- *  In addition, for INVALIDATE_ALL, INVALIDATE_VADDR_UPPER4 may be set and
- *  bit 31..28 of addr are used to select the virtual addresses to invalidate.
- *  (This is useful for PowerPC emulation, when segment registers are updated.)
- *
- *  In the case when all translations are invalidated, paddr doesn't need
- *  to be supplied.
- *
- *  NOTE/TODO: When invalidating a virtual address, it is only cleared from
- *             the quick translation array, not from the linear
- *             vph_tlb_entry[] array.  Hopefully this is enough anyway.
- */
-void DYNTRANS_INVALIDATE_TC(struct cpu *cpu, uint64_t addr, int flags)
-{
-	int r;
-#ifdef MODE32
-	uint32_t
-#else
-	uint64_t
-#endif
-	    addr_page = addr & ~(DYNTRANS_PAGESIZE - 1);
-
-	/*  fatal("invalidate(): ");  */
-
-	/*  Quick case for _one_ virtual addresses: see note above.  */
-	if (flags & INVALIDATE_VADDR) {
-		/*  fatal("vaddr 0x%08x\n", (int)addr_page);  */
-
-#ifdef MODE32
-		DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, addr_page, flags);
-#else
-		// In principle, there can be multiple entries, and they must
-		// be invalidated based on the bits that matter. For example,
-		// using vaddr 0x00A0000012345678 and 0x00B000001234567c
-		// actually point to the same physical page, and if then
-		// the virtual address 0x0000000012345000 is to be invalidated,
-		// then both of those should be invalidated!
-		int n = 0;
-		for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++)
-			if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid &&
-			    (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page
-			    & cpu->vaddr_mask) == (addr_page & cpu->vaddr_mask)) {
-				DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page, flags);
-				n ++;
-			}
-
-		if (n > 1)
-			debug("[ DYNTRANS_INVALIDATE_TC: CACHE COLLISION vaddr 0x%016llx! ]\n",
-				(long long)addr_page);
-#endif
-
-		return;
-	}
-
-	/*  Invalidate everything:  */
-#ifdef DYNTRANS_PPC
-	if (flags & INVALIDATE_ALL && flags & INVALIDATE_VADDR_UPPER4) {
-		/*  fatal("all, upper4 (PowerPC segment)\n");  */
-		for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++) {
-			if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid &&
-			    (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page
-			    & 0xf0000000) == addr_page) {
-				DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, cpu->cd.
-				    DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page,
-				    0);
-				// Not needed: DYNTRANS_INVALIDATE_TLB_ENTRY should
-				// set valid to 0 anyway.
-				// cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid=0;
-			}
-		}
-		return;
-	}
-#endif
-	if (flags & INVALIDATE_ALL) {
-		/*  fatal("all\n");  */
-		for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++) {
-			if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) {
-				DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, cpu->cd.
-				    DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page,
-				    0);
-				// Not needed: DYNTRANS_INVALIDATE_TLB_ENTRY should
-				// set valid to 0 anyway.
-				// cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid=0;
-			}
-		}
-		return;
-	}
-
-	/*  Invalidate a physical page:  */
-
-	if (!(flags & INVALIDATE_PADDR))
-		fatal("HUH? Invalidate: Not vaddr, all, or paddr?\n");
-
-	/*  fatal("addr 0x%08x\n", (int)addr_page);  */
-
-	for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++) {
-		if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid && addr_page
-		    == cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].paddr_page) {
-			DYNTRANS_INVALIDATE_TLB_ENTRY(cpu,
-			    cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page,
-			    flags);
-			if (flags & JUST_MARK_AS_NON_WRITABLE)
-				cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r]
-				    .writeflag = 0;
-			else
-				cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r]
-				    .valid = 0;
-		}
-	}
-}
-#endif	/*  DYNTRANS_INVALIDATE_TC  */
-
-
-
-#ifdef DYNTRANS_INVALIDATE_TC_CODE
-/*
- *  XXX_invalidate_code_translation():
- *
- *  Invalidate code translations for a specific physical address, a specific
- *  virtual address, or for all entries in the cache.
- */
-void DYNTRANS_INVALIDATE_TC_CODE(struct cpu *cpu, uint64_t addr, int flags)
-{
-	int r;
-#ifdef MODE32
-	uint32_t
-#else
-	uint64_t
-#endif
-	    vaddr_page, paddr_page;
-
-	addr &= ~(DYNTRANS_PAGESIZE-1);
-
-	/*  printf("DYNTRANS_INVALIDATE_TC_CODE addr=0x%08x flags=%i\n",
-	    (int)addr, flags);  */
-
-	if (flags & INVALIDATE_PADDR) {
-		int pagenr, table_index;
-		uint32_t physpage_ofs, *physpage_entryp;
-		struct DYNTRANS_TC_PHYSPAGE *ppp, *prev_ppp;
-
-		pagenr = DYNTRANS_ADDR_TO_PAGENR(addr);
-		table_index = PAGENR_TO_TABLE_INDEX(pagenr);
-
-		physpage_entryp = &(((uint32_t *)cpu->
-		    translation_cache)[table_index]);
-		physpage_ofs = *physpage_entryp;
-
-		/*  Return immediately if there is no code translation
-		    for this page.  */
-		if (physpage_ofs == 0)
-			return;
-
-		prev_ppp = ppp = NULL;
-
-		/*  Traverse the physical page chain:  */
-		while (physpage_ofs != 0) {
-			prev_ppp = ppp;
-			ppp = (struct DYNTRANS_TC_PHYSPAGE *)
-			    (cpu->translation_cache + physpage_ofs);
-
-			/*  If we found the page in the cache,
-			    then we're done:  */
-			if (ppp->physaddr == addr)
-				break;
-
-			/*  Try the next page in the chain:  */
-			physpage_ofs = ppp->next_ofs;
-		}
-
-		/*  If there is no translation, there is no need to go
-		    on and try to remove it from the vph_tlb_entry array:  */
-		if (physpage_ofs == 0)
-			return;
-
-#if 0
-		/*
-		 *  "Bypass" the page, removing it from the code cache.
-		 *
-		 *  NOTE/TODO: This gives _TERRIBLE_ performance with self-
-		 *  modifying code, or when a single page is used for both
-		 *  code and (writable) data.
-		 */
-		if (ppp != NULL) {
-			if (prev_ppp != NULL)
-				prev_ppp->next_ofs = ppp->next_ofs;
-			else
-				*physpage_entryp = ppp->next_ofs;
-		}
-#else
-		(void)prev_ppp;	// shut up compiler warning
-
-		/*
-		 *  Instead of removing the page from the code cache, each
-		 *  entry can be set to "to_be_translated". This is slow in
-		 *  the general case, but in the case of self-modifying code,
-		 *  it might be faster since we don't risk wasting cache
-		 *  memory as quickly (which would force unnecessary Restarts).
-		 */
-		if (ppp != NULL && ppp->translations_bitmap != 0) {
-			uint32_t x = ppp->translations_bitmap;	/*  TODO:
-				urk Should be same type as the bitmap */
-			int i, j, n, m;
-
-#ifdef DYNTRANS_ARM
-			/*
-			 *  Note: On ARM, PC-relative load instructions are
-			 *  implemented as immediate mov instructions. When
-			 *  setting parts of the page to "to be translated",
-			 *  we cannot keep track of which of the immediate
-			 *  movs that were affected, so we need to clear
-			 *  the entire page. (ARM only; not for the general
-			 *  case.)
-			 */
-			x = 0xffffffff;
-#endif
-			n = 8 * sizeof(x);
-			m = DYNTRANS_IC_ENTRIES_PER_PAGE / n;
-
-			for (i=0; i<n; i++) {
-				if (x & 1) {
-					for (j=0; j<m; j++)
-						ppp->ics[i*m + j].f =
-						    TO_BE_TRANSLATED;
-				}
-
-				x >>= 1;
-			}
-
-			ppp->translations_bitmap = 0;
-
-			/*  Clear the list of translatable ranges:  */
-			if (ppp->translation_ranges_ofs != 0) {
-				struct physpage_ranges *physpage_ranges =
-				    (struct physpage_ranges *)
-				    (cpu->translation_cache +
-				    ppp->translation_ranges_ofs);
-				physpage_ranges->next_ofs = 0;
-				physpage_ranges->n_entries_used = 0;
-			}
-		}
-#endif
-	}
-
-	/*  Invalidate entries in the VPH table:  */
-	for (r = 0; r < DYNTRANS_MAX_VPH_TLB_ENTRIES; r ++) {
-		if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) {
-			vaddr_page = cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r]
-			    .vaddr_page & ~(DYNTRANS_PAGESIZE-1);
-			paddr_page = cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r]
-			    .paddr_page & ~(DYNTRANS_PAGESIZE-1);
-
-			if (flags & INVALIDATE_ALL ||
-			    (flags & INVALIDATE_PADDR && paddr_page == addr) ||
-			    (flags & INVALIDATE_VADDR && vaddr_page == addr)) {
-#ifdef MODE32
-				uint32_t index =
-				    DYNTRANS_ADDR_TO_PAGENR(vaddr_page);
-				cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL;
-#else
-				const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
-				const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
-				const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
-				uint32_t x1, x2, x3;
-				struct DYNTRANS_L2_64_TABLE *l2;
-				struct DYNTRANS_L3_64_TABLE *l3;
-
-				x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1;
-				x2 = (vaddr_page >> (64-DYNTRANS_L1N -
-				    DYNTRANS_L2N)) & mask2;
-				x3 = (vaddr_page >> (64-DYNTRANS_L1N -
-				    DYNTRANS_L2N - DYNTRANS_L3N)) & mask3;
-				l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
-				l3 = l2->l3[x2];
-				l3->phys_page[x3] = NULL;
-#endif
-			}
-		}
-	}
-}
-#endif	/*  DYNTRANS_INVALIDATE_TC_CODE  */
-
-
-
-#ifdef DYNTRANS_UPDATE_TRANSLATION_TABLE
-/*
- *  XXX_update_translation_table():
- *
- *  Update the virtual memory translation tables.
- */
-void DYNTRANS_UPDATE_TRANSLATION_TABLE(struct cpu *cpu, uint64_t vaddr_page,
-	unsigned char *host_page, int writeflag, uint64_t paddr_page)
-{
-	int found, r, useraccess = 0;
-
-#ifdef MODE32
-	uint32_t index;
-	vaddr_page &= 0xffffffffULL;
-
-	if (paddr_page > 0xffffffffULL) {
-		fatal("update_translation_table(): v=0x%016" PRIx64", h=%p w=%i"
-		    " p=0x%016" PRIx64"\n", vaddr_page, host_page, writeflag,
-		    paddr_page);
-		exit(1);
-	}
-
-	/*  fatal("update_translation_table(): v=0x%x, h=%p w=%i"
-	    " p=0x%x\n", (int)vaddr_page, host_page, writeflag,
-	    (int)paddr_page);  */
-#else	/*  !MODE32  */
-	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
-	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
-	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
-	uint32_t x1, x2, x3;
-	struct DYNTRANS_L2_64_TABLE *l2;
-	struct DYNTRANS_L3_64_TABLE *l3;
-
-	/*  fatal("update_translation_table(): v=0x%016" PRIx64", h=%p w=%i"
-	    " p=0x%016" PRIx64"\n", (uint64_t)vaddr_page, host_page, writeflag,
-	    (uint64_t)paddr_page);  */
-#endif
-
-	assert((vaddr_page & (DYNTRANS_PAGESIZE-1)) == 0);
-	assert((paddr_page & (DYNTRANS_PAGESIZE-1)) == 0);
-
-	if (writeflag & MEMORY_USER_ACCESS) {
-		writeflag &= ~MEMORY_USER_ACCESS;
-		useraccess = 1;
-	}
-
-	(void)useraccess;  // shut up compiler warning about unused var
-
-#ifdef DYNTRANS_M88K
-	/*  TODO  */
-	if (useraccess)
-		return;
-#endif
-
-	/*  Scan the current TLB entries:  */
-
-#ifdef MODE32
-	/*
-	 *  NOTE 1: vaddr_to_tlbindex is one more than the index, so that
-	 *          0 becomes -1, which means a miss.
-	 *
-	 *  NOTE 2: When a miss occurs, instead of scanning the entire tlb
-	 *          for the entry with the lowest time stamp, just choosing
-	 *          one at random will work as well.
-	 */
-	found = (int)cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[
-	    DYNTRANS_ADDR_TO_PAGENR(vaddr_page)] - 1;
-#else
-	x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1;
-	x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
-	x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N))
-	    & mask3;
-
-	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
-	if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy)
-		found = -1;
-	else {
-		l3 = l2->l3[x2];
-		if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy)
-			found = -1;
-		else
-			found = (int)l3->vaddr_to_tlbindex[x3] - 1;
-	}
-#endif
-
-	if (found < 0) {
-		/*  Create the new TLB entry, overwriting a "random" entry:  */
-		static unsigned int x = 0;
-		r = (x++) % DYNTRANS_MAX_VPH_TLB_ENTRIES;
-
-		if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) {
-			/*  This one has to be invalidated first:  */
-			DYNTRANS_INVALIDATE_TLB_ENTRY(cpu,
-			    cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page,
-			    0);
-		}
-
-		cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid = 1;
-		cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].host_page = host_page;
-		cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].paddr_page = paddr_page;
-		cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page = vaddr_page;
-		cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag =
-		    writeflag & MEM_WRITE;
-
-		/*  Add the new translation to the table:  */
-#ifdef MODE32
-		index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page);
-		cpu->cd.DYNTRANS_ARCH.host_load[index] = host_page;
-		cpu->cd.DYNTRANS_ARCH.host_store[index] =
-		    writeflag? host_page : NULL;
-		cpu->cd.DYNTRANS_ARCH.phys_addr[index] = paddr_page;
-		cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL;
-		cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index] = r + 1;
-#ifdef DYNTRANS_ARM
-		if (useraccess)
-			cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 5]
-			    |= 1 << (index & 31);
-#endif
-#else	/* !MODE32  */
-		l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
-		if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) {
-			if (cpu->cd.DYNTRANS_ARCH.next_free_l2 != NULL) {
-				l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1] =
-				    cpu->cd.DYNTRANS_ARCH.next_free_l2;
-				cpu->cd.DYNTRANS_ARCH.next_free_l2 = l2->next;
-			} else {
-				int i;
-				CHECK_ALLOCATION(l2 =
-				    cpu->cd.DYNTRANS_ARCH.l1_64[x1] =
-				    (struct DYNTRANS_L2_64_TABLE *) malloc(
-				    sizeof(struct DYNTRANS_L2_64_TABLE)));
-				l2->refcount = 0;
-				for (i=0; i<(1 << DYNTRANS_L2N); i++)
-					l2->l3[i] = cpu->cd.DYNTRANS_ARCH.
-					    l3_64_dummy;
-			}
-			if (l2->refcount != 0) {
-				fatal("Huh? l2 Refcount problem.\n");
-				exit(1);
-			}
-		}
-		if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) {
-			fatal("INTERNAL ERROR L2 reuse\n");
-			exit(1);
-		}
-		l3 = l2->l3[x2];
-		if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy) {
-			if (cpu->cd.DYNTRANS_ARCH.next_free_l3 != NULL) {
-				l3 = l2->l3[x2] =
-				    cpu->cd.DYNTRANS_ARCH.next_free_l3;
-				cpu->cd.DYNTRANS_ARCH.next_free_l3 = l3->next;
-			} else {
-				l3 = l2->l3[x2] = (struct DYNTRANS_L3_64_TABLE *)
-				    zeroed_alloc(sizeof(
-				    struct DYNTRANS_L3_64_TABLE));
-			}
-			if (l3->refcount != 0) {
-				fatal("Huh? l3 Refcount problem.\n");
-				exit(1);
-			}
-			l2->refcount ++;
-		}
-		if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy) {
-			fatal("INTERNAL ERROR L3 reuse\n");
-			exit(1);
-		}
-
-		l3->host_load[x3] = host_page;
-		l3->host_store[x3] = writeflag? host_page : NULL;
-		l3->phys_addr[x3] = paddr_page;
-		l3->phys_page[x3] = NULL;
-		l3->vaddr_to_tlbindex[x3] = r + 1;
-		l3->refcount ++;
-
-#ifdef BUGHUNT
-/*  Count how many pages are actually in use:  */
-{
-	int n=0, i;
-	for (i=0; i<=mask3; i++)
-		if (l3->vaddr_to_tlbindex[i])
-			n++;
-	if (n != l3->refcount) {
-		printf("X: %i in use, but refcount = %i!\n", n, l3->refcount);
-		exit(1);
-	}
-
-	n = 0;
-	for (i=0; i<=mask3; i++)
-		if (l3->host_load[i] != NULL)
-			n++;
-	if (n != l3->refcount) {
-		printf("XHL: %i in use, but refcount = %i!\n", n, l3->refcount);
-		exit(1);
-	}
-}
-#endif
-
-#endif	/* !MODE32  */
-	} else {
-		/*
-		 *  The translation was already in the TLB.
-		 *	Writeflag = 0:  Do nothing.
-		 *	Writeflag = 1:  Make sure the page is writable.
-		 *	Writeflag = MEM_DOWNGRADE: Downgrade to readonly.
-		 */
-		r = found;
-		if (writeflag & MEM_WRITE)
-			cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 1;
-		if (writeflag & MEM_DOWNGRADE)
-			cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 0;
-#ifdef MODE32
-		index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page);
-		cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL;
-#ifdef DYNTRANS_ARM
-		cpu->cd.DYNTRANS_ARCH.is_userpage[index>>5] &= ~(1<<(index&31));
-		if (useraccess)
-			cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 5]
-			    |= 1 << (index & 31);
-#endif
-		if (cpu->cd.DYNTRANS_ARCH.phys_addr[index] == paddr_page) {
-			if (writeflag & MEM_WRITE)
-				cpu->cd.DYNTRANS_ARCH.host_store[index] =
-				    host_page;
-			if (writeflag & MEM_DOWNGRADE)
-				cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL;
-		} else {
-			/*  Change the entire physical/host mapping:  */
-			cpu->cd.DYNTRANS_ARCH.host_load[index] = host_page;
-			cpu->cd.DYNTRANS_ARCH.host_store[index] =
-			    writeflag? host_page : NULL;
-			cpu->cd.DYNTRANS_ARCH.phys_addr[index] = paddr_page;
-		}
-#else	/*  !MODE32  */
-		x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1;
-		x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
-		x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N))
-		    & mask3;
-		l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
-		l3 = l2->l3[x2];
-		if (l3->phys_addr[x3] == paddr_page) {
-			if (writeflag & MEM_WRITE)
-				l3->host_store[x3] = host_page;
-			if (writeflag & MEM_DOWNGRADE)
-				l3->host_store[x3] = NULL;
-		} else {
-			/*  Change the entire physical/host mapping:  */
-			l3->host_load[x3] = host_page;
-			l3->host_store[x3] = writeflag? host_page : NULL;
-			l3->phys_addr[x3] = paddr_page;
-		}
-		
-		/*  HM!  /2013-11-17  */
-		/*  Should this be here?  2014-08-02  */
-		//l3->phys_page[x3] = NULL;
-
-#ifdef BUGHUNT
-/*  Count how many pages are actually in use:  */
-{
-	int n=0, i;
-	for (i=0; i<=mask3; i++)
-		if (l3->vaddr_to_tlbindex[i])
-			n++;
-	if (n != l3->refcount) {
-		printf("Y: %i in use, but refcount = %i!\n", n, l3->refcount);
-		exit(1);
-	}
-
-	n = 0;
-	for (i=0; i<=mask3; i++)
-		if (l3->host_load[i] != NULL)
-			n++;
-	if (n != l3->refcount) {
-		printf("YHL: %i in use, but refcount = %i!\n", n, l3->refcount);
-		printf("Entry r = %i\n", r);
-		printf("Valid = %i\n",
-cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid);
-		exit(1);
-	}
-}
-#endif
-
-#endif	/*  !MODE32  */
-	}
-}
-#endif	/*  DYNTRANS_UPDATE_TRANSLATION_TABLE  */
-
-
-/*****************************************************************************/
-
-
-#ifdef DYNTRANS_TO_BE_TRANSLATED_HEAD
-	/*
-	 *  Check for breakpoints.
-	 */
-	if (!single_step_breakpoint && !cpu->translation_readahead) {
-		MODE_uint_t curpc = cpu->pc;
-		int i;
-		for (i=0; i<cpu->machine->breakpoints.n; i++)
-			if (curpc == (MODE_uint_t)
-			    cpu->machine->breakpoints.addr[i]) {
-				if (!cpu->machine->instruction_trace) {
-					int tmp_old_quiet_mode = quiet_mode;
-					quiet_mode = 0;
-					DISASSEMBLE(cpu, ib, 1, 0);
-					quiet_mode = tmp_old_quiet_mode;
-				}
-#ifdef MODE32
-				fatal("BREAKPOINT: pc = 0x%" PRIx32"\n(The "
-				    "instruction has not yet executed.)\n",
-				    (uint32_t)cpu->pc);
-#else
-				fatal("BREAKPOINT: pc = 0x%" PRIx64"\n(The "
-				    "instruction has not yet executed.)\n",
-				    (uint64_t)cpu->pc);
-#endif
-#ifdef DYNTRANS_DELAYSLOT
-				if (cpu->delay_slot != NOT_DELAYED)
-					fatal("ERROR! Breakpoint in a delay"
-					    " slot! Not yet supported.\n");
-#endif
-				single_step_breakpoint = 1;
-				single_step = ENTER_SINGLE_STEPPING;
-				goto stop_running_translated;
-			}
-	}
-#endif	/*  DYNTRANS_TO_BE_TRANSLATED_HEAD  */
-
-
-/*****************************************************************************/
-
-
-#ifdef DYNTRANS_TO_BE_TRANSLATED_TAIL
-	/*
-	 *  If we end up here, then an instruction was translated. Let's mark
-	 *  the page as containing a translation at this part of the page.
-	 */
-
-	/*  Make sure cur_physpage is in synch:  */
-	cpu->cd.DYNTRANS_ARCH.cur_physpage = (struct DYNTRANS_TC_PHYSPAGE *)
-	    cpu->cd.DYNTRANS_ARCH.cur_ic_page;
-
-	{
-		int x = addr & (DYNTRANS_PAGESIZE - 1);
-		int addr_per_translation_range = DYNTRANS_PAGESIZE / (8 *
-		    sizeof(cpu->cd.DYNTRANS_ARCH.cur_physpage->
-		    translations_bitmap));
-		x /= addr_per_translation_range;
-
-		cpu->cd.DYNTRANS_ARCH.cur_physpage->
-		    translations_bitmap |= (1 << x);
-	}
-
-
-	/*
-	 *  Now it is time to check for combinations of instructions that can
-	 *  be converted into a single function call.
-	 *
-	 *  Note: Single-stepping or instruction tracing doesn't work with
-	 *  instruction combinations. For architectures with delay slots,
-	 *  we also ignore combinations if the delay slot is across a page
-	 *  boundary.
-	 */
-	if (!single_step && !cpu->machine->instruction_trace
-#ifdef DYNTRANS_DELAYSLOT
-	    && !in_crosspage_delayslot
-#endif
-	    && cpu->cd.DYNTRANS_ARCH.combination_check != NULL
-	    && cpu->machine->allow_instruction_combinations) {
-		cpu->cd.DYNTRANS_ARCH.combination_check(cpu, ic,
-		    addr & (DYNTRANS_PAGESIZE - 1));
-	}
-
-	cpu->cd.DYNTRANS_ARCH.combination_check = NULL;
-
-	/*  An additional check, to catch some bugs:  */
-	if (ic->f == TO_BE_TRANSLATED) {
-		fatal("INTERNAL ERROR: ic->f not set!\n");
-		goto bad;
-	}
-	if (ic->f == NULL) {
-		fatal("INTERNAL ERROR: ic->f == NULL!\n");
-		goto bad;
-	}
-
-
-	/*
-	 *  ... and finally execute the translated instruction:
-	 */
-
-	/*  (Except when doing read-ahead!)  */
-	if (cpu->translation_readahead)
-		return;
-
-	/*
-	 *  Special case when single-stepping: Execute the translated
-	 *  instruction, but then replace it with a "to be translated"
-	 *  directly afterwards.
-	 */
-	if ((single_step_breakpoint && cpu->delay_slot == NOT_DELAYED)
-#ifdef DYNTRANS_DELAYSLOT
-	    || in_crosspage_delayslot
-#endif
-	    ) {
-		single_step_breakpoint = 0;
-		ic->f(cpu, ic);
-		ic->f = TO_BE_TRANSLATED;
-		return;
-	}
-
-
-	/*  Translation read-ahead:  */
-	if (!single_step && !cpu->machine->instruction_trace &&
-	    cpu->machine->breakpoints.n == 0) {
-		uint64_t baseaddr = cpu->pc;
-		uint64_t pagenr = DYNTRANS_ADDR_TO_PAGENR(baseaddr);
-		int i = 1;
-
-		cpu->translation_readahead = MAX_DYNTRANS_READAHEAD;
-
-		while (DYNTRANS_ADDR_TO_PAGENR(baseaddr +
-		    (i << DYNTRANS_INSTR_ALIGNMENT_SHIFT)) == pagenr &&
-		    cpu->translation_readahead > 0) {
-			void (*old_f)(struct cpu *,
-			    struct DYNTRANS_IC *) = ic[i].f;
-
-			/*  Already translated? Then abort:  */
-			if (old_f != TO_BE_TRANSLATED)
-				break;
-
-			/*  Translate the instruction:  */
-			ic[i].f(cpu, ic+i);
-
-			/*  Translation failed? Then abort.  */
-			if (ic[i].f == old_f)
-				break;
-
-			cpu->translation_readahead --;
-			++i;
-		}
-
-		cpu->translation_readahead = 0;
-	}
-
-
-	/*
-	 *  Finally finally :-), execute the instruction.
-	 *
-	 *  Note: The instruction might have changed during read-ahead, if
-	 *  instruction combinations are used.
-	 */
-
-	ic->f(cpu, ic);
-
-	return;
-
-
-bad:	/*
-	 *  Nothing was translated. (Unimplemented or illegal instruction.)
-	 */
-
-	/*  Clear the translation, in case it was "half-way" done:  */
-	ic->f = TO_BE_TRANSLATED;
-
-	if (cpu->translation_readahead)
-		return;
-
-	quiet_mode = 0;
-	fatal("to_be_translated(): TODO: unimplemented instruction");
-
-	if (cpu->machine->instruction_trace) {
-		if (cpu->is_32bit)
-			fatal(" at 0x%" PRIx32"\n", (uint32_t)cpu->pc);
-		else
-			fatal(" at 0x%" PRIx64"\n", (uint64_t)cpu->pc);
-	} else {
-		fatal(":\n");
-		DISASSEMBLE(cpu, ib, 1, 0);
-	}
-
-	cpu->running = 0;
-
-	/*  Note: Single-stepping can jump here.  */
-stop_running_translated:
-
-	debugger_n_steps_left_before_interaction = 0;
-
-	ic = cpu->cd.DYNTRANS_ARCH.next_ic = &nothing_call;
-	cpu->cd.DYNTRANS_ARCH.next_ic ++;
-
-#ifdef DYNTRANS_DELAYSLOT
-	/*  Special hack: If the bad instruction was in a delay slot,
-	    make sure that execution does not continue anyway:  */
-	if (cpu->delay_slot)
-		cpu->delay_slot |= EXCEPTION_IN_DELAY_SLOT;
-#endif
-
-	/*  Execute the "nothing" instruction:  */
-	ic->f(cpu, ic);
-
-#endif	/*  DYNTRANS_TO_BE_TRANSLATED_TAIL  */
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_i960.c gxemul-0.7.0+dfsg/src/cpus/cpu_i960.c
--- gxemul-0.6.2/src/cpus/cpu_i960.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_i960.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,823 @@
+/*
+ *  Copyright (C) 2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Intel 80960 (i960) CPU emulation.
+ *
+ *  Disassembly of i960CA should work.
+ *
+ *  TODO: Almost everything else.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <unistd.h>
+
+#include "cpu.h"
+#include "float_emul.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "settings.h"
+#include "symbol.h"
+
+
+// TODO: #define DYNTRANS_DELAYSLOT ?
+
+#define DYNTRANS_32
+#include "tmp_i960_head.c"
+
+
+// Register conventions according to
+// https://people.cs.clemson.edu/~mark/subroutines/i960.html
+
+static const char* i960_regnames[N_I960_REGS] = {
+	"pfp",		// r0 = previous frame pointer
+	"sp",		// r1 = stack pointer
+	"rip",		// r2 = return instruction pointer
+	"r3", "r4", "r5", "r6", "r7",
+	"r8", "r9", "r10", "r11", "r12",
+	"r13", "r14", "r15",
+
+	"g0", "g1", "g2", "g3",	// parameters 0-3; return words 0-3
+	"g4", "g5", "g6", "g7", // parameters 4-7; temporaries
+	"g8", "g9", "g10", "g11", "g12",	// preserved accross call
+	"g13",		// structure return pointer
+	"g14",		// argument block pointer; leaf return address (HW)
+	"fp" 		// g15 = frame pointer (16-byte aligned HW)
+};
+
+struct reg_instruction {
+	int opcode;
+	const char* mnemonic;
+	bool has_src1;
+	bool has_src2;
+	bool has_dst;
+	bool has_src3;	// true if the dst/src field is used as a source
+};
+
+struct reg_instruction reg_instructions[] = {
+	{ 0x580, "notbit",      true,  true,  true,  false },
+	{ 0x581, "and",         true,  true,  true,  false },
+	{ 0x582, "andnot",      true,  true,  true,  false },
+	{ 0x583, "setbit",      true,  true,  true,  false },
+	{ 0x584, "notand",      true,  true,  true,  false },
+	{ 0x586, "xor",         true,  true,  true,  false },
+	{ 0x587, "or",          true,  true,  true,  false },
+	{ 0x588, "nor",         true,  true,  true,  false },
+	{ 0x589, "xnor",        true,  true,  true,  false },
+	{ 0x58a, "not",         true,  false, true,  false },
+	{ 0x58b, "ornot",       true,  true,  true,  false },
+	{ 0x58c, "clrbit",      true,  true,  true,  false },
+	{ 0x58d, "notor",       true,  true,  true,  false },
+	{ 0x58e, "nand",        true,  true,  true,  false },
+	{ 0x58f, "alterbit",    true,  true,  true,  false },
+
+	{ 0x590, "addo",        true,  true,  true,  false },
+	{ 0x591, "addi",        true,  true,  true,  false },
+	{ 0x592, "subo",        true,  true,  true,  false },
+	{ 0x593, "subi",        true,  true,  true,  false },
+	{ 0x598, "shro",        true,  true,  true,  false },
+	{ 0x59a, "shrdi",       true,  true,  true,  false },
+	{ 0x59b, "shri" ,       true,  true,  true,  false },
+	{ 0x59c, "shlo",        true,  true,  true,  false },
+	{ 0x59d, "rotate",      true,  true,  true,  false },
+	{ 0x59e, "shli",        true,  true,  true,  false },
+
+	{ 0x5a0, "cmpo",        true,  true,  false, false },
+	{ 0x5a1, "cmpi",        true,  true,  false, false },
+	{ 0x5a2, "concmpo",     true,  true,  false, false },
+	{ 0x5a3, "concmpi",     true,  true,  false, false },
+	{ 0x5a4, "cmpinco",     true,  true,  true,  false },
+	{ 0x5a5, "cmpinci",     true,  true,  true,  false },
+	{ 0x5a6, "cmpdeco",     true,  true,  true,  false },
+	{ 0x5a7, "cmpdeci",     true,  true,  true,  false },
+
+	{ 0x5ac, "scanbyte",    true,  true,  false, false },
+	{ 0x5ae, "chkbit",      true,  true,  false, false },
+
+	{ 0x5b0, "addc",        true,  true,  true,  false },
+	{ 0x5b2, "subc",        true,  true,  true,  false },
+
+	{ 0x5cc, "mov",         true,  false, true,  false },
+	{ 0x5d8, "eshro",       true,  true,  true,  false },
+	{ 0x5dc, "movl",        true,  false, true,  false },
+	{ 0x5ec, "movt",        true,  false, true,  false },
+	{ 0x5fc, "movq",        true,  false, true,  false },
+
+	{ 0x630, "sdma",        true,  true,  true,  true  },
+	{ 0x631, "udma",        false, false, false, false },
+
+	{ 0x640, "spanbit",     true,  false, true,  false },
+	{ 0x641, "scanbit",     true,  false, true,  false },
+	{ 0x645, "modac",       true,  true,  true,  true  },
+
+	{ 0x650, "modify",      true,  true,  true,  true  },
+	{ 0x651, "extract",     true,  true,  true,  true  },
+	{ 0x654, "modtc",       true,  true,  true,  true  },
+	{ 0x655, "modpc",       true,  true,  true,  true  },
+	{ 0x659, "sysctl",      true,  true,  true,  true  },
+
+	{ 0x660, "calls",       true,  false, false, false },
+	{ 0x66b, "mark",        false, false, false, false },
+	{ 0x66c, "fmark",       false, false, false, false },
+	{ 0x66d, "flushreg",    false, false, false, false },
+	{ 0x66f, "syncf",       false, false, false, false },
+
+	{ 0x670, "emul",        true,  true,  true,  false },
+	{ 0x671, "ediv",        true,  true,  true,  false },
+
+	{ 0x701, "mulo",        true,  true,  true,  false },
+	{ 0x708, "remo",        true,  true,  true,  false },
+	{ 0x70b, "divo",        true,  true,  true,  false },
+
+	{ 0x741, "muli",        true,  true,  true,  false },
+	{ 0x748, "remi",        true,  true,  true,  false },
+	{ 0x749, "modi",        true,  true,  true,  false },
+	{ 0x74b, "divi",        true,  true,  true,  false },
+
+	{ 0,     NULL,          false, false, false, false }
+};
+
+
+static const char *regname_or_literal(int reg, int m, int s)
+{
+	// Regular g or r registers
+	if (m == 0 && s == 0)
+		return i960_regnames[reg];
+
+	static char buf[32];
+
+	if (m != 0 && s == 0) {
+		// Literal
+		snprintf(buf, sizeof(buf), "%i", reg);
+	} else if (m == 0 && s != 0) {
+		// Special Function Register
+		snprintf(buf, sizeof(buf), "sfr%i", reg);
+	} else {
+		snprintf(buf, sizeof(buf), "reserved%i", reg);
+	}
+	
+	return buf;
+}
+
+
+void i960_pc_to_pointers(struct cpu *);
+void i960_cpu_functioncall_trace(struct cpu *cpu, int n_args);
+
+void i960_irq_interrupt_assert(struct interrupt *interrupt);
+void i960_irq_interrupt_deassert(struct interrupt *interrupt);
+
+
+/*
+ *  i960_cpu_new():
+ *
+ *  Create a new 80960 cpu object by filling the CPU struct.
+ *  Return 1 on success, 0 if cpu_type_name isn't a valid i960 processor model.
+ */
+int i960_cpu_new(struct cpu *cpu, struct memory *mem,
+	struct machine *machine, int cpu_id, char *cpu_type_name)
+{
+	/*  TODO: Check cpu_type_name in a better way.  */
+	if (strcmp(cpu_type_name, "i960Jx") != 0 && strcmp(cpu_type_name, "i960CA") != 0)
+		return 0;
+
+	cpu->run_instr = i960_run_instr;
+	cpu->memory_rw = i960_memory_rw;
+	cpu->update_translation_table = i960_update_translation_table;
+	cpu->invalidate_translation_caches = i960_invalidate_translation_caches;
+	cpu->invalidate_code_translation = i960_invalidate_code_translation;
+
+	cpu->name            = strdup(cpu_type_name);
+	cpu->is_32bit        = 1;
+	cpu->byte_order      = EMUL_BIG_ENDIAN;
+
+	cpu->vaddr_mask = 0x00000000ffffffffULL;
+
+	if (strcmp(cpu_type_name, "i960CA") == 0)
+		cpu->cd.i960.nr_of_valid_sfrs = 3;
+
+
+	/*
+	 *  Add register names as settings:
+	 */
+
+	settings_add(cpu->settings, "ip", 1, SETTINGS_TYPE_UINT64,
+            SETTINGS_FORMAT_HEX32, (void *) &cpu->pc);
+
+	CPU_SETTINGS_ADD_REGISTER32("ac", cpu->cd.i960.ac);
+	CPU_SETTINGS_ADD_REGISTER32("pc", cpu->cd.i960.i960_pc);
+	CPU_SETTINGS_ADD_REGISTER32("tc", cpu->cd.i960.tc);
+
+	for (int i = 0; i < N_I960_REGS; i++) {
+		CPU_SETTINGS_ADD_REGISTER32(i960_regnames[i], cpu->cd.i960.r[i]);
+	}
+
+	for (int i = 0; i < cpu->cd.i960.nr_of_valid_sfrs; i++) {
+		char name[20];
+		snprintf(name, sizeof(name), "sfr%i", i);
+		CPU_SETTINGS_ADD_REGISTER32(name, cpu->cd.i960.sfr[i]);
+	}
+
+
+	/*  Register the CPU interrupt pin:  */
+	struct interrupt templ;
+	char name[50];
+	snprintf(name, sizeof(name), "%s", cpu->path);
+
+	memset(&templ, 0, sizeof(templ));
+	templ.line = 0;
+	templ.name = name;
+	templ.extra = cpu;
+	templ.interrupt_assert = i960_irq_interrupt_assert;
+	templ.interrupt_deassert = i960_irq_interrupt_deassert;
+	interrupt_handler_register(&templ);
+
+	return 1;
+}
+
+
+/*
+ *  i960_cpu_dumpinfo():
+ */
+void i960_cpu_dumpinfo(struct cpu *cpu, bool verbose)
+{
+	debugmsg(SUBSYS_MACHINE, "cpu", VERBOSITY_INFO,
+	    "%s",
+	    cpu->name);
+}
+
+
+/*
+ *  i960_cpu_list_available_types():
+ *
+ *  Print a list of available i960 CPU types.
+ */
+void i960_cpu_list_available_types(void)
+{
+	debug("i960CA\ti960Jx\n");
+}
+
+
+/*
+ *  i960_cpu_register_dump():
+ *
+ *  Dump cpu registers in a relatively readable format.
+ *  
+ *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
+ *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
+ */
+void i960_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
+{
+	char *symbol;
+	uint64_t offset;
+	int i, x = cpu->cpu_id;
+
+	if (gprs) {
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    cpu->pc, &offset);
+		debug("cpu%i:  ip  = 0x%08" PRIx32, x, (uint32_t)cpu->pc);
+		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
+
+		debug("cpu%i:  ac  = 0x%08" PRIx32 "\n", x, cpu->cd.i960.ac);
+		debug("cpu%i:  pc  = 0x%08" PRIx32 "\n", x, cpu->cd.i960.i960_pc);
+		debug("cpu%i:  tc  = 0x%08" PRIx32 "\n", x, cpu->cd.i960.tc);
+
+		for (i=0; i<N_I960_REGS; i++) {
+			if ((i % 4) == 0)
+				debug("cpu%i:", x);
+
+			debug("  %-3s = 0x%08" PRIx32,
+			    i960_regnames[i], cpu->cd.i960.r[i]);
+
+			if ((i % 4) == 3)
+				debug("\n");
+		}
+	}
+
+	if (coprocs) {
+		for (i = 0; i < cpu->cd.i960.nr_of_valid_sfrs; i++) {
+			debug("cpu%i:  sfr%i = 0x%08" PRIx32 "\n", x, i, cpu->cd.i960.sfr[i]);
+		}
+	}
+}
+
+
+/*
+ *  i960_cpu_tlbdump():
+ *
+ *  Called from the debugger to dump the TLB in a readable format.
+ *
+ *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
+ *  just dumped.
+ */
+void i960_cpu_tlbdump(struct cpu* cpu, int rawflag)
+{
+}
+
+
+/*
+ *  i960_irq_interrupt_assert():
+ *  i960_irq_interrupt_deassert():
+ */
+void i960_irq_interrupt_assert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.i960.irq_asserted = 1;
+}
+void i960_irq_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.i960.irq_asserted = 0;
+}
+
+
+/*
+ *  i960_exception():
+ *
+ *  Cause an exception.
+ */
+void i960_exception(struct cpu *cpu, int vector, int is_trap)
+{
+	debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "", VERBOSITY_ERROR,
+	    "i960_exception(): TODO");
+
+	cpu->running = false;
+
+	i960_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  i960_cpu_disassemble_instr():
+ *
+ *  Convert an instruction word into human readable format, for instruction
+ *  tracing.
+ *              
+ *  If running is 1, cpu->pc should be the address of the instruction.
+ *
+ *  If running is 0, things that depend on the runtime environment (eg.
+ *  register contents) will not be shown, and dumpaddr will be used instead of
+ *  cpu->pc for relative addresses.
+ */                     
+int i960_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
+        int running, uint64_t dumpaddr)
+{
+	if (running)
+		dumpaddr = cpu->pc;
+
+	uint64_t offset;
+	const char *symbol = get_symbol_name(&cpu->machine->symbol_context,
+	    dumpaddr, &offset);
+	if (symbol != NULL && offset == 0)
+		debug("<%s>\n", symbol);
+
+	if (cpu->machine->ncpus > 1 && running)
+		debug("cpu%i:\t", cpu->cpu_id);
+
+	debug("%08" PRIx32": ", (uint32_t) dumpaddr);
+
+	uint32_t iw;
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
+	else
+		iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);
+
+	const int opcode = iw >> 24;
+
+	const int REG_src_dst  = (iw >> 19) & 0x1f;
+	const int REG_src2     = (iw >> 14) & 0x1f;
+	const int REG_m3       = (iw >> 13) & 0x1;
+	const int REG_m2       = (iw >> 12) & 0x1;
+	const int REG_m1       = (iw >> 11) & 0x1;
+	const int REG_opcode2  = (iw >> 7) & 0xf;
+	const int REG_sfr2     = (iw >> 6) & 0x1;
+	const int REG_sfr1     = (iw >> 5) & 0x1;
+	const int REG_src1     = (iw >> 0) & 0x1f;
+	
+	const int COBR_src_dst = (iw >> 19) & 0x1f;
+	const int COBR_src_2   = (iw >> 14) & 0x1f;
+	const int COBR_m1      = (iw >> 13) & 0x1;
+	const int COBR_disp    = (iw >> 2) & 0x7ff;
+	const int COBR_t       = (iw >> 1) & 0x1;
+	const int COBR_s2      = (iw >> 0) & 0x1;
+	
+	const int CTRL_disp    = (iw >> 2) & 0x3fffff;
+	const int CTRL_t       = (iw >> 1) & 0x1;
+
+	// const int MEMA_src_dst = (iw >> 19) & 0x1f; Same as MEMB_src_dst
+	const int MEMA_abase   = (iw >> 14) & 0x1f;
+	const int MEMA_md      = (iw >> 13) & 0x1;
+	// const int MEMA_zero    = (iw >> 12) & 0x1;  0 for MEMA, 1 for MEMB
+	const int MEMA_offset  = (iw >> 0) & 0xfff;
+
+	const int MEMB_src_dst = (iw >> 19) & 0x1f;
+	const int MEMB_abase   = (iw >> 14) & 0x1f;
+	const int MEMB_mode    = (iw >> 10) & 0xf;
+	const int MEMB_scale   = (iw >> 7) & 0x7;
+	// const int MEMB_sfr     = (iw >> 5) & 0x3;  Should be 00?
+	const int MEMB_index   = (iw >> 0) & 0x1f;
+
+	bool is_64bit_long_instruction = false;
+	uint32_t iw2 = 0;
+
+	if (opcode >= 0x80 && iw & 0x1000) {
+		/*  Only some MEMB instructions have displacement words:  */
+		int mode = (iw >> 10) & 0xf;
+		if (mode == 0x5 || mode >= 0xc)
+			is_64bit_long_instruction = true;		
+	}
+
+	debug("%08 " PRIx32, (uint32_t) iw);
+
+	if (is_64bit_long_instruction) {
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			iw2 = ib[4] + (ib[5]<<8) + (ib[6]<<16) + (ib[7]<<24);
+		else
+			iw2 = ib[7] + (ib[6]<<8) + (ib[5]<<16) + (ib[4]<<24);
+
+		debug(" %08" PRIx32, (uint32_t) iw2);
+	} else {
+		debug("         ");
+	}
+
+	cpu_print_pc_indicator_in_disassembly(cpu, running, dumpaddr);
+
+	if (opcode >= 0x08 && opcode <= 0x1f) {
+		/*  CTRL:  */
+		const char* mnemonics[] = {
+				"b",			/*  0x08  */
+				"call",			/*  0x09  */
+				"ret",			/*  0x0a  */
+				"bal",			/*  0x0b  */
+				"unknown_ctrl_0x0c",	/*  0x0c  */
+				"unknown_ctrl_0x0d",	/*  0x0d  */
+				"unknown_ctrl_0x0e",	/*  0x0e  */
+				"unknown_ctrl_0x0f",	/*  0x0f  */
+				"bno",			/*  0x10  */
+				"bg",			/*  0x11  */
+				"be",			/*  0x12  */
+				"bge",			/*  0x13  */
+				"bl",			/*  0x14  */
+				"bne",			/*  0x15  */
+				"ble",			/*  0x16  */
+				"bo",			/*  0x17  */
+				"faultno",		/*  0x18  */
+				"faultg",		/*  0x19  */
+				"faulte",		/*  0x1a  */
+				"faultge",		/*  0x1b  */
+				"faultl",		/*  0x1c  */
+				"faultne",		/*  0x1d  */
+				"faultle",		/*  0x1e  */
+				"faulto"		/*  0x1f  */
+			};
+
+		debug("%s", mnemonics[opcode - 0x08]);
+		if (CTRL_t)
+			debug(".f");
+
+		bool hasDisplacement = opcode < 0x18 && opcode != 0x0a;
+		if (hasDisplacement) {
+			uint32_t disp = CTRL_disp << 2;
+			if (disp & 0x00800000)
+				disp |= 0xff000000;
+
+			uint32_t addr = dumpaddr + disp;
+
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    addr, &offset);
+			if (symbol != NULL)
+				debug("\t0x%08x\t; <%s>", addr, symbol);
+			else
+				debug("\t0x%08x", addr);
+		}
+	} else if (opcode >= 0x20 && opcode <= 0x3f) {
+		/*  COBR:  */
+		const char* mnemonics[] = {
+				"testno",		/*  0x20  */
+				"testg",		/*  0x21  */
+				"teste",		/*  0x22  */
+				"testge",		/*  0x23  */
+				"testl",		/*  0x24  */
+				"testne",		/*  0x25  */
+				"testle",		/*  0x26  */
+				"testo",		/*  0x27  */
+
+				"unknown_cobr_0x28",	/*  0x28  */
+				"unknown_cobr_0x29",	/*  0x29  */
+				"unknown_cobr_0x2a",	/*  0x2a  */
+				"unknown_cobr_0x2b",	/*  0x2b  */
+				"unknown_cobr_0x2c",	/*  0x2c  */
+				"unknown_cobr_0x2d",	/*  0x2d  */
+				"unknown_cobr_0x2e",	/*  0x2e  */
+				"unknown_cobr_0x2f",	/*  0x2f  */
+
+				"bbc",			/*  0x30  */
+				"cmpobg",		/*  0x31  */
+				"cmpobe",		/*  0x32  */
+				"cmpobge",		/*  0x33  */
+				"cmpobl",		/*  0x34  */
+				"cmpobne",		/*  0x35  */
+				"cmpobne",		/*  0x36  */
+				"bbs",			/*  0x37  */
+
+				"cmpibno",		/*  0x38  */
+				"cmpibg",		/*  0x39  */
+				"cmpibe",		/*  0x3a  */
+				"cmpibge",		/*  0x3b  */
+				"cmpibl",		/*  0x3c  */
+				"cmpibne",		/*  0x3d  */
+				"cmpible",		/*  0x3e  */
+				"cmpibo",		/*  0x3f  */
+			};
+
+		debug("%s", mnemonics[opcode - 0x20]);
+		if (COBR_t)
+			debug(".f");
+
+		bool src1isBitpos = opcode == 0x30 || opcode == 0x37;
+
+		if (opcode <= 0x27) {
+			debug("\t%s", regname_or_literal(COBR_src_dst, 0, COBR_s2));
+		} else {
+			uint32_t targ = COBR_disp << 2;
+			if (targ & 0x00001000)
+				targ |= 0xffffe000;
+			targ += dumpaddr;
+
+			debug("\t%s", regname_or_literal(COBR_src_dst, src1isBitpos ? 1 : COBR_m1, 0));
+			debug(",%s", regname_or_literal(COBR_src_2, 0, COBR_s2));
+
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    targ, &offset);
+			if (symbol != NULL)
+				debug(",0x%08x\t; <%s>", targ, symbol);
+			else
+				debug(",0x%08x", targ);
+		}
+	} else if (opcode >= 0x58 && opcode <= 0x7f) {
+		/*  REG:  */
+		struct reg_instruction *rinstr = NULL;
+		for (int i = 0; ; ++i) {
+			if (reg_instructions[i].mnemonic == NULL)
+				break;
+			if (reg_instructions[i].opcode == (opcode << 4) + REG_opcode2) {
+				rinstr = &reg_instructions[i];
+				break;
+			}
+		}
+
+		bool has_src1 = true, has_src2 = true, has_dst = true, has_src3 = false;
+
+		if (rinstr == NULL) {
+			debug("unknown_reg_0x%02x:0x%x", opcode, REG_opcode2);
+		} else {
+			debug("%s", rinstr->mnemonic);
+			has_src1 = rinstr->has_src1;
+			has_src2 = rinstr->has_src2;
+			has_dst = rinstr->has_dst;
+			has_src3 = rinstr->has_src3;
+		}
+
+		if (has_src1)
+			debug("\t%s", regname_or_literal(REG_src1, REG_m1, REG_sfr1));
+
+		if (has_src2) {
+			if (has_src1)
+				debug(",");
+
+			debug("%s", regname_or_literal(REG_src2, REG_m2, REG_sfr2));
+		}
+		
+		if (has_dst) {
+			if (has_src1 || has_src2)
+				debug(",");
+
+			if (REG_m3) {
+				/*
+				 *  The manual for i960CA says (when M3 = 1):
+				 *
+				 *  "src/dst is a literal when used as a source
+				 *   or a special function register when used
+				 *   as a destination. M3 may not be 1 when
+				 *   src/dst is used both as a source and 
+				 *   destination in an instruction (atmod,
+				 *   modify, extract, modpc)."
+				 */
+				if (has_src3)
+					debug("%s", regname_or_literal(REG_src_dst, 1, 0));
+				else
+					debug("%s", regname_or_literal(REG_src_dst, 0, 1));
+			} else
+				debug("%s", regname_or_literal(REG_src_dst, 0, 0));
+		}
+	} else if (opcode >= 0x80 && opcode <= 0xcf) {
+		/*  MEM:  */
+		
+		/*  NOTE: These are for i960CA. When implementing support for
+		    other CPU variants, include an enum indicating which CPU
+		    it is for so that a warning can be printed for instructions
+		    that will cause faults on another CPU.  */
+		const char* mnemonics[] = {
+			"ldob",			/*  0x80  */
+			"unknown_mem_0x81",	/*  0x81 BiiN ldvob  */
+			"stob",			/*  0x82  */
+			"unknown_mem_0x83",	/*  0x83 BiiN stvob  */
+			"bx",			/*  0x84  */
+			"balx",			/*  0x85  */
+			"callx",		/*  0x86  */
+			"unknown_mem_0x87",	/*  0x87  */
+
+			"ldos",			/*  0x88  */
+			"unknown_mem_0x89",	/*  0x89 BiiN ldvos  */
+			"stos",			/*  0x8a  */
+			"unknown_mem_0x8b",	/*  0x8b BiiN stvos  */
+			"lda",			/*  0x8c  */
+			"unknown_mem_0x8d",	/*  0x8d  */
+			"unknown_mem_0x8e",	/*  0x8e  */
+			"unknown_mem_0x8f",	/*  0x8f  */
+
+			"ld",			/*  0x90  */
+			"unknown_mem_0x91",	/*  0x91 BiiN ldv  */
+			"st",			/*  0x92  */
+			"unknown_mem_0x93",	/*  0x93 Biin stv  */
+			"unknown_mem_0x94",	/*  0x94  */
+			"unknown_mem_0x95",	/*  0x95  */
+			"unknown_mem_0x96",	/*  0x96  */
+			"unknown_mem_0x97",	/*  0x97  */
+
+			"ldl",			/*  0x98  */
+			"unknown_mem_0x99",	/*  0x99 BiiN ldvl  */
+			"stl",			/*  0x9a  */
+			"unknown_mem_0x9b",	/*  0x9b BiiN stvl  */
+			"unknown_mem_0x9c",	/*  0x9c  */
+			"unknown_mem_0x9d",	/*  0x9d  */
+			"unknown_mem_0x9e",	/*  0x9e  */
+			"unknown_mem_0x9f",	/*  0x9f  */
+
+			"ldt",			/*  0xa0  */
+			"unknown_mem_0xa1",	/*  0xa1 BiiN ldvt  */
+			"stt",			/*  0xa2  */
+			"unknown_mem_0xa3",	/*  0xa3 Biin stvt  */
+			"unknown_mem_0xa4",	/*  0xa4  */
+			"unknown_mem_0xa5",	/*  0xa5  */
+			"unknown_mem_0xa6",	/*  0xa6  */
+			"unknown_mem_0xa7",	/*  0xa7  */
+
+			"unknown_mem_0xa8",	/*  0xa8  */
+			"unknown_mem_0xa9",	/*  0xa9  */
+			"unknown_mem_0xaa",	/*  0xaa  */
+			"unknown_mem_0xab",	/*  0xab  */
+			"unknown_mem_0xac",	/*  0xac  */
+			"unknown_mem_0xad",	/*  0xad  */
+			"unknown_mem_0xae",	/*  0xae  */
+			"unknown_mem_0xaf",	/*  0xaf  */
+
+			"ldq",			/*  0xb0  */
+			"unknown_mem_0xb1",	/*  0xb1 BiiN ldvq  */
+			"stq",			/*  0xb2  */
+			"unknown_mem_0xb3",	/*  0xb3 BiiN stvq  */
+			"unknown_mem_0xb4",	/*  0xb4  */
+			"unknown_mem_0xb5",	/*  0xb5  */
+			"unknown_mem_0xb6",	/*  0xb6  */
+			"unknown_mem_0xb7",	/*  0xb7  */
+
+			"unknown_mem_0xb8",	/*  0xb8  */
+			"unknown_mem_0xb9",	/*  0xb9  */
+			"unknown_mem_0xba",	/*  0xba  */
+			"unknown_mem_0xbb",	/*  0xbb  */
+			"unknown_mem_0xbc",	/*  0xbc  */
+			"unknown_mem_0xbd",	/*  0xbd  */
+			"unknown_mem_0xbe",	/*  0xbe  */
+			"unknown_mem_0xbf",	/*  0xbf  */
+
+			"ldib",			/*  0xc0  */
+			"unknown_mem_0xc1",	/*  0xc1 BiiN ldvib  */
+			"stib",			/*  0xc2  */
+			"unknown_mem_0xc3",	/*  0xc3 Biin stvib  */
+			"unknown_mem_0xc4",	/*  0xc4  */
+			"unknown_mem_0xc5",	/*  0xc5  */
+			"unknown_mem_0xc6",	/*  0xc6  */
+			"unknown_mem_0xc7",	/*  0xc7  */
+
+			"ldis",			/*  0xc8  */
+			"unknown_mem_0xc9",	/*  0xc9 BiiN ldvis  */
+			"stis",			/*  0xca  */
+			"unknown_mem_0xcb",	/*  0xcb BiiN stvis  */
+			"unknown_mem_0xcc",	/*  0xcc  */
+			"unknown_mem_0xcd",	/*  0xcd  */
+			"unknown_mem_0xce",	/*  0xce  */
+			"unknown_mem_0xcf",	/*  0xcf  */
+			
+			/*  BiiN:
+				d0 = ldm
+				d1 = ldvm
+				d2 = stm
+				d3 = stvm
+				d8 = ldml
+				d9 = ldvml
+				da = stml
+				db = stvml */
+			};
+
+		debug("%s\t", mnemonics[opcode - 0x80]);
+
+		bool usesDst = opcode != 0x84 && opcode != 0x86;
+		bool isStore = !!(opcode & 2);
+
+		if (usesDst && isStore)
+			debug("%s,", regname_or_literal(MEMB_src_dst, 0, 0));
+
+		if (iw & 0x1000) {
+			/*  MEMB:  */
+			int scale = 1 << MEMB_scale;
+			switch (MEMB_mode) {
+			case 0x4:
+				debug("(%s)", regname_or_literal(MEMB_abase, 0, 0));
+				break;
+			case 0x5:
+				{
+					uint32_t offset32 = iw2 + 8;
+					debug("0x%x(ip)", offset32);
+				}
+				break;
+			case 0x7:
+				// (reg1)[reg2 * scale]
+				debug("(%s)", regname_or_literal(MEMB_abase, 0, 0));
+				debug("[%s*%i]", regname_or_literal(MEMB_index, 0, 0), scale);
+				break;
+			case 0xc:
+			case 0xd:
+				{
+					uint32_t offset32 = iw2;
+					debug("0x%x", offset32);
+					if (MEMB_mode == 0xd)
+						debug("(%s)", regname_or_literal(MEMB_abase, 0, 0));
+				}
+				break;
+			case 0xe:
+			case 0xf:
+				{
+					uint32_t offset32 = iw2;
+					debug("0x%x", offset32);
+					if (MEMB_mode == 0xf)
+						debug("(%s)", regname_or_literal(MEMB_abase, 0, 0));
+
+					debug("[%s*%i]", regname_or_literal(MEMB_index, 0, 0), scale);
+				}
+				break;
+			default:
+				debug("unimplemented MEMB mode!");
+			}
+		} else {
+			/*  MEMA:  */
+			debug("0x%x", MEMA_offset);
+
+			if (MEMA_md)
+				debug("(%s)", regname_or_literal(MEMA_abase, 0, 0));
+		}
+
+		if (usesDst && !isStore)
+			debug(",%s", regname_or_literal(MEMB_src_dst, 0, 0));
+	} else if (iw == 0) {
+		debug("--");
+	} else {
+		debug("unimplemented opcode %i", opcode);
+	}
+
+	debug("\n");
+
+	return is_64bit_long_instruction ? sizeof(uint64_t) : sizeof(uint32_t);
+}
+
+
+#include "tmp_i960_tail.c"
+
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_i960_instr.c gxemul-0.7.0+dfsg/src/cpus/cpu_i960_instr.c
--- gxemul-0.6.2/src/cpus/cpu_i960_instr.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_i960_instr.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,208 @@
+/*
+ *  Copyright (C) 2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Intel 80960 (i960) instructions.
+ *
+ *  Individual functions should keep track of cpu->n_translated_instrs.
+ *  (If no instruction was executed, then it should be decreased. If, say, 4
+ *  instructions were combined into one function and executed, then it should
+ *  be increased by 3.)
+ */
+
+
+#define SYNCH_PC                {                                       \
+                int low_pc_ = ((size_t)ic - (size_t)cpu->cd.i960.cur_ic_page) \
+                    / sizeof(struct i960_instr_call);                   \
+                cpu->pc &= ~((I960_IC_ENTRIES_PER_PAGE-1)               \
+                    << I960_INSTR_ALIGNMENT_SHIFT);                     \
+                cpu->pc += (low_pc_ << I960_INSTR_ALIGNMENT_SHIFT);      \
+        }
+
+#define	ABORT_EXECUTION	  {	SYNCH_PC;				\
+				cpu->cd.i960.next_ic = &nothing_call;	\
+				cpu->running = false; }
+
+
+/*
+ *  nop:  Do nothing.
+ */
+X(nop)
+{
+}
+
+
+/*****************************************************************************/
+
+
+X(end_of_page)
+{
+	/*  Update the PC:  (offset 0, but on the next page)  */
+	cpu->pc &= ~((I960_IC_ENTRIES_PER_PAGE-1) <<
+	    I960_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (I960_IC_ENTRIES_PER_PAGE << I960_INSTR_ALIGNMENT_SHIFT);
+
+	/*  end_of_page doesn't count as an executed instruction:  */
+	cpu->n_translated_instrs --;
+
+	/*
+	 *  Find the new physpage and update translation pointers.
+	 *
+	 *  Note: This may cause an exception, if e.g. the new page is
+	 *  not accessible.
+	 */
+	quick_pc_to_pointers(cpu);
+
+	/*  Simple jump to the next page (if we are lucky):  */
+	if (cpu->delay_slot == NOT_DELAYED)
+		return;
+
+	/*
+	 *  If we were in a delay slot, and we got an exception while doing
+	 *  quick_pc_to_pointers, then return. The function which called
+	 *  end_of_page should handle this case.
+	 */
+	if (cpu->delay_slot == EXCEPTION_IN_DELAY_SLOT)
+		return;
+
+	/*
+	 *  Tricky situation; the delay slot is on the next virtual page.
+	 *  Calling to_be_translated will translate one instruction manually,
+	 *  execute it, and then discard it.
+	 */
+	/*  fatal("[ end_of_page: delay slot across page boundary! ]\n");  */
+
+	instr(to_be_translated)(cpu, cpu->cd.i960.next_ic);
+
+	/*  The instruction in the delay slot has now executed.  */
+	/*  fatal("[ end_of_page: back from executing the delay slot, %i ]\n",
+	    cpu->delay_slot);  */
+
+	/*  Find the physpage etc of the instruction in the delay slot
+	    (or, if there was an exception, the exception handler):  */
+	quick_pc_to_pointers(cpu);
+}
+
+
+X(end_of_page2)
+{
+	/*  Synchronize PC on the _second_ instruction on the next page:  */
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.i960.cur_ic_page)
+	    / sizeof(struct i960_instr_call);
+	cpu->pc &= ~((I960_IC_ENTRIES_PER_PAGE-1)
+	    << I960_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << I960_INSTR_ALIGNMENT_SHIFT);
+
+	if (low_pc < 0 || low_pc > ((I960_IC_ENTRIES_PER_PAGE+1)
+	    << I960_INSTR_ALIGNMENT_SHIFT)) {
+		printf("[ end_of_page2: HUH? low_pc=%i, cpu->pc = %08"
+		    PRIx32" ]\n", low_pc, (uint32_t) cpu->pc);
+	}
+
+	/*  This doesn't count as an executed instruction.  */
+	cpu->n_translated_instrs --;
+
+	quick_pc_to_pointers(cpu);
+
+	if (cpu->delay_slot == NOT_DELAYED)
+		return;
+
+	debugmsg_cpu(cpu, SUBSYS_CPU, "i960", VERBOSITY_ERROR,
+	    "end_of_page2: fatal error, we're in a delay slot");
+	ABORT_EXECUTION;
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  i960_instr_to_be_translated():
+ *
+ *  Translate an instruction word into a i960_instr_call. ic is filled in with
+ *  valid data for the translated instruction, or a "nothing" instruction if
+ *  there was a translation failure. The newly translated instruction is then
+ *  executed.
+ */
+X(to_be_translated)
+{
+	/*  Figure out the (virtual) address of the instruction:  */
+	uint32_t low_pc = ((size_t)ic - (size_t)cpu->cd.i960.cur_ic_page)
+	    / sizeof(struct i960_instr_call);
+
+	uint32_t addr = cpu->pc & ~((I960_IC_ENTRIES_PER_PAGE-1)
+	    << I960_INSTR_ALIGNMENT_SHIFT);
+	addr += (low_pc << I960_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc = (uint32_t)addr;
+	addr &= ~((1 << I960_INSTR_ALIGNMENT_SHIFT) - 1);
+
+	/*  Read the instruction word from memory:  */
+	uint8_t* page = cpu->cd.i960.host_load[(uint32_t)addr >> 12];
+
+	unsigned char ib[4];
+
+	if (page != NULL) {
+		/*  fatal("TRANSLATION HIT!\n");  */
+		memcpy(ib, page + (addr & 0xffc), sizeof(ib));
+	} else {
+		/*  fatal("TRANSLATION MISS!\n");  */
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
+		    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
+			fatal("to_be_translated(): read failed: TODO\n");
+			goto bad;
+		}
+	}
+
+	uint32_t iw;
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
+	else
+		iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);
+
+	const int opcode = iw >> 24;
+
+
+#define DYNTRANS_TO_BE_TRANSLATED_HEAD
+#include "cpu_dyntrans.c"
+#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD
+
+
+	/*
+	 *  Translate the instruction:
+	 */
+
+	switch (opcode) {
+
+	default:goto bad;
+	}
+
+
+#define	DYNTRANS_TO_BE_TRANSLATED_TAIL
+#include "cpu_dyntrans.c" 
+#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_m88k.c gxemul-0.7.0+dfsg/src/cpus/cpu_m88k.c
--- gxemul-0.6.2/src/cpus/cpu_m88k.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_m88k.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1563 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Motorola M881x0 CPU emulation.
+ *
+ *  M88100: Disassembly of (almost?) everything, and execution of most
+ *          instructions. Exception handling and virtual memory has also
+ *          been implemented. Exceptions while in delay slots may not work
+ *          fully yet, though.
+ *
+ *  M88110: Not yet. 
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <unistd.h>
+
+#include "cpu.h"
+#include "float_emul.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "settings.h"
+#include "symbol.h"
+
+#include "thirdparty/m8820x_pte.h"
+#include "thirdparty/m88k_dmt.h"
+#include "thirdparty/mvmeprom.h"
+
+#define DYNTRANS_32
+#define DYNTRANS_DELAYSLOT
+#include "tmp_m88k_head.c"
+
+
+void m88k_pc_to_pointers(struct cpu *);
+void m88k_cpu_functioncall_trace(struct cpu *cpu, int n_args);
+
+static const char *memop[4] = { ".d", "", ".h", ".b" };
+
+void m88k_irq_interrupt_assert(struct interrupt *interrupt);
+void m88k_irq_interrupt_deassert(struct interrupt *interrupt);
+
+
+static const char *m88k_cr_names[] = M88K_CR_NAMES;
+static const char *m88k_cr_197_names[] = M88K_CR_NAMES_197;
+
+static const char *m88k_cr_name(struct cpu *cpu, int i)
+{
+	const char **cr_names = m88k_cr_names;
+
+	/*  Hm. Is this really MVME197 specific? TODO  */
+	if (cpu->machine->machine_subtype == MACHINE_MVME88K_197)
+		cr_names = m88k_cr_197_names;
+
+	return cr_names[i];
+}
+
+static char *m88k_fcr_name(struct cpu *cpu, int fi)
+{
+	/*  TODO  */
+	static char fcr_name[10];
+	snprintf(fcr_name, sizeof(fcr_name), "FCR%i", fi);
+	return fcr_name;
+}
+
+
+
+/*
+ *  m88k_cpu_new():
+ *
+ *  Create a new M88K cpu object by filling the CPU struct.
+ *  Return 1 on success, 0 if cpu_type_name isn't a valid M88K processor.
+ */
+int m88k_cpu_new(struct cpu *cpu, struct memory *mem,
+	struct machine *machine, int cpu_id, char *cpu_type_name)
+{
+	int i, found;
+	struct m88k_cpu_type_def cpu_type_defs[] = M88K_CPU_TYPE_DEFS;
+
+	/*  Scan the list for this cpu type:  */
+	i = 0; found = -1;
+	while (i >= 0 && cpu_type_defs[i].name != NULL) {
+		if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
+			found = i;
+			break;
+		}
+		i++;
+	}
+	if (found == -1)
+		return 0;
+
+	cpu->run_instr = m88k_run_instr;
+	cpu->memory_rw = m88k_memory_rw;
+	cpu->update_translation_table = m88k_update_translation_table;
+	cpu->invalidate_translation_caches =
+	    m88k_invalidate_translation_caches;
+	cpu->invalidate_code_translation = m88k_invalidate_code_translation;
+	cpu->translate_v2p = m88k_translate_v2p;
+
+	cpu->cd.m88k.cpu_type = cpu_type_defs[found];
+	cpu->name            = strdup(cpu->cd.m88k.cpu_type.name);
+	cpu->is_32bit        = 1;
+	cpu->byte_order      = EMUL_BIG_ENDIAN;
+
+	cpu->instruction_has_delayslot = m88k_cpu_instruction_has_delayslot;
+
+	cpu->vaddr_mask = 0x00000000ffffffffULL;
+
+
+	/*
+	 *  Add register names as settings:
+	 */
+
+	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
+
+	for (i=0; i<N_M88K_REGS; i++) {
+		char name[10];
+		snprintf(name, sizeof(name), "r%i", i);
+		CPU_SETTINGS_ADD_REGISTER32(name, cpu->cd.m88k.r[i]);
+	}
+
+	for (i=0; i<N_M88K_CONTROL_REGS; i++) {
+		char name[10];
+		snprintf(name, sizeof(name), "%s", m88k_cr_name(cpu, i));
+		CPU_SETTINGS_ADD_REGISTER32(name, cpu->cd.m88k.cr[i]);
+	}
+
+	for (i=0; i<N_M88K_FPU_CONTROL_REGS; i++) {
+		char name[10];
+		snprintf(name, sizeof(name), "%s", m88k_fcr_name(cpu, i));
+		CPU_SETTINGS_ADD_REGISTER32(name, cpu->cd.m88k.fcr[i]);
+	}
+
+
+	/*  Register the CPU interrupt pin:  */
+	{
+		struct interrupt templ;
+		char name[50];
+		snprintf(name, sizeof(name), "%s", cpu->path);
+
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 0;
+		templ.name = name;
+		templ.extra = cpu;
+		templ.interrupt_assert = m88k_irq_interrupt_assert;
+		templ.interrupt_deassert = m88k_irq_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	/*  Set the Processor ID:  */
+	cpu->cd.m88k.cr[M88K_CR_PID] = cpu->cd.m88k.cpu_type.pid | M88K_PID_MC;
+
+	/*  Start in supervisor mode, with interrupts disabled.  */
+	cpu->cd.m88k.cr[M88K_CR_PSR] = M88K_PSR_MODE | M88K_PSR_IND;
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		cpu->cd.m88k.cr[M88K_CR_PSR] |= M88K_PSR_BO;
+
+	/*  Initial stack pointer:  */
+	cpu->cd.m88k.r[31] = 1048576 * cpu->machine->physical_ram_in_mb - 1024;
+
+	return 1;
+}
+
+
+/*
+ *  m88k_cpu_dumpinfo():
+ */
+void m88k_cpu_dumpinfo(struct cpu *cpu, bool verbose)
+{
+	debugmsg(SUBSYS_MACHINE, "cpu", VERBOSITY_INFO,
+	    "%s (%s-endian)",
+	    cpu->name,
+	    cpu->byte_order == EMUL_BIG_ENDIAN? "Big" : "Little");
+}
+
+
+/*
+ *  m88k_cpu_list_available_types():
+ *
+ *  Print a list of available M88K CPU types.
+ */
+void m88k_cpu_list_available_types(void)
+{
+	int i, j;
+	struct m88k_cpu_type_def tdefs[] = M88K_CPU_TYPE_DEFS;
+
+	i = 0;
+	while (tdefs[i].name != NULL) {
+		debug("%s", tdefs[i].name);
+		for (j=13 - strlen(tdefs[i].name); j>0; j--)
+			debug(" ");
+		i++;
+		if ((i % 5) == 0 || tdefs[i].name == NULL)
+			debug("\n");
+	}
+}
+
+
+/*
+ *  m88k_cpu_instruction_has_delayslot():
+ *
+ *  Returns 1 if an opcode has a delay slot after it, 0 otherwise.
+ */
+int m88k_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
+{
+	uint32_t iword = *((uint32_t *)&ib[0]);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iword = LE32_TO_HOST(iword);
+	else
+		iword = BE32_TO_HOST(iword);
+
+	switch (iword >> 26) {
+	case 0x31:	/*  br.n  */
+	case 0x33:	/*  bsr.n  */
+	case 0x35:	/*  bb0.n  */
+	case 0x37:	/*  bb1.n  */
+	case 0x3b:	/*  bcnd.n  */
+		return 1;
+	case 0x3d:
+		switch ((iword >> 8) & 0xff) {
+		case 0xc4:	/*  jmp.n  */
+		case 0xcc:	/*  jsr.n  */
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+
+/*
+ *  m88k_cpu_register_dump():
+ *
+ *  Dump cpu registers in a relatively readable format.
+ *  
+ *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
+ *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
+ */
+void m88k_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
+{
+	char *symbol;
+	uint64_t offset;
+	int i, x = cpu->cpu_id;
+
+	if (gprs) {
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    cpu->pc, &offset);
+		debug("cpu%i:  pc  = 0x%08" PRIx32, x, (uint32_t)cpu->pc);
+		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
+
+		for (i=0; i<N_M88K_REGS; i++) {
+			if ((i % 4) == 0)
+				debug("cpu%i:", x);
+			if (i == 0)
+				debug("                  ");
+			else
+				debug("  r%-2i = 0x%08" PRIx32,
+				    i, cpu->cd.m88k.r[i]);
+			if ((i % 4) == 3)
+				debug("\n");
+		}
+	}
+
+	if (coprocs & 1) {
+		int n_control_regs = 32;
+
+		/*  Hm. Is this really MVME197 specific? TODO  */
+		if (cpu->machine->machine_subtype == MACHINE_MVME88K_197)
+			n_control_regs = 64;
+
+		for (i=0; i<n_control_regs; i++) {
+			if ((i % 4) == 0)
+				debug("cpu%i:", x);
+			debug("  %4s=0x%08" PRIx32,
+			    m88k_cr_name(cpu, i), cpu->cd.m88k.cr[i]);
+			if ((i % 4) == 3)
+				debug("\n");
+		}
+	}
+
+	if (coprocs & 2) {
+		int n_fpu_control_regs = 64;
+
+		for (i=0; i<n_fpu_control_regs; i++) {
+			if ((i % 4) == 0)
+				debug("cpu%i:", x);
+			debug("  %5s=0x%08" PRIx32,
+			    m88k_fcr_name(cpu, i), cpu->cd.m88k.fcr[i]);
+			if ((i % 4) == 3)
+				debug("\n");
+		}
+	}
+}
+
+
+/*
+ *  m88k_cpu_tlbdump():
+ *
+ *  Called from the debugger to dump the TLB in a readable format.
+ *
+ *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
+ *  just dumped.
+ */
+void m88k_cpu_tlbdump(struct cpu* cpu, int rawflag)
+{
+	int cpu_nr = -1, cmmu_nr, i;
+
+	for (i = 0; i < cpu->machine->ncpus; ++i)
+		if (cpu == cpu->machine->cpus[i])
+			cpu_nr = i;
+
+	for (cmmu_nr = 0; cmmu_nr < MAX_M8820X_CMMUS; cmmu_nr++) {
+		struct m8820x_cmmu *cmmu = cpu->cd.m88k.cmmu[cmmu_nr];
+		if (cmmu == NULL)
+			continue;
+
+		printf("cpu%i: CMMU %i (%s)\n", cpu_nr, cmmu_nr,
+		    cmmu_nr & 1? "data" : "instruction");
+
+		/*  BATC:  */
+		for (i = 0; i < N_M88200_BATC_REGS; i++) {
+			uint32_t b = cmmu->batc[i];
+			printf("cpu%i: BATC[%2i]: ", cpu_nr, i);
+			printf("v=0x%08" PRIx32, b & 0xfff80000);
+			printf(", p=0x%08" PRIx32,
+			    (b << 13) & 0xfff80000);
+			printf(", %s %s %s %s %s %s\n",
+			    b & BATC_SO? "SP " : "!sp",
+			    b & BATC_WT? "WT " : "!wt",
+			    b & BATC_GLOBAL? "G  " : "!g ",
+			    b & BATC_INH? "CI " : "!ci",
+			    b & BATC_PROT? "WP " : "!wp",
+			    b & BATC_SO? "V " : "!v");
+		}
+
+		/*  PATC:  */
+		for (i = 0; i < N_M88200_PATC_ENTRIES; i++) {
+			uint32_t v = cmmu->patc_v_and_control[i];
+			uint32_t p = cmmu->patc_p_and_supervisorbit[i];
+
+			printf("cpu%i: patc[%2i]: ", cpu_nr, i);
+			if (p & M8820X_PATC_SUPERVISOR_BIT)
+				printf("superv");
+			else
+				printf("user  ");
+			printf(" v=0x%08" PRIx32, v & 0xfffff000);
+			printf(", p=0x%08" PRIx32, p & 0xfffff000);
+
+			printf("  %s %s %s %s %s %s %s",
+			    v & PG_U1?   "U1 " : "!u1",
+			    v & PG_U0?   "U0 " : "!u0",
+			    v & PG_SO?   "SP " : "!sp",
+			    v & PG_M?    "M "  : "!m",
+			    v & PG_U?    "U "  : "!u",
+			    v & PG_PROT? "WP " : "!wp",
+			    v & PG_V?    "V "  : "!v");
+
+			if (i == cmmu->patc_update_index)
+				printf(" <--");
+			printf("\n");
+		}
+	}
+}
+
+
+/*
+ *  m88k_irq_interrupt_assert():
+ *  m88k_irq_interrupt_deassert():
+ */
+void m88k_irq_interrupt_assert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.m88k.irq_asserted = 1;
+}
+void m88k_irq_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.m88k.irq_asserted = 0;
+}
+
+
+/*
+ *  m88k_ldcr():
+ *
+ *  Read from a control register. Store the resulting value in a register
+ *  (pointed to by r32ptr).
+ */
+void m88k_ldcr(struct cpu *cpu, uint32_t *r32ptr, int cr)
+{
+	uint32_t retval = cpu->cd.m88k.cr[cr];
+
+	switch (cr) {
+
+	case M88K_CR_PID:
+	case M88K_CR_PSR:
+	case M88K_CR_EPSR:
+	case M88K_CR_SSBR:
+	case M88K_CR_SXIP:
+	case M88K_CR_SNIP:
+	case M88K_CR_SFIP:
+	case M88K_CR_VBR:
+	case M88K_CR_DMD0:
+	case M88K_CR_DMD1:
+	case M88K_CR_DMD2:
+	case M88K_CR_SR0:
+	case M88K_CR_SR1:
+	case M88K_CR_SR2:
+	case M88K_CR_SR3:
+		break;
+
+	case M88K_CR_DMT0:
+	case M88K_CR_DMT1:
+	case M88K_CR_DMT2:
+		/*
+		 *  Catch some possible internal errors in the emulator:
+		 *
+		 *  For valid memory Load transactions, the Destination Register
+		 *  should not be zero.
+		 *
+		 *  The Byte Order bit should be the same as the CPU's.
+		 */
+		if (retval & DMT_VALID && !(retval & DMT_WRITE)) {
+			if (DMT_DREGBITS(retval) == M88K_ZERO_REG) {
+				debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+				    "ldcr: DMT DREG = zero? Internal error.");
+				cpu->running = false;
+				return;
+			}
+		}
+		if (!!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_BO)
+		    != !!(retval & DMT_BO) && retval & DMT_VALID) {
+			debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+			    "ldcr: DMT byte order not same as CPUs?");
+			cpu->running = false;
+			return;
+		}
+
+		break;
+
+	case M88K_CR_DMA0:
+	case M88K_CR_DMA1:
+	case M88K_CR_DMA2:
+		/*
+		 *  Catch some possible internal errors in the emulator:
+		 *  The lowest 2 bits of the transaction address registers
+		 *  should always be zero.
+		 */
+		if (retval & 3) {
+			debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+			    "ldcr: DMAx not word-aligned? Internal error.");
+			cpu->running = false;
+			return;
+		}
+
+		break;
+
+	default:debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+		    "ldcr: UNIMPLEMENTED cr = 0x%02x (%s)\n",
+		    cr, m88k_cr_name(cpu, cr));
+		cpu->running = false;
+		return;
+	}
+
+	*r32ptr = retval;
+}
+
+
+/*
+ *  m88k_stcr():
+ *
+ *  Write to a control register.
+ *  (Used by both the stcr and rte instructions.)
+ */
+void m88k_stcr(struct cpu *cpu, uint32_t value, int cr, int rte)
+{
+	uint32_t old = cpu->cd.m88k.cr[cr];
+
+	switch (cr) {
+
+	case M88K_CR_PSR:	/*  Processor Status Register  */
+		if ((cpu->byte_order == EMUL_LITTLE_ENDIAN
+		    && !(value & M88K_PSR_BO)) ||
+		    (cpu->byte_order == EMUL_BIG_ENDIAN
+		    && (value & M88K_PSR_BO))) {
+			debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+			    "stcr: TODO: attempt to change endianness by flipping"
+			    " the endianness bit in the PSR. How should this"
+			    " be handled? Aborting.");
+			cpu->running = false;
+			return;
+		}
+
+		if (!rte && old & M88K_PSR_MODE && !(value & M88K_PSR_MODE))
+			debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_WARNING,
+			    "stcr: WARNING! the PSR_MODE bit is being"
+			    " cleared; this should be done using the RTE "
+			    "instruction only, according to the M88100 "
+			    "manual! Continuing anyway.");
+
+		if (value & M88K_PSR_MXM) {
+			debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+			    "stcr: TODO: MXM support");
+			cpu->running = false;
+			return;
+		}
+
+		if ((old & M88K_PSR_MODE) != (value & M88K_PSR_MODE))
+			cpu->invalidate_translation_caches(
+			    cpu, 0, INVALIDATE_ALL);
+
+		cpu->cd.m88k.cr[cr] = value;
+		break;
+
+	case M88K_CR_EPSR:
+		cpu->cd.m88k.cr[cr] = value;
+		break;
+
+	case M88K_CR_SXIP:
+	case M88K_CR_SNIP:
+	case M88K_CR_SFIP:
+		cpu->cd.m88k.cr[cr] = value;
+		break;
+
+	case M88K_CR_SSBR:	/*  Shadow ScoreBoard Register  */
+		if (value & 1)
+			debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_WARNING,
+			    "stcr: WARNING! bit 0 non-zero when"
+			    " writing to SSBR (?)");
+
+		cpu->cd.m88k.cr[cr] = value;
+		break;
+
+	case M88K_CR_VBR:
+		if (value & 0x00000fff)
+			debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_WARNING,
+			    "stcr: WARNING! bits 0..11 non-zero when"
+			    " writing to VBR (?)");
+
+		cpu->cd.m88k.cr[cr] = value;
+		break;
+
+	case M88K_CR_DMT0:
+	case M88K_CR_DMT1:
+	case M88K_CR_DMT2:
+		cpu->cd.m88k.cr[cr] = value;
+		break;
+
+	case M88K_CR_SR0:	/*  Supervisor Storage Registers 0..3  */
+	case M88K_CR_SR1:
+	case M88K_CR_SR2:
+	case M88K_CR_SR3:
+		cpu->cd.m88k.cr[cr] = value;
+		break;
+
+	default:debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+		    "stcr: UNIMPLEMENTED cr = 0x%02x (%s)",
+		    cr, m88k_cr_name(cpu, cr));
+		cpu->running = false;
+		return;
+	}
+}
+
+
+/*
+ *  m88k_fstcr():
+ *
+ *  Write to a floating-point control register.
+ */
+void m88k_fstcr(struct cpu *cpu, uint32_t value, int fcr)
+{
+	switch (fcr) {
+
+	case 0:
+	case 62:
+	case 63:
+		// Don't warn for writes with the value zero for these, for now.
+		if (value == 0)
+			break;
+
+		// fall through
+	
+	default:debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_WARNING,
+		    "WARNING: fstcr: write 0x%08x to UNIMPLEMENTED fcr = 0x%02x (%s)",
+		    value, fcr, m88k_fcr_name(cpu, fcr));
+	}
+
+	cpu->cd.m88k.fcr[fcr] = value;
+}
+
+
+/*
+ *  m88k_memory_transaction_debug_dump():
+ *
+ *  Debug dump of the memory transaction registers of a cpu.
+ */
+static void m88k_memory_transaction_debug_dump(struct cpu *cpu, int n)
+{
+	uint32_t dmt = cpu->cd.m88k.dmt[n];
+
+	debug("[ DMT%i: ", n);
+	if (dmt & DMT_VALID) {
+		if (dmt & DMT_BO)
+			debug("Little-Endian, ");
+		else
+			debug("Big-Endian, ");
+		if (dmt & DMT_DAS)
+			debug("Supervisor, ");
+		else
+			debug("User, ");
+		if (dmt & DMT_DOUB1)
+			debug("DOUB1, ");
+		if (dmt & DMT_LOCKBAR)
+			debug("LOCKBAR, ");
+		if (dmt & DMT_WRITE)
+			debug("store, ");
+		else {
+			debug("load.%c(r%i), ",
+			    dmt & DMT_SIGNED? 's' : 'u',
+			    DMT_DREGBITS(dmt));
+		}
+		debug("bytebits=0x%x ]\n", DMT_ENBITS(dmt));
+
+		debug("[ DMD%i: 0x%08" PRIx32"; ", n, cpu->cd.m88k.dmd[n]);
+		debug("DMA%i: 0x%08" PRIx32" ]\n", n, cpu->cd.m88k.dma[n]);
+	} else
+		debug("not valid ]\n");
+}
+
+
+/*
+ *  m88k_exception():
+ *
+ *  Cause an exception.
+ */
+void m88k_exception(struct cpu *cpu, int vector, int is_trap)
+{
+	bool update_shadow_regs = true;
+	bool implemented = false;
+
+	// TODO: Use a const char * instead or something like that, inside the switch...
+
+	switch (vector) {
+
+	case M88K_EXCEPTION_RESET:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "RESET", VERBOSITY_INFO, "");
+		implemented = true;
+		break;
+
+	case M88K_EXCEPTION_INTERRUPT:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "INTERRUPT", VERBOSITY_INFO, "");
+		implemented = true;
+		break;
+
+	case M88K_EXCEPTION_INSTRUCTION_ACCESS:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "INSTRUCTION_ACCESS", VERBOSITY_INFO, "");
+		implemented = true;
+		break;
+
+	case M88K_EXCEPTION_DATA_ACCESS:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "DATA_ACCESS", VERBOSITY_INFO, "");
+		implemented = true;
+		break;
+
+	case M88K_EXCEPTION_MISALIGNED_ACCESS:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "MISALIGNED_ACCESS", VERBOSITY_ERROR, "");
+		break;
+
+	case M88K_EXCEPTION_UNIMPLEMENTED_OPCODE:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "UNIMPLEMENTED_OPCODE", VERBOSITY_ERROR, "");
+		break;
+
+	case M88K_EXCEPTION_PRIVILEGE_VIOLATION:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "PRIVILEGE_VIOLATION", VERBOSITY_ERROR, "");
+		break;
+
+	case M88K_EXCEPTION_BOUNDS_CHECK_VIOLATION:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "BOUNDS_CHECK_VIOLATION", VERBOSITY_ERROR, "");
+		break;
+
+	case M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "ILLEGAL_INTEGER_DIVIDE", VERBOSITY_ERROR, "");
+		break;
+
+	case M88K_EXCEPTION_INTEGER_OVERFLOW:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "INTEGER_OVERFLOW", VERBOSITY_ERROR, "");
+		break;
+
+	case M88K_EXCEPTION_ERROR:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "ERROR", VERBOSITY_ERROR, "");
+		break;
+
+	case M88K_EXCEPTION_SFU1_PRECISE:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "SFU1_PRECISE", VERBOSITY_ERROR, "");
+		break;
+
+	case M88K_EXCEPTION_SFU1_IMPRECISE:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "SFU1_IMPRECISE", VERBOSITY_ERROR, "");
+		break;
+
+	case 0x80:	/*  up to OpenBSD 5.2  */
+	case 0x1c2:	/*  from OpenBSD 5.3 and forward...  */
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "syscall", VERBOSITY_INFO,
+		    "r13=%i", cpu->cd.m88k.r[13]);
+#if 0
+		fatal("[ syscall %i(", cpu->cd.m88k.r[13]);
+		m88k_cpu_functioncall_trace(cpu, 8);
+		fatal(") ]\n");
+#endif
+		break;
+
+	case MVMEPROM_VECTOR:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "MVMEPROM_VECTOR", VERBOSITY_INFO, "");
+		break;
+
+	default:
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "unknown vector",
+		    vector < M88K_EXCEPTION_USER_TRAPS_START ? VERBOSITY_ERROR
+		    : VERBOSITY_INFO, "0x%03x", vector);
+	}
+
+	if (vector < M88K_EXCEPTION_USER_TRAPS_START && !implemented) {
+		debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "unimplemented",
+		    VERBOSITY_ERROR, "vector=0x%03x pc=0x%08x",
+			vector,
+			(int)cpu->pc);
+		for (int j = 0; j < cpu->machine->ncpus; ++j)
+			cpu->machine->cpus[j]->running = false;
+		m88k_pc_to_pointers(cpu);
+		return;
+	}
+
+	/*  Stuff common for all exceptions:  */
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFRZ) {
+		/*
+		 *  Non-trap exceptions when the shadow freeze bit is already
+		 *  set result in an Error exception:
+		 */
+		if (!is_trap) {
+			vector = M88K_EXCEPTION_ERROR;
+			fatal("[ SFRZ already set in PSR => ERROR ]\n");
+		}
+
+		update_shadow_regs = false;
+	} else {
+		/*  Freeze shadow registers, and save the PSR:  */
+		cpu->cd.m88k.cr[M88K_CR_EPSR] = cpu->cd.m88k.cr[M88K_CR_PSR];
+	}
+
+	m88k_stcr(cpu, cpu->cd.m88k.cr[M88K_CR_PSR]
+	    | M88K_PSR_SFRZ	/*  Freeze shadow registers,          */
+	    | M88K_PSR_IND	/*  disable interrupts,               */
+	    | M88K_PSR_SFD1	/*  disable the floating point unit,  */
+	    | M88K_PSR_MODE,	/*  and switch to supervisor mode.    */
+	    M88K_CR_PSR, 0);
+
+	if (update_shadow_regs) {
+		cpu->cd.m88k.cr[M88K_CR_SSBR] = 0;
+
+		cpu->cd.m88k.cr[M88K_CR_SXIP] = cpu->pc | M88K_XIP_V;
+
+		/*  SNIP is the address to return to, when executing rte:  */
+		if (cpu->delay_slot) {
+			if (vector == M88K_EXCEPTION_DATA_ACCESS) {
+				cpu->cd.m88k.cr[M88K_CR_SNIP] = cpu->cd.m88k.delay_target | M88K_NIP_V;
+				cpu->cd.m88k.cr[M88K_CR_SFIP] = cpu->cd.m88k.cr[M88K_CR_SNIP]+4;
+			} else if (vector == M88K_EXCEPTION_INSTRUCTION_ACCESS) {
+				/*  If we are in a delay slot, then pc is
+				    something like 0xc6000 here (not 0xc5ffc).  */
+				cpu->cd.m88k.cr[M88K_CR_SNIP] = cpu->cd.m88k.delay_target | M88K_NIP_V;
+				cpu->cd.m88k.cr[M88K_CR_SFIP] = 0;
+			} else {
+				/*  Perhaps something like this could work:  */
+				cpu->cd.m88k.cr[M88K_CR_SNIP] = (cpu->pc + 4) | M88K_NIP_V;
+				cpu->cd.m88k.cr[M88K_CR_SFIP] = cpu->cd.m88k.delay_target | M88K_NIP_V;
+			}
+		} else {
+			cpu->cd.m88k.cr[M88K_CR_SNIP] = (cpu->pc + 4) | M88K_NIP_V;
+			cpu->cd.m88k.cr[M88K_CR_SFIP] = cpu->cd.m88k.cr[M88K_CR_SNIP]+4;
+		}
+
+		if (vector == M88K_EXCEPTION_INSTRUCTION_ACCESS)
+			cpu->cd.m88k.cr[M88K_CR_SXIP] |= M88K_XIP_E;
+	}
+
+	cpu->pc = cpu->cd.m88k.cr[M88K_CR_VBR] + 8 * vector;
+
+	if (cpu->delay_slot)
+		cpu->delay_slot = EXCEPTION_IN_DELAY_SLOT;
+	else
+		cpu->delay_slot = NOT_DELAYED;
+
+	/*  Default to no memory transactions:  */
+	cpu->cd.m88k.cr[M88K_CR_DMT0] = 0;
+	cpu->cd.m88k.cr[M88K_CR_DMD0] = 0;
+	cpu->cd.m88k.cr[M88K_CR_DMA0] = 0;
+	cpu->cd.m88k.cr[M88K_CR_DMT1] = 0;
+	cpu->cd.m88k.cr[M88K_CR_DMD1] = 0;
+	cpu->cd.m88k.cr[M88K_CR_DMA1] = 0;
+	cpu->cd.m88k.cr[M88K_CR_DMT2] = 0;
+	cpu->cd.m88k.cr[M88K_CR_DMD2] = 0;
+	cpu->cd.m88k.cr[M88K_CR_DMA2] = 0;
+
+	/*  Vector-specific handling:  */
+	if (vector < M88K_EXCEPTION_USER_TRAPS_START) {
+		switch (vector) {
+
+		case M88K_EXCEPTION_RESET:
+			fatal("[ m88k_exception: reset ]\n");
+			for (int j = 0; j < cpu->machine->ncpus; ++j)
+				cpu->machine->cpus[j]->running = false;
+			break;
+
+		case M88K_EXCEPTION_INTERRUPT:
+			/*  When returning with rte, we want to re-  */
+			/*  execute the interrupted instruction:  */
+			cpu->cd.m88k.cr[M88K_CR_SNIP] -= 4;
+			cpu->cd.m88k.cr[M88K_CR_SFIP] -= 4;
+			break;
+
+		case M88K_EXCEPTION_INSTRUCTION_ACCESS:
+			/*  When returning with rte, we want to re-  */
+			/*  execute the instruction in SXIP, not SNIP/SFIP,  */
+			/*  (unless the exception was in a delay-slot):  */
+			if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+				cpu->cd.m88k.cr[M88K_CR_SNIP] = 0;
+				cpu->cd.m88k.cr[M88K_CR_SFIP] = 0;
+			}
+			break;
+
+		case M88K_EXCEPTION_DATA_ACCESS:
+			/*  Update the memory transaction registers:  */
+			cpu->cd.m88k.cr[M88K_CR_DMT0] = cpu->cd.m88k.dmt[0];
+			cpu->cd.m88k.cr[M88K_CR_DMD0] = cpu->cd.m88k.dmd[0];
+			cpu->cd.m88k.cr[M88K_CR_DMA0] = cpu->cd.m88k.dma[0];
+			cpu->cd.m88k.cr[M88K_CR_DMT1] = cpu->cd.m88k.dmt[1];
+			cpu->cd.m88k.cr[M88K_CR_DMD1] = cpu->cd.m88k.dmd[1];
+			cpu->cd.m88k.cr[M88K_CR_DMA1] = cpu->cd.m88k.dma[1];
+			cpu->cd.m88k.cr[M88K_CR_DMT2] = 0;
+			cpu->cd.m88k.cr[M88K_CR_DMD2] = 0;
+			cpu->cd.m88k.cr[M88K_CR_DMA2] = 0;
+			m88k_memory_transaction_debug_dump(cpu, 0);
+			m88k_memory_transaction_debug_dump(cpu, 1);
+			break;
+
+#if 0
+		case M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE:
+			/*  TODO: Is it correct to continue on the instruction
+			    _after_ the division by zero? Or should the PC
+			    be backed up one step?  */
+			break;
+#endif
+
+#if 0
+		// TODO: Read up more about SFU1 exceptions and how the
+		// control registers look when they happen.
+		case M88K_EXCEPTION_SFU1_PRECISE:
+			cpu->cd.m88k.cr[M88K_CR_SNIP] = 0; //?
+			cpu->cd.m88k.cr[M88K_CR_SFIP] = 0;
+			//cpu->cd.m88k.cr[M88K_CR_SNIP] -= 4;
+			//cpu->cd.m88k.cr[M88K_CR_SFIP] -= 4;
+			break;
+#endif
+
+		default:debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "m88k",
+			    VERBOSITY_ERROR, "internal error");
+			cpu->running = false;
+		}
+	}
+
+	m88k_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  m88k_cpu_disassemble_instr():
+ *
+ *  Convert an instruction word into human readable format, for instruction
+ *  tracing.
+ *              
+ *  If running is 1, cpu->pc should be the address of the instruction.
+ *
+ *  If running is 0, things that depend on the runtime environment (eg.
+ *  register contents) will not be shown, and dumpaddr will be used instead of
+ *  cpu->pc for relative addresses.
+ */                     
+int m88k_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
+        int running, uint64_t dumpaddr)
+{
+	int supervisor = cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE;
+	uint32_t iw;
+	const char *symbol, *mnem = NULL;
+	uint64_t offset;
+	uint32_t op26, op10, op11, d, s1, s2, w5, cr6, imm16;
+	int32_t d16, d26;
+
+	if (running)
+		dumpaddr = cpu->pc;
+
+	symbol = get_symbol_name(&cpu->machine->symbol_context,
+	    dumpaddr, &offset);
+	if (symbol != NULL && offset == 0 && supervisor)
+		debug("<%s>\n", symbol);
+
+	if (cpu->machine->ncpus > 1 && running)
+		debug("cpu%i:\t", cpu->cpu_id);
+
+	debug("%c%08" PRIx32": ",
+	    cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE? 's' : 'u',
+	    (uint32_t) dumpaddr);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
+	else
+		iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);
+
+	debug("%08" PRIx32, (uint32_t) iw);
+
+	if (running && cpu->delay_slot)
+		debug(" (d)");
+	else
+		debug("    ");
+
+	cpu_print_pc_indicator_in_disassembly(cpu, running, dumpaddr);
+
+	op26   = (iw >> 26) & 0x3f;
+	op11   = (iw >> 11) & 0x1f;
+	op10   = (iw >> 10) & 0x3f;
+	d      = (iw >> 21) & 0x1f;
+	s1     = (iw >> 16) & 0x1f;
+	s2     =  iw        & 0x1f;
+	imm16  = iw & 0xffff;
+	w5     = (iw >>  5) & 0x1f;
+	cr6    = (iw >>  5) & 0x3f;
+	d16    = ((int16_t) (iw & 0xffff)) * 4;
+	d26    = ((int32_t)((iw & 0x03ffffff) << 6)) >> 4;
+
+	switch (op26) {
+
+	case 0x00:	/*  xmem.bu  */
+	case 0x01:	/*  xmem     */
+	case 0x02:	/*  ld.hu    */
+	case 0x03:	/*  ld.bu    */
+	case 0x04:	/*  ld.d     */
+	case 0x05:	/*  ld       */
+	case 0x06:	/*  ld.h     */
+	case 0x07:	/*  ld.b     */
+	case 0x08:	/*  st.d     */
+	case 0x09:	/*  st       */
+	case 0x0a:	/*  st.h     */
+	case 0x0b:	/*  st.b     */
+		if (iw == 0x00000000) {
+			debug("-\n");
+			break;
+		}
+		switch (op26) {
+		case 0x00:  debug("xmem.bu"); break;
+		case 0x01:  debug("xmem"); break;
+		case 0x02:  debug("ld.hu"); break;
+		case 0x03:  debug("ld.bu"); break;
+		default:    debug("%s%s", op26 >= 0x08? "st" : "ld",
+				memop[op26 & 3]);
+		}
+		debug("\tr%i,r%i,0x%x", d, s1, imm16);
+		if (running) {
+			uint32_t tmpaddr = cpu->cd.m88k.r[s1] + imm16;
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    tmpaddr, &offset);
+			if (symbol != NULL && supervisor)
+				debug("\t; [<%s>]", symbol);
+			else
+				debug("\t; [0x%08" PRIx32"]", tmpaddr);
+			if (op26 >= 0x08) {
+				/*  Store:  */
+				debug(" = ");
+				switch (op26 & 3) {
+				case 0:	debug("0x%016" PRIx64, (uint64_t)
+					    ((((uint64_t) cpu->cd.m88k.r[d])
+					    << 32) + ((uint64_t)
+					    cpu->cd.m88k.r[d+1])) );
+					break;
+				case 1:	debug("0x%08" PRIx32,
+					    (uint32_t) cpu->cd.m88k.r[d]);
+					break;
+				case 2:	debug("0x%04" PRIx16,
+					    (uint16_t) cpu->cd.m88k.r[d]);
+					break;
+				case 3:	debug("0x%02" PRIx8,
+					    (uint8_t) cpu->cd.m88k.r[d]);
+					break;
+				}
+			} else {
+				/*  Load:  */
+				/*  TODO  */
+			}
+		} else {
+			/*
+			 *  Not running, but the following instruction
+			 *  sequence is quite common:
+			 *
+			 *  or.u      rX,r0,A
+			 *  st_or_ld  rY,rX,B
+			 */
+
+			/*  Try loading the instruction before the
+			    current one.  */
+			uint32_t iw2 = 0;
+			cpu->memory_rw(cpu, cpu->mem,
+			    dumpaddr - sizeof(uint32_t), (unsigned char *)&iw2,
+			    sizeof(iw2), MEM_READ, CACHE_INSTRUCTION
+			    | NO_EXCEPTIONS);
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+				 iw2 = LE32_TO_HOST(iw2);
+			else
+				 iw2 = BE32_TO_HOST(iw2);
+			if ((iw2 >> 26) == 0x17 &&	/*  or.u  */
+			    ((iw2 >> 21) & 0x1f) == s1) {
+				uint32_t tmpaddr = (iw2 << 16) + imm16;
+				symbol = get_symbol_name(
+				    &cpu->machine->symbol_context,
+				    tmpaddr, &offset);
+				if (symbol != NULL && supervisor)
+					debug("\t; [<%s>]", symbol);
+				else
+					debug("\t; [0x%08" PRIx32"]", tmpaddr);
+			}
+		}
+		debug("\n");
+		break;
+
+	case 0x10:	/*  and     */
+	case 0x11:	/*  and.u   */
+	case 0x12:	/*  mask    */
+	case 0x13:	/*  mask.u  */
+	case 0x14:	/*  xor     */
+	case 0x15:	/*  xor.u   */
+	case 0x16:	/*  or      */
+	case 0x17:	/*  or.u    */
+		if (d == M88K_ZERO_REG)
+			debug("nop");
+
+		switch (op26) {
+		case 0x10:
+		case 0x11:	mnem = "and"; break;
+		case 0x12:
+		case 0x13:	mnem = "mask"; break;
+		case 0x14:
+		case 0x15:	mnem = "xor"; break;
+		case 0x16:
+		case 0x17:	mnem = "or"; break;
+		}
+
+		if (d != M88K_ZERO_REG || op26 != 0x16 || s1 != M88K_ZERO_REG) {
+			if (d == M88K_ZERO_REG)
+				debug("\t\t; weird nop encoding: ");
+			debug("%s%s\t", mnem, op26 & 1? ".u" : "");
+			debug("r%i,r%i,0x%x", d, s1, imm16);
+		}
+
+		if (op26 == 0x16 && d != M88K_ZERO_REG) {
+			/*
+			 *  The following instruction sequence is common:
+			 *
+			 *  or.u   rX,r0,A
+			 *  or     rY,rX,B	; rY = AAAABBBB
+			 */
+
+			/*  Try loading the instruction before the
+			    current one.  */
+			uint32_t iw2 = 0;
+			cpu->memory_rw(cpu, cpu->mem,
+			    dumpaddr - sizeof(uint32_t), (unsigned char *)&iw2,
+			    sizeof(iw2), MEM_READ, CACHE_INSTRUCTION
+			    | NO_EXCEPTIONS);
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+				 iw2 = LE32_TO_HOST(iw2);
+			else
+				 iw2 = BE32_TO_HOST(iw2);
+			if ((iw2 >> 26) == 0x17 &&	/*  or.u  */
+			    ((iw2 >> 21) & 0x1f) == s1) {
+				uint32_t tmpaddr = (iw2 << 16) + imm16;
+				symbol = get_symbol_name(
+				    &cpu->machine->symbol_context,
+				    tmpaddr, &offset);
+				debug("\t; ");
+				if (symbol != NULL && supervisor)
+					debug("<%s>", symbol);
+				else
+					debug("0x%08" PRIx32, tmpaddr);
+			}
+		}
+
+		debug("\n");
+		break;
+
+	case 0x18:	/*  addu    */
+	case 0x19:	/*  subu    */
+	case 0x1a:	/*  divu    */
+	case 0x1b:	/*  mulu    */
+	case 0x1c:	/*  add    */
+	case 0x1d:	/*  sub    */
+	case 0x1e:	/*  div    */
+	case 0x1f:	/*  cmp    */
+		switch (op26) {
+		case 0x18:	mnem = "addu"; break;
+		case 0x19:	mnem = "subu"; break;
+		case 0x1a:	mnem = "divu"; break;
+		case 0x1b:	mnem = "mulu"; break;
+		case 0x1c:	mnem = "add"; break;
+		case 0x1d:	mnem = "sub"; break;
+		case 0x1e:	mnem = "div"; break;
+		case 0x1f:	mnem = "cmp"; break;
+		}
+		debug("%s\tr%i,r%i,%i\n", mnem, d, s1, imm16);
+		break;
+
+	case 0x20:
+		if ((iw & 0x001ff81f) == 0x00004000) {
+			debug("ldcr\tr%i,%s", d, m88k_cr_name(cpu, cr6));
+			if (running)
+				debug("\t\t; %s = 0x%08x", m88k_cr_name(cpu, cr6), cpu->cd.m88k.cr[cr6]);
+			debug("\n");
+		} else if ((iw & 0x001ff81f) == 0x00004800) {
+			debug("fldcr\tr%i,%s\n", d, m88k_fcr_name(cpu, cr6));
+		} else if ((iw & 0x03e0f800) == 0x00008000) {
+			debug("stcr\tr%i,%s", s1, m88k_cr_name(cpu, cr6));
+			if (s1 != s2)
+				debug("\t\t; NOTE: weird encoding: "
+				    "low 5 bits = 0x%02x", s2);
+			if (running)
+				debug("\t\t; r%i = 0x%08x", s1, cpu->cd.m88k.r[s1]);
+			debug("\n");
+		} else if ((iw & 0x03e0f800) == 0x00008800) {
+			debug("fstcr\tr%i,%s", s1,
+			    m88k_fcr_name(cpu, cr6));
+			if (s1 != s2)
+				debug("\t\t; NOTE: weird encoding: "
+				    "low 5 bits = 0x%02x", s2);
+			debug("\n");
+		} else if ((iw & 0x0000f800) == 0x0000c000) {
+			debug("xcr\tr%i,r%i,%s", d, s1,
+			    m88k_cr_name(cpu, cr6));
+			if (s1 != s2)
+				debug("\t\t; NOTE: weird encoding: "
+				    "low 5 bits = 0x%02x", s2);
+			debug("\n");
+		} else if ((iw & 0x0000f800) == 0x0000c800) {
+			debug("fxcr\tr%i,r%i,%s", d, s1,
+			    m88k_fcr_name(cpu, cr6));
+			if (s1 != s2)
+				debug("\t\t; NOTE: weird encoding: "
+				    "low 5 bits = 0x%02x", s2);
+			debug("\n");
+		} else {
+			debug("UNIMPLEMENTED 0x20\n");
+		}
+		break;
+
+	case 0x21:
+		switch (op11) {
+		case 0x00:	/*  fmul  */
+		case 0x05:	/*  fadd  */
+		case 0x06:	/*  fsub  */
+		case 0x07:	/*  fcmp  */
+		case 0x0e:	/*  fdiv  */
+			switch (op11) {
+			case 0x00: mnem = "fmul"; break;
+			case 0x05: mnem = "fadd"; break;
+			case 0x06: mnem = "fsub"; break;
+			case 0x07: mnem = "fcmp"; break;
+			case 0x0e: mnem = "fdiv"; break;
+			}
+			debug("%s.%c%c%c r%i,r%i,r%i\n",
+			    mnem,
+			    ((iw >> 5) & 1)? 'd' : 's',
+			    ((iw >> 9) & 1)? 'd' : 's',
+			    ((iw >> 7) & 1)? 'd' : 's',
+			    d, s1, s2);
+			break;
+		case 0x04:	/*  flt  */
+			switch (op11) {
+			case 0x04: mnem = "flt"; break;
+			}
+			debug("%s.%cs\tr%i,r%i\n",
+			    mnem,
+			    ((iw >> 5) & 1)? 'd' : 's',
+			    d, s2);
+			break;
+		case 0x09:	/*  int  */
+		case 0x0a:	/*  nint  */
+		case 0x0b:	/*  trnc  */
+			switch (op11) {
+			case 0x09: mnem = "int"; break;
+			case 0x0a: mnem = "nint"; break;
+			case 0x0b: mnem = "trnc"; break;
+			}
+			debug("%s.s%c r%i,r%i\n",
+			    mnem,
+			    ((iw >> 7) & 1)? 'd' : 's',
+			    d, s2);
+			break;
+		default:debug("UNIMPLEMENTED 0x21, op11=0x%02x\n", op11);
+		}
+		break;
+
+	case 0x30:
+	case 0x31:
+	case 0x32:
+	case 0x33:
+		debug("b%sr%s\t",
+		    op26 >= 0x32? "s" : "",
+		    op26 & 1? ".n" : "");
+		debug("0x%08" PRIx32, (uint32_t) (dumpaddr + d26));
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    dumpaddr + d26, &offset);
+		if (symbol != NULL && supervisor)
+			debug("\t; <%s>", symbol);
+		debug("\n");
+		break;
+
+	case 0x34:	/*  bb0    */
+	case 0x35:	/*  bb0.n  */
+	case 0x36:	/*  bb1    */
+	case 0x37:	/*  bb1.n  */
+	case 0x3a:	/*  bcnd    */
+	case 0x3b:	/*  bcnd.n  */
+		switch (op26) {
+		case 0x34:
+		case 0x35: mnem = "bb0"; break;
+		case 0x36:
+		case 0x37: mnem = "bb1"; break;
+		case 0x3a:
+		case 0x3b: mnem = "bcnd"; break;
+		}
+		debug("%s%s\t", mnem, op26 & 1? ".n" : "");
+		if (op26 == 0x3a || op26 == 0x3b) {
+			/*  Attempt to decode bcnd condition:  */
+			switch (d) {
+			case 0x1: debug("gt0"); break;
+			case 0x2: debug("eq0"); break;
+			case 0x3: debug("ge0"); break;
+			case 0x5: debug("not_maxneg_nor_zero"); break;
+			case 0x7: debug("not_maxneg"); break;
+			case 0x8: debug("maxneg"); break;
+			case 0xc: debug("lt0"); break;
+			case 0xd: debug("ne0"); break;
+			case 0xe: debug("le0"); break;
+			default:  debug("unimplemented_%i", d);
+			}
+		} else {
+			debug("%i", d);
+		}
+		debug(",r%i,0x%08" PRIx32, s1, (uint32_t) (dumpaddr + d16));
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    dumpaddr + d16, &offset);
+		if (symbol != NULL && supervisor)
+			debug("\t; <%s>", symbol);
+		debug("\n");
+		break;
+
+	case 0x3c:
+		if ((iw & 0x0000f000)==0x1000 || (iw & 0x0000f000)==0x2000) {
+			int scale = 0;
+
+			/*  Load/store:  */
+			debug("%s", (iw & 0x0000f000) == 0x1000? "ld" : "st");
+			switch (iw & 0x00000c00) {
+			case 0x000: scale = 8; debug(".d"); break;
+			case 0x400: scale = 4; break;
+			case 0x800: debug(".x"); break;
+			default: debug(".UNIMPLEMENTED");
+			}
+			if (iw & 0x100)
+				debug(".usr");
+			if (iw & 0x80)
+				debug(".wt");
+			debug("\tr%i,r%i", d, s1);
+			if (iw & 0x200)
+				debug("[r%i]", s2);
+			else
+				debug(",r%i", s2);
+
+			if (running && scale >= 1) {
+				uint32_t tmpaddr = cpu->cd.m88k.r[s1];
+				if (iw & 0x200)
+					tmpaddr += scale * cpu->cd.m88k.r[s2];
+				else
+					tmpaddr += cpu->cd.m88k.r[s2];
+				symbol = get_symbol_name(&cpu->machine->
+				    symbol_context, tmpaddr, &offset);
+				if (symbol != NULL && supervisor)
+					debug("\t; [<%s>]", symbol);
+				else
+					debug("\t; [0x%08" PRIx32"]", tmpaddr);
+			}
+
+			debug("\n");
+		} else switch (op10) {
+		case 0x20:	/*  clr  */
+		case 0x22:	/*  set  */
+		case 0x24:	/*  ext  */
+		case 0x26:	/*  extu  */
+		case 0x28:	/*  mak  */
+		case 0x2a:	/*  rot  */
+			switch (op10) {
+			case 0x20: mnem = "clr"; break;
+			case 0x22: mnem = "set"; break;
+			case 0x24: mnem = "ext"; break;
+			case 0x26: mnem = "extu"; break;
+			case 0x28: mnem = "mak"; break;
+			case 0x2a: mnem = "rot"; break;
+			}
+			debug("%s\tr%i,r%i,", mnem, d, s1);
+			/*  Don't include w5 for the rot instruction:  */
+			if (op10 != 0x2a)
+				debug("%i", w5);
+			/*  Note: o5 = s2:  */
+			debug("<%i>\n", s2);
+			break;
+		case 0x34:	/*  tb0  */
+		case 0x36:	/*  tb1  */
+			switch (op10) {
+			case 0x34: mnem = "tb0"; break;
+			case 0x36: mnem = "tb1"; break;
+			}
+			debug("%s\t%i,r%i,0x%x\n", mnem, d, s1, iw & 0x1ff);
+			break;
+		default:debug("UNIMPLEMENTED 0x3c, op10=0x%02x\n", op10);
+		}
+		break;
+
+	case 0x3d:
+		if ((iw & 0xf000) <= 0x3fff) {
+			int scale = 0;
+
+			/*  Load, Store, xmem, and lda:  */
+			switch (iw & 0xf000) {
+			case 0x2000: debug("st"); break;
+			case 0x3000: debug("lda"); break;
+			default:     if ((iw & 0xf800) >= 0x0800)
+					  debug("ld");
+				     else
+					  debug("xmem");
+			}
+			if ((iw & 0xf000) >= 0x1000) {
+				/*  ld, st, lda  */
+				scale = 1 << (3 - ((iw >> 10) & 3));
+				debug("%s", memop[(iw >> 10) & 3]);
+			} else if ((iw & 0xf800) == 0x0000) {
+				/*  xmem  */
+				if (iw & 0x400)
+					scale = 4;
+				else
+					debug(".bu"), scale = 1;
+			} else {
+				/*  ld  */
+				if ((iw & 0xf00) < 0xc00)
+					debug(".hu"), scale = 2;
+				else
+					debug(".bu"), scale = 1;
+			}
+			if (iw & 0x100)
+				debug(".usr");
+			if (iw & 0x80)
+				debug(".wt");
+			debug("\tr%i,r%i", d, s1);
+			if (iw & 0x200)
+				debug("[r%i]", s2);
+			else
+				debug(",r%i", s2);
+
+			if (running && scale >= 1) {
+				uint32_t tmpaddr = cpu->cd.m88k.r[s1];
+				if (iw & 0x200)
+					tmpaddr += scale * cpu->cd.m88k.r[s2];
+				else
+					tmpaddr += cpu->cd.m88k.r[s2];
+				symbol = get_symbol_name(&cpu->machine->
+				    symbol_context, tmpaddr, &offset);
+				if (symbol != NULL && supervisor)
+					debug("\t; [<%s>]", symbol);
+				else
+					debug("\t; [0x%08" PRIx32"]", tmpaddr);
+			}
+
+			debug("\n");
+		} else switch ((iw >> 8) & 0xff) {
+		case 0x40:	/*  and  */
+		case 0x44:	/*  and.c  */
+		case 0x50:	/*  xor  */
+		case 0x54:	/*  xor.c  */
+		case 0x58:	/*  or  */
+		case 0x5c:	/*  or.c  */
+		case 0x60:	/*  addu  */
+		case 0x61:	/*  addu.co  */
+		case 0x62:	/*  addu.ci  */
+		case 0x63:	/*  addu.cio  */
+		case 0x64:	/*  subu  */
+		case 0x65:	/*  subu.co  */
+		case 0x66:	/*  subu.ci  */
+		case 0x67:	/*  subu.cio  */
+		case 0x68:	/*  divu  */
+		case 0x69:	/*  divu.d  */
+		case 0x6c:	/*  mul  */
+		case 0x6d:	/*  mulu.d  */
+		case 0x6e:	/*  muls  */
+		case 0x70:	/*  add  */
+		case 0x71:	/*  add.co  */
+		case 0x72:	/*  add.ci  */
+		case 0x73:	/*  add.cio  */
+		case 0x74:	/*  sub  */
+		case 0x75:	/*  sub.co  */
+		case 0x76:	/*  sub.ci  */
+		case 0x77:	/*  sub.cio  */
+		case 0x78:	/*  div  */
+		case 0x7c:	/*  cmp  */
+		case 0x80:	/*  clr  */
+		case 0x88:	/*  set  */
+		case 0x90:	/*  ext  */
+		case 0x98:	/*  extu  */
+		case 0xa0:	/*  mak  */
+		case 0xa8:	/*  rot  */
+			/*  Three-register opcodes:  */
+			switch ((iw >> 8) & 0xff) {
+			case 0x40: mnem = "and"; break;
+			case 0x44: mnem = "and.c"; break;
+			case 0x50: mnem = "xor"; break;
+			case 0x54: mnem = "xor.c"; break;
+			case 0x58: mnem = "or"; break;
+			case 0x5c: mnem = "or.c"; break;
+			case 0x60: mnem = "addu"; break;
+			case 0x61: mnem = "addu.co"; break;
+			case 0x62: mnem = "addu.ci"; break;
+			case 0x63: mnem = "addu.cio"; break;
+			case 0x64: mnem = "subu"; break;
+			case 0x65: mnem = "subu.co"; break;
+			case 0x66: mnem = "subu.ci"; break;
+			case 0x67: mnem = "subu.cio"; break;
+			case 0x68: mnem = "divu"; break;
+			case 0x69: mnem = "divu.d"; break;
+			case 0x6c: mnem = "mul"; break;
+			case 0x6d: mnem = "mulu.d"; break;
+			case 0x6e: mnem = "muls"; break;
+			case 0x70: mnem = "add"; break;
+			case 0x71: mnem = "add.co"; break;
+			case 0x72: mnem = "add.ci"; break;
+			case 0x73: mnem = "add.cio"; break;
+			case 0x74: mnem = "sub"; break;
+			case 0x75: mnem = "sub.co"; break;
+			case 0x76: mnem = "sub.ci"; break;
+			case 0x77: mnem = "sub.cio"; break;
+			case 0x78: mnem = "div"; break;
+			case 0x7c: mnem = "cmp"; break;
+			case 0x80: mnem = "clr"; break;
+			case 0x88: mnem = "set"; break;
+			case 0x90: mnem = "ext"; break;
+			case 0x98: mnem = "extu"; break;
+			case 0xa0: mnem = "mak"; break;
+			case 0xa8: mnem = "rot"; break;
+			}
+
+			if (((iw >> 8) & 0xff) == 0x58 && d == M88K_ZERO_REG)
+				debug("nop");
+
+			if (((iw >> 8) & 0xff) != 0x58 || d != M88K_ZERO_REG) {
+				if (d == M88K_ZERO_REG)
+					debug("\t\t; weird nop encoding: ");
+				debug("%s\tr%i,r%i,r%i", mnem, d, s1, s2);
+			}
+
+			debug("\n");
+			break;
+		case 0xc0:	/*  jmp  */
+		case 0xc4:	/*  jmp.n  */
+		case 0xc8:	/*  jsr  */
+		case 0xcc:	/*  jsr.n  */
+			debug("%s%s\t(r%i)",
+			    op11 & 1? "jsr" : "jmp",
+			    iw & 0x400? ".n" : "",
+			    s2);
+			if (running) {
+				uint32_t tmpaddr = cpu->cd.m88k.r[s2];
+				symbol = get_symbol_name(&cpu->machine->
+				    symbol_context, tmpaddr, &offset);
+				debug("\t\t; ");
+				if (symbol != NULL && supervisor)
+					debug("<%s>", symbol);
+				else
+					debug("0x%08" PRIx32, tmpaddr);
+			}
+			debug("\n");
+			break;
+		case 0xe8:	/*  ff1  */
+		case 0xec:	/*  ff0  */
+			debug("%s\tr%i,r%i\n",
+			    ((iw >> 8) & 0xff) == 0xe8 ? "ff1" : "ff0", d, s2);
+			break;
+		case 0xf8:	/*  tbnd  */
+			debug("tbnd\tr%i,r%i\n", s1, s2);
+			break;
+		case 0xfc:
+			switch (iw & 0xff) {
+			case 0x00:
+				debug("rte\n");
+				break;
+			case 0x01:
+			case 0x02:
+			case 0x03:
+				debug("illop%i\n", iw & 0xff);
+				break;
+			case (M88K_PROM_INSTR & 0xff):
+				debug("gxemul_prom_call\n");
+				break;
+			default:debug("UNIMPLEMENTED 0x3d,0xfc: 0x%02x\n",
+				    iw & 0xff);
+			}
+			break;
+		default:debug("UNIMPLEMENTED 0x3d, opbyte = 0x%02x\n",
+			    (iw >> 8) & 0xff);
+		}
+		break;
+
+	case 0x3e:
+		debug("tbnd\tr%i,0x%x\n", s1, imm16);
+		break;
+
+	default:debug("UNIMPLEMENTED op26=0x%02x\n", op26);
+	}
+
+	return sizeof(uint32_t);
+}
+
+
+#include "tmp_m88k_tail.c"
+
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_m88k.cc gxemul-0.7.0+dfsg/src/cpus/cpu_m88k.cc
--- gxemul-0.6.2/src/cpus/cpu_m88k.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_m88k.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1481 +0,0 @@
-/*
- *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Motorola M881x0 CPU emulation.
- *
- *  M88100: Disassembly of (almost?) everything, and execution of most
- *          instructions. Exception handling and virtual memory has also
- *          been implemented. Exceptions while in delay slots may not work
- *          fully yet, though.
- *
- *  M88110: Not yet. 
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <ctype.h>
-#include <unistd.h>
-
-#include "cpu.h"
-#include "float_emul.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "settings.h"
-#include "symbol.h"
-
-#include "thirdparty/m8820x_pte.h"
-#include "thirdparty/m88k_dmt.h"
-#include "thirdparty/mvmeprom.h"
-
-#define DYNTRANS_32
-#define DYNTRANS_DELAYSLOT
-#include "tmp_m88k_head.cc"
-
-
-void m88k_pc_to_pointers(struct cpu *);
-void m88k_cpu_functioncall_trace(struct cpu *cpu, int n_args);
-
-static const char *memop[4] = { ".d", "", ".h", ".b" };
-
-void m88k_irq_interrupt_assert(struct interrupt *interrupt);
-void m88k_irq_interrupt_deassert(struct interrupt *interrupt);
-
-
-static const char *m88k_cr_names[] = M88K_CR_NAMES;
-static const char *m88k_cr_197_names[] = M88K_CR_NAMES_197;
-
-static const char *m88k_cr_name(struct cpu *cpu, int i)
-{
-	const char **cr_names = m88k_cr_names;
-
-	/*  Hm. Is this really MVME197 specific? TODO  */
-	if (cpu->machine->machine_subtype == MACHINE_MVME88K_197)
-		cr_names = m88k_cr_197_names;
-
-	return cr_names[i];
-}
-
-static char *m88k_fcr_name(struct cpu *cpu, int fi)
-{
-	/*  TODO  */
-	static char fcr_name[10];
-	snprintf(fcr_name, sizeof(fcr_name), "FCR%i", fi);
-	return fcr_name;
-}
-
-
-
-/*
- *  m88k_cpu_new():
- *
- *  Create a new M88K cpu object by filling the CPU struct.
- *  Return 1 on success, 0 if cpu_type_name isn't a valid M88K processor.
- */
-int m88k_cpu_new(struct cpu *cpu, struct memory *mem,
-	struct machine *machine, int cpu_id, char *cpu_type_name)
-{
-	int i, found;
-	struct m88k_cpu_type_def cpu_type_defs[] = M88K_CPU_TYPE_DEFS;
-
-	/*  Scan the list for this cpu type:  */
-	i = 0; found = -1;
-	while (i >= 0 && cpu_type_defs[i].name != NULL) {
-		if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
-			found = i;
-			break;
-		}
-		i++;
-	}
-	if (found == -1)
-		return 0;
-
-	cpu->run_instr = m88k_run_instr;
-	cpu->memory_rw = m88k_memory_rw;
-	cpu->update_translation_table = m88k_update_translation_table;
-	cpu->invalidate_translation_caches =
-	    m88k_invalidate_translation_caches;
-	cpu->invalidate_code_translation = m88k_invalidate_code_translation;
-	cpu->translate_v2p = m88k_translate_v2p;
-
-	cpu->cd.m88k.cpu_type = cpu_type_defs[found];
-	cpu->name            = strdup(cpu->cd.m88k.cpu_type.name);
-	cpu->is_32bit        = 1;
-	cpu->byte_order      = EMUL_BIG_ENDIAN;
-
-	cpu->instruction_has_delayslot = m88k_cpu_instruction_has_delayslot;
-
-	/*  Only show name and caches etc for CPU nr 0:  */
-	if (cpu_id == 0) {
-		debug("%s", cpu->name);
-	}
-
-
-	/*
-	 *  Add register names as settings:
-	 */
-
-	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
-
-	for (i=0; i<N_M88K_REGS; i++) {
-		char name[10];
-		snprintf(name, sizeof(name), "r%i", i);
-		CPU_SETTINGS_ADD_REGISTER32(name, cpu->cd.m88k.r[i]);
-	}
-
-	for (i=0; i<N_M88K_CONTROL_REGS; i++) {
-		char name[10];
-		snprintf(name, sizeof(name), "%s", m88k_cr_name(cpu, i));
-		CPU_SETTINGS_ADD_REGISTER32(name, cpu->cd.m88k.cr[i]);
-	}
-
-	for (i=0; i<N_M88K_FPU_CONTROL_REGS; i++) {
-		char name[10];
-		snprintf(name, sizeof(name), "%s", m88k_fcr_name(cpu, i));
-		CPU_SETTINGS_ADD_REGISTER32(name, cpu->cd.m88k.fcr[i]);
-	}
-
-
-	/*  Register the CPU interrupt pin:  */
-	{
-		struct interrupt templ;
-		char name[50];
-		snprintf(name, sizeof(name), "%s", cpu->path);
-
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 0;
-		templ.name = name;
-		templ.extra = cpu;
-		templ.interrupt_assert = m88k_irq_interrupt_assert;
-		templ.interrupt_deassert = m88k_irq_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	/*  Set the Processor ID:  */
-	cpu->cd.m88k.cr[M88K_CR_PID] = cpu->cd.m88k.cpu_type.pid | M88K_PID_MC;
-
-	/*  Start in supervisor mode, with interrupts disabled.  */
-	cpu->cd.m88k.cr[M88K_CR_PSR] = M88K_PSR_MODE | M88K_PSR_IND;
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		cpu->cd.m88k.cr[M88K_CR_PSR] |= M88K_PSR_BO;
-
-	/*  Initial stack pointer:  */
-	cpu->cd.m88k.r[31] = 1048576 * cpu->machine->physical_ram_in_mb - 1024;
-
-	return 1;
-}
-
-
-/*
- *  m88k_cpu_dumpinfo():
- */
-void m88k_cpu_dumpinfo(struct cpu *cpu)
-{
-	/*  struct m88k_cpu_type_def *ct = &cpu->cd.m88k.cpu_type;  */
-
-	debug(", %s-endian",
-	    cpu->byte_order == EMUL_BIG_ENDIAN? "Big" : "Little");
-
-	debug("\n");
-}
-
-
-/*
- *  m88k_cpu_list_available_types():
- *
- *  Print a list of available M88K CPU types.
- */
-void m88k_cpu_list_available_types(void)
-{
-	int i, j;
-	struct m88k_cpu_type_def tdefs[] = M88K_CPU_TYPE_DEFS;
-
-	i = 0;
-	while (tdefs[i].name != NULL) {
-		debug("%s", tdefs[i].name);
-		for (j=13 - strlen(tdefs[i].name); j>0; j--)
-			debug(" ");
-		i++;
-		if ((i % 5) == 0 || tdefs[i].name == NULL)
-			debug("\n");
-	}
-}
-
-
-/*
- *  m88k_cpu_instruction_has_delayslot():
- *
- *  Returns 1 if an opcode has a delay slot after it, 0 otherwise.
- */
-int m88k_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
-{
-	uint32_t iword = *((uint32_t *)&ib[0]);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		iword = LE32_TO_HOST(iword);
-	else
-		iword = BE32_TO_HOST(iword);
-
-	switch (iword >> 26) {
-	case 0x31:	/*  br.n  */
-	case 0x33:	/*  bsr.n  */
-	case 0x35:	/*  bb0.n  */
-	case 0x37:	/*  bb1.n  */
-	case 0x3b:	/*  bcnd.n  */
-		return 1;
-	case 0x3d:
-		switch ((iword >> 8) & 0xff) {
-		case 0xc4:	/*  jmp.n  */
-		case 0xcc:	/*  jsr.n  */
-			return 1;
-		}
-	}
-
-	return 0;
-}
-
-
-/*
- *  m88k_cpu_register_dump():
- *
- *  Dump cpu registers in a relatively readable format.
- *  
- *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
- *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
- */
-void m88k_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
-{
-	char *symbol;
-	uint64_t offset;
-	int i, x = cpu->cpu_id;
-
-	if (gprs) {
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    cpu->pc, &offset);
-		debug("cpu%i:  pc  = 0x%08" PRIx32, x, (uint32_t)cpu->pc);
-		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
-
-		for (i=0; i<N_M88K_REGS; i++) {
-			if ((i % 4) == 0)
-				debug("cpu%i:", x);
-			if (i == 0)
-				debug("                  ");
-			else
-				debug("  r%-2i = 0x%08" PRIx32,
-				    i, cpu->cd.m88k.r[i]);
-			if ((i % 4) == 3)
-				debug("\n");
-		}
-	}
-
-	if (coprocs & 1) {
-		int n_control_regs = 32;
-
-		/*  Hm. Is this really MVME197 specific? TODO  */
-		if (cpu->machine->machine_subtype == MACHINE_MVME88K_197)
-			n_control_regs = 64;
-
-		for (i=0; i<n_control_regs; i++) {
-			if ((i % 4) == 0)
-				debug("cpu%i:", x);
-			debug("  %4s=0x%08" PRIx32,
-			    m88k_cr_name(cpu, i), cpu->cd.m88k.cr[i]);
-			if ((i % 4) == 3)
-				debug("\n");
-		}
-	}
-
-	if (coprocs & 2) {
-		int n_fpu_control_regs = 64;
-
-		for (i=0; i<n_fpu_control_regs; i++) {
-			if ((i % 4) == 0)
-				debug("cpu%i:", x);
-			debug("  %5s=0x%08" PRIx32,
-			    m88k_fcr_name(cpu, i), cpu->cd.m88k.fcr[i]);
-			if ((i % 4) == 3)
-				debug("\n");
-		}
-	}
-}
-
-
-/*
- *  m88k_cpu_tlbdump():
- *
- *  Called from the debugger to dump the TLB in a readable format.
- *  x is the cpu number to dump, or -1 to dump all CPUs.
- *
- *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
- *  just dumped.
- */
-void m88k_cpu_tlbdump(struct machine *m, int x, int rawflag)
-{
-	int cpu_nr, cmmu_nr, i;
-
-	for (cpu_nr = 0; cpu_nr < m->ncpus; cpu_nr++) {
-		struct cpu *cpu = m->cpus[cpu_nr];
-
-		if (x != -1 && cpu_nr != x)
-			continue;
-
-		for (cmmu_nr = 0; cmmu_nr < MAX_M8820X_CMMUS; cmmu_nr++) {
-			struct m8820x_cmmu *cmmu = cpu->cd.m88k.cmmu[cmmu_nr];
-			if (cmmu == NULL)
-				continue;
-
-			printf("cpu%i: CMMU %i (%s)\n", cpu_nr, cmmu_nr,
-			    cmmu_nr & 1? "data" : "instruction");
-
-			/*  BATC:  */
-			for (i = 0; i < N_M88200_BATC_REGS; i++) {
-				uint32_t b = cmmu->batc[i];
-				printf("cpu%i: BATC[%2i]: ", cpu_nr, i);
-				printf("v=0x%08" PRIx32, b & 0xfff80000);
-				printf(", p=0x%08" PRIx32,
-				    (b << 13) & 0xfff80000);
-				printf(", %s %s %s %s %s %s\n",
-				    b & BATC_SO? "SP " : "!sp",
-				    b & BATC_WT? "WT " : "!wt",
-				    b & BATC_GLOBAL? "G  " : "!g ",
-				    b & BATC_INH? "CI " : "!ci",
-				    b & BATC_PROT? "WP " : "!wp",
-				    b & BATC_SO? "V " : "!v");
-			}
-
-			/*  PATC:  */
-			for (i = 0; i < N_M88200_PATC_ENTRIES; i++) {
-				uint32_t v = cmmu->patc_v_and_control[i];
-				uint32_t p = cmmu->patc_p_and_supervisorbit[i];
-
-				printf("cpu%i: patc[%2i]: ", cpu_nr, i);
-				if (p & M8820X_PATC_SUPERVISOR_BIT)
-					printf("superv");
-				else
-					printf("user  ");
-				printf(" v=0x%08" PRIx32, v & 0xfffff000);
-				printf(", p=0x%08" PRIx32, p & 0xfffff000);
-
-				printf("  %s %s %s %s %s %s %s",
-				    v & PG_U1?   "U1 " : "!u1",
-				    v & PG_U0?   "U0 " : "!u0",
-				    v & PG_SO?   "SP " : "!sp",
-				    v & PG_M?    "M "  : "!m",
-				    v & PG_U?    "U "  : "!u",
-				    v & PG_PROT? "WP " : "!wp",
-				    v & PG_V?    "V "  : "!v");
-
-				if (i == cmmu->patc_update_index)
-					printf(" <--");
-				printf("\n");
-			}
-		}
-	}
-}
-
-
-/*
- *  m88k_irq_interrupt_assert():
- *  m88k_irq_interrupt_deassert():
- */
-void m88k_irq_interrupt_assert(struct interrupt *interrupt)
-{
-	struct cpu *cpu = (struct cpu *) interrupt->extra;
-	cpu->cd.m88k.irq_asserted = 1;
-}
-void m88k_irq_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct cpu *cpu = (struct cpu *) interrupt->extra;
-	cpu->cd.m88k.irq_asserted = 0;
-}
-
-
-/*
- *  m88k_ldcr():
- *
- *  Read from a control register. Store the resulting value in a register
- *  (pointed to by r32ptr).
- */
-void m88k_ldcr(struct cpu *cpu, uint32_t *r32ptr, int cr)
-{
-	uint32_t retval = cpu->cd.m88k.cr[cr];
-
-	switch (cr) {
-
-	case M88K_CR_PID:
-	case M88K_CR_PSR:
-	case M88K_CR_EPSR:
-	case M88K_CR_SSBR:
-	case M88K_CR_SXIP:
-	case M88K_CR_SNIP:
-	case M88K_CR_SFIP:
-	case M88K_CR_VBR:
-	case M88K_CR_DMD0:
-	case M88K_CR_DMD1:
-	case M88K_CR_DMD2:
-	case M88K_CR_SR0:
-	case M88K_CR_SR1:
-	case M88K_CR_SR2:
-	case M88K_CR_SR3:
-		break;
-
-	case M88K_CR_DMT0:
-	case M88K_CR_DMT1:
-	case M88K_CR_DMT2:
-		/*
-		 *  Catch some possible internal errors in the emulator:
-		 *
-		 *  For valid memory Load transactions, the Destination Register
-		 *  should not be zero.
-		 *
-		 *  The Byte Order bit should be the same as the CPU's.
-		 */
-		if (retval & DMT_VALID && !(retval & DMT_WRITE)) {
-			if (DMT_DREGBITS(retval) == M88K_ZERO_REG) {
-				fatal("DMT DREG = zero? Internal error.\n");
-				exit(1);
-			}
-		}
-		if (!!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_BO)
-		    != !!(retval & DMT_BO) && retval & DMT_VALID) {
-			fatal("DMT byte order not same as CPUs?\n");
-			exit(1);
-		}
-
-		break;
-
-	case M88K_CR_DMA0:
-	case M88K_CR_DMA1:
-	case M88K_CR_DMA2:
-		/*
-		 *  Catch some possible internal errors in the emulator:
-		 *  The lowest 2 bits of the transaction address registers
-		 *  should always be zero.
-		 */
-		if (retval & 3) {
-			fatal("DMAx not word-aligned? Internal error.\n");
-			exit(1);
-		}
-
-		break;
-
-	default:fatal("m88k_ldcr: UNIMPLEMENTED cr = 0x%02x (%s)\n",
-		    cr, m88k_cr_name(cpu, cr));
-		exit(1);
-	}
-
-	*r32ptr = retval;
-}
-
-
-/*
- *  m88k_stcr():
- *
- *  Write to a control register.
- *  (Used by both the stcr and rte instructions.)
- */
-void m88k_stcr(struct cpu *cpu, uint32_t value, int cr, int rte)
-{
-	uint32_t old = cpu->cd.m88k.cr[cr];
-
-	switch (cr) {
-
-	case M88K_CR_PSR:	/*  Processor Status Regoster  */
-		if ((cpu->byte_order == EMUL_LITTLE_ENDIAN
-		    && !(value & M88K_PSR_BO)) ||
-		    (cpu->byte_order == EMUL_BIG_ENDIAN
-		    && (value & M88K_PSR_BO))) {
-			fatal("TODO: attempt to change endianness by flipping"
-			    " the endianness bit in the PSR. How should this"
-			    " be handled? Aborting.\n");
-			exit(1);
-		}
-
-		if (!rte && old & M88K_PSR_MODE && !(value & M88K_PSR_MODE))
-			fatal("[ m88k_stcr: WARNING! the PSR_MODE bit is being"
-			    " cleared; this should be done using the RTE "
-			    "instruction only, according to the M88100 "
-			    "manual! Continuing anyway. ]\n");
-
-		if (value & M88K_PSR_MXM) {
-			fatal("m88k_stcr: TODO: MXM support\n");
-			exit(1);
-		}
-
-		if ((old & M88K_PSR_MODE) != (value & M88K_PSR_MODE))
-			cpu->invalidate_translation_caches(
-			    cpu, 0, INVALIDATE_ALL);
-
-		cpu->cd.m88k.cr[cr] = value;
-		break;
-
-	case M88K_CR_EPSR:
-		cpu->cd.m88k.cr[cr] = value;
-		break;
-
-	case M88K_CR_SXIP:
-	case M88K_CR_SNIP:
-	case M88K_CR_SFIP:
-		cpu->cd.m88k.cr[cr] = value;
-		break;
-
-	case M88K_CR_SSBR:	/*  Shadow ScoreBoard Register  */
-		if (value & 1)
-			fatal("[ m88k_stcr: WARNING! bit 0 non-zero when"
-			    " writing to SSBR (?) ]\n");
-		cpu->cd.m88k.cr[cr] = value;
-		break;
-
-	case M88K_CR_VBR:
-		if (value & 0x00000fff)
-			fatal("[ m88k_stcr: WARNING! bits 0..11 non-zero when"
-			    " writing to VBR (?) ]\n");
-		cpu->cd.m88k.cr[cr] = value;
-		break;
-
-	case M88K_CR_DMT0:
-	case M88K_CR_DMT1:
-	case M88K_CR_DMT2:
-		cpu->cd.m88k.cr[cr] = value;
-		break;
-
-	case M88K_CR_SR0:	/*  Supervisor Storage Registers 0..3  */
-	case M88K_CR_SR1:
-	case M88K_CR_SR2:
-	case M88K_CR_SR3:
-		cpu->cd.m88k.cr[cr] = value;
-		break;
-
-	default:fatal("m88k_stcr: UNIMPLEMENTED cr = 0x%02x (%s)\n",
-		    cr, m88k_cr_name(cpu, cr));
-		exit(1);
-	}
-}
-
-
-/*
- *  m88k_fstcr():
- *
- *  Write to a floating-point control register.
- */
-void m88k_fstcr(struct cpu *cpu, uint32_t value, int fcr)
-{
-#if 0
-	/*  TODO (?)  */
-	uint32_t old = cpu->cd.m88k.cr[fcr];
-
-	switch (fcr) {
-	default:fatal("m88k_fstcr: UNIMPLEMENTED fcr = 0x%02x (%s)\n",
-		    fcr, m88k_fcr_name(cpu, fcr));
-		exit(1);
-	}
-#else
-	cpu->cd.m88k.cr[fcr] = value;
-#endif
-}
-
-
-/*
- *  m88k_memory_transaction_debug_dump():
- *
- *  Debug dump of the memory transaction registers of a cpu.
- */
-static void m88k_memory_transaction_debug_dump(struct cpu *cpu, int n)
-{
-	uint32_t dmt = cpu->cd.m88k.dmt[n];
-
-	debug("[ DMT%i: ", n);
-	if (dmt & DMT_VALID) {
-		if (dmt & DMT_BO)
-			debug("Little-Endian, ");
-		else
-			debug("Big-Endian, ");
-		if (dmt & DMT_DAS)
-			debug("Supervisor, ");
-		else
-			debug("User, ");
-		if (dmt & DMT_DOUB1)
-			debug("DOUB1, ");
-		if (dmt & DMT_LOCKBAR)
-			debug("LOCKBAR, ");
-		if (dmt & DMT_WRITE)
-			debug("store, ");
-		else {
-			debug("load.%c(r%i), ",
-			    dmt & DMT_SIGNED? 's' : 'u',
-			    DMT_DREGBITS(dmt));
-		}
-		debug("bytebits=0x%x ]\n", DMT_ENBITS(dmt));
-
-		debug("[ DMD%i: 0x%08" PRIx32"; ", n, cpu->cd.m88k.dmd[n]);
-		debug("DMA%i: 0x%08" PRIx32" ]\n", n, cpu->cd.m88k.dma[n]);
-	} else
-		debug("not valid ]\n");
-}
-
-
-/*
- *  m88k_exception():
- *
- *  Cause an exception.
- */
-void m88k_exception(struct cpu *cpu, int vector, int is_trap)
-{
-	int update_shadow_regs = 1;
-
-	debug("[ EXCEPTION 0x%03x: ", vector);
-	switch (vector) {
-	case M88K_EXCEPTION_RESET:
-		debug("RESET"); break;
-	case M88K_EXCEPTION_INTERRUPT:
-		debug("INTERRUPT"); break;
-	case M88K_EXCEPTION_INSTRUCTION_ACCESS:
-		debug("INSTRUCTION_ACCESS"); break;
-	case M88K_EXCEPTION_DATA_ACCESS:
-		debug("DATA_ACCESS"); break;
-	case M88K_EXCEPTION_MISALIGNED_ACCESS:
-		debug("MISALIGNED_ACCESS"); break;
-	case M88K_EXCEPTION_UNIMPLEMENTED_OPCODE:
-		debug("UNIMPLEMENTED_OPCODE"); break;
-	case M88K_EXCEPTION_PRIVILEGE_VIOLATION:
-		debug("PRIVILEGE_VIOLATION"); break;
-	case M88K_EXCEPTION_BOUNDS_CHECK_VIOLATION:
-		debug("BOUNDS_CHECK_VIOLATION"); break;
-	case M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE:
-		debug("ILLEGAL_INTEGER_DIVIDE"); break;
-	case M88K_EXCEPTION_INTEGER_OVERFLOW:
-		debug("INTEGER_OVERFLOW"); break;
-	case M88K_EXCEPTION_ERROR:
-		debug("ERROR"); break;
-	case M88K_EXCEPTION_SFU1_PRECISE:
-		debug("SFU1_PRECISE"); break;
-	case M88K_EXCEPTION_SFU1_IMPRECISE:
-		debug("SFU1_IMPRECISE"); break;
-	case 0x80:	/*  up to OpenBSD 5.2  */
-	case 0x1c2:	/*  from OpenBSD 5.3 and forward...  */
-#if 0
-		fatal("[ syscall %i(", cpu->cd.m88k.r[13]);
-		m88k_cpu_functioncall_trace(cpu, 8);
-		fatal(") ]\n");
-#endif
-		debug("syscall, r13=%i", cpu->cd.m88k.r[13]); break;
-	case MVMEPROM_VECTOR:
-		debug("MVMEPROM_VECTOR"); break;
-	default:debug("unknown"); break;
-	}
-	debug(" ]\n");
-
-	/*  Stuff common for all exceptions:  */
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFRZ) {
-		/*
-		 *  Non-trap exceptions when the shadow freeze bit is already
-		 *  set result in an Error exception:
-		 */
-		if (!is_trap) {
-			vector = M88K_EXCEPTION_ERROR;
-			fatal("[ SFRZ already set in PSR => ERROR ]\n");
-		}
-
-		update_shadow_regs = 0;
-	} else {
-		/*  Freeze shadow registers, and save the PSR:  */
-		cpu->cd.m88k.cr[M88K_CR_EPSR] = cpu->cd.m88k.cr[M88K_CR_PSR];
-	}
-
-	m88k_stcr(cpu, cpu->cd.m88k.cr[M88K_CR_PSR]
-	    | M88K_PSR_SFRZ	/*  Freeze shadow registers,          */
-	    | M88K_PSR_IND	/*  disable interrupts,               */
-	    | M88K_PSR_SFD1	/*  disable the floating point unit,  */
-	    | M88K_PSR_MODE,	/*  and switch to supervisor mode.    */
-	    M88K_CR_PSR, 0);
-
-	if (update_shadow_regs) {
-		cpu->cd.m88k.cr[M88K_CR_SSBR] = 0;
-
-		cpu->cd.m88k.cr[M88K_CR_SXIP] = cpu->pc | M88K_XIP_V;
-
-		/*  SNIP is the address to return to, when executing rte:  */
-		if (cpu->delay_slot) {
-			if (vector == M88K_EXCEPTION_DATA_ACCESS) {
-				cpu->cd.m88k.cr[M88K_CR_SNIP] = cpu->cd.m88k.delay_target | M88K_NIP_V;
-				cpu->cd.m88k.cr[M88K_CR_SFIP] = cpu->cd.m88k.cr[M88K_CR_SNIP]+4;
-			} else if (vector == M88K_EXCEPTION_INSTRUCTION_ACCESS) {
-				/*  If we are in a delay slot, then pc is
-				    something like 0xc6000 here (not 0xc5ffc).  */
-				cpu->cd.m88k.cr[M88K_CR_SNIP] = cpu->cd.m88k.delay_target | M88K_NIP_V;
-				cpu->cd.m88k.cr[M88K_CR_SFIP] = 0;
-			} else {
-				/*  Perhaps something like this could work:  */
-				cpu->cd.m88k.cr[M88K_CR_SNIP] = (cpu->pc + 4) | M88K_NIP_V;
-				cpu->cd.m88k.cr[M88K_CR_SFIP] = cpu->cd.m88k.delay_target | M88K_NIP_V;
-			}
-		} else {
-			cpu->cd.m88k.cr[M88K_CR_SNIP] = (cpu->pc + 4) | M88K_NIP_V;
-			cpu->cd.m88k.cr[M88K_CR_SFIP] = cpu->cd.m88k.cr[M88K_CR_SNIP]+4;
-		}
-
-		if (vector == M88K_EXCEPTION_INSTRUCTION_ACCESS)
-			cpu->cd.m88k.cr[M88K_CR_SXIP] |= M88K_XIP_E;
-	}
-
-	cpu->pc = cpu->cd.m88k.cr[M88K_CR_VBR] + 8 * vector;
-
-	if (cpu->delay_slot)
-		cpu->delay_slot = EXCEPTION_IN_DELAY_SLOT;
-	else
-		cpu->delay_slot = NOT_DELAYED;
-
-	/*  Default to no memory transactions:  */
-	cpu->cd.m88k.cr[M88K_CR_DMT0] = 0;
-	cpu->cd.m88k.cr[M88K_CR_DMD0] = 0;
-	cpu->cd.m88k.cr[M88K_CR_DMA0] = 0;
-	cpu->cd.m88k.cr[M88K_CR_DMT1] = 0;
-	cpu->cd.m88k.cr[M88K_CR_DMD1] = 0;
-	cpu->cd.m88k.cr[M88K_CR_DMA1] = 0;
-	cpu->cd.m88k.cr[M88K_CR_DMT2] = 0;
-	cpu->cd.m88k.cr[M88K_CR_DMD2] = 0;
-	cpu->cd.m88k.cr[M88K_CR_DMA2] = 0;
-
-	/*  Vector-specific handling:  */
-	if (vector < M88K_EXCEPTION_USER_TRAPS_START) {
-		switch (vector) {
-
-		case M88K_EXCEPTION_RESET:
-			fatal("[ m88k_exception: reset ]\n");
-			exit(1);
-
-		case M88K_EXCEPTION_INTERRUPT:
-			/*  When returning with rte, we want to re-  */
-			/*  execute the interrupted instruction:  */
-			cpu->cd.m88k.cr[M88K_CR_SNIP] -= 4;
-			cpu->cd.m88k.cr[M88K_CR_SFIP] -= 4;
-			break;
-
-		case M88K_EXCEPTION_INSTRUCTION_ACCESS:
-			/*  When returning with rte, we want to re-  */
-			/*  execute the instruction in SXIP, not SNIP/SFIP,  */
-			/*  (unless the exception was in a delay-slot):  */
-			if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-				cpu->cd.m88k.cr[M88K_CR_SNIP] = 0;
-				cpu->cd.m88k.cr[M88K_CR_SFIP] = 0;
-			}
-			break;
-
-		case M88K_EXCEPTION_DATA_ACCESS:
-			/*  Update the memory transaction registers:  */
-			cpu->cd.m88k.cr[M88K_CR_DMT0] = cpu->cd.m88k.dmt[0];
-			cpu->cd.m88k.cr[M88K_CR_DMD0] = cpu->cd.m88k.dmd[0];
-			cpu->cd.m88k.cr[M88K_CR_DMA0] = cpu->cd.m88k.dma[0];
-			cpu->cd.m88k.cr[M88K_CR_DMT1] = cpu->cd.m88k.dmt[1];
-			cpu->cd.m88k.cr[M88K_CR_DMD1] = cpu->cd.m88k.dmd[1];
-			cpu->cd.m88k.cr[M88K_CR_DMA1] = cpu->cd.m88k.dma[1];
-			cpu->cd.m88k.cr[M88K_CR_DMT2] = 0;
-			cpu->cd.m88k.cr[M88K_CR_DMD2] = 0;
-			cpu->cd.m88k.cr[M88K_CR_DMA2] = 0;
-			m88k_memory_transaction_debug_dump(cpu, 0);
-			m88k_memory_transaction_debug_dump(cpu, 1);
-			break;
-
-#if 0
-		case M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE:
-			/*  TODO: Is it correct to continue on the instruction
-			    _after_ the division by zero? Or should the PC
-			    be backed up one step?  */
-			break;
-#endif
-
-		default:fatal("m88k_exception(): 0x%x: TODO\n", vector);
-			fflush(stdout);
-			exit(1);
-		}
-	}
-
-	m88k_pc_to_pointers(cpu);
-}
-
-
-/*
- *  m88k_cpu_disassemble_instr():
- *
- *  Convert an instruction word into human readable format, for instruction
- *  tracing.
- *              
- *  If running is 1, cpu->pc should be the address of the instruction.
- *
- *  If running is 0, things that depend on the runtime environment (eg.
- *  register contents) will not be shown, and dumpaddr will be used instead of
- *  cpu->pc for relative addresses.
- */                     
-int m88k_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
-        int running, uint64_t dumpaddr)
-{
-	int supervisor = cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE;
-	uint32_t iw;
-	const char *symbol, *mnem = NULL;
-	uint64_t offset;
-	uint32_t op26, op10, op11, d, s1, s2, w5, cr6, imm16;
-	int32_t d16, d26;
-
-	if (running)
-		dumpaddr = cpu->pc;
-
-	symbol = get_symbol_name(&cpu->machine->symbol_context,
-	    dumpaddr, &offset);
-	if (symbol != NULL && offset == 0 && supervisor)
-		debug("<%s>\n", symbol);
-
-	if (cpu->machine->ncpus > 1 && running)
-		debug("cpu%i:\t", cpu->cpu_id);
-
-	debug("%c%08" PRIx32": ",
-	    cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE? 's' : 'u',
-	    (uint32_t) dumpaddr);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
-	else
-		iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);
-
-	debug("%08" PRIx32, (uint32_t) iw);
-
-	if (running && cpu->delay_slot)
-		debug(" (d)");
-
-	debug("\t");
-
-	op26   = (iw >> 26) & 0x3f;
-	op11   = (iw >> 11) & 0x1f;
-	op10   = (iw >> 10) & 0x3f;
-	d      = (iw >> 21) & 0x1f;
-	s1     = (iw >> 16) & 0x1f;
-	s2     =  iw        & 0x1f;
-	imm16  = iw & 0xffff;
-	w5     = (iw >>  5) & 0x1f;
-	cr6    = (iw >>  5) & 0x3f;
-	d16    = ((int16_t) (iw & 0xffff)) * 4;
-	d26    = ((int32_t)((iw & 0x03ffffff) << 6)) >> 4;
-
-	switch (op26) {
-
-	case 0x00:	/*  xmem.bu  */
-	case 0x01:	/*  xmem     */
-	case 0x02:	/*  ld.hu    */
-	case 0x03:	/*  ld.bu    */
-	case 0x04:	/*  ld.d     */
-	case 0x05:	/*  ld       */
-	case 0x06:	/*  ld.h     */
-	case 0x07:	/*  ld.b     */
-	case 0x08:	/*  st.d     */
-	case 0x09:	/*  st       */
-	case 0x0a:	/*  st.h     */
-	case 0x0b:	/*  st.b     */
-		if (iw == 0x00000000) {
-			debug("-\n");
-			break;
-		}
-		switch (op26) {
-		case 0x00:  debug("xmem.bu"); break;
-		case 0x01:  debug("xmem"); break;
-		case 0x02:  debug("ld.hu"); break;
-		case 0x03:  debug("ld.bu"); break;
-		default:    debug("%s%s", op26 >= 0x08? "st" : "ld",
-				memop[op26 & 3]);
-		}
-		debug("\tr%i,r%i,0x%x", d, s1, imm16);
-		if (running) {
-			uint32_t tmpaddr = cpu->cd.m88k.r[s1] + imm16;
-			symbol = get_symbol_name(&cpu->machine->symbol_context,
-			    tmpaddr, &offset);
-			if (symbol != NULL && supervisor)
-				debug("\t; [<%s>]", symbol);
-			else
-				debug("\t; [0x%08" PRIx32"]", tmpaddr);
-			if (op26 >= 0x08) {
-				/*  Store:  */
-				debug(" = ");
-				switch (op26 & 3) {
-				case 0:	debug("0x%016" PRIx64, (uint64_t)
-					    ((((uint64_t) cpu->cd.m88k.r[d])
-					    << 32) + ((uint64_t)
-					    cpu->cd.m88k.r[d+1])) );
-					break;
-				case 1:	debug("0x%08" PRIx32,
-					    (uint32_t) cpu->cd.m88k.r[d]);
-					break;
-				case 2:	debug("0x%04" PRIx16,
-					    (uint16_t) cpu->cd.m88k.r[d]);
-					break;
-				case 3:	debug("0x%02" PRIx8,
-					    (uint8_t) cpu->cd.m88k.r[d]);
-					break;
-				}
-			} else {
-				/*  Load:  */
-				/*  TODO  */
-			}
-		} else {
-			/*
-			 *  Not running, but the following instruction
-			 *  sequence is quite common:
-			 *
-			 *  or.u      rX,r0,A
-			 *  st_or_ld  rY,rX,B
-			 */
-
-			/*  Try loading the instruction before the
-			    current one.  */
-			uint32_t iw2 = 0;
-			cpu->memory_rw(cpu, cpu->mem,
-			    dumpaddr - sizeof(uint32_t), (unsigned char *)&iw2,
-			    sizeof(iw2), MEM_READ, CACHE_INSTRUCTION
-			    | NO_EXCEPTIONS);
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-				 iw2 = LE32_TO_HOST(iw2);
-			else
-				 iw2 = BE32_TO_HOST(iw2);
-			if ((iw2 >> 26) == 0x17 &&	/*  or.u  */
-			    ((iw2 >> 21) & 0x1f) == s1) {
-				uint32_t tmpaddr = (iw2 << 16) + imm16;
-				symbol = get_symbol_name(
-				    &cpu->machine->symbol_context,
-				    tmpaddr, &offset);
-				if (symbol != NULL && supervisor)
-					debug("\t; [<%s>]", symbol);
-				else
-					debug("\t; [0x%08" PRIx32"]", tmpaddr);
-			}
-		}
-		debug("\n");
-		break;
-
-	case 0x10:	/*  and     */
-	case 0x11:	/*  and.u   */
-	case 0x12:	/*  mask    */
-	case 0x13:	/*  mask.u  */
-	case 0x14:	/*  xor     */
-	case 0x15:	/*  xor.u   */
-	case 0x16:	/*  or      */
-	case 0x17:	/*  or.u    */
-		if (d == M88K_ZERO_REG)
-			debug("nop");
-
-		switch (op26) {
-		case 0x10:
-		case 0x11:	mnem = "and"; break;
-		case 0x12:
-		case 0x13:	mnem = "mask"; break;
-		case 0x14:
-		case 0x15:	mnem = "xor"; break;
-		case 0x16:
-		case 0x17:	mnem = "or"; break;
-		}
-
-		if (d != M88K_ZERO_REG || op26 != 0x16 || s1 != M88K_ZERO_REG) {
-			if (d == M88K_ZERO_REG)
-				debug("\t\t; weird nop encoding: ");
-			debug("%s%s\t", mnem, op26 & 1? ".u" : "");
-			debug("r%i,r%i,0x%x", d, s1, imm16);
-		}
-
-		if (op26 == 0x16 && d != M88K_ZERO_REG) {
-			/*
-			 *  The following instruction sequence is common:
-			 *
-			 *  or.u   rX,r0,A
-			 *  or     rY,rX,B	; rY = AAAABBBB
-			 */
-
-			/*  Try loading the instruction before the
-			    current one.  */
-			uint32_t iw2 = 0;
-			cpu->memory_rw(cpu, cpu->mem,
-			    dumpaddr - sizeof(uint32_t), (unsigned char *)&iw2,
-			    sizeof(iw2), MEM_READ, CACHE_INSTRUCTION
-			    | NO_EXCEPTIONS);
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-				 iw2 = LE32_TO_HOST(iw2);
-			else
-				 iw2 = BE32_TO_HOST(iw2);
-			if ((iw2 >> 26) == 0x17 &&	/*  or.u  */
-			    ((iw2 >> 21) & 0x1f) == s1) {
-				uint32_t tmpaddr = (iw2 << 16) + imm16;
-				symbol = get_symbol_name(
-				    &cpu->machine->symbol_context,
-				    tmpaddr, &offset);
-				debug("\t; ");
-				if (symbol != NULL && supervisor)
-					debug("<%s>", symbol);
-				else
-					debug("0x%08" PRIx32, tmpaddr);
-			}
-		}
-
-		debug("\n");
-		break;
-
-	case 0x18:	/*  addu    */
-	case 0x19:	/*  subu    */
-	case 0x1a:	/*  divu    */
-	case 0x1b:	/*  mulu    */
-	case 0x1c:	/*  add    */
-	case 0x1d:	/*  sub    */
-	case 0x1e:	/*  div    */
-	case 0x1f:	/*  cmp    */
-		switch (op26) {
-		case 0x18:	mnem = "addu"; break;
-		case 0x19:	mnem = "subu"; break;
-		case 0x1a:	mnem = "divu"; break;
-		case 0x1b:	mnem = "mulu"; break;
-		case 0x1c:	mnem = "add"; break;
-		case 0x1d:	mnem = "sub"; break;
-		case 0x1e:	mnem = "div"; break;
-		case 0x1f:	mnem = "cmp"; break;
-		}
-		debug("%s\tr%i,r%i,%i\n", mnem, d, s1, imm16);
-		break;
-
-	case 0x20:
-		if ((iw & 0x001ff81f) == 0x00004000) {
-			debug("ldcr\tr%i,%s", d, m88k_cr_name(cpu, cr6));
-			if (running)
-				debug("\t\t; %s = 0x%08x", m88k_cr_name(cpu, cr6), cpu->cd.m88k.cr[cr6]);
-			debug("\n");
-		} else if ((iw & 0x001ff81f) == 0x00004800) {
-			debug("fldcr\tr%i,%s\n", d, m88k_fcr_name(cpu, cr6));
-		} else if ((iw & 0x03e0f800) == 0x00008000) {
-			debug("stcr\tr%i,%s", s1, m88k_cr_name(cpu, cr6));
-			if (s1 != s2)
-				debug("\t\t; NOTE: weird encoding: "
-				    "low 5 bits = 0x%02x", s2);
-			if (running)
-				debug("\t\t; r%i = 0x%08x", s1, cpu->cd.m88k.r[s1]);
-			debug("\n");
-		} else if ((iw & 0x03e0f800) == 0x00008800) {
-			debug("fstcr\tr%i,%s", s1,
-			    m88k_fcr_name(cpu, cr6));
-			if (s1 != s2)
-				debug("\t\t; NOTE: weird encoding: "
-				    "low 5 bits = 0x%02x", s2);
-			debug("\n");
-		} else if ((iw & 0x0000f800) == 0x0000c000) {
-			debug("xcr\tr%i,r%i,%s", d, s1,
-			    m88k_cr_name(cpu, cr6));
-			if (s1 != s2)
-				debug("\t\t; NOTE: weird encoding: "
-				    "low 5 bits = 0x%02x", s2);
-			debug("\n");
-		} else if ((iw & 0x0000f800) == 0x0000c800) {
-			debug("fxcr\tr%i,r%i,%s", d, s1,
-			    m88k_fcr_name(cpu, cr6));
-			if (s1 != s2)
-				debug("\t\t; NOTE: weird encoding: "
-				    "low 5 bits = 0x%02x", s2);
-			debug("\n");
-		} else {
-			debug("UNIMPLEMENTED 0x20\n");
-		}
-		break;
-
-	case 0x21:
-		switch (op11) {
-		case 0x00:	/*  fmul  */
-		case 0x05:	/*  fadd  */
-		case 0x06:	/*  fsub  */
-		case 0x07:	/*  fcmp  */
-		case 0x0e:	/*  fdiv  */
-			switch (op11) {
-			case 0x00: mnem = "fmul"; break;
-			case 0x05: mnem = "fadd"; break;
-			case 0x06: mnem = "fsub"; break;
-			case 0x07: mnem = "fcmp"; break;
-			case 0x0e: mnem = "fdiv"; break;
-			}
-			debug("%s.%c%c%c r%i,r%i,r%i\n",
-			    mnem,
-			    ((iw >> 5) & 1)? 'd' : 's',
-			    ((iw >> 9) & 1)? 'd' : 's',
-			    ((iw >> 7) & 1)? 'd' : 's',
-			    d, s1, s2);
-			break;
-		case 0x04:	/*  flt  */
-			switch (op11) {
-			case 0x04: mnem = "flt"; break;
-			}
-			debug("%s.%cs\tr%i,r%i\n",
-			    mnem,
-			    ((iw >> 5) & 1)? 'd' : 's',
-			    d, s2);
-			break;
-		case 0x09:	/*  int  */
-		case 0x0a:	/*  nint  */
-		case 0x0b:	/*  trnc  */
-			switch (op11) {
-			case 0x09: mnem = "int"; break;
-			case 0x0a: mnem = "nint"; break;
-			case 0x0b: mnem = "trnc"; break;
-			}
-			debug("%s.s%c r%i,r%i\n",
-			    mnem,
-			    ((iw >> 7) & 1)? 'd' : 's',
-			    d, s2);
-			break;
-		default:debug("UNIMPLEMENTED 0x21, op11=0x%02x\n", op11);
-		}
-		break;
-
-	case 0x30:
-	case 0x31:
-	case 0x32:
-	case 0x33:
-		debug("b%sr%s\t",
-		    op26 >= 0x32? "s" : "",
-		    op26 & 1? ".n" : "");
-		debug("0x%08" PRIx32, (uint32_t) (dumpaddr + d26));
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    dumpaddr + d26, &offset);
-		if (symbol != NULL && supervisor)
-			debug("\t; <%s>", symbol);
-		debug("\n");
-		break;
-
-	case 0x34:	/*  bb0    */
-	case 0x35:	/*  bb0.n  */
-	case 0x36:	/*  bb1    */
-	case 0x37:	/*  bb1.n  */
-	case 0x3a:	/*  bcnd    */
-	case 0x3b:	/*  bcnd.n  */
-		switch (op26) {
-		case 0x34:
-		case 0x35: mnem = "bb0"; break;
-		case 0x36:
-		case 0x37: mnem = "bb1"; break;
-		case 0x3a:
-		case 0x3b: mnem = "bcnd"; break;
-		}
-		debug("%s%s\t", mnem, op26 & 1? ".n" : "");
-		if (op26 == 0x3a || op26 == 0x3b) {
-			/*  Attempt to decode bcnd condition:  */
-			switch (d) {
-			case 0x1: debug("gt0"); break;
-			case 0x2: debug("eq0"); break;
-			case 0x3: debug("ge0"); break;
-			case 0x7: debug("not_maxneg"); break;
-			case 0x8: debug("maxneg"); break;
-			case 0xc: debug("lt0"); break;
-			case 0xd: debug("ne0"); break;
-			case 0xe: debug("le0"); break;
-			default:  debug("unimplemented_%i", d);
-			}
-		} else {
-			debug("%i", d);
-		}
-		debug(",r%i,0x%08" PRIx32, s1, (uint32_t) (dumpaddr + d16));
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    dumpaddr + d16, &offset);
-		if (symbol != NULL && supervisor)
-			debug("\t; <%s>", symbol);
-		debug("\n");
-		break;
-
-	case 0x3c:
-		if ((iw & 0x0000f000)==0x1000 || (iw & 0x0000f000)==0x2000) {
-			int scale = 0;
-
-			/*  Load/store:  */
-			debug("%s", (iw & 0x0000f000) == 0x1000? "ld" : "st");
-			switch (iw & 0x00000c00) {
-			case 0x000: scale = 8; debug(".d"); break;
-			case 0x400: scale = 4; break;
-			case 0x800: debug(".x"); break;
-			default: debug(".UNIMPLEMENTED");
-			}
-			if (iw & 0x100)
-				debug(".usr");
-			if (iw & 0x80)
-				debug(".wt");
-			debug("\tr%i,r%i", d, s1);
-			if (iw & 0x200)
-				debug("[r%i]", s2);
-			else
-				debug(",r%i", s2);
-
-			if (running && scale >= 1) {
-				uint32_t tmpaddr = cpu->cd.m88k.r[s1];
-				if (iw & 0x200)
-					tmpaddr += scale * cpu->cd.m88k.r[s2];
-				else
-					tmpaddr += cpu->cd.m88k.r[s2];
-				symbol = get_symbol_name(&cpu->machine->
-				    symbol_context, tmpaddr, &offset);
-				if (symbol != NULL && supervisor)
-					debug("\t; [<%s>]", symbol);
-				else
-					debug("\t; [0x%08" PRIx32"]", tmpaddr);
-			}
-
-			debug("\n");
-		} else switch (op10) {
-		case 0x20:	/*  clr  */
-		case 0x22:	/*  set  */
-		case 0x24:	/*  ext  */
-		case 0x26:	/*  extu  */
-		case 0x28:	/*  mak  */
-		case 0x2a:	/*  rot  */
-			switch (op10) {
-			case 0x20: mnem = "clr"; break;
-			case 0x22: mnem = "set"; break;
-			case 0x24: mnem = "ext"; break;
-			case 0x26: mnem = "extu"; break;
-			case 0x28: mnem = "mak"; break;
-			case 0x2a: mnem = "rot"; break;
-			}
-			debug("%s\tr%i,r%i,", mnem, d, s1);
-			/*  Don't include w5 for the rot instruction:  */
-			if (op10 != 0x2a)
-				debug("%i", w5);
-			/*  Note: o5 = s2:  */
-			debug("<%i>\n", s2);
-			break;
-		case 0x34:	/*  tb0  */
-		case 0x36:	/*  tb1  */
-			switch (op10) {
-			case 0x34: mnem = "tb0"; break;
-			case 0x36: mnem = "tb1"; break;
-			}
-			debug("%s\t%i,r%i,0x%x\n", mnem, d, s1, iw & 0x1ff);
-			break;
-		default:debug("UNIMPLEMENTED 0x3c, op10=0x%02x\n", op10);
-		}
-		break;
-
-	case 0x3d:
-		if ((iw & 0xf000) <= 0x3fff) {
-			int scale = 0;
-
-			/*  Load, Store, xmem, and lda:  */
-			switch (iw & 0xf000) {
-			case 0x2000: debug("st"); break;
-			case 0x3000: debug("lda"); break;
-			default:     if ((iw & 0xf800) >= 0x0800)
-					  debug("ld");
-				     else
-					  debug("xmem");
-			}
-			if ((iw & 0xf000) >= 0x1000) {
-				/*  ld, st, lda  */
-				scale = 1 << (3 - ((iw >> 10) & 3));
-				debug("%s", memop[(iw >> 10) & 3]);
-			} else if ((iw & 0xf800) == 0x0000) {
-				/*  xmem  */
-				if (iw & 0x400)
-					scale = 4;
-				else
-					debug(".bu"), scale = 1;
-			} else {
-				/*  ld  */
-				if ((iw & 0xf00) < 0xc00)
-					debug(".hu"), scale = 2;
-				else
-					debug(".bu"), scale = 1;
-			}
-			if (iw & 0x100)
-				debug(".usr");
-			if (iw & 0x80)
-				debug(".wt");
-			debug("\tr%i,r%i", d, s1);
-			if (iw & 0x200)
-				debug("[r%i]", s2);
-			else
-				debug(",r%i", s2);
-
-			if (running && scale >= 1) {
-				uint32_t tmpaddr = cpu->cd.m88k.r[s1];
-				if (iw & 0x200)
-					tmpaddr += scale * cpu->cd.m88k.r[s2];
-				else
-					tmpaddr += cpu->cd.m88k.r[s2];
-				symbol = get_symbol_name(&cpu->machine->
-				    symbol_context, tmpaddr, &offset);
-				if (symbol != NULL && supervisor)
-					debug("\t; [<%s>]", symbol);
-				else
-					debug("\t; [0x%08" PRIx32"]", tmpaddr);
-			}
-
-			debug("\n");
-		} else switch ((iw >> 8) & 0xff) {
-		case 0x40:	/*  and  */
-		case 0x44:	/*  and.c  */
-		case 0x50:	/*  xor  */
-		case 0x54:	/*  xor.c  */
-		case 0x58:	/*  or  */
-		case 0x5c:	/*  or.c  */
-		case 0x60:	/*  addu  */
-		case 0x61:	/*  addu.co  */
-		case 0x62:	/*  addu.ci  */
-		case 0x63:	/*  addu.cio  */
-		case 0x64:	/*  subu  */
-		case 0x65:	/*  subu.co  */
-		case 0x66:	/*  subu.ci  */
-		case 0x67:	/*  subu.cio  */
-		case 0x68:	/*  divu  */
-		case 0x69:	/*  divu.d  */
-		case 0x6c:	/*  mul  */
-		case 0x6d:	/*  mulu.d  */
-		case 0x6e:	/*  muls  */
-		case 0x70:	/*  add  */
-		case 0x71:	/*  add.co  */
-		case 0x72:	/*  add.ci  */
-		case 0x73:	/*  add.cio  */
-		case 0x74:	/*  sub  */
-		case 0x75:	/*  sub.co  */
-		case 0x76:	/*  sub.ci  */
-		case 0x77:	/*  sub.cio  */
-		case 0x78:	/*  div  */
-		case 0x7c:	/*  cmp  */
-		case 0x80:	/*  clr  */
-		case 0x88:	/*  set  */
-		case 0x90:	/*  ext  */
-		case 0x98:	/*  extu  */
-		case 0xa0:	/*  mak  */
-		case 0xa8:	/*  rot  */
-			/*  Three-register opcodes:  */
-			switch ((iw >> 8) & 0xff) {
-			case 0x40: mnem = "and"; break;
-			case 0x44: mnem = "and.c"; break;
-			case 0x50: mnem = "xor"; break;
-			case 0x54: mnem = "xor.c"; break;
-			case 0x58: mnem = "or"; break;
-			case 0x5c: mnem = "or.c"; break;
-			case 0x60: mnem = "addu"; break;
-			case 0x61: mnem = "addu.co"; break;
-			case 0x62: mnem = "addu.ci"; break;
-			case 0x63: mnem = "addu.cio"; break;
-			case 0x64: mnem = "subu"; break;
-			case 0x65: mnem = "subu.co"; break;
-			case 0x66: mnem = "subu.ci"; break;
-			case 0x67: mnem = "subu.cio"; break;
-			case 0x68: mnem = "divu"; break;
-			case 0x69: mnem = "divu.d"; break;
-			case 0x6c: mnem = "mul"; break;
-			case 0x6d: mnem = "mulu.d"; break;
-			case 0x6e: mnem = "muls"; break;
-			case 0x70: mnem = "add"; break;
-			case 0x71: mnem = "add.co"; break;
-			case 0x72: mnem = "add.ci"; break;
-			case 0x73: mnem = "add.cio"; break;
-			case 0x74: mnem = "sub"; break;
-			case 0x75: mnem = "sub.co"; break;
-			case 0x76: mnem = "sub.ci"; break;
-			case 0x77: mnem = "sub.cio"; break;
-			case 0x78: mnem = "div"; break;
-			case 0x7c: mnem = "cmp"; break;
-			case 0x80: mnem = "clr"; break;
-			case 0x88: mnem = "set"; break;
-			case 0x90: mnem = "ext"; break;
-			case 0x98: mnem = "extu"; break;
-			case 0xa0: mnem = "mak"; break;
-			case 0xa8: mnem = "rot"; break;
-			}
-
-			if (((iw >> 8) & 0xff) == 0x58 && d == M88K_ZERO_REG)
-				debug("nop");
-
-			if (((iw >> 8) & 0xff) != 0x58 || d != M88K_ZERO_REG) {
-				if (d == M88K_ZERO_REG)
-					debug("\t\t; weird nop encoding: ");
-				debug("%s\tr%i,r%i,r%i", mnem, d, s1, s2);
-			}
-
-			debug("\n");
-			break;
-		case 0xc0:	/*  jmp  */
-		case 0xc4:	/*  jmp.n  */
-		case 0xc8:	/*  jsr  */
-		case 0xcc:	/*  jsr.n  */
-			debug("%s%s\t(r%i)",
-			    op11 & 1? "jsr" : "jmp",
-			    iw & 0x400? ".n" : "",
-			    s2);
-			if (running) {
-				uint32_t tmpaddr = cpu->cd.m88k.r[s2];
-				symbol = get_symbol_name(&cpu->machine->
-				    symbol_context, tmpaddr, &offset);
-				debug("\t\t; ");
-				if (symbol != NULL && supervisor)
-					debug("<%s>", symbol);
-				else
-					debug("0x%08" PRIx32, tmpaddr);
-			}
-			debug("\n");
-			break;
-		case 0xe8:	/*  ff1  */
-		case 0xec:	/*  ff0  */
-			debug("%s\tr%i,r%i\n",
-			    ((iw >> 8) & 0xff) == 0xe8 ? "ff1" : "ff0", d, s2);
-			break;
-		case 0xf8:	/*  tbnd  */
-			debug("tbnd\tr%i,r%i\n", s1, s2);
-			break;
-		case 0xfc:
-			switch (iw & 0xff) {
-			case 0x00:
-				debug("rte\n");
-				break;
-			case 0x01:
-			case 0x02:
-			case 0x03:
-				debug("illop%i\n", iw & 0xff);
-				break;
-			case (M88K_PROM_INSTR & 0xff):
-				debug("gxemul_prom_call\n");
-				break;
-			default:debug("UNIMPLEMENTED 0x3d,0xfc: 0x%02x\n",
-				    iw & 0xff);
-			}
-			break;
-		default:debug("UNIMPLEMENTED 0x3d, opbyte = 0x%02x\n",
-			    (iw >> 8) & 0xff);
-		}
-		break;
-
-	case 0x3e:
-		debug("tbnd\tr%i,0x%x\n", s1, imm16);
-		break;
-
-	default:debug("UNIMPLEMENTED op26=0x%02x\n", op26);
-	}
-
-	return sizeof(uint32_t);
-}
-
-
-#include "tmp_m88k_tail.cc"
-
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_m88k_instr.c gxemul-0.7.0+dfsg/src/cpus/cpu_m88k_instr.c
--- gxemul-0.6.2/src/cpus/cpu_m88k_instr.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_m88k_instr.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,2942 @@
+/*
+ *  Copyright (C) 2007-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  M88K instructions.
+ *
+ *  Individual functions should keep track of cpu->n_translated_instrs.
+ *  (If no instruction was executed, then it should be decreased. If, say, 4
+ *  instructions were combined into one function and executed, then it should
+ *  be increased by 3.)
+ */
+
+
+#define SYNCH_PC                {                                       \
+                int low_pc_ = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page) \
+                    / sizeof(struct m88k_instr_call);                   \
+                cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1)               \
+                    << M88K_INSTR_ALIGNMENT_SHIFT);                     \
+                cpu->pc += (low_pc_ << M88K_INSTR_ALIGNMENT_SHIFT);      \
+        }
+
+#define	ABORT_EXECUTION	  {	SYNCH_PC;				\
+				cpu->cd.m88k.next_ic = &nothing_call;	\
+				cpu->running = false; }
+
+
+/*
+ *  nop:  Do nothing.
+ */
+X(nop)
+{
+}
+
+
+/*
+ *  br_samepage:    Branch (to within the same translated page)
+ *  bsr_samepage:   Branch to subroutine (to within the same translated page)
+ *
+ *  arg[0] = pointer to new instr_call
+ *  arg[2] = offset to return address, from start of page
+ */
+X(br_samepage)
+{
+	cpu->cd.m88k.next_ic = (struct m88k_instr_call *) ic->arg[0];
+}
+X(bsr_samepage)
+{
+	cpu->cd.m88k.r[M88K_RETURN_REG] = (cpu->pc &
+	    ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT))
+	    + ic->arg[2];
+	cpu->cd.m88k.next_ic = (struct m88k_instr_call *) ic->arg[0];
+}
+
+
+/*
+ *  br:    Branch (to a different translated page)
+ *  br.n:  Branch (to a different translated page) with delay slot
+ *  bsr:   Branch to subroutine (to a different translated page)
+ *  bsr.n: Branch to subroutine (to a different page) with delay slot
+ *
+ *  arg[1] = relative offset from start of page
+ *  arg[2] = offset to return address, from start of page
+ */
+X(br)
+{
+	cpu->pc = (uint32_t)((cpu->pc & 0xfffff000) + (int32_t)ic->arg[1]);
+	quick_pc_to_pointers(cpu);
+}
+X(br_n)
+{
+	cpu->cd.m88k.delay_target = (cpu->pc & ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
+	    M88K_INSTR_ALIGNMENT_SHIFT)) + (int32_t)ic->arg[1];
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		cpu->pc = cpu->cd.m88k.delay_target;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bsr)
+{
+	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
+	    M88K_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.m88k.r[M88K_RETURN_REG] = cpu->pc + ic->arg[2];
+	cpu->pc = (uint32_t) (cpu->pc + ic->arg[1]);
+	quick_pc_to_pointers(cpu);
+}
+X(bsr_n)
+{
+	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
+	    M88K_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.m88k.r[M88K_RETURN_REG] = cpu->pc + ic->arg[2] + 4;
+	cpu->cd.m88k.delay_target = cpu->pc + ic->arg[1];
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		cpu->pc = cpu->cd.m88k.delay_target;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bsr_trace)
+{
+	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
+	    M88K_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.m88k.r[M88K_RETURN_REG] = cpu->pc + ic->arg[2];
+	cpu->pc = (uint32_t) (cpu->pc + ic->arg[1]);
+	cpu_functioncall_trace(cpu, cpu->pc);
+	quick_pc_to_pointers(cpu);
+}
+X(bsr_n_trace)
+{
+	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
+	    M88K_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.m88k.r[M88K_RETURN_REG] = cpu->pc + ic->arg[2] + 4;
+	cpu->cd.m88k.delay_target = cpu->pc + ic->arg[1];
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		cpu->pc = cpu->cd.m88k.delay_target;
+		cpu_functioncall_trace(cpu, cpu->pc);
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  bb?            Branch if a bit in a register is 0 or 1.
+ *  bb?_samepage:  Branch within the same translated page.
+ *  bb?_n_*:       With delay slot.
+ *
+ *  arg[0] = pointer to source register to test (s1).
+ *  arg[1] = uint32_t mask to test (e.g. 0x00010000 to test bit 16)
+ *  arg[2] = offset from start of current page _OR_ pointer to new instr_call
+ */
+X(bb0)
+{
+	if (!(reg(ic->arg[0]) & ic->arg[1])) {
+		cpu->pc = (cpu->pc & 0xfffff000) + (int32_t)ic->arg[2];
+		quick_pc_to_pointers(cpu);
+	}
+}
+X(bb0_samepage)
+{
+	if (!(reg(ic->arg[0]) & ic->arg[1]))
+		cpu->cd.m88k.next_ic = (struct m88k_instr_call *) ic->arg[2];
+}
+X(bb0_n)
+{
+	int cond = !(reg(ic->arg[0]) & (uint32_t)ic->arg[1]);
+
+	SYNCH_PC;
+
+	if (cond)
+		cpu->cd.m88k.delay_target =
+		    (cpu->pc & ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
+		    M88K_INSTR_ALIGNMENT_SHIFT)) + (int32_t)ic->arg[2];
+	else
+		cpu->cd.m88k.delay_target = cpu->pc + 8;
+
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (cond) {
+			cpu->pc = cpu->cd.m88k.delay_target;
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.m88k.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bb1)
+{
+	if (reg(ic->arg[0]) & ic->arg[1]) {
+		cpu->pc = (cpu->pc & 0xfffff000) + (int32_t)ic->arg[2];
+		quick_pc_to_pointers(cpu);
+	}
+}
+X(bb1_samepage)
+{
+	if (reg(ic->arg[0]) & ic->arg[1])
+		cpu->cd.m88k.next_ic = (struct m88k_instr_call *) ic->arg[2];
+}
+X(bb1_n)
+{
+	int cond = reg(ic->arg[0]) & ic->arg[1];
+
+	SYNCH_PC;
+
+	if (cond)
+		cpu->cd.m88k.delay_target =
+		    (cpu->pc & ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
+		    M88K_INSTR_ALIGNMENT_SHIFT)) + (int32_t)ic->arg[2];
+	else
+		cpu->cd.m88k.delay_target = cpu->pc + 8;
+
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (cond) {
+			cpu->pc = cpu->cd.m88k.delay_target;
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.m88k.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  ff0, ff1: Find first cleared/set bit in a register
+ *
+ *  arg[0] = pointer to register d
+ *  arg[2] = pointer to register s2
+ */
+X(ff0)
+{
+	uint32_t mask = 0x80000000, s2 = reg(ic->arg[2]);
+	int n = 31;
+
+	for (;;) {
+		if (!(s2 & mask)) {
+			reg(ic->arg[0]) = n;
+			return;
+		}
+		mask >>= 1; n--;
+		if (mask == 0) {
+			reg(ic->arg[0]) = 32;
+			return;
+		}
+	}
+}
+X(ff1)
+{
+	uint32_t mask = 0x80000000, s2 = reg(ic->arg[2]);
+	int n = 31;
+
+	for (;;) {
+		if (s2 & mask) {
+			reg(ic->arg[0]) = n;
+			return;
+		}
+		mask >>= 1; n--;
+		if (mask == 0) {
+			reg(ic->arg[0]) = 32;
+			return;
+		}
+	}
+}
+
+
+/*  Include all automatically generated bcnd and bcnd.n instructions:  */
+#include "tmp_m88k_bcnd.c"
+
+
+/*  Include all automatically generated load/store instructions:  */
+#include "tmp_m88k_loadstore.c"
+#define M88K_LOADSTORE_STORE            4
+#define M88K_LOADSTORE_SIGNEDNESS       8
+#define M88K_LOADSTORE_ENDIANNESS       16
+#define M88K_LOADSTORE_SCALEDNESS       32
+#define M88K_LOADSTORE_USR              64
+#define M88K_LOADSTORE_REGISTEROFFSET   128
+#define	M88K_LOADSTORE_NO_PC_SYNC	256
+
+
+/*
+ *  jmp:   Jump to register
+ *  jmp.n: Jump to register, with delay slot
+ *  jsr:   Jump to register, set r1 to return address
+ *  jsr.n: Jump to register, set r1 to return address, with delay slot
+ *
+ *  arg[1] = offset to return address, from start of current page
+ *  arg[2] = pointer to register s2
+ */
+X(jmp)
+{
+	cpu->pc = reg(ic->arg[2]) & ~3;
+	quick_pc_to_pointers(cpu);
+}
+X(jmp_n)
+{
+	cpu->cd.m88k.delay_target = reg(ic->arg[2]) & ~3;
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		cpu->pc = cpu->cd.m88k.delay_target;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(jmp_trace)
+{
+	cpu->pc = reg(ic->arg[2]) & ~3;
+	cpu_functioncall_trace_return(cpu);
+	quick_pc_to_pointers(cpu);
+}
+X(jmp_n_trace)
+{
+	cpu->cd.m88k.delay_target = reg(ic->arg[2]) & ~3;
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		cpu->pc = cpu->cd.m88k.delay_target;
+		cpu_functioncall_trace_return(cpu);
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(jsr)
+{
+	cpu->cd.m88k.r[M88K_RETURN_REG] = (cpu->pc & 0xfffff000) + ic->arg[1];
+	cpu->pc = reg(ic->arg[2]) & ~3;
+	quick_pc_to_pointers(cpu);
+}
+X(jsr_n)
+{
+	cpu->cd.m88k.delay_target = reg(ic->arg[2]) & ~3;
+	cpu->cd.m88k.r[M88K_RETURN_REG] = (cpu->pc & 0xfffff000) + ic->arg[1];
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		cpu->pc = cpu->cd.m88k.delay_target;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(jsr_trace)
+{
+	cpu->cd.m88k.r[M88K_RETURN_REG] = (cpu->pc & 0xfffff000) + ic->arg[1];
+	cpu->pc = reg(ic->arg[2]) & ~3;
+	cpu_functioncall_trace(cpu, cpu->pc);
+	quick_pc_to_pointers(cpu);
+}
+X(jsr_n_trace)
+{
+	cpu->cd.m88k.delay_target = reg(ic->arg[2]) & ~3;
+	cpu->cd.m88k.r[M88K_RETURN_REG] = (cpu->pc & 0xfffff000) + ic->arg[1];
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		cpu->pc = cpu->cd.m88k.delay_target;
+		cpu_functioncall_trace(cpu, cpu->pc);
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  cmp_imm:  Compare S1 with immediate value.
+ *  cmp:      Compare S1 with S2.
+ *
+ *  arg[0] = pointer to register d
+ *  arg[1] = pointer to register s1
+ *  arg[2] = pointer to register s2 or imm
+ */
+static void m88k_cmp(struct cpu *cpu, struct m88k_instr_call *ic, uint32_t y)
+{
+	uint32_t x = reg(ic->arg[1]);
+	uint32_t r;
+
+	if (x == y) {
+		r = M88K_CMP_HS | M88K_CMP_LS | M88K_CMP_GE
+		  | M88K_CMP_LE | M88K_CMP_EQ;
+	} else {
+		if (x > y)
+			r = M88K_CMP_NE | M88K_CMP_HS | M88K_CMP_HI;
+		else
+			r = M88K_CMP_NE | M88K_CMP_LO | M88K_CMP_LS;
+		if ((int32_t)x > (int32_t)y)
+			r |= M88K_CMP_GE | M88K_CMP_GT;
+		else
+			r |= M88K_CMP_LT | M88K_CMP_LE;
+	}
+
+	reg(ic->arg[0]) = r;
+}
+X(cmp_imm) { m88k_cmp(cpu, ic, ic->arg[2]); }
+X(cmp)     { m88k_cmp(cpu, ic, reg(ic->arg[2])); }
+
+
+/*
+ *  extu_imm:  Extract bits, unsigned, immediate W<O>.
+ *  extu:      Extract bits, unsigned, W<O> taken from register s2.
+ *  ext_imm:   Extract bits, signed, immediate W<O>.
+ *  ext:       Extract bits, signed, W<O> taken from register s2.
+ *  mak_imm:   Make bit field, immediate W<O>.
+ *  mak:       Make bit field, W<O> taken from register s2.
+ *  rot:       Rotate s1 right, nr of steps taken from s2.
+ *  clr:       Clear bits, W<O> taken from register s2.
+ *  set:       Set bits, W<O> taken from register s2.
+ *
+ *  arg[0] = pointer to register d
+ *  arg[1] = pointer to register s1
+ *  arg[2] = pointer to register s2 or 10 bits wwwwwooooo
+ */
+static void m88k_extu(struct cpu *cpu, struct m88k_instr_call *ic, int w, int o)
+{
+	uint32_t x = reg(ic->arg[1]) >> o;
+	if (w != 0) {
+		x <<= (32-w);
+		x >>= (32-w);
+	}
+	reg(ic->arg[0]) = x;
+}
+static void m88k_ext(struct cpu *cpu, struct m88k_instr_call *ic, int w, int o)
+{
+	int32_t x = reg(ic->arg[1]);
+	x >>= o;	/*  signed (arithmetic) shift  */
+	if (w != 0) {
+		x <<= (32-w);
+		x >>= (32-w);
+	}
+	reg(ic->arg[0]) = x;
+}
+static void m88k_mak(struct cpu *cpu, struct m88k_instr_call *ic, int w, int o)
+{
+	uint32_t x = reg(ic->arg[1]);
+	if (w != 0) {
+		x <<= (32-w);
+		x >>= (32-w);
+	}
+	reg(ic->arg[0]) = x << o;
+}
+X(extu_imm)
+{
+	m88k_extu(cpu, ic, ic->arg[2] >> 5, ic->arg[2] & 0x1f);
+}
+X(extu)
+{
+	m88k_extu(cpu, ic, (reg(ic->arg[2]) >> 5) & 0x1f,
+	    reg(ic->arg[2]) & 0x1f);
+}
+X(ext_imm)
+{
+	m88k_ext(cpu, ic, ic->arg[2] >> 5, ic->arg[2] & 0x1f);
+}
+X(ext)
+{
+	m88k_ext(cpu, ic, (reg(ic->arg[2]) >> 5) & 0x1f,
+	    reg(ic->arg[2]) & 0x1f);
+}
+X(mak_imm)
+{
+	m88k_mak(cpu, ic, ic->arg[2] >> 5, ic->arg[2] & 0x1f);
+}
+X(mak)
+{
+	m88k_mak(cpu, ic, (reg(ic->arg[2]) >> 5) & 0x1f,
+	    reg(ic->arg[2]) & 0x1f);
+}
+static void m88k_rot(struct cpu *cpu, struct m88k_instr_call *ic, int n)
+{
+	uint32_t x = reg(ic->arg[1]);
+
+	if (n != 0) {
+		uint32_t mask = (1 << n) - 1;
+		uint32_t bits = x & mask;
+		x >>= n;
+		x |= (bits << (32-n));
+	}
+
+	reg(ic->arg[0]) = x;
+}
+X(rot_imm)
+{
+	m88k_rot(cpu, ic, ic->arg[2] & 0x1f);
+}
+X(rot)
+{
+	m88k_rot(cpu, ic, reg(ic->arg[2]) & 0x1f);
+}
+X(clr)
+{
+	int w = (reg(ic->arg[2]) >> 5) & 0x1f, o = reg(ic->arg[2]) & 0x1f;
+	uint32_t x = w == 0? 0xffffffff : ((uint32_t)1 << w) - 1;
+	x <<= o;
+	reg(ic->arg[0]) = reg(ic->arg[1]) & ~x;
+}
+X(set)
+{
+	int w = (reg(ic->arg[2]) >> 5) & 0x1f, o = reg(ic->arg[2]) & 0x1f;
+	uint32_t x = w == 0? 0xffffffff : ((uint32_t)1 << w) - 1;
+	x <<= o;
+	reg(ic->arg[0]) = reg(ic->arg[1]) | x;
+}
+
+
+/*
+ *  or_r0_imm0: d = 0		(optimized case when s1 = r0, imm = 0)
+ *  or_r0_imm:  d = imm		(optimized case when s1 = r0)
+ *  or_imm:     d = s1 | imm
+ *  xor_imm:    d = s1 ^ imm
+ *  and_imm:    d = (s1 & imm) | (s1 & 0xffff0000)
+ *  and_u_imm:  d = (s1 & imm) | (s1 & 0xffff)
+ *  mask_imm:   d = s1 & imm
+ *  add_imm:    d = s1 - imm	(addition with overflow exception)
+ *  addu_imm:   d = s1 + imm
+ *  subu_imm:   d = s1 - imm
+ *  inc_reg:    d ++;		(addu special case; d = d + 1)
+ *  dec_reg:    d --;		(subu special case; d = d - 1)
+ *  mulu_imm:   d = s1 * imm
+ *  divu_imm:   d = s1 / imm	(unsigned)
+ *  div_imm:    d = s1 / imm	(signed)
+ *  sub_imm:    d = s1 - imm	(subtraction with overflow exception)
+ *
+ *  arg[0] = pointer to register d
+ *  arg[1] = pointer to register s1
+ *  arg[2] = imm
+ */
+X(or_r0_imm0)	{ reg(ic->arg[0]) = 0; }
+X(or_r0_imm)	{ reg(ic->arg[0]) = ic->arg[2]; }
+X(or_imm)	{ reg(ic->arg[0]) = reg(ic->arg[1]) | ic->arg[2]; }
+X(xor_imm)	{ reg(ic->arg[0]) = reg(ic->arg[1]) ^ ic->arg[2]; }
+X(and_imm)	{ reg(ic->arg[0]) = (reg(ic->arg[1]) & ic->arg[2])
+		    | (reg(ic->arg[1]) & 0xffff0000); }
+X(and_u_imm)	{ reg(ic->arg[0]) = (reg(ic->arg[1]) & ic->arg[2])
+		    | (reg(ic->arg[1]) & 0xffff); }
+X(mask_imm)	{ reg(ic->arg[0]) = reg(ic->arg[1]) & ic->arg[2]; }
+X(add_imm)
+{
+	uint64_t a = (int32_t) reg(ic->arg[1]);
+	uint64_t b = ic->arg[2];
+	uint64_t res = a + b;
+	uint64_t res2 = (int32_t) res;
+
+	if (res != res2) {
+		SYNCH_PC;
+		m88k_exception(cpu, M88K_EXCEPTION_INTEGER_OVERFLOW, 0);
+		return;
+	}
+
+	reg(ic->arg[0]) = res;
+}
+X(addu_imm)	{ reg(ic->arg[0]) = reg(ic->arg[1]) + ic->arg[2]; }
+X(subu_imm)	{ reg(ic->arg[0]) = reg(ic->arg[1]) - ic->arg[2]; }
+X(inc_reg)	{ reg(ic->arg[0]) ++; }
+X(dec_reg)	{ reg(ic->arg[0]) --; }
+X(mulu_imm)
+{
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+	} else
+		reg(ic->arg[0]) = reg(ic->arg[1]) * ic->arg[2];
+}
+X(divu_imm)
+{
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+	} else if (ic->arg[2] == 0) {
+		SYNCH_PC;
+		m88k_exception(cpu, M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE, 0);
+	} else
+		reg(ic->arg[0]) = (uint32_t) reg(ic->arg[1]) / (uint32_t) ic->arg[2];
+}
+X(div_imm)
+{
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+	} else if (ic->arg[2] == 0) {
+		SYNCH_PC;
+		m88k_exception(cpu, M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE, 0);
+	} else {
+		int32_t res = (int32_t) reg(ic->arg[1]) / (int32_t) ic->arg[2];
+		reg(ic->arg[0]) = res;
+	}
+}
+X(sub_imm)
+{
+	uint64_t a = (int32_t) reg(ic->arg[1]);
+	uint64_t b = ic->arg[2];
+	uint64_t res = a - b;
+	uint64_t res2 = (int32_t) res;
+
+	if (res != res2) {
+		SYNCH_PC;
+		m88k_exception(cpu, M88K_EXCEPTION_INTEGER_OVERFLOW, 0);
+		return;
+	}
+
+	reg(ic->arg[0]) = res;
+}
+
+
+/*
+ *  or:     	d = s1 | s2
+ *  or_c:     	d = s1 | ~s2
+ *  or_r0:  	d =      s2
+ *  xor:    	d = s1 ^ s2
+ *  xor_c:    	d = s1 ^ ~s2
+ *  and:    	d = s1 & s2
+ *  and_c:    	d = s1 & ~s2
+ *  add:   	d = s1 + s2		with trap on overflow
+ *  addu:   	d = s1 + s2
+ *  addu_co:   	d = s1 + s2		carry out
+ *  addu_ci:   	d = s1 + s2 + carry	carry in
+ *  addu_cio:   d = s1 + s2 + carry	carry in & carry out
+ *  lda_reg_X:	same as addu, but s2 is scaled by 2, 4, or 8
+ *  subu:   	d = s1 - s2
+ *  subu_co:   	d = s1 - s2		carry/borrow out
+ *  subu_ci:   	d = s1 - s2 - (carry? 0 : 1)	carry in
+ *  subu_cio:   d = s1 - s2 - (carry? 0 : 1)	carry in & carry/borrow out
+ *  mul:    	d = s1 * s2
+ *  divu:   	d = s1 / s2		(unsigned)
+ *  div:    	d = s1 / s2		(signed)
+ *
+ *  arg[0] = pointer to register d
+ *  arg[1] = pointer to register s1
+ *  arg[2] = pointer to register s2
+ */
+X(or)	{ reg(ic->arg[0]) = reg(ic->arg[1]) | reg(ic->arg[2]); }
+X(or_c)	{ reg(ic->arg[0]) = reg(ic->arg[1]) | ~(reg(ic->arg[2])); }
+X(or_r0){ reg(ic->arg[0]) = reg(ic->arg[2]); }
+X(xor)	{ reg(ic->arg[0]) = reg(ic->arg[1]) ^ reg(ic->arg[2]); }
+X(xor_c){ reg(ic->arg[0]) = reg(ic->arg[1]) ^ ~(reg(ic->arg[2])); }
+X(and)	{ reg(ic->arg[0]) = reg(ic->arg[1]) & reg(ic->arg[2]); }
+X(and_c){ reg(ic->arg[0]) = reg(ic->arg[1]) & ~(reg(ic->arg[2])); }
+X(addu)	{ reg(ic->arg[0]) = reg(ic->arg[1]) + reg(ic->arg[2]); }
+X(addu_s2r0)	{ reg(ic->arg[0]) = reg(ic->arg[1]); }
+X(lda_reg_2)	{ reg(ic->arg[0]) = reg(ic->arg[1]) + reg(ic->arg[2]) * 2; }
+X(lda_reg_4)	{ reg(ic->arg[0]) = reg(ic->arg[1]) + reg(ic->arg[2]) * 4; }
+X(lda_reg_8)	{ reg(ic->arg[0]) = reg(ic->arg[1]) + reg(ic->arg[2]) * 8; }
+X(subu)	{ reg(ic->arg[0]) = reg(ic->arg[1]) - reg(ic->arg[2]); }
+X(add)
+{
+	uint64_t s1 = (int32_t) reg(ic->arg[1]);
+	uint64_t s2 = (int32_t) reg(ic->arg[2]);
+	uint64_t d = s1 + s2;
+	uint64_t dx = (int32_t) d;
+
+	/*  "If the result cannot be represented as a signed 32-bit integer"
+	    then there should be an exception.  */
+	if (d != dx) {
+		SYNCH_PC;
+		m88k_exception(cpu, M88K_EXCEPTION_INTEGER_OVERFLOW, 0);
+	} else {
+		reg(ic->arg[0]) = d;
+	}
+}
+X(mul)
+{
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+	} else
+		reg(ic->arg[0]) = reg(ic->arg[1]) * reg(ic->arg[2]);
+}
+X(divu)
+{
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+	} else if (reg(ic->arg[2]) == 0) {
+		SYNCH_PC;
+		m88k_exception(cpu, M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE, 0);
+	} else
+		reg(ic->arg[0]) = (uint32_t) reg(ic->arg[1]) / (uint32_t) reg(ic->arg[2]);
+}
+X(div)
+{
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+	} else if (reg(ic->arg[2]) == 0) {
+		SYNCH_PC;
+		m88k_exception(cpu, M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE, 0);
+	} else {
+		int32_t res = (int32_t) reg(ic->arg[1]) / (int32_t) reg(ic->arg[2]);
+		reg(ic->arg[0]) = res;
+	}
+}
+X(addu_co)
+{
+	uint64_t a = reg(ic->arg[1]), b = reg(ic->arg[2]);
+	a += b;
+	reg(ic->arg[0]) = a;
+	cpu->cd.m88k.cr[M88K_CR_PSR] &= ~M88K_PSR_C;
+	if ((a >> 32) & 1)
+		cpu->cd.m88k.cr[M88K_CR_PSR] |= M88K_PSR_C;
+}
+X(addu_cio)
+{
+	uint64_t a = reg(ic->arg[1]), b = reg(ic->arg[2]);
+	a += b;
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_C)
+		a ++;
+	reg(ic->arg[0]) = a;
+	cpu->cd.m88k.cr[M88K_CR_PSR] &= ~M88K_PSR_C;
+	if ((a >> 32) & 1)
+		cpu->cd.m88k.cr[M88K_CR_PSR] |= M88K_PSR_C;
+}
+X(addu_ci)
+{
+	uint32_t result = reg(ic->arg[1]) + reg(ic->arg[2]);
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_C)
+		result ++;
+	reg(ic->arg[0]) = result;
+}
+X(subu_cio)
+{
+	uint64_t a = reg(ic->arg[1]), b = reg(ic->arg[2]) ^ 0xffffffff;
+	a += b;
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_C)
+		a ++;
+	reg(ic->arg[0]) = a;
+	cpu->cd.m88k.cr[M88K_CR_PSR] &= ~M88K_PSR_C;
+	if ((a >> 32) & 1)
+		cpu->cd.m88k.cr[M88K_CR_PSR] |= M88K_PSR_C;
+}
+X(subu_co)
+{
+	uint64_t a = reg(ic->arg[1]), b = reg(ic->arg[2]) ^ 0xffffffff;
+	a += b + 1;
+	reg(ic->arg[0]) = a;
+	cpu->cd.m88k.cr[M88K_CR_PSR] &= ~M88K_PSR_C;
+	if ((a >> 32) & 1)
+		cpu->cd.m88k.cr[M88K_CR_PSR] |= M88K_PSR_C;
+}
+X(subu_ci)
+{
+	uint32_t result = reg(ic->arg[1]) + ~reg(ic->arg[2]);
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_C)
+		result ++;
+	reg(ic->arg[0]) = result;
+}
+
+
+/*
+ *  ldcr:   Load value from a control register, store in register d.
+ *  fldcr:  Load value from a floating point control register, store in reg d.
+ *
+ *  arg[0] = pointer to register d
+ *  arg[1] = 6-bit control register number
+ */
+X(ldcr)
+{
+	SYNCH_PC;
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE) {
+		m88k_ldcr(cpu, (uint32_t *) (void *) ic->arg[0], ic->arg[1]);
+
+		if (!cpu->running)
+			ABORT_EXECUTION;
+	} else
+		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
+}
+X(fldcr)
+{
+	SYNCH_PC;
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE || ic->arg[1] >= 62)
+		reg(ic->arg[0]) = cpu->cd.m88k.fcr[ic->arg[1]];
+	else {
+		/*  TODO: The manual says "floating point privilege
+		    violation", not just "privilege violation"!  */
+		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
+	}
+}
+
+
+/*
+ *  stcr:   Store a value into a control register.
+ *  fstcr:  Store a value into a floating point control register.
+ *
+ *  arg[0] = pointer to source register
+ *  arg[1] = 6-bit control register number
+ */
+X(stcr)
+{
+	SYNCH_PC;
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE) {
+		m88k_stcr(cpu, reg(ic->arg[0]), ic->arg[1], 0);
+
+		if (!cpu->running)
+			ABORT_EXECUTION;
+	} else
+		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
+}
+X(fstcr)
+{
+	SYNCH_PC;
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE || ic->arg[1] >= 62) {
+		m88k_fstcr(cpu, reg(ic->arg[0]), ic->arg[1]);
+
+		if (!cpu->running)
+			ABORT_EXECUTION;
+	} else {
+		/*  TODO: The manual says "floating point privilege
+		    violation", not just "privilege violation"!  */
+		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
+	}
+}
+
+
+/*
+ *  fadd.xxx:  Floating point addition
+ *  fsub.xxx:  Floating point subtraction
+ *  fmul.xxx:  Floating point multiplication
+ *  fdiv.xxx:  Floating point multiplication
+ *
+ *  arg[0] = pointer to destination register
+ *  arg[1] = pointer to source register s1
+ *  arg[2] = pointer to source register s2
+ *
+ *  Note: For 'd' variants, arg[x] points to a _pair_ of registers!
+ */
+X(fadd_sss)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint32_t d;
+	uint32_t s2 = reg(ic->arg[2]);
+	uint32_t s1 = reg(ic->arg[1]);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+
+	d = ieee_store_float_value(f1.f + f2.f, IEEE_FMT_S);
+
+	reg(ic->arg[0]) = d;
+}
+X(fadd_dss)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint32_t s2 = reg(ic->arg[2]);
+	uint32_t s1 = reg(ic->arg[1]);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+
+	d = ieee_store_float_value(f1.f + f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fadd_dsd)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint64_t s2 = reg(ic->arg[2]);
+	uint32_t s1 = reg(ic->arg[1]);
+	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
+
+	d = ieee_store_float_value(f1.f + f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fadd_dds)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint32_t s2 = reg(ic->arg[2]);
+	uint64_t s1 = reg(ic->arg[1]);
+	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+
+	d = ieee_store_float_value(f1.f + f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fadd_ddd)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint64_t s1 = reg(ic->arg[1]);
+	uint64_t s2 = reg(ic->arg[2]);
+	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
+	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
+
+	d = ieee_store_float_value(f1.f + f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fsub_sss)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint32_t d;
+	uint32_t s2 = reg(ic->arg[2]);
+	uint32_t s1 = reg(ic->arg[1]);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+
+	d = ieee_store_float_value(f1.f - f2.f, IEEE_FMT_S);
+	reg(ic->arg[0]) = d;
+}
+X(fsub_sds)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint32_t d;
+	uint32_t s2 = reg(ic->arg[2]);
+	uint64_t s1 = reg(ic->arg[1]);
+	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+
+	d = ieee_store_float_value(f1.f - f2.f, IEEE_FMT_S);
+	reg(ic->arg[0]) = d;
+}
+X(fsub_dss)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint32_t s2 = reg(ic->arg[2]);
+	uint32_t s1 = reg(ic->arg[1]);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+
+	d = ieee_store_float_value(f1.f - f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fsub_dsd)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint64_t s2 = reg(ic->arg[2]);
+	uint32_t s1 = reg(ic->arg[1]);
+	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
+
+	d = ieee_store_float_value(f1.f - f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fsub_dds)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint32_t s2 = reg(ic->arg[2]);
+	uint64_t s1 = reg(ic->arg[1]);
+	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+
+	d = ieee_store_float_value(f1.f - f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fsub_ddd)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint64_t s1 = reg(ic->arg[1]);
+	uint64_t s2 = reg(ic->arg[2]);
+	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
+	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
+
+	d = ieee_store_float_value(f1.f - f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fmul_sss)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint32_t d;
+	uint32_t s2 = reg(ic->arg[2]);
+	uint32_t s1 = reg(ic->arg[1]);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+
+	d = ieee_store_float_value(f1.f * f2.f, IEEE_FMT_S);
+	reg(ic->arg[0]) = d;
+}
+X(fmul_dss)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint32_t s2 = reg(ic->arg[2]);
+	uint32_t s1 = reg(ic->arg[1]);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+
+	d = ieee_store_float_value(f1.f * f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fmul_dsd)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint64_t s2 = reg(ic->arg[2]);
+	uint32_t s1 = reg(ic->arg[1]);
+	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
+
+	d = ieee_store_float_value(f1.f * f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fmul_dds)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint32_t s2 = reg(ic->arg[2]);
+	uint64_t s1 = reg(ic->arg[1]);
+	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+
+	d = ieee_store_float_value(f1.f * f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fmul_ddd)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint64_t s1 = reg(ic->arg[1]);
+	uint64_t s2 = reg(ic->arg[2]);
+	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
+	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
+
+	d = ieee_store_float_value(f1.f * f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fdiv_sss)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint32_t d;
+	uint32_t s1 = reg(ic->arg[1]);
+	uint32_t s2 = reg(ic->arg[2]);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+
+	if (f2.f == 0) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FDVZ;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	d = ieee_store_float_value(f1.f / f2.f, IEEE_FMT_S);
+
+	reg(ic->arg[0]) = d;
+}
+X(fdiv_dss)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint32_t s1 = reg(ic->arg[1]);
+	uint32_t s2 = reg(ic->arg[2]);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+
+	if (f2.f == 0) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FDVZ;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	d = ieee_store_float_value(f1.f / f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fdiv_dsd)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint32_t s1 = reg(ic->arg[1]);
+	uint64_t s2 = reg(ic->arg[2]);
+	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
+
+	if (f2.f == 0) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FDVZ;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	d = ieee_store_float_value(f1.f / f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+X(fdiv_ddd)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t d;
+	uint64_t s1 = reg(ic->arg[1]);
+	uint64_t s2 = reg(ic->arg[2]);
+	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
+	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
+
+	if (f2.f == 0) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FDVZ;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	d = ieee_store_float_value(f1.f / f2.f, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
+}
+
+
+/*
+ *  fcmp.sXX:  Floating point comparison
+ *
+ *  arg[0] = pointer to destination register
+ *  arg[1] = pointer to source register s1
+ *  arg[2] = pointer to source register s2
+ *
+ *  Note: For 'd' variants, arg[x] points to a _pair_ of registers!
+ */
+static uint32_t m88k_fcmp_common(struct ieee_float_value *f1,
+	struct ieee_float_value *f2)
+{
+	uint32_t d;
+
+	/*  TODO: Implement all bits correctly, e.g. "in range" bits.  */
+	d = 0;
+	if (isnan(f1->f) || isnan(f2->f))
+		// This bit is set if the two numbers are not comparable.
+		d |= (1 << 0);
+	else {
+		// This bit is set if the two numbers are comparable.
+		d |= (1 << 1);
+
+		if (f1->f == f2->f)
+			d |= (1 << 2);
+		else
+			d |= (1 << 3);
+
+		if (f1->f > f2->f)
+			d |= (1 << 4);
+		else
+			d |= (1 << 5);
+
+		if (f1->f < f2->f)
+			d |= (1 << 6);
+		else
+			d |= (1 << 7);
+	}
+
+	return d;
+}
+X(fcmp_sss)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint32_t s2 = reg(ic->arg[2]);
+	uint32_t s1 = reg(ic->arg[1]);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+	reg(ic->arg[0]) = m88k_fcmp_common(&f1, &f2);
+}
+X(fcmp_ssd)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t s2 = reg(ic->arg[2]);
+	uint32_t s1 = reg(ic->arg[1]);
+	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
+	reg(ic->arg[0]) = m88k_fcmp_common(&f1, &f2);
+}
+X(fcmp_sds)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint32_t s2 = reg(ic->arg[2]);
+	uint64_t s1 = reg(ic->arg[1]);
+	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
+	reg(ic->arg[0]) = m88k_fcmp_common(&f1, &f2);
+}
+X(fcmp_sdd)
+{
+	struct ieee_float_value f1;
+	struct ieee_float_value f2;
+	uint64_t s1 = reg(ic->arg[1]);
+	uint64_t s2 = reg(ic->arg[2]);
+	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
+	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
+	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
+	reg(ic->arg[0]) = m88k_fcmp_common(&f1, &f2);
+}
+
+
+/*
+ *  flt.ss and flt.ds:  Convert integer to floating point.
+ *
+ *  arg[0] = pointer to destination register
+ *  arg[1] = pointer to source register s2
+ *
+ *  Note: For flt.ds, arg[0] points to a _pair_ of registers!
+ */
+X(flt_ss)
+{
+	int32_t x = reg(ic->arg[1]);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	reg(ic->arg[0]) = ieee_store_float_value((double)x, IEEE_FMT_S);
+}
+X(flt_ds)
+{
+	int32_t x = reg(ic->arg[1]);
+	uint64_t result;
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	result = ieee_store_float_value((double)x, IEEE_FMT_D);
+
+	reg(ic->arg[0]) = result >> 32;	/*  High 32-bit word,  */
+	reg(ic->arg[0] + 4) = result;	/*  and low word.  */
+}
+
+
+/*
+ *  trnc.ss and trnc.sd:  Truncate floating point to interger.
+ *
+ *  arg[0] = pointer to destination register
+ *  arg[1] = pointer to source register s2
+ *
+ *  Note: For trnc.sd, arg[1] points to a _pair_ of registers!
+ */
+X(trnc_ss)
+{
+	struct ieee_float_value f1;
+	ieee_interpret_float_value(reg(ic->arg[1]), &f1, IEEE_FMT_S);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	reg(ic->arg[0]) = (int32_t) f1.f;
+}
+X(trnc_sd)
+{
+	struct ieee_float_value f1;
+	uint64_t x = reg(ic->arg[1]);
+	x = (x << 32) + reg(ic->arg[1] + 4);
+	ieee_interpret_float_value(x, &f1, IEEE_FMT_D);
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
+		SYNCH_PC;
+		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
+		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
+		return;
+	}
+
+	reg(ic->arg[0]) = (int32_t) f1.f;
+}
+
+
+/*
+ *  xcr:   Exchange (load + store) control register.
+ *
+ *  arg[0] = pointer to register d
+ *  arg[1] = pointer to register s1
+ *  arg[2] = 6-bit control register number
+ */
+X(xcr)
+{
+	uint32_t tmp, tmp2;
+	SYNCH_PC;
+
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE) {
+		tmp = reg(ic->arg[1]);
+		m88k_ldcr(cpu, &tmp2, ic->arg[2]);
+		if (!cpu->running) {
+			ABORT_EXECUTION;
+		} else {
+			m88k_stcr(cpu, tmp, ic->arg[2], 0);
+			reg(ic->arg[0]) = tmp2;
+		}
+	} else
+		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
+}
+
+
+/*
+ *  rte:  Return from exception
+ */
+X(rte)
+{
+	/*  If executed from user mode, then cause an exception:  */
+	if (!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)) {
+		SYNCH_PC;
+		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
+		return;
+	}
+
+	m88k_stcr(cpu, cpu->cd.m88k.cr[M88K_CR_EPSR], M88K_CR_PSR, 1);
+
+	if (cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_E) {
+		debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+		    "rte: NIP: TODO: single-step support");
+		goto abort_dump;
+	}
+
+	if (cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_E) {
+		debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+		    "rte: TODO: FIP single-step support");
+		goto abort_dump;
+	}
+
+	/*  First try the NIP, if it is Valid:  */
+	cpu->pc = cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_ADDR;
+
+	/*  If the NIP is not valid, then try the FIP:  */
+	if (!(cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_V)) {
+		/*  Neither the NIP nor the FIP valid?  */
+		if (!(cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_V)) {
+			if ((cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_ADDR)
+			    != (cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_ADDR) + 4) {
+				debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+		    		    "rte: TODO: Neither FIP nor NIP has the "
+				    "Valid bit set?!");
+				goto abort_dump;
+			}
+
+			/*  For now, continue anyway, using NIP.  */
+		} else {
+			cpu->pc = cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_ADDR;
+		}
+	} else if (cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_V &&
+	    cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_V &&
+	    (cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_ADDR)
+	    != (cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_ADDR) + 4) {
+		/*
+		 *  The NIP instruction should first be executed (this
+		 *  is the one the exception handler choose to return to),
+		 *  and then the FIP instruction should run (the target
+		 *  of a delayed branch).
+		 */
+
+		uint32_t nip = cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_ADDR;
+		uint32_t fip = cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_ADDR;
+
+		cpu->pc = nip;
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+
+		if (cpu->pc != nip) {
+			debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+			    "NIP execution caused exception?! TODO");
+			goto abort_dump;
+		}
+
+		instr(to_be_translated)(cpu, cpu->cd.m88k.next_ic);
+
+		if ((cpu->pc & 0xfffff000) != (nip & 0xfffff000)) {
+			debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+			    "instruction in delay slot when returning via"
+			    " rte caused an exception?! nip=0x%08x, but pc "
+			    "changed to 0x%08x! TODO", nip, (int)cpu->pc);
+			goto abort_dump;
+		}
+
+		cpu->pc = fip;
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+		return;
+	}
+
+	/*  fatal("RTE: NIP=0x%08" PRIx32", FIP=0x%08" PRIx32"\n",
+	    cpu->cd.m88k.cr[M88K_CR_SNIP], cpu->cd.m88k.cr[M88K_CR_SFIP]);  */
+
+	quick_pc_to_pointers(cpu);
+	return;
+
+abort_dump:
+	debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+	    "rte failed. NIP=0x%08" PRIx32", FIP=0x%08" PRIx32,
+	    cpu->cd.m88k.cr[M88K_CR_SNIP], cpu->cd.m88k.cr[M88K_CR_SFIP]);
+
+	ABORT_EXECUTION;
+}
+
+
+/*
+ *  xmem_slow:  Unoptimized xmem (exchange register with memory)
+ *
+ *  arg[0] = copy of the instruction word
+ *
+ *  NOTE: The alternative would be to extend the load/store instructions
+ *  to also include xmem, and thus implement a "fast" version (where
+ *  the page is already accessible both readable and writable) and a
+ *  generic version. (The generic implementation would then not need to
+ *  have a NO_PC_SYNC flag, since they would always sync.)
+ */
+X(xmem_slow)
+{
+	uint32_t iword = ic->arg[0];
+	uint32_t tmp;
+	int d      = (iword >> 21) & 0x1f;
+	int s1     = (iword >> 16) & 0x1f;
+	int s2     =  iword        & 0x1f;
+	int imm16  =  iword        & 0xffff;
+	int regofs = (iword & 0xf0000000) != 0;
+	int scaled = iword & 0x200;
+	int size   = iword & 0x400;
+	int user   = iword & 0x80;
+	uint32_t pc_before_memory_access;
+	void (*xmem_load)(struct cpu*, struct m88k_instr_call*);
+	void (*xmem_store)(struct cpu*, struct m88k_instr_call*);
+	struct m88k_instr_call call;
+
+	SYNCH_PC;
+	pc_before_memory_access = (uint32_t)cpu->pc;
+
+	if (!regofs) {
+		/*  immediate offset:  */
+		scaled = 0;
+		size = (iword >> 26) & 1;
+		user = 0;
+	}
+
+	tmp = cpu->cd.m88k.r[d];
+
+	xmem_load = m88k_loadstore[ (size? 2 : 0)
+	    + (cpu->byte_order == EMUL_BIG_ENDIAN? M88K_LOADSTORE_ENDIANNESS : 0)
+	    + (scaled? M88K_LOADSTORE_SCALEDNESS : 0)
+	    + (user? M88K_LOADSTORE_USR : 0)
+	    + (regofs? M88K_LOADSTORE_REGISTEROFFSET : 0)
+	    + M88K_LOADSTORE_NO_PC_SYNC ];
+
+	call.f = xmem_load;
+	call.arg[0] = (size_t) &cpu->cd.m88k.r[d];
+	call.arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+	if (regofs)
+		call.arg[2] = (size_t) &cpu->cd.m88k.r[s2];
+	else
+		call.arg[2] = imm16;
+
+	if (d == M88K_ZERO_REG)
+		call.arg[0] = (size_t)&cpu->cd.m88k.zero_scratch;
+
+	xmem_load(cpu, &call);
+
+	// If there was an exception in the load or store call, then the pc
+	// will have changed. Alternatively, one could check for changes in
+	// the transaction registers. (But handling the theoretical tiny risk
+	// that the pc was the same before and after, i.e. that the faulting
+	// instruction was the same as the exception handler, is not worth it.)
+	if ((uint32_t)cpu->pc != pc_before_memory_access) {
+		//printf("xmem_load exception, pc_before_memory_access = %08x\n", pc_before_memory_access);
+		cpu->cd.m88k.dmd[0] = tmp;
+		cpu->cd.m88k.dmt[0] |= DMT_LOCKBAR | DMT_WRITE;
+		cpu->cd.m88k.dmt[0] &= ~((0x1f) << DMT_DREGSHIFT);
+		cpu->cd.m88k.dmt[0] |= d << DMT_DREGSHIFT;
+		return;
+	}
+
+	xmem_store = m88k_loadstore[ (size? 2 : 0)
+	    + M88K_LOADSTORE_STORE
+	    + (cpu->byte_order == EMUL_BIG_ENDIAN? M88K_LOADSTORE_ENDIANNESS : 0)
+	    + (scaled? M88K_LOADSTORE_SCALEDNESS : 0)
+	    + (user? M88K_LOADSTORE_USR : 0)
+	    + (regofs? M88K_LOADSTORE_REGISTEROFFSET : 0)
+	    + M88K_LOADSTORE_NO_PC_SYNC ];
+
+	call.f = xmem_store;
+	call.arg[0] = (size_t) &tmp;
+	// arg[1] and arg[2] are already set up from xmem_load call.
+
+	if (d == M88K_ZERO_REG)
+		tmp = 0;
+
+	xmem_store(cpu, &call);
+
+	// If there was an exception in xmem_store(), then return the d register
+	// to what it was before the xmem_load().
+	if ((uint32_t)cpu->pc != pc_before_memory_access) {
+		//printf("xmem_store exception, pc_before_memory_access = %08x\n", pc_before_memory_access);
+		// cpu->cd.m88k.r[d] = tmp;
+		cpu->cd.m88k.dmd[0] = tmp;
+		cpu->cd.m88k.dmt[0] |= DMT_LOCKBAR | DMT_WRITE;
+		cpu->cd.m88k.dmt[0] &= ~((0x1f) << DMT_DREGSHIFT);
+		cpu->cd.m88k.dmt[0] |= d << DMT_DREGSHIFT;
+		return;
+	}
+}
+
+
+/*
+ *  prom-call:
+ */
+X(prom_call)
+{
+	/*  If executed from user mode, then cause an exception:  */
+	if (!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)) {
+		SYNCH_PC;
+		m88k_exception(cpu, M88K_EXCEPTION_UNIMPLEMENTED_OPCODE, 0);
+		return;
+	}
+
+	switch (cpu->machine->machine_type) {
+
+	case MACHINE_LUNA88K:
+		luna88kprom_emul(cpu);
+		break;
+
+	case MACHINE_MVME88K:
+		mvmeprom_emul(cpu);
+		break;
+
+	default:debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+		    "prom_call: unimplemented machine type");
+		ABORT_EXECUTION;
+	}
+
+	if (!cpu->running) {
+		cpu->n_translated_instrs --;
+		cpu->cd.m88k.next_ic = &nothing_call;
+	}
+}
+
+
+/*
+ *  tb0, tb1:  Trap on bit Clear/Set
+ *
+ *  arg[0] = bitmask to check (e.g. 0x00020000 for bit 17)
+ *  arg[1] = pointer to register s1
+ *  arg[2] = 9-bit vector number
+ */
+X(tb0)
+{
+	SYNCH_PC;
+
+	if (!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)
+	    && ic->arg[2] < M88K_EXCEPTION_USER_TRAPS_START) {
+		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
+		return;
+	}
+
+	if (!(reg(ic->arg[1]) & ic->arg[0]))
+		m88k_exception(cpu, ic->arg[2], 1);
+}
+X(tb1)
+{
+	SYNCH_PC;
+
+	if (!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)
+	    && ic->arg[2] < M88K_EXCEPTION_USER_TRAPS_START) {
+		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
+		return;
+	}
+
+	if (reg(ic->arg[1]) & ic->arg[0])
+		m88k_exception(cpu, ic->arg[2], 1);
+}
+
+
+/*
+ *  idle:
+ *
+ *  s:	ld    rX,rY,ofs
+ *      bcnd  eq0,rX,s
+ */
+X(idle)
+{
+	uint32_t rY = reg(ic[0].arg[1]) + ic[0].arg[2];
+	uint32_t index = rY >> 12;
+	unsigned char *p = cpu->cd.m88k.host_load[index];
+	uint32_t *p32 = (uint32_t *) p;
+	uint32_t v;
+
+	/*  Fallback:  */
+	if (p == NULL || (rY & 3)) {
+		instr(ld_u_4_be)(cpu, ic);
+		return;
+	}
+
+	v = p32[(rY & 0xfff) >> 2];
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		v = LE32_TO_HOST(v);
+	else
+		v = BE32_TO_HOST(v);
+
+	reg(ic[0].arg[0]) = v;
+
+	if (v == 0) {
+		SYNCH_PC;
+		cpu->wants_to_idle = true;
+		cpu->n_translated_instrs += N_DYNTRANS_IDLE_BREAK;
+		cpu->cd.m88k.next_ic = &nothing_call;
+	} else {
+		cpu->n_translated_instrs ++;
+		cpu->cd.m88k.next_ic = &ic[2];
+	}
+}
+
+
+/*
+ *  idle_with_tb1:
+ *
+ *  s:	tb1	bit,r0,vector
+ *	ld	rX,rY,ofs
+ *	bcnd	eq0,rX,s
+ */
+X(idle_with_tb1)
+{
+	uint32_t rY = reg(ic[1].arg[1]) + ic[1].arg[2];
+	uint32_t index = rY >> 12;
+	unsigned char *p = cpu->cd.m88k.host_load[index];
+	uint32_t *p32 = (uint32_t *) p;
+	uint32_t v;
+
+	/*  Fallback:  */
+	if (p == NULL || (rY & 3)) {
+		instr(tb1)(cpu, ic);
+		return;
+	}
+
+	v = p32[(rY & 0xfff) >> 2];
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		v = LE32_TO_HOST(v);
+	else
+		v = BE32_TO_HOST(v);
+
+	reg(ic[1].arg[0]) = v;
+
+	if (v == 0) {
+		SYNCH_PC;
+		cpu->wants_to_idle = true;
+		cpu->n_translated_instrs += N_DYNTRANS_IDLE_BREAK;
+		cpu->cd.m88k.next_ic = &nothing_call;
+	} else {
+		cpu->n_translated_instrs += 2;
+		cpu->cd.m88k.next_ic = &ic[3];
+	}
+}
+
+
+/*****************************************************************************/
+
+
+X(end_of_page)
+{
+	/*  Update the PC:  (offset 0, but on the next page)  */
+	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
+	    M88K_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (M88K_IC_ENTRIES_PER_PAGE << M88K_INSTR_ALIGNMENT_SHIFT);
+
+	/*  end_of_page doesn't count as an executed instruction:  */
+	cpu->n_translated_instrs --;
+
+	/*
+	 *  Find the new physpage and update translation pointers.
+	 *
+	 *  Note: This may cause an exception, if e.g. the new page is
+	 *  not accessible.
+	 */
+	quick_pc_to_pointers(cpu);
+
+	/*  Simple jump to the next page (if we are lucky):  */
+	if (cpu->delay_slot == NOT_DELAYED)
+		return;
+
+	/*
+	 *  If we were in a delay slot, and we got an exception while doing
+	 *  quick_pc_to_pointers, then return. The function which called
+	 *  end_of_page should handle this case.
+	 */
+	if (cpu->delay_slot == EXCEPTION_IN_DELAY_SLOT)
+		return;
+
+	/*
+	 *  Tricky situation; the delay slot is on the next virtual page.
+	 *  Calling to_be_translated will translate one instruction manually,
+	 *  execute it, and then discard it.
+	 */
+	/*  fatal("[ end_of_page: delay slot across page boundary! ]\n");  */
+
+	instr(to_be_translated)(cpu, cpu->cd.m88k.next_ic);
+
+	/*  The instruction in the delay slot has now executed.  */
+	/*  fatal("[ end_of_page: back from executing the delay slot, %i ]\n",
+	    cpu->delay_slot);  */
+
+	/*  Find the physpage etc of the instruction in the delay slot
+	    (or, if there was an exception, the exception handler):  */
+	quick_pc_to_pointers(cpu);
+}
+
+
+X(end_of_page2)
+{
+	/*  Synchronize PC on the _second_ instruction on the next page:  */
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page)
+	    / sizeof(struct m88k_instr_call);
+	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1)
+	    << M88K_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << M88K_INSTR_ALIGNMENT_SHIFT);
+
+	if (low_pc < 0 || low_pc > ((M88K_IC_ENTRIES_PER_PAGE+1)
+	    << M88K_INSTR_ALIGNMENT_SHIFT)) {
+		printf("[ end_of_page2: HUH? low_pc=%i, cpu->pc = %08"
+		    PRIx32" ]\n", low_pc, (uint32_t) cpu->pc);
+	}
+
+	/*  This doesn't count as an executed instruction.  */
+	cpu->n_translated_instrs --;
+
+	quick_pc_to_pointers(cpu);
+
+	if (cpu->delay_slot == NOT_DELAYED)
+		return;
+
+	debugmsg_cpu(cpu, SUBSYS_CPU, "m88k", VERBOSITY_ERROR,
+	    "end_of_page2: fatal error, we're in a delay slot");
+	ABORT_EXECUTION;
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  Idle loop detection, e.g.:
+ *
+ *  s00028d44: 15b7d650	ld	r13,r23,0xd650	    ; [<_sched_whichqs>]
+ *  s00028d48: e84dffff	bcnd	eq0,r13,0x00028d44  ; <_sched_idle+0xc4>
+ *
+ *  or
+ *
+ *  s00079d78: f020d8ff	tb1	1,r0,0xff
+ *  s00079d7c: 15ac7320	ld	r13,r12,0x7320	; [<_sched_whichqs>]
+ *  s00079d80: e84dfffe	bcnd	eq0,r13,0x00079d78	; <_sched_idle+0x158>
+ *
+ *  or
+ *
+ *  s00244840: f020d8ff	tb1	1,r0,0xff
+ *  s00244844: 15b80168	ld	r13,r24,0x168	; [<m88k_cpus+0x1b0>]
+ *  s00244848: ec4dfffe	bcnd.n	eq0,r13,0x00244840	; <sched_idle+0x100>
+ *  s0024484c: 5853fd80 (d)	or	r2,r19,0xfd80
+ */
+void COMBINE(idle)(struct cpu *cpu, struct m88k_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> M88K_INSTR_ALIGNMENT_SHIFT)
+	    & (M88K_IC_ENTRIES_PER_PAGE-1);
+	if (n_back < 2)
+		return;
+
+	if (ic[0].f == instr(bcnd_samepage_eq0) &&
+	    ic[0].arg[2] == (size_t) &ic[-1] &&
+	    ic[-1].f == instr(ld_u_4_be) &&
+	    ic[0].arg[0] == ic[-1].arg[0] &&
+	    ic[0].arg[0] != (size_t) &cpu->cd.m88k.r[M88K_ZERO_REG]) {
+		ic[-1].f = instr(idle);
+		return;
+	}
+
+	if (ic[0].f == instr(bcnd_samepage_eq0) &&
+	    ic[0].arg[2] == (size_t) &ic[-2] &&
+	    ic[-2].f == instr(tb1) &&
+	    ic[-2].arg[1] == (size_t) &cpu->cd.m88k.r[M88K_ZERO_REG] &&
+	    ic[-1].f == instr(ld_u_4_be) &&
+	    ic[0].arg[0] == ic[-1].arg[0] &&
+	    ic[0].arg[0] != (size_t) &cpu->cd.m88k.r[M88K_ZERO_REG]) {
+		ic[-2].f = instr(idle_with_tb1);
+		return;
+	}
+
+	// NOTE: In this case, we are only checking the tb1, the ld, and
+	// the bcnd.n instruction. It actually executes the instruction after
+	// it: hopefully it is an 'or', but in principle it could be anything.
+	// Here we take a chance and hope that it is not something weird that
+	// would cause an exception. (It is unlikely that this particular loop
+	// construct, used for idle loops, would have something else after it.)
+	if (ic[0].f == instr(bcnd_n_eq0) &&
+	    ic[0].arg[2] == (size_t) low_addr - 8 &&
+	    ic[-2].f == instr(tb1) &&
+	    ic[-2].arg[1] == (size_t) &cpu->cd.m88k.r[M88K_ZERO_REG] &&
+	    ic[-1].f == instr(ld_u_4_be) &&
+	    ic[0].arg[0] == ic[-1].arg[0] &&
+	    ic[0].arg[0] != (size_t) &cpu->cd.m88k.r[M88K_ZERO_REG]) {
+		ic[-2].f = instr(idle_with_tb1);
+		// printf("NEW IDLE using bcnd.n!!!\n");
+		return;
+	}
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  m88k_instr_to_be_translated():
+ *
+ *  Translate an instruction word into a m88k_instr_call. ic is filled in with
+ *  valid data for the translated instruction, or a "nothing" instruction if
+ *  there was a translation failure. The newly translated instruction is then
+ *  executed.
+ */
+X(to_be_translated)
+{
+	uint32_t addr, low_pc, iword;
+	unsigned char *page;
+	unsigned char ib[4];
+	uint32_t op26, op10, op11, d, s1, s2, cr6, imm16;
+	int32_t d16, d26; //, simm16;
+	int offset, shift;
+	int in_crosspage_delayslot = 0;
+	void (*samepage_function)(struct cpu *, struct m88k_instr_call *)=NULL;
+
+	/*  Figure out the (virtual) address of the instruction:  */
+	low_pc = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page)
+	    / sizeof(struct m88k_instr_call);
+
+	/*  Special case for branch with delayslot on the next page:  */
+	if (cpu->delay_slot == TO_BE_DELAYED && low_pc == 0) {
+		/*  fatal("[ delay-slot translation across page "
+		    "boundary ]\n");  */
+		in_crosspage_delayslot = 1;
+	}
+
+	addr = cpu->pc & ~((M88K_IC_ENTRIES_PER_PAGE-1)
+	    << M88K_INSTR_ALIGNMENT_SHIFT);
+	addr += (low_pc << M88K_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc = (uint32_t)addr;
+	addr &= ~((1 << M88K_INSTR_ALIGNMENT_SHIFT) - 1);
+
+	/*  Read the instruction word from memory:  */
+	page = cpu->cd.m88k.host_load[(uint32_t)addr >> 12];
+
+	if (page != NULL) {
+		/*  fatal("TRANSLATION HIT!\n");  */
+		memcpy(ib, page + (addr & 0xffc), sizeof(ib));
+	} else {
+		/*  fatal("TRANSLATION MISS!\n");  */
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
+		    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
+			fatal("to_be_translated(): read failed: TODO\n");
+			goto bad;
+		}
+	}
+
+	{
+		uint32_t *p = (uint32_t *) ib;
+		iword = *p;
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iword = LE32_TO_HOST(iword);
+	else
+		iword = BE32_TO_HOST(iword);
+
+
+#define DYNTRANS_TO_BE_TRANSLATED_HEAD
+#include "cpu_dyntrans.c"
+#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD
+
+
+	/*
+	 *  Translate the instruction:
+ 	 *
+	 *  NOTE: _NEVER_ allow writes to the zero register; all instructions
+	 *  that use the zero register as their destination should be treated
+	 *  as NOPs, except those that access memory (they should use the
+	 *  scratch register instead).
+	 */
+	if (cpu->cd.m88k.r[M88K_ZERO_REG] != 0) {
+		debugmsg_cpu(cpu, SUBSYS_CPU, "to_be_translated", VERBOSITY_ERROR,
+		    "INTERNAL ERROR! M88K_ZERO_REG != 0");
+		cpu->running = false;
+		goto bad;
+	}
+
+	op26   = (iword >> 26) & 0x3f;
+	op11   = (iword >> 11) & 0x1f;
+	op10   = (iword >> 10) & 0x3f;
+	d      = (iword >> 21) & 0x1f;
+	s1     = (iword >> 16) & 0x1f;
+	s2     =  iword        & 0x1f;
+	imm16  =  iword        & 0xffff;
+	// simm16 = (int16_t) (iword & 0xffff);
+	cr6    = (iword >>  5) & 0x3f;
+	d16    = ((int16_t) (iword & 0xffff)) * 4;
+	d26    = ((int32_t)((iword & 0x03ffffff) << 6)) >> 4;
+
+	switch (op26) {
+
+	case 0x00:
+	case 0x01:
+		ic->f = instr(xmem_slow);
+		ic->arg[0] = iword;
+		if (d == M88K_ZERO_REG)
+			ic->f = instr(nop);
+		if (iword == 0)
+			goto bad;
+		break;
+
+	case 0x02:	/*  ld.hu  */
+	case 0x03:	/*  ld.bu  */
+	case 0x04:	/*  ld.d   */
+	case 0x05:	/*  ld     */
+	case 0x06:	/*  ld.h   */
+	case 0x07:	/*  ld.b   */
+	case 0x08:	/*  st.d   */
+	case 0x09:	/*  st     */
+	case 0x0a:	/*  st.h   */
+	case 0x0b:	/*  st.b   */
+		{
+			int store = 0, signedness = 0, opsize = 0;
+
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[2] = imm16;
+
+			switch (op26) {
+			case 0x02: opsize = 1; break;
+			case 0x03: opsize = 0; break;
+			case 0x04: opsize = 3; break;
+			case 0x05: opsize = 2; break;
+			case 0x06: opsize = 1; signedness = 1; break;
+			case 0x07: opsize = 0; signedness = 1; break;
+			case 0x08: store = 1; opsize = 3; break;
+			case 0x09: store = 1; opsize = 2; break;
+			case 0x0a: store = 1; opsize = 1; break;
+			case 0x0b: store = 1; opsize = 0; break;
+			}
+
+			if (opsize == 3 && d == 31) {
+				fatal("m88k load/store of register pair r31/r0"
+				    " is not yet implemented\n");
+				goto bad;
+			}
+
+			ic->f = m88k_loadstore[ opsize
+			    + (store? M88K_LOADSTORE_STORE : 0)
+			    + (signedness? M88K_LOADSTORE_SIGNEDNESS:0)
+			    + (cpu->byte_order == EMUL_BIG_ENDIAN?
+			       M88K_LOADSTORE_ENDIANNESS : 0) ];
+
+			if (!store && d == 0)
+				ic->arg[0] = (size_t) &cpu->cd.m88k.zero_scratch;
+		}
+		break;
+
+	case 0x10:	/*  and    imm  */
+	case 0x11:	/*  and.u  imm  */
+	case 0x12:	/*  mask   imm  */
+	case 0x13:	/*  mask.u imm  */
+	case 0x14:	/*  xor    imm  */
+	case 0x15:	/*  xor.u  imm  */
+	case 0x16:	/*  or     imm  */
+	case 0x17:	/*  or.u   imm  */
+	case 0x18:	/*  addu   imm  */
+	case 0x19:	/*  subu   imm  */
+	case 0x1a:	/*  divu   imm  */
+	case 0x1b:	/*  mulu   imm  */
+	case 0x1c:	/*  add    imm  */
+	case 0x1d:	/*  sub    imm  */
+	case 0x1e:	/*  div    imm  */
+	case 0x1f:	/*  cmp    imm  */
+		shift = 0;
+		switch (op26) {
+		case 0x10: ic->f = instr(and_imm); break;
+		case 0x11: ic->f = instr(and_u_imm); shift = 16; break;
+		case 0x12: ic->f = instr(mask_imm); break;
+		case 0x13: ic->f = instr(mask_imm); shift = 16; break;
+		case 0x14: ic->f = instr(xor_imm); break;
+		case 0x15: ic->f = instr(xor_imm); shift = 16; break;
+		case 0x16: ic->f = instr(or_imm); break;
+		case 0x17: ic->f = instr(or_imm); shift = 16; break;
+		case 0x18: ic->f = instr(addu_imm); break;
+		case 0x19: ic->f = instr(subu_imm); break;
+		case 0x1a: ic->f = instr(divu_imm); break;
+		case 0x1b: ic->f = instr(mulu_imm); break;
+		case 0x1c: ic->f = instr(add_imm); break;
+		case 0x1d: ic->f = instr(sub_imm); break;
+		case 0x1e: ic->f = instr(div_imm); break;
+		case 0x1f: ic->f = instr(cmp_imm); break;
+		}
+
+		ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+		ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+		ic->arg[2] = imm16 << shift;
+
+		/*  Optimization for  or d,r0,imm  and similar  */
+		if (s1 == M88K_ZERO_REG && ic->f == instr(or_imm)) {
+			if (ic->arg[2] == 0)
+				ic->f = instr(or_r0_imm0);
+			else
+				ic->f = instr(or_r0_imm);
+		}
+		if (ic->arg[2] == 0 && ic->f == instr(addu_imm))
+			ic->f = instr(addu_s2r0);
+
+		if (d == s1 && ic->arg[2] == 1) {
+			if (ic->f == instr(addu_imm))
+				ic->f = instr(inc_reg);
+			if (ic->f == instr(subu_imm))
+				ic->f = instr(dec_reg);
+		}
+
+		if (d == M88K_ZERO_REG)
+			ic->f = instr(nop);
+		break;
+
+	case 0x20:
+		if ((iword & 0x001ff81f) == 0x00004000) {
+			ic->f = instr(ldcr);
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = cr6;
+			if (d == M88K_ZERO_REG)
+				ic->arg[0] = (size_t)
+				    &cpu->cd.m88k.zero_scratch;
+		} else if ((iword & 0x001ff81f) == 0x00004800) {
+			ic->f = instr(fldcr);
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = cr6;
+			if (d == M88K_ZERO_REG)
+				ic->arg[0] = (size_t)
+				    &cpu->cd.m88k.zero_scratch;
+		} else if ((iword & 0x03e0f800) == 0x00008000) {
+			ic->f = instr(stcr);
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[1] = cr6;
+			if (s1 != s2)
+				goto bad;
+		} else if ((iword & 0x03e0f800) == 0x00008800) {
+			ic->f = instr(fstcr);
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[1] = cr6;
+			if (s1 != s2)
+				goto bad;
+		} else if ((iword & 0x0000f800) == 0x0000c000) {
+			ic->f = instr(xcr);
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[2] = cr6;
+			if (s1 != s2)
+				goto bad;
+		} else
+			goto bad;
+		break;
+
+	case 0x21:
+		switch (op11) {
+
+		case 0x00:	/*  fmul  */
+			if (d == 0) {
+				/*  d = 0 isn't allowed. for now, let's abort execution.  */
+				fatal("TODO: exception for d = 0 in fmul.xxx instruction\n");
+				goto bad;
+			}
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
+			switch ((iword >> 5) & 0x3f) {
+			case 0x00:	ic->f = instr(fmul_sss); break;
+			case 0x01:	ic->f = instr(fmul_dss); break;
+			case 0x05:	ic->f = instr(fmul_dsd); break;
+			case 0x11:	ic->f = instr(fmul_dds); break;
+			case 0x15:	ic->f = instr(fmul_ddd); break;
+			default:if (!cpu->translation_readahead)
+					fatal("Unimplemented fmul combination 0x%x.\n",
+					    (iword >> 5) & 0x3f);
+				goto bad;
+			}
+			break;
+
+		case 0x04:	/*  flt  */
+			if (d == 0) {
+				/*  d = 0 isn't allowed. for now, let's abort execution.  */
+				fatal("TODO: exception for d = 0 in flt.xx instruction\n");
+				goto bad;
+			}
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s2];
+			if ((iword >> 5) & 1) {
+				ic->f = instr(flt_ds);
+				if (d & 1) {
+					fatal("TODO: double precision load into uneven register r%i?\n", d);
+					goto bad;
+				}
+			} else {
+				ic->f = instr(flt_ss);
+			}
+			break;
+
+		case 0x05:	/*  fadd  */
+			if (d == 0) {
+				/*  d = 0 isn't allowed. for now, let's abort execution.  */
+				fatal("TODO: exception for d = 0 in fadd.xxx instruction\n");
+				goto bad;
+			}
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
+			switch ((iword >> 5) & 0x3f) {
+			case 0x00:	ic->f = instr(fadd_sss); break;
+			case 0x01:	ic->f = instr(fadd_dss); break;
+			case 0x05:	ic->f = instr(fadd_dsd); break;
+			case 0x11:	ic->f = instr(fadd_dds); break;
+			case 0x15:	ic->f = instr(fadd_ddd); break;
+			default:if (!cpu->translation_readahead)
+					fatal("Unimplemented fadd combination 0x%x.\n",
+					    (iword >> 5) & 0x3f);
+				goto bad;
+			}
+			break;
+
+		case 0x06:	/*  fsub  */
+			if (d == 0) {
+				/*  d = 0 isn't allowed. for now, let's abort execution.  */
+				fatal("TODO: exception for d = 0 in fsub.xxx instruction\n");
+				goto bad;
+			}
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
+			switch ((iword >> 5) & 0x3f) {
+			case 0x00:	ic->f = instr(fsub_sss); break;
+			case 0x01:	ic->f = instr(fsub_dss); break;
+			case 0x05:	ic->f = instr(fsub_dsd); break;
+			case 0x10:	ic->f = instr(fsub_sds); break;
+			case 0x11:	ic->f = instr(fsub_dds); break;
+			case 0x15:	ic->f = instr(fsub_ddd); break;
+			default:if (!cpu->translation_readahead)
+					fatal("Unimplemented fsub combination 0x%x.\n",
+					    (iword >> 5) & 0x3f);
+				goto bad;
+			}
+			break;
+
+		case 0x07:	/*  fcmp  */
+			if (d == 0) {
+				/*  d = 0 isn't allowed. for now, let's abort execution.  */
+				fatal("TODO: exception for d = 0 in fcmp.xxx instruction\n");
+				goto bad;
+			}
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
+			switch ((iword >> 5) & 0x3f) {
+			case 0x00:	ic->f = instr(fcmp_sss); break;
+			case 0x04:	ic->f = instr(fcmp_ssd); break;
+			case 0x10:	ic->f = instr(fcmp_sds); break;
+			case 0x14:	ic->f = instr(fcmp_sdd); break;
+			default:if (!cpu->translation_readahead)
+					fatal("Unimplemented fcmp combination 0x%x.\n",
+					    (iword >> 5) & 0x3f);
+				goto bad;
+			}
+			break;
+
+		case 0x0b:	/*  trnc  */
+			if (d == 0) {
+				/*  d = 0 isn't allowed. for now, let's abort execution.  */
+				fatal("TODO: exception for d = 0 in trnc.xx instruction\n");
+				goto bad;
+			}
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s2];
+			if ((iword >> 7) & 1) {
+				ic->f = instr(trnc_sd);
+				if (s2 & 1) {
+					fatal("TODO: double precision truncation into uneven register r%i?\n", d);
+					goto bad;
+				}
+			} else {
+				ic->f = instr(trnc_ss);
+			}
+			break;
+
+		case 0x0e:	/*  fdiv  */
+			if (d == 0) {
+				/*  d = 0 isn't allowed. for now, let's abort execution.  */
+				fatal("TODO: exception for d = 0 in fdiv.xxx instruction\n");
+				goto bad;
+			}
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
+			switch ((iword >> 5) & 0x3f) {
+			case 0x00:	ic->f = instr(fdiv_sss); break;
+			case 0x01:	ic->f = instr(fdiv_dss); break;
+			case 0x05:	ic->f = instr(fdiv_dsd); break;
+			case 0x15:	ic->f = instr(fdiv_ddd); break;
+			default:if (!cpu->translation_readahead)
+					fatal("Unimplemented fdiv combination 0x%x.\n",
+					    (iword >> 5) & 0x3f);
+				goto bad;
+			}
+			break;
+
+		default:goto bad;
+		}
+		break;
+
+	case 0x30:	/*  br     */
+	case 0x31:	/*  br.n   */
+	case 0x32:	/*  bsr    */
+	case 0x33:	/*  bsr.n  */
+		switch (op26) {
+		case 0x30:
+			ic->f = instr(br);
+			samepage_function = instr(br_samepage);
+			if (cpu->translation_readahead > 1)
+				cpu->translation_readahead = 1;
+			break;
+		case 0x31:
+			ic->f = instr(br_n);
+			if (cpu->translation_readahead > 2)
+				cpu->translation_readahead = 2;
+			break;
+		case 0x32:
+			ic->f = instr(bsr);
+			samepage_function = instr(bsr_samepage);
+			break;
+		case 0x33:
+			ic->f = instr(bsr_n);
+			break;
+		}
+
+		offset = (addr & 0xffc) + d26;
+
+		/*  Prepare both samepage and offset style args.
+		    (Only one will be used in the actual instruction.)  */
+		ic->arg[0] = (size_t) ( cpu->cd.m88k.cur_ic_page +
+		    (offset >> M88K_INSTR_ALIGNMENT_SHIFT) );
+		ic->arg[1] = offset;
+		ic->arg[2] = (addr & 0xffc) + 4;    /*  Return offset
+							for bsr_samepage  */
+
+		if (offset >= 0 && offset <= 0xffc &&
+		    samepage_function != NULL)
+			ic->f = samepage_function;
+
+		if (cpu->machine->show_trace_tree) {
+			if (op26 == 0x32)
+				ic->f = instr(bsr_trace);
+			if (op26 == 0x33)
+				ic->f = instr(bsr_n_trace);
+		}
+
+		break;
+
+	case 0x34:	/*  bb0     */
+	case 0x35:	/*  bb0.n   */
+	case 0x36:	/*  bb1     */
+	case 0x37:	/*  bb1.n   */
+		switch (op26) {
+		case 0x34:
+			ic->f = instr(bb0);
+			samepage_function = instr(bb0_samepage);
+			break;
+		case 0x35:
+			ic->f = instr(bb0_n);
+			break;
+		case 0x36:
+			ic->f = instr(bb1);
+			samepage_function = instr(bb1_samepage);
+			break;
+		case 0x37:
+			ic->f = instr(bb1_n);
+			break;
+		}
+
+		ic->arg[0] = (size_t) &cpu->cd.m88k.r[s1];
+		ic->arg[1] = (uint32_t) (1 << d);
+
+		offset = (addr & 0xffc) + d16;
+		ic->arg[2] = offset;
+
+		if (offset >= 0 && offset <= 0xffc &&
+		    samepage_function != NULL) {
+			ic->f = samepage_function;
+			ic->arg[2] = (size_t) ( cpu->cd.m88k.cur_ic_page +
+			    (offset >> M88K_INSTR_ALIGNMENT_SHIFT) );
+		}
+		break;
+
+	case 0x3a:	/*  bcnd    */
+	case 0x3b:	/*  bcnd.n  */
+		ic->f = m88k_bcnd[d + 32 * (op26 & 1)];
+		samepage_function = m88k_bcnd[64 + d + 32 * (op26 & 1)];
+
+		if (ic->f == NULL)
+			goto bad;
+
+		ic->arg[0] = (size_t) &cpu->cd.m88k.r[s1];
+
+		offset = (addr & 0xffc) + d16;
+		ic->arg[2] = offset;
+
+		if (offset >= 0 && offset <= 0xffc &&
+		    samepage_function != NULL) {
+			ic->f = samepage_function;
+			ic->arg[2] = (size_t) ( cpu->cd.m88k.cur_ic_page +
+			    (offset >> M88K_INSTR_ALIGNMENT_SHIFT) );
+		}
+
+		if ((iword & 0xffe0ffff) == 0xe840ffff ||
+		    (iword & 0xffe0ffff) == 0xe840fffe ||
+		    (iword & 0xffe0ffff) == 0xec40fffe)
+			cpu->cd.m88k.combination_check = COMBINE(idle);
+
+		break;
+
+	case 0x3c:
+		switch (op10) {
+
+		case 0x20:	/*  clr  */
+		case 0x22:	/*  set  */
+		case 0x24:	/*  ext  */
+		case 0x26:	/*  extu  */
+		case 0x28:	/*  mak  */
+		case 0x2a:	/*  rot  */
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[2] = iword & 0x3ff;
+
+			switch (op10) {
+			case 0x20: ic->f = instr(mask_imm);
+				   {
+					int w = ic->arg[2] >> 5;
+					int o = ic->arg[2] & 0x1f;
+					uint32_t x = w == 0? 0xffffffff
+					    : ((uint32_t)1 << w) - 1;
+					x <<= o;
+					ic->arg[2] = ~x;
+				   }
+				   break;
+			case 0x22: ic->f = instr(or_imm);
+				   {
+					int w = ic->arg[2] >> 5;
+					int o = ic->arg[2] & 0x1f;
+					uint32_t x = w == 0? 0xffffffff
+					    : ((uint32_t)1 << w) - 1;
+					x <<= o;
+					ic->arg[2] = x;
+				   }
+				   break;
+			case 0x24: ic->f = instr(ext_imm); break;
+			case 0x26: ic->f = instr(extu_imm); break;
+			case 0x28: ic->f = instr(mak_imm); break;
+			case 0x2a: ic->f = instr(rot_imm); break;
+			}
+
+			if (d == M88K_ZERO_REG)
+				ic->f = instr(nop);
+			break;
+
+		case 0x34:	/*  tb0  */
+		case 0x36:	/*  tb1  */
+			ic->arg[0] = 1 << d;
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[2] = iword & 0x1ff;
+			switch (op10) {
+			case 0x34: ic->f = instr(tb0); break;
+			case 0x36: ic->f = instr(tb1); break;
+			}
+			break;
+
+		default:goto bad;
+		}
+		break;
+
+	case 0x3d:
+		if ((iword & 0xf000) <= 0x3fff ) {
+			/*  Load, Store, xmem, and lda:  */
+			int op = 0, opsize, user = 0, wt = 0;
+			int signedness = 1, scaled = 0;
+
+			switch (iword & 0xf000) {
+			case 0x2000: op = 1; /* st */  break;
+			case 0x3000: op = 2; /* lda */ break;
+			default:     if ((iword & 0xf800) >= 0x0800)
+					op = 0; /* ld */
+				     else
+					op = 3; /* xmem */
+			}
+
+			/*  for (most) ld, st, lda:  */
+			opsize = (iword >> 10) & 3;
+
+			/*  Turn opsize into x, where size = 1 << x:  */
+			opsize = 3 - opsize;
+
+			if (op == 3) {
+				/*  xmem:  */
+				switch ((iword >> 10) & 3) {
+				case 0: opsize = 0; break;
+				case 1: opsize = 2; break;
+				default:fatal("Weird xmem opsize/type?\n");
+					goto bad;
+				}
+			} else {
+				if ((iword & 0xf800) == 0x800) {
+					signedness = 0;
+					if ((iword & 0xf00) < 0xc00)
+						opsize = 1;
+					else
+						opsize = 0;
+				} else {
+					if (opsize >= 2 || op == 1)
+						signedness = 0;
+				}
+			}
+
+			if (iword & 0x100)
+				user = 1;
+			if (iword & 0x80)
+				wt = 1;
+			if (iword & 0x200)
+				scaled = 1;
+
+			if (wt) {
+				fatal("wt bit not yet implemented! TODO\n");
+				goto bad;
+			}
+
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
+
+			if (op == 0 || op == 1) {
+				/*  ld or st:  */
+				ic->f = m88k_loadstore[ opsize
+				    + (op==1? M88K_LOADSTORE_STORE : 0)
+				    + (signedness? M88K_LOADSTORE_SIGNEDNESS:0)
+				    + (cpu->byte_order == EMUL_BIG_ENDIAN?
+				       M88K_LOADSTORE_ENDIANNESS : 0)
+				    + (scaled? M88K_LOADSTORE_SCALEDNESS : 0)
+				    + (user? M88K_LOADSTORE_USR : 0)
+				    + M88K_LOADSTORE_REGISTEROFFSET ];
+
+				if (d == M88K_ZERO_REG && op == 0)
+					ic->arg[0] = (size_t)&cpu->cd.m88k.zero_scratch;
+
+				if (opsize == 3 && d == 31) {
+					fatal("m88k load/store of register "
+					    "pair r31/r0: TODO\n");
+					goto bad;
+				}
+			} else if (op == 2) {
+				/*  lda:  */
+				if (scaled) {
+					switch (opsize) {
+					case 0: ic->f = instr(addu); break;
+					case 1: ic->f = instr(lda_reg_2); break;
+					case 2: ic->f = instr(lda_reg_4); break;
+					case 3: ic->f = instr(lda_reg_8); break;
+					}
+				} else {
+					ic->f = instr(addu);
+				}
+				if (d == M88K_ZERO_REG)
+					ic->f = instr(nop);
+			} else {
+				/*  xmem:  */
+				ic->f = instr(xmem_slow);
+				ic->arg[0] = iword;
+				if (d == M88K_ZERO_REG)
+					ic->f = instr(nop);
+			}
+		} else switch ((iword >> 8) & 0xff) {
+		case 0x40:	/*  and    */
+		case 0x44:	/*  and.c  */
+		case 0x50:	/*  xor    */
+		case 0x54:	/*  xor.c  */
+		case 0x58:	/*  or     */
+		case 0x5c:	/*  or.c   */
+		case 0x60:	/*  addu   */
+		case 0x61:	/*  addu.co  */
+		case 0x62:	/*  addu.ci  */
+		case 0x63:	/*  addu.cio */
+		case 0x64:	/*  subu   */
+		case 0x65:	/*  subu.co  */
+		case 0x66:	/*  subu.ci  */
+		case 0x67:	/*  subu.cio */
+		case 0x68:	/*  divu   */
+		case 0x6c:	/*  mul    */
+		case 0x70:	/*  add    */
+		case 0x78:	/*  div    */
+		case 0x7c:	/*  cmp    */
+		case 0x80:	/*  clr    */
+		case 0x88:	/*  set    */
+		case 0x90:	/*  ext    */
+		case 0x98:	/*  extu   */
+		case 0xa0:	/*  mak    */
+		case 0xa8:	/*  rot    */
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
+			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
+
+			switch ((iword >> 8) & 0xff) {
+			case 0x40: ic->f = instr(and);   break;
+			case 0x44: ic->f = instr(and_c); break;
+			case 0x50: ic->f = instr(xor);   break;
+			case 0x54: ic->f = instr(xor_c); break;
+			case 0x58: ic->f = instr(or);    break;
+			case 0x5c: ic->f = instr(or_c);  break;
+			case 0x60: ic->f = instr(addu);  break;
+			case 0x61: ic->f = instr(addu_co); break;
+			case 0x62: ic->f = instr(addu_ci); break;
+			case 0x63: ic->f = instr(addu_cio); break;
+			case 0x64: ic->f = instr(subu);  break;
+			case 0x65: ic->f = instr(subu_co); break;
+			case 0x66: ic->f = instr(subu_ci); break;
+			case 0x67: ic->f = instr(subu_cio); break;
+			case 0x68: ic->f = instr(divu);  break;
+			case 0x6c: ic->f = instr(mul);   break;
+			case 0x70: ic->f = instr(add);   break;
+			case 0x78: ic->f = instr(div);   break;
+			case 0x7c: ic->f = instr(cmp);   break;
+			case 0x80: ic->f = instr(clr);   break;
+			case 0x88: ic->f = instr(set);   break;
+			case 0x90: ic->f = instr(ext);   break;
+			case 0x98: ic->f = instr(extu);  break;
+			case 0xa0: ic->f = instr(mak);   break;
+			case 0xa8: ic->f = instr(rot);   break;
+			}
+
+			/*  Optimization for  or rX,r0,rY  etc:  */
+			if (s1 == M88K_ZERO_REG && ic->f == instr(or))
+				ic->f = instr(or_r0);
+			if (s2 == M88K_ZERO_REG && ic->f == instr(addu))
+				ic->f = instr(addu_s2r0);
+
+			/*
+			 *  Handle the case when the destination register is r0:
+			 *
+			 *  If there is NO SIDE-EFFECT! (i.e. no carry out),
+			 *  then replace the instruction with a nop. If there is
+			 *  a side-effect, we still have to run the instruction,
+			 *  so replace the destination register with a scratch
+			 *  register.
+			 */
+			if (d == M88K_ZERO_REG) {
+				int opc = (iword >> 8) & 0xff;
+				if (opc != 0x61 /* addu.co */ && opc != 0x63 /* addu.cio */ &&
+				    opc != 0x65 /* subu.co */ && opc != 0x67 /* subu.cio */ &&
+				    opc != 0x71 /*  add.co */ && opc != 0x73 /*  add.cio */ &&
+				    opc != 0x75 /*  sub.co */ && opc != 0x77 /*  sub.cio */ &&
+				    opc != 0x68 /*  divu   */ && opc != 0x69 /* divu.d   */ &&
+				    opc != 0x6c /*  mul    */ && opc != 0x6d /* mulu.d   */ &&
+				    opc != 0x6e /*  muls   */ && opc != 0x78 /*  div     */)
+					ic->f = instr(nop);
+				else
+					ic->arg[0] = (size_t)
+					    &cpu->cd.m88k.zero_scratch;
+			}
+			break;
+		case 0xc0:	/*  jmp    */
+		case 0xc4:	/*  jmp.n  */
+		case 0xc8:	/*  jsr    */
+		case 0xcc:	/*  jsr.n  */
+			switch ((iword >> 8) & 0xff) {
+			case 0xc0: ic->f = instr(jmp);
+				   if (cpu->translation_readahead > 1)
+					cpu->translation_readahead = 1;
+				   break;
+			case 0xc4: ic->f = instr(jmp_n);
+				   if (cpu->translation_readahead > 2)
+					cpu->translation_readahead = 2;
+				   break;
+			case 0xc8: ic->f = instr(jsr); break;
+			case 0xcc: ic->f = instr(jsr_n); break;
+			}
+
+			ic->arg[1] = (addr & 0xffc) + 4;
+			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
+
+			if (((iword >> 8) & 0x04) == 0x04)
+				ic->arg[1] = (addr & 0xffc) + 8;
+
+			if (cpu->machine->show_trace_tree &&
+			    s2 == M88K_RETURN_REG) {
+				if (ic->f == instr(jmp))
+					ic->f = instr(jmp_trace);
+				if (ic->f == instr(jmp_n))
+					ic->f = instr(jmp_n_trace);
+			}
+			if (cpu->machine->show_trace_tree) {
+				if (ic->f == instr(jsr))
+					ic->f = instr(jsr_trace);
+				if (ic->f == instr(jsr_n))
+					ic->f = instr(jsr_n_trace);
+			}
+			break;
+		case 0xe8:	/*  ff1  */
+		case 0xec:      /*  ff0  */
+			switch ((iword >> 8) & 0xff) {
+			case 0xe8: ic->f = instr(ff1); break;
+			case 0xec: ic->f = instr(ff0); break;
+			}
+
+			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
+			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
+
+			if (d == M88K_ZERO_REG)
+				ic->f = instr(nop);
+			break;
+		case 0xfc:
+			switch (iword & 0xff) {
+			case 0x00:
+				if (iword == 0xf400fc00)
+					ic->f = instr(rte);
+				else {
+					fatal("unimplemented rte variant: 0x%08" PRIx32"\n", iword);
+					goto bad;
+				}
+				break;
+			case (M88K_PROM_INSTR & 0xff):
+				ic->f = instr(prom_call);
+				break;
+			default:fatal("Unimplemented 3d/fc instruction\n");
+				goto bad;
+			}
+			break;
+		default:goto bad;
+		}
+		break;
+
+	default:goto bad;
+	}
+
+
+#define	DYNTRANS_TO_BE_TRANSLATED_TAIL
+#include "cpu_dyntrans.c" 
+#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_m88k_instr.cc gxemul-0.7.0+dfsg/src/cpus/cpu_m88k_instr.cc
--- gxemul-0.6.2/src/cpus/cpu_m88k_instr.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_m88k_instr.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,2731 +0,0 @@
-/*
- *  Copyright (C) 2007-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  M88K instructions.
- *
- *  Individual functions should keep track of cpu->n_translated_instrs.
- *  (If no instruction was executed, then it should be decreased. If, say, 4
- *  instructions were combined into one function and executed, then it should
- *  be increased by 3.)
- */
-
-
-#define SYNCH_PC                {                                       \
-                int low_pc = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page) \
-                    / sizeof(struct m88k_instr_call);                   \
-                cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1)               \
-                    << M88K_INSTR_ALIGNMENT_SHIFT);                     \
-                cpu->pc += (low_pc << M88K_INSTR_ALIGNMENT_SHIFT);      \
-        }
-
-#define	ABORT_EXECUTION	  {	SYNCH_PC;				\
-				fatal("Execution aborted at: pc = 0x%08x\n", (int)cpu->pc); \
-				cpu->cd.m88k.next_ic = &nothing_call;	\
-				cpu->running = 0;			\
-				debugger_n_steps_left_before_interaction = 0; }
-
-
-/*
- *  nop:  Do nothing.
- */
-X(nop)
-{
-}
-
-
-/*
- *  br_samepage:    Branch (to within the same translated page)
- *  bsr_samepage:   Branch to subroutine (to within the same translated page)
- *
- *  arg[0] = pointer to new instr_call
- *  arg[2] = offset to return address, from start of page
- */
-X(br_samepage)
-{
-	cpu->cd.m88k.next_ic = (struct m88k_instr_call *) ic->arg[0];
-}
-X(bsr_samepage)
-{
-	cpu->cd.m88k.r[M88K_RETURN_REG] = (cpu->pc &
-	    ~((M88K_IC_ENTRIES_PER_PAGE-1) << M88K_INSTR_ALIGNMENT_SHIFT))
-	    + ic->arg[2];
-	cpu->cd.m88k.next_ic = (struct m88k_instr_call *) ic->arg[0];
-}
-
-
-/*
- *  br:    Branch (to a different translated page)
- *  br.n:  Branch (to a different translated page) with delay slot
- *  bsr:   Branch to subroutine (to a different translated page)
- *  bsr.n: Branch to subroutine (to a different page) with delay slot
- *
- *  arg[1] = relative offset from start of page
- *  arg[2] = offset to return address, from start of page
- */
-X(br)
-{
-	cpu->pc = (uint32_t)((cpu->pc & 0xfffff000) + (int32_t)ic->arg[1]);
-	quick_pc_to_pointers(cpu);
-}
-X(br_n)
-{
-	cpu->cd.m88k.delay_target = (cpu->pc & ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
-	    M88K_INSTR_ALIGNMENT_SHIFT)) + (int32_t)ic->arg[1];
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		cpu->pc = cpu->cd.m88k.delay_target;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bsr)
-{
-	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
-	    M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.m88k.r[M88K_RETURN_REG] = cpu->pc + ic->arg[2];
-	cpu->pc = (uint32_t) (cpu->pc + ic->arg[1]);
-	quick_pc_to_pointers(cpu);
-}
-X(bsr_n)
-{
-	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
-	    M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.m88k.r[M88K_RETURN_REG] = cpu->pc + ic->arg[2] + 4;
-	cpu->cd.m88k.delay_target = cpu->pc + ic->arg[1];
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		cpu->pc = cpu->cd.m88k.delay_target;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bsr_trace)
-{
-	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
-	    M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.m88k.r[M88K_RETURN_REG] = cpu->pc + ic->arg[2];
-	cpu->pc = (uint32_t) (cpu->pc + ic->arg[1]);
-	cpu_functioncall_trace(cpu, cpu->pc);
-	quick_pc_to_pointers(cpu);
-}
-X(bsr_n_trace)
-{
-	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
-	    M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.m88k.r[M88K_RETURN_REG] = cpu->pc + ic->arg[2] + 4;
-	cpu->cd.m88k.delay_target = cpu->pc + ic->arg[1];
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		cpu->pc = cpu->cd.m88k.delay_target;
-		cpu_functioncall_trace(cpu, cpu->pc);
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  bb?            Branch if a bit in a register is 0 or 1.
- *  bb?_samepage:  Branch within the same translated page.
- *  bb?_n_*:       With delay slot.
- *
- *  arg[0] = pointer to source register to test (s1).
- *  arg[1] = uint32_t mask to test (e.g. 0x00010000 to test bit 16)
- *  arg[2] = offset from start of current page _OR_ pointer to new instr_call
- */
-X(bb0)
-{
-	if (!(reg(ic->arg[0]) & ic->arg[1])) {
-		cpu->pc = (cpu->pc & 0xfffff000) + (int32_t)ic->arg[2];
-		quick_pc_to_pointers(cpu);
-	}
-}
-X(bb0_samepage)
-{
-	if (!(reg(ic->arg[0]) & ic->arg[1]))
-		cpu->cd.m88k.next_ic = (struct m88k_instr_call *) ic->arg[2];
-}
-X(bb0_n)
-{
-	int cond = !(reg(ic->arg[0]) & (uint32_t)ic->arg[1]);
-
-	SYNCH_PC;
-
-	if (cond)
-		cpu->cd.m88k.delay_target =
-		    (cpu->pc & ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
-		    M88K_INSTR_ALIGNMENT_SHIFT)) + (int32_t)ic->arg[2];
-	else
-		cpu->cd.m88k.delay_target = cpu->pc + 8;
-
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (cond) {
-			cpu->pc = cpu->cd.m88k.delay_target;
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.m88k.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bb1)
-{
-	if (reg(ic->arg[0]) & ic->arg[1]) {
-		cpu->pc = (cpu->pc & 0xfffff000) + (int32_t)ic->arg[2];
-		quick_pc_to_pointers(cpu);
-	}
-}
-X(bb1_samepage)
-{
-	if (reg(ic->arg[0]) & ic->arg[1])
-		cpu->cd.m88k.next_ic = (struct m88k_instr_call *) ic->arg[2];
-}
-X(bb1_n)
-{
-	int cond = reg(ic->arg[0]) & ic->arg[1];
-
-	SYNCH_PC;
-
-	if (cond)
-		cpu->cd.m88k.delay_target =
-		    (cpu->pc & ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
-		    M88K_INSTR_ALIGNMENT_SHIFT)) + (int32_t)ic->arg[2];
-	else
-		cpu->cd.m88k.delay_target = cpu->pc + 8;
-
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (cond) {
-			cpu->pc = cpu->cd.m88k.delay_target;
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.m88k.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  ff0, ff1: Find first cleared/set bit in a register
- *
- *  arg[0] = pointer to register d
- *  arg[2] = pointer to register s2
- */
-X(ff0)
-{
-	uint32_t mask = 0x80000000, s2 = reg(ic->arg[2]);
-	int n = 31;
-
-	for (;;) {
-		if (!(s2 & mask)) {
-			reg(ic->arg[0]) = n;
-			return;
-		}
-		mask >>= 1; n--;
-		if (mask == 0) {
-			reg(ic->arg[0]) = 32;
-			return;
-		}
-	}
-}
-X(ff1)
-{
-	uint32_t mask = 0x80000000, s2 = reg(ic->arg[2]);
-	int n = 31;
-
-	for (;;) {
-		if (s2 & mask) {
-			reg(ic->arg[0]) = n;
-			return;
-		}
-		mask >>= 1; n--;
-		if (mask == 0) {
-			reg(ic->arg[0]) = 32;
-			return;
-		}
-	}
-}
-
-
-/*  Include all automatically generated bcnd and bcnd.n instructions:  */
-#include "tmp_m88k_bcnd.cc"
-
-
-/*  Include all automatically generated load/store instructions:  */
-#include "tmp_m88k_loadstore.cc"
-#define M88K_LOADSTORE_STORE            4
-#define M88K_LOADSTORE_SIGNEDNESS       8
-#define M88K_LOADSTORE_ENDIANNESS       16
-#define M88K_LOADSTORE_SCALEDNESS       32
-#define M88K_LOADSTORE_USR              64
-#define M88K_LOADSTORE_REGISTEROFFSET   128
-
-
-/*
- *  jmp:   Jump to register
- *  jmp.n: Jump to register, with delay slot
- *  jsr:   Jump to register, set r1 to return address
- *  jsr.n: Jump to register, set r1 to return address, with delay slot
- *
- *  arg[1] = offset to return address, from start of current page
- *  arg[2] = pointer to register s2
- */
-X(jmp)
-{
-	cpu->pc = reg(ic->arg[2]) & ~3;
-	quick_pc_to_pointers(cpu);
-}
-X(jmp_n)
-{
-	cpu->cd.m88k.delay_target = reg(ic->arg[2]) & ~3;
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		cpu->pc = cpu->cd.m88k.delay_target;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(jmp_trace)
-{
-	cpu->pc = reg(ic->arg[2]) & ~3;
-	cpu_functioncall_trace_return(cpu);
-	quick_pc_to_pointers(cpu);
-}
-X(jmp_n_trace)
-{
-	cpu->cd.m88k.delay_target = reg(ic->arg[2]) & ~3;
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		cpu->pc = cpu->cd.m88k.delay_target;
-		cpu_functioncall_trace_return(cpu);
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(jsr)
-{
-	cpu->cd.m88k.r[M88K_RETURN_REG] = (cpu->pc & 0xfffff000) + ic->arg[1];
-	cpu->pc = reg(ic->arg[2]) & ~3;
-	quick_pc_to_pointers(cpu);
-}
-X(jsr_n)
-{
-	cpu->cd.m88k.delay_target = reg(ic->arg[2]) & ~3;
-	cpu->cd.m88k.r[M88K_RETURN_REG] = (cpu->pc & 0xfffff000) + ic->arg[1];
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		cpu->pc = cpu->cd.m88k.delay_target;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(jsr_trace)
-{
-	cpu->cd.m88k.r[M88K_RETURN_REG] = (cpu->pc & 0xfffff000) + ic->arg[1];
-	cpu->pc = reg(ic->arg[2]) & ~3;
-	cpu_functioncall_trace(cpu, cpu->pc);
-	quick_pc_to_pointers(cpu);
-}
-X(jsr_n_trace)
-{
-	cpu->cd.m88k.delay_target = reg(ic->arg[2]) & ~3;
-	cpu->cd.m88k.r[M88K_RETURN_REG] = (cpu->pc & 0xfffff000) + ic->arg[1];
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		cpu->pc = cpu->cd.m88k.delay_target;
-		cpu_functioncall_trace(cpu, cpu->pc);
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  cmp_imm:  Compare S1 with immediate value.
- *  cmp:      Compare S1 with S2.
- *
- *  arg[0] = pointer to register d
- *  arg[1] = pointer to register s1
- *  arg[2] = pointer to register s2 or imm
- */
-static void m88k_cmp(struct cpu *cpu, struct m88k_instr_call *ic, uint32_t y)
-{
-	uint32_t x = reg(ic->arg[1]);
-	uint32_t r;
-
-	if (x == y) {
-		r = M88K_CMP_HS | M88K_CMP_LS | M88K_CMP_GE
-		  | M88K_CMP_LE | M88K_CMP_EQ;
-	} else {
-		if (x > y)
-			r = M88K_CMP_NE | M88K_CMP_HS | M88K_CMP_HI;
-		else
-			r = M88K_CMP_NE | M88K_CMP_LO | M88K_CMP_LS;
-		if ((int32_t)x > (int32_t)y)
-			r |= M88K_CMP_GE | M88K_CMP_GT;
-		else
-			r |= M88K_CMP_LT | M88K_CMP_LE;
-	}
-
-	reg(ic->arg[0]) = r;
-}
-X(cmp_imm) { m88k_cmp(cpu, ic, ic->arg[2]); }
-X(cmp)     { m88k_cmp(cpu, ic, reg(ic->arg[2])); }
-
-
-/*
- *  extu_imm:  Extract bits, unsigned, immediate W<O>.
- *  extu:      Extract bits, unsigned, W<O> taken from register s2.
- *  ext_imm:   Extract bits, signed, immediate W<O>.
- *  ext:       Extract bits, signed, W<O> taken from register s2.
- *  mak_imm:   Make bit field, immediate W<O>.
- *  mak:       Make bit field, W<O> taken from register s2.
- *  rot:       Rotate s1 right, nr of steps taken from s2.
- *  clr:       Clear bits, W<O> taken from register s2.
- *  set:       Set bits, W<O> taken from register s2.
- *
- *  arg[0] = pointer to register d
- *  arg[1] = pointer to register s1
- *  arg[2] = pointer to register s2 or 10 bits wwwwwooooo
- */
-static void m88k_extu(struct cpu *cpu, struct m88k_instr_call *ic, int w, int o)
-{
-	uint32_t x = reg(ic->arg[1]) >> o;
-	if (w != 0) {
-		x <<= (32-w);
-		x >>= (32-w);
-	}
-	reg(ic->arg[0]) = x;
-}
-static void m88k_ext(struct cpu *cpu, struct m88k_instr_call *ic, int w, int o)
-{
-	int32_t x = reg(ic->arg[1]);
-	x >>= o;	/*  signed (arithmetic) shift  */
-	if (w != 0) {
-		x <<= (32-w);
-		x >>= (32-w);
-	}
-	reg(ic->arg[0]) = x;
-}
-static void m88k_mak(struct cpu *cpu, struct m88k_instr_call *ic, int w, int o)
-{
-	uint32_t x = reg(ic->arg[1]);
-	if (w != 0) {
-		x <<= (32-w);
-		x >>= (32-w);
-	}
-	reg(ic->arg[0]) = x << o;
-}
-X(extu_imm)
-{
-	m88k_extu(cpu, ic, ic->arg[2] >> 5, ic->arg[2] & 0x1f);
-}
-X(extu)
-{
-	m88k_extu(cpu, ic, (reg(ic->arg[2]) >> 5) & 0x1f,
-	    reg(ic->arg[2]) & 0x1f);
-}
-X(ext_imm)
-{
-	m88k_ext(cpu, ic, ic->arg[2] >> 5, ic->arg[2] & 0x1f);
-}
-X(ext)
-{
-	m88k_ext(cpu, ic, (reg(ic->arg[2]) >> 5) & 0x1f,
-	    reg(ic->arg[2]) & 0x1f);
-}
-X(mak_imm)
-{
-	m88k_mak(cpu, ic, ic->arg[2] >> 5, ic->arg[2] & 0x1f);
-}
-X(mak)
-{
-	m88k_mak(cpu, ic, (reg(ic->arg[2]) >> 5) & 0x1f,
-	    reg(ic->arg[2]) & 0x1f);
-}
-static void m88k_rot(struct cpu *cpu, struct m88k_instr_call *ic, int n)
-{
-	uint32_t x = reg(ic->arg[1]);
-
-	if (n != 0) {
-		uint32_t mask = (1 << n) - 1;
-		uint32_t bits = x & mask;
-		x >>= n;
-		x |= (bits << (32-n));
-	}
-
-	reg(ic->arg[0]) = x;
-}
-X(rot)
-{
-	m88k_rot(cpu, ic, reg(ic->arg[2]) & 0x1f);
-}
-X(clr)
-{
-	int w = (reg(ic->arg[2]) >> 5) & 0x1f, o = reg(ic->arg[2]) & 0x1f;
-	uint32_t x = w == 0? 0xffffffff : ((uint32_t)1 << w) - 1;
-	x <<= o;
-	reg(ic->arg[0]) = reg(ic->arg[1]) & ~x;
-}
-X(set)
-{
-	int w = (reg(ic->arg[2]) >> 5) & 0x1f, o = reg(ic->arg[2]) & 0x1f;
-	uint32_t x = w == 0? 0xffffffff : ((uint32_t)1 << w) - 1;
-	x <<= o;
-	reg(ic->arg[0]) = reg(ic->arg[1]) | x;
-}
-
-
-/*
- *  or_r0_imm0: d = 0		(optimized case when s1 = r0, imm = 0)
- *  or_r0_imm:  d = imm		(optimized case when s1 = r0)
- *  or_imm:     d = s1 | imm
- *  xor_imm:    d = s1 ^ imm
- *  and_imm:    d = (s1 & imm) | (s1 & 0xffff0000)
- *  and_u_imm:  d = (s1 & imm) | (s1 & 0xffff)
- *  mask_imm:   d = s1 & imm
- *  add_imm:    d = s1 - imm	(addition with overflow exception)
- *  addu_imm:   d = s1 + imm
- *  subu_imm:   d = s1 - imm
- *  inc_reg:    d ++;		(addu special case; d = d + 1)
- *  dec_reg:    d --;		(subu special case; d = d - 1)
- *  mulu_imm:   d = s1 * imm
- *  divu_imm:   d = s1 / imm	(unsigned)
- *  div_imm:    d = s1 / imm	(signed)
- *  sub_imm:    d = s1 - imm	(subtraction with overflow exception)
- *
- *  arg[0] = pointer to register d
- *  arg[1] = pointer to register s1
- *  arg[2] = imm
- */
-X(or_r0_imm0)	{ reg(ic->arg[0]) = 0; }
-X(or_r0_imm)	{ reg(ic->arg[0]) = ic->arg[2]; }
-X(or_imm)	{ reg(ic->arg[0]) = reg(ic->arg[1]) | ic->arg[2]; }
-X(xor_imm)	{ reg(ic->arg[0]) = reg(ic->arg[1]) ^ ic->arg[2]; }
-X(and_imm)	{ reg(ic->arg[0]) = (reg(ic->arg[1]) & ic->arg[2])
-		    | (reg(ic->arg[1]) & 0xffff0000); }
-X(and_u_imm)	{ reg(ic->arg[0]) = (reg(ic->arg[1]) & ic->arg[2])
-		    | (reg(ic->arg[1]) & 0xffff); }
-X(mask_imm)	{ reg(ic->arg[0]) = reg(ic->arg[1]) & ic->arg[2]; }
-X(add_imm)
-{
-	uint64_t a = (int32_t) reg(ic->arg[1]);
-	uint64_t b = ic->arg[2];
-	uint64_t res = a + b;
-	uint64_t res2 = (int32_t) res;
-
-	if (res != res2) {
-		SYNCH_PC;
-		m88k_exception(cpu, M88K_EXCEPTION_INTEGER_OVERFLOW, 0);
-		return;
-	}
-
-	reg(ic->arg[0]) = res;
-}
-X(addu_imm)	{ reg(ic->arg[0]) = reg(ic->arg[1]) + ic->arg[2]; }
-X(subu_imm)	{ reg(ic->arg[0]) = reg(ic->arg[1]) - ic->arg[2]; }
-X(inc_reg)	{ reg(ic->arg[0]) ++; }
-X(dec_reg)	{ reg(ic->arg[0]) --; }
-X(mulu_imm)
-{
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-	} else
-		reg(ic->arg[0]) = reg(ic->arg[1]) * ic->arg[2];
-}
-X(divu_imm)
-{
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-	} else if (ic->arg[2] == 0) {
-		SYNCH_PC;
-		m88k_exception(cpu, M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE, 0);
-	} else
-		reg(ic->arg[0]) = (uint32_t) reg(ic->arg[1]) / (uint32_t) ic->arg[2];
-}
-X(div_imm)
-{
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-	} else if (ic->arg[2] == 0) {
-		SYNCH_PC;
-		m88k_exception(cpu, M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE, 0);
-	} else {
-		int32_t res = (int32_t) reg(ic->arg[1]) / (int32_t) ic->arg[2];
-		reg(ic->arg[0]) = res;
-	}
-}
-X(sub_imm)
-{
-	uint64_t a = (int32_t) reg(ic->arg[1]);
-	uint64_t b = ic->arg[2];
-	uint64_t res = a - b;
-	uint64_t res2 = (int32_t) res;
-
-	if (res != res2) {
-		SYNCH_PC;
-		m88k_exception(cpu, M88K_EXCEPTION_INTEGER_OVERFLOW, 0);
-		return;
-	}
-
-	reg(ic->arg[0]) = res;
-}
-
-
-/*
- *  or:     	d = s1 | s2
- *  or_c:     	d = s1 | ~s2
- *  or_r0:  	d =      s2
- *  xor:    	d = s1 ^ s2
- *  xor_c:    	d = s1 ^ ~s2
- *  and:    	d = s1 & s2
- *  and_c:    	d = s1 & ~s2
- *  add:   	d = s1 + s2		with trap on overflow
- *  addu:   	d = s1 + s2
- *  addu_co:   	d = s1 + s2		carry out
- *  addu_ci:   	d = s1 + s2 + carry	carry in
- *  lda_reg_X:	same as addu, but s2 is scaled by 2, 4, or 8
- *  subu:   	d = s1 - s2
- *  subu_co:   	d = s1 - s2		carry/borrow out
- *  subu_ci:   	d = s1 - s2 - (carry? 0 : 1)	carry in
- *  mul:    	d = s1 * s2
- *  divu:   	d = s1 / s2		(unsigned)
- *  div:    	d = s1 / s2		(signed)
- *
- *  arg[0] = pointer to register d
- *  arg[1] = pointer to register s1
- *  arg[2] = pointer to register s2
- */
-X(or)	{ reg(ic->arg[0]) = reg(ic->arg[1]) | reg(ic->arg[2]); }
-X(or_c)	{ reg(ic->arg[0]) = reg(ic->arg[1]) | ~(reg(ic->arg[2])); }
-X(or_r0){ reg(ic->arg[0]) = reg(ic->arg[2]); }
-X(xor)	{ reg(ic->arg[0]) = reg(ic->arg[1]) ^ reg(ic->arg[2]); }
-X(xor_c){ reg(ic->arg[0]) = reg(ic->arg[1]) ^ ~(reg(ic->arg[2])); }
-X(and)	{ reg(ic->arg[0]) = reg(ic->arg[1]) & reg(ic->arg[2]); }
-X(and_c){ reg(ic->arg[0]) = reg(ic->arg[1]) & ~(reg(ic->arg[2])); }
-X(addu)	{ reg(ic->arg[0]) = reg(ic->arg[1]) + reg(ic->arg[2]); }
-X(addu_s2r0)	{ reg(ic->arg[0]) = reg(ic->arg[1]); }
-X(lda_reg_2)	{ reg(ic->arg[0]) = reg(ic->arg[1]) + reg(ic->arg[2]) * 2; }
-X(lda_reg_4)	{ reg(ic->arg[0]) = reg(ic->arg[1]) + reg(ic->arg[2]) * 4; }
-X(lda_reg_8)	{ reg(ic->arg[0]) = reg(ic->arg[1]) + reg(ic->arg[2]) * 8; }
-X(subu)	{ reg(ic->arg[0]) = reg(ic->arg[1]) - reg(ic->arg[2]); }
-X(add)
-{
-	uint64_t s1 = (int32_t) reg(ic->arg[1]);
-	uint64_t s2 = (int32_t) reg(ic->arg[2]);
-	uint64_t d = s1 + s2;
-	uint64_t dx = (int32_t) d;
-
-	/*  "If the result cannot be represented as a signed 32-bit integer"
-	    then there should be an exception.  */
-	if (d != dx) {
-		SYNCH_PC;
-		m88k_exception(cpu, M88K_EXCEPTION_INTEGER_OVERFLOW, 0);
-	} else {
-		reg(ic->arg[0]) = d;
-	}
-}
-X(mul)
-{
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-	} else
-		reg(ic->arg[0]) = reg(ic->arg[1]) * reg(ic->arg[2]);
-}
-X(divu)
-{
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-	} else if (reg(ic->arg[2]) == 0) {
-		SYNCH_PC;
-		m88k_exception(cpu, M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE, 0);
-	} else
-		reg(ic->arg[0]) = (uint32_t) reg(ic->arg[1]) / (uint32_t) reg(ic->arg[2]);
-}
-X(div)
-{
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-	} else if (reg(ic->arg[2]) == 0) {
-		SYNCH_PC;
-		m88k_exception(cpu, M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE, 0);
-	} else {
-		int32_t res = (int32_t) reg(ic->arg[1]) / (int32_t) reg(ic->arg[2]);
-		reg(ic->arg[0]) = res;
-	}
-}
-X(addu_co)
-{
-	uint64_t a = reg(ic->arg[1]), b = reg(ic->arg[2]);
-	a += b;
-	reg(ic->arg[0]) = a;
-	cpu->cd.m88k.cr[M88K_CR_PSR] &= ~M88K_PSR_C;
-	if ((a >> 32) & 1)
-		cpu->cd.m88k.cr[M88K_CR_PSR] |= M88K_PSR_C;
-}
-X(addu_ci)
-{
-	uint32_t result = reg(ic->arg[1]) + reg(ic->arg[2]);
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_C)
-		result ++;
-	reg(ic->arg[0]) = result;
-}
-X(subu_co)
-{
-	uint64_t a = reg(ic->arg[1]), b = reg(ic->arg[2]);
-	a -= b;
-	reg(ic->arg[0]) = a;
-	cpu->cd.m88k.cr[M88K_CR_PSR] &= ~M88K_PSR_C;
-	if ((a >> 32) & 1)
-		cpu->cd.m88k.cr[M88K_CR_PSR] |= M88K_PSR_C;
-}
-X(subu_ci)
-{
-	uint32_t result = reg(ic->arg[1]) - reg(ic->arg[2]);
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_C)
-		result --;
-	reg(ic->arg[0]) = result;
-}
-
-
-/*
- *  ldcr:   Load value from a control register, store in register d.
- *  fldcr:  Load value from a floating point control register, store in reg d.
- *
- *  arg[0] = pointer to register d
- *  arg[1] = 6-bit control register number
- */
-X(ldcr)
-{
-	SYNCH_PC;
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)
-		m88k_ldcr(cpu, (uint32_t *) (void *) ic->arg[0], ic->arg[1]);
-	else
-		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
-}
-X(fldcr)
-{
-	SYNCH_PC;
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE || ic->arg[1] >= 62)
-		reg(ic->arg[0]) = cpu->cd.m88k.fcr[ic->arg[1]];
-	else {
-		/*  TODO: The manual says "floating point privilege
-		    violation", not just "privilege violation"!  */
-		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
-	}
-}
-
-
-/*
- *  stcr:   Store a value into a control register.
- *  fstcr:  Store a value into a floating point control register.
- *
- *  arg[0] = pointer to source register
- *  arg[1] = 6-bit control register number
- */
-X(stcr)
-{
-	SYNCH_PC;
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)
-		m88k_stcr(cpu, reg(ic->arg[0]), ic->arg[1], 0);
-	else
-		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
-}
-X(fstcr)
-{
-	SYNCH_PC;
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE || ic->arg[1] >= 62)
-		m88k_fstcr(cpu, reg(ic->arg[0]), ic->arg[1]);
-	else {
-		/*  TODO: The manual says "floating point privilege
-		    violation", not just "privilege violation"!  */
-		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
-	}
-}
-
-
-/*
- *  fadd.xxx:  Floating point addition
- *  fsub.xxx:  Floating point subtraction
- *  fmul.xxx:  Floating point multiplication
- *  fdiv.xxx:  Floating point multiplication
- *
- *  arg[0] = pointer to destination register
- *  arg[1] = pointer to source register s1
- *  arg[2] = pointer to source register s2
- *
- *  Note: For 'd' variants, arg[x] points to a _pair_ of registers!
- */
-X(fadd_sss)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint32_t d;
-	uint32_t s2 = reg(ic->arg[2]);
-	uint32_t s1 = reg(ic->arg[1]);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
-
-	d = ieee_store_float_value(f1.f + f2.f, IEEE_FMT_S);
-
-	reg(ic->arg[0]) = d;
-}
-X(fadd_dsd)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint64_t s2 = reg(ic->arg[2]);
-	uint32_t s1 = reg(ic->arg[1]);
-	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
-
-	d = ieee_store_float_value(f1.f + f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-X(fadd_dds)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint32_t s2 = reg(ic->arg[2]);
-	uint64_t s1 = reg(ic->arg[1]);
-	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
-
-	d = ieee_store_float_value(f1.f + f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-X(fadd_ddd)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint64_t s1 = reg(ic->arg[1]);
-	uint64_t s2 = reg(ic->arg[2]);
-	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
-	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
-
-	d = ieee_store_float_value(f1.f + f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-X(fsub_sds)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint32_t d;
-	uint32_t s2 = reg(ic->arg[2]);
-	uint64_t s1 = reg(ic->arg[1]);
-	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
-
-	d = ieee_store_float_value(f1.f - f2.f, IEEE_FMT_S);
-	reg(ic->arg[0]) = d;
-}
-X(fsub_dss)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint32_t s2 = reg(ic->arg[2]);
-	uint32_t s1 = reg(ic->arg[1]);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
-
-	d = ieee_store_float_value(f1.f - f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-X(fsub_dsd)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint64_t s2 = reg(ic->arg[2]);
-	uint32_t s1 = reg(ic->arg[1]);
-	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
-
-	d = ieee_store_float_value(f1.f - f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-X(fsub_dds)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint32_t s2 = reg(ic->arg[2]);
-	uint64_t s1 = reg(ic->arg[1]);
-	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
-
-	d = ieee_store_float_value(f1.f - f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-X(fsub_ddd)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint64_t s1 = reg(ic->arg[1]);
-	uint64_t s2 = reg(ic->arg[2]);
-	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
-	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
-
-	d = ieee_store_float_value(f1.f - f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-X(fmul_sss)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint32_t d;
-	uint32_t s2 = reg(ic->arg[2]);
-	uint32_t s1 = reg(ic->arg[1]);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
-
-	d = ieee_store_float_value(f1.f * f2.f, IEEE_FMT_S);
-	reg(ic->arg[0]) = d;
-}
-X(fmul_dss)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint32_t s2 = reg(ic->arg[2]);
-	uint32_t s1 = reg(ic->arg[1]);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
-
-	d = ieee_store_float_value(f1.f * f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-X(fmul_dsd)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint64_t s2 = reg(ic->arg[2]);
-	uint32_t s1 = reg(ic->arg[1]);
-	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
-
-	d = ieee_store_float_value(f1.f * f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-X(fmul_dds)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint32_t s2 = reg(ic->arg[2]);
-	uint64_t s1 = reg(ic->arg[1]);
-	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
-
-	d = ieee_store_float_value(f1.f * f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-X(fmul_ddd)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint64_t s1 = reg(ic->arg[1]);
-	uint64_t s2 = reg(ic->arg[2]);
-	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
-	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
-
-	d = ieee_store_float_value(f1.f * f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-X(fdiv_sss)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint32_t d;
-	uint32_t s1 = reg(ic->arg[1]);
-	uint32_t s2 = reg(ic->arg[2]);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
-
-	if (f2.f == 0) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FDVZ;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	d = ieee_store_float_value(f1.f / f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d;
-}
-X(fdiv_dsd)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint32_t s1 = reg(ic->arg[1]);
-	uint64_t s2 = reg(ic->arg[2]);
-	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_S);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
-
-	if (f2.f == 0) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FDVZ;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	d = ieee_store_float_value(f1.f / f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-X(fdiv_ddd)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t d;
-	uint64_t s1 = reg(ic->arg[1]);
-	uint64_t s2 = reg(ic->arg[2]);
-	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
-	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
-
-	if (f2.f == 0) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FDVZ;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	d = ieee_store_float_value(f1.f / f2.f, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = d >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = d;	/*  and low word.  */
-}
-
-
-/*
- *  fcmp.sXX:  Floating point comparison
- *
- *  arg[0] = pointer to destination register
- *  arg[1] = pointer to source register s1
- *  arg[2] = pointer to source register s2
- *
- *  Note: For 'd' variants, arg[x] points to a _pair_ of registers!
- */
-static uint32_t m88k_fcmp_common(struct ieee_float_value *f1,
-	struct ieee_float_value *f2)
-{
-	uint32_t d;
-
-	/*  TODO: Implement all bits correctly, e.g. "in range" bits.  */
-	d = 0;
-	if (isnan(f1->f) || isnan(f2->f))
-		d |= (1 << 0);
-	else {
-		d |= (1 << 1);
-		if (f1->f == f2->f)
-			d |= (1 << 2);
-		else
-			d |= (1 << 3);
-		if (f1->f > f2->f)
-			d |= (1 << 4);
-		else
-			d |= (1 << 5);
-		if (f1->f < f2->f)
-			d |= (1 << 6);
-		else
-			d |= (1 << 7);
-	}
-
-	return d;
-}
-X(fcmp_sds)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint32_t s2 = reg(ic->arg[2]);
-	uint64_t s1 = reg(ic->arg[1]);
-	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_S);
-	reg(ic->arg[0]) = m88k_fcmp_common(&f1, &f2);
-}
-X(fcmp_sdd)
-{
-	struct ieee_float_value f1;
-	struct ieee_float_value f2;
-	uint64_t s1 = reg(ic->arg[1]);
-	uint64_t s2 = reg(ic->arg[2]);
-	s1 = (s1 << 32) + reg(ic->arg[1] + 4);
-	s2 = (s2 << 32) + reg(ic->arg[2] + 4);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	ieee_interpret_float_value(s1, &f1, IEEE_FMT_D);
-	ieee_interpret_float_value(s2, &f2, IEEE_FMT_D);
-	reg(ic->arg[0]) = m88k_fcmp_common(&f1, &f2);
-}
-
-
-/*
- *  flt.ss and flt.ds:  Convert integer to floating point.
- *
- *  arg[0] = pointer to destination register
- *  arg[1] = pointer to source register s2
- *
- *  Note: For flt.ds, arg[0] points to a _pair_ of registers!
- */
-X(flt_ss)
-{
-	int32_t x = reg(ic->arg[1]);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	reg(ic->arg[0]) = ieee_store_float_value((double)x, IEEE_FMT_S);
-}
-X(flt_ds)
-{
-	int32_t x = reg(ic->arg[1]);
-	uint64_t result;
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	result = ieee_store_float_value((double)x, IEEE_FMT_D);
-
-	reg(ic->arg[0]) = result >> 32;	/*  High 32-bit word,  */
-	reg(ic->arg[0] + 4) = result;	/*  and low word.  */
-}
-
-
-/*
- *  trnc.ss and trnc.sd:  Truncate floating point to interger.
- *
- *  arg[0] = pointer to destination register
- *  arg[1] = pointer to source register s2
- *
- *  Note: For trnc.sd, arg[1] points to a _pair_ of registers!
- */
-X(trnc_ss)
-{
-	struct ieee_float_value f1;
-	ieee_interpret_float_value(reg(ic->arg[1]), &f1, IEEE_FMT_S);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	reg(ic->arg[0]) = (int32_t) f1.f;
-}
-X(trnc_sd)
-{
-	struct ieee_float_value f1;
-	uint64_t x = reg(ic->arg[1]);
-	x = (x << 32) + reg(ic->arg[1] + 4);
-	ieee_interpret_float_value(x, &f1, IEEE_FMT_D);
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_SFD1) {
-		SYNCH_PC;
-		cpu->cd.m88k.fcr[M88K_FPCR_FPECR] = M88K_FPECR_FUNIMP;
-		m88k_exception(cpu, M88K_EXCEPTION_SFU1_PRECISE, 0);
-		return;
-	}
-
-	reg(ic->arg[0]) = (int32_t) f1.f;
-}
-
-
-/*
- *  xcr:   Exchange (load + store) control register.
- *
- *  arg[0] = pointer to register d
- *  arg[1] = pointer to register s1
- *  arg[2] = 6-bit control register number
- */
-X(xcr)
-{
-	uint32_t tmp, tmp2;
-	SYNCH_PC;
-
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE) {
-		tmp = reg(ic->arg[1]);
-		m88k_ldcr(cpu, &tmp2, ic->arg[2]);
-		m88k_stcr(cpu, tmp, ic->arg[2], 0);
-		reg(ic->arg[0]) = tmp2;
-	} else
-		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
-}
-
-
-/*
- *  rte:  Return from exception
- */
-X(rte)
-{
-	/*  If executed from user mode, then cause an exception:  */
-	if (!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)) {
-		SYNCH_PC;
-		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
-		return;
-	}
-
-	m88k_stcr(cpu, cpu->cd.m88k.cr[M88K_CR_EPSR], M88K_CR_PSR, 1);
-
-	if (cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_E) {
-		fatal("rte: NIP: TODO: single-step support\n");
-		goto abort_dump;
-	}
-
-	if (cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_E) {
-		fatal("rte: TODO: FIP single-step support\n");
-		goto abort_dump;
-	}
-
-	/*  First try the NIP, if it is Valid:  */
-	cpu->pc = cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_ADDR;
-
-	/*  If the NIP is not valid, then try the FIP:  */
-	if (!(cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_V)) {
-		/*  Neither the NIP nor the FIP valid?  */
-		if (!(cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_V)) {
-			if ((cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_ADDR)
-			    != (cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_ADDR) + 4) {
-				fatal("[ TODO: Neither FIP nor NIP has the "
-				    "Valid bit set?! ]\n");
-				goto abort_dump;
-			}
-
-			/*  For now, continue anyway, using NIP.  */
-		} else {
-			cpu->pc = cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_ADDR;
-		}
-	} else if (cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_V &&
-	    cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_V &&
-	    (cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_ADDR)
-	    != (cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_ADDR) + 4) {
-		/*
-		 *  The NIP instruction should first be executed (this
-		 *  is the one the exception handler choose to return to),
-		 *  and then the FIP instruction should run (the target
-		 *  of a delayed branch).
-		 */
-
-		uint32_t nip = cpu->cd.m88k.cr[M88K_CR_SNIP] & M88K_NIP_ADDR;
-		uint32_t fip = cpu->cd.m88k.cr[M88K_CR_SFIP] & M88K_FIP_ADDR;
-
-		cpu->pc = nip;
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-
-		if (cpu->pc != nip) {
-			fatal("NIP execution caused exception?! TODO\n");
-			goto abort_dump;
-		}
-
-		instr(to_be_translated)(cpu, cpu->cd.m88k.next_ic);
-
-		if ((cpu->pc & 0xfffff000) != (nip & 0xfffff000)) {
-			fatal("instruction in delay slot when returning via"
-			    " rte caused an exception?! nip=0x%08x, but pc "
-			    "changed to 0x%08x! TODO\n", nip, (int)cpu->pc);
-			goto abort_dump;
-		}
-
-		cpu->pc = fip;
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-		return;
-	}
-
-	/*  fatal("RTE: NIP=0x%08" PRIx32", FIP=0x%08" PRIx32"\n",
-	    cpu->cd.m88k.cr[M88K_CR_SNIP], cpu->cd.m88k.cr[M88K_CR_SFIP]);  */
-
-	quick_pc_to_pointers(cpu);
-	return;
-
-abort_dump:
-	fatal("RTE failed. NIP=0x%08" PRIx32", FIP=0x%08" PRIx32"\n",
-	    cpu->cd.m88k.cr[M88K_CR_SNIP], cpu->cd.m88k.cr[M88K_CR_SFIP]);
-
-	ABORT_EXECUTION;
-}
-
-
-/*
- *  xmem_slow:  Unoptimized xmem (exchange register with memory)
- *
- *  arg[0] = copy of the instruction word
- */
-X(xmem_slow)
-{
-	uint32_t iword = ic->arg[0], addr;
-	uint8_t tmp[4];
-	uint8_t data[4];
-	int d      = (iword >> 21) & 0x1f;
-	int s1     = (iword >> 16) & 0x1f;
-	int s2     =  iword        & 0x1f;
-	int imm16  =  iword        & 0xffff;
-	int scaled = iword & 0x200;
-	int size   = iword & 0x400;
-	int user   = iword & 0x80;
-
-	SYNCH_PC;
-
-	if (user) {
-		fatal("xmem_slow: user: not yet (TODO)\n");
-		exit(1);
-	}
-
-	if ((iword & 0xf0000000) == 0) {
-		/*  immediate offset:  */
-		addr = imm16;
-		scaled = 0;
-		size = (iword >> 26) & 1;
-		user = 0;
-	} else {
-		/*  register offset:  */
-		addr = cpu->cd.m88k.r[s2];
-		if (scaled && size)
-			addr *= sizeof(uint32_t);
-	}
-
-	addr += cpu->cd.m88k.r[s1];
-
-	if (size) {
-		uint32_t x = cpu->cd.m88k.r[d];
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			x = LE32_TO_HOST(x);
-		else
-			x = BE32_TO_HOST(x);
-
-		{
-			uint32_t *p = (uint32_t *) tmp;
-			*p = x;
-		}
-
-		if (addr & 3) {
-			m88k_exception(cpu,
-			    M88K_EXCEPTION_MISALIGNED_ACCESS, 0);
-			return;
-		}
-	} else
-		tmp[0] = cpu->cd.m88k.r[d];
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, (uint8_t *) &data,
-	    size? 4 : 1, MEM_READ, CACHE_DATA)) {
-		/*  Exception.  */
-
-		fatal("XMEM exception: TODO: update the transaction"
-		    " registers!\n");
-		exit(1);
-		/*  return;  */
-	}
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, (uint8_t *) &tmp,
-	    size? 4 : 1, MEM_WRITE, CACHE_DATA)) {
-		/*  Exception.  */
-
-		fatal("XMEM exception: TODO: update the transaction"
-		    " registers!\n");
-		exit(1);
-		/*  return;  */
-	}
-
-	if (size) {
-		uint32_t x;
-		uint32_t *p = (uint32_t *) data;
-		x = *p;
-
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			x = LE32_TO_HOST(x);
-		else
-			x = BE32_TO_HOST(x);
-		cpu->cd.m88k.r[d] = x;
-	} else
-		cpu->cd.m88k.r[d] = data[0];
-}
-
-
-/*
- *  prom-call:
- */
-X(prom_call)
-{
-	/*  If executed from user mode, then cause an exception:  */
-	if (!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)) {
-		SYNCH_PC;
-		m88k_exception(cpu, M88K_EXCEPTION_UNIMPLEMENTED_OPCODE, 0);
-		return;
-	}
-
-	switch (cpu->machine->machine_type) {
-
-	case MACHINE_LUNA88K:
-		luna88kprom_emul(cpu);
-		break;
-
-	case MACHINE_MVME88K:
-		mvmeprom_emul(cpu);
-		break;
-
-	default:fatal("m88k prom_call: unimplemented machine type\n");
-		ABORT_EXECUTION;
-	}
-
-	if (!cpu->running) {
-		cpu->n_translated_instrs --;
-		cpu->cd.m88k.next_ic = &nothing_call;
-	}
-}
-
-
-/*
- *  tb0, tb1:  Trap on bit Clear/Set
- *
- *  arg[0] = bitmask to check (e.g. 0x00020000 for bit 17)
- *  arg[1] = pointer to register s1
- *  arg[2] = 9-bit vector number
- */
-X(tb0)
-{
-	SYNCH_PC;
-
-	if (!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)
-	    && ic->arg[2] < M88K_EXCEPTION_USER_TRAPS_START) {
-		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
-		return;
-	}
-
-	if (!(reg(ic->arg[1]) & ic->arg[0]))
-		m88k_exception(cpu, ic->arg[2], 1);
-}
-X(tb1)
-{
-	SYNCH_PC;
-
-	if (!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)
-	    && ic->arg[2] < M88K_EXCEPTION_USER_TRAPS_START) {
-		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
-		return;
-	}
-
-	if (reg(ic->arg[1]) & ic->arg[0])
-		m88k_exception(cpu, ic->arg[2], 1);
-}
-
-
-/*
- *  idle:
- *
- *  s:	ld    rX,rY,ofs
- *      bcnd  eq0,rX,s
- */
-X(idle)
-{
-	uint32_t rY = reg(ic[0].arg[1]) + ic[0].arg[2];
-	uint32_t index = rY >> 12;
-	unsigned char *p = cpu->cd.m88k.host_load[index];
-	uint32_t *p32 = (uint32_t *) p;
-	uint32_t v;
-
-	/*  Fallback:  */
-	if (p == NULL || (rY & 3)) {
-		instr(ld_u_4_be)(cpu, ic);
-		return;
-	}
-
-	v = p32[(rY & 0xfff) >> 2];
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		v = LE32_TO_HOST(v);
-	else
-		v = BE32_TO_HOST(v);
-
-	reg(ic[0].arg[0]) = v;
-
-	if (v == 0) {
-		SYNCH_PC;
-		usleep(50);
-		cpu->has_been_idling = 1;
-		cpu->n_translated_instrs += N_SAFE_DYNTRANS_LIMIT / 2;
-		cpu->cd.m88k.next_ic = &nothing_call;
-	} else {
-		cpu->n_translated_instrs ++;
-		cpu->cd.m88k.next_ic = &ic[2];
-	}
-}
-
-
-/*
- *  idle_with_tb1:
- *
- *  s:	tb1	bit,r0,vector
- *	ld	rX,rY,ofs
- *	bcnd	eq0,rX,s
- */
-X(idle_with_tb1)
-{
-	uint32_t rY = reg(ic[1].arg[1]) + ic[1].arg[2];
-	uint32_t index = rY >> 12;
-	unsigned char *p = cpu->cd.m88k.host_load[index];
-	uint32_t *p32 = (uint32_t *) p;
-	uint32_t v;
-
-	/*  Fallback:  */
-	if (p == NULL || (rY & 3)) {
-		instr(tb1)(cpu, ic);
-		return;
-	}
-
-	v = p32[(rY & 0xfff) >> 2];
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		v = LE32_TO_HOST(v);
-	else
-		v = BE32_TO_HOST(v);
-
-	reg(ic[1].arg[0]) = v;
-
-	if (v == 0) {
-		SYNCH_PC;
-		usleep(50);
-		cpu->has_been_idling = 1;
-		cpu->n_translated_instrs += N_SAFE_DYNTRANS_LIMIT / 2;
-		cpu->cd.m88k.next_ic = &nothing_call;
-	} else {
-		cpu->n_translated_instrs += 2;
-		cpu->cd.m88k.next_ic = &ic[3];
-	}
-}
-
-
-/*****************************************************************************/
-
-
-X(end_of_page)
-{
-	/*  Update the PC:  (offset 0, but on the next page)  */
-	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
-	    M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (M88K_IC_ENTRIES_PER_PAGE << M88K_INSTR_ALIGNMENT_SHIFT);
-
-	/*  end_of_page doesn't count as an executed instruction:  */
-	cpu->n_translated_instrs --;
-
-	/*
-	 *  Find the new physpage and update translation pointers.
-	 *
-	 *  Note: This may cause an exception, if e.g. the new page is
-	 *  not accessible.
-	 */
-	quick_pc_to_pointers(cpu);
-
-	/*  Simple jump to the next page (if we are lucky):  */
-	if (cpu->delay_slot == NOT_DELAYED)
-		return;
-
-	/*
-	 *  If we were in a delay slot, and we got an exception while doing
-	 *  quick_pc_to_pointers, then return. The function which called
-	 *  end_of_page should handle this case.
-	 */
-	if (cpu->delay_slot == EXCEPTION_IN_DELAY_SLOT)
-		return;
-
-	/*
-	 *  Tricky situation; the delay slot is on the next virtual page.
-	 *  Calling to_be_translated will translate one instruction manually,
-	 *  execute it, and then discard it.
-	 */
-	/*  fatal("[ end_of_page: delay slot across page boundary! ]\n");  */
-
-	instr(to_be_translated)(cpu, cpu->cd.m88k.next_ic);
-
-	/*  The instruction in the delay slot has now executed.  */
-	/*  fatal("[ end_of_page: back from executing the delay slot, %i ]\n",
-	    cpu->delay_slot);  */
-
-	/*  Find the physpage etc of the instruction in the delay slot
-	    (or, if there was an exception, the exception handler):  */
-	quick_pc_to_pointers(cpu);
-}
-
-
-X(end_of_page2)
-{
-	/*  Synchronize PC on the _second_ instruction on the next page:  */
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page)
-	    / sizeof(struct m88k_instr_call);
-	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1)
-	    << M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << M88K_INSTR_ALIGNMENT_SHIFT);
-
-	if (low_pc < 0 || low_pc > ((M88K_IC_ENTRIES_PER_PAGE+1)
-	    << M88K_INSTR_ALIGNMENT_SHIFT)) {
-		printf("[ end_of_page2: HUH? low_pc=%i, cpu->pc = %08"
-		    PRIx32" ]\n", low_pc, (uint32_t) cpu->pc);
-	}
-
-	/*  This doesn't count as an executed instruction.  */
-	cpu->n_translated_instrs --;
-
-	quick_pc_to_pointers(cpu);
-
-	if (cpu->delay_slot == NOT_DELAYED)
-		return;
-
-	fatal("end_of_page2: fatal error, we're in a delay slot\n");
-	exit(1);
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  Idle loop detection, e.g.:
- *
- *  s00028d44: 15b7d650	ld	r13,r23,0xd650	    ; [<_sched_whichqs>]
- *  s00028d48: e84dffff	bcnd	eq0,r13,0x00028d44  ; <_sched_idle+0xc4>
- *
- *  or
- *
- *  s00079d78: f020d8ff	tb1	1,r0,0xff
- *  s00079d7c: 15ac7320	ld	r13,r12,0x7320	; [<_sched_whichqs>]
- *  s00079d80: e84dfffe	bcnd	eq0,r13,0x00079d78	; <_sched_idle+0x158>
- */
-void COMBINE(idle)(struct cpu *cpu, struct m88k_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> M88K_INSTR_ALIGNMENT_SHIFT)
-	    & (M88K_IC_ENTRIES_PER_PAGE-1);
-	if (n_back < 2)
-		return;
-
-	if (ic[0].f == instr(bcnd_samepage_eq0) &&
-	    ic[0].arg[2] == (size_t) &ic[-1] &&
-	    ic[-1].f == instr(ld_u_4_be) &&
-	    ic[0].arg[0] == ic[-1].arg[0] &&
-	    ic[0].arg[0] != (size_t) &cpu->cd.m88k.r[M88K_ZERO_REG]) {
-		ic[-1].f = instr(idle);
-		return;
-	}
-
-	if (ic[0].f == instr(bcnd_samepage_eq0) &&
-	    ic[0].arg[2] == (size_t) &ic[-2] &&
-	    ic[-2].f == instr(tb1) &&
-	    ic[-2].arg[1] == (size_t) &cpu->cd.m88k.r[M88K_ZERO_REG] &&
-	    ic[-1].f == instr(ld_u_4_be) &&
-	    ic[0].arg[0] == ic[-1].arg[0] &&
-	    ic[0].arg[0] != (size_t) &cpu->cd.m88k.r[M88K_ZERO_REG]) {
-		ic[-2].f = instr(idle_with_tb1);
-		return;
-	}
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  m88k_instr_to_be_translated():
- *
- *  Translate an instruction word into a m88k_instr_call. ic is filled in with
- *  valid data for the translated instruction, or a "nothing" instruction if
- *  there was a translation failure. The newly translated instruction is then
- *  executed.
- */
-X(to_be_translated)
-{
-	uint32_t addr, low_pc, iword;
-	unsigned char *page;
-	unsigned char ib[4];
-	uint32_t op26, op10, op11, d, s1, s2, cr6, imm16;
-	int32_t d16, d26; //, simm16;
-	int offset, shift;
-	int in_crosspage_delayslot = 0;
-	void (*samepage_function)(struct cpu *, struct m88k_instr_call *)=NULL;
-
-	/*  Figure out the (virtual) address of the instruction:  */
-	low_pc = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page)
-	    / sizeof(struct m88k_instr_call);
-
-	/*  Special case for branch with delayslot on the next page:  */
-	if (cpu->delay_slot == TO_BE_DELAYED && low_pc == 0) {
-		/*  fatal("[ delay-slot translation across page "
-		    "boundary ]\n");  */
-		in_crosspage_delayslot = 1;
-	}
-
-	addr = cpu->pc & ~((M88K_IC_ENTRIES_PER_PAGE-1)
-	    << M88K_INSTR_ALIGNMENT_SHIFT);
-	addr += (low_pc << M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc = (MODE_int_t)addr;
-	addr &= ~((1 << M88K_INSTR_ALIGNMENT_SHIFT) - 1);
-
-	/*  Read the instruction word from memory:  */
-	page = cpu->cd.m88k.host_load[(uint32_t)addr >> 12];
-
-	if (page != NULL) {
-		/*  fatal("TRANSLATION HIT!\n");  */
-		memcpy(ib, page + (addr & 0xffc), sizeof(ib));
-	} else {
-		/*  fatal("TRANSLATION MISS!\n");  */
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
-		    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
-			fatal("to_be_translated(): read failed: TODO\n");
-			goto bad;
-		}
-	}
-
-	{
-		uint32_t *p = (uint32_t *) ib;
-		iword = *p;
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		iword = LE32_TO_HOST(iword);
-	else
-		iword = BE32_TO_HOST(iword);
-
-
-#define DYNTRANS_TO_BE_TRANSLATED_HEAD
-#include "cpu_dyntrans.cc"
-#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD
-
-
-	/*
-	 *  Translate the instruction:
- 	 *
-	 *  NOTE: _NEVER_ allow writes to the zero register; all instructions
-	 *  that use the zero register as their destination should be treated
-	 *  as NOPs, except those that access memory (they should use the
-	 *  scratch register instead).
-	 */
-	if (cpu->cd.m88k.r[M88K_ZERO_REG] != 0) {
-		fatal("INTERNAL ERROR! M88K_ZERO_REG != 0?\n");
-		exit(1);
-	}
-
-	op26   = (iword >> 26) & 0x3f;
-	op11   = (iword >> 11) & 0x1f;
-	op10   = (iword >> 10) & 0x3f;
-	d      = (iword >> 21) & 0x1f;
-	s1     = (iword >> 16) & 0x1f;
-	s2     =  iword        & 0x1f;
-	imm16  =  iword        & 0xffff;
-	// simm16 = (int16_t) (iword & 0xffff);
-	cr6    = (iword >>  5) & 0x3f;
-	d16    = ((int16_t) (iword & 0xffff)) * 4;
-	d26    = ((int32_t)((iword & 0x03ffffff) << 6)) >> 4;
-
-	switch (op26) {
-
-	case 0x00:
-	case 0x01:
-		ic->f = instr(xmem_slow);
-		ic->arg[0] = iword;
-		if (d == M88K_ZERO_REG)
-			ic->f = instr(nop);
-		if (iword == 0)
-			goto bad;
-		break;
-
-	case 0x02:	/*  ld.hu  */
-	case 0x03:	/*  ld.bu  */
-	case 0x04:	/*  ld.d   */
-	case 0x05:	/*  ld     */
-	case 0x06:	/*  ld.h   */
-	case 0x07:	/*  ld.b   */
-	case 0x08:	/*  st.d   */
-	case 0x09:	/*  st     */
-	case 0x0a:	/*  st.h   */
-	case 0x0b:	/*  st.b   */
-		{
-			int store = 0, signedness = 0, opsize = 0;
-
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[2] = imm16;
-
-			switch (op26) {
-			case 0x02: opsize = 1; break;
-			case 0x03: opsize = 0; break;
-			case 0x04: opsize = 3; break;
-			case 0x05: opsize = 2; break;
-			case 0x06: opsize = 1; signedness = 1; break;
-			case 0x07: opsize = 0; signedness = 1; break;
-			case 0x08: store = 1; opsize = 3; break;
-			case 0x09: store = 1; opsize = 2; break;
-			case 0x0a: store = 1; opsize = 1; break;
-			case 0x0b: store = 1; opsize = 0; break;
-			}
-
-			if (opsize == 3 && d == 31) {
-				fatal("m88k load/store of register pair r31/r0"
-				    " is not yet implemented\n");
-				goto bad;
-			}
-
-			ic->f = m88k_loadstore[ opsize
-			    + (store? M88K_LOADSTORE_STORE : 0)
-			    + (signedness? M88K_LOADSTORE_SIGNEDNESS:0)
-			    + (cpu->byte_order == EMUL_BIG_ENDIAN?
-			       M88K_LOADSTORE_ENDIANNESS : 0) ];
-
-			if (!store && d == 0)
-				ic->arg[0] = (size_t) &cpu->cd.m88k.zero_scratch;
-		}
-		break;
-
-	case 0x10:	/*  and    imm  */
-	case 0x11:	/*  and.u  imm  */
-	case 0x12:	/*  mask   imm  */
-	case 0x13:	/*  mask.u imm  */
-	case 0x14:	/*  xor    imm  */
-	case 0x15:	/*  xor.u  imm  */
-	case 0x16:	/*  or     imm  */
-	case 0x17:	/*  or.u   imm  */
-	case 0x18:	/*  addu   imm  */
-	case 0x19:	/*  subu   imm  */
-	case 0x1a:	/*  divu   imm  */
-	case 0x1b:	/*  mulu   imm  */
-	case 0x1c:	/*  add    imm  */
-	case 0x1d:	/*  sub    imm  */
-	case 0x1e:	/*  div    imm  */
-	case 0x1f:	/*  cmp    imm  */
-		shift = 0;
-		switch (op26) {
-		case 0x10: ic->f = instr(and_imm); break;
-		case 0x11: ic->f = instr(and_u_imm); shift = 16; break;
-		case 0x12: ic->f = instr(mask_imm); break;
-		case 0x13: ic->f = instr(mask_imm); shift = 16; break;
-		case 0x14: ic->f = instr(xor_imm); break;
-		case 0x15: ic->f = instr(xor_imm); shift = 16; break;
-		case 0x16: ic->f = instr(or_imm); break;
-		case 0x17: ic->f = instr(or_imm); shift = 16; break;
-		case 0x18: ic->f = instr(addu_imm); break;
-		case 0x19: ic->f = instr(subu_imm); break;
-		case 0x1a: ic->f = instr(divu_imm); break;
-		case 0x1b: ic->f = instr(mulu_imm); break;
-		case 0x1c: ic->f = instr(add_imm); break;
-		case 0x1d: ic->f = instr(sub_imm); break;
-		case 0x1e: ic->f = instr(div_imm); break;
-		case 0x1f: ic->f = instr(cmp_imm); break;
-		}
-
-		ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-		ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-		ic->arg[2] = imm16 << shift;
-
-		/*  Optimization for  or d,r0,imm  and similar  */
-		if (s1 == M88K_ZERO_REG && ic->f == instr(or_imm)) {
-			if (ic->arg[2] == 0)
-				ic->f = instr(or_r0_imm0);
-			else
-				ic->f = instr(or_r0_imm);
-		}
-		if (ic->arg[2] == 0 && ic->f == instr(addu_imm))
-			ic->f = instr(addu_s2r0);
-
-		if (d == s1 && ic->arg[2] == 1) {
-			if (ic->f == instr(addu_imm))
-				ic->f = instr(inc_reg);
-			if (ic->f == instr(subu_imm))
-				ic->f = instr(dec_reg);
-		}
-
-		if (d == M88K_ZERO_REG)
-			ic->f = instr(nop);
-		break;
-
-	case 0x20:
-		if ((iword & 0x001ff81f) == 0x00004000) {
-			ic->f = instr(ldcr);
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = cr6;
-			if (d == M88K_ZERO_REG)
-				ic->arg[0] = (size_t)
-				    &cpu->cd.m88k.zero_scratch;
-		} else if ((iword & 0x001ff81f) == 0x00004800) {
-			ic->f = instr(fldcr);
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = cr6;
-			if (d == M88K_ZERO_REG)
-				ic->arg[0] = (size_t)
-				    &cpu->cd.m88k.zero_scratch;
-		} else if ((iword & 0x03e0f800) == 0x00008000) {
-			ic->f = instr(stcr);
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[1] = cr6;
-			if (s1 != s2)
-				goto bad;
-		} else if ((iword & 0x03e0f800) == 0x00008800) {
-			ic->f = instr(fstcr);
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[1] = cr6;
-			if (s1 != s2)
-				goto bad;
-		} else if ((iword & 0x0000f800) == 0x0000c000) {
-			ic->f = instr(xcr);
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[2] = cr6;
-			if (s1 != s2)
-				goto bad;
-		} else
-			goto bad;
-		break;
-
-	case 0x21:
-		switch (op11) {
-
-		case 0x00:	/*  fmul  */
-			if (d == 0) {
-				/*  d = 0 isn't allowed. for now, let's abort execution.  */
-				fatal("TODO: exception for d = 0 in fmul.xxx instruction\n");
-				goto bad;
-			}
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
-			switch ((iword >> 5) & 0x3f) {
-			case 0x00:	ic->f = instr(fmul_sss); break;
-			case 0x01:	ic->f = instr(fmul_dss); break;
-			case 0x05:	ic->f = instr(fmul_dsd); break;
-			case 0x11:	ic->f = instr(fmul_dds); break;
-			case 0x15:	ic->f = instr(fmul_ddd); break;
-			default:if (!cpu->translation_readahead)
-					fatal("Unimplemented fmul combination 0x%x.\n",
-					    (iword >> 5) & 0x3f);
-				goto bad;
-			}
-			break;
-
-		case 0x04:	/*  flt  */
-			if (d == 0) {
-				/*  d = 0 isn't allowed. for now, let's abort execution.  */
-				fatal("TODO: exception for d = 0 in flt.xx instruction\n");
-				goto bad;
-			}
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s2];
-			if ((iword >> 5) & 1) {
-				ic->f = instr(flt_ds);
-				if (d & 1) {
-					fatal("TODO: double precision load into uneven register r%i?\n", d);
-					goto bad;
-				}
-			} else {
-				ic->f = instr(flt_ss);
-			}
-			break;
-
-		case 0x05:	/*  fadd  */
-			if (d == 0) {
-				/*  d = 0 isn't allowed. for now, let's abort execution.  */
-				fatal("TODO: exception for d = 0 in fadd.xxx instruction\n");
-				goto bad;
-			}
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
-			switch ((iword >> 5) & 0x3f) {
-			case 0x00:	ic->f = instr(fadd_sss); break;
-			case 0x05:	ic->f = instr(fadd_dsd); break;
-			case 0x11:	ic->f = instr(fadd_dds); break;
-			case 0x15:	ic->f = instr(fadd_ddd); break;
-			default:if (!cpu->translation_readahead)
-					fatal("Unimplemented fadd combination 0x%x.\n",
-					    (iword >> 5) & 0x3f);
-				goto bad;
-			}
-			break;
-
-		case 0x06:	/*  fsub  */
-			if (d == 0) {
-				/*  d = 0 isn't allowed. for now, let's abort execution.  */
-				fatal("TODO: exception for d = 0 in fsub.xxx instruction\n");
-				goto bad;
-			}
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
-			switch ((iword >> 5) & 0x3f) {
-			case 0x01:	ic->f = instr(fsub_dss); break;
-			case 0x05:	ic->f = instr(fsub_dsd); break;
-			case 0x10:	ic->f = instr(fsub_sds); break;
-			case 0x11:	ic->f = instr(fsub_dds); break;
-			case 0x15:	ic->f = instr(fsub_ddd); break;
-			default:if (!cpu->translation_readahead)
-					fatal("Unimplemented fsub combination 0x%x.\n",
-					    (iword >> 5) & 0x3f);
-				goto bad;
-			}
-			break;
-
-		case 0x07:	/*  fcmp  */
-			if (d == 0) {
-				/*  d = 0 isn't allowed. for now, let's abort execution.  */
-				fatal("TODO: exception for d = 0 in fcmp.xxx instruction\n");
-				goto bad;
-			}
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
-			switch ((iword >> 5) & 0x3f) {
-			case 0x10:	ic->f = instr(fcmp_sds); break;
-			case 0x14:	ic->f = instr(fcmp_sdd); break;
-			default:if (!cpu->translation_readahead)
-					fatal("Unimplemented fcmp combination 0x%x.\n",
-					    (iword >> 5) & 0x3f);
-				goto bad;
-			}
-			break;
-
-		case 0x0b:	/*  trnc  */
-			if (d == 0) {
-				/*  d = 0 isn't allowed. for now, let's abort execution.  */
-				fatal("TODO: exception for d = 0 in trnc.xx instruction\n");
-				goto bad;
-			}
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s2];
-			if ((iword >> 7) & 1) {
-				ic->f = instr(trnc_sd);
-				if (s2 & 1) {
-					fatal("TODO: double precision truncation into uneven register r%i?\n", d);
-					goto bad;
-				}
-			} else {
-				ic->f = instr(trnc_ss);
-			}
-			break;
-
-		case 0x0e:	/*  fdiv  */
-			if (d == 0) {
-				/*  d = 0 isn't allowed. for now, let's abort execution.  */
-				fatal("TODO: exception for d = 0 in fdiv.xxx instruction\n");
-				goto bad;
-			}
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
-			switch ((iword >> 5) & 0x3f) {
-			case 0x00:	ic->f = instr(fdiv_sss); break;
-			case 0x05:	ic->f = instr(fdiv_dsd); break;
-			case 0x15:	ic->f = instr(fdiv_ddd); break;
-			default:if (!cpu->translation_readahead)
-					fatal("Unimplemented fdiv combination 0x%x.\n",
-					    (iword >> 5) & 0x3f);
-				goto bad;
-			}
-			break;
-
-		default:goto bad;
-		}
-		break;
-
-	case 0x30:	/*  br     */
-	case 0x31:	/*  br.n   */
-	case 0x32:	/*  bsr    */
-	case 0x33:	/*  bsr.n  */
-		switch (op26) {
-		case 0x30:
-			ic->f = instr(br);
-			samepage_function = instr(br_samepage);
-			if (cpu->translation_readahead > 1)
-				cpu->translation_readahead = 1;
-			break;
-		case 0x31:
-			ic->f = instr(br_n);
-			if (cpu->translation_readahead > 2)
-				cpu->translation_readahead = 2;
-			break;
-		case 0x32:
-			ic->f = instr(bsr);
-			samepage_function = instr(bsr_samepage);
-			break;
-		case 0x33:
-			ic->f = instr(bsr_n);
-			break;
-		}
-
-		offset = (addr & 0xffc) + d26;
-
-		/*  Prepare both samepage and offset style args.
-		    (Only one will be used in the actual instruction.)  */
-		ic->arg[0] = (size_t) ( cpu->cd.m88k.cur_ic_page +
-		    (offset >> M88K_INSTR_ALIGNMENT_SHIFT) );
-		ic->arg[1] = offset;
-		ic->arg[2] = (addr & 0xffc) + 4;    /*  Return offset
-							for bsr_samepage  */
-
-		if (offset >= 0 && offset <= 0xffc &&
-		    samepage_function != NULL)
-			ic->f = samepage_function;
-
-		if (cpu->machine->show_trace_tree) {
-			if (op26 == 0x32)
-				ic->f = instr(bsr_trace);
-			if (op26 == 0x33)
-				ic->f = instr(bsr_n_trace);
-		}
-
-		break;
-
-	case 0x34:	/*  bb0     */
-	case 0x35:	/*  bb0.n   */
-	case 0x36:	/*  bb1     */
-	case 0x37:	/*  bb1.n   */
-		switch (op26) {
-		case 0x34:
-			ic->f = instr(bb0);
-			samepage_function = instr(bb0_samepage);
-			break;
-		case 0x35:
-			ic->f = instr(bb0_n);
-			break;
-		case 0x36:
-			ic->f = instr(bb1);
-			samepage_function = instr(bb1_samepage);
-			break;
-		case 0x37:
-			ic->f = instr(bb1_n);
-			break;
-		}
-
-		ic->arg[0] = (size_t) &cpu->cd.m88k.r[s1];
-		ic->arg[1] = (uint32_t) (1 << d);
-
-		offset = (addr & 0xffc) + d16;
-		ic->arg[2] = offset;
-
-		if (offset >= 0 && offset <= 0xffc &&
-		    samepage_function != NULL) {
-			ic->f = samepage_function;
-			ic->arg[2] = (size_t) ( cpu->cd.m88k.cur_ic_page +
-			    (offset >> M88K_INSTR_ALIGNMENT_SHIFT) );
-		}
-		break;
-
-	case 0x3a:	/*  bcnd    */
-	case 0x3b:	/*  bcnd.n  */
-		ic->f = m88k_bcnd[d + 32 * (op26 & 1)];
-		samepage_function = m88k_bcnd[64 + d + 32 * (op26 & 1)];
-
-		if (ic->f == NULL)
-			goto bad;
-
-		ic->arg[0] = (size_t) &cpu->cd.m88k.r[s1];
-
-		offset = (addr & 0xffc) + d16;
-		ic->arg[2] = offset;
-
-		if (offset >= 0 && offset <= 0xffc &&
-		    samepage_function != NULL) {
-			ic->f = samepage_function;
-			ic->arg[2] = (size_t) ( cpu->cd.m88k.cur_ic_page +
-			    (offset >> M88K_INSTR_ALIGNMENT_SHIFT) );
-		}
-
-		if ((iword & 0xffe0ffff) == 0xe840ffff ||
-		    (iword & 0xffe0ffff) == 0xe840fffe)
-			cpu->cd.m88k.combination_check = COMBINE(idle);
-
-		break;
-
-	case 0x3c:
-		switch (op10) {
-
-		case 0x20:	/*  clr  */
-		case 0x22:	/*  set  */
-		case 0x24:	/*  ext  */
-		case 0x26:	/*  extu  */
-		case 0x28:	/*  mak  */
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[2] = iword & 0x3ff;
-
-			switch (op10) {
-			case 0x20: ic->f = instr(mask_imm);
-				   {
-					int w = ic->arg[2] >> 5;
-					int o = ic->arg[2] & 0x1f;
-					uint32_t x = w == 0? 0xffffffff
-					    : ((uint32_t)1 << w) - 1;
-					x <<= o;
-					ic->arg[2] = ~x;
-				   }
-				   break;
-			case 0x22: ic->f = instr(or_imm);
-				   {
-					int w = ic->arg[2] >> 5;
-					int o = ic->arg[2] & 0x1f;
-					uint32_t x = w == 0? 0xffffffff
-					    : ((uint32_t)1 << w) - 1;
-					x <<= o;
-					ic->arg[2] = x;
-				   }
-				   break;
-			case 0x24: ic->f = instr(ext_imm); break;
-			case 0x26: ic->f = instr(extu_imm); break;
-			case 0x28: ic->f = instr(mak_imm); break;
-			}
-
-			if (d == M88K_ZERO_REG)
-				ic->f = instr(nop);
-			break;
-
-		case 0x34:	/*  tb0  */
-		case 0x36:	/*  tb1  */
-			ic->arg[0] = 1 << d;
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[2] = iword & 0x1ff;
-			switch (op10) {
-			case 0x34: ic->f = instr(tb0); break;
-			case 0x36: ic->f = instr(tb1); break;
-			}
-			break;
-
-		default:goto bad;
-		}
-		break;
-
-	case 0x3d:
-		if ((iword & 0xf000) <= 0x3fff ) {
-			/*  Load, Store, xmem, and lda:  */
-			int op = 0, opsize, user = 0, wt = 0;
-			int signedness = 1, scaled = 0;
-
-			switch (iword & 0xf000) {
-			case 0x2000: op = 1; /* st */  break;
-			case 0x3000: op = 2; /* lda */ break;
-			default:     if ((iword & 0xf800) >= 0x0800)
-					op = 0; /* ld */
-				     else
-					op = 3; /* xmem */
-			}
-
-			/*  for (most) ld, st, lda:  */
-			opsize = (iword >> 10) & 3;
-
-			/*  Turn opsize into x, where size = 1 << x:  */
-			opsize = 3 - opsize;
-
-			if (op == 3) {
-				/*  xmem:  */
-				switch ((iword >> 10) & 3) {
-				case 0: opsize = 0; break;
-				case 1: opsize = 2; break;
-				default:fatal("Weird xmem opsize/type?\n");
-					goto bad;
-				}
-			} else {
-				if ((iword & 0xf800) == 0x800) {
-					signedness = 0;
-					if ((iword & 0xf00) < 0xc00)
-						opsize = 1;
-					else
-						opsize = 0;
-				} else {
-					if (opsize >= 2 || op == 1)
-						signedness = 0;
-				}
-			}
-
-			if (iword & 0x100)
-				user = 1;
-			if (iword & 0x80)
-				wt = 1;
-			if (iword & 0x200)
-				scaled = 1;
-
-			if (wt) {
-				fatal("wt bit not yet implemented! TODO\n");
-				goto bad;
-			}
-
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
-
-			if (op == 0 || op == 1) {
-				/*  ld or st:  */
-				ic->f = m88k_loadstore[ opsize
-				    + (op==1? M88K_LOADSTORE_STORE : 0)
-				    + (signedness? M88K_LOADSTORE_SIGNEDNESS:0)
-				    + (cpu->byte_order == EMUL_BIG_ENDIAN?
-				       M88K_LOADSTORE_ENDIANNESS : 0)
-				    + (scaled? M88K_LOADSTORE_SCALEDNESS : 0)
-				    + (user? M88K_LOADSTORE_USR : 0)
-				    + M88K_LOADSTORE_REGISTEROFFSET ];
-
-				if (d == M88K_ZERO_REG && op == 0)
-					ic->arg[0] = (size_t)&cpu->cd.m88k.zero_scratch;
-
-				if (opsize == 3 && d == 31) {
-					fatal("m88k load/store of register "
-					    "pair r31/r0: TODO\n");
-					goto bad;
-				}
-			} else if (op == 2) {
-				/*  lda:  */
-				if (scaled) {
-					switch (opsize) {
-					case 0: ic->f = instr(addu); break;
-					case 1: ic->f = instr(lda_reg_2); break;
-					case 2: ic->f = instr(lda_reg_4); break;
-					case 3: ic->f = instr(lda_reg_8); break;
-					}
-				} else {
-					ic->f = instr(addu);
-				}
-				if (d == M88K_ZERO_REG)
-					ic->f = instr(nop);
-			} else {
-				/*  xmem:  */
-				ic->f = instr(xmem_slow);
-				ic->arg[0] = iword;
-				if (d == M88K_ZERO_REG)
-					ic->f = instr(nop);
-			}
-		} else switch ((iword >> 8) & 0xff) {
-		case 0x40:	/*  and    */
-		case 0x44:	/*  and.c  */
-		case 0x50:	/*  xor    */
-		case 0x54:	/*  xor.c  */
-		case 0x58:	/*  or     */
-		case 0x5c:	/*  or.c   */
-		case 0x60:	/*  addu   */
-		case 0x61:	/*  addu.co  */
-		case 0x62:	/*  addu.ci  */
-		case 0x64:	/*  subu   */
-		case 0x65:	/*  subu.co  */
-		case 0x66:	/*  subu.ci  */
-		case 0x68:	/*  divu   */
-		case 0x6c:	/*  mul    */
-		case 0x70:	/*  add    */
-		case 0x78:	/*  div    */
-		case 0x7c:	/*  cmp    */
-		case 0x80:	/*  clr    */
-		case 0x88:	/*  set    */
-		case 0x90:	/*  ext    */
-		case 0x98:	/*  extu   */
-		case 0xa0:	/*  mak    */
-		case 0xa8:	/*  rot    */
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
-			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
-
-			switch ((iword >> 8) & 0xff) {
-			case 0x40: ic->f = instr(and);   break;
-			case 0x44: ic->f = instr(and_c); break;
-			case 0x50: ic->f = instr(xor);   break;
-			case 0x54: ic->f = instr(xor_c); break;
-			case 0x58: ic->f = instr(or);    break;
-			case 0x5c: ic->f = instr(or_c);  break;
-			case 0x60: ic->f = instr(addu);  break;
-			case 0x61: ic->f = instr(addu_co); break;
-			case 0x62: ic->f = instr(addu_ci); break;
-			case 0x64: ic->f = instr(subu);  break;
-			case 0x65: ic->f = instr(subu_co); break;
-			case 0x66: ic->f = instr(subu_ci); break;
-			case 0x68: ic->f = instr(divu);  break;
-			case 0x6c: ic->f = instr(mul);   break;
-			case 0x70: ic->f = instr(add);   break;
-			case 0x78: ic->f = instr(div);   break;
-			case 0x7c: ic->f = instr(cmp);   break;
-			case 0x80: ic->f = instr(clr);   break;
-			case 0x88: ic->f = instr(set);   break;
-			case 0x90: ic->f = instr(ext);   break;
-			case 0x98: ic->f = instr(extu);  break;
-			case 0xa0: ic->f = instr(mak);   break;
-			case 0xa8: ic->f = instr(rot);   break;
-			}
-
-			/*  Optimization for  or rX,r0,rY  etc:  */
-			if (s1 == M88K_ZERO_REG && ic->f == instr(or))
-				ic->f = instr(or_r0);
-			if (s2 == M88K_ZERO_REG && ic->f == instr(addu))
-				ic->f = instr(addu_s2r0);
-
-			/*
-			 *  Handle the case when the destination register is r0:
-			 *
-			 *  If there is NO SIDE-EFFECT! (i.e. no carry out),
-			 *  then replace the instruction with a nop. If there is
-			 *  a side-effect, we still have to run the instruction,
-			 *  so replace the destination register with a scratch
-			 *  register.
-			 */
-			if (d == M88K_ZERO_REG) {
-				int opc = (iword >> 8) & 0xff;
-				if (opc != 0x61 /* addu.co */ && opc != 0x63 /* addu.cio */ &&
-				    opc != 0x65 /* subu.co */ && opc != 0x67 /* subu.cio */ &&
-				    opc != 0x71 /*  add.co */ && opc != 0x73 /*  add.cio */ &&
-				    opc != 0x75 /*  sub.co */ && opc != 0x77 /*  sub.cio */ &&
-				    opc != 0x68 /*  divu   */ && opc != 0x69 /* divu.d   */ &&
-				    opc != 0x6c /*  mul    */ && opc != 0x6d /* mulu.d   */ &&
-				    opc != 0x6e /*  muls   */ && opc != 0x78 /*  div     */)
-					ic->f = instr(nop);
-				else
-					ic->arg[0] = (size_t)
-					    &cpu->cd.m88k.zero_scratch;
-			}
-			break;
-		case 0xc0:	/*  jmp    */
-		case 0xc4:	/*  jmp.n  */
-		case 0xc8:	/*  jsr    */
-		case 0xcc:	/*  jsr.n  */
-			switch ((iword >> 8) & 0xff) {
-			case 0xc0: ic->f = instr(jmp);
-				   if (cpu->translation_readahead > 1)
-					cpu->translation_readahead = 1;
-				   break;
-			case 0xc4: ic->f = instr(jmp_n);
-				   if (cpu->translation_readahead > 2)
-					cpu->translation_readahead = 2;
-				   break;
-			case 0xc8: ic->f = instr(jsr); break;
-			case 0xcc: ic->f = instr(jsr_n); break;
-			}
-
-			ic->arg[1] = (addr & 0xffc) + 4;
-			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
-
-			if (((iword >> 8) & 0x04) == 0x04)
-				ic->arg[1] = (addr & 0xffc) + 8;
-
-			if (cpu->machine->show_trace_tree &&
-			    s2 == M88K_RETURN_REG) {
-				if (ic->f == instr(jmp))
-					ic->f = instr(jmp_trace);
-				if (ic->f == instr(jmp_n))
-					ic->f = instr(jmp_n_trace);
-			}
-			if (cpu->machine->show_trace_tree) {
-				if (ic->f == instr(jsr))
-					ic->f = instr(jsr_trace);
-				if (ic->f == instr(jsr_n))
-					ic->f = instr(jsr_n_trace);
-			}
-			break;
-		case 0xe8:	/*  ff1  */
-		case 0xec:      /*  ff0  */
-			switch ((iword >> 8) & 0xff) {
-			case 0xe8: ic->f = instr(ff1); break;
-			case 0xec: ic->f = instr(ff0); break;
-			}
-
-			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
-			ic->arg[2] = (size_t) &cpu->cd.m88k.r[s2];
-
-			if (d == M88K_ZERO_REG)
-				ic->f = instr(nop);
-			break;
-		case 0xfc:
-			switch (iword & 0xff) {
-			case 0x00:
-				if (iword == 0xf400fc00)
-					ic->f = instr(rte);
-				else {
-					fatal("unimplemented rte variant: 0x%08" PRIx32"\n", iword);
-					goto bad;
-				}
-				break;
-			case (M88K_PROM_INSTR & 0xff):
-				ic->f = instr(prom_call);
-				break;
-			default:fatal("Unimplemented 3d/fc instruction\n");
-				goto bad;
-			}
-			break;
-		default:goto bad;
-		}
-		break;
-
-	default:goto bad;
-	}
-
-
-#define	DYNTRANS_TO_BE_TRANSLATED_TAIL
-#include "cpu_dyntrans.cc" 
-#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_m88k_instr_loadstore.c gxemul-0.7.0+dfsg/src/cpus/cpu_m88k_instr_loadstore.c
--- gxemul-0.6.2/src/cpus/cpu_m88k_instr_loadstore.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_m88k_instr_loadstore.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,466 @@
+/*
+ *  Copyright (C) 2007-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  M88K load/store instructions; the following args are used:
+ *  
+ *  arg[0] = pointer to the register to load to or store from (d)
+ *  arg[1] = pointer to the base register (s1)
+ *  arg[2] = pointer to the offset register (s2), or an uint32_t offset
+ *
+ *  The GENERIC function always checks for alignment, and supports both big
+ *  and little endian byte order.
+ *
+ *  The quick function is included twice (big/little endian) for each
+ *  GENERIC function.
+ *
+ *
+ *  Defines:
+ *	LS_LOAD or LS_STORE (only one)
+ *	LS_INCLUDE_GENERIC (to generate the generic function)
+ *	LS_GENERIC_N is defined as the name of the generic function
+ *	LS_NO_PC_SYNC is defined to skip Program Counter sync in the generic function
+ *	LS_N is defined as the name of the fast function
+ *	LS_1, LS_2, LS_4, or LS_8 (only one)
+ *	LS_SIZE is defined to 1, 2, 4, or 8
+ *	LS_SIGNED is defined for signed loads
+ *	LS_LE or LS_BE (only one)
+ *	LS_SCALED for scaled accesses
+ *	LS_USR for usr accesses
+ *	LS_REGOFS is defined when arg[2] is a register pointer
+ */
+
+
+#ifdef LS_INCLUDE_GENERIC
+void LS_GENERIC_N(struct cpu *cpu, struct m88k_instr_call *ic)
+{
+#ifdef LS_USR
+	const int memory_rw_flags = CACHE_DATA | MEMORY_USER_ACCESS;
+#else
+	const int memory_rw_flags = CACHE_DATA;
+#endif
+	uint32_t addr = reg(ic->arg[1]) +
+#ifdef LS_REGOFS
+#ifdef LS_SCALED
+	    LS_SIZE *
+#endif
+	    reg(ic->arg[2]);
+#else
+	    ic->arg[2];
+#endif
+	uint8_t data[LS_SIZE];
+	uint64_t x;
+
+#ifndef LS_NO_PC_SYNC
+	/*  Synchronize the PC:  */
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page)
+	    / sizeof(struct m88k_instr_call);
+	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1)<<M88K_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << M88K_INSTR_ALIGNMENT_SHIFT);
+#endif
+
+	/*
+	 *  Update the memory transaction registers:
+	 */
+	cpu->cd.m88k.dmt[1] = 0;
+
+	cpu->cd.m88k.dmt[0] = DMT_VALID;
+#ifdef LS_STORE
+	cpu->cd.m88k.dmt[0] |= DMT_WRITE;
+#else
+	{
+		int dreg = (((uint32_t *)ic->arg[0]) - &cpu->cd.m88k.r[0]);
+		if (dreg < 1 || dreg > 31) {
+			debugmsg_cpu(cpu, SUBSYS_CPU, "m88k load/store",
+			    VERBOSITY_ERROR,
+			    "HUH? dreg = %i in cpu_m88k_instr_loadstore.c."
+			    " Internal error.", dreg);
+			cpu->running = 0;
+			cpu->cd.m88k.next_ic = &nothing_call;
+			return;
+		}
+		cpu->cd.m88k.dmt[0] |= dreg << DMT_DREGSHIFT;
+	}
+#ifdef LS_SIGNED
+	cpu->cd.m88k.dmt[0] |= DMT_SIGNED;
+#endif
+#endif
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		cpu->cd.m88k.dmt[0] |= DMT_BO;
+
+#ifndef LS_USR
+	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)
+		cpu->cd.m88k.dmt[0] |= DMT_DAS;		/*  supervisor  */
+#endif
+
+	/*  EN bits:  */
+#ifdef LS_1
+	/*  TODO: Is the EN offset only valid for Big-Endian?  */
+	cpu->cd.m88k.dmt[0] |= 1 << DMT_ENSHIFT << (3 - (addr & 3));
+#else
+#ifdef LS_2
+	cpu->cd.m88k.dmt[0] |= 3 << DMT_ENSHIFT << (2 - (addr & 2));
+#else
+	cpu->cd.m88k.dmt[0] |= 0xf << DMT_ENSHIFT;
+#endif
+#endif
+
+	cpu->cd.m88k.dma[0] = addr & ~0x3;
+	cpu->cd.m88k.dmd[0] = 0;
+
+#ifdef LS_8
+	cpu->cd.m88k.dmt[1] = cpu->cd.m88k.dmt[0];
+	cpu->cd.m88k.dmt[0] |= DMT_DOUB1;
+	cpu->cd.m88k.dma[1] = cpu->cd.m88k.dma[0] + sizeof(uint32_t);
+	cpu->cd.m88k.dmd[1] = 0;
+#ifdef LS_LOAD
+	{
+		int dreg = (((uint32_t *)ic->arg[0]) - &cpu->cd.m88k.r[0]);
+		dreg ++;
+		if (dreg < 1 || dreg > 31) {
+			debugmsg_cpu(cpu, SUBSYS_CPU, "m88k load/store",
+			    VERBOSITY_ERROR,
+			    "HUH? dreg = %i in cpu_m88k_instr_loadstore.c."
+			    " Internal error.", dreg);
+			cpu->running = 0;
+			cpu->cd.m88k.next_ic = &nothing_call;
+			return;
+		}
+		cpu->cd.m88k.dmt[1] &= ~((0x1f) << DMT_DREGSHIFT);
+		cpu->cd.m88k.dmt[1] |= dreg << DMT_DREGSHIFT;
+	}
+#endif
+#endif
+
+
+#ifdef LS_USR
+	if (!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)) {
+		/*  Cause a privilege violation exception:  */
+		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
+		return;
+	}
+#endif
+
+#ifndef LS_1
+	/*  Check alignment:  */
+	if (addr & (LS_SIZE - 1)) {
+#if 1
+		/*  Cause an address alignment exception:  */
+		m88k_exception(cpu, M88K_EXCEPTION_MISALIGNED_ACCESS, 0);
+#else
+		fatal("{ m88k dyntrans alignment exception, size = %i,"
+		    " addr = %08" PRIx32", pc = %08" PRIx32" }\n", LS_SIZE,
+		    (uint32_t) addr, (uint32_t) cpu->pc);
+
+		cpu->running = 0;
+		cpu->cd.m88k.next_ic = &nothing_call;
+
+		if (cpu->delay_slot)
+			cpu->delay_slot |= EXCEPTION_IN_DELAY_SLOT;
+#endif
+		return;
+	}
+#endif
+
+#ifdef LS_LOAD
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
+	    MEM_READ, memory_rw_flags)) {
+		/*  Exception or aborted execution.  */
+		if (!cpu->running)
+			cpu->cd.m88k.next_ic = &nothing_call;
+		return;
+	}
+	x = memory_readmax64(cpu, data, LS_SIZE);
+#ifdef LS_8
+	if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+		reg(ic->arg[0]) = x >> 32;
+		reg(ic->arg[0] + 4) = x;
+	} else {
+		reg(ic->arg[0]) = x;
+		reg(ic->arg[0] + 4) = x >> 32;
+	}
+#else
+#ifdef LS_SIGNED
+#ifdef LS_1
+	x = (int8_t)x;
+#endif
+#ifdef LS_2
+	x = (int16_t)x;
+#endif
+#ifdef LS_4
+	x = (int32_t)x;
+#endif
+#endif
+	reg(ic->arg[0]) = x;
+#endif
+
+#else	/*  LS_STORE:  */
+
+#ifdef LS_8
+	if (cpu->byte_order == EMUL_BIG_ENDIAN)
+		x = ((uint64_t)reg(ic->arg[0]) << 32) + reg(ic->arg[0] + 4);
+	else
+		x = ((uint64_t)reg(ic->arg[0] + 4) << 32) + reg(ic->arg[0]);
+	cpu->cd.m88k.dmd[0] = reg(ic->arg[0]);
+	cpu->cd.m88k.dmd[1] = reg(ic->arg[0] + 4);
+#else
+	x = reg(ic->arg[0]);
+	cpu->cd.m88k.dmd[0] = x;
+#endif
+	memory_writemax64(cpu, data, LS_SIZE, x);
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
+	    MEM_WRITE, memory_rw_flags)) {
+		/*  Exception or aborted execution.  */
+		if (!cpu->running)
+			cpu->cd.m88k.next_ic = &nothing_call;
+		return;
+	}
+#endif
+}
+#endif	/*  LS_INCLUDE_GENERIC  */
+
+
+void LS_N(struct cpu *cpu, struct m88k_instr_call *ic)
+{
+	uint32_t addr = reg(ic->arg[1]) +
+#ifdef LS_REGOFS
+#ifdef LS_SCALED
+	    LS_SIZE *
+#endif
+	    reg(ic->arg[2]);
+#else
+	    ic->arg[2];
+#endif
+
+#ifdef LS_USR
+#ifdef LS_LOAD
+	uint8_t *p = cpu->cd.m88k.host_load_usr[addr >> 12];
+#else
+	uint8_t *p = cpu->cd.m88k.host_store_usr[addr >> 12];
+#endif
+#else
+#ifdef LS_LOAD
+	uint8_t *p = cpu->cd.m88k.host_load[addr >> 12];
+#else
+	uint8_t *p = cpu->cd.m88k.host_store[addr >> 12];
+#endif
+#endif
+
+	/*
+	 *  Call the generic function, if things become too complicated:
+	 *
+	 *  1)  .usr used in non-supervisor mode
+	 *  2)  the page pointer is NULL
+	 *  3)  unaligned access
+	 */
+	if (unlikely(
+#ifdef LS_USR
+	    !(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE) ||
+#endif
+
+	    p == NULL
+#ifndef LS_1
+	    || addr & (LS_SIZE - 1)
+#endif
+	    )) {
+		LS_GENERIC_N(cpu, ic);
+		return;
+	}
+
+	addr &= 0xfff;
+
+#ifdef LS_LOAD
+	/*  Load:  */
+
+#ifdef LS_1
+	reg(ic->arg[0]) =
+#ifdef LS_SIGNED
+	    (int8_t)
+#endif
+	    p[addr];
+#endif	/*  LS_1  */
+
+#ifdef LS_2
+	reg(ic->arg[0]) =
+#ifdef LS_SIGNED
+	    (int16_t)
+#endif
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	    ( *(uint16_t *)(p + addr) );
+#else
+	    ((p[addr]<<8) + p[addr+1]);
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	    ( *(uint16_t *)(p + addr) );
+#else
+	    (p[addr] + (p[addr+1]<<8));
+#endif
+#endif
+#endif	/*  LS_2  */
+
+#ifdef LS_4
+	reg(ic->arg[0]) =
+#ifdef LS_SIGNED
+	    (int32_t)
+#else
+	    (uint32_t)
+#endif
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	    ( *(uint32_t *)(p + addr) );
+#else
+	    ((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]);
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	    ( *(uint32_t *)(p + addr) );
+#else
+	    (p[addr] + (p[addr+1]<<8) + (p[addr+2]<<16) + (p[addr+3]<<24));
+#endif
+#endif
+#endif	/*  LS_4  */
+
+#ifdef LS_8
+
+	/*  Load first word in pair:  */
+	reg(ic->arg[0]) =
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	    ( *(uint32_t *)(p + addr) );
+#else
+	    ((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]);
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	    ( *(uint32_t *)(p + addr + 4) );
+#else
+	    (p[addr+4] + (p[addr+5]<<8) + (p[addr+6]<<16) + (p[addr+7]<<24));
+#endif
+#endif
+
+	/*  Load second word in pair:  */
+	reg(ic->arg[0] + 4) =
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	    ( *(uint32_t *)(p + addr + 4) );
+#else
+	    ((p[addr+4]<<24) + (p[addr+5]<<16) + (p[addr+6]<<8) + p[addr+7]);
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	    ( *(uint32_t *)(p + addr) );
+#else
+	    (p[addr] + (p[addr+1]<<8) + (p[addr+2]<<16) + (p[addr+3]<<24));
+#endif
+#endif
+
+#endif	/*  LS_8  */
+
+#else
+	/*  Store: */
+
+#ifdef LS_1
+	p[addr] = reg(ic->arg[0]);
+#endif
+#ifdef LS_2
+	{ uint32_t x = reg(ic->arg[0]);
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	*((uint16_t *)(p+addr)) = x; }
+#else
+	p[addr] = x >> 8; p[addr+1] = x; }
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	*((uint16_t *)(p+addr)) = x; }
+#else
+	p[addr] = x; p[addr+1] = x >> 8; }
+#endif
+#endif
+#endif  /*  LS_2  */
+#ifdef LS_4
+	{ uint32_t x = reg(ic->arg[0]);
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	*((uint32_t *)(p+addr)) = x; }
+#else
+	p[addr] = x >> 24; p[addr+1] = x >> 16; 
+	p[addr+2] = x >> 8; p[addr+3] = x; }
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	*((uint32_t *)(p+addr)) = x; }
+#else
+	p[addr] = x; p[addr+1] = x >> 8; 
+	p[addr+2] = x >> 16; p[addr+3] = x >> 24; }
+#endif
+#endif
+#endif  /*  LS_4  */
+#ifdef LS_8
+
+	/*  First word in pair:  */
+	{ uint32_t x = reg(ic->arg[0]);
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	*((uint32_t *)(p+addr)) = x; }
+#else
+	p[addr]   = x >> 24; p[addr+1] = x >> 16;
+	p[addr+2] = x >> 8;  p[addr+3] = x; }
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	*((uint32_t *)(p+addr+4)) = x; }
+#else
+	p[addr  +4] = x;        p[addr+1+4] = x >> 8;
+	p[addr+2+4] = x >> 16;  p[addr+3+4] = x >> 24; }
+#endif
+#endif
+
+	/*  Second word in pair:  */
+	{ uint32_t x = reg(ic->arg[0] + 4);
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	*((uint32_t *)(p+addr+4)) = x; }
+#else
+	p[addr  +4] = x >> 24; p[addr+1+4] = x >> 16;
+	p[addr+2+4] = x >> 8;  p[addr+3+4] = x; }
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	*((uint32_t *)(p+addr)) = x; }
+#else
+	p[addr  ] = x;        p[addr+1] = x >> 8;
+	p[addr+2] = x >> 16;  p[addr+3] = x >> 24; }
+#endif
+#endif
+
+#endif	/*  LS_8  */
+
+#endif	/*  store  */
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_m88k_instr_loadstore.cc gxemul-0.7.0+dfsg/src/cpus/cpu_m88k_instr_loadstore.cc
--- gxemul-0.6.2/src/cpus/cpu_m88k_instr_loadstore.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_m88k_instr_loadstore.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,453 +0,0 @@
-/*
- *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  M88K load/store instructions; the following args are used:
- *  
- *  arg[0] = pointer to the register to load to or store from (d)
- *  arg[1] = pointer to the base register (s1)
- *  arg[2] = pointer to the offset register (s2), or an uint32_t offset
- *
- *  The GENERIC function always checks for alignment, and supports both big
- *  and little endian byte order.
- *
- *  The quick function is included twice (big/little endian) for each
- *  GENERIC function.
- *
- *
- *  Defines:
- *	LS_LOAD or LS_STORE (only one)
- *	LS_INCLUDE_GENERIC (to generate the generic function)
- *	LS_GENERIC_N is defined as the name of the generic function
- *	LS_N is defined as the name of the fast function
- *	LS_1, LS_2, LS_4, or LS_8 (only one)
- *	LS_SIZE is defined to 1, 2, 4, or 8
- *	LS_SIGNED is defined for signed loads
- *	LS_LE or LS_BE (only one)
- *	LS_SCALED for scaled accesses
- *	LS_USR for usr accesses
- *	LS_REGOFS is defined when arg[2] is a register pointer
- */
-
-
-#ifdef LS_INCLUDE_GENERIC
-void LS_GENERIC_N(struct cpu *cpu, struct m88k_instr_call *ic)
-{
-#ifdef LS_USR
-	const int memory_rw_flags = CACHE_DATA | MEMORY_USER_ACCESS;
-#else
-	const int memory_rw_flags = CACHE_DATA;
-#endif
-	uint32_t addr = reg(ic->arg[1]) +
-#ifdef LS_REGOFS
-#ifdef LS_SCALED
-	    LS_SIZE *
-#endif
-	    reg(ic->arg[2]);
-#else
-	    ic->arg[2];
-#endif
-	uint8_t data[LS_SIZE];
-	uint64_t x;
-
-	/*  Synchronize the PC:  */
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page)
-	    / sizeof(struct m88k_instr_call);
-	cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1)<<M88K_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << M88K_INSTR_ALIGNMENT_SHIFT);
-
-	/*
-	 *  Update the memory transaction registers:
-	 */
-	cpu->cd.m88k.dmt[1] = 0;
-
-	cpu->cd.m88k.dmt[0] = DMT_VALID;
-#ifdef LS_STORE
-	cpu->cd.m88k.dmt[0] |= DMT_WRITE;
-#else
-	{
-		int dreg = (((uint32_t *)ic->arg[0]) - &cpu->cd.m88k.r[0]);
-		if (dreg < 1 || dreg > 31) {
-			fatal("HUH? dreg = %i in cpu_m88k_instr_loadstore.c."
-			    " Internal error.\n", dreg);
-			exit(1);
-		}
-		cpu->cd.m88k.dmt[0] |= dreg << DMT_DREGSHIFT;
-	}
-#ifdef LS_SIGNED
-	cpu->cd.m88k.dmt[0] |= DMT_SIGNED;
-#endif
-#endif
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		cpu->cd.m88k.dmt[0] |= DMT_BO;
-
-#ifndef LS_USR
-	if (cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)
-		cpu->cd.m88k.dmt[0] |= DMT_DAS;		/*  supervisor  */
-#endif
-
-	/*  EN bits:  */
-#ifdef LS_1
-	/*  TODO: Is the EN offset only valid for Big-Endian?  */
-	cpu->cd.m88k.dmt[0] |= 1 << DMT_ENSHIFT << (3 - (addr & 3));
-#else
-#ifdef LS_2
-	cpu->cd.m88k.dmt[0] |= 3 << DMT_ENSHIFT << (2 - (addr & 2));
-#else
-	cpu->cd.m88k.dmt[0] |= 0xf << DMT_ENSHIFT;
-#endif
-#endif
-
-	cpu->cd.m88k.dma[0] = addr & ~0x3;
-	cpu->cd.m88k.dmd[0] = 0;
-
-#ifdef LS_8
-	cpu->cd.m88k.dmt[1] = cpu->cd.m88k.dmt[0];
-	cpu->cd.m88k.dmt[0] |= DMT_DOUB1;
-	cpu->cd.m88k.dma[1] = cpu->cd.m88k.dma[0] + sizeof(uint32_t);
-	cpu->cd.m88k.dmd[1] = 0;
-#ifdef LS_LOAD
-	{
-		int dreg = (((uint32_t *)ic->arg[0]) - &cpu->cd.m88k.r[0]);
-		dreg ++;
-		if (dreg < 1 || dreg > 31) {
-			fatal("HUH? dreg = %i in cpu_m88k_instr_loadstore.c."
-			    " Internal error.\n", dreg);
-			exit(1);
-		}
-		cpu->cd.m88k.dmt[1] &= ~((0x1f) << DMT_DREGSHIFT);
-		cpu->cd.m88k.dmt[1] |= dreg << DMT_DREGSHIFT;
-	}
-#endif
-#endif
-
-
-#ifdef LS_USR
-	if (!(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE)) {
-		/*  Cause a privilege violation exception:  */
-		m88k_exception(cpu, M88K_EXCEPTION_PRIVILEGE_VIOLATION, 0);
-		return;
-	}
-#endif
-
-#ifndef LS_1
-	/*  Check alignment:  */
-	if (addr & (LS_SIZE - 1)) {
-#if 0
-		/*  Cause an address alignment exception:  */
-		m88k_exception(cpu, M88K_EXCEPTION_MISALIGNED_ACCESS, 0);
-#else
-		fatal("{ m88k dyntrans alignment exception, size = %i,"
-		    " addr = %08" PRIx32", pc = %08" PRIx32" }\n", LS_SIZE,
-		    (uint32_t) addr, (uint32_t) cpu->pc);
-
-		/*  TODO: Generalize this into a abort_call, or similar:  */
-		cpu->running = 0;
-		debugger_n_steps_left_before_interaction = 0;
-		cpu->cd.m88k.next_ic = &nothing_call;
-
-		if (cpu->delay_slot)
-			cpu->delay_slot |= EXCEPTION_IN_DELAY_SLOT;
-#endif
-		return;
-	}
-#endif
-
-#ifdef LS_LOAD
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
-	    MEM_READ, memory_rw_flags)) {
-		/*  Exception.  */
-		return;
-	}
-	x = memory_readmax64(cpu, data, LS_SIZE);
-#ifdef LS_8
-	if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-		reg(ic->arg[0]) = x >> 32;
-		reg(ic->arg[0] + 4) = x;
-	} else {
-		reg(ic->arg[0]) = x;
-		reg(ic->arg[0] + 4) = x >> 32;
-	}
-#else
-#ifdef LS_SIGNED
-#ifdef LS_1
-	x = (int8_t)x;
-#endif
-#ifdef LS_2
-	x = (int16_t)x;
-#endif
-#ifdef LS_4
-	x = (int32_t)x;
-#endif
-#endif
-	reg(ic->arg[0]) = x;
-#endif
-
-#else	/*  LS_STORE:  */
-
-#ifdef LS_8
-	if (cpu->byte_order == EMUL_BIG_ENDIAN)
-		x = ((uint64_t)reg(ic->arg[0]) << 32) + reg(ic->arg[0] + 4);
-	else
-		x = ((uint64_t)reg(ic->arg[0] + 4) << 32) + reg(ic->arg[0]);
-	cpu->cd.m88k.dmd[0] = reg(ic->arg[0]);
-	cpu->cd.m88k.dmd[1] = reg(ic->arg[0] + 4);
-#else
-	x = reg(ic->arg[0]);
-	cpu->cd.m88k.dmd[0] = x;
-#endif
-	memory_writemax64(cpu, data, LS_SIZE, x);
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
-	    MEM_WRITE, memory_rw_flags)) {
-		/*  Exception.  */
-		return;
-	}
-#endif
-}
-#endif	/*  LS_INCLUDE_GENERIC  */
-
-
-void LS_N(struct cpu *cpu, struct m88k_instr_call *ic)
-{
-	uint32_t addr = reg(ic->arg[1]) +
-#ifdef LS_REGOFS
-#ifdef LS_SCALED
-	    LS_SIZE *
-#endif
-	    reg(ic->arg[2]);
-#else
-	    ic->arg[2];
-#endif
-
-#ifdef LS_USR
-#ifdef LS_LOAD
-	uint8_t *p = cpu->cd.m88k.host_load_usr[addr >> 12];
-#else
-	uint8_t *p = cpu->cd.m88k.host_store_usr[addr >> 12];
-#endif
-#else
-#ifdef LS_LOAD
-	uint8_t *p = cpu->cd.m88k.host_load[addr >> 12];
-#else
-	uint8_t *p = cpu->cd.m88k.host_store[addr >> 12];
-#endif
-#endif
-
-	/*
-	 *  Call the generic function, if things become too complicated:
-	 *
-	 *  1)  .usr used in non-supervisor mode
-	 *  2)  the page pointer is NULL
-	 *  3)  unaligned access
-	 */
-	if (
-#ifdef LS_USR
-	    !(cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE) ||
-#endif
-
-	    p == NULL
-#ifndef LS_1
-	    || addr & (LS_SIZE - 1)
-#endif
-	    ) {
-		LS_GENERIC_N(cpu, ic);
-		return;
-	}
-
-	addr &= 0xfff;
-
-#ifdef LS_LOAD
-	/*  Load:  */
-
-#ifdef LS_1
-	reg(ic->arg[0]) =
-#ifdef LS_SIGNED
-	    (int8_t)
-#endif
-	    p[addr];
-#endif	/*  LS_1  */
-
-#ifdef LS_2
-	reg(ic->arg[0]) =
-#ifdef LS_SIGNED
-	    (int16_t)
-#endif
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	    ( *(uint16_t *)(p + addr) );
-#else
-	    ((p[addr]<<8) + p[addr+1]);
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	    ( *(uint16_t *)(p + addr) );
-#else
-	    (p[addr] + (p[addr+1]<<8));
-#endif
-#endif
-#endif	/*  LS_2  */
-
-#ifdef LS_4
-	reg(ic->arg[0]) =
-#ifdef LS_SIGNED
-	    (int32_t)
-#else
-	    (uint32_t)
-#endif
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	    ( *(uint32_t *)(p + addr) );
-#else
-	    ((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]);
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	    ( *(uint32_t *)(p + addr) );
-#else
-	    (p[addr] + (p[addr+1]<<8) + (p[addr+2]<<16) + (p[addr+3]<<24));
-#endif
-#endif
-#endif	/*  LS_4  */
-
-#ifdef LS_8
-
-	/*  Load first word in pair:  */
-	reg(ic->arg[0]) =
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	    ( *(uint32_t *)(p + addr) );
-#else
-	    ((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]);
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	    ( *(uint32_t *)(p + addr + 4) );
-#else
-	    (p[addr+4] + (p[addr+5]<<8) + (p[addr+6]<<16) + (p[addr+7]<<24));
-#endif
-#endif
-
-	/*  Load second word in pair:  */
-	reg(ic->arg[0] + 4) =
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	    ( *(uint32_t *)(p + addr + 4) );
-#else
-	    ((p[addr+4]<<24) + (p[addr+5]<<16) + (p[addr+6]<<8) + p[addr+7]);
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	    ( *(uint32_t *)(p + addr) );
-#else
-	    (p[addr] + (p[addr+1]<<8) + (p[addr+2]<<16) + (p[addr+3]<<24));
-#endif
-#endif
-
-#endif	/*  LS_8  */
-
-#else
-	/*  Store: */
-
-#ifdef LS_1
-	p[addr] = reg(ic->arg[0]);
-#endif
-#ifdef LS_2
-	{ uint32_t x = reg(ic->arg[0]);
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	*((uint16_t *)(p+addr)) = x; }
-#else
-	p[addr] = x >> 8; p[addr+1] = x; }
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	*((uint16_t *)(p+addr)) = x; }
-#else
-	p[addr] = x; p[addr+1] = x >> 8; }
-#endif
-#endif
-#endif  /*  LS_2  */
-#ifdef LS_4
-	{ uint32_t x = reg(ic->arg[0]);
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	*((uint32_t *)(p+addr)) = x; }
-#else
-	p[addr] = x >> 24; p[addr+1] = x >> 16; 
-	p[addr+2] = x >> 8; p[addr+3] = x; }
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	*((uint32_t *)(p+addr)) = x; }
-#else
-	p[addr] = x; p[addr+1] = x >> 8; 
-	p[addr+2] = x >> 16; p[addr+3] = x >> 24; }
-#endif
-#endif
-#endif  /*  LS_4  */
-#ifdef LS_8
-
-	/*  First word in pair:  */
-	{ uint32_t x = reg(ic->arg[0]);
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	*((uint32_t *)(p+addr)) = x; }
-#else
-	p[addr]   = x >> 24; p[addr+1] = x >> 16;
-	p[addr+2] = x >> 8;  p[addr+3] = x; }
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	*((uint32_t *)(p+addr+4)) = x; }
-#else
-	p[addr  +4] = x;        p[addr+1+4] = x >> 8;
-	p[addr+2+4] = x >> 16;  p[addr+3+4] = x >> 24; }
-#endif
-#endif
-
-	/*  Second word in pair:  */
-	{ uint32_t x = reg(ic->arg[0] + 4);
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	*((uint32_t *)(p+addr+4)) = x; }
-#else
-	p[addr  +4] = x >> 24; p[addr+1+4] = x >> 16;
-	p[addr+2+4] = x >> 8;  p[addr+3+4] = x; }
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	*((uint32_t *)(p+addr)) = x; }
-#else
-	p[addr  ] = x;        p[addr+1] = x >> 8;
-	p[addr+2] = x >> 16;  p[addr+3] = x >> 24; }
-#endif
-#endif
-
-#endif	/*  LS_8  */
-
-#endif	/*  store  */
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_mips.c gxemul-0.7.0+dfsg/src/cpus/cpu_mips.c
--- gxemul-0.6.2/src/cpus/cpu_mips.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_mips.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,2012 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  MIPS core CPU emulation.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <ctype.h>
+#include <unistd.h>
+
+#include "../../config.h"
+
+#include "arcbios.h"
+#include "cop0.h"
+#include "cpu.h"
+#include "cpu_mips.h"
+#include "debugger.h"
+#include "devices.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "mips_cpu_types.h"
+#include "opcodes_mips.h"
+#include "settings.h"
+#include "symbol.h"
+
+
+static const char *exception_names[] = EXCEPTION_NAMES;
+
+static const char *hi6_names[] = HI6_NAMES;
+static const char *regimm_names[] = REGIMM_NAMES;
+static const char *special_names[] = SPECIAL_NAMES;
+static const char *special_rot_names[] = SPECIAL_ROT_NAMES;
+static const char *special2_names[] = SPECIAL2_NAMES;
+static const char *mmi_names[] = MMI_NAMES;
+static const char *mmi0_names[] = MMI0_NAMES;
+static const char *mmi1_names[] = MMI1_NAMES;
+static const char *mmi2_names[] = MMI2_NAMES;
+static const char *mmi3_names[] = MMI3_NAMES;
+static const char *special3_names[] = SPECIAL3_NAMES;
+
+static const char *regnames[] = MIPS_REGISTER_NAMES;
+static const char *cop0_names[] = COP0_NAMES;
+
+
+#define DYNTRANS_DUALMODE_32
+#define DYNTRANS_DELAYSLOT
+#include "tmp_mips_head.c"
+
+void mips_pc_to_pointers(struct cpu *);
+void mips32_pc_to_pointers(struct cpu *);
+
+
+/*
+ *  mips_cpu_new():
+ *
+ *  Create a new MIPS cpu object.
+ *
+ *  Returns 1 on success, 0 if there was no valid MIPS processor with
+ *  a matching name.
+ */
+int mips_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
+	int cpu_id, char *cpu_type_name)
+{
+	int i, found, j, tags_size, n_cache_lines, size_per_cache_line;
+	struct mips_cpu_type_def cpu_type_defs[] = MIPS_CPU_TYPE_DEFS;
+	int x, linesize;
+
+	/*  Scan the cpu_type_defs list for this cpu type:  */
+	i = 0;
+	found = -1;
+	while (i >= 0 && cpu_type_defs[i].name != NULL) {
+		if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
+			found = i;
+			break;
+		}
+		i++;
+	}
+
+	if (found == -1)
+		return 0;
+
+	cpu->memory_rw                = mips_memory_rw;
+	cpu->cd.mips.cpu_type         = cpu_type_defs[found];
+	cpu->name                     = strdup(cpu->cd.mips.cpu_type.name);
+	cpu->byte_order               = EMUL_LITTLE_ENDIAN;
+	cpu->cd.mips.gpr[MIPS_GPR_SP] = INITIAL_STACK_POINTER;
+
+	if (cpu->cd.mips.cpu_type.isa_level <= 2 ||
+	    cpu->cd.mips.cpu_type.isa_level == 32)
+		cpu->is_32bit = 1;
+
+	if (cpu->is_32bit) {
+		cpu->run_instr = mips32_run_instr;
+		cpu->update_translation_table = mips32_update_translation_table;
+		cpu->invalidate_translation_caches =
+		    mips32_invalidate_translation_caches;
+		cpu->invalidate_code_translation =
+		    mips32_invalidate_code_translation;
+	} else {
+		cpu->run_instr = mips_run_instr;
+		cpu->update_translation_table = mips_update_translation_table;
+		cpu->invalidate_translation_caches =
+		    mips_invalidate_translation_caches;
+		cpu->invalidate_code_translation =
+		    mips_invalidate_code_translation;
+	}
+
+	cpu->instruction_has_delayslot = mips_cpu_instruction_has_delayslot;
+
+	/*
+	 *  CACHES:
+	 *
+	 *  1) Use DEFAULT_PCACHE_SIZE and DEFAULT_PCACHE_LINESIZE etc.
+	 *  2) If there are specific values defined for this type of cpu,
+	 *     in its cpu_type substruct, then let's use those.
+	 *  3) Values in the emul struct override both of the above.
+	 *
+	 *  Once we've decided which values to use, they are stored in
+	 *  the emul struct so they can be used from src/machine.c etc.
+	 */
+
+	x = DEFAULT_PCACHE_SIZE;
+	if (cpu->cd.mips.cpu_type.pdcache)
+		x = cpu->cd.mips.cpu_type.pdcache;
+	if (cpu->cd.mips.cache_pdcache == 0)
+		cpu->cd.mips.cache_pdcache = x;
+
+	x = DEFAULT_PCACHE_SIZE;
+	if (cpu->cd.mips.cpu_type.picache)
+		x = cpu->cd.mips.cpu_type.picache;
+	if (cpu->cd.mips.cache_picache == 0)
+		cpu->cd.mips.cache_picache = x;
+
+	if (cpu->cd.mips.cache_secondary == 0)
+		cpu->cd.mips.cache_secondary = cpu->cd.mips.cpu_type.scache;
+
+	linesize = DEFAULT_PCACHE_LINESIZE;
+	if (cpu->cd.mips.cpu_type.pdlinesize)
+		linesize = cpu->cd.mips.cpu_type.pdlinesize;
+	if (cpu->cd.mips.cache_pdcache_linesize == 0)
+		cpu->cd.mips.cache_pdcache_linesize = linesize;
+
+	linesize = DEFAULT_PCACHE_LINESIZE;
+	if (cpu->cd.mips.cpu_type.pilinesize)
+		linesize = cpu->cd.mips.cpu_type.pilinesize;
+	if (cpu->cd.mips.cache_picache_linesize == 0)
+		cpu->cd.mips.cache_picache_linesize = linesize;
+
+	linesize = 0;
+	if (cpu->cd.mips.cpu_type.slinesize)
+		linesize = cpu->cd.mips.cpu_type.slinesize;
+	if (cpu->cd.mips.cache_secondary_linesize == 0)
+		cpu->cd.mips.cache_secondary_linesize = linesize;
+
+
+	/*
+	 *  Primary Data and Instruction caches:
+	 */
+	for (i=CACHE_DATA; i<=CACHE_INSTRUCTION; i++) {
+		switch (i) {
+		case CACHE_DATA:
+			x = 1 << cpu->cd.mips.cache_pdcache;
+			linesize = 1 << cpu->cd.mips.cache_pdcache_linesize;
+			break;
+		case CACHE_INSTRUCTION:
+			x = 1 << cpu->cd.mips.cache_picache;
+			linesize = 1 << cpu->cd.mips.cache_picache_linesize;
+			break;
+		}
+
+		/*  Primary cache size and linesize:  */
+		cpu->cd.mips.cache_size[i] = x;
+		cpu->cd.mips.cache_linesize[i] = linesize;
+
+		switch (cpu->cd.mips.cpu_type.rev) {
+		case MIPS_R2000:
+		case MIPS_R3000:
+			size_per_cache_line = sizeof(struct r3000_cache_line);
+			break;
+		default:
+			size_per_cache_line = 32;	/*  TODO  */
+		}
+
+		cpu->cd.mips.cache_mask[i] = cpu->cd.mips.cache_size[i] - 1;
+
+		CHECK_ALLOCATION(cpu->cd.mips.cache[i] = (unsigned char *)
+		    malloc(cpu->cd.mips.cache_size[i]));
+
+		n_cache_lines = cpu->cd.mips.cache_size[i] /
+		    cpu->cd.mips.cache_linesize[i];
+		tags_size = n_cache_lines * size_per_cache_line;
+
+		CHECK_ALLOCATION(cpu->cd.mips.cache_tags[i] =
+		    malloc(tags_size));
+
+		/*  Initialize the cache tags:  */
+		switch (cpu->cd.mips.cpu_type.rev) {
+		case MIPS_R2000:
+		case MIPS_R3000:
+			for (j=0; j<n_cache_lines; j++) {
+				struct r3000_cache_line *rp;
+				rp = (struct r3000_cache_line *)
+				    cpu->cd.mips.cache_tags[i];
+				rp[j].tag_paddr = 0;
+				rp[j].tag_valid = 0;
+			}
+			break;
+		default:
+			;
+		}
+
+		/*  Set cache_last_paddr to something "impossible":  */
+		cpu->cd.mips.cache_last_paddr[i] = IMPOSSIBLE_PADDR;
+	}
+
+	/*  Register the CPU's interrupts:  */
+	for (i=2; i<8; i++) {
+		struct interrupt templ;
+		char name[50];
+		snprintf(name, sizeof(name), "%s.%i", cpu->path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 1 << (STATUS_IM_SHIFT + i);
+		templ.name = name;
+		templ.extra = cpu;
+		templ.interrupt_assert = mips_cpu_interrupt_assert;
+		templ.interrupt_deassert = mips_cpu_interrupt_deassert;
+		interrupt_handler_register(&templ);
+
+		if (i == 7)
+			INTERRUPT_CONNECT(name, cpu->cd.mips.irq_compare);
+	}
+
+	/*  System coprocessor (0), and FPU (1):  */
+	cpu->cd.mips.coproc[0] = mips_coproc_new(cpu, 0);
+	cpu->cd.mips.coproc[1] = mips_coproc_new(cpu, 1);
+
+	switch (cpu->cd.mips.cpu_type.mmu_model) {
+	case MMU3K:
+		cpu->vaddr_mask = 0x00000000ffffffffULL;
+		cpu->translate_v2p = translate_v2p_mmu3k;
+		break;
+	case MMU8K:
+		cpu->translate_v2p = translate_v2p_mmu8k;
+		break;
+	case MMU10K:
+		cpu->vaddr_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K | 0x1fff;
+		cpu->translate_v2p = translate_v2p_mmu10k;
+		break;
+	default:
+		if (cpu->is_32bit)
+			cpu->vaddr_mask = 0x00000000ffffffffULL;
+		else
+			cpu->vaddr_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK | 0x1fff;
+
+		if (cpu->cd.mips.cpu_type.rev == MIPS_R4100)
+			cpu->translate_v2p = translate_v2p_mmu4100;
+		else
+			cpu->translate_v2p = translate_v2p_generic;
+	}
+
+	// TODO: Consider moving to src/machine/machine_test.c?
+	// This is only here to make the floating point tests work out-of-the-box.
+	if (!cpu->is_32bit)
+		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |= STATUS_FR;
+
+	if (cpu->machine->prom_emulation) {
+		/*
+		 *  Default behaviour of jumping to 0xbfc00000 should be
+		 *  a reboot, unless machine-specific initialization code
+		 *  overrides this.
+		 *
+		 *  Note: Specifically big-endian machines should override
+		 *  this, since the default MIPS CPU is little-endian!
+		 */
+		store_32bit_word(cpu, 0xffffffff9fc00000ULL, 0x00c0de0d);
+	}
+
+	/*  Add all register names to the settings:  */
+	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
+	CPU_SETTINGS_ADD_REGISTER64("hi", cpu->cd.mips.hi);
+	CPU_SETTINGS_ADD_REGISTER64("lo", cpu->cd.mips.lo);
+	for (i=0; i<N_MIPS_GPRS; i++)
+		CPU_SETTINGS_ADD_REGISTER64(regnames[i], cpu->cd.mips.gpr[i]);
+	/*  TODO: Write via special handler function!  */
+	for (i=0; i<N_MIPS_COPROC_REGS; i++)
+		CPU_SETTINGS_ADD_REGISTER64(cop0_names[i],
+		    cpu->cd.mips.coproc[0]->reg[i]);
+
+	return 1;
+}
+
+
+/*
+ *  mips_cpu_dumpinfo():
+ *
+ *  Debug dump of MIPS-specific CPU data for specific CPU.
+ */
+void mips_cpu_dumpinfo(struct cpu *cpu, bool verbose)
+{
+	struct mips_cpu_type_def *ct = &cpu->cd.mips.cpu_type;
+	int secondary_cache_size = 0;
+	if (cpu->cd.mips.cache_secondary)
+		secondary_cache_size = 1 << cpu->cd.mips.cache_secondary;
+
+	if (!verbose) {
+		debugmsg(SUBSYS_MACHINE, "cpu", VERBOSITY_INFO,
+		    "%s (%i-bit, I+D = %i+%i KB, L2 = %i KB)",
+		    cpu->name,
+		    cpu->is_32bit? 32 : 64,
+		    (int)(cpu->cd.mips.cache_size[CACHE_INSTRUCTION] / 1024),
+		    (int)(cpu->cd.mips.cache_size[CACHE_DATA] / 1024),
+		    (int)(secondary_cache_size / 1024));
+
+		return;
+	}
+
+	debug("%s-endian (MIPS",
+	    cpu->byte_order == EMUL_BIG_ENDIAN? "Big" : "Little");
+
+	switch (ct->isa_level) {
+	case 1:	debug(" ISA I"); break;
+	case 2:	debug(" ISA II"); break;
+	case 3:	debug(" ISA III"); break;
+	case 4:	debug(" ISA IV"); break;
+	case 5:	debug(" ISA V"); break;
+	case 32:
+	case 64:debug("%i, revision %i", ct->isa_level, ct->isa_revision);
+		break;
+	default:debug(" ISA level %i", ct->isa_level);
+	}
+
+	debug("), ");
+	if (ct->nr_of_tlb_entries)
+		debug("%i TLB entries", ct->nr_of_tlb_entries);
+	else
+		debug("no TLB");
+	debug("\n");
+
+	if (ct->picache) {
+		debug("L1 I-cache: %i KB", (1 << ct->picache) / 1024);
+		if (ct->pilinesize)
+			debug(", %i bytes per line", 1 << ct->pilinesize);
+		if (ct->piways > 1)
+			debug(", %i-way", ct->piways);
+		else
+			debug(", direct-mapped");
+		debug("\n");
+	}
+
+	if (ct->pdcache) {
+		debug("L1 D-cache: %i KB", (1 << ct->pdcache) / 1024);
+		if (ct->pdlinesize)
+			debug(", %i bytes per line", 1 << ct->pdlinesize);
+		if (ct->pdways > 1)
+			debug(", %i-way", ct->pdways);
+		else
+			debug(", direct-mapped");
+		debug("\n");
+	}
+
+	if (ct->scache) {
+		int kb = (1 << ct->scache) / 1024;
+		debug("L2 cache: %i %s",
+		    kb >= 1024? kb / 1024 : kb, kb >= 1024? "MB":"KB");
+		if (ct->slinesize)
+			debug(", %i bytes per line", 1 << ct->slinesize);
+		if (ct->sways > 1)
+			debug(", %i-way", ct->sways);
+		else
+			debug(", direct-mapped");
+		debug("\n");
+	}
+}
+
+
+/*
+ *  mips_cpu_list_available_types():
+ *
+ *  Print a list of available MIPS CPU types.
+ */
+void mips_cpu_list_available_types(void)
+{
+	int i, j;
+	struct mips_cpu_type_def cpu_type_defs[] = MIPS_CPU_TYPE_DEFS;
+
+	i = 0;
+	while (cpu_type_defs[i].name != NULL) {
+		debug("%s", cpu_type_defs[i].name);
+		for (j=10 - strlen(cpu_type_defs[i].name); j>0; j--)
+			debug(" ");
+		i++;
+		if ((i % 6) == 0 || cpu_type_defs[i].name == NULL)
+			debug("\n");
+	}
+}
+
+
+/*
+ *  mips_cpu_instruction_has_delayslot():
+ *
+ *  Return 1 if an opcode is a branch, 0 otherwise.
+ */
+int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
+{
+	uint32_t iword = *((uint32_t *)&ib[0]);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iword = LE32_TO_HOST(iword);
+	else
+		iword = BE32_TO_HOST(iword);
+
+	switch (iword >> 26) {
+	case HI6_SPECIAL:
+		switch (iword & 0x3f) {
+		case SPECIAL_JR:
+		case SPECIAL_JALR:
+			return 1;
+		}
+		break;
+	case HI6_REGIMM:
+		switch ((iword >> 16) & 0x1f) {
+		case REGIMM_BLTZ:
+		case REGIMM_BGEZ:
+		case REGIMM_BLTZL:
+		case REGIMM_BGEZL:
+		case REGIMM_BLTZAL:
+		case REGIMM_BLTZALL:
+		case REGIMM_BGEZAL:
+		case REGIMM_BGEZALL:
+			return 1;
+		}
+		break;
+	case HI6_BEQ:
+	case HI6_BEQL:
+	case HI6_BNE:
+	case HI6_BNEL:
+	case HI6_BGTZ:
+	case HI6_BGTZL:
+	case HI6_BLEZ:
+	case HI6_BLEZL:
+	case HI6_J:
+	case HI6_JAL:
+		return 1;
+	}
+
+	return 0;
+}
+
+
+/*
+ *  mips_cpu_tlbdump():
+ *
+ *  Called from the debugger to dump the TLB in a readable format.
+ *
+ *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
+ *  just dumped.
+ */
+void mips_cpu_tlbdump(struct cpu *cpu, int rawflag)
+{
+	int i, j;
+	struct machine* m = cpu->machine;
+
+	/*  Raw output:  */
+	if (rawflag) {
+		for (i=0; i<m->ncpus; i++) {
+			if (cpu != m->cpus[i])
+				continue;
+
+			struct mips_coproc *cop0 =
+			    m->cpus[i]->cd.mips.coproc[0];
+
+			/*  Print index, random, and wired:  */
+			printf("cpu%i: (", i);
+
+			if (m->cpus[i]->is_32bit)
+				printf("index=0x%08x random=0x%08x",
+				    (int) cop0->reg[COP0_INDEX],
+				    (int) cop0->reg[COP0_RANDOM]);
+			else
+				printf("index=0x%016" PRIx64
+				    " random=0x%016" PRIx64,
+				    (uint64_t) cop0->reg[COP0_INDEX],
+				    (uint64_t) cop0->reg[COP0_RANDOM]);
+
+			if (m->cpus[i]->cd.mips.cpu_type.isa_level >= 3)
+				printf(" wired=0x%" PRIx64,
+				    (uint64_t) cop0->reg[COP0_WIRED]);
+
+			printf(")\n");
+
+			for (j=0; j<m->cpus[i]->cd.mips.cpu_type.
+			    nr_of_tlb_entries; j++) {
+				if (m->cpus[i]->cd.mips.cpu_type.mmu_model ==
+				    MMU3K)
+					printf(" %02x: hi=0x%08" PRIx32" lo=0x%08"
+					    PRIx32"\n", j,
+					    (uint32_t) cop0->tlbs[j].hi,
+					    (uint32_t) cop0->tlbs[j].lo0);
+				else if (m->cpus[i]->is_32bit)
+					printf(" %02x: hi=0x%08" PRIx32" mask=0x"
+					    "%08" PRIx32" lo0=0x%08" PRIx32
+					    " lo1=0x%08" PRIx32"\n", j,
+					    (uint32_t) cop0->tlbs[j].hi,
+					    (uint32_t) cop0->tlbs[j].mask,
+					    (uint32_t) cop0->tlbs[j].lo0,
+					    (uint32_t) cop0->tlbs[j].lo1);
+				else
+					printf(" %02x: hi=0x%016" PRIx64" mask="
+					    "0x%016" PRIx64" lo0=0x%016" PRIx64
+					    " lo1=0x%016" PRIx64"\n", j,
+					    (uint64_t) cop0->tlbs[j].hi,
+					    (uint64_t) cop0->tlbs[j].mask,
+					    (uint64_t) cop0->tlbs[j].lo0,
+					    (uint64_t) cop0->tlbs[j].lo1);
+			}
+		}
+
+		return;
+	}
+
+	/*  Nicely formatted output:  */
+	for (i=0; i<m->ncpus; i++) {
+		if (cpu != m->cpus[i])
+			continue;
+
+		int pageshift = 12;
+		struct mips_coproc *cop0 = m->cpus[i]->cd.mips.coproc[0];
+
+
+		if (m->cpus[i]->cd.mips.cpu_type.rev == MIPS_R4100)
+			pageshift = 10;
+
+		/*  Print index, random, and wired:  */
+		printf("cpu%i: (", i);
+		switch (m->cpus[i]->cd.mips.cpu_type.isa_level) {
+		case 1:
+		case 2:	printf("index=0x%x random=0x%x",
+			    (int) ((cop0->reg[COP0_INDEX] & R2K3K_INDEX_MASK)
+			    >> R2K3K_INDEX_SHIFT),
+			    (int) ((cop0->reg[COP0_RANDOM] & R2K3K_RANDOM_MASK)
+			    >> R2K3K_RANDOM_SHIFT));
+			break;
+		default:printf("index=0x%x random=0x%x",
+			    (int) (cop0->reg[COP0_INDEX] & INDEX_MASK),
+			    (int) (cop0->reg[COP0_RANDOM] & RANDOM_MASK));
+			printf(" wired=0x%" PRIx64,
+			    (uint64_t) cop0->reg[COP0_WIRED]);
+		}
+
+		printf(")\n");
+
+		for (j=0; j<m->cpus[i]->cd.mips.cpu_type.
+		    nr_of_tlb_entries; j++) {
+			uint64_t hi = cop0->tlbs[j].hi;
+			uint64_t lo0 = cop0->tlbs[j].lo0;
+			uint64_t lo1 = cop0->tlbs[j].lo1;
+			uint64_t mask = cop0->tlbs[j].mask;
+			uint64_t psize;
+
+			mask |= (1 << (pageshift+1)) - 1;
+			/*  here mask = e.g. 0x1fff for 4KB pages  */
+
+			printf(" %02x: ", j);
+
+			switch (m->cpus[i]->cd.mips.cpu_type.mmu_model) {
+			case MMU3K:
+				if (!(lo0 & R2K3K_ENTRYLO_V)) {
+					printf("(invalid)\n");
+					continue;
+				}
+				printf("vaddr=0x%08x ",
+				    (int) (hi&R2K3K_ENTRYHI_VPN_MASK));
+				if (lo0 & R2K3K_ENTRYLO_G)
+					printf("(global), ");
+				else
+					printf("(asid %02x),", (int) ((hi &
+					    R2K3K_ENTRYHI_ASID_MASK)
+					    >> R2K3K_ENTRYHI_ASID_SHIFT));
+				printf(" paddr=0x%08x ",
+				    (int) (lo0&R2K3K_ENTRYLO_PFN_MASK));
+				if (lo0 & R2K3K_ENTRYLO_N)
+					printf("N");
+				if (lo0 & R2K3K_ENTRYLO_D)
+					printf("D");
+				printf("\n");
+				break;
+			default:switch (m->cpus[i]->cd.mips.cpu_type.mmu_model){
+				case MMU32:
+					printf("vaddr=0x%08" PRIx32" ",
+					    (uint32_t) (hi & ~mask));
+					break;
+				default:/*  R4x00, R1x000, MIPS64, etc.  */
+					printf("vaddr=%016" PRIx64" ",
+					    (uint64_t) (hi & ~mask));
+				}
+				if (hi & TLB_G)
+					printf("(global): ");
+				else
+					printf("(asid %02x):",
+					    (int) (hi & ENTRYHI_ASID));
+
+				/*  TODO: Coherency bits  */
+
+				if (!(lo0 & ENTRYLO_V))
+					printf(" p0=(invalid)   ");
+				else {
+					uint64_t paddr = lo0 & ENTRYLO_PFN_MASK;
+					paddr >>= ENTRYLO_PFN_SHIFT;
+					paddr <<= pageshift;
+					paddr &= ~(mask >> 1);
+					printf(" p0=0x%09" PRIx64" ",
+					    (uint64_t) paddr);
+				}
+				printf(lo0 & ENTRYLO_D? "D" : " ");
+
+				if (!(lo1 & ENTRYLO_V))
+					printf(" p1=(invalid)   ");
+				else {
+					uint64_t paddr = lo1 & ENTRYLO_PFN_MASK;
+					paddr >>= ENTRYLO_PFN_SHIFT;
+					paddr <<= pageshift;
+					paddr &= ~(mask >> 1);
+					printf(" p1=0x%09" PRIx64" ",
+					    (uint64_t) paddr);
+				}
+				printf(lo1 & ENTRYLO_D? "D" : " ");
+
+				/*  convert e.g. 0x1fff to 4096  */
+				psize = (mask + 1) >> 1;
+
+				if (psize >= 1024 && psize <= 256*1024)
+					printf(" (%iKB)", (int) (psize >> 10));
+				else if (psize >= 1024*1024 && psize <=
+				    64*1024*1024)
+					printf(" (%iMB)", (int) (psize >> 20));
+				else
+					printf(" (?)");
+
+				printf("\n");
+			}
+		}
+	}
+}
+
+
+/*
+ *  mips_cpu_disassemble_instr():
+ *
+ *  Convert an instruction word into human readable format, for instruction
+ *  tracing.
+ *
+ *  If running is 1, cpu->pc should be the address of the instruction.
+ *
+ *  If running is 0, things that depend on the runtime environment (eg.
+ *  register contents) will not be shown, and addr will be used instead of
+ *  cpu->pc for relative addresses.
+ *
+ *  NOTE 2:  coprocessor instructions are not decoded nicely yet  (TODO)
+ */
+int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *originstr,
+	int running, uint64_t dumpaddr)
+{
+	int hi6, special6, regimm5, sub;
+	int rt, rd, rs, sa, imm, copz, cache_op, which_cache, showtag;
+	uint64_t addr, offset;
+	uint32_t instrword;
+	unsigned char instr[4];
+	char *symbol;
+
+	if (running)
+		dumpaddr = cpu->pc;
+
+	if ((dumpaddr & 3) != 0)
+		printf("WARNING: Unaligned address!\n");
+
+	symbol = get_symbol_name(&cpu->machine->symbol_context,
+	    dumpaddr, &offset);
+	if (symbol != NULL && offset==0)
+		debug("<%s>\n", symbol);
+
+	if (cpu->machine->ncpus > 1 && running)
+		debug("cpu%i: ", cpu->cpu_id);
+
+	if (cpu->is_32bit)
+		debug("%08" PRIx32, (uint32_t)dumpaddr);
+	else
+		debug("%016" PRIx64, (uint64_t)dumpaddr);
+
+	memcpy(instr, originstr, sizeof(uint32_t));
+
+	/*
+	 *  The rest of the code is written for little endian,
+	 *  so swap if necessary:
+	 */
+	if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+		int tmp = instr[0]; instr[0] = instr[3];
+		    instr[3] = tmp;
+		tmp = instr[1]; instr[1] = instr[2];
+		    instr[2] = tmp;
+	}
+
+	debug(": %02x%02x%02x%02x",
+	    instr[3], instr[2], instr[1], instr[0]);
+
+	if (running && cpu->delay_slot)
+		debug(" (d)");
+	else
+		debug("    ");
+
+	cpu_print_pc_indicator_in_disassembly(cpu, running, dumpaddr);
+
+	/*
+	 *  Decode the instruction:
+	 */
+
+	hi6 = (instr[3] >> 2) & 0x3f;
+
+	switch (hi6) {
+	case HI6_SPECIAL:
+		special6 = instr[0] & 0x3f;
+		switch (special6) {
+		case SPECIAL_SLL:
+		case SPECIAL_SRL:
+		case SPECIAL_SRA:
+		case SPECIAL_DSLL:
+		case SPECIAL_DSRL:
+		case SPECIAL_DSRA:
+		case SPECIAL_DSLL32:
+		case SPECIAL_DSRL32:
+		case SPECIAL_DSRA32:
+			sub = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+			rt = instr[2] & 31;
+			rd = (instr[1] >> 3) & 31;
+			sa = ((instr[1] & 7) << 2) + ((instr[0] >> 6) & 3);
+
+			if (rd == 0 && special6 == SPECIAL_SLL) {
+				if (sa == 0)
+					debug("nop");
+				else if (sa == 1)
+					debug("ssnop");
+				else if (sa == 3)
+					debug("ehb");
+				else
+					debug("nop (weird, sa=%i)", sa);
+				break;
+			}
+
+			switch (sub) {
+			case 0x00:
+				debug("%s\t%s,", special_names[special6],
+				    regnames[rd]);
+				debug("%s,%i", regnames[rt], sa);
+				break;
+			case 0x01:
+				debug("%s\t%s,",
+				    special_rot_names[special6],
+				    regnames[rd]);
+				debug("%s,%i", regnames[rt], sa);
+				break;
+			default:debug("UNIMPLEMENTED special, sub=0x%02x\n",
+				    sub);
+			}
+			break;
+		case SPECIAL_DSRLV:
+		case SPECIAL_DSRAV:
+		case SPECIAL_DSLLV:
+		case SPECIAL_SLLV:
+		case SPECIAL_SRAV:
+		case SPECIAL_SRLV:
+			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+			rt = instr[2] & 31;
+			rd = (instr[1] >> 3) & 31;
+			sub = ((instr[1] & 7) << 2) + ((instr[0] >> 6) & 3);
+
+			switch (sub) {
+			case 0x00:
+				debug("%s\t%s", special_names[special6],
+				    regnames[rd]);
+				debug(",%s", regnames[rt]);
+				debug(",%s", regnames[rs]);
+				break;
+			case 0x01:
+				debug("%s\t%s", special_rot_names[special6],
+				    regnames[rd]);
+				debug(",%s", regnames[rt]);
+				debug(",%s", regnames[rs]);
+				break;
+			default:debug("UNIMPLEMENTED special, sub=0x%02x\n",
+				    sub);
+			}
+			break;
+		case SPECIAL_JR:
+			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    cpu->cd.mips.gpr[rs], &offset);
+			/*  .hb = hazard barrier hint on MIPS32/64 rev 2  */
+			debug("jr%s\t%s",
+			    (instr[1] & 0x04) ? ".hb" : "",
+			    regnames[rs]);
+			if (running && symbol != NULL)
+				debug("\t<%s>", symbol);
+			break;
+		case SPECIAL_JALR:
+			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+			rd = (instr[1] >> 3) & 31;
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    cpu->cd.mips.gpr[rs], &offset);
+			/*  .hb = hazard barrier hint on MIPS32/64 rev 2  */
+			debug("jalr%s\t%s",
+			    (instr[1] & 0x04) ? ".hb" : "",
+			    regnames[rd]);
+			debug(",%s", regnames[rs]);
+			if (running && symbol != NULL)
+				debug("\t<%s>", symbol);
+			break;
+		case SPECIAL_MFHI:
+		case SPECIAL_MFLO:
+			rd = (instr[1] >> 3) & 31;
+			debug("%s\t%s", special_names[special6], regnames[rd]);
+			break;
+		case SPECIAL_MTLO:
+		case SPECIAL_MTHI:
+			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+			debug("%s\t%s", special_names[special6], regnames[rs]);
+			break;
+		case SPECIAL_ADD:
+		case SPECIAL_ADDU:
+		case SPECIAL_SUB:
+		case SPECIAL_SUBU:
+		case SPECIAL_AND:
+		case SPECIAL_OR:
+		case SPECIAL_XOR:
+		case SPECIAL_NOR:
+		case SPECIAL_SLT:
+		case SPECIAL_SLTU: 
+		case SPECIAL_DADD:
+		case SPECIAL_DADDU:
+		case SPECIAL_DSUB:
+		case SPECIAL_DSUBU:
+		case SPECIAL_MOVZ:
+		case SPECIAL_MOVN:
+			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+			rt = instr[2] & 31;
+			rd = (instr[1] >> 3) & 31;
+			if (cpu->is_32bit && (special6 == SPECIAL_ADDU ||
+			    special6 == SPECIAL_SUBU) && rt == 0) {
+				/*  Special case 1: addu/subu with
+				    rt = the zero register ==> move  */
+				debug("move\t%s", regnames[rd]);
+				debug(",%s", regnames[rs]);
+			} else if (special6 == SPECIAL_ADDU && cpu->is_32bit
+			    && rs == 0) {
+				/*  Special case 2: addu with
+				    rs = the zero register ==> move  */
+				debug("move\t%s", regnames[rd]);
+				debug(",%s", regnames[rt]);
+			} else {
+				debug("%s\t%s", special_names[special6],
+				    regnames[rd]);
+				debug(",%s", regnames[rs]);
+				debug(",%s", regnames[rt]);
+			}
+			break;
+		case SPECIAL_MULT:
+		case SPECIAL_MULTU:
+		case SPECIAL_DMULT:
+		case SPECIAL_DMULTU:
+		case SPECIAL_DIV:
+		case SPECIAL_DIVU:
+		case SPECIAL_DDIV:
+		case SPECIAL_DDIVU:
+			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+			rt = instr[2] & 31;
+			rd = (instr[1] >> 3) & 31;
+			debug("%s\t", special_names[special6]);
+			if (rd != 0) {
+				if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
+					if (special6 == SPECIAL_MULT ||
+					    special6 == SPECIAL_MULTU)
+						debug("%s,", regnames[rd]);
+					else
+						debug("WEIRD_R5900_RD,");
+				} else {
+					debug("WEIRD_RD_NONZERO,");
+				}
+			}
+			debug("%s", regnames[rs]);
+			debug(",%s", regnames[rt]);
+			break;
+		case SPECIAL_TGE:
+		case SPECIAL_TGEU:
+		case SPECIAL_TLT:
+		case SPECIAL_TLTU:
+		case SPECIAL_TEQ:
+		case SPECIAL_TNE:
+			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+			rt = instr[2] & 31;
+			rd = ((instr[1] << 8) + instr[0]) >> 6;	// code, not rd
+			debug("%s\t", special_names[special6]);
+			debug("%s", regnames[rs]);
+			debug(",%s", regnames[rt]);
+			if (rd != 0)
+				debug(",0x%x", rd);
+			break;
+		case SPECIAL_SYNC:
+			imm = ((instr[1] & 7) << 2) + (instr[0] >> 6);
+			debug("sync\t0x%02x", imm);
+			break;
+		case SPECIAL_SYSCALL:
+			imm = (((instr[3] << 24) + (instr[2] << 16) +
+			    (instr[1] << 8) + instr[0]) >> 6) & 0xfffff;
+			if (imm != 0)
+				debug("syscall\t0x%05x", imm);
+			else
+				debug("syscall");
+			break;
+		case SPECIAL_BREAK:
+			imm = (((instr[3] << 24) + (instr[2] << 16) +
+			    (instr[1] << 8) + instr[0]) >> 6) & 0xfffff;
+			if (imm != 0)
+				debug("break\t0x%05x", imm);
+			else
+				debug("break");
+			break;
+		case SPECIAL_MFSA:
+			if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
+				rd = (instr[1] >> 3) & 31;
+				debug("mfsa\t%s", regnames[rd]);
+			} else {
+				debug("unimplemented special 0x28");
+			}
+			break;
+		case SPECIAL_MTSA:
+			if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
+				rs = ((instr[3] & 3) << 3) +
+				    ((instr[2] >> 5) & 7);
+				debug("mtsa\t%s", regnames[rs]);
+			} else {
+				debug("unimplemented special 0x29");
+			}
+			break;
+		default:
+			debug("%s\t= UNIMPLEMENTED", special_names[special6]);
+		}
+		break;
+	case HI6_BEQ:
+	case HI6_BEQL:
+	case HI6_BNE:
+	case HI6_BNEL:
+	case HI6_BGTZ:
+	case HI6_BGTZL:
+	case HI6_BLEZ:
+	case HI6_BLEZL:
+		rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+		rt = instr[2] & 31;
+		imm = (instr[1] << 8) + instr[0];
+		if (imm >= 32768)
+			imm -= 65536;
+		addr = (dumpaddr + 4) + (imm << 2);
+
+		if (hi6 == HI6_BEQ && rt == MIPS_GPR_ZERO &&
+		    rs == MIPS_GPR_ZERO)
+			debug("b\t");
+		else {
+			debug("%s\t", hi6_names[hi6]);
+			switch (hi6) {
+			case HI6_BEQ:
+			case HI6_BEQL:
+			case HI6_BNE:
+			case HI6_BNEL:
+				debug("%s,", regnames[rt]);
+			}
+			debug("%s,", regnames[rs]);
+		}
+
+		if (cpu->is_32bit)
+			debug("0x%08" PRIx32, (uint32_t)addr);
+		else
+			debug("0x%016" PRIx64, (uint64_t)addr);
+
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    addr, &offset);
+		if (symbol != NULL && offset != addr)
+			debug("\t<%s>", symbol);
+		break;
+	case HI6_ADDI:
+	case HI6_ADDIU:
+	case HI6_DADDI:
+	case HI6_DADDIU:
+	case HI6_SLTI:
+	case HI6_SLTIU:
+	case HI6_ANDI:
+	case HI6_ORI:
+	case HI6_XORI:
+		rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+		rt = instr[2] & 31;
+		imm = (instr[1] << 8) + instr[0];
+		if (imm >= 32768)
+			imm -= 65536;
+		debug("%s\t%s,", hi6_names[hi6], regnames[rt]);
+		debug("%s,", regnames[rs]);
+		if (hi6 == HI6_ANDI || hi6 == HI6_ORI || hi6 == HI6_XORI)
+			debug("0x%04x", imm & 0xffff);
+		else
+			debug("%i", imm);
+		break;
+	case HI6_LUI:
+		rt = instr[2] & 31;
+		imm = (instr[1] << 8) + instr[0];
+		debug("lui\t%s,0x%x", regnames[rt], imm);
+		break;
+	case HI6_LB:
+	case HI6_LBU:
+	case HI6_LH:
+	case HI6_LHU:
+	case HI6_LW:
+	case HI6_LWU:
+	case HI6_LD:
+	case HI6_LQ_MDMX:
+	case HI6_LWC1:
+	case HI6_LWC2:
+	case HI6_LWC3:
+	case HI6_LDC1:
+	case HI6_LDC2:
+	case HI6_LL:
+	case HI6_LLD:
+	case HI6_SB:
+	case HI6_SH:
+	case HI6_SW:
+	case HI6_SD:
+	case HI6_SQ_SPECIAL3:
+	case HI6_SC:
+	case HI6_SCD:
+	case HI6_SWC1:
+	case HI6_SWC2:
+	case HI6_SWC3:
+	case HI6_SDC1:
+	case HI6_SDC2:
+	case HI6_LWL:   
+	case HI6_LWR:
+	case HI6_LDL:
+	case HI6_LDR:
+	case HI6_SWL:
+	case HI6_SWR:
+	case HI6_SDL:
+	case HI6_SDR:
+		if (hi6 == HI6_LQ_MDMX &&
+		    cpu->cd.mips.cpu_type.rev != MIPS_R5900) {
+			debug("mdmx\t(UNIMPLEMENTED)");
+			break;
+		}
+		if (hi6 == HI6_SQ_SPECIAL3 &&
+		    cpu->cd.mips.cpu_type.rev != MIPS_R5900) {
+			int msbd, lsb, sub10;
+			special6 = instr[0] & 0x3f;
+			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+			rt = instr[2] & 31;
+			rd = msbd = (instr[1] >> 3) & 31;
+			lsb = ((instr[1] & 7) << 2) | (instr[0] >> 6);
+			sub10 = (rs << 5) | lsb;
+
+			switch (special6) {
+
+			case SPECIAL3_EXT:
+			case SPECIAL3_DEXT:
+			case SPECIAL3_DEXTM:
+			case SPECIAL3_DEXTU:
+				debug("%s", special3_names[special6]);
+				if (special6 == SPECIAL3_DEXTM)
+					msbd += 32;
+				if (special6 == SPECIAL3_DEXTU)
+					lsb += 32;
+				debug("\t%s", regnames[rt]);
+				debug(",%s", regnames[rs]);
+				debug(",%i,%i", lsb, msbd + 1);
+				break;
+
+			case SPECIAL3_INS:
+			case SPECIAL3_DINS:
+			case SPECIAL3_DINSM:
+			case SPECIAL3_DINSU:
+				debug("%s", special3_names[special6]);
+				if (special6 == SPECIAL3_DINSM)
+					msbd += 32;
+				if (special6 == SPECIAL3_DINSU) {
+					lsb += 32;
+					msbd += 32;
+				}
+				msbd -= lsb;
+				debug("\t%s", regnames[rt]);
+				debug(",%s", regnames[rs]);
+				debug(",%i,%i", lsb, msbd + 1);
+				break;
+
+			case SPECIAL3_BSHFL:
+				switch (sub10) {
+				case BSHFL_WSBH:
+				case BSHFL_SEB:
+				case BSHFL_SEH:
+					switch (sub10) {
+					case BSHFL_WSBH: debug("wsbh"); break;
+					case BSHFL_SEB:  debug("seb"); break;
+					case BSHFL_SEH:  debug("seh"); break;
+					}
+					debug("\t%s", regnames[rd]);
+					debug(",%s", regnames[rt]);
+					break;
+				default:debug("%s", special3_names[special6]);
+					debug("\t(UNIMPLEMENTED)");
+				}
+				break;
+
+			case SPECIAL3_DBSHFL:
+				switch (sub10) {
+				case BSHFL_DSBH:
+				case BSHFL_DSHD:
+					switch (sub10) {
+					case BSHFL_DSBH: debug("dsbh"); break;
+					case BSHFL_DSHD: debug("dshd"); break;
+					}
+					debug("\t%s", regnames[rd]);
+					debug(",%s", regnames[rt]);
+					break;
+				default:debug("%s", special3_names[special6]);
+					debug("\t(UNIMPLEMENTED)");
+				}
+				break;
+
+			case SPECIAL3_RDHWR:
+				debug("%s", special3_names[special6]);
+				debug("\t%s", regnames[rt]);
+				debug(",hwr%i", rd);
+				break;
+
+			default:debug("%s", special3_names[special6]);
+				debug("\t(UNIMPLEMENTED)");
+			}
+			break;
+		}
+
+		rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+		rt = instr[2] & 31;
+		imm = (instr[1] << 8) + instr[0];
+		if (imm >= 32768)
+			imm -= 65536;
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    cpu->cd.mips.gpr[rs] + imm, &offset);
+
+		/*  LWC3 is PREF in the newer ISA levels:  */
+		/*  TODO: Which ISAs? IV? V? 32? 64?  */
+		if (cpu->cd.mips.cpu_type.isa_level >= 4 && hi6 == HI6_LWC3) {
+			debug("pref\t0x%x,%i(%s)",
+			    rt, imm, regnames[rs]);
+
+			if (running) {
+				debug("\t[0x%016" PRIx64" = %s]",
+				    (uint64_t)(cpu->cd.mips.gpr[rs] + imm));
+				if (symbol != NULL)
+					debug(" = %s", symbol);
+				debug("]");
+			}
+			goto disasm_ret;
+		}
+
+		debug("%s\t", hi6_names[hi6]);
+
+		if (hi6 == HI6_SWC1 || hi6 == HI6_SWC2 || hi6 == HI6_SWC3 ||
+		    hi6 == HI6_SDC1 || hi6 == HI6_SDC2 ||
+		    hi6 == HI6_LWC1 || hi6 == HI6_LWC2 || hi6 == HI6_LWC3 ||
+		    hi6 == HI6_LDC1 || hi6 == HI6_LDC2)
+			debug("r%i", rt);
+		else
+			debug("%s", regnames[rt]);
+
+		debug(",%i(%s)", imm, regnames[rs]);
+
+		if (running) {
+			debug("\t[");
+
+			if (cpu->is_32bit)
+				debug("0x%08" PRIx32,
+				    (uint32_t) (cpu->cd.mips.gpr[rs] + imm));
+			else
+				debug("0x%016" PRIx64,
+				    (uint64_t) (cpu->cd.mips.gpr[rs] + imm));
+
+			if (symbol != NULL)
+				debug(" = %s", symbol);
+
+			/*  TODO: In some cases, it is possible to peek into
+			    memory, and display that data here, like for the
+			    other emulation modes.  */
+
+			debug("]");
+		}
+		break;
+
+	case HI6_J:
+	case HI6_JAL:
+		imm = (((instr[3] & 3) << 24) + (instr[2] << 16) +
+		    (instr[1] << 8) + instr[0]) << 2;
+		addr = (dumpaddr + 4) & ~((1 << 28) - 1);
+		addr |= imm;
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    addr, &offset);
+		debug("%s\t0x", hi6_names[hi6]);
+		if (cpu->is_32bit)
+			debug("%08" PRIx32, (uint32_t) addr);
+		else
+			debug("%016" PRIx64, (uint64_t) addr);
+		if (symbol != NULL)
+			debug("\t<%s>", symbol);
+		break;
+
+	case HI6_COP0:
+	case HI6_COP1:
+	case HI6_COP2:
+	case HI6_COP3:
+		imm = (instr[3] << 24) + (instr[2] << 16) +
+		     (instr[1] << 8) + instr[0];
+		imm &= ((1 << 26) - 1);
+
+		/*  Call coproc_function(), but ONLY disassembly, no exec:  */
+		coproc_function(cpu, cpu->cd.mips.coproc[hi6 - HI6_COP0],
+		    hi6 - HI6_COP0, imm, 1, running);
+		return sizeof(instrword);
+
+	case HI6_CACHE:
+		rt   = ((instr[3] & 3) << 3) + (instr[2] >> 5); /*  base  */
+		copz = instr[2] & 31;
+		imm  = (instr[1] << 8) + instr[0];
+		cache_op    = copz >> 2;
+		which_cache = copz & 3;
+		showtag = 0;
+		debug("cache\t0x%02x,0x%04x(%s)", copz, imm, regnames[rt]);
+		if (which_cache==0)	debug("  [ primary I-cache");
+		if (which_cache==1)	debug("  [ primary D-cache");
+		if (which_cache==2)	debug("  [ secondary I-cache");
+		if (which_cache==3)	debug("  [ secondary D-cache");
+		debug(", ");
+		if (cache_op==0)	debug("index invalidate");
+		if (cache_op==1)	debug("index load tag");
+		if (cache_op==2)	debug("index store tag"), showtag=1;
+		if (cache_op==3)	debug("create dirty exclusive");
+		if (cache_op==4)	debug("hit invalidate");
+		if (cache_op==5)     debug("fill OR hit writeback invalidate");
+		if (cache_op==6)	debug("hit writeback");
+		if (cache_op==7)	debug("hit set virtual");
+		if (running)
+			debug(", addr 0x%016" PRIx64,
+			    (uint64_t)(cpu->cd.mips.gpr[rt] + imm));
+		if (showtag)
+		debug(", taghi=%08lx lo=%08lx",
+		    (long)cpu->cd.mips.coproc[0]->reg[COP0_TAGDATA_HI],
+		    (long)cpu->cd.mips.coproc[0]->reg[COP0_TAGDATA_LO]);
+		debug(" ]");
+		break;
+
+	case HI6_SPECIAL2:
+		special6 = instr[0] & 0x3f;
+		instrword = (instr[3] << 24) + (instr[2] << 16) +
+		    (instr[1] << 8) + instr[0];
+		rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+		rt = instr[2] & 31;
+		rd = (instr[1] >> 3) & 31;
+
+		if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
+			int c790mmifunc = (instrword >> 6) & 0x1f;
+			if (special6 != MMI_MMI0 && special6 != MMI_MMI1 &&
+			    special6 != MMI_MMI2 && special6 != MMI_MMI3)
+				debug("%s\t", mmi_names[special6]);
+
+			switch (special6) {
+
+			case MMI_MADD:
+			case MMI_MADDU:
+				if (rd != MIPS_GPR_ZERO) {
+					debug("%s,", regnames[rd]);
+				}
+				debug("%s,%s", regnames[rs], regnames[rt]);
+				break;
+
+			case MMI_MMI0:
+				debug("%s\t", mmi0_names[c790mmifunc]);
+				switch (c790mmifunc) {
+
+				case MMI0_PEXTLB:
+				case MMI0_PEXTLH:
+				case MMI0_PEXTLW:
+				case MMI0_PMAXH:
+				case MMI0_PMAXW:
+				case MMI0_PPACB:
+				case MMI0_PPACH:
+				case MMI0_PPACW:
+					debug("%s,%s,%s", regnames[rd],
+					    regnames[rs], regnames[rt]);
+					break;
+
+				default:debug("(UNIMPLEMENTED)");
+				}
+				break;
+
+			case MMI_MMI1:
+				debug("%s\t", mmi1_names[c790mmifunc]);
+				switch (c790mmifunc) {
+
+				case MMI1_PEXTUB:
+				case MMI1_PEXTUH:
+				case MMI1_PEXTUW:
+				case MMI1_PMINH:
+				case MMI1_PMINW:
+					debug("%s,%s,%s", regnames[rd],
+					    regnames[rs], regnames[rt]);
+					break;
+
+				default:debug("(UNIMPLEMENTED)");
+				}
+				break;
+
+			case MMI_MMI2:
+				debug("%s\t", mmi2_names[c790mmifunc]);
+				switch (c790mmifunc) {
+
+				case MMI2_PMFHI:
+				case MMI2_PMFLO:
+					debug("%s", regnames[rd]);
+					break;
+
+				case MMI2_PHMADH:
+				case MMI2_PHMSBH:
+				case MMI2_PINTH:
+				case MMI2_PMADDH:
+				case MMI2_PMADDW:
+				case MMI2_PMSUBH:
+				case MMI2_PMSUBW:
+				case MMI2_PMULTH:
+				case MMI2_PMULTW:
+				case MMI2_PSLLVW:
+					debug("%s,%s,%s", regnames[rd],
+					    regnames[rs], regnames[rt]);
+					break;
+
+				default:debug("(UNIMPLEMENTED)");
+				}
+				break;
+
+			case MMI_MMI3:
+				debug("%s\t", mmi3_names[c790mmifunc]);
+				switch (c790mmifunc) {
+
+				case MMI3_PMTHI:
+				case MMI3_PMTLO:
+					debug("%s", regnames[rs]);
+					break;
+
+				case MMI3_PINTEH:
+				case MMI3_PMADDUW:
+				case MMI3_PMULTUW:
+				case MMI3_PNOR:
+				case MMI3_POR:
+				case MMI3_PSRAVW:
+					debug("%s,%s,%s", regnames[rd],
+					    regnames[rs], regnames[rt]);
+					break;
+
+				default:debug("(UNIMPLEMENTED)");
+				}
+				break;
+
+			default:debug("(UNIMPLEMENTED)");
+			}
+			break;
+		}
+
+		/*  SPECIAL2:  */
+		debug("%s\t", special2_names[special6]);
+
+		switch (special6) {
+
+		case SPECIAL2_MADD:
+		case SPECIAL2_MADDU:
+		case SPECIAL2_MSUB:
+		case SPECIAL2_MSUBU:
+			if (rd != MIPS_GPR_ZERO) {
+				debug("WEIRD_NONZERO_RD(%s),",
+				    regnames[rd]);
+			}
+			debug("%s,%s", regnames[rs], regnames[rt]);
+			break;
+
+		case SPECIAL2_MUL:
+			/*  Apparently used both on R5900 and MIPS32:  */
+			debug("%s,%s,%s", regnames[rd],
+			    regnames[rs], regnames[rt]);
+			break;
+
+		case SPECIAL2_CLZ:
+		case SPECIAL2_CLO:
+		case SPECIAL2_DCLZ:
+		case SPECIAL2_DCLO:
+			debug("%s,%s", regnames[rd], regnames[rs]);
+			break;
+
+		default:
+			debug("(UNIMPLEMENTED)");
+		}
+		break;
+
+	case HI6_REGIMM:
+		regimm5 = instr[2] & 0x1f;
+		rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
+		imm = (instr[1] << 8) + instr[0];
+		if (imm >= 32768)               
+			imm -= 65536;
+
+		switch (regimm5) {
+
+		case REGIMM_BLTZ:
+		case REGIMM_BGEZ:
+		case REGIMM_BLTZL:
+		case REGIMM_BGEZL:
+		case REGIMM_BLTZAL:
+		case REGIMM_BLTZALL:
+		case REGIMM_BGEZAL:
+		case REGIMM_BGEZALL:
+			debug("%s\t%s,", regimm_names[regimm5], regnames[rs]);
+
+			addr = (dumpaddr + 4) + (imm << 2);
+
+			if (cpu->is_32bit)
+				debug("0x%08" PRIx32, (uint32_t) addr);
+			else
+				debug("0x%016" PRIx64, (uint64_t) addr);
+			break;
+
+		case REGIMM_TGEI:
+		case REGIMM_TGEIU:
+		case REGIMM_TLTI:
+		case REGIMM_TLTIU:
+		case REGIMM_TEQI:
+		case REGIMM_TNEI:
+			debug("%s\t%s,", regimm_names[regimm5], regnames[rs]);
+
+			if (cpu->is_32bit)
+				debug("0x%" PRIx32, (uint32_t) imm);
+			else
+				debug("0x%" PRIx64, (uint64_t) imm);
+			break;
+
+		case REGIMM_SYNCI:
+			debug("%s\t%i(%s)", regimm_names[regimm5],
+			    imm, regnames[rs]);
+			break;
+
+		default:
+			debug("unimplemented regimm5 = 0x%02x", regimm5);
+		}
+		break;
+	default:
+		debug("unimplemented hi6 = 0x%02x", hi6);
+	}
+
+disasm_ret:
+	debug("\n");
+	return sizeof(instrword);
+}
+
+
+/*
+ *  mips_cpu_register_dump():
+ *
+ *  Dump cpu registers in a relatively readable format.
+ *
+ *  gprs: set to non-zero to dump GPRs and hi/lo/pc
+ *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
+ */
+void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
+{
+	int coprocnr, i, bits32;
+	uint64_t offset;
+	char *symbol;
+	int bits128 = cpu->cd.mips.cpu_type.rev == MIPS_R5900;
+
+	bits32 = cpu->is_32bit;
+
+	if (gprs) {
+		/*  Special registers (pc, hi/lo) first:  */
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    cpu->pc, &offset);
+
+		if (bits32)
+			debug("cpu%i:  pc = %08" PRIx32,
+			    cpu->cpu_id, (uint32_t) cpu->pc);
+		else if (bits128)
+			debug("cpu%i:  pc=%016" PRIx64,
+			    cpu->cpu_id, (uint64_t) cpu->pc);
+		else
+			debug("cpu%i:    pc = 0x%016" PRIx64,
+			    cpu->cpu_id, (uint64_t) cpu->pc);
+
+		debug("    <%s>\n", symbol != NULL? symbol :
+		    " no symbol ");
+
+		if (bits32)
+			debug("cpu%i:  hi = %08" PRIx32"  lo = %08" PRIx32"\n",
+			    cpu->cpu_id, (uint32_t) cpu->cd.mips.hi,
+			    (uint32_t) cpu->cd.mips.lo);
+		else if (bits128) {
+			debug("cpu%i:  hi=%016" PRIx64"%016" PRIx64"  lo="
+			    "%016" PRIx64"%016" PRIx64"\n", cpu->cpu_id,
+			    cpu->cd.mips.hi1, cpu->cd.mips.hi,
+			    cpu->cd.mips.lo1, cpu->cd.mips.lo);
+		} else {
+			debug("cpu%i:    hi = 0x%016" PRIx64"    lo = 0x%016"
+			    PRIx64"\n", cpu->cpu_id,
+			    (uint64_t) cpu->cd.mips.hi,
+			    (uint64_t) cpu->cd.mips.lo);
+		}
+
+		/*  General registers:  */
+		if (bits128) {
+			/*  128-bit:  */
+			for (i=0; i<32; i++) {
+				int r = (i >> 1) + ((i & 1) << 4);
+				if ((i & 1) == 0)
+					debug("cpu%i:", cpu->cpu_id);
+				if (r == MIPS_GPR_ZERO)
+					debug("                           "
+					    "          ");
+				else
+					debug(" %3s=%016" PRIx64"%016" PRIx64,
+					    regnames[r], (uint64_t)
+					    cpu->cd.mips.gpr_quadhi[r],
+					    (uint64_t)cpu->cd.mips.gpr[r]);
+				if ((i & 1) == 1)
+					debug("\n");
+			}
+		} else if (bits32) {
+			/*  32-bit:  */
+			for (i=0; i<32; i++) {
+				if ((i & 3) == 0)
+					debug("cpu%i:", cpu->cpu_id);
+				if (i == MIPS_GPR_ZERO)
+					debug("               ");
+				else
+					debug(" %3s = %08" PRIx32, regnames[i],
+					    (uint32_t)cpu->cd.mips.gpr[i]);
+				if ((i & 3) == 3)
+					debug("\n");
+			}
+		} else {
+			/*  64-bit:  */
+			for (i=0; i<32; i++) {
+				int r = (i >> 1) + ((i & 1) << 4);
+				if ((i & 1) == 0)
+					debug("cpu%i:", cpu->cpu_id);
+				if (r == MIPS_GPR_ZERO)
+					debug("                           ");
+				else
+					debug("   %3s = 0x%016" PRIx64,
+					    regnames[r],
+					    (uint64_t)cpu->cd.mips.gpr[r]);
+				if ((i & 1) == 1)
+					debug("\n");
+			}
+		}
+	}
+
+	for (coprocnr=0; coprocnr<4; coprocnr++) {
+		int nm1 = 1;
+
+		if (bits32)
+			nm1 = 3;
+
+		if (!(coprocs & (1<<coprocnr)))
+			continue;
+		if (cpu->cd.mips.coproc[coprocnr] == NULL) {
+			debug("cpu%i: no coprocessor %i\n",
+			    cpu->cpu_id, coprocnr);
+			continue;
+		}
+
+		/*  Coprocessor registers:  */
+		for (i=0; i<32; i++) {
+			/*  32-bit:  */
+			if ((i & nm1) == 0)
+				debug("cpu%i:", cpu->cpu_id);
+
+			if (coprocnr == 0)
+				debug(" %8s", cop0_names[i]);
+			else
+				debug(" c%i,%02i", coprocnr, i);
+
+			if (bits32)
+				debug("=%08x", (int)cpu->cd.mips.
+				    coproc[coprocnr]->reg[i]);
+			else {
+				if (coprocnr == 0 && (i == COP0_COUNT
+				    || i == COP0_COMPARE || i == COP0_INDEX
+				    || i == COP0_RANDOM || i == COP0_WIRED))
+					debug(" =         0x%08x",
+					    (int) cpu->cd.mips.coproc[
+					    coprocnr]->reg[i]);
+				else
+					debug(" = 0x%016" PRIx64, (uint64_t)
+					    cpu->cd.mips.coproc[
+					    coprocnr]->reg[i]);
+			}
+
+			if ((i & nm1) == nm1)
+				debug("\n");
+
+			/*  Skip the last 16 cop0 registers on R3000 etc.  */
+			if (coprocnr == 0 && cpu->cd.mips.cpu_type.isa_level < 3
+			    && i == 15)
+				i = 31;
+		}
+
+		if (coprocnr == 0 && cpu->cd.mips.cpu_type.isa_level >= 32) {
+			debug("cpu%i: ", cpu->cpu_id);
+			debug("config_select1 = 0x");
+			if (cpu->is_32bit)
+				debug("%08" PRIx32,
+				    (uint32_t)cpu->cd.mips.cop0_config_select1);
+			else
+				debug("%016" PRIx64,
+				    (uint64_t)cpu->cd.mips.cop0_config_select1);
+			debug("\n");
+		}
+
+		/*  Floating point control registers:  */
+		if (coprocnr == 1) {
+			for (i=0; i<32; i++)
+				switch (i) {
+				case MIPS_FPU_FCIR:
+					printf("cpu%i: fcr0  (fcir) = 0x%08x\n",
+					    cpu->cpu_id, (int)cpu->cd.mips.
+					    coproc[coprocnr]->fcr[i]);
+					break;
+				case MIPS_FPU_FCCR:
+					printf("cpu%i: fcr25 (fccr) = 0x%08x\n",
+					    cpu->cpu_id, (int)cpu->cd.mips.
+					    coproc[coprocnr]->fcr[i]);
+					break;
+				case MIPS_FPU_FCSR:
+					printf("cpu%i: fcr31 (fcsr) = 0x%08x\n",
+					    cpu->cpu_id, (int)cpu->cd.mips.
+					    coproc[coprocnr]->fcr[i]);
+					break;
+				}
+		}
+	}
+
+	if (cpu->cd.mips.rmw) {
+		printf("cpu%i: Read-Modify-Write in progress, address "
+		    "0x%016" PRIx64"\n", cpu->cpu_id, cpu->cd.mips.rmw_addr);
+	}
+}
+
+
+/*
+ *  mips_cpu_interrupt_assert(), mips_cpu_interrupt_deassert():
+ *
+ *  Assert or deassert a MIPS CPU interrupt by masking in or out bits
+ *  in the CAUSE register of coprocessor 0.
+ */
+void mips_cpu_interrupt_assert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] |= interrupt->line;
+}
+void mips_cpu_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] &= ~interrupt->line;
+}
+
+
+/*
+ *  mips_cpu_exception():
+ *
+ *  Cause an exception in a CPU.  This sets a couple of coprocessor 0
+ *  registers, and the program counter.
+ *
+ *	exccode		the exception code
+ *	tlb		set to non-zero if the exception handler at
+ *			0x80000000 should be used. (normal = 0x80000180)
+ *	vaddr		virtual address (for some exceptions)
+ *	coproc_nr	coprocessor number (for some exceptions)
+ *	vaddr_vpn2	vpn2 (for some exceptions)
+ *	vaddr_asid	asid (for some exceptions)
+ *	x_64		non-zero for 64-bit mode for R4000-style tlb misses
+ */
+void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,
+	int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64)
+{
+	uint64_t base;
+	uint64_t *reg = &cpu->cd.mips.coproc[0]->reg[0];
+	int exc_model = cpu->cd.mips.cpu_type.exc_model;
+
+	if (cpu->is_halted) {
+		/*
+		 *  If the exception occurred on a 'wait' instruction, then let
+		 *  the instruction following the wait instruction be the one
+		 *  we continue at when the interrupt service routine returns.
+		 */
+		cpu->is_halted = false;
+		cpu->pc += sizeof(uint32_t);
+
+		debugmsg_cpu(cpu, SUBSYS_CPU, "wakeup", VERBOSITY_DEBUG,
+		    "waking up from halted state");
+	}
+
+	if (!quiet_mode) {
+		uint64_t offset;
+		int x;
+		char *symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    cpu->pc, &offset);
+
+
+		// TODO: build up full exception string...
+		//debugmsg_cpu(cpu, SUBSYS_EXCEPTION, exception_names[exccode], VERBOSITY_INFO, "todo");
+
+
+		debug("[ ");
+		if (cpu->machine->ncpus > 1)
+			debug("cpu%i: ", cpu->cpu_id);
+
+		debug("exception %s%s",
+		    exception_names[exccode], tlb? " <tlb>" : "");
+
+		switch (exccode) {
+
+		case EXCEPTION_INT:
+			debug(" cause_im=0x%02x", (int)
+			    ((reg[COP0_CAUSE] & CAUSE_IP_MASK)
+			    >> CAUSE_IP_SHIFT));
+			break;
+
+		case EXCEPTION_SYS:
+			debug(" v0=%i", (int)cpu->cd.mips.gpr[MIPS_GPR_V0]);
+			for (x=0; x<4; x++) {
+				int64_t d = cpu->cd.mips.gpr[MIPS_GPR_A0 + x];
+				char strbuf[30];
+
+				if (d > -256 && d < 256) {
+					debug(" a%i=%i", x, (int)d);
+				} else if (memory_points_to_string(cpu,
+				    cpu->mem, d, 1)) {
+					debug(" a%i=\"%s\"", x,
+					    memory_conv_to_string(cpu, cpu->mem,
+					    d, strbuf, sizeof(strbuf)));
+				} else {
+					if (cpu->is_32bit)
+						debug(" a%i=0x%" PRIx32, x,
+						    (uint32_t)d);
+					else
+						debug(" a%i=0x%" PRIx64, x,
+						    (uint64_t)d);
+				}
+			}
+			break;
+
+		case EXCEPTION_CPU:
+			debug(" coproc_nr=%i", coproc_nr);
+			break;
+
+		default:
+			if (cpu->is_32bit)
+				debug(" vaddr=0x%08x", (int)vaddr);
+			else
+				debug(" vaddr=0x%016" PRIx64, (uint64_t)vaddr);
+		}
+
+		if (cpu->is_32bit)
+			debug(" pc=0x%08" PRIx32" ", (uint32_t)cpu->pc);
+		else
+			debug(" pc=0x%016" PRIx64" ", (uint64_t)cpu->pc);
+
+		if (symbol != NULL)
+			debug("<%s> ]\n", symbol);
+		else
+			debug("]\n");
+	}
+
+	if (tlb && vaddr < 0x1000) {
+		uint64_t offset;
+		char *symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    cpu->pc, &offset);
+
+		// TODO: debugmsg SUBSYS_CPU, or better: SUBSYS_EXCEPTION
+		// VERBOSITY_WARNING since this is a relatively sure sign of a bug.
+
+		fatal("[ ");
+		if (cpu->machine->ncpus > 1)
+			fatal("cpu%i: ", cpu->cpu_id);
+		fatal("warning: LOW reference: vaddr=");
+		if (cpu->is_32bit)
+			fatal("0x%08" PRIx32, (uint32_t) vaddr);
+		else
+			fatal("0x%016" PRIx64, (uint64_t) vaddr);
+		fatal(", exception %s, pc=", exception_names[exccode]);
+		if (cpu->is_32bit)
+			fatal("0x%08" PRIx32, (uint32_t) cpu->pc);
+		else
+			fatal("0x%016" PRIx64, (uint64_t)cpu->pc);
+		fatal(" <%s> ]\n", symbol? symbol : "(no symbol)");
+	}
+
+	/*  Clear the exception code bits of the cause register...  */
+	if (exc_model == EXC3K)
+		reg[COP0_CAUSE] &= ~R2K3K_CAUSE_EXCCODE_MASK;
+	else
+		reg[COP0_CAUSE] &= ~CAUSE_EXCCODE_MASK;
+
+	/*  ... and OR in the exception code:  */
+	reg[COP0_CAUSE] |= (exccode << CAUSE_EXCCODE_SHIFT);
+
+	/*  Always set CE (according to the R5000 manual):  */
+	reg[COP0_CAUSE] &= ~CAUSE_CE_MASK;
+	reg[COP0_CAUSE] |= (coproc_nr << CAUSE_CE_SHIFT);
+
+	if (tlb || (exccode >= EXCEPTION_MOD && exccode <= EXCEPTION_ADES) ||
+	    exccode == EXCEPTION_VCEI || exccode == EXCEPTION_VCED) {
+		reg[COP0_BADVADDR] = vaddr;
+		if (cpu->is_32bit)
+			reg[COP0_BADVADDR] = (int32_t)reg[COP0_BADVADDR];
+
+		if (exc_model == EXC3K) {
+			reg[COP0_CONTEXT] &= ~R2K3K_CONTEXT_BADVPN_MASK;
+			reg[COP0_CONTEXT] |= ((vaddr_vpn2 <<
+			    R2K3K_CONTEXT_BADVPN_SHIFT) &
+			    R2K3K_CONTEXT_BADVPN_MASK);
+
+			reg[COP0_ENTRYHI] = (vaddr & R2K3K_ENTRYHI_VPN_MASK)
+			    | (vaddr_asid << R2K3K_ENTRYHI_ASID_SHIFT);
+
+			/*  Sign-extend:  */
+			reg[COP0_CONTEXT] = (int64_t)(int32_t)reg[COP0_CONTEXT];
+			reg[COP0_ENTRYHI] = (int64_t)(int32_t)reg[COP0_ENTRYHI];
+		} else {
+			if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
+				reg[COP0_CONTEXT] &=
+				    ~CONTEXT_BADVPN2_MASK_R4100;
+				reg[COP0_CONTEXT] |= ((vaddr_vpn2 <<
+				    CONTEXT_BADVPN2_SHIFT) &
+				    CONTEXT_BADVPN2_MASK_R4100);
+
+				/*  TODO:  fix these  */
+				reg[COP0_XCONTEXT] &= ~XCONTEXT_R_MASK;
+				reg[COP0_XCONTEXT] &= ~XCONTEXT_BADVPN2_MASK;
+				reg[COP0_XCONTEXT] |= (vaddr_vpn2 << XCONTEXT_BADVPN2_SHIFT) & XCONTEXT_BADVPN2_MASK;
+				reg[COP0_XCONTEXT] |= ((vaddr >> 62) & 0x3) << XCONTEXT_R_SHIFT;
+
+				/*  reg[COP0_PAGEMASK] = cpu->cd.mips.coproc[0]->tlbs[0].mask & PAGEMASK_MASK;  */
+
+				reg[COP0_ENTRYHI] = (vaddr & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK | 0x1800)) | vaddr_asid;
+			} else {
+				reg[COP0_CONTEXT] &= ~CONTEXT_BADVPN2_MASK;
+				reg[COP0_CONTEXT] |= ((vaddr_vpn2 << CONTEXT_BADVPN2_SHIFT) & CONTEXT_BADVPN2_MASK);
+
+				reg[COP0_XCONTEXT] &= ~XCONTEXT_R_MASK;
+				reg[COP0_XCONTEXT] &= ~XCONTEXT_BADVPN2_MASK;
+				reg[COP0_XCONTEXT] |= (vaddr_vpn2 << XCONTEXT_BADVPN2_SHIFT) & XCONTEXT_BADVPN2_MASK;
+				reg[COP0_XCONTEXT] |= ((vaddr >> 62) & 0x3) << XCONTEXT_R_SHIFT;
+
+				/*  reg[COP0_PAGEMASK] = cpu->cd.mips.coproc[0]->tlbs[0].mask & PAGEMASK_MASK;  */
+
+				// Actually, the R10000 manual says:
+				// "When either a TLB refill, TLB invalid, or TLB modified exception occurs, the
+				//  EntryHi register is loaded with the virtual page number (VPN2) and the ASID of
+				//  the virtual address that did not have a matching TLB entry."
+				// Strange that it does not mention the 2 top bits (R).
+				//
+				// However, the MIPS64 manual says:
+				// "A TLB exception (TLB Refill, XTLB Refill, TLB Invalid, or TLB Modified) causes
+				//  the bits of the virtual address corresponding to the R and VPN2 fields to be
+				//  written into the EntryHi register."
+
+				if ((reg[COP0_ENTRYHI] & ENTRYHI_ASID) != (uint32_t)vaddr_asid)
+					fatal("[ huh? vaddr_asid 0x%02x not same as in ENTRYHI 0x%02x ]\n",
+						vaddr_asid, reg[COP0_ENTRYHI] & ENTRYHI_ASID);
+
+				if (cpu->cd.mips.cpu_type.mmu_model == MMU10K)
+					reg[COP0_ENTRYHI] = (vaddr & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K)) | vaddr_asid;
+				else
+					reg[COP0_ENTRYHI] = (vaddr & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK)) | vaddr_asid;
+			}
+		}
+	}
+
+	if (exc_model != EXC3K && reg[COP0_STATUS] & STATUS_EXL) {
+		/*
+		 *  Don't set EPC if STATUS_EXL is set, for R4000 and up.
+		 *  This actually happens when running IRIX and Ultrix, when
+		 *  they handle interrupts and/or tlb updates, I think, so
+		 *  printing this with debug() looks better than with fatal().
+		 */
+		/*  debug("[ warning: cpu%i exception while EXL is set,"
+		    " not setting EPC ]\n", cpu->cpu_id);  */
+	} else {
+		if (cpu->delay_slot) {
+			reg[COP0_EPC] = cpu->pc - 4;
+			reg[COP0_CAUSE] |= CAUSE_BD;
+		} else {
+			reg[COP0_EPC] = cpu->pc;
+			reg[COP0_CAUSE] &= ~CAUSE_BD;
+		}
+	}
+
+	if (cpu->delay_slot)
+		cpu->delay_slot = EXCEPTION_IN_DELAY_SLOT;
+	else
+		cpu->delay_slot = NOT_DELAYED;
+
+	/*  TODO: This is true for MIPS64, but how about others?  */
+	if (reg[COP0_STATUS] & STATUS_BEV)
+		base = 0xffffffffbfc00200ULL;
+	else
+		base = 0xffffffff80000000ULL;
+
+	switch (exc_model) {
+	case EXC3K:
+		/*  Userspace tlb, vs others:  */
+		if (tlb && !(vaddr & 0x80000000ULL) &&
+		    (exccode == EXCEPTION_TLBL || exccode == EXCEPTION_TLBS) )
+			cpu->pc = base + 0x000;
+		else
+			cpu->pc = base + 0x080;
+		break;
+	default:
+		/*
+		 *  These offsets are according to the MIPS64 manual, but
+		 *  should work with R4000 and the rest too (I hope).
+		 *
+		 *  0x000  TLB refill, if EXL=0
+		 *  0x080  64-bit XTLB refill, if EXL=0
+		 *  0x100  cache error  (not implemented yet)
+		 *  0x180  general exception
+		 *  0x200  interrupt (if CAUSE_IV is set)
+		 */
+		if (tlb && (exccode == EXCEPTION_TLBL ||
+		    exccode == EXCEPTION_TLBS) &&
+		    !(reg[COP0_STATUS] & STATUS_EXL)) {
+			if (x_64)
+				cpu->pc = base + 0x080;
+			else
+				cpu->pc = base + 0x000;
+		} else {
+			if (exccode == EXCEPTION_INT &&
+			    (reg[COP0_CAUSE] & CAUSE_IV))
+				cpu->pc = base + 0x200;
+			else
+				cpu->pc = base + 0x180;
+		}
+	}
+
+	if (exc_model == EXC3K) {
+		/*  R{2,3}000:  Shift the lowest 6 bits to the left two steps:*/
+		reg[COP0_STATUS] = (reg[COP0_STATUS] & ~0x3f) +
+		    ((reg[COP0_STATUS] & 0xf) << 2);
+	} else {
+		/*  R4000:  */
+		reg[COP0_STATUS] |= STATUS_EXL;
+	}
+
+	/*  Sign-extend:  */
+	reg[COP0_CAUSE] = (int64_t)(int32_t)reg[COP0_CAUSE];
+	reg[COP0_STATUS] = (int64_t)(int32_t)reg[COP0_STATUS];
+
+	if (cpu->is_32bit) {
+		reg[COP0_EPC] = (int64_t)(int32_t)reg[COP0_EPC];
+		mips32_pc_to_pointers(cpu);
+	} else {
+		mips_pc_to_pointers(cpu);
+	}
+}
+
+
+#include "memory_mips.c"
+
+
+#include "tmp_mips_tail.c"
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_mips.cc gxemul-0.7.0+dfsg/src/cpus/cpu_mips.cc
--- gxemul-0.6.2/src/cpus/cpu_mips.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_mips.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,2018 +0,0 @@
-/*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  MIPS core CPU emulation.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-#include <ctype.h>
-#include <unistd.h>
-
-#include "../../config.h"
-
-#include "arcbios.h"
-#include "cop0.h"
-#include "cpu.h"
-#include "cpu_mips.h"
-#include "debugger.h"
-#include "devices.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "mips_cpu_types.h"
-#include "opcodes_mips.h"
-#include "settings.h"
-#include "symbol.h"
-
-
-static const char *exception_names[] = EXCEPTION_NAMES;
-
-static const char *hi6_names[] = HI6_NAMES;
-static const char *regimm_names[] = REGIMM_NAMES;
-static const char *special_names[] = SPECIAL_NAMES;
-static const char *special_rot_names[] = SPECIAL_ROT_NAMES;
-static const char *special2_names[] = SPECIAL2_NAMES;
-static const char *mmi_names[] = MMI_NAMES;
-static const char *mmi0_names[] = MMI0_NAMES;
-static const char *mmi1_names[] = MMI1_NAMES;
-static const char *mmi2_names[] = MMI2_NAMES;
-static const char *mmi3_names[] = MMI3_NAMES;
-static const char *special3_names[] = SPECIAL3_NAMES;
-
-static const char *regnames[] = MIPS_REGISTER_NAMES;
-static const char *cop0_names[] = COP0_NAMES;
-
-
-#define DYNTRANS_DUALMODE_32
-#define DYNTRANS_DELAYSLOT
-#include "tmp_mips_head.cc"
-
-void mips_pc_to_pointers(struct cpu *);
-void mips32_pc_to_pointers(struct cpu *);
-
-
-/*
- *  mips_cpu_new():
- *
- *  Create a new MIPS cpu object.
- *
- *  Returns 1 on success, 0 if there was no valid MIPS processor with
- *  a matching name.
- */
-int mips_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
-	int cpu_id, char *cpu_type_name)
-{
-	int i, found, j, tags_size, n_cache_lines, size_per_cache_line;
-	struct mips_cpu_type_def cpu_type_defs[] = MIPS_CPU_TYPE_DEFS;
-	int64_t secondary_cache_size;
-	int x, linesize;
-
-	/*  Scan the cpu_type_defs list for this cpu type:  */
-	i = 0;
-	found = -1;
-	while (i >= 0 && cpu_type_defs[i].name != NULL) {
-		if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
-			found = i;
-			break;
-		}
-		i++;
-	}
-
-	if (found == -1)
-		return 0;
-
-	cpu->memory_rw                = mips_memory_rw;
-	cpu->cd.mips.cpu_type         = cpu_type_defs[found];
-	cpu->name                     = strdup(cpu->cd.mips.cpu_type.name);
-	cpu->byte_order               = EMUL_LITTLE_ENDIAN;
-	cpu->cd.mips.gpr[MIPS_GPR_SP] = INITIAL_STACK_POINTER;
-
-	if (cpu->cd.mips.cpu_type.isa_level <= 2 ||
-	    cpu->cd.mips.cpu_type.isa_level == 32)
-		cpu->is_32bit = 1;
-
-	if (cpu->is_32bit) {
-		cpu->run_instr = mips32_run_instr;
-		cpu->update_translation_table = mips32_update_translation_table;
-		cpu->invalidate_translation_caches =
-		    mips32_invalidate_translation_caches;
-		cpu->invalidate_code_translation =
-		    mips32_invalidate_code_translation;
-	} else {
-		cpu->run_instr = mips_run_instr;
-		cpu->update_translation_table = mips_update_translation_table;
-		cpu->invalidate_translation_caches =
-		    mips_invalidate_translation_caches;
-		cpu->invalidate_code_translation =
-		    mips_invalidate_code_translation;
-	}
-
-	cpu->instruction_has_delayslot = mips_cpu_instruction_has_delayslot;
-
-	if (cpu_id == 0)
-		debug("%s", cpu->cd.mips.cpu_type.name);
-
-	/*
-	 *  CACHES:
-	 *
-	 *  1) Use DEFAULT_PCACHE_SIZE and DEFAULT_PCACHE_LINESIZE etc.
-	 *  2) If there are specific values defined for this type of cpu,
-	 *     in its cpu_type substruct, then let's use those.
-	 *  3) Values in the emul struct override both of the above.
-	 *
-	 *  Once we've decided which values to use, they are stored in
-	 *  the emul struct so they can be used from src/machine.c etc.
-	 */
-
-	x = DEFAULT_PCACHE_SIZE;
-	if (cpu->cd.mips.cpu_type.pdcache)
-		x = cpu->cd.mips.cpu_type.pdcache;
-	if (cpu->cd.mips.cache_pdcache == 0)
-		cpu->cd.mips.cache_pdcache = x;
-
-	x = DEFAULT_PCACHE_SIZE;
-	if (cpu->cd.mips.cpu_type.picache)
-		x = cpu->cd.mips.cpu_type.picache;
-	if (cpu->cd.mips.cache_picache == 0)
-		cpu->cd.mips.cache_picache = x;
-
-	if (cpu->cd.mips.cache_secondary == 0)
-		cpu->cd.mips.cache_secondary = cpu->cd.mips.cpu_type.scache;
-
-	linesize = DEFAULT_PCACHE_LINESIZE;
-	if (cpu->cd.mips.cpu_type.pdlinesize)
-		linesize = cpu->cd.mips.cpu_type.pdlinesize;
-	if (cpu->cd.mips.cache_pdcache_linesize == 0)
-		cpu->cd.mips.cache_pdcache_linesize = linesize;
-
-	linesize = DEFAULT_PCACHE_LINESIZE;
-	if (cpu->cd.mips.cpu_type.pilinesize)
-		linesize = cpu->cd.mips.cpu_type.pilinesize;
-	if (cpu->cd.mips.cache_picache_linesize == 0)
-		cpu->cd.mips.cache_picache_linesize = linesize;
-
-	linesize = 0;
-	if (cpu->cd.mips.cpu_type.slinesize)
-		linesize = cpu->cd.mips.cpu_type.slinesize;
-	if (cpu->cd.mips.cache_secondary_linesize == 0)
-		cpu->cd.mips.cache_secondary_linesize = linesize;
-
-
-	/*
-	 *  Primary Data and Instruction caches:
-	 */
-	for (i=CACHE_DATA; i<=CACHE_INSTRUCTION; i++) {
-		switch (i) {
-		case CACHE_DATA:
-			x = 1 << cpu->cd.mips.cache_pdcache;
-			linesize = 1 << cpu->cd.mips.cache_pdcache_linesize;
-			break;
-		case CACHE_INSTRUCTION:
-			x = 1 << cpu->cd.mips.cache_picache;
-			linesize = 1 << cpu->cd.mips.cache_picache_linesize;
-			break;
-		}
-
-		/*  Primary cache size and linesize:  */
-		cpu->cd.mips.cache_size[i] = x;
-		cpu->cd.mips.cache_linesize[i] = linesize;
-
-		switch (cpu->cd.mips.cpu_type.rev) {
-		case MIPS_R2000:
-		case MIPS_R3000:
-			size_per_cache_line = sizeof(struct r3000_cache_line);
-			break;
-		default:
-			size_per_cache_line = 32;	/*  TODO  */
-		}
-
-		cpu->cd.mips.cache_mask[i] = cpu->cd.mips.cache_size[i] - 1;
-
-		CHECK_ALLOCATION(cpu->cd.mips.cache[i] = (unsigned char *)
-		    malloc(cpu->cd.mips.cache_size[i]));
-
-		n_cache_lines = cpu->cd.mips.cache_size[i] /
-		    cpu->cd.mips.cache_linesize[i];
-		tags_size = n_cache_lines * size_per_cache_line;
-
-		CHECK_ALLOCATION(cpu->cd.mips.cache_tags[i] =
-		    malloc(tags_size));
-
-		/*  Initialize the cache tags:  */
-		switch (cpu->cd.mips.cpu_type.rev) {
-		case MIPS_R2000:
-		case MIPS_R3000:
-			for (j=0; j<n_cache_lines; j++) {
-				struct r3000_cache_line *rp;
-				rp = (struct r3000_cache_line *)
-				    cpu->cd.mips.cache_tags[i];
-				rp[j].tag_paddr = 0;
-				rp[j].tag_valid = 0;
-			}
-			break;
-		default:
-			;
-		}
-
-		/*  Set cache_last_paddr to something "impossible":  */
-		cpu->cd.mips.cache_last_paddr[i] = IMPOSSIBLE_PADDR;
-	}
-
-	/*
-	 *  Secondary cache:
-	 */
-	secondary_cache_size = 0;
-	if (cpu->cd.mips.cache_secondary)
-		secondary_cache_size = 1 << cpu->cd.mips.cache_secondary;
-	/*  TODO: linesize...  */
-
-	if (cpu_id == 0) {
-		debug(" (I+D = %i+%i KB",
-		    (int)(cpu->cd.mips.cache_size[CACHE_INSTRUCTION] / 1024),
-		    (int)(cpu->cd.mips.cache_size[CACHE_DATA] / 1024));
-
-		if (secondary_cache_size != 0) {
-			debug(", L2 = ");
-			if (secondary_cache_size >= 1048576)
-				debug("%i MB", (int)
-				    (secondary_cache_size / 1048576));
-			else
-				debug("%i KB", (int)
-				    (secondary_cache_size / 1024));
-		}
-
-		debug(")");
-	}
-
-	/*  Register the CPU's interrupts:  */
-	for (i=2; i<8; i++) {
-		struct interrupt templ;
-		char name[50];
-		snprintf(name, sizeof(name), "%s.%i", cpu->path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 1 << (STATUS_IM_SHIFT + i);
-		templ.name = name;
-		templ.extra = cpu;
-		templ.interrupt_assert = mips_cpu_interrupt_assert;
-		templ.interrupt_deassert = mips_cpu_interrupt_deassert;
-		interrupt_handler_register(&templ);
-
-		if (i == 7)
-			INTERRUPT_CONNECT(name, cpu->cd.mips.irq_compare);
-	}
-
-	/*  System coprocessor (0), and FPU (1):  */
-	cpu->cd.mips.coproc[0] = mips_coproc_new(cpu, 0);
-	cpu->cd.mips.coproc[1] = mips_coproc_new(cpu, 1);
-
-	switch (cpu->cd.mips.cpu_type.mmu_model) {
-	case MMU3K:
-		cpu->vaddr_mask = 0x00000000ffffffffULL;
-		cpu->translate_v2p = translate_v2p_mmu3k;
-		break;
-	case MMU8K:
-		cpu->translate_v2p = translate_v2p_mmu8k;
-		break;
-	case MMU10K:
-		cpu->vaddr_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K | 0x1fff;
-		cpu->translate_v2p = translate_v2p_mmu10k;
-		break;
-	default:
-		if (cpu->is_32bit)
-			cpu->vaddr_mask = 0x00000000ffffffffULL;
-		else
-			cpu->vaddr_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK | 0x1fff;
-
-		if (cpu->cd.mips.cpu_type.rev == MIPS_R4100)
-			cpu->translate_v2p = translate_v2p_mmu4100;
-		else
-			cpu->translate_v2p = translate_v2p_generic;
-	}
-
-	// TODO: Consider moving to src/machine/machine_test.cc?
-	// This is only here to make the floating point tests work out-of-the-box.
-	if (!cpu->is_32bit)
-		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |= STATUS_FR;
-
-	if (cpu->machine->prom_emulation) {
-		/*
-		 *  Default behaviour of jumping to 0xbfc00000 should be
-		 *  a reboot, unless machine-specific initialization code
-		 *  overrides this.
-		 *
-		 *  Note: Specifically big-endian machines should override
-		 *  this, since the default MIPS CPU is little-endian!
-		 */
-		store_32bit_word(cpu, 0xffffffff9fc00000ULL, 0x00c0de0d);
-	}
-
-	/*  Add all register names to the settings:  */
-	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
-	CPU_SETTINGS_ADD_REGISTER64("hi", cpu->cd.mips.hi);
-	CPU_SETTINGS_ADD_REGISTER64("lo", cpu->cd.mips.lo);
-	for (i=0; i<N_MIPS_GPRS; i++)
-		CPU_SETTINGS_ADD_REGISTER64(regnames[i], cpu->cd.mips.gpr[i]);
-	/*  TODO: Write via special handler function!  */
-	for (i=0; i<N_MIPS_COPROC_REGS; i++)
-		CPU_SETTINGS_ADD_REGISTER64(cop0_names[i],
-		    cpu->cd.mips.coproc[0]->reg[i]);
-
-	return 1;
-}
-
-
-/*
- *  mips_cpu_dumpinfo():
- *
- *  Debug dump of MIPS-specific CPU data for specific CPU.
- */
-void mips_cpu_dumpinfo(struct cpu *cpu)
-{
-	int iadd = DEBUG_INDENTATION;
-	struct mips_cpu_type_def *ct = &cpu->cd.mips.cpu_type;
-
-	debug_indentation(iadd);
-
-	debug("\n%i-bit %s-endian (MIPS",
-	    cpu->is_32bit? 32 : 64,
-	    cpu->byte_order == EMUL_BIG_ENDIAN? "Big" : "Little");
-
-	switch (ct->isa_level) {
-	case 1:	debug(" ISA I"); break;
-	case 2:	debug(" ISA II"); break;
-	case 3:	debug(" ISA III"); break;
-	case 4:	debug(" ISA IV"); break;
-	case 5:	debug(" ISA V"); break;
-	case 32:
-	case 64:debug("%i, revision %i", ct->isa_level, ct->isa_revision);
-		break;
-	default:debug(" ISA level %i", ct->isa_level);
-	}
-
-	debug("), ");
-	if (ct->nr_of_tlb_entries)
-		debug("%i TLB entries", ct->nr_of_tlb_entries);
-	else
-		debug("no TLB");
-	debug("\n");
-
-	if (ct->picache) {
-		debug("L1 I-cache: %i KB", (1 << ct->picache) / 1024);
-		if (ct->pilinesize)
-			debug(", %i bytes per line", 1 << ct->pilinesize);
-		if (ct->piways > 1)
-			debug(", %i-way", ct->piways);
-		else
-			debug(", direct-mapped");
-		debug("\n");
-	}
-
-	if (ct->pdcache) {
-		debug("L1 D-cache: %i KB", (1 << ct->pdcache) / 1024);
-		if (ct->pdlinesize)
-			debug(", %i bytes per line", 1 << ct->pdlinesize);
-		if (ct->pdways > 1)
-			debug(", %i-way", ct->pdways);
-		else
-			debug(", direct-mapped");
-		debug("\n");
-	}
-
-	if (ct->scache) {
-		int kb = (1 << ct->scache) / 1024;
-		debug("L2 cache: %i %s",
-		    kb >= 1024? kb / 1024 : kb, kb >= 1024? "MB":"KB");
-		if (ct->slinesize)
-			debug(", %i bytes per line", 1 << ct->slinesize);
-		if (ct->sways > 1)
-			debug(", %i-way", ct->sways);
-		else
-			debug(", direct-mapped");
-		debug("\n");
-	}
-
-	debug_indentation(-iadd);
-}
-
-
-/*
- *  mips_cpu_list_available_types():
- *
- *  Print a list of available MIPS CPU types.
- */
-void mips_cpu_list_available_types(void)
-{
-	int i, j;
-	struct mips_cpu_type_def cpu_type_defs[] = MIPS_CPU_TYPE_DEFS;
-
-	i = 0;
-	while (cpu_type_defs[i].name != NULL) {
-		debug("%s", cpu_type_defs[i].name);
-		for (j=10 - strlen(cpu_type_defs[i].name); j>0; j--)
-			debug(" ");
-		i++;
-		if ((i % 6) == 0 || cpu_type_defs[i].name == NULL)
-			debug("\n");
-	}
-}
-
-
-/*
- *  mips_cpu_instruction_has_delayslot():
- *
- *  Return 1 if an opcode is a branch, 0 otherwise.
- */
-int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
-{
-	uint32_t iword = *((uint32_t *)&ib[0]);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		iword = LE32_TO_HOST(iword);
-	else
-		iword = BE32_TO_HOST(iword);
-
-	switch (iword >> 26) {
-	case HI6_SPECIAL:
-		switch (iword & 0x3f) {
-		case SPECIAL_JR:
-		case SPECIAL_JALR:
-			return 1;
-		}
-		break;
-	case HI6_REGIMM:
-		switch ((iword >> 16) & 0x1f) {
-		case REGIMM_BLTZ:
-		case REGIMM_BGEZ:
-		case REGIMM_BLTZL:
-		case REGIMM_BGEZL:
-		case REGIMM_BLTZAL:
-		case REGIMM_BLTZALL:
-		case REGIMM_BGEZAL:
-		case REGIMM_BGEZALL:
-			return 1;
-		}
-		break;
-	case HI6_BEQ:
-	case HI6_BEQL:
-	case HI6_BNE:
-	case HI6_BNEL:
-	case HI6_BGTZ:
-	case HI6_BGTZL:
-	case HI6_BLEZ:
-	case HI6_BLEZL:
-	case HI6_J:
-	case HI6_JAL:
-		return 1;
-	}
-
-	return 0;
-}
-
-
-/*
- *  mips_cpu_tlbdump():
- *
- *  Called from the debugger to dump the TLB in a readable format.
- *  x is the cpu number to dump, or -1 to dump all CPUs.
- *
- *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
- *  just dumped.
- */
-void mips_cpu_tlbdump(struct machine *m, int x, int rawflag)
-{
-	int i, j;
-
-	/*  Raw output:  */
-	if (rawflag) {
-		for (i=0; i<m->ncpus; i++) {
-			struct mips_coproc *cop0 =
-			    m->cpus[i]->cd.mips.coproc[0];
-
-			if (x >= 0 && i != x)
-				continue;
-
-			/*  Print index, random, and wired:  */
-			printf("cpu%i: (", i);
-
-			if (m->cpus[i]->is_32bit)
-				printf("index=0x%08x random=0x%08x",
-				    (int) cop0->reg[COP0_INDEX],
-				    (int) cop0->reg[COP0_RANDOM]);
-			else
-				printf("index=0x%016" PRIx64
-				    " random=0x%016" PRIx64,
-				    (uint64_t) cop0->reg[COP0_INDEX],
-				    (uint64_t) cop0->reg[COP0_RANDOM]);
-
-			if (m->cpus[i]->cd.mips.cpu_type.isa_level >= 3)
-				printf(" wired=0x%" PRIx64,
-				    (uint64_t) cop0->reg[COP0_WIRED]);
-
-			printf(")\n");
-
-			for (j=0; j<m->cpus[i]->cd.mips.cpu_type.
-			    nr_of_tlb_entries; j++) {
-				if (m->cpus[i]->cd.mips.cpu_type.mmu_model ==
-				    MMU3K)
-					printf(" %02x: hi=0x%08" PRIx32" lo=0x%08"
-					    PRIx32"\n", j,
-					    (uint32_t) cop0->tlbs[j].hi,
-					    (uint32_t) cop0->tlbs[j].lo0);
-				else if (m->cpus[i]->is_32bit)
-					printf(" %02x: hi=0x%08" PRIx32" mask=0x"
-					    "%08" PRIx32" lo0=0x%08" PRIx32
-					    " lo1=0x%08" PRIx32"\n", j,
-					    (uint32_t) cop0->tlbs[j].hi,
-					    (uint32_t) cop0->tlbs[j].mask,
-					    (uint32_t) cop0->tlbs[j].lo0,
-					    (uint32_t) cop0->tlbs[j].lo1);
-				else
-					printf(" %02x: hi=0x%016" PRIx64" mask="
-					    "0x%016" PRIx64" lo0=0x%016" PRIx64
-					    " lo1=0x%016" PRIx64"\n", j,
-					    (uint64_t) cop0->tlbs[j].hi,
-					    (uint64_t) cop0->tlbs[j].mask,
-					    (uint64_t) cop0->tlbs[j].lo0,
-					    (uint64_t) cop0->tlbs[j].lo1);
-			}
-		}
-
-		return;
-	}
-
-	/*  Nicely formatted output:  */
-	for (i=0; i<m->ncpus; i++) {
-		int pageshift = 12;
-		struct mips_coproc *cop0 = m->cpus[i]->cd.mips.coproc[0];
-
-		if (x >= 0 && i != x)
-			continue;
-
-		if (m->cpus[i]->cd.mips.cpu_type.rev == MIPS_R4100)
-			pageshift = 10;
-
-		/*  Print index, random, and wired:  */
-		printf("cpu%i: (", i);
-		switch (m->cpus[i]->cd.mips.cpu_type.isa_level) {
-		case 1:
-		case 2:	printf("index=0x%x random=0x%x",
-			    (int) ((cop0->reg[COP0_INDEX] & R2K3K_INDEX_MASK)
-			    >> R2K3K_INDEX_SHIFT),
-			    (int) ((cop0->reg[COP0_RANDOM] & R2K3K_RANDOM_MASK)
-			    >> R2K3K_RANDOM_SHIFT));
-			break;
-		default:printf("index=0x%x random=0x%x",
-			    (int) (cop0->reg[COP0_INDEX] & INDEX_MASK),
-			    (int) (cop0->reg[COP0_RANDOM] & RANDOM_MASK));
-			printf(" wired=0x%" PRIx64,
-			    (uint64_t) cop0->reg[COP0_WIRED]);
-		}
-
-		printf(")\n");
-
-		for (j=0; j<m->cpus[i]->cd.mips.cpu_type.
-		    nr_of_tlb_entries; j++) {
-			uint64_t hi = cop0->tlbs[j].hi;
-			uint64_t lo0 = cop0->tlbs[j].lo0;
-			uint64_t lo1 = cop0->tlbs[j].lo1;
-			uint64_t mask = cop0->tlbs[j].mask;
-			uint64_t psize;
-
-			mask |= (1 << (pageshift+1)) - 1;
-			/*  here mask = e.g. 0x1fff for 4KB pages  */
-
-			printf(" %02x: ", j);
-
-			switch (m->cpus[i]->cd.mips.cpu_type.mmu_model) {
-			case MMU3K:
-				if (!(lo0 & R2K3K_ENTRYLO_V)) {
-					printf("(invalid)\n");
-					continue;
-				}
-				printf("vaddr=0x%08x ",
-				    (int) (hi&R2K3K_ENTRYHI_VPN_MASK));
-				if (lo0 & R2K3K_ENTRYLO_G)
-					printf("(global), ");
-				else
-					printf("(asid %02x),", (int) ((hi &
-					    R2K3K_ENTRYHI_ASID_MASK)
-					    >> R2K3K_ENTRYHI_ASID_SHIFT));
-				printf(" paddr=0x%08x ",
-				    (int) (lo0&R2K3K_ENTRYLO_PFN_MASK));
-				if (lo0 & R2K3K_ENTRYLO_N)
-					printf("N");
-				if (lo0 & R2K3K_ENTRYLO_D)
-					printf("D");
-				printf("\n");
-				break;
-			default:switch (m->cpus[i]->cd.mips.cpu_type.mmu_model){
-				case MMU32:
-					printf("vaddr=0x%08" PRIx32" ",
-					    (uint32_t) (hi & ~mask));
-					break;
-				default:/*  R4x00, R1x000, MIPS64, etc.  */
-					printf("vaddr=%016" PRIx64" ",
-					    (uint64_t) (hi & ~mask));
-				}
-				if (hi & TLB_G)
-					printf("(global): ");
-				else
-					printf("(asid %02x):",
-					    (int) (hi & ENTRYHI_ASID));
-
-				/*  TODO: Coherency bits  */
-
-				if (!(lo0 & ENTRYLO_V))
-					printf(" p0=(invalid)   ");
-				else {
-					uint64_t paddr = lo0 & ENTRYLO_PFN_MASK;
-					paddr >>= ENTRYLO_PFN_SHIFT;
-					paddr <<= pageshift;
-					paddr &= ~(mask >> 1);
-					printf(" p0=0x%09" PRIx64" ",
-					    (uint64_t) paddr);
-				}
-				printf(lo0 & ENTRYLO_D? "D" : " ");
-
-				if (!(lo1 & ENTRYLO_V))
-					printf(" p1=(invalid)   ");
-				else {
-					uint64_t paddr = lo1 & ENTRYLO_PFN_MASK;
-					paddr >>= ENTRYLO_PFN_SHIFT;
-					paddr <<= pageshift;
-					paddr &= ~(mask >> 1);
-					printf(" p1=0x%09" PRIx64" ",
-					    (uint64_t) paddr);
-				}
-				printf(lo1 & ENTRYLO_D? "D" : " ");
-
-				/*  convert e.g. 0x1fff to 4096  */
-				psize = (mask + 1) >> 1;
-
-				if (psize >= 1024 && psize <= 256*1024)
-					printf(" (%iKB)", (int) (psize >> 10));
-				else if (psize >= 1024*1024 && psize <=
-				    64*1024*1024)
-					printf(" (%iMB)", (int) (psize >> 20));
-				else
-					printf(" (?)");
-
-				printf("\n");
-			}
-		}
-	}
-}
-
-
-/*
- *  mips_cpu_disassemble_instr():
- *
- *  Convert an instruction word into human readable format, for instruction
- *  tracing.
- *
- *  If running is 1, cpu->pc should be the address of the instruction.
- *
- *  If running is 0, things that depend on the runtime environment (eg.
- *  register contents) will not be shown, and addr will be used instead of
- *  cpu->pc for relative addresses.
- *
- *  NOTE 2:  coprocessor instructions are not decoded nicely yet  (TODO)
- */
-int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *originstr,
-	int running, uint64_t dumpaddr)
-{
-	int hi6, special6, regimm5, sub;
-	int rt, rd, rs, sa, imm, copz, cache_op, which_cache, showtag;
-	uint64_t addr, offset;
-	uint32_t instrword;
-	unsigned char instr[4];
-	char *symbol;
-
-	if (running)
-		dumpaddr = cpu->pc;
-
-	if ((dumpaddr & 3) != 0)
-		printf("WARNING: Unaligned address!\n");
-
-	symbol = get_symbol_name(&cpu->machine->symbol_context,
-	    dumpaddr, &offset);
-	if (symbol != NULL && offset==0)
-		debug("<%s>\n", symbol);
-
-	if (cpu->machine->ncpus > 1 && running)
-		debug("cpu%i: ", cpu->cpu_id);
-
-	if (cpu->is_32bit)
-		debug("%08" PRIx32, (uint32_t)dumpaddr);
-	else
-		debug("%016" PRIx64, (uint64_t)dumpaddr);
-
-	memcpy(instr, originstr, sizeof(uint32_t));
-
-	/*
-	 *  The rest of the code is written for little endian,
-	 *  so swap if necessary:
-	 */
-	if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-		int tmp = instr[0]; instr[0] = instr[3];
-		    instr[3] = tmp;
-		tmp = instr[1]; instr[1] = instr[2];
-		    instr[2] = tmp;
-	}
-
-	debug(": %02x%02x%02x%02x",
-	    instr[3], instr[2], instr[1], instr[0]);
-
-	if (running && cpu->delay_slot)
-		debug(" (d)");
-
-	debug("\t");
-
-	/*
-	 *  Decode the instruction:
-	 */
-
-	hi6 = (instr[3] >> 2) & 0x3f;
-
-	switch (hi6) {
-	case HI6_SPECIAL:
-		special6 = instr[0] & 0x3f;
-		switch (special6) {
-		case SPECIAL_SLL:
-		case SPECIAL_SRL:
-		case SPECIAL_SRA:
-		case SPECIAL_DSLL:
-		case SPECIAL_DSRL:
-		case SPECIAL_DSRA:
-		case SPECIAL_DSLL32:
-		case SPECIAL_DSRL32:
-		case SPECIAL_DSRA32:
-			sub = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-			rt = instr[2] & 31;
-			rd = (instr[1] >> 3) & 31;
-			sa = ((instr[1] & 7) << 2) + ((instr[0] >> 6) & 3);
-
-			if (rd == 0 && special6 == SPECIAL_SLL) {
-				if (sa == 0)
-					debug("nop");
-				else if (sa == 1)
-					debug("ssnop");
-				else if (sa == 3)
-					debug("ehb");
-				else
-					debug("nop (weird, sa=%i)", sa);
-				break;
-			}
-
-			switch (sub) {
-			case 0x00:
-				debug("%s\t%s,", special_names[special6],
-				    regnames[rd]);
-				debug("%s,%i", regnames[rt], sa);
-				break;
-			case 0x01:
-				debug("%s\t%s,",
-				    special_rot_names[special6],
-				    regnames[rd]);
-				debug("%s,%i", regnames[rt], sa);
-				break;
-			default:debug("UNIMPLEMENTED special, sub=0x%02x\n",
-				    sub);
-			}
-			break;
-		case SPECIAL_DSRLV:
-		case SPECIAL_DSRAV:
-		case SPECIAL_DSLLV:
-		case SPECIAL_SLLV:
-		case SPECIAL_SRAV:
-		case SPECIAL_SRLV:
-			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-			rt = instr[2] & 31;
-			rd = (instr[1] >> 3) & 31;
-			sub = ((instr[1] & 7) << 2) + ((instr[0] >> 6) & 3);
-
-			switch (sub) {
-			case 0x00:
-				debug("%s\t%s", special_names[special6],
-				    regnames[rd]);
-				debug(",%s", regnames[rt]);
-				debug(",%s", regnames[rs]);
-				break;
-			case 0x01:
-				debug("%s\t%s", special_rot_names[special6],
-				    regnames[rd]);
-				debug(",%s", regnames[rt]);
-				debug(",%s", regnames[rs]);
-				break;
-			default:debug("UNIMPLEMENTED special, sub=0x%02x\n",
-				    sub);
-			}
-			break;
-		case SPECIAL_JR:
-			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-			symbol = get_symbol_name(&cpu->machine->symbol_context,
-			    cpu->cd.mips.gpr[rs], &offset);
-			/*  .hb = hazard barrier hint on MIPS32/64 rev 2  */
-			debug("jr%s\t%s",
-			    (instr[1] & 0x04) ? ".hb" : "",
-			    regnames[rs]);
-			if (running && symbol != NULL)
-				debug("\t<%s>", symbol);
-			break;
-		case SPECIAL_JALR:
-			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-			rd = (instr[1] >> 3) & 31;
-			symbol = get_symbol_name(&cpu->machine->symbol_context,
-			    cpu->cd.mips.gpr[rs], &offset);
-			/*  .hb = hazard barrier hint on MIPS32/64 rev 2  */
-			debug("jalr%s\t%s",
-			    (instr[1] & 0x04) ? ".hb" : "",
-			    regnames[rd]);
-			debug(",%s", regnames[rs]);
-			if (running && symbol != NULL)
-				debug("\t<%s>", symbol);
-			break;
-		case SPECIAL_MFHI:
-		case SPECIAL_MFLO:
-			rd = (instr[1] >> 3) & 31;
-			debug("%s\t%s", special_names[special6], regnames[rd]);
-			break;
-		case SPECIAL_MTLO:
-		case SPECIAL_MTHI:
-			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-			debug("%s\t%s", special_names[special6], regnames[rs]);
-			break;
-		case SPECIAL_ADD:
-		case SPECIAL_ADDU:
-		case SPECIAL_SUB:
-		case SPECIAL_SUBU:
-		case SPECIAL_AND:
-		case SPECIAL_OR:
-		case SPECIAL_XOR:
-		case SPECIAL_NOR:
-		case SPECIAL_SLT:
-		case SPECIAL_SLTU: 
-		case SPECIAL_DADD:
-		case SPECIAL_DADDU:
-		case SPECIAL_DSUB:
-		case SPECIAL_DSUBU:
-		case SPECIAL_MOVZ:
-		case SPECIAL_MOVN:
-			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-			rt = instr[2] & 31;
-			rd = (instr[1] >> 3) & 31;
-			if (cpu->is_32bit && (special6 == SPECIAL_ADDU ||
-			    special6 == SPECIAL_SUBU) && rt == 0) {
-				/*  Special case 1: addu/subu with
-				    rt = the zero register ==> move  */
-				debug("move\t%s", regnames[rd]);
-				debug(",%s", regnames[rs]);
-			} else if (special6 == SPECIAL_ADDU && cpu->is_32bit
-			    && rs == 0) {
-				/*  Special case 2: addu with
-				    rs = the zero register ==> move  */
-				debug("move\t%s", regnames[rd]);
-				debug(",%s", regnames[rt]);
-			} else {
-				debug("%s\t%s", special_names[special6],
-				    regnames[rd]);
-				debug(",%s", regnames[rs]);
-				debug(",%s", regnames[rt]);
-			}
-			break;
-		case SPECIAL_MULT:
-		case SPECIAL_MULTU:
-		case SPECIAL_DMULT:
-		case SPECIAL_DMULTU:
-		case SPECIAL_DIV:
-		case SPECIAL_DIVU:
-		case SPECIAL_DDIV:
-		case SPECIAL_DDIVU:
-			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-			rt = instr[2] & 31;
-			rd = (instr[1] >> 3) & 31;
-			debug("%s\t", special_names[special6]);
-			if (rd != 0) {
-				if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
-					if (special6 == SPECIAL_MULT ||
-					    special6 == SPECIAL_MULTU)
-						debug("%s,", regnames[rd]);
-					else
-						debug("WEIRD_R5900_RD,");
-				} else {
-					debug("WEIRD_RD_NONZERO,");
-				}
-			}
-			debug("%s", regnames[rs]);
-			debug(",%s", regnames[rt]);
-			break;
-		case SPECIAL_TGE:
-		case SPECIAL_TGEU:
-		case SPECIAL_TLT:
-		case SPECIAL_TLTU:
-		case SPECIAL_TEQ:
-		case SPECIAL_TNE:
-			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-			rt = instr[2] & 31;
-			rd = ((instr[1] << 8) + instr[0]) >> 6;	// code, not rd
-			debug("%s\t", special_names[special6]);
-			debug("%s", regnames[rs]);
-			debug(",%s", regnames[rt]);
-			if (rd != 0)
-				debug(",0x%x", rd);
-			break;
-		case SPECIAL_SYNC:
-			imm = ((instr[1] & 7) << 2) + (instr[0] >> 6);
-			debug("sync\t0x%02x", imm);
-			break;
-		case SPECIAL_SYSCALL:
-			imm = (((instr[3] << 24) + (instr[2] << 16) +
-			    (instr[1] << 8) + instr[0]) >> 6) & 0xfffff;
-			if (imm != 0)
-				debug("syscall\t0x%05x", imm);
-			else
-				debug("syscall");
-			break;
-		case SPECIAL_BREAK:
-			imm = (((instr[3] << 24) + (instr[2] << 16) +
-			    (instr[1] << 8) + instr[0]) >> 6) & 0xfffff;
-			if (imm != 0)
-				debug("break\t0x%05x", imm);
-			else
-				debug("break");
-			break;
-		case SPECIAL_MFSA:
-			if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
-				rd = (instr[1] >> 3) & 31;
-				debug("mfsa\t%s", regnames[rd]);
-			} else {
-				debug("unimplemented special 0x28");
-			}
-			break;
-		case SPECIAL_MTSA:
-			if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
-				rs = ((instr[3] & 3) << 3) +
-				    ((instr[2] >> 5) & 7);
-				debug("mtsa\t%s", regnames[rs]);
-			} else {
-				debug("unimplemented special 0x29");
-			}
-			break;
-		default:
-			debug("%s\t= UNIMPLEMENTED", special_names[special6]);
-		}
-		break;
-	case HI6_BEQ:
-	case HI6_BEQL:
-	case HI6_BNE:
-	case HI6_BNEL:
-	case HI6_BGTZ:
-	case HI6_BGTZL:
-	case HI6_BLEZ:
-	case HI6_BLEZL:
-		rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-		rt = instr[2] & 31;
-		imm = (instr[1] << 8) + instr[0];
-		if (imm >= 32768)
-			imm -= 65536;
-		addr = (dumpaddr + 4) + (imm << 2);
-
-		if (hi6 == HI6_BEQ && rt == MIPS_GPR_ZERO &&
-		    rs == MIPS_GPR_ZERO)
-			debug("b\t");
-		else {
-			debug("%s\t", hi6_names[hi6]);
-			switch (hi6) {
-			case HI6_BEQ:
-			case HI6_BEQL:
-			case HI6_BNE:
-			case HI6_BNEL:
-				debug("%s,", regnames[rt]);
-			}
-			debug("%s,", regnames[rs]);
-		}
-
-		if (cpu->is_32bit)
-			debug("0x%08" PRIx32, (uint32_t)addr);
-		else
-			debug("0x%016" PRIx64, (uint64_t)addr);
-
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    addr, &offset);
-		if (symbol != NULL && offset != addr)
-			debug("\t<%s>", symbol);
-		break;
-	case HI6_ADDI:
-	case HI6_ADDIU:
-	case HI6_DADDI:
-	case HI6_DADDIU:
-	case HI6_SLTI:
-	case HI6_SLTIU:
-	case HI6_ANDI:
-	case HI6_ORI:
-	case HI6_XORI:
-		rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-		rt = instr[2] & 31;
-		imm = (instr[1] << 8) + instr[0];
-		if (imm >= 32768)
-			imm -= 65536;
-		debug("%s\t%s,", hi6_names[hi6], regnames[rt]);
-		debug("%s,", regnames[rs]);
-		if (hi6 == HI6_ANDI || hi6 == HI6_ORI || hi6 == HI6_XORI)
-			debug("0x%04x", imm & 0xffff);
-		else
-			debug("%i", imm);
-		break;
-	case HI6_LUI:
-		rt = instr[2] & 31;
-		imm = (instr[1] << 8) + instr[0];
-		debug("lui\t%s,0x%x", regnames[rt], imm);
-		break;
-	case HI6_LB:
-	case HI6_LBU:
-	case HI6_LH:
-	case HI6_LHU:
-	case HI6_LW:
-	case HI6_LWU:
-	case HI6_LD:
-	case HI6_LQ_MDMX:
-	case HI6_LWC1:
-	case HI6_LWC2:
-	case HI6_LWC3:
-	case HI6_LDC1:
-	case HI6_LDC2:
-	case HI6_LL:
-	case HI6_LLD:
-	case HI6_SB:
-	case HI6_SH:
-	case HI6_SW:
-	case HI6_SD:
-	case HI6_SQ_SPECIAL3:
-	case HI6_SC:
-	case HI6_SCD:
-	case HI6_SWC1:
-	case HI6_SWC2:
-	case HI6_SWC3:
-	case HI6_SDC1:
-	case HI6_SDC2:
-	case HI6_LWL:   
-	case HI6_LWR:
-	case HI6_LDL:
-	case HI6_LDR:
-	case HI6_SWL:
-	case HI6_SWR:
-	case HI6_SDL:
-	case HI6_SDR:
-		if (hi6 == HI6_LQ_MDMX &&
-		    cpu->cd.mips.cpu_type.rev != MIPS_R5900) {
-			debug("mdmx\t(UNIMPLEMENTED)");
-			break;
-		}
-		if (hi6 == HI6_SQ_SPECIAL3 &&
-		    cpu->cd.mips.cpu_type.rev != MIPS_R5900) {
-			int msbd, lsb, sub10;
-			special6 = instr[0] & 0x3f;
-			rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-			rt = instr[2] & 31;
-			rd = msbd = (instr[1] >> 3) & 31;
-			lsb = ((instr[1] & 7) << 2) | (instr[0] >> 6);
-			sub10 = (rs << 5) | lsb;
-
-			switch (special6) {
-
-			case SPECIAL3_EXT:
-			case SPECIAL3_DEXT:
-			case SPECIAL3_DEXTM:
-			case SPECIAL3_DEXTU:
-				debug("%s", special3_names[special6]);
-				if (special6 == SPECIAL3_DEXTM)
-					msbd += 32;
-				if (special6 == SPECIAL3_DEXTU)
-					lsb += 32;
-				debug("\t%s", regnames[rt]);
-				debug(",%s", regnames[rs]);
-				debug(",%i,%i", lsb, msbd + 1);
-				break;
-
-			case SPECIAL3_INS:
-			case SPECIAL3_DINS:
-			case SPECIAL3_DINSM:
-			case SPECIAL3_DINSU:
-				debug("%s", special3_names[special6]);
-				if (special6 == SPECIAL3_DINSM)
-					msbd += 32;
-				if (special6 == SPECIAL3_DINSU) {
-					lsb += 32;
-					msbd += 32;
-				}
-				msbd -= lsb;
-				debug("\t%s", regnames[rt]);
-				debug(",%s", regnames[rs]);
-				debug(",%i,%i", lsb, msbd + 1);
-				break;
-
-			case SPECIAL3_BSHFL:
-				switch (sub10) {
-				case BSHFL_WSBH:
-				case BSHFL_SEB:
-				case BSHFL_SEH:
-					switch (sub10) {
-					case BSHFL_WSBH: debug("wsbh"); break;
-					case BSHFL_SEB:  debug("seb"); break;
-					case BSHFL_SEH:  debug("seh"); break;
-					}
-					debug("\t%s", regnames[rd]);
-					debug(",%s", regnames[rt]);
-					break;
-				default:debug("%s", special3_names[special6]);
-					debug("\t(UNIMPLEMENTED)");
-				}
-				break;
-
-			case SPECIAL3_DBSHFL:
-				switch (sub10) {
-				case BSHFL_DSBH:
-				case BSHFL_DSHD:
-					switch (sub10) {
-					case BSHFL_DSBH: debug("dsbh"); break;
-					case BSHFL_DSHD: debug("dshd"); break;
-					}
-					debug("\t%s", regnames[rd]);
-					debug(",%s", regnames[rt]);
-					break;
-				default:debug("%s", special3_names[special6]);
-					debug("\t(UNIMPLEMENTED)");
-				}
-				break;
-
-			case SPECIAL3_RDHWR:
-				debug("%s", special3_names[special6]);
-				debug("\t%s", regnames[rt]);
-				debug(",hwr%i", rd);
-				break;
-
-			default:debug("%s", special3_names[special6]);
-				debug("\t(UNIMPLEMENTED)");
-			}
-			break;
-		}
-
-		rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-		rt = instr[2] & 31;
-		imm = (instr[1] << 8) + instr[0];
-		if (imm >= 32768)
-			imm -= 65536;
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    cpu->cd.mips.gpr[rs] + imm, &offset);
-
-		/*  LWC3 is PREF in the newer ISA levels:  */
-		/*  TODO: Which ISAs? IV? V? 32? 64?  */
-		if (cpu->cd.mips.cpu_type.isa_level >= 4 && hi6 == HI6_LWC3) {
-			debug("pref\t0x%x,%i(%s)",
-			    rt, imm, regnames[rs]);
-
-			if (running) {
-				debug("\t[0x%016" PRIx64" = %s]",
-				    (uint64_t)(cpu->cd.mips.gpr[rs] + imm));
-				if (symbol != NULL)
-					debug(" = %s", symbol);
-				debug("]");
-			}
-			goto disasm_ret;
-		}
-
-		debug("%s\t", hi6_names[hi6]);
-
-		if (hi6 == HI6_SWC1 || hi6 == HI6_SWC2 || hi6 == HI6_SWC3 ||
-		    hi6 == HI6_SDC1 || hi6 == HI6_SDC2 ||
-		    hi6 == HI6_LWC1 || hi6 == HI6_LWC2 || hi6 == HI6_LWC3 ||
-		    hi6 == HI6_LDC1 || hi6 == HI6_LDC2)
-			debug("r%i", rt);
-		else
-			debug("%s", regnames[rt]);
-
-		debug(",%i(%s)", imm, regnames[rs]);
-
-		if (running) {
-			debug("\t[");
-
-			if (cpu->is_32bit)
-				debug("0x%08" PRIx32,
-				    (uint32_t) (cpu->cd.mips.gpr[rs] + imm));
-			else
-				debug("0x%016" PRIx64,
-				    (uint64_t) (cpu->cd.mips.gpr[rs] + imm));
-
-			if (symbol != NULL)
-				debug(" = %s", symbol);
-
-			/*  TODO: In some cases, it is possible to peek into
-			    memory, and display that data here, like for the
-			    other emulation modes.  */
-
-			debug("]");
-		}
-		break;
-
-	case HI6_J:
-	case HI6_JAL:
-		imm = (((instr[3] & 3) << 24) + (instr[2] << 16) +
-		    (instr[1] << 8) + instr[0]) << 2;
-		addr = (dumpaddr + 4) & ~((1 << 28) - 1);
-		addr |= imm;
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    addr, &offset);
-		debug("%s\t0x", hi6_names[hi6]);
-		if (cpu->is_32bit)
-			debug("%08" PRIx32, (uint32_t) addr);
-		else
-			debug("%016" PRIx64, (uint64_t) addr);
-		if (symbol != NULL)
-			debug("\t<%s>", symbol);
-		break;
-
-	case HI6_COP0:
-	case HI6_COP1:
-	case HI6_COP2:
-	case HI6_COP3:
-		imm = (instr[3] << 24) + (instr[2] << 16) +
-		     (instr[1] << 8) + instr[0];
-		imm &= ((1 << 26) - 1);
-
-		/*  Call coproc_function(), but ONLY disassembly, no exec:  */
-		coproc_function(cpu, cpu->cd.mips.coproc[hi6 - HI6_COP0],
-		    hi6 - HI6_COP0, imm, 1, running);
-		return sizeof(instrword);
-
-	case HI6_CACHE:
-		rt   = ((instr[3] & 3) << 3) + (instr[2] >> 5); /*  base  */
-		copz = instr[2] & 31;
-		imm  = (instr[1] << 8) + instr[0];
-		cache_op    = copz >> 2;
-		which_cache = copz & 3;
-		showtag = 0;
-		debug("cache\t0x%02x,0x%04x(%s)", copz, imm, regnames[rt]);
-		if (which_cache==0)	debug("  [ primary I-cache");
-		if (which_cache==1)	debug("  [ primary D-cache");
-		if (which_cache==2)	debug("  [ secondary I-cache");
-		if (which_cache==3)	debug("  [ secondary D-cache");
-		debug(", ");
-		if (cache_op==0)	debug("index invalidate");
-		if (cache_op==1)	debug("index load tag");
-		if (cache_op==2)	debug("index store tag"), showtag=1;
-		if (cache_op==3)	debug("create dirty exclusive");
-		if (cache_op==4)	debug("hit invalidate");
-		if (cache_op==5)     debug("fill OR hit writeback invalidate");
-		if (cache_op==6)	debug("hit writeback");
-		if (cache_op==7)	debug("hit set virtual");
-		if (running)
-			debug(", addr 0x%016" PRIx64,
-			    (uint64_t)(cpu->cd.mips.gpr[rt] + imm));
-		if (showtag)
-		debug(", taghi=%08lx lo=%08lx",
-		    (long)cpu->cd.mips.coproc[0]->reg[COP0_TAGDATA_HI],
-		    (long)cpu->cd.mips.coproc[0]->reg[COP0_TAGDATA_LO]);
-		debug(" ]");
-		break;
-
-	case HI6_SPECIAL2:
-		special6 = instr[0] & 0x3f;
-		instrword = (instr[3] << 24) + (instr[2] << 16) +
-		    (instr[1] << 8) + instr[0];
-		rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-		rt = instr[2] & 31;
-		rd = (instr[1] >> 3) & 31;
-
-		if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
-			int c790mmifunc = (instrword >> 6) & 0x1f;
-			if (special6 != MMI_MMI0 && special6 != MMI_MMI1 &&
-			    special6 != MMI_MMI2 && special6 != MMI_MMI3)
-				debug("%s\t", mmi_names[special6]);
-
-			switch (special6) {
-
-			case MMI_MADD:
-			case MMI_MADDU:
-				if (rd != MIPS_GPR_ZERO) {
-					debug("%s,", regnames[rd]);
-				}
-				debug("%s,%s", regnames[rs], regnames[rt]);
-				break;
-
-			case MMI_MMI0:
-				debug("%s\t", mmi0_names[c790mmifunc]);
-				switch (c790mmifunc) {
-
-				case MMI0_PEXTLB:
-				case MMI0_PEXTLH:
-				case MMI0_PEXTLW:
-				case MMI0_PMAXH:
-				case MMI0_PMAXW:
-				case MMI0_PPACB:
-				case MMI0_PPACH:
-				case MMI0_PPACW:
-					debug("%s,%s,%s", regnames[rd],
-					    regnames[rs], regnames[rt]);
-					break;
-
-				default:debug("(UNIMPLEMENTED)");
-				}
-				break;
-
-			case MMI_MMI1:
-				debug("%s\t", mmi1_names[c790mmifunc]);
-				switch (c790mmifunc) {
-
-				case MMI1_PEXTUB:
-				case MMI1_PEXTUH:
-				case MMI1_PEXTUW:
-				case MMI1_PMINH:
-				case MMI1_PMINW:
-					debug("%s,%s,%s", regnames[rd],
-					    regnames[rs], regnames[rt]);
-					break;
-
-				default:debug("(UNIMPLEMENTED)");
-				}
-				break;
-
-			case MMI_MMI2:
-				debug("%s\t", mmi2_names[c790mmifunc]);
-				switch (c790mmifunc) {
-
-				case MMI2_PMFHI:
-				case MMI2_PMFLO:
-					debug("%s", regnames[rd]);
-					break;
-
-				case MMI2_PHMADH:
-				case MMI2_PHMSBH:
-				case MMI2_PINTH:
-				case MMI2_PMADDH:
-				case MMI2_PMADDW:
-				case MMI2_PMSUBH:
-				case MMI2_PMSUBW:
-				case MMI2_PMULTH:
-				case MMI2_PMULTW:
-				case MMI2_PSLLVW:
-					debug("%s,%s,%s", regnames[rd],
-					    regnames[rs], regnames[rt]);
-					break;
-
-				default:debug("(UNIMPLEMENTED)");
-				}
-				break;
-
-			case MMI_MMI3:
-				debug("%s\t", mmi3_names[c790mmifunc]);
-				switch (c790mmifunc) {
-
-				case MMI3_PMTHI:
-				case MMI3_PMTLO:
-					debug("%s", regnames[rs]);
-					break;
-
-				case MMI3_PINTEH:
-				case MMI3_PMADDUW:
-				case MMI3_PMULTUW:
-				case MMI3_PNOR:
-				case MMI3_POR:
-				case MMI3_PSRAVW:
-					debug("%s,%s,%s", regnames[rd],
-					    regnames[rs], regnames[rt]);
-					break;
-
-				default:debug("(UNIMPLEMENTED)");
-				}
-				break;
-
-			default:debug("(UNIMPLEMENTED)");
-			}
-			break;
-		}
-
-		/*  SPECIAL2:  */
-		debug("%s\t", special2_names[special6]);
-
-		switch (special6) {
-
-		case SPECIAL2_MADD:
-		case SPECIAL2_MADDU:
-		case SPECIAL2_MSUB:
-		case SPECIAL2_MSUBU:
-			if (rd != MIPS_GPR_ZERO) {
-				debug("WEIRD_NONZERO_RD(%s),",
-				    regnames[rd]);
-			}
-			debug("%s,%s", regnames[rs], regnames[rt]);
-			break;
-
-		case SPECIAL2_MUL:
-			/*  Apparently used both on R5900 and MIPS32:  */
-			debug("%s,%s,%s", regnames[rd],
-			    regnames[rs], regnames[rt]);
-			break;
-
-		case SPECIAL2_CLZ:
-		case SPECIAL2_CLO:
-		case SPECIAL2_DCLZ:
-		case SPECIAL2_DCLO:
-			debug("%s,%s", regnames[rd], regnames[rs]);
-			break;
-
-		default:
-			debug("(UNIMPLEMENTED)");
-		}
-		break;
-
-	case HI6_REGIMM:
-		regimm5 = instr[2] & 0x1f;
-		rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
-		imm = (instr[1] << 8) + instr[0];
-		if (imm >= 32768)               
-			imm -= 65536;
-
-		switch (regimm5) {
-
-		case REGIMM_BLTZ:
-		case REGIMM_BGEZ:
-		case REGIMM_BLTZL:
-		case REGIMM_BGEZL:
-		case REGIMM_BLTZAL:
-		case REGIMM_BLTZALL:
-		case REGIMM_BGEZAL:
-		case REGIMM_BGEZALL:
-			debug("%s\t%s,", regimm_names[regimm5], regnames[rs]);
-
-			addr = (dumpaddr + 4) + (imm << 2);
-
-			if (cpu->is_32bit)
-				debug("0x%08" PRIx32, (uint32_t) addr);
-			else
-				debug("0x%016" PRIx64, (uint64_t) addr);
-			break;
-
-		case REGIMM_TGEI:
-		case REGIMM_TGEIU:
-		case REGIMM_TLTI:
-		case REGIMM_TLTIU:
-		case REGIMM_TEQI:
-		case REGIMM_TNEI:
-			debug("%s\t%s,", regimm_names[regimm5], regnames[rs]);
-
-			if (cpu->is_32bit)
-				debug("0x%" PRIx32, (uint32_t) imm);
-			else
-				debug("0x%" PRIx64, (uint64_t) imm);
-			break;
-
-		case REGIMM_SYNCI:
-			debug("%s\t%i(%s)", regimm_names[regimm5],
-			    imm, regnames[rs]);
-			break;
-
-		default:
-			debug("unimplemented regimm5 = 0x%02x", regimm5);
-		}
-		break;
-	default:
-		debug("unimplemented hi6 = 0x%02x", hi6);
-	}
-
-disasm_ret:
-	debug("\n");
-	return sizeof(instrword);
-}
-
-
-/*
- *  mips_cpu_register_dump():
- *
- *  Dump cpu registers in a relatively readable format.
- *
- *  gprs: set to non-zero to dump GPRs and hi/lo/pc
- *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
- */
-void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
-{
-	int coprocnr, i, bits32;
-	uint64_t offset;
-	char *symbol;
-	int bits128 = cpu->cd.mips.cpu_type.rev == MIPS_R5900;
-
-	bits32 = cpu->is_32bit;
-
-	if (gprs) {
-		/*  Special registers (pc, hi/lo) first:  */
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    cpu->pc, &offset);
-
-		if (bits32)
-			debug("cpu%i:  pc = %08" PRIx32,
-			    cpu->cpu_id, (uint32_t) cpu->pc);
-		else if (bits128)
-			debug("cpu%i:  pc=%016" PRIx64,
-			    cpu->cpu_id, (uint64_t) cpu->pc);
-		else
-			debug("cpu%i:    pc = 0x%016" PRIx64,
-			    cpu->cpu_id, (uint64_t) cpu->pc);
-
-		debug("    <%s>\n", symbol != NULL? symbol :
-		    " no symbol ");
-
-		if (bits32)
-			debug("cpu%i:  hi = %08" PRIx32"  lo = %08" PRIx32"\n",
-			    cpu->cpu_id, (uint32_t) cpu->cd.mips.hi,
-			    (uint32_t) cpu->cd.mips.lo);
-		else if (bits128) {
-			debug("cpu%i:  hi=%016" PRIx64"%016" PRIx64"  lo="
-			    "%016" PRIx64"%016" PRIx64"\n", cpu->cpu_id,
-			    cpu->cd.mips.hi1, cpu->cd.mips.hi,
-			    cpu->cd.mips.lo1, cpu->cd.mips.lo);
-		} else {
-			debug("cpu%i:    hi = 0x%016" PRIx64"    lo = 0x%016"
-			    PRIx64"\n", cpu->cpu_id,
-			    (uint64_t) cpu->cd.mips.hi,
-			    (uint64_t) cpu->cd.mips.lo);
-		}
-
-		/*  General registers:  */
-		if (bits128) {
-			/*  128-bit:  */
-			for (i=0; i<32; i++) {
-				int r = (i >> 1) + ((i & 1) << 4);
-				if ((i & 1) == 0)
-					debug("cpu%i:", cpu->cpu_id);
-				if (r == MIPS_GPR_ZERO)
-					debug("                           "
-					    "          ");
-				else
-					debug(" %3s=%016" PRIx64"%016" PRIx64,
-					    regnames[r], (uint64_t)
-					    cpu->cd.mips.gpr_quadhi[r],
-					    (uint64_t)cpu->cd.mips.gpr[r]);
-				if ((i & 1) == 1)
-					debug("\n");
-			}
-		} else if (bits32) {
-			/*  32-bit:  */
-			for (i=0; i<32; i++) {
-				if ((i & 3) == 0)
-					debug("cpu%i:", cpu->cpu_id);
-				if (i == MIPS_GPR_ZERO)
-					debug("               ");
-				else
-					debug(" %3s = %08" PRIx32, regnames[i],
-					    (uint32_t)cpu->cd.mips.gpr[i]);
-				if ((i & 3) == 3)
-					debug("\n");
-			}
-		} else {
-			/*  64-bit:  */
-			for (i=0; i<32; i++) {
-				int r = (i >> 1) + ((i & 1) << 4);
-				if ((i & 1) == 0)
-					debug("cpu%i:", cpu->cpu_id);
-				if (r == MIPS_GPR_ZERO)
-					debug("                           ");
-				else
-					debug("   %3s = 0x%016" PRIx64,
-					    regnames[r],
-					    (uint64_t)cpu->cd.mips.gpr[r]);
-				if ((i & 1) == 1)
-					debug("\n");
-			}
-		}
-	}
-
-	for (coprocnr=0; coprocnr<4; coprocnr++) {
-		int nm1 = 1;
-
-		if (bits32)
-			nm1 = 3;
-
-		if (!(coprocs & (1<<coprocnr)))
-			continue;
-		if (cpu->cd.mips.coproc[coprocnr] == NULL) {
-			debug("cpu%i: no coprocessor %i\n",
-			    cpu->cpu_id, coprocnr);
-			continue;
-		}
-
-		/*  Coprocessor registers:  */
-		for (i=0; i<32; i++) {
-			/*  32-bit:  */
-			if ((i & nm1) == 0)
-				debug("cpu%i:", cpu->cpu_id);
-
-			if (coprocnr == 0)
-				debug(" %8s", cop0_names[i]);
-			else
-				debug(" c%i,%02i", coprocnr, i);
-
-			if (bits32)
-				debug("=%08x", (int)cpu->cd.mips.
-				    coproc[coprocnr]->reg[i]);
-			else {
-				if (coprocnr == 0 && (i == COP0_COUNT
-				    || i == COP0_COMPARE || i == COP0_INDEX
-				    || i == COP0_RANDOM || i == COP0_WIRED))
-					debug(" =         0x%08x",
-					    (int) cpu->cd.mips.coproc[
-					    coprocnr]->reg[i]);
-				else
-					debug(" = 0x%016" PRIx64, (uint64_t)
-					    cpu->cd.mips.coproc[
-					    coprocnr]->reg[i]);
-			}
-
-			if ((i & nm1) == nm1)
-				debug("\n");
-
-			/*  Skip the last 16 cop0 registers on R3000 etc.  */
-			if (coprocnr == 0 && cpu->cd.mips.cpu_type.isa_level < 3
-			    && i == 15)
-				i = 31;
-		}
-
-		if (coprocnr == 0 && cpu->cd.mips.cpu_type.isa_level >= 32) {
-			debug("cpu%i: ", cpu->cpu_id);
-			debug("config_select1 = 0x");
-			if (cpu->is_32bit)
-				debug("%08" PRIx32,
-				    (uint32_t)cpu->cd.mips.cop0_config_select1);
-			else
-				debug("%016" PRIx64,
-				    (uint64_t)cpu->cd.mips.cop0_config_select1);
-			debug("\n");
-		}
-
-		/*  Floating point control registers:  */
-		if (coprocnr == 1) {
-			for (i=0; i<32; i++)
-				switch (i) {
-				case MIPS_FPU_FCIR:
-					printf("cpu%i: fcr0  (fcir) = 0x%08x\n",
-					    cpu->cpu_id, (int)cpu->cd.mips.
-					    coproc[coprocnr]->fcr[i]);
-					break;
-				case MIPS_FPU_FCCR:
-					printf("cpu%i: fcr25 (fccr) = 0x%08x\n",
-					    cpu->cpu_id, (int)cpu->cd.mips.
-					    coproc[coprocnr]->fcr[i]);
-					break;
-				case MIPS_FPU_FCSR:
-					printf("cpu%i: fcr31 (fcsr) = 0x%08x\n",
-					    cpu->cpu_id, (int)cpu->cd.mips.
-					    coproc[coprocnr]->fcr[i]);
-					break;
-				}
-		}
-	}
-
-	if (cpu->cd.mips.rmw) {
-		printf("cpu%i: Read-Modify-Write in progress, address "
-		    "0x%016" PRIx64"\n", cpu->cpu_id, cpu->cd.mips.rmw_addr);
-	}
-}
-
-
-/*
- *  mips_cpu_interrupt_assert(), mips_cpu_interrupt_deassert():
- *
- *  Assert or deassert a MIPS CPU interrupt by masking in or out bits
- *  in the CAUSE register of coprocessor 0.
- */
-void mips_cpu_interrupt_assert(struct interrupt *interrupt)
-{
-	struct cpu *cpu = (struct cpu *) interrupt->extra;
-	cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] |= interrupt->line;
-}
-void mips_cpu_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct cpu *cpu = (struct cpu *) interrupt->extra;
-	cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] &= ~interrupt->line;
-}
-
-
-/*
- *  mips_cpu_exception():
- *
- *  Cause an exception in a CPU.  This sets a couple of coprocessor 0
- *  registers, and the program counter.
- *
- *	exccode		the exception code
- *	tlb		set to non-zero if the exception handler at
- *			0x80000000 should be used. (normal = 0x80000180)
- *	vaddr		virtual address (for some exceptions)
- *	coproc_nr	coprocessor number (for some exceptions)
- *	vaddr_vpn2	vpn2 (for some exceptions)
- *	vaddr_asid	asid (for some exceptions)
- *	x_64		non-zero for 64-bit mode for R4000-style tlb misses
- */
-void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,
-	int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64)
-{
-	uint64_t base;
-	uint64_t *reg = &cpu->cd.mips.coproc[0]->reg[0];
-	int exc_model = cpu->cd.mips.cpu_type.exc_model;
-
-	if (cpu->is_halted) {
-		/*
-		 *  If the exception occurred on a 'wait' instruction, then let
-		 *  the instruction following the wait instruction be the one
-		 *  we continue at when the interrupt service routine returns.
-		 */
-		cpu->is_halted = 0;
-		cpu->pc += sizeof(uint32_t);
-	}
-
-	if (!quiet_mode) {
-		uint64_t offset;
-		int x;
-		char *symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    cpu->pc, &offset);
-
-		debug("[ ");
-		if (cpu->machine->ncpus > 1)
-			debug("cpu%i: ", cpu->cpu_id);
-
-		debug("exception %s%s",
-		    exception_names[exccode], tlb? " <tlb>" : "");
-
-		switch (exccode) {
-
-		case EXCEPTION_INT:
-			debug(" cause_im=0x%02x", (int)
-			    ((reg[COP0_CAUSE] & CAUSE_IP_MASK)
-			    >> CAUSE_IP_SHIFT));
-			break;
-
-		case EXCEPTION_SYS:
-			debug(" v0=%i", (int)cpu->cd.mips.gpr[MIPS_GPR_V0]);
-			for (x=0; x<4; x++) {
-				int64_t d = cpu->cd.mips.gpr[MIPS_GPR_A0 + x];
-				char strbuf[30];
-
-				if (d > -256 && d < 256) {
-					debug(" a%i=%i", x, (int)d);
-				} else if (memory_points_to_string(cpu,
-				    cpu->mem, d, 1)) {
-					debug(" a%i=\"%s\"", x,
-					    memory_conv_to_string(cpu, cpu->mem,
-					    d, strbuf, sizeof(strbuf)));
-				} else {
-					if (cpu->is_32bit)
-						debug(" a%i=0x%" PRIx32, x,
-						    (uint32_t)d);
-					else
-						debug(" a%i=0x%" PRIx64, x,
-						    (uint64_t)d);
-				}
-			}
-			break;
-
-		case EXCEPTION_CPU:
-			debug(" coproc_nr=%i", coproc_nr);
-			break;
-
-		default:
-			if (cpu->is_32bit)
-				debug(" vaddr=0x%08x", (int)vaddr);
-			else
-				debug(" vaddr=0x%016" PRIx64, (uint64_t)vaddr);
-		}
-
-		if (cpu->is_32bit)
-			debug(" pc=0x%08" PRIx32" ", (uint32_t)cpu->pc);
-		else
-			debug(" pc=0x%016" PRIx64" ", (uint64_t)cpu->pc);
-
-		if (symbol != NULL)
-			debug("<%s> ]\n", symbol);
-		else
-			debug("]\n");
-	}
-
-	if (tlb && vaddr < 0x1000) {
-		uint64_t offset;
-		char *symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    cpu->pc, &offset);
-		fatal("[ ");
-		if (cpu->machine->ncpus > 1)
-			fatal("cpu%i: ", cpu->cpu_id);
-		fatal("warning: LOW reference: vaddr=");
-		if (cpu->is_32bit)
-			fatal("0x%08" PRIx32, (uint32_t) vaddr);
-		else
-			fatal("0x%016" PRIx64, (uint64_t) vaddr);
-		fatal(", exception %s, pc=", exception_names[exccode]);
-		if (cpu->is_32bit)
-			fatal("0x%08" PRIx32, (uint32_t) cpu->pc);
-		else
-			fatal("0x%016" PRIx64, (uint64_t)cpu->pc);
-		fatal(" <%s> ]\n", symbol? symbol : "(no symbol)");
-	}
-
-	/*  Clear the exception code bits of the cause register...  */
-	if (exc_model == EXC3K)
-		reg[COP0_CAUSE] &= ~R2K3K_CAUSE_EXCCODE_MASK;
-	else
-		reg[COP0_CAUSE] &= ~CAUSE_EXCCODE_MASK;
-
-	/*  ... and OR in the exception code:  */
-	reg[COP0_CAUSE] |= (exccode << CAUSE_EXCCODE_SHIFT);
-
-	/*  Always set CE (according to the R5000 manual):  */
-	reg[COP0_CAUSE] &= ~CAUSE_CE_MASK;
-	reg[COP0_CAUSE] |= (coproc_nr << CAUSE_CE_SHIFT);
-
-	if (tlb || (exccode >= EXCEPTION_MOD && exccode <= EXCEPTION_ADES) ||
-	    exccode == EXCEPTION_VCEI || exccode == EXCEPTION_VCED) {
-		reg[COP0_BADVADDR] = vaddr;
-		if (cpu->is_32bit)
-			reg[COP0_BADVADDR] = (int32_t)reg[COP0_BADVADDR];
-
-		if (exc_model == EXC3K) {
-			reg[COP0_CONTEXT] &= ~R2K3K_CONTEXT_BADVPN_MASK;
-			reg[COP0_CONTEXT] |= ((vaddr_vpn2 <<
-			    R2K3K_CONTEXT_BADVPN_SHIFT) &
-			    R2K3K_CONTEXT_BADVPN_MASK);
-
-			reg[COP0_ENTRYHI] = (vaddr & R2K3K_ENTRYHI_VPN_MASK)
-			    | (vaddr_asid << R2K3K_ENTRYHI_ASID_SHIFT);
-
-			/*  Sign-extend:  */
-			reg[COP0_CONTEXT] = (int64_t)(int32_t)reg[COP0_CONTEXT];
-			reg[COP0_ENTRYHI] = (int64_t)(int32_t)reg[COP0_ENTRYHI];
-		} else {
-			if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
-				reg[COP0_CONTEXT] &=
-				    ~CONTEXT_BADVPN2_MASK_R4100;
-				reg[COP0_CONTEXT] |= ((vaddr_vpn2 <<
-				    CONTEXT_BADVPN2_SHIFT) &
-				    CONTEXT_BADVPN2_MASK_R4100);
-
-				/*  TODO:  fix these  */
-				reg[COP0_XCONTEXT] &= ~XCONTEXT_R_MASK;
-				reg[COP0_XCONTEXT] &= ~XCONTEXT_BADVPN2_MASK;
-				reg[COP0_XCONTEXT] |= (vaddr_vpn2 << XCONTEXT_BADVPN2_SHIFT) & XCONTEXT_BADVPN2_MASK;
-				reg[COP0_XCONTEXT] |= ((vaddr >> 62) & 0x3) << XCONTEXT_R_SHIFT;
-
-				/*  reg[COP0_PAGEMASK] = cpu->cd.mips.coproc[0]->tlbs[0].mask & PAGEMASK_MASK;  */
-
-				reg[COP0_ENTRYHI] = (vaddr & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK | 0x1800)) | vaddr_asid;
-			} else {
-				reg[COP0_CONTEXT] &= ~CONTEXT_BADVPN2_MASK;
-				reg[COP0_CONTEXT] |= ((vaddr_vpn2 << CONTEXT_BADVPN2_SHIFT) & CONTEXT_BADVPN2_MASK);
-
-				reg[COP0_XCONTEXT] &= ~XCONTEXT_R_MASK;
-				reg[COP0_XCONTEXT] &= ~XCONTEXT_BADVPN2_MASK;
-				reg[COP0_XCONTEXT] |= (vaddr_vpn2 << XCONTEXT_BADVPN2_SHIFT) & XCONTEXT_BADVPN2_MASK;
-				reg[COP0_XCONTEXT] |= ((vaddr >> 62) & 0x3) << XCONTEXT_R_SHIFT;
-
-				/*  reg[COP0_PAGEMASK] = cpu->cd.mips.coproc[0]->tlbs[0].mask & PAGEMASK_MASK;  */
-
-				// Actually, the R10000 manual says:
-				// "When either a TLB refill, TLB invalid, or TLB modified exception occurs, the
-				//  EntryHi register is loaded with the virtual page number (VPN2) and the ASID of
-				//  the virtual address that did not have a matching TLB entry."
-				// Strange that it does not mention the 2 top bits (R).
-				//
-				// However, the MIPS64 manual says:
-				// "A TLB exception (TLB Refill, XTLB Refill, TLB Invalid, or TLB Modified) causes
-				//  the bits of the virtual address corresponding to the R and VPN2 fields to be
-				//  written into the EntryHi register."
-
-				if ((reg[COP0_ENTRYHI] & ENTRYHI_ASID) != vaddr_asid)
-					fatal("[ huh? vaddr_asid 0x%02x not same as in ENTRYHI 0x%02x ]\n",
-						vaddr_asid, reg[COP0_ENTRYHI] & ENTRYHI_ASID);
-
-				if (cpu->cd.mips.cpu_type.mmu_model == MMU10K)
-					reg[COP0_ENTRYHI] = (vaddr & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K)) | vaddr_asid;
-				else
-					reg[COP0_ENTRYHI] = (vaddr & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK)) | vaddr_asid;
-			}
-		}
-	}
-
-	if (exc_model != EXC3K && reg[COP0_STATUS] & STATUS_EXL) {
-		/*
-		 *  Don't set EPC if STATUS_EXL is set, for R4000 and up.
-		 *  This actually happens when running IRIX and Ultrix, when
-		 *  they handle interrupts and/or tlb updates, I think, so
-		 *  printing this with debug() looks better than with fatal().
-		 */
-		/*  debug("[ warning: cpu%i exception while EXL is set,"
-		    " not setting EPC ]\n", cpu->cpu_id);  */
-	} else {
-		if (cpu->delay_slot) {
-			reg[COP0_EPC] = cpu->pc - 4;
-			reg[COP0_CAUSE] |= CAUSE_BD;
-		} else {
-			reg[COP0_EPC] = cpu->pc;
-			reg[COP0_CAUSE] &= ~CAUSE_BD;
-		}
-	}
-
-	if (cpu->delay_slot)
-		cpu->delay_slot = EXCEPTION_IN_DELAY_SLOT;
-	else
-		cpu->delay_slot = NOT_DELAYED;
-
-	/*  TODO: This is true for MIPS64, but how about others?  */
-	if (reg[COP0_STATUS] & STATUS_BEV)
-		base = 0xffffffffbfc00200ULL;
-	else
-		base = 0xffffffff80000000ULL;
-
-	switch (exc_model) {
-	case EXC3K:
-		/*  Userspace tlb, vs others:  */
-		if (tlb && !(vaddr & 0x80000000ULL) &&
-		    (exccode == EXCEPTION_TLBL || exccode == EXCEPTION_TLBS) )
-			cpu->pc = base + 0x000;
-		else
-			cpu->pc = base + 0x080;
-		break;
-	default:
-		/*
-		 *  These offsets are according to the MIPS64 manual, but
-		 *  should work with R4000 and the rest too (I hope).
-		 *
-		 *  0x000  TLB refill, if EXL=0
-		 *  0x080  64-bit XTLB refill, if EXL=0
-		 *  0x100  cache error  (not implemented yet)
-		 *  0x180  general exception
-		 *  0x200  interrupt (if CAUSE_IV is set)
-		 */
-		if (tlb && (exccode == EXCEPTION_TLBL ||
-		    exccode == EXCEPTION_TLBS) &&
-		    !(reg[COP0_STATUS] & STATUS_EXL)) {
-			if (x_64)
-				cpu->pc = base + 0x080;
-			else
-				cpu->pc = base + 0x000;
-		} else {
-			if (exccode == EXCEPTION_INT &&
-			    (reg[COP0_CAUSE] & CAUSE_IV))
-				cpu->pc = base + 0x200;
-			else
-				cpu->pc = base + 0x180;
-		}
-	}
-
-	if (exc_model == EXC3K) {
-		/*  R{2,3}000:  Shift the lowest 6 bits to the left two steps:*/
-		reg[COP0_STATUS] = (reg[COP0_STATUS] & ~0x3f) +
-		    ((reg[COP0_STATUS] & 0xf) << 2);
-	} else {
-		/*  R4000:  */
-		reg[COP0_STATUS] |= STATUS_EXL;
-	}
-
-	/*  Sign-extend:  */
-	reg[COP0_CAUSE] = (int64_t)(int32_t)reg[COP0_CAUSE];
-	reg[COP0_STATUS] = (int64_t)(int32_t)reg[COP0_STATUS];
-
-	if (cpu->is_32bit) {
-		reg[COP0_EPC] = (int64_t)(int32_t)reg[COP0_EPC];
-		mips32_pc_to_pointers(cpu);
-	} else {
-		mips_pc_to_pointers(cpu);
-	}
-}
-
-
-#include "memory_mips.cc"
-
-
-#include "tmp_mips_tail.cc"
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_mips_coproc.c gxemul-0.7.0+dfsg/src/cpus/cpu_mips_coproc.c
--- gxemul-0.6.2/src/cpus/cpu_mips_coproc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_mips_coproc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,2288 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Emulation of MIPS coprocessors.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#include "cop0.h"
+#include "cpu.h"
+#include "cpu_mips.h"
+#include "emul.h"
+#include "float_emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "mips_cpu_types.h"
+#include "misc.h"
+#include "opcodes_mips.h"
+#include "timer.h"
+
+
+static const char *cop0_names[] = COP0_NAMES;
+static const char *regnames[] = MIPS_REGISTER_NAMES;
+
+
+/*
+ *  initialize_cop0_config():
+ *
+ *  Helper function, called from mips_coproc_new().
+ */
+static void initialize_cop0_config(struct cpu *cpu, struct mips_coproc *c)
+{
+	const int m16 = 0;	/*  TODO: MIPS16 support  */
+	int IB, DB, SB, IC, DC, SC, IA, DA;
+
+	/*  Generic case for MIPS32/64:  */
+	if (cpu->cd.mips.cpu_type.isa_level == 32 ||
+	    cpu->cd.mips.cpu_type.isa_level == 64) {
+		/*  According to the MIPS64 (5K) User's Manual:  */
+		c->reg[COP0_CONFIG] =
+		      (   (uint32_t)1 << 31)/*  Config 1 present bit  */
+		    | (   0 << 20)	/*  ISD:  instruction scheduling
+					    disable (=1)  */
+		    | (   0 << 17)	/*  DID:  dual issue disable  */
+		    | (   0 << 16)	/*  BM:   burst mode  */
+		    | ((cpu->byte_order == EMUL_BIG_ENDIAN? 1 : 0) << 15)
+				 	/*  endian mode  */
+		    | ((cpu->cd.mips.cpu_type.isa_level == 64? 2 : 0) << 13)
+					/*  0=MIPS32, 1=64S, 2=64  */
+		    | (   0 << 10)	/*  Architecture revision  */
+		    | (   1 <<  7)	/*  MMU type: 1=TLB, 3=FMT  */
+		    | (   2 <<  0)	/*  kseg0 cache coherency algorithm  */
+		    ;
+		/*  Config select 1: caches etc. TODO: Don't use
+			cpu->machine for this stuff!  */
+		IB = cpu->cd.mips.cache_picache_linesize - 1;
+		IB = IB < 0? 0 : (IB > 7? 7 : IB);
+		DB = cpu->cd.mips.cache_pdcache_linesize - 1;
+		DB = DB < 0? 0 : (DB > 7? 7 : DB);
+		IC = cpu->cd.mips.cache_picache -
+		    cpu->cd.mips.cache_picache_linesize - 7;
+		DC = cpu->cd.mips.cache_pdcache -
+		    cpu->cd.mips.cache_pdcache_linesize - 7;
+		IA = cpu->cd.mips.cpu_type.piways - 1;
+		DA = cpu->cd.mips.cpu_type.pdways - 1;
+		cpu->cd.mips.cop0_config_select1 =
+		    ((cpu->cd.mips.cpu_type.nr_of_tlb_entries - 1) << 25)
+		    | (IC << 22)	/*  IS: I-cache sets per way  */
+		    | (IB << 19)	/*  IL: I-cache line-size  */
+		    | (IA << 16)	/*  IA: I-cache assoc. (ways-1)  */
+		    | (DC << 13)	/*  DS: D-cache sets per way  */
+		    | (DB << 10)	/*  DL: D-cache line-size  */
+		    | (DA <<  7)	/*  DA: D-cache assoc. (ways-1)  */
+		    | (16 * 0)		/*  Existance of PerformanceCounters  */
+		    | ( 8 * 0)		/*  Existance of Watch Registers  */
+		    | ( 4 * m16)	/*  Existance of MIPS16  */
+		    | ( 2 * 0)		/*  Existance of EJTAG  */
+		    | ( 1 * 1)		/*  Existance of FPU  */
+		    ;
+
+		return;
+	}
+
+	switch (cpu->cd.mips.cpu_type.rev) {
+	case MIPS_R2000:
+	case MIPS_R3000:
+		/*  No config register.  */
+		break;
+	case MIPS_R4000:	/*  according to the R4000 manual  */
+	case MIPS_R4600:
+		IB = cpu->cd.mips.cache_picache_linesize - 4;
+		IB = IB < 0? 0 : (IB > 1? 1 : IB);
+		DB = cpu->cd.mips.cache_pdcache_linesize - 4;
+		DB = DB < 0? 0 : (DB > 1? 1 : DB);
+		SB = cpu->cd.mips.cache_secondary_linesize - 4;
+		SB = SB < 0? 0 : (SB > 3? 3 : SB);
+		IC = cpu->cd.mips.cache_picache - 12;
+		IC = IC < 0? 0 : (IC > 7? 7 : IC);
+		DC = cpu->cd.mips.cache_pdcache - 12;
+		DC = DC < 0? 0 : (DC > 7? 7 : DC);
+		SC = cpu->cd.mips.cache_secondary? 0 : 1;
+		c->reg[COP0_CONFIG] =
+		      (   0 << 31)	/*  Master/Checker present bit  */
+		    | (0x00 << 28)	/*  EC: system clock divisor,
+					    0x00 = '2'  */
+		    | (0x00 << 24)	/*  EP  */
+		    | (  SB << 22)	/*  SB  */
+		    | (0x00 << 21)	/*  SS: 0 = mixed i/d scache  */
+		    | (0x00 << 20)	/*  SW  */
+		    | (0x00 << 18)	/*  EW: 0=64-bit  */
+		    | (  SC << 17)	/*  SC: 0=secondary cache present,
+					    1=non-present  */
+		    | (0x00 << 16)	/*  SM: (todo)  */
+		    | ((cpu->byte_order==EMUL_BIG_ENDIAN? 1 : 0) << 15)
+				 	/*  endian mode  */
+		    | (0x01 << 14)	/*  ECC: 0=enabled, 1=disabled  */
+		    | (0x00 << 13)	/*  EB: (todo)  */
+		    | (0x00 << 12)	/*  0 (resered)  */
+		    | (  IC <<  9)	/*  IC: I-cache = 2^(12+IC) bytes
+					    (1 = 8KB, 4=64K)  */
+		    | (  DC <<  6)	/*  DC: D-cache = 2^(12+DC) bytes
+					    (1 = 8KB, 4=64K)  */
+		    | (  IB <<  5)	/*  IB: I-cache line size (0=16,
+					    1=32)  */
+		    | (  DB <<  4)	/*  DB: D-cache line size (0=16,
+					    1=32)  */
+		    | (   0 <<  3)	/*  CU: todo  */
+		    | (   0 <<  0)	/*  kseg0 coherency algorithm
+						(TODO)  */
+		    ;
+		break;
+	case MIPS_R4100:	/*  According to the VR4131 manual:  */
+		IB = cpu->cd.mips.cache_picache_linesize - 4;
+		IB = IB < 0? 0 : (IB > 1? 1 : IB);
+		DB = cpu->cd.mips.cache_pdcache_linesize - 4;
+		DB = DB < 0? 0 : (DB > 1? 1 : DB);
+		IC = cpu->cd.mips.cache_picache - 10;
+		IC = IC < 0? 0 : (IC > 7? 7 : IC);
+		DC = cpu->cd.mips.cache_pdcache - 10;
+		DC = DC < 0? 0 : (DC > 7? 7 : DC);
+		c->reg[COP0_CONFIG] =
+		      (   0 << 31)	/*  IS: Instruction Streaming bit  */
+		    | (0x01 << 28)	/*  EC: system clock divisor,
+					    0x01 = 2  */
+		    | (0x00 << 24)	/*  EP  */
+		    | (0x00 << 23)	/*  AD: Accelerate data mode
+					    (0=VR4000-compatible)  */
+		    | ( m16 << 20)	/*  M16: MIPS16 support  */
+		    | (   1 << 17)	/*  '1'  */
+		    | (0x00 << 16)	/*  BP: 'Branch forecast'
+					    (0 = enabled)  */
+		    | ((cpu->byte_order==EMUL_BIG_ENDIAN? 1 : 0) << 15)
+				 	/*  endian mode  */
+		    | (   2 << 13)	/*  '2' hardcoded on VR4131  */
+		    | (   1 << 12)	/*  CS: Cache size mode
+					    (1 on VR4131)  */
+		    | (  IC <<  9)	/*  IC: I-cache = 2^(10+IC) bytes
+					    (0 = 1KB, 4=16K)  */
+		    | (  DC <<  6)	/*  DC: D-cache = 2^(10+DC) bytes
+					    (0 = 1KB, 4=16K)  */
+		    | (  IB <<  5)	/*  IB: I-cache line size (0=16,
+					    1=32)  */
+		    | (  DB <<  4)	/*  DB: D-cache line size (0=16,
+					    1=32)  */
+		    | (   0 <<  0)	/*  kseg0 coherency algorithm (TODO)  */
+		    ;
+		break;
+	case MIPS_R5000:
+	case MIPS_RM5200:	/*  rm5200 is just a wild guess  */
+		/*  These are just guesses: (the comments are wrong) */
+		c->reg[COP0_CONFIG] =
+		      (   0 << 31)	/*  Master/Checker present bit  */
+		    | (0x00 << 28)	/*  EC: system clock divisor,
+					    0x00 = '2'  */
+		    | (0x00 << 24)	/*  EP  */
+		    | (0x00 << 22)	/*  SB  */
+		    | (0x00 << 21)	/*  SS  */
+		    | (0x00 << 20)	/*  SW  */
+		    | (0x00 << 18)	/*  EW: 0=64-bit  */
+		    | (0x01 << 17)	/*  SC: 0=secondary cache present,
+					    1=non-present  */
+		    | (0x00 << 16)	/*  SM: (todo)  */
+		    | ((cpu->byte_order==EMUL_BIG_ENDIAN? 1 : 0) << 15)
+				 	/*  endian mode  */
+		    | (0x01 << 14)	/*  ECC: 0=enabled, 1=disabled  */
+		    | (0x00 << 13)	/*  EB: (todo)  */
+		    | (0x00 << 12)	/*  0 (resered)  */
+		    | (   3 <<  9)	/*  IC: I-cache = 2^(12+IC) bytes
+					    (1 = 8KB, 4=64K)  */
+		    | (   3 <<  6)	/*  DC: D-cache = 2^(12+DC) bytes
+					    (1 = 8KB, 4=64K)  */
+		    | (   1 <<  5)	/*  IB: I-cache line size (0=16,
+					    1=32)  */
+		    | (   1 <<  4)	/*  DB: D-cache line size (0=16,
+					    1=32)  */
+		    | (   0 <<  3)	/*  CU: todo  */
+		    | (   2 <<  0)	/*  kseg0 coherency algorithm
+						(TODO)  */
+		    ;
+		break;
+	case MIPS_R10000:
+	case MIPS_R12000:
+	case MIPS_R14000:
+		IC = cpu->cd.mips.cache_picache - 12;
+		IC = IC < 0? 0 : (IC > 7? 7 : IC);
+		DC = cpu->cd.mips.cache_pdcache - 12;
+		DC = DC < 0? 0 : (DC > 7? 7 : DC);
+		SC = cpu->cd.mips.cache_secondary - 19;
+		SC = SC < 0? 0 : (SC > 7? 7 : SC);
+		/*  According to the R10000 User's Manual:  */
+		c->reg[COP0_CONFIG] =
+		      (  IC << 29)	/*  Primary instruction cache size
+					    (3 = 32KB)  */
+		    | (  DC << 26)	/*  Primary data cache size (3 =
+					    32KB)  */
+		    | (   0 << 19)	/*  SCClkDiv  */
+		    | (  SC << 16)	/*  SCSize, secondary cache size.
+					    0 = 512KB. powers of two  */
+		    | (   0 << 15)	/*  MemEnd  */
+		    | (   0 << 14)	/*  SCCorEn  */
+		    | (   1 << 13)	/*  SCBlkSize. 0=16 words,
+					    1=32 words  */
+		    | (   0 <<  9)	/*  SysClkDiv  */
+		    | (   0 <<  7)	/*  PrcReqMax  */
+		    | (   0 <<  6)	/*  PrcElmReq  */
+		    | (   0 <<  5)	/*  CohPrcReqTar  */
+		    | (   0 <<  3)	/*  Device number  */
+		    | (   2 <<  0)	/*  Cache coherency algorithm for
+					    kseg0  */
+		    ;
+		break;
+	case MIPS_R5900:
+		/*
+		 *  R5900 is supposed to have the following (according
+		 *  to NetBSD/playstation2):
+		 *	cpu0: 16KB/64B 2-way set-associative L1 Instruction
+		 *		cache, 48 TLB entries
+		 *	cpu0: 8KB/64B 2-way set-associative write-back L1
+		 *		Data cache
+		 *  The following settings are just guesses:
+		 *  (comments are incorrect)
+		 */
+		c->reg[COP0_CONFIG] =
+		      (   0 << 31)	/*  Master/Checker present bit  */
+		    | (0x00 << 28)	/*  EC: system clock divisor,
+					    0x00 = '2'  */
+		    | (0x00 << 24)	/*  EP  */
+		    | (0x00 << 22)	/*  SB  */
+		    | (0x00 << 21)	/*  SS  */
+		    | (0x00 << 20)	/*  SW  */
+		    | (0x00 << 18)	/*  EW: 0=64-bit  */
+		    | (0x01 << 17)	/*  SC: 0=secondary cache present,
+					    1=non-present  */
+		    | (0x00 << 16)	/*  SM: (todo)  */
+		    | ((cpu->byte_order==EMUL_BIG_ENDIAN? 1 : 0) << 15)
+				 	/*  endian mode  */
+		    | (0x01 << 14)	/*  ECC: 0=enabled, 1=disabled  */
+		    | (0x00 << 13)	/*  EB: (todo)  */
+		    | (0x00 << 12)	/*  0 (resered)  */
+		    | (   3 <<  9)	/*  IC: I-cache = 2^(12+IC) bytes
+					    (1 = 8KB, 4=64K)  */
+		    | (   3 <<  6)	/*  DC: D-cache = 2^(12+DC) bytes
+					    (1 = 8KB, 4=64K)  */
+		    | (   1 <<  5)	/*  IB: I-cache line size (0=16,
+					    1=32)  */
+		    | (   1 <<  4)	/*  DB: D-cache line size (0=16,
+					    1=32)  */
+		    | (   0 <<  3)	/*  CU: todo  */
+		    | (   0 <<  0)	/*  kseg0 coherency algorithm
+						(TODO)  */
+		    ;
+		break;
+	default:fatal("Internal error: No initialization code for"
+		    " config0? cpu rev = 0x%x", cpu->cd.mips.cpu_type.rev);
+		exit(1);
+	}
+}
+
+
+/*
+ *  initialize_cop1():
+ *
+ *  Helper function, called from mips_coproc_new().
+ */
+static void initialize_cop1(struct cpu *cpu, struct mips_coproc *c)
+{
+	int fpu_rev;
+	uint64_t other_stuff = 0;
+
+	switch (cpu->cd.mips.cpu_type.rev & 0xff) {
+	case MIPS_R2000:	fpu_rev = MIPS_R2010;	break;
+	case MIPS_R3000:	fpu_rev = MIPS_R3010;
+				other_stuff |= 0x40;	/*  or 0x30? TODO  */
+				break;
+	case MIPS_R6000:	fpu_rev = MIPS_R6010;	break;
+	case MIPS_R4000:	fpu_rev = MIPS_R4010;	break;
+	case MIPS_4Kc:		/*  TODO: Is this the same as 5Kc?  */
+	case MIPS_5Kc:		other_stuff = COP1_REVISION_DOUBLE
+				    | COP1_REVISION_SINGLE;
+				// fall through
+	case MIPS_R5000:
+	case MIPS_RM5200:	fpu_rev = cpu->cd.mips.cpu_type.rev;
+				other_stuff |= 0x10;
+				/*  or cpu->cd.mips.cpu_type.sub ? TODO  */
+				break;
+	case MIPS_R10000:	fpu_rev = MIPS_R10000;	break;
+	case MIPS_R12000:	fpu_rev = 0x9;	break;
+	default:		fpu_rev = MIPS_SOFT;
+	}
+
+	c->fcr[COP1_REVISION] = (fpu_rev << 8) | other_stuff;
+
+#if 0
+	/*  These are mentioned in the MIPS64 documentation:  */
+	    + (1 << 16)		/*  single  */
+	    + (1 << 17)		/*  double  */
+	    + (1 << 18)		/*  paired-single  */
+	    + (1 << 19)		/*  3d  */
+#endif
+}
+
+
+/*
+ *  mips_coproc_new():
+ *
+ *  Create a new MIPS coprocessor object.
+ */
+struct mips_coproc *mips_coproc_new(struct cpu *cpu, int coproc_nr)
+{
+	struct mips_coproc *c;
+
+	CHECK_ALLOCATION(c = (struct mips_coproc *) malloc(sizeof(struct mips_coproc)));
+	memset(c, 0, sizeof(struct mips_coproc));
+
+	c->coproc_nr = coproc_nr;
+
+	if (coproc_nr == 0) {
+		c->nr_of_tlbs = cpu->cd.mips.cpu_type.nr_of_tlb_entries;
+		c->tlbs = (struct mips_tlb *) zeroed_alloc(c->nr_of_tlbs * sizeof(struct mips_tlb));
+
+		/*
+		 *  Start with nothing in the status register. This makes sure
+		 *  that we are running in kernel mode with all interrupts
+		 *  disabled.
+		 */
+		c->reg[COP0_STATUS] = 0;
+
+		/*  Hm. Enable coprocessors 0 and 1 even if we're not just
+		    emulating userland? TODO: Think about this.  */
+		/*  if (cpu->machine->prom_emulation)  */
+			c->reg[COP0_STATUS] |=
+			    ((uint32_t)0x3 << STATUS_CU_SHIFT);
+
+		if (!cpu->machine->prom_emulation)
+			c->reg[COP0_STATUS] |= STATUS_BEV;
+
+		/*  Ugly hack for R5900/TX79/C790:  */
+		if (cpu->cd.mips.cpu_type.rev == MIPS_R5900)
+			c->reg[COP0_STATUS] |= R5900_STATUS_EIE;
+
+		/*  Default pagesize = 4 KB  (i.e. dualpage = 8KB)  */
+		c->reg[COP0_PAGEMASK] = 0x1fff;
+
+		/*  Note: .rev may contain the company ID as well!  */
+		c->reg[COP0_PRID] =
+		      (0x00 << 24)			/*  Company Options  */
+		    | (0x00 << 16)			/*  Company ID       */
+		    | (cpu->cd.mips.cpu_type.rev <<  8)	/*  Processor ID     */
+		    | (cpu->cd.mips.cpu_type.sub)	/*  Revision         */
+		    ;
+
+		c->reg[COP0_WIRED] = 0;
+
+		initialize_cop0_config(cpu, c);
+
+		/*  Make sure the status register is sign-extended nicely:  */
+		c->reg[COP0_STATUS] = (int32_t)c->reg[COP0_STATUS];
+	}
+
+	if (coproc_nr == 1)
+		initialize_cop1(cpu, c);
+
+	return c;
+}
+
+
+/*
+ *  mips_timer_tick():
+ */
+static void mips_timer_tick(struct timer *timer, void *extra)
+{
+	struct cpu *cpu = (struct cpu *) extra;
+
+	cpu->cd.mips.compare_interrupts_pending ++;
+
+	if ((int32_t) (cpu->cd.mips.coproc[0]->reg[COP0_COUNT] -
+	    cpu->cd.mips.coproc[0]->reg[COP0_COMPARE]) < 0) {
+		cpu->cd.mips.coproc[0]->reg[COP0_COUNT] =
+		    cpu->cd.mips.coproc[0]->reg[COP0_COMPARE];
+	}
+}
+
+
+/*
+ *  mips_coproc_tlb_set_entry():
+ *
+ *  Used by machine setup code, if a specific machine emulation starts up
+ *  with hardcoded virtual to physical mappings.
+ */
+void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size,
+	uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
+	int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
+	int cachealgo0, int cachealgo1)
+{
+	if (entrynr < 0 || entrynr >= cpu->cd.mips.coproc[0]->nr_of_tlbs) {
+		printf("mips_coproc_tlb_set_entry(): invalid entry nr: %i\n",
+		    entrynr);
+		exit(1);
+	}
+
+	switch (cpu->cd.mips.cpu_type.mmu_model) {
+	case MMU3K:
+		if (size != 4096) {
+			printf("mips_coproc_tlb_set_entry(): invalid pagesize "
+			    "(%i) for MMU3K\n", size);
+			exit(1);
+		}
+		cpu->cd.mips.coproc[0]->tlbs[entrynr].hi =
+		    (vaddr & R2K3K_ENTRYHI_VPN_MASK) |
+		    ((asid << R2K3K_ENTRYHI_ASID_SHIFT) & 
+		    R2K3K_ENTRYHI_ASID_MASK);
+		cpu->cd.mips.coproc[0]->tlbs[entrynr].lo0 =
+		    (paddr0 & R2K3K_ENTRYLO_PFN_MASK) |
+		    (cachealgo0? R2K3K_ENTRYLO_N : 0) |
+		    (dirty0? R2K3K_ENTRYLO_D : 0) |
+		    (valid0? R2K3K_ENTRYLO_V : 0) |
+		    (global? R2K3K_ENTRYLO_G : 0);
+		break;
+	default:
+		/*  MMU4K and MMU10K, etc:  */
+		if (cpu->cd.mips.cpu_type.mmu_model == MMU10K)
+			cpu->cd.mips.coproc[0]->tlbs[entrynr].hi =
+			    (vaddr & ENTRYHI_VPN2_MASK_R10K) |
+			    (vaddr & ENTRYHI_R_MASK) |
+			    (asid & ENTRYHI_ASID) |
+			    (global? TLB_G : 0);
+		else
+			cpu->cd.mips.coproc[0]->tlbs[entrynr].hi =
+			    (vaddr & ENTRYHI_VPN2_MASK) |
+			    (vaddr & ENTRYHI_R_MASK) |
+			    (asid & ENTRYHI_ASID) |
+			    (global? TLB_G : 0);
+		/*  NOTE: The pagemask size is for a "dual" page:  */
+		cpu->cd.mips.coproc[0]->tlbs[entrynr].mask =
+		    (2*size - 1) & ~0x1fff;
+		cpu->cd.mips.coproc[0]->tlbs[entrynr].lo0 =
+		    (((paddr0 >> 12) << ENTRYLO_PFN_SHIFT) &
+			ENTRYLO_PFN_MASK) |
+		    (dirty0? ENTRYLO_D : 0) |
+		    (valid0? ENTRYLO_V : 0) |
+		    (global? ENTRYLO_G : 0) |
+		    ((cachealgo0 << ENTRYLO_C_SHIFT) & ENTRYLO_C_MASK);
+		cpu->cd.mips.coproc[0]->tlbs[entrynr].lo1 =
+		    (((paddr1 >> 12) << ENTRYLO_PFN_SHIFT) &
+			ENTRYLO_PFN_MASK) |
+		    (dirty1? ENTRYLO_D : 0) |
+		    (valid1? ENTRYLO_V : 0) |
+		    (global? ENTRYLO_G : 0) |
+		    ((cachealgo1 << ENTRYLO_C_SHIFT) & ENTRYLO_C_MASK);
+		/*  TODO: R4100, 1KB pages etc  */
+	}
+}
+
+
+/*
+ *  invalidate_asid():
+ *
+ *  Go through all entries in the TLB. If an entry has a matching asid, is
+ *  valid, and is not global (i.e. the ASID matters), then its virtual address
+ *  translation is invalidated.
+ *
+ *  Note: In the R3000 case, the asid argument is shifted 6 bits.
+ */
+static void invalidate_asid(struct cpu *cpu, unsigned int asid)
+{
+	struct mips_coproc *cp = cpu->cd.mips.coproc[0];
+	unsigned int i, ntlbs = cp->nr_of_tlbs;
+	struct mips_tlb *tlb = cp->tlbs;
+
+	if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
+		for (i = 0; i < ntlbs; i++)
+			if ((tlb[i].hi & R2K3K_ENTRYHI_ASID_MASK) == asid
+			    && (tlb[i].lo0 & R2K3K_ENTRYLO_V)
+			    && !(tlb[i].lo0 & R2K3K_ENTRYLO_G)) {
+				cpu->invalidate_translation_caches(cpu,
+				    tlb[i].hi & R2K3K_ENTRYHI_VPN_MASK,
+				    INVALIDATE_VADDR);
+			}
+	} else {
+		for (i = 0; i < ntlbs; i++) {
+			if ((tlb[i].hi & ENTRYHI_ASID) != asid || (tlb[i].hi & TLB_G))
+				continue;
+
+			uint64_t mask = cp->tlbs[i].mask;
+			uint64_t pagesize = 0x1000;
+			uint64_t tmp = mask >> 13;
+			while ((tmp & 1)) {
+				tmp >>= 1;
+				pagesize <<= 1;
+			}
+			
+			uint64_t oldvaddr;
+
+			if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) {
+				oldvaddr = cp->tlbs[i].hi &
+					    (ENTRYHI_VPN2_MASK_R10K | ENTRYHI_R_MASK);
+			} else if (cpu->is_32bit) {
+				/*  MIPS32 etc.:  */
+				oldvaddr = cp->tlbs[i].hi & ENTRYHI_VPN2_MASK;
+				oldvaddr = (int32_t)oldvaddr;
+			} else {
+				/*  Assume MMU4K  */
+				oldvaddr = cp->tlbs[i].hi &
+				    (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK);
+			}
+
+			mask |= 0x1fff;
+			oldvaddr &= ~mask;
+
+			// printf("pagesize = %016llx mask = %016llx\n", pagesize, mask);
+			
+			if (cp->tlbs[i].lo0 & ENTRYLO_V)
+				for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
+					cpu->invalidate_translation_caches(cpu, oldvaddr + ofs, INVALIDATE_VADDR);
+			
+			if (cp->tlbs[i].lo1 & ENTRYLO_V)
+				for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
+					cpu->invalidate_translation_caches(cpu, oldvaddr + ofs + pagesize, INVALIDATE_VADDR);
+		}
+	}
+}
+
+
+/*
+ *  coproc_register_read();
+ *
+ *  Read a value from a MIPS coprocessor register.
+ */
+void coproc_register_read(struct cpu *cpu,
+	struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select)
+{
+	int unimpl = 1;
+
+	if (cp->coproc_nr==0 && reg_nr==COP0_INDEX)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_RANDOM)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_ENTRYLO0)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_ENTRYLO1)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_CONTEXT)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_PAGEMASK)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_WIRED)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_BADVADDR)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_COUNT) {
+		/*  TODO: Increase count in a more meaningful way!  */
+		cp->reg[COP0_COUNT] = (int32_t) (cp->reg[COP0_COUNT] + 1);
+		cpu->cd.mips.count_register_read_count ++;
+		unimpl = 0;
+	}
+	if (cp->coproc_nr==0 && reg_nr==COP0_ENTRYHI)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_COMPARE)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_STATUS)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_CAUSE)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_EPC)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_PRID)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_CONFIG) {
+		if (select > 0) {
+			switch (select) {
+			case 1:	*ptr = cpu->cd.mips.cop0_config_select1;
+				break;
+			default:fatal("coproc_register_read(): unimplemented"
+				    " config register select %i\n", select);
+				exit(1);
+			}
+			return;
+		}
+		unimpl = 0;
+	}
+	if (cp->coproc_nr==0 && reg_nr==COP0_LLADDR)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_WATCHLO)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_WATCHHI)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_XCONTEXT)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_ERRCTL)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_CACHEERR)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_TAGDATA_LO)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_TAGDATA_HI)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_ERROREPC)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_RESERV22) {
+		/*  Used by Linux on Linksys WRT54G  */
+		unimpl = 0;
+	}
+	if (cp->coproc_nr==0 && reg_nr==COP0_DEBUG)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_PERFCNT)	unimpl = 0;
+	if (cp->coproc_nr==0 && reg_nr==COP0_DESAVE)	unimpl = 0;
+
+	if (cp->coproc_nr==1)	unimpl = 0;
+
+	if (unimpl) {
+		fatal("cpu%i: warning: read from unimplemented coproc%i"
+		    " register %i (%s)\n", cpu->cpu_id, cp->coproc_nr, reg_nr,
+		    cp->coproc_nr==0? cop0_names[reg_nr] : "?");
+
+		mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0,
+		    cp->coproc_nr, 0, 0, 0);
+		return;
+	}
+
+	*ptr = cp->reg[reg_nr];
+}
+
+
+/*
+ *  coproc_register_write();
+ *
+ *  Write a value to a MIPS coprocessor register.
+ */
+void coproc_register_write(struct cpu *cpu,
+	struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64,
+	int select)
+{
+	int unimpl = 1;
+	int readonly = 0;
+	uint64_t tmp = *ptr;
+	uint64_t tmp2 = 0, old;
+	int inval = 0;
+	unsigned int old_asid;
+	uint64_t oldmode;
+
+	switch (cp->coproc_nr) {
+	case 0:
+		/*  COPROC 0:  */
+		switch (reg_nr) {
+		case COP0_INDEX:
+		case COP0_RANDOM:
+			unimpl = 0;
+			break;
+		case COP0_ENTRYLO0:
+			unimpl = 0;
+			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
+				/*  char *symbol;
+				    uint64_t offset;
+				    symbol = get_symbol_name(cpu->pc, &offset);
+				    fatal("YO! pc = 0x%08llx <%s> "
+				    "lo=%016llx\n", (long long)
+				    cpu->pc, symbol? symbol :
+				    "no symbol", (long long)tmp); */
+				tmp &= (R2K3K_ENTRYLO_PFN_MASK |
+				    R2K3K_ENTRYLO_N | R2K3K_ENTRYLO_D |
+				    R2K3K_ENTRYLO_V | R2K3K_ENTRYLO_G);
+			} else {
+				// Both MIPS III (such as R4000) and MIPS32/MIPS64 (?)
+				tmp &= (ENTRYLO_PFN_MASK | ENTRYLO_C_MASK |
+				    ENTRYLO_D | ENTRYLO_V | ENTRYLO_G);
+
+				int c = (tmp & ENTRYLO_C_MASK) >> ENTRYLO_C_SHIFT;
+				switch (c) {
+				case 2:	// Uncached
+				case 3:	// Cached
+					break;
+				default:if (tmp & ENTRYLO_V)
+						debug("[ MIPS coproc_register_write: unimplemented c = %i ]\n", c);
+				}
+			}
+			break;
+		case COP0_BADVADDR:
+			/*  Hm. Irix writes to this register. (Why?)  */
+			unimpl = 0;
+			break;
+		case COP0_ENTRYLO1:
+			unimpl = 0;
+			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
+				fatal("Attempt to access ENTRYLO1 with MMU3K?\n");
+				exit(1);
+			}
+			// Both MIPS III (such as R4000) and MIPS32/MIPS64 (?)
+			if (cpu->cd.mips.cpu_type.mmu_model != MMU3K) {
+				tmp &= (ENTRYLO_PFN_MASK | ENTRYLO_C_MASK |
+				    ENTRYLO_D | ENTRYLO_V | ENTRYLO_G);
+			}
+			break;
+		case COP0_CONTEXT:
+			old = cp->reg[COP0_CONTEXT];
+			cp->reg[COP0_CONTEXT] = tmp;
+			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
+				cp->reg[COP0_CONTEXT] &=
+				    ~R2K3K_CONTEXT_BADVPN_MASK;
+				cp->reg[COP0_CONTEXT] |=
+				    (old & R2K3K_CONTEXT_BADVPN_MASK);
+			} else if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
+				cp->reg[COP0_CONTEXT] &=
+				    ~CONTEXT_BADVPN2_MASK_R4100;
+				cp->reg[COP0_CONTEXT] |=
+				    (old & CONTEXT_BADVPN2_MASK_R4100);
+			} else {
+				cp->reg[COP0_CONTEXT] &=
+				    ~CONTEXT_BADVPN2_MASK;
+				cp->reg[COP0_CONTEXT] |=
+				    (old & CONTEXT_BADVPN2_MASK);
+			}
+			return;
+		case COP0_PAGEMASK:
+			tmp2 = tmp >> PAGEMASK_SHIFT;
+			if (cpu->cd.mips.cpu_type.rev != MIPS_R4100) {
+				if (tmp2 != 0x000 &&
+				    tmp2 != 0x003 &&
+				    tmp2 != 0x00f &&
+				    tmp2 != 0x03f &&
+				    tmp2 != 0x0ff &&
+				    tmp2 != 0x3ff &&
+				    tmp2 != 0xfff &&
+				    tmp2 != 0x3fff &&
+				    tmp2 != 0xffff)
+					fatal("[ cpu%i: trying to write an invalid"
+					    " pagemask 0x%08lx to COP0_PAGEMASK ]\n",
+					    cpu->cpu_id, (long)tmp);
+				// Actually just 0xfff << shift for R10000.
+				if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) {
+					tmp &= 0x0fff << PAGEMASK_SHIFT;
+				} else {
+					tmp &= 0xffff << PAGEMASK_SHIFT;
+				}
+			}
+			unimpl = 0;
+			break;
+		case COP0_WIRED:
+			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
+				fatal("[ cpu%i: r2k/r3k wired register must "
+				    "always be 8 ]\n", cpu->cpu_id);
+				tmp = 8;
+			}
+			cp->reg[COP0_RANDOM] = cp->nr_of_tlbs-1;
+			tmp &= INDEX_MASK;
+			unimpl = 0;
+			break;
+		case COP0_COUNT:
+			if (tmp != (uint64_t)(int64_t)(int32_t)tmp)
+				fatal("[ WARNING: trying to write a 64-bit value"
+				    " to the COUNT register! ]\n");
+			tmp = (int64_t)(int32_t)tmp;
+			unimpl = 0;
+			break;
+		case COP0_COMPARE:
+			if (cpu->machine->emulated_hz > 0) {
+				int32_t compare_diff = tmp -
+				    cp->reg[COP0_COMPARE];
+				double hz;
+
+				if (compare_diff < 0)
+					hz = tmp - cp->reg[COP0_COUNT];
+
+				if (compare_diff == 0)
+					hz = 0;
+				else
+					hz = (double)cpu->machine->emulated_hz
+					    / (double)compare_diff;
+
+				/*  Initialize or re-set the periodic timer:  */
+				if (hz > 0) {
+					if (cpu->cd.mips.timer == NULL)
+						cpu->cd.mips.timer = timer_add(
+						    hz, mips_timer_tick, cpu);
+					else
+						timer_update_frequency(
+						    cpu->cd.mips.timer, hz);
+				}
+			}
+
+			/*  Ack the periodic timer, if it was asserted:  */
+			if (cp->reg[COP0_CAUSE] & 0x8000 &&
+			    cpu->cd.mips.compare_interrupts_pending > 0)
+				cpu->cd.mips.compare_interrupts_pending --;
+
+			/*  Clear the timer interrupt assertion (bit 7):  */
+			cp->reg[COP0_CAUSE] &= ~0x8000;
+
+			if (tmp != (uint64_t)(int64_t)(int32_t)tmp)
+				fatal("[ WARNING: trying to write a 64-bit value"
+				    " to the COMPARE register! ]\n");
+
+			tmp = (int64_t)(int32_t)tmp;
+			cpu->cd.mips.compare_register_set = 1;
+			unimpl = 0;
+			break;
+		case COP0_ENTRYHI:
+			/*
+			 *  Translation caches must be invalidated if the
+			 *  ASID changes:
+			 */
+			switch (cpu->cd.mips.cpu_type.mmu_model) {
+			case MMU3K:
+				old_asid = cp->reg[COP0_ENTRYHI] &
+				    R2K3K_ENTRYHI_ASID_MASK;
+				if ((cp->reg[COP0_ENTRYHI] &
+				    R2K3K_ENTRYHI_ASID_MASK) !=
+				    (tmp & R2K3K_ENTRYHI_ASID_MASK))
+					inval = 1;
+				break;
+			default:
+				old_asid = cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID;
+				if ((cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID) !=
+				    (tmp & ENTRYHI_ASID))
+					inval = 1;
+				break;
+			}
+
+			if (inval)
+				invalidate_asid(cpu, old_asid);
+
+			unimpl = 0;
+			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K &&
+			    (tmp & 0x3f)!=0) {
+				/* char *symbol;
+				   uint64_t offset;
+				   symbol = get_symbol_name(cpu->pc,
+				    &offset);
+				   fatal("YO! pc = 0x%08llx <%s> "
+				    "hi=%016llx\n", (long long)cpu->pc,
+				    symbol? symbol :
+				    "no symbol", (long long)tmp);  */
+				tmp &= ~0x3f;
+			}
+			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K)
+				tmp &= (R2K3K_ENTRYHI_VPN_MASK |
+				    R2K3K_ENTRYHI_ASID_MASK);
+			else if (cpu->cd.mips.cpu_type.mmu_model == MMU10K)
+				tmp &= (ENTRYHI_R_MASK |
+				    ENTRYHI_VPN2_MASK_R10K | ENTRYHI_ASID);
+			else if (cpu->cd.mips.cpu_type.rev == MIPS_R4100)
+				tmp &= (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK |
+				    0x1800 | ENTRYHI_ASID);
+			else
+				tmp &= (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK |
+				    ENTRYHI_ASID);
+			break;
+		case COP0_EPC:
+			unimpl = 0;
+			break;
+		case COP0_PRID:
+			readonly = 1;
+			break;
+		case COP0_CONFIG:
+			if (select > 0) {
+				switch (select) {
+				case 1:	cpu->cd.mips.cop0_config_select1 = tmp;
+					break;
+				default:fatal("[ coproc_register_write(): unimpl"
+					    "emented config register select "
+					    "%i ]\n", select);
+					exit(1);
+				}
+				return;
+			}
+
+			/*  fatal("COP0_CONFIG: modifying K0 bits: "
+			    "0x%08x => ", cp->reg[reg_nr]);  */
+			tmp = *ptr;
+			tmp &= 0x3;	/*  only bits 2..0 can be written  */
+			cp->reg[reg_nr] &= ~(0x3);  cp->reg[reg_nr] |= tmp;
+			/*  fatal("0x%08x\n", cp->reg[reg_nr]);  */
+			return;
+		case COP0_STATUS:
+			oldmode = cp->reg[COP0_STATUS];
+			tmp &= ~(1 << 21);	/*  bit 21 is read-only  */
+
+			/*
+			 *  When switching between 32-bit and 64-bit address
+			 *  spaces, invalidate all translations.
+			 */
+			if (!cpu->is_32bit &&
+			    (oldmode & (STATUS_KX | STATUS_SX | STATUS_UX)) !=
+			    (tmp & (STATUS_KX | STATUS_SX | STATUS_UX)))
+				cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
+
+			/*
+			 *  When isolating caches, invalidate all translations.
+			 *  During the isolation, a special hack in memory_rw.c
+			 *  prevents translation tables from being updated, so
+			 *  the translation caches don't have to be invalidated
+			 *  when switching back to normal mode.
+			 */
+			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K &&
+			    (oldmode & MIPS1_ISOL_CACHES) !=
+			    (tmp & MIPS1_ISOL_CACHES)) {
+				/*  Invalidate everything if we are switching
+				    to isolated mode:  */
+				if (tmp & MIPS1_ISOL_CACHES) {
+					cpu->invalidate_translation_caches(
+					    cpu, 0, INVALIDATE_ALL);
+				}
+			}
+			unimpl = 0;
+			break;
+		case COP0_CAUSE:
+			/*  A write to the cause register only
+			    affects IM bits 0 and 1:  */
+			cp->reg[reg_nr] &= ~(0x3 << STATUS_IM_SHIFT);
+			cp->reg[reg_nr] |= (tmp & (0x3 << STATUS_IM_SHIFT));
+			return;
+		case COP0_FRAMEMASK:
+			/*  TODO: R10000  */
+			unimpl = 0;
+			break;
+		case COP0_TAGDATA_LO:
+		case COP0_TAGDATA_HI:
+			/*  TODO: R4300 and others?  */
+			unimpl = 0;
+			break;
+		case COP0_LLADDR:
+			unimpl = 0;
+			break;
+		case COP0_WATCHLO:
+		case COP0_WATCHHI:
+			unimpl = 0;
+			break;
+		case COP0_XCONTEXT:
+			/*
+			 *  TODO:  According to the R10000 manual, the R4400
+			 *  shares the PTEbase portion of the context registers
+			 *  (that is, xcontext and context). On R10000, they
+			 *  are separate registers.
+			 */
+			/*  debug("[ xcontext 0x%016llx ]\n", tmp);  */
+			unimpl = 0;
+			break;
+
+		/*  Most of these are actually TODOs:  */
+		case COP0_ERROREPC:
+		case COP0_DEPC:
+		case COP0_RESERV22:	/*  Used by Linux on Linksys WRT54G  */
+		case COP0_DESAVE:
+		case COP0_PERFCNT:
+		case COP0_ERRCTL:	/*  R10000  */
+			unimpl = 0;
+			break;
+		}
+		break;
+
+	case 1:
+		/*  COPROC 1:  */
+		unimpl = 0;
+		break;
+	}
+
+	if (unimpl) {
+		fatal("[ cpu%i: warning: write to unimplemented coproc%i "
+		    "register %i (%s), data = 0x%016llx ]\n", cpu->cpu_id,
+		    cp->coproc_nr, reg_nr, cp->coproc_nr==0?
+		    cop0_names[reg_nr] : "?", (long long)tmp);
+
+		/*  mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0,
+		    cp->coproc_nr, 0, 0, 0);
+		return;  */
+	}
+
+	if (readonly) {
+		fatal("[ cpu%i: warning: write to READONLY coproc%i register "
+		    "%i ignored ]\n", cpu->cpu_id, cp->coproc_nr, reg_nr);
+		return;
+	}
+
+	cp->reg[reg_nr] = tmp;
+
+	if (!flag64)
+		cp->reg[reg_nr] = (int64_t)(int32_t)cp->reg[reg_nr];
+}
+
+
+/*
+ *  MIPS floating-point stuff:
+ *
+ *  TODO:  Move this to some other file?
+ */
+static int mips_fmt_to_ieee_fmt[32] = {
+	0, 0, 0, 0,  0, 0, 0, 0,
+	0, 0, 0, 0,  0, 0, 0, 0,
+	IEEE_FMT_S, IEEE_FMT_D, 0, 0,
+	IEEE_FMT_W, IEEE_FMT_L, /* PS (Paired Single) */ 0, 0,
+	0, 0, 0, 0,  0, 0, 0, 0  };
+
+static const char *fmtname[32] = {
+	 "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
+	 "8",  "9", "10", "11", "12", "13", "14", "15",
+	 "s",  "d", "18", "19",  "w",  "l", "ps", "23",
+	"24", "25", "26", "27", "28", "29", "30", "31" 	};
+
+static const char *ccname[16] = {
+	"f",  "un",   "eq",  "ueq", "olt", "ult", "ole", "ule",
+	"sf", "ngle", "seq", "ngl", "lt",  "nge", "le",  "ngt"  };
+
+#define	FPU_OP_ADD	1
+#define	FPU_OP_SUB	2
+#define	FPU_OP_MUL	3
+#define	FPU_OP_DIV	4
+#define	FPU_OP_SQRT	5
+#define	FPU_OP_MOV	6
+#define	FPU_OP_CVT	7
+#define	FPU_OP_C	8
+#define	FPU_OP_ABS	9
+#define	FPU_OP_NEG	10
+/*  TODO: CEIL.L, CEIL.W, FLOOR.L, FLOOR.W, RECIP, ROUND.L, ROUND.W, RSQRT  */
+
+
+/*
+ *  fpu_store_float_value():
+ *
+ *  Stores a float value (actually a double) in fmt format.
+ */
+static void fpu_store_float_value(int fr_flag, struct mips_coproc *cp, int fd,
+	double nf, int fmt, int nan)
+{
+	int ieee_fmt = mips_fmt_to_ieee_fmt[fmt];
+	uint64_t r = ieee_store_float_value(nf, ieee_fmt);
+
+	/*
+	 *  TODO: This is for 32-bit mode. It has to be updated later
+	 *        for 64-bit coprocessor functionality!
+	 */
+	if (fmt == COP1_FMT_D || fmt == COP1_FMT_L) {
+		if (fr_flag)
+			cp->reg[fd] = r;
+		else {
+			cp->reg[fd] = r & 0xffffffffULL;
+			cp->reg[(fd+1) & 31] = (r >> 32) & 0xffffffffULL;
+
+			if (cp->reg[fd] & 0x80000000ULL)
+				cp->reg[fd] |= 0xffffffff00000000ULL;
+			if (cp->reg[fd+1] & 0x80000000ULL)
+				cp->reg[fd+1] |= 0xffffffff00000000ULL;
+		}
+	} else {
+		cp->reg[fd] = r & 0xffffffffULL;
+
+		if (cp->reg[fd] & 0x80000000ULL)
+			cp->reg[fd] |= 0xffffffff00000000ULL;
+	}
+}
+
+
+/*
+ *  fpu_op():
+ *
+ *  Perform a floating-point operation. For those of fs and ft that are >= 0,
+ *  those numbers are interpreted into local variables.
+ *
+ *  Only FPU_OP_C (compare) returns anything of interest, 1 for true, 0 for
+ *  false.
+ */
+static int fpu_op(struct cpu *cpu, struct mips_coproc *cp, int op, int fmt,
+	int ft, int fs, int fd, int cond, int output_fmt)
+{
+	/*  Potentially two input registers, fs and ft  */
+	struct ieee_float_value float_value[2];
+	int unordered, nan, ieee_fmt = mips_fmt_to_ieee_fmt[fmt];
+	uint64_t fs_v = 0;
+	double nf;
+	int fr = cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & STATUS_FR ? 1 : 0;
+
+	// printf("op %x (fmt %i):\n", op, fmt);
+
+	if (fs >= 0) {
+		fs_v = cp->reg[fs];
+		if (fmt == COP1_FMT_D || fmt == COP1_FMT_L) {
+			if (!fr)
+				fs_v = (fs_v & 0xffffffffULL) +
+				    (cp->reg[(fs + 1) & 31] << 32);
+		}
+		// printf("    fs_v = 0x%016llx\n", (long long)fs_v);
+		ieee_interpret_float_value(fs_v, &float_value[0], ieee_fmt);
+	}
+	if (ft >= 0) {
+		uint64_t v = cp->reg[ft];
+		if (fmt == COP1_FMT_D || fmt == COP1_FMT_L) {
+			if (!fr)
+				v = (v & 0xffffffffULL) +
+				    (cp->reg[(ft + 1) & 31] << 32);
+		}
+		// printf("    ft_v = 0x%016llx\n", (long long)v);
+		ieee_interpret_float_value(v, &float_value[1], ieee_fmt);
+	}
+
+
+	switch (op) {
+	case FPU_OP_ADD:
+		nf = float_value[0].f + float_value[1].f;
+		/*  debug("  add: %f + %f = %f\n",
+		    float_value[0].f, float_value[1].f, nf);  */
+		fpu_store_float_value(fr, cp, fd, nf, output_fmt,
+		    float_value[0].nan || float_value[1].nan);
+		break;
+	case FPU_OP_SUB:
+		nf = float_value[0].f - float_value[1].f;
+		/*  debug("  sub: %f - %f = %f\n",
+		    float_value[0].f, float_value[1].f, nf);  */
+		fpu_store_float_value(fr, cp, fd, nf, output_fmt,
+		    float_value[0].nan || float_value[1].nan);
+		break;
+	case FPU_OP_MUL:
+		nf = float_value[0].f * float_value[1].f;
+		/*  debug("  mul: %f * %f = %f\n",
+		    float_value[0].f, float_value[1].f, nf);  */
+		fpu_store_float_value(fr, cp, fd, nf, output_fmt,
+		    float_value[0].nan || float_value[1].nan);
+		break;
+	case FPU_OP_DIV:
+		nan = float_value[0].nan || float_value[1].nan;
+		if (fabs(float_value[1].f) > 0.00000000001)
+			nf = float_value[0].f / float_value[1].f;
+		else {
+			fatal("DIV by zero !!!! TODO\n");
+			nf = 0.0;	/*  TODO  */
+			nan = 1;
+			// mips_cpu_exception(cpu, EXCEPTION_FPE, 0, 0, 1, 0, 0, 0);
+			return 0;
+		}
+		/*  debug("  div: %f / %f = %f\n",
+		    float_value[0].f, float_value[1].f, nf);  */
+		fpu_store_float_value(fr, cp, fd, nf, output_fmt, nan);
+		break;
+	case FPU_OP_SQRT:
+		nan = float_value[0].nan;
+		if (float_value[0].f >= 0.0)
+			nf = sqrt(float_value[0].f);
+		else {
+			fatal("SQRT by less than zero, %f !!!!\n",
+			    float_value[0].f);
+			nf = 0.0;	/*  TODO  */
+			nan = 1;
+		}
+		/*  debug("  sqrt: %f => %f\n", float_value[0].f, nf);  */
+		fpu_store_float_value(fr, cp, fd, nf, output_fmt, nan);
+		break;
+	case FPU_OP_ABS:
+		nf = fabs(float_value[0].f);
+		/*  debug("  abs: %f => %f\n", float_value[0].f, nf);  */
+		fpu_store_float_value(fr, cp, fd, nf, output_fmt,
+		    float_value[0].nan);
+		break;
+	case FPU_OP_NEG:
+		nf = - float_value[0].f;
+		/*  debug("  neg: %f => %f\n", float_value[0].f, nf);  */
+		fpu_store_float_value(fr, cp, fd, nf, output_fmt,
+		    float_value[0].nan);
+		break;
+	case FPU_OP_CVT:
+		nf = float_value[0].f;
+		/*  debug("  mov: %f => %f\n", float_value[0].f, nf);  */
+		fpu_store_float_value(fr, cp, fd, nf, output_fmt,
+		    float_value[0].nan);
+		break;
+	case FPU_OP_MOV:
+		/*  Non-arithmetic move:  */
+		/*
+		 *  TODO:  this is for 32-bit mode. It has to be updated later
+		 *		for 64-bit coprocessor stuff.
+		 */
+		if (output_fmt == COP1_FMT_D || output_fmt == COP1_FMT_L) {
+			if (fr)
+				cp->reg[fd] = fs_v;
+			else {
+				cp->reg[fd] = fs_v & 0xffffffffULL;
+				cp->reg[(fd+1) & 31] = (fs_v >> 32) & 0xffffffffULL;
+				if (cp->reg[fd] & 0x80000000ULL)
+					cp->reg[fd] |= 0xffffffff00000000ULL;
+				if (cp->reg[fd+1] & 0x80000000ULL)
+					cp->reg[fd+1] |= 0xffffffff00000000ULL;
+			}
+		} else {
+			cp->reg[fd] = fs_v & 0xffffffffULL;
+			if (cp->reg[fd] & 0x80000000ULL)
+				cp->reg[fd] |= 0xffffffff00000000ULL;
+		}
+		break;
+	case FPU_OP_C:
+		/*  debug("  c: cond=%i\n", cond);  */
+
+		unordered = 0;
+		if (float_value[0].nan || float_value[1].nan)
+			unordered = 1;
+
+		switch (cond) {
+		case 2:	/*  Equal  */
+			return (float_value[0].f == float_value[1].f);
+		case 4:	/*  Ordered or Less than  */
+			return (float_value[0].f < float_value[1].f)
+			    || !unordered;
+		case 5:	/*  Unordered or Less than  */
+			return (float_value[0].f < float_value[1].f)
+			    || unordered;
+		case 6:	/*  Ordered or Less than or Equal  */
+			return (float_value[0].f <= float_value[1].f)
+			    || !unordered;
+		case 7:	/*  Unordered or Less than or Equal  */
+			return (float_value[0].f <= float_value[1].f)
+			    || unordered;
+		case 12:/*  Less than  */
+			return (float_value[0].f < float_value[1].f);
+		case 14:/*  Less than or equal  */
+			return (float_value[0].f <= float_value[1].f);
+
+		/*  The following are not commonly used, so I'll move these out
+		    of the if-0 on a case-by-case basis.  */
+#if 0
+case 0:	return 0;					/*  False  */
+case 1:	return 0;					/*  Unordered  */
+case 3:	return (float_value[0].f == float_value[1].f);
+			/*  Unordered or Equal  */
+case 8:	return 0;				/*  Signaling false  */
+case 9:	return 0;	/*  Not Greater than or Less than or Equal  */
+case 10:return (float_value[0].f == float_value[1].f);	/*  Signaling Equal  */
+case 11:return (float_value[0].f == float_value[1].f);	/*  Not Greater
+		than or Less than  */
+case 13:return !(float_value[0].f >= float_value[1].f);	/*  Not greater
+		than or equal */
+case 15:return !(float_value[0].f > float_value[1].f);	/*  Not greater than  */
+#endif
+
+		default:
+			fatal("fpu_op(): unimplemented condition "
+			    "code %i. see cpu_mips_coproc.c\n", cond);
+		}
+		break;
+	default:
+		fatal("fpu_op(): unimplemented op %i\n", op);
+	}
+
+	return 0;
+}
+
+
+/*
+ *  fpu_function():
+ *
+ *  Returns 1 if function was implemented, 0 otherwise.
+ *  Debug trace should be printed for known instructions.
+ */
+static int fpu_function(struct cpu *cpu, struct mips_coproc *cp,
+	uint32_t function, int unassemble_only)
+{
+	int fd, fs, ft, fmt, cond, cc;
+
+	fmt = (function >> 21) & 31;
+	ft = (function >> 16) & 31;
+	fs = (function >> 11) & 31;
+	cc = (function >> 8) & 7;
+	fd = (function >> 6) & 31;
+	cond = (function >> 0) & 15;
+
+
+	/*  bc1f, bc1t, bc1fl, bc1tl:  */
+	if ((function & 0x03e00000) == 0x01000000) {
+		int nd, tf, imm;
+		const char *instr_mnem;
+
+		/*  cc are bits 20..18:  */
+		cc = (function >> 18) & 7;
+		nd = (function >> 17) & 1;
+		tf = (function >> 16) & 1;
+		imm = function & 65535;
+		if (imm >= 32768)
+			imm -= 65536;
+
+		instr_mnem = NULL;
+		if (nd == 0 && tf == 0)  instr_mnem = "bc1f";
+		if (nd == 0 && tf == 1)  instr_mnem = "bc1t";
+		if (nd == 1 && tf == 0)  instr_mnem = "bc1fl";
+		if (nd == 1 && tf == 1)  instr_mnem = "bc1tl";
+
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("%s\t%i,0x%016llx\n", instr_mnem, cc,
+			    (long long) (cpu->pc + 4 + (imm << 2)));
+		if (unassemble_only)
+			return 1;
+
+		fatal("INTERNAL ERROR: MIPS coprocessor branches should not"
+		    " be implemented in cpu_mips_coproc.c, but in"
+		    " cpu_mips_instr.c!\n");
+		exit(1);
+	}
+
+	/*  add.fmt: Floating-point add  */
+	if ((function & 0x0000003f) == 0x00000000) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("add.%s\tr%i,r%i,r%i\n",
+			    fmtname[fmt], fd, fs, ft);
+		if (unassemble_only)
+			return 1;
+
+		fpu_op(cpu, cp, FPU_OP_ADD, fmt, ft, fs, fd, -1, fmt);
+		return 1;
+	}
+
+	/*  sub.fmt: Floating-point subtract  */
+	if ((function & 0x0000003f) == 0x00000001) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("sub.%s\tr%i,r%i,r%i\n",
+			    fmtname[fmt], fd, fs, ft);
+		if (unassemble_only)
+			return 1;
+
+		fpu_op(cpu, cp, FPU_OP_SUB, fmt, ft, fs, fd, -1, fmt);
+		return 1;
+	}
+
+	/*  mul.fmt: Floating-point multiply  */
+	if ((function & 0x0000003f) == 0x00000002) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("mul.%s\tr%i,r%i,r%i\n",
+			    fmtname[fmt], fd, fs, ft);
+		if (unassemble_only)
+			return 1;
+
+		fpu_op(cpu, cp, FPU_OP_MUL, fmt, ft, fs, fd, -1, fmt);
+		return 1;
+	}
+
+	/*  div.fmt: Floating-point divide  */
+	if ((function & 0x0000003f) == 0x00000003) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("div.%s\tr%i,r%i,r%i\n",
+			    fmtname[fmt], fd, fs, ft);
+		if (unassemble_only)
+			return 1;
+
+		fpu_op(cpu, cp, FPU_OP_DIV, fmt, ft, fs, fd, -1, fmt);
+		return 1;
+	}
+
+	/*  sqrt.fmt: Floating-point square-root  */
+	if ((function & 0x001f003f) == 0x00000004) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("sqrt.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
+		if (unassemble_only)
+			return 1;
+
+		fpu_op(cpu, cp, FPU_OP_SQRT, fmt, -1, fs, fd, -1, fmt);
+		return 1;
+	}
+
+	/*  abs.fmt: Floating-point absolute value  */
+	if ((function & 0x001f003f) == 0x00000005) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("abs.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
+		if (unassemble_only)
+			return 1;
+
+		fpu_op(cpu, cp, FPU_OP_ABS, fmt, -1, fs, fd, -1, fmt);
+		return 1;
+	}
+
+	/*  mov.fmt: Floating-point (non-arithmetic) move  */
+	if ((function & 0x0000003f) == 0x00000006) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("mov.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
+		if (unassemble_only)
+			return 1;
+
+		fpu_op(cpu, cp, FPU_OP_MOV, fmt, -1, fs, fd, -1, fmt);
+		return 1;
+	}
+
+	/*  neg.fmt: Floating-point negate  */
+	if ((function & 0x001f003f) == 0x00000007) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("neg.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
+		if (unassemble_only)
+			return 1;
+
+		fpu_op(cpu, cp, FPU_OP_NEG, fmt, -1, fs, fd, -1, fmt);
+		return 1;
+	}
+
+	/*  trunc.l.fmt: Truncate  */
+	if ((function & 0x001f003f) == 0x00000009) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("trunc.l.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
+		if (unassemble_only)
+			return 1;
+
+		/*  TODO: not CVT?  */
+
+		fpu_op(cpu, cp, FPU_OP_CVT, fmt, -1, fs, fd, -1, COP1_FMT_L);
+		return 1;
+	}
+
+	/*  trunc.w.fmt: Truncate  */
+	if ((function & 0x001f003f) == 0x0000000d) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("trunc.w.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
+		if (unassemble_only)
+			return 1;
+
+		/*  TODO: not CVT?  */
+
+		fpu_op(cpu, cp, FPU_OP_CVT, fmt, -1, fs, fd, -1, COP1_FMT_W);
+		return 1;
+	}
+
+	/*  c.cond.fmt: Floating-point compare  */
+	if ((function & 0x000000f0) == 0x00000030) {
+		int cond_true;
+		int bit;
+
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("c.%s.%s\tcc%i,r%i,r%i\n", ccname[cond],
+			    fmtname[fmt], cc, fs, ft);
+		if (unassemble_only)
+			return 1;
+
+		cond_true = fpu_op(cpu, cp, FPU_OP_C, fmt,
+		    ft, fs, -1, cond, fmt);
+
+		/*
+		 *  Both the FCCR and FCSR contain condition code bits:
+		 *	FCCR:  bits 7..0
+		 *	FCSR:  bits 31..25 and 23
+		 */
+		cp->fcr[MIPS_FPU_FCCR] &= ~(1 << cc);
+		if (cond_true)
+			cp->fcr[MIPS_FPU_FCCR] |= (1 << cc);
+
+		if (cc == 0) {
+			bit = 1 << MIPS_FCSR_FCC0_SHIFT;
+			cp->fcr[MIPS_FPU_FCSR] &= ~bit;
+			if (cond_true)
+				cp->fcr[MIPS_FPU_FCSR] |= bit;
+		} else {
+			bit = 1 << (MIPS_FCSR_FCC1_SHIFT + cc-1);
+			cp->fcr[MIPS_FPU_FCSR] &= ~bit;
+			if (cond_true)
+				cp->fcr[MIPS_FPU_FCSR] |= bit;
+		}
+
+		return 1;
+	}
+
+	/*  cvt.s.fmt: Convert to single floating-point  */
+	if ((function & 0x001f003f) == 0x00000020) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("cvt.s.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
+		if (unassemble_only)
+			return 1;
+
+		fpu_op(cpu, cp, FPU_OP_CVT, fmt, -1, fs, fd, -1, COP1_FMT_S);
+		return 1;
+	}
+
+	/*  cvt.d.fmt: Convert to double floating-point  */
+	if ((function & 0x001f003f) == 0x00000021) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("cvt.d.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
+		if (unassemble_only)
+			return 1;
+
+		fpu_op(cpu, cp, FPU_OP_CVT, fmt, -1, fs, fd, -1, COP1_FMT_D);
+		return 1;
+	}
+
+	/*  cvt.w.fmt: Convert to word fixed-point  */
+	if ((function & 0x001f003f) == 0x00000024) {
+		if (cpu->machine->instruction_trace || unassemble_only)
+			debug("cvt.w.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
+		if (unassemble_only)
+			return 1;
+
+		fpu_op(cpu, cp, FPU_OP_CVT, fmt, -1, fs, fd, -1, COP1_FMT_W);
+		return 1;
+	}
+
+	return 0;
+}
+
+
+/*
+ *  coproc_tlbpr():
+ *
+ *  'tlbp' and 'tlbr'.
+ */
+void coproc_tlbpr(struct cpu *cpu, int readflag)
+{
+	struct mips_coproc *cp = cpu->cd.mips.coproc[0];
+	int i, found, g_bit;
+	uint64_t vpn2, xmask;
+
+	/*  Read:  */
+	if (readflag) {
+		if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
+			i = (cp->reg[COP0_INDEX] & R2K3K_INDEX_MASK) >>
+			    R2K3K_INDEX_SHIFT;
+			if (i >= cp->nr_of_tlbs) {
+				/*  TODO:  exception?  */
+				fatal("[ warning: tlbr from index %i (too "
+				    "high) ]\n", i);
+				return;
+			}
+
+			cp->reg[COP0_ENTRYHI]  = cp->tlbs[i].hi;
+			cp->reg[COP0_ENTRYLO0] = cp->tlbs[i].lo0;
+		} else {
+			/*  R4000:  */
+			i = cp->reg[COP0_INDEX] & INDEX_MASK;
+			if (i >= cp->nr_of_tlbs) {
+				/*  TODO:  exception?  */
+				fatal("[ warning: tlbr from index %i (too "
+				    "high) ]\n", i);
+				return;
+			}
+
+			cp->reg[COP0_PAGEMASK] = cp->tlbs[i].mask;
+			cp->reg[COP0_ENTRYHI]  = cp->tlbs[i].hi;
+			cp->reg[COP0_ENTRYLO1] = cp->tlbs[i].lo1;
+			cp->reg[COP0_ENTRYLO0] = cp->tlbs[i].lo0;
+
+			if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
+				/*  R4100 don't have the G bit in entryhi  */
+			} else {
+				/*  R4000 etc:  */
+				cp->reg[COP0_ENTRYHI] &= ~TLB_G;
+				g_bit = cp->tlbs[i].hi & TLB_G;
+
+				cp->reg[COP0_ENTRYLO0] &= ~ENTRYLO_G;
+				cp->reg[COP0_ENTRYLO1] &= ~ENTRYLO_G;
+				if (g_bit) {
+					cp->reg[COP0_ENTRYLO0] |= ENTRYLO_G;
+					cp->reg[COP0_ENTRYLO1] |= ENTRYLO_G;
+				}
+			}
+		}
+
+		return;
+	}
+
+	/*  Probe:  */
+	if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
+		vpn2 = cp->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_VPN_MASK;
+		found = -1;
+		for (i=0; i<cp->nr_of_tlbs; i++)
+			if ( ((cp->tlbs[i].hi & R2K3K_ENTRYHI_ASID_MASK) ==
+			    (cp->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_ASID_MASK))
+			    || cp->tlbs[i].lo0 & R2K3K_ENTRYLO_G)
+				if ((cp->tlbs[i].hi & R2K3K_ENTRYHI_VPN_MASK)
+				    == vpn2) {
+					found = i;
+					break;
+				}
+	} else {
+		/*  R4000 and R10000:  */
+		if (cpu->cd.mips.cpu_type.mmu_model == MMU10K)
+			xmask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K;
+		else if (cpu->cd.mips.cpu_type.rev == MIPS_R4100)
+			xmask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK | 0x1800;
+		else
+			xmask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK;
+		vpn2 = cp->reg[COP0_ENTRYHI] & xmask;
+
+		found = -1;
+		for (i=0; i<cp->nr_of_tlbs; i++) {
+			int gbit = cp->tlbs[i].hi & TLB_G;
+			if (cpu->cd.mips.cpu_type.rev == MIPS_R4100)
+				gbit = (cp->tlbs[i].lo0 & ENTRYLO_G) &&
+				    (cp->tlbs[i].lo1 & ENTRYLO_G);
+
+			if ( ((cp->tlbs[i].hi & ENTRYHI_ASID) ==
+			    (cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID)) || gbit) {
+				uint64_t a = vpn2 & ~cp->tlbs[i].mask;
+				uint64_t b = (cp->tlbs[i].hi & xmask) &
+				    ~cp->tlbs[i].mask;
+				if (a == b) {
+					found = i;
+					break;
+				}
+			}
+		}
+	}
+
+	if (found == -1)
+		cp->reg[COP0_INDEX] = INDEX_P;
+	else {
+		if (cpu->cd.mips.cpu_type.mmu_model == MMU3K)
+			cp->reg[COP0_INDEX] = found << R2K3K_INDEX_SHIFT;
+		else
+			cp->reg[COP0_INDEX] = found;
+	}
+
+	/*  Sign extend the index register:  */
+	if ((cp->reg[COP0_INDEX] >> 32) == 0 &&
+	    cp->reg[COP0_INDEX] & 0x80000000)
+		cp->reg[COP0_INDEX] |=
+		    0xffffffff00000000ULL;
+}
+
+
+/*
+ *  coproc_tlbwri():
+ *
+ *  MIPS TLB write random (tlbwr) and write indexed (tlbwi) instructions.
+ */
+void coproc_tlbwri(struct cpu *cpu, int randomflag)
+{
+	struct mips_coproc *cp = cpu->cd.mips.coproc[0];
+	int index, g_bit;
+	uint64_t oldvaddr;
+
+	if (randomflag) {
+		if (cpu->cd.mips.cpu_type.exc_model == EXC3K) {
+			index = ((cp->reg[COP0_RANDOM] & R2K3K_RANDOM_MASK)
+			    >> R2K3K_RANDOM_SHIFT) - 1;
+			/*  R3000 always has 8 wired entries:  */
+			if (index < 8)
+				index = cp->nr_of_tlbs - 1;
+			cp->reg[COP0_RANDOM] = index << R2K3K_RANDOM_SHIFT;
+		} else {
+			cp->reg[COP0_RANDOM] = cp->reg[COP0_WIRED] + (random()
+			    % (cp->nr_of_tlbs - cp->reg[COP0_WIRED]));
+			index = cp->reg[COP0_RANDOM] & RANDOM_MASK;
+		}
+	} else {
+		if (cpu->cd.mips.cpu_type.mmu_model == MMU3K)
+			index = (cp->reg[COP0_INDEX] & R2K3K_INDEX_MASK)
+			    >> R2K3K_INDEX_SHIFT;
+		else
+			index = cp->reg[COP0_INDEX] & INDEX_MASK;
+	}
+
+	if (index >= cp->nr_of_tlbs) {
+		fatal("warning: tlb index %i too high (max is %i)\n",
+		    index, cp->nr_of_tlbs - 1);
+		/*  TODO:  cause an exception?  */
+		return;
+	}
+
+
+#if 0
+	/*  Debug dump of the previous entry at that index:  */
+	fatal("{ old TLB entry at index %02x:", index);
+	if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
+		fatal(" hi=%08" PRIx32, (uint32_t)cp->tlbs[index].hi);
+		fatal(" lo=%08" PRIx32, (uint32_t)cp->tlbs[index].lo0);
+	} else {
+		if (cpu->is_32bit) {
+			fatal(" mask=%08" PRIx32,(uint32_t)cp->tlbs[index].mask);
+			fatal(" hi=%08" PRIx32, (uint32_t)cp->tlbs[index].hi);
+			fatal(" lo0=%08" PRIx32, (uint32_t)cp->tlbs[index].lo0);
+			fatal(" lo1=%08" PRIx32, (uint32_t)cp->tlbs[index].lo1);
+		} else {
+			fatal(" mask=%016" PRIx64, cp->tlbs[index].mask);
+			fatal(" hi=%016" PRIx64, cp->tlbs[index].hi);
+			fatal(" lo0=%016" PRIx64, cp->tlbs[index].lo0);
+			fatal(" lo1=%016" PRIx64, cp->tlbs[index].lo1);
+		}
+	}
+	fatal(" }\n");
+#endif
+
+	/*
+	 *  Any virtual address translation for the old TLB entry must be
+	 *  invalidated first:
+	 *
+	 *  (Only Valid entries need to be invalidated, and only those that
+	 *  are either Global, or have the same ASID as the new entry will
+	 *  have. No other address translations should be active anyway.)
+	 */
+
+	switch (cpu->cd.mips.cpu_type.mmu_model) {
+
+	case MMU3K:
+		oldvaddr = cp->tlbs[index].hi & R2K3K_ENTRYHI_VPN_MASK;
+		oldvaddr = (int32_t) oldvaddr;
+
+		if (cp->tlbs[index].lo0 & R2K3K_ENTRYLO_V &&
+		    (cp->tlbs[index].lo0 & R2K3K_ENTRYLO_G ||
+		    (cp->tlbs[index].hi & R2K3K_ENTRYHI_ASID_MASK) ==
+		    (cp->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_ASID_MASK) ))
+			cpu->invalidate_translation_caches(cpu, oldvaddr,
+			    INVALIDATE_VADDR);
+
+		break;
+
+	default:if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) {
+			oldvaddr = cp->tlbs[index].hi &
+			    (ENTRYHI_VPN2_MASK_R10K | ENTRYHI_R_MASK);
+		} else if (cpu->is_32bit) {
+			/*  MIPS32 etc.:  */
+			oldvaddr = cp->tlbs[index].hi & ENTRYHI_VPN2_MASK;
+			oldvaddr = (int32_t)oldvaddr;
+		} else {
+			/*  Assume MMU4K  */
+			oldvaddr = cp->tlbs[index].hi &
+			    (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK);
+		}
+
+		{
+			// This is the "dual page" mask:
+			uint64_t dpmask = cp->tlbs[index].mask;
+			if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
+				dpmask |= 0x07ff;
+			} else {
+				dpmask |= 0x1fff;
+			}
+
+			if (dpmask == 0x7ff) {
+				if (cp->tlbs[index].lo0 & ENTRYLO_V ||
+				    cp->tlbs[index].lo1 & ENTRYLO_V) {
+					fatal("1KB pages don't work with dyntrans.\n");
+					exit(1);
+				}
+			}
+
+			// Mask for bytes within a single page:
+			uint64_t mask = dpmask >> 1;
+
+			uint64_t pagesize = mask + 1;
+			
+			oldvaddr &= ~dpmask;
+
+			// printf("pagesize = %016llx mask = %016llx\n", pagesize, mask);
+			
+			if (cp->tlbs[index].lo0 & ENTRYLO_V)
+				for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
+					cpu->invalidate_translation_caches(cpu, oldvaddr + ofs, INVALIDATE_VADDR);
+			
+			if (cp->tlbs[index].lo1 & ENTRYLO_V)
+				for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
+					cpu->invalidate_translation_caches(cpu, oldvaddr + ofs + pagesize, INVALIDATE_VADDR);
+		}
+	}
+
+#if 0
+	/*
+	 *  Check for duplicate entries.  (There should not be two mappings
+	 *  from one virtual address to physical addresses.)
+	 *
+	 *  TODO: Do this for MMU3K and R4100 too.
+	 *
+	 *  TODO: Make this detection more robust.
+	 */
+	if (cpu->cd.mips.cpu_type.mmu_model != MMU3K &&
+	    cpu->cd.mips.cpu_type.rev != MIPS_R4100) {
+		uint64_t vaddr1, vaddr2;
+		int i;
+		unsigned int asid;
+
+		vaddr1 = cp->reg[COP0_ENTRYHI] &
+		    (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K);
+		asid = cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID;
+		/*  Since this is just a warning, it's probably not necessary
+		    to use R4000 masks etc.  */
+
+		for (i=0; i<cp->nr_of_tlbs; i++) {
+			if (i == index && !randomflag)
+				continue;
+
+			if (!(cp->tlbs[i].hi & TLB_G) &&
+			    (cp->tlbs[i].hi & ENTRYHI_ASID) != asid)
+				continue;
+
+			vaddr2 = cp->tlbs[i].hi &
+			    (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K);
+			if (vaddr1 == vaddr2 && ((cp->tlbs[i].lo0 &
+			    ENTRYLO_V) || (cp->tlbs[i].lo1 & ENTRYLO_V)))
+				fatal("\n[ WARNING! tlbw%s to index 0x%02x "
+				    "vaddr=0x%llx (asid 0x%02x) is already in"
+				    " the TLB (entry 0x%02x) ! ]\n\n",
+				    randomflag? "r" : "i", index,
+				    (long long)vaddr1, asid, i);
+		}
+	}
+#endif
+
+	/*  Write the new entry:  */
+
+	if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
+		uint32_t vaddr, paddr;
+		int wf = cp->reg[COP0_ENTRYLO0] & R2K3K_ENTRYLO_D? 1 : 0;
+
+		cp->tlbs[index].hi = cp->reg[COP0_ENTRYHI];
+		cp->tlbs[index].lo0 = cp->reg[COP0_ENTRYLO0];
+
+		vaddr =  cp->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_VPN_MASK;
+		paddr = cp->reg[COP0_ENTRYLO0] & R2K3K_ENTRYLO_PFN_MASK;
+
+		/*  Invalidate any code translation, if we are writing
+		    a Dirty page to the TLB:  */
+		if (wf) {
+			cpu->invalidate_code_translation(cpu, paddr,
+			    INVALIDATE_PADDR);
+		}
+
+		/*  Set new last_written_tlb_index hint:  */
+		cpu->cd.mips.last_written_tlb_index = index;
+
+		if (cp->reg[COP0_STATUS] & MIPS1_ISOL_CACHES) {
+			fatal("Wow! Interesting case; tlbw* while caches"
+			    " are isolated. TODO\n");
+			/*  Don't update the translation table in this
+			    case...  */
+			exit(1);
+		}
+
+		/*  If we have a memblock (host page) for the physical
+		    page, then add a translation for it immediately:  */
+		if (cp->reg[COP0_ENTRYLO0] & R2K3K_ENTRYLO_V) {
+		    	unsigned char *memblock = memory_paddr_to_hostaddr(cpu->mem, paddr, 0);
+			if (memblock != NULL)
+				cpu->update_translation_table(cpu, vaddr, memblock, wf, paddr);
+		}
+	} else {
+		/*  R4000, R10000, VR41xx etc.:  */
+		int wf0, wf1;
+		uint64_t vaddr0, vaddr1, ptmp, psize;
+
+		cp->tlbs[index].mask = cp->reg[COP0_PAGEMASK];
+		cp->tlbs[index].hi   = cp->reg[COP0_ENTRYHI];
+		cp->tlbs[index].lo1  = cp->reg[COP0_ENTRYLO1];
+		cp->tlbs[index].lo0  = cp->reg[COP0_ENTRYLO0];
+
+		wf0 = cp->tlbs[index].lo0 & ENTRYLO_D;
+		wf1 = cp->tlbs[index].lo1 & ENTRYLO_D;
+
+		// This is the "dual page" mask:
+		uint64_t dpmask = cp->reg[COP0_PAGEMASK];
+		if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
+			dpmask |= 0x07ff;
+		} else {
+			dpmask |= 0x1fff;
+		}
+
+		if (dpmask == 0x7ff) {
+			if (cp->tlbs[index].lo0 & ENTRYLO_V ||
+			    cp->tlbs[index].lo1 & ENTRYLO_V) {
+				fatal("1KB pages don't work with dyntrans.\n");
+				exit(1);
+			}
+		}
+
+		// Mask for bytes within a single page:
+		uint64_t mask = dpmask >> 1;
+
+		// printf("mask = %016llx\n", (long long)mask);
+
+		uint64_t pfn0 = (cp->tlbs[index].lo0 & ENTRYLO_PFN_MASK) >> ENTRYLO_PFN_SHIFT;
+		uint64_t pfn1 = (cp->tlbs[index].lo1 & ENTRYLO_PFN_MASK) >> ENTRYLO_PFN_SHIFT;
+
+		uint64_t paddr0, paddr1;
+
+		if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
+			paddr0 = (pfn0 << 10) & ~mask;
+			paddr1 = (pfn1 << 10) & ~mask;
+		} else {
+			paddr0 = (pfn0 << 12) & ~mask;
+			paddr1 = (pfn1 << 12) & ~mask;
+		}
+
+		if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) {
+			vaddr0 = cp->tlbs[index].hi & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K);
+		} else if (cpu->is_32bit) {
+			/*  MIPS32 etc.:  */
+			vaddr0 = cp->tlbs[index].hi & ENTRYHI_VPN2_MASK;
+			vaddr0 = (int32_t)vaddr0;
+		} else {
+			/*  Assume MMU4K  */
+			vaddr0 = cp->tlbs[index].hi & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK);
+		}
+
+		psize = mask + 1;
+
+		vaddr0 &= ~dpmask;
+		vaddr1 = vaddr0 | psize;
+
+		g_bit = (cp->reg[COP0_ENTRYLO0] & cp->reg[COP0_ENTRYLO1]) & ENTRYLO_G;
+
+		if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
+			/*  NOTE: The VR4131 (and possibly others) don't have
+			    a Global bit in entryhi  */
+			cp->tlbs[index].hi &= ~cp->reg[COP0_PAGEMASK];
+		} else {
+			cp->tlbs[index].lo0 &= ~ENTRYLO_G;
+			cp->tlbs[index].lo1 &= ~ENTRYLO_G;
+
+			cp->tlbs[index].hi &= ~TLB_G;
+			if (g_bit)
+				cp->tlbs[index].hi |= TLB_G;
+		}
+
+		/*
+		 *  Invalidate any code translations, if we are writing Dirty
+		 *  pages to the TLB:
+		 */
+
+		if (wf0) {
+			for (ptmp = 0; ptmp < psize; ptmp += 0x1000)
+				cpu->invalidate_code_translation(cpu,
+				    paddr0 + ptmp, INVALIDATE_PADDR);
+		}
+		if (wf1) {
+			for (ptmp = 0; ptmp < psize; ptmp += 0x1000)
+				cpu->invalidate_code_translation(cpu,
+				    paddr1 + ptmp, INVALIDATE_PADDR);
+		}
+
+		/*
+		 *  If we have a memblock (host page) for the physical page,
+		 *  then add a translation for it immediately, to save some
+		 *  time. (It would otherwise be added later on anyway,
+		 *  because of a translation miss.)
+		 *
+		 *  NOTE/TODO: This is only for 4KB pages so far. It would
+		 *             be too expensive to add e.g. 16MB pages like
+		 *             this.
+		 */
+		if (psize == 0x1000) {
+			if (cp->reg[COP0_ENTRYLO0] & ENTRYLO_V) {
+				unsigned char *memblock = memory_paddr_to_hostaddr(cpu->mem, paddr0, 0);
+				if (memblock != NULL)
+					cpu->update_translation_table(cpu, vaddr0, memblock, wf0, paddr0);
+			}
+			if (cp->reg[COP0_ENTRYLO1] & ENTRYLO_V) {
+				unsigned char *memblock = memory_paddr_to_hostaddr(cpu->mem, paddr1, 0);
+				if (memblock != NULL)
+					cpu->update_translation_table(cpu, vaddr1, memblock, wf1, paddr1);
+			}
+		}
+
+		/*  Set new last_written_tlb_index hint:  */
+		cpu->cd.mips.last_written_tlb_index = index;
+	}
+}
+
+
+/*
+ *  coproc_eret():
+ *
+ *  Return from exception. (R4000 etc.)
+ */
+void coproc_eret(struct cpu *cpu)
+{
+	if (cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & STATUS_ERL) {
+		cpu->pc = cpu->cd.mips.coproc[0]->reg[COP0_ERROREPC];
+		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_ERL;
+	} else {
+		cpu->pc = cpu->cd.mips.coproc[0]->reg[COP0_EPC];
+		cpu->delay_slot = 0;
+		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_EXL;
+	}
+
+	cpu->cd.mips.rmw = 0;	/*  the "LL bit"  */
+}
+
+
+/*
+ *  coproc_function():
+ *
+ *  Execute a coprocessor specific instruction. cp must be != NULL.
+ *  Debug trace should be printed for known instructions, if
+ *  unassemble_only is non-zero. (This will NOT execute the instruction.)
+ *
+ *  TODO:  This is a mess and should be restructured (again).
+ */
+void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr,
+	uint32_t function, int unassemble_only, int running)
+{
+	int co_bit, op, rt, rd, fs, copz;
+	uint64_t tmpvalue;
+
+	if (cp == NULL) {
+		if (unassemble_only) {
+			debug("cop%i\t0x%08x (coprocessor not available)\n",
+			    cpnr, (int)function);
+			return;
+		}
+		fatal("[ pc=0x%016llx cop%i\t0x%08x (coprocessor not "
+		    "available)\n", (long long)cpu->pc, cpnr, (int)function);
+		return;
+	}
+
+	/*  No FPU?  */
+	if (cpnr == 1 && (cpu->cd.mips.cpu_type.flags & NOFPU)) {
+		mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0, cpnr, 0, 0, 0);
+		return;
+	}
+
+	/*  For quick reference:  */
+	copz = (function >> 21) & 31;
+	rt = (function >> 16) & 31;
+	rd = (function >> 11) & 31;
+
+	if (cpnr < 2 && (((function & 0x03e007f8) == (COPz_MFCz << 21))
+	              || ((function & 0x03e007f8) == (COPz_DMFCz << 21)))) {
+		if (unassemble_only) {
+			debug("%s%i\t%s,", copz==COPz_DMFCz? "dmfc" : "mfc",
+			    cpnr, regnames[rt]);
+			if (cpnr == 0)
+				debug("%s", cop0_names[rd]);
+			else
+				debug("r%i", rd);
+			if (function & 7)
+				debug(",%i", (int)(function & 7));
+			debug("\n");
+			return;
+		}
+		coproc_register_read(cpu, cpu->cd.mips.coproc[cpnr],
+		    rd, &tmpvalue, function & 7);
+		cpu->cd.mips.gpr[rt] = tmpvalue;
+		if (copz == COPz_MFCz) {
+			/*  Sign-extend:  */
+			cpu->cd.mips.gpr[rt] &= 0xffffffffULL;
+			if (cpu->cd.mips.gpr[rt] & 0x80000000ULL)
+				cpu->cd.mips.gpr[rt] |= 0xffffffff00000000ULL;
+		}
+		return;
+	}
+
+	if (cpnr < 2 && (((function & 0x03e007f8) == (COPz_MTCz << 21))
+	              || ((function & 0x03e007f8) == (COPz_DMTCz << 21)))) {
+		tmpvalue = cpu->cd.mips.gpr[rt];
+		if (copz == COPz_MTCz) {
+			/*  Sign-extend:  */
+			tmpvalue &= 0xffffffffULL;
+			if (tmpvalue & 0x80000000ULL)
+				tmpvalue |= 0xffffffff00000000ULL;
+		}
+		if (unassemble_only) {
+			debug("%s%i\t%s,", copz==COPz_DMTCz? "dmtc" : "mtc",
+			    cpnr, regnames[rt]);
+			if (cpnr == 0)
+				debug("%s", cop0_names[rd]);
+			else
+				debug("r%i", rd);
+			if (function & 7)
+				debug(",%i", (int)(function & 7));
+			debug(" [%016llx]", (long long)tmpvalue);
+			debug("\n");
+			return;
+		}
+		coproc_register_write(cpu, cpu->cd.mips.coproc[cpnr], rd,
+		    &tmpvalue, copz == COPz_DMTCz, function & 7);
+		return;
+	}
+
+	if (cpnr <= 1 && (((function & 0x03e007ff) == (COPz_CFCz << 21))
+	              || ((function & 0x03e007ff) == (COPz_CTCz << 21)))) {
+		switch (copz) {
+		case COPz_CFCz:		/*  Copy from FPU control register  */
+			rt = (function >> 16) & 31;
+			fs = (function >> 11) & 31;
+			if (unassemble_only) {
+				debug("cfc%i\t%s,r%i\n", cpnr,
+				    regnames[rt], fs);
+				return;
+			}
+			cpu->cd.mips.gpr[rt] = (int32_t)cp->fcr[fs];
+			/*  TODO: implement delay for gpr[rt]
+			    (for MIPS I,II,III only)  */
+			return;
+		case COPz_CTCz:		/*  Copy to FPU control register  */
+			rt = (function >> 16) & 31;
+			fs = (function >> 11) & 31;
+			if (unassemble_only) {
+				debug("ctc%i\t%s,r%i\n", cpnr,
+				    regnames[rt], fs);
+				return;
+			}
+
+			switch (cpnr) {
+			case 0:	/*  System coprocessor  */
+				fatal("[ warning: unimplemented ctc%i, "
+				    "0x%08x -> ctl reg %i ]\n", cpnr,
+				    (int)cpu->cd.mips.gpr[rt], fs);
+				break;
+			case 1:	/*  FPU  */
+				if (fs == 0)
+					fatal("[ Attempt to write to FPU "
+					    "control register 0 (?) ]\n");
+				else {
+					uint64_t tmp = cpu->cd.mips.gpr[rt];
+					cp->fcr[fs] = tmp;
+
+					/*  TODO: writing to control register 31
+					    should cause exceptions, depending
+					    on status bits!  */
+
+					switch (fs) {
+					case MIPS_FPU_FCCR:
+						cp->fcr[MIPS_FPU_FCSR] =
+						    (cp->fcr[MIPS_FPU_FCSR] &
+						    0x017fffffULL) | ((tmp & 1)
+						    << MIPS_FCSR_FCC0_SHIFT)
+						    | (((tmp & 0xfe) >> 1) <<
+						    MIPS_FCSR_FCC1_SHIFT);
+						break;
+					case MIPS_FPU_FCSR:
+						cp->fcr[MIPS_FPU_FCCR] =
+						    (cp->fcr[MIPS_FPU_FCCR] &
+						    0xffffff00ULL) | ((tmp >>
+						    MIPS_FCSR_FCC0_SHIFT) & 1) |
+						    (((tmp >>
+						    MIPS_FCSR_FCC1_SHIFT)
+						    & 0x7f) << 1);
+						break;
+					default:
+						;
+					}
+				}
+				break;
+			}
+
+			/*  TODO: implement delay for gpr[rt]
+			    (for MIPS I,II,III only)  */
+			return;
+		default:
+			;
+		}
+	}
+
+	/*  Math (Floating point) coprocessor calls:  */
+	if (cpnr==1) {
+		if (fpu_function(cpu, cp, function, unassemble_only))
+			return;
+	}
+
+
+	/*  Ugly R5900 hacks:  */
+	if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
+		if ((function & 0xfffff) == COP0_EI) {
+			if (unassemble_only) {
+				debug("ei\n");
+				return;
+			}
+			cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |=
+			    R5900_STATUS_EIE;
+			return;
+		}
+
+		if ((function & 0xfffff) == COP0_DI) {
+			if (unassemble_only) {
+				debug("di\n");
+				return;
+			}
+			cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &=
+			    ~R5900_STATUS_EIE;
+			return;
+		}
+	}
+
+	co_bit = (function >> 25) & 1;
+
+	/*  TLB operations and other things:  */
+	if (cp->coproc_nr == 0) {
+		if (!unassemble_only) {
+			fatal("FATAL INTERNAL ERROR: Should be implemented"
+			    " with dyntrans instead.\n");
+			exit(1);
+		}
+
+		switch (co_bit) {
+		case 0:
+			if ((function & 0x03e0ffdf) == 0x01606000) {
+				debug("%ci", function & 0x20? 'e' : 'd');
+				if (rt != MIPS_GPR_ZERO)
+					debug("\t%s", regnames[rt]);
+				debug("\n");
+				return;
+			}
+			break;
+		case 1:
+			op = (function) & 0xff;
+			switch (op) {
+			case COP0_TLBR:		/*  Read indexed TLB entry  */
+				debug("tlbr\n");
+				return;
+			case COP0_TLBWI:	/*  Write indexed  */
+			case COP0_TLBWR:	/*  Write random  */
+				if (op == COP0_TLBWI)
+					debug("tlbwi");
+				else
+					debug("tlbwr");
+				if (!running) {
+					debug("\n");
+					return;
+				}
+				debug("\tindex=%08llx",
+				    (long long)cp->reg[COP0_INDEX]);
+				debug(", random=%08llx",
+				    (long long)cp->reg[COP0_RANDOM]);
+				debug(", mask=%016llx",
+				    (long long)cp->reg[COP0_PAGEMASK]);
+				debug(", hi=%016llx",
+				    (long long)cp->reg[COP0_ENTRYHI]);
+				debug(", lo0=%016llx",
+				    (long long)cp->reg[COP0_ENTRYLO0]);
+				debug(", lo1=%016llx\n",
+				    (long long)cp->reg[COP0_ENTRYLO1]);
+				return;
+			case COP0_TLBP:		/*  Probe TLB for
+						    matching entry  */
+				debug("tlbp\n");
+				return;
+			case COP0_RFE:		/*  R2000/R3000 only:
+						    Return from Exception  */
+				debug("rfe\n");
+				return;
+			case COP0_ERET:	/*  R4000: Return from exception  */
+				debug("eret\n");
+				return;
+			case COP0_DERET:
+				debug("deret\n");
+				return;
+			case COP0_WAIT:
+				{
+					int code = (function >> 6) & 0x7ffff;
+					debug("wait");
+					if (code > 0)
+						debug("\t0x%x", code);
+					debug("\n");
+				}
+				return;
+			case COP0_STANDBY:
+				debug("standby\n");
+				return;
+			case COP0_SUSPEND:
+				debug("suspend\n");
+				return;
+			case COP0_HIBERNATE:
+				debug("hibernate\n");
+				return;
+			default:
+				;
+			}
+			break;
+		}
+	}
+
+	/*  TODO: coprocessor R2020 on DECstation?  */
+	if ((cp->coproc_nr==0 || cp->coproc_nr==3) && function == 0x0100ffff) {
+		if (unassemble_only) {
+			debug("decstation_r2020_writeback\n");
+			return;
+		}
+		/*  TODO  */
+		return;
+	}
+
+	if (unassemble_only) {
+		debug("cop%i\t0x%08x (unimplemented)\n", cpnr, (int)function);
+		return;
+	}
+
+	fatal("cpu%i: UNIMPLEMENTED coproc%i function %08" PRIx32" "
+	    "(pc = %016" PRIx64")\n", cpu->cpu_id, cp->coproc_nr,
+	    (uint32_t)function, cpu->pc);
+
+	mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0, cp->coproc_nr, 0, 0, 0);
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_mips_coproc.cc gxemul-0.7.0+dfsg/src/cpus/cpu_mips_coproc.cc
--- gxemul-0.6.2/src/cpus/cpu_mips_coproc.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_mips_coproc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,2290 +0,0 @@
-/*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Emulation of MIPS coprocessors.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#include "cop0.h"
-#include "cpu.h"
-#include "cpu_mips.h"
-#include "emul.h"
-#include "float_emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "mips_cpu_types.h"
-#include "misc.h"
-#include "opcodes_mips.h"
-#include "timer.h"
-
-
-extern volatile int single_step;
-
-static const char *cop0_names[] = COP0_NAMES;
-static const char *regnames[] = MIPS_REGISTER_NAMES;
-
-
-/*
- *  initialize_cop0_config():
- *
- *  Helper function, called from mips_coproc_new().
- */
-static void initialize_cop0_config(struct cpu *cpu, struct mips_coproc *c)
-{
-	const int m16 = 0;	/*  TODO: MIPS16 support  */
-	int IB, DB, SB, IC, DC, SC, IA, DA;
-
-	/*  Generic case for MIPS32/64:  */
-	if (cpu->cd.mips.cpu_type.isa_level == 32 ||
-	    cpu->cd.mips.cpu_type.isa_level == 64) {
-		/*  According to the MIPS64 (5K) User's Manual:  */
-		c->reg[COP0_CONFIG] =
-		      (   (uint32_t)1 << 31)/*  Config 1 present bit  */
-		    | (   0 << 20)	/*  ISD:  instruction scheduling
-					    disable (=1)  */
-		    | (   0 << 17)	/*  DID:  dual issue disable  */
-		    | (   0 << 16)	/*  BM:   burst mode  */
-		    | ((cpu->byte_order == EMUL_BIG_ENDIAN? 1 : 0) << 15)
-				 	/*  endian mode  */
-		    | ((cpu->cd.mips.cpu_type.isa_level == 64? 2 : 0) << 13)
-					/*  0=MIPS32, 1=64S, 2=64  */
-		    | (   0 << 10)	/*  Architecture revision  */
-		    | (   1 <<  7)	/*  MMU type: 1=TLB, 3=FMT  */
-		    | (   2 <<  0)	/*  kseg0 cache coherency algorithm  */
-		    ;
-		/*  Config select 1: caches etc. TODO: Don't use
-			cpu->machine for this stuff!  */
-		IB = cpu->cd.mips.cache_picache_linesize - 1;
-		IB = IB < 0? 0 : (IB > 7? 7 : IB);
-		DB = cpu->cd.mips.cache_pdcache_linesize - 1;
-		DB = DB < 0? 0 : (DB > 7? 7 : DB);
-		IC = cpu->cd.mips.cache_picache -
-		    cpu->cd.mips.cache_picache_linesize - 7;
-		DC = cpu->cd.mips.cache_pdcache -
-		    cpu->cd.mips.cache_pdcache_linesize - 7;
-		IA = cpu->cd.mips.cpu_type.piways - 1;
-		DA = cpu->cd.mips.cpu_type.pdways - 1;
-		cpu->cd.mips.cop0_config_select1 =
-		    ((cpu->cd.mips.cpu_type.nr_of_tlb_entries - 1) << 25)
-		    | (IC << 22)	/*  IS: I-cache sets per way  */
-		    | (IB << 19)	/*  IL: I-cache line-size  */
-		    | (IA << 16)	/*  IA: I-cache assoc. (ways-1)  */
-		    | (DC << 13)	/*  DS: D-cache sets per way  */
-		    | (DB << 10)	/*  DL: D-cache line-size  */
-		    | (DA <<  7)	/*  DA: D-cache assoc. (ways-1)  */
-		    | (16 * 0)		/*  Existance of PerformanceCounters  */
-		    | ( 8 * 0)		/*  Existance of Watch Registers  */
-		    | ( 4 * m16)	/*  Existance of MIPS16  */
-		    | ( 2 * 0)		/*  Existance of EJTAG  */
-		    | ( 1 * 1)		/*  Existance of FPU  */
-		    ;
-
-		return;
-	}
-
-	switch (cpu->cd.mips.cpu_type.rev) {
-	case MIPS_R2000:
-	case MIPS_R3000:
-		/*  No config register.  */
-		break;
-	case MIPS_R4000:	/*  according to the R4000 manual  */
-	case MIPS_R4600:
-		IB = cpu->cd.mips.cache_picache_linesize - 4;
-		IB = IB < 0? 0 : (IB > 1? 1 : IB);
-		DB = cpu->cd.mips.cache_pdcache_linesize - 4;
-		DB = DB < 0? 0 : (DB > 1? 1 : DB);
-		SB = cpu->cd.mips.cache_secondary_linesize - 4;
-		SB = SB < 0? 0 : (SB > 3? 3 : SB);
-		IC = cpu->cd.mips.cache_picache - 12;
-		IC = IC < 0? 0 : (IC > 7? 7 : IC);
-		DC = cpu->cd.mips.cache_pdcache - 12;
-		DC = DC < 0? 0 : (DC > 7? 7 : DC);
-		SC = cpu->cd.mips.cache_secondary? 0 : 1;
-		c->reg[COP0_CONFIG] =
-		      (   0 << 31)	/*  Master/Checker present bit  */
-		    | (0x00 << 28)	/*  EC: system clock divisor,
-					    0x00 = '2'  */
-		    | (0x00 << 24)	/*  EP  */
-		    | (  SB << 22)	/*  SB  */
-		    | (0x00 << 21)	/*  SS: 0 = mixed i/d scache  */
-		    | (0x00 << 20)	/*  SW  */
-		    | (0x00 << 18)	/*  EW: 0=64-bit  */
-		    | (  SC << 17)	/*  SC: 0=secondary cache present,
-					    1=non-present  */
-		    | (0x00 << 16)	/*  SM: (todo)  */
-		    | ((cpu->byte_order==EMUL_BIG_ENDIAN? 1 : 0) << 15)
-				 	/*  endian mode  */
-		    | (0x01 << 14)	/*  ECC: 0=enabled, 1=disabled  */
-		    | (0x00 << 13)	/*  EB: (todo)  */
-		    | (0x00 << 12)	/*  0 (resered)  */
-		    | (  IC <<  9)	/*  IC: I-cache = 2^(12+IC) bytes
-					    (1 = 8KB, 4=64K)  */
-		    | (  DC <<  6)	/*  DC: D-cache = 2^(12+DC) bytes
-					    (1 = 8KB, 4=64K)  */
-		    | (  IB <<  5)	/*  IB: I-cache line size (0=16,
-					    1=32)  */
-		    | (  DB <<  4)	/*  DB: D-cache line size (0=16,
-					    1=32)  */
-		    | (   0 <<  3)	/*  CU: todo  */
-		    | (   0 <<  0)	/*  kseg0 coherency algorithm
-						(TODO)  */
-		    ;
-		break;
-	case MIPS_R4100:	/*  According to the VR4131 manual:  */
-		IB = cpu->cd.mips.cache_picache_linesize - 4;
-		IB = IB < 0? 0 : (IB > 1? 1 : IB);
-		DB = cpu->cd.mips.cache_pdcache_linesize - 4;
-		DB = DB < 0? 0 : (DB > 1? 1 : DB);
-		IC = cpu->cd.mips.cache_picache - 10;
-		IC = IC < 0? 0 : (IC > 7? 7 : IC);
-		DC = cpu->cd.mips.cache_pdcache - 10;
-		DC = DC < 0? 0 : (DC > 7? 7 : DC);
-		c->reg[COP0_CONFIG] =
-		      (   0 << 31)	/*  IS: Instruction Streaming bit  */
-		    | (0x01 << 28)	/*  EC: system clock divisor,
-					    0x01 = 2  */
-		    | (0x00 << 24)	/*  EP  */
-		    | (0x00 << 23)	/*  AD: Accelerate data mode
-					    (0=VR4000-compatible)  */
-		    | ( m16 << 20)	/*  M16: MIPS16 support  */
-		    | (   1 << 17)	/*  '1'  */
-		    | (0x00 << 16)	/*  BP: 'Branch forecast'
-					    (0 = enabled)  */
-		    | ((cpu->byte_order==EMUL_BIG_ENDIAN? 1 : 0) << 15)
-				 	/*  endian mode  */
-		    | (   2 << 13)	/*  '2' hardcoded on VR4131  */
-		    | (   1 << 12)	/*  CS: Cache size mode
-					    (1 on VR4131)  */
-		    | (  IC <<  9)	/*  IC: I-cache = 2^(10+IC) bytes
-					    (0 = 1KB, 4=16K)  */
-		    | (  DC <<  6)	/*  DC: D-cache = 2^(10+DC) bytes
-					    (0 = 1KB, 4=16K)  */
-		    | (  IB <<  5)	/*  IB: I-cache line size (0=16,
-					    1=32)  */
-		    | (  DB <<  4)	/*  DB: D-cache line size (0=16,
-					    1=32)  */
-		    | (   0 <<  0)	/*  kseg0 coherency algorithm (TODO)  */
-		    ;
-		break;
-	case MIPS_R5000:
-	case MIPS_RM5200:	/*  rm5200 is just a wild guess  */
-		/*  These are just guesses: (the comments are wrong) */
-		c->reg[COP0_CONFIG] =
-		      (   0 << 31)	/*  Master/Checker present bit  */
-		    | (0x00 << 28)	/*  EC: system clock divisor,
-					    0x00 = '2'  */
-		    | (0x00 << 24)	/*  EP  */
-		    | (0x00 << 22)	/*  SB  */
-		    | (0x00 << 21)	/*  SS  */
-		    | (0x00 << 20)	/*  SW  */
-		    | (0x00 << 18)	/*  EW: 0=64-bit  */
-		    | (0x01 << 17)	/*  SC: 0=secondary cache present,
-					    1=non-present  */
-		    | (0x00 << 16)	/*  SM: (todo)  */
-		    | ((cpu->byte_order==EMUL_BIG_ENDIAN? 1 : 0) << 15)
-				 	/*  endian mode  */
-		    | (0x01 << 14)	/*  ECC: 0=enabled, 1=disabled  */
-		    | (0x00 << 13)	/*  EB: (todo)  */
-		    | (0x00 << 12)	/*  0 (resered)  */
-		    | (   3 <<  9)	/*  IC: I-cache = 2^(12+IC) bytes
-					    (1 = 8KB, 4=64K)  */
-		    | (   3 <<  6)	/*  DC: D-cache = 2^(12+DC) bytes
-					    (1 = 8KB, 4=64K)  */
-		    | (   1 <<  5)	/*  IB: I-cache line size (0=16,
-					    1=32)  */
-		    | (   1 <<  4)	/*  DB: D-cache line size (0=16,
-					    1=32)  */
-		    | (   0 <<  3)	/*  CU: todo  */
-		    | (   2 <<  0)	/*  kseg0 coherency algorithm
-						(TODO)  */
-		    ;
-		break;
-	case MIPS_R10000:
-	case MIPS_R12000:
-	case MIPS_R14000:
-		IC = cpu->cd.mips.cache_picache - 12;
-		IC = IC < 0? 0 : (IC > 7? 7 : IC);
-		DC = cpu->cd.mips.cache_pdcache - 12;
-		DC = DC < 0? 0 : (DC > 7? 7 : DC);
-		SC = cpu->cd.mips.cache_secondary - 19;
-		SC = SC < 0? 0 : (SC > 7? 7 : SC);
-		/*  According to the R10000 User's Manual:  */
-		c->reg[COP0_CONFIG] =
-		      (  IC << 29)	/*  Primary instruction cache size
-					    (3 = 32KB)  */
-		    | (  DC << 26)	/*  Primary data cache size (3 =
-					    32KB)  */
-		    | (   0 << 19)	/*  SCClkDiv  */
-		    | (  SC << 16)	/*  SCSize, secondary cache size.
-					    0 = 512KB. powers of two  */
-		    | (   0 << 15)	/*  MemEnd  */
-		    | (   0 << 14)	/*  SCCorEn  */
-		    | (   1 << 13)	/*  SCBlkSize. 0=16 words,
-					    1=32 words  */
-		    | (   0 <<  9)	/*  SysClkDiv  */
-		    | (   0 <<  7)	/*  PrcReqMax  */
-		    | (   0 <<  6)	/*  PrcElmReq  */
-		    | (   0 <<  5)	/*  CohPrcReqTar  */
-		    | (   0 <<  3)	/*  Device number  */
-		    | (   2 <<  0)	/*  Cache coherency algorithm for
-					    kseg0  */
-		    ;
-		break;
-	case MIPS_R5900:
-		/*
-		 *  R5900 is supposed to have the following (according
-		 *  to NetBSD/playstation2):
-		 *	cpu0: 16KB/64B 2-way set-associative L1 Instruction
-		 *		cache, 48 TLB entries
-		 *	cpu0: 8KB/64B 2-way set-associative write-back L1
-		 *		Data cache
-		 *  The following settings are just guesses:
-		 *  (comments are incorrect)
-		 */
-		c->reg[COP0_CONFIG] =
-		      (   0 << 31)	/*  Master/Checker present bit  */
-		    | (0x00 << 28)	/*  EC: system clock divisor,
-					    0x00 = '2'  */
-		    | (0x00 << 24)	/*  EP  */
-		    | (0x00 << 22)	/*  SB  */
-		    | (0x00 << 21)	/*  SS  */
-		    | (0x00 << 20)	/*  SW  */
-		    | (0x00 << 18)	/*  EW: 0=64-bit  */
-		    | (0x01 << 17)	/*  SC: 0=secondary cache present,
-					    1=non-present  */
-		    | (0x00 << 16)	/*  SM: (todo)  */
-		    | ((cpu->byte_order==EMUL_BIG_ENDIAN? 1 : 0) << 15)
-				 	/*  endian mode  */
-		    | (0x01 << 14)	/*  ECC: 0=enabled, 1=disabled  */
-		    | (0x00 << 13)	/*  EB: (todo)  */
-		    | (0x00 << 12)	/*  0 (resered)  */
-		    | (   3 <<  9)	/*  IC: I-cache = 2^(12+IC) bytes
-					    (1 = 8KB, 4=64K)  */
-		    | (   3 <<  6)	/*  DC: D-cache = 2^(12+DC) bytes
-					    (1 = 8KB, 4=64K)  */
-		    | (   1 <<  5)	/*  IB: I-cache line size (0=16,
-					    1=32)  */
-		    | (   1 <<  4)	/*  DB: D-cache line size (0=16,
-					    1=32)  */
-		    | (   0 <<  3)	/*  CU: todo  */
-		    | (   0 <<  0)	/*  kseg0 coherency algorithm
-						(TODO)  */
-		    ;
-		break;
-	default:fatal("Internal error: No initialization code for"
-		    " config0? cpu rev = 0x%x", cpu->cd.mips.cpu_type.rev);
-		exit(1);
-	}
-}
-
-
-/*
- *  initialize_cop1():
- *
- *  Helper function, called from mips_coproc_new().
- */
-static void initialize_cop1(struct cpu *cpu, struct mips_coproc *c)
-{
-	int fpu_rev;
-	uint64_t other_stuff = 0;
-
-	switch (cpu->cd.mips.cpu_type.rev & 0xff) {
-	case MIPS_R2000:	fpu_rev = MIPS_R2010;	break;
-	case MIPS_R3000:	fpu_rev = MIPS_R3010;
-				other_stuff |= 0x40;	/*  or 0x30? TODO  */
-				break;
-	case MIPS_R6000:	fpu_rev = MIPS_R6010;	break;
-	case MIPS_R4000:	fpu_rev = MIPS_R4010;	break;
-	case MIPS_4Kc:		/*  TODO: Is this the same as 5Kc?  */
-	case MIPS_5Kc:		other_stuff = COP1_REVISION_DOUBLE
-				    | COP1_REVISION_SINGLE;
-	case MIPS_R5000:
-	case MIPS_RM5200:	fpu_rev = cpu->cd.mips.cpu_type.rev;
-				other_stuff |= 0x10;
-				/*  or cpu->cd.mips.cpu_type.sub ? TODO  */
-				break;
-	case MIPS_R10000:	fpu_rev = MIPS_R10000;	break;
-	case MIPS_R12000:	fpu_rev = 0x9;	break;
-	default:		fpu_rev = MIPS_SOFT;
-	}
-
-	c->fcr[COP1_REVISION] = (fpu_rev << 8) | other_stuff;
-
-#if 0
-	/*  These are mentioned in the MIPS64 documentation:  */
-	    + (1 << 16)		/*  single  */
-	    + (1 << 17)		/*  double  */
-	    + (1 << 18)		/*  paired-single  */
-	    + (1 << 19)		/*  3d  */
-#endif
-}
-
-
-/*
- *  mips_coproc_new():
- *
- *  Create a new MIPS coprocessor object.
- */
-struct mips_coproc *mips_coproc_new(struct cpu *cpu, int coproc_nr)
-{
-	struct mips_coproc *c;
-
-	CHECK_ALLOCATION(c = (struct mips_coproc *) malloc(sizeof(struct mips_coproc)));
-	memset(c, 0, sizeof(struct mips_coproc));
-
-	c->coproc_nr = coproc_nr;
-
-	if (coproc_nr == 0) {
-		c->nr_of_tlbs = cpu->cd.mips.cpu_type.nr_of_tlb_entries;
-		c->tlbs = (struct mips_tlb *) zeroed_alloc(c->nr_of_tlbs * sizeof(struct mips_tlb));
-
-		/*
-		 *  Start with nothing in the status register. This makes sure
-		 *  that we are running in kernel mode with all interrupts
-		 *  disabled.
-		 */
-		c->reg[COP0_STATUS] = 0;
-
-		/*  Hm. Enable coprocessors 0 and 1 even if we're not just
-		    emulating userland? TODO: Think about this.  */
-		/*  if (cpu->machine->prom_emulation)  */
-			c->reg[COP0_STATUS] |=
-			    ((uint32_t)0x3 << STATUS_CU_SHIFT);
-
-		if (!cpu->machine->prom_emulation)
-			c->reg[COP0_STATUS] |= STATUS_BEV;
-
-		/*  Ugly hack for R5900/TX79/C790:  */
-		if (cpu->cd.mips.cpu_type.rev == MIPS_R5900)
-			c->reg[COP0_STATUS] |= R5900_STATUS_EIE;
-
-		/*  Default pagesize = 4 KB  (i.e. dualpage = 8KB)  */
-		c->reg[COP0_PAGEMASK] = 0x1fff;
-
-		/*  Note: .rev may contain the company ID as well!  */
-		c->reg[COP0_PRID] =
-		      (0x00 << 24)			/*  Company Options  */
-		    | (0x00 << 16)			/*  Company ID       */
-		    | (cpu->cd.mips.cpu_type.rev <<  8)	/*  Processor ID     */
-		    | (cpu->cd.mips.cpu_type.sub)	/*  Revision         */
-		    ;
-
-		c->reg[COP0_WIRED] = 0;
-
-		initialize_cop0_config(cpu, c);
-
-		/*  Make sure the status register is sign-extended nicely:  */
-		c->reg[COP0_STATUS] = (int32_t)c->reg[COP0_STATUS];
-	}
-
-	if (coproc_nr == 1)
-		initialize_cop1(cpu, c);
-
-	return c;
-}
-
-
-/*
- *  mips_timer_tick():
- */
-static void mips_timer_tick(struct timer *timer, void *extra)
-{
-	struct cpu *cpu = (struct cpu *) extra;
-
-	cpu->cd.mips.compare_interrupts_pending ++;
-
-	if ((int32_t) (cpu->cd.mips.coproc[0]->reg[COP0_COUNT] -
-	    cpu->cd.mips.coproc[0]->reg[COP0_COMPARE]) < 0) {
-		cpu->cd.mips.coproc[0]->reg[COP0_COUNT] =
-		    cpu->cd.mips.coproc[0]->reg[COP0_COMPARE];
-	}
-}
-
-
-/*
- *  mips_coproc_tlb_set_entry():
- *
- *  Used by machine setup code, if a specific machine emulation starts up
- *  with hardcoded virtual to physical mappings.
- */
-void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size,
-	uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
-	int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
-	int cachealgo0, int cachealgo1)
-{
-	if (entrynr < 0 || entrynr >= cpu->cd.mips.coproc[0]->nr_of_tlbs) {
-		printf("mips_coproc_tlb_set_entry(): invalid entry nr: %i\n",
-		    entrynr);
-		exit(1);
-	}
-
-	switch (cpu->cd.mips.cpu_type.mmu_model) {
-	case MMU3K:
-		if (size != 4096) {
-			printf("mips_coproc_tlb_set_entry(): invalid pagesize "
-			    "(%i) for MMU3K\n", size);
-			exit(1);
-		}
-		cpu->cd.mips.coproc[0]->tlbs[entrynr].hi =
-		    (vaddr & R2K3K_ENTRYHI_VPN_MASK) |
-		    ((asid << R2K3K_ENTRYHI_ASID_SHIFT) & 
-		    R2K3K_ENTRYHI_ASID_MASK);
-		cpu->cd.mips.coproc[0]->tlbs[entrynr].lo0 =
-		    (paddr0 & R2K3K_ENTRYLO_PFN_MASK) |
-		    (cachealgo0? R2K3K_ENTRYLO_N : 0) |
-		    (dirty0? R2K3K_ENTRYLO_D : 0) |
-		    (valid0? R2K3K_ENTRYLO_V : 0) |
-		    (global? R2K3K_ENTRYLO_G : 0);
-		break;
-	default:
-		/*  MMU4K and MMU10K, etc:  */
-		if (cpu->cd.mips.cpu_type.mmu_model == MMU10K)
-			cpu->cd.mips.coproc[0]->tlbs[entrynr].hi =
-			    (vaddr & ENTRYHI_VPN2_MASK_R10K) |
-			    (vaddr & ENTRYHI_R_MASK) |
-			    (asid & ENTRYHI_ASID) |
-			    (global? TLB_G : 0);
-		else
-			cpu->cd.mips.coproc[0]->tlbs[entrynr].hi =
-			    (vaddr & ENTRYHI_VPN2_MASK) |
-			    (vaddr & ENTRYHI_R_MASK) |
-			    (asid & ENTRYHI_ASID) |
-			    (global? TLB_G : 0);
-		/*  NOTE: The pagemask size is for a "dual" page:  */
-		cpu->cd.mips.coproc[0]->tlbs[entrynr].mask =
-		    (2*size - 1) & ~0x1fff;
-		cpu->cd.mips.coproc[0]->tlbs[entrynr].lo0 =
-		    (((paddr0 >> 12) << ENTRYLO_PFN_SHIFT) &
-			ENTRYLO_PFN_MASK) |
-		    (dirty0? ENTRYLO_D : 0) |
-		    (valid0? ENTRYLO_V : 0) |
-		    (global? ENTRYLO_G : 0) |
-		    ((cachealgo0 << ENTRYLO_C_SHIFT) & ENTRYLO_C_MASK);
-		cpu->cd.mips.coproc[0]->tlbs[entrynr].lo1 =
-		    (((paddr1 >> 12) << ENTRYLO_PFN_SHIFT) &
-			ENTRYLO_PFN_MASK) |
-		    (dirty1? ENTRYLO_D : 0) |
-		    (valid1? ENTRYLO_V : 0) |
-		    (global? ENTRYLO_G : 0) |
-		    ((cachealgo1 << ENTRYLO_C_SHIFT) & ENTRYLO_C_MASK);
-		/*  TODO: R4100, 1KB pages etc  */
-	}
-}
-
-
-/*
- *  invalidate_asid():
- *
- *  Go through all entries in the TLB. If an entry has a matching asid, is
- *  valid, and is not global (i.e. the ASID matters), then its virtual address
- *  translation is invalidated.
- *
- *  Note: In the R3000 case, the asid argument is shifted 6 bits.
- */
-static void invalidate_asid(struct cpu *cpu, unsigned int asid)
-{
-	struct mips_coproc *cp = cpu->cd.mips.coproc[0];
-	unsigned int i, ntlbs = cp->nr_of_tlbs;
-	struct mips_tlb *tlb = cp->tlbs;
-
-	if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
-		for (i = 0; i < ntlbs; i++)
-			if ((tlb[i].hi & R2K3K_ENTRYHI_ASID_MASK) == asid
-			    && (tlb[i].lo0 & R2K3K_ENTRYLO_V)
-			    && !(tlb[i].lo0 & R2K3K_ENTRYLO_G)) {
-				cpu->invalidate_translation_caches(cpu,
-				    tlb[i].hi & R2K3K_ENTRYHI_VPN_MASK,
-				    INVALIDATE_VADDR);
-			}
-	} else {
-		for (i = 0; i < ntlbs; i++) {
-			if ((tlb[i].hi & ENTRYHI_ASID) != asid || (tlb[i].hi & TLB_G))
-				continue;
-
-			uint64_t mask = cp->tlbs[i].mask;
-			uint64_t pagesize = 0x1000;
-			uint64_t tmp = mask >> 13;
-			while ((tmp & 1)) {
-				tmp >>= 1;
-				pagesize <<= 1;
-			}
-			
-			uint64_t oldvaddr;
-
-			if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) {
-				oldvaddr = cp->tlbs[i].hi &
-					    (ENTRYHI_VPN2_MASK_R10K | ENTRYHI_R_MASK);
-			} else if (cpu->is_32bit) {
-				/*  MIPS32 etc.:  */
-				oldvaddr = cp->tlbs[i].hi & ENTRYHI_VPN2_MASK;
-				oldvaddr = (int32_t)oldvaddr;
-			} else {
-				/*  Assume MMU4K  */
-				oldvaddr = cp->tlbs[i].hi &
-				    (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK);
-			}
-
-			mask |= 0x1fff;
-			oldvaddr &= ~mask;
-
-			// printf("pagesize = %016llx mask = %016llx\n", pagesize, mask);
-			
-			if (cp->tlbs[i].lo0 & ENTRYLO_V)
-				for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
-					cpu->invalidate_translation_caches(cpu, oldvaddr + ofs, INVALIDATE_VADDR);
-			
-			if (cp->tlbs[i].lo1 & ENTRYLO_V)
-				for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
-					cpu->invalidate_translation_caches(cpu, oldvaddr + ofs + pagesize, INVALIDATE_VADDR);
-		}
-	}
-}
-
-
-/*
- *  coproc_register_read();
- *
- *  Read a value from a MIPS coprocessor register.
- */
-void coproc_register_read(struct cpu *cpu,
-	struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select)
-{
-	int unimpl = 1;
-
-	if (cp->coproc_nr==0 && reg_nr==COP0_INDEX)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_RANDOM)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_ENTRYLO0)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_ENTRYLO1)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_CONTEXT)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_PAGEMASK)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_WIRED)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_BADVADDR)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_COUNT) {
-		/*  TODO: Increase count in a more meaningful way!  */
-		cp->reg[COP0_COUNT] = (int32_t) (cp->reg[COP0_COUNT] + 1);
-		cpu->cd.mips.count_register_read_count ++;
-		unimpl = 0;
-	}
-	if (cp->coproc_nr==0 && reg_nr==COP0_ENTRYHI)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_COMPARE)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_STATUS)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_CAUSE)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_EPC)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_PRID)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_CONFIG) {
-		if (select > 0) {
-			switch (select) {
-			case 1:	*ptr = cpu->cd.mips.cop0_config_select1;
-				break;
-			default:fatal("coproc_register_read(): unimplemented"
-				    " config register select %i\n", select);
-				exit(1);
-			}
-			return;
-		}
-		unimpl = 0;
-	}
-	if (cp->coproc_nr==0 && reg_nr==COP0_LLADDR)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_WATCHLO)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_WATCHHI)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_XCONTEXT)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_ERRCTL)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_CACHEERR)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_TAGDATA_LO)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_TAGDATA_HI)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_ERROREPC)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_RESERV22) {
-		/*  Used by Linux on Linksys WRT54G  */
-		unimpl = 0;
-	}
-	if (cp->coproc_nr==0 && reg_nr==COP0_DEBUG)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_PERFCNT)	unimpl = 0;
-	if (cp->coproc_nr==0 && reg_nr==COP0_DESAVE)	unimpl = 0;
-
-	if (cp->coproc_nr==1)	unimpl = 0;
-
-	if (unimpl) {
-		fatal("cpu%i: warning: read from unimplemented coproc%i"
-		    " register %i (%s)\n", cpu->cpu_id, cp->coproc_nr, reg_nr,
-		    cp->coproc_nr==0? cop0_names[reg_nr] : "?");
-
-		mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0,
-		    cp->coproc_nr, 0, 0, 0);
-		return;
-	}
-
-	*ptr = cp->reg[reg_nr];
-}
-
-
-/*
- *  coproc_register_write();
- *
- *  Write a value to a MIPS coprocessor register.
- */
-void coproc_register_write(struct cpu *cpu,
-	struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64,
-	int select)
-{
-	int unimpl = 1;
-	int readonly = 0;
-	uint64_t tmp = *ptr;
-	uint64_t tmp2 = 0, old;
-	int inval = 0;
-	unsigned int old_asid;
-	uint64_t oldmode;
-
-	switch (cp->coproc_nr) {
-	case 0:
-		/*  COPROC 0:  */
-		switch (reg_nr) {
-		case COP0_INDEX:
-		case COP0_RANDOM:
-			unimpl = 0;
-			break;
-		case COP0_ENTRYLO0:
-			unimpl = 0;
-			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K &&
-			    (tmp & 0xff)!=0) {
-				/*  char *symbol;
-				    uint64_t offset;
-				    symbol = get_symbol_name(cpu->pc, &offset);
-				    fatal("YO! pc = 0x%08llx <%s> "
-				    "lo=%016llx\n", (long long)
-				    cpu->pc, symbol? symbol :
-				    "no symbol", (long long)tmp); */
-				tmp &= (R2K3K_ENTRYLO_PFN_MASK |
-				    R2K3K_ENTRYLO_N | R2K3K_ENTRYLO_D |
-				    R2K3K_ENTRYLO_V | R2K3K_ENTRYLO_G);
-			} else {
-				// Both MIPS III (such as R4000) and MIPS32/MIPS64 (?)
-				tmp &= (ENTRYLO_PFN_MASK | ENTRYLO_C_MASK |
-				    ENTRYLO_D | ENTRYLO_V | ENTRYLO_G);
-
-				int c = (tmp & ENTRYLO_C_MASK) >> ENTRYLO_C_SHIFT;
-				switch (c) {
-				case 2:	// Uncached
-				case 3:	// Cached
-					break;
-				default:if (tmp & ENTRYLO_V)
-						debug("[ MIPS coproc_register_write: unimplemented c = %i ]\n", c);
-				}
-			}
-			break;
-		case COP0_BADVADDR:
-			/*  Hm. Irix writes to this register. (Why?)  */
-			unimpl = 0;
-			break;
-		case COP0_ENTRYLO1:
-			unimpl = 0;
-			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
-				fatal("Attempt to access ENTRYLO1 with MMU3K?\n");
-				exit(1);
-			}
-			// Both MIPS III (such as R4000) and MIPS32/MIPS64 (?)
-			if (cpu->cd.mips.cpu_type.mmu_model != MMU3K) {
-				tmp &= (ENTRYLO_PFN_MASK | ENTRYLO_C_MASK |
-				    ENTRYLO_D | ENTRYLO_V | ENTRYLO_G);
-			}
-			break;
-		case COP0_CONTEXT:
-			old = cp->reg[COP0_CONTEXT];
-			cp->reg[COP0_CONTEXT] = tmp;
-			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
-				cp->reg[COP0_CONTEXT] &=
-				    ~R2K3K_CONTEXT_BADVPN_MASK;
-				cp->reg[COP0_CONTEXT] |=
-				    (old & R2K3K_CONTEXT_BADVPN_MASK);
-			} else if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
-				cp->reg[COP0_CONTEXT] &=
-				    ~CONTEXT_BADVPN2_MASK_R4100;
-				cp->reg[COP0_CONTEXT] |=
-				    (old & CONTEXT_BADVPN2_MASK_R4100);
-			} else {
-				cp->reg[COP0_CONTEXT] &=
-				    ~CONTEXT_BADVPN2_MASK;
-				cp->reg[COP0_CONTEXT] |=
-				    (old & CONTEXT_BADVPN2_MASK);
-			}
-			return;
-		case COP0_PAGEMASK:
-			tmp2 = tmp >> PAGEMASK_SHIFT;
-			if (cpu->cd.mips.cpu_type.rev != MIPS_R4100) {
-				if (tmp2 != 0x000 &&
-				    tmp2 != 0x003 &&
-				    tmp2 != 0x00f &&
-				    tmp2 != 0x03f &&
-				    tmp2 != 0x0ff &&
-				    tmp2 != 0x3ff &&
-				    tmp2 != 0xfff &&
-				    tmp2 != 0x3fff &&
-				    tmp2 != 0xffff)
-					fatal("[ cpu%i: trying to write an invalid"
-					    " pagemask 0x%08lx to COP0_PAGEMASK ]\n",
-					    cpu->cpu_id, (long)tmp);
-				// Actually just 0xfff << shift for R10000.
-				if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) {
-					tmp &= 0x0fff << PAGEMASK_SHIFT;
-				} else {
-					tmp &= 0xffff << PAGEMASK_SHIFT;
-				}
-			}
-			unimpl = 0;
-			break;
-		case COP0_WIRED:
-			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
-				fatal("[ cpu%i: r2k/r3k wired register must "
-				    "always be 8 ]\n", cpu->cpu_id);
-				tmp = 8;
-			}
-			cp->reg[COP0_RANDOM] = cp->nr_of_tlbs-1;
-			tmp &= INDEX_MASK;
-			unimpl = 0;
-			break;
-		case COP0_COUNT:
-			if (tmp != (uint64_t)(int64_t)(int32_t)tmp)
-				fatal("[ WARNING: trying to write a 64-bit value"
-				    " to the COUNT register! ]\n");
-			tmp = (int64_t)(int32_t)tmp;
-			unimpl = 0;
-			break;
-		case COP0_COMPARE:
-			if (cpu->machine->emulated_hz > 0) {
-				int32_t compare_diff = tmp -
-				    cp->reg[COP0_COMPARE];
-				double hz;
-
-				if (compare_diff < 0)
-					hz = tmp - cp->reg[COP0_COUNT];
-
-				if (compare_diff == 0)
-					hz = 0;
-				else
-					hz = (double)cpu->machine->emulated_hz
-					    / (double)compare_diff;
-
-				/*  Initialize or re-set the periodic timer:  */
-				if (hz > 0) {
-					if (cpu->cd.mips.timer == NULL)
-						cpu->cd.mips.timer = timer_add(
-						    hz, mips_timer_tick, cpu);
-					else
-						timer_update_frequency(
-						    cpu->cd.mips.timer, hz);
-				}
-			}
-
-			/*  Ack the periodic timer, if it was asserted:  */
-			if (cp->reg[COP0_CAUSE] & 0x8000 &&
-			    cpu->cd.mips.compare_interrupts_pending > 0)
-				cpu->cd.mips.compare_interrupts_pending --;
-
-			/*  Clear the timer interrupt assertion (bit 7):  */
-			cp->reg[COP0_CAUSE] &= ~0x8000;
-
-			if (tmp != (uint64_t)(int64_t)(int32_t)tmp)
-				fatal("[ WARNING: trying to write a 64-bit value"
-				    " to the COMPARE register! ]\n");
-
-			tmp = (int64_t)(int32_t)tmp;
-			cpu->cd.mips.compare_register_set = 1;
-			unimpl = 0;
-			break;
-		case COP0_ENTRYHI:
-			/*
-			 *  Translation caches must be invalidated if the
-			 *  ASID changes:
-			 */
-			switch (cpu->cd.mips.cpu_type.mmu_model) {
-			case MMU3K:
-				old_asid = cp->reg[COP0_ENTRYHI] &
-				    R2K3K_ENTRYHI_ASID_MASK;
-				if ((cp->reg[COP0_ENTRYHI] &
-				    R2K3K_ENTRYHI_ASID_MASK) !=
-				    (tmp & R2K3K_ENTRYHI_ASID_MASK))
-					inval = 1;
-				break;
-			default:
-				old_asid = cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID;
-				if ((cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID) !=
-				    (tmp & ENTRYHI_ASID))
-					inval = 1;
-				break;
-			}
-
-			if (inval)
-				invalidate_asid(cpu, old_asid);
-
-			unimpl = 0;
-			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K &&
-			    (tmp & 0x3f)!=0) {
-				/* char *symbol;
-				   uint64_t offset;
-				   symbol = get_symbol_name(cpu->pc,
-				    &offset);
-				   fatal("YO! pc = 0x%08llx <%s> "
-				    "hi=%016llx\n", (long long)cpu->pc,
-				    symbol? symbol :
-				    "no symbol", (long long)tmp);  */
-				tmp &= ~0x3f;
-			}
-			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K)
-				tmp &= (R2K3K_ENTRYHI_VPN_MASK |
-				    R2K3K_ENTRYHI_ASID_MASK);
-			else if (cpu->cd.mips.cpu_type.mmu_model == MMU10K)
-				tmp &= (ENTRYHI_R_MASK |
-				    ENTRYHI_VPN2_MASK_R10K | ENTRYHI_ASID);
-			else if (cpu->cd.mips.cpu_type.rev == MIPS_R4100)
-				tmp &= (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK |
-				    0x1800 | ENTRYHI_ASID);
-			else
-				tmp &= (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK |
-				    ENTRYHI_ASID);
-			break;
-		case COP0_EPC:
-			unimpl = 0;
-			break;
-		case COP0_PRID:
-			readonly = 1;
-			break;
-		case COP0_CONFIG:
-			if (select > 0) {
-				switch (select) {
-				case 1:	cpu->cd.mips.cop0_config_select1 = tmp;
-					break;
-				default:fatal("[ coproc_register_write(): unimpl"
-					    "emented config register select "
-					    "%i ]\n", select);
-					exit(1);
-				}
-				return;
-			}
-
-			/*  fatal("COP0_CONFIG: modifying K0 bits: "
-			    "0x%08x => ", cp->reg[reg_nr]);  */
-			tmp = *ptr;
-			tmp &= 0x3;	/*  only bits 2..0 can be written  */
-			cp->reg[reg_nr] &= ~(0x3);  cp->reg[reg_nr] |= tmp;
-			/*  fatal("0x%08x\n", cp->reg[reg_nr]);  */
-			return;
-		case COP0_STATUS:
-			oldmode = cp->reg[COP0_STATUS];
-			tmp &= ~(1 << 21);	/*  bit 21 is read-only  */
-
-			/*
-			 *  When switching between 32-bit and 64-bit address
-			 *  spaces, invalidate all translations.
-			 */
-			if (!cpu->is_32bit &&
-			    (oldmode & (STATUS_KX | STATUS_SX | STATUS_UX)) !=
-			    (tmp & (STATUS_KX | STATUS_SX | STATUS_UX)))
-				cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
-
-			/*
-			 *  When isolating caches, invalidate all translations.
-			 *  During the isolation, a special hack in memory_rw.c
-			 *  prevents translation tables from being updated, so
-			 *  the translation caches don't have to be invalidated
-			 *  when switching back to normal mode.
-			 */
-			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K &&
-			    (oldmode & MIPS1_ISOL_CACHES) !=
-			    (tmp & MIPS1_ISOL_CACHES)) {
-				/*  Invalidate everything if we are switching
-				    to isolated mode:  */
-				if (tmp & MIPS1_ISOL_CACHES) {
-					cpu->invalidate_translation_caches(
-					    cpu, 0, INVALIDATE_ALL);
-				}
-			}
-			unimpl = 0;
-			break;
-		case COP0_CAUSE:
-			/*  A write to the cause register only
-			    affects IM bits 0 and 1:  */
-			cp->reg[reg_nr] &= ~(0x3 << STATUS_IM_SHIFT);
-			cp->reg[reg_nr] |= (tmp & (0x3 << STATUS_IM_SHIFT));
-			return;
-		case COP0_FRAMEMASK:
-			/*  TODO: R10000  */
-			unimpl = 0;
-			break;
-		case COP0_TAGDATA_LO:
-		case COP0_TAGDATA_HI:
-			/*  TODO: R4300 and others?  */
-			unimpl = 0;
-			break;
-		case COP0_LLADDR:
-			unimpl = 0;
-			break;
-		case COP0_WATCHLO:
-		case COP0_WATCHHI:
-			unimpl = 0;
-			break;
-		case COP0_XCONTEXT:
-			/*
-			 *  TODO:  According to the R10000 manual, the R4400
-			 *  shares the PTEbase portion of the context registers
-			 *  (that is, xcontext and context). On R10000, they
-			 *  are separate registers.
-			 */
-			/*  debug("[ xcontext 0x%016llx ]\n", tmp);  */
-			unimpl = 0;
-			break;
-
-		/*  Most of these are actually TODOs:  */
-		case COP0_ERROREPC:
-		case COP0_DEPC:
-		case COP0_RESERV22:	/*  Used by Linux on Linksys WRT54G  */
-		case COP0_DESAVE:
-		case COP0_PERFCNT:
-		case COP0_ERRCTL:	/*  R10000  */
-			unimpl = 0;
-			break;
-		}
-		break;
-
-	case 1:
-		/*  COPROC 1:  */
-		unimpl = 0;
-		break;
-	}
-
-	if (unimpl) {
-		fatal("[ cpu%i: warning: write to unimplemented coproc%i "
-		    "register %i (%s), data = 0x%016llx ]\n", cpu->cpu_id,
-		    cp->coproc_nr, reg_nr, cp->coproc_nr==0?
-		    cop0_names[reg_nr] : "?", (long long)tmp);
-
-		/*  mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0,
-		    cp->coproc_nr, 0, 0, 0);
-		return;  */
-	}
-
-	if (readonly) {
-		fatal("[ cpu%i: warning: write to READONLY coproc%i register "
-		    "%i ignored ]\n", cpu->cpu_id, cp->coproc_nr, reg_nr);
-		return;
-	}
-
-	cp->reg[reg_nr] = tmp;
-
-	if (!flag64)
-		cp->reg[reg_nr] = (int64_t)(int32_t)cp->reg[reg_nr];
-}
-
-
-/*
- *  MIPS floating-point stuff:
- *
- *  TODO:  Move this to some other file?
- */
-static int mips_fmt_to_ieee_fmt[32] = {
-	0, 0, 0, 0,  0, 0, 0, 0,
-	0, 0, 0, 0,  0, 0, 0, 0,
-	IEEE_FMT_S, IEEE_FMT_D, 0, 0,
-	IEEE_FMT_W, IEEE_FMT_L, /* PS (Paired Single) */ 0, 0,
-	0, 0, 0, 0,  0, 0, 0, 0  };
-
-static const char *fmtname[32] = {
-	 "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
-	 "8",  "9", "10", "11", "12", "13", "14", "15",
-	 "s",  "d", "18", "19",  "w",  "l", "ps", "23",
-	"24", "25", "26", "27", "28", "29", "30", "31" 	};
-
-static const char *ccname[16] = {
-	"f",  "un",   "eq",  "ueq", "olt", "ult", "ole", "ule",
-	"sf", "ngle", "seq", "ngl", "lt",  "nge", "le",  "ngt"  };
-
-#define	FPU_OP_ADD	1
-#define	FPU_OP_SUB	2
-#define	FPU_OP_MUL	3
-#define	FPU_OP_DIV	4
-#define	FPU_OP_SQRT	5
-#define	FPU_OP_MOV	6
-#define	FPU_OP_CVT	7
-#define	FPU_OP_C	8
-#define	FPU_OP_ABS	9
-#define	FPU_OP_NEG	10
-/*  TODO: CEIL.L, CEIL.W, FLOOR.L, FLOOR.W, RECIP, ROUND.L, ROUND.W, RSQRT  */
-
-
-/*
- *  fpu_store_float_value():
- *
- *  Stores a float value (actually a double) in fmt format.
- */
-static void fpu_store_float_value(bool fr, struct mips_coproc *cp, int fd,
-	double nf, int fmt, int nan)
-{
-	int ieee_fmt = mips_fmt_to_ieee_fmt[fmt];
-	uint64_t r = ieee_store_float_value(nf, ieee_fmt);
-
-	/*
-	 *  TODO: This is for 32-bit mode. It has to be updated later
-	 *        for 64-bit coprocessor functionality!
-	 */
-	if (fmt == COP1_FMT_D || fmt == COP1_FMT_L) {
-		if (fr)
-			cp->reg[fd] = r;
-		else {
-			cp->reg[fd] = r & 0xffffffffULL;
-			cp->reg[(fd+1) & 31] = (r >> 32) & 0xffffffffULL;
-
-			if (cp->reg[fd] & 0x80000000ULL)
-				cp->reg[fd] |= 0xffffffff00000000ULL;
-			if (cp->reg[fd+1] & 0x80000000ULL)
-				cp->reg[fd+1] |= 0xffffffff00000000ULL;
-		}
-	} else {
-		cp->reg[fd] = r & 0xffffffffULL;
-
-		if (cp->reg[fd] & 0x80000000ULL)
-			cp->reg[fd] |= 0xffffffff00000000ULL;
-	}
-}
-
-
-/*
- *  fpu_op():
- *
- *  Perform a floating-point operation. For those of fs and ft that are >= 0,
- *  those numbers are interpreted into local variables.
- *
- *  Only FPU_OP_C (compare) returns anything of interest, 1 for true, 0 for
- *  false.
- */
-static int fpu_op(struct cpu *cpu, struct mips_coproc *cp, int op, int fmt,
-	int ft, int fs, int fd, int cond, int output_fmt)
-{
-	/*  Potentially two input registers, fs and ft  */
-	struct ieee_float_value float_value[2];
-	int unordered, nan, ieee_fmt = mips_fmt_to_ieee_fmt[fmt];
-	uint64_t fs_v = 0;
-	double nf;
-	bool fr = cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & STATUS_FR ? true : false;
-
-	// printf("op %x (fmt %i):\n", op, fmt);
-
-	if (fs >= 0) {
-		fs_v = cp->reg[fs];
-		if (fmt == COP1_FMT_D || fmt == COP1_FMT_L) {
-			if (!fr)
-				fs_v = (fs_v & 0xffffffffULL) +
-				    (cp->reg[(fs + 1) & 31] << 32);
-		}
-		// printf("    fs_v = 0x%016llx\n", (long long)fs_v);
-		ieee_interpret_float_value(fs_v, &float_value[0], ieee_fmt);
-	}
-	if (ft >= 0) {
-		uint64_t v = cp->reg[ft];
-		if (fmt == COP1_FMT_D || fmt == COP1_FMT_L) {
-			if (!fr)
-				v = (v & 0xffffffffULL) +
-				    (cp->reg[(ft + 1) & 31] << 32);
-		}
-		// printf("    ft_v = 0x%016llx\n", (long long)v);
-		ieee_interpret_float_value(v, &float_value[1], ieee_fmt);
-	}
-
-
-	switch (op) {
-	case FPU_OP_ADD:
-		nf = float_value[0].f + float_value[1].f;
-		/*  debug("  add: %f + %f = %f\n",
-		    float_value[0].f, float_value[1].f, nf);  */
-		fpu_store_float_value(fr, cp, fd, nf, output_fmt,
-		    float_value[0].nan || float_value[1].nan);
-		break;
-	case FPU_OP_SUB:
-		nf = float_value[0].f - float_value[1].f;
-		/*  debug("  sub: %f - %f = %f\n",
-		    float_value[0].f, float_value[1].f, nf);  */
-		fpu_store_float_value(fr, cp, fd, nf, output_fmt,
-		    float_value[0].nan || float_value[1].nan);
-		break;
-	case FPU_OP_MUL:
-		nf = float_value[0].f * float_value[1].f;
-		/*  debug("  mul: %f * %f = %f\n",
-		    float_value[0].f, float_value[1].f, nf);  */
-		fpu_store_float_value(fr, cp, fd, nf, output_fmt,
-		    float_value[0].nan || float_value[1].nan);
-		break;
-	case FPU_OP_DIV:
-		nan = float_value[0].nan || float_value[1].nan;
-		if (fabs(float_value[1].f) > 0.00000000001)
-			nf = float_value[0].f / float_value[1].f;
-		else {
-			fatal("DIV by zero !!!! TODO\n");
-			nf = 0.0;	/*  TODO  */
-			nan = 1;
-			// mips_cpu_exception(cpu, EXCEPTION_FPE, 0, 0, 1, 0, 0, 0);
-			return 0;
-		}
-		/*  debug("  div: %f / %f = %f\n",
-		    float_value[0].f, float_value[1].f, nf);  */
-		fpu_store_float_value(fr, cp, fd, nf, output_fmt, nan);
-		break;
-	case FPU_OP_SQRT:
-		nan = float_value[0].nan;
-		if (float_value[0].f >= 0.0)
-			nf = sqrt(float_value[0].f);
-		else {
-			fatal("SQRT by less than zero, %f !!!!\n",
-			    float_value[0].f);
-			nf = 0.0;	/*  TODO  */
-			nan = 1;
-		}
-		/*  debug("  sqrt: %f => %f\n", float_value[0].f, nf);  */
-		fpu_store_float_value(fr, cp, fd, nf, output_fmt, nan);
-		break;
-	case FPU_OP_ABS:
-		nf = fabs(float_value[0].f);
-		/*  debug("  abs: %f => %f\n", float_value[0].f, nf);  */
-		fpu_store_float_value(fr, cp, fd, nf, output_fmt,
-		    float_value[0].nan);
-		break;
-	case FPU_OP_NEG:
-		nf = - float_value[0].f;
-		/*  debug("  neg: %f => %f\n", float_value[0].f, nf);  */
-		fpu_store_float_value(fr, cp, fd, nf, output_fmt,
-		    float_value[0].nan);
-		break;
-	case FPU_OP_CVT:
-		nf = float_value[0].f;
-		/*  debug("  mov: %f => %f\n", float_value[0].f, nf);  */
-		fpu_store_float_value(fr, cp, fd, nf, output_fmt,
-		    float_value[0].nan);
-		break;
-	case FPU_OP_MOV:
-		/*  Non-arithmetic move:  */
-		/*
-		 *  TODO:  this is for 32-bit mode. It has to be updated later
-		 *		for 64-bit coprocessor stuff.
-		 */
-		if (output_fmt == COP1_FMT_D || output_fmt == COP1_FMT_L) {
-			if (fr)
-				cp->reg[fd] = fs_v;
-			else {
-				cp->reg[fd] = fs_v & 0xffffffffULL;
-				cp->reg[(fd+1) & 31] = (fs_v >> 32) & 0xffffffffULL;
-				if (cp->reg[fd] & 0x80000000ULL)
-					cp->reg[fd] |= 0xffffffff00000000ULL;
-				if (cp->reg[fd+1] & 0x80000000ULL)
-					cp->reg[fd+1] |= 0xffffffff00000000ULL;
-			}
-		} else {
-			cp->reg[fd] = fs_v & 0xffffffffULL;
-			if (cp->reg[fd] & 0x80000000ULL)
-				cp->reg[fd] |= 0xffffffff00000000ULL;
-		}
-		break;
-	case FPU_OP_C:
-		/*  debug("  c: cond=%i\n", cond);  */
-
-		unordered = 0;
-		if (float_value[0].nan || float_value[1].nan)
-			unordered = 1;
-
-		switch (cond) {
-		case 2:	/*  Equal  */
-			return (float_value[0].f == float_value[1].f);
-		case 4:	/*  Ordered or Less than  */
-			return (float_value[0].f < float_value[1].f)
-			    || !unordered;
-		case 5:	/*  Unordered or Less than  */
-			return (float_value[0].f < float_value[1].f)
-			    || unordered;
-		case 6:	/*  Ordered or Less than or Equal  */
-			return (float_value[0].f <= float_value[1].f)
-			    || !unordered;
-		case 7:	/*  Unordered or Less than or Equal  */
-			return (float_value[0].f <= float_value[1].f)
-			    || unordered;
-		case 12:/*  Less than  */
-			return (float_value[0].f < float_value[1].f);
-		case 14:/*  Less than or equal  */
-			return (float_value[0].f <= float_value[1].f);
-
-		/*  The following are not commonly used, so I'll move these out
-		    of the if-0 on a case-by-case basis.  */
-#if 0
-case 0:	return 0;					/*  False  */
-case 1:	return 0;					/*  Unordered  */
-case 3:	return (float_value[0].f == float_value[1].f);
-			/*  Unordered or Equal  */
-case 8:	return 0;				/*  Signaling false  */
-case 9:	return 0;	/*  Not Greater than or Less than or Equal  */
-case 10:return (float_value[0].f == float_value[1].f);	/*  Signaling Equal  */
-case 11:return (float_value[0].f == float_value[1].f);	/*  Not Greater
-		than or Less than  */
-case 13:return !(float_value[0].f >= float_value[1].f);	/*  Not greater
-		than or equal */
-case 15:return !(float_value[0].f > float_value[1].f);	/*  Not greater than  */
-#endif
-
-		default:
-			fatal("fpu_op(): unimplemented condition "
-			    "code %i. see cpu_mips_coproc.c\n", cond);
-		}
-		break;
-	default:
-		fatal("fpu_op(): unimplemented op %i\n", op);
-	}
-
-	return 0;
-}
-
-
-/*
- *  fpu_function():
- *
- *  Returns 1 if function was implemented, 0 otherwise.
- *  Debug trace should be printed for known instructions.
- */
-static int fpu_function(struct cpu *cpu, struct mips_coproc *cp,
-	uint32_t function, int unassemble_only)
-{
-	int fd, fs, ft, fmt, cond, cc;
-
-	fmt = (function >> 21) & 31;
-	ft = (function >> 16) & 31;
-	fs = (function >> 11) & 31;
-	cc = (function >> 8) & 7;
-	fd = (function >> 6) & 31;
-	cond = (function >> 0) & 15;
-
-
-	/*  bc1f, bc1t, bc1fl, bc1tl:  */
-	if ((function & 0x03e00000) == 0x01000000) {
-		int nd, tf, imm;
-		const char *instr_mnem;
-
-		/*  cc are bits 20..18:  */
-		cc = (function >> 18) & 7;
-		nd = (function >> 17) & 1;
-		tf = (function >> 16) & 1;
-		imm = function & 65535;
-		if (imm >= 32768)
-			imm -= 65536;
-
-		instr_mnem = NULL;
-		if (nd == 0 && tf == 0)  instr_mnem = "bc1f";
-		if (nd == 0 && tf == 1)  instr_mnem = "bc1t";
-		if (nd == 1 && tf == 0)  instr_mnem = "bc1fl";
-		if (nd == 1 && tf == 1)  instr_mnem = "bc1tl";
-
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("%s\t%i,0x%016llx\n", instr_mnem, cc,
-			    (long long) (cpu->pc + 4 + (imm << 2)));
-		if (unassemble_only)
-			return 1;
-
-		fatal("INTERNAL ERROR: MIPS coprocessor branches should not"
-		    " be implemented in cpu_mips_coproc.c, but in"
-		    " cpu_mips_instr.c!\n");
-		exit(1);
-	}
-
-	/*  add.fmt: Floating-point add  */
-	if ((function & 0x0000003f) == 0x00000000) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("add.%s\tr%i,r%i,r%i\n",
-			    fmtname[fmt], fd, fs, ft);
-		if (unassemble_only)
-			return 1;
-
-		fpu_op(cpu, cp, FPU_OP_ADD, fmt, ft, fs, fd, -1, fmt);
-		return 1;
-	}
-
-	/*  sub.fmt: Floating-point subtract  */
-	if ((function & 0x0000003f) == 0x00000001) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("sub.%s\tr%i,r%i,r%i\n",
-			    fmtname[fmt], fd, fs, ft);
-		if (unassemble_only)
-			return 1;
-
-		fpu_op(cpu, cp, FPU_OP_SUB, fmt, ft, fs, fd, -1, fmt);
-		return 1;
-	}
-
-	/*  mul.fmt: Floating-point multiply  */
-	if ((function & 0x0000003f) == 0x00000002) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("mul.%s\tr%i,r%i,r%i\n",
-			    fmtname[fmt], fd, fs, ft);
-		if (unassemble_only)
-			return 1;
-
-		fpu_op(cpu, cp, FPU_OP_MUL, fmt, ft, fs, fd, -1, fmt);
-		return 1;
-	}
-
-	/*  div.fmt: Floating-point divide  */
-	if ((function & 0x0000003f) == 0x00000003) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("div.%s\tr%i,r%i,r%i\n",
-			    fmtname[fmt], fd, fs, ft);
-		if (unassemble_only)
-			return 1;
-
-		fpu_op(cpu, cp, FPU_OP_DIV, fmt, ft, fs, fd, -1, fmt);
-		return 1;
-	}
-
-	/*  sqrt.fmt: Floating-point square-root  */
-	if ((function & 0x001f003f) == 0x00000004) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("sqrt.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
-		if (unassemble_only)
-			return 1;
-
-		fpu_op(cpu, cp, FPU_OP_SQRT, fmt, -1, fs, fd, -1, fmt);
-		return 1;
-	}
-
-	/*  abs.fmt: Floating-point absolute value  */
-	if ((function & 0x001f003f) == 0x00000005) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("abs.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
-		if (unassemble_only)
-			return 1;
-
-		fpu_op(cpu, cp, FPU_OP_ABS, fmt, -1, fs, fd, -1, fmt);
-		return 1;
-	}
-
-	/*  mov.fmt: Floating-point (non-arithmetic) move  */
-	if ((function & 0x0000003f) == 0x00000006) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("mov.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
-		if (unassemble_only)
-			return 1;
-
-		fpu_op(cpu, cp, FPU_OP_MOV, fmt, -1, fs, fd, -1, fmt);
-		return 1;
-	}
-
-	/*  neg.fmt: Floating-point negate  */
-	if ((function & 0x001f003f) == 0x00000007) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("neg.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
-		if (unassemble_only)
-			return 1;
-
-		fpu_op(cpu, cp, FPU_OP_NEG, fmt, -1, fs, fd, -1, fmt);
-		return 1;
-	}
-
-	/*  trunc.l.fmt: Truncate  */
-	if ((function & 0x001f003f) == 0x00000009) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("trunc.l.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
-		if (unassemble_only)
-			return 1;
-
-		/*  TODO: not CVT?  */
-
-		fpu_op(cpu, cp, FPU_OP_CVT, fmt, -1, fs, fd, -1, COP1_FMT_L);
-		return 1;
-	}
-
-	/*  trunc.w.fmt: Truncate  */
-	if ((function & 0x001f003f) == 0x0000000d) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("trunc.w.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
-		if (unassemble_only)
-			return 1;
-
-		/*  TODO: not CVT?  */
-
-		fpu_op(cpu, cp, FPU_OP_CVT, fmt, -1, fs, fd, -1, COP1_FMT_W);
-		return 1;
-	}
-
-	/*  c.cond.fmt: Floating-point compare  */
-	if ((function & 0x000000f0) == 0x00000030) {
-		int cond_true;
-		int bit;
-
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("c.%s.%s\tcc%i,r%i,r%i\n", ccname[cond],
-			    fmtname[fmt], cc, fs, ft);
-		if (unassemble_only)
-			return 1;
-
-		cond_true = fpu_op(cpu, cp, FPU_OP_C, fmt,
-		    ft, fs, -1, cond, fmt);
-
-		/*
-		 *  Both the FCCR and FCSR contain condition code bits:
-		 *	FCCR:  bits 7..0
-		 *	FCSR:  bits 31..25 and 23
-		 */
-		cp->fcr[MIPS_FPU_FCCR] &= ~(1 << cc);
-		if (cond_true)
-			cp->fcr[MIPS_FPU_FCCR] |= (1 << cc);
-
-		if (cc == 0) {
-			bit = 1 << MIPS_FCSR_FCC0_SHIFT;
-			cp->fcr[MIPS_FPU_FCSR] &= ~bit;
-			if (cond_true)
-				cp->fcr[MIPS_FPU_FCSR] |= bit;
-		} else {
-			bit = 1 << (MIPS_FCSR_FCC1_SHIFT + cc-1);
-			cp->fcr[MIPS_FPU_FCSR] &= ~bit;
-			if (cond_true)
-				cp->fcr[MIPS_FPU_FCSR] |= bit;
-		}
-
-		return 1;
-	}
-
-	/*  cvt.s.fmt: Convert to single floating-point  */
-	if ((function & 0x001f003f) == 0x00000020) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("cvt.s.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
-		if (unassemble_only)
-			return 1;
-
-		fpu_op(cpu, cp, FPU_OP_CVT, fmt, -1, fs, fd, -1, COP1_FMT_S);
-		return 1;
-	}
-
-	/*  cvt.d.fmt: Convert to double floating-point  */
-	if ((function & 0x001f003f) == 0x00000021) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("cvt.d.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
-		if (unassemble_only)
-			return 1;
-
-		fpu_op(cpu, cp, FPU_OP_CVT, fmt, -1, fs, fd, -1, COP1_FMT_D);
-		return 1;
-	}
-
-	/*  cvt.w.fmt: Convert to word fixed-point  */
-	if ((function & 0x001f003f) == 0x00000024) {
-		if (cpu->machine->instruction_trace || unassemble_only)
-			debug("cvt.w.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
-		if (unassemble_only)
-			return 1;
-
-		fpu_op(cpu, cp, FPU_OP_CVT, fmt, -1, fs, fd, -1, COP1_FMT_W);
-		return 1;
-	}
-
-	return 0;
-}
-
-
-/*
- *  coproc_tlbpr():
- *
- *  'tlbp' and 'tlbr'.
- */
-void coproc_tlbpr(struct cpu *cpu, int readflag)
-{
-	struct mips_coproc *cp = cpu->cd.mips.coproc[0];
-	int i, found, g_bit;
-	uint64_t vpn2, xmask;
-
-	/*  Read:  */
-	if (readflag) {
-		if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
-			i = (cp->reg[COP0_INDEX] & R2K3K_INDEX_MASK) >>
-			    R2K3K_INDEX_SHIFT;
-			if (i >= cp->nr_of_tlbs) {
-				/*  TODO:  exception?  */
-				fatal("[ warning: tlbr from index %i (too "
-				    "high) ]\n", i);
-				return;
-			}
-
-			cp->reg[COP0_ENTRYHI]  = cp->tlbs[i].hi;
-			cp->reg[COP0_ENTRYLO0] = cp->tlbs[i].lo0;
-		} else {
-			/*  R4000:  */
-			i = cp->reg[COP0_INDEX] & INDEX_MASK;
-			if (i >= cp->nr_of_tlbs) {
-				/*  TODO:  exception?  */
-				fatal("[ warning: tlbr from index %i (too "
-				    "high) ]\n", i);
-				return;
-			}
-
-			cp->reg[COP0_PAGEMASK] = cp->tlbs[i].mask;
-			cp->reg[COP0_ENTRYHI]  = cp->tlbs[i].hi;
-			cp->reg[COP0_ENTRYLO1] = cp->tlbs[i].lo1;
-			cp->reg[COP0_ENTRYLO0] = cp->tlbs[i].lo0;
-
-			if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
-				/*  R4100 don't have the G bit in entryhi  */
-			} else {
-				/*  R4000 etc:  */
-				cp->reg[COP0_ENTRYHI] &= ~TLB_G;
-				g_bit = cp->tlbs[i].hi & TLB_G;
-
-				cp->reg[COP0_ENTRYLO0] &= ~ENTRYLO_G;
-				cp->reg[COP0_ENTRYLO1] &= ~ENTRYLO_G;
-				if (g_bit) {
-					cp->reg[COP0_ENTRYLO0] |= ENTRYLO_G;
-					cp->reg[COP0_ENTRYLO1] |= ENTRYLO_G;
-				}
-			}
-		}
-
-		return;
-	}
-
-	/*  Probe:  */
-	if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
-		vpn2 = cp->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_VPN_MASK;
-		found = -1;
-		for (i=0; i<cp->nr_of_tlbs; i++)
-			if ( ((cp->tlbs[i].hi & R2K3K_ENTRYHI_ASID_MASK) ==
-			    (cp->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_ASID_MASK))
-			    || cp->tlbs[i].lo0 & R2K3K_ENTRYLO_G)
-				if ((cp->tlbs[i].hi & R2K3K_ENTRYHI_VPN_MASK)
-				    == vpn2) {
-					found = i;
-					break;
-				}
-	} else {
-		/*  R4000 and R10000:  */
-		if (cpu->cd.mips.cpu_type.mmu_model == MMU10K)
-			xmask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K;
-		else if (cpu->cd.mips.cpu_type.rev == MIPS_R4100)
-			xmask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK | 0x1800;
-		else
-			xmask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK;
-		vpn2 = cp->reg[COP0_ENTRYHI] & xmask;
-
-		found = -1;
-		for (i=0; i<cp->nr_of_tlbs; i++) {
-			int gbit = cp->tlbs[i].hi & TLB_G;
-			if (cpu->cd.mips.cpu_type.rev == MIPS_R4100)
-				gbit = (cp->tlbs[i].lo0 & ENTRYLO_G) &&
-				    (cp->tlbs[i].lo1 & ENTRYLO_G);
-
-			if ( ((cp->tlbs[i].hi & ENTRYHI_ASID) ==
-			    (cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID)) || gbit) {
-				uint64_t a = vpn2 & ~cp->tlbs[i].mask;
-				uint64_t b = (cp->tlbs[i].hi & xmask) &
-				    ~cp->tlbs[i].mask;
-				if (a == b) {
-					found = i;
-					break;
-				}
-			}
-		}
-	}
-
-	if (found == -1)
-		cp->reg[COP0_INDEX] = INDEX_P;
-	else {
-		if (cpu->cd.mips.cpu_type.mmu_model == MMU3K)
-			cp->reg[COP0_INDEX] = found << R2K3K_INDEX_SHIFT;
-		else
-			cp->reg[COP0_INDEX] = found;
-	}
-
-	/*  Sign extend the index register:  */
-	if ((cp->reg[COP0_INDEX] >> 32) == 0 &&
-	    cp->reg[COP0_INDEX] & 0x80000000)
-		cp->reg[COP0_INDEX] |=
-		    0xffffffff00000000ULL;
-}
-
-
-/*
- *  coproc_tlbwri():
- *
- *  MIPS TLB write random (tlbwr) and write indexed (tlbwi) instructions.
- */
-void coproc_tlbwri(struct cpu *cpu, int randomflag)
-{
-	struct mips_coproc *cp = cpu->cd.mips.coproc[0];
-	int index, g_bit;
-	uint64_t oldvaddr;
-
-	if (randomflag) {
-		if (cpu->cd.mips.cpu_type.exc_model == EXC3K) {
-			index = ((cp->reg[COP0_RANDOM] & R2K3K_RANDOM_MASK)
-			    >> R2K3K_RANDOM_SHIFT) - 1;
-			/*  R3000 always has 8 wired entries:  */
-			if (index < 8)
-				index = cp->nr_of_tlbs - 1;
-			cp->reg[COP0_RANDOM] = index << R2K3K_RANDOM_SHIFT;
-		} else {
-			cp->reg[COP0_RANDOM] = cp->reg[COP0_WIRED] + (random()
-			    % (cp->nr_of_tlbs - cp->reg[COP0_WIRED]));
-			index = cp->reg[COP0_RANDOM] & RANDOM_MASK;
-		}
-	} else {
-		if (cpu->cd.mips.cpu_type.mmu_model == MMU3K)
-			index = (cp->reg[COP0_INDEX] & R2K3K_INDEX_MASK)
-			    >> R2K3K_INDEX_SHIFT;
-		else
-			index = cp->reg[COP0_INDEX] & INDEX_MASK;
-	}
-
-	if (index >= cp->nr_of_tlbs) {
-		fatal("warning: tlb index %i too high (max is %i)\n",
-		    index, cp->nr_of_tlbs - 1);
-		/*  TODO:  cause an exception?  */
-		return;
-	}
-
-
-#if 0
-	/*  Debug dump of the previous entry at that index:  */
-	fatal("{ old TLB entry at index %02x:", index);
-	if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
-		fatal(" hi=%08" PRIx32, (uint32_t)cp->tlbs[index].hi);
-		fatal(" lo=%08" PRIx32, (uint32_t)cp->tlbs[index].lo0);
-	} else {
-		if (cpu->is_32bit) {
-			fatal(" mask=%08" PRIx32,(uint32_t)cp->tlbs[index].mask);
-			fatal(" hi=%08" PRIx32, (uint32_t)cp->tlbs[index].hi);
-			fatal(" lo0=%08" PRIx32, (uint32_t)cp->tlbs[index].lo0);
-			fatal(" lo1=%08" PRIx32, (uint32_t)cp->tlbs[index].lo1);
-		} else {
-			fatal(" mask=%016" PRIx64, cp->tlbs[index].mask);
-			fatal(" hi=%016" PRIx64, cp->tlbs[index].hi);
-			fatal(" lo0=%016" PRIx64, cp->tlbs[index].lo0);
-			fatal(" lo1=%016" PRIx64, cp->tlbs[index].lo1);
-		}
-	}
-	fatal(" }\n");
-#endif
-
-	/*
-	 *  Any virtual address translation for the old TLB entry must be
-	 *  invalidated first:
-	 *
-	 *  (Only Valid entries need to be invalidated, and only those that
-	 *  are either Global, or have the same ASID as the new entry will
-	 *  have. No other address translations should be active anyway.)
-	 */
-
-	switch (cpu->cd.mips.cpu_type.mmu_model) {
-
-	case MMU3K:
-		oldvaddr = cp->tlbs[index].hi & R2K3K_ENTRYHI_VPN_MASK;
-		oldvaddr = (int32_t) oldvaddr;
-
-		if (cp->tlbs[index].lo0 & R2K3K_ENTRYLO_V &&
-		    (cp->tlbs[index].lo0 & R2K3K_ENTRYLO_G ||
-		    (cp->tlbs[index].hi & R2K3K_ENTRYHI_ASID_MASK) ==
-		    (cp->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_ASID_MASK) ))
-			cpu->invalidate_translation_caches(cpu, oldvaddr,
-			    INVALIDATE_VADDR);
-
-		break;
-
-	default:if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) {
-			oldvaddr = cp->tlbs[index].hi &
-			    (ENTRYHI_VPN2_MASK_R10K | ENTRYHI_R_MASK);
-		} else if (cpu->is_32bit) {
-			/*  MIPS32 etc.:  */
-			oldvaddr = cp->tlbs[index].hi & ENTRYHI_VPN2_MASK;
-			oldvaddr = (int32_t)oldvaddr;
-		} else {
-			/*  Assume MMU4K  */
-			oldvaddr = cp->tlbs[index].hi &
-			    (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK);
-		}
-
-		{
-			// This is the "dual page" mask:
-			uint64_t dpmask = cp->tlbs[index].mask;
-			if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
-				dpmask |= 0x07ff;
-			} else {
-				dpmask |= 0x1fff;
-			}
-
-			if (dpmask == 0x7ff) {
-				if (cp->tlbs[index].lo0 & ENTRYLO_V ||
-				    cp->tlbs[index].lo1 & ENTRYLO_V) {
-					fatal("1KB pages don't work with dyntrans.\n");
-					exit(1);
-				}
-			}
-
-			// Mask for bytes within a single page:
-			uint64_t mask = dpmask >> 1;
-
-			uint64_t pagesize = mask + 1;
-			
-			oldvaddr &= ~dpmask;
-
-			// printf("pagesize = %016llx mask = %016llx\n", pagesize, mask);
-			
-			if (cp->tlbs[index].lo0 & ENTRYLO_V)
-				for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
-					cpu->invalidate_translation_caches(cpu, oldvaddr + ofs, INVALIDATE_VADDR);
-			
-			if (cp->tlbs[index].lo1 & ENTRYLO_V)
-				for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
-					cpu->invalidate_translation_caches(cpu, oldvaddr + ofs + pagesize, INVALIDATE_VADDR);
-		}
-	}
-
-#if 0
-	/*
-	 *  Check for duplicate entries.  (There should not be two mappings
-	 *  from one virtual address to physical addresses.)
-	 *
-	 *  TODO: Do this for MMU3K and R4100 too.
-	 *
-	 *  TODO: Make this detection more robust.
-	 */
-	if (cpu->cd.mips.cpu_type.mmu_model != MMU3K &&
-	    cpu->cd.mips.cpu_type.rev != MIPS_R4100) {
-		uint64_t vaddr1, vaddr2;
-		int i;
-		unsigned int asid;
-
-		vaddr1 = cp->reg[COP0_ENTRYHI] &
-		    (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K);
-		asid = cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID;
-		/*  Since this is just a warning, it's probably not necessary
-		    to use R4000 masks etc.  */
-
-		for (i=0; i<cp->nr_of_tlbs; i++) {
-			if (i == index && !randomflag)
-				continue;
-
-			if (!(cp->tlbs[i].hi & TLB_G) &&
-			    (cp->tlbs[i].hi & ENTRYHI_ASID) != asid)
-				continue;
-
-			vaddr2 = cp->tlbs[i].hi &
-			    (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K);
-			if (vaddr1 == vaddr2 && ((cp->tlbs[i].lo0 &
-			    ENTRYLO_V) || (cp->tlbs[i].lo1 & ENTRYLO_V)))
-				fatal("\n[ WARNING! tlbw%s to index 0x%02x "
-				    "vaddr=0x%llx (asid 0x%02x) is already in"
-				    " the TLB (entry 0x%02x) ! ]\n\n",
-				    randomflag? "r" : "i", index,
-				    (long long)vaddr1, asid, i);
-		}
-	}
-#endif
-
-	/*  Write the new entry:  */
-
-	if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
-		uint32_t vaddr, paddr;
-		int wf = cp->reg[COP0_ENTRYLO0] & R2K3K_ENTRYLO_D? 1 : 0;
-
-		cp->tlbs[index].hi = cp->reg[COP0_ENTRYHI];
-		cp->tlbs[index].lo0 = cp->reg[COP0_ENTRYLO0];
-
-		vaddr =  cp->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_VPN_MASK;
-		paddr = cp->reg[COP0_ENTRYLO0] & R2K3K_ENTRYLO_PFN_MASK;
-
-		/*  Invalidate any code translation, if we are writing
-		    a Dirty page to the TLB:  */
-		if (wf) {
-			cpu->invalidate_code_translation(cpu, paddr,
-			    INVALIDATE_PADDR);
-		}
-
-		/*  Set new last_written_tlb_index hint:  */
-		cpu->cd.mips.last_written_tlb_index = index;
-
-		if (cp->reg[COP0_STATUS] & MIPS1_ISOL_CACHES) {
-			fatal("Wow! Interesting case; tlbw* while caches"
-			    " are isolated. TODO\n");
-			/*  Don't update the translation table in this
-			    case...  */
-			exit(1);
-		}
-
-		/*  If we have a memblock (host page) for the physical
-		    page, then add a translation for it immediately:  */
-		if (cp->reg[COP0_ENTRYLO0] & R2K3K_ENTRYLO_V) {
-		    	unsigned char *memblock = memory_paddr_to_hostaddr(cpu->mem, paddr, 0);
-			if (memblock != NULL)
-				cpu->update_translation_table(cpu, vaddr, memblock, wf, paddr);
-		}
-	} else {
-		/*  R4000, R10000, VR41xx etc.:  */
-		int wf0, wf1;
-		uint64_t vaddr0, vaddr1, ptmp, psize;
-
-		cp->tlbs[index].mask = cp->reg[COP0_PAGEMASK];
-		cp->tlbs[index].hi   = cp->reg[COP0_ENTRYHI];
-		cp->tlbs[index].lo1  = cp->reg[COP0_ENTRYLO1];
-		cp->tlbs[index].lo0  = cp->reg[COP0_ENTRYLO0];
-
-		wf0 = cp->tlbs[index].lo0 & ENTRYLO_D;
-		wf1 = cp->tlbs[index].lo1 & ENTRYLO_D;
-
-		// This is the "dual page" mask:
-		uint64_t dpmask = cp->reg[COP0_PAGEMASK];
-		if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
-			dpmask |= 0x07ff;
-		} else {
-			dpmask |= 0x1fff;
-		}
-
-		if (dpmask == 0x7ff) {
-			if (cp->tlbs[index].lo0 & ENTRYLO_V ||
-			    cp->tlbs[index].lo1 & ENTRYLO_V) {
-				fatal("1KB pages don't work with dyntrans.\n");
-				exit(1);
-			}
-		}
-
-		// Mask for bytes within a single page:
-		uint64_t mask = dpmask >> 1;
-
-		// printf("mask = %016llx\n", (long long)mask);
-
-		uint64_t pfn0 = (cp->tlbs[index].lo0 & ENTRYLO_PFN_MASK) >> ENTRYLO_PFN_SHIFT;
-		uint64_t pfn1 = (cp->tlbs[index].lo1 & ENTRYLO_PFN_MASK) >> ENTRYLO_PFN_SHIFT;
-
-		uint64_t paddr0, paddr1;
-
-		if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
-			paddr0 = (pfn0 << 10) & ~mask;
-			paddr1 = (pfn1 << 10) & ~mask;
-		} else {
-			paddr0 = (pfn0 << 12) & ~mask;
-			paddr1 = (pfn1 << 12) & ~mask;
-		}
-
-		if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) {
-			vaddr0 = cp->tlbs[index].hi & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K);
-		} else if (cpu->is_32bit) {
-			/*  MIPS32 etc.:  */
-			vaddr0 = cp->tlbs[index].hi & ENTRYHI_VPN2_MASK;
-			vaddr0 = (int32_t)vaddr0;
-		} else {
-			/*  Assume MMU4K  */
-			vaddr0 = cp->tlbs[index].hi & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK);
-		}
-
-		psize = mask + 1;
-
-		vaddr0 &= ~dpmask;
-		vaddr1 = vaddr0 | psize;
-
-		g_bit = (cp->reg[COP0_ENTRYLO0] & cp->reg[COP0_ENTRYLO1]) & ENTRYLO_G;
-
-		if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) {
-			/*  NOTE: The VR4131 (and possibly others) don't have
-			    a Global bit in entryhi  */
-			cp->tlbs[index].hi &= ~cp->reg[COP0_PAGEMASK];
-		} else {
-			cp->tlbs[index].lo0 &= ~ENTRYLO_G;
-			cp->tlbs[index].lo1 &= ~ENTRYLO_G;
-
-			cp->tlbs[index].hi &= ~TLB_G;
-			if (g_bit)
-				cp->tlbs[index].hi |= TLB_G;
-		}
-
-		/*
-		 *  Invalidate any code translations, if we are writing Dirty
-		 *  pages to the TLB:
-		 */
-
-		if (wf0) {
-			for (ptmp = 0; ptmp < psize; ptmp += 0x1000)
-				cpu->invalidate_code_translation(cpu,
-				    paddr0 + ptmp, INVALIDATE_PADDR);
-		}
-		if (wf1) {
-			for (ptmp = 0; ptmp < psize; ptmp += 0x1000)
-				cpu->invalidate_code_translation(cpu,
-				    paddr1 + ptmp, INVALIDATE_PADDR);
-		}
-
-		/*
-		 *  If we have a memblock (host page) for the physical page,
-		 *  then add a translation for it immediately, to save some
-		 *  time. (It would otherwise be added later on anyway,
-		 *  because of a translation miss.)
-		 *
-		 *  NOTE/TODO: This is only for 4KB pages so far. It would
-		 *             be too expensive to add e.g. 16MB pages like
-		 *             this.
-		 */
-		if (psize == 0x1000) {
-			if (cp->reg[COP0_ENTRYLO0] & ENTRYLO_V) {
-				unsigned char *memblock = memory_paddr_to_hostaddr(cpu->mem, paddr0, 0);
-				if (memblock != NULL)
-					cpu->update_translation_table(cpu, vaddr0, memblock, wf0, paddr0);
-			}
-			if (cp->reg[COP0_ENTRYLO1] & ENTRYLO_V) {
-				unsigned char *memblock = memory_paddr_to_hostaddr(cpu->mem, paddr1, 0);
-				if (memblock != NULL)
-					cpu->update_translation_table(cpu, vaddr1, memblock, wf1, paddr1);
-			}
-		}
-
-		/*  Set new last_written_tlb_index hint:  */
-		cpu->cd.mips.last_written_tlb_index = index;
-	}
-}
-
-
-/*
- *  coproc_eret():
- *
- *  Return from exception. (R4000 etc.)
- */
-void coproc_eret(struct cpu *cpu)
-{
-	if (cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & STATUS_ERL) {
-		cpu->pc = cpu->cd.mips.coproc[0]->reg[COP0_ERROREPC];
-		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_ERL;
-	} else {
-		cpu->pc = cpu->cd.mips.coproc[0]->reg[COP0_EPC];
-		cpu->delay_slot = 0;
-		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_EXL;
-	}
-
-	cpu->cd.mips.rmw = 0;	/*  the "LL bit"  */
-}
-
-
-/*
- *  coproc_function():
- *
- *  Execute a coprocessor specific instruction. cp must be != NULL.
- *  Debug trace should be printed for known instructions, if
- *  unassemble_only is non-zero. (This will NOT execute the instruction.)
- *
- *  TODO:  This is a mess and should be restructured (again).
- */
-void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr,
-	uint32_t function, int unassemble_only, int running)
-{
-	int co_bit, op, rt, rd, fs, copz;
-	uint64_t tmpvalue;
-
-	if (cp == NULL) {
-		if (unassemble_only) {
-			debug("cop%i\t0x%08x (coprocessor not available)\n",
-			    cpnr, (int)function);
-			return;
-		}
-		fatal("[ pc=0x%016llx cop%i\t0x%08x (coprocessor not "
-		    "available)\n", (long long)cpu->pc, cpnr, (int)function);
-		return;
-	}
-
-	/*  No FPU?  */
-	if (cpnr == 1 && (cpu->cd.mips.cpu_type.flags & NOFPU)) {
-		mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0, cpnr, 0, 0, 0);
-		return;
-	}
-
-	/*  For quick reference:  */
-	copz = (function >> 21) & 31;
-	rt = (function >> 16) & 31;
-	rd = (function >> 11) & 31;
-
-	if (cpnr < 2 && (((function & 0x03e007f8) == (COPz_MFCz << 21))
-	              || ((function & 0x03e007f8) == (COPz_DMFCz << 21)))) {
-		if (unassemble_only) {
-			debug("%s%i\t%s,", copz==COPz_DMFCz? "dmfc" : "mfc",
-			    cpnr, regnames[rt]);
-			if (cpnr == 0)
-				debug("%s", cop0_names[rd]);
-			else
-				debug("r%i", rd);
-			if (function & 7)
-				debug(",%i", (int)(function & 7));
-			debug("\n");
-			return;
-		}
-		coproc_register_read(cpu, cpu->cd.mips.coproc[cpnr],
-		    rd, &tmpvalue, function & 7);
-		cpu->cd.mips.gpr[rt] = tmpvalue;
-		if (copz == COPz_MFCz) {
-			/*  Sign-extend:  */
-			cpu->cd.mips.gpr[rt] &= 0xffffffffULL;
-			if (cpu->cd.mips.gpr[rt] & 0x80000000ULL)
-				cpu->cd.mips.gpr[rt] |= 0xffffffff00000000ULL;
-		}
-		return;
-	}
-
-	if (cpnr < 2 && (((function & 0x03e007f8) == (COPz_MTCz << 21))
-	              || ((function & 0x03e007f8) == (COPz_DMTCz << 21)))) {
-		tmpvalue = cpu->cd.mips.gpr[rt];
-		if (copz == COPz_MTCz) {
-			/*  Sign-extend:  */
-			tmpvalue &= 0xffffffffULL;
-			if (tmpvalue & 0x80000000ULL)
-				tmpvalue |= 0xffffffff00000000ULL;
-		}
-		if (unassemble_only) {
-			debug("%s%i\t%s,", copz==COPz_DMTCz? "dmtc" : "mtc",
-			    cpnr, regnames[rt]);
-			if (cpnr == 0)
-				debug("%s", cop0_names[rd]);
-			else
-				debug("r%i", rd);
-			if (function & 7)
-				debug(",%i", (int)(function & 7));
-			debug(" [%016llx]", (long long)tmpvalue);
-			debug("\n");
-			return;
-		}
-		coproc_register_write(cpu, cpu->cd.mips.coproc[cpnr], rd,
-		    &tmpvalue, copz == COPz_DMTCz, function & 7);
-		return;
-	}
-
-	if (cpnr <= 1 && (((function & 0x03e007ff) == (COPz_CFCz << 21))
-	              || ((function & 0x03e007ff) == (COPz_CTCz << 21)))) {
-		switch (copz) {
-		case COPz_CFCz:		/*  Copy from FPU control register  */
-			rt = (function >> 16) & 31;
-			fs = (function >> 11) & 31;
-			if (unassemble_only) {
-				debug("cfc%i\t%s,r%i\n", cpnr,
-				    regnames[rt], fs);
-				return;
-			}
-			cpu->cd.mips.gpr[rt] = (int32_t)cp->fcr[fs];
-			/*  TODO: implement delay for gpr[rt]
-			    (for MIPS I,II,III only)  */
-			return;
-		case COPz_CTCz:		/*  Copy to FPU control register  */
-			rt = (function >> 16) & 31;
-			fs = (function >> 11) & 31;
-			if (unassemble_only) {
-				debug("ctc%i\t%s,r%i\n", cpnr,
-				    regnames[rt], fs);
-				return;
-			}
-
-			switch (cpnr) {
-			case 0:	/*  System coprocessor  */
-				fatal("[ warning: unimplemented ctc%i, "
-				    "0x%08x -> ctl reg %i ]\n", cpnr,
-				    (int)cpu->cd.mips.gpr[rt], fs);
-				break;
-			case 1:	/*  FPU  */
-				if (fs == 0)
-					fatal("[ Attempt to write to FPU "
-					    "control register 0 (?) ]\n");
-				else {
-					uint64_t tmp = cpu->cd.mips.gpr[rt];
-					cp->fcr[fs] = tmp;
-
-					/*  TODO: writing to control register 31
-					    should cause exceptions, depending
-					    on status bits!  */
-
-					switch (fs) {
-					case MIPS_FPU_FCCR:
-						cp->fcr[MIPS_FPU_FCSR] =
-						    (cp->fcr[MIPS_FPU_FCSR] &
-						    0x017fffffULL) | ((tmp & 1)
-						    << MIPS_FCSR_FCC0_SHIFT)
-						    | (((tmp & 0xfe) >> 1) <<
-						    MIPS_FCSR_FCC1_SHIFT);
-						break;
-					case MIPS_FPU_FCSR:
-						cp->fcr[MIPS_FPU_FCCR] =
-						    (cp->fcr[MIPS_FPU_FCCR] &
-						    0xffffff00ULL) | ((tmp >>
-						    MIPS_FCSR_FCC0_SHIFT) & 1) |
-						    (((tmp >>
-						    MIPS_FCSR_FCC1_SHIFT)
-						    & 0x7f) << 1);
-						break;
-					default:
-						;
-					}
-				}
-				break;
-			}
-
-			/*  TODO: implement delay for gpr[rt]
-			    (for MIPS I,II,III only)  */
-			return;
-		default:
-			;
-		}
-	}
-
-	/*  Math (Floating point) coprocessor calls:  */
-	if (cpnr==1) {
-		if (fpu_function(cpu, cp, function, unassemble_only))
-			return;
-	}
-
-
-	/*  Ugly R5900 hacks:  */
-	if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
-		if ((function & 0xfffff) == COP0_EI) {
-			if (unassemble_only) {
-				debug("ei\n");
-				return;
-			}
-			cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |=
-			    R5900_STATUS_EIE;
-			return;
-		}
-
-		if ((function & 0xfffff) == COP0_DI) {
-			if (unassemble_only) {
-				debug("di\n");
-				return;
-			}
-			cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &=
-			    ~R5900_STATUS_EIE;
-			return;
-		}
-	}
-
-	co_bit = (function >> 25) & 1;
-
-	/*  TLB operations and other things:  */
-	if (cp->coproc_nr == 0) {
-		if (!unassemble_only) {
-			fatal("FATAL INTERNAL ERROR: Should be implemented"
-			    " with dyntrans instead.\n");
-			exit(1);
-		}
-
-		switch (co_bit) {
-		case 0:
-			if ((function & 0x03e0ffdf) == 0x01606000) {
-				debug("%ci", function & 0x20? 'e' : 'd');
-				if (rt != MIPS_GPR_ZERO)
-					debug("\t%s", regnames[rt]);
-				debug("\n");
-				return;
-			}
-			break;
-		case 1:
-			op = (function) & 0xff;
-			switch (op) {
-			case COP0_TLBR:		/*  Read indexed TLB entry  */
-				debug("tlbr\n");
-				return;
-			case COP0_TLBWI:	/*  Write indexed  */
-			case COP0_TLBWR:	/*  Write random  */
-				if (op == COP0_TLBWI)
-					debug("tlbwi");
-				else
-					debug("tlbwr");
-				if (!running) {
-					debug("\n");
-					return;
-				}
-				debug("\tindex=%08llx",
-				    (long long)cp->reg[COP0_INDEX]);
-				debug(", random=%08llx",
-				    (long long)cp->reg[COP0_RANDOM]);
-				debug(", mask=%016llx",
-				    (long long)cp->reg[COP0_PAGEMASK]);
-				debug(", hi=%016llx",
-				    (long long)cp->reg[COP0_ENTRYHI]);
-				debug(", lo0=%016llx",
-				    (long long)cp->reg[COP0_ENTRYLO0]);
-				debug(", lo1=%016llx\n",
-				    (long long)cp->reg[COP0_ENTRYLO1]);
-				return;
-			case COP0_TLBP:		/*  Probe TLB for
-						    matching entry  */
-				debug("tlbp\n");
-				return;
-			case COP0_RFE:		/*  R2000/R3000 only:
-						    Return from Exception  */
-				debug("rfe\n");
-				return;
-			case COP0_ERET:	/*  R4000: Return from exception  */
-				debug("eret\n");
-				return;
-			case COP0_DERET:
-				debug("deret\n");
-				return;
-			case COP0_WAIT:
-				{
-					int code = (function >> 6) & 0x7ffff;
-					debug("wait");
-					if (code > 0)
-						debug("\t0x%x", code);
-					debug("\n");
-				}
-				return;
-			case COP0_STANDBY:
-				debug("standby\n");
-				return;
-			case COP0_SUSPEND:
-				debug("suspend\n");
-				return;
-			case COP0_HIBERNATE:
-				debug("hibernate\n");
-				return;
-			default:
-				;
-			}
-			break;
-		}
-	}
-
-	/*  TODO: coprocessor R2020 on DECstation?  */
-	if ((cp->coproc_nr==0 || cp->coproc_nr==3) && function == 0x0100ffff) {
-		if (unassemble_only) {
-			debug("decstation_r2020_writeback\n");
-			return;
-		}
-		/*  TODO  */
-		return;
-	}
-
-	if (unassemble_only) {
-		debug("cop%i\t0x%08x (unimplemented)\n", cpnr, (int)function);
-		return;
-	}
-
-	fatal("cpu%i: UNIMPLEMENTED coproc%i function %08" PRIx32" "
-	    "(pc = %016" PRIx64")\n", cpu->cpu_id, cp->coproc_nr,
-	    (uint32_t)function, cpu->pc);
-
-	mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0, cp->coproc_nr, 0, 0, 0);
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_mips_instr.c gxemul-0.7.0+dfsg/src/cpus/cpu_mips_instr.c
--- gxemul-0.6.2/src/cpus/cpu_mips_instr.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_mips_instr.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,4985 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  MIPS instructions.
+ *
+ *  Individual functions should keep track of cpu->n_translated_instrs.
+ *  (If no instruction was executed, then it should be decreased. If, say, 4
+ *  instructions were combined into one function and executed, then it should
+ *  be increased by 3.)
+ */
+
+
+/*
+ *  COPROC_AVAILABILITY_CHECK(n) checks for the coprocessor available bit for
+ *  coprocessor number n, and causes a CoProcessor Unusable exception if it
+ *  is not set.  (Note: For coprocessor 0 checks, use cop0_availability_check!)
+ */
+#ifndef	COPROC_AVAILABILITY_CHECK
+#define	COPROC_AVAILABILITY_CHECK(x)		{		\
+		const int cpnr = (x);					\
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page) \
+		    / sizeof(struct mips_instr_call);			\
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)		\
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);			\
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);	\
+		if (!(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &	\
+		    ((1 << cpnr) << STATUS_CU_SHIFT)) ) {		\
+			mips_cpu_exception(cpu, EXCEPTION_CPU,		\
+			    0, 0, cpnr, 0, 0, 0);			\
+			return;						\
+		}							\
+	}
+#endif
+
+
+#ifndef	COP0_AVAILABILITY_CHECK_INCLUDED
+#define	COP0_AVAILABILITY_CHECK_INCLUDED
+/*
+ *  cop0_availability_check() causes a CoProcessor Unusable exception if
+ *  we are currently running in usermode, and the coprocessor available bit
+ *  for coprocessor 0 is not set.
+ *
+ *  Returns 1 if ok (i.e. if the coprocessor was usable), 0 on exceptions.
+ */
+int cop0_availability_check(struct cpu *cpu, struct mips_instr_call *ic)
+{
+	int in_usermode = 0;
+	struct mips_coproc *cp0 = cpu->cd.mips.coproc[0];
+
+	switch (cpu->cd.mips.cpu_type.exc_model) {
+	case EXC3K:
+		/*
+		 *  NOTE: If the KU bit is checked, Linux crashes.
+		 *  It is the PC that counts.
+		 *
+		 *  TODO: Check whether this is true or not for R4000 as well.
+		 */
+		/*  TODO: if (cp0->reg[COP0_STATUS] & MIPS1_SR_KU_CUR)  */
+		if (cpu->pc <= 0x7fffffff)
+			in_usermode = 1;
+		break;
+	default:
+		/*  R4000 etc:  (TODO: How about supervisor mode?)  */
+		if (((cp0->reg[COP0_STATUS] &
+		    STATUS_KSU_MASK) >> STATUS_KSU_SHIFT) != KSU_KERNEL)
+			in_usermode = 1;
+		if (cp0->reg[COP0_STATUS] & (STATUS_ERL | STATUS_EXL))
+			in_usermode = 0;
+		break;
+	}
+
+	if (in_usermode) {
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		if (!(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &
+		    (1 << STATUS_CU_SHIFT)) ) {
+			mips_cpu_exception(cpu, EXCEPTION_CPU,
+			    0, 0, /* cpnr */ 0, 0, 0, 0);
+			return 0;
+		}
+	}
+
+	return 1;
+}
+#endif
+
+
+/*
+ *  invalid:  For catching bugs.
+ */
+X(invalid)
+{
+	fatal("FATAL ERROR: An internal error occured in the MIPS"
+	    " dyntrans code. Please contact the author with detailed"
+	    " repro steps on how to trigger this bug.\n");
+	exit(1);
+}
+
+
+/*
+ *  reserved:  Attempt to execute a reserved instruction (e.g. a 64-bit
+ *             instruction on an emulated 32-bit processor).
+ */
+X(reserved)
+{
+	/*  Synchronize the PC and cause an exception:  */
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	mips_cpu_exception(cpu, EXCEPTION_RI, 0, 0, 0, 0, 0, 0);
+}
+
+
+/*
+ *  cpu:  Cause a CoProcessor Unusable exception.
+ *
+ *  arg[0] = the number of the coprocessor
+ */
+X(cpu)
+{
+	/*  Synchronize the PC and cause an exception:  */
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0, ic->arg[0], 0, 0, 0);
+}
+
+
+/*
+ *  nop:  Do nothing.
+ */
+X(nop)
+{
+}
+
+
+/*
+ *  beq:  Branch if equal
+ *  bne:  Branch if not equal
+ *  b:  Branch (comparing a register to itself, always true)
+ *
+ *  arg[0] = pointer to rs
+ *  arg[1] = pointer to rt
+ *  arg[2] = (int32_t) relative offset from the next instruction
+ */
+X(beq)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	int x = rs == rt;
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(beq_samepage)
+{
+	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	int x = rs == rt;
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+X(beq_samepage_addiu)
+{
+	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	cpu->n_translated_instrs ++;
+	reg(ic[1].arg[1]) = (int32_t)
+	    ((int32_t)reg(ic[1].arg[0]) + (int32_t)ic[1].arg[2]);
+	if (rs == rt)
+		cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
+	else
+		cpu->cd.mips.next_ic ++;
+}
+X(beq_samepage_nop)
+{
+	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	cpu->n_translated_instrs ++;
+	if (rs == rt)
+		cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
+	else
+		cpu->cd.mips.next_ic ++;
+}
+X(bne)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	int x = rs != rt;
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bne_samepage)
+{
+	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	int x = rs != rt;
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+X(bne_samepage_addiu)
+{
+	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	cpu->n_translated_instrs ++;
+	reg(ic[1].arg[1]) = (int32_t)
+	    ((int32_t)reg(ic[1].arg[0]) + (int32_t)ic[1].arg[2]);
+	if (rs != rt)
+		cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
+	else
+		cpu->cd.mips.next_ic ++;
+}
+X(bne_samepage_nop)
+{
+	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	cpu->n_translated_instrs ++;
+	if (rs != rt)
+		cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
+	else
+		cpu->cd.mips.next_ic ++;
+}
+X(b)
+{
+	MODE_int_t old_pc = cpu->pc;
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+		    MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc = old_pc + (int32_t)ic->arg[2];
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(b_samepage)
+{
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)))
+		cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
+	cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  beql:  Branch if equal likely
+ *  bnel:  Branch if not equal likely
+ *
+ *  arg[0] = pointer to rs
+ *  arg[1] = pointer to rt
+ *  arg[2] = (int32_t) relative offset from the next instruction
+ */
+X(beql)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	int x = rs == rt;
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(beql_samepage)
+{
+	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	int x = rs == rt;
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+X(bnel)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	int x = rs != rt;
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bnel_samepage)
+{
+	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	int x = rs != rt;
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  blez:   Branch if less than or equal
+ *  blezl:  Branch if less than or equal likely
+ *
+ *  arg[0] = pointer to rs
+ *  arg[2] = (int32_t) relative offset from the next instruction
+ */
+X(blez)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs <= 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(blez_samepage)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs <= 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+X(blezl)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs <= 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(blezl_samepage)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs <= 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  bltz:   Branch if less than
+ *  bltzl:  Branch if less than likely
+ *
+ *  arg[0] = pointer to rs
+ *  arg[2] = (int32_t) relative offset from the next instruction
+ */
+X(bltz)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs < 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bltz_samepage)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs < 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+X(bltzl)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs < 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bltzl_samepage)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs < 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  bgez:   Branch if greater than or equal
+ *  bgezl:  Branch if greater than or equal likely
+ *
+ *  arg[0] = pointer to rs
+ *  arg[2] = (int32_t) relative offset from the next instruction
+ */
+X(bgez)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs >= 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bgez_samepage)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs >= 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+X(bgezl)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs >= 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bgezl_samepage)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs >= 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  bgezal:   Branch if greater than or equal (and link)
+ *  bgezall:  Branch if greater than or equal (and link) likely
+ *
+ *  arg[0] = pointer to rs
+ *  arg[2] = (int32_t) relative offset from the next instruction
+ */
+X(bgezal)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs >= 0), low_pc;
+
+	cpu->delay_slot = TO_BE_DELAYED;
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
+
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bgezal_samepage)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs >= 0), low_pc;
+
+	cpu->delay_slot = TO_BE_DELAYED;
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
+
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+X(bgezall)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs >= 0), low_pc;
+
+	cpu->delay_slot = TO_BE_DELAYED;
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
+
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bgezall_samepage)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs >= 0), low_pc;
+
+	cpu->delay_slot = TO_BE_DELAYED;
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
+
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  bltzal:   Branch if less than zero (and link)
+ *  bltzall:  Branch if less than zero (and link) likely
+ *
+ *  arg[0] = pointer to rs
+ *  arg[2] = (int32_t) relative offset from the next instruction
+ */
+X(bltzal)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs < 0), low_pc;
+
+	cpu->delay_slot = TO_BE_DELAYED;
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
+
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bltzal_samepage)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs < 0), low_pc;
+
+	cpu->delay_slot = TO_BE_DELAYED;
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
+
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+X(bltzall)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs < 0), low_pc;
+
+	cpu->delay_slot = TO_BE_DELAYED;
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
+
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bltzall_samepage)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs < 0), low_pc;
+
+	cpu->delay_slot = TO_BE_DELAYED;
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
+
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  bgtz:   Branch if greater than zero
+ *  bgtzl:  Branch if greater than zero likely
+ *
+ *  arg[0] = pointer to rs
+ *  arg[2] = (int32_t) relative offset from the next instruction
+ */
+X(bgtz)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs > 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bgtz_samepage)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs > 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+X(bgtzl)
+{
+	MODE_int_t old_pc = cpu->pc;
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs > 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bgtzl_samepage)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	int x = (rs > 0);
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x)
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		if (x)
+			cpu->cd.mips.next_ic = (struct mips_instr_call *)
+			    ic->arg[2];
+		else
+			cpu->cd.mips.next_ic ++;
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  jr, jalr: Jump to a register [and link].
+ *
+ *  arg[0] = ptr to rs
+ *  arg[1] = ptr to rd (for jalr)
+ *  arg[2] = (int32_t) relative offset of the next instruction
+ */
+X(jr)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		cpu->pc = rs;
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(jr_ra)
+{
+	MODE_int_t rs = cpu->cd.mips.gpr[MIPS_GPR_RA];
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		cpu->pc = rs;
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(jr_ra_addiu)
+{
+	/*  jr ra, followed by an addiu  */
+	MODE_int_t rs = cpu->cd.mips.gpr[MIPS_GPR_RA];
+	reg(ic[1].arg[1]) = (int32_t)
+	    ((int32_t)reg(ic[1].arg[0]) + (int32_t)ic[1].arg[2]);
+	cpu->pc = rs;
+	quick_pc_to_pointers(cpu);
+	cpu->n_translated_instrs ++;
+}
+X(jr_ra_trace)
+{
+	MODE_int_t rs = cpu->cd.mips.gpr[MIPS_GPR_RA];
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		cpu->pc = rs;
+		cpu_functioncall_trace_return(cpu);
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(jalr)
+{
+	MODE_int_t rs = reg(ic->arg[0]), rd;
+	cpu->delay_slot = TO_BE_DELAYED;
+	rd = cpu->pc & ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+	    MIPS_INSTR_ALIGNMENT_SHIFT);
+	rd += (int32_t)ic->arg[2];
+	reg(ic->arg[1]) = rd;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		cpu->pc = rs;
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(jalr_trace)
+{
+	MODE_int_t rs = reg(ic->arg[0]), rd;
+	cpu->delay_slot = TO_BE_DELAYED;
+	rd = cpu->pc & ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+	    MIPS_INSTR_ALIGNMENT_SHIFT);
+	rd += (int32_t)ic->arg[2];
+	reg(ic->arg[1]) = rd;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		cpu->pc = rs;
+		cpu_functioncall_trace(cpu, cpu->pc);
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  j, jal:  Jump [and link].
+ *
+ *  arg[0] = lowest 28 bits of new pc.
+ *  arg[1] = offset from start of page to the jal instruction + 8
+ */
+X(j)
+{
+	MODE_int_t old_pc = cpu->pc;
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		old_pc &= ~0x03ffffff;
+		cpu->pc = old_pc | (uint32_t)ic->arg[0];
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(jal)
+{
+	MODE_int_t old_pc = cpu->pc;
+	cpu->delay_slot = TO_BE_DELAYED;
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.mips.gpr[31] = (MODE_int_t)cpu->pc + (int32_t)ic->arg[1];
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		old_pc &= ~0x03ffffff;
+		cpu->pc = old_pc | (int32_t)ic->arg[0];
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(jal_trace)
+{
+	MODE_int_t old_pc = cpu->pc;
+	cpu->delay_slot = TO_BE_DELAYED;
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.mips.gpr[31] = (MODE_int_t)cpu->pc + (int32_t)ic->arg[1];
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		old_pc &= ~0x03ffffff;
+		cpu->pc = old_pc | (int32_t)ic->arg[0];
+		cpu_functioncall_trace(cpu, cpu->pc);
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  cache:  Cache operation.
+ */
+X(cache)
+{
+	/*  TODO: Implement cache operations.  */
+
+	/*  Make sure the rmw bit is cleared:  */
+	cpu->cd.mips.rmw = 0;
+}
+
+
+/*
+ *  tgei:  Trap if Greater-or-Equal Immediate.
+ *  tgeiu:  Trap if Greater-or-Equal Immediate Unsigned.
+ *  tlti:  Trap if Less-Than Immediate.
+ *  tltiu:  Trap if Less-Than Immediate Unsigned.
+ *  teqi:  Trap if Equal Immediate.
+ *  tnei:  Trap if Not-Equal Immediate.
+ *
+ *  arg[0] = pointer to rs
+ *  arg[2] = immediate value, sign-extended to native word size
+ */
+X(tgei)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	MODE_int_t imm = ic->arg[2];
+
+	if (rs >= imm) {
+		/*  Synchronize the PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
+	}
+}
+X(tgeiu)
+{
+	MODE_uint_t rs = reg(ic->arg[0]);
+	MODE_uint_t imm = ic->arg[2];
+
+	if (rs >= imm) {
+		/*  Synchronize the PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
+	}
+}
+X(tlti)
+{
+	MODE_int_t rs = reg(ic->arg[0]);
+	MODE_int_t imm = ic->arg[2];
+
+	if (rs < imm) {
+		/*  Synchronize the PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
+	}
+}
+X(tltiu)
+{
+	MODE_uint_t rs = reg(ic->arg[0]);
+	MODE_uint_t imm = ic->arg[2];
+
+	if (rs < imm) {
+		/*  Synchronize the PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
+	}
+}
+X(teqi)
+{
+	MODE_uint_t rs = reg(ic->arg[0]);
+	MODE_uint_t imm = ic->arg[2];
+
+	if (rs == imm) {
+		/*  Synchronize the PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
+	}
+}
+X(tnei)
+{
+	MODE_uint_t rs = reg(ic->arg[0]);
+	MODE_uint_t imm = ic->arg[2];
+
+	if (rs != imm) {
+		/*  Synchronize the PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
+	}
+}
+
+
+/*
+ *  ins: Insert bitfield.
+ *
+ *  arg[0] = pointer to rt
+ *  arg[1] = pointer to rs
+ *  arg[2] = (msb << 5) + lsb
+ */
+X(ins)
+{
+	int msb = ic->arg[2] >> 5, pos = ic->arg[2] & 0x1f;
+	int size = msb + 1 - pos;
+	uint32_t rt = reg(ic->arg[0]);
+	uint32_t rs = reg(ic->arg[1]);
+	uint32_t mask = (uint32_t)(-1) << pos;
+
+	mask <<= (32 - pos - size);
+	mask >>= (32 - pos - size);
+
+	reg(ic->arg[0]) = (int32_t) ((rt & ~mask) | ((rs << pos) & mask));
+}
+
+
+/*
+ *  ext:  Extract bitfield.
+ *
+ *  arg[0] = pointer to rt
+ *  arg[1] = pointer to rs
+ *  arg[2] = (msbd << 5) + lsb
+ */
+X(ext)
+{
+	int msbd = ic->arg[2] >> 5, lsb = ic->arg[2] & 0x1f;
+	int size = msbd + 1;
+	uint32_t rs = reg(ic->arg[1]);
+	uint32_t x = (rs << (32-lsb-size)) >> (32-lsb-size);
+	reg(ic->arg[0]) = (int32_t) (x >> lsb);
+}
+
+
+/*
+ *  dext:  Extract bitfield (64-bit).
+ *
+ *  arg[0] = pointer to rt
+ *  arg[1] = pointer to rs
+ *  arg[2] = (msbd << 6) + lsb
+ */
+X(dext)
+{
+	int msbd = ic->arg[2] >> 6, lsb = ic->arg[2] & 0x3f;
+	int size = msbd + 1;
+	uint64_t rs = reg(ic->arg[1]);
+	uint64_t x = (rs << (uint64_t)(64-lsb-size)) >> (uint64_t)(64-lsb-size);
+	reg(ic->arg[0]) = x >> lsb;
+}
+
+
+/*
+ *  dsbh:  Doubleword swap bytes within half-word
+ *  dshd:  Doubleword swap half-words within double-word
+ *  wsbh:  Word swap bytes within half-word
+ *  seb:   Sign-extend byte
+ *  seh:   Sign-extend half-word
+ *
+ *  arg[0] = pointer to rt
+ *  arg[1] = pointer to rd
+ */
+X(dsbh)
+{
+	uint64_t x = reg(ic->arg[0]);
+	x = ((x & 0x00ff00ff00ff00ffULL) << 8)
+	  | ((x & 0xff00ff00ff00ff00ULL) >> 8);
+	reg(ic->arg[1]) = x;
+}
+X(dshd)
+{
+	uint64_t x = reg(ic->arg[0]);
+	x = ((x & 0x000000000000ffffULL) << 48)
+	  | ((x & 0x00000000ffff0000ULL) << 16)
+	  | ((x & 0x0000ffff00000000ULL) >> 16)
+	  | ((x & 0xffff000000000000ULL) >> 48);
+	reg(ic->arg[1]) = x;
+}
+X(wsbh)
+{
+	uint32_t x = reg(ic->arg[0]);
+	x = ((x & 0x00ff00ff) << 8) | ((x & 0xff00ff00) >> 8);
+	reg(ic->arg[1]) = (int32_t) x;
+}
+X(seb) { reg(ic->arg[1]) = (int8_t)reg(ic->arg[0]); }
+X(seh) { reg(ic->arg[1]) = (int16_t)reg(ic->arg[0]); }
+
+
+/*
+ *  2-register + immediate:
+ *
+ *  arg[0] = pointer to rs
+ *  arg[1] = pointer to rt
+ *  arg[2] = uint32_t immediate value
+ */
+X(andi) { reg(ic->arg[1]) = reg(ic->arg[0]) & (uint32_t)ic->arg[2]; }
+X(ori)  { reg(ic->arg[1]) = reg(ic->arg[0]) | (uint32_t)ic->arg[2]; }
+X(xori) { reg(ic->arg[1]) = reg(ic->arg[0]) ^ (uint32_t)ic->arg[2]; }
+
+
+/*
+ *  2-register:
+ *
+ *  arg[0] = ptr to rs
+ *  arg[1] = ptr to rt
+ */
+X(div)
+{
+	int32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	int32_t res, rem;
+	if (b == 0)
+		res = 0, rem = a;
+	else if (a == (int32_t)0x80000000U && b == -1)
+		res = 0, rem = 0;
+	else
+		res = a / b, rem = a - b*res;
+	cpu->cd.mips.lo = (int32_t)res;
+	cpu->cd.mips.hi = (int32_t)rem;
+}
+X(divu)
+{
+	uint32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	uint32_t res, rem;
+	if (b == 0)
+		res = 0, rem = a;
+	else
+		res = a / b, rem = a - b*res;
+	cpu->cd.mips.lo = (int32_t)res;
+	cpu->cd.mips.hi = (int32_t)rem;
+}
+X(ddiv)
+{
+	int64_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	int64_t res, rem;
+	if (b == 0)
+		res = 0;
+	else if (a == (int64_t)0x8000000000000000ULL && b == -1)
+		res = 0;
+	else
+		res = a / b;
+	rem = a - b*res;
+	cpu->cd.mips.lo = res;
+	cpu->cd.mips.hi = rem;
+}
+X(ddivu)
+{
+	uint64_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	uint64_t res, rem;
+	if (b == 0)
+		res = 0;
+	else
+		res = a / b;
+	rem = a - b*res;
+	cpu->cd.mips.lo = res;
+	cpu->cd.mips.hi = rem;
+}
+X(mult)
+{
+	int32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	int64_t res = (int64_t)a * (int64_t)b;
+	cpu->cd.mips.lo = (int32_t)res;
+	cpu->cd.mips.hi = (int32_t)(res >> 32);
+}
+X(mult_r5900)
+{
+	/*  C790/TX79/R5900 multiplication, stores result in
+	    hi, lo, and a third register  */
+	int32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	int64_t res = (int64_t)a * (int64_t)b;
+	cpu->cd.mips.lo = (int32_t)res;
+	cpu->cd.mips.hi = (int32_t)(res >> 32);
+	reg(ic->arg[2]) = (int32_t)res;
+}
+X(multu)
+{
+	uint32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	uint64_t res = (uint64_t)a * (uint64_t)b;
+	cpu->cd.mips.lo = (int32_t)res;
+	cpu->cd.mips.hi = (int32_t)(res >> 32);
+}
+X(multu_r5900)
+{
+	/*  C790/TX79/R5900 multiplication, stores result in
+	    hi, lo, and a third register  */
+	uint32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	uint64_t res = (uint64_t)a * (uint64_t)b;
+	cpu->cd.mips.lo = (int32_t)res;
+	cpu->cd.mips.hi = (int32_t)(res >> 32);
+	reg(ic->arg[2]) = (int32_t)res;
+}
+X(dmult)
+{
+	uint64_t a = reg(ic->arg[0]), b = reg(ic->arg[1]), c = 0;
+	uint64_t hi = 0, lo = 0;
+	int neg = 0;
+	if (a >> 63)
+		neg = !neg, a = -a;
+	if (b >> 63)
+		neg = !neg, b = -b;
+	for (; a; a >>= 1) {
+		if (a & 1) {
+			uint64_t old_lo = lo;
+			hi += c;
+			lo += b;
+			if (lo < old_lo)
+				hi ++;
+		}
+		c = (c << 1) | (b >> 63); b <<= 1;
+	}
+	if (neg) {
+		if (lo == 0)
+			hi --;
+		lo --;
+		hi ^= (int64_t) -1;
+		lo ^= (int64_t) -1;
+	}
+	cpu->cd.mips.lo = lo;
+	cpu->cd.mips.hi = hi;
+}
+X(dmultu)
+{
+	uint64_t a = reg(ic->arg[0]), b = reg(ic->arg[1]), c = 0;
+	uint64_t hi = 0, lo = 0;
+	for (; a; a >>= 1) {
+		if (a & 1) {
+			uint64_t old_lo = lo;
+			hi += c;
+			lo += b;
+			if (lo < old_lo)
+				hi ++;
+		}
+		c = (c << 1) | (b >> 63); b <<= 1;
+	}
+	cpu->cd.mips.lo = lo;
+	cpu->cd.mips.hi = hi;
+}
+X(tge)
+{
+	MODE_int_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	if (a >= b) {
+		/*  Synch. PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
+	}
+}
+X(tgeu)
+{
+	MODE_uint_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	if (a >= b) {
+		/*  Synch. PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
+	}
+}
+X(tlt)
+{
+	MODE_int_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	if (a < b) {
+		/*  Synch. PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
+	}
+}
+X(tltu)
+{
+	MODE_uint_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	if (a < b) {
+		/*  Synch. PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
+	}
+}
+X(teq)
+{
+	MODE_uint_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	if (a == b) {
+		/*  Synch. PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
+	}
+}
+X(tne)
+{
+	MODE_uint_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	if (a != b) {
+		/*  Synch. PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
+	}
+}
+
+
+/*
+ *  3-register arithmetic instructions:
+ *
+ *  arg[0] = ptr to rs
+ *  arg[1] = ptr to rt
+ *  arg[2] = ptr to rd
+ */
+X(addu) { reg(ic->arg[2]) = (int32_t)(reg(ic->arg[0]) + reg(ic->arg[1])); }
+X(add)
+{
+	int32_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	int32_t rd = rs + rt;
+
+	if (unlikely((rs >= 0 && rt >= 0 && rd < 0) || (rs < 0 && rt < 0 && rd >= 0))) {
+		/*  Synch. PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0);
+	} else
+		reg(ic->arg[2]) = rd;
+}
+X(daddu){ reg(ic->arg[2]) = reg(ic->arg[0]) + reg(ic->arg[1]); }
+X(dadd)
+{
+	int64_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
+	int64_t rd = rs + rt;
+
+	if (unlikely((rs >= 0 && rt >= 0 && rd < 0) || (rs < 0 && rt < 0 && rd >= 0))) {
+		/*  Synch. PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0);
+	} else
+		reg(ic->arg[2]) = rd;
+}
+X(subu) { reg(ic->arg[2]) = (int32_t)(reg(ic->arg[0]) - reg(ic->arg[1])); }
+X(sub)
+{
+	/*  NOTE: Negating rt and using addition. TODO: Is this correct?  */
+	int32_t rs = reg(ic->arg[0]), rt = - reg(ic->arg[1]);
+	int32_t rd = rs + rt;
+
+	if (unlikely((rs >= 0 && rt >= 0 && rd < 0) || (rs < 0 && rt < 0 && rd >= 0))) {
+		/*  Synch. PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0);
+	} else
+		reg(ic->arg[2]) = rd;
+}
+X(dsubu){ reg(ic->arg[2]) = reg(ic->arg[0]) - reg(ic->arg[1]); }
+X(dsub)
+{
+	/*  NOTE: Negating rt and using addition. TODO: Is this correct?  */
+	int64_t rs = reg(ic->arg[0]), rt = - reg(ic->arg[1]);
+	int64_t rd = rs + rt;
+
+	if (unlikely((rs >= 0 && rt >= 0 && rd < 0) || (rs < 0 && rt < 0 && rd >= 0))) {
+		/*  Synch. PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0);
+	} else
+		reg(ic->arg[2]) = rd;
+}
+X(slt) {
+	reg(ic->arg[2]) =
+	    (MODE_int_t)reg(ic->arg[0]) < (MODE_int_t)reg(ic->arg[1]);
+}
+X(sltu) {
+	reg(ic->arg[2]) =
+	    (MODE_uint_t)reg(ic->arg[0]) < (MODE_uint_t)reg(ic->arg[1]);
+}
+X(and) { reg(ic->arg[2]) = reg(ic->arg[0]) & reg(ic->arg[1]); }
+X(or)  { reg(ic->arg[2]) = reg(ic->arg[0]) | reg(ic->arg[1]); }
+X(xor) { reg(ic->arg[2]) = reg(ic->arg[0]) ^ reg(ic->arg[1]); }
+X(nor) { reg(ic->arg[2]) = ~(reg(ic->arg[0]) | reg(ic->arg[1])); }
+X(sll) { reg(ic->arg[2]) = (int32_t)(reg(ic->arg[0]) << (int32_t)ic->arg[1]); }
+X(sllv){ int32_t sa = reg(ic->arg[1]) & 31;
+	 reg(ic->arg[2]) = (int32_t)(reg(ic->arg[0]) << sa); }
+X(srl) { reg(ic->arg[2]) = (int32_t)((uint32_t)reg(ic->arg[0]) >> ic->arg[1]); }
+X(srlv){ int32_t sa = reg(ic->arg[1]) & 31;
+	 reg(ic->arg[2]) = (int32_t)((uint32_t)reg(ic->arg[0]) >> sa); }
+X(sra) { reg(ic->arg[2]) = (int32_t)((int32_t)reg(ic->arg[0]) >> ic->arg[1]); }
+X(srav){ int32_t sa = reg(ic->arg[1]) & 31;
+	 reg(ic->arg[2]) = (int32_t)((int32_t)reg(ic->arg[0]) >> sa); }
+X(dsll) { reg(ic->arg[2]) = (int64_t)reg(ic->arg[0]) << (int64_t)ic->arg[1]; }
+X(dsllv){ int64_t sa = reg(ic->arg[1]) & 63;
+	 reg(ic->arg[2]) = reg(ic->arg[0]) << sa; }
+X(dsrl) { reg(ic->arg[2]) = (int64_t)((uint64_t)reg(ic->arg[0]) >>
+	(uint64_t) ic->arg[1]);}
+X(dsrlv){ int64_t sa = reg(ic->arg[1]) & 63;
+	 reg(ic->arg[2]) = (uint64_t)reg(ic->arg[0]) >> sa; }
+X(dsra) { reg(ic->arg[2]) = (int64_t)reg(ic->arg[0]) >> (int64_t)ic->arg[1]; }
+X(dsrav){ int64_t sa = reg(ic->arg[1]) & 63;
+	 reg(ic->arg[2]) = (int64_t)reg(ic->arg[0]) >> sa; }
+X(mul) { reg(ic->arg[2]) = (int32_t)
+	( (int32_t)reg(ic->arg[0]) * (int32_t)reg(ic->arg[1]) ); }
+X(movn) { if (reg(ic->arg[1])) reg(ic->arg[2]) = reg(ic->arg[0]); }
+X(movz) { if (!reg(ic->arg[1])) reg(ic->arg[2]) = reg(ic->arg[0]); }
+
+X(ror)
+{
+	uint32_t result = reg(ic->arg[0]);
+	int sa = ic->arg[1];
+
+	result = (result >> sa) | (result << (32-sa));
+
+	reg(ic->arg[2]) = (int32_t) result;
+}
+
+X(rorv)
+{
+	uint32_t result = reg(ic->arg[0]);
+	int sa = reg(ic->arg[1]);
+
+	result = (result >> sa) | (result << (32-sa));
+
+	reg(ic->arg[2]) = (int32_t) result;
+}
+
+
+/*
+ *  p*:  128-bit C790/TX79/R5900 stuff
+ *
+ *  arg[0] = rs (note: not a pointer)
+ *  arg[1] = rt (note: not a pointer)
+ *  arg[2] = rd (note: not a pointer)
+ */
+X(por)
+{
+	cpu->cd.mips.gpr[ic->arg[2]] = cpu->cd.mips.gpr[ic->arg[0]] |
+	    cpu->cd.mips.gpr[ic->arg[1]];
+	cpu->cd.mips.gpr_quadhi[ic->arg[2]] =
+	    cpu->cd.mips.gpr_quadhi[ic->arg[0]] |
+	    cpu->cd.mips.gpr_quadhi[ic->arg[1]];
+}
+X(pextlw)
+{
+	uint64_t lo, hi;
+
+	lo = (uint32_t)cpu->cd.mips.gpr[ic->arg[1]] |
+	    (uint64_t)((uint64_t)cpu->cd.mips.gpr[ic->arg[0]] << 32);
+	hi = (cpu->cd.mips.gpr[ic->arg[0]] & 0xffffffff00000000ULL) |
+	    (uint32_t)((uint64_t)cpu->cd.mips.gpr[ic->arg[1]] >> 32);
+
+	cpu->cd.mips.gpr[ic->arg[2]] = lo;
+	cpu->cd.mips.gpr_quadhi[ic->arg[2]] = hi;
+}
+
+
+/*
+ *  madd, maddu, msub, msubu: Multiply-and-add/subtract
+ *
+ *  arg[0] = ptr to rs
+ *  arg[1] = ptr to rt
+ *  arg[2] = ptr to rd (only used on R5900/TX79)
+ */
+X(madd)
+{
+	int64_t rs = (int32_t)reg(ic->arg[0]), rt = (int32_t)reg(ic->arg[1]);
+	int64_t sum = rs * rt,
+	    hilo = (cpu->cd.mips.hi << 32) | (uint32_t)(cpu->cd.mips.lo);
+	hilo += sum;
+	cpu->cd.mips.hi = (int32_t)(hilo>>32); cpu->cd.mips.lo = (int32_t)hilo;
+}
+X(madd_rd)
+{
+	int64_t rs = (int32_t)reg(ic->arg[0]), rt = (int32_t)reg(ic->arg[1]);
+	int64_t sum = rs * rt,
+	    hilo = (cpu->cd.mips.hi << 32) | (uint32_t)(cpu->cd.mips.lo);
+	hilo += sum;
+	cpu->cd.mips.hi = (int32_t)(hilo>>32); cpu->cd.mips.lo = (int32_t)hilo;
+	reg(ic->arg[2]) = (int32_t)hilo;
+}
+X(msub)
+{
+	int64_t rs = (int32_t)reg(ic->arg[0]), rt = (int32_t)reg(ic->arg[1]);
+	int64_t sum = rs * rt,
+	    hilo = (cpu->cd.mips.hi << 32) | (uint32_t)(cpu->cd.mips.lo);
+	hilo -= sum;
+	cpu->cd.mips.hi = (int32_t)(hilo>>32); cpu->cd.mips.lo = (int32_t)hilo;
+}
+X(maddu)
+{
+	int64_t rs = (uint32_t)reg(ic->arg[0]), rt = (uint32_t)reg(ic->arg[1]);
+	int64_t sum = rs * rt,
+	    hilo = (cpu->cd.mips.hi << 32) | (uint32_t)(cpu->cd.mips.lo);
+	hilo += sum;
+	cpu->cd.mips.hi = (int32_t)(hilo>>32); cpu->cd.mips.lo = (int32_t)hilo;
+}
+X(maddu_rd)
+{
+	int64_t rs = (uint32_t)reg(ic->arg[0]), rt = (uint32_t)reg(ic->arg[1]);
+	int64_t sum = rs * rt,
+	    hilo = (cpu->cd.mips.hi << 32) | (uint32_t)(cpu->cd.mips.lo);
+	hilo += sum;
+	cpu->cd.mips.hi = (int32_t)(hilo>>32); cpu->cd.mips.lo = (int32_t)hilo;
+	reg(ic->arg[2]) = (int32_t)hilo;
+}
+X(msubu)
+{
+	int64_t rs = (uint32_t)reg(ic->arg[0]), rt = (uint32_t)reg(ic->arg[1]);
+	int64_t sum = rs * rt,
+	    hilo = (cpu->cd.mips.hi << 32) | (uint32_t)(cpu->cd.mips.lo);
+	hilo -= sum;
+	cpu->cd.mips.hi = (int32_t)(hilo>>32); cpu->cd.mips.lo = (int32_t)hilo;
+}
+
+
+/*
+ *  mov:  Move one register into another.
+ *
+ *  arg[0] = pointer to source
+ *  arg[2] = pointer to destination
+ */
+X(mov)  { reg(ic->arg[2]) = reg(ic->arg[0]); }
+
+
+/*
+ *  clz, clo, dclz, dclo: Count leading zeroes/ones.
+ *
+ *  arg[0] = pointer to rs
+ *  arg[1] = pointer to rd
+ */
+X(clz)
+{
+	uint32_t x = reg(ic->arg[0]);
+	int count;
+	for (count=0; count<32; count++) {
+		if (x & 0x80000000UL)
+			break;
+		x <<= 1;
+	}
+	reg(ic->arg[1]) = count;
+}
+X(clo)
+{
+	uint32_t x = reg(ic->arg[0]);
+	int count;
+	for (count=0; count<32; count++) {
+		if (!(x & 0x80000000UL))
+			break;
+		x <<= 1;
+	}
+	reg(ic->arg[1]) = count;
+}
+X(dclz)
+{
+	uint64_t x = reg(ic->arg[0]);
+	int count;
+	for (count=0; count<64; count++) {
+		if (x & 0x8000000000000000ULL)
+			break;
+		x <<= 1;
+	}
+	reg(ic->arg[1]) = count;
+}
+X(dclo)
+{
+	uint64_t x = reg(ic->arg[0]);
+	int count;
+	for (count=0; count<64; count++) {
+		if (!(x & 0x8000000000000000ULL))
+			break;
+		x <<= 1;
+	}
+	reg(ic->arg[1]) = count;
+}
+
+
+/*
+ *  addi, daddi: Add immediate, overflow detection.
+ *  addiu, daddiu: Add immediate.
+ *  slti:   Set if less than immediate (signed 32-bit)
+ *  sltiu:  Set if less than immediate (signed 32-bit, but unsigned compare)
+ *
+ *  arg[0] = pointer to rs
+ *  arg[1] = pointer to rt
+ *  arg[2] = (int32_t) immediate value
+ */
+X(addi)
+{
+	int32_t rs = reg(ic->arg[0]), imm = (int32_t)ic->arg[2];
+	int32_t rt = rs + imm;
+
+	if (unlikely((rs >= 0 && imm >= 0 && rt < 0) || (rs < 0 && imm < 0 && rt >= 0))) {
+		/*  Synch. PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0);
+	} else
+		reg(ic->arg[1]) = rt;
+}
+X(addiu)
+{
+	reg(ic->arg[1]) = (int32_t)
+	    ((int32_t)reg(ic->arg[0]) + (int32_t)ic->arg[2]);
+}
+X(daddi)
+{
+	int64_t rs = reg(ic->arg[0]), imm = (int32_t)ic->arg[2];
+	int64_t rt = rs + imm;
+
+	if (unlikely((rs >= 0 && imm >= 0 && rt < 0) || (rs < 0 && imm < 0 && rt >= 0))) {
+		/*  Synch. PC and cause an exception:  */
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+		    / sizeof(struct mips_instr_call);
+		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+		mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0);
+	} else
+		reg(ic->arg[1]) = rt;
+}
+X(daddiu)
+{
+	reg(ic->arg[1]) = reg(ic->arg[0]) + (int32_t)ic->arg[2];
+}
+X(slti)
+{
+	reg(ic->arg[1]) = (MODE_int_t)reg(ic->arg[0]) < (int32_t)ic->arg[2];
+}
+X(sltiu)
+{
+	reg(ic->arg[1]) = (MODE_uint_t)reg(ic->arg[0]) <
+	   ((MODE_uint_t)(int32_t)ic->arg[2]);
+}
+
+
+/*
+ *  set:  Set a register to an immediate (signed) 32-bit value.
+ *        (This is the actual implementation of the lui instruction.)
+ *
+ *  arg[0] = pointer to the register
+ *  arg[1] = (int32_t) immediate value
+ */
+X(set)
+{
+	reg(ic->arg[0]) = (int32_t)ic->arg[1];
+}
+
+
+/*
+ *  cfc0:         Copy from Coprocessor 0.
+ *  mfc0, dmfc0:  Move from Coprocessor 0.
+ *  mtc0, dmtc0:  Move to Coprocessor 0.
+ *
+ *  arg[0] = pointer to GPR (rt)
+ *  arg[1] = coprocessor 0 register number | (select << 5)   (or for the
+ *           cfc0 instruction, the coprocessor control register number)
+ *  arg[2] = relative addr of this instruction within the page
+ */
+X(cfc0)
+{
+	int fs = ic->arg[1] & 31;
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc |= ic->arg[2];
+	/*  TODO: cause exception if necessary  */
+	reg(ic->arg[0]) = (int32_t)cpu->cd.mips.coproc[0]->fcr[fs];
+}
+X(mfc0)
+{
+	int rd = ic->arg[1] & 31, select = ic->arg[1] >> 5;
+	uint64_t tmp;
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc |= ic->arg[2];
+	/*  TODO: cause exception if necessary  */
+	coproc_register_read(cpu, cpu->cd.mips.coproc[0], rd, &tmp, select);
+	reg(ic->arg[0]) = (int32_t)tmp;
+}
+X(mfc0_select0)
+{
+	/*  Fast int32_t read, with no side effects:  */
+	int rd = ic->arg[1] & 31;
+#if 0
+	uint64_t tmp;
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc |= ic->arg[2];
+	/*  TODO: cause exception if necessary  */
+#endif
+	reg(ic->arg[0]) = (int32_t)cpu->cd.mips.coproc[0]->reg[rd];
+}
+X(mtc0)
+{
+	int rd = ic->arg[1] & 31, select = ic->arg[1] >> 5;
+	uint64_t tmp = (int32_t) reg(ic->arg[0]);
+
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc |= ic->arg[2];
+
+	/*  TODO: cause exception if necessary  */
+	coproc_register_write(cpu, cpu->cd.mips.coproc[0], rd, &tmp, 0, select);
+
+	/*
+	 *  Interrupts enabled, and any interrupt pending? (Note/TODO: This
+	 *  code is duplicated in cpu_dyntrans.c. Fix this?)
+	 */
+	if (rd == COP0_STATUS && !cpu->delay_slot) {
+		uint32_t status = cpu->cd.mips.coproc[0]->reg[COP0_STATUS];
+		uint32_t cause = cpu->cd.mips.coproc[0]->reg[COP0_CAUSE];
+		/*  NOTE: STATUS_IE happens to match the enable bit also
+		    on R2000/R3000, so this is ok.  */
+		if (cpu->cd.mips.cpu_type.exc_model != EXC3K) {
+			if (status & (STATUS_EXL | STATUS_ERL))
+				status &= ~STATUS_IE;
+		}
+		/*  Ugly R5900 special case:  (TODO: move this?)  */
+		if (cpu->cd.mips.cpu_type.rev == MIPS_R5900 &&
+		    !(status & R5900_STATUS_EIE))
+			status &= ~STATUS_IE;
+		if (status & STATUS_IE && (status & cause & STATUS_IM_MASK)) {
+			cpu->pc += sizeof(uint32_t);
+			mips_cpu_exception(cpu, EXCEPTION_INT, 0, 0,0,0,0,0);
+		}
+	}
+}
+X(dmfc0)
+{
+	int rd = ic->arg[1] & 31, select = ic->arg[1] >> 5;
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc |= ic->arg[2];
+	/*  TODO: cause exception if necessary  */
+	coproc_register_read(cpu, cpu->cd.mips.coproc[0], rd,
+	    (uint64_t *)ic->arg[0], select);
+}
+X(dmfc0_select0)
+{
+	/*  Fast int64_t read, with no side effects:  */
+	int rd = ic->arg[1] & 31;
+#if 0
+	uint64_t tmp;
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc |= ic->arg[2];
+	/*  TODO: cause exception if necessary  */
+#endif
+	reg(ic->arg[0]) = cpu->cd.mips.coproc[0]->reg[rd];
+}
+X(dmtc0)
+{
+	int rd = ic->arg[1] & 31, select = ic->arg[1] >> 5;
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc |= ic->arg[2];
+	/*  TODO: cause exception if necessary  */
+	coproc_register_write(cpu, cpu->cd.mips.coproc[0], rd,
+	    (uint64_t *)ic->arg[0], 1, select);
+}
+
+
+/*
+ *  cop1_bc:  Floating point conditional branch.
+ *
+ *  arg[0] = cc
+ *  arg[1] = nd (=2) and tf (=1) bits
+ *  arg[2] = offset (relative to start of this page)
+ */
+X(cop1_bc)
+{
+	MODE_int_t old_pc = cpu->pc;
+	int x, cc = ic->arg[0];
+
+	COPROC_AVAILABILITY_CHECK(1);
+
+	/*  Get the correct condition code bit:  */
+	if (cc == 0)
+		x = (cpu->cd.mips.coproc[1]->fcr[MIPS_FPU_FCSR]
+		    >> MIPS_FCSR_FCC0_SHIFT) & 1;
+	else
+		x = (cpu->cd.mips.coproc[1]->fcr[MIPS_FPU_FCSR]
+		    >> (MIPS_FCSR_FCC1_SHIFT + cc-1)) & 1;
+
+	/*  Branch on false? Then invert the truth value.  */
+	if (!(ic->arg[1] & 1))
+		x ^= 1;
+
+	/*  Execute the delay slot (except if it is nullified):  */
+	cpu->delay_slot = TO_BE_DELAYED;
+	if (x || !(ic->arg[1] & 2))
+		ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		/*  Note: Must be non-delayed when jumping to the new pc:  */
+		cpu->delay_slot = NOT_DELAYED;
+		if (x) {
+			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT);
+			cpu->pc = old_pc + (int32_t)ic->arg[2];
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.mips.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  cop1_slow:  Fallback to legacy cop1 code. (Slow, but it should work.)
+ */
+X(cop1_slow)
+{
+	COPROC_AVAILABILITY_CHECK(1);
+
+	coproc_function(cpu, cpu->cd.mips.coproc[1], 1, ic->arg[0], 0, 1);
+}
+
+
+/*
+ *  syscall, break:  Synchronize the PC and cause an exception.
+ */
+X(syscall)
+{
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<< MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	mips_cpu_exception(cpu, EXCEPTION_SYS, 0, 0, 0, 0, 0, 0);
+}
+X(break)
+{
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<< MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	mips_cpu_exception(cpu, EXCEPTION_BP, 0, 0, 0, 0, 0, 0);
+}
+X(reboot)
+{
+	if (!cop0_availability_check(cpu, ic))
+		return;
+
+	cpu->running = false;
+	cpu->cd.mips.next_ic = &nothing_call;
+}
+
+
+/*
+ *  promemul:  PROM software emulation.
+ */
+X(promemul)
+{
+	/*  Synchronize the PC and call the correct emulation layer:  */
+	MODE_int_t old_pc;
+	int res, low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<< MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	old_pc = cpu->pc;
+
+	switch (cpu->machine->machine_type) {
+	case MACHINE_PMAX:
+		res = decstation_prom_emul(cpu);
+		break;
+	case MACHINE_PS2:
+		res = playstation2_sifbios_emul(cpu);
+		break;
+	case MACHINE_ARC:
+	case MACHINE_SGI:
+		res = arcbios_emul(cpu);
+		break;
+	case MACHINE_EVBMIPS:
+		res = yamon_emul(cpu);
+		break;
+	default:fatal("TODO: Unimplemented machine type for PROM magic trap\n");
+		exit(1);
+	}
+
+	if (res) {
+		/*  Return from the PROM call:  */
+		cpu->pc = (MODE_int_t)cpu->cd.mips.gpr[MIPS_GPR_RA];
+		cpu->delay_slot = NOT_DELAYED;
+
+		if (cpu->machine->show_trace_tree)
+			cpu_functioncall_trace_return(cpu);
+	} else {
+		/*  The PROM call blocks.  */
+		cpu->n_translated_instrs += 10;
+		cpu->pc = old_pc;
+	}
+
+	quick_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  tlbw: TLB write indexed and random
+ *
+ *  arg[0] = 1 for random, 0 for indexed
+ *  arg[2] = relative addr of this instruction within the page
+ */
+X(tlbw)
+{
+	if (!cop0_availability_check(cpu, ic))
+		return;
+
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc |= ic->arg[2];
+	coproc_tlbwri(cpu, ic->arg[0]);
+}
+
+
+/*
+ *  tlbp: TLB probe
+ *  tlbr: TLB read
+ *
+ *  arg[2] = relative addr of this instruction within the page
+ */
+X(tlbp)
+{
+	if (!cop0_availability_check(cpu, ic))
+		return;
+
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc |= ic->arg[2];
+	coproc_tlbpr(cpu, 0);
+}
+X(tlbr)
+{
+	if (!cop0_availability_check(cpu, ic))
+		return;
+
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc |= ic->arg[2];
+	coproc_tlbpr(cpu, 1);
+}
+
+
+/*
+ *  ei_or_di:  MIPS32/64 rev 2, Enable or disable interrupts
+ *
+ *  arg[0] = ptr to rt
+ *  arg[1] = non-zero to enable interrupts
+ */
+X(ei_or_di)
+{
+	reg(ic->arg[0]) = cpu->cd.mips.coproc[0]->reg[COP0_STATUS];
+	if (ic->arg[1])
+		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |= STATUS_IE;
+	else
+		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_IE;
+}
+
+
+/*
+ *  rfe: Return from exception handler (R2000/R3000)
+ */
+X(rfe)
+{
+	if (!cop0_availability_check(cpu, ic))
+		return;
+
+	/*  Just rotate the interrupt/user bits:  */
+	cpu->cd.mips.coproc[0]->reg[COP0_STATUS] =
+	    (cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & ~0x3f) |
+	    ((cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & 0x3c) >> 2);
+
+	/*
+	 *  Note: no pc to pointers conversion is necessary here. Usually the
+	 *  rfe instruction resides in the delay slot of a jr k0/k1, and
+	 *  it is up to that instruction to do the pointer conversion.
+	 */
+}
+
+
+/*
+ *  eret: Return from exception handler (non-R3000 style)
+ */
+X(eret)
+{
+	if (!cop0_availability_check(cpu, ic))
+		return;
+
+	if (cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & STATUS_ERL) {
+		cpu->pc = cpu->cd.mips.coproc[0]->reg[COP0_ERROREPC];
+		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_ERL;
+	} else {
+		cpu->pc = cpu->cd.mips.coproc[0]->reg[COP0_EPC];
+		cpu->delay_slot = 0;             
+		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_EXL;
+	}
+
+	quick_pc_to_pointers(cpu);
+
+	cpu->cd.mips.rmw = 0;   /*  the "LL bit"  */
+}
+
+
+/*
+ *  deret: Return from debug (EJTAG) handler
+ */
+X(deret)
+{
+	if (!cop0_availability_check(cpu, ic))
+		return;
+
+	/*
+	 *  According to the MIPS64 manual, deret loads PC from the DEPC cop0
+	 *  register, and jumps there immediately. No delay slot.
+	 *
+	 *  TODO: This instruction is only available if the processor is in
+	 *  debug mode. (What does that mean?)
+	 *
+	 *  TODO: This instruction is undefined in a delay slot.
+	 */
+
+	cpu->pc = cpu->cd.mips.coproc[0]->reg[COP0_DEPC];
+	cpu->delay_slot = 0;
+	cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_EXL;
+	quick_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  idle:  Called from the implementation of wait, or netbsd_pmax_idle.
+ */
+X(idle)
+{
+	/*
+	 *  If there is an interrupt, then just return. Otherwise
+	 *  re-run the wait instruction (after a delay).
+	 */
+	uint32_t status = cpu->cd.mips.coproc[0]->reg[COP0_STATUS];
+	uint32_t cause = cpu->cd.mips.coproc[0]->reg[COP0_CAUSE];
+
+	if (cpu->cd.mips.cpu_type.exc_model != EXC3K) {
+		if (status & (STATUS_EXL | STATUS_ERL))
+			status &= ~STATUS_IE;
+	}
+
+	/*  Ugly R5900 special case:  (TODO: move this?)  */
+	if (cpu->cd.mips.cpu_type.rev == MIPS_R5900 &&
+	    !(status & R5900_STATUS_EIE))
+		status &= ~STATUS_IE;
+	if (status & STATUS_IE && (status & cause & STATUS_IM_MASK))
+		return;
+
+	// Sync pc:
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+
+	cpu->cd.mips.next_ic = ic;
+	cpu->is_halted = true;
+
+	cpu->wants_to_idle = true;
+	cpu->n_translated_instrs += N_DYNTRANS_IDLE_BREAK;
+	cpu->cd.mips.next_ic = &nothing_call;
+}
+
+
+/*
+ *  wait: Wait for external interrupt.
+ */
+X(wait)
+{
+	if (!cop0_availability_check(cpu, ic))
+		return;
+
+	instr(idle)(cpu, ic);
+}
+
+
+/*
+ *  rdhwr: Read CPUNum hardware register into gpr (MIPS32/64 rev 2).
+ *
+ *  arg[0] = ptr to rt (destination register)
+ */
+X(rdhwr_cpunum)
+{
+	reg(ic->arg[0]) = cpu->cpu_id;
+}
+
+
+/*
+ *  rdhwr: Read CC (cycle count) register into gpr (MIPS32/64 rev 2).
+ *
+ *  arg[0] = ptr to rt (destination register)
+ */
+X(rdhwr_cc)
+{
+	reg(ic->arg[0]) = cpu->cd.mips.coproc[0]->reg[COP0_COUNT];
+}
+
+
+#include "tmp_mips_loadstore.c"
+
+
+/*
+ *  Load linked / store conditional:
+ *
+ *  A Load-linked instruction initiates a RMW (read-modify-write) sequence.
+ *  COP0_LLADDR is updated for diagnostic purposes, except for CPUs in the
+ *  R10000 family.
+ *
+ *  A Store-conditional instruction ends the sequence.
+ *
+ *  arg[0] = ptr to rt
+ *  arg[1] = ptr to rs
+ *  arg[2] = int32_t imm
+ */
+X(ll)
+{
+	MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
+	int low_pc;
+	uint8_t word[sizeof(uint32_t)];
+
+	/*  Synch. PC and load using slow memory_rw():  */
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+
+	if (addr & (sizeof(word)-1)) {
+		fatal("TODO: load linked unaligned access: exception\n");
+		exit(1);
+	}
+
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, word,
+	    sizeof(word), MEM_READ, CACHE_DATA)) {
+		/*  An exception occurred.  */
+		return;
+	}
+
+	cpu->cd.mips.rmw = 1;
+	cpu->cd.mips.rmw_addr = addr;
+	cpu->cd.mips.rmw_len = sizeof(word);
+	if (cpu->cd.mips.cpu_type.exc_model != MMU10K)
+		cpu->cd.mips.coproc[0]->reg[COP0_LLADDR] =
+		    (addr >> 4) & 0xffffffffULL;
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		reg(ic->arg[0]) = (int32_t) (word[0] + (word[1] << 8)
+		    + (word[2] << 16) + (word[3] << 24));
+	else
+		reg(ic->arg[0]) = (int32_t) (word[3] + (word[2] << 8)
+		    + (word[1] << 16) + (word[0] << 24));
+}
+X(lld)
+{
+	MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
+	int low_pc;
+	uint8_t word[sizeof(uint64_t)];
+
+	/*  Synch. PC and load using slow memory_rw():  */
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+
+	if (addr & (sizeof(word)-1)) {
+		fatal("TODO: load linked unaligned access: exception\n");
+		exit(1);
+	}
+
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, word,
+	    sizeof(word), MEM_READ, CACHE_DATA)) {
+		/*  An exception occurred.  */
+		return;
+	}
+
+	cpu->cd.mips.rmw = 1;
+	cpu->cd.mips.rmw_addr = addr;
+	cpu->cd.mips.rmw_len = sizeof(word);
+	if (cpu->cd.mips.cpu_type.exc_model != MMU10K)
+		cpu->cd.mips.coproc[0]->reg[COP0_LLADDR] =
+		    (addr >> 4) & 0xffffffffULL;
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		reg(ic->arg[0]) = word[0] + (word[1] << 8)
+		    + (word[2] << 16) + ((uint64_t)word[3] << 24) +
+		    + ((uint64_t)word[4] << 32) + ((uint64_t)word[5] << 40)
+		    + ((uint64_t)word[6] << 48) + ((uint64_t)word[7] << 56);
+	else
+		reg(ic->arg[0]) = word[7] + (word[6] << 8)
+		    + (word[5] << 16) + ((uint64_t)word[4] << 24) +
+		    + ((uint64_t)word[3] << 32) + ((uint64_t)word[2] << 40)
+		    + ((uint64_t)word[1] << 48) + ((uint64_t)word[0] << 56);
+}
+X(sc)
+{
+	MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
+	uint64_t r = reg(ic->arg[0]);
+	int low_pc, i;
+	uint8_t word[sizeof(uint32_t)];
+
+	/*  Synch. PC and store using slow memory_rw():  */
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+
+	if (addr & (sizeof(word)-1)) {
+		fatal("TODO: sc unaligned access: exception\n");
+		exit(1);
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		word[0]=r; word[1]=r>>8; word[2]=r>>16; word[3]=r>>24;
+	} else {
+		word[3]=r; word[2]=r>>8; word[1]=r>>16; word[0]=r>>24;
+	}
+
+	/*  If rmw is 0, then the store failed.  (This cache-line was written
+	    to by someone else.)  */
+	if (cpu->cd.mips.rmw == 0 || (MODE_int_t)cpu->cd.mips.rmw_addr != addr
+	    || cpu->cd.mips.rmw_len != sizeof(word)) {
+		reg(ic->arg[0]) = 0;
+		cpu->cd.mips.rmw = 0;
+		return;
+	}
+
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, word,
+	    sizeof(word), MEM_WRITE, CACHE_DATA)) {
+		/*  An exception occurred.  */
+		return;
+	}
+
+	/*  We succeeded. Let's invalidate everybody else's store to this
+	    cache line:  */
+	for (i=0; i<cpu->machine->ncpus; i++) {
+		if (cpu->machine->cpus[i]->cd.mips.rmw) {
+			uint64_t yaddr = addr, xaddr = cpu->machine->cpus[i]->
+			    cd.mips.rmw_addr;
+			uint64_t mask = ~(cpu->machine->cpus[i]->
+			    cd.mips.cache_linesize[CACHE_DATA] - 1);
+			xaddr &= mask;
+			yaddr &= mask;
+			if (xaddr == yaddr)
+				cpu->machine->cpus[i]->cd.mips.rmw = 0;
+		}
+	}
+
+	reg(ic->arg[0]) = 1;
+	cpu->cd.mips.rmw = 0;
+}
+X(scd)
+{
+	MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
+	uint64_t r = reg(ic->arg[0]);
+	int low_pc, i;
+	uint8_t word[sizeof(uint64_t)];
+
+	/*  Synch. PC and store using slow memory_rw():  */
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+
+	if (addr & (sizeof(word)-1)) {
+		fatal("TODO: sc unaligned access: exception\n");
+		exit(1);
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		word[0]=r;     word[1]=r>>8; word[2]=r>>16; word[3]=r>>24;
+		word[4]=r>>32; word[5]=r>>40; word[6]=r>>48; word[7]=r>>56;
+	} else {
+		word[7]=r;     word[6]=r>>8; word[5]=r>>16; word[4]=r>>24;
+		word[3]=r>>32; word[2]=r>>40; word[1]=r>>48; word[0]=r>>56;
+	}
+
+	/*  If rmw is 0, then the store failed.  (This cache-line was written
+	    to by someone else.)  */
+	if (cpu->cd.mips.rmw == 0 || (MODE_int_t)cpu->cd.mips.rmw_addr != addr
+	    || cpu->cd.mips.rmw_len != sizeof(word)) {
+		reg(ic->arg[0]) = 0;
+		cpu->cd.mips.rmw = 0;
+		return;
+	}
+
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, word,
+	    sizeof(word), MEM_WRITE, CACHE_DATA)) {
+		/*  An exception occurred.  */
+		return;
+	}
+
+	/*  We succeeded. Let's invalidate everybody else's store to this
+	    cache line:  */
+	for (i=0; i<cpu->machine->ncpus; i++) {
+		if (cpu->machine->cpus[i]->cd.mips.rmw) {
+			uint64_t yaddr = addr, xaddr = cpu->machine->cpus[i]->
+			    cd.mips.rmw_addr;
+			uint64_t mask = ~(cpu->machine->cpus[i]->
+			    cd.mips.cache_linesize[CACHE_DATA] - 1);
+			xaddr &= mask;
+			yaddr &= mask;
+			if (xaddr == yaddr)
+				cpu->machine->cpus[i]->cd.mips.rmw = 0;
+		}
+	}
+
+	reg(ic->arg[0]) = 1;
+	cpu->cd.mips.rmw = 0;
+}
+
+
+/*
+ *  lwc1, swc1:  Coprocessor 1 load/store (32-bit)
+ *  ldc1, sdc1:  Coprocessor 1 load/store (64-bit)
+ *
+ *  arg[0] = ptr to coprocessor register
+ *  arg[1] = ptr to rs (base pointer register)
+ *  arg[2] = int32_t imm
+ */
+X(lwc1)
+{
+	COPROC_AVAILABILITY_CHECK(1);
+
+#ifdef MODE32
+	mips32_loadstore
+#else
+	mips_loadstore
+#endif
+	    [ (cpu->byte_order == EMUL_LITTLE_ENDIAN? 0 : 16) + 2 * 2 + 1]
+	    (cpu, ic);
+}
+X(swc1)
+{
+	COPROC_AVAILABILITY_CHECK(1);
+
+#ifdef MODE32
+	mips32_loadstore
+#else
+	mips_loadstore
+#endif
+	    [ (cpu->byte_order == EMUL_LITTLE_ENDIAN? 0 : 16) + 8 + 2 * 2]
+	    (cpu, ic);
+}
+X(ldc1)
+{
+	int use_fp_pairs =
+	    !(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & STATUS_FR);
+	uint64_t fpr, *backup_ptr;
+
+	COPROC_AVAILABILITY_CHECK(1);
+
+	backup_ptr = (uint64_t *) ic->arg[0];
+	ic->arg[0] = (size_t) &fpr;
+
+#ifdef MODE32
+	mips32_loadstore
+#else
+	mips_loadstore
+#endif
+	    [ (cpu->byte_order == EMUL_LITTLE_ENDIAN? 0 : 16) + 3 * 2 + 1]
+	    (cpu, ic);
+
+	if (use_fp_pairs) {
+		backup_ptr[0] = (int64_t)(int32_t) fpr;
+		backup_ptr[1] = (int64_t)(int32_t) (fpr >> 32);
+	} else {
+		*backup_ptr = fpr;
+	}
+
+	ic->arg[0] = (size_t) backup_ptr;
+}
+X(sdc1)
+{
+	int use_fp_pairs =
+	    !(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & STATUS_FR);
+	uint64_t fpr, *backup_ptr;
+
+	COPROC_AVAILABILITY_CHECK(1);
+
+	backup_ptr = (uint64_t *) ic->arg[0];
+	ic->arg[0] = (size_t) &fpr;
+
+	if (use_fp_pairs) {
+		uint32_t lo = backup_ptr[0];
+		uint32_t hi = backup_ptr[1];
+		fpr = (((uint64_t)hi) << 32) | lo;
+	} else {
+		fpr = *backup_ptr;
+	}
+
+#ifdef MODE32
+	mips32_loadstore
+#else
+	mips_loadstore
+#endif
+	    [ (cpu->byte_order == EMUL_LITTLE_ENDIAN? 0 : 16) + 8 + 3 * 2]
+	    (cpu, ic);
+
+	ic->arg[0] = (size_t) backup_ptr;
+}
+
+
+/*
+ *  Unaligned loads/stores:
+ *
+ *  arg[0] = ptr to rt
+ *  arg[1] = ptr to rs
+ *  arg[2] = int32_t imm
+ */
+X(lwl) { mips_unaligned_loadstore(cpu, ic, 1, sizeof(uint32_t), 0); }
+X(lwr) { mips_unaligned_loadstore(cpu, ic, 0, sizeof(uint32_t), 0); }
+X(ldl) { mips_unaligned_loadstore(cpu, ic, 1, sizeof(uint64_t), 0); }
+X(ldr) { mips_unaligned_loadstore(cpu, ic, 0, sizeof(uint64_t), 0); }
+X(swl) { mips_unaligned_loadstore(cpu, ic, 1, sizeof(uint32_t), 1); }
+X(swr) { mips_unaligned_loadstore(cpu, ic, 0, sizeof(uint32_t), 1); }
+X(sdl) { mips_unaligned_loadstore(cpu, ic, 1, sizeof(uint64_t), 1); }
+X(sdr) { mips_unaligned_loadstore(cpu, ic, 0, sizeof(uint64_t), 1); }
+
+
+/*
+ *  di, ei: R5900 interrupt enable/disable.
+ *
+ *  TODO: check the R5900_STATUS_EDI bit in the status register. If it is
+ *  cleared, and we are not running in kernel mode, then both the EI and DI
+ *  instructions should be treated as NOPs!
+ */
+X(di_r5900)
+{
+	if (!cop0_availability_check(cpu, ic))
+		return;
+
+	cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~R5900_STATUS_EIE;
+}
+X(ei_r5900)
+{
+	if (!cop0_availability_check(cpu, ic))
+		return;
+
+	cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |= R5900_STATUS_EIE;
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  memset_addiu_bne_sw:
+ *
+ *  s:	addiu	rX,rX,4			rX = arg[0] and arg[1]
+ *	bne	rY,rX,s  (or rX,rY,s)	rt=arg[1], rs=arg[0]
+ *	sw	rZ,-4(rX)		rt=arg[0], rs=arg[1]
+ */
+X(memset_addiu_bne_sw)
+{
+	MODE_uint_t rX = reg(ic->arg[0]), rZ = reg(ic[2].arg[0]);
+	uint64_t *rYp = (uint64_t *) ic[1].arg[0];
+	MODE_uint_t rY, bytes_to_write;
+	unsigned char *page;
+	int partial = 0;
+
+#ifdef MODE32
+	page = cpu->cd.mips.host_store[rX >> 12];
+#else
+	{
+		const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+		const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+		const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+		uint32_t x1 = (rX >> (64-DYNTRANS_L1N)) & mask1;
+		uint32_t x2 = (rX >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+		uint32_t x3 = (rX >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
+		struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.mips.l1_64[x1];
+		struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
+		page = l3->host_store[x3];
+	}
+#endif
+
+	/*  Fallback:  */
+	if (cpu->delay_slot || page == NULL || (rX & 3) != 0 || rZ != 0) {
+		instr(addiu)(cpu, ic);
+		return;
+	}
+
+	if (rYp == (uint64_t *) ic->arg[0])
+		rYp = (uint64_t *) ic[1].arg[1];
+
+	rY = reg(rYp);
+
+	bytes_to_write = rY - rX;
+	if ((rX & 0xfff) + bytes_to_write > 0x1000) {
+		bytes_to_write = 0x1000 - (rX & 0xfff);
+		partial = 1;
+	}
+
+	/*  printf("rX = %08x\n", (int)rX);
+	    printf("rY = %08x\n", (int)rY);
+	    printf("rZ = %08x\n", (int)rZ);
+	    printf("%i bytes\n", (int)bytes_to_write);  */
+
+	memset(page + (rX & 0xfff), 0, bytes_to_write);
+
+	reg(ic->arg[0]) = rX + bytes_to_write;
+
+	cpu->n_translated_instrs += bytes_to_write / 4 * 3 - 1;
+	cpu->cd.mips.next_ic = partial?
+	    (struct mips_instr_call *) &ic[0] :
+	    (struct mips_instr_call *) &ic[3];
+}
+
+
+/*  multi_{l,s}w_2, _3, etc.  */
+#include "tmp_mips_loadstore_multi.c"
+
+
+/*
+ *  multi_addu_3:
+ */
+X(multi_addu_3)
+{
+	/*  Fallback:  */
+	if (cpu->delay_slot) {
+		instr(addu)(cpu, ic);
+		return;
+	}
+
+	reg(ic[0].arg[2]) = (int32_t)(reg(ic[0].arg[0]) + reg(ic[0].arg[1]));
+	reg(ic[1].arg[2]) = (int32_t)(reg(ic[1].arg[0]) + reg(ic[1].arg[1]));
+	reg(ic[2].arg[2]) = (int32_t)(reg(ic[2].arg[0]) + reg(ic[2].arg[1]));
+	cpu->n_translated_instrs += 2;
+	cpu->cd.mips.next_ic = ic + 3;
+}
+
+
+/*
+ *  netbsd_r3k_picache_do_inv:
+ *
+ *  ic[0]	mtc0	rV,status
+ *     1	nop
+ *     2	nop
+ *     3  s:	addiu	rX,rX,4
+ *     4	bne	rY,rX,s
+ *     5	sb	zr,-4(rX)
+ *     6	nop
+ *     7	nop
+ *     8	mtc0	rT,status
+ */
+X(netbsd_r3k_picache_do_inv)
+{
+	MODE_uint_t rx = reg(ic[3].arg[0]), ry = reg(ic[4].arg[1]);
+
+	/*  Fallback if the environment isn't exactly right:  */
+	if (!(reg(ic[0].arg[0]) & MIPS1_ISOL_CACHES) ||
+	    (rx & 3) || (ry & 3) || cpu->delay_slot) {
+		instr(mtc0)(cpu, ic);
+		return;
+        }
+
+	reg(ic[3].arg[0]) = ry;
+	cpu->n_translated_instrs += (ry - rx + 4) / 4 * 3 + 4;
+
+	/*  Run the last mtc0 instruction:  */
+	cpu->cd.mips.next_ic = ic + 8;
+}
+
+
+#ifdef MODE32
+/*
+ *  netbsd_pmax_idle():
+ *
+ *  s:  lui     rX, hi
+ *      lw      rY, lo(rX)
+ *      nop
+ *      beq     zr, rY, s
+ *      nop
+ */
+X(netbsd_pmax_idle)
+{
+	uint32_t addr, pageindex, i;
+	int32_t *page;
+
+	reg(ic[0].arg[0]) = (int32_t)ic[0].arg[1];
+
+	addr = reg(ic[0].arg[0]) + (int32_t)ic[1].arg[2];
+	pageindex = addr >> 12;
+	i = (addr & 0xfff) >> 2;
+	page = (int32_t *) cpu->cd.mips.host_load[pageindex];
+
+	/*  Fallback:  */
+	if (cpu->delay_slot || page == NULL || page[i] != 0)
+		return;
+
+	instr(idle)(cpu, ic);
+}
+
+
+/*
+ *  linux_pmax_idle():
+ *
+ *  s:  lui     rX, hi
+ *      lw      rX, lo(rX)
+ *      nop
+ *      bne     zr, rX, ...
+ *      nop
+ *      lw      rX, ofs(gp)
+ *      nop
+ *      beq     zr, rX, s
+ *      nop
+ */
+X(linux_pmax_idle)
+{
+	uint32_t addr, addr2, pageindex, pageindex2, i, i2;
+	int32_t *page, *page2;
+
+	reg(ic[0].arg[0]) = (int32_t)ic[0].arg[1];
+
+	addr = reg(ic[0].arg[0]) + (int32_t)ic[1].arg[2];
+	pageindex = addr >> 12;
+	i = (addr & 0xfff) >> 2;
+	page = (int32_t *) cpu->cd.mips.host_load[pageindex];
+
+	addr2 = reg(ic[5].arg[1]) + (int32_t)ic[5].arg[2];
+	pageindex2 = addr2 >> 12;
+	i2 = (addr2 & 0xfff) >> 2;
+	page2 = (int32_t *) cpu->cd.mips.host_load[pageindex2];
+
+	/*  Fallback:  */
+	if (cpu->delay_slot || page == NULL || page[i] != 0 || page2[i2] != 0)
+		return;
+
+	instr(idle)(cpu, ic);
+}
+#endif
+
+
+/*
+ *  strlen_lb_addiu_bne_nop():
+ *
+ *  Used by some versions of NetBSD.
+ *
+ *  s:	lb      rV,0(rX)	(lb = signed, lbu = unsigned)
+ *	addiu   rX,rX,1
+ *	bne	zr,rV,s
+ *	nop
+ */
+X(strlen_lb_addiu_bne_nop)
+{
+	MODE_uint_t rx = reg(ic[0].arg[1]);
+	MODE_int_t rv;
+	signed char *page;
+	int i;
+
+#ifdef MODE32
+	page = (signed char *) cpu->cd.mips.host_load[rx >> 12];
+#else
+	{
+		const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+		const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+		const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+		uint32_t x1 = (rx >> (64-DYNTRANS_L1N)) & mask1;
+		uint32_t x2 = (rx >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+		uint32_t x3 = (rx >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
+		struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.mips.l1_64[x1];
+		struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
+		page = (signed char *) l3->host_load[x3];
+	}
+#endif
+
+	/*
+	 *  Fallback:
+	 *
+	 *  If the first instruction (the lb/lbu) is in the delay slot of a
+	 *  branch instruction, we bail out.
+	 *
+	 *  Also, if the page for the strlen string to measure is not in the
+	 *  fast host_load arrays, we bail out and let the normal lb/lbu
+	 *  implementation handle it (and if the string is long enough, we
+	 *  will get back into this instruction combination code anyway).
+	 *
+	 *  The reason why we can run a fixed load instruction as the fall-
+	 *  back (say, signed lb) rather than checking whether to run lb or
+	 *  lbu, is as follows:
+	 *
+	 *  If the loaded byte is 0x00, we break out of the strlen loop. This
+	 *  value would be the same regardless of whether lb or lbu is used.
+	 *
+	 *  If the loaded byte is not 0x00, say, 0x8a, it does not matter
+	 *  whether the loaded rV value is 0xffffffffffffff8a or
+	 *  0x000000000000008a. The only way to get out of the strlen loop is
+	 *  to read rV as 0x00, _except_ for CPU exceptions (either interrupts
+	 *  or page-fault exceptions). But it is extremely unlikely that any
+	 *  exception handling code in any guest OS would do anything other
+	 *  than preserve rV (whatever its value is) and restore it when the
+	 *  exception handling is done. So this discrepancy should be ok.
+	 */
+	if (cpu->delay_slot || page == NULL) {
+#ifdef MODE32
+		mips32_loadstore[1](cpu, ic);
+#else
+		mips_loadstore[1](cpu, ic);
+#endif
+		return;
+	}
+
+	i = rx & 0xfff;
+
+	/*
+	 *  TODO: This loop can be optimized further for optimal
+	 *  performance on the host, e.g. by reading full words...
+	 */
+	do {
+		rv = page[i ++];
+	} while (i < 0x1000 && rv != 0);
+
+	cpu->n_translated_instrs += (i - (rx & 0xfff)) * 4 - 1;
+
+	reg(ic[0].arg[1]) = (rx & ~0xfff) + i;
+	reg(ic[2].arg[0]) = rv;
+
+	/*  Done with the loop? Or continue on the next rx page?  */
+	if (rv == 0)
+		cpu->cd.mips.next_ic = ic + 4;
+	else
+		cpu->cd.mips.next_ic = ic;
+}
+
+
+/*
+ *  addiu_bne_samepage_addiu:
+ */
+X(addiu_bne_samepage_addiu)
+{
+	MODE_uint_t rs, rt;
+
+	if (cpu->delay_slot) {
+		instr(addiu)(cpu, ic);
+		return;
+	}
+
+	cpu->n_translated_instrs += 2;
+	reg(ic[0].arg[1]) = (int32_t)
+	    ((int32_t)reg(ic[0].arg[0]) + (int32_t)ic[0].arg[2]);
+	rs = reg(ic[1].arg[0]);
+	rt = reg(ic[1].arg[1]);
+	reg(ic[2].arg[1]) = (int32_t)
+	    ((int32_t)reg(ic[2].arg[0]) + (int32_t)ic[2].arg[2]);
+	if (rs != rt)
+		cpu->cd.mips.next_ic = (struct mips_instr_call *) ic[1].arg[2];
+	else
+		cpu->cd.mips.next_ic = ic + 3;
+}
+
+
+/*
+ *  xor_andi_sll:
+ */
+X(xor_andi_sll)
+{
+	/*  Fallback:  */
+	if (cpu->delay_slot) {
+		instr(xor)(cpu, ic);
+		return;
+	}
+
+	reg(ic[0].arg[2]) = reg(ic[0].arg[0]) ^ reg(ic[0].arg[1]);
+	reg(ic[1].arg[1]) = reg(ic[1].arg[0]) & (uint32_t)ic[1].arg[2];
+	reg(ic[2].arg[2]) = (int32_t)(reg(ic[2].arg[0])<<(int32_t)ic[2].arg[1]);
+
+	cpu->n_translated_instrs += 2;
+	cpu->cd.mips.next_ic = ic + 3;
+}
+
+
+/*
+ *  andi_sll:
+ */
+X(andi_sll)
+{
+	/*  Fallback:  */
+	if (cpu->delay_slot) {
+		instr(andi)(cpu, ic);
+		return;
+	}
+
+	reg(ic[0].arg[1]) = reg(ic[0].arg[0]) & (uint32_t)ic[0].arg[2];
+	reg(ic[1].arg[2]) = (int32_t)(reg(ic[1].arg[0])<<(int32_t)ic[1].arg[1]);
+
+	cpu->n_translated_instrs ++;
+	cpu->cd.mips.next_ic = ic + 2;
+}
+
+
+/*
+ *  lui_ori:
+ */
+X(lui_ori)
+{
+	/*  Fallback:  */
+	if (cpu->delay_slot) {
+		instr(set)(cpu, ic);
+		return;
+	}
+
+	reg(ic[0].arg[0]) = (int32_t)ic[0].arg[1];
+	reg(ic[1].arg[1]) = reg(ic[1].arg[0]) | (uint32_t)ic[1].arg[2];
+
+	cpu->n_translated_instrs ++;
+	cpu->cd.mips.next_ic = ic + 2;
+}
+
+
+/*
+ *  lui_addiu:
+ */
+X(lui_addiu)
+{
+	/*  Fallback:  */
+	if (cpu->delay_slot) {
+		instr(set)(cpu, ic);
+		return;
+	}
+
+	reg(ic[0].arg[0]) = (int32_t)ic[0].arg[1];
+	reg(ic[1].arg[1]) = (int32_t)
+	    ((int32_t)reg(ic[1].arg[0]) + (int32_t)ic[1].arg[2]);
+
+	cpu->n_translated_instrs ++;
+	cpu->cd.mips.next_ic = ic + 2;
+}
+
+
+/*
+ *  b_samepage_addiu:
+ *
+ *  Combination of branch within the same page, followed by addiu.
+ */
+X(b_samepage_addiu)
+{
+	reg(ic[1].arg[1]) = (int32_t)
+	    ( (int32_t)reg(ic[1].arg[0]) + (int32_t)ic[1].arg[2] );
+	cpu->n_translated_instrs ++;
+	cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
+}
+
+
+/*
+ *  b_samepage_daddiu:
+ *
+ *  Combination of branch within the same page, followed by daddiu.
+ */
+X(b_samepage_daddiu)
+{
+	*(uint64_t *)ic[1].arg[1] = *(uint64_t *)ic[1].arg[0] +
+	    (int32_t)ic[1].arg[2];
+	cpu->n_translated_instrs ++;
+	cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
+}
+
+
+/*****************************************************************************/
+
+
+X(end_of_page)
+{
+	/*  Update the PC:  (offset 0, but on the next page)  */
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
+	    MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (MIPS_IC_ENTRIES_PER_PAGE << MIPS_INSTR_ALIGNMENT_SHIFT);
+
+	/*  end_of_page doesn't count as an executed instruction:  */
+	cpu->n_translated_instrs --;
+
+	/*
+	 *  Find the new physpage and update translation pointers.
+	 *
+	 *  Note: This may cause an exception, if e.g. the new page is
+	 *  not accessible.
+	 */
+	quick_pc_to_pointers(cpu);
+
+	/*  Simple jump to the next page (if we are lucky):  */
+	if (cpu->delay_slot == NOT_DELAYED)
+		return;
+
+	/*
+	 *  If we were in a delay slot, and we got an exception while doing
+	 *  quick_pc_to_pointers, then return. The function which called
+	 *  end_of_page should handle this case.
+	 */
+	if (cpu->delay_slot == EXCEPTION_IN_DELAY_SLOT)
+		return;
+
+	/*
+	 *  Tricky situation; the delay slot is on the next virtual page.
+	 *  Calling to_be_translated will translate one instruction manually,
+	 *  execute it, and then discard it.
+	 */
+	/*  fatal("[ end_of_page: delay slot across page boundary! ]\n");  */
+
+	instr(to_be_translated)(cpu, cpu->cd.mips.next_ic);
+
+	/*  The instruction in the delay slot has now executed.  */
+	/*  fatal("[ end_of_page: back from executing the delay slot, %i ]\n",
+	    cpu->delay_slot);  */
+
+	/*  Find the physpage etc of the instruction in the delay slot
+	    (or, if there was an exception, the exception handler):  */
+	quick_pc_to_pointers(cpu);
+}
+
+
+X(end_of_page2)
+{
+	/*  Synchronize PC on the _second_ instruction on the next page:  */
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+
+	/*  This doesn't count as an executed instruction.  */
+	cpu->n_translated_instrs --;
+
+	quick_pc_to_pointers(cpu);
+
+	if (cpu->delay_slot == NOT_DELAYED)
+		return;
+
+	fatal("end_of_page2: fatal error, we're in a delay slot\n");
+	exit(1);
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  Combine:  Multiple SW in a row using the same base register
+ *
+ *	sw	r?,???(rX)
+ *	sw	r?,???(rX)
+ *	sw	r?,???(rX)
+ *	...
+ *
+ *  and memset loops, etc.
+ */
+void COMBINE(sw)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
+	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
+
+	if (n_back < 4)
+		return;
+
+	/*  Convert a multi_sw_4 to a multi_sw_5:  */
+	if ((ic[-4].f == instr(multi_sw_4_be) ||
+	    ic[-4].f == instr(multi_sw_4_le)) &&
+	    ic[-4].arg[1] == ic[0].arg[1]) {
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			ic[-4].f = instr(multi_sw_5_le);
+		else
+			ic[-4].f = instr(multi_sw_5_be);
+	}
+
+	/*  Convert a multi_sw_3 to a multi_sw_4:  */
+	if ((ic[-3].f == instr(multi_sw_3_be) ||
+	    ic[-3].f == instr(multi_sw_3_le)) &&
+	    ic[-3].arg[1] == ic[0].arg[1]) {
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			ic[-3].f = instr(multi_sw_4_le);
+		else
+			ic[-3].f = instr(multi_sw_4_be);
+	}
+
+	/*  Convert a multi_sw_2 to a multi_sw_3:  */
+	if ((ic[-2].f == instr(multi_sw_2_be) ||
+	    ic[-2].f == instr(multi_sw_2_le)) &&
+	    ic[-2].arg[1] == ic[0].arg[1]) {
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			ic[-2].f = instr(multi_sw_3_le);
+		else
+			ic[-2].f = instr(multi_sw_3_be);
+	}
+
+	if (ic[-1].f == ic[0].f && ic[-1].arg[1] == ic[0].arg[1]) {
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			ic[-1].f = instr(multi_sw_2_le);
+		else
+			ic[-1].f = instr(multi_sw_2_be);
+	}
+
+	if (ic[-2].f == instr(addiu) && ic[-2].arg[0] == ic[-2].arg[1] &&
+	    (int32_t)ic[-2].arg[2] == 4 &&
+	    ic[-1].f == instr(bne_samepage) &&
+	    (ic[-1].arg[0] == ic[-2].arg[0] ||
+		ic[-1].arg[1] == ic[-2].arg[0]) &&
+	    ic[-1].arg[0] != ic[-1].arg[1] &&
+	    ic[-1].arg[2] == (size_t) &ic[-2] &&
+	    ic[0].arg[0] != ic[0].arg[1] &&
+	    ic[0].arg[1] == ic[-2].arg[0] && (int32_t)ic[0].arg[2] == -4) {
+		ic[-2].f = instr(memset_addiu_bne_sw);
+	}
+}
+
+
+/*
+ *  Combine:  Multiple LW in a row using the same base register
+ *
+ *	lw	r?,???(rX)
+ *	lw	r?,???(rX)
+ *	lw	r?,???(rX)
+ *	...
+ */
+void COMBINE(lw)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
+	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
+
+	if (n_back < 4)
+		return;
+
+	/*  Convert a multi_lw_4 to a multi_lw_5:  */
+	if ((ic[-4].f == instr(multi_lw_4_be) ||
+	    ic[-4].f == instr(multi_lw_4_le)) &&
+	    ic[-4].arg[1] == ic[0].arg[1] &&
+	    ic[-1].arg[0] != ic[0].arg[1]) {
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			ic[-4].f = instr(multi_lw_5_le);
+		else
+			ic[-4].f = instr(multi_lw_5_be);
+	}
+
+	/*  Convert a multi_lw_3 to a multi_lw_4:  */
+	if ((ic[-3].f == instr(multi_lw_3_be) ||
+	    ic[-3].f == instr(multi_lw_3_le)) &&
+	    ic[-3].arg[1] == ic[0].arg[1] &&
+	    ic[-1].arg[0] != ic[0].arg[1]) {
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			ic[-3].f = instr(multi_lw_4_le);
+		else
+			ic[-3].f = instr(multi_lw_4_be);
+	}
+
+	/*  Convert a multi_lw_2 to a multi_lw_3:  */
+	if ((ic[-2].f == instr(multi_lw_2_be) ||
+	    ic[-2].f == instr(multi_lw_2_le)) &&
+	    ic[-2].arg[1] == ic[0].arg[1] &&
+	    ic[-1].arg[0] != ic[0].arg[1]) {
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			ic[-2].f = instr(multi_lw_3_le);
+		else
+			ic[-2].f = instr(multi_lw_3_be);
+	}
+
+	/*  Note: Loads to the base register are not allowed in slot -1.  */
+	if (ic[-1].f == ic[0].f &&
+	    ic[-1].arg[1] == ic[0].arg[1] &&
+	    ic[-1].arg[0] != ic[0].arg[1]) {
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			ic[-1].f = instr(multi_lw_2_le);
+		else
+			ic[-1].f = instr(multi_lw_2_be);
+	}
+}
+
+
+/*
+ *  Combine:  NetBSD/pmax 3.0 R2000/R3000 physical cache invalidation loop
+ *
+ *  Instruction cache loop:
+ *
+ *  ic[-8]	mtc0	rV,status
+ *     -7	nop
+ *     -6	nop
+ *     -5  s:	addiu	rX,rX,4
+ *     -4	bne	rY,rX,s
+ *     -3	sb	zr,-4(rX)
+ *     -2	nop
+ *     -1	nop
+ *      0	mtc0	rT,status
+ */
+void COMBINE(netbsd_r3k_cache_inv)(struct cpu *cpu,
+	struct mips_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
+	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
+
+	if (n_back < 8)
+		return;
+
+	if (ic[-8].f == instr(mtc0) && ic[-8].arg[1] == COP0_STATUS &&
+	    ic[-7].f == instr(nop) && ic[-6].f == instr(nop) &&
+	    ic[-5].f == instr(addiu) && ic[-5].arg[0] == ic[-5].arg[1] &&
+	    (int32_t)ic[-5].arg[2] == 4 && ic[-4].f == instr(bne_samepage) &&
+	    ic[-4].arg[0] == ic[-5].arg[0] && ic[-4].arg[0] != ic[-4].arg[1] &&
+	    ic[-4].arg[2] == (size_t) &ic[-5] &&
+	    ic[-3].arg[1] == ic[-5].arg[0] &&
+	    ic[-2].f == instr(nop) && ic[-1].f == instr(nop)) {
+		ic[-8].f = instr(netbsd_r3k_picache_do_inv);
+	}
+}
+
+
+/*
+ *  Combine: something ending with a nop.
+ *
+ *	NetBSD's strlen core.
+ *	[Conditional] branch, followed by nop.
+ *	NetBSD/pmax' idle loop (and possibly others as well).
+ *	Linux/pmax' idle loop.
+ */
+void COMBINE(nop)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
+	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
+
+	if (n_back < 8)
+		return;
+
+#ifdef MODE32
+	if (ic[-8].f == instr(set) &&
+	    ic[-7].f == mips32_loadstore[4 + 1] &&
+	    ic[-7].arg[0] == ic[-1].arg[0] &&
+	    ic[-7].arg[0] == ic[-3].arg[0] &&
+	    ic[-7].arg[0] == ic[-5].arg[0] &&
+	    ic[-7].arg[0] == ic[-7].arg[1] &&
+	    ic[-7].arg[0] == ic[-8].arg[0] &&
+	    ic[-6].f == instr(nop) &&
+	    ic[-5].arg[1] == (size_t) &cpu->cd.mips.gpr[MIPS_GPR_ZERO] &&
+	    ic[-5].f == instr(bne_samepage_nop) &&
+	    ic[-4].f == instr(nop) &&
+	    ic[-3].f == mips32_loadstore[4 + 1] &&
+	    ic[-2].f == instr(nop) &&
+	    ic[-1].arg[1] == (size_t) &cpu->cd.mips.gpr[MIPS_GPR_ZERO] &&
+	    ic[-1].arg[2] == (size_t) &ic[-8] &&
+	    ic[-1].f == instr(beq_samepage)) {
+		ic[-8].f = instr(linux_pmax_idle);
+		return;
+	}
+
+	if (ic[-4].f == instr(set) &&
+	    ic[-3].f == mips32_loadstore[4 + 1] &&
+	    ic[-3].arg[0] == ic[-1].arg[0] &&
+	    ic[-3].arg[1] == ic[-4].arg[0] &&
+	    ic[-2].f == instr(nop) &&
+	    ic[-1].arg[1] == (size_t) &cpu->cd.mips.gpr[MIPS_GPR_ZERO] &&
+	    ic[-1].arg[2] == (size_t) &ic[-4] &&
+	    ic[-1].f == instr(beq_samepage)) {
+		ic[-4].f = instr(netbsd_pmax_idle);
+		return;
+	}
+
+	if ((ic[-3].f == mips32_loadstore[1] || ic[-3].f == mips32_loadstore[1+16]) &&
+	    ic[-3].arg[2] == 0 &&
+	    ic[-3].arg[0] == ic[-1].arg[0] && ic[-3].arg[1] == ic[-2].arg[0] &&
+	    ic[-2].arg[0] == ic[-2].arg[1] && ic[-2].arg[2] == 1 &&
+	    ic[-2].f == instr(addiu) && ic[-1].arg[2] == (size_t) &ic[-3] &&
+	    ic[-1].arg[1] == (size_t) &cpu->cd.mips.gpr[MIPS_GPR_ZERO] &&
+	    ic[-1].f == instr(bne_samepage)) {
+		ic[-3].f = instr(strlen_lb_addiu_bne_nop);
+		return;
+	}
+#else
+	if ((ic[-3].f == mips_loadstore[1] || ic[-3].f == mips_loadstore[1+16]) &&
+	    ic[-3].arg[2] == 0 &&
+	    ic[-3].arg[0] == ic[-1].arg[0] && ic[-3].arg[1] == ic[-2].arg[0] &&
+	    ic[-2].arg[0] == ic[-2].arg[1] && ic[-2].arg[2] == 1 &&
+	    ic[-2].f == instr(addiu) && ic[-1].arg[2] == (size_t) &ic[-3] &&
+	    ic[-1].arg[1] == (size_t) &cpu->cd.mips.gpr[MIPS_GPR_ZERO] &&
+	    ic[-1].f == instr(bne_samepage)) {
+		ic[-3].f = instr(strlen_lb_addiu_bne_nop);
+		return;
+	}
+#endif
+
+	if (ic[-1].f == instr(bne_samepage)) {
+		ic[-1].f = instr(bne_samepage_nop);
+		return;
+	}
+
+	if (ic[-1].f == instr(beq_samepage)) {
+		ic[-1].f = instr(beq_samepage_nop);
+		return;
+	}
+
+	/*  TODO: other branches that are followed by nop should be here  */
+}
+
+
+/*
+ *  Combine:
+ *
+ *	xor + andi + sll
+ *	andi + sll
+ */
+void COMBINE(sll)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
+	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
+
+	if (n_back < 2)
+		return;
+
+	if (ic[-2].f == instr(xor) && ic[-1].f == instr(andi)) {
+		ic[-2].f = instr(xor_andi_sll);
+		return;
+	}
+
+	if (ic[-1].f == instr(andi)) {
+		ic[-1].f = instr(andi_sll);
+		return;
+	}
+}
+
+
+/*
+ *  lui + ori
+ */
+void COMBINE(ori)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
+	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
+
+	if (n_back < 1)
+		return;
+
+	if (ic[-1].f == instr(set)) {
+		ic[-1].f = instr(lui_ori);
+		return;
+	}
+}
+
+
+/*
+ *  addu + addu + addu
+ */
+void COMBINE(addu)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
+	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
+
+	if (n_back < 4)
+		return;
+
+	/*  Avoid "overlapping" instruction combinations:  */
+	if (ic[-4].f == instr(multi_addu_3) ||
+	    ic[-3].f == instr(multi_addu_3))
+		return;
+
+	if (ic[-2].f == instr(addu) && ic[-1].f == instr(addu)) {
+		ic[-2].f = instr(multi_addu_3);
+		return;
+	}
+}
+
+
+/*
+ *  Combine:
+ *
+ *	[Conditional] branch, followed by addiu.
+ */
+void COMBINE(addiu)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
+	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
+
+	if (n_back < 2)
+		return;
+
+	if (ic[-2].f == instr(addiu) &&
+	    ic[-1].f == instr(bne_samepage)) {
+		ic[-2].f = instr(addiu_bne_samepage_addiu);
+		return;
+	}
+
+	if (ic[-1].f == instr(set)) {
+		ic[-1].f = instr(lui_addiu);
+		return;
+	}
+
+	if (ic[-1].f == instr(b_samepage)) {
+		ic[-1].f = instr(b_samepage_addiu);
+		return;
+	}
+
+	if (ic[-1].f == instr(beq_samepage)) {
+		ic[-1].f = instr(beq_samepage_addiu);
+		return;
+	}
+
+	if (ic[-1].f == instr(bne_samepage)) {
+		ic[-1].f = instr(bne_samepage_addiu);
+		return;
+	}
+
+	if (ic[-1].f == instr(jr_ra)) {
+		ic[-1].f = instr(jr_ra_addiu);
+		return;
+	}
+
+	/*  TODO: other branches that are followed by addiu should be here  */
+}
+
+
+/*
+ *  Combine: [Conditional] branch, followed by daddiu.
+ */
+void COMBINE(b_daddiu)(struct cpu *cpu, struct mips_instr_call *ic,
+	int low_addr)
+{
+	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
+	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
+
+	if (n_back < 1)
+		return;
+
+	if (ic[-1].f == instr(b_samepage)) {
+		ic[-1].f = instr(b_samepage_daddiu);
+	}
+
+	/*  TODO: other branches that are followed by daddiu should be here  */
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  mips_instr_to_be_translated():
+ *
+ *  Translate an instruction word into a mips_instr_call. ic is filled in with
+ *  valid data for the translated instruction, or a "nothing" instruction if
+ *  there was a translation failure. The newly translated instruction is then
+ *  executed.
+ */
+X(to_be_translated)
+{
+	uint64_t addr, low_pc;
+	uint32_t iword, imm;
+	unsigned char *page;
+	unsigned char ib[4];
+	int main_opcode, rt, rs, rd, sa, s6, x64 = 0, s10;
+	int in_crosspage_delayslot = 0;
+	void (*samepage_function)(struct cpu *, struct mips_instr_call *);
+	int store, signedness, size;
+
+	/*  Figure out the (virtual) address of the instruction:  */
+	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+
+	/*  Special case for branch with delayslot on the next page:  */
+	if (cpu->delay_slot == TO_BE_DELAYED && low_pc == 0) {
+		/*  fatal("[ delay-slot translation across page "
+		    "boundary ]\n");  */
+		in_crosspage_delayslot = 1;
+	}
+
+	addr = cpu->pc & ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	addr += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc = (MODE_int_t)addr;
+	addr &= ~((1 << MIPS_INSTR_ALIGNMENT_SHIFT) - 1);
+
+	/*  Read the instruction word from memory:  */
+#ifdef MODE32
+	page = cpu->cd.mips.host_load[(uint32_t)addr >> 12];
+#else
+	{
+		const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+		const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+		const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+		uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
+		uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+		uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
+		    DYNTRANS_L3N)) & mask3;
+		struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.mips.l1_64[x1];
+		struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
+		page = l3->host_load[x3];
+	}
+#endif
+
+	if (page != NULL) {
+		/*  fatal("TRANSLATION HIT!\n");  */
+		memcpy(ib, page + (addr & 0xffc), sizeof(ib));
+	} else {
+		/*  fatal("TRANSLATION MISS!\n");  */
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
+		    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
+			fatal("to_be_translated(): read failed: TODO\n");
+			goto bad;
+		}
+	}
+
+	{
+		uint32_t *p = (uint32_t *) ib;
+		iword = *p;
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iword = LE32_TO_HOST(iword);
+	else
+		iword = BE32_TO_HOST(iword);
+
+
+#define DYNTRANS_TO_BE_TRANSLATED_HEAD
+#include "cpu_dyntrans.c"
+#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD
+
+
+	/*
+	 *  Translate the instruction:
+ 	 *
+	 *  NOTE: _NEVER_ allow writes to the zero register; all instructions
+	 *  that use the zero register as their destination should be treated
+	 *  as NOPs, except those that access memory (they should use the
+	 *  scratch register instead).
+	 */
+
+	main_opcode = iword >> 26;
+	rs = (iword >> 21) & 31;
+	rt = (iword >> 16) & 31;
+	rd = (iword >> 11) & 31;
+	sa = (iword >>  6) & 31;
+	imm = (int16_t)iword;
+	s6 = iword & 63;
+	s10 = (rs << 5) | sa;
+
+	switch (main_opcode) {
+
+	case HI6_SPECIAL:
+		switch (s6) {
+
+		case SPECIAL_SLL:
+		case SPECIAL_SLLV:
+		case SPECIAL_SRL:
+		case SPECIAL_SRLV:
+		case SPECIAL_SRA:
+		case SPECIAL_SRAV:
+		case SPECIAL_DSRL:
+		case SPECIAL_DSRLV:
+		case SPECIAL_DSRL32:
+		case SPECIAL_DSLL:
+		case SPECIAL_DSLLV:
+		case SPECIAL_DSLL32:
+		case SPECIAL_DSRA:
+		case SPECIAL_DSRAV:
+		case SPECIAL_DSRA32:
+			switch (s6) {
+			case SPECIAL_SLL:  ic->f = instr(sll); break;
+			case SPECIAL_SLLV: ic->f = instr(sllv); sa = -1; break;
+			case SPECIAL_SRL:  ic->f = instr(srl); break;
+			case SPECIAL_SRLV: ic->f = instr(srlv); sa = -1; break;
+			case SPECIAL_SRA:  ic->f = instr(sra); break;
+			case SPECIAL_SRAV: ic->f = instr(srav); sa = -1; break;
+			case SPECIAL_DSRL: ic->f = instr(dsrl); x64=1; break;
+			case SPECIAL_DSRLV:ic->f = instr(dsrlv);
+					   x64 = 1; sa = -1; break;
+			case SPECIAL_DSRL32:ic->f= instr(dsrl); x64=1;
+					   sa += 32; break;
+			case SPECIAL_DSLL: ic->f = instr(dsll); x64=1; break;
+			case SPECIAL_DSLLV:ic->f = instr(dsllv);
+					   x64 = 1; sa = -1; break;
+			case SPECIAL_DSLL32:ic->f= instr(dsll); x64=1;
+					   sa += 32; break;
+			case SPECIAL_DSRA: ic->f = instr(dsra); x64=1; break;
+			case SPECIAL_DSRAV:ic->f = instr(dsrav);
+					   x64 = 1; sa = -1; break;
+			case SPECIAL_DSRA32:ic->f = instr(dsra); x64=1;
+					   sa += 32; break;
+			}
+
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+			if (sa >= 0)
+				ic->arg[1] = sa;
+			else
+				ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
+			ic->arg[2] = (size_t)&cpu->cd.mips.gpr[rd];
+
+			/*  Special checks for MIPS32/64 revision 2 opcodes,
+			    such as rotation instructions:  */
+			if (sa >= 0 && rs != 0x00) {
+				if (cpu->cd.mips.cpu_type.isa_level < 32 ||
+				    cpu->cd.mips.cpu_type.isa_revision < 2) {
+					static int warning_rotate = 0;
+					if (!warning_rotate &&
+					    !cpu->translation_readahead) {
+						fatal("[ WARNING! MIPS32/64 "
+						    "revision 2 rotate opcode"
+						    " used, but the %s process"
+						    "or does not implement "
+						    "such instructions. Only "
+						    "printing this "
+						    "warning once. ]\n",
+						    cpu->cd.mips.cpu_type.name);
+						warning_rotate = 1;
+					}
+					ic->f = instr(reserved);
+					break;
+				}
+				switch (rs) {
+				case 0x01:
+					switch (s6) {
+					case SPECIAL_SRL:	/*  ror (aka. rotr?) */
+						ic->f = instr(ror);
+						break;
+					default:goto bad;
+					}
+					break;
+				default:goto bad;
+				}
+			}
+			if (sa < 0 && (s10 & 0x1f) != 0) {
+				int orig_sa = (iword >>  6) & 31;
+				switch (s6) {
+				case SPECIAL_SRLV:	/*  rorv (aka. rotrv?) */
+					if (orig_sa == 0x01) {
+						ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
+						ic->f = instr(rorv);
+					}
+					break;
+				default:goto bad;
+				}
+				break;
+			}
+
+			if (rd == MIPS_GPR_ZERO)
+				ic->f = instr(nop);
+			if (ic->f == instr(sll))
+				cpu->cd.mips.combination_check = COMBINE(sll);
+			if (ic->f == instr(nop))
+				cpu->cd.mips.combination_check = COMBINE(nop);
+			break;
+
+		case SPECIAL_ADD:
+		case SPECIAL_ADDU:
+		case SPECIAL_SUB:
+		case SPECIAL_SUBU:
+		case SPECIAL_DADD:
+		case SPECIAL_DADDU:
+		case SPECIAL_DSUB:
+		case SPECIAL_DSUBU:
+		case SPECIAL_SLT:
+		case SPECIAL_SLTU:
+		case SPECIAL_AND:
+		case SPECIAL_OR:
+		case SPECIAL_XOR:
+		case SPECIAL_NOR:
+		case SPECIAL_MOVN:
+		case SPECIAL_MOVZ:
+		case SPECIAL_MFHI:
+		case SPECIAL_MFLO:
+		case SPECIAL_MTHI:
+		case SPECIAL_MTLO:
+		case SPECIAL_DIV:
+		case SPECIAL_DIVU:
+		case SPECIAL_DDIV:
+		case SPECIAL_DDIVU:
+		case SPECIAL_MULT:
+		case SPECIAL_MULTU:
+		case SPECIAL_DMULT:
+		case SPECIAL_DMULTU:
+		case SPECIAL_TGE:
+		case SPECIAL_TGEU:
+		case SPECIAL_TLT:
+		case SPECIAL_TLTU:
+		case SPECIAL_TEQ:
+		case SPECIAL_TNE:
+			switch (s6) {
+			case SPECIAL_ADD:   ic->f = instr(add); break;
+			case SPECIAL_ADDU:  ic->f = instr(addu); break;
+			case SPECIAL_SUB:   ic->f = instr(sub); break;
+			case SPECIAL_SUBU:  ic->f = instr(subu); break;
+			case SPECIAL_DADD:  ic->f = instr(dadd); x64=1; break;
+			case SPECIAL_DADDU: ic->f = instr(daddu); x64=1; break;
+			case SPECIAL_DSUB:  ic->f = instr(dsub); x64=1; break;
+			case SPECIAL_DSUBU: ic->f = instr(dsubu); x64=1; break;
+			case SPECIAL_SLT:   ic->f = instr(slt); break;
+			case SPECIAL_SLTU:  ic->f = instr(sltu); break;
+			case SPECIAL_AND:   ic->f = instr(and); break;
+			case SPECIAL_OR:    ic->f = instr(or); break;
+			case SPECIAL_XOR:   ic->f = instr(xor); break;
+			case SPECIAL_NOR:   ic->f = instr(nor); break;
+			case SPECIAL_MFHI:  ic->f = instr(mov); break;
+			case SPECIAL_MFLO:  ic->f = instr(mov); break;
+			case SPECIAL_MTHI:  ic->f = instr(mov); break;
+			case SPECIAL_MTLO:  ic->f = instr(mov); break;
+			case SPECIAL_DIV:   ic->f = instr(div); break;
+			case SPECIAL_DIVU:  ic->f = instr(divu); break;
+			case SPECIAL_DDIV:  ic->f = instr(ddiv); x64=1; break;
+			case SPECIAL_DDIVU: ic->f = instr(ddivu); x64=1; break;
+			case SPECIAL_MULT : ic->f = instr(mult); break;
+			case SPECIAL_MULTU: ic->f = instr(multu); break;
+			case SPECIAL_DMULT: ic->f = instr(dmult); x64=1; break;
+			case SPECIAL_DMULTU:ic->f = instr(dmultu); x64=1; break;
+			case SPECIAL_TGE:   ic->f = instr(tge); break;
+			case SPECIAL_TGEU:  ic->f = instr(tgeu); break;
+			case SPECIAL_TLT:   ic->f = instr(tlt); break;
+			case SPECIAL_TLTU:  ic->f = instr(tltu); break;
+			case SPECIAL_TEQ:   ic->f = instr(teq); break;
+			case SPECIAL_TNE:   ic->f = instr(tne); break;
+			case SPECIAL_MOVN:  ic->f = instr(movn); break;
+			case SPECIAL_MOVZ:  ic->f = instr(movz); break;
+			}
+
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
+			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
+			ic->arg[2] = (size_t)&cpu->cd.mips.gpr[rd];
+
+			switch (s6) {
+			case SPECIAL_MFHI:
+				ic->arg[0] = (size_t)&cpu->cd.mips.hi;
+				break;
+			case SPECIAL_MFLO:
+				ic->arg[0] = (size_t)&cpu->cd.mips.lo;
+				break;
+			case SPECIAL_MTHI:
+				ic->arg[2] = (size_t)&cpu->cd.mips.hi;
+				break;
+			case SPECIAL_MTLO:
+				ic->arg[2] = (size_t)&cpu->cd.mips.lo;
+				break;
+			}
+			/*  Special cases for rd:  */
+			switch (s6) {
+			case SPECIAL_MTHI:
+			case SPECIAL_MTLO:
+			case SPECIAL_DIV:
+			case SPECIAL_DIVU:
+			case SPECIAL_DDIV:
+			case SPECIAL_DDIVU:
+			case SPECIAL_MULT:
+			case SPECIAL_MULTU:
+			case SPECIAL_DMULT:
+			case SPECIAL_DMULTU:
+				if (s6 == SPECIAL_MULT && rd != MIPS_GPR_ZERO) {
+					if (cpu->cd.mips.cpu_type.rev ==
+					    MIPS_R5900) {
+						ic->f = instr(mult_r5900);
+						break;
+					}
+					break;
+				}
+				if (s6 == SPECIAL_MULTU && rd!=MIPS_GPR_ZERO) {
+					if (cpu->cd.mips.cpu_type.rev ==
+					    MIPS_R5900) {
+						ic->f = instr(multu_r5900);
+						break;
+					}
+				}
+				if (rd != MIPS_GPR_ZERO) {
+					if (!cpu->translation_readahead)
+						fatal("TODO: rd NON-zero\n");
+					goto bad;
+				}
+				/*  These instructions don't use rd.  */
+				break;
+			case SPECIAL_TGE:
+			case SPECIAL_TGEU:
+			case SPECIAL_TLT:
+			case SPECIAL_TLTU:
+			case SPECIAL_TEQ:
+			case SPECIAL_TNE:
+				/*  In these instructions, rd is a 'code',
+				    only read by trap handling software.  */
+				break;
+			default:if (rd == MIPS_GPR_ZERO)
+					ic->f = instr(nop);
+			}
+
+			if (ic->f == instr(addu))
+				cpu->cd.mips.combination_check = COMBINE(addu);
+
+			break;
+
+		case SPECIAL_JR:
+		case SPECIAL_JALR:
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
+			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rd];
+			if (s6 == SPECIAL_JALR && rd == MIPS_GPR_ZERO)
+				s6 = SPECIAL_JR;
+			ic->arg[2] = (addr & 0xffc) + 8;
+			switch (s6) {
+			case SPECIAL_JR:
+				if (rs == MIPS_GPR_RA) {
+					if (cpu->machine->show_trace_tree)
+						ic->f = instr(jr_ra_trace);
+					else
+						ic->f = instr(jr_ra);
+				} else {
+					ic->f = instr(jr);
+				}
+				if (cpu->translation_readahead > 2)
+					cpu->translation_readahead = 2;
+				break;
+			case SPECIAL_JALR:
+				if (cpu->machine->show_trace_tree)
+					ic->f = instr(jalr_trace);
+				else
+					ic->f = instr(jalr);
+				break;
+			}
+			if (cpu->delay_slot) {
+				if (!cpu->translation_readahead)
+					fatal("TODO: branch in delay "
+					    "slot? (1)\n");
+				goto bad;
+			}
+			break;
+
+		case SPECIAL_SYSCALL:
+			if (((iword >> 6) & 0xfffff) == 0x30378) {
+				/*  "Magic trap" for PROM emulation:  */
+				ic->f = instr(promemul);
+			} else {
+				ic->f = instr(syscall);
+			}
+			break;
+
+		case SPECIAL_BREAK:
+			if (((iword >> 6) & 0xfffff) == 0x30378) {
+				/*  "Magic trap" for REBOOT:  */
+				ic->f = instr(reboot);
+			} else {
+				ic->f = instr(break);
+			}
+			break;
+
+		case SPECIAL_SYNC:
+			ic->f = instr(nop);
+			break;
+
+		default:goto bad;
+		}
+		break;
+
+	case HI6_BEQ:
+	case HI6_BNE:
+	case HI6_BEQL:
+	case HI6_BNEL:
+	case HI6_BLEZ:
+	case HI6_BLEZL:
+	case HI6_BGTZ:
+	case HI6_BGTZL:
+		samepage_function = NULL;  /*  get rid of a compiler warning  */
+		switch (main_opcode) {
+		case HI6_BEQ:
+			ic->f = instr(beq);
+			samepage_function = instr(beq_samepage);
+			/*  Special case: comparing a register with itself:  */
+			if (rs == rt) {
+				ic->f = instr(b);
+				samepage_function = instr(b_samepage);
+			}
+			break;
+		case HI6_BNE:
+			ic->f = instr(bne);
+			samepage_function = instr(bne_samepage);
+			break;
+		case HI6_BEQL:
+			ic->f = instr(beql);
+			samepage_function = instr(beql_samepage);
+			/*  Special case: comparing a register with itself:  */
+			if (rs == rt) {
+				ic->f = instr(b);
+				samepage_function = instr(b_samepage);
+			}
+			break;
+		case HI6_BNEL:
+			ic->f = instr(bnel);
+			samepage_function = instr(bnel_samepage);
+			break;
+		case HI6_BLEZ:
+			ic->f = instr(blez);
+			samepage_function = instr(blez_samepage);
+			break;
+		case HI6_BLEZL:
+			ic->f = instr(blezl);
+			samepage_function = instr(blezl_samepage);
+			break;
+		case HI6_BGTZ:
+			ic->f = instr(bgtz);
+			samepage_function = instr(bgtz_samepage);
+			break;
+		case HI6_BGTZL:
+			ic->f = instr(bgtzl);
+			samepage_function = instr(bgtzl_samepage);
+			break;
+		}
+		ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
+		ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
+		ic->arg[2] = (int32_t) ( (imm << MIPS_INSTR_ALIGNMENT_SHIFT)
+		    + (addr & 0xffc) + 4 );
+		/*  Is the offset from the start of the current page still
+		    within the same page? Then use the samepage_function:  */
+		if ((uint32_t)ic->arg[2] < ((MIPS_IC_ENTRIES_PER_PAGE - 1)
+		    << MIPS_INSTR_ALIGNMENT_SHIFT) && (addr & 0xffc) < 0xffc) {
+			ic->arg[2] = (size_t) (cpu->cd.mips.cur_ic_page +
+			    ((ic->arg[2] >> MIPS_INSTR_ALIGNMENT_SHIFT)
+			    & (MIPS_IC_ENTRIES_PER_PAGE - 1)));
+			ic->f = samepage_function;
+		}
+		if (cpu->delay_slot) {
+			if (!cpu->translation_readahead)
+				fatal("TODO: branch in delay slot? (2)\n");
+			goto bad;
+		}
+		break;
+
+	case HI6_ADDI:
+	case HI6_ADDIU:
+	case HI6_SLTI:
+	case HI6_SLTIU:
+	case HI6_DADDI:
+	case HI6_DADDIU:
+	case HI6_ANDI:
+	case HI6_ORI:
+	case HI6_XORI:
+		ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
+		ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
+		if (main_opcode == HI6_ADDI ||
+		    main_opcode == HI6_ADDIU ||
+		    main_opcode == HI6_SLTI ||
+		    main_opcode == HI6_SLTIU ||
+		    main_opcode == HI6_DADDI ||
+		    main_opcode == HI6_DADDIU)
+			ic->arg[2] = (int16_t)iword;
+		else
+			ic->arg[2] = (uint16_t)iword;
+
+		switch (main_opcode) {
+		case HI6_ADDI:    ic->f = instr(addi); break;
+		case HI6_ADDIU:   ic->f = instr(addiu); break;
+		case HI6_SLTI:    ic->f = instr(slti); break;
+		case HI6_SLTIU:   ic->f = instr(sltiu); break;
+		case HI6_DADDI:   ic->f = instr(daddi); x64 = 1; break;
+		case HI6_DADDIU:  ic->f = instr(daddiu); x64 = 1; break;
+		case HI6_ANDI:    ic->f = instr(andi); break;
+		case HI6_ORI:     ic->f = instr(ori); break;
+		case HI6_XORI:    ic->f = instr(xori); break;
+		}
+
+		if (ic->arg[2] == 0) {
+			if ((cpu->is_32bit && ic->f == instr(addiu)) ||
+			    (!cpu->is_32bit && ic->f == instr(daddiu))) {
+				ic->f = instr(mov);
+				ic->arg[2] = ic->arg[1];
+			}
+		}
+
+		if (rt == MIPS_GPR_ZERO)
+			ic->f = instr(nop);
+
+		if (ic->f == instr(ori))
+			cpu->cd.mips.combination_check = COMBINE(ori);
+		if (ic->f == instr(addiu))
+			cpu->cd.mips.combination_check = COMBINE(addiu);
+		if (ic->f == instr(daddiu))
+			cpu->cd.mips.combination_check = COMBINE(b_daddiu);
+		break;
+
+	case HI6_LUI:
+		ic->f = instr(set);
+		ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+		ic->arg[1] = (int32_t) (imm << 16);
+		/*  NOTE: Don't use arg[2] here. It can be used with
+		    instruction combinations, to do lui + addiu, etc.  */
+		if (rt == MIPS_GPR_ZERO)
+			ic->f = instr(nop);
+		break;
+
+	case HI6_J:
+	case HI6_JAL:
+		switch (main_opcode) {
+		case HI6_J:
+			ic->f = instr(j);
+			if (cpu->translation_readahead > 2)
+				cpu->translation_readahead = 2;
+			break;
+		case HI6_JAL:
+			if (cpu->machine->show_trace_tree)
+				ic->f = instr(jal_trace);
+			else
+				ic->f = instr(jal);
+			break;
+		}
+		ic->arg[0] = (iword & 0x03ffffff) << 2;
+		ic->arg[1] = (addr & 0xffc) + 8;
+		if (cpu->delay_slot) {
+			if (!cpu->translation_readahead)
+				fatal("TODO: branch in delay slot (=%i)? (3);"
+				    " addr=%016" PRIx64" iword=%08" PRIx32"\n",
+				    cpu->delay_slot, (uint64_t)addr, iword);
+			goto bad;
+		}
+		break;
+
+	case HI6_COP0:
+		/*  TODO: Is checking bit 25 enough, or perhaps all bits
+		    25..21 must be checked?  */
+		if ((iword >> 25) & 1) {
+			ic->arg[2] = addr & 0xffc;
+			switch (iword & 0xff) {
+			case COP0_TLBR:
+				ic->f = instr(tlbr);
+				break;
+			case COP0_TLBWI:
+			case COP0_TLBWR:
+				ic->f = instr(tlbw);
+				ic->arg[0] = (iword & 0xff) == COP0_TLBWR;
+				break;
+			case COP0_TLBP:
+				ic->f = instr(tlbp);
+				break;
+			case COP0_RFE:
+				ic->f = instr(rfe);
+				break;
+			case COP0_ERET:
+				ic->f = instr(eret);
+				break;
+			case COP0_DERET:
+				ic->f = instr(deret);
+				break;
+			case COP0_WAIT:
+				ic->f = instr(wait);
+				if (cpu->cd.mips.cpu_type.rev != MIPS_RM5200 &&
+				    cpu->cd.mips.cpu_type.isa_level < 32) {
+					static int warned = 0;
+					ic->f = instr(reserved);
+					if (!warned &&
+					    !cpu->translation_readahead) {
+						fatal("{ WARNING: Attempt to "
+						    "execute the WAIT instruct"
+					            "ion, but the emulated CPU "
+						    "is neither RM52xx, nor "
+						    "MIPS32/64! }\n");
+						warned = 1;
+					}
+				}
+				break;
+			case COP0_STANDBY:
+				/*  NOTE: Reusing the 'wait' instruction:  */
+				ic->f = instr(wait);
+				if (cpu->cd.mips.cpu_type.rev != MIPS_R4100) {
+					static int warned = 0;
+					ic->f = instr(reserved);
+					if (!warned &&
+					    !cpu->translation_readahead) {
+						fatal("{ WARNING: Attempt to "
+						    "execute a R41xx instruct"
+					            "ion, but the emulated CPU "
+						    "doesn't support it! }\n");
+						warned = 1;
+					}
+				}
+				break;
+			case COP0_HIBERNATE:
+				/*  TODO  */
+				goto bad;
+			case COP0_SUSPEND:
+				/*  Used by NetBSD on HPCmips (VR41xx) to
+				    halt the machine.  */
+				ic->f = instr(reboot);
+				break;
+			case COP0_EI:
+				if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
+					ic->f = instr(ei_r5900);
+				} else
+					goto bad;
+				break;
+			case COP0_DI:
+				if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
+					ic->f = instr(di_r5900);
+				} else
+					goto bad;
+				break;
+			default:if (!cpu->translation_readahead)
+					fatal("UNIMPLEMENTED cop0 (func "
+					    "0x%02x)\n", iword & 0xff);
+				goto bad;
+			}
+			break;
+		}
+
+		/*  rs contains the coprocessor opcode!  */
+		switch (rs) {
+		case COPz_CFCz:
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+			ic->arg[1] = rd + ((iword & 7) << 5);
+			ic->arg[2] = addr & 0xffc;
+			ic->f = instr(cfc0);
+			if (rt == MIPS_GPR_ZERO)
+				ic->f = instr(nop);
+			break;
+		case COPz_MFCz:
+		case COPz_DMFCz:
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+			ic->arg[1] = rd + ((iword & 7) << 5);
+			ic->arg[2] = addr & 0xffc;
+			ic->f = rs == COPz_MFCz? instr(mfc0) : instr(dmfc0);
+			if (rs == COPz_MFCz && (iword & 7) == 0 &&
+			    rd != COP0_COUNT)
+				ic->f = instr(mfc0_select0);
+			if (rs == COPz_DMFCz && (iword & 7) == 0 &&
+			    rd != COP0_COUNT)
+				ic->f = instr(dmfc0_select0);
+			if (rt == MIPS_GPR_ZERO)
+				ic->f = instr(nop);
+			break;
+		case COPz_MTCz:
+		case COPz_DMTCz:
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+			ic->arg[1] = rd + ((iword & 7) << 5);
+			ic->arg[2] = addr & 0xffc;
+			ic->f = rs == COPz_MTCz? instr(mtc0) : instr(dmtc0);
+
+			if (cpu->cd.mips.cpu_type.exc_model == EXC3K &&
+			    rs == COPz_MTCz && rd == COP0_STATUS)
+				cpu->cd.mips.combination_check =
+				    COMBINE(netbsd_r3k_cache_inv);
+
+			break;
+		case COPz_MFMCz:
+			if ((iword & 0xffdf) == 0x6000) {
+				/*  MIPS32/64 rev 2 "ei" or "di":   */
+				if (cpu->cd.mips.cpu_type.isa_level < 32 ||
+				    cpu->cd.mips.cpu_type.isa_revision < 2) {
+					static int warning_ei_di = 0;
+					if (!warning_ei_di &&
+					    !cpu->translation_readahead) {
+						fatal("[ WARNING! MIPS32/64 "
+						    "revision 2 di or ei opcode"
+						    " used, but the %s process"
+						    "or does not implement "
+						    "such instructions. Only "
+						    "printing this "
+						    "warning once. ]\n",
+						    cpu->cd.mips.cpu_type.name);
+						warning_ei_di = 1;
+					}
+					ic->f = instr(reserved);
+					break;
+				}
+				ic->f = instr(ei_or_di);
+				ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+				if (rt == MIPS_GPR_ZERO)
+					ic->arg[0] =
+					    (size_t)&cpu->cd.mips.scratch;
+				ic->arg[1] = iword & 0x20;
+			} else {
+				if (!cpu->translation_readahead)
+					fatal("Unimplemented COP0_MFMCz\n");
+				goto bad;
+			}
+			break;
+		case COPz_BCzc:
+			if (iword == 0x4100ffff) {
+				/*  R2020 DECstation write-loop thingy.  */
+				ic->f = instr(nop);
+			} else {
+				if (!cpu->translation_readahead)
+					fatal("Unimplemented COP0_BCzc\n");
+				goto bad;
+			}
+			break;
+		
+		default:if (!cpu->translation_readahead)
+				fatal("UNIMPLEMENTED cop0 (rs = %i)\n", rs);
+			goto bad;
+		}
+		break;
+
+	case HI6_COP1:
+		/*  Always cause a coprocessor unusable exception if
+		    there is no floating point coprocessor:  */
+		if (cpu->cd.mips.cpu_type.flags & NOFPU ||
+		    cpu->cd.mips.coproc[1] == NULL) {
+			ic->f = instr(cpu);
+			ic->arg[0] = 1;
+			break;
+		}
+
+		/*  Bits 25..21 are floating point main opcode:  */
+		switch (rs) {
+
+		case COPz_BCzc:
+			/*  Conditional branch:  */
+			/*  TODO: Reimplement this in a faster way.  */
+			ic->f = instr(cop1_bc);
+			ic->arg[0] = (iword >> 18) & 7;	/*  cc  */
+			ic->arg[1] = (iword >> 16) & 3;	/*  nd, tf bits  */
+			ic->arg[2] = (int32_t) ((imm <<
+			    MIPS_INSTR_ALIGNMENT_SHIFT) + (addr & 0xffc) + 4);
+			if (cpu->delay_slot) {
+				if (!cpu->translation_readahead)
+					fatal("TODO: branch in delay slot 4\n");
+				goto bad;
+			}
+			if (cpu->cd.mips.cpu_type.isa_level <= 3 &&
+			    ic->arg[0] != 0) {
+				if (!cpu->translation_readahead)
+					fatal("Attempt to execute a non-cc-0 "
+					    "BC* instruction on an isa level "
+					    "%i cpu. TODO: How should this be "
+					    "handled?\n",
+					    cpu->cd.mips.cpu_type.isa_level);
+				goto bad;
+			}
+
+			break;
+
+		case COPz_DMFCz:
+		case COPz_DMTCz:
+			x64 = 1;
+			/*  FALL-THROUGH  */
+		case COP1_FMT_S:
+		case COP1_FMT_D:
+		case COP1_FMT_W:
+		case COP1_FMT_L:
+		case COP1_FMT_PS:
+		case COPz_CFCz:
+		case COPz_CTCz:
+		case COPz_MFCz:
+		case COPz_MTCz:
+			/*  Fallback to slow pre-dyntrans code, for now.  */
+			/*  TODO: Fix/optimize/rewrite.  */
+			ic->f = instr(cop1_slow);
+			ic->arg[0] = (uint32_t)iword & ((1 << 26) - 1);
+			break;
+
+		default:if (!cpu->translation_readahead)
+			    fatal("COP1 floating point opcode = 0x%02x\n", rs);
+			goto bad;
+		}
+		break;
+
+	case HI6_COP2:
+		/*  Always cause a coprocessor unusable exception if
+		    there is no coprocessor 2:  */
+		if (cpu->cd.mips.coproc[2] == NULL) {
+			ic->f = instr(cpu);
+			ic->arg[0] = 2;
+			break;
+		}
+		if (!cpu->translation_readahead)
+			fatal("COP2 functionality not yet implemented\n");
+		goto bad;
+		break;
+
+	case HI6_COP3:
+		/*  Always cause a coprocessor unusable exception if
+		    there is no coprocessor 3:  */
+		if (cpu->cd.mips.coproc[3] == NULL) {
+			ic->f = instr(cpu);
+			ic->arg[0] = 3;
+			break;
+		}
+
+		if (iword == 0x4d00ffff) {
+			/*  R2020 writeback thing, used by e.g. NetBSD/pmax
+			    on MIPSMATE.  */
+			ic->f = instr(nop);
+		} else {
+			if (!cpu->translation_readahead)
+				fatal("COP3 iword=0x%08x\n", iword);
+			goto bad;
+		}
+		break;
+
+	case HI6_SPECIAL2:
+		if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
+			/*  R5900, TX79/C790, have MMI instead of SPECIAL2:  */
+			int mmi_subopcode = (iword >> 6) & 0x1f;
+
+			switch (s6) {
+
+			case MMI_MADD:
+				ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
+				ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
+				ic->arg[2] = (size_t)&cpu->cd.mips.gpr[rd];
+				if (rd == MIPS_GPR_ZERO)
+					ic->f = instr(madd);
+				else
+					ic->f = instr(madd_rd);
+				break;
+
+			case MMI_MADDU:
+				ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
+				ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
+				ic->arg[2] = (size_t)&cpu->cd.mips.gpr[rd];
+				if (rd == MIPS_GPR_ZERO)
+					ic->f = instr(maddu);
+				else
+					ic->f = instr(maddu_rd);
+				break;
+
+			case MMI_MMI0:
+				switch (mmi_subopcode) {
+
+				case MMI0_PEXTLW:
+					ic->arg[0] = rs;
+					ic->arg[1] = rt;
+					ic->arg[2] = rd;
+					if (rd == MIPS_GPR_ZERO)
+						ic->f = instr(nop);
+					else
+						ic->f = instr(pextlw);
+					break;
+
+				default:goto bad;
+				}
+				break;
+
+			case MMI_MMI3:
+				switch (mmi_subopcode) {
+
+				case MMI3_POR:
+					ic->arg[0] = rs;
+					ic->arg[1] = rt;
+					ic->arg[2] = rd;
+					if (rd == MIPS_GPR_ZERO)
+						ic->f = instr(nop);
+					else
+						ic->f = instr(por);
+					break;
+
+				default:goto bad;
+				}
+				break;
+
+			default:goto bad;
+			}
+			break;
+		}
+
+		/*  TODO: is this correct? Or are there other non-MIPS32/64
+		    MIPS processors that have support for SPECIAL2 opcodes?  */
+		if (cpu->cd.mips.cpu_type.isa_level < 32) {
+			ic->f = instr(reserved);
+			break;
+		}
+
+		/*  SPECIAL2:  */
+		switch (s6) {
+
+		case SPECIAL2_MADD:
+		case SPECIAL2_MADDU:
+		case SPECIAL2_MSUB:
+		case SPECIAL2_MSUBU:
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
+			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
+			switch (s6) {
+			case SPECIAL2_MADD: ic->f = instr(madd); break;
+			case SPECIAL2_MADDU:ic->f = instr(maddu); break;
+			case SPECIAL2_MSUB: ic->f = instr(msub); break;
+			case SPECIAL2_MSUBU:ic->f = instr(msubu); break;
+			}
+			break;
+
+		case SPECIAL2_MUL:
+			ic->f = instr(mul);
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
+			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
+			ic->arg[2] = (size_t)&cpu->cd.mips.gpr[rd];
+			if (rd == MIPS_GPR_ZERO)
+				ic->f = instr(nop);
+			break;
+
+		case SPECIAL2_CLZ:
+		case SPECIAL2_CLO:
+		case SPECIAL2_DCLZ:
+		case SPECIAL2_DCLO:
+			switch (s6) {
+			case SPECIAL2_CLZ:  ic->f = instr(clz); break;
+			case SPECIAL2_CLO:  ic->f = instr(clo); break;
+			case SPECIAL2_DCLZ: ic->f = instr(dclz); break;
+			case SPECIAL2_DCLO: ic->f = instr(dclo); break;
+			}
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
+			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rd];
+			if (rd == MIPS_GPR_ZERO)
+				ic->f = instr(nop);
+			break;
+
+		default:goto bad;
+		}
+		break;
+
+	case HI6_REGIMM:
+		switch (rt) {
+		case REGIMM_BGEZ:
+		case REGIMM_BGEZL:
+		case REGIMM_BLTZ:
+		case REGIMM_BLTZL:
+		case REGIMM_BGEZAL:
+		case REGIMM_BGEZALL:
+		case REGIMM_BLTZAL:
+		case REGIMM_BLTZALL:
+			samepage_function = NULL;
+			switch (rt) {
+			case REGIMM_BGEZ:
+				ic->f = instr(bgez);
+				samepage_function = instr(bgez_samepage);
+				break;
+			case REGIMM_BGEZL:
+				ic->f = instr(bgezl);
+				samepage_function = instr(bgezl_samepage);
+				break;
+			case REGIMM_BLTZ:
+				ic->f = instr(bltz);
+				samepage_function = instr(bltz_samepage);
+				break;
+			case REGIMM_BLTZL:
+				ic->f = instr(bltzl);
+				samepage_function = instr(bltzl_samepage);
+				break;
+			case REGIMM_BGEZAL:
+				ic->f = instr(bgezal);
+				samepage_function = instr(bgezal_samepage);
+				break;
+			case REGIMM_BGEZALL:
+				ic->f = instr(bgezall);
+				samepage_function = instr(bgezall_samepage);
+				break;
+			case REGIMM_BLTZAL:
+				ic->f = instr(bltzal);
+				samepage_function = instr(bltzal_samepage);
+				break;
+			case REGIMM_BLTZALL:
+				ic->f = instr(bltzall);
+				samepage_function = instr(bltzall_samepage);
+				break;
+			}
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
+			ic->arg[2] = (imm << MIPS_INSTR_ALIGNMENT_SHIFT)
+			    + (addr & 0xffc) + 4;
+			/*  Is the offset from the start of the current page
+			    still within the same page? Then use the
+			    samepage_function:  */
+			if ((uint32_t)ic->arg[2] < ((MIPS_IC_ENTRIES_PER_PAGE-1)
+			    << MIPS_INSTR_ALIGNMENT_SHIFT) && (addr & 0xffc)
+			    < 0xffc) {
+				ic->arg[2] = (size_t) (cpu->cd.mips.cur_ic_page+
+				    ((ic->arg[2] >> MIPS_INSTR_ALIGNMENT_SHIFT)
+				    & (MIPS_IC_ENTRIES_PER_PAGE - 1)));
+				ic->f = samepage_function;
+			}
+			if (cpu->delay_slot) {
+				if (!cpu->translation_readahead)
+					fatal("TODO: branch in delay slot:5\n");
+				goto bad;
+			}
+			break;
+
+		case REGIMM_TGEI:
+		case REGIMM_TGEIU:
+		case REGIMM_TLTI:
+		case REGIMM_TLTIU:
+		case REGIMM_TEQI:
+		case REGIMM_TNEI:
+			switch (rt) {
+			case REGIMM_TGEI:	ic->f = instr(tgei); break;
+			case REGIMM_TGEIU:	ic->f = instr(tgeiu); break;
+			case REGIMM_TLTI:	ic->f = instr(tlti); break;
+			case REGIMM_TLTIU:	ic->f = instr(tltiu); break;
+			case REGIMM_TEQI:	ic->f = instr(teqi); break;
+			case REGIMM_TNEI:	ic->f = instr(tnei); break;
+			}
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
+			ic->arg[2] = (int64_t)(int16_t)imm;
+
+			if (cpu->cd.mips.cpu_type.isa_level < 32) {
+				static int warning = 0;
+				if (!warning && !cpu->translation_readahead) {
+					fatal("[ WARNING! Trap opcode used, but"
+					    " the %s processor does not implement "
+					    "such instructions. Only printing this "
+					    "warning once. ]\n",
+					    cpu->cd.mips.cpu_type.name);
+					warning = 1;
+				}
+				ic->f = instr(reserved);
+			}
+			break;
+
+		default:if (!cpu->translation_readahead)
+				fatal("UNIMPLEMENTED regimm rt=%i\n", rt);
+			goto bad;
+		}
+		break;
+
+	case HI6_LB:
+	case HI6_LBU:
+	case HI6_SB:
+	case HI6_LH:
+	case HI6_LHU:
+	case HI6_SH:
+	case HI6_LW:
+	case HI6_LWU:
+	case HI6_SW:
+	case HI6_LD:
+	case HI6_SD:
+		/*  TODO: LWU should probably also be x64=1?  */
+		size = 2; signedness = 0; store = 0;
+		switch (main_opcode) {
+		case HI6_LB:  size = 0; signedness = 1; break;
+		case HI6_LBU: size = 0; break;
+		case HI6_LH:  size = 1; signedness = 1; break;
+		case HI6_LHU: size = 1; break;
+		case HI6_LW:  signedness = 1; break;
+		case HI6_LWU: break;
+		case HI6_LD:  size = 3; x64 = 1; break;
+		case HI6_SB:  store = 1; size = 0; break;
+		case HI6_SH:  store = 1; size = 1; break;
+		case HI6_SW:  store = 1; break;
+		case HI6_SD:  store = 1; size = 3; x64 = 1; break;
+		}
+
+		ic->f =
+#ifdef MODE32
+		    mips32_loadstore
+#else
+		    mips_loadstore
+#endif
+		    [ (cpu->byte_order == EMUL_LITTLE_ENDIAN? 0 : 16)
+		    + store * 8 + size * 2 + signedness];
+		ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+		ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
+		ic->arg[2] = (int32_t)imm;
+
+		/*  Load into the dummy scratch register, if rt = zero  */
+		if (!store && rt == MIPS_GPR_ZERO)
+			ic->arg[0] = (size_t)&cpu->cd.mips.scratch;
+
+		if (main_opcode == HI6_LW)
+			cpu->cd.mips.combination_check = COMBINE(lw);
+		if (main_opcode == HI6_SW)
+			cpu->cd.mips.combination_check = COMBINE(sw);
+		break;
+
+	case HI6_LL:
+	case HI6_LLD:
+	case HI6_SC:
+	case HI6_SCD:
+		/*  32-bit load-linked/store-condition for ISA II and up:  */
+		/*  (64-bit load-linked/store-condition for ISA III...)  */
+		if (cpu->cd.mips.cpu_type.isa_level < 2) {
+			ic->f = instr(reserved);
+			break;
+		}
+
+		store = 0;
+		switch (main_opcode) {
+		case HI6_LL:  ic->f = instr(ll); break;
+		case HI6_LLD: ic->f = instr(lld); x64 = 1; break;
+		case HI6_SC:  ic->f = instr(sc); store = 1; break;
+		case HI6_SCD: ic->f = instr(scd); store = 1; x64 = 1; break;
+		}
+		ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+		ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
+		ic->arg[2] = (int32_t)imm;
+		if (!store && rt == MIPS_GPR_ZERO) {
+			if (!cpu->translation_readahead)
+				fatal("HM... unusual load linked\n");
+			goto bad;
+		}
+		break;
+
+	case HI6_LWL:
+	case HI6_LWR:
+	case HI6_LDL:
+	case HI6_LDR:
+	case HI6_SWL:
+	case HI6_SWR:
+	case HI6_SDL:
+	case HI6_SDR:
+		/*  TODO: replace these with faster versions...  */
+		store = 0;
+		switch (main_opcode) {
+		case HI6_LWL: ic->f = instr(lwl); break;
+		case HI6_LWR: ic->f = instr(lwr); break;
+		case HI6_LDL: ic->f = instr(ldl); x64 = 1; break;
+		case HI6_LDR: ic->f = instr(ldr); x64 = 1; break;
+		case HI6_SWL: ic->f = instr(swl); store = 1; break;
+		case HI6_SWR: ic->f = instr(swr); store = 1; break;
+		case HI6_SDL: ic->f = instr(sdl); store = 1; x64 = 1; break;
+		case HI6_SDR: ic->f = instr(sdr); store = 1; x64 = 1; break;
+		}
+		ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+		ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
+		ic->arg[2] = (int32_t)imm;
+
+		/*  Load into the dummy scratch register, if rt = zero  */
+		if (!store && rt == MIPS_GPR_ZERO)
+			ic->arg[0] = (size_t)&cpu->cd.mips.scratch;
+		break;
+
+	case HI6_LWC1:
+	case HI6_SWC1:
+	case HI6_LDC1:
+	case HI6_SDC1:
+		/*  64-bit floating-point load/store for ISA II and up...  */
+		if ((main_opcode == HI6_LDC1 || main_opcode == HI6_SDC1)
+		    && cpu->cd.mips.cpu_type.isa_level < 2) {
+			ic->f = instr(reserved);
+			break;
+		}
+
+		ic->arg[0] = (size_t)&cpu->cd.mips.coproc[1]->reg[rt];
+		ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
+		ic->arg[2] = (int32_t)imm;
+		switch (main_opcode) {
+		case HI6_LWC1: ic->f = instr(lwc1); break;
+		case HI6_LDC1: ic->f = instr(ldc1); break;
+		case HI6_SWC1: ic->f = instr(swc1); break;
+		case HI6_SDC1: ic->f = instr(sdc1); break;
+		}
+
+		/*  Cause a coprocessor unusable exception if
+		    there is no floating point coprocessor:  */
+		if (cpu->cd.mips.cpu_type.flags & NOFPU ||
+		    cpu->cd.mips.coproc[1] == NULL) {
+			ic->f = instr(cpu);
+			ic->arg[0] = 1;
+		}
+		break;
+
+	case HI6_LWC3:
+		/*  PREF (prefetch) on ISA IV and MIPS32/64:  */
+		if (cpu->cd.mips.cpu_type.isa_level >= 4) {
+			/*  Treat as nop for now:  */
+			ic->f = instr(nop);
+		} else {
+			if (!cpu->translation_readahead)
+				fatal("TODO: lwc3 not implemented yet\n");
+			goto bad;
+		}
+		break;
+
+	case HI6_LQ_MDMX:
+		if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
+			if (!cpu->translation_readahead)
+				fatal("TODO: R5900 128-bit loads\n");
+			goto bad;
+		}
+
+		if (!cpu->translation_readahead)
+			fatal("TODO: MDMX\n");
+
+		goto bad;
+		/*  break  */
+
+	case HI6_SQ_SPECIAL3:
+		if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
+			if (!cpu->translation_readahead)
+				fatal("TODO: R5900 128-bit stores\n");
+			goto bad;
+		}
+
+		if (cpu->cd.mips.cpu_type.isa_level < 32 ||
+		    cpu->cd.mips.cpu_type.isa_revision < 2) {
+			static int warning = 0;
+			if (!warning && !cpu->translation_readahead) {
+				fatal("[ WARNING! SPECIAL3 opcode used, but"
+				    " the %s processor does not implement "
+				    "such instructions. Only printing this "
+				    "warning once. ]\n",
+				    cpu->cd.mips.cpu_type.name);
+				warning = 1;
+			}
+			ic->f = instr(reserved);
+			break;
+		}
+
+		switch (s6) {
+
+		case SPECIAL3_EXT:
+			{
+				int msbd = rd, lsb = (iword >> 6) & 0x1f;
+				ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+				ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
+				ic->arg[2] = (msbd << 5) + lsb;
+				ic->f = instr(ext);
+				if (rt == MIPS_GPR_ZERO)
+					ic->f = instr(nop);
+			}
+			break;
+
+		case SPECIAL3_DEXT:
+		case SPECIAL3_DEXTM:
+		case SPECIAL3_DEXTU:
+			{
+				int msbd = rd, lsb = (iword >> 6) & 0x1f;
+				if (s6 == SPECIAL3_DEXTM)
+					msbd += 32;
+				if (s6 == SPECIAL3_DEXTU)
+					lsb += 32;
+				ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+				ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
+				ic->arg[2] = (msbd << 6) + lsb;
+				ic->f = instr(dext);
+				if (rt == MIPS_GPR_ZERO)
+					ic->f = instr(nop);
+			}
+			break;
+
+		case SPECIAL3_INS:
+			{
+				int msb = rd, lsb = (iword >> 6) & 0x1f;
+				ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+				ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
+				ic->arg[2] = (msb << 5) + lsb;
+				ic->f = instr(ins);
+				if (rt == MIPS_GPR_ZERO)
+					ic->f = instr(nop);
+			}
+			break;
+
+		case SPECIAL3_BSHFL:
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rd];
+			switch (s10) {
+			case BSHFL_WSBH:
+				ic->f = instr(wsbh);
+				break;
+			case BSHFL_SEB:
+				ic->f = instr(seb);
+				break;
+			case BSHFL_SEH:
+				ic->f = instr(seh);
+				break;
+			default:goto bad;
+			}
+			break;
+
+		case SPECIAL3_DBSHFL:
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rd];
+			switch (s10) {
+			case BSHFL_DSBH:
+				ic->f = instr(dsbh);
+				break;
+			case BSHFL_DSHD:
+				ic->f = instr(dshd);
+				break;
+			default:goto bad;
+			}
+			break;
+
+		case SPECIAL3_RDHWR:
+			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
+
+			switch (rd) {
+
+			case 0:	ic->f = instr(rdhwr_cpunum);
+				if (rt == MIPS_GPR_ZERO)
+					ic->f = instr(nop);
+				break;
+
+			case 2:	ic->f = instr(rdhwr_cc);
+				if (rt == MIPS_GPR_ZERO)
+					ic->f = instr(nop);
+				break;
+
+                        case 29: ic->f = instr(reserved);
+                                 break;
+
+			default:if (!cpu->translation_readahead)
+					fatal("unimplemented rdhwr "
+					    "register rd=%i\n", rd);
+				goto bad;
+			}
+			break;
+
+		default:goto bad;
+		}
+		break;
+
+	case HI6_CACHE:
+		/*  TODO: rt and op etc...  */
+		ic->f = instr(cache);
+		break;
+
+	default:goto bad;
+	}
+
+
+#ifdef MODE32
+	if (x64) {
+		static int has_warned = 0;
+		if (!has_warned && !cpu->translation_readahead) {
+			fatal("[ WARNING/NOTE: attempt to execute a 64-bit"
+			    " instruction on an emulated 32-bit processor; "
+			    "pc=0x%08" PRIx32" ]\n", (uint32_t)cpu->pc);
+			has_warned = 1;
+		}
+		if (cpu->translation_readahead)
+			goto bad;
+		else
+			ic->f = instr(reserved);
+	}
+#else
+	(void)x64; // avoid compiler warning
+#endif
+
+
+#define	DYNTRANS_TO_BE_TRANSLATED_TAIL
+#include "cpu_dyntrans.c" 
+#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_mips_instr.cc gxemul-0.7.0+dfsg/src/cpus/cpu_mips_instr.cc
--- gxemul-0.6.2/src/cpus/cpu_mips_instr.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_mips_instr.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,4955 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  MIPS instructions.
- *
- *  Individual functions should keep track of cpu->n_translated_instrs.
- *  (If no instruction was executed, then it should be decreased. If, say, 4
- *  instructions were combined into one function and executed, then it should
- *  be increased by 3.)
- */
-
-
-/*
- *  COPROC_AVAILABILITY_CHECK(n) checks for the coprocessor available bit for
- *  coprocessor number n, and causes a CoProcessor Unusable exception if it
- *  is not set.  (Note: For coprocessor 0 checks, use cop0_availability_check!)
- */
-#ifndef	COPROC_AVAILABILITY_CHECK
-#define	COPROC_AVAILABILITY_CHECK(x)		{		\
-		const int cpnr = (x);					\
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page) \
-		    / sizeof(struct mips_instr_call);			\
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)		\
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);			\
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);	\
-		if (!(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &	\
-		    ((1 << cpnr) << STATUS_CU_SHIFT)) ) {		\
-			mips_cpu_exception(cpu, EXCEPTION_CPU,		\
-			    0, 0, cpnr, 0, 0, 0);			\
-			return;						\
-		}							\
-	}
-#endif
-
-
-#ifndef	COP0_AVAILABILITY_CHECK_INCLUDED
-#define	COP0_AVAILABILITY_CHECK_INCLUDED
-/*
- *  cop0_availability_check() causes a CoProcessor Unusable exception if
- *  we are currently running in usermode, and the coprocessor available bit
- *  for coprocessor 0 is not set.
- *
- *  Returns 1 if ok (i.e. if the coprocessor was usable), 0 on exceptions.
- */
-int cop0_availability_check(struct cpu *cpu, struct mips_instr_call *ic)
-{
-	int in_usermode = 0;
-	struct mips_coproc *cp0 = cpu->cd.mips.coproc[0];
-
-	switch (cpu->cd.mips.cpu_type.exc_model) {
-	case EXC3K:
-		/*
-		 *  NOTE: If the KU bit is checked, Linux crashes.
-		 *  It is the PC that counts.
-		 *
-		 *  TODO: Check whether this is true or not for R4000 as well.
-		 */
-		/*  TODO: if (cp0->reg[COP0_STATUS] & MIPS1_SR_KU_CUR)  */
-		if (cpu->pc <= 0x7fffffff)
-			in_usermode = 1;
-		break;
-	default:
-		/*  R4000 etc:  (TODO: How about supervisor mode?)  */
-		if (((cp0->reg[COP0_STATUS] &
-		    STATUS_KSU_MASK) >> STATUS_KSU_SHIFT) != KSU_KERNEL)
-			in_usermode = 1;
-		if (cp0->reg[COP0_STATUS] & (STATUS_ERL | STATUS_EXL))
-			in_usermode = 0;
-		break;
-	}
-
-	if (in_usermode) {
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		if (!(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &
-		    (1 << STATUS_CU_SHIFT)) ) {
-			mips_cpu_exception(cpu, EXCEPTION_CPU,
-			    0, 0, /* cpnr */ 0, 0, 0, 0);
-			return 0;
-		}
-	}
-
-	return 1;
-}
-#endif
-
-
-/*
- *  invalid:  For catching bugs.
- */
-X(invalid)
-{
-	fatal("FATAL ERROR: An internal error occured in the MIPS"
-	    " dyntrans code. Please contact the author with detailed"
-	    " repro steps on how to trigger this bug.\n");
-	exit(1);
-}
-
-
-/*
- *  reserved:  Attempt to execute a reserved instruction (e.g. a 64-bit
- *             instruction on an emulated 32-bit processor).
- */
-X(reserved)
-{
-	/*  Synchronize the PC and cause an exception:  */
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	mips_cpu_exception(cpu, EXCEPTION_RI, 0, 0, 0, 0, 0, 0);
-}
-
-
-/*
- *  cpu:  Cause a CoProcessor Unusable exception.
- *
- *  arg[0] = the number of the coprocessor
- */
-X(cpu)
-{
-	/*  Synchronize the PC and cause an exception:  */
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0, ic->arg[0], 0, 0, 0);
-}
-
-
-/*
- *  nop:  Do nothing.
- */
-X(nop)
-{
-}
-
-
-/*
- *  beq:  Branch if equal
- *  bne:  Branch if not equal
- *  b:  Branch (comparing a register to itself, always true)
- *
- *  arg[0] = pointer to rs
- *  arg[1] = pointer to rt
- *  arg[2] = (int32_t) relative offset from the next instruction
- */
-X(beq)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	int x = rs == rt;
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(beq_samepage)
-{
-	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	int x = rs == rt;
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-X(beq_samepage_addiu)
-{
-	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	cpu->n_translated_instrs ++;
-	reg(ic[1].arg[1]) = (int32_t)
-	    ((int32_t)reg(ic[1].arg[0]) + (int32_t)ic[1].arg[2]);
-	if (rs == rt)
-		cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
-	else
-		cpu->cd.mips.next_ic ++;
-}
-X(beq_samepage_nop)
-{
-	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	cpu->n_translated_instrs ++;
-	if (rs == rt)
-		cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
-	else
-		cpu->cd.mips.next_ic ++;
-}
-X(bne)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	int x = rs != rt;
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bne_samepage)
-{
-	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	int x = rs != rt;
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-X(bne_samepage_addiu)
-{
-	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	cpu->n_translated_instrs ++;
-	reg(ic[1].arg[1]) = (int32_t)
-	    ((int32_t)reg(ic[1].arg[0]) + (int32_t)ic[1].arg[2]);
-	if (rs != rt)
-		cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
-	else
-		cpu->cd.mips.next_ic ++;
-}
-X(bne_samepage_nop)
-{
-	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	cpu->n_translated_instrs ++;
-	if (rs != rt)
-		cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
-	else
-		cpu->cd.mips.next_ic ++;
-}
-X(b)
-{
-	MODE_int_t old_pc = cpu->pc;
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-		    MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc = old_pc + (int32_t)ic->arg[2];
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(b_samepage)
-{
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)))
-		cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
-	cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  beql:  Branch if equal likely
- *  bnel:  Branch if not equal likely
- *
- *  arg[0] = pointer to rs
- *  arg[1] = pointer to rt
- *  arg[2] = (int32_t) relative offset from the next instruction
- */
-X(beql)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	int x = rs == rt;
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(beql_samepage)
-{
-	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	int x = rs == rt;
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-X(bnel)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	int x = rs != rt;
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bnel_samepage)
-{
-	MODE_uint_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	int x = rs != rt;
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  blez:   Branch if less than or equal
- *  blezl:  Branch if less than or equal likely
- *
- *  arg[0] = pointer to rs
- *  arg[2] = (int32_t) relative offset from the next instruction
- */
-X(blez)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs <= 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(blez_samepage)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs <= 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-X(blezl)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs <= 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(blezl_samepage)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs <= 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  bltz:   Branch if less than
- *  bltzl:  Branch if less than likely
- *
- *  arg[0] = pointer to rs
- *  arg[2] = (int32_t) relative offset from the next instruction
- */
-X(bltz)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs < 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bltz_samepage)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs < 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-X(bltzl)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs < 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bltzl_samepage)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs < 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  bgez:   Branch if greater than or equal
- *  bgezl:  Branch if greater than or equal likely
- *
- *  arg[0] = pointer to rs
- *  arg[2] = (int32_t) relative offset from the next instruction
- */
-X(bgez)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs >= 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bgez_samepage)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs >= 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-X(bgezl)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs >= 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bgezl_samepage)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs >= 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  bgezal:   Branch if greater than or equal (and link)
- *  bgezall:  Branch if greater than or equal (and link) likely
- *
- *  arg[0] = pointer to rs
- *  arg[2] = (int32_t) relative offset from the next instruction
- */
-X(bgezal)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs >= 0), low_pc;
-
-	cpu->delay_slot = TO_BE_DELAYED;
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
-
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bgezal_samepage)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs >= 0), low_pc;
-
-	cpu->delay_slot = TO_BE_DELAYED;
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
-
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-X(bgezall)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs >= 0), low_pc;
-
-	cpu->delay_slot = TO_BE_DELAYED;
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
-
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bgezall_samepage)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs >= 0), low_pc;
-
-	cpu->delay_slot = TO_BE_DELAYED;
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
-
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  bltzal:   Branch if less than zero (and link)
- *  bltzall:  Branch if less than zero (and link) likely
- *
- *  arg[0] = pointer to rs
- *  arg[2] = (int32_t) relative offset from the next instruction
- */
-X(bltzal)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs < 0), low_pc;
-
-	cpu->delay_slot = TO_BE_DELAYED;
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
-
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bltzal_samepage)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs < 0), low_pc;
-
-	cpu->delay_slot = TO_BE_DELAYED;
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
-
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-X(bltzall)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs < 0), low_pc;
-
-	cpu->delay_slot = TO_BE_DELAYED;
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
-
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bltzall_samepage)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs < 0), low_pc;
-
-	cpu->delay_slot = TO_BE_DELAYED;
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.mips.gpr[MIPS_GPR_RA] = cpu->pc + 8;
-
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  bgtz:   Branch if greater than zero
- *  bgtzl:  Branch if greater than zero likely
- *
- *  arg[0] = pointer to rs
- *  arg[2] = (int32_t) relative offset from the next instruction
- */
-X(bgtz)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs > 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bgtz_samepage)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs > 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-X(bgtzl)
-{
-	MODE_int_t old_pc = cpu->pc;
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs > 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bgtzl_samepage)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	int x = (rs > 0);
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x)
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		if (x)
-			cpu->cd.mips.next_ic = (struct mips_instr_call *)
-			    ic->arg[2];
-		else
-			cpu->cd.mips.next_ic ++;
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  jr, jalr: Jump to a register [and link].
- *
- *  arg[0] = ptr to rs
- *  arg[1] = ptr to rd (for jalr)
- *  arg[2] = (int32_t) relative offset of the next instruction
- */
-X(jr)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		cpu->pc = rs;
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(jr_ra)
-{
-	MODE_int_t rs = cpu->cd.mips.gpr[MIPS_GPR_RA];
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		cpu->pc = rs;
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(jr_ra_addiu)
-{
-	/*  jr ra, followed by an addiu  */
-	MODE_int_t rs = cpu->cd.mips.gpr[MIPS_GPR_RA];
-	reg(ic[1].arg[1]) = (int32_t)
-	    ((int32_t)reg(ic[1].arg[0]) + (int32_t)ic[1].arg[2]);
-	cpu->pc = rs;
-	quick_pc_to_pointers(cpu);
-	cpu->n_translated_instrs ++;
-}
-X(jr_ra_trace)
-{
-	MODE_int_t rs = cpu->cd.mips.gpr[MIPS_GPR_RA];
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		cpu->pc = rs;
-		cpu_functioncall_trace_return(cpu);
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(jalr)
-{
-	MODE_int_t rs = reg(ic->arg[0]), rd;
-	cpu->delay_slot = TO_BE_DELAYED;
-	rd = cpu->pc & ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-	    MIPS_INSTR_ALIGNMENT_SHIFT);
-	rd += (int32_t)ic->arg[2];
-	reg(ic->arg[1]) = rd;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		cpu->pc = rs;
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(jalr_trace)
-{
-	MODE_int_t rs = reg(ic->arg[0]), rd;
-	cpu->delay_slot = TO_BE_DELAYED;
-	rd = cpu->pc & ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-	    MIPS_INSTR_ALIGNMENT_SHIFT);
-	rd += (int32_t)ic->arg[2];
-	reg(ic->arg[1]) = rd;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		cpu->pc = rs;
-		cpu_functioncall_trace(cpu, cpu->pc);
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  j, jal:  Jump [and link].
- *
- *  arg[0] = lowest 28 bits of new pc.
- *  arg[1] = offset from start of page to the jal instruction + 8
- */
-X(j)
-{
-	MODE_int_t old_pc = cpu->pc;
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		old_pc &= ~0x03ffffff;
-		cpu->pc = old_pc | (uint32_t)ic->arg[0];
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(jal)
-{
-	MODE_int_t old_pc = cpu->pc;
-	cpu->delay_slot = TO_BE_DELAYED;
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.mips.gpr[31] = (MODE_int_t)cpu->pc + (int32_t)ic->arg[1];
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		old_pc &= ~0x03ffffff;
-		cpu->pc = old_pc | (int32_t)ic->arg[0];
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(jal_trace)
-{
-	MODE_int_t old_pc = cpu->pc;
-	cpu->delay_slot = TO_BE_DELAYED;
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.mips.gpr[31] = (MODE_int_t)cpu->pc + (int32_t)ic->arg[1];
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (likely(!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		old_pc &= ~0x03ffffff;
-		cpu->pc = old_pc | (int32_t)ic->arg[0];
-		cpu_functioncall_trace(cpu, cpu->pc);
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  cache:  Cache operation.
- */
-X(cache)
-{
-	/*  TODO: Implement cache operations.  */
-
-	/*  Make sure the rmw bit is cleared:  */
-	cpu->cd.mips.rmw = 0;
-}
-
-
-/*
- *  tgei:  Trap if Greater-or-Equal Immediate.
- *  tgeiu:  Trap if Greater-or-Equal Immediate Unsigned.
- *  tlti:  Trap if Less-Than Immediate.
- *  tltiu:  Trap if Less-Than Immediate Unsigned.
- *  teqi:  Trap if Equal Immediate.
- *  tnei:  Trap if Not-Equal Immediate.
- *
- *  arg[0] = pointer to rs
- *  arg[2] = immediate value, sign-extended to native word size
- */
-X(tgei)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	MODE_int_t imm = ic->arg[2];
-
-	if (rs >= imm) {
-		/*  Synchronize the PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
-	}
-}
-X(tgeiu)
-{
-	MODE_uint_t rs = reg(ic->arg[0]);
-	MODE_uint_t imm = ic->arg[2];
-
-	if (rs >= imm) {
-		/*  Synchronize the PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
-	}
-}
-X(tlti)
-{
-	MODE_int_t rs = reg(ic->arg[0]);
-	MODE_int_t imm = ic->arg[2];
-
-	if (rs < imm) {
-		/*  Synchronize the PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
-	}
-}
-X(tltiu)
-{
-	MODE_uint_t rs = reg(ic->arg[0]);
-	MODE_uint_t imm = ic->arg[2];
-
-	if (rs < imm) {
-		/*  Synchronize the PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
-	}
-}
-X(teqi)
-{
-	MODE_uint_t rs = reg(ic->arg[0]);
-	MODE_uint_t imm = ic->arg[2];
-
-	if (rs == imm) {
-		/*  Synchronize the PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
-	}
-}
-X(tnei)
-{
-	MODE_uint_t rs = reg(ic->arg[0]);
-	MODE_uint_t imm = ic->arg[2];
-
-	if (rs != imm) {
-		/*  Synchronize the PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
-	}
-}
-
-
-/*
- *  ins: Insert bitfield.
- *
- *  arg[0] = pointer to rt
- *  arg[1] = pointer to rs
- *  arg[2] = (msb << 5) + lsb
- */
-X(ins)
-{
-	int msb = ic->arg[2] >> 5, pos = ic->arg[2] & 0x1f;
-	int size = msb + 1 - pos;
-	uint32_t rt = reg(ic->arg[0]);
-	uint32_t rs = reg(ic->arg[1]);
-	uint32_t mask = (-1) << pos;
-
-	mask <<= (32 - pos - size);
-	mask >>= (32 - pos - size);
-
-	reg(ic->arg[0]) = (int32_t) ((rt & ~mask) | ((rs << pos) & mask));
-}
-
-
-/*
- *  ext:  Extract bitfield.
- *
- *  arg[0] = pointer to rt
- *  arg[1] = pointer to rs
- *  arg[2] = (msbd << 5) + lsb
- */
-X(ext)
-{
-	int msbd = ic->arg[2] >> 5, lsb = ic->arg[2] & 0x1f;
-	int size = msbd + 1;
-	uint32_t rs = reg(ic->arg[1]);
-	uint32_t x = (rs << (32-lsb-size)) >> (32-lsb-size);
-	reg(ic->arg[0]) = (int32_t) (x >> lsb);
-}
-
-
-/*
- *  dext:  Extract bitfield (64-bit).
- *
- *  arg[0] = pointer to rt
- *  arg[1] = pointer to rs
- *  arg[2] = (msbd << 6) + lsb
- */
-X(dext)
-{
-	int msbd = ic->arg[2] >> 6, lsb = ic->arg[2] & 0x3f;
-	int size = msbd + 1;
-	uint64_t rs = reg(ic->arg[1]);
-	uint64_t x = (rs << (uint64_t)(64-lsb-size)) >> (uint64_t)(64-lsb-size);
-	reg(ic->arg[0]) = x >> lsb;
-}
-
-
-/*
- *  dsbh:  Doubleword swap bytes within half-word
- *  dshd:  Doubleword swap half-words within double-word
- *  wsbh:  Word swap bytes within half-word
- *  seb:   Sign-extend byte
- *  seh:   Sign-extend half-word
- *
- *  arg[0] = pointer to rt
- *  arg[1] = pointer to rd
- */
-X(dsbh)
-{
-	uint64_t x = reg(ic->arg[0]);
-	x = ((x & 0x00ff00ff00ff00ffULL) << 8)
-	  | ((x & 0xff00ff00ff00ff00ULL) >> 8);
-	reg(ic->arg[1]) = x;
-}
-X(dshd)
-{
-	uint64_t x = reg(ic->arg[0]);
-	x = ((x & 0x000000000000ffffULL) << 48)
-	  | ((x & 0x00000000ffff0000ULL) << 16)
-	  | ((x & 0x0000ffff00000000ULL) >> 16)
-	  | ((x & 0xffff000000000000ULL) >> 48);
-	reg(ic->arg[1]) = x;
-}
-X(wsbh)
-{
-	uint32_t x = reg(ic->arg[0]);
-	x = ((x & 0x00ff00ff) << 8) | ((x & 0xff00ff00) >> 8);
-	reg(ic->arg[1]) = (int32_t) x;
-}
-X(seb) { reg(ic->arg[1]) = (int8_t)reg(ic->arg[0]); }
-X(seh) { reg(ic->arg[1]) = (int16_t)reg(ic->arg[0]); }
-
-
-/*
- *  2-register + immediate:
- *
- *  arg[0] = pointer to rs
- *  arg[1] = pointer to rt
- *  arg[2] = uint32_t immediate value
- */
-X(andi) { reg(ic->arg[1]) = reg(ic->arg[0]) & (uint32_t)ic->arg[2]; }
-X(ori)  { reg(ic->arg[1]) = reg(ic->arg[0]) | (uint32_t)ic->arg[2]; }
-X(xori) { reg(ic->arg[1]) = reg(ic->arg[0]) ^ (uint32_t)ic->arg[2]; }
-
-
-/*
- *  2-register:
- *
- *  arg[0] = ptr to rs
- *  arg[1] = ptr to rt
- */
-X(div)
-{
-	int32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	int32_t res, rem;
-	if (b == 0)
-		res = 0, rem = a;
-	else if (a == (int32_t)0x80000000U && b == -1)
-		res = 0, rem = 0;
-	else
-		res = a / b, rem = a - b*res;
-	cpu->cd.mips.lo = (int32_t)res;
-	cpu->cd.mips.hi = (int32_t)rem;
-}
-X(divu)
-{
-	uint32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	uint32_t res, rem;
-	if (b == 0)
-		res = 0, rem = a;
-	else
-		res = a / b, rem = a - b*res;
-	cpu->cd.mips.lo = (int32_t)res;
-	cpu->cd.mips.hi = (int32_t)rem;
-}
-X(ddiv)
-{
-	int64_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	int64_t res, rem;
-	if (b == 0)
-		res = 0;
-	else if (a == (int64_t)0x8000000000000000ULL && b == -1)
-		res = 0;
-	else
-		res = a / b;
-	rem = a - b*res;
-	cpu->cd.mips.lo = res;
-	cpu->cd.mips.hi = rem;
-}
-X(ddivu)
-{
-	uint64_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	uint64_t res, rem;
-	if (b == 0)
-		res = 0;
-	else
-		res = a / b;
-	rem = a - b*res;
-	cpu->cd.mips.lo = res;
-	cpu->cd.mips.hi = rem;
-}
-X(mult)
-{
-	int32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	int64_t res = (int64_t)a * (int64_t)b;
-	cpu->cd.mips.lo = (int32_t)res;
-	cpu->cd.mips.hi = (int32_t)(res >> 32);
-}
-X(mult_r5900)
-{
-	/*  C790/TX79/R5900 multiplication, stores result in
-	    hi, lo, and a third register  */
-	int32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	int64_t res = (int64_t)a * (int64_t)b;
-	cpu->cd.mips.lo = (int32_t)res;
-	cpu->cd.mips.hi = (int32_t)(res >> 32);
-	reg(ic->arg[2]) = (int32_t)res;
-}
-X(multu)
-{
-	uint32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	uint64_t res = (uint64_t)a * (uint64_t)b;
-	cpu->cd.mips.lo = (int32_t)res;
-	cpu->cd.mips.hi = (int32_t)(res >> 32);
-}
-X(multu_r5900)
-{
-	/*  C790/TX79/R5900 multiplication, stores result in
-	    hi, lo, and a third register  */
-	uint32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	uint64_t res = (uint64_t)a * (uint64_t)b;
-	cpu->cd.mips.lo = (int32_t)res;
-	cpu->cd.mips.hi = (int32_t)(res >> 32);
-	reg(ic->arg[2]) = (int32_t)res;
-}
-X(dmult)
-{
-	uint64_t a = reg(ic->arg[0]), b = reg(ic->arg[1]), c = 0;
-	uint64_t hi = 0, lo = 0;
-	int neg = 0;
-	if (a >> 63)
-		neg = !neg, a = -a;
-	if (b >> 63)
-		neg = !neg, b = -b;
-	for (; a; a >>= 1) {
-		if (a & 1) {
-			uint64_t old_lo = lo;
-			hi += c;
-			lo += b;
-			if (lo < old_lo)
-				hi ++;
-		}
-		c = (c << 1) | (b >> 63); b <<= 1;
-	}
-	if (neg) {
-		if (lo == 0)
-			hi --;
-		lo --;
-		hi ^= (int64_t) -1;
-		lo ^= (int64_t) -1;
-	}
-	cpu->cd.mips.lo = lo;
-	cpu->cd.mips.hi = hi;
-}
-X(dmultu)
-{
-	uint64_t a = reg(ic->arg[0]), b = reg(ic->arg[1]), c = 0;
-	uint64_t hi = 0, lo = 0;
-	for (; a; a >>= 1) {
-		if (a & 1) {
-			uint64_t old_lo = lo;
-			hi += c;
-			lo += b;
-			if (lo < old_lo)
-				hi ++;
-		}
-		c = (c << 1) | (b >> 63); b <<= 1;
-	}
-	cpu->cd.mips.lo = lo;
-	cpu->cd.mips.hi = hi;
-}
-X(tge)
-{
-	MODE_int_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	if (a >= b) {
-		/*  Synch. PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
-	}
-}
-X(tgeu)
-{
-	MODE_uint_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	if (a >= b) {
-		/*  Synch. PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
-	}
-}
-X(tlt)
-{
-	MODE_int_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	if (a < b) {
-		/*  Synch. PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
-	}
-}
-X(tltu)
-{
-	MODE_uint_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	if (a < b) {
-		/*  Synch. PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
-	}
-}
-X(teq)
-{
-	MODE_uint_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	if (a == b) {
-		/*  Synch. PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
-	}
-}
-X(tne)
-{
-	MODE_uint_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	if (a != b) {
-		/*  Synch. PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
-	}
-}
-
-
-/*
- *  3-register arithmetic instructions:
- *
- *  arg[0] = ptr to rs
- *  arg[1] = ptr to rt
- *  arg[2] = ptr to rd
- */
-X(addu) { reg(ic->arg[2]) = (int32_t)(reg(ic->arg[0]) + reg(ic->arg[1])); }
-X(add)
-{
-	int32_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	int32_t rd = rs + rt;
-
-	if (unlikely((rs >= 0 && rt >= 0 && rd < 0) || (rs < 0 && rt < 0 && rd >= 0))) {
-		/*  Synch. PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0);
-	} else
-		reg(ic->arg[2]) = rd;
-}
-X(daddu){ reg(ic->arg[2]) = reg(ic->arg[0]) + reg(ic->arg[1]); }
-X(dadd)
-{
-	int64_t rs = reg(ic->arg[0]), rt = reg(ic->arg[1]);
-	int64_t rd = rs + rt;
-
-	if (unlikely((rs >= 0 && rt >= 0 && rd < 0) || (rs < 0 && rt < 0 && rd >= 0))) {
-		/*  Synch. PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0);
-	} else
-		reg(ic->arg[2]) = rd;
-}
-X(subu) { reg(ic->arg[2]) = (int32_t)(reg(ic->arg[0]) - reg(ic->arg[1])); }
-X(sub)
-{
-	/*  NOTE: Negating rt and using addition. TODO: Is this correct?  */
-	int32_t rs = reg(ic->arg[0]), rt = - reg(ic->arg[1]);
-	int32_t rd = rs + rt;
-
-	if (unlikely((rs >= 0 && rt >= 0 && rd < 0) || (rs < 0 && rt < 0 && rd >= 0))) {
-		/*  Synch. PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0);
-	} else
-		reg(ic->arg[2]) = rd;
-}
-X(dsubu){ reg(ic->arg[2]) = reg(ic->arg[0]) - reg(ic->arg[1]); }
-X(dsub)
-{
-	/*  NOTE: Negating rt and using addition. TODO: Is this correct?  */
-	int64_t rs = reg(ic->arg[0]), rt = - reg(ic->arg[1]);
-	int64_t rd = rs + rt;
-
-	if (unlikely((rs >= 0 && rt >= 0 && rd < 0) || (rs < 0 && rt < 0 && rd >= 0))) {
-		/*  Synch. PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0);
-	} else
-		reg(ic->arg[2]) = rd;
-}
-X(slt) {
-	reg(ic->arg[2]) =
-	    (MODE_int_t)reg(ic->arg[0]) < (MODE_int_t)reg(ic->arg[1]);
-}
-X(sltu) {
-	reg(ic->arg[2]) =
-	    (MODE_uint_t)reg(ic->arg[0]) < (MODE_uint_t)reg(ic->arg[1]);
-}
-X(and) { reg(ic->arg[2]) = reg(ic->arg[0]) & reg(ic->arg[1]); }
-X(or)  { reg(ic->arg[2]) = reg(ic->arg[0]) | reg(ic->arg[1]); }
-X(xor) { reg(ic->arg[2]) = reg(ic->arg[0]) ^ reg(ic->arg[1]); }
-X(nor) { reg(ic->arg[2]) = ~(reg(ic->arg[0]) | reg(ic->arg[1])); }
-X(sll) { reg(ic->arg[2]) = (int32_t)(reg(ic->arg[0]) << (int32_t)ic->arg[1]); }
-X(sllv){ int32_t sa = reg(ic->arg[1]) & 31;
-	 reg(ic->arg[2]) = (int32_t)(reg(ic->arg[0]) << sa); }
-X(srl) { reg(ic->arg[2]) = (int32_t)((uint32_t)reg(ic->arg[0]) >> ic->arg[1]); }
-X(srlv){ int32_t sa = reg(ic->arg[1]) & 31;
-	 reg(ic->arg[2]) = (int32_t)((uint32_t)reg(ic->arg[0]) >> sa); }
-X(sra) { reg(ic->arg[2]) = (int32_t)((int32_t)reg(ic->arg[0]) >> ic->arg[1]); }
-X(srav){ int32_t sa = reg(ic->arg[1]) & 31;
-	 reg(ic->arg[2]) = (int32_t)((int32_t)reg(ic->arg[0]) >> sa); }
-X(dsll) { reg(ic->arg[2]) = (int64_t)reg(ic->arg[0]) << (int64_t)ic->arg[1]; }
-X(dsllv){ int64_t sa = reg(ic->arg[1]) & 63;
-	 reg(ic->arg[2]) = reg(ic->arg[0]) << sa; }
-X(dsrl) { reg(ic->arg[2]) = (int64_t)((uint64_t)reg(ic->arg[0]) >>
-	(uint64_t) ic->arg[1]);}
-X(dsrlv){ int64_t sa = reg(ic->arg[1]) & 63;
-	 reg(ic->arg[2]) = (uint64_t)reg(ic->arg[0]) >> sa; }
-X(dsra) { reg(ic->arg[2]) = (int64_t)reg(ic->arg[0]) >> (int64_t)ic->arg[1]; }
-X(dsrav){ int64_t sa = reg(ic->arg[1]) & 63;
-	 reg(ic->arg[2]) = (int64_t)reg(ic->arg[0]) >> sa; }
-X(mul) { reg(ic->arg[2]) = (int32_t)
-	( (int32_t)reg(ic->arg[0]) * (int32_t)reg(ic->arg[1]) ); }
-X(movn) { if (reg(ic->arg[1])) reg(ic->arg[2]) = reg(ic->arg[0]); }
-X(movz) { if (!reg(ic->arg[1])) reg(ic->arg[2]) = reg(ic->arg[0]); }
-
-X(ror)
-{
-	uint32_t result = reg(ic->arg[0]);
-	int sa = ic->arg[1];
-
-	result = (result >> sa) | (result << (32-sa));
-
-	reg(ic->arg[2]) = (int32_t) result;
-}
-
-X(rorv)
-{
-	uint32_t result = reg(ic->arg[0]);
-	int sa = reg(ic->arg[1]);
-
-	result = (result >> sa) | (result << (32-sa));
-
-	reg(ic->arg[2]) = (int32_t) result;
-}
-
-
-/*
- *  p*:  128-bit C790/TX79/R5900 stuff
- *
- *  arg[0] = rs (note: not a pointer)
- *  arg[1] = rt (note: not a pointer)
- *  arg[2] = rd (note: not a pointer)
- */
-X(por)
-{
-	cpu->cd.mips.gpr[ic->arg[2]] = cpu->cd.mips.gpr[ic->arg[0]] |
-	    cpu->cd.mips.gpr[ic->arg[1]];
-	cpu->cd.mips.gpr_quadhi[ic->arg[2]] =
-	    cpu->cd.mips.gpr_quadhi[ic->arg[0]] |
-	    cpu->cd.mips.gpr_quadhi[ic->arg[1]];
-}
-X(pextlw)
-{
-	uint64_t lo, hi;
-
-	lo = (uint32_t)cpu->cd.mips.gpr[ic->arg[1]] |
-	    (uint64_t)((uint64_t)cpu->cd.mips.gpr[ic->arg[0]] << 32);
-	hi = (cpu->cd.mips.gpr[ic->arg[0]] & 0xffffffff00000000ULL) |
-	    (uint32_t)((uint64_t)cpu->cd.mips.gpr[ic->arg[1]] >> 32);
-
-	cpu->cd.mips.gpr[ic->arg[2]] = lo;
-	cpu->cd.mips.gpr_quadhi[ic->arg[2]] = hi;
-}
-
-
-/*
- *  madd, maddu, msub, msubu: Multiply-and-add/subtract
- *
- *  arg[0] = ptr to rs
- *  arg[1] = ptr to rt
- *  arg[2] = ptr to rd (only used on R5900/TX79)
- */
-X(madd)
-{
-	int64_t rs = (int32_t)reg(ic->arg[0]), rt = (int32_t)reg(ic->arg[1]);
-	int64_t sum = rs * rt,
-	    hilo = (cpu->cd.mips.hi << 32) | (uint32_t)(cpu->cd.mips.lo);
-	hilo += sum;
-	cpu->cd.mips.hi = (int32_t)(hilo>>32); cpu->cd.mips.lo = (int32_t)hilo;
-}
-X(madd_rd)
-{
-	int64_t rs = (int32_t)reg(ic->arg[0]), rt = (int32_t)reg(ic->arg[1]);
-	int64_t sum = rs * rt,
-	    hilo = (cpu->cd.mips.hi << 32) | (uint32_t)(cpu->cd.mips.lo);
-	hilo += sum;
-	cpu->cd.mips.hi = (int32_t)(hilo>>32); cpu->cd.mips.lo = (int32_t)hilo;
-	reg(ic->arg[2]) = (int32_t)hilo;
-}
-X(msub)
-{
-	int64_t rs = (int32_t)reg(ic->arg[0]), rt = (int32_t)reg(ic->arg[1]);
-	int64_t sum = rs * rt,
-	    hilo = (cpu->cd.mips.hi << 32) | (uint32_t)(cpu->cd.mips.lo);
-	hilo -= sum;
-	cpu->cd.mips.hi = (int32_t)(hilo>>32); cpu->cd.mips.lo = (int32_t)hilo;
-}
-X(maddu)
-{
-	int64_t rs = (uint32_t)reg(ic->arg[0]), rt = (uint32_t)reg(ic->arg[1]);
-	int64_t sum = rs * rt,
-	    hilo = (cpu->cd.mips.hi << 32) | (uint32_t)(cpu->cd.mips.lo);
-	hilo += sum;
-	cpu->cd.mips.hi = (int32_t)(hilo>>32); cpu->cd.mips.lo = (int32_t)hilo;
-}
-X(maddu_rd)
-{
-	int64_t rs = (uint32_t)reg(ic->arg[0]), rt = (uint32_t)reg(ic->arg[1]);
-	int64_t sum = rs * rt,
-	    hilo = (cpu->cd.mips.hi << 32) | (uint32_t)(cpu->cd.mips.lo);
-	hilo += sum;
-	cpu->cd.mips.hi = (int32_t)(hilo>>32); cpu->cd.mips.lo = (int32_t)hilo;
-	reg(ic->arg[2]) = (int32_t)hilo;
-}
-X(msubu)
-{
-	int64_t rs = (uint32_t)reg(ic->arg[0]), rt = (uint32_t)reg(ic->arg[1]);
-	int64_t sum = rs * rt,
-	    hilo = (cpu->cd.mips.hi << 32) | (uint32_t)(cpu->cd.mips.lo);
-	hilo -= sum;
-	cpu->cd.mips.hi = (int32_t)(hilo>>32); cpu->cd.mips.lo = (int32_t)hilo;
-}
-
-
-/*
- *  mov:  Move one register into another.
- *
- *  arg[0] = pointer to source
- *  arg[2] = pointer to destination
- */
-X(mov)  { reg(ic->arg[2]) = reg(ic->arg[0]); }
-
-
-/*
- *  clz, clo, dclz, dclo: Count leading zeroes/ones.
- *
- *  arg[0] = pointer to rs
- *  arg[1] = pointer to rd
- */
-X(clz)
-{
-	uint32_t x = reg(ic->arg[0]);
-	int count;
-	for (count=0; count<32; count++) {
-		if (x & 0x80000000UL)
-			break;
-		x <<= 1;
-	}
-	reg(ic->arg[1]) = count;
-}
-X(clo)
-{
-	uint32_t x = reg(ic->arg[0]);
-	int count;
-	for (count=0; count<32; count++) {
-		if (!(x & 0x80000000UL))
-			break;
-		x <<= 1;
-	}
-	reg(ic->arg[1]) = count;
-}
-X(dclz)
-{
-	uint64_t x = reg(ic->arg[0]);
-	int count;
-	for (count=0; count<64; count++) {
-		if (x & 0x8000000000000000ULL)
-			break;
-		x <<= 1;
-	}
-	reg(ic->arg[1]) = count;
-}
-X(dclo)
-{
-	uint64_t x = reg(ic->arg[0]);
-	int count;
-	for (count=0; count<64; count++) {
-		if (!(x & 0x8000000000000000ULL))
-			break;
-		x <<= 1;
-	}
-	reg(ic->arg[1]) = count;
-}
-
-
-/*
- *  addi, daddi: Add immediate, overflow detection.
- *  addiu, daddiu: Add immediate.
- *  slti:   Set if less than immediate (signed 32-bit)
- *  sltiu:  Set if less than immediate (signed 32-bit, but unsigned compare)
- *
- *  arg[0] = pointer to rs
- *  arg[1] = pointer to rt
- *  arg[2] = (int32_t) immediate value
- */
-X(addi)
-{
-	int32_t rs = reg(ic->arg[0]), imm = (int32_t)ic->arg[2];
-	int32_t rt = rs + imm;
-
-	if (unlikely((rs >= 0 && imm >= 0 && rt < 0) || (rs < 0 && imm < 0 && rt >= 0))) {
-		/*  Synch. PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0);
-	} else
-		reg(ic->arg[1]) = rt;
-}
-X(addiu)
-{
-	reg(ic->arg[1]) = (int32_t)
-	    ((int32_t)reg(ic->arg[0]) + (int32_t)ic->arg[2]);
-}
-X(daddi)
-{
-	int64_t rs = reg(ic->arg[0]), imm = (int32_t)ic->arg[2];
-	int64_t rt = rs + imm;
-
-	if (unlikely((rs >= 0 && imm >= 0 && rt < 0) || (rs < 0 && imm < 0 && rt >= 0))) {
-		/*  Synch. PC and cause an exception:  */
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-		    / sizeof(struct mips_instr_call);
-		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-		mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0);
-	} else
-		reg(ic->arg[1]) = rt;
-}
-X(daddiu)
-{
-	reg(ic->arg[1]) = reg(ic->arg[0]) + (int32_t)ic->arg[2];
-}
-X(slti)
-{
-	reg(ic->arg[1]) = (MODE_int_t)reg(ic->arg[0]) < (int32_t)ic->arg[2];
-}
-X(sltiu)
-{
-	reg(ic->arg[1]) = (MODE_uint_t)reg(ic->arg[0]) <
-	   ((MODE_uint_t)(int32_t)ic->arg[2]);
-}
-
-
-/*
- *  set:  Set a register to an immediate (signed) 32-bit value.
- *        (This is the actual implementation of the lui instruction.)
- *
- *  arg[0] = pointer to the register
- *  arg[1] = (int32_t) immediate value
- */
-X(set)
-{
-	reg(ic->arg[0]) = (int32_t)ic->arg[1];
-}
-
-
-/*
- *  cfc0:         Copy from Coprocessor 0.
- *  mfc0, dmfc0:  Move from Coprocessor 0.
- *  mtc0, dmtc0:  Move to Coprocessor 0.
- *
- *  arg[0] = pointer to GPR (rt)
- *  arg[1] = coprocessor 0 register number | (select << 5)   (or for the
- *           cfc0 instruction, the coprocessor control register number)
- *  arg[2] = relative addr of this instruction within the page
- */
-X(cfc0)
-{
-	int fs = ic->arg[1] & 31;
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc |= ic->arg[2];
-	/*  TODO: cause exception if necessary  */
-	reg(ic->arg[0]) = (int32_t)cpu->cd.mips.coproc[0]->fcr[fs];
-}
-X(mfc0)
-{
-	int rd = ic->arg[1] & 31, select = ic->arg[1] >> 5;
-	uint64_t tmp;
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc |= ic->arg[2];
-	/*  TODO: cause exception if necessary  */
-	coproc_register_read(cpu, cpu->cd.mips.coproc[0], rd, &tmp, select);
-	reg(ic->arg[0]) = (int32_t)tmp;
-}
-X(mfc0_select0)
-{
-	/*  Fast int32_t read, with no side effects:  */
-	int rd = ic->arg[1] & 31;
-#if 0
-	uint64_t tmp;
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc |= ic->arg[2];
-	/*  TODO: cause exception if necessary  */
-#endif
-	reg(ic->arg[0]) = (int32_t)cpu->cd.mips.coproc[0]->reg[rd];
-}
-X(mtc0)
-{
-	int rd = ic->arg[1] & 31, select = ic->arg[1] >> 5;
-	uint64_t tmp = (int32_t) reg(ic->arg[0]);
-
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc |= ic->arg[2];
-
-	/*  TODO: cause exception if necessary  */
-	coproc_register_write(cpu, cpu->cd.mips.coproc[0], rd, &tmp, 0, select);
-
-	/*
-	 *  Interrupts enabled, and any interrupt pending? (Note/TODO: This
-	 *  code is duplicated in cpu_dyntrans.c. Fix this?)
-	 */
-	if (rd == COP0_STATUS && !cpu->delay_slot) {
-		uint32_t status = cpu->cd.mips.coproc[0]->reg[COP0_STATUS];
-		uint32_t cause = cpu->cd.mips.coproc[0]->reg[COP0_CAUSE];
-		/*  NOTE: STATUS_IE happens to match the enable bit also
-		    on R2000/R3000, so this is ok.  */
-		if (cpu->cd.mips.cpu_type.exc_model != EXC3K) {
-			if (status & (STATUS_EXL | STATUS_ERL))
-				status &= ~STATUS_IE;
-		}
-		/*  Ugly R5900 special case:  (TODO: move this?)  */
-		if (cpu->cd.mips.cpu_type.rev == MIPS_R5900 &&
-		    !(status & R5900_STATUS_EIE))
-			status &= ~STATUS_IE;
-		if (status & STATUS_IE && (status & cause & STATUS_IM_MASK)) {
-			cpu->pc += sizeof(uint32_t);
-			mips_cpu_exception(cpu, EXCEPTION_INT, 0, 0,0,0,0,0);
-		}
-	}
-}
-X(dmfc0)
-{
-	int rd = ic->arg[1] & 31, select = ic->arg[1] >> 5;
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc |= ic->arg[2];
-	/*  TODO: cause exception if necessary  */
-	coproc_register_read(cpu, cpu->cd.mips.coproc[0], rd,
-	    (uint64_t *)ic->arg[0], select);
-}
-X(dmfc0_select0)
-{
-	/*  Fast int64_t read, with no side effects:  */
-	int rd = ic->arg[1] & 31;
-#if 0
-	uint64_t tmp;
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc |= ic->arg[2];
-	/*  TODO: cause exception if necessary  */
-#endif
-	reg(ic->arg[0]) = cpu->cd.mips.coproc[0]->reg[rd];
-}
-X(dmtc0)
-{
-	int rd = ic->arg[1] & 31, select = ic->arg[1] >> 5;
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc |= ic->arg[2];
-	/*  TODO: cause exception if necessary  */
-	coproc_register_write(cpu, cpu->cd.mips.coproc[0], rd,
-	    (uint64_t *)ic->arg[0], 1, select);
-}
-
-
-/*
- *  cop1_bc:  Floating point conditional branch.
- *
- *  arg[0] = cc
- *  arg[1] = nd (=2) and tf (=1) bits
- *  arg[2] = offset (relative to start of this page)
- */
-X(cop1_bc)
-{
-	MODE_int_t old_pc = cpu->pc;
-	int x, cc = ic->arg[0];
-
-	COPROC_AVAILABILITY_CHECK(1);
-
-	/*  Get the correct condition code bit:  */
-	if (cc == 0)
-		x = (cpu->cd.mips.coproc[1]->fcr[MIPS_FPU_FCSR]
-		    >> MIPS_FCSR_FCC0_SHIFT) & 1;
-	else
-		x = (cpu->cd.mips.coproc[1]->fcr[MIPS_FPU_FCSR]
-		    >> (MIPS_FCSR_FCC1_SHIFT + cc-1)) & 1;
-
-	/*  Branch on false? Then invert the truth value.  */
-	if (!(ic->arg[1] & 1))
-		x ^= 1;
-
-	/*  Execute the delay slot (except if it is nullified):  */
-	cpu->delay_slot = TO_BE_DELAYED;
-	if (x || !(ic->arg[1] & 2))
-		ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		/*  Note: Must be non-delayed when jumping to the new pc:  */
-		cpu->delay_slot = NOT_DELAYED;
-		if (x) {
-			old_pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT);
-			cpu->pc = old_pc + (int32_t)ic->arg[2];
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.mips.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  cop1_slow:  Fallback to legacy cop1 code. (Slow, but it should work.)
- */
-X(cop1_slow)
-{
-	COPROC_AVAILABILITY_CHECK(1);
-
-	coproc_function(cpu, cpu->cd.mips.coproc[1], 1, ic->arg[0], 0, 1);
-}
-
-
-/*
- *  syscall, break:  Synchronize the PC and cause an exception.
- */
-X(syscall)
-{
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<< MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	mips_cpu_exception(cpu, EXCEPTION_SYS, 0, 0, 0, 0, 0, 0);
-}
-X(break)
-{
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<< MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	mips_cpu_exception(cpu, EXCEPTION_BP, 0, 0, 0, 0, 0, 0);
-}
-X(reboot)
-{
-	if (!cop0_availability_check(cpu, ic))
-		return;
-
-	cpu->running = 0;
-	debugger_n_steps_left_before_interaction = 0;
-	cpu->cd.mips.next_ic = &nothing_call;
-}
-
-
-/*
- *  promemul:  PROM software emulation.
- */
-X(promemul)
-{
-	/*  Synchronize the PC and call the correct emulation layer:  */
-	MODE_int_t old_pc;
-	int res, low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<< MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	old_pc = cpu->pc;
-
-	switch (cpu->machine->machine_type) {
-	case MACHINE_PMAX:
-		res = decstation_prom_emul(cpu);
-		break;
-	case MACHINE_PS2:
-		res = playstation2_sifbios_emul(cpu);
-		break;
-	case MACHINE_ARC:
-	case MACHINE_SGI:
-		res = arcbios_emul(cpu);
-		break;
-	case MACHINE_EVBMIPS:
-		res = yamon_emul(cpu);
-		break;
-	default:fatal("TODO: Unimplemented machine type for PROM magic trap\n");
-		exit(1);
-	}
-
-	if (res) {
-		/*  Return from the PROM call:  */
-		cpu->pc = (MODE_int_t)cpu->cd.mips.gpr[MIPS_GPR_RA];
-		cpu->delay_slot = NOT_DELAYED;
-
-		if (cpu->machine->show_trace_tree)
-			cpu_functioncall_trace_return(cpu);
-	} else {
-		/*  The PROM call blocks.  */
-		cpu->n_translated_instrs += 10;
-		cpu->pc = old_pc;
-	}
-
-	quick_pc_to_pointers(cpu);
-}
-
-
-/*
- *  tlbw: TLB write indexed and random
- *
- *  arg[0] = 1 for random, 0 for indexed
- *  arg[2] = relative addr of this instruction within the page
- */
-X(tlbw)
-{
-	if (!cop0_availability_check(cpu, ic))
-		return;
-
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc |= ic->arg[2];
-	coproc_tlbwri(cpu, ic->arg[0]);
-}
-
-
-/*
- *  tlbp: TLB probe
- *  tlbr: TLB read
- *
- *  arg[2] = relative addr of this instruction within the page
- */
-X(tlbp)
-{
-	if (!cop0_availability_check(cpu, ic))
-		return;
-
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc |= ic->arg[2];
-	coproc_tlbpr(cpu, 0);
-}
-X(tlbr)
-{
-	if (!cop0_availability_check(cpu, ic))
-		return;
-
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc |= ic->arg[2];
-	coproc_tlbpr(cpu, 1);
-}
-
-
-/*
- *  ei_or_di:  MIPS32/64 rev 2, Enable or disable interrupts
- *
- *  arg[0] = ptr to rt
- *  arg[1] = non-zero to enable interrupts
- */
-X(ei_or_di)
-{
-	reg(ic->arg[0]) = cpu->cd.mips.coproc[0]->reg[COP0_STATUS];
-	if (ic->arg[1])
-		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |= STATUS_IE;
-	else
-		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_IE;
-}
-
-
-/*
- *  rfe: Return from exception handler (R2000/R3000)
- */
-X(rfe)
-{
-	if (!cop0_availability_check(cpu, ic))
-		return;
-
-	/*  Just rotate the interrupt/user bits:  */
-	cpu->cd.mips.coproc[0]->reg[COP0_STATUS] =
-	    (cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & ~0x3f) |
-	    ((cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & 0x3c) >> 2);
-
-	/*
-	 *  Note: no pc to pointers conversion is necessary here. Usually the
-	 *  rfe instruction resides in the delay slot of a jr k0/k1, and
-	 *  it is up to that instruction to do the pointer conversion.
-	 */
-}
-
-
-/*
- *  eret: Return from exception handler (non-R3000 style)
- */
-X(eret)
-{
-	if (!cop0_availability_check(cpu, ic))
-		return;
-
-	if (cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & STATUS_ERL) {
-		cpu->pc = cpu->cd.mips.coproc[0]->reg[COP0_ERROREPC];
-		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_ERL;
-	} else {
-		cpu->pc = cpu->cd.mips.coproc[0]->reg[COP0_EPC];
-		cpu->delay_slot = 0;             
-		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_EXL;
-	}
-
-	quick_pc_to_pointers(cpu);
-
-	cpu->cd.mips.rmw = 0;   /*  the "LL bit"  */
-}
-
-
-/*
- *  deret: Return from debug (EJTAG) handler
- */
-X(deret)
-{
-	if (!cop0_availability_check(cpu, ic))
-		return;
-
-	/*
-	 *  According to the MIPS64 manual, deret loads PC from the DEPC cop0
-	 *  register, and jumps there immediately. No delay slot.
-	 *
-	 *  TODO: This instruction is only available if the processor is in
-	 *  debug mode. (What does that mean?)
-	 *
-	 *  TODO: This instruction is undefined in a delay slot.
-	 */
-
-	cpu->pc = cpu->cd.mips.coproc[0]->reg[COP0_DEPC];
-	cpu->delay_slot = 0;
-	cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_EXL;
-	quick_pc_to_pointers(cpu);
-}
-
-
-/*
- *  idle:  Called from the implementation of wait, or netbsd_pmax_idle.
- */
-X(idle)
-{
-	/*
-	 *  If there is an interrupt, then just return. Otherwise
-	 *  re-run the wait instruction (after a delay).
-	 */
-	uint32_t status = cpu->cd.mips.coproc[0]->reg[COP0_STATUS];
-	uint32_t cause = cpu->cd.mips.coproc[0]->reg[COP0_CAUSE];
-
-	if (cpu->cd.mips.cpu_type.exc_model != EXC3K) {
-		if (status & (STATUS_EXL | STATUS_ERL))
-			status &= ~STATUS_IE;
-	}
-
-	/*  Ugly R5900 special case:  (TODO: move this?)  */
-	if (cpu->cd.mips.cpu_type.rev == MIPS_R5900 &&
-	    !(status & R5900_STATUS_EIE))
-		status &= ~STATUS_IE;
-	if (status & STATUS_IE && (status & cause & STATUS_IM_MASK))
-		return;
-
-	cpu->cd.mips.next_ic = ic;
-	cpu->is_halted = 1;
-	cpu->has_been_idling = 1;
-
-	/*
-	 *  There was no interrupt. Go to sleep.
-	 *
-	 *  TODO:
-	 *
-	 *  Think about how to actually implement this usleep stuff,
-	 *  in an SMP and/or timing accurate environment.
-	 */
-
-	if (cpu->machine->ncpus == 1) {
-		static int x = 0;
-
-		if ((++x) == 300) {
-			usleep(20);
-			x = 0;
-		}
-
-		cpu->n_translated_instrs += N_SAFE_DYNTRANS_LIMIT / 6;
-	}
-}
-
-
-/*
- *  wait: Wait for external interrupt.
- */
-X(wait)
-{
-	if (!cop0_availability_check(cpu, ic))
-		return;
-
-	instr(idle)(cpu, ic);
-}
-
-
-/*
- *  rdhwr: Read CPUNum hardware register into gpr (MIPS32/64 rev 2).
- *
- *  arg[0] = ptr to rt (destination register)
- */
-X(rdhwr_cpunum)
-{
-	reg(ic->arg[0]) = cpu->cpu_id;
-}
-
-
-/*
- *  rdhwr: Read CC (cycle count) register into gpr (MIPS32/64 rev 2).
- *
- *  arg[0] = ptr to rt (destination register)
- */
-X(rdhwr_cc)
-{
-	reg(ic->arg[0]) = cpu->cd.mips.coproc[0]->reg[COP0_COUNT];
-}
-
-
-#include "tmp_mips_loadstore.cc"
-
-
-/*
- *  Load linked / store conditional:
- *
- *  A Load-linked instruction initiates a RMW (read-modify-write) sequence.
- *  COP0_LLADDR is updated for diagnostic purposes, except for CPUs in the
- *  R10000 family.
- *
- *  A Store-conditional instruction ends the sequence.
- *
- *  arg[0] = ptr to rt
- *  arg[1] = ptr to rs
- *  arg[2] = int32_t imm
- */
-X(ll)
-{
-	MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
-	int low_pc;
-	uint8_t word[sizeof(uint32_t)];
-
-	/*  Synch. PC and load using slow memory_rw():  */
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-
-	if (addr & (sizeof(word)-1)) {
-		fatal("TODO: load linked unaligned access: exception\n");
-		exit(1);
-	}
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, word,
-	    sizeof(word), MEM_READ, CACHE_DATA)) {
-		/*  An exception occurred.  */
-		return;
-	}
-
-	cpu->cd.mips.rmw = 1;
-	cpu->cd.mips.rmw_addr = addr;
-	cpu->cd.mips.rmw_len = sizeof(word);
-	if (cpu->cd.mips.cpu_type.exc_model != MMU10K)
-		cpu->cd.mips.coproc[0]->reg[COP0_LLADDR] =
-		    (addr >> 4) & 0xffffffffULL;
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		reg(ic->arg[0]) = (int32_t) (word[0] + (word[1] << 8)
-		    + (word[2] << 16) + (word[3] << 24));
-	else
-		reg(ic->arg[0]) = (int32_t) (word[3] + (word[2] << 8)
-		    + (word[1] << 16) + (word[0] << 24));
-}
-X(lld)
-{
-	MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
-	int low_pc;
-	uint8_t word[sizeof(uint64_t)];
-
-	/*  Synch. PC and load using slow memory_rw():  */
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-
-	if (addr & (sizeof(word)-1)) {
-		fatal("TODO: load linked unaligned access: exception\n");
-		exit(1);
-	}
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, word,
-	    sizeof(word), MEM_READ, CACHE_DATA)) {
-		/*  An exception occurred.  */
-		return;
-	}
-
-	cpu->cd.mips.rmw = 1;
-	cpu->cd.mips.rmw_addr = addr;
-	cpu->cd.mips.rmw_len = sizeof(word);
-	if (cpu->cd.mips.cpu_type.exc_model != MMU10K)
-		cpu->cd.mips.coproc[0]->reg[COP0_LLADDR] =
-		    (addr >> 4) & 0xffffffffULL;
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		reg(ic->arg[0]) = word[0] + (word[1] << 8)
-		    + (word[2] << 16) + ((uint64_t)word[3] << 24) +
-		    + ((uint64_t)word[4] << 32) + ((uint64_t)word[5] << 40)
-		    + ((uint64_t)word[6] << 48) + ((uint64_t)word[7] << 56);
-	else
-		reg(ic->arg[0]) = word[7] + (word[6] << 8)
-		    + (word[5] << 16) + ((uint64_t)word[4] << 24) +
-		    + ((uint64_t)word[3] << 32) + ((uint64_t)word[2] << 40)
-		    + ((uint64_t)word[1] << 48) + ((uint64_t)word[0] << 56);
-}
-X(sc)
-{
-	MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
-	uint64_t r = reg(ic->arg[0]);
-	int low_pc, i;
-	uint8_t word[sizeof(uint32_t)];
-
-	/*  Synch. PC and store using slow memory_rw():  */
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-
-	if (addr & (sizeof(word)-1)) {
-		fatal("TODO: sc unaligned access: exception\n");
-		exit(1);
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		word[0]=r; word[1]=r>>8; word[2]=r>>16; word[3]=r>>24;
-	} else {
-		word[3]=r; word[2]=r>>8; word[1]=r>>16; word[0]=r>>24;
-	}
-
-	/*  If rmw is 0, then the store failed.  (This cache-line was written
-	    to by someone else.)  */
-	if (cpu->cd.mips.rmw == 0 || (MODE_int_t)cpu->cd.mips.rmw_addr != addr
-	    || cpu->cd.mips.rmw_len != sizeof(word)) {
-		reg(ic->arg[0]) = 0;
-		cpu->cd.mips.rmw = 0;
-		return;
-	}
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, word,
-	    sizeof(word), MEM_WRITE, CACHE_DATA)) {
-		/*  An exception occurred.  */
-		return;
-	}
-
-	/*  We succeeded. Let's invalidate everybody else's store to this
-	    cache line:  */
-	for (i=0; i<cpu->machine->ncpus; i++) {
-		if (cpu->machine->cpus[i]->cd.mips.rmw) {
-			uint64_t yaddr = addr, xaddr = cpu->machine->cpus[i]->
-			    cd.mips.rmw_addr;
-			uint64_t mask = ~(cpu->machine->cpus[i]->
-			    cd.mips.cache_linesize[CACHE_DATA] - 1);
-			xaddr &= mask;
-			yaddr &= mask;
-			if (xaddr == yaddr)
-				cpu->machine->cpus[i]->cd.mips.rmw = 0;
-		}
-	}
-
-	reg(ic->arg[0]) = 1;
-	cpu->cd.mips.rmw = 0;
-}
-X(scd)
-{
-	MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
-	uint64_t r = reg(ic->arg[0]);
-	int low_pc, i;
-	uint8_t word[sizeof(uint64_t)];
-
-	/*  Synch. PC and store using slow memory_rw():  */
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-
-	if (addr & (sizeof(word)-1)) {
-		fatal("TODO: sc unaligned access: exception\n");
-		exit(1);
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		word[0]=r;     word[1]=r>>8; word[2]=r>>16; word[3]=r>>24;
-		word[4]=r>>32; word[5]=r>>40; word[6]=r>>48; word[7]=r>>56;
-	} else {
-		word[7]=r;     word[6]=r>>8; word[5]=r>>16; word[4]=r>>24;
-		word[3]=r>>32; word[2]=r>>40; word[1]=r>>48; word[0]=r>>56;
-	}
-
-	/*  If rmw is 0, then the store failed.  (This cache-line was written
-	    to by someone else.)  */
-	if (cpu->cd.mips.rmw == 0 || (MODE_int_t)cpu->cd.mips.rmw_addr != addr
-	    || cpu->cd.mips.rmw_len != sizeof(word)) {
-		reg(ic->arg[0]) = 0;
-		cpu->cd.mips.rmw = 0;
-		return;
-	}
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, word,
-	    sizeof(word), MEM_WRITE, CACHE_DATA)) {
-		/*  An exception occurred.  */
-		return;
-	}
-
-	/*  We succeeded. Let's invalidate everybody else's store to this
-	    cache line:  */
-	for (i=0; i<cpu->machine->ncpus; i++) {
-		if (cpu->machine->cpus[i]->cd.mips.rmw) {
-			uint64_t yaddr = addr, xaddr = cpu->machine->cpus[i]->
-			    cd.mips.rmw_addr;
-			uint64_t mask = ~(cpu->machine->cpus[i]->
-			    cd.mips.cache_linesize[CACHE_DATA] - 1);
-			xaddr &= mask;
-			yaddr &= mask;
-			if (xaddr == yaddr)
-				cpu->machine->cpus[i]->cd.mips.rmw = 0;
-		}
-	}
-
-	reg(ic->arg[0]) = 1;
-	cpu->cd.mips.rmw = 0;
-}
-
-
-/*
- *  lwc1, swc1:  Coprocessor 1 load/store (32-bit)
- *  ldc1, sdc1:  Coprocessor 1 load/store (64-bit)
- *
- *  arg[0] = ptr to coprocessor register
- *  arg[1] = ptr to rs (base pointer register)
- *  arg[2] = int32_t imm
- */
-X(lwc1)
-{
-	COPROC_AVAILABILITY_CHECK(1);
-
-#ifdef MODE32
-	mips32_loadstore
-#else
-	mips_loadstore
-#endif
-	    [ (cpu->byte_order == EMUL_LITTLE_ENDIAN? 0 : 16) + 2 * 2 + 1]
-	    (cpu, ic);
-}
-X(swc1)
-{
-	COPROC_AVAILABILITY_CHECK(1);
-
-#ifdef MODE32
-	mips32_loadstore
-#else
-	mips_loadstore
-#endif
-	    [ (cpu->byte_order == EMUL_LITTLE_ENDIAN? 0 : 16) + 8 + 2 * 2]
-	    (cpu, ic);
-}
-X(ldc1)
-{
-	int use_fp_pairs =
-	    !(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & STATUS_FR);
-	uint64_t fpr, *backup_ptr;
-
-	COPROC_AVAILABILITY_CHECK(1);
-
-	backup_ptr = (uint64_t *) ic->arg[0];
-	ic->arg[0] = (size_t) &fpr;
-
-#ifdef MODE32
-	mips32_loadstore
-#else
-	mips_loadstore
-#endif
-	    [ (cpu->byte_order == EMUL_LITTLE_ENDIAN? 0 : 16) + 3 * 2 + 1]
-	    (cpu, ic);
-
-	if (use_fp_pairs) {
-		backup_ptr[0] = (int64_t)(int32_t) fpr;
-		backup_ptr[1] = (int64_t)(int32_t) (fpr >> 32);
-	} else {
-		*backup_ptr = fpr;
-	}
-
-	ic->arg[0] = (size_t) backup_ptr;
-}
-X(sdc1)
-{
-	int use_fp_pairs =
-	    !(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & STATUS_FR);
-	uint64_t fpr, *backup_ptr;
-
-	COPROC_AVAILABILITY_CHECK(1);
-
-	backup_ptr = (uint64_t *) ic->arg[0];
-	ic->arg[0] = (size_t) &fpr;
-
-	if (use_fp_pairs) {
-		uint32_t lo = backup_ptr[0];
-		uint32_t hi = backup_ptr[1];
-		fpr = (((uint64_t)hi) << 32) | lo;
-	} else {
-		fpr = *backup_ptr;
-	}
-
-#ifdef MODE32
-	mips32_loadstore
-#else
-	mips_loadstore
-#endif
-	    [ (cpu->byte_order == EMUL_LITTLE_ENDIAN? 0 : 16) + 8 + 3 * 2]
-	    (cpu, ic);
-
-	ic->arg[0] = (size_t) backup_ptr;
-}
-
-
-/*
- *  Unaligned loads/stores:
- *
- *  arg[0] = ptr to rt
- *  arg[1] = ptr to rs
- *  arg[2] = int32_t imm
- */
-X(lwl) { mips_unaligned_loadstore(cpu, ic, 1, sizeof(uint32_t), 0); }
-X(lwr) { mips_unaligned_loadstore(cpu, ic, 0, sizeof(uint32_t), 0); }
-X(ldl) { mips_unaligned_loadstore(cpu, ic, 1, sizeof(uint64_t), 0); }
-X(ldr) { mips_unaligned_loadstore(cpu, ic, 0, sizeof(uint64_t), 0); }
-X(swl) { mips_unaligned_loadstore(cpu, ic, 1, sizeof(uint32_t), 1); }
-X(swr) { mips_unaligned_loadstore(cpu, ic, 0, sizeof(uint32_t), 1); }
-X(sdl) { mips_unaligned_loadstore(cpu, ic, 1, sizeof(uint64_t), 1); }
-X(sdr) { mips_unaligned_loadstore(cpu, ic, 0, sizeof(uint64_t), 1); }
-
-
-/*
- *  di, ei: R5900 interrupt enable/disable.
- *
- *  TODO: check the R5900_STATUS_EDI bit in the status register. If it is
- *  cleared, and we are not running in kernel mode, then both the EI and DI
- *  instructions should be treated as NOPs!
- */
-X(di_r5900)
-{
-	if (!cop0_availability_check(cpu, ic))
-		return;
-
-	cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~R5900_STATUS_EIE;
-}
-X(ei_r5900)
-{
-	if (!cop0_availability_check(cpu, ic))
-		return;
-
-	cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |= R5900_STATUS_EIE;
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  sw_loop:
- *
- *  s:	addiu	rX,rX,4			rX = arg[0] and arg[1]
- *	bne	rY,rX,s  (or rX,rY,s)	rt=arg[1], rs=arg[0]
- *	sw	rZ,-4(rX)		rt=arg[0], rs=arg[1]
- */
-X(sw_loop)
-{
-	MODE_uint_t rX = reg(ic->arg[0]), rZ = reg(ic[2].arg[0]);
-	uint64_t *rYp = (uint64_t *) ic[1].arg[0];
-	MODE_uint_t rY, bytes_to_write;
-	unsigned char *page;
-	int partial = 0;
-
-	page = cpu->cd.mips.host_store[rX >> 12];
-
-	/*  Fallback:  */
-	if (cpu->delay_slot || page == NULL || (rX & 3) != 0 || rZ != 0) {
-		instr(addiu)(cpu, ic);
-		return;
-	}
-
-	if (rYp == (uint64_t *) ic->arg[0])
-		rYp = (uint64_t *) ic[1].arg[1];
-
-	rY = reg(rYp);
-
-	bytes_to_write = rY - rX;
-	if ((rX & 0xfff) + bytes_to_write > 0x1000) {
-		bytes_to_write = 0x1000 - (rX & 0xfff);
-		partial = 1;
-	}
-
-	/*  printf("rX = %08x\n", (int)rX);
-	    printf("rY = %08x\n", (int)rY);
-	    printf("rZ = %08x\n", (int)rZ);
-	    printf("%i bytes\n", (int)bytes_to_write);  */
-
-	memset(page + (rX & 0xfff), 0, bytes_to_write);
-
-	reg(ic->arg[0]) = rX + bytes_to_write;
-
-	cpu->n_translated_instrs += bytes_to_write / 4 * 3 - 1;
-	cpu->cd.mips.next_ic = partial?
-	    (struct mips_instr_call *) &ic[0] :
-	    (struct mips_instr_call *) &ic[3];
-}
-
-
-/*  multi_{l,s}w_2, _3, etc.  */
-#include "tmp_mips_loadstore_multi.cc"
-
-
-/*
- *  multi_addu_3:
- */
-X(multi_addu_3)
-{
-	/*  Fallback:  */
-	if (cpu->delay_slot) {
-		instr(addu)(cpu, ic);
-		return;
-	}
-
-	reg(ic[0].arg[2]) = (int32_t)(reg(ic[0].arg[0]) + reg(ic[0].arg[1]));
-	reg(ic[1].arg[2]) = (int32_t)(reg(ic[1].arg[0]) + reg(ic[1].arg[1]));
-	reg(ic[2].arg[2]) = (int32_t)(reg(ic[2].arg[0]) + reg(ic[2].arg[1]));
-	cpu->n_translated_instrs += 2;
-	cpu->cd.mips.next_ic = ic + 3;
-}
-
-
-/*
- *  netbsd_r3k_picache_do_inv:
- *
- *  ic[0]	mtc0	rV,status
- *     1	nop
- *     2	nop
- *     3  s:	addiu	rX,rX,4
- *     4	bne	rY,rX,s
- *     5	sb	zr,-4(rX)
- *     6	nop
- *     7	nop
- *     8	mtc0	rT,status
- */
-X(netbsd_r3k_picache_do_inv)
-{
-	MODE_uint_t rx = reg(ic[3].arg[0]), ry = reg(ic[4].arg[1]);
-
-	/*  Fallback if the environment isn't exactly right:  */
-	if (!(reg(ic[0].arg[0]) & MIPS1_ISOL_CACHES) ||
-	    (rx & 3) || (ry & 3) || cpu->delay_slot) {
-		instr(mtc0)(cpu, ic);
-		return;
-        }
-
-	reg(ic[3].arg[0]) = ry;
-	cpu->n_translated_instrs += (ry - rx + 4) / 4 * 3 + 4;
-
-	/*  Run the last mtc0 instruction:  */
-	cpu->cd.mips.next_ic = ic + 8;
-}
-
-
-#ifdef MODE32
-/*
- *  netbsd_pmax_idle():
- *
- *  s:  lui     rX, hi
- *      lw      rY, lo(rX)
- *      nop
- *      beq     zr, rY, s
- *      nop
- */
-X(netbsd_pmax_idle)
-{
-	uint32_t addr, pageindex, i;
-	int32_t *page;
-
-	reg(ic[0].arg[0]) = (int32_t)ic[0].arg[1];
-
-	addr = reg(ic[0].arg[0]) + (int32_t)ic[1].arg[2];
-	pageindex = addr >> 12;
-	i = (addr & 0xfff) >> 2;
-	page = (int32_t *) cpu->cd.mips.host_load[pageindex];
-
-	/*  Fallback:  */
-	if (cpu->delay_slot || page == NULL || page[i] != 0)
-		return;
-
-	instr(idle)(cpu, ic);
-}
-
-
-/*
- *  linux_pmax_idle():
- *
- *  s:  lui     rX, hi
- *      lw      rX, lo(rX)
- *      nop
- *      bne     zr, rX, ...
- *      nop
- *      lw      rX, ofs(gp)
- *      nop
- *      beq     zr, rX, s
- *      nop
- */
-X(linux_pmax_idle)
-{
-	uint32_t addr, addr2, pageindex, pageindex2, i, i2;
-	int32_t *page, *page2;
-
-	reg(ic[0].arg[0]) = (int32_t)ic[0].arg[1];
-
-	addr = reg(ic[0].arg[0]) + (int32_t)ic[1].arg[2];
-	pageindex = addr >> 12;
-	i = (addr & 0xfff) >> 2;
-	page = (int32_t *) cpu->cd.mips.host_load[pageindex];
-
-	addr2 = reg(ic[5].arg[1]) + (int32_t)ic[5].arg[2];
-	pageindex2 = addr2 >> 12;
-	i2 = (addr2 & 0xfff) >> 2;
-	page2 = (int32_t *) cpu->cd.mips.host_load[pageindex2];
-
-	/*  Fallback:  */
-	if (cpu->delay_slot || page == NULL || page[i] != 0 || page2[i2] != 0)
-		return;
-
-	instr(idle)(cpu, ic);
-}
-
-
-/*
- *  netbsd_strlen():
- *
- *	lb      rV,0(rX)
- *   s:	addiu   rX,rX,1
- *	bne	zr,rV,s
- *	nop
- */
-X(netbsd_strlen)
-{
-	MODE_uint_t rx = reg(ic[0].arg[1]);
-	MODE_int_t rv;
-	signed char *page;
-	uint32_t pageindex = rx >> 12;
-	int i;
-
-	page = (signed char *) cpu->cd.mips.host_load[pageindex];
-
-	/*  Fallback:  */
-	if (cpu->delay_slot || page == NULL) {
-		/*
-		 *  Normal lb:  NOTE: It doesn't matter whether [1] or
-		 *  [16+1] is called here, because endianness for 8-bit
-		 *  loads is irrelevant. :-)
-		 */
-		mips32_loadstore[1](cpu, ic);
-		return;
-	}
-
-	i = rx & 0xfff;
-
-	/*
-	 *  TODO: This loop can be optimized further for optimal
-	 *  performance on the host, e.g. by reading full words...
-	 */
-	do {
-		rv = page[i ++];
-	} while (i < 0x1000 && rv != 0);
-
-	cpu->n_translated_instrs += (i - (rx & 0xfff)) * 4 - 1;
-
-	reg(ic[0].arg[1]) = (rx & ~0xfff) + i;
-	reg(ic[2].arg[0]) = rv;
-
-	/*  Done with the loop? Or continue on the next rx page?  */
-	if (rv == 0)
-		cpu->cd.mips.next_ic = ic + 4;
-	else
-		cpu->cd.mips.next_ic = ic;
-}
-#endif
-
-
-/*
- *  addiu_bne_samepage_addiu:
- */
-X(addiu_bne_samepage_addiu)
-{
-	MODE_uint_t rs, rt;
-
-	if (cpu->delay_slot) {
-		instr(addiu)(cpu, ic);
-		return;
-	}
-
-	cpu->n_translated_instrs += 2;
-	reg(ic[0].arg[1]) = (int32_t)
-	    ((int32_t)reg(ic[0].arg[0]) + (int32_t)ic[0].arg[2]);
-	rs = reg(ic[1].arg[0]);
-	rt = reg(ic[1].arg[1]);
-	reg(ic[2].arg[1]) = (int32_t)
-	    ((int32_t)reg(ic[2].arg[0]) + (int32_t)ic[2].arg[2]);
-	if (rs != rt)
-		cpu->cd.mips.next_ic = (struct mips_instr_call *) ic[1].arg[2];
-	else
-		cpu->cd.mips.next_ic = ic + 3;
-}
-
-
-/*
- *  xor_andi_sll:
- */
-X(xor_andi_sll)
-{
-	/*  Fallback:  */
-	if (cpu->delay_slot) {
-		instr(xor)(cpu, ic);
-		return;
-	}
-
-	reg(ic[0].arg[2]) = reg(ic[0].arg[0]) ^ reg(ic[0].arg[1]);
-	reg(ic[1].arg[1]) = reg(ic[1].arg[0]) & (uint32_t)ic[1].arg[2];
-	reg(ic[2].arg[2]) = (int32_t)(reg(ic[2].arg[0])<<(int32_t)ic[2].arg[1]);
-
-	cpu->n_translated_instrs += 2;
-	cpu->cd.mips.next_ic = ic + 3;
-}
-
-
-/*
- *  andi_sll:
- */
-X(andi_sll)
-{
-	/*  Fallback:  */
-	if (cpu->delay_slot) {
-		instr(andi)(cpu, ic);
-		return;
-	}
-
-	reg(ic[0].arg[1]) = reg(ic[0].arg[0]) & (uint32_t)ic[0].arg[2];
-	reg(ic[1].arg[2]) = (int32_t)(reg(ic[1].arg[0])<<(int32_t)ic[1].arg[1]);
-
-	cpu->n_translated_instrs ++;
-	cpu->cd.mips.next_ic = ic + 2;
-}
-
-
-/*
- *  lui_ori:
- */
-X(lui_ori)
-{
-	/*  Fallback:  */
-	if (cpu->delay_slot) {
-		instr(set)(cpu, ic);
-		return;
-	}
-
-	reg(ic[0].arg[0]) = (int32_t)ic[0].arg[1];
-	reg(ic[1].arg[1]) = reg(ic[1].arg[0]) | (uint32_t)ic[1].arg[2];
-
-	cpu->n_translated_instrs ++;
-	cpu->cd.mips.next_ic = ic + 2;
-}
-
-
-/*
- *  lui_addiu:
- */
-X(lui_addiu)
-{
-	/*  Fallback:  */
-	if (cpu->delay_slot) {
-		instr(set)(cpu, ic);
-		return;
-	}
-
-	reg(ic[0].arg[0]) = (int32_t)ic[0].arg[1];
-	reg(ic[1].arg[1]) = (int32_t)
-	    ((int32_t)reg(ic[1].arg[0]) + (int32_t)ic[1].arg[2]);
-
-	cpu->n_translated_instrs ++;
-	cpu->cd.mips.next_ic = ic + 2;
-}
-
-
-/*
- *  b_samepage_addiu:
- *
- *  Combination of branch within the same page, followed by addiu.
- */
-X(b_samepage_addiu)
-{
-	reg(ic[1].arg[1]) = (int32_t)
-	    ( (int32_t)reg(ic[1].arg[0]) + (int32_t)ic[1].arg[2] );
-	cpu->n_translated_instrs ++;
-	cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
-}
-
-
-/*
- *  b_samepage_daddiu:
- *
- *  Combination of branch within the same page, followed by daddiu.
- */
-X(b_samepage_daddiu)
-{
-	*(uint64_t *)ic[1].arg[1] = *(uint64_t *)ic[1].arg[0] +
-	    (int32_t)ic[1].arg[2];
-	cpu->n_translated_instrs ++;
-	cpu->cd.mips.next_ic = (struct mips_instr_call *) ic->arg[2];
-}
-
-
-/*****************************************************************************/
-
-
-X(end_of_page)
-{
-	/*  Update the PC:  (offset 0, but on the next page)  */
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) <<
-	    MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (MIPS_IC_ENTRIES_PER_PAGE << MIPS_INSTR_ALIGNMENT_SHIFT);
-
-	/*  end_of_page doesn't count as an executed instruction:  */
-	cpu->n_translated_instrs --;
-
-	/*
-	 *  Find the new physpage and update translation pointers.
-	 *
-	 *  Note: This may cause an exception, if e.g. the new page is
-	 *  not accessible.
-	 */
-	quick_pc_to_pointers(cpu);
-
-	/*  Simple jump to the next page (if we are lucky):  */
-	if (cpu->delay_slot == NOT_DELAYED)
-		return;
-
-	/*
-	 *  If we were in a delay slot, and we got an exception while doing
-	 *  quick_pc_to_pointers, then return. The function which called
-	 *  end_of_page should handle this case.
-	 */
-	if (cpu->delay_slot == EXCEPTION_IN_DELAY_SLOT)
-		return;
-
-	/*
-	 *  Tricky situation; the delay slot is on the next virtual page.
-	 *  Calling to_be_translated will translate one instruction manually,
-	 *  execute it, and then discard it.
-	 */
-	/*  fatal("[ end_of_page: delay slot across page boundary! ]\n");  */
-
-	instr(to_be_translated)(cpu, cpu->cd.mips.next_ic);
-
-	/*  The instruction in the delay slot has now executed.  */
-	/*  fatal("[ end_of_page: back from executing the delay slot, %i ]\n",
-	    cpu->delay_slot);  */
-
-	/*  Find the physpage etc of the instruction in the delay slot
-	    (or, if there was an exception, the exception handler):  */
-	quick_pc_to_pointers(cpu);
-}
-
-
-X(end_of_page2)
-{
-	/*  Synchronize PC on the _second_ instruction on the next page:  */
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-
-	/*  This doesn't count as an executed instruction.  */
-	cpu->n_translated_instrs --;
-
-	quick_pc_to_pointers(cpu);
-
-	if (cpu->delay_slot == NOT_DELAYED)
-		return;
-
-	fatal("end_of_page2: fatal error, we're in a delay slot\n");
-	exit(1);
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  Combine:  Memory fill loop (addiu, bne, sw)
- *
- *  s:	addiu	rX,rX,4
- *	bne	rY,rX,s
- *	sw	rZ,-4(rX)
- */
-void COMBINE(sw_loop)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
-	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
-
-	/*  Only for 32-bit virtual address translation so far.  */
-	if (!cpu->is_32bit)
-		return;
-
-	if (n_back < 2)
-		return;
-
-	if (ic[-2].f == instr(addiu) && ic[-2].arg[0] == ic[-2].arg[1] &&
-	    (int32_t)ic[-2].arg[2] == 4 &&
-	    ic[-1].f == instr(bne_samepage) &&
-	    (ic[-1].arg[0] == ic[-2].arg[0] ||
-		ic[-1].arg[1] == ic[-2].arg[0]) &&
-	    ic[-1].arg[0] != ic[-1].arg[1] &&
-	    ic[-1].arg[2] == (size_t) &ic[-2] &&
-	    ic[0].arg[0] != ic[0].arg[1] &&
-	    ic[0].arg[1] == ic[-2].arg[0] && (int32_t)ic[0].arg[2] == -4) {
-		ic[-2].f = instr(sw_loop);
-	}
-}
-
-
-/*
- *  Combine:  Multiple SW in a row using the same base register
- *
- *	sw	r?,???(rX)
- *	sw	r?,???(rX)
- *	sw	r?,???(rX)
- *	...
- */
-void COMBINE(multi_sw)(struct cpu *cpu, struct mips_instr_call *ic,
-	int low_addr)
-{
-	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
-	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
-
-	if (n_back < 4)
-		return;
-
-	/*  Convert a multi_sw_4 to a multi_sw_5:  */
-	if ((ic[-4].f == instr(multi_sw_4_be) ||
-	    ic[-4].f == instr(multi_sw_4_le)) &&
-	    ic[-4].arg[1] == ic[0].arg[1]) {
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			ic[-4].f = instr(multi_sw_5_le);
-		else
-			ic[-4].f = instr(multi_sw_5_be);
-	}
-
-	/*  Convert a multi_sw_3 to a multi_sw_4:  */
-	if ((ic[-3].f == instr(multi_sw_3_be) ||
-	    ic[-3].f == instr(multi_sw_3_le)) &&
-	    ic[-3].arg[1] == ic[0].arg[1]) {
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			ic[-3].f = instr(multi_sw_4_le);
-		else
-			ic[-3].f = instr(multi_sw_4_be);
-	}
-
-	/*  Convert a multi_sw_2 to a multi_sw_3:  */
-	if ((ic[-2].f == instr(multi_sw_2_be) ||
-	    ic[-2].f == instr(multi_sw_2_le)) &&
-	    ic[-2].arg[1] == ic[0].arg[1]) {
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			ic[-2].f = instr(multi_sw_3_le);
-		else
-			ic[-2].f = instr(multi_sw_3_be);
-	}
-
-	if (ic[-1].f == ic[0].f && ic[-1].arg[1] == ic[0].arg[1]) {
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			ic[-1].f = instr(multi_sw_2_le);
-		else
-			ic[-1].f = instr(multi_sw_2_be);
-	}
-}
-
-
-/*
- *  Combine:  Multiple LW in a row using the same base register
- *
- *	lw	r?,???(rX)
- *	lw	r?,???(rX)
- *	lw	r?,???(rX)
- *	...
- */
-void COMBINE(multi_lw)(struct cpu *cpu, struct mips_instr_call *ic,
-	int low_addr)
-{
-	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
-	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
-
-	if (n_back < 4)
-		return;
-
-	/*  Convert a multi_lw_4 to a multi_lw_5:  */
-	if ((ic[-4].f == instr(multi_lw_4_be) ||
-	    ic[-4].f == instr(multi_lw_4_le)) &&
-	    ic[-4].arg[1] == ic[0].arg[1] &&
-	    ic[-1].arg[0] != ic[0].arg[1]) {
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			ic[-4].f = instr(multi_lw_5_le);
-		else
-			ic[-4].f = instr(multi_lw_5_be);
-	}
-
-	/*  Convert a multi_lw_3 to a multi_lw_4:  */
-	if ((ic[-3].f == instr(multi_lw_3_be) ||
-	    ic[-3].f == instr(multi_lw_3_le)) &&
-	    ic[-3].arg[1] == ic[0].arg[1] &&
-	    ic[-1].arg[0] != ic[0].arg[1]) {
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			ic[-3].f = instr(multi_lw_4_le);
-		else
-			ic[-3].f = instr(multi_lw_4_be);
-	}
-
-	/*  Convert a multi_lw_2 to a multi_lw_3:  */
-	if ((ic[-2].f == instr(multi_lw_2_be) ||
-	    ic[-2].f == instr(multi_lw_2_le)) &&
-	    ic[-2].arg[1] == ic[0].arg[1] &&
-	    ic[-1].arg[0] != ic[0].arg[1]) {
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			ic[-2].f = instr(multi_lw_3_le);
-		else
-			ic[-2].f = instr(multi_lw_3_be);
-	}
-
-	/*  Note: Loads to the base register are not allowed in slot -1.  */
-	if (ic[-1].f == ic[0].f &&
-	    ic[-1].arg[1] == ic[0].arg[1] &&
-	    ic[-1].arg[0] != ic[0].arg[1]) {
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			ic[-1].f = instr(multi_lw_2_le);
-		else
-			ic[-1].f = instr(multi_lw_2_be);
-	}
-}
-
-
-/*
- *  Combine:  NetBSD/pmax 3.0 R2000/R3000 physical cache invalidation loop
- *
- *  Instruction cache loop:
- *
- *  ic[-8]	mtc0	rV,status
- *     -7	nop
- *     -6	nop
- *     -5  s:	addiu	rX,rX,4
- *     -4	bne	rY,rX,s
- *     -3	sb	zr,-4(rX)
- *     -2	nop
- *     -1	nop
- *      0	mtc0	rT,status
- */
-void COMBINE(netbsd_r3k_cache_inv)(struct cpu *cpu,
-	struct mips_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
-	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
-
-	if (n_back < 8)
-		return;
-
-	if (ic[-8].f == instr(mtc0) && ic[-8].arg[1] == COP0_STATUS &&
-	    ic[-7].f == instr(nop) && ic[-6].f == instr(nop) &&
-	    ic[-5].f == instr(addiu) && ic[-5].arg[0] == ic[-5].arg[1] &&
-	    (int32_t)ic[-5].arg[2] == 4 && ic[-4].f == instr(bne_samepage) &&
-	    ic[-4].arg[0] == ic[-5].arg[0] && ic[-4].arg[0] != ic[-4].arg[1] &&
-	    ic[-4].arg[2] == (size_t) &ic[-5] &&
-	    ic[-3].arg[1] == ic[-5].arg[0] &&
-	    ic[-2].f == instr(nop) && ic[-1].f == instr(nop)) {
-		ic[-8].f = instr(netbsd_r3k_picache_do_inv);
-	}
-}
-
-
-/*
- *  Combine: something ending with a nop.
- *
- *	NetBSD's strlen core.
- *	[Conditional] branch, followed by nop.
- *	NetBSD/pmax' idle loop (and possibly others as well).
- *	Linux/pmax' idle loop.
- */
-void COMBINE(nop)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
-	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
-
-	if (n_back < 8)
-		return;
-
-#ifdef MODE32
-	if (ic[-8].f == instr(set) &&
-	    ic[-7].f == mips32_loadstore[4 + 1] &&
-	    ic[-7].arg[0] == ic[-1].arg[0] &&
-	    ic[-7].arg[0] == ic[-3].arg[0] &&
-	    ic[-7].arg[0] == ic[-5].arg[0] &&
-	    ic[-7].arg[0] == ic[-7].arg[1] &&
-	    ic[-7].arg[0] == ic[-8].arg[0] &&
-	    ic[-6].f == instr(nop) &&
-	    ic[-5].arg[1] == (size_t) &cpu->cd.mips.gpr[MIPS_GPR_ZERO] &&
-	    ic[-5].f == instr(bne_samepage_nop) &&
-	    ic[-4].f == instr(nop) &&
-	    ic[-3].f == mips32_loadstore[4 + 1] &&
-	    ic[-2].f == instr(nop) &&
-	    ic[-1].arg[1] == (size_t) &cpu->cd.mips.gpr[MIPS_GPR_ZERO] &&
-	    ic[-1].arg[2] == (size_t) &ic[-8] &&
-	    ic[-1].f == instr(beq_samepage)) {
-		ic[-8].f = instr(linux_pmax_idle);
-		return;
-	}
-
-	if (ic[-4].f == instr(set) &&
-	    ic[-3].f == mips32_loadstore[4 + 1] &&
-	    ic[-3].arg[0] == ic[-1].arg[0] &&
-	    ic[-3].arg[1] == ic[-4].arg[0] &&
-	    ic[-2].f == instr(nop) &&
-	    ic[-1].arg[1] == (size_t) &cpu->cd.mips.gpr[MIPS_GPR_ZERO] &&
-	    ic[-1].arg[2] == (size_t) &ic[-4] &&
-	    ic[-1].f == instr(beq_samepage)) {
-		ic[-4].f = instr(netbsd_pmax_idle);
-		return;
-	}
-
-	if ((ic[-3].f == mips32_loadstore[1] ||
-	    ic[-3].f == mips32_loadstore[16 + 1]) &&
-	    ic[-3].arg[2] == 0 &&
-	    ic[-3].arg[0] == ic[-1].arg[0] && ic[-3].arg[1] == ic[-2].arg[0] &&
-	    ic[-2].arg[0] == ic[-2].arg[1] && ic[-2].arg[2] == 1 &&
-	    ic[-2].f == instr(addiu) && ic[-1].arg[2] == (size_t) &ic[-3] &&
-	    ic[-1].arg[1] == (size_t) &cpu->cd.mips.gpr[MIPS_GPR_ZERO] &&
-	    ic[-1].f == instr(bne_samepage)) {
-		ic[-3].f = instr(netbsd_strlen);
-		return;
-	}
-#endif
-
-	if (ic[-1].f == instr(bne_samepage)) {
-		ic[-1].f = instr(bne_samepage_nop);
-		return;
-	}
-
-	if (ic[-1].f == instr(beq_samepage)) {
-		ic[-1].f = instr(beq_samepage_nop);
-		return;
-	}
-
-	/*  TODO: other branches that are followed by nop should be here  */
-}
-
-
-/*
- *  Combine:
- *
- *	xor + andi + sll
- *	andi + sll
- */
-void COMBINE(sll)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
-	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
-
-	if (n_back < 2)
-		return;
-
-	if (ic[-2].f == instr(xor) && ic[-1].f == instr(andi)) {
-		ic[-2].f = instr(xor_andi_sll);
-		return;
-	}
-
-	if (ic[-1].f == instr(andi)) {
-		ic[-1].f = instr(andi_sll);
-		return;
-	}
-}
-
-
-/*
- *  lui + ori
- */
-void COMBINE(ori)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
-	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
-
-	if (n_back < 1)
-		return;
-
-	if (ic[-1].f == instr(set)) {
-		ic[-1].f = instr(lui_ori);
-		return;
-	}
-}
-
-
-/*
- *  addu + addu + addu
- */
-void COMBINE(addu)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
-	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
-
-	if (n_back < 4)
-		return;
-
-	/*  Avoid "overlapping" instruction combinations:  */
-	if (ic[-4].f == instr(multi_addu_3) ||
-	    ic[-3].f == instr(multi_addu_3))
-		return;
-
-	if (ic[-2].f == instr(addu) && ic[-1].f == instr(addu)) {
-		ic[-2].f = instr(multi_addu_3);
-		return;
-	}
-}
-
-
-/*
- *  Combine:
- *
- *	[Conditional] branch, followed by addiu.
- */
-void COMBINE(addiu)(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
-	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
-
-	if (n_back < 2)
-		return;
-
-	if (ic[-2].f == instr(addiu) &&
-	    ic[-1].f == instr(bne_samepage)) {
-		ic[-2].f = instr(addiu_bne_samepage_addiu);
-		return;
-	}
-
-	if (ic[-1].f == instr(set)) {
-		ic[-1].f = instr(lui_addiu);
-		return;
-	}
-
-	if (ic[-1].f == instr(b_samepage)) {
-		ic[-1].f = instr(b_samepage_addiu);
-		return;
-	}
-
-	if (ic[-1].f == instr(beq_samepage)) {
-		ic[-1].f = instr(beq_samepage_addiu);
-		return;
-	}
-
-	if (ic[-1].f == instr(bne_samepage)) {
-		ic[-1].f = instr(bne_samepage_addiu);
-		return;
-	}
-
-	if (ic[-1].f == instr(jr_ra)) {
-		ic[-1].f = instr(jr_ra_addiu);
-		return;
-	}
-
-	/*  TODO: other branches that are followed by addiu should be here  */
-}
-
-
-/*
- *  Combine: [Conditional] branch, followed by daddiu.
- */
-void COMBINE(b_daddiu)(struct cpu *cpu, struct mips_instr_call *ic,
-	int low_addr)
-{
-	int n_back = (low_addr >> MIPS_INSTR_ALIGNMENT_SHIFT)
-	    & (MIPS_IC_ENTRIES_PER_PAGE - 1);
-
-	if (n_back < 1)
-		return;
-
-	if (ic[-1].f == instr(b_samepage)) {
-		ic[-1].f = instr(b_samepage_daddiu);
-	}
-
-	/*  TODO: other branches that are followed by daddiu should be here  */
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  mips_instr_to_be_translated():
- *
- *  Translate an instruction word into a mips_instr_call. ic is filled in with
- *  valid data for the translated instruction, or a "nothing" instruction if
- *  there was a translation failure. The newly translated instruction is then
- *  executed.
- */
-X(to_be_translated)
-{
-	uint64_t addr, low_pc;
-	uint32_t iword, imm;
-	unsigned char *page;
-	unsigned char ib[4];
-	int main_opcode, rt, rs, rd, sa, s6, x64 = 0, s10;
-	int in_crosspage_delayslot = 0;
-	void (*samepage_function)(struct cpu *, struct mips_instr_call *);
-	int store, signedness, size;
-
-	/*  Figure out the (virtual) address of the instruction:  */
-	low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-
-	/*  Special case for branch with delayslot on the next page:  */
-	if (cpu->delay_slot == TO_BE_DELAYED && low_pc == 0) {
-		/*  fatal("[ delay-slot translation across page "
-		    "boundary ]\n");  */
-		in_crosspage_delayslot = 1;
-	}
-
-	addr = cpu->pc & ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	addr += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc = (MODE_int_t)addr;
-	addr &= ~((1 << MIPS_INSTR_ALIGNMENT_SHIFT) - 1);
-
-	/*  Read the instruction word from memory:  */
-#ifdef MODE32
-	page = cpu->cd.mips.host_load[(uint32_t)addr >> 12];
-#else
-	{
-		const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
-		const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
-		const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
-		uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
-		uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
-		uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
-		    DYNTRANS_L3N)) & mask3;
-		struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.mips.l1_64[x1];
-		struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
-		page = l3->host_load[x3];
-	}
-#endif
-
-	if (page != NULL) {
-		/*  fatal("TRANSLATION HIT!\n");  */
-		memcpy(ib, page + (addr & 0xffc), sizeof(ib));
-	} else {
-		/*  fatal("TRANSLATION MISS!\n");  */
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
-		    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
-			fatal("to_be_translated(): read failed: TODO\n");
-			goto bad;
-		}
-	}
-
-	{
-		uint32_t *p = (uint32_t *) ib;
-		iword = *p;
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		iword = LE32_TO_HOST(iword);
-	else
-		iword = BE32_TO_HOST(iword);
-
-
-#define DYNTRANS_TO_BE_TRANSLATED_HEAD
-#include "cpu_dyntrans.cc"
-#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD
-
-
-	/*
-	 *  Translate the instruction:
- 	 *
-	 *  NOTE: _NEVER_ allow writes to the zero register; all instructions
-	 *  that use the zero register as their destination should be treated
-	 *  as NOPs, except those that access memory (they should use the
-	 *  scratch register instead).
-	 */
-
-	main_opcode = iword >> 26;
-	rs = (iword >> 21) & 31;
-	rt = (iword >> 16) & 31;
-	rd = (iword >> 11) & 31;
-	sa = (iword >>  6) & 31;
-	imm = (int16_t)iword;
-	s6 = iword & 63;
-	s10 = (rs << 5) | sa;
-
-	switch (main_opcode) {
-
-	case HI6_SPECIAL:
-		switch (s6) {
-
-		case SPECIAL_SLL:
-		case SPECIAL_SLLV:
-		case SPECIAL_SRL:
-		case SPECIAL_SRLV:
-		case SPECIAL_SRA:
-		case SPECIAL_SRAV:
-		case SPECIAL_DSRL:
-		case SPECIAL_DSRLV:
-		case SPECIAL_DSRL32:
-		case SPECIAL_DSLL:
-		case SPECIAL_DSLLV:
-		case SPECIAL_DSLL32:
-		case SPECIAL_DSRA:
-		case SPECIAL_DSRAV:
-		case SPECIAL_DSRA32:
-			switch (s6) {
-			case SPECIAL_SLL:  ic->f = instr(sll); break;
-			case SPECIAL_SLLV: ic->f = instr(sllv); sa = -1; break;
-			case SPECIAL_SRL:  ic->f = instr(srl); break;
-			case SPECIAL_SRLV: ic->f = instr(srlv); sa = -1; break;
-			case SPECIAL_SRA:  ic->f = instr(sra); break;
-			case SPECIAL_SRAV: ic->f = instr(srav); sa = -1; break;
-			case SPECIAL_DSRL: ic->f = instr(dsrl); x64=1; break;
-			case SPECIAL_DSRLV:ic->f = instr(dsrlv);
-					   x64 = 1; sa = -1; break;
-			case SPECIAL_DSRL32:ic->f= instr(dsrl); x64=1;
-					   sa += 32; break;
-			case SPECIAL_DSLL: ic->f = instr(dsll); x64=1; break;
-			case SPECIAL_DSLLV:ic->f = instr(dsllv);
-					   x64 = 1; sa = -1; break;
-			case SPECIAL_DSLL32:ic->f= instr(dsll); x64=1;
-					   sa += 32; break;
-			case SPECIAL_DSRA: ic->f = instr(dsra); x64=1; break;
-			case SPECIAL_DSRAV:ic->f = instr(dsrav);
-					   x64 = 1; sa = -1; break;
-			case SPECIAL_DSRA32:ic->f = instr(dsra); x64=1;
-					   sa += 32; break;
-			}
-
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-			if (sa >= 0)
-				ic->arg[1] = sa;
-			else
-				ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
-			ic->arg[2] = (size_t)&cpu->cd.mips.gpr[rd];
-
-			/*  Special checks for MIPS32/64 revision 2 opcodes,
-			    such as rotation instructions:  */
-			if (sa >= 0 && rs != 0x00) {
-				if (cpu->cd.mips.cpu_type.isa_level < 32 ||
-				    cpu->cd.mips.cpu_type.isa_revision < 2) {
-					static int warning_rotate = 0;
-					if (!warning_rotate &&
-					    !cpu->translation_readahead) {
-						fatal("[ WARNING! MIPS32/64 "
-						    "revision 2 rotate opcode"
-						    " used, but the %s process"
-						    "or does not implement "
-						    "such instructions. Only "
-						    "printing this "
-						    "warning once. ]\n",
-						    cpu->cd.mips.cpu_type.name);
-						warning_rotate = 1;
-					}
-					ic->f = instr(reserved);
-					break;
-				}
-				switch (rs) {
-				case 0x01:
-					switch (s6) {
-					case SPECIAL_SRL:	/*  ror (aka. rotr?) */
-						ic->f = instr(ror);
-						break;
-					default:goto bad;
-					}
-					break;
-				default:goto bad;
-				}
-			}
-			if (sa < 0 && (s10 & 0x1f) != 0) {
-				int orig_sa = (iword >>  6) & 31;
-				switch (s6) {
-				case SPECIAL_SRLV:	/*  rorv (aka. rotrv?) */
-					if (orig_sa == 0x01) {
-						ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
-						ic->f = instr(rorv);
-					}
-					break;
-				default:goto bad;
-				}
-				break;
-			}
-
-			if (rd == MIPS_GPR_ZERO)
-				ic->f = instr(nop);
-			if (ic->f == instr(sll))
-				cpu->cd.mips.combination_check = COMBINE(sll);
-			if (ic->f == instr(nop))
-				cpu->cd.mips.combination_check = COMBINE(nop);
-			break;
-
-		case SPECIAL_ADD:
-		case SPECIAL_ADDU:
-		case SPECIAL_SUB:
-		case SPECIAL_SUBU:
-		case SPECIAL_DADD:
-		case SPECIAL_DADDU:
-		case SPECIAL_DSUB:
-		case SPECIAL_DSUBU:
-		case SPECIAL_SLT:
-		case SPECIAL_SLTU:
-		case SPECIAL_AND:
-		case SPECIAL_OR:
-		case SPECIAL_XOR:
-		case SPECIAL_NOR:
-		case SPECIAL_MOVN:
-		case SPECIAL_MOVZ:
-		case SPECIAL_MFHI:
-		case SPECIAL_MFLO:
-		case SPECIAL_MTHI:
-		case SPECIAL_MTLO:
-		case SPECIAL_DIV:
-		case SPECIAL_DIVU:
-		case SPECIAL_DDIV:
-		case SPECIAL_DDIVU:
-		case SPECIAL_MULT:
-		case SPECIAL_MULTU:
-		case SPECIAL_DMULT:
-		case SPECIAL_DMULTU:
-		case SPECIAL_TGE:
-		case SPECIAL_TGEU:
-		case SPECIAL_TLT:
-		case SPECIAL_TLTU:
-		case SPECIAL_TEQ:
-		case SPECIAL_TNE:
-			switch (s6) {
-			case SPECIAL_ADD:   ic->f = instr(add); break;
-			case SPECIAL_ADDU:  ic->f = instr(addu); break;
-			case SPECIAL_SUB:   ic->f = instr(sub); break;
-			case SPECIAL_SUBU:  ic->f = instr(subu); break;
-			case SPECIAL_DADD:  ic->f = instr(dadd); x64=1; break;
-			case SPECIAL_DADDU: ic->f = instr(daddu); x64=1; break;
-			case SPECIAL_DSUB:  ic->f = instr(dsub); x64=1; break;
-			case SPECIAL_DSUBU: ic->f = instr(dsubu); x64=1; break;
-			case SPECIAL_SLT:   ic->f = instr(slt); break;
-			case SPECIAL_SLTU:  ic->f = instr(sltu); break;
-			case SPECIAL_AND:   ic->f = instr(and); break;
-			case SPECIAL_OR:    ic->f = instr(or); break;
-			case SPECIAL_XOR:   ic->f = instr(xor); break;
-			case SPECIAL_NOR:   ic->f = instr(nor); break;
-			case SPECIAL_MFHI:  ic->f = instr(mov); break;
-			case SPECIAL_MFLO:  ic->f = instr(mov); break;
-			case SPECIAL_MTHI:  ic->f = instr(mov); break;
-			case SPECIAL_MTLO:  ic->f = instr(mov); break;
-			case SPECIAL_DIV:   ic->f = instr(div); break;
-			case SPECIAL_DIVU:  ic->f = instr(divu); break;
-			case SPECIAL_DDIV:  ic->f = instr(ddiv); x64=1; break;
-			case SPECIAL_DDIVU: ic->f = instr(ddivu); x64=1; break;
-			case SPECIAL_MULT : ic->f = instr(mult); break;
-			case SPECIAL_MULTU: ic->f = instr(multu); break;
-			case SPECIAL_DMULT: ic->f = instr(dmult); x64=1; break;
-			case SPECIAL_DMULTU:ic->f = instr(dmultu); x64=1; break;
-			case SPECIAL_TGE:   ic->f = instr(tge); break;
-			case SPECIAL_TGEU:  ic->f = instr(tgeu); break;
-			case SPECIAL_TLT:   ic->f = instr(tlt); break;
-			case SPECIAL_TLTU:  ic->f = instr(tltu); break;
-			case SPECIAL_TEQ:   ic->f = instr(teq); break;
-			case SPECIAL_TNE:   ic->f = instr(tne); break;
-			case SPECIAL_MOVN:  ic->f = instr(movn); break;
-			case SPECIAL_MOVZ:  ic->f = instr(movz); break;
-			}
-
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
-			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
-			ic->arg[2] = (size_t)&cpu->cd.mips.gpr[rd];
-
-			switch (s6) {
-			case SPECIAL_MFHI:
-				ic->arg[0] = (size_t)&cpu->cd.mips.hi;
-				break;
-			case SPECIAL_MFLO:
-				ic->arg[0] = (size_t)&cpu->cd.mips.lo;
-				break;
-			case SPECIAL_MTHI:
-				ic->arg[2] = (size_t)&cpu->cd.mips.hi;
-				break;
-			case SPECIAL_MTLO:
-				ic->arg[2] = (size_t)&cpu->cd.mips.lo;
-				break;
-			}
-			/*  Special cases for rd:  */
-			switch (s6) {
-			case SPECIAL_MTHI:
-			case SPECIAL_MTLO:
-			case SPECIAL_DIV:
-			case SPECIAL_DIVU:
-			case SPECIAL_DDIV:
-			case SPECIAL_DDIVU:
-			case SPECIAL_MULT:
-			case SPECIAL_MULTU:
-			case SPECIAL_DMULT:
-			case SPECIAL_DMULTU:
-				if (s6 == SPECIAL_MULT && rd != MIPS_GPR_ZERO) {
-					if (cpu->cd.mips.cpu_type.rev ==
-					    MIPS_R5900) {
-						ic->f = instr(mult_r5900);
-						break;
-					}
-					break;
-				}
-				if (s6 == SPECIAL_MULTU && rd!=MIPS_GPR_ZERO) {
-					if (cpu->cd.mips.cpu_type.rev ==
-					    MIPS_R5900) {
-						ic->f = instr(multu_r5900);
-						break;
-					}
-				}
-				if (rd != MIPS_GPR_ZERO) {
-					if (!cpu->translation_readahead)
-						fatal("TODO: rd NON-zero\n");
-					goto bad;
-				}
-				/*  These instructions don't use rd.  */
-				break;
-			case SPECIAL_TGE:
-			case SPECIAL_TGEU:
-			case SPECIAL_TLT:
-			case SPECIAL_TLTU:
-			case SPECIAL_TEQ:
-			case SPECIAL_TNE:
-				/*  In these instructions, rd is a 'code',
-				    only read by trap handling software.  */
-				break;
-			default:if (rd == MIPS_GPR_ZERO)
-					ic->f = instr(nop);
-			}
-
-			if (ic->f == instr(addu))
-				cpu->cd.mips.combination_check = COMBINE(addu);
-
-			break;
-
-		case SPECIAL_JR:
-		case SPECIAL_JALR:
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
-			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rd];
-			if (s6 == SPECIAL_JALR && rd == MIPS_GPR_ZERO)
-				s6 = SPECIAL_JR;
-			ic->arg[2] = (addr & 0xffc) + 8;
-			switch (s6) {
-			case SPECIAL_JR:
-				if (rs == MIPS_GPR_RA) {
-					if (cpu->machine->show_trace_tree)
-						ic->f = instr(jr_ra_trace);
-					else
-						ic->f = instr(jr_ra);
-				} else {
-					ic->f = instr(jr);
-				}
-				if (cpu->translation_readahead > 2)
-					cpu->translation_readahead = 2;
-				break;
-			case SPECIAL_JALR:
-				if (cpu->machine->show_trace_tree)
-					ic->f = instr(jalr_trace);
-				else
-					ic->f = instr(jalr);
-				break;
-			}
-			if (cpu->delay_slot) {
-				if (!cpu->translation_readahead)
-					fatal("TODO: branch in delay "
-					    "slot? (1)\n");
-				goto bad;
-			}
-			break;
-
-		case SPECIAL_SYSCALL:
-			if (((iword >> 6) & 0xfffff) == 0x30378) {
-				/*  "Magic trap" for PROM emulation:  */
-				ic->f = instr(promemul);
-			} else {
-				ic->f = instr(syscall);
-			}
-			break;
-
-		case SPECIAL_BREAK:
-			if (((iword >> 6) & 0xfffff) == 0x30378) {
-				/*  "Magic trap" for REBOOT:  */
-				ic->f = instr(reboot);
-			} else {
-				ic->f = instr(break);
-			}
-			break;
-
-		case SPECIAL_SYNC:
-			ic->f = instr(nop);
-			break;
-
-		default:goto bad;
-		}
-		break;
-
-	case HI6_BEQ:
-	case HI6_BNE:
-	case HI6_BEQL:
-	case HI6_BNEL:
-	case HI6_BLEZ:
-	case HI6_BLEZL:
-	case HI6_BGTZ:
-	case HI6_BGTZL:
-		samepage_function = NULL;  /*  get rid of a compiler warning  */
-		switch (main_opcode) {
-		case HI6_BEQ:
-			ic->f = instr(beq);
-			samepage_function = instr(beq_samepage);
-			/*  Special case: comparing a register with itself:  */
-			if (rs == rt) {
-				ic->f = instr(b);
-				samepage_function = instr(b_samepage);
-			}
-			break;
-		case HI6_BNE:
-			ic->f = instr(bne);
-			samepage_function = instr(bne_samepage);
-			break;
-		case HI6_BEQL:
-			ic->f = instr(beql);
-			samepage_function = instr(beql_samepage);
-			/*  Special case: comparing a register with itself:  */
-			if (rs == rt) {
-				ic->f = instr(b);
-				samepage_function = instr(b_samepage);
-			}
-			break;
-		case HI6_BNEL:
-			ic->f = instr(bnel);
-			samepage_function = instr(bnel_samepage);
-			break;
-		case HI6_BLEZ:
-			ic->f = instr(blez);
-			samepage_function = instr(blez_samepage);
-			break;
-		case HI6_BLEZL:
-			ic->f = instr(blezl);
-			samepage_function = instr(blezl_samepage);
-			break;
-		case HI6_BGTZ:
-			ic->f = instr(bgtz);
-			samepage_function = instr(bgtz_samepage);
-			break;
-		case HI6_BGTZL:
-			ic->f = instr(bgtzl);
-			samepage_function = instr(bgtzl_samepage);
-			break;
-		}
-		ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
-		ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
-		ic->arg[2] = (int32_t) ( (imm << MIPS_INSTR_ALIGNMENT_SHIFT)
-		    + (addr & 0xffc) + 4 );
-		/*  Is the offset from the start of the current page still
-		    within the same page? Then use the samepage_function:  */
-		if ((uint32_t)ic->arg[2] < ((MIPS_IC_ENTRIES_PER_PAGE - 1)
-		    << MIPS_INSTR_ALIGNMENT_SHIFT) && (addr & 0xffc) < 0xffc) {
-			ic->arg[2] = (size_t) (cpu->cd.mips.cur_ic_page +
-			    ((ic->arg[2] >> MIPS_INSTR_ALIGNMENT_SHIFT)
-			    & (MIPS_IC_ENTRIES_PER_PAGE - 1)));
-			ic->f = samepage_function;
-		}
-		if (cpu->delay_slot) {
-			if (!cpu->translation_readahead)
-				fatal("TODO: branch in delay slot? (2)\n");
-			goto bad;
-		}
-		break;
-
-	case HI6_ADDI:
-	case HI6_ADDIU:
-	case HI6_SLTI:
-	case HI6_SLTIU:
-	case HI6_DADDI:
-	case HI6_DADDIU:
-	case HI6_ANDI:
-	case HI6_ORI:
-	case HI6_XORI:
-		ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
-		ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
-		if (main_opcode == HI6_ADDI ||
-		    main_opcode == HI6_ADDIU ||
-		    main_opcode == HI6_SLTI ||
-		    main_opcode == HI6_SLTIU ||
-		    main_opcode == HI6_DADDI ||
-		    main_opcode == HI6_DADDIU)
-			ic->arg[2] = (int16_t)iword;
-		else
-			ic->arg[2] = (uint16_t)iword;
-
-		switch (main_opcode) {
-		case HI6_ADDI:    ic->f = instr(addi); break;
-		case HI6_ADDIU:   ic->f = instr(addiu); break;
-		case HI6_SLTI:    ic->f = instr(slti); break;
-		case HI6_SLTIU:   ic->f = instr(sltiu); break;
-		case HI6_DADDI:   ic->f = instr(daddi); x64 = 1; break;
-		case HI6_DADDIU:  ic->f = instr(daddiu); x64 = 1; break;
-		case HI6_ANDI:    ic->f = instr(andi); break;
-		case HI6_ORI:     ic->f = instr(ori); break;
-		case HI6_XORI:    ic->f = instr(xori); break;
-		}
-
-		if (ic->arg[2] == 0) {
-			if ((cpu->is_32bit && ic->f == instr(addiu)) ||
-			    (!cpu->is_32bit && ic->f == instr(daddiu))) {
-				ic->f = instr(mov);
-				ic->arg[2] = ic->arg[1];
-			}
-		}
-
-		if (rt == MIPS_GPR_ZERO)
-			ic->f = instr(nop);
-
-		if (ic->f == instr(ori))
-			cpu->cd.mips.combination_check = COMBINE(ori);
-		if (ic->f == instr(addiu))
-			cpu->cd.mips.combination_check = COMBINE(addiu);
-		if (ic->f == instr(daddiu))
-			cpu->cd.mips.combination_check = COMBINE(b_daddiu);
-		break;
-
-	case HI6_LUI:
-		ic->f = instr(set);
-		ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-		ic->arg[1] = (int32_t) (imm << 16);
-		/*  NOTE: Don't use arg[2] here. It can be used with
-		    instruction combinations, to do lui + addiu, etc.  */
-		if (rt == MIPS_GPR_ZERO)
-			ic->f = instr(nop);
-		break;
-
-	case HI6_J:
-	case HI6_JAL:
-		switch (main_opcode) {
-		case HI6_J:
-			ic->f = instr(j);
-			if (cpu->translation_readahead > 2)
-				cpu->translation_readahead = 2;
-			break;
-		case HI6_JAL:
-			if (cpu->machine->show_trace_tree)
-				ic->f = instr(jal_trace);
-			else
-				ic->f = instr(jal);
-			break;
-		}
-		ic->arg[0] = (iword & 0x03ffffff) << 2;
-		ic->arg[1] = (addr & 0xffc) + 8;
-		if (cpu->delay_slot) {
-			if (!cpu->translation_readahead)
-				fatal("TODO: branch in delay slot (=%i)? (3);"
-				    " addr=%016" PRIx64" iword=%08" PRIx32"\n",
-				    cpu->delay_slot, (uint64_t)addr, iword);
-			goto bad;
-		}
-		break;
-
-	case HI6_COP0:
-		/*  TODO: Is checking bit 25 enough, or perhaps all bits
-		    25..21 must be checked?  */
-		if ((iword >> 25) & 1) {
-			ic->arg[2] = addr & 0xffc;
-			switch (iword & 0xff) {
-			case COP0_TLBR:
-				ic->f = instr(tlbr);
-				break;
-			case COP0_TLBWI:
-			case COP0_TLBWR:
-				ic->f = instr(tlbw);
-				ic->arg[0] = (iword & 0xff) == COP0_TLBWR;
-				break;
-			case COP0_TLBP:
-				ic->f = instr(tlbp);
-				break;
-			case COP0_RFE:
-				ic->f = instr(rfe);
-				break;
-			case COP0_ERET:
-				ic->f = instr(eret);
-				break;
-			case COP0_DERET:
-				ic->f = instr(deret);
-				break;
-			case COP0_WAIT:
-				ic->f = instr(wait);
-				if (cpu->cd.mips.cpu_type.rev != MIPS_RM5200 &&
-				    cpu->cd.mips.cpu_type.isa_level < 32) {
-					static int warned = 0;
-					ic->f = instr(reserved);
-					if (!warned &&
-					    !cpu->translation_readahead) {
-						fatal("{ WARNING: Attempt to "
-						    "execute the WAIT instruct"
-					            "ion, but the emulated CPU "
-						    "is neither RM52xx, nor "
-						    "MIPS32/64! }\n");
-						warned = 1;
-					}
-				}
-				break;
-			case COP0_STANDBY:
-				/*  NOTE: Reusing the 'wait' instruction:  */
-				ic->f = instr(wait);
-				if (cpu->cd.mips.cpu_type.rev != MIPS_R4100) {
-					static int warned = 0;
-					ic->f = instr(reserved);
-					if (!warned &&
-					    !cpu->translation_readahead) {
-						fatal("{ WARNING: Attempt to "
-						    "execute a R41xx instruct"
-					            "ion, but the emulated CPU "
-						    "doesn't support it! }\n");
-						warned = 1;
-					}
-				}
-				break;
-			case COP0_HIBERNATE:
-				/*  TODO  */
-				goto bad;
-			case COP0_SUSPEND:
-				/*  Used by NetBSD on HPCmips (VR41xx) to
-				    halt the machine.  */
-				ic->f = instr(reboot);
-				break;
-			case COP0_EI:
-				if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
-					ic->f = instr(ei_r5900);
-				} else
-					goto bad;
-				break;
-			case COP0_DI:
-				if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
-					ic->f = instr(di_r5900);
-				} else
-					goto bad;
-				break;
-			default:if (!cpu->translation_readahead)
-					fatal("UNIMPLEMENTED cop0 (func "
-					    "0x%02x)\n", iword & 0xff);
-				goto bad;
-			}
-			break;
-		}
-
-		/*  rs contains the coprocessor opcode!  */
-		switch (rs) {
-		case COPz_CFCz:
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-			ic->arg[1] = rd + ((iword & 7) << 5);
-			ic->arg[2] = addr & 0xffc;
-			ic->f = instr(cfc0);
-			if (rt == MIPS_GPR_ZERO)
-				ic->f = instr(nop);
-			break;
-		case COPz_MFCz:
-		case COPz_DMFCz:
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-			ic->arg[1] = rd + ((iword & 7) << 5);
-			ic->arg[2] = addr & 0xffc;
-			ic->f = rs == COPz_MFCz? instr(mfc0) : instr(dmfc0);
-			if (rs == COPz_MFCz && (iword & 7) == 0 &&
-			    rd != COP0_COUNT)
-				ic->f = instr(mfc0_select0);
-			if (rs == COPz_DMFCz && (iword & 7) == 0 &&
-			    rd != COP0_COUNT)
-				ic->f = instr(dmfc0_select0);
-			if (rt == MIPS_GPR_ZERO)
-				ic->f = instr(nop);
-			break;
-		case COPz_MTCz:
-		case COPz_DMTCz:
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-			ic->arg[1] = rd + ((iword & 7) << 5);
-			ic->arg[2] = addr & 0xffc;
-			ic->f = rs == COPz_MTCz? instr(mtc0) : instr(dmtc0);
-
-			if (cpu->cd.mips.cpu_type.exc_model == EXC3K &&
-			    rs == COPz_MTCz && rd == COP0_STATUS)
-				cpu->cd.mips.combination_check =
-				    COMBINE(netbsd_r3k_cache_inv);
-
-			break;
-		case COPz_MFMCz:
-			if ((iword & 0xffdf) == 0x6000) {
-				/*  MIPS32/64 rev 2 "ei" or "di":   */
-				if (cpu->cd.mips.cpu_type.isa_level < 32 ||
-				    cpu->cd.mips.cpu_type.isa_revision < 2) {
-					static int warning_ei_di = 0;
-					if (!warning_ei_di &&
-					    !cpu->translation_readahead) {
-						fatal("[ WARNING! MIPS32/64 "
-						    "revision 2 di or ei opcode"
-						    " used, but the %s process"
-						    "or does not implement "
-						    "such instructions. Only "
-						    "printing this "
-						    "warning once. ]\n",
-						    cpu->cd.mips.cpu_type.name);
-						warning_ei_di = 1;
-					}
-					ic->f = instr(reserved);
-					break;
-				}
-				ic->f = instr(ei_or_di);
-				ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-				if (rt == MIPS_GPR_ZERO)
-					ic->arg[0] =
-					    (size_t)&cpu->cd.mips.scratch;
-				ic->arg[1] = iword & 0x20;
-			} else {
-				if (!cpu->translation_readahead)
-					fatal("Unimplemented COP0_MFMCz\n");
-				goto bad;
-			}
-			break;
-		case COPz_BCzc:
-			if (iword == 0x4100ffff) {
-				/*  R2020 DECstation write-loop thingy.  */
-				ic->f = instr(nop);
-			} else {
-				if (!cpu->translation_readahead)
-					fatal("Unimplemented COP0_BCzc\n");
-				goto bad;
-			}
-			break;
-		
-		default:if (!cpu->translation_readahead)
-				fatal("UNIMPLEMENTED cop0 (rs = %i)\n", rs);
-			goto bad;
-		}
-		break;
-
-	case HI6_COP1:
-		/*  Always cause a coprocessor unusable exception if
-		    there is no floating point coprocessor:  */
-		if (cpu->cd.mips.cpu_type.flags & NOFPU ||
-		    cpu->cd.mips.coproc[1] == NULL) {
-			ic->f = instr(cpu);
-			ic->arg[0] = 1;
-			break;
-		}
-
-		/*  Bits 25..21 are floating point main opcode:  */
-		switch (rs) {
-
-		case COPz_BCzc:
-			/*  Conditional branch:  */
-			/*  TODO: Reimplement this in a faster way.  */
-			ic->f = instr(cop1_bc);
-			ic->arg[0] = (iword >> 18) & 7;	/*  cc  */
-			ic->arg[1] = (iword >> 16) & 3;	/*  nd, tf bits  */
-			ic->arg[2] = (int32_t) ((imm <<
-			    MIPS_INSTR_ALIGNMENT_SHIFT) + (addr & 0xffc) + 4);
-			if (cpu->delay_slot) {
-				if (!cpu->translation_readahead)
-					fatal("TODO: branch in delay slot 4\n");
-				goto bad;
-			}
-			if (cpu->cd.mips.cpu_type.isa_level <= 3 &&
-			    ic->arg[0] != 0) {
-				if (!cpu->translation_readahead)
-					fatal("Attempt to execute a non-cc-0 "
-					    "BC* instruction on an isa level "
-					    "%i cpu. TODO: How should this be "
-					    "handled?\n",
-					    cpu->cd.mips.cpu_type.isa_level);
-				goto bad;
-			}
-
-			break;
-
-		case COPz_DMFCz:
-		case COPz_DMTCz:
-			x64 = 1;
-			/*  FALL-THROUGH  */
-		case COP1_FMT_S:
-		case COP1_FMT_D:
-		case COP1_FMT_W:
-		case COP1_FMT_L:
-		case COP1_FMT_PS:
-		case COPz_CFCz:
-		case COPz_CTCz:
-		case COPz_MFCz:
-		case COPz_MTCz:
-			/*  Fallback to slow pre-dyntrans code, for now.  */
-			/*  TODO: Fix/optimize/rewrite.  */
-			ic->f = instr(cop1_slow);
-			ic->arg[0] = (uint32_t)iword & ((1 << 26) - 1);
-			break;
-
-		default:if (!cpu->translation_readahead)
-			    fatal("COP1 floating point opcode = 0x%02x\n", rs);
-			goto bad;
-		}
-		break;
-
-	case HI6_COP2:
-		/*  Always cause a coprocessor unusable exception if
-		    there is no coprocessor 2:  */
-		if (cpu->cd.mips.coproc[2] == NULL) {
-			ic->f = instr(cpu);
-			ic->arg[0] = 2;
-			break;
-		}
-		if (!cpu->translation_readahead)
-			fatal("COP2 functionality not yet implemented\n");
-		goto bad;
-		break;
-
-	case HI6_COP3:
-		/*  Always cause a coprocessor unusable exception if
-		    there is no coprocessor 3:  */
-		if (cpu->cd.mips.coproc[3] == NULL) {
-			ic->f = instr(cpu);
-			ic->arg[0] = 3;
-			break;
-		}
-
-		if (iword == 0x4d00ffff) {
-			/*  R2020 writeback thing, used by e.g. NetBSD/pmax
-			    on MIPSMATE.  */
-			ic->f = instr(nop);
-		} else {
-			if (!cpu->translation_readahead)
-				fatal("COP3 iword=0x%08x\n", iword);
-			goto bad;
-		}
-		break;
-
-	case HI6_SPECIAL2:
-		if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
-			/*  R5900, TX79/C790, have MMI instead of SPECIAL2:  */
-			int mmi_subopcode = (iword >> 6) & 0x1f;
-
-			switch (s6) {
-
-			case MMI_MADD:
-				ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
-				ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
-				ic->arg[2] = (size_t)&cpu->cd.mips.gpr[rd];
-				if (rd == MIPS_GPR_ZERO)
-					ic->f = instr(madd);
-				else
-					ic->f = instr(madd_rd);
-				break;
-
-			case MMI_MADDU:
-				ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
-				ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
-				ic->arg[2] = (size_t)&cpu->cd.mips.gpr[rd];
-				if (rd == MIPS_GPR_ZERO)
-					ic->f = instr(maddu);
-				else
-					ic->f = instr(maddu_rd);
-				break;
-
-			case MMI_MMI0:
-				switch (mmi_subopcode) {
-
-				case MMI0_PEXTLW:
-					ic->arg[0] = rs;
-					ic->arg[1] = rt;
-					ic->arg[2] = rd;
-					if (rd == MIPS_GPR_ZERO)
-						ic->f = instr(nop);
-					else
-						ic->f = instr(pextlw);
-					break;
-
-				default:goto bad;
-				}
-				break;
-
-			case MMI_MMI3:
-				switch (mmi_subopcode) {
-
-				case MMI3_POR:
-					ic->arg[0] = rs;
-					ic->arg[1] = rt;
-					ic->arg[2] = rd;
-					if (rd == MIPS_GPR_ZERO)
-						ic->f = instr(nop);
-					else
-						ic->f = instr(por);
-					break;
-
-				default:goto bad;
-				}
-				break;
-
-			default:goto bad;
-			}
-			break;
-		}
-
-		/*  TODO: is this correct? Or are there other non-MIPS32/64
-		    MIPS processors that have support for SPECIAL2 opcodes?  */
-		if (cpu->cd.mips.cpu_type.isa_level < 32) {
-			ic->f = instr(reserved);
-			break;
-		}
-
-		/*  SPECIAL2:  */
-		switch (s6) {
-
-		case SPECIAL2_MADD:
-		case SPECIAL2_MADDU:
-		case SPECIAL2_MSUB:
-		case SPECIAL2_MSUBU:
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
-			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
-			switch (s6) {
-			case SPECIAL2_MADD: ic->f = instr(madd); break;
-			case SPECIAL2_MADDU:ic->f = instr(maddu); break;
-			case SPECIAL2_MSUB: ic->f = instr(msub); break;
-			case SPECIAL2_MSUBU:ic->f = instr(msubu); break;
-			}
-			break;
-
-		case SPECIAL2_MUL:
-			ic->f = instr(mul);
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
-			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rt];
-			ic->arg[2] = (size_t)&cpu->cd.mips.gpr[rd];
-			if (rd == MIPS_GPR_ZERO)
-				ic->f = instr(nop);
-			break;
-
-		case SPECIAL2_CLZ:
-		case SPECIAL2_CLO:
-		case SPECIAL2_DCLZ:
-		case SPECIAL2_DCLO:
-			switch (s6) {
-			case SPECIAL2_CLZ:  ic->f = instr(clz); break;
-			case SPECIAL2_CLO:  ic->f = instr(clo); break;
-			case SPECIAL2_DCLZ: ic->f = instr(dclz); break;
-			case SPECIAL2_DCLO: ic->f = instr(dclo); break;
-			}
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
-			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rd];
-			if (rd == MIPS_GPR_ZERO)
-				ic->f = instr(nop);
-			break;
-
-		default:goto bad;
-		}
-		break;
-
-	case HI6_REGIMM:
-		switch (rt) {
-		case REGIMM_BGEZ:
-		case REGIMM_BGEZL:
-		case REGIMM_BLTZ:
-		case REGIMM_BLTZL:
-		case REGIMM_BGEZAL:
-		case REGIMM_BGEZALL:
-		case REGIMM_BLTZAL:
-		case REGIMM_BLTZALL:
-			samepage_function = NULL;
-			switch (rt) {
-			case REGIMM_BGEZ:
-				ic->f = instr(bgez);
-				samepage_function = instr(bgez_samepage);
-				break;
-			case REGIMM_BGEZL:
-				ic->f = instr(bgezl);
-				samepage_function = instr(bgezl_samepage);
-				break;
-			case REGIMM_BLTZ:
-				ic->f = instr(bltz);
-				samepage_function = instr(bltz_samepage);
-				break;
-			case REGIMM_BLTZL:
-				ic->f = instr(bltzl);
-				samepage_function = instr(bltzl_samepage);
-				break;
-			case REGIMM_BGEZAL:
-				ic->f = instr(bgezal);
-				samepage_function = instr(bgezal_samepage);
-				break;
-			case REGIMM_BGEZALL:
-				ic->f = instr(bgezall);
-				samepage_function = instr(bgezall_samepage);
-				break;
-			case REGIMM_BLTZAL:
-				ic->f = instr(bltzal);
-				samepage_function = instr(bltzal_samepage);
-				break;
-			case REGIMM_BLTZALL:
-				ic->f = instr(bltzall);
-				samepage_function = instr(bltzall_samepage);
-				break;
-			}
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
-			ic->arg[2] = (imm << MIPS_INSTR_ALIGNMENT_SHIFT)
-			    + (addr & 0xffc) + 4;
-			/*  Is the offset from the start of the current page
-			    still within the same page? Then use the
-			    samepage_function:  */
-			if ((uint32_t)ic->arg[2] < ((MIPS_IC_ENTRIES_PER_PAGE-1)
-			    << MIPS_INSTR_ALIGNMENT_SHIFT) && (addr & 0xffc)
-			    < 0xffc) {
-				ic->arg[2] = (size_t) (cpu->cd.mips.cur_ic_page+
-				    ((ic->arg[2] >> MIPS_INSTR_ALIGNMENT_SHIFT)
-				    & (MIPS_IC_ENTRIES_PER_PAGE - 1)));
-				ic->f = samepage_function;
-			}
-			if (cpu->delay_slot) {
-				if (!cpu->translation_readahead)
-					fatal("TODO: branch in delay slot:5\n");
-				goto bad;
-			}
-			break;
-
-		case REGIMM_TGEI:
-		case REGIMM_TGEIU:
-		case REGIMM_TLTI:
-		case REGIMM_TLTIU:
-		case REGIMM_TEQI:
-		case REGIMM_TNEI:
-			switch (rt) {
-			case REGIMM_TGEI:	ic->f = instr(tgei); break;
-			case REGIMM_TGEIU:	ic->f = instr(tgeiu); break;
-			case REGIMM_TLTI:	ic->f = instr(tlti); break;
-			case REGIMM_TLTIU:	ic->f = instr(tltiu); break;
-			case REGIMM_TEQI:	ic->f = instr(teqi); break;
-			case REGIMM_TNEI:	ic->f = instr(tnei); break;
-			}
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
-			ic->arg[2] = (int64_t)(int16_t)imm;
-
-			if (cpu->cd.mips.cpu_type.isa_level < 32) {
-				static int warning = 0;
-				if (!warning && !cpu->translation_readahead) {
-					fatal("[ WARNING! Trap opcode used, but"
-					    " the %s processor does not implement "
-					    "such instructions. Only printing this "
-					    "warning once. ]\n",
-					    cpu->cd.mips.cpu_type.name);
-					warning = 1;
-				}
-				ic->f = instr(reserved);
-			}
-			break;
-
-		default:if (!cpu->translation_readahead)
-				fatal("UNIMPLEMENTED regimm rt=%i\n", rt);
-			goto bad;
-		}
-		break;
-
-	case HI6_LB:
-	case HI6_LBU:
-	case HI6_SB:
-	case HI6_LH:
-	case HI6_LHU:
-	case HI6_SH:
-	case HI6_LW:
-	case HI6_LWU:
-	case HI6_SW:
-	case HI6_LD:
-	case HI6_SD:
-		/*  TODO: LWU should probably also be x64=1?  */
-		size = 2; signedness = 0; store = 0;
-		switch (main_opcode) {
-		case HI6_LB:  size = 0; signedness = 1; break;
-		case HI6_LBU: size = 0; break;
-		case HI6_LH:  size = 1; signedness = 1; break;
-		case HI6_LHU: size = 1; break;
-		case HI6_LW:  signedness = 1; break;
-		case HI6_LWU: break;
-		case HI6_LD:  size = 3; x64 = 1; break;
-		case HI6_SB:  store = 1; size = 0; break;
-		case HI6_SH:  store = 1; size = 1; break;
-		case HI6_SW:  store = 1; break;
-		case HI6_SD:  store = 1; size = 3; x64 = 1; break;
-		}
-
-		ic->f =
-#ifdef MODE32
-		    mips32_loadstore
-#else
-		    mips_loadstore
-#endif
-		    [ (cpu->byte_order == EMUL_LITTLE_ENDIAN? 0 : 16)
-		    + store * 8 + size * 2 + signedness];
-		ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-		ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
-		ic->arg[2] = (int32_t)imm;
-
-		/*  Load into the dummy scratch register, if rt = zero  */
-		if (!store && rt == MIPS_GPR_ZERO)
-			ic->arg[0] = (size_t)&cpu->cd.mips.scratch;
-
-		/*  Check for multiple loads or stores in a row using the same
-		    base register:  */
-		if (main_opcode == HI6_LW)
-			cpu->cd.mips.combination_check = COMBINE(multi_lw);
-		if (main_opcode == HI6_SW)
-			cpu->cd.mips.combination_check = COMBINE(multi_sw);
-		break;
-
-	case HI6_LL:
-	case HI6_LLD:
-	case HI6_SC:
-	case HI6_SCD:
-		/*  32-bit load-linked/store-condition for ISA II and up:  */
-		/*  (64-bit load-linked/store-condition for ISA III...)  */
-		if (cpu->cd.mips.cpu_type.isa_level < 2) {
-			ic->f = instr(reserved);
-			break;
-		}
-
-		store = 0;
-		switch (main_opcode) {
-		case HI6_LL:  ic->f = instr(ll); break;
-		case HI6_LLD: ic->f = instr(lld); x64 = 1; break;
-		case HI6_SC:  ic->f = instr(sc); store = 1; break;
-		case HI6_SCD: ic->f = instr(scd); store = 1; x64 = 1; break;
-		}
-		ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-		ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
-		ic->arg[2] = (int32_t)imm;
-		if (!store && rt == MIPS_GPR_ZERO) {
-			if (!cpu->translation_readahead)
-				fatal("HM... unusual load linked\n");
-			goto bad;
-		}
-		break;
-
-	case HI6_LWL:
-	case HI6_LWR:
-	case HI6_LDL:
-	case HI6_LDR:
-	case HI6_SWL:
-	case HI6_SWR:
-	case HI6_SDL:
-	case HI6_SDR:
-		/*  TODO: replace these with faster versions...  */
-		store = 0;
-		switch (main_opcode) {
-		case HI6_LWL: ic->f = instr(lwl); break;
-		case HI6_LWR: ic->f = instr(lwr); break;
-		case HI6_LDL: ic->f = instr(ldl); x64 = 1; break;
-		case HI6_LDR: ic->f = instr(ldr); x64 = 1; break;
-		case HI6_SWL: ic->f = instr(swl); store = 1; break;
-		case HI6_SWR: ic->f = instr(swr); store = 1; break;
-		case HI6_SDL: ic->f = instr(sdl); store = 1; x64 = 1; break;
-		case HI6_SDR: ic->f = instr(sdr); store = 1; x64 = 1; break;
-		}
-		ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-		ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
-		ic->arg[2] = (int32_t)imm;
-
-		/*  Load into the dummy scratch register, if rt = zero  */
-		if (!store && rt == MIPS_GPR_ZERO)
-			ic->arg[0] = (size_t)&cpu->cd.mips.scratch;
-		break;
-
-	case HI6_LWC1:
-	case HI6_SWC1:
-	case HI6_LDC1:
-	case HI6_SDC1:
-		/*  64-bit floating-point load/store for ISA II and up...  */
-		if ((main_opcode == HI6_LDC1 || main_opcode == HI6_SDC1)
-		    && cpu->cd.mips.cpu_type.isa_level < 2) {
-			ic->f = instr(reserved);
-			break;
-		}
-
-		ic->arg[0] = (size_t)&cpu->cd.mips.coproc[1]->reg[rt];
-		ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
-		ic->arg[2] = (int32_t)imm;
-		switch (main_opcode) {
-		case HI6_LWC1: ic->f = instr(lwc1); break;
-		case HI6_LDC1: ic->f = instr(ldc1); break;
-		case HI6_SWC1: ic->f = instr(swc1); break;
-		case HI6_SDC1: ic->f = instr(sdc1); break;
-		}
-
-		/*  Cause a coprocessor unusable exception if
-		    there is no floating point coprocessor:  */
-		if (cpu->cd.mips.cpu_type.flags & NOFPU ||
-		    cpu->cd.mips.coproc[1] == NULL) {
-			ic->f = instr(cpu);
-			ic->arg[0] = 1;
-		}
-		break;
-
-	case HI6_LWC3:
-		/*  PREF (prefetch) on ISA IV and MIPS32/64:  */
-		if (cpu->cd.mips.cpu_type.isa_level >= 4) {
-			/*  Treat as nop for now:  */
-			ic->f = instr(nop);
-		} else {
-			if (!cpu->translation_readahead)
-				fatal("TODO: lwc3 not implemented yet\n");
-			goto bad;
-		}
-		break;
-
-	case HI6_LQ_MDMX:
-		if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
-			if (!cpu->translation_readahead)
-				fatal("TODO: R5900 128-bit loads\n");
-			goto bad;
-		}
-
-		if (!cpu->translation_readahead)
-			fatal("TODO: MDMX\n");
-
-		goto bad;
-		/*  break  */
-
-	case HI6_SQ_SPECIAL3:
-		if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) {
-			if (!cpu->translation_readahead)
-				fatal("TODO: R5900 128-bit stores\n");
-			goto bad;
-		}
-
-		if (cpu->cd.mips.cpu_type.isa_level < 32 ||
-		    cpu->cd.mips.cpu_type.isa_revision < 2) {
-			static int warning = 0;
-			if (!warning && !cpu->translation_readahead) {
-				fatal("[ WARNING! SPECIAL3 opcode used, but"
-				    " the %s processor does not implement "
-				    "such instructions. Only printing this "
-				    "warning once. ]\n",
-				    cpu->cd.mips.cpu_type.name);
-				warning = 1;
-			}
-			ic->f = instr(reserved);
-			break;
-		}
-
-		switch (s6) {
-
-		case SPECIAL3_EXT:
-			{
-				int msbd = rd, lsb = (iword >> 6) & 0x1f;
-				ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-				ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
-				ic->arg[2] = (msbd << 5) + lsb;
-				ic->f = instr(ext);
-				if (rt == MIPS_GPR_ZERO)
-					ic->f = instr(nop);
-			}
-			break;
-
-		case SPECIAL3_DEXT:
-		case SPECIAL3_DEXTM:
-		case SPECIAL3_DEXTU:
-			{
-				int msbd = rd, lsb = (iword >> 6) & 0x1f;
-				if (s6 == SPECIAL3_DEXTM)
-					msbd += 32;
-				if (s6 == SPECIAL3_DEXTU)
-					lsb += 32;
-				ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-				ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
-				ic->arg[2] = (msbd << 6) + lsb;
-				ic->f = instr(dext);
-				if (rt == MIPS_GPR_ZERO)
-					ic->f = instr(nop);
-			}
-			break;
-
-		case SPECIAL3_INS:
-			{
-				int msb = rd, lsb = (iword >> 6) & 0x1f;
-				ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-				ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs];
-				ic->arg[2] = (msb << 5) + lsb;
-				ic->f = instr(ins);
-				if (rt == MIPS_GPR_ZERO)
-					ic->f = instr(nop);
-			}
-			break;
-
-		case SPECIAL3_BSHFL:
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rd];
-			switch (s10) {
-			case BSHFL_WSBH:
-				ic->f = instr(wsbh);
-				break;
-			case BSHFL_SEB:
-				ic->f = instr(seb);
-				break;
-			case BSHFL_SEH:
-				ic->f = instr(seh);
-				break;
-			default:goto bad;
-			}
-			break;
-
-		case SPECIAL3_DBSHFL:
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-			ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rd];
-			switch (s10) {
-			case BSHFL_DSBH:
-				ic->f = instr(dsbh);
-				break;
-			case BSHFL_DSHD:
-				ic->f = instr(dshd);
-				break;
-			default:goto bad;
-			}
-			break;
-
-		case SPECIAL3_RDHWR:
-			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt];
-
-			switch (rd) {
-
-			case 0:	ic->f = instr(rdhwr_cpunum);
-				if (rt == MIPS_GPR_ZERO)
-					ic->f = instr(nop);
-				break;
-
-			case 2:	ic->f = instr(rdhwr_cc);
-				if (rt == MIPS_GPR_ZERO)
-					ic->f = instr(nop);
-				break;
-
-                        case 29: ic->f = instr(reserved);
-                                 break;
-
-			default:if (!cpu->translation_readahead)
-					fatal("unimplemented rdhwr "
-					    "register rd=%i\n", rd);
-				goto bad;
-			}
-			break;
-
-		default:goto bad;
-		}
-		break;
-
-	case HI6_CACHE:
-		/*  TODO: rt and op etc...  */
-		ic->f = instr(cache);
-		break;
-
-	default:goto bad;
-	}
-
-
-#ifdef MODE32
-	if (x64) {
-		static int has_warned = 0;
-		if (!has_warned && !cpu->translation_readahead) {
-			fatal("[ WARNING/NOTE: attempt to execute a 64-bit"
-			    " instruction on an emulated 32-bit processor; "
-			    "pc=0x%08" PRIx32" ]\n", (uint32_t)cpu->pc);
-			has_warned = 1;
-		}
-		if (cpu->translation_readahead)
-			goto bad;
-		else
-			ic->f = instr(reserved);
-	}
-#else
-	(void)x64; // avoid compiler warning
-#endif
-
-
-#define	DYNTRANS_TO_BE_TRANSLATED_TAIL
-#include "cpu_dyntrans.cc" 
-#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_mips_instr_loadstore.c gxemul-0.7.0+dfsg/src/cpus/cpu_mips_instr_loadstore.c
--- gxemul-0.6.2/src/cpus/cpu_mips_instr_loadstore.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_mips_instr_loadstore.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,325 @@
+/*
+ *  Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  MIPS load/store instructions; the following args are used:
+ *  
+ *  arg[0] = pointer to the register to load to or store from
+ *  arg[1] = pointer to the base register
+ *  arg[2] = offset (as an int32_t)
+ *
+ *  The GENERIC function always checks for alignment, and supports both big
+ *  and little endian byte order.
+ *
+ *  The quick function is included twice (big/little endian) for each
+ *  GENERIC function.
+ */
+
+
+#ifdef LS_INCLUDE_GENERIC
+void LS_GENERIC_N(struct cpu *cpu, struct mips_instr_call *ic)
+{
+	MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
+	uint8_t data[LS_SIZE];
+#ifdef LS_LOAD
+	uint64_t x;
+#endif
+
+	/*  Synchronize the PC:  */
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+
+#ifndef LS_1
+	/*  Check alignment:  */
+	if (addr & (LS_SIZE - 1)) {
+#if 1
+		uint64_t vaddr_vpn2=0, vaddr_asid=0;
+
+		int exc_model = cpu->cd.mips.cpu_type.exc_model;
+		struct mips_coproc *cp0 = cpu->cd.mips.coproc[0];
+
+		if (exc_model == EXC3K) {
+			vaddr_asid = (cp0->reg[COP0_ENTRYHI] &
+			    R2K3K_ENTRYHI_ASID_MASK) >>
+			    R2K3K_ENTRYHI_ASID_SHIFT;
+			vaddr_vpn2 = (addr & R2K3K_ENTRYHI_VPN_MASK) >>
+			    R2K3K_ENTRYHI_VPN_SHIFT;
+		} else {
+			vaddr_asid = cp0->reg[COP0_ENTRYHI] & ENTRYHI_ASID;
+
+			if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) {
+				vaddr_vpn2 = (addr &
+				    ENTRYHI_VPN2_MASK_R10K) >>
+				    ENTRYHI_VPN2_SHIFT;
+			} else {
+				vaddr_vpn2 = (addr & ENTRYHI_VPN2_MASK) >>
+				    ENTRYHI_VPN2_SHIFT;
+			}
+		}
+
+		/*  Cause an address alignment exception:  */
+		mips_cpu_exception(cpu,
+#ifdef LS_LOAD
+		    EXCEPTION_ADEL,
+#else
+		    EXCEPTION_ADES,
+#endif
+		    0, addr, 0, vaddr_vpn2, vaddr_asid, 0);
+#else
+		fatal("{ mips dyntrans alignment exception, size = %i,"
+		    " addr = %016"PRIx64", pc = %016"PRIx64" }\n", LS_SIZE,
+		    (uint64_t) addr, cpu->pc);
+
+		cpu->running = false;
+		cpu->cd.mips.next_ic = &nothing_call;
+#endif
+		return;
+	}
+#endif
+
+#ifdef LS_LOAD
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
+	    MEM_READ, CACHE_DATA)) {
+		/*  Exception.  */
+		if (!cpu->running)
+			cpu->cd.mips.next_ic = &nothing_call;
+		return;
+	}
+	x = memory_readmax64(cpu, data, LS_SIZE);
+#ifdef LS_SIGNED
+#ifdef LS_1
+	x = (int8_t)x;
+#endif
+#ifdef LS_2
+	x = (int16_t)x;
+#endif
+#ifdef LS_4
+	x = (int32_t)x;
+#endif
+#endif
+	reg(ic->arg[0]) = x;
+#else	/*  LS_STORE:  */
+	memory_writemax64(cpu, data, LS_SIZE, reg(ic->arg[0]));
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
+	    MEM_WRITE, CACHE_DATA)) {
+		/*  Exception.  */
+		if (!cpu->running)
+			cpu->cd.mips.next_ic = &nothing_call;
+		return;
+	}
+#endif
+}
+#endif	/*  LS_INCLUDE_GENERIC  */
+
+
+void LS_N(struct cpu *cpu, struct mips_instr_call *ic)
+{
+	MODE_uint_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
+	unsigned char *p;
+#ifdef MODE32
+#ifdef LS_LOAD
+	p = cpu->cd.mips.host_load[addr >> 12];
+#else
+	p = cpu->cd.mips.host_store[addr >> 12];
+#endif
+#else	/*  !MODE32  */
+	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+	uint32_t x1, x2, x3;
+	struct DYNTRANS_L2_64_TABLE *l2;
+	struct DYNTRANS_L3_64_TABLE *l3;
+
+	x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
+	x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+	x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
+	/*  fatal("X3: addr=%016"PRIx64" x1=%x x2=%x x3=%x\n",
+	    (uint64_t) addr, (int) x1, (int) x2, (int) x3);  */
+	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
+	/*  fatal("  l2 = %p\n", l2);  */
+	l3 = l2->l3[x2];
+	/*  fatal("  l3 = %p\n", l3);  */
+#ifdef LS_LOAD
+	p = l3->host_load[x3];
+#else
+	p = l3->host_store[x3];
+#endif
+	/*  fatal("  p = %p\n", p);  */
+#endif
+
+	if (unlikely(p == NULL
+#ifndef LS_1
+	    || addr & (LS_SIZE - 1)
+#endif
+	    )) {
+		LS_GENERIC_N(cpu, ic);
+		return;
+	}
+
+	addr &= 0xfff;
+
+#ifdef LS_LOAD
+	/*  Load:  */
+
+#ifdef LS_1
+	reg(ic->arg[0]) =
+#ifdef LS_SIGNED
+	    (int8_t)
+#endif
+	    p[addr];
+#endif	/*  LS_1  */
+
+#ifdef LS_2
+	reg(ic->arg[0]) =
+#ifdef LS_SIGNED
+	    (int16_t)
+#endif
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	    ( *(uint16_t *)(p + addr) );
+#else
+	    ((p[addr]<<8) + p[addr+1]);
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	    ( *(uint16_t *)(p + addr) );
+#else
+	    (p[addr] + (p[addr+1]<<8));
+#endif
+#endif
+#endif	/*  LS_2  */
+
+#ifdef LS_4
+	reg(ic->arg[0]) =
+#ifdef LS_SIGNED
+	    (int32_t)
+#else
+	    (uint32_t)
+#endif
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	    ( *(uint32_t *)(p + addr) );
+#else
+	    ((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]);
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	    ( *(uint32_t *)(p + addr) );
+#else
+	    (p[addr] + (p[addr+1]<<8) + (p[addr+2]<<16) + (p[addr+3]<<24));
+#endif
+#endif
+#endif	/*  LS_4  */
+
+#ifdef LS_8
+	*((uint64_t *)ic->arg[0]) =
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	    ( *(uint64_t *)(p + addr) );
+#else
+	    ((uint64_t)p[addr] << 56) + ((uint64_t)p[addr+1] << 48) +
+	    ((uint64_t)p[addr+2] << 40) + ((uint64_t)p[addr+3] << 32) +
+	    ((uint64_t)p[addr+4] << 24) +
+	    (p[addr+5] << 16) + (p[addr+6] << 8) + p[addr+7];
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	    ( *(uint64_t *)(p + addr) );
+#else
+	    p[addr+0] + (p[addr+1] << 8) + (p[addr+2] << 16) +
+	    ((uint64_t)p[addr+3] << 24) + ((uint64_t)p[addr+4] << 32) +
+	    ((uint64_t)p[addr+5] << 40) + ((uint64_t)p[addr+6] << 48) +
+	    ((uint64_t)p[addr+7] << 56);
+#endif
+#endif
+#endif	/*  LS_8  */
+
+#else
+	/*  Store: */
+
+#ifdef LS_1
+	p[addr] = reg(ic->arg[0]);
+#endif
+#ifdef LS_2
+	{ uint32_t x = reg(ic->arg[0]);
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	*((uint16_t *)(p+addr)) = x; }
+#else
+	p[addr] = x >> 8; p[addr+1] = x; }
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	*((uint16_t *)(p+addr)) = x; }
+#else
+	p[addr] = x; p[addr+1] = x >> 8; }
+#endif
+#endif
+#endif  /*  LS_2  */
+#ifdef LS_4
+	{ uint32_t x = reg(ic->arg[0]);
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	*((uint32_t *)(p+addr)) = x; }
+#else
+	p[addr] = x >> 24; p[addr+1] = x >> 16; 
+	p[addr+2] = x >> 8; p[addr+3] = x; }
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	*((uint32_t *)(p+addr)) = x; }
+#else
+	p[addr] = x; p[addr+1] = x >> 8; 
+	p[addr+2] = x >> 16; p[addr+3] = x >> 24; }
+#endif
+#endif
+#endif  /*  LS_4  */
+#ifdef LS_8
+	{ uint64_t x = *(uint64_t *)(ic->arg[0]);
+#ifdef LS_BE
+#ifdef HOST_BIG_ENDIAN
+	*((uint64_t *)(p+addr)) = x; }
+#else
+	p[addr]   = x >> 56; p[addr+1] = x >> 48; p[addr+2] = x >> 40;
+	p[addr+3] = x >> 32; p[addr+4] = x >> 24; p[addr+5] = x >> 16;
+	p[addr+6] = x >> 8;  p[addr+7] = x; }
+#endif
+#else
+#ifdef HOST_LITTLE_ENDIAN
+	*((uint64_t *)(p+addr)) = x; }
+#else
+	p[addr]   = x;       p[addr+1] = x >>  8; p[addr+2] = x >> 16;
+	p[addr+3] = x >> 24; p[addr+4] = x >> 32; p[addr+5] = x >> 40;
+	p[addr+6] = x >> 48; p[addr+7] = x >> 56; }
+#endif
+#endif
+#endif	/*  LS_8  */
+
+#endif	/*  store  */
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_mips_instr_loadstore.cc gxemul-0.7.0+dfsg/src/cpus/cpu_mips_instr_loadstore.cc
--- gxemul-0.6.2/src/cpus/cpu_mips_instr_loadstore.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_mips_instr_loadstore.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,299 +0,0 @@
-/*
- *  Copyright (C) 2006-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  MIPS load/store instructions; the following args are used:
- *  
- *  arg[0] = pointer to the register to load to or store from
- *  arg[1] = pointer to the base register
- *  arg[2] = offset (as an int32_t)
- *
- *  The GENERIC function always checks for alignment, and supports both big
- *  and little endian byte order.
- *
- *  The quick function is included twice (big/little endian) for each
- *  GENERIC function.
- */
-
-
-#ifdef LS_INCLUDE_GENERIC
-void LS_GENERIC_N(struct cpu *cpu, struct mips_instr_call *ic)
-{
-	MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
-	uint8_t data[LS_SIZE];
-#ifdef LS_LOAD
-	uint64_t x;
-#endif
-
-	/*  Synchronize the PC:  */
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-
-#ifndef LS_1
-	/*  Check alignment:  */
-	if (addr & (LS_SIZE - 1)) {
-#if 1
-		/*  Cause an address alignment exception:  */
-		mips_cpu_exception(cpu,
-#ifdef LS_LOAD
-		    EXCEPTION_ADEL,
-#else
-		    EXCEPTION_ADES,
-#endif
-		    0, addr, 0, 0, 0, 0);
-#else
-		fatal("{ mips dyntrans alignment exception, size = %i,"
-		    " addr = %016"PRIx64", pc = %016"PRIx64" }\n", LS_SIZE,
-		    (uint64_t) addr, cpu->pc);
-
-		/*  TODO: Generalize this into a abort_call, or similar:  */
-		cpu->running = 0;
-		debugger_n_steps_left_before_interaction = 0;
-		cpu->cd.mips.next_ic = &nothing_call;
-#endif
-		return;
-	}
-#endif
-
-#ifdef LS_LOAD
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
-	    MEM_READ, CACHE_DATA)) {
-		/*  Exception.  */
-		return;
-	}
-	x = memory_readmax64(cpu, data, LS_SIZE);
-#ifdef LS_SIGNED
-#ifdef LS_1
-	x = (int8_t)x;
-#endif
-#ifdef LS_2
-	x = (int16_t)x;
-#endif
-#ifdef LS_4
-	x = (int32_t)x;
-#endif
-#endif
-	reg(ic->arg[0]) = x;
-#else	/*  LS_STORE:  */
-	memory_writemax64(cpu, data, LS_SIZE, reg(ic->arg[0]));
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
-	    MEM_WRITE, CACHE_DATA)) {
-		/*  Exception.  */
-		return;
-	}
-#endif
-}
-#endif	/*  LS_INCLUDE_GENERIC  */
-
-
-void LS_N(struct cpu *cpu, struct mips_instr_call *ic)
-{
-	MODE_uint_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
-	unsigned char *p;
-#ifdef MODE32
-#ifdef LS_LOAD
-	p = cpu->cd.mips.host_load[addr >> 12];
-#else
-	p = cpu->cd.mips.host_store[addr >> 12];
-#endif
-#else	/*  !MODE32  */
-	const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
-	const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
-	const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
-	uint32_t x1, x2, x3;
-	struct DYNTRANS_L2_64_TABLE *l2;
-	struct DYNTRANS_L3_64_TABLE *l3;
-
-	x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
-	x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
-	x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
-	/*  fatal("X3: addr=%016"PRIx64" x1=%x x2=%x x3=%x\n",
-	    (uint64_t) addr, (int) x1, (int) x2, (int) x3);  */
-	l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
-	/*  fatal("  l2 = %p\n", l2);  */
-	l3 = l2->l3[x2];
-	/*  fatal("  l3 = %p\n", l3);  */
-#ifdef LS_LOAD
-	p = l3->host_load[x3];
-#else
-	p = l3->host_store[x3];
-#endif
-	/*  fatal("  p = %p\n", p);  */
-#endif
-
-	if (unlikely(p == NULL
-#ifndef LS_1
-	    || addr & (LS_SIZE - 1)
-#endif
-	    )) {
-		LS_GENERIC_N(cpu, ic);
-		return;
-	}
-
-	addr &= 0xfff;
-
-#ifdef LS_LOAD
-	/*  Load:  */
-
-#ifdef LS_1
-	reg(ic->arg[0]) =
-#ifdef LS_SIGNED
-	    (int8_t)
-#endif
-	    p[addr];
-#endif	/*  LS_1  */
-
-#ifdef LS_2
-	reg(ic->arg[0]) =
-#ifdef LS_SIGNED
-	    (int16_t)
-#endif
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	    ( *(uint16_t *)(p + addr) );
-#else
-	    ((p[addr]<<8) + p[addr+1]);
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	    ( *(uint16_t *)(p + addr) );
-#else
-	    (p[addr] + (p[addr+1]<<8));
-#endif
-#endif
-#endif	/*  LS_2  */
-
-#ifdef LS_4
-	reg(ic->arg[0]) =
-#ifdef LS_SIGNED
-	    (int32_t)
-#else
-	    (uint32_t)
-#endif
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	    ( *(uint32_t *)(p + addr) );
-#else
-	    ((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]);
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	    ( *(uint32_t *)(p + addr) );
-#else
-	    (p[addr] + (p[addr+1]<<8) + (p[addr+2]<<16) + (p[addr+3]<<24));
-#endif
-#endif
-#endif	/*  LS_4  */
-
-#ifdef LS_8
-	*((uint64_t *)ic->arg[0]) =
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	    ( *(uint64_t *)(p + addr) );
-#else
-	    ((uint64_t)p[addr] << 56) + ((uint64_t)p[addr+1] << 48) +
-	    ((uint64_t)p[addr+2] << 40) + ((uint64_t)p[addr+3] << 32) +
-	    ((uint64_t)p[addr+4] << 24) +
-	    (p[addr+5] << 16) + (p[addr+6] << 8) + p[addr+7];
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	    ( *(uint64_t *)(p + addr) );
-#else
-	    p[addr+0] + (p[addr+1] << 8) + (p[addr+2] << 16) +
-	    ((uint64_t)p[addr+3] << 24) + ((uint64_t)p[addr+4] << 32) +
-	    ((uint64_t)p[addr+5] << 40) + ((uint64_t)p[addr+6] << 48) +
-	    ((uint64_t)p[addr+7] << 56);
-#endif
-#endif
-#endif	/*  LS_8  */
-
-#else
-	/*  Store: */
-
-#ifdef LS_1
-	p[addr] = reg(ic->arg[0]);
-#endif
-#ifdef LS_2
-	{ uint32_t x = reg(ic->arg[0]);
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	*((uint16_t *)(p+addr)) = x; }
-#else
-	p[addr] = x >> 8; p[addr+1] = x; }
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	*((uint16_t *)(p+addr)) = x; }
-#else
-	p[addr] = x; p[addr+1] = x >> 8; }
-#endif
-#endif
-#endif  /*  LS_2  */
-#ifdef LS_4
-	{ uint32_t x = reg(ic->arg[0]);
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	*((uint32_t *)(p+addr)) = x; }
-#else
-	p[addr] = x >> 24; p[addr+1] = x >> 16; 
-	p[addr+2] = x >> 8; p[addr+3] = x; }
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	*((uint32_t *)(p+addr)) = x; }
-#else
-	p[addr] = x; p[addr+1] = x >> 8; 
-	p[addr+2] = x >> 16; p[addr+3] = x >> 24; }
-#endif
-#endif
-#endif  /*  LS_4  */
-#ifdef LS_8
-	{ uint64_t x = *(uint64_t *)(ic->arg[0]);
-#ifdef LS_BE
-#ifdef HOST_BIG_ENDIAN
-	*((uint64_t *)(p+addr)) = x; }
-#else
-	p[addr]   = x >> 56; p[addr+1] = x >> 48; p[addr+2] = x >> 40;
-	p[addr+3] = x >> 32; p[addr+4] = x >> 24; p[addr+5] = x >> 16;
-	p[addr+6] = x >> 8;  p[addr+7] = x; }
-#endif
-#else
-#ifdef HOST_LITTLE_ENDIAN
-	*((uint64_t *)(p+addr)) = x; }
-#else
-	p[addr]   = x;       p[addr+1] = x >>  8; p[addr+2] = x >> 16;
-	p[addr+3] = x >> 24; p[addr+4] = x >> 32; p[addr+5] = x >> 40;
-	p[addr+6] = x >> 48; p[addr+7] = x >> 56; }
-#endif
-#endif
-#endif	/*  LS_8  */
-
-#endif	/*  store  */
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_mips_instr_unaligned.c gxemul-0.7.0+dfsg/src/cpus/cpu_mips_instr_unaligned.c
--- gxemul-0.6.2/src/cpus/cpu_mips_instr_unaligned.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_mips_instr_unaligned.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,158 @@
+/*
+ *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  MIPS unaligned load/store instructions; the following args are used:
+ *  
+ *  arg[0] = pointer to the register to load to or store from
+ *  arg[1] = pointer to the base register
+ *  arg[2] = offset (as an int32_t)
+ *
+ *  NOTE/TODO: This is a very slow generic implementation, from the
+ *  pre-Dyntrans emulation mode. It should be rewritten.
+ */
+
+#include "cop0.h"
+#include "cpu.h"
+#include "memory.h"
+#include "misc.h"
+
+
+void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic,
+	int is_left, int wlen, int store)
+{
+	/*  For L (Left):   address is the most significant byte  */
+	/*  For R (Right):  address is the least significant byte  */
+	uint64_t addr = *((uint64_t *)ic->arg[1]) + (int32_t)ic->arg[2];
+	int i, dir, reg_dir, reg_ofs, ok;
+	uint64_t result_value, tmpaddr;
+	uint64_t aligned_addr = addr & ~(wlen-1);
+	unsigned char aligned_word[8], databyte;
+
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
+	    / sizeof(struct mips_instr_call);
+	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
+	    << MIPS_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
+
+	dir = 1;		/*  big endian, Left  */
+	reg_dir = -1;
+	reg_ofs = wlen - 1;	/*  byte offset in the register  */
+	if (!is_left) {
+		dir = -dir;
+		reg_ofs = 0;
+		reg_dir = 1;
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		dir = -dir;
+
+	result_value = *((uint64_t *)ic->arg[0]);
+
+	if (cpu->is_32bit) {
+		result_value = (int32_t)result_value;
+		aligned_addr = (int32_t)aligned_addr;
+		addr = (int32_t)addr;
+	}
+
+	if (store) {
+		/*  Store:  */
+		uint64_t oldpc = cpu->pc;
+
+		/*
+		 *  NOTE (this is ugly): The memory_rw()
+		 *  call generates a TLBL exception, if there
+		 *  is a tlb refill exception. However, since
+		 *  this is a Store, the exception is converted
+		 *  to a TLBS:
+		 */
+		ok = cpu->memory_rw(cpu, cpu->mem, aligned_addr,
+		    &aligned_word[0], wlen, MEM_READ, CACHE_DATA);
+		if (!ok) {
+			if (cpu->pc != oldpc) {
+				cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] &=
+				    ~CAUSE_EXCCODE_MASK;
+				cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] |=
+				    (EXCEPTION_TLBS << CAUSE_EXCCODE_SHIFT);
+			}
+			return;
+		}
+
+		for (i=0; i<wlen; i++) {
+			tmpaddr = addr + i*dir;
+			/*  Have we moved into another word/dword? Then stop: */
+			if ( (tmpaddr & ~(wlen-1)) != (addr & ~(wlen-1)) )
+				break;
+
+			/*  debug("unaligned byte at %016"PRIx64",
+			    reg_ofs=%i reg=0x%016"PRIx64"\n",
+			    tmpaddr, reg_ofs, (long long)result_value);  */
+
+			/*  Store one byte:  */
+			aligned_word[tmpaddr & (wlen-1)] =
+			    (result_value >> (reg_ofs * 8)) & 255;
+
+			reg_ofs += reg_dir;
+		}
+
+		ok = cpu->memory_rw(cpu, cpu->mem,
+		    aligned_addr, &aligned_word[0], wlen,
+		    MEM_WRITE, CACHE_DATA);
+
+		return;
+	}
+
+	/*  Load:  */
+	ok = cpu->memory_rw(cpu, cpu->mem, aligned_addr, &aligned_word[0], wlen,
+	    MEM_READ, CACHE_DATA);
+	if (!ok)
+		return;
+
+	for (i=0; i<wlen; i++) {
+		tmpaddr = addr + i*dir;
+		/*  Have we moved into another word/dword? Then stop: */
+		if ( (tmpaddr & ~(wlen-1)) != (addr & ~(wlen-1)) )
+			break;
+
+		/*  debug("unaligned byte at %016"PRIx64", reg_ofs=%i reg="
+		    "0x%016"PRIx64"\n", (uint64_t) tmpaddr,
+		    reg_ofs, (uint64_t)result_value); */
+
+		/*  Load one byte:  */
+		databyte = aligned_word[tmpaddr & (wlen-1)];
+		result_value &= ~((uint64_t)0xff << (reg_ofs * 8));
+		result_value |= (uint64_t)databyte << (reg_ofs * 8);
+
+		reg_ofs += reg_dir;
+	}
+
+	/*  Sign extend for 32-bit load lefts:  */
+	if (!store && wlen == sizeof(uint32_t))
+		result_value = (int32_t)result_value;
+
+	(*(uint64_t *)ic->arg[0]) = result_value;
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_mips_instr_unaligned.cc gxemul-0.7.0+dfsg/src/cpus/cpu_mips_instr_unaligned.cc
--- gxemul-0.6.2/src/cpus/cpu_mips_instr_unaligned.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_mips_instr_unaligned.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,158 +0,0 @@
-/*
- *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  MIPS unaligned load/store instructions; the following args are used:
- *  
- *  arg[0] = pointer to the register to load to or store from
- *  arg[1] = pointer to the base register
- *  arg[2] = offset (as an int32_t)
- *
- *  NOTE/TODO: This is a very slow generic implementation, from the
- *  pre-Dyntrans emulation mode. It should be rewritten.
- */
-
-#include "cop0.h"
-#include "cpu.h"
-#include "memory.h"
-#include "misc.h"
-
-
-void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic,
-	int is_left, int wlen, int store)
-{
-	/*  For L (Left):   address is the most significant byte  */
-	/*  For R (Right):  address is the least significant byte  */
-	uint64_t addr = *((uint64_t *)ic->arg[1]) + (int32_t)ic->arg[2];
-	int i, dir, reg_dir, reg_ofs, ok;
-	uint64_t result_value, tmpaddr;
-	uint64_t aligned_addr = addr & ~(wlen-1);
-	unsigned char aligned_word[8], databyte;
-
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
-	    / sizeof(struct mips_instr_call);
-	cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
-	    << MIPS_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
-
-	dir = 1;		/*  big endian, Left  */
-	reg_dir = -1;
-	reg_ofs = wlen - 1;	/*  byte offset in the register  */
-	if (!is_left) {
-		dir = -dir;
-		reg_ofs = 0;
-		reg_dir = 1;
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		dir = -dir;
-
-	result_value = *((uint64_t *)ic->arg[0]);
-
-	if (cpu->is_32bit) {
-		result_value = (int32_t)result_value;
-		aligned_addr = (int32_t)aligned_addr;
-		addr = (int32_t)addr;
-	}
-
-	if (store) {
-		/*  Store:  */
-		uint64_t oldpc = cpu->pc;
-
-		/*
-		 *  NOTE (this is ugly): The memory_rw()
-		 *  call generates a TLBL exception, if there
-		 *  is a tlb refill exception. However, since
-		 *  this is a Store, the exception is converted
-		 *  to a TLBS:
-		 */
-		ok = cpu->memory_rw(cpu, cpu->mem, aligned_addr,
-		    &aligned_word[0], wlen, MEM_READ, CACHE_DATA);
-		if (!ok) {
-			if (cpu->pc != oldpc) {
-				cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] &=
-				    ~CAUSE_EXCCODE_MASK;
-				cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] |=
-				    (EXCEPTION_TLBS << CAUSE_EXCCODE_SHIFT);
-			}
-			return;
-		}
-
-		for (i=0; i<wlen; i++) {
-			tmpaddr = addr + i*dir;
-			/*  Have we moved into another word/dword? Then stop: */
-			if ( (tmpaddr & ~(wlen-1)) != (addr & ~(wlen-1)) )
-				break;
-
-			/*  debug("unaligned byte at %016"PRIx64",
-			    reg_ofs=%i reg=0x%016"PRIx64"\n",
-			    tmpaddr, reg_ofs, (long long)result_value);  */
-
-			/*  Store one byte:  */
-			aligned_word[tmpaddr & (wlen-1)] =
-			    (result_value >> (reg_ofs * 8)) & 255;
-
-			reg_ofs += reg_dir;
-		}
-
-		ok = cpu->memory_rw(cpu, cpu->mem,
-		    aligned_addr, &aligned_word[0], wlen,
-		    MEM_WRITE, CACHE_DATA);
-
-		return;
-	}
-
-	/*  Load:  */
-	ok = cpu->memory_rw(cpu, cpu->mem, aligned_addr, &aligned_word[0], wlen,
-	    MEM_READ, CACHE_DATA);
-	if (!ok)
-		return;
-
-	for (i=0; i<wlen; i++) {
-		tmpaddr = addr + i*dir;
-		/*  Have we moved into another word/dword? Then stop: */
-		if ( (tmpaddr & ~(wlen-1)) != (addr & ~(wlen-1)) )
-			break;
-
-		/*  debug("unaligned byte at %016"PRIx64", reg_ofs=%i reg="
-		    "0x%016"PRIx64"\n", (uint64_t) tmpaddr,
-		    reg_ofs, (uint64_t)result_value); */
-
-		/*  Load one byte:  */
-		databyte = aligned_word[tmpaddr & (wlen-1)];
-		result_value &= ~((uint64_t)0xff << (reg_ofs * 8));
-		result_value |= (uint64_t)databyte << (reg_ofs * 8);
-
-		reg_ofs += reg_dir;
-	}
-
-	/*  Sign extend for 32-bit load lefts:  */
-	if (!store && wlen == sizeof(uint32_t))
-		result_value = (int32_t)result_value;
-
-	(*(uint64_t *)ic->arg[0]) = result_value;
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_ppc.c gxemul-0.7.0+dfsg/src/cpus/cpu_ppc.c
--- gxemul-0.6.2/src/cpus/cpu_ppc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_ppc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1835 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  PowerPC/POWER CPU emulation.
+ */
+
+#include <ctype.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "cpu.h"
+#include "devices.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "of.h"
+#include "opcodes_ppc.h"
+#include "ppc_spr_strings.h"
+#include "settings.h"
+#include "symbol.h"
+
+#include "thirdparty/ppc_bat.h"
+#include "thirdparty/ppc_pte.h"
+#include "thirdparty/ppc_spr.h"
+
+#define	DYNTRANS_DUALMODE_32
+#include "tmp_ppc_head.c"
+
+
+void ppc_pc_to_pointers(struct cpu *);
+void ppc32_pc_to_pointers(struct cpu *);
+
+void ppc_irq_interrupt_assert(struct interrupt *interrupt);
+void ppc_irq_interrupt_deassert(struct interrupt *interrupt);
+
+
+/*
+ *  ppc_cpu_new():
+ *
+ *  Create a new PPC cpu object.
+ *
+ *  Returns 1 on success, 0 if there was no matching PPC processor with
+ *  this cpu_type_name.
+ */
+int ppc_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
+	int cpu_id, char *cpu_type_name)
+{
+	int i, found;
+	struct ppc_cpu_type_def cpu_type_defs[] = PPC_CPU_TYPE_DEFS;
+
+	/*  Scan the cpu_type_defs list for this cpu type:  */
+	i = 0;
+	found = -1;
+	while (i >= 0 && cpu_type_defs[i].name != NULL) {
+		if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
+			found = i;
+			break;
+		}
+		i++;
+	}
+	if (found == -1)
+		return 0;
+
+	cpu->memory_rw = ppc_memory_rw;
+
+	cpu->cd.ppc.cpu_type = cpu_type_defs[found];
+	cpu->name            = strdup(cpu->cd.ppc.cpu_type.name);
+	cpu->byte_order      = EMUL_BIG_ENDIAN;
+	cpu->cd.ppc.mode     = MODE_PPC;	/*  TODO  */
+
+	/*  Current operating mode:  */
+	cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits;
+	cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr;
+
+	/*  cpu->cd.ppc.msr = PPC_MSR_IR | PPC_MSR_DR |
+	    PPC_MSR_SF | PPC_MSR_FP;  */
+
+	cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_IBAT1L] = 0x00000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_IBAT3U] = 0xf0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_IBAT3L] = 0xf0000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_DBAT0U] = 0x00001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_DBAT0L] = 0x00000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_DBAT1U] = 0xc0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_DBAT1L] = 0x00000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_DBAT2U] = 0xe0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_DBAT2L] = 0xe0000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_DBAT3U] = 0xf0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_DBAT3L] = 0xf0000000 | BAT_PP_RW;
+
+	cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0;
+
+	if (cpu->is_32bit) {
+		cpu->run_instr = ppc32_run_instr;
+		cpu->update_translation_table = ppc32_update_translation_table;
+		cpu->invalidate_translation_caches =
+		    ppc32_invalidate_translation_caches;
+		cpu->invalidate_code_translation =
+		    ppc32_invalidate_code_translation;
+	} else {
+		cpu->run_instr = ppc_run_instr;
+		cpu->update_translation_table = ppc_update_translation_table;
+		cpu->invalidate_translation_caches =
+		    ppc_invalidate_translation_caches;
+		cpu->invalidate_code_translation =
+		    ppc_invalidate_code_translation;
+	}
+
+	cpu->translate_v2p = ppc_translate_v2p;
+
+	cpu->cd.ppc.spr[SPR_PIR] = cpu_id;
+
+	/*  Some default stack pointer value.  TODO: move this?  */
+	cpu->cd.ppc.gpr[1] = machine->physical_ram_in_mb * 1048576 - 4096;
+
+	/*
+	 *  NOTE/TODO: Ugly hack for OpenFirmware emulation:
+	 */
+	if (cpu->machine->prom_emulation)
+		cpu->cd.ppc.of_emul_addr = 0xfff00000;
+
+	/*  Add all register names to the settings:  */
+	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
+	CPU_SETTINGS_ADD_REGISTER64("msr", cpu->cd.ppc.msr);
+	CPU_SETTINGS_ADD_REGISTER64("ctr", cpu->cd.ppc.spr[SPR_CTR]);
+	CPU_SETTINGS_ADD_REGISTER64("xer", cpu->cd.ppc.spr[SPR_XER]);
+	CPU_SETTINGS_ADD_REGISTER64("dec", cpu->cd.ppc.spr[SPR_DEC]);
+	CPU_SETTINGS_ADD_REGISTER64("hdec", cpu->cd.ppc.spr[SPR_HDEC]);
+	CPU_SETTINGS_ADD_REGISTER64("srr0", cpu->cd.ppc.spr[SPR_SRR0]);
+	CPU_SETTINGS_ADD_REGISTER64("srr1", cpu->cd.ppc.spr[SPR_SRR1]);
+	CPU_SETTINGS_ADD_REGISTER64("sdr1", cpu->cd.ppc.spr[SPR_SDR1]);
+	CPU_SETTINGS_ADD_REGISTER64("ibat0u", cpu->cd.ppc.spr[SPR_IBAT0U]);
+	CPU_SETTINGS_ADD_REGISTER64("ibat0l", cpu->cd.ppc.spr[SPR_IBAT0L]);
+	CPU_SETTINGS_ADD_REGISTER64("ibat1u", cpu->cd.ppc.spr[SPR_IBAT1U]);
+	CPU_SETTINGS_ADD_REGISTER64("ibat1l", cpu->cd.ppc.spr[SPR_IBAT1L]);
+	CPU_SETTINGS_ADD_REGISTER64("ibat2u", cpu->cd.ppc.spr[SPR_IBAT2U]);
+	CPU_SETTINGS_ADD_REGISTER64("ibat2l", cpu->cd.ppc.spr[SPR_IBAT2L]);
+	CPU_SETTINGS_ADD_REGISTER64("ibat3u", cpu->cd.ppc.spr[SPR_IBAT3U]);
+	CPU_SETTINGS_ADD_REGISTER64("ibat3l", cpu->cd.ppc.spr[SPR_IBAT3L]);
+	CPU_SETTINGS_ADD_REGISTER64("dbat0u", cpu->cd.ppc.spr[SPR_DBAT0U]);
+	CPU_SETTINGS_ADD_REGISTER64("dbat0l", cpu->cd.ppc.spr[SPR_DBAT0L]);
+	CPU_SETTINGS_ADD_REGISTER64("dbat1u", cpu->cd.ppc.spr[SPR_DBAT1U]);
+	CPU_SETTINGS_ADD_REGISTER64("dbat1l", cpu->cd.ppc.spr[SPR_DBAT1L]);
+	CPU_SETTINGS_ADD_REGISTER64("dbat2u", cpu->cd.ppc.spr[SPR_DBAT2U]);
+	CPU_SETTINGS_ADD_REGISTER64("dbat2l", cpu->cd.ppc.spr[SPR_DBAT2L]);
+	CPU_SETTINGS_ADD_REGISTER64("dbat3u", cpu->cd.ppc.spr[SPR_DBAT3U]);
+	CPU_SETTINGS_ADD_REGISTER64("dbat3l", cpu->cd.ppc.spr[SPR_DBAT3L]);
+	CPU_SETTINGS_ADD_REGISTER64("lr", cpu->cd.ppc.spr[SPR_LR]);
+	CPU_SETTINGS_ADD_REGISTER32("cr", cpu->cd.ppc.cr);
+	CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.ppc.fpscr);
+	/*  Integer GPRs, floating point registers, and segment registers:  */
+	for (i=0; i<PPC_NGPRS; i++) {
+		char tmpstr[5];
+		snprintf(tmpstr, sizeof(tmpstr), "r%i", i);
+		CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.gpr[i]);
+	}
+	for (i=0; i<PPC_NFPRS; i++) {
+		char tmpstr[5];
+		snprintf(tmpstr, sizeof(tmpstr), "f%i", i);
+		CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.fpr[i]);
+	}
+	for (i=0; i<16; i++) {
+		char tmpstr[5];
+		snprintf(tmpstr, sizeof(tmpstr), "sr%i", i);
+		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.ppc.sr[i]);
+	}
+
+	/*  Register the CPU as an interrupt handler:  */
+	{
+		struct interrupt templ;
+		char name[150];
+		snprintf(name, sizeof(name), "%s", cpu->path);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 0;
+		templ.name = name;
+		templ.extra = cpu;
+		templ.interrupt_assert = ppc_irq_interrupt_assert;
+		templ.interrupt_deassert = ppc_irq_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	if (cpu->is_32bit)
+		cpu->vaddr_mask = 0x00000000ffffffffULL;
+
+	return 1;
+}
+
+
+/*
+ *  ppc_cpu_list_available_types():
+ *
+ *  Print a list of available PPC CPU types.
+ */
+void ppc_cpu_list_available_types(void)
+{
+	int i, j;
+	struct ppc_cpu_type_def tdefs[] = PPC_CPU_TYPE_DEFS;
+
+	i = 0;
+	while (tdefs[i].name != NULL) {
+		debug("%s", tdefs[i].name);
+		for (j=10 - strlen(tdefs[i].name); j>0; j--)
+			debug(" ");
+		i++;
+		if ((i % 6) == 0 || tdefs[i].name == NULL)
+			debug("\n");
+	}
+}
+
+
+/*
+ *  ppc_cpu_dumpinfo():
+ */
+void ppc_cpu_dumpinfo(struct cpu *cpu, bool verbose)
+{
+	struct ppc_cpu_type_def *ct = &cpu->cd.ppc.cpu_type;
+	int l2kb = 0;
+	if (ct->l2cache_shift)
+		l2kb = (1 << ct->l2cache_shift) / 1024;
+
+	debugmsg(SUBSYS_MACHINE, "cpu", VERBOSITY_INFO,
+	    "%s (%i-bit, %s, I+D = %i+%i KB, L2 = %i %cB)",
+	    cpu->name,
+	    cpu->cd.ppc.bits,
+	    cpu->cd.ppc.mode == MODE_PPC ? "PPC" : "POWER",
+	    (1 << ct->icache_shift) / 1024,
+	    (1 << ct->dcache_shift) / 1024,
+	    l2kb >= 1024? l2kb / 1024 : l2kb,
+	    l2kb >= 1024? 'M' : 'K');
+}
+
+
+/*
+ *  reg_access_msr():
+ */
+void reg_access_msr(struct cpu *cpu, uint64_t *valuep, int writeflag,
+	int check_for_interrupts)
+{
+	uint64_t old = cpu->cd.ppc.msr;
+
+	if (valuep == NULL) {
+		fatal("reg_access_msr(): NULL\n");
+		return;
+	}
+
+	if (writeflag) {
+		cpu->cd.ppc.msr = *valuep;
+
+		/*  Switching between temporary and real gpr 0..3?  */
+		if ((old & PPC_MSR_TGPR) != (cpu->cd.ppc.msr & PPC_MSR_TGPR)) {
+			int i;
+			for (i=0; i<PPC_N_TGPRS; i++) {
+				uint64_t t = cpu->cd.ppc.gpr[i];
+				cpu->cd.ppc.gpr[i] = cpu->cd.ppc.tgpr[i];
+				cpu->cd.ppc.tgpr[i] = t;
+			}
+		}
+
+		if (cpu->cd.ppc.msr & PPC_MSR_IP) {
+			fatal("\n[ Reboot hack for NetBSD/prep. TODO: "
+			    "fix this. ]\n");
+			cpu->running = 0;
+		}
+	}
+
+	/*  TODO: Is the little-endian bit writable?  */
+
+	cpu->cd.ppc.msr &= ~PPC_MSR_LE;
+	if (cpu->byte_order != EMUL_BIG_ENDIAN)
+		cpu->cd.ppc.msr |= PPC_MSR_LE;
+
+	if (!writeflag)
+		*valuep = cpu->cd.ppc.msr;
+
+	if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) {
+		if (cpu->cd.ppc.dec_intr_pending &&
+		    !(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) {
+			ppc_exception(cpu, PPC_EXCEPTION_DEC);
+			cpu->cd.ppc.dec_intr_pending = 0;
+		} else if (cpu->cd.ppc.irq_asserted)
+			ppc_exception(cpu, PPC_EXCEPTION_EI);
+	}
+}
+
+
+/*
+ *  ppc_exception():
+ */
+void ppc_exception(struct cpu *cpu, int exception_nr)
+{
+	/*  Save PC and MSR:  */
+	cpu->cd.ppc.spr[SPR_SRR0] = cpu->pc;
+
+	if (exception_nr >= 0x10 && exception_nr <= 0x13)
+		cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0xffff)
+		    | (cpu->cd.ppc.cr & 0xf0000000);
+	else
+		cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff);
+
+	if (!quiet_mode)
+		fatal("[ PPC Exception 0x%x; pc=0x%" PRIx64" ]\n",
+		    exception_nr, cpu->pc);
+
+	/*  Disable External Interrupts, Recoverable Interrupt Mode,
+	    and go to Supervisor mode  */
+	cpu->cd.ppc.msr &= ~(PPC_MSR_EE | PPC_MSR_RI | PPC_MSR_PR);
+
+	cpu->pc = exception_nr * 0x100;
+	if (cpu->cd.ppc.msr & PPC_MSR_IP)
+		cpu->pc += 0xfff00000ULL;
+
+	if (cpu->is_32bit)
+		ppc32_pc_to_pointers(cpu);
+	else
+		ppc_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  ppc_cpu_register_dump():
+ *
+ *  Dump cpu registers in a relatively readable format.
+ *
+ *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
+ *  coprocs: if bit i is set, then we should dump registers from coproc i.
+ */
+void ppc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
+{
+	char *symbol;
+	uint64_t offset, tmp;
+	int i, x = cpu->cpu_id;
+	int bits32 = cpu->cd.ppc.bits == 32;
+
+	if (gprs) {
+		/*  Special registers (pc, ...) first:  */
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    cpu->pc, &offset);
+
+		debug("cpu%i: pc  = 0x", x);
+		if (bits32)
+			debug("%08" PRIx32, (uint32_t)cpu->pc);
+		else
+			debug("%016" PRIx64, (uint64_t)cpu->pc);
+		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
+
+		debug("cpu%i: lr  = 0x", x);
+		if (bits32)
+			debug("%08" PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]);
+		else
+			debug("%016" PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]);
+		debug("  cr  = 0x%08" PRIx32, (uint32_t)cpu->cd.ppc.cr);
+
+		if (bits32)
+			debug("  ");
+		else
+			debug("\ncpu%i: ", x);
+		debug("ctr = 0x", x);
+		if (bits32)
+			debug("%08" PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]);
+		else
+			debug("%016" PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]);
+
+		debug("  xer = 0x", x);
+		if (bits32)
+			debug("%08" PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]);
+		else
+			debug("%016" PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]);
+
+		debug("\n");
+
+		if (bits32) {
+			/*  32-bit:  */
+			for (i=0; i<PPC_NGPRS; i++) {
+				if ((i % 4) == 0)
+					debug("cpu%i:", x);
+				debug(" r%02i = 0x%08" PRIx32" ", i,
+				    (uint32_t) cpu->cd.ppc.gpr[i]);
+				if ((i % 4) == 3)
+					debug("\n");
+			}
+		} else {
+			/*  64-bit:  */
+			for (i=0; i<PPC_NGPRS; i++) {
+				int r = (i >> 1) + ((i & 1) << 4);
+				if ((i % 2) == 0)
+					debug("cpu%i:", x);
+				debug(" r%02i = 0x%016" PRIx64" ", r,
+				    (uint64_t) cpu->cd.ppc.gpr[r]);
+				if ((i % 2) == 1)
+					debug("\n");
+			}
+		}
+
+		/*  Other special registers:  */
+		if (bits32) {
+			debug("cpu%i: srr0 = 0x%08" PRIx32
+			    " srr1 = 0x%08" PRIx32"\n", x,
+			    (uint32_t) cpu->cd.ppc.spr[SPR_SRR0],
+			    (uint32_t) cpu->cd.ppc.spr[SPR_SRR1]);
+		} else {
+			debug("cpu%i: srr0 = 0x%016" PRIx64
+			    "  srr1 = 0x%016" PRIx64"\n", x,
+			    (uint64_t) cpu->cd.ppc.spr[SPR_SRR0],
+			    (uint64_t) cpu->cd.ppc.spr[SPR_SRR1]);
+		}
+
+		debug("cpu%i: msr = ", x);
+		reg_access_msr(cpu, &tmp, 0, 0);
+		if (bits32)
+			debug("0x%08" PRIx32, (uint32_t) tmp);
+		else
+			debug("0x%016" PRIx64, (uint64_t) tmp);
+
+		debug("  tb  = 0x%08" PRIx32"%08" PRIx32"\n",
+		    (uint32_t) cpu->cd.ppc.spr[SPR_TBU],
+		    (uint32_t) cpu->cd.ppc.spr[SPR_TBL]);
+
+		debug("cpu%i: dec = 0x%08" PRIx32,
+		    x, (uint32_t) cpu->cd.ppc.spr[SPR_DEC]);
+		if (!bits32)
+			debug("  hdec = 0x%08" PRIx32"\n",
+			    (uint32_t) cpu->cd.ppc.spr[SPR_HDEC]);
+
+		debug("\n");
+	}
+
+	if (coprocs & 1) {
+		debug("cpu%i: fpscr = 0x%08" PRIx32"\n",
+		    x, (uint32_t) cpu->cd.ppc.fpscr);
+
+		/*  TODO: show floating-point values :-)  */
+
+		/*  TODO: 32-bit fprs on 32-bit PPC cpus?  */
+
+		for (i=0; i<PPC_NFPRS; i++) {
+			if ((i % 2) == 0)
+				debug("cpu%i:", x);
+			debug(" f%02i = 0x%016" PRIx64" ", i,
+			    (uint64_t) cpu->cd.ppc.fpr[i]);
+			if ((i % 2) == 1)
+				debug("\n");
+		}
+	}
+
+	if (coprocs & 2) {
+		debug("cpu%i:  sdr1 = 0x%" PRIx64"\n", x,
+		    (uint64_t) cpu->cd.ppc.spr[SPR_SDR1]);
+		if (cpu->cd.ppc.cpu_type.flags & PPC_601)
+			debug("cpu%i:  PPC601-style, TODO!\n");
+		else {
+			for (i=0; i<8; i++) {
+				int spr = SPR_IBAT0U + i*2;
+				uint32_t upper = cpu->cd.ppc.spr[spr];
+				uint32_t lower = cpu->cd.ppc.spr[spr+1];
+				uint32_t len = (((upper & BAT_BL) << 15)
+				    | 0x1ffff) + 1;
+				debug("cpu%i:  %sbat%i: u=0x%08" PRIx32
+				    " l=0x%08" PRIx32" ",
+				    x, i<4? "i" : "d", i&3, upper, lower);
+				if (!(upper & BAT_V)) {
+					debug(" (not valid)\n");
+					continue;
+				}
+				if (len < 1048576)
+					debug(" (%i KB, ", len >> 10);
+				else
+					debug(" (%i MB, ", len >> 20);
+				if (upper & BAT_Vu)
+					debug("user, ");
+				if (upper & BAT_Vs)
+					debug("supervisor, ");
+				if (lower & (BAT_W | BAT_I | BAT_M | BAT_G))
+					debug("%s%s%s%s, ",
+					    lower & BAT_W? "W" : "",
+					    lower & BAT_I? "I" : "",
+					    lower & BAT_M? "M" : "",
+					    lower & BAT_G? "G" : "");
+				switch (lower & BAT_PP) {
+				case BAT_PP_NONE: debug("NO access"); break;
+				case BAT_PP_RO_S: debug("read-only, soft");
+					          break;
+				case BAT_PP_RO:   debug("read-only"); break;
+				case BAT_PP_RW:   debug("read/write"); break;
+				}
+				debug(")\n");
+			}
+		}
+	}
+
+	if (coprocs & 4) {
+		for (i=0; i<16; i++) {
+			uint32_t s = cpu->cd.ppc.sr[i];
+
+			debug("cpu%i:", x);
+			debug("  sr%-2i = 0x%08" PRIx32, i, s);
+
+			s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC);
+			if (s != 0) {
+				debug("  (");
+				if (s & SR_TYPE) {
+					debug("NON-memory type");
+					s &= ~SR_TYPE;
+					if (s != 0)
+						debug(", ");
+				}
+				if (s & SR_SUKEY) {
+					debug("supervisor-key");
+					s &= ~SR_SUKEY;
+					if (s != 0)
+						debug(", ");
+				}
+				if (s & SR_PRKEY) {
+					debug("user-key");
+					s &= ~SR_PRKEY;
+					if (s != 0)
+						debug(", ");
+				}
+				if (s & SR_NOEXEC)
+					debug("NOEXEC");
+				debug(")");
+			}
+			debug("\n");
+		}
+	}
+}
+
+
+/*
+ *  ppc_cpu_tlbdump():
+ *
+ *  Not currently used for PPC.
+ */
+void ppc_cpu_tlbdump(struct cpu* cpu, int rawflag)
+{
+}
+
+
+/*
+ *  ppc_irq_interrupt_assert():
+ */
+void ppc_irq_interrupt_assert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.ppc.irq_asserted = 1;
+}
+
+
+/*
+ *  ppc_irq_interrupt_deassert():
+ */
+void ppc_irq_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.ppc.irq_asserted = 0;
+}
+
+
+/*
+ *  ppc_cpu_disassemble_instr():
+ *
+ *  Convert an instruction word into human readable format, for instruction
+ *  tracing.
+ *
+ *  If running is 1, cpu->pc should be the address of the instruction.
+ *
+ *  If running is 0, things that depend on the runtime environment (eg.
+ *  register contents) will not be shown, and addr will be used instead of
+ *  cpu->pc for relative addresses.
+ */
+int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
+	int running, uint64_t dumpaddr)
+{
+	int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit; //, oe_bit;
+	int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg;
+	int bfa, to, load, wlen, no_rb = 0;
+	uint64_t offset, addr;
+	uint32_t iword;
+	const char *symbol, *mnem = "ERROR";
+	int power = cpu->cd.ppc.mode == MODE_POWER;
+
+	if (running)
+		dumpaddr = cpu->pc;
+
+	symbol = get_symbol_name(&cpu->machine->symbol_context,
+	    dumpaddr, &offset);
+	if (symbol != NULL && offset==0)
+		debug("<%s>\n", symbol);
+
+	if (cpu->machine->ncpus > 1 && running)
+		debug("cpu%i: ", cpu->cpu_id);
+
+	if (cpu->cd.ppc.bits == 32)
+		debug("%08" PRIx32, (uint32_t) dumpaddr);
+	else
+		debug("%016" PRIx64, (uint64_t) dumpaddr);
+
+	/*  NOTE: Fixed to big-endian.  */
+	iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8)
+	    + instr[3];
+
+	debug(": %08" PRIx32, iword);
+
+	cpu_print_pc_indicator_in_disassembly(cpu, running, dumpaddr);
+
+
+	/*
+	 *  Decode the instruction:
+	 */
+
+	hi6 = iword >> 26;
+
+	switch (hi6) {
+	case 0x4:
+		debug("ALTIVEC TODO");
+		/*  vxor etc  */
+		break;
+	case PPC_HI6_MULLI:
+	case PPC_HI6_SUBFIC:
+		rt = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		imm = (int16_t)(iword & 0xffff);
+		switch (hi6) {
+		case PPC_HI6_MULLI:
+			mnem = power? "muli":"mulli";
+			break;
+		case PPC_HI6_SUBFIC:
+			mnem = power? "sfi":"subfic";
+			break;
+		}
+		debug("%s\tr%i,r%i,%i", mnem, rt, ra, imm);
+		break;
+	case PPC_HI6_CMPLI:
+	case PPC_HI6_CMPI:
+		bf = (iword >> 23) & 7;
+		l_bit = (iword >> 21) & 1;
+		ra = (iword >> 16) & 31;
+		if (hi6 == PPC_HI6_CMPLI) {
+			imm = iword & 0xffff;
+			mnem = "cmpl";
+		} else {
+			imm = (int16_t)(iword & 0xffff);
+			mnem = "cmp";
+		}
+		debug("%s%si\t", mnem, l_bit? "d" : "w");
+		if (bf != 0)
+			debug("cr%i,", bf);
+		debug("r%i,%i", ra, imm);
+		break;
+	case PPC_HI6_ADDIC:
+	case PPC_HI6_ADDIC_DOT:
+		rt = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		rc = hi6 == PPC_HI6_ADDIC_DOT;
+		imm = (int16_t)(iword & 0xffff);
+		mnem = power? "ai":"addic";
+		if (imm < 0 && !power) {
+			mnem = "subic";
+			imm = -imm;
+		}
+		debug("%s%s\tr%i,r%i,%i", mnem, rc?".":"", rt, ra, imm);
+		break;
+	case PPC_HI6_ADDI:
+		rt = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		imm = (int16_t)(iword & 0xffff);
+		if (ra == 0)
+			debug("li\tr%i,%i", rt, imm);
+		else {
+			mnem = power? "cal":"addi";
+			if (imm < 0 && !power) {
+				mnem = "subi";
+				imm = -imm;
+			}
+			debug("%s\tr%i,r%i,%i", mnem, rt, ra, imm);
+		}
+		break;
+	case PPC_HI6_ADDIS:
+		rt = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		imm = (int16_t)(iword & 0xffff);
+		if (ra == 0)
+			debug("lis\tr%i,%i", rt, imm);
+		else
+			debug("%s\tr%i,r%i,%i",
+			    power? "cau":"addis", rt, ra, imm);
+		break;
+	case PPC_HI6_BC:
+		aa_bit = (iword & 2) >> 1;
+		lk_bit = iword & 1;
+		bo = (iword >> 21) & 31;
+		bi = (iword >> 16) & 31;
+		/*  Sign-extend addr:  */
+		addr = (int64_t)(int16_t)(iword & 0xfffc);
+		debug("bc");
+		if (lk_bit)
+			debug("l");
+		if (aa_bit)
+			debug("a");
+		else
+			addr += dumpaddr;
+		debug("\t%i,%i,", bo, bi);
+		if (cpu->cd.ppc.bits == 32)
+			addr &= 0xffffffff;
+		if (cpu->cd.ppc.bits == 32)
+			debug("0x%" PRIx32, (uint32_t) addr);
+		else
+			debug("0x%" PRIx64, (uint64_t) addr);
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    addr, &offset);
+		if (symbol != NULL)
+			debug("\t<%s>", symbol);
+		break;
+	case PPC_HI6_SC:
+		lev = (iword >> 5) & 0x7f;
+		debug("sc");
+		if (lev != 0) {
+			debug("\t%i", lev);
+			if (lev > 1)
+				debug(" (WARNING! reserved value)");
+		}
+		break;
+	case PPC_HI6_B:
+		aa_bit = (iword & 2) >> 1;
+		lk_bit = iword & 1;
+		/*  Sign-extend addr:  */
+		addr = (int64_t)(int32_t)((iword & 0x03fffffc) << 6);
+		addr = (int64_t)addr >> 6;
+		debug("b");
+		if (lk_bit)
+			debug("l");
+		if (aa_bit)
+			debug("a");
+		else
+			addr += dumpaddr;
+		if (cpu->cd.ppc.bits == 32)
+			addr &= 0xffffffff;
+		if (cpu->cd.ppc.bits == 32)
+			debug("\t0x%" PRIx32, (uint32_t) addr);
+		else
+			debug("\t0x%" PRIx64, (uint64_t) addr);
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    addr, &offset);
+		if (symbol != NULL)
+			debug("\t<%s>", symbol);
+		break;
+	case PPC_HI6_19:
+		xo = (iword >> 1) & 1023;
+		switch (xo) {
+		case PPC_19_MCRF:
+			bf = (iword >> 23) & 7;
+			bfa = (iword >> 18) & 7;
+			debug("mcrf\tcr%i,cr%i", bf, bfa);
+			break;
+		case PPC_19_RFI:
+			debug("rfi");
+			break;
+		case PPC_19_RFID:
+			debug("rfid");
+			break;
+		case PPC_19_RFSVC:
+			debug("rfsvc%s", power?"":"\t(INVALID for PowerPC)");
+			break;
+		case PPC_19_BCLR:
+		case PPC_19_BCCTR:
+			bo = (iword >> 21) & 31;
+			bi = (iword >> 16) & 31;
+			bh = (iword >> 11) & 3;
+			lk_bit = iword & 1;
+			switch (xo) {
+			case PPC_19_BCLR:
+				mnem = power? "bcr" : "bclr"; break;
+			case PPC_19_BCCTR:
+				mnem = power? "bcc" : "bcctr"; break;
+			}
+			debug("%s%s%s\t%i,%i,%i", mnem, lk_bit? "l" : "",
+			    bh? (bh==3? "+" : (bh==2? "-" : "?")) : "",
+			    bo, bi, bh);
+			break;
+		case PPC_19_ISYNC:
+			debug("%s", power? "ics" : "isync");
+			break;
+		case PPC_19_CRAND:
+		case PPC_19_CRXOR:
+		case PPC_19_CROR:
+		case PPC_19_CRNAND:
+		case PPC_19_CRNOR:
+		case PPC_19_CRANDC:
+		case PPC_19_CREQV:
+		case PPC_19_CRORC:
+			bt = (iword >> 21) & 31;
+			ba = (iword >> 16) & 31;
+			bb = (iword >> 11) & 31;
+			switch (xo) {
+			case PPC_19_CRAND:	mnem = "crand"; break;
+			case PPC_19_CRXOR:	mnem = "crxor"; break;
+			case PPC_19_CROR:	mnem = "cror"; break;
+			case PPC_19_CRNAND:	mnem = "crnand"; break;
+			case PPC_19_CRNOR:	mnem = "crnor"; break;
+			case PPC_19_CRANDC:	mnem = "crandc"; break;
+			case PPC_19_CREQV:	mnem = "creqv"; break;
+			case PPC_19_CRORC:	mnem = "crorc"; break;
+			}
+			debug("%s\t%i,%i,%i", mnem, bt, ba, bb);
+			break;
+		default:
+			debug("unimplemented hi6_19, xo = 0x%x", xo);
+		}
+		break;
+	case PPC_HI6_RLWNM:
+	case PPC_HI6_RLWIMI:
+	case PPC_HI6_RLWINM:
+		rs = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		sh = (iword >> 11) & 31;	/*  actually rb for rlwnm  */
+		mb = (iword >> 6) & 31;
+		me = (iword >> 1) & 31;
+		rc = iword & 1;
+		switch (hi6) {
+		case PPC_HI6_RLWNM:
+			mnem = power? "rlnm" : "rlwnm"; break;
+		case PPC_HI6_RLWIMI:
+			mnem = power? "rlimi" : "rlwimi"; break;
+		case PPC_HI6_RLWINM:
+			mnem = power? "rlinm" : "rlwinm"; break;
+		}
+		debug("%s%s\tr%i,r%i,%s%i,%i,%i",
+		    mnem, rc?".":"", ra, rs,
+		    hi6 == PPC_HI6_RLWNM? "r" : "",
+		    sh, mb, me);
+		break;
+	case PPC_HI6_ORI:
+	case PPC_HI6_ORIS:
+	case PPC_HI6_XORI:
+	case PPC_HI6_XORIS:
+	case PPC_HI6_ANDI_DOT:
+	case PPC_HI6_ANDIS_DOT:
+		rs = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		imm = iword & 0xffff;
+		switch (hi6) {
+		case PPC_HI6_ORI:
+			mnem = power? "oril":"ori";
+			break;
+		case PPC_HI6_ORIS:
+			mnem = power? "oriu":"oris";
+			break;
+		case PPC_HI6_XORI:
+			mnem = power? "xoril":"xori";
+			break;
+		case PPC_HI6_XORIS:
+			mnem = power? "xoriu":"xoris";
+			break;
+		case PPC_HI6_ANDI_DOT:
+			mnem = power? "andil.":"andi.";
+			break;
+		case PPC_HI6_ANDIS_DOT:
+			mnem = power? "andiu.":"andis.";
+			break;
+		}
+		if (hi6 == PPC_HI6_ORI && rs == 0 && ra == 0 && imm == 0)
+			debug("nop");
+		else
+			debug("%s\tr%i,r%i,0x%04x", mnem, ra, rs, imm);
+		break;
+	case PPC_HI6_30:
+		xo = (iword >> 2) & 7;
+		switch (xo) {
+		case PPC_30_RLDICL:
+		case PPC_30_RLDICR:
+		case PPC_30_RLDIMI:	/*  mb, not me  */
+			mnem = NULL;
+			switch (xo) {
+			case PPC_30_RLDICL: mnem = "rldicl"; break;
+			case PPC_30_RLDICR: mnem = "rldicr"; break;
+			case PPC_30_RLDIMI: mnem = "rldimi"; break;
+			}
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			sh = ((iword >> 11) & 31) | ((iword & 2) << 4);
+			me = ((iword >> 6) & 31) | (iword & 0x20);
+			rc = iword & 1;
+			debug("%s%s\tr%i,r%i,%i,%i",
+			    mnem, rc?".":"", ra, rs, sh, me);
+			break;
+		default:
+			debug("unimplemented hi6_30, xo = 0x%x", xo);
+		}
+		break;
+	case PPC_HI6_31:
+		xo = (iword >> 1) & 1023;
+		switch (xo) {
+
+		case PPC_31_CMP:
+		case PPC_31_CMPL:
+			bf = (iword >> 23) & 7;
+			l_bit = (iword >> 21) & 1;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			if (xo == PPC_31_CMPL)
+				mnem = "cmpl";
+			else
+				mnem = "cmp";
+			debug("%s%s\t", mnem, l_bit? "d" : "w");
+			if (bf != 0)
+				debug("cr%i,", bf);
+			debug("r%i,r%i", ra, rb);
+			break;
+		case PPC_31_MFCR:
+			rt = (iword >> 21) & 31;
+			debug("mfcr\tr%i", rt);
+			break;
+		case PPC_31_MFMSR:
+			rt = (iword >> 21) & 31;
+			debug("mfmsr\tr%i", rt);
+			break;
+		case PPC_31_MTCRF:
+			rs = (iword >> 21) & 31;
+			mb = (iword >> 12) & 255;  /*  actually fxm, not mb  */
+			debug("mtcrf\t%i,r%i", mb, rs);
+			break;
+		case PPC_31_MTMSR:
+			rs = (iword >> 21) & 31;
+			l_bit = (iword >> 16) & 1;
+			debug("mtmsr\tr%i", rs);
+			if (l_bit)
+				debug(",%i", l_bit);
+			break;
+		case PPC_31_TW:
+		case PPC_31_TD:
+			to = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			switch (xo) {
+			case PPC_31_TW: mnem = power? "t" : "tw"; break;
+			case PPC_31_TD: mnem = "td"; break;
+			}
+			debug("%s\t%i,r%i,r%i", mnem, to, ra, rb);
+			break;
+		case PPC_31_LWARX:
+		case PPC_31_LDARX:
+		case PPC_31_LBZX:
+		case PPC_31_LBZUX:
+		case PPC_31_LHAX:
+		case PPC_31_LHAUX:
+		case PPC_31_LHZX:
+		case PPC_31_LHZUX:
+		case PPC_31_LWZX:
+		case PPC_31_LWZUX:
+		case PPC_31_LHBRX:
+		case PPC_31_LWBRX:
+		case PPC_31_LFDX:
+		case PPC_31_LFSX:
+		case PPC_31_STWCX_DOT:
+		case PPC_31_STDCX_DOT:
+		case PPC_31_STBX:
+		case PPC_31_STBUX:
+		case PPC_31_STHX:
+		case PPC_31_STHUX:
+		case PPC_31_STWX:
+		case PPC_31_STWUX:
+		case PPC_31_STDX:
+		case PPC_31_STDUX:
+		case PPC_31_STHBRX:
+		case PPC_31_STWBRX:
+		case PPC_31_STFDX:
+		case PPC_31_STFSX:
+			/*  rs for stores, rt for loads, actually  */
+			load = 0; wlen = 0; fpreg = 0;
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			switch (xo) {
+			case PPC_31_LWARX: wlen=4;load=1; mnem = "lwarx"; break;
+			case PPC_31_LDARX: wlen=8;load=1; mnem = "ldarx"; break;
+			case PPC_31_LBZX:  wlen=1;load=1; mnem = "lbzx"; break;
+			case PPC_31_LBZUX: wlen=1;load=1; mnem = "lbzux"; break;
+			case PPC_31_LHAX:  wlen=2;load=1; mnem = "lhax"; break;
+			case PPC_31_LHAUX: wlen=2;load=1; mnem = "lhaux"; break;
+			case PPC_31_LHZX:  wlen=2;load=1; mnem = "lhzx"; break;
+			case PPC_31_LHZUX: wlen=2;load=1; mnem = "lhzux"; break;
+			case PPC_31_LWZX:  wlen = 4; load = 1;
+				mnem = power? "lx" : "lwzx";
+				break;
+			case PPC_31_LWZUX: wlen = 4; load = 1;
+				mnem = power? "lux":"lwzux";
+				break;
+			case PPC_31_LFDX: fpreg = 1; wlen = 8; load = 1;
+				mnem = "lfdx"; break;
+			case PPC_31_LFSX: fpreg = 1; wlen = 4; load = 1;
+				mnem = "lfsx"; break;
+			case PPC_31_STWCX_DOT: wlen=4; mnem = "stwcx."; break;
+			case PPC_31_STDCX_DOT: wlen=8; mnem = "stdcx."; break;
+			case PPC_31_STBX:  wlen=1; mnem = "stbx"; break;
+			case PPC_31_STBUX: wlen=1; mnem = "stbux"; break;
+			case PPC_31_STHX:  wlen=2; mnem = "sthx"; break;
+			case PPC_31_STHUX: wlen=2; mnem = "sthux"; break;
+			case PPC_31_STWX:
+				wlen = 4; mnem = power? "stx" : "stwx";
+				break;
+			case PPC_31_STWUX:
+				wlen = 4; mnem = power? "stux" : "stwux";
+				break;
+			case PPC_31_STDX:  wlen = 8; mnem = "stdx"; break;
+			case PPC_31_STDUX: wlen = 8; mnem = "stdux"; break;
+			case PPC_31_LHBRX:  wlen = 2; mnem = "lhbrx"; break;
+			case PPC_31_LWBRX:  wlen = 4; mnem = power?
+					    "lbrx" : "lwbrx"; break;
+			case PPC_31_STHBRX: wlen = 2; mnem = "sthbrx"; break;
+			case PPC_31_STWBRX: wlen = 4; mnem = power?
+					    "stbrx" : "stwbrx"; break;
+			case PPC_31_STFDX: fpreg = 1; wlen = 8;
+				mnem = "stfdx"; break;
+			case PPC_31_STFSX: fpreg = 1; wlen = 4;
+				mnem = "stfsx"; break;
+			}
+			debug("%s\t%s%i,r%i,r%i", mnem,
+			    fpreg? "f" : "r", rs, ra, rb);
+			if (!running)
+				break;
+			addr = (ra==0? 0 : cpu->cd.ppc.gpr[ra]) +
+			    cpu->cd.ppc.gpr[rb];
+			if (cpu->cd.ppc.bits == 32)
+				addr &= 0xffffffff;
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    addr, &offset);
+			if (symbol != NULL)
+				debug(" \t<%s", symbol);
+			else
+				debug(" \t<0x%" PRIx64, (uint64_t) addr);
+			if (wlen > 0 && !fpreg /* && !reverse */) {
+				/*  TODO  */
+			}
+			debug(">");
+			break;
+		case PPC_31_NEG:
+		case PPC_31_NEGO:
+			rt = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			// oe_bit = (iword >> 10) & 1;
+			rc = iword & 1;
+			switch (xo) {
+			case PPC_31_NEG:  mnem = "neg"; break;
+			case PPC_31_NEGO: mnem = "nego"; break;
+			}
+			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra);
+			break;
+		case PPC_31_WRTEEI:
+			debug("wrteei\t%i", iword & 0x8000? 1 : 0);
+			break;
+		case PPC_31_MTMSRD:
+			/*  TODO: Just a guess based on MTMSR  */
+			rs = (iword >> 21) & 31;
+			l_bit = (iword >> 16) & 1;
+			debug("mtmsrd\tr%i", rs);
+			if (l_bit)
+				debug(",%i", l_bit);
+			break;
+		case PPC_31_ADDZE:
+		case PPC_31_ADDZEO:
+			rt = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			// oe_bit = (iword >> 10) & 1;
+			rc = iword & 1;
+			switch (xo) {
+			case PPC_31_ADDZE:
+				mnem = power? "aze" : "addze";
+				break;
+			case PPC_31_ADDZEO:
+				mnem = power? "azeo" : "addzeo";
+				break;
+			}
+			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra);
+			break;
+		case PPC_31_MTSR:
+		case PPC_31_MFSR:
+			/*  Move to/from segment register  */
+			rt = (iword >> 21) & 31;
+			ra = (iword >> 16) & 15;	/*  actually: sr  */
+			switch (xo) {
+			case PPC_31_MTSR:  mnem = "mtsr"; break;
+			case PPC_31_MFSR:  mnem = "mfsr"; break;
+			}
+			debug("%s\tr%i,%i", mnem, rt, ra);
+			break;
+		case PPC_31_MTSRIN:
+		case PPC_31_MFSRIN:
+			/*  Move to/from segment register indirect  */
+			rt = (iword >> 21) & 31;
+			rb = (iword >> 11) & 31;
+			switch (xo) {
+			case PPC_31_MTSRIN:  mnem = "mtsrin"; break;
+			case PPC_31_MFSRIN:  mnem = "mfsrin"; break;
+			}
+			debug("%s\tr%i,r%i", mnem, rt, rb);
+			break;
+		case PPC_31_ADDC:
+		case PPC_31_ADDCO:
+		case PPC_31_ADDE:
+		case PPC_31_ADDEO:
+		case PPC_31_ADDME:
+		case PPC_31_ADDMEO:
+		case PPC_31_ADD:
+		case PPC_31_ADDO:
+		case PPC_31_MULHW:
+		case PPC_31_MULHWU:
+		case PPC_31_MULLW:
+		case PPC_31_MULLWO:
+		case PPC_31_SUBF:
+		case PPC_31_SUBFO:
+		case PPC_31_SUBFC:
+		case PPC_31_SUBFCO:
+		case PPC_31_SUBFE:
+		case PPC_31_SUBFEO:
+		case PPC_31_SUBFME:
+		case PPC_31_SUBFMEO:
+		case PPC_31_SUBFZE:
+		case PPC_31_SUBFZEO:
+			rt = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			// oe_bit = (iword >> 10) & 1;
+			rc = iword & 1;
+			switch (xo) {
+			case PPC_31_ADDC:
+				mnem = power? "a" : "addc";
+				break;
+			case PPC_31_ADDCO:
+				mnem = power? "ao" : "addco";
+				break;
+			case PPC_31_ADDE:
+				mnem = power? "ae" : "adde";
+				break;
+			case PPC_31_ADDEO:
+				mnem = power? "aeo" : "addeo";
+				break;
+			case PPC_31_ADDME:
+				mnem = power? "ame" : "addme";
+				no_rb = 1;
+				break;
+			case PPC_31_ADDMEO:
+				mnem = power? "ameo" : "addmeo";
+				no_rb = 1;
+				break;
+			case PPC_31_ADD:
+				mnem = power? "cax" : "add";
+				break;
+			case PPC_31_ADDO:
+				mnem = power? "caxo" : "addo";
+				break;
+			case PPC_31_MULHW:  mnem = "mulhw"; break;
+			case PPC_31_MULHWU: mnem = "mulhwu"; break;
+			case PPC_31_MULLW:
+				mnem = power? "muls" : "mullw";
+				break;
+			case PPC_31_MULLWO:
+				mnem = power? "mulso" : "mullwo";
+				break;
+			case PPC_31_SUBF:   mnem = "subf"; break;
+			case PPC_31_SUBFO:  mnem = "subfo"; break;
+			case PPC_31_SUBFC:
+				mnem = power? "sf" : "subfc"; break;
+			case PPC_31_SUBFCO:
+				mnem = power? "sfo" : "subfco"; break;
+			case PPC_31_SUBFE:
+				mnem = power? "sfe" : "subfe"; break;
+			case PPC_31_SUBFEO:
+				mnem = power? "sfeo" : "subfeo"; break;
+			case PPC_31_SUBFME:
+				mnem = power? "sfme" : "subfme"; break;
+			case PPC_31_SUBFMEO:
+				mnem = power? "sfmeo" : "subfmeo"; break;
+			case PPC_31_SUBFZE:
+				mnem = power? "sfze" : "subfze";
+				no_rb = 1;
+				break;
+			case PPC_31_SUBFZEO:
+				mnem = power? "sfzeo" : "subfzeo";
+				no_rb = 1;
+				break;
+			}
+			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra);
+			if (!no_rb)
+				debug(",r%i", rb);
+			break;
+		case PPC_31_MFSPR:
+			rt = (iword >> 21) & 31;
+			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
+			switch (spr) {
+			/*  Some very common ones:  */
+			case 8:	   debug("mflr\tr%i", rt); break;
+			case 9:	   debug("mfctr\tr%i", rt); break;
+			default:debug("mfspr\tr%i,spr%i", rt, spr);
+			}
+			if (spr == 8 || spr == 9)
+				debug("\t");
+			debug("\t<%s%s", running? "read from " : "",
+			    ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]);
+			if (running) {
+				if (cpu->cd.ppc.bits == 32)
+					debug(": 0x%" PRIx32, (uint32_t)
+					    cpu->cd.ppc.spr[spr]);
+				else
+					debug(": 0x%" PRIx64, (uint64_t)
+					    cpu->cd.ppc.spr[spr]);
+			}
+			debug(">");
+			break;
+		case PPC_31_TLBIA:
+			debug("tlbia");
+			break;
+		case PPC_31_SLBIA:
+			debug("slbia");
+			break;
+		case PPC_31_TLBLD:
+		case PPC_31_TLBLI:
+			rb = (iword >> 11) & 31;
+			debug("tlbl%s\tr%i", xo == PPC_31_TLBLD? "d" : "i", rb);
+			break;
+		case PPC_31_TLBIE:
+			/*  TODO: what is ra? The IBM online docs didn't say  */
+			ra = 0;
+			rb = (iword >> 11) & 31;
+			if (power)
+				debug("tlbi\tr%i,r%i", ra, rb);
+			else
+				debug("tlbie\tr%i", rb);
+			break;
+		case PPC_31_TLBSX_DOT:
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			debug("tlbsx.\tr%i,r%i,r%i", rs, ra, rb);
+			break;
+		case PPC_31_TLBSYNC:
+			debug("tlbsync");
+			break;
+		case PPC_31_MFTB:
+			rt = (iword >> 21) & 31;
+			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
+			debug("mftb%s\tr%i", spr==268? "" :
+			    (spr==269? "u" : "?"), rt);
+			break;
+		case PPC_31_CNTLZW:
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rc = iword & 1;
+			mnem = power? "cntlz" : "cntlzw";
+			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs);
+			break;
+		case PPC_31_CLF:	/*  POWER only  */
+		case PPC_31_CLI:	/*  POWER only  */
+		case PPC_31_DCLST:	/*  POWER only  */
+		case PPC_31_DCBF:	/*  PowerPC only  */
+		case PPC_31_DCBI:	/*  PowerPC only  */
+		case PPC_31_DCBST:	/*  PowerPC only  */
+		case PPC_31_DCBTST:	/*  PowerPC only  */
+		case PPC_31_DCBT:	/*  PowerPC only  */
+		case PPC_31_ICBI:	/*  PowerPC only  */
+		case PPC_31_DCBZ:	/*  POWER/PowerPC  */
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			switch (xo) {
+			case PPC_31_CLF:   mnem = "clf"; break;
+			case PPC_31_CLI:   mnem = "cli"; break;
+			case PPC_31_DCLST: mnem = "dclst"; break;
+			case PPC_31_DCBF:  mnem = "dcbf"; break;
+			case PPC_31_DCBI:  mnem = "dcbi"; break;
+			case PPC_31_DCBST: mnem = "dcbst"; break;
+			case PPC_31_DCBTST:mnem = "dcbtst"; break;
+			case PPC_31_DCBT:  mnem = "dcbt"; break;
+			case PPC_31_ICBI:  mnem = "icbi"; break;
+			case PPC_31_DCBZ:  mnem = power ?
+					   "dclz" : "dcbz"; break;
+			}
+			debug("%s\tr%i,r%i", mnem, ra, rb);
+			break;
+		case PPC_31_SLW:
+		case PPC_31_SLD:
+		case PPC_31_SRAW:
+		case PPC_31_SRW:
+		case PPC_31_AND:
+		case PPC_31_ANDC:
+		case PPC_31_NOR:
+		case PPC_31_EQV:
+		case PPC_31_OR:
+		case PPC_31_ORC:
+		case PPC_31_XOR:
+		case PPC_31_NAND:
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			rc = iword & 1;
+			if (rs == rb && xo == PPC_31_OR)
+				debug("mr%s\tr%i,r%i", rc? "." : "", ra, rs);
+			else {
+				switch (xo) {
+				case PPC_31_SLW:  mnem =
+					power? "sl" : "slw"; break;
+				case PPC_31_SLD:  mnem = "sld"; break;
+				case PPC_31_SRAW:  mnem =
+					power? "sra" : "sraw"; break;
+				case PPC_31_SRW:  mnem =
+					power? "sr" : "srw"; break;
+				case PPC_31_AND:  mnem = "and"; break;
+				case PPC_31_NAND: mnem = "nand"; break;
+				case PPC_31_ANDC: mnem = "andc"; break;
+				case PPC_31_NOR:  mnem = "nor"; break;
+				case PPC_31_EQV:  mnem = "eqv"; break;
+				case PPC_31_OR:   mnem = "or"; break;
+				case PPC_31_ORC:  mnem = "orc"; break;
+				case PPC_31_XOR:  mnem = "xor"; break;
+				}
+				debug("%s%s\tr%i,r%i,r%i", mnem,
+				    rc? "." : "", ra, rs, rb);
+			}
+			break;
+		case PPC_31_DCCCI:
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			debug("dccci\tr%i,r%i", ra, rb);
+			break;
+		case PPC_31_ICCCI:
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			debug("iccci\tr%i,r%i", ra, rb);
+			break;
+		case PPC_31_DIVW:
+		case PPC_31_DIVWO:
+		case PPC_31_DIVWU:
+		case PPC_31_DIVWUO:
+			rt = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			// oe_bit = (iword >> 10) & 1;
+			rc = iword & 1;
+			switch (xo) {
+			case PPC_31_DIVWU:  mnem = "divwu"; break;
+			case PPC_31_DIVWUO: mnem = "divwuo"; break;
+			case PPC_31_DIVW:   mnem = "divw"; break;
+			case PPC_31_DIVWO:  mnem = "divwo"; break;
+			}
+			debug("%s%s\tr%i,r%i,r%i", mnem, rc? "." : "",
+			    rt, ra, rb);
+			break;
+		case PPC_31_MTSPR:
+			rs = (iword >> 21) & 31;
+			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
+			switch (spr) {
+			/*  Some very common ones:  */
+			case 8:	   debug("mtlr\tr%i", rs); break;
+			case 9:	   debug("mtctr\tr%i", rs); break;
+			default:debug("mtspr\tspr%i,r%i", spr, rs);
+			}
+			if (spr == 8 || spr == 9)
+				debug("\t");
+			debug("\t<%s%s", running? "write to " : "",
+			    ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]);
+			if (running) {
+				if (cpu->cd.ppc.bits == 32)
+					debug(": 0x%" PRIx32, (uint32_t)
+					    cpu->cd.ppc.gpr[rs]);
+				else
+					debug(": 0x%" PRIx64, (uint64_t)
+					    cpu->cd.ppc.gpr[rs]);
+			}
+			debug(">");
+			break;
+		case PPC_31_SYNC:
+			debug("%s", power? "dcs" : "sync");
+			break;
+		case PPC_31_LSWI:
+		case PPC_31_STSWI:
+			rs = (iword >> 21) & 31;	/*  lwsi uses rt  */
+			ra = (iword >> 16) & 31;
+			nb = (iword >> 11) & 31;
+			switch (xo) {
+			case PPC_31_LSWI:
+				mnem = power? "lsi" : "lswi"; break;
+			case PPC_31_STSWI:
+				mnem = power? "stsi" : "stswi"; break;
+			}
+			debug("%s\tr%i,r%i,%i", mnem, rs, ra, nb);
+			break;
+		case PPC_31_SRAWI:
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			sh = (iword >> 11) & 31;
+			rc = iword & 1;
+			mnem = power? "srai" : "srawi";
+			debug("%s%s\tr%i,r%i,%i", mnem,
+			    rc? "." : "", ra, rs, sh);
+			break;
+		case PPC_31_DSSALL:
+			debug("dssall");
+			break;
+		case PPC_31_EIEIO:
+			debug("%s", power? "eieio?" : "eieio");
+			break;
+		case PPC_31_EXTSB:
+		case PPC_31_EXTSH:
+		case PPC_31_EXTSW:
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rc = iword & 1;
+			switch (xo) {
+			case PPC_31_EXTSB:
+				mnem = power? "exts" : "extsb";
+				break;
+			case PPC_31_EXTSH:
+				mnem = "extsh";
+				break;
+			case PPC_31_EXTSW:
+				mnem = "extsw";
+				break;
+			}
+			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs);
+			break;
+		case PPC_31_LVX:
+		case PPC_31_LVXL:
+		case PPC_31_STVX:
+		case PPC_31_STVXL:
+			rs = (iword >> 21) & 31;	/*  vs for stores,  */
+			ra = (iword >> 16) & 31;	/*  rs=vl for loads  */
+			rb = (iword >> 11) & 31;
+			rc = iword & 1;
+			switch (xo) {
+			case PPC_31_LVX:   mnem = "lvx";  break;
+			case PPC_31_LVXL:  mnem = "lvxl"; break;
+			case PPC_31_STVX:  mnem = "stvx";  break;
+			case PPC_31_STVXL: mnem = "stvxl"; break;
+			}
+			debug("%s%s\tv%i,r%i,r%i", mnem, rc? "." : "",
+			    rs, ra, rb);
+			break;
+		default:
+			debug("unimplemented hi6_31, xo = 0x%x", xo);
+		}
+		break;
+	case PPC_HI6_LD:
+	case PPC_HI6_LWZ:
+	case PPC_HI6_LWZU:
+	case PPC_HI6_LHZ:
+	case PPC_HI6_LHZU:
+	case PPC_HI6_LHA:
+	case PPC_HI6_LHAU:
+	case PPC_HI6_LBZ:
+	case PPC_HI6_LBZU:
+	case PPC_HI6_LFD:
+	case PPC_HI6_LFS:
+	case PPC_HI6_LMW:
+	case PPC_HI6_STD:
+	case PPC_HI6_STW:
+	case PPC_HI6_STWU:
+	case PPC_HI6_STH:
+	case PPC_HI6_STHU:
+	case PPC_HI6_STB:
+	case PPC_HI6_STBU:
+	case PPC_HI6_STMW:
+	case PPC_HI6_STFD:
+	case PPC_HI6_STFS:
+		/*  NOTE: Loads use rt, not rs, but are otherwise similar
+		    to stores  */
+		load = 0; wlen = 0;
+		rs = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		imm = (int16_t)(iword & 0xffff);
+		fpreg = 0;
+		switch (hi6) {
+		case PPC_HI6_LD:  load=1; wlen = 8; mnem = "ld"; break;
+		case PPC_HI6_LWZ:  load=1; wlen = 4;
+			mnem = power? "l" : "lwz"; break;
+		case PPC_HI6_LWZU: load=1; wlen = 4;
+			mnem = power? "lu" : "lwzu"; break;
+		case PPC_HI6_LHZ:  load=1; wlen = 2;
+			mnem = "lhz"; break;
+		case PPC_HI6_LHZU: load=1; wlen = 2;
+			mnem = "lhzu"; break;
+		case PPC_HI6_LHA:  load=2; wlen = 2;
+			mnem = "lha"; break;
+		case PPC_HI6_LHAU: load=2; wlen = 2;
+			mnem = "lhau"; break;
+		case PPC_HI6_LBZ:  load=1; wlen = 1;
+			mnem = "lbz"; break;
+		case PPC_HI6_LBZU: load=1; wlen = 1;
+			mnem = "lbzu"; break;
+		case PPC_HI6_LFD:  load=1; fpreg=1; wlen=8; mnem = "lfd"; break;
+		case PPC_HI6_LFS:  load=1; fpreg=1; wlen=4; mnem = "lfs"; break;
+		case PPC_HI6_STD:  wlen=8; mnem = "std"; break;
+		case PPC_HI6_STW:  wlen=4; mnem = power? "st" : "stw"; break;
+		case PPC_HI6_STWU: wlen=4; mnem = power? "stu" : "stwu"; break;
+		case PPC_HI6_STH:  wlen=2; mnem = "sth"; break;
+		case PPC_HI6_STHU: wlen=2; mnem = "sthu"; break;
+		case PPC_HI6_STB:  wlen=1; mnem = "stb"; break;
+		case PPC_HI6_STBU: wlen=1; mnem = "stbu"; break;
+		case PPC_HI6_LMW:  load=1; mnem = power? "lm" : "lmw"; break;
+		case PPC_HI6_STMW: mnem = power? "stm" : "stmw"; break;
+		case PPC_HI6_STFD: fpreg=1; wlen=8; mnem = "stfd"; break;
+		case PPC_HI6_STFS: fpreg=1; wlen=4; mnem = "stfs"; break;
+		}
+		debug("%s\t", mnem);
+		if (fpreg)
+			debug("f");
+		else
+			debug("r");
+		debug("%i,%i(r%i)", rs, imm, ra);
+		if (!running)
+			break;
+		addr = (ra==0? 0 : cpu->cd.ppc.gpr[ra]) + imm;
+		if (cpu->cd.ppc.bits == 32)
+			addr &= 0xffffffff;
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    addr, &offset);
+		if (symbol != NULL)
+			debug(" \t<%s", symbol);
+		else
+			debug(" \t<0x%" PRIx64, (uint64_t) addr);
+		if (wlen > 0 && load && wlen > 0) {
+			unsigned char tw[8];
+			uint64_t tdata = 0;
+			int i, res = cpu->memory_rw(cpu, cpu->mem, addr, tw,
+			    wlen, MEM_READ, NO_EXCEPTIONS);
+			if (res) {
+				if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+					for (i=0; i<wlen; i++) {
+						tdata <<= 8;
+						tdata |= tw[wlen-1-i];
+					}
+				else
+					for (i=0; i<wlen; i++) {
+						tdata <<= 8;
+						tdata |= tw[i];
+					}
+				debug(": ");
+				if (wlen >= 4) {
+					symbol = get_symbol_name(&cpu->machine->
+					    symbol_context, tdata, &offset);
+					if (symbol != NULL)
+						debug("%s", symbol);
+					else
+						debug("0x%" PRIx64,
+						    (uint64_t) tdata);
+				} else {
+					/*  TODO: if load==2, then this is
+					    a _signed_ load.  */
+					debug("0x%" PRIx64, (uint64_t) tdata);
+				}
+			} else
+				debug(": unreadable");
+		}
+		if (wlen > 0 && !load && wlen > 0) {
+			int64_t tdata = 0;
+			int i;
+			for (i=0; i<wlen; i++)
+				tdata |= (cpu->cd.ppc.gpr[rs] &
+				    ((uint64_t)0xff << (i*8)));
+			debug(": ");
+			if (wlen >= 4) {
+				symbol = get_symbol_name(&cpu->machine->
+				    symbol_context, tdata, &offset);
+				if (symbol != NULL)
+					debug("%s", symbol);
+				else
+					debug("0x%" PRIx64, (uint64_t) tdata);
+			} else {
+				if (tdata > -256 && tdata < 256)
+					debug("%i", (int)tdata);
+				else
+					debug("0x%" PRIx64, (uint64_t) tdata);
+			}
+		}
+		debug(">");
+		break;
+	case PPC_HI6_59:
+		xo = (iword >> 1) & 1023;
+		/*  NOTE: Some floating point instructions only use the
+		    lowest 5 bits of xo, some use all 10 bits!  */
+		switch (xo & 31) {
+		case PPC_59_FDIVS:
+		case PPC_59_FSUBS:
+		case PPC_59_FADDS:
+		case PPC_59_FMULS:
+		case PPC_59_FMADDS:
+			rt = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			rs = (iword >>  6) & 31;	/*  actually frc  */
+			rc = iword & 1;
+			switch (xo & 31) {
+			case PPC_59_FDIVS:	mnem = "fdivs"; break;
+			case PPC_59_FSUBS:	mnem = "fsubs"; break;
+			case PPC_59_FADDS:	mnem = "fadds"; break;
+			case PPC_59_FMULS:	mnem = "fmuls"; break;
+			case PPC_59_FMADDS:	mnem = "fmadds"; break;
+			}
+			debug("%s%s\t", mnem, rc? "." : "");
+			switch (xo & 31) {
+			case PPC_59_FMULS:
+				debug("f%i,f%i,f%i", rt, ra, rs);
+				break;
+			case PPC_59_FMADDS:
+				debug("f%i,f%i,f%i,f%i", rt, ra, rs, rb);
+				break;
+			default:debug("f%i,f%i,f%i", rt, ra, rb);
+			}
+			break;
+		default:/*  TODO: similar to hi6_63  */
+			debug("unimplemented hi6_59, xo = 0x%x", xo);
+		}
+		break;
+	case PPC_HI6_63:
+		xo = (iword >> 1) & 1023;
+		/*  NOTE: Some floating point instructions only use the
+		    lowest 5 bits of xo, some use all 10 bits!  */
+		switch (xo & 31) {
+		case PPC_63_FDIV:
+		case PPC_63_FSUB:
+		case PPC_63_FADD:
+		case PPC_63_FMUL:
+		case PPC_63_FMSUB:
+		case PPC_63_FMADD:
+			rt = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			rs = (iword >>  6) & 31;	/*  actually frc  */
+			rc = iword & 1;
+			switch (xo & 31) {
+			case PPC_63_FDIV:
+				mnem = power? "fd" : "fdiv"; break;
+			case PPC_63_FSUB:
+				mnem = power? "fs" : "fsub"; break;
+			case PPC_63_FADD:
+				mnem = power? "fa" : "fadd"; break;
+			case PPC_63_FMUL:
+				mnem = power? "fm" : "fmul"; break;
+			case PPC_63_FMSUB:
+				mnem = power? "fms" : "fmsub"; break;
+			case PPC_63_FMADD:
+				mnem = power? "fma" : "fmadd"; break;
+			}
+			debug("%s%s\t", mnem, rc? "." : "");
+			switch (xo & 31) {
+			case PPC_63_FMUL:
+				debug("f%i,f%i,f%i", rt, ra, rs);
+				break;
+			case PPC_63_FMADD:
+				debug("f%i,f%i,f%i,f%i", rt, ra, rs, rb);
+				break;
+			default:debug("f%i,f%i,f%i", rt, ra, rb);
+			}
+			break;
+		default:rt = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			rc = iword & 1;
+			switch (xo) {
+			case PPC_63_FCMPU:
+			case PPC_63_FRSP:
+			case PPC_63_FCTIWZ:
+			case PPC_63_FNEG:
+			case PPC_63_FMR:
+			case PPC_63_FNABS:
+			case PPC_63_FABS:
+				switch (xo) {
+				case PPC_63_FCMPU:	mnem = "fcmpu"; break;
+				case PPC_63_FCTIWZ:
+					mnem = power? "fcirz" : "fctiwz"; break;
+				case PPC_63_FRSP:	mnem = "frsp"; break;
+				case PPC_63_FNEG:	mnem = "fneg"; break;
+				case PPC_63_FMR:	mnem = "fmr"; break;
+				case PPC_63_FNABS:	mnem = "fnabs"; break;
+				case PPC_63_FABS:	mnem = "fabs"; break;
+				}
+				debug("%s%s\t", mnem, rc? "." : "");
+				switch (xo) {
+				case PPC_63_FCMPU:
+					debug("%i,f%i,f%i", rt >> 2, ra, rb);
+					break;
+				case PPC_63_FCTIWZ:
+				case PPC_63_FRSP:
+				case PPC_63_FNEG:
+				case PPC_63_FMR:
+				case PPC_63_FNABS:
+				case PPC_63_FABS:
+					debug("f%i,f%i", rt, rb);
+					break;
+				default:debug("f%i,f%i,f%i", rt, ra, rb);
+				}
+				break;
+			case PPC_63_MFFS:
+				debug("mffs%s\tf%i", rc?".":"", rt);
+				break;
+			case PPC_63_MTFSF:
+				ra = (iword >> 17) & 255;	/*  flm  */
+				debug("mtfsf%s\t0x%02x,f%i", rc?".":"", ra, rb);
+				break;
+			default:debug("unimplemented hi6_63, xo = 0x%x", xo);
+			}
+		}
+		break;
+	default:
+		/*  TODO  */
+		debug("unimplemented hi6 = 0x%02x", hi6);
+	}
+
+	debug("\n");
+	return sizeof(iword);
+}
+
+
+/*
+ *  debug_spr_usage():
+ *
+ *  Helper function. To speed up overall development speed of the emulator,
+ *  all SPR accesses are allowed. This function causes unknown/unimplemented
+ *  SPRs to give a warning.
+ */
+static void debug_spr_usage(uint64_t pc, int spr)
+{
+	static uint32_t spr_used[1024 / sizeof(uint32_t)];
+	static int initialized = 0;
+
+	if (!initialized) {
+		memset(spr_used, 0, sizeof(spr_used));
+		initialized = 1;
+	}
+
+	spr &= 1023;
+	if (spr_used[spr >> 2] & (1 << (spr & 3)))
+		return;
+
+	switch (spr) {
+	/*  Known/implemented SPRs:  */
+	case SPR_XER:
+	case SPR_LR:
+	case SPR_CTR:
+	case SPR_DSISR:
+	case SPR_DAR:
+	case SPR_DEC:
+	case SPR_SDR1:
+	case SPR_SRR0:
+	case SPR_SRR1:
+	case SPR_SPRG0:
+	case SPR_SPRG1:
+	case SPR_SPRG2:
+	case SPR_SPRG3:
+	case SPR_PVR:
+	case SPR_DMISS:
+	case SPR_DCMP:
+	case SPR_HASH1:
+	case SPR_HASH2:
+	case SPR_IMISS:
+	case SPR_ICMP:
+	case SPR_DBSR:
+	case SPR_PIR:
+		break;
+	default:if (spr >= SPR_IBAT0U && spr <= SPR_DBAT3L) {
+			break;
+		} else
+			fatal("[ using UNIMPLEMENTED spr %i (%s), pc = "
+			    "0x%" PRIx64" ]\n", spr, ppc_spr_names[spr] == NULL?
+			    "UNKNOWN" : ppc_spr_names[spr], (uint64_t) pc);
+	}
+
+	spr_used[spr >> 2] |= (1 << (spr & 3));
+}
+
+
+/*
+ *  update_cr0():
+ *
+ *  Sets the top 4 bits of the CR register.
+ */
+void update_cr0(struct cpu *cpu, uint64_t value)
+{
+	int c;
+
+	if (cpu->cd.ppc.bits == 64) {
+		if ((int64_t)value < 0)
+			c = 8;
+		else if ((int64_t)value > 0)
+			c = 4;
+		else
+			c = 2;
+	} else {
+		if ((int32_t)value < 0)
+			c = 8;
+		else if ((int32_t)value > 0)
+			c = 4;
+		else
+			c = 2;
+	}
+
+	/*  SO bit, copied from XER:  */
+	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
+
+	cpu->cd.ppc.cr &= ~((uint32_t)0xf << 28);
+	cpu->cd.ppc.cr |= ((uint32_t)c << 28);
+}
+
+
+#include "memory_ppc.c"
+
+
+#include "tmp_ppc_tail.c"
+
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_ppc.cc gxemul-0.7.0+dfsg/src/cpus/cpu_ppc.cc
--- gxemul-0.6.2/src/cpus/cpu_ppc.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_ppc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1866 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  PowerPC/POWER CPU emulation.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <ctype.h>
-
-#include "cpu.h"
-#include "devices.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "of.h"
-#include "opcodes_ppc.h"
-#include "ppc_spr_strings.h"
-#include "settings.h"
-#include "symbol.h"
-
-#include "thirdparty/ppc_bat.h"
-#include "thirdparty/ppc_pte.h"
-#include "thirdparty/ppc_spr.h"
-
-#define	DYNTRANS_DUALMODE_32
-#include "tmp_ppc_head.cc"
-
-
-void ppc_pc_to_pointers(struct cpu *);
-void ppc32_pc_to_pointers(struct cpu *);
-
-void ppc_irq_interrupt_assert(struct interrupt *interrupt);
-void ppc_irq_interrupt_deassert(struct interrupt *interrupt);
-
-
-/*
- *  ppc_cpu_new():
- *
- *  Create a new PPC cpu object.
- *
- *  Returns 1 on success, 0 if there was no matching PPC processor with
- *  this cpu_type_name.
- */
-int ppc_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
-	int cpu_id, char *cpu_type_name)
-{
-	int any_cache = 0;
-	int i, found;
-	struct ppc_cpu_type_def cpu_type_defs[] = PPC_CPU_TYPE_DEFS;
-
-	/*  Scan the cpu_type_defs list for this cpu type:  */
-	i = 0;
-	found = -1;
-	while (i >= 0 && cpu_type_defs[i].name != NULL) {
-		if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
-			found = i;
-			break;
-		}
-		i++;
-	}
-	if (found == -1)
-		return 0;
-
-	cpu->memory_rw = ppc_memory_rw;
-
-	cpu->cd.ppc.cpu_type = cpu_type_defs[found];
-	cpu->name            = strdup(cpu->cd.ppc.cpu_type.name);
-	cpu->byte_order      = EMUL_BIG_ENDIAN;
-	cpu->cd.ppc.mode     = MODE_PPC;	/*  TODO  */
-
-	/*  Current operating mode:  */
-	cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits;
-	cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr;
-
-	/*  cpu->cd.ppc.msr = PPC_MSR_IR | PPC_MSR_DR |
-	    PPC_MSR_SF | PPC_MSR_FP;  */
-
-	cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs;
-	cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW;
-	cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs;
-	cpu->cd.ppc.spr[SPR_IBAT1L] = 0x00000000 | BAT_PP_RW;
-	cpu->cd.ppc.spr[SPR_IBAT3U] = 0xf0001ffc | BAT_Vs;
-	cpu->cd.ppc.spr[SPR_IBAT3L] = 0xf0000000 | BAT_PP_RW;
-	cpu->cd.ppc.spr[SPR_DBAT0U] = 0x00001ffc | BAT_Vs;
-	cpu->cd.ppc.spr[SPR_DBAT0L] = 0x00000000 | BAT_PP_RW;
-	cpu->cd.ppc.spr[SPR_DBAT1U] = 0xc0001ffc | BAT_Vs;
-	cpu->cd.ppc.spr[SPR_DBAT1L] = 0x00000000 | BAT_PP_RW;
-	cpu->cd.ppc.spr[SPR_DBAT2U] = 0xe0001ffc | BAT_Vs;
-	cpu->cd.ppc.spr[SPR_DBAT2L] = 0xe0000000 | BAT_PP_RW;
-	cpu->cd.ppc.spr[SPR_DBAT3U] = 0xf0001ffc | BAT_Vs;
-	cpu->cd.ppc.spr[SPR_DBAT3L] = 0xf0000000 | BAT_PP_RW;
-
-	cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0;
-
-	if (cpu->is_32bit) {
-		cpu->run_instr = ppc32_run_instr;
-		cpu->update_translation_table = ppc32_update_translation_table;
-		cpu->invalidate_translation_caches =
-		    ppc32_invalidate_translation_caches;
-		cpu->invalidate_code_translation =
-		    ppc32_invalidate_code_translation;
-	} else {
-		cpu->run_instr = ppc_run_instr;
-		cpu->update_translation_table = ppc_update_translation_table;
-		cpu->invalidate_translation_caches =
-		    ppc_invalidate_translation_caches;
-		cpu->invalidate_code_translation =
-		    ppc_invalidate_code_translation;
-	}
-
-	cpu->translate_v2p = ppc_translate_v2p;
-
-	/*  Only show name and caches etc for CPU nr 0 (in SMP machines):  */
-	if (cpu_id == 0) {
-		debug("%s", cpu->cd.ppc.cpu_type.name);
-
-		if (cpu->cd.ppc.cpu_type.icache_shift != 0)
-			any_cache = 1;
-		if (cpu->cd.ppc.cpu_type.dcache_shift != 0)
-			any_cache = 1;
-		if (cpu->cd.ppc.cpu_type.l2cache_shift != 0)
-			any_cache = 1;
-
-		if (any_cache) {
-			debug(" (I+D = %i+%i KB",
-			    (int)(1 << (cpu->cd.ppc.cpu_type.icache_shift-10)),
-			    (int)(1 << (cpu->cd.ppc.cpu_type.dcache_shift-10)));
-			if (cpu->cd.ppc.cpu_type.l2cache_shift != 0) {
-				debug(", L2 = %i KB",
-				    (int)(1 << (cpu->cd.ppc.cpu_type.
-				    l2cache_shift-10)));
-			}
-			debug(")");
-		}
-	}
-
-	cpu->cd.ppc.spr[SPR_PIR] = cpu_id;
-
-	/*  Some default stack pointer value.  TODO: move this?  */
-	cpu->cd.ppc.gpr[1] = machine->physical_ram_in_mb * 1048576 - 4096;
-
-	/*
-	 *  NOTE/TODO: Ugly hack for OpenFirmware emulation:
-	 */
-	if (cpu->machine->prom_emulation)
-		cpu->cd.ppc.of_emul_addr = 0xfff00000;
-
-	/*  Add all register names to the settings:  */
-	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
-	CPU_SETTINGS_ADD_REGISTER64("msr", cpu->cd.ppc.msr);
-	CPU_SETTINGS_ADD_REGISTER64("ctr", cpu->cd.ppc.spr[SPR_CTR]);
-	CPU_SETTINGS_ADD_REGISTER64("xer", cpu->cd.ppc.spr[SPR_XER]);
-	CPU_SETTINGS_ADD_REGISTER64("dec", cpu->cd.ppc.spr[SPR_DEC]);
-	CPU_SETTINGS_ADD_REGISTER64("hdec", cpu->cd.ppc.spr[SPR_HDEC]);
-	CPU_SETTINGS_ADD_REGISTER64("srr0", cpu->cd.ppc.spr[SPR_SRR0]);
-	CPU_SETTINGS_ADD_REGISTER64("srr1", cpu->cd.ppc.spr[SPR_SRR1]);
-	CPU_SETTINGS_ADD_REGISTER64("sdr1", cpu->cd.ppc.spr[SPR_SDR1]);
-	CPU_SETTINGS_ADD_REGISTER64("ibat0u", cpu->cd.ppc.spr[SPR_IBAT0U]);
-	CPU_SETTINGS_ADD_REGISTER64("ibat0l", cpu->cd.ppc.spr[SPR_IBAT0L]);
-	CPU_SETTINGS_ADD_REGISTER64("ibat1u", cpu->cd.ppc.spr[SPR_IBAT1U]);
-	CPU_SETTINGS_ADD_REGISTER64("ibat1l", cpu->cd.ppc.spr[SPR_IBAT1L]);
-	CPU_SETTINGS_ADD_REGISTER64("ibat2u", cpu->cd.ppc.spr[SPR_IBAT2U]);
-	CPU_SETTINGS_ADD_REGISTER64("ibat2l", cpu->cd.ppc.spr[SPR_IBAT2L]);
-	CPU_SETTINGS_ADD_REGISTER64("ibat3u", cpu->cd.ppc.spr[SPR_IBAT3U]);
-	CPU_SETTINGS_ADD_REGISTER64("ibat3l", cpu->cd.ppc.spr[SPR_IBAT3L]);
-	CPU_SETTINGS_ADD_REGISTER64("dbat0u", cpu->cd.ppc.spr[SPR_DBAT0U]);
-	CPU_SETTINGS_ADD_REGISTER64("dbat0l", cpu->cd.ppc.spr[SPR_DBAT0L]);
-	CPU_SETTINGS_ADD_REGISTER64("dbat1u", cpu->cd.ppc.spr[SPR_DBAT1U]);
-	CPU_SETTINGS_ADD_REGISTER64("dbat1l", cpu->cd.ppc.spr[SPR_DBAT1L]);
-	CPU_SETTINGS_ADD_REGISTER64("dbat2u", cpu->cd.ppc.spr[SPR_DBAT2U]);
-	CPU_SETTINGS_ADD_REGISTER64("dbat2l", cpu->cd.ppc.spr[SPR_DBAT2L]);
-	CPU_SETTINGS_ADD_REGISTER64("dbat3u", cpu->cd.ppc.spr[SPR_DBAT3U]);
-	CPU_SETTINGS_ADD_REGISTER64("dbat3l", cpu->cd.ppc.spr[SPR_DBAT3L]);
-	CPU_SETTINGS_ADD_REGISTER64("lr", cpu->cd.ppc.spr[SPR_LR]);
-	CPU_SETTINGS_ADD_REGISTER32("cr", cpu->cd.ppc.cr);
-	CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.ppc.fpscr);
-	/*  Integer GPRs, floating point registers, and segment registers:  */
-	for (i=0; i<PPC_NGPRS; i++) {
-		char tmpstr[5];
-		snprintf(tmpstr, sizeof(tmpstr), "r%i", i);
-		CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.gpr[i]);
-	}
-	for (i=0; i<PPC_NFPRS; i++) {
-		char tmpstr[5];
-		snprintf(tmpstr, sizeof(tmpstr), "f%i", i);
-		CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.fpr[i]);
-	}
-	for (i=0; i<16; i++) {
-		char tmpstr[5];
-		snprintf(tmpstr, sizeof(tmpstr), "sr%i", i);
-		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.ppc.sr[i]);
-	}
-
-	/*  Register the CPU as an interrupt handler:  */
-	{
-		struct interrupt templ;
-		char name[150];
-		snprintf(name, sizeof(name), "%s", cpu->path);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 0;
-		templ.name = name;
-		templ.extra = cpu;
-		templ.interrupt_assert = ppc_irq_interrupt_assert;
-		templ.interrupt_deassert = ppc_irq_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	return 1;
-}
-
-
-/*
- *  ppc_cpu_list_available_types():
- *
- *  Print a list of available PPC CPU types.
- */
-void ppc_cpu_list_available_types(void)
-{
-	int i, j;
-	struct ppc_cpu_type_def tdefs[] = PPC_CPU_TYPE_DEFS;
-
-	i = 0;
-	while (tdefs[i].name != NULL) {
-		debug("%s", tdefs[i].name);
-		for (j=10 - strlen(tdefs[i].name); j>0; j--)
-			debug(" ");
-		i++;
-		if ((i % 6) == 0 || tdefs[i].name == NULL)
-			debug("\n");
-	}
-}
-
-
-/*
- *  ppc_cpu_dumpinfo():
- */
-void ppc_cpu_dumpinfo(struct cpu *cpu)
-{
-	struct ppc_cpu_type_def *ct = &cpu->cd.ppc.cpu_type;
-
-	debug(" (%i-bit ", cpu->cd.ppc.bits);
-
-	switch (cpu->cd.ppc.mode) {
-	case MODE_PPC:
-		debug("PPC");
-		break;
-	case MODE_POWER:
-		debug("POWER");
-		break;
-	default:
-		debug("_INTERNAL ERROR_");
-	}
-
-	debug(", I+D = %i+%i KB",
-	    (1 << ct->icache_shift) / 1024,
-	    (1 << ct->dcache_shift) / 1024);
-
-	if (ct->l2cache_shift) {
-		int kb = (1 << ct->l2cache_shift) / 1024;
-		debug(", L2 = %i %cB",
-		    kb >= 1024? kb / 1024 : kb,
-		    kb >= 1024? 'M' : 'K');
-	}
-
-	debug(")\n");
-}
-
-
-/*
- *  reg_access_msr():
- */
-void reg_access_msr(struct cpu *cpu, uint64_t *valuep, int writeflag,
-	int check_for_interrupts)
-{
-	uint64_t old = cpu->cd.ppc.msr;
-
-	if (valuep == NULL) {
-		fatal("reg_access_msr(): NULL\n");
-		return;
-	}
-
-	if (writeflag) {
-		cpu->cd.ppc.msr = *valuep;
-
-		/*  Switching between temporary and real gpr 0..3?  */
-		if ((old & PPC_MSR_TGPR) != (cpu->cd.ppc.msr & PPC_MSR_TGPR)) {
-			int i;
-			for (i=0; i<PPC_N_TGPRS; i++) {
-				uint64_t t = cpu->cd.ppc.gpr[i];
-				cpu->cd.ppc.gpr[i] = cpu->cd.ppc.tgpr[i];
-				cpu->cd.ppc.tgpr[i] = t;
-			}
-		}
-
-		if (cpu->cd.ppc.msr & PPC_MSR_IP) {
-			fatal("\n[ Reboot hack for NetBSD/prep. TODO: "
-			    "fix this. ]\n");
-			cpu->running = 0;
-		}
-	}
-
-	/*  TODO: Is the little-endian bit writable?  */
-
-	cpu->cd.ppc.msr &= ~PPC_MSR_LE;
-	if (cpu->byte_order != EMUL_BIG_ENDIAN)
-		cpu->cd.ppc.msr |= PPC_MSR_LE;
-
-	if (!writeflag)
-		*valuep = cpu->cd.ppc.msr;
-
-	if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) {
-		if (cpu->cd.ppc.dec_intr_pending &&
-		    !(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) {
-			ppc_exception(cpu, PPC_EXCEPTION_DEC);
-			cpu->cd.ppc.dec_intr_pending = 0;
-		} else if (cpu->cd.ppc.irq_asserted)
-			ppc_exception(cpu, PPC_EXCEPTION_EI);
-	}
-}
-
-
-/*
- *  ppc_exception():
- */
-void ppc_exception(struct cpu *cpu, int exception_nr)
-{
-	/*  Save PC and MSR:  */
-	cpu->cd.ppc.spr[SPR_SRR0] = cpu->pc;
-
-	if (exception_nr >= 0x10 && exception_nr <= 0x13)
-		cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0xffff)
-		    | (cpu->cd.ppc.cr & 0xf0000000);
-	else
-		cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff);
-
-	if (!quiet_mode)
-		fatal("[ PPC Exception 0x%x; pc=0x%" PRIx64" ]\n",
-		    exception_nr, cpu->pc);
-
-	/*  Disable External Interrupts, Recoverable Interrupt Mode,
-	    and go to Supervisor mode  */
-	cpu->cd.ppc.msr &= ~(PPC_MSR_EE | PPC_MSR_RI | PPC_MSR_PR);
-
-	cpu->pc = exception_nr * 0x100;
-	if (cpu->cd.ppc.msr & PPC_MSR_IP)
-		cpu->pc += 0xfff00000ULL;
-
-	if (cpu->is_32bit)
-		ppc32_pc_to_pointers(cpu);
-	else
-		ppc_pc_to_pointers(cpu);
-}
-
-
-/*
- *  ppc_cpu_register_dump():
- *
- *  Dump cpu registers in a relatively readable format.
- *
- *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
- *  coprocs: if bit i is set, then we should dump registers from coproc i.
- */
-void ppc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
-{
-	char *symbol;
-	uint64_t offset, tmp;
-	int i, x = cpu->cpu_id;
-	int bits32 = cpu->cd.ppc.bits == 32;
-
-	if (gprs) {
-		/*  Special registers (pc, ...) first:  */
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    cpu->pc, &offset);
-
-		debug("cpu%i: pc  = 0x", x);
-		if (bits32)
-			debug("%08" PRIx32, (uint32_t)cpu->pc);
-		else
-			debug("%016" PRIx64, (uint64_t)cpu->pc);
-		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
-
-		debug("cpu%i: lr  = 0x", x);
-		if (bits32)
-			debug("%08" PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]);
-		else
-			debug("%016" PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]);
-		debug("  cr  = 0x%08" PRIx32, (uint32_t)cpu->cd.ppc.cr);
-
-		if (bits32)
-			debug("  ");
-		else
-			debug("\ncpu%i: ", x);
-		debug("ctr = 0x", x);
-		if (bits32)
-			debug("%08" PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]);
-		else
-			debug("%016" PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]);
-
-		debug("  xer = 0x", x);
-		if (bits32)
-			debug("%08" PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]);
-		else
-			debug("%016" PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]);
-
-		debug("\n");
-
-		if (bits32) {
-			/*  32-bit:  */
-			for (i=0; i<PPC_NGPRS; i++) {
-				if ((i % 4) == 0)
-					debug("cpu%i:", x);
-				debug(" r%02i = 0x%08" PRIx32" ", i,
-				    (uint32_t) cpu->cd.ppc.gpr[i]);
-				if ((i % 4) == 3)
-					debug("\n");
-			}
-		} else {
-			/*  64-bit:  */
-			for (i=0; i<PPC_NGPRS; i++) {
-				int r = (i >> 1) + ((i & 1) << 4);
-				if ((i % 2) == 0)
-					debug("cpu%i:", x);
-				debug(" r%02i = 0x%016" PRIx64" ", r,
-				    (uint64_t) cpu->cd.ppc.gpr[r]);
-				if ((i % 2) == 1)
-					debug("\n");
-			}
-		}
-
-		/*  Other special registers:  */
-		if (bits32) {
-			debug("cpu%i: srr0 = 0x%08" PRIx32
-			    " srr1 = 0x%08" PRIx32"\n", x,
-			    (uint32_t) cpu->cd.ppc.spr[SPR_SRR0],
-			    (uint32_t) cpu->cd.ppc.spr[SPR_SRR1]);
-		} else {
-			debug("cpu%i: srr0 = 0x%016" PRIx64
-			    "  srr1 = 0x%016" PRIx64"\n", x,
-			    (uint64_t) cpu->cd.ppc.spr[SPR_SRR0],
-			    (uint64_t) cpu->cd.ppc.spr[SPR_SRR1]);
-		}
-
-		debug("cpu%i: msr = ", x);
-		reg_access_msr(cpu, &tmp, 0, 0);
-		if (bits32)
-			debug("0x%08" PRIx32, (uint32_t) tmp);
-		else
-			debug("0x%016" PRIx64, (uint64_t) tmp);
-
-		debug("  tb  = 0x%08" PRIx32"%08" PRIx32"\n",
-		    (uint32_t) cpu->cd.ppc.spr[SPR_TBU],
-		    (uint32_t) cpu->cd.ppc.spr[SPR_TBL]);
-
-		debug("cpu%i: dec = 0x%08" PRIx32,
-		    x, (uint32_t) cpu->cd.ppc.spr[SPR_DEC]);
-		if (!bits32)
-			debug("  hdec = 0x%08" PRIx32"\n",
-			    (uint32_t) cpu->cd.ppc.spr[SPR_HDEC]);
-
-		debug("\n");
-	}
-
-	if (coprocs & 1) {
-		debug("cpu%i: fpscr = 0x%08" PRIx32"\n",
-		    x, (uint32_t) cpu->cd.ppc.fpscr);
-
-		/*  TODO: show floating-point values :-)  */
-
-		/*  TODO: 32-bit fprs on 32-bit PPC cpus?  */
-
-		for (i=0; i<PPC_NFPRS; i++) {
-			if ((i % 2) == 0)
-				debug("cpu%i:", x);
-			debug(" f%02i = 0x%016" PRIx64" ", i,
-			    (uint64_t) cpu->cd.ppc.fpr[i]);
-			if ((i % 2) == 1)
-				debug("\n");
-		}
-	}
-
-	if (coprocs & 2) {
-		debug("cpu%i:  sdr1 = 0x%" PRIx64"\n", x,
-		    (uint64_t) cpu->cd.ppc.spr[SPR_SDR1]);
-		if (cpu->cd.ppc.cpu_type.flags & PPC_601)
-			debug("cpu%i:  PPC601-style, TODO!\n");
-		else {
-			for (i=0; i<8; i++) {
-				int spr = SPR_IBAT0U + i*2;
-				uint32_t upper = cpu->cd.ppc.spr[spr];
-				uint32_t lower = cpu->cd.ppc.spr[spr+1];
-				uint32_t len = (((upper & BAT_BL) << 15)
-				    | 0x1ffff) + 1;
-				debug("cpu%i:  %sbat%i: u=0x%08" PRIx32
-				    " l=0x%08" PRIx32" ",
-				    x, i<4? "i" : "d", i&3, upper, lower);
-				if (!(upper & BAT_V)) {
-					debug(" (not valid)\n");
-					continue;
-				}
-				if (len < 1048576)
-					debug(" (%i KB, ", len >> 10);
-				else
-					debug(" (%i MB, ", len >> 20);
-				if (upper & BAT_Vu)
-					debug("user, ");
-				if (upper & BAT_Vs)
-					debug("supervisor, ");
-				if (lower & (BAT_W | BAT_I | BAT_M | BAT_G))
-					debug("%s%s%s%s, ",
-					    lower & BAT_W? "W" : "",
-					    lower & BAT_I? "I" : "",
-					    lower & BAT_M? "M" : "",
-					    lower & BAT_G? "G" : "");
-				switch (lower & BAT_PP) {
-				case BAT_PP_NONE: debug("NO access"); break;
-				case BAT_PP_RO_S: debug("read-only, soft");
-					          break;
-				case BAT_PP_RO:   debug("read-only"); break;
-				case BAT_PP_RW:   debug("read/write"); break;
-				}
-				debug(")\n");
-			}
-		}
-	}
-
-	if (coprocs & 4) {
-		for (i=0; i<16; i++) {
-			uint32_t s = cpu->cd.ppc.sr[i];
-
-			debug("cpu%i:", x);
-			debug("  sr%-2i = 0x%08" PRIx32, i, s);
-
-			s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC);
-			if (s != 0) {
-				debug("  (");
-				if (s & SR_TYPE) {
-					debug("NON-memory type");
-					s &= ~SR_TYPE;
-					if (s != 0)
-						debug(", ");
-				}
-				if (s & SR_SUKEY) {
-					debug("supervisor-key");
-					s &= ~SR_SUKEY;
-					if (s != 0)
-						debug(", ");
-				}
-				if (s & SR_PRKEY) {
-					debug("user-key");
-					s &= ~SR_PRKEY;
-					if (s != 0)
-						debug(", ");
-				}
-				if (s & SR_NOEXEC)
-					debug("NOEXEC");
-				debug(")");
-			}
-			debug("\n");
-		}
-	}
-}
-
-
-/*
- *  ppc_cpu_tlbdump():
- *
- *  Not currently used for PPC.
- */
-void ppc_cpu_tlbdump(struct machine *m, int x, int rawflag)
-{
-}
-
-
-/*
- *  ppc_irq_interrupt_assert():
- */
-void ppc_irq_interrupt_assert(struct interrupt *interrupt)
-{
-	struct cpu *cpu = (struct cpu *) interrupt->extra;
-	cpu->cd.ppc.irq_asserted = 1;
-}
-
-
-/*
- *  ppc_irq_interrupt_deassert():
- */
-void ppc_irq_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct cpu *cpu = (struct cpu *) interrupt->extra;
-	cpu->cd.ppc.irq_asserted = 0;
-}
-
-
-/*
- *  ppc_cpu_disassemble_instr():
- *
- *  Convert an instruction word into human readable format, for instruction
- *  tracing.
- *
- *  If running is 1, cpu->pc should be the address of the instruction.
- *
- *  If running is 0, things that depend on the runtime environment (eg.
- *  register contents) will not be shown, and addr will be used instead of
- *  cpu->pc for relative addresses.
- */
-int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
-	int running, uint64_t dumpaddr)
-{
-	int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit; //, oe_bit;
-	int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg;
-	int bfa, to, load, wlen, no_rb = 0;
-	uint64_t offset, addr;
-	uint32_t iword;
-	const char *symbol, *mnem = "ERROR";
-	int power = cpu->cd.ppc.mode == MODE_POWER;
-
-	if (running)
-		dumpaddr = cpu->pc;
-
-	symbol = get_symbol_name(&cpu->machine->symbol_context,
-	    dumpaddr, &offset);
-	if (symbol != NULL && offset==0)
-		debug("<%s>\n", symbol);
-
-	if (cpu->machine->ncpus > 1 && running)
-		debug("cpu%i: ", cpu->cpu_id);
-
-	if (cpu->cd.ppc.bits == 32)
-		debug("%08" PRIx32, (uint32_t) dumpaddr);
-	else
-		debug("%016" PRIx64, (uint64_t) dumpaddr);
-
-	/*  NOTE: Fixed to big-endian.  */
-	iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8)
-	    + instr[3];
-
-	debug(": %08" PRIx32"\t", iword);
-
-	/*
-	 *  Decode the instruction:
-	 */
-
-	hi6 = iword >> 26;
-
-	switch (hi6) {
-	case 0x4:
-		debug("ALTIVEC TODO");
-		/*  vxor etc  */
-		break;
-	case PPC_HI6_MULLI:
-	case PPC_HI6_SUBFIC:
-		rt = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		imm = (int16_t)(iword & 0xffff);
-		switch (hi6) {
-		case PPC_HI6_MULLI:
-			mnem = power? "muli":"mulli";
-			break;
-		case PPC_HI6_SUBFIC:
-			mnem = power? "sfi":"subfic";
-			break;
-		}
-		debug("%s\tr%i,r%i,%i", mnem, rt, ra, imm);
-		break;
-	case PPC_HI6_CMPLI:
-	case PPC_HI6_CMPI:
-		bf = (iword >> 23) & 7;
-		l_bit = (iword >> 21) & 1;
-		ra = (iword >> 16) & 31;
-		if (hi6 == PPC_HI6_CMPLI) {
-			imm = iword & 0xffff;
-			mnem = "cmpl";
-		} else {
-			imm = (int16_t)(iword & 0xffff);
-			mnem = "cmp";
-		}
-		debug("%s%si\t", mnem, l_bit? "d" : "w");
-		if (bf != 0)
-			debug("cr%i,", bf);
-		debug("r%i,%i", ra, imm);
-		break;
-	case PPC_HI6_ADDIC:
-	case PPC_HI6_ADDIC_DOT:
-		rt = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		rc = hi6 == PPC_HI6_ADDIC_DOT;
-		imm = (int16_t)(iword & 0xffff);
-		mnem = power? "ai":"addic";
-		if (imm < 0 && !power) {
-			mnem = "subic";
-			imm = -imm;
-		}
-		debug("%s%s\tr%i,r%i,%i", mnem, rc?".":"", rt, ra, imm);
-		break;
-	case PPC_HI6_ADDI:
-		rt = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		imm = (int16_t)(iword & 0xffff);
-		if (ra == 0)
-			debug("li\tr%i,%i", rt, imm);
-		else {
-			mnem = power? "cal":"addi";
-			if (imm < 0 && !power) {
-				mnem = "subi";
-				imm = -imm;
-			}
-			debug("%s\tr%i,r%i,%i", mnem, rt, ra, imm);
-		}
-		break;
-	case PPC_HI6_ADDIS:
-		rt = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		imm = (int16_t)(iword & 0xffff);
-		if (ra == 0)
-			debug("lis\tr%i,%i", rt, imm);
-		else
-			debug("%s\tr%i,r%i,%i",
-			    power? "cau":"addis", rt, ra, imm);
-		break;
-	case PPC_HI6_BC:
-		aa_bit = (iword & 2) >> 1;
-		lk_bit = iword & 1;
-		bo = (iword >> 21) & 31;
-		bi = (iword >> 16) & 31;
-		/*  Sign-extend addr:  */
-		addr = (int64_t)(int16_t)(iword & 0xfffc);
-		debug("bc");
-		if (lk_bit)
-			debug("l");
-		if (aa_bit)
-			debug("a");
-		else
-			addr += dumpaddr;
-		debug("\t%i,%i,", bo, bi);
-		if (cpu->cd.ppc.bits == 32)
-			addr &= 0xffffffff;
-		if (cpu->cd.ppc.bits == 32)
-			debug("0x%" PRIx32, (uint32_t) addr);
-		else
-			debug("0x%" PRIx64, (uint64_t) addr);
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    addr, &offset);
-		if (symbol != NULL)
-			debug("\t<%s>", symbol);
-		break;
-	case PPC_HI6_SC:
-		lev = (iword >> 5) & 0x7f;
-		debug("sc");
-		if (lev != 0) {
-			debug("\t%i", lev);
-			if (lev > 1)
-				debug(" (WARNING! reserved value)");
-		}
-		break;
-	case PPC_HI6_B:
-		aa_bit = (iword & 2) >> 1;
-		lk_bit = iword & 1;
-		/*  Sign-extend addr:  */
-		addr = (int64_t)(int32_t)((iword & 0x03fffffc) << 6);
-		addr = (int64_t)addr >> 6;
-		debug("b");
-		if (lk_bit)
-			debug("l");
-		if (aa_bit)
-			debug("a");
-		else
-			addr += dumpaddr;
-		if (cpu->cd.ppc.bits == 32)
-			addr &= 0xffffffff;
-		if (cpu->cd.ppc.bits == 32)
-			debug("\t0x%" PRIx32, (uint32_t) addr);
-		else
-			debug("\t0x%" PRIx64, (uint64_t) addr);
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    addr, &offset);
-		if (symbol != NULL)
-			debug("\t<%s>", symbol);
-		break;
-	case PPC_HI6_19:
-		xo = (iword >> 1) & 1023;
-		switch (xo) {
-		case PPC_19_MCRF:
-			bf = (iword >> 23) & 7;
-			bfa = (iword >> 18) & 7;
-			debug("mcrf\tcr%i,cr%i", bf, bfa);
-			break;
-		case PPC_19_RFI:
-			debug("rfi");
-			break;
-		case PPC_19_RFID:
-			debug("rfid");
-			break;
-		case PPC_19_RFSVC:
-			debug("rfsvc%s", power?"":"\t(INVALID for PowerPC)");
-			break;
-		case PPC_19_BCLR:
-		case PPC_19_BCCTR:
-			bo = (iword >> 21) & 31;
-			bi = (iword >> 16) & 31;
-			bh = (iword >> 11) & 3;
-			lk_bit = iword & 1;
-			switch (xo) {
-			case PPC_19_BCLR:
-				mnem = power? "bcr" : "bclr"; break;
-			case PPC_19_BCCTR:
-				mnem = power? "bcc" : "bcctr"; break;
-			}
-			debug("%s%s%s\t%i,%i,%i", mnem, lk_bit? "l" : "",
-			    bh? (bh==3? "+" : (bh==2? "-" : "?")) : "",
-			    bo, bi, bh);
-			break;
-		case PPC_19_ISYNC:
-			debug("%s", power? "ics" : "isync");
-			break;
-		case PPC_19_CRAND:
-		case PPC_19_CRXOR:
-		case PPC_19_CROR:
-		case PPC_19_CRNAND:
-		case PPC_19_CRNOR:
-		case PPC_19_CRANDC:
-		case PPC_19_CREQV:
-		case PPC_19_CRORC:
-			bt = (iword >> 21) & 31;
-			ba = (iword >> 16) & 31;
-			bb = (iword >> 11) & 31;
-			switch (xo) {
-			case PPC_19_CRAND:	mnem = "crand"; break;
-			case PPC_19_CRXOR:	mnem = "crxor"; break;
-			case PPC_19_CROR:	mnem = "cror"; break;
-			case PPC_19_CRNAND:	mnem = "crnand"; break;
-			case PPC_19_CRNOR:	mnem = "crnor"; break;
-			case PPC_19_CRANDC:	mnem = "crandc"; break;
-			case PPC_19_CREQV:	mnem = "creqv"; break;
-			case PPC_19_CRORC:	mnem = "crorc"; break;
-			}
-			debug("%s\t%i,%i,%i", mnem, bt, ba, bb);
-			break;
-		default:
-			debug("unimplemented hi6_19, xo = 0x%x", xo);
-		}
-		break;
-	case PPC_HI6_RLWNM:
-	case PPC_HI6_RLWIMI:
-	case PPC_HI6_RLWINM:
-		rs = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		sh = (iword >> 11) & 31;	/*  actually rb for rlwnm  */
-		mb = (iword >> 6) & 31;
-		me = (iword >> 1) & 31;
-		rc = iword & 1;
-		switch (hi6) {
-		case PPC_HI6_RLWNM:
-			mnem = power? "rlnm" : "rlwnm"; break;
-		case PPC_HI6_RLWIMI:
-			mnem = power? "rlimi" : "rlwimi"; break;
-		case PPC_HI6_RLWINM:
-			mnem = power? "rlinm" : "rlwinm"; break;
-		}
-		debug("%s%s\tr%i,r%i,%s%i,%i,%i",
-		    mnem, rc?".":"", ra, rs,
-		    hi6 == PPC_HI6_RLWNM? "r" : "",
-		    sh, mb, me);
-		break;
-	case PPC_HI6_ORI:
-	case PPC_HI6_ORIS:
-	case PPC_HI6_XORI:
-	case PPC_HI6_XORIS:
-	case PPC_HI6_ANDI_DOT:
-	case PPC_HI6_ANDIS_DOT:
-		rs = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		imm = iword & 0xffff;
-		switch (hi6) {
-		case PPC_HI6_ORI:
-			mnem = power? "oril":"ori";
-			break;
-		case PPC_HI6_ORIS:
-			mnem = power? "oriu":"oris";
-			break;
-		case PPC_HI6_XORI:
-			mnem = power? "xoril":"xori";
-			break;
-		case PPC_HI6_XORIS:
-			mnem = power? "xoriu":"xoris";
-			break;
-		case PPC_HI6_ANDI_DOT:
-			mnem = power? "andil.":"andi.";
-			break;
-		case PPC_HI6_ANDIS_DOT:
-			mnem = power? "andiu.":"andis.";
-			break;
-		}
-		if (hi6 == PPC_HI6_ORI && rs == 0 && ra == 0 && imm == 0)
-			debug("nop");
-		else
-			debug("%s\tr%i,r%i,0x%04x", mnem, ra, rs, imm);
-		break;
-	case PPC_HI6_30:
-		xo = (iword >> 2) & 7;
-		switch (xo) {
-		case PPC_30_RLDICL:
-		case PPC_30_RLDICR:
-		case PPC_30_RLDIMI:	/*  mb, not me  */
-			mnem = NULL;
-			switch (xo) {
-			case PPC_30_RLDICL: mnem = "rldicl"; break;
-			case PPC_30_RLDICR: mnem = "rldicr"; break;
-			case PPC_30_RLDIMI: mnem = "rldimi"; break;
-			}
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			sh = ((iword >> 11) & 31) | ((iword & 2) << 4);
-			me = ((iword >> 6) & 31) | (iword & 0x20);
-			rc = iword & 1;
-			debug("%s%s\tr%i,r%i,%i,%i",
-			    mnem, rc?".":"", ra, rs, sh, me);
-			break;
-		default:
-			debug("unimplemented hi6_30, xo = 0x%x", xo);
-		}
-		break;
-	case PPC_HI6_31:
-		xo = (iword >> 1) & 1023;
-		switch (xo) {
-
-		case PPC_31_CMP:
-		case PPC_31_CMPL:
-			bf = (iword >> 23) & 7;
-			l_bit = (iword >> 21) & 1;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			if (xo == PPC_31_CMPL)
-				mnem = "cmpl";
-			else
-				mnem = "cmp";
-			debug("%s%s\t", mnem, l_bit? "d" : "w");
-			if (bf != 0)
-				debug("cr%i,", bf);
-			debug("r%i,r%i", ra, rb);
-			break;
-		case PPC_31_MFCR:
-			rt = (iword >> 21) & 31;
-			debug("mfcr\tr%i", rt);
-			break;
-		case PPC_31_MFMSR:
-			rt = (iword >> 21) & 31;
-			debug("mfmsr\tr%i", rt);
-			break;
-		case PPC_31_MTCRF:
-			rs = (iword >> 21) & 31;
-			mb = (iword >> 12) & 255;  /*  actually fxm, not mb  */
-			debug("mtcrf\t%i,r%i", mb, rs);
-			break;
-		case PPC_31_MTMSR:
-			rs = (iword >> 21) & 31;
-			l_bit = (iword >> 16) & 1;
-			debug("mtmsr\tr%i", rs);
-			if (l_bit)
-				debug(",%i", l_bit);
-			break;
-		case PPC_31_TW:
-		case PPC_31_TD:
-			to = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			switch (xo) {
-			case PPC_31_TW: mnem = power? "t" : "tw"; break;
-			case PPC_31_TD: mnem = "td"; break;
-			}
-			debug("%s\t%i,r%i,r%i", mnem, to, ra, rb);
-			break;
-		case PPC_31_LWARX:
-		case PPC_31_LDARX:
-		case PPC_31_LBZX:
-		case PPC_31_LBZUX:
-		case PPC_31_LHAX:
-		case PPC_31_LHAUX:
-		case PPC_31_LHZX:
-		case PPC_31_LHZUX:
-		case PPC_31_LWZX:
-		case PPC_31_LWZUX:
-		case PPC_31_LHBRX:
-		case PPC_31_LWBRX:
-		case PPC_31_LFDX:
-		case PPC_31_LFSX:
-		case PPC_31_STWCX_DOT:
-		case PPC_31_STDCX_DOT:
-		case PPC_31_STBX:
-		case PPC_31_STBUX:
-		case PPC_31_STHX:
-		case PPC_31_STHUX:
-		case PPC_31_STWX:
-		case PPC_31_STWUX:
-		case PPC_31_STDX:
-		case PPC_31_STDUX:
-		case PPC_31_STHBRX:
-		case PPC_31_STWBRX:
-		case PPC_31_STFDX:
-		case PPC_31_STFSX:
-			/*  rs for stores, rt for loads, actually  */
-			load = 0; wlen = 0; fpreg = 0;
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			switch (xo) {
-			case PPC_31_LWARX: wlen=4;load=1; mnem = "lwarx"; break;
-			case PPC_31_LDARX: wlen=8;load=1; mnem = "ldarx"; break;
-			case PPC_31_LBZX:  wlen=1;load=1; mnem = "lbzx"; break;
-			case PPC_31_LBZUX: wlen=1;load=1; mnem = "lbzux"; break;
-			case PPC_31_LHAX:  wlen=2;load=1; mnem = "lhax"; break;
-			case PPC_31_LHAUX: wlen=2;load=1; mnem = "lhaux"; break;
-			case PPC_31_LHZX:  wlen=2;load=1; mnem = "lhzx"; break;
-			case PPC_31_LHZUX: wlen=2;load=1; mnem = "lhzux"; break;
-			case PPC_31_LWZX:  wlen = 4; load = 1;
-				mnem = power? "lx" : "lwzx";
-				break;
-			case PPC_31_LWZUX: wlen = 4; load = 1;
-				mnem = power? "lux":"lwzux";
-				break;
-			case PPC_31_LFDX: fpreg = 1; wlen = 8; load = 1;
-				mnem = "lfdx"; break;
-			case PPC_31_LFSX: fpreg = 1; wlen = 4; load = 1;
-				mnem = "lfsx"; break;
-			case PPC_31_STWCX_DOT: wlen=4; mnem = "stwcx."; break;
-			case PPC_31_STDCX_DOT: wlen=8; mnem = "stdcx."; break;
-			case PPC_31_STBX:  wlen=1; mnem = "stbx"; break;
-			case PPC_31_STBUX: wlen=1; mnem = "stbux"; break;
-			case PPC_31_STHX:  wlen=2; mnem = "sthx"; break;
-			case PPC_31_STHUX: wlen=2; mnem = "sthux"; break;
-			case PPC_31_STWX:
-				wlen = 4; mnem = power? "stx" : "stwx";
-				break;
-			case PPC_31_STWUX:
-				wlen = 4; mnem = power? "stux" : "stwux";
-				break;
-			case PPC_31_STDX:  wlen = 8; mnem = "stdx"; break;
-			case PPC_31_STDUX: wlen = 8; mnem = "stdux"; break;
-			case PPC_31_LHBRX:  wlen = 2; mnem = "lhbrx"; break;
-			case PPC_31_LWBRX:  wlen = 4; mnem = power?
-					    "lbrx" : "lwbrx"; break;
-			case PPC_31_STHBRX: wlen = 2; mnem = "sthbrx"; break;
-			case PPC_31_STWBRX: wlen = 4; mnem = power?
-					    "stbrx" : "stwbrx"; break;
-			case PPC_31_STFDX: fpreg = 1; wlen = 8;
-				mnem = "stfdx"; break;
-			case PPC_31_STFSX: fpreg = 1; wlen = 4;
-				mnem = "stfsx"; break;
-			}
-			debug("%s\t%s%i,r%i,r%i", mnem,
-			    fpreg? "f" : "r", rs, ra, rb);
-			if (!running)
-				break;
-			addr = (ra==0? 0 : cpu->cd.ppc.gpr[ra]) +
-			    cpu->cd.ppc.gpr[rb];
-			if (cpu->cd.ppc.bits == 32)
-				addr &= 0xffffffff;
-			symbol = get_symbol_name(&cpu->machine->symbol_context,
-			    addr, &offset);
-			if (symbol != NULL)
-				debug(" \t<%s", symbol);
-			else
-				debug(" \t<0x%" PRIx64, (uint64_t) addr);
-			if (wlen > 0 && !fpreg /* && !reverse */) {
-				/*  TODO  */
-			}
-			debug(">");
-			break;
-		case PPC_31_NEG:
-		case PPC_31_NEGO:
-			rt = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			// oe_bit = (iword >> 10) & 1;
-			rc = iword & 1;
-			switch (xo) {
-			case PPC_31_NEG:  mnem = "neg"; break;
-			case PPC_31_NEGO: mnem = "nego"; break;
-			}
-			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra);
-			break;
-		case PPC_31_WRTEEI:
-			debug("wrteei\t%i", iword & 0x8000? 1 : 0);
-			break;
-		case PPC_31_MTMSRD:
-			/*  TODO: Just a guess based on MTMSR  */
-			rs = (iword >> 21) & 31;
-			l_bit = (iword >> 16) & 1;
-			debug("mtmsrd\tr%i", rs);
-			if (l_bit)
-				debug(",%i", l_bit);
-			break;
-		case PPC_31_ADDZE:
-		case PPC_31_ADDZEO:
-			rt = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			// oe_bit = (iword >> 10) & 1;
-			rc = iword & 1;
-			switch (xo) {
-			case PPC_31_ADDZE:
-				mnem = power? "aze" : "addze";
-				break;
-			case PPC_31_ADDZEO:
-				mnem = power? "azeo" : "addzeo";
-				break;
-			}
-			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra);
-			break;
-		case PPC_31_MTSR:
-		case PPC_31_MFSR:
-			/*  Move to/from segment register  */
-			rt = (iword >> 21) & 31;
-			ra = (iword >> 16) & 15;	/*  actually: sr  */
-			switch (xo) {
-			case PPC_31_MTSR:  mnem = "mtsr"; break;
-			case PPC_31_MFSR:  mnem = "mfsr"; break;
-			}
-			debug("%s\tr%i,%i", mnem, rt, ra);
-			break;
-		case PPC_31_MTSRIN:
-		case PPC_31_MFSRIN:
-			/*  Move to/from segment register indirect  */
-			rt = (iword >> 21) & 31;
-			rb = (iword >> 11) & 31;
-			switch (xo) {
-			case PPC_31_MTSRIN:  mnem = "mtsrin"; break;
-			case PPC_31_MFSRIN:  mnem = "mfsrin"; break;
-			}
-			debug("%s\tr%i,r%i", mnem, rt, rb);
-			break;
-		case PPC_31_ADDC:
-		case PPC_31_ADDCO:
-		case PPC_31_ADDE:
-		case PPC_31_ADDEO:
-		case PPC_31_ADDME:
-		case PPC_31_ADDMEO:
-		case PPC_31_ADD:
-		case PPC_31_ADDO:
-		case PPC_31_MULHW:
-		case PPC_31_MULHWU:
-		case PPC_31_MULLW:
-		case PPC_31_MULLWO:
-		case PPC_31_SUBF:
-		case PPC_31_SUBFO:
-		case PPC_31_SUBFC:
-		case PPC_31_SUBFCO:
-		case PPC_31_SUBFE:
-		case PPC_31_SUBFEO:
-		case PPC_31_SUBFME:
-		case PPC_31_SUBFMEO:
-		case PPC_31_SUBFZE:
-		case PPC_31_SUBFZEO:
-			rt = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			// oe_bit = (iword >> 10) & 1;
-			rc = iword & 1;
-			switch (xo) {
-			case PPC_31_ADDC:
-				mnem = power? "a" : "addc";
-				break;
-			case PPC_31_ADDCO:
-				mnem = power? "ao" : "addco";
-				break;
-			case PPC_31_ADDE:
-				mnem = power? "ae" : "adde";
-				break;
-			case PPC_31_ADDEO:
-				mnem = power? "aeo" : "addeo";
-				break;
-			case PPC_31_ADDME:
-				mnem = power? "ame" : "addme";
-				no_rb = 1;
-				break;
-			case PPC_31_ADDMEO:
-				mnem = power? "ameo" : "addmeo";
-				no_rb = 1;
-				break;
-			case PPC_31_ADD:
-				mnem = power? "cax" : "add";
-				break;
-			case PPC_31_ADDO:
-				mnem = power? "caxo" : "addo";
-				break;
-			case PPC_31_MULHW:  mnem = "mulhw"; break;
-			case PPC_31_MULHWU: mnem = "mulhwu"; break;
-			case PPC_31_MULLW:
-				mnem = power? "muls" : "mullw";
-				break;
-			case PPC_31_MULLWO:
-				mnem = power? "mulso" : "mullwo";
-				break;
-			case PPC_31_SUBF:   mnem = "subf"; break;
-			case PPC_31_SUBFO:  mnem = "subfo"; break;
-			case PPC_31_SUBFC:
-				mnem = power? "sf" : "subfc"; break;
-			case PPC_31_SUBFCO:
-				mnem = power? "sfo" : "subfco"; break;
-			case PPC_31_SUBFE:
-				mnem = power? "sfe" : "subfe"; break;
-			case PPC_31_SUBFEO:
-				mnem = power? "sfeo" : "subfeo"; break;
-			case PPC_31_SUBFME:
-				mnem = power? "sfme" : "subfme"; break;
-			case PPC_31_SUBFMEO:
-				mnem = power? "sfmeo" : "subfmeo"; break;
-			case PPC_31_SUBFZE:
-				mnem = power? "sfze" : "subfze";
-				no_rb = 1;
-				break;
-			case PPC_31_SUBFZEO:
-				mnem = power? "sfzeo" : "subfzeo";
-				no_rb = 1;
-				break;
-			}
-			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra);
-			if (!no_rb)
-				debug(",r%i", rb);
-			break;
-		case PPC_31_MFSPR:
-			rt = (iword >> 21) & 31;
-			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
-			switch (spr) {
-			/*  Some very common ones:  */
-			case 8:	   debug("mflr\tr%i", rt); break;
-			case 9:	   debug("mfctr\tr%i", rt); break;
-			default:debug("mfspr\tr%i,spr%i", rt, spr);
-			}
-			if (spr == 8 || spr == 9)
-				debug("\t");
-			debug("\t<%s%s", running? "read from " : "",
-			    ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]);
-			if (running) {
-				if (cpu->cd.ppc.bits == 32)
-					debug(": 0x%" PRIx32, (uint32_t)
-					    cpu->cd.ppc.spr[spr]);
-				else
-					debug(": 0x%" PRIx64, (uint64_t)
-					    cpu->cd.ppc.spr[spr]);
-			}
-			debug(">");
-			break;
-		case PPC_31_TLBIA:
-			debug("tlbia");
-			break;
-		case PPC_31_SLBIA:
-			debug("slbia");
-			break;
-		case PPC_31_TLBLD:
-		case PPC_31_TLBLI:
-			rb = (iword >> 11) & 31;
-			debug("tlbl%s\tr%i", xo == PPC_31_TLBLD? "d" : "i", rb);
-			break;
-		case PPC_31_TLBIE:
-			/*  TODO: what is ra? The IBM online docs didn't say  */
-			ra = 0;
-			rb = (iword >> 11) & 31;
-			if (power)
-				debug("tlbi\tr%i,r%i", ra, rb);
-			else
-				debug("tlbie\tr%i", rb);
-			break;
-		case PPC_31_TLBSX_DOT:
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			debug("tlbsx.\tr%i,r%i,r%i", rs, ra, rb);
-			break;
-		case PPC_31_TLBSYNC:
-			debug("tlbsync");
-			break;
-		case PPC_31_MFTB:
-			rt = (iword >> 21) & 31;
-			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
-			debug("mftb%s\tr%i", spr==268? "" :
-			    (spr==269? "u" : "?"), rt);
-			break;
-		case PPC_31_CNTLZW:
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rc = iword & 1;
-			mnem = power? "cntlz" : "cntlzw";
-			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs);
-			break;
-		case PPC_31_CLF:	/*  POWER only  */
-		case PPC_31_CLI:	/*  POWER only  */
-		case PPC_31_DCLST:	/*  POWER only  */
-		case PPC_31_DCBF:	/*  PowerPC only  */
-		case PPC_31_DCBI:	/*  PowerPC only  */
-		case PPC_31_DCBST:	/*  PowerPC only  */
-		case PPC_31_DCBTST:	/*  PowerPC only  */
-		case PPC_31_DCBT:	/*  PowerPC only  */
-		case PPC_31_ICBI:	/*  PowerPC only  */
-		case PPC_31_DCBZ:	/*  POWER/PowerPC  */
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			switch (xo) {
-			case PPC_31_CLF:   mnem = "clf"; break;
-			case PPC_31_CLI:   mnem = "cli"; break;
-			case PPC_31_DCLST: mnem = "dclst"; break;
-			case PPC_31_DCBF:  mnem = "dcbf"; break;
-			case PPC_31_DCBI:  mnem = "dcbi"; break;
-			case PPC_31_DCBST: mnem = "dcbst"; break;
-			case PPC_31_DCBTST:mnem = "dcbtst"; break;
-			case PPC_31_DCBT:  mnem = "dcbt"; break;
-			case PPC_31_ICBI:  mnem = "icbi"; break;
-			case PPC_31_DCBZ:  mnem = power ?
-					   "dclz" : "dcbz"; break;
-			}
-			debug("%s\tr%i,r%i", mnem, ra, rb);
-			break;
-		case PPC_31_SLW:
-		case PPC_31_SLD:
-		case PPC_31_SRAW:
-		case PPC_31_SRW:
-		case PPC_31_AND:
-		case PPC_31_ANDC:
-		case PPC_31_NOR:
-		case PPC_31_EQV:
-		case PPC_31_OR:
-		case PPC_31_ORC:
-		case PPC_31_XOR:
-		case PPC_31_NAND:
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			rc = iword & 1;
-			if (rs == rb && xo == PPC_31_OR)
-				debug("mr%s\tr%i,r%i", rc? "." : "", ra, rs);
-			else {
-				switch (xo) {
-				case PPC_31_SLW:  mnem =
-					power? "sl" : "slw"; break;
-				case PPC_31_SLD:  mnem = "sld"; break;
-				case PPC_31_SRAW:  mnem =
-					power? "sra" : "sraw"; break;
-				case PPC_31_SRW:  mnem =
-					power? "sr" : "srw"; break;
-				case PPC_31_AND:  mnem = "and"; break;
-				case PPC_31_NAND: mnem = "nand"; break;
-				case PPC_31_ANDC: mnem = "andc"; break;
-				case PPC_31_NOR:  mnem = "nor"; break;
-				case PPC_31_EQV:  mnem = "eqv"; break;
-				case PPC_31_OR:   mnem = "or"; break;
-				case PPC_31_ORC:  mnem = "orc"; break;
-				case PPC_31_XOR:  mnem = "xor"; break;
-				}
-				debug("%s%s\tr%i,r%i,r%i", mnem,
-				    rc? "." : "", ra, rs, rb);
-			}
-			break;
-		case PPC_31_DCCCI:
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			debug("dccci\tr%i,r%i", ra, rb);
-			break;
-		case PPC_31_ICCCI:
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			debug("iccci\tr%i,r%i", ra, rb);
-			break;
-		case PPC_31_DIVW:
-		case PPC_31_DIVWO:
-		case PPC_31_DIVWU:
-		case PPC_31_DIVWUO:
-			rt = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			// oe_bit = (iword >> 10) & 1;
-			rc = iword & 1;
-			switch (xo) {
-			case PPC_31_DIVWU:  mnem = "divwu"; break;
-			case PPC_31_DIVWUO: mnem = "divwuo"; break;
-			case PPC_31_DIVW:   mnem = "divw"; break;
-			case PPC_31_DIVWO:  mnem = "divwo"; break;
-			}
-			debug("%s%s\tr%i,r%i,r%i", mnem, rc? "." : "",
-			    rt, ra, rb);
-			break;
-		case PPC_31_MTSPR:
-			rs = (iword >> 21) & 31;
-			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
-			switch (spr) {
-			/*  Some very common ones:  */
-			case 8:	   debug("mtlr\tr%i", rs); break;
-			case 9:	   debug("mtctr\tr%i", rs); break;
-			default:debug("mtspr\tspr%i,r%i", spr, rs);
-			}
-			if (spr == 8 || spr == 9)
-				debug("\t");
-			debug("\t<%s%s", running? "write to " : "",
-			    ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]);
-			if (running) {
-				if (cpu->cd.ppc.bits == 32)
-					debug(": 0x%" PRIx32, (uint32_t)
-					    cpu->cd.ppc.gpr[rs]);
-				else
-					debug(": 0x%" PRIx64, (uint64_t)
-					    cpu->cd.ppc.gpr[rs]);
-			}
-			debug(">");
-			break;
-		case PPC_31_SYNC:
-			debug("%s", power? "dcs" : "sync");
-			break;
-		case PPC_31_LSWI:
-		case PPC_31_STSWI:
-			rs = (iword >> 21) & 31;	/*  lwsi uses rt  */
-			ra = (iword >> 16) & 31;
-			nb = (iword >> 11) & 31;
-			switch (xo) {
-			case PPC_31_LSWI:
-				mnem = power? "lsi" : "lswi"; break;
-			case PPC_31_STSWI:
-				mnem = power? "stsi" : "stswi"; break;
-			}
-			debug("%s\tr%i,r%i,%i", mnem, rs, ra, nb);
-			break;
-		case PPC_31_SRAWI:
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			sh = (iword >> 11) & 31;
-			rc = iword & 1;
-			mnem = power? "srai" : "srawi";
-			debug("%s%s\tr%i,r%i,%i", mnem,
-			    rc? "." : "", ra, rs, sh);
-			break;
-		case PPC_31_DSSALL:
-			debug("dssall");
-			break;
-		case PPC_31_EIEIO:
-			debug("%s", power? "eieio?" : "eieio");
-			break;
-		case PPC_31_EXTSB:
-		case PPC_31_EXTSH:
-		case PPC_31_EXTSW:
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rc = iword & 1;
-			switch (xo) {
-			case PPC_31_EXTSB:
-				mnem = power? "exts" : "extsb";
-				break;
-			case PPC_31_EXTSH:
-				mnem = "extsh";
-				break;
-			case PPC_31_EXTSW:
-				mnem = "extsw";
-				break;
-			}
-			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs);
-			break;
-		case PPC_31_LVX:
-		case PPC_31_LVXL:
-		case PPC_31_STVX:
-		case PPC_31_STVXL:
-			rs = (iword >> 21) & 31;	/*  vs for stores,  */
-			ra = (iword >> 16) & 31;	/*  rs=vl for loads  */
-			rb = (iword >> 11) & 31;
-			rc = iword & 1;
-			switch (xo) {
-			case PPC_31_LVX:   mnem = "lvx";  break;
-			case PPC_31_LVXL:  mnem = "lvxl"; break;
-			case PPC_31_STVX:  mnem = "stvx";  break;
-			case PPC_31_STVXL: mnem = "stvxl"; break;
-			}
-			debug("%s%s\tv%i,r%i,r%i", mnem, rc? "." : "",
-			    rs, ra, rb);
-			break;
-		default:
-			debug("unimplemented hi6_31, xo = 0x%x", xo);
-		}
-		break;
-	case PPC_HI6_LD:
-	case PPC_HI6_LWZ:
-	case PPC_HI6_LWZU:
-	case PPC_HI6_LHZ:
-	case PPC_HI6_LHZU:
-	case PPC_HI6_LHA:
-	case PPC_HI6_LHAU:
-	case PPC_HI6_LBZ:
-	case PPC_HI6_LBZU:
-	case PPC_HI6_LFD:
-	case PPC_HI6_LFS:
-	case PPC_HI6_LMW:
-	case PPC_HI6_STD:
-	case PPC_HI6_STW:
-	case PPC_HI6_STWU:
-	case PPC_HI6_STH:
-	case PPC_HI6_STHU:
-	case PPC_HI6_STB:
-	case PPC_HI6_STBU:
-	case PPC_HI6_STMW:
-	case PPC_HI6_STFD:
-	case PPC_HI6_STFS:
-		/*  NOTE: Loads use rt, not rs, but are otherwise similar
-		    to stores  */
-		load = 0; wlen = 0;
-		rs = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		imm = (int16_t)(iword & 0xffff);
-		fpreg = 0;
-		switch (hi6) {
-		case PPC_HI6_LD:  load=1; wlen = 8; mnem = "ld"; break;
-		case PPC_HI6_LWZ:  load=1; wlen = 4;
-			mnem = power? "l" : "lwz"; break;
-		case PPC_HI6_LWZU: load=1; wlen = 4;
-			mnem = power? "lu" : "lwzu"; break;
-		case PPC_HI6_LHZ:  load=1; wlen = 2;
-			mnem = "lhz"; break;
-		case PPC_HI6_LHZU: load=1; wlen = 2;
-			mnem = "lhzu"; break;
-		case PPC_HI6_LHA:  load=2; wlen = 2;
-			mnem = "lha"; break;
-		case PPC_HI6_LHAU: load=2; wlen = 2;
-			mnem = "lhau"; break;
-		case PPC_HI6_LBZ:  load=1; wlen = 1;
-			mnem = "lbz"; break;
-		case PPC_HI6_LBZU: load=1; wlen = 1;
-			mnem = "lbzu"; break;
-		case PPC_HI6_LFD:  load=1; fpreg=1; wlen=8; mnem = "lfd"; break;
-		case PPC_HI6_LFS:  load=1; fpreg=1; wlen=4; mnem = "lfs"; break;
-		case PPC_HI6_STD:  wlen=8; mnem = "std"; break;
-		case PPC_HI6_STW:  wlen=4; mnem = power? "st" : "stw"; break;
-		case PPC_HI6_STWU: wlen=4; mnem = power? "stu" : "stwu"; break;
-		case PPC_HI6_STH:  wlen=2; mnem = "sth"; break;
-		case PPC_HI6_STHU: wlen=2; mnem = "sthu"; break;
-		case PPC_HI6_STB:  wlen=1; mnem = "stb"; break;
-		case PPC_HI6_STBU: wlen=1; mnem = "stbu"; break;
-		case PPC_HI6_LMW:  load=1; mnem = power? "lm" : "lmw"; break;
-		case PPC_HI6_STMW: mnem = power? "stm" : "stmw"; break;
-		case PPC_HI6_STFD: fpreg=1; wlen=8; mnem = "stfd"; break;
-		case PPC_HI6_STFS: fpreg=1; wlen=4; mnem = "stfs"; break;
-		}
-		debug("%s\t", mnem);
-		if (fpreg)
-			debug("f");
-		else
-			debug("r");
-		debug("%i,%i(r%i)", rs, imm, ra);
-		if (!running)
-			break;
-		addr = (ra==0? 0 : cpu->cd.ppc.gpr[ra]) + imm;
-		if (cpu->cd.ppc.bits == 32)
-			addr &= 0xffffffff;
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    addr, &offset);
-		if (symbol != NULL)
-			debug(" \t<%s", symbol);
-		else
-			debug(" \t<0x%" PRIx64, (uint64_t) addr);
-		if (wlen > 0 && load && wlen > 0) {
-			unsigned char tw[8];
-			uint64_t tdata = 0;
-			int i, res = cpu->memory_rw(cpu, cpu->mem, addr, tw,
-			    wlen, MEM_READ, NO_EXCEPTIONS);
-			if (res) {
-				if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-					for (i=0; i<wlen; i++) {
-						tdata <<= 8;
-						tdata |= tw[wlen-1-i];
-					}
-				else
-					for (i=0; i<wlen; i++) {
-						tdata <<= 8;
-						tdata |= tw[i];
-					}
-				debug(": ");
-				if (wlen >= 4) {
-					symbol = get_symbol_name(&cpu->machine->
-					    symbol_context, tdata, &offset);
-					if (symbol != NULL)
-						debug("%s", symbol);
-					else
-						debug("0x%" PRIx64,
-						    (uint64_t) tdata);
-				} else {
-					/*  TODO: if load==2, then this is
-					    a _signed_ load.  */
-					debug("0x%" PRIx64, (uint64_t) tdata);
-				}
-			} else
-				debug(": unreadable");
-		}
-		if (wlen > 0 && !load && wlen > 0) {
-			int64_t tdata = 0;
-			int i;
-			for (i=0; i<wlen; i++)
-				tdata |= (cpu->cd.ppc.gpr[rs] &
-				    ((uint64_t)0xff << (i*8)));
-			debug(": ");
-			if (wlen >= 4) {
-				symbol = get_symbol_name(&cpu->machine->
-				    symbol_context, tdata, &offset);
-				if (symbol != NULL)
-					debug("%s", symbol);
-				else
-					debug("0x%" PRIx64, (uint64_t) tdata);
-			} else {
-				if (tdata > -256 && tdata < 256)
-					debug("%i", (int)tdata);
-				else
-					debug("0x%" PRIx64, (uint64_t) tdata);
-			}
-		}
-		debug(">");
-		break;
-	case PPC_HI6_59:
-		xo = (iword >> 1) & 1023;
-		/*  NOTE: Some floating point instructions only use the
-		    lowest 5 bits of xo, some use all 10 bits!  */
-		switch (xo & 31) {
-		case PPC_59_FDIVS:
-		case PPC_59_FSUBS:
-		case PPC_59_FADDS:
-		case PPC_59_FMULS:
-		case PPC_59_FMADDS:
-			rt = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			rs = (iword >>  6) & 31;	/*  actually frc  */
-			rc = iword & 1;
-			switch (xo & 31) {
-			case PPC_59_FDIVS:	mnem = "fdivs"; break;
-			case PPC_59_FSUBS:	mnem = "fsubs"; break;
-			case PPC_59_FADDS:	mnem = "fadds"; break;
-			case PPC_59_FMULS:	mnem = "fmuls"; break;
-			case PPC_59_FMADDS:	mnem = "fmadds"; break;
-			}
-			debug("%s%s\t", mnem, rc? "." : "");
-			switch (xo & 31) {
-			case PPC_59_FMULS:
-				debug("f%i,f%i,f%i", rt, ra, rs);
-				break;
-			case PPC_59_FMADDS:
-				debug("f%i,f%i,f%i,f%i", rt, ra, rs, rb);
-				break;
-			default:debug("f%i,f%i,f%i", rt, ra, rb);
-			}
-			break;
-		default:/*  TODO: similar to hi6_63  */
-			debug("unimplemented hi6_59, xo = 0x%x", xo);
-		}
-		break;
-	case PPC_HI6_63:
-		xo = (iword >> 1) & 1023;
-		/*  NOTE: Some floating point instructions only use the
-		    lowest 5 bits of xo, some use all 10 bits!  */
-		switch (xo & 31) {
-		case PPC_63_FDIV:
-		case PPC_63_FSUB:
-		case PPC_63_FADD:
-		case PPC_63_FMUL:
-		case PPC_63_FMSUB:
-		case PPC_63_FMADD:
-			rt = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			rs = (iword >>  6) & 31;	/*  actually frc  */
-			rc = iword & 1;
-			switch (xo & 31) {
-			case PPC_63_FDIV:
-				mnem = power? "fd" : "fdiv"; break;
-			case PPC_63_FSUB:
-				mnem = power? "fs" : "fsub"; break;
-			case PPC_63_FADD:
-				mnem = power? "fa" : "fadd"; break;
-			case PPC_63_FMUL:
-				mnem = power? "fm" : "fmul"; break;
-			case PPC_63_FMSUB:
-				mnem = power? "fms" : "fmsub"; break;
-			case PPC_63_FMADD:
-				mnem = power? "fma" : "fmadd"; break;
-			}
-			debug("%s%s\t", mnem, rc? "." : "");
-			switch (xo & 31) {
-			case PPC_63_FMUL:
-				debug("f%i,f%i,f%i", rt, ra, rs);
-				break;
-			case PPC_63_FMADD:
-				debug("f%i,f%i,f%i,f%i", rt, ra, rs, rb);
-				break;
-			default:debug("f%i,f%i,f%i", rt, ra, rb);
-			}
-			break;
-		default:rt = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			rc = iword & 1;
-			switch (xo) {
-			case PPC_63_FCMPU:
-			case PPC_63_FRSP:
-			case PPC_63_FCTIWZ:
-			case PPC_63_FNEG:
-			case PPC_63_FMR:
-			case PPC_63_FNABS:
-			case PPC_63_FABS:
-				switch (xo) {
-				case PPC_63_FCMPU:	mnem = "fcmpu"; break;
-				case PPC_63_FCTIWZ:
-					mnem = power? "fcirz" : "fctiwz"; break;
-				case PPC_63_FRSP:	mnem = "frsp"; break;
-				case PPC_63_FNEG:	mnem = "fneg"; break;
-				case PPC_63_FMR:	mnem = "fmr"; break;
-				case PPC_63_FNABS:	mnem = "fnabs"; break;
-				case PPC_63_FABS:	mnem = "fabs"; break;
-				}
-				debug("%s%s\t", mnem, rc? "." : "");
-				switch (xo) {
-				case PPC_63_FCMPU:
-					debug("%i,f%i,f%i", rt >> 2, ra, rb);
-					break;
-				case PPC_63_FCTIWZ:
-				case PPC_63_FRSP:
-				case PPC_63_FNEG:
-				case PPC_63_FMR:
-				case PPC_63_FNABS:
-				case PPC_63_FABS:
-					debug("f%i,f%i", rt, rb);
-					break;
-				default:debug("f%i,f%i,f%i", rt, ra, rb);
-				}
-				break;
-			case PPC_63_MFFS:
-				debug("mffs%s\tf%i", rc?".":"", rt);
-				break;
-			case PPC_63_MTFSF:
-				ra = (iword >> 17) & 255;	/*  flm  */
-				debug("mtfsf%s\t0x%02x,f%i", rc?".":"", ra, rb);
-				break;
-			default:debug("unimplemented hi6_63, xo = 0x%x", xo);
-			}
-		}
-		break;
-	default:
-		/*  TODO  */
-		debug("unimplemented hi6 = 0x%02x", hi6);
-	}
-
-	debug("\n");
-	return sizeof(iword);
-}
-
-
-/*
- *  debug_spr_usage():
- *
- *  Helper function. To speed up overall development speed of the emulator,
- *  all SPR accesses are allowed. This function causes unknown/unimplemented
- *  SPRs to give a warning.
- */
-static void debug_spr_usage(uint64_t pc, int spr)
-{
-	static uint32_t spr_used[1024 / sizeof(uint32_t)];
-	static int initialized = 0;
-
-	if (!initialized) {
-		memset(spr_used, 0, sizeof(spr_used));
-		initialized = 1;
-	}
-
-	spr &= 1023;
-	if (spr_used[spr >> 2] & (1 << (spr & 3)))
-		return;
-
-	switch (spr) {
-	/*  Known/implemented SPRs:  */
-	case SPR_XER:
-	case SPR_LR:
-	case SPR_CTR:
-	case SPR_DSISR:
-	case SPR_DAR:
-	case SPR_DEC:
-	case SPR_SDR1:
-	case SPR_SRR0:
-	case SPR_SRR1:
-	case SPR_SPRG0:
-	case SPR_SPRG1:
-	case SPR_SPRG2:
-	case SPR_SPRG3:
-	case SPR_PVR:
-	case SPR_DMISS:
-	case SPR_DCMP:
-	case SPR_HASH1:
-	case SPR_HASH2:
-	case SPR_IMISS:
-	case SPR_ICMP:
-	case SPR_DBSR:
-	case SPR_PIR:
-		break;
-	default:if (spr >= SPR_IBAT0U && spr <= SPR_DBAT3L) {
-			break;
-		} else
-			fatal("[ using UNIMPLEMENTED spr %i (%s), pc = "
-			    "0x%" PRIx64" ]\n", spr, ppc_spr_names[spr] == NULL?
-			    "UNKNOWN" : ppc_spr_names[spr], (uint64_t) pc);
-	}
-
-	spr_used[spr >> 2] |= (1 << (spr & 3));
-}
-
-
-/*
- *  update_cr0():
- *
- *  Sets the top 4 bits of the CR register.
- */
-void update_cr0(struct cpu *cpu, uint64_t value)
-{
-	int c;
-
-	if (cpu->cd.ppc.bits == 64) {
-		if ((int64_t)value < 0)
-			c = 8;
-		else if ((int64_t)value > 0)
-			c = 4;
-		else
-			c = 2;
-	} else {
-		if ((int32_t)value < 0)
-			c = 8;
-		else if ((int32_t)value > 0)
-			c = 4;
-		else
-			c = 2;
-	}
-
-	/*  SO bit, copied from XER:  */
-	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
-
-	cpu->cd.ppc.cr &= ~((uint32_t)0xf << 28);
-	cpu->cd.ppc.cr |= ((uint32_t)c << 28);
-}
-
-
-#include "memory_ppc.cc"
-
-
-#include "tmp_ppc_tail.cc"
-
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_ppc_instr.c gxemul-0.7.0+dfsg/src/cpus/cpu_ppc_instr.c
--- gxemul-0.6.2/src/cpus/cpu_ppc_instr.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_ppc_instr.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,3903 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  POWER/PowerPC instructions.
+ *
+ *  Individual functions should keep track of cpu->n_translated_instrs.
+ *  (If no instruction was executed, then it should be decreased. If, say, 4
+ *  instructions were combined into one function and executed, then it should
+ *  be increased by 3.)
+ */
+
+
+#include "float_emul.h"
+
+
+#define DOT0(n) X(n ## _dot) { instr(n)(cpu,ic); \
+	update_cr0(cpu, reg(ic->arg[0])); }
+#define DOT1(n) X(n ## _dot) { instr(n)(cpu,ic); \
+	update_cr0(cpu, reg(ic->arg[1])); }
+#define DOT2(n) X(n ## _dot) { instr(n)(cpu,ic); \
+	update_cr0(cpu, reg(ic->arg[2])); }
+
+#ifndef CHECK_FOR_FPU_EXCEPTION
+#define CHECK_FOR_FPU_EXCEPTION { if (!(cpu->cd.ppc.msr & PPC_MSR_FP)) { \
+		/*  Synchronize the PC, and cause an FPU exception:  */  \
+		uint64_t low_pc = ((size_t)ic -				 \
+		    (size_t)cpu->cd.ppc.cur_ic_page)			 \
+		    / sizeof(struct ppc_instr_call);			 \
+		cpu->pc = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) <<	 \
+		    PPC_INSTR_ALIGNMENT_SHIFT)) + (low_pc <<		 \
+		    PPC_INSTR_ALIGNMENT_SHIFT);				 \
+		ppc_exception(cpu, PPC_EXCEPTION_FPU);			 \
+		return; } }
+#endif
+
+
+
+/*
+ *  nop:  Do nothing.
+ */
+X(nop)
+{
+}
+
+
+/*
+ *  invalid:  To catch bugs.
+ */
+X(invalid)
+{
+	fatal("PPC: invalid(): INTERNAL ERROR\n");
+	exit(1);
+}
+
+
+/*
+ *  addi:  Add immediate.
+ *
+ *  arg[0] = pointer to source uint64_t
+ *  arg[1] = immediate value (int32_t or larger)
+ *  arg[2] = pointer to destination uint64_t
+ */
+X(addi)
+{
+	reg(ic->arg[2]) = reg(ic->arg[0]) + (int32_t)ic->arg[1];
+}
+X(li)
+{
+	reg(ic->arg[2]) = (int32_t)ic->arg[1];
+}
+X(li_0)
+{
+	reg(ic->arg[2]) = 0;
+}
+
+
+/*
+ *  andi_dot:  AND immediate, update CR.
+ *
+ *  arg[0] = pointer to source uint64_t
+ *  arg[1] = immediate value (uint32_t)
+ *  arg[2] = pointer to destination uint64_t
+ */
+X(andi_dot)
+{
+	MODE_uint_t tmp = reg(ic->arg[0]) & (uint32_t)ic->arg[1];
+	reg(ic->arg[2]) = tmp;
+	update_cr0(cpu, tmp);
+}
+
+
+/*
+ *  addic:  Add immediate, Carry.
+ *
+ *  arg[0] = pointer to source register
+ *  arg[1] = immediate value (int32_t or larger)
+ *  arg[2] = pointer to destination register
+ */
+X(addic)
+{
+	/*  TODO/NOTE: Only for 32-bit mode, so far!  */
+	uint64_t tmp = (uint32_t)reg(ic->arg[0]);
+	uint64_t tmp2 = tmp;
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	tmp2 += (uint32_t)ic->arg[1];
+	if ((tmp2 >> 32) != (tmp >> 32))
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	reg(ic->arg[2]) = (uint32_t)tmp2;
+}
+
+
+/*
+ *  subfic:  Subtract from immediate, Carry.
+ *
+ *  arg[0] = pointer to source uint64_t
+ *  arg[1] = immediate value (int32_t or larger)
+ *  arg[2] = pointer to destination uint64_t
+ */
+X(subfic)
+{
+	MODE_uint_t tmp = (int64_t)(int32_t)ic->arg[1];
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	if (tmp >= reg(ic->arg[0]))
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	reg(ic->arg[2]) = tmp - reg(ic->arg[0]);
+}
+
+
+/*
+ *  addic_dot:  Add immediate, Carry.
+ *
+ *  arg[0] = pointer to source uint64_t
+ *  arg[1] = immediate value (int32_t or larger)
+ *  arg[2] = pointer to destination uint64_t
+ */
+X(addic_dot)
+{
+	/*  TODO/NOTE: Only for 32-bit mode, so far!  */
+	uint64_t tmp = (uint32_t)reg(ic->arg[0]);
+	uint64_t tmp2 = tmp;
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	tmp2 += (uint32_t)ic->arg[1];
+	if ((tmp2 >> 32) != (tmp >> 32))
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	reg(ic->arg[2]) = (uint32_t)tmp2;
+	update_cr0(cpu, (uint32_t)tmp2);
+}
+
+
+/*
+ *  bclr:  Branch Conditional to Link Register
+ *
+ *  arg[0] = bo
+ *  arg[1] = 31 - bi
+ *  arg[2] = bh
+ */
+X(bclr)
+{
+	unsigned int bo = ic->arg[0], bi31m = ic->arg[1];
+	int ctr_ok, cond_ok;
+	uint64_t old_pc = cpu->pc;
+	MODE_uint_t tmp, addr = cpu->cd.ppc.spr[SPR_LR];
+	if (!(bo & 4))
+		cpu->cd.ppc.spr[SPR_CTR] --;
+	ctr_ok = (bo >> 2) & 1;
+	tmp = cpu->cd.ppc.spr[SPR_CTR];
+	ctr_ok |= ( (tmp == 0) == ((bo >> 1) & 1) );
+	cond_ok = (bo >> 4) & 1;
+	cond_ok |= ( ((bo >> 3) & 1) == ((cpu->cd.ppc.cr >> bi31m) & 1) );
+	if (ctr_ok && cond_ok) {
+		uint64_t mask_within_page =
+		    ((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT)
+		    | ((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
+		cpu->pc = addr & ~((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
+		/*  TODO: trace in separate (duplicate) function?  */
+		if (cpu->machine->show_trace_tree)
+			cpu_functioncall_trace_return(cpu);
+		if ((old_pc  & ~mask_within_page) ==
+		    (cpu->pc & ~mask_within_page)) {
+			cpu->cd.ppc.next_ic =
+			    cpu->cd.ppc.cur_ic_page +
+			    ((cpu->pc & mask_within_page) >>
+			    PPC_INSTR_ALIGNMENT_SHIFT);
+		} else {
+			/*  Find the new physical page and update pointers:  */
+			quick_pc_to_pointers(cpu);
+		}
+	}
+}
+X(bclr_20)
+{
+	cpu->pc = cpu->cd.ppc.spr[SPR_LR];
+	quick_pc_to_pointers(cpu);
+}
+X(bclr_l)
+{
+	uint64_t low_pc, old_pc = cpu->pc;
+	unsigned int bo = ic->arg[0], bi31m = ic->arg[1]  /* ,bh = ic->arg[2]*/;
+	int ctr_ok, cond_ok;
+	MODE_uint_t tmp, addr = cpu->cd.ppc.spr[SPR_LR];
+	if (!(bo & 4))
+		cpu->cd.ppc.spr[SPR_CTR] --;
+	ctr_ok = (bo >> 2) & 1;
+	tmp = cpu->cd.ppc.spr[SPR_CTR];
+	ctr_ok |= ( (tmp == 0) == ((bo >> 1) & 1) );
+	cond_ok = (bo >> 4) & 1;
+	cond_ok |= ( ((bo >> 3) & 1) == ((cpu->cd.ppc.cr >> bi31m) & 1) );
+
+	/*  Calculate return PC:  */
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call) + 1;
+	cpu->cd.ppc.spr[SPR_LR] = cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1)
+	    << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.ppc.spr[SPR_LR] += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+
+	if (ctr_ok && cond_ok) {
+		uint64_t mask_within_page =
+		    ((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT)
+		    | ((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
+		cpu->pc = addr & ~((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
+		/*  TODO: trace in separate (duplicate) function?  */
+		if (cpu->machine->show_trace_tree)
+			cpu_functioncall_trace_return(cpu);
+		if (cpu->machine->show_trace_tree)
+			cpu_functioncall_trace(cpu, cpu->pc);
+		if ((old_pc  & ~mask_within_page) ==
+		    (cpu->pc & ~mask_within_page)) {
+			cpu->cd.ppc.next_ic =
+			    cpu->cd.ppc.cur_ic_page +
+			    ((cpu->pc & mask_within_page) >>
+			    PPC_INSTR_ALIGNMENT_SHIFT);
+		} else {
+			/*  Find the new physical page and update pointers:  */
+			quick_pc_to_pointers(cpu);
+		}
+	}
+}
+
+
+/*
+ *  bcctr:  Branch Conditional to Count register
+ *
+ *  arg[0] = bo
+ *  arg[1] = 31 - bi
+ *  arg[2] = bh
+ */
+X(bcctr)
+{
+	unsigned int bo = ic->arg[0], bi31m = ic->arg[1];
+	uint64_t old_pc = cpu->pc;
+	MODE_uint_t addr = cpu->cd.ppc.spr[SPR_CTR];
+	int cond_ok = (bo >> 4) & 1;
+	cond_ok |= ( ((bo >> 3) & 1) == ((cpu->cd.ppc.cr >> bi31m) & 1) );
+	if (cond_ok) {
+		uint64_t mask_within_page =
+		    ((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT)
+		    | ((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
+		cpu->pc = addr & ~((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
+		/*  TODO: trace in separate (duplicate) function?  */
+		if (cpu->machine->show_trace_tree)
+			cpu_functioncall_trace_return(cpu);
+		if ((old_pc  & ~mask_within_page) ==
+		    (cpu->pc & ~mask_within_page)) {
+			cpu->cd.ppc.next_ic =
+			    cpu->cd.ppc.cur_ic_page +
+			    ((cpu->pc & mask_within_page) >>
+			    PPC_INSTR_ALIGNMENT_SHIFT);
+		} else {
+			/*  Find the new physical page and update pointers:  */
+			quick_pc_to_pointers(cpu);
+		}
+	}
+}
+X(bcctr_l)
+{
+	uint64_t low_pc, old_pc = cpu->pc;
+	unsigned int bo = ic->arg[0], bi31m = ic->arg[1]  /*,bh = ic->arg[2] */;
+	MODE_uint_t addr = cpu->cd.ppc.spr[SPR_CTR];
+	int cond_ok = (bo >> 4) & 1;
+	cond_ok |= ( ((bo >> 3) & 1) == ((cpu->cd.ppc.cr >> bi31m) & 1) );
+
+	/*  Calculate return PC:  */
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call) + 1;
+	cpu->cd.ppc.spr[SPR_LR] = cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1)
+	    << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.ppc.spr[SPR_LR] += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+
+	if (cond_ok) {
+		uint64_t mask_within_page =
+		    ((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT)
+		    | ((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
+		cpu->pc = addr & ~((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
+		/*  TODO: trace in separate (duplicate) function?  */
+		if (cpu->machine->show_trace_tree)
+			cpu_functioncall_trace(cpu, cpu->pc);
+		if ((old_pc  & ~mask_within_page) ==
+		    (cpu->pc & ~mask_within_page)) {
+			cpu->cd.ppc.next_ic =
+			    cpu->cd.ppc.cur_ic_page +
+			    ((cpu->pc & mask_within_page) >>
+			    PPC_INSTR_ALIGNMENT_SHIFT);
+		} else {
+			/*  Find the new physical page and update pointers:  */
+			quick_pc_to_pointers(cpu);
+		}
+	}
+}
+
+
+/*
+ *  b:  Branch (to a different translated page)
+ *
+ *  arg[0] = relative offset (as an int32_t) from start of page
+ */
+X(b)
+{
+	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (int32_t)ic->arg[0];
+
+	/*  Find the new physical page and update the translation pointers:  */
+	quick_pc_to_pointers(cpu);
+}
+X(ba)
+{
+	cpu->pc = (int32_t)ic->arg[0];
+	quick_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  bc:  Branch Conditional (to a different translated page)
+ *
+ *  arg[0] = relative offset (as an int32_t) from start of page
+ *  arg[1] = bo
+ *  arg[2] = 31-bi
+ */
+X(bc)
+{
+	MODE_uint_t tmp;
+	unsigned int ctr_ok, cond_ok, bi31m = ic->arg[2], bo = ic->arg[1];
+	if (!(bo & 4))
+		cpu->cd.ppc.spr[SPR_CTR] --;
+	ctr_ok = (bo >> 2) & 1;
+	tmp = cpu->cd.ppc.spr[SPR_CTR];
+	ctr_ok |= ( (tmp == 0) == ((bo >> 1) & 1) );
+	cond_ok = (bo >> 4) & 1;
+	cond_ok |= ( ((bo >> 3) & 1) ==
+	    ((cpu->cd.ppc.cr >> (bi31m)) & 1)  );
+	if (ctr_ok && cond_ok)
+		instr(b)(cpu,ic);
+}
+X(bcl)
+{
+	MODE_uint_t tmp;
+	unsigned int ctr_ok, cond_ok, bi31m = ic->arg[2], bo = ic->arg[1];
+	int low_pc;
+
+	/*  Calculate LR:  */
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call) + 1;
+	cpu->cd.ppc.spr[SPR_LR] = cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1)
+	    << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.ppc.spr[SPR_LR] += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+
+	if (!(bo & 4))
+		cpu->cd.ppc.spr[SPR_CTR] --;
+	ctr_ok = (bo >> 2) & 1;
+	tmp = cpu->cd.ppc.spr[SPR_CTR];
+	ctr_ok |= ( (tmp == 0) == ((bo >> 1) & 1) );
+	cond_ok = (bo >> 4) & 1;
+	cond_ok |= ( ((bo >> 3) & 1) ==
+	    ((cpu->cd.ppc.cr >> bi31m) & 1)  );
+	if (ctr_ok && cond_ok)
+		instr(b)(cpu,ic);
+}
+
+
+/*
+ *  b_samepage:  Branch (to within the same translated page)
+ *
+ *  arg[0] = pointer to new ppc_instr_call
+ */
+X(b_samepage)
+{
+	cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
+}
+
+
+/*
+ *  bc_samepage:  Branch Conditional (to within the same page)
+ *
+ *  arg[0] = new ic ptr
+ *  arg[1] = bo
+ *  arg[2] = 31-bi
+ */
+X(bc_samepage)
+{
+	MODE_uint_t tmp;
+	unsigned int ctr_ok, cond_ok, bi31m = ic->arg[2], bo = ic->arg[1];
+	if (!(bo & 4))
+		cpu->cd.ppc.spr[SPR_CTR] --;
+	ctr_ok = (bo >> 2) & 1;
+	tmp = cpu->cd.ppc.spr[SPR_CTR];
+	ctr_ok |= ( (tmp == 0) == ((bo >> 1) & 1) );
+	cond_ok = (bo >> 4) & 1;
+	cond_ok |= ( ((bo >> 3) & 1) ==
+	    ((cpu->cd.ppc.cr >> bi31m) & 1)  );
+	if (ctr_ok && cond_ok)
+		cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
+}
+X(bc_samepage_simple0)
+{
+	int bi31m = ic->arg[2];
+	if (!((cpu->cd.ppc.cr >> bi31m) & 1))
+		cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
+}
+X(bc_samepage_simple1)
+{
+	int bi31m = ic->arg[2];
+	if ((cpu->cd.ppc.cr >> bi31m) & 1)
+		cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
+}
+X(bcl_samepage)
+{
+	MODE_uint_t tmp;
+	unsigned int ctr_ok, cond_ok, bi31m = ic->arg[2], bo = ic->arg[1];
+	int low_pc;
+
+	/*  Calculate LR:  */
+	low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call) + 1;
+	cpu->cd.ppc.spr[SPR_LR] = cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1)
+	    << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.ppc.spr[SPR_LR] += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+
+	if (!(bo & 4))
+		cpu->cd.ppc.spr[SPR_CTR] --;
+	ctr_ok = (bo >> 2) & 1;
+	tmp = cpu->cd.ppc.spr[SPR_CTR];
+	ctr_ok |= ( (tmp == 0) == ((bo >> 1) & 1) );
+	cond_ok = (bo >> 4) & 1;
+	cond_ok |= ( ((bo >> 3) & 1) ==
+	    ((cpu->cd.ppc.cr >> bi31m) & 1)  );
+	if (ctr_ok && cond_ok)
+		cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
+}
+
+
+/*
+ *  bl:  Branch and Link (to a different translated page)
+ *
+ *  arg[0] = relative offset (as an int32_t) from start of page
+ *  arg[1] = lr offset (relative to start of current page)
+ */
+X(bl)
+{
+	/*  Calculate LR and new PC:  */
+	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->cd.ppc.spr[SPR_LR] = cpu->pc + ic->arg[1];
+	cpu->pc += (int32_t)ic->arg[0];
+
+	/*  Find the new physical page and update the translation pointers:  */
+	quick_pc_to_pointers(cpu);
+}
+X(bla)
+{
+	/*  Calculate LR:  */
+	cpu->cd.ppc.spr[SPR_LR] = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) 
+	    << PPC_INSTR_ALIGNMENT_SHIFT)) + ic->arg[1];
+
+	cpu->pc = (int32_t)ic->arg[0];
+	quick_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  bl_trace:  Branch and Link (to a different translated page)  (with trace)
+ *
+ *  arg[0] = relative offset (as an int32_t) from start of page
+ *  arg[1] = lr offset (relative to start of current page)
+ */
+X(bl_trace)
+{
+	/*  Calculate LR:  */
+	cpu->cd.ppc.spr[SPR_LR] = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) 
+	    << PPC_INSTR_ALIGNMENT_SHIFT)) + ic->arg[1];
+
+	/*  Calculate new PC from start of page + arg[0]  */
+	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (int32_t)ic->arg[0];
+
+	cpu_functioncall_trace(cpu, cpu->pc);
+
+	/*  Find the new physical page and update the translation pointers:  */
+	quick_pc_to_pointers(cpu);
+}
+X(bla_trace)
+{
+	/*  Calculate LR:  */
+	cpu->cd.ppc.spr[SPR_LR] = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) 
+	    << PPC_INSTR_ALIGNMENT_SHIFT)) + ic->arg[1];
+
+	cpu->pc = (int32_t)ic->arg[0];
+	cpu_functioncall_trace(cpu, cpu->pc);
+	quick_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  bl_samepage:  Branch and Link (to within the same translated page)
+ *
+ *  arg[0] = pointer to new ppc_instr_call
+ *  arg[1] = lr offset (relative to start of current page)
+ */
+X(bl_samepage)
+{
+	/*  Calculate LR:  */
+	cpu->cd.ppc.spr[SPR_LR] = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) 
+	    << PPC_INSTR_ALIGNMENT_SHIFT)) + ic->arg[1];
+
+	cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
+}
+
+
+/*
+ *  bl_samepage_trace:  Branch and Link (to within the same translated page)
+ *
+ *  arg[0] = pointer to new ppc_instr_call
+ *  arg[1] = lr offset (relative to start of current page)
+ */
+X(bl_samepage_trace)
+{
+	uint32_t low_pc;
+
+	/*  Calculate LR:  */
+	cpu->cd.ppc.spr[SPR_LR] = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) 
+	    << PPC_INSTR_ALIGNMENT_SHIFT)) + ic->arg[1];
+
+	cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
+
+	/*  Calculate new PC (for the trace)  */
+	low_pc = ((size_t)cpu->cd.ppc.next_ic - (size_t)
+	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call);
+	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu_functioncall_trace(cpu, cpu->pc);
+}
+
+
+/*
+ *  cntlzw:  Count leading zeroes (32-bit word).
+ *
+ *  arg[0] = ptr to rs
+ *  arg[1] = ptr to ra
+ */
+X(cntlzw)
+{
+	uint32_t tmp = reg(ic->arg[0]);
+	int i;
+	for (i=0; i<32; i++) {
+		if (tmp & 0x80000000)
+			break;
+		tmp <<= 1;
+	}
+	reg(ic->arg[1]) = i;
+}
+
+
+/*
+ *  cmpd:  Compare Doubleword
+ *
+ *  arg[0] = ptr to ra
+ *  arg[1] = ptr to rb
+ *  arg[2] = 28 - 4*bf
+ */
+X(cmpd)
+{
+	int64_t tmp = reg(ic->arg[0]), tmp2 = reg(ic->arg[1]);
+	int bf_shift = ic->arg[2], c;
+	if (tmp < tmp2)
+		c = 8;
+	else if (tmp > tmp2)
+		c = 4;
+	else
+		c = 2;
+	/*  SO bit, copied from XER  */
+	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
+	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
+	cpu->cd.ppc.cr |= (c << bf_shift);
+}
+
+
+/*
+ *  cmpld:  Compare Doubleword, unsigned
+ *
+ *  arg[0] = ptr to ra
+ *  arg[1] = ptr to rb
+ *  arg[2] = 28 - 4*bf
+ */
+X(cmpld)
+{
+	uint64_t tmp = reg(ic->arg[0]), tmp2 = reg(ic->arg[1]);
+	int bf_shift = ic->arg[2], c;
+	if (tmp < tmp2)
+		c = 8;
+	else if (tmp > tmp2)
+		c = 4;
+	else
+		c = 2;
+	/*  SO bit, copied from XER  */
+	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
+	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
+	cpu->cd.ppc.cr |= (c << bf_shift);
+}
+
+
+/*
+ *  cmpdi:  Compare Doubleword immediate
+ *
+ *  arg[0] = ptr to ra
+ *  arg[1] = int32_t imm
+ *  arg[2] = 28 - 4*bf
+ */
+X(cmpdi)
+{
+	int64_t tmp = reg(ic->arg[0]), imm = (int32_t)ic->arg[1];
+	int bf_shift = ic->arg[2], c;
+	if (tmp < imm)
+		c = 8;
+	else if (tmp > imm)
+		c = 4;
+	else
+		c = 2;
+	/*  SO bit, copied from XER  */
+	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
+	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
+	cpu->cd.ppc.cr |= (c << bf_shift);
+}
+
+
+/*
+ *  cmpldi:  Compare Doubleword immediate, logical
+ *
+ *  arg[0] = ptr to ra
+ *  arg[1] = int32_t imm
+ *  arg[2] = 28 - 4*bf
+ */
+X(cmpldi)
+{
+	uint64_t tmp = reg(ic->arg[0]), imm = (uint32_t)ic->arg[1];
+	int bf_shift = ic->arg[2], c;
+	if (tmp < imm)
+		c = 8;
+	else if (tmp > imm)
+		c = 4;
+	else
+		c = 2;
+	/*  SO bit, copied from XER  */
+	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
+	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
+	cpu->cd.ppc.cr |= (c << bf_shift);
+}
+
+
+/*
+ *  cmpw:  Compare Word
+ *
+ *  arg[0] = ptr to ra
+ *  arg[1] = ptr to rb
+ *  arg[2] = 28 - 4*bf
+ */
+X(cmpw)
+{
+	int32_t tmp = reg(ic->arg[0]), tmp2 = reg(ic->arg[1]);
+	int bf_shift = ic->arg[2], c;
+	if (tmp < tmp2)
+		c = 8;
+	else if (tmp > tmp2)
+		c = 4;
+	else
+		c = 2;
+	/*  SO bit, copied from XER  */
+	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
+	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
+	cpu->cd.ppc.cr |= (c << bf_shift);
+}
+X(cmpw_cr0)
+{
+	/*  arg[2] is assumed to be 28  */
+	int32_t tmp = reg(ic->arg[0]), tmp2 = reg(ic->arg[1]);
+	cpu->cd.ppc.cr &= ~(0xf0000000);
+	if (tmp < tmp2)
+		cpu->cd.ppc.cr |= 0x80000000;
+	else if (tmp > tmp2)
+		cpu->cd.ppc.cr |= 0x40000000;
+	else
+		cpu->cd.ppc.cr |= 0x20000000;
+	cpu->cd.ppc.cr |= ((cpu->cd.ppc.spr[SPR_XER] >> 3) & 0x10000000);
+}
+
+
+/*
+ *  cmplw:  Compare Word, unsigned
+ *
+ *  arg[0] = ptr to ra
+ *  arg[1] = ptr to rb
+ *  arg[2] = 28 - 4*bf
+ */
+X(cmplw)
+{
+	uint32_t tmp = reg(ic->arg[0]), tmp2 = reg(ic->arg[1]);
+	int bf_shift = ic->arg[2], c;
+	if (tmp < tmp2)
+		c = 8;
+	else if (tmp > tmp2)
+		c = 4;
+	else
+		c = 2;
+	/*  SO bit, copied from XER  */
+	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
+	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
+	cpu->cd.ppc.cr |= (c << bf_shift);
+}
+
+
+/*
+ *  cmpwi:  Compare Word immediate
+ *
+ *  arg[0] = ptr to ra
+ *  arg[1] = int32_t imm
+ *  arg[2] = 28 - 4*bf
+ */
+X(cmpwi)
+{
+	int32_t tmp = reg(ic->arg[0]), imm = ic->arg[1];
+	int bf_shift = ic->arg[2], c;
+	if (tmp < imm)
+		c = 8;
+	else if (tmp > imm)
+		c = 4;
+	else
+		c = 2;
+	/*  SO bit, copied from XER  */
+	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
+	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
+	cpu->cd.ppc.cr |= (c << bf_shift);
+}
+X(cmpwi_cr0)
+{
+	/*  arg[2] is assumed to be 28  */
+	int32_t tmp = reg(ic->arg[0]), imm = ic->arg[1];
+	cpu->cd.ppc.cr &= ~(0xf0000000);
+	if (tmp < imm)
+		cpu->cd.ppc.cr |= 0x80000000;
+	else if (tmp > imm)
+		cpu->cd.ppc.cr |= 0x40000000;
+	else
+		cpu->cd.ppc.cr |= 0x20000000;
+	cpu->cd.ppc.cr |= ((cpu->cd.ppc.spr[SPR_XER] >> 3) & 0x10000000);
+}
+
+
+/*
+ *  cmplwi:  Compare Word immediate, logical
+ *
+ *  arg[0] = ptr to ra
+ *  arg[1] = int32_t imm
+ *  arg[2] = 28 - 4*bf
+ */
+X(cmplwi)
+{
+	uint32_t tmp = reg(ic->arg[0]), imm = ic->arg[1];
+	int bf_shift = ic->arg[2], c;
+	if (tmp < imm)
+		c = 8;
+	else if (tmp > imm)
+		c = 4;
+	else
+		c = 2;
+	/*  SO bit, copied from XER  */
+	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
+	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
+	cpu->cd.ppc.cr |= (c << bf_shift);
+}
+
+
+/*
+ *  dcbz:  Data-Cache Block Zero
+ *
+ *  arg[0] = ptr to ra (or zero)
+ *  arg[1] = ptr to rb
+ */
+X(dcbz)
+{
+	MODE_uint_t addr = reg(ic->arg[0]) + reg(ic->arg[1]);
+	unsigned char cacheline[128];
+	size_t cacheline_size = 1 << cpu->cd.ppc.cpu_type.dlinesize;
+	size_t cleared = 0;
+
+	/*  Synchronize the PC first:  */
+	cpu->pc = (cpu->pc & ~0xfff) + ic->arg[2];
+
+	addr &= ~(cacheline_size - 1);
+	memset(cacheline, 0, sizeof(cacheline));
+
+	while (cleared < cacheline_size) {
+		int to_clear = cacheline_size < sizeof(cacheline)?
+		    cacheline_size : sizeof(cacheline);
+#ifdef MODE32
+		unsigned char *page = cpu->cd.ppc.host_store[addr >> 12];
+		if (page != NULL) {
+			memset(page + (addr & 0xfff), 0, to_clear);
+		} else
+#endif
+		if (cpu->memory_rw(cpu, cpu->mem, addr, cacheline,
+		    to_clear, MEM_WRITE, CACHE_DATA) != MEMORY_ACCESS_OK) {
+			/*  exception  */
+			return;
+		}
+
+		cleared += to_clear;
+		addr += to_clear;
+	}
+}
+
+
+/*
+ *  mtfsf:  Copy FPR into the FPSCR.
+ *
+ *  arg[0] = ptr to frb
+ *  arg[1] = mask
+ */
+X(mtfsf)
+{
+	CHECK_FOR_FPU_EXCEPTION;
+	cpu->cd.ppc.fpscr &= ~ic->arg[1];
+	cpu->cd.ppc.fpscr |= (ic->arg[1] & (*(uint64_t *)ic->arg[0]));
+}
+
+
+/*
+ *  mffs:  Copy FPSCR into a FPR.
+ *
+ *  arg[0] = ptr to frt
+ */
+X(mffs)
+{
+	CHECK_FOR_FPU_EXCEPTION;
+	(*(uint64_t *)ic->arg[0]) = cpu->cd.ppc.fpscr;
+}
+
+
+/*
+ *  fmr:  Floating-point Move
+ *
+ *  arg[0] = ptr to frb
+ *  arg[1] = ptr to frt
+ */
+X(fmr)
+{
+	/*
+	 *  This works like a normal register to register copy, but
+	 *  a) it can cause an FPU exception, and b) the move is always
+	 *  64-bit, even when running in 32-bit mode.
+	 */
+	CHECK_FOR_FPU_EXCEPTION;
+	*(uint64_t *)ic->arg[1] = *(uint64_t *)ic->arg[0];
+}
+
+
+/*
+ *  fabs:  Floating-point Absulute Value
+ *
+ *  arg[0] = ptr to frb
+ *  arg[1] = ptr to frt
+ */
+X(fabs)
+{
+	uint64_t v;
+	CHECK_FOR_FPU_EXCEPTION;
+	v = *(uint64_t *)ic->arg[0];
+	*(uint64_t *)ic->arg[1] = v & 0x7fffffffffffffffULL;
+}
+
+
+/*
+ *  fneg:  Floating-point Negate
+ *
+ *  arg[0] = ptr to frb
+ *  arg[1] = ptr to frt
+ */
+X(fneg)
+{
+	uint64_t v;
+	CHECK_FOR_FPU_EXCEPTION;
+	v = *(uint64_t *)ic->arg[0];
+	*(uint64_t *)ic->arg[1] = v ^ 0x8000000000000000ULL;
+}
+
+
+/*
+ *  fcmpu:  Floating-point Compare Unordered
+ *
+ *  arg[0] = 28 - 4*bf  (bitfield shift)
+ *  arg[1] = ptr to fra
+ *  arg[2] = ptr to frb
+ */
+X(fcmpu)
+{
+	struct ieee_float_value fra, frb;
+	int bf_shift = ic->arg[0], c = 0;
+
+	CHECK_FOR_FPU_EXCEPTION;
+
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &fra, IEEE_FMT_D);
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[2], &frb, IEEE_FMT_D);
+	if (fra.nan | frb.nan) {
+		c = 1;
+	} else {
+		if (fra.f < frb.f)
+			c = 8;
+		else if (fra.f > frb.f)
+			c = 4;
+		else
+			c = 2;
+	}
+	/*  TODO: Signaling vs Quiet NaN  */
+	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
+	cpu->cd.ppc.cr |= ((c&0xe) << bf_shift);
+	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
+	cpu->cd.ppc.fpscr |= (c << PPC_FPSCR_FPCC_SHIFT);
+}
+
+
+/*
+ *  frsp:  Floating-point Round to Single Precision
+ *
+ *  arg[0] = ptr to frb
+ *  arg[1] = ptr to frt
+ */
+X(frsp)
+{
+	struct ieee_float_value frb;
+	float fl = 0.0;
+	int c = 0;
+
+	CHECK_FOR_FPU_EXCEPTION;
+
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[0], &frb, IEEE_FMT_D);
+	if (frb.nan) {
+		c = 1;
+	} else {
+		fl = frb.f;
+		if (fl < 0.0)
+			c = 8;
+		else if (fl > 0.0)
+			c = 4;
+		else
+			c = 2;
+	}
+	/*  TODO: Signaling vs Quiet NaN  */
+	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
+	cpu->cd.ppc.fpscr |= (c << PPC_FPSCR_FPCC_SHIFT);
+	(*(uint64_t *)ic->arg[1]) = ieee_store_float_value(fl, IEEE_FMT_D);
+}
+
+
+/*
+ *  fctiwz:  Floating-point Convert to Integer Word, Round to Zero
+ *
+ *  arg[0] = ptr to frb
+ *  arg[1] = ptr to frt
+ */
+X(fctiwz)
+{
+	struct ieee_float_value frb;
+	uint32_t res = 0;
+
+	CHECK_FOR_FPU_EXCEPTION;
+
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[0], &frb, IEEE_FMT_D);
+	if (!frb.nan) {
+		if (frb.f >= 2147483647.0)
+			res = 0x7fffffff;
+		else if (frb.f <= -2147483648.0)
+			res = 0x80000000;
+		else
+			res = (int32_t) frb.f;
+	}
+
+	*(uint64_t *)ic->arg[1] = (uint32_t)res;
+}
+
+
+/*
+ *  fmul:  Floating-point Multiply
+ *
+ *  arg[0] = ptr to frt
+ *  arg[1] = ptr to fra
+ *  arg[2] = ptr to frc
+ */
+X(fmul)
+{
+	struct ieee_float_value fra;
+	struct ieee_float_value frc;
+	double result = 0.0;
+	int c;
+
+	CHECK_FOR_FPU_EXCEPTION;
+
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &fra, IEEE_FMT_D);
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[2], &frc, IEEE_FMT_D);
+	result = fra.f * frc.f;
+	if (isnan(result))
+		c = 1;
+	else {
+		if (result < 0.0)
+			c = 8;
+		else if (result > 0.0)
+			c = 4;
+		else
+			c = 2;
+	}
+	/*  TODO: Signaling vs Quiet NaN  */
+	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
+	cpu->cd.ppc.fpscr |= (c << PPC_FPSCR_FPCC_SHIFT);
+
+	(*(uint64_t *)ic->arg[0]) =
+	    ieee_store_float_value(result, IEEE_FMT_D);
+}
+X(fmuls)
+{
+	/*  TODO  */
+	instr(fmul)(cpu, ic);
+}
+
+
+/*
+ *  fmadd:  Floating-point Multiply and Add
+ *
+ *  arg[0] = ptr to frt
+ *  arg[1] = ptr to fra
+ *  arg[2] = copy of the instruction word
+ */
+X(fmadd)
+{
+	uint32_t iw = ic->arg[2];
+	int b = (iw >> 11) & 31, c = (iw >> 6) & 31;
+	struct ieee_float_value fra;
+	struct ieee_float_value frb;
+	struct ieee_float_value frc;
+	double result = 0.0;
+	int cc;
+
+	CHECK_FOR_FPU_EXCEPTION;
+
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &fra, IEEE_FMT_D);
+	ieee_interpret_float_value(cpu->cd.ppc.fpr[b], &frb, IEEE_FMT_D);
+	ieee_interpret_float_value(cpu->cd.ppc.fpr[c], &frc, IEEE_FMT_D);
+	result = fra.f * frc.f + frb.f;
+	if (isnan(result))
+		cc = 1;
+	else {
+		if (result < 0.0)
+			cc = 8;
+		else if (result > 0.0)
+			cc = 4;
+		else
+			cc = 2;
+	}
+	/*  TODO: Signaling vs Quiet NaN  */
+	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
+	cpu->cd.ppc.fpscr |= (cc << PPC_FPSCR_FPCC_SHIFT);
+
+	(*(uint64_t *)ic->arg[0]) =
+	    ieee_store_float_value(result, IEEE_FMT_D);
+}
+
+
+/*
+ *  fmsub:  Floating-point Multiply and Sub
+ *
+ *  arg[0] = ptr to frt
+ *  arg[1] = ptr to fra
+ *  arg[2] = copy of the instruction word
+ */
+X(fmsub)
+{
+	uint32_t iw = ic->arg[2];
+	int b = (iw >> 11) & 31, c = (iw >> 6) & 31;
+	struct ieee_float_value fra;
+	struct ieee_float_value frb;
+	struct ieee_float_value frc;
+	double result = 0.0;
+	int cc;
+
+	CHECK_FOR_FPU_EXCEPTION;
+
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &fra, IEEE_FMT_D);
+	ieee_interpret_float_value(cpu->cd.ppc.fpr[b], &frb, IEEE_FMT_D);
+	ieee_interpret_float_value(cpu->cd.ppc.fpr[c], &frc, IEEE_FMT_D);
+	result = fra.f * frc.f - frb.f;
+	if (isnan(result))
+		cc = 1;
+	else {
+		if (result < 0.0)
+			cc = 8;
+		else if (result > 0.0)
+			cc = 4;
+		else
+			cc = 2;
+	}
+	/*  TODO: Signaling vs Quiet NaN  */
+	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
+	cpu->cd.ppc.fpscr |= (cc << PPC_FPSCR_FPCC_SHIFT);
+
+	(*(uint64_t *)ic->arg[0]) =
+	    ieee_store_float_value(result, IEEE_FMT_D);
+}
+
+
+/*
+ *  fadd, fsub, fdiv:  Various Floating-point operationgs
+ *
+ *  arg[0] = ptr to fra
+ *  arg[1] = ptr to frb
+ *  arg[2] = ptr to frt
+ */
+X(fadd)
+{
+	struct ieee_float_value fra;
+	struct ieee_float_value frb;
+	double result = 0.0;
+	int c;
+
+	CHECK_FOR_FPU_EXCEPTION;
+
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[0], &fra, IEEE_FMT_D);
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &frb, IEEE_FMT_D);
+	result = fra.f + frb.f;
+	if (isnan(result))
+		c = 1;
+	else {
+		if (result < 0.0)
+			c = 8;
+		else if (result > 0.0)
+			c = 4;
+		else
+			c = 2;
+	}
+	/*  TODO: Signaling vs Quiet NaN  */
+	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
+	cpu->cd.ppc.fpscr |= (c << PPC_FPSCR_FPCC_SHIFT);
+
+	(*(uint64_t *)ic->arg[2]) =
+	    ieee_store_float_value(result, IEEE_FMT_D);
+}
+X(fadds)
+{
+	/*  TODO  */
+	instr(fadd)(cpu, ic);
+}
+X(fsub)
+{
+	struct ieee_float_value fra;
+	struct ieee_float_value frb;
+	double result = 0.0;
+	int c;
+
+	CHECK_FOR_FPU_EXCEPTION;
+
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[0], &fra, IEEE_FMT_D);
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &frb, IEEE_FMT_D);
+	result = fra.f - frb.f;
+	if (isnan(result))
+		c = 1;
+	else {
+		if (result < 0.0)
+			c = 8;
+		else if (result > 0.0)
+			c = 4;
+		else
+			c = 2;
+	}
+	/*  TODO: Signaling vs Quiet NaN  */
+	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
+	cpu->cd.ppc.fpscr |= (c << PPC_FPSCR_FPCC_SHIFT);
+
+	(*(uint64_t *)ic->arg[2]) =
+	    ieee_store_float_value(result, IEEE_FMT_D);
+}
+X(fsubs)
+{
+	/*  TODO  */
+	instr(fsub)(cpu, ic);
+}
+X(fdiv)
+{
+	struct ieee_float_value fra;
+	struct ieee_float_value frb;
+	double result = 0.0;
+	int c;
+
+	CHECK_FOR_FPU_EXCEPTION;
+
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[0], &fra, IEEE_FMT_D);
+	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &frb, IEEE_FMT_D);
+	result = fra.f / frb.f;
+	if (isnan(result))
+		c = 1;
+	else {
+		if (result < 0.0)
+			c = 8;
+		else if (result > 0.0)
+			c = 4;
+		else
+			c = 2;
+	}
+	/*  TODO: Signaling vs Quiet NaN  */
+	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
+	cpu->cd.ppc.fpscr |= (c << PPC_FPSCR_FPCC_SHIFT);
+
+	(*(uint64_t *)ic->arg[2]) =
+	    ieee_store_float_value(result, IEEE_FMT_D);
+}
+X(fdivs)
+{
+	/*  TODO  */
+	instr(fdiv)(cpu, ic);
+}
+
+
+/*
+ *  llsc: Load-linked and store conditional
+ *
+ *  arg[0] = copy of the instruction word.
+ */
+X(llsc)
+{
+	int iw = ic->arg[0], len = 4, load = 0, xo = (iw >> 1) & 1023;
+	int i, rc = iw & 1, rt, ra, rb;
+	uint64_t addr = 0, value;
+	unsigned char d[8];
+
+	switch (xo) {
+	case PPC_31_LDARX:
+		len = 8;
+		// fall through
+	case PPC_31_LWARX:
+		load = 1;
+		break;
+	case PPC_31_STDCX_DOT:
+		len = 8;
+	case PPC_31_STWCX_DOT:
+		break;
+	}
+
+	rt = (iw >> 21) & 31;
+	ra = (iw >> 16) & 31;
+	rb = (iw >> 11) & 31;
+
+	if (ra != 0)
+		addr = cpu->cd.ppc.gpr[ra];
+	addr += cpu->cd.ppc.gpr[rb];
+
+	if (load) {
+		if (rc) {
+			fatal("ll: rc-bit set?\n");
+			exit(1);
+		}
+		if (cpu->memory_rw(cpu, cpu->mem, addr, d, len,
+		    MEM_READ, CACHE_DATA) != MEMORY_ACCESS_OK) {
+			fatal("ll: error: TODO\n");
+			exit(1);
+		}
+
+		value = 0;
+		for (i=0; i<len; i++) {
+			value <<= 8;
+			if (cpu->byte_order == EMUL_BIG_ENDIAN)
+				value |= d[i];
+			else
+				value |= d[len - 1 - i];
+		}
+
+		cpu->cd.ppc.gpr[rt] = value;
+		cpu->cd.ppc.ll_addr = addr;
+		cpu->cd.ppc.ll_bit = 1;
+	} else {
+		uint32_t old_so = cpu->cd.ppc.spr[SPR_XER] & PPC_XER_SO;
+		if (!rc) {
+			fatal("sc: rc-bit not set?\n");
+			exit(1);
+		}
+
+		value = cpu->cd.ppc.gpr[rt];
+
+		/*  "If the store is performed, bits 0-2 of Condition
+		    Register Field 0 are set to 0b001, otherwise, they are
+		    set to 0b000. The SO bit of the XER is copied to to bit
+		    4 of Condition Register Field 0.  */
+		if (!cpu->cd.ppc.ll_bit || cpu->cd.ppc.ll_addr != addr) {
+			cpu->cd.ppc.cr &= 0x0fffffff;
+			if (old_so)
+				cpu->cd.ppc.cr |= 0x10000000;
+			cpu->cd.ppc.ll_bit = 0;
+			return;
+		}
+
+		for (i=0; i<len; i++) {
+			if (cpu->byte_order == EMUL_BIG_ENDIAN)
+				d[len - 1 - i] = value >> (8*i);
+			else
+				d[i] = value >> (8*i);
+		}
+
+		if (cpu->memory_rw(cpu, cpu->mem, addr, d, len,
+		    MEM_WRITE, CACHE_DATA) != MEMORY_ACCESS_OK) {
+			fatal("sc: error: TODO\n");
+			exit(1);
+		}
+
+		cpu->cd.ppc.cr &= 0x0fffffff;
+		cpu->cd.ppc.cr |= 0x20000000;	/*  success!  */
+		if (old_so)
+			cpu->cd.ppc.cr |= 0x10000000;
+
+		/*  Clear _all_ CPUs' ll_bits:  */
+		for (i=0; i<cpu->machine->ncpus; i++)
+			cpu->machine->cpus[i]->cd.ppc.ll_bit = 0;
+	}
+}
+
+
+/*
+ *  mtsr, mtsrin:  Move To Segment Register [Indirect]
+ *
+ *  arg[0] = sr number, or for indirect mode: ptr to rb
+ *  arg[1] = ptr to rt
+ *
+ *  TODO: These only work for 32-bit mode!
+ */
+X(mtsr)
+{
+	int sr_num = ic->arg[0];
+	uint32_t old = cpu->cd.ppc.sr[sr_num];
+	cpu->cd.ppc.sr[sr_num] = reg(ic->arg[1]);
+
+	if (cpu->cd.ppc.sr[sr_num] != old)
+		cpu->invalidate_translation_caches(cpu, ic->arg[0] << 28,
+		    INVALIDATE_ALL | INVALIDATE_VADDR_UPPER4);
+}
+X(mtsrin)
+{
+	int sr_num = reg(ic->arg[0]) >> 28;
+	uint32_t old = cpu->cd.ppc.sr[sr_num];
+	cpu->cd.ppc.sr[sr_num] = reg(ic->arg[1]);
+
+	if (cpu->cd.ppc.sr[sr_num] != old)
+		cpu->invalidate_translation_caches(cpu, sr_num << 28,
+		    INVALIDATE_ALL | INVALIDATE_VADDR_UPPER4);
+}
+
+
+/*
+ *  mfsrin, mtsrin:  Move From/To Segment Register Indirect
+ *
+ *  arg[0] = sr number, or for indirect mode: ptr to rb
+ *  arg[1] = ptr to rt
+ */
+X(mfsr)
+{
+	/*  TODO: This only works for 32-bit mode  */
+	reg(ic->arg[1]) = cpu->cd.ppc.sr[ic->arg[0]];
+}
+X(mfsrin)
+{
+	/*  TODO: This only works for 32-bit mode  */
+	uint32_t sr_num = reg(ic->arg[0]) >> 28;
+	reg(ic->arg[1]) = cpu->cd.ppc.sr[sr_num];
+}
+
+
+/*
+ *  rldicl:
+ *
+ *  arg[0] = copy of the instruction word
+ */
+X(rldicl)
+{
+	int rs = (ic->arg[0] >> 21) & 31;
+	int ra = (ic->arg[0] >> 16) & 31;
+	int sh = ((ic->arg[0] >> 11) & 31) | ((ic->arg[0] & 2) << 4);
+	int mb = ((ic->arg[0] >> 6) & 31) | (ic->arg[0] & 0x20);
+	int rc = ic->arg[0] & 1;
+	uint64_t tmp = cpu->cd.ppc.gpr[rs], tmp2;
+	/*  TODO: Fix this, its performance is awful:  */
+	while (sh-- != 0) {
+		int b = (tmp >> 63) & 1;
+		tmp = (tmp << 1) | b;
+	}
+	tmp2 = 0;
+	while (mb <= 63) {
+		tmp |= ((uint64_t)1 << (63-mb));
+		mb ++;
+	}
+	cpu->cd.ppc.gpr[ra] = tmp & tmp2;
+	if (rc)
+		update_cr0(cpu, cpu->cd.ppc.gpr[ra]);
+}
+
+
+/*
+ *  rldicr:
+ *
+ *  arg[0] = copy of the instruction word
+ */
+X(rldicr)
+{
+	int rs = (ic->arg[0] >> 21) & 31;
+	int ra = (ic->arg[0] >> 16) & 31;
+	int sh = ((ic->arg[0] >> 11) & 31) | ((ic->arg[0] & 2) << 4);
+	int me = ((ic->arg[0] >> 6) & 31) | (ic->arg[0] & 0x20);
+	int rc = ic->arg[0] & 1;
+	uint64_t tmp = cpu->cd.ppc.gpr[rs];
+	/*  TODO: Fix this, its performance is awful:  */
+	while (sh-- != 0) {
+		int b = (tmp >> 63) & 1;
+		tmp = (tmp << 1) | b;
+	}
+	while (me++ < 63)
+		tmp &= ~((uint64_t)1 << (63-me));
+	cpu->cd.ppc.gpr[ra] = tmp;
+	if (rc)
+		update_cr0(cpu, tmp);
+}
+
+
+/*
+ *  rldimi:
+ *
+ *  arg[0] = copy of the instruction word
+ */
+X(rldimi)
+{
+	uint32_t iw = ic->arg[0];
+	int rs = (iw >> 21) & 31, ra = (iw >> 16) & 31;
+	int sh = ((iw >> 11) & 31) | ((iw & 2) << 4);
+	int mb = ((iw >> 6) & 31) | (iw & 0x20);
+	int rc = ic->arg[0] & 1;
+	int m;
+	uint64_t tmp, s = cpu->cd.ppc.gpr[rs];
+	/*  TODO: Fix this, its performance is awful:  */
+	while (sh-- != 0) {
+		int b = (s >> 63) & 1;
+		s = (s << 1) | b;
+	}
+	m = mb; tmp = 0;
+	do {
+		tmp |= ((uint64_t)1 << (63-m));
+		m ++;
+	} while (m != 63 - sh);
+	cpu->cd.ppc.gpr[ra] &= ~tmp;
+	cpu->cd.ppc.gpr[ra] |= (tmp & s);
+	if (rc)
+		update_cr0(cpu, cpu->cd.ppc.gpr[ra]);
+}
+
+
+/*
+ *  rlwnm:
+ *
+ *  arg[0] = ptr to ra
+ *  arg[1] = mask
+ *  arg[2] = copy of the instruction word
+ */
+X(rlwnm)
+{
+	uint32_t tmp, iword = ic->arg[2];
+	int rs = (iword >> 21) & 31;
+	int rb = (iword >> 11) & 31;
+	int sh = cpu->cd.ppc.gpr[rb] & 0x1f;
+	tmp = (uint32_t)cpu->cd.ppc.gpr[rs];
+	tmp = (tmp << sh) | (tmp >> (32-sh));
+	tmp &= (uint32_t)ic->arg[1];
+	reg(ic->arg[0]) = tmp;
+}
+DOT0(rlwnm)
+
+
+/*
+ *  rlwinm:
+ *
+ *  arg[0] = ptr to ra
+ *  arg[1] = mask
+ *  arg[2] = copy of the instruction word
+ */
+X(rlwinm)
+{
+	uint32_t tmp, iword = ic->arg[2];
+	int rs = (iword >> 21) & 31;
+	int sh = (iword >> 11) & 31;
+	tmp = (uint32_t)cpu->cd.ppc.gpr[rs];
+	tmp = (tmp << sh) | (tmp >> (32-sh));
+	tmp &= (uint32_t)ic->arg[1];
+	reg(ic->arg[0]) = tmp;
+}
+DOT0(rlwinm)
+
+
+/*
+ *  rlwimi:
+ *
+ *  arg[0] = ptr to rs
+ *  arg[1] = ptr to ra
+ *  arg[2] = copy of the instruction word
+ */
+X(rlwimi)
+{
+	MODE_uint_t tmp = reg(ic->arg[0]), ra = reg(ic->arg[1]);
+	uint32_t iword = ic->arg[2];
+	int sh = (iword >> 11) & 31;
+	int mb = (iword >> 6) & 31;
+	int me = (iword >> 1) & 31;   
+	int rc = iword & 1;
+
+	tmp = (tmp << sh) | (tmp >> (32-sh));
+
+	for (;;) {
+		uint64_t mask;
+		mask = (uint64_t)1 << (31-mb);
+		ra &= ~mask;
+		ra |= (tmp & mask);
+		if (mb == me)
+			break;
+		mb ++;
+		if (mb == 32)
+			mb = 0;
+	}
+	reg(ic->arg[1]) = ra;
+	if (rc)
+		update_cr0(cpu, ra);
+}
+
+
+/*
+ *  srawi:
+ *
+ *  arg[0] = ptr to rs
+ *  arg[1] = ptr to ra
+ *  arg[2] = sh (shift amount)
+ */
+X(srawi)
+{
+	uint32_t tmp = reg(ic->arg[0]);
+	int i = 0, j = 0, sh = ic->arg[2];
+
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	if (tmp & 0x80000000)
+		i = 1;
+	while (sh-- > 0) {
+		if (tmp & 1)
+			j ++;
+		tmp >>= 1;
+		if (tmp & 0x40000000)
+			tmp |= 0x80000000;
+	}
+	if (i && j>0)
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	reg(ic->arg[1]) = (int64_t)(int32_t)tmp;
+}
+DOT1(srawi)
+
+
+/*
+ *  mcrf:  Move inside condition register
+ *
+ *  arg[0] = 28-4*bf,  arg[1] = 28-4*bfa
+ */
+X(mcrf)
+{
+	int bf_shift = ic->arg[0], bfa_shift = ic->arg[1];
+	uint32_t tmp = (cpu->cd.ppc.cr >> bfa_shift) & 0xf;
+	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
+	cpu->cd.ppc.cr |= (tmp << bf_shift);
+}
+
+
+/*
+ *  crand, crxor etc:  Condition Register operations
+ *
+ *  arg[0] = copy of the instruction word
+ */
+X(crand) {
+	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
+	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
+	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
+	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
+	cpu->cd.ppc.cr &= ~(1 << (31-bt));
+	if (ba & bb)
+		cpu->cd.ppc.cr |= (1 << (31-bt));
+}
+X(crandc) {
+	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
+	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
+	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
+	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
+	cpu->cd.ppc.cr &= ~(1 << (31-bt));
+	if (!(ba & bb))
+		cpu->cd.ppc.cr |= (1 << (31-bt));
+}
+X(creqv) {
+	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
+	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
+	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
+	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
+	cpu->cd.ppc.cr &= ~(1 << (31-bt));
+	if (!(ba ^ bb))
+		cpu->cd.ppc.cr |= (1 << (31-bt));
+}
+X(cror) {
+	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
+	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
+	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
+	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
+	cpu->cd.ppc.cr &= ~(1 << (31-bt));
+	if (ba | bb)
+		cpu->cd.ppc.cr |= (1 << (31-bt));
+}
+X(crorc) {
+	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
+	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
+	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
+	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
+	cpu->cd.ppc.cr &= ~(1 << (31-bt));
+	if (!(ba | bb))
+		cpu->cd.ppc.cr |= (1 << (31-bt));
+}
+X(crnor) {
+	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
+	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
+	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
+	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
+	cpu->cd.ppc.cr &= ~(1 << (31-bt));
+	if (!(ba | bb))
+		cpu->cd.ppc.cr |= (1 << (31-bt));
+}
+X(crxor) {
+	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
+	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
+	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
+	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
+	cpu->cd.ppc.cr &= ~(1 << (31-bt));
+	if (ba ^ bb)
+		cpu->cd.ppc.cr |= (1 << (31-bt));
+}
+
+
+/*
+ *  mfspr: Move from SPR
+ *
+ *  arg[0] = pointer to destination register
+ *  arg[1] = pointer to source SPR
+ */
+X(mfspr) {
+	/*  TODO: Check permission  */
+	reg(ic->arg[0]) = reg(ic->arg[1]);
+}
+X(mfspr_pmc1) {
+	/*
+	 *  TODO: This is a temporary hack to make NetBSD/ppc detect
+	 *  a CPU of the correct (emulated) speed.
+	 */
+	reg(ic->arg[0]) = cpu->machine->emulated_hz / 10;
+}
+X(mftb) {
+	/*  NOTE/TODO: This increments the time base (slowly) if it
+	    is being polled.  */
+	if (++cpu->cd.ppc.spr[SPR_TBL] == 0)
+		cpu->cd.ppc.spr[SPR_TBU] ++;
+	reg(ic->arg[0]) = cpu->cd.ppc.spr[SPR_TBL];
+}
+X(mftbu) {
+	reg(ic->arg[0]) = cpu->cd.ppc.spr[SPR_TBU];
+}
+
+
+/*
+ *  mtspr: Move to SPR.
+ *
+ *  arg[0] = pointer to source register
+ *  arg[1] = pointer to the SPR
+ */
+X(mtspr) {
+	/*  TODO: Check permission  */
+	reg(ic->arg[1]) = reg(ic->arg[0]);
+}
+X(mtspr_sprg2) {
+	if (cpu->cd.ppc.bits == 32) {
+		// Ignore for now. FreeBSD/powerpc seems to write 0xffffffe0
+		// here, and read it back. If it is non-zero, it assumes a 64-bit
+		// cpu.
+	} else {
+		reg(ic->arg[1]) = reg(ic->arg[0]);
+	}
+}
+X(mtlr) {
+	cpu->cd.ppc.spr[SPR_LR] = reg(ic->arg[0]);
+}
+X(mtctr) {
+	cpu->cd.ppc.spr[SPR_CTR] = reg(ic->arg[0]);
+}
+
+
+/*
+ *  rfi[d]:  Return from Interrupt
+ */
+X(rfi)
+{
+	uint64_t tmp;
+
+	reg_access_msr(cpu, &tmp, 0, 0);
+	tmp &= ~0xffff;
+	tmp |= (cpu->cd.ppc.spr[SPR_SRR1] & 0xffff);
+	reg_access_msr(cpu, &tmp, 1, 0);
+
+	cpu->pc = cpu->cd.ppc.spr[SPR_SRR0];
+	quick_pc_to_pointers(cpu);
+}
+X(rfid)
+{
+	uint64_t tmp, mask = 0x800000000000ff73ULL;
+
+	reg_access_msr(cpu, &tmp, 0, 0);
+	tmp &= ~mask;
+	tmp |= (cpu->cd.ppc.spr[SPR_SRR1] & mask);
+	reg_access_msr(cpu, &tmp, 1, 0);
+
+	cpu->pc = cpu->cd.ppc.spr[SPR_SRR0];
+	if (!(tmp & PPC_MSR_SF))
+		cpu->pc = (uint32_t)cpu->pc;
+	quick_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  mfcr:  Move From Condition Register
+ *
+ *  arg[0] = pointer to destination register
+ */
+X(mfcr)
+{
+	reg(ic->arg[0]) = cpu->cd.ppc.cr;
+}
+
+
+/*
+ *  mfmsr:  Move From MSR
+ *
+ *  arg[0] = pointer to destination register
+ */
+X(mfmsr)
+{
+	reg_access_msr(cpu, (uint64_t*)ic->arg[0], 0, 0);
+}
+
+
+/*
+ *  mtmsr:  Move To MSR
+ *
+ *  arg[0] = pointer to source register
+ *  arg[1] = page offset of the next instruction
+ *  arg[2] = 0 for 32-bit (mtmsr), 1 for 64-bit (mtmsrd)
+ */
+X(mtmsr)
+{
+	MODE_uint_t old_pc;
+	uint64_t x = reg(ic->arg[0]);
+
+	/*  TODO: check permission!  */
+
+	/*  Synchronize the PC (pointing to _after_ this instruction)  */
+	cpu->pc = (cpu->pc & ~0xfff) + ic->arg[1];
+	old_pc = cpu->pc;
+
+	if (!ic->arg[2]) {
+		uint64_t y;
+		reg_access_msr(cpu, &y, 0, 0);
+		x = (y & 0xffffffff00000000ULL) | (x & 0xffffffffULL);
+	}
+
+	reg_access_msr(cpu, &x, 1, 1);
+
+	/*
+	 *  Super-ugly hack:  If the pc wasn't changed (i.e. if there was no
+	 *  exception while accessing the msr), then we _decrease_ the PC by 4
+	 *  again. This is because the next ic could be an end_of_page.
+	 */
+	if ((MODE_uint_t)cpu->pc == old_pc)
+		cpu->pc -= 4;
+}
+
+
+/*
+ *  wrteei:  Write EE immediate  (on PPC405GP)
+ *
+ *  arg[0] = either 0 or 0x8000
+ */
+X(wrteei)
+{
+	/*  TODO: check permission!  */
+	uint64_t x;
+
+	/*  Synchronize the PC (pointing to _after_ this instruction)  */
+	cpu->pc = (cpu->pc & ~0xfff) + ic->arg[1];
+
+	reg_access_msr(cpu, &x, 0, 0);
+	x = (x & ~0x8000) | ic->arg[0];
+	reg_access_msr(cpu, &x, 1, 1);
+}
+
+
+/*
+ *  mtcrf:  Move To Condition Register Fields
+ *
+ *  arg[0] = pointer to source register
+ */
+X(mtcrf)
+{
+	cpu->cd.ppc.cr &= ~ic->arg[1];
+	cpu->cd.ppc.cr |= (reg(ic->arg[0]) & ic->arg[1]);
+}
+
+
+/*
+ *  mulli:  Multiply Low Immediate.
+ *
+ *  arg[0] = pointer to source register ra
+ *  arg[1] = int32_t immediate
+ *  arg[2] = pointer to destination register rt
+ */
+X(mulli)
+{
+	reg(ic->arg[2]) = (uint32_t)(reg(ic->arg[0]) * (int32_t)ic->arg[1]);
+}
+
+
+/*
+ *  Load/Store Multiple:
+ *
+ *  arg[0] = rs  (or rt for loads)  NOTE: not a pointer
+ *  arg[1] = ptr to ra
+ *  arg[2] = int32_t immediate offset
+ */
+X(lmw) {
+	MODE_uint_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
+	unsigned char d[4];
+	int rs = ic->arg[0];
+
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page)
+	    / sizeof(struct ppc_instr_call);
+	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1)
+	    << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc |= (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+
+	while (rs <= 31) {
+		if (cpu->memory_rw(cpu, cpu->mem, addr, d, sizeof(d),
+		    MEM_READ, CACHE_DATA) != MEMORY_ACCESS_OK) {
+			/*  exception  */
+			return;
+		}
+
+		if (cpu->byte_order == EMUL_BIG_ENDIAN)
+			cpu->cd.ppc.gpr[rs] = (d[0] << 24) + (d[1] << 16)
+			    + (d[2] << 8) + d[3];
+		else
+			cpu->cd.ppc.gpr[rs] = (d[3] << 24) + (d[2] << 16)
+			    + (d[1] << 8) + d[0];
+
+		rs ++;
+		addr += sizeof(uint32_t);
+	}
+}
+X(stmw) {
+	MODE_uint_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
+	unsigned char d[4];
+	int rs = ic->arg[0];
+
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page)
+	    / sizeof(struct ppc_instr_call);
+	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1)
+	    << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+
+	while (rs <= 31) {
+		uint32_t tmp = cpu->cd.ppc.gpr[rs];
+		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+			d[3] = tmp; d[2] = tmp >> 8;
+			d[1] = tmp >> 16; d[0] = tmp >> 24;
+		} else {
+			d[0] = tmp; d[1] = tmp >> 8;
+			d[2] = tmp >> 16; d[3] = tmp >> 24;
+		}
+		if (cpu->memory_rw(cpu, cpu->mem, addr, d, sizeof(d),
+		    MEM_WRITE, CACHE_DATA) != MEMORY_ACCESS_OK) {
+			/*  exception  */
+			return;
+		}
+
+		rs ++;
+		addr += sizeof(uint32_t);
+	}
+}
+
+
+/*
+ *  Load/store string:
+ *
+ *  arg[0] = rs   (well, rt for lswi)
+ *  arg[1] = ptr to ra (or ptr to zero)
+ *  arg[2] = nb
+ */
+X(lswi)
+{
+	MODE_uint_t addr = reg(ic->arg[1]);
+	int rt = ic->arg[0], nb = ic->arg[2];
+	int sub = 0;
+
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page)
+	    / sizeof(struct ppc_instr_call);
+	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1)
+	    << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+
+	while (nb > 0) {
+		unsigned char d;
+		if (cpu->memory_rw(cpu, cpu->mem, addr, &d, 1,
+		    MEM_READ, CACHE_DATA) != MEMORY_ACCESS_OK) {
+			/*  exception  */
+			return;
+		}
+
+		if (cpu->cd.ppc.mode == MODE_POWER && sub == 0)
+			cpu->cd.ppc.gpr[rt] = 0;
+		cpu->cd.ppc.gpr[rt] &= ~(0xff << (24-8*sub));
+		cpu->cd.ppc.gpr[rt] |= (d << (24-8*sub));
+		sub ++;
+		if (sub == 4) {
+			rt = (rt + 1) & 31;
+			sub = 0;
+		}
+		addr ++;
+		nb --;
+	}
+}
+X(stswi)
+{
+	MODE_uint_t addr = reg(ic->arg[1]);
+	int rs = ic->arg[0], nb = ic->arg[2];
+	uint32_t cur = cpu->cd.ppc.gpr[rs];
+	int sub = 0;
+
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page)
+	    / sizeof(struct ppc_instr_call);
+	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1)
+	    << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+
+	while (nb > 0) {
+		unsigned char d = cur >> 24;
+		if (cpu->memory_rw(cpu, cpu->mem, addr, &d, 1,
+		    MEM_WRITE, CACHE_DATA) != MEMORY_ACCESS_OK) {
+			/*  exception  */
+			return;
+		}
+		cur <<= 8;
+		sub ++;
+		if (sub == 4) {
+			rs = (rs + 1) & 31;
+			sub = 0;
+			cur = cpu->cd.ppc.gpr[rs];
+		}
+		addr ++;
+		nb --;
+	}
+}
+
+
+/*
+ *  Shifts, and, or, xor, etc.
+ *
+ *  arg[0] = pointer to source register rs
+ *  arg[1] = pointer to source register rb
+ *  arg[2] = pointer to destination register ra
+ */
+X(extsb) {
+#ifdef MODE32
+	reg(ic->arg[2]) = (int32_t)(int8_t)reg(ic->arg[0]);
+#else
+	reg(ic->arg[2]) = (int64_t)(int8_t)reg(ic->arg[0]);
+#endif
+}
+DOT2(extsb)
+X(extsh) {
+#ifdef MODE32
+	reg(ic->arg[2]) = (int32_t)(int16_t)reg(ic->arg[0]);
+#else
+	reg(ic->arg[2]) = (int64_t)(int16_t)reg(ic->arg[0]);
+#endif
+}
+DOT2(extsh)
+X(extsw) {
+#ifdef MODE32
+	fatal("TODO: extsw: invalid instruction\n");
+#else
+	reg(ic->arg[2]) = (int64_t)(int32_t)reg(ic->arg[0]);
+#endif
+}
+DOT2(extsw)
+X(slw) {	reg(ic->arg[2]) = (uint64_t)reg(ic->arg[0])
+		    << (reg(ic->arg[1]) & 31); }
+DOT2(slw)
+X(sld) {int sa = reg(ic->arg[1]) & 127;
+	if (sa >= 64)	reg(ic->arg[2]) = 0;
+	else reg(ic->arg[2]) = (uint64_t)reg(ic->arg[0]) << (sa & 63); }
+DOT2(sld)
+X(sraw)
+{
+	uint32_t tmp = reg(ic->arg[0]);
+	int i = 0, j = 0, sh = reg(ic->arg[1]) & 31;
+
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	if (tmp & 0x80000000)
+		i = 1;
+	while (sh-- > 0) {
+		if (tmp & 1)
+			j ++;
+		tmp >>= 1;
+		if (tmp & 0x40000000)
+			tmp |= 0x80000000;
+	}
+	if (i && j>0)
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	reg(ic->arg[2]) = (int64_t)(int32_t)tmp;
+}
+DOT2(sraw)
+X(srw) {	reg(ic->arg[2]) = (uint64_t)reg(ic->arg[0])
+		    >> (reg(ic->arg[1]) & 31); }
+DOT2(srw)
+X(and) {	reg(ic->arg[2]) = reg(ic->arg[0]) & reg(ic->arg[1]); }
+DOT2(and)
+X(nand) {	reg(ic->arg[2]) = ~(reg(ic->arg[0]) & reg(ic->arg[1])); }
+DOT2(nand)
+X(andc) {	reg(ic->arg[2]) = reg(ic->arg[0]) & (~reg(ic->arg[1])); }
+DOT2(andc)
+X(nor) {	reg(ic->arg[2]) = ~(reg(ic->arg[0]) | reg(ic->arg[1])); }
+DOT2(nor)
+X(mr) {		reg(ic->arg[2]) = reg(ic->arg[1]); }
+X(or) {		reg(ic->arg[2]) = reg(ic->arg[0]) | reg(ic->arg[1]); }
+DOT2(or)
+X(orc) {	reg(ic->arg[2]) = reg(ic->arg[0]) | (~reg(ic->arg[1])); }
+DOT2(orc)
+X(xor) {	reg(ic->arg[2]) = reg(ic->arg[0]) ^ reg(ic->arg[1]); }
+DOT2(xor)
+X(eqv) {	reg(ic->arg[2]) = ~(reg(ic->arg[0]) ^ reg(ic->arg[1])); }
+DOT2(eqv)
+
+
+/*
+ *  neg:
+ *
+ *  arg[0] = pointer to source register ra
+ *  arg[1] = pointer to destination register rt
+ */
+X(neg) {	reg(ic->arg[1]) = -reg(ic->arg[0]); }
+DOT1(neg)
+
+
+/*
+ *  mullw, mulhw[u], divw[u]:
+ *
+ *  arg[0] = pointer to source register ra
+ *  arg[1] = pointer to source register rb
+ *  arg[2] = pointer to destination register rt
+ */
+X(mullw)
+{
+	int32_t sum = (int32_t)reg(ic->arg[0]) * (int32_t)reg(ic->arg[1]);
+	reg(ic->arg[2]) = (int32_t)sum;
+}
+DOT2(mullw)
+X(mulhw)
+{
+	int64_t sum;
+	sum = (int64_t)(int32_t)reg(ic->arg[0])
+	    * (int64_t)(int32_t)reg(ic->arg[1]);
+	reg(ic->arg[2]) = sum >> 32;
+}
+DOT2(mulhw)
+X(mulhwu)
+{
+	uint64_t sum;
+	sum = (uint64_t)(uint32_t)reg(ic->arg[0])
+	    * (uint64_t)(uint32_t)reg(ic->arg[1]);
+	reg(ic->arg[2]) = sum >> 32;
+}
+DOT2(mulhwu)
+X(divw)
+{
+	int32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	int32_t sum;
+	if (b == 0)
+		sum = 0;
+	else
+		sum = a / b;
+	reg(ic->arg[2]) = (uint32_t)sum;
+}
+DOT2(divw)
+X(divwu)
+{
+	uint32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
+	uint32_t sum;
+	if (b == 0)
+		sum = 0;
+	else
+		sum = a / b;
+	reg(ic->arg[2]) = sum;
+}
+DOT2(divwu)
+
+
+/*
+ *  add:  Add.
+ *
+ *  arg[0] = pointer to source register ra
+ *  arg[1] = pointer to source register rb
+ *  arg[2] = pointer to destination register rt
+ */
+X(add)     { reg(ic->arg[2]) = reg(ic->arg[0]) + reg(ic->arg[1]); }
+DOT2(add)
+
+
+/*
+ *  addc:  Add carrying.
+ *
+ *  arg[0] = pointer to source register ra
+ *  arg[1] = pointer to source register rb
+ *  arg[2] = pointer to destination register rt
+ */
+X(addc)
+{
+	/*  TODO: this only works in 32-bit mode  */
+	uint64_t tmp = (uint32_t)reg(ic->arg[0]);
+	uint64_t tmp2 = tmp;
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	tmp += (uint32_t)reg(ic->arg[1]);
+	if ((tmp >> 32) != (tmp2 >> 32))
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	reg(ic->arg[2]) = (uint32_t)tmp;
+}
+
+
+/*
+ *  adde:  Add extended, etc.
+ *
+ *  arg[0] = pointer to source register ra
+ *  arg[1] = pointer to source register rb
+ *  arg[2] = pointer to destination register rt
+ */
+X(adde)
+{
+	/*  TODO: this only works in 32-bit mode  */
+	int old_ca = cpu->cd.ppc.spr[SPR_XER] & PPC_XER_CA;
+	uint64_t tmp = (uint32_t)reg(ic->arg[0]);
+	uint64_t tmp2 = tmp;
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	tmp += (uint32_t)reg(ic->arg[1]);
+	if (old_ca)
+		tmp ++;
+	if ((tmp >> 32) != (tmp2 >> 32))
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	reg(ic->arg[2]) = (uint32_t)tmp;
+}
+DOT2(adde)
+X(addme)
+{
+	/*  TODO: this only works in 32-bit mode  */
+	int old_ca = cpu->cd.ppc.spr[SPR_XER] & PPC_XER_CA;
+	uint64_t tmp = (uint32_t)reg(ic->arg[0]);
+	uint64_t tmp2 = tmp;
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	if (old_ca)
+		tmp ++;
+	tmp += 0xffffffffULL;
+	if ((tmp >> 32) != (tmp2 >> 32))
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	reg(ic->arg[2]) = (uint32_t)tmp;
+}
+DOT2(addme)
+X(addze)
+{
+	/*  TODO: this only works in 32-bit mode  */
+	int old_ca = cpu->cd.ppc.spr[SPR_XER] & PPC_XER_CA;
+	uint64_t tmp = (uint32_t)reg(ic->arg[0]);
+	uint64_t tmp2 = tmp;
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	if (old_ca)
+		tmp ++;
+	if ((tmp >> 32) != (tmp2 >> 32))
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	reg(ic->arg[2]) = (uint32_t)tmp;
+}
+DOT2(addze)
+
+
+/*
+ *  subf:  Subf, etc.
+ *
+ *  arg[0] = pointer to source register ra
+ *  arg[1] = pointer to source register rb
+ *  arg[2] = pointer to destination register rt
+ */
+X(subf)
+{
+	reg(ic->arg[2]) = reg(ic->arg[1]) - reg(ic->arg[0]);
+}
+DOT2(subf)
+X(subfc)
+{
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	if (reg(ic->arg[1]) >= reg(ic->arg[0]))
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	reg(ic->arg[2]) = reg(ic->arg[1]) - reg(ic->arg[0]);
+}
+DOT2(subfc)
+X(subfe)
+{
+	int old_ca = (cpu->cd.ppc.spr[SPR_XER] & PPC_XER_CA)? 1 : 0;
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	if (reg(ic->arg[1]) == reg(ic->arg[0])) {
+		if (old_ca)
+			cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	} else if (reg(ic->arg[1]) >= reg(ic->arg[0]))
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+
+	/*
+	 *  TODO: The register value calculation should be correct,
+	 *  but the CA bit calculation above is probably not.
+	 */
+
+	reg(ic->arg[2]) = reg(ic->arg[1]) - reg(ic->arg[0]) - (old_ca? 0 : 1);
+}
+DOT2(subfe)
+X(subfme)
+{
+	int old_ca = cpu->cd.ppc.spr[SPR_XER] & PPC_XER_CA;
+	uint64_t tmp = (uint32_t)(~reg(ic->arg[0]));
+	tmp += 0xffffffffULL;
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	if (old_ca)
+		tmp ++;
+	if ((tmp >> 32) != 0)
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	reg(ic->arg[2]) = (uint32_t)tmp;
+}
+DOT2(subfme)
+X(subfze)
+{
+	int old_ca = cpu->cd.ppc.spr[SPR_XER] & PPC_XER_CA;
+	uint64_t tmp = (uint32_t)(~reg(ic->arg[0]));
+	uint64_t tmp2 = tmp;
+	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
+	if (old_ca)
+		tmp ++;
+	if ((tmp >> 32) != (tmp2 >> 32))
+		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
+	reg(ic->arg[2]) = (uint32_t)tmp;
+}
+DOT2(subfze)
+
+
+/*
+ *  ori, xori etc.:
+ *
+ *  arg[0] = pointer to source uint64_t
+ *  arg[1] = immediate value (uint32_t or larger)
+ *  arg[2] = pointer to destination uint64_t
+ */
+X(ori)  { reg(ic->arg[2]) = reg(ic->arg[0]) | (uint32_t)ic->arg[1]; }
+X(xori) { reg(ic->arg[2]) = reg(ic->arg[0]) ^ (uint32_t)ic->arg[1]; }
+
+
+#include "tmp_ppc_loadstore.c"
+
+
+/*
+ *  lfs, stfs: Load/Store Floating-point Single precision
+ */
+X(lfs)
+{
+	/*  Sync. PC in case of an exception, and remember it:  */
+	uint64_t old_pc, low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call);
+	old_pc = cpu->pc = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) <<
+	    PPC_INSTR_ALIGNMENT_SHIFT)) + (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+	if (!(cpu->cd.ppc.msr & PPC_MSR_FP)) {
+		ppc_exception(cpu, PPC_EXCEPTION_FPU);
+		return;
+	}
+
+	/*  Perform a 32-bit load:  */
+#ifdef MODE32
+	ppc32_loadstore
+#else
+	ppc_loadstore
+#endif
+	    [2 + 4 + 8](cpu, ic);
+
+	if (old_pc == cpu->pc) {
+		/*  The load succeeded. Let's convert the value:  */
+		struct ieee_float_value val;
+		(*(uint64_t *)ic->arg[0]) &= 0xffffffff;
+		ieee_interpret_float_value(*(uint64_t *)ic->arg[0],
+		    &val, IEEE_FMT_S);
+		(*(uint64_t *)ic->arg[0]) =
+		    ieee_store_float_value(val.f, IEEE_FMT_D);
+	}
+}
+X(lfsx)
+{
+	/*  Sync. PC in case of an exception, and remember it:  */
+	uint64_t old_pc, low_pc = ((size_t)ic - (size_t)
+	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call);
+	old_pc = cpu->pc = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) <<
+	    PPC_INSTR_ALIGNMENT_SHIFT)) + (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+	if (!(cpu->cd.ppc.msr & PPC_MSR_FP)) {
+		ppc_exception(cpu, PPC_EXCEPTION_FPU);
+		return;
+	}
+
+	/*  Perform a 32-bit load:  */
+#ifdef MODE32
+	ppc32_loadstore_indexed
+#else
+	ppc_loadstore_indexed
+#endif
+	    [2 + 4 + 8](cpu, ic);
+
+	if (old_pc == cpu->pc) {
+		/*  The load succeeded. Let's convert the value:  */
+		struct ieee_float_value val;
+		(*(uint64_t *)ic->arg[0]) &= 0xffffffff;
+		ieee_interpret_float_value(*(uint64_t *)ic->arg[0],
+		    &val, IEEE_FMT_S);
+		(*(uint64_t *)ic->arg[0]) =
+		    ieee_store_float_value(val.f, IEEE_FMT_D);
+	}
+}
+X(lfd)
+{
+	CHECK_FOR_FPU_EXCEPTION;
+
+	/*  Perform a 64-bit load:  */
+#ifdef MODE32
+	ppc32_loadstore
+#else
+	ppc_loadstore
+#endif
+	    [3 + 4 + 8](cpu, ic);
+}
+X(lfdx)
+{
+	CHECK_FOR_FPU_EXCEPTION;
+
+	/*  Perform a 64-bit load:  */
+#ifdef MODE32
+	ppc32_loadstore_indexed
+#else
+	ppc_loadstore_indexed
+#endif
+	    [3 + 4 + 8](cpu, ic);
+}
+X(stfs)
+{
+	uint64_t *old_arg0 = (uint64_t *) ic->arg[0];
+	struct ieee_float_value val;
+	uint64_t tmp_val;
+
+	CHECK_FOR_FPU_EXCEPTION;
+
+	ieee_interpret_float_value(*old_arg0, &val, IEEE_FMT_D);
+	tmp_val = ieee_store_float_value(val.f, IEEE_FMT_S);
+
+	ic->arg[0] = (size_t)&tmp_val;
+
+	/*  Perform a 32-bit store:  */
+#ifdef MODE32
+	ppc32_loadstore
+#else
+	ppc_loadstore
+#endif
+	    [2 + 4](cpu, ic);
+
+	ic->arg[0] = (size_t)old_arg0;
+}
+X(stfsx)
+{
+	uint64_t *old_arg0 = (uint64_t *)ic->arg[0];
+	struct ieee_float_value val;
+	uint64_t tmp_val;
+
+	CHECK_FOR_FPU_EXCEPTION;
+
+	ieee_interpret_float_value(*old_arg0, &val, IEEE_FMT_D);
+	tmp_val = ieee_store_float_value(val.f, IEEE_FMT_S);
+
+	ic->arg[0] = (size_t)&tmp_val;
+
+	/*  Perform a 32-bit store:  */
+#ifdef MODE32
+	ppc32_loadstore_indexed
+#else
+	ppc_loadstore_indexed
+#endif
+	    [2 + 4](cpu, ic);
+
+	ic->arg[0] = (size_t)old_arg0;
+}
+X(stfd)
+{
+	CHECK_FOR_FPU_EXCEPTION;
+
+	/*  Perform a 64-bit store:  */
+#ifdef MODE32
+	ppc32_loadstore
+#else
+	ppc_loadstore
+#endif
+	    [3 + 4](cpu, ic);
+}
+X(stfdx)
+{
+	CHECK_FOR_FPU_EXCEPTION;
+
+	/*  Perform a 64-bit store:  */
+#ifdef MODE32
+	ppc32_loadstore_indexed
+#else
+	ppc_loadstore_indexed
+#endif
+	    [3 + 4](cpu, ic);
+}
+
+
+/*
+ *  lvx, stvx:  Vector (16-byte) load/store  (slow implementation)
+ *
+ *  arg[0] = v-register nr of rs
+ *  arg[1] = pointer to ra
+ *  arg[2] = pointer to rb
+ */
+X(lvx)
+{
+	MODE_uint_t addr = reg(ic->arg[1]) + reg(ic->arg[2]);
+	uint8_t data[16];
+	uint64_t hi, lo;
+	int rs = ic->arg[0];
+
+	if (cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
+	    MEM_READ, CACHE_DATA) != MEMORY_ACCESS_OK) {
+		/*  exception  */
+		return;
+	}
+
+	hi = ((uint64_t)data[0] << 56) +
+	     ((uint64_t)data[1] << 48) +
+	     ((uint64_t)data[2] << 40) +
+	     ((uint64_t)data[3] << 32) +
+	     ((uint64_t)data[4] << 24) +
+	     ((uint64_t)data[5] << 16) +
+	     ((uint64_t)data[6] << 8) +
+	     ((uint64_t)data[7]);
+	lo = ((uint64_t)data[8] << 56) +
+	     ((uint64_t)data[9] << 48) +
+	     ((uint64_t)data[10] << 40) +
+	     ((uint64_t)data[11] << 32) +
+	     ((uint64_t)data[12] << 24) +
+	     ((uint64_t)data[13] << 16) +
+	     ((uint64_t)data[14] << 8) +
+	     ((uint64_t)data[15]);
+
+	cpu->cd.ppc.vr_hi[rs] = hi; cpu->cd.ppc.vr_lo[rs] = lo;
+}
+X(stvx)
+{
+	uint8_t data[16];
+	MODE_uint_t addr = reg(ic->arg[1]) + reg(ic->arg[2]);
+	int rs = ic->arg[0];
+	uint64_t hi = cpu->cd.ppc.vr_hi[rs], lo = cpu->cd.ppc.vr_lo[rs];
+
+	data[0] = hi >> 56;
+	data[1] = hi >> 48;
+	data[2] = hi >> 40;
+	data[3] = hi >> 32;
+	data[4] = hi >> 24;
+	data[5] = hi >> 16;
+	data[6] = hi >> 8;
+	data[7] = hi;
+	data[8] = lo >> 56;
+	data[9] = lo >> 48;
+	data[10] = lo >> 40;
+	data[11] = lo >> 32;
+	data[12] = lo >> 24;
+	data[13] = lo >> 16;
+	data[14] = lo >> 8;
+	data[15] = lo;
+
+	cpu->memory_rw(cpu, cpu->mem, addr, data,
+	    sizeof(data), MEM_WRITE, CACHE_DATA);
+}
+
+
+/*
+ *  vxor:  Vector (16-byte) XOR
+ *
+ *  arg[0] = v-register nr of source 1
+ *  arg[1] = v-register nr of source 2
+ *  arg[2] = v-register nr of destination
+ */
+X(vxor)
+{
+	cpu->cd.ppc.vr_hi[ic->arg[2]] =
+	    cpu->cd.ppc.vr_hi[ic->arg[0]] ^ cpu->cd.ppc.vr_hi[ic->arg[1]];
+	cpu->cd.ppc.vr_lo[ic->arg[2]] =
+	    cpu->cd.ppc.vr_lo[ic->arg[0]] ^ cpu->cd.ppc.vr_lo[ic->arg[1]];
+}
+
+
+/*
+ *  tlbia:  TLB invalidate all
+ */
+X(tlbia)
+{
+	fatal("[ tlbia ]\n");
+	cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
+}
+
+
+/*
+ *  tlbie:  TLB invalidate
+ */
+X(tlbie)
+{
+	/*  fatal("[ tlbie ]\n");  */
+	cpu->invalidate_translation_caches(cpu, reg(ic->arg[0]),
+	    INVALIDATE_VADDR);
+}
+
+
+/*
+ *  sc: Syscall.
+ */
+X(sc)
+{
+	/*  Synchronize the PC (pointing to _after_ this instruction)  */
+	cpu->pc = (cpu->pc & ~0xfff) + ic->arg[1];
+
+	ppc_exception(cpu, PPC_EXCEPTION_SC);
+
+	/*  This caused an update to the PC register, so there is no need
+	    to worry about the next instruction being an end_of_page.  */
+}
+
+
+/*
+ *  openfirmware:
+ */
+X(openfirmware)
+{
+	of_emul(cpu);
+
+	cpu->pc = cpu->cd.ppc.spr[SPR_LR];
+	if (cpu->machine->show_trace_tree)
+		cpu_functioncall_trace_return(cpu);
+
+	quick_pc_to_pointers(cpu);
+
+	if (!cpu->running) {
+		cpu->n_translated_instrs --;
+		cpu->cd.ppc.next_ic = &nothing_call;
+	}
+}
+
+
+/*
+ *  tlbsx_dot: TLB scan
+ */
+X(tlbsx_dot)
+{
+	/*  TODO  */
+	cpu->cd.ppc.cr &= ~(0xf0000000);
+	cpu->cd.ppc.cr |= 0x20000000;
+	cpu->cd.ppc.cr |= ((cpu->cd.ppc.spr[SPR_XER] >> 3) & 0x10000000);
+}
+
+
+/*
+ *  tlbli:
+ */
+X(tlbli)
+{
+	fatal("tlbli\n");
+	cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
+}
+
+
+/*
+ *  tlbld:
+ */
+X(tlbld)
+{
+	/*  MODE_uint_t vaddr = reg(ic->arg[0]);
+	    MODE_uint_t paddr = cpu->cd.ppc.spr[SPR_RPA];  */
+
+	fatal("tlbld\n");
+	cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
+}
+
+
+/*****************************************************************************/
+
+
+X(end_of_page)
+{
+	/*  Update the PC:  (offset 0, but on the next page)  */
+	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (PPC_IC_ENTRIES_PER_PAGE << PPC_INSTR_ALIGNMENT_SHIFT);
+
+	/*  Find the new physical page and update the translation pointers:  */
+	quick_pc_to_pointers(cpu);
+
+	/*  end_of_page doesn't count as an executed instruction:  */
+	cpu->n_translated_instrs --;
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  ppc_instr_to_be_translated():
+ *
+ *  Translate an instruction word into a ppc_instr_call. ic is filled in with
+ *  valid data for the translated instruction, or a "nothing" instruction if
+ *  there was a translation failure. The newly translated instruction is then
+ *  executed.
+ */
+X(to_be_translated)
+{
+	uint64_t addr, low_pc, tmp_addr;
+	uint32_t iword, mask;
+	unsigned char *page;
+	unsigned char ib[4];
+	int main_opcode, rt, rs, ra, rb, rc, aa_bit, l_bit, lk_bit, spr, sh,
+	    xo, imm, load, size, update, zero, bf, bo, bi, bh, oe_bit, n64=0,
+	    bfa, fp, byterev, nb, mb, me;
+	void (*samepage_function)(struct cpu *, struct ppc_instr_call *);
+	void (*rc_f)(struct cpu *, struct ppc_instr_call *);
+
+	/*  Figure out the (virtual) address of the instruction:  */
+	low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page)
+	    / sizeof(struct ppc_instr_call);
+	addr = cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1)
+	    << PPC_INSTR_ALIGNMENT_SHIFT);
+	addr += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc = addr;
+	addr &= ~((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
+
+	/*  Read the instruction word from memory:  */
+#ifdef MODE32
+	page = cpu->cd.ppc.host_load[((uint32_t)addr) >> 12];
+#else
+	{
+		const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+		const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+		const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+		uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
+		uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+		uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
+		    DYNTRANS_L3N)) & mask3;
+		struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.ppc.l1_64[x1];
+		struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
+		page = l3->host_load[x3];
+	}
+#endif
+
+	if (page != NULL) {
+		/*  fatal("TRANSLATION HIT!\n");  */
+		memcpy(ib, page + (addr & 0xfff), sizeof(ib));
+	} else {
+		/*  fatal("TRANSLATION MISS!\n");  */
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
+		    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
+			fatal("PPC to_be_translated(): "
+			    "read failed: TODO\n");
+			exit(1);
+			/*  goto bad;  */
+		}
+	}
+
+	{
+		uint32_t *p = (uint32_t *) ib;
+		iword = *p;
+		iword = BE32_TO_HOST(iword);
+	}
+
+#define DYNTRANS_TO_BE_TRANSLATED_HEAD
+#include "cpu_dyntrans.c"
+#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD
+
+
+	/*
+	 *  Translate the instruction:
+	 */
+
+	main_opcode = iword >> 26;
+
+	switch (main_opcode) {
+
+	case 0x04:
+		if (iword == 0x12739cc4) {
+			/*  vxor v19,v19,v19  */
+			ic->f = instr(vxor);
+			ic->arg[0] = 19;
+			ic->arg[1] = 19;
+			ic->arg[2] = 19;
+		} else {
+			if (!cpu->translation_readahead)
+				fatal("[ TODO: Unimplemented ALTIVEC, iword"
+				    " = 0x%08" PRIx32"x ]\n", iword);
+			goto bad;
+		}
+		break;
+
+	case PPC_HI6_MULLI:
+		rt = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		imm = (int16_t)(iword & 0xffff);
+		ic->f = instr(mulli);
+		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+		ic->arg[1] = (ssize_t)imm;
+		ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rt]);
+		break;
+
+	case PPC_HI6_SUBFIC:
+		rt = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		imm = (int16_t)(iword & 0xffff);
+		ic->f = instr(subfic);
+		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+		ic->arg[1] = (ssize_t)imm;
+		ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rt]);
+		break;
+
+	case PPC_HI6_CMPLI:
+	case PPC_HI6_CMPI:
+		bf = (iword >> 23) & 7;
+		l_bit = (iword >> 21) & 1;
+		ra = (iword >> 16) & 31;
+		if (main_opcode == PPC_HI6_CMPLI) {
+			imm = iword & 0xffff;
+			if (l_bit)
+				ic->f = instr(cmpldi);
+			else
+				ic->f = instr(cmplwi);
+		} else {
+			imm = (int16_t)(iword & 0xffff);
+			if (l_bit)
+				ic->f = instr(cmpdi);
+			else {
+				if (bf == 0)
+					ic->f = instr(cmpwi_cr0);
+				else
+					ic->f = instr(cmpwi);
+			}
+		}
+		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+		ic->arg[1] = (ssize_t)imm;
+		ic->arg[2] = 28 - 4 * bf;
+		break;
+
+	case PPC_HI6_ADDIC:
+	case PPC_HI6_ADDIC_DOT:
+		if (cpu->cd.ppc.bits == 64) {
+			if (!cpu->translation_readahead)
+				fatal("addic for 64-bit: TODO\n");
+			goto bad;
+		}
+		rt = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		imm = (int16_t)(iword & 0xffff);
+		if (main_opcode == PPC_HI6_ADDIC)
+			ic->f = instr(addic);
+		else
+			ic->f = instr(addic_dot);
+		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+		ic->arg[1] = imm;
+		ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rt]);
+		break;
+
+	case PPC_HI6_ADDI:
+	case PPC_HI6_ADDIS:
+		rt = (iword >> 21) & 31; ra = (iword >> 16) & 31;
+		ic->f = instr(addi);
+		if (ra == 0)
+			ic->f = instr(li);
+		else
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+		ic->arg[1] = (int16_t)(iword & 0xffff);
+		if (main_opcode == PPC_HI6_ADDIS)
+			ic->arg[1] <<= 16;
+		if (ra == 0 && ic->arg[1] == 0)
+			ic->f = instr(li_0);
+		ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rt]);
+		break;
+
+	case PPC_HI6_ANDI_DOT:
+	case PPC_HI6_ANDIS_DOT:
+		rs = (iword >> 21) & 31; ra = (iword >> 16) & 31;
+		ic->f = instr(andi_dot);
+		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
+		ic->arg[1] = iword & 0xffff;
+		if (main_opcode == PPC_HI6_ANDIS_DOT)
+			ic->arg[1] <<= 16;
+		ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+		break;
+
+	case PPC_HI6_ORI:
+	case PPC_HI6_ORIS:
+	case PPC_HI6_XORI:
+	case PPC_HI6_XORIS:
+		rs = (iword >> 21) & 31; ra = (iword >> 16) & 31;
+		if (main_opcode == PPC_HI6_ORI ||
+		    main_opcode == PPC_HI6_ORIS)
+			ic->f = instr(ori);
+		else
+			ic->f = instr(xori);
+		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
+		ic->arg[1] = iword & 0xffff;
+		if (main_opcode == PPC_HI6_ORIS ||
+		    main_opcode == PPC_HI6_XORIS)
+			ic->arg[1] <<= 16;
+		ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+		break;
+
+	case PPC_HI6_LBZ:
+	case PPC_HI6_LBZU:
+	case PPC_HI6_LHZ:
+	case PPC_HI6_LHZU:
+	case PPC_HI6_LHA:
+	case PPC_HI6_LHAU:
+	case PPC_HI6_LWZ:
+	case PPC_HI6_LWZU:
+	case PPC_HI6_LD:
+	case PPC_HI6_LFD:
+	case PPC_HI6_LFS:
+	case PPC_HI6_STB:
+	case PPC_HI6_STBU:
+	case PPC_HI6_STH:
+	case PPC_HI6_STHU:
+	case PPC_HI6_STW:
+	case PPC_HI6_STWU:
+	case PPC_HI6_STD:
+	case PPC_HI6_STFD:
+	case PPC_HI6_STFS:
+		rs = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		imm = (int16_t)iword;
+		load = 0; zero = 1; size = 0; update = 0; fp = 0;
+		ic->f = NULL;
+		switch (main_opcode) {
+		case PPC_HI6_LBZ:  load=1; break;
+		case PPC_HI6_LBZU: load=1; update=1; break;
+		case PPC_HI6_LHA:  load=1; size=1; zero=0; break;
+		case PPC_HI6_LHAU: load=1; size=1; zero=0; update=1; break;
+		case PPC_HI6_LHZ:  load=1; size=1; break;
+		case PPC_HI6_LHZU: load=1; size=1; update=1; break;
+		case PPC_HI6_LWZ:  load=1; size=2; break;
+		case PPC_HI6_LWZU: load=1; size=2; update=1; break;
+		case PPC_HI6_LD:   load=1; size=3; break;
+		case PPC_HI6_LFD:  load=1; size=3; fp=1;ic->f=instr(lfd);break;
+		case PPC_HI6_LFS:  load=1; size=2; fp=1;ic->f=instr(lfs);break;
+		case PPC_HI6_STB:  break;
+		case PPC_HI6_STBU: update=1; break;
+		case PPC_HI6_STH:  size=1; break;
+		case PPC_HI6_STHU: size=1; update=1; break;
+		case PPC_HI6_STW:  size=2; break;
+		case PPC_HI6_STWU: size=2; update=1; break;
+		case PPC_HI6_STD:  size=3; break;
+		case PPC_HI6_STFD: size=3; fp=1; ic->f = instr(stfd); break;
+		case PPC_HI6_STFS: size=2; fp=1; ic->f = instr(stfs); break;
+		}
+		if (ic->f == NULL) {
+			ic->f =
+#ifdef MODE32
+			    ppc32_loadstore
+#else
+			    ppc_loadstore
+#endif
+			    [size + 4*zero + 8*load + (imm==0? 16 : 0)
+			    + 32*update];
+		}
+		if (ra == 0 && update) {
+			if (!cpu->translation_readahead)
+				fatal("TODO: ra=0 && update?\n");
+			goto bad;
+		}
+		if (fp)
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rs]);
+		else
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
+		if (ra == 0)
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.zero);
+		else
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+		ic->arg[2] = (ssize_t)imm;
+		break;
+
+	case PPC_HI6_BC:
+		aa_bit = (iword >> 1) & 1;
+		lk_bit = iword & 1;
+		bo = (iword >> 21) & 31;
+		bi = (iword >> 16) & 31;
+		tmp_addr = (int64_t)(int16_t)(iword & 0xfffc);
+		if (aa_bit) {
+			if (!cpu->translation_readahead)
+				fatal("aa_bit: NOT YET\n");
+			goto bad;
+		}
+		if (lk_bit) {
+			ic->f = instr(bcl);
+			samepage_function = instr(bcl_samepage);
+		} else {
+			ic->f = instr(bc);
+			if ((bo & 0x14) == 0x04) {
+				samepage_function = bo & 8?
+				    instr(bc_samepage_simple1) :
+				    instr(bc_samepage_simple0);
+			} else
+				samepage_function = instr(bc_samepage);
+		}
+		ic->arg[0] = (ssize_t)(tmp_addr + (addr & 0xffc));
+		ic->arg[1] = bo;
+		ic->arg[2] = 31-bi;
+		/*  Branches are calculated as cur PC + offset.  */
+		/*  Special case: branch within the same page:  */
+		{
+			uint64_t mask_within_page =
+			    ((PPC_IC_ENTRIES_PER_PAGE-1) << 2) | 3;
+			uint64_t old_pc = addr;
+			uint64_t new_pc = old_pc + (int32_t)tmp_addr;
+			if ((old_pc & ~mask_within_page) ==
+			    (new_pc & ~mask_within_page)) {
+				ic->f = samepage_function;
+				ic->arg[0] = (size_t) (
+				    cpu->cd.ppc.cur_ic_page +
+				    ((new_pc & mask_within_page) >> 2));
+			}
+		}
+		break;
+
+	case PPC_HI6_SC:
+		ic->arg[0] = (iword >> 5) & 0x7f;
+		ic->arg[1] = (addr & 0xfff) + 4;
+		if (iword == 0x44ee0002) {
+			/*  Special case/magic hack for OpenFirmware emul:  */
+			ic->f = instr(openfirmware);
+		} else
+			ic->f = instr(sc);
+		break;
+
+	case PPC_HI6_B:
+		aa_bit = (iword & 2) >> 1;
+		lk_bit = iword & 1;
+		tmp_addr = (int64_t)(int32_t)((iword & 0x03fffffc) << 6);
+		tmp_addr = (int64_t)tmp_addr >> 6;
+		if (lk_bit) {
+			if (cpu->machine->show_trace_tree) {
+				ic->f = instr(bl_trace);
+				samepage_function = instr(bl_samepage_trace);
+			} else {
+				ic->f = instr(bl);
+				samepage_function = instr(bl_samepage);
+			}
+		} else {
+			ic->f = instr(b);
+			samepage_function = instr(b_samepage);
+		}
+		ic->arg[0] = (ssize_t)(tmp_addr + (addr & 0xffc));
+		ic->arg[1] = (addr & 0xffc) + 4;
+		/*  Branches are calculated as cur PC + offset.  */
+		/*  Special case: branch within the same page:  */
+		{
+			uint64_t mask_within_page =
+			    ((PPC_IC_ENTRIES_PER_PAGE-1) << 2) | 3;
+			uint64_t old_pc = addr;
+			uint64_t new_pc = old_pc + (int32_t)tmp_addr;
+			if ((old_pc & ~mask_within_page) ==
+			    (new_pc & ~mask_within_page)) {
+				ic->f = samepage_function;
+				ic->arg[0] = (size_t) (
+				    cpu->cd.ppc.cur_ic_page +
+				    ((new_pc & mask_within_page) >> 2));
+			}
+		}
+		if (aa_bit) {
+			if (lk_bit) {
+				if (cpu->machine->show_trace_tree) {
+					ic->f = instr(bla_trace);
+				} else {
+					ic->f = instr(bla);
+				}
+			} else {
+				ic->f = instr(ba);
+			}
+			ic->arg[0] = (ssize_t)tmp_addr;
+		}
+		break;
+
+	case PPC_HI6_19:
+		xo = (iword >> 1) & 1023;
+		switch (xo) {
+
+		case PPC_19_BCLR:
+		case PPC_19_BCCTR:
+			bo = (iword >> 21) & 31;
+			bi = (iword >> 16) & 31;
+			bh = (iword >> 11) & 3;
+			lk_bit = iword & 1;
+			if (xo == PPC_19_BCLR) {
+				if (lk_bit)
+					ic->f = instr(bclr_l);
+				else {
+					ic->f = instr(bclr);
+					if (!cpu->machine->show_trace_tree &&
+					    (bo & 0x14) == 0x14)
+						ic->f = instr(bclr_20);
+				}
+			} else {
+				if (!(bo & 4)) {
+					if (!cpu->translation_readahead)
+						fatal("TODO: bclr/bcctr "
+						    "bo bit 2 clear!\n");
+					goto bad;
+				}
+				if (lk_bit)
+					ic->f = instr(bcctr_l);
+				else
+					ic->f = instr(bcctr);
+			}
+			ic->arg[0] = bo;
+			ic->arg[1] = 31 - bi;
+			ic->arg[2] = bh;
+			break;
+
+		case PPC_19_ISYNC:
+			/*  TODO  */
+			ic->f = instr(nop);
+			break;
+
+		case PPC_19_RFI:
+			ic->f = instr(rfi);
+			break;
+
+		case PPC_19_RFID:
+			ic->f = instr(rfid);
+			break;
+
+		case PPC_19_MCRF:
+			bf = (iword >> 23) & 7;
+			bfa = (iword >> 18) & 7;
+			ic->arg[0] = 28 - 4*bf;
+			ic->arg[1] = 28 - 4*bfa;
+			ic->f = instr(mcrf);
+			break;
+
+		case PPC_19_CRAND:
+		case PPC_19_CRANDC:
+		case PPC_19_CREQV:
+		case PPC_19_CROR:
+		case PPC_19_CRORC:
+		case PPC_19_CRNOR:
+		case PPC_19_CRXOR:
+			switch (xo) {
+			case PPC_19_CRAND:  ic->f = instr(crand); break;
+			case PPC_19_CRANDC: ic->f = instr(crandc); break;
+			case PPC_19_CREQV:  ic->f = instr(creqv); break;
+			case PPC_19_CROR:   ic->f = instr(cror); break;
+			case PPC_19_CRORC:  ic->f = instr(crorc); break;
+			case PPC_19_CRNOR:  ic->f = instr(crnor); break;
+			case PPC_19_CRXOR:  ic->f = instr(crxor); break;
+			}
+			ic->arg[0] = iword;
+			break;
+
+		default:goto bad;
+		}
+		break;
+
+	case PPC_HI6_RLWNM:
+	case PPC_HI6_RLWINM:
+		ra = (iword >> 16) & 31;
+		mb = (iword >> 6) & 31;
+		me = (iword >> 1) & 31;   
+		rc = iword & 1;
+		mask = 0;
+		for (;;) {
+			mask |= ((uint32_t)0x80000000 >> mb);
+			if (mb == me)
+				break;
+			mb ++; mb &= 31;
+		}
+		switch (main_opcode) {
+		case PPC_HI6_RLWNM:
+			ic->f = rc? instr(rlwnm_dot) : instr(rlwnm); break;
+		case PPC_HI6_RLWINM:
+			ic->f = rc? instr(rlwinm_dot) : instr(rlwinm); break;
+		}
+		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+		ic->arg[1] = mask;
+		ic->arg[2] = (uint32_t)iword;
+		break;
+
+	case PPC_HI6_RLWIMI:
+		rs = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		ic->f = instr(rlwimi);
+		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
+		ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+		ic->arg[2] = (uint32_t)iword;
+		break;
+
+	case PPC_HI6_LMW:
+	case PPC_HI6_STMW:
+		/*  NOTE: Loads use rt, not rs.  */
+		rs = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		ic->arg[0] = rs;
+		if (ra == 0)
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.zero);
+		else
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+		ic->arg[2] = (int32_t)(int16_t)iword;
+		switch (main_opcode) {
+		case PPC_HI6_LMW:
+			ic->f = instr(lmw);
+			break;
+		case PPC_HI6_STMW:
+			ic->f = instr(stmw);
+			break;
+		}
+		break;
+
+	case PPC_HI6_30:
+		xo = (iword >> 2) & 7;
+		switch (xo) {
+
+		case PPC_30_RLDICL:
+		case PPC_30_RLDICR:
+		case PPC_30_RLDIMI:
+			switch (xo) {
+			case PPC_30_RLDICL: ic->f = instr(rldicl); break;
+			case PPC_30_RLDICR: ic->f = instr(rldicr); break;
+			case PPC_30_RLDIMI: ic->f = instr(rldimi); break;
+			}
+			ic->arg[0] = iword;
+			if (cpu->cd.ppc.bits == 32) {
+				if (!cpu->translation_readahead)
+					fatal("TODO: rld* in 32-bit mode?\n");
+				goto bad;
+			}
+			break;
+
+		default:goto bad;
+		}
+		break;
+
+	case PPC_HI6_31:
+		xo = (iword >> 1) & 1023;
+		switch (xo) {
+
+		case PPC_31_CMPL:
+		case PPC_31_CMP:
+			bf = (iword >> 23) & 7;
+			l_bit = (iword >> 21) & 1;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			if (xo == PPC_31_CMPL) {
+				if (l_bit)
+					ic->f = instr(cmpld);
+				else
+					ic->f = instr(cmplw);
+			} else {
+				if (l_bit)
+					ic->f = instr(cmpd);
+				else {
+					if (bf == 0)
+						ic->f = instr(cmpw_cr0);
+					else
+						ic->f = instr(cmpw);
+				}
+			}
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rb]);
+			ic->arg[2] = 28 - 4*bf;
+			break;
+
+		case PPC_31_CNTLZW:
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rc = iword & 1;
+			if (rc) {
+				if (!cpu->translation_readahead)
+					fatal("TODO: rc\n");
+				goto bad;
+			}
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+			ic->f = instr(cntlzw);
+			break;
+
+		case PPC_31_MFSPR:
+			rt = (iword >> 21) & 31;
+			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
+			debug_spr_usage(cpu->pc, spr);
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rt]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.spr[spr]);
+			switch (spr) {
+			// Reuse SPR_TB* for TBR_TB*:
+			case TBR_TBL: ic->f = instr(mftb); break;
+			case TBR_TBU: ic->f = instr(mftbu); break;
+			case SPR_PMC1:	ic->f = instr(mfspr_pmc1); break;
+			default:	ic->f = instr(mfspr);
+			}
+			break;
+
+		case PPC_31_MTSPR:
+			rs = (iword >> 21) & 31;
+			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
+			debug_spr_usage(cpu->pc, spr);
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.spr[spr]);
+			switch (spr) {
+			case SPR_LR:
+				ic->f = instr(mtlr);
+				break;
+			case SPR_CTR:
+				ic->f = instr(mtctr);
+				break;
+			case SPR_SPRG2:
+				ic->f = instr(mtspr_sprg2);
+				break;
+			default:ic->f = instr(mtspr);
+			}
+			break;
+
+		case PPC_31_MFCR:
+			rt = (iword >> 21) & 31;
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rt]);
+			ic->f = instr(mfcr);
+			break;
+
+		case PPC_31_MFMSR:
+			rt = (iword >> 21) & 31;
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rt]);
+			ic->f = instr(mfmsr);
+			break;
+
+		case PPC_31_MTMSR:
+		case PPC_31_MTMSRD:
+			rs = (iword >> 21) & 31;
+			l_bit = (iword >> 16) & 1;
+			if (l_bit) {
+				if (!cpu->translation_readahead)
+					fatal("TODO: mtmsr l-bit\n");
+				goto bad;
+			}
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
+			ic->arg[1] = (addr & 0xfff) + 4;
+			ic->arg[2] = xo == PPC_31_MTMSRD;
+			ic->f = instr(mtmsr);
+			break;
+
+		case PPC_31_MTCRF:
+			rs = (iword >> 21) & 31;
+			{
+				int i, fxm = (iword >> 12) & 255;
+				uint32_t tmp = 0;
+				for (i=0; i<8; i++, fxm <<= 1) {
+					tmp <<= 4;
+					if (fxm & 128)
+						tmp |= 0xf;
+				}
+				ic->arg[1] = (uint32_t)tmp;
+			}
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
+			ic->f = instr(mtcrf);
+			break;
+
+		case PPC_31_MFSRIN:
+		case PPC_31_MTSRIN:
+			rt = (iword >> 21) & 31;
+			rb = (iword >> 11) & 31;
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rb]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rt]);
+			switch (xo) {
+			case PPC_31_MFSRIN: ic->f = instr(mfsrin); break;
+			case PPC_31_MTSRIN: ic->f = instr(mtsrin); break;
+			}
+			if (cpu->cd.ppc.bits == 64) {
+				if (!cpu->translation_readahead)
+					fatal("Not yet for 64-bit mode\n");
+				goto bad;
+			}
+			break;
+
+		case PPC_31_MFSR:
+		case PPC_31_MTSR:
+			rt = (iword >> 21) & 31;
+			ic->arg[0] = (iword >> 16) & 15;
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rt]);
+			switch (xo) {
+			case PPC_31_MFSR:   ic->f = instr(mfsr); break;
+			case PPC_31_MTSR:   ic->f = instr(mtsr); break;
+			}
+			if (cpu->cd.ppc.bits == 64) {
+				if (!cpu->translation_readahead)
+					fatal("Not yet for 64-bit mode\n");
+				goto bad;
+			}
+			break;
+
+		case PPC_31_SRAWI:
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			sh = (iword >> 11) & 31;
+			rc = iword & 1;
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+			ic->arg[2] = sh;
+			if (rc)
+				ic->f = instr(srawi_dot);
+			else
+				ic->f = instr(srawi);
+			break;
+
+		case PPC_31_SYNC:
+		case PPC_31_DSSALL:
+		case PPC_31_EIEIO:
+		case PPC_31_DCBST:
+		case PPC_31_DCBTST:
+		case PPC_31_DCBF:
+		case PPC_31_DCBT:
+		case PPC_31_ICBI:
+			ic->f = instr(nop);
+			break;
+
+		case PPC_31_DCBZ:
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			if (ra == 0)
+				ic->arg[0] = (size_t)(&cpu->cd.ppc.zero);
+			else
+				ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rb]);
+			ic->arg[2] = addr & 0xfff;
+			ic->f = instr(dcbz);
+			break;
+
+		case PPC_31_TLBIA:
+			ic->f = instr(tlbia);
+			break;
+
+		case PPC_31_TLBSYNC:
+			/*  According to IBM, "Ensures that a tlbie and
+			    tlbia instruction executed by one processor has
+			    completed on all other processors.", which in
+			    GXemul means a nop :-)  */
+			ic->f = instr(nop);
+			break;
+
+		case PPC_31_TLBIE:
+			/*  TODO: POWER also uses ra?  */
+			rb = (iword >> 11) & 31;
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rb]);
+			ic->f = instr(tlbie);
+			break;
+
+		case PPC_31_TLBLD:	/*  takes an arg  */
+			rb = (iword >> 11) & 31;
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rb]);
+			ic->f = instr(tlbld);
+			break;
+
+		case PPC_31_TLBLI:	/*  takes an arg  */
+			rb = (iword >> 11) & 31;
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rb]);
+			ic->f = instr(tlbli);
+			break;
+
+		case PPC_31_TLBSX_DOT:
+			/*  TODO  */
+			ic->f = instr(tlbsx_dot);
+			break;
+
+		case PPC_31_MFTB:
+			rt = (iword >> 21) & 31;
+			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rt]);
+			switch (spr) {
+			case 268: ic->f = instr(mftb); break;
+			case 269: ic->f = instr(mftbu); break;
+			default:if (!cpu->translation_readahead)
+					fatal("mftb spr=%i?\n", spr);
+				goto bad;
+			}
+			break;
+
+		case PPC_31_NEG:
+			rt = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rc = iword & 1;
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rt]);
+			if (rc)
+				ic->f = instr(neg_dot);
+			else
+				ic->f = instr(neg);
+			break;
+
+		case PPC_31_LWARX:
+		case PPC_31_LDARX:
+		case PPC_31_STWCX_DOT:
+		case PPC_31_STDCX_DOT:
+			ic->arg[0] = iword;
+			ic->f = instr(llsc);
+			break;
+
+		case PPC_31_LSWI:
+		case PPC_31_STSWI:
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			nb = (iword >> 11) & 31;
+			ic->arg[0] = rs;
+			if (ra == 0)
+				ic->arg[1] = (size_t)(&cpu->cd.ppc.zero);
+			else
+				ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+			ic->arg[2] = nb == 0? 32 : nb;
+			switch (xo) {
+			case PPC_31_LSWI:  ic->f = instr(lswi); break;
+			case PPC_31_STSWI: ic->f = instr(stswi); break;
+			}
+			break;
+
+		case PPC_31_WRTEEI:
+			ic->arg[0] = iword & 0x8000;
+			ic->f = instr(wrteei);
+			break;
+
+		case 0x1c3:
+			fatal("[ mtdcr: TODO ]\n");
+			ic->f = instr(nop);
+			break;
+
+		case PPC_31_LBZX:
+		case PPC_31_LBZUX:
+		case PPC_31_LHAX:
+		case PPC_31_LHAUX:
+		case PPC_31_LHZX:
+		case PPC_31_LHZUX:
+		case PPC_31_LWZX:
+		case PPC_31_LWZUX:
+		case PPC_31_LHBRX:
+		case PPC_31_LWBRX:
+		case PPC_31_LFDX:
+		case PPC_31_LFSX:
+		case PPC_31_STBX:
+		case PPC_31_STBUX:
+		case PPC_31_STHX:
+		case PPC_31_STHUX:
+		case PPC_31_STWX:
+		case PPC_31_STWUX:
+		case PPC_31_STDX:
+		case PPC_31_STDUX:
+		case PPC_31_STHBRX:
+		case PPC_31_STWBRX:
+		case PPC_31_STFDX:
+		case PPC_31_STFSX:
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			if (ra == 0)
+				ic->arg[1] = (size_t)(&cpu->cd.ppc.zero);
+			else
+				ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+			ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rb]);
+			load = 0; zero = 1; size = 0; update = 0;
+			byterev = 0; fp = 0;
+			ic->f = NULL;
+			switch (xo) {
+			case PPC_31_LBZX:  load = 1; break;
+			case PPC_31_LBZUX: load=update=1; break;
+			case PPC_31_LHAX:  size=1; load=1; zero=0; break;
+			case PPC_31_LHAUX: size=1; load=update=1; zero=0; break;
+			case PPC_31_LHZX:  size=1; load=1; break;
+			case PPC_31_LHZUX: size=1; load=update = 1; break;
+			case PPC_31_LWZX:  size=2; load=1; break;
+			case PPC_31_LWZUX: size=2; load=update = 1; break;
+			case PPC_31_LHBRX: size=1; load=1; byterev=1;
+					   ic->f = instr(lhbrx); break;
+			case PPC_31_LWBRX: size=2; load=1; byterev=1;
+					   ic->f = instr(lwbrx); break;
+			case PPC_31_LFDX:  size=3; load=1; fp=1;
+					   ic->f = instr(lfdx); break;
+			case PPC_31_LFSX:  size=2; load=1; fp=1;
+					   ic->f = instr(lfsx); break;
+			case PPC_31_STBX:  break;
+			case PPC_31_STBUX: update = 1; break;
+			case PPC_31_STHX:  size=1; break;
+			case PPC_31_STHUX: size=1; update = 1; break;
+			case PPC_31_STWX:  size=2; break;
+			case PPC_31_STWUX: size=2; update = 1; break;
+			case PPC_31_STDX:  size=3; break;
+			case PPC_31_STDUX: size=3; update = 1; break;
+			case PPC_31_STHBRX:size=1; byterev = 1;
+					   ic->f = instr(sthbrx); break;
+			case PPC_31_STWBRX:size=2; byterev = 1;
+					   ic->f = instr(stwbrx); break;
+			case PPC_31_STFDX: size=3; fp=1;
+					   ic->f = instr(stfdx); break;
+			case PPC_31_STFSX: size=2; fp=1;
+					   ic->f = instr(stfsx); break;
+			}
+			if (fp)
+				ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rs]);
+			else
+				ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
+			if (!byterev && ic->f == NULL) {
+				ic->f =
+#ifdef MODE32
+				    ppc32_loadstore_indexed
+#else
+				    ppc_loadstore_indexed
+#endif
+				    [size + 4*zero + 8*load + 16*update];
+			}
+			if (ra == 0 && update) {
+				if (!cpu->translation_readahead)
+					fatal("TODO: ra=0 && update?\n");
+				goto bad;
+			}
+			break;
+
+		case PPC_31_EXTSB:
+		case PPC_31_EXTSH:
+		case PPC_31_EXTSW:
+		case PPC_31_SLW:
+		case PPC_31_SLD:
+		case PPC_31_SRAW:
+		case PPC_31_SRW:
+		case PPC_31_AND:
+		case PPC_31_NAND:
+		case PPC_31_ANDC:
+		case PPC_31_NOR:
+		case PPC_31_OR:
+		case PPC_31_ORC:
+		case PPC_31_XOR:
+		case PPC_31_EQV:
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			rc = iword & 1;
+			rc_f = NULL;
+			switch (xo) {
+			case PPC_31_EXTSB:ic->f = instr(extsb);
+					  rc_f  = instr(extsb_dot); break;
+			case PPC_31_EXTSH:ic->f = instr(extsh);
+					  rc_f  = instr(extsh_dot); break;
+			case PPC_31_EXTSW:ic->f = instr(extsw);
+					  rc_f  = instr(extsw_dot); break;
+			case PPC_31_SLW:  ic->f = instr(slw);
+					  rc_f  = instr(slw_dot); break;
+			case PPC_31_SLD:  ic->f = instr(sld);
+					  rc_f  = instr(sld_dot); break;
+			case PPC_31_SRAW: ic->f = instr(sraw);
+					  rc_f  = instr(sraw_dot); break;
+			case PPC_31_SRW:  ic->f = instr(srw);
+					  rc_f  = instr(srw_dot); break;
+			case PPC_31_AND:  ic->f = instr(and);
+					  rc_f  = instr(and_dot); break;
+			case PPC_31_NAND: ic->f = instr(nand);
+					  rc_f  = instr(nand_dot); break;
+			case PPC_31_ANDC: ic->f = instr(andc);
+					  rc_f  = instr(andc_dot); break;
+			case PPC_31_NOR:  ic->f = instr(nor);
+					  rc_f  = instr(nor_dot); break;
+			case PPC_31_OR:   ic->f = rs == rb? instr(mr)
+						: instr(or);
+					  rc_f  = instr(or_dot); break;
+			case PPC_31_ORC:  ic->f = instr(orc);
+					  rc_f  = instr(orc_dot); break;
+			case PPC_31_XOR:  ic->f = instr(xor);
+					  rc_f  = instr(xor_dot); break;
+			case PPC_31_EQV:  ic->f = instr(eqv);
+					  rc_f  = instr(eqv_dot); break;
+			}
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rb]);
+			ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+			if (rc)
+				ic->f = rc_f;
+			break;
+
+		case PPC_31_MULLW:
+		case PPC_31_MULHW:
+		case PPC_31_MULHWU:
+		case PPC_31_DIVW:
+		case PPC_31_DIVWU:
+		case PPC_31_ADD:
+		case PPC_31_ADDC:
+		case PPC_31_ADDE:
+		case PPC_31_ADDME:
+		case PPC_31_ADDZE:
+		case PPC_31_SUBF:
+		case PPC_31_SUBFC:
+		case PPC_31_SUBFE:
+		case PPC_31_SUBFME:
+		case PPC_31_SUBFZE:
+			rt = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			oe_bit = (iword >> 10) & 1;
+			rc = iword & 1;
+			if (oe_bit) {
+				if (!cpu->translation_readahead)
+					fatal("oe_bit not yet implemented\n");
+				goto bad;
+			}
+			switch (xo) {
+			case PPC_31_MULLW:  ic->f = instr(mullw); break;
+			case PPC_31_MULHW:  ic->f = instr(mulhw); break;
+			case PPC_31_MULHWU: ic->f = instr(mulhwu); break;
+			case PPC_31_DIVW:   ic->f = instr(divw); n64=1; break;
+			case PPC_31_DIVWU:  ic->f = instr(divwu); n64=1; break;
+			case PPC_31_ADD:    ic->f = instr(add); break;
+			case PPC_31_ADDC:   ic->f = instr(addc); n64=1; break;
+			case PPC_31_ADDE:   ic->f = instr(adde); n64=1; break;
+			case PPC_31_ADDME:  ic->f = instr(addme); n64=1; break;
+			case PPC_31_ADDZE:  ic->f = instr(addze); n64=1; break;
+			case PPC_31_SUBF:   ic->f = instr(subf); break;
+			case PPC_31_SUBFC:  ic->f = instr(subfc); break;
+			case PPC_31_SUBFE:  ic->f = instr(subfe); n64=1; break;
+			case PPC_31_SUBFME: ic->f = instr(subfme); n64=1; break;
+			case PPC_31_SUBFZE: ic->f = instr(subfze); n64=1;break;
+			}
+			if (rc) {
+				switch (xo) {
+				case PPC_31_ADD:
+					ic->f = instr(add_dot); break;
+				case PPC_31_ADDE:
+					ic->f = instr(adde_dot); break;
+				case PPC_31_ADDME:
+					ic->f = instr(addme_dot); break;
+				case PPC_31_ADDZE:
+					ic->f = instr(addze_dot); break;
+				case PPC_31_DIVW:
+					ic->f = instr(divw_dot); break;
+				case PPC_31_DIVWU:
+					ic->f = instr(divwu_dot); break;
+				case PPC_31_MULLW:
+					ic->f = instr(mullw_dot); break;
+				case PPC_31_MULHW:
+					ic->f = instr(mulhw_dot); break;
+				case PPC_31_MULHWU:
+					ic->f = instr(mulhwu_dot); break;
+				case PPC_31_SUBF:
+					ic->f = instr(subf_dot); break;
+				case PPC_31_SUBFC:
+					ic->f = instr(subfc_dot); break;
+				case PPC_31_SUBFE:
+					ic->f = instr(subfe_dot); break;
+				case PPC_31_SUBFME:
+					ic->f = instr(subfme_dot); break;
+				case PPC_31_SUBFZE:
+					ic->f = instr(subfze_dot); break;
+				default:if (!cpu->translation_readahead)
+						fatal("RC bit not yet "
+						    "implemented\n");
+					goto bad;
+				}
+			}
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rb]);
+			ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rt]);
+			if (cpu->cd.ppc.bits == 64 && n64) {
+				if (!cpu->translation_readahead)
+					fatal("Not yet for 64-bit mode\n");
+				goto bad;
+			}
+			break;
+
+		case PPC_31_LVX:
+		case PPC_31_LVXL:
+		case PPC_31_STVX:
+		case PPC_31_STVXL:
+			load = 0;
+			switch (xo) {
+			case PPC_31_LVX:
+			case PPC_31_LVXL:
+				load = 1; break;
+			}
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			ic->arg[0] = rs;
+			if (ra == 0)
+				ic->arg[1] = (size_t)(&cpu->cd.ppc.zero);
+			else
+				ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
+			ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rb]);
+			ic->f = load? instr(lvx) : instr(stvx);
+			break;
+
+		default:goto bad;
+		}
+		break;
+
+	case PPC_HI6_59:
+		xo = (iword >>  1) & 1023;
+		rt = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		rb = (iword >> 11) & 31;
+		rs = (iword >>  6) & 31;	/*  actually frc  */
+		rc = iword & 1;
+
+		if (rc) {
+			if (!cpu->translation_readahead)
+				fatal("Floating point (59) "
+				    "with rc bit! TODO\n");
+			goto bad;
+		}
+
+		/*  NOTE: Some floating-point instructions are selected
+		    using only the lowest 5 bits, not all 10!  */
+		switch (xo & 31) {
+		case PPC_59_FDIVS:
+		case PPC_59_FSUBS:
+		case PPC_59_FADDS:
+			switch (xo & 31) {
+			case PPC_59_FDIVS: ic->f = instr(fdivs); break;
+			case PPC_59_FSUBS: ic->f = instr(fsubs); break;
+			case PPC_59_FADDS: ic->f = instr(fadds); break;
+			}
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[ra]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[rb]);
+			ic->arg[2] = (size_t)(&cpu->cd.ppc.fpr[rt]);
+			break;
+		case PPC_59_FMULS:
+			ic->f = instr(fmuls);
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rt]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[ra]);
+			ic->arg[2] = (size_t)(&cpu->cd.ppc.fpr[rs]); /* frc */
+			break;
+		default:/*  Use all 10 bits of xo:  */
+			switch (xo) {
+			default:goto bad;
+			}
+		}
+		break;
+
+	case PPC_HI6_63:
+		xo = (iword >>  1) & 1023;
+		rt = (iword >> 21) & 31;
+		ra = (iword >> 16) & 31;
+		rb = (iword >> 11) & 31;
+		rs = (iword >>  6) & 31;	/*  actually frc  */
+		rc = iword & 1;
+
+		if (rc) {
+			if (!cpu->translation_readahead)
+				fatal("Floating point (63) "
+				    "with rc bit! TODO\n");
+			goto bad;
+		}
+
+		/*  NOTE: Some floating-point instructions are selected
+		    using only the lowest 5 bits, not all 10!  */
+		switch (xo & 31) {
+		case PPC_63_FDIV:
+		case PPC_63_FSUB:
+		case PPC_63_FADD:
+			switch (xo & 31) {
+			case PPC_63_FDIV: ic->f = instr(fdiv); break;
+			case PPC_63_FSUB: ic->f = instr(fsub); break;
+			case PPC_63_FADD: ic->f = instr(fadd); break;
+			}
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[ra]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[rb]);
+			ic->arg[2] = (size_t)(&cpu->cd.ppc.fpr[rt]);
+			break;
+		case PPC_63_FMUL:
+			ic->f = instr(fmul);
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rt]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[ra]);
+			ic->arg[2] = (size_t)(&cpu->cd.ppc.fpr[rs]); /* frc */
+			break;
+		case PPC_63_FMSUB:
+		case PPC_63_FMADD:
+			switch (xo & 31) {
+			case PPC_63_FMSUB: ic->f = instr(fmsub); break;
+			case PPC_63_FMADD: ic->f = instr(fmadd); break;
+			}
+			ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rt]);
+			ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[ra]);
+			ic->arg[2] = iword;
+			break;
+		default:/*  Use all 10 bits of xo:  */
+			switch (xo) {
+			case PPC_63_FCMPU:
+				ic->f = instr(fcmpu);
+				ic->arg[0] = 28 - 4*(rt >> 2);
+				ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[ra]);
+				ic->arg[2] = (size_t)(&cpu->cd.ppc.fpr[rb]);
+				break;
+			case PPC_63_FRSP:
+			case PPC_63_FCTIWZ:
+			case PPC_63_FNEG:
+			case PPC_63_FABS:
+			case PPC_63_FMR:
+				switch (xo) {
+				case PPC_63_FRSP:   ic->f = instr(frsp); break;
+				case PPC_63_FCTIWZ: ic->f = instr(fctiwz);break;
+				case PPC_63_FNEG:   ic->f = instr(fneg); break;
+				case PPC_63_FABS:   ic->f = instr(fabs); break;
+				case PPC_63_FMR:    ic->f = instr(fmr); break;
+				}
+				ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rb]);
+				ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[rt]);
+				break;
+			case PPC_63_MFFS:
+				ic->f = instr(mffs);
+				ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rt]);
+				break;
+			case PPC_63_MTFSF:
+				ic->f = instr(mtfsf);
+				ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rb]);
+				ic->arg[1] = 0;
+				for (bi=7; bi>=0; bi--) {
+					ic->arg[1] <<= 8;
+					if (iword & (1 << (17+bi)))
+						ic->arg[1] |= 0xf;
+				}
+				break;
+			default:goto bad;
+			}
+		}
+		break;
+
+	default:goto bad;
+	}
+
+
+#define	DYNTRANS_TO_BE_TRANSLATED_TAIL
+#include "cpu_dyntrans.c"
+#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_ppc_instr.cc gxemul-0.7.0+dfsg/src/cpus/cpu_ppc_instr.cc
--- gxemul-0.6.2/src/cpus/cpu_ppc_instr.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_ppc_instr.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,3902 +0,0 @@
-/*
- *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  POWER/PowerPC instructions.
- *
- *  Individual functions should keep track of cpu->n_translated_instrs.
- *  (If no instruction was executed, then it should be decreased. If, say, 4
- *  instructions were combined into one function and executed, then it should
- *  be increased by 3.)
- */
-
-
-#include "float_emul.h"
-
-
-#define DOT0(n) X(n ## _dot) { instr(n)(cpu,ic); \
-	update_cr0(cpu, reg(ic->arg[0])); }
-#define DOT1(n) X(n ## _dot) { instr(n)(cpu,ic); \
-	update_cr0(cpu, reg(ic->arg[1])); }
-#define DOT2(n) X(n ## _dot) { instr(n)(cpu,ic); \
-	update_cr0(cpu, reg(ic->arg[2])); }
-
-#ifndef CHECK_FOR_FPU_EXCEPTION
-#define CHECK_FOR_FPU_EXCEPTION { if (!(cpu->cd.ppc.msr & PPC_MSR_FP)) { \
-		/*  Synchronize the PC, and cause an FPU exception:  */  \
-		uint64_t low_pc = ((size_t)ic -				 \
-		    (size_t)cpu->cd.ppc.cur_ic_page)			 \
-		    / sizeof(struct ppc_instr_call);			 \
-		cpu->pc = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) <<	 \
-		    PPC_INSTR_ALIGNMENT_SHIFT)) + (low_pc <<		 \
-		    PPC_INSTR_ALIGNMENT_SHIFT);				 \
-		ppc_exception(cpu, PPC_EXCEPTION_FPU);			 \
-		return; } }
-#endif
-
-
-
-/*
- *  nop:  Do nothing.
- */
-X(nop)
-{
-}
-
-
-/*
- *  invalid:  To catch bugs.
- */
-X(invalid)
-{
-	fatal("PPC: invalid(): INTERNAL ERROR\n");
-	exit(1);
-}
-
-
-/*
- *  addi:  Add immediate.
- *
- *  arg[0] = pointer to source uint64_t
- *  arg[1] = immediate value (int32_t or larger)
- *  arg[2] = pointer to destination uint64_t
- */
-X(addi)
-{
-	reg(ic->arg[2]) = reg(ic->arg[0]) + (int32_t)ic->arg[1];
-}
-X(li)
-{
-	reg(ic->arg[2]) = (int32_t)ic->arg[1];
-}
-X(li_0)
-{
-	reg(ic->arg[2]) = 0;
-}
-
-
-/*
- *  andi_dot:  AND immediate, update CR.
- *
- *  arg[0] = pointer to source uint64_t
- *  arg[1] = immediate value (uint32_t)
- *  arg[2] = pointer to destination uint64_t
- */
-X(andi_dot)
-{
-	MODE_uint_t tmp = reg(ic->arg[0]) & (uint32_t)ic->arg[1];
-	reg(ic->arg[2]) = tmp;
-	update_cr0(cpu, tmp);
-}
-
-
-/*
- *  addic:  Add immediate, Carry.
- *
- *  arg[0] = pointer to source register
- *  arg[1] = immediate value (int32_t or larger)
- *  arg[2] = pointer to destination register
- */
-X(addic)
-{
-	/*  TODO/NOTE: Only for 32-bit mode, so far!  */
-	uint64_t tmp = (uint32_t)reg(ic->arg[0]);
-	uint64_t tmp2 = tmp;
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	tmp2 += (uint32_t)ic->arg[1];
-	if ((tmp2 >> 32) != (tmp >> 32))
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	reg(ic->arg[2]) = (uint32_t)tmp2;
-}
-
-
-/*
- *  subfic:  Subtract from immediate, Carry.
- *
- *  arg[0] = pointer to source uint64_t
- *  arg[1] = immediate value (int32_t or larger)
- *  arg[2] = pointer to destination uint64_t
- */
-X(subfic)
-{
-	MODE_uint_t tmp = (int64_t)(int32_t)ic->arg[1];
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	if (tmp >= reg(ic->arg[0]))
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	reg(ic->arg[2]) = tmp - reg(ic->arg[0]);
-}
-
-
-/*
- *  addic_dot:  Add immediate, Carry.
- *
- *  arg[0] = pointer to source uint64_t
- *  arg[1] = immediate value (int32_t or larger)
- *  arg[2] = pointer to destination uint64_t
- */
-X(addic_dot)
-{
-	/*  TODO/NOTE: Only for 32-bit mode, so far!  */
-	uint64_t tmp = (uint32_t)reg(ic->arg[0]);
-	uint64_t tmp2 = tmp;
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	tmp2 += (uint32_t)ic->arg[1];
-	if ((tmp2 >> 32) != (tmp >> 32))
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	reg(ic->arg[2]) = (uint32_t)tmp2;
-	update_cr0(cpu, (uint32_t)tmp2);
-}
-
-
-/*
- *  bclr:  Branch Conditional to Link Register
- *
- *  arg[0] = bo
- *  arg[1] = 31 - bi
- *  arg[2] = bh
- */
-X(bclr)
-{
-	unsigned int bo = ic->arg[0], bi31m = ic->arg[1];
-	int ctr_ok, cond_ok;
-	uint64_t old_pc = cpu->pc;
-	MODE_uint_t tmp, addr = cpu->cd.ppc.spr[SPR_LR];
-	if (!(bo & 4))
-		cpu->cd.ppc.spr[SPR_CTR] --;
-	ctr_ok = (bo >> 2) & 1;
-	tmp = cpu->cd.ppc.spr[SPR_CTR];
-	ctr_ok |= ( (tmp == 0) == ((bo >> 1) & 1) );
-	cond_ok = (bo >> 4) & 1;
-	cond_ok |= ( ((bo >> 3) & 1) == ((cpu->cd.ppc.cr >> bi31m) & 1) );
-	if (ctr_ok && cond_ok) {
-		uint64_t mask_within_page =
-		    ((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT)
-		    | ((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
-		cpu->pc = addr & ~((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
-		/*  TODO: trace in separate (duplicate) function?  */
-		if (cpu->machine->show_trace_tree)
-			cpu_functioncall_trace_return(cpu);
-		if ((old_pc  & ~mask_within_page) ==
-		    (cpu->pc & ~mask_within_page)) {
-			cpu->cd.ppc.next_ic =
-			    cpu->cd.ppc.cur_ic_page +
-			    ((cpu->pc & mask_within_page) >>
-			    PPC_INSTR_ALIGNMENT_SHIFT);
-		} else {
-			/*  Find the new physical page and update pointers:  */
-			quick_pc_to_pointers(cpu);
-		}
-	}
-}
-X(bclr_20)
-{
-	cpu->pc = cpu->cd.ppc.spr[SPR_LR];
-	quick_pc_to_pointers(cpu);
-}
-X(bclr_l)
-{
-	uint64_t low_pc, old_pc = cpu->pc;
-	unsigned int bo = ic->arg[0], bi31m = ic->arg[1]  /* ,bh = ic->arg[2]*/;
-	int ctr_ok, cond_ok;
-	MODE_uint_t tmp, addr = cpu->cd.ppc.spr[SPR_LR];
-	if (!(bo & 4))
-		cpu->cd.ppc.spr[SPR_CTR] --;
-	ctr_ok = (bo >> 2) & 1;
-	tmp = cpu->cd.ppc.spr[SPR_CTR];
-	ctr_ok |= ( (tmp == 0) == ((bo >> 1) & 1) );
-	cond_ok = (bo >> 4) & 1;
-	cond_ok |= ( ((bo >> 3) & 1) == ((cpu->cd.ppc.cr >> bi31m) & 1) );
-
-	/*  Calculate return PC:  */
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call) + 1;
-	cpu->cd.ppc.spr[SPR_LR] = cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1)
-	    << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.ppc.spr[SPR_LR] += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-
-	if (ctr_ok && cond_ok) {
-		uint64_t mask_within_page =
-		    ((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT)
-		    | ((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
-		cpu->pc = addr & ~((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
-		/*  TODO: trace in separate (duplicate) function?  */
-		if (cpu->machine->show_trace_tree)
-			cpu_functioncall_trace_return(cpu);
-		if (cpu->machine->show_trace_tree)
-			cpu_functioncall_trace(cpu, cpu->pc);
-		if ((old_pc  & ~mask_within_page) ==
-		    (cpu->pc & ~mask_within_page)) {
-			cpu->cd.ppc.next_ic =
-			    cpu->cd.ppc.cur_ic_page +
-			    ((cpu->pc & mask_within_page) >>
-			    PPC_INSTR_ALIGNMENT_SHIFT);
-		} else {
-			/*  Find the new physical page and update pointers:  */
-			quick_pc_to_pointers(cpu);
-		}
-	}
-}
-
-
-/*
- *  bcctr:  Branch Conditional to Count register
- *
- *  arg[0] = bo
- *  arg[1] = 31 - bi
- *  arg[2] = bh
- */
-X(bcctr)
-{
-	unsigned int bo = ic->arg[0], bi31m = ic->arg[1];
-	uint64_t old_pc = cpu->pc;
-	MODE_uint_t addr = cpu->cd.ppc.spr[SPR_CTR];
-	int cond_ok = (bo >> 4) & 1;
-	cond_ok |= ( ((bo >> 3) & 1) == ((cpu->cd.ppc.cr >> bi31m) & 1) );
-	if (cond_ok) {
-		uint64_t mask_within_page =
-		    ((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT)
-		    | ((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
-		cpu->pc = addr & ~((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
-		/*  TODO: trace in separate (duplicate) function?  */
-		if (cpu->machine->show_trace_tree)
-			cpu_functioncall_trace_return(cpu);
-		if ((old_pc  & ~mask_within_page) ==
-		    (cpu->pc & ~mask_within_page)) {
-			cpu->cd.ppc.next_ic =
-			    cpu->cd.ppc.cur_ic_page +
-			    ((cpu->pc & mask_within_page) >>
-			    PPC_INSTR_ALIGNMENT_SHIFT);
-		} else {
-			/*  Find the new physical page and update pointers:  */
-			quick_pc_to_pointers(cpu);
-		}
-	}
-}
-X(bcctr_l)
-{
-	uint64_t low_pc, old_pc = cpu->pc;
-	unsigned int bo = ic->arg[0], bi31m = ic->arg[1]  /*,bh = ic->arg[2] */;
-	MODE_uint_t addr = cpu->cd.ppc.spr[SPR_CTR];
-	int cond_ok = (bo >> 4) & 1;
-	cond_ok |= ( ((bo >> 3) & 1) == ((cpu->cd.ppc.cr >> bi31m) & 1) );
-
-	/*  Calculate return PC:  */
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call) + 1;
-	cpu->cd.ppc.spr[SPR_LR] = cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1)
-	    << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.ppc.spr[SPR_LR] += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-
-	if (cond_ok) {
-		uint64_t mask_within_page =
-		    ((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT)
-		    | ((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
-		cpu->pc = addr & ~((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
-		/*  TODO: trace in separate (duplicate) function?  */
-		if (cpu->machine->show_trace_tree)
-			cpu_functioncall_trace(cpu, cpu->pc);
-		if ((old_pc  & ~mask_within_page) ==
-		    (cpu->pc & ~mask_within_page)) {
-			cpu->cd.ppc.next_ic =
-			    cpu->cd.ppc.cur_ic_page +
-			    ((cpu->pc & mask_within_page) >>
-			    PPC_INSTR_ALIGNMENT_SHIFT);
-		} else {
-			/*  Find the new physical page and update pointers:  */
-			quick_pc_to_pointers(cpu);
-		}
-	}
-}
-
-
-/*
- *  b:  Branch (to a different translated page)
- *
- *  arg[0] = relative offset (as an int32_t) from start of page
- */
-X(b)
-{
-	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (int32_t)ic->arg[0];
-
-	/*  Find the new physical page and update the translation pointers:  */
-	quick_pc_to_pointers(cpu);
-}
-X(ba)
-{
-	cpu->pc = (int32_t)ic->arg[0];
-	quick_pc_to_pointers(cpu);
-}
-
-
-/*
- *  bc:  Branch Conditional (to a different translated page)
- *
- *  arg[0] = relative offset (as an int32_t) from start of page
- *  arg[1] = bo
- *  arg[2] = 31-bi
- */
-X(bc)
-{
-	MODE_uint_t tmp;
-	unsigned int ctr_ok, cond_ok, bi31m = ic->arg[2], bo = ic->arg[1];
-	if (!(bo & 4))
-		cpu->cd.ppc.spr[SPR_CTR] --;
-	ctr_ok = (bo >> 2) & 1;
-	tmp = cpu->cd.ppc.spr[SPR_CTR];
-	ctr_ok |= ( (tmp == 0) == ((bo >> 1) & 1) );
-	cond_ok = (bo >> 4) & 1;
-	cond_ok |= ( ((bo >> 3) & 1) ==
-	    ((cpu->cd.ppc.cr >> (bi31m)) & 1)  );
-	if (ctr_ok && cond_ok)
-		instr(b)(cpu,ic);
-}
-X(bcl)
-{
-	MODE_uint_t tmp;
-	unsigned int ctr_ok, cond_ok, bi31m = ic->arg[2], bo = ic->arg[1];
-	int low_pc;
-
-	/*  Calculate LR:  */
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call) + 1;
-	cpu->cd.ppc.spr[SPR_LR] = cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1)
-	    << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.ppc.spr[SPR_LR] += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-
-	if (!(bo & 4))
-		cpu->cd.ppc.spr[SPR_CTR] --;
-	ctr_ok = (bo >> 2) & 1;
-	tmp = cpu->cd.ppc.spr[SPR_CTR];
-	ctr_ok |= ( (tmp == 0) == ((bo >> 1) & 1) );
-	cond_ok = (bo >> 4) & 1;
-	cond_ok |= ( ((bo >> 3) & 1) ==
-	    ((cpu->cd.ppc.cr >> bi31m) & 1)  );
-	if (ctr_ok && cond_ok)
-		instr(b)(cpu,ic);
-}
-
-
-/*
- *  b_samepage:  Branch (to within the same translated page)
- *
- *  arg[0] = pointer to new ppc_instr_call
- */
-X(b_samepage)
-{
-	cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
-}
-
-
-/*
- *  bc_samepage:  Branch Conditional (to within the same page)
- *
- *  arg[0] = new ic ptr
- *  arg[1] = bo
- *  arg[2] = 31-bi
- */
-X(bc_samepage)
-{
-	MODE_uint_t tmp;
-	unsigned int ctr_ok, cond_ok, bi31m = ic->arg[2], bo = ic->arg[1];
-	if (!(bo & 4))
-		cpu->cd.ppc.spr[SPR_CTR] --;
-	ctr_ok = (bo >> 2) & 1;
-	tmp = cpu->cd.ppc.spr[SPR_CTR];
-	ctr_ok |= ( (tmp == 0) == ((bo >> 1) & 1) );
-	cond_ok = (bo >> 4) & 1;
-	cond_ok |= ( ((bo >> 3) & 1) ==
-	    ((cpu->cd.ppc.cr >> bi31m) & 1)  );
-	if (ctr_ok && cond_ok)
-		cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
-}
-X(bc_samepage_simple0)
-{
-	int bi31m = ic->arg[2];
-	if (!((cpu->cd.ppc.cr >> bi31m) & 1))
-		cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
-}
-X(bc_samepage_simple1)
-{
-	int bi31m = ic->arg[2];
-	if ((cpu->cd.ppc.cr >> bi31m) & 1)
-		cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
-}
-X(bcl_samepage)
-{
-	MODE_uint_t tmp;
-	unsigned int ctr_ok, cond_ok, bi31m = ic->arg[2], bo = ic->arg[1];
-	int low_pc;
-
-	/*  Calculate LR:  */
-	low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call) + 1;
-	cpu->cd.ppc.spr[SPR_LR] = cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1)
-	    << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.ppc.spr[SPR_LR] += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-
-	if (!(bo & 4))
-		cpu->cd.ppc.spr[SPR_CTR] --;
-	ctr_ok = (bo >> 2) & 1;
-	tmp = cpu->cd.ppc.spr[SPR_CTR];
-	ctr_ok |= ( (tmp == 0) == ((bo >> 1) & 1) );
-	cond_ok = (bo >> 4) & 1;
-	cond_ok |= ( ((bo >> 3) & 1) ==
-	    ((cpu->cd.ppc.cr >> bi31m) & 1)  );
-	if (ctr_ok && cond_ok)
-		cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
-}
-
-
-/*
- *  bl:  Branch and Link (to a different translated page)
- *
- *  arg[0] = relative offset (as an int32_t) from start of page
- *  arg[1] = lr offset (relative to start of current page)
- */
-X(bl)
-{
-	/*  Calculate LR and new PC:  */
-	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->cd.ppc.spr[SPR_LR] = cpu->pc + ic->arg[1];
-	cpu->pc += (int32_t)ic->arg[0];
-
-	/*  Find the new physical page and update the translation pointers:  */
-	quick_pc_to_pointers(cpu);
-}
-X(bla)
-{
-	/*  Calculate LR:  */
-	cpu->cd.ppc.spr[SPR_LR] = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) 
-	    << PPC_INSTR_ALIGNMENT_SHIFT)) + ic->arg[1];
-
-	cpu->pc = (int32_t)ic->arg[0];
-	quick_pc_to_pointers(cpu);
-}
-
-
-/*
- *  bl_trace:  Branch and Link (to a different translated page)  (with trace)
- *
- *  arg[0] = relative offset (as an int32_t) from start of page
- *  arg[1] = lr offset (relative to start of current page)
- */
-X(bl_trace)
-{
-	/*  Calculate LR:  */
-	cpu->cd.ppc.spr[SPR_LR] = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) 
-	    << PPC_INSTR_ALIGNMENT_SHIFT)) + ic->arg[1];
-
-	/*  Calculate new PC from start of page + arg[0]  */
-	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (int32_t)ic->arg[0];
-
-	cpu_functioncall_trace(cpu, cpu->pc);
-
-	/*  Find the new physical page and update the translation pointers:  */
-	quick_pc_to_pointers(cpu);
-}
-X(bla_trace)
-{
-	/*  Calculate LR:  */
-	cpu->cd.ppc.spr[SPR_LR] = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) 
-	    << PPC_INSTR_ALIGNMENT_SHIFT)) + ic->arg[1];
-
-	cpu->pc = (int32_t)ic->arg[0];
-	cpu_functioncall_trace(cpu, cpu->pc);
-	quick_pc_to_pointers(cpu);
-}
-
-
-/*
- *  bl_samepage:  Branch and Link (to within the same translated page)
- *
- *  arg[0] = pointer to new ppc_instr_call
- *  arg[1] = lr offset (relative to start of current page)
- */
-X(bl_samepage)
-{
-	/*  Calculate LR:  */
-	cpu->cd.ppc.spr[SPR_LR] = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) 
-	    << PPC_INSTR_ALIGNMENT_SHIFT)) + ic->arg[1];
-
-	cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
-}
-
-
-/*
- *  bl_samepage_trace:  Branch and Link (to within the same translated page)
- *
- *  arg[0] = pointer to new ppc_instr_call
- *  arg[1] = lr offset (relative to start of current page)
- */
-X(bl_samepage_trace)
-{
-	uint32_t low_pc;
-
-	/*  Calculate LR:  */
-	cpu->cd.ppc.spr[SPR_LR] = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) 
-	    << PPC_INSTR_ALIGNMENT_SHIFT)) + ic->arg[1];
-
-	cpu->cd.ppc.next_ic = (struct ppc_instr_call *) ic->arg[0];
-
-	/*  Calculate new PC (for the trace)  */
-	low_pc = ((size_t)cpu->cd.ppc.next_ic - (size_t)
-	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call);
-	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu_functioncall_trace(cpu, cpu->pc);
-}
-
-
-/*
- *  cntlzw:  Count leading zeroes (32-bit word).
- *
- *  arg[0] = ptr to rs
- *  arg[1] = ptr to ra
- */
-X(cntlzw)
-{
-	uint32_t tmp = reg(ic->arg[0]);
-	int i;
-	for (i=0; i<32; i++) {
-		if (tmp & 0x80000000)
-			break;
-		tmp <<= 1;
-	}
-	reg(ic->arg[1]) = i;
-}
-
-
-/*
- *  cmpd:  Compare Doubleword
- *
- *  arg[0] = ptr to ra
- *  arg[1] = ptr to rb
- *  arg[2] = 28 - 4*bf
- */
-X(cmpd)
-{
-	int64_t tmp = reg(ic->arg[0]), tmp2 = reg(ic->arg[1]);
-	int bf_shift = ic->arg[2], c;
-	if (tmp < tmp2)
-		c = 8;
-	else if (tmp > tmp2)
-		c = 4;
-	else
-		c = 2;
-	/*  SO bit, copied from XER  */
-	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
-	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
-	cpu->cd.ppc.cr |= (c << bf_shift);
-}
-
-
-/*
- *  cmpld:  Compare Doubleword, unsigned
- *
- *  arg[0] = ptr to ra
- *  arg[1] = ptr to rb
- *  arg[2] = 28 - 4*bf
- */
-X(cmpld)
-{
-	uint64_t tmp = reg(ic->arg[0]), tmp2 = reg(ic->arg[1]);
-	int bf_shift = ic->arg[2], c;
-	if (tmp < tmp2)
-		c = 8;
-	else if (tmp > tmp2)
-		c = 4;
-	else
-		c = 2;
-	/*  SO bit, copied from XER  */
-	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
-	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
-	cpu->cd.ppc.cr |= (c << bf_shift);
-}
-
-
-/*
- *  cmpdi:  Compare Doubleword immediate
- *
- *  arg[0] = ptr to ra
- *  arg[1] = int32_t imm
- *  arg[2] = 28 - 4*bf
- */
-X(cmpdi)
-{
-	int64_t tmp = reg(ic->arg[0]), imm = (int32_t)ic->arg[1];
-	int bf_shift = ic->arg[2], c;
-	if (tmp < imm)
-		c = 8;
-	else if (tmp > imm)
-		c = 4;
-	else
-		c = 2;
-	/*  SO bit, copied from XER  */
-	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
-	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
-	cpu->cd.ppc.cr |= (c << bf_shift);
-}
-
-
-/*
- *  cmpldi:  Compare Doubleword immediate, logical
- *
- *  arg[0] = ptr to ra
- *  arg[1] = int32_t imm
- *  arg[2] = 28 - 4*bf
- */
-X(cmpldi)
-{
-	uint64_t tmp = reg(ic->arg[0]), imm = (uint32_t)ic->arg[1];
-	int bf_shift = ic->arg[2], c;
-	if (tmp < imm)
-		c = 8;
-	else if (tmp > imm)
-		c = 4;
-	else
-		c = 2;
-	/*  SO bit, copied from XER  */
-	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
-	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
-	cpu->cd.ppc.cr |= (c << bf_shift);
-}
-
-
-/*
- *  cmpw:  Compare Word
- *
- *  arg[0] = ptr to ra
- *  arg[1] = ptr to rb
- *  arg[2] = 28 - 4*bf
- */
-X(cmpw)
-{
-	int32_t tmp = reg(ic->arg[0]), tmp2 = reg(ic->arg[1]);
-	int bf_shift = ic->arg[2], c;
-	if (tmp < tmp2)
-		c = 8;
-	else if (tmp > tmp2)
-		c = 4;
-	else
-		c = 2;
-	/*  SO bit, copied from XER  */
-	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
-	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
-	cpu->cd.ppc.cr |= (c << bf_shift);
-}
-X(cmpw_cr0)
-{
-	/*  arg[2] is assumed to be 28  */
-	int32_t tmp = reg(ic->arg[0]), tmp2 = reg(ic->arg[1]);
-	cpu->cd.ppc.cr &= ~(0xf0000000);
-	if (tmp < tmp2)
-		cpu->cd.ppc.cr |= 0x80000000;
-	else if (tmp > tmp2)
-		cpu->cd.ppc.cr |= 0x40000000;
-	else
-		cpu->cd.ppc.cr |= 0x20000000;
-	cpu->cd.ppc.cr |= ((cpu->cd.ppc.spr[SPR_XER] >> 3) & 0x10000000);
-}
-
-
-/*
- *  cmplw:  Compare Word, unsigned
- *
- *  arg[0] = ptr to ra
- *  arg[1] = ptr to rb
- *  arg[2] = 28 - 4*bf
- */
-X(cmplw)
-{
-	uint32_t tmp = reg(ic->arg[0]), tmp2 = reg(ic->arg[1]);
-	int bf_shift = ic->arg[2], c;
-	if (tmp < tmp2)
-		c = 8;
-	else if (tmp > tmp2)
-		c = 4;
-	else
-		c = 2;
-	/*  SO bit, copied from XER  */
-	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
-	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
-	cpu->cd.ppc.cr |= (c << bf_shift);
-}
-
-
-/*
- *  cmpwi:  Compare Word immediate
- *
- *  arg[0] = ptr to ra
- *  arg[1] = int32_t imm
- *  arg[2] = 28 - 4*bf
- */
-X(cmpwi)
-{
-	int32_t tmp = reg(ic->arg[0]), imm = ic->arg[1];
-	int bf_shift = ic->arg[2], c;
-	if (tmp < imm)
-		c = 8;
-	else if (tmp > imm)
-		c = 4;
-	else
-		c = 2;
-	/*  SO bit, copied from XER  */
-	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
-	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
-	cpu->cd.ppc.cr |= (c << bf_shift);
-}
-X(cmpwi_cr0)
-{
-	/*  arg[2] is assumed to be 28  */
-	int32_t tmp = reg(ic->arg[0]), imm = ic->arg[1];
-	cpu->cd.ppc.cr &= ~(0xf0000000);
-	if (tmp < imm)
-		cpu->cd.ppc.cr |= 0x80000000;
-	else if (tmp > imm)
-		cpu->cd.ppc.cr |= 0x40000000;
-	else
-		cpu->cd.ppc.cr |= 0x20000000;
-	cpu->cd.ppc.cr |= ((cpu->cd.ppc.spr[SPR_XER] >> 3) & 0x10000000);
-}
-
-
-/*
- *  cmplwi:  Compare Word immediate, logical
- *
- *  arg[0] = ptr to ra
- *  arg[1] = int32_t imm
- *  arg[2] = 28 - 4*bf
- */
-X(cmplwi)
-{
-	uint32_t tmp = reg(ic->arg[0]), imm = ic->arg[1];
-	int bf_shift = ic->arg[2], c;
-	if (tmp < imm)
-		c = 8;
-	else if (tmp > imm)
-		c = 4;
-	else
-		c = 2;
-	/*  SO bit, copied from XER  */
-	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
-	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
-	cpu->cd.ppc.cr |= (c << bf_shift);
-}
-
-
-/*
- *  dcbz:  Data-Cache Block Zero
- *
- *  arg[0] = ptr to ra (or zero)
- *  arg[1] = ptr to rb
- */
-X(dcbz)
-{
-	MODE_uint_t addr = reg(ic->arg[0]) + reg(ic->arg[1]);
-	unsigned char cacheline[128];
-	size_t cacheline_size = 1 << cpu->cd.ppc.cpu_type.dlinesize;
-	size_t cleared = 0;
-
-	/*  Synchronize the PC first:  */
-	cpu->pc = (cpu->pc & ~0xfff) + ic->arg[2];
-
-	addr &= ~(cacheline_size - 1);
-	memset(cacheline, 0, sizeof(cacheline));
-
-	while (cleared < cacheline_size) {
-		int to_clear = cacheline_size < sizeof(cacheline)?
-		    cacheline_size : sizeof(cacheline);
-#ifdef MODE32
-		unsigned char *page = cpu->cd.ppc.host_store[addr >> 12];
-		if (page != NULL) {
-			memset(page + (addr & 0xfff), 0, to_clear);
-		} else
-#endif
-		if (cpu->memory_rw(cpu, cpu->mem, addr, cacheline,
-		    to_clear, MEM_WRITE, CACHE_DATA) != MEMORY_ACCESS_OK) {
-			/*  exception  */
-			return;
-		}
-
-		cleared += to_clear;
-		addr += to_clear;
-	}
-}
-
-
-/*
- *  mtfsf:  Copy FPR into the FPSCR.
- *
- *  arg[0] = ptr to frb
- *  arg[1] = mask
- */
-X(mtfsf)
-{
-	CHECK_FOR_FPU_EXCEPTION;
-	cpu->cd.ppc.fpscr &= ~ic->arg[1];
-	cpu->cd.ppc.fpscr |= (ic->arg[1] & (*(uint64_t *)ic->arg[0]));
-}
-
-
-/*
- *  mffs:  Copy FPSCR into a FPR.
- *
- *  arg[0] = ptr to frt
- */
-X(mffs)
-{
-	CHECK_FOR_FPU_EXCEPTION;
-	(*(uint64_t *)ic->arg[0]) = cpu->cd.ppc.fpscr;
-}
-
-
-/*
- *  fmr:  Floating-point Move
- *
- *  arg[0] = ptr to frb
- *  arg[1] = ptr to frt
- */
-X(fmr)
-{
-	/*
-	 *  This works like a normal register to register copy, but
-	 *  a) it can cause an FPU exception, and b) the move is always
-	 *  64-bit, even when running in 32-bit mode.
-	 */
-	CHECK_FOR_FPU_EXCEPTION;
-	*(uint64_t *)ic->arg[1] = *(uint64_t *)ic->arg[0];
-}
-
-
-/*
- *  fabs:  Floating-point Absulute Value
- *
- *  arg[0] = ptr to frb
- *  arg[1] = ptr to frt
- */
-X(fabs)
-{
-	uint64_t v;
-	CHECK_FOR_FPU_EXCEPTION;
-	v = *(uint64_t *)ic->arg[0];
-	*(uint64_t *)ic->arg[1] = v & 0x7fffffffffffffffULL;
-}
-
-
-/*
- *  fneg:  Floating-point Negate
- *
- *  arg[0] = ptr to frb
- *  arg[1] = ptr to frt
- */
-X(fneg)
-{
-	uint64_t v;
-	CHECK_FOR_FPU_EXCEPTION;
-	v = *(uint64_t *)ic->arg[0];
-	*(uint64_t *)ic->arg[1] = v ^ 0x8000000000000000ULL;
-}
-
-
-/*
- *  fcmpu:  Floating-point Compare Unordered
- *
- *  arg[0] = 28 - 4*bf  (bitfield shift)
- *  arg[1] = ptr to fra
- *  arg[2] = ptr to frb
- */
-X(fcmpu)
-{
-	struct ieee_float_value fra, frb;
-	int bf_shift = ic->arg[0], c = 0;
-
-	CHECK_FOR_FPU_EXCEPTION;
-
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &fra, IEEE_FMT_D);
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[2], &frb, IEEE_FMT_D);
-	if (fra.nan | frb.nan) {
-		c = 1;
-	} else {
-		if (fra.f < frb.f)
-			c = 8;
-		else if (fra.f > frb.f)
-			c = 4;
-		else
-			c = 2;
-	}
-	/*  TODO: Signaling vs Quiet NaN  */
-	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
-	cpu->cd.ppc.cr |= ((c&0xe) << bf_shift);
-	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
-	cpu->cd.ppc.fpscr |= (c << PPC_FPSCR_FPCC_SHIFT);
-}
-
-
-/*
- *  frsp:  Floating-point Round to Single Precision
- *
- *  arg[0] = ptr to frb
- *  arg[1] = ptr to frt
- */
-X(frsp)
-{
-	struct ieee_float_value frb;
-	float fl = 0.0;
-	int c = 0;
-
-	CHECK_FOR_FPU_EXCEPTION;
-
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[0], &frb, IEEE_FMT_D);
-	if (frb.nan) {
-		c = 1;
-	} else {
-		fl = frb.f;
-		if (fl < 0.0)
-			c = 8;
-		else if (fl > 0.0)
-			c = 4;
-		else
-			c = 2;
-	}
-	/*  TODO: Signaling vs Quiet NaN  */
-	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
-	cpu->cd.ppc.fpscr |= (c << PPC_FPSCR_FPCC_SHIFT);
-	(*(uint64_t *)ic->arg[1]) = ieee_store_float_value(fl, IEEE_FMT_D);
-}
-
-
-/*
- *  fctiwz:  Floating-point Convert to Integer Word, Round to Zero
- *
- *  arg[0] = ptr to frb
- *  arg[1] = ptr to frt
- */
-X(fctiwz)
-{
-	struct ieee_float_value frb;
-	uint32_t res = 0;
-
-	CHECK_FOR_FPU_EXCEPTION;
-
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[0], &frb, IEEE_FMT_D);
-	if (!frb.nan) {
-		if (frb.f >= 2147483647.0)
-			res = 0x7fffffff;
-		else if (frb.f <= -2147483648.0)
-			res = 0x80000000;
-		else
-			res = (int32_t) frb.f;
-	}
-
-	*(uint64_t *)ic->arg[1] = (uint32_t)res;
-}
-
-
-/*
- *  fmul:  Floating-point Multiply
- *
- *  arg[0] = ptr to frt
- *  arg[1] = ptr to fra
- *  arg[2] = ptr to frc
- */
-X(fmul)
-{
-	struct ieee_float_value fra;
-	struct ieee_float_value frc;
-	double result = 0.0;
-	int c;
-
-	CHECK_FOR_FPU_EXCEPTION;
-
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &fra, IEEE_FMT_D);
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[2], &frc, IEEE_FMT_D);
-	result = fra.f * frc.f;
-	if (isnan(result))
-		c = 1;
-	else {
-		if (result < 0.0)
-			c = 8;
-		else if (result > 0.0)
-			c = 4;
-		else
-			c = 2;
-	}
-	/*  TODO: Signaling vs Quiet NaN  */
-	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
-	cpu->cd.ppc.fpscr |= (c << PPC_FPSCR_FPCC_SHIFT);
-
-	(*(uint64_t *)ic->arg[0]) =
-	    ieee_store_float_value(result, IEEE_FMT_D);
-}
-X(fmuls)
-{
-	/*  TODO  */
-	instr(fmul)(cpu, ic);
-}
-
-
-/*
- *  fmadd:  Floating-point Multiply and Add
- *
- *  arg[0] = ptr to frt
- *  arg[1] = ptr to fra
- *  arg[2] = copy of the instruction word
- */
-X(fmadd)
-{
-	uint32_t iw = ic->arg[2];
-	int b = (iw >> 11) & 31, c = (iw >> 6) & 31;
-	struct ieee_float_value fra;
-	struct ieee_float_value frb;
-	struct ieee_float_value frc;
-	double result = 0.0;
-	int cc;
-
-	CHECK_FOR_FPU_EXCEPTION;
-
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &fra, IEEE_FMT_D);
-	ieee_interpret_float_value(cpu->cd.ppc.fpr[b], &frb, IEEE_FMT_D);
-	ieee_interpret_float_value(cpu->cd.ppc.fpr[c], &frc, IEEE_FMT_D);
-	result = fra.f * frc.f + frb.f;
-	if (isnan(result))
-		cc = 1;
-	else {
-		if (result < 0.0)
-			cc = 8;
-		else if (result > 0.0)
-			cc = 4;
-		else
-			cc = 2;
-	}
-	/*  TODO: Signaling vs Quiet NaN  */
-	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
-	cpu->cd.ppc.fpscr |= (cc << PPC_FPSCR_FPCC_SHIFT);
-
-	(*(uint64_t *)ic->arg[0]) =
-	    ieee_store_float_value(result, IEEE_FMT_D);
-}
-
-
-/*
- *  fmsub:  Floating-point Multiply and Sub
- *
- *  arg[0] = ptr to frt
- *  arg[1] = ptr to fra
- *  arg[2] = copy of the instruction word
- */
-X(fmsub)
-{
-	uint32_t iw = ic->arg[2];
-	int b = (iw >> 11) & 31, c = (iw >> 6) & 31;
-	struct ieee_float_value fra;
-	struct ieee_float_value frb;
-	struct ieee_float_value frc;
-	double result = 0.0;
-	int cc;
-
-	CHECK_FOR_FPU_EXCEPTION;
-
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &fra, IEEE_FMT_D);
-	ieee_interpret_float_value(cpu->cd.ppc.fpr[b], &frb, IEEE_FMT_D);
-	ieee_interpret_float_value(cpu->cd.ppc.fpr[c], &frc, IEEE_FMT_D);
-	result = fra.f * frc.f - frb.f;
-	if (isnan(result))
-		cc = 1;
-	else {
-		if (result < 0.0)
-			cc = 8;
-		else if (result > 0.0)
-			cc = 4;
-		else
-			cc = 2;
-	}
-	/*  TODO: Signaling vs Quiet NaN  */
-	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
-	cpu->cd.ppc.fpscr |= (cc << PPC_FPSCR_FPCC_SHIFT);
-
-	(*(uint64_t *)ic->arg[0]) =
-	    ieee_store_float_value(result, IEEE_FMT_D);
-}
-
-
-/*
- *  fadd, fsub, fdiv:  Various Floating-point operationgs
- *
- *  arg[0] = ptr to fra
- *  arg[1] = ptr to frb
- *  arg[2] = ptr to frt
- */
-X(fadd)
-{
-	struct ieee_float_value fra;
-	struct ieee_float_value frb;
-	double result = 0.0;
-	int c;
-
-	CHECK_FOR_FPU_EXCEPTION;
-
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[0], &fra, IEEE_FMT_D);
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &frb, IEEE_FMT_D);
-	result = fra.f + frb.f;
-	if (isnan(result))
-		c = 1;
-	else {
-		if (result < 0.0)
-			c = 8;
-		else if (result > 0.0)
-			c = 4;
-		else
-			c = 2;
-	}
-	/*  TODO: Signaling vs Quiet NaN  */
-	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
-	cpu->cd.ppc.fpscr |= (c << PPC_FPSCR_FPCC_SHIFT);
-
-	(*(uint64_t *)ic->arg[2]) =
-	    ieee_store_float_value(result, IEEE_FMT_D);
-}
-X(fadds)
-{
-	/*  TODO  */
-	instr(fadd)(cpu, ic);
-}
-X(fsub)
-{
-	struct ieee_float_value fra;
-	struct ieee_float_value frb;
-	double result = 0.0;
-	int c;
-
-	CHECK_FOR_FPU_EXCEPTION;
-
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[0], &fra, IEEE_FMT_D);
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &frb, IEEE_FMT_D);
-	result = fra.f - frb.f;
-	if (isnan(result))
-		c = 1;
-	else {
-		if (result < 0.0)
-			c = 8;
-		else if (result > 0.0)
-			c = 4;
-		else
-			c = 2;
-	}
-	/*  TODO: Signaling vs Quiet NaN  */
-	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
-	cpu->cd.ppc.fpscr |= (c << PPC_FPSCR_FPCC_SHIFT);
-
-	(*(uint64_t *)ic->arg[2]) =
-	    ieee_store_float_value(result, IEEE_FMT_D);
-}
-X(fsubs)
-{
-	/*  TODO  */
-	instr(fsub)(cpu, ic);
-}
-X(fdiv)
-{
-	struct ieee_float_value fra;
-	struct ieee_float_value frb;
-	double result = 0.0;
-	int c;
-
-	CHECK_FOR_FPU_EXCEPTION;
-
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[0], &fra, IEEE_FMT_D);
-	ieee_interpret_float_value(*(uint64_t *)ic->arg[1], &frb, IEEE_FMT_D);
-	result = fra.f / frb.f;
-	if (isnan(result))
-		c = 1;
-	else {
-		if (result < 0.0)
-			c = 8;
-		else if (result > 0.0)
-			c = 4;
-		else
-			c = 2;
-	}
-	/*  TODO: Signaling vs Quiet NaN  */
-	cpu->cd.ppc.fpscr &= ~(PPC_FPSCR_FPCC | PPC_FPSCR_VXNAN);
-	cpu->cd.ppc.fpscr |= (c << PPC_FPSCR_FPCC_SHIFT);
-
-	(*(uint64_t *)ic->arg[2]) =
-	    ieee_store_float_value(result, IEEE_FMT_D);
-}
-X(fdivs)
-{
-	/*  TODO  */
-	instr(fdiv)(cpu, ic);
-}
-
-
-/*
- *  llsc: Load-linked and store conditional
- *
- *  arg[0] = copy of the instruction word.
- */
-X(llsc)
-{
-	int iw = ic->arg[0], len = 4, load = 0, xo = (iw >> 1) & 1023;
-	int i, rc = iw & 1, rt, ra, rb;
-	uint64_t addr = 0, value;
-	unsigned char d[8];
-
-	switch (xo) {
-	case PPC_31_LDARX:
-		len = 8;
-	case PPC_31_LWARX:
-		load = 1;
-		break;
-	case PPC_31_STDCX_DOT:
-		len = 8;
-	case PPC_31_STWCX_DOT:
-		break;
-	}
-
-	rt = (iw >> 21) & 31;
-	ra = (iw >> 16) & 31;
-	rb = (iw >> 11) & 31;
-
-	if (ra != 0)
-		addr = cpu->cd.ppc.gpr[ra];
-	addr += cpu->cd.ppc.gpr[rb];
-
-	if (load) {
-		if (rc) {
-			fatal("ll: rc-bit set?\n");
-			exit(1);
-		}
-		if (cpu->memory_rw(cpu, cpu->mem, addr, d, len,
-		    MEM_READ, CACHE_DATA) != MEMORY_ACCESS_OK) {
-			fatal("ll: error: TODO\n");
-			exit(1);
-		}
-
-		value = 0;
-		for (i=0; i<len; i++) {
-			value <<= 8;
-			if (cpu->byte_order == EMUL_BIG_ENDIAN)
-				value |= d[i];
-			else
-				value |= d[len - 1 - i];
-		}
-
-		cpu->cd.ppc.gpr[rt] = value;
-		cpu->cd.ppc.ll_addr = addr;
-		cpu->cd.ppc.ll_bit = 1;
-	} else {
-		uint32_t old_so = cpu->cd.ppc.spr[SPR_XER] & PPC_XER_SO;
-		if (!rc) {
-			fatal("sc: rc-bit not set?\n");
-			exit(1);
-		}
-
-		value = cpu->cd.ppc.gpr[rt];
-
-		/*  "If the store is performed, bits 0-2 of Condition
-		    Register Field 0 are set to 0b001, otherwise, they are
-		    set to 0b000. The SO bit of the XER is copied to to bit
-		    4 of Condition Register Field 0.  */
-		if (!cpu->cd.ppc.ll_bit || cpu->cd.ppc.ll_addr != addr) {
-			cpu->cd.ppc.cr &= 0x0fffffff;
-			if (old_so)
-				cpu->cd.ppc.cr |= 0x10000000;
-			cpu->cd.ppc.ll_bit = 0;
-			return;
-		}
-
-		for (i=0; i<len; i++) {
-			if (cpu->byte_order == EMUL_BIG_ENDIAN)
-				d[len - 1 - i] = value >> (8*i);
-			else
-				d[i] = value >> (8*i);
-		}
-
-		if (cpu->memory_rw(cpu, cpu->mem, addr, d, len,
-		    MEM_WRITE, CACHE_DATA) != MEMORY_ACCESS_OK) {
-			fatal("sc: error: TODO\n");
-			exit(1);
-		}
-
-		cpu->cd.ppc.cr &= 0x0fffffff;
-		cpu->cd.ppc.cr |= 0x20000000;	/*  success!  */
-		if (old_so)
-			cpu->cd.ppc.cr |= 0x10000000;
-
-		/*  Clear _all_ CPUs' ll_bits:  */
-		for (i=0; i<cpu->machine->ncpus; i++)
-			cpu->machine->cpus[i]->cd.ppc.ll_bit = 0;
-	}
-}
-
-
-/*
- *  mtsr, mtsrin:  Move To Segment Register [Indirect]
- *
- *  arg[0] = sr number, or for indirect mode: ptr to rb
- *  arg[1] = ptr to rt
- *
- *  TODO: These only work for 32-bit mode!
- */
-X(mtsr)
-{
-	int sr_num = ic->arg[0];
-	uint32_t old = cpu->cd.ppc.sr[sr_num];
-	cpu->cd.ppc.sr[sr_num] = reg(ic->arg[1]);
-
-	if (cpu->cd.ppc.sr[sr_num] != old)
-		cpu->invalidate_translation_caches(cpu, ic->arg[0] << 28,
-		    INVALIDATE_ALL | INVALIDATE_VADDR_UPPER4);
-}
-X(mtsrin)
-{
-	int sr_num = reg(ic->arg[0]) >> 28;
-	uint32_t old = cpu->cd.ppc.sr[sr_num];
-	cpu->cd.ppc.sr[sr_num] = reg(ic->arg[1]);
-
-	if (cpu->cd.ppc.sr[sr_num] != old)
-		cpu->invalidate_translation_caches(cpu, sr_num << 28,
-		    INVALIDATE_ALL | INVALIDATE_VADDR_UPPER4);
-}
-
-
-/*
- *  mfsrin, mtsrin:  Move From/To Segment Register Indirect
- *
- *  arg[0] = sr number, or for indirect mode: ptr to rb
- *  arg[1] = ptr to rt
- */
-X(mfsr)
-{
-	/*  TODO: This only works for 32-bit mode  */
-	reg(ic->arg[1]) = cpu->cd.ppc.sr[ic->arg[0]];
-}
-X(mfsrin)
-{
-	/*  TODO: This only works for 32-bit mode  */
-	uint32_t sr_num = reg(ic->arg[0]) >> 28;
-	reg(ic->arg[1]) = cpu->cd.ppc.sr[sr_num];
-}
-
-
-/*
- *  rldicl:
- *
- *  arg[0] = copy of the instruction word
- */
-X(rldicl)
-{
-	int rs = (ic->arg[0] >> 21) & 31;
-	int ra = (ic->arg[0] >> 16) & 31;
-	int sh = ((ic->arg[0] >> 11) & 31) | ((ic->arg[0] & 2) << 4);
-	int mb = ((ic->arg[0] >> 6) & 31) | (ic->arg[0] & 0x20);
-	int rc = ic->arg[0] & 1;
-	uint64_t tmp = cpu->cd.ppc.gpr[rs], tmp2;
-	/*  TODO: Fix this, its performance is awful:  */
-	while (sh-- != 0) {
-		int b = (tmp >> 63) & 1;
-		tmp = (tmp << 1) | b;
-	}
-	tmp2 = 0;
-	while (mb <= 63) {
-		tmp |= ((uint64_t)1 << (63-mb));
-		mb ++;
-	}
-	cpu->cd.ppc.gpr[ra] = tmp & tmp2;
-	if (rc)
-		update_cr0(cpu, cpu->cd.ppc.gpr[ra]);
-}
-
-
-/*
- *  rldicr:
- *
- *  arg[0] = copy of the instruction word
- */
-X(rldicr)
-{
-	int rs = (ic->arg[0] >> 21) & 31;
-	int ra = (ic->arg[0] >> 16) & 31;
-	int sh = ((ic->arg[0] >> 11) & 31) | ((ic->arg[0] & 2) << 4);
-	int me = ((ic->arg[0] >> 6) & 31) | (ic->arg[0] & 0x20);
-	int rc = ic->arg[0] & 1;
-	uint64_t tmp = cpu->cd.ppc.gpr[rs];
-	/*  TODO: Fix this, its performance is awful:  */
-	while (sh-- != 0) {
-		int b = (tmp >> 63) & 1;
-		tmp = (tmp << 1) | b;
-	}
-	while (me++ < 63)
-		tmp &= ~((uint64_t)1 << (63-me));
-	cpu->cd.ppc.gpr[ra] = tmp;
-	if (rc)
-		update_cr0(cpu, tmp);
-}
-
-
-/*
- *  rldimi:
- *
- *  arg[0] = copy of the instruction word
- */
-X(rldimi)
-{
-	uint32_t iw = ic->arg[0];
-	int rs = (iw >> 21) & 31, ra = (iw >> 16) & 31;
-	int sh = ((iw >> 11) & 31) | ((iw & 2) << 4);
-	int mb = ((iw >> 6) & 31) | (iw & 0x20);
-	int rc = ic->arg[0] & 1;
-	int m;
-	uint64_t tmp, s = cpu->cd.ppc.gpr[rs];
-	/*  TODO: Fix this, its performance is awful:  */
-	while (sh-- != 0) {
-		int b = (s >> 63) & 1;
-		s = (s << 1) | b;
-	}
-	m = mb; tmp = 0;
-	do {
-		tmp |= ((uint64_t)1 << (63-m));
-		m ++;
-	} while (m != 63 - sh);
-	cpu->cd.ppc.gpr[ra] &= ~tmp;
-	cpu->cd.ppc.gpr[ra] |= (tmp & s);
-	if (rc)
-		update_cr0(cpu, cpu->cd.ppc.gpr[ra]);
-}
-
-
-/*
- *  rlwnm:
- *
- *  arg[0] = ptr to ra
- *  arg[1] = mask
- *  arg[2] = copy of the instruction word
- */
-X(rlwnm)
-{
-	uint32_t tmp, iword = ic->arg[2];
-	int rs = (iword >> 21) & 31;
-	int rb = (iword >> 11) & 31;
-	int sh = cpu->cd.ppc.gpr[rb] & 0x1f;
-	tmp = (uint32_t)cpu->cd.ppc.gpr[rs];
-	tmp = (tmp << sh) | (tmp >> (32-sh));
-	tmp &= (uint32_t)ic->arg[1];
-	reg(ic->arg[0]) = tmp;
-}
-DOT0(rlwnm)
-
-
-/*
- *  rlwinm:
- *
- *  arg[0] = ptr to ra
- *  arg[1] = mask
- *  arg[2] = copy of the instruction word
- */
-X(rlwinm)
-{
-	uint32_t tmp, iword = ic->arg[2];
-	int rs = (iword >> 21) & 31;
-	int sh = (iword >> 11) & 31;
-	tmp = (uint32_t)cpu->cd.ppc.gpr[rs];
-	tmp = (tmp << sh) | (tmp >> (32-sh));
-	tmp &= (uint32_t)ic->arg[1];
-	reg(ic->arg[0]) = tmp;
-}
-DOT0(rlwinm)
-
-
-/*
- *  rlwimi:
- *
- *  arg[0] = ptr to rs
- *  arg[1] = ptr to ra
- *  arg[2] = copy of the instruction word
- */
-X(rlwimi)
-{
-	MODE_uint_t tmp = reg(ic->arg[0]), ra = reg(ic->arg[1]);
-	uint32_t iword = ic->arg[2];
-	int sh = (iword >> 11) & 31;
-	int mb = (iword >> 6) & 31;
-	int me = (iword >> 1) & 31;   
-	int rc = iword & 1;
-
-	tmp = (tmp << sh) | (tmp >> (32-sh));
-
-	for (;;) {
-		uint64_t mask;
-		mask = (uint64_t)1 << (31-mb);
-		ra &= ~mask;
-		ra |= (tmp & mask);
-		if (mb == me)
-			break;
-		mb ++;
-		if (mb == 32)
-			mb = 0;
-	}
-	reg(ic->arg[1]) = ra;
-	if (rc)
-		update_cr0(cpu, ra);
-}
-
-
-/*
- *  srawi:
- *
- *  arg[0] = ptr to rs
- *  arg[1] = ptr to ra
- *  arg[2] = sh (shift amount)
- */
-X(srawi)
-{
-	uint32_t tmp = reg(ic->arg[0]);
-	int i = 0, j = 0, sh = ic->arg[2];
-
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	if (tmp & 0x80000000)
-		i = 1;
-	while (sh-- > 0) {
-		if (tmp & 1)
-			j ++;
-		tmp >>= 1;
-		if (tmp & 0x40000000)
-			tmp |= 0x80000000;
-	}
-	if (i && j>0)
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	reg(ic->arg[1]) = (int64_t)(int32_t)tmp;
-}
-DOT1(srawi)
-
-
-/*
- *  mcrf:  Move inside condition register
- *
- *  arg[0] = 28-4*bf,  arg[1] = 28-4*bfa
- */
-X(mcrf)
-{
-	int bf_shift = ic->arg[0], bfa_shift = ic->arg[1];
-	uint32_t tmp = (cpu->cd.ppc.cr >> bfa_shift) & 0xf;
-	cpu->cd.ppc.cr &= ~(0xf << bf_shift);
-	cpu->cd.ppc.cr |= (tmp << bf_shift);
-}
-
-
-/*
- *  crand, crxor etc:  Condition Register operations
- *
- *  arg[0] = copy of the instruction word
- */
-X(crand) {
-	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
-	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
-	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
-	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
-	cpu->cd.ppc.cr &= ~(1 << (31-bt));
-	if (ba & bb)
-		cpu->cd.ppc.cr |= (1 << (31-bt));
-}
-X(crandc) {
-	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
-	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
-	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
-	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
-	cpu->cd.ppc.cr &= ~(1 << (31-bt));
-	if (!(ba & bb))
-		cpu->cd.ppc.cr |= (1 << (31-bt));
-}
-X(creqv) {
-	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
-	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
-	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
-	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
-	cpu->cd.ppc.cr &= ~(1 << (31-bt));
-	if (!(ba ^ bb))
-		cpu->cd.ppc.cr |= (1 << (31-bt));
-}
-X(cror) {
-	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
-	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
-	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
-	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
-	cpu->cd.ppc.cr &= ~(1 << (31-bt));
-	if (ba | bb)
-		cpu->cd.ppc.cr |= (1 << (31-bt));
-}
-X(crorc) {
-	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
-	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
-	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
-	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
-	cpu->cd.ppc.cr &= ~(1 << (31-bt));
-	if (!(ba | bb))
-		cpu->cd.ppc.cr |= (1 << (31-bt));
-}
-X(crnor) {
-	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
-	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
-	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
-	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
-	cpu->cd.ppc.cr &= ~(1 << (31-bt));
-	if (!(ba | bb))
-		cpu->cd.ppc.cr |= (1 << (31-bt));
-}
-X(crxor) {
-	uint32_t iword = ic->arg[0]; int bt = (iword >> 21) & 31;
-	int ba = (iword >> 16) & 31, bb = (iword >> 11) & 31;
-	ba = (cpu->cd.ppc.cr >> (31-ba)) & 1;
-	bb = (cpu->cd.ppc.cr >> (31-bb)) & 1;
-	cpu->cd.ppc.cr &= ~(1 << (31-bt));
-	if (ba ^ bb)
-		cpu->cd.ppc.cr |= (1 << (31-bt));
-}
-
-
-/*
- *  mfspr: Move from SPR
- *
- *  arg[0] = pointer to destination register
- *  arg[1] = pointer to source SPR
- */
-X(mfspr) {
-	/*  TODO: Check permission  */
-	reg(ic->arg[0]) = reg(ic->arg[1]);
-}
-X(mfspr_pmc1) {
-	/*
-	 *  TODO: This is a temporary hack to make NetBSD/ppc detect
-	 *  a CPU of the correct (emulated) speed.
-	 */
-	reg(ic->arg[0]) = cpu->machine->emulated_hz / 10;
-}
-X(mftb) {
-	/*  NOTE/TODO: This increments the time base (slowly) if it
-	    is being polled.  */
-	if (++cpu->cd.ppc.spr[SPR_TBL] == 0)
-		cpu->cd.ppc.spr[SPR_TBU] ++;
-	reg(ic->arg[0]) = cpu->cd.ppc.spr[SPR_TBL];
-}
-X(mftbu) {
-	reg(ic->arg[0]) = cpu->cd.ppc.spr[SPR_TBU];
-}
-
-
-/*
- *  mtspr: Move to SPR.
- *
- *  arg[0] = pointer to source register
- *  arg[1] = pointer to the SPR
- */
-X(mtspr) {
-	/*  TODO: Check permission  */
-	reg(ic->arg[1]) = reg(ic->arg[0]);
-}
-X(mtspr_sprg2) {
-	if (cpu->cd.ppc.bits == 32) {
-		// Ignore for now. FreeBSD/powerpc seems to write 0xffffffe0
-		// here, and read it back. If it is non-zero, it assumes a 64-bit
-		// cpu.
-	} else {
-		reg(ic->arg[1]) = reg(ic->arg[0]);
-	}
-}
-X(mtlr) {
-	cpu->cd.ppc.spr[SPR_LR] = reg(ic->arg[0]);
-}
-X(mtctr) {
-	cpu->cd.ppc.spr[SPR_CTR] = reg(ic->arg[0]);
-}
-
-
-/*
- *  rfi[d]:  Return from Interrupt
- */
-X(rfi)
-{
-	uint64_t tmp;
-
-	reg_access_msr(cpu, &tmp, 0, 0);
-	tmp &= ~0xffff;
-	tmp |= (cpu->cd.ppc.spr[SPR_SRR1] & 0xffff);
-	reg_access_msr(cpu, &tmp, 1, 0);
-
-	cpu->pc = cpu->cd.ppc.spr[SPR_SRR0];
-	quick_pc_to_pointers(cpu);
-}
-X(rfid)
-{
-	uint64_t tmp, mask = 0x800000000000ff73ULL;
-
-	reg_access_msr(cpu, &tmp, 0, 0);
-	tmp &= ~mask;
-	tmp |= (cpu->cd.ppc.spr[SPR_SRR1] & mask);
-	reg_access_msr(cpu, &tmp, 1, 0);
-
-	cpu->pc = cpu->cd.ppc.spr[SPR_SRR0];
-	if (!(tmp & PPC_MSR_SF))
-		cpu->pc = (uint32_t)cpu->pc;
-	quick_pc_to_pointers(cpu);
-}
-
-
-/*
- *  mfcr:  Move From Condition Register
- *
- *  arg[0] = pointer to destination register
- */
-X(mfcr)
-{
-	reg(ic->arg[0]) = cpu->cd.ppc.cr;
-}
-
-
-/*
- *  mfmsr:  Move From MSR
- *
- *  arg[0] = pointer to destination register
- */
-X(mfmsr)
-{
-	reg_access_msr(cpu, (uint64_t*)ic->arg[0], 0, 0);
-}
-
-
-/*
- *  mtmsr:  Move To MSR
- *
- *  arg[0] = pointer to source register
- *  arg[1] = page offset of the next instruction
- *  arg[2] = 0 for 32-bit (mtmsr), 1 for 64-bit (mtmsrd)
- */
-X(mtmsr)
-{
-	MODE_uint_t old_pc;
-	uint64_t x = reg(ic->arg[0]);
-
-	/*  TODO: check permission!  */
-
-	/*  Synchronize the PC (pointing to _after_ this instruction)  */
-	cpu->pc = (cpu->pc & ~0xfff) + ic->arg[1];
-	old_pc = cpu->pc;
-
-	if (!ic->arg[2]) {
-		uint64_t y;
-		reg_access_msr(cpu, &y, 0, 0);
-		x = (y & 0xffffffff00000000ULL) | (x & 0xffffffffULL);
-	}
-
-	reg_access_msr(cpu, &x, 1, 1);
-
-	/*
-	 *  Super-ugly hack:  If the pc wasn't changed (i.e. if there was no
-	 *  exception while accessing the msr), then we _decrease_ the PC by 4
-	 *  again. This is because the next ic could be an end_of_page.
-	 */
-	if ((MODE_uint_t)cpu->pc == old_pc)
-		cpu->pc -= 4;
-}
-
-
-/*
- *  wrteei:  Write EE immediate  (on PPC405GP)
- *
- *  arg[0] = either 0 or 0x8000
- */
-X(wrteei)
-{
-	/*  TODO: check permission!  */
-	uint64_t x;
-
-	/*  Synchronize the PC (pointing to _after_ this instruction)  */
-	cpu->pc = (cpu->pc & ~0xfff) + ic->arg[1];
-
-	reg_access_msr(cpu, &x, 0, 0);
-	x = (x & ~0x8000) | ic->arg[0];
-	reg_access_msr(cpu, &x, 1, 1);
-}
-
-
-/*
- *  mtcrf:  Move To Condition Register Fields
- *
- *  arg[0] = pointer to source register
- */
-X(mtcrf)
-{
-	cpu->cd.ppc.cr &= ~ic->arg[1];
-	cpu->cd.ppc.cr |= (reg(ic->arg[0]) & ic->arg[1]);
-}
-
-
-/*
- *  mulli:  Multiply Low Immediate.
- *
- *  arg[0] = pointer to source register ra
- *  arg[1] = int32_t immediate
- *  arg[2] = pointer to destination register rt
- */
-X(mulli)
-{
-	reg(ic->arg[2]) = (uint32_t)(reg(ic->arg[0]) * (int32_t)ic->arg[1]);
-}
-
-
-/*
- *  Load/Store Multiple:
- *
- *  arg[0] = rs  (or rt for loads)  NOTE: not a pointer
- *  arg[1] = ptr to ra
- *  arg[2] = int32_t immediate offset
- */
-X(lmw) {
-	MODE_uint_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
-	unsigned char d[4];
-	int rs = ic->arg[0];
-
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page)
-	    / sizeof(struct ppc_instr_call);
-	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1)
-	    << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc |= (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-
-	while (rs <= 31) {
-		if (cpu->memory_rw(cpu, cpu->mem, addr, d, sizeof(d),
-		    MEM_READ, CACHE_DATA) != MEMORY_ACCESS_OK) {
-			/*  exception  */
-			return;
-		}
-
-		if (cpu->byte_order == EMUL_BIG_ENDIAN)
-			cpu->cd.ppc.gpr[rs] = (d[0] << 24) + (d[1] << 16)
-			    + (d[2] << 8) + d[3];
-		else
-			cpu->cd.ppc.gpr[rs] = (d[3] << 24) + (d[2] << 16)
-			    + (d[1] << 8) + d[0];
-
-		rs ++;
-		addr += sizeof(uint32_t);
-	}
-}
-X(stmw) {
-	MODE_uint_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
-	unsigned char d[4];
-	int rs = ic->arg[0];
-
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page)
-	    / sizeof(struct ppc_instr_call);
-	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1)
-	    << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-
-	while (rs <= 31) {
-		uint32_t tmp = cpu->cd.ppc.gpr[rs];
-		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-			d[3] = tmp; d[2] = tmp >> 8;
-			d[1] = tmp >> 16; d[0] = tmp >> 24;
-		} else {
-			d[0] = tmp; d[1] = tmp >> 8;
-			d[2] = tmp >> 16; d[3] = tmp >> 24;
-		}
-		if (cpu->memory_rw(cpu, cpu->mem, addr, d, sizeof(d),
-		    MEM_WRITE, CACHE_DATA) != MEMORY_ACCESS_OK) {
-			/*  exception  */
-			return;
-		}
-
-		rs ++;
-		addr += sizeof(uint32_t);
-	}
-}
-
-
-/*
- *  Load/store string:
- *
- *  arg[0] = rs   (well, rt for lswi)
- *  arg[1] = ptr to ra (or ptr to zero)
- *  arg[2] = nb
- */
-X(lswi)
-{
-	MODE_uint_t addr = reg(ic->arg[1]);
-	int rt = ic->arg[0], nb = ic->arg[2];
-	int sub = 0;
-
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page)
-	    / sizeof(struct ppc_instr_call);
-	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1)
-	    << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-
-	while (nb > 0) {
-		unsigned char d;
-		if (cpu->memory_rw(cpu, cpu->mem, addr, &d, 1,
-		    MEM_READ, CACHE_DATA) != MEMORY_ACCESS_OK) {
-			/*  exception  */
-			return;
-		}
-
-		if (cpu->cd.ppc.mode == MODE_POWER && sub == 0)
-			cpu->cd.ppc.gpr[rt] = 0;
-		cpu->cd.ppc.gpr[rt] &= ~(0xff << (24-8*sub));
-		cpu->cd.ppc.gpr[rt] |= (d << (24-8*sub));
-		sub ++;
-		if (sub == 4) {
-			rt = (rt + 1) & 31;
-			sub = 0;
-		}
-		addr ++;
-		nb --;
-	}
-}
-X(stswi)
-{
-	MODE_uint_t addr = reg(ic->arg[1]);
-	int rs = ic->arg[0], nb = ic->arg[2];
-	uint32_t cur = cpu->cd.ppc.gpr[rs];
-	int sub = 0;
-
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page)
-	    / sizeof(struct ppc_instr_call);
-	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1)
-	    << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-
-	while (nb > 0) {
-		unsigned char d = cur >> 24;
-		if (cpu->memory_rw(cpu, cpu->mem, addr, &d, 1,
-		    MEM_WRITE, CACHE_DATA) != MEMORY_ACCESS_OK) {
-			/*  exception  */
-			return;
-		}
-		cur <<= 8;
-		sub ++;
-		if (sub == 4) {
-			rs = (rs + 1) & 31;
-			sub = 0;
-			cur = cpu->cd.ppc.gpr[rs];
-		}
-		addr ++;
-		nb --;
-	}
-}
-
-
-/*
- *  Shifts, and, or, xor, etc.
- *
- *  arg[0] = pointer to source register rs
- *  arg[1] = pointer to source register rb
- *  arg[2] = pointer to destination register ra
- */
-X(extsb) {
-#ifdef MODE32
-	reg(ic->arg[2]) = (int32_t)(int8_t)reg(ic->arg[0]);
-#else
-	reg(ic->arg[2]) = (int64_t)(int8_t)reg(ic->arg[0]);
-#endif
-}
-DOT2(extsb)
-X(extsh) {
-#ifdef MODE32
-	reg(ic->arg[2]) = (int32_t)(int16_t)reg(ic->arg[0]);
-#else
-	reg(ic->arg[2]) = (int64_t)(int16_t)reg(ic->arg[0]);
-#endif
-}
-DOT2(extsh)
-X(extsw) {
-#ifdef MODE32
-	fatal("TODO: extsw: invalid instruction\n");
-#else
-	reg(ic->arg[2]) = (int64_t)(int32_t)reg(ic->arg[0]);
-#endif
-}
-DOT2(extsw)
-X(slw) {	reg(ic->arg[2]) = (uint64_t)reg(ic->arg[0])
-		    << (reg(ic->arg[1]) & 31); }
-DOT2(slw)
-X(sld) {int sa = reg(ic->arg[1]) & 127;
-	if (sa >= 64)	reg(ic->arg[2]) = 0;
-	else reg(ic->arg[2]) = (uint64_t)reg(ic->arg[0]) << (sa & 63); }
-DOT2(sld)
-X(sraw)
-{
-	uint32_t tmp = reg(ic->arg[0]);
-	int i = 0, j = 0, sh = reg(ic->arg[1]) & 31;
-
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	if (tmp & 0x80000000)
-		i = 1;
-	while (sh-- > 0) {
-		if (tmp & 1)
-			j ++;
-		tmp >>= 1;
-		if (tmp & 0x40000000)
-			tmp |= 0x80000000;
-	}
-	if (i && j>0)
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	reg(ic->arg[2]) = (int64_t)(int32_t)tmp;
-}
-DOT2(sraw)
-X(srw) {	reg(ic->arg[2]) = (uint64_t)reg(ic->arg[0])
-		    >> (reg(ic->arg[1]) & 31); }
-DOT2(srw)
-X(and) {	reg(ic->arg[2]) = reg(ic->arg[0]) & reg(ic->arg[1]); }
-DOT2(and)
-X(nand) {	reg(ic->arg[2]) = ~(reg(ic->arg[0]) & reg(ic->arg[1])); }
-DOT2(nand)
-X(andc) {	reg(ic->arg[2]) = reg(ic->arg[0]) & (~reg(ic->arg[1])); }
-DOT2(andc)
-X(nor) {	reg(ic->arg[2]) = ~(reg(ic->arg[0]) | reg(ic->arg[1])); }
-DOT2(nor)
-X(mr) {		reg(ic->arg[2]) = reg(ic->arg[1]); }
-X(or) {		reg(ic->arg[2]) = reg(ic->arg[0]) | reg(ic->arg[1]); }
-DOT2(or)
-X(orc) {	reg(ic->arg[2]) = reg(ic->arg[0]) | (~reg(ic->arg[1])); }
-DOT2(orc)
-X(xor) {	reg(ic->arg[2]) = reg(ic->arg[0]) ^ reg(ic->arg[1]); }
-DOT2(xor)
-X(eqv) {	reg(ic->arg[2]) = ~(reg(ic->arg[0]) ^ reg(ic->arg[1])); }
-DOT2(eqv)
-
-
-/*
- *  neg:
- *
- *  arg[0] = pointer to source register ra
- *  arg[1] = pointer to destination register rt
- */
-X(neg) {	reg(ic->arg[1]) = -reg(ic->arg[0]); }
-DOT1(neg)
-
-
-/*
- *  mullw, mulhw[u], divw[u]:
- *
- *  arg[0] = pointer to source register ra
- *  arg[1] = pointer to source register rb
- *  arg[2] = pointer to destination register rt
- */
-X(mullw)
-{
-	int32_t sum = (int32_t)reg(ic->arg[0]) * (int32_t)reg(ic->arg[1]);
-	reg(ic->arg[2]) = (int32_t)sum;
-}
-DOT2(mullw)
-X(mulhw)
-{
-	int64_t sum;
-	sum = (int64_t)(int32_t)reg(ic->arg[0])
-	    * (int64_t)(int32_t)reg(ic->arg[1]);
-	reg(ic->arg[2]) = sum >> 32;
-}
-DOT2(mulhw)
-X(mulhwu)
-{
-	uint64_t sum;
-	sum = (uint64_t)(uint32_t)reg(ic->arg[0])
-	    * (uint64_t)(uint32_t)reg(ic->arg[1]);
-	reg(ic->arg[2]) = sum >> 32;
-}
-DOT2(mulhwu)
-X(divw)
-{
-	int32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	int32_t sum;
-	if (b == 0)
-		sum = 0;
-	else
-		sum = a / b;
-	reg(ic->arg[2]) = (uint32_t)sum;
-}
-DOT2(divw)
-X(divwu)
-{
-	uint32_t a = reg(ic->arg[0]), b = reg(ic->arg[1]);
-	uint32_t sum;
-	if (b == 0)
-		sum = 0;
-	else
-		sum = a / b;
-	reg(ic->arg[2]) = sum;
-}
-DOT2(divwu)
-
-
-/*
- *  add:  Add.
- *
- *  arg[0] = pointer to source register ra
- *  arg[1] = pointer to source register rb
- *  arg[2] = pointer to destination register rt
- */
-X(add)     { reg(ic->arg[2]) = reg(ic->arg[0]) + reg(ic->arg[1]); }
-DOT2(add)
-
-
-/*
- *  addc:  Add carrying.
- *
- *  arg[0] = pointer to source register ra
- *  arg[1] = pointer to source register rb
- *  arg[2] = pointer to destination register rt
- */
-X(addc)
-{
-	/*  TODO: this only works in 32-bit mode  */
-	uint64_t tmp = (uint32_t)reg(ic->arg[0]);
-	uint64_t tmp2 = tmp;
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	tmp += (uint32_t)reg(ic->arg[1]);
-	if ((tmp >> 32) != (tmp2 >> 32))
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	reg(ic->arg[2]) = (uint32_t)tmp;
-}
-
-
-/*
- *  adde:  Add extended, etc.
- *
- *  arg[0] = pointer to source register ra
- *  arg[1] = pointer to source register rb
- *  arg[2] = pointer to destination register rt
- */
-X(adde)
-{
-	/*  TODO: this only works in 32-bit mode  */
-	int old_ca = cpu->cd.ppc.spr[SPR_XER] & PPC_XER_CA;
-	uint64_t tmp = (uint32_t)reg(ic->arg[0]);
-	uint64_t tmp2 = tmp;
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	tmp += (uint32_t)reg(ic->arg[1]);
-	if (old_ca)
-		tmp ++;
-	if ((tmp >> 32) != (tmp2 >> 32))
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	reg(ic->arg[2]) = (uint32_t)tmp;
-}
-DOT2(adde)
-X(addme)
-{
-	/*  TODO: this only works in 32-bit mode  */
-	int old_ca = cpu->cd.ppc.spr[SPR_XER] & PPC_XER_CA;
-	uint64_t tmp = (uint32_t)reg(ic->arg[0]);
-	uint64_t tmp2 = tmp;
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	if (old_ca)
-		tmp ++;
-	tmp += 0xffffffffULL;
-	if ((tmp >> 32) != (tmp2 >> 32))
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	reg(ic->arg[2]) = (uint32_t)tmp;
-}
-DOT2(addme)
-X(addze)
-{
-	/*  TODO: this only works in 32-bit mode  */
-	int old_ca = cpu->cd.ppc.spr[SPR_XER] & PPC_XER_CA;
-	uint64_t tmp = (uint32_t)reg(ic->arg[0]);
-	uint64_t tmp2 = tmp;
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	if (old_ca)
-		tmp ++;
-	if ((tmp >> 32) != (tmp2 >> 32))
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	reg(ic->arg[2]) = (uint32_t)tmp;
-}
-DOT2(addze)
-
-
-/*
- *  subf:  Subf, etc.
- *
- *  arg[0] = pointer to source register ra
- *  arg[1] = pointer to source register rb
- *  arg[2] = pointer to destination register rt
- */
-X(subf)
-{
-	reg(ic->arg[2]) = reg(ic->arg[1]) - reg(ic->arg[0]);
-}
-DOT2(subf)
-X(subfc)
-{
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	if (reg(ic->arg[1]) >= reg(ic->arg[0]))
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	reg(ic->arg[2]) = reg(ic->arg[1]) - reg(ic->arg[0]);
-}
-DOT2(subfc)
-X(subfe)
-{
-	int old_ca = (cpu->cd.ppc.spr[SPR_XER] & PPC_XER_CA)? 1 : 0;
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	if (reg(ic->arg[1]) == reg(ic->arg[0])) {
-		if (old_ca)
-			cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	} else if (reg(ic->arg[1]) >= reg(ic->arg[0]))
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-
-	/*
-	 *  TODO: The register value calculation should be correct,
-	 *  but the CA bit calculation above is probably not.
-	 */
-
-	reg(ic->arg[2]) = reg(ic->arg[1]) - reg(ic->arg[0]) - (old_ca? 0 : 1);
-}
-DOT2(subfe)
-X(subfme)
-{
-	int old_ca = cpu->cd.ppc.spr[SPR_XER] & PPC_XER_CA;
-	uint64_t tmp = (uint32_t)(~reg(ic->arg[0]));
-	tmp += 0xffffffffULL;
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	if (old_ca)
-		tmp ++;
-	if ((tmp >> 32) != 0)
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	reg(ic->arg[2]) = (uint32_t)tmp;
-}
-DOT2(subfme)
-X(subfze)
-{
-	int old_ca = cpu->cd.ppc.spr[SPR_XER] & PPC_XER_CA;
-	uint64_t tmp = (uint32_t)(~reg(ic->arg[0]));
-	uint64_t tmp2 = tmp;
-	cpu->cd.ppc.spr[SPR_XER] &= ~PPC_XER_CA;
-	if (old_ca)
-		tmp ++;
-	if ((tmp >> 32) != (tmp2 >> 32))
-		cpu->cd.ppc.spr[SPR_XER] |= PPC_XER_CA;
-	reg(ic->arg[2]) = (uint32_t)tmp;
-}
-DOT2(subfze)
-
-
-/*
- *  ori, xori etc.:
- *
- *  arg[0] = pointer to source uint64_t
- *  arg[1] = immediate value (uint32_t or larger)
- *  arg[2] = pointer to destination uint64_t
- */
-X(ori)  { reg(ic->arg[2]) = reg(ic->arg[0]) | (uint32_t)ic->arg[1]; }
-X(xori) { reg(ic->arg[2]) = reg(ic->arg[0]) ^ (uint32_t)ic->arg[1]; }
-
-
-#include "tmp_ppc_loadstore.cc"
-
-
-/*
- *  lfs, stfs: Load/Store Floating-point Single precision
- */
-X(lfs)
-{
-	/*  Sync. PC in case of an exception, and remember it:  */
-	uint64_t old_pc, low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call);
-	old_pc = cpu->pc = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) <<
-	    PPC_INSTR_ALIGNMENT_SHIFT)) + (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-	if (!(cpu->cd.ppc.msr & PPC_MSR_FP)) {
-		ppc_exception(cpu, PPC_EXCEPTION_FPU);
-		return;
-	}
-
-	/*  Perform a 32-bit load:  */
-#ifdef MODE32
-	ppc32_loadstore
-#else
-	ppc_loadstore
-#endif
-	    [2 + 4 + 8](cpu, ic);
-
-	if (old_pc == cpu->pc) {
-		/*  The load succeeded. Let's convert the value:  */
-		struct ieee_float_value val;
-		(*(uint64_t *)ic->arg[0]) &= 0xffffffff;
-		ieee_interpret_float_value(*(uint64_t *)ic->arg[0],
-		    &val, IEEE_FMT_S);
-		(*(uint64_t *)ic->arg[0]) =
-		    ieee_store_float_value(val.f, IEEE_FMT_D);
-	}
-}
-X(lfsx)
-{
-	/*  Sync. PC in case of an exception, and remember it:  */
-	uint64_t old_pc, low_pc = ((size_t)ic - (size_t)
-	    cpu->cd.ppc.cur_ic_page) / sizeof(struct ppc_instr_call);
-	old_pc = cpu->pc = (cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1) <<
-	    PPC_INSTR_ALIGNMENT_SHIFT)) + (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-	if (!(cpu->cd.ppc.msr & PPC_MSR_FP)) {
-		ppc_exception(cpu, PPC_EXCEPTION_FPU);
-		return;
-	}
-
-	/*  Perform a 32-bit load:  */
-#ifdef MODE32
-	ppc32_loadstore_indexed
-#else
-	ppc_loadstore_indexed
-#endif
-	    [2 + 4 + 8](cpu, ic);
-
-	if (old_pc == cpu->pc) {
-		/*  The load succeeded. Let's convert the value:  */
-		struct ieee_float_value val;
-		(*(uint64_t *)ic->arg[0]) &= 0xffffffff;
-		ieee_interpret_float_value(*(uint64_t *)ic->arg[0],
-		    &val, IEEE_FMT_S);
-		(*(uint64_t *)ic->arg[0]) =
-		    ieee_store_float_value(val.f, IEEE_FMT_D);
-	}
-}
-X(lfd)
-{
-	CHECK_FOR_FPU_EXCEPTION;
-
-	/*  Perform a 64-bit load:  */
-#ifdef MODE32
-	ppc32_loadstore
-#else
-	ppc_loadstore
-#endif
-	    [3 + 4 + 8](cpu, ic);
-}
-X(lfdx)
-{
-	CHECK_FOR_FPU_EXCEPTION;
-
-	/*  Perform a 64-bit load:  */
-#ifdef MODE32
-	ppc32_loadstore_indexed
-#else
-	ppc_loadstore_indexed
-#endif
-	    [3 + 4 + 8](cpu, ic);
-}
-X(stfs)
-{
-	uint64_t *old_arg0 = (uint64_t *) ic->arg[0];
-	struct ieee_float_value val;
-	uint64_t tmp_val;
-
-	CHECK_FOR_FPU_EXCEPTION;
-
-	ieee_interpret_float_value(*old_arg0, &val, IEEE_FMT_D);
-	tmp_val = ieee_store_float_value(val.f, IEEE_FMT_S);
-
-	ic->arg[0] = (size_t)&tmp_val;
-
-	/*  Perform a 32-bit store:  */
-#ifdef MODE32
-	ppc32_loadstore
-#else
-	ppc_loadstore
-#endif
-	    [2 + 4](cpu, ic);
-
-	ic->arg[0] = (size_t)old_arg0;
-}
-X(stfsx)
-{
-	uint64_t *old_arg0 = (uint64_t *)ic->arg[0];
-	struct ieee_float_value val;
-	uint64_t tmp_val;
-
-	CHECK_FOR_FPU_EXCEPTION;
-
-	ieee_interpret_float_value(*old_arg0, &val, IEEE_FMT_D);
-	tmp_val = ieee_store_float_value(val.f, IEEE_FMT_S);
-
-	ic->arg[0] = (size_t)&tmp_val;
-
-	/*  Perform a 32-bit store:  */
-#ifdef MODE32
-	ppc32_loadstore_indexed
-#else
-	ppc_loadstore_indexed
-#endif
-	    [2 + 4](cpu, ic);
-
-	ic->arg[0] = (size_t)old_arg0;
-}
-X(stfd)
-{
-	CHECK_FOR_FPU_EXCEPTION;
-
-	/*  Perform a 64-bit store:  */
-#ifdef MODE32
-	ppc32_loadstore
-#else
-	ppc_loadstore
-#endif
-	    [3 + 4](cpu, ic);
-}
-X(stfdx)
-{
-	CHECK_FOR_FPU_EXCEPTION;
-
-	/*  Perform a 64-bit store:  */
-#ifdef MODE32
-	ppc32_loadstore_indexed
-#else
-	ppc_loadstore_indexed
-#endif
-	    [3 + 4](cpu, ic);
-}
-
-
-/*
- *  lvx, stvx:  Vector (16-byte) load/store  (slow implementation)
- *
- *  arg[0] = v-register nr of rs
- *  arg[1] = pointer to ra
- *  arg[2] = pointer to rb
- */
-X(lvx)
-{
-	MODE_uint_t addr = reg(ic->arg[1]) + reg(ic->arg[2]);
-	uint8_t data[16];
-	uint64_t hi, lo;
-	int rs = ic->arg[0];
-
-	if (cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
-	    MEM_READ, CACHE_DATA) != MEMORY_ACCESS_OK) {
-		/*  exception  */
-		return;
-	}
-
-	hi = ((uint64_t)data[0] << 56) +
-	     ((uint64_t)data[1] << 48) +
-	     ((uint64_t)data[2] << 40) +
-	     ((uint64_t)data[3] << 32) +
-	     ((uint64_t)data[4] << 24) +
-	     ((uint64_t)data[5] << 16) +
-	     ((uint64_t)data[6] << 8) +
-	     ((uint64_t)data[7]);
-	lo = ((uint64_t)data[8] << 56) +
-	     ((uint64_t)data[9] << 48) +
-	     ((uint64_t)data[10] << 40) +
-	     ((uint64_t)data[11] << 32) +
-	     ((uint64_t)data[12] << 24) +
-	     ((uint64_t)data[13] << 16) +
-	     ((uint64_t)data[14] << 8) +
-	     ((uint64_t)data[15]);
-
-	cpu->cd.ppc.vr_hi[rs] = hi; cpu->cd.ppc.vr_lo[rs] = lo;
-}
-X(stvx)
-{
-	uint8_t data[16];
-	MODE_uint_t addr = reg(ic->arg[1]) + reg(ic->arg[2]);
-	int rs = ic->arg[0];
-	uint64_t hi = cpu->cd.ppc.vr_hi[rs], lo = cpu->cd.ppc.vr_lo[rs];
-
-	data[0] = hi >> 56;
-	data[1] = hi >> 48;
-	data[2] = hi >> 40;
-	data[3] = hi >> 32;
-	data[4] = hi >> 24;
-	data[5] = hi >> 16;
-	data[6] = hi >> 8;
-	data[7] = hi;
-	data[8] = lo >> 56;
-	data[9] = lo >> 48;
-	data[10] = lo >> 40;
-	data[11] = lo >> 32;
-	data[12] = lo >> 24;
-	data[13] = lo >> 16;
-	data[14] = lo >> 8;
-	data[15] = lo;
-
-	cpu->memory_rw(cpu, cpu->mem, addr, data,
-	    sizeof(data), MEM_WRITE, CACHE_DATA);
-}
-
-
-/*
- *  vxor:  Vector (16-byte) XOR
- *
- *  arg[0] = v-register nr of source 1
- *  arg[1] = v-register nr of source 2
- *  arg[2] = v-register nr of destination
- */
-X(vxor)
-{
-	cpu->cd.ppc.vr_hi[ic->arg[2]] =
-	    cpu->cd.ppc.vr_hi[ic->arg[0]] ^ cpu->cd.ppc.vr_hi[ic->arg[1]];
-	cpu->cd.ppc.vr_lo[ic->arg[2]] =
-	    cpu->cd.ppc.vr_lo[ic->arg[0]] ^ cpu->cd.ppc.vr_lo[ic->arg[1]];
-}
-
-
-/*
- *  tlbia:  TLB invalidate all
- */
-X(tlbia)
-{
-	fatal("[ tlbia ]\n");
-	cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
-}
-
-
-/*
- *  tlbie:  TLB invalidate
- */
-X(tlbie)
-{
-	/*  fatal("[ tlbie ]\n");  */
-	cpu->invalidate_translation_caches(cpu, reg(ic->arg[0]),
-	    INVALIDATE_VADDR);
-}
-
-
-/*
- *  sc: Syscall.
- */
-X(sc)
-{
-	/*  Synchronize the PC (pointing to _after_ this instruction)  */
-	cpu->pc = (cpu->pc & ~0xfff) + ic->arg[1];
-
-	ppc_exception(cpu, PPC_EXCEPTION_SC);
-
-	/*  This caused an update to the PC register, so there is no need
-	    to worry about the next instruction being an end_of_page.  */
-}
-
-
-/*
- *  openfirmware:
- */
-X(openfirmware)
-{
-	of_emul(cpu);
-	if (cpu->running == 0) {
-		cpu->n_translated_instrs --;
-		cpu->cd.ppc.next_ic = &nothing_call;
-		debugger_n_steps_left_before_interaction = 0;
-	}
-
-	cpu->pc = cpu->cd.ppc.spr[SPR_LR];
-	if (cpu->machine->show_trace_tree)
-		cpu_functioncall_trace_return(cpu);
-
-	quick_pc_to_pointers(cpu);
-}
-
-
-/*
- *  tlbsx_dot: TLB scan
- */
-X(tlbsx_dot)
-{
-	/*  TODO  */
-	cpu->cd.ppc.cr &= ~(0xf0000000);
-	cpu->cd.ppc.cr |= 0x20000000;
-	cpu->cd.ppc.cr |= ((cpu->cd.ppc.spr[SPR_XER] >> 3) & 0x10000000);
-}
-
-
-/*
- *  tlbli:
- */
-X(tlbli)
-{
-	fatal("tlbli\n");
-	cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
-}
-
-
-/*
- *  tlbld:
- */
-X(tlbld)
-{
-	/*  MODE_uint_t vaddr = reg(ic->arg[0]);
-	    MODE_uint_t paddr = cpu->cd.ppc.spr[SPR_RPA];  */
-
-	fatal("tlbld\n");
-	cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
-}
-
-
-/*****************************************************************************/
-
-
-X(end_of_page)
-{
-	/*  Update the PC:  (offset 0, but on the next page)  */
-	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (PPC_IC_ENTRIES_PER_PAGE << PPC_INSTR_ALIGNMENT_SHIFT);
-
-	/*  Find the new physical page and update the translation pointers:  */
-	quick_pc_to_pointers(cpu);
-
-	/*  end_of_page doesn't count as an executed instruction:  */
-	cpu->n_translated_instrs --;
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  ppc_instr_to_be_translated():
- *
- *  Translate an instruction word into a ppc_instr_call. ic is filled in with
- *  valid data for the translated instruction, or a "nothing" instruction if
- *  there was a translation failure. The newly translated instruction is then
- *  executed.
- */
-X(to_be_translated)
-{
-	uint64_t addr, low_pc, tmp_addr;
-	uint32_t iword, mask;
-	unsigned char *page;
-	unsigned char ib[4];
-	int main_opcode, rt, rs, ra, rb, rc, aa_bit, l_bit, lk_bit, spr, sh,
-	    xo, imm, load, size, update, zero, bf, bo, bi, bh, oe_bit, n64=0,
-	    bfa, fp, byterev, nb, mb, me;
-	void (*samepage_function)(struct cpu *, struct ppc_instr_call *);
-	void (*rc_f)(struct cpu *, struct ppc_instr_call *);
-
-	/*  Figure out the (virtual) address of the instruction:  */
-	low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page)
-	    / sizeof(struct ppc_instr_call);
-	addr = cpu->pc & ~((PPC_IC_ENTRIES_PER_PAGE-1)
-	    << PPC_INSTR_ALIGNMENT_SHIFT);
-	addr += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc = addr;
-	addr &= ~((1 << PPC_INSTR_ALIGNMENT_SHIFT) - 1);
-
-	/*  Read the instruction word from memory:  */
-#ifdef MODE32
-	page = cpu->cd.ppc.host_load[((uint32_t)addr) >> 12];
-#else
-	{
-		const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
-		const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
-		const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
-		uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
-		uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
-		uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
-		    DYNTRANS_L3N)) & mask3;
-		struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.ppc.l1_64[x1];
-		struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
-		page = l3->host_load[x3];
-	}
-#endif
-
-	if (page != NULL) {
-		/*  fatal("TRANSLATION HIT!\n");  */
-		memcpy(ib, page + (addr & 0xfff), sizeof(ib));
-	} else {
-		/*  fatal("TRANSLATION MISS!\n");  */
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
-		    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
-			fatal("PPC to_be_translated(): "
-			    "read failed: TODO\n");
-			exit(1);
-			/*  goto bad;  */
-		}
-	}
-
-	{
-		uint32_t *p = (uint32_t *) ib;
-		iword = *p;
-		iword = BE32_TO_HOST(iword);
-	}
-
-#define DYNTRANS_TO_BE_TRANSLATED_HEAD
-#include "cpu_dyntrans.cc"
-#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD
-
-
-	/*
-	 *  Translate the instruction:
-	 */
-
-	main_opcode = iword >> 26;
-
-	switch (main_opcode) {
-
-	case 0x04:
-		if (iword == 0x12739cc4) {
-			/*  vxor v19,v19,v19  */
-			ic->f = instr(vxor);
-			ic->arg[0] = 19;
-			ic->arg[1] = 19;
-			ic->arg[2] = 19;
-		} else {
-			if (!cpu->translation_readahead)
-				fatal("[ TODO: Unimplemented ALTIVEC, iword"
-				    " = 0x%08" PRIx32"x ]\n", iword);
-			goto bad;
-		}
-		break;
-
-	case PPC_HI6_MULLI:
-		rt = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		imm = (int16_t)(iword & 0xffff);
-		ic->f = instr(mulli);
-		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-		ic->arg[1] = (ssize_t)imm;
-		ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rt]);
-		break;
-
-	case PPC_HI6_SUBFIC:
-		rt = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		imm = (int16_t)(iword & 0xffff);
-		ic->f = instr(subfic);
-		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-		ic->arg[1] = (ssize_t)imm;
-		ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rt]);
-		break;
-
-	case PPC_HI6_CMPLI:
-	case PPC_HI6_CMPI:
-		bf = (iword >> 23) & 7;
-		l_bit = (iword >> 21) & 1;
-		ra = (iword >> 16) & 31;
-		if (main_opcode == PPC_HI6_CMPLI) {
-			imm = iword & 0xffff;
-			if (l_bit)
-				ic->f = instr(cmpldi);
-			else
-				ic->f = instr(cmplwi);
-		} else {
-			imm = (int16_t)(iword & 0xffff);
-			if (l_bit)
-				ic->f = instr(cmpdi);
-			else {
-				if (bf == 0)
-					ic->f = instr(cmpwi_cr0);
-				else
-					ic->f = instr(cmpwi);
-			}
-		}
-		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-		ic->arg[1] = (ssize_t)imm;
-		ic->arg[2] = 28 - 4 * bf;
-		break;
-
-	case PPC_HI6_ADDIC:
-	case PPC_HI6_ADDIC_DOT:
-		if (cpu->cd.ppc.bits == 64) {
-			if (!cpu->translation_readahead)
-				fatal("addic for 64-bit: TODO\n");
-			goto bad;
-		}
-		rt = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		imm = (int16_t)(iword & 0xffff);
-		if (main_opcode == PPC_HI6_ADDIC)
-			ic->f = instr(addic);
-		else
-			ic->f = instr(addic_dot);
-		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-		ic->arg[1] = imm;
-		ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rt]);
-		break;
-
-	case PPC_HI6_ADDI:
-	case PPC_HI6_ADDIS:
-		rt = (iword >> 21) & 31; ra = (iword >> 16) & 31;
-		ic->f = instr(addi);
-		if (ra == 0)
-			ic->f = instr(li);
-		else
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-		ic->arg[1] = (int16_t)(iword & 0xffff);
-		if (main_opcode == PPC_HI6_ADDIS)
-			ic->arg[1] <<= 16;
-		if (ra == 0 && ic->arg[1] == 0)
-			ic->f = instr(li_0);
-		ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rt]);
-		break;
-
-	case PPC_HI6_ANDI_DOT:
-	case PPC_HI6_ANDIS_DOT:
-		rs = (iword >> 21) & 31; ra = (iword >> 16) & 31;
-		ic->f = instr(andi_dot);
-		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
-		ic->arg[1] = iword & 0xffff;
-		if (main_opcode == PPC_HI6_ANDIS_DOT)
-			ic->arg[1] <<= 16;
-		ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-		break;
-
-	case PPC_HI6_ORI:
-	case PPC_HI6_ORIS:
-	case PPC_HI6_XORI:
-	case PPC_HI6_XORIS:
-		rs = (iword >> 21) & 31; ra = (iword >> 16) & 31;
-		if (main_opcode == PPC_HI6_ORI ||
-		    main_opcode == PPC_HI6_ORIS)
-			ic->f = instr(ori);
-		else
-			ic->f = instr(xori);
-		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
-		ic->arg[1] = iword & 0xffff;
-		if (main_opcode == PPC_HI6_ORIS ||
-		    main_opcode == PPC_HI6_XORIS)
-			ic->arg[1] <<= 16;
-		ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-		break;
-
-	case PPC_HI6_LBZ:
-	case PPC_HI6_LBZU:
-	case PPC_HI6_LHZ:
-	case PPC_HI6_LHZU:
-	case PPC_HI6_LHA:
-	case PPC_HI6_LHAU:
-	case PPC_HI6_LWZ:
-	case PPC_HI6_LWZU:
-	case PPC_HI6_LD:
-	case PPC_HI6_LFD:
-	case PPC_HI6_LFS:
-	case PPC_HI6_STB:
-	case PPC_HI6_STBU:
-	case PPC_HI6_STH:
-	case PPC_HI6_STHU:
-	case PPC_HI6_STW:
-	case PPC_HI6_STWU:
-	case PPC_HI6_STD:
-	case PPC_HI6_STFD:
-	case PPC_HI6_STFS:
-		rs = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		imm = (int16_t)iword;
-		load = 0; zero = 1; size = 0; update = 0; fp = 0;
-		ic->f = NULL;
-		switch (main_opcode) {
-		case PPC_HI6_LBZ:  load=1; break;
-		case PPC_HI6_LBZU: load=1; update=1; break;
-		case PPC_HI6_LHA:  load=1; size=1; zero=0; break;
-		case PPC_HI6_LHAU: load=1; size=1; zero=0; update=1; break;
-		case PPC_HI6_LHZ:  load=1; size=1; break;
-		case PPC_HI6_LHZU: load=1; size=1; update=1; break;
-		case PPC_HI6_LWZ:  load=1; size=2; break;
-		case PPC_HI6_LWZU: load=1; size=2; update=1; break;
-		case PPC_HI6_LD:   load=1; size=3; break;
-		case PPC_HI6_LFD:  load=1; size=3; fp=1;ic->f=instr(lfd);break;
-		case PPC_HI6_LFS:  load=1; size=2; fp=1;ic->f=instr(lfs);break;
-		case PPC_HI6_STB:  break;
-		case PPC_HI6_STBU: update=1; break;
-		case PPC_HI6_STH:  size=1; break;
-		case PPC_HI6_STHU: size=1; update=1; break;
-		case PPC_HI6_STW:  size=2; break;
-		case PPC_HI6_STWU: size=2; update=1; break;
-		case PPC_HI6_STD:  size=3; break;
-		case PPC_HI6_STFD: size=3; fp=1; ic->f = instr(stfd); break;
-		case PPC_HI6_STFS: size=2; fp=1; ic->f = instr(stfs); break;
-		}
-		if (ic->f == NULL) {
-			ic->f =
-#ifdef MODE32
-			    ppc32_loadstore
-#else
-			    ppc_loadstore
-#endif
-			    [size + 4*zero + 8*load + (imm==0? 16 : 0)
-			    + 32*update];
-		}
-		if (ra == 0 && update) {
-			if (!cpu->translation_readahead)
-				fatal("TODO: ra=0 && update?\n");
-			goto bad;
-		}
-		if (fp)
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rs]);
-		else
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
-		if (ra == 0)
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.zero);
-		else
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-		ic->arg[2] = (ssize_t)imm;
-		break;
-
-	case PPC_HI6_BC:
-		aa_bit = (iword >> 1) & 1;
-		lk_bit = iword & 1;
-		bo = (iword >> 21) & 31;
-		bi = (iword >> 16) & 31;
-		tmp_addr = (int64_t)(int16_t)(iword & 0xfffc);
-		if (aa_bit) {
-			if (!cpu->translation_readahead)
-				fatal("aa_bit: NOT YET\n");
-			goto bad;
-		}
-		if (lk_bit) {
-			ic->f = instr(bcl);
-			samepage_function = instr(bcl_samepage);
-		} else {
-			ic->f = instr(bc);
-			if ((bo & 0x14) == 0x04) {
-				samepage_function = bo & 8?
-				    instr(bc_samepage_simple1) :
-				    instr(bc_samepage_simple0);
-			} else
-				samepage_function = instr(bc_samepage);
-		}
-		ic->arg[0] = (ssize_t)(tmp_addr + (addr & 0xffc));
-		ic->arg[1] = bo;
-		ic->arg[2] = 31-bi;
-		/*  Branches are calculated as cur PC + offset.  */
-		/*  Special case: branch within the same page:  */
-		{
-			uint64_t mask_within_page =
-			    ((PPC_IC_ENTRIES_PER_PAGE-1) << 2) | 3;
-			uint64_t old_pc = addr;
-			uint64_t new_pc = old_pc + (int32_t)tmp_addr;
-			if ((old_pc & ~mask_within_page) ==
-			    (new_pc & ~mask_within_page)) {
-				ic->f = samepage_function;
-				ic->arg[0] = (size_t) (
-				    cpu->cd.ppc.cur_ic_page +
-				    ((new_pc & mask_within_page) >> 2));
-			}
-		}
-		break;
-
-	case PPC_HI6_SC:
-		ic->arg[0] = (iword >> 5) & 0x7f;
-		ic->arg[1] = (addr & 0xfff) + 4;
-		if (iword == 0x44ee0002) {
-			/*  Special case/magic hack for OpenFirmware emul:  */
-			ic->f = instr(openfirmware);
-		} else
-			ic->f = instr(sc);
-		break;
-
-	case PPC_HI6_B:
-		aa_bit = (iword & 2) >> 1;
-		lk_bit = iword & 1;
-		tmp_addr = (int64_t)(int32_t)((iword & 0x03fffffc) << 6);
-		tmp_addr = (int64_t)tmp_addr >> 6;
-		if (lk_bit) {
-			if (cpu->machine->show_trace_tree) {
-				ic->f = instr(bl_trace);
-				samepage_function = instr(bl_samepage_trace);
-			} else {
-				ic->f = instr(bl);
-				samepage_function = instr(bl_samepage);
-			}
-		} else {
-			ic->f = instr(b);
-			samepage_function = instr(b_samepage);
-		}
-		ic->arg[0] = (ssize_t)(tmp_addr + (addr & 0xffc));
-		ic->arg[1] = (addr & 0xffc) + 4;
-		/*  Branches are calculated as cur PC + offset.  */
-		/*  Special case: branch within the same page:  */
-		{
-			uint64_t mask_within_page =
-			    ((PPC_IC_ENTRIES_PER_PAGE-1) << 2) | 3;
-			uint64_t old_pc = addr;
-			uint64_t new_pc = old_pc + (int32_t)tmp_addr;
-			if ((old_pc & ~mask_within_page) ==
-			    (new_pc & ~mask_within_page)) {
-				ic->f = samepage_function;
-				ic->arg[0] = (size_t) (
-				    cpu->cd.ppc.cur_ic_page +
-				    ((new_pc & mask_within_page) >> 2));
-			}
-		}
-		if (aa_bit) {
-			if (lk_bit) {
-				if (cpu->machine->show_trace_tree) {
-					ic->f = instr(bla_trace);
-				} else {
-					ic->f = instr(bla);
-				}
-			} else {
-				ic->f = instr(ba);
-			}
-			ic->arg[0] = (ssize_t)tmp_addr;
-		}
-		break;
-
-	case PPC_HI6_19:
-		xo = (iword >> 1) & 1023;
-		switch (xo) {
-
-		case PPC_19_BCLR:
-		case PPC_19_BCCTR:
-			bo = (iword >> 21) & 31;
-			bi = (iword >> 16) & 31;
-			bh = (iword >> 11) & 3;
-			lk_bit = iword & 1;
-			if (xo == PPC_19_BCLR) {
-				if (lk_bit)
-					ic->f = instr(bclr_l);
-				else {
-					ic->f = instr(bclr);
-					if (!cpu->machine->show_trace_tree &&
-					    (bo & 0x14) == 0x14)
-						ic->f = instr(bclr_20);
-				}
-			} else {
-				if (!(bo & 4)) {
-					if (!cpu->translation_readahead)
-						fatal("TODO: bclr/bcctr "
-						    "bo bit 2 clear!\n");
-					goto bad;
-				}
-				if (lk_bit)
-					ic->f = instr(bcctr_l);
-				else
-					ic->f = instr(bcctr);
-			}
-			ic->arg[0] = bo;
-			ic->arg[1] = 31 - bi;
-			ic->arg[2] = bh;
-			break;
-
-		case PPC_19_ISYNC:
-			/*  TODO  */
-			ic->f = instr(nop);
-			break;
-
-		case PPC_19_RFI:
-			ic->f = instr(rfi);
-			break;
-
-		case PPC_19_RFID:
-			ic->f = instr(rfid);
-			break;
-
-		case PPC_19_MCRF:
-			bf = (iword >> 23) & 7;
-			bfa = (iword >> 18) & 7;
-			ic->arg[0] = 28 - 4*bf;
-			ic->arg[1] = 28 - 4*bfa;
-			ic->f = instr(mcrf);
-			break;
-
-		case PPC_19_CRAND:
-		case PPC_19_CRANDC:
-		case PPC_19_CREQV:
-		case PPC_19_CROR:
-		case PPC_19_CRORC:
-		case PPC_19_CRNOR:
-		case PPC_19_CRXOR:
-			switch (xo) {
-			case PPC_19_CRAND:  ic->f = instr(crand); break;
-			case PPC_19_CRANDC: ic->f = instr(crandc); break;
-			case PPC_19_CREQV:  ic->f = instr(creqv); break;
-			case PPC_19_CROR:   ic->f = instr(cror); break;
-			case PPC_19_CRORC:  ic->f = instr(crorc); break;
-			case PPC_19_CRNOR:  ic->f = instr(crnor); break;
-			case PPC_19_CRXOR:  ic->f = instr(crxor); break;
-			}
-			ic->arg[0] = iword;
-			break;
-
-		default:goto bad;
-		}
-		break;
-
-	case PPC_HI6_RLWNM:
-	case PPC_HI6_RLWINM:
-		ra = (iword >> 16) & 31;
-		mb = (iword >> 6) & 31;
-		me = (iword >> 1) & 31;   
-		rc = iword & 1;
-		mask = 0;
-		for (;;) {
-			mask |= ((uint32_t)0x80000000 >> mb);
-			if (mb == me)
-				break;
-			mb ++; mb &= 31;
-		}
-		switch (main_opcode) {
-		case PPC_HI6_RLWNM:
-			ic->f = rc? instr(rlwnm_dot) : instr(rlwnm); break;
-		case PPC_HI6_RLWINM:
-			ic->f = rc? instr(rlwinm_dot) : instr(rlwinm); break;
-		}
-		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-		ic->arg[1] = mask;
-		ic->arg[2] = (uint32_t)iword;
-		break;
-
-	case PPC_HI6_RLWIMI:
-		rs = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		ic->f = instr(rlwimi);
-		ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
-		ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-		ic->arg[2] = (uint32_t)iword;
-		break;
-
-	case PPC_HI6_LMW:
-	case PPC_HI6_STMW:
-		/*  NOTE: Loads use rt, not rs.  */
-		rs = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		ic->arg[0] = rs;
-		if (ra == 0)
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.zero);
-		else
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-		ic->arg[2] = (int32_t)(int16_t)iword;
-		switch (main_opcode) {
-		case PPC_HI6_LMW:
-			ic->f = instr(lmw);
-			break;
-		case PPC_HI6_STMW:
-			ic->f = instr(stmw);
-			break;
-		}
-		break;
-
-	case PPC_HI6_30:
-		xo = (iword >> 2) & 7;
-		switch (xo) {
-
-		case PPC_30_RLDICL:
-		case PPC_30_RLDICR:
-		case PPC_30_RLDIMI:
-			switch (xo) {
-			case PPC_30_RLDICL: ic->f = instr(rldicl); break;
-			case PPC_30_RLDICR: ic->f = instr(rldicr); break;
-			case PPC_30_RLDIMI: ic->f = instr(rldimi); break;
-			}
-			ic->arg[0] = iword;
-			if (cpu->cd.ppc.bits == 32) {
-				if (!cpu->translation_readahead)
-					fatal("TODO: rld* in 32-bit mode?\n");
-				goto bad;
-			}
-			break;
-
-		default:goto bad;
-		}
-		break;
-
-	case PPC_HI6_31:
-		xo = (iword >> 1) & 1023;
-		switch (xo) {
-
-		case PPC_31_CMPL:
-		case PPC_31_CMP:
-			bf = (iword >> 23) & 7;
-			l_bit = (iword >> 21) & 1;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			if (xo == PPC_31_CMPL) {
-				if (l_bit)
-					ic->f = instr(cmpld);
-				else
-					ic->f = instr(cmplw);
-			} else {
-				if (l_bit)
-					ic->f = instr(cmpd);
-				else {
-					if (bf == 0)
-						ic->f = instr(cmpw_cr0);
-					else
-						ic->f = instr(cmpw);
-				}
-			}
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rb]);
-			ic->arg[2] = 28 - 4*bf;
-			break;
-
-		case PPC_31_CNTLZW:
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rc = iword & 1;
-			if (rc) {
-				if (!cpu->translation_readahead)
-					fatal("TODO: rc\n");
-				goto bad;
-			}
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-			ic->f = instr(cntlzw);
-			break;
-
-		case PPC_31_MFSPR:
-			rt = (iword >> 21) & 31;
-			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
-			debug_spr_usage(cpu->pc, spr);
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rt]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.spr[spr]);
-			switch (spr) {
-			// Reuse SPR_TB* for TBR_TB*:
-			case TBR_TBL: ic->f = instr(mftb); break;
-			case TBR_TBU: ic->f = instr(mftbu); break;
-			case SPR_PMC1:	ic->f = instr(mfspr_pmc1); break;
-			default:	ic->f = instr(mfspr);
-			}
-			break;
-
-		case PPC_31_MTSPR:
-			rs = (iword >> 21) & 31;
-			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
-			debug_spr_usage(cpu->pc, spr);
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.spr[spr]);
-			switch (spr) {
-			case SPR_LR:
-				ic->f = instr(mtlr);
-				break;
-			case SPR_CTR:
-				ic->f = instr(mtctr);
-				break;
-			case SPR_SPRG2:
-				ic->f = instr(mtspr_sprg2);
-				break;
-			default:ic->f = instr(mtspr);
-			}
-			break;
-
-		case PPC_31_MFCR:
-			rt = (iword >> 21) & 31;
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rt]);
-			ic->f = instr(mfcr);
-			break;
-
-		case PPC_31_MFMSR:
-			rt = (iword >> 21) & 31;
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rt]);
-			ic->f = instr(mfmsr);
-			break;
-
-		case PPC_31_MTMSR:
-		case PPC_31_MTMSRD:
-			rs = (iword >> 21) & 31;
-			l_bit = (iword >> 16) & 1;
-			if (l_bit) {
-				if (!cpu->translation_readahead)
-					fatal("TODO: mtmsr l-bit\n");
-				goto bad;
-			}
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
-			ic->arg[1] = (addr & 0xfff) + 4;
-			ic->arg[2] = xo == PPC_31_MTMSRD;
-			ic->f = instr(mtmsr);
-			break;
-
-		case PPC_31_MTCRF:
-			rs = (iword >> 21) & 31;
-			{
-				int i, fxm = (iword >> 12) & 255;
-				uint32_t tmp = 0;
-				for (i=0; i<8; i++, fxm <<= 1) {
-					tmp <<= 4;
-					if (fxm & 128)
-						tmp |= 0xf;
-				}
-				ic->arg[1] = (uint32_t)tmp;
-			}
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
-			ic->f = instr(mtcrf);
-			break;
-
-		case PPC_31_MFSRIN:
-		case PPC_31_MTSRIN:
-			rt = (iword >> 21) & 31;
-			rb = (iword >> 11) & 31;
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rb]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rt]);
-			switch (xo) {
-			case PPC_31_MFSRIN: ic->f = instr(mfsrin); break;
-			case PPC_31_MTSRIN: ic->f = instr(mtsrin); break;
-			}
-			if (cpu->cd.ppc.bits == 64) {
-				if (!cpu->translation_readahead)
-					fatal("Not yet for 64-bit mode\n");
-				goto bad;
-			}
-			break;
-
-		case PPC_31_MFSR:
-		case PPC_31_MTSR:
-			rt = (iword >> 21) & 31;
-			ic->arg[0] = (iword >> 16) & 15;
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rt]);
-			switch (xo) {
-			case PPC_31_MFSR:   ic->f = instr(mfsr); break;
-			case PPC_31_MTSR:   ic->f = instr(mtsr); break;
-			}
-			if (cpu->cd.ppc.bits == 64) {
-				if (!cpu->translation_readahead)
-					fatal("Not yet for 64-bit mode\n");
-				goto bad;
-			}
-			break;
-
-		case PPC_31_SRAWI:
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			sh = (iword >> 11) & 31;
-			rc = iword & 1;
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-			ic->arg[2] = sh;
-			if (rc)
-				ic->f = instr(srawi_dot);
-			else
-				ic->f = instr(srawi);
-			break;
-
-		case PPC_31_SYNC:
-		case PPC_31_DSSALL:
-		case PPC_31_EIEIO:
-		case PPC_31_DCBST:
-		case PPC_31_DCBTST:
-		case PPC_31_DCBF:
-		case PPC_31_DCBT:
-		case PPC_31_ICBI:
-			ic->f = instr(nop);
-			break;
-
-		case PPC_31_DCBZ:
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			if (ra == 0)
-				ic->arg[0] = (size_t)(&cpu->cd.ppc.zero);
-			else
-				ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rb]);
-			ic->arg[2] = addr & 0xfff;
-			ic->f = instr(dcbz);
-			break;
-
-		case PPC_31_TLBIA:
-			ic->f = instr(tlbia);
-			break;
-
-		case PPC_31_TLBSYNC:
-			/*  According to IBM, "Ensures that a tlbie and
-			    tlbia instruction executed by one processor has
-			    completed on all other processors.", which in
-			    GXemul means a nop :-)  */
-			ic->f = instr(nop);
-			break;
-
-		case PPC_31_TLBIE:
-			/*  TODO: POWER also uses ra?  */
-			rb = (iword >> 11) & 31;
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rb]);
-			ic->f = instr(tlbie);
-			break;
-
-		case PPC_31_TLBLD:	/*  takes an arg  */
-			rb = (iword >> 11) & 31;
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rb]);
-			ic->f = instr(tlbld);
-			break;
-
-		case PPC_31_TLBLI:	/*  takes an arg  */
-			rb = (iword >> 11) & 31;
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rb]);
-			ic->f = instr(tlbli);
-			break;
-
-		case PPC_31_TLBSX_DOT:
-			/*  TODO  */
-			ic->f = instr(tlbsx_dot);
-			break;
-
-		case PPC_31_MFTB:
-			rt = (iword >> 21) & 31;
-			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rt]);
-			switch (spr) {
-			case 268: ic->f = instr(mftb); break;
-			case 269: ic->f = instr(mftbu); break;
-			default:if (!cpu->translation_readahead)
-					fatal("mftb spr=%i?\n", spr);
-				goto bad;
-			}
-			break;
-
-		case PPC_31_NEG:
-			rt = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rc = iword & 1;
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rt]);
-			if (rc)
-				ic->f = instr(neg_dot);
-			else
-				ic->f = instr(neg);
-			break;
-
-		case PPC_31_LWARX:
-		case PPC_31_LDARX:
-		case PPC_31_STWCX_DOT:
-		case PPC_31_STDCX_DOT:
-			ic->arg[0] = iword;
-			ic->f = instr(llsc);
-			break;
-
-		case PPC_31_LSWI:
-		case PPC_31_STSWI:
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			nb = (iword >> 11) & 31;
-			ic->arg[0] = rs;
-			if (ra == 0)
-				ic->arg[1] = (size_t)(&cpu->cd.ppc.zero);
-			else
-				ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-			ic->arg[2] = nb == 0? 32 : nb;
-			switch (xo) {
-			case PPC_31_LSWI:  ic->f = instr(lswi); break;
-			case PPC_31_STSWI: ic->f = instr(stswi); break;
-			}
-			break;
-
-		case PPC_31_WRTEEI:
-			ic->arg[0] = iword & 0x8000;
-			ic->f = instr(wrteei);
-			break;
-
-		case 0x1c3:
-			fatal("[ mtdcr: TODO ]\n");
-			ic->f = instr(nop);
-			break;
-
-		case PPC_31_LBZX:
-		case PPC_31_LBZUX:
-		case PPC_31_LHAX:
-		case PPC_31_LHAUX:
-		case PPC_31_LHZX:
-		case PPC_31_LHZUX:
-		case PPC_31_LWZX:
-		case PPC_31_LWZUX:
-		case PPC_31_LHBRX:
-		case PPC_31_LWBRX:
-		case PPC_31_LFDX:
-		case PPC_31_LFSX:
-		case PPC_31_STBX:
-		case PPC_31_STBUX:
-		case PPC_31_STHX:
-		case PPC_31_STHUX:
-		case PPC_31_STWX:
-		case PPC_31_STWUX:
-		case PPC_31_STDX:
-		case PPC_31_STDUX:
-		case PPC_31_STHBRX:
-		case PPC_31_STWBRX:
-		case PPC_31_STFDX:
-		case PPC_31_STFSX:
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			if (ra == 0)
-				ic->arg[1] = (size_t)(&cpu->cd.ppc.zero);
-			else
-				ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-			ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rb]);
-			load = 0; zero = 1; size = 0; update = 0;
-			byterev = 0; fp = 0;
-			ic->f = NULL;
-			switch (xo) {
-			case PPC_31_LBZX:  load = 1; break;
-			case PPC_31_LBZUX: load=update=1; break;
-			case PPC_31_LHAX:  size=1; load=1; zero=0; break;
-			case PPC_31_LHAUX: size=1; load=update=1; zero=0; break;
-			case PPC_31_LHZX:  size=1; load=1; break;
-			case PPC_31_LHZUX: size=1; load=update = 1; break;
-			case PPC_31_LWZX:  size=2; load=1; break;
-			case PPC_31_LWZUX: size=2; load=update = 1; break;
-			case PPC_31_LHBRX: size=1; load=1; byterev=1;
-					   ic->f = instr(lhbrx); break;
-			case PPC_31_LWBRX: size=2; load=1; byterev=1;
-					   ic->f = instr(lwbrx); break;
-			case PPC_31_LFDX:  size=3; load=1; fp=1;
-					   ic->f = instr(lfdx); break;
-			case PPC_31_LFSX:  size=2; load=1; fp=1;
-					   ic->f = instr(lfsx); break;
-			case PPC_31_STBX:  break;
-			case PPC_31_STBUX: update = 1; break;
-			case PPC_31_STHX:  size=1; break;
-			case PPC_31_STHUX: size=1; update = 1; break;
-			case PPC_31_STWX:  size=2; break;
-			case PPC_31_STWUX: size=2; update = 1; break;
-			case PPC_31_STDX:  size=3; break;
-			case PPC_31_STDUX: size=3; update = 1; break;
-			case PPC_31_STHBRX:size=1; byterev = 1;
-					   ic->f = instr(sthbrx); break;
-			case PPC_31_STWBRX:size=2; byterev = 1;
-					   ic->f = instr(stwbrx); break;
-			case PPC_31_STFDX: size=3; fp=1;
-					   ic->f = instr(stfdx); break;
-			case PPC_31_STFSX: size=2; fp=1;
-					   ic->f = instr(stfsx); break;
-			}
-			if (fp)
-				ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rs]);
-			else
-				ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
-			if (!byterev && ic->f == NULL) {
-				ic->f =
-#ifdef MODE32
-				    ppc32_loadstore_indexed
-#else
-				    ppc_loadstore_indexed
-#endif
-				    [size + 4*zero + 8*load + 16*update];
-			}
-			if (ra == 0 && update) {
-				if (!cpu->translation_readahead)
-					fatal("TODO: ra=0 && update?\n");
-				goto bad;
-			}
-			break;
-
-		case PPC_31_EXTSB:
-		case PPC_31_EXTSH:
-		case PPC_31_EXTSW:
-		case PPC_31_SLW:
-		case PPC_31_SLD:
-		case PPC_31_SRAW:
-		case PPC_31_SRW:
-		case PPC_31_AND:
-		case PPC_31_NAND:
-		case PPC_31_ANDC:
-		case PPC_31_NOR:
-		case PPC_31_OR:
-		case PPC_31_ORC:
-		case PPC_31_XOR:
-		case PPC_31_EQV:
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			rc = iword & 1;
-			rc_f = NULL;
-			switch (xo) {
-			case PPC_31_EXTSB:ic->f = instr(extsb);
-					  rc_f  = instr(extsb_dot); break;
-			case PPC_31_EXTSH:ic->f = instr(extsh);
-					  rc_f  = instr(extsh_dot); break;
-			case PPC_31_EXTSW:ic->f = instr(extsw);
-					  rc_f  = instr(extsw_dot); break;
-			case PPC_31_SLW:  ic->f = instr(slw);
-					  rc_f  = instr(slw_dot); break;
-			case PPC_31_SLD:  ic->f = instr(sld);
-					  rc_f  = instr(sld_dot); break;
-			case PPC_31_SRAW: ic->f = instr(sraw);
-					  rc_f  = instr(sraw_dot); break;
-			case PPC_31_SRW:  ic->f = instr(srw);
-					  rc_f  = instr(srw_dot); break;
-			case PPC_31_AND:  ic->f = instr(and);
-					  rc_f  = instr(and_dot); break;
-			case PPC_31_NAND: ic->f = instr(nand);
-					  rc_f  = instr(nand_dot); break;
-			case PPC_31_ANDC: ic->f = instr(andc);
-					  rc_f  = instr(andc_dot); break;
-			case PPC_31_NOR:  ic->f = instr(nor);
-					  rc_f  = instr(nor_dot); break;
-			case PPC_31_OR:   ic->f = rs == rb? instr(mr)
-						: instr(or);
-					  rc_f  = instr(or_dot); break;
-			case PPC_31_ORC:  ic->f = instr(orc);
-					  rc_f  = instr(orc_dot); break;
-			case PPC_31_XOR:  ic->f = instr(xor);
-					  rc_f  = instr(xor_dot); break;
-			case PPC_31_EQV:  ic->f = instr(eqv);
-					  rc_f  = instr(eqv_dot); break;
-			}
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[rs]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rb]);
-			ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-			if (rc)
-				ic->f = rc_f;
-			break;
-
-		case PPC_31_MULLW:
-		case PPC_31_MULHW:
-		case PPC_31_MULHWU:
-		case PPC_31_DIVW:
-		case PPC_31_DIVWU:
-		case PPC_31_ADD:
-		case PPC_31_ADDC:
-		case PPC_31_ADDE:
-		case PPC_31_ADDME:
-		case PPC_31_ADDZE:
-		case PPC_31_SUBF:
-		case PPC_31_SUBFC:
-		case PPC_31_SUBFE:
-		case PPC_31_SUBFME:
-		case PPC_31_SUBFZE:
-			rt = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			oe_bit = (iword >> 10) & 1;
-			rc = iword & 1;
-			if (oe_bit) {
-				if (!cpu->translation_readahead)
-					fatal("oe_bit not yet implemented\n");
-				goto bad;
-			}
-			switch (xo) {
-			case PPC_31_MULLW:  ic->f = instr(mullw); break;
-			case PPC_31_MULHW:  ic->f = instr(mulhw); break;
-			case PPC_31_MULHWU: ic->f = instr(mulhwu); break;
-			case PPC_31_DIVW:   ic->f = instr(divw); n64=1; break;
-			case PPC_31_DIVWU:  ic->f = instr(divwu); n64=1; break;
-			case PPC_31_ADD:    ic->f = instr(add); break;
-			case PPC_31_ADDC:   ic->f = instr(addc); n64=1; break;
-			case PPC_31_ADDE:   ic->f = instr(adde); n64=1; break;
-			case PPC_31_ADDME:  ic->f = instr(addme); n64=1; break;
-			case PPC_31_ADDZE:  ic->f = instr(addze); n64=1; break;
-			case PPC_31_SUBF:   ic->f = instr(subf); break;
-			case PPC_31_SUBFC:  ic->f = instr(subfc); break;
-			case PPC_31_SUBFE:  ic->f = instr(subfe); n64=1; break;
-			case PPC_31_SUBFME: ic->f = instr(subfme); n64=1; break;
-			case PPC_31_SUBFZE: ic->f = instr(subfze); n64=1;break;
-			}
-			if (rc) {
-				switch (xo) {
-				case PPC_31_ADD:
-					ic->f = instr(add_dot); break;
-				case PPC_31_ADDE:
-					ic->f = instr(adde_dot); break;
-				case PPC_31_ADDME:
-					ic->f = instr(addme_dot); break;
-				case PPC_31_ADDZE:
-					ic->f = instr(addze_dot); break;
-				case PPC_31_DIVW:
-					ic->f = instr(divw_dot); break;
-				case PPC_31_DIVWU:
-					ic->f = instr(divwu_dot); break;
-				case PPC_31_MULLW:
-					ic->f = instr(mullw_dot); break;
-				case PPC_31_MULHW:
-					ic->f = instr(mulhw_dot); break;
-				case PPC_31_MULHWU:
-					ic->f = instr(mulhwu_dot); break;
-				case PPC_31_SUBF:
-					ic->f = instr(subf_dot); break;
-				case PPC_31_SUBFC:
-					ic->f = instr(subfc_dot); break;
-				case PPC_31_SUBFE:
-					ic->f = instr(subfe_dot); break;
-				case PPC_31_SUBFME:
-					ic->f = instr(subfme_dot); break;
-				case PPC_31_SUBFZE:
-					ic->f = instr(subfze_dot); break;
-				default:if (!cpu->translation_readahead)
-						fatal("RC bit not yet "
-						    "implemented\n");
-					goto bad;
-				}
-			}
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[rb]);
-			ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rt]);
-			if (cpu->cd.ppc.bits == 64 && n64) {
-				if (!cpu->translation_readahead)
-					fatal("Not yet for 64-bit mode\n");
-				goto bad;
-			}
-			break;
-
-		case PPC_31_LVX:
-		case PPC_31_LVXL:
-		case PPC_31_STVX:
-		case PPC_31_STVXL:
-			load = 0;
-			switch (xo) {
-			case PPC_31_LVX:
-			case PPC_31_LVXL:
-				load = 1; break;
-			}
-			rs = (iword >> 21) & 31;
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			ic->arg[0] = rs;
-			if (ra == 0)
-				ic->arg[1] = (size_t)(&cpu->cd.ppc.zero);
-			else
-				ic->arg[1] = (size_t)(&cpu->cd.ppc.gpr[ra]);
-			ic->arg[2] = (size_t)(&cpu->cd.ppc.gpr[rb]);
-			ic->f = load? instr(lvx) : instr(stvx);
-			break;
-
-		default:goto bad;
-		}
-		break;
-
-	case PPC_HI6_59:
-		xo = (iword >>  1) & 1023;
-		rt = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		rb = (iword >> 11) & 31;
-		rs = (iword >>  6) & 31;	/*  actually frc  */
-		rc = iword & 1;
-
-		if (rc) {
-			if (!cpu->translation_readahead)
-				fatal("Floating point (59) "
-				    "with rc bit! TODO\n");
-			goto bad;
-		}
-
-		/*  NOTE: Some floating-point instructions are selected
-		    using only the lowest 5 bits, not all 10!  */
-		switch (xo & 31) {
-		case PPC_59_FDIVS:
-		case PPC_59_FSUBS:
-		case PPC_59_FADDS:
-			switch (xo & 31) {
-			case PPC_59_FDIVS: ic->f = instr(fdivs); break;
-			case PPC_59_FSUBS: ic->f = instr(fsubs); break;
-			case PPC_59_FADDS: ic->f = instr(fadds); break;
-			}
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[ra]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[rb]);
-			ic->arg[2] = (size_t)(&cpu->cd.ppc.fpr[rt]);
-			break;
-		case PPC_59_FMULS:
-			ic->f = instr(fmuls);
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rt]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[ra]);
-			ic->arg[2] = (size_t)(&cpu->cd.ppc.fpr[rs]); /* frc */
-			break;
-		default:/*  Use all 10 bits of xo:  */
-			switch (xo) {
-			default:goto bad;
-			}
-		}
-		break;
-
-	case PPC_HI6_63:
-		xo = (iword >>  1) & 1023;
-		rt = (iword >> 21) & 31;
-		ra = (iword >> 16) & 31;
-		rb = (iword >> 11) & 31;
-		rs = (iword >>  6) & 31;	/*  actually frc  */
-		rc = iword & 1;
-
-		if (rc) {
-			if (!cpu->translation_readahead)
-				fatal("Floating point (63) "
-				    "with rc bit! TODO\n");
-			goto bad;
-		}
-
-		/*  NOTE: Some floating-point instructions are selected
-		    using only the lowest 5 bits, not all 10!  */
-		switch (xo & 31) {
-		case PPC_63_FDIV:
-		case PPC_63_FSUB:
-		case PPC_63_FADD:
-			switch (xo & 31) {
-			case PPC_63_FDIV: ic->f = instr(fdiv); break;
-			case PPC_63_FSUB: ic->f = instr(fsub); break;
-			case PPC_63_FADD: ic->f = instr(fadd); break;
-			}
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[ra]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[rb]);
-			ic->arg[2] = (size_t)(&cpu->cd.ppc.fpr[rt]);
-			break;
-		case PPC_63_FMUL:
-			ic->f = instr(fmul);
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rt]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[ra]);
-			ic->arg[2] = (size_t)(&cpu->cd.ppc.fpr[rs]); /* frc */
-			break;
-		case PPC_63_FMSUB:
-		case PPC_63_FMADD:
-			switch (xo & 31) {
-			case PPC_63_FMSUB: ic->f = instr(fmsub); break;
-			case PPC_63_FMADD: ic->f = instr(fmadd); break;
-			}
-			ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rt]);
-			ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[ra]);
-			ic->arg[2] = iword;
-			break;
-		default:/*  Use all 10 bits of xo:  */
-			switch (xo) {
-			case PPC_63_FCMPU:
-				ic->f = instr(fcmpu);
-				ic->arg[0] = 28 - 4*(rt >> 2);
-				ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[ra]);
-				ic->arg[2] = (size_t)(&cpu->cd.ppc.fpr[rb]);
-				break;
-			case PPC_63_FRSP:
-			case PPC_63_FCTIWZ:
-			case PPC_63_FNEG:
-			case PPC_63_FABS:
-			case PPC_63_FMR:
-				switch (xo) {
-				case PPC_63_FRSP:   ic->f = instr(frsp); break;
-				case PPC_63_FCTIWZ: ic->f = instr(fctiwz);break;
-				case PPC_63_FNEG:   ic->f = instr(fneg); break;
-				case PPC_63_FABS:   ic->f = instr(fabs); break;
-				case PPC_63_FMR:    ic->f = instr(fmr); break;
-				}
-				ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rb]);
-				ic->arg[1] = (size_t)(&cpu->cd.ppc.fpr[rt]);
-				break;
-			case PPC_63_MFFS:
-				ic->f = instr(mffs);
-				ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rt]);
-				break;
-			case PPC_63_MTFSF:
-				ic->f = instr(mtfsf);
-				ic->arg[0] = (size_t)(&cpu->cd.ppc.fpr[rb]);
-				ic->arg[1] = 0;
-				for (bi=7; bi>=0; bi--) {
-					ic->arg[1] <<= 8;
-					if (iword & (1 << (17+bi)))
-						ic->arg[1] |= 0xf;
-				}
-				break;
-			default:goto bad;
-			}
-		}
-		break;
-
-	default:goto bad;
-	}
-
-
-#define	DYNTRANS_TO_BE_TRANSLATED_TAIL
-#include "cpu_dyntrans.cc"
-#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_ppc_instr_loadstore.c gxemul-0.7.0+dfsg/src/cpus/cpu_ppc_instr_loadstore.c
--- gxemul-0.6.2/src/cpus/cpu_ppc_instr_loadstore.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_ppc_instr_loadstore.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,318 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  POWER/PowerPC load/store instructions.
+ *
+ *
+ *  Load/store instructions have the following arguments:
+ *
+ *  arg[0] = pointer to the register to load to or store from
+ *  arg[1] = pointer to the base register
+ *
+ *  arg[2] = offset (as an int32_t)
+ *	     (or, for Indexed load/stores: pointer to index register)
+ */
+
+
+#ifndef LS_IGNOREOFS
+void LS_GENERIC_N(struct cpu *cpu, struct ppc_instr_call *ic)
+{
+#ifdef MODE32
+	uint32_t addr =
+#else
+	uint64_t addr =
+#endif
+	    reg(ic->arg[1]) +
+#ifdef LS_INDEXED
+	    reg(ic->arg[2]);
+#else
+	    (int32_t)ic->arg[2];
+#endif
+	unsigned char data[LS_SIZE];
+
+	/*  Synchronize the PC:  */
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page)
+	    / sizeof(struct ppc_instr_call);
+	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
+
+#ifndef LS_B
+	if ((addr & 0xfff) + LS_SIZE-1 > 0xfff) {
+		debugmsg_cpu(cpu, SUBSYS_CPU, "ppc", VERBOSITY_ERROR,
+		    "PPC LOAD/STORE misalignment across page boundary: TODO"
+		    " (addr=0x%08x, LS_SIZE=%i)\n", (int)addr, LS_SIZE);
+		cpu->running = false;
+		cpu->cd.ppc.next_ic = &nothing_call;
+		return;
+	}
+#endif
+
+#ifdef LS_LOAD
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
+	    MEM_READ, CACHE_DATA)) {
+		/*  Exception.  */
+		if (!cpu->running)
+			cpu->cd.ppc.next_ic = &nothing_call;
+		return;
+	}
+#ifdef LS_B
+	reg(ic->arg[0]) =
+#ifndef LS_ZERO
+	    (int8_t)
+#endif
+	    data[0];
+#endif
+#ifdef LS_H
+	reg(ic->arg[0]) =
+#ifdef LS_BYTEREVERSE
+	    ((data[1] << 8) + data[0]);
+#else
+#ifndef LS_ZERO
+	    (int16_t)
+#endif
+	    ((data[0] << 8) + data[1]);
+#endif /*  !BYTEREVERSE  */
+#endif
+#ifdef LS_W
+	reg(ic->arg[0]) =
+#ifdef LS_BYTEREVERSE
+	    ((data[3] << 24) + (data[2] << 16) +
+	    (data[1] << 8) + data[0]);
+#else  /* !LS_BYTEREVERSE  */
+#ifndef LS_ZERO
+	    (int32_t)
+#else
+	    (uint32_t)
+#endif
+	    ((data[0] << 24) + (data[1] << 16) +
+	    (data[2] << 8) + data[3]);
+#endif /* !LS_BYTEREVERSE */
+#endif
+#ifdef LS_D
+	(*(uint64_t *)(ic->arg[0])) =
+	    ((uint64_t)data[0] << 56) + ((uint64_t)data[1] << 48) +
+	    ((uint64_t)data[2] << 40) + ((uint64_t)data[3] << 32) +
+	    ((uint64_t)data[4] << 24) + (data[5] << 16) +
+	    (data[6] << 8) + data[7];
+#endif
+
+#else	/*  store:  */
+
+#ifdef LS_B
+	data[0] = reg(ic->arg[0]);
+#endif
+#ifdef LS_H
+#ifdef LS_BYTEREVERSE
+	data[0] = reg(ic->arg[0]);
+	data[1] = reg(ic->arg[0]) >> 8;
+#else
+	data[0] = reg(ic->arg[0]) >> 8;
+	data[1] = reg(ic->arg[0]);
+#endif
+#endif
+#ifdef LS_W
+#ifdef LS_BYTEREVERSE
+	data[0] = reg(ic->arg[0]);
+	data[1] = reg(ic->arg[0]) >> 8;
+	data[2] = reg(ic->arg[0]) >> 16;
+	data[3] = reg(ic->arg[0]) >> 24;
+#else
+	data[0] = reg(ic->arg[0]) >> 24;
+	data[1] = reg(ic->arg[0]) >> 16;
+	data[2] = reg(ic->arg[0]) >> 8;
+	data[3] = reg(ic->arg[0]);
+#endif /* !LS_BYTEREVERSE */
+#endif
+#ifdef LS_D
+	{ uint64_t x = *(uint64_t *)(ic->arg[0]);
+	data[0] = x >> 56;
+	data[1] = x >> 48;
+	data[2] = x >> 40;
+	data[3] = x >> 32;
+	data[4] = x >> 24;
+	data[5] = x >> 16;
+	data[6] = x >> 8;
+	data[7] = x; }
+#endif
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
+	    MEM_WRITE, CACHE_DATA)) {
+		/*  Exception.  */
+		if (!cpu->running)
+			cpu->cd.ppc.next_ic = &nothing_call;
+		return;
+	}
+#endif
+
+#ifdef LS_UPDATE
+	reg(ic->arg[1]) = addr;
+#endif
+}
+#endif
+
+
+void LS_N(struct cpu *cpu, struct ppc_instr_call *ic)
+{
+#ifndef MODE32
+	/************************************************************/
+	/* For now, 64-bit access is done using the slow fallback.  */
+	if (!cpu->is_32bit) {
+		LS_GENERIC_N(cpu, ic);
+		return;
+	}
+#endif
+
+
+#ifdef MODE32
+	uint32_t addr =
+#else
+	uint64_t addr =
+#endif
+	    reg(ic->arg[1])
+#ifdef LS_INDEXED
+	    + reg(ic->arg[2])
+#else
+#ifndef LS_IGNOREOFS
+	    + (int32_t)ic->arg[2]
+#endif
+#endif
+	    ;
+
+	unsigned char *page = cpu->cd.ppc.
+#ifdef LS_LOAD
+	    host_load
+#else
+	    host_store
+#endif
+	    [addr >> 12];
+#ifdef LS_UPDATE
+	uint32_t new_addr = addr;
+#endif
+
+#ifndef LS_B
+	if (addr & (LS_SIZE-1)) {
+		LS_GENERIC_N(cpu, ic);
+		return;
+	}
+#endif
+
+	if (page == NULL) {
+		LS_GENERIC_N(cpu, ic);
+		return;
+	} else {
+		addr &= 4095;
+#ifdef LS_LOAD
+		/*  Load:  */
+#ifdef LS_B
+		reg(ic->arg[0]) =
+#ifndef LS_ZERO
+		    (int8_t)
+#endif
+		    page[addr];
+#endif	/*  LS_B  */
+#ifdef LS_H
+		reg(ic->arg[0]) =
+#ifdef LS_BYTEREVERSE
+		    ((page[addr+1] << 8) + page[addr]);
+#else
+#ifndef LS_ZERO
+		    (int16_t)
+#endif
+		    ((page[addr] << 8) + page[addr+1]);
+#endif /* !BYTEREVERSE */
+#endif	/*  LS_H  */
+#ifdef LS_W
+		reg(ic->arg[0]) =
+#ifdef LS_BYTEREVERSE
+		    ((page[addr+3] << 24) + (page[addr+2] << 16) +
+		    (page[addr+1] << 8) + page[addr]);
+#else  /*  !LS_BYTEREVERSE  */
+#ifndef LS_ZERO
+		    (int32_t)
+#else
+		    (uint32_t)
+#endif
+		    ((page[addr] << 24) + (page[addr+1] << 16) +
+		    (page[addr+2] << 8) + page[addr+3]);
+#endif  /*  !LS_BYTEREVERSE  */
+#endif	/*  LS_W  */
+#ifdef LS_D
+		(*(uint64_t *)(ic->arg[0])) =
+		    ((uint64_t)page[addr+0] << 56) +
+		    ((uint64_t)page[addr+1] << 48) +
+		    ((uint64_t)page[addr+2] << 40) +
+		    ((uint64_t)page[addr+3] << 32) +
+		    ((uint64_t)page[addr+4] << 24) + (page[addr+5] << 16) +
+		    (page[addr+6] << 8) + page[addr+7];
+#endif	/*  LS_D  */
+
+#else	/*  !LS_LOAD  */
+
+		/*  Store:  */
+#ifdef LS_B
+		page[addr] = reg(ic->arg[0]);
+#endif
+#ifdef LS_H
+#ifdef LS_BYTEREVERSE
+		page[addr]   = reg(ic->arg[0]);
+		page[addr+1] = reg(ic->arg[0]) >> 8;
+#else
+		page[addr]   = reg(ic->arg[0]) >> 8;
+		page[addr+1] = reg(ic->arg[0]);
+#endif /* !BYTEREVERSE */
+#endif
+#ifdef LS_W
+#ifdef LS_BYTEREVERSE
+		page[addr]   = reg(ic->arg[0]);
+		page[addr+1] = reg(ic->arg[0]) >> 8;
+		page[addr+2] = reg(ic->arg[0]) >> 16;
+		page[addr+3] = reg(ic->arg[0]) >> 24;
+#else
+		page[addr]   = reg(ic->arg[0]) >> 24;
+		page[addr+1] = reg(ic->arg[0]) >> 16;
+		page[addr+2] = reg(ic->arg[0]) >> 8;
+		page[addr+3] = reg(ic->arg[0]);
+#endif /* !LS_BYTEREVERSE  */
+#endif
+#ifdef LS_D
+		{ uint64_t x = *(uint64_t *)(ic->arg[0]);
+		page[addr]   = x >> 56;
+		page[addr+1] = x >> 48;
+		page[addr+2] = x >> 40;
+		page[addr+3] = x >> 32;
+		page[addr+4] = x >> 24;
+		page[addr+5] = x >> 16;
+		page[addr+6] = x >> 8;
+		page[addr+7] = x; }
+#endif
+#endif	/*  !LS_LOAD  */
+	}
+
+#ifdef LS_UPDATE
+	reg(ic->arg[1]) = new_addr;
+#endif
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_ppc_instr_loadstore.cc gxemul-0.7.0+dfsg/src/cpus/cpu_ppc_instr_loadstore.cc
--- gxemul-0.6.2/src/cpus/cpu_ppc_instr_loadstore.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_ppc_instr_loadstore.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,311 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  POWER/PowerPC load/store instructions.
- *
- *
- *  Load/store instructions have the following arguments:
- *
- *  arg[0] = pointer to the register to load to or store from
- *  arg[1] = pointer to the base register
- *
- *  arg[2] = offset (as an int32_t)
- *	     (or, for Indexed load/stores: pointer to index register)
- */
-
-
-#ifndef LS_IGNOREOFS
-void LS_GENERIC_N(struct cpu *cpu, struct ppc_instr_call *ic)
-{
-#ifdef MODE32
-	uint32_t addr =
-#else
-	uint64_t addr =
-#endif
-	    reg(ic->arg[1]) +
-#ifdef LS_INDEXED
-	    reg(ic->arg[2]);
-#else
-	    (int32_t)ic->arg[2];
-#endif
-	unsigned char data[LS_SIZE];
-
-	/*  Synchronize the PC:  */
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page)
-	    / sizeof(struct ppc_instr_call);
-	cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT);
-
-#ifndef LS_B
-	if ((addr & 0xfff) + LS_SIZE-1 > 0xfff) {
-		fatal("PPC LOAD/STORE misalignment across page boundary: TODO"
-		    " (addr=0x%08x, LS_SIZE=%i)\n", (int)addr, LS_SIZE);
-		exit(1);
-	}
-#endif
-
-#ifdef LS_LOAD
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
-	    MEM_READ, CACHE_DATA)) {
-		/*  Exception.  */
-		return;
-	}
-#ifdef LS_B
-	reg(ic->arg[0]) =
-#ifndef LS_ZERO
-	    (int8_t)
-#endif
-	    data[0];
-#endif
-#ifdef LS_H
-	reg(ic->arg[0]) =
-#ifdef LS_BYTEREVERSE
-	    ((data[1] << 8) + data[0]);
-#else
-#ifndef LS_ZERO
-	    (int16_t)
-#endif
-	    ((data[0] << 8) + data[1]);
-#endif /*  !BYTEREVERSE  */
-#endif
-#ifdef LS_W
-	reg(ic->arg[0]) =
-#ifdef LS_BYTEREVERSE
-	    ((data[3] << 24) + (data[2] << 16) +
-	    (data[1] << 8) + data[0]);
-#else  /* !LS_BYTEREVERSE  */
-#ifndef LS_ZERO
-	    (int32_t)
-#else
-	    (uint32_t)
-#endif
-	    ((data[0] << 24) + (data[1] << 16) +
-	    (data[2] << 8) + data[3]);
-#endif /* !LS_BYTEREVERSE */
-#endif
-#ifdef LS_D
-	(*(uint64_t *)(ic->arg[0])) =
-	    ((uint64_t)data[0] << 56) + ((uint64_t)data[1] << 48) +
-	    ((uint64_t)data[2] << 40) + ((uint64_t)data[3] << 32) +
-	    ((uint64_t)data[4] << 24) + (data[5] << 16) +
-	    (data[6] << 8) + data[7];
-#endif
-
-#else	/*  store:  */
-
-#ifdef LS_B
-	data[0] = reg(ic->arg[0]);
-#endif
-#ifdef LS_H
-#ifdef LS_BYTEREVERSE
-	data[0] = reg(ic->arg[0]);
-	data[1] = reg(ic->arg[0]) >> 8;
-#else
-	data[0] = reg(ic->arg[0]) >> 8;
-	data[1] = reg(ic->arg[0]);
-#endif
-#endif
-#ifdef LS_W
-#ifdef LS_BYTEREVERSE
-	data[0] = reg(ic->arg[0]);
-	data[1] = reg(ic->arg[0]) >> 8;
-	data[2] = reg(ic->arg[0]) >> 16;
-	data[3] = reg(ic->arg[0]) >> 24;
-#else
-	data[0] = reg(ic->arg[0]) >> 24;
-	data[1] = reg(ic->arg[0]) >> 16;
-	data[2] = reg(ic->arg[0]) >> 8;
-	data[3] = reg(ic->arg[0]);
-#endif /* !LS_BYTEREVERSE */
-#endif
-#ifdef LS_D
-	{ uint64_t x = *(uint64_t *)(ic->arg[0]);
-	data[0] = x >> 56;
-	data[1] = x >> 48;
-	data[2] = x >> 40;
-	data[3] = x >> 32;
-	data[4] = x >> 24;
-	data[5] = x >> 16;
-	data[6] = x >> 8;
-	data[7] = x; }
-#endif
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
-	    MEM_WRITE, CACHE_DATA)) {
-		/*  Exception.  */
-		return;
-	}
-#endif
-
-#ifdef LS_UPDATE
-	reg(ic->arg[1]) = addr;
-#endif
-}
-#endif
-
-
-void LS_N(struct cpu *cpu, struct ppc_instr_call *ic)
-{
-#ifndef MODE32
-	/************************************************************/
-	/* For now, 64-bit access is done using the slow fallback.  */
-	if (!cpu->is_32bit) {
-		LS_GENERIC_N(cpu, ic);
-		return;
-	}
-#endif
-
-
-#ifdef MODE32
-	uint32_t addr =
-#else
-	uint64_t addr =
-#endif
-	    reg(ic->arg[1])
-#ifdef LS_INDEXED
-	    + reg(ic->arg[2])
-#else
-#ifndef LS_IGNOREOFS
-	    + (int32_t)ic->arg[2]
-#endif
-#endif
-	    ;
-
-	unsigned char *page = cpu->cd.ppc.
-#ifdef LS_LOAD
-	    host_load
-#else
-	    host_store
-#endif
-	    [addr >> 12];
-#ifdef LS_UPDATE
-	uint32_t new_addr = addr;
-#endif
-
-#ifndef LS_B
-	if (addr & (LS_SIZE-1)) {
-		LS_GENERIC_N(cpu, ic);
-		return;
-	}
-#endif
-
-	if (page == NULL) {
-		LS_GENERIC_N(cpu, ic);
-		return;
-	} else {
-		addr &= 4095;
-#ifdef LS_LOAD
-		/*  Load:  */
-#ifdef LS_B
-		reg(ic->arg[0]) =
-#ifndef LS_ZERO
-		    (int8_t)
-#endif
-		    page[addr];
-#endif	/*  LS_B  */
-#ifdef LS_H
-		reg(ic->arg[0]) =
-#ifdef LS_BYTEREVERSE
-		    ((page[addr+1] << 8) + page[addr]);
-#else
-#ifndef LS_ZERO
-		    (int16_t)
-#endif
-		    ((page[addr] << 8) + page[addr+1]);
-#endif /* !BYTEREVERSE */
-#endif	/*  LS_H  */
-#ifdef LS_W
-		reg(ic->arg[0]) =
-#ifdef LS_BYTEREVERSE
-		    ((page[addr+3] << 24) + (page[addr+2] << 16) +
-		    (page[addr+1] << 8) + page[addr]);
-#else  /*  !LS_BYTEREVERSE  */
-#ifndef LS_ZERO
-		    (int32_t)
-#else
-		    (uint32_t)
-#endif
-		    ((page[addr] << 24) + (page[addr+1] << 16) +
-		    (page[addr+2] << 8) + page[addr+3]);
-#endif  /*  !LS_BYTEREVERSE  */
-#endif	/*  LS_W  */
-#ifdef LS_D
-		(*(uint64_t *)(ic->arg[0])) =
-		    ((uint64_t)page[addr+0] << 56) +
-		    ((uint64_t)page[addr+1] << 48) +
-		    ((uint64_t)page[addr+2] << 40) +
-		    ((uint64_t)page[addr+3] << 32) +
-		    ((uint64_t)page[addr+4] << 24) + (page[addr+5] << 16) +
-		    (page[addr+6] << 8) + page[addr+7];
-#endif	/*  LS_D  */
-
-#else	/*  !LS_LOAD  */
-
-		/*  Store:  */
-#ifdef LS_B
-		page[addr] = reg(ic->arg[0]);
-#endif
-#ifdef LS_H
-#ifdef LS_BYTEREVERSE
-		page[addr]   = reg(ic->arg[0]);
-		page[addr+1] = reg(ic->arg[0]) >> 8;
-#else
-		page[addr]   = reg(ic->arg[0]) >> 8;
-		page[addr+1] = reg(ic->arg[0]);
-#endif /* !BYTEREVERSE */
-#endif
-#ifdef LS_W
-#ifdef LS_BYTEREVERSE
-		page[addr]   = reg(ic->arg[0]);
-		page[addr+1] = reg(ic->arg[0]) >> 8;
-		page[addr+2] = reg(ic->arg[0]) >> 16;
-		page[addr+3] = reg(ic->arg[0]) >> 24;
-#else
-		page[addr]   = reg(ic->arg[0]) >> 24;
-		page[addr+1] = reg(ic->arg[0]) >> 16;
-		page[addr+2] = reg(ic->arg[0]) >> 8;
-		page[addr+3] = reg(ic->arg[0]);
-#endif /* !LS_BYTEREVERSE  */
-#endif
-#ifdef LS_D
-		{ uint64_t x = *(uint64_t *)(ic->arg[0]);
-		page[addr]   = x >> 56;
-		page[addr+1] = x >> 48;
-		page[addr+2] = x >> 40;
-		page[addr+3] = x >> 32;
-		page[addr+4] = x >> 24;
-		page[addr+5] = x >> 16;
-		page[addr+6] = x >> 8;
-		page[addr+7] = x; }
-#endif
-#endif	/*  !LS_LOAD  */
-	}
-
-#ifdef LS_UPDATE
-	reg(ic->arg[1]) = new_addr;
-#endif
-}
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_riscv.c gxemul-0.7.0+dfsg/src/cpus/cpu_riscv.c
--- gxemul-0.6.2/src/cpus/cpu_riscv.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_riscv.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,501 @@
+/*
+ *  Copyright (C) 2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  RISC-V CPU emulation.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <unistd.h>
+
+#include "cpu.h"
+#include "float_emul.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "settings.h"
+#include "symbol.h"
+
+
+#define DYNTRANS_DUALMODE_32
+
+#include "tmp_riscv_head.c"
+
+void riscv_pc_to_pointers(struct cpu *);
+void riscv32_pc_to_pointers(struct cpu *);
+void riscv_cpu_functioncall_trace(struct cpu *cpu, int n_args);
+
+void riscv_irq_interrupt_assert(struct interrupt *interrupt);
+void riscv_irq_interrupt_deassert(struct interrupt *interrupt);
+
+static const char *riscv_register_names[] = RISCV_REGISTER_NAMES;
+static const char *riscv_extension_names[] = RISCV_EXTENSION_NAMES;
+
+
+/*
+ *  riscv_cpu_new():
+ *
+ *  Create a new RISC-V cpu object by filling the CPU struct.
+ *  Return 1 on success, 0 if cpu_type_name isn't a valid processor model.
+ */
+int riscv_cpu_new(struct cpu *cpu, struct memory *mem,
+	struct machine *machine, int cpu_id, char *cpu_type_name)
+{
+	int bits;
+
+	if (strncmp(cpu_type_name, "RV32", 4) == 0) {
+		bits = 32;
+	} else if (strncmp(cpu_type_name, "RV64", 4) == 0) {
+		bits = 64;
+	} else if (strncmp(cpu_type_name, "RV128", 4) == 0) {
+		bits = 128;
+	} else
+		return 0;
+
+	if (bits == 128) {
+		debugmsg_cpu(cpu, SUBSYS_CPU, "riscv_cpu_new", VERBOSITY_ERROR,
+	    	    "TODO: 128-bit");
+	    	return 0;
+	}
+
+	// Step through extension letters.
+	const char *p = cpu_type_name + strlen("RVxx");
+	cpu->cd.riscv.extensions = 0;
+	while (*p) {
+		char c = *p;
+		if (c == 'G') {
+			cpu->cd.riscv.extensions |= RISCV_EXT_G;
+		} else {
+			int i = 0;
+			while (riscv_extension_names[i] != NULL) {
+				if (c == riscv_extension_names[i][0])
+					cpu->cd.riscv.extensions |= 1 << i;
+
+				++ i;
+			}
+		}
+
+		++p;
+	}
+
+	if (cpu->cd.riscv.extensions & RISCV_EXT_E) {
+		if (bits != 32) {
+			debugmsg_cpu(cpu, SUBSYS_CPU, "riscv_cpu_new", VERBOSITY_ERROR,
+		    	    "the E extension only works with RV32");
+		    	return 0;
+		}
+
+		if (cpu->cd.riscv.extensions & RISCV_EXT_I) {
+			debugmsg_cpu(cpu, SUBSYS_CPU, "riscv_cpu_new", VERBOSITY_ERROR,
+		    	    "the E extension can not be combined with I");
+		    	return 0;
+		}
+	} else {
+		if (!(cpu->cd.riscv.extensions & RISCV_EXT_I)) {
+			debugmsg_cpu(cpu, SUBSYS_CPU, "riscv_cpu_new", VERBOSITY_ERROR,
+		    	    "either the I or E extensions must be present");
+		    	return 0;
+		}
+	}
+
+	cpu->name = strdup(cpu_type_name);
+
+	cpu->byte_order = EMUL_BIG_ENDIAN;
+	cpu->memory_rw = riscv_memory_rw;
+
+	if (bits == 32) {
+		cpu->is_32bit        = 1;
+		cpu->vaddr_mask = 0x00000000ffffffffULL;
+		cpu->run_instr = riscv32_run_instr;
+		cpu->update_translation_table = riscv32_update_translation_table;
+		cpu->invalidate_translation_caches = riscv32_invalidate_translation_caches;
+		cpu->invalidate_code_translation = riscv32_invalidate_code_translation;
+	} else {
+		cpu->is_32bit        = 0;
+		cpu->vaddr_mask = 0xffffffffffffffffULL;
+		cpu->run_instr = riscv_run_instr;
+		cpu->update_translation_table = riscv_update_translation_table;
+		cpu->invalidate_translation_caches = riscv_invalidate_translation_caches;
+		cpu->invalidate_code_translation = riscv_invalidate_code_translation;
+	}
+
+
+	/*
+	 *  Add register names as settings:
+	 */
+
+	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
+
+	// Readonly "x0" register (zero).
+	settings_add(cpu->settings, "x0", 0, SETTINGS_TYPE_UINT64,
+            cpu->is_32bit? SETTINGS_FORMAT_HEX32 : SETTINGS_FORMAT_HEX64,
+            (void *) &cpu->cd.riscv.x[0]);
+
+	for (int i = 1; i < N_RISCV_REGS; i++) {
+		char name[10];
+		snprintf(name, sizeof(name), "x%i", i);
+
+		CPU_SETTINGS_ADD_REGISTER64(name, cpu->cd.riscv.x[i]);
+		CPU_SETTINGS_ADD_REGISTER64(riscv_register_names[i], cpu->cd.riscv.x[i]);
+	}
+
+	/*  Register the CPU interrupt pin:  */
+	struct interrupt templ;
+	char name[50];
+	snprintf(name, sizeof(name), "%s", cpu->path);
+
+	memset(&templ, 0, sizeof(templ));
+	templ.line = 0;
+	templ.name = name;
+	templ.extra = cpu;
+	templ.interrupt_assert = riscv_irq_interrupt_assert;
+	templ.interrupt_deassert = riscv_irq_interrupt_deassert;
+	interrupt_handler_register(&templ);
+
+	return 1;
+}
+
+
+static const char* riscv_extensions_string(struct cpu *cpu)
+{
+	static char buf[200];
+
+	snprintf(buf, sizeof(buf), "RV%i", cpu->is_32bit ? 32 : 64);
+
+	int i = 0;
+	while (riscv_extension_names[i] != NULL) {
+		if (cpu->cd.riscv.extensions & (1 << i))
+			snprintf(buf + strlen(buf), sizeof(buf) - strlen(buf),
+			    "%s", riscv_extension_names[i]);
+
+		++ i;
+	}
+
+	return buf;
+}
+
+
+/*
+ *  riscv_cpu_dumpinfo():
+ */
+void riscv_cpu_dumpinfo(struct cpu *cpu, bool verbose)
+{
+	debugmsg(SUBSYS_MACHINE, "cpu", VERBOSITY_INFO,
+	    "%s (%s)",
+	    cpu->name,
+	    riscv_extensions_string(cpu));
+}
+
+
+/*
+ *  riscv_cpu_list_available_types():
+ *
+ *  Print a list of available riscv CPU types.
+ */
+void riscv_cpu_list_available_types(void)
+{
+	debug("RV{32,64,128}EIMAFDGQLCBJTPVN\n");
+}
+
+
+/*
+ *  riscv_cpu_register_dump():
+ *
+ *  Dump cpu registers in a relatively readable format.
+ *  
+ *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
+ *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
+ */
+void riscv_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
+{
+	if (gprs) {
+		uint64_t offset;
+		const char *symbol = get_symbol_name(&cpu->machine->symbol_context, cpu->pc, &offset);
+
+		debug("cpu%i:  pc  = ", cpu->cpu_id);
+
+		if (cpu->is_32bit)
+			debug("0x%08" PRIx32, (uint32_t) cpu->pc);
+		else
+			debug("0x%016" PRIx64, (uint64_t) cpu->pc);
+
+		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
+
+		int n_regs_per_line = cpu->is_32bit ? 4 : 2;
+
+		for (int i = 0; i < N_RISCV_REGS; i++) {
+			if ((i % n_regs_per_line) == 0)
+				debug("cpu%i:", cpu->cpu_id);
+
+			debug("  ");
+
+			if (i == 0) {
+				debug("      ");
+
+				if (cpu->is_32bit)
+					debug("          ");
+				else
+					debug("                  ");
+			} else {
+				debug("%-3s = ", riscv_register_names[i]);
+
+				if (cpu->is_32bit)
+					debug("0x%08" PRIx32, (uint32_t) cpu->cd.riscv.x[i]);
+				else
+					debug("0x%016" PRIx64, (uint64_t) cpu->cd.riscv.x[i]);
+			}
+
+			if ((i % n_regs_per_line) == n_regs_per_line-1)
+				debug("\n");
+		}
+	}
+}
+
+
+/*
+ *  riscv_cpu_tlbdump():
+ *
+ *  Called from the debugger to dump the TLB in a readable format.
+ *
+ *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
+ *  just dumped.
+ */
+void riscv_cpu_tlbdump(struct cpu* cpu, int rawflag)
+{
+}
+
+
+/*
+ *  riscv_irq_interrupt_assert():
+ *  riscv_irq_interrupt_deassert():
+ */
+void riscv_irq_interrupt_assert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.riscv.irq_asserted = 1;
+}
+void riscv_irq_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	cpu->cd.riscv.irq_asserted = 0;
+}
+
+
+/*
+ *  riscv_exception():
+ *
+ *  Cause an exception.
+ */
+void riscv_exception(struct cpu *cpu, int vector, int is_trap)
+{
+	debugmsg_cpu(cpu, SUBSYS_EXCEPTION, "", VERBOSITY_ERROR,
+	    "riscv_exception(): TODO");
+
+	cpu->running = false;
+
+	riscv_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  riscv_cpu_disassemble_instr():
+ *
+ *  Convert an instruction word into human readable format, for instruction
+ *  tracing.
+ *              
+ *  If running is 1, cpu->pc should be the address of the instruction.
+ *
+ *  If running is 0, things that depend on the runtime environment (eg.
+ *  register contents) will not be shown, and dumpaddr will be used instead of
+ *  cpu->pc for relative addresses.
+ */                     
+int riscv_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
+        int running, uint64_t dumpaddr)
+{
+	if (running)
+		dumpaddr = cpu->pc;
+
+	uint64_t offset;
+	const char *symbol = get_symbol_name(&cpu->machine->symbol_context,
+	    dumpaddr, &offset);
+	if (symbol != NULL && offset == 0)
+		debug("<%s>\n", symbol);
+
+	if (cpu->machine->ncpus > 1 && running)
+		debug("cpu%i:\t", cpu->cpu_id);
+
+	if (cpu->is_32bit)
+		debug("%08" PRIx32": ", (uint32_t) dumpaddr);
+	else
+		debug("%016" PRIx64": ", (uint64_t) dumpaddr);
+
+	int instr_length_in_bytes = sizeof(uint16_t);
+	uint32_t iw;
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iw = ib[0] + (ib[1]<<8);
+	else
+		iw = ib[1] + (ib[0]<<8);
+
+	if ((iw & 3) == 3) {
+		// At least 2 16-bit chunks.
+		uint16_t iw2;
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			iw2 = ib[2] + (ib[3]<<8);
+		else
+			iw2 = ib[3] + (ib[2]<<8);
+
+		iw |= (iw2 << 16);
+
+		if (((iw >> 2) & 7) == 7) {
+			debug("longer than 32-bit instruction: TODO\n");
+			return sizeof(uint32_t);	// actually wrong... :-(
+		}
+
+		instr_length_in_bytes = sizeof(uint32_t);
+	}
+
+	if (instr_length_in_bytes == sizeof(uint16_t))
+		debug("%04x    ", (uint32_t) iw);
+	else
+		debug("%08" PRIx32, (uint32_t) iw);
+
+	cpu_print_pc_indicator_in_disassembly(cpu, running, dumpaddr);
+
+
+	// As far as I understood, the 16-bit compressed instructions can be
+	// "remapped" into 32-bit encoded instructions. Instead of showing
+	// disassembly such as "c.lui", the approach is to just show "lui"
+	// instead, like GNU's objdump -d. This makes the disassembly more
+	// readable. On the implementation side (cpu_riscv_instr.c), the
+	// compressed and the normal encoding should (hopefully) always end up
+	// in the same instruction implementation anyway.
+	if (instr_length_in_bytes == sizeof(uint16_t)) {
+		if (!(cpu->cd.riscv.extensions & RISCV_EXT_C))
+			debug("compressed (req. C ext)\t; ");
+
+		uint w13 = (iw >> 13) & 7;
+		uint w0 = (iw >> 0) & 3;
+		uint op = (w13 << 2) | w0;
+
+		uint rs1rd = (iw >> 7) & 31;
+		uint rs2 = (iw >> 2) & 31;
+		uint rprim_2 = ((iw >> 2) & 7) + RISCV_CREGBASE;
+		uint64_t nzimm5 = ((iw & (1 << 12)) ? -1 : 0) << 5;
+		uint64_t nzimm;
+
+		int hi_imm53 = (iw >> 10) & 7;
+		int hi_imm86 = (iw >> 7) & 7;
+		int imm;
+
+		switch (op) {
+		case 0:	// c.addi4spn
+			// nzimm[5:4|9:6|2|3] at bitpos 5
+			nzimm = (((iw >> 5) & 1) << 3)
+			      | (((iw >> 6) & 1) << 2)
+			      | (((iw >> 7) & 15) << 6)
+			      | (((iw >> 11) & 7) << 4);
+
+			if (nzimm == 0) {
+				debug("INVALID instruction");
+			} else {
+				debug("addi\t%s,%s,%lli",
+				    riscv_register_names[rprim_2],
+				    riscv_register_names[RISCV_REG_SP],
+				    (long long) nzimm);
+			}
+			break;
+
+		case 1:	// c.addi
+			nzimm = nzimm5 | ((iw >> 2) & 31);
+			if (rs1rd == 0 && nzimm == 0)
+				debug("nop");
+			else if (rs1rd == 0)
+				debug("addi\tTODO: rs1rd = 0 but nzimm = %lli?", (long long) nzimm);
+			else
+				debug("addi\t%s,%s,%lli", riscv_register_names[rs1rd], riscv_register_names[rs1rd], (long long) nzimm);
+			break;
+
+		case 13:	// c.lui
+			nzimm = (((iw >> 2) & 31) << 12)
+			      | (((iw >> 12) & 1) << 17);
+
+			if (nzimm == 0) {
+				debug("INVALID lui?");
+			} else if (rs1rd == 0) {
+				debug("INVALID lui, rs1rd = 0?");
+			} else if (rs1rd == RISCV_REG_SP) {
+				debug("TODO: c.addi16sp");
+			} else {
+				debug("lui\t%s,0x%x",
+				    riscv_register_names[rs1rd],
+				    (int) (nzimm >> 12));
+			}
+
+			break;
+
+		case 14:	// c.ldsp
+			// TODO: RV64/128 only
+			imm = (((iw >> 2) & 7) << 6)
+			      | (((iw >> 5) & 3) << 3)
+			      | (((iw >> 12) & 1) << 5);
+			debug("ld\t%s,%i(%s)",
+			    riscv_register_names[rs1rd],
+			    imm,
+			    riscv_register_names[RISCV_REG_SP]);
+			break;
+
+		case 30:	// c.sdsp
+			// TODO: RV64/128 only
+			imm = (hi_imm53 << 3) + (hi_imm86 << 6);
+			debug("sd\t%s,%i(%s)",
+			    riscv_register_names[rs2],
+			    imm,
+			    riscv_register_names[RISCV_REG_SP]);
+			break;
+
+		default:
+			debug("UNIMPLEMENTED compressed op %i", op);
+		}
+	} else if (instr_length_in_bytes == sizeof(uint32_t)) {
+		debug("TODO: 32-bit wide instruction words");
+	} else {
+		debug("TODO");
+	}
+	
+	debug("\n");
+
+	return instr_length_in_bytes;
+}
+
+
+#include "tmp_riscv_tail.c"
+
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_riscv_instr.c gxemul-0.7.0+dfsg/src/cpus/cpu_riscv_instr.c
--- gxemul-0.6.2/src/cpus/cpu_riscv_instr.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_riscv_instr.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,254 @@
+/*
+ *  Copyright (C) 2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  RISC-V instructions.
+ */
+
+
+#define SYNCH_PC                {                                       \
+                int low_pc = ((size_t)ic - (size_t)cpu->cd.riscv.cur_ic_page) \
+                    / sizeof(struct riscv_instr_call);                   \
+                cpu->pc &= ~((RISCV_IC_ENTRIES_PER_PAGE-1)               \
+                    << RISCV_INSTR_ALIGNMENT_SHIFT);                     \
+                cpu->pc += (low_pc << RISCV_INSTR_ALIGNMENT_SHIFT);      \
+        }
+
+
+/*
+ *  nop:  Do nothing.
+ */
+X(nop)
+{
+}
+
+
+/*
+ *  addi: Add immediate.
+ *
+ *  arg[0] = pointer to rd
+ *  arg[1] = pointer to rs
+ *  arg[2] = (int32_t) immediate value
+ */
+X(addi)
+{
+	reg(ic->arg[0]) = (MODE_uint_t) (
+	    (MODE_uint_t)reg(ic->arg[1]) + (MODE_int_t)(int32_t)ic->arg[2] );
+}
+
+
+/*****************************************************************************/
+
+
+X(end_of_page)
+{
+	/*  Update the PC:  (offset 0, but on the next page)  */
+	cpu->pc &= ~((RISCV_IC_ENTRIES_PER_PAGE-1) << RISCV_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (RISCV_IC_ENTRIES_PER_PAGE << RISCV_INSTR_ALIGNMENT_SHIFT);
+
+	/*  end_of_page doesn't count as an executed instruction:  */
+	cpu->n_translated_instrs --;
+
+	/*
+	 *  Find the new physpage and update translation pointers.
+	 *
+	 *  Note: This may cause an exception, if e.g. the new page is
+	 *  not accessible.
+	 */
+	quick_pc_to_pointers(cpu);
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  riscv_instr_to_be_translated():
+ *
+ *  Translate an instruction word into a riscv_instr_call. ic is filled in with
+ *  valid data for the translated instruction, or a "nothing" instruction if
+ *  there was a translation failure. The newly translated instruction is then
+ *  executed.
+ */
+X(to_be_translated)
+{
+	uint8_t ib[sizeof(uint32_t)];
+	bool cross_page_instruction = false;
+
+	/*  Figure out the (virtual) address of the instruction:  */
+	uint64_t low_pc = ((size_t)ic - (size_t)cpu->cd.riscv.cur_ic_page)
+	    / sizeof(struct riscv_instr_call);
+
+	uint64_t addr = cpu->pc & ~((RISCV_IC_ENTRIES_PER_PAGE-1)
+	    << RISCV_INSTR_ALIGNMENT_SHIFT);
+	addr += (low_pc << RISCV_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc = (MODE_int_t)addr;
+	addr &= ~((1 << RISCV_INSTR_ALIGNMENT_SHIFT) - 1);
+
+	/*  Read the instruction word from memory:  */
+	uint8_t* page;
+#ifdef MODE32
+	page = cpu->cd.riscv.host_load[(uint32_t)addr >> 12];
+#else
+	{
+		const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+		const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+		const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+		uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
+		uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+		uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
+		    DYNTRANS_L3N)) & mask3;
+		struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.riscv.l1_64[x1];
+		struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
+		page = l3->host_load[x3];
+	}
+#endif
+
+	if (page != NULL) {
+		// fatal("PAGE TRANSLATION HIT!\n");
+		memcpy(ib, page + (addr & 0xffe), sizeof(uint16_t));
+	} else {
+		// fatal("PAGE TRANSLATION MISS!\n");
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
+		    sizeof(uint16_t), MEM_READ, CACHE_INSTRUCTION)) {
+			fatal("to_be_translated(): read failed: TODO\n");
+			goto bad;
+		}
+	}
+
+	int instr_length_in_bytes = sizeof(uint16_t);
+	uint32_t iw;
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iw = ib[0] + (ib[1]<<8);
+	else
+		iw = ib[1] + (ib[0]<<8);
+
+	if ((iw & 3) == 3) {
+		// At least 2 16-bit chunks. Read the second 16-bit chunk:
+
+		uint8_t* page2;
+		uint64_t addr2 = addr + sizeof(uint16_t);
+
+		cross_page_instruction = (addr2 & 0xffe) == 0x000;
+
+#ifdef MODE32
+		page2 = cpu->cd.riscv.host_load[(uint32_t)addr2 >> 12];
+#else
+		const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
+		const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
+		const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
+		uint32_t x1 = (addr2 >> (64-DYNTRANS_L1N)) & mask1;
+		uint32_t x2 = (addr2 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+		uint32_t x3 = (addr2 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
+		    DYNTRANS_L3N)) & mask3;
+		struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.riscv.l1_64[x1];
+		struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
+		page2 = l3->host_load[x3];
+#endif
+
+		if (page2 != NULL) {
+			// fatal("PAGE2 TRANSLATION HIT!\n");
+			memcpy(&ib[2], page2 + (addr2 & 0xffe), sizeof(uint16_t));
+		} else {
+			// fatal("PAGE2 TRANSLATION MISS!\n");
+			if (!cpu->memory_rw(cpu, cpu->mem, addr2, &ib[2],
+			    sizeof(uint16_t), MEM_READ, CACHE_INSTRUCTION)) {
+				fatal("to_be_translated(): read failed: TODO\n");
+				goto bad;
+			}
+		}
+
+		uint16_t iw2;
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			iw2 = ib[2] + (ib[3]<<8);
+		else
+			iw2 = ib[3] + (ib[2]<<8);
+
+		iw |= (iw2 << 16);
+
+		if (((iw >> 2) & 7) == 7) {
+			fatal("longer than 32-bit instruction: TODO\n");
+			goto bad;
+		}
+
+		instr_length_in_bytes = sizeof(uint32_t);
+	}
+
+
+#define DYNTRANS_TO_BE_TRANSLATED_HEAD
+#include "cpu_dyntrans.c"
+#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD
+
+
+	/*
+	 *  Translate the instruction:
+	 */
+
+	if (instr_length_in_bytes == sizeof(uint16_t)) {
+		uint w13 = (iw >> 13) & 7;
+		uint w0 = (iw >> 0) & 3;
+		uint op = (w13 << 2) | w0;
+
+		uint rs1rd = (iw >> 7) & 31;
+		uint64_t nzimm5 = ((iw & (1 << 12)) ? -1 : 0) << 5;
+		uint64_t nzimm = nzimm5 | ((iw >> 2) & 31);
+
+		switch (op) {
+		case 1:
+			if (rs1rd == 0 && nzimm == 0)
+				ic->f = instr(nop);
+			else if (rs1rd == 0)
+				goto bad;
+			else {
+				ic->f = instr(addi);
+				ic->arg[0] = (size_t)&cpu->cd.riscv.x[rs1rd];
+				ic->arg[1] = (size_t)&cpu->cd.riscv.x[rs1rd];
+				ic->arg[2] = nzimm;
+			}
+			break;
+		default:
+			goto bad;
+		}
+
+	} else if (instr_length_in_bytes == sizeof(uint32_t)) {
+		goto bad;
+	} else {
+		goto bad;
+	}
+
+
+	if (cross_page_instruction) {
+		debugmsg_cpu(cpu, SUBSYS_CPU, "", VERBOSITY_ERROR,
+		    "TODO: RISC-V cross page instruction");
+		goto bad;
+	}
+
+#define	DYNTRANS_TO_BE_TRANSLATED_TAIL
+#include "cpu_dyntrans.c" 
+#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_sh.c gxemul-0.7.0+dfsg/src/cpus/cpu_sh.c
--- gxemul-0.6.2/src/cpus/cpu_sh.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_sh.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1410 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Hitachi SuperH ("SH") CPU emulation.
+ *
+ *  TODO: It would be nice if this could encompass both 64-bit SH5, and
+ *        32-bit SH encodings. Right now, it only really supports 32-bit mode.
+ *
+ *  TODO: This actually only works or SH4 so far, not SH3.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <unistd.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "float_emul.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "settings.h"
+#include "symbol.h"
+
+#include "thirdparty/sh4_exception.h"
+#include "thirdparty/sh4_mmu.h"
+
+
+#define DYNTRANS_32
+#define DYNTRANS_DELAYSLOT
+#include "tmp_sh_head.c"
+
+
+extern int quiet_mode;
+
+void sh_pc_to_pointers(struct cpu *);
+
+void sh3_cpu_interrupt_assert(struct interrupt *interrupt);
+void sh3_cpu_interrupt_deassert(struct interrupt *interrupt);
+
+
+/*
+ *  sh_cpu_new():
+ *
+ *  Create a new SH cpu object.
+ *
+ *  Returns 1 on success, 0 if there was no matching SH processor with
+ *  this cpu_type_name.
+ */
+int sh_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
+	int cpu_id, char *cpu_type_name)
+{
+	int i = 0;
+	struct sh_cpu_type_def cpu_type_defs[] = SH_CPU_TYPE_DEFS;
+
+	/*  Scan the cpu_type_defs list for this cpu type:  */
+	while (cpu_type_defs[i].name != NULL) {
+		if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
+			break;
+		}
+		i++;
+	}
+	if (cpu_type_defs[i].name == NULL)
+		return 0;
+
+	cpu->memory_rw = sh_memory_rw;
+
+	cpu->cd.sh.cpu_type = cpu_type_defs[i];
+	cpu->byte_order = EMUL_LITTLE_ENDIAN;
+	cpu->is_32bit = cpu->cd.sh.cpu_type.bits == 32;
+
+	if (!cpu->is_32bit) {
+		fatal("SH64 emulation not implemented. Sorry.\n");
+		exit(1);
+	}
+
+	cpu->instruction_has_delayslot = sh_cpu_instruction_has_delayslot;
+
+	cpu->translate_v2p = sh_translate_v2p;
+
+	cpu->run_instr = sh_run_instr;
+	cpu->update_translation_table = sh_update_translation_table;
+	cpu->invalidate_translation_caches =
+	    sh_invalidate_translation_caches;
+	cpu->invalidate_code_translation =
+	    sh_invalidate_code_translation;
+
+	/*  Initial value of FPSCR (according to the SH4 manual):  */
+	cpu->cd.sh.fpscr = 0x00040001;
+
+	/*  (Initial value of the program counter on reboot is 0xA0000000.)  */
+
+	/*  Start in Privileged Mode:  */
+	cpu->cd.sh.sr = SH_SR_MD | SH_SR_IMASK;
+
+	/*  Stack pointer at end of physical RAM:  */
+	cpu->cd.sh.r[15] = cpu->machine->physical_ram_in_mb * 1048576 - 64;
+
+	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
+	CPU_SETTINGS_ADD_REGISTER32("sr", cpu->cd.sh.sr);
+	CPU_SETTINGS_ADD_REGISTER32("pr", cpu->cd.sh.pr);
+	CPU_SETTINGS_ADD_REGISTER32("vbr", cpu->cd.sh.vbr);
+	CPU_SETTINGS_ADD_REGISTER32("sgr", cpu->cd.sh.sgr);
+	CPU_SETTINGS_ADD_REGISTER32("gbr", cpu->cd.sh.gbr);
+	CPU_SETTINGS_ADD_REGISTER32("dbr", cpu->cd.sh.dbr);
+	CPU_SETTINGS_ADD_REGISTER32("macl", cpu->cd.sh.macl);
+	CPU_SETTINGS_ADD_REGISTER32("mach", cpu->cd.sh.mach);
+	CPU_SETTINGS_ADD_REGISTER32("expevt", cpu->cd.sh.expevt);
+	CPU_SETTINGS_ADD_REGISTER32("intevt", cpu->cd.sh.intevt);
+	CPU_SETTINGS_ADD_REGISTER32("tra", cpu->cd.sh.tra);
+	CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.sh.fpscr);
+	CPU_SETTINGS_ADD_REGISTER32("fpul", cpu->cd.sh.fpul);
+	for (i=0; i<SH_N_GPRS; i++) {
+		char tmpstr[5];
+		snprintf(tmpstr, sizeof(tmpstr), "r%i", i);
+		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.r[i]);
+	}
+	for (i=0; i<SH_N_GPRS_BANKED; i++) {
+		char tmpstr[15];
+		snprintf(tmpstr, sizeof(tmpstr), "r%i_bank", i);
+		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.r_bank[i]);
+	}
+	for (i=0; i<SH_N_FPRS; i++) {
+		char tmpstr[6];
+		snprintf(tmpstr, sizeof(tmpstr), "fr%i", i);
+		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.fr[i]);
+		snprintf(tmpstr, sizeof(tmpstr), "xf%i", i);
+		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.xf[i]);
+	}
+	for (i=0; i<SH_N_ITLB_ENTRIES; i++) {
+		char tmpstr[15];
+		snprintf(tmpstr, sizeof(tmpstr), "itlb_hi_%i", i);
+		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.itlb_hi[i]);
+		snprintf(tmpstr, sizeof(tmpstr), "itlb_lo_%i", i);
+		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.itlb_lo[i]);
+	}
+	for (i=0; i<SH_N_UTLB_ENTRIES; i++) {
+		char tmpstr[15];
+		snprintf(tmpstr, sizeof(tmpstr), "utlb_hi_%i", i);
+		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.utlb_hi[i]);
+		snprintf(tmpstr, sizeof(tmpstr), "utlb_lo_%i", i);
+		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.utlb_lo[i]);
+	}
+
+	/*  Register the CPU's interrupts:  */
+	if (cpu->cd.sh.cpu_type.arch == 4) {
+		for (i=SH_INTEVT_NMI; i<0x1000; i+=0x20) {
+			struct interrupt templ;
+			char name[100];
+			snprintf(name, sizeof(name), "%s.irq[0x%x]",
+			    cpu->path, i);
+			memset(&templ, 0, sizeof(templ));
+			templ.line = i;
+			templ.name = name;
+			templ.extra = cpu;
+			templ.interrupt_assert = sh_cpu_interrupt_assert;
+			templ.interrupt_deassert = sh_cpu_interrupt_deassert;
+			interrupt_handler_register(&templ);
+		}
+	} else {
+		struct interrupt templ;
+		memset(&templ, 0, sizeof(templ));
+		templ.line = i;
+		templ.name = cpu->path;
+		templ.extra = cpu;
+		templ.interrupt_assert = sh3_cpu_interrupt_assert;
+		templ.interrupt_deassert = sh3_cpu_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	/*  SH4-specific memory mapped registers, TLBs, caches, etc:  */
+	if (cpu->cd.sh.cpu_type.arch == 4) {
+		cpu->cd.sh.pcic_pcibus = (struct pci_data *) device_add(machine, "sh4");
+
+		/*
+		 *  Interrupt Controller initial values, according to the
+		 *  SH7760 manual:
+		 */
+		cpu->cd.sh.intc_iprd = 0xda74;
+		cpu->cd.sh.intc_intmsk00 = 0xf3ff7fff;
+		cpu->cd.sh.intc_intmsk04 = 0x00ffffff;
+		/*  All others are zero.  */
+
+		/*  TODO: Initial priorities?  */
+		cpu->cd.sh.intc_intpri00 = 0x33333333;
+		cpu->cd.sh.intc_intpri04 = 0x33333333;
+		cpu->cd.sh.intc_intpri08 = 0x33333333;
+		cpu->cd.sh.intc_intpri0c = 0x33333333;
+	}
+
+	sh_update_interrupt_priorities(cpu);
+
+	return 1;
+}
+
+
+/*
+ *  sh_update_interrupt_priorities():
+ *
+ *  SH interrupts are a bit complicated; there are several intc registers
+ *  controlling priorities for various peripherals:
+ *
+ *  Register:  Bits 15..12  11..8  7..4      3..0
+ *  ---------  -----------  -----  ----      ----
+ *  ipra       TMU0         TMU1   TMU2      Reserved
+ *  iprb       WDT          REF    Reserved  Reserved
+ *  iprc       GPIO         DMAC   Reserved  H-UDI
+ *  iprd       IRL0         IRL1   IRL2      IRL3
+ *
+ *  Register:  31..28  27..24  23..20  19..16  15..12  11..8   7..4   3..0
+ *  ---------  ------  ------  ------  ------  ------  -----   ----   ----
+ *  intpri00   IRQ4    IRQ5    IRQ6    IRQ7    Rsrvd.  Rsrvd.  Rsrvd. Reserved
+ *  intpri04   HCAN2,0 HCAN2,1 SSI(0)  SSI(1)  HAC(0)  HAC(1)  I2C(0) I2C(1)
+ *  intpri08   USB     LCDC    DMABRG  SCIF(0) SCIF(1) SCIF(2) SIM    HSPI
+ *  intpri0c   Reserv. Reserv. MMCIF   Reserv. MFI     Rsrvd.  ADC    CMT
+ */
+void sh_update_interrupt_priorities(struct cpu *cpu)
+{
+	int i;
+
+	/*
+	 *  Set priorities of known interrupts, without affecting the
+	 *  SH_INT_ASSERTED bit:
+	 */
+
+	for (i=SH4_INTEVT_IRQ0; i<=SH4_INTEVT_IRQ14; i+=0x20) {
+		cpu->cd.sh.int_prio_and_pending[i/0x20] &= ~SH_INT_PRIO_MASK;
+		cpu->cd.sh.int_prio_and_pending[i/0x20] |= (15 - ((i - 
+		    SH4_INTEVT_IRQ0) / 0x20));
+	}
+
+	cpu->cd.sh.int_prio_and_pending[SH_INTEVT_TMU0_TUNI0 / 0x20] &=
+	    ~SH_INT_PRIO_MASK;
+	cpu->cd.sh.int_prio_and_pending[SH_INTEVT_TMU0_TUNI0 / 0x20] |=
+	    (cpu->cd.sh.intc_ipra >> 12) & 0xf;
+
+	cpu->cd.sh.int_prio_and_pending[SH_INTEVT_TMU1_TUNI1 / 0x20] &=
+	    ~SH_INT_PRIO_MASK;
+	cpu->cd.sh.int_prio_and_pending[SH_INTEVT_TMU1_TUNI1 / 0x20] |=
+	    (cpu->cd.sh.intc_ipra >> 8) & 0xf;
+
+	cpu->cd.sh.int_prio_and_pending[SH_INTEVT_TMU2_TUNI2 / 0x20] &=
+	    ~SH_INT_PRIO_MASK;
+	cpu->cd.sh.int_prio_and_pending[SH_INTEVT_TMU2_TUNI2 / 0x20] |=
+	    (cpu->cd.sh.intc_ipra >> 4) & 0xf;
+
+	for (i=SH4_INTEVT_SCIF_ERI; i<=SH4_INTEVT_SCIF_TXI; i+=0x20) {
+		cpu->cd.sh.int_prio_and_pending[i/0x20] &= ~SH_INT_PRIO_MASK;
+		cpu->cd.sh.int_prio_and_pending[i/0x20] |=
+		    ((cpu->cd.sh.intc_intpri08 >> 16) & 0xf);
+	}
+}
+
+
+/*
+ *  sh3_cpu_interrupt_assert():
+ *  sh3_cpu_interrupt_deassert():
+ */
+void sh3_cpu_interrupt_assert(struct interrupt *interrupt)
+{
+	/*  TODO  */
+}
+void sh3_cpu_interrupt_deassert(struct interrupt *interrupt)
+{
+	/*  TODO  */
+}       
+
+
+/*
+ *  sh_cpu_interrupt_assert():
+ */
+void sh_cpu_interrupt_assert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	unsigned int irq_nr = interrupt->line;
+	unsigned int index = irq_nr / 0x20;
+	unsigned int prio;
+
+	/*  Assert the interrupt, and check its priority level:  */
+	cpu->cd.sh.int_prio_and_pending[index] |= SH_INT_ASSERTED;
+	prio = cpu->cd.sh.int_prio_and_pending[index] & SH_INT_PRIO_MASK;
+
+	if (prio == 0) {
+		/*  Interrupt not implemented? Hm.  */
+		fatal("[ SH interrupt 0x%x, prio 0 (?), aborting ]\n", irq_nr);
+		exit(1);
+	}
+
+	if (cpu->cd.sh.int_to_assert == 0 || prio > cpu->cd.sh.int_level) {
+		cpu->cd.sh.int_to_assert = irq_nr;
+		cpu->cd.sh.int_level = prio;
+	}
+}
+
+
+/*
+ *  sh_cpu_interrupt_deassert():
+ */
+void sh_cpu_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct cpu *cpu = (struct cpu *) interrupt->extra;
+	int irq_nr = interrupt->line;
+	int index = irq_nr / 0x20;
+
+	/*  Deassert the interrupt:  */
+	if (cpu->cd.sh.int_prio_and_pending[index] & SH_INT_ASSERTED) {
+		cpu->cd.sh.int_prio_and_pending[index] &= ~SH_INT_ASSERTED;
+
+		/*  Calculate new interrupt assertion:  */
+		cpu->cd.sh.int_to_assert = 0;
+		cpu->cd.sh.int_level = 0;
+
+		/*  NOTE/TODO: This is slow, but should hopefully work:  */
+		for (index=0; index<0x1000/0x20; index++) {
+			uint8_t x = cpu->cd.sh.int_prio_and_pending[index];
+			uint8_t prio = x & SH_INT_PRIO_MASK;
+			if (x & SH_INT_ASSERTED &&
+			    prio > cpu->cd.sh.int_level) {
+				cpu->cd.sh.int_to_assert = index * 0x20;
+				cpu->cd.sh.int_level = prio;
+			}
+		}
+	}
+}
+
+
+/*
+ *  sh_cpu_list_available_types():
+ *
+ *  Print a list of available SH CPU types.
+ */
+void sh_cpu_list_available_types(void)
+{
+	int i = 0, j;
+	struct sh_cpu_type_def tdefs[] = SH_CPU_TYPE_DEFS;
+
+	while (tdefs[i].name != NULL) {
+		debug("%s", tdefs[i].name);
+		for (j=10 - strlen(tdefs[i].name); j>0; j--)
+			debug(" ");
+		i ++;
+		if ((i % 6) == 0 || tdefs[i].name == NULL)
+			debug("\n");
+	}
+}
+
+
+/*
+ *  sh_cpu_dumpinfo():
+ */
+void sh_cpu_dumpinfo(struct cpu *cpu, bool verbose)
+{
+	debugmsg(SUBSYS_MACHINE, "cpu", VERBOSITY_INFO,
+	    "%s (%s-endian)",
+	    cpu->name,
+	    cpu->byte_order == EMUL_BIG_ENDIAN? "Big" : "Little");
+}
+
+
+/*
+ *  sh_cpu_instruction_has_delayslot():
+ *
+ *  Return 1 if an opcode is a branch, 0 otherwise.
+ */
+int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
+{
+	uint16_t iword = *((uint16_t *)&ib[0]);
+	int hi4, lo8; // , lo4
+
+	if (!cpu->is_32bit)
+		return 0;
+
+	if (cpu->byte_order == EMUL_BIG_ENDIAN)
+		iword = BE16_TO_HOST(iword);
+	else
+		iword = LE16_TO_HOST(iword);
+
+	hi4 = iword >> 12;
+	lo8 = iword & 255;
+	// lo4 = iword & 15;
+
+        switch (hi4) {
+	case 0x0:
+		if (iword == 0x000b)	/*  rts  */
+			return 1;
+		if (iword == 0x002b)	/*  rte  */
+			return 1;
+		if (lo8 == 0x03)	/*  bsrf  */
+			return 1;
+		if (lo8 == 0x23)	/*  braf  */
+			return 1;
+		break;
+	case 0x4:
+		switch (lo8) {
+		case 0x0b:	/*  jsr  */
+		case 0x2b:	/*  jmp  */
+			return 1;
+		}
+		break;
+	case 0x8:
+		switch ((iword >> 8) & 0xf) {
+		case 0xd:	/*  bt/s  */
+		case 0xf:	/*  bf/s  */
+			return 1;
+		}
+		break;
+	case 0xa:	/*  bra  */
+	case 0xb:	/*  bsr  */
+		return 1;
+	}
+
+	return 0;
+}
+
+
+/*
+ *  sh_cpu_register_dump():
+ *
+ *  Dump cpu registers in a relatively readable format.
+ *
+ *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
+ *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
+ */
+void sh_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
+{
+	char *symbol;
+	uint64_t offset;
+	int i, x = cpu->cpu_id;
+
+	if (gprs) {
+		/*  Special registers (pc, ...) first:  */
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    cpu->pc, &offset);
+
+		debug("cpu%i: pc  = 0x%08" PRIx32, x, (uint32_t)cpu->pc);
+		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
+
+		debug("cpu%i: sr  = 0x%08" PRIx32"  (%s, %s, %s, %s, %s, %s,"
+		    " imask=0x%x, %s, %s)\n", x, (int32_t)cpu->cd.sh.sr,
+		    (cpu->cd.sh.sr & SH_SR_MD)? "MD" : "!md",
+		    (cpu->cd.sh.sr & SH_SR_RB)? "RB" : "!rb",
+		    (cpu->cd.sh.sr & SH_SR_BL)? "BL" : "!bl",
+		    (cpu->cd.sh.sr & SH_SR_FD)? "FD" : "!fd",
+		    (cpu->cd.sh.sr & SH_SR_M)? "M" : "!m",
+		    (cpu->cd.sh.sr & SH_SR_Q)? "Q" : "!q",
+		    (cpu->cd.sh.sr & SH_SR_IMASK) >> SH_SR_IMASK_SHIFT,
+		    (cpu->cd.sh.sr & SH_SR_S)? "S" : "!s",
+		    (cpu->cd.sh.sr & SH_SR_T)? "T" : "!t");
+
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    cpu->cd.sh.pr, &offset);
+		debug("cpu%i: pr  = 0x%08" PRIx32, x, (uint32_t)cpu->cd.sh.pr);
+		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
+
+		debug("cpu%i: mach = 0x%08" PRIx32"  macl = 0x%08" PRIx32
+		    "  gbr = 0x%08" PRIx32"\n", x, (uint32_t)cpu->cd.sh.mach,
+		    (uint32_t)cpu->cd.sh.macl, (uint32_t)cpu->cd.sh.gbr);
+
+		for (i=0; i<SH_N_GPRS; i++) {
+			if ((i % 4) == 0)
+				debug("cpu%i:", x);
+			debug(" r%-2i = 0x%08x ", i, (int)cpu->cd.sh.r[i]);
+			if ((i % 4) == 3)
+				debug("\n");
+		}
+	}
+
+	if (coprocs & 1) {
+		/*  Floating point:  */
+		debug("cpu%i: fpscr = 0x%08" PRIx32" (%s,%s,%s)  fpul = 0x%08"
+		    PRIx32"\n", x, cpu->cd.sh.fpscr,
+		    cpu->cd.sh.fpscr & SH_FPSCR_PR? "PR" : "!pr",
+		    cpu->cd.sh.fpscr & SH_FPSCR_SZ? "SZ" : "!sz",
+		    cpu->cd.sh.fpscr & SH_FPSCR_FR? "FR" : "!fr",
+		    cpu->cd.sh.fpul);
+
+		for (i=0; i<SH_N_FPRS; i++) {
+			if ((i % 4) == 0)
+				debug("cpu%i:", x);
+			debug(" fr%-2i=0x%08x ", i, (int)cpu->cd.sh.fr[i]);
+			if ((i % 4) == 3)
+				debug("\n");
+		}
+
+		for (i=0; i<SH_N_FPRS; i++) {
+			if ((i % 4) == 0)
+				debug("cpu%i:", x);
+			debug(" xf%-2i=0x%08x ", i, (int)cpu->cd.sh.xf[i]);
+			if ((i % 4) == 3)
+				debug("\n");
+		}
+	}
+
+	if (coprocs & 2) {
+		/*  System registers, etc:  */
+		debug("cpu%i: vbr = 0x%08" PRIx32"  sgr = 0x%08" PRIx32
+		    "  dbr = 0x%08" PRIx32"\n", x, cpu->cd.sh.vbr, cpu->cd.sh.sgr,
+		    cpu->cd.sh.dbr);
+		debug("cpu%i: spc = 0x%08" PRIx32"  ssr = 0x%08" PRIx32"\n",
+		    x, cpu->cd.sh.spc, cpu->cd.sh.ssr);
+		debug("cpu%i: expevt = 0x%" PRIx32"  intevt = 0x%" PRIx32
+		    "  tra = 0x%" PRIx32"\n", x, cpu->cd.sh.expevt,
+		    cpu->cd.sh.intevt, cpu->cd.sh.tra);
+
+		for (i=0; i<SH_N_GPRS_BANKED; i++) {
+			if ((i % 2) == 0)
+				debug("cpu%i:", x);
+			debug(" r%i_bank = 0x%08x ", i,
+			    (int)cpu->cd.sh.r_bank[i]);
+			if ((i % 2) == 1)
+				debug("\n");
+		}
+	}
+}
+
+
+/*
+ *  sh_cpu_tlbdump():
+ *
+ *  Called from the debugger to dump the TLB in a readable format.
+ *
+ *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
+ *  just dumped.
+ */
+void sh_cpu_tlbdump(struct cpu* cpu, int rawflag)
+{
+	int i, j;
+	struct machine* m = cpu->machine;
+
+	for (j=0; j<m->ncpus; j++) {
+		if (cpu != m->cpus[j])
+			continue;
+
+		for (i=0; i<SH_N_ITLB_ENTRIES; i++)
+			printf("cpu%i: itlb_hi_%-2i = 0x%08" PRIx32"  "
+			    "itlb_lo_%-2i = 0x%08" PRIx32"\n", j, i,
+			    (uint32_t) cpu->cd.sh.itlb_hi[i], i,
+			    (uint32_t) cpu->cd.sh.itlb_lo[i]);
+		for (i=0; i<SH_N_UTLB_ENTRIES; i++)
+			printf("cpu%i: utlb_hi_%-2i = 0x%08" PRIx32"  "
+			    "utlb_lo_%-2i = 0x%08" PRIx32"\n", j, i,
+			    (uint32_t) cpu->cd.sh.utlb_hi[i], i,
+			    (uint32_t) cpu->cd.sh.utlb_lo[i]);
+	}
+}
+
+
+/*
+ *  sh_update_sr():
+ *
+ *  Writes a new value to the status register.
+ */
+void sh_update_sr(struct cpu *cpu, uint32_t new_sr)
+{
+	uint32_t old_sr = cpu->cd.sh.sr;
+
+	if ((new_sr & SH_SR_RB) != (old_sr & SH_SR_RB)) {
+		int i;
+		for (i=0; i<SH_N_GPRS_BANKED; i++) {
+			uint32_t tmp = cpu->cd.sh.r[i];
+			cpu->cd.sh.r[i] = cpu->cd.sh.r_bank[i];
+			cpu->cd.sh.r_bank[i] = tmp;
+		}
+	}
+
+	cpu->cd.sh.sr = new_sr;
+}
+
+
+/*
+ *  sh_update_fpscr():
+ *
+ *  Writes a new value to the floating-point status/control register.
+ */
+void sh_update_fpscr(struct cpu *cpu, uint32_t new_fpscr)
+{
+	uint32_t old_fpscr = cpu->cd.sh.fpscr;
+
+	if ((new_fpscr & SH_FPSCR_FR) != (old_fpscr & SH_FPSCR_FR)) {
+		int i;
+		for (i=0; i<SH_N_FPRS; i++) {
+			uint32_t tmp = cpu->cd.sh.fr[i];
+			cpu->cd.sh.fr[i] = cpu->cd.sh.xf[i];
+			cpu->cd.sh.xf[i] = tmp;
+		}
+	}
+
+	cpu->cd.sh.fpscr = new_fpscr;
+}
+
+
+/*
+ *  sh_exception():
+ *
+ *  Causes a transfer of control to an exception or interrupt handler.
+ *  If intevt > 0, then it is an interrupt, otherwise an exception.
+ *
+ *  vaddr contains the faulting address, on TLB exceptions.
+ */
+void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr)
+{
+	uint32_t vbr = cpu->cd.sh.vbr;
+
+	if (!quiet_mode) {
+		if (intevt > 0)
+			debug("[ interrupt 0x%03x", intevt);
+		else
+			debug("[ exception 0x%03x", expevt);
+
+		debug(", pc=0x%08" PRIx32" ", (uint32_t)cpu->pc);
+		if (intevt == 0)
+			debug("vaddr=0x%08" PRIx32" ", vaddr);
+
+		debug(" ]\n");
+	}
+
+	if (cpu->cd.sh.sr & SH_SR_BL) {
+		fatal("[ sh_exception(): BL bit already set. ]\n");
+
+		/*  This is actually OK in two cases: a User Break,
+		    or on NMI interrupts if a special flag is set?  */
+		/*  TODO  */
+
+		expevt = EXPEVT_RESET_POWER;
+	}
+
+	if (cpu->is_halted) {
+		/*
+		 *  If the exception occurred on a 'sleep' instruction, then let
+		 *  the instruction following the sleep instruction be the one
+		 *  where execution resumes when the interrupt service routine
+		 *  returns.
+		 */
+		cpu->is_halted = false;
+		cpu->pc += sizeof(uint16_t);
+	}
+
+	if (cpu->delay_slot) {
+		cpu->delay_slot = EXCEPTION_IN_DELAY_SLOT;
+		cpu->pc -= sizeof(uint16_t);
+	}
+
+
+	/*
+	 *  Stuff common to all exceptions:
+	 */
+
+	cpu->cd.sh.spc = cpu->pc;
+	cpu->cd.sh.ssr = cpu->cd.sh.sr;
+	cpu->cd.sh.sgr = cpu->cd.sh.r[15];
+
+	if (intevt > 0) {
+		cpu->cd.sh.intevt = intevt;
+		expevt = -1;
+	} else {
+		cpu->cd.sh.expevt = expevt;
+	}
+
+	sh_update_sr(cpu, cpu->cd.sh.sr | SH_SR_MD | SH_SR_RB | SH_SR_BL);
+
+	/*  Most exceptions set PC to VBR + 0x100.  */
+	cpu->pc = vbr + 0x100;
+
+
+	/*  Specific cases:  */
+	switch (expevt) {
+
+	case -1:	/*  Interrupt  */
+		cpu->pc = vbr + 0x600;
+		break;
+
+	case EXPEVT_RESET_POWER:
+	case EXPEVT_RESET_MANUAL:
+		cpu->pc = 0xa0000000;
+		cpu->cd.sh.vbr = 0x00000000;
+		sh_update_sr(cpu, (cpu->cd.sh.sr | SH_SR_IMASK) & ~SH_SR_FD);
+		break;
+
+	case EXPEVT_TLB_MISS_LD:
+	case EXPEVT_TLB_MISS_ST:
+		cpu->pc = vbr + 0x400;
+		// fall through
+	case EXPEVT_TLB_PROT_LD:
+	case EXPEVT_TLB_PROT_ST:
+	case EXPEVT_TLB_MOD:
+		cpu->cd.sh.tea = vaddr;
+		cpu->cd.sh.pteh &= ~SH4_PTEH_VPN_MASK;
+		cpu->cd.sh.pteh |= (vaddr & SH4_PTEH_VPN_MASK);
+		break;
+
+	case EXPEVT_TRAPA:
+		/*
+		 *  Note: The TRA register is already set by the implementation
+		 *  of the trapa instruction. See cpu_sh_instr.c for details.
+		 *  Here, spc is incremented, so that a return from the trap
+		 *  handler transfers control to the instruction _following_
+		 *  the trapa.
+		 */
+		cpu->cd.sh.spc += sizeof(uint16_t);
+		break;
+
+	case EXPEVT_RES_INST:
+		/*
+		 *  Note: Having this code here makes it possible to catch
+		 *  reserved instructions; during normal instruction execution,
+		 *  these are not very common.
+		 */
+#if 1
+		printf("\nRESERVED SuperH instruction at spc=%08" PRIx32"\n",
+		    cpu->cd.sh.spc);
+		exit(1);
+#else
+		break;
+#endif
+
+	case EXPEVT_FPU_DISABLE:
+		break;
+
+	default:fatal("sh_exception(): exception 0x%x is not yet "
+		    "implemented.\n", expevt);
+		exit(1);
+	}
+
+	sh_pc_to_pointers(cpu);
+}
+
+
+/*
+ *  sh_cpu_disassemble_instr():
+ *
+ *  SHcompact instruction disassembly. The top 4 bits of each 16-bit
+ *  instruction word is used as the main opcode. For most instructions, the
+ *  lowest 4 or 8 bits then select sub-opcode.
+ *
+ *  This function convert an instruction word into human readable format,
+ *  for instruction tracing.
+ *
+ *  If running is 1, cpu->pc should be the address of the instruction.
+ *
+ *  If running is 0, things that depend on the runtime environment (eg.
+ *  register contents) will not be shown, and addr will be used instead of
+ *  cpu->pc for relative addresses.
+ */
+int sh_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
+	int running, uint64_t dumpaddr)
+{
+	char *symbol;
+	uint64_t offset, addr;
+	uint16_t iword;
+
+	if (running)
+		dumpaddr = cpu->pc;
+
+	symbol = get_symbol_name(&cpu->machine->symbol_context,
+	    dumpaddr, &offset);
+	if (symbol != NULL && offset==0)
+		debug("<%s>\n", symbol);
+
+	if (cpu->machine->ncpus > 1 && running)
+		debug("cpu%i: ", cpu->cpu_id);
+
+	debug("%08" PRIx32, (uint32_t) dumpaddr);
+
+	if (cpu->byte_order == EMUL_BIG_ENDIAN)
+		iword = (instr[0] << 8) + instr[1];
+	else
+		iword = (instr[1] << 8) + instr[0];
+
+	debug(":  %04x %s", iword, cpu->delay_slot? "(d)" : "   ");
+
+	cpu_print_pc_indicator_in_disassembly(cpu, running, dumpaddr);
+
+	const int hi4 = iword >> 12, lo4 = iword & 15, lo8 = iword & 255;
+	int r8 = (iword >> 8) & 15, r4 = (iword >> 4) & 15;
+
+
+	/*
+	 *  Decode the instruction:
+	 */
+
+	switch (hi4) {
+	case 0x0:
+		if (lo8 == 0x02)
+			debug("stc\tsr,r%i\n", r8);
+		else if (lo8 == 0x03)
+			debug("bsrf\tr%i\n", r8);
+		else if (lo4 >= 4 && lo4 <= 6) {
+			if (lo4 == 0x4)
+				debug("mov.b\tr%i,@(r0,r%i)", r4, r8);
+			else if (lo4 == 0x5)
+				debug("mov.w\tr%i,@(r0,r%i)", r4, r8);
+			else if (lo4 == 0x6)
+				debug("mov.l\tr%i,@(r0,r%i)", r4, r8);
+			if (running) {
+				addr = cpu->cd.sh.r[0] + cpu->cd.sh.r[r8];
+				debug("\t; r0+r%i = ", r8);
+				symbol = get_symbol_name(
+				    &cpu->machine->symbol_context,
+				    addr, &offset);
+				if (symbol != NULL)
+					debug("<%s>", symbol);
+				else
+					debug("0x%08" PRIx32, addr);
+			}
+			debug("\n");
+		} else if (lo4 == 0x7)
+			debug("mul.l\tr%i,r%i\n", r4, r8);
+		else if (iword == 0x0008)
+			debug("clrt\n");
+		else if (iword == 0x0009)
+			debug("nop\n");
+		else if (lo8 == 0x0a)
+			debug("sts\tmach,r%i\n", r8);
+		else if (iword == 0x000b)
+			debug("rts\n");
+		else if (lo4 >= 0xc && lo4 <= 0xe) {
+			if (lo4 == 0xc)
+				debug("mov.b\t@(r0,r%i),r%i", r4, r8);
+			else if (lo4 == 0xd)
+				debug("mov.w\t@(r0,r%i),r%i", r4, r8);
+			else if (lo4 == 0xe)
+				debug("mov.l\t@(r0,r%i),r%i", r4, r8);
+			if (running) {
+				addr = cpu->cd.sh.r[0] + cpu->cd.sh.r[r4];
+				debug("\t; r0+r%i = ", r4);
+				symbol = get_symbol_name(
+				    &cpu->machine->symbol_context,
+				    addr, &offset);
+				if (symbol != NULL)
+					debug("<%s>", symbol);
+				else
+					debug("0x%08" PRIx32, addr);
+			}
+			debug("\n");
+		} else if (lo8 == 0x12)
+			debug("stc\tgbr,r%i\n", r8);
+		else if (iword == 0x0018)
+			debug("sett\n");
+		else if (iword == 0x0019)
+			debug("div0u\n");
+		else if (lo8 == 0x1a)
+			debug("sts\tmacl,r%i\n", r8);
+		else if (iword == 0x001b)
+			debug("sleep\n");
+		else if (lo8 == 0x22)
+			debug("stc\tvbr,r%i\n", r8);
+		else if (lo8 == 0x23)
+			debug("braf\tr%i\n", r8);
+		else if (iword == 0x0028)
+			debug("clrmac\n");
+		else if (lo8 == 0x29)
+			debug("movt\tr%i\n", r8);
+		else if (lo8 == 0x2a)
+			debug("sts\tpr,r%i\n", r8);
+		else if (iword == 0x002b)
+			debug("rte\n");
+		else if (lo8 == 0x32)
+			debug("stc\tssr,r%i\n", r8);
+		else if (iword == 0x0038)
+			debug("ldtlb\n");
+		else if (iword == 0x003b)
+			debug("brk\n");
+		else if (lo8 == 0x42)
+			debug("stc\tspc,r%i\n", r8);
+		else if (iword == 0x0048)
+			debug("clrs\n");
+		else if (iword == 0x0058)
+			debug("sets\n");
+		else if (lo8 == 0x5a)
+			debug("sts\tfpul,r%i\n", r8);
+		else if (lo8 == 0x6a)
+			debug("sts\tfpscr,r%i\n", r8);
+		else if ((lo8 & 0x8f) == 0x82)
+			debug("stc\tr%i_bank,r%i\n", (lo8 >> 4) & 7, r8);
+		else if (lo8 == 0x83)
+			debug("pref\t@r%i\n", r8);
+		else if (lo8 == 0x93)
+			debug("ocbi\t@r%i\n", r8);
+		else if (lo8 == 0xa3)
+			debug("ocbp\t@r%i\n", r8);
+		else if (lo8 == 0xb3)
+			debug("ocbwb\t@r%i\n", r8);
+		else if (lo8 == 0xc3)
+			debug("movca.l\tr0,@r%i\n", r8);
+		else if (lo8 == 0xfa)
+			debug("stc\tdbr,r%i\n", r8);
+		else if (iword == SH_INVALID_INSTR)
+			debug("gxemul_dreamcast_prom_emul\n");
+		else
+			debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
+		break;
+	case 0x1:
+		debug("mov.l\tr%i,@(%i,r%i)", r4, lo4 * 4, r8);
+		if (running) {
+			addr = cpu->cd.sh.r[r8] + lo4 * 4;
+			debug("\t; r%i+%i = ", r8, lo4 * 4);
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    addr, &offset);
+			if (symbol != NULL)
+				debug("<%s>", symbol);
+			else
+				debug("0x%08" PRIx32, addr);
+		}
+		debug("\n");
+		break;
+	case 0x2:
+		if (lo4 == 0x0)
+			debug("mov.b\tr%i,@r%i", r4, r8);
+		else if (lo4 == 0x1)
+			debug("mov.w\tr%i,@r%i", r4, r8);
+		else if (lo4 == 0x2)
+			debug("mov.l\tr%i,@r%i", r4, r8);
+		else if (lo4 == 0x4)
+			debug("mov.b\tr%i,@-r%i", r4, r8);
+		else if (lo4 == 0x5)
+			debug("mov.w\tr%i,@-r%i", r4, r8);
+		else if (lo4 == 0x6)
+			debug("mov.l\tr%i,@-r%i", r4, r8);
+		else if (lo4 == 0x7)
+			debug("div0s\tr%i,r%i", r4, r8);
+		else if (lo4 == 0x8)
+			debug("tst\tr%i,r%i", r4, r8);
+		else if (lo4 == 0x9)
+			debug("and\tr%i,r%i", r4, r8);
+		else if (lo4 == 0xa)
+			debug("xor\tr%i,r%i", r4, r8);
+		else if (lo4 == 0xb)
+			debug("or\tr%i,r%i", r4, r8);
+		else if (lo4 == 0xc)
+			debug("cmp/str\tr%i,r%i", r4, r8);
+		else if (lo4 == 0xd)
+			debug("xtrct\tr%i,r%i", r4, r8);
+		else if (lo4 == 0xe)
+			debug("mulu.w\tr%i,r%i", r4, r8);
+		else if (lo4 == 0xf)
+			debug("muls.w\tr%i,r%i", r4, r8);
+		else
+			debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x", hi4, lo8);
+		if (running && lo4 <= 6) {
+			debug("\t; r%i = 0x%08" PRIx32, r8, cpu->cd.sh.r[r8]);
+		}
+		debug("\n");
+		break;
+	case 0x3:
+		if (lo4 == 0x0)
+			debug("cmp/eq\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0x2)
+			debug("cmp/hs\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0x3)
+			debug("cmp/ge\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0x4)
+			debug("div1\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0x5)
+			debug("dmulu.l\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0x6)
+			debug("cmp/hi\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0x7)
+			debug("cmp/gt\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0x8)
+			debug("sub\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0xa)
+			debug("subc\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0xb)
+			debug("subv\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0xc)
+			debug("add\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0xd)
+			debug("dmuls.l\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0xe)
+			debug("addc\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0xf)
+			debug("addv\tr%i,r%i\n", r4, r8);
+		else
+			debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
+		break;
+	case 0x4:
+		if (lo8 == 0x00)
+			debug("shll\tr%i\n", r8);
+		else if (lo8 == 0x01)
+			debug("shlr\tr%i\n", r8);
+		else if (lo8 == 0x02)
+			debug("sts.l\tmach,@-r%i\n", r8);
+		else if (lo8 == 0x03)
+			debug("stc.l\tsr,@-r%i\n", r8);
+		else if (lo8 == 0x04)
+			debug("rotl\tr%i\n", r8);
+		else if (lo8 == 0x05)
+			debug("rotr\tr%i\n", r8);
+		else if (lo8 == 0x06)
+			debug("lds.l\t@r%i+,mach\n", r8);
+		else if (lo8 == 0x07)
+			debug("ldc.l\t@r%i+,sr\n", r8);
+		else if (lo8 == 0x08)
+			debug("shll2\tr%i\n", r8);
+		else if (lo8 == 0x09)
+			debug("shlr2\tr%i\n", r8);
+		else if (lo8 == 0x0a)
+			debug("lds\tr%i,mach\n", r8);
+		else if (lo8 == 0x0b)
+			debug("jsr\t@r%i\n", r8);
+		else if (lo4 == 0xc)
+			debug("shad\tr%i,r%i\n", r4, r8);
+		else if (lo4 == 0xd)
+			debug("shld\tr%i,r%i\n", r4, r8);
+		else if (lo8 == 0x0e)
+			debug("ldc\tr%i,sr\n", r8);
+		else if (lo8 == 0x10)
+			debug("dt\tr%i\n", r8);
+		else if (lo8 == 0x11)
+			debug("cmp/pz\tr%i\n", r8);
+		else if (lo8 == 0x12)
+			debug("sts.l\tmacl,@-r%i\n", r8);
+		else if (lo8 == 0x13)
+			debug("stc.l\tgbr,@-r%i\n", r8);
+		else if (lo8 == 0x15)
+			debug("cmp/pl\tr%i\n", r8);
+		else if (lo8 == 0x16)
+			debug("lds.l\t@r%i+,macl\n", r8);
+		else if (lo8 == 0x17)
+			debug("ldc.l\t@r%i+,gbr\n", r8);
+		else if (lo8 == 0x18)
+			debug("shll8\tr%i\n", r8);
+		else if (lo8 == 0x19)
+			debug("shlr8\tr%i\n", r8);
+		else if (lo8 == 0x1a)
+			debug("lds\tr%i,macl\n", r8);
+		else if (lo8 == 0x1b)
+			debug("tas.b\t@r%i\n", r8);
+		else if (lo8 == 0x1e)
+			debug("ldc\tr%i,gbr\n", r8);
+		else if (lo8 == 0x20)
+			debug("shal\tr%i\n", r8);
+		else if (lo8 == 0x21)
+			debug("shar\tr%i\n", r8);
+		else if (lo8 == 0x22)
+			debug("sts.l\tpr,@-r%i\n", r8);
+		else if (lo8 == 0x23)
+			debug("stc.l\tvbr,@-r%i\n", r8);
+		else if (lo8 == 0x24)
+			debug("rotcl\tr%i\n", r8);
+		else if (lo8 == 0x25)
+			debug("rotcr\tr%i\n", r8);
+		else if (lo8 == 0x26)
+			debug("lds.l\t@r%i+,pr\n", r8);
+		else if (lo8 == 0x27)
+			debug("ldc.l\t@r%i+,vbr\n", r8);
+		else if (lo8 == 0x28)
+			debug("shll16\tr%i\n", r8);
+		else if (lo8 == 0x29)
+			debug("shlr16\tr%i\n", r8);
+		else if (lo8 == 0x2a)
+			debug("lds\tr%i,pr\n", r8);
+		else if (lo8 == 0x2b) {
+			debug("jmp\t@r%i", r8);
+			if (running) {
+				symbol = get_symbol_name(
+				    &cpu->machine->symbol_context,
+				    cpu->cd.sh.r[r8], &offset);
+				if (symbol != NULL)
+					debug("\t\t; <%s>", symbol);
+			}
+			debug("\n");
+		} else if (lo8 == 0x2e)
+			debug("ldc\tr%i,vbr\n", r8);
+		else if (lo8 == 0x33)
+			debug("stc.l\tssr,@-r%i\n", r8);
+		else if (lo8 == 0x37)
+			debug("ldc.l\t@r%i+,ssr\n", r8);
+		else if (lo8 == 0x3e)
+			debug("ldc\tr%i,ssr\n", r8);
+		else if (lo8 == 0x43)
+			debug("stc.l\tspc,@-r%i\n", r8);
+		else if (lo8 == 0x47)
+			debug("ldc.l\t@r%i+,spc\n", r8);
+		else if (lo8 == 0x4e)
+			debug("ldc\tr%i,spc\n", r8);
+		else if (lo8 == 0x52)
+			debug("sts.l\tfpul,@-r%i\n", r8);
+		else if (lo8 == 0x56)
+			debug("lds.l\t@r%i+,fpul\n", r8);
+		else if (lo8 == 0x5a)
+			debug("lds\tr%i,fpul\n", r8);
+		else if (lo8 == 0x62)
+			debug("sts.l\tfpscr,@-r%i\n", r8);
+		else if (lo8 == 0x66)
+			debug("lds.l\t@r%i+,fpscr\n", r8);
+		else if (lo8 == 0x6a)
+			debug("lds\tr%i,fpscr\n", r8);
+		else if ((lo8 & 0x8f) == 0x83)
+			debug("stc.l\tr%i_bank,@-r%i\n", (lo8 >> 4) & 7, r8);
+		else if ((lo8 & 0x8f) == 0x87)
+			debug("ldc.l\t@r%i,r%i_bank\n", r8, (lo8 >> 4) & 7, r8);
+		else if ((lo8 & 0x8f) == 0x8e)
+			debug("ldc\tr%i,r%i_bank\n", r8, (lo8 >> 4) & 7);
+		else if (lo8 == 0xfa)
+			debug("ldc\tr%i,dbr\n", r8);
+		else
+			debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
+		break;
+	case 0x5:
+		debug("mov.l\t@(%i,r%i),r%i", lo4 * 4, r4, r8);
+		if (running) {
+			addr = cpu->cd.sh.r[r4] + lo4 * 4;
+			symbol = get_symbol_name(&cpu->machine->symbol_context, addr, &offset);
+			if (symbol != NULL)
+				debug("\t; r%i+%i <%s>", r4, lo4 * 4, symbol);
+			else
+				debug("\t; r%i+%i = 0x%08" PRIx32, r4, lo4 * 4, (int)addr);
+		}
+		debug("\n");
+		break;
+	case 0x6:
+		if (lo4 == 0x0)
+			debug("mov.b\t@r%i,r%i", r4, r8);
+		else if (lo4 == 0x1)
+			debug("mov.w\t@r%i,r%i", r4, r8);
+		else if (lo4 == 0x2)
+			debug("mov.l\t@r%i,r%i", r4, r8);
+		else if (lo4 == 0x3)
+			debug("mov\tr%i,r%i", r4, r8);
+		else if (lo4 == 0x4)
+			debug("mov.b\t@r%i+,r%i", r4, r8);
+		else if (lo4 == 0x5)
+			debug("mov.w\t@r%i+,r%i", r4, r8);
+		else if (lo4 == 0x6)
+			debug("mov.l\t@r%i+,r%i", r4, r8);
+		else if (lo4 == 0x7)
+			debug("not\tr%i,r%i", r4, r8);
+		else if (lo4 == 0x8)
+			debug("swap.b\tr%i,r%i", r4, r8);
+		else if (lo4 == 0x9)
+			debug("swap.w\tr%i,r%i", r4, r8);
+		else if (lo4 == 0xa)
+			debug("negc\tr%i,r%i", r4, r8);
+		else if (lo4 == 0xb)
+			debug("neg\tr%i,r%i", r4, r8);
+		else if (lo4 == 0xc)
+			debug("extu.b\tr%i,r%i", r4, r8);
+		else if (lo4 == 0xd)
+			debug("extu.w\tr%i,r%i", r4, r8);
+		else if (lo4 == 0xe)
+			debug("exts.b\tr%i,r%i", r4, r8);
+		else if (lo4 == 0xf)
+			debug("exts.w\tr%i,r%i", r4, r8);
+		else
+			debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x", hi4, lo8);
+		if (running && lo4 < 8 && (lo4 & 3) < 3) {
+			debug("\t; r%i = 0x%08" PRIx32, r4, cpu->cd.sh.r[r4]);
+		}
+		debug("\n");
+		break;
+	case 0x7:
+		debug("add\t#%i,r%i\n", (int8_t)lo8, r8);
+		break;
+	case 0x8:
+		if (r8 == 0 || r8 == 4) {
+			if (r8 == 0x0)
+				debug("mov.b\tr0,@(%i,r%i)", lo4, r4);
+			else if (r8 == 0x4)
+				debug("mov.b\t@(%i,r%i),r0", lo4, r4);
+			if (running) {
+				debug("\t; r%i+%i = 0x%08" PRIx32, r4, lo4,
+				    cpu->cd.sh.r[r4] + lo4);
+			}
+			debug("\n");
+		} else if (r8 == 1 || r8 == 5) {
+			if (r8 == 0x1)
+				debug("mov.w\tr0,@(%i,r%i)", lo4 * 2, r4);
+			else if (r8 == 0x5)
+				debug("mov.w\t@(%i,r%i),r0", lo4 * 2, r4);
+			if (running) {
+				debug("\t; r%i+%i = 0x%08" PRIx32, r4, lo4 * 2,
+				    cpu->cd.sh.r[r4] + lo4 * 2);
+			}
+			debug("\n");
+		} else if (r8 == 0x8) {
+			debug("cmp/eq\t#%i,r0\n", (int8_t)lo8);
+		} else if (r8 == 0x9 || r8 == 0xb || r8 == 0xd || r8 == 0xf) {
+			addr = (int8_t)lo8;
+			addr = dumpaddr + 4 + (addr << 1);
+			debug("b%s%s\t0x%x",
+			    (r8 == 0x9 || r8 == 0xd)? "t" : "f",
+			    (r8 == 0x9 || r8 == 0xb)? "" : "/s", (int)addr);
+			symbol = get_symbol_name(&cpu->machine->symbol_context,
+			    addr, &offset);
+			if (symbol != NULL)
+				debug("\t; <%s>", symbol);
+			debug("\n");
+		} else
+			debug("UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, r8);
+		break;
+	case 0x9:
+	case 0xd:
+		addr = lo8 * (hi4==9? 2 : 4);
+		addr += (dumpaddr & ~(hi4==9? 1 : 3)) + 4;
+		debug("mov.%s\t0x%x,r%i", hi4==9? "w":"l", (int)addr, r8);
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    addr, &offset);
+		if (symbol != NULL)
+			debug("\t; <%s>", symbol);
+		debug("\n");
+		break;
+	case 0xa:
+	case 0xb:
+		addr = (int32_t)(int16_t)((iword & 0xfff) << 4);
+		addr = ((int32_t)addr >> 3);
+		addr += dumpaddr + 4;
+		debug("%s\t0x%x", hi4==0xa? "bra":"bsr", (int)addr);
+
+		symbol = get_symbol_name(&cpu->machine->symbol_context,
+		    addr, &offset);
+		if (symbol != NULL)
+			debug("\t; <%s>", symbol);
+		debug("\n");
+		break;
+	case 0xc:
+		if (r8 == 0x0)
+			debug("mov.b\tr0,@(%i,gbr)\n", lo8);
+		else if (r8 == 0x1)
+			debug("mov.w\tr0,@(%i,gbr)\n", lo8 * 2);
+		else if (r8 == 0x2)
+			debug("mov.l\tr0,@(%i,gbr)\n", lo8 * 4);
+		else if (r8 == 0x3)
+			debug("trapa\t#%i\n", (uint8_t)lo8);
+		else if (r8 == 0x4)
+			debug("mov.b\t(%i,gbr),r0\n", lo8);
+		else if (r8 == 0x5)
+			debug("mov.w\t(%i,gbr),r0\n", lo8 * 2);
+		else if (r8 == 0x6)
+			debug("mov.l\t(%i,gbr),r0\n", lo8 * 4);
+		else if (r8 == 0x7) {
+			addr = lo8 * 4 + (dumpaddr & ~3) + 4;
+			debug("mova\t0x%x,r0\n", (int)addr);
+		} else if (r8 == 0x8)
+			debug("tst\t#%i,r0\n", (uint8_t)lo8);
+		else if (r8 == 0x9)
+			debug("and\t#%i,r0\n", (uint8_t)lo8);
+		else if (r8 == 0xa)
+			debug("xor\t#%i,r0\n", (uint8_t)lo8);
+		else if (r8 == 0xb)
+			debug("or\t#%i,r0\n", (uint8_t)lo8);
+		else if (r8 == 0xc)
+			debug("tst.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
+		else if (r8 == 0xd)
+			debug("and.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
+		else if (r8 == 0xe)
+			debug("xor.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
+		else if (r8 == 0xf)
+			debug("or.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
+		else
+			debug("UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, r8);
+		break;
+	case 0xe:
+		debug("mov\t#%i,r%i\n", (int8_t)lo8, r8);
+		break;
+	case 0xf:
+		if (lo4 == 0x0)
+			debug("fadd\t%sr%i,%sr%i\n",
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r4,
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
+		else if (lo4 == 0x1)
+			debug("fsub\t%sr%i,%sr%i\n",
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r4,
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
+		else if (lo4 == 0x2)
+			debug("fmul\t%sr%i,%sr%i\n",
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r4,
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
+		else if (lo4 == 0x3)
+			debug("fdiv\t%sr%i,%sr%i\n",
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r4,
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
+		else if (lo4 == 0x4)
+			debug("fcmp/eq\t%sr%i,%sr%i\n",
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r4,
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
+		else if (lo4 == 0x5)
+			debug("fcmp/gt\t%sr%i,%sr%i\n",
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r4,
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
+		else if (lo4 == 0x6) {
+			const char *n = "fr";
+			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
+				n = (r8 & 1)? "xd" : "dr";
+				r8 &= ~1;
+			}
+			debug("fmov\t@(r0,r%i),%s%i\n", r4, n, r8);
+		} else if (lo4 == 0x7) {
+			const char *n = "fr";
+			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
+				n = (r4 & 1)? "xd" : "dr";
+				r4 &= ~1;
+			}
+			debug("fmov\t%s%i,@(r0,r%i)\n", n, r4, r8);
+		} else if (lo4 == 0x8) {
+			const char *n = "fr";
+			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
+				n = (r8 & 1)? "xd" : "dr";
+				r8 &= ~1;
+			}
+			debug("fmov\t@r%i,%s%i\n", r4, n, r8);
+		} else if (lo4 == 0x9) {
+			const char *n = "fr";
+			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
+				n = (r8 & 1)? "xd" : "dr";
+				r8 &= ~1;
+			}
+			debug("fmov\t@r%i+,%s%i\n", r4, n, r8);
+		} else if (lo4 == 0xa) {
+			const char *n = "fr";
+			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
+				n = (r4 & 1)? "xd" : "dr";
+				r4 &= ~1;
+			}
+			debug("fmov\t%s%i,@r%i\n", n, r4, r8);
+		} else if (lo4 == 0xb) {
+			const char *n = "fr";
+			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
+				n = (r4 & 1)? "xd" : "dr";
+				r4 &= ~1;
+			}
+			debug("fmov\t%s%i,@-r%i\n", n, r4, r8);
+		} else if (lo4 == 0xc) {
+			const char *n1 = "fr", *n2 = "fr";
+			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
+				n1 = (r4 & 1)? "xd" : "dr";
+				n2 = (r8 & 1)? "xd" : "dr";
+				r4 &= ~1; r8 &= ~1;
+			}
+			debug("fmov\t%s%i,%s%i\n", n1, r4, n2, r8);
+		} else if (lo8 == 0x0d)
+			debug("fsts\tfpul,fr%i\n", r8);
+		else if (lo8 == 0x1d)
+			debug("flds\tfr%i,fpul\n", r8);
+		else if (lo8 == 0x2d)
+			debug("float\tfpul,%sr%i\n",
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
+		else if (lo8 == 0x3d)
+			debug("ftrc\t%sr%i,fpul\n",
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
+		else if (lo8 == 0x4d)
+			debug("fneg\t%sr%i\n",
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
+		else if (lo8 == 0x5d)
+			debug("fabs\t%sr%i\n",
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
+		else if (lo8 == 0x6d)
+			debug("fsqrt\t%sr%i\n",
+			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
+		else if (lo8 == 0x7d)
+			debug("fsrra\tfr%i\n", r8);
+		else if (lo8 == 0x8d)
+			debug("fldi0\tfr%i\n", r8);
+		else if (lo8 == 0x9d)
+			debug("fldi1\tfr%i\n", r8);
+		else if (lo8 == 0xad)
+			debug("fcnvsd\tfpul,dr%i\n", r8);
+		else if (lo8 == 0xbd)
+			debug("fcnvds\tdr%i,fpul\n", r8);
+		else if (lo8 == 0xed)
+			debug("fipr\tfv%i,fv%i\n", (r8 & 3) << 2, r8 & 0xc);
+		else if ((iword & 0x01ff) == 0x00fd)
+			debug("fsca\tfpul,dr%i\n", r8);
+		else if (iword == 0xf3fd)
+			debug("fschg\n");
+		else if (iword == 0xfbfd)
+			debug("frchg\n");
+		else if ((iword & 0xf3ff) == 0xf1fd)
+			debug("ftrv\txmtrx,fv%i\n", r8 & 0xc);
+		else if (lo4 == 0xe)
+			debug("fmac\tfr0,fr%i,fr%i\n", r4, r8);
+		else
+			debug("UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, lo8);
+		break;
+	default:debug("UNIMPLEMENTED hi4=0x%x\n", hi4);
+	}
+
+	return sizeof(iword);
+}
+
+
+#include "tmp_sh_tail.c"
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_sh.cc gxemul-0.7.0+dfsg/src/cpus/cpu_sh.cc
--- gxemul-0.6.2/src/cpus/cpu_sh.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_sh.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1411 +0,0 @@
-/*
- *  Copyright (C) 2005-2011  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Hitachi SuperH ("SH") CPU emulation.
- *
- *  TODO: It would be nice if this could encompass both 64-bit SH5, and
- *        32-bit SH encodings. Right now, it only really supports 32-bit mode.
- *
- *  TODO: This actually only works or SH4 so far, not SH3.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <ctype.h>
-#include <unistd.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "float_emul.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "settings.h"
-#include "symbol.h"
-
-#include "thirdparty/sh4_exception.h"
-#include "thirdparty/sh4_mmu.h"
-
-
-#define DYNTRANS_32
-#define DYNTRANS_DELAYSLOT
-#include "tmp_sh_head.cc"
-
-
-extern int quiet_mode;
-
-void sh_pc_to_pointers(struct cpu *);
-
-void sh3_cpu_interrupt_assert(struct interrupt *interrupt);
-void sh3_cpu_interrupt_deassert(struct interrupt *interrupt);
-
-
-/*
- *  sh_cpu_new():
- *
- *  Create a new SH cpu object.
- *
- *  Returns 1 on success, 0 if there was no matching SH processor with
- *  this cpu_type_name.
- */
-int sh_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
-	int cpu_id, char *cpu_type_name)
-{
-	int i = 0;
-	struct sh_cpu_type_def cpu_type_defs[] = SH_CPU_TYPE_DEFS;
-
-	/*  Scan the cpu_type_defs list for this cpu type:  */
-	while (cpu_type_defs[i].name != NULL) {
-		if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
-			break;
-		}
-		i++;
-	}
-	if (cpu_type_defs[i].name == NULL)
-		return 0;
-
-	cpu->memory_rw = sh_memory_rw;
-
-	cpu->cd.sh.cpu_type = cpu_type_defs[i];
-	cpu->byte_order = EMUL_LITTLE_ENDIAN;
-	cpu->is_32bit = cpu->cd.sh.cpu_type.bits == 32;
-
-	if (!cpu->is_32bit) {
-		fatal("SH64 emulation not implemented. Sorry.\n");
-		exit(1);
-	}
-
-	cpu->instruction_has_delayslot = sh_cpu_instruction_has_delayslot;
-
-	cpu->translate_v2p = sh_translate_v2p;
-
-	cpu->run_instr = sh_run_instr;
-	cpu->update_translation_table = sh_update_translation_table;
-	cpu->invalidate_translation_caches =
-	    sh_invalidate_translation_caches;
-	cpu->invalidate_code_translation =
-	    sh_invalidate_code_translation;
-
-	/*  Only show name and caches etc for CPU nr 0 (in SMP machines):  */
-	if (cpu_id == 0) {
-		debug("%s", cpu->name);
-	}
-
-	/*  Initial value of FPSCR (according to the SH4 manual):  */
-	cpu->cd.sh.fpscr = 0x00040001;
-
-	/*  (Initial value of the program counter on reboot is 0xA0000000.)  */
-
-	/*  Start in Privileged Mode:  */
-	cpu->cd.sh.sr = SH_SR_MD | SH_SR_IMASK;
-
-	/*  Stack pointer at end of physical RAM:  */
-	cpu->cd.sh.r[15] = cpu->machine->physical_ram_in_mb * 1048576 - 64;
-
-	CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
-	CPU_SETTINGS_ADD_REGISTER32("sr", cpu->cd.sh.sr);
-	CPU_SETTINGS_ADD_REGISTER32("pr", cpu->cd.sh.pr);
-	CPU_SETTINGS_ADD_REGISTER32("vbr", cpu->cd.sh.vbr);
-	CPU_SETTINGS_ADD_REGISTER32("sgr", cpu->cd.sh.sgr);
-	CPU_SETTINGS_ADD_REGISTER32("gbr", cpu->cd.sh.gbr);
-	CPU_SETTINGS_ADD_REGISTER32("dbr", cpu->cd.sh.dbr);
-	CPU_SETTINGS_ADD_REGISTER32("macl", cpu->cd.sh.macl);
-	CPU_SETTINGS_ADD_REGISTER32("mach", cpu->cd.sh.mach);
-	CPU_SETTINGS_ADD_REGISTER32("expevt", cpu->cd.sh.expevt);
-	CPU_SETTINGS_ADD_REGISTER32("intevt", cpu->cd.sh.intevt);
-	CPU_SETTINGS_ADD_REGISTER32("tra", cpu->cd.sh.tra);
-	CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.sh.fpscr);
-	CPU_SETTINGS_ADD_REGISTER32("fpul", cpu->cd.sh.fpul);
-	for (i=0; i<SH_N_GPRS; i++) {
-		char tmpstr[5];
-		snprintf(tmpstr, sizeof(tmpstr), "r%i", i);
-		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.r[i]);
-	}
-	for (i=0; i<SH_N_GPRS_BANKED; i++) {
-		char tmpstr[15];
-		snprintf(tmpstr, sizeof(tmpstr), "r%i_bank", i);
-		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.r_bank[i]);
-	}
-	for (i=0; i<SH_N_FPRS; i++) {
-		char tmpstr[6];
-		snprintf(tmpstr, sizeof(tmpstr), "fr%i", i);
-		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.fr[i]);
-		snprintf(tmpstr, sizeof(tmpstr), "xf%i", i);
-		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.xf[i]);
-	}
-	for (i=0; i<SH_N_ITLB_ENTRIES; i++) {
-		char tmpstr[15];
-		snprintf(tmpstr, sizeof(tmpstr), "itlb_hi_%i", i);
-		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.itlb_hi[i]);
-		snprintf(tmpstr, sizeof(tmpstr), "itlb_lo_%i", i);
-		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.itlb_lo[i]);
-	}
-	for (i=0; i<SH_N_UTLB_ENTRIES; i++) {
-		char tmpstr[15];
-		snprintf(tmpstr, sizeof(tmpstr), "utlb_hi_%i", i);
-		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.utlb_hi[i]);
-		snprintf(tmpstr, sizeof(tmpstr), "utlb_lo_%i", i);
-		CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.utlb_lo[i]);
-	}
-
-	/*  Register the CPU's interrupts:  */
-	if (cpu->cd.sh.cpu_type.arch == 4) {
-		for (i=SH_INTEVT_NMI; i<0x1000; i+=0x20) {
-			struct interrupt templ;
-			char name[100];
-			snprintf(name, sizeof(name), "%s.irq[0x%x]",
-			    cpu->path, i);
-			memset(&templ, 0, sizeof(templ));
-			templ.line = i;
-			templ.name = name;
-			templ.extra = cpu;
-			templ.interrupt_assert = sh_cpu_interrupt_assert;
-			templ.interrupt_deassert = sh_cpu_interrupt_deassert;
-			interrupt_handler_register(&templ);
-		}
-	} else {
-		struct interrupt templ;
-		memset(&templ, 0, sizeof(templ));
-		templ.line = i;
-		templ.name = cpu->path;
-		templ.extra = cpu;
-		templ.interrupt_assert = sh3_cpu_interrupt_assert;
-		templ.interrupt_deassert = sh3_cpu_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	/*  SH4-specific memory mapped registers, TLBs, caches, etc:  */
-	if (cpu->cd.sh.cpu_type.arch == 4) {
-		cpu->cd.sh.pcic_pcibus = (struct pci_data *) device_add(machine, "sh4");
-
-		/*
-		 *  Interrupt Controller initial values, according to the
-		 *  SH7760 manual:
-		 */
-		cpu->cd.sh.intc_iprd = 0xda74;
-		cpu->cd.sh.intc_intmsk00 = 0xf3ff7fff;
-		cpu->cd.sh.intc_intmsk04 = 0x00ffffff;
-		/*  All others are zero.  */
-
-		/*  TODO: Initial priorities?  */
-		cpu->cd.sh.intc_intpri00 = 0x33333333;
-		cpu->cd.sh.intc_intpri04 = 0x33333333;
-		cpu->cd.sh.intc_intpri08 = 0x33333333;
-		cpu->cd.sh.intc_intpri0c = 0x33333333;
-	}
-
-	sh_update_interrupt_priorities(cpu);
-
-	return 1;
-}
-
-
-/*
- *  sh_update_interrupt_priorities():
- *
- *  SH interrupts are a bit complicated; there are several intc registers
- *  controlling priorities for various peripherals:
- *
- *  Register:  Bits 15..12  11..8  7..4      3..0
- *  ---------  -----------  -----  ----      ----
- *  ipra       TMU0         TMU1   TMU2      Reserved
- *  iprb       WDT          REF    Reserved  Reserved
- *  iprc       GPIO         DMAC   Reserved  H-UDI
- *  iprd       IRL0         IRL1   IRL2      IRL3
- *
- *  Register:  31..28  27..24  23..20  19..16  15..12  11..8   7..4   3..0
- *  ---------  ------  ------  ------  ------  ------  -----   ----   ----
- *  intpri00   IRQ4    IRQ5    IRQ6    IRQ7    Rsrvd.  Rsrvd.  Rsrvd. Reserved
- *  intpri04   HCAN2,0 HCAN2,1 SSI(0)  SSI(1)  HAC(0)  HAC(1)  I2C(0) I2C(1)
- *  intpri08   USB     LCDC    DMABRG  SCIF(0) SCIF(1) SCIF(2) SIM    HSPI
- *  intpri0c   Reserv. Reserv. MMCIF   Reserv. MFI     Rsrvd.  ADC    CMT
- */
-void sh_update_interrupt_priorities(struct cpu *cpu)
-{
-	int i;
-
-	/*
-	 *  Set priorities of known interrupts, without affecting the
-	 *  SH_INT_ASSERTED bit:
-	 */
-
-	for (i=SH4_INTEVT_IRQ0; i<=SH4_INTEVT_IRQ14; i+=0x20) {
-		cpu->cd.sh.int_prio_and_pending[i/0x20] &= ~SH_INT_PRIO_MASK;
-		cpu->cd.sh.int_prio_and_pending[i/0x20] |= (15 - ((i - 
-		    SH4_INTEVT_IRQ0) / 0x20));
-	}
-
-	cpu->cd.sh.int_prio_and_pending[SH_INTEVT_TMU0_TUNI0 / 0x20] &=
-	    ~SH_INT_PRIO_MASK;
-	cpu->cd.sh.int_prio_and_pending[SH_INTEVT_TMU0_TUNI0 / 0x20] |=
-	    (cpu->cd.sh.intc_ipra >> 12) & 0xf;
-
-	cpu->cd.sh.int_prio_and_pending[SH_INTEVT_TMU1_TUNI1 / 0x20] &=
-	    ~SH_INT_PRIO_MASK;
-	cpu->cd.sh.int_prio_and_pending[SH_INTEVT_TMU1_TUNI1 / 0x20] |=
-	    (cpu->cd.sh.intc_ipra >> 8) & 0xf;
-
-	cpu->cd.sh.int_prio_and_pending[SH_INTEVT_TMU2_TUNI2 / 0x20] &=
-	    ~SH_INT_PRIO_MASK;
-	cpu->cd.sh.int_prio_and_pending[SH_INTEVT_TMU2_TUNI2 / 0x20] |=
-	    (cpu->cd.sh.intc_ipra >> 4) & 0xf;
-
-	for (i=SH4_INTEVT_SCIF_ERI; i<=SH4_INTEVT_SCIF_TXI; i+=0x20) {
-		cpu->cd.sh.int_prio_and_pending[i/0x20] &= ~SH_INT_PRIO_MASK;
-		cpu->cd.sh.int_prio_and_pending[i/0x20] |=
-		    ((cpu->cd.sh.intc_intpri08 >> 16) & 0xf);
-	}
-}
-
-
-/*
- *  sh3_cpu_interrupt_assert():
- *  sh3_cpu_interrupt_deassert():
- */
-void sh3_cpu_interrupt_assert(struct interrupt *interrupt)
-{
-	/*  TODO  */
-}
-void sh3_cpu_interrupt_deassert(struct interrupt *interrupt)
-{
-	/*  TODO  */
-}       
-
-
-/*
- *  sh_cpu_interrupt_assert():
- */
-void sh_cpu_interrupt_assert(struct interrupt *interrupt)
-{
-	struct cpu *cpu = (struct cpu *) interrupt->extra;
-	unsigned int irq_nr = interrupt->line;
-	unsigned int index = irq_nr / 0x20;
-	unsigned int prio;
-
-	/*  Assert the interrupt, and check its priority level:  */
-	cpu->cd.sh.int_prio_and_pending[index] |= SH_INT_ASSERTED;
-	prio = cpu->cd.sh.int_prio_and_pending[index] & SH_INT_PRIO_MASK;
-
-	if (prio == 0) {
-		/*  Interrupt not implemented? Hm.  */
-		fatal("[ SH interrupt 0x%x, prio 0 (?), aborting ]\n", irq_nr);
-		exit(1);
-	}
-
-	if (cpu->cd.sh.int_to_assert == 0 || prio > cpu->cd.sh.int_level) {
-		cpu->cd.sh.int_to_assert = irq_nr;
-		cpu->cd.sh.int_level = prio;
-	}
-}
-
-
-/*
- *  sh_cpu_interrupt_deassert():
- */
-void sh_cpu_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct cpu *cpu = (struct cpu *) interrupt->extra;
-	int irq_nr = interrupt->line;
-	int index = irq_nr / 0x20;
-
-	/*  Deassert the interrupt:  */
-	if (cpu->cd.sh.int_prio_and_pending[index] & SH_INT_ASSERTED) {
-		cpu->cd.sh.int_prio_and_pending[index] &= ~SH_INT_ASSERTED;
-
-		/*  Calculate new interrupt assertion:  */
-		cpu->cd.sh.int_to_assert = 0;
-		cpu->cd.sh.int_level = 0;
-
-		/*  NOTE/TODO: This is slow, but should hopefully work:  */
-		for (index=0; index<0x1000/0x20; index++) {
-			uint8_t x = cpu->cd.sh.int_prio_and_pending[index];
-			uint8_t prio = x & SH_INT_PRIO_MASK;
-			if (x & SH_INT_ASSERTED &&
-			    prio > cpu->cd.sh.int_level) {
-				cpu->cd.sh.int_to_assert = index * 0x20;
-				cpu->cd.sh.int_level = prio;
-			}
-		}
-	}
-}
-
-
-/*
- *  sh_cpu_list_available_types():
- *
- *  Print a list of available SH CPU types.
- */
-void sh_cpu_list_available_types(void)
-{
-	int i = 0, j;
-	struct sh_cpu_type_def tdefs[] = SH_CPU_TYPE_DEFS;
-
-	while (tdefs[i].name != NULL) {
-		debug("%s", tdefs[i].name);
-		for (j=10 - strlen(tdefs[i].name); j>0; j--)
-			debug(" ");
-		i ++;
-		if ((i % 6) == 0 || tdefs[i].name == NULL)
-			debug("\n");
-	}
-}
-
-
-/*
- *  sh_cpu_dumpinfo():
- */
-void sh_cpu_dumpinfo(struct cpu *cpu)
-{
-	debug(" (%s-endian)\n",
-	    cpu->byte_order == EMUL_BIG_ENDIAN? "Big" : "Little");
-}
-
-
-/*
- *  sh_cpu_instruction_has_delayslot():
- *
- *  Return 1 if an opcode is a branch, 0 otherwise.
- */
-int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
-{
-	uint16_t iword = *((uint16_t *)&ib[0]);
-	int hi4, lo8; // , lo4
-
-	if (!cpu->is_32bit)
-		return 0;
-
-	if (cpu->byte_order == EMUL_BIG_ENDIAN)
-		iword = BE16_TO_HOST(iword);
-	else
-		iword = LE16_TO_HOST(iword);
-
-	hi4 = iword >> 12;
-	lo8 = iword & 255;
-	// lo4 = iword & 15;
-
-        switch (hi4) {
-	case 0x0:
-		if (iword == 0x000b)	/*  rts  */
-			return 1;
-		if (iword == 0x002b)	/*  rte  */
-			return 1;
-		if (lo8 == 0x03)	/*  bsrf  */
-			return 1;
-		if (lo8 == 0x23)	/*  braf  */
-			return 1;
-		break;
-	case 0x4:
-		switch (lo8) {
-		case 0x0b:	/*  jsr  */
-		case 0x2b:	/*  jmp  */
-			return 1;
-		}
-		break;
-	case 0x8:
-		switch ((iword >> 8) & 0xf) {
-		case 0xd:	/*  bt/s  */
-		case 0xf:	/*  bf/s  */
-			return 1;
-		}
-		break;
-	case 0xa:	/*  bra  */
-	case 0xb:	/*  bsr  */
-		return 1;
-	}
-
-	return 0;
-}
-
-
-/*
- *  sh_cpu_register_dump():
- *
- *  Dump cpu registers in a relatively readable format.
- *
- *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
- *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
- */
-void sh_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
-{
-	char *symbol;
-	uint64_t offset;
-	int i, x = cpu->cpu_id;
-
-	if (gprs) {
-		/*  Special registers (pc, ...) first:  */
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    cpu->pc, &offset);
-
-		debug("cpu%i: pc  = 0x%08" PRIx32, x, (uint32_t)cpu->pc);
-		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
-
-		debug("cpu%i: sr  = 0x%08" PRIx32"  (%s, %s, %s, %s, %s, %s,"
-		    " imask=0x%x, %s, %s)\n", x, (int32_t)cpu->cd.sh.sr,
-		    (cpu->cd.sh.sr & SH_SR_MD)? "MD" : "!md",
-		    (cpu->cd.sh.sr & SH_SR_RB)? "RB" : "!rb",
-		    (cpu->cd.sh.sr & SH_SR_BL)? "BL" : "!bl",
-		    (cpu->cd.sh.sr & SH_SR_FD)? "FD" : "!fd",
-		    (cpu->cd.sh.sr & SH_SR_M)? "M" : "!m",
-		    (cpu->cd.sh.sr & SH_SR_Q)? "Q" : "!q",
-		    (cpu->cd.sh.sr & SH_SR_IMASK) >> SH_SR_IMASK_SHIFT,
-		    (cpu->cd.sh.sr & SH_SR_S)? "S" : "!s",
-		    (cpu->cd.sh.sr & SH_SR_T)? "T" : "!t");
-
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    cpu->cd.sh.pr, &offset);
-		debug("cpu%i: pr  = 0x%08" PRIx32, x, (uint32_t)cpu->cd.sh.pr);
-		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
-
-		debug("cpu%i: mach = 0x%08" PRIx32"  macl = 0x%08" PRIx32
-		    "  gbr = 0x%08" PRIx32"\n", x, (uint32_t)cpu->cd.sh.mach,
-		    (uint32_t)cpu->cd.sh.macl, (uint32_t)cpu->cd.sh.gbr);
-
-		for (i=0; i<SH_N_GPRS; i++) {
-			if ((i % 4) == 0)
-				debug("cpu%i:", x);
-			debug(" r%-2i = 0x%08x ", i, (int)cpu->cd.sh.r[i]);
-			if ((i % 4) == 3)
-				debug("\n");
-		}
-	}
-
-	if (coprocs & 1) {
-		/*  Floating point:  */
-		debug("cpu%i: fpscr = 0x%08" PRIx32" (%s,%s,%s)  fpul = 0x%08"
-		    PRIx32"\n", x, cpu->cd.sh.fpscr,
-		    cpu->cd.sh.fpscr & SH_FPSCR_PR? "PR" : "!pr",
-		    cpu->cd.sh.fpscr & SH_FPSCR_SZ? "SZ" : "!sz",
-		    cpu->cd.sh.fpscr & SH_FPSCR_FR? "FR" : "!fr",
-		    cpu->cd.sh.fpul);
-
-		for (i=0; i<SH_N_FPRS; i++) {
-			if ((i % 4) == 0)
-				debug("cpu%i:", x);
-			debug(" fr%-2i=0x%08x ", i, (int)cpu->cd.sh.fr[i]);
-			if ((i % 4) == 3)
-				debug("\n");
-		}
-
-		for (i=0; i<SH_N_FPRS; i++) {
-			if ((i % 4) == 0)
-				debug("cpu%i:", x);
-			debug(" xf%-2i=0x%08x ", i, (int)cpu->cd.sh.xf[i]);
-			if ((i % 4) == 3)
-				debug("\n");
-		}
-	}
-
-	if (coprocs & 2) {
-		/*  System registers, etc:  */
-		debug("cpu%i: vbr = 0x%08" PRIx32"  sgr = 0x%08" PRIx32
-		    "  dbr = 0x%08" PRIx32"\n", x, cpu->cd.sh.vbr, cpu->cd.sh.sgr,
-		    cpu->cd.sh.dbr);
-		debug("cpu%i: spc = 0x%08" PRIx32"  ssr = 0x%08" PRIx32"\n",
-		    x, cpu->cd.sh.spc, cpu->cd.sh.ssr);
-		debug("cpu%i: expevt = 0x%" PRIx32"  intevt = 0x%" PRIx32
-		    "  tra = 0x%" PRIx32"\n", x, cpu->cd.sh.expevt,
-		    cpu->cd.sh.intevt, cpu->cd.sh.tra);
-
-		for (i=0; i<SH_N_GPRS_BANKED; i++) {
-			if ((i % 2) == 0)
-				debug("cpu%i:", x);
-			debug(" r%i_bank = 0x%08x ", i,
-			    (int)cpu->cd.sh.r_bank[i]);
-			if ((i % 2) == 1)
-				debug("\n");
-		}
-	}
-}
-
-
-/*
- *  sh_cpu_tlbdump():
- *
- *  Called from the debugger to dump the TLB in a readable format.
- *  x is the cpu number to dump, or -1 to dump all CPUs.
- *
- *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
- *  just dumped.
- */
-void sh_cpu_tlbdump(struct machine *m, int x, int rawflag)
-{
-	int i, j;
-
-	for (j=0; j<m->ncpus; j++) {
-		struct cpu *cpu = m->cpus[j];
-
-		if (x >= 0 && j != x)
-			continue;
-
-		for (i=0; i<SH_N_ITLB_ENTRIES; i++)
-			printf("cpu%i: itlb_hi_%-2i = 0x%08" PRIx32"  "
-			    "itlb_lo_%-2i = 0x%08" PRIx32"\n", j, i,
-			    (uint32_t) cpu->cd.sh.itlb_hi[i], i,
-			    (uint32_t) cpu->cd.sh.itlb_lo[i]);
-		for (i=0; i<SH_N_UTLB_ENTRIES; i++)
-			printf("cpu%i: utlb_hi_%-2i = 0x%08" PRIx32"  "
-			    "utlb_lo_%-2i = 0x%08" PRIx32"\n", j, i,
-			    (uint32_t) cpu->cd.sh.utlb_hi[i], i,
-			    (uint32_t) cpu->cd.sh.utlb_lo[i]);
-	}
-}
-
-
-/*
- *  sh_update_sr():
- *
- *  Writes a new value to the status register.
- */
-void sh_update_sr(struct cpu *cpu, uint32_t new_sr)
-{
-	uint32_t old_sr = cpu->cd.sh.sr;
-
-	if ((new_sr & SH_SR_RB) != (old_sr & SH_SR_RB)) {
-		int i;
-		for (i=0; i<SH_N_GPRS_BANKED; i++) {
-			uint32_t tmp = cpu->cd.sh.r[i];
-			cpu->cd.sh.r[i] = cpu->cd.sh.r_bank[i];
-			cpu->cd.sh.r_bank[i] = tmp;
-		}
-	}
-
-	cpu->cd.sh.sr = new_sr;
-}
-
-
-/*
- *  sh_update_fpscr():
- *
- *  Writes a new value to the floating-point status/control register.
- */
-void sh_update_fpscr(struct cpu *cpu, uint32_t new_fpscr)
-{
-	uint32_t old_fpscr = cpu->cd.sh.fpscr;
-
-	if ((new_fpscr & SH_FPSCR_FR) != (old_fpscr & SH_FPSCR_FR)) {
-		int i;
-		for (i=0; i<SH_N_FPRS; i++) {
-			uint32_t tmp = cpu->cd.sh.fr[i];
-			cpu->cd.sh.fr[i] = cpu->cd.sh.xf[i];
-			cpu->cd.sh.xf[i] = tmp;
-		}
-	}
-
-	cpu->cd.sh.fpscr = new_fpscr;
-}
-
-
-/*
- *  sh_exception():
- *
- *  Causes a transfer of control to an exception or interrupt handler.
- *  If intevt > 0, then it is an interrupt, otherwise an exception.
- *
- *  vaddr contains the faulting address, on TLB exceptions.
- */
-void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr)
-{
-	uint32_t vbr = cpu->cd.sh.vbr;
-
-	if (!quiet_mode) {
-		if (intevt > 0)
-			debug("[ interrupt 0x%03x", intevt);
-		else
-			debug("[ exception 0x%03x", expevt);
-
-		debug(", pc=0x%08" PRIx32" ", (uint32_t)cpu->pc);
-		if (intevt == 0)
-			debug("vaddr=0x%08" PRIx32" ", vaddr);
-
-		debug(" ]\n");
-	}
-
-	if (cpu->cd.sh.sr & SH_SR_BL) {
-		fatal("[ sh_exception(): BL bit already set. ]\n");
-
-		/*  This is actually OK in two cases: a User Break,
-		    or on NMI interrupts if a special flag is set?  */
-		/*  TODO  */
-
-		expevt = EXPEVT_RESET_POWER;
-	}
-
-	if (cpu->is_halted) {
-		/*
-		 *  If the exception occurred on a 'sleep' instruction, then let
-		 *  the instruction following the sleep instruction be the one
-		 *  where execution resumes when the interrupt service routine
-		 *  returns.
-		 */
-		cpu->is_halted = 0;
-		cpu->pc += sizeof(uint16_t);
-	}
-
-	if (cpu->delay_slot) {
-		cpu->delay_slot = EXCEPTION_IN_DELAY_SLOT;
-		cpu->pc -= sizeof(uint16_t);
-	}
-
-
-	/*
-	 *  Stuff common to all exceptions:
-	 */
-
-	cpu->cd.sh.spc = cpu->pc;
-	cpu->cd.sh.ssr = cpu->cd.sh.sr;
-	cpu->cd.sh.sgr = cpu->cd.sh.r[15];
-
-	if (intevt > 0) {
-		cpu->cd.sh.intevt = intevt;
-		expevt = -1;
-	} else {
-		cpu->cd.sh.expevt = expevt;
-	}
-
-	sh_update_sr(cpu, cpu->cd.sh.sr | SH_SR_MD | SH_SR_RB | SH_SR_BL);
-
-	/*  Most exceptions set PC to VBR + 0x100.  */
-	cpu->pc = vbr + 0x100;
-
-
-	/*  Specific cases:  */
-	switch (expevt) {
-
-	case -1:	/*  Interrupt  */
-		cpu->pc = vbr + 0x600;
-		break;
-
-	case EXPEVT_RESET_POWER:
-	case EXPEVT_RESET_MANUAL:
-		cpu->pc = 0xa0000000;
-		cpu->cd.sh.vbr = 0x00000000;
-		sh_update_sr(cpu, (cpu->cd.sh.sr | SH_SR_IMASK) & ~SH_SR_FD);
-		break;
-
-	case EXPEVT_TLB_MISS_LD:
-	case EXPEVT_TLB_MISS_ST:
-		cpu->pc = vbr + 0x400;
-	case EXPEVT_TLB_PROT_LD:
-	case EXPEVT_TLB_PROT_ST:
-	case EXPEVT_TLB_MOD:
-		cpu->cd.sh.tea = vaddr;
-		cpu->cd.sh.pteh &= ~SH4_PTEH_VPN_MASK;
-		cpu->cd.sh.pteh |= (vaddr & SH4_PTEH_VPN_MASK);
-		break;
-
-	case EXPEVT_TRAPA:
-		/*
-		 *  Note: The TRA register is already set by the implementation
-		 *  of the trapa instruction. See cpu_sh_instr.c for details.
-		 *  Here, spc is incremented, so that a return from the trap
-		 *  handler transfers control to the instruction _following_
-		 *  the trapa.
-		 */
-		cpu->cd.sh.spc += sizeof(uint16_t);
-		break;
-
-	case EXPEVT_RES_INST:
-		/*
-		 *  Note: Having this code here makes it possible to catch
-		 *  reserved instructions; during normal instruction execution,
-		 *  these are not very common.
-		 */
-#if 1
-		printf("\nRESERVED SuperH instruction at spc=%08" PRIx32"\n",
-		    cpu->cd.sh.spc);
-		exit(1);
-#else
-		break;
-#endif
-
-	case EXPEVT_FPU_DISABLE:
-		break;
-
-	default:fatal("sh_exception(): exception 0x%x is not yet "
-		    "implemented.\n", expevt);
-		exit(1);
-	}
-
-	sh_pc_to_pointers(cpu);
-}
-
-
-/*
- *  sh_cpu_disassemble_instr():
- *
- *  SHcompact instruction disassembly. The top 4 bits of each 16-bit
- *  instruction word is used as the main opcode. For most instructions, the
- *  lowest 4 or 8 bits then select sub-opcode.
- *
- *  This function convert an instruction word into human readable format,
- *  for instruction tracing.
- *
- *  If running is 1, cpu->pc should be the address of the instruction.
- *
- *  If running is 0, things that depend on the runtime environment (eg.
- *  register contents) will not be shown, and addr will be used instead of
- *  cpu->pc for relative addresses.
- */
-int sh_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
-	int running, uint64_t dumpaddr)
-{
-	char *symbol;
-	uint64_t offset, addr;
-	uint16_t iword;
-
-	if (running)
-		dumpaddr = cpu->pc;
-
-	symbol = get_symbol_name(&cpu->machine->symbol_context,
-	    dumpaddr, &offset);
-	if (symbol != NULL && offset==0)
-		debug("<%s>\n", symbol);
-
-	if (cpu->machine->ncpus > 1 && running)
-		debug("cpu%i: ", cpu->cpu_id);
-
-	debug("%08" PRIx32, (uint32_t) dumpaddr);
-
-	if (cpu->byte_order == EMUL_BIG_ENDIAN)
-		iword = (instr[0] << 8) + instr[1];
-	else
-		iword = (instr[1] << 8) + instr[0];
-
-	debug(":  %04x %s\t", iword, cpu->delay_slot? "(d)" : "");
-	const int hi4 = iword >> 12, lo4 = iword & 15, lo8 = iword & 255;
-	int r8 = (iword >> 8) & 15, r4 = (iword >> 4) & 15;
-
-
-	/*
-	 *  Decode the instruction:
-	 */
-
-	switch (hi4) {
-	case 0x0:
-		if (lo8 == 0x02)
-			debug("stc\tsr,r%i\n", r8);
-		else if (lo8 == 0x03)
-			debug("bsrf\tr%i\n", r8);
-		else if (lo4 >= 4 && lo4 <= 6) {
-			if (lo4 == 0x4)
-				debug("mov.b\tr%i,@(r0,r%i)", r4, r8);
-			else if (lo4 == 0x5)
-				debug("mov.w\tr%i,@(r0,r%i)", r4, r8);
-			else if (lo4 == 0x6)
-				debug("mov.l\tr%i,@(r0,r%i)", r4, r8);
-			if (running) {
-				addr = cpu->cd.sh.r[0] + cpu->cd.sh.r[r8];
-				debug("\t; r0+r%i = ", r8);
-				symbol = get_symbol_name(
-				    &cpu->machine->symbol_context,
-				    addr, &offset);
-				if (symbol != NULL)
-					debug("<%s>", symbol);
-				else
-					debug("0x%08" PRIx32, addr);
-			}
-			debug("\n");
-		} else if (lo4 == 0x7)
-			debug("mul.l\tr%i,r%i\n", r4, r8);
-		else if (iword == 0x0008)
-			debug("clrt\n");
-		else if (iword == 0x0009)
-			debug("nop\n");
-		else if (lo8 == 0x0a)
-			debug("sts\tmach,r%i\n", r8);
-		else if (iword == 0x000b)
-			debug("rts\n");
-		else if (lo4 >= 0xc && lo4 <= 0xe) {
-			if (lo4 == 0xc)
-				debug("mov.b\t@(r0,r%i),r%i", r4, r8);
-			else if (lo4 == 0xd)
-				debug("mov.w\t@(r0,r%i),r%i", r4, r8);
-			else if (lo4 == 0xe)
-				debug("mov.l\t@(r0,r%i),r%i", r4, r8);
-			if (running) {
-				addr = cpu->cd.sh.r[0] + cpu->cd.sh.r[r4];
-				debug("\t; r0+r%i = ", r4);
-				symbol = get_symbol_name(
-				    &cpu->machine->symbol_context,
-				    addr, &offset);
-				if (symbol != NULL)
-					debug("<%s>", symbol);
-				else
-					debug("0x%08" PRIx32, addr);
-			}
-			debug("\n");
-		} else if (lo8 == 0x12)
-			debug("stc\tgbr,r%i\n", r8);
-		else if (iword == 0x0018)
-			debug("sett\n");
-		else if (iword == 0x0019)
-			debug("div0u\n");
-		else if (lo8 == 0x1a)
-			debug("sts\tmacl,r%i\n", r8);
-		else if (iword == 0x001b)
-			debug("sleep\n");
-		else if (lo8 == 0x22)
-			debug("stc\tvbr,r%i\n", r8);
-		else if (lo8 == 0x23)
-			debug("braf\tr%i\n", r8);
-		else if (iword == 0x0028)
-			debug("clrmac\n");
-		else if (lo8 == 0x29)
-			debug("movt\tr%i\n", r8);
-		else if (lo8 == 0x2a)
-			debug("sts\tpr,r%i\n", r8);
-		else if (iword == 0x002b)
-			debug("rte\n");
-		else if (lo8 == 0x32)
-			debug("stc\tssr,r%i\n", r8);
-		else if (iword == 0x0038)
-			debug("ldtlb\n");
-		else if (iword == 0x003b)
-			debug("brk\n");
-		else if (lo8 == 0x42)
-			debug("stc\tspc,r%i\n", r8);
-		else if (iword == 0x0048)
-			debug("clrs\n");
-		else if (iword == 0x0058)
-			debug("sets\n");
-		else if (lo8 == 0x5a)
-			debug("sts\tfpul,r%i\n", r8);
-		else if (lo8 == 0x6a)
-			debug("sts\tfpscr,r%i\n", r8);
-		else if ((lo8 & 0x8f) == 0x82)
-			debug("stc\tr%i_bank,r%i\n", (lo8 >> 4) & 7, r8);
-		else if (lo8 == 0x83)
-			debug("pref\t@r%i\n", r8);
-		else if (lo8 == 0x93)
-			debug("ocbi\t@r%i\n", r8);
-		else if (lo8 == 0xa3)
-			debug("ocbp\t@r%i\n", r8);
-		else if (lo8 == 0xb3)
-			debug("ocbwb\t@r%i\n", r8);
-		else if (lo8 == 0xc3)
-			debug("movca.l\tr0,@r%i\n", r8);
-		else if (lo8 == 0xfa)
-			debug("stc\tdbr,r%i\n", r8);
-		else if (iword == SH_INVALID_INSTR)
-			debug("gxemul_dreamcast_prom_emul\n");
-		else
-			debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
-		break;
-	case 0x1:
-		debug("mov.l\tr%i,@(%i,r%i)", r4, lo4 * 4, r8);
-		if (running) {
-			addr = cpu->cd.sh.r[r8] + lo4 * 4;
-			debug("\t; r%i+%i = ", r8, lo4 * 4);
-			symbol = get_symbol_name(&cpu->machine->symbol_context,
-			    addr, &offset);
-			if (symbol != NULL)
-				debug("<%s>", symbol);
-			else
-				debug("0x%08" PRIx32, addr);
-		}
-		debug("\n");
-		break;
-	case 0x2:
-		if (lo4 == 0x0)
-			debug("mov.b\tr%i,@r%i", r4, r8);
-		else if (lo4 == 0x1)
-			debug("mov.w\tr%i,@r%i", r4, r8);
-		else if (lo4 == 0x2)
-			debug("mov.l\tr%i,@r%i", r4, r8);
-		else if (lo4 == 0x4)
-			debug("mov.b\tr%i,@-r%i", r4, r8);
-		else if (lo4 == 0x5)
-			debug("mov.w\tr%i,@-r%i", r4, r8);
-		else if (lo4 == 0x6)
-			debug("mov.l\tr%i,@-r%i", r4, r8);
-		else if (lo4 == 0x7)
-			debug("div0s\tr%i,r%i", r4, r8);
-		else if (lo4 == 0x8)
-			debug("tst\tr%i,r%i", r4, r8);
-		else if (lo4 == 0x9)
-			debug("and\tr%i,r%i", r4, r8);
-		else if (lo4 == 0xa)
-			debug("xor\tr%i,r%i", r4, r8);
-		else if (lo4 == 0xb)
-			debug("or\tr%i,r%i", r4, r8);
-		else if (lo4 == 0xc)
-			debug("cmp/str\tr%i,r%i", r4, r8);
-		else if (lo4 == 0xd)
-			debug("xtrct\tr%i,r%i", r4, r8);
-		else if (lo4 == 0xe)
-			debug("mulu.w\tr%i,r%i", r4, r8);
-		else if (lo4 == 0xf)
-			debug("muls.w\tr%i,r%i", r4, r8);
-		else
-			debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x", hi4, lo8);
-		if (running && lo4 <= 6) {
-			debug("\t; r%i = 0x%08" PRIx32, r8, cpu->cd.sh.r[r8]);
-		}
-		debug("\n");
-		break;
-	case 0x3:
-		if (lo4 == 0x0)
-			debug("cmp/eq\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0x2)
-			debug("cmp/hs\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0x3)
-			debug("cmp/ge\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0x4)
-			debug("div1\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0x5)
-			debug("dmulu.l\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0x6)
-			debug("cmp/hi\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0x7)
-			debug("cmp/gt\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0x8)
-			debug("sub\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0xa)
-			debug("subc\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0xb)
-			debug("subv\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0xc)
-			debug("add\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0xd)
-			debug("dmuls.l\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0xe)
-			debug("addc\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0xf)
-			debug("addv\tr%i,r%i\n", r4, r8);
-		else
-			debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
-		break;
-	case 0x4:
-		if (lo8 == 0x00)
-			debug("shll\tr%i\n", r8);
-		else if (lo8 == 0x01)
-			debug("shlr\tr%i\n", r8);
-		else if (lo8 == 0x02)
-			debug("sts.l\tmach,@-r%i\n", r8);
-		else if (lo8 == 0x03)
-			debug("stc.l\tsr,@-r%i\n", r8);
-		else if (lo8 == 0x04)
-			debug("rotl\tr%i\n", r8);
-		else if (lo8 == 0x05)
-			debug("rotr\tr%i\n", r8);
-		else if (lo8 == 0x06)
-			debug("lds.l\t@r%i+,mach\n", r8);
-		else if (lo8 == 0x07)
-			debug("ldc.l\t@r%i+,sr\n", r8);
-		else if (lo8 == 0x08)
-			debug("shll2\tr%i\n", r8);
-		else if (lo8 == 0x09)
-			debug("shlr2\tr%i\n", r8);
-		else if (lo8 == 0x0a)
-			debug("lds\tr%i,mach\n", r8);
-		else if (lo8 == 0x0b)
-			debug("jsr\t@r%i\n", r8);
-		else if (lo4 == 0xc)
-			debug("shad\tr%i,r%i\n", r4, r8);
-		else if (lo4 == 0xd)
-			debug("shld\tr%i,r%i\n", r4, r8);
-		else if (lo8 == 0x0e)
-			debug("ldc\tr%i,sr\n", r8);
-		else if (lo8 == 0x10)
-			debug("dt\tr%i\n", r8);
-		else if (lo8 == 0x11)
-			debug("cmp/pz\tr%i\n", r8);
-		else if (lo8 == 0x12)
-			debug("sts.l\tmacl,@-r%i\n", r8);
-		else if (lo8 == 0x13)
-			debug("stc.l\tgbr,@-r%i\n", r8);
-		else if (lo8 == 0x15)
-			debug("cmp/pl\tr%i\n", r8);
-		else if (lo8 == 0x16)
-			debug("lds.l\t@r%i+,macl\n", r8);
-		else if (lo8 == 0x17)
-			debug("ldc.l\t@r%i+,gbr\n", r8);
-		else if (lo8 == 0x18)
-			debug("shll8\tr%i\n", r8);
-		else if (lo8 == 0x19)
-			debug("shlr8\tr%i\n", r8);
-		else if (lo8 == 0x1a)
-			debug("lds\tr%i,macl\n", r8);
-		else if (lo8 == 0x1b)
-			debug("tas.b\t@r%i\n", r8);
-		else if (lo8 == 0x1e)
-			debug("ldc\tr%i,gbr\n", r8);
-		else if (lo8 == 0x20)
-			debug("shal\tr%i\n", r8);
-		else if (lo8 == 0x21)
-			debug("shar\tr%i\n", r8);
-		else if (lo8 == 0x22)
-			debug("sts.l\tpr,@-r%i\n", r8);
-		else if (lo8 == 0x23)
-			debug("stc.l\tvbr,@-r%i\n", r8);
-		else if (lo8 == 0x24)
-			debug("rotcl\tr%i\n", r8);
-		else if (lo8 == 0x25)
-			debug("rotcr\tr%i\n", r8);
-		else if (lo8 == 0x26)
-			debug("lds.l\t@r%i+,pr\n", r8);
-		else if (lo8 == 0x27)
-			debug("ldc.l\t@r%i+,vbr\n", r8);
-		else if (lo8 == 0x28)
-			debug("shll16\tr%i\n", r8);
-		else if (lo8 == 0x29)
-			debug("shlr16\tr%i\n", r8);
-		else if (lo8 == 0x2a)
-			debug("lds\tr%i,pr\n", r8);
-		else if (lo8 == 0x2b) {
-			debug("jmp\t@r%i", r8);
-			if (running) {
-				symbol = get_symbol_name(
-				    &cpu->machine->symbol_context,
-				    cpu->cd.sh.r[r8], &offset);
-				if (symbol != NULL)
-					debug("\t\t; <%s>", symbol);
-			}
-			debug("\n");
-		} else if (lo8 == 0x2e)
-			debug("ldc\tr%i,vbr\n", r8);
-		else if (lo8 == 0x33)
-			debug("stc.l\tssr,@-r%i\n", r8);
-		else if (lo8 == 0x37)
-			debug("ldc.l\t@r%i+,ssr\n", r8);
-		else if (lo8 == 0x3e)
-			debug("ldc\tr%i,ssr\n", r8);
-		else if (lo8 == 0x43)
-			debug("stc.l\tspc,@-r%i\n", r8);
-		else if (lo8 == 0x47)
-			debug("ldc.l\t@r%i+,spc\n", r8);
-		else if (lo8 == 0x4e)
-			debug("ldc\tr%i,spc\n", r8);
-		else if (lo8 == 0x52)
-			debug("sts.l\tfpul,@-r%i\n", r8);
-		else if (lo8 == 0x56)
-			debug("lds.l\t@r%i+,fpul\n", r8);
-		else if (lo8 == 0x5a)
-			debug("lds\tr%i,fpul\n", r8);
-		else if (lo8 == 0x62)
-			debug("sts.l\tfpscr,@-r%i\n", r8);
-		else if (lo8 == 0x66)
-			debug("lds.l\t@r%i+,fpscr\n", r8);
-		else if (lo8 == 0x6a)
-			debug("lds\tr%i,fpscr\n", r8);
-		else if ((lo8 & 0x8f) == 0x83)
-			debug("stc.l\tr%i_bank,@-r%i\n", (lo8 >> 4) & 7, r8);
-		else if ((lo8 & 0x8f) == 0x87)
-			debug("ldc.l\t@r%i,r%i_bank\n", r8, (lo8 >> 4) & 7, r8);
-		else if ((lo8 & 0x8f) == 0x8e)
-			debug("ldc\tr%i,r%i_bank\n", r8, (lo8 >> 4) & 7);
-		else if (lo8 == 0xfa)
-			debug("ldc\tr%i,dbr\n", r8);
-		else
-			debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
-		break;
-	case 0x5:
-		debug("mov.l\t@(%i,r%i),r%i", lo4 * 4, r4, r8);
-		if (running) {
-			addr = cpu->cd.sh.r[r4] + lo4 * 4;
-			symbol = get_symbol_name(&cpu->machine->symbol_context, addr, &offset);
-			if (symbol != NULL)
-				debug("\t; r%i+%i <%s>", r4, lo4 * 4, symbol);
-			else
-				debug("\t; r%i+%i = 0x%08" PRIx32, r4, lo4 * 4, (int)addr);
-		}
-		debug("\n");
-		break;
-	case 0x6:
-		if (lo4 == 0x0)
-			debug("mov.b\t@r%i,r%i", r4, r8);
-		else if (lo4 == 0x1)
-			debug("mov.w\t@r%i,r%i", r4, r8);
-		else if (lo4 == 0x2)
-			debug("mov.l\t@r%i,r%i", r4, r8);
-		else if (lo4 == 0x3)
-			debug("mov\tr%i,r%i", r4, r8);
-		else if (lo4 == 0x4)
-			debug("mov.b\t@r%i+,r%i", r4, r8);
-		else if (lo4 == 0x5)
-			debug("mov.w\t@r%i+,r%i", r4, r8);
-		else if (lo4 == 0x6)
-			debug("mov.l\t@r%i+,r%i", r4, r8);
-		else if (lo4 == 0x7)
-			debug("not\tr%i,r%i", r4, r8);
-		else if (lo4 == 0x8)
-			debug("swap.b\tr%i,r%i", r4, r8);
-		else if (lo4 == 0x9)
-			debug("swap.w\tr%i,r%i", r4, r8);
-		else if (lo4 == 0xa)
-			debug("negc\tr%i,r%i", r4, r8);
-		else if (lo4 == 0xb)
-			debug("neg\tr%i,r%i", r4, r8);
-		else if (lo4 == 0xc)
-			debug("extu.b\tr%i,r%i", r4, r8);
-		else if (lo4 == 0xd)
-			debug("extu.w\tr%i,r%i", r4, r8);
-		else if (lo4 == 0xe)
-			debug("exts.b\tr%i,r%i", r4, r8);
-		else if (lo4 == 0xf)
-			debug("exts.w\tr%i,r%i", r4, r8);
-		else
-			debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x", hi4, lo8);
-		if (running && lo4 < 8 && (lo4 & 3) < 3) {
-			debug("\t; r%i = 0x%08" PRIx32, r4, cpu->cd.sh.r[r4]);
-		}
-		debug("\n");
-		break;
-	case 0x7:
-		debug("add\t#%i,r%i\n", (int8_t)lo8, r8);
-		break;
-	case 0x8:
-		if (r8 == 0 || r8 == 4) {
-			if (r8 == 0x0)
-				debug("mov.b\tr0,@(%i,r%i)", lo4, r4);
-			else if (r8 == 0x4)
-				debug("mov.b\t@(%i,r%i),r0", lo4, r4);
-			if (running) {
-				debug("\t; r%i+%i = 0x%08" PRIx32, r4, lo4,
-				    cpu->cd.sh.r[r4] + lo4);
-			}
-			debug("\n");
-		} else if (r8 == 1 || r8 == 5) {
-			if (r8 == 0x1)
-				debug("mov.w\tr0,@(%i,r%i)", lo4 * 2, r4);
-			else if (r8 == 0x5)
-				debug("mov.w\t@(%i,r%i),r0", lo4 * 2, r4);
-			if (running) {
-				debug("\t; r%i+%i = 0x%08" PRIx32, r4, lo4 * 2,
-				    cpu->cd.sh.r[r4] + lo4 * 2);
-			}
-			debug("\n");
-		} else if (r8 == 0x8) {
-			debug("cmp/eq\t#%i,r0\n", (int8_t)lo8);
-		} else if (r8 == 0x9 || r8 == 0xb || r8 == 0xd || r8 == 0xf) {
-			addr = (int8_t)lo8;
-			addr = dumpaddr + 4 + (addr << 1);
-			debug("b%s%s\t0x%x",
-			    (r8 == 0x9 || r8 == 0xd)? "t" : "f",
-			    (r8 == 0x9 || r8 == 0xb)? "" : "/s", (int)addr);
-			symbol = get_symbol_name(&cpu->machine->symbol_context,
-			    addr, &offset);
-			if (symbol != NULL)
-				debug("\t; <%s>", symbol);
-			debug("\n");
-		} else
-			debug("UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, r8);
-		break;
-	case 0x9:
-	case 0xd:
-		addr = lo8 * (hi4==9? 2 : 4);
-		addr += (dumpaddr & ~(hi4==9? 1 : 3)) + 4;
-		debug("mov.%s\t0x%x,r%i", hi4==9? "w":"l", (int)addr, r8);
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    addr, &offset);
-		if (symbol != NULL)
-			debug("\t; <%s>", symbol);
-		debug("\n");
-		break;
-	case 0xa:
-	case 0xb:
-		addr = (int32_t)(int16_t)((iword & 0xfff) << 4);
-		addr = ((int32_t)addr >> 3);
-		addr += dumpaddr + 4;
-		debug("%s\t0x%x", hi4==0xa? "bra":"bsr", (int)addr);
-
-		symbol = get_symbol_name(&cpu->machine->symbol_context,
-		    addr, &offset);
-		if (symbol != NULL)
-			debug("\t; <%s>", symbol);
-		debug("\n");
-		break;
-	case 0xc:
-		if (r8 == 0x0)
-			debug("mov.b\tr0,@(%i,gbr)\n", lo8);
-		else if (r8 == 0x1)
-			debug("mov.w\tr0,@(%i,gbr)\n", lo8 * 2);
-		else if (r8 == 0x2)
-			debug("mov.l\tr0,@(%i,gbr)\n", lo8 * 4);
-		else if (r8 == 0x3)
-			debug("trapa\t#%i\n", (uint8_t)lo8);
-		else if (r8 == 0x4)
-			debug("mov.b\t(%i,gbr),r0\n", lo8);
-		else if (r8 == 0x5)
-			debug("mov.w\t(%i,gbr),r0\n", lo8 * 2);
-		else if (r8 == 0x6)
-			debug("mov.l\t(%i,gbr),r0\n", lo8 * 4);
-		else if (r8 == 0x7) {
-			addr = lo8 * 4 + (dumpaddr & ~3) + 4;
-			debug("mova\t0x%x,r0\n", (int)addr);
-		} else if (r8 == 0x8)
-			debug("tst\t#%i,r0\n", (uint8_t)lo8);
-		else if (r8 == 0x9)
-			debug("and\t#%i,r0\n", (uint8_t)lo8);
-		else if (r8 == 0xa)
-			debug("xor\t#%i,r0\n", (uint8_t)lo8);
-		else if (r8 == 0xb)
-			debug("or\t#%i,r0\n", (uint8_t)lo8);
-		else if (r8 == 0xc)
-			debug("tst.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
-		else if (r8 == 0xd)
-			debug("and.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
-		else if (r8 == 0xe)
-			debug("xor.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
-		else if (r8 == 0xf)
-			debug("or.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
-		else
-			debug("UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, r8);
-		break;
-	case 0xe:
-		debug("mov\t#%i,r%i\n", (int8_t)lo8, r8);
-		break;
-	case 0xf:
-		if (lo4 == 0x0)
-			debug("fadd\t%sr%i,%sr%i\n",
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r4,
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
-		else if (lo4 == 0x1)
-			debug("fsub\t%sr%i,%sr%i\n",
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r4,
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
-		else if (lo4 == 0x2)
-			debug("fmul\t%sr%i,%sr%i\n",
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r4,
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
-		else if (lo4 == 0x3)
-			debug("fdiv\t%sr%i,%sr%i\n",
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r4,
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
-		else if (lo4 == 0x4)
-			debug("fcmp/eq\t%sr%i,%sr%i\n",
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r4,
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
-		else if (lo4 == 0x5)
-			debug("fcmp/gt\t%sr%i,%sr%i\n",
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r4,
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
-		else if (lo4 == 0x6) {
-			const char *n = "fr";
-			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
-				n = (r8 & 1)? "xd" : "dr";
-				r8 &= ~1;
-			}
-			debug("fmov\t@(r0,r%i),%s%i\n", r4, n, r8);
-		} else if (lo4 == 0x7) {
-			const char *n = "fr";
-			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
-				n = (r4 & 1)? "xd" : "dr";
-				r4 &= ~1;
-			}
-			debug("fmov\t%s%i,@(r0,r%i)\n", n, r4, r8);
-		} else if (lo4 == 0x8) {
-			const char *n = "fr";
-			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
-				n = (r8 & 1)? "xd" : "dr";
-				r8 &= ~1;
-			}
-			debug("fmov\t@r%i,%s%i\n", r4, n, r8);
-		} else if (lo4 == 0x9) {
-			const char *n = "fr";
-			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
-				n = (r8 & 1)? "xd" : "dr";
-				r8 &= ~1;
-			}
-			debug("fmov\t@r%i+,%s%i\n", r4, n, r8);
-		} else if (lo4 == 0xa) {
-			const char *n = "fr";
-			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
-				n = (r4 & 1)? "xd" : "dr";
-				r4 &= ~1;
-			}
-			debug("fmov\t%s%i,@r%i\n", n, r4, r8);
-		} else if (lo4 == 0xb) {
-			const char *n = "fr";
-			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
-				n = (r4 & 1)? "xd" : "dr";
-				r4 &= ~1;
-			}
-			debug("fmov\t%s%i,@-r%i\n", n, r4, r8);
-		} else if (lo4 == 0xc) {
-			const char *n1 = "fr", *n2 = "fr";
-			if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
-				n1 = (r4 & 1)? "xd" : "dr";
-				n2 = (r8 & 1)? "xd" : "dr";
-				r4 &= ~1; r8 &= ~1;
-			}
-			debug("fmov\t%s%i,%s%i\n", n1, r4, n2, r8);
-		} else if (lo8 == 0x0d)
-			debug("fsts\tfpul,fr%i\n", r8);
-		else if (lo8 == 0x1d)
-			debug("flds\tfr%i,fpul\n", r8);
-		else if (lo8 == 0x2d)
-			debug("float\tfpul,%sr%i\n",
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
-		else if (lo8 == 0x3d)
-			debug("ftrc\t%sr%i,fpul\n",
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
-		else if (lo8 == 0x4d)
-			debug("fneg\t%sr%i\n",
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
-		else if (lo8 == 0x5d)
-			debug("fabs\t%sr%i\n",
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
-		else if (lo8 == 0x6d)
-			debug("fsqrt\t%sr%i\n",
-			    cpu->cd.sh.fpscr & SH_FPSCR_PR? "d" : "f", r8);
-		else if (lo8 == 0x7d)
-			debug("fsrra\tfr%i\n", r8);
-		else if (lo8 == 0x8d)
-			debug("fldi0\tfr%i\n", r8);
-		else if (lo8 == 0x9d)
-			debug("fldi1\tfr%i\n", r8);
-		else if (lo8 == 0xad)
-			debug("fcnvsd\tfpul,dr%i\n", r8);
-		else if (lo8 == 0xbd)
-			debug("fcnvds\tdr%i,fpul\n", r8);
-		else if (lo8 == 0xed)
-			debug("fipr\tfv%i,fv%i\n", (r8 & 3) << 2, r8 & 0xc);
-		else if ((iword & 0x01ff) == 0x00fd)
-			debug("fsca\tfpul,dr%i\n", r8);
-		else if (iword == 0xf3fd)
-			debug("fschg\n");
-		else if (iword == 0xfbfd)
-			debug("frchg\n");
-		else if ((iword & 0xf3ff) == 0xf1fd)
-			debug("ftrv\txmtrx,fv%i\n", r8 & 0xc);
-		else if (lo4 == 0xe)
-			debug("fmac\tfr0,fr%i,fr%i\n", r4, r8);
-		else
-			debug("UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, lo8);
-		break;
-	default:debug("UNIMPLEMENTED hi4=0x%x\n", hi4);
-	}
-
-	return sizeof(iword);
-}
-
-
-#include "tmp_sh_tail.cc"
-
diff -Nru gxemul-0.6.2/src/cpus/cpu_sh_instr.c gxemul-0.7.0+dfsg/src/cpus/cpu_sh_instr.c
--- gxemul-0.6.2/src/cpus/cpu_sh_instr.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_sh_instr.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,4312 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  SH instructions.
+ *
+ *  Individual functions should keep track of cpu->n_translated_instrs.
+ *  (If no instruction was executed, then it should be decreased. If, say, 4
+ *  instructions were combined into one function and executed, then it should
+ *  be increased by 3.)
+ */
+
+
+#define	SYNCH_PC		{					\
+		int low_pc = ((size_t)ic - (size_t)cpu->cd.sh.cur_ic_page) \
+		    / sizeof(struct sh_instr_call);			\
+		cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1)			\
+		    << SH_INSTR_ALIGNMENT_SHIFT);			\
+		cpu->pc += (low_pc << SH_INSTR_ALIGNMENT_SHIFT);	\
+	}
+
+#define	ABORT_EXECUTION	  {	SYNCH_PC;				\
+				fatal("Execution aborted at: pc = 0x%08x\n", (int)cpu->pc); \
+				cpu->cd.sh.next_ic = &nothing_call;	\
+				cpu->running = false; }
+
+#define	RES_INST_IF_NOT_MD						\
+	if (!(cpu->cd.sh.sr & SH_SR_MD)) {				\
+		SYNCH_PC;						\
+		sh_exception(cpu, EXPEVT_RES_INST, 0, 0);		\
+		return;							\
+	}
+
+#define	FLOATING_POINT_AVAILABLE_CHECK					\
+	if (cpu->cd.sh.sr & SH_SR_FD) {					\
+		/*  FPU disabled: Cause exception.  */			\
+		SYNCH_PC;						\
+		if (cpu->delay_slot)					\
+			sh_exception(cpu, EXPEVT_FPU_SLOT_DISABLE, 0, 0);\
+		else							\
+			sh_exception(cpu, EXPEVT_FPU_DISABLE, 0, 0);	\
+		return;							\
+	}
+
+
+/*
+ *  nop: Nothing
+ */
+X(nop)
+{
+}
+
+
+/*
+ *  sleep:  Wait for interrupt
+ */
+X(sleep)
+{
+	RES_INST_IF_NOT_MD;
+
+	/*
+	 *  If there is an interrupt, then just return. Otherwise
+	 *  re-run the sleep instruction (after a delay).
+	 */
+	if (cpu->cd.sh.int_to_assert > 0 && !(cpu->cd.sh.sr & SH_SR_BL)
+	    && ((cpu->cd.sh.sr & SH_SR_IMASK) >> SH_SR_IMASK_SHIFT)
+	    < cpu->cd.sh.int_level)
+		return;
+
+	SYNCH_PC;
+	cpu->cd.sh.next_ic = ic;
+	cpu->is_halted = true;
+
+	cpu->wants_to_idle = true;
+	cpu->n_translated_instrs += N_DYNTRANS_IDLE_BREAK;
+	cpu->cd.sh.next_ic = &nothing_call;
+}
+
+
+/*
+ *  sett:     t = 1
+ *  sets:     s = 1
+ *  clrt:     t = 1
+ *  clrs:     s = 1
+ *  movt_rn:  rn = t
+ *  clrmac:   mach = macl = 0
+ *
+ *  arg[1] = ptr to rn
+ */
+X(sett)    { cpu->cd.sh.sr |= SH_SR_T; }
+X(sets)    { cpu->cd.sh.sr |= SH_SR_S; }
+X(clrt)    { cpu->cd.sh.sr &= ~SH_SR_T; }
+X(clrs)    { cpu->cd.sh.sr &= ~SH_SR_S; }
+X(movt_rn) { reg(ic->arg[1]) = cpu->cd.sh.sr & SH_SR_T? 1 : 0; }
+X(clrmac)  { cpu->cd.sh.macl = cpu->cd.sh.mach = 0; }
+
+
+/*
+ *  mov_rm_rn:     rn = rm
+ *  neg_rm_rn:     rn = -rm
+ *  negc_rm_rn:    rn = -rm - t, t = borrow
+ *  not_rm_rn:     rn = ~rm
+ *  swap_b_rm_rn:  rn = rm with lowest 2 bytes swapped
+ *  swap_w_rm_rn:  rn = rm with high and low 16-bit words swapped
+ *  exts_b_rm_rn:  rn = (int8_t) rm
+ *  extu_b_rm_rn:  rn = (uint8_t) rm
+ *  exts_w_rm_rn:  rn = (int16_t) rm
+ *  extu_w_rm_rn:  rn = (uint16_t) rm
+ *
+ *  arg[0] = ptr to rm
+ *  arg[1] = ptr to rn
+ */
+X(mov_rm_rn)    { reg(ic->arg[1]) = reg(ic->arg[0]); }
+X(not_rm_rn)    { reg(ic->arg[1]) = ~reg(ic->arg[0]); }
+X(neg_rm_rn)    { reg(ic->arg[1]) = -reg(ic->arg[0]); }
+X(negc_rm_rn)
+{
+	uint64_t res = 0;
+	res -= (uint64_t) reg(ic->arg[0]);
+	if (cpu->cd.sh.sr & SH_SR_T)
+		res --;
+	if ((res >> 32) & 1)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	reg(ic->arg[1]) = (uint32_t) res;
+}
+X(swap_b_rm_rn)
+{
+	uint32_t r = reg(ic->arg[0]);
+	reg(ic->arg[1]) = (r & 0xffff0000) | ((r >> 8)&0xff) | ((r&0xff) << 8);
+}
+X(swap_w_rm_rn)
+{
+	uint32_t r = reg(ic->arg[0]);
+	reg(ic->arg[1]) = (r >> 16) | (r << 16);
+}
+X(exts_b_rm_rn) { reg(ic->arg[1]) = (int8_t)reg(ic->arg[0]); }
+X(extu_b_rm_rn) { reg(ic->arg[1]) = (uint8_t)reg(ic->arg[0]); }
+X(exts_w_rm_rn) { reg(ic->arg[1]) = (int16_t)reg(ic->arg[0]); }
+X(extu_w_rm_rn) { reg(ic->arg[1]) = (uint16_t)reg(ic->arg[0]); }
+/*  Note: rm and rn are the same on these:  */
+X(extu_b_rm)    { reg(ic->arg[1]) = (uint8_t)reg(ic->arg[1]); }
+X(extu_w_rm)    { reg(ic->arg[1]) = (uint16_t)reg(ic->arg[1]); }
+
+
+/*
+ *  and_imm_r0:  r0 &= imm
+ *  xor_imm_r0:  r0 ^= imm
+ *  tst_imm_r0:  t = (r0 & imm) == 0
+ *  or_imm_r0:   r0 |= imm
+ *
+ *  arg[0] = imm
+ */
+X(and_imm_r0) { cpu->cd.sh.r[0] &= ic->arg[0]; }
+X(xor_imm_r0) { cpu->cd.sh.r[0] ^= ic->arg[0]; }
+X(or_imm_r0)  { cpu->cd.sh.r[0] |= ic->arg[0]; }
+X(tst_imm_r0)
+{
+	if (cpu->cd.sh.r[0] & ic->arg[0])
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	else
+		cpu->cd.sh.sr |= SH_SR_T;
+}
+
+
+/*
+ *  xor_b_imm_r0_gbr:  mem[r0+gbr] |= imm
+ *  or_b_imm_r0_gbr:   mem[r0+gbr] ^= imm
+ *  and_b_imm_r0_gbr:  mem[r0+gbr] &= imm
+ *
+ *  arg[0] = imm
+ */
+X(xor_b_imm_r0_gbr)
+{
+	uint32_t addr = cpu->cd.sh.gbr + cpu->cd.sh.r[0];
+	uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12];
+
+	if (p != NULL) {
+		p[addr & 0xfff] ^= ic->arg[0];
+	} else {
+		uint8_t data;
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		   sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+		data ^= ic->arg[0];
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(or_b_imm_r0_gbr)
+{
+	uint32_t addr = cpu->cd.sh.gbr + cpu->cd.sh.r[0];
+	uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12];
+
+	if (p != NULL) {
+		p[addr & 0xfff] |= ic->arg[0];
+	} else {
+		uint8_t data;
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		   sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+		data |= ic->arg[0];
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(and_b_imm_r0_gbr)
+{
+	uint32_t addr = cpu->cd.sh.gbr + cpu->cd.sh.r[0];
+	uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12];
+
+	if (p != NULL) {
+		p[addr & 0xfff] &= ic->arg[0];
+	} else {
+		uint8_t data;
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		   sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+		data &= ic->arg[0];
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+
+
+/*
+ *  mov_imm_rn:  Set rn to a signed 8-bit value
+ *  add_imm_rn:  Add a signed 8-bit value to Rn
+ *
+ *  arg[0] = int8_t imm, extended to at least int32_t
+ *  arg[1] = ptr to rn
+ */
+X(mov_imm_rn) { reg(ic->arg[1]) = ic->arg[0]; }
+X(mov_0_rn)   { reg(ic->arg[1]) = 0; }
+X(add_imm_rn) { reg(ic->arg[1]) += ic->arg[0]; }
+X(inc_rn)     { reg(ic->arg[1]) ++; }
+X(add_4_rn)   { reg(ic->arg[1]) += 4; }
+X(sub_4_rn)   { reg(ic->arg[1]) -= 4; }
+X(dec_rn)     { reg(ic->arg[1]) --; }
+
+
+/*
+ *  mov_b_rm_predec_rn:     mov.b reg,@-Rn
+ *  mov_w_rm_predec_rn:     mov.w reg,@-Rn
+ *  mov_l_rm_predec_rn:     mov.l reg,@-Rn
+ *  stc_l_rm_predec_rn_md:  mov.l reg,@-Rn, with MD status bit check
+ *
+ *  arg[0] = ptr to rm  (or other register)
+ *  arg[1] = ptr to rn
+ */
+X(mov_b_rm_predec_rn)
+{
+	uint32_t addr = reg(ic->arg[1]) - sizeof(uint8_t);
+	int8_t *p = (int8_t *) cpu->cd.sh.host_store[addr >> 12];
+	int8_t data = reg(ic->arg[0]);
+	if (p != NULL) {
+		p[addr & 0xfff] = data;
+		reg(ic->arg[1]) = addr;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+		/*  The store was ok:  */
+		reg(ic->arg[1]) = addr;
+	}
+}
+X(mov_w_rm_predec_rn)
+{
+	uint32_t addr = reg(ic->arg[1]) - sizeof(uint16_t);
+	uint16_t *p = (uint16_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint16_t data = reg(ic->arg[0]);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE16_TO_HOST(data);
+	else
+		data = BE16_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 1] = data;
+		reg(ic->arg[1]) = addr;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+		/*  The store was ok:  */
+		reg(ic->arg[1]) = addr;
+	}
+}
+X(mov_l_rm_predec_rn)
+{
+	uint32_t addr = reg(ic->arg[1]) - sizeof(uint32_t);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint32_t data = reg(ic->arg[0]);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 2] = data;
+		reg(ic->arg[1]) = addr;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+		/*  The store was ok:  */
+		reg(ic->arg[1]) = addr;
+	}
+}
+X(stc_l_rm_predec_rn_md)
+{
+	uint32_t addr = reg(ic->arg[1]) - sizeof(uint32_t);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint32_t data = reg(ic->arg[0]);
+
+	RES_INST_IF_NOT_MD;
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 2] = data;
+		reg(ic->arg[1]) = addr;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+		/*  The store was ok:  */
+		reg(ic->arg[1]) = addr;
+	}
+}
+
+
+/*
+ *  mov_l_disp_pc_rn:  Load a 32-bit value into a register,
+ *                     from an immediate address relative to the pc.
+ *
+ *  arg[0] = offset from beginning of the current pc's page
+ *  arg[1] = ptr to rn
+ */
+X(mov_l_disp_pc_rn)
+{
+	uint32_t addr = ic->arg[0] + (cpu->pc &
+	    ~((SH_IC_ENTRIES_PER_PAGE-1) << SH_INSTR_ALIGNMENT_SHIFT));
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint32_t data;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 2];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+	reg(ic->arg[1]) = data;
+}
+
+
+/*
+ *  mova_r0:  Set r0 to an address close to the program counter.
+ *
+ *  arg[0] = relative offset from beginning of the current pc's page
+ */
+X(mova_r0)
+{
+	cpu->cd.sh.r[0] = ic->arg[0] + (cpu->pc &
+	    ~((SH_IC_ENTRIES_PER_PAGE-1) << SH_INSTR_ALIGNMENT_SHIFT));
+}
+
+
+/*
+ *  mov_w_disp_pc_rn:  Load a 16-bit value into a register,
+ *                     from an immediate address relative to the pc.
+ *
+ *  arg[0] = offset from beginning of the current pc's page
+ *  arg[1] = ptr to rn
+ */
+X(mov_w_disp_pc_rn)
+{
+	uint32_t addr = ic->arg[0] + (cpu->pc &
+	    ~((SH_IC_ENTRIES_PER_PAGE-1) << SH_INSTR_ALIGNMENT_SHIFT));
+	uint16_t *p = (uint16_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint16_t data;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 1];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE16_TO_HOST(data);
+	else
+		data = BE16_TO_HOST(data);
+
+	reg(ic->arg[1]) = (int16_t)data;
+}
+
+
+/*
+ *  load_b_rm_rn:      Load an int8_t value into Rn from address Rm.
+ *  load_w_rm_rn:      Load an int16_t value into Rn from address Rm.
+ *  load_l_rm_rn:      Load a 32-bit value into Rn from address Rm.
+ *  fmov_rm_frn:       Load a floating point value into FRn from address Rm.
+ *  fmov_r0_rm_frn:    Load a floating point value into FRn from address R0+Rm.
+ *  fmov_rm_postinc_frn: Load a floating point value into FRn from address Rm.
+ *  mov_b_r0_rm_rn:    Load an int8_t value into Rn from address Rm + R0.
+ *  mov_w_r0_rm_rn:    Load an int16_t value into Rn from address Rm + R0.
+ *  mov_l_r0_rm_rn:    Load a 32-bit value into Rn from address Rm + R0.
+ *  mov_l_disp_rm_rn:  Load a 32-bit value into Rn from address Rm + disp.
+ *  mov_b_disp_rn_r0:  Load an int8_t from Rn+disp into R0.
+ *  mov_w_disp_rn_r0:  Load an int16_t from Rn+disp into R0.
+ *  mov_b_disp_gbr_r0: Load an int8_t from GBR+disp into R0.
+ *  mov_w_disp_gbr_r0: Load an int16_t from GBR+disp into R0.
+ *  mov_l_disp_gbr_r0: Load an int32_t from GBR+disp into R0.
+ *  mov_b_arg1_postinc_to_arg0:
+ *  mov_w_arg1_postinc_to_arg0:
+ *  mov_l_arg1_postinc_to_arg0:
+ *  mov_l_arg1_postinc_to_arg0_md:  With MD (privilege level) check.
+ *  mov_l_arg1_postinc_to_arg0_fp:  With FP check.
+ *
+ *  arg[0] = ptr to rm   (or rm + (lo4 << 4) for disp)
+ *  arg[1] = ptr to rn
+ */
+X(load_b_rm_rn)
+{
+	uint32_t addr = reg(ic->arg[0]);
+	uint8_t *p = (uint8_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint8_t data;
+
+	if (p != NULL) {
+		data = p[addr & 0xfff];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+	reg(ic->arg[1]) = (int8_t) data;
+}
+X(load_w_rm_rn)
+{
+	uint32_t addr = reg(ic->arg[0]);
+	int16_t *p = (int16_t *) cpu->cd.sh.host_load[addr >> 12];
+	int16_t data;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 1];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE16_TO_HOST(data);
+	else
+		data = BE16_TO_HOST(data);
+	reg(ic->arg[1]) = data;
+}
+X(load_l_rm_rn)
+{
+	uint32_t addr = reg(ic->arg[0]);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint32_t data;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 2];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+	reg(ic->arg[1]) = data;
+}
+X(fmov_rm_frn)
+{
+	uint32_t addr = reg(ic->arg[0]);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint32_t data;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	uint32_t data2 = 0;
+	if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
+		// Register pair. Read second word first, then fallback
+		// to read the first word.
+
+		// Check if it is to an odd register first.
+		size_t r1 = ic->arg[1];
+		int ofs = (r1 - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
+		if (ofs & 1) {
+			fatal("ODD fmov_rm_frn: TODO");
+			exit(1);
+			r1 = (size_t)&cpu->cd.sh.xf[ofs & ~1];
+		}
+		
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr + 4, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+
+		data2 = data;
+		
+		// fall-through to read the first word in the pair:
+	}
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 2];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	reg(ic->arg[1]) = data;
+
+	// TODO: How about little endian: read words in opposite order?
+	if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			data2 = LE32_TO_HOST(data2);
+		else
+			data2 = BE32_TO_HOST(data2);
+		reg(ic->arg[1] + 4) = data2;
+	}
+}
+X(fmov_r0_rm_frn)
+{
+	uint32_t data, addr = reg(ic->arg[0]) + cpu->cd.sh.r[0];
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
+		fatal("fmov_r0_rm_frn: sz=1 (register pair): TODO\n");
+		ABORT_EXECUTION;
+		return;
+	}
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 2];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	reg(ic->arg[1]) = data;
+}
+X(fmov_rm_postinc_frn)
+{
+	int d = cpu->cd.sh.fpscr & SH_FPSCR_SZ;
+	uint32_t data, data2, addr = reg(ic->arg[0]);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
+	size_t r1 = ic->arg[1];
+
+	if (d) {
+		/*  xd instead of dr?  */
+		int ofs = (r1 - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
+		if (ofs & 1)
+			r1 = (size_t)&cpu->cd.sh.xf[ofs & ~1];
+	}
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 2];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	if (d) {
+		/*  Double-precision load:  */
+		addr += 4;
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned
+		    char *)&data2, sizeof(data2), MEM_READ, CACHE_DATA)) {
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			data2 = LE32_TO_HOST(data2);
+		else
+			data2 = BE32_TO_HOST(data2);
+		reg(r1 + 4) = data2;
+	}
+
+	reg(r1) = data;
+	reg(ic->arg[0]) = addr + sizeof(uint32_t);
+}
+X(mov_b_disp_gbr_r0)
+{
+	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
+	int8_t *p = (int8_t *) cpu->cd.sh.host_load[addr >> 12];
+	int8_t data;
+	if (p != NULL) {
+		data = p[addr & 0xfff];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+	cpu->cd.sh.r[0] = data;
+}
+X(mov_w_disp_gbr_r0)
+{
+	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
+	int16_t *p = (int16_t *) cpu->cd.sh.host_load[addr >> 12];
+	int16_t data;
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 1];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE16_TO_HOST(data);
+	else
+		data = BE16_TO_HOST(data);
+	cpu->cd.sh.r[0] = data;
+}
+X(mov_l_disp_gbr_r0)
+{
+	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint32_t data;
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 2];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+	cpu->cd.sh.r[0] = data;
+}
+X(mov_b_arg1_postinc_to_arg0)
+{
+	uint32_t addr = reg(ic->arg[1]);
+	int8_t *p = (int8_t *) cpu->cd.sh.host_load[addr >> 12];
+	int8_t data;
+	if (p != NULL) {
+		data = p[addr & 0xfff];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+	/*  The load was ok:  */
+	reg(ic->arg[1]) = addr + sizeof(int8_t);
+	reg(ic->arg[0]) = data;
+}
+X(mov_w_arg1_postinc_to_arg0)
+{
+	uint32_t addr = reg(ic->arg[1]);
+	uint16_t *p = (uint16_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint16_t data;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 1];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE16_TO_HOST(data);
+	else
+		data = BE16_TO_HOST(data);
+	reg(ic->arg[1]) = addr + sizeof(data);
+	reg(ic->arg[0]) = (int16_t)data;
+}
+X(mov_l_arg1_postinc_to_arg0)
+{
+	uint32_t addr = reg(ic->arg[1]);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint32_t data;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 2];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+	/*  The load was ok:  */
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+	reg(ic->arg[1]) = addr + sizeof(data);
+	reg(ic->arg[0]) = data;
+}
+X(mov_l_arg1_postinc_to_arg0_md)
+{
+	uint32_t addr = reg(ic->arg[1]);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint32_t data;
+
+	RES_INST_IF_NOT_MD;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 2];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+	/*  The load was ok:  */
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+	reg(ic->arg[1]) = addr + sizeof(data);
+
+	/*  Special case when loading into the SR register:  */
+	if (ic->arg[0] == (size_t)&cpu->cd.sh.sr)
+		sh_update_sr(cpu, data);
+	else
+		reg(ic->arg[0]) = data;
+}
+X(mov_l_arg1_postinc_to_arg0_fp)
+{
+	uint32_t addr = reg(ic->arg[1]);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint32_t data;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 2];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+	/*  The load was ok:  */
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+	reg(ic->arg[1]) = addr + sizeof(data);
+
+	/*  Ugly special case for FPSCR:  */
+	if (ic->arg[0] == (size_t)&cpu->cd.sh.fpscr)
+		sh_update_fpscr(cpu, data);
+	else
+		reg(ic->arg[0]) = data;
+}
+X(mov_b_r0_rm_rn)
+{
+	uint32_t addr = reg(ic->arg[0]) + cpu->cd.sh.r[0];
+	int8_t *p = (int8_t *) cpu->cd.sh.host_load[addr >> 12];
+	int8_t data;
+
+	if (p != NULL) {
+		data = p[addr & 0xfff];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	reg(ic->arg[1]) = data;
+}
+X(mov_w_r0_rm_rn)
+{
+	uint32_t addr = reg(ic->arg[0]) + cpu->cd.sh.r[0];
+	int16_t *p = (int16_t *) cpu->cd.sh.host_load[addr >> 12];
+	int16_t data;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 1];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE16_TO_HOST(data);
+	else
+		data = BE16_TO_HOST(data);
+	reg(ic->arg[1]) = data;
+}
+X(mov_l_r0_rm_rn)
+{
+	uint32_t addr = reg(ic->arg[0]) + cpu->cd.sh.r[0];
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint32_t data;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 2];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+	reg(ic->arg[1]) = data;
+}
+X(mov_l_disp_rm_rn)
+{
+	uint32_t addr = cpu->cd.sh.r[ic->arg[0] & 0xf] +
+	    ((ic->arg[0] >> 4) << 2);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint32_t data;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 2];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+	reg(ic->arg[1]) = data;
+}
+X(mov_b_disp_rn_r0)
+{
+	uint32_t addr = reg(ic->arg[0]) + ic->arg[1];
+	uint8_t *p = (uint8_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint8_t data;
+
+	if (p != NULL) {
+		data = p[addr & 0xfff];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	cpu->cd.sh.r[0] = (int8_t) data;
+}
+X(mov_w_disp_rn_r0)
+{
+	uint32_t addr = reg(ic->arg[0]) + ic->arg[1];
+	uint16_t *p = (uint16_t *) cpu->cd.sh.host_load[addr >> 12];
+	uint16_t data;
+
+	if (p != NULL) {
+		data = p[(addr & 0xfff) >> 1];
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_READ, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE16_TO_HOST(data);
+	else
+		data = BE16_TO_HOST(data);
+	cpu->cd.sh.r[0] = (int16_t) data;
+}
+
+
+/*
+ *  mov_b_store_rm_rn:  Store Rm to address Rn (8-bit).
+ *  mov_w_store_rm_rn:  Store Rm to address Rn (16-bit).
+ *  mov_l_store_rm_rn:  Store Rm to address Rn (32-bit).
+ *  fmov_frm_rn:        Store FRm to address Rn.
+ *  fmov_frm_r0_rn:     Store FRm to address R0 + Rn.
+ *  fmov_frm_predec_rn: Store FRm to address Rn - 4 (or 8), update Rn.
+ *  mov_b_rm_r0_rn:     Store Rm to address Rn + R0 (8-bit).
+ *  mov_w_rm_r0_rn:     Store Rm to address Rn + R0 (16-bit).
+ *  mov_l_rm_r0_rn:     Store Rm to address Rn + R0 (32-bit).
+ *  mov_b_r0_disp_gbr:  Store R0 to address disp + GBR (8-bit).
+ *  mov_w_r0_disp_gbr:  Store R0 to address disp + GBR (16-bit).
+ *  mov_l_r0_disp_gbr:  Store R0 to address disp + GBR (32-bit).
+ *  mov_l_rm_disp_rn:   Store Rm to address disp + Rn.
+ *  mov_b_r0_disp_rn:   Store R0 to address disp + Rn (8-bit).
+ *  mov_w_r0_disp_rn:   Store R0 to address disp + Rn (16-bit).
+ *
+ *  arg[0] = ptr to rm
+ *  arg[1] = ptr to rn    (or  Rn+(disp<<4)  for mov_l_rm_disp_rn)
+ *                        (or  disp          for mov_*_r0_disp_gbr)
+ */
+X(mov_b_store_rm_rn)
+{
+	uint32_t addr = reg(ic->arg[1]);
+	uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint8_t data = reg(ic->arg[0]);
+
+	if (p != NULL) {
+		p[addr & 0xfff] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, &data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(mov_w_store_rm_rn)
+{
+	uint32_t addr = reg(ic->arg[1]);
+	uint16_t *p = (uint16_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint16_t data = reg(ic->arg[0]);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE16_TO_HOST(data);
+	else
+		data = BE16_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 1] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(mov_l_store_rm_rn)
+{
+	uint32_t addr = reg(ic->arg[1]);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint32_t data = reg(ic->arg[0]);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 2] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(fmov_frm_rn)
+{
+	uint32_t addr = reg(ic->arg[1]);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint32_t data = reg(ic->arg[0]);
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
+		// Register pair. Store second word first, then fallback
+		// to store the first word.
+
+		// Check if it is to an odd register first.
+		size_t r0 = ic->arg[1];
+		int ofs = (r0 - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
+		if (ofs & 1) {
+			fatal("ODD fmov_frm_rn: TODO");
+			exit(1);
+			r0 = (size_t)&cpu->cd.sh.xf[ofs & ~1];
+		}
+
+		uint32_t data2 = reg(ic->arg[0] + 4);
+
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr + 4, (unsigned char *)&data2,
+		    sizeof(data2), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+		
+		// fall-through to write the first word in the pair:
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 2] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(fmov_frm_r0_rn)
+{
+	uint32_t addr = reg(ic->arg[1]) + cpu->cd.sh.r[0];
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint32_t data = reg(ic->arg[0]);
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
+		fatal("fmov_frm_r0_rn: sz=1 (register pair): TODO\n");
+		ABORT_EXECUTION;
+		return;
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 2] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(fmov_frm_predec_rn)
+{
+	int d = cpu->cd.sh.fpscr & SH_FPSCR_SZ? 1 : 0;
+	uint32_t data, addr = reg(ic->arg[1]) - (d? 8 : 4);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
+	size_t r0 = ic->arg[0];
+
+	if (d) {
+		/*  xd instead of dr?  */
+		int ofs0 = (r0 - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
+		if (ofs0 & 1)
+			r0 = (size_t)&cpu->cd.sh.xf[ofs0 & ~1];
+	}
+
+	data = reg(r0);
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 2] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	if (d) {
+		/*  Store second single-precision floating point word:  */
+		data = reg(r0 + 4);
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			data = LE32_TO_HOST(data);
+		else
+			data = BE32_TO_HOST(data);
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr + 4, (unsigned
+		    char *)&data, sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+
+	reg(ic->arg[1]) = addr;
+}
+X(mov_b_rm_r0_rn)
+{
+	uint32_t addr = reg(ic->arg[1]) + cpu->cd.sh.r[0];
+	int8_t *p = (int8_t *) cpu->cd.sh.host_store[addr >> 12];
+	int8_t data = reg(ic->arg[0]);
+	if (p != NULL) {
+		p[addr & 0xfff] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(mov_w_rm_r0_rn)
+{
+	uint32_t addr = reg(ic->arg[1]) + cpu->cd.sh.r[0];
+	uint16_t *p = (uint16_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint16_t data = reg(ic->arg[0]);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE16_TO_HOST(data);
+	else
+		data = BE16_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 1] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+		return;
+		}
+	}
+}
+X(mov_l_rm_r0_rn)
+{
+	uint32_t addr = reg(ic->arg[1]) + cpu->cd.sh.r[0];
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint32_t data = reg(ic->arg[0]);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 2] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(mov_b_r0_disp_gbr)
+{
+	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
+	uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint8_t data = cpu->cd.sh.r[0];
+	if (p != NULL) {
+		p[addr & 0xfff] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(mov_w_r0_disp_gbr)
+{
+	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
+	uint16_t *p = (uint16_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint16_t data = cpu->cd.sh.r[0];
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE16_TO_HOST(data);
+	else
+		data = BE16_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 1] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(mov_l_r0_disp_gbr)
+{
+	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint32_t data = cpu->cd.sh.r[0];
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 2] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(mov_l_rm_disp_rn)
+{
+	uint32_t addr = cpu->cd.sh.r[ic->arg[1] & 0xf] +
+	    ((ic->arg[1] >> 4) << 2);
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint32_t data = reg(ic->arg[0]);
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 2] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(mov_b_r0_disp_rn)
+{
+	uint32_t addr = reg(ic->arg[0]) + ic->arg[1];
+	uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint8_t data = cpu->cd.sh.r[0];
+
+	if (p != NULL) {
+		p[addr & 0xfff] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+X(mov_w_r0_disp_rn)
+{
+	uint32_t addr = reg(ic->arg[0]) + ic->arg[1];
+	uint16_t *p = (uint16_t *) cpu->cd.sh.host_store[addr >> 12];
+	uint16_t data = cpu->cd.sh.r[0];
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE16_TO_HOST(data);
+	else
+		data = BE16_TO_HOST(data);
+
+	if (p != NULL) {
+		p[(addr & 0xfff) >> 1] = data;
+	} else {
+		SYNCH_PC;
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
+		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
+			/*  Exception.  */
+			if (!cpu->running)
+				cpu->cd.sh.next_ic = &nothing_call;
+			return;
+		}
+	}
+}
+
+
+/*
+ *  add_rm_rn:  rn = rn + rm
+ *  addc_rm_rn: rn = rn + rm + t
+ *  and_rm_rn:  rn = rn & rm
+ *  xor_rm_rn:  rn = rn ^ rm
+ *  or_rm_rn:   rn = rn | rm
+ *  sub_rm_rn:  rn = rn - rm
+ *  subc_rm_rn: rn = rn - rm - t; t = borrow
+ *  tst_rm_rn:  t = ((rm & rn) == 0)
+ *  tst_rm:     t = (rm == 0)
+ *  xtrct_rm_rn:  rn = (rn >> 16) | (rm << 16)
+ *
+ *  arg[0] = ptr to rm
+ *  arg[1] = ptr to rn
+ */
+X(add_rm_rn) { reg(ic->arg[1]) += reg(ic->arg[0]); }
+X(addc_rm_rn)
+{
+	uint64_t res = reg(ic->arg[1]);
+	res += (uint64_t) reg(ic->arg[0]);
+	if (cpu->cd.sh.sr & SH_SR_T)
+		res ++;
+	if ((res >> 32) & 1)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	reg(ic->arg[1]) = (uint32_t) res;
+}
+X(and_rm_rn) { reg(ic->arg[1]) &= reg(ic->arg[0]); }
+X(xor_rm_rn) { reg(ic->arg[1]) ^= reg(ic->arg[0]); }
+X(or_rm_rn)  { reg(ic->arg[1]) |= reg(ic->arg[0]); }
+X(sub_rm_rn) { reg(ic->arg[1]) -= reg(ic->arg[0]); }
+X(subc_rm_rn)
+{
+	uint64_t res = reg(ic->arg[1]);
+	res -= (uint64_t) reg(ic->arg[0]);
+	if (cpu->cd.sh.sr & SH_SR_T)
+		res --;
+	if ((res >> 32) & 1)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	reg(ic->arg[1]) = (uint32_t) res;
+}
+X(tst_rm_rn)
+{
+	if (reg(ic->arg[1]) & reg(ic->arg[0]))
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	else
+		cpu->cd.sh.sr |= SH_SR_T;
+}
+X(tst_rm)
+{
+	if (reg(ic->arg[0]))
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	else
+		cpu->cd.sh.sr |= SH_SR_T;
+}
+X(xtrct_rm_rn)
+{
+	uint32_t rn = reg(ic->arg[1]), rm = reg(ic->arg[0]);
+	reg(ic->arg[1]) = (rn >> 16) | (rm << 16);
+}
+
+
+/*
+ *  div0u:       Division step 0; prepare for unsigned division.
+ *  div0s_rm_rn: Division step 0; prepare for signed division.
+ *  div1_rm_rn:  Division step 1.
+ *
+ *  arg[0] = ptr to rm
+ *  arg[1] = ptr to rn
+ */
+X(div0u)
+{
+	cpu->cd.sh.sr &= ~(SH_SR_Q | SH_SR_M | SH_SR_T);
+}
+X(div0s_rm_rn)
+{
+	int q = reg(ic->arg[1]) & 0x80000000;
+	int m = reg(ic->arg[0]) & 0x80000000;
+	uint32_t new_sr = cpu->cd.sh.sr & ~(SH_SR_Q | SH_SR_M | SH_SR_T);
+	if (q)
+		new_sr |= SH_SR_Q;
+	if (m)
+		new_sr |= SH_SR_M;
+	if (m ^ q)
+		new_sr |= SH_SR_T;
+	cpu->cd.sh.sr = new_sr;
+}
+X(div1_rm_rn)
+{
+	uint32_t q, old_q = (cpu->cd.sh.sr & SH_SR_Q)? 1 : 0;
+	uint32_t m = (cpu->cd.sh.sr & SH_SR_M)? 1 : 0;
+	uint32_t t = (cpu->cd.sh.sr & SH_SR_T)? 1 : 0;
+	uint32_t op1 = reg(ic->arg[0]), op2 = reg(ic->arg[1]);
+	uint64_t op2_64;
+
+	q = op2 >> 31;
+	op2_64 = (uint32_t) ((op2 << 1) + t);
+	if (old_q == m)
+		op2_64 -= (uint64_t)op1;
+	else
+		op2_64 += (uint64_t)op1;
+	q ^= m ^ ((op2_64 >> 32) & 1);
+	t = 1 - (q ^ m);
+	cpu->cd.sh.sr &= ~(SH_SR_Q | SH_SR_T);
+	if (q)
+		cpu->cd.sh.sr |= SH_SR_Q;
+	if (t)
+		cpu->cd.sh.sr |= SH_SR_T;
+	reg(ic->arg[1]) = (uint32_t) op2_64;
+}
+
+
+/*
+ *  mul_l_rm_rn:   MACL = Rm * Rn       (32-bit)
+ *  muls_w_rm_rn:  MACL = Rm * Rn       (signed 16-bit * 16-bit ==> 32-bit)
+ *  mulu_w_rm_rn:  MACL = Rm * Rn       (unsigned 16-bit * 16-bit ==> 32-bit)
+ *  dmuls_l_rm_rn: MACH:MACL = Rm * Rn  (signed, 64-bit result)
+ *  dmulu_l_rm_rn: MACH:MACL = Rm * Rn  (unsigned, 64-bit result)
+ *
+ *  arg[0] = ptr to rm
+ *  arg[1] = ptr to rn
+ */
+X(mul_l_rm_rn)
+{
+	cpu->cd.sh.macl = reg(ic->arg[0]) * reg(ic->arg[1]);
+}
+X(muls_w_rm_rn)
+{
+	cpu->cd.sh.macl = (int32_t)(int16_t)reg(ic->arg[0]) *
+	    (int32_t)(int16_t)reg(ic->arg[1]);
+}
+X(mulu_w_rm_rn)
+{
+	cpu->cd.sh.macl = (int32_t)(uint16_t)reg(ic->arg[0]) *
+	    (int32_t)(uint16_t)reg(ic->arg[1]);
+}
+X(dmuls_l_rm_rn)
+{
+	uint64_t rm = (int32_t)reg(ic->arg[0]), rn = (int32_t)reg(ic->arg[1]);
+	uint64_t res = rm * rn;
+	cpu->cd.sh.mach = (uint32_t) (res >> 32);
+	cpu->cd.sh.macl = (uint32_t) res;
+}
+X(dmulu_l_rm_rn)
+{
+	uint64_t rm = reg(ic->arg[0]), rn = reg(ic->arg[1]), res;
+	res = rm * rn;
+	cpu->cd.sh.mach = (uint32_t) (res >> 32);
+	cpu->cd.sh.macl = (uint32_t) res;
+}
+
+
+/*
+ *  cmpeq_imm_r0:  rn == int8_t immediate
+ *  cmpeq_rm_rn:   rn == rm
+ *  cmphs_rm_rn:   rn >= rm, unsigned
+ *  cmpge_rm_rn:   rn >= rm, signed
+ *  cmphi_rm_rn:   rn > rm, unsigned
+ *  cmpgt_rm_rn:   rn > rm, signed
+ *  cmppz_rn:      rn >= 0, signed
+ *  cmppl_rn:      rn > 0, signed
+ *  cmp_str_rm_rn: t=1 if any bytes in rm and rn match, 0 otherwise
+ *
+ *  arg[0] = ptr to rm   (or imm, for cmpeq_imm_r0)
+ *  arg[1] = ptr to rn
+ */
+X(cmpeq_imm_r0)
+{
+	if (cpu->cd.sh.r[0] == (uint32_t)ic->arg[0])
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+}
+X(cmpeq_rm_rn)
+{
+	if (reg(ic->arg[1]) == reg(ic->arg[0]))
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+}
+X(cmphs_rm_rn)
+{
+	if (reg(ic->arg[1]) >= reg(ic->arg[0]))
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+}
+X(cmpge_rm_rn)
+{
+	if ((int32_t)reg(ic->arg[1]) >= (int32_t)reg(ic->arg[0]))
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+}
+X(cmphi_rm_rn)
+{
+	if (reg(ic->arg[1]) > reg(ic->arg[0]))
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+}
+X(cmpgt_rm_rn)
+{
+	if ((int32_t)reg(ic->arg[1]) > (int32_t)reg(ic->arg[0]))
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+}
+X(cmppz_rn)
+{
+	if ((int32_t)reg(ic->arg[1]) >= 0)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+}
+X(cmppl_rn)
+{
+	if ((int32_t)reg(ic->arg[1]) > 0)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+}
+X(cmp_str_rm_rn)
+{
+	uint32_t r0 = reg(ic->arg[0]), r1 = reg(ic->arg[1]);
+	int t = 0;
+	if ((r0 & 0xff000000) == (r1 & 0xff000000))
+		t = 1;
+	else if ((r0 & 0xff0000) == (r1 & 0xff0000))
+		t = 1;
+	else if ((r0 & 0xff00) == (r1 & 0xff00))
+		t = 1;
+	else if ((r0 & 0xff) == (r1 & 0xff))
+		t = 1;
+	if (t)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+}
+
+
+/*
+ *  shll_rn:  Shift rn left by 1  (t = bit that was shifted out)
+ *  shlr_rn:  Shift rn right by 1 (t = bit that was shifted out)
+ *  rotl_rn:  Shift rn left by 1  (t = bit that was shifted out)
+ *  rotr_rn:  Shift rn right by 1 (t = bit that was shifted out)
+ *  shar_rn:  Shift rn right arithmetically by 1 (t = bit that was shifted out)
+ *  shllX_rn: Shift rn left logically by X bits
+ *  shlrX_rn: Shift rn right logically by X bits
+ *  rotcl_rn: Rotate rn left via the t bit
+ *  rotcr_rn: Rotate rn right via the t bit
+ *  dt_rn:    Decrease rn; t = (rn == 0)
+ *
+ *  arg[1] = ptr to rn
+ */
+X(shll_rn)
+{
+	uint32_t rn = reg(ic->arg[1]);
+	if (rn & 0x80000000)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	reg(ic->arg[1]) = rn << 1;
+}
+X(shlr_rn)
+{
+	uint32_t rn = reg(ic->arg[1]);
+	if (rn & 1)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	reg(ic->arg[1]) = rn >> 1;
+}
+X(rotl_rn)
+{
+	uint32_t rn = reg(ic->arg[1]), x;
+	if (rn & 0x80000000) {
+		x = 1;
+		cpu->cd.sh.sr |= SH_SR_T;
+	} else {
+		x = 0;
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	}
+	reg(ic->arg[1]) = (rn << 1) | x;
+}
+X(rotr_rn)
+{
+	uint32_t rn = reg(ic->arg[1]);
+	if (rn & 1)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	reg(ic->arg[1]) = (rn >> 1) | (rn << 31);
+}
+X(shar_rn)
+{
+	int32_t rn = reg(ic->arg[1]);
+	if (rn & 1)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	reg(ic->arg[1]) = rn >> 1;
+}
+X(rotcl_rn)
+{
+	uint32_t rn = reg(ic->arg[1]), top;
+	top = rn & 0x80000000;
+	rn <<= 1;
+	if (cpu->cd.sh.sr & SH_SR_T)
+		rn ++;
+	if (top)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	reg(ic->arg[1]) = rn;
+}
+X(rotcr_rn)
+{
+	uint32_t rn = reg(ic->arg[1]), bottom;
+	bottom = rn & 1;
+	rn >>= 1;
+	if (cpu->cd.sh.sr & SH_SR_T)
+		rn |= 0x80000000;
+	if (bottom)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	reg(ic->arg[1]) = rn;
+}
+X(dt_rn)
+{
+	uint32_t rn = reg(ic->arg[1]) - 1;
+	if (rn == 0)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+	reg(ic->arg[1]) = rn;
+}
+X(shll2_rn) { reg(ic->arg[1]) <<= 2; }
+X(shll8_rn) { reg(ic->arg[1]) <<= 8; }
+X(shll16_rn) { reg(ic->arg[1]) <<= 16; }
+X(shlr2_rn) { reg(ic->arg[1]) >>= 2; }
+X(shlr8_rn) { reg(ic->arg[1]) >>= 8; }
+X(shlr16_rn) { reg(ic->arg[1]) >>= 16; }
+
+
+/*
+ *  shad: Shift Rn arithmetic left/right, as indicated by Rm. Result in Rn.
+ *  shld: Shift Rn logically left/right, as indicated by Rm. Result in Rn.
+ *
+ *  arg[0] = ptr to rm
+ *  arg[1] = ptr to rn
+ */
+X(shad)
+{
+	int32_t rn = reg(ic->arg[1]);
+	int32_t rm = reg(ic->arg[0]);
+	int sa = rm & 0x1f;
+
+	if (rm >= 0)
+		rn <<= sa;
+	else if (sa != 0)
+		rn >>= (32 - sa);
+	else if (rn < 0)
+		rn = -1;
+	else
+		rn = 0;
+
+	reg(ic->arg[1]) = rn;
+}
+X(shld)
+{
+	uint32_t rn = reg(ic->arg[1]);
+	int32_t rm = reg(ic->arg[0]);
+	int sa = rm & 0x1f;
+
+	if (rm >= 0)
+		rn <<= sa;
+	else if (sa != 0)
+		rn >>= (32 - sa);
+	else
+		rn = 0;
+
+	reg(ic->arg[1]) = rn;
+}
+
+
+/*
+ *  bra:   Branch using PC relative immediace displacement (with delay-slot)
+ *  bsr:   Like bra, but also sets PR to the return address
+ *  braf:  Like bra, but using a register instead of an immediate
+ *  bsrf:  Like braf, but also sets PR to the return address
+ *
+ *  arg[0] = immediate offset relative to start of page,
+ *           or ptr to target instruction, for samepage branches
+ *  arg[1] = ptr to Rn  (for braf/bsrf)
+ */
+X(bra)
+{
+	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+	    SH_INSTR_ALIGNMENT_SHIFT);
+	target += ic->arg[0];
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->pc = target;
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bra_samepage)
+{
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))
+		cpu->cd.sh.next_ic = (struct sh_instr_call *) ic->arg[0];
+	cpu->delay_slot = NOT_DELAYED;
+}
+X(bsr)
+{
+	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+	    SH_INSTR_ALIGNMENT_SHIFT);
+	uint32_t old_pc;
+	SYNCH_PC;
+	old_pc = cpu->pc;
+	target += ic->arg[0];
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->cd.sh.pr = old_pc + 4;
+		cpu->pc = target;
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bsr_trace)
+{
+	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+	    SH_INSTR_ALIGNMENT_SHIFT);
+	uint32_t old_pc;
+	SYNCH_PC;
+	old_pc = cpu->pc;
+	target += ic->arg[0];
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->cd.sh.pr = old_pc + 4;
+		cpu->pc = target;
+		cpu_functioncall_trace(cpu, cpu->pc);
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bsr_samepage)
+{
+	uint32_t old_pc;
+	SYNCH_PC;
+	old_pc = cpu->pc;
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->cd.sh.pr = old_pc + 4;
+		cpu->cd.sh.next_ic = (struct sh_instr_call *) ic->arg[0];
+	}
+	cpu->delay_slot = NOT_DELAYED;
+}
+X(braf_rn)
+{
+	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+	    SH_INSTR_ALIGNMENT_SHIFT);
+	target += ic->arg[0] + reg(ic->arg[1]);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->pc = target;
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bsrf_rn)
+{
+	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+	    SH_INSTR_ALIGNMENT_SHIFT);
+	uint32_t old_pc;
+	SYNCH_PC;
+	old_pc = cpu->pc;
+	target += ic->arg[0] + reg(ic->arg[1]);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->cd.sh.pr = old_pc + 4;
+		cpu->pc = target;
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bsrf_rn_trace)
+{
+	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+	    SH_INSTR_ALIGNMENT_SHIFT);
+	uint32_t old_pc;
+	SYNCH_PC;
+	old_pc = cpu->pc;
+	target += ic->arg[0] + reg(ic->arg[1]);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->cd.sh.pr = old_pc + 4;
+		cpu->pc = target;
+		cpu_functioncall_trace(cpu, cpu->pc);
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  bt: Branch if true
+ *  bf: Branch if false
+ *  bt/s: Branch if true (with delay-slot)
+ *  bf/s: Branch if false (with delay-slot)
+ *
+ *  arg[0] = immediate offset relative to start of page
+ *  arg[1] = for samepage functions, the new instruction pointer
+ */
+X(bt)
+{
+	if (cpu->cd.sh.sr & SH_SR_T) {
+		cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+		    SH_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += ic->arg[0];
+		quick_pc_to_pointers(cpu);
+	}
+}
+X(bf)
+{
+	if (!(cpu->cd.sh.sr & SH_SR_T)) {
+		cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+		    SH_INSTR_ALIGNMENT_SHIFT);
+		cpu->pc += ic->arg[0];
+		quick_pc_to_pointers(cpu);
+	}
+}
+X(bt_samepage)
+{
+	if (cpu->cd.sh.sr & SH_SR_T)
+		cpu->cd.sh.next_ic = (struct sh_instr_call *) ic->arg[1];
+}
+X(bf_samepage)
+{
+	if (!(cpu->cd.sh.sr & SH_SR_T))
+		cpu->cd.sh.next_ic = (struct sh_instr_call *) ic->arg[1];
+}
+X(bt_s)
+{
+	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+	    SH_INSTR_ALIGNMENT_SHIFT);
+	int cond = cpu->cd.sh.sr & SH_SR_T;
+	target += ic->arg[0];
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->delay_slot = NOT_DELAYED;
+		if (cond) {
+			cpu->pc = target;
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.sh.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bf_s)
+{
+	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+	    SH_INSTR_ALIGNMENT_SHIFT);
+	int cond = !(cpu->cd.sh.sr & SH_SR_T);
+	target += ic->arg[0];
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->delay_slot = NOT_DELAYED;
+		if (cond) {
+			cpu->pc = target;
+			quick_pc_to_pointers(cpu);
+		} else
+			cpu->cd.sh.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bt_s_samepage)
+{
+	int cond = cpu->cd.sh.sr & SH_SR_T;
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->delay_slot = NOT_DELAYED;
+		if (cond)
+			cpu->cd.sh.next_ic =
+			    (struct sh_instr_call *) ic->arg[1];
+		else
+			cpu->cd.sh.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(bf_s_samepage)
+{
+	int cond = !(cpu->cd.sh.sr & SH_SR_T);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->delay_slot = NOT_DELAYED;
+		if (cond)
+			cpu->cd.sh.next_ic =
+			    (struct sh_instr_call *) ic->arg[1];
+		else
+			cpu->cd.sh.next_ic ++;
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  jmp_rn: Jump to Rn
+ *  jsr_rn: Jump to Rn, store return address in PR.
+ *
+ *  arg[0] = ptr to rn
+ */
+X(jmp_rn)
+{
+	MODE_int_t target = reg(ic->arg[0]);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->pc = target;
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(jmp_rn_trace)
+{
+	MODE_int_t target = reg(ic->arg[0]);
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->pc = target;
+#if 0
+		/*  NOTE: Jmp works like both a return, and a subroutine
+		    call.  */
+		cpu_functioncall_trace_return(cpu);
+		cpu_functioncall_trace(cpu, cpu->pc);
+#endif
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(jsr_rn)
+{
+	MODE_int_t target = reg(ic->arg[0]), retaddr;
+	cpu->delay_slot = TO_BE_DELAYED;
+	retaddr = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+	    SH_INSTR_ALIGNMENT_SHIFT);
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	cpu->cd.sh.pr = retaddr + (int32_t)ic->arg[1];
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->pc = target;
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(jsr_rn_trace)
+{
+	MODE_int_t target = reg(ic->arg[0]), retaddr;
+	cpu->delay_slot = TO_BE_DELAYED;
+	retaddr = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+	    SH_INSTR_ALIGNMENT_SHIFT);
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	cpu->cd.sh.pr = retaddr + (int32_t)ic->arg[1];
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->pc = target;
+		cpu_functioncall_trace(cpu, cpu->pc);
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  rts: Jump to PR.
+ */
+X(rts)
+{
+	MODE_int_t target = cpu->cd.sh.pr;
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->pc = target;
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+X(rts_trace)
+{
+	MODE_int_t target = cpu->cd.sh.pr;
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->pc = target;
+		cpu_functioncall_trace_return(cpu);
+		cpu->delay_slot = NOT_DELAYED;
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  rte:  Return from exception.
+ */
+X(rte)
+{
+	RES_INST_IF_NOT_MD;
+
+	cpu->delay_slot = TO_BE_DELAYED;
+	ic[1].f(cpu, ic+1);
+	cpu->n_translated_instrs ++;
+	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
+		cpu->pc = cpu->cd.sh.spc;
+		cpu->delay_slot = NOT_DELAYED;
+		sh_update_sr(cpu, cpu->cd.sh.ssr);
+		quick_pc_to_pointers(cpu);
+	} else
+		cpu->delay_slot = NOT_DELAYED;
+}
+
+
+/*
+ *  ldtlb:  Load UTLB entry.
+ */
+X(ldtlb)
+{
+	uint32_t old_hi, old_lo;
+	int urc = (cpu->cd.sh.mmucr & SH4_MMUCR_URC_MASK)
+	    >> SH4_MMUCR_URC_SHIFT;
+
+	RES_INST_IF_NOT_MD;
+
+	old_hi = cpu->cd.sh.utlb_hi[urc];
+	old_lo = cpu->cd.sh.utlb_lo[urc];
+
+	cpu->cd.sh.utlb_hi[urc] = cpu->cd.sh.pteh;
+	cpu->cd.sh.utlb_lo[urc] = cpu->cd.sh.ptel;
+
+	/*  Invalidate the old mapping, if it belonged to the same ASID:  */
+	if ((old_hi & SH4_PTEH_ASID_MASK) ==
+	    (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) {
+		if ((old_lo & SH4_PTEL_SZ_MASK) == SH4_PTEL_SZ_4K)
+			cpu->invalidate_translation_caches(cpu,
+			    old_hi & 0xfffff000, INVALIDATE_VADDR);
+		else
+			cpu->invalidate_translation_caches(cpu,
+			    0, INVALIDATE_ALL);
+	}
+}
+
+
+/*
+ *  copy_privileged_register: Copy normal into privileged register, or vice
+ *                            versa, after checking the MD status bit.
+ *
+ *  arg[0] = ptr to source register
+ *  arg[1] = ptr to destination register
+ */
+X(copy_privileged_register)
+{
+	RES_INST_IF_NOT_MD;
+	reg(ic->arg[1]) = reg(ic->arg[0]);
+}
+
+
+/*
+ *  ldc_rm_sr:      Copy Rm into SR, after checking the MD status bit.
+ *
+ *  arg[1] = ptr to rm
+ */
+X(ldc_rm_sr)
+{
+	RES_INST_IF_NOT_MD;
+	sh_update_sr(cpu, reg(ic->arg[1]));
+
+#if 0
+/*  NOTE: This code causes NetBSD/landisk to get past a point where it
+    otherwise hangs, but it causes Linux/Dreamcast to bug out instead. :/  */
+
+	if (!(cpu->cd.sh.sr & SH_SR_BL) && cpu->cd.sh.int_to_assert > 0 &&
+	    ( (cpu->cd.sh.sr & SH_SR_IMASK) >> SH_SR_IMASK_SHIFT)
+	    < cpu->cd.sh.int_level) {
+		/*  Cause interrupt immediately, by dropping out of the
+		    main dyntrans loop:  */
+		cpu->cd.sh.next_ic = &nothing_call;
+	}
+#endif
+}
+
+
+/*
+ *  trapa:  Immediate trap.
+ *
+ *  arg[0] = imm << 2
+ */
+X(trapa)
+{
+	SYNCH_PC;
+
+	if (cpu->delay_slot) {
+		sh_exception(cpu, EXPEVT_SLOT_INST, 0, 0);
+		return;
+	}
+
+	cpu->cd.sh.tra = ic->arg[0];
+	sh_exception(cpu, EXPEVT_TRAPA, 0, 0);
+}
+
+
+/*
+ *  copy_fp_register:   Copy a register into another, with FP avail check.
+ *  lds_rm_fpscr:       Copy Rm into FPSCR.
+ *
+ *  arg[0] = ptr to source
+ *  arg[1] = ptr to destination
+ */
+X(copy_fp_register)
+{
+	FLOATING_POINT_AVAILABLE_CHECK;
+	reg(ic->arg[1]) = reg(ic->arg[0]);
+}
+X(lds_rm_fpscr)
+{
+	FLOATING_POINT_AVAILABLE_CHECK;
+	sh_update_fpscr(cpu, reg(ic->arg[1]));
+}
+
+
+/*
+ *  fmov_frm_frn:  Copy one floating-point register (or pair) to another.
+ *
+ *  arg[0] = ptr to source float register or pair
+ *  arg[1] = ptr to destination float register or pair
+ */
+X(fmov_frm_frn)
+{
+	size_t r0, r1;
+	int ofs0, ofs1;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	/*  Simplest case, single-precision:  */
+	if (!(cpu->cd.sh.fpscr & SH_FPSCR_SZ)) {
+		reg(ic->arg[1]) = reg(ic->arg[0]);
+		return;
+	}
+
+	/*  Double-precision:  */
+	r0 = ic->arg[0]; r1 = ic->arg[1];
+	ofs0 = (r0 - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
+	ofs1 = (r1 - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
+	if (ofs0 & 1)
+		r0 = (size_t)&cpu->cd.sh.xf[ofs0 & ~1];
+	if (ofs1 & 1)
+		r1 = (size_t)&cpu->cd.sh.xf[ofs1 & ~1];
+
+	reg(r1) = reg(r0);
+	reg(r1 + 4) = reg(r0 + 4);
+}
+
+
+/*
+ *  float_fpul_frn:  Load FPUL into float register.
+ *
+ *  arg[0] = ptr to float register, or float register pair
+ */
+X(float_fpul_frn)
+{
+	int32_t fpul = cpu->cd.sh.fpul;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
+		/*  Double-precision, using a pair of registers:  */
+		uint64_t ieee = ieee_store_float_value(fpul, IEEE_FMT_D);
+		reg(ic->arg[0]) = (uint32_t) (ieee >> 32);
+		reg(ic->arg[0] + sizeof(uint32_t)) = (uint32_t) ieee;
+	} else {
+		/*  Single-precision:  */
+		uint32_t ieee = ieee_store_float_value(fpul, IEEE_FMT_S);
+		reg(ic->arg[0]) = (uint32_t) ieee;
+	}
+}
+
+
+/*
+ *  ftrc_frm_fpul:  Truncate a float register into FPUL.
+ *
+ *  arg[0] = ptr to float register, or float register pair
+ */
+X(ftrc_frm_fpul)
+{
+	struct ieee_float_value op1;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
+		/*  Double-precision, using a pair of registers:  */
+		int64_t r1 = ((uint64_t)reg(ic->arg[0]) << 32) +
+		    reg(ic->arg[0] + sizeof(uint32_t));
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
+		cpu->cd.sh.fpul = (int32_t) op1.f;
+	} else {
+		/*  Single-precision:  */
+		ieee_interpret_float_value(reg(ic->arg[0]), &op1, IEEE_FMT_S);
+		cpu->cd.sh.fpul = (int32_t) op1.f;
+	}
+}
+
+
+/*
+ *  fcnvsd_fpul_drn:  Convert single-precision to double-precision.
+ *  fcnvds_drm_fpul:  Convert double-precision to single-precision.
+ *
+ *  arg[0] = ptr to destination (double- or single-precision float)
+ */
+X(fcnvsd_fpul_drn)
+{
+	struct ieee_float_value op1;
+	int64_t ieee;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	ieee_interpret_float_value(cpu->cd.sh.fpul, &op1, IEEE_FMT_S);
+	cpu->cd.sh.fpul = (int32_t) op1.f;
+
+	/*  Store double-precision result:  */
+	ieee = ieee_store_float_value(op1.f, IEEE_FMT_D);
+	reg(ic->arg[0]) = (uint32_t) (ieee >> 32);
+	reg(ic->arg[0] + sizeof(uint32_t)) = (uint32_t) ieee;
+}
+X(fcnvds_drm_fpul)
+{
+	struct ieee_float_value op1;
+	int64_t r1;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
+	    ((uint64_t)reg(ic->arg[0]) << 32);
+	ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
+
+	cpu->cd.sh.fpul = ieee_store_float_value(op1.f, IEEE_FMT_S);
+}
+
+
+/*
+ *  fsca_fpul_drn:  Sinus/cosinus approximation.
+ *
+ *  Note: This is an interesting instruction. It is not included in the SH4
+ *  manual. Some googling indicated that this might be an SH4X instruction.
+ *  On the other hand, it is used by Dreamcast code (and the Dreamcast has an
+ *  SH4), and a cvs comment for gdb said that this is an SH4 instruction, not
+ *  an SH4A instruction. Well well...
+ *
+ *  arg[0] = ptr to single-precision float register pair
+ */
+X(fsca_fpul_drn)
+{
+	double fpulAngle = ((double)cpu->cd.sh.fpul) * 2.0 * M_PI / 65536.0;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	reg(ic->arg[0]) = ieee_store_float_value(sin(fpulAngle), IEEE_FMT_S);
+	reg(ic->arg[0] + sizeof(uint32_t)) =
+	    ieee_store_float_value(cos(fpulAngle), IEEE_FMT_S);
+}
+
+
+/*
+ *  fipr_fvm_fvn:  Vector * vector  =>  scalar
+ *
+ *  arg[0] = ptr to FVm
+ *  arg[1] = ptr to FVn
+ *
+ *  Result of adding all   FR{m+i} * FR{n+i}  where i=0..3
+ *  is stored in FR{n+3}.
+ */
+X(fipr_fvm_fvn)
+{
+	struct ieee_float_value frn0, frn1, frn2, frn3;
+	struct ieee_float_value frm0, frm1, frm2, frm3;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	ieee_interpret_float_value(reg(ic->arg[0] +  0), &frm0, IEEE_FMT_S);
+	ieee_interpret_float_value(reg(ic->arg[0] +  4), &frm1, IEEE_FMT_S);
+	ieee_interpret_float_value(reg(ic->arg[0] +  8), &frm2, IEEE_FMT_S);
+	ieee_interpret_float_value(reg(ic->arg[0] + 12), &frm3, IEEE_FMT_S);
+	ieee_interpret_float_value(reg(ic->arg[1] +  0), &frn0, IEEE_FMT_S);
+	ieee_interpret_float_value(reg(ic->arg[1] +  4), &frn1, IEEE_FMT_S);
+	ieee_interpret_float_value(reg(ic->arg[1] +  8), &frn2, IEEE_FMT_S);
+	ieee_interpret_float_value(reg(ic->arg[1] + 12), &frn3, IEEE_FMT_S);
+
+	frn3.f =
+	    frm0.f * frn0.f + frm1.f * frn1.f +
+	    frm2.f * frn2.f + frm3.f * frn3.f;
+
+	reg(ic->arg[1] + 12) = ieee_store_float_value(frn3.f, IEEE_FMT_S);
+}
+
+
+/*
+ *  ftrv_xmtrx_fvn:  Matrix * vector  ==>  vector
+ *
+ *  arg[0] = ptr to FVn
+ */
+X(ftrv_xmtrx_fvn)
+{
+	int i;
+	struct ieee_float_value xmtrx[16], frn[4];
+	double frnp0 = 0.0, frnp1 = 0.0, frnp2 = 0.0, frnp3 = 0.0;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+	// TODO: FPSCR.EN.V = 1 should cause invalid operation exception?
+
+	ieee_interpret_float_value(reg(ic->arg[0] +  0), &frn[0], IEEE_FMT_S);
+	ieee_interpret_float_value(reg(ic->arg[0] +  4), &frn[1], IEEE_FMT_S);
+	ieee_interpret_float_value(reg(ic->arg[0] +  8), &frn[2], IEEE_FMT_S);
+	ieee_interpret_float_value(reg(ic->arg[0] + 12), &frn[3], IEEE_FMT_S);
+
+	for (i=0; i<16; i++)
+		ieee_interpret_float_value(cpu->cd.sh.xf[i],
+		    &xmtrx[i], IEEE_FMT_S);
+
+	for (i=0; i<4; i++)
+		frnp0 += xmtrx[i*4].f * frn[i].f;
+
+	for (i=0; i<4; i++)
+		frnp1 += xmtrx[i*4 + 1].f * frn[i].f;
+
+	for (i=0; i<4; i++)
+		frnp2 += xmtrx[i*4 + 2].f * frn[i].f;
+
+	for (i=0; i<4; i++)
+		frnp3 += xmtrx[i*4 + 3].f * frn[i].f;
+
+	reg(ic->arg[0] +  0) = ieee_store_float_value(frnp0, IEEE_FMT_S);
+	reg(ic->arg[0] +  4) = ieee_store_float_value(frnp1, IEEE_FMT_S);
+	reg(ic->arg[0] +  8) = ieee_store_float_value(frnp2, IEEE_FMT_S);
+	reg(ic->arg[0] + 12) = ieee_store_float_value(frnp3, IEEE_FMT_S);
+}
+
+
+/*
+ *  fldi:  Load immediate (0.0 or 1.0) into floating point register.
+ *  fneg:  Negate a floating point register
+ *  fabs:  Get the absolute value of a floating point register
+ *  fsqrt: Calculate square root
+ *  fsrra: Calculate 1 / (square root)
+ *
+ *  arg[0] = ptr to fp register
+ *  arg[1] = (uint32_t) immediate value (for fldi)
+ */
+X(fldi_frn)
+{
+	FLOATING_POINT_AVAILABLE_CHECK;
+	reg(ic->arg[0]) = ic->arg[1];
+}
+X(fneg_frn)
+{
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	// Hm. If in double register mode... and the register is pointing to
+	// an _odd_ register, what happens then?
+	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
+		int ofs0 = (ic->arg[0] - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
+		if (ofs0 & 1) {
+			fatal("TODO: fneg_frn odd register in double prec. mode.\n");
+			exit(1);
+		}
+	}
+
+	/*  Note: This also works for double-precision.  */
+	reg(ic->arg[0]) ^= 0x80000000;
+}
+X(fabs_frn)
+{
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	// Hm. If in double register mode... and the register is pointing to
+	// an _odd_ register, what happens then?
+	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
+		int ofs0 = (ic->arg[0] - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
+		if (ofs0 & 1) {
+			fatal("TODO: fneg_frn odd register in double prec. mode.\n");
+			exit(1);
+		}
+	}
+
+	/*  Note: This also works for double-precision.  */
+	reg(ic->arg[0]) &= 0x7fffffff;
+}
+X(fsqrt_frn)
+{
+	struct ieee_float_value op1;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
+		/*  Double-precision:  */
+		int64_t r1, ieee;
+		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[0]) << 32);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
+		ieee = ieee_store_float_value(sqrt(op1.f), IEEE_FMT_D);
+		reg(ic->arg[0]) = (uint32_t) (ieee >> 32);
+		reg(ic->arg[0] + sizeof(uint32_t)) = (uint32_t) ieee;
+	} else {
+		/*  Single-precision:  */
+		int32_t ieee, r1 = reg(ic->arg[0]);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
+		ieee = ieee_store_float_value(sqrt(op1.f), IEEE_FMT_S);
+		reg(ic->arg[0]) = ieee;
+	}
+}
+X(fsrra_frn)
+{
+	// I'm guessing that this is 1/sqrt. That's how it is described at
+	// http://yam.20to4.net/dreamcast/hints/index.html at least.
+
+	struct ieee_float_value op1;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
+		/*  Double-precision:  */
+		fatal("Double-precision fsrra? TODO\n");
+		ABORT_EXECUTION;
+		return;
+	} else {
+		/*  Single-precision:  */
+		int32_t ieee, r1 = reg(ic->arg[0]);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
+		ieee = ieee_store_float_value(1.0f / sqrt(op1.f), IEEE_FMT_S);
+		reg(ic->arg[0]) = ieee;
+	}
+}
+
+
+/*
+ *  fadd_frm_frn:     Floating point addition.
+ *  fsub_frm_frn:     Floating point subtraction.
+ *  fmul_frm_frn:     Floating point multiplication.
+ *  fdiv_frm_frn:     Floating point division.
+ *  fmac_fr0_frm_frn: Multiply-and-accumulate.
+ *  fcmp_eq_frm_frn:  Floating point greater-than comparison.
+ *  fcmp_gt_frm_frn:  Floating point greater-than comparison.
+ *
+ *  arg[0] = ptr to float register FRm
+ *  arg[1] = ptr to float register FRn
+ */
+X(fadd_frm_frn)
+{
+	struct ieee_float_value op1, op2;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
+		/*  Double-precision, using a pair of registers:  */
+		int64_t r1, r2, ieee;
+		double result;
+
+		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[0]) << 32);
+		r2 = reg(ic->arg[1] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[1]) << 32);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
+		ieee_interpret_float_value(r2, &op2, IEEE_FMT_D);
+
+		result = op2.f + op1.f;
+		ieee = ieee_store_float_value(result, IEEE_FMT_D);
+		reg(ic->arg[1]) = (uint32_t) (ieee >> 32);
+		reg(ic->arg[1] + sizeof(uint32_t)) = (uint32_t) ieee;
+	} else {
+		/*  Single-precision:  */
+		uint32_t r1, r2, ieee;
+		double result;
+
+		r1 = reg(ic->arg[0]);
+		r2 = reg(ic->arg[1]);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
+		ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
+
+		result = op2.f + op1.f;
+		ieee = ieee_store_float_value(result, IEEE_FMT_S);
+		reg(ic->arg[1]) = (uint32_t) ieee;
+	}
+}
+X(fsub_frm_frn)
+{
+	struct ieee_float_value op1, op2;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
+		/*  Double-precision, using a pair of registers:  */
+		int64_t r1, r2, ieee;
+		double result;
+		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[0]) << 32);
+		r2 = reg(ic->arg[1] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[1]) << 32);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
+		ieee_interpret_float_value(r2, &op2, IEEE_FMT_D);
+		result = op2.f - op1.f;
+		ieee = ieee_store_float_value(result, IEEE_FMT_D);
+		reg(ic->arg[1]) = (uint32_t) (ieee >> 32);
+		reg(ic->arg[1] + sizeof(uint32_t)) = (uint32_t) ieee;
+	} else {
+		/*  Single-precision:  */
+		uint32_t r1, r2, ieee;
+		double result;
+		r1 = reg(ic->arg[0]);
+		r2 = reg(ic->arg[1]);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
+		ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
+		result = op2.f - op1.f;
+		ieee = ieee_store_float_value(result, IEEE_FMT_S);
+		reg(ic->arg[1]) = (uint32_t) ieee;
+	}
+}
+X(fmul_frm_frn)
+{
+	struct ieee_float_value op1, op2;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
+		/*  Double-precision, using a pair of registers:  */
+		int64_t r1, r2, ieee;
+		double result;
+
+		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[0]) << 32);
+		r2 = reg(ic->arg[1] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[1]) << 32);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
+		ieee_interpret_float_value(r2, &op2, IEEE_FMT_D);
+
+		result = op2.f * op1.f;
+		ieee = ieee_store_float_value(result, IEEE_FMT_D);
+		reg(ic->arg[1]) = (uint32_t) (ieee >> 32);
+		reg(ic->arg[1] + sizeof(uint32_t)) = (uint32_t) ieee;
+	} else {
+		/*  Single-precision:  */
+		uint32_t r1, r2, ieee;
+		double result;
+
+		r1 = reg(ic->arg[0]);
+		r2 = reg(ic->arg[1]);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
+		ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
+
+		result = op2.f * op1.f;
+		ieee = ieee_store_float_value(result, IEEE_FMT_S);
+		reg(ic->arg[1]) = (uint32_t) ieee;
+	}
+}
+X(fdiv_frm_frn)
+{
+	struct ieee_float_value op1, op2;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
+		/*  Double-precision, using a pair of registers:  */
+		int64_t r1, r2, ieee;
+		double result;
+
+		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[0]) << 32);
+		r2 = reg(ic->arg[1] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[1]) << 32);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
+		ieee_interpret_float_value(r2, &op2, IEEE_FMT_D);
+
+		if (op1.f != 0.0)
+			result = op2.f / op1.f;
+		else
+			result = 0.0;
+
+		ieee = ieee_store_float_value(result, IEEE_FMT_D);
+
+		reg(ic->arg[1]) = (uint32_t) (ieee >> 32);
+		reg(ic->arg[1] + sizeof(uint32_t)) = (uint32_t) ieee;
+	} else {
+		/*  Single-precision:  */
+		uint32_t r1, r2, ieee;
+		double result;
+
+		r1 = reg(ic->arg[0]);
+		r2 = reg(ic->arg[1]);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
+		ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
+
+		if (op1.f != 0.0)
+			result = op2.f / op1.f;
+		else
+			result = 0.0;
+
+		ieee = ieee_store_float_value(result, IEEE_FMT_S);
+
+		reg(ic->arg[1]) = (uint32_t) ieee;
+	}
+}
+X(fmac_fr0_frm_frn)
+{
+	struct ieee_float_value op1, op2, op0;
+	int32_t r1, r2, fr0 = cpu->cd.sh.fr[0], ieee;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	r1 = reg(ic->arg[0]), r2 = reg(ic->arg[1]);
+	ieee_interpret_float_value(fr0, &op0, IEEE_FMT_S);
+	ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
+	ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
+	ieee = ieee_store_float_value(op0.f * op1.f + op2.f, IEEE_FMT_S);
+	reg(ic->arg[1]) = ieee;
+}
+X(fcmp_eq_frm_frn)
+{
+	struct ieee_float_value op1, op2;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
+		/*  Double-precision, using a pair of registers:  */
+		int64_t r1, r2;
+		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[0]) << 32);
+		r2 = reg(ic->arg[1] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[1]) << 32);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
+		ieee_interpret_float_value(r2, &op2, IEEE_FMT_D);
+	} else {
+		/*  Single-precision:  */
+		uint32_t r1 = reg(ic->arg[0]), r2 = reg(ic->arg[1]);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
+		ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
+	}
+
+	if (op2.f == op1.f)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+}
+X(fcmp_gt_frm_frn)
+{
+	struct ieee_float_value op1, op2;
+
+	FLOATING_POINT_AVAILABLE_CHECK;
+
+	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
+		/*  Double-precision, using a pair of registers:  */
+		int64_t r1, r2;
+		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[0]) << 32);
+		r2 = reg(ic->arg[1] + sizeof(uint32_t)) +
+		    ((uint64_t)reg(ic->arg[1]) << 32);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
+		ieee_interpret_float_value(r2, &op2, IEEE_FMT_D);
+	} else {
+		/*  Single-precision:  */
+		uint32_t r1 = reg(ic->arg[0]), r2 = reg(ic->arg[1]);
+		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
+		ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
+	}
+
+	if (op2.f > op1.f)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+}
+
+
+/*
+ *  frchg:  Change floating-point register banks.
+ *  fschg:  Change floating-point register size.
+ */
+X(frchg)
+{
+	FLOATING_POINT_AVAILABLE_CHECK;
+	sh_update_fpscr(cpu, cpu->cd.sh.fpscr ^ SH_FPSCR_FR);
+}
+X(fschg)
+{
+	FLOATING_POINT_AVAILABLE_CHECK;
+	sh_update_fpscr(cpu, cpu->cd.sh.fpscr ^ SH_FPSCR_SZ);
+}
+
+
+/*
+ *  pref_rn:  Prefetch.
+ *
+ *  TODO: According to the SH4 manual, "OTLBMULTIHIT or RADDERR may be
+ *  delivered", so those things should be checked for. Not implemented yet.
+ *
+ *  arg[1] = ptr to Rn
+ */
+X(pref_rn)
+{
+	uint32_t addr = reg(ic->arg[1]), extaddr;
+	int sq_nr, ofs;
+
+	if (addr < 0xe0000000U || addr >= 0xe4000000U)
+	{
+		// printf("[ SH4 pref 0x%08x (pc = 0x%08x) ]\n", addr, (int)cpu->pc);
+		return;
+	}
+
+	SYNCH_PC;
+
+	// Calculate the external address:
+	extaddr = addr & 0x03ffffe0;
+	sq_nr = addr & 0x20? 1 : 0;
+
+	// if (addr & 0x0000001f)
+	//	debug("[ WARNING: SH4 Store Queue, addr = 0x%08x... lowest 5 "
+	//	    "bits are non-zero. Ignoring. ]\n", addr);
+
+	if (sq_nr == 0)
+		extaddr |= (((cpu->cd.sh.qacr0 >> 2) & 7) << 26);
+	else
+		extaddr |= (((cpu->cd.sh.qacr1 >> 2) & 7) << 26);
+
+	// fatal("[ SH4 pref: SQ extaddr = 0x%08x (pc = 0x%08x) ]\n", extaddr, (int)cpu->pc);
+
+	// Is the MMU turned on?
+	if (cpu->cd.sh.mmucr & SH4_MMUCR_AT) {
+		// When the SQMD bit in MMUCR is set, user access is prohibited
+		// if the MMU is enabled.
+		if (cpu->cd.sh.mmucr & SH4_MMUCR_SQMD) {
+			// In user mode? Then cause exception.
+			if (cpu->cd.sh.sr & SH_SR_MD) {
+				sh_exception(cpu, EXPEVT_RES_INST, 0, 0);
+				return;
+			}
+		}
+
+		fatal("Store Queue to external memory, when "
+		    "MMU enabled: Not yet implemented... TODO\n");
+		ABORT_EXECUTION;
+		return;
+	}
+
+	for (ofs = 0; ofs < 32; ofs += sizeof(uint32_t)) {
+		uint32_t word;
+		cpu->memory_rw(cpu, cpu->mem, 0xe0000000UL + ofs
+		    + sq_nr * 0x20, (unsigned char *)
+		    &word, sizeof(word), MEM_READ, PHYSICAL);
+		// fatal("  addr %08x: %08x\n", (extaddr + ofs), word);
+		cpu->memory_rw(cpu, cpu->mem, extaddr+ofs, (unsigned char *)
+		    &word, sizeof(word), MEM_WRITE, PHYSICAL);
+	}
+}
+
+
+/*
+ *  tas_b_rn: Test-and-Set.
+ *
+ *  arg[1] = ptr to Rn
+ */
+X(tas_b_rn)
+{
+	uint32_t addr = reg(ic->arg[1]);
+	uint8_t byte, newbyte;
+
+	SYNCH_PC;
+
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, &byte, 1, MEM_READ,
+	   CACHE_DATA)) {
+		/*  Exception.  */
+		if (!cpu->running)
+			cpu->cd.sh.next_ic = &nothing_call;
+		return;
+	}
+
+	newbyte = byte | 0x80;
+
+	if (!cpu->memory_rw(cpu, cpu->mem, addr, &newbyte, 1, MEM_WRITE,
+	   CACHE_DATA)) {
+		/*  Exception.  */
+		if (!cpu->running)
+			cpu->cd.sh.next_ic = &nothing_call;
+		return;
+	}
+
+	if (byte == 0)
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+}
+
+
+/*
+ *  prom_emul:
+ */
+X(prom_emul)
+{
+	uint32_t old_pc;
+	SYNCH_PC;
+	old_pc = cpu->pc;
+
+	switch (cpu->machine->machine_type) {
+	case MACHINE_DREAMCAST:
+		dreamcast_emul(cpu);
+		break;
+	case MACHINE_LANDISK:
+		sh_ipl_g_emul(cpu);
+		break;
+	default:
+		fatal("SH prom_emul: unimplemented machine type.\n");
+		exit(1);
+	}
+
+	if (!cpu->running) {
+		cpu->n_translated_instrs --;
+		cpu->cd.sh.next_ic = &nothing_call;
+	} else if ((uint32_t)cpu->pc != old_pc) {
+		/*  The PC value was changed by the PROM call.  */
+		quick_pc_to_pointers(cpu);
+	}
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  bt_samepage_wait_for_variable:
+ *
+ *  Loop which reads a variable in memory forever until it changes state,
+ *  can most likely only change state if an interrupt occurs. Simulate speed
+ *  by skipping ahead quickly, until the next interrupt occurs.
+ *
+ *	z:  mov.l  (X,gbr),r0		mov_l_disp_gbr_r0 with arg[1] = X
+ *          cmp/eq r0,rY		cmpeq_rm_rn with args 0 and 1 being r0 and rY
+ *          bt     x			bt_samepage with arg[1] = z
+ */
+X(bt_samepage_wait_for_variable)
+{
+	if (cpu->delay_slot) {
+		instr(mov_l_disp_gbr_r0)(cpu, ic);
+		return;
+	}
+
+	// mov_l_disp_gbr_r0:
+	// Bail out quickly if the memory is not on a readable page.
+	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
+	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
+	if (p == NULL) {
+		instr(mov_l_disp_gbr_r0)(cpu, ic);
+		return;
+	}
+
+	uint32_t data = p[(addr & 0xfff) >> 2];
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		data = LE32_TO_HOST(data);
+	else
+		data = BE32_TO_HOST(data);
+
+	cpu->cd.sh.r[0] = data;
+
+	// cmpeq_rm_rn:
+	if (reg(ic[1].arg[1]) == reg(ic[1].arg[0]))
+		cpu->cd.sh.sr |= SH_SR_T;
+	else
+		cpu->cd.sh.sr &= ~SH_SR_T;
+
+	// Loop for a "long time" if the two registered were equal.
+	if (cpu->cd.sh.sr & SH_SR_T) {
+		// Some bogus amount of instructions.
+		// TODO: Make nicer?
+		cpu->n_translated_instrs += 500;
+		cpu->cd.sh.next_ic = ic;	// "jump to z"
+	} else {
+		// otherwise, get out of the loop.
+		cpu->n_translated_instrs += 2;
+		cpu->cd.sh.next_ic = ic + 3;
+	}
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  Combine: something ending with a bt_samepage.
+ *
+ *  See comment for bt_samepage_wait_for_variable above for details.
+ */
+void COMBINE(bt_samepage)(struct cpu *cpu, struct sh_instr_call *ic, int low_addr)
+{
+	int n_back = (low_addr >> SH_INSTR_ALIGNMENT_SHIFT)
+	    & (SH_IC_ENTRIES_PER_PAGE - 1);
+
+	if (n_back < 2)
+		return;
+
+	if (ic[-2].f == instr(mov_l_disp_gbr_r0) &&
+	    ic[-1].f == instr(cmpeq_rm_rn) &&
+	    (ic[-1].arg[0] == (size_t) &cpu->cd.sh.r[0] ||
+	     ic[-1].arg[1] == (size_t) &cpu->cd.sh.r[0]) &&
+	    ic[0].arg[1] == (size_t) &ic[-2]) {
+		ic[-2].f = instr(bt_samepage_wait_for_variable);
+	}
+}
+
+
+/*****************************************************************************/
+
+
+X(end_of_page)
+{
+	/*  Update the PC:  (offset 0, but on the next page)  */
+	cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1) <<
+	    SH_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (SH_IC_ENTRIES_PER_PAGE << SH_INSTR_ALIGNMENT_SHIFT);
+
+	/*  end_of_page doesn't count as an executed instruction:  */
+	cpu->n_translated_instrs --;
+
+	/*
+	 *  Find the new physpage and update translation pointers.
+	 *
+	 *  Note: This may cause an exception, if e.g. the new page is
+	 *  not accessible.
+	 */
+	quick_pc_to_pointers(cpu);
+
+	/*  Simple jump to the next page (if we are lucky):  */
+	if (cpu->delay_slot == NOT_DELAYED)
+		return;
+
+	/*
+	 *  If we were in a delay slot, and we got an exception while doing
+	 *  quick_pc_to_pointers, then return. The function which called
+	 *  end_of_page should handle this case.
+	 */
+	if (cpu->delay_slot == EXCEPTION_IN_DELAY_SLOT)
+		return;
+
+	/*
+	 *  Tricky situation; the delay slot is on the next virtual page.
+	 *  Calling to_be_translated will translate one instruction manually,
+	 *  execute it, and then discard it.
+	 */
+	/*  fatal("[ end_of_page: delay slot across page boundary! ]\n");  */
+
+	instr(to_be_translated)(cpu, cpu->cd.sh.next_ic);
+
+	/*  The instruction in the delay slot has now executed.  */
+	/*  fatal("[ end_of_page: back from executing the delay slot, %i ]\n",
+	    cpu->delay_slot);  */
+
+	/*  Find the physpage etc of the instruction in the delay slot
+	    (or, if there was an exception, the exception handler):  */
+	quick_pc_to_pointers(cpu);
+}
+
+
+X(end_of_page2)
+{
+	/*  Synchronize PC on the _second_ instruction on the next page:  */
+	int low_pc = ((size_t)ic - (size_t)cpu->cd.sh.cur_ic_page)
+	    / sizeof(struct sh_instr_call);
+	cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1)
+	    << SH_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc += (low_pc << SH_INSTR_ALIGNMENT_SHIFT);
+
+	/*  This doesn't count as an executed instruction.  */
+	cpu->n_translated_instrs --;
+
+	quick_pc_to_pointers(cpu);
+
+	if (cpu->delay_slot == NOT_DELAYED)
+		return;
+
+	fatal("end_of_page2: fatal error, we're in a delay slot\n");
+	exit(1);
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  sh_instr_to_be_translated():
+ *
+ *  Translate an instruction word into an sh_instr_call. ic is filled in with
+ *  valid data for the translated instruction, or a "nothing" instruction if
+ *  there was a translation failure. The newly translated instruction is then
+ *  executed.
+ */
+X(to_be_translated)
+{
+	uint32_t addr, low_pc, iword;
+	unsigned char *page;
+	unsigned char ib[2];
+	int main_opcode, isize = sizeof(ib);
+	int in_crosspage_delayslot = 0, r8, r4, lo4, lo8;
+	void (*samepage_function)(struct cpu *, struct sh_instr_call *);
+
+	/*  Figure out the (virtual) address of the instruction:  */
+	low_pc = ((size_t)ic - (size_t)cpu->cd.sh.cur_ic_page)
+	    / sizeof(struct sh_instr_call);
+
+	/*  Special case for branch with delayslot on the next page:  */
+	if (cpu->delay_slot == TO_BE_DELAYED && low_pc == 0) {
+		/*  fatal("[ delay-slot translation across page "
+		    "boundary ]\n");  */
+		in_crosspage_delayslot = 1;
+	}
+
+	addr = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1)
+	    << SH_INSTR_ALIGNMENT_SHIFT);
+	addr += (low_pc << SH_INSTR_ALIGNMENT_SHIFT);
+	cpu->pc = (MODE_int_t)addr;
+	addr &= ~((1 << SH_INSTR_ALIGNMENT_SHIFT) - 1);
+
+	/*  Read the instruction word from memory:  */
+	page = cpu->cd.sh.host_load[(uint32_t)addr >> 12];
+
+	if (page != NULL) {
+		/*  fatal("TRANSLATION HIT!\n");  */
+		memcpy(ib, page + (addr & 0xfff), isize);
+	} else {
+		/*  fatal("TRANSLATION MISS!\n");  */
+		if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
+		    isize, MEM_READ, CACHE_INSTRUCTION)) {
+			fatal("to_be_translated(): read failed: TODO\n");
+			goto bad;
+		}
+	}
+
+	{
+		uint16_t *p = (uint16_t *) ib;
+		iword = *p;
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		iword = LE16_TO_HOST(iword);
+	else
+		iword = BE16_TO_HOST(iword);
+
+	main_opcode = iword >> 12;
+	r8 = (iword >> 8) & 0xf;
+	r4 = (iword >> 4) & 0xf;
+	lo8 = iword & 0xff;
+	lo4 = iword & 0xf;
+
+
+#define DYNTRANS_TO_BE_TRANSLATED_HEAD
+#include "cpu_dyntrans.c"
+#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD
+
+
+	/*
+	 *  Translate the instruction:
+	 */
+
+	/*  Default args. for many instructions:  */
+	ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];	/* m */
+	ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];	/* n */
+
+	switch (main_opcode) {
+
+	case 0x0:
+		if (lo4 == 0x4) {
+			/*  MOV.B Rm,@(R0,Rn)  */
+			ic->f = instr(mov_b_rm_r0_rn);
+		} else if (lo4 == 0x5) {
+			/*  MOV.W Rm,@(R0,Rn)  */
+			ic->f = instr(mov_w_rm_r0_rn);
+		} else if (lo4 == 0x6) {
+			/*  MOV.L Rm,@(R0,Rn)  */
+			ic->f = instr(mov_l_rm_r0_rn);
+		} else if (lo4 == 0x7) {
+			/*  MUL.L Rm,Rn  */
+			ic->f = instr(mul_l_rm_rn);
+		} else if (iword == 0x000b) {
+			if (cpu->machine->show_trace_tree)
+				ic->f = instr(rts_trace);
+			else
+				ic->f = instr(rts);
+		} else if (lo4 == 0xc) {
+			/*  MOV.B @(R0,Rm),Rn  */
+			ic->f = instr(mov_b_r0_rm_rn);
+		} else if (lo4 == 0xd) {
+			/*  MOV.W @(R0,Rm),Rn  */
+			ic->f = instr(mov_w_r0_rm_rn);
+		} else if (lo4 == 0xe) {
+			/*  MOV.L @(R0,Rm),Rn  */
+			ic->f = instr(mov_l_r0_rm_rn);
+		} else if (iword == 0x0008) {
+			/*  CLRT  */
+			ic->f = instr(clrt);
+		} else if (iword == 0x0018) {
+			/*  SETT  */
+			ic->f = instr(sett);
+		} else if (iword == 0x0019) {
+			/*  DIV0U  */
+			ic->f = instr(div0u);
+		} else if (iword == 0x001b) {
+			/*  SLEEP  */
+			ic->f = instr(sleep);
+		} else if (iword == 0x0028) {
+			/*  CLRMAC  */
+			ic->f = instr(clrmac);
+		} else if (iword == 0x002b) {
+			/*  RTE  */
+			ic->f = instr(rte);
+		} else if (iword == 0x0038) {
+			/*  LDTLB  */
+			ic->f = instr(ldtlb);
+		} else if (iword == 0x0048) {
+			/*  CLRS  */
+			ic->f = instr(clrs);
+		} else if (iword == 0x0058) {
+			/*  SETS  */
+			ic->f = instr(sets);
+		} else if ((lo8 & 0x8f) == 0x82) {
+			/*  STC Rm_BANK, Rn  */
+			ic->f = instr(copy_privileged_register);
+			ic->arg[0] = (size_t)&cpu->cd.sh.r_bank[(lo8 >> 4) & 7];
+		} else if (iword == SH_INVALID_INSTR) {
+			/*  PROM emulation (GXemul specific)  */
+			ic->f = instr(prom_emul);
+		} else {
+			switch (lo8) {
+			case 0x02:	/*  STC SR,Rn  */
+				ic->f = instr(copy_privileged_register);
+				ic->arg[0] = (size_t)&cpu->cd.sh.sr;
+				break;
+			case 0x03:	/*  BSRF Rn  */
+				if (cpu->machine->show_trace_tree)
+					ic->f = instr(bsrf_rn_trace);
+				else
+					ic->f = instr(bsrf_rn);
+
+				ic->arg[0] = (int32_t) (addr &
+				    ((SH_IC_ENTRIES_PER_PAGE-1)
+				    << SH_INSTR_ALIGNMENT_SHIFT) & ~1) + 4;
+				/*  arg[1] is Rn  */
+				break;
+			case 0x09:	/*  NOP  */
+				ic->f = instr(nop);
+				if (iword & 0x0f00) {
+					if (!cpu->translation_readahead)
+						fatal("Unimplemented NOP"
+						    " variant?\n");
+					goto bad;
+				}
+				break;
+			case 0x0a:	/*  STS MACH,Rn  */
+				ic->f = instr(mov_rm_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.mach;
+				break;
+			case 0x12:	/*  STC GBR,Rn  */
+				ic->f = instr(mov_rm_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.gbr;
+				break;
+			case 0x1a:	/*  STS MACL,Rn  */
+				ic->f = instr(mov_rm_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.macl;
+				break;
+			case 0x22:	/*  STC VBR,Rn  */
+				ic->f = instr(copy_privileged_register);
+				ic->arg[0] = (size_t)&cpu->cd.sh.vbr;
+				break;
+			case 0x23:	/*  BRAF Rn  */
+				ic->f = instr(braf_rn);
+				ic->arg[0] = (int32_t) (addr &
+				    ((SH_IC_ENTRIES_PER_PAGE-1)
+				    << SH_INSTR_ALIGNMENT_SHIFT) & ~1) + 4;
+				/*  arg[1] is Rn  */
+				break;
+			case 0x29:	/*  MOVT Rn  */
+				ic->f = instr(movt_rn);
+				break;
+			case 0x2a:	/*  STS PR,Rn  */
+				ic->f = instr(mov_rm_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.pr;
+				break;
+			case 0x32:	/*  STC SSR,Rn  */
+				ic->f = instr(copy_privileged_register);
+				ic->arg[0] = (size_t)&cpu->cd.sh.ssr;
+				break;
+			case 0x42:	/*  STC SPC,Rn  */
+				ic->f = instr(copy_privileged_register);
+				ic->arg[0] = (size_t)&cpu->cd.sh.spc;
+				break;
+			case 0x5a:	/*  STS FPUL,Rn  */
+				ic->f = instr(copy_fp_register);
+				ic->arg[0] = (size_t)&cpu->cd.sh.fpul;
+				ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];
+				break;
+			case 0x6a:	/*  STS FPSCR,Rn  */
+				ic->f = instr(copy_fp_register);
+				ic->arg[0] = (size_t)&cpu->cd.sh.fpscr;
+				ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];
+				break;
+			case 0x83:	/*  PREF @Rn  */
+				ic->f = instr(pref_rn);
+				break;
+			case 0x93:	/*  OCBI @Rn  */
+				/*  Treat as nop for now:  */
+				/*  TODO: Implement this.  */
+				ic->f = instr(nop);
+				break;
+			case 0xa3:	/*  OCBP @Rn  */
+				/*  Treat as nop for now:  */
+				/*  TODO: Implement this.  */
+				ic->f = instr(nop);
+				break;
+			case 0xb3:	/*  OCBWB @Rn  */
+				/*  Treat as nop for now:  */
+				/*  TODO: Implement this.  */
+				ic->f = instr(nop);
+				break;
+			case 0xc3:	/*  MOVCA.L R0,@Rn  */
+				/*  Treat as nop for now:  */
+				/*  TODO: Implement this.  */
+				ic->f = instr(nop);
+				break;
+			case 0xfa:	/*  STC DBR,Rn  */
+				ic->f = instr(copy_privileged_register);
+				ic->arg[0] = (size_t)&cpu->cd.sh.dbr;
+				ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];
+				break;
+			default:if (!cpu->translation_readahead)
+					fatal("Unimplemented opcode 0x%x,"
+					    "0x%03x\n", main_opcode,
+					    iword & 0xfff);
+				goto bad;
+			}
+		}
+		break;
+
+	case 0x1:
+		ic->f = instr(mov_l_rm_disp_rn);
+		ic->arg[1] = r8 + (lo4 << 4);
+		break;
+
+	case 0x2:
+		switch (lo4) {
+		case 0x0:	/*  MOV.B Rm,@Rn  */
+			ic->f = instr(mov_b_store_rm_rn);
+			break;
+		case 0x1:	/*  MOV.W Rm,@Rn  */
+			ic->f = instr(mov_w_store_rm_rn);
+			break;
+		case 0x2:	/*  MOV.L Rm,@Rn  */
+			ic->f = instr(mov_l_store_rm_rn);
+			break;
+		case 0x4:	/*  MOV.B Rm,@-Rn  */
+			ic->f = instr(mov_b_rm_predec_rn);
+			break;
+		case 0x5:	/*  MOV.W Rm,@-Rn  */
+			ic->f = instr(mov_w_rm_predec_rn);
+			break;
+		case 0x6:	/*  MOV.L Rm,@-Rn  */
+			ic->f = instr(mov_l_rm_predec_rn);
+			break;
+		case 0x7:	/*  DIV0S Rm,Rn  */
+			ic->f = instr(div0s_rm_rn);
+			break;
+		case 0x8:	/*  TST Rm,Rn  */
+			ic->f = instr(tst_rm_rn);
+			if (r8 == r4)
+				ic->f = instr(tst_rm);
+			break;
+		case 0x9:	/*  AND Rm,Rn  */
+			ic->f = instr(and_rm_rn);
+			break;
+		case 0xa:	/*  XOR Rm,Rn  */
+			ic->f = instr(xor_rm_rn);
+			break;
+		case 0xb:	/*  OR Rm,Rn  */
+			ic->f = instr(or_rm_rn);
+			break;
+		case 0xc:	/*  CMP/STR Rm,Rn  */
+			ic->f = instr(cmp_str_rm_rn);
+			break;
+		case 0xd:	/*  XTRCT Rm,Rn  */
+			ic->f = instr(xtrct_rm_rn);
+			break;
+		case 0xe:	/*  MULU.W Rm,Rn  */
+			ic->f = instr(mulu_w_rm_rn);
+			break;
+		case 0xf:	/*  MULS.W Rm,Rn  */
+			ic->f = instr(muls_w_rm_rn);
+			break;
+		default:if (!cpu->translation_readahead)
+				fatal("Unimplemented opcode 0x%x,0x%x\n",
+				    main_opcode, lo4);
+			goto bad;
+		}
+		break;
+
+	case 0x3:
+		switch (lo4) {
+		case 0x0:	/*  CMP/EQ Rm,Rn  */
+			ic->f = instr(cmpeq_rm_rn);
+			break;
+		case 0x2:	/*  CMP/HS Rm,Rn  */
+			ic->f = instr(cmphs_rm_rn);
+			break;
+		case 0x3:	/*  CMP/GE Rm,Rn  */
+			ic->f = instr(cmpge_rm_rn);
+			break;
+		case 0x4:	/*  DIV1 Rm,Rn  */
+			ic->f = instr(div1_rm_rn);
+			break;
+		case 0x5:	/*  DMULU.L Rm,Rn  */
+			ic->f = instr(dmulu_l_rm_rn);
+			break;
+		case 0x6:	/*  CMP/HI Rm,Rn  */
+			ic->f = instr(cmphi_rm_rn);
+			break;
+		case 0x7:	/*  CMP/GT Rm,Rn  */
+			ic->f = instr(cmpgt_rm_rn);
+			break;
+		case 0x8:	/*  SUB Rm,Rn  */
+			ic->f = instr(sub_rm_rn);
+			break;
+		case 0xa:	/*  SUBC Rm,Rn  */
+			ic->f = instr(subc_rm_rn);
+			break;
+		case 0xc:	/*  ADD Rm,Rn  */
+			ic->f = instr(add_rm_rn);
+			break;
+		case 0xd:	/*  DMULS.L Rm,Rn  */
+			ic->f = instr(dmuls_l_rm_rn);
+			break;
+		case 0xe:	/*  ADDC Rm,Rn  */
+			ic->f = instr(addc_rm_rn);
+			break;
+		default:if (!cpu->translation_readahead)
+				fatal("Unimplemented opcode 0x%x,0x%x\n",
+				    main_opcode, lo4);
+			goto bad;
+		}
+		break;
+
+	case 0x4:
+		if (lo4 == 0xc) {
+			ic->f = instr(shad);
+		} else if (lo4 == 0xd) {
+			ic->f = instr(shld);
+		} else if ((lo8 & 0x8f) == 0x83) {
+			/*  STC.L Rm_BANK,@-Rn  */
+			ic->f = instr(stc_l_rm_predec_rn_md);
+			ic->arg[0] = (size_t)&cpu->cd.sh.r_bank[
+			    (lo8 >> 4) & 7];	/* m */
+		} else if ((lo8 & 0x8f) == 0x87) {
+			/*   LDC.L @Rm+,Rn_BANK  */
+			ic->f = instr(mov_l_arg1_postinc_to_arg0_md);
+			ic->arg[0] = (size_t)&cpu->cd.sh.r_bank[(lo8 >> 4) & 7];
+		} else if ((lo8 & 0x8f) == 0x8e) {
+			/*  LDC Rm, Rn_BANK  */
+			ic->f = instr(copy_privileged_register);
+			ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];
+			ic->arg[1] = (size_t)&cpu->cd.sh.r_bank[(lo8 >> 4) & 7];
+		} else {
+			switch (lo8) {
+			case 0x00:	/*  SHLL Rn  */
+				ic->f = instr(shll_rn);
+				break;
+			case 0x01:	/*  SHLR Rn  */
+				ic->f = instr(shlr_rn);
+				break;
+			case 0x02:	/*  STS.L MACH,@-Rn  */
+				ic->f = instr(mov_l_rm_predec_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.mach;
+				break;
+			case 0x03:	/*  STC.L SR,@-Rn  */
+				ic->f = instr(stc_l_rm_predec_rn_md);
+				ic->arg[0] = (size_t)&cpu->cd.sh.sr;
+				break;
+			case 0x04:	/*  ROTL Rn  */
+				ic->f = instr(rotl_rn);
+				break;
+			case 0x05:	/*  ROTR Rn  */
+				ic->f = instr(rotr_rn);
+				break;
+			case 0x06:	/*  LDS.L @Rm+,MACH  */
+				ic->f = instr(mov_l_arg1_postinc_to_arg0);
+				ic->arg[0] = (size_t)&cpu->cd.sh.mach;
+				break;
+			case 0x07:	/*  LDC.L @Rm+,SR  */
+				ic->f = instr(mov_l_arg1_postinc_to_arg0_md);
+				ic->arg[0] = (size_t)&cpu->cd.sh.sr;
+				break;
+			case 0x08:	/*  SHLL2 Rn  */
+				ic->f = instr(shll2_rn);
+				break;
+			case 0x09:	/*  SHLR2 Rn  */
+				ic->f = instr(shlr2_rn);
+				break;
+			case 0x0a:	/*  LDS Rm,MACH  */
+				ic->f = instr(mov_rm_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
+				ic->arg[1] = (size_t)&cpu->cd.sh.mach;
+				break;
+			case 0x0b:	/*  JSR @Rn  */
+				if (cpu->machine->show_trace_tree)
+					ic->f = instr(jsr_rn_trace);
+				else
+					ic->f = instr(jsr_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* n */
+				ic->arg[1] = (addr & 0xffe) + 4;
+				break;
+			case 0x0e:	/*  LDC Rm,SR  */
+				ic->f = instr(ldc_rm_sr);
+				break;
+			case 0x10:	/*  DT Rn  */
+				ic->f = instr(dt_rn);
+				break;
+			case 0x11:	/*  CMP/PZ Rn  */
+				ic->f = instr(cmppz_rn);
+				break;
+			case 0x12:	/*  STS.L MACL,@-Rn  */
+				ic->f = instr(mov_l_rm_predec_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.macl;
+				break;
+			case 0x13:	/*  STC.L GBR,@-Rn  */
+				ic->f = instr(mov_l_rm_predec_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.gbr;
+				break;
+			case 0x15:	/*  CMP/PL Rn  */
+				ic->f = instr(cmppl_rn);
+				break;
+			case 0x16:	/*  LDS.L @Rm+,MACL  */
+				ic->f = instr(mov_l_arg1_postinc_to_arg0);
+				ic->arg[0] = (size_t)&cpu->cd.sh.macl;
+				break;
+			case 0x17:	/*  LDC.L @Rm+,GBR  */
+				ic->f = instr(mov_l_arg1_postinc_to_arg0);
+				ic->arg[0] = (size_t)&cpu->cd.sh.gbr;
+				break;
+			case 0x18:	/*  SHLL8 Rn  */
+				ic->f = instr(shll8_rn);
+				break;
+			case 0x19:	/*  SHLR8 Rn  */
+				ic->f = instr(shlr8_rn);
+				break;
+			case 0x1a:	/*  LDS Rm,MACL  */
+				ic->f = instr(mov_rm_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
+				ic->arg[1] = (size_t)&cpu->cd.sh.macl;
+				break;
+			case 0x1b:	/*  TAS.B @Rn  */
+				ic->f = instr(tas_b_rn);
+				break;
+			case 0x1e:	/*  LDC Rm,GBR  */
+				ic->f = instr(mov_rm_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
+				ic->arg[1] = (size_t)&cpu->cd.sh.gbr;
+				break;
+			case 0x20:	/*  SHAL Rn  */
+				ic->f = instr(shll_rn);  /*  NOTE: shll  */
+				break;
+			case 0x21:	/*  SHAR Rn  */
+				ic->f = instr(shar_rn);
+				break;
+			case 0x22:	/*  STS.L PR,@-Rn  */
+				ic->f = instr(mov_l_rm_predec_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.pr;	/* m */
+				ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];	/* n */
+				break;
+			case 0x23:	/*  STC.L VBR,@-Rn  */
+				ic->f = instr(stc_l_rm_predec_rn_md);
+				ic->arg[0] = (size_t)&cpu->cd.sh.vbr;
+				break;
+			case 0x24:	/*  ROTCL Rn  */
+				ic->f = instr(rotcl_rn);
+				break;
+			case 0x25:	/*  ROTCR Rn  */
+				ic->f = instr(rotcr_rn);
+				break;
+			case 0x26:	/*  LDS.L @Rm+,PR  */
+				ic->f = instr(mov_l_arg1_postinc_to_arg0);
+				ic->arg[0] = (size_t)&cpu->cd.sh.pr;
+				break;
+			case 0x27:	/*  LDC.L @Rm+,VBR  */
+				ic->f = instr(mov_l_arg1_postinc_to_arg0_md);
+				ic->arg[0] = (size_t)&cpu->cd.sh.vbr;
+				break;
+			case 0x28:	/*  SHLL16 Rn  */
+				ic->f = instr(shll16_rn);
+				break;
+			case 0x29:	/*  SHLR16 Rn  */
+				ic->f = instr(shlr16_rn);
+				break;
+			case 0x2a:	/*  LDS Rm,PR  */
+				ic->f = instr(mov_rm_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
+				ic->arg[1] = (size_t)&cpu->cd.sh.pr;
+				break;
+			case 0x2b:	/*  JMP @Rn  */
+				if (cpu->machine->show_trace_tree)
+					ic->f = instr(jmp_rn_trace);
+				else
+					ic->f = instr(jmp_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* n */
+				ic->arg[1] = (addr & 0xffe) + 4;
+				break;
+			case 0x2e:	/*  LDC Rm,VBR  */
+				ic->f = instr(copy_privileged_register);
+				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
+				ic->arg[1] = (size_t)&cpu->cd.sh.vbr;
+				break;
+			case 0x33:	/*  STC.L SSR,@-Rn  */
+				ic->f = instr(stc_l_rm_predec_rn_md);
+				ic->arg[0] = (size_t)&cpu->cd.sh.ssr;
+				break;
+			case 0x37:	/*  LDC.L @Rm+,SSR  */
+				ic->f = instr(mov_l_arg1_postinc_to_arg0_md);
+				ic->arg[0] = (size_t)&cpu->cd.sh.ssr;
+				break;
+			case 0x3e:	/*  LDC rm,SSR  */
+				ic->f = instr(copy_privileged_register);
+				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
+				ic->arg[1] = (size_t)&cpu->cd.sh.ssr;
+				break;
+			case 0x43:	/*  STC.L SPC,@-Rn  */
+				ic->f = instr(stc_l_rm_predec_rn_md);
+				ic->arg[0] = (size_t)&cpu->cd.sh.spc;
+				break;
+			case 0x47:	/*  LDC.L @Rm+,SPC  */
+				ic->f = instr(mov_l_arg1_postinc_to_arg0_md);
+				ic->arg[0] = (size_t)&cpu->cd.sh.spc;
+				break;
+			case 0x4e:	/*  LDC rm,SPC  */
+				ic->f = instr(copy_privileged_register);
+				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
+				ic->arg[1] = (size_t)&cpu->cd.sh.spc;
+				break;
+			case 0x52:	/*  STS.L FPUL,@-Rn  */
+				ic->f = instr(mov_l_rm_predec_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.fpul;
+				ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];	/* n */
+				break;
+			case 0x56:	/*  LDS.L @Rm+,FPUL  */
+				ic->f = instr(mov_l_arg1_postinc_to_arg0_fp);
+				ic->arg[0] = (size_t)&cpu->cd.sh.fpul;
+				break;
+			case 0x5a:	/*  LDS Rm,FPUL  */
+				ic->f = instr(copy_fp_register);
+				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
+				ic->arg[1] = (size_t)&cpu->cd.sh.fpul;
+				break;
+			case 0x62:	/*  STS.L FPSCR,@-Rn  */
+				ic->f = instr(mov_l_rm_predec_rn);
+				ic->arg[0] = (size_t)&cpu->cd.sh.fpscr;
+				ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];	/* n */
+				break;
+			case 0x66:	/*  LDS.L @Rm+,FPSCR  */
+				/*  Note: Loading into FPSCR is a specia
+				    case (need to call sh_update_fpsrc()).  */
+				ic->f = instr(mov_l_arg1_postinc_to_arg0_fp);
+				ic->arg[0] = (size_t)&cpu->cd.sh.fpscr;
+				break;
+			case 0x6a:	/*  LDS Rm,FPSCR  */
+				ic->f = instr(lds_rm_fpscr);
+				/*  arg 1 = R8 = Rm  */
+				break;
+			case 0xfa:	/*  LDC Rm,DBR  */
+				ic->f = instr(copy_privileged_register);
+				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];
+				ic->arg[1] = (size_t)&cpu->cd.sh.dbr;
+				break;
+			default:if (!cpu->translation_readahead)
+					fatal("Unimplemented opcode 0x%x,"
+					    "0x%02x\n", main_opcode, lo8);
+				goto bad;
+			}
+		}
+		break;
+
+	case 0x5:
+		ic->f = instr(mov_l_disp_rm_rn);
+		ic->arg[0] = r4 + (lo4 << 4);
+		break;
+
+	case 0x6:
+		switch (lo4) {
+		case 0x0:	/*  MOV.B @Rm,Rn  */
+			ic->f = instr(load_b_rm_rn);
+			break;
+		case 0x1:	/*  MOV.W @Rm,Rn  */
+			ic->f = instr(load_w_rm_rn);
+			break;
+		case 0x2:	/*  MOV.L @Rm,Rn  */
+			ic->f = instr(load_l_rm_rn);
+			break;
+		case 0x3:	/*  MOV Rm,Rn  */
+			ic->f = instr(mov_rm_rn);
+			break;
+		case 0x4:	/*  MOV.B @Rm+,Rn  */
+			ic->f = instr(mov_b_arg1_postinc_to_arg0);
+			/*  Note: Order  */
+			ic->arg[1] = (size_t)&cpu->cd.sh.r[r4];	/* m */
+			ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* n */
+			break;
+		case 0x5:	/*  MOV.W @Rm+,Rn  */
+			ic->f = instr(mov_w_arg1_postinc_to_arg0);
+			/*  Note: Order  */
+			ic->arg[1] = (size_t)&cpu->cd.sh.r[r4];	/* m */
+			ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* n */
+			break;
+		case 0x6:	/*  MOV.L @Rm+,Rn  */
+			ic->f = instr(mov_l_arg1_postinc_to_arg0);
+			/*  Note: Order  */
+			ic->arg[1] = (size_t)&cpu->cd.sh.r[r4];	/* m */
+			ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* n */
+			break;
+		case 0x7:	/*  NOT Rm,Rn  */
+			ic->f = instr(not_rm_rn);
+			break;
+		case 0x8:	/*  SWAP.B Rm,Rn  */
+			ic->f = instr(swap_b_rm_rn);
+			break;
+		case 0x9:	/*  SWAP.W Rm,Rn  */
+			ic->f = instr(swap_w_rm_rn);
+			break;
+		case 0xa:	/*  NEGC Rm,Rn  */
+			ic->f = instr(negc_rm_rn);
+			break;
+		case 0xb:	/*  NEG Rm,Rn  */
+			ic->f = instr(neg_rm_rn);
+			break;
+		case 0xc:	/*  EXTU.B Rm,Rn  */
+			ic->f = instr(extu_b_rm_rn);
+			if (r8 == r4)
+				ic->f = instr(extu_b_rm);
+			break;
+		case 0xd:	/*  EXTU.W Rm,Rn  */
+			ic->f = instr(extu_w_rm_rn);
+			if (r8 == r4)
+				ic->f = instr(extu_w_rm);
+			break;
+		case 0xe:	/*  EXTS.B Rm,Rn  */
+			ic->f = instr(exts_b_rm_rn);
+			break;
+		case 0xf:	/*  EXTS.W Rm,Rn  */
+			ic->f = instr(exts_w_rm_rn);
+			break;
+		default:if (!cpu->translation_readahead)
+				fatal("Unimplemented opcode 0x%x,0x%x\n",
+				    main_opcode, lo4);
+			goto bad;
+		}
+		break;
+
+	case 0x7:	/*  ADD #imm,Rn  */
+		ic->f = instr(add_imm_rn);
+		ic->arg[0] = (int8_t)lo8;
+		ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];		/* n */
+		if (lo8 == 1)
+			ic->f = instr(inc_rn);
+		if (lo8 == 4)
+			ic->f = instr(add_4_rn);
+		if (lo8 == 0xfc)
+			ic->f = instr(sub_4_rn);
+		if (lo8 == 0xff)
+			ic->f = instr(dec_rn);
+		break;
+
+	case 0x8:
+		/*  Displacement from beginning of page = default arg 0.  */
+		ic->arg[0] = (int8_t)lo8 * 2 +
+		    (addr & ((SH_IC_ENTRIES_PER_PAGE-1)
+		    << SH_INSTR_ALIGNMENT_SHIFT) & ~1) + 4;
+		samepage_function = NULL;
+
+		switch (r8) {
+		case 0x0:	/*  MOV.B R0,@(disp,Rn)  */
+			ic->f = instr(mov_b_r0_disp_rn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];	/* n */
+			ic->arg[1] = lo4;
+			break;
+		case 0x1:	/*  MOV.W R0,@(disp,Rn)  */
+			ic->f = instr(mov_w_r0_disp_rn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];	/* n */
+			ic->arg[1] = lo4 * 2;
+			break;
+		case 0x4:	/*  MOV.B @(disp,Rn),R0  */
+			ic->f = instr(mov_b_disp_rn_r0);
+			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];	/* n */
+			ic->arg[1] = lo4;
+			break;
+		case 0x5:	/*  MOV.W @(disp,Rn),R0  */
+			ic->f = instr(mov_w_disp_rn_r0);
+			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];	/* n */
+			ic->arg[1] = lo4 * 2;
+			break;
+		case 0x8:	/*  CMP/EQ #imm,R0  */
+			ic->f = instr(cmpeq_imm_r0);
+			ic->arg[0] = (int8_t)lo8;
+			break;
+		case 0x9:	/*  BT (disp,PC)  */
+			ic->f = instr(bt);
+			samepage_function = instr(bt_samepage);
+			break;
+		case 0xb:	/*  BF (disp,PC)  */
+			ic->f = instr(bf);
+			samepage_function = instr(bf_samepage);
+			break;
+		case 0xd:	/*  BT/S (disp,PC)  */
+			ic->f = instr(bt_s);
+			samepage_function = instr(bt_s_samepage);
+			break;
+		case 0xf:	/*  BF/S (disp,PC)  */
+			ic->f = instr(bf_s);
+			samepage_function = instr(bf_s_samepage);
+			break;
+		default:if (!cpu->translation_readahead)
+				fatal("Unimplemented opcode 0x%x,0x%x\n",
+				    main_opcode, r8);
+			goto bad;
+		}
+
+		/*  samepage branches:  */
+		if (samepage_function != NULL && ic->arg[0] < 0x1000 &&
+		    (addr & 0xfff) < 0xffe) {
+			ic->arg[1] = (size_t) (cpu->cd.sh.cur_ic_page +
+			    (ic->arg[0] >> SH_INSTR_ALIGNMENT_SHIFT));
+			ic->f = samepage_function;
+		}
+
+		if (ic->f == instr(bt_samepage))
+			cpu->cd.sh.combination_check = COMBINE(bt_samepage);
+
+		break;
+
+	case 0x9:	/*  MOV.W @(disp,PC),Rn  */
+		ic->f = instr(mov_w_disp_pc_rn);
+		ic->arg[0] = lo8 * 2 + (addr & ((SH_IC_ENTRIES_PER_PAGE-1)
+		    << SH_INSTR_ALIGNMENT_SHIFT) & ~1) + 4;
+
+		/*  If the word is reachable from the same page as the
+		    current address, then optimize it as a mov_imm_rn:  */
+		if (ic->arg[0] < 0x1000 && page != NULL) {
+			uint16_t *p = (uint16_t *) page;
+			uint16_t data = p[ic->arg[0] >> 1];
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+				data = LE16_TO_HOST(data);
+			else
+				data = BE16_TO_HOST(data);
+			ic->f = instr(mov_imm_rn);
+			ic->arg[0] = (int16_t) data;
+		}
+		break;
+
+	case 0xa:	/*  BRA disp  */
+	case 0xb:	/*  BSR disp  */
+		samepage_function = NULL;
+
+		switch (main_opcode) {
+		case 0xa:
+			ic->f = instr(bra);
+			samepage_function = instr(bra_samepage);
+			break;
+		case 0xb:
+			if (cpu->machine->show_trace_tree)
+				ic->f = instr(bsr_trace);
+			else
+			{
+				ic->f = instr(bsr);
+				samepage_function = instr(bsr_samepage);
+			}
+			break;
+		}
+
+		ic->arg[0] = (int32_t) ( (addr & ((SH_IC_ENTRIES_PER_PAGE-1)
+		    << SH_INSTR_ALIGNMENT_SHIFT) & ~1) + 4 +
+		    (((int32_t)(int16_t)((iword & 0xfff) << 4)) >> 3) );
+
+		/*  samepage branches:  */
+		if (samepage_function != NULL && ic->arg[0] < 0x1000 &&
+		    (addr & 0xfff) < 0xffe) {
+			ic->arg[0] = (size_t) (cpu->cd.sh.cur_ic_page +
+			    (ic->arg[0] >> SH_INSTR_ALIGNMENT_SHIFT));
+			ic->f = samepage_function;
+		}
+		break;
+
+	case 0xc:
+		switch (r8) {
+		case 0x0:
+			ic->f = instr(mov_b_r0_disp_gbr);
+			ic->arg[1] = lo8;
+			break;
+		case 0x1:
+			ic->f = instr(mov_w_r0_disp_gbr);
+			ic->arg[1] = lo8 << 1;
+			break;
+		case 0x2:
+			ic->f = instr(mov_l_r0_disp_gbr);
+			ic->arg[1] = lo8 << 2;
+			break;
+		case 0x3:
+			ic->f = instr(trapa);
+			ic->arg[0] = lo8 << 2;
+			break;
+		case 0x4:
+			ic->f = instr(mov_b_disp_gbr_r0);
+			ic->arg[1] = lo8;
+			break;
+		case 0x5:
+			ic->f = instr(mov_w_disp_gbr_r0);
+			ic->arg[1] = lo8 << 1;
+			break;
+		case 0x6:
+			ic->f = instr(mov_l_disp_gbr_r0);
+			ic->arg[1] = lo8 << 2;
+			break;
+		case 0x7:	/*  MOVA @(disp,pc),R0  */
+			ic->f = instr(mova_r0);
+			ic->arg[0] = lo8 * 4 + (addr &
+			    ((SH_IC_ENTRIES_PER_PAGE-1)
+			    << SH_INSTR_ALIGNMENT_SHIFT) & ~3) + 4;
+			break;
+		case 0x8:	/*  TST #imm,R0  */
+			ic->f = instr(tst_imm_r0);
+			ic->arg[0] = lo8;
+			break;
+		case 0x9:	/*  AND #imm,R0  */
+			ic->f = instr(and_imm_r0);
+			ic->arg[0] = lo8;
+			break;
+		case 0xa:	/*  XOR #imm,R0  */
+			ic->f = instr(xor_imm_r0);
+			ic->arg[0] = lo8;
+			break;
+		case 0xb:	/*  OR #imm,R0  */
+			ic->f = instr(or_imm_r0);
+			ic->arg[0] = lo8;
+			break;
+		case 0xd:	/*  AND.B #imm,@(R0,GBR)  */
+			ic->f = instr(and_b_imm_r0_gbr);
+			ic->arg[0] = lo8;
+			break;
+		case 0xe:	/*  XOR.B #imm,@(R0,GBR)  */
+			ic->f = instr(xor_b_imm_r0_gbr);
+			ic->arg[0] = lo8;
+			break;
+		case 0xf:	/*  OR.B #imm,@(R0,GBR)  */
+			ic->f = instr(or_b_imm_r0_gbr);
+			ic->arg[0] = lo8;
+			break;
+		default:if (!cpu->translation_readahead)
+				fatal("Unimplemented opcode 0x%x,0x%x\n",
+				    main_opcode, r8);
+			goto bad;
+		}
+		break;
+
+	case 0xd:	/*  MOV.L @(disp,PC),Rn  */
+		ic->f = instr(mov_l_disp_pc_rn);
+		ic->arg[0] = lo8 * 4 + (addr & ((SH_IC_ENTRIES_PER_PAGE-1)
+		    << SH_INSTR_ALIGNMENT_SHIFT) & ~3) + 4;
+
+		/*  If the word is reachable from the same page as the
+		    current address, then optimize it as a mov_imm_rn:  */
+		if (ic->arg[0] < 0x1000 && page != NULL) {
+			uint32_t *p = (uint32_t *) page;
+			uint32_t data = p[ic->arg[0] >> 2];
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+				data = LE32_TO_HOST(data);
+			else
+				data = BE32_TO_HOST(data);
+			ic->f = instr(mov_imm_rn);
+			ic->arg[0] = data;
+		}
+		break;
+
+	case 0xe:	/*  MOV #imm,Rn  */
+		ic->f = instr(mov_imm_rn);
+		ic->arg[0] = (int8_t)lo8;
+		ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];	/* n */
+		if (lo8 == 0)
+			ic->f = instr(mov_0_rn);
+		break;
+
+	case 0xf:
+		if (lo4 == 0x0) {
+			/*  FADD FRm,FRn  */
+			ic->f = instr(fadd_frm_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo4 == 0x1) {
+			/*  FSUB FRm,FRn  */
+			ic->f = instr(fsub_frm_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo4 == 0x2) {
+			/*  FMUL FRm,FRn  */
+			ic->f = instr(fmul_frm_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo4 == 0x3) {
+			/*  FDIV FRm,FRn  */
+			ic->f = instr(fdiv_frm_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo4 == 0x4) {
+			/*  FCMP/EQ FRm,FRn  */
+			ic->f = instr(fcmp_eq_frm_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo4 == 0x5) {
+			/*  FCMP/GT FRm,FRn  */
+			ic->f = instr(fcmp_gt_frm_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo4 == 0x6) {
+			/*  FMOV @(R0,Rm),FRn  */
+			ic->f = instr(fmov_r0_rm_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];  /* m */
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo4 == 0x7) {
+			/*  FMOV FRm,@(R0,Rn)  */
+			ic->f = instr(fmov_frm_r0_rn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];  /* m */
+			ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];
+		} else if (lo4 == 0x8) {
+			/*  FMOV @Rm,FRn  */
+			ic->f = instr(fmov_rm_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];  /* m */
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo4 == 0x9) {
+			/*  FMOV @Rm+,FRn  */
+			ic->f = instr(fmov_rm_postinc_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];  /* m */
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo4 == 0xa) {
+			/*  FMOV FRm,@Rn  */
+			ic->f = instr(fmov_frm_rn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];  /* m */
+			ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];
+		} else if (lo4 == 0xb) {
+			/*  FMOV FRm,@-Rn  */
+			ic->f = instr(fmov_frm_predec_rn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];  /* m */
+			ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];
+		} else if (lo4 == 0xc) {
+			/*  FMOV FRm,FRn  */
+			ic->f = instr(fmov_frm_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo8 == 0x0d) {
+			/*  FSTS FPUL,FRn  */
+			ic->f = instr(copy_fp_register);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fpul;
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo8 == 0x1d) {
+			/*  FLDS FRn,FPUL  */
+			ic->f = instr(copy_fp_register);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
+			ic->arg[1] = (size_t)&cpu->cd.sh.fpul;
+		} else if (lo8 == 0x2d) {
+			/*  FLOAT FPUL,FRn  */
+			ic->f = instr(float_fpul_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo8 == 0x3d) {
+			/*  FTRC FRm,FPUL  */
+			ic->f = instr(ftrc_frm_fpul);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo8 == 0x4d) {
+			/*  FNEG FRn  */
+			ic->f = instr(fneg_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo8 == 0x5d) {
+			/*  FABS FRn  */
+			ic->f = instr(fabs_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo8 == 0x6d) {
+			/*  FSQRT FRn  */
+			ic->f = instr(fsqrt_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo8 == 0x7d) {
+			/*  FSRRA FRn  */
+			ic->f = instr(fsrra_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo8 == 0x8d) {
+			/*  FLDI0 FRn  */
+			ic->f = instr(fldi_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
+			ic->arg[1] = 0x00000000;
+		} else if (lo8 == 0x9d) {
+			/*  FLDI1 FRn  */
+			ic->f = instr(fldi_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
+			ic->arg[1] = 0x3f800000;
+		} else if ((iword & 0x01ff) == 0x00ad) {
+			/*  FCNVSD FPUL,DRn  */
+			ic->f = instr(fcnvsd_fpul_drn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if ((iword & 0x01ff) == 0x00bd) {
+			/*  FCNVDS DRm,FPUL  */
+			ic->f = instr(fcnvds_drm_fpul);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (lo8 == 0xed) {
+			/*  FIPR FVm,FVn  */
+			ic->f = instr(fipr_fvm_fvn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[(r8<<2) & 0xc];  /* m */
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8 & 0xc];  /* n */
+		} else if ((iword & 0x01ff) == 0x00fd) {
+			/*  FSCA FPUL,DRn  */
+			ic->f = instr(fsca_fpul_drn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
+		} else if (iword == 0xf3fd) {
+			/*  FSCHG  */
+			ic->f = instr(fschg);
+		} else if (iword == 0xfbfd) {
+			/*  FRCHG  */
+			ic->f = instr(frchg);
+		} else if ((iword & 0xf3ff) == 0xf1fd) {
+			/*  FTRV XMTRX, FVn  */
+			ic->f = instr(ftrv_xmtrx_fvn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8 & 0xc];
+		} else if (lo4 == 0xe) {
+			/*  FMAC FR0,FRm,FRn  */
+			ic->f = instr(fmac_fr0_frm_frn);
+			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
+			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
+		} else {
+			if (!cpu->translation_readahead)
+				fatal("Unimplemented opcode 0x%x,0x%02x\n",
+				    main_opcode, lo8);
+			goto bad;
+		}
+		break;
+
+	default:if (!cpu->translation_readahead)
+			fatal("Unimplemented main opcode 0x%x\n", main_opcode);
+		goto bad;
+	}
+
+
+#define	DYNTRANS_TO_BE_TRANSLATED_TAIL
+#include "cpu_dyntrans.c"
+#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
+}
+
diff -Nru gxemul-0.6.2/src/cpus/cpu_sh_instr.cc gxemul-0.7.0+dfsg/src/cpus/cpu_sh_instr.cc
--- gxemul-0.6.2/src/cpus/cpu_sh_instr.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/cpu_sh_instr.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,4221 +0,0 @@
-/*
- *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  SH instructions.
- *
- *  Individual functions should keep track of cpu->n_translated_instrs.
- *  (If no instruction was executed, then it should be decreased. If, say, 4
- *  instructions were combined into one function and executed, then it should
- *  be increased by 3.)
- */
-
-
-#define	SYNCH_PC		{					\
-		int low_pc = ((size_t)ic - (size_t)cpu->cd.sh.cur_ic_page) \
-		    / sizeof(struct sh_instr_call);			\
-		cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1)			\
-		    << SH_INSTR_ALIGNMENT_SHIFT);			\
-		cpu->pc += (low_pc << SH_INSTR_ALIGNMENT_SHIFT);	\
-	}
-
-#define	ABORT_EXECUTION	  {	SYNCH_PC;				\
-				fatal("Execution aborted at: pc = 0x%08x\n", (int)cpu->pc); \
-				cpu->cd.sh.next_ic = &nothing_call;	\
-				cpu->running = 0;			\
-				debugger_n_steps_left_before_interaction = 0; }
-
-#define	RES_INST_IF_NOT_MD						\
-	if (!(cpu->cd.sh.sr & SH_SR_MD)) {				\
-		SYNCH_PC;						\
-		sh_exception(cpu, EXPEVT_RES_INST, 0, 0);		\
-		return;							\
-	}
-
-#define	FLOATING_POINT_AVAILABLE_CHECK					\
-	if (cpu->cd.sh.sr & SH_SR_FD) {					\
-		/*  FPU disabled: Cause exception.  */			\
-		SYNCH_PC;						\
-		if (cpu->delay_slot)					\
-			sh_exception(cpu, EXPEVT_FPU_SLOT_DISABLE, 0, 0);\
-		else							\
-			sh_exception(cpu, EXPEVT_FPU_DISABLE, 0, 0);	\
-		return;							\
-	}
-
-
-/*
- *  nop: Nothing
- */
-X(nop)
-{
-}
-
-
-/*
- *  sleep:  Wait for interrupt
- */
-X(sleep)
-{
-	RES_INST_IF_NOT_MD;
-
-	/*
-	 *  If there is an interrupt, then just return. Otherwise
-	 *  re-run the sleep instruction (after a delay).
-	 */
-	if (cpu->cd.sh.int_to_assert > 0 && !(cpu->cd.sh.sr & SH_SR_BL)
-	    && ((cpu->cd.sh.sr & SH_SR_IMASK) >> SH_SR_IMASK_SHIFT)
-	    < cpu->cd.sh.int_level)
-		return;
-
-	cpu->cd.sh.next_ic = ic;
-	cpu->is_halted = 1;
-	cpu->has_been_idling = 1;
-
-	/*
-	 *  There was no interrupt. Let the host sleep for a while.
-	 *
-	 *  TODO:
-	 *
-	 *  Think about how to actually implement this usleep stuff,
-	 *  in an SMP and/or timing accurate environment.
-	 */
-
-	if (cpu->machine->ncpus == 1) {
-		static int x = 0;
-
-		if ((++x) == 600) {
-			usleep(10);
-			x = 0;
-		}
-
-		cpu->n_translated_instrs += N_SAFE_DYNTRANS_LIMIT / 6;
-	}
-}
-
-
-/*
- *  sett:     t = 1
- *  sets:     s = 1
- *  clrt:     t = 1
- *  clrs:     s = 1
- *  movt_rn:  rn = t
- *  clrmac:   mach = macl = 0
- *
- *  arg[1] = ptr to rn
- */
-X(sett)    { cpu->cd.sh.sr |= SH_SR_T; }
-X(sets)    { cpu->cd.sh.sr |= SH_SR_S; }
-X(clrt)    { cpu->cd.sh.sr &= ~SH_SR_T; }
-X(clrs)    { cpu->cd.sh.sr &= ~SH_SR_S; }
-X(movt_rn) { reg(ic->arg[1]) = cpu->cd.sh.sr & SH_SR_T? 1 : 0; }
-X(clrmac)  { cpu->cd.sh.macl = cpu->cd.sh.mach = 0; }
-
-
-/*
- *  mov_rm_rn:     rn = rm
- *  neg_rm_rn:     rn = -rm
- *  negc_rm_rn:    rn = -rm - t, t = borrow
- *  not_rm_rn:     rn = ~rm
- *  swap_b_rm_rn:  rn = rm with lowest 2 bytes swapped
- *  swap_w_rm_rn:  rn = rm with high and low 16-bit words swapped
- *  exts_b_rm_rn:  rn = (int8_t) rm
- *  extu_b_rm_rn:  rn = (uint8_t) rm
- *  exts_w_rm_rn:  rn = (int16_t) rm
- *  extu_w_rm_rn:  rn = (uint16_t) rm
- *
- *  arg[0] = ptr to rm
- *  arg[1] = ptr to rn
- */
-X(mov_rm_rn)    { reg(ic->arg[1]) = reg(ic->arg[0]); }
-X(not_rm_rn)    { reg(ic->arg[1]) = ~reg(ic->arg[0]); }
-X(neg_rm_rn)    { reg(ic->arg[1]) = -reg(ic->arg[0]); }
-X(negc_rm_rn)
-{
-	uint64_t res = 0;
-	res -= (uint64_t) reg(ic->arg[0]);
-	if (cpu->cd.sh.sr & SH_SR_T)
-		res --;
-	if ((res >> 32) & 1)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	reg(ic->arg[1]) = (uint32_t) res;
-}
-X(swap_b_rm_rn)
-{
-	uint32_t r = reg(ic->arg[0]);
-	reg(ic->arg[1]) = (r & 0xffff0000) | ((r >> 8)&0xff) | ((r&0xff) << 8);
-}
-X(swap_w_rm_rn)
-{
-	uint32_t r = reg(ic->arg[0]);
-	reg(ic->arg[1]) = (r >> 16) | (r << 16);
-}
-X(exts_b_rm_rn) { reg(ic->arg[1]) = (int8_t)reg(ic->arg[0]); }
-X(extu_b_rm_rn) { reg(ic->arg[1]) = (uint8_t)reg(ic->arg[0]); }
-X(exts_w_rm_rn) { reg(ic->arg[1]) = (int16_t)reg(ic->arg[0]); }
-X(extu_w_rm_rn) { reg(ic->arg[1]) = (uint16_t)reg(ic->arg[0]); }
-/*  Note: rm and rn are the same on these:  */
-X(extu_b_rm)    { reg(ic->arg[1]) = (uint8_t)reg(ic->arg[1]); }
-X(extu_w_rm)    { reg(ic->arg[1]) = (uint16_t)reg(ic->arg[1]); }
-
-
-/*
- *  and_imm_r0:  r0 &= imm
- *  xor_imm_r0:  r0 ^= imm
- *  tst_imm_r0:  t = (r0 & imm) == 0
- *  or_imm_r0:   r0 |= imm
- *
- *  arg[0] = imm
- */
-X(and_imm_r0) { cpu->cd.sh.r[0] &= ic->arg[0]; }
-X(xor_imm_r0) { cpu->cd.sh.r[0] ^= ic->arg[0]; }
-X(or_imm_r0)  { cpu->cd.sh.r[0] |= ic->arg[0]; }
-X(tst_imm_r0)
-{
-	if (cpu->cd.sh.r[0] & ic->arg[0])
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	else
-		cpu->cd.sh.sr |= SH_SR_T;
-}
-
-
-/*
- *  xor_b_imm_r0_gbr:  mem[r0+gbr] |= imm
- *  or_b_imm_r0_gbr:   mem[r0+gbr] ^= imm
- *  and_b_imm_r0_gbr:  mem[r0+gbr] &= imm
- *
- *  arg[0] = imm
- */
-X(xor_b_imm_r0_gbr)
-{
-	uint32_t addr = cpu->cd.sh.gbr + cpu->cd.sh.r[0];
-	uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12];
-
-	if (p != NULL) {
-		p[addr & 0xfff] ^= ic->arg[0];
-	} else {
-		uint8_t data;
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		   sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-		data ^= ic->arg[0];
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(or_b_imm_r0_gbr)
-{
-	uint32_t addr = cpu->cd.sh.gbr + cpu->cd.sh.r[0];
-	uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12];
-
-	if (p != NULL) {
-		p[addr & 0xfff] |= ic->arg[0];
-	} else {
-		uint8_t data;
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		   sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-		data |= ic->arg[0];
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(and_b_imm_r0_gbr)
-{
-	uint32_t addr = cpu->cd.sh.gbr + cpu->cd.sh.r[0];
-	uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12];
-
-	if (p != NULL) {
-		p[addr & 0xfff] &= ic->arg[0];
-	} else {
-		uint8_t data;
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		   sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-		data &= ic->arg[0];
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-
-
-/*
- *  mov_imm_rn:  Set rn to a signed 8-bit value
- *  add_imm_rn:  Add a signed 8-bit value to Rn
- *
- *  arg[0] = int8_t imm, extended to at least int32_t
- *  arg[1] = ptr to rn
- */
-X(mov_imm_rn) { reg(ic->arg[1]) = ic->arg[0]; }
-X(mov_0_rn)   { reg(ic->arg[1]) = 0; }
-X(add_imm_rn) { reg(ic->arg[1]) += ic->arg[0]; }
-X(inc_rn)     { reg(ic->arg[1]) ++; }
-X(add_4_rn)   { reg(ic->arg[1]) += 4; }
-X(sub_4_rn)   { reg(ic->arg[1]) -= 4; }
-X(dec_rn)     { reg(ic->arg[1]) --; }
-
-
-/*
- *  mov_b_rm_predec_rn:     mov.b reg,@-Rn
- *  mov_w_rm_predec_rn:     mov.w reg,@-Rn
- *  mov_l_rm_predec_rn:     mov.l reg,@-Rn
- *  stc_l_rm_predec_rn_md:  mov.l reg,@-Rn, with MD status bit check
- *
- *  arg[0] = ptr to rm  (or other register)
- *  arg[1] = ptr to rn
- */
-X(mov_b_rm_predec_rn)
-{
-	uint32_t addr = reg(ic->arg[1]) - sizeof(uint8_t);
-	int8_t *p = (int8_t *) cpu->cd.sh.host_store[addr >> 12];
-	int8_t data = reg(ic->arg[0]);
-	if (p != NULL) {
-		p[addr & 0xfff] = data;
-		reg(ic->arg[1]) = addr;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-		/*  The store was ok:  */
-		reg(ic->arg[1]) = addr;
-	}
-}
-X(mov_w_rm_predec_rn)
-{
-	uint32_t addr = reg(ic->arg[1]) - sizeof(uint16_t);
-	uint16_t *p = (uint16_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint16_t data = reg(ic->arg[0]);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE16_TO_HOST(data);
-	else
-		data = BE16_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 1] = data;
-		reg(ic->arg[1]) = addr;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-		/*  The store was ok:  */
-		reg(ic->arg[1]) = addr;
-	}
-}
-X(mov_l_rm_predec_rn)
-{
-	uint32_t addr = reg(ic->arg[1]) - sizeof(uint32_t);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint32_t data = reg(ic->arg[0]);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 2] = data;
-		reg(ic->arg[1]) = addr;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-		/*  The store was ok:  */
-		reg(ic->arg[1]) = addr;
-	}
-}
-X(stc_l_rm_predec_rn_md)
-{
-	uint32_t addr = reg(ic->arg[1]) - sizeof(uint32_t);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint32_t data = reg(ic->arg[0]);
-
-	RES_INST_IF_NOT_MD;
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 2] = data;
-		reg(ic->arg[1]) = addr;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		   sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-		/*  The store was ok:  */
-		reg(ic->arg[1]) = addr;
-	}
-}
-
-
-/*
- *  mov_l_disp_pc_rn:  Load a 32-bit value into a register,
- *                     from an immediate address relative to the pc.
- *
- *  arg[0] = offset from beginning of the current pc's page
- *  arg[1] = ptr to rn
- */
-X(mov_l_disp_pc_rn)
-{
-	uint32_t addr = ic->arg[0] + (cpu->pc &
-	    ~((SH_IC_ENTRIES_PER_PAGE-1) << SH_INSTR_ALIGNMENT_SHIFT));
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint32_t data;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 2];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-	reg(ic->arg[1]) = data;
-}
-
-
-/*
- *  mova_r0:  Set r0 to an address close to the program counter.
- *
- *  arg[0] = relative offset from beginning of the current pc's page
- */
-X(mova_r0)
-{
-	cpu->cd.sh.r[0] = ic->arg[0] + (cpu->pc &
-	    ~((SH_IC_ENTRIES_PER_PAGE-1) << SH_INSTR_ALIGNMENT_SHIFT));
-}
-
-
-/*
- *  mov_w_disp_pc_rn:  Load a 16-bit value into a register,
- *                     from an immediate address relative to the pc.
- *
- *  arg[0] = offset from beginning of the current pc's page
- *  arg[1] = ptr to rn
- */
-X(mov_w_disp_pc_rn)
-{
-	uint32_t addr = ic->arg[0] + (cpu->pc &
-	    ~((SH_IC_ENTRIES_PER_PAGE-1) << SH_INSTR_ALIGNMENT_SHIFT));
-	uint16_t *p = (uint16_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint16_t data;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 1];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE16_TO_HOST(data);
-	else
-		data = BE16_TO_HOST(data);
-
-	reg(ic->arg[1]) = (int16_t)data;
-}
-
-
-/*
- *  load_b_rm_rn:      Load an int8_t value into Rn from address Rm.
- *  load_w_rm_rn:      Load an int16_t value into Rn from address Rm.
- *  load_l_rm_rn:      Load a 32-bit value into Rn from address Rm.
- *  fmov_rm_frn:       Load a floating point value into FRn from address Rm.
- *  fmov_r0_rm_frn:    Load a floating point value into FRn from address R0+Rm.
- *  fmov_rm_postinc_frn: Load a floating point value into FRn from address Rm.
- *  mov_b_r0_rm_rn:    Load an int8_t value into Rn from address Rm + R0.
- *  mov_w_r0_rm_rn:    Load an int16_t value into Rn from address Rm + R0.
- *  mov_l_r0_rm_rn:    Load a 32-bit value into Rn from address Rm + R0.
- *  mov_l_disp_rm_rn:  Load a 32-bit value into Rn from address Rm + disp.
- *  mov_b_disp_rn_r0:  Load an int8_t from Rn+disp into R0.
- *  mov_w_disp_rn_r0:  Load an int16_t from Rn+disp into R0.
- *  mov_b_disp_gbr_r0: Load an int8_t from GBR+disp into R0.
- *  mov_w_disp_gbr_r0: Load an int16_t from GBR+disp into R0.
- *  mov_l_disp_gbr_r0: Load an int32_t from GBR+disp into R0.
- *  mov_b_arg1_postinc_to_arg0:
- *  mov_w_arg1_postinc_to_arg0:
- *  mov_l_arg1_postinc_to_arg0:
- *  mov_l_arg1_postinc_to_arg0_md:  With MD (privilege level) check.
- *  mov_l_arg1_postinc_to_arg0_fp:  With FP check.
- *
- *  arg[0] = ptr to rm   (or rm + (lo4 << 4) for disp)
- *  arg[1] = ptr to rn
- */
-X(load_b_rm_rn)
-{
-	uint32_t addr = reg(ic->arg[0]);
-	uint8_t *p = (uint8_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint8_t data;
-
-	if (p != NULL) {
-		data = p[addr & 0xfff];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-	reg(ic->arg[1]) = (int8_t) data;
-}
-X(load_w_rm_rn)
-{
-	uint32_t addr = reg(ic->arg[0]);
-	int16_t *p = (int16_t *) cpu->cd.sh.host_load[addr >> 12];
-	int16_t data;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 1];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE16_TO_HOST(data);
-	else
-		data = BE16_TO_HOST(data);
-	reg(ic->arg[1]) = data;
-}
-X(load_l_rm_rn)
-{
-	uint32_t addr = reg(ic->arg[0]);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint32_t data;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 2];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-	reg(ic->arg[1]) = data;
-}
-X(fmov_rm_frn)
-{
-	uint32_t addr = reg(ic->arg[0]);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint32_t data;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	uint32_t data2 = 0;
-	if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
-		// Register pair. Read second word first, then fallback
-		// to read the first word.
-
-		// Check if it is to an odd register first.
-		size_t r1 = ic->arg[1];
-		int ofs = (r1 - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
-		if (ofs & 1) {
-			fatal("ODD fmov_rm_frn: TODO");
-			exit(1);
-			r1 = (size_t)&cpu->cd.sh.xf[ofs & ~1];
-		}
-		
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr + 4, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-
-		data2 = data;
-		
-		// fall-through to read the first word in the pair:
-	}
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 2];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	reg(ic->arg[1]) = data;
-
-	// TODO: How about little endian: read words in opposite order?
-	if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			data2 = LE32_TO_HOST(data2);
-		else
-			data2 = BE32_TO_HOST(data2);
-		reg(ic->arg[1] + 4) = data2;
-	}
-}
-X(fmov_r0_rm_frn)
-{
-	uint32_t data, addr = reg(ic->arg[0]) + cpu->cd.sh.r[0];
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
-		fatal("fmov_r0_rm_frn: sz=1 (register pair): TODO\n");
-		ABORT_EXECUTION;
-		return;
-	}
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 2];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	reg(ic->arg[1]) = data;
-}
-X(fmov_rm_postinc_frn)
-{
-	int d = cpu->cd.sh.fpscr & SH_FPSCR_SZ;
-	uint32_t data, data2, addr = reg(ic->arg[0]);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
-	size_t r1 = ic->arg[1];
-
-	if (d) {
-		/*  xd instead of dr?  */
-		int ofs = (r1 - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
-		if (ofs & 1)
-			r1 = (size_t)&cpu->cd.sh.xf[ofs & ~1];
-	}
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 2];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	if (d) {
-		/*  Double-precision load:  */
-		addr += 4;
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned
-		    char *)&data2, sizeof(data2), MEM_READ, CACHE_DATA))
-			return;
-
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			data2 = LE32_TO_HOST(data2);
-		else
-			data2 = BE32_TO_HOST(data2);
-		reg(r1 + 4) = data2;
-	}
-
-	reg(r1) = data;
-	reg(ic->arg[0]) = addr + sizeof(uint32_t);
-}
-X(mov_b_disp_gbr_r0)
-{
-	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
-	int8_t *p = (int8_t *) cpu->cd.sh.host_load[addr >> 12];
-	int8_t data;
-	if (p != NULL) {
-		data = p[addr & 0xfff];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-	cpu->cd.sh.r[0] = data;
-}
-X(mov_w_disp_gbr_r0)
-{
-	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
-	int16_t *p = (int16_t *) cpu->cd.sh.host_load[addr >> 12];
-	int16_t data;
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 1];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE16_TO_HOST(data);
-	else
-		data = BE16_TO_HOST(data);
-	cpu->cd.sh.r[0] = data;
-}
-X(mov_l_disp_gbr_r0)
-{
-	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint32_t data;
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 2];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-	cpu->cd.sh.r[0] = data;
-}
-X(mov_b_arg1_postinc_to_arg0)
-{
-	uint32_t addr = reg(ic->arg[1]);
-	int8_t *p = (int8_t *) cpu->cd.sh.host_load[addr >> 12];
-	int8_t data;
-	if (p != NULL) {
-		data = p[addr & 0xfff];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-	/*  The load was ok:  */
-	reg(ic->arg[1]) = addr + sizeof(int8_t);
-	reg(ic->arg[0]) = data;
-}
-X(mov_w_arg1_postinc_to_arg0)
-{
-	uint32_t addr = reg(ic->arg[1]);
-	uint16_t *p = (uint16_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint16_t data;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 1];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE16_TO_HOST(data);
-	else
-		data = BE16_TO_HOST(data);
-	reg(ic->arg[1]) = addr + sizeof(data);
-	reg(ic->arg[0]) = (int16_t)data;
-}
-X(mov_l_arg1_postinc_to_arg0)
-{
-	uint32_t addr = reg(ic->arg[1]);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint32_t data;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 2];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-	/*  The load was ok:  */
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-	reg(ic->arg[1]) = addr + sizeof(data);
-	reg(ic->arg[0]) = data;
-}
-X(mov_l_arg1_postinc_to_arg0_md)
-{
-	uint32_t addr = reg(ic->arg[1]);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint32_t data;
-
-	RES_INST_IF_NOT_MD;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 2];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-	/*  The load was ok:  */
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-	reg(ic->arg[1]) = addr + sizeof(data);
-
-	/*  Special case when loading into the SR register:  */
-	if (ic->arg[0] == (size_t)&cpu->cd.sh.sr)
-		sh_update_sr(cpu, data);
-	else
-		reg(ic->arg[0]) = data;
-}
-X(mov_l_arg1_postinc_to_arg0_fp)
-{
-	uint32_t addr = reg(ic->arg[1]);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint32_t data;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 2];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-	/*  The load was ok:  */
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-	reg(ic->arg[1]) = addr + sizeof(data);
-
-	/*  Ugly special case for FPSCR:  */
-	if (ic->arg[0] == (size_t)&cpu->cd.sh.fpscr)
-		sh_update_fpscr(cpu, data);
-	else
-		reg(ic->arg[0]) = data;
-}
-X(mov_b_r0_rm_rn)
-{
-	uint32_t addr = reg(ic->arg[0]) + cpu->cd.sh.r[0];
-	int8_t *p = (int8_t *) cpu->cd.sh.host_load[addr >> 12];
-	int8_t data;
-
-	if (p != NULL) {
-		data = p[addr & 0xfff];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	reg(ic->arg[1]) = data;
-}
-X(mov_w_r0_rm_rn)
-{
-	uint32_t addr = reg(ic->arg[0]) + cpu->cd.sh.r[0];
-	int16_t *p = (int16_t *) cpu->cd.sh.host_load[addr >> 12];
-	int16_t data;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 1];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE16_TO_HOST(data);
-	else
-		data = BE16_TO_HOST(data);
-	reg(ic->arg[1]) = data;
-}
-X(mov_l_r0_rm_rn)
-{
-	uint32_t addr = reg(ic->arg[0]) + cpu->cd.sh.r[0];
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint32_t data;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 2];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-	reg(ic->arg[1]) = data;
-}
-X(mov_l_disp_rm_rn)
-{
-	uint32_t addr = cpu->cd.sh.r[ic->arg[0] & 0xf] +
-	    ((ic->arg[0] >> 4) << 2);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint32_t data;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 2];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-	reg(ic->arg[1]) = data;
-}
-X(mov_b_disp_rn_r0)
-{
-	uint32_t addr = reg(ic->arg[0]) + ic->arg[1];
-	uint8_t *p = (uint8_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint8_t data;
-
-	if (p != NULL) {
-		data = p[addr & 0xfff];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	cpu->cd.sh.r[0] = (int8_t) data;
-}
-X(mov_w_disp_rn_r0)
-{
-	uint32_t addr = reg(ic->arg[0]) + ic->arg[1];
-	uint16_t *p = (uint16_t *) cpu->cd.sh.host_load[addr >> 12];
-	uint16_t data;
-
-	if (p != NULL) {
-		data = p[(addr & 0xfff) >> 1];
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_READ, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE16_TO_HOST(data);
-	else
-		data = BE16_TO_HOST(data);
-	cpu->cd.sh.r[0] = (int16_t) data;
-}
-
-
-/*
- *  mov_b_store_rm_rn:  Store Rm to address Rn (8-bit).
- *  mov_w_store_rm_rn:  Store Rm to address Rn (16-bit).
- *  mov_l_store_rm_rn:  Store Rm to address Rn (32-bit).
- *  fmov_frm_rn:        Store FRm to address Rn.
- *  fmov_frm_r0_rn:     Store FRm to address R0 + Rn.
- *  fmov_frm_predec_rn: Store FRm to address Rn - 4 (or 8), update Rn.
- *  mov_b_rm_r0_rn:     Store Rm to address Rn + R0 (8-bit).
- *  mov_w_rm_r0_rn:     Store Rm to address Rn + R0 (16-bit).
- *  mov_l_rm_r0_rn:     Store Rm to address Rn + R0 (32-bit).
- *  mov_b_r0_disp_gbr:  Store R0 to address disp + GBR (8-bit).
- *  mov_w_r0_disp_gbr:  Store R0 to address disp + GBR (16-bit).
- *  mov_l_r0_disp_gbr:  Store R0 to address disp + GBR (32-bit).
- *  mov_l_rm_disp_rn:   Store Rm to address disp + Rn.
- *  mov_b_r0_disp_rn:   Store R0 to address disp + Rn (8-bit).
- *  mov_w_r0_disp_rn:   Store R0 to address disp + Rn (16-bit).
- *
- *  arg[0] = ptr to rm
- *  arg[1] = ptr to rn    (or  Rn+(disp<<4)  for mov_l_rm_disp_rn)
- *                        (or  disp          for mov_*_r0_disp_gbr)
- */
-X(mov_b_store_rm_rn)
-{
-	uint32_t addr = reg(ic->arg[1]);
-	uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint8_t data = reg(ic->arg[0]);
-
-	if (p != NULL) {
-		p[addr & 0xfff] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, &data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(mov_w_store_rm_rn)
-{
-	uint32_t addr = reg(ic->arg[1]);
-	uint16_t *p = (uint16_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint16_t data = reg(ic->arg[0]);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE16_TO_HOST(data);
-	else
-		data = BE16_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 1] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(mov_l_store_rm_rn)
-{
-	uint32_t addr = reg(ic->arg[1]);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint32_t data = reg(ic->arg[0]);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 2] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(fmov_frm_rn)
-{
-	uint32_t addr = reg(ic->arg[1]);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint32_t data = reg(ic->arg[0]);
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
-		// Register pair. Store second word first, then fallback
-		// to store the first word.
-
-		// Check if it is to an odd register first.
-		size_t r0 = ic->arg[1];
-		int ofs = (r0 - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
-		if (ofs & 1) {
-			fatal("ODD fmov_frm_rn: TODO");
-			exit(1);
-			r0 = (size_t)&cpu->cd.sh.xf[ofs & ~1];
-		}
-
-		uint32_t data2 = reg(ic->arg[0] + 4);
-
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr + 4, (unsigned char *)&data2,
-		    sizeof(data2), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-		
-		// fall-through to write the first word in the pair:
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 2] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(fmov_frm_r0_rn)
-{
-	uint32_t addr = reg(ic->arg[1]) + cpu->cd.sh.r[0];
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint32_t data = reg(ic->arg[0]);
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_SZ) {
-		fatal("fmov_frm_r0_rn: sz=1 (register pair): TODO\n");
-		ABORT_EXECUTION;
-		return;
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 2] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(fmov_frm_predec_rn)
-{
-	int d = cpu->cd.sh.fpscr & SH_FPSCR_SZ? 1 : 0;
-	uint32_t data, addr = reg(ic->arg[1]) - (d? 8 : 4);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
-	size_t r0 = ic->arg[0];
-
-	if (d) {
-		/*  xd instead of dr?  */
-		int ofs0 = (r0 - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
-		if (ofs0 & 1)
-			r0 = (size_t)&cpu->cd.sh.xf[ofs0 & ~1];
-	}
-
-	data = reg(r0);
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 2] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-
-	if (d) {
-		/*  Store second single-precision floating point word:  */
-		data = reg(r0 + 4);
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			data = LE32_TO_HOST(data);
-		else
-			data = BE32_TO_HOST(data);
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr + 4, (unsigned
-		    char *)&data, sizeof(data), MEM_WRITE, CACHE_DATA))
-			return;
-	}
-
-	reg(ic->arg[1]) = addr;
-}
-X(mov_b_rm_r0_rn)
-{
-	uint32_t addr = reg(ic->arg[1]) + cpu->cd.sh.r[0];
-	int8_t *p = (int8_t *) cpu->cd.sh.host_store[addr >> 12];
-	int8_t data = reg(ic->arg[0]);
-	if (p != NULL) {
-		p[addr & 0xfff] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(mov_w_rm_r0_rn)
-{
-	uint32_t addr = reg(ic->arg[1]) + cpu->cd.sh.r[0];
-	uint16_t *p = (uint16_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint16_t data = reg(ic->arg[0]);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE16_TO_HOST(data);
-	else
-		data = BE16_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 1] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(mov_l_rm_r0_rn)
-{
-	uint32_t addr = reg(ic->arg[1]) + cpu->cd.sh.r[0];
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint32_t data = reg(ic->arg[0]);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 2] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(mov_b_r0_disp_gbr)
-{
-	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
-	uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint8_t data = cpu->cd.sh.r[0];
-	if (p != NULL) {
-		p[addr & 0xfff] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(mov_w_r0_disp_gbr)
-{
-	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
-	uint16_t *p = (uint16_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint16_t data = cpu->cd.sh.r[0];
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE16_TO_HOST(data);
-	else
-		data = BE16_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 1] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(mov_l_r0_disp_gbr)
-{
-	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint32_t data = cpu->cd.sh.r[0];
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 2] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(mov_l_rm_disp_rn)
-{
-	uint32_t addr = cpu->cd.sh.r[ic->arg[1] & 0xf] +
-	    ((ic->arg[1] >> 4) << 2);
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint32_t data = reg(ic->arg[0]);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 2] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(mov_b_r0_disp_rn)
-{
-	uint32_t addr = reg(ic->arg[0]) + ic->arg[1];
-	uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint8_t data = cpu->cd.sh.r[0];
-
-	if (p != NULL) {
-		p[addr & 0xfff] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-X(mov_w_r0_disp_rn)
-{
-	uint32_t addr = reg(ic->arg[0]) + ic->arg[1];
-	uint16_t *p = (uint16_t *) cpu->cd.sh.host_store[addr >> 12];
-	uint16_t data = cpu->cd.sh.r[0];
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE16_TO_HOST(data);
-	else
-		data = BE16_TO_HOST(data);
-
-	if (p != NULL) {
-		p[(addr & 0xfff) >> 1] = data;
-	} else {
-		SYNCH_PC;
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data,
-		    sizeof(data), MEM_WRITE, CACHE_DATA)) {
-			/*  Exception.  */
-			return;
-		}
-	}
-}
-
-
-/*
- *  add_rm_rn:  rn = rn + rm
- *  addc_rm_rn: rn = rn + rm + t
- *  and_rm_rn:  rn = rn & rm
- *  xor_rm_rn:  rn = rn ^ rm
- *  or_rm_rn:   rn = rn | rm
- *  sub_rm_rn:  rn = rn - rm
- *  subc_rm_rn: rn = rn - rm - t; t = borrow
- *  tst_rm_rn:  t = ((rm & rn) == 0)
- *  tst_rm:     t = (rm == 0)
- *  xtrct_rm_rn:  rn = (rn >> 16) | (rm << 16)
- *
- *  arg[0] = ptr to rm
- *  arg[1] = ptr to rn
- */
-X(add_rm_rn) { reg(ic->arg[1]) += reg(ic->arg[0]); }
-X(addc_rm_rn)
-{
-	uint64_t res = reg(ic->arg[1]);
-	res += (uint64_t) reg(ic->arg[0]);
-	if (cpu->cd.sh.sr & SH_SR_T)
-		res ++;
-	if ((res >> 32) & 1)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	reg(ic->arg[1]) = (uint32_t) res;
-}
-X(and_rm_rn) { reg(ic->arg[1]) &= reg(ic->arg[0]); }
-X(xor_rm_rn) { reg(ic->arg[1]) ^= reg(ic->arg[0]); }
-X(or_rm_rn)  { reg(ic->arg[1]) |= reg(ic->arg[0]); }
-X(sub_rm_rn) { reg(ic->arg[1]) -= reg(ic->arg[0]); }
-X(subc_rm_rn)
-{
-	uint64_t res = reg(ic->arg[1]);
-	res -= (uint64_t) reg(ic->arg[0]);
-	if (cpu->cd.sh.sr & SH_SR_T)
-		res --;
-	if ((res >> 32) & 1)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	reg(ic->arg[1]) = (uint32_t) res;
-}
-X(tst_rm_rn)
-{
-	if (reg(ic->arg[1]) & reg(ic->arg[0]))
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	else
-		cpu->cd.sh.sr |= SH_SR_T;
-}
-X(tst_rm)
-{
-	if (reg(ic->arg[0]))
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	else
-		cpu->cd.sh.sr |= SH_SR_T;
-}
-X(xtrct_rm_rn)
-{
-	uint32_t rn = reg(ic->arg[1]), rm = reg(ic->arg[0]);
-	reg(ic->arg[1]) = (rn >> 16) | (rm << 16);
-}
-
-
-/*
- *  div0u:       Division step 0; prepare for unsigned division.
- *  div0s_rm_rn: Division step 0; prepare for signed division.
- *  div1_rm_rn:  Division step 1.
- *
- *  arg[0] = ptr to rm
- *  arg[1] = ptr to rn
- */
-X(div0u)
-{
-	cpu->cd.sh.sr &= ~(SH_SR_Q | SH_SR_M | SH_SR_T);
-}
-X(div0s_rm_rn)
-{
-	int q = reg(ic->arg[1]) & 0x80000000;
-	int m = reg(ic->arg[0]) & 0x80000000;
-	uint32_t new_sr = cpu->cd.sh.sr & ~(SH_SR_Q | SH_SR_M | SH_SR_T);
-	if (q)
-		new_sr |= SH_SR_Q;
-	if (m)
-		new_sr |= SH_SR_M;
-	if (m ^ q)
-		new_sr |= SH_SR_T;
-	cpu->cd.sh.sr = new_sr;
-}
-X(div1_rm_rn)
-{
-	uint32_t q, old_q = (cpu->cd.sh.sr & SH_SR_Q)? 1 : 0;
-	uint32_t m = (cpu->cd.sh.sr & SH_SR_M)? 1 : 0;
-	uint32_t t = (cpu->cd.sh.sr & SH_SR_T)? 1 : 0;
-	uint32_t op1 = reg(ic->arg[0]), op2 = reg(ic->arg[1]);
-	uint64_t op2_64;
-
-	q = op2 >> 31;
-	op2_64 = (uint32_t) ((op2 << 1) + t);
-	if (old_q == m)
-		op2_64 -= (uint64_t)op1;
-	else
-		op2_64 += (uint64_t)op1;
-	q ^= m ^ ((op2_64 >> 32) & 1);
-	t = 1 - (q ^ m);
-	cpu->cd.sh.sr &= ~(SH_SR_Q | SH_SR_T);
-	if (q)
-		cpu->cd.sh.sr |= SH_SR_Q;
-	if (t)
-		cpu->cd.sh.sr |= SH_SR_T;
-	reg(ic->arg[1]) = (uint32_t) op2_64;
-}
-
-
-/*
- *  mul_l_rm_rn:   MACL = Rm * Rn       (32-bit)
- *  muls_w_rm_rn:  MACL = Rm * Rn       (signed 16-bit * 16-bit ==> 32-bit)
- *  mulu_w_rm_rn:  MACL = Rm * Rn       (unsigned 16-bit * 16-bit ==> 32-bit)
- *  dmuls_l_rm_rn: MACH:MACL = Rm * Rn  (signed, 64-bit result)
- *  dmulu_l_rm_rn: MACH:MACL = Rm * Rn  (unsigned, 64-bit result)
- *
- *  arg[0] = ptr to rm
- *  arg[1] = ptr to rn
- */
-X(mul_l_rm_rn)
-{
-	cpu->cd.sh.macl = reg(ic->arg[0]) * reg(ic->arg[1]);
-}
-X(muls_w_rm_rn)
-{
-	cpu->cd.sh.macl = (int32_t)(int16_t)reg(ic->arg[0]) *
-	    (int32_t)(int16_t)reg(ic->arg[1]);
-}
-X(mulu_w_rm_rn)
-{
-	cpu->cd.sh.macl = (int32_t)(uint16_t)reg(ic->arg[0]) *
-	    (int32_t)(uint16_t)reg(ic->arg[1]);
-}
-X(dmuls_l_rm_rn)
-{
-	uint64_t rm = (int32_t)reg(ic->arg[0]), rn = (int32_t)reg(ic->arg[1]);
-	uint64_t res = rm * rn;
-	cpu->cd.sh.mach = (uint32_t) (res >> 32);
-	cpu->cd.sh.macl = (uint32_t) res;
-}
-X(dmulu_l_rm_rn)
-{
-	uint64_t rm = reg(ic->arg[0]), rn = reg(ic->arg[1]), res;
-	res = rm * rn;
-	cpu->cd.sh.mach = (uint32_t) (res >> 32);
-	cpu->cd.sh.macl = (uint32_t) res;
-}
-
-
-/*
- *  cmpeq_imm_r0:  rn == int8_t immediate
- *  cmpeq_rm_rn:   rn == rm
- *  cmphs_rm_rn:   rn >= rm, unsigned
- *  cmpge_rm_rn:   rn >= rm, signed
- *  cmphi_rm_rn:   rn > rm, unsigned
- *  cmpgt_rm_rn:   rn > rm, signed
- *  cmppz_rn:      rn >= 0, signed
- *  cmppl_rn:      rn > 0, signed
- *  cmp_str_rm_rn: t=1 if any bytes in rm and rn match, 0 otherwise
- *
- *  arg[0] = ptr to rm   (or imm, for cmpeq_imm_r0)
- *  arg[1] = ptr to rn
- */
-X(cmpeq_imm_r0)
-{
-	if (cpu->cd.sh.r[0] == (uint32_t)ic->arg[0])
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-}
-X(cmpeq_rm_rn)
-{
-	if (reg(ic->arg[1]) == reg(ic->arg[0]))
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-}
-X(cmphs_rm_rn)
-{
-	if (reg(ic->arg[1]) >= reg(ic->arg[0]))
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-}
-X(cmpge_rm_rn)
-{
-	if ((int32_t)reg(ic->arg[1]) >= (int32_t)reg(ic->arg[0]))
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-}
-X(cmphi_rm_rn)
-{
-	if (reg(ic->arg[1]) > reg(ic->arg[0]))
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-}
-X(cmpgt_rm_rn)
-{
-	if ((int32_t)reg(ic->arg[1]) > (int32_t)reg(ic->arg[0]))
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-}
-X(cmppz_rn)
-{
-	if ((int32_t)reg(ic->arg[1]) >= 0)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-}
-X(cmppl_rn)
-{
-	if ((int32_t)reg(ic->arg[1]) > 0)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-}
-X(cmp_str_rm_rn)
-{
-	uint32_t r0 = reg(ic->arg[0]), r1 = reg(ic->arg[1]);
-	int t = 0;
-	if ((r0 & 0xff000000) == (r1 & 0xff000000))
-		t = 1;
-	else if ((r0 & 0xff0000) == (r1 & 0xff0000))
-		t = 1;
-	else if ((r0 & 0xff00) == (r1 & 0xff00))
-		t = 1;
-	else if ((r0 & 0xff) == (r1 & 0xff))
-		t = 1;
-	if (t)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-}
-
-
-/*
- *  shll_rn:  Shift rn left by 1  (t = bit that was shifted out)
- *  shlr_rn:  Shift rn right by 1 (t = bit that was shifted out)
- *  rotl_rn:  Shift rn left by 1  (t = bit that was shifted out)
- *  rotr_rn:  Shift rn right by 1 (t = bit that was shifted out)
- *  shar_rn:  Shift rn right arithmetically by 1 (t = bit that was shifted out)
- *  shllX_rn: Shift rn left logically by X bits
- *  shlrX_rn: Shift rn right logically by X bits
- *  rotcl_rn: Rotate rn left via the t bit
- *  rotcr_rn: Rotate rn right via the t bit
- *  dt_rn:    Decrease rn; t = (rn == 0)
- *
- *  arg[1] = ptr to rn
- */
-X(shll_rn)
-{
-	uint32_t rn = reg(ic->arg[1]);
-	if (rn & 0x80000000)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	reg(ic->arg[1]) = rn << 1;
-}
-X(shlr_rn)
-{
-	uint32_t rn = reg(ic->arg[1]);
-	if (rn & 1)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	reg(ic->arg[1]) = rn >> 1;
-}
-X(rotl_rn)
-{
-	uint32_t rn = reg(ic->arg[1]), x;
-	if (rn & 0x80000000) {
-		x = 1;
-		cpu->cd.sh.sr |= SH_SR_T;
-	} else {
-		x = 0;
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	}
-	reg(ic->arg[1]) = (rn << 1) | x;
-}
-X(rotr_rn)
-{
-	uint32_t rn = reg(ic->arg[1]);
-	if (rn & 1)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	reg(ic->arg[1]) = (rn >> 1) | (rn << 31);
-}
-X(shar_rn)
-{
-	int32_t rn = reg(ic->arg[1]);
-	if (rn & 1)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	reg(ic->arg[1]) = rn >> 1;
-}
-X(rotcl_rn)
-{
-	uint32_t rn = reg(ic->arg[1]), top;
-	top = rn & 0x80000000;
-	rn <<= 1;
-	if (cpu->cd.sh.sr & SH_SR_T)
-		rn ++;
-	if (top)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	reg(ic->arg[1]) = rn;
-}
-X(rotcr_rn)
-{
-	uint32_t rn = reg(ic->arg[1]), bottom;
-	bottom = rn & 1;
-	rn >>= 1;
-	if (cpu->cd.sh.sr & SH_SR_T)
-		rn |= 0x80000000;
-	if (bottom)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	reg(ic->arg[1]) = rn;
-}
-X(dt_rn)
-{
-	uint32_t rn = reg(ic->arg[1]) - 1;
-	if (rn == 0)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-	reg(ic->arg[1]) = rn;
-}
-X(shll2_rn) { reg(ic->arg[1]) <<= 2; }
-X(shll8_rn) { reg(ic->arg[1]) <<= 8; }
-X(shll16_rn) { reg(ic->arg[1]) <<= 16; }
-X(shlr2_rn) { reg(ic->arg[1]) >>= 2; }
-X(shlr8_rn) { reg(ic->arg[1]) >>= 8; }
-X(shlr16_rn) { reg(ic->arg[1]) >>= 16; }
-
-
-/*
- *  shad: Shift Rn arithmetic left/right, as indicated by Rm. Result in Rn.
- *  shld: Shift Rn logically left/right, as indicated by Rm. Result in Rn.
- *
- *  arg[0] = ptr to rm
- *  arg[1] = ptr to rn
- */
-X(shad)
-{
-	int32_t rn = reg(ic->arg[1]);
-	int32_t rm = reg(ic->arg[0]);
-	int sa = rm & 0x1f;
-
-	if (rm >= 0)
-		rn <<= sa;
-	else if (sa != 0)
-		rn >>= (32 - sa);
-	else if (rn < 0)
-		rn = -1;
-	else
-		rn = 0;
-
-	reg(ic->arg[1]) = rn;
-}
-X(shld)
-{
-	uint32_t rn = reg(ic->arg[1]);
-	int32_t rm = reg(ic->arg[0]);
-	int sa = rm & 0x1f;
-
-	if (rm >= 0)
-		rn <<= sa;
-	else if (sa != 0)
-		rn >>= (32 - sa);
-	else
-		rn = 0;
-
-	reg(ic->arg[1]) = rn;
-}
-
-
-/*
- *  bra:   Branch using PC relative immediace displacement (with delay-slot)
- *  bsr:   Like bra, but also sets PR to the return address
- *  braf:  Like bra, but using a register instead of an immediate
- *  bsrf:  Like braf, but also sets PR to the return address
- *
- *  arg[0] = immediate offset relative to start of page,
- *           or ptr to target instruction, for samepage branches
- *  arg[1] = ptr to Rn  (for braf/bsrf)
- */
-X(bra)
-{
-	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-	    SH_INSTR_ALIGNMENT_SHIFT);
-	target += ic->arg[0];
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->pc = target;
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bra_samepage)
-{
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT))
-		cpu->cd.sh.next_ic = (struct sh_instr_call *) ic->arg[0];
-	cpu->delay_slot = NOT_DELAYED;
-}
-X(bsr)
-{
-	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-	    SH_INSTR_ALIGNMENT_SHIFT);
-	uint32_t old_pc;
-	SYNCH_PC;
-	old_pc = cpu->pc;
-	target += ic->arg[0];
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->cd.sh.pr = old_pc + 4;
-		cpu->pc = target;
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bsr_trace)
-{
-	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-	    SH_INSTR_ALIGNMENT_SHIFT);
-	uint32_t old_pc;
-	SYNCH_PC;
-	old_pc = cpu->pc;
-	target += ic->arg[0];
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->cd.sh.pr = old_pc + 4;
-		cpu->pc = target;
-		cpu_functioncall_trace(cpu, cpu->pc);
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bsr_samepage)
-{
-	uint32_t old_pc;
-	SYNCH_PC;
-	old_pc = cpu->pc;
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->cd.sh.pr = old_pc + 4;
-		cpu->cd.sh.next_ic = (struct sh_instr_call *) ic->arg[0];
-	}
-	cpu->delay_slot = NOT_DELAYED;
-}
-X(braf_rn)
-{
-	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-	    SH_INSTR_ALIGNMENT_SHIFT);
-	target += ic->arg[0] + reg(ic->arg[1]);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->pc = target;
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bsrf_rn)
-{
-	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-	    SH_INSTR_ALIGNMENT_SHIFT);
-	uint32_t old_pc;
-	SYNCH_PC;
-	old_pc = cpu->pc;
-	target += ic->arg[0] + reg(ic->arg[1]);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->cd.sh.pr = old_pc + 4;
-		cpu->pc = target;
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bsrf_rn_trace)
-{
-	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-	    SH_INSTR_ALIGNMENT_SHIFT);
-	uint32_t old_pc;
-	SYNCH_PC;
-	old_pc = cpu->pc;
-	target += ic->arg[0] + reg(ic->arg[1]);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->cd.sh.pr = old_pc + 4;
-		cpu->pc = target;
-		cpu_functioncall_trace(cpu, cpu->pc);
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  bt: Branch if true
- *  bf: Branch if false
- *  bt/s: Branch if true (with delay-slot)
- *  bf/s: Branch if false (with delay-slot)
- *
- *  arg[0] = immediate offset relative to start of page
- *  arg[1] = for samepage functions, the new instruction pointer
- */
-X(bt)
-{
-	if (cpu->cd.sh.sr & SH_SR_T) {
-		cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-		    SH_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += ic->arg[0];
-		quick_pc_to_pointers(cpu);
-	}
-}
-X(bf)
-{
-	if (!(cpu->cd.sh.sr & SH_SR_T)) {
-		cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-		    SH_INSTR_ALIGNMENT_SHIFT);
-		cpu->pc += ic->arg[0];
-		quick_pc_to_pointers(cpu);
-	}
-}
-X(bt_samepage)
-{
-	if (cpu->cd.sh.sr & SH_SR_T)
-		cpu->cd.sh.next_ic = (struct sh_instr_call *) ic->arg[1];
-}
-X(bf_samepage)
-{
-	if (!(cpu->cd.sh.sr & SH_SR_T))
-		cpu->cd.sh.next_ic = (struct sh_instr_call *) ic->arg[1];
-}
-X(bt_s)
-{
-	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-	    SH_INSTR_ALIGNMENT_SHIFT);
-	int cond = cpu->cd.sh.sr & SH_SR_T;
-	target += ic->arg[0];
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->delay_slot = NOT_DELAYED;
-		if (cond) {
-			cpu->pc = target;
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.sh.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bf_s)
-{
-	MODE_int_t target = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-	    SH_INSTR_ALIGNMENT_SHIFT);
-	int cond = !(cpu->cd.sh.sr & SH_SR_T);
-	target += ic->arg[0];
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->delay_slot = NOT_DELAYED;
-		if (cond) {
-			cpu->pc = target;
-			quick_pc_to_pointers(cpu);
-		} else
-			cpu->cd.sh.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bt_s_samepage)
-{
-	int cond = cpu->cd.sh.sr & SH_SR_T;
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->delay_slot = NOT_DELAYED;
-		if (cond)
-			cpu->cd.sh.next_ic =
-			    (struct sh_instr_call *) ic->arg[1];
-		else
-			cpu->cd.sh.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(bf_s_samepage)
-{
-	int cond = !(cpu->cd.sh.sr & SH_SR_T);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->delay_slot = NOT_DELAYED;
-		if (cond)
-			cpu->cd.sh.next_ic =
-			    (struct sh_instr_call *) ic->arg[1];
-		else
-			cpu->cd.sh.next_ic ++;
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  jmp_rn: Jump to Rn
- *  jsr_rn: Jump to Rn, store return address in PR.
- *
- *  arg[0] = ptr to rn
- */
-X(jmp_rn)
-{
-	MODE_int_t target = reg(ic->arg[0]);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->pc = target;
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(jmp_rn_trace)
-{
-	MODE_int_t target = reg(ic->arg[0]);
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->pc = target;
-#if 0
-		/*  NOTE: Jmp works like both a return, and a subroutine
-		    call.  */
-		cpu_functioncall_trace_return(cpu);
-		cpu_functioncall_trace(cpu, cpu->pc);
-#endif
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(jsr_rn)
-{
-	MODE_int_t target = reg(ic->arg[0]), retaddr;
-	cpu->delay_slot = TO_BE_DELAYED;
-	retaddr = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-	    SH_INSTR_ALIGNMENT_SHIFT);
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	cpu->cd.sh.pr = retaddr + (int32_t)ic->arg[1];
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->pc = target;
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(jsr_rn_trace)
-{
-	MODE_int_t target = reg(ic->arg[0]), retaddr;
-	cpu->delay_slot = TO_BE_DELAYED;
-	retaddr = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-	    SH_INSTR_ALIGNMENT_SHIFT);
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	cpu->cd.sh.pr = retaddr + (int32_t)ic->arg[1];
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->pc = target;
-		cpu_functioncall_trace(cpu, cpu->pc);
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  rts: Jump to PR.
- */
-X(rts)
-{
-	MODE_int_t target = cpu->cd.sh.pr;
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->pc = target;
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-X(rts_trace)
-{
-	MODE_int_t target = cpu->cd.sh.pr;
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->pc = target;
-		cpu_functioncall_trace_return(cpu);
-		cpu->delay_slot = NOT_DELAYED;
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  rte:  Return from exception.
- */
-X(rte)
-{
-	RES_INST_IF_NOT_MD;
-
-	cpu->delay_slot = TO_BE_DELAYED;
-	ic[1].f(cpu, ic+1);
-	cpu->n_translated_instrs ++;
-	if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) {
-		cpu->pc = cpu->cd.sh.spc;
-		cpu->delay_slot = NOT_DELAYED;
-		sh_update_sr(cpu, cpu->cd.sh.ssr);
-		quick_pc_to_pointers(cpu);
-	} else
-		cpu->delay_slot = NOT_DELAYED;
-}
-
-
-/*
- *  ldtlb:  Load UTLB entry.
- */
-X(ldtlb)
-{
-	uint32_t old_hi, old_lo;
-	int urc = (cpu->cd.sh.mmucr & SH4_MMUCR_URC_MASK)
-	    >> SH4_MMUCR_URC_SHIFT;
-
-	RES_INST_IF_NOT_MD;
-
-	old_hi = cpu->cd.sh.utlb_hi[urc];
-	old_lo = cpu->cd.sh.utlb_lo[urc];
-
-	cpu->cd.sh.utlb_hi[urc] = cpu->cd.sh.pteh;
-	cpu->cd.sh.utlb_lo[urc] = cpu->cd.sh.ptel;
-
-	/*  Invalidate the old mapping, if it belonged to the same ASID:  */
-	if ((old_hi & SH4_PTEH_ASID_MASK) ==
-	    (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) {
-		if ((old_lo & SH4_PTEL_SZ_MASK) == SH4_PTEL_SZ_4K)
-			cpu->invalidate_translation_caches(cpu,
-			    old_hi & 0xfffff000, INVALIDATE_VADDR);
-		else
-			cpu->invalidate_translation_caches(cpu,
-			    0, INVALIDATE_ALL);
-	}
-}
-
-
-/*
- *  copy_privileged_register: Copy normal into privileged register, or vice
- *                            versa, after checking the MD status bit.
- *
- *  arg[0] = ptr to source register
- *  arg[1] = ptr to destination register
- */
-X(copy_privileged_register)
-{
-	RES_INST_IF_NOT_MD;
-	reg(ic->arg[1]) = reg(ic->arg[0]);
-}
-
-
-/*
- *  ldc_rm_sr:      Copy Rm into SR, after checking the MD status bit.
- *
- *  arg[1] = ptr to rm
- */
-X(ldc_rm_sr)
-{
-	RES_INST_IF_NOT_MD;
-	sh_update_sr(cpu, reg(ic->arg[1]));
-
-#if 0
-/*  NOTE: This code causes NetBSD/landisk to get past a point where it
-    otherwise hangs, but it causes Linux/Dreamcast to bug out instead. :/  */
-
-	if (!(cpu->cd.sh.sr & SH_SR_BL) && cpu->cd.sh.int_to_assert > 0 &&
-	    ( (cpu->cd.sh.sr & SH_SR_IMASK) >> SH_SR_IMASK_SHIFT)
-	    < cpu->cd.sh.int_level) {
-		/*  Cause interrupt immediately, by dropping out of the
-		    main dyntrans loop:  */
-		cpu->cd.sh.next_ic = &nothing_call;
-	}
-#endif
-}
-
-
-/*
- *  trapa:  Immediate trap.
- *
- *  arg[0] = imm << 2
- */
-X(trapa)
-{
-	SYNCH_PC;
-
-	if (cpu->delay_slot) {
-		sh_exception(cpu, EXPEVT_SLOT_INST, 0, 0);
-		return;
-	}
-
-	cpu->cd.sh.tra = ic->arg[0];
-	sh_exception(cpu, EXPEVT_TRAPA, 0, 0);
-}
-
-
-/*
- *  copy_fp_register:   Copy a register into another, with FP avail check.
- *  lds_rm_fpscr:       Copy Rm into FPSCR.
- *
- *  arg[0] = ptr to source
- *  arg[1] = ptr to destination
- */
-X(copy_fp_register)
-{
-	FLOATING_POINT_AVAILABLE_CHECK;
-	reg(ic->arg[1]) = reg(ic->arg[0]);
-}
-X(lds_rm_fpscr)
-{
-	FLOATING_POINT_AVAILABLE_CHECK;
-	sh_update_fpscr(cpu, reg(ic->arg[1]));
-}
-
-
-/*
- *  fmov_frm_frn:  Copy one floating-point register (or pair) to another.
- *
- *  arg[0] = ptr to source float register or pair
- *  arg[1] = ptr to destination float register or pair
- */
-X(fmov_frm_frn)
-{
-	size_t r0, r1;
-	int ofs0, ofs1;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	/*  Simplest case, single-precision:  */
-	if (!(cpu->cd.sh.fpscr & SH_FPSCR_SZ)) {
-		reg(ic->arg[1]) = reg(ic->arg[0]);
-		return;
-	}
-
-	/*  Double-precision:  */
-	r0 = ic->arg[0]; r1 = ic->arg[1];
-	ofs0 = (r0 - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
-	ofs1 = (r1 - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
-	if (ofs0 & 1)
-		r0 = (size_t)&cpu->cd.sh.xf[ofs0 & ~1];
-	if (ofs1 & 1)
-		r1 = (size_t)&cpu->cd.sh.xf[ofs1 & ~1];
-
-	reg(r1) = reg(r0);
-	reg(r1 + 4) = reg(r0 + 4);
-}
-
-
-/*
- *  float_fpul_frn:  Load FPUL into float register.
- *
- *  arg[0] = ptr to float register, or float register pair
- */
-X(float_fpul_frn)
-{
-	int32_t fpul = cpu->cd.sh.fpul;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
-		/*  Double-precision, using a pair of registers:  */
-		uint64_t ieee = ieee_store_float_value(fpul, IEEE_FMT_D);
-		reg(ic->arg[0]) = (uint32_t) (ieee >> 32);
-		reg(ic->arg[0] + sizeof(uint32_t)) = (uint32_t) ieee;
-	} else {
-		/*  Single-precision:  */
-		uint32_t ieee = ieee_store_float_value(fpul, IEEE_FMT_S);
-		reg(ic->arg[0]) = (uint32_t) ieee;
-	}
-}
-
-
-/*
- *  ftrc_frm_fpul:  Truncate a float register into FPUL.
- *
- *  arg[0] = ptr to float register, or float register pair
- */
-X(ftrc_frm_fpul)
-{
-	struct ieee_float_value op1;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
-		/*  Double-precision, using a pair of registers:  */
-		int64_t r1 = ((uint64_t)reg(ic->arg[0]) << 32) +
-		    reg(ic->arg[0] + sizeof(uint32_t));
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
-		cpu->cd.sh.fpul = (int32_t) op1.f;
-	} else {
-		/*  Single-precision:  */
-		ieee_interpret_float_value(reg(ic->arg[0]), &op1, IEEE_FMT_S);
-		cpu->cd.sh.fpul = (int32_t) op1.f;
-	}
-}
-
-
-/*
- *  fcnvsd_fpul_drn:  Convert single-precision to double-precision.
- *  fcnvds_drm_fpul:  Convert double-precision to single-precision.
- *
- *  arg[0] = ptr to destination (double- or single-precision float)
- */
-X(fcnvsd_fpul_drn)
-{
-	struct ieee_float_value op1;
-	int64_t ieee;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	ieee_interpret_float_value(cpu->cd.sh.fpul, &op1, IEEE_FMT_S);
-	cpu->cd.sh.fpul = (int32_t) op1.f;
-
-	/*  Store double-precision result:  */
-	ieee = ieee_store_float_value(op1.f, IEEE_FMT_D);
-	reg(ic->arg[0]) = (uint32_t) (ieee >> 32);
-	reg(ic->arg[0] + sizeof(uint32_t)) = (uint32_t) ieee;
-}
-X(fcnvds_drm_fpul)
-{
-	struct ieee_float_value op1;
-	int64_t r1;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
-	    ((uint64_t)reg(ic->arg[0]) << 32);
-	ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
-
-	cpu->cd.sh.fpul = ieee_store_float_value(op1.f, IEEE_FMT_S);
-}
-
-
-/*
- *  fsca_fpul_drn:  Sinus/cosinus approximation.
- *
- *  Note: This is an interesting instruction. It is not included in the SH4
- *  manual. Some googling indicated that this might be an SH4X instruction.
- *  On the other hand, it is used by Dreamcast code (and the Dreamcast has an
- *  SH4), and a cvs comment for gdb said that this is an SH4 instruction, not
- *  an SH4A instruction. Well well...
- *
- *  arg[0] = ptr to single-precision float register pair
- */
-X(fsca_fpul_drn)
-{
-	double fpulAngle = ((double)cpu->cd.sh.fpul) * 2.0 * M_PI / 65536.0;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	reg(ic->arg[0]) = ieee_store_float_value(sin(fpulAngle), IEEE_FMT_S);
-	reg(ic->arg[0] + sizeof(uint32_t)) =
-	    ieee_store_float_value(cos(fpulAngle), IEEE_FMT_S);
-}
-
-
-/*
- *  fipr_fvm_fvn:  Vector * vector  =>  scalar
- *
- *  arg[0] = ptr to FVm
- *  arg[1] = ptr to FVn
- *
- *  Result of adding all   FR{m+i} * FR{n+i}  where i=0..3
- *  is stored in FR{n+3}.
- */
-X(fipr_fvm_fvn)
-{
-	struct ieee_float_value frn0, frn1, frn2, frn3;
-	struct ieee_float_value frm0, frm1, frm2, frm3;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	ieee_interpret_float_value(reg(ic->arg[0] +  0), &frm0, IEEE_FMT_S);
-	ieee_interpret_float_value(reg(ic->arg[0] +  4), &frm1, IEEE_FMT_S);
-	ieee_interpret_float_value(reg(ic->arg[0] +  8), &frm2, IEEE_FMT_S);
-	ieee_interpret_float_value(reg(ic->arg[0] + 12), &frm3, IEEE_FMT_S);
-	ieee_interpret_float_value(reg(ic->arg[1] +  0), &frn0, IEEE_FMT_S);
-	ieee_interpret_float_value(reg(ic->arg[1] +  4), &frn1, IEEE_FMT_S);
-	ieee_interpret_float_value(reg(ic->arg[1] +  8), &frn2, IEEE_FMT_S);
-	ieee_interpret_float_value(reg(ic->arg[1] + 12), &frn3, IEEE_FMT_S);
-
-	frn3.f =
-	    frm0.f * frn0.f + frm1.f * frn1.f +
-	    frm2.f * frn2.f + frm3.f * frn3.f;
-
-	reg(ic->arg[1] + 12) = ieee_store_float_value(frn3.f, IEEE_FMT_S);
-}
-
-
-/*
- *  ftrv_xmtrx_fvn:  Matrix * vector  ==>  vector
- *
- *  arg[0] = ptr to FVn
- */
-X(ftrv_xmtrx_fvn)
-{
-	int i;
-	struct ieee_float_value xmtrx[16], frn[4];
-	double frnp0 = 0.0, frnp1 = 0.0, frnp2 = 0.0, frnp3 = 0.0;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-	// TODO: FPSCR.EN.V = 1 should cause invalid operation exception?
-
-	ieee_interpret_float_value(reg(ic->arg[0] +  0), &frn[0], IEEE_FMT_S);
-	ieee_interpret_float_value(reg(ic->arg[0] +  4), &frn[1], IEEE_FMT_S);
-	ieee_interpret_float_value(reg(ic->arg[0] +  8), &frn[2], IEEE_FMT_S);
-	ieee_interpret_float_value(reg(ic->arg[0] + 12), &frn[3], IEEE_FMT_S);
-
-	for (i=0; i<16; i++)
-		ieee_interpret_float_value(cpu->cd.sh.xf[i],
-		    &xmtrx[i], IEEE_FMT_S);
-
-	for (i=0; i<4; i++)
-		frnp0 += xmtrx[i*4].f * frn[i].f;
-
-	for (i=0; i<4; i++)
-		frnp1 += xmtrx[i*4 + 1].f * frn[i].f;
-
-	for (i=0; i<4; i++)
-		frnp2 += xmtrx[i*4 + 2].f * frn[i].f;
-
-	for (i=0; i<4; i++)
-		frnp3 += xmtrx[i*4 + 3].f * frn[i].f;
-
-	reg(ic->arg[0] +  0) = ieee_store_float_value(frnp0, IEEE_FMT_S);
-	reg(ic->arg[0] +  4) = ieee_store_float_value(frnp1, IEEE_FMT_S);
-	reg(ic->arg[0] +  8) = ieee_store_float_value(frnp2, IEEE_FMT_S);
-	reg(ic->arg[0] + 12) = ieee_store_float_value(frnp3, IEEE_FMT_S);
-}
-
-
-/*
- *  fldi:  Load immediate (0.0 or 1.0) into floating point register.
- *  fneg:  Negate a floating point register
- *  fabs:  Get the absolute value of a floating point register
- *  fsqrt: Calculate square root
- *  fsrra: Calculate 1 / (square root)
- *
- *  arg[0] = ptr to fp register
- *  arg[1] = (uint32_t) immediate value (for fldi)
- */
-X(fldi_frn)
-{
-	FLOATING_POINT_AVAILABLE_CHECK;
-	reg(ic->arg[0]) = ic->arg[1];
-}
-X(fneg_frn)
-{
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	// Hm. If in double register mode... and the register is pointing to
-	// an _odd_ register, what happens then?
-	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
-		int ofs0 = (ic->arg[0] - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
-		if (ofs0 & 1) {
-			fatal("TODO: fneg_frn odd register in double prec. mode.\n");
-			exit(1);
-		}
-	}
-
-	/*  Note: This also works for double-precision.  */
-	reg(ic->arg[0]) ^= 0x80000000;
-}
-X(fabs_frn)
-{
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	// Hm. If in double register mode... and the register is pointing to
-	// an _odd_ register, what happens then?
-	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
-		int ofs0 = (ic->arg[0] - (size_t)&cpu->cd.sh.fr[0]) / sizeof(uint32_t);
-		if (ofs0 & 1) {
-			fatal("TODO: fneg_frn odd register in double prec. mode.\n");
-			exit(1);
-		}
-	}
-
-	/*  Note: This also works for double-precision.  */
-	reg(ic->arg[0]) &= 0x7fffffff;
-}
-X(fsqrt_frn)
-{
-	struct ieee_float_value op1;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
-		/*  Double-precision:  */
-		int64_t r1, ieee;
-		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[0]) << 32);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
-		ieee = ieee_store_float_value(sqrt(op1.f), IEEE_FMT_D);
-		reg(ic->arg[0]) = (uint32_t) (ieee >> 32);
-		reg(ic->arg[0] + sizeof(uint32_t)) = (uint32_t) ieee;
-	} else {
-		/*  Single-precision:  */
-		int32_t ieee, r1 = reg(ic->arg[0]);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
-		ieee = ieee_store_float_value(sqrt(op1.f), IEEE_FMT_S);
-		reg(ic->arg[0]) = ieee;
-	}
-}
-X(fsrra_frn)
-{
-	// I'm guessing that this is 1/sqrt. That's how it is described at
-	// http://yam.20to4.net/dreamcast/hints/index.html at least.
-
-	struct ieee_float_value op1;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
-		/*  Double-precision:  */
-		fatal("Double-precision fsrra? TODO\n");
-		ABORT_EXECUTION;
-		return;
-	} else {
-		/*  Single-precision:  */
-		int32_t ieee, r1 = reg(ic->arg[0]);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
-		ieee = ieee_store_float_value(1.0f / sqrt(op1.f), IEEE_FMT_S);
-		reg(ic->arg[0]) = ieee;
-	}
-}
-
-
-/*
- *  fadd_frm_frn:     Floating point addition.
- *  fsub_frm_frn:     Floating point subtraction.
- *  fmul_frm_frn:     Floating point multiplication.
- *  fdiv_frm_frn:     Floating point division.
- *  fmac_fr0_frm_frn: Multiply-and-accumulate.
- *  fcmp_eq_frm_frn:  Floating point greater-than comparison.
- *  fcmp_gt_frm_frn:  Floating point greater-than comparison.
- *
- *  arg[0] = ptr to float register FRm
- *  arg[1] = ptr to float register FRn
- */
-X(fadd_frm_frn)
-{
-	struct ieee_float_value op1, op2;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
-		/*  Double-precision, using a pair of registers:  */
-		int64_t r1, r2, ieee;
-		double result;
-
-		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[0]) << 32);
-		r2 = reg(ic->arg[1] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[1]) << 32);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
-		ieee_interpret_float_value(r2, &op2, IEEE_FMT_D);
-
-		result = op2.f + op1.f;
-		ieee = ieee_store_float_value(result, IEEE_FMT_D);
-		reg(ic->arg[1]) = (uint32_t) (ieee >> 32);
-		reg(ic->arg[1] + sizeof(uint32_t)) = (uint32_t) ieee;
-	} else {
-		/*  Single-precision:  */
-		uint32_t r1, r2, ieee;
-		double result;
-
-		r1 = reg(ic->arg[0]);
-		r2 = reg(ic->arg[1]);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
-		ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
-
-		result = op2.f + op1.f;
-		ieee = ieee_store_float_value(result, IEEE_FMT_S);
-		reg(ic->arg[1]) = (uint32_t) ieee;
-	}
-}
-X(fsub_frm_frn)
-{
-	struct ieee_float_value op1, op2;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
-		/*  Double-precision, using a pair of registers:  */
-		int64_t r1, r2, ieee;
-		double result;
-		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[0]) << 32);
-		r2 = reg(ic->arg[1] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[1]) << 32);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
-		ieee_interpret_float_value(r2, &op2, IEEE_FMT_D);
-		result = op2.f - op1.f;
-		ieee = ieee_store_float_value(result, IEEE_FMT_D);
-		reg(ic->arg[1]) = (uint32_t) (ieee >> 32);
-		reg(ic->arg[1] + sizeof(uint32_t)) = (uint32_t) ieee;
-	} else {
-		/*  Single-precision:  */
-		uint32_t r1, r2, ieee;
-		double result;
-		r1 = reg(ic->arg[0]);
-		r2 = reg(ic->arg[1]);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
-		ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
-		result = op2.f - op1.f;
-		ieee = ieee_store_float_value(result, IEEE_FMT_S);
-		reg(ic->arg[1]) = (uint32_t) ieee;
-	}
-}
-X(fmul_frm_frn)
-{
-	struct ieee_float_value op1, op2;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
-		/*  Double-precision, using a pair of registers:  */
-		int64_t r1, r2, ieee;
-		double result;
-
-		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[0]) << 32);
-		r2 = reg(ic->arg[1] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[1]) << 32);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
-		ieee_interpret_float_value(r2, &op2, IEEE_FMT_D);
-
-		result = op2.f * op1.f;
-		ieee = ieee_store_float_value(result, IEEE_FMT_D);
-		reg(ic->arg[1]) = (uint32_t) (ieee >> 32);
-		reg(ic->arg[1] + sizeof(uint32_t)) = (uint32_t) ieee;
-	} else {
-		/*  Single-precision:  */
-		uint32_t r1, r2, ieee;
-		double result;
-
-		r1 = reg(ic->arg[0]);
-		r2 = reg(ic->arg[1]);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
-		ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
-
-		result = op2.f * op1.f;
-		ieee = ieee_store_float_value(result, IEEE_FMT_S);
-		reg(ic->arg[1]) = (uint32_t) ieee;
-	}
-}
-X(fdiv_frm_frn)
-{
-	struct ieee_float_value op1, op2;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
-		/*  Double-precision, using a pair of registers:  */
-		int64_t r1, r2, ieee;
-		double result;
-
-		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[0]) << 32);
-		r2 = reg(ic->arg[1] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[1]) << 32);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
-		ieee_interpret_float_value(r2, &op2, IEEE_FMT_D);
-
-		if (op1.f != 0.0)
-			result = op2.f / op1.f;
-		else
-			result = 0.0;
-
-		ieee = ieee_store_float_value(result, IEEE_FMT_D);
-
-		reg(ic->arg[1]) = (uint32_t) (ieee >> 32);
-		reg(ic->arg[1] + sizeof(uint32_t)) = (uint32_t) ieee;
-	} else {
-		/*  Single-precision:  */
-		uint32_t r1, r2, ieee;
-		double result;
-
-		r1 = reg(ic->arg[0]);
-		r2 = reg(ic->arg[1]);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
-		ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
-
-		if (op1.f != 0.0)
-			result = op2.f / op1.f;
-		else
-			result = 0.0;
-
-		ieee = ieee_store_float_value(result, IEEE_FMT_S);
-
-		reg(ic->arg[1]) = (uint32_t) ieee;
-	}
-}
-X(fmac_fr0_frm_frn)
-{
-	struct ieee_float_value op1, op2, op0;
-	int32_t r1, r2, fr0 = cpu->cd.sh.fr[0], ieee;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	r1 = reg(ic->arg[0]), r2 = reg(ic->arg[1]);
-	ieee_interpret_float_value(fr0, &op0, IEEE_FMT_S);
-	ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
-	ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
-	ieee = ieee_store_float_value(op0.f * op1.f + op2.f, IEEE_FMT_S);
-	reg(ic->arg[1]) = ieee;
-}
-X(fcmp_eq_frm_frn)
-{
-	struct ieee_float_value op1, op2;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
-		/*  Double-precision, using a pair of registers:  */
-		int64_t r1, r2;
-		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[0]) << 32);
-		r2 = reg(ic->arg[1] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[1]) << 32);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
-		ieee_interpret_float_value(r2, &op2, IEEE_FMT_D);
-	} else {
-		/*  Single-precision:  */
-		uint32_t r1 = reg(ic->arg[0]), r2 = reg(ic->arg[1]);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
-		ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
-	}
-
-	if (op2.f == op1.f)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-}
-X(fcmp_gt_frm_frn)
-{
-	struct ieee_float_value op1, op2;
-
-	FLOATING_POINT_AVAILABLE_CHECK;
-
-	if (cpu->cd.sh.fpscr & SH_FPSCR_PR) {
-		/*  Double-precision, using a pair of registers:  */
-		int64_t r1, r2;
-		r1 = reg(ic->arg[0] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[0]) << 32);
-		r2 = reg(ic->arg[1] + sizeof(uint32_t)) +
-		    ((uint64_t)reg(ic->arg[1]) << 32);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_D);
-		ieee_interpret_float_value(r2, &op2, IEEE_FMT_D);
-	} else {
-		/*  Single-precision:  */
-		uint32_t r1 = reg(ic->arg[0]), r2 = reg(ic->arg[1]);
-		ieee_interpret_float_value(r1, &op1, IEEE_FMT_S);
-		ieee_interpret_float_value(r2, &op2, IEEE_FMT_S);
-	}
-
-	if (op2.f > op1.f)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-}
-
-
-/*
- *  frchg:  Change floating-point register banks.
- *  fschg:  Change floating-point register size.
- */
-X(frchg)
-{
-	FLOATING_POINT_AVAILABLE_CHECK;
-	sh_update_fpscr(cpu, cpu->cd.sh.fpscr ^ SH_FPSCR_FR);
-}
-X(fschg)
-{
-	FLOATING_POINT_AVAILABLE_CHECK;
-	sh_update_fpscr(cpu, cpu->cd.sh.fpscr ^ SH_FPSCR_SZ);
-}
-
-
-/*
- *  pref_rn:  Prefetch.
- *
- *  TODO: According to the SH4 manual, "OTLBMULTIHIT or RADDERR may be
- *  delivered", so those things should be checked for. Not implemented yet.
- *
- *  arg[1] = ptr to Rn
- */
-X(pref_rn)
-{
-	uint32_t addr = reg(ic->arg[1]), extaddr;
-	int sq_nr, ofs;
-
-	if (addr < 0xe0000000U || addr >= 0xe4000000U)
-	{
-		// printf("[ SH4 pref 0x%08x (pc = 0x%08x) ]\n", addr, (int)cpu->pc);
-		return;
-	}
-
-	SYNCH_PC;
-
-	// Calculate the external address:
-	extaddr = addr & 0x03ffffe0;
-	sq_nr = addr & 0x20? 1 : 0;
-
-	// if (addr & 0x0000001f)
-	//	debug("[ WARNING: SH4 Store Queue, addr = 0x%08x... lowest 5 "
-	//	    "bits are non-zero. Ignoring. ]\n", addr);
-
-	if (sq_nr == 0)
-		extaddr |= (((cpu->cd.sh.qacr0 >> 2) & 7) << 26);
-	else
-		extaddr |= (((cpu->cd.sh.qacr1 >> 2) & 7) << 26);
-
-	// fatal("[ SH4 pref: SQ extaddr = 0x%08x (pc = 0x%08x) ]\n", extaddr, (int)cpu->pc);
-
-	// Is the MMU turned on?
-	if (cpu->cd.sh.mmucr & SH4_MMUCR_AT) {
-		// When the SQMD bit in MMUCR is set, user access is prohibited
-		// if the MMU is enabled.
-		if (cpu->cd.sh.mmucr & SH4_MMUCR_SQMD) {
-			bool inUserMode = (cpu->cd.sh.sr & SH_SR_MD) ? false : true;
-			if (inUserMode) {
-				sh_exception(cpu, EXPEVT_RES_INST, 0, 0);
-				return;
-			}
-		}
-
-		fatal("Store Queue to external memory, when "
-		    "MMU enabled: Not yet implemented... TODO\n");
-		ABORT_EXECUTION;
-		return;
-	}
-
-	for (ofs = 0; ofs < 32; ofs += sizeof(uint32_t)) {
-		uint32_t word;
-		cpu->memory_rw(cpu, cpu->mem, 0xe0000000UL + ofs
-		    + sq_nr * 0x20, (unsigned char *)
-		    &word, sizeof(word), MEM_READ, PHYSICAL);
-		// fatal("  addr %08x: %08x\n", (extaddr + ofs), word);
-		cpu->memory_rw(cpu, cpu->mem, extaddr+ofs, (unsigned char *)
-		    &word, sizeof(word), MEM_WRITE, PHYSICAL);
-	}
-}
-
-
-/*
- *  tas_b_rn: Test-and-Set.
- *
- *  arg[1] = ptr to Rn
- */
-X(tas_b_rn)
-{
-	uint32_t addr = reg(ic->arg[1]);
-	uint8_t byte, newbyte;
-
-	SYNCH_PC;
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, &byte, 1, MEM_READ,
-	   CACHE_DATA)) {
-		/*  Exception.  */
-		return;
-	}
-
-	newbyte = byte | 0x80;
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, &newbyte, 1, MEM_WRITE,
-	   CACHE_DATA)) {
-		/*  Exception.  */
-		return;
-	}
-
-	if (byte == 0)
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-}
-
-
-/*
- *  prom_emul:
- */
-X(prom_emul)
-{
-	uint32_t old_pc;
-	SYNCH_PC;
-	old_pc = cpu->pc;
-
-	switch (cpu->machine->machine_type) {
-	case MACHINE_DREAMCAST:
-		dreamcast_emul(cpu);
-		break;
-	case MACHINE_LANDISK:
-		sh_ipl_g_emul(cpu);
-		break;
-	default:
-		fatal("SH prom_emul: unimplemented machine type.\n");
-		exit(1);
-	}
-
-	if (!cpu->running) {
-		cpu->n_translated_instrs --;
-		cpu->cd.sh.next_ic = &nothing_call;
-	} else if ((uint32_t)cpu->pc != old_pc) {
-		/*  The PC value was changed by the PROM call.  */
-		quick_pc_to_pointers(cpu);
-	}
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  bt_samepage_wait_for_variable:
- *
- *  Loop which reads a variable in memory forever until it changes state,
- *  can most likely only change state if an interrupt occurs. Simulate speed
- *  by skipping ahead quickly, until the next interrupt occurs.
- *
- *	z:  mov.l  (X,gbr),r0		mov_l_disp_gbr_r0 with arg[1] = X
- *          cmp/eq r0,rY		cmpeq_rm_rn with args 0 and 1 being r0 and rY
- *          bt     x			bt_samepage with arg[1] = z
- */
-X(bt_samepage_wait_for_variable)
-{
-	if (cpu->delay_slot) {
-		instr(mov_l_disp_gbr_r0)(cpu, ic);
-		return;
-	}
-
-	// mov_l_disp_gbr_r0:
-	// Bail out quickly if the memory is not on a readable page.
-	uint32_t addr = cpu->cd.sh.gbr + ic->arg[1];
-	uint32_t *p = (uint32_t *) cpu->cd.sh.host_load[addr >> 12];
-	if (p == NULL) {
-		instr(mov_l_disp_gbr_r0)(cpu, ic);
-		return;
-	}
-
-	uint32_t data = p[(addr & 0xfff) >> 2];
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		data = LE32_TO_HOST(data);
-	else
-		data = BE32_TO_HOST(data);
-
-	cpu->cd.sh.r[0] = data;
-
-	// cmpeq_rm_rn:
-	if (reg(ic[1].arg[1]) == reg(ic[1].arg[0]))
-		cpu->cd.sh.sr |= SH_SR_T;
-	else
-		cpu->cd.sh.sr &= ~SH_SR_T;
-
-	// Loop for a "long time" if the two registered were equal.
-	if (cpu->cd.sh.sr & SH_SR_T) {
-		// Some bogus amount of instructions.
-		// TODO: Make nicer?
-		cpu->n_translated_instrs += 500;
-		cpu->cd.sh.next_ic = ic;	// "jump to z"
-	} else {
-		// otherwise, get out of the loop.
-		cpu->n_translated_instrs += 2;
-		cpu->cd.sh.next_ic = ic + 3;
-	}
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  Combine: something ending with a bt_samepage.
- *
- *  See comment for bt_samepage_wait_for_variable above for details.
- */
-void COMBINE(bt_samepage)(struct cpu *cpu, struct sh_instr_call *ic, int low_addr)
-{
-	int n_back = (low_addr >> SH_INSTR_ALIGNMENT_SHIFT)
-	    & (SH_IC_ENTRIES_PER_PAGE - 1);
-
-	if (n_back < 2)
-		return;
-
-	if (ic[-2].f == instr(mov_l_disp_gbr_r0) &&
-	    ic[-1].f == instr(cmpeq_rm_rn) &&
-	    (ic[-1].arg[0] == (size_t) &cpu->cd.sh.r[0] ||
-	     ic[-1].arg[1] == (size_t) &cpu->cd.sh.r[0]) &&
-	    ic[0].arg[1] == (size_t) &ic[-2]) {
-		ic[-2].f = instr(bt_samepage_wait_for_variable);
-	}
-}
-
-
-/*****************************************************************************/
-
-
-X(end_of_page)
-{
-	/*  Update the PC:  (offset 0, but on the next page)  */
-	cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1) <<
-	    SH_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (SH_IC_ENTRIES_PER_PAGE << SH_INSTR_ALIGNMENT_SHIFT);
-
-	/*  end_of_page doesn't count as an executed instruction:  */
-	cpu->n_translated_instrs --;
-
-	/*
-	 *  Find the new physpage and update translation pointers.
-	 *
-	 *  Note: This may cause an exception, if e.g. the new page is
-	 *  not accessible.
-	 */
-	quick_pc_to_pointers(cpu);
-
-	/*  Simple jump to the next page (if we are lucky):  */
-	if (cpu->delay_slot == NOT_DELAYED)
-		return;
-
-	/*
-	 *  If we were in a delay slot, and we got an exception while doing
-	 *  quick_pc_to_pointers, then return. The function which called
-	 *  end_of_page should handle this case.
-	 */
-	if (cpu->delay_slot == EXCEPTION_IN_DELAY_SLOT)
-		return;
-
-	/*
-	 *  Tricky situation; the delay slot is on the next virtual page.
-	 *  Calling to_be_translated will translate one instruction manually,
-	 *  execute it, and then discard it.
-	 */
-	/*  fatal("[ end_of_page: delay slot across page boundary! ]\n");  */
-
-	instr(to_be_translated)(cpu, cpu->cd.sh.next_ic);
-
-	/*  The instruction in the delay slot has now executed.  */
-	/*  fatal("[ end_of_page: back from executing the delay slot, %i ]\n",
-	    cpu->delay_slot);  */
-
-	/*  Find the physpage etc of the instruction in the delay slot
-	    (or, if there was an exception, the exception handler):  */
-	quick_pc_to_pointers(cpu);
-}
-
-
-X(end_of_page2)
-{
-	/*  Synchronize PC on the _second_ instruction on the next page:  */
-	int low_pc = ((size_t)ic - (size_t)cpu->cd.sh.cur_ic_page)
-	    / sizeof(struct sh_instr_call);
-	cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1)
-	    << SH_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc += (low_pc << SH_INSTR_ALIGNMENT_SHIFT);
-
-	/*  This doesn't count as an executed instruction.  */
-	cpu->n_translated_instrs --;
-
-	quick_pc_to_pointers(cpu);
-
-	if (cpu->delay_slot == NOT_DELAYED)
-		return;
-
-	fatal("end_of_page2: fatal error, we're in a delay slot\n");
-	exit(1);
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  sh_instr_to_be_translated():
- *
- *  Translate an instruction word into an sh_instr_call. ic is filled in with
- *  valid data for the translated instruction, or a "nothing" instruction if
- *  there was a translation failure. The newly translated instruction is then
- *  executed.
- */
-X(to_be_translated)
-{
-	uint32_t addr, low_pc, iword;
-	unsigned char *page;
-	unsigned char ib[2];
-	int main_opcode, isize = sizeof(ib);
-	int in_crosspage_delayslot = 0, r8, r4, lo4, lo8;
-	void (*samepage_function)(struct cpu *, struct sh_instr_call *);
-
-	/*  Figure out the (virtual) address of the instruction:  */
-	low_pc = ((size_t)ic - (size_t)cpu->cd.sh.cur_ic_page)
-	    / sizeof(struct sh_instr_call);
-
-	/*  Special case for branch with delayslot on the next page:  */
-	if (cpu->delay_slot == TO_BE_DELAYED && low_pc == 0) {
-		/*  fatal("[ delay-slot translation across page "
-		    "boundary ]\n");  */
-		in_crosspage_delayslot = 1;
-	}
-
-	addr = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1)
-	    << SH_INSTR_ALIGNMENT_SHIFT);
-	addr += (low_pc << SH_INSTR_ALIGNMENT_SHIFT);
-	cpu->pc = (MODE_int_t)addr;
-	addr &= ~((1 << SH_INSTR_ALIGNMENT_SHIFT) - 1);
-
-	/*  Read the instruction word from memory:  */
-	page = cpu->cd.sh.host_load[(uint32_t)addr >> 12];
-
-	if (page != NULL) {
-		/*  fatal("TRANSLATION HIT!\n");  */
-		memcpy(ib, page + (addr & 0xfff), isize);
-	} else {
-		/*  fatal("TRANSLATION MISS!\n");  */
-		if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
-		    isize, MEM_READ, CACHE_INSTRUCTION)) {
-			fatal("to_be_translated(): read failed: TODO\n");
-			goto bad;
-		}
-	}
-
-	{
-		uint16_t *p = (uint16_t *) ib;
-		iword = *p;
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		iword = LE16_TO_HOST(iword);
-	else
-		iword = BE16_TO_HOST(iword);
-
-	main_opcode = iword >> 12;
-	r8 = (iword >> 8) & 0xf;
-	r4 = (iword >> 4) & 0xf;
-	lo8 = iword & 0xff;
-	lo4 = iword & 0xf;
-
-
-#define DYNTRANS_TO_BE_TRANSLATED_HEAD
-#include "cpu_dyntrans.cc"
-#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD
-
-
-	/*
-	 *  Translate the instruction:
-	 */
-
-	/*  Default args. for many instructions:  */
-	ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];	/* m */
-	ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];	/* n */
-
-	switch (main_opcode) {
-
-	case 0x0:
-		if (lo4 == 0x4) {
-			/*  MOV.B Rm,@(R0,Rn)  */
-			ic->f = instr(mov_b_rm_r0_rn);
-		} else if (lo4 == 0x5) {
-			/*  MOV.W Rm,@(R0,Rn)  */
-			ic->f = instr(mov_w_rm_r0_rn);
-		} else if (lo4 == 0x6) {
-			/*  MOV.L Rm,@(R0,Rn)  */
-			ic->f = instr(mov_l_rm_r0_rn);
-		} else if (lo4 == 0x7) {
-			/*  MUL.L Rm,Rn  */
-			ic->f = instr(mul_l_rm_rn);
-		} else if (iword == 0x000b) {
-			if (cpu->machine->show_trace_tree)
-				ic->f = instr(rts_trace);
-			else
-				ic->f = instr(rts);
-		} else if (lo4 == 0xc) {
-			/*  MOV.B @(R0,Rm),Rn  */
-			ic->f = instr(mov_b_r0_rm_rn);
-		} else if (lo4 == 0xd) {
-			/*  MOV.W @(R0,Rm),Rn  */
-			ic->f = instr(mov_w_r0_rm_rn);
-		} else if (lo4 == 0xe) {
-			/*  MOV.L @(R0,Rm),Rn  */
-			ic->f = instr(mov_l_r0_rm_rn);
-		} else if (iword == 0x0008) {
-			/*  CLRT  */
-			ic->f = instr(clrt);
-		} else if (iword == 0x0018) {
-			/*  SETT  */
-			ic->f = instr(sett);
-		} else if (iword == 0x0019) {
-			/*  DIV0U  */
-			ic->f = instr(div0u);
-		} else if (iword == 0x001b) {
-			/*  SLEEP  */
-			ic->f = instr(sleep);
-		} else if (iword == 0x0028) {
-			/*  CLRMAC  */
-			ic->f = instr(clrmac);
-		} else if (iword == 0x002b) {
-			/*  RTE  */
-			ic->f = instr(rte);
-		} else if (iword == 0x0038) {
-			/*  LDTLB  */
-			ic->f = instr(ldtlb);
-		} else if (iword == 0x0048) {
-			/*  CLRS  */
-			ic->f = instr(clrs);
-		} else if (iword == 0x0058) {
-			/*  SETS  */
-			ic->f = instr(sets);
-		} else if ((lo8 & 0x8f) == 0x82) {
-			/*  STC Rm_BANK, Rn  */
-			ic->f = instr(copy_privileged_register);
-			ic->arg[0] = (size_t)&cpu->cd.sh.r_bank[(lo8 >> 4) & 7];
-		} else if (iword == SH_INVALID_INSTR) {
-			/*  PROM emulation (GXemul specific)  */
-			ic->f = instr(prom_emul);
-		} else {
-			switch (lo8) {
-			case 0x02:	/*  STC SR,Rn  */
-				ic->f = instr(copy_privileged_register);
-				ic->arg[0] = (size_t)&cpu->cd.sh.sr;
-				break;
-			case 0x03:	/*  BSRF Rn  */
-				if (cpu->machine->show_trace_tree)
-					ic->f = instr(bsrf_rn_trace);
-				else
-					ic->f = instr(bsrf_rn);
-
-				ic->arg[0] = (int32_t) (addr &
-				    ((SH_IC_ENTRIES_PER_PAGE-1)
-				    << SH_INSTR_ALIGNMENT_SHIFT) & ~1) + 4;
-				/*  arg[1] is Rn  */
-				break;
-			case 0x09:	/*  NOP  */
-				ic->f = instr(nop);
-				if (iword & 0x0f00) {
-					if (!cpu->translation_readahead)
-						fatal("Unimplemented NOP"
-						    " variant?\n");
-					goto bad;
-				}
-				break;
-			case 0x0a:	/*  STS MACH,Rn  */
-				ic->f = instr(mov_rm_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.mach;
-				break;
-			case 0x12:	/*  STC GBR,Rn  */
-				ic->f = instr(mov_rm_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.gbr;
-				break;
-			case 0x1a:	/*  STS MACL,Rn  */
-				ic->f = instr(mov_rm_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.macl;
-				break;
-			case 0x22:	/*  STC VBR,Rn  */
-				ic->f = instr(copy_privileged_register);
-				ic->arg[0] = (size_t)&cpu->cd.sh.vbr;
-				break;
-			case 0x23:	/*  BRAF Rn  */
-				ic->f = instr(braf_rn);
-				ic->arg[0] = (int32_t) (addr &
-				    ((SH_IC_ENTRIES_PER_PAGE-1)
-				    << SH_INSTR_ALIGNMENT_SHIFT) & ~1) + 4;
-				/*  arg[1] is Rn  */
-				break;
-			case 0x29:	/*  MOVT Rn  */
-				ic->f = instr(movt_rn);
-				break;
-			case 0x2a:	/*  STS PR,Rn  */
-				ic->f = instr(mov_rm_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.pr;
-				break;
-			case 0x32:	/*  STC SSR,Rn  */
-				ic->f = instr(copy_privileged_register);
-				ic->arg[0] = (size_t)&cpu->cd.sh.ssr;
-				break;
-			case 0x42:	/*  STC SPC,Rn  */
-				ic->f = instr(copy_privileged_register);
-				ic->arg[0] = (size_t)&cpu->cd.sh.spc;
-				break;
-			case 0x5a:	/*  STS FPUL,Rn  */
-				ic->f = instr(copy_fp_register);
-				ic->arg[0] = (size_t)&cpu->cd.sh.fpul;
-				ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];
-				break;
-			case 0x6a:	/*  STS FPSCR,Rn  */
-				ic->f = instr(copy_fp_register);
-				ic->arg[0] = (size_t)&cpu->cd.sh.fpscr;
-				ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];
-				break;
-			case 0x83:	/*  PREF @Rn  */
-				ic->f = instr(pref_rn);
-				break;
-			case 0x93:	/*  OCBI @Rn  */
-				/*  Treat as nop for now:  */
-				/*  TODO: Implement this.  */
-				ic->f = instr(nop);
-				break;
-			case 0xa3:	/*  OCBP @Rn  */
-				/*  Treat as nop for now:  */
-				/*  TODO: Implement this.  */
-				ic->f = instr(nop);
-				break;
-			case 0xb3:	/*  OCBWB @Rn  */
-				/*  Treat as nop for now:  */
-				/*  TODO: Implement this.  */
-				ic->f = instr(nop);
-				break;
-			case 0xc3:	/*  MOVCA.L R0,@Rn  */
-				/*  Treat as nop for now:  */
-				/*  TODO: Implement this.  */
-				ic->f = instr(nop);
-				break;
-			case 0xfa:	/*  STC DBR,Rn  */
-				ic->f = instr(copy_privileged_register);
-				ic->arg[0] = (size_t)&cpu->cd.sh.dbr;
-				ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];
-				break;
-			default:if (!cpu->translation_readahead)
-					fatal("Unimplemented opcode 0x%x,"
-					    "0x%03x\n", main_opcode,
-					    iword & 0xfff);
-				goto bad;
-			}
-		}
-		break;
-
-	case 0x1:
-		ic->f = instr(mov_l_rm_disp_rn);
-		ic->arg[1] = r8 + (lo4 << 4);
-		break;
-
-	case 0x2:
-		switch (lo4) {
-		case 0x0:	/*  MOV.B Rm,@Rn  */
-			ic->f = instr(mov_b_store_rm_rn);
-			break;
-		case 0x1:	/*  MOV.W Rm,@Rn  */
-			ic->f = instr(mov_w_store_rm_rn);
-			break;
-		case 0x2:	/*  MOV.L Rm,@Rn  */
-			ic->f = instr(mov_l_store_rm_rn);
-			break;
-		case 0x4:	/*  MOV.B Rm,@-Rn  */
-			ic->f = instr(mov_b_rm_predec_rn);
-			break;
-		case 0x5:	/*  MOV.W Rm,@-Rn  */
-			ic->f = instr(mov_w_rm_predec_rn);
-			break;
-		case 0x6:	/*  MOV.L Rm,@-Rn  */
-			ic->f = instr(mov_l_rm_predec_rn);
-			break;
-		case 0x7:	/*  DIV0S Rm,Rn  */
-			ic->f = instr(div0s_rm_rn);
-			break;
-		case 0x8:	/*  TST Rm,Rn  */
-			ic->f = instr(tst_rm_rn);
-			if (r8 == r4)
-				ic->f = instr(tst_rm);
-			break;
-		case 0x9:	/*  AND Rm,Rn  */
-			ic->f = instr(and_rm_rn);
-			break;
-		case 0xa:	/*  XOR Rm,Rn  */
-			ic->f = instr(xor_rm_rn);
-			break;
-		case 0xb:	/*  OR Rm,Rn  */
-			ic->f = instr(or_rm_rn);
-			break;
-		case 0xc:	/*  CMP/STR Rm,Rn  */
-			ic->f = instr(cmp_str_rm_rn);
-			break;
-		case 0xd:	/*  XTRCT Rm,Rn  */
-			ic->f = instr(xtrct_rm_rn);
-			break;
-		case 0xe:	/*  MULU.W Rm,Rn  */
-			ic->f = instr(mulu_w_rm_rn);
-			break;
-		case 0xf:	/*  MULS.W Rm,Rn  */
-			ic->f = instr(muls_w_rm_rn);
-			break;
-		default:if (!cpu->translation_readahead)
-				fatal("Unimplemented opcode 0x%x,0x%x\n",
-				    main_opcode, lo4);
-			goto bad;
-		}
-		break;
-
-	case 0x3:
-		switch (lo4) {
-		case 0x0:	/*  CMP/EQ Rm,Rn  */
-			ic->f = instr(cmpeq_rm_rn);
-			break;
-		case 0x2:	/*  CMP/HS Rm,Rn  */
-			ic->f = instr(cmphs_rm_rn);
-			break;
-		case 0x3:	/*  CMP/GE Rm,Rn  */
-			ic->f = instr(cmpge_rm_rn);
-			break;
-		case 0x4:	/*  DIV1 Rm,Rn  */
-			ic->f = instr(div1_rm_rn);
-			break;
-		case 0x5:	/*  DMULU.L Rm,Rn  */
-			ic->f = instr(dmulu_l_rm_rn);
-			break;
-		case 0x6:	/*  CMP/HI Rm,Rn  */
-			ic->f = instr(cmphi_rm_rn);
-			break;
-		case 0x7:	/*  CMP/GT Rm,Rn  */
-			ic->f = instr(cmpgt_rm_rn);
-			break;
-		case 0x8:	/*  SUB Rm,Rn  */
-			ic->f = instr(sub_rm_rn);
-			break;
-		case 0xa:	/*  SUBC Rm,Rn  */
-			ic->f = instr(subc_rm_rn);
-			break;
-		case 0xc:	/*  ADD Rm,Rn  */
-			ic->f = instr(add_rm_rn);
-			break;
-		case 0xd:	/*  DMULS.L Rm,Rn  */
-			ic->f = instr(dmuls_l_rm_rn);
-			break;
-		case 0xe:	/*  ADDC Rm,Rn  */
-			ic->f = instr(addc_rm_rn);
-			break;
-		default:if (!cpu->translation_readahead)
-				fatal("Unimplemented opcode 0x%x,0x%x\n",
-				    main_opcode, lo4);
-			goto bad;
-		}
-		break;
-
-	case 0x4:
-		if (lo4 == 0xc) {
-			ic->f = instr(shad);
-		} else if (lo4 == 0xd) {
-			ic->f = instr(shld);
-		} else if ((lo8 & 0x8f) == 0x83) {
-			/*  STC.L Rm_BANK,@-Rn  */
-			ic->f = instr(stc_l_rm_predec_rn_md);
-			ic->arg[0] = (size_t)&cpu->cd.sh.r_bank[
-			    (lo8 >> 4) & 7];	/* m */
-		} else if ((lo8 & 0x8f) == 0x87) {
-			/*   LDC.L @Rm+,Rn_BANK  */
-			ic->f = instr(mov_l_arg1_postinc_to_arg0_md);
-			ic->arg[0] = (size_t)&cpu->cd.sh.r_bank[(lo8 >> 4) & 7];
-		} else if ((lo8 & 0x8f) == 0x8e) {
-			/*  LDC Rm, Rn_BANK  */
-			ic->f = instr(copy_privileged_register);
-			ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];
-			ic->arg[1] = (size_t)&cpu->cd.sh.r_bank[(lo8 >> 4) & 7];
-		} else {
-			switch (lo8) {
-			case 0x00:	/*  SHLL Rn  */
-				ic->f = instr(shll_rn);
-				break;
-			case 0x01:	/*  SHLR Rn  */
-				ic->f = instr(shlr_rn);
-				break;
-			case 0x02:	/*  STS.L MACH,@-Rn  */
-				ic->f = instr(mov_l_rm_predec_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.mach;
-				break;
-			case 0x03:	/*  STC.L SR,@-Rn  */
-				ic->f = instr(stc_l_rm_predec_rn_md);
-				ic->arg[0] = (size_t)&cpu->cd.sh.sr;
-				break;
-			case 0x04:	/*  ROTL Rn  */
-				ic->f = instr(rotl_rn);
-				break;
-			case 0x05:	/*  ROTR Rn  */
-				ic->f = instr(rotr_rn);
-				break;
-			case 0x06:	/*  LDS.L @Rm+,MACH  */
-				ic->f = instr(mov_l_arg1_postinc_to_arg0);
-				ic->arg[0] = (size_t)&cpu->cd.sh.mach;
-				break;
-			case 0x07:	/*  LDC.L @Rm+,SR  */
-				ic->f = instr(mov_l_arg1_postinc_to_arg0_md);
-				ic->arg[0] = (size_t)&cpu->cd.sh.sr;
-				break;
-			case 0x08:	/*  SHLL2 Rn  */
-				ic->f = instr(shll2_rn);
-				break;
-			case 0x09:	/*  SHLR2 Rn  */
-				ic->f = instr(shlr2_rn);
-				break;
-			case 0x0a:	/*  LDS Rm,MACH  */
-				ic->f = instr(mov_rm_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
-				ic->arg[1] = (size_t)&cpu->cd.sh.mach;
-				break;
-			case 0x0b:	/*  JSR @Rn  */
-				if (cpu->machine->show_trace_tree)
-					ic->f = instr(jsr_rn_trace);
-				else
-					ic->f = instr(jsr_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* n */
-				ic->arg[1] = (addr & 0xffe) + 4;
-				break;
-			case 0x0e:	/*  LDC Rm,SR  */
-				ic->f = instr(ldc_rm_sr);
-				break;
-			case 0x10:	/*  DT Rn  */
-				ic->f = instr(dt_rn);
-				break;
-			case 0x11:	/*  CMP/PZ Rn  */
-				ic->f = instr(cmppz_rn);
-				break;
-			case 0x12:	/*  STS.L MACL,@-Rn  */
-				ic->f = instr(mov_l_rm_predec_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.macl;
-				break;
-			case 0x13:	/*  STC.L GBR,@-Rn  */
-				ic->f = instr(mov_l_rm_predec_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.gbr;
-				break;
-			case 0x15:	/*  CMP/PL Rn  */
-				ic->f = instr(cmppl_rn);
-				break;
-			case 0x16:	/*  LDS.L @Rm+,MACL  */
-				ic->f = instr(mov_l_arg1_postinc_to_arg0);
-				ic->arg[0] = (size_t)&cpu->cd.sh.macl;
-				break;
-			case 0x17:	/*  LDC.L @Rm+,GBR  */
-				ic->f = instr(mov_l_arg1_postinc_to_arg0);
-				ic->arg[0] = (size_t)&cpu->cd.sh.gbr;
-				break;
-			case 0x18:	/*  SHLL8 Rn  */
-				ic->f = instr(shll8_rn);
-				break;
-			case 0x19:	/*  SHLR8 Rn  */
-				ic->f = instr(shlr8_rn);
-				break;
-			case 0x1a:	/*  LDS Rm,MACL  */
-				ic->f = instr(mov_rm_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
-				ic->arg[1] = (size_t)&cpu->cd.sh.macl;
-				break;
-			case 0x1b:	/*  TAS.B @Rn  */
-				ic->f = instr(tas_b_rn);
-				break;
-			case 0x1e:	/*  LDC Rm,GBR  */
-				ic->f = instr(mov_rm_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
-				ic->arg[1] = (size_t)&cpu->cd.sh.gbr;
-				break;
-			case 0x20:	/*  SHAL Rn  */
-				ic->f = instr(shll_rn);  /*  NOTE: shll  */
-				break;
-			case 0x21:	/*  SHAR Rn  */
-				ic->f = instr(shar_rn);
-				break;
-			case 0x22:	/*  STS.L PR,@-Rn  */
-				ic->f = instr(mov_l_rm_predec_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.pr;	/* m */
-				ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];	/* n */
-				break;
-			case 0x23:	/*  STC.L VBR,@-Rn  */
-				ic->f = instr(stc_l_rm_predec_rn_md);
-				ic->arg[0] = (size_t)&cpu->cd.sh.vbr;
-				break;
-			case 0x24:	/*  ROTCL Rn  */
-				ic->f = instr(rotcl_rn);
-				break;
-			case 0x25:	/*  ROTCR Rn  */
-				ic->f = instr(rotcr_rn);
-				break;
-			case 0x26:	/*  LDS.L @Rm+,PR  */
-				ic->f = instr(mov_l_arg1_postinc_to_arg0);
-				ic->arg[0] = (size_t)&cpu->cd.sh.pr;
-				break;
-			case 0x27:	/*  LDC.L @Rm+,VBR  */
-				ic->f = instr(mov_l_arg1_postinc_to_arg0_md);
-				ic->arg[0] = (size_t)&cpu->cd.sh.vbr;
-				break;
-			case 0x28:	/*  SHLL16 Rn  */
-				ic->f = instr(shll16_rn);
-				break;
-			case 0x29:	/*  SHLR16 Rn  */
-				ic->f = instr(shlr16_rn);
-				break;
-			case 0x2a:	/*  LDS Rm,PR  */
-				ic->f = instr(mov_rm_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
-				ic->arg[1] = (size_t)&cpu->cd.sh.pr;
-				break;
-			case 0x2b:	/*  JMP @Rn  */
-				if (cpu->machine->show_trace_tree)
-					ic->f = instr(jmp_rn_trace);
-				else
-					ic->f = instr(jmp_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* n */
-				ic->arg[1] = (addr & 0xffe) + 4;
-				break;
-			case 0x2e:	/*  LDC Rm,VBR  */
-				ic->f = instr(copy_privileged_register);
-				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
-				ic->arg[1] = (size_t)&cpu->cd.sh.vbr;
-				break;
-			case 0x33:	/*  STC.L SSR,@-Rn  */
-				ic->f = instr(stc_l_rm_predec_rn_md);
-				ic->arg[0] = (size_t)&cpu->cd.sh.ssr;
-				break;
-			case 0x37:	/*  LDC.L @Rm+,SSR  */
-				ic->f = instr(mov_l_arg1_postinc_to_arg0_md);
-				ic->arg[0] = (size_t)&cpu->cd.sh.ssr;
-				break;
-			case 0x3e:	/*  LDC rm,SSR  */
-				ic->f = instr(copy_privileged_register);
-				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
-				ic->arg[1] = (size_t)&cpu->cd.sh.ssr;
-				break;
-			case 0x43:	/*  STC.L SPC,@-Rn  */
-				ic->f = instr(stc_l_rm_predec_rn_md);
-				ic->arg[0] = (size_t)&cpu->cd.sh.spc;
-				break;
-			case 0x47:	/*  LDC.L @Rm+,SPC  */
-				ic->f = instr(mov_l_arg1_postinc_to_arg0_md);
-				ic->arg[0] = (size_t)&cpu->cd.sh.spc;
-				break;
-			case 0x4e:	/*  LDC rm,SPC  */
-				ic->f = instr(copy_privileged_register);
-				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
-				ic->arg[1] = (size_t)&cpu->cd.sh.spc;
-				break;
-			case 0x52:	/*  STS.L FPUL,@-Rn  */
-				ic->f = instr(mov_l_rm_predec_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.fpul;
-				ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];	/* n */
-				break;
-			case 0x56:	/*  LDS.L @Rm+,FPUL  */
-				ic->f = instr(mov_l_arg1_postinc_to_arg0_fp);
-				ic->arg[0] = (size_t)&cpu->cd.sh.fpul;
-				break;
-			case 0x5a:	/*  LDS Rm,FPUL  */
-				ic->f = instr(copy_fp_register);
-				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* m */
-				ic->arg[1] = (size_t)&cpu->cd.sh.fpul;
-				break;
-			case 0x62:	/*  STS.L FPSCR,@-Rn  */
-				ic->f = instr(mov_l_rm_predec_rn);
-				ic->arg[0] = (size_t)&cpu->cd.sh.fpscr;
-				ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];	/* n */
-				break;
-			case 0x66:	/*  LDS.L @Rm+,FPSCR  */
-				/*  Note: Loading into FPSCR is a specia
-				    case (need to call sh_update_fpsrc()).  */
-				ic->f = instr(mov_l_arg1_postinc_to_arg0_fp);
-				ic->arg[0] = (size_t)&cpu->cd.sh.fpscr;
-				break;
-			case 0x6a:	/*  LDS Rm,FPSCR  */
-				ic->f = instr(lds_rm_fpscr);
-				/*  arg 1 = R8 = Rm  */
-				break;
-			case 0xfa:	/*  LDC Rm,DBR  */
-				ic->f = instr(copy_privileged_register);
-				ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];
-				ic->arg[1] = (size_t)&cpu->cd.sh.dbr;
-				break;
-			default:if (!cpu->translation_readahead)
-					fatal("Unimplemented opcode 0x%x,"
-					    "0x%02x\n", main_opcode, lo8);
-				goto bad;
-			}
-		}
-		break;
-
-	case 0x5:
-		ic->f = instr(mov_l_disp_rm_rn);
-		ic->arg[0] = r4 + (lo4 << 4);
-		break;
-
-	case 0x6:
-		switch (lo4) {
-		case 0x0:	/*  MOV.B @Rm,Rn  */
-			ic->f = instr(load_b_rm_rn);
-			break;
-		case 0x1:	/*  MOV.W @Rm,Rn  */
-			ic->f = instr(load_w_rm_rn);
-			break;
-		case 0x2:	/*  MOV.L @Rm,Rn  */
-			ic->f = instr(load_l_rm_rn);
-			break;
-		case 0x3:	/*  MOV Rm,Rn  */
-			ic->f = instr(mov_rm_rn);
-			break;
-		case 0x4:	/*  MOV.B @Rm+,Rn  */
-			ic->f = instr(mov_b_arg1_postinc_to_arg0);
-			/*  Note: Order  */
-			ic->arg[1] = (size_t)&cpu->cd.sh.r[r4];	/* m */
-			ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* n */
-			break;
-		case 0x5:	/*  MOV.W @Rm+,Rn  */
-			ic->f = instr(mov_w_arg1_postinc_to_arg0);
-			/*  Note: Order  */
-			ic->arg[1] = (size_t)&cpu->cd.sh.r[r4];	/* m */
-			ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* n */
-			break;
-		case 0x6:	/*  MOV.L @Rm+,Rn  */
-			ic->f = instr(mov_l_arg1_postinc_to_arg0);
-			/*  Note: Order  */
-			ic->arg[1] = (size_t)&cpu->cd.sh.r[r4];	/* m */
-			ic->arg[0] = (size_t)&cpu->cd.sh.r[r8];	/* n */
-			break;
-		case 0x7:	/*  NOT Rm,Rn  */
-			ic->f = instr(not_rm_rn);
-			break;
-		case 0x8:	/*  SWAP.B Rm,Rn  */
-			ic->f = instr(swap_b_rm_rn);
-			break;
-		case 0x9:	/*  SWAP.W Rm,Rn  */
-			ic->f = instr(swap_w_rm_rn);
-			break;
-		case 0xa:	/*  NEGC Rm,Rn  */
-			ic->f = instr(negc_rm_rn);
-			break;
-		case 0xb:	/*  NEG Rm,Rn  */
-			ic->f = instr(neg_rm_rn);
-			break;
-		case 0xc:	/*  EXTU.B Rm,Rn  */
-			ic->f = instr(extu_b_rm_rn);
-			if (r8 == r4)
-				ic->f = instr(extu_b_rm);
-			break;
-		case 0xd:	/*  EXTU.W Rm,Rn  */
-			ic->f = instr(extu_w_rm_rn);
-			if (r8 == r4)
-				ic->f = instr(extu_w_rm);
-			break;
-		case 0xe:	/*  EXTS.B Rm,Rn  */
-			ic->f = instr(exts_b_rm_rn);
-			break;
-		case 0xf:	/*  EXTS.W Rm,Rn  */
-			ic->f = instr(exts_w_rm_rn);
-			break;
-		default:if (!cpu->translation_readahead)
-				fatal("Unimplemented opcode 0x%x,0x%x\n",
-				    main_opcode, lo4);
-			goto bad;
-		}
-		break;
-
-	case 0x7:	/*  ADD #imm,Rn  */
-		ic->f = instr(add_imm_rn);
-		ic->arg[0] = (int8_t)lo8;
-		ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];		/* n */
-		if (lo8 == 1)
-			ic->f = instr(inc_rn);
-		if (lo8 == 4)
-			ic->f = instr(add_4_rn);
-		if (lo8 == 0xfc)
-			ic->f = instr(sub_4_rn);
-		if (lo8 == 0xff)
-			ic->f = instr(dec_rn);
-		break;
-
-	case 0x8:
-		/*  Displacement from beginning of page = default arg 0.  */
-		ic->arg[0] = (int8_t)lo8 * 2 +
-		    (addr & ((SH_IC_ENTRIES_PER_PAGE-1)
-		    << SH_INSTR_ALIGNMENT_SHIFT) & ~1) + 4;
-		samepage_function = NULL;
-
-		switch (r8) {
-		case 0x0:	/*  MOV.B R0,@(disp,Rn)  */
-			ic->f = instr(mov_b_r0_disp_rn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];	/* n */
-			ic->arg[1] = lo4;
-			break;
-		case 0x1:	/*  MOV.W R0,@(disp,Rn)  */
-			ic->f = instr(mov_w_r0_disp_rn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];	/* n */
-			ic->arg[1] = lo4 * 2;
-			break;
-		case 0x4:	/*  MOV.B @(disp,Rn),R0  */
-			ic->f = instr(mov_b_disp_rn_r0);
-			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];	/* n */
-			ic->arg[1] = lo4;
-			break;
-		case 0x5:	/*  MOV.W @(disp,Rn),R0  */
-			ic->f = instr(mov_w_disp_rn_r0);
-			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];	/* n */
-			ic->arg[1] = lo4 * 2;
-			break;
-		case 0x8:	/*  CMP/EQ #imm,R0  */
-			ic->f = instr(cmpeq_imm_r0);
-			ic->arg[0] = (int8_t)lo8;
-			break;
-		case 0x9:	/*  BT (disp,PC)  */
-			ic->f = instr(bt);
-			samepage_function = instr(bt_samepage);
-			break;
-		case 0xb:	/*  BF (disp,PC)  */
-			ic->f = instr(bf);
-			samepage_function = instr(bf_samepage);
-			break;
-		case 0xd:	/*  BT/S (disp,PC)  */
-			ic->f = instr(bt_s);
-			samepage_function = instr(bt_s_samepage);
-			break;
-		case 0xf:	/*  BF/S (disp,PC)  */
-			ic->f = instr(bf_s);
-			samepage_function = instr(bf_s_samepage);
-			break;
-		default:if (!cpu->translation_readahead)
-				fatal("Unimplemented opcode 0x%x,0x%x\n",
-				    main_opcode, r8);
-			goto bad;
-		}
-
-		/*  samepage branches:  */
-		if (samepage_function != NULL && ic->arg[0] < 0x1000 &&
-		    (addr & 0xfff) < 0xffe) {
-			ic->arg[1] = (size_t) (cpu->cd.sh.cur_ic_page +
-			    (ic->arg[0] >> SH_INSTR_ALIGNMENT_SHIFT));
-			ic->f = samepage_function;
-		}
-
-		if (ic->f == instr(bt_samepage))
-			cpu->cd.sh.combination_check = COMBINE(bt_samepage);
-
-		break;
-
-	case 0x9:	/*  MOV.W @(disp,PC),Rn  */
-		ic->f = instr(mov_w_disp_pc_rn);
-		ic->arg[0] = lo8 * 2 + (addr & ((SH_IC_ENTRIES_PER_PAGE-1)
-		    << SH_INSTR_ALIGNMENT_SHIFT) & ~1) + 4;
-
-		/*  If the word is reachable from the same page as the
-		    current address, then optimize it as a mov_imm_rn:  */
-		if (ic->arg[0] < 0x1000 && page != NULL) {
-			uint16_t *p = (uint16_t *) page;
-			uint16_t data = p[ic->arg[0] >> 1];
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-				data = LE16_TO_HOST(data);
-			else
-				data = BE16_TO_HOST(data);
-			ic->f = instr(mov_imm_rn);
-			ic->arg[0] = (int16_t) data;
-		}
-		break;
-
-	case 0xa:	/*  BRA disp  */
-	case 0xb:	/*  BSR disp  */
-		samepage_function = NULL;
-
-		switch (main_opcode) {
-		case 0xa:
-			ic->f = instr(bra);
-			samepage_function = instr(bra_samepage);
-			break;
-		case 0xb:
-			if (cpu->machine->show_trace_tree)
-				ic->f = instr(bsr_trace);
-			else
-			{
-				ic->f = instr(bsr);
-				samepage_function = instr(bsr_samepage);
-			}
-			break;
-		}
-
-		ic->arg[0] = (int32_t) ( (addr & ((SH_IC_ENTRIES_PER_PAGE-1)
-		    << SH_INSTR_ALIGNMENT_SHIFT) & ~1) + 4 +
-		    (((int32_t)(int16_t)((iword & 0xfff) << 4)) >> 3) );
-
-		/*  samepage branches:  */
-		if (samepage_function != NULL && ic->arg[0] < 0x1000 &&
-		    (addr & 0xfff) < 0xffe) {
-			ic->arg[0] = (size_t) (cpu->cd.sh.cur_ic_page +
-			    (ic->arg[0] >> SH_INSTR_ALIGNMENT_SHIFT));
-			ic->f = samepage_function;
-		}
-		break;
-
-	case 0xc:
-		switch (r8) {
-		case 0x0:
-			ic->f = instr(mov_b_r0_disp_gbr);
-			ic->arg[1] = lo8;
-			break;
-		case 0x1:
-			ic->f = instr(mov_w_r0_disp_gbr);
-			ic->arg[1] = lo8 << 1;
-			break;
-		case 0x2:
-			ic->f = instr(mov_l_r0_disp_gbr);
-			ic->arg[1] = lo8 << 2;
-			break;
-		case 0x3:
-			ic->f = instr(trapa);
-			ic->arg[0] = lo8 << 2;
-			break;
-		case 0x4:
-			ic->f = instr(mov_b_disp_gbr_r0);
-			ic->arg[1] = lo8;
-			break;
-		case 0x5:
-			ic->f = instr(mov_w_disp_gbr_r0);
-			ic->arg[1] = lo8 << 1;
-			break;
-		case 0x6:
-			ic->f = instr(mov_l_disp_gbr_r0);
-			ic->arg[1] = lo8 << 2;
-			break;
-		case 0x7:	/*  MOVA @(disp,pc),R0  */
-			ic->f = instr(mova_r0);
-			ic->arg[0] = lo8 * 4 + (addr &
-			    ((SH_IC_ENTRIES_PER_PAGE-1)
-			    << SH_INSTR_ALIGNMENT_SHIFT) & ~3) + 4;
-			break;
-		case 0x8:	/*  TST #imm,R0  */
-			ic->f = instr(tst_imm_r0);
-			ic->arg[0] = lo8;
-			break;
-		case 0x9:	/*  AND #imm,R0  */
-			ic->f = instr(and_imm_r0);
-			ic->arg[0] = lo8;
-			break;
-		case 0xa:	/*  XOR #imm,R0  */
-			ic->f = instr(xor_imm_r0);
-			ic->arg[0] = lo8;
-			break;
-		case 0xb:	/*  OR #imm,R0  */
-			ic->f = instr(or_imm_r0);
-			ic->arg[0] = lo8;
-			break;
-		case 0xd:	/*  AND.B #imm,@(R0,GBR)  */
-			ic->f = instr(and_b_imm_r0_gbr);
-			ic->arg[0] = lo8;
-			break;
-		case 0xe:	/*  XOR.B #imm,@(R0,GBR)  */
-			ic->f = instr(xor_b_imm_r0_gbr);
-			ic->arg[0] = lo8;
-			break;
-		case 0xf:	/*  OR.B #imm,@(R0,GBR)  */
-			ic->f = instr(or_b_imm_r0_gbr);
-			ic->arg[0] = lo8;
-			break;
-		default:if (!cpu->translation_readahead)
-				fatal("Unimplemented opcode 0x%x,0x%x\n",
-				    main_opcode, r8);
-			goto bad;
-		}
-		break;
-
-	case 0xd:	/*  MOV.L @(disp,PC),Rn  */
-		ic->f = instr(mov_l_disp_pc_rn);
-		ic->arg[0] = lo8 * 4 + (addr & ((SH_IC_ENTRIES_PER_PAGE-1)
-		    << SH_INSTR_ALIGNMENT_SHIFT) & ~3) + 4;
-
-		/*  If the word is reachable from the same page as the
-		    current address, then optimize it as a mov_imm_rn:  */
-		if (ic->arg[0] < 0x1000 && page != NULL) {
-			uint32_t *p = (uint32_t *) page;
-			uint32_t data = p[ic->arg[0] >> 2];
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-				data = LE32_TO_HOST(data);
-			else
-				data = BE32_TO_HOST(data);
-			ic->f = instr(mov_imm_rn);
-			ic->arg[0] = data;
-		}
-		break;
-
-	case 0xe:	/*  MOV #imm,Rn  */
-		ic->f = instr(mov_imm_rn);
-		ic->arg[0] = (int8_t)lo8;
-		ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];	/* n */
-		if (lo8 == 0)
-			ic->f = instr(mov_0_rn);
-		break;
-
-	case 0xf:
-		if (lo4 == 0x0) {
-			/*  FADD FRm,FRn  */
-			ic->f = instr(fadd_frm_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo4 == 0x1) {
-			/*  FSUB FRm,FRn  */
-			ic->f = instr(fsub_frm_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo4 == 0x2) {
-			/*  FMUL FRm,FRn  */
-			ic->f = instr(fmul_frm_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo4 == 0x3) {
-			/*  FDIV FRm,FRn  */
-			ic->f = instr(fdiv_frm_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo4 == 0x4) {
-			/*  FCMP/EQ FRm,FRn  */
-			ic->f = instr(fcmp_eq_frm_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo4 == 0x5) {
-			/*  FCMP/GT FRm,FRn  */
-			ic->f = instr(fcmp_gt_frm_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo4 == 0x6) {
-			/*  FMOV @(R0,Rm),FRn  */
-			ic->f = instr(fmov_r0_rm_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];  /* m */
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo4 == 0x7) {
-			/*  FMOV FRm,@(R0,Rn)  */
-			ic->f = instr(fmov_frm_r0_rn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];  /* m */
-			ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];
-		} else if (lo4 == 0x8) {
-			/*  FMOV @Rm,FRn  */
-			ic->f = instr(fmov_rm_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];  /* m */
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo4 == 0x9) {
-			/*  FMOV @Rm+,FRn  */
-			ic->f = instr(fmov_rm_postinc_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4];  /* m */
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo4 == 0xa) {
-			/*  FMOV FRm,@Rn  */
-			ic->f = instr(fmov_frm_rn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];  /* m */
-			ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];
-		} else if (lo4 == 0xb) {
-			/*  FMOV FRm,@-Rn  */
-			ic->f = instr(fmov_frm_predec_rn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];  /* m */
-			ic->arg[1] = (size_t)&cpu->cd.sh.r[r8];
-		} else if (lo4 == 0xc) {
-			/*  FMOV FRm,FRn  */
-			ic->f = instr(fmov_frm_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo8 == 0x0d) {
-			/*  FSTS FPUL,FRn  */
-			ic->f = instr(copy_fp_register);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fpul;
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo8 == 0x1d) {
-			/*  FLDS FRn,FPUL  */
-			ic->f = instr(copy_fp_register);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
-			ic->arg[1] = (size_t)&cpu->cd.sh.fpul;
-		} else if (lo8 == 0x2d) {
-			/*  FLOAT FPUL,FRn  */
-			ic->f = instr(float_fpul_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo8 == 0x3d) {
-			/*  FTRC FRm,FPUL  */
-			ic->f = instr(ftrc_frm_fpul);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo8 == 0x4d) {
-			/*  FNEG FRn  */
-			ic->f = instr(fneg_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo8 == 0x5d) {
-			/*  FABS FRn  */
-			ic->f = instr(fabs_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo8 == 0x6d) {
-			/*  FSQRT FRn  */
-			ic->f = instr(fsqrt_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo8 == 0x7d) {
-			/*  FSRRA FRn  */
-			ic->f = instr(fsrra_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo8 == 0x8d) {
-			/*  FLDI0 FRn  */
-			ic->f = instr(fldi_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
-			ic->arg[1] = 0x00000000;
-		} else if (lo8 == 0x9d) {
-			/*  FLDI1 FRn  */
-			ic->f = instr(fldi_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
-			ic->arg[1] = 0x3f800000;
-		} else if ((iword & 0x01ff) == 0x00ad) {
-			/*  FCNVSD FPUL,DRn  */
-			ic->f = instr(fcnvsd_fpul_drn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if ((iword & 0x01ff) == 0x00bd) {
-			/*  FCNVDS DRm,FPUL  */
-			ic->f = instr(fcnvds_drm_fpul);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (lo8 == 0xed) {
-			/*  FIPR FVm,FVn  */
-			ic->f = instr(fipr_fvm_fvn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[(r8<<2) & 0xc];  /* m */
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8 & 0xc];  /* n */
-		} else if ((iword & 0x01ff) == 0x00fd) {
-			/*  FSCA FPUL,DRn  */
-			ic->f = instr(fsca_fpul_drn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8];
-		} else if (iword == 0xf3fd) {
-			/*  FSCHG  */
-			ic->f = instr(fschg);
-		} else if (iword == 0xfbfd) {
-			/*  FRCHG  */
-			ic->f = instr(frchg);
-		} else if ((iword & 0xf3ff) == 0xf1fd) {
-			/*  FTRV XMTRX, FVn  */
-			ic->f = instr(ftrv_xmtrx_fvn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r8 & 0xc];
-		} else if (lo4 == 0xe) {
-			/*  FMAC FR0,FRm,FRn  */
-			ic->f = instr(fmac_fr0_frm_frn);
-			ic->arg[0] = (size_t)&cpu->cd.sh.fr[r4];
-			ic->arg[1] = (size_t)&cpu->cd.sh.fr[r8];
-		} else {
-			if (!cpu->translation_readahead)
-				fatal("Unimplemented opcode 0x%x,0x%02x\n",
-				    main_opcode, lo8);
-			goto bad;
-		}
-		break;
-
-	default:if (!cpu->translation_readahead)
-			fatal("Unimplemented main opcode 0x%x\n", main_opcode);
-		goto bad;
-	}
-
-
-#define	DYNTRANS_TO_BE_TRANSLATED_TAIL
-#include "cpu_dyntrans.cc"
-#undef	DYNTRANS_TO_BE_TRANSLATED_TAIL
-}
-
diff -Nru gxemul-0.6.2/src/cpus/experiment_arm_multi.c gxemul-0.7.0+dfsg/src/cpus/experiment_arm_multi.c
--- gxemul-0.6.2/src/cpus/experiment_arm_multi.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/experiment_arm_multi.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,160 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Given a list of common ARM load/store multiple opcodes, figure out (using 
+ *  simple brute force), which n bits (where n is low, e.g. 7) that cause the
+ *  best separation of the 24 bit opcode space into linear lists, where "best"
+ *  means to optimize the length of the longest such linear list.
+ *
+ *  The result is a set of bits, such as this:
+ *
+ *	  xxxx100P USWLnnnn llllllll llllllll
+ *	         ^ ^ ^^       ^^    (in this case, n = 6)
+ *
+ *  (it's a 24-bit space, because the s-bit isn't used).
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+
+int bit_count(unsigned int x)
+{
+	static const int c[16] = { 0,1,1,2, 1,2,2,3, 1,2,2,3, 2,3,3,4 };
+	return c[x & 15] + c[(x>>4) & 15] +
+	    c[(x>>8) & 15] + c[(x>>12) & 15] +
+	    c[(x>>16) & 15] + c[(x>>20) & 15] +
+	    c[(x>>24) & 15] + c[(x>>28) & 15];
+}
+
+
+int cmpfunc(const void *a, const void *b)
+{
+	int *pa = (int *) a, *pb = (int *) b;
+	if (*pa < *pb)
+		return -1;
+	if (*pa > *pb)
+		return  1;
+	return 0;
+}
+
+
+int calc_max_list_length(int *opcodes, int *tmp_table,
+	int n_opcodes, int bit_mask)
+{
+	int i, maxlen, curlen;
+
+	for (i=0; i<n_opcodes; i++)
+		tmp_table[i] = opcodes[i] & bit_mask;
+
+	qsort(tmp_table, n_opcodes, sizeof(int), cmpfunc);
+	curlen = maxlen = 1;
+
+	for (i=1; i<n_opcodes; i++)
+		if (tmp_table[i] == tmp_table[i-1]) {
+			curlen ++;
+			if (curlen > maxlen)
+				maxlen = curlen;
+		} else
+			curlen = 1;
+
+	return maxlen;
+}
+
+
+int main(int argc, char *argv[])
+{
+	FILE *f = fopen("cpu_arm_multi.txt", "r");
+	int n;
+	const int max = 10000;
+	int opcode[max];
+	int tmp_table[max];
+	int n_opcodes = 0;
+	int *max_len;
+	int bit_mask, best_bit_mask, best_bit_mask_len;
+
+	if (argc < 2) {
+		fprintf(stderr, "usage: %s n\n", argv[0]);
+		fprintf(stderr, "where n=6 might be a good choice\n");
+		exit(1);
+	}
+
+	n = atoi(argv[1]);
+
+	if (f == NULL) {
+		fprintf(stderr, "could not open cpu_arm_multi.txt\n");
+		exit(1);
+	}
+
+	/*  Read the opcodes:  */
+	while (!feof(f)) {
+		char s[100];
+		s[0] = s[sizeof(s)-1] = '\0';
+		fgets(s, sizeof(s), f);
+		if (s[0] == '0') {
+			if (n_opcodes > max) {
+				fprintf(stderr, "too many opcodes\n");
+				exit(1);
+			}
+			opcode[n_opcodes++] = strtol(s, NULL, 0);
+		}
+	}
+
+	printf("nr of opcodes = %i\n", n_opcodes);
+
+	max_len = malloc(sizeof(int) * (1 << 25));
+	if (max_len == NULL) {
+		fprintf(stderr, "out of memory\n");
+		exit(1);
+	}
+
+	best_bit_mask_len = -1;
+
+	for (bit_mask = 0; bit_mask <= 0x01ffffff; bit_mask ++) {
+		/*  Skip the s-bit:  */
+		if (bit_mask & 0x00400000)
+			continue;
+
+		if (bit_count(bit_mask) != n)
+			continue;
+
+		/*  Calculate the max list length for this bit_mask:  */
+		max_len[bit_mask] = calc_max_list_length(opcode,
+		    tmp_table, n_opcodes, bit_mask);
+
+		if (best_bit_mask_len == -1 ||
+		    max_len[bit_mask] < best_bit_mask_len) {
+			best_bit_mask_len = max_len[bit_mask];
+			best_bit_mask = bit_mask;
+			printf("best bit_mask so far: 0x%08x: %i\n",
+			    best_bit_mask, best_bit_mask_len);
+		}
+	}
+
+	return 0;
+}
+
diff -Nru gxemul-0.6.2/src/cpus/experiment_arm_multi.cc gxemul-0.7.0+dfsg/src/cpus/experiment_arm_multi.cc
--- gxemul-0.6.2/src/cpus/experiment_arm_multi.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/experiment_arm_multi.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,160 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Given a list of common ARM load/store multiple opcodes, figure out (using 
- *  simple brute force), which n bits (where n is low, e.g. 7) that cause the
- *  best separation of the 24 bit opcode space into linear lists, where "best"
- *  means to optimize the length of the longest such linear list.
- *
- *  The result is a set of bits, such as this:
- *
- *	  xxxx100P USWLnnnn llllllll llllllll
- *	         ^ ^ ^^       ^^    (in this case, n = 6)
- *
- *  (it's a 24-bit space, because the s-bit isn't used).
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-
-
-int bit_count(unsigned int x)
-{
-	static const int c[16] = { 0,1,1,2, 1,2,2,3, 1,2,2,3, 2,3,3,4 };
-	return c[x & 15] + c[(x>>4) & 15] +
-	    c[(x>>8) & 15] + c[(x>>12) & 15] +
-	    c[(x>>16) & 15] + c[(x>>20) & 15] +
-	    c[(x>>24) & 15] + c[(x>>28) & 15];
-}
-
-
-int cmpfunc(const void *a, const void *b)
-{
-	int *pa = (int *) a, *pb = (int *) b;
-	if (*pa < *pb)
-		return -1;
-	if (*pa > *pb)
-		return  1;
-	return 0;
-}
-
-
-int calc_max_list_length(int *opcodes, int *tmp_table,
-	int n_opcodes, int bit_mask)
-{
-	int i, maxlen, curlen;
-
-	for (i=0; i<n_opcodes; i++)
-		tmp_table[i] = opcodes[i] & bit_mask;
-
-	qsort(tmp_table, n_opcodes, sizeof(int), cmpfunc);
-	curlen = maxlen = 1;
-
-	for (i=1; i<n_opcodes; i++)
-		if (tmp_table[i] == tmp_table[i-1]) {
-			curlen ++;
-			if (curlen > maxlen)
-				maxlen = curlen;
-		} else
-			curlen = 1;
-
-	return maxlen;
-}
-
-
-int main(int argc, char *argv[])
-{
-	FILE *f = fopen("cpu_arm_multi.txt", "r");
-	int n;
-	const int max = 10000;
-	int opcode[max];
-	int tmp_table[max];
-	int n_opcodes = 0;
-	int *max_len;
-	int bit_mask, best_bit_mask, best_bit_mask_len;
-
-	if (argc < 2) {
-		fprintf(stderr, "usage: %s n\n", argv[0]);
-		fprintf(stderr, "where n=6 might be a good choice\n");
-		exit(1);
-	}
-
-	n = atoi(argv[1]);
-
-	if (f == NULL) {
-		fprintf(stderr, "could not open cpu_arm_multi.txt\n");
-		exit(1);
-	}
-
-	/*  Read the opcodes:  */
-	while (!feof(f)) {
-		char s[100];
-		s[0] = s[sizeof(s)-1] = '\0';
-		fgets(s, sizeof(s), f);
-		if (s[0] == '0') {
-			if (n_opcodes > max) {
-				fprintf(stderr, "too many opcodes\n");
-				exit(1);
-			}
-			opcode[n_opcodes++] = strtol(s, NULL, 0);
-		}
-	}
-
-	printf("nr of opcodes = %i\n", n_opcodes);
-
-	max_len = malloc(sizeof(int) * (1 << 25));
-	if (max_len == NULL) {
-		fprintf(stderr, "out of memory\n");
-		exit(1);
-	}
-
-	best_bit_mask_len = -1;
-
-	for (bit_mask = 0; bit_mask <= 0x01ffffff; bit_mask ++) {
-		/*  Skip the s-bit:  */
-		if (bit_mask & 0x00400000)
-			continue;
-
-		if (bit_count(bit_mask) != n)
-			continue;
-
-		/*  Calculate the max list length for this bit_mask:  */
-		max_len[bit_mask] = calc_max_list_length(opcode,
-		    tmp_table, n_opcodes, bit_mask);
-
-		if (best_bit_mask_len == -1 ||
-		    max_len[bit_mask] < best_bit_mask_len) {
-			best_bit_mask_len = max_len[bit_mask];
-			best_bit_mask = bit_mask;
-			printf("best bit_mask so far: 0x%08x: %i\n",
-			    best_bit_mask, best_bit_mask_len);
-		}
-	}
-
-	return 0;
-}
-
diff -Nru gxemul-0.6.2/src/cpus/generate_alpha_misc.c gxemul-0.7.0+dfsg/src/cpus/generate_alpha_misc.c
--- gxemul-0.6.2/src/cpus/generate_alpha_misc.c	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/generate_alpha_misc.c	2021-11-27 09:42:23.000000000 +0000
@@ -69,7 +69,7 @@
 			if (scale)
 				printf("#define ALU_S%i\n", scale);
 
-			printf("#include \"cpu_alpha_instr_alu.cc\"\n");
+			printf("#include \"cpu_alpha_instr_alu.c\"\n");
 
 			if (imm)
 				printf("#undef ALU_IMM\n");
@@ -119,7 +119,7 @@
 			}
 			if (not)
 				printf("#define ALU_NOT\n");
-			printf("#include \"cpu_alpha_instr_alu.cc\"\n");
+			printf("#include \"cpu_alpha_instr_alu.c\"\n");
 
 			if (imm)
 				printf("#undef ALU_IMM\n");
@@ -158,7 +158,7 @@
 		if (strcmp(cmps[op]+strlen(cmps[op])-2,"eq") == 0)
 			printf("#define ALU_CMP_EQ\n");
 
-		printf("#include \"cpu_alpha_instr_alu.cc\"\n");
+		printf("#include \"cpu_alpha_instr_alu.c\"\n");
 
 		if (cmps[op][0] == 'u')
 			printf("#undef ALU_UNSIGNED\n");
@@ -184,7 +184,7 @@
 		if (imm)
 			printf("#define ALU_IMM\n");
 		printf("#define ALU_CMOV_%s\n", cmov[op]);
-		printf("#include \"cpu_alpha_instr_alu.cc\"\n");
+		printf("#include \"cpu_alpha_instr_alu.c\"\n");
 		printf("#undef ALU_CMOV_%s\n", cmov[op]);
 		if (imm)
 			printf("#undef ALU_IMM\n");
@@ -200,7 +200,7 @@
 		printf("\n");
 		if (imm)
 			printf("#define ALU_IMM\n");
-		printf("#include \"cpu_alpha_instr_alu.cc\"\n");
+		printf("#include \"cpu_alpha_instr_alu.c\"\n");
 		if (imm)
 			printf("#undef ALU_IMM\n");
 		printf("#undef ALU_N\n");
@@ -241,7 +241,7 @@
 		}
 		if (lo)
 			printf("#define ALU_LO\n");
-		printf("#include \"cpu_alpha_instr_alu.cc\"\n");
+		printf("#include \"cpu_alpha_instr_alu.c\"\n");
 		switch (size) {
 		case 0:	printf("#undef ALU_B\n"); break;
 		case 1:	printf("#undef ALU_W\n"); break;
@@ -301,7 +301,7 @@
 			if (llsc)
 				printf("_llsc");
 			printf("\n");
-			printf("#include \"cpu_alpha_instr_loadstore.cc\"\n");
+			printf("#include \"cpu_alpha_instr_loadstore.c\"\n");
 			printf("#undef LS_N\n");
 			printf("#undef LS_GENERIC_N\n");
 			switch (size) {
@@ -343,7 +343,7 @@
 			printf("%s", sizechar[size]);
 			printf("_u");		/*  NOTE: unaligned  */
 			printf("\n");
-			printf("#include \"cpu_alpha_instr_loadstore.cc\"\n");
+			printf("#include \"cpu_alpha_instr_loadstore.c\"\n");
 			printf("#undef LS_N\n");
 			printf("#undef LS_GENERIC_N\n");
 			printf("#undef LS_Q\n");
diff -Nru gxemul-0.6.2/src/cpus/generate_arm_dpi.c gxemul-0.7.0+dfsg/src/cpus/generate_arm_dpi.c
--- gxemul-0.6.2/src/cpus/generate_arm_dpi.c	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/generate_arm_dpi.c	2021-11-27 09:42:23.000000000 +0000
@@ -94,7 +94,7 @@
 		}
 		if (pc)	printf("#define A__PC\n");
 		printf("#define A__%s\n", uppercase(op[a]));
-		printf("#include \"cpu_arm_instr_dpi.cc\"\n");
+		printf("#include \"cpu_arm_instr_dpi.c\"\n");
 		printf("#undef A__%s\n", uppercase(op[a]));
 		if (s)	printf("#undef A__S\n");
 		switch (reg) {
diff -Nru gxemul-0.6.2/src/cpus/generate_arm_loadstore.c gxemul-0.7.0+dfsg/src/cpus/generate_arm_loadstore.c
--- gxemul-0.6.2/src/cpus/generate_arm_loadstore.c	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/generate_arm_loadstore.c	2021-11-27 09:42:23.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -59,14 +59,13 @@
 	    "#define DYNTRANS_PC_TO_POINTERS arm_pc_to_pointers\n"
 	    "#include \"quick_pc_to_pointers.h\"\n"
 	    "#define reg(x) (*((uint32_t *)(x)))\n");
-	printf("extern void arm_instr_nop(struct cpu *, "
-	    "struct arm_instr_call *);\n");
-	printf("extern void arm_instr_invalid(struct cpu *, "
-	    "struct arm_instr_call *);\n");
+	printf("extern void arm_instr_nop(struct cpu *, struct arm_instr_call *);\n");
+	printf("extern void arm_instr_nothing(struct cpu *, struct arm_instr_call *);\n");
+	printf("extern void arm_instr_invalid(struct cpu *, struct arm_instr_call *);\n");
 	printf("extern void arm_pc_to_pointers(struct cpu *);\n");
-
-    if (!only_array)
-	for (reg=0; reg<=1; reg++)
+	
+	if (!only_array)
+	  for (reg=0; reg<=1; reg++)
 	      for (b=0; b<=1; b++)
 		  for (l=0; l<=1; l++) {
 			printf("#define A__NAME__general arm_instr_%s_"
@@ -103,7 +102,7 @@
 			if (u)	printf("#define A__U\n");
 			if (p)	printf("#define A__P\n");
 			if (reg)printf("#define A__REG\n");
-			printf("#include \"cpu_arm_instr_loadstore.cc\"\n");
+			printf("#include \"cpu_arm_instr_loadstore.c\"\n");
 			if (l)	printf("#undef A__L\n");
 			if (w)	printf("#undef A__W\n");
 			if (b)	printf("#undef A__B\n");
@@ -217,8 +216,8 @@
 
 	/*  "Addressing mode 3":  */
 
-    if (!only_array)
-	for (reg=0; reg<=1; reg++)
+	if (!only_array)
+	  for (reg=0; reg<=1; reg++)
 	      for (h=0; h<=1; h++)
 		  for (s=0; s<=1; s++)
 		    for (l=0; l<=1; l++) {
@@ -268,7 +267,7 @@
 			if (u)	printf("#define A__U\n");
 			if (p)	printf("#define A__P\n");
 			if (reg)printf("#define A__REG\n");
-			printf("#include \"cpu_arm_instr_loadstore.cc\"\n");
+			printf("#include \"cpu_arm_instr_loadstore.c\"\n");
 			if (s)	printf("#undef A__SIGNED\n");
 			if (l)	printf("#undef A__L\n");
 			if (w)	printf("#undef A__W\n");
diff -Nru gxemul-0.6.2/src/cpus/generate_head.c gxemul-0.7.0+dfsg/src/cpus/generate_head.c
--- gxemul-0.6.2/src/cpus/generate_head.c	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/generate_head.c	2021-11-27 09:42:23.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -53,7 +53,7 @@
 
 int main(int argc, char *argv[])
 {
-	char *a, *b;
+	char *a; //, *b;
 
 	if (argc != 3) {
 		fprintf(stderr, "usage: %s arch Arch\n", argv[0]);
@@ -63,7 +63,7 @@
 	}
 
 	a = argv[1];
-	b = argv[2];
+	// b = argv[2];
 
 
 	printf("\n/*  AUTOMATICALLY GENERATED! Do not edit.  */\n\n");
@@ -114,10 +114,9 @@
 	printf("#define COMBINE_INSTRUCTIONS %s_combine_instructions\n", a);
 	printf("#define DISASSEMBLE %s_cpu_disassemble_instr\n", a);
 
-	printf("\nextern volatile int single_step, single_step_breakpoint;"
-	    "\nextern int debugger_n_steps_left_before_interaction;\n"
-	    "extern int old_show_trace_tree;\n"
-	    "extern int old_instruction_trace;\n"
+	printf("\nextern bool single_step;\n"
+	    "extern bool about_to_enter_single_step;\n"
+	    "extern int single_step_breakpoint;\n"
 	    "extern int old_quiet_mode;\n"
 	    "extern int quiet_mode;\n");
 
@@ -138,6 +137,7 @@
 	    "translated\n *  mode.\n */\n");
 	printf("X(nothing)\n{\n");
 	printf("\tcpu->cd.%s.next_ic --;\n", a);
+	printf("\tcpu->ninstrs --;\n");
 	printf("}\n\n");
 
 	/*  Ugly special hacks for SH[34]:  */
diff -Nru gxemul-0.6.2/src/cpus/generate_m88k_bcnd.c gxemul-0.7.0+dfsg/src/cpus/generate_m88k_bcnd.c
--- gxemul-0.6.2/src/cpus/generate_m88k_bcnd.c	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/generate_m88k_bcnd.c	2021-11-27 09:42:23.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2007-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -43,6 +43,7 @@
 	case 0x1: printf("gt0"); break;
 	case 0x2: printf("eq0"); break;
 	case 0x3: printf("ge0"); break;
+	case 0x5: printf("not_maxneg_nor_zero"); break;
 	case 0x7: printf("not_maxneg"); break;
 	case 0x8: printf("maxneg"); break;
 	case 0xc: printf("lt0"); break;
@@ -58,6 +59,7 @@
 	case 0x1: printf("> 0"); break;
 	case 0x2: printf("== 0"); break;
 	case 0x3: printf(">= 0"); break;
+	case 0x5: printf("!= 0x80000000UL"); break;
 	case 0x7: printf("!= 0x80000000UL"); break;
 	case 0x8: printf("== 0x80000000UL"); break;
 	case 0xc: printf("< 0"); break;
@@ -79,8 +81,12 @@
 	/*  Easiest case is without the n_bit:  */
 	if (!n_bit) {
 		printf("\tif ((%sint32_t)reg(ic->arg[0]) ",
-		    (m5 == 7 || m5 == 8)? "u" : "");
+		    (m5 == 5 || m5 == 7 || m5 == 8)? "u" : "");
 		print_operator(m5);
+
+		if (m5 == 5)
+			printf(" && (int32_t)reg(ic->arg[0]) != 0");
+
 		printf(") {\n");
 
 		if (samepage)
@@ -95,8 +101,10 @@
 	} else {
 		/*  n_bit, i.e. delay slot:  */
 		printf("\tint cond = (%sint32_t)reg(ic->arg[0]) ",
-		    (m5 == 7 || m5 == 8)? "u" : "");
+		    (m5 == 5 || m5 == 7 || m5 == 8)? "u" : "");
 		print_operator(m5);
+		if (m5 == 5)
+			printf(" && (int32_t)reg(ic->arg[0]) != 0");
 		printf(";\n");
 
 		printf("\tSYNCH_PC;\n");
@@ -141,7 +149,7 @@
 	for (samepage=0; samepage<=1; samepage++)
 		for (n_bit=0; n_bit<=1; n_bit++)
 			for (m5=0; m5<=31; m5++) {
-				if (m5 == 1 || m5 == 2 || m5 == 3 || m5 == 7 || m5 == 8 ||
+				if (m5 == 1 || m5 == 2 || m5 == 3 || m5 == 5 || m5 == 7 || m5 == 8 ||
 				    m5 == 0xc || m5 == 0xd || m5 == 0xe)
 					bcnd(samepage, n_bit, m5);
 			}
@@ -155,7 +163,7 @@
 				if (m5 || n_bit || samepage)
 					printf(",\n");
 
-				if (m5 == 1 || m5 == 2 || m5 == 3 || m5 == 7 || m5 == 8 ||
+				if (m5 == 1 || m5 == 2 || m5 == 3 || m5 == 5 || m5 == 7 || m5 == 8 ||
 				    m5 == 0xc || m5 == 0xd || m5 == 0xe) {
 					if (samepage && n_bit)
 						printf("NULL");
diff -Nru gxemul-0.6.2/src/cpus/generate_m88k_loadstore.c gxemul-0.7.0+dfsg/src/cpus/generate_m88k_loadstore.c
--- gxemul-0.6.2/src/cpus/generate_m88k_loadstore.c	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/generate_m88k_loadstore.c	2021-11-27 09:42:23.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2007-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -35,6 +35,8 @@
  *			  and only when using register offset)
  *	1 bit ".usr" (only when using register offset)
  *	1 bit registeroffset
+ *	1 bit indicating that Program Counter syncronization is skipped
+ *		(for using the load/store routine from another instruction)
  */
 
 #include <stdio.h>
@@ -47,13 +49,15 @@
 #define	M88K_LOADSTORE_SCALEDNESS	32
 #define	M88K_LOADSTORE_USR		64
 #define	M88K_LOADSTORE_REGISTEROFFSET	128
+#define	M88K_LOADSTORE_NO_PC_SYNC	256
 
 
 int generated_functions = 0;
 
 
 void print_function_name(int size, int store, int signedness,
-	int endianness, int scaledness, int usr, int registeroffset)
+	int endianness, int scaledness, int usr, int registeroffset,
+	int no_pc_sync)
 {
 	if (store)
 		printf("st");
@@ -81,11 +85,15 @@
 
 	if (registeroffset)
 		printf("_regofs");
+
+	if (no_pc_sync)
+		printf("_nopcsync");
 }
 
 
 void loadstore(int size, int store, int signedness,
-	int endianness, int scaledness, int usr, int registeroffset)
+	int endianness, int scaledness, int usr, int registeroffset,
+	int no_pc_sync)
 {
 	if (store && signedness)
 		return;
@@ -109,12 +117,12 @@
 
 	printf("#define LS_N m88k_instr_");
 	print_function_name(size, store, signedness, endianness,
-	    scaledness, usr, registeroffset);
+	    scaledness, usr, registeroffset, no_pc_sync);
 	printf("\n");
 
 	printf("#define LS_GENERIC_N m88k_generic_");
 	print_function_name(size, store, signedness, -1,
-	    scaledness, usr, registeroffset);
+	    scaledness, usr, registeroffset, no_pc_sync);
 	printf("\n");
 
 	printf("#define LS_%i\n", 1 << size);
@@ -140,9 +148,15 @@
 	if (registeroffset)
 		printf("#define LS_REGOFS\n");
 
-	printf("#include \"cpu_m88k_instr_loadstore.cc\"\n");
+	if (no_pc_sync)
+		printf("#define LS_NO_PC_SYNC\n");
+
+	printf("#include \"cpu_m88k_instr_loadstore.c\"\n");
 	generated_functions ++;
 
+	if (no_pc_sync)
+		printf("#undef LS_NO_PC_SYNC\n");
+
 	if (registeroffset)
 		printf("#undef LS_REGOFS\n");
 
@@ -179,14 +193,16 @@
 int main(int argc, char *argv[])
 {
 	int size, store, signedness, endianness, scaledness, usr,
-	    registeroffset;
+	    registeroffset, no_pc_sync;
 
 	printf("\n/*  AUTOMATICALLY GENERATED! Do not edit.  */\n\n");
 
-	for (registeroffset=0; registeroffset<=M88K_LOADSTORE_REGISTEROFFSET;
+	for (no_pc_sync=0; no_pc_sync<=M88K_LOADSTORE_NO_PC_SYNC;
+		      no_pc_sync+=M88K_LOADSTORE_NO_PC_SYNC)
+	 for (registeroffset=0; registeroffset<=M88K_LOADSTORE_REGISTEROFFSET;
 		      registeroffset+=M88K_LOADSTORE_REGISTEROFFSET)
-	 for (usr=0; usr<=M88K_LOADSTORE_USR; usr+=M88K_LOADSTORE_USR)
-	  for (scaledness=0; scaledness<=M88K_LOADSTORE_SCALEDNESS;
+	  for (usr=0; usr<=M88K_LOADSTORE_USR; usr+=M88K_LOADSTORE_USR)
+	   for (scaledness=0; scaledness<=M88K_LOADSTORE_SCALEDNESS;
 			scaledness+=M88K_LOADSTORE_SCALEDNESS)
 	    for (endianness=0; endianness<=M88K_LOADSTORE_ENDIANNESS;
 			  endianness+=M88K_LOADSTORE_ENDIANNESS)
@@ -196,15 +212,18 @@
 			      store+=M88K_LOADSTORE_STORE)
 		  for (size=0; size<=3; size++)
 			loadstore(size, store, signedness,
-			    endianness, scaledness, usr, registeroffset);
+			    endianness, scaledness, usr, registeroffset,
+			    no_pc_sync);
 
 	/*  Array of pointers to fast load/store functions:  */
-	printf("\n\nvoid (*m88k_loadstore[256])(struct cpu *, struct "
+	printf("\n\nvoid (*m88k_loadstore[512])(struct cpu *, struct "
 	    "m88k_instr_call *) = {\n");
-	for (registeroffset=0; registeroffset<=M88K_LOADSTORE_REGISTEROFFSET;
+	for (no_pc_sync=0; no_pc_sync<=M88K_LOADSTORE_NO_PC_SYNC;
+		      no_pc_sync+=M88K_LOADSTORE_NO_PC_SYNC)
+	 for (registeroffset=0; registeroffset<=M88K_LOADSTORE_REGISTEROFFSET;
 		      registeroffset+=M88K_LOADSTORE_REGISTEROFFSET)
-	 for (usr=0; usr<=M88K_LOADSTORE_USR; usr+=M88K_LOADSTORE_USR)
-	  for (scaledness=0; scaledness<=M88K_LOADSTORE_SCALEDNESS;
+	  for (usr=0; usr<=M88K_LOADSTORE_USR; usr+=M88K_LOADSTORE_USR)
+	   for (scaledness=0; scaledness<=M88K_LOADSTORE_SCALEDNESS;
 			scaledness+=M88K_LOADSTORE_SCALEDNESS)
 	    for (endianness=0; endianness<=M88K_LOADSTORE_ENDIANNESS;
 			  endianness+=M88K_LOADSTORE_ENDIANNESS)
@@ -214,7 +233,7 @@
 			      store+=M88K_LOADSTORE_STORE)
 		  for (size=0; size<=3; size++) {
 			if (store || size || signedness || endianness
-			    || scaledness || usr || registeroffset)
+			    || scaledness || usr || registeroffset || no_pc_sync)
 				printf(",\n");
 
 			if (store && signedness) {
@@ -239,7 +258,8 @@
 
 			printf("\tm88k_instr_");
 			print_function_name(size, store, signedness,
-			    endianness, scaledness, usr, registeroffset);
+			    endianness, scaledness, usr, registeroffset,
+			    no_pc_sync);
 		}
 	printf(" };\n");
 
diff -Nru gxemul-0.6.2/src/cpus/generate_mips_loadstore.c gxemul-0.7.0+dfsg/src/cpus/generate_mips_loadstore.c
--- gxemul-0.6.2/src/cpus/generate_mips_loadstore.c	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/generate_mips_loadstore.c	2021-11-27 09:42:23.000000000 +0000
@@ -88,7 +88,7 @@
 	if (endianness == 0)
 		printf("#define LS_INCLUDE_GENERIC\n");
 
-	printf("#include \"cpu_mips_instr_loadstore.cc\"\n");
+	printf("#include \"cpu_mips_instr_loadstore.c\"\n");
 
 	if (endianness == 0)
 		printf("#undef LS_INCLUDE_GENERIC\n");
diff -Nru gxemul-0.6.2/src/cpus/generate_ppc_loadstore.c gxemul-0.7.0+dfsg/src/cpus/generate_ppc_loadstore.c
--- gxemul-0.6.2/src/cpus/generate_ppc_loadstore.c	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/generate_ppc_loadstore.c	2021-11-27 09:42:23.000000000 +0000
@@ -99,7 +99,7 @@
 				printf("_0");
 			printf("\n");
 
-			printf("#include \"cpu_ppc_instr_loadstore.cc\"\n");
+			printf("#include \"cpu_ppc_instr_loadstore.c\"\n");
 
 			printf("#undef LS_N\n");
 			printf("#undef LS_GENERIC_N\n");
@@ -180,7 +180,7 @@
 			printf("x");
 			printf("\n");
 
-			printf("#include \"cpu_ppc_instr_loadstore.cc\"\n");
+			printf("#include \"cpu_ppc_instr_loadstore.c\"\n");
 
 			printf("#undef LS_N\n");
 			printf("#undef LS_GENERIC_N\n");
@@ -286,13 +286,13 @@
 	    "#define LS_GENERIC_N ppc%s_generic_lhbrx\n"
 	    "#define LS_N ppc%s_instr_lhbrx\n"
 	    "#define LS_LOAD\n"
-	    "#include \"cpu_ppc_instr_loadstore.cc\"\n"
+	    "#include \"cpu_ppc_instr_loadstore.c\"\n"
 	    "#undef LS_LOAD\n"
 	    "#undef LS_N\n"
 	    "#undef LS_GENERIC_N\n"
 	    "#define LS_GENERIC_N ppc%s_generic_sthbrx\n"
 	    "#define LS_N ppc%s_instr_sthbrx\n"
-	    "#include \"cpu_ppc_instr_loadstore.cc\"\n"
+	    "#include \"cpu_ppc_instr_loadstore.c\"\n"
 	    "#undef LS_N\n"
 	    "#undef LS_GENERIC_N\n"
 	    "#undef LS_H\n"
@@ -303,13 +303,13 @@
 	    "#define LS_GENERIC_N ppc%s_generic_lwbrx\n"
 	    "#define LS_N ppc%s_instr_lwbrx\n"
 	    "#define LS_LOAD\n"
-	    "#include \"cpu_ppc_instr_loadstore.cc\"\n"
+	    "#include \"cpu_ppc_instr_loadstore.c\"\n"
 	    "#undef LS_LOAD\n"
 	    "#undef LS_N\n"
 	    "#undef LS_GENERIC_N\n"
 	    "#define LS_GENERIC_N ppc%s_generic_stwbrx\n"
 	    "#define LS_N ppc%s_instr_stwbrx\n"
-	    "#include \"cpu_ppc_instr_loadstore.cc\"\n"
+	    "#include \"cpu_ppc_instr_loadstore.c\"\n"
 	    "#undef LS_N\n"
 	    "#undef LS_GENERIC_N\n"
 	    "#undef LS_W\n"
diff -Nru gxemul-0.6.2/src/cpus/generate_tail.c gxemul-0.7.0+dfsg/src/cpus/generate_tail.c
--- gxemul-0.6.2/src/cpus/generate_tail.c	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/generate_tail.c	2021-11-27 09:42:23.000000000 +0000
@@ -71,48 +71,48 @@
 
 	printf("#define DYNTRANS_FUNCTION_TRACE_DEF "
 	    "%s_cpu_functioncall_trace\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_FUNCTION_TRACE_DEF\n\n");
 
 	printf("#define DYNTRANS_INIT_TABLES "
 	    "%s_cpu_init_tables\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_INIT_TABLES\n\n");
 
 	printf("#define DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE_DEF "
 	    "%s_tc_allocate_default_page\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE_DEF\n\n");
 
 	printf("#define DYNTRANS_INVAL_ENTRY\n");
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_INVAL_ENTRY\n\n");
 
 	printf("#define DYNTRANS_INVALIDATE_TC "
 	    "%s_invalidate_translation_caches\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_INVALIDATE_TC\n\n");
 
 	printf("#define DYNTRANS_INVALIDATE_TC_CODE "
 	    "%s_invalidate_code_translation\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_INVALIDATE_TC_CODE\n\n");
 
 	printf("#define DYNTRANS_UPDATE_TRANSLATION_TABLE "
 	    "%s_update_translation_table\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_UPDATE_TRANSLATION_TABLE\n\n");
 
 	printf("#define MEMORY_RW %s_memory_rw\n", a);
 	printf("#define MEM_%s\n", uppercase(a));
-	printf("#include \"memory_rw.cc\"\n");
+	printf("#include \"memory_rw.c\"\n");
 	printf("#undef MEM_%s\n", uppercase(a));
 	printf("#undef MEMORY_RW\n\n");
 
 	printf("#define DYNTRANS_PC_TO_POINTERS_FUNC %s_pc_to_pointers\n", a);
 	printf("#define DYNTRANS_PC_TO_POINTERS_GENERIC "
 	    "%s_pc_to_pointers_generic\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_PC_TO_POINTERS_FUNC\n\n");
 	printf("#undef DYNTRANS_PC_TO_POINTERS_GENERIC\n\n");
 
@@ -129,10 +129,10 @@
 	printf("#endif\n");
 	printf("#define COMBINE(n) %s_combine_ ## n\n", a);
 	printf("#include \"quick_pc_to_pointers.h\"\n");
-	printf("#include \"cpu_%s_instr.cc\"\n\n", a);
+	printf("#include \"cpu_%s_instr.c\"\n\n", a);
 
 	printf("#define DYNTRANS_RUN_INSTR_DEF %s_run_instr\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_RUN_INSTR_DEF\n\n");
 
 
@@ -157,39 +157,39 @@
 	printf("#undef DYNTRANS_INVALIDATE_TLB_ENTRY\n"
 	    "#define DYNTRANS_INVALIDATE_TLB_ENTRY "
 	    "%s32_invalidate_tlb_entry\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_INVAL_ENTRY\n\n");
 	printf("#define DYNTRANS_INVALIDATE_TC "
 	    "%s32_invalidate_translation_caches\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_INVALIDATE_TC\n\n");
 	printf("#define DYNTRANS_INVALIDATE_TC_CODE "
 	    "%s32_invalidate_code_translation\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_INVALIDATE_TC_CODE\n\n");
 	printf("#define DYNTRANS_UPDATE_TRANSLATION_TABLE "
 	    "%s32_update_translation_table\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_UPDATE_TRANSLATION_TABLE\n\n");
 	printf("#define DYNTRANS_PC_TO_POINTERS_FUNC %s32_pc_to_pointers\n", a);
 	printf("#define DYNTRANS_PC_TO_POINTERS_GENERIC "
 	    "%s32_pc_to_pointers_generic\n", a);
 	printf("#undef DYNTRANS_PC_TO_POINTERS\n"
 	    "#define DYNTRANS_PC_TO_POINTERS %s32_pc_to_pointers\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_PC_TO_POINTERS_FUNC\n\n");
 	printf("#undef DYNTRANS_PC_TO_POINTERS_GENERIC\n\n");
 	printf("#undef COMBINE\n");
 	printf("#define COMBINE(n) %s32_combine_ ## n\n", a);
 	printf("#include \"quick_pc_to_pointers.h\"\n");
-	printf("#include \"cpu_%s_instr.cc\"\n", a);
+	printf("#include \"cpu_%s_instr.c\"\n", a);
 
 	printf("\n#undef DYNTRANS_PC_TO_POINTERS\n"
 	    "#define DYNTRANS_PC_TO_POINTERS %s_pc_to_pointers\n"
 	    "#define DYNTRANS_PC_TO_POINTERS32 %s32_pc_to_pointers\n\n", a, a);
 
 	printf("#define DYNTRANS_RUN_INSTR_DEF %s32_run_instr\n", a);
-	printf("#include \"cpu_dyntrans.cc\"\n");
+	printf("#include \"cpu_dyntrans.c\"\n");
 	printf("#undef DYNTRANS_RUN_INSTR_DEF\n\n");
 
 	printf("#endif /*  DYNTRANS_DUALMODE_32  */\n\n\n");
diff -Nru gxemul-0.6.2/src/cpus/Makefile.skel gxemul-0.7.0+dfsg/src/cpus/Makefile.skel
--- gxemul-0.6.2/src/cpus/Makefile.skel	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #  Makefile for GXemul src/cpus
 #
 
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(DINCLUDE)
+CFLAGS=$(CWARNINGS) $(COPTIM) $(DINCLUDE)
 
 OBJS=cpu.o $(CPU_ARCHS) $(CPU_BACKENDS)
 TOOLS=generate_head generate_tail $(CPU_TOOLS)
@@ -21,160 +21,184 @@
 
 ###############################################################################
 
-cpu_alpha.o: cpu_alpha.cc cpu_alpha_instr.cc cpu_dyntrans.cc memory_rw.cc \
-	tmp_alpha_head.cc tmp_alpha_tail.cc
+cpu_alpha.o: cpu_alpha.c cpu_alpha_instr.c cpu_dyntrans.c memory_rw.c \
+	tmp_alpha_head.c tmp_alpha_tail.c
 
-cpu_alpha_instr.cc: cpu_alpha_instr_alu.cc tmp_alpha_misc.cc
+cpu_alpha_instr.c: cpu_alpha_instr_alu.c tmp_alpha_misc.c
 
-tmp_alpha_misc.cc: cpu_alpha_instr_loadstore.cc generate_alpha_misc
-	./generate_alpha_misc > tmp_alpha_misc.cc
+tmp_alpha_misc.c: cpu_alpha_instr_loadstore.c generate_alpha_misc
+	./generate_alpha_misc > tmp_alpha_misc.c
 
-tmp_alpha_head.cc: generate_head
-	./generate_head alpha Alpha > tmp_alpha_head.cc
+tmp_alpha_head.c: generate_head
+	./generate_head alpha Alpha > tmp_alpha_head.c
 
-tmp_alpha_tail.cc: generate_tail
-	./generate_tail alpha Alpha > tmp_alpha_tail.cc
+tmp_alpha_tail.c: generate_tail
+	./generate_tail alpha Alpha > tmp_alpha_tail.c
 
 
 ###############################################################################
 
-cpu_arm.o: cpu_arm.cc cpu_arm_instr.cc cpu_dyntrans.cc memory_rw.cc \
-	tmp_arm_head.cc tmp_arm_tail.cc
+cpu_arm.o: cpu_arm.c cpu_arm_instr.c cpu_dyntrans.c memory_rw.c \
+	tmp_arm_head.c tmp_arm_tail.c
 
-cpu_arm_instr.cc: cpu_arm_instr_misc.cc
+cpu_arm_instr.c: cpu_arm_instr_misc.c
 
-tmp_arm_loadstore.cc: cpu_arm_instr_loadstore.cc generate_arm_loadstore
-	./generate_arm_loadstore > tmp_arm_loadstore.cc
-tmp_arm_loadstore_p0_u0_w0.cc: cpu_arm_instr_loadstore.cc generate_arm_loadstore
-	./generate_arm_loadstore 0 0 0 > tmp_arm_loadstore_p0_u0_w0.cc
-tmp_arm_loadstore_p0_u0_w1.cc: cpu_arm_instr_loadstore.cc generate_arm_loadstore
-	./generate_arm_loadstore 0 0 1 > tmp_arm_loadstore_p0_u0_w1.cc
-tmp_arm_loadstore_p0_u1_w0.cc: cpu_arm_instr_loadstore.cc generate_arm_loadstore
-	./generate_arm_loadstore 0 1 0 > tmp_arm_loadstore_p0_u1_w0.cc
-tmp_arm_loadstore_p0_u1_w1.cc: cpu_arm_instr_loadstore.cc generate_arm_loadstore
-	./generate_arm_loadstore 0 1 1 > tmp_arm_loadstore_p0_u1_w1.cc
-tmp_arm_loadstore_p1_u0_w0.cc: cpu_arm_instr_loadstore.cc generate_arm_loadstore
-	./generate_arm_loadstore 1 0 0 > tmp_arm_loadstore_p1_u0_w0.cc
-tmp_arm_loadstore_p1_u0_w1.cc: cpu_arm_instr_loadstore.cc generate_arm_loadstore
-	./generate_arm_loadstore 1 0 1 > tmp_arm_loadstore_p1_u0_w1.cc
-tmp_arm_loadstore_p1_u1_w0.cc: cpu_arm_instr_loadstore.cc generate_arm_loadstore
-	./generate_arm_loadstore 1 1 0 > tmp_arm_loadstore_p1_u1_w0.cc
-tmp_arm_loadstore_p1_u1_w1.cc: cpu_arm_instr_loadstore.cc generate_arm_loadstore
-	./generate_arm_loadstore 1 1 1 > tmp_arm_loadstore_p1_u1_w1.cc
+tmp_arm_loadstore.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
+	./generate_arm_loadstore > tmp_arm_loadstore.c
+tmp_arm_loadstore_p0_u0_w0.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
+	./generate_arm_loadstore 0 0 0 > tmp_arm_loadstore_p0_u0_w0.c
+tmp_arm_loadstore_p0_u0_w1.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
+	./generate_arm_loadstore 0 0 1 > tmp_arm_loadstore_p0_u0_w1.c
+tmp_arm_loadstore_p0_u1_w0.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
+	./generate_arm_loadstore 0 1 0 > tmp_arm_loadstore_p0_u1_w0.c
+tmp_arm_loadstore_p0_u1_w1.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
+	./generate_arm_loadstore 0 1 1 > tmp_arm_loadstore_p0_u1_w1.c
+tmp_arm_loadstore_p1_u0_w0.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
+	./generate_arm_loadstore 1 0 0 > tmp_arm_loadstore_p1_u0_w0.c
+tmp_arm_loadstore_p1_u0_w1.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
+	./generate_arm_loadstore 1 0 1 > tmp_arm_loadstore_p1_u0_w1.c
+tmp_arm_loadstore_p1_u1_w0.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
+	./generate_arm_loadstore 1 1 0 > tmp_arm_loadstore_p1_u1_w0.c
+tmp_arm_loadstore_p1_u1_w1.c: cpu_arm_instr_loadstore.c generate_arm_loadstore
+	./generate_arm_loadstore 1 1 1 > tmp_arm_loadstore_p1_u1_w1.c
 
-tmp_arm_multi.cc: generate_arm_multi cpu_arm_multi.txt
-	./generate_arm_multi `cat cpu_arm_multi.txt` > tmp_arm_multi.cc
+tmp_arm_multi.c: generate_arm_multi cpu_arm_multi.txt
+	./generate_arm_multi `cat cpu_arm_multi.txt` > tmp_arm_multi.c
 
-tmp_arm_dpi.cc: cpu_arm_instr_dpi.cc generate_arm_dpi
-	./generate_arm_dpi > tmp_arm_dpi.cc
+tmp_arm_dpi.c: cpu_arm_instr_dpi.c generate_arm_dpi
+	./generate_arm_dpi > tmp_arm_dpi.c
 
-tmp_arm_r0.cc: generate_arm_r
-	./generate_arm_r 0x000 0x0ff > tmp_arm_r0.cc
-tmp_arm_r1.cc: generate_arm_r
-	./generate_arm_r 0x100 0x1ff > tmp_arm_r1.cc
-tmp_arm_r2.cc: generate_arm_r
-	./generate_arm_r 0x200 0x2ff > tmp_arm_r2.cc
-tmp_arm_r3.cc: generate_arm_r
-	./generate_arm_r 0x300 0x3ff > tmp_arm_r3.cc
-tmp_arm_r4.cc: generate_arm_r
-	./generate_arm_r 0x400 0x4ff > tmp_arm_r4.cc
-tmp_arm_r5.cc: generate_arm_r
-	./generate_arm_r 0x500 0x5ff > tmp_arm_r5.cc
-tmp_arm_r6.cc: generate_arm_r
-	./generate_arm_r 0x600 0x6ff > tmp_arm_r6.cc
-tmp_arm_r7.cc: generate_arm_r
-	./generate_arm_r 0x700 0x7ff > tmp_arm_r7.cc
-tmp_arm_r8.cc: generate_arm_r
-	./generate_arm_r 0x800 0x8ff > tmp_arm_r8.cc
-tmp_arm_r9.cc: generate_arm_r
-	./generate_arm_r 0x900 0x9ff > tmp_arm_r9.cc
-tmp_arm_ra.cc: generate_arm_r
-	./generate_arm_r 0xa00 0xaff > tmp_arm_ra.cc
-tmp_arm_rb.cc: generate_arm_r
-	./generate_arm_r 0xb00 0xbff > tmp_arm_rb.cc
-tmp_arm_rc.cc: generate_arm_r
-	./generate_arm_r 0xc00 0xcff > tmp_arm_rc.cc
-tmp_arm_rd.cc: generate_arm_r
-	./generate_arm_r 0xd00 0xdff > tmp_arm_rd.cc
-tmp_arm_re.cc: generate_arm_r
-	./generate_arm_r 0xe00 0xeff > tmp_arm_re.cc
-tmp_arm_rf.cc: generate_arm_r
-	./generate_arm_r 0xf00 0xfff > tmp_arm_rf.cc
+tmp_arm_r0.c: generate_arm_r
+	./generate_arm_r 0x000 0x0ff > tmp_arm_r0.c
+tmp_arm_r1.c: generate_arm_r
+	./generate_arm_r 0x100 0x1ff > tmp_arm_r1.c
+tmp_arm_r2.c: generate_arm_r
+	./generate_arm_r 0x200 0x2ff > tmp_arm_r2.c
+tmp_arm_r3.c: generate_arm_r
+	./generate_arm_r 0x300 0x3ff > tmp_arm_r3.c
+tmp_arm_r4.c: generate_arm_r
+	./generate_arm_r 0x400 0x4ff > tmp_arm_r4.c
+tmp_arm_r5.c: generate_arm_r
+	./generate_arm_r 0x500 0x5ff > tmp_arm_r5.c
+tmp_arm_r6.c: generate_arm_r
+	./generate_arm_r 0x600 0x6ff > tmp_arm_r6.c
+tmp_arm_r7.c: generate_arm_r
+	./generate_arm_r 0x700 0x7ff > tmp_arm_r7.c
+tmp_arm_r8.c: generate_arm_r
+	./generate_arm_r 0x800 0x8ff > tmp_arm_r8.c
+tmp_arm_r9.c: generate_arm_r
+	./generate_arm_r 0x900 0x9ff > tmp_arm_r9.c
+tmp_arm_ra.c: generate_arm_r
+	./generate_arm_r 0xa00 0xaff > tmp_arm_ra.c
+tmp_arm_rb.c: generate_arm_r
+	./generate_arm_r 0xb00 0xbff > tmp_arm_rb.c
+tmp_arm_rc.c: generate_arm_r
+	./generate_arm_r 0xc00 0xcff > tmp_arm_rc.c
+tmp_arm_rd.c: generate_arm_r
+	./generate_arm_r 0xd00 0xdff > tmp_arm_rd.c
+tmp_arm_re.c: generate_arm_r
+	./generate_arm_r 0xe00 0xeff > tmp_arm_re.c
+tmp_arm_rf.c: generate_arm_r
+	./generate_arm_r 0xf00 0xfff > tmp_arm_rf.c
 
-tmp_arm_r.cc: generate_arm_r
-	./generate_arm_r 0 0 > tmp_arm_r.cc
+tmp_arm_r.c: generate_arm_r
+	./generate_arm_r 0 0 > tmp_arm_r.c
 
-tmp_arm_head.cc: generate_head
-	./generate_head arm ARM > tmp_arm_head.cc
+tmp_arm_head.c: generate_head
+	./generate_head arm ARM > tmp_arm_head.c
 
-tmp_arm_tail.cc: generate_tail
-	./generate_tail arm ARM > tmp_arm_tail.cc
+tmp_arm_tail.c: generate_tail
+	./generate_tail arm ARM > tmp_arm_tail.c
 
 
 ###############################################################################
 
-cpu_m88k.o: cpu_m88k.cc cpu_m88k_instr.cc cpu_dyntrans.cc memory_rw.cc \
-	tmp_m88k_loadstore.cc tmp_m88k_head.cc tmp_m88k_tail.cc tmp_m88k_bcnd.cc
+cpu_i960.o: cpu_i960.c cpu_i960_instr.c cpu_dyntrans.c memory_rw.c \
+	tmp_i960_head.c tmp_i960_tail.c
 
-tmp_m88k_bcnd.cc: generate_m88k_bcnd
-	./generate_m88k_bcnd > tmp_m88k_bcnd.cc
+tmp_i960_head.c: generate_head
+	./generate_head i960 I960 > tmp_i960_head.c
 
-tmp_m88k_loadstore.cc: cpu_m88k_instr_loadstore.cc generate_m88k_loadstore
-	./generate_m88k_loadstore > tmp_m88k_loadstore.cc
+tmp_i960_tail.c: generate_tail
+	./generate_tail i960 I960 > tmp_i960_tail.c
 
-tmp_m88k_head.cc: generate_head
-	./generate_head m88k M88K > tmp_m88k_head.cc
 
-tmp_m88k_tail.cc: generate_tail
-	./generate_tail m88k M88K > tmp_m88k_tail.cc
+###############################################################################
+
+cpu_m88k.o: cpu_m88k.c cpu_m88k_instr.c cpu_dyntrans.c memory_rw.c \
+	tmp_m88k_loadstore.c tmp_m88k_head.c tmp_m88k_tail.c tmp_m88k_bcnd.c
+
+tmp_m88k_bcnd.c: generate_m88k_bcnd
+	./generate_m88k_bcnd > tmp_m88k_bcnd.c
+
+tmp_m88k_loadstore.c: cpu_m88k_instr_loadstore.c generate_m88k_loadstore
+	./generate_m88k_loadstore > tmp_m88k_loadstore.c
+
+tmp_m88k_head.c: generate_head
+	./generate_head m88k M88K > tmp_m88k_head.c
+
+tmp_m88k_tail.c: generate_tail
+	./generate_tail m88k M88K > tmp_m88k_tail.c
 
 
 ###############################################################################
 
-cpu_mips.o: cpu_mips.cc cpu_dyntrans.cc memory_mips.cc \
-	cpu_mips_instr.cc tmp_mips_loadstore.cc tmp_mips_loadstore_multi.cc \
-	tmp_mips_head.cc tmp_mips_tail.cc
+cpu_mips.o: cpu_mips.c cpu_dyntrans.c memory_mips.c \
+	cpu_mips_instr.c tmp_mips_loadstore.c tmp_mips_loadstore_multi.c \
+	tmp_mips_head.c tmp_mips_tail.c
 
-memory_mips.cc: memory_rw.cc memory_mips_v2p.cc
+memory_mips.c: memory_rw.c memory_mips_v2p.c
 
-tmp_mips_loadstore.cc: cpu_mips_instr_loadstore.cc generate_mips_loadstore
-	./generate_mips_loadstore > tmp_mips_loadstore.cc
+tmp_mips_loadstore.c: cpu_mips_instr_loadstore.c generate_mips_loadstore
+	./generate_mips_loadstore > tmp_mips_loadstore.c
 
-tmp_mips_loadstore_multi.cc: generate_mips_loadstore_multi
-	./generate_mips_loadstore_multi > tmp_mips_loadstore_multi.cc
+tmp_mips_loadstore_multi.c: generate_mips_loadstore_multi
+	./generate_mips_loadstore_multi > tmp_mips_loadstore_multi.c
 
-tmp_mips_head.cc: generate_head
-	./generate_head mips MIPS > tmp_mips_head.cc
+tmp_mips_head.c: generate_head
+	./generate_head mips MIPS > tmp_mips_head.c
 
-tmp_mips_tail.cc: generate_tail
-	./generate_tail mips MIPS > tmp_mips_tail.cc
+tmp_mips_tail.c: generate_tail
+	./generate_tail mips MIPS > tmp_mips_tail.c
 
 
 ###############################################################################
 
-cpu_ppc.o: cpu_ppc.cc cpu_ppc_instr.cc cpu_dyntrans.cc memory_ppc.cc \
-	memory_rw.cc tmp_ppc_head.cc tmp_ppc_tail.cc tmp_ppc_loadstore.cc
+cpu_ppc.o: cpu_ppc.c cpu_ppc_instr.c cpu_dyntrans.c memory_ppc.c \
+	memory_rw.c tmp_ppc_head.c tmp_ppc_tail.c tmp_ppc_loadstore.c
+
+tmp_ppc_loadstore.c: cpu_ppc_instr_loadstore.c generate_ppc_loadstore
+	./generate_ppc_loadstore > tmp_ppc_loadstore.c
+
+tmp_ppc_head.c: generate_head
+	./generate_head ppc PPC > tmp_ppc_head.c
+
+tmp_ppc_tail.c: generate_tail
+	./generate_tail ppc PPC > tmp_ppc_tail.c
+
+
+###############################################################################
 
-tmp_ppc_loadstore.cc: cpu_ppc_instr_loadstore.cc generate_ppc_loadstore
-	./generate_ppc_loadstore > tmp_ppc_loadstore.cc
+cpu_riscv.o: cpu_riscv.c cpu_riscv_instr.c cpu_dyntrans.c memory_rw.c \
+	tmp_riscv_head.c tmp_riscv_tail.c
 
-tmp_ppc_head.cc: generate_head
-	./generate_head ppc PPC > tmp_ppc_head.cc
+tmp_riscv_head.c: generate_head
+	./generate_head riscv RISCV > tmp_riscv_head.c
 
-tmp_ppc_tail.cc: generate_tail
-	./generate_tail ppc PPC > tmp_ppc_tail.cc
+tmp_riscv_tail.c: generate_tail
+	./generate_tail riscv RISCV > tmp_riscv_tail.c
 
 
 ###############################################################################
 
-cpu_sh.o: cpu_sh.cc cpu_sh_instr.cc cpu_dyntrans.cc memory_rw.cc \
-	tmp_sh_head.cc tmp_sh_tail.cc
+cpu_sh.o: cpu_sh.c cpu_sh_instr.c cpu_dyntrans.c memory_rw.c \
+	tmp_sh_head.c tmp_sh_tail.c
 
-tmp_sh_head.cc: generate_head
-	./generate_head sh SH > tmp_sh_head.cc
+tmp_sh_head.c: generate_head
+	./generate_head sh SH > tmp_sh_head.c
 
-tmp_sh_tail.cc: generate_tail
-	./generate_tail sh SH > tmp_sh_tail.cc
+tmp_sh_tail.c: generate_tail
+	./generate_tail sh SH > tmp_sh_tail.c
 
 
 ###############################################################################
diff -Nru gxemul-0.6.2/src/cpus/memory_alpha.c gxemul-0.7.0+dfsg/src/cpus/memory_alpha.c
--- gxemul-0.6.2/src/cpus/memory_alpha.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_alpha.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,180 @@
+/*
+ *  Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/alpha_rpb.h"
+
+
+/*
+ *  alpha_translate_v2p():
+ */
+int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr,
+	uint64_t *return_paddr, int flags)
+{
+	uint64_t base = cpu->cd.alpha.pcb.apcb_ptbr << ALPHA_PAGESHIFT;
+	uint64_t userMode = cpu->cd.alpha.ps & ALPHA_PSL_USERMODE;
+	// uint64_t vptptr = cpu->cd.alpha.vptptr;
+	
+	// TODO: From the Alpha "arm_book.book":
+	// IF {SEXT(VA<63:VA_SIZE>) NEQ SEXT(VA<VA_SIZE-1>} THEN
+	// 	{initiate Access Violation fault}
+	// IF (VIRBND in use) THEN
+	//   IF (VA LTU VIRBND) THEN
+	//     ptbr_value <- PTBR
+	//   ELSE
+	//     ptbr_value <- SYSPTBR
+	// ELSE
+	//   ptbr_value <- PTBR
+
+	/*  Kernel direct-mapped space (OSF/1, NetBSD):  */
+	if (!userMode && (vaddr >= ALPHA_K0SEG_BASE && vaddr <= ALPHA_K0SEG_END)) {
+		*return_paddr = vaddr & 0x000003ffffffffffULL;
+		return 2;
+	}
+
+	/*
+	 *  UGLY hack for now:
+	 *
+	 *  Before virtual memory has been set up, ptbr is most likely zero.
+	 *  In that case, simply map everything vaddr == paddr.
+	 */
+	if (!userMode && base == 0) {
+		*return_paddr = vaddr & 0x000003ffffffffffULL;
+if (vaddr == 0xfffffffd80000000ULL) {
+	fatal("Alpha kernel virtual memory seems to want to be used. Not yet implemented.\n");
+	exit(1);
+}
+#if 1
+		if ((vaddr & ~0x7fff) == 0x0000000010000000ULL)
+			*return_paddr = (vaddr & 0x7fff) + HWRPB_PADDR;
+
+		if ((vaddr & ~0xffffff) == 0xfffffe0000000000ULL)
+			*return_paddr = 0x7efa000 + (vaddr & 0xffffff);
+
+		/*  At 0x20000000, NetBSD stores 8KB temp prom data  */
+		if ((vaddr & ~0x1fff) == 0x0000000020000000ULL)
+			*return_paddr = (vaddr & 0x1fff) + PROM_ARGSPACE_PADDR;
+#endif
+		return 2;
+	}
+
+	// debug("base = 0x%016"PRIx64"\n", base);
+if (vaddr == 0xfffffffd80000000ULL) fatal("AYONA3\n");
+
+	uint64_t addr, pte1, pte2, pte3;
+	int i1, i2, i3;
+	unsigned char *pt_entry_ptr;
+	const int pageSizeShift = 13;
+	// const int pageSize = 1 << pageSizeShift;
+	const int bitsPerLevel = 10;
+	const int maskPerLevel = (1 << bitsPerLevel) - 1;
+
+	i1 = (vaddr >> (pageSizeShift + 2 * bitsPerLevel)) & maskPerLevel;
+	i2 = (vaddr >> (pageSizeShift + 1 * bitsPerLevel)) & maskPerLevel;
+	i3 = (vaddr >> (pageSizeShift + 0 * bitsPerLevel)) & maskPerLevel;
+
+	// debug("vaddr=%016llx i1=0x%x i2=0x%x i3=0x%x\n", (long long)vaddr, i1, i2, i3);
+
+	addr = base + i1 * sizeof(uint64_t);
+	
+	pt_entry_ptr = memory_paddr_to_hostaddr(cpu->mem, addr, 0);
+	if (pt_entry_ptr == NULL)
+		goto not_found;
+
+	pte1 = *(uint64_t *)(pt_entry_ptr);
+	pte1 = LE64_TO_HOST(pte1);
+
+	// debug("pte1 = 0x%016"PRIx64"\n", pte1);
+	if (!(pte1 & ALPHA_PTE_VALID)) {
+		// TODO:
+		// IF level1_pte<KRE> EQ 0 THEN
+		//   {initiate Access Violation fault}
+		// ELSE
+		//   {initiate Translation Not Valid fault}
+
+		// fatal("TODO: pte1 not valid.\n");
+		goto not_found;
+	}
+
+	addr = ((pte1 >> 32) << ALPHA_PAGESHIFT) + (i2 * sizeof(uint64_t));
+
+	pt_entry_ptr = memory_paddr_to_hostaddr(cpu->mem, addr, 0);
+	if (pt_entry_ptr == NULL)
+		goto not_found;
+
+	pte2 = *(uint64_t *)(pt_entry_ptr);
+	pte2 = LE64_TO_HOST(pte2);
+
+	// debug("pte2 = 0x%016"PRIx64"\n", pte2);
+	if (!(pte2 & ALPHA_PTE_VALID)) {
+		// TODO:
+		// IF level2_pte<KRE> EQ 0 THEN
+		//   {initiate Access Violation fault}
+		// ELSE
+		//   {initiate Translation Not Valid fault}
+
+		fatal("TODO: pte2 not valid.\n");
+		goto not_found;
+	}
+
+	addr = ((pte2 >> 32) << ALPHA_PAGESHIFT) + (i3 * sizeof(uint64_t));
+
+	pt_entry_ptr = memory_paddr_to_hostaddr(cpu->mem, addr, 0);
+	if (pt_entry_ptr == NULL)
+		goto not_found;
+
+	pte3 = *(uint64_t *)(pt_entry_ptr);
+	pte3 = LE64_TO_HOST(pte3);
+
+	// debug("pte3 = 0x%016"PRIx64"\n", pte3);
+
+	if (!(pte3 & ALPHA_PTE_VALID)) {
+		fatal("TODO: pte3 not valid.\n");
+		goto not_found;
+	}
+
+	(*return_paddr) = ALPHA_PTE_TO_PFN(pte3) << pageSizeShift;
+
+	// TODO.
+	return 2;
+
+not_found:
+	/*  No match.  */
+	fatal("[ alpha_translate_v2p: 0x%016" PRIx64" wasn't found ]\n", vaddr);
+abort();
+	exit(1);
+	return 0;
+}
+
diff -Nru gxemul-0.6.2/src/cpus/memory_alpha.cc gxemul-0.7.0+dfsg/src/cpus/memory_alpha.cc
--- gxemul-0.6.2/src/cpus/memory_alpha.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_alpha.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,180 +0,0 @@
-/*
- *  Copyright (C) 2006-2011  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/alpha_rpb.h"
-
-
-/*
- *  alpha_translate_v2p():
- */
-int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr,
-	uint64_t *return_paddr, int flags)
-{
-	uint64_t base = cpu->cd.alpha.pcb.apcb_ptbr << ALPHA_PAGESHIFT;
-	bool userMode = cpu->cd.alpha.ps & ALPHA_PSL_USERMODE;
-	// uint64_t vptptr = cpu->cd.alpha.vptptr;
-	
-	// TODO: From the Alpha "arm_book.book":
-	// IF {SEXT(VA<63:VA_SIZE>) NEQ SEXT(VA<VA_SIZE-1>} THEN
-	// 	{initiate Access Violation fault}
-	// IF (VIRBND in use) THEN
-	//   IF (VA LTU VIRBND) THEN
-	//     ptbr_value <- PTBR
-	//   ELSE
-	//     ptbr_value <- SYSPTBR
-	// ELSE
-	//   ptbr_value <- PTBR
-
-	/*  Kernel direct-mapped space (OSF/1, NetBSD):  */
-	if (!userMode && (vaddr >= ALPHA_K0SEG_BASE && vaddr <= ALPHA_K0SEG_END)) {
-		*return_paddr = vaddr & 0x000003ffffffffffULL;
-		return 2;
-	}
-
-	/*
-	 *  UGLY hack for now:
-	 *
-	 *  Before virtual memory has been set up, ptbr is most likely zero.
-	 *  In that case, simply map everything vaddr == paddr.
-	 */
-	if (!userMode && base == 0) {
-		*return_paddr = vaddr & 0x000003ffffffffffULL;
-if (vaddr == 0xfffffffd80000000ULL) {
-	fatal("Alpha kernel virtual memory seems to want to be used. Not yet implemented.\n");
-	exit(1);
-}
-#if 1
-		if ((vaddr & ~0x7fff) == 0x0000000010000000ULL)
-			*return_paddr = (vaddr & 0x7fff) + HWRPB_PADDR;
-
-		if ((vaddr & ~0xffffff) == 0xfffffe0000000000ULL)
-			*return_paddr = 0x7efa000 + (vaddr & 0xffffff);
-
-		/*  At 0x20000000, NetBSD stores 8KB temp prom data  */
-		if ((vaddr & ~0x1fff) == 0x0000000020000000ULL)
-			*return_paddr = (vaddr & 0x1fff) + PROM_ARGSPACE_PADDR;
-#endif
-		return 2;
-	}
-
-	// debug("base = 0x%016"PRIx64"\n", base);
-if (vaddr == 0xfffffffd80000000ULL) fatal("AYONA3\n");
-
-	uint64_t addr, pte1, pte2, pte3;
-	int i1, i2, i3;
-	unsigned char *pt_entry_ptr;
-	const int pageSizeShift = 13;
-	// const int pageSize = 1 << pageSizeShift;
-	const int bitsPerLevel = 10;
-	const int maskPerLevel = (1 << bitsPerLevel) - 1;
-
-	i1 = (vaddr >> (pageSizeShift + 2 * bitsPerLevel)) & maskPerLevel;
-	i2 = (vaddr >> (pageSizeShift + 1 * bitsPerLevel)) & maskPerLevel;
-	i3 = (vaddr >> (pageSizeShift + 0 * bitsPerLevel)) & maskPerLevel;
-
-	// debug("vaddr=%016llx i1=0x%x i2=0x%x i3=0x%x\n", (long long)vaddr, i1, i2, i3);
-
-	addr = base + i1 * sizeof(uint64_t);
-	
-	pt_entry_ptr = memory_paddr_to_hostaddr(cpu->mem, addr, 0);
-	if (pt_entry_ptr == NULL)
-		goto not_found;
-
-	pte1 = *(uint64_t *)(pt_entry_ptr);
-	pte1 = LE64_TO_HOST(pte1);
-
-	// debug("pte1 = 0x%016"PRIx64"\n", pte1);
-	if (!(pte1 & ALPHA_PTE_VALID)) {
-		// TODO:
-		// IF level1_pte<KRE> EQ 0 THEN
-		//   {initiate Access Violation fault}
-		// ELSE
-		//   {initiate Translation Not Valid fault}
-
-		// fatal("TODO: pte1 not valid.\n");
-		goto not_found;
-	}
-
-	addr = ((pte1 >> 32) << ALPHA_PAGESHIFT) + (i2 * sizeof(uint64_t));
-
-	pt_entry_ptr = memory_paddr_to_hostaddr(cpu->mem, addr, 0);
-	if (pt_entry_ptr == NULL)
-		goto not_found;
-
-	pte2 = *(uint64_t *)(pt_entry_ptr);
-	pte2 = LE64_TO_HOST(pte2);
-
-	// debug("pte2 = 0x%016"PRIx64"\n", pte2);
-	if (!(pte2 & ALPHA_PTE_VALID)) {
-		// TODO:
-		// IF level2_pte<KRE> EQ 0 THEN
-		//   {initiate Access Violation fault}
-		// ELSE
-		//   {initiate Translation Not Valid fault}
-
-		fatal("TODO: pte2 not valid.\n");
-		goto not_found;
-	}
-
-	addr = ((pte2 >> 32) << ALPHA_PAGESHIFT) + (i3 * sizeof(uint64_t));
-
-	pt_entry_ptr = memory_paddr_to_hostaddr(cpu->mem, addr, 0);
-	if (pt_entry_ptr == NULL)
-		goto not_found;
-
-	pte3 = *(uint64_t *)(pt_entry_ptr);
-	pte3 = LE64_TO_HOST(pte3);
-
-	// debug("pte3 = 0x%016"PRIx64"\n", pte3);
-
-	if (!(pte3 & ALPHA_PTE_VALID)) {
-		fatal("TODO: pte3 not valid.\n");
-		goto not_found;
-	}
-
-	(*return_paddr) = ALPHA_PTE_TO_PFN(pte3) << pageSizeShift;
-
-	// TODO.
-	return 2;
-
-not_found:
-	/*  No match.  */
-	fatal("[ alpha_translate_v2p: 0x%016" PRIx64" wasn't found ]\n", vaddr);
-abort();
-	exit(1);
-	return 0;
-}
-
diff -Nru gxemul-0.6.2/src/cpus/memory_arm.c gxemul-0.7.0+dfsg/src/cpus/memory_arm.c
--- gxemul-0.6.2/src/cpus/memory_arm.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_arm.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,276 @@
+/*
+ *  Copyright (C) 2005-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  TODO/NOTE:  The B and/or C bits could also cause the return value to
+ *  be MEMORY_NOT_FULL_PAGE, to make sure it doesn't get entered into the
+ *  translation arrays. TODO: Find out if this is a good thing to do.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "arm_cpu_types.h"
+#include "cpu.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/armreg.h"
+
+
+extern int quiet_mode;
+
+
+/*
+ *  arm_translate_v2p():
+ *
+ *  Address translation with the MMU disabled. (Just treat the virtual address
+ *  as a physical address.)
+ */
+int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr64,
+	uint64_t *return_paddr, int flags)
+{
+	*return_paddr = vaddr64 & 0xffffffff;
+
+	return 2;
+}
+
+
+/*
+ *  arm_check_access():
+ *
+ *  Helper function.  Returns 0 for no access, 1 for read-only, and 2 for
+ *  read/write.
+ */
+static int arm_check_access(struct cpu *cpu, int ap, int dav, int user)
+{
+	int s, r;
+
+	switch (dav) {
+	case 0:	/*  No access at all.  */
+		return 0;
+	case 1:	/*  Normal access check.  */
+		break;
+	case 2:	fatal("arm_check_access(): 1 shouldn't be used\n");
+		exit(1);
+	case 3:	/*  Anything is allowed.  */
+		return 2;
+	}
+
+	switch (ap) {
+	case 0:	s = (cpu->cd.arm.control & ARM_CONTROL_S)? 1 : 0;
+		r = (cpu->cd.arm.control & ARM_CONTROL_R)? 2 : 0;
+		switch (s + r) {
+		case 0:	return 0;
+		case 1:	return user? 0 : 1;
+		case 2:	return 1;
+		}
+		fatal("arm_check_access: UNPREDICTABLE s+r value!\n");
+		return 0;
+	case 1:	return user? 0 : 2;
+	case 2:	return user? 1 : 2;
+	}
+
+	/*  "case 3":  */
+	return 2;
+}
+
+
+/*
+ *  arm_translate_v2p_mmu():
+ *
+ *  Return values:
+ *	0  Failure
+ *	1  Success, the page is readable only
+ *	2  Success, the page is read/write
+ *
+ *  If this is a 1KB page access, then the return value is ORed with
+ *  MEMORY_NOT_FULL_PAGE.
+ */
+int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr64,
+	uint64_t *return_paddr, int flags)
+{
+	unsigned char *q;
+	uint32_t addr, d=0, d2 = (uint32_t)(int32_t)-1, ptba, vaddr = vaddr64;
+	int instr = flags & FLAG_INSTR;
+	int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0;
+	int useraccess = flags & MEMORY_USER_ACCESS;
+	int no_exceptions = flags & FLAG_NOEXCEPTIONS;
+	int user = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32;
+	int domain, dav, ap0,ap1,ap2,ap3, ap = 0, access = 0;
+	int fs = 2;		/*  fault status (2 = terminal exception)  */
+	int subpage = 0;
+
+	if (useraccess)
+		user = 1;
+
+	addr = ((vaddr & 0xfff00000ULL) >> 18);
+
+	if (cpu->cd.arm.translation_table == NULL ||
+	    cpu->cd.arm.ttb != cpu->cd.arm.last_ttb) {
+		cpu->cd.arm.translation_table = memory_paddr_to_hostaddr(
+		    cpu->mem, cpu->cd.arm.ttb & 0x0fffffff, 0);
+		cpu->cd.arm.last_ttb = cpu->cd.arm.ttb;
+	}
+
+	if (cpu->cd.arm.translation_table != NULL) {
+		d = *(uint32_t *)(cpu->cd.arm.translation_table + addr);
+#ifdef HOST_LITTLE_ENDIAN
+		if (cpu->byte_order == EMUL_BIG_ENDIAN)
+#else
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+#endif
+			d = ((d & 0xff) << 24) | ((d & 0xff00) << 8) |
+			    ((d & 0xff0000) >> 8) | ((d & 0xff000000) >> 24);
+	}
+
+	/*  Get the domain from the descriptor, and the Domain Access Value:  */
+	domain = (d >> 5) & 15;
+	dav = (cpu->cd.arm.dacr >> (domain * 2)) & 3;
+
+	switch (d & 3) {
+
+	case 0:	domain = 0;
+		fs = FAULT_TRANS_S;
+		goto exception_return;
+
+	case 1:	/*  Course Pagetable:  */
+		if (dav == 0) {
+			fs = FAULT_DOMAIN_P;
+			goto exception_return;
+		}
+		ptba = d & 0xfffffc00;
+		addr = ptba + ((vaddr & 0x000ff000) >> 10);
+
+		q = memory_paddr_to_hostaddr(cpu->mem, addr & 0x0fffffff, 0);
+		if (q == NULL) {
+			printf("arm memory blah blah adfh asfg asdgasdg\n");
+			exit(1);
+		}
+		d2 = *(uint32_t *)(q);
+#ifdef HOST_LITTLE_ENDIAN
+		if (cpu->byte_order == EMUL_BIG_ENDIAN)
+#else
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+#endif
+			d2 = ((d2 & 0xff) << 24) | ((d2 & 0xff00) << 8) |
+			     ((d2 & 0xff0000) >> 8) | ((d2 & 0xff000000) >> 24);
+
+		switch (d2 & 3) {
+		case 0:	fs = FAULT_TRANS_P;
+			goto exception_return;
+		case 1:	/*  16KB page:  */
+			ap = (d2 >> 4) & 255;
+			switch (vaddr & 0x0000c000) {
+			case 0x4000:	ap >>= 2; break;
+			case 0x8000:	ap >>= 4; break;
+			case 0xc000:	ap >>= 6; break;
+			}
+			ap &= 3;
+			*return_paddr = (d2 & 0xffff0000)|(vaddr & 0x0000ffff);
+			break;
+		case 3:	if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) {
+				/*  4KB page (Xscale)  */
+				subpage = 0;
+			} else {
+				/*  1KB page  */
+				subpage = 1;
+				ap = (d2 >> 4) & 3;
+				*return_paddr = (d2 & 0xfffffc00) |
+				    (vaddr & 0x000003ff);
+				break;
+			}
+			/*  NOTE: Fall-through for XScale!  */
+			// fall through
+		case 2:	/*  4KB page:  */
+			ap3 = (d2 >> 10) & 3;
+			ap2 = (d2 >>  8) & 3;
+			ap1 = (d2 >>  6) & 3;
+			ap0 = (d2 >>  4) & 3;
+			switch (vaddr & 0x00000c00) {
+			case 0x000: ap = ap0; break;
+			case 0x400: ap = ap1; break;
+			case 0x800: ap = ap2; break;
+			default:    ap = ap3;
+			}
+			/*  NOTE: Ugly hack for XScale:  */
+			if ((d2 & 3) == 3) {
+				/*  Treated as 4KB page:  */
+				ap = ap0;
+			} else {
+				if (ap0 != ap1 || ap0 != ap2 || ap0 != ap3)
+					subpage = 1;
+			}
+			*return_paddr = (d2 & 0xfffff000)|(vaddr & 0x00000fff);
+			break;
+		}
+		access = arm_check_access(cpu, ap, dav, user);
+		if (access > writeflag)
+			return access | (subpage? MEMORY_NOT_FULL_PAGE : 0);
+		fs = FAULT_PERM_P;
+		goto exception_return;
+
+	case 2:	/*  Section descriptor:  */
+		if (dav == 0) {
+			fs = FAULT_DOMAIN_S;
+			goto exception_return;
+		}
+		*return_paddr = (d & 0xfff00000) | (vaddr & 0x000fffff);
+		ap = (d >> 10) & 3;
+		access = arm_check_access(cpu, ap, dav, user);
+		if (access > writeflag)
+			return access;
+		fs = FAULT_PERM_S;
+		goto exception_return;
+
+	default:fatal("TODO: descriptor for vaddr 0x%08x: 0x%08x ("
+		    "unimplemented type %i)\n", vaddr, d, d&3);
+		exit(1);
+	}
+
+exception_return:
+	if (no_exceptions)
+		return 0;
+
+	if (!quiet_mode) {
+		fatal("{ arm memory fault: vaddr=0x%08x domain=%i dav=%i ap=%i "
+		    "access=%i user=%i", (int)vaddr, domain, dav, ap,
+		    access, user);
+		fatal(" d=0x%08x d2=0x%08x pc=0x%08x }\n", d, d2, (int)cpu->pc);
+	}
+
+	if (instr)
+		arm_exception(cpu, ARM_EXCEPTION_PREF_ABT);
+	else {
+		cpu->cd.arm.far = vaddr;
+		cpu->cd.arm.fsr = (domain << 4) | fs;
+		arm_exception(cpu, ARM_EXCEPTION_DATA_ABT);
+	}
+
+	return 0;
+}
+
diff -Nru gxemul-0.6.2/src/cpus/memory_arm.cc gxemul-0.7.0+dfsg/src/cpus/memory_arm.cc
--- gxemul-0.6.2/src/cpus/memory_arm.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_arm.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,275 +0,0 @@
-/*
- *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  TODO/NOTE:  The B and/or C bits could also cause the return value to
- *  be MEMORY_NOT_FULL_PAGE, to make sure it doesn't get entered into the
- *  translation arrays. TODO: Find out if this is a good thing to do.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "arm_cpu_types.h"
-#include "cpu.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/armreg.h"
-
-
-extern int quiet_mode;
-
-
-/*
- *  arm_translate_v2p():
- *
- *  Address translation with the MMU disabled. (Just treat the virtual address
- *  as a physical address.)
- */
-int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr64,
-	uint64_t *return_paddr, int flags)
-{
-	*return_paddr = vaddr64 & 0xffffffff;
-
-	return 2;
-}
-
-
-/*
- *  arm_check_access():
- *
- *  Helper function.  Returns 0 for no access, 1 for read-only, and 2 for
- *  read/write.
- */
-static int arm_check_access(struct cpu *cpu, int ap, int dav, int user)
-{
-	int s, r;
-
-	switch (dav) {
-	case 0:	/*  No access at all.  */
-		return 0;
-	case 1:	/*  Normal access check.  */
-		break;
-	case 2:	fatal("arm_check_access(): 1 shouldn't be used\n");
-		exit(1);
-	case 3:	/*  Anything is allowed.  */
-		return 2;
-	}
-
-	switch (ap) {
-	case 0:	s = (cpu->cd.arm.control & ARM_CONTROL_S)? 1 : 0;
-		r = (cpu->cd.arm.control & ARM_CONTROL_R)? 2 : 0;
-		switch (s + r) {
-		case 0:	return 0;
-		case 1:	return user? 0 : 1;
-		case 2:	return 1;
-		}
-		fatal("arm_check_access: UNPREDICTABLE s+r value!\n");
-		return 0;
-	case 1:	return user? 0 : 2;
-	case 2:	return user? 1 : 2;
-	}
-
-	/*  "case 3":  */
-	return 2;
-}
-
-
-/*
- *  arm_translate_v2p_mmu():
- *
- *  Return values:
- *	0  Failure
- *	1  Success, the page is readable only
- *	2  Success, the page is read/write
- *
- *  If this is a 1KB page access, then the return value is ORed with
- *  MEMORY_NOT_FULL_PAGE.
- */
-int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr64,
-	uint64_t *return_paddr, int flags)
-{
-	unsigned char *q;
-	uint32_t addr, d=0, d2 = (uint32_t)(int32_t)-1, ptba, vaddr = vaddr64;
-	int instr = flags & FLAG_INSTR;
-	int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0;
-	int useraccess = flags & MEMORY_USER_ACCESS;
-	int no_exceptions = flags & FLAG_NOEXCEPTIONS;
-	int user = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32;
-	int domain, dav, ap0,ap1,ap2,ap3, ap = 0, access = 0;
-	int fs = 2;		/*  fault status (2 = terminal exception)  */
-	int subpage = 0;
-
-	if (useraccess)
-		user = 1;
-
-	addr = ((vaddr & 0xfff00000ULL) >> 18);
-
-	if (cpu->cd.arm.translation_table == NULL ||
-	    cpu->cd.arm.ttb != cpu->cd.arm.last_ttb) {
-		cpu->cd.arm.translation_table = memory_paddr_to_hostaddr(
-		    cpu->mem, cpu->cd.arm.ttb & 0x0fffffff, 0);
-		cpu->cd.arm.last_ttb = cpu->cd.arm.ttb;
-	}
-
-	if (cpu->cd.arm.translation_table != NULL) {
-		d = *(uint32_t *)(cpu->cd.arm.translation_table + addr);
-#ifdef HOST_LITTLE_ENDIAN
-		if (cpu->byte_order == EMUL_BIG_ENDIAN)
-#else
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-#endif
-			d = ((d & 0xff) << 24) | ((d & 0xff00) << 8) |
-			    ((d & 0xff0000) >> 8) | ((d & 0xff000000) >> 24);
-	}
-
-	/*  Get the domain from the descriptor, and the Domain Access Value:  */
-	domain = (d >> 5) & 15;
-	dav = (cpu->cd.arm.dacr >> (domain * 2)) & 3;
-
-	switch (d & 3) {
-
-	case 0:	domain = 0;
-		fs = FAULT_TRANS_S;
-		goto exception_return;
-
-	case 1:	/*  Course Pagetable:  */
-		if (dav == 0) {
-			fs = FAULT_DOMAIN_P;
-			goto exception_return;
-		}
-		ptba = d & 0xfffffc00;
-		addr = ptba + ((vaddr & 0x000ff000) >> 10);
-
-		q = memory_paddr_to_hostaddr(cpu->mem, addr & 0x0fffffff, 0);
-		if (q == NULL) {
-			printf("arm memory blah blah adfh asfg asdgasdg\n");
-			exit(1);
-		}
-		d2 = *(uint32_t *)(q);
-#ifdef HOST_LITTLE_ENDIAN
-		if (cpu->byte_order == EMUL_BIG_ENDIAN)
-#else
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-#endif
-			d2 = ((d2 & 0xff) << 24) | ((d2 & 0xff00) << 8) |
-			     ((d2 & 0xff0000) >> 8) | ((d2 & 0xff000000) >> 24);
-
-		switch (d2 & 3) {
-		case 0:	fs = FAULT_TRANS_P;
-			goto exception_return;
-		case 1:	/*  16KB page:  */
-			ap = (d2 >> 4) & 255;
-			switch (vaddr & 0x0000c000) {
-			case 0x4000:	ap >>= 2; break;
-			case 0x8000:	ap >>= 4; break;
-			case 0xc000:	ap >>= 6; break;
-			}
-			ap &= 3;
-			*return_paddr = (d2 & 0xffff0000)|(vaddr & 0x0000ffff);
-			break;
-		case 3:	if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) {
-				/*  4KB page (Xscale)  */
-				subpage = 0;
-			} else {
-				/*  1KB page  */
-				subpage = 1;
-				ap = (d2 >> 4) & 3;
-				*return_paddr = (d2 & 0xfffffc00) |
-				    (vaddr & 0x000003ff);
-				break;
-			}
-			/*  NOTE: Fall-through for XScale!  */
-		case 2:	/*  4KB page:  */
-			ap3 = (d2 >> 10) & 3;
-			ap2 = (d2 >>  8) & 3;
-			ap1 = (d2 >>  6) & 3;
-			ap0 = (d2 >>  4) & 3;
-			switch (vaddr & 0x00000c00) {
-			case 0x000: ap = ap0; break;
-			case 0x400: ap = ap1; break;
-			case 0x800: ap = ap2; break;
-			default:    ap = ap3;
-			}
-			/*  NOTE: Ugly hack for XScale:  */
-			if ((d2 & 3) == 3) {
-				/*  Treated as 4KB page:  */
-				ap = ap0;
-			} else {
-				if (ap0 != ap1 || ap0 != ap2 || ap0 != ap3)
-					subpage = 1;
-			}
-			*return_paddr = (d2 & 0xfffff000)|(vaddr & 0x00000fff);
-			break;
-		}
-		access = arm_check_access(cpu, ap, dav, user);
-		if (access > writeflag)
-			return access | (subpage? MEMORY_NOT_FULL_PAGE : 0);
-		fs = FAULT_PERM_P;
-		goto exception_return;
-
-	case 2:	/*  Section descriptor:  */
-		if (dav == 0) {
-			fs = FAULT_DOMAIN_S;
-			goto exception_return;
-		}
-		*return_paddr = (d & 0xfff00000) | (vaddr & 0x000fffff);
-		ap = (d >> 10) & 3;
-		access = arm_check_access(cpu, ap, dav, user);
-		if (access > writeflag)
-			return access;
-		fs = FAULT_PERM_S;
-		goto exception_return;
-
-	default:fatal("TODO: descriptor for vaddr 0x%08x: 0x%08x ("
-		    "unimplemented type %i)\n", vaddr, d, d&3);
-		exit(1);
-	}
-
-exception_return:
-	if (no_exceptions)
-		return 0;
-
-	if (!quiet_mode) {
-		fatal("{ arm memory fault: vaddr=0x%08x domain=%i dav=%i ap=%i "
-		    "access=%i user=%i", (int)vaddr, domain, dav, ap,
-		    access, user);
-		fatal(" d=0x%08x d2=0x%08x pc=0x%08x }\n", d, d2, (int)cpu->pc);
-	}
-
-	if (instr)
-		arm_exception(cpu, ARM_EXCEPTION_PREF_ABT);
-	else {
-		cpu->cd.arm.far = vaddr;
-		cpu->cd.arm.fsr = (domain << 4) | fs;
-		arm_exception(cpu, ARM_EXCEPTION_DATA_ABT);
-	}
-
-	return 0;
-}
-
diff -Nru gxemul-0.6.2/src/cpus/memory_m88k.c gxemul-0.7.0+dfsg/src/cpus/memory_m88k.c
--- gxemul-0.6.2/src/cpus/memory_m88k.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_m88k.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,421 @@
+/*
+ *  Copyright (C) 2007-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Virtual to physical memory translation for M88K emulation.
+ *
+ *  (This is where the actual work of the M8820x chips is emulated.)
+ *
+ *
+ *  TODO:
+ *	M88204 stuff, where it differs from the M88200.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/m8820x.h"
+#include "thirdparty/m8820x_pte.h"
+
+
+/*  #define M8820X_TABLE_SEARCH_DEBUG  */
+
+
+/*
+ *  m8820x_mark_page_as_modified():
+ *
+ *  Helper function which traverses the page table structure in emulated
+ *  memory, and marks a page as Modified and Used.
+ */
+void m8820x_mark_page_as_modified(struct cpu *cpu,
+	struct m8820x_cmmu *cmmu, uint32_t apr, uint32_t vaddr)
+{
+	int seg_nr = vaddr >> 22, page_nr = (vaddr >> 12) & 0x3ff;
+	uint32_t *seg_base, *page_base;
+	sdt_entry_t seg_descriptor;
+	pt_entry_t page_descriptor;
+
+	/*  Read the segment descriptor from memory:  */
+	seg_base = (uint32_t *) memory_paddr_to_hostaddr(
+	    cpu->mem, apr & 0xfffff000, 1);
+	seg_descriptor = seg_base[seg_nr];
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		seg_descriptor = LE32_TO_HOST(seg_descriptor);
+	else
+		seg_descriptor = BE32_TO_HOST(seg_descriptor);
+
+	/*  ... and the page descriptor:  */
+	page_base = (uint32_t *) memory_paddr_to_hostaddr(
+	    cpu->mem, seg_descriptor & 0xfffff000, 1);
+	page_descriptor = page_base[page_nr];
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		page_descriptor = LE32_TO_HOST(page_descriptor);
+	else
+		page_descriptor = BE32_TO_HOST(page_descriptor);
+
+	/*  ... set the Modified and Used bits:  */
+	page_descriptor |= PG_M | PG_U;
+
+	/*  ... and write it back:  */
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		page_descriptor = LE32_TO_HOST(page_descriptor);
+	else
+		page_descriptor = BE32_TO_HOST(page_descriptor);
+	page_base[page_nr] = page_descriptor;
+}
+
+
+/*
+ *  m88k_translate_v2p():
+ *
+ *  Returns 0 for translation failure (access denied), 1 for read access
+ *  (success), or 2 for read/write access (success).
+ */
+int m88k_translate_v2p(struct cpu *cpu, uint64_t vaddr64,
+	uint64_t *return_paddr, int flags)
+{
+	int instr = flags & FLAG_INSTR;
+	int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0;
+	int no_exceptions = flags & FLAG_NOEXCEPTIONS;
+	int exception_type = instr? M88K_EXCEPTION_INSTRUCTION_ACCESS
+	    : M88K_EXCEPTION_DATA_ACCESS;
+	int supervisor = cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE;
+	struct m8820x_cmmu *cmmu = cpu->cd.m88k.cmmu[instr? 0 : 1];
+	uint32_t vaddr = vaddr64;
+	uint32_t apr;
+	uint32_t *seg_base, *page_base;
+	sdt_entry_t seg_descriptor;
+	pt_entry_t page_descriptor;
+	int pfsr_status = CMMU_PFSR_SUCCESS;
+	uint32_t pfar = 0;
+	int accumulated_flags;
+	int i, seg_nr = vaddr >> 22, page_nr = (vaddr >> 12) & 0x3ff;
+
+	if (flags & MEMORY_USER_ACCESS)
+		supervisor = 0;
+
+
+	/*
+	 *  Is the CMMU not yet initialized? Then return physical = virtual.
+	 */
+	*return_paddr = vaddr;
+	if (cmmu == NULL)
+		return 2;
+
+	if (supervisor)
+		apr = cmmu->reg[CMMU_SAPR];
+	else
+		apr = cmmu->reg[CMMU_UAPR];
+
+
+	/*
+	 *  Address translation not enabled? Then return physical = virtual.
+	 */
+	if (!(apr & APR_V))
+		return 2;
+
+	/*
+	 *  BATC lookup:
+	 *
+	 *  The BATC is a 10-entry array of virtual to physical mappings,
+	 *  where the top 13 bits of the virtual address must match.
+	 */
+	for (i=0; i<N_M88200_BATC_REGS; i++) {
+		uint32_t batc = cmmu->batc[i];
+
+		/*  The batc entry must be valid:  */
+		if (!(batc & BATC_V))
+			continue;
+
+		/*  ... and have a matching supervisor/user bit:  */
+		if ((supervisor && !(batc & BATC_SO)) ||
+		    (!supervisor && (batc & BATC_SO)))
+			continue;
+
+		/*  ... and matching virtual address:  */
+		if ((vaddr & 0xfff80000) != (batc & 0xfff80000))
+			continue;
+
+		/*  A matching BATC entry was found!  */
+
+		/*  Is it write protected?  */
+		if ((batc & BATC_PROT) && writeflag) {
+			pfsr_status = CMMU_PFSR_WRITE;
+			goto exception;
+		}
+
+		*return_paddr = ((batc & 0x0007ffc0) << 13)
+		    | (vaddr & 0x0007ffff);
+
+		return batc & BATC_PROT? 1 : 2;
+	}
+
+	/*
+	 *  PATC lookup:
+	 *
+	 *  The PATC is a 56-entry array of virtual to physical mappings for
+	 *  4 KB pages. If writeflag is set, and a PATC entry is found without
+	 *  the Modified bit set, a page table search must be performed to
+	 *  set the Modified bit in emulated memory.
+	 */
+	for (i=0; i<N_M88200_PATC_ENTRIES; i++) {
+		uint32_t vaddr_and_control = cmmu->patc_v_and_control[i];
+		uint32_t paddr_and_sbit = cmmu->patc_p_and_supervisorbit[i];
+
+		/*  Skip this entry if the valid bit isn't set:  */
+		if (!(vaddr_and_control & PG_V))
+			continue;
+
+		/*  ... or the virtual addresses don't match:  */
+		if ((vaddr & 0xfffff000) != (vaddr_and_control & 0xfffff000))
+			continue;
+
+		/*  ... or if the supervisor bit doesn't match:  */
+		if (((paddr_and_sbit & M8820X_PATC_SUPERVISOR_BIT)
+		    && !supervisor) || (supervisor &&
+		    !(paddr_and_sbit & M8820X_PATC_SUPERVISOR_BIT)))
+			continue;
+
+		/*  A matching PATC entry was found!  */
+
+		/*  Is it write protected?  */
+		if ((vaddr_and_control & PG_PROT) && writeflag) {
+			pfsr_status = CMMU_PFSR_WRITE;
+			goto exception;
+		}
+
+		/*  On writes: Is the page not yet marked as modified?  */
+		if (!(vaddr_and_control & PG_M) && writeflag &&
+		    !no_exceptions) {
+			/*  Then perform a page table search and mark
+			    it as Modified (and used):  */
+			m8820x_mark_page_as_modified(cpu, cmmu, apr, vaddr);
+
+			/*  ... and mark the PATC entry too:  */
+			cmmu->patc_v_and_control[i] |= PG_M;
+		}
+
+		/*  Set the Used bit of the PATC entry:  */
+		if (!no_exceptions)
+			cmmu->patc_v_and_control[i] |= PG_U;
+
+		/*  ... and finally return the physical address:  */
+		*return_paddr = (paddr_and_sbit & 0xfffff000) | (vaddr & 0xfff);
+		return vaddr_and_control & PG_PROT? 1 : 2;
+	}
+
+	/*
+	 *  The address was neither found in the BATC, nor the PATC.
+	 */
+
+	/*
+	 *  Attempt a search through page tables, to refill the PATC:
+	 */
+	seg_base = (uint32_t *) memory_paddr_to_hostaddr(
+	    cpu->mem, apr & 0xfffff000, 1);
+
+	seg_descriptor = seg_base[seg_nr];
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		seg_descriptor = LE32_TO_HOST(seg_descriptor);
+	else
+		seg_descriptor = BE32_TO_HOST(seg_descriptor);
+
+#ifdef M8820X_TABLE_SEARCH_DEBUG
+	printf("+---   M8820x page table search debug:\n");
+	printf("| vaddr     0x%08"PRIx32"\n", vaddr);
+	printf("| apr       0x%08"PRIx32"\n", apr);
+	printf("| seg_base  %p (on the host)\n", seg_base);
+	printf("| seg_nr    0x%03x\n", seg_nr);
+	printf("| page_nr   0x%03x\n", page_nr);
+	printf("| sd        0x%08"PRIx32"\n", seg_descriptor);
+#endif
+
+	/*  Segment descriptor invalid? Then cause a segfault exception.  */
+	if (!(seg_descriptor & SG_V)) {
+		/*  PFAR = physical address of faulting segment descriptor:  */
+		pfar = (apr & 0xfffff000) + seg_nr * sizeof(uint32_t);
+		pfsr_status = CMMU_PFSR_SFAULT;
+		goto exception;
+	}
+
+	/*  Usermode attempted to access a supervisor segment?  */
+	if ((seg_descriptor & SG_SO) && !supervisor) {
+		/*  PFAR = physical address of faulting segment descriptor:  */
+		pfar = (apr & 0xfffff000) + seg_nr * sizeof(uint32_t);
+		pfsr_status = CMMU_PFSR_SUPER;
+		goto exception;
+	}
+
+	accumulated_flags = seg_descriptor & SG_RO;
+
+	page_base = (uint32_t *) memory_paddr_to_hostaddr(
+	    cpu->mem, seg_descriptor & 0xfffff000, 1);
+
+	page_descriptor = page_base[page_nr];
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		page_descriptor = LE32_TO_HOST(page_descriptor);
+	else
+		page_descriptor = BE32_TO_HOST(page_descriptor);
+
+#ifdef M8820X_TABLE_SEARCH_DEBUG
+	printf("| page_base %p (on the host)\n", page_base);
+	printf("| pd        0x%08"PRIx32"\n", page_descriptor);
+#endif
+
+	/*  Page descriptor invalid? Then cause a page fault exception.  */
+	if (!(page_descriptor & PG_V)) {
+		/*  PFAR = physical address of faulting page descriptor:  */
+		pfar = (seg_descriptor & 0xfffff000)
+		    + page_nr * sizeof(uint32_t);
+		pfsr_status = CMMU_PFSR_PFAULT;
+		goto exception;
+	}
+
+	/*  Usermode attempted to access a supervisor page?  */
+	if ((page_descriptor & PG_SO) && !supervisor) {
+		/*  PFAR = physical address of faulting page descriptor:  */
+		pfar = (seg_descriptor & 0xfffff000)
+		    + page_nr * sizeof(uint32_t);
+		pfsr_status = CMMU_PFSR_SUPER;
+		goto exception;
+	}
+
+	accumulated_flags |= (page_descriptor & PG_RO);
+
+
+	/*
+	 *  Overwrite the next entry in the PATC with a new entry:
+	 */
+
+	if (!no_exceptions) {
+		i = cmmu->patc_update_index;
+
+		/*  Invalidate the current entry, if it is valid:  */
+		if (cmmu->patc_v_and_control[i] & PG_V)
+			cpu->invalidate_translation_caches(cpu,
+			    cmmu->patc_v_and_control[i] & 0xfffff000,
+			    INVALIDATE_VADDR);
+
+		/*  ... and write the new one:  */
+		cmmu->patc_update_index ++;
+		cmmu->patc_update_index %= N_M88200_PATC_ENTRIES;
+		cmmu->patc_v_and_control[i] =
+		    (vaddr & 0xfffff000) | accumulated_flags | PG_V;
+		cmmu->patc_p_and_supervisorbit[i] =
+		    (page_descriptor & 0xfffff000) |
+		    (supervisor? M8820X_PATC_SUPERVISOR_BIT : 0);
+	}
+
+	/*  Check for writes to read-only pages:  */
+	if (writeflag && (accumulated_flags & PG_RO)) {
+		pfsr_status = CMMU_PFSR_WRITE;
+		goto exception;
+	}
+
+	if (!no_exceptions) {
+		uint32_t tmp;
+
+		/*  We now know that the page is in use.  */
+		cmmu->patc_v_and_control[i] |= PG_U;
+		if (writeflag)
+			cmmu->patc_v_and_control[i] |= PG_M;
+
+		/*
+		 *  Write back the U bit (and possibly the M bit) to the page
+		 *  descriptor in emulated memory:
+		 */
+		tmp = page_descriptor | PG_U;
+		if (writeflag)
+			tmp |= PG_M;
+
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			tmp = LE32_TO_HOST(tmp);
+		else
+			tmp = BE32_TO_HOST(tmp);
+
+		page_base[page_nr] = tmp;
+	}
+
+	/*  Now finally return with the translated page address:  */
+	*return_paddr = (page_descriptor & 0xfffff000) | (vaddr & 0xfff);
+	return (accumulated_flags & PG_RO)? 1 : 2;
+
+
+exception:
+	if (no_exceptions)
+		return 0;
+
+	/*
+	 *  Update the Page Fault Status Register of the CMMU which this fault
+	 *  was associated with, but also clear the PFSR of the _other_ CMMU:
+	 */
+
+	cmmu->reg[CMMU_PFSR] = pfsr_status << 16;
+	cpu->cd.m88k.cmmu[instr? 1 : 0]->reg[CMMU_PFSR] =
+	    CMMU_PFSR_SUCCESS << 16;
+
+	/*  ... and (if necessary) update the Page Fault Address Register:  */
+
+	switch (pfsr_status) {
+
+	case CMMU_PFSR_SUCCESS:
+		debugmsg_cpu(cpu, SUBSYS_CPU, "m88k",
+		    VERBOSITY_ERROR,
+		    "HUH? CMMU_PFSR_SUCCESS:, but exception? TODO");
+		exit(1);
+		break;
+
+	case CMMU_PFSR_WRITE:
+		/*  Note: The PFAR is "destroyed"/undefined on write faults.  */
+		cmmu->reg[CMMU_PFAR] = 0;
+		break;
+
+	case CMMU_PFSR_SUPER:
+	case CMMU_PFSR_SFAULT:
+	case CMMU_PFSR_PFAULT:
+		cmmu->reg[CMMU_PFAR] = pfar;
+		break;
+
+	default:
+		debugmsg_cpu(cpu, SUBSYS_CPU, "m88k",
+		    VERBOSITY_ERROR,
+		    "Internal error in memory_m88k? pfsr_status = %i",
+		    pfsr_status);
+		exit(1);
+	}
+
+	/*  ... and finally cause the exception:  */
+	m88k_exception(cpu, exception_type, 0);
+
+	return 0;
+}
+
diff -Nru gxemul-0.6.2/src/cpus/memory_m88k.cc gxemul-0.7.0+dfsg/src/cpus/memory_m88k.cc
--- gxemul-0.6.2/src/cpus/memory_m88k.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_m88k.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,417 +0,0 @@
-/*
- *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Virtual to physical memory translation for M88K emulation.
- *
- *  (This is where the actual work of the M8820x chips is emulated.)
- *
- *
- *  TODO:
- *	M88204 stuff, where it differs from the M88200.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/m8820x.h"
-#include "thirdparty/m8820x_pte.h"
-
-
-/*  #define M8820X_TABLE_SEARCH_DEBUG  */
-
-
-/*
- *  m8820x_mark_page_as_modified():
- *
- *  Helper function which traverses the page table structure in emulated
- *  memory, and marks a page as Modified and Used.
- */
-void m8820x_mark_page_as_modified(struct cpu *cpu,
-	struct m8820x_cmmu *cmmu, uint32_t apr, uint32_t vaddr)
-{
-	int seg_nr = vaddr >> 22, page_nr = (vaddr >> 12) & 0x3ff;
-	uint32_t *seg_base, *page_base;
-	sdt_entry_t seg_descriptor;
-	pt_entry_t page_descriptor;
-
-	/*  Read the segment descriptor from memory:  */
-	seg_base = (uint32_t *) memory_paddr_to_hostaddr(
-	    cpu->mem, apr & 0xfffff000, 1);
-	seg_descriptor = seg_base[seg_nr];
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		seg_descriptor = LE32_TO_HOST(seg_descriptor);
-	else
-		seg_descriptor = BE32_TO_HOST(seg_descriptor);
-
-	/*  ... and the page descriptor:  */
-	page_base = (uint32_t *) memory_paddr_to_hostaddr(
-	    cpu->mem, seg_descriptor & 0xfffff000, 1);
-	page_descriptor = page_base[page_nr];
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		page_descriptor = LE32_TO_HOST(page_descriptor);
-	else
-		page_descriptor = BE32_TO_HOST(page_descriptor);
-
-	/*  ... set the Modified and Used bits:  */
-	page_descriptor |= PG_M | PG_U;
-
-	/*  ... and write it back:  */
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		page_descriptor = LE32_TO_HOST(page_descriptor);
-	else
-		page_descriptor = BE32_TO_HOST(page_descriptor);
-	page_base[page_nr] = page_descriptor;
-}
-
-
-/*
- *  m88k_translate_v2p():
- *
- *  Returns 0 for translation failure (access denied), 1 for read access
- *  (success), or 2 for read/write access (success).
- */
-int m88k_translate_v2p(struct cpu *cpu, uint64_t vaddr64,
-	uint64_t *return_paddr, int flags)
-{
-	int instr = flags & FLAG_INSTR;
-	int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0;
-	int no_exceptions = flags & FLAG_NOEXCEPTIONS;
-	int exception_type = instr? M88K_EXCEPTION_INSTRUCTION_ACCESS
-	    : M88K_EXCEPTION_DATA_ACCESS;
-	int supervisor = cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE;
-	struct m8820x_cmmu *cmmu = cpu->cd.m88k.cmmu[instr? 0 : 1];
-	uint32_t vaddr = vaddr64;
-	uint32_t apr;
-	uint32_t *seg_base, *page_base;
-	sdt_entry_t seg_descriptor;
-	pt_entry_t page_descriptor;
-	int pfsr_status = CMMU_PFSR_SUCCESS;
-	uint32_t pfar = 0;
-	int accumulated_flags;
-	int i, seg_nr = vaddr >> 22, page_nr = (vaddr >> 12) & 0x3ff;
-
-	if (flags & MEMORY_USER_ACCESS)
-		supervisor = 0;
-
-
-	/*
-	 *  Is the CMMU not yet initialized? Then return physical = virtual.
-	 */
-	*return_paddr = vaddr;
-	if (cmmu == NULL)
-		return 2;
-
-	if (supervisor)
-		apr = cmmu->reg[CMMU_SAPR];
-	else
-		apr = cmmu->reg[CMMU_UAPR];
-
-
-	/*
-	 *  Address translation not enabled? Then return physical = virtual.
-	 */
-	if (!(apr & APR_V))
-		return 2;
-
-	/*
-	 *  BATC lookup:
-	 *
-	 *  The BATC is a 10-entry array of virtual to physical mappings,
-	 *  where the top 13 bits of the virtual address must match.
-	 */
-	for (i=0; i<N_M88200_BATC_REGS; i++) {
-		uint32_t batc = cmmu->batc[i];
-
-		/*  The batc entry must be valid:  */
-		if (!(batc & BATC_V))
-			continue;
-
-		/*  ... and have a matching supervisor/user bit:  */
-		if ((supervisor && !(batc & BATC_SO)) ||
-		    (!supervisor && (batc & BATC_SO)))
-			continue;
-
-		/*  ... and matching virtual address:  */
-		if ((vaddr & 0xfff80000) != (batc & 0xfff80000))
-			continue;
-
-		/*  A matching BATC entry was found!  */
-
-		/*  Is it write protected?  */
-		if ((batc & BATC_PROT) && writeflag) {
-			pfsr_status = CMMU_PFSR_WRITE;
-			goto exception;
-		}
-
-		*return_paddr = ((batc & 0x0007ffc0) << 13)
-		    | (vaddr & 0x0007ffff);
-
-		return batc & BATC_PROT? 1 : 2;
-	}
-
-	/*
-	 *  PATC lookup:
-	 *
-	 *  The PATC is a 56-entry array of virtual to physical mappings for
-	 *  4 KB pages. If writeflag is set, and a PATC entry is found without
-	 *  the Modified bit set, a page table search must be performed to
-	 *  set the Modified bit in emulated memory.
-	 */
-	for (i=0; i<N_M88200_PATC_ENTRIES; i++) {
-		uint32_t vaddr_and_control = cmmu->patc_v_and_control[i];
-		uint32_t paddr_and_sbit = cmmu->patc_p_and_supervisorbit[i];
-
-		/*  Skip this entry if the valid bit isn't set:  */
-		if (!(vaddr_and_control & PG_V))
-			continue;
-
-		/*  ... or the virtual addresses don't match:  */
-		if ((vaddr & 0xfffff000) != (vaddr_and_control & 0xfffff000))
-			continue;
-
-		/*  ... or if the supervisor bit doesn't match:  */
-		if (((paddr_and_sbit & M8820X_PATC_SUPERVISOR_BIT)
-		    && !supervisor) || (supervisor &&
-		    !(paddr_and_sbit & M8820X_PATC_SUPERVISOR_BIT)))
-			continue;
-
-		/*  A matching PATC entry was found!  */
-
-		/*  Is it write protected?  */
-		if ((vaddr_and_control & PG_PROT) && writeflag) {
-			pfsr_status = CMMU_PFSR_WRITE;
-			goto exception;
-		}
-
-		/*  On writes: Is the page not yet marked as modified?  */
-		if (!(vaddr_and_control & PG_M) && writeflag &&
-		    !no_exceptions) {
-			/*  Then perform a page table search and mark
-			    it as Modified (and used):  */
-			m8820x_mark_page_as_modified(cpu, cmmu, apr, vaddr);
-
-			/*  ... and mark the PATC entry too:  */
-			cmmu->patc_v_and_control[i] |= PG_M;
-		}
-
-		/*  Set the Used bit of the PATC entry:  */
-		if (!no_exceptions)
-			cmmu->patc_v_and_control[i] |= PG_U;
-
-		/*  ... and finally return the physical address:  */
-		*return_paddr = (paddr_and_sbit & 0xfffff000) | (vaddr & 0xfff);
-		return vaddr_and_control & PG_PROT? 1 : 2;
-	}
-
-	/*
-	 *  The address was neither found in the BATC, nor the PATC.
-	 */
-
-	/*
-	 *  Attempt a search through page tables, to refill the PATC:
-	 */
-	seg_base = (uint32_t *) memory_paddr_to_hostaddr(
-	    cpu->mem, apr & 0xfffff000, 1);
-
-	seg_descriptor = seg_base[seg_nr];
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		seg_descriptor = LE32_TO_HOST(seg_descriptor);
-	else
-		seg_descriptor = BE32_TO_HOST(seg_descriptor);
-
-#ifdef M8820X_TABLE_SEARCH_DEBUG
-	printf("+---   M8820x page table search debug:\n");
-	printf("| vaddr     0x%08"PRIx32"\n", vaddr);
-	printf("| apr       0x%08"PRIx32"\n", apr);
-	printf("| seg_base  %p (on the host)\n", seg_base);
-	printf("| seg_nr    0x%03x\n", seg_nr);
-	printf("| page_nr   0x%03x\n", page_nr);
-	printf("| sd        0x%08"PRIx32"\n", seg_descriptor);
-#endif
-
-	/*  Segment descriptor invalid? Then cause a segfault exception.  */
-	if (!(seg_descriptor & SG_V)) {
-		/*  PFAR = physical address of faulting segment descriptor:  */
-		pfar = (apr & 0xfffff000) + seg_nr * sizeof(uint32_t);
-		pfsr_status = CMMU_PFSR_SFAULT;
-		goto exception;
-	}
-
-	/*  Usermode attempted to access a supervisor segment?  */
-	if ((seg_descriptor & SG_SO) && !supervisor) {
-		/*  PFAR = physical address of faulting segment descriptor:  */
-		pfar = (apr & 0xfffff000) + seg_nr * sizeof(uint32_t);
-		pfsr_status = CMMU_PFSR_SUPER;
-		goto exception;
-	}
-
-	accumulated_flags = seg_descriptor & SG_RO;
-
-	page_base = (uint32_t *) memory_paddr_to_hostaddr(
-	    cpu->mem, seg_descriptor & 0xfffff000, 1);
-
-	page_descriptor = page_base[page_nr];
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		page_descriptor = LE32_TO_HOST(page_descriptor);
-	else
-		page_descriptor = BE32_TO_HOST(page_descriptor);
-
-#ifdef M8820X_TABLE_SEARCH_DEBUG
-	printf("| page_base %p (on the host)\n", page_base);
-	printf("| pd        0x%08"PRIx32"\n", page_descriptor);
-#endif
-
-	/*  Page descriptor invalid? Then cause a page fault exception.  */
-	if (!(page_descriptor & PG_V)) {
-		/*  PFAR = physical address of faulting page descriptor:  */
-		pfar = (seg_descriptor & 0xfffff000)
-		    + page_nr * sizeof(uint32_t);
-		pfsr_status = CMMU_PFSR_PFAULT;
-		goto exception;
-	}
-
-	/*  Usermode attempted to access a supervisor page?  */
-	if ((page_descriptor & PG_SO) && !supervisor) {
-		/*  PFAR = physical address of faulting page descriptor:  */
-		pfar = (seg_descriptor & 0xfffff000)
-		    + page_nr * sizeof(uint32_t);
-		pfsr_status = CMMU_PFSR_SUPER;
-		goto exception;
-	}
-
-	accumulated_flags |= (page_descriptor & PG_RO);
-
-
-	/*
-	 *  Overwrite the next entry in the PATC with a new entry:
-	 */
-
-	if (!no_exceptions) {
-		i = cmmu->patc_update_index;
-
-		/*  Invalidate the current entry, if it is valid:  */
-		if (cmmu->patc_v_and_control[i] & PG_V)
-			cpu->invalidate_translation_caches(cpu,
-			    cmmu->patc_v_and_control[i] & 0xfffff000,
-			    INVALIDATE_VADDR);
-
-		/*  ... and write the new one:  */
-		cmmu->patc_update_index ++;
-		cmmu->patc_update_index %= N_M88200_PATC_ENTRIES;
-		cmmu->patc_v_and_control[i] =
-		    (vaddr & 0xfffff000) | accumulated_flags | PG_V;
-		cmmu->patc_p_and_supervisorbit[i] =
-		    (page_descriptor & 0xfffff000) |
-		    (supervisor? M8820X_PATC_SUPERVISOR_BIT : 0);
-	}
-
-	/*  Check for writes to read-only pages:  */
-	if (writeflag && (accumulated_flags & PG_RO)) {
-		pfsr_status = CMMU_PFSR_WRITE;
-		goto exception;
-	}
-
-	if (!no_exceptions) {
-		uint32_t tmp;
-
-		/*  We now know that the page is in use.  */
-		cmmu->patc_v_and_control[i] |= PG_U;
-		if (writeflag)
-			cmmu->patc_v_and_control[i] |= PG_M;
-
-		/*
-		 *  Write back the U bit (and possibly the M bit) to the page
-		 *  descriptor in emulated memory:
-		 */
-		tmp = page_descriptor | PG_U;
-		if (writeflag)
-			tmp |= PG_M;
-
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			tmp = LE32_TO_HOST(tmp);
-		else
-			tmp = BE32_TO_HOST(tmp);
-
-		page_base[page_nr] = tmp;
-	}
-
-	/*  Now finally return with the translated page address:  */
-	*return_paddr = (page_descriptor & 0xfffff000) | (vaddr & 0xfff);
-	return (accumulated_flags & PG_RO)? 1 : 2;
-
-
-exception:
-	if (no_exceptions)
-		return 0;
-
-	/*
-	 *  Update the Page Fault Status Register of the CMMU which this fault
-	 *  was associated with, but also clear the PFSR of the _other_ CMMU:
-	 */
-
-	cmmu->reg[CMMU_PFSR] = pfsr_status << 16;
-	cpu->cd.m88k.cmmu[instr? 1 : 0]->reg[CMMU_PFSR] =
-	    CMMU_PFSR_SUCCESS << 16;
-
-	/*  ... and (if necessary) update the Page Fault Address Register:  */
-
-	switch (pfsr_status) {
-
-	case CMMU_PFSR_SUCCESS:
-		fatal("HUH? CMMU_PFSR_SUCCESS:, but exception? TODO\n");
-		exit(1);
-		break;
-
-	case CMMU_PFSR_WRITE:
-		/*  Note: The PFAR is "destroyed"/undefined on write faults.  */
-		cmmu->reg[CMMU_PFAR] = 0;
-		break;
-
-	case CMMU_PFSR_SUPER:
-	case CMMU_PFSR_SFAULT:
-	case CMMU_PFSR_PFAULT:
-		cmmu->reg[CMMU_PFAR] = pfar;
-		break;
-
-	default:
-		fatal("Internal error in memory_m88k? pfsr_status = %i\n",
-		    pfsr_status);
-		exit(1);
-	}
-
-	/*  ... and finally cause the exception:  */
-	m88k_exception(cpu, exception_type, 0);
-
-	return 0;
-}
-
diff -Nru gxemul-0.6.2/src/cpus/memory_mips.c gxemul-0.7.0+dfsg/src/cpus/memory_mips.c
--- gxemul-0.6.2/src/cpus/memory_mips.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_mips.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,148 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  MIPS-specific memory routines. Included from cpu_mips.c.
+ */
+
+#include <sys/types.h>
+#include <sys/mman.h>
+
+
+/*
+ *  memory_cache_R3000():
+ *
+ *  R2000/R3000 specific cache handling.
+ *
+ *  Return value is 1 if a jump to do_return_ok is supposed to happen directly
+ *  after this routine is finished, 0 otherwise.
+ */
+int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr,
+	int writeflag, size_t len, unsigned char *data)
+{
+	unsigned int i;
+	int cache_isolated = 0, addr, hit, which_cache = cache;
+
+
+	if (len > 4 || cache == CACHE_NONE)
+		return 0;
+
+
+	/*
+	 *  R2000/R3000 without correct cache emulation:
+	 *
+	 *  TODO: This is just enough to trick NetBSD/pmax and Ultrix into
+	 *  being able to detect the cache sizes and think that the caches
+	 *  are actually working, but they are not.
+	 */
+
+	if (cache != CACHE_DATA)
+		return 0;
+
+	/*  Is this a cache hit or miss?  */
+	hit = (cpu->cd.mips.cache_last_paddr[which_cache]
+		& ~cpu->cd.mips.cache_mask[which_cache])
+	    == (paddr & ~(cpu->cd.mips.cache_mask[which_cache]));
+
+	/*
+	 *  The cache miss bit is only set on cache reads, and only to the
+	 *  data cache. (?)
+	 *
+	 *  (TODO: is this correct? I don't remember where I got this from.)
+	 */
+	if (cache == CACHE_DATA && writeflag==MEM_READ) {
+		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~MIPS1_CACHE_MISS;
+		if (!hit)
+			cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |=
+			    MIPS1_CACHE_MISS;
+	}
+
+	/*
+	 *  Is the Data cache isolated?  Then don't access main memory:
+	 */
+	if (cache == CACHE_DATA &&
+	    cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES)
+		cache_isolated = 1;
+
+	addr = paddr & cpu->cd.mips.cache_mask[which_cache];
+
+	/*  Data cache isolated?  Then don't access main memory:  */
+	if (cache_isolated) {
+		/*  debug("ISOLATED write=%i cache=%i vaddr=%016"PRIx64" "
+		    "paddr=%016"PRIx64" => addr in cache = 0x%lx\n",
+		    writeflag, cache, (uint64_t) vaddr,
+		    (uint64_t) paddr, addr);  */
+
+		if (writeflag==MEM_READ) {
+			for (i=0; i<len; i++)
+				data[i] = cpu->cd.mips.cache[cache][(addr+i) &
+				    cpu->cd.mips.cache_mask[cache]];
+		} else {
+			for (i=0; i<len; i++)
+				cpu->cd.mips.cache[cache][(addr+i) &
+				    cpu->cd.mips.cache_mask[cache]] = data[i];
+		}
+		return 1;
+	} else {
+		/*  Reload caches if necessary:  */
+
+		/*  No!  Not when not emulating caches fully. (TODO?)  */
+		cpu->cd.mips.cache_last_paddr[cache] = paddr;
+	}
+
+	return 0;
+}
+
+
+#define TRANSLATE_ADDRESS	translate_v2p_mmu3k
+#define	V2P_MMU3K
+#include "memory_mips_v2p.c"
+#undef TRANSLATE_ADDRESS
+#undef V2P_MMU3K
+
+#define TRANSLATE_ADDRESS	translate_v2p_mmu8k
+#define	V2P_MMU8K
+#include "memory_mips_v2p.c"
+#undef TRANSLATE_ADDRESS
+#undef V2P_MMU8K
+
+#define TRANSLATE_ADDRESS	translate_v2p_mmu10k
+#define	V2P_MMU10K
+#include "memory_mips_v2p.c"
+#undef TRANSLATE_ADDRESS
+#undef V2P_MMU10K
+
+/*  Almost generic  :-)  */
+#define TRANSLATE_ADDRESS	translate_v2p_mmu4100
+#define	V2P_MMU4100
+#include "memory_mips_v2p.c"
+#undef TRANSLATE_ADDRESS
+#undef V2P_MMU4100
+
+#define TRANSLATE_ADDRESS	translate_v2p_generic
+#include "memory_mips_v2p.c"
+
+
diff -Nru gxemul-0.6.2/src/cpus/memory_mips.cc gxemul-0.7.0+dfsg/src/cpus/memory_mips.cc
--- gxemul-0.6.2/src/cpus/memory_mips.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_mips.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,148 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  MIPS-specific memory routines. Included from cpu_mips.c.
- */
-
-#include <sys/types.h>
-#include <sys/mman.h>
-
-
-/*
- *  memory_cache_R3000():
- *
- *  R2000/R3000 specific cache handling.
- *
- *  Return value is 1 if a jump to do_return_ok is supposed to happen directly
- *  after this routine is finished, 0 otherwise.
- */
-int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr,
-	int writeflag, size_t len, unsigned char *data)
-{
-	unsigned int i;
-	int cache_isolated = 0, addr, hit, which_cache = cache;
-
-
-	if (len > 4 || cache == CACHE_NONE)
-		return 0;
-
-
-	/*
-	 *  R2000/R3000 without correct cache emulation:
-	 *
-	 *  TODO: This is just enough to trick NetBSD/pmax and Ultrix into
-	 *  being able to detect the cache sizes and think that the caches
-	 *  are actually working, but they are not.
-	 */
-
-	if (cache != CACHE_DATA)
-		return 0;
-
-	/*  Is this a cache hit or miss?  */
-	hit = (cpu->cd.mips.cache_last_paddr[which_cache]
-		& ~cpu->cd.mips.cache_mask[which_cache])
-	    == (paddr & ~(cpu->cd.mips.cache_mask[which_cache]));
-
-	/*
-	 *  The cache miss bit is only set on cache reads, and only to the
-	 *  data cache. (?)
-	 *
-	 *  (TODO: is this correct? I don't remember where I got this from.)
-	 */
-	if (cache == CACHE_DATA && writeflag==MEM_READ) {
-		cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~MIPS1_CACHE_MISS;
-		if (!hit)
-			cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |=
-			    MIPS1_CACHE_MISS;
-	}
-
-	/*
-	 *  Is the Data cache isolated?  Then don't access main memory:
-	 */
-	if (cache == CACHE_DATA &&
-	    cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES)
-		cache_isolated = 1;
-
-	addr = paddr & cpu->cd.mips.cache_mask[which_cache];
-
-	/*  Data cache isolated?  Then don't access main memory:  */
-	if (cache_isolated) {
-		/*  debug("ISOLATED write=%i cache=%i vaddr=%016"PRIx64" "
-		    "paddr=%016"PRIx64" => addr in cache = 0x%lx\n",
-		    writeflag, cache, (uint64_t) vaddr,
-		    (uint64_t) paddr, addr);  */
-
-		if (writeflag==MEM_READ) {
-			for (i=0; i<len; i++)
-				data[i] = cpu->cd.mips.cache[cache][(addr+i) &
-				    cpu->cd.mips.cache_mask[cache]];
-		} else {
-			for (i=0; i<len; i++)
-				cpu->cd.mips.cache[cache][(addr+i) &
-				    cpu->cd.mips.cache_mask[cache]] = data[i];
-		}
-		return 1;
-	} else {
-		/*  Reload caches if necessary:  */
-
-		/*  No!  Not when not emulating caches fully. (TODO?)  */
-		cpu->cd.mips.cache_last_paddr[cache] = paddr;
-	}
-
-	return 0;
-}
-
-
-#define TRANSLATE_ADDRESS	translate_v2p_mmu3k
-#define	V2P_MMU3K
-#include "memory_mips_v2p.cc"
-#undef TRANSLATE_ADDRESS
-#undef V2P_MMU3K
-
-#define TRANSLATE_ADDRESS	translate_v2p_mmu8k
-#define	V2P_MMU8K
-#include "memory_mips_v2p.cc"
-#undef TRANSLATE_ADDRESS
-#undef V2P_MMU8K
-
-#define TRANSLATE_ADDRESS	translate_v2p_mmu10k
-#define	V2P_MMU10K
-#include "memory_mips_v2p.cc"
-#undef TRANSLATE_ADDRESS
-#undef V2P_MMU10K
-
-/*  Almost generic  :-)  */
-#define TRANSLATE_ADDRESS	translate_v2p_mmu4100
-#define	V2P_MMU4100
-#include "memory_mips_v2p.cc"
-#undef TRANSLATE_ADDRESS
-#undef V2P_MMU4100
-
-#define TRANSLATE_ADDRESS	translate_v2p_generic
-#include "memory_mips_v2p.cc"
-
-
diff -Nru gxemul-0.6.2/src/cpus/memory_mips_v2p.c gxemul-0.7.0+dfsg/src/cpus/memory_mips_v2p.c
--- gxemul-0.6.2/src/cpus/memory_mips_v2p.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_mips_v2p.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,449 @@
+/*
+ *  Copyright (C) 2003-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ */
+
+
+/*
+ *  translate_v2p():
+ *
+ *  Translate a virtual MIPS address to a physical address, by looking up the
+ *  address in the TLB. On failure, an exception is generated (except for the
+ *  case when FLAG_NOEXCEPTIONS is used).
+ *
+ *  Note: This function is long and hairy, it is included several times with
+ *        various defines set, to produce more or less optimized versions of
+ *        the function for different emulated CPU types.
+ *
+ *  V2P_MMU3K       Defined for R2000/R3000 emulation. If it is not defined,
+ *                  R4000+/MIPS32/MIPS64 is presumed.
+ *  V2P_MMU10K      This enables the use of 44 userspace bits, instead of 40.
+ *  V2P_MMU4100     VR41xx processors support 1 KB pages, so their page mask
+ *                  is slightly different. (The emulator only supports 4 KB
+ *                  pages, though.)
+ *  V2P_MMU8K       Not yet. (TODO.)
+ *
+ *
+ *  Note:  Unfortunately, the variable name vpn2 is poorly choosen for R2K/R3K,
+ *         since it actual contains the vpn.
+ *
+ *  Return values:
+ *	0  Failure
+ *	1  Success, the page is readable only
+ *	2  Success, the page is read/write
+ */
+int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr,
+	uint64_t *return_paddr, int flags)
+{
+	int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ;
+	int no_exceptions = flags & FLAG_NOEXCEPTIONS;
+	int ksu, use_tlb, status, i;
+	uint64_t vaddr_vpn2=0, vaddr_asid=0;
+	int exccode, tlb_refill;
+	struct mips_coproc *cp0;
+
+#ifdef V2P_MMU3K
+	const int x_64 = 0;
+	const int n_tlbs = 64;
+	const uint32_t pmask = 0xfff;
+	uint64_t xuseg_top;		/*  Well, useg actually.  */
+#else
+#ifdef V2P_MMU10K
+	const uint64_t vpn2_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K;
+	uint64_t xuseg_top = ENTRYHI_VPN2_MASK_R10K | 0x1fffULL;
+#else
+#ifdef V2P_MMU4100
+	const uint64_t vpn2_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK | 0x1800;
+#else
+	const uint64_t vpn2_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK;
+#endif
+	uint64_t xuseg_top = ENTRYHI_VPN2_MASK | 0x1fffULL;
+#endif
+	int x_64;	/*  non-zero for 64-bit address space accesses  */
+	int pageshift, n_tlbs;
+	uint32_t pmask;
+#ifdef V2P_MMU4100
+	const int pagemask_mask = PAGEMASK_MASK_R4100;
+	const int pagemask_shift = PAGEMASK_SHIFT_R4100;
+	const int pfn_shift = 10;
+#else
+	const int pagemask_mask = PAGEMASK_MASK;
+	const int pagemask_shift = PAGEMASK_SHIFT;
+	const int pfn_shift = 12;
+#endif
+#endif	/*  !V2P_MMU3K  */
+
+
+	exccode = -1;
+	tlb_refill = 1;
+
+	/*  Cached values:  */
+	cp0 = cpu->cd.mips.coproc[0];
+	status = cp0->reg[COP0_STATUS];
+
+	/*
+	 *  MIPS R4000+ and MIPS64 Address Translation:
+	 *
+	 *  An address may be in one of the kernel segments, that are directly
+	 *  mapped to physical addresses, or the address needs to be looked up
+	 *  in the TLB entries.
+	 *
+	 *  KSU: EXL: ERL: X:  Name:   Range:
+	 *  ---- ---- ---- --  -----   ------
+	 *
+	 *   10   0    0    0  useg    0 - 0x7fffffff    (2GB)  (via TLB)
+	 *   10   0    0    1  xuseg   0 - 0xffffffffff  (1TB)  (via TLB)
+	 *
+	 *   01   0    0    0  suseg   0          - 0x7fffffff  (2GB via TLB)
+	 *   01   0    0    0  ssseg   0xc0000000 - 0xdfffffff  (0.5 GB via TLB)
+	 *   01   0    0    1  xsuseg  0 - 0xffffffffff         (1TB)  (via TLB)
+	 *   01   0    0    1  xsseg   0x4000000000000000 - 0x400000ffffffffff
+	 *					  (1TB)  (via TLB)
+	 *   01   0    0    1  csseg   0xffffffffc0000000 - 0xffffffffdfffffff
+	 *					  (0.5TB)  (via TLB)
+	 *
+	 *   00   x    x    0  kuseg   0 - 0x7fffffff  (2GB)  (via TLB)  (*)
+	 *   00   x    x    0  kseg0   0x80000000 - 0x9fffffff (0.5GB)
+	 *					  unmapped, cached
+	 *   00   x    x    0  kseg1   0xa0000000 - 0xbfffffff (0.5GB)
+	 *					  unmapped, uncached
+	 *   00   x    x    0  ksseg   0xc0000000 - 0xdfffffff (0.5GB) (via TLB)
+	 *   00   x    x    0  kseg3   0xe0000000 - 0xffffffff (0.5GB) (via TLB)
+	 *   00   x    x    1  xksuseg 0 - 0xffffffffff (1TB) (via TLB) (*)
+	 *   00   x    x    1  xksseg  0x4000000000000000 - 0x400000ffffffffff
+	 *					  (1TB)  (via TLB)
+	 *   00   x    x    1  xkphys  0x8000000000000000 - 0xbfffffffffffffff
+	 *   00   x    x    1  xkseg   0xc000000000000000 - 0xc00000ff7fffffff
+	 *   00   x    x    1  ckseg0  0xffffffff80000000 - 0xffffffff9fffffff
+	 *   00   x    x    1  ckseg1  0xffffffffa0000000 - 0xffffffffbfffffff
+	 *   00   x    x    1  cksseg  0xffffffffc0000000 - 0xffffffffdfffffff
+	 *   00   x    x    1  ckseg3  0xffffffffe0000000 - 0xffffffffffffffff
+	 *					  like 0x80000000 - 0xffffffff
+	 *
+	 *  (*) = if ERL=1 then kuseg is not via TLB, but unmapped,
+	 *  uncached physical memory.
+	 *
+	 *  (KSU==0 or EXL=1 or ERL=1 is enough to use k*seg*.)
+	 *
+	 *  An invalid address causes an Address Error.
+	 *
+	 *  See chapter 4, page 96, in the R4000 manual for more info!
+	 */
+
+#ifdef V2P_MMU3K
+	if (status & MIPS1_SR_KU_CUR)
+		ksu = KSU_USER;
+	else
+		ksu = KSU_KERNEL;
+
+	/*  These are needed later:  */
+	vaddr_asid = cp0->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_ASID_MASK;
+	vaddr_vpn2 = vaddr & R2K3K_ENTRYHI_VPN_MASK;
+#else
+	/*  kx,sx,ux = 0 for 32-bit addressing, 1 for 64-bit addressing.  */
+	ksu = (status & STATUS_KSU_MASK) >> STATUS_KSU_SHIFT;
+	if (status & (STATUS_EXL | STATUS_ERL))
+		ksu = KSU_KERNEL;
+
+	switch (ksu) {
+	case KSU_USER:
+		x_64 = status & STATUS_UX;
+		break;
+	case KSU_KERNEL:
+		x_64 = status & STATUS_KX;
+		break;
+	case KSU_SUPERVISOR:
+		x_64 = status & STATUS_SX;
+		/*  FALLTHROUGH, since supervisor address spaces are not
+		    really implemented yet.  */
+		// fall through
+	default:fatal("memory_mips_v2p.c: ksu=%i not yet implemented yet\n",
+		    ksu);
+		exit(1);
+	}
+
+	n_tlbs = cpu->cd.mips.cpu_type.nr_of_tlb_entries;
+
+	/*  Having this here suppresses a compiler warning:  */
+	pageshift = 12;
+
+	/*  KUSEG: 0x00000000 - 0x7fffffff if ERL = 1 and KSU = kernel:  */
+	if (ksu == KSU_KERNEL && (status & STATUS_ERL) &&
+	    vaddr <= 0x7fffffff) {
+		*return_paddr = vaddr & 0x7fffffff;
+		return 2;
+	}
+
+	/*
+	 *  XKPHYS: 0x8000000000000000 - 0xbfffffffffffffff
+	 *
+	 *  TODO: Is the correct error generated if accessing XKPHYS from
+	 *        usermode?
+	 *
+	 *  TODO: Magic on SGI machines... Cache control, NUMA, etc.:
+	 *        0x9000000080000000   = disable L2 cache (?)
+	 *        0x90000000a0000000   = something on IP30?
+	 *        0x92.... and 0x96... = NUMA on IP27
+	 */
+	if (ksu == KSU_KERNEL && (vaddr & ENTRYHI_R_MASK) == ENTRYHI_R_XKPHYS) {
+		*return_paddr = vaddr & (((uint64_t)1 << 44) - 1);
+		return 2;
+	}
+
+	/*  This is needed later:  */
+	vaddr_asid = cp0->reg[COP0_ENTRYHI] & ENTRYHI_ASID;
+	/*  vpn2 depends on pagemask, which is not fixed on R4000  */
+#endif
+
+	/*  If 32-bit, truncate address and sign extend:  */
+	if (x_64 == 0) {
+		vaddr = (int32_t) vaddr;
+		xuseg_top = 0x7fffffff;
+		/*  (Actually useg for R2000/R3000)  */
+	}
+
+	if (vaddr <= xuseg_top) {
+		use_tlb = 1;
+	} else {
+		if (ksu == KSU_KERNEL) {
+			/*  kseg0, kseg1:  */
+			if (vaddr >= (uint64_t)0xffffffff80000000ULL &&
+			    vaddr <= (uint64_t)0xffffffffbfffffffULL) {
+				*return_paddr = vaddr & 0x1fffffff;
+				return 2;
+			}
+
+			/*  other segments:  */
+			use_tlb = 1;
+		} else {
+			use_tlb = 0;
+		}
+	}
+
+	if (use_tlb) {
+#ifndef V2P_MMU3K
+		int odd = 0;
+		uint64_t cached_lo1 = 0;
+#endif
+		int g_bit, v_bit, d_bit;
+		uint64_t cached_hi, cached_lo0;
+		uint64_t entry_vpn2 = 0, entry_asid, pfn;
+		int i_end;
+
+		i = cpu->cd.mips.last_written_tlb_index;
+		i_end = i == 0? n_tlbs-1 : i - 1;
+
+		/*  Scan all TLB entries:  */
+		for (;;) {
+#ifdef V2P_MMU3K
+			/*  R3000 or similar:  */
+			cached_hi = cp0->tlbs[i].hi;
+			cached_lo0 = cp0->tlbs[i].lo0;
+
+			entry_vpn2 = cached_hi & R2K3K_ENTRYHI_VPN_MASK;
+			entry_asid = cached_hi & R2K3K_ENTRYHI_ASID_MASK;
+			g_bit = cached_lo0 & R2K3K_ENTRYLO_G;
+			v_bit = cached_lo0 & R2K3K_ENTRYLO_V;
+			d_bit = cached_lo0 & R2K3K_ENTRYLO_D;
+#else
+			/*  R4000 or similar:  */
+			pmask = cp0->tlbs[i].mask & pagemask_mask;
+			cached_hi = cp0->tlbs[i].hi;
+			cached_lo0 = cp0->tlbs[i].lo0;
+			cached_lo1 = cp0->tlbs[i].lo1;
+
+			/*  Optimized for minimum page size:  */
+			if (pmask == 0) {
+				pageshift = pagemask_shift - 1;
+				entry_vpn2 = (cached_hi & vpn2_mask)
+				    >> pagemask_shift;
+				vaddr_vpn2 = (vaddr & vpn2_mask)
+				    >> pagemask_shift;
+				pmask = (1 << (pagemask_shift-1)) - 1;
+				odd = (vaddr >> (pagemask_shift-1)) & 1;
+			} else {
+				/*  Non-standard page mask:  */
+				switch (pmask | ((1 << pagemask_shift) - 1)) {
+				case 0x00007ff:	pageshift = 10; break;
+				case 0x0001fff:	pageshift = 12; break;
+				case 0x0007fff:	pageshift = 14; break;
+				case 0x001ffff:	pageshift = 16; break;
+				case 0x007ffff:	pageshift = 18; break;
+				case 0x01fffff:	pageshift = 20; break;
+				case 0x07fffff:	pageshift = 22; break;
+				case 0x1ffffff:	pageshift = 24; break;
+				case 0x7ffffff:	pageshift = 26; break;
+				default:fatal("pmask=%08" PRIx32"\n", pmask);
+					exit(1);
+				}
+
+				entry_vpn2 = (cached_hi &
+				    vpn2_mask) >> (pageshift + 1);
+				vaddr_vpn2 = (vaddr & vpn2_mask) >>
+				    (pageshift + 1);
+				pmask = (1 << pageshift) - 1;
+				odd = (vaddr >> pageshift) & 1;
+			}
+
+			/*  Assume even virtual page...  */
+			v_bit = cached_lo0 & ENTRYLO_V;
+			d_bit = cached_lo0 & ENTRYLO_D;
+
+#ifdef V2P_MMU8K
+			/*
+			 *  TODO:  I don't really know anything about the R8000.
+			 *  http://futuretech.mirror.vuurwerk.net/i2sec7.html
+			 *  says that it has a three-way associative TLB with
+			 *  384 entries, 16KB page size, and some other things.
+			 *
+			 *  It feels like things like the valid bit (ala R4000)
+			 *  and dirty bit are not implemented the same on R8000.
+			 *
+			 *  http://sgistuff.tastensuppe.de/documents/
+			 *		R8000_chipset.html
+			 *  also has some info, but no details.
+			 */
+			v_bit = 1;	/*  Big TODO  */
+			d_bit = 1;
+#endif
+
+			entry_asid = cached_hi & ENTRYHI_ASID;
+
+			/*  ... reload pfn, v_bit, d_bit if
+			    it was the odd virtual page:  */
+			if (odd) {
+				v_bit = cached_lo1 & ENTRYLO_V;
+				d_bit = cached_lo1 & ENTRYLO_D;
+			}
+#ifdef V2P_MMU4100
+			g_bit = cached_lo1 & cached_lo0 & ENTRYLO_G;
+#else
+			g_bit = cached_hi & TLB_G;
+#endif
+
+#endif
+
+			/*  Is there a VPN and ASID match?  */
+			if (entry_vpn2 == vaddr_vpn2 &&
+			    (entry_asid == vaddr_asid || g_bit)) {
+				/*  debug("OK MAP 1, i=%i { vaddr=%016" PRIx64" "
+				    "==> paddr %016" PRIx64" v=%i d=%i "
+				    "asid=0x%02x }\n", i, (uint64_t) vaddr,
+				    (uint64_t) *return_paddr, v_bit?1:0,
+				    d_bit?1:0, vaddr_asid);  */
+				if (v_bit) {
+					if (d_bit || (!d_bit &&
+					    writeflag == MEM_READ)) {
+						uint64_t paddr;
+						/*  debug("OK MAP 2!!! { w=%i "
+						    "vaddr=%016" PRIx64" ==> "
+						    "d=%i v=%i paddr %016"
+						    PRIx64" ",
+						    writeflag, (uint64_t)vaddr,
+						    d_bit?1:0, v_bit?1:0,
+						    (uint64_t) *return_paddr);
+						    debug(", tlb entry %2i: ma"
+						    "sk=%016" PRIx64" hi=%016"
+						    PRIx64" lo0=%016" PRIx64
+						    " lo1=%016" PRIx64"\n",
+						    i, cp0->tlbs[i].mask, cp0->
+						    tlbs[i].hi, cp0->tlbs[i].
+						    lo0, cp0->tlbs[i].lo1);
+						*/
+#ifdef V2P_MMU3K
+						pfn = cached_lo0 &
+						    R2K3K_ENTRYLO_PFN_MASK;
+						paddr = pfn | (vaddr & pmask);
+#else
+						pfn = ((odd? cached_lo1 :
+						    cached_lo0)
+						    & ENTRYLO_PFN_MASK)
+						    >> ENTRYLO_PFN_SHIFT;
+						paddr = ((pfn << pfn_shift) &
+						    ~pmask) | (vaddr & pmask);
+#endif
+
+						*return_paddr = paddr;
+						return d_bit? 2 : 1;
+					} else {
+						/*  TLB modif. exception  */
+						tlb_refill = 0;
+						exccode = EXCEPTION_MOD;
+						goto exception;
+					}
+				} else {
+					/*  TLB invalid exception  */
+					tlb_refill = 0;
+					goto exception;
+				}
+			}
+
+			if (i == i_end)
+				break;
+
+			/*  Go to the next TLB entry:  */
+			i ++;
+			if (i == n_tlbs)
+				i = 0;
+		}
+	}
+
+	/*
+	 *  We are here if for example userland code tried to access
+	 *  kernel memory, OR if there was a TLB refill.
+	 */
+
+	if (!use_tlb) {
+		tlb_refill = 0;
+		if (writeflag == MEM_WRITE)
+			exccode = EXCEPTION_ADES;
+		else
+			exccode = EXCEPTION_ADEL;
+	}
+
+exception:
+	if (no_exceptions)
+		return 0;
+
+	/*  TLB Load or Store exception:  */
+	if (exccode == -1) {
+		if (writeflag == MEM_WRITE)
+			exccode = EXCEPTION_TLBS;
+		else
+			exccode = EXCEPTION_TLBL;
+	}
+
+#ifdef V2P_MMU3K
+	vaddr_asid >>= R2K3K_ENTRYHI_ASID_SHIFT;
+	vaddr_vpn2 >>= 12;
+#endif
+
+	mips_cpu_exception(cpu, exccode, tlb_refill, vaddr,
+	    0, vaddr_vpn2, vaddr_asid, x_64);
+
+	/*  Return failure:  */
+	return 0;
+}
+
diff -Nru gxemul-0.6.2/src/cpus/memory_mips_v2p.cc gxemul-0.7.0+dfsg/src/cpus/memory_mips_v2p.cc
--- gxemul-0.6.2/src/cpus/memory_mips_v2p.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_mips_v2p.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,448 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-
-/*
- *  translate_v2p():
- *
- *  Translate a virtual MIPS address to a physical address, by looking up the
- *  address in the TLB. On failure, an exception is generated (except for the
- *  case when FLAG_NOEXCEPTIONS is used).
- *
- *  Note: This function is long and hairy, it is included several times with
- *        various defines set, to produce more or less optimized versions of
- *        the function for different emulated CPU types.
- *
- *  V2P_MMU3K       Defined for R2000/R3000 emulation. If it is not defined,
- *                  R4000+/MIPS32/MIPS64 is presumed.
- *  V2P_MMU10K      This enables the use of 44 userspace bits, instead of 40.
- *  V2P_MMU4100     VR41xx processors support 1 KB pages, so their page mask
- *                  is slightly different. (The emulator only supports 4 KB
- *                  pages, though.)
- *  V2P_MMU8K       Not yet. (TODO.)
- *
- *
- *  Note:  Unfortunately, the variable name vpn2 is poorly choosen for R2K/R3K,
- *         since it actual contains the vpn.
- *
- *  Return values:
- *	0  Failure
- *	1  Success, the page is readable only
- *	2  Success, the page is read/write
- */
-int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr,
-	uint64_t *return_paddr, int flags)
-{
-	int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ;
-	int no_exceptions = flags & FLAG_NOEXCEPTIONS;
-	int ksu, use_tlb, status, i;
-	uint64_t vaddr_vpn2=0, vaddr_asid=0;
-	int exccode, tlb_refill;
-	struct mips_coproc *cp0;
-
-#ifdef V2P_MMU3K
-	const int x_64 = 0;
-	const int n_tlbs = 64;
-	const uint32_t pmask = 0xfff;
-	uint64_t xuseg_top;		/*  Well, useg actually.  */
-#else
-#ifdef V2P_MMU10K
-	const uint64_t vpn2_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K;
-	uint64_t xuseg_top = ENTRYHI_VPN2_MASK_R10K | 0x1fffULL;
-#else
-#ifdef V2P_MMU4100
-	const uint64_t vpn2_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK | 0x1800;
-#else
-	const uint64_t vpn2_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK;
-#endif
-	uint64_t xuseg_top = ENTRYHI_VPN2_MASK | 0x1fffULL;
-#endif
-	int x_64;	/*  non-zero for 64-bit address space accesses  */
-	int pageshift, n_tlbs;
-	uint32_t pmask;
-#ifdef V2P_MMU4100
-	const int pagemask_mask = PAGEMASK_MASK_R4100;
-	const int pagemask_shift = PAGEMASK_SHIFT_R4100;
-	const int pfn_shift = 10;
-#else
-	const int pagemask_mask = PAGEMASK_MASK;
-	const int pagemask_shift = PAGEMASK_SHIFT;
-	const int pfn_shift = 12;
-#endif
-#endif	/*  !V2P_MMU3K  */
-
-
-	exccode = -1;
-	tlb_refill = 1;
-
-	/*  Cached values:  */
-	cp0 = cpu->cd.mips.coproc[0];
-	status = cp0->reg[COP0_STATUS];
-
-	/*
-	 *  MIPS R4000+ and MIPS64 Address Translation:
-	 *
-	 *  An address may be in one of the kernel segments, that are directly
-	 *  mapped to physical addresses, or the address needs to be looked up
-	 *  in the TLB entries.
-	 *
-	 *  KSU: EXL: ERL: X:  Name:   Range:
-	 *  ---- ---- ---- --  -----   ------
-	 *
-	 *   10   0    0    0  useg    0 - 0x7fffffff    (2GB)  (via TLB)
-	 *   10   0    0    1  xuseg   0 - 0xffffffffff  (1TB)  (via TLB)
-	 *
-	 *   01   0    0    0  suseg   0          - 0x7fffffff  (2GB via TLB)
-	 *   01   0    0    0  ssseg   0xc0000000 - 0xdfffffff  (0.5 GB via TLB)
-	 *   01   0    0    1  xsuseg  0 - 0xffffffffff         (1TB)  (via TLB)
-	 *   01   0    0    1  xsseg   0x4000000000000000 - 0x400000ffffffffff
-	 *					  (1TB)  (via TLB)
-	 *   01   0    0    1  csseg   0xffffffffc0000000 - 0xffffffffdfffffff
-	 *					  (0.5TB)  (via TLB)
-	 *
-	 *   00   x    x    0  kuseg   0 - 0x7fffffff  (2GB)  (via TLB)  (*)
-	 *   00   x    x    0  kseg0   0x80000000 - 0x9fffffff (0.5GB)
-	 *					  unmapped, cached
-	 *   00   x    x    0  kseg1   0xa0000000 - 0xbfffffff (0.5GB)
-	 *					  unmapped, uncached
-	 *   00   x    x    0  ksseg   0xc0000000 - 0xdfffffff (0.5GB) (via TLB)
-	 *   00   x    x    0  kseg3   0xe0000000 - 0xffffffff (0.5GB) (via TLB)
-	 *   00   x    x    1  xksuseg 0 - 0xffffffffff (1TB) (via TLB) (*)
-	 *   00   x    x    1  xksseg  0x4000000000000000 - 0x400000ffffffffff
-	 *					  (1TB)  (via TLB)
-	 *   00   x    x    1  xkphys  0x8000000000000000 - 0xbfffffffffffffff
-	 *   00   x    x    1  xkseg   0xc000000000000000 - 0xc00000ff7fffffff
-	 *   00   x    x    1  ckseg0  0xffffffff80000000 - 0xffffffff9fffffff
-	 *   00   x    x    1  ckseg1  0xffffffffa0000000 - 0xffffffffbfffffff
-	 *   00   x    x    1  cksseg  0xffffffffc0000000 - 0xffffffffdfffffff
-	 *   00   x    x    1  ckseg3  0xffffffffe0000000 - 0xffffffffffffffff
-	 *					  like 0x80000000 - 0xffffffff
-	 *
-	 *  (*) = if ERL=1 then kuseg is not via TLB, but unmapped,
-	 *  uncached physical memory.
-	 *
-	 *  (KSU==0 or EXL=1 or ERL=1 is enough to use k*seg*.)
-	 *
-	 *  An invalid address causes an Address Error.
-	 *
-	 *  See chapter 4, page 96, in the R4000 manual for more info!
-	 */
-
-#ifdef V2P_MMU3K
-	if (status & MIPS1_SR_KU_CUR)
-		ksu = KSU_USER;
-	else
-		ksu = KSU_KERNEL;
-
-	/*  These are needed later:  */
-	vaddr_asid = cp0->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_ASID_MASK;
-	vaddr_vpn2 = vaddr & R2K3K_ENTRYHI_VPN_MASK;
-#else
-	/*  kx,sx,ux = 0 for 32-bit addressing, 1 for 64-bit addressing.  */
-	ksu = (status & STATUS_KSU_MASK) >> STATUS_KSU_SHIFT;
-	if (status & (STATUS_EXL | STATUS_ERL))
-		ksu = KSU_KERNEL;
-
-	switch (ksu) {
-	case KSU_USER:
-		x_64 = status & STATUS_UX;
-		break;
-	case KSU_KERNEL:
-		x_64 = status & STATUS_KX;
-		break;
-	case KSU_SUPERVISOR:
-		x_64 = status & STATUS_SX;
-		/*  FALLTHROUGH, since supervisor address spaces are not
-		    really implemented yet.  */
-	default:fatal("memory_mips_v2p.c: ksu=%i not yet implemented yet\n",
-		    ksu);
-		exit(1);
-	}
-
-	n_tlbs = cpu->cd.mips.cpu_type.nr_of_tlb_entries;
-
-	/*  Having this here suppresses a compiler warning:  */
-	pageshift = 12;
-
-	/*  KUSEG: 0x00000000 - 0x7fffffff if ERL = 1 and KSU = kernel:  */
-	if (ksu == KSU_KERNEL && (status & STATUS_ERL) &&
-	    vaddr <= 0x7fffffff) {
-		*return_paddr = vaddr & 0x7fffffff;
-		return 2;
-	}
-
-	/*
-	 *  XKPHYS: 0x8000000000000000 - 0xbfffffffffffffff
-	 *
-	 *  TODO: Is the correct error generated if accessing XKPHYS from
-	 *        usermode?
-	 *
-	 *  TODO: Magic on SGI machines... Cache control, NUMA, etc.:
-	 *        0x9000000080000000   = disable L2 cache (?)
-	 *        0x90000000a0000000   = something on IP30?
-	 *        0x92.... and 0x96... = NUMA on IP27
-	 */
-	if (ksu == KSU_KERNEL && (vaddr & ENTRYHI_R_MASK) == ENTRYHI_R_XKPHYS) {
-		*return_paddr = vaddr & (((uint64_t)1 << 44) - 1);
-		return 2;
-	}
-
-	/*  This is needed later:  */
-	vaddr_asid = cp0->reg[COP0_ENTRYHI] & ENTRYHI_ASID;
-	/*  vpn2 depends on pagemask, which is not fixed on R4000  */
-#endif
-
-	/*  If 32-bit, truncate address and sign extend:  */
-	if (x_64 == 0) {
-		vaddr = (int32_t) vaddr;
-		xuseg_top = 0x7fffffff;
-		/*  (Actually useg for R2000/R3000)  */
-	}
-
-	if (vaddr <= xuseg_top) {
-		use_tlb = 1;
-	} else {
-		if (ksu == KSU_KERNEL) {
-			/*  kseg0, kseg1:  */
-			if (vaddr >= (uint64_t)0xffffffff80000000ULL &&
-			    vaddr <= (uint64_t)0xffffffffbfffffffULL) {
-				*return_paddr = vaddr & 0x1fffffff;
-				return 2;
-			}
-
-			/*  other segments:  */
-			use_tlb = 1;
-		} else {
-			use_tlb = 0;
-		}
-	}
-
-	if (use_tlb) {
-#ifndef V2P_MMU3K
-		int odd = 0;
-		uint64_t cached_lo1 = 0;
-#endif
-		int g_bit, v_bit, d_bit;
-		uint64_t cached_hi, cached_lo0;
-		uint64_t entry_vpn2 = 0, entry_asid, pfn;
-		int i_end;
-
-		i = cpu->cd.mips.last_written_tlb_index;
-		i_end = i == 0? n_tlbs-1 : i - 1;
-
-		/*  Scan all TLB entries:  */
-		for (;;) {
-#ifdef V2P_MMU3K
-			/*  R3000 or similar:  */
-			cached_hi = cp0->tlbs[i].hi;
-			cached_lo0 = cp0->tlbs[i].lo0;
-
-			entry_vpn2 = cached_hi & R2K3K_ENTRYHI_VPN_MASK;
-			entry_asid = cached_hi & R2K3K_ENTRYHI_ASID_MASK;
-			g_bit = cached_lo0 & R2K3K_ENTRYLO_G;
-			v_bit = cached_lo0 & R2K3K_ENTRYLO_V;
-			d_bit = cached_lo0 & R2K3K_ENTRYLO_D;
-#else
-			/*  R4000 or similar:  */
-			pmask = cp0->tlbs[i].mask & pagemask_mask;
-			cached_hi = cp0->tlbs[i].hi;
-			cached_lo0 = cp0->tlbs[i].lo0;
-			cached_lo1 = cp0->tlbs[i].lo1;
-
-			/*  Optimized for minimum page size:  */
-			if (pmask == 0) {
-				pageshift = pagemask_shift - 1;
-				entry_vpn2 = (cached_hi & vpn2_mask)
-				    >> pagemask_shift;
-				vaddr_vpn2 = (vaddr & vpn2_mask)
-				    >> pagemask_shift;
-				pmask = (1 << (pagemask_shift-1)) - 1;
-				odd = (vaddr >> (pagemask_shift-1)) & 1;
-			} else {
-				/*  Non-standard page mask:  */
-				switch (pmask | ((1 << pagemask_shift) - 1)) {
-				case 0x00007ff:	pageshift = 10; break;
-				case 0x0001fff:	pageshift = 12; break;
-				case 0x0007fff:	pageshift = 14; break;
-				case 0x001ffff:	pageshift = 16; break;
-				case 0x007ffff:	pageshift = 18; break;
-				case 0x01fffff:	pageshift = 20; break;
-				case 0x07fffff:	pageshift = 22; break;
-				case 0x1ffffff:	pageshift = 24; break;
-				case 0x7ffffff:	pageshift = 26; break;
-				default:fatal("pmask=%08" PRIx32"\n", pmask);
-					exit(1);
-				}
-
-				entry_vpn2 = (cached_hi &
-				    vpn2_mask) >> (pageshift + 1);
-				vaddr_vpn2 = (vaddr & vpn2_mask) >>
-				    (pageshift + 1);
-				pmask = (1 << pageshift) - 1;
-				odd = (vaddr >> pageshift) & 1;
-			}
-
-			/*  Assume even virtual page...  */
-			v_bit = cached_lo0 & ENTRYLO_V;
-			d_bit = cached_lo0 & ENTRYLO_D;
-
-#ifdef V2P_MMU8K
-			/*
-			 *  TODO:  I don't really know anything about the R8000.
-			 *  http://futuretech.mirror.vuurwerk.net/i2sec7.html
-			 *  says that it has a three-way associative TLB with
-			 *  384 entries, 16KB page size, and some other things.
-			 *
-			 *  It feels like things like the valid bit (ala R4000)
-			 *  and dirty bit are not implemented the same on R8000.
-			 *
-			 *  http://sgistuff.tastensuppe.de/documents/
-			 *		R8000_chipset.html
-			 *  also has some info, but no details.
-			 */
-			v_bit = 1;	/*  Big TODO  */
-			d_bit = 1;
-#endif
-
-			entry_asid = cached_hi & ENTRYHI_ASID;
-
-			/*  ... reload pfn, v_bit, d_bit if
-			    it was the odd virtual page:  */
-			if (odd) {
-				v_bit = cached_lo1 & ENTRYLO_V;
-				d_bit = cached_lo1 & ENTRYLO_D;
-			}
-#ifdef V2P_MMU4100
-			g_bit = cached_lo1 & cached_lo0 & ENTRYLO_G;
-#else
-			g_bit = cached_hi & TLB_G;
-#endif
-
-#endif
-
-			/*  Is there a VPN and ASID match?  */
-			if (entry_vpn2 == vaddr_vpn2 &&
-			    (entry_asid == vaddr_asid || g_bit)) {
-				/*  debug("OK MAP 1, i=%i { vaddr=%016" PRIx64" "
-				    "==> paddr %016" PRIx64" v=%i d=%i "
-				    "asid=0x%02x }\n", i, (uint64_t) vaddr,
-				    (uint64_t) *return_paddr, v_bit?1:0,
-				    d_bit?1:0, vaddr_asid);  */
-				if (v_bit) {
-					if (d_bit || (!d_bit &&
-					    writeflag == MEM_READ)) {
-						uint64_t paddr;
-						/*  debug("OK MAP 2!!! { w=%i "
-						    "vaddr=%016" PRIx64" ==> "
-						    "d=%i v=%i paddr %016"
-						    PRIx64" ",
-						    writeflag, (uint64_t)vaddr,
-						    d_bit?1:0, v_bit?1:0,
-						    (uint64_t) *return_paddr);
-						    debug(", tlb entry %2i: ma"
-						    "sk=%016" PRIx64" hi=%016"
-						    PRIx64" lo0=%016" PRIx64
-						    " lo1=%016" PRIx64"\n",
-						    i, cp0->tlbs[i].mask, cp0->
-						    tlbs[i].hi, cp0->tlbs[i].
-						    lo0, cp0->tlbs[i].lo1);
-						*/
-#ifdef V2P_MMU3K
-						pfn = cached_lo0 &
-						    R2K3K_ENTRYLO_PFN_MASK;
-						paddr = pfn | (vaddr & pmask);
-#else
-						pfn = ((odd? cached_lo1 :
-						    cached_lo0)
-						    & ENTRYLO_PFN_MASK)
-						    >> ENTRYLO_PFN_SHIFT;
-						paddr = ((pfn << pfn_shift) &
-						    ~pmask) | (vaddr & pmask);
-#endif
-
-						*return_paddr = paddr;
-						return d_bit? 2 : 1;
-					} else {
-						/*  TLB modif. exception  */
-						tlb_refill = 0;
-						exccode = EXCEPTION_MOD;
-						goto exception;
-					}
-				} else {
-					/*  TLB invalid exception  */
-					tlb_refill = 0;
-					goto exception;
-				}
-			}
-
-			if (i == i_end)
-				break;
-
-			/*  Go to the next TLB entry:  */
-			i ++;
-			if (i == n_tlbs)
-				i = 0;
-		}
-	}
-
-	/*
-	 *  We are here if for example userland code tried to access
-	 *  kernel memory, OR if there was a TLB refill.
-	 */
-
-	if (!use_tlb) {
-		tlb_refill = 0;
-		if (writeflag == MEM_WRITE)
-			exccode = EXCEPTION_ADES;
-		else
-			exccode = EXCEPTION_ADEL;
-	}
-
-exception:
-	if (no_exceptions)
-		return 0;
-
-	/*  TLB Load or Store exception:  */
-	if (exccode == -1) {
-		if (writeflag == MEM_WRITE)
-			exccode = EXCEPTION_TLBS;
-		else
-			exccode = EXCEPTION_TLBL;
-	}
-
-#ifdef V2P_MMU3K
-	vaddr_asid >>= R2K3K_ENTRYHI_ASID_SHIFT;
-	vaddr_vpn2 >>= 12;
-#endif
-
-	mips_cpu_exception(cpu, exccode, tlb_refill, vaddr,
-	    0, vaddr_vpn2, vaddr_asid, x_64);
-
-	/*  Return failure:  */
-	return 0;
-}
-
diff -Nru gxemul-0.6.2/src/cpus/memory_ppc.c gxemul-0.7.0+dfsg/src/cpus/memory_ppc.c
--- gxemul-0.6.2/src/cpus/memory_ppc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_ppc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,298 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Included from cpu_ppc.c.
+ */
+
+
+/*
+ *  ppc_bat():
+ *
+ *  BAT translation. Returns -1 if there was no BAT hit, >= 0 for a hit.
+ *  (0 for access denied, 1 for read-only, and 2 for read-write access allowed.)
+ */
+int ppc_bat(struct cpu *cpu, uint64_t vaddr, uint64_t *return_paddr, int flags,
+	int user)
+{
+	int i, istart = 0, iend = 8, pp;
+
+	if (flags & FLAG_INSTR)
+		iend = 4;
+	else
+		istart = 4;
+
+	if (cpu->cd.ppc.bits != 32) {
+		fatal("TODO: ppc_bat() for non-32-bit\n");
+		exit(1);
+	}
+	if (cpu->cd.ppc.cpu_type.flags & PPC_601) {
+		fatal("TODO: ppc_bat() for PPC 601\n");
+		exit(1);
+	}
+
+	/*  Scan either the 4 instruction BATs or the 4 data BATs:  */
+	for (i=istart; i<iend; i++) {
+		int regnr = SPR_IBAT0U + i * 2;
+		uint32_t upper = cpu->cd.ppc.spr[regnr];
+		uint32_t lower = cpu->cd.ppc.spr[regnr + 1];
+		uint32_t phys = lower & BAT_RPN, ebs = upper & BAT_EPI;
+		uint32_t mask = ((upper & BAT_BL) << 15) | 0x1ffff;
+
+		/*  Not valid in either supervisor or user mode?  */
+		if (user && !(upper & BAT_Vu))
+			continue;
+		if (!user && !(upper & BAT_Vs))
+			continue;
+
+		/*  Virtual address mismatch? Then skip.  */
+		if ((vaddr & ~mask) != (ebs & ~mask))
+			continue;
+
+		*return_paddr = (vaddr & mask) | (phys & ~mask);
+
+		pp = lower & BAT_PP;
+		switch (pp) {
+		case BAT_PP_NONE:
+			return 0;
+		case BAT_PP_RO_S:
+		case BAT_PP_RO:
+			return (flags & FLAG_WRITEFLAG)? 0 : 1;
+		default:/*  BAT_PP_RW:  */
+			return 2;
+		}
+	}
+
+	return -1;
+}
+
+
+/*
+ *  get_pte_low():
+ *
+ *  Scan a PTE group for a cmp (compare) value.
+ *
+ *  Returns 1 if the value was found, and *lowp is set to the low PTE word.
+ *  Returns 0 if no match was found.
+ */
+static int get_pte_low(struct cpu *cpu, uint64_t pteg_select,
+	uint32_t *lowp, uint32_t cmp)
+{
+	unsigned char *d = memory_paddr_to_hostaddr(cpu->mem, pteg_select, 1);
+	int i;
+
+	for (i=0; i<8; i++) {
+		uint32_t *ep = (uint32_t *) (d + (i << 3)), upper;
+		upper = *ep;
+		upper = BE32_TO_HOST(upper);
+
+		/*  Valid PTE, and correct api and vsid?  */
+		if (upper == cmp) {
+			uint32_t lo = ep[1];
+			lo = BE32_TO_HOST(lo);
+			*lowp = lo;
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+
+/*
+ *  ppc_vtp32():
+ *
+ *  Virtual to physical address translation (32-bit mode).
+ *
+ *  Returns 1 if a translation was found, 0 if none was found. However, finding
+ *  a translation does not mean that it should be returned; there can be
+ *  a permission violation. *resp is set to 0 for no access, 1 for read-only
+ *  access, or 2 for read/write access.
+ */
+static int ppc_vtp32(struct cpu *cpu, uint32_t vaddr, uint64_t *return_paddr,
+	int *resp, uint64_t msr, int writeflag, int instr)
+{
+	int srn = (vaddr >> 28) & 15, api = (vaddr >> 22) & PTE_API;
+	int access, key, match;
+	uint32_t vsid = cpu->cd.ppc.sr[srn] & 0x00ffffff;
+	uint64_t sdr1 = cpu->cd.ppc.spr[SPR_SDR1], htaborg;
+	uint32_t hash1, hash2, pteg_select, tmp;
+	uint32_t lower_pte = 0, cmp;
+
+	htaborg = sdr1 & 0xffff0000UL;
+
+	/*  Primary hash:  */
+	hash1 = (vsid & 0x7ffff) ^ ((vaddr >> 12) & 0xffff);
+	tmp = (hash1 >> 10) & (sdr1 & 0x1ff);
+	pteg_select = htaborg & 0xfe000000;
+	pteg_select |= ((hash1 & 0x3ff) << 6);
+	pteg_select |= (htaborg & 0x01ff0000) | (tmp << 16);
+	cpu->cd.ppc.spr[SPR_HASH1] = pteg_select;
+	cmp = cpu->cd.ppc.spr[instr? SPR_ICMP : SPR_DCMP] =
+	    PTE_VALID | api | (vsid << PTE_VSID_SHFT);
+	match = get_pte_low(cpu, pteg_select, &lower_pte, cmp);
+
+	/*  Secondary hash:  */
+	hash2 = hash1 ^ 0x7ffff;
+	tmp = (hash2 >> 10) & (sdr1 & 0x1ff);
+	pteg_select = htaborg & 0xfe000000;
+	pteg_select |= ((hash2 & 0x3ff) << 6);
+	pteg_select |= (htaborg & 0x01ff0000) | (tmp << 16);
+	cpu->cd.ppc.spr[SPR_HASH2] = pteg_select;
+	if (!match) {
+		cmp |= PTE_HID;
+		match = get_pte_low(cpu, pteg_select, &lower_pte, cmp);
+	}
+
+	*resp = 0;
+
+	if (!match)
+		return 0;
+
+	/*  Non-executable, or Guarded page?  */
+	if (instr && cpu->cd.ppc.sr[srn] & SR_NOEXEC)
+		return 1;
+	if (instr && lower_pte & PTE_G)
+		return 1;
+
+	access = lower_pte & PTE_PP;
+	*return_paddr = (lower_pte & PTE_RPGN) | (vaddr & ~PTE_RPGN);
+
+	key = (cpu->cd.ppc.sr[srn] & SR_PRKEY && msr & PPC_MSR_PR) ||
+	    (cpu->cd.ppc.sr[srn] & SR_SUKEY && !(msr & PPC_MSR_PR));
+
+	if (key) {
+		switch (access) {
+		case 1:
+		case 3:	*resp = writeflag? 0 : 1;
+			break;
+		case 2:	*resp = 2;
+			break;
+		}
+	} else {
+		switch (access) {
+		case 3:	*resp = writeflag? 0 : 1;
+			break;
+		default:*resp = 2;
+		}
+	}
+
+	return 1;
+}
+
+
+/*
+ *  ppc_translate_v2p():
+ *
+ *  Return values:
+ *	0  Failure
+ *	1  Success, the page is readable only
+ *	2  Success, the page is read/write
+ */
+int ppc_translate_v2p(struct cpu *cpu, uint64_t vaddr,
+	uint64_t *return_paddr, int flags)
+{
+	int instr = flags & FLAG_INSTR, res = 0, match, user;
+	int writeflag = flags & FLAG_WRITEFLAG? 1 : 0;
+	uint64_t msr;
+
+	reg_access_msr(cpu, &msr, 0, 0);
+	user = msr & PPC_MSR_PR? 1 : 0;
+
+	if (cpu->cd.ppc.bits == 32)
+		vaddr &= 0xffffffff;
+
+	if ((instr && !(msr & PPC_MSR_IR)) || (!instr && !(msr & PPC_MSR_DR))) {
+		*return_paddr = vaddr;
+		return 2;
+	}
+
+	if (cpu->cd.ppc.cpu_type.flags & PPC_601) {
+		fatal("ppc_translate_v2p(): TODO: 601\n");
+		exit(1);
+	}
+
+	/*  Try the BATs first:  */
+	if (cpu->cd.ppc.bits == 32) {
+		res = ppc_bat(cpu, vaddr, return_paddr, flags, user);
+		if (res > 0)
+			return res;
+		if (res == 0) {
+			fatal("[ TODO: BAT exception ]\n");
+			exit(1);
+		}
+	}
+
+	/*  Virtual to physical translation:  */
+	if (cpu->cd.ppc.bits == 32) {
+		match = ppc_vtp32(cpu, vaddr, return_paddr, &res, msr,
+		    writeflag, instr);
+		if (match && res > 0)
+			return res;
+	} else {
+		/*  htaborg = sdr1 & 0xfffffffffffc0000ULL;  */
+		fatal("TODO: ppc 64-bit translation\n");
+		exit(1);
+	}
+
+
+	/*
+	 *  No match? Then cause an exception.
+	 *
+	 *  PPC603: cause a software TLB reload exception.
+	 *  All others: cause a DSI or ISI.
+	 */
+
+	if (flags & FLAG_NOEXCEPTIONS)
+		return 0;
+
+	if (!quiet_mode)
+		fatal("[ memory_ppc: exception! vaddr=0x%" PRIx64" pc=0x%" PRIx64
+		    " instr=%i user=%i wf=%i ]\n", (uint64_t) vaddr,
+		    (uint64_t) cpu->pc, instr, user, writeflag);
+
+	if (cpu->cd.ppc.cpu_type.flags & PPC_603) {
+		cpu->cd.ppc.spr[instr? SPR_IMISS : SPR_DMISS] = vaddr;
+
+		msr |= PPC_MSR_TGPR;
+		reg_access_msr(cpu, &msr, 1, 0);
+
+		ppc_exception(cpu, instr? 0x10 : (writeflag? 0x12 : 0x11));
+	} else {
+		if (!instr) {
+			cpu->cd.ppc.spr[SPR_DAR] = vaddr;
+			cpu->cd.ppc.spr[SPR_DSISR] = match?
+			    DSISR_PROTECT : DSISR_NOTFOUND;
+			if (writeflag)
+				cpu->cd.ppc.spr[SPR_DSISR] |= DSISR_STORE;
+		}
+		ppc_exception(cpu, instr?
+		    PPC_EXCEPTION_ISI : PPC_EXCEPTION_DSI);
+	}
+
+	return 0;
+}
+
diff -Nru gxemul-0.6.2/src/cpus/memory_ppc.cc gxemul-0.7.0+dfsg/src/cpus/memory_ppc.cc
--- gxemul-0.6.2/src/cpus/memory_ppc.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_ppc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,298 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Included from cpu_ppc.c.
- */
-
-
-/*
- *  ppc_bat():
- *
- *  BAT translation. Returns -1 if there was no BAT hit, >= 0 for a hit.
- *  (0 for access denied, 1 for read-only, and 2 for read-write access allowed.)
- */
-int ppc_bat(struct cpu *cpu, uint64_t vaddr, uint64_t *return_paddr, int flags,
-	int user)
-{
-	int i, istart = 0, iend = 8, pp;
-
-	if (flags & FLAG_INSTR)
-		iend = 4;
-	else
-		istart = 4;
-
-	if (cpu->cd.ppc.bits != 32) {
-		fatal("TODO: ppc_bat() for non-32-bit\n");
-		exit(1);
-	}
-	if (cpu->cd.ppc.cpu_type.flags & PPC_601) {
-		fatal("TODO: ppc_bat() for PPC 601\n");
-		exit(1);
-	}
-
-	/*  Scan either the 4 instruction BATs or the 4 data BATs:  */
-	for (i=istart; i<iend; i++) {
-		int regnr = SPR_IBAT0U + i * 2;
-		uint32_t upper = cpu->cd.ppc.spr[regnr];
-		uint32_t lower = cpu->cd.ppc.spr[regnr + 1];
-		uint32_t phys = lower & BAT_RPN, ebs = upper & BAT_EPI;
-		uint32_t mask = ((upper & BAT_BL) << 15) | 0x1ffff;
-
-		/*  Not valid in either supervisor or user mode?  */
-		if (user && !(upper & BAT_Vu))
-			continue;
-		if (!user && !(upper & BAT_Vs))
-			continue;
-
-		/*  Virtual address mismatch? Then skip.  */
-		if ((vaddr & ~mask) != (ebs & ~mask))
-			continue;
-
-		*return_paddr = (vaddr & mask) | (phys & ~mask);
-
-		pp = lower & BAT_PP;
-		switch (pp) {
-		case BAT_PP_NONE:
-			return 0;
-		case BAT_PP_RO_S:
-		case BAT_PP_RO:
-			return (flags & FLAG_WRITEFLAG)? 0 : 1;
-		default:/*  BAT_PP_RW:  */
-			return 2;
-		}
-	}
-
-	return -1;
-}
-
-
-/*
- *  get_pte_low():
- *
- *  Scan a PTE group for a cmp (compare) value.
- *
- *  Returns 1 if the value was found, and *lowp is set to the low PTE word.
- *  Returns 0 if no match was found.
- */
-static int get_pte_low(struct cpu *cpu, uint64_t pteg_select,
-	uint32_t *lowp, uint32_t cmp)
-{
-	unsigned char *d = memory_paddr_to_hostaddr(cpu->mem, pteg_select, 1);
-	int i;
-
-	for (i=0; i<8; i++) {
-		uint32_t *ep = (uint32_t *) (d + (i << 3)), upper;
-		upper = *ep;
-		upper = BE32_TO_HOST(upper);
-
-		/*  Valid PTE, and correct api and vsid?  */
-		if (upper == cmp) {
-			uint32_t lo = ep[1];
-			lo = BE32_TO_HOST(lo);
-			*lowp = lo;
-			return 1;
-		}
-	}
-
-	return 0;
-}
-
-
-/*
- *  ppc_vtp32():
- *
- *  Virtual to physical address translation (32-bit mode).
- *
- *  Returns 1 if a translation was found, 0 if none was found. However, finding
- *  a translation does not mean that it should be returned; there can be
- *  a permission violation. *resp is set to 0 for no access, 1 for read-only
- *  access, or 2 for read/write access.
- */
-static int ppc_vtp32(struct cpu *cpu, uint32_t vaddr, uint64_t *return_paddr,
-	int *resp, uint64_t msr, int writeflag, int instr)
-{
-	int srn = (vaddr >> 28) & 15, api = (vaddr >> 22) & PTE_API;
-	int access, key, match;
-	uint32_t vsid = cpu->cd.ppc.sr[srn] & 0x00ffffff;
-	uint64_t sdr1 = cpu->cd.ppc.spr[SPR_SDR1], htaborg;
-	uint32_t hash1, hash2, pteg_select, tmp;
-	uint32_t lower_pte = 0, cmp;
-
-	htaborg = sdr1 & 0xffff0000UL;
-
-	/*  Primary hash:  */
-	hash1 = (vsid & 0x7ffff) ^ ((vaddr >> 12) & 0xffff);
-	tmp = (hash1 >> 10) & (sdr1 & 0x1ff);
-	pteg_select = htaborg & 0xfe000000;
-	pteg_select |= ((hash1 & 0x3ff) << 6);
-	pteg_select |= (htaborg & 0x01ff0000) | (tmp << 16);
-	cpu->cd.ppc.spr[SPR_HASH1] = pteg_select;
-	cmp = cpu->cd.ppc.spr[instr? SPR_ICMP : SPR_DCMP] =
-	    PTE_VALID | api | (vsid << PTE_VSID_SHFT);
-	match = get_pte_low(cpu, pteg_select, &lower_pte, cmp);
-
-	/*  Secondary hash:  */
-	hash2 = hash1 ^ 0x7ffff;
-	tmp = (hash2 >> 10) & (sdr1 & 0x1ff);
-	pteg_select = htaborg & 0xfe000000;
-	pteg_select |= ((hash2 & 0x3ff) << 6);
-	pteg_select |= (htaborg & 0x01ff0000) | (tmp << 16);
-	cpu->cd.ppc.spr[SPR_HASH2] = pteg_select;
-	if (!match) {
-		cmp |= PTE_HID;
-		match = get_pte_low(cpu, pteg_select, &lower_pte, cmp);
-	}
-
-	*resp = 0;
-
-	if (!match)
-		return 0;
-
-	/*  Non-executable, or Guarded page?  */
-	if (instr && cpu->cd.ppc.sr[srn] & SR_NOEXEC)
-		return 1;
-	if (instr && lower_pte & PTE_G)
-		return 1;
-
-	access = lower_pte & PTE_PP;
-	*return_paddr = (lower_pte & PTE_RPGN) | (vaddr & ~PTE_RPGN);
-
-	key = (cpu->cd.ppc.sr[srn] & SR_PRKEY && msr & PPC_MSR_PR) ||
-	    (cpu->cd.ppc.sr[srn] & SR_SUKEY && !(msr & PPC_MSR_PR));
-
-	if (key) {
-		switch (access) {
-		case 1:
-		case 3:	*resp = writeflag? 0 : 1;
-			break;
-		case 2:	*resp = 2;
-			break;
-		}
-	} else {
-		switch (access) {
-		case 3:	*resp = writeflag? 0 : 1;
-			break;
-		default:*resp = 2;
-		}
-	}
-
-	return 1;
-}
-
-
-/*
- *  ppc_translate_v2p():
- *
- *  Return values:
- *	0  Failure
- *	1  Success, the page is readable only
- *	2  Success, the page is read/write
- */
-int ppc_translate_v2p(struct cpu *cpu, uint64_t vaddr,
-	uint64_t *return_paddr, int flags)
-{
-	int instr = flags & FLAG_INSTR, res = 0, match, user;
-	int writeflag = flags & FLAG_WRITEFLAG? 1 : 0;
-	uint64_t msr;
-
-	reg_access_msr(cpu, &msr, 0, 0);
-	user = msr & PPC_MSR_PR? 1 : 0;
-
-	if (cpu->cd.ppc.bits == 32)
-		vaddr &= 0xffffffff;
-
-	if ((instr && !(msr & PPC_MSR_IR)) || (!instr && !(msr & PPC_MSR_DR))) {
-		*return_paddr = vaddr;
-		return 2;
-	}
-
-	if (cpu->cd.ppc.cpu_type.flags & PPC_601) {
-		fatal("ppc_translate_v2p(): TODO: 601\n");
-		exit(1);
-	}
-
-	/*  Try the BATs first:  */
-	if (cpu->cd.ppc.bits == 32) {
-		res = ppc_bat(cpu, vaddr, return_paddr, flags, user);
-		if (res > 0)
-			return res;
-		if (res == 0) {
-			fatal("[ TODO: BAT exception ]\n");
-			exit(1);
-		}
-	}
-
-	/*  Virtual to physical translation:  */
-	if (cpu->cd.ppc.bits == 32) {
-		match = ppc_vtp32(cpu, vaddr, return_paddr, &res, msr,
-		    writeflag, instr);
-		if (match && res > 0)
-			return res;
-	} else {
-		/*  htaborg = sdr1 & 0xfffffffffffc0000ULL;  */
-		fatal("TODO: ppc 64-bit translation\n");
-		exit(1);
-	}
-
-
-	/*
-	 *  No match? Then cause an exception.
-	 *
-	 *  PPC603: cause a software TLB reload exception.
-	 *  All others: cause a DSI or ISI.
-	 */
-
-	if (flags & FLAG_NOEXCEPTIONS)
-		return 0;
-
-	if (!quiet_mode)
-		fatal("[ memory_ppc: exception! vaddr=0x%" PRIx64" pc=0x%" PRIx64
-		    " instr=%i user=%i wf=%i ]\n", (uint64_t) vaddr,
-		    (uint64_t) cpu->pc, instr, user, writeflag);
-
-	if (cpu->cd.ppc.cpu_type.flags & PPC_603) {
-		cpu->cd.ppc.spr[instr? SPR_IMISS : SPR_DMISS] = vaddr;
-
-		msr |= PPC_MSR_TGPR;
-		reg_access_msr(cpu, &msr, 1, 0);
-
-		ppc_exception(cpu, instr? 0x10 : (writeflag? 0x12 : 0x11));
-	} else {
-		if (!instr) {
-			cpu->cd.ppc.spr[SPR_DAR] = vaddr;
-			cpu->cd.ppc.spr[SPR_DSISR] = match?
-			    DSISR_PROTECT : DSISR_NOTFOUND;
-			if (writeflag)
-				cpu->cd.ppc.spr[SPR_DSISR] |= DSISR_STORE;
-		}
-		ppc_exception(cpu, instr?
-		    PPC_EXCEPTION_ISI : PPC_EXCEPTION_DSI);
-	}
-
-	return 0;
-}
-
diff -Nru gxemul-0.6.2/src/cpus/memory_rw.c gxemul-0.7.0+dfsg/src/cpus/memory_rw.c
--- gxemul-0.6.2/src/cpus/memory_rw.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_rw.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,530 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Generic memory_rw(), with special hacks for specific CPU families.
+ *
+ *  Example for inclusion from memory_mips.c:
+ *
+ *	MEMORY_RW should be mips_memory_rw
+ *	MEM_MIPS should be defined
+ *
+ *
+ *  TODO: Cleanup the "ok" variable usage!
+ */
+
+
+/*
+ *  memory_rw():
+ *
+ *  Read or write data from/to memory.
+ *
+ *	cpu		the cpu doing the read/write
+ *	mem		the memory object to use
+ *	vaddr		the virtual address
+ *	data		a pointer to the data to be written to memory, or
+ *			a placeholder for data when reading from memory
+ *	len		the length of the 'data' buffer
+ *	writeflag	set to MEM_READ or MEM_WRITE
+ *	misc_flags	CACHE_{NONE,DATA,INSTRUCTION} | other flags
+ *
+ *  If the address indicates access to a memory mapped device, that device'
+ *  read/write access function is called.
+ *
+ *  This function should not be called with cpu == NULL.
+ *
+ *  Returns one of the following:
+ *	MEMORY_ACCESS_FAILED
+ *	MEMORY_ACCESS_OK
+ *
+ *  (MEMORY_ACCESS_FAILED is 0.)
+ */
+int MEMORY_RW(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
+	unsigned char *data, size_t len, int writeflag, int misc_flags)
+{
+#ifdef MEM_ALPHA
+	const int offset_mask = 0x1fff;
+#else
+	const int offset_mask = 0xfff;
+#endif
+
+	int ok = 2;
+	uint64_t paddr;
+	int cache, no_exceptions, offset;
+	unsigned char *memblock;
+	int dyntrans_device_danger = 0;
+
+	no_exceptions = misc_flags & NO_EXCEPTIONS;
+	cache = misc_flags & CACHE_FLAGS_MASK;
+
+
+	if (misc_flags & PHYSICAL || cpu->translate_v2p == NULL) {
+		paddr = vaddr;
+	} else {
+		ok = cpu->translate_v2p(cpu, vaddr, &paddr,
+		    (writeflag? FLAG_WRITEFLAG : 0) +
+		    (no_exceptions? FLAG_NOEXCEPTIONS : 0)
+		    + (misc_flags & MEMORY_USER_ACCESS)
+		    + (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0));
+
+		/*
+		 *  If the translation caused an exception, or was invalid in
+		 *  some way, then simply return without doing the memory
+		 *  access:
+		 */
+		if (!ok)
+			return MEMORY_ACCESS_FAILED;
+	}
+
+#if 0
+	/*
+	 *  For quick-and-dirty debugging of 32-bit code, typically
+	 *  unknown ROM code:  Write out a summary of accessed memory ranges.
+	 */
+	if (cpu->running && paddr < 0x00300000)
+	{
+		static int swriteflag = -1, lastswriteflag;
+		static int32_t start = -1, stop = -1;
+		static int32_t laststart = -1, laststop = -1;
+
+		if (start == -1)
+		{
+			start = stop = paddr;
+			swriteflag = writeflag;
+		}
+		else
+		{
+			if (paddr == stop + len && writeflag == swriteflag)
+			{
+				stop = paddr;
+			}
+			else
+			{
+				if (start != laststart || stop != laststop || swriteflag != lastswriteflag)
+				{
+					printf("%s  %08x -- %08x  %i-bit\n",
+						swriteflag ? "WRITE" : "READ ",
+						(int)start, (int)(stop + len - 1), (int)len*8);
+				}
+
+				laststart = start; laststop = stop; lastswriteflag = swriteflag;
+
+				start = stop = paddr;
+				swriteflag = writeflag;
+			}
+		}
+
+		// Make sure the access is not put into quick lookup tables:
+		ok |= MEMORY_NOT_FULL_PAGE;
+	}
+#endif
+
+#if 0
+	/*
+	 *  For quick-and-dirty test to see which memory addresses are in use,
+	 *  making a "waterfall spectrum"...
+	 */
+	if (cpu->running && (paddr < 0x200000 ||
+		(paddr >= 0x0c000000 && paddr < 0x0d000000)))
+	{
+		int64_t xsize = 1920, ysize = 1080;
+		static int y = 0;
+		static int count = 0;
+		static uint8_t* buf = NULL;
+
+		if (buf == NULL)
+		{
+			buf = (uint8_t*)malloc(xsize * ysize*3);
+			memset(buf, 0xff, xsize * ysize*3);
+		}
+
+		uint64_t paddr2 = paddr - 0x0c000000;
+		
+		if (paddr < 0x200000)
+			paddr2 = paddr + 16*1048576;
+
+		int64_t max = 16*1048576 + (2*1048576);
+
+		int64_t x = xsize * paddr2 / max;
+
+		if (x >= 0 && x < xsize)
+		{
+			if (writeflag)
+			{
+				int c = buf[(x+y*xsize)*3+0];
+				if (c == 255)
+					c = 128;
+				else if (c > 0)
+				{
+					c = c - 8;
+				}
+
+				buf[(x+y*xsize)*3+1] = c;
+				buf[(x+y*xsize)*3+2] = c;
+			}
+			else
+			{
+				int c = buf[(x+y*xsize)*3+1];
+				if (c == 255)
+					c = 128;
+				else if (c > 0)
+				{
+					c = c - 8;
+				}
+
+				buf[(x+y*xsize)*3+0] = c;
+				buf[(x+y*xsize)*3+2] = c;
+			}
+		}
+		
+		for (int meg = 0; meg < 18; ++meg)
+			buf[((xsize * (meg * 0x100000LL) / max) +y*xsize)*3+1] = 64;
+
+		count ++;
+		if (count >= 8192)
+		{
+			count = 0;
+			y ++;
+			
+			if (y >= ysize)
+			{
+				static int n = 0;
+				char name[40];
+				snprintf(name, sizeof(name), "memory_%05i.ppm", n++);
+				FILE* f = fopen(name, "w");
+				printf("writing out %s\n", name);
+				fprintf(f, "P6\n%i %i\n255\n", (int)xsize, (int)ysize);
+				fwrite((char*)buf, 1, (int)(xsize*ysize*3), f);
+				fclose(f);
+				memset(buf, 0xff, xsize*ysize);
+				y = 0;
+			}
+		}
+		
+		// Make sure the access is not put into quick lookup tables:
+		ok |= MEMORY_NOT_FULL_PAGE;
+	}
+#endif
+
+	/*
+	 *  Memory mapped device?
+	 *
+	 *  TODO: if paddr < base, but len enough, then the device should
+	 *  still be written to!
+	 */
+	if (paddr >= mem->mmap_dev_minaddr && paddr < mem->mmap_dev_maxaddr) {
+		uint64_t orig_paddr = paddr;
+		int i, start, end, res;
+
+#if 0
+
+TODO: The correct solution for this is to add RAM devices _around_ the
+dangerous device. The solution below incurs a slowdown for _everything_,
+not just the device in question.
+
+		/*
+		 *  Really really slow, but unfortunately necessary. This is
+		 *  to avoid the folowing scenario:
+		 *
+		 *	a) offsets 0x000..0x123 are normal memory
+		 *	b) offsets 0x124..0x777 are a device
+		 *
+		 *	1) a read is done from offset 0x100. the page is
+		 *	   added to the dyntrans system as a "RAM" page
+		 *	2) a dyntranslated read is done from offset 0x200,
+		 *	   which should access the device, but since the
+		 *	   entire page is added, it will access non-existant
+		 *	   RAM instead, without warning.
+		 *
+		 *  Setting dyntrans_device_danger = 1 on accesses which are
+		 *  on _any_ offset on pages that are device mapped avoids
+		 *  this problem, but it is probably not very fast.
+		 *
+		 *  TODO: Convert this into a quick (multi-level, 64-bit)
+		 *  address space lookup, to find dangerous pages.
+		 */
+		for (i=0; i<mem->n_mmapped_devices; i++)
+			if (paddr >= (mem->devices[i].baseaddr & ~offset_mask)&&
+			    paddr <= ((mem->devices[i].endaddr-1)|offset_mask)){
+				dyntrans_device_danger = 1;
+				break;
+			}
+#endif
+
+		start = 0; end = mem->n_mmapped_devices - 1;
+		i = mem->last_accessed_device;
+
+		/*  Scan through all devices:  */
+		do {
+			if (paddr >= mem->devices[i].baseaddr &&
+			    paddr < mem->devices[i].endaddr) {
+				/*  Found a device, let's access it:  */
+				mem->last_accessed_device = i;
+
+				paddr -= mem->devices[i].baseaddr;
+				if (paddr + len > mem->devices[i].length)
+					len = mem->devices[i].length - paddr;
+
+				if (cpu->update_translation_table != NULL &&
+				    !(ok & MEMORY_NOT_FULL_PAGE) &&
+				    mem->devices[i].flags & DM_DYNTRANS_OK) {
+					int wf = writeflag == MEM_WRITE? 1 : 0;
+					unsigned char *host_addr;
+
+					if (!(mem->devices[i].flags &
+					    DM_DYNTRANS_WRITE_OK))
+						wf = 0;
+
+					if (writeflag && wf) {
+						if (paddr < mem->devices[i].
+						    dyntrans_write_low)
+							mem->devices[i].
+							dyntrans_write_low =
+							    paddr &~offset_mask;
+						if (paddr >= mem->devices[i].
+						    dyntrans_write_high)
+							mem->devices[i].
+						 	dyntrans_write_high =
+							    paddr | offset_mask;
+					}
+
+					if (mem->devices[i].flags &
+					    DM_EMULATED_RAM) {
+						/*  MEM_WRITE to force the page
+						    to be allocated, if it
+						    wasn't already  */
+						uint64_t *pp = (uint64_t *)mem->
+						    devices[i].dyntrans_data;
+						uint64_t p = orig_paddr - *pp;
+						host_addr =
+						    memory_paddr_to_hostaddr(
+						    mem, p & ~offset_mask,
+						    MEM_WRITE);
+					} else {
+						host_addr = mem->devices[i].
+						    dyntrans_data +
+						    (paddr & ~offset_mask);
+					}
+
+					cpu->update_translation_table(cpu,
+					    vaddr & ~offset_mask, host_addr,
+					    wf, orig_paddr & ~offset_mask);
+				}
+
+				res = 0;
+				if (!no_exceptions || (mem->devices[i].flags &
+				    DM_READS_HAVE_NO_SIDE_EFFECTS)) {
+					bool running_before_device_access = cpu->running;
+					res = mem->devices[i].f(cpu, mem, paddr,
+					    data, len, writeflag,
+					    mem->devices[i].extra);
+
+					if (running_before_device_access && !cpu->running)
+						return MEMORY_ACCESS_FAILED;
+				}
+
+				if (res == 0)
+					res = -1;
+
+				/*
+				 *  If accessing the memory mapped device
+				 *  failed, then return with an exception.
+				 *  (Architecture specific.)
+				 */
+				if (res <= 0 && !no_exceptions) {
+					debug("[ %s device '%s' addr %08lx "
+					    "failed ]\n", writeflag?
+					    "writing to" : "reading from",
+					    mem->devices[i].name, (long)paddr);
+#ifdef MEM_MIPS
+					mips_cpu_exception(cpu,
+					    cache == CACHE_INSTRUCTION?
+					    EXCEPTION_IBE : EXCEPTION_DBE,
+					    0, vaddr, 0, 0, 0, 0);
+#endif
+#ifdef MEM_M88K
+					/*  TODO: This is enough for
+					    OpenBSD/mvme88k's badaddr()
+					    implementation... but the
+					    faulting address should probably
+					    be included somewhere too!  */
+					m88k_exception(cpu, cache == CACHE_INSTRUCTION
+					    ? M88K_EXCEPTION_INSTRUCTION_ACCESS
+					    : M88K_EXCEPTION_DATA_ACCESS, 0);
+#endif
+					return MEMORY_ACCESS_FAILED;
+				}
+				goto do_return_ok;
+			}
+
+			if (paddr < mem->devices[i].baseaddr)
+				end = i - 1;
+			if (paddr >= mem->devices[i].endaddr)
+				start = i + 1;
+			i = (start + end) >> 1;
+		} while (start <= end);
+	}
+
+
+#ifdef MEM_MIPS
+	/*
+	 *  Data and instruction cache emulation:
+	 */
+
+	switch (cpu->cd.mips.cpu_type.mmu_model) {
+	case MMU3K:
+		/*  if not uncached addess  (TODO: generalize this)  */
+		if (!(misc_flags & PHYSICAL) && cache != CACHE_NONE &&
+		    !((vaddr & 0xffffffffULL) >= 0xa0000000ULL &&
+		      (vaddr & 0xffffffffULL) <= 0xbfffffffULL)) {
+			if (memory_cache_R3000(cpu, cache, paddr,
+			    writeflag, len, data))
+				goto do_return_ok;
+		}
+		break;
+	default:
+		/*  R4000 etc  */
+		/*  TODO  */
+		;
+	}
+#endif	/*  MEM_MIPS  */
+
+
+	/*  Outside of physical RAM?  */
+	if (paddr >= mem->physical_max) {
+#ifdef MEM_MIPS
+		if ((paddr & 0xffffc00000ULL) == 0x1fc00000) {
+			/*  Ok, this is PROM stuff  */
+		} else if ((paddr & 0xfffff00000ULL) == 0x1ff00000) {
+			/*  Sprite reads from this area of memory...  */
+			/*  TODO: is this still correct?  */
+			if (writeflag == MEM_READ)
+				memset(data, 0, len);
+			goto do_return_ok;
+		} else
+#endif /* MIPS */
+		{
+			if (paddr >= mem->physical_max && !no_exceptions)
+				if (memory_warn_about_unimplemented_addr
+				    (cpu, mem, writeflag, paddr, len))
+					return MEMORY_ACCESS_FAILED;
+
+			if (writeflag == MEM_READ) {
+				/*  Return all zeroes? (Or 0xff? TODO)  */
+				memset(data, 0, len);
+
+#if 0
+/*
+ *  NOTE: This code prevents a PROM image from a real 5000/200 from booting.
+ *  I think I introduced it because it was how some guest OS (NetBSD?) detected
+ *  the amount of RAM on some machine.
+ *
+ *  TODO: Figure out if it is not needed anymore, and remove it completely.
+ */
+#ifdef MEM_MIPS
+				/*
+				 *  For real data/instruction accesses, cause
+				 *  an exceptions on an illegal read:
+				 */
+				if (cache != CACHE_NONE && !no_exceptions &&
+				    paddr >= mem->physical_max &&
+				    paddr < mem->physical_max+1048576) {
+					mips_cpu_exception(cpu,
+					    EXCEPTION_DBE, 0, vaddr, 0,
+					    0, 0, 0);
+				}
+#endif  /*  MEM_MIPS  */
+#endif
+			}
+
+			/*  Hm? Shouldn't there be a DBE exception for
+			    invalid writes as well?  TODO  */
+
+			goto do_return_ok;
+		}
+	}
+
+
+	/*
+	 *  Uncached access:
+	 *
+	 *  1)  Translate the physical address to a host address.
+	 *
+	 *  2)  Insert this virtual->physical->host translation into the
+	 *      fast translation arrays (using update_translation_table()).
+	 *
+	 *  3)  If this was a Write, then invalidate any code translations
+	 *      in that page.
+	 */
+	memblock = memory_paddr_to_hostaddr(mem, paddr & ~offset_mask,
+	    writeflag);
+	if (memblock == NULL) {
+		if (writeflag == MEM_READ)
+			memset(data, 0, len);
+		goto do_return_ok;
+	}
+
+	offset = paddr & offset_mask;
+
+	if (cpu->update_translation_table != NULL && !dyntrans_device_danger
+#ifdef MEM_MIPS
+	    /*  Ugly hack for R2000/R3000 caches:  */
+	    && (cpu->cd.mips.cpu_type.mmu_model != MMU3K ||
+            !(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES))
+#endif
+	    && !(ok & MEMORY_NOT_FULL_PAGE)
+	    && !no_exceptions)
+		cpu->update_translation_table(cpu, vaddr & ~offset_mask,
+		    memblock, (misc_flags & MEMORY_USER_ACCESS) |
+		    (cache == CACHE_INSTRUCTION?
+			(writeflag == MEM_WRITE? 1 : 0) : ok - 1),
+		    paddr & ~offset_mask);
+
+	/*
+	 *  If writing, or if mapping a page where writing is ok later on,
+	 *  then invalidate code translations for the (physical) page address:
+	 */
+
+	if ((writeflag == MEM_WRITE
+	    || (ok == 2 && cache == CACHE_DATA)
+	    ) && cpu->invalidate_code_translation != NULL)
+		cpu->invalidate_code_translation(cpu, paddr, INVALIDATE_PADDR);
+
+	if ((paddr&((1<<BITS_PER_MEMBLOCK)-1)) + len > (1<<BITS_PER_MEMBLOCK)) {
+		printf("Write over memblock boundary?\n");
+		exit(1);
+	}
+
+	/*  And finally, read or write the data:  */
+	if (writeflag == MEM_WRITE)
+		memcpy(memblock + offset, data, len);
+	else
+		memcpy(data, memblock + offset, len);
+
+do_return_ok:
+	return MEMORY_ACCESS_OK;
+}
+
diff -Nru gxemul-0.6.2/src/cpus/memory_rw.cc gxemul-0.7.0+dfsg/src/cpus/memory_rw.cc
--- gxemul-0.6.2/src/cpus/memory_rw.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_rw.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,524 +0,0 @@
-/*
- *  Copyright (C) 2003-2014  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Generic memory_rw(), with special hacks for specific CPU families.
- *
- *  Example for inclusion from memory_mips.c:
- *
- *	MEMORY_RW should be mips_memory_rw
- *	MEM_MIPS should be defined
- *
- *
- *  TODO: Cleanup the "ok" variable usage!
- */
-
-
-/*
- *  memory_rw():
- *
- *  Read or write data from/to memory.
- *
- *	cpu		the cpu doing the read/write
- *	mem		the memory object to use
- *	vaddr		the virtual address
- *	data		a pointer to the data to be written to memory, or
- *			a placeholder for data when reading from memory
- *	len		the length of the 'data' buffer
- *	writeflag	set to MEM_READ or MEM_WRITE
- *	misc_flags	CACHE_{NONE,DATA,INSTRUCTION} | other flags
- *
- *  If the address indicates access to a memory mapped device, that device'
- *  read/write access function is called.
- *
- *  This function should not be called with cpu == NULL.
- *
- *  Returns one of the following:
- *	MEMORY_ACCESS_FAILED
- *	MEMORY_ACCESS_OK
- *
- *  (MEMORY_ACCESS_FAILED is 0.)
- */
-int MEMORY_RW(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
-	unsigned char *data, size_t len, int writeflag, int misc_flags)
-{
-#ifdef MEM_ALPHA
-	const int offset_mask = 0x1fff;
-#else
-	const int offset_mask = 0xfff;
-#endif
-
-	int ok = 2;
-	uint64_t paddr;
-	int cache, no_exceptions, offset;
-	unsigned char *memblock;
-	int dyntrans_device_danger = 0;
-
-	no_exceptions = misc_flags & NO_EXCEPTIONS;
-	cache = misc_flags & CACHE_FLAGS_MASK;
-
-
-	if (misc_flags & PHYSICAL || cpu->translate_v2p == NULL) {
-		paddr = vaddr;
-	} else {
-		ok = cpu->translate_v2p(cpu, vaddr, &paddr,
-		    (writeflag? FLAG_WRITEFLAG : 0) +
-		    (no_exceptions? FLAG_NOEXCEPTIONS : 0)
-		    + (misc_flags & MEMORY_USER_ACCESS)
-		    + (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0));
-
-		/*
-		 *  If the translation caused an exception, or was invalid in
-		 *  some way, then simply return without doing the memory
-		 *  access:
-		 */
-		if (!ok)
-			return MEMORY_ACCESS_FAILED;
-	}
-
-#if 0
-	/*
-	 *  For quick-and-dirty debugging of 32-bit code, typically
-	 *  unknown ROM code:  Write out a summary of accessed memory ranges.
-	 */
-	if (cpu->running && paddr < 0x00300000)
-	{
-		static int swriteflag = -1, lastswriteflag;
-		static int32_t start = -1, stop = -1;
-		static int32_t laststart = -1, laststop = -1;
-
-		if (start == -1)
-		{
-			start = stop = paddr;
-			swriteflag = writeflag;
-		}
-		else
-		{
-			if (paddr == stop + len && writeflag == swriteflag)
-			{
-				stop = paddr;
-			}
-			else
-			{
-				if (start != laststart || stop != laststop || swriteflag != lastswriteflag)
-				{
-					printf("%s  %08x -- %08x  %i-bit\n",
-						swriteflag ? "WRITE" : "READ ",
-						(int)start, (int)(stop + len - 1), (int)len*8);
-				}
-
-				laststart = start; laststop = stop; lastswriteflag = swriteflag;
-
-				start = stop = paddr;
-				swriteflag = writeflag;
-			}
-		}
-
-		// Make sure the access is not put into quick lookup tables:
-		ok |= MEMORY_NOT_FULL_PAGE;
-	}
-#endif
-
-#if 0
-	/*
-	 *  For quick-and-dirty test to see which memory addresses are in use,
-	 *  making a "waterfall spectrum"...
-	 */
-	if (cpu->running && (paddr < 0x200000 ||
-		(paddr >= 0x0c000000 && paddr < 0x0d000000)))
-	{
-		int64_t xsize = 1920, ysize = 1080;
-		static int y = 0;
-		static int count = 0;
-		static uint8_t* buf = NULL;
-
-		if (buf == NULL)
-		{
-			buf = (uint8_t*)malloc(xsize * ysize*3);
-			memset(buf, 0xff, xsize * ysize*3);
-		}
-
-		uint64_t paddr2 = paddr - 0x0c000000;
-		
-		if (paddr < 0x200000)
-			paddr2 = paddr + 16*1048576;
-
-		int64_t max = 16*1048576 + (2*1048576);
-
-		int64_t x = xsize * paddr2 / max;
-
-		if (x >= 0 && x < xsize)
-		{
-			if (writeflag)
-			{
-				int c = buf[(x+y*xsize)*3+0];
-				if (c == 255)
-					c = 128;
-				else if (c > 0)
-				{
-					c = c - 8;
-				}
-
-				buf[(x+y*xsize)*3+1] = c;
-				buf[(x+y*xsize)*3+2] = c;
-			}
-			else
-			{
-				int c = buf[(x+y*xsize)*3+1];
-				if (c == 255)
-					c = 128;
-				else if (c > 0)
-				{
-					c = c - 8;
-				}
-
-				buf[(x+y*xsize)*3+0] = c;
-				buf[(x+y*xsize)*3+2] = c;
-			}
-		}
-		
-		for (int meg = 0; meg < 18; ++meg)
-			buf[((xsize * (meg * 0x100000LL) / max) +y*xsize)*3+1] = 64;
-
-		count ++;
-		if (count >= 8192)
-		{
-			count = 0;
-			y ++;
-			
-			if (y >= ysize)
-			{
-				static int n = 0;
-				char name[40];
-				snprintf(name, sizeof(name), "memory_%05i.ppm", n++);
-				FILE* f = fopen(name, "w");
-				printf("writing out %s\n", name);
-				fprintf(f, "P6\n%i %i\n255\n", (int)xsize, (int)ysize);
-				fwrite((char*)buf, 1, (int)(xsize*ysize*3), f);
-				fclose(f);
-				memset(buf, 0xff, xsize*ysize);
-				y = 0;
-			}
-		}
-		
-		// Make sure the access is not put into quick lookup tables:
-		ok |= MEMORY_NOT_FULL_PAGE;
-	}
-#endif
-
-	/*
-	 *  Memory mapped device?
-	 *
-	 *  TODO: if paddr < base, but len enough, then the device should
-	 *  still be written to!
-	 */
-	if (paddr >= mem->mmap_dev_minaddr && paddr < mem->mmap_dev_maxaddr) {
-		uint64_t orig_paddr = paddr;
-		int i, start, end, res;
-
-#if 0
-
-TODO: The correct solution for this is to add RAM devices _around_ the
-dangerous device. The solution below incurs a slowdown for _everything_,
-not just the device in question.
-
-		/*
-		 *  Really really slow, but unfortunately necessary. This is
-		 *  to avoid the folowing scenario:
-		 *
-		 *	a) offsets 0x000..0x123 are normal memory
-		 *	b) offsets 0x124..0x777 are a device
-		 *
-		 *	1) a read is done from offset 0x100. the page is
-		 *	   added to the dyntrans system as a "RAM" page
-		 *	2) a dyntranslated read is done from offset 0x200,
-		 *	   which should access the device, but since the
-		 *	   entire page is added, it will access non-existant
-		 *	   RAM instead, without warning.
-		 *
-		 *  Setting dyntrans_device_danger = 1 on accesses which are
-		 *  on _any_ offset on pages that are device mapped avoids
-		 *  this problem, but it is probably not very fast.
-		 *
-		 *  TODO: Convert this into a quick (multi-level, 64-bit)
-		 *  address space lookup, to find dangerous pages.
-		 */
-		for (i=0; i<mem->n_mmapped_devices; i++)
-			if (paddr >= (mem->devices[i].baseaddr & ~offset_mask)&&
-			    paddr <= ((mem->devices[i].endaddr-1)|offset_mask)){
-				dyntrans_device_danger = 1;
-				break;
-			}
-#endif
-
-		start = 0; end = mem->n_mmapped_devices - 1;
-		i = mem->last_accessed_device;
-
-		/*  Scan through all devices:  */
-		do {
-			if (paddr >= mem->devices[i].baseaddr &&
-			    paddr < mem->devices[i].endaddr) {
-				/*  Found a device, let's access it:  */
-				mem->last_accessed_device = i;
-
-				paddr -= mem->devices[i].baseaddr;
-				if (paddr + len > mem->devices[i].length)
-					len = mem->devices[i].length - paddr;
-
-				if (cpu->update_translation_table != NULL &&
-				    !(ok & MEMORY_NOT_FULL_PAGE) &&
-				    mem->devices[i].flags & DM_DYNTRANS_OK) {
-					int wf = writeflag == MEM_WRITE? 1 : 0;
-					unsigned char *host_addr;
-
-					if (!(mem->devices[i].flags &
-					    DM_DYNTRANS_WRITE_OK))
-						wf = 0;
-
-					if (writeflag && wf) {
-						if (paddr < mem->devices[i].
-						    dyntrans_write_low)
-							mem->devices[i].
-							dyntrans_write_low =
-							    paddr &~offset_mask;
-						if (paddr >= mem->devices[i].
-						    dyntrans_write_high)
-							mem->devices[i].
-						 	dyntrans_write_high =
-							    paddr | offset_mask;
-					}
-
-					if (mem->devices[i].flags &
-					    DM_EMULATED_RAM) {
-						/*  MEM_WRITE to force the page
-						    to be allocated, if it
-						    wasn't already  */
-						uint64_t *pp = (uint64_t *)mem->
-						    devices[i].dyntrans_data;
-						uint64_t p = orig_paddr - *pp;
-						host_addr =
-						    memory_paddr_to_hostaddr(
-						    mem, p & ~offset_mask,
-						    MEM_WRITE);
-					} else {
-						host_addr = mem->devices[i].
-						    dyntrans_data +
-						    (paddr & ~offset_mask);
-					}
-
-					cpu->update_translation_table(cpu,
-					    vaddr & ~offset_mask, host_addr,
-					    wf, orig_paddr & ~offset_mask);
-				}
-
-				res = 0;
-				if (!no_exceptions || (mem->devices[i].flags &
-				    DM_READS_HAVE_NO_SIDE_EFFECTS))
-					res = mem->devices[i].f(cpu, mem, paddr,
-					    data, len, writeflag,
-					    mem->devices[i].extra);
-
-				if (res == 0)
-					res = -1;
-
-				/*
-				 *  If accessing the memory mapped device
-				 *  failed, then return with an exception.
-				 *  (Architecture specific.)
-				 */
-				if (res <= 0 && !no_exceptions) {
-					debug("[ %s device '%s' addr %08lx "
-					    "failed ]\n", writeflag?
-					    "writing to" : "reading from",
-					    mem->devices[i].name, (long)paddr);
-#ifdef MEM_MIPS
-					mips_cpu_exception(cpu,
-					    cache == CACHE_INSTRUCTION?
-					    EXCEPTION_IBE : EXCEPTION_DBE,
-					    0, vaddr, 0, 0, 0, 0);
-#endif
-#ifdef MEM_M88K
-					/*  TODO: This is enough for
-					    OpenBSD/mvme88k's badaddr()
-					    implementation... but the
-					    faulting address should probably
-					    be included somewhere too!  */
-					m88k_exception(cpu, cache == CACHE_INSTRUCTION
-					    ? M88K_EXCEPTION_INSTRUCTION_ACCESS
-					    : M88K_EXCEPTION_DATA_ACCESS, 0);
-#endif
-					return MEMORY_ACCESS_FAILED;
-				}
-				goto do_return_ok;
-			}
-
-			if (paddr < mem->devices[i].baseaddr)
-				end = i - 1;
-			if (paddr >= mem->devices[i].endaddr)
-				start = i + 1;
-			i = (start + end) >> 1;
-		} while (start <= end);
-	}
-
-
-#ifdef MEM_MIPS
-	/*
-	 *  Data and instruction cache emulation:
-	 */
-
-	switch (cpu->cd.mips.cpu_type.mmu_model) {
-	case MMU3K:
-		/*  if not uncached addess  (TODO: generalize this)  */
-		if (!(misc_flags & PHYSICAL) && cache != CACHE_NONE &&
-		    !((vaddr & 0xffffffffULL) >= 0xa0000000ULL &&
-		      (vaddr & 0xffffffffULL) <= 0xbfffffffULL)) {
-			if (memory_cache_R3000(cpu, cache, paddr,
-			    writeflag, len, data))
-				goto do_return_ok;
-		}
-		break;
-	default:
-		/*  R4000 etc  */
-		/*  TODO  */
-		;
-	}
-#endif	/*  MEM_MIPS  */
-
-
-	/*  Outside of physical RAM?  */
-	if (paddr >= mem->physical_max) {
-#ifdef MEM_MIPS
-		if ((paddr & 0xffffc00000ULL) == 0x1fc00000) {
-			/*  Ok, this is PROM stuff  */
-		} else if ((paddr & 0xfffff00000ULL) == 0x1ff00000) {
-			/*  Sprite reads from this area of memory...  */
-			/*  TODO: is this still correct?  */
-			if (writeflag == MEM_READ)
-				memset(data, 0, len);
-			goto do_return_ok;
-		} else
-#endif /* MIPS */
-		{
-			if (paddr >= mem->physical_max && !no_exceptions)
-				memory_warn_about_unimplemented_addr
-				    (cpu, mem, writeflag, paddr, data, len);
-
-			if (writeflag == MEM_READ) {
-				/*  Return all zeroes? (Or 0xff? TODO)  */
-				memset(data, 0, len);
-
-#if 0
-/*
- *  NOTE: This code prevents a PROM image from a real 5000/200 from booting.
- *  I think I introduced it because it was how some guest OS (NetBSD?) detected
- *  the amount of RAM on some machine.
- *
- *  TODO: Figure out if it is not needed anymore, and remove it completely.
- */
-#ifdef MEM_MIPS
-				/*
-				 *  For real data/instruction accesses, cause
-				 *  an exceptions on an illegal read:
-				 */
-				if (cache != CACHE_NONE && !no_exceptions &&
-				    paddr >= mem->physical_max &&
-				    paddr < mem->physical_max+1048576) {
-					mips_cpu_exception(cpu,
-					    EXCEPTION_DBE, 0, vaddr, 0,
-					    0, 0, 0);
-				}
-#endif  /*  MEM_MIPS  */
-#endif
-			}
-
-			/*  Hm? Shouldn't there be a DBE exception for
-			    invalid writes as well?  TODO  */
-
-			goto do_return_ok;
-		}
-	}
-
-
-	/*
-	 *  Uncached access:
-	 *
-	 *  1)  Translate the physical address to a host address.
-	 *
-	 *  2)  Insert this virtual->physical->host translation into the
-	 *      fast translation arrays (using update_translation_table()).
-	 *
-	 *  3)  If this was a Write, then invalidate any code translations
-	 *      in that page.
-	 */
-	memblock = memory_paddr_to_hostaddr(mem, paddr & ~offset_mask,
-	    writeflag);
-	if (memblock == NULL) {
-		if (writeflag == MEM_READ)
-			memset(data, 0, len);
-		goto do_return_ok;
-	}
-
-	offset = paddr & offset_mask;
-
-	if (cpu->update_translation_table != NULL && !dyntrans_device_danger
-#ifdef MEM_MIPS
-	    /*  Ugly hack for R2000/R3000 caches:  */
-	    && (cpu->cd.mips.cpu_type.mmu_model != MMU3K ||
-            !(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES))
-#endif
-	    && !(ok & MEMORY_NOT_FULL_PAGE)
-	    && !no_exceptions)
-		cpu->update_translation_table(cpu, vaddr & ~offset_mask,
-		    memblock, (misc_flags & MEMORY_USER_ACCESS) |
-		    (cache == CACHE_INSTRUCTION?
-			(writeflag == MEM_WRITE? 1 : 0) : ok - 1),
-		    paddr & ~offset_mask);
-
-	/*
-	 *  If writing, or if mapping a page where writing is ok later on,
-	 *  then invalidate code translations for the (physical) page address:
-	 */
-
-	if ((writeflag == MEM_WRITE
-	    || (ok == 2 && cache == CACHE_DATA)
-	    ) && cpu->invalidate_code_translation != NULL)
-		cpu->invalidate_code_translation(cpu, paddr, INVALIDATE_PADDR);
-
-	if ((paddr&((1<<BITS_PER_MEMBLOCK)-1)) + len > (1<<BITS_PER_MEMBLOCK)) {
-		printf("Write over memblock boundary?\n");
-		exit(1);
-	}
-
-	/*  And finally, read or write the data:  */
-	if (writeflag == MEM_WRITE)
-		memcpy(memblock + offset, data, len);
-	else
-		memcpy(data, memblock + offset, len);
-
-do_return_ok:
-	return MEMORY_ACCESS_OK;
-}
-
diff -Nru gxemul-0.6.2/src/cpus/memory_sh.c gxemul-0.7.0+dfsg/src/cpus/memory_sh.c
--- gxemul-0.6.2/src/cpus/memory_sh.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_sh.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,321 @@
+/*
+ *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/sh4_exception.h"
+#include "thirdparty/sh4_mmu.h"
+
+
+/*
+ *  translate_via_mmu():
+ *
+ *  Scan the UTLB for a matching virtual address. If a match was found, then
+ *  check permission bits etc. If everything was ok, then return the physical
+ *  page address, otherwise cause an exception.
+ *
+ *  The implementation should (hopefully) be quite complete, except for lack
+ *  of "Multiple matching entries" detection. (On a real CPU, these would
+ *  cause exceptions.)
+ *
+ *  Same return values as sh_translate_v2p().
+ */
+static int translate_via_mmu(struct cpu *cpu, uint32_t vaddr,
+	uint64_t *return_paddr, int flags)
+{
+	int wf = flags & FLAG_WRITEFLAG;
+	int i, urb, urc, require_asid_match, cur_asid, expevt = 0;
+	uint32_t hi, lo = 0, mask = 0;
+	int sh;		/*  Shared  */
+	int d;		/*  Dirty bit  */
+	int v;		/*  Valid bit  */
+	int pr;		/*  Protection  */
+	int i_start;
+
+	cur_asid = cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK;
+	require_asid_match = !(cpu->cd.sh.mmucr & SH4_MMUCR_SV)
+	    || !(cpu->cd.sh.sr & SH_SR_MD);
+
+	if (!(flags & FLAG_NOEXCEPTIONS)) {
+		/*
+		 *  Increase URC every time the UTLB is accessed. (Note:
+		 *  According to the SH4 manual, the URC should not be
+		 *  increased when running the ldtlb instruction. Perhaps this
+		 *  is a good place? Perhaps it is better to just set it to a
+		 *  random value? TODO: Find out.
+		 */
+		urb = (cpu->cd.sh.mmucr & SH4_MMUCR_URB_MASK) >>
+		    SH4_MMUCR_URB_SHIFT;
+		urc = (cpu->cd.sh.mmucr & SH4_MMUCR_URC_MASK) >>
+		    SH4_MMUCR_URC_SHIFT;
+
+		/*  fatal("urc = %i  ==>  ", urc);  */
+		urc ++;
+		if (urc >= SH_N_UTLB_ENTRIES || (urb > 0 && urc == urb))
+			urc = 0;
+		/*  fatal("%i\n", urc);  */
+
+		cpu->cd.sh.mmucr &= ~SH4_MMUCR_URC_MASK;
+		cpu->cd.sh.mmucr |= (urc << SH4_MMUCR_URC_SHIFT);
+	}
+
+	/*
+	 *  When doing Instruction lookups, the ITLB should be scanned first.
+	 *  This is done by using negative i. (Ugly hack, but works.)
+	 */
+	if (flags & FLAG_INSTR)
+		i_start = -SH_N_ITLB_ENTRIES;
+	else
+		i_start = 0;
+
+	for (i=i_start; i<SH_N_UTLB_ENTRIES; i++) {
+		if (i<0) {
+			hi = cpu->cd.sh.itlb_hi[i + SH_N_ITLB_ENTRIES];
+			lo = cpu->cd.sh.itlb_lo[i + SH_N_ITLB_ENTRIES];
+		} else {
+			hi = cpu->cd.sh.utlb_hi[i];
+			lo = cpu->cd.sh.utlb_lo[i];
+		}
+		mask = 0xfff00000;
+
+		v = lo & SH4_PTEL_V;
+		if (!v)
+			continue;
+
+		switch (lo & SH4_PTEL_SZ_MASK) {
+		case SH4_PTEL_SZ_1K:  mask = 0xfffffc00; break;
+		case SH4_PTEL_SZ_4K:  mask = 0xfffff000; break;
+		case SH4_PTEL_SZ_64K: mask = 0xffff0000; break;
+		/*  case SH4_PTEL_SZ_1M:  mask = 0xfff00000; break;  */
+		}
+
+		if ((hi & mask) != (vaddr & mask))
+			continue;
+
+		sh = lo & SH4_PTEL_SH;
+
+		if (!sh && require_asid_match) {
+			int asid = hi & SH4_PTEH_ASID_MASK;
+			if (asid != cur_asid)
+				continue;
+		}
+
+		/*  Note/TODO: Check for multiple matches is not implemented. */
+
+		break;
+	}
+
+	/*  Virtual address not found? Then it's a TLB miss.  */
+	if (i == SH_N_UTLB_ENTRIES)
+		goto tlb_miss;
+
+	/*  Matching address found! Let's see whether it is
+	    readable/writable, etc.:  */
+	d = lo & SH4_PTEL_D? 1 : 0;
+	pr = (lo & SH4_PTEL_PR_MASK) >> SH4_PTEL_PR_SHIFT;
+
+	*return_paddr = (vaddr & ~mask) | (lo & mask & 0x1fffffff);
+
+	if (flags & FLAG_INSTR) {
+		/*
+		 *  Instruction access:
+		 */
+#if 0
+		/*  NOTE: Emulating the ITLB as exact as this is not
+			necessary... so I'm disabling it for now.  */
+		/*
+		 *  If a matching entry wasn't found in the ITLB, but in the
+		 *  UTLB, then copy it to a random place in the ITLB.
+		 */
+		if (i >= 0 && !(flags & FLAG_NOEXCEPTIONS)) {
+			int r = random() % SH_N_ITLB_ENTRIES;
+
+			/*  NOTE: Make sure that the old mapping for
+			    that itlb entry is invalidated:  */
+			cpu->invalidate_translation_caches(cpu,
+			    cpu->cd.sh.itlb_hi[r] & ~0xfff, INVALIDATE_VADDR);
+
+			cpu->invalidate_code_translation(cpu,
+			    cpu->cd.sh.utlb_lo[i] & ~0xfff, INVALIDATE_PADDR);
+
+			cpu->cd.sh.itlb_hi[r] = cpu->cd.sh.utlb_hi[i];
+			cpu->cd.sh.itlb_lo[r] = cpu->cd.sh.utlb_lo[i];
+		}
+#endif
+
+		/*  Permission checks:  */
+		if (cpu->cd.sh.sr & SH_SR_MD)
+			return 1;
+		if (!(pr & 2))
+			goto protection_violation;
+
+		return 1;
+	}
+
+	/*  Data access:  */
+	if (cpu->cd.sh.sr & SH_SR_MD) {
+		/*  Kernel access:  */
+		switch (pr) {
+		case 0:
+		case 2:	if (wf)
+				goto protection_violation;
+			return 1;
+		case 1:
+		case 3:	if (wf && !d)
+				goto initial_write_exception;
+			return 1 + d;
+		}
+	}
+
+	/*  User access  */
+	switch (pr) {
+	case 0:
+	case 1:	goto protection_violation;
+	case 2:	if (wf)
+			goto protection_violation;
+		return 1;
+	case 3:	if (wf && !d)
+			goto initial_write_exception;
+		return 1 + d;
+	}
+
+
+tlb_miss:
+	expevt = wf? EXPEVT_TLB_MISS_ST : EXPEVT_TLB_MISS_LD;
+	goto exception;
+
+protection_violation:
+	expevt = wf? EXPEVT_TLB_PROT_ST : EXPEVT_TLB_PROT_LD;
+	goto exception;
+
+initial_write_exception:
+	expevt = EXPEVT_TLB_MOD;
+
+
+exception:
+	if (flags & FLAG_NOEXCEPTIONS) {
+		*return_paddr = 0;
+		return 2;
+	}
+
+	sh_exception(cpu, expevt, 0, vaddr);
+
+	return 0;
+}
+
+
+/*
+ *  sh_translate_v2p():
+ *
+ *  Return values:
+ *
+ *	0	No access to the virtual address.
+ *	1	return_paddr contains the physical address, the page is
+ *		available as read-only.
+ *	2	Same as 1, but the page is available as read/write.
+ */
+int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr64, uint64_t *return_paddr,
+	int flags)
+{
+	int user = cpu->cd.sh.sr & SH_SR_MD? 0 : 1;
+	uint32_t vaddr = vaddr64;
+
+	/*  U0/P0: Userspace addresses, or P3: Kernel virtual memory.  */
+	if (!(vaddr & 0x80000000) ||
+	    (vaddr >= 0xc0000000 && vaddr < 0xe0000000)) {
+		/*  Address translation turned off?  */
+		if (!(cpu->cd.sh.mmucr & SH4_MMUCR_AT)) {
+			/*  Then return raw physical address:  */
+			*return_paddr = vaddr & 0x1fffffff;
+			return 2;
+		}
+
+		/*  Perform translation via the MMU:  */
+		return translate_via_mmu(cpu, vaddr, return_paddr, flags);
+	}
+
+	/*  Store queue region:  */
+	if (vaddr >= 0xe0000000 && vaddr < 0xe4000000) {
+		/*  Note/TODO: Take SH4_MMUCR_SQMD into account.  */
+		*return_paddr = vaddr;
+		return 2;
+	}
+
+	if (user) {
+		if (flags & FLAG_NOEXCEPTIONS) {
+			*return_paddr = 0;
+			return 2;
+		}
+
+		// Hopefully correct behavior; nbjoerg on #GXemul (FreeNode)
+		// noticed that this case was easily triggered inside a
+		// guest OS, by:  int main(void){ *(int *)-4 = 0; }
+		sh_exception(cpu, (flags & FLAG_WRITEFLAG)?
+		    EXPEVT_TLB_MISS_ST : EXPEVT_TLB_MISS_LD, 0, vaddr);
+		return 0;
+	}
+
+	/*  P1,P2: Direct-mapped physical memory.  */
+	if (vaddr >= 0x80000000 && vaddr < 0xc0000000) {
+		*return_paddr = vaddr & 0x1fffffff;
+		return 2;
+	}
+
+	if (flags & FLAG_INSTR) {
+		fatal("TODO: instr at 0x%08" PRIx32"\n", (uint32_t)vaddr);
+		exit(1);
+	}
+
+	/*  P4: Special registers mapped at 0xf0000000 .. 0xffffffff:  */
+	if ((vaddr & 0xf0000000) == 0xf0000000) {
+		*return_paddr = vaddr;
+		return 2;
+	}
+
+	if (flags & FLAG_NOEXCEPTIONS) {
+		*return_paddr = 0;
+		return 2;
+	}
+
+	/*  TODO  */
+
+	/*  The ugly 'if' is just here to fool Compaq CC.  */
+	if (!(flags & FLAG_NOEXCEPTIONS)) {
+		fatal("Unimplemented SH vaddr 0x%08" PRIx32"\n", vaddr);
+		exit(1);
+	}
+
+	return 0;
+}
+
diff -Nru gxemul-0.6.2/src/cpus/memory_sh.cc gxemul-0.7.0+dfsg/src/cpus/memory_sh.cc
--- gxemul-0.6.2/src/cpus/memory_sh.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/memory_sh.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,321 +0,0 @@
-/*
- *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/sh4_exception.h"
-#include "thirdparty/sh4_mmu.h"
-
-
-/*
- *  translate_via_mmu():
- *
- *  Scan the UTLB for a matching virtual address. If a match was found, then
- *  check permission bits etc. If everything was ok, then return the physical
- *  page address, otherwise cause an exception.
- *
- *  The implementation should (hopefully) be quite complete, except for lack
- *  of "Multiple matching entries" detection. (On a real CPU, these would
- *  cause exceptions.)
- *
- *  Same return values as sh_translate_v2p().
- */
-static int translate_via_mmu(struct cpu *cpu, uint32_t vaddr,
-	uint64_t *return_paddr, int flags)
-{
-	int wf = flags & FLAG_WRITEFLAG;
-	int i, urb, urc, require_asid_match, cur_asid, expevt = 0;
-	uint32_t hi, lo = 0, mask = 0;
-	int sh;		/*  Shared  */
-	int d;		/*  Dirty bit  */
-	int v;		/*  Valid bit  */
-	int pr;		/*  Protection  */
-	int i_start;
-
-	cur_asid = cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK;
-	require_asid_match = !(cpu->cd.sh.mmucr & SH4_MMUCR_SV)
-	    || !(cpu->cd.sh.sr & SH_SR_MD);
-
-	if (!(flags & FLAG_NOEXCEPTIONS)) {
-		/*
-		 *  Increase URC every time the UTLB is accessed. (Note:
-		 *  According to the SH4 manual, the URC should not be
-		 *  increased when running the ldtlb instruction. Perhaps this
-		 *  is a good place? Perhaps it is better to just set it to a
-		 *  random value? TODO: Find out.
-		 */
-		urb = (cpu->cd.sh.mmucr & SH4_MMUCR_URB_MASK) >>
-		    SH4_MMUCR_URB_SHIFT;
-		urc = (cpu->cd.sh.mmucr & SH4_MMUCR_URC_MASK) >>
-		    SH4_MMUCR_URC_SHIFT;
-
-		/*  fatal("urc = %i  ==>  ", urc);  */
-		urc ++;
-		if (urc >= SH_N_UTLB_ENTRIES || (urb > 0 && urc == urb))
-			urc = 0;
-		/*  fatal("%i\n", urc);  */
-
-		cpu->cd.sh.mmucr &= ~SH4_MMUCR_URC_MASK;
-		cpu->cd.sh.mmucr |= (urc << SH4_MMUCR_URC_SHIFT);
-	}
-
-	/*
-	 *  When doing Instruction lookups, the ITLB should be scanned first.
-	 *  This is done by using negative i. (Ugly hack, but works.)
-	 */
-	if (flags & FLAG_INSTR)
-		i_start = -SH_N_ITLB_ENTRIES;
-	else
-		i_start = 0;
-
-	for (i=i_start; i<SH_N_UTLB_ENTRIES; i++) {
-		if (i<0) {
-			hi = cpu->cd.sh.itlb_hi[i + SH_N_ITLB_ENTRIES];
-			lo = cpu->cd.sh.itlb_lo[i + SH_N_ITLB_ENTRIES];
-		} else {
-			hi = cpu->cd.sh.utlb_hi[i];
-			lo = cpu->cd.sh.utlb_lo[i];
-		}
-		mask = 0xfff00000;
-
-		v = lo & SH4_PTEL_V;
-		if (!v)
-			continue;
-
-		switch (lo & SH4_PTEL_SZ_MASK) {
-		case SH4_PTEL_SZ_1K:  mask = 0xfffffc00; break;
-		case SH4_PTEL_SZ_4K:  mask = 0xfffff000; break;
-		case SH4_PTEL_SZ_64K: mask = 0xffff0000; break;
-		/*  case SH4_PTEL_SZ_1M:  mask = 0xfff00000; break;  */
-		}
-
-		if ((hi & mask) != (vaddr & mask))
-			continue;
-
-		sh = lo & SH4_PTEL_SH;
-
-		if (!sh && require_asid_match) {
-			int asid = hi & SH4_PTEH_ASID_MASK;
-			if (asid != cur_asid)
-				continue;
-		}
-
-		/*  Note/TODO: Check for multiple matches is not implemented. */
-
-		break;
-	}
-
-	/*  Virtual address not found? Then it's a TLB miss.  */
-	if (i == SH_N_UTLB_ENTRIES)
-		goto tlb_miss;
-
-	/*  Matching address found! Let's see whether it is
-	    readable/writable, etc.:  */
-	d = lo & SH4_PTEL_D? 1 : 0;
-	pr = (lo & SH4_PTEL_PR_MASK) >> SH4_PTEL_PR_SHIFT;
-
-	*return_paddr = (vaddr & ~mask) | (lo & mask & 0x1fffffff);
-
-	if (flags & FLAG_INSTR) {
-		/*
-		 *  Instruction access:
-		 */
-#if 0
-		/*  NOTE: Emulating the ITLB as exact as this is not
-			necessary... so I'm disabling it for now.  */
-		/*
-		 *  If a matching entry wasn't found in the ITLB, but in the
-		 *  UTLB, then copy it to a random place in the ITLB.
-		 */
-		if (i >= 0 && !(flags & FLAG_NOEXCEPTIONS)) {
-			int r = random() % SH_N_ITLB_ENTRIES;
-
-			/*  NOTE: Make sure that the old mapping for
-			    that itlb entry is invalidated:  */
-			cpu->invalidate_translation_caches(cpu,
-			    cpu->cd.sh.itlb_hi[r] & ~0xfff, INVALIDATE_VADDR);
-
-			cpu->invalidate_code_translation(cpu,
-			    cpu->cd.sh.utlb_lo[i] & ~0xfff, INVALIDATE_PADDR);
-
-			cpu->cd.sh.itlb_hi[r] = cpu->cd.sh.utlb_hi[i];
-			cpu->cd.sh.itlb_lo[r] = cpu->cd.sh.utlb_lo[i];
-		}
-#endif
-
-		/*  Permission checks:  */
-		if (cpu->cd.sh.sr & SH_SR_MD)
-			return 1;
-		if (!(pr & 2))
-			goto protection_violation;
-
-		return 1;
-	}
-
-	/*  Data access:  */
-	if (cpu->cd.sh.sr & SH_SR_MD) {
-		/*  Kernel access:  */
-		switch (pr) {
-		case 0:
-		case 2:	if (wf)
-				goto protection_violation;
-			return 1;
-		case 1:
-		case 3:	if (wf && !d)
-				goto initial_write_exception;
-			return 1 + d;
-		}
-	}
-
-	/*  User access  */
-	switch (pr) {
-	case 0:
-	case 1:	goto protection_violation;
-	case 2:	if (wf)
-			goto protection_violation;
-		return 1;
-	case 3:	if (wf && !d)
-			goto initial_write_exception;
-		return 1 + d;
-	}
-
-
-tlb_miss:
-	expevt = wf? EXPEVT_TLB_MISS_ST : EXPEVT_TLB_MISS_LD;
-	goto exception;
-
-protection_violation:
-	expevt = wf? EXPEVT_TLB_PROT_ST : EXPEVT_TLB_PROT_LD;
-	goto exception;
-
-initial_write_exception:
-	expevt = EXPEVT_TLB_MOD;
-
-
-exception:
-	if (flags & FLAG_NOEXCEPTIONS) {
-		*return_paddr = 0;
-		return 2;
-	}
-
-	sh_exception(cpu, expevt, 0, vaddr);
-
-	return 0;
-}
-
-
-/*
- *  sh_translate_v2p():
- *
- *  Return values:
- *
- *	0	No access to the virtual address.
- *	1	return_paddr contains the physical address, the page is
- *		available as read-only.
- *	2	Same as 1, but the page is available as read/write.
- */
-int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr64, uint64_t *return_paddr,
-	int flags)
-{
-	int user = cpu->cd.sh.sr & SH_SR_MD? 0 : 1;
-	uint32_t vaddr = vaddr64;
-
-	/*  U0/P0: Userspace addresses, or P3: Kernel virtual memory.  */
-	if (!(vaddr & 0x80000000) ||
-	    (vaddr >= 0xc0000000 && vaddr < 0xe0000000)) {
-		/*  Address translation turned off?  */
-		if (!(cpu->cd.sh.mmucr & SH4_MMUCR_AT)) {
-			/*  Then return raw physical address:  */
-			*return_paddr = vaddr & 0x1fffffff;
-			return 2;
-		}
-
-		/*  Perform translation via the MMU:  */
-		return translate_via_mmu(cpu, vaddr, return_paddr, flags);
-	}
-
-	/*  Store queue region:  */
-	if (vaddr >= 0xe0000000 && vaddr < 0xe4000000) {
-		/*  Note/TODO: Take SH4_MMUCR_SQMD into account.  */
-		*return_paddr = vaddr;
-		return 2;
-	}
-
-	if (user) {
-		if (flags & FLAG_NOEXCEPTIONS) {
-			*return_paddr = 0;
-			return 2;
-		}
-
-		// Hopefully correct behavior; nbjoerg on #GXemul (FreeNode)
-		// noticed that this case was easily triggered inside a
-		// guest OS, by:  int main(void){ *(int *)-4 = 0; }
-		sh_exception(cpu, (flags & FLAG_WRITEFLAG)?
-		    EXPEVT_TLB_MISS_ST : EXPEVT_TLB_MISS_LD, 0, vaddr);
-		return 0;
-	}
-
-	/*  P1,P2: Direct-mapped physical memory.  */
-	if (vaddr >= 0x80000000 && vaddr < 0xc0000000) {
-		*return_paddr = vaddr & 0x1fffffff;
-		return 2;
-	}
-
-	if (flags & FLAG_INSTR) {
-		fatal("TODO: instr at 0x%08" PRIx32"\n", (uint32_t)vaddr);
-		exit(1);
-	}
-
-	/*  P4: Special registers mapped at 0xf0000000 .. 0xffffffff:  */
-	if ((vaddr & 0xf0000000) == 0xf0000000) {
-		*return_paddr = vaddr;
-		return 2;
-	}
-
-	if (flags & FLAG_NOEXCEPTIONS) {
-		*return_paddr = 0;
-		return 2;
-	}
-
-	/*  TODO  */
-
-	/*  The ugly 'if' is just here to fool Compaq CC.  */
-	if (!(flags & FLAG_NOEXCEPTIONS)) {
-		fatal("Unimplemented SH vaddr 0x%08" PRIx32"\n", vaddr);
-		exit(1);
-	}
-
-	return 0;
-}
-
diff -Nru gxemul-0.6.2/src/cpus/README_DYNTRANS gxemul-0.7.0+dfsg/src/cpus/README_DYNTRANS
--- gxemul-0.6.2/src/cpus/README_DYNTRANS	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/cpus/README_DYNTRANS	2021-11-27 09:42:23.000000000 +0000
@@ -38,6 +38,7 @@
 	------		-------				-----		-----
 	Alpha		32-bit				64		no
 	ARM		32-bit, 16-bit (Thumb)		32		no
+	ARM64/AArch64	32-bit ?			64		no
 	AVR		16-bit + variable		8		no
 	AVR32		16-bit + variable		32		?
 	F-CPU		?				?		?
@@ -54,6 +55,7 @@
 	PC532		?				32 (?)		?
 	POWER/PPC	32-bit				64/32		no
 	RCA180x		8-bit (+ variable on 1805)	8-16 (?)	no
+	RISC-V		16-bit + variable (usually 32)	128/64/32	no
 	SH1..4		16-bit				32		yes
 	SH5		32-bit, 16-bit (SHcompact)	64		yes (*1)
 	SPARC		32-bit				64/32		yes
diff -Nru gxemul-0.6.2/src/debugger/debugger.c gxemul-0.7.0+dfsg/src/debugger/debugger.c
--- gxemul-0.6.2/src/debugger/debugger.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/debugger/debugger.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,826 @@
+/*
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Single-step debugger.
+ *
+ *
+ *  This entire module is very much non-reentrant. :-/  TODO: Fix.
+ */
+
+#include <ctype.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "debugger.h"
+#include "diskimage.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "net.h"
+#include "settings.h"
+#include "timer.h"
+#include "x11.h"
+
+
+extern int extra_argc;
+extern char **extra_argv;
+extern struct settings *global_settings;
+
+extern int quiet_mode;
+extern int verbose;
+
+
+/*
+ *  Global debugger variables:
+ *
+ *  TODO: Some of these should be moved to some other place!
+ */
+
+bool single_step = false;
+bool about_to_enter_single_step = false;
+bool debugger_enter_at_end_of_run = false;
+volatile int single_step_breakpoint = 0;
+
+extern bool emul_shutdown;
+
+int old_quiet_mode = 0;
+
+static int debugger_n_steps_left_before_interaction = 0;
+static volatile bool exit_debugger;
+static volatile bool exit_debugger_to_continue_single_stepping;
+
+
+/*
+ *  Private (global) debugger variables:
+ */
+
+static volatile int ctrl_c;
+
+/*  Currently focused CPU, machine, and emulation:  */
+int debugger_cur_cpu;
+int debugger_cur_machine;
+static struct machine *debugger_machine;
+static struct emul *debugger_emul;
+
+#define	MAX_CMD_BUFLEN		72
+#define	N_PREVIOUS_CMDS		150
+static char *last_cmd[N_PREVIOUS_CMDS];
+static int last_cmd_index;
+
+static char repeat_cmd[MAX_CMD_BUFLEN];
+
+#define	MAGIC_UNTOUCHED		0x98ca76c2ffcc0011ULL
+
+static uint64_t last_dump_addr = MAGIC_UNTOUCHED;
+static uint64_t last_unasm_addr = MAGIC_UNTOUCHED;
+
+
+/*
+ *  debugger_readchar():
+ */
+char debugger_readchar(void)
+{
+	int ch;
+
+	while ((ch = console_readchar(MAIN_CONSOLE)) < 0 && !exit_debugger) {
+		/*  Check for X11 events:  */
+		x11_check_event(debugger_emul);
+
+		/*  Give up some CPU time:  */
+		usleep(10000);
+	}
+	return ch;
+}
+
+
+/*
+ *  debugger_activate():
+ *
+ *  This is a signal handler for CTRL-C.  It shouldn't be called directly,
+ *  but setup code in emul.c sets the CTRL-C signal handler to use this
+ *  function.
+ */
+void debugger_activate(int x)
+{
+	ctrl_c = 1;
+
+	if (single_step) {
+		/*  Already in the debugger. Just abort the current line.  */
+		console_makeavail(MAIN_CONSOLE, 3);
+		printf("^C");
+		fflush(stdout);
+	} else {
+		/*
+		 * Enter the single step debugger.
+		 *
+		 * NOTE: Setting single_step = true directly is not wise,
+		 * since it may be in the middle of executing.
+		 */
+		about_to_enter_single_step = true;
+
+		/*  Discard any chars in the input queue:  */
+		while (console_charavail(MAIN_CONSOLE))
+			console_readchar(MAIN_CONSOLE);
+	}
+
+	/*  Clear the repeat-command buffer:  */
+	repeat_cmd[0] = '\0';
+
+	/*  Reactivate the signal handler:  */
+	signal(SIGINT, debugger_activate);
+}
+
+
+/*
+ *  show_breakpoint():
+ */
+static void show_breakpoint(struct machine *m, int i)
+{
+	printf("%3i: 0x", i);
+	if (m->cpus[0]->is_32bit)
+		printf("%08" PRIx32, (uint32_t) m->breakpoints.addr[i]);
+	else
+		printf("%016" PRIx64, (uint64_t) m->breakpoints.addr[i]);
+	if (m->breakpoints.string[i] != NULL)
+		printf(" (%s)", m->breakpoints.string[i]);
+	printf("\n");
+}
+
+
+/****************************************************************************/
+
+
+#include "debugger_cmds.c"
+
+
+/****************************************************************************/
+
+
+/*
+ *  debugger_assignment():
+ *
+ *  cmd contains something like "pc=0x80001000", or "r31=memcpy+0x40".
+ */
+void debugger_assignment(struct machine *m, char *cmd)
+{
+	char *left, *right;
+	int res_left, res_right;
+	uint64_t tmp;
+	uint64_t old_pc = m->cpus[0]->pc;	/*  TODO: multiple cpus?  */
+
+	CHECK_ALLOCATION(left = (char *) malloc(MAX_CMD_BUFLEN));
+	strlcpy(left, cmd, MAX_CMD_BUFLEN);
+	right = strchr(left, '=');
+	if (right == NULL) {
+		fprintf(stderr, "internal error in the debugger\n");
+		exit(1);
+	}
+	*right = '\0';
+
+	/*  Remove trailing spaces in left:  */
+	while (strlen(left) >= 1 && left[strlen(left)-1] == ' ')
+		left[strlen(left)-1] = '\0';
+
+	/*  Remove leading spaces in right:  */
+	right++;
+	while (*right == ' ' && *right != '\0')
+		right++;
+
+	/*  printf("left  = '%s'\nright = '%s'\n", left, right);  */
+
+	res_right = debugger_parse_expression(m, right, 0, &tmp);
+	switch (res_right) {
+	case PARSE_NOMATCH:
+		printf("No match for the right-hand side of the assignment.\n");
+		break;
+	case PARSE_MULTIPLE:
+		printf("Multiple matches for the right-hand side of the "
+		    "assignment.\n");
+		break;
+	default:
+		res_left = debugger_parse_expression(m, left, 1, &tmp);
+		switch (res_left) {
+		case PARSE_NOMATCH:
+			printf("No match for the left-hand side of the "
+			    "assignment.\n");
+			break;
+		case PARSE_MULTIPLE:
+			printf("Multiple matches for the left-hand side "
+			    "of the assignment.\n");
+			break;
+		default:
+			debugger_cmd_print(m, left);
+		}
+	}
+
+	/*
+	 *  If the PC has changed, then release any breakpoint we were
+	 *  currently stopped at.
+	 *
+	 *  TODO: multiple cpus?
+	 */
+	if (old_pc != m->cpus[0]->pc)
+		single_step_breakpoint = 0;
+
+	free(left);
+}
+
+
+/*
+ *  debugger_execute_cmd():
+ */
+void debugger_execute_cmd(char *cmd, int cmd_len)
+{
+	int i, n, i_match, matchlen;
+
+	/*
+	 *  Is there a '=' on the command line? Then try to do an
+	 *  assignment.  (Only if there is just one word, followed
+	 *  by the '=' sign. This makes it possible to use commands
+	 *  such as "device add name addr=xyz".)
+	 */
+	if (strchr(cmd, '=') != NULL) {
+		/*  Count the nr of words:  */
+		int nw = 0, inword = 0;
+		char *p = cmd;
+		while (*p) {
+			if (*p == '=')
+				break;
+			if (*p != ' ') {
+				if (!inword)
+					nw ++;
+				inword = 1;
+			} else
+				inword = 0;
+			p++;
+		}
+
+		if (nw == 1) {
+			debugger_assignment(debugger_machine, cmd);
+			return;
+		}
+	}
+
+	i = 0;
+	while (cmds[i].name != NULL)
+		cmds[i++].tmp_flag = 0;
+
+	/*  How many chars in cmd to match against:  */
+	matchlen = 0;
+	while (isalpha((int)cmd[matchlen]))
+		matchlen ++;
+
+	/*  Check for a command name match:  */
+	n = i = i_match = 0;
+	while (cmds[i].name != NULL) {
+		if (strncasecmp(cmds[i].name, cmd, matchlen) == 0
+		    && cmds[i].f != NULL) {
+			cmds[i].tmp_flag = 1;
+			i_match = i;
+			n++;
+		}
+		i++;
+	}
+
+	/*  No match?  */
+	if (n == 0) {
+		printf("Unknown command '%s'. Type 'help' for help.\n", cmd);
+		return;
+	}
+
+	/*  More than one match?  */
+	if (n > 1) {
+		printf("Ambiguous command '%s':  ", cmd);
+		i = 0;
+		while (cmds[i].name != NULL) {
+			if (cmds[i].tmp_flag)
+				printf("  %s", cmds[i].name);
+			i++;
+		}
+		printf("\n");
+		return;
+	}
+
+	/*  Exactly one match:  */
+	if (cmds[i_match].f != NULL) {
+		char *p = cmd + matchlen;
+		/*  Remove leading whitespace from the args...  */
+		while (*p != '\0' && *p == ' ')
+			p++;
+
+		/*  ... and run the command:  */
+		cmds[i_match].f(debugger_machine, p);
+	} else
+		printf("FATAL ERROR: internal error in debugger.c:"
+		    " no handler for this command?\n");
+}
+
+
+/*
+ *  debugger_readline():
+ *
+ *  Read a line from the terminal.
+ */
+static char *debugger_readline(void)
+{
+	int ch, i, j, n, i_match, reallen, cmd_len, cursor_pos;
+	int read_from_index = last_cmd_index;
+	char *cmd = last_cmd[last_cmd_index];
+
+	cmd_len = 0; cmd[0] = '\0';
+
+	color_prompt();
+	printf("GXemul> ");
+	color_normal();
+
+	fflush(stdout);
+
+	ch = '\0';
+	cmd_len = 0;
+	cursor_pos = 0;
+
+	while (ch != '\n' && !exit_debugger) {
+		ch = debugger_readchar();
+
+		if ((ch == '\b' || ch == 127) && cursor_pos > 0) {
+			/*  Backspace.  */
+			cursor_pos --;
+			cmd_len --;
+			memmove(cmd + cursor_pos, cmd + cursor_pos + 1,
+			    cmd_len);
+			cmd[cmd_len] = '\0';
+			printf("\b");
+			for (i=cursor_pos; i<cmd_len; i++)
+				printf("%c", cmd[i]);
+			printf(" \b");
+			for (i=cursor_pos; i<cmd_len; i++)
+				printf("\b");
+		} else if (ch == 4 && cmd_len > 0 && cursor_pos < cmd_len) {
+			/*  CTRL-D: Delete.  */
+			cmd_len --;
+			memmove(cmd + cursor_pos, cmd + cursor_pos + 1,
+			    cmd_len);
+			cmd[cmd_len] = '\0';
+			for (i=cursor_pos; i<cmd_len; i++)
+				printf("%c", cmd[i]);
+			printf(" \b");
+			for (i=cursor_pos; i<cmd_len; i++)
+				printf("\b");
+		} else if (ch == 1) {
+			/*  CTRL-A: Start of line.  */
+			while (cursor_pos > 0) {
+				cursor_pos --;
+				printf("\b");
+			}
+		} else if (ch == 2) {
+			/*  CTRL-B: Backwards one character.  */
+			if (cursor_pos > 0) {
+				printf("\b");
+				cursor_pos --;
+			}
+		} else if (ch == 3) {
+			/*  CTRL-C: Abort the current line.  */
+			cmd_len = 0; cmd[0] = '\0'; cursor_pos = 0;
+			color_normal();
+			printf("\n");
+			color_prompt();
+			printf("GXemul> ");
+			color_normal();
+			fflush(stdout);
+		} else if (ch == 5) {
+			/*  CTRL-E: End of line.  */
+			while (cursor_pos < cmd_len) {
+				printf("%c", cmd[cursor_pos]);
+				cursor_pos ++;
+			}
+		} else if (ch == 6) {
+			/*  CTRL-F: Forward one character.  */
+			if (cursor_pos < cmd_len) {
+				printf("%c",
+				    cmd[cursor_pos]);
+				cursor_pos ++;
+			}
+		} else if (ch == 11) {
+			/*  CTRL-K: Kill to end of line.  */
+			for (i=0; i<MAX_CMD_BUFLEN; i++)
+				console_makeavail(MAIN_CONSOLE, 4); /*  :-)  */
+		} else if (ch == 14 || ch == 16) {
+			/*  CTRL-P: Previous line in the command history,
+			    CTRL-N: next line  */
+			do {
+				if (ch == 14 &&
+				    read_from_index == last_cmd_index)
+					break;
+				if (ch == 16)
+					i = read_from_index - 1;
+				else
+					i = read_from_index + 1;
+
+				if (i < 0)
+					i = N_PREVIOUS_CMDS - 1;
+				if (i >= N_PREVIOUS_CMDS)
+					i = 0;
+
+				/*  Special case: pressing 'down'
+				    to reach last_cmd_index:  */
+				if (i == last_cmd_index) {
+					read_from_index = i;
+					for (i=cursor_pos; i<cmd_len;
+					    i++)
+						printf(" ");
+					for (i=cmd_len-1; i>=0; i--)
+						printf("\b \b");
+					cmd[0] = '\0';
+					cmd_len = cursor_pos = 0;
+				} else if (last_cmd[i][0] != '\0') {
+					/*  Copy from old line:  */
+					read_from_index = i;
+					for (i=cursor_pos; i<cmd_len;
+					    i++)
+						printf(" ");
+					for (i=cmd_len-1; i>=0; i--)
+						printf("\b \b");
+					strlcpy(cmd,
+					    last_cmd[read_from_index],
+					    MAX_CMD_BUFLEN);
+					cmd_len = strlen(cmd);
+					printf("%s", cmd);
+					cursor_pos = cmd_len;
+				}
+			} while (0);
+		} else if (ch == 20) {
+			/*  CTRL-T: Print SIGINFO-like info.  */
+			color_normal();
+			printf("^T\n");
+
+			struct cpu* cpu = debugger_machine->cpus[debugger_cur_cpu];
+
+			char info[1000];
+			snprintf(info, sizeof(info), "ninstrs=%lli, pc=", (long long) cpu->ninstrs);
+
+			if (cpu->is_32bit)
+				snprintf(info + strlen(info), sizeof(info) - strlen(info),
+				    "0x%08" PRIx32, (uint32_t) cpu->pc);
+			else
+				snprintf(info + strlen(info), sizeof(info) - strlen(info),
+				    "0x%016" PRIx64, (uint64_t) cpu->pc);
+
+			uint64_t offset;
+			int n_args;
+			char* pc_symbol = get_symbol_name_and_n_args(&debugger_machine->symbol_context, cpu->pc, &offset, &n_args);
+			if (pc_symbol != NULL)
+				snprintf(info + strlen(info), sizeof(info) - strlen(info),
+				    " <%s>", pc_symbol);
+
+			if (!cpu->running)
+				snprintf(info + strlen(info), sizeof(info) - strlen(info),
+				    ", stopped");
+
+			debugmsg_cpu(cpu, SUBSYS_CPU, "", VERBOSITY_INFO, "%s", info);
+
+			color_prompt();
+			printf("GXemul> ");
+			color_normal();
+
+			// Reprint all chars, then backspace if cursor_pos is less than cmd_len.
+			for (i = 0; i < cmd_len; ++i)
+				printf("%c", cmd[i]);
+			for (i = 0; i < cmd_len - cursor_pos; ++i)
+				printf("\b");
+
+			fflush(stdout);
+		} else if (ch == 23) {
+			/*  CTRL-W: Backspace a full word.  */
+
+			while (cursor_pos >= 1 && cmd[cursor_pos-1] == ' ') {
+				/*  Backspace.  */
+				cursor_pos --;
+				cmd_len --;
+				memmove(cmd + cursor_pos, cmd + cursor_pos + 1,
+				    cmd_len);
+				cmd[cmd_len] = '\0';
+				printf("\b");
+				for (i=cursor_pos; i<cmd_len; i++)
+					printf("%c", cmd[i]);
+				printf(" \b");
+				for (i=cursor_pos; i<cmd_len; i++)
+					printf("\b");
+			}
+
+			while (cursor_pos >= 1 && cmd[cursor_pos-1] != ' ') {
+				/*  Backspace.  */
+				cursor_pos --;
+				cmd_len --;
+				memmove(cmd + cursor_pos, cmd + cursor_pos + 1,
+				    cmd_len);
+				cmd[cmd_len] = '\0';
+				printf("\b");
+				for (i=cursor_pos; i<cmd_len; i++)
+					printf("%c", cmd[i]);
+				printf(" \b");
+				for (i=cursor_pos; i<cmd_len; i++)
+					printf("\b");
+			}
+		} else if (ch >= ' ' && ch != 127 && cmd_len < MAX_CMD_BUFLEN-1) {
+			/*  Visible character:  */
+			memmove(cmd + cursor_pos + 1, cmd + cursor_pos,
+			    cmd_len - cursor_pos);
+			cmd[cursor_pos] = ch;
+			cmd_len ++;
+			cursor_pos ++;
+			cmd[cmd_len] = '\0';
+			printf("%c", ch);
+			for (i=cursor_pos; i<cmd_len; i++)
+				printf("%c", cmd[i]);
+			for (i=cursor_pos; i<cmd_len; i++)
+				printf("\b");
+		} else if (ch == '\r' || ch == '\n') {
+			ch = '\n';
+			printf("\n");
+		} else if (ch == '\t') {
+			/*  Super-simple tab-completion:  */
+			i = 0;
+			while (cmds[i].name != NULL)
+				cmds[i++].tmp_flag = 0;
+
+			/*  Check for a (partial) command match:  */
+			n = i = i_match = 0;
+			while (cmds[i].name != NULL) {
+				if (strncasecmp(cmds[i].name, cmd,
+				    cmd_len) == 0) {
+					cmds[i].tmp_flag = 1;
+					i_match = i;
+					n++;
+				}
+				i++;
+			}
+
+			switch (n) {
+			case 0:	/*  Beep.  */
+				printf("\a");
+				break;
+			case 1:	/*  Add the rest of the command:  */
+				reallen = strlen(cmds[i_match].name);
+				for (i=cmd_len; i<reallen; i++)
+					console_makeavail(MAIN_CONSOLE,
+					    cmds[i_match].name[i]);
+				/*  ... and a space, if the command takes
+				    any arguments:  */
+				if (cmds[i_match].args != NULL &&
+				    cmds[i_match].args[0] != '\0')
+					console_makeavail(MAIN_CONSOLE, ' ');
+				break;
+			default:
+				/*  Show all possible commands:  */
+				printf("\a\n");	/*  Beep. :-)  */
+				i = 0;		/*  i = cmds index  */
+				j = 0;		/*  j = # of cmds printed  */
+				while (cmds[i].name != NULL) {
+					if (cmds[i].tmp_flag) {
+						size_t q;
+						if (j == 0)
+							printf("  ");
+						printf("%s",
+						    cmds[i].name);
+						j++;
+						if (j != 6)
+							for (q=0; q<13-strlen(
+							    cmds[i].name); q++)
+								printf(" ");
+						if (j == 6) {
+							printf("\n");
+							j = 0;
+						}
+					}
+					i++;
+				}
+				if (j != 0)
+					printf("\n");
+				color_prompt();
+				printf("GXemul> ");
+				color_normal();
+				for (i=0; i<cmd_len; i++)
+					printf("%c", cmd[i]);
+			}
+		} else if (ch == 27) {
+			/*  Escape codes: (cursor keys etc)  */
+			while ((ch = console_readchar(MAIN_CONSOLE)) < 0)
+				usleep(10000);
+			if (ch == '[' || ch == 'O') {
+				while ((ch = console_readchar(MAIN_CONSOLE))
+				    < 0)
+					usleep(10000);
+				switch (ch) {
+				case '2':	/*  2~ = ins  */
+				case '5':	/*  5~ = pgup  */
+				case '6':	/*  6~ = pgdn  */
+					/*  TODO: Ugly hack, but might work.  */
+					while ((ch = console_readchar(
+					    MAIN_CONSOLE)) < 0)
+						usleep(10000);
+					/*  Do nothing for these keys.  */
+					break;
+				case '3':	/*  3~ = delete  */
+					/*  TODO: Ugly hack, but might work.  */
+					while ((ch = console_readchar(
+					    MAIN_CONSOLE)) < 0)
+						usleep(10000);
+					console_makeavail(MAIN_CONSOLE, '\b');
+					break;
+				case 'A':	/*  Up.  */
+					/*  Up cursor ==> CTRL-P  */
+					console_makeavail(MAIN_CONSOLE, 16);
+					break;
+				case 'B':	/*  Down.  */
+					/*  Down cursor ==> CTRL-N  */
+					console_makeavail(MAIN_CONSOLE, 14);
+					break;
+				case 'C':
+					/*  Right cursor ==> CTRL-F  */
+					console_makeavail(MAIN_CONSOLE, 6);
+					break;
+				case 'D':	/*  Left  */
+					/*  Left cursor ==> CTRL-B  */
+					console_makeavail(MAIN_CONSOLE, 2);
+					break;
+				case 'F':
+					/*  End ==> CTRL-E  */
+					console_makeavail(MAIN_CONSOLE, 5);
+					break;
+				case 'H':
+					/*  Home ==> CTRL-A  */
+					console_makeavail(MAIN_CONSOLE, 1);
+					break;
+				}
+			}
+		}
+
+		fflush(stdout);
+	}
+
+	if (exit_debugger)
+		cmd[0] = '\0';
+
+	return cmd;
+}
+
+
+/*
+ *  debugger():
+ *
+ *  This is a loop, which reads a command from the terminal, and executes it.
+ */
+void debugger(void)
+{
+	int i, cmd_len;
+	char *cmd;
+
+	if (debugger_n_steps_left_before_interaction > 0) {
+		debugger_n_steps_left_before_interaction --;
+		return;
+	}
+
+	/*
+	 *  Clear all dyntrans translations, because otherwise things would
+	 *  become to complex to keep in sync.
+	 */
+	/*  TODO: In all machines  */
+	for (i=0; i<debugger_machine->ncpus; i++)
+		if (debugger_machine->cpus[i]->translation_cache != NULL) {
+			cpu_create_or_reset_tc(debugger_machine->cpus[i]);
+			debugger_machine->cpus[i]->
+			    invalidate_translation_caches(
+			    debugger_machine->cpus[i], 0, INVALIDATE_ALL);
+		}
+
+	/*  Stop timers while interacting with the user:  */
+	timer_stop();
+
+	exit_debugger = false;
+	exit_debugger_to_continue_single_stepping = false;
+
+	while (!exit_debugger) {
+		/*  Read a line from the terminal:  */
+		cmd = debugger_readline();
+
+		cmd_len = strlen(cmd);
+
+		/*  Remove spaces:  */
+		while (cmd_len > 0 && cmd[0]==' ')
+			memmove(cmd, cmd+1, cmd_len --);
+		while (cmd_len > 0 && cmd[cmd_len-1] == ' ')
+			cmd[(cmd_len--)-1] = '\0';
+
+		/*  No command? Then try reading another line.  */
+		if (cmd_len == 0) {
+			/*  Special case for repeated commands:  */
+			if (repeat_cmd[0] != '\0')
+				strlcpy(cmd, repeat_cmd, MAX_CMD_BUFLEN);
+			else
+				continue;
+		} else {
+			last_cmd_index ++;
+			if (last_cmd_index >= N_PREVIOUS_CMDS)
+				last_cmd_index = 0;
+
+			repeat_cmd[0] = '\0';
+		}
+
+		debugger_execute_cmd(cmd, cmd_len);
+
+		/*  Special hack for the "step" command:  */
+		if (exit_debugger_to_continue_single_stepping)
+			return;
+	}
+
+	/*  Start up timers again:  */
+	timer_start();
+
+	/*  ... and reset starttime, so that nr of instructions per second
+	    can be calculated correctly:  */
+	for (i=0; i<debugger_machine->ncpus; i++) {
+		gettimeofday(&debugger_machine->cpus[i]->starttime, NULL);
+		debugger_machine->cpus[i]->ninstrs_since_gettimeofday = 0;
+	}
+
+	single_step = false;
+	quiet_mode = old_quiet_mode;
+}
+
+
+/*
+ *  debugger_reset():
+ *
+ *  This function should be called before calling debugger(), when it is
+ *  absolutely necessary that debugger() is interactive. Otherwise, it might
+ *  return without doing anything, such as when single-stepping multiple
+ *  instructions at a time.
+ */
+void debugger_reset(void)
+{
+	debugger_n_steps_left_before_interaction = 0;
+}
+
+
+/*
+ *  debugger_init():
+ *
+ *  Must be called before any other debugger function is used.
+ */
+void debugger_init(struct emul *emul)
+{
+	int i;
+
+	debugger_emul = emul;
+
+	if (emul->n_machines < 1) {
+		fprintf(stderr, "\nERROR: No machines, "
+		    "cannot handle this situation yet.\n\n");
+		exit(1);
+	}
+
+	debugger_machine = emul->machines[0];
+
+	debugger_cur_cpu = 0;
+	debugger_cur_machine = 0;
+
+	for (i=0; i<N_PREVIOUS_CMDS; i++) {
+		CHECK_ALLOCATION(last_cmd[i] = (char *) malloc(MAX_CMD_BUFLEN));
+		last_cmd[i][0] = '\0';
+	}
+
+	last_cmd_index = 0;
+	repeat_cmd[0] = '\0';
+}
+
diff -Nru gxemul-0.6.2/src/debugger/debugger.cc gxemul-0.7.0+dfsg/src/debugger/debugger.cc
--- gxemul-0.6.2/src/debugger/debugger.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/debugger/debugger.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,734 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Single-step debugger.
- *
- *
- *  This entire module is very much non-reentrant. :-/  TODO: Fix.
- */
-
-#include <ctype.h>
-#include <signal.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "debugger.h"
-#include "diskimage.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "net.h"
-#include "settings.h"
-#include "timer.h"
-#include "x11.h"
-
-
-extern int extra_argc;
-extern char **extra_argv;
-extern struct settings *global_settings;
-extern int quiet_mode;
-
-
-/*
- *  Global debugger variables:
- *
- *  TODO: Some of these should be moved to some other place!
- */
-
-volatile int single_step = NOT_SINGLE_STEPPING;
-volatile int exit_debugger;
-int force_debugger_at_exit = 0;
-
-volatile int single_step_breakpoint = 0;
-int debugger_n_steps_left_before_interaction = 0;
-
-int old_instruction_trace = 0;
-int old_quiet_mode = 0;
-int old_show_trace_tree = 0;
-
-
-/*
- *  Private (global) debugger variables:
- */
-
-static volatile int ctrl_c;
-
-/*  Currently focused CPU, machine, and emulation:  */
-int debugger_cur_cpu;
-int debugger_cur_machine;
-static struct machine *debugger_machine;
-static struct emul *debugger_emul;
-
-#define	MAX_CMD_BUFLEN		72
-#define	N_PREVIOUS_CMDS		150
-static char *last_cmd[N_PREVIOUS_CMDS];
-static int last_cmd_index;
-
-static char repeat_cmd[MAX_CMD_BUFLEN];
-
-#define	MAGIC_UNTOUCHED		0x98ca76c2ffcc0011ULL
-
-static uint64_t last_dump_addr = MAGIC_UNTOUCHED;
-static uint64_t last_unasm_addr = MAGIC_UNTOUCHED;
-
-
-/*
- *  debugger_readchar():
- */
-char debugger_readchar(void)
-{
-	int ch;
-
-	while ((ch = console_readchar(MAIN_CONSOLE)) < 0 && !exit_debugger) {
-		/*  Check for X11 events:  */
-		x11_check_event(debugger_emul);
-
-		/*  Give up some CPU time:  */
-		usleep(10000);
-	}
-	return ch;
-}
-
-
-/*
- *  debugger_activate():
- *
- *  This is a signal handler for CTRL-C.  It shouldn't be called directly,
- *  but setup code in emul.c sets the CTRL-C signal handler to use this
- *  function.
- */
-void debugger_activate(int x)
-{
-	ctrl_c = 1;
-
-	if (single_step != NOT_SINGLE_STEPPING) {
-		/*  Already in the debugger. Do nothing.  */
-		int i;
-		for (i=0; i<MAX_CMD_BUFLEN; i++)
-			console_makeavail(MAIN_CONSOLE, '\b');
-		console_makeavail(MAIN_CONSOLE, ' ');
-		console_makeavail(MAIN_CONSOLE, '\n');
-		printf("^C");
-		fflush(stdout);
-	} else {
-		/*  Enter the single step debugger.  */
-		single_step = ENTER_SINGLE_STEPPING;
-
-		/*  Discard any chars in the input queue:  */
-		while (console_charavail(MAIN_CONSOLE))
-			console_readchar(MAIN_CONSOLE);
-	}
-
-	/*  Clear the repeat-command buffer:  */
-	repeat_cmd[0] = '\0';
-
-	/*  Reactivate the signal handler:  */
-	signal(SIGINT, debugger_activate);
-}
-
-
-/*
- *  show_breakpoint():
- */
-static void show_breakpoint(struct machine *m, int i)
-{
-	printf("%3i: 0x", i);
-	if (m->cpus[0]->is_32bit)
-		printf("%08" PRIx32, (uint32_t) m->breakpoints.addr[i]);
-	else
-		printf("%016" PRIx64, (uint64_t) m->breakpoints.addr[i]);
-	if (m->breakpoints.string[i] != NULL)
-		printf(" (%s)", m->breakpoints.string[i]);
-	printf("\n");
-}
-
-
-/****************************************************************************/
-
-
-#include "debugger_cmds.cc"
-
-
-/****************************************************************************/
-
-
-/*
- *  debugger_assignment():
- *
- *  cmd contains something like "pc=0x80001000", or "r31=memcpy+0x40".
- */
-void debugger_assignment(struct machine *m, char *cmd)
-{
-	char *left, *right;
-	int res_left, res_right;
-	uint64_t tmp;
-	uint64_t old_pc = m->cpus[0]->pc;	/*  TODO: multiple cpus?  */
-
-	CHECK_ALLOCATION(left = (char *) malloc(MAX_CMD_BUFLEN));
-	strlcpy(left, cmd, MAX_CMD_BUFLEN);
-	right = strchr(left, '=');
-	if (right == NULL) {
-		fprintf(stderr, "internal error in the debugger\n");
-		exit(1);
-	}
-	*right = '\0';
-
-	/*  Remove trailing spaces in left:  */
-	while (strlen(left) >= 1 && left[strlen(left)-1] == ' ')
-		left[strlen(left)-1] = '\0';
-
-	/*  Remove leading spaces in right:  */
-	right++;
-	while (*right == ' ' && *right != '\0')
-		right++;
-
-	/*  printf("left  = '%s'\nright = '%s'\n", left, right);  */
-
-	res_right = debugger_parse_expression(m, right, 0, &tmp);
-	switch (res_right) {
-	case PARSE_NOMATCH:
-		printf("No match for the right-hand side of the assignment.\n");
-		break;
-	case PARSE_MULTIPLE:
-		printf("Multiple matches for the right-hand side of the "
-		    "assignment.\n");
-		break;
-	default:
-		res_left = debugger_parse_expression(m, left, 1, &tmp);
-		switch (res_left) {
-		case PARSE_NOMATCH:
-			printf("No match for the left-hand side of the "
-			    "assignment.\n");
-			break;
-		case PARSE_MULTIPLE:
-			printf("Multiple matches for the left-hand side "
-			    "of the assignment.\n");
-			break;
-		default:
-			debugger_cmd_print(m, left);
-		}
-	}
-
-	/*
-	 *  If the PC has changed, then release any breakpoint we were
-	 *  currently stopped at.
-	 *
-	 *  TODO: multiple cpus?
-	 */
-	if (old_pc != m->cpus[0]->pc)
-		single_step_breakpoint = 0;
-
-	free(left);
-}
-
-
-/*
- *  debugger_execute_cmd():
- */
-void debugger_execute_cmd(char *cmd, int cmd_len)
-{
-	int i, n, i_match, matchlen;
-
-	/*
-	 *  Is there a '=' on the command line? Then try to do an
-	 *  assignment.  (Only if there is just one word, followed
-	 *  by the '=' sign. This makes it possible to use commands
-	 *  such as "device add name addr=xyz".)
-	 */
-	if (strchr(cmd, '=') != NULL) {
-		/*  Count the nr of words:  */
-		int nw = 0, inword = 0;
-		char *p = cmd;
-		while (*p) {
-			if (*p == '=')
-				break;
-			if (*p != ' ') {
-				if (!inword)
-					nw ++;
-				inword = 1;
-			} else
-				inword = 0;
-			p++;
-		}
-
-		if (nw == 1) {
-			debugger_assignment(debugger_machine, cmd);
-			return;
-		}
-	}
-
-	i = 0;
-	while (cmds[i].name != NULL)
-		cmds[i++].tmp_flag = 0;
-
-	/*  How many chars in cmd to match against:  */
-	matchlen = 0;
-	while (isalpha((int)cmd[matchlen]))
-		matchlen ++;
-
-	/*  Check for a command name match:  */
-	n = i = i_match = 0;
-	while (cmds[i].name != NULL) {
-		if (strncasecmp(cmds[i].name, cmd, matchlen) == 0
-		    && cmds[i].f != NULL) {
-			cmds[i].tmp_flag = 1;
-			i_match = i;
-			n++;
-		}
-		i++;
-	}
-
-	/*  No match?  */
-	if (n == 0) {
-		printf("Unknown command '%s'. Type 'help' for help.\n", cmd);
-		return;
-	}
-
-	/*  More than one match?  */
-	if (n > 1) {
-		printf("Ambiguous command '%s':  ", cmd);
-		i = 0;
-		while (cmds[i].name != NULL) {
-			if (cmds[i].tmp_flag)
-				printf("  %s", cmds[i].name);
-			i++;
-		}
-		printf("\n");
-		return;
-	}
-
-	/*  Exactly one match:  */
-	if (cmds[i_match].f != NULL) {
-		char *p = cmd + matchlen;
-		/*  Remove leading whitespace from the args...  */
-		while (*p != '\0' && *p == ' ')
-			p++;
-
-		/*  ... and run the command:  */
-		cmds[i_match].f(debugger_machine, p);
-	} else
-		printf("FATAL ERROR: internal error in debugger.c:"
-		    " no handler for this command?\n");
-}
-
-
-/*
- *  debugger_readline():
- *
- *  Read a line from the terminal.
- */
-static char *debugger_readline(void)
-{
-	int ch, i, j, n, i_match, reallen, cmd_len, cursor_pos;
-	int read_from_index = last_cmd_index;
-	char *cmd = last_cmd[last_cmd_index];
-
-	cmd_len = 0; cmd[0] = '\0';
-	printf("GXemul> ");
-	fflush(stdout);
-
-	ch = '\0';
-	cmd_len = 0;
-	cursor_pos = 0;
-
-	while (ch != '\n' && !exit_debugger) {
-		ch = debugger_readchar();
-
-		if ((ch == '\b' || ch == 127) && cursor_pos > 0) {
-			/*  Backspace.  */
-			cursor_pos --;
-			cmd_len --;
-			memmove(cmd + cursor_pos, cmd + cursor_pos + 1,
-			    cmd_len);
-			cmd[cmd_len] = '\0';
-			printf("\b");
-			for (i=cursor_pos; i<cmd_len; i++)
-				printf("%c", cmd[i]);
-			printf(" \b");
-			for (i=cursor_pos; i<cmd_len; i++)
-				printf("\b");
-		} else if (ch == 4 && cmd_len > 0 && cursor_pos < cmd_len) {
-			/*  CTRL-D: Delete.  */
-			cmd_len --;
-			memmove(cmd + cursor_pos, cmd + cursor_pos + 1,
-			    cmd_len);
-			cmd[cmd_len] = '\0';
-			for (i=cursor_pos; i<cmd_len; i++)
-				printf("%c", cmd[i]);
-			printf(" \b");
-			for (i=cursor_pos; i<cmd_len; i++)
-				printf("\b");
-		} else if (ch == 1) {
-			/*  CTRL-A: Start of line.  */
-			while (cursor_pos > 0) {
-				cursor_pos --;
-				printf("\b");
-			}
-		} else if (ch == 2) {
-			/*  CTRL-B: Backwards one character.  */
-			if (cursor_pos > 0) {
-				printf("\b");
-				cursor_pos --;
-			}
-		} else if (ch == 5) {
-			/*  CTRL-E: End of line.  */
-			while (cursor_pos < cmd_len) {
-				printf("%c", cmd[cursor_pos]);
-				cursor_pos ++;
-			}
-		} else if (ch == 6) {
-			/*  CTRL-F: Forward one character.  */
-			if (cursor_pos < cmd_len) {
-				printf("%c",
-				    cmd[cursor_pos]);
-				cursor_pos ++;
-			}
-		} else if (ch == 11) {
-			/*  CTRL-K: Kill to end of line.  */
-			for (i=0; i<MAX_CMD_BUFLEN; i++)
-				console_makeavail(MAIN_CONSOLE, 4); /*  :-)  */
-		} else if (ch == 14 || ch == 16) {
-			/*  CTRL-P: Previous line in the command history,
-			    CTRL-N: next line  */
-			do {
-				if (ch == 14 &&
-				    read_from_index == last_cmd_index)
-					break;
-				if (ch == 16)
-					i = read_from_index - 1;
-				else
-					i = read_from_index + 1;
-
-				if (i < 0)
-					i = N_PREVIOUS_CMDS - 1;
-				if (i >= N_PREVIOUS_CMDS)
-					i = 0;
-
-				/*  Special case: pressing 'down'
-				    to reach last_cmd_index:  */
-				if (i == last_cmd_index) {
-					read_from_index = i;
-					for (i=cursor_pos; i<cmd_len;
-					    i++)
-						printf(" ");
-					for (i=cmd_len-1; i>=0; i--)
-						printf("\b \b");
-					cmd[0] = '\0';
-					cmd_len = cursor_pos = 0;
-				} else if (last_cmd[i][0] != '\0') {
-					/*  Copy from old line:  */
-					read_from_index = i;
-					for (i=cursor_pos; i<cmd_len;
-					    i++)
-						printf(" ");
-					for (i=cmd_len-1; i>=0; i--)
-						printf("\b \b");
-					strlcpy(cmd,
-					    last_cmd[read_from_index],
-					    MAX_CMD_BUFLEN);
-					cmd_len = strlen(cmd);
-					printf("%s", cmd);
-					cursor_pos = cmd_len;
-				}
-			} while (0);
-		} else if (ch >= ' ' && cmd_len < MAX_CMD_BUFLEN-1) {
-			/*  Visible character:  */
-			memmove(cmd + cursor_pos + 1, cmd + cursor_pos,
-			    cmd_len - cursor_pos);
-			cmd[cursor_pos] = ch;
-			cmd_len ++;
-			cursor_pos ++;
-			cmd[cmd_len] = '\0';
-			printf("%c", ch);
-			for (i=cursor_pos; i<cmd_len; i++)
-				printf("%c", cmd[i]);
-			for (i=cursor_pos; i<cmd_len; i++)
-				printf("\b");
-		} else if (ch == '\r' || ch == '\n') {
-			ch = '\n';
-			printf("\n");
-		} else if (ch == '\t') {
-			/*  Super-simple tab-completion:  */
-			i = 0;
-			while (cmds[i].name != NULL)
-				cmds[i++].tmp_flag = 0;
-
-			/*  Check for a (partial) command match:  */
-			n = i = i_match = 0;
-			while (cmds[i].name != NULL) {
-				if (strncasecmp(cmds[i].name, cmd,
-				    cmd_len) == 0) {
-					cmds[i].tmp_flag = 1;
-					i_match = i;
-					n++;
-				}
-				i++;
-			}
-
-			switch (n) {
-			case 0:	/*  Beep.  */
-				printf("\a");
-				break;
-			case 1:	/*  Add the rest of the command:  */
-				reallen = strlen(cmds[i_match].name);
-				for (i=cmd_len; i<reallen; i++)
-					console_makeavail(MAIN_CONSOLE,
-					    cmds[i_match].name[i]);
-				/*  ... and a space, if the command takes
-				    any arguments:  */
-				if (cmds[i_match].args != NULL &&
-				    cmds[i_match].args[0] != '\0')
-					console_makeavail(MAIN_CONSOLE, ' ');
-				break;
-			default:
-				/*  Show all possible commands:  */
-				printf("\a\n");	/*  Beep. :-)  */
-				i = 0;		/*  i = cmds index  */
-				j = 0;		/*  j = # of cmds printed  */
-				while (cmds[i].name != NULL) {
-					if (cmds[i].tmp_flag) {
-						size_t q;
-						if (j == 0)
-							printf("  ");
-						printf("%s",
-						    cmds[i].name);
-						j++;
-						if (j != 6)
-							for (q=0; q<13-strlen(
-							    cmds[i].name); q++)
-								printf(" ");
-						if (j == 6) {
-							printf("\n");
-							j = 0;
-						}
-					}
-					i++;
-				}
-				if (j != 0)
-					printf("\n");
-				printf("GXemul> ");
-				for (i=0; i<cmd_len; i++)
-					printf("%c", cmd[i]);
-			}
-		} else if (ch == 27) {
-			/*  Escape codes: (cursor keys etc)  */
-			while ((ch = console_readchar(MAIN_CONSOLE)) < 0)
-				usleep(10000);
-			if (ch == '[' || ch == 'O') {
-				while ((ch = console_readchar(MAIN_CONSOLE))
-				    < 0)
-					usleep(10000);
-				switch (ch) {
-				case '2':	/*  2~ = ins  */
-				case '5':	/*  5~ = pgup  */
-				case '6':	/*  6~ = pgdn  */
-					/*  TODO: Ugly hack, but might work.  */
-					while ((ch = console_readchar(
-					    MAIN_CONSOLE)) < 0)
-						usleep(10000);
-					/*  Do nothing for these keys.  */
-					break;
-				case '3':	/*  3~ = delete  */
-					/*  TODO: Ugly hack, but might work.  */
-					while ((ch = console_readchar(
-					    MAIN_CONSOLE)) < 0)
-						usleep(10000);
-					console_makeavail(MAIN_CONSOLE, '\b');
-					break;
-				case 'A':	/*  Up.  */
-					/*  Up cursor ==> CTRL-P  */
-					console_makeavail(MAIN_CONSOLE, 16);
-					break;
-				case 'B':	/*  Down.  */
-					/*  Down cursor ==> CTRL-N  */
-					console_makeavail(MAIN_CONSOLE, 14);
-					break;
-				case 'C':
-					/*  Right cursor ==> CTRL-F  */
-					console_makeavail(MAIN_CONSOLE, 6);
-					break;
-				case 'D':	/*  Left  */
-					/*  Left cursor ==> CTRL-B  */
-					console_makeavail(MAIN_CONSOLE, 2);
-					break;
-				case 'F':
-					/*  End ==> CTRL-E  */
-					console_makeavail(MAIN_CONSOLE, 5);
-					break;
-				case 'H':
-					/*  Home ==> CTRL-A  */
-					console_makeavail(MAIN_CONSOLE, 1);
-					break;
-				}
-			}
-		}
-
-		fflush(stdout);
-	}
-
-	if (exit_debugger)
-		cmd[0] = '\0';
-
-	return cmd;
-}
-
-
-/*
- *  debugger():
- *
- *  This is a loop, which reads a command from the terminal, and executes it.
- */
-void debugger(void)
-{
-	int i, cmd_len;
-	char *cmd;
-
-	if (debugger_n_steps_left_before_interaction > 0) {
-		debugger_n_steps_left_before_interaction --;
-		return;
-	}
-
-	/*
-	 *  Clear all dyntrans translations, because otherwise things would
-	 *  become to complex to keep in sync.
-	 */
-	/*  TODO: In all machines  */
-	for (i=0; i<debugger_machine->ncpus; i++)
-		if (debugger_machine->cpus[i]->translation_cache != NULL) {
-			cpu_create_or_reset_tc(debugger_machine->cpus[i]);
-			debugger_machine->cpus[i]->
-			    invalidate_translation_caches(
-			    debugger_machine->cpus[i], 0, INVALIDATE_ALL);
-		}
-
-	/*  Stop timers while interacting with the user:  */
-	timer_stop();
-
-	exit_debugger = 0;
-
-	while (!exit_debugger) {
-		/*  Read a line from the terminal:  */
-		cmd = debugger_readline();
-
-		cmd_len = strlen(cmd);
-
-		/*  Remove spaces:  */
-		while (cmd_len > 0 && cmd[0]==' ')
-			memmove(cmd, cmd+1, cmd_len --);
-		while (cmd_len > 0 && cmd[cmd_len-1] == ' ')
-			cmd[(cmd_len--)-1] = '\0';
-
-		/*  No command? Then try reading another line.  */
-		if (cmd_len == 0) {
-			/*  Special case for repeated commands:  */
-			if (repeat_cmd[0] != '\0')
-				strlcpy(cmd, repeat_cmd, MAX_CMD_BUFLEN);
-			else
-				continue;
-		} else {
-			last_cmd_index ++;
-			if (last_cmd_index >= N_PREVIOUS_CMDS)
-				last_cmd_index = 0;
-
-			repeat_cmd[0] = '\0';
-		}
-
-		debugger_execute_cmd(cmd, cmd_len);
-
-		/*  Special hack for the "step" command:  */
-		if (exit_debugger == -1)
-			return;
-	}
-
-	/*  Start up timers again:  */
-	timer_start();
-
-	/*  ... and reset starttime, so that nr of instructions per second
-	    can be calculated correctly:  */
-	for (i=0; i<debugger_machine->ncpus; i++) {
-		gettimeofday(&debugger_machine->cpus[i]->starttime, NULL);
-		debugger_machine->cpus[i]->ninstrs_since_gettimeofday = 0;
-	}
-
-	single_step = NOT_SINGLE_STEPPING;
-	debugger_machine->instruction_trace = old_instruction_trace;
-	debugger_machine->show_trace_tree = old_show_trace_tree;
-	quiet_mode = old_quiet_mode;
-}
-
-
-/*
- *  debugger_reset():
- *
- *  This function should be called before calling debugger(), when it is
- *  absolutely necessary that debugger() is interactive. Otherwise, it might
- *  return without doing anything, such as when single-stepping multiple
- *  instructions at a time.
- */
-void debugger_reset(void)
-{
-	debugger_n_steps_left_before_interaction = 0;
-}
-
-
-/*
- *  debugger_init():
- *
- *  Must be called before any other debugger function is used.
- */
-void debugger_init(struct emul *emul)
-{
-	int i;
-
-	debugger_emul = emul;
-
-	if (emul->n_machines < 1) {
-		fprintf(stderr, "\nERROR: No machines, "
-		    "cannot handle this situation yet.\n\n");
-		exit(1);
-	}
-
-	debugger_machine = emul->machines[0];
-
-	debugger_cur_cpu = 0;
-	debugger_cur_machine = 0;
-
-	for (i=0; i<N_PREVIOUS_CMDS; i++) {
-		CHECK_ALLOCATION(last_cmd[i] = (char *) malloc(MAX_CMD_BUFLEN));
-		last_cmd[i][0] = '\0';
-	}
-
-	last_cmd_index = 0;
-	repeat_cmd[0] = '\0';
-}
-
diff -Nru gxemul-0.6.2/src/debugger/debugger_cmds.c gxemul-0.7.0+dfsg/src/debugger/debugger_cmds.c
--- gxemul-0.6.2/src/debugger/debugger_cmds.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/debugger/debugger_cmds.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1425 @@
+/*
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Debugger commands. Included from debugger.c.
+ */
+
+
+/*
+ *  debugger_cmd_allsettings():
+ */
+static void debugger_cmd_allsettings(struct machine *m, char *args)
+{
+	settings_debugdump(global_settings, GLOBAL_SETTINGS_NAME, 1);
+}
+
+
+/*
+ *  debugger_cmd_breakpoint():
+ *
+ *  TODO: automagic "expansion" for the subcommand names (s => show).
+ */
+static void debugger_cmd_breakpoint(struct machine *m, char *args)
+{
+	int i, res;
+
+	while (args[0] != '\0' && args[0] == ' ')
+		args ++;
+
+	if (args[0] == '\0') {
+		printf("syntax: breakpoint subcmd [args...]\n");
+		printf("Available subcmds (and args) are:\n");
+		printf("  add addr      add a breakpoint for address addr\n");
+		printf("  delete x      delete breakpoint nr x\n");
+		printf("  show          show current breakpoints\n");
+		return;
+	}
+
+	if (strcmp(args, "show") == 0) {
+		if (m->breakpoints.n == 0)
+			printf("No breakpoints set.\n");
+		for (i=0; i<m->breakpoints.n; i++)
+			show_breakpoint(m, i);
+		return;
+	}
+
+	if (strncmp(args, "delete ", 7) == 0) {
+		int x = atoi(args + 7);
+
+		if (m->breakpoints.n == 0) {
+			printf("No breakpoints set.\n");
+			return;
+		}
+		if (x < 0 || x > m->breakpoints.n) {
+			printf("Invalid breakpoint nr %i. Use 'breakpoint "
+			    "show' to see the current breakpoints.\n", x);
+			return;
+		}
+
+		free(m->breakpoints.string[x]);
+
+		for (i=x; i<m->breakpoints.n-1; i++) {
+			m->breakpoints.addr[i]   = m->breakpoints.addr[i+1];
+			m->breakpoints.string[i] = m->breakpoints.string[i+1];
+		}
+		m->breakpoints.n --;
+
+		/*  Clear translations:  */
+		for (i=0; i<m->ncpus; i++)
+			if (m->cpus[i]->translation_cache != NULL)
+				cpu_create_or_reset_tc(m->cpus[i]);
+		return;
+	}
+
+	if (strncmp(args, "add ", 4) == 0) {
+		uint64_t tmp;
+		size_t breakpoint_buf_len;
+
+		i = m->breakpoints.n;
+
+		res = debugger_parse_expression(m, args + 4, 0, &tmp);
+		if (!res) {
+			printf("Couldn't parse '%s'\n", args + 4);
+			return;
+		}
+
+		CHECK_ALLOCATION(m->breakpoints.string = (char **) realloc(
+		    m->breakpoints.string, sizeof(char *) *
+		    (m->breakpoints.n + 1)));
+		CHECK_ALLOCATION(m->breakpoints.addr = (uint64_t *) realloc(
+		    m->breakpoints.addr, sizeof(uint64_t) *
+		   (m->breakpoints.n + 1)));
+
+		breakpoint_buf_len = strlen(args+4) + 1;
+
+		CHECK_ALLOCATION(m->breakpoints.string[i] = (char *)
+		    malloc(breakpoint_buf_len));
+		strlcpy(m->breakpoints.string[i], args+4,
+		    breakpoint_buf_len);
+		m->breakpoints.addr[i] = tmp;
+
+		m->breakpoints.n ++;
+		show_breakpoint(m, i);
+
+		/*  Clear translations:  */
+		for (i=0; i<m->ncpus; i++)
+			if (m->cpus[i]->translation_cache != NULL)
+				cpu_create_or_reset_tc(m->cpus[i]);
+		return;
+	}
+
+	printf("Unknown breakpoint subcommand.\n");
+}
+
+
+/*
+ *  debugger_cmd_continue():
+ */
+static void debugger_cmd_continue(struct machine *m, char *args)
+{
+	if (*args) {
+		printf("syntax: continue\n");
+		return;
+	}
+
+	exit_debugger = true;
+}
+
+
+/*
+ *  debugger_cmd_device():
+ */
+static void debugger_cmd_device(struct machine *m, char *args)
+{
+	int i;
+	struct memory *mem;
+	struct cpu *c;
+
+	if (args[0] == '\0')
+		goto return_help;
+
+	if (m->cpus == NULL) {
+		printf("No cpus (?)\n");
+		return;
+	}
+	c = m->cpus[m->bootstrap_cpu];
+	if (c == NULL) {
+		printf("m->cpus[m->bootstrap_cpu] = NULL\n");
+		return;
+	}
+	mem = m->cpus[m->bootstrap_cpu]->mem;
+
+	if (m->cpus == NULL) {
+		printf("No cpus (?)\n");
+		return;
+	}
+	c = m->cpus[m->bootstrap_cpu];
+	if (c == NULL) {
+		printf("m->cpus[m->bootstrap_cpu] = NULL\n");
+		return;
+	}
+	mem = m->cpus[m->bootstrap_cpu]->mem;
+
+	if (strcmp(args, "all") == 0) {
+		device_dumplist();
+	} else if (strncmp(args, "add ", 4) == 0) {
+		device_add(m, args+4);
+	} else if (strcmp(args, "consoles") == 0) {
+		console_debug_dump(m);
+	} else if (strncmp(args, "remove ", 7) == 0) {
+		i = atoi(args + 7);
+		if (i==0 && args[7]!='0') {
+			printf("Weird device number. Use 'device list'.\n");
+		} else
+			memory_device_remove(m->memory, i);
+	} else if (strcmp(args, "list") == 0) {
+		if (mem->n_mmapped_devices == 0)
+			printf("No memory-mapped devices in this machine.\n");
+
+		for (i=0; i<mem->n_mmapped_devices; i++) {
+			printf("%2i: %25s @ 0x%011" PRIx64", len = 0x%" PRIx64,
+			    i, mem->devices[i].name,
+			    (uint64_t) mem->devices[i].baseaddr,
+			    (uint64_t) mem->devices[i].length);
+
+			if (mem->devices[i].flags) {
+				printf(" (");
+				if (mem->devices[i].flags & DM_DYNTRANS_OK)
+					printf("DYNTRANS R");
+				if (mem->devices[i].flags &DM_DYNTRANS_WRITE_OK)
+					printf("+W");
+				printf(")");
+			}
+			printf("\n");
+		}
+	} else
+		goto return_help;
+
+	return;
+
+return_help:
+	printf("syntax: devices cmd [...]\n");
+	printf("Available cmds are:\n");
+	printf("  add name_and_params    add a device to the current "
+	    "machine\n");
+	printf("  all                    list all registered devices\n");
+	printf("  consoles               list all slave consoles\n");
+	printf("  list                   list memory-mapped devices in the"
+	    " current machine\n");
+	printf("  remove x               remove device nr x from the "
+	    "current machine\n");
+}
+
+
+/*
+ *  debugger_cmd_dump():
+ *
+ *  Dump emulated memory in hex and ASCII.
+ *
+ *  syntax: dump [addr [endaddr]]
+ */
+static void debugger_cmd_dump(struct machine *m, char *args)
+{
+	uint64_t addr, addr_start, addr_end;
+	struct cpu *c;
+	struct memory *mem;
+	char *p = NULL;
+	int x, r;
+
+	if (args[0] != '\0') {
+		uint64_t tmp;
+		char *tmps;
+
+		CHECK_ALLOCATION(tmps = strdup(args));
+
+		/*  addr:  */
+		p = strchr(tmps, ' ');
+		if (p != NULL)
+			*p = '\0';
+		r = debugger_parse_expression(m, tmps, 0, &tmp);
+		free(tmps);
+
+		if (r == PARSE_NOMATCH || r == PARSE_MULTIPLE) {
+			printf("Unparsable address: %s\n", args);
+			return;
+		} else {
+			last_dump_addr = tmp;
+		}
+
+		p = strchr(args, ' ');
+	}
+
+	if (m->cpus == NULL) {
+		printf("No cpus (?)\n");
+		return;
+	}
+	c = m->cpus[m->bootstrap_cpu];
+	if (c == NULL) {
+		printf("m->cpus[m->bootstrap_cpu] = NULL\n");
+		return;
+	}
+	mem = m->cpus[m->bootstrap_cpu]->mem;
+
+	addr_start = last_dump_addr;
+
+	if (addr_start == MAGIC_UNTOUCHED)
+		addr_start = c->pc;
+
+	addr_end = addr_start + 16 * 16;
+
+	/*  endaddr:  */
+	if (p != NULL) {
+		while (*p == ' ' && *p)
+			p++;
+		r = debugger_parse_expression(m, p, 0, &addr_end);
+		if (r == PARSE_NOMATCH || r == PARSE_MULTIPLE) {
+			printf("Unparsable address: %s\n", args);
+			return;
+		}
+	}
+
+	addr = addr_start & ~0xf;
+
+	ctrl_c = 0;
+
+	while (addr < addr_end) {
+		unsigned char buf[16];
+		memset(buf, 0, sizeof(buf));
+		r = c->memory_rw(c, mem, addr, &buf[0], sizeof(buf),
+		    MEM_READ, CACHE_NONE | NO_EXCEPTIONS);
+
+		if (c->is_32bit)
+			printf("0x%08" PRIx32"  ", (uint32_t) addr);
+		else
+			printf("0x%016" PRIx64"  ", (uint64_t) addr);
+
+		if (r == MEMORY_ACCESS_FAILED)
+			printf("(memory access failed)\n");
+		else {
+			for (x=0; x<16; x++) {
+				if (addr + x >= addr_start &&
+				    addr + x < addr_end)
+					printf("%02x%s", buf[x],
+					    (x&3)==3? " " : "");
+				else
+					printf("  %s", (x&3)==3? " " : "");
+			}
+			printf(" ");
+			for (x=0; x<16; x++) {
+				if (addr + x >= addr_start &&
+				    addr + x < addr_end)
+					printf("%c", (buf[x]>=' ' &&
+					    buf[x]<127)? buf[x] : '.');
+				else
+					printf(" ");
+			}
+			printf("\n");
+		}
+
+		if (ctrl_c)
+			return;
+
+		addr += sizeof(buf);
+	}
+
+	last_dump_addr = addr_end;
+
+	strlcpy(repeat_cmd, "dump", MAX_CMD_BUFLEN);
+}
+
+
+/*
+ *  debugger_cmd_emul():
+ *
+ *  Dump info about the current emulation.
+ */
+static void debugger_cmd_emul(struct machine *m, char *args)
+{
+	if (*args) {
+		printf("syntax: emul\n");
+		return;
+	}
+
+	if (debugger_emul->name != NULL)
+		debugmsg(SUBSYS_EMUL, "", VERBOSITY_INFO, "\"%s\"", debugger_emul->name);
+
+	debug_indentation(1);
+	emul_dumpinfo(debugger_emul);
+	debug_indentation(-1);
+}
+
+
+/*
+ *  debugger_cmd_focus():
+ *
+ *  Changes focus to specific cpu, in a specific machine (in a specific
+ *  emulation).
+ */
+static void debugger_cmd_focus(struct machine *m, char *args)
+{
+	int x = -1, y = -1;
+	char *p, *p2;
+
+	if (!args[0]) {
+		printf("syntax: focus x[,y]\n");
+		printf("where x (cpu id) and y (machine number) "
+		    "are integers as\nreported by the 'emul'"
+		    " command.\n");
+		goto print_current_focus_and_return;
+	}
+
+	x = atoi(args);
+	p = strchr(args, ',');
+	if (p == args) {
+		printf("No cpu number specified?\n");
+		return;
+	}
+
+	if (p != NULL) {
+		y = atoi(p+1);
+		p2 = strchr(p+1, ',');
+		if (p2 == p+1) {
+			printf("No machine number specified?\n");
+			return;
+		}
+	}
+
+	if (y != -1) {
+		/*  Change machine:  */
+		if (y < 0 || y >= debugger_emul->n_machines) {
+			printf("Invalid machine number: %i\n", y);
+			return;
+		}
+
+		debugger_cur_machine = y;
+		debugger_machine = debugger_emul->machines[y];
+	}
+
+	/*  Change cpu:  */
+	if (x < 0 || x >= debugger_machine->ncpus) {
+		printf("Invalid cpu number: %i\n", x);
+		return;
+	}
+
+	debugger_cur_cpu = x;
+
+print_current_focus_and_return:
+	if (debugger_emul->n_machines > 1)
+		printf("current machine (%i): \"%s\"\n",
+		    debugger_cur_machine, debugger_machine->name == NULL?
+		    "(no name)" : debugger_machine->name);
+
+	printf("current cpu (%i)\n", debugger_cur_cpu);
+}
+
+
+/*  This is defined below.  */
+static void debugger_cmd_help(struct machine *m, char *args);
+
+
+/*
+ *  debugger_cmd_itrace():
+ */
+static void debugger_cmd_itrace(struct machine *m, char *args)
+{
+	if (*args) {
+		printf("syntax: itrace\n");
+		return;
+	}
+
+	m->instruction_trace = !m->instruction_trace;
+
+	if (m->instruction_trace)
+		verbose ++;
+	else
+		verbose --;
+
+	printf("instruction_trace = %s\n", m->instruction_trace? "ON":"OFF");
+}
+
+
+/*
+ *  debugger_cmd_lookup():
+ */
+static void debugger_cmd_lookup(struct machine *m, char *args)
+{
+	uint64_t addr;
+	int res;
+	char *symbol;
+	uint64_t offset;
+
+	if (args[0] == '\0') {
+		printf("syntax: lookup name|addr\n");
+		return;
+
+	}
+
+	/*  Addresses never need to be given in decimal form anyway,
+	    so assuming hex here will be ok.  */
+	addr = strtoull(args, NULL, 16);
+
+	if (addr == 0) {
+		uint64_t newaddr;
+		res = get_symbol_addr(&m->symbol_context,
+		    args, &newaddr);
+		if (!res) {
+			printf("lookup for '%s' failed\n", args);
+			return;
+		}
+		printf("%s = 0x", args);
+		if (m->cpus[0]->is_32bit)
+			printf("%08" PRIx32"\n", (uint32_t) newaddr);
+		else
+			printf("%016" PRIx64"\n", (uint64_t) newaddr);
+		return;
+	}
+
+	symbol = get_symbol_name(&m->symbol_context, addr, &offset);
+
+	if (symbol != NULL) {
+		if (m->cpus[0]->is_32bit)
+			printf("0x%08" PRIx32, (uint32_t) addr);
+		else
+			printf("0x%016" PRIx64, (uint64_t) addr);
+		printf(" = %s\n", symbol);
+	} else
+		printf("lookup for '%s' failed\n", args);
+}
+
+
+/*
+ *  debugger_cmd_machine():
+ *
+ *  Dump info about the currently focused machine.
+ */
+static void debugger_cmd_machine(struct machine *m, char *args)
+{
+	if (*args) {
+		printf("syntax: machine\n");
+		return;
+	}
+
+	if (m->name != NULL && m->name[0])
+		debugmsg(SUBSYS_MACHINE, "", VERBOSITY_INFO, "%s", m->name);
+	else
+		debugmsg(SUBSYS_MACHINE, "", VERBOSITY_INFO, "");
+
+	debug_indentation(1);
+	machine_dumpinfo(m);
+	debug_indentation(-1);
+}
+
+
+/*
+ *  debugger_cmd_ninstrs():
+ */
+static void debugger_cmd_ninstrs(struct machine *m, char *args)
+{
+	int toggle = 1;
+	int previous_mode = m->show_nr_of_instructions;
+
+	if (args[0] != '\0') {
+		while (args[0] != '\0' && args[0] == ' ')
+			args ++;
+		switch (args[0]) {
+		case '0':
+			toggle = 0;
+			m->show_nr_of_instructions = 0;
+			break;
+		case '1':
+			toggle = 0;
+			m->show_nr_of_instructions = 1;
+			break;
+		case 'o':
+		case 'O':
+			toggle = 0;
+			switch (args[1]) {
+			case 'n':
+			case 'N':
+				m->show_nr_of_instructions = 1;
+				break;
+			default:
+				m->show_nr_of_instructions = 0;
+			}
+			break;
+		default:
+			printf("syntax: trace [on|off]\n");
+			return;
+		}
+	}
+
+	if (toggle)
+		m->show_nr_of_instructions = !m->show_nr_of_instructions;
+
+	printf("show_nr_of_instructions = %s",
+	    m->show_nr_of_instructions? "ON" : "OFF");
+	if (m->show_nr_of_instructions != previous_mode)
+		printf("  (was: %s)", previous_mode? "ON" : "OFF");
+	printf("\n");
+}
+
+
+/*
+ *  debugger_cmd_pause():
+ */
+static void debugger_cmd_pause(struct machine *m, char *args)
+{
+	int cpuid = -1;
+
+	if (args[0] != '\0')
+		cpuid = atoi(args);
+	else {
+		printf("syntax: pause cpuid\n");
+		return;
+	}
+
+	if (cpuid < 0 || cpuid >= m->ncpus) {
+		printf("cpu%i doesn't exist.\n", cpuid);
+		return;
+	}
+
+	m->cpus[cpuid]->running = !m->cpus[cpuid]->running;
+
+	printf("cpu%i (%s) in machine \"%s\" is now %s\n", cpuid,
+	    m->cpus[cpuid]->name, m->name,
+	    m->cpus[cpuid]->running? "RUNNING" : "STOPPED");
+}
+
+
+/*
+ *  debugger_cmd_print():
+ */
+static void debugger_cmd_print(struct machine *m, char *args)
+{
+	int res;
+	uint64_t tmp;
+
+	while (args[0] != '\0' && args[0] == ' ')
+		args ++;
+
+	if (args[0] == '\0') {
+		printf("syntax: print expr\n");
+		return;
+	}
+
+	res = debugger_parse_expression(m, args, 0, &tmp);
+	switch (res) {
+	case PARSE_NOMATCH:
+		printf("No match.\n");
+		break;
+	case PARSE_MULTIPLE:
+		printf("Multiple matches. Try prefixing with %%, $, or @.\n");
+		break;
+	case PARSE_SETTINGS:
+		printf("%s = 0x%" PRIx64"\n", args, (uint64_t)tmp);
+		break;
+	case PARSE_SYMBOL:
+		if (m->cpus[0]->is_32bit)
+			printf("%s = 0x%08" PRIx32"\n", args, (uint32_t)tmp);
+		else
+			printf("%s = 0x%016" PRIx64"\n", args,(uint64_t)tmp);
+		break;
+	case PARSE_NUMBER:
+		printf("0x%" PRIx64"\n", (uint64_t) tmp);
+		break;
+	}
+}
+
+
+/*
+ *  debugger_cmd_put():
+ */
+static void debugger_cmd_put(struct machine *m, char *args)
+{
+	static char put_type = ' ';  /*  Remembered across multiple calls.  */
+	char copy[200];
+	int res, syntax_ok = 0;
+	char *p, *p2, *q = NULL;
+	uint64_t addr, data;
+	unsigned char a_byte;
+
+	strncpy(copy, args, sizeof(copy));
+	copy[sizeof(copy)-1] = '\0';
+
+	/*  syntax: put [b|h|w|d|q] addr, data  */
+
+	p = strchr(copy, ',');
+	if (p != NULL) {
+		*p++ = '\0';
+		while (*p == ' ' && *p)
+			p++;
+		while (strlen(copy) >= 1 &&
+		    copy[strlen(copy) - 1] == ' ')
+			copy[strlen(copy) - 1] = '\0';
+
+		/*  printf("L = '%s', R = '%s'\n", copy, p);  */
+
+		q = copy;
+		p2 = strchr(q, ' ');
+
+		if (p2 != NULL) {
+			*p2 = '\0';
+			if (strlen(q) != 1) {
+				printf("Invalid type '%s'\n", q);
+				return;
+			}
+			put_type = *q;
+			q = p2 + 1;
+		}
+
+		/*  printf("type '%c', L '%s', R '%s'\n", put_type, q, p);  */
+		syntax_ok = 1;
+	}
+
+	if (!syntax_ok) {
+		printf("syntax: put [b|h|w|d|q] addr, data\n");
+		printf("   b    byte        (8 bits)\n");
+		printf("   h    half-word   (16 bits)\n");
+		printf("   w    word        (32 bits)\n");
+		printf("   d    doubleword  (64 bits)\n");
+		printf("   q    quad-word   (128 bits)\n");
+		return;
+	}
+
+	if (put_type == ' ') {
+		printf("No type specified.\n");
+		return;
+	}
+
+	/*  here: q is the address, p is the data.  */
+	res = debugger_parse_expression(m, q, 0, &addr);
+	switch (res) {
+	case PARSE_NOMATCH:
+		printf("Couldn't parse the address.\n");
+		return;
+	case PARSE_MULTIPLE:
+		printf("Multiple matches for the address."
+		    " Try prefixing with %%, $, or @.\n");
+		return;
+	case PARSE_SETTINGS:
+	case PARSE_SYMBOL:
+	case PARSE_NUMBER:
+		break;
+	default:
+		printf("INTERNAL ERROR in debugger.c.\n");
+		return;
+	}
+
+	res = debugger_parse_expression(m, p, 0, &data);
+	switch (res) {
+	case PARSE_NOMATCH:
+		printf("Couldn't parse the data.\n");
+		return;
+	case PARSE_MULTIPLE:
+		printf("Multiple matches for the data value."
+		    " Try prefixing with %%, $, or @.\n");
+		return;
+	case PARSE_SETTINGS:
+	case PARSE_SYMBOL:
+	case PARSE_NUMBER:
+		break;
+	default:
+		printf("INTERNAL ERROR in debugger.c.\n");
+		return;
+	}
+
+	/*  TODO: haha, maybe this should be refactored  */
+
+	switch (put_type) {
+	case 'b':
+		a_byte = data;
+		if (m->cpus[0]->is_32bit)
+			printf("0x%08" PRIx32, (uint32_t) addr);
+		else
+			printf("0x%016" PRIx64, (uint64_t) addr);
+		printf(": %02x", a_byte);
+		if (data > 255)
+			printf(" (NOTE: truncating %0" PRIx64")",
+			    (uint64_t) data);
+		res = m->cpus[0]->memory_rw(m->cpus[0], m->cpus[0]->mem, addr,
+		    &a_byte, 1, MEM_WRITE, CACHE_NONE | NO_EXCEPTIONS);
+		if (!res)
+			printf("  FAILED!\n");
+		printf("\n");
+		return;
+	case 'h':
+		if ((addr & 1) != 0)
+			printf("WARNING: address isn't aligned\n");
+		if (m->cpus[0]->is_32bit)
+			printf("0x%08" PRIx32, (uint32_t) addr);
+		else
+			printf("0x%016" PRIx64, (uint64_t) addr);
+		printf(": %04x", (int)data);
+		if (data > 0xffff)
+			printf(" (NOTE: truncating %0" PRIx64")",
+			    (uint64_t) data);
+		res = store_16bit_word(m->cpus[0], addr, data);
+		if (!res)
+			printf("  FAILED!\n");
+		printf("\n");
+		return;
+	case 'w':
+		if ((addr & 3) != 0)
+			printf("WARNING: address isn't aligned\n");
+		if (m->cpus[0]->is_32bit)
+			printf("0x%08" PRIx32, (uint32_t) addr);
+		else
+			printf("0x%016" PRIx64, (uint64_t) addr);
+
+		printf(": %08x", (int)data);
+
+		if (data > 0xffffffff && (data >> 32) != 0
+		    && (data >> 32) != 0xffffffff)
+			printf(" (NOTE: truncating %0" PRIx64")",
+			    (uint64_t) data);
+
+		res = store_32bit_word(m->cpus[0], addr, data);
+		if (!res)
+			printf("  FAILED!\n");
+		printf("\n");
+		return;
+	case 'd':
+		if ((addr & 7) != 0)
+			printf("WARNING: address isn't aligned\n");
+		if (m->cpus[0]->is_32bit)
+			printf("0x%08" PRIx32, (uint32_t) addr);
+		else
+			printf("0x%016" PRIx64, (uint64_t) addr);
+
+		printf(": %016" PRIx64, (uint64_t) data);
+
+		res = store_64bit_word(m->cpus[0], addr, data);
+		if (!res)
+			printf("  FAILED!\n");
+		printf("\n");
+		return;
+	case 'q':
+		printf("quad-words: TODO\n");
+		/*  TODO  */
+		return;
+	default:
+		printf("Unimplemented type '%c'\n", put_type);
+		return;
+	}
+}
+
+
+/*
+ *  debugger_cmd_quiet():
+ */
+static void debugger_cmd_quiet(struct machine *m, char *args)
+{
+	int toggle = 1;
+	int previous_mode = old_quiet_mode;
+
+	if (args[0] != '\0') {
+		while (args[0] != '\0' && args[0] == ' ')
+			args ++;
+		switch (args[0]) {
+		case '0':
+			toggle = 0;
+			old_quiet_mode = 0;
+			break;
+		case '1':
+			toggle = 0;
+			old_quiet_mode = 1;
+			break;
+		case 'o':
+		case 'O':
+			toggle = 0;
+			switch (args[1]) {
+			case 'n':
+			case 'N':
+				old_quiet_mode = 1;
+				break;
+			default:
+				old_quiet_mode = 0;
+			}
+			break;
+		default:
+			printf("syntax: quiet [on|off]\n");
+			return;
+		}
+	}
+
+	if (toggle)
+		old_quiet_mode = 1 - old_quiet_mode;
+
+	printf("quiet_mode = %s", old_quiet_mode? "ON" : "OFF");
+	if (old_quiet_mode != previous_mode)
+		printf(" (was: %s)", previous_mode? "ON" : "OFF");
+	printf("; setting verbosity for all subsystems to %s\n",
+	    old_quiet_mode ? "ERROR" : "WARNING");
+
+	debugmsg_set_verbosity_level(SUBSYS_ALL,
+	    old_quiet_mode ? VERBOSITY_ERROR : VERBOSITY_WARNING);
+}
+
+
+/*
+ *  debugger_cmd_quit():
+ */
+static void debugger_cmd_quit(struct machine *m, char *args)
+{
+	if (*args) {
+		printf("syntax: quit\n");
+		return;
+	}
+
+	emul_shutdown = true;
+	exit_debugger = true;
+}
+
+
+/*
+ *  debugger_cmd_reg():
+ */
+static void debugger_cmd_reg(struct machine *m, char *args)
+{
+	int cpuid = debugger_cur_cpu, coprocnr = -1;
+	int gprs, coprocs;
+	char *p;
+
+	/*  [cpuid][,c]  */
+	if (args[0] != '\0') {
+		if (args[0] != ',') {
+			cpuid = strtoull(args, NULL, 0);
+			if (cpuid < 0 || cpuid >= m->ncpus) {
+				printf("cpu%i doesn't exist.\n", cpuid);
+				return;
+			}
+		}
+		p = strchr(args, ',');
+		if (p != NULL) {
+			coprocnr = atoi(p + 1);
+			if (coprocnr < 0 || coprocnr >= 4) {
+				printf("Invalid coprocessor number.\n");
+				return;
+			}
+		}
+	}
+
+	gprs = (coprocnr == -1)? 1 : 0;
+	coprocs = (coprocnr == -1)? 0x0 : (1 << coprocnr);
+
+	cpu_register_dump(m, m->cpus[cpuid], gprs, coprocs);
+}
+
+
+/*
+ *  debugger_cmd_step():
+ */
+static void debugger_cmd_step(struct machine *m, char *args)
+{
+	int n = 1;
+
+	if (args[0] != '\0') {
+		n = strtoull(args, NULL, 0);
+		if (n < 1) {
+			printf("invalid nr of steps\n");
+			return;
+		}
+	}
+
+	debugger_n_steps_left_before_interaction = n - 1;
+
+	/*  Special hack, see the main debugger() loop for more info.  */
+	exit_debugger = true;
+	exit_debugger_to_continue_single_stepping = true;
+
+	strlcpy(repeat_cmd, "step", MAX_CMD_BUFLEN);
+}
+
+
+/*
+ *  debugger_cmd_tlbdump():
+ *
+ *  Dumps a CPU's TLB content.
+ */
+static void debugger_cmd_tlbdump(struct machine *m, char *args)
+{
+	int x = 0;
+	int rawflag = 0;
+
+	if (args[0] != '\0') {
+		char *p;
+		if (args[0] != ',') {
+			x = strtoull(args, NULL, 0);
+			if (x < 0 || x >= m->ncpus) {
+				printf("cpu%i doesn't exist.\n", x);
+				return;
+			}
+		}
+		p = strchr(args, ',');
+		if (p != NULL) {
+			switch (p[1]) {
+			case 'r':
+			case 'R':
+				rawflag = 1;
+				break;
+			default:
+				printf("Unknown tlbdump flag.\n");
+				printf("syntax: tlbdump [cpuid][,r]\n");
+				return;
+			}
+		}
+	}
+
+	cpu_tlbdump(m->cpus[x], rawflag);
+}
+
+
+/*
+ *  debugger_cmd_trace():
+ */
+static void debugger_cmd_trace(struct machine *m, char *args)
+{
+	int toggle = 1;
+	int previous_mode = m->show_trace_tree;
+
+	if (args[0] != '\0') {
+		while (args[0] != '\0' && args[0] == ' ')
+			args ++;
+		switch (args[0]) {
+		case '0':
+			toggle = 0;
+			m->show_trace_tree = 0;
+			break;
+		case '1':
+			toggle = 0;
+			m->show_trace_tree = 1;
+			break;
+		case 'o':
+		case 'O':
+			toggle = 0;
+			switch (args[1]) {
+			case 'n':
+			case 'N':
+				m->show_trace_tree = 1;
+				break;
+			default:
+				m->show_trace_tree = 0;
+			}
+			break;
+		default:
+			printf("syntax: trace [on|off]\n");
+			return;
+		}
+	}
+
+	if (toggle)
+		m->show_trace_tree = !m->show_trace_tree;
+
+	printf("show_trace_tree = %s", m->show_trace_tree? "ON" : "OFF");
+	if (m->show_trace_tree != previous_mode)
+		printf("  (was: %s)", previous_mode? "ON" : "OFF");
+	printf("\n");
+}
+
+
+/*
+ *  debugger_cmd_unassemble():
+ *
+ *  Dump emulated memory as instructions.
+ *
+ *  syntax: unassemble [addr [endaddr]]
+ */
+static void debugger_cmd_unassemble(struct machine *m, char *args)
+{
+	uint64_t addr, addr_start, addr_end;
+	struct cpu *c;
+	struct memory *mem;
+	char *p = NULL;
+	int r, lines_left = -1;
+
+	if (args[0] != '\0') {
+		uint64_t tmp;
+		char *tmps;
+
+		CHECK_ALLOCATION(tmps = strdup(args));
+
+		/*  addr:  */
+		p = strchr(tmps, ' ');
+		if (p != NULL)
+			*p = '\0';
+		r = debugger_parse_expression(m, tmps, 0, &tmp);
+		free(tmps);
+
+		if (r == PARSE_NOMATCH || r == PARSE_MULTIPLE) {
+			printf("Unparsable address: %s\n", args);
+			return;
+		} else {
+			last_unasm_addr = tmp;
+		}
+
+		p = strchr(args, ' ');
+	}
+
+	if (m->cpus == NULL) {
+		printf("No cpus (?)\n");
+		return;
+	}
+	c = m->cpus[m->bootstrap_cpu];
+	if (c == NULL) {
+		printf("m->cpus[m->bootstrap_cpu] = NULL\n");
+		return;
+	}
+	mem = m->cpus[m->bootstrap_cpu]->mem;
+
+	addr_start = last_unasm_addr;
+
+	if (addr_start == MAGIC_UNTOUCHED)
+		addr_start = c->pc;
+
+	addr_end = addr_start + 1000;
+
+	/*  endaddr:  */
+	if (p != NULL) {
+		while (*p == ' ' && *p)
+			p++;
+		r = debugger_parse_expression(m, p, 0, &addr_end);
+		if (r == PARSE_NOMATCH || r == PARSE_MULTIPLE) {
+			printf("Unparsable address: %s\n", args);
+			return;
+		}
+	} else
+		lines_left = 20;
+
+	addr = addr_start;
+
+	ctrl_c = 0;
+
+	while (addr < addr_end) {
+		unsigned int i, len;
+		int failed = 0;
+		unsigned char buf[17];	/*  TODO: How long can an
+					    instruction be, on weird archs?  */
+		memset(buf, 0, sizeof(buf));
+
+		for (i=0; i<sizeof(buf); i++) {
+			uint64_t actualaddr = addr;
+
+			// Hack for ARM (THUMB): (Lowest bit = 1 means 16-bit encoding)
+			if (c->cpu_family->arch == ARCH_ARM)
+				actualaddr &= ~1;
+
+			if (c->memory_rw(c, mem, actualaddr+i, buf+i, 1, MEM_READ,
+			    CACHE_NONE | NO_EXCEPTIONS) == MEMORY_ACCESS_FAILED)
+				failed ++;
+		}
+
+		if (failed == sizeof(buf)) {
+			printf("(memory access failed)\n");
+			break;
+		}
+
+		len = cpu_disassemble_instr(m, c, buf, 0, addr);
+
+		if (ctrl_c)
+			return;
+		if (len == 0)
+			break;
+
+		addr += len;
+
+		if (lines_left != -1) {
+			lines_left --;
+			if (lines_left == 0)
+				break;
+		}
+	}
+
+	last_unasm_addr = addr;
+
+	strlcpy(repeat_cmd, "unassemble", MAX_CMD_BUFLEN);
+}
+
+
+/*
+ *  debugger_cmd_verbosity():
+ */
+static void debugger_cmd_verbosity(struct machine *m, char *args)
+{
+	char *subsystem = args;
+	char *n = subsystem;
+	if (*n) {
+		while (*n && *n != ' ')
+			n++;
+		while (*n && *n == ' ')
+			n++;
+	}
+
+	if (*n == '\0') {
+		debugmsg_print_settings(subsystem);
+		return;
+	}
+
+	char s[200];
+	snprintf(s, sizeof(s), "%s", subsystem);
+	size_t i = n - subsystem - 1;
+	if (i < sizeof(s))
+		s[i] = '\0';
+	else {
+		printf("syntax: verbosity [subsystem [n]]\n");
+		return;
+	}
+
+	char *n2 = n;
+	while (*n2 && *n2 != ' ')
+		n2++;
+	*n2 = '\0';
+
+	/* printf("subsystem = '%s'\n", s);
+	if (*n)
+		printf("n = '%s'\n", n);
+	*/
+
+	debugmsg_change_settings(s, n);
+}
+
+
+/*
+ *  debugger_cmd_version():
+ */
+static void debugger_cmd_version(struct machine *m, char *args)
+{
+	if (*args) {
+		printf("syntax: version\n");
+		return;
+	}
+
+	printf("%s, %s\n", VERSION, COMPILE_DATE);
+}
+
+
+/****************************************************************************/
+
+
+struct cmd {
+	const char	*name;
+	const char	*args;
+	int		tmp_flag;
+	void		(*f)(struct machine *, char *args);
+	const char	*description;
+};
+
+static struct cmd cmds[] = {
+	{ "allsettings", "", 0, debugger_cmd_allsettings,
+		"show all settings" },
+
+	{ "breakpoint", "...", 0, debugger_cmd_breakpoint,
+		"manipulate breakpoints" },
+
+	/*  NOTE: Try to keep 'c' down to only one command. Having 'continue'
+	    available as a one-letter command is very convenient.  */
+
+	{ "continue", "", 0, debugger_cmd_continue,
+		"continue execution" },
+
+	{ "device", "...", 0, debugger_cmd_device,
+		"show info about (or manipulate) devices" },
+
+	{ "dump", "[addr [endaddr]]", 0, debugger_cmd_dump,
+		"dump memory contents in hex and ASCII" },
+
+	{ "emul", "", 0, debugger_cmd_emul,
+		"Print a summary of the current emulation" },
+
+	{ "focus", "x[,y[,z]]", 0, debugger_cmd_focus,
+		"changes focus to cpu x, machine x, emul z" },
+
+	{ "help", "", 0, debugger_cmd_help,
+		"Print this help message" },
+
+	{ "itrace", "", 0, debugger_cmd_itrace,
+		"toggle instruction_trace on or off" },
+
+	{ "lookup", "name|addr", 0, debugger_cmd_lookup,
+		"lookup a symbol by name or address" },
+
+	{ "machine", "", 0, debugger_cmd_machine,
+		"Print a summary of the current machine" },
+
+	{ "ninstrs", "[on|off]", 0, debugger_cmd_ninstrs,
+		"toggle (set or unset) show_nr_of_instructions" },
+
+	{ "pause", "cpuid", 0, debugger_cmd_pause,
+		"pause (or unpause) a CPU" },
+
+	{ "print", "expr", 0, debugger_cmd_print,
+		"evaluate an expression without side-effects" },
+
+	{ "put", "[b|h|w|d|q] addr, data", 0, debugger_cmd_put,
+		"modify emulated memory contents" },
+
+	{ "quiet", "[on|off]", 0, debugger_cmd_quiet,
+		"toggle quiet_mode on or off" },
+
+	{ "quit", "", 0, debugger_cmd_quit,
+		"quit the emulator" },
+
+	/*  NOTE: Try to keep 'r' down to only one command. Having 'reg'
+	    available as a one-letter command is very convenient.  */
+
+	{ "reg", "[cpuid][,c]", 0, debugger_cmd_reg,
+		"show GPRs (or coprocessor c's registers)" },
+
+	/*  NOTE: Try to keep 's' down to only one command. Having 'step'
+	    available as a one-letter command is very convenient.  */
+
+	{ "step", "[n]", 0, debugger_cmd_step,
+		"single-step one (or n) instruction(s)" },
+
+	{ "tlbdump", "[cpuid][,r]", 0, debugger_cmd_tlbdump,
+		"dump TLB contents (add ',r' for raw data)" },
+
+	{ "trace", "[on|off]", 0, debugger_cmd_trace,
+		"toggle show_trace_tree on or off" },
+
+	/*  NOTE: Try to keep 'u' down to only one command. Having 'unassemble'
+	    available as a one-letter command is very convenient.  */
+
+	{ "unassemble", "[addr [endaddr]]", 0, debugger_cmd_unassemble,
+		"dump memory contents as instructions" },
+
+	{ "verbosity", "[subsystem [n]]", 0, debugger_cmd_verbosity,
+		"sets or displays debug message verbosity levels" },
+
+	{ "version", "", 0, debugger_cmd_version,
+		"Print version information" },
+
+	/*  Note: NULL handler.  */
+	{ "x = expr", "", 0, NULL, "generic assignment" },
+
+	{ NULL, NULL, 0, NULL, NULL }
+};
+
+
+/*
+ *  debugger_cmd_help():
+ *
+ *  Print a list of available commands.
+ *
+ *  NOTE: This is placed after the cmds[] array, because it needs to
+ *  access it.
+ *
+ *  TODO: Command completion (ie just type "help s" for "help step").
+ */
+static void debugger_cmd_help(struct machine *m, char *args)
+{
+	int only_one = 0, only_one_match = 0;
+	char *nlines_env = getenv("LINES");
+	int nlines = atoi(nlines_env != NULL? nlines_env : "999999"), curlines;
+	size_t i, j, max_name_len = 0;
+
+	if (args[0] != '\0') {
+		only_one = 1;
+	}
+
+	i = 0;
+	while (cmds[i].name != NULL) {
+		size_t a = strlen(cmds[i].name);
+		if (cmds[i].args != NULL)
+			a += 1 + strlen(cmds[i].args);
+		if (a > max_name_len)
+			max_name_len = a;
+		i++;
+	}
+
+	curlines = 0;
+	if (!only_one) {
+		printf("Available commands:\n");
+		curlines++;
+	}
+
+	i = 0;
+	while (cmds[i].name != NULL) {
+		char buf[100];
+		snprintf(buf, sizeof(buf), "%s", cmds[i].name);
+
+		if (only_one) {
+			if (strcmp(cmds[i].name, args) != 0) {
+				i++;
+				continue;
+			}
+			only_one_match = 1;
+		}
+
+		if (cmds[i].args != NULL)
+			snprintf(buf + strlen(buf), sizeof(buf) - strlen(buf),
+			    " %s", cmds[i].args);
+
+		printf("  ");
+		for (j=0; j<max_name_len; j++)
+			if (j < strlen(buf))
+				printf("%c", buf[j]);
+			else
+				printf(" ");
+
+		printf("  %s\n", cmds[i].description);
+		i++;
+
+		curlines ++;
+		if (curlines >= nlines - 1) {
+			char ch;
+			printf("-- more --"); fflush(stdout);
+			ch = debugger_readchar();
+			printf("\n");
+			if (ch == 'q' || ch == 'Q')
+				return;
+			curlines = 0;
+		}
+	}
+
+	if (only_one) {
+		if (!only_one_match)
+			printf("%s: no such command\n", args);
+		return;
+	}
+
+	/*  TODO: generalize/refactor  */
+	curlines += 8;
+	if (curlines > nlines - 1) {
+		char ch;
+		printf("-- more --"); fflush(stdout);
+		ch = debugger_readchar();
+		printf("\n");
+		if (ch == 'q' || ch == 'Q')
+			return;
+		curlines = 0;
+	}
+
+	printf("\nIn generic assignments, x must be a register or other "
+	    "writable settings\nvariable, and expr can contain registers/"
+	    "settings, numeric values, or symbol\nnames, in combination with"
+	    " parenthesis and + - * / & %% ^ | operators.\nIn case there are"
+	    " multiple matches (i.e. a symbol that has the same name as a\n"
+	    "register), you may add a prefix character as a hint: '#' for"
+	    " registers, '@'\nfor symbols, and '$' for numeric values. Use"
+	    " 0x for hexadecimal values.\n");
+}
+
diff -Nru gxemul-0.6.2/src/debugger/debugger_cmds.cc gxemul-0.7.0+dfsg/src/debugger/debugger_cmds.cc
--- gxemul-0.6.2/src/debugger/debugger_cmds.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/debugger/debugger_cmds.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1389 +0,0 @@
-/*
- *  Copyright (C) 2004-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Debugger commands. Included from debugger.c.
- */
-
-
-/*
- *  debugger_cmd_allsettings():
- */
-static void debugger_cmd_allsettings(struct machine *m, char *cmd_line)
-{
-	settings_debugdump(global_settings, GLOBAL_SETTINGS_NAME, 1);
-}
-
-
-/*
- *  debugger_cmd_breakpoint():
- *
- *  TODO: automagic "expansion" for the subcommand names (s => show).
- */
-static void debugger_cmd_breakpoint(struct machine *m, char *cmd_line)
-{
-	int i, res;
-
-	while (cmd_line[0] != '\0' && cmd_line[0] == ' ')
-		cmd_line ++;
-
-	if (cmd_line[0] == '\0') {
-		printf("syntax: breakpoint subcmd [args...]\n");
-		printf("Available subcmds (and args) are:\n");
-		printf("  add addr      add a breakpoint for address addr\n");
-		printf("  delete x      delete breakpoint nr x\n");
-		printf("  show          show current breakpoints\n");
-		return;
-	}
-
-	if (strcmp(cmd_line, "show") == 0) {
-		if (m->breakpoints.n == 0)
-			printf("No breakpoints set.\n");
-		for (i=0; i<m->breakpoints.n; i++)
-			show_breakpoint(m, i);
-		return;
-	}
-
-	if (strncmp(cmd_line, "delete ", 7) == 0) {
-		int x = atoi(cmd_line + 7);
-
-		if (m->breakpoints.n == 0) {
-			printf("No breakpoints set.\n");
-			return;
-		}
-		if (x < 0 || x > m->breakpoints.n) {
-			printf("Invalid breakpoint nr %i. Use 'breakpoint "
-			    "show' to see the current breakpoints.\n", x);
-			return;
-		}
-
-		free(m->breakpoints.string[x]);
-
-		for (i=x; i<m->breakpoints.n-1; i++) {
-			m->breakpoints.addr[i]   = m->breakpoints.addr[i+1];
-			m->breakpoints.string[i] = m->breakpoints.string[i+1];
-		}
-		m->breakpoints.n --;
-
-		/*  Clear translations:  */
-		for (i=0; i<m->ncpus; i++)
-			if (m->cpus[i]->translation_cache != NULL)
-				cpu_create_or_reset_tc(m->cpus[i]);
-		return;
-	}
-
-	if (strncmp(cmd_line, "add ", 4) == 0) {
-		uint64_t tmp;
-		size_t breakpoint_buf_len;
-
-		i = m->breakpoints.n;
-
-		res = debugger_parse_expression(m, cmd_line + 4, 0, &tmp);
-		if (!res) {
-			printf("Couldn't parse '%s'\n", cmd_line + 4);
-			return;
-		}
-
-		CHECK_ALLOCATION(m->breakpoints.string = (char **) realloc(
-		    m->breakpoints.string, sizeof(char *) *
-		    (m->breakpoints.n + 1)));
-		CHECK_ALLOCATION(m->breakpoints.addr = (uint64_t *) realloc(
-		    m->breakpoints.addr, sizeof(uint64_t) *
-		   (m->breakpoints.n + 1)));
-
-		breakpoint_buf_len = strlen(cmd_line+4) + 1;
-
-		CHECK_ALLOCATION(m->breakpoints.string[i] = (char *)
-		    malloc(breakpoint_buf_len));
-		strlcpy(m->breakpoints.string[i], cmd_line+4,
-		    breakpoint_buf_len);
-		m->breakpoints.addr[i] = tmp;
-
-		m->breakpoints.n ++;
-		show_breakpoint(m, i);
-
-		/*  Clear translations:  */
-		for (i=0; i<m->ncpus; i++)
-			if (m->cpus[i]->translation_cache != NULL)
-				cpu_create_or_reset_tc(m->cpus[i]);
-		return;
-	}
-
-	printf("Unknown breakpoint subcommand.\n");
-}
-
-
-/*
- *  debugger_cmd_continue():
- */
-static void debugger_cmd_continue(struct machine *m, char *cmd_line)
-{
-	if (*cmd_line) {
-		printf("syntax: continue\n");
-		return;
-	}
-
-	exit_debugger = 1;
-}
-
-
-/*
- *  debugger_cmd_device():
- */
-static void debugger_cmd_device(struct machine *m, char *cmd_line)
-{
-	int i;
-	struct memory *mem;
-	struct cpu *c;
-
-	if (cmd_line[0] == '\0')
-		goto return_help;
-
-	if (m->cpus == NULL) {
-		printf("No cpus (?)\n");
-		return;
-	}
-	c = m->cpus[m->bootstrap_cpu];
-	if (c == NULL) {
-		printf("m->cpus[m->bootstrap_cpu] = NULL\n");
-		return;
-	}
-	mem = m->cpus[m->bootstrap_cpu]->mem;
-
-	if (m->cpus == NULL) {
-		printf("No cpus (?)\n");
-		return;
-	}
-	c = m->cpus[m->bootstrap_cpu];
-	if (c == NULL) {
-		printf("m->cpus[m->bootstrap_cpu] = NULL\n");
-		return;
-	}
-	mem = m->cpus[m->bootstrap_cpu]->mem;
-
-	if (strcmp(cmd_line, "all") == 0) {
-		device_dumplist();
-	} else if (strncmp(cmd_line, "add ", 4) == 0) {
-		device_add(m, cmd_line+4);
-	} else if (strcmp(cmd_line, "consoles") == 0) {
-		console_debug_dump(m);
-	} else if (strncmp(cmd_line, "remove ", 7) == 0) {
-		i = atoi(cmd_line + 7);
-		if (i==0 && cmd_line[7]!='0') {
-			printf("Weird device number. Use 'device list'.\n");
-		} else
-			memory_device_remove(m->memory, i);
-	} else if (strcmp(cmd_line, "list") == 0) {
-		if (mem->n_mmapped_devices == 0)
-			printf("No memory-mapped devices in this machine.\n");
-
-		for (i=0; i<mem->n_mmapped_devices; i++) {
-			printf("%2i: %25s @ 0x%011" PRIx64", len = 0x%" PRIx64,
-			    i, mem->devices[i].name,
-			    (uint64_t) mem->devices[i].baseaddr,
-			    (uint64_t) mem->devices[i].length);
-
-			if (mem->devices[i].flags) {
-				printf(" (");
-				if (mem->devices[i].flags & DM_DYNTRANS_OK)
-					printf("DYNTRANS R");
-				if (mem->devices[i].flags &DM_DYNTRANS_WRITE_OK)
-					printf("+W");
-				printf(")");
-			}
-			printf("\n");
-		}
-	} else
-		goto return_help;
-
-	return;
-
-return_help:
-	printf("syntax: devices cmd [...]\n");
-	printf("Available cmds are:\n");
-	printf("  add name_and_params    add a device to the current "
-	    "machine\n");
-	printf("  all                    list all registered devices\n");
-	printf("  consoles               list all slave consoles\n");
-	printf("  list                   list memory-mapped devices in the"
-	    " current machine\n");
-	printf("  remove x               remove device nr x from the "
-	    "current machine\n");
-}
-
-
-/*
- *  debugger_cmd_dump():
- *
- *  Dump emulated memory in hex and ASCII.
- *
- *  syntax: dump [addr [endaddr]]
- */
-static void debugger_cmd_dump(struct machine *m, char *cmd_line)
-{
-	uint64_t addr, addr_start, addr_end;
-	struct cpu *c;
-	struct memory *mem;
-	char *p = NULL;
-	int x, r;
-
-	if (cmd_line[0] != '\0') {
-		uint64_t tmp;
-		char *tmps;
-
-		CHECK_ALLOCATION(tmps = strdup(cmd_line));
-
-		/*  addr:  */
-		p = strchr(tmps, ' ');
-		if (p != NULL)
-			*p = '\0';
-		r = debugger_parse_expression(m, tmps, 0, &tmp);
-		free(tmps);
-
-		if (r == PARSE_NOMATCH || r == PARSE_MULTIPLE) {
-			printf("Unparsable address: %s\n", cmd_line);
-			return;
-		} else {
-			last_dump_addr = tmp;
-		}
-
-		p = strchr(cmd_line, ' ');
-	}
-
-	if (m->cpus == NULL) {
-		printf("No cpus (?)\n");
-		return;
-	}
-	c = m->cpus[m->bootstrap_cpu];
-	if (c == NULL) {
-		printf("m->cpus[m->bootstrap_cpu] = NULL\n");
-		return;
-	}
-	mem = m->cpus[m->bootstrap_cpu]->mem;
-
-	addr_start = last_dump_addr;
-
-	if (addr_start == MAGIC_UNTOUCHED)
-		addr_start = c->pc;
-
-	addr_end = addr_start + 16 * 16;
-
-	/*  endaddr:  */
-	if (p != NULL) {
-		while (*p == ' ' && *p)
-			p++;
-		r = debugger_parse_expression(m, p, 0, &addr_end);
-		if (r == PARSE_NOMATCH || r == PARSE_MULTIPLE) {
-			printf("Unparsable address: %s\n", cmd_line);
-			return;
-		}
-	}
-
-	addr = addr_start & ~0xf;
-
-	ctrl_c = 0;
-
-	while (addr < addr_end) {
-		unsigned char buf[16];
-		memset(buf, 0, sizeof(buf));
-		r = c->memory_rw(c, mem, addr, &buf[0], sizeof(buf),
-		    MEM_READ, CACHE_NONE | NO_EXCEPTIONS);
-
-		if (c->is_32bit)
-			printf("0x%08" PRIx32"  ", (uint32_t) addr);
-		else
-			printf("0x%016" PRIx64"  ", (uint64_t) addr);
-
-		if (r == MEMORY_ACCESS_FAILED)
-			printf("(memory access failed)\n");
-		else {
-			for (x=0; x<16; x++) {
-				if (addr + x >= addr_start &&
-				    addr + x < addr_end)
-					printf("%02x%s", buf[x],
-					    (x&3)==3? " " : "");
-				else
-					printf("  %s", (x&3)==3? " " : "");
-			}
-			printf(" ");
-			for (x=0; x<16; x++) {
-				if (addr + x >= addr_start &&
-				    addr + x < addr_end)
-					printf("%c", (buf[x]>=' ' &&
-					    buf[x]<127)? buf[x] : '.');
-				else
-					printf(" ");
-			}
-			printf("\n");
-		}
-
-		if (ctrl_c)
-			return;
-
-		addr += sizeof(buf);
-	}
-
-	last_dump_addr = addr_end;
-
-	strlcpy(repeat_cmd, "dump", MAX_CMD_BUFLEN);
-}
-
-
-/*
- *  debugger_cmd_emul():
- *
- *  Dump info about the current emulation.
- */
-static void debugger_cmd_emul(struct machine *m, char *cmd_line)
-{
-	int iadd = DEBUG_INDENTATION;
-
-	if (*cmd_line) {
-		printf("syntax: emul\n");
-		return;
-	}
-
-	debug("emulation \"%s\":\n", debugger_emul->name == NULL?
-	    "(simple setup)" : debugger_emul->name);
-
-	debug_indentation(iadd);
-	emul_dumpinfo(debugger_emul);
-	debug_indentation(-iadd);
-}
-
-
-/*
- *  debugger_cmd_focus():
- *
- *  Changes focus to specific cpu, in a specific machine (in a specific
- *  emulation).
- */
-static void debugger_cmd_focus(struct machine *m, char *cmd_line)
-{
-	int x = -1, y = -1;
-	char *p, *p2;
-
-	if (!cmd_line[0]) {
-		printf("syntax: focus x[,y]\n");
-		printf("where x (cpu id) and y (machine number) "
-		    "are integers as\nreported by the 'emul'"
-		    " command.\n");
-		goto print_current_focus_and_return;
-	}
-
-	x = atoi(cmd_line);
-	p = strchr(cmd_line, ',');
-	if (p == cmd_line) {
-		printf("No cpu number specified?\n");
-		return;
-	}
-
-	if (p != NULL) {
-		y = atoi(p+1);
-		p2 = strchr(p+1, ',');
-		if (p2 == p+1) {
-			printf("No machine number specified?\n");
-			return;
-		}
-	}
-
-	if (y != -1) {
-		/*  Change machine:  */
-		if (y < 0 || y >= debugger_emul->n_machines) {
-			printf("Invalid machine number: %i\n", y);
-			return;
-		}
-
-		debugger_cur_machine = y;
-		debugger_machine = debugger_emul->machines[y];
-	}
-
-	/*  Change cpu:  */
-	if (x < 0 || x >= debugger_machine->ncpus) {
-		printf("Invalid cpu number: %i\n", x);
-		return;
-	}
-
-	debugger_cur_cpu = x;
-
-print_current_focus_and_return:
-	if (debugger_emul->n_machines > 1)
-		printf("current machine (%i): \"%s\"\n",
-		    debugger_cur_machine, debugger_machine->name == NULL?
-		    "(no name)" : debugger_machine->name);
-
-	printf("current cpu (%i)\n", debugger_cur_cpu);
-}
-
-
-/*  This is defined below.  */
-static void debugger_cmd_help(struct machine *m, char *cmd_line);
-
-
-/*
- *  debugger_cmd_itrace():
- */
-static void debugger_cmd_itrace(struct machine *m, char *cmd_line)
-{
-	if (*cmd_line) {
-		printf("syntax: itrace\n");
-		return;
-	}
-
-	old_instruction_trace = 1 - old_instruction_trace;
-	printf("instruction_trace = %s\n", old_instruction_trace? "ON":"OFF");
-	/*  TODO: how to preserve quiet_mode?  */
-	old_quiet_mode = 0;
-	printf("quiet_mode = %s\n", old_quiet_mode? "ON" : "OFF");
-}
-
-
-/*
- *  debugger_cmd_lookup():
- */
-static void debugger_cmd_lookup(struct machine *m, char *cmd_line)
-{
-	uint64_t addr;
-	int res;
-	char *symbol;
-	uint64_t offset;
-
-	if (cmd_line[0] == '\0') {
-		printf("syntax: lookup name|addr\n");
-		return;
-
-	}
-
-	/*  Addresses never need to be given in decimal form anyway,
-	    so assuming hex here will be ok.  */
-	addr = strtoull(cmd_line, NULL, 16);
-
-	if (addr == 0) {
-		uint64_t newaddr;
-		res = get_symbol_addr(&m->symbol_context,
-		    cmd_line, &newaddr);
-		if (!res) {
-			printf("lookup for '%s' failed\n", cmd_line);
-			return;
-		}
-		printf("%s = 0x", cmd_line);
-		if (m->cpus[0]->is_32bit)
-			printf("%08" PRIx32"\n", (uint32_t) newaddr);
-		else
-			printf("%016" PRIx64"\n", (uint64_t) newaddr);
-		return;
-	}
-
-	symbol = get_symbol_name(&m->symbol_context, addr, &offset);
-
-	if (symbol != NULL) {
-		if (m->cpus[0]->is_32bit)
-			printf("0x%08" PRIx32, (uint32_t) addr);
-		else
-			printf("0x%016" PRIx64, (uint64_t) addr);
-		printf(" = %s\n", symbol);
-	} else
-		printf("lookup for '%s' failed\n", cmd_line);
-}
-
-
-/*
- *  debugger_cmd_machine():
- *
- *  Dump info about the currently focused machine.
- */
-static void debugger_cmd_machine(struct machine *m, char *cmd_line)
-{
-	int iadd = 0;
-
-	if (*cmd_line) {
-		printf("syntax: machine\n");
-		return;
-	}
-
-	if (m->name != NULL) {
-		debug("machine \"%s\":\n", m->name);
-		iadd = DEBUG_INDENTATION;
-	}
-
-	debug_indentation(iadd);
-	machine_dumpinfo(m);
-	debug_indentation(-iadd);
-}
-
-
-/*
- *  debugger_cmd_ninstrs():
- */
-static void debugger_cmd_ninstrs(struct machine *m, char *cmd_line)
-{
-	int toggle = 1;
-	int previous_mode = m->show_nr_of_instructions;
-
-	if (cmd_line[0] != '\0') {
-		while (cmd_line[0] != '\0' && cmd_line[0] == ' ')
-			cmd_line ++;
-		switch (cmd_line[0]) {
-		case '0':
-			toggle = 0;
-			m->show_nr_of_instructions = 0;
-			break;
-		case '1':
-			toggle = 0;
-			m->show_nr_of_instructions = 1;
-			break;
-		case 'o':
-		case 'O':
-			toggle = 0;
-			switch (cmd_line[1]) {
-			case 'n':
-			case 'N':
-				m->show_nr_of_instructions = 1;
-				break;
-			default:
-				m->show_nr_of_instructions = 0;
-			}
-			break;
-		default:
-			printf("syntax: trace [on|off]\n");
-			return;
-		}
-	}
-
-	if (toggle)
-		m->show_nr_of_instructions = !m->show_nr_of_instructions;
-
-	printf("show_nr_of_instructions = %s",
-	    m->show_nr_of_instructions? "ON" : "OFF");
-	if (m->show_nr_of_instructions != previous_mode)
-		printf("  (was: %s)", previous_mode? "ON" : "OFF");
-	printf("\n");
-}
-
-
-/*
- *  debugger_cmd_pause():
- */
-static void debugger_cmd_pause(struct machine *m, char *cmd_line)
-{
-	int cpuid = -1;
-
-	if (cmd_line[0] != '\0')
-		cpuid = atoi(cmd_line);
-	else {
-		printf("syntax: pause cpuid\n");
-		return;
-	}
-
-	if (cpuid < 0 || cpuid >= m->ncpus) {
-		printf("cpu%i doesn't exist.\n", cpuid);
-		return;
-	}
-
-	m->cpus[cpuid]->running ^= 1;
-
-	printf("cpu%i (%s) in machine \"%s\" is now %s\n", cpuid,
-	    m->cpus[cpuid]->name, m->name,
-	    m->cpus[cpuid]->running? "RUNNING" : "STOPPED");
-}
-
-
-/*
- *  debugger_cmd_print():
- */
-static void debugger_cmd_print(struct machine *m, char *cmd_line)
-{
-	int res;
-	uint64_t tmp;
-
-	while (cmd_line[0] != '\0' && cmd_line[0] == ' ')
-		cmd_line ++;
-
-	if (cmd_line[0] == '\0') {
-		printf("syntax: print expr\n");
-		return;
-	}
-
-	res = debugger_parse_expression(m, cmd_line, 0, &tmp);
-	switch (res) {
-	case PARSE_NOMATCH:
-		printf("No match.\n");
-		break;
-	case PARSE_MULTIPLE:
-		printf("Multiple matches. Try prefixing with %%, $, or @.\n");
-		break;
-	case PARSE_SETTINGS:
-		printf("%s = 0x%" PRIx64"\n", cmd_line, (uint64_t)tmp);
-		break;
-	case PARSE_SYMBOL:
-		if (m->cpus[0]->is_32bit)
-			printf("%s = 0x%08" PRIx32"\n", cmd_line, (uint32_t)tmp);
-		else
-			printf("%s = 0x%016" PRIx64"\n", cmd_line,(uint64_t)tmp);
-		break;
-	case PARSE_NUMBER:
-		printf("0x%" PRIx64"\n", (uint64_t) tmp);
-		break;
-	}
-}
-
-
-/*
- *  debugger_cmd_put():
- */
-static void debugger_cmd_put(struct machine *m, char *cmd_line)
-{
-	static char put_type = ' ';  /*  Remembered across multiple calls.  */
-	char copy[200];
-	int res, syntax_ok = 0;
-	char *p, *p2, *q = NULL;
-	uint64_t addr, data;
-	unsigned char a_byte;
-
-	strncpy(copy, cmd_line, sizeof(copy));
-	copy[sizeof(copy)-1] = '\0';
-
-	/*  syntax: put [b|h|w|d|q] addr, data  */
-
-	p = strchr(copy, ',');
-	if (p != NULL) {
-		*p++ = '\0';
-		while (*p == ' ' && *p)
-			p++;
-		while (strlen(copy) >= 1 &&
-		    copy[strlen(copy) - 1] == ' ')
-			copy[strlen(copy) - 1] = '\0';
-
-		/*  printf("L = '%s', R = '%s'\n", copy, p);  */
-
-		q = copy;
-		p2 = strchr(q, ' ');
-
-		if (p2 != NULL) {
-			*p2 = '\0';
-			if (strlen(q) != 1) {
-				printf("Invalid type '%s'\n", q);
-				return;
-			}
-			put_type = *q;
-			q = p2 + 1;
-		}
-
-		/*  printf("type '%c', L '%s', R '%s'\n", put_type, q, p);  */
-		syntax_ok = 1;
-	}
-
-	if (!syntax_ok) {
-		printf("syntax: put [b|h|w|d|q] addr, data\n");
-		printf("   b    byte        (8 bits)\n");
-		printf("   h    half-word   (16 bits)\n");
-		printf("   w    word        (32 bits)\n");
-		printf("   d    doubleword  (64 bits)\n");
-		printf("   q    quad-word   (128 bits)\n");
-		return;
-	}
-
-	if (put_type == ' ') {
-		printf("No type specified.\n");
-		return;
-	}
-
-	/*  here: q is the address, p is the data.  */
-	res = debugger_parse_expression(m, q, 0, &addr);
-	switch (res) {
-	case PARSE_NOMATCH:
-		printf("Couldn't parse the address.\n");
-		return;
-	case PARSE_MULTIPLE:
-		printf("Multiple matches for the address."
-		    " Try prefixing with %%, $, or @.\n");
-		return;
-	case PARSE_SETTINGS:
-	case PARSE_SYMBOL:
-	case PARSE_NUMBER:
-		break;
-	default:
-		printf("INTERNAL ERROR in debugger.c.\n");
-		return;
-	}
-
-	res = debugger_parse_expression(m, p, 0, &data);
-	switch (res) {
-	case PARSE_NOMATCH:
-		printf("Couldn't parse the data.\n");
-		return;
-	case PARSE_MULTIPLE:
-		printf("Multiple matches for the data value."
-		    " Try prefixing with %%, $, or @.\n");
-		return;
-	case PARSE_SETTINGS:
-	case PARSE_SYMBOL:
-	case PARSE_NUMBER:
-		break;
-	default:
-		printf("INTERNAL ERROR in debugger.c.\n");
-		return;
-	}
-
-	/*  TODO: haha, maybe this should be refactored  */
-
-	switch (put_type) {
-	case 'b':
-		a_byte = data;
-		if (m->cpus[0]->is_32bit)
-			printf("0x%08" PRIx32, (uint32_t) addr);
-		else
-			printf("0x%016" PRIx64, (uint64_t) addr);
-		printf(": %02x", a_byte);
-		if (data > 255)
-			printf(" (NOTE: truncating %0" PRIx64")",
-			    (uint64_t) data);
-		res = m->cpus[0]->memory_rw(m->cpus[0], m->cpus[0]->mem, addr,
-		    &a_byte, 1, MEM_WRITE, CACHE_NONE | NO_EXCEPTIONS);
-		if (!res)
-			printf("  FAILED!\n");
-		printf("\n");
-		return;
-	case 'h':
-		if ((addr & 1) != 0)
-			printf("WARNING: address isn't aligned\n");
-		if (m->cpus[0]->is_32bit)
-			printf("0x%08" PRIx32, (uint32_t) addr);
-		else
-			printf("0x%016" PRIx64, (uint64_t) addr);
-		printf(": %04x", (int)data);
-		if (data > 0xffff)
-			printf(" (NOTE: truncating %0" PRIx64")",
-			    (uint64_t) data);
-		res = store_16bit_word(m->cpus[0], addr, data);
-		if (!res)
-			printf("  FAILED!\n");
-		printf("\n");
-		return;
-	case 'w':
-		if ((addr & 3) != 0)
-			printf("WARNING: address isn't aligned\n");
-		if (m->cpus[0]->is_32bit)
-			printf("0x%08" PRIx32, (uint32_t) addr);
-		else
-			printf("0x%016" PRIx64, (uint64_t) addr);
-
-		printf(": %08x", (int)data);
-
-		if (data > 0xffffffff && (data >> 32) != 0
-		    && (data >> 32) != 0xffffffff)
-			printf(" (NOTE: truncating %0" PRIx64")",
-			    (uint64_t) data);
-
-		res = store_32bit_word(m->cpus[0], addr, data);
-		if (!res)
-			printf("  FAILED!\n");
-		printf("\n");
-		return;
-	case 'd':
-		if ((addr & 7) != 0)
-			printf("WARNING: address isn't aligned\n");
-		if (m->cpus[0]->is_32bit)
-			printf("0x%08" PRIx32, (uint32_t) addr);
-		else
-			printf("0x%016" PRIx64, (uint64_t) addr);
-
-		printf(": %016" PRIx64, (uint64_t) data);
-
-		res = store_64bit_word(m->cpus[0], addr, data);
-		if (!res)
-			printf("  FAILED!\n");
-		printf("\n");
-		return;
-	case 'q':
-		printf("quad-words: TODO\n");
-		/*  TODO  */
-		return;
-	default:
-		printf("Unimplemented type '%c'\n", put_type);
-		return;
-	}
-}
-
-
-/*
- *  debugger_cmd_quiet():
- */
-static void debugger_cmd_quiet(struct machine *m, char *cmd_line)
-{
-	int toggle = 1;
-	int previous_mode = old_quiet_mode;
-
-	if (cmd_line[0] != '\0') {
-		while (cmd_line[0] != '\0' && cmd_line[0] == ' ')
-			cmd_line ++;
-		switch (cmd_line[0]) {
-		case '0':
-			toggle = 0;
-			old_quiet_mode = 0;
-			break;
-		case '1':
-			toggle = 0;
-			old_quiet_mode = 1;
-			break;
-		case 'o':
-		case 'O':
-			toggle = 0;
-			switch (cmd_line[1]) {
-			case 'n':
-			case 'N':
-				old_quiet_mode = 1;
-				break;
-			default:
-				old_quiet_mode = 0;
-			}
-			break;
-		default:
-			printf("syntax: quiet [on|off]\n");
-			return;
-		}
-	}
-
-	if (toggle)
-		old_quiet_mode = 1 - old_quiet_mode;
-
-	printf("quiet_mode = %s", old_quiet_mode? "ON" : "OFF");
-	if (old_quiet_mode != previous_mode)
-		printf("  (was: %s)", previous_mode? "ON" : "OFF");
-	printf("\n");
-}
-
-
-/*
- *  debugger_cmd_quit():
- */
-static void debugger_cmd_quit(struct machine *m, char *cmd_line)
-{
-	int j, k;
-
-	if (*cmd_line) {
-		printf("syntax: quit\n");
-		return;
-	}
-
-	single_step = NOT_SINGLE_STEPPING;
-
-	force_debugger_at_exit = 0;
-
-	for (j=0; j<debugger_emul->n_machines; j++) {
-		struct machine *mp = debugger_emul->machines[j];
-
-		for (k=0; k<mp->ncpus; k++)
-			mp->cpus[k]->running = 0;
-
-		mp->exit_without_entering_debugger = 1;
-	}
-
-	exit_debugger = 1;
-}
-
-
-/*
- *  debugger_cmd_reg():
- */
-static void debugger_cmd_reg(struct machine *m, char *cmd_line)
-{
-	int cpuid = debugger_cur_cpu, coprocnr = -1;
-	int gprs, coprocs;
-	char *p;
-
-	/*  [cpuid][,c]  */
-	if (cmd_line[0] != '\0') {
-		if (cmd_line[0] != ',') {
-			cpuid = strtoull(cmd_line, NULL, 0);
-			if (cpuid < 0 || cpuid >= m->ncpus) {
-				printf("cpu%i doesn't exist.\n", cpuid);
-				return;
-			}
-		}
-		p = strchr(cmd_line, ',');
-		if (p != NULL) {
-			coprocnr = atoi(p + 1);
-			if (coprocnr < 0 || coprocnr >= 4) {
-				printf("Invalid coprocessor number.\n");
-				return;
-			}
-		}
-	}
-
-	gprs = (coprocnr == -1)? 1 : 0;
-	coprocs = (coprocnr == -1)? 0x0 : (1 << coprocnr);
-
-	cpu_register_dump(m, m->cpus[cpuid], gprs, coprocs);
-}
-
-
-/*
- *  debugger_cmd_step():
- */
-static void debugger_cmd_step(struct machine *m, char *cmd_line)
-{
-	int n = 1;
-
-	if (cmd_line[0] != '\0') {
-		n = strtoull(cmd_line, NULL, 0);
-		if (n < 1) {
-			printf("invalid nr of steps\n");
-			return;
-		}
-	}
-
-	debugger_n_steps_left_before_interaction = n - 1;
-
-	/*  Special hack, see debugger() for more info.  */
-	exit_debugger = -1;
-
-	strlcpy(repeat_cmd, "step", MAX_CMD_BUFLEN);
-}
-
-
-/*
- *  debugger_cmd_tlbdump():
- *
- *  Dump each CPU's TLB contents.
- */
-static void debugger_cmd_tlbdump(struct machine *m, char *cmd_line)
-{
-	int x = -1;
-	int rawflag = 0;
-
-	if (cmd_line[0] != '\0') {
-		char *p;
-		if (cmd_line[0] != ',') {
-			x = strtoull(cmd_line, NULL, 0);
-			if (x < 0 || x >= m->ncpus) {
-				printf("cpu%i doesn't exist.\n", x);
-				return;
-			}
-		}
-		p = strchr(cmd_line, ',');
-		if (p != NULL) {
-			switch (p[1]) {
-			case 'r':
-			case 'R':
-				rawflag = 1;
-				break;
-			default:
-				printf("Unknown tlbdump flag.\n");
-				printf("syntax: tlbdump [cpuid][,r]\n");
-				return;
-			}
-		}
-	}
-
-	cpu_tlbdump(m, x, rawflag);
-}
-
-
-/*
- *  debugger_cmd_trace():
- */
-static void debugger_cmd_trace(struct machine *m, char *cmd_line)
-{
-	int toggle = 1;
-	int previous_mode = old_show_trace_tree;
-
-	if (cmd_line[0] != '\0') {
-		while (cmd_line[0] != '\0' && cmd_line[0] == ' ')
-			cmd_line ++;
-		switch (cmd_line[0]) {
-		case '0':
-			toggle = 0;
-			old_show_trace_tree = 0;
-			break;
-		case '1':
-			toggle = 0;
-			old_show_trace_tree = 1;
-			break;
-		case 'o':
-		case 'O':
-			toggle = 0;
-			switch (cmd_line[1]) {
-			case 'n':
-			case 'N':
-				old_show_trace_tree = 1;
-				break;
-			default:
-				old_show_trace_tree = 0;
-			}
-			break;
-		default:
-			printf("syntax: trace [on|off]\n");
-			return;
-		}
-	}
-
-	if (toggle)
-		old_show_trace_tree = 1 - old_show_trace_tree;
-
-	printf("show_trace_tree = %s", old_show_trace_tree? "ON" : "OFF");
-	if (old_show_trace_tree != previous_mode)
-		printf("  (was: %s)", previous_mode? "ON" : "OFF");
-	printf("\n");
-}
-
-
-/*
- *  debugger_cmd_unassemble():
- *
- *  Dump emulated memory as instructions.
- *
- *  syntax: unassemble [addr [endaddr]]
- */
-static void debugger_cmd_unassemble(struct machine *m, char *cmd_line)
-{
-	uint64_t addr, addr_start, addr_end;
-	struct cpu *c;
-	struct memory *mem;
-	char *p = NULL;
-	int r, lines_left = -1;
-
-	if (cmd_line[0] != '\0') {
-		uint64_t tmp;
-		char *tmps;
-
-		CHECK_ALLOCATION(tmps = strdup(cmd_line));
-
-		/*  addr:  */
-		p = strchr(tmps, ' ');
-		if (p != NULL)
-			*p = '\0';
-		r = debugger_parse_expression(m, tmps, 0, &tmp);
-		free(tmps);
-
-		if (r == PARSE_NOMATCH || r == PARSE_MULTIPLE) {
-			printf("Unparsable address: %s\n", cmd_line);
-			return;
-		} else {
-			last_unasm_addr = tmp;
-		}
-
-		p = strchr(cmd_line, ' ');
-	}
-
-	if (m->cpus == NULL) {
-		printf("No cpus (?)\n");
-		return;
-	}
-	c = m->cpus[m->bootstrap_cpu];
-	if (c == NULL) {
-		printf("m->cpus[m->bootstrap_cpu] = NULL\n");
-		return;
-	}
-	mem = m->cpus[m->bootstrap_cpu]->mem;
-
-	addr_start = last_unasm_addr;
-
-	if (addr_start == MAGIC_UNTOUCHED)
-		addr_start = c->pc;
-
-	addr_end = addr_start + 1000;
-
-	/*  endaddr:  */
-	if (p != NULL) {
-		while (*p == ' ' && *p)
-			p++;
-		r = debugger_parse_expression(m, p, 0, &addr_end);
-		if (r == PARSE_NOMATCH || r == PARSE_MULTIPLE) {
-			printf("Unparsable address: %s\n", cmd_line);
-			return;
-		}
-	} else
-		lines_left = 20;
-
-	addr = addr_start;
-
-	ctrl_c = 0;
-
-	while (addr < addr_end) {
-		unsigned int i, len;
-		int failed = 0;
-		unsigned char buf[17];	/*  TODO: How long can an
-					    instruction be, on weird archs?  */
-		memset(buf, 0, sizeof(buf));
-
-		for (i=0; i<sizeof(buf); i++) {
-			uint64_t actualaddr = addr;
-
-			// Hack for ARM (THUMB): (Lowest bit = 1 means 16-bit encoding)
-			if (m->arch == ARCH_ARM)
-				actualaddr &= ~1;
-
-			if (c->memory_rw(c, mem, actualaddr+i, buf+i, 1, MEM_READ,
-			    CACHE_NONE | NO_EXCEPTIONS) == MEMORY_ACCESS_FAILED)
-				failed ++;
-		}
-
-		if (failed == sizeof(buf)) {
-			printf("(memory access failed)\n");
-			break;
-		}
-
-		len = cpu_disassemble_instr(m, c, buf, 0, addr);
-
-		if (ctrl_c)
-			return;
-		if (len == 0)
-			break;
-
-		addr += len;
-
-		if (lines_left != -1) {
-			lines_left --;
-			if (lines_left == 0)
-				break;
-		}
-	}
-
-	last_unasm_addr = addr;
-
-	strlcpy(repeat_cmd, "unassemble", MAX_CMD_BUFLEN);
-}
-
-
-/*
- *  debugger_cmd_version():
- */
-static void debugger_cmd_version(struct machine *m, char *cmd_line)
-{
-	if (*cmd_line) {
-		printf("syntax: version\n");
-		return;
-	}
-
-	printf("%s, %s\n", VERSION, COMPILE_DATE);
-}
-
-
-/****************************************************************************/
-
-
-struct cmd {
-	const char	*name;
-	const char	*args;
-	int		tmp_flag;
-	void		(*f)(struct machine *, char *cmd_line);
-	const char	*description;
-};
-
-static struct cmd cmds[] = {
-	{ "allsettings", "", 0, debugger_cmd_allsettings,
-		"show all settings" },
-
-	{ "breakpoint", "...", 0, debugger_cmd_breakpoint,
-		"manipulate breakpoints" },
-
-	/*  NOTE: Try to keep 'c' down to only one command. Having 'continue'
-	    available as a one-letter command is very convenient.  */
-
-	{ "continue", "", 0, debugger_cmd_continue,
-		"continue execution" },
-
-	{ "device", "...", 0, debugger_cmd_device,
-		"show info about (or manipulate) devices" },
-
-	{ "dump", "[addr [endaddr]]", 0, debugger_cmd_dump,
-		"dump memory contents in hex and ASCII" },
-
-	{ "emul", "", 0, debugger_cmd_emul,
-		"Print a summary of the current emulation" },
-
-	{ "focus", "x[,y[,z]]", 0, debugger_cmd_focus,
-		"changes focus to cpu x, machine x, emul z" },
-
-	{ "help", "", 0, debugger_cmd_help,
-		"Print this help message" },
-
-	{ "itrace", "", 0, debugger_cmd_itrace,
-		"toggle instruction_trace on or off" },
-
-	{ "lookup", "name|addr", 0, debugger_cmd_lookup,
-		"lookup a symbol by name or address" },
-
-	{ "machine", "", 0, debugger_cmd_machine,
-		"Print a summary of the current machine" },
-
-	{ "ninstrs", "[on|off]", 0, debugger_cmd_ninstrs,
-		"toggle (set or unset) show_nr_of_instructions" },
-
-	{ "pause", "cpuid", 0, debugger_cmd_pause,
-		"pause (or unpause) a CPU" },
-
-	{ "print", "expr", 0, debugger_cmd_print,
-		"evaluate an expression without side-effects" },
-
-	{ "put", "[b|h|w|d|q] addr, data", 0, debugger_cmd_put,
-		"modify emulated memory contents" },
-
-	{ "quiet", "[on|off]", 0, debugger_cmd_quiet,
-		"toggle quiet_mode on or off" },
-
-	{ "quit", "", 0, debugger_cmd_quit,
-		"quit the emulator" },
-
-	/*  NOTE: Try to keep 'r' down to only one command. Having 'reg'
-	    available as a one-letter command is very convenient.  */
-
-	{ "reg", "[cpuid][,c]", 0, debugger_cmd_reg,
-		"show GPRs (or coprocessor c's registers)" },
-
-	/*  NOTE: Try to keep 's' down to only one command. Having 'step'
-	    available as a one-letter command is very convenient.  */
-
-	{ "step", "[n]", 0, debugger_cmd_step,
-		"single-step one (or n) instruction(s)" },
-
-	{ "tlbdump", "[cpuid][,r]", 0, debugger_cmd_tlbdump,
-		"dump TLB contents (add ',r' for raw data)" },
-
-	{ "trace", "[on|off]", 0, debugger_cmd_trace,
-		"toggle show_trace_tree on or off" },
-
-	/*  NOTE: Try to keep 'u' down to only one command. Having 'unassemble'
-	    available as a one-letter command is very convenient.  */
-
-	{ "unassemble", "[addr [endaddr]]", 0, debugger_cmd_unassemble,
-		"dump memory contents as instructions" },
-
-	{ "version", "", 0, debugger_cmd_version,
-		"Print version information" },
-
-	/*  Note: NULL handler.  */
-	{ "x = expr", "", 0, NULL, "generic assignment" },
-
-	{ NULL, NULL, 0, NULL, NULL }
-};
-
-
-/*
- *  debugger_cmd_help():
- *
- *  Print a list of available commands.
- *
- *  NOTE: This is placed after the cmds[] array, because it needs to
- *  access it.
- *
- *  TODO: Command completion (ie just type "help s" for "help step").
- */
-static void debugger_cmd_help(struct machine *m, char *cmd_line)
-{
-	int only_one = 0, only_one_match = 0;
-	char *nlines_env = getenv("LINES");
-	int nlines = atoi(nlines_env != NULL? nlines_env : "999999"), curlines;
-	size_t i, j, max_name_len = 0;
-
-	if (cmd_line[0] != '\0') {
-		only_one = 1;
-	}
-
-	i = 0;
-	while (cmds[i].name != NULL) {
-		size_t a = strlen(cmds[i].name);
-		if (cmds[i].args != NULL)
-			a += 1 + strlen(cmds[i].args);
-		if (a > max_name_len)
-			max_name_len = a;
-		i++;
-	}
-
-	curlines = 0;
-	if (!only_one) {
-		printf("Available commands:\n");
-		curlines++;
-	}
-
-	i = 0;
-	while (cmds[i].name != NULL) {
-		char buf[100];
-		snprintf(buf, sizeof(buf), "%s", cmds[i].name);
-
-		if (only_one) {
-			if (strcmp(cmds[i].name, cmd_line) != 0) {
-				i++;
-				continue;
-			}
-			only_one_match = 1;
-		}
-
-		if (cmds[i].args != NULL)
-			snprintf(buf + strlen(buf), sizeof(buf) - strlen(buf),
-			    " %s", cmds[i].args);
-
-		printf("  ");
-		for (j=0; j<max_name_len; j++)
-			if (j < strlen(buf))
-				printf("%c", buf[j]);
-			else
-				printf(" ");
-
-		printf("   %s\n", cmds[i].description);
-		i++;
-
-		curlines ++;
-		if (curlines >= nlines - 1) {
-			char ch;
-			printf("-- more --"); fflush(stdout);
-			ch = debugger_readchar();
-			printf("\n");
-			if (ch == 'q' || ch == 'Q')
-				return;
-			curlines = 0;
-		}
-	}
-
-	if (only_one) {
-		if (!only_one_match)
-			printf("%s: no such command\n", cmd_line);
-		return;
-	}
-
-	/*  TODO: generalize/refactor  */
-	curlines += 8;
-	if (curlines > nlines - 1) {
-		char ch;
-		printf("-- more --"); fflush(stdout);
-		ch = debugger_readchar();
-		printf("\n");
-		if (ch == 'q' || ch == 'Q')
-			return;
-		curlines = 0;
-	}
-
-	printf("\nIn generic assignments, x must be a register or other "
-	    "writable settings\nvariable, and expr can contain registers/"
-	    "settings, numeric values, or symbol\nnames, in combination with"
-	    " parenthesis and + - * / & %% ^ | operators.\nIn case there are"
-	    " multiple matches (i.e. a symbol that has the same name as a\n"
-	    "register), you may add a prefix character as a hint: '#' for"
-	    " registers, '@'\nfor symbols, and '$' for numeric values. Use"
-	    " 0x for hexadecimal values.\n");
-}
-
diff -Nru gxemul-0.6.2/src/debugger/debugger_expr.c gxemul-0.7.0+dfsg/src/debugger/debugger_expr.c
--- gxemul-0.6.2/src/debugger/debugger_expr.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/debugger/debugger_expr.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,404 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Expression evaluator.
+ *
+ *
+ *  TODO:
+ *	Sign-extension is arch dependent (e.g. MIPS has it).
+ *	SPECIAL IMPORTANT CASE: Clear the delay_slot flag when writing
+ *		to the pc register.
+ *	TAB completion? :-)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+
+#include "cpu.h"
+#include "debugger.h"
+#include "machine.h"
+#include "misc.h"
+#include "settings.h"
+
+
+extern struct settings *global_settings;
+
+extern int debugger_cur_cpu;
+extern int debugger_cur_machine;
+
+
+/*
+ *  debugger_parse_name():
+ *
+ *  This function takes a string as input, and tries to match it to a register
+ *  name or a more general "setting", a hexadecimal or decimal numeric value,
+ *  or a registered symbol.
+ *
+ *  Some examples:
+ *
+ *	Settings (including register names):
+ *		verbose
+ *		pc
+ *		r5
+ *
+ *	Numeric values:
+ *		12345
+ *		0x7fff1234
+ *
+ *	Symbols:
+ *		memcpy
+ *
+ *  To force detection of different types, a character can be added in front of
+ *  the name: "$" for numeric values, "#" for registers or other settings,
+ *  and "@" for symbols.
+ *
+ *  Return value is:
+ *
+ *	PARSE_NOMATCH		no match
+ *	PARSE_MULTIPLE		multiple matches
+ *
+ *  or one of these (and then *valuep is read or written, depending on
+ *  the writeflag):
+ *
+ *	PARSE_SETTINGS		a setting (e.g. a register)
+ *	PARSE_NUMBER		a hex number
+ *	PARSE_SYMBOL		a symbol
+ */
+int debugger_parse_name(struct machine *m, char *name, int writeflag,
+	uint64_t *valuep)
+{
+	int match_settings = 0, match_symbol = 0, match_numeric = 0;
+	int skip_settings, skip_numeric, skip_symbol;
+
+	if (m == NULL || name == NULL) {
+		fprintf(stderr, "debugger_parse_name(): NULL ptr\n");
+		exit(1);
+	}
+
+	while (name[0] == '\t' || name[0] == ' ')
+		name ++;
+
+	/*  Warn about non-signextended values:  */
+	if (writeflag) {
+		if (m->cpus[0]->is_32bit) {
+			/*
+			 *  Automagically sign-extend for MIPS.
+			 *  TODO: Is this good?
+			 */
+			if (m->cpus[0]->cpu_family->arch == ARCH_MIPS &&
+			    ((*valuep) >> 32) == 0 && (*valuep) & 0x80000000ULL)
+				(*valuep) |= 0xffffffff00000000ULL;
+		} else {
+			if (((*valuep) >> 32) == 0 && (*valuep) & 0x80000000ULL)
+				printf("WARNING: The value is not sign-extende"
+				    "d. Is this what you intended?\n");
+		}
+	}
+
+	skip_settings = name[0] == '$' || name[0] == '@';
+	skip_numeric  = name[0] == '#' || name[0] == '@';
+	skip_symbol   = name[0] == '$' || name[0] == '#';
+
+	if (!skip_settings) {
+		char setting_name[400];
+		int res;
+
+		res = settings_access(global_settings, name, writeflag, valuep);
+		if (res == SETTINGS_OK)
+			match_settings = 1;
+
+		if (!match_settings) {
+			snprintf(setting_name, sizeof(setting_name),
+			    GLOBAL_SETTINGS_NAME".%s", name);
+			res = settings_access(global_settings, setting_name,
+			    writeflag, valuep);
+			if (res == SETTINGS_OK)
+				match_settings = 1;
+		}
+
+		if (!match_settings) {
+			snprintf(setting_name, sizeof(setting_name),
+			    GLOBAL_SETTINGS_NAME".emul.%s", name);
+			res = settings_access(global_settings, setting_name,
+			    writeflag, valuep);
+			if (res == SETTINGS_OK)
+				match_settings = 1;
+		}
+
+		if (!match_settings) {
+			snprintf(setting_name, sizeof(setting_name),
+			    GLOBAL_SETTINGS_NAME".emul.machine[%i].%s",
+			    debugger_cur_machine, name);
+			res = settings_access(global_settings, setting_name,
+			    writeflag, valuep);
+			if (res == SETTINGS_OK)
+				match_settings = 1;
+		}
+
+		if (!match_settings) {
+			snprintf(setting_name, sizeof(setting_name),
+			    GLOBAL_SETTINGS_NAME".emul.machine[%i]."
+			    "cpu[%i].%s", debugger_cur_machine,
+			    debugger_cur_cpu, name);
+			res = settings_access(global_settings, setting_name,
+			    writeflag, valuep);
+			if (res == SETTINGS_OK)
+				match_settings = 1;
+		}
+	}
+
+	/*  Check for a number match:  */
+	if (!skip_numeric && isdigit((int)name[0])) {
+		uint64_t x;
+		x = strtoull(name, NULL, 0);
+		if (writeflag)
+			printf("You cannot assign like that.\n");
+		else
+			*valuep = x;
+		match_numeric = 1;
+	}
+
+	/*  Check for a symbol match:  */
+	if (!skip_symbol) {
+		uint64_t newaddr;
+		if (get_symbol_addr(&m->symbol_context, name, &newaddr)) {
+			if (writeflag)
+				printf("You cannot assign like that.\n");
+			else
+				*valuep = newaddr;
+			match_symbol = 1;
+		}
+	}
+
+	if (match_settings + match_symbol + match_numeric > 1)
+		return PARSE_MULTIPLE;
+
+	if (match_settings)
+		return PARSE_SETTINGS;
+	if (match_numeric)
+		return PARSE_NUMBER;
+	if (match_symbol)
+		return PARSE_SYMBOL;
+
+	return PARSE_NOMATCH;
+}
+
+
+/*
+ *  debugger_parse_expression()
+ *
+ *  Input:
+ *	writeflag = 0:	expr = an expression to evaluate. The result is
+ *			returned in *valuep.
+ *
+ *	writeflag = 1:	expr = an lvalue name. *valuep is written to that
+ *			lvalue, using debugger_parse_name().
+ *
+ *  Parentheses always have precedence.
+ *  * / and % have second highest precedence.
+ *  + - & | ^ have lowest precedence.
+ *
+ *  Return value on failure is:
+ *
+ *	PARSE_NOMATCH		one or more words in the expression didn't
+ *				match any known symbol/register/number
+ *	PARSE_MULTIPLE		multiple matches within the expression
+ *
+ *  Return value on success is PARSE_NUMBER (for now).
+ *
+ *
+ *  TODO: BETTER RETURN VALUE!
+ *
+ *  NOTE: This is a quick hack, but hopefully it should work. The internal
+ *        mechanism is to split the expression into a left half and a right
+ *        half around an operator. This operator should be the operator
+ *        in the string which has the lowest precedence (except those that
+ *        are inside parentheses sub-expressions). E.g. if the expression
+ *        is   a * (b + c * d) / e   then the operator with the lowest
+ *        precedence is the first multiplication sign, and the split will
+ *        be:   left  = a
+ *              right = (b+c*d)/e
+ */
+int debugger_parse_expression(struct machine *m, char *expr, int writeflag,
+	uint64_t *valuep)
+{
+	int prec, res, i, nest;
+	char *copy;
+
+	if (writeflag)
+		return debugger_parse_name(m, expr, writeflag, valuep);
+
+	while (expr[0] == '\t' || expr[0] == ' ')
+		expr ++;
+
+	CHECK_ALLOCATION(copy = strdup(expr));
+
+	while (copy[0] && copy[strlen(copy)-1] == ' ')
+		copy[strlen(copy)-1] = '\0';
+
+	/*  Find the lowest operator precedence:  */
+	i = 0; prec = 2; nest = 0;
+	while (copy[i] != '\0') {
+		switch (copy[i]) {
+		case '(':
+			nest ++;
+			break;
+		case ')':
+			nest --;
+			break;
+		case '+':
+		case '-':
+		case '^':
+		case '&':
+		case '|':
+			if (nest == 0)
+				prec = 0;
+			break;
+		case '*':
+		case '/':
+		case '%':
+			if (nest == 0 && prec > 1)
+				prec = 1;
+			break;
+		}
+
+		i++;
+	}
+
+	if (nest != 0) {
+		printf("Unmatching parentheses.\n");
+		return PARSE_NOMATCH;
+	}
+
+	if (prec == 2 && copy[0] == '(' && copy[strlen(copy)-1] == ')') {
+		int res2;
+		copy[strlen(copy)-1] = '\0';
+		res2 = debugger_parse_expression(m, copy+1, 0, valuep);
+		free(copy);
+		return res2;
+	}
+
+	/*  Split according to the first lowest priority operator:  */
+	i = 0; nest = 0;
+	while (copy[i] != '\0') {
+		switch (copy[i]) {
+		case '(':
+			nest ++;
+			break;
+		case ')':
+			nest --;
+			break;
+		case '*':
+		case '/':
+		case '%':
+			if (prec == 0)
+				break;
+			/*  Fallthrough.  */
+		case '+':
+		case '-':
+		case '^':
+		case '&':
+		case '|':
+			if (nest == 0) {
+				uint64_t left, right;
+				int res1, res2, j;
+				char op = copy[i];
+
+				copy[i] = '\0';
+				j = i;
+				while (j>0 && copy[j-1] == ' ') {
+					copy[j-1] = '\0';
+					j --;
+				}
+
+				res1 = debugger_parse_expression(
+				    m, copy, 0, &left);
+				res2 = debugger_parse_expression(
+				    m, copy + i + 1, 0, &right);
+
+				if (res1 == PARSE_NOMATCH ||
+				    res2 == PARSE_NOMATCH) {
+					res = PARSE_NOMATCH;
+					goto return_failure;
+				}
+
+				if (res1 == PARSE_MULTIPLE ||
+				    res2 == PARSE_MULTIPLE) {
+					res = PARSE_MULTIPLE;
+					goto return_failure;
+				}
+
+				switch (op) {
+				case '+':
+					(*valuep) = left + right;
+					break;
+				case '-':
+					(*valuep) = left - right;
+					break;
+				case '^':
+					(*valuep) = left ^ right;
+					break;
+				case '&':
+					(*valuep) = left & right;
+					break;
+				case '|':
+					(*valuep) = left | right;
+					break;
+				case '*':
+					(*valuep) = left * right;
+					break;
+				case '/':
+					(*valuep) = left / right;
+					break;
+				case '%':
+					(*valuep) = left % right;
+					break;
+				}
+
+				goto return_ok;
+			}
+			break;
+		}
+
+		i ++;
+	}
+
+	res = debugger_parse_name(m, expr, writeflag, valuep);
+	if (res == PARSE_NOMATCH || res == PARSE_MULTIPLE)
+		goto return_failure;
+
+return_ok:
+	free(copy);
+	return PARSE_NUMBER;
+
+return_failure:
+	free(copy);
+	return res;
+}
+
diff -Nru gxemul-0.6.2/src/debugger/debugger_expr.cc gxemul-0.7.0+dfsg/src/debugger/debugger_expr.cc
--- gxemul-0.6.2/src/debugger/debugger_expr.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/debugger/debugger_expr.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,400 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Expression evaluator.
- *
- *
- *  TODO:
- *	Sign-extension is arch dependent (e.g. MIPS has it).
- *	SPECIAL IMPORTANT CASE: Clear the delay_slot flag when writing
- *		to the pc register.
- *	TAB completion? :-)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <ctype.h>
-
-#include "cpu.h"
-#include "debugger.h"
-#include "machine.h"
-#include "misc.h"
-#include "settings.h"
-
-
-extern struct settings *global_settings;
-
-extern int debugger_cur_cpu;
-extern int debugger_cur_machine;
-
-
-/*
- *  debugger_parse_name():
- *
- *  This function takes a string as input, and tries to match it to a register
- *  name or a more general "setting", a hexadecimal or decimal numeric value,
- *  or a registered symbol.
- *
- *  Some examples:
- *
- *	Settings (including register names):
- *		verbose
- *		pc
- *		r5
- *
- *	Numeric values:
- *		12345
- *		0x7fff1234
- *
- *	Symbols:
- *		memcpy
- *
- *  To force detection of different types, a character can be added in front of
- *  the name: "$" for numeric values, "#" for registers or other settings,
- *  and "@" for symbols.
- *
- *  Return value is:
- *
- *	PARSE_NOMATCH		no match
- *	PARSE_MULTIPLE		multiple matches
- *
- *  or one of these (and then *valuep is read or written, depending on
- *  the writeflag):
- *
- *	PARSE_SETTINGS		a setting (e.g. a register)
- *	PARSE_NUMBER		a hex number
- *	PARSE_SYMBOL		a symbol
- */
-int debugger_parse_name(struct machine *m, char *name, int writeflag,
-	uint64_t *valuep)
-{
-	int match_settings = 0, match_symbol = 0, match_numeric = 0;
-	int skip_settings, skip_numeric, skip_symbol;
-
-	if (m == NULL || name == NULL) {
-		fprintf(stderr, "debugger_parse_name(): NULL ptr\n");
-		exit(1);
-	}
-
-	while (name[0] == '\t' || name[0] == ' ')
-		name ++;
-
-	/*  Warn about non-signextended values:  */
-	if (writeflag) {
-		if (m->cpus[0]->is_32bit) {
-			/*  Automagically sign-extend.  TODO: Is this good?  */
-			if (((*valuep) >> 32) == 0 && (*valuep) & 0x80000000ULL)
-				(*valuep) |= 0xffffffff00000000ULL;
-		} else {
-			if (((*valuep) >> 32) == 0 && (*valuep) & 0x80000000ULL)
-				printf("WARNING: The value is not sign-extende"
-				    "d. Is this what you intended?\n");
-		}
-	}
-
-	skip_settings = name[0] == '$' || name[0] == '@';
-	skip_numeric  = name[0] == '#' || name[0] == '@';
-	skip_symbol   = name[0] == '$' || name[0] == '#';
-
-	if (!skip_settings) {
-		char setting_name[400];
-		int res;
-
-		res = settings_access(global_settings, name, writeflag, valuep);
-		if (res == SETTINGS_OK)
-			match_settings = 1;
-
-		if (!match_settings) {
-			snprintf(setting_name, sizeof(setting_name),
-			    GLOBAL_SETTINGS_NAME".%s", name);
-			res = settings_access(global_settings, setting_name,
-			    writeflag, valuep);
-			if (res == SETTINGS_OK)
-				match_settings = 1;
-		}
-
-		if (!match_settings) {
-			snprintf(setting_name, sizeof(setting_name),
-			    GLOBAL_SETTINGS_NAME".emul.%s", name);
-			res = settings_access(global_settings, setting_name,
-			    writeflag, valuep);
-			if (res == SETTINGS_OK)
-				match_settings = 1;
-		}
-
-		if (!match_settings) {
-			snprintf(setting_name, sizeof(setting_name),
-			    GLOBAL_SETTINGS_NAME".emul.machine[%i].%s",
-			    debugger_cur_machine, name);
-			res = settings_access(global_settings, setting_name,
-			    writeflag, valuep);
-			if (res == SETTINGS_OK)
-				match_settings = 1;
-		}
-
-		if (!match_settings) {
-			snprintf(setting_name, sizeof(setting_name),
-			    GLOBAL_SETTINGS_NAME".emul.machine[%i]."
-			    "cpu[%i].%s", debugger_cur_machine,
-			    debugger_cur_cpu, name);
-			res = settings_access(global_settings, setting_name,
-			    writeflag, valuep);
-			if (res == SETTINGS_OK)
-				match_settings = 1;
-		}
-	}
-
-	/*  Check for a number match:  */
-	if (!skip_numeric && isdigit((int)name[0])) {
-		uint64_t x;
-		x = strtoull(name, NULL, 0);
-		if (writeflag)
-			printf("You cannot assign like that.\n");
-		else
-			*valuep = x;
-		match_numeric = 1;
-	}
-
-	/*  Check for a symbol match:  */
-	if (!skip_symbol) {
-		uint64_t newaddr;
-		if (get_symbol_addr(&m->symbol_context, name, &newaddr)) {
-			if (writeflag)
-				printf("You cannot assign like that.\n");
-			else
-				*valuep = newaddr;
-			match_symbol = 1;
-		}
-	}
-
-	if (match_settings + match_symbol + match_numeric > 1)
-		return PARSE_MULTIPLE;
-
-	if (match_settings)
-		return PARSE_SETTINGS;
-	if (match_numeric)
-		return PARSE_NUMBER;
-	if (match_symbol)
-		return PARSE_SYMBOL;
-
-	return PARSE_NOMATCH;
-}
-
-
-/*
- *  debugger_parse_expression()
- *
- *  Input:
- *	writeflag = 0:	expr = an expression to evaluate. The result is
- *			returned in *valuep.
- *
- *	writeflag = 1:	expr = an lvalue name. *valuep is written to that
- *			lvalue, using debugger_parse_name().
- *
- *  Parentheses always have precedence.
- *  * / and % have second highest precedence.
- *  + - & | ^ have lowest precedence.
- *
- *  Return value on failure is:
- *
- *	PARSE_NOMATCH		one or more words in the expression didn't
- *				match any known symbol/register/number
- *	PARSE_MULTIPLE		multiple matches within the expression
- *
- *  Return value on success is PARSE_NUMBER (for now).
- *
- *
- *  TODO: BETTER RETURN VALUE!
- *
- *  NOTE: This is a quick hack, but hopefully it should work. The internal
- *        mechanism is to split the expression into a left half and a right
- *        half around an operator. This operator should be the operator
- *        in the string which has the lowest precedence (except those that
- *        are inside parentheses sub-expressions). E.g. if the expression
- *        is   a * (b + c * d) / e   then the operator with the lowest
- *        precedence is the first multiplication sign, and the split will
- *        be:   left  = a
- *              right = (b+c*d)/e
- */
-int debugger_parse_expression(struct machine *m, char *expr, int writeflag,
-	uint64_t *valuep)
-{
-	int prec, res, i, nest;
-	char *copy;
-
-	if (writeflag)
-		return debugger_parse_name(m, expr, writeflag, valuep);
-
-	while (expr[0] == '\t' || expr[0] == ' ')
-		expr ++;
-
-	CHECK_ALLOCATION(copy = strdup(expr));
-
-	while (copy[0] && copy[strlen(copy)-1] == ' ')
-		copy[strlen(copy)-1] = '\0';
-
-	/*  Find the lowest operator precedence:  */
-	i = 0; prec = 2; nest = 0;
-	while (copy[i] != '\0') {
-		switch (copy[i]) {
-		case '(':
-			nest ++;
-			break;
-		case ')':
-			nest --;
-			break;
-		case '+':
-		case '-':
-		case '^':
-		case '&':
-		case '|':
-			if (nest == 0)
-				prec = 0;
-			break;
-		case '*':
-		case '/':
-		case '%':
-			if (nest == 0 && prec > 1)
-				prec = 1;
-			break;
-		}
-
-		i++;
-	}
-
-	if (nest != 0) {
-		printf("Unmatching parentheses.\n");
-		return PARSE_NOMATCH;
-	}
-
-	if (prec == 2 && copy[0] == '(' && copy[strlen(copy)-1] == ')') {
-		int res2;
-		copy[strlen(copy)-1] = '\0';
-		res2 = debugger_parse_expression(m, copy+1, 0, valuep);
-		free(copy);
-		return res2;
-	}
-
-	/*  Split according to the first lowest priority operator:  */
-	i = 0; nest = 0;
-	while (copy[i] != '\0') {
-		switch (copy[i]) {
-		case '(':
-			nest ++;
-			break;
-		case ')':
-			nest --;
-			break;
-		case '*':
-		case '/':
-		case '%':
-			if (prec == 0)
-				break;
-			/*  Fallthrough.  */
-		case '+':
-		case '-':
-		case '^':
-		case '&':
-		case '|':
-			if (nest == 0) {
-				uint64_t left, right;
-				int res1, res2, j;
-				char op = copy[i];
-
-				copy[i] = '\0';
-				j = i;
-				while (j>0 && copy[j-1] == ' ') {
-					copy[j-1] = '\0';
-					j --;
-				}
-
-				res1 = debugger_parse_expression(
-				    m, copy, 0, &left);
-				res2 = debugger_parse_expression(
-				    m, copy + i + 1, 0, &right);
-
-				if (res1 == PARSE_NOMATCH ||
-				    res2 == PARSE_NOMATCH) {
-					res = PARSE_NOMATCH;
-					goto return_failure;
-				}
-
-				if (res1 == PARSE_MULTIPLE ||
-				    res2 == PARSE_MULTIPLE) {
-					res = PARSE_MULTIPLE;
-					goto return_failure;
-				}
-
-				switch (op) {
-				case '+':
-					(*valuep) = left + right;
-					break;
-				case '-':
-					(*valuep) = left - right;
-					break;
-				case '^':
-					(*valuep) = left ^ right;
-					break;
-				case '&':
-					(*valuep) = left & right;
-					break;
-				case '|':
-					(*valuep) = left | right;
-					break;
-				case '*':
-					(*valuep) = left * right;
-					break;
-				case '/':
-					(*valuep) = left / right;
-					break;
-				case '%':
-					(*valuep) = left % right;
-					break;
-				}
-
-				goto return_ok;
-			}
-			break;
-		}
-
-		i ++;
-	}
-
-	res = debugger_parse_name(m, expr, writeflag, valuep);
-	if (res == PARSE_NOMATCH || res == PARSE_MULTIPLE)
-		goto return_failure;
-
-return_ok:
-	free(copy);
-	return PARSE_NUMBER;
-
-return_failure:
-	free(copy);
-	return res;
-}
-
diff -Nru gxemul-0.6.2/src/debugger/Makefile.skel gxemul-0.7.0+dfsg/src/debugger/Makefile.skel
--- gxemul-0.6.2/src/debugger/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/debugger/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #  Makefile for GXemul src/debugger
 #
 
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
+CFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
 
 OBJS=debugger.o debugger_expr.o
 
@@ -10,7 +10,7 @@
 
 $(OBJS): Makefile
 
-debugger.cc: debugger_cmds.cc
+debugger.c: debugger_cmds.c
 
 clean:
 	rm -f $(OBJS) *core tmp_*.*c
diff -Nru gxemul-0.6.2/src/devices/autodev_head.c gxemul-0.7.0+dfsg/src/devices/autodev_head.c
--- gxemul-0.6.2/src/devices/autodev_head.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/autodev_head.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,39 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  Automatically register all devices from the devices/ subdir.
+ *
+ *  NOTE: autodev_head.c, plus a line for each device, plus autodev_middle.c,
+ *  plus another line (again) for each device, plus autodev_tail.c should be
+ *  combined into one. See makeautodev.sh for more info.
+ */
+
+#include <stdio.h>
+
+#include "bus_pci.h"
+#include "device.h"
+
diff -Nru gxemul-0.6.2/src/devices/autodev_head.cc gxemul-0.7.0+dfsg/src/devices/autodev_head.cc
--- gxemul-0.6.2/src/devices/autodev_head.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/autodev_head.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,39 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  Automatically register all devices from the devices/ subdir.
- *
- *  NOTE: autodev_head.c, plus a line for each device, plus autodev_middle.c,
- *  plus another line (again) for each device, plus autodev_tail.c should be
- *  combined into one. See makeautodev.sh for more info.
- */
-
-#include <stdio.h>
-
-#include "bus_pci.h"
-#include "device.h"
-
diff -Nru gxemul-0.6.2/src/devices/autodev_middle.c gxemul-0.7.0+dfsg/src/devices/autodev_middle.c
--- gxemul-0.6.2/src/devices/autodev_middle.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/autodev_middle.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,10 @@
+
+/*
+ *  autodev_init():
+ */
+void autodev_init(void)
+{
+	/*  printf("autodev_init()\n");  */
+
+	/*  autodev_middle.c ends here.  */
+
diff -Nru gxemul-0.6.2/src/devices/autodev_middle.cc gxemul-0.7.0+dfsg/src/devices/autodev_middle.cc
--- gxemul-0.6.2/src/devices/autodev_middle.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/autodev_middle.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,10 +0,0 @@
-
-/*
- *  autodev_init():
- */
-void autodev_init(void)
-{
-	/*  printf("autodev_init()\n");  */
-
-	/*  autodev_middle.c ends here.  */
-
diff -Nru gxemul-0.6.2/src/devices/autodev_tail.c gxemul-0.7.0+dfsg/src/devices/autodev_tail.c
--- gxemul-0.6.2/src/devices/autodev_tail.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/autodev_tail.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,4 @@
+
+	/*  autodev_tail.c  */
+}
+
diff -Nru gxemul-0.6.2/src/devices/autodev_tail.cc gxemul-0.7.0+dfsg/src/devices/autodev_tail.cc
--- gxemul-0.6.2/src/devices/autodev_tail.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/autodev_tail.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,4 +0,0 @@
-
-	/*  autodev_tail.c  */
-}
-
diff -Nru gxemul-0.6.2/src/devices/bus_isa.c gxemul-0.7.0+dfsg/src/devices/bus_isa.c
--- gxemul-0.6.2/src/devices/bus_isa.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/bus_isa.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,323 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Generic ISA bus framework
+ *
+ *  This is not a normal device, but it can be used as a quick way of adding
+ *  most of the common legacy ISA devices to a machine.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#define BUS_ISA_C
+
+#include "bus_isa.h"
+#include "device.h"
+#include "devices.h"
+#include "diskimage.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "misc.h"
+
+
+/*
+ *  isa_interrupt_common():
+ */
+void isa_interrupt_common(struct bus_isa_data *d, int old_isa_assert)
+{
+	int new_isa_assert, x;
+
+	/*  Any interrupt assertions on PIC2 go to irq 2 on PIC1  */
+	/*  (TODO: don't hardcode this here)  */
+	if (d->pic2->irr & ~d->pic2->ier)
+		d->pic1->irr |= 0x04;
+	else
+		d->pic1->irr &= ~0x04;
+
+	/*  printf("ISA: irr=%02x%02x ier=%02x%02x\n",
+	    d->pic2->irr, d->pic1->irr, d->pic2->ier, d->pic1->ier);  */
+
+	new_isa_assert = d->pic1->irr & ~d->pic1->ier;
+
+	if (old_isa_assert == new_isa_assert)
+		return;
+
+	if (!new_isa_assert) {
+		INTERRUPT_DEASSERT(d->irq);
+		return;
+	}
+
+	for (x=0; x<16; x++) {
+		if (x == 2)
+			continue;
+
+		if (x < 8 && (d->pic1->irr & ~d->pic1->ier & (1 << x)))
+			break;
+
+		if (x >= 8 && (d->pic2->irr & ~d->pic2->ier & (1 << (x&7))))
+			break;
+	}
+
+	*d->ptr_to_last_int = x;
+
+	INTERRUPT_ASSERT(d->irq);
+}
+
+
+/*
+ *  isa_interrupt_assert():
+ *
+ *  Called whenever an ISA device asserts an interrupt (0..15).
+ */
+void isa_interrupt_assert(struct interrupt *interrupt)
+{
+	struct bus_isa_data *d = (struct bus_isa_data *) interrupt->extra;
+	int old_isa_assert, line = interrupt->line;
+	int mask = 1 << (line & 7);
+
+	old_isa_assert = d->pic1->irr & ~d->pic1->ier;
+
+	if (line < 8)
+		d->pic1->irr |= mask;
+	else if (d->pic2 != NULL)
+		d->pic2->irr |= mask;
+
+	isa_interrupt_common(d, old_isa_assert);
+}
+
+
+/*
+ *  isa_interrupt_deassert():
+ *
+ *  Called whenever an ISA device deasserts an interrupt (0..15).
+ */
+void isa_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct bus_isa_data *d = (struct bus_isa_data *) interrupt->extra;
+	int line = interrupt->line, mask = 1 << (line & 7);
+	int old_irr1 = d->pic1->irr, old_isa_assert;
+
+	old_isa_assert = old_irr1 & ~d->pic1->ier;
+
+	if (line < 8)
+		d->pic1->irr &= ~mask;
+	else if (d->pic2 != NULL)
+		d->pic2->irr &= ~mask;
+
+	/*  If IRQ 0 has been cleared, then this is a timer interrupt.
+	    Let's ack it here:  */
+	if (old_irr1 & 1 && !(d->pic1->irr & 1) &&
+	    d->ptr_to_pending_timer_interrupts != NULL &&
+            (*d->ptr_to_pending_timer_interrupts) > 0)
+                (*d->ptr_to_pending_timer_interrupts) --;
+
+	isa_interrupt_common(d, old_isa_assert);
+}
+
+
+/*
+ *  bus_isa_init():
+ *
+ *  Flags are zero or more of the following, ORed together:
+ *
+ *  BUS_ISA_EXTERNAL_PIC	Don't register/use isa_interrupt_*().
+ *  BUS_ISA_IDE0		Include wdc0.
+ *  BUS_ISA_IDE1		Include wdc1.
+ *  BUS_ISA_FDC			Include a floppy controller. (Dummy.)
+ *  BUS_ISA_VGA			Include old-style (non-PCI) VGA. (*1)
+ *  BUS_ISA_VGA_FORCE		Include VGA even when running without X11. (*2)
+ *  BUS_ISA_PCKBC_FORCE_USE	Always assume keyboard console, not serial. (*3)
+ *  BUS_ISA_PCKBC_NONPCSTYLE	Don't set the pc-style flag for the keyboard.
+ *  BUS_ISA_NO_SECOND_PIC	Only useful for 8086 XT (pre-AT) emulation. :-)
+ *  BUS_ISA_LPTBASE_3BC		Set lptbase to 0x3bc instead of 0x378.
+ *
+ *  (*1) For machines with a PCI bus, this flag should not be used. Instead, a
+ *       PCI VGA card should be added to the PCI bus.
+ *
+ *  (*2) For machines where it is easy to select VGA vs serial console during
+ *       boot, this flag should not be used. Machines that "always" boot up
+ *       in VGA console mode should have it set.
+ *
+ *  (*3) Similar to *2 above; machines that always boot up with VGA console
+ *       should have this flag set, so that the keyboard is always used.
+ *
+ *  The interrupt_base_path is the name of the bus, CPU, or controller onto
+ *  which this ISA bus will be attached, e.g. "machine[0].lca" or
+ *  "machine[0].cpu[0].pic1".
+ */
+struct bus_isa_data *bus_isa_init(struct machine *machine,
+	char *interrupt_base_path, uint32_t bus_isa_flags,
+	uint64_t isa_portbase, uint64_t isa_membase)
+{
+	struct bus_isa_data *d;
+	char tmpstr[300], tmpstr2[300];
+	int wdc0_irq = 14, wdc1_irq = 15;
+	int i, tmp_handle, kbd_in_use;
+	int lptbase = 0x378;
+
+	CHECK_ALLOCATION(d = (struct bus_isa_data *) malloc(sizeof(struct bus_isa_data)));
+	memset(d, 0, sizeof(struct bus_isa_data));
+
+	d->isa_portbase = isa_portbase;
+	d->isa_membase  = isa_membase;
+
+	if (!(bus_isa_flags & BUS_ISA_EXTERNAL_PIC)) {
+		/*  Connect to the interrupt which we're interrupting
+		    at (usually a CPU):  */
+		INTERRUPT_CONNECT(interrupt_base_path, d->irq);
+
+		/*  Register the 16 possible ISA interrupts:  */
+		for (i=0; i<16; i++) {
+			struct interrupt templ;
+			char name[300];
+			snprintf(name, sizeof(name),
+			    "%s.isa.%i", interrupt_base_path, i);
+			memset(&templ, 0, sizeof(templ));
+			templ.line = i;
+			templ.name = name;
+			templ.extra = d;
+			templ.interrupt_assert = isa_interrupt_assert;
+			templ.interrupt_deassert = isa_interrupt_deassert;
+			interrupt_handler_register(&templ);
+		}
+	}
+
+	kbd_in_use = ((bus_isa_flags & BUS_ISA_PCKBC_FORCE_USE) ||
+	    (machine->x11_md.in_use))? 1 : 0;
+
+	if (machine->machine_type == MACHINE_PREP) {
+		/*  PReP with obio controller has both WDCs on irq 13!  */
+		wdc0_irq = wdc1_irq = 13;
+	}
+
+	if (!(bus_isa_flags & BUS_ISA_EXTERNAL_PIC)) {
+		snprintf(tmpstr, sizeof(tmpstr), "8259 irq=%s addr=0x%llx",
+		    interrupt_base_path, (long long)(isa_portbase + 0x20));
+		d->pic1 = machine->isa_pic_data.pic1 = (struct pic8259_data *)
+		    device_add(machine, tmpstr);
+		d->ptr_to_pending_timer_interrupts =
+		    machine->isa_pic_data.pending_timer_interrupts;
+		d->ptr_to_last_int = &machine->isa_pic_data.last_int;
+
+		if (bus_isa_flags & BUS_ISA_NO_SECOND_PIC)
+			bus_isa_flags &= ~BUS_ISA_NO_SECOND_PIC;
+		else {
+			snprintf(tmpstr, sizeof(tmpstr),
+			    "8259 irq=%s.isa.2 addr=0x%llx",
+			    interrupt_base_path,(long long)(isa_portbase+0xa0));
+			d->pic2 = machine->isa_pic_data.pic2 = (struct pic8259_data *)
+			    device_add(machine, tmpstr);
+		}
+	} else {
+		bus_isa_flags &= ~BUS_ISA_EXTERNAL_PIC;
+	}
+
+	snprintf(tmpstr, sizeof(tmpstr), "8253 irq=%s.isa.%i addr=0x%llx "
+	    "in_use=0", interrupt_base_path, 0,
+	    (long long)(isa_portbase + 0x40));
+	device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "pccmos irq=%s.isa.%i addr=0x%llx",
+	    interrupt_base_path, 8, (long long)(isa_portbase + 0x70));
+	device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.isa.%i addr=0x%llx "
+	    "name2=tty0 in_use=%i", interrupt_base_path, 4,
+	    (long long)(isa_portbase + 0x3f8), 1 - kbd_in_use);
+	machine->main_console_handle = (size_t)device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.isa.%i addr=0x%llx "
+	    "name2=tty1 in_use=0", interrupt_base_path, 3,
+	    (long long)(isa_portbase + 0x2f8));
+	device_add(machine, tmpstr);
+
+	if (bus_isa_flags & BUS_ISA_LPTBASE_3BC) {
+		bus_isa_flags &= ~BUS_ISA_LPTBASE_3BC;
+		lptbase = 0x3bc;
+	}
+
+	snprintf(tmpstr, sizeof(tmpstr), "lpt irq=%s.isa.%i addr=0x%llx "
+	    "name2=lpt in_use=0", interrupt_base_path, 7,
+	    (long long)(isa_portbase + lptbase));
+	device_add(machine, tmpstr);
+
+	if (bus_isa_flags & BUS_ISA_IDE0) {
+		bus_isa_flags &= ~BUS_ISA_IDE0;
+		snprintf(tmpstr, sizeof(tmpstr), "wdc irq=%s.isa.%i "
+		    "addr=0x%llx", interrupt_base_path, wdc0_irq,
+		    (long long)(isa_portbase + 0x1f0));
+		if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
+		    diskimage_exist(machine, 1, DISKIMAGE_IDE))
+			device_add(machine, tmpstr);
+	}
+
+	if (bus_isa_flags & BUS_ISA_IDE1) {
+		bus_isa_flags &= ~BUS_ISA_IDE1;
+		snprintf(tmpstr, sizeof(tmpstr), "wdc irq=%s.isa.%i "
+		    "addr=0x%llx", interrupt_base_path, wdc1_irq,
+		    (long long)(isa_portbase + 0x170));
+		if (diskimage_exist(machine, 2, DISKIMAGE_IDE) ||
+		    diskimage_exist(machine, 3, DISKIMAGE_IDE))
+			device_add(machine, tmpstr);
+	}
+
+	if (bus_isa_flags & BUS_ISA_FDC) {
+		bus_isa_flags &= ~BUS_ISA_FDC;
+		snprintf(tmpstr, sizeof(tmpstr), "fdc irq=%s.isa.%i "
+		    "addr=0x%llx", interrupt_base_path, 6,
+		    (long long)(isa_portbase + 0x3f0));
+		device_add(machine, tmpstr);
+	}
+
+	if (bus_isa_flags & BUS_ISA_VGA) {
+		if (machine->x11_md.in_use || bus_isa_flags & BUS_ISA_VGA_FORCE)
+			dev_vga_init(machine, machine->memory,
+			    isa_membase + 0xa0000, isa_portbase + 0x3c0,
+			    machine->machine_name);
+		bus_isa_flags &= ~(BUS_ISA_VGA | BUS_ISA_VGA_FORCE);
+	}
+
+	snprintf(tmpstr, sizeof(tmpstr), "%s.isa.1", interrupt_base_path);
+	snprintf(tmpstr2, sizeof(tmpstr2), "%s.isa.12", interrupt_base_path);
+	tmp_handle = dev_pckbc_init(machine, machine->memory,
+	    isa_portbase + 0x60, PCKBC_8042, tmpstr, tmpstr2,
+	    kbd_in_use, bus_isa_flags & BUS_ISA_PCKBC_NONPCSTYLE? 0 : 1);
+
+	if (kbd_in_use)
+		machine->main_console_handle = tmp_handle;
+
+	bus_isa_flags &= ~(BUS_ISA_PCKBC_NONPCSTYLE | BUS_ISA_PCKBC_FORCE_USE);
+
+	if (bus_isa_flags != 0)
+		fatal("WARNING! bus_isa(): unimplemented bus_isa_flags 0x%x\n",
+		    bus_isa_flags);
+
+	return d;
+}
+
diff -Nru gxemul-0.6.2/src/devices/bus_isa.cc gxemul-0.7.0+dfsg/src/devices/bus_isa.cc
--- gxemul-0.6.2/src/devices/bus_isa.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/bus_isa.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,323 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Generic ISA bus framework
- *
- *  This is not a normal device, but it can be used as a quick way of adding
- *  most of the common legacy ISA devices to a machine.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#define BUS_ISA_C
-
-#include "bus_isa.h"
-#include "device.h"
-#include "devices.h"
-#include "diskimage.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "misc.h"
-
-
-/*
- *  isa_interrupt_common():
- */
-void isa_interrupt_common(struct bus_isa_data *d, int old_isa_assert)
-{
-	int new_isa_assert, x;
-
-	/*  Any interrupt assertions on PIC2 go to irq 2 on PIC1  */
-	/*  (TODO: don't hardcode this here)  */
-	if (d->pic2->irr & ~d->pic2->ier)
-		d->pic1->irr |= 0x04;
-	else
-		d->pic1->irr &= ~0x04;
-
-	/*  printf("ISA: irr=%02x%02x ier=%02x%02x\n",
-	    d->pic2->irr, d->pic1->irr, d->pic2->ier, d->pic1->ier);  */
-
-	new_isa_assert = d->pic1->irr & ~d->pic1->ier;
-
-	if (old_isa_assert == new_isa_assert)
-		return;
-
-	if (!new_isa_assert) {
-		INTERRUPT_DEASSERT(d->irq);
-		return;
-	}
-
-	for (x=0; x<16; x++) {
-		if (x == 2)
-			continue;
-
-		if (x < 8 && (d->pic1->irr & ~d->pic1->ier & (1 << x)))
-			break;
-
-		if (x >= 8 && (d->pic2->irr & ~d->pic2->ier & (1 << (x&7))))
-			break;
-	}
-
-	*d->ptr_to_last_int = x;
-
-	INTERRUPT_ASSERT(d->irq);
-}
-
-
-/*
- *  isa_interrupt_assert():
- *
- *  Called whenever an ISA device asserts an interrupt (0..15).
- */
-void isa_interrupt_assert(struct interrupt *interrupt)
-{
-	struct bus_isa_data *d = (struct bus_isa_data *) interrupt->extra;
-	int old_isa_assert, line = interrupt->line;
-	int mask = 1 << (line & 7);
-
-	old_isa_assert = d->pic1->irr & ~d->pic1->ier;
-
-	if (line < 8)
-		d->pic1->irr |= mask;
-	else if (d->pic2 != NULL)
-		d->pic2->irr |= mask;
-
-	isa_interrupt_common(d, old_isa_assert);
-}
-
-
-/*
- *  isa_interrupt_deassert():
- *
- *  Called whenever an ISA device deasserts an interrupt (0..15).
- */
-void isa_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct bus_isa_data *d = (struct bus_isa_data *) interrupt->extra;
-	int line = interrupt->line, mask = 1 << (line & 7);
-	int old_irr1 = d->pic1->irr, old_isa_assert;
-
-	old_isa_assert = old_irr1 & ~d->pic1->ier;
-
-	if (line < 8)
-		d->pic1->irr &= ~mask;
-	else if (d->pic2 != NULL)
-		d->pic2->irr &= ~mask;
-
-	/*  If IRQ 0 has been cleared, then this is a timer interrupt.
-	    Let's ack it here:  */
-	if (old_irr1 & 1 && !(d->pic1->irr & 1) &&
-	    d->ptr_to_pending_timer_interrupts != NULL &&
-            (*d->ptr_to_pending_timer_interrupts) > 0)
-                (*d->ptr_to_pending_timer_interrupts) --;
-
-	isa_interrupt_common(d, old_isa_assert);
-}
-
-
-/*
- *  bus_isa_init():
- *
- *  Flags are zero or more of the following, ORed together:
- *
- *  BUS_ISA_EXTERNAL_PIC	Don't register/use isa_interrupt_*().
- *  BUS_ISA_IDE0		Include wdc0.
- *  BUS_ISA_IDE1		Include wdc1.
- *  BUS_ISA_FDC			Include a floppy controller. (Dummy.)
- *  BUS_ISA_VGA			Include old-style (non-PCI) VGA. (*1)
- *  BUS_ISA_VGA_FORCE		Include VGA even when running without X11. (*2)
- *  BUS_ISA_PCKBC_FORCE_USE	Always assume keyboard console, not serial. (*3)
- *  BUS_ISA_PCKBC_NONPCSTYLE	Don't set the pc-style flag for the keyboard.
- *  BUS_ISA_NO_SECOND_PIC	Only useful for 8086 XT (pre-AT) emulation. :-)
- *  BUS_ISA_LPTBASE_3BC		Set lptbase to 0x3bc instead of 0x378.
- *
- *  (*1) For machines with a PCI bus, this flag should not be used. Instead, a
- *       PCI VGA card should be added to the PCI bus.
- *
- *  (*2) For machines where it is easy to select VGA vs serial console during
- *       boot, this flag should not be used. Machines that "always" boot up
- *       in VGA console mode should have it set.
- *
- *  (*3) Similar to *2 above; machines that always boot up with VGA console
- *       should have this flag set, so that the keyboard is always used.
- *
- *  The interrupt_base_path is the name of the bus, CPU, or controller onto
- *  which this ISA bus will be attached, e.g. "machine[0].lca" or
- *  "machine[0].cpu[0].pic1".
- */
-struct bus_isa_data *bus_isa_init(struct machine *machine,
-	char *interrupt_base_path, uint32_t bus_isa_flags,
-	uint64_t isa_portbase, uint64_t isa_membase)
-{
-	struct bus_isa_data *d;
-	char tmpstr[300], tmpstr2[300];
-	int wdc0_irq = 14, wdc1_irq = 15;
-	int i, tmp_handle, kbd_in_use;
-	int lptbase = 0x378;
-
-	CHECK_ALLOCATION(d = (struct bus_isa_data *) malloc(sizeof(struct bus_isa_data)));
-	memset(d, 0, sizeof(struct bus_isa_data));
-
-	d->isa_portbase = isa_portbase;
-	d->isa_membase  = isa_membase;
-
-	if (!(bus_isa_flags & BUS_ISA_EXTERNAL_PIC)) {
-		/*  Connect to the interrupt which we're interrupting
-		    at (usually a CPU):  */
-		INTERRUPT_CONNECT(interrupt_base_path, d->irq);
-
-		/*  Register the 16 possible ISA interrupts:  */
-		for (i=0; i<16; i++) {
-			struct interrupt templ;
-			char name[300];
-			snprintf(name, sizeof(name),
-			    "%s.isa.%i", interrupt_base_path, i);
-			memset(&templ, 0, sizeof(templ));
-			templ.line = i;
-			templ.name = name;
-			templ.extra = d;
-			templ.interrupt_assert = isa_interrupt_assert;
-			templ.interrupt_deassert = isa_interrupt_deassert;
-			interrupt_handler_register(&templ);
-		}
-	}
-
-	kbd_in_use = ((bus_isa_flags & BUS_ISA_PCKBC_FORCE_USE) ||
-	    (machine->x11_md.in_use))? 1 : 0;
-
-	if (machine->machine_type == MACHINE_PREP) {
-		/*  PReP with obio controller has both WDCs on irq 13!  */
-		wdc0_irq = wdc1_irq = 13;
-	}
-
-	if (!(bus_isa_flags & BUS_ISA_EXTERNAL_PIC)) {
-		snprintf(tmpstr, sizeof(tmpstr), "8259 irq=%s addr=0x%llx",
-		    interrupt_base_path, (long long)(isa_portbase + 0x20));
-		d->pic1 = machine->isa_pic_data.pic1 = (struct pic8259_data *)
-		    device_add(machine, tmpstr);
-		d->ptr_to_pending_timer_interrupts =
-		    machine->isa_pic_data.pending_timer_interrupts;
-		d->ptr_to_last_int = &machine->isa_pic_data.last_int;
-
-		if (bus_isa_flags & BUS_ISA_NO_SECOND_PIC)
-			bus_isa_flags &= ~BUS_ISA_NO_SECOND_PIC;
-		else {
-			snprintf(tmpstr, sizeof(tmpstr),
-			    "8259 irq=%s.isa.2 addr=0x%llx",
-			    interrupt_base_path,(long long)(isa_portbase+0xa0));
-			d->pic2 = machine->isa_pic_data.pic2 = (struct pic8259_data *)
-			    device_add(machine, tmpstr);
-		}
-	} else {
-		bus_isa_flags &= ~BUS_ISA_EXTERNAL_PIC;
-	}
-
-	snprintf(tmpstr, sizeof(tmpstr), "8253 irq=%s.isa.%i addr=0x%llx "
-	    "in_use=0", interrupt_base_path, 0,
-	    (long long)(isa_portbase + 0x40));
-	device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "pccmos irq=%s.isa.%i addr=0x%llx",
-	    interrupt_base_path, 8, (long long)(isa_portbase + 0x70));
-	device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.isa.%i addr=0x%llx "
-	    "name2=tty0 in_use=%i", interrupt_base_path, 4,
-	    (long long)(isa_portbase + 0x3f8), 1 - kbd_in_use);
-	machine->main_console_handle = (size_t)device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.isa.%i addr=0x%llx "
-	    "name2=tty1 in_use=0", interrupt_base_path, 3,
-	    (long long)(isa_portbase + 0x2f8));
-	device_add(machine, tmpstr);
-
-	if (bus_isa_flags & BUS_ISA_LPTBASE_3BC) {
-		bus_isa_flags &= ~BUS_ISA_LPTBASE_3BC;
-		lptbase = 0x3bc;
-	}
-
-	snprintf(tmpstr, sizeof(tmpstr), "lpt irq=%s.isa.%i addr=0x%llx "
-	    "name2=lpt in_use=0", interrupt_base_path, 7,
-	    (long long)(isa_portbase + lptbase));
-	device_add(machine, tmpstr);
-
-	if (bus_isa_flags & BUS_ISA_IDE0) {
-		bus_isa_flags &= ~BUS_ISA_IDE0;
-		snprintf(tmpstr, sizeof(tmpstr), "wdc irq=%s.isa.%i "
-		    "addr=0x%llx", interrupt_base_path, wdc0_irq,
-		    (long long)(isa_portbase + 0x1f0));
-		if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
-		    diskimage_exist(machine, 1, DISKIMAGE_IDE))
-			device_add(machine, tmpstr);
-	}
-
-	if (bus_isa_flags & BUS_ISA_IDE1) {
-		bus_isa_flags &= ~BUS_ISA_IDE1;
-		snprintf(tmpstr, sizeof(tmpstr), "wdc irq=%s.isa.%i "
-		    "addr=0x%llx", interrupt_base_path, wdc1_irq,
-		    (long long)(isa_portbase + 0x170));
-		if (diskimage_exist(machine, 2, DISKIMAGE_IDE) ||
-		    diskimage_exist(machine, 3, DISKIMAGE_IDE))
-			device_add(machine, tmpstr);
-	}
-
-	if (bus_isa_flags & BUS_ISA_FDC) {
-		bus_isa_flags &= ~BUS_ISA_FDC;
-		snprintf(tmpstr, sizeof(tmpstr), "fdc irq=%s.isa.%i "
-		    "addr=0x%llx", interrupt_base_path, 6,
-		    (long long)(isa_portbase + 0x3f0));
-		device_add(machine, tmpstr);
-	}
-
-	if (bus_isa_flags & BUS_ISA_VGA) {
-		if (machine->x11_md.in_use || bus_isa_flags & BUS_ISA_VGA_FORCE)
-			dev_vga_init(machine, machine->memory,
-			    isa_membase + 0xa0000, isa_portbase + 0x3c0,
-			    machine->machine_name);
-		bus_isa_flags &= ~(BUS_ISA_VGA | BUS_ISA_VGA_FORCE);
-	}
-
-	snprintf(tmpstr, sizeof(tmpstr), "%s.isa.1", interrupt_base_path);
-	snprintf(tmpstr2, sizeof(tmpstr2), "%s.isa.12", interrupt_base_path);
-	tmp_handle = dev_pckbc_init(machine, machine->memory,
-	    isa_portbase + 0x60, PCKBC_8042, tmpstr, tmpstr2,
-	    kbd_in_use, bus_isa_flags & BUS_ISA_PCKBC_NONPCSTYLE? 0 : 1);
-
-	if (kbd_in_use)
-		machine->main_console_handle = tmp_handle;
-
-	bus_isa_flags &= ~(BUS_ISA_PCKBC_NONPCSTYLE | BUS_ISA_PCKBC_FORCE_USE);
-
-	if (bus_isa_flags != 0)
-		fatal("WARNING! bus_isa(): unimplemented bus_isa_flags 0x%x\n",
-		    bus_isa_flags);
-
-	return d;
-}
-
diff -Nru gxemul-0.6.2/src/devices/bus_pci.c gxemul-0.7.0+dfsg/src/devices/bus_pci.c
--- gxemul-0.6.2/src/devices/bus_pci.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/bus_pci.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1419 @@
+/*
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Generic PCI bus framework
+ *
+ *  This is not a normal "device", but is used by individual PCI controllers
+ *  and devices.
+ *
+ *  See NetBSD's pcidevs.h for more PCI vendor and device identifiers.
+ *
+ *  TODO:
+ *
+ *	x) Allow guest OSes to do runtime address fixups (i.e. actually
+ *	   move a device from one address to another).
+ *
+ *	x) Generalize the PCI and legacy ISA interrupt routing stuff.
+ *
+ *	x) Make sure that pci_little_endian is used correctly everywhere.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#define BUS_PCI_C
+
+#include "bus_isa.h"
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "wdc.h"
+
+#include "thirdparty/cpc700reg.h"
+
+extern int verbose;
+
+
+/*
+ *  bus_pci_decompose_1():
+ *
+ *  Helper function for decomposing Mechanism 1 tags.
+ */
+void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
+{
+	*bus  = (t >> 16) & 0xff;
+	*dev  = (t >> 11) & 0x1f;
+	*func = (t >>  8) &  0x7;
+	*reg  =  t        & 0xff;
+
+	/*  Warn about unaligned register access:  */
+	if (t & 3)
+		fatal("[ bus_pci_decompose_1: WARNING: reg = 0x%02x ]\n",
+		    t & 0xff);
+}
+
+
+/*
+ *  bus_pci_data_access():
+ *
+ *  Reads from or writes to the PCI configuration registers of a device.
+ */
+void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data,
+	uint64_t *data, int len, int writeflag)
+{
+	struct pci_device *dev;
+	unsigned char *cfg_base;
+	uint64_t x, idata = *data;
+	int i;
+
+	/*  Scan through the list of pci_device entries.  */
+	dev = pci_data->first_device;
+	while (dev != NULL) {
+		if (dev->bus      == pci_data->cur_bus &&
+		    dev->function == pci_data->cur_func &&
+		    dev->device   == pci_data->cur_device)
+			break;
+		dev = dev->next;
+	}
+
+	/*  No device? Then return emptiness.  */
+	if (dev == NULL) {
+		if (writeflag == MEM_READ) {
+			if (pci_data->cur_reg == 0)
+				*data = (uint64_t) -1;
+			else
+				*data = 0;
+		} else {
+			fatal("[ bus_pci_data_access(): write to non-existant"
+			    " device, bus %i func %i device %i ]\n",
+			    pci_data->cur_bus, pci_data->cur_func,
+			    pci_data->cur_device);
+		}
+		return;
+	}
+
+	/*  Return normal config data, or length data?  */
+	if (pci_data->last_was_write_ffffffff &&
+	    pci_data->cur_reg >= PCI_MAPREG_START &&
+	    pci_data->cur_reg <= PCI_MAPREG_END - 4)
+		cfg_base = dev->cfg_mem_size;
+	else
+		cfg_base = dev->cfg_mem;
+
+	/*  Read data as little-endian:  */
+	x = 0;
+	for (i=len-1; i>=0; i--) {
+		int ofs = pci_data->cur_reg + i;
+		x <<= 8;
+		x |= cfg_base[ofs & (PCI_CFG_MEM_SIZE - 1)];
+	}
+
+	/*  Register write:  */
+	if (writeflag == MEM_WRITE) {
+		debug("[ bus_pci: write to PCI DATA: data = 0x%08llx ]\n",
+		    (long long)idata);
+		if (idata == 0xffffffffULL &&
+		    pci_data->cur_reg >= PCI_MAPREG_START &&
+		    pci_data->cur_reg <= PCI_MAPREG_END - 4) {
+			pci_data->last_was_write_ffffffff = 1;
+			return;
+		}
+
+		if (dev->cfg_reg_write == NULL ||
+		    dev->cfg_reg_write(dev, pci_data->cur_reg, *data) == 0) {
+			/*  Print a warning for unhandled writes:  */
+			debug("[ bus_pci: write to PCI DATA: data = 0x%08llx"
+			    " (current value = 0x%08llx); NOT YET"
+			    " SUPPORTED. bus %i, device %i, function %i (%s)"
+			    " register 0x%02x ]\n", (long long)idata,
+			    (long long)x, pci_data->cur_bus,
+			    pci_data->cur_device, pci_data->cur_func,
+			    dev->name, pci_data->cur_reg);
+
+			/*  Special warning, to detect if NetBSD's special
+			    detection of PCI devices fails:  */
+			if (pci_data->cur_reg == PCI_COMMAND_STATUS_REG
+			    && !((*data) & PCI_COMMAND_IO_ENABLE)) {
+				fatal("\n[ NetBSD PCI detection stuff not"
+				    " yet implemented for device '%s' ]\n",
+				    dev->name);
+			}
+		}
+		return;
+	}
+
+	/*  Register read:  */
+	*data = x;
+
+	pci_data->last_was_write_ffffffff = 0;
+
+	debug("[ bus_pci: read from PCI DATA, bus %i, device "
+	    "%i, function %i (%s) register 0x%02x: (len=%i) 0x%08lx ]\n",
+	    pci_data->cur_bus, pci_data->cur_device, pci_data->cur_func,
+	    dev->name, pci_data->cur_reg, len, (long)*data);
+}
+
+
+/*
+ *  bus_pci_setaddr():
+ *
+ *  Sets the address in preparation for a PCI register transfer.
+ */
+void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data,
+	int bus, int device, int function, int reg)
+{
+	if (cpu == NULL || pci_data == NULL) {
+		fatal("bus_pci_setaddr(): NULL ptr\n");
+		exit(1);
+	}
+
+	pci_data->cur_bus = bus;
+	pci_data->cur_device = device;
+	pci_data->cur_func = function;
+	pci_data->cur_reg = reg;
+}
+
+
+/*
+ *  bus_pci_add():
+ *
+ *  Add a PCI device to a bus_pci device.
+ */
+void bus_pci_add(struct machine *machine, struct pci_data *pci_data,
+	struct memory *mem, int bus, int device, int function,
+	const char *name)
+{
+	struct pci_device *pd;
+	int ofs;
+	void (*init)(struct machine *, struct memory *, struct pci_device *);
+
+	if (pci_data == NULL) {
+		fatal("bus_pci_add(): pci_data == NULL!\n");
+		abort();
+	}
+
+	/*  Find the PCI device:  */
+	init = pci_lookup_initf(name);
+
+	/*  Make sure this bus/device/function number isn't already in use:  */
+	pd = pci_data->first_device;
+	while (pd != NULL) {
+		if (pd->bus == bus && pd->device == device &&
+		    pd->function == function) {
+			fatal("bus_pci_add(): (bus %i, device %i, function"
+			    " %i) already in use\n", bus, device, function);
+			exit(1);
+		}
+		pd = pd->next;
+	}
+
+	CHECK_ALLOCATION(pd = (struct pci_device *) malloc(sizeof(struct pci_device)));
+	memset(pd, 0, sizeof(struct pci_device));
+
+	/*  Add the new device first in the PCI bus' chain:  */
+	pd->next = pci_data->first_device;
+	pci_data->first_device = pd;
+
+	CHECK_ALLOCATION(pd->name = strdup(name));
+	pd->pcibus   = pci_data;
+	pd->bus      = bus;
+	pd->device   = device;
+	pd->function = function;
+
+	/*
+	 *  Initialize with some default values:
+	 *
+	 *  TODO:  The command status register is best to set up per device.
+	 *  The size registers should also be set up on a per-device basis.
+	 */
+	PCI_SET_DATA(PCI_COMMAND_STATUS_REG,
+	    PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
+	for (ofs = PCI_MAPREG_START; ofs < PCI_MAPREG_END; ofs += 4)
+		PCI_SET_DATA_SIZE(ofs, 0x00100000 - 1);
+
+	if (init == NULL) {
+		fatal("No init function for PCI device \"%s\"?\n", name);
+		exit(1);
+	}
+
+	/*  Call the PCI device' init function:  */
+	init(machine, mem, pd);
+}
+
+
+/*
+ *  allocate_device_space():
+ *
+ *  Used by glue code (see below) to allocate space for a PCI device.
+ *
+ *  The returned values in portp and memp are the actual (emulated) addresses
+ *  that the device should use. (Normally only one of these is actually used.)
+ *
+ *  TODO: PCI irqs?
+ */
+static void allocate_device_space(struct pci_device *pd,
+	uint64_t portsize, uint64_t memsize,
+	uint64_t *portp, uint64_t *memp)
+{
+	uint64_t port, mem;
+
+	/*  Calculate an aligned starting port:  */
+	port = pd->pcibus->cur_pci_portbase;
+	if (portsize != 0) {
+		port = ((port - 1) | (portsize - 1)) + 1;
+		pd->pcibus->cur_pci_portbase = port;
+		PCI_SET_DATA(PCI_MAPREG_START + pd->cur_mapreg_offset,
+		    port | PCI_MAPREG_TYPE_IO);
+		PCI_SET_DATA_SIZE(PCI_MAPREG_START + pd->cur_mapreg_offset,
+		    ((portsize - 1) & ~0xf) | 0xd);
+		pd->cur_mapreg_offset += sizeof(uint32_t);
+	}
+
+	/*  Calculate an aligned starting memory location:  */
+	mem = pd->pcibus->cur_pci_membase;
+	if (memsize != 0) {
+		mem = ((mem - 1) | (memsize - 1)) + 1;
+		pd->pcibus->cur_pci_membase = mem;
+		PCI_SET_DATA(PCI_MAPREG_START + pd->cur_mapreg_offset, mem);
+		PCI_SET_DATA_SIZE(PCI_MAPREG_START + pd->cur_mapreg_offset,
+		    ((memsize - 1) & ~0xf) | 0x0);
+		pd->cur_mapreg_offset += sizeof(uint32_t);
+	}
+
+	*portp = port + pd->pcibus->pci_actual_io_offset;
+	*memp  = mem  + pd->pcibus->pci_actual_mem_offset;
+
+	if (verbose >= 2) {
+		debug("pci device '%s' at", pd->name);
+		if (portsize != 0)
+			debug(" port 0x%llx-0x%llx", (long long)pd->pcibus->
+			    cur_pci_portbase, (long long)(pd->pcibus->
+			    cur_pci_portbase + portsize - 1));
+		if (memsize != 0)
+			debug(" mem 0x%llx-0x%llx", (long long)pd->pcibus->
+			    cur_pci_membase, (long long)(pd->pcibus->
+			    cur_pci_membase + memsize - 1));
+		debug("\n");
+	}
+
+	pd->pcibus->cur_pci_portbase += portsize;
+	pd->pcibus->cur_pci_membase += memsize;
+}
+
+
+/*
+ *  bus_pci_init():
+ *
+ *  This doesn't register a device, but instead returns a pointer to a struct
+ *  which should be passed to other bus_pci functions when accessing the bus.
+ *
+ *  irq_path is the interrupt path to the PCI controller.
+ *
+ *  pci_portbase, pci_membase, and pci_irqbase are the port, memory, and
+ *  interrupt bases for PCI devices (as found in the configuration registers).
+ *
+ *  pci_actual_io_offset and pci_actual_mem_offset are the offset from
+ *  the values in the configuration registers to the actual (emulated) device.
+ *
+ *  isa_portbase, isa_membase, and isa_irqbase are the port, memory, and
+ *  interrupt bases for legacy ISA devices.
+ */
+struct pci_data *bus_pci_init(struct machine *machine, const char *irq_path,
+	uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
+	uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase,
+	uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
+{
+	struct pci_data *d;
+
+	CHECK_ALLOCATION(d = (struct pci_data *) malloc(sizeof(struct pci_data)));
+	memset(d, 0, sizeof(struct pci_data));
+
+	CHECK_ALLOCATION(d->irq_path     = strdup(irq_path));
+	CHECK_ALLOCATION(d->irq_path_isa = strdup(isa_irqbase));
+	CHECK_ALLOCATION(d->irq_path_pci = strdup(pci_irqbase));
+
+	d->pci_actual_io_offset  = pci_actual_io_offset;
+	d->pci_actual_mem_offset = pci_actual_mem_offset;
+	d->pci_portbase          = pci_portbase;
+	d->pci_membase           = pci_membase;
+	d->isa_portbase          = isa_portbase;
+	d->isa_membase           = isa_membase;
+
+	d->cur_pci_portbase = d->pci_portbase;
+	d->cur_pci_membase  = d->pci_membase;
+
+	/*  Assume that the first 64KB could be used by legacy ISA devices:  */
+	if (d->isa_portbase != 0 || d->isa_membase != 0) {
+		d->cur_pci_portbase += 0x10000;
+		d->cur_pci_membase  += 0x10000;
+	}
+
+	return d;
+}
+
+
+
+/******************************************************************************
+ *                                                                            *
+ *  The following is glue code for PCI controllers and devices. The glue      *
+ *  code does the minimal stuff necessary to get an emulated OS to detect     *
+ *  the device (i.e. set up PCI configuration registers), and then if         *
+ *  necessary adds a "normal" device.                                         *
+ *                                                                            *
+ ******************************************************************************/
+
+
+
+/*
+ *  Integraphics Systems "igsfb" Framebuffer (graphics) card, used in at
+ *  least the NetWinder.
+ */
+
+#define	PCI_VENDOR_INTEGRAPHICS		0x10ea
+
+PCIINIT(igsfb)
+{
+	char tmpstr[2000];
+
+	PCI_SET_DATA(PCI_ID_REG,
+	    PCI_ID_CODE(PCI_VENDOR_INTEGRAPHICS, 0x2010));
+
+	PCI_SET_DATA(PCI_CLASS_REG,
+	    PCI_CLASS_CODE(PCI_CLASS_DISPLAY,
+	    PCI_SUBCLASS_DISPLAY_VGA, 0) + 0x01);
+
+	/*  TODO  */
+	PCI_SET_DATA(0x10, 0x08000000);
+
+	snprintf(tmpstr, sizeof(tmpstr), "igsfb addr=0x%llx",
+	    (long long)(pd->pcibus->isa_membase + 0x08000000));
+	device_add(machine, tmpstr);
+}
+
+
+
+/*
+ *  S3 ViRGE graphics.
+ *
+ *  TODO: Only emulates a standard VGA card, so far.
+ */
+
+#define PCI_VENDOR_S3			0x5333
+#define PCI_PRODUCT_S3_VIRGE		0x5631
+#define	PCI_PRODUCT_S3_VIRGE_DX		0x8a01
+
+PCIINIT(s3_virge)
+{
+	PCI_SET_DATA(PCI_ID_REG,
+	    PCI_ID_CODE(PCI_VENDOR_S3, PCI_PRODUCT_S3_VIRGE_DX));
+
+	PCI_SET_DATA(PCI_CLASS_REG,
+	    PCI_CLASS_CODE(PCI_CLASS_DISPLAY,
+	    PCI_SUBCLASS_DISPLAY_VGA, 0) + 0x01);
+
+	dev_vga_init(machine, mem, pd->pcibus->isa_membase + 0xa0000,
+	    pd->pcibus->isa_portbase + 0x3c0, machine->machine_name);
+}
+
+
+
+/*
+ *  Acer Labs M5229 PCI-IDE (UDMA) controller.
+ *  Acer Labs M1543 PCI->ISA bridge.
+ */
+
+#define PCI_VENDOR_ALI			0x10b9
+#define PCI_PRODUCT_ALI_M1543		0x1533	/*  NOTE: not 1543  */
+#define	PCI_PRODUCT_ALI_M5229		0x5229
+
+PCIINIT(ali_m1543)
+{
+	PCI_SET_DATA(PCI_ID_REG,
+	    PCI_ID_CODE(PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1543));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0xc3);
+
+	PCI_SET_DATA(PCI_BHLC_REG,
+	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
+
+	/*  Linux uses these to detect which IRQ the IDE controller uses:  */
+	PCI_SET_DATA(0x44, 0x0000000e);
+	PCI_SET_DATA(0x58, 0x00000003);
+
+	switch (machine->machine_type) {
+	case MACHINE_CATS:
+		bus_isa_init(machine, pd->pcibus->irq_path_isa,
+		    BUS_ISA_PCKBC_FORCE_USE | BUS_ISA_PCKBC_NONPCSTYLE,
+		    0x7c000000, 0x80000000);
+		break;
+	default:fatal("ali_m1543 init: unimplemented machine type\n");
+		exit(1);
+	}
+}
+
+PCIINIT(ali_m5229)
+{
+	char tmpstr[2000], irqstr[1000];
+
+	PCI_SET_DATA(PCI_ID_REG,
+	    PCI_ID_CODE(PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5229));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
+	    PCI_SUBCLASS_MASS_STORAGE_IDE, 0x60) + 0xc1);
+
+	switch (machine->machine_type) {
+	case MACHINE_CATS:
+		/*  CATS ISA interrupts are at footbridge irq 10:  */
+		snprintf(irqstr, sizeof(irqstr), "%s.10.isa",
+		    pd->pcibus->irq_path);
+		break;
+	default:fatal("ali_m5229 init: unimplemented machine type\n");
+		exit(1);
+	}
+
+	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
+	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
+		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s.%i",
+		    (long long)(pd->pcibus->isa_portbase + 0x1f0),
+		    irqstr, 14);
+		device_add(machine, tmpstr);
+	}
+
+	/*  The secondary channel is disabled. TODO: fix this.  */
+}
+
+
+
+/*
+ *  Adaptec AHC SCSI controller, with values as they are in my SGI O2.
+ */
+
+#define PCI_VENDOR_ADP			0x9004          /* Adaptec */
+#define PCI_PRODUCT_ADP_AIC7880		0x8078          /* AIC7880 */
+
+PCIINIT(ahc)
+{
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_ADP,
+	    PCI_PRODUCT_ADP_AIC7880));
+
+	PCI_SET_DATA(PCI_COMMAND_STATUS_REG, 0x02800046);
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
+	    PCI_SUBCLASS_MASS_STORAGE_SCSI, 0) + 0x01);
+
+	PCI_SET_DATA(PCI_BHLC_REG, 0x00001020);
+
+	PCI_SET_DATA(PCI_MAPREG_START + 0x00, 0xffffff01);
+	PCI_SET_DATA(PCI_MAPREG_START + 0x04, 0x80001000);
+	PCI_SET_DATA(PCI_MAPREG_START + 0x08, 0x00000000);
+	PCI_SET_DATA(PCI_MAPREG_START + 0x0c, 0x00000000);
+	PCI_SET_DATA(PCI_MAPREG_START + 0x10, 0x00000000);
+	PCI_SET_DATA(PCI_MAPREG_START + 0x14, 0x00000000);
+	PCI_SET_DATA(PCI_MAPREG_START + 0x18, 0x00000000);
+
+	PCI_SET_DATA(PCI_MAPREG_START + 0x1c, 0x00000000);
+
+	PCI_SET_DATA(0x30, 0x80010000);
+	PCI_SET_DATA(PCI_INTERRUPT_REG, 0x08080100);	/*  interrupt pin  */
+
+	PCI_SET_DATA(0x40, 0x00000180);
+	PCI_SET_DATA(0x40, 0x00000180);
+
+
+	/*
+	 *  TODO:  this address is based on what NetBSD/sgimips uses
+	 *  on SGI IP32 (O2). Fix this! Allow devices to move? Or
+	 *  implement PCI space redirection at least!
+	 */
+
+	// device_add(machine, "ahc addr=0x1a001000");
+	device_add(machine, "ahc addr=0x18002000");
+}
+
+
+
+/*
+ *  Galileo Technology GT-64xxx PCI controller.
+ *
+ *	GT-64011	Used in Cobalt machines.
+ *	GT-64120	Used in evbmips machines (Malta).
+ *
+ *  NOTE: This works in the opposite way compared to other devices; the PCI
+ *  device is added from the normal device instead of the other way around.
+ */
+
+#define PCI_VENDOR_GALILEO           0x11ab    /* Galileo Technology */
+#define PCI_PRODUCT_GALILEO_GT64011  0x4146    /* GT-64011 System Controller */
+#define	PCI_PRODUCT_GALILEO_GT64120  0x4620    /* GT-64120 */
+#define	PCI_PRODUCT_GALILEO_GT64260  0x6430    /* GT-64260 */
+
+PCIINIT(gt64011)
+{
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_GALILEO,
+	    PCI_PRODUCT_GALILEO_GT64011));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x01);	/*  Revision 1  */
+}
+
+PCIINIT(gt64120)
+{
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_GALILEO,
+	    PCI_PRODUCT_GALILEO_GT64120));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x02);	/*  Revision 2?  */
+
+	switch (machine->machine_type) {
+	case MACHINE_EVBMIPS:
+		PCI_SET_DATA(PCI_MAPREG_START + 0x10, 0x1be00000);
+		break;
+	}
+}
+
+PCIINIT(gt64260)
+{
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_GALILEO,
+	    PCI_PRODUCT_GALILEO_GT64260));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x01);	/*  Revision 1?  */
+}
+
+
+
+/*
+ *  AMD PCnet Ethernet card.
+ *
+ *  "Am79c970A PCnet-PCI II rev 0" or similar.
+ */
+
+#define	PCI_VENDOR_AMD			0x1022	/* Advanced Micro Devices */
+#define	PCI_PRODUCT_AMD_PCNET_PCI	0x2000	/* PCnet-PCI Ethernet */
+
+PCIINIT(pcn)
+{
+	int irq;
+
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_AMD,
+	    PCI_PRODUCT_AMD_PCNET_PCI));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_NETWORK,
+	    PCI_SUBCLASS_NETWORK_ETHERNET, 0) + 0x00);	/*  Revision 0  */
+
+	switch (machine->machine_type) {
+
+	case MACHINE_EVBMIPS:
+		irq = (1 << 8) + 10;	/*  TODO  */
+		break;
+
+	default:fatal("pcn in non-implemented machine type %i\n",
+		    machine->machine_type);
+		exit(1);
+	}
+
+	PCI_SET_DATA(PCI_INTERRUPT_REG, 0x01100000 | irq);
+
+	/*
+	 *  TODO: Add the pcn device here. The pcn device will need to work as
+	 *  a wrapper for dev_le + all the DMA magic and whatever is required.
+	 *  It's too much to implement right now.
+	 */
+}
+
+
+
+/*
+ *  Intel 31244   Serial ATA Controller
+ *  Intel 82371SB PIIX3 PCI-ISA bridge
+ *  Intel 82371AB PIIX4 PCI-ISA bridge
+ *  Intel 82371SB IDE controller
+ *  Intel 82371AB IDE controller
+ *  Intel 82378ZB System I/O controller.
+ */
+
+#define	PCI_VENDOR_INTEL		0x8086
+#define	PCI_PRODUCT_INTEL_31244		0x3200
+#define	PCI_PRODUCT_INTEL_82371SB_ISA	0x7000
+#define	PCI_PRODUCT_INTEL_82371SB_IDE	0x7010
+#define	PCI_PRODUCT_INTEL_82371AB_ISA	0x7110
+#define	PCI_PRODUCT_INTEL_82371AB_IDE	0x7111
+#define	PCI_PRODUCT_INTEL_SIO		0x0484
+
+PCIINIT(i31244)
+{
+	uint64_t port, memaddr;
+	int irq = 0;
+
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_INTEL,
+	    PCI_PRODUCT_INTEL_31244));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
+	    PCI_SUBCLASS_MASS_STORAGE_IDE, 0x33) + 0x00);
+
+	switch (machine->machine_type) {
+	case MACHINE_IQ80321:
+		/*  S-PCI-X slot uses PCI IRQ A, int 29  */
+		irq = (1 << 8) + 29;
+		break;
+	default:fatal("i31244 in non-implemented machine type %i\n",
+		    machine->machine_type);
+		exit(1);
+	}
+
+	PCI_SET_DATA(PCI_INTERRUPT_REG, 0x01100000 | irq);
+
+	allocate_device_space(pd, 0x1000, 0, &port, &memaddr);
+	allocate_device_space(pd, 0x1000, 0, &port, &memaddr);
+
+	/*  PCI IDE using dev_wdc:  */
+	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
+	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
+		char tmpstr[2000];
+		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s.%i",
+		    (long long)(pd->pcibus->pci_actual_io_offset + 0),
+		    pd->pcibus->irq_path_pci, irq & 255);
+		device_add(machine, tmpstr);
+	}
+}
+
+int piix_isa_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
+{
+	switch (reg) {
+	case PCI_MAPREG_START:
+	case PCI_MAPREG_START + 4:
+	case PCI_MAPREG_START + 8:
+	case PCI_MAPREG_START + 12:
+	case PCI_MAPREG_START + 16:
+	case PCI_MAPREG_START + 20:
+		PCI_SET_DATA(reg, value);
+		return 1;
+	}
+
+	return 0;
+}
+
+PCIINIT(piix3_isa)
+{
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_INTEL,
+	    PCI_PRODUCT_INTEL_82371SB_ISA));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x01);	/*  Rev 1  */
+
+	PCI_SET_DATA(PCI_BHLC_REG,
+	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
+}
+
+PCIINIT(piix4_isa)
+{
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_INTEL,
+	    PCI_PRODUCT_INTEL_82371AB_ISA));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x01);	/*  Rev 1  */
+
+	PCI_SET_DATA(PCI_BHLC_REG,
+	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
+
+	pd->cfg_reg_write = piix_isa_cfg_reg_write;
+}
+
+PCIINIT(i82378zb)
+{
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_INTEL,
+	    PCI_PRODUCT_INTEL_SIO));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x43);
+
+	PCI_SET_DATA(PCI_BHLC_REG,
+	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
+
+	PCI_SET_DATA(0x40, 0x20);
+
+	/*  PIRQ[0]=10 PIRQ[1]=11 PIRQ[2]=14 PIRQ[3]=15  */
+	PCI_SET_DATA(0x60, 0x0f0e0b0a);
+}
+
+struct piix_ide_extra {
+	void	*wdc0;
+	void	*wdc1;
+};
+
+int piix_ide_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
+{
+	void *wdc0 = ((struct piix_ide_extra *)pd->extra)->wdc0;
+	void *wdc1 = ((struct piix_ide_extra *)pd->extra)->wdc1;
+	int enabled = 0;
+
+	PCI_SET_DATA(reg, value);
+
+	switch (reg) {
+	case PCI_COMMAND_STATUS_REG:
+		if (value & PCI_COMMAND_IO_ENABLE)
+			enabled = 1;
+		if (wdc0 != NULL)
+			wdc_set_io_enabled((struct wdc_data *) wdc0, enabled);
+		if (wdc1 != NULL)
+			wdc_set_io_enabled((struct wdc_data *) wdc1, enabled);
+		return 1;
+	case PCI_MAPREG_START:
+	case PCI_MAPREG_START + 4:
+	case PCI_MAPREG_START + 8:
+	case PCI_MAPREG_START + 12:
+	case PCI_MAPREG_START + 16:
+	case PCI_MAPREG_START + 20:
+		return 1;
+	}
+
+	return 0;
+}
+
+PCIINIT(piix3_ide)
+{
+	char tmpstr[2000];
+
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_INTEL,
+	    PCI_PRODUCT_INTEL_82371SB_IDE));
+
+	/*  Possibly not correct:  */
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
+	    PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x00);
+
+	/*  PIIX_IDETIM (see NetBSD's pciide_piix_reg.h)  */
+	/*  channel 0 and 1 enabled as IDE  */
+	PCI_SET_DATA(0x40, 0x80008000);
+
+	CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct piix_ide_extra)));
+	((struct piix_ide_extra *)pd->extra)->wdc0 = NULL;
+	((struct piix_ide_extra *)pd->extra)->wdc1 = NULL;
+
+	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
+	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
+		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx "
+		    "irq=%s.isa.%i", (long long)(pd->pcibus->isa_portbase +
+		    0x1f0), pd->pcibus->irq_path_isa, 14);
+		((struct piix_ide_extra *)pd->extra)->wdc0 =
+		    device_add(machine, tmpstr);
+	}
+
+	if (diskimage_exist(machine, 2, DISKIMAGE_IDE) ||
+	    diskimage_exist(machine, 3, DISKIMAGE_IDE)) {
+		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx "
+		    "irq=%s.isa.%i", (long long)(pd->pcibus->isa_portbase +
+		    0x170), pd->pcibus->irq_path_isa, 15);
+		((struct piix_ide_extra *)pd->extra)->wdc1 =
+		    device_add(machine, tmpstr);
+	}
+
+	pd->cfg_reg_write = piix_ide_cfg_reg_write;
+}
+
+PCIINIT(piix4_ide)
+{
+	char tmpstr[2000];
+
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_INTEL,
+	    PCI_PRODUCT_INTEL_82371AB_IDE));
+
+	/*  Possibly not correct:  */
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
+	    PCI_SUBCLASS_MASS_STORAGE_IDE, 0x80) + 0x01);
+
+	/*  PIIX_BMIBA (see NetBSD's pciide_piix_reg.h)  */
+	/*  2009-05-18: Needs to have the lowest bit set, or Linux/Malta
+	    crashes.  */
+	PCI_SET_DATA(0x20, 1);
+
+	/*  PIIX_IDETIM (see NetBSD's pciide_piix_reg.h)  */
+	/*  channel 0 and 1 enabled as IDE  */
+	PCI_SET_DATA(0x40, 0x80008000);
+
+	CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct piix_ide_extra)));
+	((struct piix_ide_extra *)pd->extra)->wdc0 = NULL;
+	((struct piix_ide_extra *)pd->extra)->wdc1 = NULL;
+
+	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
+	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
+		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
+		    "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0),
+		    pd->pcibus->irq_path_isa, 14);
+		((struct piix_ide_extra *)pd->extra)->wdc0 =
+		    device_add(machine, tmpstr);
+	}
+
+	if (diskimage_exist(machine, 2, DISKIMAGE_IDE) ||
+	    diskimage_exist(machine, 3, DISKIMAGE_IDE)) {
+		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
+		    "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170),
+		    pd->pcibus->irq_path_isa, 15);
+		((struct piix_ide_extra *)pd->extra)->wdc1 =
+		    device_add(machine, tmpstr);
+	}
+
+	pd->cfg_reg_write = piix_ide_cfg_reg_write;
+}
+
+
+
+/*
+ *  IBM ISA bridge (used by at least one PReP machine).
+ */
+
+#define	PCI_VENDOR_IBM			0x1014
+#define	PCI_PRODUCT_IBM_ISABRIDGE	0x000a
+
+PCIINIT(ibm_isa)
+{
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_IBM,
+	    PCI_PRODUCT_IBM_ISABRIDGE));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x02);
+
+	PCI_SET_DATA(PCI_BHLC_REG,
+	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
+}
+
+
+
+/*
+ *  Heuricon PCI host bridge for PM/PPC.
+ */
+
+#define	PCI_VENDOR_HEURICON		0x1223
+#define	PCI_PRODUCT_HEURICON_PMPPC	0x000e
+
+PCIINIT(heuricon_pmppc)
+{
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_HEURICON,
+	    PCI_PRODUCT_HEURICON_PMPPC));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x00);   /*  Revision?  */
+
+	PCI_SET_DATA(PCI_BHLC_REG,
+	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
+}
+
+
+
+/*
+ *  VIATECH VT82C586 devices:
+ *
+ *	vt82c586_isa	PCI->ISA bridge
+ *	vt82c586_ide	IDE controller
+ *
+ *  TODO:  This more or less just a dummy device, so far.
+ */
+
+#define PCI_VENDOR_VIATECH                0x1106  /* VIA Technologies */
+#define PCI_PRODUCT_VIATECH_VT82C586_IDE  0x1571  /* VT82C586 (Apollo VP)
+					             IDE Controller */
+#define PCI_PRODUCT_VIATECH_VT82C586_ISA  0x0586  /* VT82C586 (Apollo VP)
+						     PCI-ISA Bridge */
+
+PCIINIT(vt82c586_isa)
+{
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_VIATECH,
+	    PCI_PRODUCT_VIATECH_VT82C586_ISA));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x39);   /*  Revision 37 or 39  */
+
+	PCI_SET_DATA(PCI_BHLC_REG,
+	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
+
+	/*
+	 *  NetBSD/cobalt specific: bits 7..4 are the "model id". See
+	 *  netbsd/usr/src/sys/arch/cobalt/cobalt/machdep.c read_board_id()
+	 *  for details.
+	 */
+	if (machine->machine_type == MACHINE_COBALT) {
+#define	COBALT_PCIB_BOARD_ID_REG	0x94
+#define	COBALT_QUBE2_ID			5
+		PCI_SET_DATA(COBALT_PCIB_BOARD_ID_REG, COBALT_QUBE2_ID << 4);
+	}
+}
+
+struct vt82c586_ide_extra {
+	void	*wdc0;
+	void	*wdc1;
+};
+
+int vt82c586_ide_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
+{
+	void *wdc0 = ((struct vt82c586_ide_extra *)pd->extra)->wdc0;
+	void *wdc1 = ((struct vt82c586_ide_extra *)pd->extra)->wdc1;
+	int enabled = 0;
+
+	switch (reg) {
+	case PCI_COMMAND_STATUS_REG:
+		if (value & PCI_COMMAND_IO_ENABLE)
+			enabled = 1;
+		if (wdc0 != NULL)
+			wdc_set_io_enabled((struct wdc_data *) wdc0, enabled);
+		if (wdc1 != NULL)
+			wdc_set_io_enabled((struct wdc_data *) wdc1, enabled);
+		return 1;
+	}
+
+	return 0;
+}
+
+PCIINIT(vt82c586_ide)
+{
+	char tmpstr[2000];
+
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_VIATECH,
+	    PCI_PRODUCT_VIATECH_VT82C586_IDE));
+
+	/*  Possibly not correct:  */
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
+	    PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x01);
+
+	/*  APO_IDECONF  */
+	/*  channel 0 and 1 enabled  */
+	PCI_SET_DATA(0x40, 0x00000003);
+
+	CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct vt82c586_ide_extra)));
+	((struct vt82c586_ide_extra *)pd->extra)->wdc0 = NULL;
+	((struct vt82c586_ide_extra *)pd->extra)->wdc1 = NULL;
+
+	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
+	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
+		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
+		    "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0),
+		    pd->pcibus->irq_path_isa, 14);
+		((struct vt82c586_ide_extra *)pd->extra)->wdc0 =
+		    device_add(machine, tmpstr);
+	}
+
+	if (diskimage_exist(machine, 2, DISKIMAGE_IDE) ||
+	    diskimage_exist(machine, 3, DISKIMAGE_IDE)) {
+		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
+		    "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170),
+		    pd->pcibus->irq_path_isa, 15);
+		((struct vt82c586_ide_extra *)pd->extra)->wdc1 =
+		    device_add(machine, tmpstr);
+	}
+
+	pd->cfg_reg_write = vt82c586_ide_cfg_reg_write;
+}
+
+
+
+/*
+ *  Symphony Labs 83C553 PCI->ISA bridge.
+ *  Symphony Labs 82C105 PCIIDE controller.
+ */
+
+#define PCI_VENDOR_SYMPHONY		0x10ad
+#define PCI_PRODUCT_SYMPHONY_83C553	0x0565
+#define	PCI_PRODUCT_SYMPHONY_82C105	0x0105
+
+PCIINIT(symphony_83c553)
+{
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_SYMPHONY,
+	    PCI_PRODUCT_SYMPHONY_83C553));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x10);
+
+	PCI_SET_DATA(PCI_BHLC_REG,
+	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
+
+	switch (machine->machine_type) {
+	case MACHINE_NETWINDER:
+		bus_isa_init(machine, pd->pcibus->irq_path_isa,
+		    0, 0x7c000000, 0x80000000);
+		break;
+	default:fatal("symphony_83c553 init: unimplemented machine type\n");
+		exit(1);
+	}
+}
+
+struct symphony_82c105_extra {
+	void	*wdc0;
+	void	*wdc1;
+};
+
+int symphony_82c105_cfg_reg_write(struct pci_device *pd, int reg,
+	uint32_t value)
+{
+	void *wdc0 = ((struct symphony_82c105_extra *)pd->extra)->wdc0;
+	void *wdc1 = ((struct symphony_82c105_extra *)pd->extra)->wdc1;
+	int enabled = 0;
+
+printf("reg = 0x%x\n", reg);
+	switch (reg) {
+	case PCI_COMMAND_STATUS_REG:
+		if (value & PCI_COMMAND_IO_ENABLE)
+			enabled = 1;
+printf("  value = 0x%" PRIx32"\n", value);
+		if (wdc0 != NULL)
+			wdc_set_io_enabled((struct wdc_data *) wdc0, enabled);
+		if (wdc1 != NULL)
+			wdc_set_io_enabled((struct wdc_data *) wdc1, enabled);
+		/*  Set all bits:  */
+		PCI_SET_DATA(reg, value);
+		return 1;
+	case PCI_MAPREG_START:
+	case PCI_MAPREG_START + 4:
+	case PCI_MAPREG_START + 8:
+	case PCI_MAPREG_START + 12:
+	case PCI_MAPREG_START + 16:
+	case PCI_MAPREG_START + 20:
+		PCI_SET_DATA(reg, value);
+		return 1;
+	}
+
+	return 0;
+}
+
+PCIINIT(symphony_82c105)
+{
+	char tmpstr[2000];
+
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_SYMPHONY,
+	    PCI_PRODUCT_SYMPHONY_82C105));
+
+	/*  Possibly not correct:  */
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
+	    PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x05);
+
+	/*  TODO: Interrupt line:  */
+	/*  PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000);  */
+
+	/*  APO_IDECONF  */
+	/*  channel 0 and 1 enabled  */
+	PCI_SET_DATA(0x40, 0x00000003);
+
+	CHECK_ALLOCATION(pd->extra =
+	    malloc(sizeof(struct symphony_82c105_extra)));
+	((struct symphony_82c105_extra *)pd->extra)->wdc0 = NULL;
+	((struct symphony_82c105_extra *)pd->extra)->wdc1 = NULL;
+
+	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
+	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
+		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
+		    "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0),
+		    pd->pcibus->irq_path_isa, 14);
+		((struct symphony_82c105_extra *)pd->extra)->wdc0 =
+		    device_add(machine, tmpstr);
+	}
+
+	if (diskimage_exist(machine, 2, DISKIMAGE_IDE) ||
+	    diskimage_exist(machine, 3, DISKIMAGE_IDE)) {
+		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
+		    "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170),
+		    pd->pcibus->irq_path_isa, 15);
+		((struct symphony_82c105_extra *)pd->extra)->wdc1 =
+		    device_add(machine, tmpstr);
+	}
+
+	pd->cfg_reg_write = symphony_82c105_cfg_reg_write;
+}
+
+
+
+/*
+ *  Realtek 8139C+ PCI ethernet.
+ */
+
+#define PCI_VENDOR_REALTEK		0x10ec
+#define	PCI_PRODUCT_REALTEK_RT8139	0x8139
+
+PCIINIT(rtl8139c)
+{
+	uint64_t port, memaddr;
+	int pci_int_line = 0x101, irq = 0;
+	char irqstr[1000];
+	char tmpstr[2000];
+
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_REALTEK,
+	    PCI_PRODUCT_REALTEK_RT8139));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_NETWORK,
+	    PCI_SUBCLASS_NETWORK_ETHERNET, 0x00) + 0x20);
+
+	switch (machine->machine_type) {
+	case MACHINE_LANDISK:
+		irq = 5;
+		pci_int_line = 0x105;
+		break;
+	default:fatal("rtl8139c for this machine has not been "
+		    "implemented yet\n");
+		exit(1);
+	}
+
+	PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000 | pci_int_line);
+
+	allocate_device_space(pd, 0x100, 0, &port, &memaddr);
+
+	snprintf(irqstr, sizeof(irqstr), "%s.%i",
+	    pd->pcibus->irq_path_pci, irq);
+
+	snprintf(tmpstr, sizeof(tmpstr), "rtl8139c addr=0x%llx "
+	    "irq=%s pci_little_endian=1", (long long)port, irqstr);
+
+	device_add(machine, tmpstr);
+}
+
+
+
+/*
+ *  DEC 21143 ("Tulip") PCI ethernet.
+ */
+
+#define PCI_VENDOR_DEC          0x1011 /* Digital Equipment */
+#define PCI_PRODUCT_DEC_21142   0x0019 /* DECchip 21142/21143 10/100 Ethernet */
+
+PCIINIT(dec21143)
+{
+	uint64_t port, memaddr;
+	int pci_int_line = 0x101, irq = 0, isa = 0;
+	char irqstr[1000];
+	char tmpstr[2000];
+
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_DEC,
+	    PCI_PRODUCT_DEC_21142));
+
+	PCI_SET_DATA(PCI_COMMAND_STATUS_REG, 0x02000017);
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_NETWORK,
+	    PCI_SUBCLASS_NETWORK_ETHERNET, 0x00) + 0x41);
+
+	PCI_SET_DATA(PCI_BHLC_REG, PCI_BHLC_CODE(0,0,0, 0x40,0));
+
+	switch (machine->machine_type) {
+	case MACHINE_CATS:
+		/*  CATS int 18 = PCI.  */
+		irq = 18;
+		pci_int_line = 0x101;
+		break;
+	case MACHINE_COBALT:
+		/*  On Cobalt, IRQ 7 = PCI.  */
+		irq = 8 + 7;
+		pci_int_line = 0x407;
+		break;
+	case MACHINE_PREP:
+		irq = 10;
+		isa = 1;
+		pci_int_line = 0x20a;
+		break;
+	case MACHINE_MVMEPPC:
+		/*  TODO  */
+		irq = 10;
+		pci_int_line = 0x40a;
+		break;
+	case MACHINE_PMPPC:
+		/*  TODO, not working yet  */
+		irq = 31 - CPC_IB_EXT1;
+		pci_int_line = 0x101;
+		break;
+	case MACHINE_MACPPC:
+		/*  TODO, not working yet  */
+		irq = 25;
+		pci_int_line = 0x101;
+		break;
+	}
+
+	PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000 | pci_int_line);
+
+	allocate_device_space(pd, 0x100, 0x100, &port, &memaddr);
+
+	if (isa)
+		snprintf(irqstr, sizeof(irqstr), "%s.isa.%i",
+		    pd->pcibus->irq_path_isa, irq);
+	else
+		snprintf(irqstr, sizeof(irqstr), "%s.%i",
+		    pd->pcibus->irq_path_pci, irq);
+
+	snprintf(tmpstr, sizeof(tmpstr), "dec21143 addr=0x%llx addr2=0x%llx "
+	    "irq=%s pci_little_endian=1", (long long)port,
+	    (long long)memaddr, irqstr);
+
+	device_add(machine, tmpstr);
+}
+
+
+
+/*
+ *  DEC 21030 "tga" graphics.
+ */
+
+#define PCI_PRODUCT_DEC_21030  0x0004          /*  DECchip 21030 ("TGA")  */
+
+PCIINIT(dec21030)
+{
+	uint64_t base = 0;
+	char tmpstr[2000];
+
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_DEC,
+	    PCI_PRODUCT_DEC_21030));
+
+	PCI_SET_DATA(PCI_COMMAND_STATUS_REG, 0x02800087);  /*  TODO  */
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_DISPLAY,
+	    PCI_SUBCLASS_DISPLAY_VGA, 0x00) + 0x03);
+
+	/*
+	 *  See http://mail-index.netbsd.org/port-arc/2001/08/13/0000.html
+	 *  for more info.
+	 */
+
+	PCI_SET_DATA(PCI_BHLC_REG, 0x0000ff00);
+
+	/*  8 = prefetchable  */
+	PCI_SET_DATA(0x10, 0x00000008);
+	PCI_SET_DATA(0x30, 0x08000001);
+	PCI_SET_DATA(PCI_INTERRUPT_REG, 0x00000100);	/*  interrupt pin A?  */
+
+	/*
+	 *  Experimental:
+	 *
+	 *  TODO: Base address, pci_little_endian, ...
+	 */
+
+	switch (machine->machine_type) {
+	case MACHINE_ARC:
+		base = 0x100000000ULL;
+		break;
+	default:fatal("dec21030 in non-implemented machine type %i\n",
+		    machine->machine_type);
+		exit(1);
+	}
+
+	snprintf(tmpstr, sizeof(tmpstr), "dec21030 addr=0x%llx",
+	    (long long)(base));
+	device_add(machine, tmpstr);
+}
+
+
+
+/*
+ *  Motorola MPC105 "Eagle" Host Bridge
+ *
+ *  Used in at least PReP and BeBox.
+ */
+
+#define	PCI_VENDOR_MOT			0x1057
+#define	PCI_PRODUCT_MOT_MPC105		0x0001
+
+PCIINIT(eagle)
+{
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_MOT,
+	    PCI_PRODUCT_MOT_MPC105));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x24);
+
+	PCI_SET_DATA(PCI_BHLC_REG,
+	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
+}
+
+
+
+/*
+ *  Apple (MacPPC) stuff:
+ *
+ *  Grand Central (I/O controller)
+ *  Uni-North (PCI controller)
+ */
+
+#define	PCI_VENDOR_APPLE		0x106b
+#define	PCI_PRODUCT_APPLE_GC		0x0002
+#define	PCI_PRODUCT_APPLE_UNINORTH1	0x001e
+
+PCIINIT(gc_obio)
+{
+	uint64_t port, memaddr;
+
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_APPLE,
+	    PCI_PRODUCT_APPLE_GC));
+
+	/*  TODO:  */
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_SYSTEM,
+	    PCI_SUBCLASS_SYSTEM_PIC, 0) + 0x00);
+
+	PCI_SET_DATA(PCI_BHLC_REG,
+	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
+
+	/*  TODO  */
+	allocate_device_space(pd, 0x10000, 0x10000, &port, &memaddr);
+}
+
+PCIINIT(uninorth)
+{
+	uint64_t port, memaddr;
+
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_APPLE,
+	    PCI_PRODUCT_APPLE_UNINORTH1));
+
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_HOST, 0) + 0xff);
+
+	PCI_SET_DATA(PCI_BHLC_REG,
+	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
+
+	/*  TODO  */
+	allocate_device_space(pd, 0x10000, 0x10000, &port, &memaddr);
+}
+
+
+
+/*
+ *  ATI graphics cards
+ */
+
+#define	PCI_VENDOR_ATI			0x1002
+#define	PCI_PRODUCT_ATI_RADEON_9200_2	0x5962
+
+PCIINIT(ati_radeon_9200_2)
+{
+	uint64_t port, memaddr;
+
+	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_ATI,
+	    PCI_PRODUCT_ATI_RADEON_9200_2));
+
+	/*  TODO: other subclass?  */
+	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_DISPLAY,
+	    PCI_SUBCLASS_DISPLAY_VGA, 0) + 0x03);
+
+	/*  TODO  */
+	allocate_device_space(pd, 0x1000, 0x400000, &port, &memaddr);
+}
+
diff -Nru gxemul-0.6.2/src/devices/bus_pci.cc gxemul-0.7.0+dfsg/src/devices/bus_pci.cc
--- gxemul-0.6.2/src/devices/bus_pci.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/bus_pci.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1423 +0,0 @@
-/*
- *  Copyright (C) 2004-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Generic PCI bus framework
- *
- *  This is not a normal "device", but is used by individual PCI controllers
- *  and devices.
- *
- *  See NetBSD's pcidevs.h for more PCI vendor and device identifiers.
- *
- *  TODO:
- *
- *	x) Allow guest OSes to do runtime address fixups (i.e. actually
- *	   move a device from one address to another).
- *
- *	x) Generalize the PCI and legacy ISA interrupt routing stuff.
- *
- *	x) Make sure that pci_little_endian is used correctly everywhere.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#define BUS_PCI_C
-
-#include "bus_isa.h"
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "wdc.h"
-
-#include "thirdparty/cpc700reg.h"
-
-extern int verbose;
-
-// #ifdef UNSTABLE_DEVEL
-// #define debug fatal
-// #endif
-
-
-/*
- *  bus_pci_decompose_1():
- *
- *  Helper function for decomposing Mechanism 1 tags.
- */
-void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
-{
-	*bus  = (t >> 16) & 0xff;
-	*dev  = (t >> 11) & 0x1f;
-	*func = (t >>  8) &  0x7;
-	*reg  =  t        & 0xff;
-
-	/*  Warn about unaligned register access:  */
-	if (t & 3)
-		fatal("[ bus_pci_decompose_1: WARNING: reg = 0x%02x ]\n",
-		    t & 0xff);
-}
-
-
-/*
- *  bus_pci_data_access():
- *
- *  Reads from or writes to the PCI configuration registers of a device.
- */
-void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data,
-	uint64_t *data, int len, int writeflag)
-{
-	struct pci_device *dev;
-	unsigned char *cfg_base;
-	uint64_t x, idata = *data;
-	int i;
-
-	/*  Scan through the list of pci_device entries.  */
-	dev = pci_data->first_device;
-	while (dev != NULL) {
-		if (dev->bus      == pci_data->cur_bus &&
-		    dev->function == pci_data->cur_func &&
-		    dev->device   == pci_data->cur_device)
-			break;
-		dev = dev->next;
-	}
-
-	/*  No device? Then return emptiness.  */
-	if (dev == NULL) {
-		if (writeflag == MEM_READ) {
-			if (pci_data->cur_reg == 0)
-				*data = (uint64_t) -1;
-			else
-				*data = 0;
-		} else {
-			fatal("[ bus_pci_data_access(): write to non-existant"
-			    " device, bus %i func %i device %i ]\n",
-			    pci_data->cur_bus, pci_data->cur_func,
-			    pci_data->cur_device);
-		}
-		return;
-	}
-
-	/*  Return normal config data, or length data?  */
-	if (pci_data->last_was_write_ffffffff &&
-	    pci_data->cur_reg >= PCI_MAPREG_START &&
-	    pci_data->cur_reg <= PCI_MAPREG_END - 4)
-		cfg_base = dev->cfg_mem_size;
-	else
-		cfg_base = dev->cfg_mem;
-
-	/*  Read data as little-endian:  */
-	x = 0;
-	for (i=len-1; i>=0; i--) {
-		int ofs = pci_data->cur_reg + i;
-		x <<= 8;
-		x |= cfg_base[ofs & (PCI_CFG_MEM_SIZE - 1)];
-	}
-
-	/*  Register write:  */
-	if (writeflag == MEM_WRITE) {
-		debug("[ bus_pci: write to PCI DATA: data = 0x%08llx ]\n",
-		    (long long)idata);
-		if (idata == 0xffffffffULL &&
-		    pci_data->cur_reg >= PCI_MAPREG_START &&
-		    pci_data->cur_reg <= PCI_MAPREG_END - 4) {
-			pci_data->last_was_write_ffffffff = 1;
-			return;
-		}
-
-		if (dev->cfg_reg_write == NULL ||
-		    dev->cfg_reg_write(dev, pci_data->cur_reg, *data) == 0) {
-			/*  Print a warning for unhandled writes:  */
-			debug("[ bus_pci: write to PCI DATA: data = 0x%08llx"
-			    " (current value = 0x%08llx); NOT YET"
-			    " SUPPORTED. bus %i, device %i, function %i (%s)"
-			    " register 0x%02x ]\n", (long long)idata,
-			    (long long)x, pci_data->cur_bus,
-			    pci_data->cur_device, pci_data->cur_func,
-			    dev->name, pci_data->cur_reg);
-
-			/*  Special warning, to detect if NetBSD's special
-			    detection of PCI devices fails:  */
-			if (pci_data->cur_reg == PCI_COMMAND_STATUS_REG
-			    && !((*data) & PCI_COMMAND_IO_ENABLE)) {
-				fatal("\n[ NetBSD PCI detection stuff not"
-				    " yet implemented for device '%s' ]\n",
-				    dev->name);
-			}
-		}
-		return;
-	}
-
-	/*  Register read:  */
-	*data = x;
-
-	pci_data->last_was_write_ffffffff = 0;
-
-	debug("[ bus_pci: read from PCI DATA, bus %i, device "
-	    "%i, function %i (%s) register 0x%02x: (len=%i) 0x%08lx ]\n",
-	    pci_data->cur_bus, pci_data->cur_device, pci_data->cur_func,
-	    dev->name, pci_data->cur_reg, len, (long)*data);
-}
-
-
-/*
- *  bus_pci_setaddr():
- *
- *  Sets the address in preparation for a PCI register transfer.
- */
-void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data,
-	int bus, int device, int function, int reg)
-{
-	if (cpu == NULL || pci_data == NULL) {
-		fatal("bus_pci_setaddr(): NULL ptr\n");
-		exit(1);
-	}
-
-	pci_data->cur_bus = bus;
-	pci_data->cur_device = device;
-	pci_data->cur_func = function;
-	pci_data->cur_reg = reg;
-}
-
-
-/*
- *  bus_pci_add():
- *
- *  Add a PCI device to a bus_pci device.
- */
-void bus_pci_add(struct machine *machine, struct pci_data *pci_data,
-	struct memory *mem, int bus, int device, int function,
-	const char *name)
-{
-	struct pci_device *pd;
-	int ofs;
-	void (*init)(struct machine *, struct memory *, struct pci_device *);
-
-	if (pci_data == NULL) {
-		fatal("bus_pci_add(): pci_data == NULL!\n");
-		abort();
-	}
-
-	/*  Find the PCI device:  */
-	init = pci_lookup_initf(name);
-
-	/*  Make sure this bus/device/function number isn't already in use:  */
-	pd = pci_data->first_device;
-	while (pd != NULL) {
-		if (pd->bus == bus && pd->device == device &&
-		    pd->function == function) {
-			fatal("bus_pci_add(): (bus %i, device %i, function"
-			    " %i) already in use\n", bus, device, function);
-			exit(1);
-		}
-		pd = pd->next;
-	}
-
-	CHECK_ALLOCATION(pd = (struct pci_device *) malloc(sizeof(struct pci_device)));
-	memset(pd, 0, sizeof(struct pci_device));
-
-	/*  Add the new device first in the PCI bus' chain:  */
-	pd->next = pci_data->first_device;
-	pci_data->first_device = pd;
-
-	CHECK_ALLOCATION(pd->name = strdup(name));
-	pd->pcibus   = pci_data;
-	pd->bus      = bus;
-	pd->device   = device;
-	pd->function = function;
-
-	/*
-	 *  Initialize with some default values:
-	 *
-	 *  TODO:  The command status register is best to set up per device.
-	 *  The size registers should also be set up on a per-device basis.
-	 */
-	PCI_SET_DATA(PCI_COMMAND_STATUS_REG,
-	    PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
-	for (ofs = PCI_MAPREG_START; ofs < PCI_MAPREG_END; ofs += 4)
-		PCI_SET_DATA_SIZE(ofs, 0x00100000 - 1);
-
-	if (init == NULL) {
-		fatal("No init function for PCI device \"%s\"?\n", name);
-		exit(1);
-	}
-
-	/*  Call the PCI device' init function:  */
-	init(machine, mem, pd);
-}
-
-
-/*
- *  allocate_device_space():
- *
- *  Used by glue code (see below) to allocate space for a PCI device.
- *
- *  The returned values in portp and memp are the actual (emulated) addresses
- *  that the device should use. (Normally only one of these is actually used.)
- *
- *  TODO: PCI irqs?
- */
-static void allocate_device_space(struct pci_device *pd,
-	uint64_t portsize, uint64_t memsize,
-	uint64_t *portp, uint64_t *memp)
-{
-	uint64_t port, mem;
-
-	/*  Calculate an aligned starting port:  */
-	port = pd->pcibus->cur_pci_portbase;
-	if (portsize != 0) {
-		port = ((port - 1) | (portsize - 1)) + 1;
-		pd->pcibus->cur_pci_portbase = port;
-		PCI_SET_DATA(PCI_MAPREG_START + pd->cur_mapreg_offset,
-		    port | PCI_MAPREG_TYPE_IO);
-		PCI_SET_DATA_SIZE(PCI_MAPREG_START + pd->cur_mapreg_offset,
-		    ((portsize - 1) & ~0xf) | 0xd);
-		pd->cur_mapreg_offset += sizeof(uint32_t);
-	}
-
-	/*  Calculate an aligned starting memory location:  */
-	mem = pd->pcibus->cur_pci_membase;
-	if (memsize != 0) {
-		mem = ((mem - 1) | (memsize - 1)) + 1;
-		pd->pcibus->cur_pci_membase = mem;
-		PCI_SET_DATA(PCI_MAPREG_START + pd->cur_mapreg_offset, mem);
-		PCI_SET_DATA_SIZE(PCI_MAPREG_START + pd->cur_mapreg_offset,
-		    ((memsize - 1) & ~0xf) | 0x0);
-		pd->cur_mapreg_offset += sizeof(uint32_t);
-	}
-
-	*portp = port + pd->pcibus->pci_actual_io_offset;
-	*memp  = mem  + pd->pcibus->pci_actual_mem_offset;
-
-	if (verbose >= 2) {
-		debug("pci device '%s' at", pd->name);
-		if (portsize != 0)
-			debug(" port 0x%llx-0x%llx", (long long)pd->pcibus->
-			    cur_pci_portbase, (long long)(pd->pcibus->
-			    cur_pci_portbase + portsize - 1));
-		if (memsize != 0)
-			debug(" mem 0x%llx-0x%llx", (long long)pd->pcibus->
-			    cur_pci_membase, (long long)(pd->pcibus->
-			    cur_pci_membase + memsize - 1));
-		debug("\n");
-	}
-
-	pd->pcibus->cur_pci_portbase += portsize;
-	pd->pcibus->cur_pci_membase += memsize;
-}
-
-
-/*
- *  bus_pci_init():
- *
- *  This doesn't register a device, but instead returns a pointer to a struct
- *  which should be passed to other bus_pci functions when accessing the bus.
- *
- *  irq_path is the interrupt path to the PCI controller.
- *
- *  pci_portbase, pci_membase, and pci_irqbase are the port, memory, and
- *  interrupt bases for PCI devices (as found in the configuration registers).
- *
- *  pci_actual_io_offset and pci_actual_mem_offset are the offset from
- *  the values in the configuration registers to the actual (emulated) device.
- *
- *  isa_portbase, isa_membase, and isa_irqbase are the port, memory, and
- *  interrupt bases for legacy ISA devices.
- */
-struct pci_data *bus_pci_init(struct machine *machine, const char *irq_path,
-	uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
-	uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase,
-	uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
-{
-	struct pci_data *d;
-
-	CHECK_ALLOCATION(d = (struct pci_data *) malloc(sizeof(struct pci_data)));
-	memset(d, 0, sizeof(struct pci_data));
-
-	CHECK_ALLOCATION(d->irq_path     = strdup(irq_path));
-	CHECK_ALLOCATION(d->irq_path_isa = strdup(isa_irqbase));
-	CHECK_ALLOCATION(d->irq_path_pci = strdup(pci_irqbase));
-
-	d->pci_actual_io_offset  = pci_actual_io_offset;
-	d->pci_actual_mem_offset = pci_actual_mem_offset;
-	d->pci_portbase          = pci_portbase;
-	d->pci_membase           = pci_membase;
-	d->isa_portbase          = isa_portbase;
-	d->isa_membase           = isa_membase;
-
-	d->cur_pci_portbase = d->pci_portbase;
-	d->cur_pci_membase  = d->pci_membase;
-
-	/*  Assume that the first 64KB could be used by legacy ISA devices:  */
-	if (d->isa_portbase != 0 || d->isa_membase != 0) {
-		d->cur_pci_portbase += 0x10000;
-		d->cur_pci_membase  += 0x10000;
-	}
-
-	return d;
-}
-
-
-
-/******************************************************************************
- *                                                                            *
- *  The following is glue code for PCI controllers and devices. The glue      *
- *  code does the minimal stuff necessary to get an emulated OS to detect     *
- *  the device (i.e. set up PCI configuration registers), and then if         *
- *  necessary adds a "normal" device.                                         *
- *                                                                            *
- ******************************************************************************/
-
-
-
-/*
- *  Integraphics Systems "igsfb" Framebuffer (graphics) card, used in at
- *  least the NetWinder.
- */
-
-#define	PCI_VENDOR_INTEGRAPHICS		0x10ea
-
-PCIINIT(igsfb)
-{
-	char tmpstr[2000];
-
-	PCI_SET_DATA(PCI_ID_REG,
-	    PCI_ID_CODE(PCI_VENDOR_INTEGRAPHICS, 0x2010));
-
-	PCI_SET_DATA(PCI_CLASS_REG,
-	    PCI_CLASS_CODE(PCI_CLASS_DISPLAY,
-	    PCI_SUBCLASS_DISPLAY_VGA, 0) + 0x01);
-
-	/*  TODO  */
-	PCI_SET_DATA(0x10, 0x08000000);
-
-	snprintf(tmpstr, sizeof(tmpstr), "igsfb addr=0x%llx",
-	    (long long)(pd->pcibus->isa_membase + 0x08000000));
-	device_add(machine, tmpstr);
-}
-
-
-
-/*
- *  S3 ViRGE graphics.
- *
- *  TODO: Only emulates a standard VGA card, so far.
- */
-
-#define PCI_VENDOR_S3			0x5333
-#define PCI_PRODUCT_S3_VIRGE		0x5631
-#define	PCI_PRODUCT_S3_VIRGE_DX		0x8a01
-
-PCIINIT(s3_virge)
-{
-	PCI_SET_DATA(PCI_ID_REG,
-	    PCI_ID_CODE(PCI_VENDOR_S3, PCI_PRODUCT_S3_VIRGE_DX));
-
-	PCI_SET_DATA(PCI_CLASS_REG,
-	    PCI_CLASS_CODE(PCI_CLASS_DISPLAY,
-	    PCI_SUBCLASS_DISPLAY_VGA, 0) + 0x01);
-
-	dev_vga_init(machine, mem, pd->pcibus->isa_membase + 0xa0000,
-	    pd->pcibus->isa_portbase + 0x3c0, machine->machine_name);
-}
-
-
-
-/*
- *  Acer Labs M5229 PCI-IDE (UDMA) controller.
- *  Acer Labs M1543 PCI->ISA bridge.
- */
-
-#define PCI_VENDOR_ALI			0x10b9
-#define PCI_PRODUCT_ALI_M1543		0x1533	/*  NOTE: not 1543  */
-#define	PCI_PRODUCT_ALI_M5229		0x5229
-
-PCIINIT(ali_m1543)
-{
-	PCI_SET_DATA(PCI_ID_REG,
-	    PCI_ID_CODE(PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1543));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0xc3);
-
-	PCI_SET_DATA(PCI_BHLC_REG,
-	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
-
-	/*  Linux uses these to detect which IRQ the IDE controller uses:  */
-	PCI_SET_DATA(0x44, 0x0000000e);
-	PCI_SET_DATA(0x58, 0x00000003);
-
-	switch (machine->machine_type) {
-	case MACHINE_CATS:
-		bus_isa_init(machine, pd->pcibus->irq_path_isa,
-		    BUS_ISA_PCKBC_FORCE_USE | BUS_ISA_PCKBC_NONPCSTYLE,
-		    0x7c000000, 0x80000000);
-		break;
-	default:fatal("ali_m1543 init: unimplemented machine type\n");
-		exit(1);
-	}
-}
-
-PCIINIT(ali_m5229)
-{
-	char tmpstr[2000], irqstr[1000];
-
-	PCI_SET_DATA(PCI_ID_REG,
-	    PCI_ID_CODE(PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5229));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
-	    PCI_SUBCLASS_MASS_STORAGE_IDE, 0x60) + 0xc1);
-
-	switch (machine->machine_type) {
-	case MACHINE_CATS:
-		/*  CATS ISA interrupts are at footbridge irq 10:  */
-		snprintf(irqstr, sizeof(irqstr), "%s.10.isa",
-		    pd->pcibus->irq_path);
-		break;
-	default:fatal("ali_m5229 init: unimplemented machine type\n");
-		exit(1);
-	}
-
-	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
-	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
-		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s.%i",
-		    (long long)(pd->pcibus->isa_portbase + 0x1f0),
-		    irqstr, 14);
-		device_add(machine, tmpstr);
-	}
-
-	/*  The secondary channel is disabled. TODO: fix this.  */
-}
-
-
-
-/*
- *  Adaptec AHC SCSI controller, with values as they are in my SGI O2.
- */
-
-#define PCI_VENDOR_ADP			0x9004          /* Adaptec */
-#define PCI_PRODUCT_ADP_AIC7880		0x8078          /* AIC7880 */
-
-PCIINIT(ahc)
-{
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_ADP,
-	    PCI_PRODUCT_ADP_AIC7880));
-
-	PCI_SET_DATA(PCI_COMMAND_STATUS_REG, 0x02800046);
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
-	    PCI_SUBCLASS_MASS_STORAGE_SCSI, 0) + 0x01);
-
-	PCI_SET_DATA(PCI_BHLC_REG, 0x00001020);
-
-	PCI_SET_DATA(PCI_MAPREG_START + 0x00, 0xffffff01);
-	PCI_SET_DATA(PCI_MAPREG_START + 0x04, 0x80001000);
-	PCI_SET_DATA(PCI_MAPREG_START + 0x08, 0x00000000);
-	PCI_SET_DATA(PCI_MAPREG_START + 0x0c, 0x00000000);
-	PCI_SET_DATA(PCI_MAPREG_START + 0x10, 0x00000000);
-	PCI_SET_DATA(PCI_MAPREG_START + 0x14, 0x00000000);
-	PCI_SET_DATA(PCI_MAPREG_START + 0x18, 0x00000000);
-
-	PCI_SET_DATA(PCI_MAPREG_START + 0x1c, 0x00000000);
-
-	PCI_SET_DATA(0x30, 0x80010000);
-	PCI_SET_DATA(PCI_INTERRUPT_REG, 0x08080100);	/*  interrupt pin  */
-
-	PCI_SET_DATA(0x40, 0x00000180);
-	PCI_SET_DATA(0x40, 0x00000180);
-
-
-	/*
-	 *  TODO:  this address is based on what NetBSD/sgimips uses
-	 *  on SGI IP32 (O2). Fix this! Allow devices to move? Or
-	 *  implement PCI space redirection at least!
-	 */
-
-	// device_add(machine, "ahc addr=0x1a001000");
-	device_add(machine, "ahc addr=0x18002000");
-}
-
-
-
-/*
- *  Galileo Technology GT-64xxx PCI controller.
- *
- *	GT-64011	Used in Cobalt machines.
- *	GT-64120	Used in evbmips machines (Malta).
- *
- *  NOTE: This works in the opposite way compared to other devices; the PCI
- *  device is added from the normal device instead of the other way around.
- */
-
-#define PCI_VENDOR_GALILEO           0x11ab    /* Galileo Technology */
-#define PCI_PRODUCT_GALILEO_GT64011  0x4146    /* GT-64011 System Controller */
-#define	PCI_PRODUCT_GALILEO_GT64120  0x4620    /* GT-64120 */
-#define	PCI_PRODUCT_GALILEO_GT64260  0x6430    /* GT-64260 */
-
-PCIINIT(gt64011)
-{
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_GALILEO,
-	    PCI_PRODUCT_GALILEO_GT64011));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x01);	/*  Revision 1  */
-}
-
-PCIINIT(gt64120)
-{
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_GALILEO,
-	    PCI_PRODUCT_GALILEO_GT64120));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x02);	/*  Revision 2?  */
-
-	switch (machine->machine_type) {
-	case MACHINE_EVBMIPS:
-		PCI_SET_DATA(PCI_MAPREG_START + 0x10, 0x1be00000);
-		break;
-	}
-}
-
-PCIINIT(gt64260)
-{
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_GALILEO,
-	    PCI_PRODUCT_GALILEO_GT64260));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x01);	/*  Revision 1?  */
-}
-
-
-
-/*
- *  AMD PCnet Ethernet card.
- *
- *  "Am79c970A PCnet-PCI II rev 0" or similar.
- */
-
-#define	PCI_VENDOR_AMD			0x1022	/* Advanced Micro Devices */
-#define	PCI_PRODUCT_AMD_PCNET_PCI	0x2000	/* PCnet-PCI Ethernet */
-
-PCIINIT(pcn)
-{
-	int irq;
-
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_AMD,
-	    PCI_PRODUCT_AMD_PCNET_PCI));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_NETWORK,
-	    PCI_SUBCLASS_NETWORK_ETHERNET, 0) + 0x00);	/*  Revision 0  */
-
-	switch (machine->machine_type) {
-
-	case MACHINE_EVBMIPS:
-		irq = (1 << 8) + 10;	/*  TODO  */
-		break;
-
-	default:fatal("pcn in non-implemented machine type %i\n",
-		    machine->machine_type);
-		exit(1);
-	}
-
-	PCI_SET_DATA(PCI_INTERRUPT_REG, 0x01100000 | irq);
-
-	/*
-	 *  TODO: Add the pcn device here. The pcn device will need to work as
-	 *  a wrapper for dev_le + all the DMA magic and whatever is required.
-	 *  It's too much to implement right now.
-	 */
-}
-
-
-
-/*
- *  Intel 31244   Serial ATA Controller
- *  Intel 82371SB PIIX3 PCI-ISA bridge
- *  Intel 82371AB PIIX4 PCI-ISA bridge
- *  Intel 82371SB IDE controller
- *  Intel 82371AB IDE controller
- *  Intel 82378ZB System I/O controller.
- */
-
-#define	PCI_VENDOR_INTEL		0x8086
-#define	PCI_PRODUCT_INTEL_31244		0x3200
-#define	PCI_PRODUCT_INTEL_82371SB_ISA	0x7000
-#define	PCI_PRODUCT_INTEL_82371SB_IDE	0x7010
-#define	PCI_PRODUCT_INTEL_82371AB_ISA	0x7110
-#define	PCI_PRODUCT_INTEL_82371AB_IDE	0x7111
-#define	PCI_PRODUCT_INTEL_SIO		0x0484
-
-PCIINIT(i31244)
-{
-	uint64_t port, memaddr;
-	int irq = 0;
-
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_INTEL,
-	    PCI_PRODUCT_INTEL_31244));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
-	    PCI_SUBCLASS_MASS_STORAGE_IDE, 0x33) + 0x00);
-
-	switch (machine->machine_type) {
-	case MACHINE_IQ80321:
-		/*  S-PCI-X slot uses PCI IRQ A, int 29  */
-		irq = (1 << 8) + 29;
-		break;
-	default:fatal("i31244 in non-implemented machine type %i\n",
-		    machine->machine_type);
-		exit(1);
-	}
-
-	PCI_SET_DATA(PCI_INTERRUPT_REG, 0x01100000 | irq);
-
-	allocate_device_space(pd, 0x1000, 0, &port, &memaddr);
-	allocate_device_space(pd, 0x1000, 0, &port, &memaddr);
-
-	/*  PCI IDE using dev_wdc:  */
-	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
-	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
-		char tmpstr[2000];
-		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s.%i",
-		    (long long)(pd->pcibus->pci_actual_io_offset + 0),
-		    pd->pcibus->irq_path_pci, irq & 255);
-		device_add(machine, tmpstr);
-	}
-}
-
-int piix_isa_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
-{
-	switch (reg) {
-	case PCI_MAPREG_START:
-	case PCI_MAPREG_START + 4:
-	case PCI_MAPREG_START + 8:
-	case PCI_MAPREG_START + 12:
-	case PCI_MAPREG_START + 16:
-	case PCI_MAPREG_START + 20:
-		PCI_SET_DATA(reg, value);
-		return 1;
-	}
-
-	return 0;
-}
-
-PCIINIT(piix3_isa)
-{
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_INTEL,
-	    PCI_PRODUCT_INTEL_82371SB_ISA));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x01);	/*  Rev 1  */
-
-	PCI_SET_DATA(PCI_BHLC_REG,
-	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
-}
-
-PCIINIT(piix4_isa)
-{
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_INTEL,
-	    PCI_PRODUCT_INTEL_82371AB_ISA));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x01);	/*  Rev 1  */
-
-	PCI_SET_DATA(PCI_BHLC_REG,
-	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
-
-	pd->cfg_reg_write = piix_isa_cfg_reg_write;
-}
-
-PCIINIT(i82378zb)
-{
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_INTEL,
-	    PCI_PRODUCT_INTEL_SIO));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x43);
-
-	PCI_SET_DATA(PCI_BHLC_REG,
-	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
-
-	PCI_SET_DATA(0x40, 0x20);
-
-	/*  PIRQ[0]=10 PIRQ[1]=11 PIRQ[2]=14 PIRQ[3]=15  */
-	PCI_SET_DATA(0x60, 0x0f0e0b0a);
-}
-
-struct piix_ide_extra {
-	void	*wdc0;
-	void	*wdc1;
-};
-
-int piix_ide_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
-{
-	void *wdc0 = ((struct piix_ide_extra *)pd->extra)->wdc0;
-	void *wdc1 = ((struct piix_ide_extra *)pd->extra)->wdc1;
-	int enabled = 0;
-
-	PCI_SET_DATA(reg, value);
-
-	switch (reg) {
-	case PCI_COMMAND_STATUS_REG:
-		if (value & PCI_COMMAND_IO_ENABLE)
-			enabled = 1;
-		if (wdc0 != NULL)
-			wdc_set_io_enabled((struct wdc_data *) wdc0, enabled);
-		if (wdc1 != NULL)
-			wdc_set_io_enabled((struct wdc_data *) wdc1, enabled);
-		return 1;
-	case PCI_MAPREG_START:
-	case PCI_MAPREG_START + 4:
-	case PCI_MAPREG_START + 8:
-	case PCI_MAPREG_START + 12:
-	case PCI_MAPREG_START + 16:
-	case PCI_MAPREG_START + 20:
-		return 1;
-	}
-
-	return 0;
-}
-
-PCIINIT(piix3_ide)
-{
-	char tmpstr[2000];
-
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_INTEL,
-	    PCI_PRODUCT_INTEL_82371SB_IDE));
-
-	/*  Possibly not correct:  */
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
-	    PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x00);
-
-	/*  PIIX_IDETIM (see NetBSD's pciide_piix_reg.h)  */
-	/*  channel 0 and 1 enabled as IDE  */
-	PCI_SET_DATA(0x40, 0x80008000);
-
-	CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct piix_ide_extra)));
-	((struct piix_ide_extra *)pd->extra)->wdc0 = NULL;
-	((struct piix_ide_extra *)pd->extra)->wdc1 = NULL;
-
-	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
-	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
-		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx "
-		    "irq=%s.isa.%i", (long long)(pd->pcibus->isa_portbase +
-		    0x1f0), pd->pcibus->irq_path_isa, 14);
-		((struct piix_ide_extra *)pd->extra)->wdc0 =
-		    device_add(machine, tmpstr);
-	}
-
-	if (diskimage_exist(machine, 2, DISKIMAGE_IDE) ||
-	    diskimage_exist(machine, 3, DISKIMAGE_IDE)) {
-		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx "
-		    "irq=%s.isa.%i", (long long)(pd->pcibus->isa_portbase +
-		    0x170), pd->pcibus->irq_path_isa, 15);
-		((struct piix_ide_extra *)pd->extra)->wdc1 =
-		    device_add(machine, tmpstr);
-	}
-
-	pd->cfg_reg_write = piix_ide_cfg_reg_write;
-}
-
-PCIINIT(piix4_ide)
-{
-	char tmpstr[2000];
-
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_INTEL,
-	    PCI_PRODUCT_INTEL_82371AB_IDE));
-
-	/*  Possibly not correct:  */
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
-	    PCI_SUBCLASS_MASS_STORAGE_IDE, 0x80) + 0x01);
-
-	/*  PIIX_BMIBA (see NetBSD's pciide_piix_reg.h)  */
-	/*  2009-05-18: Needs to have the lowest bit set, or Linux/Malta
-	    crashes.  */
-	PCI_SET_DATA(0x20, 1);
-
-	/*  PIIX_IDETIM (see NetBSD's pciide_piix_reg.h)  */
-	/*  channel 0 and 1 enabled as IDE  */
-	PCI_SET_DATA(0x40, 0x80008000);
-
-	CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct piix_ide_extra)));
-	((struct piix_ide_extra *)pd->extra)->wdc0 = NULL;
-	((struct piix_ide_extra *)pd->extra)->wdc1 = NULL;
-
-	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
-	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
-		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
-		    "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0),
-		    pd->pcibus->irq_path_isa, 14);
-		((struct piix_ide_extra *)pd->extra)->wdc0 =
-		    device_add(machine, tmpstr);
-	}
-
-	if (diskimage_exist(machine, 2, DISKIMAGE_IDE) ||
-	    diskimage_exist(machine, 3, DISKIMAGE_IDE)) {
-		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
-		    "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170),
-		    pd->pcibus->irq_path_isa, 15);
-		((struct piix_ide_extra *)pd->extra)->wdc1 =
-		    device_add(machine, tmpstr);
-	}
-
-	pd->cfg_reg_write = piix_ide_cfg_reg_write;
-}
-
-
-
-/*
- *  IBM ISA bridge (used by at least one PReP machine).
- */
-
-#define	PCI_VENDOR_IBM			0x1014
-#define	PCI_PRODUCT_IBM_ISABRIDGE	0x000a
-
-PCIINIT(ibm_isa)
-{
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_IBM,
-	    PCI_PRODUCT_IBM_ISABRIDGE));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x02);
-
-	PCI_SET_DATA(PCI_BHLC_REG,
-	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
-}
-
-
-
-/*
- *  Heuricon PCI host bridge for PM/PPC.
- */
-
-#define	PCI_VENDOR_HEURICON		0x1223
-#define	PCI_PRODUCT_HEURICON_PMPPC	0x000e
-
-PCIINIT(heuricon_pmppc)
-{
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_HEURICON,
-	    PCI_PRODUCT_HEURICON_PMPPC));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x00);   /*  Revision?  */
-
-	PCI_SET_DATA(PCI_BHLC_REG,
-	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
-}
-
-
-
-/*
- *  VIATECH VT82C586 devices:
- *
- *	vt82c586_isa	PCI->ISA bridge
- *	vt82c586_ide	IDE controller
- *
- *  TODO:  This more or less just a dummy device, so far.
- */
-
-#define PCI_VENDOR_VIATECH                0x1106  /* VIA Technologies */
-#define PCI_PRODUCT_VIATECH_VT82C586_IDE  0x1571  /* VT82C586 (Apollo VP)
-					             IDE Controller */
-#define PCI_PRODUCT_VIATECH_VT82C586_ISA  0x0586  /* VT82C586 (Apollo VP)
-						     PCI-ISA Bridge */
-
-PCIINIT(vt82c586_isa)
-{
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_VIATECH,
-	    PCI_PRODUCT_VIATECH_VT82C586_ISA));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x39);   /*  Revision 37 or 39  */
-
-	PCI_SET_DATA(PCI_BHLC_REG,
-	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
-
-	/*
-	 *  NetBSD/cobalt specific: bits 7..4 are the "model id". See
-	 *  netbsd/usr/src/sys/arch/cobalt/cobalt/machdep.c read_board_id()
-	 *  for details.
-	 */
-	if (machine->machine_type == MACHINE_COBALT) {
-#define	COBALT_PCIB_BOARD_ID_REG	0x94
-#define	COBALT_QUBE2_ID			5
-		PCI_SET_DATA(COBALT_PCIB_BOARD_ID_REG, COBALT_QUBE2_ID << 4);
-	}
-}
-
-struct vt82c586_ide_extra {
-	void	*wdc0;
-	void	*wdc1;
-};
-
-int vt82c586_ide_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
-{
-	void *wdc0 = ((struct vt82c586_ide_extra *)pd->extra)->wdc0;
-	void *wdc1 = ((struct vt82c586_ide_extra *)pd->extra)->wdc1;
-	int enabled = 0;
-
-	switch (reg) {
-	case PCI_COMMAND_STATUS_REG:
-		if (value & PCI_COMMAND_IO_ENABLE)
-			enabled = 1;
-		if (wdc0 != NULL)
-			wdc_set_io_enabled((struct wdc_data *) wdc0, enabled);
-		if (wdc1 != NULL)
-			wdc_set_io_enabled((struct wdc_data *) wdc1, enabled);
-		return 1;
-	}
-
-	return 0;
-}
-
-PCIINIT(vt82c586_ide)
-{
-	char tmpstr[2000];
-
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_VIATECH,
-	    PCI_PRODUCT_VIATECH_VT82C586_IDE));
-
-	/*  Possibly not correct:  */
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
-	    PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x01);
-
-	/*  APO_IDECONF  */
-	/*  channel 0 and 1 enabled  */
-	PCI_SET_DATA(0x40, 0x00000003);
-
-	CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct vt82c586_ide_extra)));
-	((struct vt82c586_ide_extra *)pd->extra)->wdc0 = NULL;
-	((struct vt82c586_ide_extra *)pd->extra)->wdc1 = NULL;
-
-	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
-	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
-		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
-		    "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0),
-		    pd->pcibus->irq_path_isa, 14);
-		((struct vt82c586_ide_extra *)pd->extra)->wdc0 =
-		    device_add(machine, tmpstr);
-	}
-
-	if (diskimage_exist(machine, 2, DISKIMAGE_IDE) ||
-	    diskimage_exist(machine, 3, DISKIMAGE_IDE)) {
-		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
-		    "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170),
-		    pd->pcibus->irq_path_isa, 15);
-		((struct vt82c586_ide_extra *)pd->extra)->wdc1 =
-		    device_add(machine, tmpstr);
-	}
-
-	pd->cfg_reg_write = vt82c586_ide_cfg_reg_write;
-}
-
-
-
-/*
- *  Symphony Labs 83C553 PCI->ISA bridge.
- *  Symphony Labs 82C105 PCIIDE controller.
- */
-
-#define PCI_VENDOR_SYMPHONY		0x10ad
-#define PCI_PRODUCT_SYMPHONY_83C553	0x0565
-#define	PCI_PRODUCT_SYMPHONY_82C105	0x0105
-
-PCIINIT(symphony_83c553)
-{
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_SYMPHONY,
-	    PCI_PRODUCT_SYMPHONY_83C553));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x10);
-
-	PCI_SET_DATA(PCI_BHLC_REG,
-	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
-
-	switch (machine->machine_type) {
-	case MACHINE_NETWINDER:
-		bus_isa_init(machine, pd->pcibus->irq_path_isa,
-		    0, 0x7c000000, 0x80000000);
-		break;
-	default:fatal("symphony_83c553 init: unimplemented machine type\n");
-		exit(1);
-	}
-}
-
-struct symphony_82c105_extra {
-	void	*wdc0;
-	void	*wdc1;
-};
-
-int symphony_82c105_cfg_reg_write(struct pci_device *pd, int reg,
-	uint32_t value)
-{
-	void *wdc0 = ((struct symphony_82c105_extra *)pd->extra)->wdc0;
-	void *wdc1 = ((struct symphony_82c105_extra *)pd->extra)->wdc1;
-	int enabled = 0;
-
-printf("reg = 0x%x\n", reg);
-	switch (reg) {
-	case PCI_COMMAND_STATUS_REG:
-		if (value & PCI_COMMAND_IO_ENABLE)
-			enabled = 1;
-printf("  value = 0x%" PRIx32"\n", value);
-		if (wdc0 != NULL)
-			wdc_set_io_enabled((struct wdc_data *) wdc0, enabled);
-		if (wdc1 != NULL)
-			wdc_set_io_enabled((struct wdc_data *) wdc1, enabled);
-		/*  Set all bits:  */
-		PCI_SET_DATA(reg, value);
-		return 1;
-	case PCI_MAPREG_START:
-	case PCI_MAPREG_START + 4:
-	case PCI_MAPREG_START + 8:
-	case PCI_MAPREG_START + 12:
-	case PCI_MAPREG_START + 16:
-	case PCI_MAPREG_START + 20:
-		PCI_SET_DATA(reg, value);
-		return 1;
-	}
-
-	return 0;
-}
-
-PCIINIT(symphony_82c105)
-{
-	char tmpstr[2000];
-
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_SYMPHONY,
-	    PCI_PRODUCT_SYMPHONY_82C105));
-
-	/*  Possibly not correct:  */
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
-	    PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x05);
-
-	/*  TODO: Interrupt line:  */
-	/*  PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000);  */
-
-	/*  APO_IDECONF  */
-	/*  channel 0 and 1 enabled  */
-	PCI_SET_DATA(0x40, 0x00000003);
-
-	CHECK_ALLOCATION(pd->extra =
-	    malloc(sizeof(struct symphony_82c105_extra)));
-	((struct symphony_82c105_extra *)pd->extra)->wdc0 = NULL;
-	((struct symphony_82c105_extra *)pd->extra)->wdc1 = NULL;
-
-	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
-	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
-		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
-		    "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0),
-		    pd->pcibus->irq_path_isa, 14);
-		((struct symphony_82c105_extra *)pd->extra)->wdc0 =
-		    device_add(machine, tmpstr);
-	}
-
-	if (diskimage_exist(machine, 2, DISKIMAGE_IDE) ||
-	    diskimage_exist(machine, 3, DISKIMAGE_IDE)) {
-		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
-		    "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170),
-		    pd->pcibus->irq_path_isa, 15);
-		((struct symphony_82c105_extra *)pd->extra)->wdc1 =
-		    device_add(machine, tmpstr);
-	}
-
-	pd->cfg_reg_write = symphony_82c105_cfg_reg_write;
-}
-
-
-
-/*
- *  Realtek 8139C+ PCI ethernet.
- */
-
-#define PCI_VENDOR_REALTEK		0x10ec
-#define	PCI_PRODUCT_REALTEK_RT8139	0x8139
-
-PCIINIT(rtl8139c)
-{
-	uint64_t port, memaddr;
-	int pci_int_line = 0x101, irq = 0;
-	char irqstr[1000];
-	char tmpstr[2000];
-
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_REALTEK,
-	    PCI_PRODUCT_REALTEK_RT8139));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_NETWORK,
-	    PCI_SUBCLASS_NETWORK_ETHERNET, 0x00) + 0x20);
-
-	switch (machine->machine_type) {
-	case MACHINE_LANDISK:
-		irq = 5;
-		pci_int_line = 0x105;
-		break;
-	default:fatal("rtl8139c for this machine has not been "
-		    "implemented yet\n");
-		exit(1);
-	}
-
-	PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000 | pci_int_line);
-
-	allocate_device_space(pd, 0x100, 0, &port, &memaddr);
-
-	snprintf(irqstr, sizeof(irqstr), "%s.%i",
-	    pd->pcibus->irq_path_pci, irq);
-
-	snprintf(tmpstr, sizeof(tmpstr), "rtl8139c addr=0x%llx "
-	    "irq=%s pci_little_endian=1", (long long)port, irqstr);
-
-	device_add(machine, tmpstr);
-}
-
-
-
-/*
- *  DEC 21143 ("Tulip") PCI ethernet.
- */
-
-#define PCI_VENDOR_DEC          0x1011 /* Digital Equipment */
-#define PCI_PRODUCT_DEC_21142   0x0019 /* DECchip 21142/21143 10/100 Ethernet */
-
-PCIINIT(dec21143)
-{
-	uint64_t port, memaddr;
-	int pci_int_line = 0x101, irq = 0, isa = 0;
-	char irqstr[1000];
-	char tmpstr[2000];
-
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_DEC,
-	    PCI_PRODUCT_DEC_21142));
-
-	PCI_SET_DATA(PCI_COMMAND_STATUS_REG, 0x02000017);
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_NETWORK,
-	    PCI_SUBCLASS_NETWORK_ETHERNET, 0x00) + 0x41);
-
-	PCI_SET_DATA(PCI_BHLC_REG, PCI_BHLC_CODE(0,0,0, 0x40,0));
-
-	switch (machine->machine_type) {
-	case MACHINE_CATS:
-		/*  CATS int 18 = PCI.  */
-		irq = 18;
-		pci_int_line = 0x101;
-		break;
-	case MACHINE_COBALT:
-		/*  On Cobalt, IRQ 7 = PCI.  */
-		irq = 8 + 7;
-		pci_int_line = 0x407;
-		break;
-	case MACHINE_PREP:
-		irq = 10;
-		isa = 1;
-		pci_int_line = 0x20a;
-		break;
-	case MACHINE_MVMEPPC:
-		/*  TODO  */
-		irq = 10;
-		pci_int_line = 0x40a;
-		break;
-	case MACHINE_PMPPC:
-		/*  TODO, not working yet  */
-		irq = 31 - CPC_IB_EXT1;
-		pci_int_line = 0x101;
-		break;
-	case MACHINE_MACPPC:
-		/*  TODO, not working yet  */
-		irq = 25;
-		pci_int_line = 0x101;
-		break;
-	}
-
-	PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000 | pci_int_line);
-
-	allocate_device_space(pd, 0x100, 0x100, &port, &memaddr);
-
-	if (isa)
-		snprintf(irqstr, sizeof(irqstr), "%s.isa.%i",
-		    pd->pcibus->irq_path_isa, irq);
-	else
-		snprintf(irqstr, sizeof(irqstr), "%s.%i",
-		    pd->pcibus->irq_path_pci, irq);
-
-	snprintf(tmpstr, sizeof(tmpstr), "dec21143 addr=0x%llx addr2=0x%llx "
-	    "irq=%s pci_little_endian=1", (long long)port,
-	    (long long)memaddr, irqstr);
-
-	device_add(machine, tmpstr);
-}
-
-
-
-/*
- *  DEC 21030 "tga" graphics.
- */
-
-#define PCI_PRODUCT_DEC_21030  0x0004          /*  DECchip 21030 ("TGA")  */
-
-PCIINIT(dec21030)
-{
-	uint64_t base = 0;
-	char tmpstr[2000];
-
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_DEC,
-	    PCI_PRODUCT_DEC_21030));
-
-	PCI_SET_DATA(PCI_COMMAND_STATUS_REG, 0x02800087);  /*  TODO  */
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_DISPLAY,
-	    PCI_SUBCLASS_DISPLAY_VGA, 0x00) + 0x03);
-
-	/*
-	 *  See http://mail-index.netbsd.org/port-arc/2001/08/13/0000.html
-	 *  for more info.
-	 */
-
-	PCI_SET_DATA(PCI_BHLC_REG, 0x0000ff00);
-
-	/*  8 = prefetchable  */
-	PCI_SET_DATA(0x10, 0x00000008);
-	PCI_SET_DATA(0x30, 0x08000001);
-	PCI_SET_DATA(PCI_INTERRUPT_REG, 0x00000100);	/*  interrupt pin A?  */
-
-	/*
-	 *  Experimental:
-	 *
-	 *  TODO: Base address, pci_little_endian, ...
-	 */
-
-	switch (machine->machine_type) {
-	case MACHINE_ARC:
-		base = 0x100000000ULL;
-		break;
-	default:fatal("dec21030 in non-implemented machine type %i\n",
-		    machine->machine_type);
-		exit(1);
-	}
-
-	snprintf(tmpstr, sizeof(tmpstr), "dec21030 addr=0x%llx",
-	    (long long)(base));
-	device_add(machine, tmpstr);
-}
-
-
-
-/*
- *  Motorola MPC105 "Eagle" Host Bridge
- *
- *  Used in at least PReP and BeBox.
- */
-
-#define	PCI_VENDOR_MOT			0x1057
-#define	PCI_PRODUCT_MOT_MPC105		0x0001
-
-PCIINIT(eagle)
-{
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_MOT,
-	    PCI_PRODUCT_MOT_MPC105));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x24);
-
-	PCI_SET_DATA(PCI_BHLC_REG,
-	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
-}
-
-
-
-/*
- *  Apple (MacPPC) stuff:
- *
- *  Grand Central (I/O controller)
- *  Uni-North (PCI controller)
- */
-
-#define	PCI_VENDOR_APPLE		0x106b
-#define	PCI_PRODUCT_APPLE_GC		0x0002
-#define	PCI_PRODUCT_APPLE_UNINORTH1	0x001e
-
-PCIINIT(gc_obio)
-{
-	uint64_t port, memaddr;
-
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_APPLE,
-	    PCI_PRODUCT_APPLE_GC));
-
-	/*  TODO:  */
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_SYSTEM,
-	    PCI_SUBCLASS_SYSTEM_PIC, 0) + 0x00);
-
-	PCI_SET_DATA(PCI_BHLC_REG,
-	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
-
-	/*  TODO  */
-	allocate_device_space(pd, 0x10000, 0x10000, &port, &memaddr);
-}
-
-PCIINIT(uninorth)
-{
-	uint64_t port, memaddr;
-
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_APPLE,
-	    PCI_PRODUCT_APPLE_UNINORTH1));
-
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_HOST, 0) + 0xff);
-
-	PCI_SET_DATA(PCI_BHLC_REG,
-	    PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
-
-	/*  TODO  */
-	allocate_device_space(pd, 0x10000, 0x10000, &port, &memaddr);
-}
-
-
-
-/*
- *  ATI graphics cards
- */
-
-#define	PCI_VENDOR_ATI			0x1002
-#define	PCI_PRODUCT_ATI_RADEON_9200_2	0x5962
-
-PCIINIT(ati_radeon_9200_2)
-{
-	uint64_t port, memaddr;
-
-	PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_ATI,
-	    PCI_PRODUCT_ATI_RADEON_9200_2));
-
-	/*  TODO: other subclass?  */
-	PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_DISPLAY,
-	    PCI_SUBCLASS_DISPLAY_VGA, 0) + 0x03);
-
-	/*  TODO  */
-	allocate_device_space(pd, 0x1000, 0x400000, &port, &memaddr);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_8253.c gxemul-0.7.0+dfsg/src/devices/dev_8253.c
--- gxemul-0.6.2/src/devices/dev_8253.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_8253.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,259 @@
+/*
+ *  Copyright (C) 2005-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Intel 8253/8254 Programmable Interval Timer
+ *
+ *  TODO/NOTE:
+ *	The timers don't really count down. Timer 0 causes clock interrupts
+ *	at a specific frequency, but reading the counter register would not
+ *	result in anything meaningful.
+ *
+ *  (Split counter[] into reset value and current value.)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "timer.h"
+
+#include "thirdparty/i8253reg.h"
+
+
+/*  #define debug fatal  */
+
+#define	DEV_8253_LENGTH		4
+#define	TICK_SHIFT		14
+
+
+struct pit8253_data {
+	int		in_use;
+
+	int		counter_select;
+	uint8_t		mode_byte;
+
+	int		mode[3];
+	int		counter[3];
+
+	int		hz[3];
+
+	struct timer	*timer0;
+	struct interrupt irq;
+	int		pending_interrupts_timer0;
+};
+
+
+static void timer0_tick(struct timer *t, void *extra)
+{
+	struct pit8253_data *d = (struct pit8253_data *) extra;
+	d->pending_interrupts_timer0 ++;
+
+	/*  printf("%i ", d->pending_interrupts_timer0); fflush(stdout);  */
+}
+
+
+DEVICE_TICK(8253)
+{
+	struct pit8253_data *d = (struct pit8253_data *) extra;
+
+	if (!d->in_use)
+		return;
+
+	// Generate interrupts regardless of (d->mode[0] & 0x0e)?
+	// (It seems like Linux/MALTA kernels like this.)
+	if (d->pending_interrupts_timer0 > 0)
+		INTERRUPT_ASSERT(d->irq);
+}
+
+
+DEVICE_ACCESS(8253)
+{
+	struct pit8253_data *d = (struct pit8253_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	d->in_use = 1;
+
+	switch (relative_addr) {
+
+	case I8253_TIMER_CNTR0:
+	case I8253_TIMER_CNTR1:
+	case I8253_TIMER_CNTR2:
+		if (writeflag == MEM_WRITE) {
+			switch (d->mode_byte & 0x30) {
+			case I8253_TIMER_LSB:
+			case I8253_TIMER_16BIT:
+				d->counter[relative_addr] &= 0xff00;
+				d->counter[relative_addr] |= (idata & 0xff);
+				break;
+			case I8253_TIMER_MSB:
+				d->counter[relative_addr] &= 0x00ff;
+				d->counter[relative_addr] |= ((idata&0xff)<<8);
+				if (d->counter[relative_addr] != 0)
+					d->hz[relative_addr] = (int) (
+					    I8253_TIMER_FREQ / (float)
+					    d->counter[relative_addr] + 0.5);
+				else
+					d->hz[relative_addr] = 0;
+				debug("[ 8253: counter %i set to %i (%i Hz) "
+				    "]\n", relative_addr, d->counter[
+				    relative_addr], d->hz[relative_addr]);
+				switch (relative_addr) {
+				case 0:	if (d->timer0 == NULL)
+						d->timer0 = timer_add(
+						    d->hz[0], timer0_tick, d);
+					else
+						timer_update_frequency(
+						    d->timer0, d->hz[0]);
+					break;
+				case 1:	fatal("TODO: DMA refresh?\n");
+					exit(1);
+				case 2:	fatal("TODO: 8253 tone generation?\n");
+					break;
+				}
+				break;
+			default:fatal("[ 8253: huh? writing to counter"
+				    " %i but neither from msb nor lsb? ]\n",
+				    relative_addr);
+				exit(1);
+			}
+		} else {
+			switch (d->mode_byte & 0x30) {
+			case I8253_TIMER_LSB:
+			case I8253_TIMER_16BIT:
+				odata = d->counter[relative_addr] & 0xff;
+				break;
+			case I8253_TIMER_MSB:
+				odata = (d->counter[relative_addr] >> 8) & 0xff;
+				break;
+			default:fatal("[ 8253: huh? reading from counter"
+				    " %i but neither from msb nor lsb? ]\n",
+				    relative_addr);
+				exit(1);
+			}
+		}
+
+		/*  Switch from LSB to MSB, if accessing as 16-bit word:  */
+		if ((d->mode_byte & 0x30) == I8253_TIMER_16BIT)
+			d->mode_byte &= ~I8253_TIMER_LSB;
+
+		break;
+
+	case I8253_TIMER_MODE:
+		if (writeflag == MEM_WRITE) {
+			d->mode_byte = idata;
+
+			d->counter_select = idata >> 6;
+			if (d->counter_select > 2) {
+				debug("[ 8253: attempt to select counter 3,"
+				    " which doesn't exist. ]\n");
+				d->counter_select = 0;
+			}
+
+			d->mode[d->counter_select] = idata & 0x0e;
+
+			debug("[ 8253: select=%i mode=0x%x ",
+			    d->counter_select, d->mode[d->counter_select]);
+			if (idata & 0x30) {
+				switch (idata & 0x30) {
+				case I8253_TIMER_LSB:
+					debug("LSB ");
+					break;
+				case I8253_TIMER_16BIT:
+					debug("LSB+");
+					// fall through
+				case I8253_TIMER_MSB:
+					debug("MSB ");
+				}
+			}
+			debug("]\n");
+
+			if (idata & I8253_TIMER_BCD) {
+				fatal("[ 8253: BCD not yet implemented ]\n");
+				exit(1);
+			}
+		} else {
+			debug("[ 8253: read; can this actually happen? ]\n");
+			odata = d->mode_byte;
+		}
+		break;
+
+	default:if (writeflag == MEM_WRITE) {
+			fatal("[ 8253: unimplemented write to address 0x%x"
+			    " data=0x%02x ]\n", (int)relative_addr, (int)idata);
+		} else {
+			fatal("[ 8253: unimplemented read from address 0x%x "
+			    "]\n", (int)relative_addr);
+		}
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(8253)
+{
+	struct pit8253_data *d;
+
+	CHECK_ALLOCATION(d = (struct pit8253_data *) malloc(sizeof(struct pit8253_data)));
+	memset(d, 0, sizeof(struct pit8253_data));
+
+	d->in_use = devinit->in_use;
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	/*  Don't cause interrupt, by default.  */
+	d->mode[0] = I8253_TIMER_RATEGEN;
+	d->mode[1] = I8253_TIMER_RATEGEN;
+	d->mode[2] = I8253_TIMER_RATEGEN;
+
+	devinit->machine->isa_pic_data.pending_timer_interrupts =
+	    &d->pending_interrupts_timer0;
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_8253_LENGTH, dev_8253_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(devinit->machine, dev_8253_tick,
+	    d, TICK_SHIFT);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_8253.cc gxemul-0.7.0+dfsg/src/devices/dev_8253.cc
--- gxemul-0.6.2/src/devices/dev_8253.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_8253.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,258 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Intel 8253/8254 Programmable Interval Timer
- *
- *  TODO/NOTE:
- *	The timers don't really count down. Timer 0 causes clock interrupts
- *	at a specific frequency, but reading the counter register would not
- *	result in anything meaningful.
- *
- *  (Split counter[] into reset value and current value.)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "timer.h"
-
-#include "thirdparty/i8253reg.h"
-
-
-/*  #define debug fatal  */
-
-#define	DEV_8253_LENGTH		4
-#define	TICK_SHIFT		14
-
-
-struct pit8253_data {
-	int		in_use;
-
-	int		counter_select;
-	uint8_t		mode_byte;
-
-	int		mode[3];
-	int		counter[3];
-
-	int		hz[3];
-
-	struct timer	*timer0;
-	struct interrupt irq;
-	int		pending_interrupts_timer0;
-};
-
-
-static void timer0_tick(struct timer *t, void *extra)
-{
-	struct pit8253_data *d = (struct pit8253_data *) extra;
-	d->pending_interrupts_timer0 ++;
-
-	/*  printf("%i ", d->pending_interrupts_timer0); fflush(stdout);  */
-}
-
-
-DEVICE_TICK(8253)
-{
-	struct pit8253_data *d = (struct pit8253_data *) extra;
-
-	if (!d->in_use)
-		return;
-
-	// Generate interrupts regardless of (d->mode[0] & 0x0e)?
-	// (It seems like Linux/MALTA kernels like this.)
-	if (d->pending_interrupts_timer0 > 0)
-		INTERRUPT_ASSERT(d->irq);
-}
-
-
-DEVICE_ACCESS(8253)
-{
-	struct pit8253_data *d = (struct pit8253_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	d->in_use = 1;
-
-	switch (relative_addr) {
-
-	case I8253_TIMER_CNTR0:
-	case I8253_TIMER_CNTR1:
-	case I8253_TIMER_CNTR2:
-		if (writeflag == MEM_WRITE) {
-			switch (d->mode_byte & 0x30) {
-			case I8253_TIMER_LSB:
-			case I8253_TIMER_16BIT:
-				d->counter[relative_addr] &= 0xff00;
-				d->counter[relative_addr] |= (idata & 0xff);
-				break;
-			case I8253_TIMER_MSB:
-				d->counter[relative_addr] &= 0x00ff;
-				d->counter[relative_addr] |= ((idata&0xff)<<8);
-				if (d->counter[relative_addr] != 0)
-					d->hz[relative_addr] = (int) (
-					    I8253_TIMER_FREQ / (float)
-					    d->counter[relative_addr] + 0.5);
-				else
-					d->hz[relative_addr] = 0;
-				debug("[ 8253: counter %i set to %i (%i Hz) "
-				    "]\n", relative_addr, d->counter[
-				    relative_addr], d->hz[relative_addr]);
-				switch (relative_addr) {
-				case 0:	if (d->timer0 == NULL)
-						d->timer0 = timer_add(
-						    d->hz[0], timer0_tick, d);
-					else
-						timer_update_frequency(
-						    d->timer0, d->hz[0]);
-					break;
-				case 1:	fatal("TODO: DMA refresh?\n");
-					exit(1);
-				case 2:	fatal("TODO: 8253 tone generation?\n");
-					break;
-				}
-				break;
-			default:fatal("[ 8253: huh? writing to counter"
-				    " %i but neither from msb nor lsb? ]\n",
-				    relative_addr);
-				exit(1);
-			}
-		} else {
-			switch (d->mode_byte & 0x30) {
-			case I8253_TIMER_LSB:
-			case I8253_TIMER_16BIT:
-				odata = d->counter[relative_addr] & 0xff;
-				break;
-			case I8253_TIMER_MSB:
-				odata = (d->counter[relative_addr] >> 8) & 0xff;
-				break;
-			default:fatal("[ 8253: huh? reading from counter"
-				    " %i but neither from msb nor lsb? ]\n",
-				    relative_addr);
-				exit(1);
-			}
-		}
-
-		/*  Switch from LSB to MSB, if accessing as 16-bit word:  */
-		if ((d->mode_byte & 0x30) == I8253_TIMER_16BIT)
-			d->mode_byte &= ~I8253_TIMER_LSB;
-
-		break;
-
-	case I8253_TIMER_MODE:
-		if (writeflag == MEM_WRITE) {
-			d->mode_byte = idata;
-
-			d->counter_select = idata >> 6;
-			if (d->counter_select > 2) {
-				debug("[ 8253: attempt to select counter 3,"
-				    " which doesn't exist. ]\n");
-				d->counter_select = 0;
-			}
-
-			d->mode[d->counter_select] = idata & 0x0e;
-
-			debug("[ 8253: select=%i mode=0x%x ",
-			    d->counter_select, d->mode[d->counter_select]);
-			if (idata & 0x30) {
-				switch (idata & 0x30) {
-				case I8253_TIMER_LSB:
-					debug("LSB ");
-					break;
-				case I8253_TIMER_16BIT:
-					debug("LSB+");
-				case I8253_TIMER_MSB:
-					debug("MSB ");
-				}
-			}
-			debug("]\n");
-
-			if (idata & I8253_TIMER_BCD) {
-				fatal("[ 8253: BCD not yet implemented ]\n");
-				exit(1);
-			}
-		} else {
-			debug("[ 8253: read; can this actually happen? ]\n");
-			odata = d->mode_byte;
-		}
-		break;
-
-	default:if (writeflag == MEM_WRITE) {
-			fatal("[ 8253: unimplemented write to address 0x%x"
-			    " data=0x%02x ]\n", (int)relative_addr, (int)idata);
-		} else {
-			fatal("[ 8253: unimplemented read from address 0x%x "
-			    "]\n", (int)relative_addr);
-		}
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(8253)
-{
-	struct pit8253_data *d;
-
-	CHECK_ALLOCATION(d = (struct pit8253_data *) malloc(sizeof(struct pit8253_data)));
-	memset(d, 0, sizeof(struct pit8253_data));
-
-	d->in_use = devinit->in_use;
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	/*  Don't cause interrupt, by default.  */
-	d->mode[0] = I8253_TIMER_RATEGEN;
-	d->mode[1] = I8253_TIMER_RATEGEN;
-	d->mode[2] = I8253_TIMER_RATEGEN;
-
-	devinit->machine->isa_pic_data.pending_timer_interrupts =
-	    &d->pending_interrupts_timer0;
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_8253_LENGTH, dev_8253_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(devinit->machine, dev_8253_tick,
-	    d, TICK_SHIFT);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_8259.c gxemul-0.7.0+dfsg/src/devices/dev_8259.c
--- gxemul-0.6.2/src/devices/dev_8259.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_8259.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,284 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Intel 8259 Programmable Interrupt Controller
+ *
+ *  See the following URL for more details:
+ *	http://www.nondot.org/sabre/os/files/MiscHW/8259pic.txt
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	DEV_8259_LENGTH		2
+
+/*  #define DEV_8259_DEBUG  */
+
+
+DEVICE_ACCESS(8259)
+{
+	struct pic8259_data *d = (struct pic8259_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int i;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+#ifdef DEV_8259_DEBUG
+	if (writeflag == MEM_READ)
+		fatal("[ 8259: read from 0x%x ]\n", (int)relative_addr);
+	else
+		fatal("[ 8259: write to 0x%x: 0x%x ]\n",
+		    (int)relative_addr, (int)idata);
+#endif
+
+	switch (relative_addr) {
+	case 0x00:
+		if (writeflag == MEM_WRITE) {
+			if ((idata & 0x10) == 0x10) {
+				/*  Bit 3: 0=edge, 1=level  */
+				if (idata & 0x08)
+					fatal("[ 8259: TODO: Level "
+					    "triggered (MCA bus) ]\n");
+				if (idata & 0x04)
+					fatal("[ 8259: WARNING: Bit 2 set ]\n");
+				/*  Bit 1: 0=cascade, 1=single  */
+				/*  Bit 0: 1=4th init byte  */
+				/*  This happens on non-x86 systems:
+				    if (!(idata & 0x01))
+					fatal("[ 8259: WARNING: Bit 0 NOT set!"
+					    "!! ]\n");  */
+				d->init_state = 1;
+				break;
+			}
+
+			/*  TODO: Is it ok to abort init state when there
+			    is a non-init command?  */
+			if (d->init_state)
+				fatal("[ 8259: WARNING: Was in init-state, but"
+				    " it was aborted? ]\n");
+			d->init_state = 0;
+
+			if (idata == 0x0a) {
+				d->current_command = 0x0a;
+			} else if (idata == 0x0b) {
+				d->current_command = 0x0b;
+			} else if (idata == 0x0c) {
+				/*  Put Master in Buffered Mode  */
+				d->current_command = 0x0c;
+			} else if (idata == 0x20) {
+				int old_irr = d->irr;
+				/*  End Of Interrupt  */
+				/*  TODO: in buffered mode, is this an EOI 0? */
+				d->irr &= ~d->isr;
+				d->isr = 0;
+				/*  Recalculate interrupt assertions,
+				    if necessary:  */
+				if ((old_irr & ~d->ier) != (d->irr & ~d->ier)) {
+					if (d->irr & ~d->ier)
+						INTERRUPT_ASSERT(d->irq);
+					else
+						INTERRUPT_DEASSERT(d->irq);
+				}
+			} else if ((idata >= 0x21 && idata <= 0x27) ||
+			    (idata >= 0x60 && idata <= 0x67) ||
+			    (idata >= 0xe0 && idata <= 0xe7)) {
+				/*  Specific EOI  */
+				int old_irr = d->irr;
+				d->irr &= ~(1 << (idata & 7));
+				d->isr &= ~(1 << (idata & 7));
+				/*  Recalc. int assertions, if necessary:  */
+				if ((old_irr & ~d->ier) != (d->irr & ~d->ier)) {
+					if (d->irr & ~d->ier)
+						INTERRUPT_ASSERT(d->irq);
+					else
+						INTERRUPT_DEASSERT(d->irq);
+				}
+			} else if (idata == 0x68) {
+				/*  Set Special Mask Mode  */
+				/*  TODO  */
+			} else if (idata >= 0xc0 && idata <= 0xc7) {
+				/*  Set IRQ Priority Order  */
+				/*  TODO  */
+			} else {
+				fatal("[ 8259: unimplemented command 0x%02x"
+				    " ]\n", (int)idata);
+				cpu->running = 0;
+			}
+		} else {
+			switch (d->current_command) {
+			case 0x0a:
+				odata = d->irr;
+				break;
+			case 0x0b:
+				odata = d->isr;
+				break;
+			case 0x0c:
+				/*  Buffered mode.  */
+				odata = 0x00;
+				for (i=0; i<8; i++)
+					if ((d->irr >> i) & 1) {
+						odata = 0x80 | i;
+						break;
+					}
+				break;
+			default:
+				odata = 0x00;
+				for (i=0; i<8; i++)
+					if ((d->irr >> i) & 1) {
+						odata = 0x80 | i;
+						break;
+					}
+				break;
+			/*
+			 *  TODO: The "default" label should really do
+			 *  something like this:
+			 *
+			 *	fatal("[ 8259: unimplemented command 0x%02x"
+			 *	    " while reading ]\n", d->current_command);
+			 *	cpu->running = 0;
+			 *
+			 *  but Linux seems to read from the secondary PIC
+			 *  in a manner which works better the way things
+			 *  are coded right now.
+			 */
+			}
+		}
+		break;
+	case 0x01:
+		if (d->init_state > 0) {
+			if (d->init_state == 1) {
+				d->irq_base = idata & 0xf8;
+				/*  This happens on non-x86 machines:
+				    if (idata & 7)
+					fatal("[ 8259: WARNING! Lowest"
+					    " bits in Init Cmd 1 are"
+					    " non-zero! ]\n");  */
+				d->init_state = 2;
+			} else if (d->init_state == 2) {
+				/*  Slave attachment. TODO  */
+				d->init_state = 3;
+			} else if (d->init_state == 3) {
+				if (idata & 0x02) {
+					/*  Should not be set in PCs, but
+					    on CATS, for example, it is set.  */
+					debug("[ 8259: WARNING! Bit 1 i"
+					    "n Init Cmd 4 is set! ]\n");
+				}
+				if (!(idata & 0x01))
+					fatal("[ 8259: WARNING! Bit 0 "
+					    "in Init Cmd 4 is not"
+					    " set! ]\n");
+				d->init_state = 0;
+			}
+			break;
+		}
+
+		if (writeflag == MEM_WRITE) {
+			int old_ier = d->ier;
+			d->ier = idata;
+
+			/*  Recalculate interrupt assertions,
+			    if necessary:  */
+			if ((d->irr & ~old_ier) != (d->irr & ~d->ier)) {
+				if (d->irr & ~d->ier)
+					INTERRUPT_ASSERT(d->irq);
+				else
+					INTERRUPT_DEASSERT(d->irq);
+			}
+		} else {
+			odata = d->ier;
+		}
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ 8259: unimplemented write to address 0x%x"
+			    " data=0x%02x ]\n", (int)relative_addr, (int)idata);
+			cpu->running = 0;
+		} else {
+			fatal("[ 8259: unimplemented read from address 0x%x "
+			    "]\n", (int)relative_addr);
+			cpu->running = 0;
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  devinit_8259():
+ *
+ *  Initialize an 8259 PIC. Important notes:
+ *
+ *	x)  Most systems use _TWO_ 8259 PICs. These should be registered
+ *	    as separate devices.
+ *
+ *	x)  The irq number specified is the number used to re-calculate
+ *	    CPU interrupt assertions.  It is _not_ the irq number at
+ *	    which the PIC is connected. (That is left to machine specific
+ *	    code in src/machine.c.)
+ */
+DEVINIT(8259)
+{
+	struct pic8259_data *d;
+	char *name2;
+	size_t nlen = strlen(devinit->name) + 20;
+
+	CHECK_ALLOCATION(d = (struct pic8259_data *) malloc(sizeof(struct pic8259_data)));
+	memset(d, 0, sizeof(struct pic8259_data));
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
+	snprintf(name2, nlen, "%s", devinit->name);
+	if ((devinit->addr & 0xfff) == 0xa0) {
+		strlcat(name2, " [secondary]", nlen);
+		d->irq_base = 8;
+	}
+
+	memory_device_register(devinit->machine->memory, name2,
+	    devinit->addr, DEV_8259_LENGTH, dev_8259_access, d,
+	    DM_DEFAULT, NULL);
+
+	devinit->return_ptr = d;
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_8259.cc gxemul-0.7.0+dfsg/src/devices/dev_8259.cc
--- gxemul-0.6.2/src/devices/dev_8259.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_8259.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,284 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Intel 8259 Programmable Interrupt Controller
- *
- *  See the following URL for more details:
- *	http://www.nondot.org/sabre/os/files/MiscHW/8259pic.txt
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define	DEV_8259_LENGTH		2
-
-/*  #define DEV_8259_DEBUG  */
-
-
-DEVICE_ACCESS(8259)
-{
-	struct pic8259_data *d = (struct pic8259_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int i;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-#ifdef DEV_8259_DEBUG
-	if (writeflag == MEM_READ)
-		fatal("[ 8259: read from 0x%x ]\n", (int)relative_addr);
-	else
-		fatal("[ 8259: write to 0x%x: 0x%x ]\n",
-		    (int)relative_addr, (int)idata);
-#endif
-
-	switch (relative_addr) {
-	case 0x00:
-		if (writeflag == MEM_WRITE) {
-			if ((idata & 0x10) == 0x10) {
-				/*  Bit 3: 0=edge, 1=level  */
-				if (idata & 0x08)
-					fatal("[ 8259: TODO: Level "
-					    "triggered (MCA bus) ]\n");
-				if (idata & 0x04)
-					fatal("[ 8259: WARNING: Bit 2 set ]\n");
-				/*  Bit 1: 0=cascade, 1=single  */
-				/*  Bit 0: 1=4th init byte  */
-				/*  This happens on non-x86 systems:
-				    if (!(idata & 0x01))
-					fatal("[ 8259: WARNING: Bit 0 NOT set!"
-					    "!! ]\n");  */
-				d->init_state = 1;
-				break;
-			}
-
-			/*  TODO: Is it ok to abort init state when there
-			    is a non-init command?  */
-			if (d->init_state)
-				fatal("[ 8259: WARNING: Was in init-state, but"
-				    " it was aborted? ]\n");
-			d->init_state = 0;
-
-			if (idata == 0x0a) {
-				d->current_command = 0x0a;
-			} else if (idata == 0x0b) {
-				d->current_command = 0x0b;
-			} else if (idata == 0x0c) {
-				/*  Put Master in Buffered Mode  */
-				d->current_command = 0x0c;
-			} else if (idata == 0x20) {
-				int old_irr = d->irr;
-				/*  End Of Interrupt  */
-				/*  TODO: in buffered mode, is this an EOI 0? */
-				d->irr &= ~d->isr;
-				d->isr = 0;
-				/*  Recalculate interrupt assertions,
-				    if necessary:  */
-				if ((old_irr & ~d->ier) != (d->irr & ~d->ier)) {
-					if (d->irr & ~d->ier)
-						INTERRUPT_ASSERT(d->irq);
-					else
-						INTERRUPT_DEASSERT(d->irq);
-				}
-			} else if ((idata >= 0x21 && idata <= 0x27) ||
-			    (idata >= 0x60 && idata <= 0x67) ||
-			    (idata >= 0xe0 && idata <= 0xe7)) {
-				/*  Specific EOI  */
-				int old_irr = d->irr;
-				d->irr &= ~(1 << (idata & 7));
-				d->isr &= ~(1 << (idata & 7));
-				/*  Recalc. int assertions, if necessary:  */
-				if ((old_irr & ~d->ier) != (d->irr & ~d->ier)) {
-					if (d->irr & ~d->ier)
-						INTERRUPT_ASSERT(d->irq);
-					else
-						INTERRUPT_DEASSERT(d->irq);
-				}
-			} else if (idata == 0x68) {
-				/*  Set Special Mask Mode  */
-				/*  TODO  */
-			} else if (idata >= 0xc0 && idata <= 0xc7) {
-				/*  Set IRQ Priority Order  */
-				/*  TODO  */
-			} else {
-				fatal("[ 8259: unimplemented command 0x%02x"
-				    " ]\n", (int)idata);
-				cpu->running = 0;
-			}
-		} else {
-			switch (d->current_command) {
-			case 0x0a:
-				odata = d->irr;
-				break;
-			case 0x0b:
-				odata = d->isr;
-				break;
-			case 0x0c:
-				/*  Buffered mode.  */
-				odata = 0x00;
-				for (i=0; i<8; i++)
-					if ((d->irr >> i) & 1) {
-						odata = 0x80 | i;
-						break;
-					}
-				break;
-			default:
-				odata = 0x00;
-				for (i=0; i<8; i++)
-					if ((d->irr >> i) & 1) {
-						odata = 0x80 | i;
-						break;
-					}
-				break;
-			/*
-			 *  TODO: The "default" label should really do
-			 *  something like this:
-			 *
-			 *	fatal("[ 8259: unimplemented command 0x%02x"
-			 *	    " while reading ]\n", d->current_command);
-			 *	cpu->running = 0;
-			 *
-			 *  but Linux seems to read from the secondary PIC
-			 *  in a manner which works better the way things
-			 *  are coded right now.
-			 */
-			}
-		}
-		break;
-	case 0x01:
-		if (d->init_state > 0) {
-			if (d->init_state == 1) {
-				d->irq_base = idata & 0xf8;
-				/*  This happens on non-x86 machines:
-				    if (idata & 7)
-					fatal("[ 8259: WARNING! Lowest"
-					    " bits in Init Cmd 1 are"
-					    " non-zero! ]\n");  */
-				d->init_state = 2;
-			} else if (d->init_state == 2) {
-				/*  Slave attachment. TODO  */
-				d->init_state = 3;
-			} else if (d->init_state == 3) {
-				if (idata & 0x02) {
-					/*  Should not be set in PCs, but
-					    on CATS, for example, it is set.  */
-					debug("[ 8259: WARNING! Bit 1 i"
-					    "n Init Cmd 4 is set! ]\n");
-				}
-				if (!(idata & 0x01))
-					fatal("[ 8259: WARNING! Bit 0 "
-					    "in Init Cmd 4 is not"
-					    " set! ]\n");
-				d->init_state = 0;
-			}
-			break;
-		}
-
-		if (writeflag == MEM_WRITE) {
-			int old_ier = d->ier;
-			d->ier = idata;
-
-			/*  Recalculate interrupt assertions,
-			    if necessary:  */
-			if ((d->irr & ~old_ier) != (d->irr & ~d->ier)) {
-				if (d->irr & ~d->ier)
-					INTERRUPT_ASSERT(d->irq);
-				else
-					INTERRUPT_DEASSERT(d->irq);
-			}
-		} else {
-			odata = d->ier;
-		}
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ 8259: unimplemented write to address 0x%x"
-			    " data=0x%02x ]\n", (int)relative_addr, (int)idata);
-			cpu->running = 0;
-		} else {
-			fatal("[ 8259: unimplemented read from address 0x%x "
-			    "]\n", (int)relative_addr);
-			cpu->running = 0;
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  devinit_8259():
- *
- *  Initialize an 8259 PIC. Important notes:
- *
- *	x)  Most systems use _TWO_ 8259 PICs. These should be registered
- *	    as separate devices.
- *
- *	x)  The irq number specified is the number used to re-calculate
- *	    CPU interrupt assertions.  It is _not_ the irq number at
- *	    which the PIC is connected. (That is left to machine specific
- *	    code in src/machine.c.)
- */
-DEVINIT(8259)
-{
-	struct pic8259_data *d;
-	char *name2;
-	size_t nlen = strlen(devinit->name) + 20;
-
-	CHECK_ALLOCATION(d = (struct pic8259_data *) malloc(sizeof(struct pic8259_data)));
-	memset(d, 0, sizeof(struct pic8259_data));
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
-	snprintf(name2, nlen, "%s", devinit->name);
-	if ((devinit->addr & 0xfff) == 0xa0) {
-		strlcat(name2, " [secondary]", nlen);
-		d->irq_base = 8;
-	}
-
-	memory_device_register(devinit->machine->memory, name2,
-	    devinit->addr, DEV_8259_LENGTH, dev_8259_access, d,
-	    DM_DEFAULT, NULL);
-
-	devinit->return_ptr = d;
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_adb.c gxemul-0.7.0+dfsg/src/devices/dev_adb.c
--- gxemul-0.6.2/src/devices/dev_adb.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_adb.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,455 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Apple Desktop Bus (ADB) controller
+ *
+ *  Based on intuition from reverse-engineering NetBSD/macppc source code,
+ *  so it probably only works with that OS.
+ *
+ *  The comment "OK" means that 100% of the functionality used by NetBSD/macppc
+ *  is covered.
+ *
+ *  TODO:
+ *	o)  Clean up, don't hardcode values.
+ *	o)  Convert into a separate controller, bus, device architecture.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/adb_viareg.h"
+
+
+#define debug fatal
+/*  #define ADB_DEBUG  */
+
+
+#define	TICK_SHIFT		17
+#define	DEV_ADB_LENGTH		0x2000
+
+#define	N_VIA_REGS		0x10
+#define	VIA_REG_SHIFT		9
+
+#define	MAX_BUF			100
+
+
+static const char *via_regname[N_VIA_REGS] = {
+	"vBufB", "vBufA", "vDirB", "vDirA",
+	"vT1C",  "vT1CH", "vT1L",  "vT1LH",
+	"vT2C",  "vT2CH", "vSR",   "vACR",
+	"vPCR",  "vIFR",  "vIER",  "(unknown)" };
+
+struct adb_data {
+	struct interrupt irq;
+	int		int_asserted;
+
+	int		kbd_dev;
+
+	long long	transfer_nr;
+
+	uint8_t		reg[N_VIA_REGS];
+
+	int		cur_output_offset;
+	uint8_t		output_buf[MAX_BUF];
+
+	int		cur_input_offset;
+	int		cur_input_length;
+	uint8_t		input_buf[MAX_BUF];
+
+	int		dir;
+	int		int_enable;
+	int		ack;		/*  last ack state  */
+	int		tip;		/*  transfer in progress  */
+};
+
+#define	DIR_INPUT		0
+#define	DIR_OUTPUT		1
+
+#define	BUFB_nINTR		0x08
+#define	BUFB_ACK		0x10
+#define	BUFB_nTIP		0x20
+#define	IFR_SR			0x04
+#define	IFR_ANY			0x80
+#define	ACR_SR_OUT		0x10
+
+
+
+DEVICE_TICK(adb)
+{
+	struct adb_data *d = (struct adb_data *) extra;
+	int assert;
+
+	assert = d->reg[vIFR >> VIA_REG_SHIFT] & IFR_ANY;
+	if (assert == IFR_ANY && d->int_enable)
+		assert = 1;
+
+	if (assert)
+		INTERRUPT_ASSERT(d->irq);
+	else if (d->int_asserted)
+		INTERRUPT_DEASSERT(d->irq);
+
+	d->int_asserted = assert;
+}
+
+
+/*
+ *  adb_reset():
+ *
+ *  Reset registers to default values.
+ */
+static void adb_reset(struct adb_data *d)
+{
+	d->kbd_dev = 2;
+
+	memset(d->reg, 0, sizeof(d->reg));
+	d->reg[vBufB >> VIA_REG_SHIFT] = BUFB_nINTR | BUFB_nTIP;
+
+	d->cur_output_offset = 0;
+	memset(d->output_buf, 0, sizeof(d->output_buf));
+
+	d->dir = 0;
+	d->int_enable = 0;
+	d->ack = 0;
+	d->tip = 0;
+}
+
+
+/*
+ *  adb_process_cmd():
+ *
+ *  This function should be called whenever a complete ADB command has been
+ *  received.
+ */
+static void adb_process_cmd(struct cpu *cpu, struct adb_data *d)
+{
+	int i, reg, dev;
+
+	debug("[ adb: COMMAND:");
+	for (i=0; i<d->cur_output_offset; i++)
+		debug(" %02x", d->output_buf[i]);
+	debug(" ]\n");
+
+	if (d->cur_output_offset < 2) {
+		fatal("[ adb: WEIRD output length: %i ]\n",
+		    d->cur_output_offset);
+		exit(1);
+	}
+
+	switch (d->output_buf[0]) {
+
+	case 0:	/*  ADB commands:  */
+		if (d->output_buf[1] == 0x00) {
+			/*  Reset.  */
+			return;
+		}
+		if ((d->output_buf[1] & 0x0c) == 0x0c) {
+			/*  ADBTALK:  */
+			reg = d->output_buf[1] & 3;
+			dev = d->output_buf[1] >> 4;
+			fatal("dev=%i reg=%i\n", dev, reg);
+			/*  Default values: nothing here  */
+			d->input_buf[0] = 0x00;
+			d->input_buf[1] = 0x00;
+			d->input_buf[2] = d->output_buf[1];
+			d->cur_input_length = 3;
+			if (dev == d->kbd_dev) {
+				/*  Keyboard.  */
+				d->input_buf[0] = 0x01;
+				d->input_buf[1] = 0x01;
+				d->input_buf[2] = d->output_buf[1];
+				d->input_buf[3] = 0x01;
+				d->input_buf[4] = 0x01;
+				d->cur_input_length = 5;
+			}
+		} else if ((d->output_buf[1] & 0x0c) == 0x08) {
+			int new_dev_pos = d->output_buf[2] & 15;
+			/*  ADBLISTEN:  */
+			if ((d->output_buf[1] >> 4) != d->kbd_dev) {
+				fatal("[ adb: ADBLISTEN not to kbd ]\n");
+				exit(1);
+			}
+			if (d->output_buf[3] != 0xfe ||
+			    (d->output_buf[2] & 0xf0) != 0x60) {
+				fatal("[ adb: unknown ADBLISTEN ]\n");
+				exit(1);
+			}
+			/*  Move device.  */
+			d->kbd_dev = new_dev_pos;
+		} else {
+			fatal("[ adb: unknown ADB command? ]\n");
+			exit(1);
+		}
+		break;
+
+	case 1:	/*  PRAM/RTC:  */
+		if (d->cur_output_offset == 3 &&
+		    d->output_buf[1] == 0x01 &&
+		    d->output_buf[2] == 0x01) {
+			/*  Autopoll:  */
+			d->input_buf[0] = 0x00;
+			d->input_buf[1] = 0x00;
+			d->input_buf[2] = d->output_buf[1];
+			d->cur_input_length = 3;
+		} else if (d->cur_output_offset == 2 &&
+		    d->output_buf[1] == 0x03) {
+			/*  Read RTC date/time:  */
+			struct timeval tv;
+			gettimeofday(&tv, NULL);
+			d->input_buf[0] = tv.tv_sec >> 24;
+			d->input_buf[1] = tv.tv_sec >> 16;
+			d->input_buf[2] = tv.tv_sec >>  8;
+			d->input_buf[3] = tv.tv_sec;
+			d->cur_input_length = 4;
+		} else if (d->cur_output_offset == 2 &&
+		    d->output_buf[1] == 0x11) {
+			/*  Reboot.  */
+			fatal("[ adb: reboot. TODO: make this nicer ]\n");
+			exit(1);
+		} else {
+			fatal("[ adb: UNIMPLEMENTED PRAM/RTC command ]\n");
+			exit(1);
+		}
+		break;
+
+	default:fatal("[ adb: UNKNOWN command type 0x%02x ]\n",
+		    d->output_buf[0]);
+		exit(1);
+	}
+
+	d->reg[vBufB >> VIA_REG_SHIFT] &= ~BUFB_nINTR;
+	d->reg[vIFR >> VIA_REG_SHIFT] |= IFR_ANY | IFR_SR;
+	d->reg[vSR >> VIA_REG_SHIFT] = 0x00;	/*  Dummy.  */
+}
+
+
+/*
+ *  adb_transfer():
+ *
+ *  This function should be called whenever a new transfer is started, a
+ *  transfer is finished, or when the next byte in a transfer should be
+ *  sent/received.
+ */
+static void adb_transfer(struct cpu *cpu, struct adb_data *d, int state_change)
+{
+	unsigned char c = 0x00;
+
+	if (state_change) {
+		if (d->tip == 0) {
+			debug("[ adb: transfer #%lli done ]\n",
+			    (long long)d->transfer_nr);
+			if (d->cur_output_offset > 0)
+				adb_process_cmd(cpu, d);
+			d->transfer_nr ++;
+			return;
+		}
+		debug("[ adb: starting transfer #%lli: %s ]\n", (long long)
+		    d->transfer_nr, d->dir == DIR_INPUT? "INPUT" : "OUTPUT");
+		d->cur_input_offset = d->cur_output_offset = 0;
+	}
+
+	debug("[ adb: transfer #%lli: ", (long long)d->transfer_nr);
+
+	switch (d->dir) {
+
+	case DIR_INPUT:
+		if (d->cur_input_offset >= d->cur_input_length)
+			fatal("[ adb: INPUT beyond end of data? ]\n");
+		else
+			c = d->input_buf[d->cur_input_offset ++];
+		debug("input 0x%02x", c);
+		d->reg[vSR >> VIA_REG_SHIFT] = c;
+		d->reg[vIFR >> VIA_REG_SHIFT] |= IFR_ANY | IFR_SR;
+		if (d->cur_input_offset >= d->cur_input_length)
+			d->reg[vBufB >> VIA_REG_SHIFT] |= BUFB_nINTR;
+		break;
+
+	case DIR_OUTPUT:
+		c = d->reg[vSR >> VIA_REG_SHIFT];
+		debug("output 0x%02x", c);
+		d->reg[vIFR >> VIA_REG_SHIFT] |= IFR_ANY | IFR_SR;
+		d->reg[vBufB >> VIA_REG_SHIFT] |= BUFB_nINTR;
+		d->output_buf[d->cur_output_offset ++] = c;
+		break;
+	}
+
+	debug(" ]\n");
+}
+
+
+DEVICE_ACCESS(adb)
+{
+	uint64_t idata = 0, odata = 0;
+	struct adb_data *d = (struct adb_data *) extra;
+	// uint8_t old = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+#ifdef ADB_DEBUG
+	if ((relative_addr & ((1 << VIA_REG_SHIFT) - 1)) != 0)
+		fatal("[ adb: %s non-via register? offset 0x%x ]\n",
+		    writeflag == MEM_READ? "read from" : "write to",
+		    (int)relative_addr);
+	else if (writeflag == MEM_READ)
+		fatal("[ adb: read from %s: 0x%02x ]\n",
+		    via_regname[relative_addr >> VIA_REG_SHIFT],
+		    (int)d->reg[relative_addr >> VIA_REG_SHIFT]);
+	else
+		fatal("[ adb: write to %s: 0x%02x ]\n", via_regname[
+		    relative_addr >> VIA_REG_SHIFT], (int)idata);
+#endif
+
+	if (writeflag == MEM_READ)
+		odata = d->reg[relative_addr >> VIA_REG_SHIFT];
+	else {
+		// old = d->reg[relative_addr >> VIA_REG_SHIFT];
+		switch (relative_addr) {
+		case vIFR:
+			/*
+			 *  vIFR is write-ones-to-clear, and the highest bit
+			 *  (IFR_ANY) is set if any of the lower bits are set.
+			 */
+			d->reg[relative_addr >> VIA_REG_SHIFT] &= ~(idata|0x80);
+			if (d->reg[relative_addr >> VIA_REG_SHIFT] & 0x7f)
+				d->reg[relative_addr >> VIA_REG_SHIFT] |= 0x80;
+			break;
+		default:
+			d->reg[relative_addr >> VIA_REG_SHIFT] = idata;
+		}
+	}
+
+	switch (relative_addr) {
+
+	case vBufB:
+		/*  OK  */
+		if (writeflag == MEM_WRITE) {
+			int old_tip = d->tip;
+			int old_ack = d->ack;
+			if (idata & BUFB_nINTR)
+				idata &= ~BUFB_nINTR;
+			d->ack = 0;
+			if (idata & BUFB_ACK) {
+				idata &= ~BUFB_ACK;
+				d->ack = 1;
+			}
+			d->tip = 1;
+			if (idata & BUFB_nTIP) {
+				idata &= ~BUFB_nTIP;
+				d->tip = 0;
+			}
+			if (idata != 0)
+				fatal("[ adb: WARNING! UNIMPLEMENTED bits in"
+				    " vBufB: 0x%02x ]\n", (int)idata);
+			if (old_tip != d->tip)
+				adb_transfer(cpu, d, 1);
+			else if (old_ack != d->ack)
+				adb_transfer(cpu, d, 0);
+		}
+		break;
+
+	case vDirB:
+		break;
+
+	case vSR:
+		/*  Clear the SR interrupt flag, if set:  */
+		d->reg[vIFR >> VIA_REG_SHIFT] &= ~IFR_SR;
+		break;
+
+	case vACR:
+		/*  OK  */
+		if (writeflag == MEM_WRITE) {
+			if (idata & ACR_SR_OUT)
+				d->dir = DIR_OUTPUT;
+			else
+				d->dir = DIR_INPUT;
+		}
+		break;
+
+	case vIFR:
+		/*  OK  */
+		break;
+
+	case vIER:
+		/*  OK  */
+		if (writeflag == MEM_WRITE) {
+			d->int_enable = idata & 0x80? 1 : 0;
+			if (idata != 0x04 && idata != 0x84)
+				fatal("[ adb: WARNING! vIER value 0x%x is"
+				    " UNKNOWN ]\n", (int)idata);
+		}
+		break;
+
+	default:if ((relative_addr & ((1 << VIA_REG_SHIFT) - 1)) != 0)
+			fatal("[ adb: %s non-via register? offset 0x%x ]\n",
+			    writeflag == MEM_READ? "read from" : "write to",
+			    (int)relative_addr);
+		else if (writeflag == MEM_READ)
+			fatal("[ adb: READ from UNIMPLEMENTED %s ]\n",
+			    via_regname[relative_addr >> VIA_REG_SHIFT]);
+		else
+			fatal("[ adb: WRITE to UNIMPLEMENTED %s: 0x%x ]\n",
+			    via_regname[relative_addr >> VIA_REG_SHIFT],
+			    (int)idata);
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(adb)
+{
+	struct adb_data *d;
+
+	CHECK_ALLOCATION(d = (struct adb_data *) malloc(sizeof(struct adb_data)));
+	memset(d, 0, sizeof(struct adb_data));
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	adb_reset(d);
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_ADB_LENGTH, dev_adb_access, d, DM_DEFAULT, NULL);
+	machine_add_tickfunction(devinit->machine, dev_adb_tick, d,
+	    TICK_SHIFT);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_adb.cc gxemul-0.7.0+dfsg/src/devices/dev_adb.cc
--- gxemul-0.6.2/src/devices/dev_adb.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_adb.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,455 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Apple Desktop Bus (ADB) controller
- *
- *  Based on intuition from reverse-engineering NetBSD/macppc source code,
- *  so it probably only works with that OS.
- *
- *  The comment "OK" means that 100% of the functionality used by NetBSD/macppc
- *  is covered.
- *
- *  TODO:
- *	o)  Clean up, don't hardcode values.
- *	o)  Convert into a separate controller, bus, device architecture.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/time.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/adb_viareg.h"
-
-
-#define debug fatal
-/*  #define ADB_DEBUG  */
-
-
-#define	TICK_SHIFT		17
-#define	DEV_ADB_LENGTH		0x2000
-
-#define	N_VIA_REGS		0x10
-#define	VIA_REG_SHIFT		9
-
-#define	MAX_BUF			100
-
-
-static const char *via_regname[N_VIA_REGS] = {
-	"vBufB", "vBufA", "vDirB", "vDirA",
-	"vT1C",  "vT1CH", "vT1L",  "vT1LH",
-	"vT2C",  "vT2CH", "vSR",   "vACR",
-	"vPCR",  "vIFR",  "vIER",  "(unknown)" };
-
-struct adb_data {
-	struct interrupt irq;
-	int		int_asserted;
-
-	int		kbd_dev;
-
-	long long	transfer_nr;
-
-	uint8_t		reg[N_VIA_REGS];
-
-	int		cur_output_offset;
-	uint8_t		output_buf[MAX_BUF];
-
-	int		cur_input_offset;
-	int		cur_input_length;
-	uint8_t		input_buf[MAX_BUF];
-
-	int		dir;
-	int		int_enable;
-	int		ack;		/*  last ack state  */
-	int		tip;		/*  transfer in progress  */
-};
-
-#define	DIR_INPUT		0
-#define	DIR_OUTPUT		1
-
-#define	BUFB_nINTR		0x08
-#define	BUFB_ACK		0x10
-#define	BUFB_nTIP		0x20
-#define	IFR_SR			0x04
-#define	IFR_ANY			0x80
-#define	ACR_SR_OUT		0x10
-
-
-
-DEVICE_TICK(adb)
-{
-	struct adb_data *d = (struct adb_data *) extra;
-	int assert;
-
-	assert = d->reg[vIFR >> VIA_REG_SHIFT] & IFR_ANY;
-	if (assert == IFR_ANY && d->int_enable)
-		assert = 1;
-
-	if (assert)
-		INTERRUPT_ASSERT(d->irq);
-	else if (d->int_asserted)
-		INTERRUPT_DEASSERT(d->irq);
-
-	d->int_asserted = assert;
-}
-
-
-/*
- *  adb_reset():
- *
- *  Reset registers to default values.
- */
-static void adb_reset(struct adb_data *d)
-{
-	d->kbd_dev = 2;
-
-	memset(d->reg, 0, sizeof(d->reg));
-	d->reg[vBufB >> VIA_REG_SHIFT] = BUFB_nINTR | BUFB_nTIP;
-
-	d->cur_output_offset = 0;
-	memset(d->output_buf, 0, sizeof(d->output_buf));
-
-	d->dir = 0;
-	d->int_enable = 0;
-	d->ack = 0;
-	d->tip = 0;
-}
-
-
-/*
- *  adb_process_cmd():
- *
- *  This function should be called whenever a complete ADB command has been
- *  received.
- */
-static void adb_process_cmd(struct cpu *cpu, struct adb_data *d)
-{
-	int i, reg, dev;
-
-	debug("[ adb: COMMAND:");
-	for (i=0; i<d->cur_output_offset; i++)
-		debug(" %02x", d->output_buf[i]);
-	debug(" ]\n");
-
-	if (d->cur_output_offset < 2) {
-		fatal("[ adb: WEIRD output length: %i ]\n",
-		    d->cur_output_offset);
-		exit(1);
-	}
-
-	switch (d->output_buf[0]) {
-
-	case 0:	/*  ADB commands:  */
-		if (d->output_buf[1] == 0x00) {
-			/*  Reset.  */
-			return;
-		}
-		if ((d->output_buf[1] & 0x0c) == 0x0c) {
-			/*  ADBTALK:  */
-			reg = d->output_buf[1] & 3;
-			dev = d->output_buf[1] >> 4;
-			fatal("dev=%i reg=%i\n", dev, reg);
-			/*  Default values: nothing here  */
-			d->input_buf[0] = 0x00;
-			d->input_buf[1] = 0x00;
-			d->input_buf[2] = d->output_buf[1];
-			d->cur_input_length = 3;
-			if (dev == d->kbd_dev) {
-				/*  Keyboard.  */
-				d->input_buf[0] = 0x01;
-				d->input_buf[1] = 0x01;
-				d->input_buf[2] = d->output_buf[1];
-				d->input_buf[3] = 0x01;
-				d->input_buf[4] = 0x01;
-				d->cur_input_length = 5;
-			}
-		} else if ((d->output_buf[1] & 0x0c) == 0x08) {
-			int new_dev_pos = d->output_buf[2] & 15;
-			/*  ADBLISTEN:  */
-			if ((d->output_buf[1] >> 4) != d->kbd_dev) {
-				fatal("[ adb: ADBLISTEN not to kbd ]\n");
-				exit(1);
-			}
-			if (d->output_buf[3] != 0xfe ||
-			    (d->output_buf[2] & 0xf0) != 0x60) {
-				fatal("[ adb: unknown ADBLISTEN ]\n");
-				exit(1);
-			}
-			/*  Move device.  */
-			d->kbd_dev = new_dev_pos;
-		} else {
-			fatal("[ adb: unknown ADB command? ]\n");
-			exit(1);
-		}
-		break;
-
-	case 1:	/*  PRAM/RTC:  */
-		if (d->cur_output_offset == 3 &&
-		    d->output_buf[1] == 0x01 &&
-		    d->output_buf[2] == 0x01) {
-			/*  Autopoll:  */
-			d->input_buf[0] = 0x00;
-			d->input_buf[1] = 0x00;
-			d->input_buf[2] = d->output_buf[1];
-			d->cur_input_length = 3;
-		} else if (d->cur_output_offset == 2 &&
-		    d->output_buf[1] == 0x03) {
-			/*  Read RTC date/time:  */
-			struct timeval tv;
-			gettimeofday(&tv, NULL);
-			d->input_buf[0] = tv.tv_sec >> 24;
-			d->input_buf[1] = tv.tv_sec >> 16;
-			d->input_buf[2] = tv.tv_sec >>  8;
-			d->input_buf[3] = tv.tv_sec;
-			d->cur_input_length = 4;
-		} else if (d->cur_output_offset == 2 &&
-		    d->output_buf[1] == 0x11) {
-			/*  Reboot.  */
-			fatal("[ adb: reboot. TODO: make this nicer ]\n");
-			exit(1);
-		} else {
-			fatal("[ adb: UNIMPLEMENTED PRAM/RTC command ]\n");
-			exit(1);
-		}
-		break;
-
-	default:fatal("[ adb: UNKNOWN command type 0x%02x ]\n",
-		    d->output_buf[0]);
-		exit(1);
-	}
-
-	d->reg[vBufB >> VIA_REG_SHIFT] &= ~BUFB_nINTR;
-	d->reg[vIFR >> VIA_REG_SHIFT] |= IFR_ANY | IFR_SR;
-	d->reg[vSR >> VIA_REG_SHIFT] = 0x00;	/*  Dummy.  */
-}
-
-
-/*
- *  adb_transfer():
- *
- *  This function should be called whenever a new transfer is started, a
- *  transfer is finished, or when the next byte in a transfer should be
- *  sent/received.
- */
-static void adb_transfer(struct cpu *cpu, struct adb_data *d, int state_change)
-{
-	unsigned char c = 0x00;
-
-	if (state_change) {
-		if (d->tip == 0) {
-			debug("[ adb: transfer #%lli done ]\n",
-			    (long long)d->transfer_nr);
-			if (d->cur_output_offset > 0)
-				adb_process_cmd(cpu, d);
-			d->transfer_nr ++;
-			return;
-		}
-		debug("[ adb: starting transfer #%lli: %s ]\n", (long long)
-		    d->transfer_nr, d->dir == DIR_INPUT? "INPUT" : "OUTPUT");
-		d->cur_input_offset = d->cur_output_offset = 0;
-	}
-
-	debug("[ adb: transfer #%lli: ", (long long)d->transfer_nr);
-
-	switch (d->dir) {
-
-	case DIR_INPUT:
-		if (d->cur_input_offset >= d->cur_input_length)
-			fatal("[ adb: INPUT beyond end of data? ]\n");
-		else
-			c = d->input_buf[d->cur_input_offset ++];
-		debug("input 0x%02x", c);
-		d->reg[vSR >> VIA_REG_SHIFT] = c;
-		d->reg[vIFR >> VIA_REG_SHIFT] |= IFR_ANY | IFR_SR;
-		if (d->cur_input_offset >= d->cur_input_length)
-			d->reg[vBufB >> VIA_REG_SHIFT] |= BUFB_nINTR;
-		break;
-
-	case DIR_OUTPUT:
-		c = d->reg[vSR >> VIA_REG_SHIFT];
-		debug("output 0x%02x", c);
-		d->reg[vIFR >> VIA_REG_SHIFT] |= IFR_ANY | IFR_SR;
-		d->reg[vBufB >> VIA_REG_SHIFT] |= BUFB_nINTR;
-		d->output_buf[d->cur_output_offset ++] = c;
-		break;
-	}
-
-	debug(" ]\n");
-}
-
-
-DEVICE_ACCESS(adb)
-{
-	uint64_t idata = 0, odata = 0;
-	struct adb_data *d = (struct adb_data *) extra;
-	// uint8_t old = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-#ifdef ADB_DEBUG
-	if ((relative_addr & ((1 << VIA_REG_SHIFT) - 1)) != 0)
-		fatal("[ adb: %s non-via register? offset 0x%x ]\n",
-		    writeflag == MEM_READ? "read from" : "write to",
-		    (int)relative_addr);
-	else if (writeflag == MEM_READ)
-		fatal("[ adb: read from %s: 0x%02x ]\n",
-		    via_regname[relative_addr >> VIA_REG_SHIFT],
-		    (int)d->reg[relative_addr >> VIA_REG_SHIFT]);
-	else
-		fatal("[ adb: write to %s: 0x%02x ]\n", via_regname[
-		    relative_addr >> VIA_REG_SHIFT], (int)idata);
-#endif
-
-	if (writeflag == MEM_READ)
-		odata = d->reg[relative_addr >> VIA_REG_SHIFT];
-	else {
-		// old = d->reg[relative_addr >> VIA_REG_SHIFT];
-		switch (relative_addr) {
-		case vIFR:
-			/*
-			 *  vIFR is write-ones-to-clear, and the highest bit
-			 *  (IFR_ANY) is set if any of the lower bits are set.
-			 */
-			d->reg[relative_addr >> VIA_REG_SHIFT] &= ~(idata|0x80);
-			if (d->reg[relative_addr >> VIA_REG_SHIFT] & 0x7f)
-				d->reg[relative_addr >> VIA_REG_SHIFT] |= 0x80;
-			break;
-		default:
-			d->reg[relative_addr >> VIA_REG_SHIFT] = idata;
-		}
-	}
-
-	switch (relative_addr) {
-
-	case vBufB:
-		/*  OK  */
-		if (writeflag == MEM_WRITE) {
-			int old_tip = d->tip;
-			int old_ack = d->ack;
-			if (idata & BUFB_nINTR)
-				idata &= ~BUFB_nINTR;
-			d->ack = 0;
-			if (idata & BUFB_ACK) {
-				idata &= ~BUFB_ACK;
-				d->ack = 1;
-			}
-			d->tip = 1;
-			if (idata & BUFB_nTIP) {
-				idata &= ~BUFB_nTIP;
-				d->tip = 0;
-			}
-			if (idata != 0)
-				fatal("[ adb: WARNING! UNIMPLEMENTED bits in"
-				    " vBufB: 0x%02x ]\n", (int)idata);
-			if (old_tip != d->tip)
-				adb_transfer(cpu, d, 1);
-			else if (old_ack != d->ack)
-				adb_transfer(cpu, d, 0);
-		}
-		break;
-
-	case vDirB:
-		break;
-
-	case vSR:
-		/*  Clear the SR interrupt flag, if set:  */
-		d->reg[vIFR >> VIA_REG_SHIFT] &= ~IFR_SR;
-		break;
-
-	case vACR:
-		/*  OK  */
-		if (writeflag == MEM_WRITE) {
-			if (idata & ACR_SR_OUT)
-				d->dir = DIR_OUTPUT;
-			else
-				d->dir = DIR_INPUT;
-		}
-		break;
-
-	case vIFR:
-		/*  OK  */
-		break;
-
-	case vIER:
-		/*  OK  */
-		if (writeflag == MEM_WRITE) {
-			d->int_enable = idata & 0x80? 1 : 0;
-			if (idata != 0x04 && idata != 0x84)
-				fatal("[ adb: WARNING! vIER value 0x%x is"
-				    " UNKNOWN ]\n", (int)idata);
-		}
-		break;
-
-	default:if ((relative_addr & ((1 << VIA_REG_SHIFT) - 1)) != 0)
-			fatal("[ adb: %s non-via register? offset 0x%x ]\n",
-			    writeflag == MEM_READ? "read from" : "write to",
-			    (int)relative_addr);
-		else if (writeflag == MEM_READ)
-			fatal("[ adb: READ from UNIMPLEMENTED %s ]\n",
-			    via_regname[relative_addr >> VIA_REG_SHIFT]);
-		else
-			fatal("[ adb: WRITE to UNIMPLEMENTED %s: 0x%x ]\n",
-			    via_regname[relative_addr >> VIA_REG_SHIFT],
-			    (int)idata);
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(adb)
-{
-	struct adb_data *d;
-
-	CHECK_ALLOCATION(d = (struct adb_data *) malloc(sizeof(struct adb_data)));
-	memset(d, 0, sizeof(struct adb_data));
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	adb_reset(d);
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_ADB_LENGTH, dev_adb_access, d, DM_DEFAULT, NULL);
-	machine_add_tickfunction(devinit->machine, dev_adb_tick, d,
-	    TICK_SHIFT);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_ahc.c gxemul-0.7.0+dfsg/src/devices/dev_ahc.c
--- gxemul-0.6.2/src/devices/dev_ahc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ahc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,205 @@
+/*
+ *  Copyright (C) 2004-2018  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Adaptec AHC SCSI controller
+ *
+ *  NetBSD should say something like this, on SGI-IP32:
+ *
+ *	ahc0 at pci0 dev 1 function 0: Adaptec aic7880 Ultra SCSI adapter
+ *	ahc0: interrupting at crime interrupt 8
+ *	ahc0: Using left over BIOS settings
+ *	ahc0: Host Adapter has no SEEPROM. Using default SCSI target parameters
+ *	ahc0: aic7880: Ultra Wide Channel A, SCSI Id=0, 16/253 SCBs
+ *	scsibus0 at ahc0: 16 targets, 8 luns per target
+ *
+ *  TODO:  This is just a dummy device, so far.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/aic7xxx_reg.h"
+
+
+#define	AHC_DEBUG
+#define debug fatal
+
+
+#define	DEV_AHC_LENGTH		0x100
+
+struct ahc_data {
+	unsigned char	reg[DEV_AHC_LENGTH];
+};
+
+
+DEVICE_ACCESS(ahc)
+{
+	struct ahc_data *d = (struct ahc_data *) extra;
+	uint64_t idata, odata = 0;
+	int ok = 0;
+	const char *name = NULL;
+
+	idata = memory_readmax64(cpu, data, len);
+
+	/*  SGI uses weird reversed order addresses:  */
+	if (cpu->byte_order == EMUL_BIG_ENDIAN)
+		relative_addr ^= 3;
+
+	if (len != 1)
+		fatal("[ ahc: ERROR! Unimplemented len %i ]\n", len);
+
+	if (writeflag == MEM_READ)
+		odata = d->reg[relative_addr];
+
+	switch (relative_addr) {
+
+	case SCSIID:
+		if (writeflag == MEM_READ) {
+			ok = 1; name = "SCSIID";
+			odata = 0;
+		} else {
+			fatal("[ ahc: write to SCSIOFFSET, data = 0x"
+			    "%02x: TODO ]\n", (int)idata);
+		}
+		break;
+
+	case KERNEL_QINPOS:
+		if (writeflag == MEM_WRITE) {
+
+			/*  TODO  */
+
+			d->reg[INTSTAT] |= SEQINT;
+		}
+		break;
+
+	case SEECTL:
+		ok = 1; name = "SEECTL";
+		if (writeflag == MEM_WRITE)
+			d->reg[relative_addr] = idata;
+		odata |= SEERDY;
+		break;
+
+	case SCSICONF:
+		ok = 1; name = "SCSICONF";
+		if (writeflag == MEM_READ) {
+			odata = 0;
+		} else {
+			fatal("[ ahc: write to SCSICONF, data = 0x%02x:"
+			    " TODO ]\n", (int)idata);
+		}
+		break;
+
+	case SEQRAM:
+	case SEQADDR0:
+	case SEQADDR1:
+		/*  TODO: This is just a dummy.  */
+		break;
+
+	case HCNTRL:
+		ok = 1; name = "HCNTRL";
+		if (writeflag == MEM_WRITE)
+			d->reg[relative_addr] = idata;
+		break;
+
+	case INTSTAT:
+		ok = 1; name = "INTSTAT";
+		if (writeflag == MEM_WRITE)
+			fatal("[ ahc: write to INTSTAT? data = 0x%02x ]\n",
+			    (int)idata);
+		break;
+
+	case CLRINT:
+		if (writeflag == MEM_READ) {
+			ok = 1; name = "ERROR";
+			/*  TODO  */
+		} else {
+			ok = 1; name = "CLRINT";
+			if (idata & ~0xf)
+				fatal("[ ahc: write to CLRINT: 0x%02x "
+				    "(TODO) ]\n", (int)idata);
+			/*  Clear the lowest 4 bits of intstat:  */
+			d->reg[INTSTAT] &= ~(idata & 0xf);
+		}
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			fatal("[ ahc: UNIMPLEMENTED write to address 0x%x, "
+			    "data=0x%02x ]\n", (int)relative_addr, (int)idata);
+		else
+			fatal("[ ahc: UNIMPLEMENTED read from address 0x%x ]\n",
+			    (int)relative_addr);
+	}
+
+#ifdef AHC_DEBUG
+	if (ok) {
+		if (name == NULL) {
+			if (writeflag == MEM_WRITE)
+				debug("[ ahc: write to address 0x%x: 0x"
+				    "%02x ]\n", (int)relative_addr, (int)idata);
+			else
+				debug("[ ahc: read from address 0x%x: 0x"
+				    "%02x ]\n", (int)relative_addr, (int)odata);
+		} else {
+			if (writeflag == MEM_WRITE)
+				debug("[ ahc: write to %s: 0x%02x ]\n",
+				    name, (int)idata);
+			else
+				debug("[ ahc: read from %s: 0x%02x ]\n",
+				    name, (int)odata);
+		}
+	}
+#endif
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(ahc)
+{
+	struct ahc_data *d;
+
+	CHECK_ALLOCATION(d = (struct ahc_data *) malloc(sizeof(struct ahc_data)));
+	memset(d, 0, sizeof(struct ahc_data));
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_AHC_LENGTH, dev_ahc_access, d,
+	    DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_ahc.cc gxemul-0.7.0+dfsg/src/devices/dev_ahc.cc
--- gxemul-0.6.2/src/devices/dev_ahc.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ahc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,205 +0,0 @@
-/*
- *  Copyright (C) 2004-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Adaptec AHC SCSI controller
- *
- *  NetBSD should say something like this, on SGI-IP32:
- *
- *	ahc0 at pci0 dev 1 function 0: Adaptec aic7880 Ultra SCSI adapter
- *	ahc0: interrupting at crime interrupt 8
- *	ahc0: Using left over BIOS settings
- *	ahc0: Host Adapter has no SEEPROM. Using default SCSI target parameters
- *	ahc0: aic7880: Ultra Wide Channel A, SCSI Id=0, 16/253 SCBs
- *	scsibus0 at ahc0: 16 targets, 8 luns per target
- *
- *  TODO:  This is just a dummy device, so far.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/aic7xxx_reg.h"
-
-
-#define	AHC_DEBUG
-#define debug fatal
-
-
-#define	DEV_AHC_LENGTH		0x100
-
-struct ahc_data {
-	unsigned char	reg[DEV_AHC_LENGTH];
-};
-
-
-DEVICE_ACCESS(ahc)
-{
-	struct ahc_data *d = (struct ahc_data *) extra;
-	uint64_t idata, odata = 0;
-	int ok = 0;
-	const char *name = NULL;
-
-	idata = memory_readmax64(cpu, data, len);
-
-	/*  SGI uses weird reversed order addresses:  */
-	if (cpu->byte_order == EMUL_BIG_ENDIAN)
-		relative_addr ^= 3;
-
-	if (len != 1)
-		fatal("[ ahc: ERROR! Unimplemented len %i ]\n", len);
-
-	if (writeflag == MEM_READ)
-		odata = d->reg[relative_addr];
-
-	switch (relative_addr) {
-
-	case SCSIID:
-		if (writeflag == MEM_READ) {
-			ok = 1; name = "SCSIID";
-			odata = 0;
-		} else {
-			fatal("[ ahc: write to SCSIOFFSET, data = 0x"
-			    "%02x: TODO ]\n", (int)idata);
-		}
-		break;
-
-	case KERNEL_QINPOS:
-		if (writeflag == MEM_WRITE) {
-
-			/*  TODO  */
-
-			d->reg[INTSTAT] |= SEQINT;
-		}
-		break;
-
-	case SEECTL:
-		ok = 1; name = "SEECTL";
-		if (writeflag == MEM_WRITE)
-			d->reg[relative_addr] = idata;
-		odata |= SEERDY;
-		break;
-
-	case SCSICONF:
-		ok = 1; name = "SCSICONF";
-		if (writeflag == MEM_READ) {
-			odata = 0;
-		} else {
-			fatal("[ ahc: write to SCSICONF, data = 0x%02x:"
-			    " TODO ]\n", (int)idata);
-		}
-		break;
-
-	case SEQRAM:
-	case SEQADDR0:
-	case SEQADDR1:
-		/*  TODO: This is just a dummy.  */
-		break;
-
-	case HCNTRL:
-		ok = 1; name = "HCNTRL";
-		if (writeflag == MEM_WRITE)
-			d->reg[relative_addr] = idata;
-		break;
-
-	case INTSTAT:
-		ok = 1; name = "INTSTAT";
-		if (writeflag == MEM_WRITE)
-			fatal("[ ahc: write to INTSTAT? data = 0x%02x ]\n",
-			    (int)idata);
-		break;
-
-	case CLRINT:
-		if (writeflag == MEM_READ) {
-			ok = 1; name = "ERROR";
-			/*  TODO  */
-		} else {
-			ok = 1; name = "CLRINT";
-			if (idata & ~0xf)
-				fatal("[ ahc: write to CLRINT: 0x%02x "
-				    "(TODO) ]\n", (int)idata);
-			/*  Clear the lowest 4 bits of intstat:  */
-			d->reg[INTSTAT] &= ~(idata & 0xf);
-		}
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE)
-			fatal("[ ahc: UNIMPLEMENTED write to address 0x%x, "
-			    "data=0x%02x ]\n", (int)relative_addr, (int)idata);
-		else
-			fatal("[ ahc: UNIMPLEMENTED read from address 0x%x ]\n",
-			    (int)relative_addr);
-	}
-
-#ifdef AHC_DEBUG
-	if (ok) {
-		if (name == NULL) {
-			if (writeflag == MEM_WRITE)
-				debug("[ ahc: write to address 0x%x: 0x"
-				    "%02x ]\n", (int)relative_addr, (int)idata);
-			else
-				debug("[ ahc: read from address 0x%x: 0x"
-				    "%02x ]\n", (int)relative_addr, (int)odata);
-		} else {
-			if (writeflag == MEM_WRITE)
-				debug("[ ahc: write to %s: 0x%02x ]\n",
-				    name, (int)idata);
-			else
-				debug("[ ahc: read from %s: 0x%02x ]\n",
-				    name, (int)odata);
-		}
-	}
-#endif
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(ahc)
-{
-	struct ahc_data *d;
-
-	CHECK_ALLOCATION(d = (struct ahc_data *) malloc(sizeof(struct ahc_data)));
-	memset(d, 0, sizeof(struct ahc_data));
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_AHC_LENGTH, dev_ahc_access, d,
-	    DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_algor.c gxemul-0.7.0+dfsg/src/devices/dev_algor.c
--- gxemul-0.6.2/src/devices/dev_algor.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_algor.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,229 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Algor P5064 misc. stuff
+ *
+ *  TODO: This is hardcoded for P5064 right now. Generalize it to P40xx etc.
+ *
+ *  CPU irq 2 = ISA, 3 = PCI, 4 = Local.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/algor_p5064reg.h"
+
+
+struct algor_data {
+	uint64_t		base_addr;
+	struct interrupt	mips_irq_2;
+	struct interrupt	mips_irq_3;
+	struct interrupt	mips_irq_4;
+};
+
+
+DEVICE_ACCESS(algor)
+{
+	struct algor_data *d = (struct algor_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	const char *n = NULL;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	relative_addr += d->base_addr;
+
+	switch (relative_addr) {
+
+	case P5064_LED1 + 0x0:
+	case P5064_LED1 + 0x4:
+	case P5064_LED1 + 0x8:
+	case P5064_LED1 + 0xc:
+		break;
+
+	case P5064_LOCINT:
+		/*
+		 *  TODO: See how ISAINT is implemented.
+		 *
+		 *  Implemented so far: COM1 only.
+		 */
+		n = "P5064_LOCINT";
+		if (writeflag == MEM_READ) {
+			/*  Ugly hack for NetBSD startup.  TODO: fix  */
+			static int x = 0;
+			if (((++ x) & 0xffff) == 0)
+				odata |= LOCINT_RTC;
+
+			if (cpu->machine->isa_pic_data.pic1->irr &
+			    ~cpu->machine->isa_pic_data.pic1->ier & 0x10)
+				odata |= LOCINT_COM1;
+			if (cpu->machine->isa_pic_data.pic1->irr &
+			    ~cpu->machine->isa_pic_data.pic1->ier & 0x08)
+				odata |= LOCINT_COM2;
+
+			/*  Read => ack:  */
+			cpu->machine->isa_pic_data.pic1->irr &= ~0x18;
+			INTERRUPT_DEASSERT(d->mips_irq_4);
+		} else {
+			if (idata & LOCINT_COM1)
+				cpu->machine->isa_pic_data.pic1->ier &= ~0x10;
+			else
+				cpu->machine->isa_pic_data.pic1->ier |= 0x10;
+			if (idata & LOCINT_COM2)
+				cpu->machine->isa_pic_data.pic1->ier &= ~0x08;
+			else
+				cpu->machine->isa_pic_data.pic1->ier |= 0x08;
+		}
+		break;
+
+	case P5064_PANIC:
+		n = "P5064_PANIC";
+		if (writeflag == MEM_READ)
+			odata = 0;
+		break;
+
+	case P5064_PCIINT:
+		/*
+		 *  TODO: See how ISAINT is implemented.
+		 */
+		n = "P5064_PCIINT";
+		if (writeflag == MEM_READ) {
+			odata = 0;
+			INTERRUPT_DEASSERT(d->mips_irq_3);
+		}
+		break;
+
+	case P5064_ISAINT:
+		/*
+		 *  ISA interrupts:
+		 *
+		 *	Bit:  IRQ Source:
+		 *	0     ISAINT_ISABR
+		 *	1     ISAINT_IDE0
+		 *	2     ISAINT_IDE1
+		 *
+		 *  NOTE/TODO: Ugly redirection to the ISA controller.
+		 */
+		n = "P5064_ISAINT";
+		if (writeflag == MEM_WRITE) {
+			if (idata & ISAINT_IDE0)
+				cpu->machine->isa_pic_data.pic2->ier &= ~0x40;
+			else
+				cpu->machine->isa_pic_data.pic2->ier |= 0x40;
+			if (idata & ISAINT_IDE1)
+				cpu->machine->isa_pic_data.pic2->ier &= ~0x80;
+			else
+				cpu->machine->isa_pic_data.pic2->ier |= 0x80;
+			cpu->machine->isa_pic_data.pic1->ier &= ~0x04;
+		} else {
+			if (cpu->machine->isa_pic_data.pic2->irr &
+			    ~cpu->machine->isa_pic_data.pic2->ier & 0x40)
+				odata |= ISAINT_IDE0;
+			if (cpu->machine->isa_pic_data.pic2->irr &
+			    ~cpu->machine->isa_pic_data.pic2->ier & 0x80)
+				odata |= ISAINT_IDE1;
+
+			/*  Read => ack:  */
+			cpu->machine->isa_pic_data.pic2->irr &= ~0xc0;
+			INTERRUPT_DEASSERT(d->mips_irq_2);
+		}
+		break;
+
+	case P5064_KBDINT:
+		/*
+		 *  TODO: See how ISAINT is implemented.
+		 */
+		n = "P5064_KBDINT";
+		if (writeflag == MEM_READ)
+			odata = 0;
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ algor: read from 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ algor: write to 0x%x: 0x%" PRIx64" ]\n",
+			    (int) relative_addr, (uint64_t) idata);
+		}
+	}
+
+	if (n != NULL) {
+		if (writeflag == MEM_READ) {
+			debug("[ algor: read from %s: 0x%" PRIx64" ]\n",
+			    n, (uint64_t) odata);
+		} else {
+			debug("[ algor: write to %s: 0x%" PRIx64" ]\n",
+			    n, (uint64_t) idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(algor)
+{
+	char tmpstr[200];
+	struct algor_data *d;
+
+	CHECK_ALLOCATION(d = (struct algor_data *) malloc(sizeof(struct algor_data)));
+	memset(d, 0, sizeof(struct algor_data));
+
+	d->base_addr = devinit->addr;
+	if (devinit->addr != 0x1ff00000) {
+		fatal("The Algor base address should be 0x1ff00000.\n");
+		exit(1);
+	}
+
+	/*  Connect to MIPS irq 2, 3, and 4:  */
+	snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path);
+	INTERRUPT_CONNECT(tmpstr, d->mips_irq_2);
+	snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
+	INTERRUPT_CONNECT(tmpstr, d->mips_irq_3);
+	snprintf(tmpstr, sizeof(tmpstr), "%s.4", devinit->interrupt_path);
+	INTERRUPT_CONNECT(tmpstr, d->mips_irq_4);
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, 0x100000, dev_algor_access, d, DM_DEFAULT, NULL);
+
+	devinit->return_ptr = d;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_algor.cc gxemul-0.7.0+dfsg/src/devices/dev_algor.cc
--- gxemul-0.6.2/src/devices/dev_algor.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_algor.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,229 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Algor P5064 misc. stuff
- *
- *  TODO: This is hardcoded for P5064 right now. Generalize it to P40xx etc.
- *
- *  CPU irq 2 = ISA, 3 = PCI, 4 = Local.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/algor_p5064reg.h"
-
-
-struct algor_data {
-	uint64_t		base_addr;
-	struct interrupt	mips_irq_2;
-	struct interrupt	mips_irq_3;
-	struct interrupt	mips_irq_4;
-};
-
-
-DEVICE_ACCESS(algor)
-{
-	struct algor_data *d = (struct algor_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	const char *n = NULL;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	relative_addr += d->base_addr;
-
-	switch (relative_addr) {
-
-	case P5064_LED1 + 0x0:
-	case P5064_LED1 + 0x4:
-	case P5064_LED1 + 0x8:
-	case P5064_LED1 + 0xc:
-		break;
-
-	case P5064_LOCINT:
-		/*
-		 *  TODO: See how ISAINT is implemented.
-		 *
-		 *  Implemented so far: COM1 only.
-		 */
-		n = "P5064_LOCINT";
-		if (writeflag == MEM_READ) {
-			/*  Ugly hack for NetBSD startup.  TODO: fix  */
-			static int x = 0;
-			if (((++ x) & 0xffff) == 0)
-				odata |= LOCINT_RTC;
-
-			if (cpu->machine->isa_pic_data.pic1->irr &
-			    ~cpu->machine->isa_pic_data.pic1->ier & 0x10)
-				odata |= LOCINT_COM1;
-			if (cpu->machine->isa_pic_data.pic1->irr &
-			    ~cpu->machine->isa_pic_data.pic1->ier & 0x08)
-				odata |= LOCINT_COM2;
-
-			/*  Read => ack:  */
-			cpu->machine->isa_pic_data.pic1->irr &= ~0x18;
-			INTERRUPT_DEASSERT(d->mips_irq_4);
-		} else {
-			if (idata & LOCINT_COM1)
-				cpu->machine->isa_pic_data.pic1->ier &= ~0x10;
-			else
-				cpu->machine->isa_pic_data.pic1->ier |= 0x10;
-			if (idata & LOCINT_COM2)
-				cpu->machine->isa_pic_data.pic1->ier &= ~0x08;
-			else
-				cpu->machine->isa_pic_data.pic1->ier |= 0x08;
-		}
-		break;
-
-	case P5064_PANIC:
-		n = "P5064_PANIC";
-		if (writeflag == MEM_READ)
-			odata = 0;
-		break;
-
-	case P5064_PCIINT:
-		/*
-		 *  TODO: See how ISAINT is implemented.
-		 */
-		n = "P5064_PCIINT";
-		if (writeflag == MEM_READ) {
-			odata = 0;
-			INTERRUPT_DEASSERT(d->mips_irq_3);
-		}
-		break;
-
-	case P5064_ISAINT:
-		/*
-		 *  ISA interrupts:
-		 *
-		 *	Bit:  IRQ Source:
-		 *	0     ISAINT_ISABR
-		 *	1     ISAINT_IDE0
-		 *	2     ISAINT_IDE1
-		 *
-		 *  NOTE/TODO: Ugly redirection to the ISA controller.
-		 */
-		n = "P5064_ISAINT";
-		if (writeflag == MEM_WRITE) {
-			if (idata & ISAINT_IDE0)
-				cpu->machine->isa_pic_data.pic2->ier &= ~0x40;
-			else
-				cpu->machine->isa_pic_data.pic2->ier |= 0x40;
-			if (idata & ISAINT_IDE1)
-				cpu->machine->isa_pic_data.pic2->ier &= ~0x80;
-			else
-				cpu->machine->isa_pic_data.pic2->ier |= 0x80;
-			cpu->machine->isa_pic_data.pic1->ier &= ~0x04;
-		} else {
-			if (cpu->machine->isa_pic_data.pic2->irr &
-			    ~cpu->machine->isa_pic_data.pic2->ier & 0x40)
-				odata |= ISAINT_IDE0;
-			if (cpu->machine->isa_pic_data.pic2->irr &
-			    ~cpu->machine->isa_pic_data.pic2->ier & 0x80)
-				odata |= ISAINT_IDE1;
-
-			/*  Read => ack:  */
-			cpu->machine->isa_pic_data.pic2->irr &= ~0xc0;
-			INTERRUPT_DEASSERT(d->mips_irq_2);
-		}
-		break;
-
-	case P5064_KBDINT:
-		/*
-		 *  TODO: See how ISAINT is implemented.
-		 */
-		n = "P5064_KBDINT";
-		if (writeflag == MEM_READ)
-			odata = 0;
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ algor: read from 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ algor: write to 0x%x: 0x%" PRIx64" ]\n",
-			    (int) relative_addr, (uint64_t) idata);
-		}
-	}
-
-	if (n != NULL) {
-		if (writeflag == MEM_READ) {
-			debug("[ algor: read from %s: 0x%" PRIx64" ]\n",
-			    n, (uint64_t) odata);
-		} else {
-			debug("[ algor: write to %s: 0x%" PRIx64" ]\n",
-			    n, (uint64_t) idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(algor)
-{
-	char tmpstr[200];
-	struct algor_data *d;
-
-	CHECK_ALLOCATION(d = (struct algor_data *) malloc(sizeof(struct algor_data)));
-	memset(d, 0, sizeof(struct algor_data));
-
-	d->base_addr = devinit->addr;
-	if (devinit->addr != 0x1ff00000) {
-		fatal("The Algor base address should be 0x1ff00000.\n");
-		exit(1);
-	}
-
-	/*  Connect to MIPS irq 2, 3, and 4:  */
-	snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path);
-	INTERRUPT_CONNECT(tmpstr, d->mips_irq_2);
-	snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
-	INTERRUPT_CONNECT(tmpstr, d->mips_irq_3);
-	snprintf(tmpstr, sizeof(tmpstr), "%s.4", devinit->interrupt_path);
-	INTERRUPT_CONNECT(tmpstr, d->mips_irq_4);
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, 0x100000, dev_algor_access, d, DM_DEFAULT, NULL);
-
-	devinit->return_ptr = d;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_asc.c gxemul-0.7.0+dfsg/src/devices/dev_asc.c
--- gxemul-0.6.2/src/devices/dev_asc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_asc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1269 @@
+/*
+ *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: NCR53C9X "ASC" SCSI controller
+ *
+ *  This is the SCSI controller used in some DECstation/DECsystem models and
+ *  the PICA-61 machine.
+ *
+ *  Supposed to support SCSI-1 and SCSI-2. I've not yet found any docs
+ *  on NCR53C9X, so I'll try to implement this device from LSI53CF92A docs
+ *  instead.
+ *
+ *
+ *  Memory layout on DECstation:
+ *
+ *	NCR53C94 registers	at base + 0
+ *	DMA address register	at base + 0x40000
+ *	128K SRAM buffer	at base + 0x80000
+ *	ROM			at base + 0xc0000
+ *
+ *  Memory layout on PICA-61:
+ *
+ *	I haven't had time to look this up yet, but length = 0x1000.
+ *
+ *
+ *  TODO:  This module needs a clean-up, and some testing to see that
+ *         it works will all OSes that might use it (NetBSD, OpenBSD,
+ *         Ultrix, Linux, Mach, OSF/1, Sprite, ...)
+ *
+ *	   Running Linux/DECstation 2.4.26 with no scsi disks attached causes
+ *	   a warning message to be printed by Linux. (Whether this is a bug,
+ *	   is is the way it works on real hardware, I don't know.)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "devices.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/ncr53c9xreg.h"
+
+
+/*  #define ASC_DEBUG  */
+/*  #define debug fatal  */
+/*  #define ASC_FULL_REGISTER_ACCESS_DEBUG  */
+/*  static int quiet_mode = 0;  */
+
+#define	ASC_TICK_SHIFT		15
+
+extern int quiet_mode;
+
+
+#define	ASC_FIFO_LEN		16
+#define	STATE_DISCONNECTED	0
+#define	STATE_INITIATOR		1
+#define	STATE_TARGET		2
+
+#define	PHASE_DATA_OUT		0
+#define	PHASE_DATA_IN		1
+#define	PHASE_COMMAND		2
+#define	PHASE_STATUS		3
+#define	PHASE_MSG_OUT		6
+#define	PHASE_MSG_IN		7
+
+
+/*  The controller's SCSI id:  */
+#define	ASC_SCSI_ID		7
+
+#define	ASC_DMA_SIZE		(128*1024)
+
+struct asc_data {
+	int		mode;
+
+	void		*turbochannel;
+	struct interrupt irq;
+	int		irq_asserted;
+
+	/*  Current state and transfer:  */
+	int		cur_state;
+	int		cur_phase;
+	struct scsi_transfer *xferp;
+
+	/*  FIFO:  */
+	unsigned char	fifo[ASC_FIFO_LEN];
+	int		fifo_in;
+	int		fifo_out;
+	int		n_bytes_in_fifo;		/*  cached  */
+
+	/*  ATN signal:  */
+	int		atn;
+
+	/*  Incoming dma data:  */
+	unsigned char	*incoming_data;
+	int		incoming_len;
+	int		incoming_data_addr;
+
+	/*  Built-in DMA memory (for DECstation 5000/200):  */
+	uint32_t	dma_address_reg;
+	unsigned char	*dma_address_reg_memory;
+	unsigned char	*dma;
+
+	void		*dma_controller_data;
+	size_t		(*dma_controller)(void *dma_controller_data,
+			    unsigned char *data, size_t len, int writeflag);
+
+	/*  Read registers and write registers:  */
+	uint32_t	reg_ro[0x10];
+	uint32_t	reg_wo[0x10];
+};
+
+/*  (READ/WRITE name, if split)  */
+const char *asc_reg_names[0x10] = {
+	"NCR_TCL", "NCR_TCM", "NCR_FIFO", "NCR_CMD",
+	"NCR_STAT/NCR_SELID", "NCR_INTR/NCR_TIMEOUT",
+	"NCR_STEP/NCR_SYNCTP", "NCR_FFLAG/NCR_SYNCOFF",
+	"NCR_CFG1", "NCR_CCF", "NCR_TEST", "NCR_CFG2",
+	"NCR_CFG3", "reg_0xd", "NCR_TCH", "reg_0xf"
+};
+
+
+/*  This is referenced below.  */
+static int dev_asc_select(struct cpu *cpu, struct asc_data *d, int from_id,
+	int to_id, int dmaflag, int n_messagebytes);
+
+
+DEVICE_TICK(asc)
+{
+	struct asc_data *d = (struct asc_data *) extra;
+	int new_assert = d->reg_ro[NCR_STAT] & NCRSTAT_INT;
+
+	if (new_assert && !d->irq_asserted)
+		INTERRUPT_ASSERT(d->irq);
+
+	d->irq_asserted = new_assert;
+}
+
+
+/*
+ *  dev_asc_fifo_flush():
+ *
+ *  Flush the fifo.
+ */
+static void dev_asc_fifo_flush(struct asc_data *d)
+{
+	d->fifo[0] = 0x00;
+	d->fifo_in = 0;
+	d->fifo_out = 0;
+	d->n_bytes_in_fifo = 0;
+}
+
+
+/*
+ *  dev_asc_reset():
+ *
+ *  Reset the state of the asc.
+ */
+static void dev_asc_reset(struct asc_data *d)
+{
+	d->cur_state = STATE_DISCONNECTED;
+	d->atn = 0;
+
+	if (d->xferp != NULL)
+		scsi_transfer_free(d->xferp);
+	d->xferp = NULL;
+
+	dev_asc_fifo_flush(d);
+
+	/*  According to table 4.1 in the LSI53CF92A manual:  */
+	memset(d->reg_wo, 0, sizeof(d->reg_wo));
+	d->reg_wo[NCR_TCH] = 0x94;
+	d->reg_wo[NCR_CCF] = 2;
+	memcpy(d->reg_ro, d->reg_wo, sizeof(d->reg_ro));
+	d->reg_wo[NCR_SYNCTP] = 5;
+}
+
+
+/*
+ *  dev_asc_fifo_read():
+ *
+ *  Read a byte from the asc FIFO.
+ */
+static int dev_asc_fifo_read(struct asc_data *d)
+{
+	int res = d->fifo[d->fifo_out];
+
+	if (d->fifo_in == d->fifo_out)
+		fatal("dev_asc: WARNING! FIFO overrun!\n");
+
+	d->fifo_out = (d->fifo_out + 1) % ASC_FIFO_LEN;
+	d->n_bytes_in_fifo --;
+
+	return res;
+}
+
+
+/*
+ *  dev_asc_fifo_write():
+ *
+ *  Write a byte to the asc FIFO.
+ */
+static void dev_asc_fifo_write(struct asc_data *d, unsigned char data)
+{
+	d->fifo[d->fifo_in] = data;
+	d->fifo_in = (d->fifo_in + 1) % ASC_FIFO_LEN;
+	d->n_bytes_in_fifo ++;
+
+	if (d->fifo_in == d->fifo_out)
+		fatal("dev_asc: WARNING! FIFO overrun on write!\n");
+}
+
+
+/*
+ *  dev_asc_newxfer():
+ *
+ *  Allocate memory for a new transfer.
+ */
+static void dev_asc_newxfer(struct asc_data *d)
+{
+	if (d->xferp != NULL) {
+		printf("WARNING! dev_asc_newxfer(): freeing previous"
+		    " transfer\n");
+		scsi_transfer_free(d->xferp);
+		d->xferp = NULL;
+	}
+
+	d->xferp = scsi_transfer_alloc();
+#if 0
+	d->xferp->get_data_out = dev_asc_get_data_out;
+	d->xferp->gdo_extra = (void *) d;
+#endif
+}
+
+
+/*
+ *  dev_asc_transfer():
+ *
+ *  Transfer data from a SCSI device to the controller (or vice versa),
+ *  depending on the current phase.
+ *
+ *  Returns 1 if ok, 0 on error.
+ */
+static int dev_asc_transfer(struct cpu *cpu, struct asc_data *d, int dmaflag)
+{
+	int res = 1, all_done = 1;
+	int len, i, ch;
+
+	if (!quiet_mode)
+		debug(" { TRANSFER to/from id %i: ", d->reg_wo[NCR_SELID] & 7);
+
+	if (d->cur_phase == PHASE_DATA_IN) {
+		/*  Data coming into the controller from external device:  */
+		if (!dmaflag) {
+			if (d->xferp->data_in == NULL) {
+				fatal("no incoming data?\n");
+				res = 0;
+			} else {
+/*  TODO  */
+fatal("TODO..............\n");
+				len = d->reg_wo[NCR_TCL] +
+				    d->reg_wo[NCR_TCM] * 256;
+
+				len--;
+				ch = d->incoming_data[d->incoming_data_addr];
+				debug(" %02x", ch);
+
+				d->incoming_data_addr ++;
+				dev_asc_fifo_write(d, ch);
+
+				if (len == 0) {
+					free(d->incoming_data);
+					d->incoming_data = NULL;
+				}
+
+				d->reg_ro[NCR_TCL] = len & 255;
+				d->reg_ro[NCR_TCM] = (len >> 8) & 255;
+			}
+		} else {
+			/*  Copy from the incoming data into dma memory:  */
+			if (d->xferp->data_in == NULL) {
+				fatal("no incoming DMA data?\n");
+				res = 0;
+			} else {
+				size_t lenIn = d->xferp->data_in_len;
+				size_t lenIn2 = d->reg_wo[NCR_TCL] +
+				    d->reg_wo[NCR_TCM] * 256;
+				if (lenIn2 == 0)
+					lenIn2 = 65536;
+
+                                if (lenIn < lenIn2) {
+                                        fatal("{ asc: data in, lenIn=%i lenIn2=%i "
+					    "}\n", lenIn, lenIn2);
+                                }
+
+				/*  TODO: check lenIn2 in a similar way?  */
+				if (lenIn + (d->dma_address_reg &
+				    (ASC_DMA_SIZE-1)) > ASC_DMA_SIZE)
+					lenIn = ASC_DMA_SIZE -
+					    (d->dma_address_reg &
+					    (ASC_DMA_SIZE-1));
+
+				if (lenIn2 > lenIn) {
+					memset(d->dma + (d->dma_address_reg &
+					    (ASC_DMA_SIZE-1)), 0, lenIn2);
+					lenIn2 = lenIn;
+				}
+
+#ifdef ASC_DEBUG
+				if (!quiet_mode) {
+					int i;
+					for (i=0; i<lenIn; i++)
+						debug(" %02x", d->xferp->
+						    data_in[i]);
+				}
+#endif
+
+				/*
+				 *  Are we using an external DMA controller?
+				 *  Then use it. Otherwise place the data in
+				 *  the DECstation 5000/200 built-in DMA
+				 *  region.
+				 */
+				if (d->dma_controller != NULL)
+					d->dma_controller(
+					    d->dma_controller_data,
+					    d->xferp->data_in,
+					    lenIn2, 1);
+				else
+					memcpy(d->dma + (d->dma_address_reg &
+					    (ASC_DMA_SIZE-1)),
+					    d->xferp->data_in, lenIn2);
+
+				if (d->xferp->data_in_len > lenIn2) {
+					unsigned char *n;
+
+if (d->dma_controller != NULL)
+	printf("WARNING!!!!!!!!! BUG!!!! Unexpected stuff..."
+	    "lenIn2=%i d->xferp->data_in_len=%i\n", (int)lenIn2,
+	    (int)d->xferp->data_in_len);
+
+					all_done = 0;
+					/*  fatal("{ asc: multi-transfer"
+					    " data_in, lenIn=%i lenIn2=%i }\n",
+					    (int)lenIn, (int)lenIn2);  */
+
+					d->xferp->data_in_len -= lenIn2;
+					CHECK_ALLOCATION(n = (unsigned char *)
+					    malloc(d->xferp->data_in_len));
+					memcpy(n, d->xferp->data_in + lenIn2,
+					    d->xferp->data_in_len);
+					free(d->xferp->data_in);
+					d->xferp->data_in = n;
+
+					lenIn = lenIn2;
+				}
+
+				lenIn = 0;
+
+				d->reg_ro[NCR_TCL] = lenIn & 255;
+				d->reg_ro[NCR_TCM] = (lenIn >> 8) & 255;
+
+				/*  Successful DMA transfer:  */
+				d->reg_ro[NCR_STAT] |= NCRSTAT_TC;
+			}
+		}
+	} else if (d->cur_phase == PHASE_DATA_OUT) {
+		/*  Data going from the controller to an external device:  */
+		if (!dmaflag) {
+fatal("TODO.......asdgasin\n");
+		} else {
+			/*  Copy data from DMA to data_out:  */
+			int len2 = d->reg_wo[NCR_TCL] +
+			    d->reg_wo[NCR_TCM] * 256;
+			len = d->xferp->data_out_len;
+
+			if (len2 == 0)
+				len2 = 65536;
+
+			if (len == 0) {
+				fprintf(stderr, "d->xferp->data_out_len == "
+				    "0 ?\n");
+				exit(1);
+			}
+
+			/*  TODO: Make sure that len2 doesn't go outside
+			    of the dma memory?  */
+
+			/*  fatal("    data out offset=%5i len=%5i\n",
+			    d->xferp->data_out_offset, len2);  */
+
+			if (d->xferp->data_out_offset + len2 >
+			    d->xferp->data_out_len) {
+				len2 = d->xferp->data_out_len -
+				    d->xferp->data_out_offset;
+			}
+
+			/*
+			 *  Are we using an external DMA controller? Then use
+			 *  it. Otherwise place the data in the DECstation
+			 *  5000/200 built-in DMA region.
+			 */
+			if (d->xferp->data_out == NULL) {
+				scsi_transfer_allocbuf(&d->xferp->data_out_len,
+				    &d->xferp->data_out, len, 0);
+
+				if (d->dma_controller != NULL)
+					d->dma_controller(
+					    d->dma_controller_data,
+					    d->xferp->data_out,
+					    len2, 0);
+				else
+					memcpy(d->xferp->data_out,
+					    d->dma + (d->dma_address_reg &
+					    (ASC_DMA_SIZE-1)), len2);
+				d->xferp->data_out_offset = len2;
+			} else {
+				/*  Continuing a multi-transfer:  */
+				if (d->dma_controller != NULL)
+					d->dma_controller(
+					    d->dma_controller_data,
+					    d->xferp->data_out +
+						d->xferp->data_out_offset,
+					    len2, 0);
+				else
+					memcpy(d->xferp->data_out +
+					    d->xferp->data_out_offset,
+					    d->dma + (d->dma_address_reg &
+					    (ASC_DMA_SIZE-1)), len2);
+				d->xferp->data_out_offset += len2;
+			}
+
+			/*  If the disk wants more than we're DMAing,
+			    then this is a multitransfer:  */
+			if (d->xferp->data_out_offset !=
+			    d->xferp->data_out_len) {
+				if (!quiet_mode)
+					debug("[ asc: data_out, multitransfer "
+					    "len = %i, len2 = %i ]\n",
+					    (int)len, (int)len2);
+				if (d->xferp->data_out_offset >
+				    d->xferp->data_out_len)
+					fatal("[ asc data_out dma: too much?"
+					    " ]\n");
+				else
+					all_done = 0;
+			}
+
+#ifdef ASC_DEBUG
+			if (!quiet_mode) {
+				int i;
+				for (i=0; i<len; i++)
+					debug(" %02x", d->xferp->data_out[i]);
+			}
+#endif
+			len = 0;
+
+			d->reg_ro[NCR_TCL] = len & 255;
+			d->reg_ro[NCR_TCM] = (len >> 8) & 255;
+
+			/*  Successful DMA transfer:  */
+			d->reg_ro[NCR_STAT] |= NCRSTAT_TC;
+		}
+	} else if (d->cur_phase == PHASE_MSG_OUT) {
+		if (!quiet_mode)
+			debug("MSG OUT: ");
+		/*  Data going from the controller to an external device:  */
+		if (!dmaflag) {
+			/*  There should already be one byte in msg_out, so we
+			    just extend the message:  */
+			int oldlen = d->xferp->msg_out_len;
+			int newlen;
+
+			if (oldlen != 1) {
+				fatal(" (PHASE OUT MSG len == %i, "
+				    "should be 1)\n", oldlen);
+			}
+
+			newlen = oldlen + d->n_bytes_in_fifo;
+			CHECK_ALLOCATION(d->xferp->msg_out = (unsigned char *)
+			    realloc(d->xferp->msg_out, newlen));
+			d->xferp->msg_out_len = newlen;
+
+			i = oldlen;
+			while (d->fifo_in != d->fifo_out) {
+				ch = dev_asc_fifo_read(d);
+				d->xferp->msg_out[i++] = ch;
+#ifdef ASC_DEBUG
+				debug("0x%02x ", ch);
+#endif
+			}
+
+#ifdef MACH
+			/*  Super-ugly hack for Mach/PMAX:  TODO: make nicer  */
+			if (d->xferp->msg_out_len == 6 &&
+			    (d->xferp->msg_out[0] == 0x80 ||
+			     d->xferp->msg_out[0] == 0xc0) &&
+			    d->xferp->msg_out[1] == 0x01 &&
+			    d->xferp->msg_out[2] == 0x03 &&
+			    d->xferp->msg_out[3] == 0x01 &&
+			    d->xferp->msg_out[4] == 0x32 &&
+			    d->xferp->msg_out[5] == 0x0f) {
+				fatal(" !! Mach/PMAX hack !! ");
+				all_done = 0;
+				d->cur_phase = PHASE_MSG_IN;
+			}
+#endif
+		} else {
+			/*  Copy data from DMA to msg_out:  */
+			fatal("[ DMA MSG OUT: xxx TODO! ]");
+			/*  TODO  */
+			res = 0;
+		}
+	} else if (d->cur_phase == PHASE_MSG_IN) {
+		if (!quiet_mode)
+			debug(" MSG IN");
+		fatal("[ MACH HACK! ]");
+		/*  Super-ugly hack for Mach/PMAX:  TODO: make nicer  */
+		dev_asc_fifo_write(d, 0x07);
+		d->cur_phase = PHASE_COMMAND;
+		all_done = 0;
+	} else if (d->cur_phase == PHASE_COMMAND) {
+		if (!quiet_mode)
+			debug(" COMMAND ==> select ");
+		res = dev_asc_select(cpu, d, d->reg_ro[NCR_CFG1] & 7,
+		    d->reg_wo[NCR_SELID] & 7, dmaflag, 0);
+		return res;
+	} else {
+		fatal("!!! TODO: unknown/unimplemented phase "
+		    "in transfer: %i\n", d->cur_phase);
+	}
+
+	/*  Redo the command if data was just sent using DATA_OUT:  */
+	if (d->cur_phase == PHASE_DATA_OUT) {
+		res = diskimage_scsicommand(cpu, d->reg_wo[NCR_SELID] & 7,
+		    DISKIMAGE_SCSI, d->xferp);
+	}
+
+	if (all_done) {
+		if (d->cur_phase == PHASE_MSG_OUT)
+			d->cur_phase = PHASE_COMMAND;
+		else
+			d->cur_phase = PHASE_STATUS;
+	}
+
+	/*
+	 *  Cause an interrupt after the transfer:
+	 *
+	 *  NOTE:  Earlier I had this in here as well:
+	 *	d->reg_ro[NCR_INTR] |= NCRINTR_FC;
+	 *  but Linux/DECstation and OpenBSD/pmax seems to choke on that.
+	 */
+	d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
+	d->reg_ro[NCR_INTR] |= NCRINTR_BS;
+	d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | d->cur_phase;
+	d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | 4;	/*  4?  */
+
+	if (!quiet_mode)
+		debug("}");
+	return res;
+}
+
+
+/*
+ *  dev_asc_select():
+ *
+ *  Select a SCSI device, send msg bytes (if any), and send command bytes.
+ *  (Call diskimage_scsicommand() to handle the command.)
+ *
+ *  Return value: 1 if ok, 0 on error.
+ */
+static int dev_asc_select(struct cpu *cpu, struct asc_data *d, int from_id,
+	int to_id, int dmaflag, int n_messagebytes)
+{
+	int ok, len, i, ch;
+
+	if (!quiet_mode)
+		debug(" { SELECT id %i: ", to_id);
+
+	/*
+	 *  Message bytes, if any:
+	 */
+	if (!quiet_mode)
+		debug("msg:");
+
+	if (n_messagebytes > 0) {
+		scsi_transfer_allocbuf(&d->xferp->msg_out_len,
+		    &d->xferp->msg_out, n_messagebytes, 0);
+
+		i = 0;
+		while (n_messagebytes-- > 0) {
+			int ch2 = dev_asc_fifo_read(d);
+			if (!quiet_mode)
+				debug(" %02x", ch2);
+			d->xferp->msg_out[i++] = ch2;
+		}
+
+		if ((d->xferp->msg_out[0] & 0x7) != 0x00) {
+			debug(" (LUNs not implemented yet: 0x%02x) }",
+			    d->xferp->msg_out[0]);
+			return 0;
+		}
+
+		if (((d->xferp->msg_out[0] & ~0x7) != 0xc0) &&
+		    ((d->xferp->msg_out[0] & ~0x7) != 0x80)) {
+			fatal(" (Unimplemented msg out: 0x%02x) }",
+			    d->xferp->msg_out[0]);
+			return 0;
+		}
+
+		if (d->xferp->msg_out_len > 1) {
+			fatal(" (Long msg out, not implemented yet;"
+			    " len=%i) }", d->xferp->msg_out_len);
+			return 0;
+		}
+	} else {
+		if (!quiet_mode)
+			debug(" none");
+	}
+
+	/*  Special case: SELATNS (with STOP sequence):  */
+	if (d->cur_phase == PHASE_MSG_OUT) {
+		if (!quiet_mode)
+			debug(" MSG OUT DEBUG");
+		if (d->xferp->msg_out_len != 1) {
+			fatal(" (SELATNS: msg out len == %i, should be 1)",
+			    d->xferp->msg_out_len);
+			return 0;
+		}
+
+/* d->cur_phase = PHASE_COMMAND; */
+
+		/*  According to the LSI manual:  */
+		d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
+		d->reg_ro[NCR_INTR] |= NCRINTR_FC;
+		d->reg_ro[NCR_INTR] |= NCRINTR_BS;
+		d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | d->cur_phase;
+		d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | 1;
+
+		if (!quiet_mode)
+			debug("}");
+		return 1;
+	}
+
+	/*
+	 *  Command bytes:
+	 */
+	if (!quiet_mode)
+		debug(", cmd: ");
+
+	if (!dmaflag) {
+		if (!quiet_mode)
+			debug("[non-DMA] ");
+
+		scsi_transfer_allocbuf(&d->xferp->cmd_len,
+		    &d->xferp->cmd, d->n_bytes_in_fifo, 0);
+
+		i = 0;
+		while (d->fifo_in != d->fifo_out) {
+			ch = dev_asc_fifo_read(d);
+			d->xferp->cmd[i++] = ch;
+			if (!quiet_mode)
+				debug("%02x ", ch);
+		}
+	} else {
+		if (!quiet_mode)
+			debug("[DMA] ");
+		len = d->reg_wo[NCR_TCL] + d->reg_wo[NCR_TCM] * 256;
+		if (len == 0)
+			len = 65536;
+
+		scsi_transfer_allocbuf(&d->xferp->cmd_len,
+		    &d->xferp->cmd, len, 0);
+
+		for (i=0; i<len; i++) {
+			int ofs = d->dma_address_reg + i;
+			ch = d->dma[ofs & (ASC_DMA_SIZE-1)];
+			d->xferp->cmd[i] = ch;
+			if (!quiet_mode)
+				debug("%02x ", ch);
+		}
+
+		d->reg_ro[NCR_TCL] = len & 255;
+		d->reg_ro[NCR_TCM] = (len >> 8) & 255;
+
+		d->reg_ro[NCR_STAT] |= NCRSTAT_TC;
+	}
+
+	/*
+	 *  Call the SCSI device to perform the command:
+	 */
+	ok = diskimage_scsicommand(cpu, to_id, DISKIMAGE_SCSI, d->xferp);
+
+
+	/*  Cause an interrupt:  */
+	d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
+	d->reg_ro[NCR_INTR] |= NCRINTR_FC;
+	d->reg_ro[NCR_INTR] |= NCRINTR_BS;
+
+	if (ok == 2)
+		d->cur_phase = PHASE_DATA_OUT;
+	else if (d->xferp->data_in != NULL)
+		d->cur_phase = PHASE_DATA_IN;
+	else
+		d->cur_phase = PHASE_STATUS;
+
+	d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | d->cur_phase;
+	d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | 4;	/*  DONE (?)  */
+
+	if (!quiet_mode)
+		debug("}");
+
+	return ok;
+}
+
+
+DEVICE_ACCESS(asc_address_reg)
+{
+	struct asc_data *d = (struct asc_data *) extra;
+
+	if (relative_addr + len > 4)
+		return 0;
+
+	if (writeflag==MEM_READ) {
+		memcpy(data, d->dma_address_reg_memory + relative_addr, len);
+	} else {
+		memcpy(d->dma_address_reg_memory + relative_addr, data, len);
+	}
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(asc_dma)
+{
+	struct asc_data *d = (struct asc_data *) extra;
+
+	if (writeflag==MEM_READ) {
+		memcpy(data, d->dma + relative_addr, len);
+#ifdef ASC_DEBUG
+		{
+			int i;
+			debug("[ asc: read from DMA addr 0x%05x:",
+			    (int) relative_addr);
+			for (i=0; i<len; i++)
+				debug(" %02x", data[i]);
+			debug(" ]\n");
+		}
+#endif
+
+		/*  Don't return the common way, as that
+		    would overwrite data.  */
+		return 1;
+	} else {
+		memcpy(d->dma + relative_addr, data, len);
+#ifdef ASC_DEBUG
+		{
+			int i;
+			debug("[ asc: write to  DMA addr 0x%05x:",
+			    (int) relative_addr);
+			for (i=0; i<len; i++)
+				debug(" %02x", data[i]);
+			debug(" ]\n");
+		}
+#endif
+		/*  Quick return.  */
+		return 1;
+	}
+}
+
+
+DEVICE_ACCESS(asc)
+{
+	int regnr;
+	struct asc_data *d = (struct asc_data *) extra;
+	int target_exists;
+	int n_messagebytes = 0;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+#if 0
+	/*  Debug stuff useful when trying to make dev_asc compatible
+	    with the 'arc' emulation mode, which is different from
+	    the DECstation mode.  */
+	fatal("[ asc: writeflag=%i addr=%08x idata=%016llx ]\n",
+	    writeflag, (int)relative_addr, (long long)idata);
+#endif
+
+	switch (d->mode) {
+	case DEV_ASC_DEC:
+		regnr = relative_addr / 4;
+		break;
+	case DEV_ASC_PICA:
+	default:
+		regnr = relative_addr;
+	}
+
+	/*  Controller's ID is fixed:  */
+	d->reg_ro[NCR_CFG1] = (d->reg_ro[NCR_CFG1] & ~7) | ASC_SCSI_ID;
+
+	d->reg_ro[NCR_FFLAG] = ((d->reg_ro[NCR_STEP] & 0x7) << 5)
+	    + d->n_bytes_in_fifo;
+
+	d->dma_address_reg =
+	    d->dma_address_reg_memory[0] +
+	    (d->dma_address_reg_memory[1] << 8) +
+	    (d->dma_address_reg_memory[2] << 16) +
+	    (d->dma_address_reg_memory[3] << 24);
+
+	if (regnr < 0x10) {
+		if (regnr == NCR_FIFO) {
+			if (writeflag == MEM_WRITE)
+				dev_asc_fifo_write(d, idata);
+			else
+				odata = dev_asc_fifo_read(d);
+		} else {
+			if (writeflag==MEM_WRITE)
+				d->reg_wo[regnr] = idata;
+			else
+				odata = d->reg_ro[regnr];
+		}
+
+#ifdef ASC_FULL_REGISTER_ACCESS_DEBUG
+		if (!quiet_mode) {
+			if (writeflag==MEM_READ) {
+				debug("[ asc: read from %s: 0x%02x",
+				    asc_reg_names[regnr], (int)odata);
+			} else {
+				debug("[ asc: write to  %s: 0x%02x",
+				    asc_reg_names[regnr], (int)idata);
+			}
+		}
+#endif
+	} else if (relative_addr >= 0x300 && relative_addr < 0x600
+	    && d->turbochannel != NULL) {
+		debug("[ asc: offset 0x%x, redirecting to turbochannel"
+		    " access ]\n", relative_addr);
+		return dev_turbochannel_access(cpu, mem,
+		    relative_addr, data, len, writeflag,
+		    d->turbochannel);
+	} else {
+		if (writeflag==MEM_READ) {
+			fatal("[ asc: read from 0x%04x: 0x%02x ]\n",
+			    relative_addr, (int)odata);
+		} else {
+			fatal("[ asc: write to  0x%04x: 0x%02x ]\n",
+			    relative_addr, (int)idata);
+		}
+	}
+
+	/*
+	 *  Some registers are read/write. Copy contents of
+	 *  reg_wo to reg_ro:
+	 */
+#if 0
+	d->reg_ro[ 0] = d->reg_wo[0];	/*  Transfer count lo and  */
+	d->reg_ro[ 1] = d->reg_wo[1];	/*  middle  */
+#endif
+	d->reg_ro[ 2] = d->reg_wo[2];
+	d->reg_ro[ 3] = d->reg_wo[3];
+	d->reg_ro[ 8] = d->reg_wo[8];
+	d->reg_ro[ 9] = d->reg_wo[9];
+	d->reg_ro[10] = d->reg_wo[10];
+	d->reg_ro[11] = d->reg_wo[11];
+	d->reg_ro[12] = d->reg_wo[12];
+
+	if (regnr == NCR_CMD && writeflag == MEM_WRITE) {
+		if (!quiet_mode)
+			debug(" ");
+
+		/*  TODO:  Perhaps turn off others here too?  */
+		d->reg_ro[NCR_INTR] &= ~NCRINTR_SBR;
+
+		if (idata & NCRCMD_DMA) {
+			if (!quiet_mode)
+				debug("[DMA] ");
+
+			/*
+			 *  DMA commands load the transfer count from the
+			 *  write-only registers to the read-only ones, and
+			 *  the Terminal Count bit is cleared.
+			 */
+			d->reg_ro[NCR_TCL] = d->reg_wo[NCR_TCL];
+			d->reg_ro[NCR_TCM] = d->reg_wo[NCR_TCM];
+			d->reg_ro[NCR_TCH] = d->reg_wo[NCR_TCH];
+			d->reg_ro[NCR_STAT] &= ~NCRSTAT_TC;
+		}
+
+		switch (idata & ~NCRCMD_DMA) {
+
+		case NCRCMD_NOP:
+			if (!quiet_mode)
+				debug("NOP");
+			break;
+
+		case NCRCMD_FLUSH:
+			if (!quiet_mode)
+				debug("FLUSH");
+			/*  Flush the FIFO:  */
+			dev_asc_fifo_flush(d);
+			break;
+
+		case NCRCMD_RSTCHIP:
+			if (!quiet_mode)
+				debug("RSTCHIP");
+			/*  Hardware reset.  */
+			dev_asc_reset(d);
+			break;
+
+		case NCRCMD_RSTSCSI:
+			if (!quiet_mode)
+				debug("RSTSCSI");
+			/*  No interrupt if interrupts are disabled.  */
+			if (!(d->reg_wo[NCR_CFG1] & NCRCFG1_SRR))
+				d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
+			d->reg_ro[NCR_INTR] |= NCRINTR_SBR;
+			d->reg_ro[NCR_INTR] |= NCRINTR_FC;
+			d->cur_state = STATE_DISCONNECTED;
+			break;
+
+		case NCRCMD_ENSEL:
+			if (!quiet_mode)
+				debug("ENSEL");
+			/*  TODO  */
+			break;
+
+		case NCRCMD_ICCS:
+			if (!quiet_mode)
+				debug("ICCS");
+			/*  Reveice a status byte + a message byte.  */
+
+			/*  TODO: how about other status and message bytes?  */
+			if (d->xferp != NULL && d->xferp->status != NULL)
+				dev_asc_fifo_write(d, d->xferp->status[0]);
+			else
+				dev_asc_fifo_write(d, 0x00);
+
+			if (d->xferp != NULL && d->xferp->msg_in != NULL)
+				dev_asc_fifo_write(d, d->xferp->msg_in[0]);
+			else
+				dev_asc_fifo_write(d, 0x00);
+
+			d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
+			d->reg_ro[NCR_INTR] |= NCRINTR_FC;
+/*			d->reg_ro[NCR_INTR] |= NCRINTR_BS; */
+			d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | 7;
+				/*  ? probably 7  */
+			d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | 4;
+				/*  ?  */
+			break;
+
+		case NCRCMD_MSGOK:
+			/*  Message is being Rejected if ATN is set,
+			    otherwise Accepted.  */
+			if (!quiet_mode) {
+				debug("MSGOK");
+				if (d->atn)
+					debug("; Rejecting message");
+				else
+					debug("; Accepting message");
+			}
+			d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
+			d->reg_ro[NCR_INTR] |= NCRINTR_DIS;
+
+			d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) |
+			    d->cur_phase;	/*  6?  */
+			d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) |
+			    4;	/*  ?  */
+
+			d->cur_state = STATE_DISCONNECTED;
+
+			if (d->xferp != NULL)
+				scsi_transfer_free(d->xferp);
+			d->xferp = NULL;
+			break;
+
+		case NCRCMD_SETATN:
+			if (!quiet_mode)
+				debug("SETATN");
+			d->atn = 1;
+			break;
+
+		case NCRCMD_RSTATN:
+			if (!quiet_mode)
+				debug("RSTATN");
+			d->atn = 0;
+			break;
+
+		case NCRCMD_SELNATN:
+		case NCRCMD_SELATN:
+		case NCRCMD_SELATNS:
+		case NCRCMD_SELATN3:
+			d->cur_phase = PHASE_COMMAND;
+			switch (idata & ~NCRCMD_DMA) {
+			case NCRCMD_SELATN:
+			case NCRCMD_SELATNS:
+				if ((idata & ~NCRCMD_DMA) == NCRCMD_SELATNS) {
+					if (!quiet_mode)
+						debug("SELATNS: select with "
+						    "atn and stop, id %i",
+						    d->reg_wo[NCR_SELID] & 7);
+					d->cur_phase = PHASE_MSG_OUT;
+				} else {
+					if (!quiet_mode)
+						debug("SELATN: select with atn"
+						    ", id %i",
+						    d->reg_wo[NCR_SELID] & 7);
+				}
+				n_messagebytes = 1;
+				break;
+			case NCRCMD_SELATN3:
+				if (!quiet_mode)
+					debug("SELNATN: select with atn3, "
+					    "id %i", d->reg_wo[NCR_SELID] & 7);
+				n_messagebytes = 3;
+				break;
+			case NCRCMD_SELNATN:
+				if (!quiet_mode)
+					debug("SELNATN: select without atn, "
+					    "id %i", d->reg_wo[NCR_SELID] & 7);
+				n_messagebytes = 0;
+			}
+
+			/*  TODO: not just disk, but some generic
+			    SCSI device  */
+			target_exists = diskimage_exist(cpu->machine,
+			    d->reg_wo[NCR_SELID] & 7, DISKIMAGE_SCSI);
+
+			if (target_exists) {
+				/*
+				 *  Select a SCSI device, send message bytes
+				 *  (if any) and command bytes to the target.
+				 */
+				int ok;
+
+				dev_asc_newxfer(d);
+
+				ok = dev_asc_select(cpu, d,
+				    d->reg_ro[NCR_CFG1] & 7,
+				    d->reg_wo[NCR_SELID] & 7,
+				    idata & NCRCMD_DMA? 1 : 0,
+				    n_messagebytes);
+
+				if (ok)
+					d->cur_state = STATE_INITIATOR;
+				else {
+					d->cur_state = STATE_DISCONNECTED;
+					d->reg_ro[NCR_INTR] |= NCRINTR_DIS;
+					d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
+					d->reg_ro[NCR_STEP] =
+					    (d->reg_ro[NCR_STEP] & ~7) | 0;
+					if (d->xferp != NULL)
+						scsi_transfer_free(d->xferp);
+					d->xferp = NULL;
+				}
+			} else {
+				/*
+				 *  Selection failed, non-existant scsi ID:
+				 *
+				 *  This is good enough to fool Ultrix, NetBSD,
+				 *  OpenBSD and Linux to continue detection of
+				 *  other IDs, without giving any warnings.
+				 */
+				d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
+				d->reg_ro[NCR_INTR] |= NCRINTR_DIS;
+				d->reg_ro[NCR_STEP] &= ~7;
+				d->reg_ro[NCR_STEP] |= 0;
+				dev_asc_fifo_flush(d);
+				d->cur_state = STATE_DISCONNECTED;
+			}
+			break;
+
+		case NCRCMD_TRPAD:
+			if (!quiet_mode)
+				debug("TRPAD");
+
+			dev_asc_newxfer(d);
+			{
+				int ok;
+
+				ok = dev_asc_transfer(cpu, d,
+				    idata & NCRCMD_DMA? 1 : 0);
+				if (!ok) {
+					d->cur_state = STATE_DISCONNECTED;
+					d->reg_ro[NCR_INTR] |= NCRINTR_DIS;
+					d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
+					d->reg_ro[NCR_STEP] = (d->reg_ro[
+					    NCR_STEP] & ~7) | 0;
+					if (d->xferp != NULL)
+						scsi_transfer_free(d->xferp);
+					d->xferp = NULL;
+				}
+			}
+break;
+
+/*  Old code which didn't work with Mach:  */
+#if 0
+			d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
+			d->reg_ro[NCR_INTR] |= NCRINTR_BS;
+			d->reg_ro[NCR_INTR] |= NCRINTR_FC;
+			d->reg_ro[NCR_STAT] |= NCRSTAT_TC;
+
+			d->reg_ro[NCR_TCL] = 0;
+			d->reg_ro[NCR_TCM] = 0;
+
+			d->reg_ro[NCR_STEP] &= ~7;
+#if 0
+			d->reg_ro[NCR_STEP] |= 0;
+			dev_asc_fifo_flush(d);
+#else
+			d->reg_ro[NCR_STEP] |= 4;
+#endif
+			break;
+#endif
+
+		case NCRCMD_TRANS:
+			if (!quiet_mode)
+				debug("TRANS");
+
+			{
+				int ok;
+
+				ok = dev_asc_transfer(cpu, d,
+				    idata & NCRCMD_DMA? 1 : 0);
+				if (!ok) {
+					d->cur_state = STATE_DISCONNECTED;
+					d->reg_ro[NCR_INTR] |= NCRINTR_DIS;
+					d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
+					d->reg_ro[NCR_STEP] = (d->reg_ro[
+					    NCR_STEP] & ~7) | 0;
+					if (d->xferp != NULL)
+						scsi_transfer_free(d->xferp);
+					d->xferp = NULL;
+				}
+			}
+			break;
+
+		default:
+			fatal("(unimplemented asc cmd 0x%02x)", (int)idata);
+			d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
+			d->reg_ro[NCR_INTR] |= NCRINTR_ILL;
+			/*
+			 *  TODO:  exit or continue with Illegal command
+			 *  interrupt?
+			 */
+			exit(1);
+		}
+	}
+
+	if (regnr == NCR_INTR && writeflag == MEM_READ) {
+		/*
+		 *  Reading the interrupt register de-asserts the
+		 *  interrupt pin.  Also, INTR, STEP, and STAT are all
+		 *  cleared, according to page 64 of the LSI53CF92A manual,
+		 *  if "interrupt output is true".
+		 */
+		if (d->reg_ro[NCR_STAT] & NCRSTAT_INT) {
+			d->reg_ro[NCR_INTR] = 0;
+			d->reg_ro[NCR_STEP] = 0;
+			d->reg_ro[NCR_STAT] = 0;
+
+			/*  For Mach/PMAX? TODO  */
+			d->reg_ro[NCR_STAT] = PHASE_COMMAND;
+		}
+
+		INTERRUPT_DEASSERT(d->irq);
+		d->irq_asserted = 0;
+	}
+
+	if (regnr == NCR_CFG1) {
+		/*  TODO: other bits  */
+		if (!quiet_mode) {
+			debug(" parity %s,", d->reg_ro[regnr] &
+			    NCRCFG1_PARENB? "enabled" : "disabled");
+			debug(" scsi_id %i", d->reg_ro[regnr] & 0x7);
+		}
+	}
+
+#ifdef ASC_FULL_REGISTER_ACCESS_DEBUG
+	debug(" ]\n");
+#endif
+	dev_asc_tick(cpu, extra);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_asc_init():
+ *
+ *  Register an 'asc' device.
+ */
+void dev_asc_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, const char *irq_path, void *turbochannel, int mode,
+	size_t (*dma_controller)(void *dma_controller_data,
+		unsigned char *data, size_t len, int writeflag),
+	void *dma_controller_data)
+{
+	struct asc_data *d;
+
+	CHECK_ALLOCATION(d = (struct asc_data *) malloc(sizeof(struct asc_data)));
+	memset(d, 0, sizeof(struct asc_data));
+
+	INTERRUPT_CONNECT(irq_path, d->irq);
+	d->turbochannel = turbochannel;
+	d->mode         = mode;
+
+	d->reg_ro[NCR_CFG3] = NCRF9XCFG3_CDB;
+
+	CHECK_ALLOCATION(d->dma_address_reg_memory = (unsigned char *)
+	    malloc(machine->arch_pagesize));
+	memset(d->dma_address_reg_memory, 0, machine->arch_pagesize);
+
+	CHECK_ALLOCATION(d->dma = (unsigned char *) malloc(ASC_DMA_SIZE));
+	memset(d->dma, 0, ASC_DMA_SIZE);
+
+	d->dma_controller      = dma_controller;
+	d->dma_controller_data = dma_controller_data;
+
+	memory_device_register(mem, "asc", baseaddr,
+	    mode == DEV_ASC_PICA? DEV_ASC_PICA_LENGTH : DEV_ASC_DEC_LENGTH,
+	    dev_asc_access, d, DM_DEFAULT, NULL);
+
+	if (mode == DEV_ASC_DEC) {
+		memory_device_register(mem, "asc_dma_address_reg",
+		    baseaddr + 0x40000, 4096, dev_asc_address_reg_access, d,
+		    DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK,
+		    (unsigned char *)&d->dma_address_reg_memory[0]);
+		memory_device_register(mem, "asc_dma", baseaddr + 0x80000,
+		    ASC_DMA_SIZE, dev_asc_dma_access, d,
+		    DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK, d->dma);
+	}
+
+	machine_add_tickfunction(machine, dev_asc_tick, d, ASC_TICK_SHIFT);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_asc.cc gxemul-0.7.0+dfsg/src/devices/dev_asc.cc
--- gxemul-0.6.2/src/devices/dev_asc.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_asc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1269 +0,0 @@
-/*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: NCR53C9X "ASC" SCSI controller
- *
- *  This is the SCSI controller used in some DECstation/DECsystem models and
- *  the PICA-61 machine.
- *
- *  Supposed to support SCSI-1 and SCSI-2. I've not yet found any docs
- *  on NCR53C9X, so I'll try to implement this device from LSI53CF92A docs
- *  instead.
- *
- *
- *  Memory layout on DECstation:
- *
- *	NCR53C94 registers	at base + 0
- *	DMA address register	at base + 0x40000
- *	128K SRAM buffer	at base + 0x80000
- *	ROM			at base + 0xc0000
- *
- *  Memory layout on PICA-61:
- *
- *	I haven't had time to look this up yet, but length = 0x1000.
- *
- *
- *  TODO:  This module needs a clean-up, and some testing to see that
- *         it works will all OSes that might use it (NetBSD, OpenBSD,
- *         Ultrix, Linux, Mach, OSF/1, Sprite, ...)
- *
- *	   Running Linux/DECstation 2.4.26 with no scsi disks attached causes
- *	   a warning message to be printed by Linux. (Whether this is a bug,
- *	   is is the way it works on real hardware, I don't know.)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "devices.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/ncr53c9xreg.h"
-
-
-/*  #define ASC_DEBUG  */
-/*  #define debug fatal  */
-/*  #define ASC_FULL_REGISTER_ACCESS_DEBUG  */
-/*  static int quiet_mode = 0;  */
-
-#define	ASC_TICK_SHIFT		15
-
-extern int quiet_mode;
-
-
-#define	ASC_FIFO_LEN		16
-#define	STATE_DISCONNECTED	0
-#define	STATE_INITIATOR		1
-#define	STATE_TARGET		2
-
-#define	PHASE_DATA_OUT		0
-#define	PHASE_DATA_IN		1
-#define	PHASE_COMMAND		2
-#define	PHASE_STATUS		3
-#define	PHASE_MSG_OUT		6
-#define	PHASE_MSG_IN		7
-
-
-/*  The controller's SCSI id:  */
-#define	ASC_SCSI_ID		7
-
-#define	ASC_DMA_SIZE		(128*1024)
-
-struct asc_data {
-	int		mode;
-
-	void		*turbochannel;
-	struct interrupt irq;
-	int		irq_asserted;
-
-	/*  Current state and transfer:  */
-	int		cur_state;
-	int		cur_phase;
-	struct scsi_transfer *xferp;
-
-	/*  FIFO:  */
-	unsigned char	fifo[ASC_FIFO_LEN];
-	int		fifo_in;
-	int		fifo_out;
-	int		n_bytes_in_fifo;		/*  cached  */
-
-	/*  ATN signal:  */
-	int		atn;
-
-	/*  Incoming dma data:  */
-	unsigned char	*incoming_data;
-	int		incoming_len;
-	int		incoming_data_addr;
-
-	/*  Built-in DMA memory (for DECstation 5000/200):  */
-	uint32_t	dma_address_reg;
-	unsigned char	*dma_address_reg_memory;
-	unsigned char	*dma;
-
-	void		*dma_controller_data;
-	size_t		(*dma_controller)(void *dma_controller_data,
-			    unsigned char *data, size_t len, int writeflag);
-
-	/*  Read registers and write registers:  */
-	uint32_t	reg_ro[0x10];
-	uint32_t	reg_wo[0x10];
-};
-
-/*  (READ/WRITE name, if split)  */
-const char *asc_reg_names[0x10] = {
-	"NCR_TCL", "NCR_TCM", "NCR_FIFO", "NCR_CMD",
-	"NCR_STAT/NCR_SELID", "NCR_INTR/NCR_TIMEOUT",
-	"NCR_STEP/NCR_SYNCTP", "NCR_FFLAG/NCR_SYNCOFF",
-	"NCR_CFG1", "NCR_CCF", "NCR_TEST", "NCR_CFG2",
-	"NCR_CFG3", "reg_0xd", "NCR_TCH", "reg_0xf"
-};
-
-
-/*  This is referenced below.  */
-static int dev_asc_select(struct cpu *cpu, struct asc_data *d, int from_id,
-	int to_id, int dmaflag, int n_messagebytes);
-
-
-DEVICE_TICK(asc)
-{
-	struct asc_data *d = (struct asc_data *) extra;
-	int new_assert = d->reg_ro[NCR_STAT] & NCRSTAT_INT;
-
-	if (new_assert && !d->irq_asserted)
-		INTERRUPT_ASSERT(d->irq);
-
-	d->irq_asserted = new_assert;
-}
-
-
-/*
- *  dev_asc_fifo_flush():
- *
- *  Flush the fifo.
- */
-static void dev_asc_fifo_flush(struct asc_data *d)
-{
-	d->fifo[0] = 0x00;
-	d->fifo_in = 0;
-	d->fifo_out = 0;
-	d->n_bytes_in_fifo = 0;
-}
-
-
-/*
- *  dev_asc_reset():
- *
- *  Reset the state of the asc.
- */
-static void dev_asc_reset(struct asc_data *d)
-{
-	d->cur_state = STATE_DISCONNECTED;
-	d->atn = 0;
-
-	if (d->xferp != NULL)
-		scsi_transfer_free(d->xferp);
-	d->xferp = NULL;
-
-	dev_asc_fifo_flush(d);
-
-	/*  According to table 4.1 in the LSI53CF92A manual:  */
-	memset(d->reg_wo, 0, sizeof(d->reg_wo));
-	d->reg_wo[NCR_TCH] = 0x94;
-	d->reg_wo[NCR_CCF] = 2;
-	memcpy(d->reg_ro, d->reg_wo, sizeof(d->reg_ro));
-	d->reg_wo[NCR_SYNCTP] = 5;
-}
-
-
-/*
- *  dev_asc_fifo_read():
- *
- *  Read a byte from the asc FIFO.
- */
-static int dev_asc_fifo_read(struct asc_data *d)
-{
-	int res = d->fifo[d->fifo_out];
-
-	if (d->fifo_in == d->fifo_out)
-		fatal("dev_asc: WARNING! FIFO overrun!\n");
-
-	d->fifo_out = (d->fifo_out + 1) % ASC_FIFO_LEN;
-	d->n_bytes_in_fifo --;
-
-	return res;
-}
-
-
-/*
- *  dev_asc_fifo_write():
- *
- *  Write a byte to the asc FIFO.
- */
-static void dev_asc_fifo_write(struct asc_data *d, unsigned char data)
-{
-	d->fifo[d->fifo_in] = data;
-	d->fifo_in = (d->fifo_in + 1) % ASC_FIFO_LEN;
-	d->n_bytes_in_fifo ++;
-
-	if (d->fifo_in == d->fifo_out)
-		fatal("dev_asc: WARNING! FIFO overrun on write!\n");
-}
-
-
-/*
- *  dev_asc_newxfer():
- *
- *  Allocate memory for a new transfer.
- */
-static void dev_asc_newxfer(struct asc_data *d)
-{
-	if (d->xferp != NULL) {
-		printf("WARNING! dev_asc_newxfer(): freeing previous"
-		    " transfer\n");
-		scsi_transfer_free(d->xferp);
-		d->xferp = NULL;
-	}
-
-	d->xferp = scsi_transfer_alloc();
-#if 0
-	d->xferp->get_data_out = dev_asc_get_data_out;
-	d->xferp->gdo_extra = (void *) d;
-#endif
-}
-
-
-/*
- *  dev_asc_transfer():
- *
- *  Transfer data from a SCSI device to the controller (or vice versa),
- *  depending on the current phase.
- *
- *  Returns 1 if ok, 0 on error.
- */
-static int dev_asc_transfer(struct cpu *cpu, struct asc_data *d, int dmaflag)
-{
-	int res = 1, all_done = 1;
-	int len, i, ch;
-
-	if (!quiet_mode)
-		debug(" { TRANSFER to/from id %i: ", d->reg_wo[NCR_SELID] & 7);
-
-	if (d->cur_phase == PHASE_DATA_IN) {
-		/*  Data coming into the controller from external device:  */
-		if (!dmaflag) {
-			if (d->xferp->data_in == NULL) {
-				fatal("no incoming data?\n");
-				res = 0;
-			} else {
-/*  TODO  */
-fatal("TODO..............\n");
-				len = d->reg_wo[NCR_TCL] +
-				    d->reg_wo[NCR_TCM] * 256;
-
-				len--;
-				ch = d->incoming_data[d->incoming_data_addr];
-				debug(" %02x", ch);
-
-				d->incoming_data_addr ++;
-				dev_asc_fifo_write(d, ch);
-
-				if (len == 0) {
-					free(d->incoming_data);
-					d->incoming_data = NULL;
-				}
-
-				d->reg_ro[NCR_TCL] = len & 255;
-				d->reg_ro[NCR_TCM] = (len >> 8) & 255;
-			}
-		} else {
-			/*  Copy from the incoming data into dma memory:  */
-			if (d->xferp->data_in == NULL) {
-				fatal("no incoming DMA data?\n");
-				res = 0;
-			} else {
-				size_t lenIn = d->xferp->data_in_len;
-				size_t lenIn2 = d->reg_wo[NCR_TCL] +
-				    d->reg_wo[NCR_TCM] * 256;
-				if (lenIn2 == 0)
-					lenIn2 = 65536;
-
-                                if (lenIn < lenIn2) {
-                                        fatal("{ asc: data in, lenIn=%i lenIn2=%i "
-					    "}\n", lenIn, lenIn2);
-                                }
-
-				/*  TODO: check lenIn2 in a similar way?  */
-				if (lenIn + (d->dma_address_reg &
-				    (ASC_DMA_SIZE-1)) > ASC_DMA_SIZE)
-					lenIn = ASC_DMA_SIZE -
-					    (d->dma_address_reg &
-					    (ASC_DMA_SIZE-1));
-
-				if (lenIn2 > lenIn) {
-					memset(d->dma + (d->dma_address_reg &
-					    (ASC_DMA_SIZE-1)), 0, lenIn2);
-					lenIn2 = lenIn;
-				}
-
-#ifdef ASC_DEBUG
-				if (!quiet_mode) {
-					int i;
-					for (i=0; i<lenIn; i++)
-						debug(" %02x", d->xferp->
-						    data_in[i]);
-				}
-#endif
-
-				/*
-				 *  Are we using an external DMA controller?
-				 *  Then use it. Otherwise place the data in
-				 *  the DECstation 5000/200 built-in DMA
-				 *  region.
-				 */
-				if (d->dma_controller != NULL)
-					d->dma_controller(
-					    d->dma_controller_data,
-					    d->xferp->data_in,
-					    lenIn2, 1);
-				else
-					memcpy(d->dma + (d->dma_address_reg &
-					    (ASC_DMA_SIZE-1)),
-					    d->xferp->data_in, lenIn2);
-
-				if (d->xferp->data_in_len > lenIn2) {
-					unsigned char *n;
-
-if (d->dma_controller != NULL)
-	printf("WARNING!!!!!!!!! BUG!!!! Unexpected stuff..."
-	    "lenIn2=%i d->xferp->data_in_len=%i\n", (int)lenIn2,
-	    (int)d->xferp->data_in_len);
-
-					all_done = 0;
-					/*  fatal("{ asc: multi-transfer"
-					    " data_in, lenIn=%i lenIn2=%i }\n",
-					    (int)lenIn, (int)lenIn2);  */
-
-					d->xferp->data_in_len -= lenIn2;
-					CHECK_ALLOCATION(n = (unsigned char *)
-					    malloc(d->xferp->data_in_len));
-					memcpy(n, d->xferp->data_in + lenIn2,
-					    d->xferp->data_in_len);
-					free(d->xferp->data_in);
-					d->xferp->data_in = n;
-
-					lenIn = lenIn2;
-				}
-
-				lenIn = 0;
-
-				d->reg_ro[NCR_TCL] = lenIn & 255;
-				d->reg_ro[NCR_TCM] = (lenIn >> 8) & 255;
-
-				/*  Successful DMA transfer:  */
-				d->reg_ro[NCR_STAT] |= NCRSTAT_TC;
-			}
-		}
-	} else if (d->cur_phase == PHASE_DATA_OUT) {
-		/*  Data going from the controller to an external device:  */
-		if (!dmaflag) {
-fatal("TODO.......asdgasin\n");
-		} else {
-			/*  Copy data from DMA to data_out:  */
-			int len2 = d->reg_wo[NCR_TCL] +
-			    d->reg_wo[NCR_TCM] * 256;
-			len = d->xferp->data_out_len;
-
-			if (len2 == 0)
-				len2 = 65536;
-
-			if (len == 0) {
-				fprintf(stderr, "d->xferp->data_out_len == "
-				    "0 ?\n");
-				exit(1);
-			}
-
-			/*  TODO: Make sure that len2 doesn't go outside
-			    of the dma memory?  */
-
-			/*  fatal("    data out offset=%5i len=%5i\n",
-			    d->xferp->data_out_offset, len2);  */
-
-			if (d->xferp->data_out_offset + len2 >
-			    d->xferp->data_out_len) {
-				len2 = d->xferp->data_out_len -
-				    d->xferp->data_out_offset;
-			}
-
-			/*
-			 *  Are we using an external DMA controller? Then use
-			 *  it. Otherwise place the data in the DECstation
-			 *  5000/200 built-in DMA region.
-			 */
-			if (d->xferp->data_out == NULL) {
-				scsi_transfer_allocbuf(&d->xferp->data_out_len,
-				    &d->xferp->data_out, len, 0);
-
-				if (d->dma_controller != NULL)
-					d->dma_controller(
-					    d->dma_controller_data,
-					    d->xferp->data_out,
-					    len2, 0);
-				else
-					memcpy(d->xferp->data_out,
-					    d->dma + (d->dma_address_reg &
-					    (ASC_DMA_SIZE-1)), len2);
-				d->xferp->data_out_offset = len2;
-			} else {
-				/*  Continuing a multi-transfer:  */
-				if (d->dma_controller != NULL)
-					d->dma_controller(
-					    d->dma_controller_data,
-					    d->xferp->data_out +
-						d->xferp->data_out_offset,
-					    len2, 0);
-				else
-					memcpy(d->xferp->data_out +
-					    d->xferp->data_out_offset,
-					    d->dma + (d->dma_address_reg &
-					    (ASC_DMA_SIZE-1)), len2);
-				d->xferp->data_out_offset += len2;
-			}
-
-			/*  If the disk wants more than we're DMAing,
-			    then this is a multitransfer:  */
-			if (d->xferp->data_out_offset !=
-			    d->xferp->data_out_len) {
-				if (!quiet_mode)
-					debug("[ asc: data_out, multitransfer "
-					    "len = %i, len2 = %i ]\n",
-					    (int)len, (int)len2);
-				if (d->xferp->data_out_offset >
-				    d->xferp->data_out_len)
-					fatal("[ asc data_out dma: too much?"
-					    " ]\n");
-				else
-					all_done = 0;
-			}
-
-#ifdef ASC_DEBUG
-			if (!quiet_mode) {
-				int i;
-				for (i=0; i<len; i++)
-					debug(" %02x", d->xferp->data_out[i]);
-			}
-#endif
-			len = 0;
-
-			d->reg_ro[NCR_TCL] = len & 255;
-			d->reg_ro[NCR_TCM] = (len >> 8) & 255;
-
-			/*  Successful DMA transfer:  */
-			d->reg_ro[NCR_STAT] |= NCRSTAT_TC;
-		}
-	} else if (d->cur_phase == PHASE_MSG_OUT) {
-		if (!quiet_mode)
-			debug("MSG OUT: ");
-		/*  Data going from the controller to an external device:  */
-		if (!dmaflag) {
-			/*  There should already be one byte in msg_out, so we
-			    just extend the message:  */
-			int oldlen = d->xferp->msg_out_len;
-			int newlen;
-
-			if (oldlen != 1) {
-				fatal(" (PHASE OUT MSG len == %i, "
-				    "should be 1)\n", oldlen);
-			}
-
-			newlen = oldlen + d->n_bytes_in_fifo;
-			CHECK_ALLOCATION(d->xferp->msg_out = (unsigned char *)
-			    realloc(d->xferp->msg_out, newlen));
-			d->xferp->msg_out_len = newlen;
-
-			i = oldlen;
-			while (d->fifo_in != d->fifo_out) {
-				ch = dev_asc_fifo_read(d);
-				d->xferp->msg_out[i++] = ch;
-#ifdef ASC_DEBUG
-				debug("0x%02x ", ch);
-#endif
-			}
-
-#ifdef MACH
-			/*  Super-ugly hack for Mach/PMAX:  TODO: make nicer  */
-			if (d->xferp->msg_out_len == 6 &&
-			    (d->xferp->msg_out[0] == 0x80 ||
-			     d->xferp->msg_out[0] == 0xc0) &&
-			    d->xferp->msg_out[1] == 0x01 &&
-			    d->xferp->msg_out[2] == 0x03 &&
-			    d->xferp->msg_out[3] == 0x01 &&
-			    d->xferp->msg_out[4] == 0x32 &&
-			    d->xferp->msg_out[5] == 0x0f) {
-				fatal(" !! Mach/PMAX hack !! ");
-				all_done = 0;
-				d->cur_phase = PHASE_MSG_IN;
-			}
-#endif
-		} else {
-			/*  Copy data from DMA to msg_out:  */
-			fatal("[ DMA MSG OUT: xxx TODO! ]");
-			/*  TODO  */
-			res = 0;
-		}
-	} else if (d->cur_phase == PHASE_MSG_IN) {
-		if (!quiet_mode)
-			debug(" MSG IN");
-		fatal("[ MACH HACK! ]");
-		/*  Super-ugly hack for Mach/PMAX:  TODO: make nicer  */
-		dev_asc_fifo_write(d, 0x07);
-		d->cur_phase = PHASE_COMMAND;
-		all_done = 0;
-	} else if (d->cur_phase == PHASE_COMMAND) {
-		if (!quiet_mode)
-			debug(" COMMAND ==> select ");
-		res = dev_asc_select(cpu, d, d->reg_ro[NCR_CFG1] & 7,
-		    d->reg_wo[NCR_SELID] & 7, dmaflag, 0);
-		return res;
-	} else {
-		fatal("!!! TODO: unknown/unimplemented phase "
-		    "in transfer: %i\n", d->cur_phase);
-	}
-
-	/*  Redo the command if data was just sent using DATA_OUT:  */
-	if (d->cur_phase == PHASE_DATA_OUT) {
-		res = diskimage_scsicommand(cpu, d->reg_wo[NCR_SELID] & 7,
-		    DISKIMAGE_SCSI, d->xferp);
-	}
-
-	if (all_done) {
-		if (d->cur_phase == PHASE_MSG_OUT)
-			d->cur_phase = PHASE_COMMAND;
-		else
-			d->cur_phase = PHASE_STATUS;
-	}
-
-	/*
-	 *  Cause an interrupt after the transfer:
-	 *
-	 *  NOTE:  Earlier I had this in here as well:
-	 *	d->reg_ro[NCR_INTR] |= NCRINTR_FC;
-	 *  but Linux/DECstation and OpenBSD/pmax seems to choke on that.
-	 */
-	d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
-	d->reg_ro[NCR_INTR] |= NCRINTR_BS;
-	d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | d->cur_phase;
-	d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | 4;	/*  4?  */
-
-	if (!quiet_mode)
-		debug("}");
-	return res;
-}
-
-
-/*
- *  dev_asc_select():
- *
- *  Select a SCSI device, send msg bytes (if any), and send command bytes.
- *  (Call diskimage_scsicommand() to handle the command.)
- *
- *  Return value: 1 if ok, 0 on error.
- */
-static int dev_asc_select(struct cpu *cpu, struct asc_data *d, int from_id,
-	int to_id, int dmaflag, int n_messagebytes)
-{
-	int ok, len, i, ch;
-
-	if (!quiet_mode)
-		debug(" { SELECT id %i: ", to_id);
-
-	/*
-	 *  Message bytes, if any:
-	 */
-	if (!quiet_mode)
-		debug("msg:");
-
-	if (n_messagebytes > 0) {
-		scsi_transfer_allocbuf(&d->xferp->msg_out_len,
-		    &d->xferp->msg_out, n_messagebytes, 0);
-
-		i = 0;
-		while (n_messagebytes-- > 0) {
-			int ch2 = dev_asc_fifo_read(d);
-			if (!quiet_mode)
-				debug(" %02x", ch2);
-			d->xferp->msg_out[i++] = ch2;
-		}
-
-		if ((d->xferp->msg_out[0] & 0x7) != 0x00) {
-			debug(" (LUNs not implemented yet: 0x%02x) }",
-			    d->xferp->msg_out[0]);
-			return 0;
-		}
-
-		if (((d->xferp->msg_out[0] & ~0x7) != 0xc0) &&
-		    ((d->xferp->msg_out[0] & ~0x7) != 0x80)) {
-			fatal(" (Unimplemented msg out: 0x%02x) }",
-			    d->xferp->msg_out[0]);
-			return 0;
-		}
-
-		if (d->xferp->msg_out_len > 1) {
-			fatal(" (Long msg out, not implemented yet;"
-			    " len=%i) }", d->xferp->msg_out_len);
-			return 0;
-		}
-	} else {
-		if (!quiet_mode)
-			debug(" none");
-	}
-
-	/*  Special case: SELATNS (with STOP sequence):  */
-	if (d->cur_phase == PHASE_MSG_OUT) {
-		if (!quiet_mode)
-			debug(" MSG OUT DEBUG");
-		if (d->xferp->msg_out_len != 1) {
-			fatal(" (SELATNS: msg out len == %i, should be 1)",
-			    d->xferp->msg_out_len);
-			return 0;
-		}
-
-/* d->cur_phase = PHASE_COMMAND; */
-
-		/*  According to the LSI manual:  */
-		d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
-		d->reg_ro[NCR_INTR] |= NCRINTR_FC;
-		d->reg_ro[NCR_INTR] |= NCRINTR_BS;
-		d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | d->cur_phase;
-		d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | 1;
-
-		if (!quiet_mode)
-			debug("}");
-		return 1;
-	}
-
-	/*
-	 *  Command bytes:
-	 */
-	if (!quiet_mode)
-		debug(", cmd: ");
-
-	if (!dmaflag) {
-		if (!quiet_mode)
-			debug("[non-DMA] ");
-
-		scsi_transfer_allocbuf(&d->xferp->cmd_len,
-		    &d->xferp->cmd, d->n_bytes_in_fifo, 0);
-
-		i = 0;
-		while (d->fifo_in != d->fifo_out) {
-			ch = dev_asc_fifo_read(d);
-			d->xferp->cmd[i++] = ch;
-			if (!quiet_mode)
-				debug("%02x ", ch);
-		}
-	} else {
-		if (!quiet_mode)
-			debug("[DMA] ");
-		len = d->reg_wo[NCR_TCL] + d->reg_wo[NCR_TCM] * 256;
-		if (len == 0)
-			len = 65536;
-
-		scsi_transfer_allocbuf(&d->xferp->cmd_len,
-		    &d->xferp->cmd, len, 0);
-
-		for (i=0; i<len; i++) {
-			int ofs = d->dma_address_reg + i;
-			ch = d->dma[ofs & (ASC_DMA_SIZE-1)];
-			d->xferp->cmd[i] = ch;
-			if (!quiet_mode)
-				debug("%02x ", ch);
-		}
-
-		d->reg_ro[NCR_TCL] = len & 255;
-		d->reg_ro[NCR_TCM] = (len >> 8) & 255;
-
-		d->reg_ro[NCR_STAT] |= NCRSTAT_TC;
-	}
-
-	/*
-	 *  Call the SCSI device to perform the command:
-	 */
-	ok = diskimage_scsicommand(cpu, to_id, DISKIMAGE_SCSI, d->xferp);
-
-
-	/*  Cause an interrupt:  */
-	d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
-	d->reg_ro[NCR_INTR] |= NCRINTR_FC;
-	d->reg_ro[NCR_INTR] |= NCRINTR_BS;
-
-	if (ok == 2)
-		d->cur_phase = PHASE_DATA_OUT;
-	else if (d->xferp->data_in != NULL)
-		d->cur_phase = PHASE_DATA_IN;
-	else
-		d->cur_phase = PHASE_STATUS;
-
-	d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | d->cur_phase;
-	d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | 4;	/*  DONE (?)  */
-
-	if (!quiet_mode)
-		debug("}");
-
-	return ok;
-}
-
-
-DEVICE_ACCESS(asc_address_reg)
-{
-	struct asc_data *d = (struct asc_data *) extra;
-
-	if (relative_addr + len > 4)
-		return 0;
-
-	if (writeflag==MEM_READ) {
-		memcpy(data, d->dma_address_reg_memory + relative_addr, len);
-	} else {
-		memcpy(d->dma_address_reg_memory + relative_addr, data, len);
-	}
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(asc_dma)
-{
-	struct asc_data *d = (struct asc_data *) extra;
-
-	if (writeflag==MEM_READ) {
-		memcpy(data, d->dma + relative_addr, len);
-#ifdef ASC_DEBUG
-		{
-			int i;
-			debug("[ asc: read from DMA addr 0x%05x:",
-			    (int) relative_addr);
-			for (i=0; i<len; i++)
-				debug(" %02x", data[i]);
-			debug(" ]\n");
-		}
-#endif
-
-		/*  Don't return the common way, as that
-		    would overwrite data.  */
-		return 1;
-	} else {
-		memcpy(d->dma + relative_addr, data, len);
-#ifdef ASC_DEBUG
-		{
-			int i;
-			debug("[ asc: write to  DMA addr 0x%05x:",
-			    (int) relative_addr);
-			for (i=0; i<len; i++)
-				debug(" %02x", data[i]);
-			debug(" ]\n");
-		}
-#endif
-		/*  Quick return.  */
-		return 1;
-	}
-}
-
-
-DEVICE_ACCESS(asc)
-{
-	int regnr;
-	struct asc_data *d = (struct asc_data *) extra;
-	int target_exists;
-	int n_messagebytes = 0;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-#if 0
-	/*  Debug stuff useful when trying to make dev_asc compatible
-	    with the 'arc' emulation mode, which is different from
-	    the DECstation mode.  */
-	fatal("[ asc: writeflag=%i addr=%08x idata=%016llx ]\n",
-	    writeflag, (int)relative_addr, (long long)idata);
-#endif
-
-	switch (d->mode) {
-	case DEV_ASC_DEC:
-		regnr = relative_addr / 4;
-		break;
-	case DEV_ASC_PICA:
-	default:
-		regnr = relative_addr;
-	}
-
-	/*  Controller's ID is fixed:  */
-	d->reg_ro[NCR_CFG1] = (d->reg_ro[NCR_CFG1] & ~7) | ASC_SCSI_ID;
-
-	d->reg_ro[NCR_FFLAG] = ((d->reg_ro[NCR_STEP] & 0x7) << 5)
-	    + d->n_bytes_in_fifo;
-
-	d->dma_address_reg =
-	    d->dma_address_reg_memory[0] +
-	    (d->dma_address_reg_memory[1] << 8) +
-	    (d->dma_address_reg_memory[2] << 16) +
-	    (d->dma_address_reg_memory[3] << 24);
-
-	if (regnr < 0x10) {
-		if (regnr == NCR_FIFO) {
-			if (writeflag == MEM_WRITE)
-				dev_asc_fifo_write(d, idata);
-			else
-				odata = dev_asc_fifo_read(d);
-		} else {
-			if (writeflag==MEM_WRITE)
-				d->reg_wo[regnr] = idata;
-			else
-				odata = d->reg_ro[regnr];
-		}
-
-#ifdef ASC_FULL_REGISTER_ACCESS_DEBUG
-		if (!quiet_mode) {
-			if (writeflag==MEM_READ) {
-				debug("[ asc: read from %s: 0x%02x",
-				    asc_reg_names[regnr], (int)odata);
-			} else {
-				debug("[ asc: write to  %s: 0x%02x",
-				    asc_reg_names[regnr], (int)idata);
-			}
-		}
-#endif
-	} else if (relative_addr >= 0x300 && relative_addr < 0x600
-	    && d->turbochannel != NULL) {
-		debug("[ asc: offset 0x%x, redirecting to turbochannel"
-		    " access ]\n", relative_addr);
-		return dev_turbochannel_access(cpu, mem,
-		    relative_addr, data, len, writeflag,
-		    d->turbochannel);
-	} else {
-		if (writeflag==MEM_READ) {
-			fatal("[ asc: read from 0x%04x: 0x%02x ]\n",
-			    relative_addr, (int)odata);
-		} else {
-			fatal("[ asc: write to  0x%04x: 0x%02x ]\n",
-			    relative_addr, (int)idata);
-		}
-	}
-
-	/*
-	 *  Some registers are read/write. Copy contents of
-	 *  reg_wo to reg_ro:
-	 */
-#if 0
-	d->reg_ro[ 0] = d->reg_wo[0];	/*  Transfer count lo and  */
-	d->reg_ro[ 1] = d->reg_wo[1];	/*  middle  */
-#endif
-	d->reg_ro[ 2] = d->reg_wo[2];
-	d->reg_ro[ 3] = d->reg_wo[3];
-	d->reg_ro[ 8] = d->reg_wo[8];
-	d->reg_ro[ 9] = d->reg_wo[9];
-	d->reg_ro[10] = d->reg_wo[10];
-	d->reg_ro[11] = d->reg_wo[11];
-	d->reg_ro[12] = d->reg_wo[12];
-
-	if (regnr == NCR_CMD && writeflag == MEM_WRITE) {
-		if (!quiet_mode)
-			debug(" ");
-
-		/*  TODO:  Perhaps turn off others here too?  */
-		d->reg_ro[NCR_INTR] &= ~NCRINTR_SBR;
-
-		if (idata & NCRCMD_DMA) {
-			if (!quiet_mode)
-				debug("[DMA] ");
-
-			/*
-			 *  DMA commands load the transfer count from the
-			 *  write-only registers to the read-only ones, and
-			 *  the Terminal Count bit is cleared.
-			 */
-			d->reg_ro[NCR_TCL] = d->reg_wo[NCR_TCL];
-			d->reg_ro[NCR_TCM] = d->reg_wo[NCR_TCM];
-			d->reg_ro[NCR_TCH] = d->reg_wo[NCR_TCH];
-			d->reg_ro[NCR_STAT] &= ~NCRSTAT_TC;
-		}
-
-		switch (idata & ~NCRCMD_DMA) {
-
-		case NCRCMD_NOP:
-			if (!quiet_mode)
-				debug("NOP");
-			break;
-
-		case NCRCMD_FLUSH:
-			if (!quiet_mode)
-				debug("FLUSH");
-			/*  Flush the FIFO:  */
-			dev_asc_fifo_flush(d);
-			break;
-
-		case NCRCMD_RSTCHIP:
-			if (!quiet_mode)
-				debug("RSTCHIP");
-			/*  Hardware reset.  */
-			dev_asc_reset(d);
-			break;
-
-		case NCRCMD_RSTSCSI:
-			if (!quiet_mode)
-				debug("RSTSCSI");
-			/*  No interrupt if interrupts are disabled.  */
-			if (!(d->reg_wo[NCR_CFG1] & NCRCFG1_SRR))
-				d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
-			d->reg_ro[NCR_INTR] |= NCRINTR_SBR;
-			d->reg_ro[NCR_INTR] |= NCRINTR_FC;
-			d->cur_state = STATE_DISCONNECTED;
-			break;
-
-		case NCRCMD_ENSEL:
-			if (!quiet_mode)
-				debug("ENSEL");
-			/*  TODO  */
-			break;
-
-		case NCRCMD_ICCS:
-			if (!quiet_mode)
-				debug("ICCS");
-			/*  Reveice a status byte + a message byte.  */
-
-			/*  TODO: how about other status and message bytes?  */
-			if (d->xferp != NULL && d->xferp->status != NULL)
-				dev_asc_fifo_write(d, d->xferp->status[0]);
-			else
-				dev_asc_fifo_write(d, 0x00);
-
-			if (d->xferp != NULL && d->xferp->msg_in != NULL)
-				dev_asc_fifo_write(d, d->xferp->msg_in[0]);
-			else
-				dev_asc_fifo_write(d, 0x00);
-
-			d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
-			d->reg_ro[NCR_INTR] |= NCRINTR_FC;
-/*			d->reg_ro[NCR_INTR] |= NCRINTR_BS; */
-			d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | 7;
-				/*  ? probably 7  */
-			d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | 4;
-				/*  ?  */
-			break;
-
-		case NCRCMD_MSGOK:
-			/*  Message is being Rejected if ATN is set,
-			    otherwise Accepted.  */
-			if (!quiet_mode) {
-				debug("MSGOK");
-				if (d->atn)
-					debug("; Rejecting message");
-				else
-					debug("; Accepting message");
-			}
-			d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
-			d->reg_ro[NCR_INTR] |= NCRINTR_DIS;
-
-			d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) |
-			    d->cur_phase;	/*  6?  */
-			d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) |
-			    4;	/*  ?  */
-
-			d->cur_state = STATE_DISCONNECTED;
-
-			if (d->xferp != NULL)
-				scsi_transfer_free(d->xferp);
-			d->xferp = NULL;
-			break;
-
-		case NCRCMD_SETATN:
-			if (!quiet_mode)
-				debug("SETATN");
-			d->atn = 1;
-			break;
-
-		case NCRCMD_RSTATN:
-			if (!quiet_mode)
-				debug("RSTATN");
-			d->atn = 0;
-			break;
-
-		case NCRCMD_SELNATN:
-		case NCRCMD_SELATN:
-		case NCRCMD_SELATNS:
-		case NCRCMD_SELATN3:
-			d->cur_phase = PHASE_COMMAND;
-			switch (idata & ~NCRCMD_DMA) {
-			case NCRCMD_SELATN:
-			case NCRCMD_SELATNS:
-				if ((idata & ~NCRCMD_DMA) == NCRCMD_SELATNS) {
-					if (!quiet_mode)
-						debug("SELATNS: select with "
-						    "atn and stop, id %i",
-						    d->reg_wo[NCR_SELID] & 7);
-					d->cur_phase = PHASE_MSG_OUT;
-				} else {
-					if (!quiet_mode)
-						debug("SELATN: select with atn"
-						    ", id %i",
-						    d->reg_wo[NCR_SELID] & 7);
-				}
-				n_messagebytes = 1;
-				break;
-			case NCRCMD_SELATN3:
-				if (!quiet_mode)
-					debug("SELNATN: select with atn3, "
-					    "id %i", d->reg_wo[NCR_SELID] & 7);
-				n_messagebytes = 3;
-				break;
-			case NCRCMD_SELNATN:
-				if (!quiet_mode)
-					debug("SELNATN: select without atn, "
-					    "id %i", d->reg_wo[NCR_SELID] & 7);
-				n_messagebytes = 0;
-			}
-
-			/*  TODO: not just disk, but some generic
-			    SCSI device  */
-			target_exists = diskimage_exist(cpu->machine,
-			    d->reg_wo[NCR_SELID] & 7, DISKIMAGE_SCSI);
-
-			if (target_exists) {
-				/*
-				 *  Select a SCSI device, send message bytes
-				 *  (if any) and command bytes to the target.
-				 */
-				int ok;
-
-				dev_asc_newxfer(d);
-
-				ok = dev_asc_select(cpu, d,
-				    d->reg_ro[NCR_CFG1] & 7,
-				    d->reg_wo[NCR_SELID] & 7,
-				    idata & NCRCMD_DMA? 1 : 0,
-				    n_messagebytes);
-
-				if (ok)
-					d->cur_state = STATE_INITIATOR;
-				else {
-					d->cur_state = STATE_DISCONNECTED;
-					d->reg_ro[NCR_INTR] |= NCRINTR_DIS;
-					d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
-					d->reg_ro[NCR_STEP] =
-					    (d->reg_ro[NCR_STEP] & ~7) | 0;
-					if (d->xferp != NULL)
-						scsi_transfer_free(d->xferp);
-					d->xferp = NULL;
-				}
-			} else {
-				/*
-				 *  Selection failed, non-existant scsi ID:
-				 *
-				 *  This is good enough to fool Ultrix, NetBSD,
-				 *  OpenBSD and Linux to continue detection of
-				 *  other IDs, without giving any warnings.
-				 */
-				d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
-				d->reg_ro[NCR_INTR] |= NCRINTR_DIS;
-				d->reg_ro[NCR_STEP] &= ~7;
-				d->reg_ro[NCR_STEP] |= 0;
-				dev_asc_fifo_flush(d);
-				d->cur_state = STATE_DISCONNECTED;
-			}
-			break;
-
-		case NCRCMD_TRPAD:
-			if (!quiet_mode)
-				debug("TRPAD");
-
-			dev_asc_newxfer(d);
-			{
-				int ok;
-
-				ok = dev_asc_transfer(cpu, d,
-				    idata & NCRCMD_DMA? 1 : 0);
-				if (!ok) {
-					d->cur_state = STATE_DISCONNECTED;
-					d->reg_ro[NCR_INTR] |= NCRINTR_DIS;
-					d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
-					d->reg_ro[NCR_STEP] = (d->reg_ro[
-					    NCR_STEP] & ~7) | 0;
-					if (d->xferp != NULL)
-						scsi_transfer_free(d->xferp);
-					d->xferp = NULL;
-				}
-			}
-break;
-
-/*  Old code which didn't work with Mach:  */
-#if 0
-			d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
-			d->reg_ro[NCR_INTR] |= NCRINTR_BS;
-			d->reg_ro[NCR_INTR] |= NCRINTR_FC;
-			d->reg_ro[NCR_STAT] |= NCRSTAT_TC;
-
-			d->reg_ro[NCR_TCL] = 0;
-			d->reg_ro[NCR_TCM] = 0;
-
-			d->reg_ro[NCR_STEP] &= ~7;
-#if 0
-			d->reg_ro[NCR_STEP] |= 0;
-			dev_asc_fifo_flush(d);
-#else
-			d->reg_ro[NCR_STEP] |= 4;
-#endif
-			break;
-#endif
-
-		case NCRCMD_TRANS:
-			if (!quiet_mode)
-				debug("TRANS");
-
-			{
-				int ok;
-
-				ok = dev_asc_transfer(cpu, d,
-				    idata & NCRCMD_DMA? 1 : 0);
-				if (!ok) {
-					d->cur_state = STATE_DISCONNECTED;
-					d->reg_ro[NCR_INTR] |= NCRINTR_DIS;
-					d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
-					d->reg_ro[NCR_STEP] = (d->reg_ro[
-					    NCR_STEP] & ~7) | 0;
-					if (d->xferp != NULL)
-						scsi_transfer_free(d->xferp);
-					d->xferp = NULL;
-				}
-			}
-			break;
-
-		default:
-			fatal("(unimplemented asc cmd 0x%02x)", (int)idata);
-			d->reg_ro[NCR_STAT] |= NCRSTAT_INT;
-			d->reg_ro[NCR_INTR] |= NCRINTR_ILL;
-			/*
-			 *  TODO:  exit or continue with Illegal command
-			 *  interrupt?
-			 */
-			exit(1);
-		}
-	}
-
-	if (regnr == NCR_INTR && writeflag == MEM_READ) {
-		/*
-		 *  Reading the interrupt register de-asserts the
-		 *  interrupt pin.  Also, INTR, STEP, and STAT are all
-		 *  cleared, according to page 64 of the LSI53CF92A manual,
-		 *  if "interrupt output is true".
-		 */
-		if (d->reg_ro[NCR_STAT] & NCRSTAT_INT) {
-			d->reg_ro[NCR_INTR] = 0;
-			d->reg_ro[NCR_STEP] = 0;
-			d->reg_ro[NCR_STAT] = 0;
-
-			/*  For Mach/PMAX? TODO  */
-			d->reg_ro[NCR_STAT] = PHASE_COMMAND;
-		}
-
-		INTERRUPT_DEASSERT(d->irq);
-		d->irq_asserted = 0;
-	}
-
-	if (regnr == NCR_CFG1) {
-		/*  TODO: other bits  */
-		if (!quiet_mode) {
-			debug(" parity %s,", d->reg_ro[regnr] &
-			    NCRCFG1_PARENB? "enabled" : "disabled");
-			debug(" scsi_id %i", d->reg_ro[regnr] & 0x7);
-		}
-	}
-
-#ifdef ASC_FULL_REGISTER_ACCESS_DEBUG
-	debug(" ]\n");
-#endif
-	dev_asc_tick(cpu, extra);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_asc_init():
- *
- *  Register an 'asc' device.
- */
-void dev_asc_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, const char *irq_path, void *turbochannel, int mode,
-	size_t (*dma_controller)(void *dma_controller_data,
-		unsigned char *data, size_t len, int writeflag),
-	void *dma_controller_data)
-{
-	struct asc_data *d;
-
-	CHECK_ALLOCATION(d = (struct asc_data *) malloc(sizeof(struct asc_data)));
-	memset(d, 0, sizeof(struct asc_data));
-
-	INTERRUPT_CONNECT(irq_path, d->irq);
-	d->turbochannel = turbochannel;
-	d->mode         = mode;
-
-	d->reg_ro[NCR_CFG3] = NCRF9XCFG3_CDB;
-
-	CHECK_ALLOCATION(d->dma_address_reg_memory = (unsigned char *)
-	    malloc(machine->arch_pagesize));
-	memset(d->dma_address_reg_memory, 0, machine->arch_pagesize);
-
-	CHECK_ALLOCATION(d->dma = (unsigned char *) malloc(ASC_DMA_SIZE));
-	memset(d->dma, 0, ASC_DMA_SIZE);
-
-	d->dma_controller      = dma_controller;
-	d->dma_controller_data = dma_controller_data;
-
-	memory_device_register(mem, "asc", baseaddr,
-	    mode == DEV_ASC_PICA? DEV_ASC_PICA_LENGTH : DEV_ASC_DEC_LENGTH,
-	    dev_asc_access, d, DM_DEFAULT, NULL);
-
-	if (mode == DEV_ASC_DEC) {
-		memory_device_register(mem, "asc_dma_address_reg",
-		    baseaddr + 0x40000, 4096, dev_asc_address_reg_access, d,
-		    DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK,
-		    (unsigned char *)&d->dma_address_reg_memory[0]);
-		memory_device_register(mem, "asc_dma", baseaddr + 0x80000,
-		    ASC_DMA_SIZE, dev_asc_dma_access, d,
-		    DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK, d->dma);
-	}
-
-	machine_add_tickfunction(machine, dev_asc_tick, d, ASC_TICK_SHIFT);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_bebox.c gxemul-0.7.0+dfsg/src/devices/dev_bebox.c
--- gxemul-0.6.2/src/devices/dev_bebox.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_bebox.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,247 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: BeBox motherboard registers and interrupt controller
+ *
+ *  See the following URL for more information:
+ *
+ *	http://www.bebox.nu/history.php?s=history/benews/benews27
+ *
+ *  These interrupt numbers are from NetBSD's bebox/extint.c:
+ *
+ *	serial3			6
+ *	serial4			7
+ *	midi1			8
+ *	midi2			9
+ *	scsi			10
+ *	pci1			11
+ *	pci2			12
+ *	pci3			13
+ *	sound			14
+ *	8259			26
+ *	irda			27
+ *	a2d			28
+ *	geekport		29
+ *
+ *  Note that these are in IBM order, i.e. reversed. So 8259 interrupts
+ *  go to interrupt 31 - 26 = 5, when using normal numbers.
+ *
+ *  Interrupt routing should work to both CPUs, but I've only ever seen the
+ *  first CPU being used by NetBSD/bebox, so the second CPU is untested :-)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+struct bebox_data {
+	struct interrupt	cpu_irq[2];
+
+	/*  The 5 motherboard registers:  */
+	uint32_t		cpu0_int_mask;
+	uint32_t		cpu1_int_mask;
+	uint32_t		int_status;
+	uint32_t		xpi;
+	uint32_t		resets;
+};
+
+
+static void bebox_interrupt_assert(struct interrupt *interrupt)
+{
+	struct bebox_data *d = (struct bebox_data *) interrupt->extra;
+	d->int_status |= interrupt->line;
+
+	/*  printf("STATUS %08x  CPU0 %08x  CPU1 %08x\n",
+	    d->int_status, d->cpu0_int_mask, d->cpu1_int_mask);  */
+
+	if (d->int_status & d->cpu0_int_mask)
+		INTERRUPT_ASSERT(d->cpu_irq[0]);
+	if (d->int_status & d->cpu1_int_mask)
+		INTERRUPT_ASSERT(d->cpu_irq[1]);
+}
+static void bebox_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct bebox_data *d = (struct bebox_data *) interrupt->extra;
+	d->int_status &= ~interrupt->line;
+
+	if (!(d->int_status & d->cpu0_int_mask))
+		INTERRUPT_DEASSERT(d->cpu_irq[0]);
+	if (!(d->int_status & d->cpu1_int_mask))
+		INTERRUPT_DEASSERT(d->cpu_irq[1]);
+}
+
+
+/*
+ *  check_cpu_masks():
+ *
+ *  BeBox interrupt enable bits are not allowed to be present in
+ *  both CPUs at the same time.
+ */
+static void check_cpu_masks(struct cpu *cpu, struct bebox_data *d)
+{
+	d->cpu0_int_mask &= 0x7fffffff;
+	d->cpu1_int_mask &= 0x7fffffff;
+	if ((d->cpu0_int_mask | d->cpu1_int_mask) !=
+	    (d->cpu0_int_mask ^ d->cpu1_int_mask))
+		fatal("check_cpu_masks(): BeBox cpu int masks collide!\n");
+}
+
+
+DEVICE_ACCESS(bebox)
+{
+	struct bebox_data *d = (struct bebox_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case 0x0f0:
+		if (writeflag == MEM_READ)
+			odata = d->cpu0_int_mask;
+		else {
+			if (idata & 0x80000000)
+				d->cpu0_int_mask |= idata;
+			else
+				d->cpu0_int_mask &= ~idata;
+			check_cpu_masks(cpu, d);
+		}
+		break;
+
+	case 0x1f0:
+		if (writeflag == MEM_READ)
+			odata = d->cpu1_int_mask;
+		else {
+			if (idata & 0x80000000)
+				d->cpu1_int_mask |= idata;
+			else
+				d->cpu1_int_mask &= ~idata;
+			check_cpu_masks(cpu, d);
+		}
+		break;
+
+	case 0x2f0:
+		if (writeflag == MEM_READ)
+			odata = d->int_status;
+		else {
+			if (idata & 0x80000000)
+				d->int_status |= idata;
+			else
+				d->int_status &= ~idata;
+			d->int_status &= 0x7fffffff;
+		}
+		break;
+
+	case 0x3f0:
+		if (writeflag == MEM_READ) {
+			odata = d->xpi;
+
+			/*  Bit 6 (counted from the left) is cpuid:  */
+			odata &= ~0x02000000;
+			if (cpu->cpu_id == 1)
+				odata |= 0x02000000;
+		} else {
+			fatal("[ bebox: unimplemented write to 0x3f0:"
+			    " 0x%08x ]\n", (int)idata);
+		}
+		break;
+	default:
+		if (writeflag==MEM_READ) {
+			fatal("[ bebox: unimplemented read from 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			fatal("[ bebox: unimplemented write to 0x%08lx: 0x"
+			    "%08x ]\n", (long)relative_addr, (int)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(bebox)
+{
+	struct bebox_data *d;
+	int i;
+	char n[300];
+	struct machine *machine = devinit->machine;
+
+	CHECK_ALLOCATION(d = (struct bebox_data *) malloc(sizeof(struct bebox_data)));
+	memset(d, 0, sizeof(struct bebox_data));
+
+	/*  Connect to the two BeBox CPUs:  */
+	for (i=0; i<2; i++) {
+		if (i >= machine->ncpus) {
+			fatal("FATAL ERROR: The machine seem to be "
+			    "lacking cpu nr %i (0-based)\n", i);
+			exit(1);
+		}
+
+		snprintf(n, sizeof(n), "%s.cpu[%i]", machine->path, i);
+		INTERRUPT_CONNECT(n, d->cpu_irq[i]);
+	}
+
+	/*
+	 *  Register the 32 BeBox interrupts:
+	 *
+ 	 *  NOTE: They are registered on cpu[0], but the interrupt assert/
+	 *  deassert routines in this file make sure that the interrupts
+	 *  are routed to the correct cpu!
+	 */
+	for (i=0; i<32; i++) {
+		struct interrupt templ;
+		snprintf(n, sizeof(n), "%s.bebox.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 1 << i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = bebox_interrupt_assert;
+		templ.interrupt_deassert = bebox_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	memory_device_register(machine->memory, devinit->name,
+	    0x7ffff000, 0x500, dev_bebox_access, d, DM_DEFAULT, NULL);
+
+	devinit->return_ptr = d;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_bebox.cc gxemul-0.7.0+dfsg/src/devices/dev_bebox.cc
--- gxemul-0.6.2/src/devices/dev_bebox.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_bebox.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,247 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: BeBox motherboard registers and interrupt controller
- *
- *  See the following URL for more information:
- *
- *	http://www.bebox.nu/history.php?s=history/benews/benews27
- *
- *  These interrupt numbers are from NetBSD's bebox/extint.c:
- *
- *	serial3			6
- *	serial4			7
- *	midi1			8
- *	midi2			9
- *	scsi			10
- *	pci1			11
- *	pci2			12
- *	pci3			13
- *	sound			14
- *	8259			26
- *	irda			27
- *	a2d			28
- *	geekport		29
- *
- *  Note that these are in IBM order, i.e. reversed. So 8259 interrupts
- *  go to interrupt 31 - 26 = 5, when using normal numbers.
- *
- *  Interrupt routing should work to both CPUs, but I've only ever seen the
- *  first CPU being used by NetBSD/bebox, so the second CPU is untested :-)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-struct bebox_data {
-	struct interrupt	cpu_irq[2];
-
-	/*  The 5 motherboard registers:  */
-	uint32_t		cpu0_int_mask;
-	uint32_t		cpu1_int_mask;
-	uint32_t		int_status;
-	uint32_t		xpi;
-	uint32_t		resets;
-};
-
-
-static void bebox_interrupt_assert(struct interrupt *interrupt)
-{
-	struct bebox_data *d = (struct bebox_data *) interrupt->extra;
-	d->int_status |= interrupt->line;
-
-	/*  printf("STATUS %08x  CPU0 %08x  CPU1 %08x\n",
-	    d->int_status, d->cpu0_int_mask, d->cpu1_int_mask);  */
-
-	if (d->int_status & d->cpu0_int_mask)
-		INTERRUPT_ASSERT(d->cpu_irq[0]);
-	if (d->int_status & d->cpu1_int_mask)
-		INTERRUPT_ASSERT(d->cpu_irq[1]);
-}
-static void bebox_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct bebox_data *d = (struct bebox_data *) interrupt->extra;
-	d->int_status &= ~interrupt->line;
-
-	if (!(d->int_status & d->cpu0_int_mask))
-		INTERRUPT_DEASSERT(d->cpu_irq[0]);
-	if (!(d->int_status & d->cpu1_int_mask))
-		INTERRUPT_DEASSERT(d->cpu_irq[1]);
-}
-
-
-/*
- *  check_cpu_masks():
- *
- *  BeBox interrupt enable bits are not allowed to be present in
- *  both CPUs at the same time.
- */
-static void check_cpu_masks(struct cpu *cpu, struct bebox_data *d)
-{
-	d->cpu0_int_mask &= 0x7fffffff;
-	d->cpu1_int_mask &= 0x7fffffff;
-	if ((d->cpu0_int_mask | d->cpu1_int_mask) !=
-	    (d->cpu0_int_mask ^ d->cpu1_int_mask))
-		fatal("check_cpu_masks(): BeBox cpu int masks collide!\n");
-}
-
-
-DEVICE_ACCESS(bebox)
-{
-	struct bebox_data *d = (struct bebox_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case 0x0f0:
-		if (writeflag == MEM_READ)
-			odata = d->cpu0_int_mask;
-		else {
-			if (idata & 0x80000000)
-				d->cpu0_int_mask |= idata;
-			else
-				d->cpu0_int_mask &= ~idata;
-			check_cpu_masks(cpu, d);
-		}
-		break;
-
-	case 0x1f0:
-		if (writeflag == MEM_READ)
-			odata = d->cpu1_int_mask;
-		else {
-			if (idata & 0x80000000)
-				d->cpu1_int_mask |= idata;
-			else
-				d->cpu1_int_mask &= ~idata;
-			check_cpu_masks(cpu, d);
-		}
-		break;
-
-	case 0x2f0:
-		if (writeflag == MEM_READ)
-			odata = d->int_status;
-		else {
-			if (idata & 0x80000000)
-				d->int_status |= idata;
-			else
-				d->int_status &= ~idata;
-			d->int_status &= 0x7fffffff;
-		}
-		break;
-
-	case 0x3f0:
-		if (writeflag == MEM_READ) {
-			odata = d->xpi;
-
-			/*  Bit 6 (counted from the left) is cpuid:  */
-			odata &= ~0x02000000;
-			if (cpu->cpu_id == 1)
-				odata |= 0x02000000;
-		} else {
-			fatal("[ bebox: unimplemented write to 0x3f0:"
-			    " 0x%08x ]\n", (int)idata);
-		}
-		break;
-	default:
-		if (writeflag==MEM_READ) {
-			fatal("[ bebox: unimplemented read from 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			fatal("[ bebox: unimplemented write to 0x%08lx: 0x"
-			    "%08x ]\n", (long)relative_addr, (int)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(bebox)
-{
-	struct bebox_data *d;
-	int i;
-	char n[300];
-	struct machine *machine = devinit->machine;
-
-	CHECK_ALLOCATION(d = (struct bebox_data *) malloc(sizeof(struct bebox_data)));
-	memset(d, 0, sizeof(struct bebox_data));
-
-	/*  Connect to the two BeBox CPUs:  */
-	for (i=0; i<2; i++) {
-		if (i >= machine->ncpus) {
-			fatal("FATAL ERROR: The machine seem to be "
-			    "lacking cpu nr %i (0-based)\n", i);
-			exit(1);
-		}
-
-		snprintf(n, sizeof(n), "%s.cpu[%i]", machine->path, i);
-		INTERRUPT_CONNECT(n, d->cpu_irq[i]);
-	}
-
-	/*
-	 *  Register the 32 BeBox interrupts:
-	 *
- 	 *  NOTE: They are registered on cpu[0], but the interrupt assert/
-	 *  deassert routines in this file make sure that the interrupts
-	 *  are routed to the correct cpu!
-	 */
-	for (i=0; i<32; i++) {
-		struct interrupt templ;
-		snprintf(n, sizeof(n), "%s.bebox.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 1 << i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = bebox_interrupt_assert;
-		templ.interrupt_deassert = bebox_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	memory_device_register(machine->memory, devinit->name,
-	    0x7ffff000, 0x500, dev_bebox_access, d, DM_DEFAULT, NULL);
-
-	devinit->return_ptr = d;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_bt431.c gxemul-0.7.0+dfsg/src/devices/dev_bt431.c
--- gxemul-0.6.2/src/devices/dev_bt431.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_bt431.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,213 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Brooktree BT431, used by TURBOchannel graphics cards
+ *
+ *  TODO.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "devices.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/bt431reg.h"
+
+
+struct bt431_data {
+	uint32_t	bt431_reg[DEV_BT431_NREGS];
+
+	unsigned char	cur_addr_hi;
+	unsigned char	cur_addr_lo;
+
+	int		planes;
+	int		cursor_on;
+	int		cursor_x;
+	int		cursor_y;
+	int		cursor_xsize;
+	int		cursor_ysize;
+
+	struct vfb_data *vfb_data;
+};
+
+
+DEVICE_ACCESS(bt431)
+{
+	struct bt431_data *d = (struct bt431_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int btaddr;
+#if 0
+	int on, new_cursor_x, new_cursor_y;
+#endif
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	btaddr = ((d->cur_addr_hi << 8) + d->cur_addr_lo) % DEV_BT431_NREGS;
+
+/*  TODO  */
+
+	/*  Read from/write to the bt431:  */
+	switch (relative_addr) {
+	case 0x00:		/*  Low byte of address:  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ bt431: write to Low Address Byte, "
+			    "0x%02x ]\n", (int)idata);
+			d->cur_addr_lo = idata;
+		} else {
+			odata = d->cur_addr_lo;
+			debug("[ bt431: read from Low Address Byte: "
+			    "0x%0x ]\n", (int)odata);
+		}
+		break;
+	case 0x04:		/*  High byte of address:  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ bt431: write to High Address Byte, "
+			    "0x%02x ]\n", (int)idata);
+			d->cur_addr_hi = idata;
+		} else {
+			odata = d->cur_addr_hi;
+			debug("[ bt431: read from High Address Byte: "
+			    "0x%0x ]\n", (int)odata);
+		}
+		break;
+	case 0x08:		/*  Register access:  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ bt431: write to BT431 register 0x%04x, "
+			    "value 0x%02x ]\n", btaddr, (int)idata);
+			d->bt431_reg[btaddr] = idata;
+
+#if 0
+			/*  Write to cursor bitmap:  */
+			if (btaddr >= 0x400)
+				bt431_sync_xysize(d);
+#endif
+		} else {
+			odata = d->bt431_reg[btaddr];
+			debug("[ bt431: read from BT431 register 0x%04x, "
+			    "value 0x%02x ]\n", btaddr, (int)odata);
+		}
+
+		/*  Go to next register:  */
+		d->cur_addr_lo ++;
+		if (d->cur_addr_lo == 0)
+			d->cur_addr_hi ++;
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ bt431: unimplemented write to address "
+			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
+			    (int)idata);
+		} else {
+			debug("[ bt431: unimplemented read from address "
+			    "0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+#if 0
+
+TODO: This is from bt459!
+
+	/*  NetBSD uses 370,37 as magic values.  */
+	new_cursor_x = (d->bt431_reg[BT431_REG_CXLO] & 255) +
+	    ((d->bt431_reg[BT431_REG_CXHI] & 255) << 8) - 370;
+	new_cursor_y = (d->bt431_reg[BT431_REG_CYLO] & 255) +
+	    ((d->bt431_reg[BT431_REG_CYHI] & 255) << 8) - 37;
+
+	/*  TODO: what do the bits in the CCR do?  */
+	on = d->bt431_reg[BT431_REG_CCR] ? 1 : 0;
+
+on = 1;
+
+	if (new_cursor_x != d->cursor_x || new_cursor_y != d->cursor_y ||
+	    on != d->cursor_on) {
+		int ysize_mul = 1;
+
+		d->cursor_x = new_cursor_x;
+		d->cursor_y = new_cursor_y;
+		d->cursor_on = on;
+
+		/*
+		 *  Ugly hack for Ultrix:
+		 *
+		 *  Ultrix and NetBSD assume that the cursor works differently.
+		 *  Ultrix uses the 370,38 coordinates, but draws the cursor
+		 *  upwards. NetBSD draws it downwards.  Ultrix also makes the
+		 *  cursor smaller (?).
+		 *
+		 *  TODO:  This actually depends on which ultrix kernel you use.
+		 *  Clearly, the BT459 emulation is not implemented well
+		 *  enough yet.
+		 *
+		 *  TODO:  Find out why? Is it because of special BT459
+		 *  commands?
+		 *
+		 *  TODO: Is the above text even valid anymore? :-)
+		 */
+		if (!(d->bt431_reg[BT431_REG_CCR] & 1)) {
+/*			ysize_mul = 4; */
+			d->cursor_y += 5 - (d->cursor_ysize * ysize_mul);
+		}
+
+		debug("[ bt431: cursor = %03i,%03i ]\n", d->cursor_x,
+		    d->cursor_y);
+		dev_fb_setcursor(d->vfb_data, d->cursor_x, d->cursor_y, on,
+		    d->cursor_xsize, d->cursor_ysize * ysize_mul);
+	}
+#endif
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_bt431_init():
+ */
+void dev_bt431_init(struct memory *mem, uint64_t baseaddr,
+	struct vfb_data *vfb_data, int planes)
+{
+	struct bt431_data *d;
+
+	CHECK_ALLOCATION(d = (struct bt431_data *) malloc(sizeof(struct bt431_data)));
+	memset(d, 0, sizeof(struct bt431_data));
+
+	d->vfb_data     = vfb_data;
+	d->planes       = planes;
+	d->cursor_x     = -1;
+	d->cursor_y     = -1;
+	d->cursor_xsize = d->cursor_ysize = 8;	/*  anything  */
+
+	memory_device_register(mem, "bt431", baseaddr, DEV_BT431_LENGTH,
+	    dev_bt431_access, (void *)d, DM_DEFAULT, NULL);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_bt431.cc gxemul-0.7.0+dfsg/src/devices/dev_bt431.cc
--- gxemul-0.6.2/src/devices/dev_bt431.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_bt431.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,213 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Brooktree BT431, used by TURBOchannel graphics cards
- *
- *  TODO.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "devices.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/bt431reg.h"
-
-
-struct bt431_data {
-	uint32_t	bt431_reg[DEV_BT431_NREGS];
-
-	unsigned char	cur_addr_hi;
-	unsigned char	cur_addr_lo;
-
-	int		planes;
-	int		cursor_on;
-	int		cursor_x;
-	int		cursor_y;
-	int		cursor_xsize;
-	int		cursor_ysize;
-
-	struct vfb_data *vfb_data;
-};
-
-
-DEVICE_ACCESS(bt431)
-{
-	struct bt431_data *d = (struct bt431_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int btaddr;
-#if 0
-	int on, new_cursor_x, new_cursor_y;
-#endif
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	btaddr = ((d->cur_addr_hi << 8) + d->cur_addr_lo) % DEV_BT431_NREGS;
-
-/*  TODO  */
-
-	/*  Read from/write to the bt431:  */
-	switch (relative_addr) {
-	case 0x00:		/*  Low byte of address:  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ bt431: write to Low Address Byte, "
-			    "0x%02x ]\n", (int)idata);
-			d->cur_addr_lo = idata;
-		} else {
-			odata = d->cur_addr_lo;
-			debug("[ bt431: read from Low Address Byte: "
-			    "0x%0x ]\n", (int)odata);
-		}
-		break;
-	case 0x04:		/*  High byte of address:  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ bt431: write to High Address Byte, "
-			    "0x%02x ]\n", (int)idata);
-			d->cur_addr_hi = idata;
-		} else {
-			odata = d->cur_addr_hi;
-			debug("[ bt431: read from High Address Byte: "
-			    "0x%0x ]\n", (int)odata);
-		}
-		break;
-	case 0x08:		/*  Register access:  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ bt431: write to BT431 register 0x%04x, "
-			    "value 0x%02x ]\n", btaddr, (int)idata);
-			d->bt431_reg[btaddr] = idata;
-
-#if 0
-			/*  Write to cursor bitmap:  */
-			if (btaddr >= 0x400)
-				bt431_sync_xysize(d);
-#endif
-		} else {
-			odata = d->bt431_reg[btaddr];
-			debug("[ bt431: read from BT431 register 0x%04x, "
-			    "value 0x%02x ]\n", btaddr, (int)odata);
-		}
-
-		/*  Go to next register:  */
-		d->cur_addr_lo ++;
-		if (d->cur_addr_lo == 0)
-			d->cur_addr_hi ++;
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ bt431: unimplemented write to address "
-			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
-			    (int)idata);
-		} else {
-			debug("[ bt431: unimplemented read from address "
-			    "0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-#if 0
-
-TODO: This is from bt459!
-
-	/*  NetBSD uses 370,37 as magic values.  */
-	new_cursor_x = (d->bt431_reg[BT431_REG_CXLO] & 255) +
-	    ((d->bt431_reg[BT431_REG_CXHI] & 255) << 8) - 370;
-	new_cursor_y = (d->bt431_reg[BT431_REG_CYLO] & 255) +
-	    ((d->bt431_reg[BT431_REG_CYHI] & 255) << 8) - 37;
-
-	/*  TODO: what do the bits in the CCR do?  */
-	on = d->bt431_reg[BT431_REG_CCR] ? 1 : 0;
-
-on = 1;
-
-	if (new_cursor_x != d->cursor_x || new_cursor_y != d->cursor_y ||
-	    on != d->cursor_on) {
-		int ysize_mul = 1;
-
-		d->cursor_x = new_cursor_x;
-		d->cursor_y = new_cursor_y;
-		d->cursor_on = on;
-
-		/*
-		 *  Ugly hack for Ultrix:
-		 *
-		 *  Ultrix and NetBSD assume that the cursor works differently.
-		 *  Ultrix uses the 370,38 coordinates, but draws the cursor
-		 *  upwards. NetBSD draws it downwards.  Ultrix also makes the
-		 *  cursor smaller (?).
-		 *
-		 *  TODO:  This actually depends on which ultrix kernel you use.
-		 *  Clearly, the BT459 emulation is not implemented well
-		 *  enough yet.
-		 *
-		 *  TODO:  Find out why? Is it because of special BT459
-		 *  commands?
-		 *
-		 *  TODO: Is the above text even valid anymore? :-)
-		 */
-		if (!(d->bt431_reg[BT431_REG_CCR] & 1)) {
-/*			ysize_mul = 4; */
-			d->cursor_y += 5 - (d->cursor_ysize * ysize_mul);
-		}
-
-		debug("[ bt431: cursor = %03i,%03i ]\n", d->cursor_x,
-		    d->cursor_y);
-		dev_fb_setcursor(d->vfb_data, d->cursor_x, d->cursor_y, on,
-		    d->cursor_xsize, d->cursor_ysize * ysize_mul);
-	}
-#endif
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_bt431_init():
- */
-void dev_bt431_init(struct memory *mem, uint64_t baseaddr,
-	struct vfb_data *vfb_data, int planes)
-{
-	struct bt431_data *d;
-
-	CHECK_ALLOCATION(d = (struct bt431_data *) malloc(sizeof(struct bt431_data)));
-	memset(d, 0, sizeof(struct bt431_data));
-
-	d->vfb_data     = vfb_data;
-	d->planes       = planes;
-	d->cursor_x     = -1;
-	d->cursor_y     = -1;
-	d->cursor_xsize = d->cursor_ysize = 8;	/*  anything  */
-
-	memory_device_register(mem, "bt431", baseaddr, DEV_BT431_LENGTH,
-	    dev_bt431_access, (void *)d, DM_DEFAULT, NULL);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_bt455.c gxemul-0.7.0+dfsg/src/devices/dev_bt455.c
--- gxemul-0.6.2/src/devices/dev_bt455.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_bt455.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,181 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Brooktree BT455, used by TURBOchannel graphics cards
+ *
+ *  TODO:  This is hardcoded to only use 16 grayscales, using only the
+ *  green component of the palette.  Perhaps some other graphics card uses
+ *  the BT455 as well; if so then this device must be re-hacked.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "devices.h"
+#include "memory.h"
+#include "misc.h"
+
+
+
+struct bt455_data {
+	unsigned char	addr_cmap;
+	unsigned char	addr_cmap_data;
+	unsigned char	addr_clr;
+	unsigned char	addr_ovly;
+
+	int		cur_rgb_offset;
+
+	struct vfb_data *vfb_data;
+	unsigned char	*rgb_palette;		/*  ptr to 256 * 3 (r,g,b)  */
+};
+
+
+DEVICE_ACCESS(bt455)
+{
+	struct bt455_data *d = (struct bt455_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int i, modified;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  Read from/write to the bt455:  */
+	switch (relative_addr) {
+	case 0x00:		/*  addr_cmap  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ bt455: write to addr_cmap, 0x%02x ]\n", idata);
+			d->addr_cmap = idata;
+			d->cur_rgb_offset = (d->addr_cmap & 0xf) * 3;
+		} else {
+			odata = d->addr_cmap;
+			debug("[ bt455: read from addr_cmap: 0x%0x ]\n", odata);
+		}
+		break;
+	case 0x04:		/*  addr_cmap_data  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ bt455: write to addr_cmap_data, 0x%02x ]\n",
+			    (int)idata);
+			d->addr_cmap_data = idata;
+
+			modified = 0;
+
+			/*  Only write on updates to the Green value:  */
+			if ((d->cur_rgb_offset % 3) == 1) {
+				/*  Update 16 copies:  */
+				for (i=0; i<16; i++) {
+					int addr = (d->cur_rgb_offset + 16*i)
+					    % 0x300;
+					int newvalue = idata * 0x11;
+
+					if (d->rgb_palette[(addr / 3) * 3 + 0]
+					    != newvalue ||
+					    d->rgb_palette[(addr / 3) * 3 + 1]
+					    != newvalue ||
+					    d->rgb_palette[(addr / 3) * 3 + 2]
+					    != newvalue)
+						modified = 1;
+
+					d->rgb_palette[(addr / 3) * 3 + 0] =
+					    d->rgb_palette[(addr / 3) * 3 + 1] =
+					    d->rgb_palette[(addr / 3) * 3 + 2] =
+					    newvalue;
+				}
+			}
+
+			if (modified) {
+				d->vfb_data->update_x1 = 0;
+				d->vfb_data->update_x2 = d->vfb_data->xsize - 1;
+				d->vfb_data->update_y1 = 0;
+				d->vfb_data->update_y2 = d->vfb_data->ysize - 1;
+			}
+
+			/*  Advance to next palette byte:  */
+			d->cur_rgb_offset ++;
+		} else {
+			odata = d->addr_cmap_data;
+			debug("[ bt455: read from addr_cmap_data: 0x%0x ]\n",
+			    (int)odata);
+		}
+		break;
+	case 0x08:		/*  addr_clr  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ bt455: write to addr_clr, value 0x%02x ]\n",
+			    (int)idata);
+			d->addr_clr = idata;
+		} else {
+			odata = d->addr_clr;
+			debug("[ bt455: read from addr_clr: value 0x%02x ]\n",
+			    (int)odata);
+		}
+		break;
+	case 0x0c:		/*  addr_ovly  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ bt455: write to addr_ovly, value 0x%02x ]\n",
+			    (int)idata);
+			d->addr_ovly = idata;
+		} else {
+			odata = d->addr_ovly;
+			debug("[ bt455: read from addr_ovly: value 0x%02x ]\n",
+			    (int)odata);
+		}
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ bt455: unimplemented write to address 0x%x,"
+			    " data=0x%02x ]\n", (int)relative_addr, (int)idata);
+		} else {
+			debug("[ bt455: unimplemented read from address "
+			    "0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_bt455_init():
+ */
+void dev_bt455_init(struct memory *mem, uint64_t baseaddr,
+	struct vfb_data *vfb_data)
+{
+	struct bt455_data *d;
+
+	CHECK_ALLOCATION(d = (struct bt455_data *) malloc(sizeof(struct bt455_data)));
+	memset(d, 0, sizeof(struct bt455_data));
+
+	d->vfb_data     = vfb_data;
+	d->rgb_palette  = vfb_data->rgb_palette;
+
+	memory_device_register(mem, "bt455", baseaddr, DEV_BT455_LENGTH,
+	    dev_bt455_access, (void *)d, DM_DEFAULT, NULL);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_bt455.cc gxemul-0.7.0+dfsg/src/devices/dev_bt455.cc
--- gxemul-0.6.2/src/devices/dev_bt455.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_bt455.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,181 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Brooktree BT455, used by TURBOchannel graphics cards
- *
- *  TODO:  This is hardcoded to only use 16 grayscales, using only the
- *  green component of the palette.  Perhaps some other graphics card uses
- *  the BT455 as well; if so then this device must be re-hacked.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "devices.h"
-#include "memory.h"
-#include "misc.h"
-
-
-
-struct bt455_data {
-	unsigned char	addr_cmap;
-	unsigned char	addr_cmap_data;
-	unsigned char	addr_clr;
-	unsigned char	addr_ovly;
-
-	int		cur_rgb_offset;
-
-	struct vfb_data *vfb_data;
-	unsigned char	*rgb_palette;		/*  ptr to 256 * 3 (r,g,b)  */
-};
-
-
-DEVICE_ACCESS(bt455)
-{
-	struct bt455_data *d = (struct bt455_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int i, modified;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  Read from/write to the bt455:  */
-	switch (relative_addr) {
-	case 0x00:		/*  addr_cmap  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ bt455: write to addr_cmap, 0x%02x ]\n", idata);
-			d->addr_cmap = idata;
-			d->cur_rgb_offset = (d->addr_cmap & 0xf) * 3;
-		} else {
-			odata = d->addr_cmap;
-			debug("[ bt455: read from addr_cmap: 0x%0x ]\n", odata);
-		}
-		break;
-	case 0x04:		/*  addr_cmap_data  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ bt455: write to addr_cmap_data, 0x%02x ]\n",
-			    (int)idata);
-			d->addr_cmap_data = idata;
-
-			modified = 0;
-
-			/*  Only write on updates to the Green value:  */
-			if ((d->cur_rgb_offset % 3) == 1) {
-				/*  Update 16 copies:  */
-				for (i=0; i<16; i++) {
-					int addr = (d->cur_rgb_offset + 16*i)
-					    % 0x300;
-					int newvalue = idata * 0x11;
-
-					if (d->rgb_palette[(addr / 3) * 3 + 0]
-					    != newvalue ||
-					    d->rgb_palette[(addr / 3) * 3 + 1]
-					    != newvalue ||
-					    d->rgb_palette[(addr / 3) * 3 + 2]
-					    != newvalue)
-						modified = 1;
-
-					d->rgb_palette[(addr / 3) * 3 + 0] =
-					    d->rgb_palette[(addr / 3) * 3 + 1] =
-					    d->rgb_palette[(addr / 3) * 3 + 2] =
-					    newvalue;
-				}
-			}
-
-			if (modified) {
-				d->vfb_data->update_x1 = 0;
-				d->vfb_data->update_x2 = d->vfb_data->xsize - 1;
-				d->vfb_data->update_y1 = 0;
-				d->vfb_data->update_y2 = d->vfb_data->ysize - 1;
-			}
-
-			/*  Advance to next palette byte:  */
-			d->cur_rgb_offset ++;
-		} else {
-			odata = d->addr_cmap_data;
-			debug("[ bt455: read from addr_cmap_data: 0x%0x ]\n",
-			    (int)odata);
-		}
-		break;
-	case 0x08:		/*  addr_clr  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ bt455: write to addr_clr, value 0x%02x ]\n",
-			    (int)idata);
-			d->addr_clr = idata;
-		} else {
-			odata = d->addr_clr;
-			debug("[ bt455: read from addr_clr: value 0x%02x ]\n",
-			    (int)odata);
-		}
-		break;
-	case 0x0c:		/*  addr_ovly  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ bt455: write to addr_ovly, value 0x%02x ]\n",
-			    (int)idata);
-			d->addr_ovly = idata;
-		} else {
-			odata = d->addr_ovly;
-			debug("[ bt455: read from addr_ovly: value 0x%02x ]\n",
-			    (int)odata);
-		}
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ bt455: unimplemented write to address 0x%x,"
-			    " data=0x%02x ]\n", (int)relative_addr, (int)idata);
-		} else {
-			debug("[ bt455: unimplemented read from address "
-			    "0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_bt455_init():
- */
-void dev_bt455_init(struct memory *mem, uint64_t baseaddr,
-	struct vfb_data *vfb_data)
-{
-	struct bt455_data *d;
-
-	CHECK_ALLOCATION(d = (struct bt455_data *) malloc(sizeof(struct bt455_data)));
-	memset(d, 0, sizeof(struct bt455_data));
-
-	d->vfb_data     = vfb_data;
-	d->rgb_palette  = vfb_data->rgb_palette;
-
-	memory_device_register(mem, "bt455", baseaddr, DEV_BT455_LENGTH,
-	    dev_bt455_access, (void *)d, DM_DEFAULT, NULL);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_bt459.c gxemul-0.7.0+dfsg/src/devices/dev_bt459.c
--- gxemul-0.6.2/src/devices/dev_bt459.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_bt459.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,586 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Brooktree BT459, used by TURBOchannel graphics cards
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "x11.h"
+
+#include "thirdparty/bt459.h"
+
+
+#ifdef WITH_X11
+#include <X11/Xlib.h>     
+#include <X11/Xutil.h>
+#endif
+
+extern int quiet_mode;
+
+
+/*  #define BT459_DEBUG  */
+/*  #define WITH_CURSOR_DEBUG  */
+#define BT459_TICK_SHIFT	14
+
+struct bt459_data {
+	uint32_t	bt459_reg[DEV_BT459_NREGS];
+
+	unsigned char	cur_addr_hi;
+	unsigned char	cur_addr_lo;
+
+	int		planes;
+	int		type;
+
+	struct interrupt irq;
+	int		interrupts_enable;
+	int		interrupt_time;
+	int		interrupt_time_reset_value;
+
+	int		cursor_x_add;
+	int		cursor_y_add;
+
+	int		need_to_redraw_whole_screen;
+
+	int		need_to_update_cursor_shape;
+	int		cursor_on;
+	int		cursor_x;
+	int		cursor_y;
+	int		cursor_xsize;
+	int		cursor_ysize;
+
+	int		palette_sub_offset;	/*  0, 1, or 2  */
+
+	struct vfb_data *vfb_data;
+
+	/*
+	 *  There is one pointer to the framebuffer's RGB palette,
+	 *  and then a local copy of the palette.  256 * 3 bytes (r,g,b).
+	 *  The reason for this is that when we need to blank the screen
+	 *  (ie video_on = 0), we can set the framebuffer's palette to all
+	 *  zeroes, but keep our own copy intact, to be reused later again
+	 *  when the screen is unblanked.
+	 */
+	int		video_on;
+	unsigned char	*rgb_palette;		/*  256 * 3 (r,g,b)  */
+	unsigned char	local_rgb_palette[256 * 3];
+};
+
+
+/*
+ *  bt459_update_X_cursor():
+ *
+ *  This routine takes the color values in the cursor RAM area, and put them
+ *  in the framebuffer window's cursor_pixels.
+ *
+ *  d->cursor_xsize and ysize are also updated.
+ */
+static void bt459_update_X_cursor(struct cpu *cpu, struct bt459_data *d)
+{
+	int i, x,y, xmax=0, ymax=0;
+#ifdef WITH_X11
+	int bw_only = 1;
+#endif
+
+	/*  First, let's calculate the size of the cursor:  */
+	for (y=0; y<64; y++)
+		for (x=0; x<64; x+=4) {
+			int reg = BT459_REG_CRAM_BASE + y*16 + x/4;
+			unsigned char data = d->bt459_reg[reg];
+
+			if (data)
+				ymax = y;
+
+			for (i=0; i<4; i++) {
+				int color = (data >> (6-2*i)) & 3;
+				if (color != 0)
+					xmax = x + i;
+#ifdef WITH_X11
+				if (color != 0 && color != 3)
+					bw_only = 0;
+#endif
+			}
+		}
+
+	d->cursor_xsize = xmax + 1;
+	d->cursor_ysize = ymax + 1;
+
+	/*
+	 *  The 'bw_only' hack is because it is nicer to have the b/w
+	 *  text cursor invert whatever it is standing on, not just overwrite
+	 *  it with a big white box.
+	 *
+	 *  The following seems to work with NetBSD/OpenBSD/Ultrix/Sprite:
+	 *	0 = transparent, 1 and 2 = use the color specified by
+	 *	BT459_REG_CCOLOR_2, 3 = reverse of color 1/2.
+	 */
+
+#ifdef WITH_X11
+	if (cpu->machine->x11_md.in_use && d->vfb_data->fb_window != NULL) {
+		for (y=0; y<=ymax; y++) {
+			for (x=0; x<=xmax; x+=4) {
+				struct fb_window *win = d->vfb_data->fb_window;
+				int reg = BT459_REG_CRAM_BASE + y*16 + x/4;
+				unsigned char data = d->bt459_reg[reg];
+
+				for (i=0; i<4; i++) {
+					int color = (data >> (6-2*i)) & 3;
+					int pixelvalue;
+
+					if (bw_only) {
+						if (color)
+							pixelvalue =
+							    CURSOR_COLOR_INVERT;
+						else
+							pixelvalue = 0;
+					} else {
+						pixelvalue =
+						    CURSOR_COLOR_TRANSPARENT;
+						switch (color) {
+						case 1:
+						case 2:	pixelvalue = (d->
+							    bt459_reg[
+							    BT459_REG_CCOLOR_2]
+							    >> 4) & 0xf;
+							break;
+						case 3:	pixelvalue = 15 -
+							    ((d->bt459_reg[
+							    BT459_REG_CCOLOR_2]
+							    >> 4) & 0xf);
+							break;
+						}
+					}
+
+					win->cursor_pixels[y][x+i] =
+					    pixelvalue;
+#ifdef WITH_CURSOR_DEBUG
+printf("%i", color);
+#endif
+				}
+			}
+#ifdef WITH_CURSOR_DEBUG
+printf("\n");
+#endif
+		}
+#ifdef WITH_CURSOR_DEBUG
+printf("color 1,2,3 = 0x%02x, 0x%02x, 0x%02x\n",
+    d->bt459_reg[BT459_REG_CCOLOR_1],
+    d->bt459_reg[BT459_REG_CCOLOR_2],
+    d->bt459_reg[BT459_REG_CCOLOR_3]);
+printf("\n");
+#endif
+		/*
+		 *  Make sure the cursor is redrawn, if it is on:
+		 *
+		 *  How does this work? Well, 0 is off, and non-zero is on,
+		 *  but if the old and new differ, the cursor is redrawn.
+		 *  (Hopefully this will "never" overflow.)
+		 */
+		if (d->cursor_on)
+			d->cursor_on ++;
+	}
+#endif
+}
+
+
+/*
+ *  bt459_update_cursor_position():
+ */
+static void bt459_update_cursor_position(struct bt459_data *d,
+	int old_cursor_on)
+{
+	int new_cursor_x = (d->bt459_reg[BT459_REG_CXLO] & 255) +
+	    ((d->bt459_reg[BT459_REG_CXHI] & 255) << 8) - d->cursor_x_add;
+	int new_cursor_y = (d->bt459_reg[BT459_REG_CYLO] & 255) +
+	    ((d->bt459_reg[BT459_REG_CYHI] & 255) << 8) - d->cursor_y_add;
+
+	if (new_cursor_x != d->cursor_x || new_cursor_y != d->cursor_y ||
+	    d->cursor_on != old_cursor_on) {
+		int on;
+
+		d->cursor_x = new_cursor_x;
+		d->cursor_y = new_cursor_y;
+
+		if (!quiet_mode)
+			debug("[ bt459: cursor = %03i,%03i ]\n",
+			    d->cursor_x, d->cursor_y);
+
+		on = d->cursor_on;
+		if (d->cursor_xsize == 0 || d->cursor_ysize == 0)
+			on = 0;
+
+		dev_fb_setcursor(d->vfb_data, d->cursor_x, d->cursor_y,
+		    on, d->cursor_xsize, d->cursor_ysize);
+	}
+}
+
+
+DEVICE_TICK(bt459)
+{
+	struct bt459_data *d = (struct bt459_data *) extra;
+	int old_cursor_on = d->cursor_on;
+
+	if (d->need_to_update_cursor_shape) {
+		d->need_to_update_cursor_shape = 0;
+		bt459_update_X_cursor(cpu, d);
+		bt459_update_cursor_position(d, old_cursor_on);
+	}
+
+	if (d->need_to_redraw_whole_screen) {
+		d->vfb_data->update_x1 = 0;
+		d->vfb_data->update_x2 = d->vfb_data->xsize - 1;
+		d->vfb_data->update_y1 = 0;
+		d->vfb_data->update_y2 = d->vfb_data->ysize - 1;
+		d->need_to_redraw_whole_screen = 0;
+	}
+
+	/*
+	 *  Vertical retrace interrupts. (This hack is kind of ugly.)
+	 *  Once every 'interrupt_time_reset_value', the interrupt is
+	 *  asserted. It is acked either manually (by someone reading
+	 *  a normal BT459 register or the Interrupt ack register),
+	 *  or after another tick has passed.  (This is to prevent
+	 *  lockups from unhandled interrupts.)
+	 */
+	if (d->type != BT459_PX && d->interrupts_enable) {
+		d->interrupt_time --;
+		if (d->interrupt_time < 0) {
+			d->interrupt_time = d->interrupt_time_reset_value;
+			INTERRUPT_ASSERT(d->irq);
+		} else
+			INTERRUPT_DEASSERT(d->irq);
+	}
+}
+
+
+DEVICE_ACCESS(bt459_irq)
+{
+	struct bt459_data *d = (struct bt459_data *) extra;
+	// uint64_t idata = 0;
+	uint64_t odata = 0;
+
+//	if (writeflag == MEM_WRITE)
+//		idata = memory_readmax64(cpu, data, len);
+
+#ifdef BT459_DEBUG
+	fatal("[ bt459: IRQ ack ]\n");
+#endif
+
+	d->interrupts_enable = 1;
+
+	INTERRUPT_DEASSERT(d->irq);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(bt459)
+{
+	struct bt459_data *d = (struct bt459_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int btaddr, old_cursor_on = d->cursor_on, modified;
+
+	idata = memory_readmax64(cpu, data, len);
+
+#ifdef BT459_DEBUG
+	if (writeflag == MEM_WRITE)
+		fatal("[ bt459: write to addr 0x%02x: %08x ]\n",
+		    (int)relative_addr, (int)idata);
+#endif
+
+	/*
+	 *  Vertical retrace interrupts are acked either by
+	 *  accessing a normal BT459 register, or the irq register,
+	 *  or by simply "missing" it.
+	 */
+	INTERRUPT_DEASSERT(d->irq);
+
+	/*  ID register is read-only, should always be 0x4a or 0x4a4a4a:  */
+	if (d->planes == 24)
+		d->bt459_reg[BT459_REG_ID] = 0x4a4a4a;
+	else {
+		/*
+		 *  TODO:  Is it really 0x4a, or 0x4a0000?
+		 *  Ultrix panics with a "bad VDAC ID" message if 0x4a
+		 *  is returned.
+		 */
+		d->bt459_reg[BT459_REG_ID] = 0x4a0000;
+	}
+
+	btaddr = ((d->cur_addr_hi << 8) + d->cur_addr_lo) % DEV_BT459_NREGS;
+
+	/*  Read from/write to the bt459:  */
+	switch (relative_addr) {
+	case 0x00:		/*  Low byte of address:  */
+		if (writeflag == MEM_WRITE) {
+			if (!quiet_mode)
+				debug("[ bt459: write to Low Address Byte, "
+				    "0x%02x ]\n", (int)idata);
+			d->cur_addr_lo = idata;
+			d->palette_sub_offset = 0;
+		} else {
+			odata = d->cur_addr_lo;
+			if (!quiet_mode)
+				debug("[ bt459: read from Low Address Byte: "
+				    "0x%0x ]\n", (int)odata);
+		}
+		break;
+	case 0x04:		/*  High byte of address:  */
+		if (writeflag == MEM_WRITE) {
+			if (!quiet_mode)
+				debug("[ bt459: write to High Address Byte, "
+				    "0x%02x ]\n", (int)idata);
+			d->cur_addr_hi = idata;
+			d->palette_sub_offset = 0;
+		} else {
+			odata = d->cur_addr_hi;
+			if (!quiet_mode)
+				debug("[ bt459: read from High Address Byte: "
+				    "0x%0x ]\n", (int)odata);
+		}
+		break;
+	case 0x08:		/*  Register access:  */
+		if (writeflag == MEM_WRITE) {
+			if (!quiet_mode)
+				debug("[ bt459: write to BT459 register "
+				    "0x%04x, value 0x%02x ]\n", btaddr,
+				    (int)idata);
+			modified = (d->bt459_reg[btaddr] != idata);
+			d->bt459_reg[btaddr] = idata;
+
+			switch (btaddr) {
+			case BT459_REG_CCOLOR_1:
+			case BT459_REG_CCOLOR_2:
+			case BT459_REG_CCOLOR_3:
+				if (modified)
+					d->need_to_update_cursor_shape = 1;
+				break;
+			case BT459_REG_PRM:
+				/*
+				 *  NetBSD writes 0x00 to this register to
+				 *  blank the screen (video off), and 0xff
+				 *  to turn the screen on.
+				 */
+				switch (idata & 0xff) {
+				case 0:	d->video_on = 0;
+					memset(d->rgb_palette, 0, 256*3);
+					d->need_to_redraw_whole_screen = 1;
+					debug("[ bt459: video OFF ]\n");
+					break;
+				default:d->video_on = 1;
+					memcpy(d->rgb_palette,
+					    d->local_rgb_palette, 256*3);
+					d->need_to_redraw_whole_screen = 1;
+					debug("[ bt459: video ON ]\n");
+				}
+				break;
+			case BT459_REG_CCR:
+				/*  Cursor control register:  */
+				switch (idata & 0xff) {
+				case 0x00:	d->cursor_on = 0; break;
+				case 0xc0:
+				case 0xc1:	d->cursor_on = 1; break;
+				default:
+					fatal("[ bt459: unimplemented CCR "
+					    "value 0x%08x ]\n", (int)idata);
+				}
+				if (modified)
+					d->need_to_update_cursor_shape = 1;
+				break;
+			default:
+				if (btaddr < 0x100)
+					fatal("[ bt459: write to BT459 "
+					    "register 0x%04x, value 0x%02x ]\n",
+					    btaddr, (int)idata);
+			}
+
+			/*  Write to cursor bitmap:  */
+			if (btaddr >= BT459_REG_CRAM_BASE && modified)
+				d->need_to_update_cursor_shape = 1;
+		} else {
+			odata = d->bt459_reg[btaddr];
+
+			/*  Perhaps this hack is not necessary:  */
+			if (btaddr == BT459_REG_ID && len==1)
+				odata = (odata >> 16) & 255;
+
+			if (!quiet_mode)
+				debug("[ bt459: read from BT459 register "
+				    "0x%04x, value 0x%02x ]\n", btaddr,
+				    (int)odata);
+		}
+
+		/*  Go to next register:  */
+		d->cur_addr_lo ++;
+		if (d->cur_addr_lo == 0)
+			d->cur_addr_hi ++;
+		break;
+	case 0xc:		/*  Color map:  */
+		if (writeflag == MEM_WRITE) {
+			idata &= 255;
+			if (!quiet_mode)
+				debug("[ bt459: write to BT459 colormap "
+				    "0x%04x subaddr %i, value 0x%02x ]\n",
+				    btaddr, d->palette_sub_offset, (int)idata);
+
+			if (btaddr < 0x100) {
+				if (d->video_on &&
+				    d->local_rgb_palette[(btaddr & 0xff) * 3
+				    + d->palette_sub_offset] != idata)
+					d->need_to_redraw_whole_screen = 1;
+
+				/*
+				 *  Actually, the palette should only be
+				 *  updated after the third write,
+				 *  but this should probably work fine too:
+				 */
+				d->local_rgb_palette[(btaddr & 0xff) * 3
+				    + d->palette_sub_offset] = idata;
+
+				if (d->video_on)
+					d->rgb_palette[(btaddr & 0xff) * 3
+					    + d->palette_sub_offset] = idata;
+			}
+		} else {
+			if (btaddr < 0x100)
+				odata = d->local_rgb_palette[(btaddr & 0xff)
+				    * 3 + d->palette_sub_offset];
+			if (!quiet_mode)
+				debug("[ bt459: read from BT459 colormap "
+				    "0x%04x subaddr %i, value 0x%02x ]\n",
+				    btaddr, d->palette_sub_offset, (int)odata);
+		}
+
+		d->palette_sub_offset ++;
+		if (d->palette_sub_offset >= 3) {
+			d->palette_sub_offset = 0;
+
+			d->cur_addr_lo ++;
+			if (d->cur_addr_lo == 0)
+				d->cur_addr_hi ++;
+		}
+
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ bt459: unimplemented write to address 0x%x, "
+			    "data=0x%02x ]\n", (int)relative_addr, (int)idata);
+		} else {
+			debug("[ bt459: unimplemented read from address "
+			    "0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+
+	bt459_update_cursor_position(d, old_cursor_on);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+#ifdef BT459_DEBUG
+	if (writeflag == MEM_READ)
+		fatal("[ bt459: read from addr 0x%02x: %08x ]\n",
+		    (int)relative_addr, (int)idata);
+#endif
+
+	return 1;
+}
+
+
+/*
+ *  dev_bt459_init():
+ */
+void dev_bt459_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, uint64_t baseaddr_irq, struct vfb_data *vfb_data,
+	int planes, const char *irq_path, int type)
+{
+	struct bt459_data *d;
+
+	CHECK_ALLOCATION(d = (struct bt459_data *) malloc(sizeof(struct bt459_data)));
+	memset(d, 0, sizeof(struct bt459_data));
+
+	INTERRUPT_CONNECT(irq_path, d->irq);
+
+	d->vfb_data     = vfb_data;
+	d->rgb_palette  = vfb_data->rgb_palette;
+	d->planes       = planes;
+	d->type		= type;
+	d->cursor_x     = -1;
+	d->cursor_y     = -1;
+	d->cursor_xsize = d->cursor_ysize = 0;	/*  anything  */
+	d->video_on     = 1;
+
+	/*
+	 *  These offsets are based on those mentioned in NetBSD,
+	 *  and then adjusted to look good with both NetBSD and
+	 *  Ultrix:
+	 */
+	switch (d->type) {
+	case BT459_PX:
+		d->cursor_x_add = 370;
+		d->cursor_y_add =  37;
+		break;
+	case BT459_BA:
+		d->cursor_x_add = 220;
+		d->cursor_y_add =  35;
+		break;
+	case BT459_BBA:
+		if (vfb_data->xsize == 1280) {
+			/*  1280x1024:  */
+			d->cursor_x_add = 368;
+			d->cursor_y_add =  38;
+		} else {
+			/*  1024x864:  */
+			d->cursor_x_add = 220;
+			d->cursor_y_add =  35;
+		}
+		break;
+	}
+
+	d->interrupt_time_reset_value = 500;
+
+	memory_device_register(mem, "bt459", baseaddr, DEV_BT459_LENGTH,
+	    dev_bt459_access, (void *)d, DM_DEFAULT, NULL);
+
+	if (baseaddr_irq != 0)
+		memory_device_register(mem, "bt459_irq", baseaddr_irq, 0x10000,
+		    dev_bt459_irq_access, (void *)d, DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(machine, dev_bt459_tick, d,
+	    BT459_TICK_SHIFT);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_bt459.cc gxemul-0.7.0+dfsg/src/devices/dev_bt459.cc
--- gxemul-0.6.2/src/devices/dev_bt459.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_bt459.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,581 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Brooktree BT459, used by TURBOchannel graphics cards
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "x11.h"
-
-#include "thirdparty/bt459.h"
-
-
-#ifdef WITH_X11
-#include <X11/Xlib.h>     
-#include <X11/Xutil.h>
-#endif
-
-extern int quiet_mode;
-
-
-/*  #define BT459_DEBUG  */
-/*  #define WITH_CURSOR_DEBUG  */
-#define BT459_TICK_SHIFT	14
-
-struct bt459_data {
-	uint32_t	bt459_reg[DEV_BT459_NREGS];
-
-	unsigned char	cur_addr_hi;
-	unsigned char	cur_addr_lo;
-
-	int		planes;
-	int		type;
-
-	struct interrupt irq;
-	int		interrupts_enable;
-	int		interrupt_time;
-	int		interrupt_time_reset_value;
-
-	int		cursor_x_add;
-	int		cursor_y_add;
-
-	int		need_to_redraw_whole_screen;
-
-	int		need_to_update_cursor_shape;
-	int		cursor_on;
-	int		cursor_x;
-	int		cursor_y;
-	int		cursor_xsize;
-	int		cursor_ysize;
-
-	int		palette_sub_offset;	/*  0, 1, or 2  */
-
-	struct vfb_data *vfb_data;
-
-	/*
-	 *  There is one pointer to the framebuffer's RGB palette,
-	 *  and then a local copy of the palette.  256 * 3 bytes (r,g,b).
-	 *  The reason for this is that when we need to blank the screen
-	 *  (ie video_on = 0), we can set the framebuffer's palette to all
-	 *  zeroes, but keep our own copy intact, to be reused later again
-	 *  when the screen is unblanked.
-	 */
-	int		video_on;
-	unsigned char	*rgb_palette;		/*  256 * 3 (r,g,b)  */
-	unsigned char	local_rgb_palette[256 * 3];
-};
-
-
-/*
- *  bt459_update_X_cursor():
- *
- *  This routine takes the color values in the cursor RAM area, and put them
- *  in the framebuffer window's cursor_pixels.
- *
- *  d->cursor_xsize and ysize are also updated.
- */
-static void bt459_update_X_cursor(struct cpu *cpu, struct bt459_data *d)
-{
-	int i, x,y, xmax=0, ymax=0;
-	int bw_only = 1;
-
-	/*  First, let's calculate the size of the cursor:  */
-	for (y=0; y<64; y++)
-		for (x=0; x<64; x+=4) {
-			int reg = BT459_REG_CRAM_BASE + y*16 + x/4;
-			unsigned char data = d->bt459_reg[reg];
-
-			if (data)
-				ymax = y;
-
-			for (i=0; i<4; i++) {
-				int color = (data >> (6-2*i)) & 3;
-				if (color != 0)
-					xmax = x + i;
-				if (color != 0 && color != 3)
-					bw_only = 0;
-			}
-		}
-
-	d->cursor_xsize = xmax + 1;
-	d->cursor_ysize = ymax + 1;
-
-	/*
-	 *  The 'bw_only' hack is because it is nicer to have the b/w
-	 *  text cursor invert whatever it is standing on, not just overwrite
-	 *  it with a big white box.
-	 *
-	 *  The following seems to work with NetBSD/OpenBSD/Ultrix/Sprite:
-	 *	0 = transparent, 1 and 2 = use the color specified by
-	 *	BT459_REG_CCOLOR_2, 3 = reverse of color 1/2.
-	 */
-
-#ifdef WITH_X11
-	if (cpu->machine->x11_md.in_use && d->vfb_data->fb_window != NULL) {
-		for (y=0; y<=ymax; y++) {
-			for (x=0; x<=xmax; x+=4) {
-				struct fb_window *win = d->vfb_data->fb_window;
-				int reg = BT459_REG_CRAM_BASE + y*16 + x/4;
-				unsigned char data = d->bt459_reg[reg];
-
-				for (i=0; i<4; i++) {
-					int color = (data >> (6-2*i)) & 3;
-					int pixelvalue;
-
-					if (bw_only) {
-						if (color)
-							pixelvalue =
-							    CURSOR_COLOR_INVERT;
-						else
-							pixelvalue = 0;
-					} else {
-						pixelvalue =
-						    CURSOR_COLOR_TRANSPARENT;
-						switch (color) {
-						case 1:
-						case 2:	pixelvalue = (d->
-							    bt459_reg[
-							    BT459_REG_CCOLOR_2]
-							    >> 4) & 0xf;
-							break;
-						case 3:	pixelvalue = 15 -
-							    ((d->bt459_reg[
-							    BT459_REG_CCOLOR_2]
-							    >> 4) & 0xf);
-							break;
-						}
-					}
-
-					win->cursor_pixels[y][x+i] =
-					    pixelvalue;
-#ifdef WITH_CURSOR_DEBUG
-printf("%i", color);
-#endif
-				}
-			}
-#ifdef WITH_CURSOR_DEBUG
-printf("\n");
-#endif
-		}
-#ifdef WITH_CURSOR_DEBUG
-printf("color 1,2,3 = 0x%02x, 0x%02x, 0x%02x\n",
-    d->bt459_reg[BT459_REG_CCOLOR_1],
-    d->bt459_reg[BT459_REG_CCOLOR_2],
-    d->bt459_reg[BT459_REG_CCOLOR_3]);
-printf("\n");
-#endif
-		/*
-		 *  Make sure the cursor is redrawn, if it is on:
-		 *
-		 *  How does this work? Well, 0 is off, and non-zero is on,
-		 *  but if the old and new differ, the cursor is redrawn.
-		 *  (Hopefully this will "never" overflow.)
-		 */
-		if (d->cursor_on)
-			d->cursor_on ++;
-	}
-#endif
-}
-
-
-/*
- *  bt459_update_cursor_position():
- */
-static void bt459_update_cursor_position(struct bt459_data *d,
-	int old_cursor_on)
-{
-	int new_cursor_x = (d->bt459_reg[BT459_REG_CXLO] & 255) +
-	    ((d->bt459_reg[BT459_REG_CXHI] & 255) << 8) - d->cursor_x_add;
-	int new_cursor_y = (d->bt459_reg[BT459_REG_CYLO] & 255) +
-	    ((d->bt459_reg[BT459_REG_CYHI] & 255) << 8) - d->cursor_y_add;
-
-	if (new_cursor_x != d->cursor_x || new_cursor_y != d->cursor_y ||
-	    d->cursor_on != old_cursor_on) {
-		int on;
-
-		d->cursor_x = new_cursor_x;
-		d->cursor_y = new_cursor_y;
-
-		if (!quiet_mode)
-			debug("[ bt459: cursor = %03i,%03i ]\n",
-			    d->cursor_x, d->cursor_y);
-
-		on = d->cursor_on;
-		if (d->cursor_xsize == 0 || d->cursor_ysize == 0)
-			on = 0;
-
-		dev_fb_setcursor(d->vfb_data, d->cursor_x, d->cursor_y,
-		    on, d->cursor_xsize, d->cursor_ysize);
-	}
-}
-
-
-DEVICE_TICK(bt459)
-{
-	struct bt459_data *d = (struct bt459_data *) extra;
-	int old_cursor_on = d->cursor_on;
-
-	if (d->need_to_update_cursor_shape) {
-		d->need_to_update_cursor_shape = 0;
-		bt459_update_X_cursor(cpu, d);
-		bt459_update_cursor_position(d, old_cursor_on);
-	}
-
-	if (d->need_to_redraw_whole_screen) {
-		d->vfb_data->update_x1 = 0;
-		d->vfb_data->update_x2 = d->vfb_data->xsize - 1;
-		d->vfb_data->update_y1 = 0;
-		d->vfb_data->update_y2 = d->vfb_data->ysize - 1;
-		d->need_to_redraw_whole_screen = 0;
-	}
-
-	/*
-	 *  Vertical retrace interrupts. (This hack is kind of ugly.)
-	 *  Once every 'interrupt_time_reset_value', the interrupt is
-	 *  asserted. It is acked either manually (by someone reading
-	 *  a normal BT459 register or the Interrupt ack register),
-	 *  or after another tick has passed.  (This is to prevent
-	 *  lockups from unhandled interrupts.)
-	 */
-	if (d->type != BT459_PX && d->interrupts_enable) {
-		d->interrupt_time --;
-		if (d->interrupt_time < 0) {
-			d->interrupt_time = d->interrupt_time_reset_value;
-			INTERRUPT_ASSERT(d->irq);
-		} else
-			INTERRUPT_DEASSERT(d->irq);
-	}
-}
-
-
-DEVICE_ACCESS(bt459_irq)
-{
-	struct bt459_data *d = (struct bt459_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-#ifdef BT459_DEBUG
-	fatal("[ bt459: IRQ ack ]\n");
-#endif
-
-	d->interrupts_enable = 1;
-
-	INTERRUPT_DEASSERT(d->irq);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(bt459)
-{
-	struct bt459_data *d = (struct bt459_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int btaddr, old_cursor_on = d->cursor_on, modified;
-
-	idata = memory_readmax64(cpu, data, len);
-
-#ifdef BT459_DEBUG
-	if (writeflag == MEM_WRITE)
-		fatal("[ bt459: write to addr 0x%02x: %08x ]\n",
-		    (int)relative_addr, (int)idata);
-#endif
-
-	/*
-	 *  Vertical retrace interrupts are acked either by
-	 *  accessing a normal BT459 register, or the irq register,
-	 *  or by simply "missing" it.
-	 */
-	INTERRUPT_DEASSERT(d->irq);
-
-	/*  ID register is read-only, should always be 0x4a or 0x4a4a4a:  */
-	if (d->planes == 24)
-		d->bt459_reg[BT459_REG_ID] = 0x4a4a4a;
-	else {
-		/*
-		 *  TODO:  Is it really 0x4a, or 0x4a0000?
-		 *  Ultrix panics with a "bad VDAC ID" message if 0x4a
-		 *  is returned.
-		 */
-		d->bt459_reg[BT459_REG_ID] = 0x4a0000;
-	}
-
-	btaddr = ((d->cur_addr_hi << 8) + d->cur_addr_lo) % DEV_BT459_NREGS;
-
-	/*  Read from/write to the bt459:  */
-	switch (relative_addr) {
-	case 0x00:		/*  Low byte of address:  */
-		if (writeflag == MEM_WRITE) {
-			if (!quiet_mode)
-				debug("[ bt459: write to Low Address Byte, "
-				    "0x%02x ]\n", (int)idata);
-			d->cur_addr_lo = idata;
-			d->palette_sub_offset = 0;
-		} else {
-			odata = d->cur_addr_lo;
-			if (!quiet_mode)
-				debug("[ bt459: read from Low Address Byte: "
-				    "0x%0x ]\n", (int)odata);
-		}
-		break;
-	case 0x04:		/*  High byte of address:  */
-		if (writeflag == MEM_WRITE) {
-			if (!quiet_mode)
-				debug("[ bt459: write to High Address Byte, "
-				    "0x%02x ]\n", (int)idata);
-			d->cur_addr_hi = idata;
-			d->palette_sub_offset = 0;
-		} else {
-			odata = d->cur_addr_hi;
-			if (!quiet_mode)
-				debug("[ bt459: read from High Address Byte: "
-				    "0x%0x ]\n", (int)odata);
-		}
-		break;
-	case 0x08:		/*  Register access:  */
-		if (writeflag == MEM_WRITE) {
-			if (!quiet_mode)
-				debug("[ bt459: write to BT459 register "
-				    "0x%04x, value 0x%02x ]\n", btaddr,
-				    (int)idata);
-			modified = (d->bt459_reg[btaddr] != idata);
-			d->bt459_reg[btaddr] = idata;
-
-			switch (btaddr) {
-			case BT459_REG_CCOLOR_1:
-			case BT459_REG_CCOLOR_2:
-			case BT459_REG_CCOLOR_3:
-				if (modified)
-					d->need_to_update_cursor_shape = 1;
-				break;
-			case BT459_REG_PRM:
-				/*
-				 *  NetBSD writes 0x00 to this register to
-				 *  blank the screen (video off), and 0xff
-				 *  to turn the screen on.
-				 */
-				switch (idata & 0xff) {
-				case 0:	d->video_on = 0;
-					memset(d->rgb_palette, 0, 256*3);
-					d->need_to_redraw_whole_screen = 1;
-					debug("[ bt459: video OFF ]\n");
-					break;
-				default:d->video_on = 1;
-					memcpy(d->rgb_palette,
-					    d->local_rgb_palette, 256*3);
-					d->need_to_redraw_whole_screen = 1;
-					debug("[ bt459: video ON ]\n");
-				}
-				break;
-			case BT459_REG_CCR:
-				/*  Cursor control register:  */
-				switch (idata & 0xff) {
-				case 0x00:	d->cursor_on = 0; break;
-				case 0xc0:
-				case 0xc1:	d->cursor_on = 1; break;
-				default:
-					fatal("[ bt459: unimplemented CCR "
-					    "value 0x%08x ]\n", (int)idata);
-				}
-				if (modified)
-					d->need_to_update_cursor_shape = 1;
-				break;
-			default:
-				if (btaddr < 0x100)
-					fatal("[ bt459: write to BT459 "
-					    "register 0x%04x, value 0x%02x ]\n",
-					    btaddr, (int)idata);
-			}
-
-			/*  Write to cursor bitmap:  */
-			if (btaddr >= BT459_REG_CRAM_BASE && modified)
-				d->need_to_update_cursor_shape = 1;
-		} else {
-			odata = d->bt459_reg[btaddr];
-
-			/*  Perhaps this hack is not necessary:  */
-			if (btaddr == BT459_REG_ID && len==1)
-				odata = (odata >> 16) & 255;
-
-			if (!quiet_mode)
-				debug("[ bt459: read from BT459 register "
-				    "0x%04x, value 0x%02x ]\n", btaddr,
-				    (int)odata);
-		}
-
-		/*  Go to next register:  */
-		d->cur_addr_lo ++;
-		if (d->cur_addr_lo == 0)
-			d->cur_addr_hi ++;
-		break;
-	case 0xc:		/*  Color map:  */
-		if (writeflag == MEM_WRITE) {
-			idata &= 255;
-			if (!quiet_mode)
-				debug("[ bt459: write to BT459 colormap "
-				    "0x%04x subaddr %i, value 0x%02x ]\n",
-				    btaddr, d->palette_sub_offset, (int)idata);
-
-			if (btaddr < 0x100) {
-				if (d->video_on &&
-				    d->local_rgb_palette[(btaddr & 0xff) * 3
-				    + d->palette_sub_offset] != idata)
-					d->need_to_redraw_whole_screen = 1;
-
-				/*
-				 *  Actually, the palette should only be
-				 *  updated after the third write,
-				 *  but this should probably work fine too:
-				 */
-				d->local_rgb_palette[(btaddr & 0xff) * 3
-				    + d->palette_sub_offset] = idata;
-
-				if (d->video_on)
-					d->rgb_palette[(btaddr & 0xff) * 3
-					    + d->palette_sub_offset] = idata;
-			}
-		} else {
-			if (btaddr < 0x100)
-				odata = d->local_rgb_palette[(btaddr & 0xff)
-				    * 3 + d->palette_sub_offset];
-			if (!quiet_mode)
-				debug("[ bt459: read from BT459 colormap "
-				    "0x%04x subaddr %i, value 0x%02x ]\n",
-				    btaddr, d->palette_sub_offset, (int)odata);
-		}
-
-		d->palette_sub_offset ++;
-		if (d->palette_sub_offset >= 3) {
-			d->palette_sub_offset = 0;
-
-			d->cur_addr_lo ++;
-			if (d->cur_addr_lo == 0)
-				d->cur_addr_hi ++;
-		}
-
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ bt459: unimplemented write to address 0x%x, "
-			    "data=0x%02x ]\n", (int)relative_addr, (int)idata);
-		} else {
-			debug("[ bt459: unimplemented read from address "
-			    "0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-
-	bt459_update_cursor_position(d, old_cursor_on);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-#ifdef BT459_DEBUG
-	if (writeflag == MEM_READ)
-		fatal("[ bt459: read from addr 0x%02x: %08x ]\n",
-		    (int)relative_addr, (int)idata);
-#endif
-
-	return 1;
-}
-
-
-/*
- *  dev_bt459_init():
- */
-void dev_bt459_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, uint64_t baseaddr_irq, struct vfb_data *vfb_data,
-	int planes, const char *irq_path, int type)
-{
-	struct bt459_data *d;
-
-	CHECK_ALLOCATION(d = (struct bt459_data *) malloc(sizeof(struct bt459_data)));
-	memset(d, 0, sizeof(struct bt459_data));
-
-	INTERRUPT_CONNECT(irq_path, d->irq);
-
-	d->vfb_data     = vfb_data;
-	d->rgb_palette  = vfb_data->rgb_palette;
-	d->planes       = planes;
-	d->type		= type;
-	d->cursor_x     = -1;
-	d->cursor_y     = -1;
-	d->cursor_xsize = d->cursor_ysize = 0;	/*  anything  */
-	d->video_on     = 1;
-
-	/*
-	 *  These offsets are based on those mentioned in NetBSD,
-	 *  and then adjusted to look good with both NetBSD and
-	 *  Ultrix:
-	 */
-	switch (d->type) {
-	case BT459_PX:
-		d->cursor_x_add = 370;
-		d->cursor_y_add =  37;
-		break;
-	case BT459_BA:
-		d->cursor_x_add = 220;
-		d->cursor_y_add =  35;
-		break;
-	case BT459_BBA:
-		if (vfb_data->xsize == 1280) {
-			/*  1280x1024:  */
-			d->cursor_x_add = 368;
-			d->cursor_y_add =  38;
-		} else {
-			/*  1024x864:  */
-			d->cursor_x_add = 220;
-			d->cursor_y_add =  35;
-		}
-		break;
-	}
-
-	d->interrupt_time_reset_value = 500;
-
-	memory_device_register(mem, "bt459", baseaddr, DEV_BT459_LENGTH,
-	    dev_bt459_access, (void *)d, DM_DEFAULT, NULL);
-
-	if (baseaddr_irq != 0)
-		memory_device_register(mem, "bt459_irq", baseaddr_irq, 0x10000,
-		    dev_bt459_irq_access, (void *)d, DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(machine, dev_bt459_tick, d,
-	    BT459_TICK_SHIFT);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_clmpcc.c gxemul-0.7.0+dfsg/src/devices/dev_clmpcc.c
--- gxemul-0.6.2/src/devices/dev_clmpcc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_clmpcc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,311 @@
+/*
+ *  Copyright (C) 2007-2014  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Cirrus Logic 4-Channel Communications Controller (CD2400/CD2401)
+ *
+ *  Used by OpenBSD/mvme88k.
+ *
+ *  Works so far:
+ *	TX/RX interrupts (happy case).
+ *
+ *  TODO:
+ *	Multiple channels
+ *	DMA?
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/mvme_pcctworeg.h"
+#include "thirdparty/clmpccreg.h"
+
+
+#define debug fatal
+
+#define	CLMPCC_LEN		0x200
+#define	DEV_CLMPCC_TICK_SHIFT	16
+
+struct clmpcc_data {
+	unsigned char	reg[CLMPCC_LEN];
+
+	int		console_handle;
+
+	/*  Interrupt pins on the PCC2 controller:  */
+	struct interrupt irq_scc_rxe;
+	struct interrupt irq_scc_m;
+	struct interrupt irq_scc_tx;
+	struct interrupt irq_scc_rx;
+};
+
+
+static void reassert_interrupts(struct clmpcc_data *d)
+{
+	int rxintr = 0;
+
+	if (console_charavail(d->console_handle))
+		rxintr = 1;
+
+	if (rxintr)
+		INTERRUPT_ASSERT(d->irq_scc_rx);
+	else
+		INTERRUPT_DEASSERT(d->irq_scc_rx);
+
+	/*  TODO: Hack/experiment for now...  */
+	if ((d->reg[CLMPCC_REG_IER] & 3) != 0)
+		INTERRUPT_ASSERT(d->irq_scc_tx);
+	else
+		INTERRUPT_DEASSERT(d->irq_scc_tx);
+}
+
+
+DEVICE_TICK(clmpcc)
+{
+	struct clmpcc_data *d = (struct clmpcc_data *) extra;
+	reassert_interrupts(d);
+}
+
+
+DEVICE_ACCESS(clmpcc)
+{
+	struct clmpcc_data *d = (struct clmpcc_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE) {
+		idata = memory_readmax64(cpu, data, len);
+		d->reg[relative_addr] = idata;
+	}
+
+	if (writeflag == MEM_READ)
+		odata = d->reg[relative_addr];
+
+	switch (relative_addr) {
+
+	case 0:	/*  Used by OpenBSD/mvme88k when probing...  */
+		break;
+
+	case CLMPCC_REG_TPR:	/*  Timer Period Register  */
+		break;
+
+	case CLMPCC_REG_CAR:	/*  Channel Access Register  */
+		/*  debug("[ clmpcc: selecting channel %i ]\n",
+		    (int) idata);  */
+		break;
+
+	case CLMPCC_REG_CCR:	/*  Channel Command Register:  */
+		odata = 0;
+		break;
+
+	case CLMPCC_REG_CMR:	/*  Channel Mode Register  */
+	case CLMPCC_REG_COR1:	/*  Channel Option Register #1  */
+	case CLMPCC_REG_COR2:	/*  Channel Option Register #2  */
+	case CLMPCC_REG_COR3:	/*  Channel Option Register #3  */
+	case CLMPCC_REG_COR4:	/*  Channel Option Register #4  */
+	case CLMPCC_REG_COR5:	/*  Channel Option Register #5  */
+	case CLMPCC_REG_COR6:	/*  Channel Option Register #6  */
+	case CLMPCC_REG_COR7:	/*  Channel Option Register #7  */
+	case CLMPCC_REG_SCHR1:	/*  Special Character Register #1  */
+	case CLMPCC_REG_SCHR2:	/*  Special Character Register #2  */
+	case CLMPCC_REG_SCHR3:	/*  Special Character Register #3  */
+	case CLMPCC_REG_SCHR4:	/*  Special Character Register #4  */
+	case CLMPCC_REG_SCRl:	/*  Special Character Range (low)  */
+	case CLMPCC_REG_SCRh:	/*  Special Character Range (high)  */
+	case CLMPCC_REG_LNXT:	/*  LNext Character  */
+		break;
+
+	case CLMPCC_REG_STCR:	/*  Special Transmit Command Register  */
+		if (writeflag == MEM_WRITE) {
+			if (idata == 0x0b) {
+				if (d->reg[CLMPCC_REG_CAR] == 0)
+					console_putchar(d->console_handle,
+					    d->reg[CLMPCC_REG_SCHR3]);
+				else
+					fatal("[ clmpcc: TODO: transmit "
+					    "to channel, CAR!=0 ]\n");
+
+				/*  Command done:  */
+				d->reg[CLMPCC_REG_STCR] = 0x00;
+			} else {
+				fatal("clmpcc: unimplemented STCR byte "
+				    "0x%02x\n", (int) idata);
+				exit(1);
+			}
+		}
+		break;
+
+	case CLMPCC_REG_RBPR:	/*  Receive Baud Rate Period Register  */
+	case CLMPCC_REG_TBPR:	/*  Transmit Baud Rate Period Register  */
+	case CLMPCC_REG_RCOR:	/*  Receive Clock Options Register  */
+	case CLMPCC_REG_TCOR:	/*  Transmit Clock Options Register  */
+		break;
+
+	case CLMPCC_REG_MSVR_RTS:/* Modem Signal Value Register, RTS  */
+	case CLMPCC_REG_MSVR_DTR:/* Modem Signal Value Register, DTR  */
+		break;
+
+	case CLMPCC_REG_RTPRl:	/*  Receive Timeout Period Register (low)  */
+	case CLMPCC_REG_RTPRh:	/*  Receive Timeout Period Register (high)  */
+		break;
+
+	case CLMPCC_REG_IER:	/*  Interrupt Enable Register  */
+	case CLMPCC_REG_LIVR:	/*  Local Interrupt Vector Register  */
+	case CLMPCC_REG_RPILR:	/*  Rx Priority Interrupt Level Register  */
+	case CLMPCC_REG_TPILR:	/*  Tx Priority Interrupt Level Register  */
+	case CLMPCC_REG_MPILR:	/*  Modem Priority Interrupt Level Register  */
+		reassert_interrupts(d);
+		break;
+
+	case CLMPCC_REG_RISRl:	/*  Receive Interrupt Status Reg (low)  */
+		odata = 0x00;
+		break;
+
+	case CLMPCC_REG_TIR:	/*  Transmit Interrupt Register  */
+		odata = 0x40;	/*  see openbsd's cl_txintr  */
+		break;
+
+	case CLMPCC_REG_RIR:	/*  Rx Interrupt Register  */
+		odata = 0x00;
+		if (console_charavail(d->console_handle))
+			odata = 0xc0;
+		break;
+
+	case CLMPCC_REG_LICR:	/*  Local Interrupt Status Register  */
+		odata = 0;	/*  channel nr << 2  */
+		break;
+
+	case CLMPCC_REG_RFOC:	/*  Rx FIFO Output Count  */
+		odata = 0;
+		if (console_charavail(d->console_handle))
+			odata = 1;
+		break;
+
+	case CLMPCC_REG_TFTC:	/*  Tx FIFO Transfer Count  */
+		/*
+		 *  0x1f is low enough to allow OpenBSD/mvme88k's ramdisk
+		 *  kernel to run (bsd.rd), but not the default kernel (bsd).
+		 *  Lowering it to 0x0f seems to work.
+		 */
+		odata = 0x0f;
+		break;
+
+	case CLMPCC_REG_TEOIR:	/*  Tx End of Interrupt Register  */
+		/*  TODO: Do something more realistic?  */
+		INTERRUPT_DEASSERT(d->irq_scc_tx);
+		break;
+
+	case CLMPCC_REG_REOIR:	/*  Rx End of Interrupt Register  */
+		/*  TODO: Do something more realistic?  */
+		INTERRUPT_DEASSERT(d->irq_scc_rx);
+		break;
+
+	case CLMPCC_REG_TDR:
+		if (writeflag == MEM_WRITE) {
+			if (d->reg[CLMPCC_REG_CAR] == 0)
+				console_putchar(d->console_handle, idata);
+			else
+				fatal("[ clmpcc: TODO: transmit "
+				    "to channel, CAR!=0 ]\n");
+		} else {
+			odata = console_readchar(d->console_handle);
+		}
+		break;
+
+	default:if (writeflag == MEM_READ)
+			fatal("[ clmpcc: unimplemented READ from offset 0x%x ]"
+			    "\n", (int)relative_addr);
+		else
+			fatal("[ clmpcc: unimplemented WRITE to offset 0x%x: "
+			    "0x%x ]\n", (int)relative_addr, (int)idata);
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(clmpcc)
+{
+	struct clmpcc_data *d;
+	char tmpstr[100];
+
+	CHECK_ALLOCATION(d = (struct clmpcc_data *) malloc(sizeof(struct clmpcc_data)));
+	memset(d, 0, sizeof(struct clmpcc_data));
+
+	d->console_handle =
+	    console_start_slave(devinit->machine, devinit->name2 != NULL?
+	    devinit->name2 : devinit->name, devinit->in_use);
+
+	/*
+	 *  Connect to the PCC2's interrupt pins:
+	 *
+	 *  The supplied interrupt_path is something like
+	 *  "machine[0].cpu[0].pcc2".
+	 *
+	 *  We want to use "machine[0].cpu[0].pcc2.x", where x is
+	 *  0xc, 0xd, 0xe, and 0xf (PCC2V_SCC_xxx).
+	 */
+	snprintf(tmpstr, sizeof(tmpstr), "%s.%i",
+	    devinit->interrupt_path, PCC2V_SCC_RXE);
+	INTERRUPT_CONNECT(tmpstr, d->irq_scc_rxe);
+	snprintf(tmpstr, sizeof(tmpstr), "%s.%i",
+	    devinit->interrupt_path, PCC2V_SCC_M);
+	INTERRUPT_CONNECT(tmpstr, d->irq_scc_m);
+	snprintf(tmpstr, sizeof(tmpstr), "%s.%i",
+	    devinit->interrupt_path, PCC2V_SCC_TX);
+	INTERRUPT_CONNECT(tmpstr, d->irq_scc_tx);
+	snprintf(tmpstr, sizeof(tmpstr), "%s.%i",
+	    devinit->interrupt_path, PCC2V_SCC_RX);
+	INTERRUPT_CONNECT(tmpstr, d->irq_scc_rx);
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, CLMPCC_LEN, dev_clmpcc_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(devinit->machine,
+	    dev_clmpcc_tick, d, DEV_CLMPCC_TICK_SHIFT);
+
+	/*
+	 *  NOTE:  Ugly cast into a pointer, because this is a convenient way
+	 *         to return the console handle to code in src/machines/.
+	 */
+	devinit->return_ptr = (void *)(size_t)d->console_handle;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_clmpcc.cc gxemul-0.7.0+dfsg/src/devices/dev_clmpcc.cc
--- gxemul-0.6.2/src/devices/dev_clmpcc.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_clmpcc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,311 +0,0 @@
-/*
- *  Copyright (C) 2007-2014  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Cirrus Logic 4-Channel Communications Controller (CD2400/CD2401)
- *
- *  Used by OpenBSD/mvme88k.
- *
- *  Works so far:
- *	TX/RX interrupts (happy case).
- *
- *  TODO:
- *	Multiple channels
- *	DMA?
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/mvme_pcctworeg.h"
-#include "thirdparty/clmpccreg.h"
-
-
-#define debug fatal
-
-#define	CLMPCC_LEN		0x200
-#define	DEV_CLMPCC_TICK_SHIFT	16
-
-struct clmpcc_data {
-	unsigned char	reg[CLMPCC_LEN];
-
-	int		console_handle;
-
-	/*  Interrupt pins on the PCC2 controller:  */
-	struct interrupt irq_scc_rxe;
-	struct interrupt irq_scc_m;
-	struct interrupt irq_scc_tx;
-	struct interrupt irq_scc_rx;
-};
-
-
-static void reassert_interrupts(struct clmpcc_data *d)
-{
-	int rxintr = 0;
-
-	if (console_charavail(d->console_handle))
-		rxintr = 1;
-
-	if (rxintr)
-		INTERRUPT_ASSERT(d->irq_scc_rx);
-	else
-		INTERRUPT_DEASSERT(d->irq_scc_rx);
-
-	/*  TODO: Hack/experiment for now...  */
-	if ((d->reg[CLMPCC_REG_IER] & 3) != 0)
-		INTERRUPT_ASSERT(d->irq_scc_tx);
-	else
-		INTERRUPT_DEASSERT(d->irq_scc_tx);
-}
-
-
-DEVICE_TICK(clmpcc)
-{
-	struct clmpcc_data *d = (struct clmpcc_data *) extra;
-	reassert_interrupts(d);
-}
-
-
-DEVICE_ACCESS(clmpcc)
-{
-	struct clmpcc_data *d = (struct clmpcc_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE) {
-		idata = memory_readmax64(cpu, data, len);
-		d->reg[relative_addr] = idata;
-	}
-
-	if (writeflag == MEM_READ)
-		odata = d->reg[relative_addr];
-
-	switch (relative_addr) {
-
-	case 0:	/*  Used by OpenBSD/mvme88k when probing...  */
-		break;
-
-	case CLMPCC_REG_TPR:	/*  Timer Period Register  */
-		break;
-
-	case CLMPCC_REG_CAR:	/*  Channel Access Register  */
-		/*  debug("[ clmpcc: selecting channel %i ]\n",
-		    (int) idata);  */
-		break;
-
-	case CLMPCC_REG_CCR:	/*  Channel Command Register:  */
-		odata = 0;
-		break;
-
-	case CLMPCC_REG_CMR:	/*  Channel Mode Register  */
-	case CLMPCC_REG_COR1:	/*  Channel Option Register #1  */
-	case CLMPCC_REG_COR2:	/*  Channel Option Register #2  */
-	case CLMPCC_REG_COR3:	/*  Channel Option Register #3  */
-	case CLMPCC_REG_COR4:	/*  Channel Option Register #4  */
-	case CLMPCC_REG_COR5:	/*  Channel Option Register #5  */
-	case CLMPCC_REG_COR6:	/*  Channel Option Register #6  */
-	case CLMPCC_REG_COR7:	/*  Channel Option Register #7  */
-	case CLMPCC_REG_SCHR1:	/*  Special Character Register #1  */
-	case CLMPCC_REG_SCHR2:	/*  Special Character Register #2  */
-	case CLMPCC_REG_SCHR3:	/*  Special Character Register #3  */
-	case CLMPCC_REG_SCHR4:	/*  Special Character Register #4  */
-	case CLMPCC_REG_SCRl:	/*  Special Character Range (low)  */
-	case CLMPCC_REG_SCRh:	/*  Special Character Range (high)  */
-	case CLMPCC_REG_LNXT:	/*  LNext Character  */
-		break;
-
-	case CLMPCC_REG_STCR:	/*  Special Transmit Command Register  */
-		if (writeflag == MEM_WRITE) {
-			if (idata == 0x0b) {
-				if (d->reg[CLMPCC_REG_CAR] == 0)
-					console_putchar(d->console_handle,
-					    d->reg[CLMPCC_REG_SCHR3]);
-				else
-					fatal("[ clmpcc: TODO: transmit "
-					    "to channel, CAR!=0 ]\n");
-
-				/*  Command done:  */
-				d->reg[CLMPCC_REG_STCR] = 0x00;
-			} else {
-				fatal("clmpcc: unimplemented STCR byte "
-				    "0x%02x\n", (int) idata);
-				exit(1);
-			}
-		}
-		break;
-
-	case CLMPCC_REG_RBPR:	/*  Receive Baud Rate Period Register  */
-	case CLMPCC_REG_TBPR:	/*  Transmit Baud Rate Period Register  */
-	case CLMPCC_REG_RCOR:	/*  Receive Clock Options Register  */
-	case CLMPCC_REG_TCOR:	/*  Transmit Clock Options Register  */
-		break;
-
-	case CLMPCC_REG_MSVR_RTS:/* Modem Signal Value Register, RTS  */
-	case CLMPCC_REG_MSVR_DTR:/* Modem Signal Value Register, DTR  */
-		break;
-
-	case CLMPCC_REG_RTPRl:	/*  Receive Timeout Period Register (low)  */
-	case CLMPCC_REG_RTPRh:	/*  Receive Timeout Period Register (high)  */
-		break;
-
-	case CLMPCC_REG_IER:	/*  Interrupt Enable Register  */
-	case CLMPCC_REG_LIVR:	/*  Local Interrupt Vector Register  */
-	case CLMPCC_REG_RPILR:	/*  Rx Priority Interrupt Level Register  */
-	case CLMPCC_REG_TPILR:	/*  Tx Priority Interrupt Level Register  */
-	case CLMPCC_REG_MPILR:	/*  Modem Priority Interrupt Level Register  */
-		reassert_interrupts(d);
-		break;
-
-	case CLMPCC_REG_RISRl:	/*  Receive Interrupt Status Reg (low)  */
-		odata = 0x00;
-		break;
-
-	case CLMPCC_REG_TIR:	/*  Transmit Interrupt Register  */
-		odata = 0x40;	/*  see openbsd's cl_txintr  */
-		break;
-
-	case CLMPCC_REG_RIR:	/*  Rx Interrupt Register  */
-		odata = 0x00;
-		if (console_charavail(d->console_handle))
-			odata = 0xc0;
-		break;
-
-	case CLMPCC_REG_LICR:	/*  Local Interrupt Status Register  */
-		odata = 0;	/*  channel nr << 2  */
-		break;
-
-	case CLMPCC_REG_RFOC:	/*  Rx FIFO Output Count  */
-		odata = 0;
-		if (console_charavail(d->console_handle))
-			odata = 1;
-		break;
-
-	case CLMPCC_REG_TFTC:	/*  Tx FIFO Transfer Count  */
-		/*
-		 *  0x1f is low enough to allow OpenBSD/mvme88k's ramdisk
-		 *  kernel to run (bsd.rd), but not the default kernel (bsd).
-		 *  Lowering it to 0x0f seems to work.
-		 */
-		odata = 0x0f;
-		break;
-
-	case CLMPCC_REG_TEOIR:	/*  Tx End of Interrupt Register  */
-		/*  TODO: Do something more realistic?  */
-		INTERRUPT_DEASSERT(d->irq_scc_tx);
-		break;
-
-	case CLMPCC_REG_REOIR:	/*  Rx End of Interrupt Register  */
-		/*  TODO: Do something more realistic?  */
-		INTERRUPT_DEASSERT(d->irq_scc_rx);
-		break;
-
-	case CLMPCC_REG_TDR:
-		if (writeflag == MEM_WRITE) {
-			if (d->reg[CLMPCC_REG_CAR] == 0)
-				console_putchar(d->console_handle, idata);
-			else
-				fatal("[ clmpcc: TODO: transmit "
-				    "to channel, CAR!=0 ]\n");
-		} else {
-			odata = console_readchar(d->console_handle);
-		}
-		break;
-
-	default:if (writeflag == MEM_READ)
-			fatal("[ clmpcc: unimplemented READ from offset 0x%x ]"
-			    "\n", (int)relative_addr);
-		else
-			fatal("[ clmpcc: unimplemented WRITE to offset 0x%x: "
-			    "0x%x ]\n", (int)relative_addr, (int)idata);
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(clmpcc)
-{
-	struct clmpcc_data *d;
-	char tmpstr[100];
-
-	CHECK_ALLOCATION(d = (struct clmpcc_data *) malloc(sizeof(struct clmpcc_data)));
-	memset(d, 0, sizeof(struct clmpcc_data));
-
-	d->console_handle =
-	    console_start_slave(devinit->machine, devinit->name2 != NULL?
-	    devinit->name2 : devinit->name, devinit->in_use);
-
-	/*
-	 *  Connect to the PCC2's interrupt pins:
-	 *
-	 *  The supplied interrupt_path is something like
-	 *  "machine[0].cpu[0].pcc2".
-	 *
-	 *  We want to use "machine[0].cpu[0].pcc2.x", where x is
-	 *  0xc, 0xd, 0xe, and 0xf (PCC2V_SCC_xxx).
-	 */
-	snprintf(tmpstr, sizeof(tmpstr), "%s.%i",
-	    devinit->interrupt_path, PCC2V_SCC_RXE);
-	INTERRUPT_CONNECT(tmpstr, d->irq_scc_rxe);
-	snprintf(tmpstr, sizeof(tmpstr), "%s.%i",
-	    devinit->interrupt_path, PCC2V_SCC_M);
-	INTERRUPT_CONNECT(tmpstr, d->irq_scc_m);
-	snprintf(tmpstr, sizeof(tmpstr), "%s.%i",
-	    devinit->interrupt_path, PCC2V_SCC_TX);
-	INTERRUPT_CONNECT(tmpstr, d->irq_scc_tx);
-	snprintf(tmpstr, sizeof(tmpstr), "%s.%i",
-	    devinit->interrupt_path, PCC2V_SCC_RX);
-	INTERRUPT_CONNECT(tmpstr, d->irq_scc_rx);
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, CLMPCC_LEN, dev_clmpcc_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(devinit->machine,
-	    dev_clmpcc_tick, d, DEV_CLMPCC_TICK_SHIFT);
-
-	/*
-	 *  NOTE:  Ugly cast into a pointer, because this is a convenient way
-	 *         to return the console handle to code in src/machines/.
-	 */
-	devinit->return_ptr = (void *)(size_t)d->console_handle;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_colorplanemask.c gxemul-0.7.0+dfsg/src/devices/dev_colorplanemask.c
--- gxemul-0.6.2/src/devices/dev_colorplanemask.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_colorplanemask.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,98 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Color plane mask, used in the DECstation 3100 machine
+ *
+ *  Just a one-byte thingy, but the way things work now this has to
+ *  be a separate device. :-/
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "devices.h"
+#include "memory.h"
+#include "misc.h"
+
+
+struct colorplanemask_data {
+	unsigned char	*color_plane_mask;
+};
+
+
+DEVICE_ACCESS(colorplanemask)
+{
+	struct colorplanemask_data *d = (struct colorplanemask_data *) extra;
+
+	switch (relative_addr) {
+
+	case 0x00:
+		if (writeflag == MEM_WRITE) {
+			*d->color_plane_mask = data[0];
+		} else {
+			debug("[ colorplanemask: read isn't actually "
+			    "supported ]\n");
+			data[0] = *d->color_plane_mask;
+		}
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ colorplanemask: unimplemented write "
+			    "to address 0x%x, data=0x%02x ]\n",
+			    (int)relative_addr, data[0]);
+		} else {
+			debug("[ colorplanemask: unimplemented read "
+			    "from address 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	/*  Pretend it was ok:  */
+	return 1;
+}
+
+
+/*
+ *  dev_colorplanemask_init():
+ */
+void dev_colorplanemask_init(struct memory *mem, uint64_t baseaddr,
+	unsigned char *color_plane_mask)
+{
+	struct colorplanemask_data *d;
+
+	CHECK_ALLOCATION(d = (struct colorplanemask_data *)
+	    malloc(sizeof(struct colorplanemask_data)));
+	memset(d, 0, sizeof(struct colorplanemask_data));
+
+	d->color_plane_mask = color_plane_mask;
+
+	memory_device_register(mem, "colorplanemask", baseaddr,
+	    DEV_COLORPLANEMASK_LENGTH, dev_colorplanemask_access,
+	    (void *)d, DM_DEFAULT, NULL);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_colorplanemask.cc gxemul-0.7.0+dfsg/src/devices/dev_colorplanemask.cc
--- gxemul-0.6.2/src/devices/dev_colorplanemask.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_colorplanemask.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,98 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Color plane mask, used in the DECstation 3100 machine
- *
- *  Just a one-byte thingy, but the way things work now this has to
- *  be a separate device. :-/
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "devices.h"
-#include "memory.h"
-#include "misc.h"
-
-
-struct colorplanemask_data {
-	unsigned char	*color_plane_mask;
-};
-
-
-DEVICE_ACCESS(colorplanemask)
-{
-	struct colorplanemask_data *d = (struct colorplanemask_data *) extra;
-
-	switch (relative_addr) {
-
-	case 0x00:
-		if (writeflag == MEM_WRITE) {
-			*d->color_plane_mask = data[0];
-		} else {
-			debug("[ colorplanemask: read isn't actually "
-			    "supported ]\n");
-			data[0] = *d->color_plane_mask;
-		}
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ colorplanemask: unimplemented write "
-			    "to address 0x%x, data=0x%02x ]\n",
-			    (int)relative_addr, data[0]);
-		} else {
-			debug("[ colorplanemask: unimplemented read "
-			    "from address 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	/*  Pretend it was ok:  */
-	return 1;
-}
-
-
-/*
- *  dev_colorplanemask_init():
- */
-void dev_colorplanemask_init(struct memory *mem, uint64_t baseaddr,
-	unsigned char *color_plane_mask)
-{
-	struct colorplanemask_data *d;
-
-	CHECK_ALLOCATION(d = (struct colorplanemask_data *)
-	    malloc(sizeof(struct colorplanemask_data)));
-	memset(d, 0, sizeof(struct colorplanemask_data));
-
-	d->color_plane_mask = color_plane_mask;
-
-	memory_device_register(mem, "colorplanemask", baseaddr,
-	    DEV_COLORPLANEMASK_LENGTH, dev_colorplanemask_access,
-	    (void *)d, DM_DEFAULT, NULL);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_cons.c gxemul-0.7.0+dfsg/src/devices/dev_cons.c
--- gxemul-0.6.2/src/devices/dev_cons.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_cons.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,146 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: A simple console device, for the test machines
+ *
+ *  This device provides memory mapped I/O for a simple console supporting
+ *  putchar (writing to memory) and getchar (reading from memory), and
+ *  support for halting the emulator.  (This is useful for regression tests,
+ *  Hello World-style test programs, and other simple experiments.)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "testmachine/dev_cons.h"
+
+#define	CONS_TICK_SHIFT		14
+
+struct cons_data {
+	int			console_handle;
+	int			in_use;
+	struct interrupt	irq;
+};
+
+
+DEVICE_TICK(cons)
+{
+	struct cons_data *d = (struct cons_data *) extra;
+
+	if (console_charavail(d->console_handle))
+		INTERRUPT_ASSERT(d->irq);
+	else
+		INTERRUPT_DEASSERT(d->irq);
+}
+
+
+DEVICE_ACCESS(cons)
+{
+	struct cons_data *d = (struct cons_data *) extra;
+	unsigned int i;
+
+	/*  Exit the emulator:  */
+	if (relative_addr == DEV_CONS_HALT) {
+		/*  cpu->running = 0;
+		    return 1;  */
+		/*  TODO: this doesn't work yet. for now, let's
+		    simply use exit()  */
+		exit(0);
+	}
+
+	if (writeflag == MEM_WRITE) {
+		for (i=0; i<len; i++) {
+			if (data[i] != 0) {
+				if (cpu->machine->register_dump ||
+				    cpu->machine->instruction_trace)
+					debug("putchar '");
+
+				console_putchar(d->console_handle, data[i]);
+
+				if (cpu->machine->register_dump ||
+				    cpu->machine->instruction_trace)
+					debug("'\n");
+				fflush(stdout);
+			}
+		}
+        } else {
+		int ch = console_readchar(d->console_handle);
+		if (ch < 0)
+			ch = 0;
+		for (i=0; i<len; i++)
+			data[i] = ch;
+	}
+
+	dev_cons_tick(cpu, extra);
+
+	return 1;
+}
+
+
+DEVINIT(cons)
+{
+	struct cons_data *d;
+	char *name3;
+	size_t nlen;
+
+	CHECK_ALLOCATION(d = (struct cons_data *) malloc(sizeof(struct cons_data)));
+	memset(d, 0, sizeof(struct cons_data));
+
+	nlen = strlen(devinit->name) + 10;
+	if (devinit->name2 != NULL)
+		nlen += strlen(devinit->name2) + 10;
+	CHECK_ALLOCATION(name3 = (char *) malloc(nlen));
+	if (devinit->name2 != NULL && devinit->name2[0])
+		snprintf(name3, nlen, "%s [%s]", devinit->name, devinit->name2);
+	else
+		snprintf(name3, nlen, "%s", devinit->name);
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	d->in_use = devinit->in_use;
+	d->console_handle = console_start_slave(devinit->machine, name3,
+	    d->in_use);
+
+	memory_device_register(devinit->machine->memory, name3,
+	    devinit->addr, DEV_CONS_LENGTH, dev_cons_access, d,
+	    DM_DEFAULT, NULL);
+	machine_add_tickfunction(devinit->machine, dev_cons_tick,
+	    d, CONS_TICK_SHIFT);
+
+	/*  NOTE: Ugly cast into pointer  */
+	devinit->return_ptr = (void *)(size_t)d->console_handle;
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_cons.cc gxemul-0.7.0+dfsg/src/devices/dev_cons.cc
--- gxemul-0.6.2/src/devices/dev_cons.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_cons.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,147 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: A simple console device, for the test machines
- *
- *  This device provides memory mapped I/O for a simple console supporting
- *  putchar (writing to memory) and getchar (reading from memory), and
- *  support for halting the emulator.  (This is useful for regression tests,
- *  Hello World-style test programs, and other simple experiments.)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "testmachine/dev_cons.h"
-
-#define	CONS_TICK_SHIFT		14
-
-struct cons_data {
-	int			console_handle;
-	int			in_use;
-	struct interrupt	irq;
-};
-
-
-DEVICE_TICK(cons)
-{
-	struct cons_data *d = (struct cons_data *) extra;
-
-	if (console_charavail(d->console_handle))
-		INTERRUPT_ASSERT(d->irq);
-	else
-		INTERRUPT_DEASSERT(d->irq);
-}
-
-
-DEVICE_ACCESS(cons)
-{
-	struct cons_data *d = (struct cons_data *) extra;
-	unsigned int i;
-
-	/*  Exit the emulator:  */
-	if (relative_addr == DEV_CONS_HALT) {
-		/*  cpu->running = 0;
-		    cpu->machine->exit_without_entering_debugger = 1;
-		    return 1;  */
-		/*  TODO: this doesn't work yet. for now, let's
-		    simply use exit()  */
-		exit(0);
-	}
-
-	if (writeflag == MEM_WRITE) {
-		for (i=0; i<len; i++) {
-			if (data[i] != 0) {
-				if (cpu->machine->register_dump ||
-				    cpu->machine->instruction_trace)
-					debug("putchar '");
-
-				console_putchar(d->console_handle, data[i]);
-
-				if (cpu->machine->register_dump ||
-				    cpu->machine->instruction_trace)
-					debug("'\n");
-				fflush(stdout);
-			}
-		}
-        } else {
-		int ch = console_readchar(d->console_handle);
-		if (ch < 0)
-			ch = 0;
-		for (i=0; i<len; i++)
-			data[i] = ch;
-	}
-
-	dev_cons_tick(cpu, extra);
-
-	return 1;
-}
-
-
-DEVINIT(cons)
-{
-	struct cons_data *d;
-	char *name3;
-	size_t nlen;
-
-	CHECK_ALLOCATION(d = (struct cons_data *) malloc(sizeof(struct cons_data)));
-	memset(d, 0, sizeof(struct cons_data));
-
-	nlen = strlen(devinit->name) + 10;
-	if (devinit->name2 != NULL)
-		nlen += strlen(devinit->name2) + 10;
-	CHECK_ALLOCATION(name3 = (char *) malloc(nlen));
-	if (devinit->name2 != NULL && devinit->name2[0])
-		snprintf(name3, nlen, "%s [%s]", devinit->name, devinit->name2);
-	else
-		snprintf(name3, nlen, "%s", devinit->name);
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	d->in_use = devinit->in_use;
-	d->console_handle = console_start_slave(devinit->machine, name3,
-	    d->in_use);
-
-	memory_device_register(devinit->machine->memory, name3,
-	    devinit->addr, DEV_CONS_LENGTH, dev_cons_access, d,
-	    DM_DEFAULT, NULL);
-	machine_add_tickfunction(devinit->machine, dev_cons_tick,
-	    d, CONS_TICK_SHIFT);
-
-	/*  NOTE: Ugly cast into pointer  */
-	devinit->return_ptr = (void *)(size_t)d->console_handle;
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_cpc700.c gxemul-0.7.0+dfsg/src/devices/dev_cpc700.c
--- gxemul-0.6.2/src/devices/dev_cpc700.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_cpc700.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,261 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: IBM CPC700 bridge (PCI and interrupt controller)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/cpc700reg.h"
+
+
+struct cpc700_data {
+	struct interrupt ppc_irq;	/*  Connected to the CPU  */
+
+	uint32_t	sr;		/*  Interrupt Status register  */
+	uint32_t	er;		/*  Interrupt Enable register  */
+
+	struct pci_data *pci_data;	/*  PCI bus  */
+};
+
+
+void cpc700_interrupt_assert(struct interrupt *interrupt)
+{
+	struct cpc700_data *d = (struct cpc700_data *) interrupt->extra;
+	d->sr |= interrupt->line;
+	if (d->sr & d->er)
+		INTERRUPT_ASSERT(d->ppc_irq);
+}
+void cpc700_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct cpc700_data *d = (struct cpc700_data *) interrupt->extra;
+	d->sr &= ~interrupt->line;
+	if (!(d->sr & d->er))
+		INTERRUPT_DEASSERT(d->ppc_irq);
+}
+
+
+/*
+ *  dev_cpc700_pci_access():
+ *
+ *  Passes PCI indirect addr and data accesses onto bus_pci.
+ */
+DEVICE_ACCESS(cpc700_pci)
+{
+	uint64_t idata = 0, odata = 0;
+	int bus, dev, func, reg;
+	struct cpc700_data *d = (struct cpc700_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
+
+	switch (relative_addr) {
+	case 0:	/*  Address:  */
+		bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
+		bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
+		break;
+
+	case 4:	/*  Data:  */
+		bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
+		    &odata : &idata, len, writeflag);
+		break;
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_cpc700_int_access():
+ *
+ *  The interrupt controller.
+ */
+DEVICE_ACCESS(cpc700_int)
+{
+	struct cpc700_data *d = (struct cpc700_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case CPC_UIC_SR:
+		/*  Status register (cleared by writing ones):  */
+		if (writeflag == MEM_READ) {
+			odata = d->sr;
+		} else {
+			d->sr &= ~idata;
+			if (!(d->sr & d->er))
+				INTERRUPT_DEASSERT(d->ppc_irq);
+		}
+		break;
+
+	case CPC_UIC_SRS:
+		/*  Status register set:  */
+		if (writeflag == MEM_READ) {
+			fatal("[ cpc700_int: read from CPC_UIC_SRS? ]\n");
+			odata = d->sr;
+		} else {
+			d->sr = idata;
+			if (d->sr & d->er)
+				INTERRUPT_ASSERT(d->ppc_irq);
+			else
+				INTERRUPT_DEASSERT(d->ppc_irq);
+		}
+		break;
+
+	case CPC_UIC_ER:
+		/*  Enable register:  */
+		if (writeflag == MEM_READ) {
+			odata = d->er;
+		} else {
+			d->er = idata;
+			if (d->sr & d->er)
+				INTERRUPT_ASSERT(d->ppc_irq);
+			else
+				INTERRUPT_DEASSERT(d->ppc_irq);
+		}
+		break;
+
+	case CPC_UIC_MSR:
+		/*  Masked status:  */
+		if (writeflag == MEM_READ) {
+			odata = d->sr & d->er;
+		} else {
+			fatal("[ cpc700_int: write to CPC_UIC_MSR? ]\n");
+		}
+		break;
+
+	default:if (writeflag == MEM_WRITE) {
+			fatal("[ cpc700_int: unimplemented write to "
+			    "offset 0x%x: data=0x%x ]\n", (int)
+			    relative_addr, (int)idata);
+		} else {
+			fatal("[ cpc700_int: unimplemented read from "
+			    "offset 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(cpc700)
+{
+	struct cpc700_data *d;
+	char tmp[300];
+	int i;
+
+	CHECK_ALLOCATION(d = (struct cpc700_data *) malloc(sizeof(struct cpc700_data)));
+	memset(d, 0, sizeof(struct cpc700_data));
+
+	/*  Connect to the CPU's interrupt pin:  */
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->ppc_irq);
+
+	/*  Register 32 CPC700 interrupts:  */
+	for (i=0; i<32; i++) {
+		struct interrupt templ;
+		char n[300];
+		snprintf(n, sizeof(n), "%s.cpc700.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 1 << i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = cpc700_interrupt_assert;
+		templ.interrupt_deassert = cpc700_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	/*  Register a PCI bus:  */
+	snprintf(tmp, sizeof(tmp), "%s.cpc700", devinit->interrupt_path);
+	d->pci_data = bus_pci_init(
+	    devinit->machine,
+	    tmp,		/*  pciirq path  */
+	    0,			/*  pci device io offset  */
+	    0,			/*  pci device mem offset  */
+	    CPC_PCI_IO_BASE,	/*  PCI portbase  */
+	    CPC_PCI_MEM_BASE,	/*  PCI membase: TODO  */
+	    tmp,		/*  PCI irqbase  */
+	    0,			/*  ISA portbase: TODO  */
+	    0,			/*  ISA membase: TODO  */
+	    tmp);		/*  ISA irqbase  */
+
+	switch (devinit->machine->machine_type) {
+
+	case MACHINE_PMPPC:
+		bus_pci_add(devinit->machine, d->pci_data,
+		    devinit->machine->memory, 0, 0, 0, "heuricon_pmppc");
+		break;
+
+	default:fatal("!\n! WARNING: cpc700 for non-implemented machine"
+		    " type\n!\n");
+		exit(1);
+	}
+
+	/*  PCI configuration registers:  */
+	memory_device_register(devinit->machine->memory, "cpc700_pci",
+	    CPC_PCICFGADR, 8, dev_cpc700_pci_access, d, DM_DEFAULT, NULL);
+
+	/*  Interrupt controller:  */
+	memory_device_register(devinit->machine->memory, "cpc700_int",
+	    CPC_UIC_BASE, CPC_UIC_SIZE, dev_cpc700_int_access, d,
+	    DM_DEFAULT, NULL);
+
+	/*  Two serial ports:  */
+	snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.cpc700.%i addr=0x%llx "
+	    "name2=tty0", devinit->interrupt_path, 31 - CPC_IB_UART_0,
+	    (long long)CPC_COM0);
+	devinit->machine->main_console_handle = (size_t)
+	    device_add(devinit->machine, tmp);
+	snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.cpc700.%i addr=0x%llx "
+	    "name2=tty1", devinit->interrupt_path, 31 - CPC_IB_UART_1,
+	    (long long)CPC_COM1);
+	device_add(devinit->machine, tmp);
+
+	devinit->return_ptr = d->pci_data;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_cpc700.cc gxemul-0.7.0+dfsg/src/devices/dev_cpc700.cc
--- gxemul-0.6.2/src/devices/dev_cpc700.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_cpc700.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,261 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: IBM CPC700 bridge (PCI and interrupt controller)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/cpc700reg.h"
-
-
-struct cpc700_data {
-	struct interrupt ppc_irq;	/*  Connected to the CPU  */
-
-	uint32_t	sr;		/*  Interrupt Status register  */
-	uint32_t	er;		/*  Interrupt Enable register  */
-
-	struct pci_data *pci_data;	/*  PCI bus  */
-};
-
-
-void cpc700_interrupt_assert(struct interrupt *interrupt)
-{
-	struct cpc700_data *d = (struct cpc700_data *) interrupt->extra;
-	d->sr |= interrupt->line;
-	if (d->sr & d->er)
-		INTERRUPT_ASSERT(d->ppc_irq);
-}
-void cpc700_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct cpc700_data *d = (struct cpc700_data *) interrupt->extra;
-	d->sr &= ~interrupt->line;
-	if (!(d->sr & d->er))
-		INTERRUPT_DEASSERT(d->ppc_irq);
-}
-
-
-/*
- *  dev_cpc700_pci_access():
- *
- *  Passes PCI indirect addr and data accesses onto bus_pci.
- */
-DEVICE_ACCESS(cpc700_pci)
-{
-	uint64_t idata = 0, odata = 0;
-	int bus, dev, func, reg;
-	struct cpc700_data *d = (struct cpc700_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
-
-	switch (relative_addr) {
-	case 0:	/*  Address:  */
-		bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
-		bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
-		break;
-
-	case 4:	/*  Data:  */
-		bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
-		    &odata : &idata, len, writeflag);
-		break;
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_cpc700_int_access():
- *
- *  The interrupt controller.
- */
-DEVICE_ACCESS(cpc700_int)
-{
-	struct cpc700_data *d = (struct cpc700_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case CPC_UIC_SR:
-		/*  Status register (cleared by writing ones):  */
-		if (writeflag == MEM_READ) {
-			odata = d->sr;
-		} else {
-			d->sr &= ~idata;
-			if (!(d->sr & d->er))
-				INTERRUPT_DEASSERT(d->ppc_irq);
-		}
-		break;
-
-	case CPC_UIC_SRS:
-		/*  Status register set:  */
-		if (writeflag == MEM_READ) {
-			fatal("[ cpc700_int: read from CPC_UIC_SRS? ]\n");
-			odata = d->sr;
-		} else {
-			d->sr = idata;
-			if (d->sr & d->er)
-				INTERRUPT_ASSERT(d->ppc_irq);
-			else
-				INTERRUPT_DEASSERT(d->ppc_irq);
-		}
-		break;
-
-	case CPC_UIC_ER:
-		/*  Enable register:  */
-		if (writeflag == MEM_READ) {
-			odata = d->er;
-		} else {
-			d->er = idata;
-			if (d->sr & d->er)
-				INTERRUPT_ASSERT(d->ppc_irq);
-			else
-				INTERRUPT_DEASSERT(d->ppc_irq);
-		}
-		break;
-
-	case CPC_UIC_MSR:
-		/*  Masked status:  */
-		if (writeflag == MEM_READ) {
-			odata = d->sr & d->er;
-		} else {
-			fatal("[ cpc700_int: write to CPC_UIC_MSR? ]\n");
-		}
-		break;
-
-	default:if (writeflag == MEM_WRITE) {
-			fatal("[ cpc700_int: unimplemented write to "
-			    "offset 0x%x: data=0x%x ]\n", (int)
-			    relative_addr, (int)idata);
-		} else {
-			fatal("[ cpc700_int: unimplemented read from "
-			    "offset 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(cpc700)
-{
-	struct cpc700_data *d;
-	char tmp[300];
-	int i;
-
-	CHECK_ALLOCATION(d = (struct cpc700_data *) malloc(sizeof(struct cpc700_data)));
-	memset(d, 0, sizeof(struct cpc700_data));
-
-	/*  Connect to the CPU's interrupt pin:  */
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->ppc_irq);
-
-	/*  Register 32 CPC700 interrupts:  */
-	for (i=0; i<32; i++) {
-		struct interrupt templ;
-		char n[300];
-		snprintf(n, sizeof(n), "%s.cpc700.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 1 << i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = cpc700_interrupt_assert;
-		templ.interrupt_deassert = cpc700_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	/*  Register a PCI bus:  */
-	snprintf(tmp, sizeof(tmp), "%s.cpc700", devinit->interrupt_path);
-	d->pci_data = bus_pci_init(
-	    devinit->machine,
-	    tmp,		/*  pciirq path  */
-	    0,			/*  pci device io offset  */
-	    0,			/*  pci device mem offset  */
-	    CPC_PCI_IO_BASE,	/*  PCI portbase  */
-	    CPC_PCI_MEM_BASE,	/*  PCI membase: TODO  */
-	    tmp,		/*  PCI irqbase  */
-	    0,			/*  ISA portbase: TODO  */
-	    0,			/*  ISA membase: TODO  */
-	    tmp);		/*  ISA irqbase  */
-
-	switch (devinit->machine->machine_type) {
-
-	case MACHINE_PMPPC:
-		bus_pci_add(devinit->machine, d->pci_data,
-		    devinit->machine->memory, 0, 0, 0, "heuricon_pmppc");
-		break;
-
-	default:fatal("!\n! WARNING: cpc700 for non-implemented machine"
-		    " type\n!\n");
-		exit(1);
-	}
-
-	/*  PCI configuration registers:  */
-	memory_device_register(devinit->machine->memory, "cpc700_pci",
-	    CPC_PCICFGADR, 8, dev_cpc700_pci_access, d, DM_DEFAULT, NULL);
-
-	/*  Interrupt controller:  */
-	memory_device_register(devinit->machine->memory, "cpc700_int",
-	    CPC_UIC_BASE, CPC_UIC_SIZE, dev_cpc700_int_access, d,
-	    DM_DEFAULT, NULL);
-
-	/*  Two serial ports:  */
-	snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.cpc700.%i addr=0x%llx "
-	    "name2=tty0", devinit->interrupt_path, 31 - CPC_IB_UART_0,
-	    (long long)CPC_COM0);
-	devinit->machine->main_console_handle = (size_t)
-	    device_add(devinit->machine, tmp);
-	snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.cpc700.%i addr=0x%llx "
-	    "name2=tty1", devinit->interrupt_path, 31 - CPC_IB_UART_1,
-	    (long long)CPC_COM1);
-	device_add(devinit->machine, tmp);
-
-	devinit->return_ptr = d->pci_data;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_dc7085.c gxemul-0.7.0+dfsg/src/devices/dev_dc7085.c
--- gxemul-0.6.2/src/devices/dev_dc7085.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dc7085.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,327 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: DC7085 serial controller, used in some DECstation models
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/dc7085.h"
+
+
+#define	DC_TICK_SHIFT		14
+
+#define	MAX_QUEUE_LEN		1024
+
+struct dc_data {
+	struct dc7085regs	regs;
+
+	int			console_handle;
+
+	unsigned char		rx_queue_char[MAX_QUEUE_LEN];
+	char			rx_queue_lineno[MAX_QUEUE_LEN];
+	int			cur_rx_queue_pos_write;
+	int			cur_rx_queue_pos_read;
+
+	int			tx_scanner;
+
+	struct interrupt	irq;
+	int			use_fb;
+
+	struct lk201_data	lk201;
+};
+
+
+/*
+ *  Check if space is available in the receive queue.
+ */
+int space_available_in_queue(void *e, int line_no)
+{
+	struct dc_data *d = (struct dc_data *) e;
+	int entries_in_use = d->cur_rx_queue_pos_write -
+	    d->cur_rx_queue_pos_read;
+
+	while (entries_in_use < 0)
+		entries_in_use += MAX_QUEUE_LEN;
+
+	if (entries_in_use < MAX_QUEUE_LEN - 20)
+		return 1;
+
+	return 0;
+}
+
+
+/*
+ *  Add a character to the receive queue.
+ */
+void add_to_rx_queue(void *e, int ch, int line_no)
+{
+	struct dc_data *d = (struct dc_data *) e;
+	int entries_in_use = d->cur_rx_queue_pos_write -
+	    d->cur_rx_queue_pos_read;
+
+	while (entries_in_use < 0)
+		entries_in_use += MAX_QUEUE_LEN;
+
+	/*  Ignore mouse updates, if they come too often:  */
+	if (entries_in_use > MAX_QUEUE_LEN/2 && line_no == DCMOUSE_PORT)
+		return;
+
+	d->rx_queue_char[d->cur_rx_queue_pos_write]   = ch;
+	d->rx_queue_lineno[d->cur_rx_queue_pos_write] = line_no;
+	d->cur_rx_queue_pos_write ++;
+	if (d->cur_rx_queue_pos_write == MAX_QUEUE_LEN)
+		d->cur_rx_queue_pos_write = 0;
+
+	if (d->cur_rx_queue_pos_write == d->cur_rx_queue_pos_read)
+		fatal("warning: add_to_rx_queue(): rx_queue overrun!\n");
+}
+
+
+DEVICE_TICK(dc7085)
+{
+	/*
+	 *  If a key is available from the keyboard, add it to the rx queue.
+	 *  If other bits are set, an interrupt might need to be caused.
+	 */
+	struct dc_data *d = (struct dc_data *) extra;
+	int avail;
+
+	d->regs.dc_csr &= ~CSR_RDONE;
+
+	if ((d->regs.dc_csr & CSR_MSE) && !(d->regs.dc_csr & CSR_TRDY)) {
+		int scanner_start = d->tx_scanner;
+
+		/*  Loop until we've checked all 4 channels, or some
+			channel was ready to transmit:  */
+
+		do {
+			d->tx_scanner = (d->tx_scanner + 1) % 4;
+
+			if (d->regs.dc_tcr & (1 << d->tx_scanner)) {
+				d->regs.dc_csr |= CSR_TRDY;
+				if (d->regs.dc_csr & CSR_TIE)
+					INTERRUPT_ASSERT(d->irq);
+
+				d->regs.dc_csr &= ~CSR_TX_LINE_NUM;
+				d->regs.dc_csr |= (d->tx_scanner << 8);
+			}
+		} while (!(d->regs.dc_csr & CSR_TRDY) &&
+		    d->tx_scanner != scanner_start);
+
+		/*  We have to return here. NetBSD can handle both
+		    rx and tx interrupts simultaneously, but Ultrix
+		    doesn't like that?  */
+
+		if (d->regs.dc_csr & CSR_TRDY)
+			return;
+	}
+
+	lk201_tick(cpu->machine, &d->lk201);
+
+	avail = d->cur_rx_queue_pos_write != d->cur_rx_queue_pos_read;
+
+	if (avail && (d->regs.dc_csr & CSR_MSE))
+		d->regs.dc_csr |= CSR_RDONE;
+
+	if ((d->regs.dc_csr & CSR_RDONE) && (d->regs.dc_csr & CSR_RIE))
+		INTERRUPT_ASSERT(d->irq);
+}
+
+
+DEVICE_ACCESS(dc7085)
+{
+	struct dc_data *d = (struct dc_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	size_t i;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  Always clear:  */
+	d->regs.dc_csr &= ~CSR_CLR;
+
+	switch (relative_addr) {
+
+	case 0x00:	/*  CSR:  Control and Status  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ dc7085 write to CSR: 0x%04x ]\n", idata);
+			idata &= (CSR_TIE | CSR_RIE | CSR_MSE | CSR_CLR
+			    | CSR_MAINT);
+			d->regs.dc_csr &= ~(CSR_TIE | CSR_RIE | CSR_MSE
+			    | CSR_CLR | CSR_MAINT);
+			d->regs.dc_csr |= idata;
+			if (!(d->regs.dc_csr & CSR_MSE))
+				d->regs.dc_csr &= ~(CSR_TRDY | CSR_RDONE);
+			goto do_return;
+		} else {
+			/*  read:  */
+
+			/*  fatal("[ dc7085 read from CSR: (csr = 0x%04x) ]\n",
+			    d->regs.dc_csr);  */
+			odata = d->regs.dc_csr;
+		}
+		break;
+
+	case 0x08:	/*  LPR:  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ dc7085 write to LPR: 0x%04x ]\n", idata);
+			d->regs.dc_rbuf_lpr = idata;
+			goto do_return;
+		} else {
+			/*  read:  */
+			int avail = d->cur_rx_queue_pos_write !=
+			    d->cur_rx_queue_pos_read;
+			int ch = 0, lineno = 0;
+			/*  debug("[ dc7085 read from RBUF: ");  */
+			if (avail) {
+				ch = d->rx_queue_char[d->cur_rx_queue_pos_read];
+				lineno = d->rx_queue_lineno[
+				    d->cur_rx_queue_pos_read];
+				d->cur_rx_queue_pos_read++;
+				if (d->cur_rx_queue_pos_read == MAX_QUEUE_LEN)
+					d->cur_rx_queue_pos_read = 0;
+				/*  if (ch >= ' ' && ch < 127)
+					debug("'%c'", ch);
+				else
+					debug("0x%x", ch);
+				debug(" for lineno %i ", lineno);  */
+			}  /*  else
+				debug("empty ");
+			debug("]\n");  */
+			odata = (avail? RBUF_DVAL:0) |
+			    (lineno << RBUF_LINE_NUM_SHIFT) | ch;
+
+			d->regs.dc_csr &= ~CSR_RDONE;
+			INTERRUPT_DEASSERT(d->irq);
+		}
+		break;
+
+	case 0x10:	/*  TCR:  */
+		if (writeflag == MEM_WRITE) {
+			/*  fatal("[ dc7085 write to TCR: 0x%04x) ]\n",
+			    (int)idata);  */
+			d->regs.dc_tcr = idata;
+			d->regs.dc_csr &= ~CSR_TRDY;
+			INTERRUPT_DEASSERT(d->irq);
+			goto do_return;
+		} else {
+			/*  read:  */
+			/*  debug("[ dc7085 read from TCR: (tcr = 0x%04x) ]\n",
+			    d->regs.dc_tcr);  */
+			odata = d->regs.dc_tcr;
+		}
+		break;
+
+	case 0x18:	/*  Modem status (R), transmit data (W)  */
+		if (writeflag == MEM_WRITE) {
+			int line_no = (d->regs.dc_csr >>
+			    RBUF_LINE_NUM_SHIFT) & 0x3;
+			idata &= 0xff;
+
+			lk201_tx_data(&d->lk201, line_no, idata);
+
+			d->regs.dc_csr &= ~CSR_TRDY;
+			INTERRUPT_DEASSERT(d->irq);
+		} else {
+			/*  read:  */
+			d->regs.dc_msr_tdr |= MSR_DSR2 | MSR_CD2 |
+			    MSR_DSR3 | MSR_CD3;
+			debug("[ dc7085 read from MSR: (msr_tdr = 0x%04x) ]\n",
+			    d->regs.dc_msr_tdr);
+			odata = d->regs.dc_msr_tdr;
+		}
+		break;
+
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ dc7085 read from 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			debug("[ dc7085 write to 0x%08lx:",
+			    (long)relative_addr);
+			for (i=0; i<len; i++)
+				debug(" %02x", data[i]);
+			debug(" ]\n");
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+do_return:
+	dev_dc7085_tick(cpu, extra);
+
+	return 1;
+}
+
+
+/*
+ *  dev_dc7085_init():
+ *
+ *  Initialize a dc7085 serial controller device. use_fb should be non-zero
+ *  if a framebuffer device is used. Channel 0 will then be treated as a
+ *  DECstation keyboard, instead of a plain serial console.
+ */
+int dev_dc7085_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, char *irq_path, int use_fb)
+{
+	struct dc_data *d;
+
+	CHECK_ALLOCATION(d = (struct dc_data *) malloc(sizeof(struct dc_data)));
+	memset(d, 0, sizeof(struct dc_data));
+
+	INTERRUPT_CONNECT(irq_path, d->irq);
+	d->use_fb = use_fb;
+
+	d->regs.dc_csr = CSR_TRDY | CSR_MSE;
+	d->regs.dc_tcr = 0x00;
+
+	d->console_handle = console_start_slave(machine, "DC7085", 1);
+
+	lk201_init(&d->lk201, use_fb,
+	    space_available_in_queue,
+	    add_to_rx_queue,
+	    d->console_handle, d);
+
+	memory_device_register(mem, "dc7085", baseaddr, DEV_DC7085_LENGTH,
+	    dev_dc7085_access, d, DM_DEFAULT, NULL);
+	machine_add_tickfunction(machine, dev_dc7085_tick, d,
+	    DC_TICK_SHIFT);
+
+	return d->console_handle;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_dc7085.cc gxemul-0.7.0+dfsg/src/devices/dev_dc7085.cc
--- gxemul-0.6.2/src/devices/dev_dc7085.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dc7085.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,323 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: DC7085 serial controller, used in some DECstation models
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/dc7085.h"
-
-
-#define	DC_TICK_SHIFT		14
-
-#define	MAX_QUEUE_LEN		32768
-
-struct dc_data {
-	struct dc7085regs	regs;
-
-	int			console_handle;
-
-	/*  For slow_serial_interrupts_hack_for_linux:  */
-	int			just_transmitted_something;
-
-	unsigned char		rx_queue_char[MAX_QUEUE_LEN];
-	char			rx_queue_lineno[MAX_QUEUE_LEN];
-	int			cur_rx_queue_pos_write;
-	int			cur_rx_queue_pos_read;
-
-	int			tx_scanner;
-
-	struct interrupt	irq;
-	int			use_fb;
-
-	struct lk201_data	lk201;
-};
-
-
-/*
- *  Add a character to the receive queue.
- */
-void add_to_rx_queue(void *e, int ch, int line_no)
-{
-	struct dc_data *d = (struct dc_data *) e;
-	int entries_in_use = d->cur_rx_queue_pos_write -
-	    d->cur_rx_queue_pos_read;
-
-	while (entries_in_use < 0)
-		entries_in_use += MAX_QUEUE_LEN;
-
-	/*  Ignore mouse updates, if they come too often:  */
-	if (entries_in_use > MAX_QUEUE_LEN/2 && line_no == DCMOUSE_PORT)
-		return;
-
-	d->rx_queue_char[d->cur_rx_queue_pos_write]   = ch;
-	d->rx_queue_lineno[d->cur_rx_queue_pos_write] = line_no;
-	d->cur_rx_queue_pos_write ++;
-	if (d->cur_rx_queue_pos_write == MAX_QUEUE_LEN)
-		d->cur_rx_queue_pos_write = 0;
-
-	if (d->cur_rx_queue_pos_write == d->cur_rx_queue_pos_read)
-		fatal("warning: add_to_rx_queue(): rx_queue overrun!\n");
-}
-
-
-DEVICE_TICK(dc7085)
-{
-	/*
-	 *  If a key is available from the keyboard, add it to the rx queue.
-	 *  If other bits are set, an interrupt might need to be caused.
-	 */
-	struct dc_data *d = (struct dc_data *) extra;
-	int avail;
-
-	if (cpu->machine->slow_serial_interrupts_hack_for_linux) {
-		/*
-		 *  Special hack to prevent Linux from Oopsing. (This makes
-		 *  interrupts not come as fast as possible.)
-		 */
-		if (d->just_transmitted_something) {
-			d->just_transmitted_something --;
-			return;
-		}
-	}
-
-	d->regs.dc_csr &= ~CSR_RDONE;
-
-	if ((d->regs.dc_csr & CSR_MSE) && !(d->regs.dc_csr & CSR_TRDY)) {
-		int scanner_start = d->tx_scanner;
-
-		/*  Loop until we've checked all 4 channels, or some
-			channel was ready to transmit:  */
-
-		do {
-			d->tx_scanner = (d->tx_scanner + 1) % 4;
-
-			if (d->regs.dc_tcr & (1 << d->tx_scanner)) {
-				d->regs.dc_csr |= CSR_TRDY;
-				if (d->regs.dc_csr & CSR_TIE)
-					INTERRUPT_ASSERT(d->irq);
-
-				d->regs.dc_csr &= ~CSR_TX_LINE_NUM;
-				d->regs.dc_csr |= (d->tx_scanner << 8);
-			}
-		} while (!(d->regs.dc_csr & CSR_TRDY) &&
-		    d->tx_scanner != scanner_start);
-
-		/*  We have to return here. NetBSD can handle both
-		    rx and tx interrupts simultaneously, but Ultrix
-		    doesn't like that?  */
-
-		if (d->regs.dc_csr & CSR_TRDY)
-			return;
-	}
-
-	lk201_tick(cpu->machine, &d->lk201);
-
-	avail = d->cur_rx_queue_pos_write != d->cur_rx_queue_pos_read;
-
-	if (avail && (d->regs.dc_csr & CSR_MSE))
-		d->regs.dc_csr |= CSR_RDONE;
-
-	if ((d->regs.dc_csr & CSR_RDONE) && (d->regs.dc_csr & CSR_RIE))
-		INTERRUPT_ASSERT(d->irq);
-}
-
-
-DEVICE_ACCESS(dc7085)
-{
-	struct dc_data *d = (struct dc_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	size_t i;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  Always clear:  */
-	d->regs.dc_csr &= ~CSR_CLR;
-
-	switch (relative_addr) {
-
-	case 0x00:	/*  CSR:  Control and Status  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ dc7085 write to CSR: 0x%04x ]\n", idata);
-			idata &= (CSR_TIE | CSR_RIE | CSR_MSE | CSR_CLR
-			    | CSR_MAINT);
-			d->regs.dc_csr &= ~(CSR_TIE | CSR_RIE | CSR_MSE
-			    | CSR_CLR | CSR_MAINT);
-			d->regs.dc_csr |= idata;
-			if (!(d->regs.dc_csr & CSR_MSE))
-				d->regs.dc_csr &= ~(CSR_TRDY | CSR_RDONE);
-			goto do_return;
-		} else {
-			/*  read:  */
-
-			/*  fatal("[ dc7085 read from CSR: (csr = 0x%04x) ]\n",
-			    d->regs.dc_csr);  */
-			odata = d->regs.dc_csr;
-		}
-		break;
-
-	case 0x08:	/*  LPR:  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ dc7085 write to LPR: 0x%04x ]\n", idata);
-			d->regs.dc_rbuf_lpr = idata;
-			goto do_return;
-		} else {
-			/*  read:  */
-			int avail = d->cur_rx_queue_pos_write !=
-			    d->cur_rx_queue_pos_read;
-			int ch = 0, lineno = 0;
-			/*  debug("[ dc7085 read from RBUF: ");  */
-			if (avail) {
-				ch = d->rx_queue_char[d->cur_rx_queue_pos_read];
-				lineno = d->rx_queue_lineno[
-				    d->cur_rx_queue_pos_read];
-				d->cur_rx_queue_pos_read++;
-				if (d->cur_rx_queue_pos_read == MAX_QUEUE_LEN)
-					d->cur_rx_queue_pos_read = 0;
-				/*  if (ch >= ' ' && ch < 127)
-					debug("'%c'", ch);
-				else
-					debug("0x%x", ch);
-				debug(" for lineno %i ", lineno);  */
-			}  /*  else
-				debug("empty ");
-			debug("]\n");  */
-			odata = (avail? RBUF_DVAL:0) |
-			    (lineno << RBUF_LINE_NUM_SHIFT) | ch;
-
-			d->regs.dc_csr &= ~CSR_RDONE;
-			INTERRUPT_DEASSERT(d->irq);
-
-			d->just_transmitted_something = 4;
-		}
-		break;
-
-	case 0x10:	/*  TCR:  */
-		if (writeflag == MEM_WRITE) {
-			/*  fatal("[ dc7085 write to TCR: 0x%04x) ]\n",
-			    (int)idata);  */
-			d->regs.dc_tcr = idata;
-			d->regs.dc_csr &= ~CSR_TRDY;
-			INTERRUPT_DEASSERT(d->irq);
-			goto do_return;
-		} else {
-			/*  read:  */
-			/*  debug("[ dc7085 read from TCR: (tcr = 0x%04x) ]\n",
-			    d->regs.dc_tcr);  */
-			odata = d->regs.dc_tcr;
-		}
-		break;
-
-	case 0x18:	/*  Modem status (R), transmit data (W)  */
-		if (writeflag == MEM_WRITE) {
-			int line_no = (d->regs.dc_csr >>
-			    RBUF_LINE_NUM_SHIFT) & 0x3;
-			idata &= 0xff;
-
-			lk201_tx_data(&d->lk201, line_no, idata);
-
-			d->regs.dc_csr &= ~CSR_TRDY;
-			INTERRUPT_DEASSERT(d->irq);
-
-			d->just_transmitted_something = 4;
-		} else {
-			/*  read:  */
-			d->regs.dc_msr_tdr |= MSR_DSR2 | MSR_CD2 |
-			    MSR_DSR3 | MSR_CD3;
-			debug("[ dc7085 read from MSR: (msr_tdr = 0x%04x) ]\n",
-			    d->regs.dc_msr_tdr);
-			odata = d->regs.dc_msr_tdr;
-		}
-		break;
-
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ dc7085 read from 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			debug("[ dc7085 write to 0x%08lx:",
-			    (long)relative_addr);
-			for (i=0; i<len; i++)
-				debug(" %02x", data[i]);
-			debug(" ]\n");
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-do_return:
-	dev_dc7085_tick(cpu, extra);
-
-	return 1;
-}
-
-
-/*
- *  dev_dc7085_init():
- *
- *  Initialize a dc7085 serial controller device. use_fb should be non-zero
- *  if a framebuffer device is used. Channel 0 will then be treated as a
- *  DECstation keyboard, instead of a plain serial console.
- */
-int dev_dc7085_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, char *irq_path, int use_fb)
-{
-	struct dc_data *d;
-
-	CHECK_ALLOCATION(d = (struct dc_data *) malloc(sizeof(struct dc_data)));
-	memset(d, 0, sizeof(struct dc_data));
-
-	INTERRUPT_CONNECT(irq_path, d->irq);
-	d->use_fb = use_fb;
-
-	d->regs.dc_csr = CSR_TRDY | CSR_MSE;
-	d->regs.dc_tcr = 0x00;
-
-	d->console_handle = console_start_slave(machine, "DC7085", 1);
-
-	lk201_init(&d->lk201, use_fb, add_to_rx_queue, d->console_handle, d);
-
-	memory_device_register(mem, "dc7085", baseaddr, DEV_DC7085_LENGTH,
-	    dev_dc7085_access, d, DM_DEFAULT, NULL);
-	machine_add_tickfunction(machine, dev_dc7085_tick, d,
-	    DC_TICK_SHIFT);
-
-	return d->console_handle;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_dec21030.c gxemul-0.7.0+dfsg/src/devices/dev_dec21030.c
--- gxemul-0.6.2/src/devices/dev_dec21030.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dec21030.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,254 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: DEC 21030 "TGA" graphics card
+ *
+ *  Resolutions that seem to be possible:  640x480, 1024x768, 1280x1024.
+ *  8 bits, perhaps others? (24 bit?)
+ *
+ *  NetBSD should say something like this:
+ *
+ *	tga0 at pci0 dev 12 function 0: TGA2 pass 2, board type T8-02
+ *	tga0: 1280 x 1024, 8bpp, Bt485 RAMDAC
+ *
+ *  See netbsd/src/sys/dev/pci/tga.c for more info.
+ *	tga_rop_vtov() for video-to-video copy (scrolling and fast
+ *			erasing)
+ *
+ *  TODO: This device is far from complete.
+ *        The RAMDAC is non-existant.
+ *
+ *  TODO:  all fb device writes with direct writes to the framebuffer
+ *  memory, and update the x1,y1,x2,y2 coordinates instead.
+ *  That will give better performance.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/tgareg.h"
+
+
+#define	MAX_XSIZE	2048
+
+#if 1
+int dec21030_default_xsize = 640;
+int dec21030_default_ysize = 480;
+#else
+int dec21030_default_xsize = 1024;
+int dec21030_default_ysize = 768;
+#endif
+
+
+/*  TODO:  Ugly hack:  this causes the framebuffer to be in memory  */
+#define	FRAMEBUFFER_PADDR	0x4000000000ULL
+#define	FRAMEBUFFER_BASE	0x201000
+
+
+struct dec21030_data {
+	int		graphics_mode;
+	uint32_t	pixel_mask;
+	uint32_t	copy_source;
+	uint32_t	color;
+	struct vfb_data *vfb_data;
+};
+
+
+DEVICE_ACCESS(dec21030)
+{
+	struct dec21030_data *d = (struct dec21030_data *) extra;
+	uint64_t idata, odata = 0;
+	int reg, r, white = 255, black = 0;
+	size_t i, newlen;
+	unsigned char buf2[MAX_XSIZE];
+
+	/*  Read/write to the framebuffer:  */
+	if (relative_addr >= FRAMEBUFFER_BASE) {
+		/*  TODO:  Perhaps this isn't graphics mode (GMOR),
+		    but GOPR (operation) specific:  */
+
+		switch (d->graphics_mode) {
+		case 1:		/*  Bitmap write:  */
+			/*  Copy from data into buf2:  */
+			for (i=0; i<len; i++) {
+				buf2[i*8 + 0] = data[i]&1? white : black;
+				buf2[i*8 + 1] = data[i]&2? white : black;
+				buf2[i*8 + 2] = data[i]&4? white : black;
+				buf2[i*8 + 3] = data[i]&8? white : black;
+				buf2[i*8 + 4] = data[i]&16? white : black;
+				buf2[i*8 + 5] = data[i]&32? white : black;
+				buf2[i*8 + 6] = data[i]&64? white : black;
+				buf2[i*8 + 7] = data[i]&128? white : black;
+			}
+
+			newlen = 0;
+			for (i=0; i<32; i++)
+				if (d->pixel_mask & (1 << i))
+					newlen ++;
+
+			if (newlen > len * 8)
+				newlen = len * 8;
+
+			r = dev_fb_access(cpu, mem, relative_addr -
+			    FRAMEBUFFER_BASE, buf2, newlen, writeflag,
+			    d->vfb_data);
+			break;
+		case 0x2d:	/*  Block fill:  */
+			/*  data is nr of pixels to fill minus one  */
+			newlen = memory_readmax64(cpu, data, len) + 1;
+			/*  debug("YO addr=0x%08x, newlen=%i\n", relative_addr,
+			    newlen);  */
+			if (newlen > MAX_XSIZE)
+				newlen = MAX_XSIZE;
+			memset(buf2, d->color, newlen);
+			r = dev_fb_access(cpu, mem, relative_addr -
+			    FRAMEBUFFER_BASE, buf2, newlen, MEM_WRITE,
+			    d->vfb_data);
+			break;
+		default:
+			r = dev_fb_access(cpu, mem, relative_addr -
+			    FRAMEBUFFER_BASE, data, len, writeflag,
+			    d->vfb_data);
+		}
+		return r;
+	}
+
+	idata = memory_readmax64(cpu, data, len);
+
+	/*  Read from/write to the dec21030's registers:  */
+	reg = ((relative_addr - TGA_MEM_CREGS) & (TGA_CREGS_ALIAS - 1))
+	    / sizeof(uint32_t);
+        switch (reg) {
+
+	/*  Color?  (there are 8 of these, 2 used in 8-bit mode,
+	    8 in 24-bit mode)  */
+	case TGA_REG_GBCR0:
+		if (writeflag == MEM_WRITE)
+			d->color = idata;
+		else
+			odata = d->color;
+		break;
+
+	/*  Board revision  */
+/*	case TGA_MEM_CREGS + sizeof(uint32_t) * TGA_REG_GREV:  */
+	case TGA_REG_GREV:
+		/*  01,02,03,04 (rev0) and 20,21,22 (rev1) are allowed  */
+		odata = 0x04;
+		break;
+
+	/*  Graphics Mode:  */
+	case TGA_REG_GMOR:
+		if (writeflag == MEM_WRITE)
+			d->graphics_mode = idata;
+		else
+			odata = d->graphics_mode;
+		break;
+
+	/*  Pixel mask:  */
+	case TGA_REG_GPXR_S:		/*  "one-shot"  */
+	case TGA_REG_GPXR_P:		/*  persistant  */
+		if (writeflag == MEM_WRITE)
+			d->pixel_mask = idata;
+		else
+			odata = d->pixel_mask;
+		break;
+
+	/*  Horizonsal size:  */
+	case TGA_REG_VHCR:
+		odata = dec21030_default_xsize / 4;	/*  lowest 9 bits  */
+		break;
+
+	/*  Vertical size:  */
+	case TGA_REG_VVCR:
+		odata = dec21030_default_ysize;		/*  lowest 11 bits  */
+		break;
+
+	/*  Block copy source:  */
+	case TGA_REG_GCSR:
+		d->copy_source = idata;
+		debug("[ dec21030: block copy source = 0x%08x ]\n", idata);
+		break;
+
+	/*  Block copy destination:  */
+	case TGA_REG_GCDR:
+		debug("[ dec21030: block copy destination = 0x%08x ]\n", idata);
+		newlen = 64;
+		/*  Both source and destination are raw framebuffer addresses,
+		    offset by 0x1000.  */
+		dev_fb_access(cpu, mem, d->copy_source - 0x1000,
+		    buf2, newlen, MEM_READ,  d->vfb_data);
+		dev_fb_access(cpu, mem, idata - 0x1000,
+		    buf2, newlen, MEM_WRITE, d->vfb_data);
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			debug("[ dec21030: unimplemented write to address"
+			    " 0x%x (=reg 0x%x), data=0x%02x ]\n",
+			    (int)relative_addr, reg, (int)idata);
+		else
+			debug("[ dec21030: unimplemented read from address"
+			    " 0x%x (=reg 0x%x) ]\n", (int)relative_addr, reg);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(dec21030)
+{
+	struct dec21030_data *d;
+
+	CHECK_ALLOCATION(d = (struct dec21030_data *) malloc(sizeof(struct dec21030_data)));
+	memset(d, 0, sizeof(struct dec21030_data));
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, 128*1048576, dev_dec21030_access, d,
+	    DM_DEFAULT, NULL);
+
+	/*
+	 *  TODO:  I have no idea about how/where this framebuffer should
+	 *  be in relation to the pci device
+	 */
+	d->vfb_data = dev_fb_init(devinit->machine, devinit->machine->memory,
+	    FRAMEBUFFER_PADDR, VFB_GENERIC,
+	    dec21030_default_xsize, dec21030_default_ysize,
+	    dec21030_default_xsize, dec21030_default_ysize, 8, "TGA");
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_dec21030.cc gxemul-0.7.0+dfsg/src/devices/dev_dec21030.cc
--- gxemul-0.6.2/src/devices/dev_dec21030.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dec21030.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,254 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: DEC 21030 "TGA" graphics card
- *
- *  Resolutions that seem to be possible:  640x480, 1024x768, 1280x1024.
- *  8 bits, perhaps others? (24 bit?)
- *
- *  NetBSD should say something like this:
- *
- *	tga0 at pci0 dev 12 function 0: TGA2 pass 2, board type T8-02
- *	tga0: 1280 x 1024, 8bpp, Bt485 RAMDAC
- *
- *  See netbsd/src/sys/dev/pci/tga.c for more info.
- *	tga_rop_vtov() for video-to-video copy (scrolling and fast
- *			erasing)
- *
- *  TODO: This device is far from complete.
- *        The RAMDAC is non-existant.
- *
- *  TODO:  all fb device writes with direct writes to the framebuffer
- *  memory, and update the x1,y1,x2,y2 coordinates instead.
- *  That will give better performance.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/tgareg.h"
-
-
-#define	MAX_XSIZE	2048
-
-#if 1
-int dec21030_default_xsize = 640;
-int dec21030_default_ysize = 480;
-#else
-int dec21030_default_xsize = 1024;
-int dec21030_default_ysize = 768;
-#endif
-
-
-/*  TODO:  Ugly hack:  this causes the framebuffer to be in memory  */
-#define	FRAMEBUFFER_PADDR	0x4000000000ULL
-#define	FRAMEBUFFER_BASE	0x201000
-
-
-struct dec21030_data {
-	int		graphics_mode;
-	uint32_t	pixel_mask;
-	uint32_t	copy_source;
-	uint32_t	color;
-	struct vfb_data *vfb_data;
-};
-
-
-DEVICE_ACCESS(dec21030)
-{
-	struct dec21030_data *d = (struct dec21030_data *) extra;
-	uint64_t idata, odata = 0;
-	int reg, r, white = 255, black = 0;
-	size_t i, newlen;
-	unsigned char buf2[MAX_XSIZE];
-
-	/*  Read/write to the framebuffer:  */
-	if (relative_addr >= FRAMEBUFFER_BASE) {
-		/*  TODO:  Perhaps this isn't graphics mode (GMOR),
-		    but GOPR (operation) specific:  */
-
-		switch (d->graphics_mode) {
-		case 1:		/*  Bitmap write:  */
-			/*  Copy from data into buf2:  */
-			for (i=0; i<len; i++) {
-				buf2[i*8 + 0] = data[i]&1? white : black;
-				buf2[i*8 + 1] = data[i]&2? white : black;
-				buf2[i*8 + 2] = data[i]&4? white : black;
-				buf2[i*8 + 3] = data[i]&8? white : black;
-				buf2[i*8 + 4] = data[i]&16? white : black;
-				buf2[i*8 + 5] = data[i]&32? white : black;
-				buf2[i*8 + 6] = data[i]&64? white : black;
-				buf2[i*8 + 7] = data[i]&128? white : black;
-			}
-
-			newlen = 0;
-			for (i=0; i<32; i++)
-				if (d->pixel_mask & (1 << i))
-					newlen ++;
-
-			if (newlen > len * 8)
-				newlen = len * 8;
-
-			r = dev_fb_access(cpu, mem, relative_addr -
-			    FRAMEBUFFER_BASE, buf2, newlen, writeflag,
-			    d->vfb_data);
-			break;
-		case 0x2d:	/*  Block fill:  */
-			/*  data is nr of pixels to fill minus one  */
-			newlen = memory_readmax64(cpu, data, len) + 1;
-			/*  debug("YO addr=0x%08x, newlen=%i\n", relative_addr,
-			    newlen);  */
-			if (newlen > MAX_XSIZE)
-				newlen = MAX_XSIZE;
-			memset(buf2, d->color, newlen);
-			r = dev_fb_access(cpu, mem, relative_addr -
-			    FRAMEBUFFER_BASE, buf2, newlen, MEM_WRITE,
-			    d->vfb_data);
-			break;
-		default:
-			r = dev_fb_access(cpu, mem, relative_addr -
-			    FRAMEBUFFER_BASE, data, len, writeflag,
-			    d->vfb_data);
-		}
-		return r;
-	}
-
-	idata = memory_readmax64(cpu, data, len);
-
-	/*  Read from/write to the dec21030's registers:  */
-	reg = ((relative_addr - TGA_MEM_CREGS) & (TGA_CREGS_ALIAS - 1))
-	    / sizeof(uint32_t);
-        switch (reg) {
-
-	/*  Color?  (there are 8 of these, 2 used in 8-bit mode,
-	    8 in 24-bit mode)  */
-	case TGA_REG_GBCR0:
-		if (writeflag == MEM_WRITE)
-			d->color = idata;
-		else
-			odata = d->color;
-		break;
-
-	/*  Board revision  */
-/*	case TGA_MEM_CREGS + sizeof(uint32_t) * TGA_REG_GREV:  */
-	case TGA_REG_GREV:
-		/*  01,02,03,04 (rev0) and 20,21,22 (rev1) are allowed  */
-		odata = 0x04;
-		break;
-
-	/*  Graphics Mode:  */
-	case TGA_REG_GMOR:
-		if (writeflag == MEM_WRITE)
-			d->graphics_mode = idata;
-		else
-			odata = d->graphics_mode;
-		break;
-
-	/*  Pixel mask:  */
-	case TGA_REG_GPXR_S:		/*  "one-shot"  */
-	case TGA_REG_GPXR_P:		/*  persistant  */
-		if (writeflag == MEM_WRITE)
-			d->pixel_mask = idata;
-		else
-			odata = d->pixel_mask;
-		break;
-
-	/*  Horizonsal size:  */
-	case TGA_REG_VHCR:
-		odata = dec21030_default_xsize / 4;	/*  lowest 9 bits  */
-		break;
-
-	/*  Vertical size:  */
-	case TGA_REG_VVCR:
-		odata = dec21030_default_ysize;		/*  lowest 11 bits  */
-		break;
-
-	/*  Block copy source:  */
-	case TGA_REG_GCSR:
-		d->copy_source = idata;
-		debug("[ dec21030: block copy source = 0x%08x ]\n", idata);
-		break;
-
-	/*  Block copy destination:  */
-	case TGA_REG_GCDR:
-		debug("[ dec21030: block copy destination = 0x%08x ]\n", idata);
-		newlen = 64;
-		/*  Both source and destination are raw framebuffer addresses,
-		    offset by 0x1000.  */
-		dev_fb_access(cpu, mem, d->copy_source - 0x1000,
-		    buf2, newlen, MEM_READ,  d->vfb_data);
-		dev_fb_access(cpu, mem, idata - 0x1000,
-		    buf2, newlen, MEM_WRITE, d->vfb_data);
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE)
-			debug("[ dec21030: unimplemented write to address"
-			    " 0x%x (=reg 0x%x), data=0x%02x ]\n",
-			    (int)relative_addr, reg, (int)idata);
-		else
-			debug("[ dec21030: unimplemented read from address"
-			    " 0x%x (=reg 0x%x) ]\n", (int)relative_addr, reg);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(dec21030)
-{
-	struct dec21030_data *d;
-
-	CHECK_ALLOCATION(d = (struct dec21030_data *) malloc(sizeof(struct dec21030_data)));
-	memset(d, 0, sizeof(struct dec21030_data));
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, 128*1048576, dev_dec21030_access, d,
-	    DM_DEFAULT, NULL);
-
-	/*
-	 *  TODO:  I have no idea about how/where this framebuffer should
-	 *  be in relation to the pci device
-	 */
-	d->vfb_data = dev_fb_init(devinit->machine, devinit->machine->memory,
-	    FRAMEBUFFER_PADDR, VFB_GENERIC,
-	    dec21030_default_xsize, dec21030_default_ysize,
-	    dec21030_default_xsize, dec21030_default_ysize, 8, "TGA");
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_dec21143.c gxemul-0.7.0+dfsg/src/devices/dev_dec21143.c
--- gxemul-0.6.2/src/devices/dev_dec21143.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dec21143.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1432 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: DEC 21143 "Tulip" ethernet controller
+ *
+ *  Implemented from Intel document 278074-001 ("21143 PC/CardBus 10/100Mb/s
+ *  Ethernet LAN Controller") and by reverse-engineering OpenBSD and NetBSD
+ *  sources.
+ *
+ *  This device emulates several sub-components:
+ *
+ *	21143:	This is the actual ethernet controller.
+ *
+ *	MII:	The "physical" network interface.
+ *
+ *	SROM:	A ROM area containing setting such as which MAC address to
+ *		use, and info about the MII.
+ *
+ *
+ *  TODO:
+ *	o)  Handle _writes_ to MII registers.
+ *	o)  Make it work with modern Linux kernels (as a guest OS).
+ *	o)  Endianness for descriptors? If necessary.
+ *	o)  Don't hardcode as many values.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "emul.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "net.h"
+
+#include "thirdparty/mii.h"
+#include "thirdparty/tulipreg.h"
+
+
+/*  #define debug fatal  */
+
+#define	DEC21143_TICK_SHIFT		16
+
+#define	N_REGS			32
+#define	ROM_WIDTH		6
+
+struct dec21143_data {
+	/*  NIC common data  */
+	struct nic_data	nic;
+
+	struct interrupt irq;
+	int		irq_was_asserted;
+
+	/*  PCI:  */
+	int		pci_little_endian;
+
+	/*  SROM emulation:  */
+	uint8_t		srom[1 << (ROM_WIDTH + 1)];
+	int		srom_curbit;
+	int		srom_opcode;
+	int		srom_opcode_has_started;
+	int		srom_addr;
+
+	/*  MII PHY emulation:  */
+	uint16_t	mii_phy_reg[MII_NPHY * 32];
+	int		mii_state;
+	int		mii_bit;
+	int		mii_opcode;
+	int		mii_phyaddr;
+	int		mii_regaddr;
+
+	/*  21143 registers:  */
+	uint32_t	reg[N_REGS];
+
+	/*  Internal TX state:  */
+	uint32_t	cur_tx_addr;
+	unsigned char	*cur_tx_buf;
+	int		cur_tx_buf_len;
+	int		tx_idling;
+	int		tx_idling_threshold;
+
+	/*  Internal RX state:  */
+	uint32_t	cur_rx_addr;
+	unsigned char	*cur_rx_buf;
+	int		cur_rx_buf_len;
+	int		cur_rx_offset;
+
+	/*
+	 *  Receive filter information.  We keep our own copy of
+	 *  the promiscuous flag because to implement some of the
+	 *  filtering modes, we need to tell the network layer that
+	 *  we want all packets.
+	 */
+	int		(*drop_packet)(struct net *, struct dec21143_data *);
+	int		allmulti;
+	int		promiscuous;
+	int		filter_needs_promiscuous;
+	uint8_t		perfect_filter[6 * TULIP_MAXADDRS];
+
+	/*  Only 16 bits are used per filter word.  */
+#define	MCHASH_NWORDS	(TULIP_MCHASHSIZE / 16)
+	uint32_t	hash_filter[MCHASH_NWORDS];
+	int		hash_filter_saturated;
+
+	/*
+	 *  XXX XXX XXX
+	 *  XXX UGLY HACK.  Need a proper way to deal with
+	 *  XXX different PCI vs. CPU views of RAM.
+	 *  XXX XXX XXX
+	 */
+	uint32_t	xxx_dma_to_phys_mask;
+};
+
+/*  XXX This is an UGLY hack.  */
+static uint64_t dma_to_phys(const struct dec21143_data *d, uint32_t dma_addr)
+{
+	return dma_addr & d->xxx_dma_to_phys_mask;
+}
+
+
+static inline uint32_t load_le32(const uint8_t *buf)
+{
+	return buf[0] | ((uint32_t)buf[1] << 8) |
+	    ((uint32_t)buf[2] << 16) | ((uint32_t)buf[3] << 24);
+}
+
+
+static inline void store_le32(uint8_t *buf, uint32_t val)
+{
+	buf[0] = (uint8_t)val;
+	buf[1] = (uint8_t)(val >> 8);
+	buf[2] = (uint8_t)(val >> 16);
+	buf[3] = (uint8_t)(val >> 24);
+}
+
+
+/*  Internal states during MII data stream decode:  */
+#define	MII_STATE_RESET				0
+#define	MII_STATE_START_WAIT			1
+#define	MII_STATE_READ_OP			2
+#define	MII_STATE_READ_PHYADDR_REGADDR		3
+#define	MII_STATE_A				4
+#define	MII_STATE_D				5
+#define	MII_STATE_IDLE				6
+
+
+/*
+ * The 21143 has multiple address matching modes:
+ *
+ *	- Perfect Filtering: The chip interprets the descriptor buffer
+ *	  as a table of 16 MAC addresses that it should match.  The
+ *	  station address and broadcast must be included in the list.
+ *
+ *	- Hash Perfect Filtering: The chip interprets the descriptor buffer
+ *	  as a 512-bit hash table plus one perfect filter match.  Multicast
+ *	  addresses only are matched against the hash table.
+ *
+ *	- Inverse Filtering: Like Perfect Filtering, but the table is
+ *	  addresses NOT to match.
+ *
+ *	- Hash-only Filtering: Like Hash Perfect, except without the Perfect.
+ *	  All addresses are matched against the hash table.
+ *
+ * The mode seleted by the TDCTL descriptor field is reflected in 3
+ * read-only bits in the OPMODE register.
+ *
+ * We implement all 4 (NetBSD, at least, is known to use Perfect and
+ * Hash Perfect on the 21143; it also uses Hash-only on the 21140).
+ */
+
+#define	TDCTL_Tx_FT_MASK	(TDCTL_Tx_FT1|TDCTL_Tx_FT0)
+
+#define	dec21143_mchash(addr)	\
+	(net_ether_crc32_le((addr), 6) & (TULIP_MCHASHSIZE - 1))
+
+static int dec21143_drop_packet_perfect(struct net *net,
+	struct dec21143_data *d)
+{
+	int i;
+
+	for (i = 0; i < TULIP_MAXADDRS; i++) {
+		if (net_ether_eq(d->cur_rx_buf, &d->perfect_filter[6 * i])) {
+			/* Match! */
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+static int dec21143_drop_packet_hashperfect(struct net *net,
+	struct dec21143_data *d)
+{
+
+	/*
+	 * In this mode, we have the network layer match our station
+	 * address, and we reflect the true promiscuous status there
+	 * as well.  This means that if it's not a multicast address,
+	 * then it's already been sufficiently matched.
+	 */
+	if (! net_ether_multicast(d->cur_rx_buf))
+		return 0;
+
+	/*
+	 * Note that the broadcast address is also checked against
+	 * the hash table in this mode!
+	 */
+
+	const uint32_t hash = dec21143_mchash(d->cur_rx_buf);
+	if (d->hash_filter[hash >> 4] & (1U << (hash & 0xf))) {
+		/* Match! */
+		return 0;
+	}
+
+	return 1;
+}
+
+static int dec21143_drop_packet_inverse(struct net *net,
+	struct dec21143_data *d)
+{
+	return !dec21143_drop_packet_perfect(net, d);
+}
+
+static int dec21143_drop_packet_hashonly(struct net *net,
+	struct dec21143_data *d)
+{
+	const uint32_t hash = dec21143_mchash(d->cur_rx_buf);
+	if (d->hash_filter[hash >> 4] & (1U << (hash & 0xf))) {
+		/* Match! */
+		return 0;
+	}
+
+	return 1;
+}
+
+
+/*
+ *  dec21143_rx_drop_packet():
+ *
+ *  Implement the logic to determine if we should drop a packet
+ *  before paassing it to the guest.  Returns 1 if the packet
+ *  was dropped.
+ */
+static int dec21143_rx_drop_packet(struct net *net, struct dec21143_data *d)
+{
+	/* Only implement filtering if using a tap device. */
+	if (net->tapdev == NULL)
+		return 0;
+
+	/*
+	 * We might have told the network layer that we're promiscuous
+	 * due to the chosen filtering mode, so check the truth here.
+	 */
+	if (d->promiscuous)
+		return 0;
+
+	/*
+	 * If the guest wants all multicast (either all the bits are
+	 * set or the OPMODE_PM bit is set), then check to see if we
+	 * can short-circuit the checks.
+	 */
+	if (d->allmulti && net_ether_multicast(d->cur_rx_buf))
+		return 0;
+
+	/*
+	 * Note that if we haven't gotten a setup packet yet, then
+	 * d->drop_packet will be NULL.  If this happens, we always
+	 * drop.  This is akin to the real hardware defaulting to
+	 * Perfect filtering mode but not having any valid addresses
+	 * in the list to match against.
+	 */
+	if (d->drop_packet == NULL || d->drop_packet(net, d)) {
+		/* Not for us; drop the packet. */
+		free(d->cur_rx_buf);
+		d->cur_rx_buf = NULL;
+		d->cur_rx_buf_len = 0;
+		return 1;
+	}
+
+	return 0;
+}
+
+
+/*
+ *  dec21143_update_rx_mode():
+ *
+ *  Update promiscuous / allmulti indicators based on OPMODE
+ *  and filter state.
+ */
+static void dec21143_update_rx_mode(struct dec21143_data *d)
+{
+	int opmode_pr = (d->reg[CSR_OPMODE / 8] & OPMODE_PR) != 0;
+	int opmode_pm = (d->reg[CSR_OPMODE / 8] & OPMODE_PM) != 0;
+
+	debug("[ dec21143 rx mode: opmode_pr = %d                ]\n",
+	      opmode_pr);
+	debug("[ dec21143 rx mode: filter_needs_promiscuous = %d ]\n",
+	      d->filter_needs_promiscuous);
+	debug("[ dec21143 rx mode: opmode_pm = %d                ]\n",
+	      opmode_pm);
+	debug("[ dec21143 rx mode: filter_saturated = %d         ]\n",
+	      d->hash_filter_saturated);
+
+	d->promiscuous = opmode_pr;
+	d->nic.promiscuous_mode =
+	    d->promiscuous || d->filter_needs_promiscuous;
+
+	d->allmulti = opmode_pm || d->hash_filter_saturated;
+}
+
+
+/*
+ *  dec21143_rx():
+ *
+ *  Receive a packet. (If there is no current packet, then check for newly
+ *  arrived ones. If the current packet couldn't be fully transfered the
+ *  last time, then continue on that packet.)
+ */
+int dec21143_rx(struct cpu *cpu, struct dec21143_data *d)
+{
+	uint32_t addr = d->cur_rx_addr, bufaddr;
+	unsigned char descr[16];
+	uint32_t rdes0, rdes1, rdes2, rdes3;
+	int bufsize, buf1_size, buf2_size, i, writeback_len = 4, to_xfer;
+
+	/*  No current packet? Then check for new ones.  */
+	while (d->cur_rx_buf == NULL) {
+		/*  Nothing available? Then abort.  */
+		if (!net_ethernet_rx_avail(d->nic.net, &d->nic))
+			return 0;
+
+		/*  Get the next packet into our buffer:  */
+		net_ethernet_rx(d->nic.net, &d->nic,
+		    &d->cur_rx_buf, &d->cur_rx_buf_len);
+
+		if (dec21143_rx_drop_packet(d->nic.net, d))
+			continue;
+
+		/*  Append a 4 byte CRC:  */
+		d->cur_rx_buf_len += 4;
+		CHECK_ALLOCATION(d->cur_rx_buf = (unsigned char *) realloc(d->cur_rx_buf,
+		    d->cur_rx_buf_len));
+
+		/*  Well... the CRC is just zeros, for now.  */
+		memset(d->cur_rx_buf + d->cur_rx_buf_len - 4, 0, 4);
+
+		d->cur_rx_offset = 0;
+	}
+
+	/*  fatal("{ dec21143_rx: base = 0x%08x }\n", (int)addr);  */
+
+	if (!cpu->memory_rw(cpu, cpu->mem, dma_to_phys(d, addr),
+	    descr, sizeof(uint32_t), MEM_READ, PHYSICAL | NO_EXCEPTIONS)) {
+		fatal("[ dec21143_rx: memory_rw failed! ]\n");
+		return 0;
+	}
+
+	rdes0 = load_le32(&descr[0]);
+
+	/*  Only use descriptors owned by the 21143:  */
+	if (!(rdes0 & TDSTAT_OWN)) {
+		d->reg[CSR_STATUS/8] |= STATUS_RU;
+		return 0;
+	}
+
+	if (!cpu->memory_rw(cpu, cpu->mem,
+	    dma_to_phys(d, addr + sizeof(uint32_t)),
+	    descr + sizeof(uint32_t), sizeof(uint32_t) * 3, MEM_READ,
+	    PHYSICAL | NO_EXCEPTIONS)) {
+		fatal("[ dec21143_rx: memory_rw failed! ]\n");
+		return 0;
+	}
+
+	rdes1 = load_le32(&descr[4]);
+	rdes2 = load_le32(&descr[8]);
+	rdes3 = load_le32(&descr[12]);
+
+	buf1_size = rdes1 & TDCTL_SIZE1;
+	buf2_size = (rdes1 & TDCTL_SIZE2) >> TDCTL_SIZE2_SHIFT;
+	bufaddr = buf1_size? rdes2 : rdes3;
+	bufsize = buf1_size? buf1_size : buf2_size;
+
+	d->reg[CSR_STATUS/8] &= ~STATUS_RS;
+
+	if (rdes1 & TDCTL_ER)
+		d->cur_rx_addr = d->reg[CSR_RXLIST / 8];
+	else {
+		if (rdes1 & TDCTL_CH)
+			d->cur_rx_addr = rdes3;
+		else
+			d->cur_rx_addr += 4 * sizeof(uint32_t);
+	}
+
+	debug("{ RX (%llx): 0x%08x 0x%08x 0x%x 0x%x: buf %i bytes at 0x%x }\n",
+	    (long long)addr, rdes0, rdes1, rdes2, rdes3, bufsize, (int)bufaddr);
+
+	/*  Turn off all status bits, and give up ownership:  */
+	rdes0 = 0x00000000;
+
+	to_xfer = d->cur_rx_buf_len - d->cur_rx_offset;
+	if (to_xfer > bufsize)
+		to_xfer = bufsize;
+
+	/*  DMA bytes from the packet into emulated physical memory:  */
+	for (i=0; i<to_xfer; i++) {
+		cpu->memory_rw(cpu, cpu->mem, dma_to_phys(d, bufaddr + i),
+		    d->cur_rx_buf + d->cur_rx_offset + i, 1, MEM_WRITE,
+		    PHYSICAL | NO_EXCEPTIONS);
+		/*  fatal(" %02x", d->cur_rx_buf[d->cur_rx_offset + i]);  */
+	}
+
+	/*  Was this the first buffer in a frame? Then mark it as such.  */
+	if (d->cur_rx_offset == 0)
+		rdes0 |= TDSTAT_Rx_FS;
+
+	d->cur_rx_offset += to_xfer;
+
+	/*  Frame completed?  */
+	if (d->cur_rx_offset >= d->cur_rx_buf_len) {
+		rdes0 |= TDSTAT_Rx_LS;
+
+		/*  Set the frame length:  */
+		rdes0 |= (d->cur_rx_buf_len << 16) & TDSTAT_Rx_FL;
+
+		/*  Frame too long? (1518 is max ethernet frame length)  */
+		if (d->cur_rx_buf_len > 1518)
+			rdes0 |= TDSTAT_Rx_TL;
+
+		/*  Cause a receiver interrupt:  */
+		d->reg[CSR_STATUS/8] |= STATUS_RI;
+
+		free(d->cur_rx_buf);
+		d->cur_rx_buf = NULL;
+		d->cur_rx_buf_len = 0;
+	}
+
+	/*  Descriptor writeback:  */
+	store_le32(&descr[0], rdes0);
+	if (writeback_len > 1) {
+		store_le32(&descr[4], rdes1);
+		store_le32(&descr[8], rdes2);
+		store_le32(&descr[12], rdes3);
+	}
+
+	if (!cpu->memory_rw(cpu, cpu->mem, dma_to_phys(d, addr), descr,
+	    sizeof(uint32_t) * writeback_len, MEM_WRITE,
+	    PHYSICAL | NO_EXCEPTIONS)) {
+		fatal("[ dec21143_rx: memory_rw failed! ]\n");
+		return 0;
+	}
+
+	return 1;
+}
+
+
+/*
+ *  dec21143_setup_copy_enaddr():
+ *
+ *  Copy an Ethernet address out of the setup packet.
+ */
+static void dec21143_setup_copy_enaddr(uint8_t *enaddr,
+	const uint32_t *setup_packet)
+{
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		enaddr[i*2    ] = (uint8_t)setup_packet[i];
+		enaddr[i*2 + 1] = (uint8_t)(setup_packet[i] >> 8);
+	}
+}
+
+
+/*
+ *  dec21143_setup_perfect():
+ *
+ *  Setup perfect filtering mode.
+ */
+static void dec21143_setup_perfect(struct dec21143_data *d,
+	const uint32_t *setup_packet)
+{
+	int i;
+
+	for (i = 0; i < TULIP_MAXADDRS; i++) {
+		dec21143_setup_copy_enaddr(&d->perfect_filter[i * 6],
+		    &setup_packet[i * 3]);
+		debug("dec21143 PERFECT[%d] %02x:%02x:%02x:%02x:%02x:%02x\n",
+		    i,
+		    d->perfect_filter[i*6 + 0],
+		    d->perfect_filter[i*6 + 1],
+		    d->perfect_filter[i*6 + 2],
+		    d->perfect_filter[i*6 + 3],
+		    d->perfect_filter[i*6 + 4],
+		    d->perfect_filter[i*6 + 5]);
+	}
+
+	d->drop_packet = dec21143_drop_packet_perfect;
+}
+
+
+/*
+ *  dec21143_setup_hashperfect():
+ *
+ *  Setup hash-perfect filtering mode.
+ */
+static void dec21143_setup_hashperfect(struct dec21143_data *d,
+	const uint32_t *setup_packet)
+{
+	int i;
+
+	debug("dec21143 HASHPERFECT:");
+	for (i = 0; i < MCHASH_NWORDS; i++) {
+		if ((i % 8) == 0)
+			debug("\n\t");
+		debug(" %04x", setup_packet[i]);
+		d->hash_filter[i] = setup_packet[i];
+		d->hash_filter_saturated |= (d->hash_filter[i] == 0xffff);
+	}
+	debug("\n");
+
+	dec21143_setup_copy_enaddr(d->nic.mac_address, &setup_packet[39]);
+	debug("dec21143 HASHPERFECT %02x:%02x:%02x:%02x:%02x:%02x\n",
+	      d->nic.mac_address[0],
+	      d->nic.mac_address[1],
+	      d->nic.mac_address[2],
+	      d->nic.mac_address[3],
+	      d->nic.mac_address[4],
+	      d->nic.mac_address[5]);
+
+	d->filter_needs_promiscuous = 0;
+	d->drop_packet = dec21143_drop_packet_hashperfect;
+}
+
+
+/*
+ *  dec21143_setup_inverse():
+ *
+ *  Setup inverse filtering mode.
+ */
+static void dec21143_setup_inverse(struct dec21143_data *d,
+	const uint32_t *setup_packet)
+{
+	dec21143_setup_perfect(d, setup_packet);
+	debug("dec21143 INVERSE ^^^^\n");
+	d->drop_packet = dec21143_drop_packet_inverse;
+}
+
+
+/*
+ *  dec21143_setup_hashonly():
+ *
+ *  Setup hash-only filtering mode.
+ */
+static void dec21143_setup_hashonly(struct dec21143_data *d,
+	const uint32_t *setup_packet)
+{
+	int i;
+
+	debug("dec21143 HASHONLY:");
+	for (i = 0; i < MCHASH_NWORDS; i++) {
+		if ((i % 8) == 0)
+			fatal("\n\t");
+		debug(" %04x", setup_packet[i]);
+		d->hash_filter[i] = setup_packet[i];
+		d->hash_filter_saturated |= (d->hash_filter[i] == 0xffff);
+	}
+	debug("\n");
+
+	d->drop_packet = dec21143_drop_packet_hashonly;
+}
+
+
+/*
+ *  dec21143_process_setup_packet():
+ *
+ *  Process the address filter setup packet.
+ */
+static void dec21143_process_setup_packet(struct cpu *cpu,
+	struct dec21143_data *d, uint32_t tdctl, uint32_t bufaddr)
+{
+	uint32_t setup_packet[TULIP_SETUP_PACKET_LEN / sizeof(uint32_t)];
+	uint8_t *cp = (uint8_t *)setup_packet;
+	uint32_t tmp;
+	int i;
+
+	if (!cpu->memory_rw(cpu, cpu->mem, dma_to_phys(d, bufaddr), cp,
+	    TULIP_SETUP_PACKET_LEN, MEM_READ, PHYSICAL | NO_EXCEPTIONS)) {
+		fatal("[ dec21143_process_setup_packet: memory_rw failed! ]\n");
+		return;
+	}
+
+	/* Ensure host order of each word. */
+	for (i = 0; i < TULIP_SETUP_PACKET_LEN; i += sizeof(uint32_t)) {
+		tmp = load_le32(&cp[i]);
+		setup_packet[i / sizeof(uint32_t)] = tmp;
+	}
+
+	/* Defaults. */
+	d->hash_filter_saturated = 0;
+	d->filter_needs_promiscuous = 1;
+
+	d->reg[CSR_OPMODE / 8] &= ~(OPMODE_HP | OPMODE_HO | OPMODE_IF);
+
+	switch (tdctl & TDCTL_Tx_FT_MASK) {
+	case TDCTL_Tx_FT_PERFECT:
+		dec21143_setup_perfect(d, setup_packet);
+		break;
+
+	case TDCTL_Tx_FT_HASH:
+		dec21143_setup_hashperfect(d, setup_packet);
+		d->reg[CSR_OPMODE / 8] |= OPMODE_HP;
+		break;
+
+	case TDCTL_Tx_FT_INVERSE:
+		dec21143_setup_inverse(d, setup_packet);
+		d->reg[CSR_OPMODE / 8] |= OPMODE_IF;
+		break;
+
+	case TDCTL_Tx_FT_HASHONLY:
+		dec21143_setup_hashonly(d, setup_packet);
+		d->reg[CSR_OPMODE / 8] |= OPMODE_HO;
+		break;
+	}
+
+	dec21143_update_rx_mode(d);
+}
+
+
+/*
+ *  dec21143_tx():
+ *
+ *  Transmit a packet, if the guest OS has marked a descriptor as containing
+ *  data to transmit.
+ */
+int dec21143_tx(struct cpu *cpu, struct dec21143_data *d)
+{
+	uint32_t addr = d->cur_tx_addr, bufaddr;
+	unsigned char descr[16];
+	uint32_t tdes0, tdes1, tdes2, tdes3;
+	int bufsize, buf1_size, buf2_size, i;
+
+	if (!cpu->memory_rw(cpu, cpu->mem, dma_to_phys(d, addr), descr,
+	    sizeof(uint32_t), MEM_READ, PHYSICAL | NO_EXCEPTIONS)) {
+		fatal("[ dec21143_tx: memory_rw failed! ]\n");
+		return 0;
+	}
+
+	tdes0 = load_le32(&descr[0]);
+
+	/*  fatal("{ dec21143_tx: base=0x%08x, tdes0=0x%08x }\n",
+	    (int)addr, (int)tdes0);  */
+
+	/*  Only process packets owned by the 21143:  */
+	if (!(tdes0 & TDSTAT_OWN)) {
+		if (d->tx_idling > d->tx_idling_threshold) {
+			d->reg[CSR_STATUS/8] |= STATUS_TU;
+			d->tx_idling = 0;
+		} else
+			d->tx_idling ++;
+		return 0;
+	}
+
+	if (!cpu->memory_rw(cpu, cpu->mem,
+	    dma_to_phys(d, addr + sizeof(uint32_t)),
+	    descr + sizeof(uint32_t), sizeof(uint32_t) * 3, MEM_READ,
+	    PHYSICAL | NO_EXCEPTIONS)) {
+		fatal("[ dec21143_tx: memory_rw failed! ]\n");
+		return 0;
+	}
+
+	tdes1 = load_le32(&descr[4]);
+	tdes2 = load_le32(&descr[8]);
+	tdes3 = load_le32(&descr[12]);
+
+	buf1_size = tdes1 & TDCTL_SIZE1;
+	buf2_size = (tdes1 & TDCTL_SIZE2) >> TDCTL_SIZE2_SHIFT;
+	bufaddr = buf1_size? tdes2 : tdes3;
+	bufsize = buf1_size? buf1_size : buf2_size;
+
+	d->reg[CSR_STATUS/8] &= ~STATUS_TS;
+
+	if (tdes1 & TDCTL_ER)
+		d->cur_tx_addr = d->reg[CSR_TXLIST / 8];
+	else {
+		if (tdes1 & TDCTL_CH)
+			d->cur_tx_addr = tdes3;
+		else
+			d->cur_tx_addr += 4 * sizeof(uint32_t);
+	}
+
+	/*
+	fatal("{ TX (%x): 0x%08x 0x%08x 0x%x 0x%x: buf %i bytes at 0x%x }\n",
+	  addr, tdes0, tdes1, tdes2, tdes3, bufsize, bufaddr);
+	*/
+
+	/*  Assume no error:  */
+	tdes0 &= ~ (TDSTAT_Tx_UF | TDSTAT_Tx_EC | TDSTAT_Tx_LC
+	    | TDSTAT_Tx_NC | TDSTAT_Tx_LO | TDSTAT_Tx_TO | TDSTAT_ES);
+
+	if (tdes1 & TDCTL_Tx_SET) {
+		/*
+		 *  Setup Packet.
+		 */
+		/*  fatal("{ TX: setup packet }\n");  */
+		if (bufsize != TULIP_SETUP_PACKET_LEN)
+			fatal("[ dec21143: setup packet len = %i, should be"
+			    " %d! ]\n", (int)bufsize, TULIP_SETUP_PACKET_LEN);
+		else
+			dec21143_process_setup_packet(cpu, d, tdes1, bufaddr);
+		if (tdes1 & TDCTL_Tx_IC)
+			d->reg[CSR_STATUS/8] |= STATUS_TI;
+		/*  New descriptor values, according to the docs:  */
+		tdes0 = 0x7fffffff; tdes1 = 0xffffffff;
+		tdes2 = 0xffffffff; tdes3 = 0xffffffff;
+	} else {
+		/*
+		 *  Data Packet.
+		 */
+		/*  fatal("{ TX: data packet: ");  */
+		if (tdes1 & TDCTL_Tx_FS) {
+			/*  First segment. Let's allocate a new buffer:  */
+			/*  fatal("new frame }\n");  */
+
+			CHECK_ALLOCATION(d->cur_tx_buf = (unsigned char *) malloc(bufsize));
+			d->cur_tx_buf_len = 0;
+		} else {
+			/*  Not first segment. Increase the length of
+			    the current buffer:  */
+			/*  fatal("continuing last frame }\n");  */
+
+			if (d->cur_tx_buf == NULL)
+				fatal("[ dec21143: WARNING! tx: middle "
+				    "segment, but no first segment?! ]\n");
+
+			CHECK_ALLOCATION(d->cur_tx_buf = (unsigned char *) realloc(d->cur_tx_buf,
+			    d->cur_tx_buf_len + bufsize));
+		}
+
+		/*  "DMA" data from emulated physical memory into the buf:  */
+		for (i=0; i<bufsize; i++) {
+			cpu->memory_rw(cpu, cpu->mem,
+			    dma_to_phys(d, bufaddr + i),
+			    d->cur_tx_buf + d->cur_tx_buf_len + i, 1, MEM_READ,
+			    PHYSICAL | NO_EXCEPTIONS);
+			/*  fatal(" %02x", d->cur_tx_buf[
+			    d->cur_tx_buf_len + i]);  */
+		}
+
+		d->cur_tx_buf_len += bufsize;
+
+		/*  Last segment? Then actually transmit it:  */
+		if (tdes1 & TDCTL_Tx_LS) {
+			/*  fatal("{ TX: data frame complete. }\n");  */
+			if (d->nic.net != NULL) {
+				net_ethernet_tx(d->nic.net, &d->nic,
+				    d->cur_tx_buf, d->cur_tx_buf_len);
+			} else {
+				static int warn = 0;
+				if (!warn)
+					fatal("[ dec21143: WARNING! Not "
+					    "connected to a network! ]\n");
+				warn = 1;
+			}
+
+			free(d->cur_tx_buf);
+			d->cur_tx_buf = NULL;
+			d->cur_tx_buf_len = 0;
+
+			/*  Interrupt, if Tx_IC is set:  */
+			if (tdes1 & TDCTL_Tx_IC)
+				d->reg[CSR_STATUS/8] |= STATUS_TI;
+		}
+
+		/*  We are done with this segment.  */
+		tdes0 &= ~TDSTAT_OWN;
+	}
+
+	/*  Error summary:  */
+	if (tdes0 & (TDSTAT_Tx_UF | TDSTAT_Tx_EC | TDSTAT_Tx_LC
+	    | TDSTAT_Tx_NC | TDSTAT_Tx_LO | TDSTAT_Tx_TO))
+		tdes0 |= TDSTAT_ES;
+
+	/*  Descriptor writeback:  */
+	store_le32(&descr[0], tdes0);
+	store_le32(&descr[4], tdes1);
+	store_le32(&descr[8], tdes2);
+	store_le32(&descr[12], tdes3);
+
+	if (!cpu->memory_rw(cpu, cpu->mem, dma_to_phys(d, addr), descr,
+	    sizeof(uint32_t) * 4, MEM_WRITE, PHYSICAL | NO_EXCEPTIONS)) {
+		fatal("[ dec21143_tx: memory_rw failed! ]\n");
+		return 0;
+	}
+
+	return 1;
+}
+
+
+DEVICE_TICK(dec21143)
+{
+	struct dec21143_data *d = (struct dec21143_data *) extra;
+	int asserted;
+
+	if (d->reg[CSR_OPMODE / 8] & OPMODE_ST)
+		while (dec21143_tx(cpu, d))
+			;
+
+	if (d->reg[CSR_OPMODE / 8] & OPMODE_SR)
+		while (dec21143_rx(cpu, d))
+			;
+
+	/*  Normal and Abnormal interrupt summary:  */
+	d->reg[CSR_STATUS / 8] &= ~(STATUS_NIS | STATUS_AIS);
+	if (d->reg[CSR_STATUS / 8] & 0x00004845)
+		d->reg[CSR_STATUS / 8] |= STATUS_NIS;
+	if (d->reg[CSR_STATUS / 8] & 0x0c0037ba)
+		d->reg[CSR_STATUS / 8] |= STATUS_AIS;
+
+	asserted = d->reg[CSR_STATUS / 8] & d->reg[CSR_INTEN / 8] & 0x0c01ffff;
+
+	if (asserted)
+		INTERRUPT_ASSERT(d->irq);
+	if (!asserted && d->irq_was_asserted)
+		INTERRUPT_DEASSERT(d->irq);
+
+	/*  Remember assertion flag:  */
+	d->irq_was_asserted = asserted;
+}
+
+
+/*
+ *  mii_access():
+ *
+ *  This function handles accesses to the MII. Data streams seem to be of the
+ *  following format:
+ *
+ *      vv---- starting delimiter
+ *  ... 01 xx yyyyy zzzzz a[a] dddddddddddddddd
+ *         ^---- I am starting with mii_bit = 0 here
+ *
+ *  where x = opcode (10 = read, 01 = write)
+ *        y = PHY address
+ *        z = register address
+ *        a = on Reads: ACK bit (returned, should be 0)
+ *            on Writes: _TWO_ dummy bits (10)
+ *        d = 16 bits of data (MSB first)
+ */
+static void mii_access(struct cpu *cpu, struct dec21143_data *d,
+	uint32_t oldreg, uint32_t idata)
+{
+	int obit, ibit = 0;
+	uint16_t tmp;
+
+	/*  Only care about data during clock cycles:  */
+	if (!(idata & MIIROM_MDC))
+		return;
+
+	if (idata & MIIROM_MDC && oldreg & MIIROM_MDC)
+		return;
+
+	/*  fatal("[ mii_access(): 0x%08x ]\n", (int)idata);  */
+
+	if (idata & MIIROM_BR) {
+		fatal("[ mii_access(): MIIROM_BR: TODO ]\n");
+		return;
+	}
+
+	obit = idata & MIIROM_MDO? 1 : 0;
+
+	if (d->mii_state >= MII_STATE_START_WAIT &&
+	    d->mii_state <= MII_STATE_READ_PHYADDR_REGADDR &&
+	    idata & MIIROM_MIIDIR)
+		fatal("[ mii_access(): bad dir? ]\n");
+
+	switch (d->mii_state) {
+
+	case MII_STATE_RESET:
+		/*  Wait for a starting delimiter (0 followed by 1).  */
+		if (obit)
+			return;
+		if (idata & MIIROM_MIIDIR)
+			return;
+		/*  fatal("[ mii_access(): got a 0 delimiter ]\n");  */
+		d->mii_state = MII_STATE_START_WAIT;
+		d->mii_opcode = 0;
+		d->mii_phyaddr = 0;
+		d->mii_regaddr = 0;
+		break;
+
+	case MII_STATE_START_WAIT:
+		/*  Wait for a starting delimiter (0 followed by 1).  */
+		if (!obit)
+			return;
+		if (idata & MIIROM_MIIDIR) {
+			d->mii_state = MII_STATE_RESET;
+			return;
+		}
+		/*  fatal("[ mii_access(): got a 1 delimiter ]\n");  */
+		d->mii_state = MII_STATE_READ_OP;
+		d->mii_bit = 0;
+		break;
+
+	case MII_STATE_READ_OP:
+		if (d->mii_bit == 0) {
+			d->mii_opcode = obit << 1;
+			/*  fatal("[ mii_access(): got first opcode bit "
+			    "(%i) ]\n", obit);  */
+		} else {
+			d->mii_opcode |= obit;
+			/*  fatal("[ mii_access(): got opcode = %i ]\n",
+			    d->mii_opcode);  */
+			d->mii_state = MII_STATE_READ_PHYADDR_REGADDR;
+		}
+		d->mii_bit ++;
+		break;
+
+	case MII_STATE_READ_PHYADDR_REGADDR:
+		/*  fatal("[ mii_access(): got phy/reg addr bit nr %i (%i)"
+		    " ]\n", d->mii_bit - 2, obit);  */
+		if (d->mii_bit <= 6)
+			d->mii_phyaddr |= obit << (6-d->mii_bit);
+		else
+			d->mii_regaddr |= obit << (11-d->mii_bit);
+		d->mii_bit ++;
+		if (d->mii_bit >= 12) {
+			/*  fatal("[ mii_access(): phyaddr=0x%x regaddr=0x"
+			    "%x ]\n", d->mii_phyaddr, d->mii_regaddr);  */
+			d->mii_state = MII_STATE_A;
+		}
+		break;
+
+	case MII_STATE_A:
+		switch (d->mii_opcode) {
+		case MII_COMMAND_WRITE:
+			if (d->mii_bit >= 13)
+				d->mii_state = MII_STATE_D;
+			break;
+		case MII_COMMAND_READ:
+			ibit = 0;
+			d->mii_state = MII_STATE_D;
+			break;
+		default:debug("[ mii_access(): UNIMPLEMENTED MII opcode "
+			    "%i (probably just a bug in GXemul's "
+			    "MII data stream handling) ]\n", d->mii_opcode);
+			d->mii_state = MII_STATE_RESET;
+		}
+		d->mii_bit ++;
+		break;
+
+	case MII_STATE_D:
+		switch (d->mii_opcode) {
+		case MII_COMMAND_WRITE:
+			if (idata & MIIROM_MIIDIR)
+				fatal("[ mii_access(): write: bad dir? ]\n");
+			obit = obit? (0x8000 >> (d->mii_bit - 14)) : 0;
+			tmp = d->mii_phy_reg[(d->mii_phyaddr << 5) +
+			    d->mii_regaddr] | obit;
+			if (d->mii_bit >= 29) {
+				d->mii_state = MII_STATE_IDLE;
+				debug("[ mii_access(): WRITE to phyaddr=0x%x "
+				    "regaddr=0x%x: 0x%04x ]\n", d->mii_phyaddr,
+				    d->mii_regaddr, tmp);
+			}
+			break;
+		case MII_COMMAND_READ:
+			if (!(idata & MIIROM_MIIDIR))
+				break;
+			tmp = d->mii_phy_reg[(d->mii_phyaddr << 5) +
+			    d->mii_regaddr];
+			if (d->mii_bit == 13)
+				debug("[ mii_access(): READ phyaddr=0x%x "
+				    "regaddr=0x%x: 0x%04x ]\n", d->mii_phyaddr,
+				    d->mii_regaddr, tmp);
+			ibit = tmp & (0x8000 >> (d->mii_bit - 13));
+			if (d->mii_bit >= 28)
+				d->mii_state = MII_STATE_IDLE;
+			break;
+		}
+		d->mii_bit ++;
+		break;
+
+	case MII_STATE_IDLE:
+		d->mii_bit ++;
+		if (d->mii_bit >= 31)
+			d->mii_state = MII_STATE_RESET;
+		break;
+	}
+
+	d->reg[CSR_MIIROM / 8] &= ~MIIROM_MDI;
+	if (ibit)
+		d->reg[CSR_MIIROM / 8] |= MIIROM_MDI;
+}
+
+
+/*
+ *  srom_access():
+ *
+ *  This function handles reads from the Ethernet Address ROM. This is not a
+ *  100% correct implementation, as it was reverse-engineered from OpenBSD
+ *  sources; it seems to work with OpenBSD, NetBSD, and Linux, though.
+ *
+ *  Each transfer (if I understood this correctly) is of the following format:
+ *
+ *	1xx yyyyyy zzzzzzzzzzzzzzzz
+ *
+ *  where 1xx    = operation (6 means a Read),
+ *        yyyyyy = ROM address
+ *        zz...z = data
+ *
+ *  y and z are _both_ read and written to at the same time; this enables the
+ *  operating system to sense the number of bits in y (when reading, all y bits
+ *  are 1 except the last one).
+ */
+static void srom_access(struct cpu *cpu, struct dec21143_data *d,
+	uint32_t oldreg, uint32_t idata)
+{
+	int obit, ibit;
+
+	/*  debug("CSR9 WRITE! 0x%08x\n", (int)idata);  */
+
+	/*  New selection? Then reset internal state.  */
+	if (idata & MIIROM_SR && !(oldreg & MIIROM_SR)) {
+		d->srom_curbit = 0;
+		d->srom_opcode = 0;
+		d->srom_opcode_has_started = 0;
+		d->srom_addr = 0;
+	}
+
+	/*  Only care about data during clock cycles:  */
+	if (!(idata & MIIROM_SROMSK))
+		return;
+
+	obit = 0;
+	ibit = idata & MIIROM_SROMDI? 1 : 0;
+	/*  debug("CLOCK CYCLE! (bit %i): ", d->srom_curbit);  */
+
+	/*
+	 *  Linux sends more zeroes before starting the actual opcode, than
+	 *  OpenBSD and NetBSD. Hopefully this is correct. (I'm just guessing
+	 *  that all opcodes should start with a 1, perhaps that's not really
+	 *  the case.)
+	 */
+	if (!ibit && !d->srom_opcode_has_started)
+		return;
+
+	if (d->srom_curbit < 3) {
+		d->srom_opcode_has_started = 1;
+		d->srom_opcode <<= 1;
+		d->srom_opcode |= ibit;
+		/*  debug("opcode input '%i'\n", ibit);  */
+	} else {
+		switch (d->srom_opcode) {
+		case TULIP_SROM_OPC_READ:
+			if (d->srom_curbit < ROM_WIDTH + 3) {
+				obit = d->srom_curbit < ROM_WIDTH + 2;
+				d->srom_addr <<= 1;
+				d->srom_addr |= ibit;
+			} else {
+				uint16_t romword = d->srom[d->srom_addr*2]
+				    + (d->srom[d->srom_addr*2+1] << 8);
+				if (d->srom_curbit == ROM_WIDTH + 3)
+					debug("[ dec21143: ROM read from offset"
+					    " 0x%03x: 0x%04x ]\n",
+					    d->srom_addr, romword);
+				obit = romword & (0x8000 >>
+				    (d->srom_curbit - ROM_WIDTH - 3))? 1 : 0;
+			}
+			break;
+		default:fatal("[ dec21243: unimplemented SROM/EEPROM "
+			    "opcode %i ]\n", d->srom_opcode);
+		}
+		d->reg[CSR_MIIROM / 8] &= ~MIIROM_SROMDO;
+		if (obit)
+			d->reg[CSR_MIIROM / 8] |= MIIROM_SROMDO;
+		/*  debug("input '%i', output '%i'\n", ibit, obit);  */
+	}
+
+	d->srom_curbit ++;
+
+	/*
+	 *  Done opcode + addr + data? Then restart. (At least NetBSD does
+	 *  sequential reads without turning selection off and then on.)
+	 */
+	if (d->srom_curbit >= 3 + ROM_WIDTH + 16) {
+		d->srom_curbit = 0;
+		d->srom_opcode = 0;
+		d->srom_opcode_has_started = 0;
+		d->srom_addr = 0;
+	}
+}
+
+
+/*
+ *  dec21143_reset():
+ *
+ *  Set the 21143 registers, SROM, and MII data to reasonable values.
+ */
+static void dec21143_reset(struct cpu *cpu, struct dec21143_data *d)
+{
+
+	if (d->cur_rx_buf != NULL)
+		free(d->cur_rx_buf);
+	if (d->cur_tx_buf != NULL)
+		free(d->cur_tx_buf);
+	d->cur_rx_buf = d->cur_tx_buf = NULL;
+
+	memset(d->reg, 0, sizeof(uint32_t) * N_REGS);
+	memset(d->mii_phy_reg, 0, sizeof(d->mii_phy_reg));
+
+	/*  Register values at reset, according to the manual:  */
+	d->reg[CSR_BUSMODE / 8] = 0xfe000000;	/*  csr0   */
+	d->reg[CSR_MIIROM  / 8] = 0xfff483ff;	/*  csr9   */
+	d->reg[CSR_SIACONN / 8] = 0xffff0000;	/*  csr13  */
+	d->reg[CSR_SIATXRX / 8] = 0xffffffff;	/*  csr14  */
+	d->reg[CSR_SIAGEN  / 8] = 0x8ff00000;	/*  csr15  */
+
+	d->tx_idling_threshold = 10;
+	d->cur_rx_addr = d->cur_tx_addr = 0;
+
+	/*  Set the MAC address:  */
+	memcpy(d->nic.mac_address, d->srom + TULIP_ROM_IEEE_NETWORK_ADDRESS, 6);
+
+	/*  MII PHY initial state:  */
+	d->mii_state = MII_STATE_RESET;
+
+	/*  PHY #0:  */
+	d->mii_phy_reg[MII_BMSR] = BMSR_100TXFDX | BMSR_10TFDX |
+	    BMSR_ACOMP | BMSR_ANEG | BMSR_LINK;
+}
+
+
+DEVICE_ACCESS(dec21143)
+{
+	struct dec21143_data *d = (struct dec21143_data *) extra;
+	uint32_t idata = 0, odata = 0;
+	uint32_t oldreg = 0;
+	int regnr = relative_addr >> 3;
+
+	if (writeflag == MEM_WRITE)
+		idata = (uint32_t)memory_readmax64(cpu, data,
+		    len | d->pci_little_endian);
+
+	if ((relative_addr & 7) == 0 && regnr < N_REGS) {
+		if (writeflag == MEM_READ) {
+			odata = d->reg[regnr];
+		} else {
+			oldreg = d->reg[regnr];
+			switch (regnr) {
+			case CSR_STATUS / 8:	/*  Zero-on-write  */
+				d->reg[regnr] &= ~(idata & 0x0c01ffff);
+				break;
+			case CSR_MISSED / 8:	/*  Read only  */
+				break;
+			default:d->reg[regnr] = idata;
+			}
+		}
+	} else
+		fatal("[ dec21143: WARNING! unaligned access (0x%x) ]\n",
+		    (int)relative_addr);
+
+	switch (relative_addr) {
+
+	case CSR_BUSMODE:	/*  csr0  */
+		if (writeflag == MEM_WRITE) {
+			/*  Software reset takes effect immediately.  */
+			if (idata & BUSMODE_SWR) {
+				dec21143_reset(cpu, d);
+				idata &= ~BUSMODE_SWR;
+			}
+		}
+		break;
+
+	case CSR_TXPOLL:	/*  csr1  */
+		if (writeflag == MEM_READ)
+			fatal("[ dec21143: UNIMPLEMENTED READ from "
+			    "txpoll ]\n");
+		d->tx_idling = d->tx_idling_threshold;
+		dev_dec21143_tick(cpu, extra);
+		break;
+
+	case CSR_RXPOLL:	/*  csr2  */
+		if (writeflag == MEM_READ)
+			fatal("[ dec21143: UNIMPLEMENTED READ from "
+			    "rxpoll ]\n");
+		dev_dec21143_tick(cpu, extra);
+		break;
+
+	case CSR_RXLIST:	/*  csr3  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ dec21143: setting RXLIST to 0x%x ]\n",
+			    (int)idata);
+			if (idata & 0x3)
+				fatal("[ dec21143: WARNING! RXLIST not aligned"
+				    "? (0x%llx) ]\n", (long long)idata);
+			idata &= ~0x3;
+			d->cur_rx_addr = idata;
+		}
+		break;
+
+	case CSR_TXLIST:	/*  csr4  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ dec21143: setting TXLIST to 0x%x ]\n",
+			    (int)idata);
+			if (idata & 0x3)
+				fatal("[ dec21143: WARNING! TXLIST not aligned"
+				    "? (0x%llx) ]\n", (long long)idata);
+			idata &= ~0x3;
+			d->cur_tx_addr = idata;
+		}
+		break;
+
+	case CSR_STATUS:	/*  csr5  */
+	case CSR_INTEN:		/*  csr7  */
+		if (writeflag == MEM_WRITE) {
+			/*  Recalculate interrupt assertion.  */
+			dev_dec21143_tick(cpu, extra);
+		}
+		break;
+
+	case CSR_OPMODE:	/*  csr6:  */
+		if (writeflag == MEM_WRITE) {
+			if (idata & 0x02000000) {
+				/*  A must-be-one bit.  */
+				idata &= ~0x02000000;
+			}
+			if (idata & OPMODE_ST) {
+				idata &= ~OPMODE_ST;
+			} else {
+				/*  Turned off TX? Then idle:  */
+				d->reg[CSR_STATUS/8] |= STATUS_TPS;
+			}
+			if (idata & OPMODE_SR) {
+				idata &= ~OPMODE_SR;
+			} else {
+				/*  Turned off RX? Then go to stopped state:  */
+				d->reg[CSR_STATUS/8] &= ~STATUS_RS;
+			}
+			/*  Maintain r/o filter mode bits:  */
+			d->reg[CSR_OPMODE/8] &=
+			    ~(OPMODE_HP | OPMODE_HO | OPMODE_IF);
+			d->reg[CSR_OPMODE/8] |= oldreg &
+			    (OPMODE_HP | OPMODE_HO | OPMODE_IF);
+			idata &= ~(OPMODE_HBD | OPMODE_SCR | OPMODE_PCS
+			    | OPMODE_PS | OPMODE_SF | OPMODE_TTM | OPMODE_FD
+			    | OPMODE_IF | OPMODE_HO | OPMODE_HP | OPMODE_PR
+			    | OPMODE_PM);
+			if (idata & OPMODE_PNIC_IT) {
+				idata &= ~OPMODE_PNIC_IT;
+				d->tx_idling = d->tx_idling_threshold;
+			}
+			if (idata != 0) {
+				fatal("[ dec21143: UNIMPLEMENTED OPMODE bits"
+				    ": 0x%08x ]\n", (int)idata);
+			}
+			dec21143_update_rx_mode(d);
+			dev_dec21143_tick(cpu, extra);
+		}
+		break;
+
+	case CSR_MISSED:	/*  csr8  */
+		break;
+
+	case CSR_MIIROM:	/*  csr9  */
+		if (writeflag == MEM_WRITE) {
+			if (idata & MIIROM_MDC)
+				mii_access(cpu, d, oldreg, idata);
+			else
+				srom_access(cpu, d, oldreg, idata);
+		}
+		break;
+
+	case CSR_SIASTAT:	/*  csr12  */
+		/*  Auto-negotiation status = Good.  */
+		odata = SIASTAT_ANS_FLPGOOD;
+		break;
+
+	case CSR_SIATXRX:	/*  csr14  */
+		/*  Auto-negotiation Enabled  */
+		odata = SIATXRX_ANE;
+		break;
+
+	case CSR_SIACONN:	/*  csr13  */
+	case CSR_SIAGEN:	/*  csr15  */
+		/*  Don't print warnings for these, for now.  */
+		break;
+
+	default:if (writeflag == MEM_READ)
+			fatal("[ dec21143: read from unimplemented 0x%02x ]\n",
+			    (int)relative_addr);
+		else
+			fatal("[ dec21143: write to unimplemented 0x%02x: "
+			    "0x%02x ]\n", (int)relative_addr, (int)idata);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len | d->pci_little_endian, odata);
+
+	return 1;
+}
+
+
+DEVINIT(dec21143)
+{
+	struct dec21143_data *d;
+	char name2[100];
+	int leaf;
+
+	CHECK_ALLOCATION(d = (struct dec21143_data *) malloc(sizeof(struct dec21143_data)));
+	memset(d, 0, sizeof(struct dec21143_data));
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+	d->pci_little_endian = devinit->pci_little_endian;
+
+	/* XXX XXX XXX */
+	switch (devinit->machine->machine_type) {
+	/*
+	 * Footbridge systems -- this is actually configurable by
+	 * system software, but this is the window setting that
+	 * NetBSD uses.
+	 */
+	case MACHINE_CATS:
+	case MACHINE_NETWINDER:
+		d->xxx_dma_to_phys_mask = ~0x20000000;
+		break;
+
+	/*
+	 * V3 Semi PCI bus controller -- this is actually configurable
+	 * by system sofware, but this is the value previously hard-coded
+	 * for all platforms that did not work on Footbridge systems.
+	 */
+	case MACHINE_ALGOR:
+		/* FALLTHROUGH */
+
+	/* Other known users of dc21143 that came along for the ride. */
+	case MACHINE_COBALT:
+	case MACHINE_PMPPC:
+	case MACHINE_PREP:
+	case MACHINE_MACPPC:
+	case MACHINE_MVMEPPC:
+		d->xxx_dma_to_phys_mask = 0x7fffffff;
+		break;
+
+	default:
+		fatal("[ dec21143: default DMA mask for unhandled machine %d\n",
+		      devinit->machine->machine_type);
+		d->xxx_dma_to_phys_mask = 0xffffffff;
+	}
+
+	memset(d->srom, 0, sizeof(d->srom));
+
+	/*  Version (= 1) and Chip count (= 1):  */
+	d->srom[TULIP_ROM_SROM_FORMAT_VERION] = 1;
+	d->srom[TULIP_ROM_CHIP_COUNT] = 1;
+
+	leaf = 30;
+	d->srom[TULIP_ROM_CHIPn_DEVICE_NUMBER(0)] = 0;
+	d->srom[TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(0)] = leaf & 255;
+	d->srom[TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(0)+1] = leaf >> 8;
+
+	d->srom[leaf+TULIP_ROM_IL_SELECT_CONN_TYPE] = 0; /*  Not used?  */
+	d->srom[leaf+TULIP_ROM_IL_MEDIA_COUNT] = 2;
+	leaf += TULIP_ROM_IL_MEDIAn_BLOCK_BASE;
+
+	d->srom[leaf] = 7;	/*  descriptor length  */
+	d->srom[leaf+1] = TULIP_ROM_MB_21142_SIA;
+	d->srom[leaf+2] = TULIP_ROM_MB_MEDIA_100TX;
+	/*  here comes 4 bytes of GPIO control/data settings  */
+	leaf += d->srom[leaf];
+
+	d->srom[leaf] = 15;	/*  descriptor length  */
+	d->srom[leaf+1] = TULIP_ROM_MB_21142_MII;
+	d->srom[leaf+2] = 0;	/*  PHY nr  */
+	d->srom[leaf+3] = 0;	/*  len of select sequence  */
+	d->srom[leaf+4] = 0;	/*  len of reset sequence  */
+	/*  5,6, 7,8, 9,10, 11,12, 13,14 = unused by GXemul  */
+	leaf += d->srom[leaf];
+
+	net_generate_unique_mac(devinit->machine, d->nic.mac_address);
+	memcpy(d->srom + TULIP_ROM_IEEE_NETWORK_ADDRESS, d->nic.mac_address, 6);
+	net_add_nic(devinit->machine->emul->net, &d->nic);
+
+	dec21143_reset(devinit->machine->cpus[0], d);
+
+	snprintf(name2, sizeof(name2), "%s [%02x:%02x:%02x:%02x:%02x:%02x]",
+	    devinit->name, d->nic.mac_address[0], d->nic.mac_address[1],
+	    d->nic.mac_address[2], d->nic.mac_address[3],
+	    d->nic.mac_address[4], d->nic.mac_address[5]);
+
+	memory_device_register(devinit->machine->memory, name2,
+	    devinit->addr, 0x100, dev_dec21143_access, d, DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(devinit->machine,
+	    dev_dec21143_tick, d, DEC21143_TICK_SHIFT);
+
+	/*
+	 *  NetBSD/cats uses memory accesses, OpenBSD/cats uses I/O registers.
+	 *  Let's make a mirror from the memory range to the I/O range:
+	 */
+	dev_ram_init(devinit->machine, devinit->addr2, 0x100, DEV_RAM_MIRROR
+	    | DEV_RAM_MIGHT_POINT_TO_DEVICES, devinit->addr, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_dec21143.cc gxemul-0.7.0+dfsg/src/devices/dev_dec21143.cc
--- gxemul-0.6.2/src/devices/dev_dec21143.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dec21143.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1011 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: DEC 21143 "Tulip" ethernet controller
- *
- *  Implemented from Intel document 278074-001 ("21143 PC/CardBus 10/100Mb/s
- *  Ethernet LAN Controller") and by reverse-engineering OpenBSD and NetBSD
- *  sources.
- *
- *  This device emulates several sub-components:
- *
- *	21143:	This is the actual ethernet controller.
- *
- *	MII:	The "physical" network interface.
- *
- *	SROM:	A ROM area containing setting such as which MAC address to
- *		use, and info about the MII.
- *
- *
- *  TODO:
- *	o)  Handle _writes_ to MII registers.
- *	o)  Make it work with modern Linux kernels (as a guest OS).
- *	o)  Endianness for descriptors? If necessary.
- *	o)  Actually handle the "Setup" packet.
- *	o)  MAC filtering on incoming packets.
- *	o)  Don't hardcode as many values.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "emul.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "net.h"
-
-#include "thirdparty/mii.h"
-#include "thirdparty/tulipreg.h"
-
-
-/*  #define debug fatal  */
-
-#define	DEC21143_TICK_SHIFT		16
-
-#define	N_REGS			32
-#define	ROM_WIDTH		6
-
-struct dec21143_data {
-	struct interrupt irq;
-	int		irq_was_asserted;
-
-	/*  PCI:  */
-	int		pci_little_endian;
-
-	/*  Ethernet address, and a network which we are connected to:  */
-	uint8_t		mac[6];
-	struct net	*net;
-
-	/*  SROM emulation:  */
-	uint8_t		srom[1 << (ROM_WIDTH + 1)];
-	int		srom_curbit;
-	int		srom_opcode;
-	int		srom_opcode_has_started;
-	int		srom_addr;
-
-	/*  MII PHY emulation:  */
-	uint16_t	mii_phy_reg[MII_NPHY * 32];
-	int		mii_state;
-	int		mii_bit;
-	int		mii_opcode;
-	int		mii_phyaddr;
-	int		mii_regaddr;
-
-	/*  21143 registers:  */
-	uint32_t	reg[N_REGS];
-
-	/*  Internal TX state:  */
-	uint64_t	cur_tx_addr;
-	unsigned char	*cur_tx_buf;
-	int		cur_tx_buf_len;
-	int		tx_idling;
-	int		tx_idling_threshold;
-
-	/*  Internal RX state:  */
-	uint64_t	cur_rx_addr;
-	unsigned char	*cur_rx_buf;
-	int		cur_rx_buf_len;
-	int		cur_rx_offset;
-};
-
-
-/*  Internal states during MII data stream decode:  */
-#define	MII_STATE_RESET				0
-#define	MII_STATE_START_WAIT			1
-#define	MII_STATE_READ_OP			2
-#define	MII_STATE_READ_PHYADDR_REGADDR		3
-#define	MII_STATE_A				4
-#define	MII_STATE_D				5
-#define	MII_STATE_IDLE				6
-
-
-/*
- *  dec21143_rx():
- *
- *  Receive a packet. (If there is no current packet, then check for newly
- *  arrived ones. If the current packet couldn't be fully transfered the
- *  last time, then continue on that packet.)
- */
-int dec21143_rx(struct cpu *cpu, struct dec21143_data *d)
-{
-	uint64_t addr = d->cur_rx_addr, bufaddr;
-	unsigned char descr[16];
-	uint32_t rdes0, rdes1, rdes2, rdes3;
-	int bufsize, buf1_size, buf2_size, i, writeback_len = 4, to_xfer;
-
-	/*  No current packet? Then check for new ones.  */
-	if (d->cur_rx_buf == NULL) {
-		/*  Nothing available? Then abort.  */
-		if (!net_ethernet_rx_avail(d->net, d))
-			return 0;
-
-		/*  Get the next packet into our buffer:  */
-		net_ethernet_rx(d->net, d, &d->cur_rx_buf,
-		    &d->cur_rx_buf_len);
-
-		/*  Append a 4 byte CRC:  */
-		d->cur_rx_buf_len += 4;
-		CHECK_ALLOCATION(d->cur_rx_buf = (unsigned char *) realloc(d->cur_rx_buf,
-		    d->cur_rx_buf_len));
-
-		/*  Well... the CRC is just zeros, for now.  */
-		memset(d->cur_rx_buf + d->cur_rx_buf_len - 4, 0, 4);
-
-		d->cur_rx_offset = 0;
-	}
-
-	/*  fatal("{ dec21143_rx: base = 0x%08x }\n", (int)addr);  */
-	addr &= 0x7fffffff;
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, descr, sizeof(uint32_t),
-	    MEM_READ, PHYSICAL | NO_EXCEPTIONS)) {
-		fatal("[ dec21143_rx: memory_rw failed! ]\n");
-		return 0;
-	}
-
-	rdes0 = descr[0] + (descr[1]<<8) + (descr[2]<<16) + (descr[3]<<24);
-
-	/*  Only use descriptors owned by the 21143:  */
-	if (!(rdes0 & TDSTAT_OWN)) {
-		d->reg[CSR_STATUS/8] |= STATUS_RU;
-		return 0;
-	}
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr + sizeof(uint32_t), descr +
-	    sizeof(uint32_t), sizeof(uint32_t) * 3, MEM_READ, PHYSICAL |
-	    NO_EXCEPTIONS)) {
-		fatal("[ dec21143_rx: memory_rw failed! ]\n");
-		return 0;
-	}
-
-	rdes1 = descr[4] + (descr[5]<<8) + (descr[6]<<16) + (descr[7]<<24);
-	rdes2 = descr[8] + (descr[9]<<8) + (descr[10]<<16) + (descr[11]<<24);
-	rdes3 = descr[12] + (descr[13]<<8) + (descr[14]<<16) + (descr[15]<<24);
-
-	buf1_size = rdes1 & TDCTL_SIZE1;
-	buf2_size = (rdes1 & TDCTL_SIZE2) >> TDCTL_SIZE2_SHIFT;
-	bufaddr = buf1_size? rdes2 : rdes3;
-	bufsize = buf1_size? buf1_size : buf2_size;
-
-	d->reg[CSR_STATUS/8] &= ~STATUS_RS;
-
-	if (rdes1 & TDCTL_ER)
-		d->cur_rx_addr = d->reg[CSR_RXLIST / 8];
-	else {
-		if (rdes1 & TDCTL_CH)
-			d->cur_rx_addr = rdes3;
-		else
-			d->cur_rx_addr += 4 * sizeof(uint32_t);
-	}
-
-	debug("{ RX (%llx): 0x%08x 0x%08x 0x%x 0x%x: buf %i bytes at 0x%x }\n",
-	    (long long)addr, rdes0, rdes1, rdes2, rdes3, bufsize, (int)bufaddr);
-	bufaddr &= 0x7fffffff;
-
-	/*  Turn off all status bits, and give up ownership:  */
-	rdes0 = 0x00000000;
-
-	to_xfer = d->cur_rx_buf_len - d->cur_rx_offset;
-	if (to_xfer > bufsize)
-		to_xfer = bufsize;
-
-	/*  DMA bytes from the packet into emulated physical memory:  */
-	for (i=0; i<to_xfer; i++) {
-		cpu->memory_rw(cpu, cpu->mem, bufaddr + i,
-		    d->cur_rx_buf + d->cur_rx_offset + i, 1, MEM_WRITE,
-		    PHYSICAL | NO_EXCEPTIONS);
-		/*  fatal(" %02x", d->cur_rx_buf[d->cur_rx_offset + i]);  */
-	}
-
-	/*  Was this the first buffer in a frame? Then mark it as such.  */
-	if (d->cur_rx_offset == 0)
-		rdes0 |= TDSTAT_Rx_FS;
-
-	d->cur_rx_offset += to_xfer;
-
-	/*  Frame completed?  */
-	if (d->cur_rx_offset >= d->cur_rx_buf_len) {
-		rdes0 |= TDSTAT_Rx_LS;
-
-		/*  Set the frame length:  */
-		rdes0 |= (d->cur_rx_buf_len << 16) & TDSTAT_Rx_FL;
-
-		/*  Frame too long? (1518 is max ethernet frame length)  */
-		if (d->cur_rx_buf_len > 1518)
-			rdes0 |= TDSTAT_Rx_TL;
-
-		/*  Cause a receiver interrupt:  */
-		d->reg[CSR_STATUS/8] |= STATUS_RI;
-
-		free(d->cur_rx_buf);
-		d->cur_rx_buf = NULL;
-		d->cur_rx_buf_len = 0;
-	}
-
-	/*  Descriptor writeback:  */
-	descr[ 0] = rdes0;       descr[ 1] = rdes0 >> 8;
-	descr[ 2] = rdes0 >> 16; descr[ 3] = rdes0 >> 24;
-	if (writeback_len > 1) {
-		descr[ 4] = rdes1;       descr[ 5] = rdes1 >> 8;
-		descr[ 6] = rdes1 >> 16; descr[ 7] = rdes1 >> 24;
-		descr[ 8] = rdes2;       descr[ 9] = rdes2 >> 8;
-		descr[10] = rdes2 >> 16; descr[11] = rdes2 >> 24;
-		descr[12] = rdes3;       descr[13] = rdes3 >> 8;
-		descr[14] = rdes3 >> 16; descr[15] = rdes3 >> 24;
-	}
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, descr, sizeof(uint32_t)
-	    * writeback_len, MEM_WRITE, PHYSICAL | NO_EXCEPTIONS)) {
-		fatal("[ dec21143_rx: memory_rw failed! ]\n");
-		return 0;
-	}
-
-	return 1;
-}
-
-
-/*
- *  dec21143_tx():
- *
- *  Transmit a packet, if the guest OS has marked a descriptor as containing
- *  data to transmit.
- */
-int dec21143_tx(struct cpu *cpu, struct dec21143_data *d)
-{
-	uint64_t addr = d->cur_tx_addr, bufaddr;
-	unsigned char descr[16];
-	uint32_t tdes0, tdes1, tdes2, tdes3;
-	int bufsize, buf1_size, buf2_size, i;
-
-	addr &= 0x7fffffff;
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, descr, sizeof(uint32_t),
-	    MEM_READ, PHYSICAL | NO_EXCEPTIONS)) {
-		fatal("[ dec21143_tx: memory_rw failed! ]\n");
-		return 0;
-	}
-
-	tdes0 = descr[0] + (descr[1]<<8) + (descr[2]<<16) + (descr[3]<<24);
-
-	/*  fatal("{ dec21143_tx: base=0x%08x, tdes0=0x%08x }\n",
-	    (int)addr, (int)tdes0);  */
-
-	/*  Only process packets owned by the 21143:  */
-	if (!(tdes0 & TDSTAT_OWN)) {
-		if (d->tx_idling > d->tx_idling_threshold) {
-			d->reg[CSR_STATUS/8] |= STATUS_TU;
-			d->tx_idling = 0;
-		} else
-			d->tx_idling ++;
-		return 0;
-	}
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr + sizeof(uint32_t), descr +
-	    sizeof(uint32_t), sizeof(uint32_t) * 3, MEM_READ, PHYSICAL |
-	    NO_EXCEPTIONS)) {
-		fatal("[ dec21143_tx: memory_rw failed! ]\n");
-		return 0;
-	}
-
-	tdes1 = descr[4] + (descr[5]<<8) + (descr[6]<<16) + (descr[7]<<24);
-	tdes2 = descr[8] + (descr[9]<<8) + (descr[10]<<16) + (descr[11]<<24);
-	tdes3 = descr[12] + (descr[13]<<8) + (descr[14]<<16) + (descr[15]<<24);
-
-	buf1_size = tdes1 & TDCTL_SIZE1;
-	buf2_size = (tdes1 & TDCTL_SIZE2) >> TDCTL_SIZE2_SHIFT;
-	bufaddr = buf1_size? tdes2 : tdes3;
-	bufsize = buf1_size? buf1_size : buf2_size;
-
-	d->reg[CSR_STATUS/8] &= ~STATUS_TS;
-
-	if (tdes1 & TDCTL_ER)
-		d->cur_tx_addr = d->reg[CSR_TXLIST / 8];
-	else {
-		if (tdes1 & TDCTL_CH)
-			d->cur_tx_addr = tdes3;
-		else
-			d->cur_tx_addr += 4 * sizeof(uint32_t);
-	}
-
-	/*
-	fatal("{ TX (%llx): 0x%08x 0x%08x 0x%x 0x%x: buf %i bytes at 0x%x }\n",
-	  (long long)addr, tdes0, tdes1, tdes2, tdes3, bufsize, (int)bufaddr);
-	*/
-	bufaddr &= 0x7fffffff;
-
-	/*  Assume no error:  */
-	tdes0 &= ~ (TDSTAT_Tx_UF | TDSTAT_Tx_EC | TDSTAT_Tx_LC
-	    | TDSTAT_Tx_NC | TDSTAT_Tx_LO | TDSTAT_Tx_TO | TDSTAT_ES);
-
-	if (tdes1 & TDCTL_Tx_SET) {
-		/*
-		 *  Setup Packet.
-		 *
-		 *  TODO. For now, just ignore it, and pretend it worked.
-		 */
-		/*  fatal("{ TX: setup packet }\n");  */
-		if (bufsize != 192)
-			fatal("[ dec21143: setup packet len = %i, should be"
-			    " 192! ]\n", (int)bufsize);
-		if (tdes1 & TDCTL_Tx_IC)
-			d->reg[CSR_STATUS/8] |= STATUS_TI;
-		/*  New descriptor values, according to the docs:  */
-		tdes0 = 0x7fffffff; tdes1 = 0xffffffff;
-		tdes2 = 0xffffffff; tdes3 = 0xffffffff;
-	} else {
-		/*
-		 *  Data Packet.
-		 */
-		/*  fatal("{ TX: data packet: ");  */
-		if (tdes1 & TDCTL_Tx_FS) {
-			/*  First segment. Let's allocate a new buffer:  */
-			/*  fatal("new frame }\n");  */
-
-			CHECK_ALLOCATION(d->cur_tx_buf = (unsigned char *) malloc(bufsize));
-			d->cur_tx_buf_len = 0;
-		} else {
-			/*  Not first segment. Increase the length of
-			    the current buffer:  */
-			/*  fatal("continuing last frame }\n");  */
-
-			if (d->cur_tx_buf == NULL)
-				fatal("[ dec21143: WARNING! tx: middle "
-				    "segment, but no first segment?! ]\n");
-
-			CHECK_ALLOCATION(d->cur_tx_buf = (unsigned char *) realloc(d->cur_tx_buf,
-			    d->cur_tx_buf_len + bufsize));
-		}
-
-		/*  "DMA" data from emulated physical memory into the buf:  */
-		for (i=0; i<bufsize; i++) {
-			cpu->memory_rw(cpu, cpu->mem, bufaddr + i,
-			    d->cur_tx_buf + d->cur_tx_buf_len + i, 1, MEM_READ,
-			    PHYSICAL | NO_EXCEPTIONS);
-			/*  fatal(" %02x", d->cur_tx_buf[
-			    d->cur_tx_buf_len + i]);  */
-		}
-
-		d->cur_tx_buf_len += bufsize;
-
-		/*  Last segment? Then actually transmit it:  */
-		if (tdes1 & TDCTL_Tx_LS) {
-			/*  fatal("{ TX: data frame complete. }\n");  */
-			if (d->net != NULL) {
-				net_ethernet_tx(d->net, d, d->cur_tx_buf,
-				    d->cur_tx_buf_len);
-			} else {
-				static int warn = 0;
-				if (!warn)
-					fatal("[ dec21143: WARNING! Not "
-					    "connected to a network! ]\n");
-				warn = 1;
-			}
-
-			free(d->cur_tx_buf);
-			d->cur_tx_buf = NULL;
-			d->cur_tx_buf_len = 0;
-
-			/*  Interrupt, if Tx_IC is set:  */
-			if (tdes1 & TDCTL_Tx_IC)
-				d->reg[CSR_STATUS/8] |= STATUS_TI;
-		}
-
-		/*  We are done with this segment.  */
-		tdes0 &= ~TDSTAT_OWN;
-	}
-
-	/*  Error summary:  */
-	if (tdes0 & (TDSTAT_Tx_UF | TDSTAT_Tx_EC | TDSTAT_Tx_LC
-	    | TDSTAT_Tx_NC | TDSTAT_Tx_LO | TDSTAT_Tx_TO))
-		tdes0 |= TDSTAT_ES;
-
-	/*  Descriptor writeback:  */
-	descr[ 0] = tdes0;       descr[ 1] = tdes0 >> 8;
-	descr[ 2] = tdes0 >> 16; descr[ 3] = tdes0 >> 24;
-	descr[ 4] = tdes1;       descr[ 5] = tdes1 >> 8;
-	descr[ 6] = tdes1 >> 16; descr[ 7] = tdes1 >> 24;
-	descr[ 8] = tdes2;       descr[ 9] = tdes2 >> 8;
-	descr[10] = tdes2 >> 16; descr[11] = tdes2 >> 24;
-	descr[12] = tdes3;       descr[13] = tdes3 >> 8;
-	descr[14] = tdes3 >> 16; descr[15] = tdes3 >> 24;
-
-	if (!cpu->memory_rw(cpu, cpu->mem, addr, descr, sizeof(uint32_t)
-	    * 4, MEM_WRITE, PHYSICAL | NO_EXCEPTIONS)) {
-		fatal("[ dec21143_tx: memory_rw failed! ]\n");
-		return 0;
-	}
-
-	return 1;
-}
-
-
-DEVICE_TICK(dec21143)
-{
-	struct dec21143_data *d = (struct dec21143_data *) extra;
-	int asserted;
-
-	if (d->reg[CSR_OPMODE / 8] & OPMODE_ST)
-		while (dec21143_tx(cpu, d))
-			;
-
-	if (d->reg[CSR_OPMODE / 8] & OPMODE_SR)
-		while (dec21143_rx(cpu, d))
-			;
-
-	/*  Normal and Abnormal interrupt summary:  */
-	d->reg[CSR_STATUS / 8] &= ~(STATUS_NIS | STATUS_AIS);
-	if (d->reg[CSR_STATUS / 8] & 0x00004845)
-		d->reg[CSR_STATUS / 8] |= STATUS_NIS;
-	if (d->reg[CSR_STATUS / 8] & 0x0c0037ba)
-		d->reg[CSR_STATUS / 8] |= STATUS_AIS;
-
-	asserted = d->reg[CSR_STATUS / 8] & d->reg[CSR_INTEN / 8] & 0x0c01ffff;
-
-	if (asserted)
-		INTERRUPT_ASSERT(d->irq);
-	if (!asserted && d->irq_was_asserted)
-		INTERRUPT_DEASSERT(d->irq);
-
-	/*  Remember assertion flag:  */
-	d->irq_was_asserted = asserted;
-}
-
-
-/*
- *  mii_access():
- *
- *  This function handles accesses to the MII. Data streams seem to be of the
- *  following format:
- *
- *      vv---- starting delimiter
- *  ... 01 xx yyyyy zzzzz a[a] dddddddddddddddd
- *         ^---- I am starting with mii_bit = 0 here
- *
- *  where x = opcode (10 = read, 01 = write)
- *        y = PHY address
- *        z = register address
- *        a = on Reads: ACK bit (returned, should be 0)
- *            on Writes: _TWO_ dummy bits (10)
- *        d = 16 bits of data (MSB first)
- */
-static void mii_access(struct cpu *cpu, struct dec21143_data *d,
-	uint32_t oldreg, uint32_t idata)
-{
-	int obit, ibit = 0;
-	uint16_t tmp;
-
-	/*  Only care about data during clock cycles:  */
-	if (!(idata & MIIROM_MDC))
-		return;
-
-	if (idata & MIIROM_MDC && oldreg & MIIROM_MDC)
-		return;
-
-	/*  fatal("[ mii_access(): 0x%08x ]\n", (int)idata);  */
-
-	if (idata & MIIROM_BR) {
-		fatal("[ mii_access(): MIIROM_BR: TODO ]\n");
-		return;
-	}
-
-	obit = idata & MIIROM_MDO? 1 : 0;
-
-	if (d->mii_state >= MII_STATE_START_WAIT &&
-	    d->mii_state <= MII_STATE_READ_PHYADDR_REGADDR &&
-	    idata & MIIROM_MIIDIR)
-		fatal("[ mii_access(): bad dir? ]\n");
-
-	switch (d->mii_state) {
-
-	case MII_STATE_RESET:
-		/*  Wait for a starting delimiter (0 followed by 1).  */
-		if (obit)
-			return;
-		if (idata & MIIROM_MIIDIR)
-			return;
-		/*  fatal("[ mii_access(): got a 0 delimiter ]\n");  */
-		d->mii_state = MII_STATE_START_WAIT;
-		d->mii_opcode = 0;
-		d->mii_phyaddr = 0;
-		d->mii_regaddr = 0;
-		break;
-
-	case MII_STATE_START_WAIT:
-		/*  Wait for a starting delimiter (0 followed by 1).  */
-		if (!obit)
-			return;
-		if (idata & MIIROM_MIIDIR) {
-			d->mii_state = MII_STATE_RESET;
-			return;
-		}
-		/*  fatal("[ mii_access(): got a 1 delimiter ]\n");  */
-		d->mii_state = MII_STATE_READ_OP;
-		d->mii_bit = 0;
-		break;
-
-	case MII_STATE_READ_OP:
-		if (d->mii_bit == 0) {
-			d->mii_opcode = obit << 1;
-			/*  fatal("[ mii_access(): got first opcode bit "
-			    "(%i) ]\n", obit);  */
-		} else {
-			d->mii_opcode |= obit;
-			/*  fatal("[ mii_access(): got opcode = %i ]\n",
-			    d->mii_opcode);  */
-			d->mii_state = MII_STATE_READ_PHYADDR_REGADDR;
-		}
-		d->mii_bit ++;
-		break;
-
-	case MII_STATE_READ_PHYADDR_REGADDR:
-		/*  fatal("[ mii_access(): got phy/reg addr bit nr %i (%i)"
-		    " ]\n", d->mii_bit - 2, obit);  */
-		if (d->mii_bit <= 6)
-			d->mii_phyaddr |= obit << (6-d->mii_bit);
-		else
-			d->mii_regaddr |= obit << (11-d->mii_bit);
-		d->mii_bit ++;
-		if (d->mii_bit >= 12) {
-			/*  fatal("[ mii_access(): phyaddr=0x%x regaddr=0x"
-			    "%x ]\n", d->mii_phyaddr, d->mii_regaddr);  */
-			d->mii_state = MII_STATE_A;
-		}
-		break;
-
-	case MII_STATE_A:
-		switch (d->mii_opcode) {
-		case MII_COMMAND_WRITE:
-			if (d->mii_bit >= 13)
-				d->mii_state = MII_STATE_D;
-			break;
-		case MII_COMMAND_READ:
-			ibit = 0;
-			d->mii_state = MII_STATE_D;
-			break;
-		default:debug("[ mii_access(): UNIMPLEMENTED MII opcode "
-			    "%i (probably just a bug in GXemul's "
-			    "MII data stream handling) ]\n", d->mii_opcode);
-			d->mii_state = MII_STATE_RESET;
-		}
-		d->mii_bit ++;
-		break;
-
-	case MII_STATE_D:
-		switch (d->mii_opcode) {
-		case MII_COMMAND_WRITE:
-			if (idata & MIIROM_MIIDIR)
-				fatal("[ mii_access(): write: bad dir? ]\n");
-			obit = obit? (0x8000 >> (d->mii_bit - 14)) : 0;
-			tmp = d->mii_phy_reg[(d->mii_phyaddr << 5) +
-			    d->mii_regaddr] | obit;
-			if (d->mii_bit >= 29) {
-				d->mii_state = MII_STATE_IDLE;
-				debug("[ mii_access(): WRITE to phyaddr=0x%x "
-				    "regaddr=0x%x: 0x%04x ]\n", d->mii_phyaddr,
-				    d->mii_regaddr, tmp);
-			}
-			break;
-		case MII_COMMAND_READ:
-			if (!(idata & MIIROM_MIIDIR))
-				break;
-			tmp = d->mii_phy_reg[(d->mii_phyaddr << 5) +
-			    d->mii_regaddr];
-			if (d->mii_bit == 13)
-				debug("[ mii_access(): READ phyaddr=0x%x "
-				    "regaddr=0x%x: 0x%04x ]\n", d->mii_phyaddr,
-				    d->mii_regaddr, tmp);
-			ibit = tmp & (0x8000 >> (d->mii_bit - 13));
-			if (d->mii_bit >= 28)
-				d->mii_state = MII_STATE_IDLE;
-			break;
-		}
-		d->mii_bit ++;
-		break;
-
-	case MII_STATE_IDLE:
-		d->mii_bit ++;
-		if (d->mii_bit >= 31)
-			d->mii_state = MII_STATE_RESET;
-		break;
-	}
-
-	d->reg[CSR_MIIROM / 8] &= ~MIIROM_MDI;
-	if (ibit)
-		d->reg[CSR_MIIROM / 8] |= MIIROM_MDI;
-}
-
-
-/*
- *  srom_access():
- *
- *  This function handles reads from the Ethernet Address ROM. This is not a
- *  100% correct implementation, as it was reverse-engineered from OpenBSD
- *  sources; it seems to work with OpenBSD, NetBSD, and Linux, though.
- *
- *  Each transfer (if I understood this correctly) is of the following format:
- *
- *	1xx yyyyyy zzzzzzzzzzzzzzzz
- *
- *  where 1xx    = operation (6 means a Read),
- *        yyyyyy = ROM address
- *        zz...z = data
- *
- *  y and z are _both_ read and written to at the same time; this enables the
- *  operating system to sense the number of bits in y (when reading, all y bits
- *  are 1 except the last one).
- */
-static void srom_access(struct cpu *cpu, struct dec21143_data *d,
-	uint32_t oldreg, uint32_t idata)
-{
-	int obit, ibit;
-
-	/*  debug("CSR9 WRITE! 0x%08x\n", (int)idata);  */
-
-	/*  New selection? Then reset internal state.  */
-	if (idata & MIIROM_SR && !(oldreg & MIIROM_SR)) {
-		d->srom_curbit = 0;
-		d->srom_opcode = 0;
-		d->srom_opcode_has_started = 0;
-		d->srom_addr = 0;
-	}
-
-	/*  Only care about data during clock cycles:  */
-	if (!(idata & MIIROM_SROMSK))
-		return;
-
-	obit = 0;
-	ibit = idata & MIIROM_SROMDI? 1 : 0;
-	/*  debug("CLOCK CYCLE! (bit %i): ", d->srom_curbit);  */
-
-	/*
-	 *  Linux sends more zeroes before starting the actual opcode, than
-	 *  OpenBSD and NetBSD. Hopefully this is correct. (I'm just guessing
-	 *  that all opcodes should start with a 1, perhaps that's not really
-	 *  the case.)
-	 */
-	if (!ibit && !d->srom_opcode_has_started)
-		return;
-
-	if (d->srom_curbit < 3) {
-		d->srom_opcode_has_started = 1;
-		d->srom_opcode <<= 1;
-		d->srom_opcode |= ibit;
-		/*  debug("opcode input '%i'\n", ibit);  */
-	} else {
-		switch (d->srom_opcode) {
-		case TULIP_SROM_OPC_READ:
-			if (d->srom_curbit < ROM_WIDTH + 3) {
-				obit = d->srom_curbit < ROM_WIDTH + 2;
-				d->srom_addr <<= 1;
-				d->srom_addr |= ibit;
-			} else {
-				uint16_t romword = d->srom[d->srom_addr*2]
-				    + (d->srom[d->srom_addr*2+1] << 8);
-				if (d->srom_curbit == ROM_WIDTH + 3)
-					debug("[ dec21143: ROM read from offset"
-					    " 0x%03x: 0x%04x ]\n",
-					    d->srom_addr, romword);
-				obit = romword & (0x8000 >>
-				    (d->srom_curbit - ROM_WIDTH - 3))? 1 : 0;
-			}
-			break;
-		default:fatal("[ dec21243: unimplemented SROM/EEPROM "
-			    "opcode %i ]\n", d->srom_opcode);
-		}
-		d->reg[CSR_MIIROM / 8] &= ~MIIROM_SROMDO;
-		if (obit)
-			d->reg[CSR_MIIROM / 8] |= MIIROM_SROMDO;
-		/*  debug("input '%i', output '%i'\n", ibit, obit);  */
-	}
-
-	d->srom_curbit ++;
-
-	/*
-	 *  Done opcode + addr + data? Then restart. (At least NetBSD does
-	 *  sequential reads without turning selection off and then on.)
-	 */
-	if (d->srom_curbit >= 3 + ROM_WIDTH + 16) {
-		d->srom_curbit = 0;
-		d->srom_opcode = 0;
-		d->srom_opcode_has_started = 0;
-		d->srom_addr = 0;
-	}
-}
-
-
-/*
- *  dec21143_reset():
- *
- *  Set the 21143 registers, SROM, and MII data to reasonable values.
- */
-static void dec21143_reset(struct cpu *cpu, struct dec21143_data *d)
-{
-	int leaf;
-
-	if (d->cur_rx_buf != NULL)
-		free(d->cur_rx_buf);
-	if (d->cur_tx_buf != NULL)
-		free(d->cur_tx_buf);
-	d->cur_rx_buf = d->cur_tx_buf = NULL;
-
-	memset(d->reg, 0, sizeof(uint32_t) * N_REGS);
-	memset(d->srom, 0, sizeof(d->srom));
-	memset(d->mii_phy_reg, 0, sizeof(d->mii_phy_reg));
-
-	/*  Register values at reset, according to the manual:  */
-	d->reg[CSR_BUSMODE / 8] = 0xfe000000;	/*  csr0   */
-	d->reg[CSR_MIIROM  / 8] = 0xfff483ff;	/*  csr9   */
-	d->reg[CSR_SIACONN / 8] = 0xffff0000;	/*  csr13  */
-	d->reg[CSR_SIATXRX / 8] = 0xffffffff;	/*  csr14  */
-	d->reg[CSR_SIAGEN  / 8] = 0x8ff00000;	/*  csr15  */
-
-	d->tx_idling_threshold = 10;
-	d->cur_rx_addr = d->cur_tx_addr = 0;
-
-	/*  Version (= 1) and Chip count (= 1):  */
-	d->srom[TULIP_ROM_SROM_FORMAT_VERION] = 1;
-	d->srom[TULIP_ROM_CHIP_COUNT] = 1;
-
-	/*  Set the MAC address:  */
-	memcpy(d->srom + TULIP_ROM_IEEE_NETWORK_ADDRESS, d->mac, 6);
-
-	leaf = 30;
-	d->srom[TULIP_ROM_CHIPn_DEVICE_NUMBER(0)] = 0;
-	d->srom[TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(0)] = leaf & 255;
-	d->srom[TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(0)+1] = leaf >> 8;
-
-	d->srom[leaf+TULIP_ROM_IL_SELECT_CONN_TYPE] = 0; /*  Not used?  */
-	d->srom[leaf+TULIP_ROM_IL_MEDIA_COUNT] = 2;
-	leaf += TULIP_ROM_IL_MEDIAn_BLOCK_BASE;
-
-	d->srom[leaf] = 7;	/*  descriptor length  */
-	d->srom[leaf+1] = TULIP_ROM_MB_21142_SIA;
-	d->srom[leaf+2] = TULIP_ROM_MB_MEDIA_100TX;
-	/*  here comes 4 bytes of GPIO control/data settings  */
-	leaf += d->srom[leaf];
-
-	d->srom[leaf] = 15;	/*  descriptor length  */
-	d->srom[leaf+1] = TULIP_ROM_MB_21142_MII;
-	d->srom[leaf+2] = 0;	/*  PHY nr  */
-	d->srom[leaf+3] = 0;	/*  len of select sequence  */
-	d->srom[leaf+4] = 0;	/*  len of reset sequence  */
-	/*  5,6, 7,8, 9,10, 11,12, 13,14 = unused by GXemul  */
-	leaf += d->srom[leaf];
-
-	/*  MII PHY initial state:  */
-	d->mii_state = MII_STATE_RESET;
-
-	/*  PHY #0:  */
-	d->mii_phy_reg[MII_BMSR] = BMSR_100TXFDX | BMSR_10TFDX |
-	    BMSR_ACOMP | BMSR_ANEG | BMSR_LINK;
-}
-
-
-DEVICE_ACCESS(dec21143)
-{
-	struct dec21143_data *d = (struct dec21143_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	uint32_t oldreg = 0;
-	int regnr = relative_addr >> 3;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len | d->pci_little_endian);
-
-	if ((relative_addr & 7) == 0 && regnr < N_REGS) {
-		if (writeflag == MEM_READ) {
-			odata = d->reg[regnr];
-		} else {
-			oldreg = d->reg[regnr];
-			switch (regnr) {
-			case CSR_STATUS / 8:	/*  Zero-on-write  */
-				d->reg[regnr] &= ~(idata & 0x0c01ffff);
-				break;
-			case CSR_MISSED / 8:	/*  Read only  */
-				break;
-			default:d->reg[regnr] = idata;
-			}
-		}
-	} else
-		fatal("[ dec21143: WARNING! unaligned access (0x%x) ]\n",
-		    (int)relative_addr);
-
-	switch (relative_addr) {
-
-	case CSR_BUSMODE:	/*  csr0  */
-		if (writeflag == MEM_WRITE) {
-			/*  Software reset takes effect immediately.  */
-			if (idata & BUSMODE_SWR) {
-				dec21143_reset(cpu, d);
-				idata &= ~BUSMODE_SWR;
-			}
-		}
-		break;
-
-	case CSR_TXPOLL:	/*  csr1  */
-		if (writeflag == MEM_READ)
-			fatal("[ dec21143: UNIMPLEMENTED READ from "
-			    "txpoll ]\n");
-		d->tx_idling = d->tx_idling_threshold;
-		dev_dec21143_tick(cpu, extra);
-		break;
-
-	case CSR_RXPOLL:	/*  csr2  */
-		if (writeflag == MEM_READ)
-			fatal("[ dec21143: UNIMPLEMENTED READ from "
-			    "rxpoll ]\n");
-		dev_dec21143_tick(cpu, extra);
-		break;
-
-	case CSR_RXLIST:	/*  csr3  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ dec21143: setting RXLIST to 0x%x ]\n",
-			    (int)idata);
-			if (idata & 0x3)
-				fatal("[ dec21143: WARNING! RXLIST not aligned"
-				    "? (0x%llx) ]\n", (long long)idata);
-			idata &= ~0x3;
-			d->cur_rx_addr = idata;
-		}
-		break;
-
-	case CSR_TXLIST:	/*  csr4  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ dec21143: setting TXLIST to 0x%x ]\n",
-			    (int)idata);
-			if (idata & 0x3)
-				fatal("[ dec21143: WARNING! TXLIST not aligned"
-				    "? (0x%llx) ]\n", (long long)idata);
-			idata &= ~0x3;
-			d->cur_tx_addr = idata;
-		}
-		break;
-
-	case CSR_STATUS:	/*  csr5  */
-	case CSR_INTEN:		/*  csr7  */
-		if (writeflag == MEM_WRITE) {
-			/*  Recalculate interrupt assertion.  */
-			dev_dec21143_tick(cpu, extra);
-		}
-		break;
-
-	case CSR_OPMODE:	/*  csr6:  */
-		if (writeflag == MEM_WRITE) {
-			if (idata & 0x02000000) {
-				/*  A must-be-one bit.  */
-				idata &= ~0x02000000;
-			}
-			if (idata & OPMODE_ST) {
-				idata &= ~OPMODE_ST;
-			} else {
-				/*  Turned off TX? Then idle:  */
-				d->reg[CSR_STATUS/8] |= STATUS_TPS;
-			}
-			if (idata & OPMODE_SR) {
-				idata &= ~OPMODE_SR;
-			} else {
-				/*  Turned off RX? Then go to stopped state:  */
-				d->reg[CSR_STATUS/8] &= ~STATUS_RS;
-			}
-			idata &= ~(OPMODE_HBD | OPMODE_SCR | OPMODE_PCS
-			    | OPMODE_PS | OPMODE_SF | OPMODE_TTM | OPMODE_FD);
-			if (idata & OPMODE_PNIC_IT) {
-				idata &= ~OPMODE_PNIC_IT;
-				d->tx_idling = d->tx_idling_threshold;
-			}
-			if (idata != 0) {
-				fatal("[ dec21143: UNIMPLEMENTED OPMODE bits"
-				    ": 0x%08x ]\n", (int)idata);
-			}
-			dev_dec21143_tick(cpu, extra);
-		}
-		break;
-
-	case CSR_MISSED:	/*  csr8  */
-		break;
-
-	case CSR_MIIROM:	/*  csr9  */
-		if (writeflag == MEM_WRITE) {
-			if (idata & MIIROM_MDC)
-				mii_access(cpu, d, oldreg, idata);
-			else
-				srom_access(cpu, d, oldreg, idata);
-		}
-		break;
-
-	case CSR_SIASTAT:	/*  csr12  */
-		/*  Auto-negotiation status = Good.  */
-		odata = SIASTAT_ANS_FLPGOOD;
-		break;
-
-	case CSR_SIATXRX:	/*  csr14  */
-		/*  Auto-negotiation Enabled  */
-		odata = SIATXRX_ANE;
-		break;
-
-	case CSR_SIACONN:	/*  csr13  */
-	case CSR_SIAGEN:	/*  csr15  */
-		/*  Don't print warnings for these, for now.  */
-		break;
-
-	default:if (writeflag == MEM_READ)
-			fatal("[ dec21143: read from unimplemented 0x%02x ]\n",
-			    (int)relative_addr);
-		else
-			fatal("[ dec21143: write to unimplemented 0x%02x: "
-			    "0x%02x ]\n", (int)relative_addr, (int)idata);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len | d->pci_little_endian, odata);
-
-	return 1;
-}
-
-
-DEVINIT(dec21143)
-{
-	struct dec21143_data *d;
-	char name2[100];
-
-	CHECK_ALLOCATION(d = (struct dec21143_data *) malloc(sizeof(struct dec21143_data)));
-	memset(d, 0, sizeof(struct dec21143_data));
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-	d->pci_little_endian = devinit->pci_little_endian;
-
-	net_generate_unique_mac(devinit->machine, d->mac);
-	net_add_nic(devinit->machine->emul->net, d, d->mac);
-	d->net = devinit->machine->emul->net;
-
-	dec21143_reset(devinit->machine->cpus[0], d);
-
-	snprintf(name2, sizeof(name2), "%s [%02x:%02x:%02x:%02x:%02x:%02x]",
-	    devinit->name, d->mac[0], d->mac[1], d->mac[2], d->mac[3],
-	    d->mac[4], d->mac[5]);
-
-	memory_device_register(devinit->machine->memory, name2,
-	    devinit->addr, 0x100, dev_dec21143_access, d, DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(devinit->machine,
-	    dev_dec21143_tick, d, DEC21143_TICK_SHIFT);
-
-	/*
-	 *  NetBSD/cats uses memory accesses, OpenBSD/cats uses I/O registers.
-	 *  Let's make a mirror from the memory range to the I/O range:
-	 */
-	dev_ram_init(devinit->machine, devinit->addr2, 0x100, DEV_RAM_MIRROR
-	    | DEV_RAM_MIGHT_POINT_TO_DEVICES, devinit->addr);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_dec5800.c gxemul-0.7.0+dfsg/src/devices/dev_dec5800.c
--- gxemul-0.6.2/src/devices/dev_dec5800.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dec5800.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,511 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: DECsystem 58x0 devices
+ *
+ *  Emulation of devices found in a DECsystem 58x0, where x is the number
+ *  of CPUs in the system. (The CPU board is called KN5800 by Ultrix.)
+ *
+ *	o)  timers and misc stuff
+ *	o)  BI  (Backplane Interconnect)
+ *	o)  CCA (Console Communication Area)
+ *	o)  XMI (Extended Memory Interconnect)
+ *
+ *  TODO:  This hardware is not very easy to find docs about.
+ *  Perhaps VAX 6000/300 docs?
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define DEV_DEC5800_LENGTH		0x1000		/*  TODO  */
+
+struct dec5800_data {
+	uint32_t	csr;
+	struct interrupt cpu_irq;
+
+	uint32_t	vector_0x50;
+
+	struct interrupt timer_irq;
+};
+
+
+void dec5800_interrupt_assert(struct interrupt *interrupt)
+{
+	struct dec5800_data *d = (struct dec5800_data *) interrupt->extra;
+	d->csr |= (1 << interrupt->line);
+	if (d->csr & 0x10000000)
+		INTERRUPT_ASSERT(d->cpu_irq);
+}
+void dec5800_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct dec5800_data *d = (struct dec5800_data *) interrupt->extra;
+	d->csr &= ~(1 << interrupt->line);
+	if (!(d->csr & 0x10000000))
+		INTERRUPT_DEASSERT(d->cpu_irq);
+}
+
+
+DEVICE_TICK(dec5800)
+{
+	struct dec5800_data *d = (struct dec5800_data *) extra;
+
+	/*  Timer interrupts?  */
+	if (d->csr & 0x8000) {
+		debug("[ dec5800: timer interrupt! ]\n");
+
+		/*  Set timer interrupt pending bit:  */
+		d->csr |= 0x20000000;
+
+		INTERRUPT_ASSERT(d->timer_irq);
+	}
+}
+
+
+DEVICE_ACCESS(dec5800_vectors)
+{
+	uint64_t idata = 0, odata = 0;
+	struct dec5800_data *d = (struct dec5800_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (writeflag == MEM_READ) {
+		/*  TODO  */
+		/*  0xfc = transmit interrupt, 0xf8 = receive interrupt,
+		    0x80 = IPI  */
+		odata = d->vector_0x50;
+/* odata = 0xfc; */
+		debug("[ dec5800_vectors: read from 0x%02x: 0x%02x ]\n",
+		    (int)relative_addr, (int)odata);
+	} else {
+		d->vector_0x50 = idata;
+		debug("[ dec5800_vectors: write to 0x%02x: 0x%02x ]\n",
+		    (int)relative_addr, (int)idata);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(dec5800)
+{
+	uint64_t idata = 0, odata = 0;
+	struct dec5800_data *d = (struct dec5800_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  Lowest 4 bits of csr contain cpu id:  */
+	d->csr = (d->csr & ~0xf) | (cpu->cpu_id & 0xf);
+
+	switch (relative_addr) {
+	case 0x0000:	/*  csr  */
+		if (writeflag == MEM_READ) {
+			odata = d->csr;
+			odata ^= random() & 0x10000;
+			debug("[ dec5800: read from csr: 0x%08x ]\n",
+			    (int)odata);
+		} else {
+			d->csr = idata;
+
+			/*  Ack. timer interrupts:  */
+			d->csr &= ~0x20000000;
+			INTERRUPT_DEASSERT(d->timer_irq);
+
+			debug("[ dec5800: write to csr: 0x%08x ]\n",
+			    (int)idata);
+		}
+		break;
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ dec5800: read from 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			debug("[ dec5800: write to  0x%08lx: 0x%08x ]\n",
+			    (long)relative_addr, (int)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(dec5800)
+{
+	struct dec5800_data *d;
+	char tmpstr[200];
+	int i;
+
+	CHECK_ALLOCATION(d = (struct dec5800_data *) malloc(sizeof(struct dec5800_data)));
+	memset(d, 0, sizeof(struct dec5800_data));
+
+	snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path);
+	INTERRUPT_CONNECT(tmpstr, d->cpu_irq);
+
+	snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
+	INTERRUPT_CONNECT(tmpstr, d->timer_irq);
+
+	/*  Register 32 CSR interrupts, corresponding to bits in the CSR:  */
+	for (i=0; i<32; i++) {
+		char n[200];
+		struct interrupt templ;
+		snprintf(n, sizeof(n), "%s.dec5800.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = dec5800_interrupt_assert;
+		templ.interrupt_deassert = dec5800_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	memory_device_register(devinit->machine->memory, "dec5800",
+	    devinit->addr, DEV_DEC5800_LENGTH, dev_dec5800_access,
+	    d, DM_DEFAULT, NULL);
+	memory_device_register(devinit->machine->memory, "dec5800_vectors",
+	    devinit->addr + 0x30000000, 0x100, dev_dec5800_vectors_access,
+	    d, DM_DEFAULT, NULL);
+	machine_add_tickfunction(devinit->machine, dev_dec5800_tick,
+	    d, 14);
+
+	return 1;
+}
+
+
+/*****************************************************************************/
+
+
+#include "thirdparty/bireg.h"
+
+/*  16 slots, 0x2000 bytes each  */
+#define DEV_DECBI_LENGTH		0x20000
+
+struct decbi_data {
+	int		csr[NNODEBI];
+};
+
+
+DEVICE_ACCESS(decbi)
+{
+	uint64_t idata = 0, odata = 0;
+	int node_nr;
+	struct decbi_data *d = (struct decbi_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	relative_addr += BI_NODESIZE;	/*  HACK  */
+
+	node_nr = relative_addr / BI_NODESIZE;
+	relative_addr &= (BI_NODESIZE - 1);
+
+	/*  TODO:  This "1" here is the max node number in actual use.  */
+	if (node_nr > 1 || node_nr >= NNODEBI)
+		return 0;
+
+	switch (relative_addr) {
+	case BIREG_DTYPE:
+		if (writeflag==MEM_READ) {
+			/*
+			 *  This is a list of the devices in our BI slots:
+			 */
+			switch (node_nr) {
+			case 1:	odata = BIDT_KDB50; break;	/*  Disk  */
+			/*  case 2:	odata = BIDT_DEBNA; break;  */
+				/*  BIDT_DEBNA = Ethernet  */
+			/*  case 3:	odata = BIDT_MS820; break;  */
+				/*  BIDT_MS820 = Memory  */
+			default:
+				/*  No device.  */
+				odata = 0;
+			}
+
+			debug("[ decbi: (node %i) read from BIREG_DTYPE:"
+			    " 0x%x ]\n", node_nr, (int)odata);
+		} else {
+			debug("[ decbi: (node %i) attempt to write to "
+			    "BIREG_DTYPE: 0x%08x ]\n", node_nr, (int)idata);
+		}
+		break;
+	case BIREG_VAXBICSR:
+		if (writeflag==MEM_READ) {
+			odata = (d->csr[node_nr] & ~BICSR_NODEMASK) | node_nr;
+			debug("[ decbi: (node %i) read from BIREG_"
+			    "VAXBICSR: 0x%x ]\n", node_nr, (int)odata);
+		} else {
+			d->csr[node_nr] = idata;
+			debug("[ decbi: (node %i) attempt to write to "
+			    "BIREG_VAXBICSR: 0x%08x ]\n", node_nr, (int)idata);
+		}
+		break;
+	case 0xf4:
+		if (writeflag==MEM_READ) {
+			odata = 0xffff;	/*  ?  */
+			debug("[ decbi: (node %i) read from 0xf4: "
+			    "0x%x ]\n", node_nr, (int)odata);
+		} else {
+			debug("[ decbi: (node %i) attempt to write "
+			    "to 0xf4: 0x%08x ]\n", node_nr, (int)idata);
+		}
+		break;
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ decbi: (node %i) read from unimplemented "
+			    "0x%08lx ]\n", node_nr, (long)relative_addr,
+			    (int)odata);
+		} else {
+			debug("[ decbi: (node %i) write to unimplemented "
+			    "0x%08lx: 0x%08x ]\n", node_nr,
+			    (long)relative_addr, (int)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(decbi)
+{
+	struct decbi_data *d;
+
+	CHECK_ALLOCATION(d = (struct decbi_data *) malloc(sizeof(struct decbi_data)));
+	memset(d, 0, sizeof(struct decbi_data));
+
+	memory_device_register(devinit->machine->memory, "decbi",
+	    devinit->addr + 0x2000, DEV_DECBI_LENGTH - 0x2000,
+	    dev_decbi_access, d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  CCA, "Console Communication Area" for a DEC 5800 SMP system.
+ */
+
+struct deccca_data {
+	int		dummy;
+};
+
+
+DEVICE_ACCESS(deccca)
+{
+	uint64_t idata = 0, odata = 0;
+	/*  struct deccca_data *d = extra;  */
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	case 6:
+	case 7:
+		/*  CCA "ID" bytes? These must be here, or Ultrix complains.  */
+		if (writeflag == MEM_READ)
+			odata = 67;
+		break;
+	case 8:
+		if (writeflag == MEM_READ)
+			odata = cpu->machine->ncpus;
+		break;
+	case 20:
+		if (writeflag == MEM_READ)
+			odata = (1 << cpu->machine->ncpus) - 1;
+			    /*  one bit for each cpu  */
+		break;
+	case 28:
+		if (writeflag == MEM_READ)
+			odata = (1 << cpu->machine->ncpus) - 1;
+			    /*  one bit for each enabled(?) cpu  */
+		break;
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ deccca: read from 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			debug("[ deccca: write to  0x%08lx: 0x%08x ]\n",
+			    (long)relative_addr, (int)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_deccca_init():
+ */
+void dev_deccca_init(struct memory *mem, uint64_t baseaddr)
+{
+	struct deccca_data *d;
+
+	CHECK_ALLOCATION(d = (struct deccca_data *) malloc(sizeof(struct deccca_data)));
+	memset(d, 0, sizeof(struct deccca_data));
+
+	memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH,
+	    dev_deccca_access, d, DM_DEFAULT, NULL);
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  DEC 5800 XMI (this has to do with SMP...)
+ */
+
+#include "thirdparty/xmireg.h"
+
+struct decxmi_data {
+	uint32_t		reg_0xc[NNODEXMI];
+};
+
+
+/*
+ *  dev_decxmi_access():
+ */
+DEVICE_ACCESS(decxmi)
+{
+	uint64_t idata = 0, odata = 0;
+	int node_nr;
+	struct decxmi_data *d = (struct decxmi_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	node_nr = relative_addr / XMI_NODESIZE;
+	relative_addr &= (XMI_NODESIZE - 1);
+
+	if (node_nr >= cpu->machine->ncpus + 1 || node_nr >= NNODEXMI)
+		return 0;
+
+	switch (relative_addr) {
+	case XMI_TYPE:
+		if (writeflag == MEM_READ) {
+			/*
+			 *  The first node is an XMI->BI adapter node, and then
+			 *  there are n CPU nodes.
+			 */
+			odata = XMIDT_ISIS;
+			if (node_nr == 0)
+				odata = XMIDT_DWMBA;
+
+			debug("[ decxmi: (node %i) read from XMI_TYPE: "
+			    "0x%08x ]\n", node_nr, (int)odata);
+		} else
+			debug("[ decxmi: (node %i) write to XMI_TYPE: "
+			    "0x%08x ]\n", node_nr, (int)idata);
+		break;
+	case XMI_BUSERR:
+		if (writeflag == MEM_READ) {
+			odata = 0;
+			debug("[ decxmi: (node %i) read from XMI_BUSERR: "
+			    "0x%08x ]\n", node_nr, (int)odata);
+		} else
+			debug("[ decxmi: (node %i) write to XMI_BUSERR: "
+			    "0x%08x ]\n", node_nr, (int)idata);
+		break;
+	case XMI_FAIL:
+		if (writeflag == MEM_READ) {
+			odata = 0;
+			debug("[ decxmi: (node %i) read from XMI_FAIL: "
+			    "0x%08x ]\n", node_nr, (int)odata);
+		} else
+			debug("[ decxmi: (node %i) write to XMI_FAIL: "
+			    "0x%08x ]\n", node_nr, (int)idata);
+		break;
+	case 0xc:
+		if (writeflag == MEM_READ) {
+			odata = d->reg_0xc[node_nr];
+			debug("[ decxmi: (node %i) read from REG 0xC: "
+			    "0x%08x ]\n", node_nr, (int)odata);
+		} else {
+			d->reg_0xc[node_nr] = idata;
+			debug("[ decxmi: (node %i) write to REG 0xC: "
+			    "0x%08x ]\n", node_nr, (int)idata);
+		}
+		break;
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ decxmi: (node %i) read from unimplemented "
+			    "0x%08lx ]\n", node_nr, (long)relative_addr,
+			    (int)odata);
+		} else {
+			debug("[ decxmi: (node %i) write to unimplemented "
+			    "0x%08lx: 0x%08x ]\n", node_nr,
+			    (long)relative_addr, (int)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_decxmi_init():
+ */
+void dev_decxmi_init(struct memory *mem, uint64_t baseaddr)
+{
+	struct decxmi_data *d;
+
+	CHECK_ALLOCATION(d = (struct decxmi_data *) malloc(sizeof(struct decxmi_data)));
+	memset(d, 0, sizeof(struct decxmi_data));
+
+	memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH,
+	    dev_decxmi_access, d, DM_DEFAULT, NULL);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_dec5800.cc gxemul-0.7.0+dfsg/src/devices/dev_dec5800.cc
--- gxemul-0.6.2/src/devices/dev_dec5800.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dec5800.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,511 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: DECsystem 58x0 devices
- *
- *  Emulation of devices found in a DECsystem 58x0, where x is the number
- *  of CPUs in the system. (The CPU board is called KN5800 by Ultrix.)
- *
- *	o)  timers and misc stuff
- *	o)  BI  (Backplane Interconnect)
- *	o)  CCA (Console Communication Area)
- *	o)  XMI (Extended Memory Interconnect)
- *
- *  TODO:  This hardware is not very easy to find docs about.
- *  Perhaps VAX 6000/300 docs?
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define DEV_DEC5800_LENGTH		0x1000		/*  TODO  */
-
-struct dec5800_data {
-	uint32_t	csr;
-	struct interrupt cpu_irq;
-
-	uint32_t	vector_0x50;
-
-	struct interrupt timer_irq;
-};
-
-
-void dec5800_interrupt_assert(struct interrupt *interrupt)
-{
-	struct dec5800_data *d = (struct dec5800_data *) interrupt->extra;
-	d->csr |= (1 << interrupt->line);
-	if (d->csr & 0x10000000)
-		INTERRUPT_ASSERT(d->cpu_irq);
-}
-void dec5800_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct dec5800_data *d = (struct dec5800_data *) interrupt->extra;
-	d->csr &= ~(1 << interrupt->line);
-	if (!(d->csr & 0x10000000))
-		INTERRUPT_DEASSERT(d->cpu_irq);
-}
-
-
-DEVICE_TICK(dec5800)
-{
-	struct dec5800_data *d = (struct dec5800_data *) extra;
-
-	/*  Timer interrupts?  */
-	if (d->csr & 0x8000) {
-		debug("[ dec5800: timer interrupt! ]\n");
-
-		/*  Set timer interrupt pending bit:  */
-		d->csr |= 0x20000000;
-
-		INTERRUPT_ASSERT(d->timer_irq);
-	}
-}
-
-
-DEVICE_ACCESS(dec5800_vectors)
-{
-	uint64_t idata = 0, odata = 0;
-	struct dec5800_data *d = (struct dec5800_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (writeflag == MEM_READ) {
-		/*  TODO  */
-		/*  0xfc = transmit interrupt, 0xf8 = receive interrupt,
-		    0x80 = IPI  */
-		odata = d->vector_0x50;
-/* odata = 0xfc; */
-		debug("[ dec5800_vectors: read from 0x%02x: 0x%02x ]\n",
-		    (int)relative_addr, (int)odata);
-	} else {
-		d->vector_0x50 = idata;
-		debug("[ dec5800_vectors: write to 0x%02x: 0x%02x ]\n",
-		    (int)relative_addr, (int)idata);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(dec5800)
-{
-	uint64_t idata = 0, odata = 0;
-	struct dec5800_data *d = (struct dec5800_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  Lowest 4 bits of csr contain cpu id:  */
-	d->csr = (d->csr & ~0xf) | (cpu->cpu_id & 0xf);
-
-	switch (relative_addr) {
-	case 0x0000:	/*  csr  */
-		if (writeflag == MEM_READ) {
-			odata = d->csr;
-			odata ^= random() & 0x10000;
-			debug("[ dec5800: read from csr: 0x%08x ]\n",
-			    (int)odata);
-		} else {
-			d->csr = idata;
-
-			/*  Ack. timer interrupts:  */
-			d->csr &= ~0x20000000;
-			INTERRUPT_DEASSERT(d->timer_irq);
-
-			debug("[ dec5800: write to csr: 0x%08x ]\n",
-			    (int)idata);
-		}
-		break;
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ dec5800: read from 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			debug("[ dec5800: write to  0x%08lx: 0x%08x ]\n",
-			    (long)relative_addr, (int)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(dec5800)
-{
-	struct dec5800_data *d;
-	char tmpstr[200];
-	int i;
-
-	CHECK_ALLOCATION(d = (struct dec5800_data *) malloc(sizeof(struct dec5800_data)));
-	memset(d, 0, sizeof(struct dec5800_data));
-
-	snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path);
-	INTERRUPT_CONNECT(tmpstr, d->cpu_irq);
-
-	snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
-	INTERRUPT_CONNECT(tmpstr, d->timer_irq);
-
-	/*  Register 32 CSR interrupts, corresponding to bits in the CSR:  */
-	for (i=0; i<32; i++) {
-		char n[200];
-		struct interrupt templ;
-		snprintf(n, sizeof(n), "%s.dec5800.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = dec5800_interrupt_assert;
-		templ.interrupt_deassert = dec5800_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	memory_device_register(devinit->machine->memory, "dec5800",
-	    devinit->addr, DEV_DEC5800_LENGTH, dev_dec5800_access,
-	    d, DM_DEFAULT, NULL);
-	memory_device_register(devinit->machine->memory, "dec5800_vectors",
-	    devinit->addr + 0x30000000, 0x100, dev_dec5800_vectors_access,
-	    d, DM_DEFAULT, NULL);
-	machine_add_tickfunction(devinit->machine, dev_dec5800_tick,
-	    d, 14);
-
-	return 1;
-}
-
-
-/*****************************************************************************/
-
-
-#include "thirdparty/bireg.h"
-
-/*  16 slots, 0x2000 bytes each  */
-#define DEV_DECBI_LENGTH		0x20000
-
-struct decbi_data {
-	int		csr[NNODEBI];
-};
-
-
-DEVICE_ACCESS(decbi)
-{
-	uint64_t idata = 0, odata = 0;
-	int node_nr;
-	struct decbi_data *d = (struct decbi_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	relative_addr += BI_NODESIZE;	/*  HACK  */
-
-	node_nr = relative_addr / BI_NODESIZE;
-	relative_addr &= (BI_NODESIZE - 1);
-
-	/*  TODO:  This "1" here is the max node number in actual use.  */
-	if (node_nr > 1 || node_nr >= NNODEBI)
-		return 0;
-
-	switch (relative_addr) {
-	case BIREG_DTYPE:
-		if (writeflag==MEM_READ) {
-			/*
-			 *  This is a list of the devices in our BI slots:
-			 */
-			switch (node_nr) {
-			case 1:	odata = BIDT_KDB50; break;	/*  Disk  */
-			/*  case 2:	odata = BIDT_DEBNA; break;  */
-				/*  BIDT_DEBNA = Ethernet  */
-			/*  case 3:	odata = BIDT_MS820; break;  */
-				/*  BIDT_MS820 = Memory  */
-			default:
-				/*  No device.  */
-				odata = 0;
-			}
-
-			debug("[ decbi: (node %i) read from BIREG_DTYPE:"
-			    " 0x%x ]\n", node_nr, (int)odata);
-		} else {
-			debug("[ decbi: (node %i) attempt to write to "
-			    "BIREG_DTYPE: 0x%08x ]\n", node_nr, (int)idata);
-		}
-		break;
-	case BIREG_VAXBICSR:
-		if (writeflag==MEM_READ) {
-			odata = (d->csr[node_nr] & ~BICSR_NODEMASK) | node_nr;
-			debug("[ decbi: (node %i) read from BIREG_"
-			    "VAXBICSR: 0x%x ]\n", node_nr, (int)odata);
-		} else {
-			d->csr[node_nr] = idata;
-			debug("[ decbi: (node %i) attempt to write to "
-			    "BIREG_VAXBICSR: 0x%08x ]\n", node_nr, (int)idata);
-		}
-		break;
-	case 0xf4:
-		if (writeflag==MEM_READ) {
-			odata = 0xffff;	/*  ?  */
-			debug("[ decbi: (node %i) read from 0xf4: "
-			    "0x%x ]\n", node_nr, (int)odata);
-		} else {
-			debug("[ decbi: (node %i) attempt to write "
-			    "to 0xf4: 0x%08x ]\n", node_nr, (int)idata);
-		}
-		break;
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ decbi: (node %i) read from unimplemented "
-			    "0x%08lx ]\n", node_nr, (long)relative_addr,
-			    (int)odata);
-		} else {
-			debug("[ decbi: (node %i) write to unimplemented "
-			    "0x%08lx: 0x%08x ]\n", node_nr,
-			    (long)relative_addr, (int)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(decbi)
-{
-	struct decbi_data *d;
-
-	CHECK_ALLOCATION(d = (struct decbi_data *) malloc(sizeof(struct decbi_data)));
-	memset(d, 0, sizeof(struct decbi_data));
-
-	memory_device_register(devinit->machine->memory, "decbi",
-	    devinit->addr + 0x2000, DEV_DECBI_LENGTH - 0x2000,
-	    dev_decbi_access, d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  CCA, "Console Communication Area" for a DEC 5800 SMP system.
- */
-
-struct deccca_data {
-	int		dummy;
-};
-
-
-DEVICE_ACCESS(deccca)
-{
-	uint64_t idata = 0, odata = 0;
-	/*  struct deccca_data *d = extra;  */
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	case 6:
-	case 7:
-		/*  CCA "ID" bytes? These must be here, or Ultrix complains.  */
-		if (writeflag == MEM_READ)
-			odata = 67;
-		break;
-	case 8:
-		if (writeflag == MEM_READ)
-			odata = cpu->machine->ncpus;
-		break;
-	case 20:
-		if (writeflag == MEM_READ)
-			odata = (1 << cpu->machine->ncpus) - 1;
-			    /*  one bit for each cpu  */
-		break;
-	case 28:
-		if (writeflag == MEM_READ)
-			odata = (1 << cpu->machine->ncpus) - 1;
-			    /*  one bit for each enabled(?) cpu  */
-		break;
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ deccca: read from 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			debug("[ deccca: write to  0x%08lx: 0x%08x ]\n",
-			    (long)relative_addr, (int)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_deccca_init():
- */
-void dev_deccca_init(struct memory *mem, uint64_t baseaddr)
-{
-	struct deccca_data *d;
-
-	CHECK_ALLOCATION(d = (struct deccca_data *) malloc(sizeof(struct deccca_data)));
-	memset(d, 0, sizeof(struct deccca_data));
-
-	memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH,
-	    dev_deccca_access, d, DM_DEFAULT, NULL);
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  DEC 5800 XMI (this has to do with SMP...)
- */
-
-#include "thirdparty/xmireg.h"
-
-struct decxmi_data {
-	uint32_t		reg_0xc[NNODEXMI];
-};
-
-
-/*
- *  dev_decxmi_access():
- */
-DEVICE_ACCESS(decxmi)
-{
-	uint64_t idata = 0, odata = 0;
-	int node_nr;
-	struct decxmi_data *d = (struct decxmi_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	node_nr = relative_addr / XMI_NODESIZE;
-	relative_addr &= (XMI_NODESIZE - 1);
-
-	if (node_nr >= cpu->machine->ncpus + 1 || node_nr >= NNODEXMI)
-		return 0;
-
-	switch (relative_addr) {
-	case XMI_TYPE:
-		if (writeflag == MEM_READ) {
-			/*
-			 *  The first node is an XMI->BI adapter node, and then
-			 *  there are n CPU nodes.
-			 */
-			odata = XMIDT_ISIS;
-			if (node_nr == 0)
-				odata = XMIDT_DWMBA;
-
-			debug("[ decxmi: (node %i) read from XMI_TYPE: "
-			    "0x%08x ]\n", node_nr, (int)odata);
-		} else
-			debug("[ decxmi: (node %i) write to XMI_TYPE: "
-			    "0x%08x ]\n", node_nr, (int)idata);
-		break;
-	case XMI_BUSERR:
-		if (writeflag == MEM_READ) {
-			odata = 0;
-			debug("[ decxmi: (node %i) read from XMI_BUSERR: "
-			    "0x%08x ]\n", node_nr, (int)odata);
-		} else
-			debug("[ decxmi: (node %i) write to XMI_BUSERR: "
-			    "0x%08x ]\n", node_nr, (int)idata);
-		break;
-	case XMI_FAIL:
-		if (writeflag == MEM_READ) {
-			odata = 0;
-			debug("[ decxmi: (node %i) read from XMI_FAIL: "
-			    "0x%08x ]\n", node_nr, (int)odata);
-		} else
-			debug("[ decxmi: (node %i) write to XMI_FAIL: "
-			    "0x%08x ]\n", node_nr, (int)idata);
-		break;
-	case 0xc:
-		if (writeflag == MEM_READ) {
-			odata = d->reg_0xc[node_nr];
-			debug("[ decxmi: (node %i) read from REG 0xC: "
-			    "0x%08x ]\n", node_nr, (int)odata);
-		} else {
-			d->reg_0xc[node_nr] = idata;
-			debug("[ decxmi: (node %i) write to REG 0xC: "
-			    "0x%08x ]\n", node_nr, (int)idata);
-		}
-		break;
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ decxmi: (node %i) read from unimplemented "
-			    "0x%08lx ]\n", node_nr, (long)relative_addr,
-			    (int)odata);
-		} else {
-			debug("[ decxmi: (node %i) write to unimplemented "
-			    "0x%08lx: 0x%08x ]\n", node_nr,
-			    (long)relative_addr, (int)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_decxmi_init():
- */
-void dev_decxmi_init(struct memory *mem, uint64_t baseaddr)
-{
-	struct decxmi_data *d;
-
-	CHECK_ALLOCATION(d = (struct decxmi_data *) malloc(sizeof(struct decxmi_data)));
-	memset(d, 0, sizeof(struct decxmi_data));
-
-	memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH,
-	    dev_decxmi_access, d, DM_DEFAULT, NULL);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_dec_ioasic.c gxemul-0.7.0+dfsg/src/devices/dev_dec_ioasic.c
--- gxemul-0.6.2/src/devices/dev_dec_ioasic.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dec_ioasic.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,477 @@
+/*
+ *  Copyright (C) 2004-2018  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: IOASIC device used in some DECstation machines
+ *
+ *  TODO:  Lots of stuff, such as DMA and all bits in the control registers.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "devices.h"
+#include "interrupt.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/dec_kn03.h"
+#include "thirdparty/tc_ioasicreg.h"
+
+
+#define IOASIC_DEBUG
+/* #define debug fatal */
+
+
+void dec_ioasic_reassert(struct dec_ioasic_data* d)
+{
+	// printf("[ intr = 0x%08x, imsk = 0x%08x ]\n", d->intr, d->imsk);
+
+	if (d->intr & d->imsk && !d->int_asserted) {
+		d->int_asserted = 1;
+		d->irq->interrupt_assert(d->irq);
+	}
+	if (!(d->intr & d->imsk) && d->int_asserted) {
+		d->int_asserted = 0;
+		d->irq->interrupt_deassert(d->irq);
+	}
+}
+
+
+DEVICE_ACCESS(dec_ioasic)
+{
+	struct dec_ioasic_data *d = (struct dec_ioasic_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	// uint64_t curptr;
+	// uint32_t csr;
+	// int dma_len, dma_res, regnr;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	
+	case 0:
+		/*  NetBSD/pmax and OpenBSD/pmax read from this address.  */
+		break;
+
+	case IOASIC_SCSI_DMAPTR:
+		if (writeflag == MEM_WRITE)
+			d->scsi_dmaptr = idata;
+		else
+			odata = d->scsi_dmaptr;
+
+		debug("[ dec_ioasic: %s SCSI_DMAPTR, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_SCSI_NEXTPTR:
+		if (writeflag == MEM_WRITE)
+			d->scsi_nextptr = idata;
+		else
+			odata = d->scsi_nextptr;
+
+		debug("[ dec_ioasic: %s SCSI_NEXTPTR, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_LANCE_DMAPTR:
+		if (writeflag == MEM_WRITE)
+			d->lance_dmaptr = idata;
+		else
+			odata = d->lance_dmaptr;
+
+		debug("[ dec_ioasic: %s LANCE_DMAPTR, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_FLOPPY_DMAPTR:
+		if (writeflag == MEM_WRITE)
+			d->floppy_dmaptr = idata;
+		else
+			odata = d->floppy_dmaptr;
+
+		debug("[ dec_ioasic: %s FLOPPY_DMAPTR, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_ISDN_X_DMAPTR:
+		if (writeflag == MEM_WRITE)
+			d->isdn_x_dmaptr = idata;
+		else
+			odata = d->isdn_x_dmaptr;
+
+		debug("[ dec_ioasic: %s ISDN_X_DMAPTR, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_ISDN_X_NEXTPTR:
+		if (writeflag == MEM_WRITE)
+			d->isdn_x_nextptr = idata;
+		else
+			odata = d->isdn_x_nextptr;
+
+		debug("[ dec_ioasic: %s ISDN_X_NEXTPTR, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_ISDN_R_DMAPTR:
+		if (writeflag == MEM_WRITE)
+			d->isdn_r_dmaptr = idata;
+		else
+			odata = d->isdn_r_dmaptr;
+
+		debug("[ dec_ioasic: %s ISDN_R_DMAPTR, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_ISDN_R_NEXTPTR:
+		if (writeflag == MEM_WRITE)
+			d->isdn_r_nextptr = idata;
+		else
+			odata = d->isdn_r_nextptr;
+
+		debug("[ dec_ioasic: %s ISDN_R_NEXTPTR, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_CSR:
+		if (writeflag == MEM_WRITE)
+			d->csr = idata;
+		else
+			odata = d->csr;
+
+		debug("[ dec_ioasic: %s CSR, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+#if 0
+		if (writeflag == MEM_WRITE) {
+			csr = d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) / 0x10];
+
+			d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &=
+			    ~IOASIC_INTR_T2_PAGE_END;
+
+			if (csr & IOASIC_CSR_DMAEN_T2) {
+				/*  Transmit data:  */
+				curptr = (d->reg[(IOASIC_SCC_T2_DMAPTR -
+				    IOASIC_SLOT_1_START) / 0x10] >> 3)
+				    | ((d->reg[(IOASIC_SCC_T2_DMAPTR -
+				    IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
+				dma_len = 0x1000 - (curptr & 0xffc);
+
+				if ((curptr & 0xfff) == 0)
+					break;
+
+				if (d->dma_func[3] != NULL) {
+					d->dma_func[3](cpu,
+					    d->dma_func_extra[3], curptr,
+					    dma_len, 1);
+				} else
+					fatal("[ dec_ioasic: DMA tx: data @ "
+					    "%08x, len %i bytes, but no "
+					    "handler? ]\n", (int)curptr,
+					    dma_len);
+
+				/*  and signal the end of page:  */
+				d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) /
+				    0x10] |= IOASIC_INTR_T2_PAGE_END;
+
+				d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) /
+				    0x10] &= ~IOASIC_CSR_DMAEN_T2;
+				curptr |= 0xfff;
+				curptr ++;
+
+				d->reg[(IOASIC_SCC_T2_DMAPTR -
+				    IOASIC_SLOT_1_START) / 0x10] = ((curptr <<
+				    3) & ~0x1f) | ((curptr >> 29) & 0x1f);
+			}
+
+			if (csr & IOASIC_CSR_DMAEN_R2) {
+				/*  Receive data:  */
+				curptr = (d->reg[(IOASIC_SCC_R2_DMAPTR -
+				    IOASIC_SLOT_1_START) / 0x10] >> 3)
+				    | ((d->reg[(IOASIC_SCC_R2_DMAPTR -
+				    IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
+				dma_len = 0x1000 - (curptr & 0xffc);
+
+				dma_res = 0;
+				if (d->dma_func[3] != NULL) {
+					dma_res = d->dma_func[3](cpu,
+					    d->dma_func_extra[3], curptr,
+					    dma_len, 0);
+				} else
+					fatal("[ dec_ioasic: DMA tx: data @ "
+					    "%08x, len %i bytes, but no "
+					    "handler? ]\n", (int)curptr,
+					    dma_len);
+
+				/*  and signal the end of page:  */
+				if (dma_res > 0) {
+					if ((curptr & 0x800) != ((curptr +
+					    dma_res) & 0x800))
+						d->reg[(IOASIC_INTR -
+						    IOASIC_SLOT_1_START) / 0x10]
+						    |= IOASIC_INTR_R2_HALF_PAGE;
+					curptr += dma_res;
+/*					d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START
+					   ) / 0x10] &= ~IOASIC_CSR_DMAEN_R2; */
+					d->reg[(IOASIC_SCC_R2_DMAPTR -
+					    IOASIC_SLOT_1_START) / 0x10] =
+					    ((curptr << 3) & ~0x1f) | ((curptr
+					    >> 29) & 0x1f);
+				}
+			}
+		}
+#endif
+		break;
+
+	case IOASIC_INTR:
+		if (writeflag == MEM_WRITE) {
+			/*  Clear bits on write?  */
+			d->intr &= ~idata;
+			dec_ioasic_reassert(d);
+		} else {
+			odata = d->intr;
+
+			/*  Note/TODO: How about other models than KN03?  */
+			//if (!d->rackmount_flag)
+			//	odata |= KN03_INTR_PROD_JUMPER;
+		}
+
+		debug("[ dec_ioasic: %s INTR, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+
+		break;
+
+	case IOASIC_IMSK:
+		if (writeflag == MEM_WRITE) {
+			d->imsk = idata;
+			dec_ioasic_reassert(d);
+		} else {
+			odata = d->imsk;
+		}
+
+		debug("[ dec_ioasic: %s IMSK, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_ISDN_X_DATA:
+		if (writeflag == MEM_WRITE)
+			d->isdn_x_data = idata;
+		else
+			odata = d->isdn_x_data;
+
+		debug("[ dec_ioasic: %s ISDN_X_DATA, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_ISDN_R_DATA:
+		if (writeflag == MEM_WRITE)
+			d->isdn_r_data = idata;
+		else
+			odata = d->isdn_r_data;
+
+		debug("[ dec_ioasic: %s ISDN_R_DATA, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_LANCE_DECODE:
+		if (writeflag == MEM_WRITE)
+			d->lance_decode = idata;
+		else
+			odata = d->lance_decode;
+
+		debug("[ dec_ioasic: %s LANCE_DECODE, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_SCSI_DECODE:
+		if (writeflag == MEM_WRITE)
+			d->scsi_decode = idata;
+		else
+			odata = d->scsi_decode;
+
+		debug("[ dec_ioasic: %s SCSI_DECODE, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_SCC0_DECODE:
+		if (writeflag == MEM_WRITE)
+			d->scc0_decode = idata;
+		else
+			odata = d->scc0_decode;
+
+		debug("[ dec_ioasic: %s SCC0_DECODE, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_SCC1_DECODE:
+		if (writeflag == MEM_WRITE)
+			d->scc1_decode = idata;
+		else
+			odata = d->scc1_decode;
+
+		debug("[ dec_ioasic: %s SCC1_DECODE, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_FLOPPY_DECODE:
+		if (writeflag == MEM_WRITE)
+			d->floppy_decode = idata;
+		else
+			odata = d->floppy_decode;
+
+		debug("[ dec_ioasic: %s FLOPPY_DECODE, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_SCSI_SCR:
+		if (writeflag == MEM_WRITE)
+			d->scsi_scr = idata;
+		else
+			odata = d->scsi_scr;
+
+		debug("[ dec_ioasic: %s SCSI_SCR, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_SCSI_SDR0:
+		if (writeflag == MEM_WRITE)
+			d->scsi_sdr0 = idata;
+		else
+			odata = d->scsi_sdr0;
+
+		debug("[ dec_ioasic: %s SCSI_SDR0, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+	case IOASIC_SCSI_SDR1:
+		if (writeflag == MEM_WRITE)
+			d->scsi_sdr1 = idata;
+		else
+			odata = d->scsi_sdr1;
+
+		debug("[ dec_ioasic: %s SCSI_SDR1, data=0x%08x ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			writeflag == MEM_WRITE ? idata : odata);
+		break;
+
+
+	case IOASIC_SYS_ETHER_ADDRESS(0) + 0x00:
+	case IOASIC_SYS_ETHER_ADDRESS(0) + 0x04:
+	case IOASIC_SYS_ETHER_ADDRESS(0) + 0x08:
+	case IOASIC_SYS_ETHER_ADDRESS(0) + 0x0c:
+	case IOASIC_SYS_ETHER_ADDRESS(0) + 0x10:
+	case IOASIC_SYS_ETHER_ADDRESS(0) + 0x14:
+		/*  Station's ethernet address:  */
+		if (writeflag == MEM_WRITE) {
+			fatal("[ dec_ioasic: attempt to write to the station's"
+			    " ethernet address. ignored for now. ]\n");
+		} else {
+			odata = ((relative_addr - IOASIC_SYS_ETHER_ADDRESS(0)) / 4 + 1) * 0x10;
+		}
+		break;
+
+	/*  The DECstation 5000/125's PROM uses these for cache testing. TODO.  */
+	case 0x0f004:
+	case 0x1f008:
+	case 0x2f00c:
+	case 0x3f010:
+	case 0x4f014:
+	case 0x5f018:
+	case 0x6f01c:
+	case 0x7f020:
+	case 0x8f024:
+	case 0x9f028:
+	case 0xaf02c:
+	case 0xbf030:
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			fatal("[ dec_ioasic: unimplemented write to address "
+			    "0x%llx, data=0x%08llx ]\n",
+			    (long long)relative_addr, (long long)idata);
+		else
+			fatal("[ dec_ioasic: unimplemented read from address "
+			    "0x%llx ]\n", (long long)relative_addr);
+		// exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_dec_ioasic_init():
+ *
+ *  For DECstation "type 4", the rackmount_flag selects which model type
+ *  the IOASIC should identify itself as (5000 for zero, 5900 if rackmount_flag
+ *  is non-zero). It is probably not meaningful on other machines than
+ *  type 4.
+ */
+struct dec_ioasic_data *dev_dec_ioasic_init(struct cpu *cpu,
+	struct memory *mem, uint64_t baseaddr, int rackmount_flag, struct interrupt* irqp)
+{
+	struct dec_ioasic_data *d;
+
+	CHECK_ALLOCATION(d = (struct dec_ioasic_data *) malloc(sizeof(struct dec_ioasic_data)));
+	memset(d, 0, sizeof(struct dec_ioasic_data));
+
+	d->rackmount_flag = rackmount_flag;
+	d->irq = irqp;
+
+	memory_device_register(mem, "dec_ioasic", baseaddr,
+	    DEV_DEC_IOASIC_LENGTH, dev_dec_ioasic_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	return d;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_dec_ioasic.cc gxemul-0.7.0+dfsg/src/devices/dev_dec_ioasic.cc
--- gxemul-0.6.2/src/devices/dev_dec_ioasic.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dec_ioasic.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,477 +0,0 @@
-/*
- *  Copyright (C) 2004-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: IOASIC device used in some DECstation machines
- *
- *  TODO:  Lots of stuff, such as DMA and all bits in the control registers.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "devices.h"
-#include "interrupt.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/dec_kn03.h"
-#include "thirdparty/tc_ioasicreg.h"
-
-
-#define IOASIC_DEBUG
-/* #define debug fatal */
-
-
-void dec_ioasic_reassert(struct dec_ioasic_data* d)
-{
-	// printf("[ intr = 0x%08x, imsk = 0x%08x ]\n", d->intr, d->imsk);
-
-	if (d->intr & d->imsk && !d->int_asserted) {
-		d->int_asserted = 1;
-		d->irq->interrupt_assert(d->irq);
-	}
-	if (!(d->intr & d->imsk) && d->int_asserted) {
-		d->int_asserted = 0;
-		d->irq->interrupt_deassert(d->irq);
-	}
-}
-
-
-DEVICE_ACCESS(dec_ioasic)
-{
-	struct dec_ioasic_data *d = (struct dec_ioasic_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	// uint64_t curptr;
-	// uint32_t csr;
-	// int dma_len, dma_res, regnr;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	
-	case 0:
-		/*  NetBSD/pmax and OpenBSD/pmax read from this address.  */
-		break;
-
-	case IOASIC_SCSI_DMAPTR:
-		if (writeflag == MEM_WRITE)
-			d->scsi_dmaptr = idata;
-		else
-			odata = d->scsi_dmaptr;
-
-		debug("[ dec_ioasic: %s SCSI_DMAPTR, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_SCSI_NEXTPTR:
-		if (writeflag == MEM_WRITE)
-			d->scsi_nextptr = idata;
-		else
-			odata = d->scsi_nextptr;
-
-		debug("[ dec_ioasic: %s SCSI_NEXTPTR, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_LANCE_DMAPTR:
-		if (writeflag == MEM_WRITE)
-			d->lance_dmaptr = idata;
-		else
-			odata = d->lance_dmaptr;
-
-		debug("[ dec_ioasic: %s LANCE_DMAPTR, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_FLOPPY_DMAPTR:
-		if (writeflag == MEM_WRITE)
-			d->floppy_dmaptr = idata;
-		else
-			odata = d->floppy_dmaptr;
-
-		debug("[ dec_ioasic: %s FLOPPY_DMAPTR, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_ISDN_X_DMAPTR:
-		if (writeflag == MEM_WRITE)
-			d->isdn_x_dmaptr = idata;
-		else
-			odata = d->isdn_x_dmaptr;
-
-		debug("[ dec_ioasic: %s ISDN_X_DMAPTR, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_ISDN_X_NEXTPTR:
-		if (writeflag == MEM_WRITE)
-			d->isdn_x_nextptr = idata;
-		else
-			odata = d->isdn_x_nextptr;
-
-		debug("[ dec_ioasic: %s ISDN_X_NEXTPTR, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_ISDN_R_DMAPTR:
-		if (writeflag == MEM_WRITE)
-			d->isdn_r_dmaptr = idata;
-		else
-			odata = d->isdn_r_dmaptr;
-
-		debug("[ dec_ioasic: %s ISDN_R_DMAPTR, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_ISDN_R_NEXTPTR:
-		if (writeflag == MEM_WRITE)
-			d->isdn_r_nextptr = idata;
-		else
-			odata = d->isdn_r_nextptr;
-
-		debug("[ dec_ioasic: %s ISDN_R_NEXTPTR, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_CSR:
-		if (writeflag == MEM_WRITE)
-			d->csr = idata;
-		else
-			odata = d->csr;
-
-		debug("[ dec_ioasic: %s CSR, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-#if 0
-		if (writeflag == MEM_WRITE) {
-			csr = d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) / 0x10];
-
-			d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &=
-			    ~IOASIC_INTR_T2_PAGE_END;
-
-			if (csr & IOASIC_CSR_DMAEN_T2) {
-				/*  Transmit data:  */
-				curptr = (d->reg[(IOASIC_SCC_T2_DMAPTR -
-				    IOASIC_SLOT_1_START) / 0x10] >> 3)
-				    | ((d->reg[(IOASIC_SCC_T2_DMAPTR -
-				    IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
-				dma_len = 0x1000 - (curptr & 0xffc);
-
-				if ((curptr & 0xfff) == 0)
-					break;
-
-				if (d->dma_func[3] != NULL) {
-					d->dma_func[3](cpu,
-					    d->dma_func_extra[3], curptr,
-					    dma_len, 1);
-				} else
-					fatal("[ dec_ioasic: DMA tx: data @ "
-					    "%08x, len %i bytes, but no "
-					    "handler? ]\n", (int)curptr,
-					    dma_len);
-
-				/*  and signal the end of page:  */
-				d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) /
-				    0x10] |= IOASIC_INTR_T2_PAGE_END;
-
-				d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) /
-				    0x10] &= ~IOASIC_CSR_DMAEN_T2;
-				curptr |= 0xfff;
-				curptr ++;
-
-				d->reg[(IOASIC_SCC_T2_DMAPTR -
-				    IOASIC_SLOT_1_START) / 0x10] = ((curptr <<
-				    3) & ~0x1f) | ((curptr >> 29) & 0x1f);
-			}
-
-			if (csr & IOASIC_CSR_DMAEN_R2) {
-				/*  Receive data:  */
-				curptr = (d->reg[(IOASIC_SCC_R2_DMAPTR -
-				    IOASIC_SLOT_1_START) / 0x10] >> 3)
-				    | ((d->reg[(IOASIC_SCC_R2_DMAPTR -
-				    IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
-				dma_len = 0x1000 - (curptr & 0xffc);
-
-				dma_res = 0;
-				if (d->dma_func[3] != NULL) {
-					dma_res = d->dma_func[3](cpu,
-					    d->dma_func_extra[3], curptr,
-					    dma_len, 0);
-				} else
-					fatal("[ dec_ioasic: DMA tx: data @ "
-					    "%08x, len %i bytes, but no "
-					    "handler? ]\n", (int)curptr,
-					    dma_len);
-
-				/*  and signal the end of page:  */
-				if (dma_res > 0) {
-					if ((curptr & 0x800) != ((curptr +
-					    dma_res) & 0x800))
-						d->reg[(IOASIC_INTR -
-						    IOASIC_SLOT_1_START) / 0x10]
-						    |= IOASIC_INTR_R2_HALF_PAGE;
-					curptr += dma_res;
-/*					d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START
-					   ) / 0x10] &= ~IOASIC_CSR_DMAEN_R2; */
-					d->reg[(IOASIC_SCC_R2_DMAPTR -
-					    IOASIC_SLOT_1_START) / 0x10] =
-					    ((curptr << 3) & ~0x1f) | ((curptr
-					    >> 29) & 0x1f);
-				}
-			}
-		}
-#endif
-		break;
-
-	case IOASIC_INTR:
-		if (writeflag == MEM_WRITE) {
-			/*  Clear bits on write?  */
-			d->intr &= ~idata;
-			dec_ioasic_reassert(d);
-		} else {
-			odata = d->intr;
-
-			/*  Note/TODO: How about other models than KN03?  */
-			//if (!d->rackmount_flag)
-			//	odata |= KN03_INTR_PROD_JUMPER;
-		}
-
-		debug("[ dec_ioasic: %s INTR, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-
-		break;
-
-	case IOASIC_IMSK:
-		if (writeflag == MEM_WRITE) {
-			d->imsk = idata;
-			dec_ioasic_reassert(d);
-		} else {
-			odata = d->imsk;
-		}
-
-		debug("[ dec_ioasic: %s IMSK, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_ISDN_X_DATA:
-		if (writeflag == MEM_WRITE)
-			d->isdn_x_data = idata;
-		else
-			odata = d->isdn_x_data;
-
-		debug("[ dec_ioasic: %s ISDN_X_DATA, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_ISDN_R_DATA:
-		if (writeflag == MEM_WRITE)
-			d->isdn_r_data = idata;
-		else
-			odata = d->isdn_r_data;
-
-		debug("[ dec_ioasic: %s ISDN_R_DATA, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_LANCE_DECODE:
-		if (writeflag == MEM_WRITE)
-			d->lance_decode = idata;
-		else
-			odata = d->lance_decode;
-
-		debug("[ dec_ioasic: %s LANCE_DECODE, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_SCSI_DECODE:
-		if (writeflag == MEM_WRITE)
-			d->scsi_decode = idata;
-		else
-			odata = d->scsi_decode;
-
-		debug("[ dec_ioasic: %s SCSI_DECODE, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_SCC0_DECODE:
-		if (writeflag == MEM_WRITE)
-			d->scc0_decode = idata;
-		else
-			odata = d->scc0_decode;
-
-		debug("[ dec_ioasic: %s SCC0_DECODE, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_SCC1_DECODE:
-		if (writeflag == MEM_WRITE)
-			d->scc1_decode = idata;
-		else
-			odata = d->scc1_decode;
-
-		debug("[ dec_ioasic: %s SCC1_DECODE, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_FLOPPY_DECODE:
-		if (writeflag == MEM_WRITE)
-			d->floppy_decode = idata;
-		else
-			odata = d->floppy_decode;
-
-		debug("[ dec_ioasic: %s FLOPPY_DECODE, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_SCSI_SCR:
-		if (writeflag == MEM_WRITE)
-			d->scsi_scr = idata;
-		else
-			odata = d->scsi_scr;
-
-		debug("[ dec_ioasic: %s SCSI_SCR, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_SCSI_SDR0:
-		if (writeflag == MEM_WRITE)
-			d->scsi_sdr0 = idata;
-		else
-			odata = d->scsi_sdr0;
-
-		debug("[ dec_ioasic: %s SCSI_SDR0, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-	case IOASIC_SCSI_SDR1:
-		if (writeflag == MEM_WRITE)
-			d->scsi_sdr1 = idata;
-		else
-			odata = d->scsi_sdr1;
-
-		debug("[ dec_ioasic: %s SCSI_SDR1, data=0x%08x ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			writeflag == MEM_WRITE ? idata : odata);
-		break;
-
-
-	case IOASIC_SYS_ETHER_ADDRESS(0) + 0x00:
-	case IOASIC_SYS_ETHER_ADDRESS(0) + 0x04:
-	case IOASIC_SYS_ETHER_ADDRESS(0) + 0x08:
-	case IOASIC_SYS_ETHER_ADDRESS(0) + 0x0c:
-	case IOASIC_SYS_ETHER_ADDRESS(0) + 0x10:
-	case IOASIC_SYS_ETHER_ADDRESS(0) + 0x14:
-		/*  Station's ethernet address:  */
-		if (writeflag == MEM_WRITE) {
-			fatal("[ dec_ioasic: attempt to write to the station's"
-			    " ethernet address. ignored for now. ]\n");
-		} else {
-			odata = ((relative_addr - IOASIC_SYS_ETHER_ADDRESS(0)) / 4 + 1) * 0x10;
-		}
-		break;
-
-	/*  The DECstation 5000/125's PROM uses these for cache testing. TODO.  */
-	case 0x0f004:
-	case 0x1f008:
-	case 0x2f00c:
-	case 0x3f010:
-	case 0x4f014:
-	case 0x5f018:
-	case 0x6f01c:
-	case 0x7f020:
-	case 0x8f024:
-	case 0x9f028:
-	case 0xaf02c:
-	case 0xbf030:
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE)
-			fatal("[ dec_ioasic: unimplemented write to address "
-			    "0x%llx, data=0x%08llx ]\n",
-			    (long long)relative_addr, (long long)idata);
-		else
-			fatal("[ dec_ioasic: unimplemented read from address "
-			    "0x%llx ]\n", (long long)relative_addr);
-		// exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_dec_ioasic_init():
- *
- *  For DECstation "type 4", the rackmount_flag selects which model type
- *  the IOASIC should identify itself as (5000 for zero, 5900 if rackmount_flag
- *  is non-zero). It is probably not meaningful on other machines than
- *  type 4.
- */
-struct dec_ioasic_data *dev_dec_ioasic_init(struct cpu *cpu,
-	struct memory *mem, uint64_t baseaddr, int rackmount_flag, struct interrupt* irqp)
-{
-	struct dec_ioasic_data *d;
-
-	CHECK_ALLOCATION(d = (struct dec_ioasic_data *) malloc(sizeof(struct dec_ioasic_data)));
-	memset(d, 0, sizeof(struct dec_ioasic_data));
-
-	d->rackmount_flag = rackmount_flag;
-	d->irq = irqp;
-
-	memory_device_register(mem, "dec_ioasic", baseaddr,
-	    DEV_DEC_IOASIC_LENGTH, dev_dec_ioasic_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	return d;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_disk.c gxemul-0.7.0+dfsg/src/devices/dev_disk.c
--- gxemul-0.6.2/src/devices/dev_disk.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_disk.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,196 @@
+/*
+ *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: A simple disk controller device, for the test machines
+ *
+ *  Basic "disk" device. This is a simple test device which can be used to
+ *  read and write data from disk devices.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "diskimage.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "testmachine/dev_disk.h"
+
+extern int verbose;
+
+#define	SECTOR_SIZE	512
+
+
+struct disk_data {
+	uint64_t	offset;
+	int		disk_id;
+	int		command;
+	int		status;
+	unsigned char	*buf;
+};
+
+
+DEVICE_ACCESS(disk_buf)
+{
+	struct disk_data *d = (struct disk_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		memcpy(d->buf + relative_addr, data, len);
+	else
+		memcpy(data, d->buf + relative_addr, len);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(disk)
+{
+	struct disk_data *d = (struct disk_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case DEV_DISK_OFFSET:
+		if (writeflag == MEM_READ) {
+			odata = d->offset;
+		} else {
+			d->offset = idata;
+		}
+		
+		if (d->offset & (SECTOR_SIZE-1))
+			fatal("[ disk: WARNING! offset (%lli) must be %i-byte aligned ]\n",
+				(long long)d->offset, SECTOR_SIZE);
+		
+		break;
+
+	case DEV_DISK_OFFSET_HIGH32:
+		if (writeflag == MEM_READ) {
+			odata = d->offset >> 32;
+		} else {
+			d->offset = (uint32_t)d->offset | (idata << 32);
+		}
+		break;
+
+	case DEV_DISK_ID:
+		if (writeflag == MEM_READ) {
+			odata = d->disk_id;
+		} else {
+			d->disk_id = idata;
+		}
+		break;
+
+	case DEV_DISK_START_OPERATION:
+		if (writeflag == MEM_READ) {
+			odata = d->command;
+		} else {
+			d->command = idata;
+			switch (d->command) {
+			case 0:	d->status = diskimage_access(cpu->machine,
+				     d->disk_id, DISKIMAGE_IDE, 0,
+				     d->offset, d->buf, SECTOR_SIZE);
+				break;
+			case 1:	d->status = diskimage_access(cpu->machine,
+				     d->disk_id, DISKIMAGE_IDE, 1,
+				     d->offset, d->buf, SECTOR_SIZE);
+				break;
+			}
+			
+			if (verbose >= 2) {
+				debug("[ disk: %s disk %i offset %lli ]\n",
+					d->command ? "WRITE" : "READ",
+					d->disk_id, (long long)d->offset);
+			}
+			
+			d->offset += SECTOR_SIZE;
+		}
+		break;
+
+	case DEV_DISK_STATUS:
+		if (writeflag == MEM_READ) {
+			odata = d->status;
+		} else {
+			d->status = idata;
+		}
+		break;
+
+	default:if (writeflag == MEM_WRITE) {
+			fatal("[ disk: unimplemented write to "
+			    "offset 0x%x: data=0x%x ]\n", (int)
+			    relative_addr, (int)idata);
+		} else {
+			fatal("[ disk: unimplemented read from "
+			    "offset 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(disk)
+{
+	struct disk_data *d;
+	size_t nlen;
+	char *n1, *n2;
+                 
+	CHECK_ALLOCATION(d = (struct disk_data *) malloc(sizeof(struct disk_data)));
+	memset(d, 0, sizeof(struct disk_data));
+
+	nlen = strlen(devinit->name) + 30;
+	CHECK_ALLOCATION(n1 = (char *) malloc(nlen));
+	CHECK_ALLOCATION(n2 = (char *) malloc(nlen));
+
+	CHECK_ALLOCATION(d->buf = (unsigned char *) malloc(devinit->machine->arch_pagesize));
+	memset(d->buf, 0, devinit->machine->arch_pagesize);
+
+	snprintf(n1, nlen, "%s [control]", devinit->name);
+	snprintf(n2, nlen, "%s [data buffer]", devinit->name);
+
+	memory_device_register(devinit->machine->memory, n1,
+	    devinit->addr, DEV_DISK_BUFFER, dev_disk_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	memory_device_register(devinit->machine->memory, n2,
+	    devinit->addr + DEV_DISK_BUFFER,
+	    devinit->machine->arch_pagesize, dev_disk_buf_access,
+	    (void *)d, DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK |
+	    DM_READS_HAVE_NO_SIDE_EFFECTS, d->buf);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_disk.cc gxemul-0.7.0+dfsg/src/devices/dev_disk.cc
--- gxemul-0.6.2/src/devices/dev_disk.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_disk.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,196 +0,0 @@
-/*
- *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: A simple disk controller device, for the test machines
- *
- *  Basic "disk" device. This is a simple test device which can be used to
- *  read and write data from disk devices.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "diskimage.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "testmachine/dev_disk.h"
-
-extern int verbose;
-
-#define	SECTOR_SIZE	512
-
-
-struct disk_data {
-	uint64_t	offset;
-	int		disk_id;
-	int		command;
-	int		status;
-	unsigned char	*buf;
-};
-
-
-DEVICE_ACCESS(disk_buf)
-{
-	struct disk_data *d = (struct disk_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		memcpy(d->buf + relative_addr, data, len);
-	else
-		memcpy(data, d->buf + relative_addr, len);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(disk)
-{
-	struct disk_data *d = (struct disk_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case DEV_DISK_OFFSET:
-		if (writeflag == MEM_READ) {
-			odata = d->offset;
-		} else {
-			d->offset = idata;
-		}
-		
-		if (d->offset & (SECTOR_SIZE-1))
-			fatal("[ disk: WARNING! offset (%lli) must be %i-byte aligned ]\n",
-				(long long)d->offset, SECTOR_SIZE);
-		
-		break;
-
-	case DEV_DISK_OFFSET_HIGH32:
-		if (writeflag == MEM_READ) {
-			odata = d->offset >> 32;
-		} else {
-			d->offset = (uint32_t)d->offset | (idata << 32);
-		}
-		break;
-
-	case DEV_DISK_ID:
-		if (writeflag == MEM_READ) {
-			odata = d->disk_id;
-		} else {
-			d->disk_id = idata;
-		}
-		break;
-
-	case DEV_DISK_START_OPERATION:
-		if (writeflag == MEM_READ) {
-			odata = d->command;
-		} else {
-			d->command = idata;
-			switch (d->command) {
-			case 0:	d->status = diskimage_access(cpu->machine,
-				     d->disk_id, DISKIMAGE_IDE, 0,
-				     d->offset, d->buf, SECTOR_SIZE);
-				break;
-			case 1:	d->status = diskimage_access(cpu->machine,
-				     d->disk_id, DISKIMAGE_IDE, 1,
-				     d->offset, d->buf, SECTOR_SIZE);
-				break;
-			}
-			
-			if (verbose >= 2) {
-				debug("[ disk: %s disk %i offset %lli ]\n",
-					d->command ? "WRITE" : "READ",
-					d->disk_id, (long long)d->offset);
-			}
-			
-			d->offset += SECTOR_SIZE;
-		}
-		break;
-
-	case DEV_DISK_STATUS:
-		if (writeflag == MEM_READ) {
-			odata = d->status;
-		} else {
-			d->status = idata;
-		}
-		break;
-
-	default:if (writeflag == MEM_WRITE) {
-			fatal("[ disk: unimplemented write to "
-			    "offset 0x%x: data=0x%x ]\n", (int)
-			    relative_addr, (int)idata);
-		} else {
-			fatal("[ disk: unimplemented read from "
-			    "offset 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(disk)
-{
-	struct disk_data *d;
-	size_t nlen;
-	char *n1, *n2;
-                 
-	CHECK_ALLOCATION(d = (struct disk_data *) malloc(sizeof(struct disk_data)));
-	memset(d, 0, sizeof(struct disk_data));
-
-	nlen = strlen(devinit->name) + 30;
-	CHECK_ALLOCATION(n1 = (char *) malloc(nlen));
-	CHECK_ALLOCATION(n2 = (char *) malloc(nlen));
-
-	CHECK_ALLOCATION(d->buf = (unsigned char *) malloc(devinit->machine->arch_pagesize));
-	memset(d->buf, 0, devinit->machine->arch_pagesize);
-
-	snprintf(n1, nlen, "%s [control]", devinit->name);
-	snprintf(n2, nlen, "%s [data buffer]", devinit->name);
-
-	memory_device_register(devinit->machine->memory, n1,
-	    devinit->addr, DEV_DISK_BUFFER, dev_disk_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	memory_device_register(devinit->machine->memory, n2,
-	    devinit->addr + DEV_DISK_BUFFER,
-	    devinit->machine->arch_pagesize, dev_disk_buf_access,
-	    (void *)d, DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK |
-	    DM_READS_HAVE_NO_SIDE_EFFECTS, d->buf);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_dreamcast_asic.c gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_asic.c
--- gxemul-0.6.2/src/devices/dev_dreamcast_asic.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_asic.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,221 @@
+/*
+ *  Copyright (C) 2006-2011  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Dreamcast-specific ASIC
+ *
+ *  A simple device which forwards various Dreamcast device events as
+ *  interrupts 13, 11, or 9, to the CPU.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/dreamcast_sysasicvar.h"
+#include "thirdparty/sh4_exception.h"
+
+
+// #define debug fatal
+
+#define	DREAMCAST_ASIC_TICK_SHIFT	15
+
+struct dreamcast_asic_data {
+	uint32_t	pending_irq[3];
+	uint32_t	mask_13[3];
+	uint32_t	mask_11[3];
+	uint32_t	mask_9[3];
+
+	int		asserted_13;
+	int		asserted_11;
+	int		asserted_9;
+
+	struct interrupt irq_13;
+	struct interrupt irq_11;
+	struct interrupt irq_9;
+};
+
+
+DEVICE_TICK(dreamcast_asic)
+{
+	struct dreamcast_asic_data *d = (struct dreamcast_asic_data *) extra;
+	int i, old_asserted_13 = d->asserted_13, old_asserted_11 =
+	    d->asserted_11, old_asserted_9 = d->asserted_9;
+
+	d->asserted_13 = d->asserted_11 = d->asserted_9 = 0;
+
+	for (i=0; i<3; i++) {
+		if (d->pending_irq[i] & d->mask_13[i])
+			d->asserted_13 = 1;
+
+		if (d->pending_irq[i] & d->mask_11[i])
+			d->asserted_11 = 1;
+
+		if (d->pending_irq[i] & d->mask_9[i])
+			d->asserted_9 = 1;
+	}
+
+	if (d->asserted_13 != old_asserted_13) {
+		if (d->asserted_13)
+			INTERRUPT_ASSERT(d->irq_13);
+		else
+			INTERRUPT_DEASSERT(d->irq_13);
+	}
+	if (d->asserted_11 != old_asserted_11) {
+		if (d->asserted_11)
+			INTERRUPT_ASSERT(d->irq_11);
+		else
+			INTERRUPT_DEASSERT(d->irq_11);
+	}
+	if (d->asserted_9 != old_asserted_9) {
+		if (d->asserted_9)
+			INTERRUPT_ASSERT(d->irq_9);
+		else
+			INTERRUPT_DEASSERT(d->irq_9);
+	}
+}
+
+
+DEVICE_ACCESS(dreamcast_asic)
+{
+	struct dreamcast_asic_data *d = (struct dreamcast_asic_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int r;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	r = (relative_addr / 4) & 3;
+	if (r == 3) {
+		fatal("[ dreamcast_asic: Bad address ]\n");
+		r = 0;
+		exit(1);	// TODO?
+	}
+
+	switch (relative_addr) {
+
+	case 0:
+	case 4:
+	case 8:	if (writeflag == MEM_READ) {
+			odata = d->pending_irq[r];
+		} else {
+			/*  Should only be used interally by GXemul:  */
+			if (idata & 0x100000000ULL) {
+				/*  Set specific bits:  */
+				d->pending_irq[r] |= idata;
+			} else {
+				/*  Clear interrupt assertions:  */
+				d->pending_irq[r] &= ~idata;
+			}
+			dev_dreamcast_asic_tick(cpu, d);
+		}
+		break;
+
+	case 0x10:
+	case 0x14:
+	case 0x18:
+		if (writeflag == MEM_WRITE) {
+			d->mask_13[r] = idata;
+			dev_dreamcast_asic_tick(cpu, d);
+		} else {
+			odata = d->mask_13[r];
+		}
+		break;
+
+	case 0x20:
+	case 0x24:
+	case 0x28:
+		if (writeflag == MEM_WRITE) {
+			d->mask_11[r] = idata;
+			dev_dreamcast_asic_tick(cpu, d);
+		} else {
+			odata = d->mask_11[r];
+		}
+		break;
+
+	case 0x30:
+	case 0x34:
+	case 0x38:
+		if (writeflag == MEM_WRITE) {
+			d->mask_9[r] = idata;
+			dev_dreamcast_asic_tick(cpu, d);
+		} else {
+			odata = d->mask_9[r];
+		}
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			debug("[ dreamcast_asic: read from addr 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			debug("[ dreamcast_asic: write to addr 0x%x: 0x%x ]\n",
+			    (int)relative_addr, (int)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(dreamcast_asic)
+{
+	char tmpstr[300];
+	struct machine *machine = devinit->machine;
+	struct dreamcast_asic_data *d;
+
+	CHECK_ALLOCATION(d = (struct dreamcast_asic_data *) malloc(sizeof(struct dreamcast_asic_data)));
+	memset(d, 0, sizeof(struct dreamcast_asic_data));
+
+	/*  Connect to SH4 interrupt levels 13, 11, and 9:  */
+	snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]",
+	    devinit->interrupt_path, SH_INTEVT_IRL13);
+	INTERRUPT_CONNECT(tmpstr, d->irq_13);
+	snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]",
+	    devinit->interrupt_path, SH_INTEVT_IRL11);
+	INTERRUPT_CONNECT(tmpstr, d->irq_11);
+	snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]",
+	    devinit->interrupt_path, SH_INTEVT_IRL9);
+	INTERRUPT_CONNECT(tmpstr, d->irq_9);
+
+	memory_device_register(machine->memory, devinit->name, SYSASIC_BASE,
+	    SYSASIC_SIZE, dev_dreamcast_asic_access, d, DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(devinit->machine, dev_dreamcast_asic_tick, d,
+	    DREAMCAST_ASIC_TICK_SHIFT);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_dreamcast_asic.cc gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_asic.cc
--- gxemul-0.6.2/src/devices/dev_dreamcast_asic.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_asic.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,221 +0,0 @@
-/*
- *  Copyright (C) 2006-2011  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Dreamcast-specific ASIC
- *
- *  A simple device which forwards various Dreamcast device events as
- *  interrupts 13, 11, or 9, to the CPU.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/time.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/dreamcast_sysasicvar.h"
-#include "thirdparty/sh4_exception.h"
-
-
-// #define debug fatal
-
-#define	DREAMCAST_ASIC_TICK_SHIFT	15
-
-struct dreamcast_asic_data {
-	uint32_t	pending_irq[3];
-	uint32_t	mask_13[3];
-	uint32_t	mask_11[3];
-	uint32_t	mask_9[3];
-
-	int		asserted_13;
-	int		asserted_11;
-	int		asserted_9;
-
-	struct interrupt irq_13;
-	struct interrupt irq_11;
-	struct interrupt irq_9;
-};
-
-
-DEVICE_TICK(dreamcast_asic)
-{
-	struct dreamcast_asic_data *d = (struct dreamcast_asic_data *) extra;
-	int i, old_asserted_13 = d->asserted_13, old_asserted_11 =
-	    d->asserted_11, old_asserted_9 = d->asserted_9;
-
-	d->asserted_13 = d->asserted_11 = d->asserted_9 = 0;
-
-	for (i=0; i<3; i++) {
-		if (d->pending_irq[i] & d->mask_13[i])
-			d->asserted_13 = 1;
-
-		if (d->pending_irq[i] & d->mask_11[i])
-			d->asserted_11 = 1;
-
-		if (d->pending_irq[i] & d->mask_9[i])
-			d->asserted_9 = 1;
-	}
-
-	if (d->asserted_13 != old_asserted_13) {
-		if (d->asserted_13)
-			INTERRUPT_ASSERT(d->irq_13);
-		else
-			INTERRUPT_DEASSERT(d->irq_13);
-	}
-	if (d->asserted_11 != old_asserted_11) {
-		if (d->asserted_11)
-			INTERRUPT_ASSERT(d->irq_11);
-		else
-			INTERRUPT_DEASSERT(d->irq_11);
-	}
-	if (d->asserted_9 != old_asserted_9) {
-		if (d->asserted_9)
-			INTERRUPT_ASSERT(d->irq_9);
-		else
-			INTERRUPT_DEASSERT(d->irq_9);
-	}
-}
-
-
-DEVICE_ACCESS(dreamcast_asic)
-{
-	struct dreamcast_asic_data *d = (struct dreamcast_asic_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int r;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	r = (relative_addr / 4) & 3;
-	if (r == 3) {
-		fatal("[ dreamcast_asic: Bad address ]\n");
-		r = 0;
-		exit(1);	// TODO?
-	}
-
-	switch (relative_addr) {
-
-	case 0:
-	case 4:
-	case 8:	if (writeflag == MEM_READ) {
-			odata = d->pending_irq[r];
-		} else {
-			/*  Should only be used interally by GXemul:  */
-			if (idata & 0x100000000ULL) {
-				/*  Set specific bits:  */
-				d->pending_irq[r] |= idata;
-			} else {
-				/*  Clear interrupt assertions:  */
-				d->pending_irq[r] &= ~idata;
-			}
-			dev_dreamcast_asic_tick(cpu, d);
-		}
-		break;
-
-	case 0x10:
-	case 0x14:
-	case 0x18:
-		if (writeflag == MEM_WRITE) {
-			d->mask_13[r] = idata;
-			dev_dreamcast_asic_tick(cpu, d);
-		} else {
-			odata = d->mask_13[r];
-		}
-		break;
-
-	case 0x20:
-	case 0x24:
-	case 0x28:
-		if (writeflag == MEM_WRITE) {
-			d->mask_11[r] = idata;
-			dev_dreamcast_asic_tick(cpu, d);
-		} else {
-			odata = d->mask_11[r];
-		}
-		break;
-
-	case 0x30:
-	case 0x34:
-	case 0x38:
-		if (writeflag == MEM_WRITE) {
-			d->mask_9[r] = idata;
-			dev_dreamcast_asic_tick(cpu, d);
-		} else {
-			odata = d->mask_9[r];
-		}
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			debug("[ dreamcast_asic: read from addr 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			debug("[ dreamcast_asic: write to addr 0x%x: 0x%x ]\n",
-			    (int)relative_addr, (int)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(dreamcast_asic)
-{
-	char tmpstr[300];
-	struct machine *machine = devinit->machine;
-	struct dreamcast_asic_data *d;
-
-	CHECK_ALLOCATION(d = (struct dreamcast_asic_data *) malloc(sizeof(struct dreamcast_asic_data)));
-	memset(d, 0, sizeof(struct dreamcast_asic_data));
-
-	/*  Connect to SH4 interrupt levels 13, 11, and 9:  */
-	snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]",
-	    devinit->interrupt_path, SH_INTEVT_IRL13);
-	INTERRUPT_CONNECT(tmpstr, d->irq_13);
-	snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]",
-	    devinit->interrupt_path, SH_INTEVT_IRL11);
-	INTERRUPT_CONNECT(tmpstr, d->irq_11);
-	snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]",
-	    devinit->interrupt_path, SH_INTEVT_IRL9);
-	INTERRUPT_CONNECT(tmpstr, d->irq_9);
-
-	memory_device_register(machine->memory, devinit->name, SYSASIC_BASE,
-	    SYSASIC_SIZE, dev_dreamcast_asic_access, d, DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(devinit->machine, dev_dreamcast_asic_tick, d,
-	    DREAMCAST_ASIC_TICK_SHIFT);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_dreamcast_g2.c gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_g2.c
--- gxemul-0.6.2/src/devices/dev_dreamcast_g2.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_g2.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,298 @@
+/*
+ *  Copyright (C) 2006-2011  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Dreamcast G2 bus
+ *
+ *  Register offsets are from KOS, NetBSD sources, etc.
+ *
+ *  TODO:
+ *	Figure out what all these registers do!
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	NREGS_EXT_DMA		(0x80/sizeof(uint32_t))
+#define	NREGS_MISC		(0x80/sizeof(uint32_t))
+
+struct dreamcast_g2_data {
+	uint32_t	extdma_reg[NREGS_EXT_DMA];
+	uint32_t	misc_reg[NREGS_MISC];
+};
+
+
+/*
+ *  External DMA:  4 channels
+ *
+ *  Note: Addresses and sizes must be 32-byte aligned.
+ *  DIR is 0 for CPU to External device, 1 for External to CPU.
+ *  MODE should be 5 for transfers to/from the SPU.
+ */
+#define	EXTDMA_CTRL_EXT_ADDR	0x00	/*  EXTDMA_CTRL_* are repeated  */
+#define	EXTDMA_CTRL_SH4_ADDR	0x04	/*  4 times (once for each channel)  */
+#define	EXTDMA_CTRL_SIZE	0x08
+#define	EXTDMA_CTRL_DIR		0x0c
+#define	EXTDMA_CTRL_MODE	0x10
+#define	EXTDMA_CTRL_CHAN_ENABLE	0x14	/*  Channel enable  */
+#define	EXTDMA_CTRL_XFER_ENABLE	0x18	/*  Transfer enable  */
+#define	EXTDMA_CTRL_STATUS	0x1c	/*  Transfer status  */
+
+#define	EXTDMA_WAITSTATE	0x90
+#define	EXTDMA_MAGIC		0xbc
+#define	EXTDMA_MAGIC_VALUE	    0x4659404f
+#define	EXTDMA_MAGIC_VALUE_ROM	    0x46597f00
+
+#define	EXTDMA_STAT_EXT_ADDR	0xc0	/*  EXTDMA_STAT_* are repeated 4  */
+#define	EXTDMA_STAT_SH4_ADDR	0xc4	/*  times too  */
+#define	EXTDMA_STAT_SIZE	0xc8
+#define	EXTDMA_STAT_STATUS	0xcc
+
+
+DEVICE_ACCESS(dreamcast_g2_extdma)
+{
+	struct dreamcast_g2_data *d = (struct dreamcast_g2_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int reg = relative_addr, channel = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  Default read:  */
+	if (writeflag == MEM_READ)
+		odata = d->extdma_reg[relative_addr / sizeof(uint32_t)];
+
+	/*
+	 *  0x5f7800 .. 1f = DMA channel 0
+	 *        20 .. 3f = DMA channel 1
+	 *        40 .. 5f = DMA channel 2
+	 *        60 .. 7f = DMA channel 3
+	 *        80 .. bf = misc magic stuff
+	 *        c0 .. cf = DMA channel 0 status
+	 *        d0 .. df = DMA channel 1 status
+	 *        e0 .. ef = DMA channel 2 status
+	 *        f0 .. ff = DMA channel 3 status
+	 */
+	if (reg < 0x7f) {
+		channel = (reg >> 5) & 3;
+		reg &= 0x1f;
+	}
+	if (reg >= 0xc0 && reg < 0xff) {
+		channel = (reg >> 4) & 3;
+		reg = 0xc0 + (reg & 0xf);
+	}
+
+	switch (reg) {
+
+	case EXTDMA_CTRL_EXT_ADDR:
+		if (writeflag == MEM_WRITE) {
+			debug("[ dreamcast_g2_extdma: write to channel %i:"
+			    " EXT_ADDR = 0x%08x ]\n", channel, (int) idata);
+		}
+		break;
+
+	case EXTDMA_CTRL_SH4_ADDR:
+		if (writeflag == MEM_WRITE) {
+			debug("[ dreamcast_g2_extdma: write to channel %i:"
+			    " SH4_ADDR = 0x%08x ]\n", channel, (int) idata);
+		}
+		break;
+
+	case EXTDMA_CTRL_SIZE:
+		if (writeflag == MEM_WRITE) {
+			debug("[ dreamcast_g2_extdma: write to channel %i:"
+			    " SIZE = 0x%08x ]\n", channel, (int) idata);
+		}
+		break;
+
+	case EXTDMA_CTRL_DIR:
+		if (writeflag == MEM_WRITE) {
+			debug("[ dreamcast_g2_extdma: write to channel %i:"
+			    " DIR = 0x%08x ]\n", channel, (int) idata);
+		}
+		break;
+
+	case EXTDMA_CTRL_MODE:
+		if (writeflag == MEM_WRITE) {
+			debug("[ dreamcast_g2_extdma: write to channel %i:"
+			    " MODE = 0x%08x ]\n", channel, (int) idata);
+		}
+		break;
+
+	case EXTDMA_CTRL_CHAN_ENABLE:
+		if (writeflag == MEM_WRITE) {
+			debug("[ dreamcast_g2_extdma: write to channel %i:"
+			    " CHAN_ENABLE = 0x%08x ]\n", channel, (int) idata);
+			if (idata != 0) {
+				fatal("EXTDMA_CTRL_CHAN_ENABLE: todo\n");
+				exit(1);
+			}
+		}
+		break;
+
+	case EXTDMA_CTRL_XFER_ENABLE:
+		if (writeflag == MEM_WRITE) {
+			debug("[ dreamcast_g2_extdma: write to channel %i:"
+			    " XFER_ENABLE = 0x%08x ]\n", channel, (int) idata);
+			if (idata != 0) {
+				fatal("EXTDMA_CTRL_XFER_ENABLE: todo\n");
+				exit(1);
+			}
+		}
+		break;
+
+	case EXTDMA_CTRL_STATUS:
+		if (writeflag == MEM_WRITE) {
+			debug("[ dreamcast_g2_extdma: write to channel %i:"
+			    " STATUS = 0x%08x ]\n", channel, (int) idata);
+			if (idata != 0) {
+				fatal("[ dreamcast_g2_extdma: write to channel %i:"
+				    " STATUS = 0x%08x: TODO (start transfer?) ]\n",
+				    channel, (int) idata);
+				exit(1);
+			}
+		}
+		break;
+
+	case EXTDMA_WAITSTATE:
+		break;
+
+	case 0x94:
+	case 0x98:
+	case 0x9c:
+	case 0xa0:
+	case 0xa4:
+	case 0xa8:
+	case 0xac:
+	case 0xb0:
+	case 0xb4:
+	case 0xb8:
+		/*  TODO  */
+		break;
+
+	case EXTDMA_MAGIC:
+		if (writeflag == MEM_WRITE) {
+			if (idata != EXTDMA_MAGIC_VALUE	&&
+			    idata != EXTDMA_MAGIC_VALUE_ROM) {
+				fatal("Unimplemented g2 extdma magic "
+				    "vaule 0x%x\n", (int) idata);
+				exit(1);
+			}
+		}
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ dreamcast_g2_extdma: read from addr 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ dreamcast_g2_extdma: write to addr 0x%x: "
+			    "0x%x ]\n", (int)relative_addr, (int)idata);
+		}
+
+		exit(1);
+	}
+
+	/*  Default write:  */
+	if (writeflag == MEM_WRITE)
+		d->extdma_reg[relative_addr / sizeof(uint32_t)] = idata;
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(dreamcast_g2_misc)
+{
+	struct dreamcast_g2_data *d = (struct dreamcast_g2_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  Default read:  */
+	if (writeflag == MEM_READ)
+		odata = d->misc_reg[relative_addr / sizeof(uint32_t)];
+
+	switch (relative_addr) {
+
+	case 0x64:
+		/*  Writing 0x1fffff to 0x5f74e4 resets a disabled GD-ROM drive?  */
+		if (writeflag != MEM_WRITE || idata != 0x1fffff) {
+			fatal("[ dreamcast_g2_misc: unimplemented 0xe4 ]\n");
+			exit(1);
+		}
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			debug("[ dreamcast_g2_misc: read from addr 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			debug("[ dreamcast_g2_misc: write to addr 0x%x: "
+			    "0x%x ]\n", (int)relative_addr, (int)idata);
+		}
+
+		/*  exit(1);  */
+	}
+
+	/*  Default write:  */
+	if (writeflag == MEM_WRITE)
+		d->misc_reg[relative_addr / sizeof(uint32_t)] = idata;
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(dreamcast_g2)
+{
+	struct machine *machine = devinit->machine;
+	struct dreamcast_g2_data *d;
+
+	CHECK_ALLOCATION(d = (struct dreamcast_g2_data *)
+	    malloc(sizeof(struct dreamcast_g2_data)));
+	memset(d, 0, sizeof(struct dreamcast_g2_data));
+
+	memory_device_register(machine->memory, "g2_misc", 0x005f7480,
+	    0x80, dev_dreamcast_g2_misc_access, d, DM_DEFAULT, NULL);
+
+	memory_device_register(machine->memory, "g2_extdma", 0x005f7800,
+	    0x100, dev_dreamcast_g2_extdma_access, d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_dreamcast_g2.cc gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_g2.cc
--- gxemul-0.6.2/src/devices/dev_dreamcast_g2.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_g2.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,302 +0,0 @@
-/*
- *  Copyright (C) 2006-2011  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Dreamcast G2 bus
- *
- *  Register offsets are from KOS, NetBSD sources, etc.
- *
- *  TODO:
- *	Figure out what all these registers do!
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#ifdef UNSTABLE_DEVEL
-// #define debug fatal
-#endif
-
-#define	NREGS_EXT_DMA		(0x80/sizeof(uint32_t))
-#define	NREGS_MISC		(0x80/sizeof(uint32_t))
-
-struct dreamcast_g2_data {
-	uint32_t	extdma_reg[NREGS_EXT_DMA];
-	uint32_t	misc_reg[NREGS_MISC];
-};
-
-
-/*
- *  External DMA:  4 channels
- *
- *  Note: Addresses and sizes must be 32-byte aligned.
- *  DIR is 0 for CPU to External device, 1 for External to CPU.
- *  MODE should be 5 for transfers to/from the SPU.
- */
-#define	EXTDMA_CTRL_EXT_ADDR	0x00	/*  EXTDMA_CTRL_* are repeated  */
-#define	EXTDMA_CTRL_SH4_ADDR	0x04	/*  4 times (once for each channel)  */
-#define	EXTDMA_CTRL_SIZE	0x08
-#define	EXTDMA_CTRL_DIR		0x0c
-#define	EXTDMA_CTRL_MODE	0x10
-#define	EXTDMA_CTRL_CHAN_ENABLE	0x14	/*  Channel enable  */
-#define	EXTDMA_CTRL_XFER_ENABLE	0x18	/*  Transfer enable  */
-#define	EXTDMA_CTRL_STATUS	0x1c	/*  Transfer status  */
-
-#define	EXTDMA_WAITSTATE	0x90
-#define	EXTDMA_MAGIC		0xbc
-#define	EXTDMA_MAGIC_VALUE	    0x4659404f
-#define	EXTDMA_MAGIC_VALUE_ROM	    0x46597f00
-
-#define	EXTDMA_STAT_EXT_ADDR	0xc0	/*  EXTDMA_STAT_* are repeated 4  */
-#define	EXTDMA_STAT_SH4_ADDR	0xc4	/*  times too  */
-#define	EXTDMA_STAT_SIZE	0xc8
-#define	EXTDMA_STAT_STATUS	0xcc
-
-
-DEVICE_ACCESS(dreamcast_g2_extdma)
-{
-	struct dreamcast_g2_data *d = (struct dreamcast_g2_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int reg = relative_addr, channel = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  Default read:  */
-	if (writeflag == MEM_READ)
-		odata = d->extdma_reg[relative_addr / sizeof(uint32_t)];
-
-	/*
-	 *  0x5f7800 .. 1f = DMA channel 0
-	 *        20 .. 3f = DMA channel 1
-	 *        40 .. 5f = DMA channel 2
-	 *        60 .. 7f = DMA channel 3
-	 *        80 .. bf = misc magic stuff
-	 *        c0 .. cf = DMA channel 0 status
-	 *        d0 .. df = DMA channel 1 status
-	 *        e0 .. ef = DMA channel 2 status
-	 *        f0 .. ff = DMA channel 3 status
-	 */
-	if (reg < 0x7f) {
-		channel = (reg >> 5) & 3;
-		reg &= 0x1f;
-	}
-	if (reg >= 0xc0 && reg < 0xff) {
-		channel = (reg >> 4) & 3;
-		reg = 0xc0 + (reg & 0xf);
-	}
-
-	switch (reg) {
-
-	case EXTDMA_CTRL_EXT_ADDR:
-		if (writeflag == MEM_WRITE) {
-			debug("[ dreamcast_g2_extdma: write to channel %i:"
-			    " EXT_ADDR = 0x%08x ]\n", channel, (int) idata);
-		}
-		break;
-
-	case EXTDMA_CTRL_SH4_ADDR:
-		if (writeflag == MEM_WRITE) {
-			debug("[ dreamcast_g2_extdma: write to channel %i:"
-			    " SH4_ADDR = 0x%08x ]\n", channel, (int) idata);
-		}
-		break;
-
-	case EXTDMA_CTRL_SIZE:
-		if (writeflag == MEM_WRITE) {
-			debug("[ dreamcast_g2_extdma: write to channel %i:"
-			    " SIZE = 0x%08x ]\n", channel, (int) idata);
-		}
-		break;
-
-	case EXTDMA_CTRL_DIR:
-		if (writeflag == MEM_WRITE) {
-			debug("[ dreamcast_g2_extdma: write to channel %i:"
-			    " DIR = 0x%08x ]\n", channel, (int) idata);
-		}
-		break;
-
-	case EXTDMA_CTRL_MODE:
-		if (writeflag == MEM_WRITE) {
-			debug("[ dreamcast_g2_extdma: write to channel %i:"
-			    " MODE = 0x%08x ]\n", channel, (int) idata);
-		}
-		break;
-
-	case EXTDMA_CTRL_CHAN_ENABLE:
-		if (writeflag == MEM_WRITE) {
-			debug("[ dreamcast_g2_extdma: write to channel %i:"
-			    " CHAN_ENABLE = 0x%08x ]\n", channel, (int) idata);
-			if (idata != 0) {
-				fatal("EXTDMA_CTRL_CHAN_ENABLE: todo\n");
-				exit(1);
-			}
-		}
-		break;
-
-	case EXTDMA_CTRL_XFER_ENABLE:
-		if (writeflag == MEM_WRITE) {
-			debug("[ dreamcast_g2_extdma: write to channel %i:"
-			    " XFER_ENABLE = 0x%08x ]\n", channel, (int) idata);
-			if (idata != 0) {
-				fatal("EXTDMA_CTRL_XFER_ENABLE: todo\n");
-				exit(1);
-			}
-		}
-		break;
-
-	case EXTDMA_CTRL_STATUS:
-		if (writeflag == MEM_WRITE) {
-			debug("[ dreamcast_g2_extdma: write to channel %i:"
-			    " STATUS = 0x%08x ]\n", channel, (int) idata);
-			if (idata != 0) {
-				fatal("[ dreamcast_g2_extdma: write to channel %i:"
-				    " STATUS = 0x%08x: TODO (start transfer?) ]\n",
-				    channel, (int) idata);
-				exit(1);
-			}
-		}
-		break;
-
-	case EXTDMA_WAITSTATE:
-		break;
-
-	case 0x94:
-	case 0x98:
-	case 0x9c:
-	case 0xa0:
-	case 0xa4:
-	case 0xa8:
-	case 0xac:
-	case 0xb0:
-	case 0xb4:
-	case 0xb8:
-		/*  TODO  */
-		break;
-
-	case EXTDMA_MAGIC:
-		if (writeflag == MEM_WRITE) {
-			if (idata != EXTDMA_MAGIC_VALUE	&&
-			    idata != EXTDMA_MAGIC_VALUE_ROM) {
-				fatal("Unimplemented g2 extdma magic "
-				    "vaule 0x%x\n", (int) idata);
-				exit(1);
-			}
-		}
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ dreamcast_g2_extdma: read from addr 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ dreamcast_g2_extdma: write to addr 0x%x: "
-			    "0x%x ]\n", (int)relative_addr, (int)idata);
-		}
-
-		exit(1);
-	}
-
-	/*  Default write:  */
-	if (writeflag == MEM_WRITE)
-		d->extdma_reg[relative_addr / sizeof(uint32_t)] = idata;
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(dreamcast_g2_misc)
-{
-	struct dreamcast_g2_data *d = (struct dreamcast_g2_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  Default read:  */
-	if (writeflag == MEM_READ)
-		odata = d->misc_reg[relative_addr / sizeof(uint32_t)];
-
-	switch (relative_addr) {
-
-	case 0x64:
-		/*  Writing 0x1fffff to 0x5f74e4 resets a disabled GD-ROM drive?  */
-		if (writeflag != MEM_WRITE || idata != 0x1fffff) {
-			fatal("[ dreamcast_g2_misc: unimplemented 0xe4 ]\n");
-			exit(1);
-		}
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			debug("[ dreamcast_g2_misc: read from addr 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			debug("[ dreamcast_g2_misc: write to addr 0x%x: "
-			    "0x%x ]\n", (int)relative_addr, (int)idata);
-		}
-
-		/*  exit(1);  */
-	}
-
-	/*  Default write:  */
-	if (writeflag == MEM_WRITE)
-		d->misc_reg[relative_addr / sizeof(uint32_t)] = idata;
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(dreamcast_g2)
-{
-	struct machine *machine = devinit->machine;
-	struct dreamcast_g2_data *d;
-
-	CHECK_ALLOCATION(d = (struct dreamcast_g2_data *)
-	    malloc(sizeof(struct dreamcast_g2_data)));
-	memset(d, 0, sizeof(struct dreamcast_g2_data));
-
-	memory_device_register(machine->memory, "g2_misc", 0x005f7480,
-	    0x80, dev_dreamcast_g2_misc_access, d, DM_DEFAULT, NULL);
-
-	memory_device_register(machine->memory, "g2_extdma", 0x005f7800,
-	    0x100, dev_dreamcast_g2_extdma_access, d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_dreamcast_gdrom.c gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_gdrom.c
--- gxemul-0.6.2/src/devices/dev_dreamcast_gdrom.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_gdrom.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,540 @@
+/*
+ *  Copyright (C) 2006-2014  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Dreamcast GD-ROM
+ *
+ *  TODO: This is mostly just a dummy so far. It is enough for NetBSD/dreamcast
+ *  to read the GD-ROM (or actually, just a particular Live CD). It shouldn't
+ *  be assumed to work for anything else.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/dreamcast_sysasicvar.h"
+
+
+// #define debug fatal
+
+#define	NREGS_GDROM_DMA		(0x100/sizeof(uint32_t))
+
+struct dreamcast_gdrom_data {
+	// 0x005f7000: GDROM control registers
+	uint8_t		busy;		/*  Busy status  */
+	uint8_t		stat;		/*  Status  */
+	int		cnt;		/*  Data length in bytes  */
+	uint8_t		cond;
+
+	int		cmd_count;
+	uint8_t		cmd[12];
+
+	uint8_t		*data;
+	int		data_len;
+	int		cur_data_offset;
+	int		cur_cnt;
+
+	// 0x005f7400: GDROM DMA
+	uint32_t	dma_reg[NREGS_GDROM_DMA];
+};
+
+/*  Register offsets, from NetBSD:  */
+#define	GDROM_BUSY		0x18
+#define	GDROM_DATA		0x80
+#define	GDROM_REGX		0x84
+#define	GDROM_UNKNOWN_0x88	0x88
+#define	GDROM_STAT		0x8c
+#define	GDROM_CNTLO		0x90
+#define	GDROM_CNTHI		0x94
+#define	GDROM_COND		0x9c
+
+// See the interrupt routine (gdrom_intr()) in NetBSD's dreamcast/dev/gdrom.c:
+#define	COND_DATA_AVAIL		0x08
+
+
+static void alloc_data(struct dreamcast_gdrom_data *d)
+{
+	d->data_len = d->cnt;
+
+	CHECK_ALLOCATION(d->data = (uint8_t *) malloc(d->data_len));
+	memset(d->data, 0, d->data_len);
+}
+
+
+static void handle_command(struct cpu *cpu, struct dreamcast_gdrom_data *d)
+{
+	int64_t sector_nr, sector_count;
+	int i, res;
+
+	debug("[ GDROM cmd: ");
+	for (i=0; i<12; i++)
+		debug("%02x ", d->cmd[i]);
+	debug("(cnt=%i) ]\n", d->cnt);
+
+	if (d->data != NULL)
+		free(d->data);
+	d->data = NULL;
+	d->cur_data_offset = 0;
+	d->cur_cnt = 0;
+
+	switch (d->cmd[0]) {
+
+	case 0x14:
+		/*
+		 *  Read Table-Of-Contents:
+		 *
+		 *  See NetBSD's sys/arch/dreamcast/dev/gdrom.c: gdrom_read_toc().
+		 */
+		if (d->cnt != 408) {
+			fatal("GDROM Read TOC not 408 bytes?\n");
+			exit(1);
+		}
+		alloc_data(d);
+
+		/*
+		 *  From David Brownlee:
+		 *  "TOC from test booted real CD image on NetBSD/dreamcast
+		 *  01000096,41002e4c,ffffffff * 97,01010000,41020000,6100e641,"
+		 *
+		 *  TODO: Perhaps generalize this in the future, to support
+		 *  disk images with multiple TOCs and/or tracks.
+		 */
+		memset(d->data, 0xff, d->cnt); /* Default data to 0xff */
+
+		d->data[0*4]   = 0x10;  /* Track 1 */
+		d->data[0*4+1] = 0;
+		d->data[0*4+2] = 0;
+		d->data[0*4+3] = 0x96;
+
+		d->data[1*4]   = 0x41;  /* Track 2 */
+		d->data[1*4+1] = 0;
+		d->data[1*4+2] = 0x2e;
+		d->data[1*4+3] = 0x4c;
+
+		d->data[99*4]   = 0x01; /*  First track  */
+		d->data[99*4+1] = 0x01;
+		d->data[99*4+2] = 0;
+		d->data[99*4+3] = 0;
+
+		d->data[100*4]   = 0x41; /*  Last track  */
+		d->data[100*4+1] = 0x02;
+		d->data[100*4+2] = 0;
+		d->data[100*4+3] = 0;
+
+		d->data[101*4]   = 0x61; /*  Leadout  */
+		d->data[101*4+1] = 0;
+		d->data[101*4+2] = 0xe6;
+		d->data[101*4+3] = 0x41;
+ 
+		break;
+
+	case 0x30:
+		/*
+		 *  Read sectors:
+		 *
+		 *  See NetBSD's sys/arch/dreamcast/dev/gdrom.c: gdrom_read_sectors().
+		 */
+		if (d->cmd[1] == 0x24) {
+			fatal("GDROM unimplemented data format 0x%02x. Continuing anway.\n", d->cmd[1]);
+		} else if (d->cmd[1] != 0x20) {
+			fatal("GDROM unimplemented data format 0x%02x\n",
+			    d->cmd[1]);
+			exit(1);
+		}
+		sector_nr = d->cmd[2] * 65536 + d->cmd[3] * 256 + d->cmd[4];
+		sector_count = d->cmd[8] * 65536 + d->cmd[9] * 256 + d->cmd[10];
+
+		// NetBSD/dreamcast uses correct length, but the Dreamcast PROM
+		// uses len = 0 (!), but sector count = 7,
+		// which means len = 0x3800. It also sets up DMA to
+		// transfer 0x3800 bytes, so I'm assuming that the
+		// sector count is to be trusted more than the length.
+		if (d->cnt == 0)
+			d->cnt = 2048 * sector_count;
+
+		if (sector_count * 2048 != d->cnt) {
+			fatal("Huh? GDROM data_len=0x%x, but sector_count"
+			    "=0x%x\n", (int)d->cnt, (int)sector_count);
+			exit(1);
+		}
+
+		alloc_data(d);
+
+		// Hm. This is an ugly hack to make a NetBSD/dreamcast
+		// live-cd work. It should be fixed (i.e. removed).
+		// When running with -Q (i.e. no PROM software emulation),
+		// experiments with the Dreamcast PROM can be made instead.
+		if (cpu->machine->prom_emulation) {
+			// printf("sector nr step 1 = %i\n", (int)sector_nr);
+
+			// Hack to get NetBSD/dreamcast to work:
+			// See the variable "openpart_start" in NetBSD's
+			// sys/arch/dreamcast/dev/gdrom.c:
+			sector_nr -= 150;
+
+			// printf("sector nr step 2 = %i\n", (int)sector_nr);
+		} else {
+			// printf("sector nr step 1 = %i\n", (int)sector_nr);
+			sector_nr -= 45150;
+			// printf("sector nr step 2 = %i\n", (int)sector_nr);
+			sector_nr += (diskimage_get_baseoffset(cpu->machine, 0, DISKIMAGE_IDE) / 2048);
+			// printf("sector nr step 3 = %i\n", (int)sector_nr);
+		}
+
+		res = diskimage_access(cpu->machine, 0, DISKIMAGE_IDE,
+		    0, sector_nr * 2048, d->data, d->data_len);
+		if (!res) {
+			fatal("GDROM: diskimage_access failed? TODO\n");
+			free(d->data);
+			d->data = NULL;
+		}
+
+		/* {
+			printf("(Dump of GDROM sector %i: \"", (int)sector_nr);
+			for (int k = 0; k < 256; ++k)
+				printf("%c", d->data[k] >= 32 ? d->data[k] : '.');
+			printf("\")\n");
+		} */
+
+		break;
+
+	case 0x70:
+		/*
+		 *  Mount:
+		 *
+		 *  See NetBSD's sys/arch/dreamcast/dev/gdrom.c: gdrom_mount_disk().
+		 */
+
+		// Note/TODO: This is ignored for now.
+		break;
+
+	default:fatal("GDROM handle_command: unimplemented command 0x%02x"
+		    "\n", d->cmd[0]);
+		exit(1);
+	}
+
+	// Any resulting data? Then set COND_DATA_AVAIL. Otherwise, clear
+	// that bit, and set count to zero.
+	if (d->data != NULL) {
+		d->cond |= COND_DATA_AVAIL;
+	} else {
+		d->cnt = 0;
+		d->cond &= ~COND_DATA_AVAIL;
+	}
+
+	// NetBSD seems to sometimes request 32 sectors (2048 bytes each), i.e.
+	// 65536 bytes. That is represented as count = 0x0000 (when NetBSD reads
+	// from the CNTHI and CNTLO registers). That does not work very well.
+	// This is a hack/workaround for that.
+	if (d->cnt == 65536)
+		d->cnt = 32768;
+
+	SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_GDROM);
+}
+
+void dreamcast_gdrom_update_stat(struct cpu *cpu, struct dreamcast_gdrom_data *d)
+{
+	// See NetBSD's gdrom.c.
+	d->stat = 6;
+
+	if (diskimage_exist(cpu->machine, 0, DISKIMAGE_IDE)) {
+		d->stat = 0;
+	}
+}
+
+
+DEVICE_ACCESS(dreamcast_gdrom)
+{
+	struct dreamcast_gdrom_data *d = (struct dreamcast_gdrom_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case GDROM_BUSY:
+		if (writeflag == MEM_READ) {
+			odata = d->busy;
+		} else {
+			// fatal("[ Write to GDROM_BUSY: 0x%08x ]\n", (int)idata);
+			// I'm assuming that writing bits to BUSY clears them.
+			d->busy &= ~idata;
+		}
+		break;
+
+	case GDROM_DATA:
+		if (len != sizeof(uint16_t)) {
+			fatal("Non-16bit GDROM data access? TODO\n");
+			exit(1);
+		}
+
+		if (writeflag == MEM_READ) {
+			if (!(d->cond & COND_DATA_AVAIL)) {
+				fatal("Read from GDROM_DATA when no data"
+				    " is available? TODO\n");
+				exit(1);
+			}
+
+			if (d->cur_data_offset < d->data_len) {
+				odata = d->data[d->cur_data_offset ++];
+				odata |= (d->data[d->cur_data_offset ++] << 8);
+				d->cur_cnt += sizeof(uint16_t);
+				if (d->cur_cnt >= d->cnt) {
+					if (d->cur_data_offset >= d->data_len) {
+						d->cond &= ~COND_DATA_AVAIL;
+					} else {
+						d->cnt = d->data_len - d->cur_data_offset;
+						d->cur_cnt = 0;
+					}
+
+					SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_GDROM);
+				}
+			} else {
+				fatal("Read too much from GDROM_DATA\n");
+				exit(1);
+			}
+		} else {
+			if (d->busy & 0x08) {
+				if (d->cmd_count >= 12) {
+					fatal("Too much GDROM_DATA?\n");
+					exit(1);
+				}
+				/*  Add data to cmd:  */
+				d->cmd[d->cmd_count++] = idata;
+				d->cmd[d->cmd_count++] = idata >> 8;
+				if (d->cmd_count == 12) {
+					d->busy &= ~0x08;
+					handle_command(cpu, d);
+				}
+			} else {
+				fatal("Write to GDROM_DATA, but not waiting"
+				    " for data?\n");
+				exit(1);
+			}
+		}
+		break;
+
+	case GDROM_REGX:
+		if (writeflag == MEM_READ) {
+			debug("[ Read to GDROM_REGX? ]\n");
+		} else {
+			/*  NetBSD/dreamcast writes 0 here.  */
+			if (idata != 0)
+				debug("[ Write 0x%x to GDROM_REGX? ]\n", (int)idata);
+		}
+		break;
+
+	case GDROM_UNKNOWN_0x88:
+		if (writeflag == MEM_READ) {
+			fatal("Read from GDROM_UNKNOWN_0x88?\n");
+			// exit(1);
+		} else {
+			if (idata != 0xb) {
+				fatal("[ Write to GDROM_UNKNOWN_0x88: TODO ]\n");
+				exit(1);
+			}
+		}
+		break;
+
+	case GDROM_STAT:
+		if (writeflag == MEM_READ) {
+			dreamcast_gdrom_update_stat(cpu, d);
+			odata = d->stat;
+		} else {
+			fatal("[ Write to GDROM_STAT? ]\n");
+/*			exit(1);  */
+		}
+		break;
+
+	case GDROM_CNTLO:
+		if (writeflag == MEM_READ) {
+			odata = d->cnt & 0xff;
+		} else {
+			d->cnt = (d->cnt & 0xff00) | (idata & 0xff);
+		}
+		break;
+
+	case GDROM_CNTHI:
+		if (writeflag == MEM_READ) {
+			odata = (d->cnt >> 8) & 0xff;
+		} else {
+			d->cnt = (d->cnt & 0x00ff) | ((idata & 0xff) << 8);
+		}
+		break;
+
+	case GDROM_COND:
+		if (writeflag == MEM_READ) {
+			odata = d->cond;
+		} else {
+			d->cond = idata;
+
+			/*
+			 *  NetBSD/dreamcast writes 0xa0 to GDROM_COND to
+			 *  start a command. See gdrom_do_command() in NetBSD's
+			 *  sys/arch/dreamcast/dev/gdrom.c.
+			 *
+			 *  Before sending anything, NetBSD expects:
+			 *   o) the lowest 4 bits of STAT to not be 6.
+			 *
+			 *  After writing 0xa0 to GDROM_COND, NetBSD expects:
+			 *   o) (BUSY & 0x88) to be 0x08.
+			 *
+			 *  NetBSD then sends 6 16-bit data words to GDROM_DATA.
+			 */
+			if (idata == 0xa0) {
+				d->stat = 0;	/*  TODO  */
+				d->busy |= 0x08;
+				d->cmd_count = 0;
+			} else if (idata == 0xef) {
+				debug("dreamcast_gdrom: ROM: TODO\n");
+				SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_GDROM);
+			} else {
+				fatal("dreamcast_gdrom: unimplemented "
+				    "GDROM_COND = 0x%02x\n", (int)idata);
+				exit(1);
+			}
+		}
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ dreamcast_gdrom: read from addr 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ dreamcast_gdrom: write to addr 0x%x: 0x%x ]\n",
+			    (int)relative_addr, (int)idata);
+		}
+
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(dreamcast_gdrom_dma)
+{
+	struct dreamcast_gdrom_data *d = (struct dreamcast_gdrom_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  Default read:  */
+	if (writeflag == MEM_READ)
+		odata = d->dma_reg[relative_addr / sizeof(uint32_t)];
+
+	switch (relative_addr) {
+
+	case 0x04:	// destination address? e.g. 0x8c008000
+	case 0x08:	// DMA length in bytes? e.g. 0x3800
+	case 0x0c:	// count? e.g. 1
+	case 0x14:	// "enable"?
+		break;
+
+	case 0x18:
+		// GDROM DMA start?
+		if (idata != 0) {
+			if (d->dma_reg[0x0c / sizeof(uint32_t)] == 1 &&
+			    d->dma_reg[0x14 / sizeof(uint32_t)] == 1) {
+				// GDROM DMA transfer.
+				uint32_t dst = d->dma_reg[0x04 / sizeof(uint32_t)];
+				int length = d->dma_reg[0x08 / sizeof(uint32_t)];
+				fatal("[ dreamcast_gdrom_dma: Transfering %i bytes to 0x%08" PRIx32" ]\n", length, dst);
+
+				if (d->data == NULL) {
+					fatal("dreamcast_gdrom_dma: DMA transfer but d->data is NULL. TODO\n");
+					exit(1);
+				}
+
+				dst &= 0x0fffffff;	// 0x8c008000 => 0x0c008000
+				cpu->memory_rw(cpu, cpu->mem, dst,
+				    d->data, d->data_len, MEM_WRITE, PHYSICAL);
+
+				SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_GDROM_DMA);
+
+				idata = 0;
+			} else {
+				fatal("Unimplemented GDROM DMA start? TODO\n");
+				fatal("  %08x\n", (int) d->dma_reg[4 / sizeof(uint32_t)]);
+				fatal("  %08x\n", (int) d->dma_reg[8 / sizeof(uint32_t)]);
+				fatal("  %08x\n", (int) d->dma_reg[0xc / sizeof(uint32_t)]);
+				fatal("  %08x\n", (int) d->dma_reg[0x14 / sizeof(uint32_t)]);
+				exit(1);
+			}
+		}
+		break;			
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ dreamcast_gdrom_dma: read from addr 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ dreamcast_gdrom_dma: write to addr 0x%x: "
+			    "0x%x ]\n", (int)relative_addr, (int)idata);
+		}
+
+		exit(1);
+	}
+
+	/*  Default write:  */
+	if (writeflag == MEM_WRITE)
+		d->dma_reg[relative_addr / sizeof(uint32_t)] = idata;
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(dreamcast_gdrom)
+{
+	struct dreamcast_gdrom_data *d;
+
+	CHECK_ALLOCATION(d = (struct dreamcast_gdrom_data *) malloc(sizeof(struct dreamcast_gdrom_data)));
+	memset(d, 0, sizeof(struct dreamcast_gdrom_data));
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    0x005f7000, 0x100, dev_dreamcast_gdrom_access, d,
+	    DM_DEFAULT, NULL);
+
+	memory_device_register(devinit->machine->memory, "gdrom_dma", 0x005f7400,
+	    0x80, dev_dreamcast_gdrom_dma_access, d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_dreamcast_gdrom.cc gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_gdrom.cc
--- gxemul-0.6.2/src/devices/dev_dreamcast_gdrom.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_gdrom.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,540 +0,0 @@
-/*
- *  Copyright (C) 2006-2014  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Dreamcast GD-ROM
- *
- *  TODO: This is mostly just a dummy so far. It is enough for NetBSD/dreamcast
- *  to read the GD-ROM (or actually, just a particular Live CD). It shouldn't
- *  be assumed to work for anything else.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/dreamcast_sysasicvar.h"
-
-
-// #define debug fatal
-
-#define	NREGS_GDROM_DMA		(0x100/sizeof(uint32_t))
-
-struct dreamcast_gdrom_data {
-	// 0x005f7000: GDROM control registers
-	uint8_t		busy;		/*  Busy status  */
-	uint8_t		stat;		/*  Status  */
-	int		cnt;		/*  Data length in bytes  */
-	uint8_t		cond;
-
-	int		cmd_count;
-	uint8_t		cmd[12];
-
-	uint8_t		*data;
-	int		data_len;
-	int		cur_data_offset;
-	int		cur_cnt;
-
-	// 0x005f7400: GDROM DMA
-	uint32_t	dma_reg[NREGS_GDROM_DMA];
-};
-
-/*  Register offsets, from NetBSD:  */
-#define	GDROM_BUSY		0x18
-#define	GDROM_DATA		0x80
-#define	GDROM_REGX		0x84
-#define	GDROM_UNKNOWN_0x88	0x88
-#define	GDROM_STAT		0x8c
-#define	GDROM_CNTLO		0x90
-#define	GDROM_CNTHI		0x94
-#define	GDROM_COND		0x9c
-
-// See the interrupt routine (gdrom_intr()) in NetBSD's dreamcast/dev/gdrom.c:
-#define	COND_DATA_AVAIL		0x08
-
-
-static void alloc_data(struct dreamcast_gdrom_data *d)
-{
-	d->data_len = d->cnt;
-
-	CHECK_ALLOCATION(d->data = (uint8_t *) malloc(d->data_len));
-	memset(d->data, 0, d->data_len);
-}
-
-
-static void handle_command(struct cpu *cpu, struct dreamcast_gdrom_data *d)
-{
-	int64_t sector_nr, sector_count;
-	int i, res;
-
-	debug("[ GDROM cmd: ");
-	for (i=0; i<12; i++)
-		debug("%02x ", d->cmd[i]);
-	debug("(cnt=%i) ]\n", d->cnt);
-
-	if (d->data != NULL)
-		free(d->data);
-	d->data = NULL;
-	d->cur_data_offset = 0;
-	d->cur_cnt = 0;
-
-	switch (d->cmd[0]) {
-
-	case 0x14:
-		/*
-		 *  Read Table-Of-Contents:
-		 *
-		 *  See NetBSD's sys/arch/dreamcast/dev/gdrom.c: gdrom_read_toc().
-		 */
-		if (d->cnt != 408) {
-			fatal("GDROM Read TOC not 408 bytes?\n");
-			exit(1);
-		}
-		alloc_data(d);
-
-		/*
-		 *  From David Brownlee:
-		 *  "TOC from test booted real CD image on NetBSD/dreamcast
-		 *  01000096,41002e4c,ffffffff * 97,01010000,41020000,6100e641,"
-		 *
-		 *  TODO: Perhaps generalize this in the future, to support
-		 *  disk images with multiple TOCs and/or tracks.
-		 */
-		memset(d->data, 0xff, d->cnt); /* Default data to 0xff */
-
-		d->data[0*4]   = 0x10;  /* Track 1 */
-		d->data[0*4+1] = 0;
-		d->data[0*4+2] = 0;
-		d->data[0*4+3] = 0x96;
-
-		d->data[1*4]   = 0x41;  /* Track 2 */
-		d->data[1*4+1] = 0;
-		d->data[1*4+2] = 0x2e;
-		d->data[1*4+3] = 0x4c;
-
-		d->data[99*4]   = 0x01; /*  First track  */
-		d->data[99*4+1] = 0x01;
-		d->data[99*4+2] = 0;
-		d->data[99*4+3] = 0;
-
-		d->data[100*4]   = 0x41; /*  Last track  */
-		d->data[100*4+1] = 0x02;
-		d->data[100*4+2] = 0;
-		d->data[100*4+3] = 0;
-
-		d->data[101*4]   = 0x61; /*  Leadout  */
-		d->data[101*4+1] = 0;
-		d->data[101*4+2] = 0xe6;
-		d->data[101*4+3] = 0x41;
- 
-		break;
-
-	case 0x30:
-		/*
-		 *  Read sectors:
-		 *
-		 *  See NetBSD's sys/arch/dreamcast/dev/gdrom.c: gdrom_read_sectors().
-		 */
-		if (d->cmd[1] == 0x24) {
-			fatal("GDROM unimplemented data format 0x%02x. Continuing anway.\n", d->cmd[1]);
-		} else if (d->cmd[1] != 0x20) {
-			fatal("GDROM unimplemented data format 0x%02x\n",
-			    d->cmd[1]);
-			exit(1);
-		}
-		sector_nr = d->cmd[2] * 65536 + d->cmd[3] * 256 + d->cmd[4];
-		sector_count = d->cmd[8] * 65536 + d->cmd[9] * 256 + d->cmd[10];
-
-		// NetBSD/dreamcast uses correct length, but the Dreamcast PROM
-		// uses len = 0 (!), but sector count = 7,
-		// which means len = 0x3800. It also sets up DMA to
-		// transfer 0x3800 bytes, so I'm assuming that the
-		// sector count is to be trusted more than the length.
-		if (d->cnt == 0)
-			d->cnt = 2048 * sector_count;
-
-		if (sector_count * 2048 != d->cnt) {
-			fatal("Huh? GDROM data_len=0x%x, but sector_count"
-			    "=0x%x\n", (int)d->cnt, (int)sector_count);
-			exit(1);
-		}
-
-		alloc_data(d);
-
-		// Hm. This is an ugly hack to make a NetBSD/dreamcast
-		// live-cd work. It should be fixed (i.e. removed).
-		// When running with -Q (i.e. no PROM software emulation),
-		// experiments with the Dreamcast PROM can be made instead.
-		if (cpu->machine->prom_emulation) {
-			// printf("sector nr step 1 = %i\n", (int)sector_nr);
-
-			// Hack to get NetBSD/dreamcast to work:
-			// See the variable "openpart_start" in NetBSD's
-			// sys/arch/dreamcast/dev/gdrom.c:
-			sector_nr -= 150;
-
-			// printf("sector nr step 2 = %i\n", (int)sector_nr);
-		} else {
-			// printf("sector nr step 1 = %i\n", (int)sector_nr);
-			sector_nr -= 45150;
-			// printf("sector nr step 2 = %i\n", (int)sector_nr);
-			sector_nr += (diskimage_get_baseoffset(cpu->machine, 0, DISKIMAGE_IDE) / 2048);
-			// printf("sector nr step 3 = %i\n", (int)sector_nr);
-		}
-
-		res = diskimage_access(cpu->machine, 0, DISKIMAGE_IDE,
-		    0, sector_nr * 2048, d->data, d->data_len);
-		if (!res) {
-			fatal("GDROM: diskimage_access failed? TODO\n");
-			free(d->data);
-			d->data = NULL;
-		}
-
-		/* {
-			printf("(Dump of GDROM sector %i: \"", (int)sector_nr);
-			for (int k = 0; k < 256; ++k)
-				printf("%c", d->data[k] >= 32 ? d->data[k] : '.');
-			printf("\")\n");
-		} */
-
-		break;
-
-	case 0x70:
-		/*
-		 *  Mount:
-		 *
-		 *  See NetBSD's sys/arch/dreamcast/dev/gdrom.c: gdrom_mount_disk().
-		 */
-
-		// Note/TODO: This is ignored for now.
-		break;
-
-	default:fatal("GDROM handle_command: unimplemented command 0x%02x"
-		    "\n", d->cmd[0]);
-		exit(1);
-	}
-
-	// Any resulting data? Then set COND_DATA_AVAIL. Otherwise, clear
-	// that bit, and set count to zero.
-	if (d->data != NULL) {
-		d->cond |= COND_DATA_AVAIL;
-	} else {
-		d->cnt = 0;
-		d->cond &= ~COND_DATA_AVAIL;
-	}
-
-	// NetBSD seems to sometimes request 32 sectors (2048 bytes each), i.e.
-	// 65536 bytes. That is represented as count = 0x0000 (when NetBSD reads
-	// from the CNTHI and CNTLO registers). That does not work very well.
-	// This is a hack/workaround for that.
-	if (d->cnt == 65536)
-		d->cnt = 32768;
-
-	SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_GDROM);
-}
-
-void dreamcast_gdrom_update_stat(struct cpu *cpu, struct dreamcast_gdrom_data *d)
-{
-	// See NetBSD's gdrom.c.
-	d->stat = 6;
-
-	if (diskimage_exist(cpu->machine, 0, DISKIMAGE_IDE)) {
-		d->stat = 0;
-	}
-}
-
-
-DEVICE_ACCESS(dreamcast_gdrom)
-{
-	struct dreamcast_gdrom_data *d = (struct dreamcast_gdrom_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case GDROM_BUSY:
-		if (writeflag == MEM_READ) {
-			odata = d->busy;
-		} else {
-			// fatal("[ Write to GDROM_BUSY: 0x%08x ]\n", (int)idata);
-			// I'm assuming that writing bits to BUSY clears them.
-			d->busy &= ~idata;
-		}
-		break;
-
-	case GDROM_DATA:
-		if (len != sizeof(uint16_t)) {
-			fatal("Non-16bit GDROM data access? TODO\n");
-			exit(1);
-		}
-
-		if (writeflag == MEM_READ) {
-			if (!(d->cond & COND_DATA_AVAIL)) {
-				fatal("Read from GDROM_DATA when no data"
-				    " is available? TODO\n");
-				exit(1);
-			}
-
-			if (d->cur_data_offset < d->data_len) {
-				odata = d->data[d->cur_data_offset ++];
-				odata |= (d->data[d->cur_data_offset ++] << 8);
-				d->cur_cnt += sizeof(uint16_t);
-				if (d->cur_cnt >= d->cnt) {
-					if (d->cur_data_offset >= d->data_len) {
-						d->cond &= ~COND_DATA_AVAIL;
-					} else {
-						d->cnt = d->data_len - d->cur_data_offset;
-						d->cur_cnt = 0;
-					}
-
-					SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_GDROM);
-				}
-			} else {
-				fatal("Read too much from GDROM_DATA\n");
-				exit(1);
-			}
-		} else {
-			if (d->busy & 0x08) {
-				if (d->cmd_count >= 12) {
-					fatal("Too much GDROM_DATA?\n");
-					exit(1);
-				}
-				/*  Add data to cmd:  */
-				d->cmd[d->cmd_count++] = idata;
-				d->cmd[d->cmd_count++] = idata >> 8;
-				if (d->cmd_count == 12) {
-					d->busy &= ~0x08;
-					handle_command(cpu, d);
-				}
-			} else {
-				fatal("Write to GDROM_DATA, but not waiting"
-				    " for data?\n");
-				exit(1);
-			}
-		}
-		break;
-
-	case GDROM_REGX:
-		if (writeflag == MEM_READ) {
-			debug("[ Read to GDROM_REGX? ]\n");
-		} else {
-			/*  NetBSD/dreamcast writes 0 here.  */
-			if (idata != 0)
-				debug("[ Write 0x%x to GDROM_REGX? ]\n", (int)idata);
-		}
-		break;
-
-	case GDROM_UNKNOWN_0x88:
-		if (writeflag == MEM_READ) {
-			fatal("Read from GDROM_UNKNOWN_0x88?\n");
-			// exit(1);
-		} else {
-			if (idata != 0xb) {
-				fatal("[ Write to GDROM_UNKNOWN_0x88: TODO ]\n");
-				exit(1);
-			}
-		}
-		break;
-
-	case GDROM_STAT:
-		if (writeflag == MEM_READ) {
-			dreamcast_gdrom_update_stat(cpu, d);
-			odata = d->stat;
-		} else {
-			fatal("[ Write to GDROM_STAT? ]\n");
-/*			exit(1);  */
-		}
-		break;
-
-	case GDROM_CNTLO:
-		if (writeflag == MEM_READ) {
-			odata = d->cnt & 0xff;
-		} else {
-			d->cnt = (d->cnt & 0xff00) | (idata & 0xff);
-		}
-		break;
-
-	case GDROM_CNTHI:
-		if (writeflag == MEM_READ) {
-			odata = (d->cnt >> 8) & 0xff;
-		} else {
-			d->cnt = (d->cnt & 0x00ff) | ((idata & 0xff) << 8);
-		}
-		break;
-
-	case GDROM_COND:
-		if (writeflag == MEM_READ) {
-			odata = d->cond;
-		} else {
-			d->cond = idata;
-
-			/*
-			 *  NetBSD/dreamcast writes 0xa0 to GDROM_COND to
-			 *  start a command. See gdrom_do_command() in NetBSD's
-			 *  sys/arch/dreamcast/dev/gdrom.c.
-			 *
-			 *  Before sending anything, NetBSD expects:
-			 *   o) the lowest 4 bits of STAT to not be 6.
-			 *
-			 *  After writing 0xa0 to GDROM_COND, NetBSD expects:
-			 *   o) (BUSY & 0x88) to be 0x08.
-			 *
-			 *  NetBSD then sends 6 16-bit data words to GDROM_DATA.
-			 */
-			if (idata == 0xa0) {
-				d->stat = 0;	/*  TODO  */
-				d->busy |= 0x08;
-				d->cmd_count = 0;
-			} else if (idata == 0xef) {
-				debug("dreamcast_gdrom: ROM: TODO\n");
-				SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_GDROM);
-			} else {
-				fatal("dreamcast_gdrom: unimplemented "
-				    "GDROM_COND = 0x%02x\n", (int)idata);
-				exit(1);
-			}
-		}
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ dreamcast_gdrom: read from addr 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ dreamcast_gdrom: write to addr 0x%x: 0x%x ]\n",
-			    (int)relative_addr, (int)idata);
-		}
-
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(dreamcast_gdrom_dma)
-{
-	struct dreamcast_gdrom_data *d = (struct dreamcast_gdrom_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  Default read:  */
-	if (writeflag == MEM_READ)
-		odata = d->dma_reg[relative_addr / sizeof(uint32_t)];
-
-	switch (relative_addr) {
-
-	case 0x04:	// destination address? e.g. 0x8c008000
-	case 0x08:	// DMA length in bytes? e.g. 0x3800
-	case 0x0c:	// count? e.g. 1
-	case 0x14:	// "enable"?
-		break;
-
-	case 0x18:
-		// GDROM DMA start?
-		if (idata != 0) {
-			if (d->dma_reg[0x0c / sizeof(uint32_t)] == 1 &&
-			    d->dma_reg[0x14 / sizeof(uint32_t)] == 1) {
-				// GDROM DMA transfer.
-				uint32_t dst = d->dma_reg[0x04 / sizeof(uint32_t)];
-				int length = d->dma_reg[0x08 / sizeof(uint32_t)];
-				fatal("[ dreamcast_gdrom_dma: Transfering %i bytes to 0x%08" PRIx32" ]\n", length, dst);
-
-				if (d->data == NULL) {
-					fatal("dreamcast_gdrom_dma: DMA transfer but d->data is NULL. TODO\n");
-					exit(1);
-				}
-
-				dst &= 0x0fffffff;	// 0x8c008000 => 0x0c008000
-				cpu->memory_rw(cpu, cpu->mem, dst,
-				    d->data, d->data_len, MEM_WRITE, PHYSICAL);
-
-				SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_GDROM_DMA);
-
-				idata = 0;
-			} else {
-				fatal("Unimplemented GDROM DMA start? TODO\n");
-				fatal("  %08x\n", (int) d->dma_reg[4 / sizeof(uint32_t)]);
-				fatal("  %08x\n", (int) d->dma_reg[8 / sizeof(uint32_t)]);
-				fatal("  %08x\n", (int) d->dma_reg[0xc / sizeof(uint32_t)]);
-				fatal("  %08x\n", (int) d->dma_reg[0x14 / sizeof(uint32_t)]);
-				exit(1);
-			}
-		}
-		break;			
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ dreamcast_gdrom_dma: read from addr 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ dreamcast_gdrom_dma: write to addr 0x%x: "
-			    "0x%x ]\n", (int)relative_addr, (int)idata);
-		}
-
-		exit(1);
-	}
-
-	/*  Default write:  */
-	if (writeflag == MEM_WRITE)
-		d->dma_reg[relative_addr / sizeof(uint32_t)] = idata;
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(dreamcast_gdrom)
-{
-	struct dreamcast_gdrom_data *d;
-
-	CHECK_ALLOCATION(d = (struct dreamcast_gdrom_data *) malloc(sizeof(struct dreamcast_gdrom_data)));
-	memset(d, 0, sizeof(struct dreamcast_gdrom_data));
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    0x005f7000, 0x100, dev_dreamcast_gdrom_access, d,
-	    DM_DEFAULT, NULL);
-
-	memory_device_register(devinit->machine->memory, "gdrom_dma", 0x005f7400,
-	    0x80, dev_dreamcast_gdrom_dma_access, d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_dreamcast_maple.c gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_maple.c
--- gxemul-0.6.2/src/devices/dev_dreamcast_maple.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_maple.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,668 @@
+/*
+ *  Copyright (C) 2006-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Dreamcast Maple bus controller
+ *
+ *  The Maple bus has 4 ports (A-D), and each port has up to 6 possible "units"
+ *  (where unit 0 is the main unit). Communication is done using DMA; each
+ *  DMA transfer sends one or more requests, and for each of these requests
+ *  a response is generated (or a timeout if there was no device at the
+ *  specific port).
+ *
+ *  See Marcus Comstedt's page (http://mc.pp.se/dc/maplebus.html) for more
+ *  details about the DMA request/responses.
+ *
+ *
+ *  TODO:
+ *	Unit numbers / IDs for real Maple devices.
+ *	The Controller (up/down/left/right, buttons, etc).
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/dreamcast_maple.h"
+#include "thirdparty/dreamcast_sysasicvar.h"
+
+
+// #define debug fatal
+
+#define	N_MAPLE_PORTS		4
+
+#define	MAX_CHARS		8192
+#define	MAX_CONTROLLER_DATA	4096
+
+#define	MAPLE_TICK_SHIFT	17
+
+struct maple_device {
+	struct maple_devinfo devinfo;
+};
+
+struct dreamcast_maple_data {
+	/*  Registers:  */
+	uint32_t	dmaaddr;
+	int		enable;
+	int		timeout;
+
+	/*  Attached devices:  */
+	struct maple_device *device[N_MAPLE_PORTS];
+
+	/*  For keyboard/controller input:  */
+	int		console_handle;
+	uint8_t		char_queue[MAX_CHARS];
+	uint16_t	controller_queue[MAX_CONTROLLER_DATA];
+	int		char_queue_head, char_queue_tail;
+	int		controller_queue_head, controller_queue_tail;
+};
+
+
+/*
+ *  Maple devices:
+ *
+ *  TODO: Figure out strings and numbers of _real_ Maple devices.
+ */
+struct maple_device maple_device_controller = {
+	{
+		BE32_TO_HOST(MAPLE_FUNC(MAPLE_FN_CONTROLLER)),	/*  di_func  */
+		{ LE32_TO_HOST(0xfe060f00),0,0 },/* di_function_data[3]  */
+		0xff,				/*  di_area_code  */
+		0,				/*  di_connector_direction  */
+		"Dreamcast Controller",		/*  di_product_name  */
+		"di_product_license",		/*  di_product_license  */
+		LE16_TO_HOST(0x01ae),		/*  di_standby_power  */
+		LE16_TO_HOST(0x01f4)		/*  di_max_power  */
+	}
+};
+struct maple_device maple_device_keyboard = {
+	{
+		BE32_TO_HOST(MAPLE_FUNC(MAPLE_FN_KEYBOARD)),/*  di_func  */
+		{ LE32_TO_HOST(2),0,0 },	/*  di_function_data[3]  */
+		0xff,				/*  di_area_code  */
+		0,				/*  di_connector_direction  */
+		"Keyboard",			/*  di_product_name  */
+		"di_product_license",		/*  di_product_license  */
+		LE16_TO_HOST(100),		/*  di_standby_power  */
+		LE16_TO_HOST(100)		/*  di_max_power  */
+	}
+};
+struct maple_device maple_device_mouse = {
+	{
+		BE32_TO_HOST(MAPLE_FUNC(MAPLE_FN_MOUSE)),/*  di_func  */
+		{ LE32_TO_HOST(0xfe060f00),0,0 },/* di_function_data[3]  */
+		0xff,				/*  di_area_code  */
+		0,				/*  di_connector_direction  */
+		"Dreamcast Mouse",		/*  di_product_name  */
+		"di_product_license",		/*  di_product_license  */
+		LE16_TO_HOST(0x0069),		/*  di_standby_power  */
+		LE16_TO_HOST(0x0120)		/*  di_max_power  */
+	}
+};
+
+
+DEVICE_TICK(maple)
+{
+	struct dreamcast_maple_data *d = (struct dreamcast_maple_data *) extra;
+	int key;
+
+	while ((key = console_readchar(d->console_handle)) >= 0) {
+		/*  Add to the keyboard queue:  */
+		d->char_queue[d->char_queue_head] = key;
+		d->char_queue_head = (d->char_queue_head + 1) % MAX_CHARS;
+		if (d->char_queue_head == d->char_queue_tail)
+			fatal("[ dreamcast_maple: KEYBOARD QUEUE OVERRUN! ]\n");
+
+		/*
+		 *  NOTE/TODO:
+		 *
+		 *  Implement the controller in a reasonable way!
+		 *  Theoretically, there are all of these buttons: ABCD XYZ Start
+		 *  and two digital pads, two analog joysticks, and two
+		 *  analog fire buttons (left and right).
+		 */
+
+		int control_bits = 0;
+		switch (key) {
+		case 'a':
+		case 'A':
+			control_bits = 0x0004;
+			break;
+		case 'b':
+		case 'B':
+			control_bits = 0x0002;
+			break;
+		case 'c':
+		case 'C':
+			control_bits = 0x0001;
+			break;
+		case 'd':
+		case 'D':
+			control_bits = 0x0800;
+			break;
+
+		case 'x':
+		case 'X':
+			control_bits = 0x0400;
+			break;
+		case 'y':
+		case 'Y':
+			control_bits = 0x0200;
+			break;
+		case 'z':
+		case 'Z':
+			control_bits = 0x0100;
+			break;
+
+		case 's':
+		case 'S':	/*  Start  */
+			control_bits = 0x0008;
+			break;
+
+		case '8':	/*  up  */
+			control_bits = 0x0010;
+			break;
+		case '2':	/*  down  */
+		case 'k':
+			control_bits = 0x0020;
+			break;
+		case '4':	/*  left  */
+		case 'u':
+			control_bits = 0x0040;
+			break;
+		case '6':	/*  right  */
+		case 'o':
+			control_bits = 0x0080;
+			break;
+		}
+
+		if (control_bits != 0) {
+			/*  Add to the controller queue:  */
+			d->controller_queue[d->controller_queue_head] = control_bits;
+			d->controller_queue_head =
+			    (d->controller_queue_head + 1) % MAX_CONTROLLER_DATA;
+			if (d->controller_queue_head == d->controller_queue_tail)
+				fatal("[ dreamcast_maple: CONTROLLER QUEUE "
+				    "OVERRUN! ]\n");
+		}
+	}
+}
+
+
+static int get_key(struct dreamcast_maple_data *d)
+{
+	int key = d->char_queue[d->char_queue_tail];
+	if (d->char_queue_head == d->char_queue_tail)
+		return -1;
+
+	d->char_queue_tail = (d->char_queue_tail + 1) % MAX_CHARS;
+	return key;
+}
+
+
+static int get_controller(struct dreamcast_maple_data *d)
+{
+	int c = d->controller_queue[d->controller_queue_tail];
+	if (d->controller_queue_head == d->controller_queue_tail)
+		return 0;
+
+	d->controller_queue_tail = (d->controller_queue_tail + 1)
+	    % MAX_CONTROLLER_DATA;
+	return c;
+}
+
+
+/*
+ *  maple_getcond_controller_response():
+ *
+ *  Generate a controller response. Based on info from Marcus
+ *  Comstedt's page: http://mc.pp.se/dc/controller.html
+ */
+static void maple_getcond_controller_response(struct dreamcast_maple_data *d,
+	struct cpu *cpu, int port, uint32_t receive_addr)
+{
+	uint8_t buf[8];
+	uint32_t response_code, transfer_code;
+	int c;
+
+	transfer_code = (MAPLE_RESPONSE_DATATRF << 24) |
+	    (((port << 6) | 0x20) << 16) |
+	    ((port << 6) << 8) |
+	    3  /*  Transfer length in 32-bit words  */;
+	transfer_code = BE32_TO_HOST(transfer_code);
+	cpu->memory_rw(cpu, cpu->mem, receive_addr, (unsigned char *) (void *) &transfer_code,
+	    4, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
+	receive_addr += 4;
+
+	response_code = BE32_TO_HOST(MAPLE_FUNC(MAPLE_FN_CONTROLLER));
+	cpu->memory_rw(cpu, cpu->mem, receive_addr, (unsigned char *) (void *) &response_code,
+	    4, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
+	receive_addr += 4;
+
+	/*  NOTE: Inverse of the buttons pressed!  */
+	c = ~get_controller(d);
+
+	/*
+	 *  buf[0..1] = little endian button bitfield
+	 *  buf[2] = right analogue trigger (0-255)
+	 *  buf[3] = left analogue trigger (0-255)
+	 *  buf[4] = analogue joystick X (0-255)
+	 *  buf[5] = analogue joystick Y (0-255)
+	 *  buf[6] = second analogue joystick X (0-255)
+	 *  buf[7] = second analogue joystick Y (0-255)
+	 */
+	memset(buf, 0, 8);
+	buf[0] = c & 0xff;
+	buf[1] = c >> 8;
+	buf[2] = buf[3] = 0;				// 0 = not pressed
+	buf[4] = buf[5] = buf[6] = buf[7] = 128;	// 128 = centered
+
+	cpu->memory_rw(cpu, cpu->mem, receive_addr, (unsigned char *) (void *) &buf, 8,
+	    MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
+}
+
+
+/*
+ *  maple_getcond_keyboard_response():
+ *
+ *  Generate a keyboard key-press response. Based on info from Marcus
+ *  Comstedt's page: http://mc.pp.se/dc/kbd.html
+ */
+static void maple_getcond_keyboard_response(struct dreamcast_maple_data *d,
+	struct cpu *cpu, int port, uint32_t receive_addr)
+{
+	int key;
+	uint8_t buf[8];
+	uint32_t response_code, transfer_code;
+
+	transfer_code = (MAPLE_RESPONSE_DATATRF << 24) |
+	    (((port << 6) | 0x20) << 16) |
+	    ((port << 6) << 8) |
+	    3  /*  Transfer length in 32-bit words  */;
+	transfer_code = BE32_TO_HOST(transfer_code);
+	cpu->memory_rw(cpu, cpu->mem, receive_addr, (unsigned char *) (void *) &transfer_code,
+	    4, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
+	receive_addr += 4;
+
+	response_code = BE32_TO_HOST(MAPLE_FUNC(MAPLE_FN_KEYBOARD));
+	cpu->memory_rw(cpu, cpu->mem, receive_addr, (unsigned char *) (void *) &response_code,
+	    4, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
+	receive_addr += 4;
+
+	key = get_key(d);
+
+	/*
+	 *  buf[0] = shift keys (1 = left ctrl, 2 = shift, 0x10 = right ctrl)
+	 *  buf[1] = led state
+	 *  buf[2] = key
+	 */
+	memset(buf, 0, 8);
+
+	if (key >= 'a' && key <= 'z')	buf[2] = 4 + key - 'a';
+	if (key >= 'A' && key <= 'Z')	buf[0] = 2, buf[2] = 4 + key - 'A';
+	if (key >= 1 && key <= 26)	buf[0] = 1, buf[2] = 4 + key - 1;
+	if (key >= '1' && key <= '9')	buf[2] = 0x1e + key - '1';
+	if (key == '!')			buf[0] = 2, buf[2] = 0x1e;
+	if (key == '"')			buf[0] = 2, buf[2] = 0x1f;
+	if (key == '#')			buf[0] = 2, buf[2] = 0x20;
+	if (key == '$')			buf[0] = 2, buf[2] = 0x21;
+	if (key == '%')			buf[0] = 2, buf[2] = 0x22;
+	if (key == '^')			buf[0] = 2, buf[2] = 0x23;
+	if (key == '&')			buf[0] = 2, buf[2] = 0x24;
+	if (key == '*')			buf[0] = 2, buf[2] = 0x25;
+	if (key == '(')			buf[0] = 2, buf[2] = 0x26;
+	if (key == '@')			buf[0] = 2, buf[2] = 0x1f;
+	if (key == '\n' || key == '\r')	buf[0] = 0, buf[2] = 0x28;
+	if (key == ')')			buf[0] = 2, buf[2] = 0x27;
+	if (key == '\b')		buf[0] = 0, buf[2] = 0x2a;
+	if (key == '\t')		buf[0] = 0, buf[2] = 0x2b;
+	if (key == ' ')			buf[0] = 0, buf[2] = 0x2c;
+	if (key == '0')			buf[2] = 0x27;
+	if (key == 27)			buf[2] = 0x29;
+	if (key == '-')			buf[2] = 0x2d;
+	if (key == '=')			buf[2] = 0x2e;
+	if (key == '[')			buf[2] = 0x2f;
+	if (key == '\\')		buf[2] = 0x31;
+	if (key == '|')			buf[2] = 0x31, buf[0] = 2;
+	if (key == ']')			buf[2] = 0x32;
+	if (key == ';')			buf[2] = 0x33;
+	if (key == ':')			buf[2] = 0x34;
+	if (key == ',')			buf[2] = 0x36;
+	if (key == '.')			buf[2] = 0x37;
+	if (key == '/')			buf[2] = 0x38;
+	if (key == '<')			buf[2] = 0x36, buf[0] = 2;
+	if (key == '>')			buf[2] = 0x37, buf[0] = 2;
+	if (key == '?')			buf[2] = 0x38, buf[0] = 2;
+	if (key == '+')			buf[2] = 0x57;
+
+	cpu->memory_rw(cpu, cpu->mem, receive_addr, (unsigned char *) (void *) &buf, 8,
+	    MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
+}
+
+
+/*
+ *  maple_do_dma_xfer():
+ *
+ *  Perform a DMA transfer. enable should be 1, and dmaaddr should point to
+ *  the memory to transfer.
+ */
+void maple_do_dma_xfer(struct cpu *cpu, struct dreamcast_maple_data *d)
+{
+	uint32_t addr = d->dmaaddr;
+
+	if (!d->enable) {
+		debug("[ maple_do_dma_xfer: not enabled? ]\n");
+		return;
+	}
+
+	/*  debug("[ dreamcast_maple: DMA transfer, dmaaddr = "
+	    "0x%08" PRIx32" ]\n", addr);  */
+
+	/*
+	 *  DMA transfers must be 32-byte aligned, according to Marcus
+	 *   Comstedt's Maple demo program.
+	 */
+	if (addr & 0x1f) {
+		fatal("[ dreamcast_maple: dmaaddr 0x%08" PRIx32" is NOT"
+		    " 32-byte aligned; aborting ]\n", addr);
+		return;
+	}
+
+	/*
+	 *  Handle one or more requests/responses:
+	 *
+	 *  (This is "reverse engineered" from Comstedt's maple demo program;
+	 *  it might not be good enough to emulate how the Maple is being
+	 *  used by other programs.)
+	 */
+	for (;;) {
+		uint32_t receive_addr, response_code, cond;
+		int port, last_message, cmd, to, datalen_cmd, unit;
+		uint8_t buf[8];
+
+		/*  Read the message' two control words:  */
+		cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *) (void *) &buf, 8, MEM_READ,
+		    NO_EXCEPTIONS | PHYSICAL);
+		addr += 8;
+
+		// int datalen = buf[0] * sizeof(uint32_t);
+
+		if (buf[1] & 2) {
+			fatal("[ dreamcast_maple: TODO: GUN bit. ]\n");
+			/*  TODO: Set some bits in A05F80C4 to indicate
+			    which raster position a lightgun is pointing
+			    at!  */
+			exit(1);
+		}
+		port = buf[2];
+		last_message = buf[3] & 0x80;
+		receive_addr = buf[4] + (buf[5] << 8) + (buf[6] << 16)
+		    + (buf[7] << 24);
+
+		if (receive_addr & 0xe000001f)
+			fatal("[ dreamcast_maple: WARNING! receive address 0x"
+			    "%08" PRIx32" isn't valid! ]\n", receive_addr);
+
+		/*  Read the command word for this message:  */
+		cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *) (void *) &buf, 4, MEM_READ,
+		    NO_EXCEPTIONS | PHYSICAL);
+		addr += 4;
+
+		cmd = buf[0];
+		to = buf[1];
+		// int from = buf[2];
+		datalen_cmd = buf[3];
+
+		/*  Decode the unit number:  */
+		unit = 0;
+		switch (to & 0x3f) {
+		case 0x00:
+		case 0x20: unit = 0; break;
+		case 0x01: unit = 1; break;
+		case 0x02: unit = 2; break;
+		case 0x04: unit = 3; break;
+		case 0x08: unit = 4; break;
+		case 0x10: unit = 5; break;
+		default: fatal("[ dreamcast_maple: ERROR! multiple "
+			    "units? Not yet implemented. to = 0x%02x ]\n", to);
+			exit(1);
+		}
+
+		/*  fatal("[ dreamcast_maple: cmd=0x%02x, port=%c, unit=%i"
+		    ", datalen=%i words. receive_addr=0x%08x ]\n",
+		    cmd, port+'A', unit, datalen_cmd, receive_addr);  */
+
+		/*
+		 *  Handle the command:
+		 */
+		switch (cmd) {
+
+		case MAPLE_COMMAND_DEVINFO:
+			if (d->device[port] == NULL || unit != 0) {
+				/*  No device present: Timeout.  */
+				/*  debug("[ dreamcast_maple: response="
+				    "timeout ]\n");  */
+				response_code = (uint32_t) -1;
+				response_code = LE32_TO_HOST(response_code);
+				cpu->memory_rw(cpu, cpu->mem, receive_addr,
+				    (unsigned char *) (void *) &response_code, 4, MEM_WRITE,
+				    NO_EXCEPTIONS | PHYSICAL);
+			} else {
+				/*  Device present:  */
+				unsigned int i;
+				struct maple_devinfo *di =
+				    &d->device[port]->devinfo;
+				/*  debug("[ dreamcast_maple: response="
+				    "\"%s\" ]\n", di->di_product_name);  */
+				response_code = MAPLE_RESPONSE_DEVINFO |
+				    (((port << 6) | 0x20) << 8) |
+				    ((port << 6) << 16) |
+				    ((sizeof(struct maple_devinfo) /
+				    sizeof(uint32_t)) << 24);
+				response_code = LE32_TO_HOST(response_code);
+				cpu->memory_rw(cpu, cpu->mem, receive_addr,
+				    (unsigned char *) (void *) &response_code, 4, MEM_WRITE,
+				    NO_EXCEPTIONS | PHYSICAL);
+				for (i=0; i<sizeof(struct maple_devinfo); i++)
+					cpu->memory_rw(cpu, cpu->mem,
+					    receive_addr + 4 + i, (unsigned
+					    char *) di + i, 1, MEM_WRITE,
+					    NO_EXCEPTIONS | PHYSICAL);
+			}
+			break;
+
+		case MAPLE_COMMAND_GETCOND:
+			cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *) (void *) &buf, 4,
+			    MEM_READ, NO_EXCEPTIONS | PHYSICAL);
+			cond = buf[3] + (buf[2] << 8) + (buf[1] << 16)
+			    + (buf[0] << 24);
+			if (cond & MAPLE_FUNC(MAPLE_FN_CONTROLLER)) {
+				maple_getcond_controller_response(
+				    d, cpu, port, receive_addr);
+			} else if (cond & MAPLE_FUNC(MAPLE_FN_KEYBOARD)) {
+				maple_getcond_keyboard_response(
+				    d, cpu, port, receive_addr);
+			} else {
+				fatal("[ dreamcast_maple: WARNING: GETCOND: "
+				    "UNIMPLEMENTED 0x%08" PRIx32" ]\n", cond);
+				exit(1);
+			}
+			break;
+
+		case MAPLE_COMMAND_BWRITE:
+			fatal("[ dreamcast_maple: BWRITE: TODO ]\n");
+			break;
+
+		default:fatal("[ dreamcast_maple: command %i: TODO ]\n", cmd);
+			exit(1);
+		}
+
+		addr += datalen_cmd * 4;
+
+		/*  Last request? Then stop.  */
+		if (last_message)
+			break;
+	}
+
+	// TODO: Should the DMA address be updated?
+	d->dmaaddr = addr;
+
+	/*  Assert the SYSASIC_EVENT_MAPLE_DMADONE event:  */
+	SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_MAPLE_DMADONE);
+}
+
+
+DEVICE_ACCESS(dreamcast_maple)
+{
+	struct dreamcast_maple_data *d = (struct dreamcast_maple_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case 0x04:	/*  MAPLE_DMAADDR  */
+		if (writeflag == MEM_WRITE) {
+			d->dmaaddr = idata;
+			/* debug("[ dreamcast_maple: dmaaddr set to 0x%08x"
+			    " ]\n", d->dmaaddr);  */
+		} else {
+			fatal("[ dreamcast_maple: TODO: read from dmaaddr ]\n");
+			odata = d->dmaaddr;
+			exit(1);
+		}
+		break;
+
+	case 0x10:	/*  MAPLE_RESET2  */
+		if (writeflag == MEM_WRITE && idata != 0)
+			fatal("[ dreamcast_maple: UNIMPLEMENTED reset2 value"
+			    " 0x%08x ]\n", (int)idata);
+		break;
+
+	case 0x14:	/*  MAPLE_ENABLE  */
+		if (writeflag == MEM_WRITE)
+			d->enable = idata;
+		else
+			odata = d->enable;
+		break;
+
+	case 0x18:	/*  MAPLE_STATE  */
+		if (writeflag == MEM_WRITE) {
+			switch (idata) {
+			case 0:	break;
+			case 1:	maple_do_dma_xfer(cpu, d);
+				break;
+			default:fatal("[ dreamcast_maple: UNIMPLEMENTED "
+				    "state value %i ]\n", (int)idata);
+			}
+		} else {
+			/*  Always return 0 to indicate DMA xfer complete.  */
+			odata = 0;
+		}
+		break;
+
+	case 0x80:	/*  MAPLE_SPEED  */
+		if (writeflag == MEM_WRITE) {
+			d->timeout = (idata >> 16) & 0xffff;
+			/*  TODO: Bits 8..9 are "speed", but only the value
+			    0 (indicating 2 Mbit/s) should be used.  */
+			debug("[ dreamcast_maple: timeout set to %i ]\n",
+			    d->timeout);
+		} else {
+			odata = d->timeout << 16;
+		}
+		break;
+
+	case 0x8c:	/*  MAPLE_RESET  */
+		if (writeflag == MEM_WRITE) {
+			if (idata != 0x6155404f && idata != 0x61557f00)
+				fatal("[ dreamcast_maple: UNIMPLEMENTED reset "
+				    "value 0x%08x ]\n", (int)idata);
+			d->enable = 0;
+		}
+		break;
+
+	case 0xe8:	/*  UNKNOWN_0xe8  */
+		if (writeflag == MEM_WRITE) {
+			// The Dreamcast PROM writes 1 here.
+			if (idata != 1) {
+				fatal("[ dreamcast_maple: UNIMPLEMENTED 0xe8 "
+				    "value 0x%08x ]\n", (int)idata);
+			}
+		}
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ dreamcast_maple: UNIMPLEMENTED read from "
+			    "addr 0x%x ]\n", (int)relative_addr);
+		} else {
+			fatal("[ dreamcast_maple: UNIMPLEMENTED write to addr "
+			    "0x%x: 0x%x ]\n", (int)relative_addr, (int)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(dreamcast_maple)
+{
+	struct dreamcast_maple_data *d;
+
+	CHECK_ALLOCATION(d = (struct dreamcast_maple_data *) malloc(sizeof(struct dreamcast_maple_data)));
+	memset(d, 0, sizeof(struct dreamcast_maple_data));
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    0x5f6c00, 0x100, dev_dreamcast_maple_access, d, DM_DEFAULT, NULL);
+
+	/*  Devices connected to port A..D:  */
+	d->device[0] = &maple_device_controller;
+	d->device[1] = NULL;
+	d->device[2] = &maple_device_keyboard;
+	d->device[3] = NULL;	/*  TODO:  &maple_device_mouse;  */
+
+	d->console_handle = console_start_slave_inputonly(
+	    devinit->machine, "maple", 1);
+	devinit->machine->main_console_handle = d->console_handle;
+
+	machine_add_tickfunction(devinit->machine, dev_maple_tick, d,
+	    MAPLE_TICK_SHIFT);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_dreamcast_maple.cc gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_maple.cc
--- gxemul-0.6.2/src/devices/dev_dreamcast_maple.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_maple.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,668 +0,0 @@
-/*
- *  Copyright (C) 2006-2014  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Dreamcast Maple bus controller
- *
- *  The Maple bus has 4 ports (A-D), and each port has up to 6 possible "units"
- *  (where unit 0 is the main unit). Communication is done using DMA; each
- *  DMA transfer sends one or more requests, and for each of these requests
- *  a response is generated (or a timeout if there was no device at the
- *  specific port).
- *
- *  See Marcus Comstedt's page (http://mc.pp.se/dc/maplebus.html) for more
- *  details about the DMA request/responses.
- *
- *
- *  TODO:
- *	Unit numbers / IDs for real Maple devices.
- *	The Controller (up/down/left/right, buttons, etc).
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/time.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/dreamcast_maple.h"
-#include "thirdparty/dreamcast_sysasicvar.h"
-
-
-// #define debug fatal
-
-#define	N_MAPLE_PORTS		4
-
-#define	MAX_CHARS		8192
-#define	MAX_CONTROLLER_DATA	4096
-
-#define	MAPLE_TICK_SHIFT	17
-
-struct maple_device {
-	struct maple_devinfo devinfo;
-};
-
-struct dreamcast_maple_data {
-	/*  Registers:  */
-	uint32_t	dmaaddr;
-	int		enable;
-	int		timeout;
-
-	/*  Attached devices:  */
-	struct maple_device *device[N_MAPLE_PORTS];
-
-	/*  For keyboard/controller input:  */
-	int		console_handle;
-	uint8_t		char_queue[MAX_CHARS];
-	uint16_t	controller_queue[MAX_CONTROLLER_DATA];
-	int		char_queue_head, char_queue_tail;
-	int		controller_queue_head, controller_queue_tail;
-};
-
-
-/*
- *  Maple devices:
- *
- *  TODO: Figure out strings and numbers of _real_ Maple devices.
- */
-struct maple_device maple_device_controller = {
-	{
-		BE32_TO_HOST(MAPLE_FUNC(MAPLE_FN_CONTROLLER)),	/*  di_func  */
-		{ LE32_TO_HOST(0xfe060f00),0,0 },/* di_function_data[3]  */
-		0xff,				/*  di_area_code  */
-		0,				/*  di_connector_direction  */
-		"Dreamcast Controller",		/*  di_product_name  */
-		"di_product_license",		/*  di_product_license  */
-		LE16_TO_HOST(0x01ae),		/*  di_standby_power  */
-		LE16_TO_HOST(0x01f4)		/*  di_max_power  */
-	}
-};
-struct maple_device maple_device_keyboard = {
-	{
-		BE32_TO_HOST(MAPLE_FUNC(MAPLE_FN_KEYBOARD)),/*  di_func  */
-		{ LE32_TO_HOST(2),0,0 },	/*  di_function_data[3]  */
-		0xff,				/*  di_area_code  */
-		0,				/*  di_connector_direction  */
-		"Keyboard",			/*  di_product_name  */
-		"di_product_license",		/*  di_product_license  */
-		LE16_TO_HOST(100),		/*  di_standby_power  */
-		LE16_TO_HOST(100)		/*  di_max_power  */
-	}
-};
-struct maple_device maple_device_mouse = {
-	{
-		BE32_TO_HOST(MAPLE_FUNC(MAPLE_FN_MOUSE)),/*  di_func  */
-		{ LE32_TO_HOST(0xfe060f00),0,0 },/* di_function_data[3]  */
-		0xff,				/*  di_area_code  */
-		0,				/*  di_connector_direction  */
-		"Dreamcast Mouse",		/*  di_product_name  */
-		"di_product_license",		/*  di_product_license  */
-		LE16_TO_HOST(0x0069),		/*  di_standby_power  */
-		LE16_TO_HOST(0x0120)		/*  di_max_power  */
-	}
-};
-
-
-DEVICE_TICK(maple)
-{
-	struct dreamcast_maple_data *d = (struct dreamcast_maple_data *) extra;
-	int key;
-
-	while ((key = console_readchar(d->console_handle)) >= 0) {
-		/*  Add to the keyboard queue:  */
-		d->char_queue[d->char_queue_head] = key;
-		d->char_queue_head = (d->char_queue_head + 1) % MAX_CHARS;
-		if (d->char_queue_head == d->char_queue_tail)
-			fatal("[ dreamcast_maple: KEYBOARD QUEUE OVERRUN! ]\n");
-
-		/*
-		 *  NOTE/TODO:
-		 *
-		 *  Implement the controller in a reasonable way!
-		 *  Theoretically, there are all of these buttons: ABCD XYZ Start
-		 *  and two digital pads, two analog joysticks, and two
-		 *  analog fire buttons (left and right).
-		 */
-
-		int control_bits = 0;
-		switch (key) {
-		case 'a':
-		case 'A':
-			control_bits = 0x0004;
-			break;
-		case 'b':
-		case 'B':
-			control_bits = 0x0002;
-			break;
-		case 'c':
-		case 'C':
-			control_bits = 0x0001;
-			break;
-		case 'd':
-		case 'D':
-			control_bits = 0x0800;
-			break;
-
-		case 'x':
-		case 'X':
-			control_bits = 0x0400;
-			break;
-		case 'y':
-		case 'Y':
-			control_bits = 0x0200;
-			break;
-		case 'z':
-		case 'Z':
-			control_bits = 0x0100;
-			break;
-
-		case 's':
-		case 'S':	/*  Start  */
-			control_bits = 0x0008;
-			break;
-
-		case '8':	/*  up  */
-			control_bits = 0x0010;
-			break;
-		case '2':	/*  down  */
-		case 'k':
-			control_bits = 0x0020;
-			break;
-		case '4':	/*  left  */
-		case 'u':
-			control_bits = 0x0040;
-			break;
-		case '6':	/*  right  */
-		case 'o':
-			control_bits = 0x0080;
-			break;
-		}
-
-		if (control_bits != 0) {
-			/*  Add to the controller queue:  */
-			d->controller_queue[d->controller_queue_head] = control_bits;
-			d->controller_queue_head =
-			    (d->controller_queue_head + 1) % MAX_CONTROLLER_DATA;
-			if (d->controller_queue_head == d->controller_queue_tail)
-				fatal("[ dreamcast_maple: CONTROLLER QUEUE "
-				    "OVERRUN! ]\n");
-		}
-	}
-}
-
-
-static int get_key(struct dreamcast_maple_data *d)
-{
-	int key = d->char_queue[d->char_queue_tail];
-	if (d->char_queue_head == d->char_queue_tail)
-		return -1;
-
-	d->char_queue_tail = (d->char_queue_tail + 1) % MAX_CHARS;
-	return key;
-}
-
-
-static int get_controller(struct dreamcast_maple_data *d)
-{
-	int c = d->controller_queue[d->controller_queue_tail];
-	if (d->controller_queue_head == d->controller_queue_tail)
-		return 0;
-
-	d->controller_queue_tail = (d->controller_queue_tail + 1)
-	    % MAX_CONTROLLER_DATA;
-	return c;
-}
-
-
-/*
- *  maple_getcond_controller_response():
- *
- *  Generate a controller response. Based on info from Marcus
- *  Comstedt's page: http://mc.pp.se/dc/controller.html
- */
-static void maple_getcond_controller_response(struct dreamcast_maple_data *d,
-	struct cpu *cpu, int port, uint32_t receive_addr)
-{
-	uint8_t buf[8];
-	uint32_t response_code, transfer_code;
-	int c;
-
-	transfer_code = (MAPLE_RESPONSE_DATATRF << 24) |
-	    (((port << 6) | 0x20) << 16) |
-	    ((port << 6) << 8) |
-	    3  /*  Transfer length in 32-bit words  */;
-	transfer_code = BE32_TO_HOST(transfer_code);
-	cpu->memory_rw(cpu, cpu->mem, receive_addr, (unsigned char *) (void *) &transfer_code,
-	    4, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
-	receive_addr += 4;
-
-	response_code = BE32_TO_HOST(MAPLE_FUNC(MAPLE_FN_CONTROLLER));
-	cpu->memory_rw(cpu, cpu->mem, receive_addr, (unsigned char *) (void *) &response_code,
-	    4, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
-	receive_addr += 4;
-
-	/*  NOTE: Inverse of the buttons pressed!  */
-	c = ~get_controller(d);
-
-	/*
-	 *  buf[0..1] = little endian button bitfield
-	 *  buf[2] = right analogue trigger (0-255)
-	 *  buf[3] = left analogue trigger (0-255)
-	 *  buf[4] = analogue joystick X (0-255)
-	 *  buf[5] = analogue joystick Y (0-255)
-	 *  buf[6] = second analogue joystick X (0-255)
-	 *  buf[7] = second analogue joystick Y (0-255)
-	 */
-	memset(buf, 0, 8);
-	buf[0] = c & 0xff;
-	buf[1] = c >> 8;
-	buf[2] = buf[3] = 0;				// 0 = not pressed
-	buf[4] = buf[5] = buf[6] = buf[7] = 128;	// 128 = centered
-
-	cpu->memory_rw(cpu, cpu->mem, receive_addr, (unsigned char *) (void *) &buf, 8,
-	    MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
-}
-
-
-/*
- *  maple_getcond_keyboard_response():
- *
- *  Generate a keyboard key-press response. Based on info from Marcus
- *  Comstedt's page: http://mc.pp.se/dc/kbd.html
- */
-static void maple_getcond_keyboard_response(struct dreamcast_maple_data *d,
-	struct cpu *cpu, int port, uint32_t receive_addr)
-{
-	int key;
-	uint8_t buf[8];
-	uint32_t response_code, transfer_code;
-
-	transfer_code = (MAPLE_RESPONSE_DATATRF << 24) |
-	    (((port << 6) | 0x20) << 16) |
-	    ((port << 6) << 8) |
-	    3  /*  Transfer length in 32-bit words  */;
-	transfer_code = BE32_TO_HOST(transfer_code);
-	cpu->memory_rw(cpu, cpu->mem, receive_addr, (unsigned char *) (void *) &transfer_code,
-	    4, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
-	receive_addr += 4;
-
-	response_code = BE32_TO_HOST(MAPLE_FUNC(MAPLE_FN_KEYBOARD));
-	cpu->memory_rw(cpu, cpu->mem, receive_addr, (unsigned char *) (void *) &response_code,
-	    4, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
-	receive_addr += 4;
-
-	key = get_key(d);
-
-	/*
-	 *  buf[0] = shift keys (1 = left ctrl, 2 = shift, 0x10 = right ctrl)
-	 *  buf[1] = led state
-	 *  buf[2] = key
-	 */
-	memset(buf, 0, 8);
-
-	if (key >= 'a' && key <= 'z')	buf[2] = 4 + key - 'a';
-	if (key >= 'A' && key <= 'Z')	buf[0] = 2, buf[2] = 4 + key - 'A';
-	if (key >= 1 && key <= 26)	buf[0] = 1, buf[2] = 4 + key - 1;
-	if (key >= '1' && key <= '9')	buf[2] = 0x1e + key - '1';
-	if (key == '!')			buf[0] = 2, buf[2] = 0x1e;
-	if (key == '"')			buf[0] = 2, buf[2] = 0x1f;
-	if (key == '#')			buf[0] = 2, buf[2] = 0x20;
-	if (key == '$')			buf[0] = 2, buf[2] = 0x21;
-	if (key == '%')			buf[0] = 2, buf[2] = 0x22;
-	if (key == '^')			buf[0] = 2, buf[2] = 0x23;
-	if (key == '&')			buf[0] = 2, buf[2] = 0x24;
-	if (key == '*')			buf[0] = 2, buf[2] = 0x25;
-	if (key == '(')			buf[0] = 2, buf[2] = 0x26;
-	if (key == '@')			buf[0] = 2, buf[2] = 0x1f;
-	if (key == '\n' || key == '\r')	buf[0] = 0, buf[2] = 0x28;
-	if (key == ')')			buf[0] = 2, buf[2] = 0x27;
-	if (key == '\b')		buf[0] = 0, buf[2] = 0x2a;
-	if (key == '\t')		buf[0] = 0, buf[2] = 0x2b;
-	if (key == ' ')			buf[0] = 0, buf[2] = 0x2c;
-	if (key == '0')			buf[2] = 0x27;
-	if (key == 27)			buf[2] = 0x29;
-	if (key == '-')			buf[2] = 0x2d;
-	if (key == '=')			buf[2] = 0x2e;
-	if (key == '[')			buf[2] = 0x2f;
-	if (key == '\\')		buf[2] = 0x31;
-	if (key == '|')			buf[2] = 0x31, buf[0] = 2;
-	if (key == ']')			buf[2] = 0x32;
-	if (key == ';')			buf[2] = 0x33;
-	if (key == ':')			buf[2] = 0x34;
-	if (key == ',')			buf[2] = 0x36;
-	if (key == '.')			buf[2] = 0x37;
-	if (key == '/')			buf[2] = 0x38;
-	if (key == '<')			buf[2] = 0x36, buf[0] = 2;
-	if (key == '>')			buf[2] = 0x37, buf[0] = 2;
-	if (key == '?')			buf[2] = 0x38, buf[0] = 2;
-	if (key == '+')			buf[2] = 0x57;
-
-	cpu->memory_rw(cpu, cpu->mem, receive_addr, (unsigned char *) (void *) &buf, 8,
-	    MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
-}
-
-
-/*
- *  maple_do_dma_xfer():
- *
- *  Perform a DMA transfer. enable should be 1, and dmaaddr should point to
- *  the memory to transfer.
- */
-void maple_do_dma_xfer(struct cpu *cpu, struct dreamcast_maple_data *d)
-{
-	uint32_t addr = d->dmaaddr;
-
-	if (!d->enable) {
-		debug("[ maple_do_dma_xfer: not enabled? ]\n");
-		return;
-	}
-
-	/*  debug("[ dreamcast_maple: DMA transfer, dmaaddr = "
-	    "0x%08" PRIx32" ]\n", addr);  */
-
-	/*
-	 *  DMA transfers must be 32-byte aligned, according to Marcus
-	 *   Comstedt's Maple demo program.
-	 */
-	if (addr & 0x1f) {
-		fatal("[ dreamcast_maple: dmaaddr 0x%08" PRIx32" is NOT"
-		    " 32-byte aligned; aborting ]\n", addr);
-		return;
-	}
-
-	/*
-	 *  Handle one or more requests/responses:
-	 *
-	 *  (This is "reverse engineered" from Comstedt's maple demo program;
-	 *  it might not be good enough to emulate how the Maple is being
-	 *  used by other programs.)
-	 */
-	for (;;) {
-		uint32_t receive_addr, response_code, cond;
-		int datalen, port, last_message, cmd, to, from, datalen_cmd;
-		int unit;
-		uint8_t buf[8];
-
-		/*  Read the message' two control words:  */
-		cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *) (void *) &buf, 8, MEM_READ,
-		    NO_EXCEPTIONS | PHYSICAL);
-		addr += 8;
-
-		datalen = buf[0] * sizeof(uint32_t);
-		if (buf[1] & 2) {
-			fatal("[ dreamcast_maple: TODO: GUN bit. ]\n");
-			/*  TODO: Set some bits in A05F80C4 to indicate
-			    which raster position a lightgun is pointing
-			    at!  */
-			exit(1);
-		}
-		port = buf[2];
-		last_message = buf[3] & 0x80;
-		receive_addr = buf[4] + (buf[5] << 8) + (buf[6] << 16)
-		    + (buf[7] << 24);
-
-		if (receive_addr & 0xe000001f)
-			fatal("[ dreamcast_maple: WARNING! receive address 0x"
-			    "%08" PRIx32" isn't valid! ]\n", receive_addr);
-
-		/*  Read the command word for this message:  */
-		cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *) (void *) &buf, 4, MEM_READ,
-		    NO_EXCEPTIONS | PHYSICAL);
-		addr += 4;
-
-		cmd = buf[0];
-		to = buf[1];
-		from = buf[2];
-		datalen_cmd = buf[3];
-
-		/*  Decode the unit number:  */
-		unit = 0;
-		switch (to & 0x3f) {
-		case 0x00:
-		case 0x20: unit = 0; break;
-		case 0x01: unit = 1; break;
-		case 0x02: unit = 2; break;
-		case 0x04: unit = 3; break;
-		case 0x08: unit = 4; break;
-		case 0x10: unit = 5; break;
-		default: fatal("[ dreamcast_maple: ERROR! multiple "
-			    "units? Not yet implemented. to = 0x%02x ]\n", to);
-			exit(1);
-		}
-
-		/*  fatal("[ dreamcast_maple: cmd=0x%02x, port=%c, unit=%i"
-		    ", datalen=%i words. receive_addr=0x%08x ]\n",
-		    cmd, port+'A', unit, datalen_cmd, receive_addr);  */
-
-		/*
-		 *  Handle the command:
-		 */
-		switch (cmd) {
-
-		case MAPLE_COMMAND_DEVINFO:
-			if (d->device[port] == NULL || unit != 0) {
-				/*  No device present: Timeout.  */
-				/*  debug("[ dreamcast_maple: response="
-				    "timeout ]\n");  */
-				response_code = (uint32_t) -1;
-				response_code = LE32_TO_HOST(response_code);
-				cpu->memory_rw(cpu, cpu->mem, receive_addr,
-				    (unsigned char *) (void *) &response_code, 4, MEM_WRITE,
-				    NO_EXCEPTIONS | PHYSICAL);
-			} else {
-				/*  Device present:  */
-				unsigned int i;
-				struct maple_devinfo *di =
-				    &d->device[port]->devinfo;
-				/*  debug("[ dreamcast_maple: response="
-				    "\"%s\" ]\n", di->di_product_name);  */
-				response_code = MAPLE_RESPONSE_DEVINFO |
-				    (((port << 6) | 0x20) << 8) |
-				    ((port << 6) << 16) |
-				    ((sizeof(struct maple_devinfo) /
-				    sizeof(uint32_t)) << 24);
-				response_code = LE32_TO_HOST(response_code);
-				cpu->memory_rw(cpu, cpu->mem, receive_addr,
-				    (unsigned char *) (void *) &response_code, 4, MEM_WRITE,
-				    NO_EXCEPTIONS | PHYSICAL);
-				for (i=0; i<sizeof(struct maple_devinfo); i++)
-					cpu->memory_rw(cpu, cpu->mem,
-					    receive_addr + 4 + i, (unsigned
-					    char *) di + i, 1, MEM_WRITE,
-					    NO_EXCEPTIONS | PHYSICAL);
-			}
-			break;
-
-		case MAPLE_COMMAND_GETCOND:
-			cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *) (void *) &buf, 4,
-			    MEM_READ, NO_EXCEPTIONS | PHYSICAL);
-			cond = buf[3] + (buf[2] << 8) + (buf[1] << 16)
-			    + (buf[0] << 24);
-			if (cond & MAPLE_FUNC(MAPLE_FN_CONTROLLER)) {
-				maple_getcond_controller_response(
-				    d, cpu, port, receive_addr);
-			} else if (cond & MAPLE_FUNC(MAPLE_FN_KEYBOARD)) {
-				maple_getcond_keyboard_response(
-				    d, cpu, port, receive_addr);
-			} else {
-				fatal("[ dreamcast_maple: WARNING: GETCOND: "
-				    "UNIMPLEMENTED 0x%08" PRIx32" ]\n", cond);
-				exit(1);
-			}
-			break;
-
-		case MAPLE_COMMAND_BWRITE:
-			fatal("[ dreamcast_maple: BWRITE: TODO ]\n");
-			break;
-
-		default:fatal("[ dreamcast_maple: command %i: TODO ]\n", cmd);
-			exit(1);
-		}
-
-		addr += datalen_cmd * 4;
-
-		/*  Last request? Then stop.  */
-		if (last_message)
-			break;
-	}
-
-	// TODO: Should the DMA address be updated?
-	d->dmaaddr = addr;
-
-	/*  Assert the SYSASIC_EVENT_MAPLE_DMADONE event:  */
-	SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_MAPLE_DMADONE);
-}
-
-
-DEVICE_ACCESS(dreamcast_maple)
-{
-	struct dreamcast_maple_data *d = (struct dreamcast_maple_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case 0x04:	/*  MAPLE_DMAADDR  */
-		if (writeflag == MEM_WRITE) {
-			d->dmaaddr = idata;
-			/* debug("[ dreamcast_maple: dmaaddr set to 0x%08x"
-			    " ]\n", d->dmaaddr);  */
-		} else {
-			fatal("[ dreamcast_maple: TODO: read from dmaaddr ]\n");
-			odata = d->dmaaddr;
-			exit(1);
-		}
-		break;
-
-	case 0x10:	/*  MAPLE_RESET2  */
-		if (writeflag == MEM_WRITE && idata != 0)
-			fatal("[ dreamcast_maple: UNIMPLEMENTED reset2 value"
-			    " 0x%08x ]\n", (int)idata);
-		break;
-
-	case 0x14:	/*  MAPLE_ENABLE  */
-		if (writeflag == MEM_WRITE)
-			d->enable = idata;
-		else
-			odata = d->enable;
-		break;
-
-	case 0x18:	/*  MAPLE_STATE  */
-		if (writeflag == MEM_WRITE) {
-			switch (idata) {
-			case 0:	break;
-			case 1:	maple_do_dma_xfer(cpu, d);
-				break;
-			default:fatal("[ dreamcast_maple: UNIMPLEMENTED "
-				    "state value %i ]\n", (int)idata);
-			}
-		} else {
-			/*  Always return 0 to indicate DMA xfer complete.  */
-			odata = 0;
-		}
-		break;
-
-	case 0x80:	/*  MAPLE_SPEED  */
-		if (writeflag == MEM_WRITE) {
-			d->timeout = (idata >> 16) & 0xffff;
-			/*  TODO: Bits 8..9 are "speed", but only the value
-			    0 (indicating 2 Mbit/s) should be used.  */
-			debug("[ dreamcast_maple: timeout set to %i ]\n",
-			    d->timeout);
-		} else {
-			odata = d->timeout << 16;
-		}
-		break;
-
-	case 0x8c:	/*  MAPLE_RESET  */
-		if (writeflag == MEM_WRITE) {
-			if (idata != 0x6155404f && idata != 0x61557f00)
-				fatal("[ dreamcast_maple: UNIMPLEMENTED reset "
-				    "value 0x%08x ]\n", (int)idata);
-			d->enable = 0;
-		}
-		break;
-
-	case 0xe8:	/*  UNKNOWN_0xe8  */
-		if (writeflag == MEM_WRITE) {
-			// The Dreamcast PROM writes 1 here.
-			if (idata != 1) {
-				fatal("[ dreamcast_maple: UNIMPLEMENTED 0xe8 "
-				    "value 0x%08x ]\n", (int)idata);
-			}
-		}
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ dreamcast_maple: UNIMPLEMENTED read from "
-			    "addr 0x%x ]\n", (int)relative_addr);
-		} else {
-			fatal("[ dreamcast_maple: UNIMPLEMENTED write to addr "
-			    "0x%x: 0x%x ]\n", (int)relative_addr, (int)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(dreamcast_maple)
-{
-	struct dreamcast_maple_data *d;
-
-	CHECK_ALLOCATION(d = (struct dreamcast_maple_data *) malloc(sizeof(struct dreamcast_maple_data)));
-	memset(d, 0, sizeof(struct dreamcast_maple_data));
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    0x5f6c00, 0x100, dev_dreamcast_maple_access, d, DM_DEFAULT, NULL);
-
-	/*  Devices connected to port A..D:  */
-	d->device[0] = &maple_device_controller;
-	d->device[1] = NULL;
-	d->device[2] = &maple_device_keyboard;
-	d->device[3] = NULL;	/*  TODO:  &maple_device_mouse;  */
-
-	d->console_handle = console_start_slave_inputonly(
-	    devinit->machine, "maple", 1);
-	devinit->machine->main_console_handle = d->console_handle;
-
-	machine_add_tickfunction(devinit->machine, dev_maple_tick, d,
-	    MAPLE_TICK_SHIFT);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_dreamcast_rtc.c gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_rtc.c
--- gxemul-0.6.2/src/devices/dev_dreamcast_rtc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_rtc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,125 @@
+/*
+ *  Copyright (C) 2006-2014  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Dreamcast Real-Time Clock
+ *
+ *  Pretty basic; two 32-bit words at physical addresses 0x00710000 and
+ *  0x00710004 hold the high and low 16-bit parts, respectively, of the
+ *  system's 32-bit tv_sec value.
+ *
+ *  The only difference from the raw Unix concept is that the Dreamcast's
+ *  clock is based at 1950 instead of 1970.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define debug fatal
+
+struct dreamcast_rtc_data {
+	int		dummy;
+};
+
+
+DEVICE_ACCESS(dreamcast_rtc)
+{
+	/*  struct dreamcast_rtc_data *d = extra;  */
+	uint64_t idata = 0, odata = 0;
+	struct timeval tv;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case 0:
+	case 4:
+		/*
+		 *  While writing to the RTC could set the date/time of the
+		 *  host, that would probably be very annoying. For now,
+		 *  simply ignore writes.
+		 */
+		if (writeflag == MEM_WRITE)
+			break;
+
+		gettimeofday(&tv, NULL);
+
+		/*  Offset by 20 years:  */
+		odata = tv.tv_sec + 631152000;
+
+		if (relative_addr == 0)
+			odata = (odata >> 16) & 0xffff;
+		else
+			odata &= 0xffff;
+		break;
+
+	case 8:
+		/*
+		 *  The Dreamcast PROM writes a 1 here when setting the
+		 *  date/time. Let's ignore it for now.
+		 */
+		break;
+
+	default:
+		if (writeflag == MEM_READ) {
+			fatal("[ dreamcast_rtc: read from addr 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ dreamcast_rtc: write to addr 0x%x: 0x%x ]\n",
+			    (int)relative_addr, (int)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(dreamcast_rtc)
+{
+	struct dreamcast_rtc_data *d;
+
+	CHECK_ALLOCATION(d = (struct dreamcast_rtc_data *) malloc(sizeof(struct dreamcast_rtc_data)));
+	memset(d, 0, sizeof(struct dreamcast_rtc_data));
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    0x00710000, 0x100, dev_dreamcast_rtc_access, d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_dreamcast_rtc.cc gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_rtc.cc
--- gxemul-0.6.2/src/devices/dev_dreamcast_rtc.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_dreamcast_rtc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,125 +0,0 @@
-/*
- *  Copyright (C) 2006-2014  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Dreamcast Real-Time Clock
- *
- *  Pretty basic; two 32-bit words at physical addresses 0x00710000 and
- *  0x00710004 hold the high and low 16-bit parts, respectively, of the
- *  system's 32-bit tv_sec value.
- *
- *  The only difference from the raw Unix concept is that the Dreamcast's
- *  clock is based at 1950 instead of 1970.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/time.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define debug fatal
-
-struct dreamcast_rtc_data {
-	int		dummy;
-};
-
-
-DEVICE_ACCESS(dreamcast_rtc)
-{
-	/*  struct dreamcast_rtc_data *d = extra;  */
-	uint64_t idata = 0, odata = 0;
-	struct timeval tv;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case 0:
-	case 4:
-		/*
-		 *  While writing to the RTC could set the date/time of the
-		 *  host, that would probably be very annoying. For now,
-		 *  simply ignore writes.
-		 */
-		if (writeflag == MEM_WRITE)
-			break;
-
-		gettimeofday(&tv, NULL);
-
-		/*  Offset by 20 years:  */
-		odata = tv.tv_sec + 631152000;
-
-		if (relative_addr == 0)
-			odata = (odata >> 16) & 0xffff;
-		else
-			odata &= 0xffff;
-		break;
-
-	case 8:
-		/*
-		 *  The Dreamcast PROM writes a 1 here when setting the
-		 *  date/time. Let's ignore it for now.
-		 */
-		break;
-
-	default:
-		if (writeflag == MEM_READ) {
-			fatal("[ dreamcast_rtc: read from addr 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ dreamcast_rtc: write to addr 0x%x: 0x%x ]\n",
-			    (int)relative_addr, (int)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(dreamcast_rtc)
-{
-	struct dreamcast_rtc_data *d;
-
-	CHECK_ALLOCATION(d = (struct dreamcast_rtc_data *) malloc(sizeof(struct dreamcast_rtc_data)));
-	memset(d, 0, sizeof(struct dreamcast_rtc_data));
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    0x00710000, 0x100, dev_dreamcast_rtc_access, d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_eagle.c gxemul-0.7.0+dfsg/src/devices/dev_eagle.c
--- gxemul-0.6.2/src/devices/dev_eagle.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_eagle.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,194 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Motorola MPC105 "Eagle" host bridge
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_isa.h"
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+struct eagle_data {
+	struct interrupt irq;
+
+	struct pci_data	*pci_data;
+};
+
+
+DEVICE_ACCESS(eagle)
+{
+	struct eagle_data *d = (struct eagle_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int bus, dev, func, reg;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
+
+	/*
+	 *  Pass accesses to ISA ports 0xcf8 and 0xcfc onto bus_pci_*:
+	 */
+
+	switch (relative_addr) {
+
+	case 0:	/*  Address:  */
+		bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
+		bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
+		break;
+
+	case 4:	/*  Data:  */
+		bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
+		    &odata : &idata, len, writeflag);
+		break;
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
+
+	return 1;
+}
+
+
+DEVINIT(eagle)
+{
+	struct eagle_data *d;
+	uint64_t pci_io_offset, pci_mem_offset;
+	uint64_t isa_portbase = 0, isa_membase = 0;
+	uint64_t pci_portbase = 0, pci_membase = 0;
+	char pci_irq_base[300];
+	char isa_irq_base[300];
+
+	CHECK_ALLOCATION(d = (struct eagle_data *) malloc(sizeof(struct eagle_data)));
+	memset(d, 0, sizeof(struct eagle_data));
+
+	/*  The interrupt path to the CPU at which we are connected:  */
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	/*
+	 *  According to http://www.beatjapan.org/mirror/www.be.com/
+	 *  aboutbe/benewsletter/Issue27.html#Cookbook :
+	 *
+	 *  "HARDWARE MEMORY MAP
+	 *   The MPC105 defines the physical memory map of the system as
+	 *   follows:
+	 *
+	 *   Start        Size         Description
+	 *
+	 *   0x00000000   0x40000000   Physical RAM
+	 *   0x40000000   0x40000000   Other system memory
+	 *                             (motherboard glue regs)
+	 *   0x80000000   0x00800000   ISA I/O
+	 *   0x81000000   0x3E800000   PCI I/O
+	 *   0xBFFFFFF0   0x00000010   PCI/ISA interrupt acknowledge
+	 *   0xC0000000   0x3F000000   PCI memory
+	 *   0xFF000000   0x01000000   ROM/flash
+	 */
+
+	/*  TODO: Make these work like the BE web page stated...  */
+	pci_io_offset  = 0x80000000ULL;
+	pci_mem_offset = 0xc0000000ULL;
+	pci_portbase   = 0x00000000ULL;
+	pci_membase    = 0x00000000ULL;
+	isa_portbase   = 0x80000000ULL;
+	isa_membase    = 0xc0000000ULL;
+
+	switch (devinit->machine->machine_type) {
+	/* case MACHINE_BEBOX:
+		snprintf(pci_irq_base, sizeof(pci_irq_base), "%s.bebox",
+		    devinit->interrupt_path);
+		snprintf(isa_irq_base, sizeof(isa_irq_base), "%s.bebox.5",
+		    devinit->interrupt_path);
+		break; */
+	default:
+		snprintf(pci_irq_base, sizeof(pci_irq_base), "%s",
+		    devinit->interrupt_path);
+		snprintf(isa_irq_base, sizeof(isa_irq_base), "%s",
+		    devinit->interrupt_path);
+	}
+
+	/*  Create a PCI bus:  */
+	d->pci_data = bus_pci_init(devinit->machine, devinit->interrupt_path,
+	    pci_io_offset, pci_mem_offset,
+	    pci_portbase, pci_membase, pci_irq_base,
+	    isa_portbase, isa_membase, isa_irq_base);
+
+	/*  Add the PCI glue for the controller itself:  */
+	bus_pci_add(devinit->machine, d->pci_data,
+	    devinit->machine->memory, 0, 0, 0, "eagle");
+
+	/*  ADDR and DATA configuration ports in ISA space:  */
+	memory_device_register(devinit->machine->memory, "eagle",
+	    isa_portbase + BUS_PCI_ADDR, 8, dev_eagle_access, d,
+	    DM_DEFAULT, NULL);
+
+	switch (devinit->machine->machine_type) {
+
+	/* case MACHINE_BEBOX:
+		bus_isa_init(devinit->machine, isa_irq_base,
+		    BUS_ISA_IDE0 | BUS_ISA_VGA, isa_portbase, isa_membase);
+		bus_pci_add(devinit->machine, d->pci_data,
+		    devinit->machine->memory, 0, 11, 0, "i82378zb");
+		break; */
+
+	case MACHINE_PREP:
+		bus_pci_add(devinit->machine, d->pci_data,
+		    devinit->machine->memory, 0, 11, 0, "ibm_isa");
+		break;
+
+	case MACHINE_MVMEPPC:
+		bus_isa_init(devinit->machine, isa_irq_base,
+		    BUS_ISA_LPTBASE_3BC, isa_portbase, isa_membase);
+
+		switch (devinit->machine->machine_subtype) {
+		case MACHINE_MVMEPPC_1600:
+			bus_pci_add(devinit->machine, d->pci_data,
+			    devinit->machine->memory, 0, 11, 0, "i82378zb");
+			break;
+		default:fatal("unimplemented machine subtype for "
+			    "eagle/mvmeppc\n");
+			exit(1);
+		}
+		break;
+
+	default:fatal("unimplemented machine type for eagle\n");
+		exit(1);
+	}
+
+	devinit->return_ptr = d->pci_data;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_eagle.cc gxemul-0.7.0+dfsg/src/devices/dev_eagle.cc
--- gxemul-0.6.2/src/devices/dev_eagle.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_eagle.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,194 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Motorola MPC105 "Eagle" host bridge
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_isa.h"
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-struct eagle_data {
-	struct interrupt irq;
-
-	struct pci_data	*pci_data;
-};
-
-
-DEVICE_ACCESS(eagle)
-{
-	struct eagle_data *d = (struct eagle_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int bus, dev, func, reg;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
-
-	/*
-	 *  Pass accesses to ISA ports 0xcf8 and 0xcfc onto bus_pci_*:
-	 */
-
-	switch (relative_addr) {
-
-	case 0:	/*  Address:  */
-		bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
-		bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
-		break;
-
-	case 4:	/*  Data:  */
-		bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
-		    &odata : &idata, len, writeflag);
-		break;
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
-
-	return 1;
-}
-
-
-DEVINIT(eagle)
-{
-	struct eagle_data *d;
-	uint64_t pci_io_offset, pci_mem_offset;
-	uint64_t isa_portbase = 0, isa_membase = 0;
-	uint64_t pci_portbase = 0, pci_membase = 0;
-	char pci_irq_base[300];
-	char isa_irq_base[300];
-
-	CHECK_ALLOCATION(d = (struct eagle_data *) malloc(sizeof(struct eagle_data)));
-	memset(d, 0, sizeof(struct eagle_data));
-
-	/*  The interrupt path to the CPU at which we are connected:  */
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	/*
-	 *  According to http://www.beatjapan.org/mirror/www.be.com/
-	 *  aboutbe/benewsletter/Issue27.html#Cookbook :
-	 *
-	 *  "HARDWARE MEMORY MAP
-	 *   The MPC105 defines the physical memory map of the system as
-	 *   follows:
-	 *
-	 *   Start        Size         Description
-	 *
-	 *   0x00000000   0x40000000   Physical RAM
-	 *   0x40000000   0x40000000   Other system memory
-	 *                             (motherboard glue regs)
-	 *   0x80000000   0x00800000   ISA I/O
-	 *   0x81000000   0x3E800000   PCI I/O
-	 *   0xBFFFFFF0   0x00000010   PCI/ISA interrupt acknowledge
-	 *   0xC0000000   0x3F000000   PCI memory
-	 *   0xFF000000   0x01000000   ROM/flash
-	 */
-
-	/*  TODO: Make these work like the BE web page stated...  */
-	pci_io_offset  = 0x80000000ULL;
-	pci_mem_offset = 0xc0000000ULL;
-	pci_portbase   = 0x00000000ULL;
-	pci_membase    = 0x00000000ULL;
-	isa_portbase   = 0x80000000ULL;
-	isa_membase    = 0xc0000000ULL;
-
-	switch (devinit->machine->machine_type) {
-	/* case MACHINE_BEBOX:
-		snprintf(pci_irq_base, sizeof(pci_irq_base), "%s.bebox",
-		    devinit->interrupt_path);
-		snprintf(isa_irq_base, sizeof(isa_irq_base), "%s.bebox.5",
-		    devinit->interrupt_path);
-		break; */
-	default:
-		snprintf(pci_irq_base, sizeof(pci_irq_base), "%s",
-		    devinit->interrupt_path);
-		snprintf(isa_irq_base, sizeof(isa_irq_base), "%s",
-		    devinit->interrupt_path);
-	}
-
-	/*  Create a PCI bus:  */
-	d->pci_data = bus_pci_init(devinit->machine, devinit->interrupt_path,
-	    pci_io_offset, pci_mem_offset,
-	    pci_portbase, pci_membase, pci_irq_base,
-	    isa_portbase, isa_membase, isa_irq_base);
-
-	/*  Add the PCI glue for the controller itself:  */
-	bus_pci_add(devinit->machine, d->pci_data,
-	    devinit->machine->memory, 0, 0, 0, "eagle");
-
-	/*  ADDR and DATA configuration ports in ISA space:  */
-	memory_device_register(devinit->machine->memory, "eagle",
-	    isa_portbase + BUS_PCI_ADDR, 8, dev_eagle_access, d,
-	    DM_DEFAULT, NULL);
-
-	switch (devinit->machine->machine_type) {
-
-	/* case MACHINE_BEBOX:
-		bus_isa_init(devinit->machine, isa_irq_base,
-		    BUS_ISA_IDE0 | BUS_ISA_VGA, isa_portbase, isa_membase);
-		bus_pci_add(devinit->machine, d->pci_data,
-		    devinit->machine->memory, 0, 11, 0, "i82378zb");
-		break; */
-
-	case MACHINE_PREP:
-		bus_pci_add(devinit->machine, d->pci_data,
-		    devinit->machine->memory, 0, 11, 0, "ibm_isa");
-		break;
-
-	case MACHINE_MVMEPPC:
-		bus_isa_init(devinit->machine, isa_irq_base,
-		    BUS_ISA_LPTBASE_3BC, isa_portbase, isa_membase);
-
-		switch (devinit->machine->machine_subtype) {
-		case MACHINE_MVMEPPC_1600:
-			bus_pci_add(devinit->machine, d->pci_data,
-			    devinit->machine->memory, 0, 11, 0, "i82378zb");
-			break;
-		default:fatal("unimplemented machine subtype for "
-			    "eagle/mvmeppc\n");
-			exit(1);
-		}
-		break;
-
-	default:fatal("unimplemented machine type for eagle\n");
-		exit(1);
-	}
-
-	devinit->return_ptr = d->pci_data;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_ether.c gxemul-0.7.0+dfsg/src/devices/dev_ether.c
--- gxemul-0.6.2/src/devices/dev_ether.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ether.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,251 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: A simple ethernet controller, for the test machines
+ *
+ *  Basic "ethernet" network device. This is a simple test device which can
+ *  be used to send and receive packets to/from a simulated ethernet network.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "net.h"
+
+#include "testmachine/dev_ether.h"
+
+
+#define	DEV_ETHER_TICK_SHIFT	14
+
+struct ether_data {
+	struct nic_data		nic;
+
+	unsigned char		buf[DEV_ETHER_BUFFER_SIZE];
+	unsigned char		mac[6];
+
+	int			status;
+	int			packet_len;
+
+	struct interrupt	irq;
+};
+
+
+DEVICE_TICK(ether)
+{  
+	struct ether_data *d = (struct ether_data *) extra;
+	int r = 0;
+
+	d->status &= ~DEV_ETHER_STATUS_MORE_PACKETS_AVAILABLE;
+	if (cpu->machine->emul->net != NULL)
+		r = net_ethernet_rx_avail(cpu->machine->emul->net, &d->nic);
+	if (r)
+		d->status |= DEV_ETHER_STATUS_MORE_PACKETS_AVAILABLE;
+
+	if (d->status)
+		INTERRUPT_ASSERT(d->irq);
+	else
+		INTERRUPT_DEASSERT(d->irq);
+}
+
+
+DEVICE_ACCESS(ether_buf)
+{
+	struct ether_data *d = (struct ether_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		memcpy(d->buf + relative_addr, data, len);
+	else
+		memcpy(data, d->buf + relative_addr, len);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(ether)
+{
+	struct ether_data *d = (struct ether_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	unsigned char *incoming_ptr;
+	int incoming_len;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  Note: relative_addr + DEV_ETHER_BUFFER_SIZE to get the same
+	    offsets as in the header file:  */
+
+	switch (relative_addr + DEV_ETHER_BUFFER_SIZE) {
+
+	case DEV_ETHER_STATUS:
+		if (writeflag == MEM_READ) {
+			odata = d->status;
+			d->status = 0;
+			INTERRUPT_DEASSERT(d->irq);
+		} else
+			fatal("[ ether: WARNING: write to status ]\n");
+		break;
+
+	case DEV_ETHER_PACKETLENGTH:
+		if (writeflag == MEM_READ)
+			odata = d->packet_len;
+		else {
+			if ((int64_t)idata < 0) {
+				fatal("[ ether: ERROR: packet len too"
+				    " short (%i bytes) ]\n", (int)idata);
+				idata = (uint64_t) -1;
+			}
+			if (idata > DEV_ETHER_BUFFER_SIZE) {
+				fatal("[ ether: ERROR: packet len too"
+				    " large (%i bytes) ]\n", (int)idata);
+				idata = DEV_ETHER_BUFFER_SIZE;
+			}
+			d->packet_len = idata;
+		}
+		break;
+
+	case DEV_ETHER_COMMAND:
+		if (writeflag == MEM_READ) {
+			fatal("[ ether: WARNING: read from command ]\n");
+			break;
+		}
+
+		/*  Write:  */
+		switch (idata) {
+
+		case DEV_ETHER_COMMAND_RX:	/*  Receive:  */
+			if (cpu->machine->emul->net == NULL)
+				fatal("[ ether: RECEIVE but no net? ]\n");
+			else {
+				d->status &= ~DEV_ETHER_STATUS_PACKET_RECEIVED;
+				if (net_ethernet_rx(cpu->machine->emul->net,
+				    &d->nic, &incoming_ptr, &incoming_len)) {
+					d->status |=
+					    DEV_ETHER_STATUS_PACKET_RECEIVED;
+					if (incoming_len>DEV_ETHER_BUFFER_SIZE)
+						incoming_len =
+						    DEV_ETHER_BUFFER_SIZE;
+					memcpy(d->buf, incoming_ptr,
+					    incoming_len);
+					free(incoming_ptr);
+					d->packet_len = incoming_len;
+				}
+			}
+			dev_ether_tick(cpu, d);
+			break;
+
+		case DEV_ETHER_COMMAND_TX:	/*  Send  */
+			if (cpu->machine->emul->net == NULL)
+				fatal("[ ether: SEND but no net? ]\n");
+			else
+				net_ethernet_tx(cpu->machine->emul->net,
+				    &d->nic, d->buf, d->packet_len);
+			d->status &= ~DEV_ETHER_STATUS_PACKET_RECEIVED;
+			dev_ether_tick(cpu, d);
+			break;
+
+		default:fatal("[ ether: UNIMPLEMENTED command 0x"
+			    "%02x ]\n", idata);
+			cpu->running = 0;
+		}
+		break;
+
+	case DEV_ETHER_MAC:
+		if (writeflag == MEM_READ) {
+			fatal("[ ether: read of MAC is not allowed! ]\n");
+		} else {
+			// Write out the MAC address to the address given.
+			cpu->memory_rw(cpu, cpu->mem, idata, d->nic.mac_address,
+			    6, MEM_WRITE, CACHE_NONE);
+		}
+		break;
+
+	default:if (writeflag == MEM_WRITE) {
+			fatal("[ ether: unimplemented write to "
+			    "offset 0x%x: data=0x%x ]\n", (int)
+			    relative_addr, (int)idata);
+		} else {
+			fatal("[ ether: unimplemented read from "
+			    "offset 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(ether)
+{
+	struct ether_data *d;
+	size_t nlen;
+	char *n1, *n2;
+	char tmp[50];
+
+	CHECK_ALLOCATION(d = (struct ether_data *) malloc(sizeof(struct ether_data)));
+	memset(d, 0, sizeof(struct ether_data));
+
+	nlen = strlen(devinit->name) + 80;
+	CHECK_ALLOCATION(n1 = (char *) malloc(nlen));
+	CHECK_ALLOCATION(n2 = (char *) malloc(nlen));
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	net_generate_unique_mac(devinit->machine, d->nic.mac_address);
+	snprintf(tmp, sizeof(tmp), "%02x:%02x:%02x:%02x:%02x:%02x",
+	    d->nic.mac_address[0], d->nic.mac_address[1],
+	    d->nic.mac_address[2], d->nic.mac_address[3],
+	    d->nic.mac_address[4], d->nic.mac_address[5]);
+
+	snprintf(n1, nlen, "%s [%s]", devinit->name, tmp);
+	snprintf(n2, nlen, "%s [%s, control]", devinit->name, tmp);
+
+	memory_device_register(devinit->machine->memory, n1, devinit->addr,
+	    DEV_ETHER_BUFFER_SIZE, dev_ether_buf_access, (void *)d,
+	    DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK |
+	    DM_READS_HAVE_NO_SIDE_EFFECTS, d->buf);
+	memory_device_register(devinit->machine->memory, n2,
+	    devinit->addr + DEV_ETHER_BUFFER_SIZE,
+	    DEV_ETHER_LENGTH-DEV_ETHER_BUFFER_SIZE, dev_ether_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	net_add_nic(devinit->machine->emul->net, &d->nic);
+
+	machine_add_tickfunction(devinit->machine,
+	    dev_ether_tick, d, DEV_ETHER_TICK_SHIFT);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_ether.cc gxemul-0.7.0+dfsg/src/devices/dev_ether.cc
--- gxemul-0.6.2/src/devices/dev_ether.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ether.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,247 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: A simple ethernet controller, for the test machines
- *
- *  Basic "ethernet" network device. This is a simple test device which can
- *  be used to send and receive packets to/from a simulated ethernet network.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "net.h"
-
-#include "testmachine/dev_ether.h"
-
-
-#define	DEV_ETHER_TICK_SHIFT	14
-
-struct ether_data {
-	unsigned char		buf[DEV_ETHER_BUFFER_SIZE];
-	unsigned char		mac[6];
-
-	int			status;
-	int			packet_len;
-
-	struct interrupt	irq;
-};
-
-
-DEVICE_TICK(ether)
-{  
-	struct ether_data *d = (struct ether_data *) extra;
-	int r = 0;
-
-	d->status &= ~DEV_ETHER_STATUS_MORE_PACKETS_AVAILABLE;
-	if (cpu->machine->emul->net != NULL)
-		r = net_ethernet_rx_avail(cpu->machine->emul->net, d);
-	if (r)
-		d->status |= DEV_ETHER_STATUS_MORE_PACKETS_AVAILABLE;
-
-	if (d->status)
-		INTERRUPT_ASSERT(d->irq);
-	else
-		INTERRUPT_DEASSERT(d->irq);
-}
-
-
-DEVICE_ACCESS(ether_buf)
-{
-	struct ether_data *d = (struct ether_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		memcpy(d->buf + relative_addr, data, len);
-	else
-		memcpy(data, d->buf + relative_addr, len);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(ether)
-{
-	struct ether_data *d = (struct ether_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	unsigned char *incoming_ptr;
-	int incoming_len;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  Note: relative_addr + DEV_ETHER_BUFFER_SIZE to get the same
-	    offsets as in the header file:  */
-
-	switch (relative_addr + DEV_ETHER_BUFFER_SIZE) {
-
-	case DEV_ETHER_STATUS:
-		if (writeflag == MEM_READ) {
-			odata = d->status;
-			d->status = 0;
-			INTERRUPT_DEASSERT(d->irq);
-		} else
-			fatal("[ ether: WARNING: write to status ]\n");
-		break;
-
-	case DEV_ETHER_PACKETLENGTH:
-		if (writeflag == MEM_READ)
-			odata = d->packet_len;
-		else {
-			if ((int64_t)idata < 0) {
-				fatal("[ ether: ERROR: packet len too"
-				    " short (%i bytes) ]\n", (int)idata);
-				idata = (uint64_t) -1;
-			}
-			if (idata > DEV_ETHER_BUFFER_SIZE) {
-				fatal("[ ether: ERROR: packet len too"
-				    " large (%i bytes) ]\n", (int)idata);
-				idata = DEV_ETHER_BUFFER_SIZE;
-			}
-			d->packet_len = idata;
-		}
-		break;
-
-	case DEV_ETHER_COMMAND:
-		if (writeflag == MEM_READ) {
-			fatal("[ ether: WARNING: read from command ]\n");
-			break;
-		}
-
-		/*  Write:  */
-		switch (idata) {
-
-		case DEV_ETHER_COMMAND_RX:	/*  Receive:  */
-			if (cpu->machine->emul->net == NULL)
-				fatal("[ ether: RECEIVE but no net? ]\n");
-			else {
-				d->status &= ~DEV_ETHER_STATUS_PACKET_RECEIVED;
-				if (net_ethernet_rx(cpu->machine->emul->net,
-				    d, &incoming_ptr, &incoming_len)) {
-					d->status |=
-					    DEV_ETHER_STATUS_PACKET_RECEIVED;
-					if (incoming_len>DEV_ETHER_BUFFER_SIZE)
-						incoming_len =
-						    DEV_ETHER_BUFFER_SIZE;
-					memcpy(d->buf, incoming_ptr,
-					    incoming_len);
-					free(incoming_ptr);
-					d->packet_len = incoming_len;
-				}
-			}
-			dev_ether_tick(cpu, d);
-			break;
-
-		case DEV_ETHER_COMMAND_TX:	/*  Send  */
-			if (cpu->machine->emul->net == NULL)
-				fatal("[ ether: SEND but no net? ]\n");
-			else
-				net_ethernet_tx(cpu->machine->emul->net,
-				    d, d->buf, d->packet_len);
-			d->status &= ~DEV_ETHER_STATUS_PACKET_RECEIVED;
-			dev_ether_tick(cpu, d);
-			break;
-
-		default:fatal("[ ether: UNIMPLEMENTED command 0x"
-			    "%02x ]\n", idata);
-			cpu->running = 0;
-		}
-		break;
-
-	case DEV_ETHER_MAC:
-		if (writeflag == MEM_READ) {
-			fatal("[ ether: read of MAC is not allowed! ]\n");
-		} else {
-			// Write out the MAC address to the address given.
-			cpu->memory_rw(cpu, cpu->mem, idata, d->mac,
-			    6, MEM_WRITE, CACHE_NONE);
-		}
-		break;
-
-	default:if (writeflag == MEM_WRITE) {
-			fatal("[ ether: unimplemented write to "
-			    "offset 0x%x: data=0x%x ]\n", (int)
-			    relative_addr, (int)idata);
-		} else {
-			fatal("[ ether: unimplemented read from "
-			    "offset 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(ether)
-{
-	struct ether_data *d;
-	size_t nlen;
-	char *n1, *n2;
-	char tmp[50];
-
-	CHECK_ALLOCATION(d = (struct ether_data *) malloc(sizeof(struct ether_data)));
-	memset(d, 0, sizeof(struct ether_data));
-
-	nlen = strlen(devinit->name) + 80;
-	CHECK_ALLOCATION(n1 = (char *) malloc(nlen));
-	CHECK_ALLOCATION(n2 = (char *) malloc(nlen));
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	net_generate_unique_mac(devinit->machine, d->mac);
-	snprintf(tmp, sizeof(tmp), "%02x:%02x:%02x:%02x:%02x:%02x",
-	    d->mac[0], d->mac[1], d->mac[2], d->mac[3], d->mac[4], d->mac[5]);
-
-	snprintf(n1, nlen, "%s [%s]", devinit->name, tmp);
-	snprintf(n2, nlen, "%s [%s, control]", devinit->name, tmp);
-
-	memory_device_register(devinit->machine->memory, n1, devinit->addr,
-	    DEV_ETHER_BUFFER_SIZE, dev_ether_buf_access, (void *)d,
-	    DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK |
-	    DM_READS_HAVE_NO_SIDE_EFFECTS, d->buf);
-	memory_device_register(devinit->machine->memory, n2,
-	    devinit->addr + DEV_ETHER_BUFFER_SIZE,
-	    DEV_ETHER_LENGTH-DEV_ETHER_BUFFER_SIZE, dev_ether_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	net_add_nic(devinit->machine->emul->net, d, d->mac);
-
-	machine_add_tickfunction(devinit->machine,
-	    dev_ether_tick, d, DEV_ETHER_TICK_SHIFT);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_fb.c gxemul-0.7.0+dfsg/src/devices/dev_fb.c
--- gxemul-0.6.2/src/devices/dev_fb.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_fb.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,874 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Generic framebuffer device
+ *
+ *	DECstation VFB01 monochrome framebuffer, 1024x864
+ *	DECstation VFB02 8-bit color framebuffer, 1024x864
+ *	DECstation Maxine, 1024x768 8-bit color
+ *	Playstation 2 (24-bit color)
+ *	Generic (any resolution, several bit depths possible, useful for
+ *		testmachines)
+ *
+ *
+ *  TODO:  This should actually be independent of X11, but that
+ *         might be too hard to do right now.
+ *
+ *  TODO:  playstation 2 pixels are stored in another format, actually
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "x11.h"
+
+#ifdef WITH_X11
+#include <X11/Xlib.h>
+#include <X11/Xos.h>
+#include <X11/Xutil.h>
+#endif
+
+
+#define	FB_TICK_SHIFT		19
+
+
+/*  #define FB_DEBUG  */
+
+/*
+ *  set_grayscale_palette():
+ *
+ *  Fill d->rgb_palette with grayscale values. ncolors should
+ *  be something like 2, 4, 16, or 256.
+ */
+void set_grayscale_palette(struct vfb_data *d, int ncolors)
+{
+	int i, gray;
+
+	for (i=0; i<256; i++) {
+		gray = 255*i/(ncolors-1);
+		d->rgb_palette[i*3 + 0] = gray;
+		d->rgb_palette[i*3 + 1] = gray;
+		d->rgb_palette[i*3 + 2] = gray;
+	}
+}
+
+
+/*
+ *  set_blackwhite_palette():
+ *
+ *  Set color 0 = black, all others to white.
+ */
+void set_blackwhite_palette(struct vfb_data *d, int ncolors)
+{
+	int i, gray;
+
+	for (i=0; i<256; i++) {
+		gray = i==0? 0 : 255;
+		d->rgb_palette[i*3 + 0] = gray;
+		d->rgb_palette[i*3 + 1] = gray;
+		d->rgb_palette[i*3 + 2] = gray;
+	}
+}
+
+
+static void set_title(struct vfb_data *d)
+{
+	snprintf(d->title, sizeof(d->title),"GXemul: %ix%ix%i %s framebuffer",
+	    d->visible_xsize, d->visible_ysize, d->bit_depth, d->name);
+	d->title[sizeof(d->title)-1] = '\0';
+}
+
+
+/*
+ *  dev_fb_resize():
+ *
+ *  Resize a framebuffer window. (This functionality is probably a bit buggy,
+ *  because I didn't think of including it from the start.)
+ *
+ *  SUPER-IMPORTANT: Anyone who resizes a framebuffer by calling this function
+ *  must also clear all dyntrans address translations manually, in all cpus
+ *  which might have access to the framebuffer!
+ */
+void dev_fb_resize(struct vfb_data *d, int new_xsize, int new_ysize)
+{
+	unsigned char *new_framebuffer;
+	int y, new_bytes_per_line;
+	size_t size;
+
+	if (d == NULL) {
+		fatal("dev_fb_resize(): d == NULL\n");
+		return;
+	}
+
+	if (new_xsize < 10 || new_ysize < 10) {
+		fatal("dev_fb_resize(): size too small.\n");
+		exit(1);
+	}
+
+	new_bytes_per_line = new_xsize * d->bit_depth / 8;
+	size = new_ysize * new_bytes_per_line;
+
+	CHECK_ALLOCATION(new_framebuffer = (unsigned char *) malloc(size));
+
+	/*  Copy the old framebuffer to the new:  */
+	if (d->framebuffer != NULL) {
+		for (y=0; y<new_ysize; y++) {
+			size_t fromofs = d->bytes_per_line * y;
+			size_t toofs = new_bytes_per_line * y;
+			size_t len_to_copy = d->bytes_per_line <
+			    new_bytes_per_line? d->bytes_per_line	
+			    : new_bytes_per_line;
+			memset(new_framebuffer + toofs, 0, new_bytes_per_line);
+			if (y < d->x11_ysize)
+				memmove(new_framebuffer + toofs,
+				    d->framebuffer + fromofs, len_to_copy);
+		}
+
+		free(d->framebuffer);
+	}
+
+	d->framebuffer = new_framebuffer;
+	d->framebuffer_size = size;
+
+	if (new_xsize > d->xsize || new_ysize > d->ysize) {
+		d->update_x1 = d->update_y1 = 0;
+		d->update_x2 = new_xsize - 1;
+		d->update_y2 = new_ysize - 1;
+	}
+
+	d->bytes_per_line = new_bytes_per_line;
+	d->xsize = d->visible_xsize = new_xsize;
+	d->ysize = d->visible_ysize = new_ysize;
+
+	d->x11_xsize = d->xsize / d->vfb_scaledown;
+	d->x11_ysize = d->ysize / d->vfb_scaledown;
+
+	memory_device_update_data(d->memory, d, d->framebuffer);
+
+	set_title(d);
+
+#ifdef WITH_X11
+	if (d->fb_window != NULL) {
+		x11_fb_resize(d->fb_window, d->x11_xsize, d->x11_ysize);
+		if (d->fb_window->name != NULL)
+			free(d->fb_window->name);
+		d->fb_window->name = strdup(d->title);
+		x11_set_standard_properties(d->fb_window);
+	}
+#endif
+}
+
+
+/*
+ *  dev_fb_setcursor():
+ */
+void dev_fb_setcursor(struct vfb_data *d, int cursor_x, int cursor_y, int on,
+	int cursor_xsize, int cursor_ysize)
+{
+	if (cursor_x < 0)
+		cursor_x = 0;
+	if (cursor_y < 0)
+		cursor_y = 0;
+	if (cursor_x + cursor_xsize >= d->xsize)
+		cursor_x = d->xsize - cursor_xsize;
+	if (cursor_y + cursor_ysize >= d->ysize)
+		cursor_y = d->ysize - cursor_ysize;
+
+#ifdef WITH_X11
+	if (d->fb_window != NULL) {
+		d->fb_window->cursor_x      = cursor_x;
+		d->fb_window->cursor_y      = cursor_y;
+		d->fb_window->cursor_on     = on;
+		d->fb_window->cursor_xsize  = cursor_xsize;
+		d->fb_window->cursor_ysize  = cursor_ysize;
+	}
+#endif
+
+	/*  debug("dev_fb_setcursor(%i,%i, size %i,%i, on=%i)\n",
+	    cursor_x, cursor_y, cursor_xsize, cursor_ysize, on);  */
+}
+
+
+/*
+ *  framebuffer_blockcopyfill():
+ *
+ *  This function should be used by devices that are capable of doing
+ *  block copy/fill.
+ *
+ *  If fillflag is non-zero, then fill_[rgb] should contain the color
+ *  with which to fill. (In 8-bit mode, only fill_r is used.)
+ *
+ *  If fillflag is zero, copy mode is used, and from_[xy] should contain
+ *  the offset on the framebuffer where we should copy from.
+ *
+ *  NOTE:  Overlapping copies are undefined!
+ */
+void framebuffer_blockcopyfill(struct vfb_data *d, int fillflag, int fill_r,
+	int fill_g, int fill_b, int x1, int y1, int x2, int y2,
+	int from_x, int from_y)
+{
+	int x, y;
+	size_t from_ofs, dest_ofs, linelen;
+
+	if (fillflag)
+		debug("framebuffer_blockcopyfill(FILL, %i,%i, %i,%i, "
+		    "color %i,%i,%i)\n", x1,y1, x2,y2, fill_r, fill_g, fill_b);
+	else
+		debug("framebuffer_blockcopyfill(COPY, %i,%i, %i,%i, from "
+		    "%i,%i)\n", x1,y1, x2,y2, from_x,from_y);
+
+	/*  Clip x:  */
+	if (x1 < 0)		x1 = 0;
+	if (x1 >= d->xsize)	x1 = d->xsize-1;
+	if (x2 < 0)		x2 = 0;
+	if (x2 >= d->xsize)	x2 = d->xsize-1;
+
+	dest_ofs = d->bytes_per_line * y1 + (d->bit_depth/8) * x1;
+	linelen = (x2-x1 + 1) * (d->bit_depth/8);
+	/*  NOTE: linelen is nr of bytes, not pixels  */
+
+	if (fillflag) {
+		for (y=y1; y<=y2; y++) {
+			if (y>=0 && y<d->ysize) {
+				unsigned char *buf =
+				    d->framebuffer + dest_ofs;
+
+				if (d->bit_depth == 24) {
+					for (x=0; x<(ssize_t)linelen && x <
+					    (int) sizeof(buf); x += 3) {
+						buf[x] = fill_r;
+						buf[x+1] = fill_g;
+						buf[x+2] = fill_b;
+					}
+				} else if (d->bit_depth == 8) {
+					memset(buf, fill_r, linelen);
+				} else {
+					fatal("Unimplemented bit-depth (%i)"
+					    " for fb fill\n", d->bit_depth);
+					exit(1);
+				}
+			}
+
+			dest_ofs += d->bytes_per_line;
+		}
+	} else {
+		from_ofs = d->bytes_per_line * from_y +
+		    (d->bit_depth/8) * from_x;
+		for (y=y1; y<=y2; y++) {
+			if (y >= 0 && y < d->ysize) {
+				if (from_y >= 0 && from_y < d->ysize)
+					memmove(d->framebuffer + dest_ofs,
+					    d->framebuffer + from_ofs, linelen);
+				else
+					memset(d->framebuffer + dest_ofs,
+					    0, linelen);
+			}
+			from_y ++;
+			from_ofs += d->bytes_per_line;
+			dest_ofs += d->bytes_per_line;
+		}
+	}
+
+	if (x1 < d->update_x1 || d->update_x1 == -1)	d->update_x1 = x1;
+	if (x1 > d->update_x2 || d->update_x2 == -1)	d->update_x2 = x1;
+	if (x2 < d->update_x1 || d->update_x1 == -1)	d->update_x1 = x2;
+	if (x2 > d->update_x2 || d->update_x2 == -1)	d->update_x2 = x2;
+
+	if (y1 < d->update_y1 || d->update_y1 == -1)	d->update_y1 = y1;
+	if (y1 > d->update_y2 || d->update_y2 == -1)	d->update_y2 = y1;
+	if (y2 < d->update_y1 || d->update_y1 == -1)	d->update_y1 = y2;
+	if (y2 > d->update_y2 || d->update_y2 == -1)	d->update_y2 = y2;
+}
+
+
+#ifdef WITH_X11
+
+#define	REDRAW	redraw_fallback
+#include "fb_include.c"
+#undef REDRAW
+
+#define FB_24
+#define REDRAW	redraw_24
+#include "fb_include.c"
+#undef REDRAW
+#undef FB_24
+#define FB_16
+#define REDRAW	redraw_16
+#include "fb_include.c"
+#undef FB_16
+#undef REDRAW
+#define FB_15
+#define REDRAW	redraw_15
+#include "fb_include.c"
+#undef REDRAW
+#undef FB_15
+
+#define FB_BO
+#define FB_24
+#define REDRAW	redraw_24_bo
+#include "fb_include.c"
+#undef REDRAW
+#undef FB_24
+#define FB_16
+#define REDRAW	redraw_16_bo
+#include "fb_include.c"
+#undef FB_16
+#undef REDRAW
+#define FB_15
+#define REDRAW	redraw_15_bo
+#include "fb_include.c"
+#undef REDRAW
+#undef FB_15
+#undef FB_BO
+
+#define FB_SCALEDOWN
+
+#define	REDRAW	redraw_fallback_sd
+#include "fb_include.c"
+#undef REDRAW
+
+#define FB_24
+#define REDRAW	redraw_24_sd
+#include "fb_include.c"
+#undef REDRAW
+#undef FB_24
+#define FB_16
+#define REDRAW	redraw_16_sd
+#include "fb_include.c"
+#undef FB_16
+#undef REDRAW
+#define FB_15
+#define REDRAW	redraw_15_sd
+#include "fb_include.c"
+#undef REDRAW
+#undef FB_15
+
+#define FB_BO
+#define FB_24
+#define REDRAW	redraw_24_bo_sd
+#include "fb_include.c"
+#undef REDRAW
+#undef FB_24
+#define FB_16
+#define REDRAW	redraw_16_bo_sd
+#include "fb_include.c"
+#undef FB_16
+#undef REDRAW
+#define FB_15
+#define REDRAW	redraw_15_bo_sd
+#include "fb_include.c"
+#undef REDRAW
+#undef FB_15
+#undef FB_BO
+
+void (*redraw[2 * 4 * 2])(struct vfb_data *, int, int) = {
+	redraw_fallback, redraw_fallback,
+	redraw_15, redraw_15_bo,
+	redraw_16, redraw_16_bo,
+	redraw_24, redraw_24_bo,
+	redraw_fallback_sd, redraw_fallback_sd,
+	redraw_15_sd, redraw_15_bo_sd,
+	redraw_16_sd, redraw_16_bo_sd,
+	redraw_24_sd, redraw_24_bo_sd  };
+
+#endif	/*  WITH_X11  */
+
+
+DEVICE_TICK(fb)
+{
+	struct vfb_data *d = (struct vfb_data *) extra;
+#ifdef WITH_X11
+	int need_to_flush_x11 = 0;
+	int need_to_redraw_cursor = 0;
+#endif
+
+	if (!cpu->machine->x11_md.in_use)
+		return;
+
+	do {
+		uint64_t high, low = (uint64_t)(int64_t) -1;
+		int x, y;
+
+		memory_device_dyntrans_access(cpu, cpu->mem,
+		    extra, &low, &high);
+		if ((int64_t)low == -1)
+			break;
+
+		/*  printf("low=%016llx high=%016llx\n",
+		    (long long)low, (long long)high);  */
+
+		x = (low % d->bytes_per_line) * 8 / d->bit_depth;
+		y = low / d->bytes_per_line;
+		if (x < d->update_x1 || d->update_x1 == -1)
+			d->update_x1 = x;
+		if (x > d->update_x2 || d->update_x2 == -1)
+			d->update_x2 = x;
+		if (y < d->update_y1 || d->update_y1 == -1)
+			d->update_y1 = y;
+		if (y > d->update_y2 || d->update_y2 == -1)
+			d->update_y2 = y;
+
+		x = ((low+7) % d->bytes_per_line) * 8 / d->bit_depth;
+		y = (low+7) / d->bytes_per_line;
+		if (x < d->update_x1 || d->update_x1 == -1)
+			d->update_x1 = x;
+		if (x > d->update_x2 || d->update_x2 == -1)
+			d->update_x2 = x;
+		if (y < d->update_y1 || d->update_y1 == -1)
+			d->update_y1 = y;
+		if (y > d->update_y2 || d->update_y2 == -1)
+			d->update_y2 = y;
+
+		x = (high % d->bytes_per_line) * 8 / d->bit_depth;
+		y = high / d->bytes_per_line;
+		if (x < d->update_x1 || d->update_x1 == -1)
+			d->update_x1 = x;
+		if (x > d->update_x2 || d->update_x2 == -1)
+			d->update_x2 = x;
+		if (y < d->update_y1 || d->update_y1 == -1)
+			d->update_y1 = y;
+		if (y > d->update_y2 || d->update_y2 == -1)
+			d->update_y2 = y;
+
+		x = ((high+7) % d->bytes_per_line) * 8 / d->bit_depth;
+		y = (high+7) / d->bytes_per_line;
+		if (x < d->update_x1 || d->update_x1 == -1)
+			d->update_x1 = x;
+		if (x > d->update_x2 || d->update_x2 == -1)
+			d->update_x2 = x;
+		if (y < d->update_y1 || d->update_y1 == -1)
+			d->update_y1 = y;
+		if (y > d->update_y2 || d->update_y2 == -1)
+			d->update_y2 = y;
+
+		/*
+		 *  An update covering more than one line will automatically
+		 *  force an update of all the affected lines:
+		 */
+		if (d->update_y1 != d->update_y2) {
+			d->update_x1 = 0;
+			d->update_x2 = d->xsize-1;
+		}
+	} while (0);
+
+#ifdef WITH_X11
+	/*  Do we need to redraw the cursor?  */
+	if (d->fb_window->cursor_on != d->fb_window->OLD_cursor_on ||
+	    d->fb_window->cursor_x != d->fb_window->OLD_cursor_x ||
+	    d->fb_window->cursor_y != d->fb_window->OLD_cursor_y ||
+	    d->fb_window->cursor_xsize != d->fb_window->OLD_cursor_xsize ||
+	    d->fb_window->cursor_ysize != d->fb_window->OLD_cursor_ysize)
+		need_to_redraw_cursor = 1;
+
+	if (d->update_x2 != -1) {
+		if (((d->update_x1 >= d->fb_window->OLD_cursor_x &&
+		      d->update_x1 < (d->fb_window->OLD_cursor_x +
+		      d->fb_window->OLD_cursor_xsize)) ||
+		     (d->update_x2 >= d->fb_window->OLD_cursor_x &&
+		      d->update_x2 < (d->fb_window->OLD_cursor_x +
+		      d->fb_window->OLD_cursor_xsize)) ||
+		     (d->update_x1 <  d->fb_window->OLD_cursor_x &&
+		      d->update_x2 >= (d->fb_window->OLD_cursor_x +
+		      d->fb_window->OLD_cursor_xsize)) ) &&
+		   ( (d->update_y1 >= d->fb_window->OLD_cursor_y &&
+		      d->update_y1 < (d->fb_window->OLD_cursor_y +
+		      d->fb_window->OLD_cursor_ysize)) ||
+		     (d->update_y2 >= d->fb_window->OLD_cursor_y &&
+		      d->update_y2 < (d->fb_window->OLD_cursor_y +
+		      d->fb_window->OLD_cursor_ysize)) ||
+		     (d->update_y1 <  d->fb_window->OLD_cursor_y &&
+		      d->update_y2 >= (d->fb_window->OLD_cursor_y +
+		     d->fb_window->OLD_cursor_ysize)) ) )
+			need_to_redraw_cursor = 1;
+	}
+
+	if (need_to_redraw_cursor) {
+		/*  Remove old cursor, if any:  */
+		if (d->fb_window->OLD_cursor_on) {
+			XPutImage(d->fb_window->x11_display,
+			    d->fb_window->x11_fb_window,
+			    d->fb_window->x11_fb_gc, d->fb_window->fb_ximage,
+			    d->fb_window->OLD_cursor_x/d->vfb_scaledown,
+			    d->fb_window->OLD_cursor_y/d->vfb_scaledown,
+			    d->fb_window->OLD_cursor_x/d->vfb_scaledown,
+			    d->fb_window->OLD_cursor_y/d->vfb_scaledown,
+			    d->fb_window->OLD_cursor_xsize/d->vfb_scaledown + 1,
+			    d->fb_window->OLD_cursor_ysize/d->vfb_scaledown +1);
+		}
+	}
+#endif
+
+	if (d->update_x2 != -1) {
+#ifdef WITH_X11
+		int y;
+		int addr, addr2;
+#endif
+		int q = d->vfb_scaledown;
+
+		if (d->update_x1 >= d->visible_xsize)
+			d->update_x1 = d->visible_xsize - 1;
+		if (d->update_x2 >= d->visible_xsize)
+			d->update_x2 = d->visible_xsize - 1;
+		if (d->update_y1 >= d->visible_ysize)
+			d->update_y1 = d->visible_ysize - 1;
+		if (d->update_y2 >= d->visible_ysize)
+			d->update_y2 = d->visible_ysize - 1;
+
+		/*  Without these, we might miss the rightmost/bottom pixel:  */
+		d->update_x2 += (q - 1);
+		d->update_y2 += (q - 1);
+
+		d->update_x1 = d->update_x1 / q * q;
+		d->update_x2 = d->update_x2 / q * q;
+		d->update_y1 = d->update_y1 / q * q;
+		d->update_y2 = d->update_y2 / q * q;
+
+#ifdef WITH_X11
+		addr  = d->update_y1 * d->bytes_per_line +
+		    d->update_x1 * d->bit_depth / 8;
+		addr2 = d->update_y1 * d->bytes_per_line +
+		    d->update_x2 * d->bit_depth / 8;
+
+		for (y=d->update_y1; y<=d->update_y2; y+=q) {
+			d->redraw_func(d, addr, addr2 - addr);
+			addr  += d->bytes_per_line * q;
+			addr2 += d->bytes_per_line * q;
+		}
+
+		XPutImage(d->fb_window->x11_display, d->fb_window->
+		    x11_fb_window, d->fb_window->x11_fb_gc, d->fb_window->
+		    fb_ximage, d->update_x1/d->vfb_scaledown, d->update_y1/
+		    d->vfb_scaledown, d->update_x1/d->vfb_scaledown,
+		    d->update_y1/d->vfb_scaledown,
+		    (d->update_x2 - d->update_x1)/d->vfb_scaledown + 1,
+		    (d->update_y2 - d->update_y1)/d->vfb_scaledown + 1);
+
+		need_to_flush_x11 = 1;
+#endif
+
+		d->update_x1 = d->update_y1 = 99999;
+		d->update_x2 = d->update_y2 = -1;
+	}
+
+#ifdef WITH_X11
+	if (need_to_redraw_cursor) {
+		/*  Paint new cursor:  */
+		if (d->fb_window->cursor_on) {
+			x11_redraw_cursor(cpu->machine,
+			    d->fb_window->fb_number);
+			d->fb_window->OLD_cursor_on = d->fb_window->cursor_on;
+			d->fb_window->OLD_cursor_x = d->fb_window->cursor_x;
+			d->fb_window->OLD_cursor_y = d->fb_window->cursor_y;
+			d->fb_window->OLD_cursor_xsize = d->fb_window->
+			    cursor_xsize;
+			d->fb_window->OLD_cursor_ysize = d->fb_window->
+			    cursor_ysize;
+			need_to_flush_x11 = 1;
+		}
+	}
+#endif
+
+#ifdef WITH_X11
+	if (need_to_flush_x11)
+		XFlush(d->fb_window->x11_display);
+#endif
+}
+
+
+DEVICE_ACCESS(fb)
+{
+	struct vfb_data *d = (struct vfb_data *) extra;
+	size_t i;
+
+#ifdef FB_DEBUG
+	if (writeflag == MEM_WRITE) { if (data[0]) {
+		fatal("[ dev_fb: write  to addr=%08lx, data = ",
+		    (long)relative_addr);
+		for (i=0; i<len; i++)
+			fatal("%02x ", data[i]);
+		fatal("]\n");
+	} else {
+		fatal("[ dev_fb: read from addr=%08lx, data = ",
+		    (long)relative_addr);
+		for (i=0; i<len; i++)
+			fatal("%02x ", d->framebuffer[relative_addr + i]);
+		fatal("]\n");
+	}
+#endif
+
+	if (relative_addr >= d->framebuffer_size)
+		return 0;
+
+	/*  See if a write actually modifies the framebuffer contents:  */
+	if (writeflag == MEM_WRITE) {
+		for (i=0; i<len; i++) {
+			if (data[i] != d->framebuffer[relative_addr + i])
+				break;
+
+			/*  If all bytes are equal to what is already stored
+			    in the framebuffer, then simply return:  */
+			if (i == len-1)
+				return 1;
+		}
+	}
+
+	/*
+	 *  If the framebuffer is modified, then we should keep a track
+	 *  of which area(s) we modify, so that the display isn't updated
+	 *  unnecessarily.
+	 */
+	if (writeflag == MEM_WRITE && cpu->machine->x11_md.in_use) {
+		int x, y, x2,y2;
+
+		x = (relative_addr % d->bytes_per_line) * 8 / d->bit_depth;
+		y = relative_addr / d->bytes_per_line;
+		x2 = ((relative_addr + len) % d->bytes_per_line)
+		    * 8 / d->bit_depth;
+		y2 = (relative_addr + len) / d->bytes_per_line;
+
+		if (x < d->update_x1 || d->update_x1 == -1)
+			d->update_x1 = x;
+		if (x > d->update_x2 || d->update_x2 == -1)
+			d->update_x2 = x;
+
+		if (y < d->update_y1 || d->update_y1 == -1)
+			d->update_y1 = y;
+		if (y > d->update_y2 || d->update_y2 == -1)
+			d->update_y2 = y;
+
+		if (x2 < d->update_x1 || d->update_x1 == -1)
+			d->update_x1 = x2;
+		if (x2 > d->update_x2 || d->update_x2 == -1)
+			d->update_x2 = x2;
+
+		if (y2 < d->update_y1 || d->update_y1 == -1)
+			d->update_y1 = y2;
+		if (y2 > d->update_y2 || d->update_y2 == -1)
+			d->update_y2 = y2;
+
+		/*
+		 *  An update covering more than one line will automatically
+		 *  force an update of all the affected lines:
+		 */
+		if (y != y2) {
+			d->update_x1 = 0;
+			d->update_x2 = d->xsize-1;
+		}
+	}
+
+	/*
+	 *  Read from/write to the framebuffer:
+	 *  (TODO: take the color_plane_mask into account)
+	 *
+	 *  Calling memcpy() is probably overkill, as it usually is just one
+	 *  or a few bytes that are read/written at a time.
+	 */
+	if (writeflag == MEM_WRITE) {
+		if (len > 8)
+			memcpy(d->framebuffer + relative_addr, data, len);
+		else {
+			for (i=0; i<len; i++)
+				d->framebuffer[relative_addr + i] = data[i];
+		}
+	} else {
+		if (len > 8)
+			memcpy(data, d->framebuffer + relative_addr, len);
+		else {
+			for (i=0; i<len; i++)
+				data[i] = d->framebuffer[relative_addr + i];
+		}
+	}
+
+	return 1;
+}
+
+
+/*
+ *  dev_fb_init():
+ *
+ *  This function is big and ugly, but the point is to initialize a framebuffer
+ *  device. :-)
+ *
+ *  visible_xsize and visible_ysize are the sizes of the visible display area.
+ *  xsize and ysize tell how much memory is actually allocated (for example
+ *  visible_xsize could be 640, but xsize could be 1024, for better alignment).
+ *
+ *  vfb_type is useful for selecting special features.
+ *
+ *  type = VFB_GENERIC is the most useful type, especially when bit_depth = 24.
+ *
+ *  VFB_DEC_VFB01, _VFB02, and VFB_DEC_MAXINE are DECstation specific.
+ *
+ *  VFB_HPC is like generic, but the color encoding is done as on HPCmips
+ *  and Dreamcast.
+ *
+ *  VFB_REVERSEBITS is like generic, but with bit order reversed.
+ *
+ *  If bit_depth = -15 (note the minus sign), then a special hack is used for
+ *  the Playstation Portable's 5-bit R, 5-bit G, 5-bit B.
+ */
+struct vfb_data *dev_fb_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, int vfb_type, int visible_xsize, int visible_ysize,
+	int xsize, int ysize, int bit_depth, const char *name)
+{
+	struct vfb_data *d;
+	size_t size, nlen;
+	int flags;
+	int reverse_start = 0;
+	char *name2;
+
+	CHECK_ALLOCATION(d = (struct vfb_data *) malloc(sizeof(struct vfb_data)));
+	memset(d, 0, sizeof(struct vfb_data));
+
+	if (vfb_type & VFB_REVERSE_START) {
+		vfb_type &= ~VFB_REVERSE_START;
+		reverse_start = 1;
+	}
+
+	d->memory = mem;
+	d->vfb_type = vfb_type;
+
+	/*  Defaults:  */
+	d->xsize = xsize;  d->visible_xsize = visible_xsize;
+	d->ysize = ysize;  d->visible_ysize = visible_ysize;
+
+	d->bit_depth = bit_depth;
+
+	if (bit_depth == 15) {
+		d->color32k = 1;
+		bit_depth = d->bit_depth = 16;
+	} else if (bit_depth == -15) {
+		d->psp_15bit = 1;
+		bit_depth = d->bit_depth = 16;
+	}
+
+	/*  Specific types:  */
+	switch (vfb_type) {
+	case VFB_DEC_VFB01:
+		/*  DECstation VFB01 (monochrome)  */
+		d->xsize = 2048;  d->visible_xsize = 1024;
+		d->ysize = 1024;  d->visible_ysize = 864;
+		d->bit_depth = 1;
+		break;
+	case VFB_DEC_VFB02:
+		/*  DECstation VFB02 (color)  */
+		d->xsize = 1024;  d->visible_xsize = 1024;
+		d->ysize = 1024;  d->visible_ysize = 864;
+		d->bit_depth = 8;
+		break;
+	case VFB_DEC_MAXINE:
+		/*  DECstation Maxine (1024x768x8)  */
+		d->xsize = 1024; d->visible_xsize = d->xsize;
+		d->ysize = 768;  d->visible_ysize = d->ysize;
+		d->bit_depth = 8;
+		break;
+	case VFB_PLAYSTATION2:
+		/*  Playstation 2  */
+		d->xsize = xsize;  d->visible_xsize = d->xsize;
+		d->ysize = ysize;  d->visible_ysize = d->ysize;
+		d->bit_depth = 24;
+		break;
+	}
+
+	if (d->bit_depth == 2 || d->bit_depth == 4)
+		set_grayscale_palette(d, 1 << d->bit_depth);
+	else if (d->bit_depth == 8 || d->bit_depth == 1)
+		set_blackwhite_palette(d, 1 << d->bit_depth);
+
+	d->vfb_scaledown = machine->x11_md.scaledown;
+
+	d->bytes_per_line = d->xsize * d->bit_depth / 8;
+	size = d->ysize * d->bytes_per_line;
+
+	CHECK_ALLOCATION(d->framebuffer = (unsigned char *) malloc(size));
+
+	/*  Clear the framebuffer (all black pixels):  */
+	d->framebuffer_size = size;
+	memset(d->framebuffer, reverse_start? 255 : 0, size);
+
+	d->x11_xsize = d->visible_xsize / d->vfb_scaledown;
+	d->x11_ysize = d->visible_ysize / d->vfb_scaledown;
+
+	/*  Only "update" from the start if we need to fill with white.  */
+	/*  (The Ximage will be black from the start anyway.)  */
+	if (reverse_start) {
+		d->update_x1 = d->update_y1 = 0;
+		d->update_x2 = d->xsize - 1;
+		d->update_y2 = d->ysize - 1;
+	} else {
+		d->update_x1 = d->update_y1 = 99999;
+		d->update_x2 = d->update_y2 = -1;
+	}
+
+	CHECK_ALLOCATION(d->name = strdup(name));
+	set_title(d);
+
+#ifdef WITH_X11
+	if (machine->x11_md.in_use) {
+		int i = 0;
+		d->fb_window = x11_fb_init(d->x11_xsize, d->x11_ysize,
+		    d->title, machine->x11_md.scaledown, machine);
+		switch (d->fb_window->x11_screen_depth) {
+		case 15: i = 2; break;
+		case 16: i = 4; break;
+		case 24: i = 6; break;
+		}
+		if (d->fb_window->fb_ximage->byte_order)
+			i ++;
+		if (d->vfb_scaledown > 1)
+			i += 8;
+		d->redraw_func = redraw[i];
+	} else
+#endif
+		d->fb_window = NULL;
+
+	nlen = strlen(name) + 10;
+	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
+
+	snprintf(name2, nlen, "fb [%s]", name);
+
+	flags = DM_DEFAULT;
+	if ((baseaddr & 0xfff) == 0)
+		flags = DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK;
+
+	flags |= DM_READS_HAVE_NO_SIDE_EFFECTS;
+
+	memory_device_register(mem, name2, baseaddr, size, dev_fb_access,
+	    d, flags, d->framebuffer);
+
+	machine_add_tickfunction(machine, dev_fb_tick, d, FB_TICK_SHIFT);
+
+	return d;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_fb.cc gxemul-0.7.0+dfsg/src/devices/dev_fb.cc
--- gxemul-0.6.2/src/devices/dev_fb.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_fb.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,967 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Generic framebuffer device
- *
- *	DECstation VFB01 monochrome framebuffer, 1024x864
- *	DECstation VFB02 8-bit color framebuffer, 1024x864
- *	DECstation Maxine, 1024x768 8-bit color
- *	Playstation 2 (24-bit color)
- *	Generic (any resolution, several bit depths possible, useful for
- *		testmachines)
- *
- *
- *  TODO:  This should actually be independent of X11, but that
- *         might be too hard to do right now.
- *
- *  TODO:  playstation 2 pixels are stored in another format, actually
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "x11.h"
-
-#ifdef WITH_X11
-#include <X11/Xlib.h>
-#include <X11/Xos.h>
-#include <X11/Xutil.h>
-#endif
-
-
-#define	FB_TICK_SHIFT		19
-
-
-/*  #define FB_DEBUG  */
-
-/*
- *  set_grayscale_palette():
- *
- *  Fill d->rgb_palette with grayscale values. ncolors should
- *  be something like 2, 4, 16, or 256.
- */
-void set_grayscale_palette(struct vfb_data *d, int ncolors)
-{
-	int i, gray;
-
-	for (i=0; i<256; i++) {
-		gray = 255*i/(ncolors-1);
-		d->rgb_palette[i*3 + 0] = gray;
-		d->rgb_palette[i*3 + 1] = gray;
-		d->rgb_palette[i*3 + 2] = gray;
-	}
-}
-
-
-/*
- *  set_blackwhite_palette():
- *
- *  Set color 0 = black, all others to white.
- */
-void set_blackwhite_palette(struct vfb_data *d, int ncolors)
-{
-	int i, gray;
-
-	for (i=0; i<256; i++) {
-		gray = i==0? 0 : 255;
-		d->rgb_palette[i*3 + 0] = gray;
-		d->rgb_palette[i*3 + 1] = gray;
-		d->rgb_palette[i*3 + 2] = gray;
-	}
-}
-
-
-static void set_title(struct vfb_data *d)
-{
-	snprintf(d->title, sizeof(d->title),"GXemul: %ix%ix%i %s framebuffer",
-	    d->visible_xsize, d->visible_ysize, d->bit_depth, d->name);
-	d->title[sizeof(d->title)-1] = '\0';
-}
-
-
-/*
- *  dev_fb_resize():
- *
- *  Resize a framebuffer window. (This functionality is probably a bit buggy,
- *  because I didn't think of including it from the start.)
- *
- *  SUPER-IMPORTANT: Anyone who resizes a framebuffer by calling this function
- *  must also clear all dyntrans address translations manually, in all cpus
- *  which might have access to the framebuffer!
- */
-void dev_fb_resize(struct vfb_data *d, int new_xsize, int new_ysize)
-{
-	unsigned char *new_framebuffer;
-	int y, new_bytes_per_line;
-	size_t size;
-
-	if (d == NULL) {
-		fatal("dev_fb_resize(): d == NULL\n");
-		return;
-	}
-
-	if (new_xsize < 10 || new_ysize < 10) {
-		fatal("dev_fb_resize(): size too small.\n");
-		exit(1);
-	}
-
-	new_bytes_per_line = new_xsize * d->bit_depth / 8;
-	size = new_ysize * new_bytes_per_line;
-
-	CHECK_ALLOCATION(new_framebuffer = (unsigned char *) malloc(size));
-
-	/*  Copy the old framebuffer to the new:  */
-	if (d->framebuffer != NULL) {
-		for (y=0; y<new_ysize; y++) {
-			size_t fromofs = d->bytes_per_line * y;
-			size_t toofs = new_bytes_per_line * y;
-			size_t len_to_copy = d->bytes_per_line <
-			    new_bytes_per_line? d->bytes_per_line	
-			    : new_bytes_per_line;
-			memset(new_framebuffer + toofs, 0, new_bytes_per_line);
-			if (y < d->x11_ysize)
-				memmove(new_framebuffer + toofs,
-				    d->framebuffer + fromofs, len_to_copy);
-		}
-
-		free(d->framebuffer);
-	}
-
-	d->framebuffer = new_framebuffer;
-	d->framebuffer_size = size;
-
-	if (new_xsize > d->xsize || new_ysize > d->ysize) {
-		d->update_x1 = d->update_y1 = 0;
-		d->update_x2 = new_xsize - 1;
-		d->update_y2 = new_ysize - 1;
-	}
-
-	d->bytes_per_line = new_bytes_per_line;
-	d->xsize = d->visible_xsize = new_xsize;
-	d->ysize = d->visible_ysize = new_ysize;
-
-	d->x11_xsize = d->xsize / d->vfb_scaledown;
-	d->x11_ysize = d->ysize / d->vfb_scaledown;
-
-	memory_device_update_data(d->memory, d, d->framebuffer);
-
-	set_title(d);
-
-#ifdef WITH_X11
-	if (d->fb_window != NULL) {
-		x11_fb_resize(d->fb_window, d->x11_xsize, d->x11_ysize);
-		x11_set_standard_properties(d->fb_window, d->title);
-	}
-#endif
-}
-
-
-/*
- *  dev_fb_setcursor():
- */
-void dev_fb_setcursor(struct vfb_data *d, int cursor_x, int cursor_y, int on,
-	int cursor_xsize, int cursor_ysize)
-{
-	if (cursor_x < 0)
-		cursor_x = 0;
-	if (cursor_y < 0)
-		cursor_y = 0;
-	if (cursor_x + cursor_xsize >= d->xsize)
-		cursor_x = d->xsize - cursor_xsize;
-	if (cursor_y + cursor_ysize >= d->ysize)
-		cursor_y = d->ysize - cursor_ysize;
-
-#ifdef WITH_X11
-	if (d->fb_window != NULL) {
-		d->fb_window->cursor_x      = cursor_x;
-		d->fb_window->cursor_y      = cursor_y;
-		d->fb_window->cursor_on     = on;
-		d->fb_window->cursor_xsize  = cursor_xsize;
-		d->fb_window->cursor_ysize  = cursor_ysize;
-	}
-#endif
-
-	/*  debug("dev_fb_setcursor(%i,%i, size %i,%i, on=%i)\n",
-	    cursor_x, cursor_y, cursor_xsize, cursor_ysize, on);  */
-}
-
-
-/*
- *  framebuffer_blockcopyfill():
- *
- *  This function should be used by devices that are capable of doing
- *  block copy/fill.
- *
- *  If fillflag is non-zero, then fill_[rgb] should contain the color
- *  with which to fill. (In 8-bit mode, only fill_r is used.)
- *
- *  If fillflag is zero, copy mode is used, and from_[xy] should contain
- *  the offset on the framebuffer where we should copy from.
- *
- *  NOTE:  Overlapping copies are undefined!
- */
-void framebuffer_blockcopyfill(struct vfb_data *d, int fillflag, int fill_r,
-	int fill_g, int fill_b, int x1, int y1, int x2, int y2,
-	int from_x, int from_y)
-{
-	int x, y;
-	size_t from_ofs, dest_ofs, linelen;
-
-	if (fillflag)
-		debug("framebuffer_blockcopyfill(FILL, %i,%i, %i,%i, "
-		    "color %i,%i,%i)\n", x1,y1, x2,y2, fill_r, fill_g, fill_b);
-	else
-		debug("framebuffer_blockcopyfill(COPY, %i,%i, %i,%i, from "
-		    "%i,%i)\n", x1,y1, x2,y2, from_x,from_y);
-
-	/*  Clip x:  */
-	if (x1 < 0)		x1 = 0;
-	if (x1 >= d->xsize)	x1 = d->xsize-1;
-	if (x2 < 0)		x2 = 0;
-	if (x2 >= d->xsize)	x2 = d->xsize-1;
-
-	dest_ofs = d->bytes_per_line * y1 + (d->bit_depth/8) * x1;
-	linelen = (x2-x1 + 1) * (d->bit_depth/8);
-	/*  NOTE: linelen is nr of bytes, not pixels  */
-
-	if (fillflag) {
-		for (y=y1; y<=y2; y++) {
-			if (y>=0 && y<d->ysize) {
-				unsigned char *buf =
-				    d->framebuffer + dest_ofs;
-
-				if (d->bit_depth == 24) {
-					for (x=0; x<(ssize_t)linelen && x <
-					    (int) sizeof(buf); x += 3) {
-						buf[x] = fill_r;
-						buf[x+1] = fill_g;
-						buf[x+2] = fill_b;
-					}
-				} else if (d->bit_depth == 8) {
-					memset(buf, fill_r, linelen);
-				} else {
-					fatal("Unimplemented bit-depth (%i)"
-					    " for fb fill\n", d->bit_depth);
-					exit(1);
-				}
-			}
-
-			dest_ofs += d->bytes_per_line;
-		}
-	} else {
-		from_ofs = d->bytes_per_line * from_y +
-		    (d->bit_depth/8) * from_x;
-		for (y=y1; y<=y2; y++) {
-			if (y >= 0 && y < d->ysize) {
-				if (from_y >= 0 && from_y < d->ysize)
-					memmove(d->framebuffer + dest_ofs,
-					    d->framebuffer + from_ofs, linelen);
-				else
-					memset(d->framebuffer + dest_ofs,
-					    0, linelen);
-			}
-			from_y ++;
-			from_ofs += d->bytes_per_line;
-			dest_ofs += d->bytes_per_line;
-		}
-	}
-
-	if (x1 < d->update_x1 || d->update_x1 == -1)	d->update_x1 = x1;
-	if (x1 > d->update_x2 || d->update_x2 == -1)	d->update_x2 = x1;
-	if (x2 < d->update_x1 || d->update_x1 == -1)	d->update_x1 = x2;
-	if (x2 > d->update_x2 || d->update_x2 == -1)	d->update_x2 = x2;
-
-	if (y1 < d->update_y1 || d->update_y1 == -1)	d->update_y1 = y1;
-	if (y1 > d->update_y2 || d->update_y2 == -1)	d->update_y2 = y1;
-	if (y2 < d->update_y1 || d->update_y1 == -1)	d->update_y1 = y2;
-	if (y2 > d->update_y2 || d->update_y2 == -1)	d->update_y2 = y2;
-}
-
-
-#ifdef WITH_X11
-
-#define	REDRAW	redraw_fallback
-#include "fb_include.cc"
-#undef REDRAW
-
-#define FB_24
-#define REDRAW	redraw_24
-#include "fb_include.cc"
-#undef REDRAW
-#undef FB_24
-#define FB_16
-#define REDRAW	redraw_16
-#include "fb_include.cc"
-#undef FB_16
-#undef REDRAW
-#define FB_15
-#define REDRAW	redraw_15
-#include "fb_include.cc"
-#undef REDRAW
-#undef FB_15
-
-#define FB_BO
-#define FB_24
-#define REDRAW	redraw_24_bo
-#include "fb_include.cc"
-#undef REDRAW
-#undef FB_24
-#define FB_16
-#define REDRAW	redraw_16_bo
-#include "fb_include.cc"
-#undef FB_16
-#undef REDRAW
-#define FB_15
-#define REDRAW	redraw_15_bo
-#include "fb_include.cc"
-#undef REDRAW
-#undef FB_15
-#undef FB_BO
-
-#define FB_SCALEDOWN
-
-#define	REDRAW	redraw_fallback_sd
-#include "fb_include.cc"
-#undef REDRAW
-
-#define FB_24
-#define REDRAW	redraw_24_sd
-#include "fb_include.cc"
-#undef REDRAW
-#undef FB_24
-#define FB_16
-#define REDRAW	redraw_16_sd
-#include "fb_include.cc"
-#undef FB_16
-#undef REDRAW
-#define FB_15
-#define REDRAW	redraw_15_sd
-#include "fb_include.cc"
-#undef REDRAW
-#undef FB_15
-
-#define FB_BO
-#define FB_24
-#define REDRAW	redraw_24_bo_sd
-#include "fb_include.cc"
-#undef REDRAW
-#undef FB_24
-#define FB_16
-#define REDRAW	redraw_16_bo_sd
-#include "fb_include.cc"
-#undef FB_16
-#undef REDRAW
-#define FB_15
-#define REDRAW	redraw_15_bo_sd
-#include "fb_include.cc"
-#undef REDRAW
-#undef FB_15
-#undef FB_BO
-
-void (*redraw[2 * 4 * 2])(struct vfb_data *, int, int) = {
-	redraw_fallback, redraw_fallback,
-	redraw_15, redraw_15_bo,
-	redraw_16, redraw_16_bo,
-	redraw_24, redraw_24_bo,
-	redraw_fallback_sd, redraw_fallback_sd,
-	redraw_15_sd, redraw_15_bo_sd,
-	redraw_16_sd, redraw_16_bo_sd,
-	redraw_24_sd, redraw_24_bo_sd  };
-
-#endif	/*  WITH_X11  */
-
-
-DEVICE_TICK(fb)
-{
-	struct vfb_data *d = (struct vfb_data *) extra;
-#ifdef WITH_X11
-	int need_to_flush_x11 = 0;
-	int need_to_redraw_cursor = 0;
-#endif
-
-	if (!cpu->machine->x11_md.in_use)
-		return;
-
-	do {
-		uint64_t high, low = (uint64_t)(int64_t) -1;
-		int x, y;
-
-		memory_device_dyntrans_access(cpu, cpu->mem,
-		    extra, &low, &high);
-		if ((int64_t)low == -1)
-			break;
-
-		/*  printf("low=%016llx high=%016llx\n",
-		    (long long)low, (long long)high);  */
-
-		x = (low % d->bytes_per_line) * 8 / d->bit_depth;
-		y = low / d->bytes_per_line;
-		if (x < d->update_x1 || d->update_x1 == -1)
-			d->update_x1 = x;
-		if (x > d->update_x2 || d->update_x2 == -1)
-			d->update_x2 = x;
-		if (y < d->update_y1 || d->update_y1 == -1)
-			d->update_y1 = y;
-		if (y > d->update_y2 || d->update_y2 == -1)
-			d->update_y2 = y;
-
-		x = ((low+7) % d->bytes_per_line) * 8 / d->bit_depth;
-		y = (low+7) / d->bytes_per_line;
-		if (x < d->update_x1 || d->update_x1 == -1)
-			d->update_x1 = x;
-		if (x > d->update_x2 || d->update_x2 == -1)
-			d->update_x2 = x;
-		if (y < d->update_y1 || d->update_y1 == -1)
-			d->update_y1 = y;
-		if (y > d->update_y2 || d->update_y2 == -1)
-			d->update_y2 = y;
-
-		x = (high % d->bytes_per_line) * 8 / d->bit_depth;
-		y = high / d->bytes_per_line;
-		if (x < d->update_x1 || d->update_x1 == -1)
-			d->update_x1 = x;
-		if (x > d->update_x2 || d->update_x2 == -1)
-			d->update_x2 = x;
-		if (y < d->update_y1 || d->update_y1 == -1)
-			d->update_y1 = y;
-		if (y > d->update_y2 || d->update_y2 == -1)
-			d->update_y2 = y;
-
-		x = ((high+7) % d->bytes_per_line) * 8 / d->bit_depth;
-		y = (high+7) / d->bytes_per_line;
-		if (x < d->update_x1 || d->update_x1 == -1)
-			d->update_x1 = x;
-		if (x > d->update_x2 || d->update_x2 == -1)
-			d->update_x2 = x;
-		if (y < d->update_y1 || d->update_y1 == -1)
-			d->update_y1 = y;
-		if (y > d->update_y2 || d->update_y2 == -1)
-			d->update_y2 = y;
-
-		/*
-		 *  An update covering more than one line will automatically
-		 *  force an update of all the affected lines:
-		 */
-		if (d->update_y1 != d->update_y2) {
-			d->update_x1 = 0;
-			d->update_x2 = d->xsize-1;
-		}
-	} while (0);
-
-#ifdef WITH_X11
-	/*  Do we need to redraw the cursor?  */
-	if (d->fb_window->cursor_on != d->fb_window->OLD_cursor_on ||
-	    d->fb_window->cursor_x != d->fb_window->OLD_cursor_x ||
-	    d->fb_window->cursor_y != d->fb_window->OLD_cursor_y ||
-	    d->fb_window->cursor_xsize != d->fb_window->OLD_cursor_xsize ||
-	    d->fb_window->cursor_ysize != d->fb_window->OLD_cursor_ysize)
-		need_to_redraw_cursor = 1;
-
-	if (d->update_x2 != -1) {
-		if (((d->update_x1 >= d->fb_window->OLD_cursor_x &&
-		      d->update_x1 < (d->fb_window->OLD_cursor_x +
-		      d->fb_window->OLD_cursor_xsize)) ||
-		     (d->update_x2 >= d->fb_window->OLD_cursor_x &&
-		      d->update_x2 < (d->fb_window->OLD_cursor_x +
-		      d->fb_window->OLD_cursor_xsize)) ||
-		     (d->update_x1 <  d->fb_window->OLD_cursor_x &&
-		      d->update_x2 >= (d->fb_window->OLD_cursor_x +
-		      d->fb_window->OLD_cursor_xsize)) ) &&
-		   ( (d->update_y1 >= d->fb_window->OLD_cursor_y &&
-		      d->update_y1 < (d->fb_window->OLD_cursor_y +
-		      d->fb_window->OLD_cursor_ysize)) ||
-		     (d->update_y2 >= d->fb_window->OLD_cursor_y &&
-		      d->update_y2 < (d->fb_window->OLD_cursor_y +
-		      d->fb_window->OLD_cursor_ysize)) ||
-		     (d->update_y1 <  d->fb_window->OLD_cursor_y &&
-		      d->update_y2 >= (d->fb_window->OLD_cursor_y +
-		     d->fb_window->OLD_cursor_ysize)) ) )
-			need_to_redraw_cursor = 1;
-	}
-
-	if (need_to_redraw_cursor) {
-		/*  Remove old cursor, if any:  */
-		if (d->fb_window->OLD_cursor_on) {
-			XPutImage(d->fb_window->x11_display,
-			    d->fb_window->x11_fb_window,
-			    d->fb_window->x11_fb_gc, d->fb_window->fb_ximage,
-			    d->fb_window->OLD_cursor_x/d->vfb_scaledown,
-			    d->fb_window->OLD_cursor_y/d->vfb_scaledown,
-			    d->fb_window->OLD_cursor_x/d->vfb_scaledown,
-			    d->fb_window->OLD_cursor_y/d->vfb_scaledown,
-			    d->fb_window->OLD_cursor_xsize/d->vfb_scaledown + 1,
-			    d->fb_window->OLD_cursor_ysize/d->vfb_scaledown +1);
-		}
-	}
-#endif
-
-	if (d->update_x2 != -1) {
-#ifdef WITH_X11
-		int y;
-#endif
-		int addr, addr2, q = d->vfb_scaledown;
-
-		if (d->update_x1 >= d->visible_xsize)
-			d->update_x1 = d->visible_xsize - 1;
-		if (d->update_x2 >= d->visible_xsize)
-			d->update_x2 = d->visible_xsize - 1;
-		if (d->update_y1 >= d->visible_ysize)
-			d->update_y1 = d->visible_ysize - 1;
-		if (d->update_y2 >= d->visible_ysize)
-			d->update_y2 = d->visible_ysize - 1;
-
-		/*  Without these, we might miss the rightmost/bottom pixel:  */
-		d->update_x2 += (q - 1);
-		d->update_y2 += (q - 1);
-
-		d->update_x1 = d->update_x1 / q * q;
-		d->update_x2 = d->update_x2 / q * q;
-		d->update_y1 = d->update_y1 / q * q;
-		d->update_y2 = d->update_y2 / q * q;
-
-		addr  = d->update_y1 * d->bytes_per_line +
-		    d->update_x1 * d->bit_depth / 8;
-		addr2 = d->update_y1 * d->bytes_per_line +
-		    d->update_x2 * d->bit_depth / 8;
-
-#ifdef WITH_X11
-		for (y=d->update_y1; y<=d->update_y2; y+=q) {
-			d->redraw_func(d, addr, addr2 - addr);
-			addr  += d->bytes_per_line * q;
-			addr2 += d->bytes_per_line * q;
-		}
-
-		XPutImage(d->fb_window->x11_display, d->fb_window->
-		    x11_fb_window, d->fb_window->x11_fb_gc, d->fb_window->
-		    fb_ximage, d->update_x1/d->vfb_scaledown, d->update_y1/
-		    d->vfb_scaledown, d->update_x1/d->vfb_scaledown,
-		    d->update_y1/d->vfb_scaledown,
-		    (d->update_x2 - d->update_x1)/d->vfb_scaledown + 1,
-		    (d->update_y2 - d->update_y1)/d->vfb_scaledown + 1);
-
-		need_to_flush_x11 = 1;
-#endif
-
-		d->update_x1 = d->update_y1 = 99999;
-		d->update_x2 = d->update_y2 = -1;
-	}
-
-#ifdef WITH_X11
-	if (need_to_redraw_cursor) {
-		/*  Paint new cursor:  */
-		if (d->fb_window->cursor_on) {
-			x11_redraw_cursor(cpu->machine,
-			    d->fb_window->fb_number);
-			d->fb_window->OLD_cursor_on = d->fb_window->cursor_on;
-			d->fb_window->OLD_cursor_x = d->fb_window->cursor_x;
-			d->fb_window->OLD_cursor_y = d->fb_window->cursor_y;
-			d->fb_window->OLD_cursor_xsize = d->fb_window->
-			    cursor_xsize;
-			d->fb_window->OLD_cursor_ysize = d->fb_window->
-			    cursor_ysize;
-			need_to_flush_x11 = 1;
-		}
-	}
-#endif
-
-#ifdef WITH_X11
-	if (need_to_flush_x11)
-		XFlush(d->fb_window->x11_display);
-#endif
-
-#if 0
-
-This is a hack used to produce raw ppm image dumps, which can then be
-used to make movies, e.g. http://www.youtube.com/watch?v=Afh1ECLWac8
-
-{
-	static struct timeval tv_last;
-	static bool first = true;
-
-	struct timeval tv;
-	gettimeofday(&tv, NULL);
-
-	if (first)
-	{
-		tv_last = tv;
-		first = false;
-	}
-	else
-	{
-		double diff = (tv.tv_sec - tv_last.tv_sec) + (tv.tv_usec - tv_last.tv_usec) / 1000000.0;
-		if (diff > 0.2)
-		{
-			static int outputNr = 0;
-			outputNr ++;
-			tv_last = tv;
-
-			char name[50];
-			snprintf(name, sizeof(name), "gxemul-%06i.ppm", outputNr);
-			
-			FILE *f = fopen(name, "w");
-			if (f == NULL)
-			{
-				perror(name);
-			}
-			else
-			{
-				const int xsize = 640;
-				const int ysize = 480;
-				fprintf(f, "P6\n%i %i\n255\n", xsize, ysize);
-				unsigned char buf[xsize*ysize*3];
-				memset(buf, 0, xsize*ysize*3);
-
-				// Calculate scaledown:
-				int scaledown = 1;
-				
-				while (d->visible_xsize / scaledown > xsize ||
-					d->visible_ysize / scaledown > ysize)
-				{
-					scaledown ++;
-				}
-
-				// printf("scaledown = %i\n", scaledown);
-
-				int xofs = (xsize - d->visible_xsize / scaledown) / 2;
-				int yofs = (ysize - d->visible_ysize / scaledown) / 2;
-
-				for (int y = 0; y < d->visible_ysize / scaledown; ++y)
-				    for (int x = 0; x < d->visible_xsize / scaledown; ++x)
-				    {
-				    	int r = 0, g = 0, b = 0, n = 0;
-				    	for (int suby = 0; suby < scaledown; ++suby)
-				    	    for (int subx = 0; subx < scaledown; ++subx)
-				    	    {
-				    	    	++n;
-				    	    	int rx = x * scaledown + subx;
-				    	    	int ry = y * scaledown + suby;
-				    	    	int i = (d->xsize * ry + rx) * d->bit_depth / 8;
-
-#if 0
-						r += d->framebuffer[i+0];
-						g += d->framebuffer[i+1];
-						b += d->framebuffer[i+2];
-#else
-						int col = d->framebuffer[i];
-						r += d->rgb_palette[col*3 + 0];
-						g += d->rgb_palette[col*3 + 1];
-						b += d->rgb_palette[col*3 + 2];
-#endif
-				    	    }
-
-					r /= n; g /= n; b /= n;
-					int j = (y + yofs) * xsize + x + xofs;
-					buf[j*3+0] = r;
-					buf[j*3+1] = g;
-					buf[j*3+2] = b;
-				    }
-
-				fwrite(buf, 1, xsize*ysize*3, f);
-				fclose(f);
-			}
-		}
-	}
-
-}
-
-#endif
-
-
-}
-
-
-DEVICE_ACCESS(fb)
-{
-	struct vfb_data *d = (struct vfb_data *) extra;
-	size_t i;
-
-#ifdef FB_DEBUG
-	if (writeflag == MEM_WRITE) { if (data[0]) {
-		fatal("[ dev_fb: write  to addr=%08lx, data = ",
-		    (long)relative_addr);
-		for (i=0; i<len; i++)
-			fatal("%02x ", data[i]);
-		fatal("]\n");
-	} else {
-		fatal("[ dev_fb: read from addr=%08lx, data = ",
-		    (long)relative_addr);
-		for (i=0; i<len; i++)
-			fatal("%02x ", d->framebuffer[relative_addr + i]);
-		fatal("]\n");
-	}
-#endif
-
-	if (relative_addr >= d->framebuffer_size)
-		return 0;
-
-	/*  See if a write actually modifies the framebuffer contents:  */
-	if (writeflag == MEM_WRITE) {
-		for (i=0; i<len; i++) {
-			if (data[i] != d->framebuffer[relative_addr + i])
-				break;
-
-			/*  If all bytes are equal to what is already stored
-			    in the framebuffer, then simply return:  */
-			if (i == len-1)
-				return 1;
-		}
-	}
-
-	/*
-	 *  If the framebuffer is modified, then we should keep a track
-	 *  of which area(s) we modify, so that the display isn't updated
-	 *  unnecessarily.
-	 */
-	if (writeflag == MEM_WRITE && cpu->machine->x11_md.in_use) {
-		int x, y, x2,y2;
-
-		x = (relative_addr % d->bytes_per_line) * 8 / d->bit_depth;
-		y = relative_addr / d->bytes_per_line;
-		x2 = ((relative_addr + len) % d->bytes_per_line)
-		    * 8 / d->bit_depth;
-		y2 = (relative_addr + len) / d->bytes_per_line;
-
-		if (x < d->update_x1 || d->update_x1 == -1)
-			d->update_x1 = x;
-		if (x > d->update_x2 || d->update_x2 == -1)
-			d->update_x2 = x;
-
-		if (y < d->update_y1 || d->update_y1 == -1)
-			d->update_y1 = y;
-		if (y > d->update_y2 || d->update_y2 == -1)
-			d->update_y2 = y;
-
-		if (x2 < d->update_x1 || d->update_x1 == -1)
-			d->update_x1 = x2;
-		if (x2 > d->update_x2 || d->update_x2 == -1)
-			d->update_x2 = x2;
-
-		if (y2 < d->update_y1 || d->update_y1 == -1)
-			d->update_y1 = y2;
-		if (y2 > d->update_y2 || d->update_y2 == -1)
-			d->update_y2 = y2;
-
-		/*
-		 *  An update covering more than one line will automatically
-		 *  force an update of all the affected lines:
-		 */
-		if (y != y2) {
-			d->update_x1 = 0;
-			d->update_x2 = d->xsize-1;
-		}
-	}
-
-	/*
-	 *  Read from/write to the framebuffer:
-	 *  (TODO: take the color_plane_mask into account)
-	 *
-	 *  Calling memcpy() is probably overkill, as it usually is just one
-	 *  or a few bytes that are read/written at a time.
-	 */
-	if (writeflag == MEM_WRITE) {
-		if (len > 8)
-			memcpy(d->framebuffer + relative_addr, data, len);
-		else {
-			for (i=0; i<len; i++)
-				d->framebuffer[relative_addr + i] = data[i];
-		}
-	} else {
-		if (len > 8)
-			memcpy(data, d->framebuffer + relative_addr, len);
-		else {
-			for (i=0; i<len; i++)
-				data[i] = d->framebuffer[relative_addr + i];
-		}
-	}
-
-	return 1;
-}
-
-
-/*
- *  dev_fb_init():
- *
- *  This function is big and ugly, but the point is to initialize a framebuffer
- *  device. :-)
- *
- *  visible_xsize and visible_ysize are the sizes of the visible display area.
- *  xsize and ysize tell how much memory is actually allocated (for example
- *  visible_xsize could be 640, but xsize could be 1024, for better alignment).
- *
- *  vfb_type is useful for selecting special features.
- *
- *  type = VFB_GENERIC is the most useful type, especially when bit_depth = 24.
- *
- *  VFB_DEC_VFB01, _VFB02, and VFB_DEC_MAXINE are DECstation specific.
- *
- *  VFB_HPC is like generic, but the color encoding is done as on HPCmips
- *  and Dreamcast.
- *
- *  If bit_depth = -15 (note the minus sign), then a special hack is used for
- *  the Playstation Portable's 5-bit R, 5-bit G, 5-bit B.
- */
-struct vfb_data *dev_fb_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, int vfb_type, int visible_xsize, int visible_ysize,
-	int xsize, int ysize, int bit_depth, const char *name)
-{
-	struct vfb_data *d;
-	size_t size, nlen;
-	int flags;
-	int reverse_start = 0;
-	char *name2;
-
-	CHECK_ALLOCATION(d = (struct vfb_data *) malloc(sizeof(struct vfb_data)));
-	memset(d, 0, sizeof(struct vfb_data));
-
-	if (vfb_type & VFB_REVERSE_START) {
-		vfb_type &= ~VFB_REVERSE_START;
-		reverse_start = 1;
-	}
-
-	d->memory = mem;
-	d->vfb_type = vfb_type;
-
-	/*  Defaults:  */
-	d->xsize = xsize;  d->visible_xsize = visible_xsize;
-	d->ysize = ysize;  d->visible_ysize = visible_ysize;
-
-	d->bit_depth = bit_depth;
-
-	if (bit_depth == 15) {
-		d->color32k = 1;
-		bit_depth = d->bit_depth = 16;
-	} else if (bit_depth == -15) {
-		d->psp_15bit = 1;
-		bit_depth = d->bit_depth = 16;
-	}
-
-	/*  Specific types:  */
-	switch (vfb_type) {
-	case VFB_DEC_VFB01:
-		/*  DECstation VFB01 (monochrome)  */
-		d->xsize = 2048;  d->visible_xsize = 1024;
-		d->ysize = 1024;  d->visible_ysize = 864;
-		d->bit_depth = 1;
-		break;
-	case VFB_DEC_VFB02:
-		/*  DECstation VFB02 (color)  */
-		d->xsize = 1024;  d->visible_xsize = 1024;
-		d->ysize = 1024;  d->visible_ysize = 864;
-		d->bit_depth = 8;
-		break;
-	case VFB_DEC_MAXINE:
-		/*  DECstation Maxine (1024x768x8)  */
-		d->xsize = 1024; d->visible_xsize = d->xsize;
-		d->ysize = 768;  d->visible_ysize = d->ysize;
-		d->bit_depth = 8;
-		break;
-	case VFB_PLAYSTATION2:
-		/*  Playstation 2  */
-		d->xsize = xsize;  d->visible_xsize = d->xsize;
-		d->ysize = ysize;  d->visible_ysize = d->ysize;
-		d->bit_depth = 24;
-		break;
-	}
-
-	if (d->bit_depth == 2 || d->bit_depth == 4)
-		set_grayscale_palette(d, 1 << d->bit_depth);
-	else if (d->bit_depth == 8 || d->bit_depth == 1)
-		set_blackwhite_palette(d, 1 << d->bit_depth);
-
-	d->vfb_scaledown = machine->x11_md.scaledown;
-
-	d->bytes_per_line = d->xsize * d->bit_depth / 8;
-	size = d->ysize * d->bytes_per_line;
-
-	CHECK_ALLOCATION(d->framebuffer = (unsigned char *) malloc(size));
-
-	/*  Clear the framebuffer (all black pixels):  */
-	d->framebuffer_size = size;
-	memset(d->framebuffer, reverse_start? 255 : 0, size);
-
-	d->x11_xsize = d->visible_xsize / d->vfb_scaledown;
-	d->x11_ysize = d->visible_ysize / d->vfb_scaledown;
-
-	/*  Only "update" from the start if we need to fill with white.  */
-	/*  (The Ximage will be black from the start anyway.)  */
-	if (reverse_start) {
-		d->update_x1 = d->update_y1 = 0;
-		d->update_x2 = d->xsize - 1;
-		d->update_y2 = d->ysize - 1;
-	} else {
-		d->update_x1 = d->update_y1 = 99999;
-		d->update_x2 = d->update_y2 = -1;
-	}
-
-	CHECK_ALLOCATION(d->name = strdup(name));
-	set_title(d);
-
-#ifdef WITH_X11
-	if (machine->x11_md.in_use) {
-		int i = 0;
-		d->fb_window = x11_fb_init(d->x11_xsize, d->x11_ysize,
-		    d->title, machine->x11_md.scaledown, machine);
-		switch (d->fb_window->x11_screen_depth) {
-		case 15: i = 2; break;
-		case 16: i = 4; break;
-		case 24: i = 6; break;
-		}
-		if (d->fb_window->fb_ximage->byte_order)
-			i ++;
-		if (d->vfb_scaledown > 1)
-			i += 8;
-		d->redraw_func = redraw[i];
-	} else
-#endif
-		d->fb_window = NULL;
-
-	nlen = strlen(name) + 10;
-	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
-
-	snprintf(name2, nlen, "fb [%s]", name);
-
-	flags = DM_DEFAULT;
-	if ((baseaddr & 0xfff) == 0)
-		flags = DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK;
-
-	flags |= DM_READS_HAVE_NO_SIDE_EFFECTS;
-
-	memory_device_register(mem, name2, baseaddr, size, dev_fb_access,
-	    d, flags, d->framebuffer);
-
-	machine_add_tickfunction(machine, dev_fb_tick, d, FB_TICK_SHIFT);
-
-	return d;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_fbctrl.c gxemul-0.7.0+dfsg/src/devices/dev_fbctrl.c
--- gxemul-0.6.2/src/devices/dev_fbctrl.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_fbctrl.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,174 @@
+/*
+ *  Copyright (C) 2006-2018  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Framebuffer controller device (control's dev_fb in test machines)
+ *
+ *  A "framebuffer control" device. It can be used to manipulate the
+ *  framebuffer device in testmachines.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "testmachine/dev_fb.h"
+
+
+struct fbctrl_data {
+	struct vfb_data *vfb_data;
+	int		current_port;
+	int		port[DEV_FBCTRL_NPORTS];
+};
+
+
+/*
+ *  fbctrl_command():
+ *
+ *  Execute a framebuffer control command.
+ */
+static void fbctrl_command(struct cpu *cpu, struct fbctrl_data *d)
+{
+	int cmd = d->port[DEV_FBCTRL_PORT_COMMAND];
+	int x1, y1, i;
+
+	switch (cmd) {
+
+	case DEV_FBCTRL_COMMAND_NOP:
+		break;
+
+	case DEV_FBCTRL_COMMAND_SET_RESOLUTION:
+		/*
+		 *  Change the framebuffer resolution to X1 x Y1 pixels.
+		 */
+		x1 = d->port[DEV_FBCTRL_PORT_X1];
+		y1 = d->port[DEV_FBCTRL_PORT_Y1];
+		debug("[ dev_fbctrl: changing resolution to %i,%i ]\n", x1, y1);
+
+		dev_fb_resize(d->vfb_data, x1, y1);
+
+		/*  Remember to invalidate all translations for anyone
+		    who might have used the old framebuffer:  */
+		for (i = 0; i < cpu->machine->ncpus; i++)
+			cpu->machine->cpus[i]->invalidate_translation_caches(
+			    cpu->machine->cpus[i], 0, INVALIDATE_ALL);
+		break;
+
+	case DEV_FBCTRL_COMMAND_GET_RESOLUTION:
+		if (cpu->machine->x11_md.in_use) {
+			d->port[DEV_FBCTRL_PORT_X1] = d->vfb_data->xsize;
+			d->port[DEV_FBCTRL_PORT_Y1] = d->vfb_data->ysize;
+		} else {
+			// When not using X11 output, return 0x0 size.
+			d->port[DEV_FBCTRL_PORT_X1] = 0;
+			d->port[DEV_FBCTRL_PORT_Y1] = 0;
+		}
+		break;
+
+	/*  TODO: Block copy and fill.  */
+
+	default:fatal("fbctrl_command: Unimplemented command %i.\n", cmd);
+		exit(1);
+	}
+}
+
+
+DEVICE_ACCESS(fbctrl)
+{
+	struct fbctrl_data *d = (struct fbctrl_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+	        idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case DEV_FBCTRL_PORT:
+		if (writeflag == MEM_READ)
+			odata = d->current_port;
+		else {
+			d->current_port = idata;
+			if (idata >= DEV_FBCTRL_NPORTS)
+				fatal("[ WARNING: fbctrl port number is out"
+				    " of range! ]\n");
+		}
+		break;
+
+	case DEV_FBCTRL_DATA:
+		if (d->current_port < 0 || d->current_port
+		    >= DEV_FBCTRL_NPORTS) {
+			fatal("[ fbctrl port number is out of range! ]\n");
+			exit(1);
+		}
+
+		if (writeflag == MEM_READ)
+			odata = d->port[d->current_port];
+		else {
+			d->port[d->current_port] = idata;
+			if (d->current_port == DEV_FBCTRL_PORT_COMMAND)
+				fbctrl_command(cpu, d);
+		}
+
+		break;
+
+	default:
+		fatal("[ dev_fbctrl: unimplemented relative addr 0x%x ]\n",
+		    (int)relative_addr);
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(fbctrl)
+{
+	struct fbctrl_data *d;
+
+	CHECK_ALLOCATION(d = (struct fbctrl_data *) malloc(sizeof(struct fbctrl_data)));
+	memset(d, 0, sizeof(struct fbctrl_data));
+
+	d->vfb_data = dev_fb_init(devinit->machine, devinit->machine->memory,
+	    DEV_FB_ADDRESS, VFB_GENERIC, 640, 480, 640, DEV_FBCTRL_MAXY(640),
+	    24, "generic");
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_FBCTRL_LENGTH, dev_fbctrl_access, d,
+	    DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_fbctrl.cc gxemul-0.7.0+dfsg/src/devices/dev_fbctrl.cc
--- gxemul-0.6.2/src/devices/dev_fbctrl.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_fbctrl.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,174 +0,0 @@
-/*
- *  Copyright (C) 2006-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Framebuffer controller device (control's dev_fb in test machines)
- *
- *  A "framebuffer control" device. It can be used to manipulate the
- *  framebuffer device in testmachines.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "testmachine/dev_fb.h"
-
-
-struct fbctrl_data {
-	struct vfb_data *vfb_data;
-	int		current_port;
-	int		port[DEV_FBCTRL_NPORTS];
-};
-
-
-/*
- *  fbctrl_command():
- *
- *  Execute a framebuffer control command.
- */
-static void fbctrl_command(struct cpu *cpu, struct fbctrl_data *d)
-{
-	int cmd = d->port[DEV_FBCTRL_PORT_COMMAND];
-	int x1, y1, i;
-
-	switch (cmd) {
-
-	case DEV_FBCTRL_COMMAND_NOP:
-		break;
-
-	case DEV_FBCTRL_COMMAND_SET_RESOLUTION:
-		/*
-		 *  Change the framebuffer resolution to X1 x Y1 pixels.
-		 */
-		x1 = d->port[DEV_FBCTRL_PORT_X1];
-		y1 = d->port[DEV_FBCTRL_PORT_Y1];
-		debug("[ dev_fbctrl: changing resolution to %i,%i ]\n", x1, y1);
-
-		dev_fb_resize(d->vfb_data, x1, y1);
-
-		/*  Remember to invalidate all translations for anyone
-		    who might have used the old framebuffer:  */
-		for (i = 0; i < cpu->machine->ncpus; i++)
-			cpu->machine->cpus[i]->invalidate_translation_caches(
-			    cpu->machine->cpus[i], 0, INVALIDATE_ALL);
-		break;
-
-	case DEV_FBCTRL_COMMAND_GET_RESOLUTION:
-		if (cpu->machine->x11_md.in_use) {
-			d->port[DEV_FBCTRL_PORT_X1] = d->vfb_data->xsize;
-			d->port[DEV_FBCTRL_PORT_Y1] = d->vfb_data->ysize;
-		} else {
-			// When not using X11 output, return 0x0 size.
-			d->port[DEV_FBCTRL_PORT_X1] = 0;
-			d->port[DEV_FBCTRL_PORT_Y1] = 0;
-		}
-		break;
-
-	/*  TODO: Block copy and fill.  */
-
-	default:fatal("fbctrl_command: Unimplemented command %i.\n", cmd);
-		exit(1);
-	}
-}
-
-
-DEVICE_ACCESS(fbctrl)
-{
-	struct fbctrl_data *d = (struct fbctrl_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-	        idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case DEV_FBCTRL_PORT:
-		if (writeflag == MEM_READ)
-			odata = d->current_port;
-		else {
-			d->current_port = idata;
-			if (idata >= DEV_FBCTRL_NPORTS)
-				fatal("[ WARNING: fbctrl port number is out"
-				    " of range! ]\n");
-		}
-		break;
-
-	case DEV_FBCTRL_DATA:
-		if (d->current_port < 0 || d->current_port
-		    >= DEV_FBCTRL_NPORTS) {
-			fatal("[ fbctrl port number is out of range! ]\n");
-			exit(1);
-		}
-
-		if (writeflag == MEM_READ)
-			odata = d->port[d->current_port];
-		else {
-			d->port[d->current_port] = idata;
-			if (d->current_port == DEV_FBCTRL_PORT_COMMAND)
-				fbctrl_command(cpu, d);
-		}
-
-		break;
-
-	default:
-		fatal("[ dev_fbctrl: unimplemented relative addr 0x%x ]\n",
-		    (int)relative_addr);
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(fbctrl)
-{
-	struct fbctrl_data *d;
-
-	CHECK_ALLOCATION(d = (struct fbctrl_data *) malloc(sizeof(struct fbctrl_data)));
-	memset(d, 0, sizeof(struct fbctrl_data));
-
-	d->vfb_data = dev_fb_init(devinit->machine, devinit->machine->memory,
-	    DEV_FB_ADDRESS, VFB_GENERIC, 640, 480, 640, DEV_FBCTRL_MAXY(640),
-	    24, "generic");
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_FBCTRL_LENGTH, dev_fbctrl_access, d,
-	    DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_fdc.c gxemul-0.7.0+dfsg/src/devices/dev_fdc.c
--- gxemul-0.6.2/src/devices/dev_fdc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_fdc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,105 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: PC-style floppy controller
+ *
+ *  TODO!  (This is just a dummy skeleton right now.)
+ *
+ *  TODO 2: Make it work nicely with both ARC and PC emulation.
+ *
+ *  See http://members.tripod.com/~oldboard/assembly/765.html for a
+ *  quick overview.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "device.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	DEV_FDC_LENGTH		6	/*  TODO 8, but collision with wdc  */
+
+
+struct fdc_data {
+	uint8_t			reg[DEV_FDC_LENGTH];
+	struct interrupt	irq;
+};
+
+
+DEVICE_ACCESS(fdc)
+{
+	struct fdc_data *d = (struct fdc_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	size_t i;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	case 0x04:
+		break;
+	default:if (writeflag==MEM_READ) {
+			fatal("[ fdc: read from reg %i ]\n",
+			    (int)relative_addr);
+			odata = d->reg[relative_addr];
+		} else {
+			fatal("[ fdc: write to reg %i:", (int)relative_addr);
+			for (i=0; i<len; i++)
+				fatal(" %02x", data[i]);
+			fatal(" ]\n");
+			d->reg[relative_addr] = idata;
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(fdc)
+{
+	struct fdc_data *d;
+
+	CHECK_ALLOCATION(d = (struct fdc_data *) malloc(sizeof(struct fdc_data)));
+	memset(d, 0, sizeof(struct fdc_data));
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_FDC_LENGTH, dev_fdc_access, d,
+	    DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_fdc.cc gxemul-0.7.0+dfsg/src/devices/dev_fdc.cc
--- gxemul-0.6.2/src/devices/dev_fdc.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_fdc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,105 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: PC-style floppy controller
- *
- *  TODO!  (This is just a dummy skeleton right now.)
- *
- *  TODO 2: Make it work nicely with both ARC and PC emulation.
- *
- *  See http://members.tripod.com/~oldboard/assembly/765.html for a
- *  quick overview.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "device.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define	DEV_FDC_LENGTH		6	/*  TODO 8, but collision with wdc  */
-
-
-struct fdc_data {
-	uint8_t			reg[DEV_FDC_LENGTH];
-	struct interrupt	irq;
-};
-
-
-DEVICE_ACCESS(fdc)
-{
-	struct fdc_data *d = (struct fdc_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	size_t i;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	case 0x04:
-		break;
-	default:if (writeflag==MEM_READ) {
-			fatal("[ fdc: read from reg %i ]\n",
-			    (int)relative_addr);
-			odata = d->reg[relative_addr];
-		} else {
-			fatal("[ fdc: write to reg %i:", (int)relative_addr);
-			for (i=0; i<len; i++)
-				fatal(" %02x", data[i]);
-			fatal(" ]\n");
-			d->reg[relative_addr] = idata;
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(fdc)
-{
-	struct fdc_data *d;
-
-	CHECK_ALLOCATION(d = (struct fdc_data *) malloc(sizeof(struct fdc_data)));
-	memset(d, 0, sizeof(struct fdc_data));
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_FDC_LENGTH, dev_fdc_access, d,
-	    DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_footbridge.c gxemul-0.7.0+dfsg/src/devices/dev_footbridge.c
--- gxemul-0.6.2/src/devices/dev_footbridge.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_footbridge.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,627 @@
+/*
+ *  Copyright (C) 2005-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: DC21285 "Footbridge" controller; used in Netwinder and Cats
+ *
+ *  TODO:
+ *	o)  Add actual support for the fcom serial port.
+ *	o)  FIQs.
+ *	o)  Pretty much everything else as well :)  (This entire thing
+ *	    is a quick hack to work primarily with NetBSD and OpenBSD
+ *	    as guest OSes.)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_pci.h"
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "timer.h"
+
+#include "thirdparty/dc21285reg.h"
+
+
+#define	DEV_FOOTBRIDGE_TICK_SHIFT	14
+#define	DEV_FOOTBRIDGE_LENGTH		0x400
+
+#define	N_FOOTBRIDGE_TIMERS		4
+
+struct footbridge_data {
+	struct interrupt irq;
+
+	struct pci_data *pcibus;
+
+	int		console_handle;
+
+	uint32_t	timer_load[N_FOOTBRIDGE_TIMERS];
+	uint32_t	timer_value[N_FOOTBRIDGE_TIMERS];
+	uint32_t	timer_control[N_FOOTBRIDGE_TIMERS];
+
+	struct interrupt timer_irq[N_FOOTBRIDGE_TIMERS];
+	struct timer	*timer[N_FOOTBRIDGE_TIMERS];
+	int		pending_timer_interrupts[N_FOOTBRIDGE_TIMERS];
+
+	int		irq_asserted;
+
+	uint32_t	irq_status;
+	uint32_t	irq_enable;
+
+	uint32_t	fiq_status;
+	uint32_t	fiq_enable;
+};
+
+
+static void timer_tick0(struct timer *t, void *extra)
+{ ((struct footbridge_data *)extra)->pending_timer_interrupts[0] ++; }
+static void timer_tick1(struct timer *t, void *extra)
+{ ((struct footbridge_data *)extra)->pending_timer_interrupts[1] ++; }
+static void timer_tick2(struct timer *t, void *extra)
+{ ((struct footbridge_data *)extra)->pending_timer_interrupts[2] ++; }
+static void timer_tick3(struct timer *t, void *extra)
+{ ((struct footbridge_data *)extra)->pending_timer_interrupts[3] ++; }
+
+
+static void reload_timer_value(struct cpu *cpu, struct footbridge_data *d,
+	int timer_nr)
+{
+	double freq = (double)cpu->machine->emulated_hz;
+	int cycles = d->timer_load[timer_nr];
+
+	if (d->timer_control[timer_nr] & TIMER_FCLK_16)
+		cycles <<= 4;
+	else if (d->timer_control[timer_nr] & TIMER_FCLK_256)
+		cycles <<= 8;
+	freq /= (double)cycles;
+
+	d->timer_value[timer_nr] = d->timer_load[timer_nr];
+
+	/*  printf("%i: %i -> %f Hz\n", timer_nr,
+	    d->timer_load[timer_nr], freq);  */
+
+	if (d->timer[timer_nr] == NULL) {
+		switch (timer_nr) {
+		case 0:	d->timer[0] = timer_add(freq, timer_tick0, d); break;
+		case 1:	d->timer[1] = timer_add(freq, timer_tick1, d); break;
+		case 2:	d->timer[2] = timer_add(freq, timer_tick2, d); break;
+		case 3:	d->timer[3] = timer_add(freq, timer_tick3, d); break;
+		}
+	} else {
+		timer_update_frequency(d->timer[timer_nr], freq);
+	}
+}
+
+
+/*
+ *  The 4 footbridge timers should decrease and cause interrupts. Periodic
+ *  interrupts restart as soon as they are acknowledged, non-periodic
+ *  interrupts need to be "reloaded" to restart.
+ *
+ *  TODO: Hm. I thought I had solved this, but it didn't quite work.
+ *        This needs to be re-checked against documentation, sometime.
+ */
+DEVICE_TICK(footbridge)
+{
+	struct footbridge_data *d = (struct footbridge_data *) extra;
+	int i;
+
+	for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
+		if (d->timer_control[i] & TIMER_ENABLE) {
+			if (d->pending_timer_interrupts[i] > 0) {
+				d->timer_value[i] = random() % d->timer_load[i];
+				INTERRUPT_ASSERT(d->timer_irq[i]);
+			}
+		}
+	}
+}
+
+
+/*
+ *  footbridge_interrupt_assert():
+ */
+void footbridge_interrupt_assert(struct interrupt *interrupt)
+{
+	struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
+	d->irq_status |= interrupt->line;
+
+	// Patch from NetBSD:
+	// "fix hang interrupt issue. Always assert the irq's even if we have
+	//  already asserted the global irq for the device. prevents hangs with
+	//  cats."
+	if ((d->irq_status & d->irq_enable) /* && !d->irq_asserted */) {
+		d->irq_asserted = 1;
+		INTERRUPT_ASSERT(d->irq);
+	}
+}
+
+
+/*
+ *  footbridge_interrupt_deassert():
+ */
+void footbridge_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
+	d->irq_status &= ~interrupt->line;
+
+	if (!(d->irq_status & d->irq_enable) && d->irq_asserted) {
+		d->irq_asserted = 0;
+		INTERRUPT_DEASSERT(d->irq);
+	}
+}
+
+
+/*
+ *  Reading the byte at 0x79000000 is a quicker way to figure out which ISA
+ *  interrupt has occurred (and acknowledging it at the same time), than
+ *  dealing with the legacy 0x20/0xa0 ISA ports.
+ */
+DEVICE_ACCESS(footbridge_isa)
+{
+	/*  struct footbridge_data *d = extra;  */
+	uint64_t idata = 0, odata = 0;
+	int x;
+
+	if (writeflag == MEM_WRITE) {
+		idata = memory_readmax64(cpu, data, len);
+		fatal("[ footbridge_isa: WARNING/TODO: write! idata = 0x%016" PRIx64" ]\n", idata);
+	}
+
+	x = cpu->machine->isa_pic_data.last_int;
+	if (x < 8)
+		odata = cpu->machine->isa_pic_data.pic1->irq_base + x;
+	else
+		odata = cpu->machine->isa_pic_data.pic2->irq_base + x - 8;
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  Reset pin at ISA port 0x338, at least in the NetWinder:
+ *
+ *  TODO: NOT WORKING YET!
+ */
+DEVICE_ACCESS(footbridge_reset)
+{
+	uint64_t idata = 0;
+
+	if (writeflag == MEM_WRITE) {
+		idata = memory_readmax64(cpu, data, len);
+		if (idata & 0x40) {
+			debug("[ footbridge_reset: GP16: Halting. ]\n");
+			cpu->running = 0;
+exit(1);
+		}
+	}
+
+	return 1;
+}
+
+
+/*
+ *  The Footbridge PCI configuration space is implemented as a direct memory
+ *  space (i.e. not one port for addr and one port for data). This function
+ *  translates that into bus_pci calls.
+ */
+DEVICE_ACCESS(footbridge_pci)
+{
+	struct footbridge_data *d = (struct footbridge_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int bus, dev, func, reg;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
+
+	/*  Decompose the (direct) address into its components:  */
+	bus_pci_decompose_1(relative_addr, &bus, &dev, &func, &reg);
+	bus_pci_setaddr(cpu, d->pcibus, bus, dev, func, reg);
+
+	if (bus == 255) {
+		fatal("[ footbridge DEBUG ERROR: bus 255 unlikely,"
+		    " pc (might not be updated) = 0x%08x ]\n", (int)cpu->pc);
+		exit(1);
+	}
+
+	debug("[ footbridge pci: %s bus %i, device %i, function %i, register "
+	    "%i ]\n", writeflag == MEM_READ? "read from" : "write to", bus,
+	    dev, func, reg);
+
+	bus_pci_data_access(cpu, d->pcibus, writeflag == MEM_READ?
+	    &odata : &idata, len, writeflag);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(footbridge)
+{
+	struct footbridge_data *d = (struct footbridge_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int timer_nr = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (relative_addr >= TIMER_1_LOAD && relative_addr <= TIMER_4_CLEAR) {
+		timer_nr = (relative_addr >> 5) & (N_FOOTBRIDGE_TIMERS - 1);
+		relative_addr &= ~0x060;
+	}
+
+	switch (relative_addr) {
+
+	case VENDOR_ID:
+		odata = 0x1011;  /*  DC21285_VENDOR_ID  */
+		break;
+
+	case DEVICE_ID:
+		odata = 0x1065;  /*  DC21285_DEVICE_ID  */
+		break;
+
+	case 0x04:
+	case 0x0c:
+	case 0x10:
+	case 0x14:
+	case 0x18:
+		/*  TODO. Written to by Linux.  */
+		break;
+
+	case REVISION:
+		odata = 3;  /*  footbridge revision number  */
+		break;
+
+	case PCI_ADDRESS_EXTENSION:
+		/*  TODO: Written to by Linux.  */
+		if (writeflag == MEM_WRITE && idata != 0)
+			fatal("[ footbridge: TODO: write to PCI_ADDRESS_"
+			    "EXTENSION: 0x%llx ]\n", (long long)idata);
+		break;
+
+	case SA_CONTROL:
+		/*  Read by Linux:  */
+		odata = PCI_CENTRAL_FUNCTION;
+		break;
+
+	case UART_DATA:
+		if (writeflag == MEM_WRITE)
+			console_putchar(d->console_handle, idata);
+		break;
+
+	case UART_RX_STAT:
+		/*  TODO  */
+		odata = 0;
+		break;
+
+	case UART_FLAGS:
+		odata = UART_TX_EMPTY;
+		break;
+
+	case IRQ_STATUS:
+		if (writeflag == MEM_READ)
+			odata = d->irq_status & d->irq_enable;
+		else {
+			fatal("[ WARNING: footbridge write to irq status? ]\n");
+			exit(1);
+		}
+		break;
+
+	case IRQ_RAW_STATUS:
+		if (writeflag == MEM_READ)
+			odata = d->irq_status;
+		else {
+			fatal("[ footbridge write to irq_raw_status ]\n");
+			exit(1);
+		}
+		break;
+
+	case IRQ_ENABLE_SET:
+		if (writeflag == MEM_WRITE) {
+			d->irq_enable |= idata;
+			if (d->irq_status & d->irq_enable)
+				INTERRUPT_ASSERT(d->irq);
+			else
+				INTERRUPT_DEASSERT(d->irq);
+		} else {
+			odata = d->irq_enable;
+			fatal("[ WARNING: footbridge read from "
+			    "ENABLE SET? ]\n");
+			exit(1);
+		}
+		break;
+
+	case IRQ_ENABLE_CLEAR:
+		if (writeflag == MEM_WRITE) {
+			d->irq_enable &= ~idata;
+			if (d->irq_status & d->irq_enable)
+				INTERRUPT_ASSERT(d->irq);
+			else
+				INTERRUPT_DEASSERT(d->irq);
+		} else {
+			odata = d->irq_enable;
+			fatal("[ WARNING: footbridge read from "
+			    "ENABLE CLEAR? ]\n");
+			exit(1);
+		}
+		break;
+
+	case FIQ_STATUS:
+		if (writeflag == MEM_READ)
+			odata = d->fiq_status & d->fiq_enable;
+		else {
+			fatal("[ WARNING: footbridge write to fiq status? ]\n");
+			exit(1);
+		}
+		break;
+
+	case FIQ_RAW_STATUS:
+		if (writeflag == MEM_READ)
+			odata = d->fiq_status;
+		else {
+			fatal("[ footbridge write to fiq_raw_status ]\n");
+			exit(1);
+		}
+		break;
+
+	case FIQ_ENABLE_SET:
+		if (writeflag == MEM_WRITE)
+			d->fiq_enable |= idata;
+		break;
+
+	case FIQ_ENABLE_CLEAR:
+		if (writeflag == MEM_WRITE)
+			d->fiq_enable &= ~idata;
+		break;
+
+	case TIMER_1_LOAD:
+		if (writeflag == MEM_READ)
+			odata = d->timer_load[timer_nr];
+		else {
+			d->timer_load[timer_nr] = idata & TIMER_MAX_VAL;
+			reload_timer_value(cpu, d, timer_nr);
+			/*  debug("[ footbridge: timer %i (1-based), "
+			    "value %i ]\n", timer_nr + 1,
+			    (int)d->timer_value[timer_nr]);  */
+			INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
+		}
+		break;
+
+	case TIMER_1_VALUE:
+		if (writeflag == MEM_READ)
+			odata = d->timer_value[timer_nr];
+		else
+			d->timer_value[timer_nr] = idata & TIMER_MAX_VAL;
+		break;
+
+	case TIMER_1_CONTROL:
+		if (writeflag == MEM_READ)
+			odata = d->timer_control[timer_nr];
+		else {
+			d->timer_control[timer_nr] = idata;
+			if (idata & TIMER_FCLK_16 &&
+			    idata & TIMER_FCLK_256) {
+				fatal("TODO: footbridge timer: "
+				    "both 16 and 256?\n");
+				exit(1);
+			}
+			if (idata & TIMER_ENABLE) {
+				reload_timer_value(cpu, d, timer_nr);
+			} else {
+				d->pending_timer_interrupts[timer_nr] = 0;
+			}
+			INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
+		}
+		break;
+
+	case TIMER_1_CLEAR:
+		if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) {
+			reload_timer_value(cpu, d, timer_nr);
+		}
+
+		if (d->pending_timer_interrupts[timer_nr] > 0) {
+			d->pending_timer_interrupts[timer_nr] --;
+		}
+
+		INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
+		break;
+
+	case SDRAM_BA_MASK:
+		if (writeflag == MEM_READ) {
+			fatal("[ footbridge read from sdram_ba_mask ]\n");
+			exit(1);
+		} else {
+			switch (idata) {
+			case SDRAM_MASK_256KB:
+			case SDRAM_MASK_512KB:
+			case SDRAM_MASK_1MB:
+			case SDRAM_MASK_2MB:
+			case SDRAM_MASK_4MB:
+			case SDRAM_MASK_8MB:
+			case SDRAM_MASK_16MB:
+			case SDRAM_MASK_32MB:
+			case SDRAM_MASK_64MB:
+			case SDRAM_MASK_128MB:
+			case SDRAM_MASK_256MB:
+				break;
+			default:
+				fatal("[ footbridge write to sdram_ba_mask "
+				    "%#llx ]\n", (long long)idata);
+				break;
+			}
+		}
+		break;
+	case SDRAM_BA_OFFSET:
+		if (writeflag == MEM_READ) {
+			fatal("[ footbridge read from sdram_ba_offset ]\n");
+			exit(1);
+		} else {
+			if (idata != 0)
+				fatal("[ footbridge write to sdram_ba_offset "
+				    "%#llx ]\n", (long long)idata);
+		}
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ footbridge: read from 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ footbridge: write to 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(footbridge)
+{
+	struct footbridge_data *d;
+	char irq_path[300], irq_path_isa[400];
+	uint64_t pci_addr = 0x7b000000;
+	int i;
+
+	CHECK_ALLOCATION(d = (struct footbridge_data *) malloc(sizeof(struct footbridge_data)));
+	memset(d, 0, sizeof(struct footbridge_data));
+
+	/*  Connect to the CPU which this footbridge will interrupt:  */
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	/*  DC21285 register access:  */
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_FOOTBRIDGE_LENGTH,
+	    dev_footbridge_access, d, DM_DEFAULT, NULL);
+
+	/*  ISA interrupt status/acknowledgement:  */
+	memory_device_register(devinit->machine->memory, "footbridge_isa",
+	    0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL);
+
+	/*  The "fcom" console:  */
+	d->console_handle = console_start_slave(devinit->machine, "fcom", 0);
+
+	/*  Register 32 footbridge interrupts:  */
+	snprintf(irq_path, sizeof(irq_path), "%s.footbridge",
+	    devinit->interrupt_path);
+	for (i=0; i<32; i++) {
+		struct interrupt interrupt_template;
+		char tmpstr[600];
+
+		memset(&interrupt_template, 0, sizeof(interrupt_template));
+		interrupt_template.line = 1 << i;
+		snprintf(tmpstr, sizeof(tmpstr), "%s.%i", irq_path, i);
+		interrupt_template.name = tmpstr;
+
+		interrupt_template.extra = d;
+		interrupt_template.interrupt_assert =
+		    footbridge_interrupt_assert;
+		interrupt_template.interrupt_deassert =
+		    footbridge_interrupt_deassert;
+		interrupt_handler_register(&interrupt_template);
+
+		/*  Connect locally to some interrupts:  */
+		if (i>=IRQ_TIMER_1 && i<=IRQ_TIMER_4)
+			INTERRUPT_CONNECT(tmpstr, d->timer_irq[i-IRQ_TIMER_1]);
+	}
+
+	switch (devinit->machine->machine_type) {
+	case MACHINE_CATS:
+		snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.10", irq_path);
+		break;
+	case MACHINE_NETWINDER:
+		snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.11", irq_path);
+		break;
+	default:fatal("footbridge unimpl machine type\n");
+		exit(1);
+	}
+
+	/*  A PCI bus:  */
+	d->pcibus = bus_pci_init(
+	    devinit->machine,
+	    irq_path,
+	    0x7c000000,		/*  PCI device io offset  */
+	    0x80000000,		/*  PCI device mem offset  */
+	    0x00000000,		/*  PCI port base  */
+	    0x00000000,		/*  PCI mem base  */
+	    irq_path,		/*  PCI irq base  */
+	    0x7c000000,		/*  ISA port base  */
+	    0x80000000,		/*  ISA mem base  */
+	    irq_path_isa);	/*  ISA port base  */
+
+	/*  ... with some default devices for known machine types:  */
+	switch (devinit->machine->machine_type) {
+	case MACHINE_CATS:
+		bus_pci_add(devinit->machine, d->pcibus,
+		    devinit->machine->memory, 0xc0, 7, 0, "ali_m1543");
+		bus_pci_add(devinit->machine, d->pcibus,
+		    devinit->machine->memory, 0xc0, 10, 0, "dec21143");
+		bus_pci_add(devinit->machine, d->pcibus,
+		    devinit->machine->memory, 0xc0, 16, 0, "ali_m5229");
+		break;
+	case MACHINE_NETWINDER:
+		bus_pci_add(devinit->machine, d->pcibus,
+		    devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553");
+		bus_pci_add(devinit->machine, d->pcibus,
+		    devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105");
+		memory_device_register(devinit->machine->memory,
+		    "footbridge_reset", 0x7c000338, 1,
+		    dev_footbridge_reset_access, d, DM_DEFAULT, NULL);
+		break;
+	default:fatal("footbridge: unimplemented machine type.\n");
+		exit(1);
+	}
+
+	/*  PCI configuration space:  */
+	memory_device_register(devinit->machine->memory,
+	    "footbridge_pci", pci_addr, 0x1000000,
+	    dev_footbridge_pci_access, d, DM_DEFAULT, NULL);
+
+	/*  Timer ticks:  */
+	for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
+		d->timer_control[i] = TIMER_MODE_PERIODIC;
+		d->timer_load[i] = TIMER_MAX_VAL;
+	}
+
+	machine_add_tickfunction(devinit->machine,
+	    dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT);
+
+	devinit->return_ptr = d->pcibus;
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_footbridge.cc gxemul-0.7.0+dfsg/src/devices/dev_footbridge.cc
--- gxemul-0.6.2/src/devices/dev_footbridge.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_footbridge.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,627 +0,0 @@
-/*
- *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: DC21285 "Footbridge" controller; used in Netwinder and Cats
- *
- *  TODO:
- *	o)  Add actual support for the fcom serial port.
- *	o)  FIQs.
- *	o)  Pretty much everything else as well :)  (This entire thing
- *	    is a quick hack to work primarily with NetBSD and OpenBSD
- *	    as guest OSes.)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_pci.h"
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "timer.h"
-
-#include "thirdparty/dc21285reg.h"
-
-
-#define	DEV_FOOTBRIDGE_TICK_SHIFT	14
-#define	DEV_FOOTBRIDGE_LENGTH		0x400
-
-#define	N_FOOTBRIDGE_TIMERS		4
-
-struct footbridge_data {
-	struct interrupt irq;
-
-	struct pci_data *pcibus;
-
-	int		console_handle;
-
-	uint32_t	timer_load[N_FOOTBRIDGE_TIMERS];
-	uint32_t	timer_value[N_FOOTBRIDGE_TIMERS];
-	uint32_t	timer_control[N_FOOTBRIDGE_TIMERS];
-
-	struct interrupt timer_irq[N_FOOTBRIDGE_TIMERS];
-	struct timer	*timer[N_FOOTBRIDGE_TIMERS];
-	int		pending_timer_interrupts[N_FOOTBRIDGE_TIMERS];
-
-	int		irq_asserted;
-
-	uint32_t	irq_status;
-	uint32_t	irq_enable;
-
-	uint32_t	fiq_status;
-	uint32_t	fiq_enable;
-};
-
-
-static void timer_tick0(struct timer *t, void *extra)
-{ ((struct footbridge_data *)extra)->pending_timer_interrupts[0] ++; }
-static void timer_tick1(struct timer *t, void *extra)
-{ ((struct footbridge_data *)extra)->pending_timer_interrupts[1] ++; }
-static void timer_tick2(struct timer *t, void *extra)
-{ ((struct footbridge_data *)extra)->pending_timer_interrupts[2] ++; }
-static void timer_tick3(struct timer *t, void *extra)
-{ ((struct footbridge_data *)extra)->pending_timer_interrupts[3] ++; }
-
-
-static void reload_timer_value(struct cpu *cpu, struct footbridge_data *d,
-	int timer_nr)
-{
-	double freq = (double)cpu->machine->emulated_hz;
-	int cycles = d->timer_load[timer_nr];
-
-	if (d->timer_control[timer_nr] & TIMER_FCLK_16)
-		cycles <<= 4;
-	else if (d->timer_control[timer_nr] & TIMER_FCLK_256)
-		cycles <<= 8;
-	freq /= (double)cycles;
-
-	d->timer_value[timer_nr] = d->timer_load[timer_nr];
-
-	/*  printf("%i: %i -> %f Hz\n", timer_nr,
-	    d->timer_load[timer_nr], freq);  */
-
-	if (d->timer[timer_nr] == NULL) {
-		switch (timer_nr) {
-		case 0:	d->timer[0] = timer_add(freq, timer_tick0, d); break;
-		case 1:	d->timer[1] = timer_add(freq, timer_tick1, d); break;
-		case 2:	d->timer[2] = timer_add(freq, timer_tick2, d); break;
-		case 3:	d->timer[3] = timer_add(freq, timer_tick3, d); break;
-		}
-	} else {
-		timer_update_frequency(d->timer[timer_nr], freq);
-	}
-}
-
-
-/*
- *  The 4 footbridge timers should decrease and cause interrupts. Periodic
- *  interrupts restart as soon as they are acknowledged, non-periodic
- *  interrupts need to be "reloaded" to restart.
- *
- *  TODO: Hm. I thought I had solved this, but it didn't quite work.
- *        This needs to be re-checked against documentation, sometime.
- */
-DEVICE_TICK(footbridge)
-{
-	struct footbridge_data *d = (struct footbridge_data *) extra;
-	int i;
-
-	for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
-		if (d->timer_control[i] & TIMER_ENABLE) {
-			if (d->pending_timer_interrupts[i] > 0) {
-				d->timer_value[i] = random() % d->timer_load[i];
-				INTERRUPT_ASSERT(d->timer_irq[i]);
-			}
-		}
-	}
-}
-
-
-/*
- *  footbridge_interrupt_assert():
- */
-void footbridge_interrupt_assert(struct interrupt *interrupt)
-{
-	struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
-	d->irq_status |= interrupt->line;
-
-	// Patch from NetBSD:
-	// "fix hang interrupt issue. Always assert the irq's even if we have
-	//  already asserted the global irq for the device. prevents hangs with
-	//  cats."
-	if ((d->irq_status & d->irq_enable) /* && !d->irq_asserted */) {
-		d->irq_asserted = 1;
-		INTERRUPT_ASSERT(d->irq);
-	}
-}
-
-
-/*
- *  footbridge_interrupt_deassert():
- */
-void footbridge_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
-	d->irq_status &= ~interrupt->line;
-
-	if (!(d->irq_status & d->irq_enable) && d->irq_asserted) {
-		d->irq_asserted = 0;
-		INTERRUPT_DEASSERT(d->irq);
-	}
-}
-
-
-/*
- *  Reading the byte at 0x79000000 is a quicker way to figure out which ISA
- *  interrupt has occurred (and acknowledging it at the same time), than
- *  dealing with the legacy 0x20/0xa0 ISA ports.
- */
-DEVICE_ACCESS(footbridge_isa)
-{
-	/*  struct footbridge_data *d = extra;  */
-	uint64_t idata = 0, odata = 0;
-	int x;
-
-	if (writeflag == MEM_WRITE) {
-		idata = memory_readmax64(cpu, data, len);
-		fatal("[ footbridge_isa: WARNING/TODO: write! ]\n");
-	}
-
-	x = cpu->machine->isa_pic_data.last_int;
-	if (x < 8)
-		odata = cpu->machine->isa_pic_data.pic1->irq_base + x;
-	else
-		odata = cpu->machine->isa_pic_data.pic2->irq_base + x - 8;
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  Reset pin at ISA port 0x338, at least in the NetWinder:
- *
- *  TODO: NOT WORKING YET!
- */
-DEVICE_ACCESS(footbridge_reset)
-{
-	uint64_t idata = 0;
-
-	if (writeflag == MEM_WRITE) {
-		idata = memory_readmax64(cpu, data, len);
-		if (idata & 0x40) {
-			debug("[ footbridge_reset: GP16: Halting. ]\n");
-			cpu->running = 0;
-exit(1);
-		}
-	}
-
-	return 1;
-}
-
-
-/*
- *  The Footbridge PCI configuration space is implemented as a direct memory
- *  space (i.e. not one port for addr and one port for data). This function
- *  translates that into bus_pci calls.
- */
-DEVICE_ACCESS(footbridge_pci)
-{
-	struct footbridge_data *d = (struct footbridge_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int bus, dev, func, reg;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
-
-	/*  Decompose the (direct) address into its components:  */
-	bus_pci_decompose_1(relative_addr, &bus, &dev, &func, &reg);
-	bus_pci_setaddr(cpu, d->pcibus, bus, dev, func, reg);
-
-	if (bus == 255) {
-		fatal("[ footbridge DEBUG ERROR: bus 255 unlikely,"
-		    " pc (might not be updated) = 0x%08x ]\n", (int)cpu->pc);
-		exit(1);
-	}
-
-	debug("[ footbridge pci: %s bus %i, device %i, function %i, register "
-	    "%i ]\n", writeflag == MEM_READ? "read from" : "write to", bus,
-	    dev, func, reg);
-
-	bus_pci_data_access(cpu, d->pcibus, writeflag == MEM_READ?
-	    &odata : &idata, len, writeflag);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(footbridge)
-{
-	struct footbridge_data *d = (struct footbridge_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int timer_nr = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (relative_addr >= TIMER_1_LOAD && relative_addr <= TIMER_4_CLEAR) {
-		timer_nr = (relative_addr >> 5) & (N_FOOTBRIDGE_TIMERS - 1);
-		relative_addr &= ~0x060;
-	}
-
-	switch (relative_addr) {
-
-	case VENDOR_ID:
-		odata = 0x1011;  /*  DC21285_VENDOR_ID  */
-		break;
-
-	case DEVICE_ID:
-		odata = 0x1065;  /*  DC21285_DEVICE_ID  */
-		break;
-
-	case 0x04:
-	case 0x0c:
-	case 0x10:
-	case 0x14:
-	case 0x18:
-		/*  TODO. Written to by Linux.  */
-		break;
-
-	case REVISION:
-		odata = 3;  /*  footbridge revision number  */
-		break;
-
-	case PCI_ADDRESS_EXTENSION:
-		/*  TODO: Written to by Linux.  */
-		if (writeflag == MEM_WRITE && idata != 0)
-			fatal("[ footbridge: TODO: write to PCI_ADDRESS_"
-			    "EXTENSION: 0x%llx ]\n", (long long)idata);
-		break;
-
-	case SA_CONTROL:
-		/*  Read by Linux:  */
-		odata = PCI_CENTRAL_FUNCTION;
-		break;
-
-	case UART_DATA:
-		if (writeflag == MEM_WRITE)
-			console_putchar(d->console_handle, idata);
-		break;
-
-	case UART_RX_STAT:
-		/*  TODO  */
-		odata = 0;
-		break;
-
-	case UART_FLAGS:
-		odata = UART_TX_EMPTY;
-		break;
-
-	case IRQ_STATUS:
-		if (writeflag == MEM_READ)
-			odata = d->irq_status & d->irq_enable;
-		else {
-			fatal("[ WARNING: footbridge write to irq status? ]\n");
-			exit(1);
-		}
-		break;
-
-	case IRQ_RAW_STATUS:
-		if (writeflag == MEM_READ)
-			odata = d->irq_status;
-		else {
-			fatal("[ footbridge write to irq_raw_status ]\n");
-			exit(1);
-		}
-		break;
-
-	case IRQ_ENABLE_SET:
-		if (writeflag == MEM_WRITE) {
-			d->irq_enable |= idata;
-			if (d->irq_status & d->irq_enable)
-				INTERRUPT_ASSERT(d->irq);
-			else
-				INTERRUPT_DEASSERT(d->irq);
-		} else {
-			odata = d->irq_enable;
-			fatal("[ WARNING: footbridge read from "
-			    "ENABLE SET? ]\n");
-			exit(1);
-		}
-		break;
-
-	case IRQ_ENABLE_CLEAR:
-		if (writeflag == MEM_WRITE) {
-			d->irq_enable &= ~idata;
-			if (d->irq_status & d->irq_enable)
-				INTERRUPT_ASSERT(d->irq);
-			else
-				INTERRUPT_DEASSERT(d->irq);
-		} else {
-			odata = d->irq_enable;
-			fatal("[ WARNING: footbridge read from "
-			    "ENABLE CLEAR? ]\n");
-			exit(1);
-		}
-		break;
-
-	case FIQ_STATUS:
-		if (writeflag == MEM_READ)
-			odata = d->fiq_status & d->fiq_enable;
-		else {
-			fatal("[ WARNING: footbridge write to fiq status? ]\n");
-			exit(1);
-		}
-		break;
-
-	case FIQ_RAW_STATUS:
-		if (writeflag == MEM_READ)
-			odata = d->fiq_status;
-		else {
-			fatal("[ footbridge write to fiq_raw_status ]\n");
-			exit(1);
-		}
-		break;
-
-	case FIQ_ENABLE_SET:
-		if (writeflag == MEM_WRITE)
-			d->fiq_enable |= idata;
-		break;
-
-	case FIQ_ENABLE_CLEAR:
-		if (writeflag == MEM_WRITE)
-			d->fiq_enable &= ~idata;
-		break;
-
-	case TIMER_1_LOAD:
-		if (writeflag == MEM_READ)
-			odata = d->timer_load[timer_nr];
-		else {
-			d->timer_load[timer_nr] = idata & TIMER_MAX_VAL;
-			reload_timer_value(cpu, d, timer_nr);
-			/*  debug("[ footbridge: timer %i (1-based), "
-			    "value %i ]\n", timer_nr + 1,
-			    (int)d->timer_value[timer_nr]);  */
-			INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
-		}
-		break;
-
-	case TIMER_1_VALUE:
-		if (writeflag == MEM_READ)
-			odata = d->timer_value[timer_nr];
-		else
-			d->timer_value[timer_nr] = idata & TIMER_MAX_VAL;
-		break;
-
-	case TIMER_1_CONTROL:
-		if (writeflag == MEM_READ)
-			odata = d->timer_control[timer_nr];
-		else {
-			d->timer_control[timer_nr] = idata;
-			if (idata & TIMER_FCLK_16 &&
-			    idata & TIMER_FCLK_256) {
-				fatal("TODO: footbridge timer: "
-				    "both 16 and 256?\n");
-				exit(1);
-			}
-			if (idata & TIMER_ENABLE) {
-				reload_timer_value(cpu, d, timer_nr);
-			} else {
-				d->pending_timer_interrupts[timer_nr] = 0;
-			}
-			INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
-		}
-		break;
-
-	case TIMER_1_CLEAR:
-		if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) {
-			reload_timer_value(cpu, d, timer_nr);
-		}
-
-		if (d->pending_timer_interrupts[timer_nr] > 0) {
-			d->pending_timer_interrupts[timer_nr] --;
-		}
-
-		INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
-		break;
-
-	case SDRAM_BA_MASK:
-		if (writeflag == MEM_READ) {
-			fatal("[ footbridge read from sdram_ba_mask ]\n");
-			exit(1);
-		} else {
-			switch (idata) {
-			case SDRAM_MASK_256KB:
-			case SDRAM_MASK_512KB:
-			case SDRAM_MASK_1MB:
-			case SDRAM_MASK_2MB:
-			case SDRAM_MASK_4MB:
-			case SDRAM_MASK_8MB:
-			case SDRAM_MASK_16MB:
-			case SDRAM_MASK_32MB:
-			case SDRAM_MASK_64MB:
-			case SDRAM_MASK_128MB:
-			case SDRAM_MASK_256MB:
-				break;
-			default:
-				fatal("[ footbridge write to sdram_ba_mask "
-				    "%#llx ]\n", (long long)idata);
-				break;
-			}
-		}
-		break;
-	case SDRAM_BA_OFFSET:
-		if (writeflag == MEM_READ) {
-			fatal("[ footbridge read from sdram_ba_offset ]\n");
-			exit(1);
-		} else {
-			if (idata != 0)
-				fatal("[ footbridge write to sdram_ba_offset "
-				    "%#llx ]\n", (long long)idata);
-		}
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ footbridge: read from 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ footbridge: write to 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(footbridge)
-{
-	struct footbridge_data *d;
-	char irq_path[300], irq_path_isa[400];
-	uint64_t pci_addr = 0x7b000000;
-	int i;
-
-	CHECK_ALLOCATION(d = (struct footbridge_data *) malloc(sizeof(struct footbridge_data)));
-	memset(d, 0, sizeof(struct footbridge_data));
-
-	/*  Connect to the CPU which this footbridge will interrupt:  */
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	/*  DC21285 register access:  */
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_FOOTBRIDGE_LENGTH,
-	    dev_footbridge_access, d, DM_DEFAULT, NULL);
-
-	/*  ISA interrupt status/acknowledgement:  */
-	memory_device_register(devinit->machine->memory, "footbridge_isa",
-	    0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL);
-
-	/*  The "fcom" console:  */
-	d->console_handle = console_start_slave(devinit->machine, "fcom", 0);
-
-	/*  Register 32 footbridge interrupts:  */
-	snprintf(irq_path, sizeof(irq_path), "%s.footbridge",
-	    devinit->interrupt_path);
-	for (i=0; i<32; i++) {
-		struct interrupt interrupt_template;
-		char tmpstr[600];
-
-		memset(&interrupt_template, 0, sizeof(interrupt_template));
-		interrupt_template.line = 1 << i;
-		snprintf(tmpstr, sizeof(tmpstr), "%s.%i", irq_path, i);
-		interrupt_template.name = tmpstr;
-
-		interrupt_template.extra = d;
-		interrupt_template.interrupt_assert =
-		    footbridge_interrupt_assert;
-		interrupt_template.interrupt_deassert =
-		    footbridge_interrupt_deassert;
-		interrupt_handler_register(&interrupt_template);
-
-		/*  Connect locally to some interrupts:  */
-		if (i>=IRQ_TIMER_1 && i<=IRQ_TIMER_4)
-			INTERRUPT_CONNECT(tmpstr, d->timer_irq[i-IRQ_TIMER_1]);
-	}
-
-	switch (devinit->machine->machine_type) {
-	case MACHINE_CATS:
-		snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.10", irq_path);
-		break;
-	case MACHINE_NETWINDER:
-		snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.11", irq_path);
-		break;
-	default:fatal("footbridge unimpl machine type\n");
-		exit(1);
-	}
-
-	/*  A PCI bus:  */
-	d->pcibus = bus_pci_init(
-	    devinit->machine,
-	    irq_path,
-	    0x7c000000,		/*  PCI device io offset  */
-	    0x80000000,		/*  PCI device mem offset  */
-	    0x00000000,		/*  PCI port base  */
-	    0x00000000,		/*  PCI mem base  */
-	    irq_path,		/*  PCI irq base  */
-	    0x7c000000,		/*  ISA port base  */
-	    0x80000000,		/*  ISA mem base  */
-	    irq_path_isa);	/*  ISA port base  */
-
-	/*  ... with some default devices for known machine types:  */
-	switch (devinit->machine->machine_type) {
-	case MACHINE_CATS:
-		bus_pci_add(devinit->machine, d->pcibus,
-		    devinit->machine->memory, 0xc0, 7, 0, "ali_m1543");
-		bus_pci_add(devinit->machine, d->pcibus,
-		    devinit->machine->memory, 0xc0, 10, 0, "dec21143");
-		bus_pci_add(devinit->machine, d->pcibus,
-		    devinit->machine->memory, 0xc0, 16, 0, "ali_m5229");
-		break;
-	case MACHINE_NETWINDER:
-		bus_pci_add(devinit->machine, d->pcibus,
-		    devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553");
-		bus_pci_add(devinit->machine, d->pcibus,
-		    devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105");
-		memory_device_register(devinit->machine->memory,
-		    "footbridge_reset", 0x7c000338, 1,
-		    dev_footbridge_reset_access, d, DM_DEFAULT, NULL);
-		break;
-	default:fatal("footbridge: unimplemented machine type.\n");
-		exit(1);
-	}
-
-	/*  PCI configuration space:  */
-	memory_device_register(devinit->machine->memory,
-	    "footbridge_pci", pci_addr, 0x1000000,
-	    dev_footbridge_pci_access, d, DM_DEFAULT, NULL);
-
-	/*  Timer ticks:  */
-	for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
-		d->timer_control[i] = TIMER_MODE_PERIODIC;
-		d->timer_load[i] = TIMER_MAX_VAL;
-	}
-
-	machine_add_tickfunction(devinit->machine,
-	    dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT);
-
-	devinit->return_ptr = d->pcibus;
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_gc.c gxemul-0.7.0+dfsg/src/devices/dev_gc.c
--- gxemul-0.6.2/src/devices/dev_gc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_gc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,252 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *  
+ *  COMMENT: Grand Central Interrupt controller (used by MacPPC)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	DEV_GC_LENGTH		0x100
+
+struct gc_data {
+	struct interrupt cpu_irq;
+
+	uint32_t	status_hi;
+	uint32_t	status_lo;
+	uint32_t	enable_hi;
+	uint32_t	enable_lo;
+};
+
+
+void gc_hi_interrupt_assert(struct interrupt *interrupt)
+{
+	struct gc_data *d = (struct gc_data *) interrupt->extra;
+	d->status_hi |= interrupt->line;
+	if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
+		INTERRUPT_ASSERT(d->cpu_irq);
+}
+void gc_hi_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct gc_data *d = (struct gc_data *) interrupt->extra;
+	d->status_hi &= ~interrupt->line;
+	if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
+		INTERRUPT_DEASSERT(d->cpu_irq);
+}
+void gc_lo_interrupt_assert(struct interrupt *interrupt)
+{
+	struct gc_data *d = (struct gc_data *) interrupt->extra;
+	d->status_lo |= interrupt->line;
+	if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
+		INTERRUPT_ASSERT(d->cpu_irq);
+}
+void gc_lo_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct gc_data *d = (struct gc_data *) interrupt->extra;
+	d->status_lo &= ~interrupt->line;
+	if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
+		INTERRUPT_DEASSERT(d->cpu_irq);
+}
+
+
+DEVICE_ACCESS(gc)
+{
+	struct gc_data *d = (struct gc_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+#if 0
+#define INT_STATE_REG_H  (interrupt_reg + 0x00)
+#define INT_ENABLE_REG_H (interrupt_reg + 0x04)
+#define INT_CLEAR_REG_H  (interrupt_reg + 0x08)
+#define INT_LEVEL_REG_H  (interrupt_reg + 0x0c)
+#define INT_STATE_REG_L  (interrupt_reg + 0x10)
+#define INT_ENABLE_REG_L (interrupt_reg + 0x14)
+#define INT_CLEAR_REG_L  (interrupt_reg + 0x18)
+#define INT_LEVEL_REG_L  (interrupt_reg + 0x1c)
+#endif
+
+	case 0x10:
+		if (writeflag == MEM_READ)
+			odata = d->status_hi & d->enable_hi;
+		break;
+
+	case 0x14:
+		if (writeflag == MEM_READ)
+			odata = d->enable_hi;
+		else {
+			int old_assert = (d->status_lo & d->enable_lo
+			    || d->status_hi & d->enable_hi);
+			int new_assert;
+			d->enable_hi = idata;
+
+			new_assert = (d->status_lo & d->enable_lo ||
+			    d->status_hi & d->enable_hi);
+
+			if (old_assert && !new_assert)
+				INTERRUPT_DEASSERT(d->cpu_irq);
+			else if (!old_assert && new_assert)
+				INTERRUPT_ASSERT(d->cpu_irq);
+		}
+		break;
+
+	case 0x18:
+		if (writeflag == MEM_WRITE) {
+			int old_assert = (d->status_lo & d->enable_lo
+			    || d->status_hi & d->enable_hi);
+			int new_assert;
+			d->status_hi &= ~idata;
+
+			new_assert = (d->status_lo & d->enable_lo ||
+			    d->status_hi & d->enable_hi);
+
+			if (old_assert && !new_assert)
+				INTERRUPT_DEASSERT(d->cpu_irq);
+			else if (!old_assert && new_assert)
+				INTERRUPT_ASSERT(d->cpu_irq);
+		}
+		break;
+
+	case 0x20:
+		if (writeflag == MEM_READ)
+			odata = d->status_lo & d->enable_lo;
+		break;
+
+	case 0x24:
+		if (writeflag == MEM_READ)
+			odata = d->enable_lo;
+		else {
+			int old_assert = (d->status_lo & d->enable_lo
+			    || d->status_hi & d->enable_hi);
+			int new_assert;
+			d->enable_lo = idata;
+
+			new_assert = (d->status_lo & d->enable_lo ||
+			    d->status_hi & d->enable_hi);
+
+			if (old_assert && !new_assert)
+				INTERRUPT_DEASSERT(d->cpu_irq);
+			else if (!old_assert && new_assert)
+				INTERRUPT_ASSERT(d->cpu_irq);
+		}
+		break;
+
+	case 0x28:
+		if (writeflag == MEM_WRITE) {
+			int old_assert = (d->status_lo & d->enable_lo
+			    || d->status_hi & d->enable_hi);
+			int new_assert;
+			d->status_lo &= ~idata;
+
+			new_assert = (d->status_lo & d->enable_lo ||
+			    d->status_hi & d->enable_hi);
+
+			if (old_assert && !new_assert)
+				INTERRUPT_DEASSERT(d->cpu_irq);
+			else if (!old_assert && new_assert)
+				INTERRUPT_ASSERT(d->cpu_irq);
+		}
+		break;
+
+	case 0x1c:
+	case 0x2c:
+		/*  Avoid a debug message.  */
+		break;
+
+	default:if (writeflag == MEM_WRITE) {
+			fatal("[ gc: unimplemented write to "
+			    "offset 0x%x: data=0x%x ]\n", (int)
+			    relative_addr, (int)idata);
+		} else {
+			fatal("[ gc: unimplemented read from "
+			    "offset 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(gc)
+{
+	struct gc_data *d;
+	int i;
+
+	CHECK_ALLOCATION(d = (struct gc_data *) malloc(sizeof(struct gc_data)));
+	memset(d, 0, sizeof(struct gc_data));
+
+	/*  Connect to the CPU interrupt pin:  */
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
+
+	/*
+	 *  Register the 64 Grand Central interrupts (32 lo, 32 hi):
+	 */
+	for (i=0; i<32; i++) {
+		struct interrupt templ;
+		char n[300];
+		snprintf(n, sizeof(n), "%s.gc.lo.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 1 << i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = gc_lo_interrupt_assert;
+		templ.interrupt_deassert = gc_lo_interrupt_deassert;
+		interrupt_handler_register(&templ);
+
+		snprintf(n, sizeof(n), "%s.gc.hi.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 1 << i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = gc_hi_interrupt_assert;
+		templ.interrupt_deassert = gc_hi_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	memory_device_register(devinit->machine->memory, "gc",
+	    devinit->addr, DEV_GC_LENGTH, dev_gc_access, d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_gc.cc gxemul-0.7.0+dfsg/src/devices/dev_gc.cc
--- gxemul-0.6.2/src/devices/dev_gc.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_gc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,252 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *  
- *  COMMENT: Grand Central Interrupt controller (used by MacPPC)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define	DEV_GC_LENGTH		0x100
-
-struct gc_data {
-	struct interrupt cpu_irq;
-
-	uint32_t	status_hi;
-	uint32_t	status_lo;
-	uint32_t	enable_hi;
-	uint32_t	enable_lo;
-};
-
-
-void gc_hi_interrupt_assert(struct interrupt *interrupt)
-{
-	struct gc_data *d = (struct gc_data *) interrupt->extra;
-	d->status_hi |= interrupt->line;
-	if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
-		INTERRUPT_ASSERT(d->cpu_irq);
-}
-void gc_hi_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct gc_data *d = (struct gc_data *) interrupt->extra;
-	d->status_hi &= ~interrupt->line;
-	if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
-		INTERRUPT_DEASSERT(d->cpu_irq);
-}
-void gc_lo_interrupt_assert(struct interrupt *interrupt)
-{
-	struct gc_data *d = (struct gc_data *) interrupt->extra;
-	d->status_lo |= interrupt->line;
-	if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
-		INTERRUPT_ASSERT(d->cpu_irq);
-}
-void gc_lo_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct gc_data *d = (struct gc_data *) interrupt->extra;
-	d->status_lo &= ~interrupt->line;
-	if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
-		INTERRUPT_DEASSERT(d->cpu_irq);
-}
-
-
-DEVICE_ACCESS(gc)
-{
-	struct gc_data *d = (struct gc_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-#if 0
-#define INT_STATE_REG_H  (interrupt_reg + 0x00)
-#define INT_ENABLE_REG_H (interrupt_reg + 0x04)
-#define INT_CLEAR_REG_H  (interrupt_reg + 0x08)
-#define INT_LEVEL_REG_H  (interrupt_reg + 0x0c)
-#define INT_STATE_REG_L  (interrupt_reg + 0x10)
-#define INT_ENABLE_REG_L (interrupt_reg + 0x14)
-#define INT_CLEAR_REG_L  (interrupt_reg + 0x18)
-#define INT_LEVEL_REG_L  (interrupt_reg + 0x1c)
-#endif
-
-	case 0x10:
-		if (writeflag == MEM_READ)
-			odata = d->status_hi & d->enable_hi;
-		break;
-
-	case 0x14:
-		if (writeflag == MEM_READ)
-			odata = d->enable_hi;
-		else {
-			int old_assert = (d->status_lo & d->enable_lo
-			    || d->status_hi & d->enable_hi);
-			int new_assert;
-			d->enable_hi = idata;
-
-			new_assert = (d->status_lo & d->enable_lo ||
-			    d->status_hi & d->enable_hi);
-
-			if (old_assert && !new_assert)
-				INTERRUPT_DEASSERT(d->cpu_irq);
-			else if (!old_assert && new_assert)
-				INTERRUPT_ASSERT(d->cpu_irq);
-		}
-		break;
-
-	case 0x18:
-		if (writeflag == MEM_WRITE) {
-			int old_assert = (d->status_lo & d->enable_lo
-			    || d->status_hi & d->enable_hi);
-			int new_assert;
-			d->status_hi &= ~idata;
-
-			new_assert = (d->status_lo & d->enable_lo ||
-			    d->status_hi & d->enable_hi);
-
-			if (old_assert && !new_assert)
-				INTERRUPT_DEASSERT(d->cpu_irq);
-			else if (!old_assert && new_assert)
-				INTERRUPT_ASSERT(d->cpu_irq);
-		}
-		break;
-
-	case 0x20:
-		if (writeflag == MEM_READ)
-			odata = d->status_lo & d->enable_lo;
-		break;
-
-	case 0x24:
-		if (writeflag == MEM_READ)
-			odata = d->enable_lo;
-		else {
-			int old_assert = (d->status_lo & d->enable_lo
-			    || d->status_hi & d->enable_hi);
-			int new_assert;
-			d->enable_lo = idata;
-
-			new_assert = (d->status_lo & d->enable_lo ||
-			    d->status_hi & d->enable_hi);
-
-			if (old_assert && !new_assert)
-				INTERRUPT_DEASSERT(d->cpu_irq);
-			else if (!old_assert && new_assert)
-				INTERRUPT_ASSERT(d->cpu_irq);
-		}
-		break;
-
-	case 0x28:
-		if (writeflag == MEM_WRITE) {
-			int old_assert = (d->status_lo & d->enable_lo
-			    || d->status_hi & d->enable_hi);
-			int new_assert;
-			d->status_lo &= ~idata;
-
-			new_assert = (d->status_lo & d->enable_lo ||
-			    d->status_hi & d->enable_hi);
-
-			if (old_assert && !new_assert)
-				INTERRUPT_DEASSERT(d->cpu_irq);
-			else if (!old_assert && new_assert)
-				INTERRUPT_ASSERT(d->cpu_irq);
-		}
-		break;
-
-	case 0x1c:
-	case 0x2c:
-		/*  Avoid a debug message.  */
-		break;
-
-	default:if (writeflag == MEM_WRITE) {
-			fatal("[ gc: unimplemented write to "
-			    "offset 0x%x: data=0x%x ]\n", (int)
-			    relative_addr, (int)idata);
-		} else {
-			fatal("[ gc: unimplemented read from "
-			    "offset 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(gc)
-{
-	struct gc_data *d;
-	int i;
-
-	CHECK_ALLOCATION(d = (struct gc_data *) malloc(sizeof(struct gc_data)));
-	memset(d, 0, sizeof(struct gc_data));
-
-	/*  Connect to the CPU interrupt pin:  */
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
-
-	/*
-	 *  Register the 64 Grand Central interrupts (32 lo, 32 hi):
-	 */
-	for (i=0; i<32; i++) {
-		struct interrupt templ;
-		char n[300];
-		snprintf(n, sizeof(n), "%s.gc.lo.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 1 << i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = gc_lo_interrupt_assert;
-		templ.interrupt_deassert = gc_lo_interrupt_deassert;
-		interrupt_handler_register(&templ);
-
-		snprintf(n, sizeof(n), "%s.gc.hi.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 1 << i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = gc_hi_interrupt_assert;
-		templ.interrupt_deassert = gc_hi_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	memory_device_register(devinit->machine->memory, "gc",
-	    devinit->addr, DEV_GC_LENGTH, dev_gc_access, d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_gt.c gxemul-0.7.0+dfsg/src/devices/dev_gt.c
--- gxemul-0.6.2/src/devices/dev_gt.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_gt.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,309 @@
+/*
+ *  Copyright (C) 2003-2010  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Galileo Technology GT-64xxx PCI controller
+ *
+ *	GT-64011	Used in Cobalt machines.
+ *	GT-64120	Used in evbmips machines (Malta).
+ *	GT-64260	Used in mvmeppc machines.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_pci.h"
+#include "cpu.h"
+#include "devices.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "timer.h"
+
+#include "thirdparty/gtreg.h"
+
+
+#define	TICK_SHIFT		14
+
+/*  #define debug fatal  */
+
+#define PCI_PRODUCT_GALILEO_GT64011  0x4146    /*  GT-64011  */
+#define	PCI_PRODUCT_GALILEO_GT64120  0x4620    /*  GT-64120  */
+#define	PCI_PRODUCT_GALILEO_GT64260  0x6430    /*  GT-64260  */
+
+
+struct gt_data {
+	int		type;
+
+	struct timer	*timer;
+	struct interrupt timer0_irq;
+	int		interrupt_hz;
+	int		pending_timer0_interrupts;
+
+	/*  Address decode registers:  */
+	uint32_t	decode[GT_N_DECODE_REGS];
+
+	struct pci_data	*pci_data;
+};
+
+
+/*
+ *  timer_tick():
+ *
+ *  Called d->interrupt_hz times per (real-world) second.
+ */
+static void timer_tick(struct timer *timer, void *extra)
+{
+	struct gt_data *d = (struct gt_data *) extra;
+	d->pending_timer0_interrupts ++;
+}
+
+
+DEVICE_TICK(gt)
+{
+	struct gt_data *d = (struct gt_data *) extra;
+	if (d->pending_timer0_interrupts > 0)
+		INTERRUPT_ASSERT(d->timer0_irq);
+}
+
+
+DEVICE_ACCESS(gt)
+{
+	struct gt_data *d = (struct gt_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int bus, dev, func, reg;
+	size_t i;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case GT_PCI0IOLD_OFS:
+	case GT_PCI0IOHD_OFS:
+	case GT_PCI0M0LD_OFS:
+	case GT_PCI0M0HD_OFS:
+	case GT_PCI0M1LD_OFS:
+	case GT_PCI0M1HD_OFS:
+	case GT_PCI0IOREMAP_OFS:
+	case GT_PCI0M0REMAP_OFS:
+	case GT_PCI0M1REMAP_OFS:
+		if (writeflag == MEM_READ) {
+			odata = d->decode[relative_addr / 8];
+			debug("[ gt: read from offset 0x%x: 0x%x ]\n",
+			    (int)relative_addr, (int)odata);
+		} else {
+			d->decode[relative_addr / 8] = idata;
+			fatal("[ gt: write to offset 0x%x: 0x%x (TODO) ]\n",
+			    (int)relative_addr, (int)idata);
+		}
+		break;
+
+	case GT_PCI0_CMD_OFS:
+		if (writeflag == MEM_WRITE) {
+			debug("[ gt: write to GT_PCI0_CMD: 0x%08x (TODO) ]\n",
+			    (int)idata);
+		} else {
+			debug("[ gt: read from GT_PCI0_CMD (0x%08x) (TODO) ]\n",
+			    (int)odata);
+		}
+		break;
+
+	case GT_INTR_CAUSE:
+		if (writeflag == MEM_WRITE) {
+			debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n",
+			    (int)idata);
+			return 1;
+		} else {
+			odata = GTIC_T0EXP;
+			INTERRUPT_DEASSERT(d->timer0_irq);
+
+			if (d->pending_timer0_interrupts > 0)
+				d->pending_timer0_interrupts --;
+
+			debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n",
+			    (int)odata);
+		}
+		break;
+
+	case GT_PCI0_INTR_ACK:
+		odata = cpu->machine->isa_pic_data.last_int;
+		/*  TODO: Actually ack the interrupt?  */
+		break;
+
+	case GT_TIMER_CTRL:
+		if (writeflag == MEM_WRITE) {
+			if (idata & ENTC0) {
+				/*  TODO: Don't hardcode this.  */
+				d->interrupt_hz = 100;
+				if (d->timer == NULL)
+					d->timer = timer_add(d->interrupt_hz,
+					    timer_tick, d);
+				else
+					timer_update_frequency(d->timer,
+					    d->interrupt_hz);
+			}
+		}
+		break;
+
+	case GT_PCI0_CFG_ADDR:
+		if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
+			// Hack:
+			if (len == sizeof(uint32_t))
+			{
+				idata = data[0] + (data[1] << 8)
+					+ (data[2] << 16) + (data[3] << 24);
+			}
+		}
+		bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
+		bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
+		break;
+
+	case GT_PCI0_CFG_DATA:
+		if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
+			// Hack:
+			if (len == sizeof(uint32_t))
+			{
+				idata = data[0] + (data[1] << 8)
+					+ (data[2] << 16) + (data[3] << 24);
+			}
+		}
+		bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
+		    &odata : &idata, len, writeflag);
+		break;
+
+	default:
+		if (writeflag == MEM_READ) {
+			debug("[ gt: read from addr 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			debug("[ gt: write to addr 0x%x:", (int)relative_addr);
+			for (i=0; i<len; i++)
+				debug(" %02x", data[i]);
+			debug(" ]\n");
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_gt_init():
+ *
+ *  Initialize a Gallileo PCI controller device. First, the controller itself
+ *  is added to the bus, then a pointer to the bus is returned.
+ */
+struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, const char *timer_irq_path, const char *isa_irq_path, int type)
+{
+	struct gt_data *d;
+	uint64_t pci_portbase = 0, pci_membase = 0;
+	uint64_t isa_portbase = 0, isa_membase = 0;
+	uint64_t pci_io_offset = 0, pci_mem_offset = 0;
+	const char *gt_name = "NO";
+
+	CHECK_ALLOCATION(d = (struct gt_data *) malloc(sizeof(struct gt_data)));
+	memset(d, 0, sizeof(struct gt_data));
+
+	INTERRUPT_CONNECT(timer_irq_path, d->timer0_irq);
+
+	switch (type) {
+	case 11:
+		/*  Cobalt:  */
+		d->type = PCI_PRODUCT_GALILEO_GT64011;
+		gt_name = "gt64011";
+		pci_io_offset = 0;
+		pci_mem_offset = 0;
+		pci_portbase = 0x10000000ULL;
+		pci_membase = 0x10100000ULL;
+		isa_portbase = 0x10000000ULL;
+		isa_membase = 0x10100000ULL;
+		break;
+	case 120:
+		/*  EVBMIPS (Malta):  */
+		d->type = PCI_PRODUCT_GALILEO_GT64120;
+		gt_name = "gt64120";
+		pci_io_offset = 0;
+		pci_mem_offset = 0;
+		pci_portbase = 0x18000000ULL;
+		pci_membase = 0x10000000ULL;
+		isa_portbase = 0x18000000ULL;
+		isa_membase = 0x10000000ULL;
+		break;
+	case 260:
+		/*  MVMEPPC (mvme5500):  */
+		d->type = PCI_PRODUCT_GALILEO_GT64260;
+		gt_name = "gt64260";
+		pci_io_offset = 0;
+		pci_mem_offset = 0;
+		pci_portbase = 0x18000000ULL;
+		pci_membase = 0x10000000ULL;
+		isa_portbase = 0x18000000ULL;
+		isa_membase = 0x10000000ULL;
+		break;
+	default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
+		exit(1);
+	}
+
+
+	/*
+	 *  TODO: FIX THESE! Hardcoded numbers = bad.
+	 */
+	d->decode[GT_PCI0IOLD_OFS / 8] = pci_portbase >> 21;
+	d->decode[GT_PCI0IOHD_OFS / 8] = 0x40;
+	d->decode[GT_PCI0M0LD_OFS / 8] = 0x80;
+	d->decode[GT_PCI0M0HD_OFS / 8] = 0x3f;
+	d->decode[GT_PCI0M1LD_OFS / 8] = 0xc1;
+	d->decode[GT_PCI0M1HD_OFS / 8] = 0x5e;
+	d->decode[GT_PCI0IOREMAP_OFS / 8] = d->decode[GT_PCI0IOLD_OFS / 8];
+	d->decode[GT_PCI0M0REMAP_OFS / 8] = d->decode[GT_PCI0M0LD_OFS / 8];
+	d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8];
+
+	d->pci_data = bus_pci_init(machine,
+	    "TODO_gt_irq", pci_io_offset, pci_mem_offset,
+	    pci_portbase, pci_membase, "TODO_pci_irqbase",
+	    isa_portbase, isa_membase, isa_irq_path);
+
+	/*
+	 *  According to NetBSD/cobalt:
+	 *  pchb0 at pci0 dev 0 function 0: Galileo GT-64011
+	 *  System Controller, rev 1
+	 */
+	bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name);
+
+	memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
+	    dev_gt_access, d, DM_DEFAULT, NULL);
+	machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT);
+
+	return d->pci_data;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_gt.cc gxemul-0.7.0+dfsg/src/devices/dev_gt.cc
--- gxemul-0.6.2/src/devices/dev_gt.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_gt.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,309 +0,0 @@
-/*
- *  Copyright (C) 2003-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Galileo Technology GT-64xxx PCI controller
- *
- *	GT-64011	Used in Cobalt machines.
- *	GT-64120	Used in evbmips machines (Malta).
- *	GT-64260	Used in mvmeppc machines.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_pci.h"
-#include "cpu.h"
-#include "devices.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "timer.h"
-
-#include "thirdparty/gtreg.h"
-
-
-#define	TICK_SHIFT		14
-
-/*  #define debug fatal  */
-
-#define PCI_PRODUCT_GALILEO_GT64011  0x4146    /*  GT-64011  */
-#define	PCI_PRODUCT_GALILEO_GT64120  0x4620    /*  GT-64120  */
-#define	PCI_PRODUCT_GALILEO_GT64260  0x6430    /*  GT-64260  */
-
-
-struct gt_data {
-	int		type;
-
-	struct timer	*timer;
-	struct interrupt timer0_irq;
-	int		interrupt_hz;
-	int		pending_timer0_interrupts;
-
-	/*  Address decode registers:  */
-	uint32_t	decode[GT_N_DECODE_REGS];
-
-	struct pci_data	*pci_data;
-};
-
-
-/*
- *  timer_tick():
- *
- *  Called d->interrupt_hz times per (real-world) second.
- */
-static void timer_tick(struct timer *timer, void *extra)
-{
-	struct gt_data *d = (struct gt_data *) extra;
-	d->pending_timer0_interrupts ++;
-}
-
-
-DEVICE_TICK(gt)
-{
-	struct gt_data *d = (struct gt_data *) extra;
-	if (d->pending_timer0_interrupts > 0)
-		INTERRUPT_ASSERT(d->timer0_irq);
-}
-
-
-DEVICE_ACCESS(gt)
-{
-	struct gt_data *d = (struct gt_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int bus, dev, func, reg;
-	size_t i;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case GT_PCI0IOLD_OFS:
-	case GT_PCI0IOHD_OFS:
-	case GT_PCI0M0LD_OFS:
-	case GT_PCI0M0HD_OFS:
-	case GT_PCI0M1LD_OFS:
-	case GT_PCI0M1HD_OFS:
-	case GT_PCI0IOREMAP_OFS:
-	case GT_PCI0M0REMAP_OFS:
-	case GT_PCI0M1REMAP_OFS:
-		if (writeflag == MEM_READ) {
-			odata = d->decode[relative_addr / 8];
-			debug("[ gt: read from offset 0x%x: 0x%x ]\n",
-			    (int)relative_addr, (int)odata);
-		} else {
-			d->decode[relative_addr / 8] = idata;
-			fatal("[ gt: write to offset 0x%x: 0x%x (TODO) ]\n",
-			    (int)relative_addr, (int)idata);
-		}
-		break;
-
-	case GT_PCI0_CMD_OFS:
-		if (writeflag == MEM_WRITE) {
-			debug("[ gt: write to GT_PCI0_CMD: 0x%08x (TODO) ]\n",
-			    (int)idata);
-		} else {
-			debug("[ gt: read from GT_PCI0_CMD (0x%08x) (TODO) ]\n",
-			    (int)odata);
-		}
-		break;
-
-	case GT_INTR_CAUSE:
-		if (writeflag == MEM_WRITE) {
-			debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n",
-			    (int)idata);
-			return 1;
-		} else {
-			odata = GTIC_T0EXP;
-			INTERRUPT_DEASSERT(d->timer0_irq);
-
-			if (d->pending_timer0_interrupts > 0)
-				d->pending_timer0_interrupts --;
-
-			debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n",
-			    (int)odata);
-		}
-		break;
-
-	case GT_PCI0_INTR_ACK:
-		odata = cpu->machine->isa_pic_data.last_int;
-		/*  TODO: Actually ack the interrupt?  */
-		break;
-
-	case GT_TIMER_CTRL:
-		if (writeflag == MEM_WRITE) {
-			if (idata & ENTC0) {
-				/*  TODO: Don't hardcode this.  */
-				d->interrupt_hz = 100;
-				if (d->timer == NULL)
-					d->timer = timer_add(d->interrupt_hz,
-					    timer_tick, d);
-				else
-					timer_update_frequency(d->timer,
-					    d->interrupt_hz);
-			}
-		}
-		break;
-
-	case GT_PCI0_CFG_ADDR:
-		if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
-			// Hack:
-			if (len == sizeof(uint32_t))
-			{
-				idata = data[0] + (data[1] << 8)
-					+ (data[2] << 16) + (data[3] << 24);
-			}
-		}
-		bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
-		bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
-		break;
-
-	case GT_PCI0_CFG_DATA:
-		if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
-			// Hack:
-			if (len == sizeof(uint32_t))
-			{
-				idata = data[0] + (data[1] << 8)
-					+ (data[2] << 16) + (data[3] << 24);
-			}
-		}
-		bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
-		    &odata : &idata, len, writeflag);
-		break;
-
-	default:
-		if (writeflag == MEM_READ) {
-			debug("[ gt: read from addr 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			debug("[ gt: write to addr 0x%x:", (int)relative_addr);
-			for (i=0; i<len; i++)
-				debug(" %02x", data[i]);
-			debug(" ]\n");
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_gt_init():
- *
- *  Initialize a Gallileo PCI controller device. First, the controller itself
- *  is added to the bus, then a pointer to the bus is returned.
- */
-struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, const char *timer_irq_path, const char *isa_irq_path, int type)
-{
-	struct gt_data *d;
-	uint64_t pci_portbase = 0, pci_membase = 0;
-	uint64_t isa_portbase = 0, isa_membase = 0;
-	uint64_t pci_io_offset = 0, pci_mem_offset = 0;
-	const char *gt_name = "NO";
-
-	CHECK_ALLOCATION(d = (struct gt_data *) malloc(sizeof(struct gt_data)));
-	memset(d, 0, sizeof(struct gt_data));
-
-	INTERRUPT_CONNECT(timer_irq_path, d->timer0_irq);
-
-	switch (type) {
-	case 11:
-		/*  Cobalt:  */
-		d->type = PCI_PRODUCT_GALILEO_GT64011;
-		gt_name = "gt64011";
-		pci_io_offset = 0;
-		pci_mem_offset = 0;
-		pci_portbase = 0x10000000ULL;
-		pci_membase = 0x10100000ULL;
-		isa_portbase = 0x10000000ULL;
-		isa_membase = 0x10100000ULL;
-		break;
-	case 120:
-		/*  EVBMIPS (Malta):  */
-		d->type = PCI_PRODUCT_GALILEO_GT64120;
-		gt_name = "gt64120";
-		pci_io_offset = 0;
-		pci_mem_offset = 0;
-		pci_portbase = 0x18000000ULL;
-		pci_membase = 0x10000000ULL;
-		isa_portbase = 0x18000000ULL;
-		isa_membase = 0x10000000ULL;
-		break;
-	case 260:
-		/*  MVMEPPC (mvme5500):  */
-		d->type = PCI_PRODUCT_GALILEO_GT64260;
-		gt_name = "gt64260";
-		pci_io_offset = 0;
-		pci_mem_offset = 0;
-		pci_portbase = 0x18000000ULL;
-		pci_membase = 0x10000000ULL;
-		isa_portbase = 0x18000000ULL;
-		isa_membase = 0x10000000ULL;
-		break;
-	default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
-		exit(1);
-	}
-
-
-	/*
-	 *  TODO: FIX THESE! Hardcoded numbers = bad.
-	 */
-	d->decode[GT_PCI0IOLD_OFS / 8] = pci_portbase >> 21;
-	d->decode[GT_PCI0IOHD_OFS / 8] = 0x40;
-	d->decode[GT_PCI0M0LD_OFS / 8] = 0x80;
-	d->decode[GT_PCI0M0HD_OFS / 8] = 0x3f;
-	d->decode[GT_PCI0M1LD_OFS / 8] = 0xc1;
-	d->decode[GT_PCI0M1HD_OFS / 8] = 0x5e;
-	d->decode[GT_PCI0IOREMAP_OFS / 8] = d->decode[GT_PCI0IOLD_OFS / 8];
-	d->decode[GT_PCI0M0REMAP_OFS / 8] = d->decode[GT_PCI0M0LD_OFS / 8];
-	d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8];
-
-	d->pci_data = bus_pci_init(machine,
-	    "TODO_gt_irq", pci_io_offset, pci_mem_offset,
-	    pci_portbase, pci_membase, "TODO_pci_irqbase",
-	    isa_portbase, isa_membase, isa_irq_path);
-
-	/*
-	 *  According to NetBSD/cobalt:
-	 *  pchb0 at pci0 dev 0 function 0: Galileo GT-64011
-	 *  System Controller, rev 1
-	 */
-	bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name);
-
-	memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
-	    dev_gt_access, d, DM_DEFAULT, NULL);
-	machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT);
-
-	return d->pci_data;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_hammerhead.c gxemul-0.7.0+dfsg/src/devices/dev_hammerhead.c
--- gxemul-0.6.2/src/devices/dev_hammerhead.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_hammerhead.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,103 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Hammerhead controller, for the secondary CPU on MacPPC machines
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+/*  #define debug fatal  */
+
+void ppc_pc_to_pointers(struct cpu *);
+void ppc32_pc_to_pointers(struct cpu *);
+
+#define	DEV_HAMMERHEAD_LENGTH		4
+
+struct hammerhead_data {
+	int	dummy;
+};
+
+
+DEVICE_ACCESS(hammerhead)
+{
+	/*  struct hammerhead_data *d = extra;  */
+	uint64_t idata = 0, odata=0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (writeflag == MEM_WRITE) {
+		int my_id = cpu->cpu_id;
+		struct cpu *other_cpu = cpu->machine->cpus[!my_id];
+
+		debug("[ HAMMERHEAD: from cpu%i to cpu%i: new pc = 0x%llx ]\n",
+		    my_id, !my_id, (long long)idata);
+
+if (idata <= 0x100)
+return 1;
+
+		other_cpu->running = true;
+		other_cpu->pc = idata;
+
+		if (other_cpu->is_32bit)
+			ppc32_pc_to_pointers(other_cpu);
+		else
+			ppc_pc_to_pointers(other_cpu);
+	} else {
+		fatal("[ HAMMERHEAD read: TODO ]\n");
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(hammerhead)
+{
+	struct hammerhead_data *d;
+
+	CHECK_ALLOCATION(d = (struct hammerhead_data *) malloc(sizeof(struct hammerhead_data)));
+	memset(d, 0, sizeof(struct hammerhead_data));
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_HAMMERHEAD_LENGTH, dev_hammerhead_access, d,
+	    DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_hammerhead.cc gxemul-0.7.0+dfsg/src/devices/dev_hammerhead.cc
--- gxemul-0.6.2/src/devices/dev_hammerhead.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_hammerhead.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,103 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Hammerhead controller, for the secondary CPU on MacPPC machines
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-/*  #define debug fatal  */
-
-void ppc_pc_to_pointers(struct cpu *);
-void ppc32_pc_to_pointers(struct cpu *);
-
-#define	DEV_HAMMERHEAD_LENGTH		4
-
-struct hammerhead_data {
-	int	dummy;
-};
-
-
-DEVICE_ACCESS(hammerhead)
-{
-	/*  struct hammerhead_data *d = extra;  */
-	uint64_t idata = 0, odata=0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (writeflag == MEM_WRITE) {
-		int my_id = cpu->cpu_id;
-		struct cpu *other_cpu = cpu->machine->cpus[!my_id];
-
-		debug("[ HAMMERHEAD: from cpu%i to cpu%i: new pc = 0x%llx ]\n",
-		    my_id, !my_id, (long long)idata);
-
-if (idata <= 0x100)
-return 1;
-
-		other_cpu->running = 1;
-		other_cpu->pc = idata;
-
-		if (other_cpu->is_32bit)
-			ppc32_pc_to_pointers(other_cpu);
-		else
-			ppc_pc_to_pointers(other_cpu);
-	} else {
-		fatal("[ HAMMERHEAD read: TODO ]\n");
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(hammerhead)
-{
-	struct hammerhead_data *d;
-
-	CHECK_ALLOCATION(d = (struct hammerhead_data *) malloc(sizeof(struct hammerhead_data)));
-	memset(d, 0, sizeof(struct hammerhead_data));
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_HAMMERHEAD_LENGTH, dev_hammerhead_access, d,
-	    DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_i80321.c gxemul-0.7.0+dfsg/src/devices/dev_i80321.c
--- gxemul-0.6.2/src/devices/dev_i80321.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_i80321.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,481 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Intel i80321 (ARM) core functionality
+ *
+ *	o)  Interrupt controller
+ *	o)  Timer
+ *	o)  PCI controller
+ *	o)  Memory controller
+ *	o)  I2C
+ *
+ *  TODO:
+ *	o)  More or less everything.
+ *	o)  This is hardcoded for little endian emulation.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "timer.h"
+
+#include "thirdparty/i80321reg.h"
+#include "thirdparty/iopi2creg.h"
+
+
+#define	TICK_SHIFT		15
+#define	DEV_I80321_LENGTH	VERDE_PMMR_SIZE
+
+struct i80321_data {
+	/*  Interrupt Controller  */
+	struct interrupt irq;
+	uint32_t	*status;	/*  Note: these point to i80321_isrc  */
+	uint32_t	*enable;	/*  and i80321_inten in the CPU!  */
+
+	/*  Timer:  */
+	struct timer	*timer;
+	double		hz;
+	int		pending_tmr0_interrupts;
+
+	/*  PCI Controller:  */
+	uint32_t	pci_addr;
+	struct pci_data *pci_bus;
+
+	/*  Memory Controller:  */
+	uint32_t	mcu_reg[0x100 / sizeof(uint32_t)];
+
+	/*  I2C Controller:  */
+	uint32_t	i2c_reg[VERDE_I2C_SIZE / sizeof(uint32_t)];
+};
+
+
+static void i80321_assert(struct i80321_data *d, uint32_t linemask)
+{
+	*d->status |= linemask;
+	if (*d->status & *d->enable)
+		INTERRUPT_ASSERT(d->irq);
+}
+static void i80321_deassert(struct i80321_data *d, uint32_t linemask)
+{
+	*d->status &= ~linemask;
+	if (!(*d->status & *d->enable))
+		INTERRUPT_DEASSERT(d->irq);
+}
+
+
+/*  
+ *  i80321_interrupt_assert():
+ *  i80321_interrupt_deassert():
+ *
+ *  Called whenever an i80321 interrupt is asserted/deasserted.
+ */
+void i80321_interrupt_assert(struct interrupt *interrupt)
+{ i80321_assert((struct i80321_data *)interrupt->extra, interrupt->line); }
+void i80321_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct i80321_data *d = (struct i80321_data *) interrupt->extra;
+
+	/*  Ack. timer interrupts:  */
+	if (interrupt->line == 1 << 9 &&
+	    d->pending_tmr0_interrupts > 0)
+		d->pending_tmr0_interrupts --;
+
+	i80321_deassert(d, interrupt->line);
+}
+
+
+/*  TMR0 ticks, called d->hz times per second.  */
+static void tmr0_tick(struct timer *t, void *extra)
+{
+	struct i80321_data *d = (struct i80321_data *) extra;
+	d->pending_tmr0_interrupts ++;
+}
+
+
+DEVICE_TICK(i80321)
+{
+	struct i80321_data *d = (struct i80321_data *) extra;
+
+	if (cpu->cd.arm.tmr0 & TMRx_ENABLE && d->pending_tmr0_interrupts > 0) {
+		i80321_assert(d, 1 << 9);
+		cpu->cd.arm.tisr |= TISR_TMR0;
+	} else {
+		i80321_deassert(d, 1 << 9);
+		cpu->cd.arm.tisr &= ~TISR_TMR0;
+	}
+}
+
+        
+DEVICE_ACCESS(i80321)
+{
+	struct i80321_data *d = (struct i80321_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	const char *n = NULL;
+	int bus, dev, func, reg;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  PCI configuration space:  */
+	if (relative_addr >= 0x100 && relative_addr < 0x140) {
+		/*  TODO  */
+		goto ret;
+	}
+
+	/*  MCU registers:  */
+	if (relative_addr >= VERDE_MCU_BASE &&
+	    relative_addr <  VERDE_MCU_BASE + VERDE_MCU_SIZE) {
+		int regnr = (relative_addr - VERDE_MCU_BASE) / sizeof(uint32_t);
+		if (writeflag == MEM_WRITE)
+			d->mcu_reg[regnr] = idata;
+		else
+			odata = d->mcu_reg[regnr];
+	}
+
+	/*  I2C registers:  */
+	if (relative_addr >= VERDE_I2C_BASE &&
+	    relative_addr <  VERDE_I2C_BASE + VERDE_I2C_SIZE) {
+		int regnr = (relative_addr - VERDE_I2C_BASE) / sizeof(uint32_t);
+		if (writeflag == MEM_WRITE)
+			d->i2c_reg[regnr] = idata;
+		else
+			odata = d->i2c_reg[regnr];
+	}
+
+
+	switch (relative_addr) {
+
+	/*  Address Translation Unit:  */
+	case VERDE_ATU_BASE + ATU_IALR0:
+	case VERDE_ATU_BASE + ATU_IATVR0:
+	case VERDE_ATU_BASE + ATU_IALR1:
+	case VERDE_ATU_BASE + ATU_IALR2:
+	case VERDE_ATU_BASE + ATU_IATVR2:
+	case VERDE_ATU_BASE + ATU_OIOWTVR:
+	case VERDE_ATU_BASE + ATU_OMWTVR0:
+	case VERDE_ATU_BASE + ATU_OUMWTVR0:
+	case VERDE_ATU_BASE + ATU_OMWTVR1:
+	case VERDE_ATU_BASE + ATU_OUMWTVR1:
+		/*  Ignoring these for now. TODO  */
+		break;
+	case VERDE_ATU_BASE + ATU_ATUCR:
+		/*  ATU configuration register; ignored for now. TODO  */
+		break;
+	case VERDE_ATU_BASE + ATU_PCSR:
+		/*  TODO: Temporary hack to allow NetBSD/evbarm to
+		    reboot itself.  Should be rewritten as soon as possible!  */
+		if (writeflag == MEM_WRITE && idata == 0x30) {
+			int j;
+			for (j=0; j<cpu->machine->ncpus; j++)
+				cpu->machine->cpus[j]->running = false;
+		}
+		break;
+	case VERDE_ATU_BASE + ATU_ATUIMR:
+	case VERDE_ATU_BASE + ATU_IABAR3:
+	case VERDE_ATU_BASE + ATU_IAUBAR3:
+	case VERDE_ATU_BASE + ATU_IALR3:
+	case VERDE_ATU_BASE + ATU_IATVR3:
+		/*  Ignoring these for now. TODO  */
+		break;
+	case VERDE_ATU_BASE + ATU_OCCAR:
+		/*  PCI address  */
+		if (writeflag == MEM_WRITE) {
+			d->pci_addr = idata;
+			bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
+			bus = 0;	/*  NOTE  */
+			bus_pci_setaddr(cpu, d->pci_bus, bus, dev, func, reg);
+		} else {
+			odata = d->pci_addr;
+		}
+		break;
+	case VERDE_ATU_BASE + ATU_OCCDR:
+	case VERDE_ATU_BASE + ATU_OCCDR + 1:
+	case VERDE_ATU_BASE + ATU_OCCDR + 2:
+	case VERDE_ATU_BASE + ATU_OCCDR + 3:
+		/*  PCI data  */
+		if (writeflag == MEM_READ) {
+			uint64_t tmp;
+			bus_pci_data_access(cpu, d->pci_bus, &tmp,
+			    sizeof(uint32_t), MEM_READ);
+			switch (relative_addr) {
+			case VERDE_ATU_BASE + ATU_OCCDR + 1:
+				odata = tmp >> 8; break;
+			case VERDE_ATU_BASE + ATU_OCCDR + 2:
+				odata = tmp >> 16; break;
+			case VERDE_ATU_BASE + ATU_OCCDR + 3:
+				odata = tmp >> 24; break;
+			default:odata = tmp;
+			}
+		} else {
+			uint64_t tmp;
+			unsigned int i;
+			int r = relative_addr - (VERDE_ATU_BASE + ATU_OCCDR);
+			bus_pci_data_access(cpu, d->pci_bus, &tmp,
+			    sizeof(uint32_t), MEM_READ);
+			for (i=0; i<len; i++) {
+				uint8_t b = idata >> (i*8);
+				tmp &= ~(0xff << ((r+i)*8));
+				tmp |= b << ((r+i)*8);
+			}
+			tmp &= 0xffffffff;  /* needed because << is 32-bit */
+			bus_pci_data_access(cpu, d->pci_bus, &tmp,
+			    sizeof(uint32_t), MEM_WRITE);
+		}
+		break;
+	case VERDE_ATU_BASE + ATU_PCIXSR:
+		odata = 0;		/*  TODO  */
+		break;
+
+	/*  Memory Controller Unit:  */
+	case VERDE_MCU_BASE + MCU_SDIR:
+		n = "MCU_SDIR (DDR SDRAM Init Register)";
+		break;
+	case VERDE_MCU_BASE + MCU_SDCR:
+		n = "MCU_SDCR (DDR SDRAM Control Register)";
+		break;
+	case VERDE_MCU_BASE + MCU_SDBR:
+		n = "MCU_SDBR (SDRAM Base Register)";
+		break;
+	case VERDE_MCU_BASE + MCU_SBR0:
+		n = "MCU_SBR0 (SDRAM Boundary 0)";
+		break;
+	case VERDE_MCU_BASE + MCU_SBR1:
+		n = "MCU_SBR1 (SDRAM Boundary 1)";
+		break;
+	case VERDE_MCU_BASE + MCU_ECCR:
+		n = "MCU_ECCR (ECC Control Register)";
+		break;
+	case VERDE_MCU_BASE + MCU_RFR:
+		n = "MCU_RFR (Refresh Frequency Register)";
+		break;
+	case VERDE_MCU_BASE + MCU_DBUDSR:
+		n = "MCU_DBUDSR (Data Bus Pull-up Drive Strength)";
+		break;
+	case VERDE_MCU_BASE + MCU_DBDDSR:
+		n = "MCU_DBDDSR (Data Bus Pull-down Drive Strength)";
+		break;
+	case VERDE_MCU_BASE + MCU_CUDSR:
+		n = "MCU_CUDSR (Clock Pull-up Drive Strength)";
+		break;
+	case VERDE_MCU_BASE + MCU_CDDSR:
+		n = "MCU_CDDSR (Clock Pull-down Drive Strength)";
+		break;
+	case VERDE_MCU_BASE + MCU_CEUDSR:
+		n = "MCU_CEUDSR (Clock En Pull-up Drive Strength)";
+		break;
+	case VERDE_MCU_BASE + MCU_CEDDSR:
+		n = "MCU_CEDDSR (Clock En Pull-down Drive Strength)";
+		break;
+	case VERDE_MCU_BASE + MCU_CSUDSR:
+		n = "MCU_CSUDSR (Chip Sel Pull-up Drive Strength)";
+		break;
+	case VERDE_MCU_BASE + MCU_CSDDSR:
+		n = "MCU_CSDDSR (Chip Sel Pull-down Drive Strength)";
+		break;
+	case VERDE_MCU_BASE + MCU_REUDSR:
+		n = "MCU_REUDSR (Rx En Pull-up Drive Strength)";
+		break;
+	case VERDE_MCU_BASE + MCU_REDDSR:
+		n = "MCU_REDDSR (Rx En Pull-down Drive Strength)";
+		break;
+
+	case VERDE_MCU_BASE + MCU_ABUDSR:
+		n = "MCU_ABUDSR (Addr Bus Pull-up Drive Strength)";
+		break;
+	case VERDE_MCU_BASE + MCU_ABDDSR:
+		n = "MCU_ABDDSR (Addr Bus Pull-down Drive Strength)";
+		break;
+
+	/*  Peripheral Bus Interface Unit  */
+	case VERDE_PBIU_BASE + PBIU_PBCR:
+		n = "PBIU_PBCR (PBIU Control Register)";
+		break;
+	case VERDE_PBIU_BASE + PBIU_PBBAR0:
+		n = "PBIU_PBBAR0 (PBIU Base Address Register 0)";
+		break;
+	case VERDE_PBIU_BASE + PBIU_PBLR0:
+		n = "PBIU_PBLR0 (PBIU Limit Register 0)";
+		break;
+	case VERDE_PBIU_BASE + PBIU_PBBAR1:
+		n = "PBIU_PBBAR1 (PBIU Base Address Register 1)";
+		break;
+	case VERDE_PBIU_BASE + PBIU_PBLR1:
+		n = "PBIU_PBLR1 (PBIU Limit Register 1)";
+		break;
+	case VERDE_PBIU_BASE + PBIU_PBBAR2:
+		n = "PBIU_PBBAR2 (PBIU Base Address Register 2)";
+		break;
+	case VERDE_PBIU_BASE + PBIU_PBLR2:
+		n = "PBIU_PBLR2 (PBIU Limit Register 2)";
+		break;
+
+	/*  TODO:  */
+	case 0x7cc:
+		n = "0x7cc_TODO";
+		break;
+
+	case VERDE_I2C_BASE0 + IIC_ICR:
+		n = "I2C 0, IIC_ICR (control register)";
+		break;
+	case VERDE_I2C_BASE0 + IIC_ISR:
+		n = "I2C 0, IIC_ISR (status register)";
+		break;
+	case VERDE_I2C_BASE0 + IIC_ISAR:
+		n = "I2C 0, IIC_ISAR (slave address register)";
+		break;
+	case VERDE_I2C_BASE0 + IIC_IDBR:
+		n = "I2C 0, IIC_IDBR (data buffer register)";
+		break;
+
+	case VERDE_I2C_BASE1 + IIC_ICR:
+		n = "I2C 1, IIC_ICR (control register)";
+		break;
+	case VERDE_I2C_BASE1 + IIC_ISR:
+		n = "I2C 1, IIC_ISR (status register)";
+		odata = IIC_ISR_ITE;	/*  IDBR Tx empty  */
+		odata |= IIC_ISR_IRF;	/*  IDBR Rx full  */
+		break;
+	case VERDE_I2C_BASE1 + IIC_ISAR:
+		n = "I2C 1, IIC_ISAR (slave address register)";
+		break;
+	case VERDE_I2C_BASE1 + IIC_IDBR:
+		n = "I2C 1, IIC_IDBR (data buffer register)";
+		odata = 7;	/*  TODO  */
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ i80321: read from 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ i80321: write to 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)idata);
+		}
+		exit(1);
+	}
+
+	if (n != NULL) {
+		if (writeflag == MEM_READ) {
+			debug("[ i80321: read from %s: 0x%llx ]\n",
+			    n, (long long)idata);
+		} else {
+			debug("[ i80321: write to %s: 0x%llx ]\n",
+			    n, (long long)idata);
+		}
+	}
+
+ret:
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(i80321)
+{
+	struct i80321_data *d;
+	uint32_t memsize = devinit->machine->physical_ram_in_mb * 1048576;
+	uint32_t base;
+	char tmpstr[300];
+	struct cpu *cpu = devinit->machine->cpus[devinit->
+	    machine->bootstrap_cpu];
+	int i;
+
+	CHECK_ALLOCATION(d = (struct i80321_data *) malloc(sizeof(struct i80321_data)));
+	memset(d, 0, sizeof(struct i80321_data));
+
+	/*  Connect to the CPU interrupt pin:  */
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	/*  Register 32 i80321 interrupts:  */
+	for (i=0; i<32; i++) {
+		struct interrupt templ;
+		char tmpstr2[300];
+		snprintf(tmpstr2, sizeof(tmpstr2), "%s.i80321.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 1 << i;
+		templ.name = tmpstr2;
+		templ.extra = d;
+		templ.interrupt_assert = i80321_interrupt_assert;
+		templ.interrupt_deassert = i80321_interrupt_deassert;
+		interrupt_handler_register(&templ);
+
+		/*
+		 *  Connect the CPU's TMR0 and TMR1 interrupts to these
+		 *  i80321 timer interrupts (nr 9 and 10):
+		 */
+		if (i == 9)
+			INTERRUPT_CONNECT(tmpstr2, cpu->cd.arm.tmr0_irq);
+		if (i == 10)
+			INTERRUPT_CONNECT(tmpstr2, cpu->cd.arm.tmr1_irq);
+	}
+
+	d->status = &cpu->cd.arm.i80321_isrc;
+	d->enable = &cpu->cd.arm.i80321_inten;
+
+	/*  TODO: base = 0 on Iyonix?  */
+	d->mcu_reg[MCU_SDBR / sizeof(uint32_t)] = base = 0xa0000000;
+	d->mcu_reg[MCU_SBR0 / sizeof(uint32_t)] = (base + memsize) >> 25;
+	d->mcu_reg[MCU_SBR1 / sizeof(uint32_t)] = (base + memsize) >> 25;
+
+	snprintf(tmpstr, sizeof(tmpstr), "%s.i80321", devinit->interrupt_path);
+
+	d->pci_bus = bus_pci_init(devinit->machine,
+	    tmpstr	/*  pciirq  */,
+	    0x90000000	/*  TODO: pci_io_offset  */,
+	    0x90010000	/*  TODO: pci_mem_offset  */,
+	    0xffff0000	/*  TODO: pci_portbase  */,
+	    0x00000000	/*  TODO: pci_membase  */,
+	    tmpstr	/*  pci_irqbase  */,
+	    0x90000000	/*  TODO: isa_portbase  */,
+	    0x90010000	/*  TODO: isa_membase  */,
+	    "TODO: isa_irqbase" /*  TODO: isa_irqbase  */);
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_I80321_LENGTH,
+	    dev_i80321_access, d, DM_DEFAULT, NULL);
+
+	/*  TODO: Don't hardcode to 100 Hz!  */
+	d->hz = 100;
+	d->timer = timer_add(d->hz, tmr0_tick, d);
+
+	machine_add_tickfunction(devinit->machine, dev_i80321_tick,
+	    d, TICK_SHIFT);
+
+	devinit->return_ptr = d->pci_bus;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_i80321.cc gxemul-0.7.0+dfsg/src/devices/dev_i80321.cc
--- gxemul-0.6.2/src/devices/dev_i80321.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_i80321.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,482 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Intel i80321 (ARM) core functionality
- *
- *	o)  Interrupt controller
- *	o)  Timer
- *	o)  PCI controller
- *	o)  Memory controller
- *	o)  I2C
- *
- *  TODO:
- *	o)  More or less everything.
- *	o)  This is hardcoded for little endian emulation.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "timer.h"
-
-#include "thirdparty/i80321reg.h"
-#include "thirdparty/iopi2creg.h"
-
-
-#define	TICK_SHIFT		15
-#define	DEV_I80321_LENGTH	VERDE_PMMR_SIZE
-
-struct i80321_data {
-	/*  Interrupt Controller  */
-	struct interrupt irq;
-	uint32_t	*status;	/*  Note: these point to i80321_isrc  */
-	uint32_t	*enable;	/*  and i80321_inten in the CPU!  */
-
-	/*  Timer:  */
-	struct timer	*timer;
-	double		hz;
-	int		pending_tmr0_interrupts;
-
-	/*  PCI Controller:  */
-	uint32_t	pci_addr;
-	struct pci_data *pci_bus;
-
-	/*  Memory Controller:  */
-	uint32_t	mcu_reg[0x100 / sizeof(uint32_t)];
-
-	/*  I2C Controller:  */
-	uint32_t	i2c_reg[VERDE_I2C_SIZE / sizeof(uint32_t)];
-};
-
-
-static void i80321_assert(struct i80321_data *d, uint32_t linemask)
-{
-	*d->status |= linemask;
-	if (*d->status & *d->enable)
-		INTERRUPT_ASSERT(d->irq);
-}
-static void i80321_deassert(struct i80321_data *d, uint32_t linemask)
-{
-	*d->status &= ~linemask;
-	if (!(*d->status & *d->enable))
-		INTERRUPT_DEASSERT(d->irq);
-}
-
-
-/*  
- *  i80321_interrupt_assert():
- *  i80321_interrupt_deassert():
- *
- *  Called whenever an i80321 interrupt is asserted/deasserted.
- */
-void i80321_interrupt_assert(struct interrupt *interrupt)
-{ i80321_assert((struct i80321_data *)interrupt->extra, interrupt->line); }
-void i80321_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct i80321_data *d = (struct i80321_data *) interrupt->extra;
-
-	/*  Ack. timer interrupts:  */
-	if (interrupt->line == 1 << 9 &&
-	    d->pending_tmr0_interrupts > 0)
-		d->pending_tmr0_interrupts --;
-
-	i80321_deassert(d, interrupt->line);
-}
-
-
-/*  TMR0 ticks, called d->hz times per second.  */
-static void tmr0_tick(struct timer *t, void *extra)
-{
-	struct i80321_data *d = (struct i80321_data *) extra;
-	d->pending_tmr0_interrupts ++;
-}
-
-
-DEVICE_TICK(i80321)
-{
-	struct i80321_data *d = (struct i80321_data *) extra;
-
-	if (cpu->cd.arm.tmr0 & TMRx_ENABLE && d->pending_tmr0_interrupts > 0) {
-		i80321_assert(d, 1 << 9);
-		cpu->cd.arm.tisr |= TISR_TMR0;
-	} else {
-		i80321_deassert(d, 1 << 9);
-		cpu->cd.arm.tisr &= ~TISR_TMR0;
-	}
-}
-
-        
-DEVICE_ACCESS(i80321)
-{
-	struct i80321_data *d = (struct i80321_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	const char *n = NULL;
-	int bus, dev, func, reg;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  PCI configuration space:  */
-	if (relative_addr >= 0x100 && relative_addr < 0x140) {
-		/*  TODO  */
-		goto ret;
-	}
-
-	/*  MCU registers:  */
-	if (relative_addr >= VERDE_MCU_BASE &&
-	    relative_addr <  VERDE_MCU_BASE + VERDE_MCU_SIZE) {
-		int regnr = (relative_addr - VERDE_MCU_BASE) / sizeof(uint32_t);
-		if (writeflag == MEM_WRITE)
-			d->mcu_reg[regnr] = idata;
-		else
-			odata = d->mcu_reg[regnr];
-	}
-
-	/*  I2C registers:  */
-	if (relative_addr >= VERDE_I2C_BASE &&
-	    relative_addr <  VERDE_I2C_BASE + VERDE_I2C_SIZE) {
-		int regnr = (relative_addr - VERDE_I2C_BASE) / sizeof(uint32_t);
-		if (writeflag == MEM_WRITE)
-			d->i2c_reg[regnr] = idata;
-		else
-			odata = d->i2c_reg[regnr];
-	}
-
-
-	switch (relative_addr) {
-
-	/*  Address Translation Unit:  */
-	case VERDE_ATU_BASE + ATU_IALR0:
-	case VERDE_ATU_BASE + ATU_IATVR0:
-	case VERDE_ATU_BASE + ATU_IALR1:
-	case VERDE_ATU_BASE + ATU_IALR2:
-	case VERDE_ATU_BASE + ATU_IATVR2:
-	case VERDE_ATU_BASE + ATU_OIOWTVR:
-	case VERDE_ATU_BASE + ATU_OMWTVR0:
-	case VERDE_ATU_BASE + ATU_OUMWTVR0:
-	case VERDE_ATU_BASE + ATU_OMWTVR1:
-	case VERDE_ATU_BASE + ATU_OUMWTVR1:
-		/*  Ignoring these for now. TODO  */
-		break;
-	case VERDE_ATU_BASE + ATU_ATUCR:
-		/*  ATU configuration register; ignored for now. TODO  */
-		break;
-	case VERDE_ATU_BASE + ATU_PCSR:
-		/*  TODO: Temporary hack to allow NetBSD/evbarm to
-		    reboot itself.  Should be rewritten as soon as possible!  */
-		if (writeflag == MEM_WRITE && idata == 0x30) {
-			int j;
-			for (j=0; j<cpu->machine->ncpus; j++)
-				cpu->machine->cpus[j]->running = 0;
-			cpu->machine->exit_without_entering_debugger = 1;
-		}
-		break;
-	case VERDE_ATU_BASE + ATU_ATUIMR:
-	case VERDE_ATU_BASE + ATU_IABAR3:
-	case VERDE_ATU_BASE + ATU_IAUBAR3:
-	case VERDE_ATU_BASE + ATU_IALR3:
-	case VERDE_ATU_BASE + ATU_IATVR3:
-		/*  Ignoring these for now. TODO  */
-		break;
-	case VERDE_ATU_BASE + ATU_OCCAR:
-		/*  PCI address  */
-		if (writeflag == MEM_WRITE) {
-			d->pci_addr = idata;
-			bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
-			bus = 0;	/*  NOTE  */
-			bus_pci_setaddr(cpu, d->pci_bus, bus, dev, func, reg);
-		} else {
-			odata = d->pci_addr;
-		}
-		break;
-	case VERDE_ATU_BASE + ATU_OCCDR:
-	case VERDE_ATU_BASE + ATU_OCCDR + 1:
-	case VERDE_ATU_BASE + ATU_OCCDR + 2:
-	case VERDE_ATU_BASE + ATU_OCCDR + 3:
-		/*  PCI data  */
-		if (writeflag == MEM_READ) {
-			uint64_t tmp;
-			bus_pci_data_access(cpu, d->pci_bus, &tmp,
-			    sizeof(uint32_t), MEM_READ);
-			switch (relative_addr) {
-			case VERDE_ATU_BASE + ATU_OCCDR + 1:
-				odata = tmp >> 8; break;
-			case VERDE_ATU_BASE + ATU_OCCDR + 2:
-				odata = tmp >> 16; break;
-			case VERDE_ATU_BASE + ATU_OCCDR + 3:
-				odata = tmp >> 24; break;
-			default:odata = tmp;
-			}
-		} else {
-			uint64_t tmp;
-			unsigned int i;
-			int r = relative_addr - (VERDE_ATU_BASE + ATU_OCCDR);
-			bus_pci_data_access(cpu, d->pci_bus, &tmp,
-			    sizeof(uint32_t), MEM_READ);
-			for (i=0; i<len; i++) {
-				uint8_t b = idata >> (i*8);
-				tmp &= ~(0xff << ((r+i)*8));
-				tmp |= b << ((r+i)*8);
-			}
-			tmp &= 0xffffffff;  /* needed because << is 32-bit */
-			bus_pci_data_access(cpu, d->pci_bus, &tmp,
-			    sizeof(uint32_t), MEM_WRITE);
-		}
-		break;
-	case VERDE_ATU_BASE + ATU_PCIXSR:
-		odata = 0;		/*  TODO  */
-		break;
-
-	/*  Memory Controller Unit:  */
-	case VERDE_MCU_BASE + MCU_SDIR:
-		n = "MCU_SDIR (DDR SDRAM Init Register)";
-		break;
-	case VERDE_MCU_BASE + MCU_SDCR:
-		n = "MCU_SDCR (DDR SDRAM Control Register)";
-		break;
-	case VERDE_MCU_BASE + MCU_SDBR:
-		n = "MCU_SDBR (SDRAM Base Register)";
-		break;
-	case VERDE_MCU_BASE + MCU_SBR0:
-		n = "MCU_SBR0 (SDRAM Boundary 0)";
-		break;
-	case VERDE_MCU_BASE + MCU_SBR1:
-		n = "MCU_SBR1 (SDRAM Boundary 1)";
-		break;
-	case VERDE_MCU_BASE + MCU_ECCR:
-		n = "MCU_ECCR (ECC Control Register)";
-		break;
-	case VERDE_MCU_BASE + MCU_RFR:
-		n = "MCU_RFR (Refresh Frequency Register)";
-		break;
-	case VERDE_MCU_BASE + MCU_DBUDSR:
-		n = "MCU_DBUDSR (Data Bus Pull-up Drive Strength)";
-		break;
-	case VERDE_MCU_BASE + MCU_DBDDSR:
-		n = "MCU_DBDDSR (Data Bus Pull-down Drive Strength)";
-		break;
-	case VERDE_MCU_BASE + MCU_CUDSR:
-		n = "MCU_CUDSR (Clock Pull-up Drive Strength)";
-		break;
-	case VERDE_MCU_BASE + MCU_CDDSR:
-		n = "MCU_CDDSR (Clock Pull-down Drive Strength)";
-		break;
-	case VERDE_MCU_BASE + MCU_CEUDSR:
-		n = "MCU_CEUDSR (Clock En Pull-up Drive Strength)";
-		break;
-	case VERDE_MCU_BASE + MCU_CEDDSR:
-		n = "MCU_CEDDSR (Clock En Pull-down Drive Strength)";
-		break;
-	case VERDE_MCU_BASE + MCU_CSUDSR:
-		n = "MCU_CSUDSR (Chip Sel Pull-up Drive Strength)";
-		break;
-	case VERDE_MCU_BASE + MCU_CSDDSR:
-		n = "MCU_CSDDSR (Chip Sel Pull-down Drive Strength)";
-		break;
-	case VERDE_MCU_BASE + MCU_REUDSR:
-		n = "MCU_REUDSR (Rx En Pull-up Drive Strength)";
-		break;
-	case VERDE_MCU_BASE + MCU_REDDSR:
-		n = "MCU_REDDSR (Rx En Pull-down Drive Strength)";
-		break;
-
-	case VERDE_MCU_BASE + MCU_ABUDSR:
-		n = "MCU_ABUDSR (Addr Bus Pull-up Drive Strength)";
-		break;
-	case VERDE_MCU_BASE + MCU_ABDDSR:
-		n = "MCU_ABDDSR (Addr Bus Pull-down Drive Strength)";
-		break;
-
-	/*  Peripheral Bus Interface Unit  */
-	case VERDE_PBIU_BASE + PBIU_PBCR:
-		n = "PBIU_PBCR (PBIU Control Register)";
-		break;
-	case VERDE_PBIU_BASE + PBIU_PBBAR0:
-		n = "PBIU_PBBAR0 (PBIU Base Address Register 0)";
-		break;
-	case VERDE_PBIU_BASE + PBIU_PBLR0:
-		n = "PBIU_PBLR0 (PBIU Limit Register 0)";
-		break;
-	case VERDE_PBIU_BASE + PBIU_PBBAR1:
-		n = "PBIU_PBBAR1 (PBIU Base Address Register 1)";
-		break;
-	case VERDE_PBIU_BASE + PBIU_PBLR1:
-		n = "PBIU_PBLR1 (PBIU Limit Register 1)";
-		break;
-	case VERDE_PBIU_BASE + PBIU_PBBAR2:
-		n = "PBIU_PBBAR2 (PBIU Base Address Register 2)";
-		break;
-	case VERDE_PBIU_BASE + PBIU_PBLR2:
-		n = "PBIU_PBLR2 (PBIU Limit Register 2)";
-		break;
-
-	/*  TODO:  */
-	case 0x7cc:
-		n = "0x7cc_TODO";
-		break;
-
-	case VERDE_I2C_BASE0 + IIC_ICR:
-		n = "I2C 0, IIC_ICR (control register)";
-		break;
-	case VERDE_I2C_BASE0 + IIC_ISR:
-		n = "I2C 0, IIC_ISR (status register)";
-		break;
-	case VERDE_I2C_BASE0 + IIC_ISAR:
-		n = "I2C 0, IIC_ISAR (slave address register)";
-		break;
-	case VERDE_I2C_BASE0 + IIC_IDBR:
-		n = "I2C 0, IIC_IDBR (data buffer register)";
-		break;
-
-	case VERDE_I2C_BASE1 + IIC_ICR:
-		n = "I2C 1, IIC_ICR (control register)";
-		break;
-	case VERDE_I2C_BASE1 + IIC_ISR:
-		n = "I2C 1, IIC_ISR (status register)";
-		odata = IIC_ISR_ITE;	/*  IDBR Tx empty  */
-		odata |= IIC_ISR_IRF;	/*  IDBR Rx full  */
-		break;
-	case VERDE_I2C_BASE1 + IIC_ISAR:
-		n = "I2C 1, IIC_ISAR (slave address register)";
-		break;
-	case VERDE_I2C_BASE1 + IIC_IDBR:
-		n = "I2C 1, IIC_IDBR (data buffer register)";
-		odata = 7;	/*  TODO  */
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ i80321: read from 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ i80321: write to 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)idata);
-		}
-		exit(1);
-	}
-
-	if (n != NULL) {
-		if (writeflag == MEM_READ) {
-			debug("[ i80321: read from %s: 0x%llx ]\n",
-			    n, (long long)idata);
-		} else {
-			debug("[ i80321: write to %s: 0x%llx ]\n",
-			    n, (long long)idata);
-		}
-	}
-
-ret:
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(i80321)
-{
-	struct i80321_data *d;
-	uint32_t memsize = devinit->machine->physical_ram_in_mb * 1048576;
-	uint32_t base;
-	char tmpstr[300];
-	struct cpu *cpu = devinit->machine->cpus[devinit->
-	    machine->bootstrap_cpu];
-	int i;
-
-	CHECK_ALLOCATION(d = (struct i80321_data *) malloc(sizeof(struct i80321_data)));
-	memset(d, 0, sizeof(struct i80321_data));
-
-	/*  Connect to the CPU interrupt pin:  */
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	/*  Register 32 i80321 interrupts:  */
-	for (i=0; i<32; i++) {
-		struct interrupt templ;
-		char tmpstr2[300];
-		snprintf(tmpstr2, sizeof(tmpstr2), "%s.i80321.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 1 << i;
-		templ.name = tmpstr2;
-		templ.extra = d;
-		templ.interrupt_assert = i80321_interrupt_assert;
-		templ.interrupt_deassert = i80321_interrupt_deassert;
-		interrupt_handler_register(&templ);
-
-		/*
-		 *  Connect the CPU's TMR0 and TMR1 interrupts to these
-		 *  i80321 timer interrupts (nr 9 and 10):
-		 */
-		if (i == 9)
-			INTERRUPT_CONNECT(tmpstr2, cpu->cd.arm.tmr0_irq);
-		if (i == 10)
-			INTERRUPT_CONNECT(tmpstr2, cpu->cd.arm.tmr1_irq);
-	}
-
-	d->status = &cpu->cd.arm.i80321_isrc;
-	d->enable = &cpu->cd.arm.i80321_inten;
-
-	/*  TODO: base = 0 on Iyonix?  */
-	d->mcu_reg[MCU_SDBR / sizeof(uint32_t)] = base = 0xa0000000;
-	d->mcu_reg[MCU_SBR0 / sizeof(uint32_t)] = (base + memsize) >> 25;
-	d->mcu_reg[MCU_SBR1 / sizeof(uint32_t)] = (base + memsize) >> 25;
-
-	snprintf(tmpstr, sizeof(tmpstr), "%s.i80321", devinit->interrupt_path);
-
-	d->pci_bus = bus_pci_init(devinit->machine,
-	    tmpstr	/*  pciirq  */,
-	    0x90000000	/*  TODO: pci_io_offset  */,
-	    0x90010000	/*  TODO: pci_mem_offset  */,
-	    0xffff0000	/*  TODO: pci_portbase  */,
-	    0x00000000	/*  TODO: pci_membase  */,
-	    tmpstr	/*  pci_irqbase  */,
-	    0x90000000	/*  TODO: isa_portbase  */,
-	    0x90010000	/*  TODO: isa_membase  */,
-	    "TODO: isa_irqbase" /*  TODO: isa_irqbase  */);
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_I80321_LENGTH,
-	    dev_i80321_access, d, DM_DEFAULT, NULL);
-
-	/*  TODO: Don't hardcode to 100 Hz!  */
-	d->hz = 100;
-	d->timer = timer_add(d->hz, tmr0_tick, d);
-
-	machine_add_tickfunction(devinit->machine, dev_i80321_tick,
-	    d, TICK_SHIFT);
-
-	devinit->return_ptr = d->pci_bus;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/device.c gxemul-0.7.0+dfsg/src/devices/device.c
--- gxemul-0.6.2/src/devices/device.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/device.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,455 @@
+/*
+ *  Copyright (C) 2005-2013  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Device registry framework
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+static struct device_entry *device_entries = NULL;
+static int device_entries_sorted = 0;
+static int n_device_entries = 0;
+static int device_exit_on_error = 1;
+
+static struct pci_entry *pci_entries = NULL;
+static int n_pci_entries = 0;
+
+
+/*
+ *  device_entry_compar():
+ *
+ *  Internal function, used by sort_entries().
+ */
+static int device_entry_compar(const void *a, const void *b)
+{
+	const struct device_entry *pa = (const struct device_entry *) a;
+	const struct device_entry *pb = (const struct device_entry *) b;
+
+	return strcmp(pa->name, pb->name);
+}
+
+
+/*
+ *  sort_entries():
+ *
+ *  Internal function. Sorts the device_entries array in alphabetic order.
+ */
+static void sort_entries(void)
+{
+	qsort(device_entries, n_device_entries, sizeof(struct device_entry),
+	    device_entry_compar);
+
+	device_entries_sorted = 1;
+}
+
+
+/*
+ *  device_register():
+ *
+ *  Registers a device. The device is added to the end of the device_entries
+ *  array, and the sorted flag is set to zero.
+ *
+ *  NOTE: It would be a bad thing if two devices had the same name. However,
+ *        that isn't checked here, it is up to the caller!
+ *
+ *  Return value is 1 if the device was registered, 0 otherwise.
+ */
+int device_register(const char *name, int (*initf)(struct devinit *))
+{
+	CHECK_ALLOCATION(device_entries = (struct device_entry *) realloc(device_entries,
+	    sizeof(struct device_entry) * (n_device_entries + 1)));
+
+	memset(&device_entries[n_device_entries], 0,
+	    sizeof(struct device_entry));
+
+	CHECK_ALLOCATION(device_entries[n_device_entries].name = strdup(name));
+	device_entries[n_device_entries].initf = initf;
+
+	device_entries_sorted = 0;
+	n_device_entries ++;
+	return 1;
+}
+
+
+/*
+ *  pci_register():
+ *
+ *  Registers a pci device. The pci device is added to the pci_entries array.
+ *
+ *  Return value is 1 if the pci device was registered. If it was not
+ *  added, this function does not return.
+ */
+int pci_register(const char *name, void (*initf)(struct machine *, struct memory *,
+	struct pci_device *))
+{
+	CHECK_ALLOCATION(pci_entries = (struct pci_entry *) realloc(pci_entries,
+	    sizeof(struct pci_entry) * (n_pci_entries + 1)));
+
+	memset(&pci_entries[n_pci_entries], 0, sizeof(struct pci_entry));
+
+	CHECK_ALLOCATION(pci_entries[n_pci_entries].name = strdup(name));
+	pci_entries[n_pci_entries].initf = initf;
+	n_pci_entries ++;
+	return 1;
+}
+
+
+/*
+ *  pci_lookup_initf():
+ *
+ *  Find a pci device init function by scanning the pci_entries array.
+ *
+ *  Return value is a function pointer, or NULL if the name was not found.
+ */
+void (*pci_lookup_initf(const char *name))(struct machine *machine,
+	struct memory *mem, struct pci_device *pd)
+{
+	int i;
+
+	if (name == NULL) {
+		fprintf(stderr, "pci_lookup_initf(): name = NULL\n");
+		exit(1);
+	}
+
+	for (i=0; i<n_pci_entries; i++)
+		if (strcmp(name, pci_entries[i].name) == 0)
+			return pci_entries[i].initf;
+	return NULL;
+}
+
+
+/*
+ *  device_lookup():
+ *
+ *  Lookup a device name by scanning the device_entries array (as a binary
+ *  search tree).
+ *
+ *  Return value is a pointer to the device_entry on success, or a NULL pointer
+ *  if there was no such device.
+ */
+struct device_entry *device_lookup(char *name)
+{
+	int hi, lo;
+
+	if (name == NULL) {
+		fprintf(stderr, "device_lookup(): NULL ptr\n");
+		exit(1);
+	}
+
+	if (!device_entries_sorted)
+		sort_entries();
+
+	if (n_device_entries == 0)
+		return NULL;
+
+	lo = 0; hi = n_device_entries - 1;
+
+	while (lo <= hi) {
+		int r, i = (lo + hi) / 2;
+
+		/*  printf("device_lookup(): i=%i (lo=%i hi=%i)\n", i, lo, hi);
+		    printf("  name='%s', '%s'\n", name,
+		    device_entries[i].name);  */
+
+		r = strcmp(name, device_entries[i].name);
+		if (r == 0) {
+			/*  Found it!  */
+			return &device_entries[i];
+		}
+
+		/*  Try left or right half:  */
+		if (r < 0)
+			hi = i - 1;
+		if (r > 0)
+			lo = i + 1;
+	}
+
+	return NULL;
+}
+
+
+/*
+ *  device_unregister():
+ *
+ *  Unregisters a device.
+ *
+ *  Return value is 1 if a device was unregistered, 0 otherwise.
+ */
+int device_unregister(char *name)
+{
+	ssize_t i;
+	struct device_entry *p = device_lookup(name);
+
+	if (p == NULL) {
+		fatal("device_unregister(): no such device (\"%s\")\n", name);
+		return 0;
+	}
+
+	i = (size_t)p - (size_t)device_entries;
+	i /= sizeof(struct device_entry);
+
+	free(device_entries[i].name);
+	device_entries[i].name = NULL;
+
+	if (i == n_device_entries-1) {
+		/*  Do nothing if we're removing the last array element.  */
+	} else {
+		/*  Remove array element i by copying the last element
+		    to i's position:  */
+		device_entries[i] = device_entries[n_device_entries-1];
+
+		/*  The array is not sorted anymore:  */
+		device_entries_sorted = 0;
+	}
+
+	n_device_entries --;
+
+	/*  TODO: realloc?  */
+	return 1;
+}
+
+
+/*
+ *  device_add():
+ *
+ *  Add a device to a machine. For example: "kn210 addr=0x12340000" adds a
+ *  device called "kn210" at a specific address.
+ *
+ *  TODO: This function is quite ugly, and should be cleaned up.
+ */
+void *device_add(struct machine *machine, const char *name_and_params)
+{
+	struct device_entry *p;
+	struct devinit devinit;
+	const char *s2;
+	const char *s3;
+	size_t len, interrupt_path_len = strlen(machine->path) + 100;
+	int quoted;
+
+	memset(&devinit, 0, sizeof(struct devinit));
+	devinit.machine = machine;
+
+	/*  Default values:  */
+	devinit.addr_mult = 1;
+	devinit.in_use = 1;
+
+	/*  Get the device name first:  */
+	s2 = name_and_params;
+	while (s2[0] != ',' && s2[0] != ' ' && s2[0] != '\0')
+		s2 ++;
+
+	len = (size_t)s2 - (size_t)name_and_params;
+	CHECK_ALLOCATION(devinit.name = (char *) malloc(len + 1));
+	memcpy(devinit.name, name_and_params, len);
+	devinit.name[len] = '\0';
+
+	/*  Allocate space for the default interrupt name:  */
+	CHECK_ALLOCATION(devinit.interrupt_path = (char *)
+	    malloc(interrupt_path_len + 1));
+	snprintf(devinit.interrupt_path, interrupt_path_len,
+	    "%s.cpu[%i]", machine->path, machine->bootstrap_cpu);
+
+	p = device_lookup(devinit.name);
+	if (p == NULL) {
+		fatal("no such device (\"%s\")\n", devinit.name);
+		if (device_exit_on_error)
+			exit(1);
+		else
+			goto return_fail;
+	}
+
+	/*  Get params from name_and_params:  */
+	while (*s2 != '\0') {
+		/*  Skip spaces, commas, and semicolons:  */
+		while (*s2 == ' ' || *s2 == ',' || *s2 == ';')
+			s2 ++;
+
+		if (*s2 == '\0')
+			break;
+
+		/*  s2 now points to the next param. eg "addr=1234"  */
+
+		/*  Get a word (until there is a '=' sign):  */
+		s3 = s2;
+		while (*s3 != '=' && *s3 != '\0')
+			s3 ++;
+		if (s3 == s2) {
+			fatal("weird param: %s\n", s2);
+			if (device_exit_on_error)
+				exit(1);
+			else
+				goto return_fail;
+		}
+		s3 ++;
+		/*  s3 now points to the parameter value ("1234")  */
+
+		if (strncmp(s2, "addr=", 5) == 0) {
+			devinit.addr = mystrtoull(s3, NULL, 0);
+		} else if (strncmp(s2, "addr2=", 6) == 0) {
+			devinit.addr2 = mystrtoull(s3, NULL, 0);
+		} else if (strncmp(s2, "len=", 4) == 0) {
+			devinit.len = mystrtoull(s3, NULL, 0);
+		} else if (strncmp(s2, "addr_mult=", 10) == 0) {
+			devinit.addr_mult = mystrtoull(s3, NULL, 0);
+		} else if (strncmp(s2, "pci_little_endian=", 18) == 0) {
+			devinit.pci_little_endian = mystrtoull(s3, NULL, 0);
+			switch (devinit.pci_little_endian) {
+			case 0:	break;
+			case 1:	devinit.pci_little_endian =
+				    MEM_PCI_LITTLE_ENDIAN;
+				break;
+			default:fatal("Bad pci_little_endian value.\n");
+				exit(1);
+			}
+		} else if (strncmp(s2, "irq=", 4) == 0) {
+			snprintf(devinit.interrupt_path, interrupt_path_len, "%s", s3);
+			if (strchr(devinit.interrupt_path, ' ') != NULL)
+				*strchr(devinit.interrupt_path, ' ') = '\0';
+		} else if (strncmp(s2, "in_use=", 7) == 0) {
+			devinit.in_use = mystrtoull(s3, NULL, 0);
+		} else if (strncmp(s2, "name2=", 6) == 0) {
+			const char *h = s2 + 6;
+			size_t len2 = 0;
+			quoted = 0;
+			while (*h) {
+				if (*h == '\'')
+					quoted = !quoted;
+				h++, len2++;
+				if (!quoted && *h == ' ')
+					break;
+			}
+			CHECK_ALLOCATION(devinit.name2 = (char *) malloc(len2 + 1));
+			h = s2 + 6;
+			if (*h == '\'')
+				len2 -= 2, h++;
+			snprintf(devinit.name2, len2 + 1, "%s", h);
+		} else {
+			fatal("unknown param: %s\n", s2);
+			if (device_exit_on_error)
+				exit(1);
+			else
+				goto return_fail;
+		}
+
+		/*  skip to the next param:  */
+		s2 = s3;
+		quoted = 0;
+		while (*s2 != '\0' && (*s2 != ' ' || quoted) &&
+		    *s2 != ',' && *s2 != ';') {
+			if (*s2 == '\'')
+				quoted = !quoted;
+			s2 ++;
+		}
+	}
+
+
+	/*
+	 *  Call the init function for this device:
+	 */
+
+	devinit.return_ptr = NULL;
+
+	if (!p->initf(&devinit)) {
+		fatal("error adding device (\"%s\")\n", name_and_params);
+		if (device_exit_on_error)
+			exit(1);
+		else
+			goto return_fail;
+	}
+
+	free(devinit.interrupt_path);
+	free(devinit.name);
+	return devinit.return_ptr;
+
+return_fail:
+	free(devinit.name);
+	return NULL;
+}
+
+
+/*
+ *  device_dumplist():
+ *
+ *  Dump a list of all registered devices.  (If the list is not sorted when
+ *  this function is called, it is implicitly sorted.)
+ */
+void device_dumplist(void)
+{
+	int i;
+
+	if (!device_entries_sorted)
+		sort_entries();
+
+	for (i=0; i<n_device_entries; i++) {
+		debug("  %s", device_entries[i].name);
+
+		/*  TODO: flags?  */
+
+		debug("\n");
+	}
+}
+
+
+/*
+ *  device_set_exit_on_error():
+ *
+ *  This function selects the behaviour of the emulator when a device is not
+ *  found. During startup, it is nicest to abort the whole emulator session,
+ *  but if a device addition is attempted from within the debugger, then it is
+ *  nicer to just print a warning and continue.
+ */
+void device_set_exit_on_error(int exit_on_error)
+{
+	device_exit_on_error = exit_on_error;
+}
+
+
+/*
+ *  device_init():
+ *
+ *  Initialize the device registry, and call autodev_init() to automatically
+ *  add all normal devices (from the src/devices/ directory).
+ *
+ *  This function should be called before any other device_*() function is used.
+ */
+void device_init(void)
+{
+	device_entries = NULL;
+	device_entries_sorted = 0;
+	n_device_entries = 0;
+
+	autodev_init();
+}
+
diff -Nru gxemul-0.6.2/src/devices/device.cc gxemul-0.7.0+dfsg/src/devices/device.cc
--- gxemul-0.6.2/src/devices/device.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/device.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,455 +0,0 @@
-/*
- *  Copyright (C) 2005-2013  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Device registry framework
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-static struct device_entry *device_entries = NULL;
-static int device_entries_sorted = 0;
-static int n_device_entries = 0;
-static int device_exit_on_error = 1;
-
-static struct pci_entry *pci_entries = NULL;
-static int n_pci_entries = 0;
-
-
-/*
- *  device_entry_compar():
- *
- *  Internal function, used by sort_entries().
- */
-static int device_entry_compar(const void *a, const void *b)
-{
-	const struct device_entry *pa = (const struct device_entry *) a;
-	const struct device_entry *pb = (const struct device_entry *) b;
-
-	return strcmp(pa->name, pb->name);
-}
-
-
-/*
- *  sort_entries():
- *
- *  Internal function. Sorts the device_entries array in alphabetic order.
- */
-static void sort_entries(void)
-{
-	qsort(device_entries, n_device_entries, sizeof(struct device_entry),
-	    device_entry_compar);
-
-	device_entries_sorted = 1;
-}
-
-
-/*
- *  device_register():
- *
- *  Registers a device. The device is added to the end of the device_entries
- *  array, and the sorted flag is set to zero.
- *
- *  NOTE: It would be a bad thing if two devices had the same name. However,
- *        that isn't checked here, it is up to the caller!
- *
- *  Return value is 1 if the device was registered, 0 otherwise.
- */
-int device_register(const char *name, int (*initf)(struct devinit *))
-{
-	CHECK_ALLOCATION(device_entries = (struct device_entry *) realloc(device_entries,
-	    sizeof(struct device_entry) * (n_device_entries + 1)));
-
-	memset(&device_entries[n_device_entries], 0,
-	    sizeof(struct device_entry));
-
-	CHECK_ALLOCATION(device_entries[n_device_entries].name = strdup(name));
-	device_entries[n_device_entries].initf = initf;
-
-	device_entries_sorted = 0;
-	n_device_entries ++;
-	return 1;
-}
-
-
-/*
- *  pci_register():
- *
- *  Registers a pci device. The pci device is added to the pci_entries array.
- *
- *  Return value is 1 if the pci device was registered. If it was not
- *  added, this function does not return.
- */
-int pci_register(const char *name, void (*initf)(struct machine *, struct memory *,
-	struct pci_device *))
-{
-	CHECK_ALLOCATION(pci_entries = (struct pci_entry *) realloc(pci_entries,
-	    sizeof(struct pci_entry) * (n_pci_entries + 1)));
-
-	memset(&pci_entries[n_pci_entries], 0, sizeof(struct pci_entry));
-
-	CHECK_ALLOCATION(pci_entries[n_pci_entries].name = strdup(name));
-	pci_entries[n_pci_entries].initf = initf;
-	n_pci_entries ++;
-	return 1;
-}
-
-
-/*
- *  pci_lookup_initf():
- *
- *  Find a pci device init function by scanning the pci_entries array.
- *
- *  Return value is a function pointer, or NULL if the name was not found.
- */
-void (*pci_lookup_initf(const char *name))(struct machine *machine,
-	struct memory *mem, struct pci_device *pd)
-{
-	int i;
-
-	if (name == NULL) {
-		fprintf(stderr, "pci_lookup_initf(): name = NULL\n");
-		exit(1);
-	}
-
-	for (i=0; i<n_pci_entries; i++)
-		if (strcmp(name, pci_entries[i].name) == 0)
-			return pci_entries[i].initf;
-	return NULL;
-}
-
-
-/*
- *  device_lookup():
- *
- *  Lookup a device name by scanning the device_entries array (as a binary
- *  search tree).
- *
- *  Return value is a pointer to the device_entry on success, or a NULL pointer
- *  if there was no such device.
- */
-struct device_entry *device_lookup(char *name)
-{
-	int hi, lo;
-
-	if (name == NULL) {
-		fprintf(stderr, "device_lookup(): NULL ptr\n");
-		exit(1);
-	}
-
-	if (!device_entries_sorted)
-		sort_entries();
-
-	if (n_device_entries == 0)
-		return NULL;
-
-	lo = 0; hi = n_device_entries - 1;
-
-	while (lo <= hi) {
-		int r, i = (lo + hi) / 2;
-
-		/*  printf("device_lookup(): i=%i (lo=%i hi=%i)\n", i, lo, hi);
-		    printf("  name='%s', '%s'\n", name,
-		    device_entries[i].name);  */
-
-		r = strcmp(name, device_entries[i].name);
-		if (r == 0) {
-			/*  Found it!  */
-			return &device_entries[i];
-		}
-
-		/*  Try left or right half:  */
-		if (r < 0)
-			hi = i - 1;
-		if (r > 0)
-			lo = i + 1;
-	}
-
-	return NULL;
-}
-
-
-/*
- *  device_unregister():
- *
- *  Unregisters a device.
- *
- *  Return value is 1 if a device was unregistered, 0 otherwise.
- */
-int device_unregister(char *name)
-{
-	ssize_t i;
-	struct device_entry *p = device_lookup(name);
-
-	if (p == NULL) {
-		fatal("device_unregister(): no such device (\"%s\")\n", name);
-		return 0;
-	}
-
-	i = (size_t)p - (size_t)device_entries;
-	i /= sizeof(struct device_entry);
-
-	free(device_entries[i].name);
-	device_entries[i].name = NULL;
-
-	if (i == n_device_entries-1) {
-		/*  Do nothing if we're removing the last array element.  */
-	} else {
-		/*  Remove array element i by copying the last element
-		    to i's position:  */
-		device_entries[i] = device_entries[n_device_entries-1];
-
-		/*  The array is not sorted anymore:  */
-		device_entries_sorted = 0;
-	}
-
-	n_device_entries --;
-
-	/*  TODO: realloc?  */
-	return 1;
-}
-
-
-/*
- *  device_add():
- *
- *  Add a device to a machine. For example: "kn210 addr=0x12340000" adds a
- *  device called "kn210" at a specific address.
- *
- *  TODO: This function is quite ugly, and should be cleaned up.
- */
-void *device_add(struct machine *machine, const char *name_and_params)
-{
-	struct device_entry *p;
-	struct devinit devinit;
-	const char *s2;
-	const char *s3;
-	size_t len, interrupt_path_len = strlen(machine->path) + 100;
-	int quoted;
-
-	memset(&devinit, 0, sizeof(struct devinit));
-	devinit.machine = machine;
-
-	/*  Default values:  */
-	devinit.addr_mult = 1;
-	devinit.in_use = 1;
-
-	/*  Get the device name first:  */
-	s2 = name_and_params;
-	while (s2[0] != ',' && s2[0] != ' ' && s2[0] != '\0')
-		s2 ++;
-
-	len = (size_t)s2 - (size_t)name_and_params;
-	CHECK_ALLOCATION(devinit.name = (char *) malloc(len + 1));
-	memcpy(devinit.name, name_and_params, len);
-	devinit.name[len] = '\0';
-
-	/*  Allocate space for the default interrupt name:  */
-	CHECK_ALLOCATION(devinit.interrupt_path = (char *)
-	    malloc(interrupt_path_len + 1));
-	snprintf(devinit.interrupt_path, interrupt_path_len,
-	    "%s.cpu[%i]", machine->path, machine->bootstrap_cpu);
-
-	p = device_lookup(devinit.name);
-	if (p == NULL) {
-		fatal("no such device (\"%s\")\n", devinit.name);
-		if (device_exit_on_error)
-			exit(1);
-		else
-			goto return_fail;
-	}
-
-	/*  Get params from name_and_params:  */
-	while (*s2 != '\0') {
-		/*  Skip spaces, commas, and semicolons:  */
-		while (*s2 == ' ' || *s2 == ',' || *s2 == ';')
-			s2 ++;
-
-		if (*s2 == '\0')
-			break;
-
-		/*  s2 now points to the next param. eg "addr=1234"  */
-
-		/*  Get a word (until there is a '=' sign):  */
-		s3 = s2;
-		while (*s3 != '=' && *s3 != '\0')
-			s3 ++;
-		if (s3 == s2) {
-			fatal("weird param: %s\n", s2);
-			if (device_exit_on_error)
-				exit(1);
-			else
-				goto return_fail;
-		}
-		s3 ++;
-		/*  s3 now points to the parameter value ("1234")  */
-
-		if (strncmp(s2, "addr=", 5) == 0) {
-			devinit.addr = mystrtoull(s3, NULL, 0);
-		} else if (strncmp(s2, "addr2=", 6) == 0) {
-			devinit.addr2 = mystrtoull(s3, NULL, 0);
-		} else if (strncmp(s2, "len=", 4) == 0) {
-			devinit.len = mystrtoull(s3, NULL, 0);
-		} else if (strncmp(s2, "addr_mult=", 10) == 0) {
-			devinit.addr_mult = mystrtoull(s3, NULL, 0);
-		} else if (strncmp(s2, "pci_little_endian=", 18) == 0) {
-			devinit.pci_little_endian = mystrtoull(s3, NULL, 0);
-			switch (devinit.pci_little_endian) {
-			case 0:	break;
-			case 1:	devinit.pci_little_endian =
-				    MEM_PCI_LITTLE_ENDIAN;
-				break;
-			default:fatal("Bad pci_little_endian value.\n");
-				exit(1);
-			}
-		} else if (strncmp(s2, "irq=", 4) == 0) {
-			snprintf(devinit.interrupt_path, interrupt_path_len, "%s", s3);
-			if (strchr(devinit.interrupt_path, ' ') != NULL)
-				*strchr(devinit.interrupt_path, ' ') = '\0';
-		} else if (strncmp(s2, "in_use=", 7) == 0) {
-			devinit.in_use = mystrtoull(s3, NULL, 0);
-		} else if (strncmp(s2, "name2=", 6) == 0) {
-			const char *h = s2 + 6;
-			size_t len2 = 0;
-			quoted = 0;
-			while (*h) {
-				if (*h == '\'')
-					quoted = !quoted;
-				h++, len2++;
-				if (!quoted && *h == ' ')
-					break;
-			}
-			CHECK_ALLOCATION(devinit.name2 = (char *) malloc(len2 + 1));
-			h = s2 + 6;
-			if (*h == '\'')
-				len2 -= 2, h++;
-			snprintf(devinit.name2, len2 + 1, "%s", h);
-		} else {
-			fatal("unknown param: %s\n", s2);
-			if (device_exit_on_error)
-				exit(1);
-			else
-				goto return_fail;
-		}
-
-		/*  skip to the next param:  */
-		s2 = s3;
-		quoted = 0;
-		while (*s2 != '\0' && (*s2 != ' ' || quoted) &&
-		    *s2 != ',' && *s2 != ';') {
-			if (*s2 == '\'')
-				quoted = !quoted;
-			s2 ++;
-		}
-	}
-
-
-	/*
-	 *  Call the init function for this device:
-	 */
-
-	devinit.return_ptr = NULL;
-
-	if (!p->initf(&devinit)) {
-		fatal("error adding device (\"%s\")\n", name_and_params);
-		if (device_exit_on_error)
-			exit(1);
-		else
-			goto return_fail;
-	}
-
-	free(devinit.interrupt_path);
-	free(devinit.name);
-	return devinit.return_ptr;
-
-return_fail:
-	free(devinit.name);
-	return NULL;
-}
-
-
-/*
- *  device_dumplist():
- *
- *  Dump a list of all registered devices.  (If the list is not sorted when
- *  this function is called, it is implicitly sorted.)
- */
-void device_dumplist(void)
-{
-	int i;
-
-	if (!device_entries_sorted)
-		sort_entries();
-
-	for (i=0; i<n_device_entries; i++) {
-		debug("  %s", device_entries[i].name);
-
-		/*  TODO: flags?  */
-
-		debug("\n");
-	}
-}
-
-
-/*
- *  device_set_exit_on_error():
- *
- *  This function selects the behaviour of the emulator when a device is not
- *  found. During startup, it is nicest to abort the whole emulator session,
- *  but if a device addition is attempted from within the debugger, then it is
- *  nicer to just print a warning and continue.
- */
-void device_set_exit_on_error(int exit_on_error)
-{
-	device_exit_on_error = exit_on_error;
-}
-
-
-/*
- *  device_init():
- *
- *  Initialize the device registry, and call autodev_init() to automatically
- *  add all normal devices (from the src/devices/ directory).
- *
- *  This function should be called before any other device_*() function is used.
- */
-void device_init(void)
-{
-	device_entries = NULL;
-	device_entries_sorted = 0;
-	n_device_entries = 0;
-
-	autodev_init();
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_igsfb.c gxemul-0.7.0+dfsg/src/devices/dev_igsfb.c
--- gxemul-0.6.2/src/devices/dev_igsfb.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_igsfb.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,425 @@
+/*
+ *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Integraphics Systems "igsfb" Framebuffer graphics card
+ *
+ *  Used in at least the NetWinder.
+ *
+ *  TODO:  This is hardcoded to 1024x768x8 right now, and only supports the
+ *         two acceleration commands used by NetBSD for scrolling the
+ *         framebuffer. The cursor is hardcoded to 12x22 pixels, as that is
+ *         what NetBSD/netwinder uses.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "../include/vga.h"
+
+#include "thirdparty/igsfbreg.h"
+
+
+struct dev_igsfb_data {
+	int		xres;
+	int		yres;
+	int		bitdepth;
+	struct vfb_data *vfb_data;
+
+	/*  VGA palette stuff:  */
+	int		palette_write_index;
+	int		palette_write_subindex;
+
+	/*
+	 *  Various graphics controller registers. See igsfbreg.h for a
+	 *  brief explanation of what these do.
+	 */
+	int		src_map_width;
+	int		src2_map_width;
+	int		dst_map_width;
+	int		src_start;
+	int		src2_start;
+	int		dst_start;
+	int		map_fmt;
+	int		ctl;
+	int		fg_mix;
+	int		bg_mix;
+	int		width;
+	int		height;
+	int		fg;
+	int		bg;
+	int		pixel_op_0;
+	int		pixel_op_1;
+	int		pixel_op_2;
+	int		pixel_op_3;
+
+	uint8_t		ext_reg_select;
+	uint8_t		ext_reg[256];
+};
+
+
+/*
+ *  recalc_sprite_position():
+ *
+ *  TODO: This is hardcoded for NetBSD/netwinder's 12x22 pixel cursor.
+ */
+static void recalc_sprite_position(struct dev_igsfb_data *d)
+{
+	int x = d->ext_reg[IGS_EXT_SPRITE_HSTART_LO] +
+		d->ext_reg[IGS_EXT_SPRITE_HSTART_HI] * 256;
+	int y = d->ext_reg[IGS_EXT_SPRITE_VSTART_LO] +
+		d->ext_reg[IGS_EXT_SPRITE_VSTART_HI] * 256;
+
+	dev_fb_setcursor(d->vfb_data, x, y, 1, 12, 22);
+}
+
+
+/*
+ *  dev_igsfb_op3_written():
+ *
+ *  This function is called after the pixel_op_3 register has been written to.
+ *  I guess this is what triggers accelerated functions to start executing.
+ *
+ *  NOTE/TODO: Only those necessary to run NetBSD/netwinder have been
+ *             implemented.
+ */
+static void dev_igsfb_op3_written(struct dev_igsfb_data *d)
+{
+	if (d->pixel_op_0 == 0x00 && d->pixel_op_1 == 0x80 &&
+	    d->pixel_op_2 == 0x00 && d->pixel_op_3 == 0x28 &&
+	    d->fg_mix == 0x03 && d->ctl == 0x00) {
+		/*  NetBSD scroll-up  */
+		framebuffer_blockcopyfill(d->vfb_data, 0, 0,0,0,
+		    d->dst_start % d->xres, d->dst_start / d->xres,
+		    d->dst_start % d->xres + d->width,
+		    d->dst_start / d->xres + d->height,
+		    d->src_start % d->xres, d->src_start / d->xres);
+		return;
+	}
+
+	if (d->pixel_op_0 == 0x00 && d->pixel_op_1 == 0x80 &&
+	    d->pixel_op_2 == 0x00 && d->pixel_op_3 == 0x08 &&
+	    d->fg_mix == 0x03 && d->ctl == 0x00) {
+		/*  NetBSD fill  */
+		/*  TODO: Color!  */
+		framebuffer_blockcopyfill(d->vfb_data, 1, 0,0,0,
+		    d->dst_start % d->xres, d->dst_start / d->xres,
+		    d->dst_start % d->xres + d->width,
+		    d->dst_start / d->xres + d->height,
+		    0, 0);
+		return;
+	}
+
+	fatal("\nUnimplemented igsfb accelerated framebuffer command:\n");
+	fatal("pixel_op_0 = 0x%02x\n", d->pixel_op_0);
+	fatal("pixel_op_1 = 0x%02x\n", d->pixel_op_1);
+	fatal("pixel_op_2 = 0x%02x\n", d->pixel_op_2);
+	fatal("pixel_op_3 = 0x%02x\n", d->pixel_op_3);
+	fatal("fg_mix     = 0x%02x\n", d->fg_mix);
+	fatal("ctl        = 0x%02x\n", d->ctl);
+	fatal("src_start  = 0x%x\n", d->src_start);
+	fatal("dst_start  = 0x%x\n", d->dst_start);
+	fatal("width      = %i\n", d->width);
+	fatal("height     = %i\n", d->height);
+	exit(1);
+}
+
+
+DEVICE_ACCESS(igsfb)
+{
+	struct dev_igsfb_data *d = (struct dev_igsfb_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (relative_addr >= 0x3c0 && relative_addr <= 0x3df) {
+		switch (relative_addr - 0x3c0) {
+		case VGA_DAC_ADDR_WRITE:		/*  0x08  */
+			if (writeflag == MEM_WRITE) {
+				d->palette_write_index = idata;
+				d->palette_write_subindex = 0;
+			} else {
+				fatal("[ igsdb: WARNING: Read from "
+				    "VGA_DAC_ADDR_WRITE? ]\n");
+				odata = d->palette_write_index;
+			}
+			break;
+		case VGA_DAC_DATA:			/*  0x09  */
+			if (writeflag == MEM_WRITE) {
+				/*  Note: 8-bit color, not 6, so it isn't
+				    exactly like normal VGA palette:  */
+				int new_ = idata & 0xff;
+				int old = d->vfb_data->rgb_palette[d->
+				    palette_write_index*3+d->
+				    palette_write_subindex];
+				d->vfb_data->rgb_palette[d->palette_write_index
+				    * 3 + d->palette_write_subindex] = new_;
+				/*  Redraw whole screen, if the
+				    palette changed:  */
+				if (new_ != old) {
+					d->vfb_data->update_x1 =
+					    d->vfb_data->update_y1 = 0;
+					d->vfb_data->update_x2 = d->xres - 1;
+					d->vfb_data->update_y2 = d->yres - 1;
+				}
+				d->palette_write_subindex ++;
+				if (d->palette_write_subindex == 3) {
+					d->palette_write_index ++;
+					d->palette_write_subindex = 0;
+				}
+			}
+			/*  Note/TODO: Reading from the palette isn't
+			    implemented here.  */
+			break;
+		case 0xe:	/*  IGSFB extended register select  */
+			if (writeflag == MEM_WRITE)
+				d->ext_reg_select = idata;
+			else
+				odata = d->ext_reg_select;
+			break;
+		case 0xf:	/*  IGSFB extended register data  */
+			if (writeflag == MEM_READ)
+				odata = d->ext_reg[d->ext_reg_select];
+			else {
+				d->ext_reg[d->ext_reg_select] = idata;
+				switch (d->ext_reg_select) {
+				/*  case IGS_EXT_SPRITE_HSTART_LO:
+				case IGS_EXT_SPRITE_HSTART_HI:
+				case IGS_EXT_SPRITE_VSTART_LO:  */
+				case IGS_EXT_SPRITE_VSTART_HI:
+					recalc_sprite_position(d);
+					break;
+				}
+			}
+			break;
+		}
+		return 1;
+	}
+
+	if (relative_addr >= IGS_COP_BASE_A &&
+	    relative_addr < IGS_COP_BASE_A + IGS_COP_SIZE) {
+		fatal("[ igsfb: BASE A not implemented yet, only BASE B ]\n");
+		exit(1);
+	}
+
+	switch (relative_addr) {
+
+	case IGS_VDO:
+		if (writeflag == MEM_WRITE) {
+			if (idata & ~(IGS_VDO_ENABLE | IGS_VDO_SETUP)) {
+				fatal("[ igsfb: Unimplemented IGS_VDO flags:"
+				    " 0x%08x ]\n", (int)idata);
+				exit(1);
+			}
+		}
+		break;
+
+	case IGS_VSE:
+		if (writeflag == MEM_WRITE) {
+			if (idata & ~(IGS_VSE_ENABLE)) {
+				fatal("[ igsfb: Unimplemented IGS_VSE flags:"
+				    " 0x%08x ]\n", (int)idata);
+				exit(1);
+			}
+		}
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_SRC_MAP_WIDTH_REG:
+		if (writeflag == MEM_WRITE)
+			d->src_map_width = idata & 0x3ff;
+		else
+			odata = d->src_map_width;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_SRC2_MAP_WIDTH_REG:
+		if (writeflag == MEM_WRITE)
+			d->src2_map_width = idata & 0x3ff;
+		else
+			odata = d->src2_map_width;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_DST_MAP_WIDTH_REG:
+		if (writeflag == MEM_WRITE)
+			d->dst_map_width = idata & 0x3ff;
+		else
+			odata = d->dst_map_width;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_MAP_FMT_REG:
+		if (writeflag == MEM_WRITE)
+			d->map_fmt = idata;
+		else
+			odata = d->map_fmt;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_CTL_REG:
+		if (writeflag == MEM_WRITE)
+			d->ctl = idata;
+		else
+			odata = d->ctl;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_FG_MIX_REG:
+		if (writeflag == MEM_WRITE)
+			d->fg_mix = idata;
+		else
+			odata = d->fg_mix;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_BG_MIX_REG:
+		if (writeflag == MEM_WRITE)
+			d->bg_mix = idata;
+		else
+			odata = d->bg_mix;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_WIDTH_REG:
+		if (writeflag == MEM_WRITE)
+			d->width = idata & 0x3ff;
+		else
+			odata = d->width;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_HEIGHT_REG:
+		if (writeflag == MEM_WRITE)
+			d->height = idata & 0x3ff;
+		else
+			odata = d->height;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_SRC_START_REG:
+		if (writeflag == MEM_WRITE)
+			d->src_start = idata & 0x3fffff;
+		else
+			odata = d->src_start;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_SRC2_START_REG:
+		if (writeflag == MEM_WRITE)
+			d->src2_start = idata & 0x3fffff;
+		else
+			odata = d->src2_start;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_DST_START_REG:
+		if (writeflag == MEM_WRITE)
+			d->dst_start = idata & 0x3fffff;
+		else
+			odata = d->dst_start;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_FG_REG:
+		if (writeflag == MEM_WRITE)
+			d->fg = idata;
+		else
+			odata = d->fg;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_BG_REG:
+		if (writeflag == MEM_WRITE)
+			d->bg = idata;
+		else
+			odata = d->bg;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_PIXEL_OP_0_REG:
+		if (writeflag == MEM_WRITE)
+			d->pixel_op_0 = idata;
+		else
+			odata = d->pixel_op_0;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_PIXEL_OP_1_REG:
+		if (writeflag == MEM_WRITE)
+			d->pixel_op_1 = idata;
+		else
+			odata = d->pixel_op_1;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_PIXEL_OP_2_REG:
+		if (writeflag == MEM_WRITE)
+			d->pixel_op_2 = idata;
+		else
+			odata = d->pixel_op_2;
+		break;
+
+	case IGS_COP_BASE_B + IGS_COP_PIXEL_OP_3_REG:
+		if (writeflag == MEM_WRITE) {
+			d->pixel_op_3 = idata;
+			dev_igsfb_op3_written(d);
+		} else {
+			odata = d->pixel_op_3;
+		}
+		break;
+
+	default:if (writeflag == MEM_WRITE) {
+			fatal("[ igsfb: unimplemented write to address 0x%x"
+			    " data=0x%02x ]\n", (int)relative_addr, (int)idata);
+		} else {
+			fatal("[ igsfb: unimplemented read from address 0x%x "
+			    "]\n", (int)relative_addr);
+		}
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(igsfb)
+{
+	struct dev_igsfb_data *d;
+
+	CHECK_ALLOCATION(d = (struct dev_igsfb_data *) malloc(sizeof(struct dev_igsfb_data)));
+	memset(d, 0, sizeof(struct dev_igsfb_data));
+
+	d->xres = 1024;
+	d->yres = 768;
+	d->bitdepth = 8;
+	d->vfb_data = dev_fb_init(devinit->machine, devinit->machine->memory,
+	    0x400000 + devinit->addr, VFB_GENERIC, d->xres, d->yres,
+            d->xres, d->yres, d->bitdepth, "igsfb");
+
+        /*  TODO: Palette control etc at 0x3c0 + IGS_MEM_MMIO_SELECT  */
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr + IGS_MEM_MMIO_SELECT, 0x100000,
+	    dev_igsfb_access, d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_igsfb.cc gxemul-0.7.0+dfsg/src/devices/dev_igsfb.cc
--- gxemul-0.6.2/src/devices/dev_igsfb.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_igsfb.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,425 +0,0 @@
-/*
- *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Integraphics Systems "igsfb" Framebuffer graphics card
- *
- *  Used in at least the NetWinder.
- *
- *  TODO:  This is hardcoded to 1024x768x8 right now, and only supports the
- *         two acceleration commands used by NetBSD for scrolling the
- *         framebuffer. The cursor is hardcoded to 12x22 pixels, as that is
- *         what NetBSD/netwinder uses.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "../include/vga.h"
-
-#include "thirdparty/igsfbreg.h"
-
-
-struct dev_igsfb_data {
-	int		xres;
-	int		yres;
-	int		bitdepth;
-	struct vfb_data *vfb_data;
-
-	/*  VGA palette stuff:  */
-	int		palette_write_index;
-	int		palette_write_subindex;
-
-	/*
-	 *  Various graphics controller registers. See igsfbreg.h for a
-	 *  brief explanation of what these do.
-	 */
-	int		src_map_width;
-	int		src2_map_width;
-	int		dst_map_width;
-	int		src_start;
-	int		src2_start;
-	int		dst_start;
-	int		map_fmt;
-	int		ctl;
-	int		fg_mix;
-	int		bg_mix;
-	int		width;
-	int		height;
-	int		fg;
-	int		bg;
-	int		pixel_op_0;
-	int		pixel_op_1;
-	int		pixel_op_2;
-	int		pixel_op_3;
-
-	uint8_t		ext_reg_select;
-	uint8_t		ext_reg[256];
-};
-
-
-/*
- *  recalc_sprite_position():
- *
- *  TODO: This is hardcoded for NetBSD/netwinder's 12x22 pixel cursor.
- */
-static void recalc_sprite_position(struct dev_igsfb_data *d)
-{
-	int x = d->ext_reg[IGS_EXT_SPRITE_HSTART_LO] +
-		d->ext_reg[IGS_EXT_SPRITE_HSTART_HI] * 256;
-	int y = d->ext_reg[IGS_EXT_SPRITE_VSTART_LO] +
-		d->ext_reg[IGS_EXT_SPRITE_VSTART_HI] * 256;
-
-	dev_fb_setcursor(d->vfb_data, x, y, 1, 12, 22);
-}
-
-
-/*
- *  dev_igsfb_op3_written():
- *
- *  This function is called after the pixel_op_3 register has been written to.
- *  I guess this is what triggers accelerated functions to start executing.
- *
- *  NOTE/TODO: Only those necessary to run NetBSD/netwinder have been
- *             implemented.
- */
-static void dev_igsfb_op3_written(struct dev_igsfb_data *d)
-{
-	if (d->pixel_op_0 == 0x00 && d->pixel_op_1 == 0x80 &&
-	    d->pixel_op_2 == 0x00 && d->pixel_op_3 == 0x28 &&
-	    d->fg_mix == 0x03 && d->ctl == 0x00) {
-		/*  NetBSD scroll-up  */
-		framebuffer_blockcopyfill(d->vfb_data, 0, 0,0,0,
-		    d->dst_start % d->xres, d->dst_start / d->xres,
-		    d->dst_start % d->xres + d->width,
-		    d->dst_start / d->xres + d->height,
-		    d->src_start % d->xres, d->src_start / d->xres);
-		return;
-	}
-
-	if (d->pixel_op_0 == 0x00 && d->pixel_op_1 == 0x80 &&
-	    d->pixel_op_2 == 0x00 && d->pixel_op_3 == 0x08 &&
-	    d->fg_mix == 0x03 && d->ctl == 0x00) {
-		/*  NetBSD fill  */
-		/*  TODO: Color!  */
-		framebuffer_blockcopyfill(d->vfb_data, 1, 0,0,0,
-		    d->dst_start % d->xres, d->dst_start / d->xres,
-		    d->dst_start % d->xres + d->width,
-		    d->dst_start / d->xres + d->height,
-		    0, 0);
-		return;
-	}
-
-	fatal("\nUnimplemented igsfb accelerated framebuffer command:\n");
-	fatal("pixel_op_0 = 0x%02x\n", d->pixel_op_0);
-	fatal("pixel_op_1 = 0x%02x\n", d->pixel_op_1);
-	fatal("pixel_op_2 = 0x%02x\n", d->pixel_op_2);
-	fatal("pixel_op_3 = 0x%02x\n", d->pixel_op_3);
-	fatal("fg_mix     = 0x%02x\n", d->fg_mix);
-	fatal("ctl        = 0x%02x\n", d->ctl);
-	fatal("src_start  = 0x%x\n", d->src_start);
-	fatal("dst_start  = 0x%x\n", d->dst_start);
-	fatal("width      = %i\n", d->width);
-	fatal("height     = %i\n", d->height);
-	exit(1);
-}
-
-
-DEVICE_ACCESS(igsfb)
-{
-	struct dev_igsfb_data *d = (struct dev_igsfb_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (relative_addr >= 0x3c0 && relative_addr <= 0x3df) {
-		switch (relative_addr - 0x3c0) {
-		case VGA_DAC_ADDR_WRITE:		/*  0x08  */
-			if (writeflag == MEM_WRITE) {
-				d->palette_write_index = idata;
-				d->palette_write_subindex = 0;
-			} else {
-				fatal("[ igsdb: WARNING: Read from "
-				    "VGA_DAC_ADDR_WRITE? ]\n");
-				odata = d->palette_write_index;
-			}
-			break;
-		case VGA_DAC_DATA:			/*  0x09  */
-			if (writeflag == MEM_WRITE) {
-				/*  Note: 8-bit color, not 6, so it isn't
-				    exactly like normal VGA palette:  */
-				int new_ = idata & 0xff;
-				int old = d->vfb_data->rgb_palette[d->
-				    palette_write_index*3+d->
-				    palette_write_subindex];
-				d->vfb_data->rgb_palette[d->palette_write_index
-				    * 3 + d->palette_write_subindex] = new_;
-				/*  Redraw whole screen, if the
-				    palette changed:  */
-				if (new_ != old) {
-					d->vfb_data->update_x1 =
-					    d->vfb_data->update_y1 = 0;
-					d->vfb_data->update_x2 = d->xres - 1;
-					d->vfb_data->update_y2 = d->yres - 1;
-				}
-				d->palette_write_subindex ++;
-				if (d->palette_write_subindex == 3) {
-					d->palette_write_index ++;
-					d->palette_write_subindex = 0;
-				}
-			}
-			/*  Note/TODO: Reading from the palette isn't
-			    implemented here.  */
-			break;
-		case 0xe:	/*  IGSFB extended register select  */
-			if (writeflag == MEM_WRITE)
-				d->ext_reg_select = idata;
-			else
-				odata = d->ext_reg_select;
-			break;
-		case 0xf:	/*  IGSFB extended register data  */
-			if (writeflag == MEM_READ)
-				odata = d->ext_reg[d->ext_reg_select];
-			else {
-				d->ext_reg[d->ext_reg_select] = idata;
-				switch (d->ext_reg_select) {
-				/*  case IGS_EXT_SPRITE_HSTART_LO:
-				case IGS_EXT_SPRITE_HSTART_HI:
-				case IGS_EXT_SPRITE_VSTART_LO:  */
-				case IGS_EXT_SPRITE_VSTART_HI:
-					recalc_sprite_position(d);
-					break;
-				}
-			}
-			break;
-		}
-		return 1;
-	}
-
-	if (relative_addr >= IGS_COP_BASE_A &&
-	    relative_addr < IGS_COP_BASE_A + IGS_COP_SIZE) {
-		fatal("[ igsfb: BASE A not implemented yet, only BASE B ]\n");
-		exit(1);
-	}
-
-	switch (relative_addr) {
-
-	case IGS_VDO:
-		if (writeflag == MEM_WRITE) {
-			if (idata & ~(IGS_VDO_ENABLE | IGS_VDO_SETUP)) {
-				fatal("[ igsfb: Unimplemented IGS_VDO flags:"
-				    " 0x%08x ]\n", (int)idata);
-				exit(1);
-			}
-		}
-		break;
-
-	case IGS_VSE:
-		if (writeflag == MEM_WRITE) {
-			if (idata & ~(IGS_VSE_ENABLE)) {
-				fatal("[ igsfb: Unimplemented IGS_VSE flags:"
-				    " 0x%08x ]\n", (int)idata);
-				exit(1);
-			}
-		}
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_SRC_MAP_WIDTH_REG:
-		if (writeflag == MEM_WRITE)
-			d->src_map_width = idata & 0x3ff;
-		else
-			odata = d->src_map_width;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_SRC2_MAP_WIDTH_REG:
-		if (writeflag == MEM_WRITE)
-			d->src2_map_width = idata & 0x3ff;
-		else
-			odata = d->src2_map_width;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_DST_MAP_WIDTH_REG:
-		if (writeflag == MEM_WRITE)
-			d->dst_map_width = idata & 0x3ff;
-		else
-			odata = d->dst_map_width;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_MAP_FMT_REG:
-		if (writeflag == MEM_WRITE)
-			d->map_fmt = idata;
-		else
-			odata = d->map_fmt;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_CTL_REG:
-		if (writeflag == MEM_WRITE)
-			d->ctl = idata;
-		else
-			odata = d->ctl;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_FG_MIX_REG:
-		if (writeflag == MEM_WRITE)
-			d->fg_mix = idata;
-		else
-			odata = d->fg_mix;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_BG_MIX_REG:
-		if (writeflag == MEM_WRITE)
-			d->bg_mix = idata;
-		else
-			odata = d->bg_mix;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_WIDTH_REG:
-		if (writeflag == MEM_WRITE)
-			d->width = idata & 0x3ff;
-		else
-			odata = d->width;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_HEIGHT_REG:
-		if (writeflag == MEM_WRITE)
-			d->height = idata & 0x3ff;
-		else
-			odata = d->height;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_SRC_START_REG:
-		if (writeflag == MEM_WRITE)
-			d->src_start = idata & 0x3fffff;
-		else
-			odata = d->src_start;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_SRC2_START_REG:
-		if (writeflag == MEM_WRITE)
-			d->src2_start = idata & 0x3fffff;
-		else
-			odata = d->src2_start;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_DST_START_REG:
-		if (writeflag == MEM_WRITE)
-			d->dst_start = idata & 0x3fffff;
-		else
-			odata = d->dst_start;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_FG_REG:
-		if (writeflag == MEM_WRITE)
-			d->fg = idata;
-		else
-			odata = d->fg;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_BG_REG:
-		if (writeflag == MEM_WRITE)
-			d->bg = idata;
-		else
-			odata = d->bg;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_PIXEL_OP_0_REG:
-		if (writeflag == MEM_WRITE)
-			d->pixel_op_0 = idata;
-		else
-			odata = d->pixel_op_0;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_PIXEL_OP_1_REG:
-		if (writeflag == MEM_WRITE)
-			d->pixel_op_1 = idata;
-		else
-			odata = d->pixel_op_1;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_PIXEL_OP_2_REG:
-		if (writeflag == MEM_WRITE)
-			d->pixel_op_2 = idata;
-		else
-			odata = d->pixel_op_2;
-		break;
-
-	case IGS_COP_BASE_B + IGS_COP_PIXEL_OP_3_REG:
-		if (writeflag == MEM_WRITE) {
-			d->pixel_op_3 = idata;
-			dev_igsfb_op3_written(d);
-		} else {
-			odata = d->pixel_op_3;
-		}
-		break;
-
-	default:if (writeflag == MEM_WRITE) {
-			fatal("[ igsfb: unimplemented write to address 0x%x"
-			    " data=0x%02x ]\n", (int)relative_addr, (int)idata);
-		} else {
-			fatal("[ igsfb: unimplemented read from address 0x%x "
-			    "]\n", (int)relative_addr);
-		}
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(igsfb)
-{
-	struct dev_igsfb_data *d;
-
-	CHECK_ALLOCATION(d = (struct dev_igsfb_data *) malloc(sizeof(struct dev_igsfb_data)));
-	memset(d, 0, sizeof(struct dev_igsfb_data));
-
-	d->xres = 1024;
-	d->yres = 768;
-	d->bitdepth = 8;
-	d->vfb_data = dev_fb_init(devinit->machine, devinit->machine->memory,
-	    0x400000 + devinit->addr, VFB_GENERIC, d->xres, d->yres,
-            d->xres, d->yres, d->bitdepth, "igsfb");
-
-        /*  TODO: Palette control etc at 0x3c0 + IGS_MEM_MMIO_SELECT  */
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr + IGS_MEM_MMIO_SELECT, 0x100000,
-	    dev_igsfb_access, d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_iq80321_7seg.c gxemul-0.7.0+dfsg/src/devices/dev_iq80321_7seg.c
--- gxemul-0.6.2/src/devices/dev_iq80321_7seg.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_iq80321_7seg.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,112 @@
+/*
+ *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: IQ80321 LED device
+ *
+ *  Should work with NetBSD's iq80321_7seg.c.
+ *
+ *  TODO: Graphical output of LED lines?
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+struct iq80321_7seg_data {
+	uint8_t		msb, lsb;
+};
+
+
+DEVICE_ACCESS(iq80321_7seg)
+{
+	struct iq80321_7seg_data *d = (struct iq80321_7seg_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case 0:	if (writeflag == MEM_READ)
+			odata = d->msb;
+		else {
+			d->msb = idata;
+			debug("[ iq80321_7seg: setting MSB to 0x%02x ]\n",
+			    (int)idata);
+		}
+		break;
+
+	case 0x10000:
+		if (writeflag == MEM_READ)
+			odata = d->lsb;
+		else {
+			d->lsb = idata;
+			debug("[ iq80321_7seg: setting LSB to 0x%02x ]\n",
+			    (int)idata);
+		}
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ iq80321_7seg: read from 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ iq80321_7seg: write to 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)idata);
+		}
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(iq80321_7seg)
+{
+	struct iq80321_7seg_data *d;
+
+	CHECK_ALLOCATION(d = (struct iq80321_7seg_data *) malloc(sizeof(struct iq80321_7seg_data)));
+	memset(d, 0, sizeof(struct iq80321_7seg_data));
+
+	/*  0xfe840000 and 0xfe850000  */
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, 0x10004, dev_iq80321_7seg_access, d,
+	    DM_DEFAULT, NULL);
+
+	return 1;
+}
+
+
diff -Nru gxemul-0.6.2/src/devices/dev_iq80321_7seg.cc gxemul-0.7.0+dfsg/src/devices/dev_iq80321_7seg.cc
--- gxemul-0.6.2/src/devices/dev_iq80321_7seg.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_iq80321_7seg.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,112 +0,0 @@
-/*
- *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: IQ80321 LED device
- *
- *  Should work with NetBSD's iq80321_7seg.c.
- *
- *  TODO: Graphical output of LED lines?
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-struct iq80321_7seg_data {
-	uint8_t		msb, lsb;
-};
-
-
-DEVICE_ACCESS(iq80321_7seg)
-{
-	struct iq80321_7seg_data *d = (struct iq80321_7seg_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case 0:	if (writeflag == MEM_READ)
-			odata = d->msb;
-		else {
-			d->msb = idata;
-			debug("[ iq80321_7seg: setting MSB to 0x%02x ]\n",
-			    (int)idata);
-		}
-		break;
-
-	case 0x10000:
-		if (writeflag == MEM_READ)
-			odata = d->lsb;
-		else {
-			d->lsb = idata;
-			debug("[ iq80321_7seg: setting LSB to 0x%02x ]\n",
-			    (int)idata);
-		}
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ iq80321_7seg: read from 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ iq80321_7seg: write to 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)idata);
-		}
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(iq80321_7seg)
-{
-	struct iq80321_7seg_data *d;
-
-	CHECK_ALLOCATION(d = (struct iq80321_7seg_data *) malloc(sizeof(struct iq80321_7seg_data)));
-	memset(d, 0, sizeof(struct iq80321_7seg_data));
-
-	/*  0xfe840000 and 0xfe850000  */
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, 0x10004, dev_iq80321_7seg_access, d,
-	    DM_DEFAULT, NULL);
-
-	return 1;
-}
-
-
diff -Nru gxemul-0.6.2/src/devices/dev_irqc.c gxemul-0.7.0+dfsg/src/devices/dev_irqc.c
--- gxemul-0.6.2/src/devices/dev_irqc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_irqc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,193 @@
+/*
+ *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Generic IRQ controller for the test machines
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "testmachine/dev_irqc.h"
+
+
+#define	N_IRQC_INTERRUPTS	32
+
+struct irqc_data {
+	struct interrupt irq;		/*  Connected to the CPU  */
+
+	int		asserted;	/*  Current CPU irq assertion  */
+
+	uint32_t	status;		/*  Interrupt Status register  */
+	uint32_t	enabled;	/*  Interrupt Enable register  */
+};
+
+
+void irqc_interrupt_assert(struct interrupt *interrupt)
+{
+	struct irqc_data *d = (struct irqc_data *) interrupt->extra;
+	d->status |= interrupt->line;
+
+	if ((d->status & d->enabled) && !d->asserted) {
+		INTERRUPT_ASSERT(d->irq);
+		d->asserted = 1;
+	}
+}
+
+
+void irqc_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct irqc_data *d = (struct irqc_data *) interrupt->extra;
+	d->status &= ~interrupt->line;
+
+	if (!(d->status & d->enabled) && d->asserted) {
+		INTERRUPT_DEASSERT(d->irq);
+		d->asserted = 0;
+	}
+}
+
+
+DEVICE_ACCESS(irqc)
+{
+	struct irqc_data *d = (struct irqc_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case DEV_IRQC_IRQ:
+		/*  Status register:  */
+		if (writeflag == MEM_READ) {
+			odata = d->status;
+		} else {
+			fatal("[ irqc: WARNING! write to DEV_IRQC_IRQ ]\n");
+		}
+		break;
+
+	case DEV_IRQC_MASK:
+		/*  Mask interrupts by clearing Enable bits:  */
+		if (writeflag == MEM_READ) {
+			fatal("[ irqc: WARNING! read from DEV_IRQC_MASK ]\n");
+		} else {
+			int old_assert = d->status & d->enabled;
+			int new_assert;
+
+			d->enabled &= ~(1 << idata);
+
+			new_assert = d->status & d->enabled;
+
+			if (!old_assert && new_assert)
+				INTERRUPT_ASSERT(d->irq);
+			else if (old_assert && !new_assert)
+				INTERRUPT_DEASSERT(d->irq);
+		}
+		break;
+
+	case DEV_IRQC_UNMASK:
+		/*  Unmask interrupts by setting Enable bits:  */
+		if (writeflag == MEM_READ) {
+			fatal("[ irqc: WARNING! read from DEV_IRQC_UNMASK ]\n");
+		} else {
+			int old_assert = d->status & d->enabled;
+			int new_assert;
+
+			d->enabled |= (1 << idata);
+
+			new_assert = d->status & d->enabled;
+
+			if (!old_assert && new_assert)
+				INTERRUPT_ASSERT(d->irq);
+			else if (old_assert && !new_assert)
+				INTERRUPT_DEASSERT(d->irq);
+		}
+		break;
+
+	default:if (writeflag == MEM_WRITE) {
+			fatal("[ irqc: unimplemented write to "
+			    "offset 0x%x: data=0x%x ]\n", (int)
+			    relative_addr, (int)idata);
+		} else {
+			fatal("[ irqc: unimplemented read from "
+			    "offset 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(irqc)
+{
+	struct irqc_data *d;
+	char n[300];
+	int i;
+
+	CHECK_ALLOCATION(d = (struct irqc_data *) malloc(sizeof(struct irqc_data)));
+	memset(d, 0, sizeof(struct irqc_data));
+
+	/*  Connect to the CPU's interrupt pin:  */
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	/*  Register the interrupts:  */
+	for (i=0; i<N_IRQC_INTERRUPTS; i++) {
+		struct interrupt templ;
+
+		snprintf(n, sizeof(n), "%s.irqc.%i",
+		    devinit->interrupt_path, i);
+
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 1 << i;		/*  Note: line contains the
+						    _mask_, not line number.  */
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = irqc_interrupt_assert;
+		templ.interrupt_deassert = irqc_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	/*  Default to all interrupts enabled:  */
+	d->enabled = 0xffffffff;
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_IRQC_LENGTH, dev_irqc_access, d,
+	    DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_irqc.cc gxemul-0.7.0+dfsg/src/devices/dev_irqc.cc
--- gxemul-0.6.2/src/devices/dev_irqc.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_irqc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,193 +0,0 @@
-/*
- *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Generic IRQ controller for the test machines
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "testmachine/dev_irqc.h"
-
-
-#define	N_IRQC_INTERRUPTS	32
-
-struct irqc_data {
-	struct interrupt irq;		/*  Connected to the CPU  */
-
-	int		asserted;	/*  Current CPU irq assertion  */
-
-	uint32_t	status;		/*  Interrupt Status register  */
-	uint32_t	enabled;	/*  Interrupt Enable register  */
-};
-
-
-void irqc_interrupt_assert(struct interrupt *interrupt)
-{
-	struct irqc_data *d = (struct irqc_data *) interrupt->extra;
-	d->status |= interrupt->line;
-
-	if ((d->status & d->enabled) && !d->asserted) {
-		INTERRUPT_ASSERT(d->irq);
-		d->asserted = 1;
-	}
-}
-
-
-void irqc_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct irqc_data *d = (struct irqc_data *) interrupt->extra;
-	d->status &= ~interrupt->line;
-
-	if (!(d->status & d->enabled) && d->asserted) {
-		INTERRUPT_DEASSERT(d->irq);
-		d->asserted = 0;
-	}
-}
-
-
-DEVICE_ACCESS(irqc)
-{
-	struct irqc_data *d = (struct irqc_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case DEV_IRQC_IRQ:
-		/*  Status register:  */
-		if (writeflag == MEM_READ) {
-			odata = d->status;
-		} else {
-			fatal("[ irqc: WARNING! write to DEV_IRQC_IRQ ]\n");
-		}
-		break;
-
-	case DEV_IRQC_MASK:
-		/*  Mask interrupts by clearing Enable bits:  */
-		if (writeflag == MEM_READ) {
-			fatal("[ irqc: WARNING! read from DEV_IRQC_MASK ]\n");
-		} else {
-			int old_assert = d->status & d->enabled;
-			int new_assert;
-
-			d->enabled &= ~(1 << idata);
-
-			new_assert = d->status & d->enabled;
-
-			if (!old_assert && new_assert)
-				INTERRUPT_ASSERT(d->irq);
-			else if (old_assert && !new_assert)
-				INTERRUPT_DEASSERT(d->irq);
-		}
-		break;
-
-	case DEV_IRQC_UNMASK:
-		/*  Unmask interrupts by setting Enable bits:  */
-		if (writeflag == MEM_READ) {
-			fatal("[ irqc: WARNING! read from DEV_IRQC_UNMASK ]\n");
-		} else {
-			int old_assert = d->status & d->enabled;
-			int new_assert;
-
-			d->enabled |= (1 << idata);
-
-			new_assert = d->status & d->enabled;
-
-			if (!old_assert && new_assert)
-				INTERRUPT_ASSERT(d->irq);
-			else if (old_assert && !new_assert)
-				INTERRUPT_DEASSERT(d->irq);
-		}
-		break;
-
-	default:if (writeflag == MEM_WRITE) {
-			fatal("[ irqc: unimplemented write to "
-			    "offset 0x%x: data=0x%x ]\n", (int)
-			    relative_addr, (int)idata);
-		} else {
-			fatal("[ irqc: unimplemented read from "
-			    "offset 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(irqc)
-{
-	struct irqc_data *d;
-	char n[300];
-	int i;
-
-	CHECK_ALLOCATION(d = (struct irqc_data *) malloc(sizeof(struct irqc_data)));
-	memset(d, 0, sizeof(struct irqc_data));
-
-	/*  Connect to the CPU's interrupt pin:  */
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	/*  Register the interrupts:  */
-	for (i=0; i<N_IRQC_INTERRUPTS; i++) {
-		struct interrupt templ;
-
-		snprintf(n, sizeof(n), "%s.irqc.%i",
-		    devinit->interrupt_path, i);
-
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 1 << i;		/*  Note: line contains the
-						    _mask_, not line number.  */
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = irqc_interrupt_assert;
-		templ.interrupt_deassert = irqc_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	/*  Default to all interrupts enabled:  */
-	d->enabled = 0xffffffff;
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_IRQC_LENGTH, dev_irqc_access, d,
-	    DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_jazz.c gxemul-0.7.0+dfsg/src/devices/dev_jazz.c
--- gxemul-0.6.2/src/devices/dev_jazz.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_jazz.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,704 @@
+/*
+ *  Copyright (C) 2004-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Microsoft Jazz-related stuff (Acer PICA-61, etc)
+ *
+ *  TODO/NOTE: This is mostly a quick hack, it doesn't really implement
+ *  much of the Jazz architecture.  Also, the a0/20 isa-like stuff is
+ *  not supposed to be here.
+ *
+ *  TODO: Figure out how the int enable mask works; it seems to be shifted
+ *  10 bits (?) according to NetBSD/arc sources.
+ *
+ *  TODO: Don't hardcode the timer to 100 Hz.
+ *
+ *  JAZZ interrupts 0..14 are connected to MIPS irq 3,
+ *  JAZZ interrupt 15 (the timer) is connected to MIPS irq 6,
+ *  and ISA interrupts 0..15 are connected to MIPS irq 4.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "timer.h"
+
+#include "thirdparty/jazz_r4030_dma.h"
+#include "thirdparty/pica.h"
+
+
+#define	DEV_JAZZ_LENGTH			0x280
+#define	DEV_JAZZ_TICKSHIFT		14
+#define	PICA_TIMER_IRQ			15
+
+struct jazz_data {
+	struct interrupt mips_irq_3;
+	struct interrupt mips_irq_4;
+	struct interrupt mips_irq_6;
+
+	struct cpu	*cpu;
+
+	/*  Jazz stuff:  */
+	uint32_t	int_enable_mask;	/*  TODO!  */
+	uint32_t	int_asserted;
+
+	/*  ISA stuff:  */
+	uint32_t	isa_int_enable_mask;
+	uint32_t	isa_int_asserted;
+
+	int		interval;
+	int		interval_start;
+
+	struct timer	*timer;
+	int		pending_timer_interrupts;
+	int		jazz_timer_value;
+	int		jazz_timer_current;
+	struct interrupt jazz_timer_irq;
+
+	uint64_t	dma_translation_table_base;
+	uint64_t	dma_translation_table_limit;
+
+	uint32_t	dma0_mode;
+	uint32_t	dma0_enable;
+	uint32_t	dma0_count;
+	uint32_t	dma0_addr;
+
+	uint32_t	dma1_mode;
+	/*  same for dma1,2,3 actually (TODO)  */
+
+	int		led;
+};
+
+
+void reassert_isa_interrupts(struct jazz_data *d)
+{
+	if (d->isa_int_asserted & d->isa_int_enable_mask)
+		INTERRUPT_ASSERT(d->mips_irq_4);
+	else
+		INTERRUPT_DEASSERT(d->mips_irq_4);
+}
+
+
+void jazz_interrupt_assert(struct interrupt *interrupt)
+{
+	struct jazz_data *d = (struct jazz_data *) interrupt->extra;
+	d->int_asserted |= (1 << interrupt->line);
+
+	if (d->int_asserted & 0x7fff)
+		INTERRUPT_ASSERT(d->mips_irq_3);
+	if (d->int_asserted & 0x8000)
+		INTERRUPT_ASSERT(d->mips_irq_6);
+}
+void jazz_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct jazz_data *d = (struct jazz_data *) interrupt->extra;
+	d->int_asserted &= ~(1 << interrupt->line);
+
+	if (!(d->int_asserted & 0x7fff))
+		INTERRUPT_DEASSERT(d->mips_irq_3);
+	if (!(d->int_asserted & 0x8000))
+		INTERRUPT_DEASSERT(d->mips_irq_6);
+}
+void jazz_isa_interrupt_assert(struct interrupt *interrupt)
+{
+	struct jazz_data *d = (struct jazz_data *) interrupt->extra;
+	d->isa_int_asserted |= (1 << interrupt->line);
+	reassert_isa_interrupts(d);
+}
+void jazz_isa_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct jazz_data *d = (struct jazz_data *) interrupt->extra;
+	d->isa_int_asserted &= ~(1 << interrupt->line);
+	reassert_isa_interrupts(d);
+}
+ 
+
+/*
+ *  dev_jazz_dma_controller():
+ */
+size_t dev_jazz_dma_controller(void *dma_controller_data,
+	unsigned char *data, size_t len, int writeflag)
+{
+	struct jazz_data *d = (struct jazz_data *) dma_controller_data;
+	struct cpu *cpu = d->cpu;
+	int i, enab_writeflag;
+	int ncpy;
+	uint32_t dma_addr;
+	unsigned char tr[sizeof(uint32_t)];
+	uint32_t phys_addr;
+
+#if 0
+	fatal("[ dev_jazz_dma_controller(): writeflag=%i, len=%i, data =",
+	    writeflag, (int)len);
+	for (i=0; i<len; i++)
+		fatal(" %02x", data[i]);
+	fatal(" mode=%08x enable=%08x count=%08x addr=%08x",
+	    d->dma0_mode, d->dma0_enable, d->dma0_count, d->dma0_addr);
+	fatal(" table=%08x",
+	    d->dma_translation_table_base);
+	fatal(" ]\n");
+#endif
+
+	if (!(d->dma0_enable & R4030_DMA_ENAB_RUN)) {
+		fatal("[ dev_jazz_dma_controller(): dma not enabled? ]\n");
+		/*  return 0;  */
+	}
+
+	/*  R4030 "write" means write to the device, writeflag as the
+	    argument to this function means write to memory.  */
+	enab_writeflag = (d->dma0_enable & R4030_DMA_ENAB_WRITE)? 0 : 1;
+	if (enab_writeflag != writeflag) {
+		fatal("[ dev_jazz_dma_controller(): wrong direction? ]\n");
+		return 0;
+	}
+
+	dma_addr = d->dma0_addr;
+	i = 0;
+	while (dma_addr < d->dma0_addr + d->dma0_count && i < (int32_t)len) {
+		/* int res = */  cpu->memory_rw(cpu, cpu->mem,
+		    d->dma_translation_table_base + (dma_addr >> 12) * 8,
+		    tr, sizeof(tr), 0, PHYSICAL | NO_EXCEPTIONS);
+
+		if (cpu->byte_order==EMUL_BIG_ENDIAN)
+			phys_addr = (tr[0] << 24) + (tr[1] << 16) +
+			    (tr[2] << 8) + tr[3];
+		else
+			phys_addr = (tr[3] << 24) + (tr[2] << 16) +
+			    (tr[1] << 8) + tr[0];
+		phys_addr &= ~0xfff;	/*  just in case  */
+		phys_addr += (dma_addr & 0xfff);
+
+		/*  fatal(" !!! dma_addr = %08x, phys_addr = %08x\n",
+		    (int)dma_addr, (int)phys_addr);  */
+
+		/*  Speed up the copying by copying 16 or 256 bytes:  */
+		ncpy = 1;
+		if ((phys_addr & 15) == 0 && i + 15 <= (int32_t)len)
+			ncpy = 15;
+		if ((phys_addr & 255) == 0 && i + 255 <= (int32_t)len)
+			ncpy = 255;
+
+		/* int res = */  cpu->memory_rw(cpu, cpu->mem, phys_addr,
+		    &data[i], ncpy, writeflag, PHYSICAL | NO_EXCEPTIONS);
+
+		dma_addr += ncpy;
+		i += ncpy;
+	}
+
+	/*  TODO: Is this correct?  */
+	d->dma0_count = 0;
+
+	return len;
+}
+
+
+static void timer_tick(struct timer *t, void *extra)
+{
+	struct jazz_data *d = (struct jazz_data *) extra;
+	d->pending_timer_interrupts ++;
+}
+
+
+DEVICE_TICK(jazz)
+{
+	struct jazz_data *d = (struct jazz_data *) extra;
+
+	/*  Used by NetBSD/arc and OpenBSD/arc:  */
+	if (d->interval_start > 0 && d->interval > 0
+	    && (d->int_enable_mask & 2) /* Hm? */ ) {
+		d->interval -= 2;
+		if (d->interval <= 0) {
+			/*  debug("[ jazz: interval timer interrupt ]\n");
+			  INTERRUPT_ASSERT(d->jazz_timer_irq);  */
+		}
+
+		/*  New timer system:  */
+		if (d->pending_timer_interrupts > 0)
+			INTERRUPT_ASSERT(d->jazz_timer_irq);
+	}
+
+	/*  Linux?  */
+	if (d->jazz_timer_value != 0) {
+		d->jazz_timer_current -= 5;
+		if (d->jazz_timer_current < 1) {
+			d->jazz_timer_current = d->jazz_timer_value;
+			/*  INTERRUPT_ASSERT(d->mips_irq_6);  */
+		}
+
+		/*  New timer system:  */
+		if (d->pending_timer_interrupts > 0)
+			INTERRUPT_ASSERT(d->mips_irq_6);
+	}
+}
+
+
+DEVICE_ACCESS(jazz)
+{
+	struct jazz_data *d = (struct jazz_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	// int regnr = relative_addr / sizeof(uint32_t);
+
+	switch (relative_addr) {
+	case R4030_SYS_CONFIG:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ jazz: unimplemented write to R4030_SYS_CONFIG"
+			    ", data=0x%08x ]\n", (int)idata);
+		} else {
+			/*  Reading the config register should give
+			    0x0104 or 0x0410. Why? TODO  */
+			odata = 0x104;
+		}
+		break;
+	case R4030_SYS_TL_BASE:
+		if (writeflag == MEM_WRITE) {
+			d->dma_translation_table_base = idata;
+		} else {
+			odata = d->dma_translation_table_base;
+		}
+		break;
+	case R4030_SYS_TL_LIMIT:
+		if (writeflag == MEM_WRITE) {
+			d->dma_translation_table_limit = idata;
+		} else {
+			odata = d->dma_translation_table_limit;
+		}
+		break;
+	case R4030_SYS_TL_IVALID:
+		/*  TODO: Does invalidation actually need to be implemented?  */
+		break;
+	case R4030_SYS_DMA0_REGS:
+		if (writeflag == MEM_WRITE) {
+			d->dma0_mode = idata;
+		} else {
+			odata = d->dma0_mode;
+		}
+		break;
+	case R4030_SYS_DMA0_REGS + 0x8:
+		if (writeflag == MEM_WRITE) {
+			d->dma0_enable = idata;
+		} else {
+			odata = d->dma0_enable;
+		}
+		break;
+	case R4030_SYS_DMA0_REGS + 0x10:
+		if (writeflag == MEM_WRITE) {
+			d->dma0_count = idata;
+		} else {
+			odata = d->dma0_count;
+		}
+		break;
+	case R4030_SYS_DMA0_REGS + 0x18:
+		if (writeflag == MEM_WRITE) {
+			d->dma0_addr = idata;
+		} else {
+			odata = d->dma0_addr;
+		}
+		break;
+	case R4030_SYS_DMA1_REGS:
+		if (writeflag == MEM_WRITE) {
+			d->dma1_mode = idata;
+		} else {
+			odata = d->dma1_mode;
+		}
+		break;
+	case R4030_SYS_ISA_VECTOR:
+		/*  ?  */
+printf("R4030_SYS_ISA_VECTOR: w=%i\n", writeflag);
+		{
+			uint32_t x = d->isa_int_asserted
+			    & d->isa_int_enable_mask;
+			odata = 0;
+			while (odata < 16) {
+				if (x & (1 << odata))
+					break;
+				odata ++;
+			}
+			if (odata >= 16)
+				odata = 0;
+		}
+		break;
+	case R4030_SYS_IT_VALUE:  /*  Interval timer reload value  */
+		if (writeflag == MEM_WRITE) {
+			d->interval_start = idata;
+			d->interval = d->interval_start;
+		} else
+			odata = d->interval_start;
+		break;
+	case R4030_SYS_IT_STAT:
+		/*  Accessing this word seems to acknowledge interrupts?  */
+		INTERRUPT_DEASSERT(d->jazz_timer_irq);
+		if (d->pending_timer_interrupts > 0)
+			d->pending_timer_interrupts --;
+
+		if (writeflag == MEM_WRITE)
+			d->interval = idata;
+		else
+			odata = d->interval;
+		d->interval = d->interval_start;
+		break;
+	case R4030_SYS_EXT_IMASK:
+		if (writeflag == MEM_WRITE) {
+			int old_assert_3 = (0x7fff &
+			    d->int_asserted & d->int_enable_mask);
+			int old_assert_6 = (0x8000 &
+			    d->int_asserted & d->int_enable_mask);
+			int new_assert_3, new_assert_6;
+
+			d->int_enable_mask = idata;
+
+			new_assert_3 =
+			    d->int_asserted & d->int_enable_mask & 0x7fff;
+			new_assert_6 =
+			    d->int_asserted & d->int_enable_mask & 0x8000;
+
+			if (old_assert_3 && !new_assert_3)
+				INTERRUPT_DEASSERT(d->mips_irq_3);
+			else if (!old_assert_3 && new_assert_3)
+				INTERRUPT_ASSERT(d->mips_irq_3);
+
+			if (old_assert_6 && !new_assert_6)
+				INTERRUPT_DEASSERT(d->mips_irq_6);
+			else if (!old_assert_6 && new_assert_6)
+				INTERRUPT_ASSERT(d->mips_irq_6);
+		} else
+			odata = d->int_enable_mask;
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ jazz: unimplemented write to address 0x%x"
+			    ", data=0x%02x ]\n", (int)relative_addr,
+			    (int)idata);
+		} else {
+			fatal("[ jazz: unimplemented read from address 0x%x"
+			    " ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(jazz_led)
+{
+	struct jazz_data *d = (struct jazz_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	// int regnr = relative_addr / sizeof(uint32_t);
+
+	switch (relative_addr) {
+	case 0:
+		if (writeflag == MEM_WRITE) {
+			d->led = idata;
+			debug("[ jazz_led: write to LED: 0x%02x ]\n",
+			    (int)idata);
+		} else {
+			odata = d->led;
+		}
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ jazz_led: unimplemented write to address 0x%x"
+			    ", data=0x%02x ]\n", (int)relative_addr,
+			    (int)idata);
+		} else {
+			fatal("[ jazz_led: unimplemented read from address 0x%x"
+			    " ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_jazz_a0_access():
+ *
+ *  ISA interrupt stuff, high 8 interrupts.
+ *
+ *  TODO: use isa8 stuff instead!
+ */
+DEVICE_ACCESS(jazz_a0)
+{
+	struct jazz_data *d = (struct jazz_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	case 0:
+		if (writeflag == MEM_WRITE) {
+			/*  TODO: only if idata == 0x20?  */
+			d->isa_int_asserted &= 0xff;
+
+			reassert_isa_interrupts(d);
+		}
+		break;
+	case 1:
+		if (writeflag == MEM_WRITE) {
+			idata = ((idata ^ 0xff) & 0xff) << 8;
+			d->isa_int_enable_mask =
+			    (d->isa_int_enable_mask & 0xff) | idata;
+			debug("[ jazz_isa_a0: setting isa_int_enable_mask "
+			    "to 0x%04x ]\n", (int)d->isa_int_enable_mask);
+
+			reassert_isa_interrupts(d);
+		} else
+			odata = d->isa_int_enable_mask;
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ jazz_isa_a0: unimplemented write to "
+			    "address 0x%x, data=0x%02x ]\n",
+			    (int)relative_addr, (int)idata);
+		} else {
+			fatal("[ jazz_isa_a0: unimplemented read from "
+			    "address 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_jazz_20_access():
+ *
+ *  ISA interrupt stuff, low 8 interrupts.
+ */
+DEVICE_ACCESS(jazz_20)
+{
+	struct jazz_data *d = (struct jazz_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	case 0:
+		if (writeflag == MEM_WRITE) {
+			/*  TODO: only if idata == 0x20?  */
+			d->isa_int_asserted &= 0xff00;
+			reassert_isa_interrupts(d);
+		}
+		break;
+	case 1:
+		if (writeflag == MEM_WRITE) {
+			idata = (idata ^ 0xff) & 0xff;
+			d->isa_int_enable_mask =
+			    (d->isa_int_enable_mask & 0xff00) | idata;
+			debug("[ jazz_isa_20: setting isa_int_enable_mask "
+			    "to 0x%04x ]\n", (int)d->isa_int_enable_mask);
+
+			reassert_isa_interrupts(d);
+		} else
+			odata = d->isa_int_enable_mask;
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ jazz_isa_20: unimplemented write to "
+			    "address 0x%x, data=0x%02x ]\n",
+			    (int)relative_addr, (int)idata);
+		} else {
+			fatal("[ jazz_isa_20: unimplemented read from "
+			    "address 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_jazz_jazzio_access():
+ *
+ *  See jazzio_intr() in NetBSD's
+ *  /usr/src/sys/arch/arc/jazz/jazzio.c for more info.
+ */
+DEVICE_ACCESS(jazz_jazzio)
+{
+	struct jazz_data *d = (struct jazz_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int i, v;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	case 0:
+		v = 0;
+		for (i=0; i<15; i++) {
+			if (d->int_asserted & (1<<i)) {
+				v = i+1;
+				break;
+			}
+		}
+		odata = v << 2;
+		break;
+	case 2:
+		/*  TODO: Should this be here?!  */
+
+		if (writeflag == MEM_WRITE)
+			d->jazz_timer_value = idata;
+		else
+			odata = d->jazz_timer_value;
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ jazzio: unimplemented write to address 0x%x"
+			    ", data=0x%02x ]\n", (int)relative_addr,
+			    (int)idata);
+		} else {
+			fatal("[ jazzio: unimplemented read from address 0x%x"
+			    " ]\n", (int)relative_addr);
+		}
+	}
+
+	/*  This is needed by Windows NT during startup:  */
+	INTERRUPT_DEASSERT(d->mips_irq_3);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(jazz)
+{
+	struct jazz_data *d;
+	char tmpstr[300];
+	int i;
+
+	CHECK_ALLOCATION(d = (struct jazz_data *) malloc(sizeof(struct jazz_data)));
+	memset(d, 0, sizeof(struct jazz_data));
+
+	d->cpu = devinit->machine->cpus[0];	/*  TODO  */
+
+	d->isa_int_enable_mask = 0xffff;
+
+	/*
+	 *  Register 16 native JAZZ irqs, and 16 ISA irqs:
+	 *
+	 *  machine[y].cpu[z].jazz.%i		(native)
+	 *  machine[y].cpu[z].jazz.isa.%i	(ISA)
+	 */
+	for (i=0; i<16; i++) {
+		struct interrupt templ;
+		char n[300];
+		snprintf(n, sizeof(n), "%s.jazz.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = jazz_interrupt_assert;
+		templ.interrupt_deassert = jazz_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+	for (i=0; i<16; i++) {
+		struct interrupt templ;
+		char n[300];
+		snprintf(n, sizeof(n), "%s.jazz.isa.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = jazz_isa_interrupt_assert;
+		templ.interrupt_deassert = jazz_isa_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	/*  Connect to MIPS CPU interrupt lines:  */
+	snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
+	INTERRUPT_CONNECT(tmpstr, d->mips_irq_3);
+	snprintf(tmpstr, sizeof(tmpstr), "%s.4", devinit->interrupt_path);
+	INTERRUPT_CONNECT(tmpstr, d->mips_irq_4);
+	snprintf(tmpstr, sizeof(tmpstr), "%s.6", devinit->interrupt_path);
+	INTERRUPT_CONNECT(tmpstr, d->mips_irq_6);
+
+	/*  Connect to JAZZ timer interrupt:  */
+	snprintf(tmpstr, sizeof(tmpstr), "%s.jazz.%i",
+	    devinit->interrupt_path, PICA_TIMER_IRQ);
+	INTERRUPT_CONNECT(tmpstr, d->jazz_timer_irq);
+
+	memory_device_register(devinit->machine->memory, "jazz",
+	    devinit->addr, DEV_JAZZ_LENGTH,
+	    dev_jazz_access, (void *)d, DM_DEFAULT, NULL);
+
+	/*  At least for Magnum and Pica-61:  */
+	memory_device_register(devinit->machine->memory, "jazz_led",
+	    0x08000f000ULL, 4, dev_jazz_led_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	memory_device_register(devinit->machine->memory, "jazz_isa_20",
+	    0x90000020ULL, 2, dev_jazz_20_access, (void *)d, DM_DEFAULT, NULL);
+
+	memory_device_register(devinit->machine->memory, "jazz_isa_a0",
+	    0x900000a0ULL, 2, dev_jazz_a0_access, (void *)d, DM_DEFAULT, NULL);
+
+	memory_device_register(devinit->machine->memory, "pica_jazzio",
+	    0xf0000000ULL, 4, dev_jazz_jazzio_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	/*  Add a timer, hardcoded to 100 Hz. TODO: Don't hardcode!  */
+	d->timer = timer_add(100.0, timer_tick, d);
+	machine_add_tickfunction(devinit->machine, dev_jazz_tick,
+	    d, DEV_JAZZ_TICKSHIFT);
+
+	devinit->return_ptr = d;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_jazz.cc gxemul-0.7.0+dfsg/src/devices/dev_jazz.cc
--- gxemul-0.6.2/src/devices/dev_jazz.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_jazz.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,707 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Microsoft Jazz-related stuff (Acer PICA-61, etc)
- *
- *  TODO/NOTE: This is mostly a quick hack, it doesn't really implement
- *  much of the Jazz architecture.  Also, the a0/20 isa-like stuff is
- *  not supposed to be here.
- *
- *  TODO: Figure out how the int enable mask works; it seems to be shifted
- *  10 bits (?) according to NetBSD/arc sources.
- *
- *  TODO: Don't hardcode the timer to 100 Hz.
- *
- *  JAZZ interrupts 0..14 are connected to MIPS irq 3,
- *  JAZZ interrupt 15 (the timer) is connected to MIPS irq 6,
- *  and ISA interrupts 0..15 are connected to MIPS irq 4.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "timer.h"
-
-#include "thirdparty/jazz_r4030_dma.h"
-#include "thirdparty/pica.h"
-
-
-#define	DEV_JAZZ_LENGTH			0x280
-#define	DEV_JAZZ_TICKSHIFT		14
-#define	PICA_TIMER_IRQ			15
-
-struct jazz_data {
-	struct interrupt mips_irq_3;
-	struct interrupt mips_irq_4;
-	struct interrupt mips_irq_6;
-
-	struct cpu	*cpu;
-
-	/*  Jazz stuff:  */
-	uint32_t	int_enable_mask;	/*  TODO!  */
-	uint32_t	int_asserted;
-
-	/*  ISA stuff:  */
-	uint32_t	isa_int_enable_mask;
-	uint32_t	isa_int_asserted;
-
-	int		interval;
-	int		interval_start;
-
-	struct timer	*timer;
-	int		pending_timer_interrupts;
-	int		jazz_timer_value;
-	int		jazz_timer_current;
-	struct interrupt jazz_timer_irq;
-
-	uint64_t	dma_translation_table_base;
-	uint64_t	dma_translation_table_limit;
-
-	uint32_t	dma0_mode;
-	uint32_t	dma0_enable;
-	uint32_t	dma0_count;
-	uint32_t	dma0_addr;
-
-	uint32_t	dma1_mode;
-	/*  same for dma1,2,3 actually (TODO)  */
-
-	int		led;
-};
-
-
-void reassert_isa_interrupts(struct jazz_data *d)
-{
-	if (d->isa_int_asserted & d->isa_int_enable_mask)
-		INTERRUPT_ASSERT(d->mips_irq_4);
-	else
-		INTERRUPT_DEASSERT(d->mips_irq_4);
-}
-
-
-void jazz_interrupt_assert(struct interrupt *interrupt)
-{
-	struct jazz_data *d = (struct jazz_data *) interrupt->extra;
-	d->int_asserted |= (1 << interrupt->line);
-
-	if (d->int_asserted & 0x7fff)
-		INTERRUPT_ASSERT(d->mips_irq_3);
-	if (d->int_asserted & 0x8000)
-		INTERRUPT_ASSERT(d->mips_irq_6);
-}
-void jazz_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct jazz_data *d = (struct jazz_data *) interrupt->extra;
-	d->int_asserted &= ~(1 << interrupt->line);
-
-	if (!(d->int_asserted & 0x7fff))
-		INTERRUPT_DEASSERT(d->mips_irq_3);
-	if (!(d->int_asserted & 0x8000))
-		INTERRUPT_DEASSERT(d->mips_irq_6);
-}
-void jazz_isa_interrupt_assert(struct interrupt *interrupt)
-{
-	struct jazz_data *d = (struct jazz_data *) interrupt->extra;
-	d->isa_int_asserted |= (1 << interrupt->line);
-	reassert_isa_interrupts(d);
-}
-void jazz_isa_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct jazz_data *d = (struct jazz_data *) interrupt->extra;
-	d->isa_int_asserted &= ~(1 << interrupt->line);
-	reassert_isa_interrupts(d);
-}
- 
-
-/*
- *  dev_jazz_dma_controller():
- */
-size_t dev_jazz_dma_controller(void *dma_controller_data,
-	unsigned char *data, size_t len, int writeflag)
-{
-	struct jazz_data *d = (struct jazz_data *) dma_controller_data;
-	struct cpu *cpu = d->cpu;
-	int i, enab_writeflag;
-	int res, ncpy;
-	uint32_t dma_addr;
-	unsigned char tr[sizeof(uint32_t)];
-	uint32_t phys_addr;
-
-#if 0
-	fatal("[ dev_jazz_dma_controller(): writeflag=%i, len=%i, data =",
-	    writeflag, (int)len);
-	for (i=0; i<len; i++)
-		fatal(" %02x", data[i]);
-	fatal(" mode=%08x enable=%08x count=%08x addr=%08x",
-	    d->dma0_mode, d->dma0_enable, d->dma0_count, d->dma0_addr);
-	fatal(" table=%08x",
-	    d->dma_translation_table_base);
-	fatal(" ]\n");
-#endif
-
-	if (!(d->dma0_enable & R4030_DMA_ENAB_RUN)) {
-		fatal("[ dev_jazz_dma_controller(): dma not enabled? ]\n");
-		/*  return 0;  */
-	}
-
-	/*  R4030 "write" means write to the device, writeflag as the
-	    argument to this function means write to memory.  */
-	enab_writeflag = (d->dma0_enable & R4030_DMA_ENAB_WRITE)? 0 : 1;
-	if (enab_writeflag != writeflag) {
-		fatal("[ dev_jazz_dma_controller(): wrong direction? ]\n");
-		return 0;
-	}
-
-	dma_addr = d->dma0_addr;
-	i = 0;
-	while (dma_addr < d->dma0_addr + d->dma0_count && i < (int32_t)len) {
-
-		res = cpu->memory_rw(cpu, cpu->mem,
-		    d->dma_translation_table_base + (dma_addr >> 12) * 8,
-		    tr, sizeof(tr), 0, PHYSICAL | NO_EXCEPTIONS);
-
-		if (cpu->byte_order==EMUL_BIG_ENDIAN)
-			phys_addr = (tr[0] << 24) + (tr[1] << 16) +
-			    (tr[2] << 8) + tr[3];
-		else
-			phys_addr = (tr[3] << 24) + (tr[2] << 16) +
-			    (tr[1] << 8) + tr[0];
-		phys_addr &= ~0xfff;	/*  just in case  */
-		phys_addr += (dma_addr & 0xfff);
-
-		/*  fatal(" !!! dma_addr = %08x, phys_addr = %08x\n",
-		    (int)dma_addr, (int)phys_addr);  */
-
-		/*  Speed up the copying by copying 16 or 256 bytes:  */
-		ncpy = 1;
-		if ((phys_addr & 15) == 0 && i + 15 <= (int32_t)len)
-			ncpy = 15;
-		if ((phys_addr & 255) == 0 && i + 255 <= (int32_t)len)
-			ncpy = 255;
-
-		res = cpu->memory_rw(cpu, cpu->mem, phys_addr,
-		    &data[i], ncpy, writeflag, PHYSICAL | NO_EXCEPTIONS);
-
-		dma_addr += ncpy;
-		i += ncpy;
-	}
-
-	/*  TODO: Is this correct?  */
-	d->dma0_count = 0;
-
-	return len;
-}
-
-
-static void timer_tick(struct timer *t, void *extra)
-{
-	struct jazz_data *d = (struct jazz_data *) extra;
-	d->pending_timer_interrupts ++;
-}
-
-
-DEVICE_TICK(jazz)
-{
-	struct jazz_data *d = (struct jazz_data *) extra;
-
-	/*  Used by NetBSD/arc and OpenBSD/arc:  */
-	if (d->interval_start > 0 && d->interval > 0
-	    && (d->int_enable_mask & 2) /* Hm? */ ) {
-		d->interval -= 2;
-		if (d->interval <= 0) {
-			/*  debug("[ jazz: interval timer interrupt ]\n");
-			  INTERRUPT_ASSERT(d->jazz_timer_irq);  */
-		}
-
-		/*  New timer system:  */
-		if (d->pending_timer_interrupts > 0)
-			INTERRUPT_ASSERT(d->jazz_timer_irq);
-	}
-
-	/*  Linux?  */
-	if (d->jazz_timer_value != 0) {
-		d->jazz_timer_current -= 5;
-		if (d->jazz_timer_current < 1) {
-			d->jazz_timer_current = d->jazz_timer_value;
-			/*  INTERRUPT_ASSERT(d->mips_irq_6);  */
-		}
-
-		/*  New timer system:  */
-		if (d->pending_timer_interrupts > 0)
-			INTERRUPT_ASSERT(d->mips_irq_6);
-	}
-}
-
-
-DEVICE_ACCESS(jazz)
-{
-	struct jazz_data *d = (struct jazz_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	regnr = relative_addr / sizeof(uint32_t);
-
-	switch (relative_addr) {
-	case R4030_SYS_CONFIG:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ jazz: unimplemented write to R4030_SYS_CONFIG"
-			    ", data=0x%08x ]\n", (int)idata);
-		} else {
-			/*  Reading the config register should give
-			    0x0104 or 0x0410. Why? TODO  */
-			odata = 0x104;
-		}
-		break;
-	case R4030_SYS_TL_BASE:
-		if (writeflag == MEM_WRITE) {
-			d->dma_translation_table_base = idata;
-		} else {
-			odata = d->dma_translation_table_base;
-		}
-		break;
-	case R4030_SYS_TL_LIMIT:
-		if (writeflag == MEM_WRITE) {
-			d->dma_translation_table_limit = idata;
-		} else {
-			odata = d->dma_translation_table_limit;
-		}
-		break;
-	case R4030_SYS_TL_IVALID:
-		/*  TODO: Does invalidation actually need to be implemented?  */
-		break;
-	case R4030_SYS_DMA0_REGS:
-		if (writeflag == MEM_WRITE) {
-			d->dma0_mode = idata;
-		} else {
-			odata = d->dma0_mode;
-		}
-		break;
-	case R4030_SYS_DMA0_REGS + 0x8:
-		if (writeflag == MEM_WRITE) {
-			d->dma0_enable = idata;
-		} else {
-			odata = d->dma0_enable;
-		}
-		break;
-	case R4030_SYS_DMA0_REGS + 0x10:
-		if (writeflag == MEM_WRITE) {
-			d->dma0_count = idata;
-		} else {
-			odata = d->dma0_count;
-		}
-		break;
-	case R4030_SYS_DMA0_REGS + 0x18:
-		if (writeflag == MEM_WRITE) {
-			d->dma0_addr = idata;
-		} else {
-			odata = d->dma0_addr;
-		}
-		break;
-	case R4030_SYS_DMA1_REGS:
-		if (writeflag == MEM_WRITE) {
-			d->dma1_mode = idata;
-		} else {
-			odata = d->dma1_mode;
-		}
-		break;
-	case R4030_SYS_ISA_VECTOR:
-		/*  ?  */
-printf("R4030_SYS_ISA_VECTOR: w=%i\n", writeflag);
-		{
-			uint32_t x = d->isa_int_asserted
-			    & d->isa_int_enable_mask;
-			odata = 0;
-			while (odata < 16) {
-				if (x & (1 << odata))
-					break;
-				odata ++;
-			}
-			if (odata >= 16)
-				odata = 0;
-		}
-		break;
-	case R4030_SYS_IT_VALUE:  /*  Interval timer reload value  */
-		if (writeflag == MEM_WRITE) {
-			d->interval_start = idata;
-			d->interval = d->interval_start;
-		} else
-			odata = d->interval_start;
-		break;
-	case R4030_SYS_IT_STAT:
-		/*  Accessing this word seems to acknowledge interrupts?  */
-		INTERRUPT_DEASSERT(d->jazz_timer_irq);
-		if (d->pending_timer_interrupts > 0)
-			d->pending_timer_interrupts --;
-
-		if (writeflag == MEM_WRITE)
-			d->interval = idata;
-		else
-			odata = d->interval;
-		d->interval = d->interval_start;
-		break;
-	case R4030_SYS_EXT_IMASK:
-		if (writeflag == MEM_WRITE) {
-			int old_assert_3 = (0x7fff &
-			    d->int_asserted & d->int_enable_mask);
-			int old_assert_6 = (0x8000 &
-			    d->int_asserted & d->int_enable_mask);
-			int new_assert_3, new_assert_6;
-
-			d->int_enable_mask = idata;
-
-			new_assert_3 =
-			    d->int_asserted & d->int_enable_mask & 0x7fff;
-			new_assert_6 =
-			    d->int_asserted & d->int_enable_mask & 0x8000;
-
-			if (old_assert_3 && !new_assert_3)
-				INTERRUPT_DEASSERT(d->mips_irq_3);
-			else if (!old_assert_3 && new_assert_3)
-				INTERRUPT_ASSERT(d->mips_irq_3);
-
-			if (old_assert_6 && !new_assert_6)
-				INTERRUPT_DEASSERT(d->mips_irq_6);
-			else if (!old_assert_6 && new_assert_6)
-				INTERRUPT_ASSERT(d->mips_irq_6);
-		} else
-			odata = d->int_enable_mask;
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ jazz: unimplemented write to address 0x%x"
-			    ", data=0x%02x ]\n", (int)relative_addr,
-			    (int)idata);
-		} else {
-			fatal("[ jazz: unimplemented read from address 0x%x"
-			    " ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(jazz_led)
-{
-	struct jazz_data *d = (struct jazz_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	regnr = relative_addr / sizeof(uint32_t);
-
-	switch (relative_addr) {
-	case 0:
-		if (writeflag == MEM_WRITE) {
-			d->led = idata;
-			debug("[ jazz_led: write to LED: 0x%02x ]\n",
-			    (int)idata);
-		} else {
-			odata = d->led;
-		}
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ jazz_led: unimplemented write to address 0x%x"
-			    ", data=0x%02x ]\n", (int)relative_addr,
-			    (int)idata);
-		} else {
-			fatal("[ jazz_led: unimplemented read from address 0x%x"
-			    " ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_jazz_a0_access():
- *
- *  ISA interrupt stuff, high 8 interrupts.
- *
- *  TODO: use isa8 stuff instead!
- */
-DEVICE_ACCESS(jazz_a0)
-{
-	struct jazz_data *d = (struct jazz_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	case 0:
-		if (writeflag == MEM_WRITE) {
-			/*  TODO: only if idata == 0x20?  */
-			d->isa_int_asserted &= 0xff;
-
-			reassert_isa_interrupts(d);
-		}
-		break;
-	case 1:
-		if (writeflag == MEM_WRITE) {
-			idata = ((idata ^ 0xff) & 0xff) << 8;
-			d->isa_int_enable_mask =
-			    (d->isa_int_enable_mask & 0xff) | idata;
-			debug("[ jazz_isa_a0: setting isa_int_enable_mask "
-			    "to 0x%04x ]\n", (int)d->isa_int_enable_mask);
-
-			reassert_isa_interrupts(d);
-		} else
-			odata = d->isa_int_enable_mask;
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ jazz_isa_a0: unimplemented write to "
-			    "address 0x%x, data=0x%02x ]\n",
-			    (int)relative_addr, (int)idata);
-		} else {
-			fatal("[ jazz_isa_a0: unimplemented read from "
-			    "address 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_jazz_20_access():
- *
- *  ISA interrupt stuff, low 8 interrupts.
- */
-DEVICE_ACCESS(jazz_20)
-{
-	struct jazz_data *d = (struct jazz_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	case 0:
-		if (writeflag == MEM_WRITE) {
-			/*  TODO: only if idata == 0x20?  */
-			d->isa_int_asserted &= 0xff00;
-			reassert_isa_interrupts(d);
-		}
-		break;
-	case 1:
-		if (writeflag == MEM_WRITE) {
-			idata = (idata ^ 0xff) & 0xff;
-			d->isa_int_enable_mask =
-			    (d->isa_int_enable_mask & 0xff00) | idata;
-			debug("[ jazz_isa_20: setting isa_int_enable_mask "
-			    "to 0x%04x ]\n", (int)d->isa_int_enable_mask);
-
-			reassert_isa_interrupts(d);
-		} else
-			odata = d->isa_int_enable_mask;
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ jazz_isa_20: unimplemented write to "
-			    "address 0x%x, data=0x%02x ]\n",
-			    (int)relative_addr, (int)idata);
-		} else {
-			fatal("[ jazz_isa_20: unimplemented read from "
-			    "address 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_jazz_jazzio_access():
- *
- *  See jazzio_intr() in NetBSD's
- *  /usr/src/sys/arch/arc/jazz/jazzio.c for more info.
- */
-DEVICE_ACCESS(jazz_jazzio)
-{
-	struct jazz_data *d = (struct jazz_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int i, v;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	case 0:
-		v = 0;
-		for (i=0; i<15; i++) {
-			if (d->int_asserted & (1<<i)) {
-				v = i+1;
-				break;
-			}
-		}
-		odata = v << 2;
-		break;
-	case 2:
-		/*  TODO: Should this be here?!  */
-
-		if (writeflag == MEM_WRITE)
-			d->jazz_timer_value = idata;
-		else
-			odata = d->jazz_timer_value;
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ jazzio: unimplemented write to address 0x%x"
-			    ", data=0x%02x ]\n", (int)relative_addr,
-			    (int)idata);
-		} else {
-			fatal("[ jazzio: unimplemented read from address 0x%x"
-			    " ]\n", (int)relative_addr);
-		}
-	}
-
-	/*  This is needed by Windows NT during startup:  */
-	INTERRUPT_DEASSERT(d->mips_irq_3);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(jazz)
-{
-	struct jazz_data *d;
-	char tmpstr[300];
-	int i;
-
-	CHECK_ALLOCATION(d = (struct jazz_data *) malloc(sizeof(struct jazz_data)));
-	memset(d, 0, sizeof(struct jazz_data));
-
-	d->cpu = devinit->machine->cpus[0];	/*  TODO  */
-
-	d->isa_int_enable_mask = 0xffff;
-
-	/*
-	 *  Register 16 native JAZZ irqs, and 16 ISA irqs:
-	 *
-	 *  machine[y].cpu[z].jazz.%i		(native)
-	 *  machine[y].cpu[z].jazz.isa.%i	(ISA)
-	 */
-	for (i=0; i<16; i++) {
-		struct interrupt templ;
-		char n[300];
-		snprintf(n, sizeof(n), "%s.jazz.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = jazz_interrupt_assert;
-		templ.interrupt_deassert = jazz_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-	for (i=0; i<16; i++) {
-		struct interrupt templ;
-		char n[300];
-		snprintf(n, sizeof(n), "%s.jazz.isa.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = jazz_isa_interrupt_assert;
-		templ.interrupt_deassert = jazz_isa_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	/*  Connect to MIPS CPU interrupt lines:  */
-	snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
-	INTERRUPT_CONNECT(tmpstr, d->mips_irq_3);
-	snprintf(tmpstr, sizeof(tmpstr), "%s.4", devinit->interrupt_path);
-	INTERRUPT_CONNECT(tmpstr, d->mips_irq_4);
-	snprintf(tmpstr, sizeof(tmpstr), "%s.6", devinit->interrupt_path);
-	INTERRUPT_CONNECT(tmpstr, d->mips_irq_6);
-
-	/*  Connect to JAZZ timer interrupt:  */
-	snprintf(tmpstr, sizeof(tmpstr), "%s.jazz.%i",
-	    devinit->interrupt_path, PICA_TIMER_IRQ);
-	INTERRUPT_CONNECT(tmpstr, d->jazz_timer_irq);
-
-	memory_device_register(devinit->machine->memory, "jazz",
-	    devinit->addr, DEV_JAZZ_LENGTH,
-	    dev_jazz_access, (void *)d, DM_DEFAULT, NULL);
-
-	/*  At least for Magnum and Pica-61:  */
-	memory_device_register(devinit->machine->memory, "jazz_led",
-	    0x08000f000ULL, 4, dev_jazz_led_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	memory_device_register(devinit->machine->memory, "jazz_isa_20",
-	    0x90000020ULL, 2, dev_jazz_20_access, (void *)d, DM_DEFAULT, NULL);
-
-	memory_device_register(devinit->machine->memory, "jazz_isa_a0",
-	    0x900000a0ULL, 2, dev_jazz_a0_access, (void *)d, DM_DEFAULT, NULL);
-
-	memory_device_register(devinit->machine->memory, "pica_jazzio",
-	    0xf0000000ULL, 4, dev_jazz_jazzio_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	/*  Add a timer, hardcoded to 100 Hz. TODO: Don't hardcode!  */
-	d->timer = timer_add(100.0, timer_tick, d);
-	machine_add_tickfunction(devinit->machine, dev_jazz_tick,
-	    d, DEV_JAZZ_TICKSHIFT);
-
-	devinit->return_ptr = d;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_kn01.c gxemul-0.7.0+dfsg/src/devices/dev_kn01.c
--- gxemul-0.6.2/src/devices/dev_kn01.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_kn01.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,266 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: DEC KN01 ("PMAX", DECstation type 1) control register and VDAC
+ *
+ *  TODO: The CSR isn't really complete.
+ *
+ *  One of the few usable bits in the csr would be KN01_CSR_MONO.
+ *  If that bit is set, the framebuffer is treated as a monochrome
+ *  one.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "devices.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/dec_kn01.h"
+
+
+struct kn01_data {
+	int			color_fb;
+	uint32_t		csr;
+};
+
+
+struct vdac_data {
+	unsigned char	vdac_reg[DEV_VDAC_LENGTH];
+
+	int		color_fb_flag;
+
+	unsigned char	cur_read_addr;
+	unsigned char	cur_write_addr;
+
+	int		sub_color;	/*  subcolor. 0, 1, or 2  */
+	unsigned char	cur_rgb[3];
+
+	unsigned char	*rgb_palette;		/*  ptr to 256 * 3 (r,g,b)  */
+
+	unsigned char	cur_read_addr_overlay;
+	unsigned char	cur_write_addr_overlay;
+
+	int		sub_color_overlay;	/*  subcolor: 0, 1, or 2  */
+	unsigned char	cur_rgb_overlay[3];
+
+	unsigned char	rgb_palette_overlay[16 * 3];	/*  16 * 3 (r,g,b)  */
+};
+
+
+DEVICE_ACCESS(kn01)
+{
+	struct kn01_data *d = (struct kn01_data *) extra;
+	int csr;
+
+	if (writeflag == MEM_WRITE) {
+		/*  TODO  */
+		return 1;
+	}
+
+	/*  Read:  */
+	if (len != 2 || relative_addr != 0) {
+		fatal("[ kn01: trying to read something which is not "
+		    "the first half-word of the csr ]");
+	}
+
+	csr = d->csr;
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		data[0] = csr & 0xff;
+		data[1] = (csr >> 8) & 0xff;
+	} else {
+		data[1] = csr & 0xff;
+		data[0] = (csr >> 8) & 0xff;
+	}
+
+	return 1;
+}
+
+
+/*
+ *  dev_vdac_access():
+ */
+DEVICE_ACCESS(vdac)
+{
+	struct vdac_data *d = (struct vdac_data *) extra;
+
+	/*  Read from/write to the vdac:  */
+	switch (relative_addr) {
+	case DEV_VDAC_MAPWA:
+		if (writeflag == MEM_WRITE) {
+			d->cur_write_addr = data[0];
+			d->sub_color = 0;
+		} else {
+			debug("[ vdac: read from MAPWA ]\n");
+			data[0] = d->vdac_reg[relative_addr];
+		}
+		break;
+	case DEV_VDAC_MAP:
+		if (writeflag == MEM_WRITE) {
+			d->cur_rgb[d->sub_color] = data[0];
+			d->sub_color++;
+
+			if (d->sub_color > 2) {
+				/*  (Only update for color, not mono mode)  */
+				if (d->color_fb_flag)
+					memcpy(d->rgb_palette +
+					    3*d->cur_write_addr, d->cur_rgb, 3);
+
+				d->sub_color = 0;
+				d->cur_write_addr ++;
+			}
+		} else {
+			if (d->sub_color == 0) {
+				memcpy(d->cur_rgb, d->rgb_palette +
+				    3 * d->cur_read_addr, 3);
+			}
+			data[0] = d->cur_rgb[d->sub_color];
+			d->sub_color++;
+			if (d->sub_color > 2) {
+				d->sub_color = 0;
+				d->cur_read_addr ++;
+			}
+		}
+		break;
+	case DEV_VDAC_MAPRA:
+		if (writeflag == MEM_WRITE) {
+			d->cur_read_addr = data[0];
+			d->sub_color = 0;
+		} else {
+			debug("[ vdac: read from MAPRA ]\n");
+			data[0] = d->vdac_reg[relative_addr];
+		}
+		break;
+	case DEV_VDAC_OVERWA:
+		if (writeflag == MEM_WRITE) {
+			d->cur_write_addr_overlay = data[0];
+			d->sub_color_overlay = 0;
+		} else {
+			debug("[ vdac: read from OVERWA ]\n");
+			data[0] = d->vdac_reg[relative_addr];
+		}
+		break;
+	case DEV_VDAC_OVER:
+		if (writeflag == MEM_WRITE) {
+			d->cur_rgb_overlay[d->sub_color_overlay] = data[0];
+			d->sub_color_overlay++;
+
+			if (d->sub_color_overlay > 2) {
+				/*  (Only update for color, not mono mode)  */
+				if (d->color_fb_flag)
+					memcpy(d->rgb_palette_overlay +
+					    3 * d->cur_write_addr_overlay,
+					    d->cur_rgb_overlay, 3);
+
+				d->sub_color_overlay = 0;
+				d->cur_write_addr_overlay ++;
+				if (d->cur_write_addr_overlay > 15)
+					d->cur_write_addr_overlay = 0;
+			}
+		} else {
+			if (d->sub_color_overlay == 0) {
+				memcpy(d->cur_rgb_overlay,
+				    d->rgb_palette_overlay +
+				    3 * d->cur_read_addr_overlay, 3);
+			}
+			data[0] = d->cur_rgb_overlay[d->sub_color_overlay];
+			d->sub_color_overlay++;
+			if (d->sub_color_overlay > 2) {
+				d->sub_color_overlay = 0;
+				d->cur_read_addr_overlay ++;
+				if (d->cur_read_addr_overlay > 15)
+					d->cur_read_addr_overlay = 0;
+			}
+		}
+		break;
+	case DEV_VDAC_OVERRA:
+		if (writeflag == MEM_WRITE) {
+			d->cur_read_addr_overlay = data[0];
+			d->sub_color_overlay = 0;
+		} else {
+			debug("[ vdac: read from OVERRA ]\n");
+			data[0] = d->vdac_reg[relative_addr];
+		}
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ vdac: unimplemented write to address 0x%x,"
+			    " data=0x%02x ]\n", (int)relative_addr, data[0]);
+			d->vdac_reg[relative_addr] = data[0];
+		} else {
+			debug("[ vdac: unimplemented read from address 0x%x"
+			    " ]\n", (int)relative_addr);
+			data[0] = d->vdac_reg[relative_addr];
+		}
+	}
+
+	/*  Pretend it was ok:  */
+	return 1;
+}
+
+
+/*
+ *  dev_vdac_init():
+ */
+void dev_vdac_init(struct memory *mem, uint64_t baseaddr,
+	unsigned char *rgb_palette, int color_fb_flag)
+{
+	struct vdac_data *d;
+
+	CHECK_ALLOCATION(d = (struct vdac_data *) malloc(sizeof(struct vdac_data)));
+	memset(d, 0, sizeof(struct vdac_data));
+
+	d->rgb_palette   = rgb_palette;
+	d->color_fb_flag = color_fb_flag;
+
+	memory_device_register(mem, "vdac", baseaddr, DEV_VDAC_LENGTH,
+	    dev_vdac_access, (void *)d, DM_DEFAULT, NULL);
+}
+
+
+/*
+ *  dev_kn01_init():
+ */
+void dev_kn01_init(struct memory *mem, uint64_t baseaddr, int color_fb)
+{
+	struct kn01_data *d;
+
+	CHECK_ALLOCATION(d = (struct kn01_data *) malloc(sizeof(struct kn01_data)));
+	memset(d, 0, sizeof(struct kn01_data));
+
+	d->color_fb = color_fb;
+	d->csr = 0;
+	d->csr |= (color_fb? 0 : KN01_CSR_MONO);
+
+	memory_device_register(mem, "kn01", baseaddr,
+	    DEV_KN01_LENGTH, dev_kn01_access, d, DM_DEFAULT, NULL);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_kn01.cc gxemul-0.7.0+dfsg/src/devices/dev_kn01.cc
--- gxemul-0.6.2/src/devices/dev_kn01.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_kn01.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,266 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: DEC KN01 ("PMAX", DECstation type 1) control register and VDAC
- *
- *  TODO: The CSR isn't really complete.
- *
- *  One of the few usable bits in the csr would be KN01_CSR_MONO.
- *  If that bit is set, the framebuffer is treated as a monochrome
- *  one.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "devices.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/dec_kn01.h"
-
-
-struct kn01_data {
-	int			color_fb;
-	uint32_t		csr;
-};
-
-
-struct vdac_data {
-	unsigned char	vdac_reg[DEV_VDAC_LENGTH];
-
-	int		color_fb_flag;
-
-	unsigned char	cur_read_addr;
-	unsigned char	cur_write_addr;
-
-	int		sub_color;	/*  subcolor. 0, 1, or 2  */
-	unsigned char	cur_rgb[3];
-
-	unsigned char	*rgb_palette;		/*  ptr to 256 * 3 (r,g,b)  */
-
-	unsigned char	cur_read_addr_overlay;
-	unsigned char	cur_write_addr_overlay;
-
-	int		sub_color_overlay;	/*  subcolor: 0, 1, or 2  */
-	unsigned char	cur_rgb_overlay[3];
-
-	unsigned char	rgb_palette_overlay[16 * 3];	/*  16 * 3 (r,g,b)  */
-};
-
-
-DEVICE_ACCESS(kn01)
-{
-	struct kn01_data *d = (struct kn01_data *) extra;
-	int csr;
-
-	if (writeflag == MEM_WRITE) {
-		/*  TODO  */
-		return 1;
-	}
-
-	/*  Read:  */
-	if (len != 2 || relative_addr != 0) {
-		fatal("[ kn01: trying to read something which is not "
-		    "the first half-word of the csr ]");
-	}
-
-	csr = d->csr;
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		data[0] = csr & 0xff;
-		data[1] = (csr >> 8) & 0xff;
-	} else {
-		data[1] = csr & 0xff;
-		data[0] = (csr >> 8) & 0xff;
-	}
-
-	return 1;
-}
-
-
-/*
- *  dev_vdac_access():
- */
-DEVICE_ACCESS(vdac)
-{
-	struct vdac_data *d = (struct vdac_data *) extra;
-
-	/*  Read from/write to the vdac:  */
-	switch (relative_addr) {
-	case DEV_VDAC_MAPWA:
-		if (writeflag == MEM_WRITE) {
-			d->cur_write_addr = data[0];
-			d->sub_color = 0;
-		} else {
-			debug("[ vdac: read from MAPWA ]\n");
-			data[0] = d->vdac_reg[relative_addr];
-		}
-		break;
-	case DEV_VDAC_MAP:
-		if (writeflag == MEM_WRITE) {
-			d->cur_rgb[d->sub_color] = data[0];
-			d->sub_color++;
-
-			if (d->sub_color > 2) {
-				/*  (Only update for color, not mono mode)  */
-				if (d->color_fb_flag)
-					memcpy(d->rgb_palette +
-					    3*d->cur_write_addr, d->cur_rgb, 3);
-
-				d->sub_color = 0;
-				d->cur_write_addr ++;
-			}
-		} else {
-			if (d->sub_color == 0) {
-				memcpy(d->cur_rgb, d->rgb_palette +
-				    3 * d->cur_read_addr, 3);
-			}
-			data[0] = d->cur_rgb[d->sub_color];
-			d->sub_color++;
-			if (d->sub_color > 2) {
-				d->sub_color = 0;
-				d->cur_read_addr ++;
-			}
-		}
-		break;
-	case DEV_VDAC_MAPRA:
-		if (writeflag == MEM_WRITE) {
-			d->cur_read_addr = data[0];
-			d->sub_color = 0;
-		} else {
-			debug("[ vdac: read from MAPRA ]\n");
-			data[0] = d->vdac_reg[relative_addr];
-		}
-		break;
-	case DEV_VDAC_OVERWA:
-		if (writeflag == MEM_WRITE) {
-			d->cur_write_addr_overlay = data[0];
-			d->sub_color_overlay = 0;
-		} else {
-			debug("[ vdac: read from OVERWA ]\n");
-			data[0] = d->vdac_reg[relative_addr];
-		}
-		break;
-	case DEV_VDAC_OVER:
-		if (writeflag == MEM_WRITE) {
-			d->cur_rgb_overlay[d->sub_color_overlay] = data[0];
-			d->sub_color_overlay++;
-
-			if (d->sub_color_overlay > 2) {
-				/*  (Only update for color, not mono mode)  */
-				if (d->color_fb_flag)
-					memcpy(d->rgb_palette_overlay +
-					    3 * d->cur_write_addr_overlay,
-					    d->cur_rgb_overlay, 3);
-
-				d->sub_color_overlay = 0;
-				d->cur_write_addr_overlay ++;
-				if (d->cur_write_addr_overlay > 15)
-					d->cur_write_addr_overlay = 0;
-			}
-		} else {
-			if (d->sub_color_overlay == 0) {
-				memcpy(d->cur_rgb_overlay,
-				    d->rgb_palette_overlay +
-				    3 * d->cur_read_addr_overlay, 3);
-			}
-			data[0] = d->cur_rgb_overlay[d->sub_color_overlay];
-			d->sub_color_overlay++;
-			if (d->sub_color_overlay > 2) {
-				d->sub_color_overlay = 0;
-				d->cur_read_addr_overlay ++;
-				if (d->cur_read_addr_overlay > 15)
-					d->cur_read_addr_overlay = 0;
-			}
-		}
-		break;
-	case DEV_VDAC_OVERRA:
-		if (writeflag == MEM_WRITE) {
-			d->cur_read_addr_overlay = data[0];
-			d->sub_color_overlay = 0;
-		} else {
-			debug("[ vdac: read from OVERRA ]\n");
-			data[0] = d->vdac_reg[relative_addr];
-		}
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ vdac: unimplemented write to address 0x%x,"
-			    " data=0x%02x ]\n", (int)relative_addr, data[0]);
-			d->vdac_reg[relative_addr] = data[0];
-		} else {
-			debug("[ vdac: unimplemented read from address 0x%x"
-			    " ]\n", (int)relative_addr);
-			data[0] = d->vdac_reg[relative_addr];
-		}
-	}
-
-	/*  Pretend it was ok:  */
-	return 1;
-}
-
-
-/*
- *  dev_vdac_init():
- */
-void dev_vdac_init(struct memory *mem, uint64_t baseaddr,
-	unsigned char *rgb_palette, int color_fb_flag)
-{
-	struct vdac_data *d;
-
-	CHECK_ALLOCATION(d = (struct vdac_data *) malloc(sizeof(struct vdac_data)));
-	memset(d, 0, sizeof(struct vdac_data));
-
-	d->rgb_palette   = rgb_palette;
-	d->color_fb_flag = color_fb_flag;
-
-	memory_device_register(mem, "vdac", baseaddr, DEV_VDAC_LENGTH,
-	    dev_vdac_access, (void *)d, DM_DEFAULT, NULL);
-}
-
-
-/*
- *  dev_kn01_init():
- */
-void dev_kn01_init(struct memory *mem, uint64_t baseaddr, int color_fb)
-{
-	struct kn01_data *d;
-
-	CHECK_ALLOCATION(d = (struct kn01_data *) malloc(sizeof(struct kn01_data)));
-	memset(d, 0, sizeof(struct kn01_data));
-
-	d->color_fb = color_fb;
-	d->csr = 0;
-	d->csr |= (color_fb? 0 : KN01_CSR_MONO);
-
-	memory_device_register(mem, "kn01", baseaddr,
-	    DEV_KN01_LENGTH, dev_kn01_access, d, DM_DEFAULT, NULL);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_kn02ba.c gxemul-0.7.0+dfsg/src/devices/dev_kn02ba.c
--- gxemul-0.6.2/src/devices/dev_kn02ba.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_kn02ba.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,209 @@
+/*
+ *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: DEC KN02BA "3min" TurboChannel interrupt controller
+ *
+ *  Used in DECstation 5000/1xx "3MIN".  See include/dec_kmin.h for more info.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/dec_kmin.h"
+
+
+struct kn02ba_data {
+	struct dec_ioasic_data *dec_ioasic;
+
+	uint32_t	mer;	/*  Memory Error Register  */
+	uint32_t	msr;	/*  Memory Size Register  */
+
+	struct interrupt irq;
+};
+
+
+/*
+ *  kn02ba_interrupt_assert(), kn02ba_interrupt_deassert():
+ *
+ *  Called whenever a kn02ba interrupt is asserted/deasserted.
+ */
+void kn02ba_interrupt_assert(struct interrupt *interrupt)
+{
+	struct kn02ba_data *d = (struct kn02ba_data *) interrupt->extra;
+	struct dec_ioasic_data *r = (struct dec_ioasic_data *) d->dec_ioasic;
+	r->intr |= interrupt->line;
+	dec_ioasic_reassert(r);
+}
+void kn02ba_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct kn02ba_data *d = (struct kn02ba_data *) interrupt->extra;
+	struct dec_ioasic_data *r = (struct dec_ioasic_data *) d->dec_ioasic;
+	r->intr &= ~interrupt->line;
+	dec_ioasic_reassert(r);
+}
+
+
+DEVICE_ACCESS(kn02ba_mer)
+{
+	struct kn02ba_data *d = (struct kn02ba_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	case 0:
+		if (writeflag == MEM_WRITE)
+			d->mer = idata;
+		else
+			odata = d->mer;
+
+		debug("[ kn02ba_mer: %s MER, data=0x%08x (%s %s %s %s %s %s %s) ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			d->mer,
+			d->mer & KMIN_MER_PAGE_BRY ? "PAGE_BRY" : "--",
+			d->mer & KMIN_MER_TLEN ? "TLEN" : "--",
+			d->mer & KMIN_MER_PARDIS ? "PARDIS" : "--",
+			d->mer & KMIN_LASTB31 ? "LASTB31" : "--",
+			d->mer & KMIN_LASTB23 ? "LASTB23" : "--",
+			d->mer & KMIN_LASTB15 ? "LASTB15" : "--",
+			d->mer & KMIN_LASTB07 ? "LASTB07" : "--"
+			);
+
+		break;
+
+	default:
+		if (writeflag == MEM_READ) {
+			fatal("[ kn02ba_mer: read from offset 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			fatal("[ kn02ba_mer: write to offset 0x%08lx: 0x%08x ]\n",
+			    (long)relative_addr, (int)idata);
+		}
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(kn02ba_msr)
+{
+	struct kn02ba_data *d = (struct kn02ba_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	case 0:
+		if (writeflag == MEM_WRITE)
+			d->msr = idata;
+		else
+			odata = d->msr;
+
+		debug("[ kn02ba_msr: %s MSR, data=0x%08x (%s) ]\n",
+			writeflag == MEM_WRITE ? "write to" : "read from",
+			d->msr,
+			d->msr & KMIN_MSR_SIZE_16Mb ? "16Mb" : "--"
+			);
+
+		break;
+
+	default:
+		if (writeflag == MEM_READ) {
+			fatal("[ kn02ba_msr: read from offset 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			fatal("[ kn02ba_msr: write to offset 0x%08lx: 0x%08x ]\n",
+			    (long)relative_addr, (int)idata);
+		}
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(kn02ba)
+{
+	struct kn02ba_data *d;
+	int i;
+
+	CHECK_ALLOCATION(d = (struct kn02ba_data *) malloc(sizeof(struct kn02ba_data)));
+	memset(d, 0, sizeof(struct kn02ba_data));
+
+	/*  Connect the kn02ba to a specific MIPS CPU interrupt line:  */
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	/*  Register the interrupts:  */
+	for (i = 0; i < 32; i++) {
+		struct interrupt templ;
+		char tmpstr[300];
+		snprintf(tmpstr, sizeof(tmpstr), "%s.kn02ba.0x%x",
+		    devinit->interrupt_path, 1 << i);
+		// printf("registering '%s'\n", tmpstr);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 1 << i;
+		templ.name = tmpstr;
+		templ.extra = d;
+		templ.interrupt_assert = kn02ba_interrupt_assert;
+		templ.interrupt_deassert = kn02ba_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	memory_device_register(devinit->machine->memory, "kn02ba_mer",
+	    KMIN_REG_MER, sizeof(uint32_t), dev_kn02ba_mer_access, d,
+	    DM_DEFAULT, NULL);
+
+	memory_device_register(devinit->machine->memory, "kn02ba_msr",
+	    KMIN_REG_MSR, sizeof(uint32_t), dev_kn02ba_msr_access, d,
+	    DM_DEFAULT, NULL);
+
+	d->dec_ioasic = dev_dec_ioasic_init(devinit->machine->cpus[0],
+		devinit->machine->memory, KMIN_SYS_ASIC, 0, &d->irq);
+
+	d->msr = KMIN_MSR_SIZE_16Mb;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_kn02ba.cc gxemul-0.7.0+dfsg/src/devices/dev_kn02ba.cc
--- gxemul-0.6.2/src/devices/dev_kn02ba.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_kn02ba.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,209 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: DEC KN02BA "3min" TurboChannel interrupt controller
- *
- *  Used in DECstation 5000/1xx "3MIN".  See include/dec_kmin.h for more info.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/dec_kmin.h"
-
-
-struct kn02ba_data {
-	struct dec_ioasic_data *dec_ioasic;
-
-	uint32_t	mer;	/*  Memory Error Register  */
-	uint32_t	msr;	/*  Memory Size Register  */
-
-	struct interrupt irq;
-};
-
-
-/*
- *  kn02ba_interrupt_assert(), kn02ba_interrupt_deassert():
- *
- *  Called whenever a kn02ba interrupt is asserted/deasserted.
- */
-void kn02ba_interrupt_assert(struct interrupt *interrupt)
-{
-	struct kn02ba_data *d = (struct kn02ba_data *) interrupt->extra;
-	struct dec_ioasic_data *r = (struct dec_ioasic_data *) d->dec_ioasic;
-	r->intr |= interrupt->line;
-	dec_ioasic_reassert(r);
-}
-void kn02ba_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct kn02ba_data *d = (struct kn02ba_data *) interrupt->extra;
-	struct dec_ioasic_data *r = (struct dec_ioasic_data *) d->dec_ioasic;
-	r->intr &= ~interrupt->line;
-	dec_ioasic_reassert(r);
-}
-
-
-DEVICE_ACCESS(kn02ba_mer)
-{
-	struct kn02ba_data *d = (struct kn02ba_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	case 0:
-		if (writeflag == MEM_WRITE)
-			d->mer = idata;
-		else
-			odata = d->mer;
-
-		debug("[ kn02ba_mer: %s MER, data=0x%08x (%s %s %s %s %s %s %s) ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			d->mer,
-			d->mer & KMIN_MER_PAGE_BRY ? "PAGE_BRY" : "--",
-			d->mer & KMIN_MER_TLEN ? "TLEN" : "--",
-			d->mer & KMIN_MER_PARDIS ? "PARDIS" : "--",
-			d->mer & KMIN_LASTB31 ? "LASTB31" : "--",
-			d->mer & KMIN_LASTB23 ? "LASTB23" : "--",
-			d->mer & KMIN_LASTB15 ? "LASTB15" : "--",
-			d->mer & KMIN_LASTB07 ? "LASTB07" : "--"
-			);
-
-		break;
-
-	default:
-		if (writeflag == MEM_READ) {
-			fatal("[ kn02ba_mer: read from offset 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			fatal("[ kn02ba_mer: write to offset 0x%08lx: 0x%08x ]\n",
-			    (long)relative_addr, (int)idata);
-		}
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(kn02ba_msr)
-{
-	struct kn02ba_data *d = (struct kn02ba_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	case 0:
-		if (writeflag == MEM_WRITE)
-			d->msr = idata;
-		else
-			odata = d->msr;
-
-		debug("[ kn02ba_msr: %s MSR, data=0x%08x (%s) ]\n",
-			writeflag == MEM_WRITE ? "write to" : "read from",
-			d->msr,
-			d->msr & KMIN_MSR_SIZE_16Mb ? "16Mb" : "--"
-			);
-
-		break;
-
-	default:
-		if (writeflag == MEM_READ) {
-			fatal("[ kn02ba_msr: read from offset 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			fatal("[ kn02ba_msr: write to offset 0x%08lx: 0x%08x ]\n",
-			    (long)relative_addr, (int)idata);
-		}
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(kn02ba)
-{
-	struct kn02ba_data *d;
-	int i;
-
-	CHECK_ALLOCATION(d = (struct kn02ba_data *) malloc(sizeof(struct kn02ba_data)));
-	memset(d, 0, sizeof(struct kn02ba_data));
-
-	/*  Connect the kn02ba to a specific MIPS CPU interrupt line:  */
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	/*  Register the interrupts:  */
-	for (i = 0; i < 32; i++) {
-		struct interrupt templ;
-		char tmpstr[300];
-		snprintf(tmpstr, sizeof(tmpstr), "%s.kn02ba.0x%x",
-		    devinit->interrupt_path, 1 << i);
-		// printf("registering '%s'\n", tmpstr);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 1 << i;
-		templ.name = tmpstr;
-		templ.extra = d;
-		templ.interrupt_assert = kn02ba_interrupt_assert;
-		templ.interrupt_deassert = kn02ba_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	memory_device_register(devinit->machine->memory, "kn02ba_mer",
-	    KMIN_REG_MER, sizeof(uint32_t), dev_kn02ba_mer_access, d,
-	    DM_DEFAULT, NULL);
-
-	memory_device_register(devinit->machine->memory, "kn02ba_msr",
-	    KMIN_REG_MSR, sizeof(uint32_t), dev_kn02ba_msr_access, d,
-	    DM_DEFAULT, NULL);
-
-	d->dec_ioasic = dev_dec_ioasic_init(devinit->machine->cpus[0],
-		devinit->machine->memory, KMIN_SYS_ASIC, 0, &d->irq);
-
-	d->msr = KMIN_MSR_SIZE_16Mb;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_kn02.c gxemul-0.7.0+dfsg/src/devices/dev_kn02.c
--- gxemul-0.6.2/src/devices/dev_kn02.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_kn02.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,190 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: DEC KN02 mainbus (TurboChannel interrupt controller)
+ *
+ *  Used in DECstation type 2 ("3MAX").  See include/dec_kn02.h for more info.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/dec_kn02.h"
+
+
+#define	DEV_KN02_LENGTH		0x1000
+
+
+struct kn02_data {
+	uint8_t		csr[sizeof(uint32_t)];
+
+	/*  Dummy fill bytes, so dyntrans can be used:  */
+	uint8_t		filler[DEV_KN02_LENGTH - sizeof(uint32_t)];
+
+	struct interrupt irq;
+	int		int_asserted;
+};
+
+
+/*
+ *  kn02_interrupt_assert(), kn02_interrupt_deassert():
+ *
+ *  Called whenever a KN02 (TurboChannel) interrupt is asserted/deasserted.
+ */
+void kn02_interrupt_assert(struct interrupt *interrupt)
+{
+	struct kn02_data *d = (struct kn02_data *) interrupt->extra;
+	d->csr[0] |= interrupt->line;
+	if (d->csr[0] & d->csr[2] && !d->int_asserted) {
+		d->int_asserted = 1;
+		INTERRUPT_ASSERT(d->irq);
+	}
+}
+void kn02_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct kn02_data *d = (struct kn02_data *) interrupt->extra;
+	d->csr[0] &= ~interrupt->line;
+	if (!(d->csr[0] & d->csr[2]) && d->int_asserted) {
+		d->int_asserted = 0;
+		INTERRUPT_DEASSERT(d->irq);
+	}
+}
+
+
+DEVICE_ACCESS(kn02)
+{
+	struct kn02_data *d = (struct kn02_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	case 0:
+		if (writeflag==MEM_READ) {
+			odata = d->csr[0] + (d->csr[1] << 8) +
+			    (d->csr[2] << 16) + (d->csr[3] << 24);
+
+			/* debug("[ kn02: read from CSR: 0x%08x ]\n", odata); */
+		} else {
+			/*
+			 *  Only bits 23..8 are considered writable. The
+			 *  lowest 8 bits are actually writable, but don't
+			 *  affect the interrupt I/O bits; the low 8 bits
+			 *  on write turn on and off LEDs.  (There are no
+			 *  LEDs in the emulator, so those bits are just
+			 *  ignored.)
+			 */
+			int old_assert = (d->csr[0] & d->csr[2])? 1 : 0;
+			int new_assert;
+			/* fatal("[ kn02: write to CSR: 0x%08x ]\n", idata); */
+
+			d->csr[1] = (idata >> 8) & 255;
+			d->csr[2] = (idata >> 16) & 255;
+
+			/*  Recalculate interrupt assertions:  */
+			new_assert = (d->csr[0] & d->csr[2])? 1 : 0;
+			if (new_assert != old_assert) {
+				if (new_assert) {
+					INTERRUPT_ASSERT(d->irq);
+					d->int_asserted = 1;
+				} else {
+					INTERRUPT_DEASSERT(d->irq);
+					d->int_asserted = 0;
+				}
+			}
+		}
+		break;
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ kn02: read from 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			debug("[ kn02: write to  0x%08lx: 0x%08x ]\n",
+			    (long)relative_addr, (int)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(kn02)
+{
+	struct kn02_data *d;
+	uint32_t csr;
+	int i;
+
+	CHECK_ALLOCATION(d = (struct kn02_data *) malloc(sizeof(struct kn02_data)));
+	memset(d, 0, sizeof(struct kn02_data));
+
+	/*  Connect the KN02 to a specific MIPS CPU interrupt line:  */
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	/*  Register the 8 possible TurboChannel interrupts:  */
+	for (i=0; i<8; i++) {
+		struct interrupt templ;
+		char tmpstr[300];
+		snprintf(tmpstr, sizeof(tmpstr), "%s.kn02.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 1 << i;
+		templ.name = tmpstr;
+		templ.extra = d;
+		templ.interrupt_assert = kn02_interrupt_assert;
+		templ.interrupt_deassert = kn02_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	/*
+	 *  Set initial value of the CSR. Note: If the KN02_CSR_NRMMOD bit
+	 *  is not set, the 5000/200 PROM image loops forever.
+	 */
+	csr = KN02_CSR_NRMMOD;
+	d->csr[0] = csr;
+	d->csr[1] = csr >> 8;
+	d->csr[2] = csr >> 16;
+	d->csr[3] = csr >> 24;
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_KN02_LENGTH, dev_kn02_access, d,
+	    DM_DYNTRANS_OK, &d->csr[0]);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_kn02.cc gxemul-0.7.0+dfsg/src/devices/dev_kn02.cc
--- gxemul-0.6.2/src/devices/dev_kn02.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_kn02.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,190 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: DEC KN02 mainbus (TurboChannel interrupt controller)
- *
- *  Used in DECstation type 2 ("3MAX").  See include/dec_kn02.h for more info.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/dec_kn02.h"
-
-
-#define	DEV_KN02_LENGTH		0x1000
-
-
-struct kn02_data {
-	uint8_t		csr[sizeof(uint32_t)];
-
-	/*  Dummy fill bytes, so dyntrans can be used:  */
-	uint8_t		filler[DEV_KN02_LENGTH - sizeof(uint32_t)];
-
-	struct interrupt irq;
-	int		int_asserted;
-};
-
-
-/*
- *  kn02_interrupt_assert(), kn02_interrupt_deassert():
- *
- *  Called whenever a KN02 (TurboChannel) interrupt is asserted/deasserted.
- */
-void kn02_interrupt_assert(struct interrupt *interrupt)
-{
-	struct kn02_data *d = (struct kn02_data *) interrupt->extra;
-	d->csr[0] |= interrupt->line;
-	if (d->csr[0] & d->csr[2] && !d->int_asserted) {
-		d->int_asserted = 1;
-		INTERRUPT_ASSERT(d->irq);
-	}
-}
-void kn02_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct kn02_data *d = (struct kn02_data *) interrupt->extra;
-	d->csr[0] &= ~interrupt->line;
-	if (!(d->csr[0] & d->csr[2]) && d->int_asserted) {
-		d->int_asserted = 0;
-		INTERRUPT_DEASSERT(d->irq);
-	}
-}
-
-
-DEVICE_ACCESS(kn02)
-{
-	struct kn02_data *d = (struct kn02_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	case 0:
-		if (writeflag==MEM_READ) {
-			odata = d->csr[0] + (d->csr[1] << 8) +
-			    (d->csr[2] << 16) + (d->csr[3] << 24);
-
-			/* debug("[ kn02: read from CSR: 0x%08x ]\n", odata); */
-		} else {
-			/*
-			 *  Only bits 23..8 are considered writable. The
-			 *  lowest 8 bits are actually writable, but don't
-			 *  affect the interrupt I/O bits; the low 8 bits
-			 *  on write turn on and off LEDs.  (There are no
-			 *  LEDs in the emulator, so those bits are just
-			 *  ignored.)
-			 */
-			int old_assert = (d->csr[0] & d->csr[2])? 1 : 0;
-			int new_assert;
-			/* fatal("[ kn02: write to CSR: 0x%08x ]\n", idata); */
-
-			d->csr[1] = (idata >> 8) & 255;
-			d->csr[2] = (idata >> 16) & 255;
-
-			/*  Recalculate interrupt assertions:  */
-			new_assert = (d->csr[0] & d->csr[2])? 1 : 0;
-			if (new_assert != old_assert) {
-				if (new_assert) {
-					INTERRUPT_ASSERT(d->irq);
-					d->int_asserted = 1;
-				} else {
-					INTERRUPT_DEASSERT(d->irq);
-					d->int_asserted = 0;
-				}
-			}
-		}
-		break;
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ kn02: read from 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			debug("[ kn02: write to  0x%08lx: 0x%08x ]\n",
-			    (long)relative_addr, (int)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(kn02)
-{
-	struct kn02_data *d;
-	uint32_t csr;
-	int i;
-
-	CHECK_ALLOCATION(d = (struct kn02_data *) malloc(sizeof(struct kn02_data)));
-	memset(d, 0, sizeof(struct kn02_data));
-
-	/*  Connect the KN02 to a specific MIPS CPU interrupt line:  */
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	/*  Register the 8 possible TurboChannel interrupts:  */
-	for (i=0; i<8; i++) {
-		struct interrupt templ;
-		char tmpstr[300];
-		snprintf(tmpstr, sizeof(tmpstr), "%s.kn02.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 1 << i;
-		templ.name = tmpstr;
-		templ.extra = d;
-		templ.interrupt_assert = kn02_interrupt_assert;
-		templ.interrupt_deassert = kn02_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	/*
-	 *  Set initial value of the CSR. Note: If the KN02_CSR_NRMMOD bit
-	 *  is not set, the 5000/200 PROM image loops forever.
-	 */
-	csr = KN02_CSR_NRMMOD;
-	d->csr[0] = csr;
-	d->csr[1] = csr >> 8;
-	d->csr[2] = csr >> 16;
-	d->csr[3] = csr >> 24;
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_KN02_LENGTH, dev_kn02_access, d,
-	    DM_DYNTRANS_OK, &d->csr[0]);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_kn220.c gxemul-0.7.0+dfsg/src/devices/dev_kn220.c
--- gxemul-0.6.2/src/devices/dev_kn220.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_kn220.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,182 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: DEC KN220 (DECsystem 5500) devices
+ *
+ *	o)  I/O board
+ *	o)  SGEC (ethernet)  (Called "ne" in Ultrix.)
+ *
+ *  TODO:  Study docs.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "devices.h"
+#include "memory.h"
+#include "misc.h"
+
+#define IOBOARD_DEBUG
+
+struct dec5500_ioboard_data {
+	int	dummy;
+};
+
+#define SGEC_DEBUG
+
+struct sgec_data {
+	int	irq_nr;
+};
+
+
+/*
+ *  dev_dec5500_ioboard_access():
+ */
+DEVICE_ACCESS(dec5500_ioboard)
+{
+	/*  struct dec5500_ioboard_data *d =
+	    (struct dec5500_ioboard_data *) extra;  */
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+#ifdef IOBOARD_DEBUG
+	if (writeflag == MEM_WRITE)
+		debug("[ dec5500_ioboard: write to address 0x%llx, "
+		    "data=0x%016llx ]\n", (long long)relative_addr,
+		    (long long)idata);
+	else
+		debug("[ dec5500_ioboard: read from address 0x%llx ]\n",
+		    (long long)relative_addr);
+#endif
+
+	switch (relative_addr) {
+	case 0:
+		if (writeflag == MEM_READ)
+			/*
+			 *  TODO:  One of these bits indicate I/O board
+			 *  present.
+			 */
+			odata = 0xffffffffULL;
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			debug("[ dec5500_ioboard: unimplemented write to "
+			    "address 0x%llx, data=0x%016llx ]\n",
+			    (long long)relative_addr, (long long)idata);
+		else
+			debug("[ dec5500_ioboard: unimplemented read from"
+			    " address 0x%llx ]\n", (long long)relative_addr);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_sgec_access():
+ */
+DEVICE_ACCESS(sgec)
+{
+	/*  struct sgec_data *d = (struct sgec_data *) extra;  */
+	uint64_t idata = 0, odata = 0;
+
+	idata = memory_readmax64(cpu, data, len);
+
+#ifdef SGEC_DEBUG
+	if (writeflag == MEM_WRITE)
+		debug("[ sgec: write to address 0x%llx, data=0x%016llx ]\n",
+		    (long long)relative_addr, (long long)idata);
+	else
+		debug("[ sgec: read from address 0x%llx ]\n",
+		    (long long)relative_addr);
+#endif
+
+	switch (relative_addr) {
+	case 0x14:
+		if (writeflag == MEM_READ)
+			odata = 0x80000000;
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			debug("[ sgec: unimplemented write to address 0x%llx,"
+			    " data=0x%016llx ]\n", (long long)relative_addr,
+			    (long long)idata);
+		else
+			debug("[ sgec: unimplemented read from address "
+			    "0x%llx ]\n", (long long)relative_addr);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_sgec_init():
+ */
+void dev_sgec_init(struct memory *mem, uint64_t baseaddr, int irq_nr)
+{
+	struct sgec_data *d;
+
+	CHECK_ALLOCATION(d = (struct sgec_data *) malloc(sizeof(struct sgec_data)));
+	memset(d, 0, sizeof(struct sgec_data));
+
+	d->irq_nr = irq_nr;
+
+	memory_device_register(mem, "sgec", baseaddr, DEV_SGEC_LENGTH,
+	    dev_sgec_access, (void *)d, DM_DEFAULT, NULL);
+}
+
+
+/*
+ *  dev_dec5500_ioboard_init():
+ */
+struct dec5500_ioboard_data *dev_dec5500_ioboard_init(struct cpu *cpu,
+	struct memory *mem, uint64_t baseaddr)
+{
+	struct dec5500_ioboard_data *d;
+
+	CHECK_ALLOCATION(d = (struct dec5500_ioboard_data *) malloc(sizeof(struct dec5500_ioboard_data)));
+	memset(d, 0, sizeof(struct dec5500_ioboard_data));
+
+	memory_device_register(mem, "dec5500_ioboard", baseaddr,
+	    DEV_DEC5500_IOBOARD_LENGTH, dev_dec5500_ioboard_access,
+	    (void *)d, DM_DEFAULT, NULL);
+
+	return d;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_kn220.cc gxemul-0.7.0+dfsg/src/devices/dev_kn220.cc
--- gxemul-0.6.2/src/devices/dev_kn220.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_kn220.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,182 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: DEC KN220 (DECsystem 5500) devices
- *
- *	o)  I/O board
- *	o)  SGEC (ethernet)  (Called "ne" in Ultrix.)
- *
- *  TODO:  Study docs.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "devices.h"
-#include "memory.h"
-#include "misc.h"
-
-#define IOBOARD_DEBUG
-
-struct dec5500_ioboard_data {
-	int	dummy;
-};
-
-#define SGEC_DEBUG
-
-struct sgec_data {
-	int	irq_nr;
-};
-
-
-/*
- *  dev_dec5500_ioboard_access():
- */
-DEVICE_ACCESS(dec5500_ioboard)
-{
-	/*  struct dec5500_ioboard_data *d =
-	    (struct dec5500_ioboard_data *) extra;  */
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-#ifdef IOBOARD_DEBUG
-	if (writeflag == MEM_WRITE)
-		debug("[ dec5500_ioboard: write to address 0x%llx, "
-		    "data=0x%016llx ]\n", (long long)relative_addr,
-		    (long long)idata);
-	else
-		debug("[ dec5500_ioboard: read from address 0x%llx ]\n",
-		    (long long)relative_addr);
-#endif
-
-	switch (relative_addr) {
-	case 0:
-		if (writeflag == MEM_READ)
-			/*
-			 *  TODO:  One of these bits indicate I/O board
-			 *  present.
-			 */
-			odata = 0xffffffffULL;
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE)
-			debug("[ dec5500_ioboard: unimplemented write to "
-			    "address 0x%llx, data=0x%016llx ]\n",
-			    (long long)relative_addr, (long long)idata);
-		else
-			debug("[ dec5500_ioboard: unimplemented read from"
-			    " address 0x%llx ]\n", (long long)relative_addr);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_sgec_access():
- */
-DEVICE_ACCESS(sgec)
-{
-	/*  struct sgec_data *d = (struct sgec_data *) extra;  */
-	uint64_t idata = 0, odata = 0;
-
-	idata = memory_readmax64(cpu, data, len);
-
-#ifdef SGEC_DEBUG
-	if (writeflag == MEM_WRITE)
-		debug("[ sgec: write to address 0x%llx, data=0x%016llx ]\n",
-		    (long long)relative_addr, (long long)idata);
-	else
-		debug("[ sgec: read from address 0x%llx ]\n",
-		    (long long)relative_addr);
-#endif
-
-	switch (relative_addr) {
-	case 0x14:
-		if (writeflag == MEM_READ)
-			odata = 0x80000000;
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE)
-			debug("[ sgec: unimplemented write to address 0x%llx,"
-			    " data=0x%016llx ]\n", (long long)relative_addr,
-			    (long long)idata);
-		else
-			debug("[ sgec: unimplemented read from address "
-			    "0x%llx ]\n", (long long)relative_addr);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_sgec_init():
- */
-void dev_sgec_init(struct memory *mem, uint64_t baseaddr, int irq_nr)
-{
-	struct sgec_data *d;
-
-	CHECK_ALLOCATION(d = (struct sgec_data *) malloc(sizeof(struct sgec_data)));
-	memset(d, 0, sizeof(struct sgec_data));
-
-	d->irq_nr = irq_nr;
-
-	memory_device_register(mem, "sgec", baseaddr, DEV_SGEC_LENGTH,
-	    dev_sgec_access, (void *)d, DM_DEFAULT, NULL);
-}
-
-
-/*
- *  dev_dec5500_ioboard_init():
- */
-struct dec5500_ioboard_data *dev_dec5500_ioboard_init(struct cpu *cpu,
-	struct memory *mem, uint64_t baseaddr)
-{
-	struct dec5500_ioboard_data *d;
-
-	CHECK_ALLOCATION(d = (struct dec5500_ioboard_data *) malloc(sizeof(struct dec5500_ioboard_data)));
-	memset(d, 0, sizeof(struct dec5500_ioboard_data));
-
-	memory_device_register(mem, "dec5500_ioboard", baseaddr,
-	    DEV_DEC5500_IOBOARD_LENGTH, dev_dec5500_ioboard_access,
-	    (void *)d, DM_DEFAULT, NULL);
-
-	return d;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_kn230.c gxemul-0.7.0+dfsg/src/devices/dev_kn230.c
--- gxemul-0.6.2/src/devices/dev_kn230.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_kn230.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,174 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: DEC KN230 (MIPSMATE 5100) stuff
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "device.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/dec_5100.h"
+
+
+#define	DEV_KN230_LENGTH		0x1c00000
+
+struct kn230_data {
+	struct interrupt	mips_irq_2;
+	struct interrupt	mips_irq_3;
+
+	uint32_t		csr;
+};
+
+
+/*  
+ *  kn230_interrupt_assert():
+ *  kn230_interrupt_deassert():
+ *
+ *  Called whenever a KN230 interrupt is asserted/deasserted.
+ */
+void kn230_interrupt_assert(struct interrupt *interrupt)
+{
+	struct kn230_data *d = (struct kn230_data *) interrupt->extra;
+	int assert2 = 0, assert3 = 0;
+
+	d->csr |= interrupt->line;
+	if (d->csr & (KN230_CSR_INTR_SII | KN230_CSR_INTR_LANCE))
+		assert3 = 1;
+	if (d->csr & (KN230_CSR_INTR_DZ0 |
+	    KN230_CSR_INTR_OPT0 | KN230_CSR_INTR_OPT1))
+		assert2 = 1;
+
+	if (assert2)
+                INTERRUPT_ASSERT(d->mips_irq_2);
+	if (assert3)
+                INTERRUPT_ASSERT(d->mips_irq_2);
+}
+void kn230_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct kn230_data *d = (struct kn230_data *) interrupt->extra;
+	int assert2 = 0, assert3 = 0;
+
+	d->csr &= ~interrupt->line;
+	if (d->csr & (KN230_CSR_INTR_SII | KN230_CSR_INTR_LANCE))
+		assert3 = 1;
+	if (d->csr & (KN230_CSR_INTR_DZ0 |
+	    KN230_CSR_INTR_OPT0 | KN230_CSR_INTR_OPT1))
+		assert2 = 1;
+
+	if (!assert2)
+                INTERRUPT_DEASSERT(d->mips_irq_2);
+	if (!assert3)
+                INTERRUPT_DEASSERT(d->mips_irq_2);
+}
+
+
+DEVICE_ACCESS(kn230)
+{
+	struct kn230_data *d = (struct kn230_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	case 0:
+		if (writeflag==MEM_READ) {
+			odata = d->csr;
+			/* debug("[ kn230: read from CSR: 0x%08x ]\n",
+			    (int)odata); */
+		} else {
+			/* debug("[ kn230: write to CSR: 0x%08x ]\n",
+			    (int)idata); */
+		}
+		break;
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ kn230: read from 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			debug("[ kn230: write to  0x%08lx: 0x%08x ]\n",
+			    (long)relative_addr, (int)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+  
+	return 1;
+}
+
+
+DEVINIT(kn230)
+{
+	struct kn230_data *d;
+	char tmpstr[300];
+	int i;
+
+	CHECK_ALLOCATION(d = (struct kn230_data *) malloc(sizeof(struct kn230_data)));
+	memset(d, 0, sizeof(struct kn230_data));
+
+	/*
+	 *  devinit->interrupt_path points to the MIPS cpu itself.
+	 *  The KN230 interrupt controller interrupts at MIPS interrupts
+	 *  2 and 3, depending on which KN230 is asserted.
+	 */
+	snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path);
+	INTERRUPT_CONNECT(tmpstr, d->mips_irq_2);
+	snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
+	INTERRUPT_CONNECT(tmpstr, d->mips_irq_3);
+
+	/*  Register KN230 interrupts 8..15:  */
+	for (i=8; i<=15; i++) {
+		struct interrupt templ;
+		char tmpstr2[300];
+		snprintf(tmpstr2, sizeof(tmpstr2), "%s.kn230.0x%x",
+		    devinit->interrupt_path, 1 << i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = 1 << i;
+		templ.name = tmpstr2;
+		templ.extra = d;
+                templ.interrupt_assert = kn230_interrupt_assert;
+                templ.interrupt_deassert = kn230_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_KN230_LENGTH, dev_kn230_access, d,
+	    DM_DEFAULT, NULL);
+
+	devinit->return_ptr = d;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_kn230.cc gxemul-0.7.0+dfsg/src/devices/dev_kn230.cc
--- gxemul-0.6.2/src/devices/dev_kn230.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_kn230.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,174 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: DEC KN230 (MIPSMATE 5100) stuff
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "device.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/dec_5100.h"
-
-
-#define	DEV_KN230_LENGTH		0x1c00000
-
-struct kn230_data {
-	struct interrupt	mips_irq_2;
-	struct interrupt	mips_irq_3;
-
-	uint32_t		csr;
-};
-
-
-/*  
- *  kn230_interrupt_assert():
- *  kn230_interrupt_deassert():
- *
- *  Called whenever a KN230 interrupt is asserted/deasserted.
- */
-void kn230_interrupt_assert(struct interrupt *interrupt)
-{
-	struct kn230_data *d = (struct kn230_data *) interrupt->extra;
-	int assert2 = 0, assert3 = 0;
-
-	d->csr |= interrupt->line;
-	if (d->csr & (KN230_CSR_INTR_SII | KN230_CSR_INTR_LANCE))
-		assert3 = 1;
-	if (d->csr & (KN230_CSR_INTR_DZ0 |
-	    KN230_CSR_INTR_OPT0 | KN230_CSR_INTR_OPT1))
-		assert2 = 1;
-
-	if (assert2)
-                INTERRUPT_ASSERT(d->mips_irq_2);
-	if (assert3)
-                INTERRUPT_ASSERT(d->mips_irq_2);
-}
-void kn230_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct kn230_data *d = (struct kn230_data *) interrupt->extra;
-	int assert2 = 0, assert3 = 0;
-
-	d->csr &= ~interrupt->line;
-	if (d->csr & (KN230_CSR_INTR_SII | KN230_CSR_INTR_LANCE))
-		assert3 = 1;
-	if (d->csr & (KN230_CSR_INTR_DZ0 |
-	    KN230_CSR_INTR_OPT0 | KN230_CSR_INTR_OPT1))
-		assert2 = 1;
-
-	if (!assert2)
-                INTERRUPT_DEASSERT(d->mips_irq_2);
-	if (!assert3)
-                INTERRUPT_DEASSERT(d->mips_irq_2);
-}
-
-
-DEVICE_ACCESS(kn230)
-{
-	struct kn230_data *d = (struct kn230_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	case 0:
-		if (writeflag==MEM_READ) {
-			odata = d->csr;
-			/* debug("[ kn230: read from CSR: 0x%08x ]\n",
-			    (int)odata); */
-		} else {
-			/* debug("[ kn230: write to CSR: 0x%08x ]\n",
-			    (int)idata); */
-		}
-		break;
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ kn230: read from 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			debug("[ kn230: write to  0x%08lx: 0x%08x ]\n",
-			    (long)relative_addr, (int)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-  
-	return 1;
-}
-
-
-DEVINIT(kn230)
-{
-	struct kn230_data *d;
-	char tmpstr[300];
-	int i;
-
-	CHECK_ALLOCATION(d = (struct kn230_data *) malloc(sizeof(struct kn230_data)));
-	memset(d, 0, sizeof(struct kn230_data));
-
-	/*
-	 *  devinit->interrupt_path points to the MIPS cpu itself.
-	 *  The KN230 interrupt controller interrupts at MIPS interrupts
-	 *  2 and 3, depending on which KN230 is asserted.
-	 */
-	snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path);
-	INTERRUPT_CONNECT(tmpstr, d->mips_irq_2);
-	snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
-	INTERRUPT_CONNECT(tmpstr, d->mips_irq_3);
-
-	/*  Register KN230 interrupts 8..15:  */
-	for (i=8; i<=15; i++) {
-		struct interrupt templ;
-		char tmpstr2[300];
-		snprintf(tmpstr2, sizeof(tmpstr2), "%s.kn230.0x%x",
-		    devinit->interrupt_path, 1 << i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = 1 << i;
-		templ.name = tmpstr2;
-		templ.extra = d;
-                templ.interrupt_assert = kn230_interrupt_assert;
-                templ.interrupt_deassert = kn230_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_KN230_LENGTH, dev_kn230_access, d,
-	    DM_DEFAULT, NULL);
-
-	devinit->return_ptr = d;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_lca.c gxemul-0.7.0+dfsg/src/devices/dev_lca.c
--- gxemul-0.6.2/src/devices/dev_lca.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_lca.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,381 @@
+/*
+ *  Copyright (C) 2006-2011  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: LCA PCI bus, for Alpha machines
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_isa.h"
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/alpha_lcareg.h"
+
+#define	LCA_ISA_BASE	(LCA_PCI_SIO + 0x10000000)
+#define	LCA_ISA_MEMBASE	(LCA_PCI_SIO + 0x18000000)
+
+
+struct lca_data {
+	struct pci_data		*pci_data;
+
+	uint64_t		ioc_conf;
+	uint64_t		tlb_enable;
+	uint64_t		window_base_0;
+	uint64_t		window_mask_0;
+	uint64_t		window_t_base_0;
+	uint64_t		window_base_1;
+	uint64_t		window_mask_1;
+	uint64_t		window_t_base_1;
+};
+
+
+/*
+ *  lca_interrupt_assert():
+ *
+ *  Line 0 = ISA interrupt.
+ */
+void lca_interrupt_assert(struct interrupt *interrupt)
+{
+	fatal("lca_interrupt_assert: TODO\n");
+	exit(1);
+}
+
+
+/*
+ *  lca_interrupt_deassert():
+ *
+ *  Line 0 = ISA interrupt.
+ */
+void lca_interrupt_deassert(struct interrupt *interrupt)
+{
+	fatal("lca_interrupt_deassert: TODO\n");
+	exit(1);
+}
+
+
+DEVICE_ACCESS(lca_pci_conf)
+{
+	uint64_t idata = 0, odata = 0;
+	int tag, bus, dev, func, reg;
+	struct lca_data *d = (struct lca_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*
+	 *  1. Decompose the address into a tag.
+	 *
+	 *  According to NetBSD's lca_pci.c, the address is composed like this:
+	 *
+	 *	addr = tag << 5 | (regoffset & ~0x03) << 5 | 0x3 << 3
+	 */
+	reg = (relative_addr >> 5) & 0xfc;
+	tag = (relative_addr >> 5) & ~0xff;
+
+	/*
+	 *  2. Decompose the tag into bus, dev, and func.
+	 *
+	 *  The tag can be constructed in one of two ways. On the primary
+	 *  bus (nr 0):
+	 *
+	 *	tag = (1 << (device + 11)) | (function << 8);
+	 *
+	 *  and on other busses, the tag is a normal:
+	 *
+	 *	tag = (bus << 16) | (device << 11) | (function << 8)
+	 */
+	/*  printf("tag = 0x%x\n", (int)tag);  */
+	bus = d->ioc_conf & 1;
+
+	if (bus == 0) {
+		for (dev=0; dev<21; dev++)
+			if (tag & (0x800 << dev))
+				break;
+		if (dev >= 21) {
+			/*  fatal("[ LCA: No bus 0 device? TODO ]\n");
+			exit(1);  */
+			dev = 0;
+		}
+	} else {
+		fatal("TODO. Non-zero bus.\n");
+		exit(1);
+	}
+
+	func = (tag >> 8) & 7;
+	/*  printf("bus=%i dev=%i func=%i reg=%i\n", bus,dev,func,reg);  */
+
+	/*  Pass PCI accesses onto bus_pci:  */
+	bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
+	bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
+	    &odata : &idata, len, writeflag);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(lca_isa)
+{
+	unsigned int ofs, i;
+	uint8_t byte;
+
+	relative_addr >>= 5;
+
+	ofs = relative_addr & 3;
+	if (ofs > len) {
+		fatal("[ ofs=%i len=%i in lca_isa access function. "
+		    "aborting ]\n", ofs, len);
+		exit(1);
+	}
+
+	if (writeflag == MEM_WRITE) {
+		byte = data[ofs % len];
+		return cpu->memory_rw(cpu, cpu->mem, LCA_ISA_BASE +
+		    relative_addr, &byte, 1, writeflag, CACHE_NONE);
+	}
+
+	cpu->memory_rw(cpu, cpu->mem, LCA_ISA_BASE + relative_addr,
+	    &byte, 1, MEM_READ, CACHE_NONE);
+
+	for (i=0; i<len; i++)
+		data[i] = i == ofs? byte : 0x00;
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(lca_ioc)
+{
+	uint64_t idata = 0, odata = 0;
+	struct lca_data *d = (struct lca_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr + LCA_IOC_BASE) {
+
+	case LCA_IOC_BASE:
+		/*  Ignore? Linux reads from the base at startup.  */
+		break;
+
+	case LCA_IOC_CONF:
+		if (writeflag == MEM_READ) {
+			odata = d->ioc_conf;
+		} else {
+			d->ioc_conf = idata;
+			/*  Only bit 0 is implemented so far, the PCI bus 0 vs
+			    bus non-0 selection bit.  */
+			if (idata & ~1) {
+				fatal("TODO: Write to unimplemented bit of"
+				    " IOC_CONF: 0x%x\n", (int)idata);
+				exit(1);
+			}
+		}
+		break;
+
+	case LCA_IOC_TBIA:
+		/*  TLB Invalidate All.  */
+		/*  TODO: For now, let's just ignore it.  */
+		break;
+
+	case LCA_IOC_TB_ENA:
+		if (writeflag == MEM_READ) {
+			odata = d->tlb_enable;
+		} else {
+			d->tlb_enable = idata;
+			/*  TODO: Actually implement this.  */
+			if (idata & ~IOC_TB_ENA_TEN) {
+				fatal("TODO: LCA_IOC_TB_ENA value "
+				    " (0x%" PRIx64") has unimplemented "
+				    "bits.\n", (uint64_t)idata);
+				exit(1);
+			}
+		}
+		break;
+
+	case LCA_IOC_W_BASE0:
+		if (writeflag == MEM_READ) {
+			odata = d->window_base_0;
+		} else {
+			d->window_base_0 = idata;
+			/*  TODO: Actually implement this.  */
+			if (idata != 0ULL && idata != 0x300800000ULL) {
+				fatal("TODO: LCA_IOC_W_BASE0 value differs"
+				    " (0x%" PRIx64") from the only implemented"
+				    " values\n", (uint64_t)idata);
+				exit(1);
+			}
+		}
+		break;
+
+	case LCA_IOC_W_MASK0:
+		if (writeflag == MEM_READ) {
+			odata = d->window_mask_0;
+		} else {
+			d->window_mask_0 = idata;
+			/*  TODO: Actually implement this.  */
+			if (idata != 0x700000ULL) {
+				fatal("TODO: LCA_IOC_W_MASK0 value differs"
+				    " (0x%" PRIx64") from the only implemented"
+				    " value\n", (uint64_t)idata);
+				exit(1);
+			}
+		}
+		break;
+
+	case LCA_IOC_W_T_BASE0:
+		if (writeflag == MEM_READ) {
+			odata = d->window_t_base_0;
+		} else {
+			d->window_t_base_0 = idata;
+			/*  TODO: Actually implement this.  */
+		}
+		break;
+
+	case LCA_IOC_W_BASE1:
+		if (writeflag == MEM_READ) {
+			odata = d->window_base_1;
+		} else {
+			d->window_base_1 = idata;
+			/*  TODO: Actually implement this.  */
+			if (idata != 0x240000000ULL) {
+				fatal("TODO: LCA_IOC_W_BASE1 value differs"
+				    " (0x%" PRIx64") from the only implemented"
+				    " value\n", (uint64_t)idata);
+				exit(1);
+			}
+		}
+		break;
+
+	case LCA_IOC_W_MASK1:
+		if (writeflag == MEM_READ) {
+			odata = d->window_mask_1;
+		} else {
+			d->window_mask_1 = idata;
+			/*  TODO: Actually implement this.  */
+			if (idata != 0x3ff00000ULL) {
+				fatal("TODO: LCA_IOC_W_MASK1 value differs"
+				    " (0x%" PRIx64") from the only implemented"
+				    " value\n", (uint64_t)idata);
+				exit(1);
+			}
+		}
+		break;
+
+	case LCA_IOC_W_T_BASE1:
+		if (writeflag == MEM_READ) {
+			odata = d->window_t_base_1;
+		} else {
+			d->window_t_base_1 = idata;
+			/*  TODO: Actually implement this.  */
+		}
+		break;
+
+	default:fatal("[ lca_ioc: unimplemented %s to offset 0x%x",
+		    writeflag == MEM_WRITE? "write" : "read", (int)
+		    relative_addr);
+		if (writeflag == MEM_WRITE)
+			fatal(": 0x%x", (int)idata);
+		fatal(" ]\n");
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(lca)
+{
+	char *interrupt_path;
+	struct interrupt interrupt_template;
+	struct lca_data *d;
+
+	CHECK_ALLOCATION(d = (struct lca_data *) malloc(sizeof(struct lca_data)));
+	memset(d, 0, sizeof(struct lca_data));
+
+	/*  Register a PCI bus:  */
+	d->pci_data = bus_pci_init(
+	    devinit->machine,
+	    "TODO: irq"		/*  pciirq: TODO  */,
+	    LCA_PCI_SIO,	/*  pci device io offset  */
+	    0x00000000,		/*  pci device mem offset: TODO  */
+	    0x00000000,		/*  PCI portbase: TODO  */
+	    0x00000000,		/*  PCI membase: TODO  */
+	    "TODO: pci irq base",	/*  PCI irqbase: TODO  */
+	    LCA_ISA_BASE,	/*  ISA portbase  */
+	    LCA_ISA_MEMBASE,	/*  ISA membase  */
+	    "TODO: irqbase isa");                /*  ISA irqbase: TODO  */
+
+	/*  Add the "sio0" controller (as seen by NetBSD):  */
+	bus_pci_add(devinit->machine, d->pci_data, devinit->machine->memory,
+	    0, 7, 0, "i82378zb");
+
+	memory_device_register(devinit->machine->memory, "lca_pci_conf",
+	    LCA_PCI_CONF, 0x20000000, dev_lca_pci_conf_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	memory_device_register(devinit->machine->memory, "lca_isa",
+	    LCA_PCI_SIO, 0x10000 << 5, dev_lca_isa_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	memory_device_register(devinit->machine->memory, "lca_ioc",
+	    LCA_IOC_BASE, 0x20000000, dev_lca_ioc_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	CHECK_ALLOCATION(interrupt_path = (char *)
+	    malloc(strlen(devinit->machine->path) + 10));
+	snprintf(interrupt_path, strlen(devinit->machine->path) + 10,
+	    "%s.lca", devinit->machine->path);
+
+	memset(&interrupt_template, 0, sizeof(interrupt_template));
+	interrupt_template.line = 0;
+	interrupt_template.name = interrupt_path;
+	interrupt_template.extra = d;
+	interrupt_template.interrupt_assert = lca_interrupt_assert;
+	interrupt_template.interrupt_deassert = lca_interrupt_deassert;
+	interrupt_handler_register(&interrupt_template);
+
+	bus_isa_init(devinit->machine, interrupt_path,
+	    BUS_ISA_IDE0 | BUS_ISA_IDE1, LCA_ISA_BASE, LCA_ISA_MEMBASE);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_lca.cc gxemul-0.7.0+dfsg/src/devices/dev_lca.cc
--- gxemul-0.6.2/src/devices/dev_lca.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_lca.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,381 +0,0 @@
-/*
- *  Copyright (C) 2006-2011  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: LCA PCI bus, for Alpha machines
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_isa.h"
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/alpha_lcareg.h"
-
-#define	LCA_ISA_BASE	(LCA_PCI_SIO + 0x10000000)
-#define	LCA_ISA_MEMBASE	(LCA_PCI_SIO + 0x18000000)
-
-
-struct lca_data {
-	struct pci_data		*pci_data;
-
-	uint64_t		ioc_conf;
-	uint64_t		tlb_enable;
-	uint64_t		window_base_0;
-	uint64_t		window_mask_0;
-	uint64_t		window_t_base_0;
-	uint64_t		window_base_1;
-	uint64_t		window_mask_1;
-	uint64_t		window_t_base_1;
-};
-
-
-/*
- *  lca_interrupt_assert():
- *
- *  Line 0 = ISA interrupt.
- */
-void lca_interrupt_assert(struct interrupt *interrupt)
-{
-	fatal("lca_interrupt_assert: TODO\n");
-	exit(1);
-}
-
-
-/*
- *  lca_interrupt_deassert():
- *
- *  Line 0 = ISA interrupt.
- */
-void lca_interrupt_deassert(struct interrupt *interrupt)
-{
-	fatal("lca_interrupt_deassert: TODO\n");
-	exit(1);
-}
-
-
-DEVICE_ACCESS(lca_pci_conf)
-{
-	uint64_t idata = 0, odata = 0;
-	int tag, bus, dev, func, reg;
-	struct lca_data *d = (struct lca_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*
-	 *  1. Decompose the address into a tag.
-	 *
-	 *  According to NetBSD's lca_pci.c, the address is composed like this:
-	 *
-	 *	addr = tag << 5 | (regoffset & ~0x03) << 5 | 0x3 << 3
-	 */
-	reg = (relative_addr >> 5) & 0xfc;
-	tag = (relative_addr >> 5) & ~0xff;
-
-	/*
-	 *  2. Decompose the tag into bus, dev, and func.
-	 *
-	 *  The tag can be constructed in one of two ways. On the primary
-	 *  bus (nr 0):
-	 *
-	 *	tag = (1 << (device + 11)) | (function << 8);
-	 *
-	 *  and on other busses, the tag is a normal:
-	 *
-	 *	tag = (bus << 16) | (device << 11) | (function << 8)
-	 */
-	/*  printf("tag = 0x%x\n", (int)tag);  */
-	bus = d->ioc_conf & 1;
-
-	if (bus == 0) {
-		for (dev=0; dev<21; dev++)
-			if (tag & (0x800 << dev))
-				break;
-		if (dev >= 21) {
-			/*  fatal("[ LCA: No bus 0 device? TODO ]\n");
-			exit(1);  */
-			dev = 0;
-		}
-	} else {
-		fatal("TODO. Non-zero bus.\n");
-		exit(1);
-	}
-
-	func = (tag >> 8) & 7;
-	/*  printf("bus=%i dev=%i func=%i reg=%i\n", bus,dev,func,reg);  */
-
-	/*  Pass PCI accesses onto bus_pci:  */
-	bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
-	bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
-	    &odata : &idata, len, writeflag);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(lca_isa)
-{
-	unsigned int ofs, i;
-	uint8_t byte;
-
-	relative_addr >>= 5;
-
-	ofs = relative_addr & 3;
-	if (ofs > len) {
-		fatal("[ ofs=%i len=%i in lca_isa access function. "
-		    "aborting ]\n", ofs, len);
-		exit(1);
-	}
-
-	if (writeflag == MEM_WRITE) {
-		byte = data[ofs % len];
-		return cpu->memory_rw(cpu, cpu->mem, LCA_ISA_BASE +
-		    relative_addr, &byte, 1, writeflag, CACHE_NONE);
-	}
-
-	cpu->memory_rw(cpu, cpu->mem, LCA_ISA_BASE + relative_addr,
-	    &byte, 1, MEM_READ, CACHE_NONE);
-
-	for (i=0; i<len; i++)
-		data[i] = i == ofs? byte : 0x00;
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(lca_ioc)
-{
-	uint64_t idata = 0, odata = 0;
-	struct lca_data *d = (struct lca_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr + LCA_IOC_BASE) {
-
-	case LCA_IOC_BASE:
-		/*  Ignore? Linux reads from the base at startup.  */
-		break;
-
-	case LCA_IOC_CONF:
-		if (writeflag == MEM_READ) {
-			odata = d->ioc_conf;
-		} else {
-			d->ioc_conf = idata;
-			/*  Only bit 0 is implemented so far, the PCI bus 0 vs
-			    bus non-0 selection bit.  */
-			if (idata & ~1) {
-				fatal("TODO: Write to unimplemented bit of"
-				    " IOC_CONF: 0x%x\n", (int)idata);
-				exit(1);
-			}
-		}
-		break;
-
-	case LCA_IOC_TBIA:
-		/*  TLB Invalidate All.  */
-		/*  TODO: For now, let's just ignore it.  */
-		break;
-
-	case LCA_IOC_TB_ENA:
-		if (writeflag == MEM_READ) {
-			odata = d->tlb_enable;
-		} else {
-			d->tlb_enable = idata;
-			/*  TODO: Actually implement this.  */
-			if (idata & ~IOC_TB_ENA_TEN) {
-				fatal("TODO: LCA_IOC_TB_ENA value "
-				    " (0x%" PRIx64") has unimplemented "
-				    "bits.\n", (uint64_t)idata);
-				exit(1);
-			}
-		}
-		break;
-
-	case LCA_IOC_W_BASE0:
-		if (writeflag == MEM_READ) {
-			odata = d->window_base_0;
-		} else {
-			d->window_base_0 = idata;
-			/*  TODO: Actually implement this.  */
-			if (idata != 0ULL && idata != 0x300800000ULL) {
-				fatal("TODO: LCA_IOC_W_BASE0 value differs"
-				    " (0x%" PRIx64") from the only implemented"
-				    " values\n", (uint64_t)idata);
-				exit(1);
-			}
-		}
-		break;
-
-	case LCA_IOC_W_MASK0:
-		if (writeflag == MEM_READ) {
-			odata = d->window_mask_0;
-		} else {
-			d->window_mask_0 = idata;
-			/*  TODO: Actually implement this.  */
-			if (idata != 0x700000ULL) {
-				fatal("TODO: LCA_IOC_W_MASK0 value differs"
-				    " (0x%" PRIx64") from the only implemented"
-				    " value\n", (uint64_t)idata);
-				exit(1);
-			}
-		}
-		break;
-
-	case LCA_IOC_W_T_BASE0:
-		if (writeflag == MEM_READ) {
-			odata = d->window_t_base_0;
-		} else {
-			d->window_t_base_0 = idata;
-			/*  TODO: Actually implement this.  */
-		}
-		break;
-
-	case LCA_IOC_W_BASE1:
-		if (writeflag == MEM_READ) {
-			odata = d->window_base_1;
-		} else {
-			d->window_base_1 = idata;
-			/*  TODO: Actually implement this.  */
-			if (idata != 0x240000000ULL) {
-				fatal("TODO: LCA_IOC_W_BASE1 value differs"
-				    " (0x%" PRIx64") from the only implemented"
-				    " value\n", (uint64_t)idata);
-				exit(1);
-			}
-		}
-		break;
-
-	case LCA_IOC_W_MASK1:
-		if (writeflag == MEM_READ) {
-			odata = d->window_mask_1;
-		} else {
-			d->window_mask_1 = idata;
-			/*  TODO: Actually implement this.  */
-			if (idata != 0x3ff00000ULL) {
-				fatal("TODO: LCA_IOC_W_MASK1 value differs"
-				    " (0x%" PRIx64") from the only implemented"
-				    " value\n", (uint64_t)idata);
-				exit(1);
-			}
-		}
-		break;
-
-	case LCA_IOC_W_T_BASE1:
-		if (writeflag == MEM_READ) {
-			odata = d->window_t_base_1;
-		} else {
-			d->window_t_base_1 = idata;
-			/*  TODO: Actually implement this.  */
-		}
-		break;
-
-	default:fatal("[ lca_ioc: unimplemented %s to offset 0x%x",
-		    writeflag == MEM_WRITE? "write" : "read", (int)
-		    relative_addr);
-		if (writeflag == MEM_WRITE)
-			fatal(": 0x%x", (int)idata);
-		fatal(" ]\n");
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(lca)
-{
-	char *interrupt_path;
-	struct interrupt interrupt_template;
-	struct lca_data *d;
-
-	CHECK_ALLOCATION(d = (struct lca_data *) malloc(sizeof(struct lca_data)));
-	memset(d, 0, sizeof(struct lca_data));
-
-	/*  Register a PCI bus:  */
-	d->pci_data = bus_pci_init(
-	    devinit->machine,
-	    "TODO: irq"		/*  pciirq: TODO  */,
-	    LCA_PCI_SIO,	/*  pci device io offset  */
-	    0x00000000,		/*  pci device mem offset: TODO  */
-	    0x00000000,		/*  PCI portbase: TODO  */
-	    0x00000000,		/*  PCI membase: TODO  */
-	    "TODO: pci irq base",	/*  PCI irqbase: TODO  */
-	    LCA_ISA_BASE,	/*  ISA portbase  */
-	    LCA_ISA_MEMBASE,	/*  ISA membase  */
-	    "TODO: irqbase isa");                /*  ISA irqbase: TODO  */
-
-	/*  Add the "sio0" controller (as seen by NetBSD):  */
-	bus_pci_add(devinit->machine, d->pci_data, devinit->machine->memory,
-	    0, 7, 0, "i82378zb");
-
-	memory_device_register(devinit->machine->memory, "lca_pci_conf",
-	    LCA_PCI_CONF, 0x20000000, dev_lca_pci_conf_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	memory_device_register(devinit->machine->memory, "lca_isa",
-	    LCA_PCI_SIO, 0x10000 << 5, dev_lca_isa_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	memory_device_register(devinit->machine->memory, "lca_ioc",
-	    LCA_IOC_BASE, 0x20000000, dev_lca_ioc_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	CHECK_ALLOCATION(interrupt_path = (char *)
-	    malloc(strlen(devinit->machine->path) + 10));
-	snprintf(interrupt_path, strlen(devinit->machine->path) + 10,
-	    "%s.lca", devinit->machine->path);
-
-	memset(&interrupt_template, 0, sizeof(interrupt_template));
-	interrupt_template.line = 0;
-	interrupt_template.name = interrupt_path;
-	interrupt_template.extra = d;
-	interrupt_template.interrupt_assert = lca_interrupt_assert;
-	interrupt_template.interrupt_deassert = lca_interrupt_deassert;
-	interrupt_handler_register(&interrupt_template);
-
-	bus_isa_init(devinit->machine, interrupt_path,
-	    BUS_ISA_IDE0 | BUS_ISA_IDE1, LCA_ISA_BASE, LCA_ISA_MEMBASE);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_le.c gxemul-0.7.0+dfsg/src/devices/dev_le.c
--- gxemul-0.6.2/src/devices/dev_le.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_le.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,927 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: LANCE ethernet, as used in DECstations
+ *
+ *  This is based on "PMAD-AA TURBOchannel Ethernet Module Functional
+ *  Specification". I've tried to keep symbol names in this file to what
+ *  the specs use.
+ *
+ *  This is what the memory layout looks like on a DECstation 5000/200:
+ *
+ *	0x000000 - 0x0fffff	Ethernet SRAM buffer  (should be 128KB)
+ *	0x100000 - 0x17ffff	LANCE registers
+ *	0x1c0000 - 0x1fffff	Ethernet Diagnostic ROM and Station
+ *				Address ROM
+ *
+ *  The length of the device is set to 0x1c0200, however, because Sprite
+ *  tries to read TURBOchannel rom data from 0x1c03f0, and that is provided
+ *  by the turbochannel device, not this device.
+ *
+ *
+ *  TODO:  Error conditions (such as when there are not enough receive
+ *	   buffers) are not emulated yet.
+ *
+ *	   (Old bug, but probably still valid:  "UDP packets that are too 
+ *	   large are not handled well by the Lance device.")
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "devices.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "net.h"
+
+#include "thirdparty/if_lereg.h"
+
+
+#define	LE_TICK_SHIFT		14
+
+
+extern int quiet_mode;
+
+#define	LE_MODE_PROM		0x8000
+#define	LE_MODE_LOOP		0x0004
+#define	LE_MODE_DTX		0x0002
+#define	LE_MODE_DRX		0x0001
+
+
+#define	N_REGISTERS		4
+#define	SRAM_SIZE		(128*1024)
+#define	ROM_SIZE		32
+
+
+struct le_data {
+	struct nic_data	nic;
+
+	int		subsys;		/*  for debugmsg  */
+
+	struct interrupt irq;
+	int		irq_asserted;
+
+	uint64_t	buf_start;
+	uint64_t	buf_end;
+	int		len;
+
+	uint8_t		rom[ROM_SIZE];
+
+	int		reg_select;
+	uint16_t	reg[N_REGISTERS];
+
+	int		is_bigendian;
+
+	unsigned char	*sram;
+
+	/*  Initialization block:  */
+	uint32_t	init_block_addr;
+
+	uint16_t	mode;
+	uint16_t	ladrf[4];
+	uint32_t	rdra;	/*  receive descriptor ring address  */
+	int		rlen;	/*  nr of rx descriptors  */
+	uint32_t	tdra;	/*  transmit descriptor ring address  */
+	int		tlen;	/*  nr ot tx descriptors  */
+
+	int		allmulti;/* receive all multicast packets */
+
+	/*  Current rx and tx descriptor indices:  */
+	int		rxp;
+	int		txp;
+
+	unsigned char	*tx_packet;
+	int		tx_packet_len;
+
+	unsigned char	*rx_packet;
+	int		rx_packet_len;
+	int		rx_packet_offset;
+	int		rx_middle_bit;
+};
+
+
+/*
+ *  le_read_16bit():
+ *
+ *  Read a 16-bit word from the SRAM.
+ */
+static uint64_t le_read_16bit(struct le_data *d, int addr)
+{
+	if (d->is_bigendian)
+		return (d->sram[addr & (SRAM_SIZE-1)] << 8) +
+			(d->sram[(addr+1) & (SRAM_SIZE-1)]);
+
+	return d->sram[addr & (SRAM_SIZE-1)] +
+	       (d->sram[(addr+1) & (SRAM_SIZE-1)] << 8);
+}
+
+
+/*
+ *  le_write_16bit():
+ *
+ *  Write a 16-bit word to the SRAM.
+ */
+static void le_write_16bit(struct le_data *d, int addr, uint16_t x)
+{
+	if (d->is_bigendian)
+	{
+		d->sram[addr & (SRAM_SIZE-1)] = (x >> 8) & 0xff;
+		d->sram[(addr+1) & (SRAM_SIZE-1)] = x & 0xff;
+	}
+	else
+	{
+		d->sram[addr & (SRAM_SIZE-1)] = x & 0xff;
+		d->sram[(addr+1) & (SRAM_SIZE-1)] = (x >> 8) & 0xff;
+	}
+
+}
+
+
+/*
+ *  le_chip_init():
+ *
+ *  Initialize data structures by reading an 'initialization block' from the
+ *  SRAM.
+ */
+static void le_chip_init(struct le_data *d)
+{
+	uint16_t tmp;
+	uint8_t macaddr[6];
+
+	d->init_block_addr = (d->reg[1] & 0xffff) + ((d->reg[2] & 0xff) << 16);
+	if (d->init_block_addr & 1)
+		debugmsg(d->subsys, "initialization block", VERBOSITY_WARNING,
+		    "WARNING! address not word aligned?");
+
+	debugmsg(d->subsys, "initialization block", VERBOSITY_DEBUG,
+	    "init_block_addr = 0x%06x", d->init_block_addr);
+
+	d->mode = le_read_16bit(d, d->init_block_addr + 0);
+
+	/*
+	 * The MAC address is packed into the PADR field as 3 little-endian
+	 * 16-bit words.
+	 */
+	tmp = le_read_16bit(d, d->init_block_addr + 2);
+	macaddr[0] = (uint8_t)(tmp);
+	macaddr[1] = (uint8_t)(tmp >> 8);
+	tmp = le_read_16bit(d, d->init_block_addr + 4);
+	macaddr[2] = (uint8_t)(tmp);
+	macaddr[3] = (uint8_t)(tmp >> 8);
+	tmp = le_read_16bit(d, d->init_block_addr + 6);
+	macaddr[4] = (uint8_t)(tmp);
+	macaddr[5] = (uint8_t)(tmp >> 8);
+	memcpy(d->nic.mac_address, macaddr, sizeof(d->nic.mac_address));
+
+	/*
+	 * The muticast address filter is packed into the LADRF field
+	 * as 4 little-endian 16-bit words.
+	 */
+	d->ladrf[0] = le_read_16bit(d, d->init_block_addr + 8);
+	d->ladrf[1] = le_read_16bit(d, d->init_block_addr + 10);
+	d->ladrf[2] = le_read_16bit(d, d->init_block_addr + 12);
+	d->ladrf[3] = le_read_16bit(d, d->init_block_addr + 14);
+	if (d->ladrf[0] == 0xffff && d->ladrf[1] == 0xffff &&
+	    d->ladrf[2] == 0xffff && d->ladrf[3] == 0xffff)
+		d->allmulti = 1;
+	else
+		d->allmulti = 0;
+
+	d->rdra = le_read_16bit(d, d->init_block_addr + 16);
+	d->rdra += ((le_read_16bit(d, d->init_block_addr + 18) & 0xff) << 16);
+	d->rlen = 1 << ((le_read_16bit(d, d->init_block_addr + 18) >> 13) & 7);
+	d->tdra = le_read_16bit(d, d->init_block_addr + 20);
+	d->tdra += ((le_read_16bit(d, d->init_block_addr + 22) & 0xff) << 16);
+	d->tlen = 1 << ((le_read_16bit(d, d->init_block_addr + 22) >> 13) & 7);
+
+	debug("[ le: DEBUG: mode                 %04x ]\n", d->mode);
+	debug("[ le: DEBUG: padr    %02x:%02x:%02x:%02x:%02x:%02x ]\n",
+	      macaddr[0], macaddr[1], macaddr[2],
+	      macaddr[3], macaddr[4], macaddr[5]);
+	debug("[ le: DEBUG: ladrf %04x:%04x:%04x:%04x ]\n",
+	      d->ladrf[0], d->ladrf[1], d->ladrf[2], d->ladrf[3]);
+	debug("[ le: DEBUG: rdra               %06llx ]\n", d->rdra);
+	debug("[ le: DEBUG: rlen                  %3i ]\n", d->rlen);
+	debug("[ le: DEBUG: tdra               %06llx ]\n", d->tdra);
+	debug("[ le: DEBUG: tlen                  %3i ]\n", d->tlen);
+
+	/*  Set TXON and RXON, unless they are disabled by 'mode':  */
+	if (d->mode & LE_MODE_DTX)
+		d->reg[0] &= ~LE_TXON;
+	else
+		d->reg[0] |= LE_TXON;
+
+	if (d->mode & LE_MODE_DRX)
+		d->reg[0] &= ~LE_RXON;
+	else
+		d->reg[0] |= LE_RXON;
+
+	/*  Initialize promiscuous mode.  */
+	d->nic.promiscuous_mode = (d->mode & LE_MODE_PROM) ? 1 : 0;
+
+	/*  Go to the start of the descriptor rings:  */
+	d->rxp = d->txp = 0;
+
+	/*  Set IDON and reset the INIT bit when we are done.  */
+	d->reg[0] |= LE_IDON;
+	d->reg[0] &= ~LE_INIT;
+
+	/*  Free any old packets:  */
+	if (d->tx_packet != NULL)
+		free(d->tx_packet);
+	d->tx_packet = NULL;
+	d->tx_packet_len = 0;
+
+	if (d->rx_packet != NULL)
+		free(d->rx_packet);
+	d->rx_packet = NULL;
+	d->rx_packet_len = 0;
+	d->rx_packet_offset = 0;
+	d->rx_middle_bit = 0;
+}
+
+
+/*
+ *  le_tx():
+ *
+ *  Check the transmitter descriptor ring for buffers that are owned by the
+ *  Lance chip (that is, buffers that are to be transmitted).
+ *
+ *  This routine should only be called if TXON is enabled.
+ */
+static void le_tx(struct net *net, struct le_data *d)
+{
+	int start_txp = d->txp;
+	uint16_t tx_descr[4];
+	int stp, enp, cur_packet_offset;
+	size_t i;
+	uint32_t bufaddr, buflen;
+
+	/*  TODO: This is just a guess:  */
+	d->reg[0] &= ~LE_TDMD;
+
+	do {
+		/*  Load the 8 descriptor bytes:  */
+		tx_descr[0] = le_read_16bit(d, d->tdra + d->txp*8 + 0);
+		tx_descr[1] = le_read_16bit(d, d->tdra + d->txp*8 + 2);
+		tx_descr[2] = le_read_16bit(d, d->tdra + d->txp*8 + 4);
+		tx_descr[3] = le_read_16bit(d, d->tdra + d->txp*8 + 6);
+
+		bufaddr = tx_descr[0] + ((tx_descr[1] & 0xff) << 16);
+		stp = tx_descr[1] & LE_STP? 1 : 0;
+		enp = tx_descr[1] & LE_ENP? 1 : 0;
+		buflen = 4096 - (tx_descr[2] & 0xfff);
+
+		/*
+		 *  Check the OWN bit. If it is zero, then this buffer is
+		 *  not ready to be transmitted yet.  Also check the '1111'
+		 *  mark, and make sure that byte-count is reasonable.
+		 */
+		if (!(tx_descr[1] & LE_OWN))
+			return;
+		if ((tx_descr[2] & 0xf000) != 0xf000)
+			return;
+		if (buflen < 12 || buflen > 1900) {
+			debugmsg(d->subsys, "tx", VERBOSITY_WARNING, "buflen = %i", buflen);
+			return;
+		}
+
+		debugmsg(d->subsys, "tx", VERBOSITY_DEBUG,
+		    "descr %3i DUMP: 0x%04x 0x%04x 0x%04x 0x%04x "
+		    "=> addr=0x%06x, len=%i bytes, STP=%i ENP=%i", d->txp,
+		    tx_descr[0], tx_descr[1], tx_descr[2], tx_descr[3],
+		    bufaddr, buflen, stp, enp);
+
+		if (d->tx_packet == NULL && !stp) {
+			debugmsg(d->subsys, "tx", VERBOSITY_WARNING,
+			    "!stp but tx_packet == NULL");
+			return;
+		}
+
+		if (d->tx_packet != NULL && stp) {
+			debugmsg(d->subsys, "tx", VERBOSITY_WARNING,
+			    "stp but tx_packet != NULL");
+			free(d->tx_packet);
+			d->tx_packet = NULL;
+			d->tx_packet_len = 0;
+		}
+
+		/*  Where to write to in the tx_packet:  */
+		cur_packet_offset = d->tx_packet_len;
+
+		/*  Start of a new packet:  */
+		if (stp) {
+			d->tx_packet_len = buflen;
+			CHECK_ALLOCATION(d->tx_packet = (unsigned char *) malloc(buflen));
+		} else {
+			d->tx_packet_len += buflen;
+			CHECK_ALLOCATION(d->tx_packet = (unsigned char *)
+			    realloc(d->tx_packet, d->tx_packet_len));
+		}
+
+		/*  Copy data from SRAM into the tx packet:  */
+		for (i=0; i<buflen; i++) {
+			unsigned char ch;
+			ch = d->sram[(bufaddr + i) & (SRAM_SIZE-1)];
+			d->tx_packet[cur_packet_offset + i] = ch;
+		}
+
+		/*
+		 *  Is this the last buffer in a packet? Then transmit
+		 *  it, cause an interrupt, and free the memory used by
+		 *  the packet.
+		 */
+		if (enp) {
+			net_ethernet_tx(net, &d->nic, d->tx_packet,
+			    d->tx_packet_len);
+
+			free(d->tx_packet);
+			d->tx_packet = NULL;
+			d->tx_packet_len = 0;
+
+			d->reg[0] |= LE_TINT;
+		}
+
+		/*  Clear the OWN bit:  */
+		tx_descr[1] &= ~LE_OWN;
+
+		/*  Write back the descriptor to SRAM:  */
+		le_write_16bit(d, d->tdra + d->txp*8 + 2, tx_descr[1]);
+		le_write_16bit(d, d->tdra + d->txp*8 + 4, tx_descr[2]);
+		le_write_16bit(d, d->tdra + d->txp*8 + 6, tx_descr[3]);
+
+		/*  Go to the next descriptor:  */
+		d->txp ++;
+		if (d->txp >= d->tlen)
+			d->txp = 0;
+	} while (d->txp != start_txp);
+
+	/*  We are here if all descriptors were taken care of.  */
+	debugmsg(d->subsys, "tx", VERBOSITY_WARNING, "all descriptors used up?");
+}
+
+
+/*
+ *  le_rx():
+ *
+ *  This routine should only be called if RXON is enabled.
+ */
+static void le_rx(struct net *net, struct le_data *d)
+{
+	int start_rxp = d->rxp;
+	size_t i;
+	uint16_t rx_descr[4];
+	uint32_t bufaddr, buflen;
+
+	do {
+		if (d->rx_packet == NULL)
+			return;
+
+		/*  Load the 8 descriptor bytes:  */
+		rx_descr[0] = le_read_16bit(d, d->rdra + d->rxp*8 + 0);
+		rx_descr[1] = le_read_16bit(d, d->rdra + d->rxp*8 + 2);
+		rx_descr[2] = le_read_16bit(d, d->rdra + d->rxp*8 + 4);
+		rx_descr[3] = le_read_16bit(d, d->rdra + d->rxp*8 + 6);
+
+		bufaddr = rx_descr[0] + ((rx_descr[1] & 0xff) << 16);
+		buflen = 4096 - (rx_descr[2] & 0xfff);
+
+		/*
+		 *  Check the OWN bit. If it is zero, then this buffer is
+		 *  not ready to receive data yet.  Also check the '1111'
+		 *  mark, and make sure that byte-count is reasonable.
+		 */
+		if (!(rx_descr[1] & LE_OWN))
+			return;
+		if ((rx_descr[2] & 0xf000) != 0xf000)
+			return;
+		if (buflen < 12 || buflen > 1900) {
+			debugmsg(d->subsys, "rx", VERBOSITY_WARNING, "buflen = %i", buflen);
+			return;
+		}
+
+		debugmsg(d->subsys, "rx", VERBOSITY_DEBUG,
+		    "descr %3i DUMP: 0x%04x 0x%04x 0x%04x 0x%04x "
+		    "=> addr=0x%06x, len=%i bytes", d->rxp,
+		    rx_descr[0], rx_descr[1], rx_descr[2], rx_descr[3],
+		    bufaddr, buflen);
+
+		/*  Copy data from the packet into SRAM:  */
+		for (i=0; i<buflen; i++) {
+			if (d->rx_packet_offset+(ssize_t)i >= d->rx_packet_len)
+				break;
+			d->sram[(bufaddr + i) & (SRAM_SIZE-1)] =
+			    d->rx_packet[d->rx_packet_offset + i];
+		}
+
+		/*  Here, i is the number of bytes copied.  */
+		d->rx_packet_offset += i;
+
+		/*  Set the ENP bit if this was the end of a packet:  */
+		if (d->rx_packet_offset >= d->rx_packet_len) {
+			rx_descr[1] |= LE_ENP;
+
+			/*
+			 *  NOTE:  The Lance documentation that I have read
+			 *  says _NOTHING_ about the length being 4 more than
+			 *  the length of the data.  You can guess how
+			 *  surprised I was when I saw the following in
+			 *  NetBSD (dev/ic/am7990.c):
+			 *
+			 *	lance_read(sc, LE_RBUFADDR(sc, bix),
+			 *		(int)rmd.rmd3 - 4);
+			 */
+			rx_descr[3] &= ~0xfff;
+			rx_descr[3] |= d->rx_packet_len + 4;
+
+			free(d->rx_packet);
+			d->rx_packet = NULL;
+			d->rx_packet_len = 0;
+			d->rx_packet_offset = 0;
+			d->rx_middle_bit = 0;
+
+			d->reg[0] |= LE_RINT;
+		}
+
+		/*  Set the STP bit if this was the start of a packet:  */
+		if (!d->rx_middle_bit) {
+			rx_descr[1] |= LE_STP;
+
+			/*  Are we continuing on this packet?  */
+			if (d->rx_packet != NULL)
+				d->rx_middle_bit = 1;
+		}
+
+		/*  Clear the OWN bit:  */
+		rx_descr[1] &= ~LE_OWN;
+
+		/*  Write back the descriptor to SRAM:  */
+		le_write_16bit(d, d->rdra + d->rxp*8 + 2, rx_descr[1]);
+		le_write_16bit(d, d->rdra + d->rxp*8 + 4, rx_descr[2]);
+		le_write_16bit(d, d->rdra + d->rxp*8 + 6, rx_descr[3]);
+
+		/*  Go to the next descriptor:  */
+		d->rxp ++;
+		if (d->rxp >= d->rlen)
+			d->rxp = 0;
+	} while (d->rxp != start_rxp);
+
+	/*  We are here if all descriptors were taken care of.  */
+	debugmsg(d->subsys, "rx", VERBOSITY_WARNING, "all descriptors used up?");
+}
+
+
+/*
+ *  le_rx_drop_packet():
+ *
+ *  Implement the logic to determine if we should drop a packet
+ *  before passing it to the guest.  Returns 1 if the packet was
+ *  dropped.
+ */
+static int
+le_rx_drop_packet(struct net *net, struct le_data *d)
+{
+	/* Only implement filtering if using a tap device. */
+	if (net->tapdev == NULL)
+		return 0;
+
+	/*
+	 * The network layer has already checked for our MAC address
+	 * or promiscuous mode.  We just need to check the multicast
+	 * filter or broadcast.
+	 */
+
+	/* If the packet is not multicast, we know it should be received. */
+	if (! net_ether_multicast(d->rx_packet))
+		return 0;
+
+	/*
+	 * Optimization -- if the guest has set all of the filter
+	 * bits, then we can skip additional checks.
+	 */
+	if (d->allmulti)
+		return 0;
+
+	/* Check for broadcast. */
+	if (net_ether_broadcast(d->rx_packet))
+		return 0;
+
+	/*
+	 * Check the multicast address filter.  We pass the address
+	 * through the little-endian Ethernet CRC generator.  The
+	 * high-order 6 bits are the index into the 64-bit filter.
+	 * The upper 2 bits select the 16-bit filter word, and the
+	 * remaining 4 select the bit in the word.
+	 */
+	uint32_t crc = net_ether_crc32_le(d->rx_packet, 6);
+	crc >>= 26;
+	if (d->ladrf[crc >> 4] & (1 << (crc & 0xf)))
+		return 0;
+
+	/* Not for us; drop the packet. */
+	free(d->rx_packet);
+	d->rx_packet = NULL;
+	d->rx_packet_len = 0;
+
+	return 1;
+}
+
+
+/*
+ *  le_register_fix():
+ */
+static void le_register_fix(struct net *net, struct le_data *d)
+{
+	/*  Init with new Initialization block, if needed.  */
+	if (d->reg[0] & LE_INIT)
+		le_chip_init(d);
+
+	/*
+	 *  If the receiver is on:
+	 *  If there is a current rx_packet, try to receive it into the
+	 *  Lance buffers.  Then try to receive any additional packets.
+	 */
+	if (d->reg[0] & LE_RXON) {
+		do {
+			if (d->rx_packet != NULL)
+				/*  Try to receive the packet:  */
+				le_rx(net, d);
+
+			if (d->rx_packet != NULL)
+				/*  If the packet wasn't fully received, 
+				    then abort for now.  */
+				break;
+
+			if (d->rx_packet == NULL &&
+			    net_ethernet_rx_avail(net, &d->nic)) {
+				net_ethernet_rx(net, &d->nic,
+				    &d->rx_packet, &d->rx_packet_len);
+				if (le_rx_drop_packet(net, d))
+					continue;
+			}
+		} while (d->rx_packet != NULL);
+	}
+
+	/*  If the transmitter is on, check for outgoing buffers:  */
+	if (d->reg[0] & LE_TXON)
+		le_tx(net, d);
+
+	/*  SERR should be the OR of BABL, CERR, MISS, and MERR:  */
+	d->reg[0] &= ~LE_SERR;
+	if (d->reg[0] & (LE_BABL | LE_CERR | LE_MISS | LE_MERR))
+		d->reg[0] |= LE_SERR;
+
+	/*  INTR should be the OR of BABL, MISS, MERR, RINT, TINT, IDON:  */
+	d->reg[0] &= ~LE_INTR;
+	if (d->reg[0] & (LE_BABL | LE_MISS | LE_MERR | LE_RINT |
+	    LE_TINT | LE_IDON))
+		d->reg[0] |= LE_INTR;
+
+	/*  The MERR bit clears some bits:  */
+	if (d->reg[0] & LE_MERR)
+		d->reg[0] &= ~(LE_RXON | LE_TXON);
+
+	/*  The STOP bit clears a lot of stuff:  */
+#if 0
+	/*  According to the LANCE manual: (doesn't work with Ultrix)  */
+	if (d->reg[0] & LE_STOP)
+		d->reg[0] &= ~(LE_SERR | LE_BABL | LE_CERR | LE_MISS | LE_MERR
+		    | LE_RINT | LE_TINT | LE_IDON | LE_INTR | LE_INEA
+		    | LE_RXON | LE_TXON | LE_TDMD);
+#else
+	/*  Works with Ultrix:  */
+	if (d->reg[0] & LE_STOP)
+		d->reg[0] &= ~(LE_IDON);
+#endif
+}
+
+
+DEVICE_TICK(le)
+{
+	struct le_data *d = (struct le_data *) extra;
+	int new_assert;
+
+	le_register_fix(cpu->machine->emul->net, d);
+
+	new_assert = (d->reg[0] & LE_INTR) && (d->reg[0] & LE_INEA);
+
+	if (new_assert && !d->irq_asserted)
+		INTERRUPT_ASSERT(d->irq);
+	if (d->irq_asserted && !new_assert)
+		INTERRUPT_DEASSERT(d->irq);
+
+	d->irq_asserted = new_assert;
+}
+
+
+/*
+ *  le_register_write():
+ *
+ *  This function is called when the value 'x' is written to register 'r'.
+ */
+void le_register_write(struct le_data *d, int r, uint32_t x)
+{
+	switch (r) {
+	case 0:	/*  CSR0:  */
+		/*  Some bits are write-one-to-clear:  */
+		if (x & LE_BABL)
+			d->reg[r] &= ~LE_BABL;
+		if (x & LE_CERR)
+			d->reg[r] &= ~LE_CERR;
+		if (x & LE_MISS)
+			d->reg[r] &= ~LE_MISS;
+		if (x & LE_MERR)
+			d->reg[r] &= ~LE_MERR;
+		if (x & LE_RINT)
+			d->reg[r] &= ~LE_RINT;
+		if (x & LE_TINT)
+			d->reg[r] &= ~LE_TINT;
+		if (x & LE_IDON)
+			d->reg[r] &= ~LE_IDON;
+
+		/*  Some bits are write-only settable, not clearable:  */
+		if (x & LE_TDMD)
+			d->reg[r] |= LE_TDMD;
+		if (x & LE_STRT) {
+			d->reg[r] |= LE_STRT;
+			d->reg[r] &= ~LE_STOP;
+		}
+		if (x & LE_INIT) {
+			if (!(d->reg[r] & LE_STOP))
+				debugmsg(d->subsys, "register write", VERBOSITY_WARNING,
+				    "attempt to INIT before STOPped!");
+			d->reg[r] |= LE_INIT;
+			d->reg[r] &= ~LE_STOP;
+		}
+		if (x & LE_STOP) {
+			d->reg[r] |= LE_STOP;
+			/*  STOP takes precedence over STRT and INIT:  */
+			d->reg[r] &= ~(LE_STRT | LE_INIT);
+		}
+
+		/*  Some bits get through, both settable and clearable:  */
+		d->reg[r] &= ~LE_INEA;
+		d->reg[r] |= (x & LE_INEA);
+		break;
+
+	default:
+		/*  CSR1, CSR2, and CSR3:  */
+		d->reg[r] = x;
+	}
+}
+
+
+DEVICE_ACCESS(le_sram)
+{
+	struct le_data *d = (struct le_data *) extra;
+	size_t i;
+	int retval;
+
+#ifdef LE_DEBUG
+	if (writeflag == MEM_WRITE) {
+		fatal("[ le_sram: write to addr 0x%06x: ", (int)relative_addr);
+		for (i=0; i<len; i++)
+			fatal("%02x ", data[i]);
+		fatal("]\n");
+	}
+#endif
+
+	/*  Read/write of the SRAM:  */
+	if (relative_addr < SRAM_SIZE && relative_addr + len <= SRAM_SIZE) {
+		if (writeflag == MEM_READ) {
+			memcpy(data, d->sram + relative_addr, len);
+			if (!quiet_mode) {
+				debug("[ le: read from SRAM offset 0x%05x:",
+				    relative_addr);
+				for (i=0; i<len; i++)
+					debug(" %02x", data[i]);
+				debug(" ]\n");
+			}
+			retval = 9;	/*  9 cycles  */
+		} else {
+			memcpy(d->sram + relative_addr, data, len);
+			if (!quiet_mode) {
+				debug("[ le: write to SRAM offset 0x%05x:",
+				    relative_addr);
+				for (i=0; i<len; i++)
+					debug(" %02x", data[i]);
+				debug(" ]\n");
+			}
+			retval = 6;	/*  6 cycles  */
+		}
+		return retval;
+	}
+
+	return 0;
+}
+
+
+DEVICE_ACCESS(le)
+{
+	struct le_data *d = (struct le_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int retval = 1;
+	size_t i;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+#ifdef LE_DEBUG
+	if (writeflag == MEM_WRITE) {
+		fatal("[ le: write to addr 0x%06x: ", (int)relative_addr);
+		for (i=0; i<len; i++)
+			fatal("%02x ", data[i]);
+		fatal("]\n");
+	}
+#endif
+
+	/*  Read from station's ROM (ethernet address):  */
+	if (relative_addr >= 0xc0000 && relative_addr <= 0xfffff) {
+		uint32_t a;
+		int j = (relative_addr & 0xff) / 4;
+		a = d->rom[j & (ROM_SIZE-1)];
+
+		if (writeflag == MEM_READ) {
+			odata = (a << 24) + (a << 16) + (a << 8) + a;
+		} else {
+			fatal("[ le: WRITE to ethernet addr (%08lx):",
+			    (long)relative_addr);
+			for (i=0; i<len; i++)
+				fatal(" %02x", data[i]);
+			fatal(" ]\n");
+		}
+
+		retval = 13;	/*  13 cycles  */
+		goto do_return;
+	}
+
+
+	switch (relative_addr) {
+
+	/*  Register read/write:  */
+	case 0:
+		if (writeflag==MEM_READ) {
+			odata = d->reg[d->reg_select];
+			debugmsg(d->subsys, "register", VERBOSITY_DEBUG,
+			    "READ from register 0x%02x: 0x"
+			    "%02x", d->reg_select, (int)odata);
+
+			/*
+			 *  A read from csr1..3 should return "undefined"
+			 *  result if the stop bit is set.  However, Ultrix
+			 *  seems to do just that, so let's _not_ print
+			 *  a warning here.
+			 */
+		} else {
+			debugmsg(d->subsys, "register", VERBOSITY_DEBUG,
+			    "WRITE to register 0x%02x: 0x%02x",
+			    d->reg_select, (int)idata);
+			/*
+			 *  A write to from csr1..3 when the stop bit is
+			 *  set should be ignored. However, Ultrix writes
+			 *  even if the stop bit is set, so let's _not_
+			 *  print a warning about it.
+			 */
+			le_register_write(d, d->reg_select, idata);
+		}
+		break;
+
+	/*  Register select:  */
+	case 4:
+		if (writeflag==MEM_READ) {
+			odata = d->reg_select;
+			debugmsg(d->subsys, "register select", VERBOSITY_DEBUG,
+			    "READ: 0x%02x", (int)odata);
+		} else {
+			debugmsg(d->subsys, "register select", VERBOSITY_DEBUG,
+			     "WRITE: 0x%02x", (int)idata);
+			d->reg_select = idata & (N_REGISTERS - 1);
+
+			if (idata >= N_REGISTERS)
+				debugmsg(d->subsys, "register select", VERBOSITY_WARNING,
+				    "WARNING! register %i (max is %i)",
+				    idata, N_REGISTERS - 1);
+		}
+		break;
+
+	default:
+		if (writeflag==MEM_READ) {
+			debugmsg(d->subsys, "access", VERBOSITY_WARNING,
+			    "read from UNIMPLEMENTED addr 0x%06x",
+			    (int)relative_addr);
+		} else {
+			debugmsg(d->subsys, "access", VERBOSITY_WARNING,
+			    "write to UNIMPLEMENTED addr 0x%06x: "
+			    "0x%08x", (int)relative_addr, (int)idata);
+		}
+	}
+
+do_return:
+	if (writeflag == MEM_READ) {
+		memory_writemax64(cpu, data, len, odata);
+		debugmsg(d->subsys, "access", VERBOSITY_DEBUG,
+		    "read from addr 0x%06x: 0x%08x", relative_addr, odata);
+	}
+
+	dev_le_tick(cpu, extra);
+
+	return retval;
+}
+
+
+/*
+ *  dev_le_init():
+ */
+void dev_le_init(struct machine *machine, struct memory *mem, uint64_t baseaddr,
+	uint64_t buf_start, uint64_t buf_end, const char *irq_path, int len)
+{
+	char *name2;
+	size_t nlen = 55;
+	struct le_data *d;
+
+	CHECK_ALLOCATION(d = (struct le_data *) malloc(sizeof(struct le_data)));
+	memset(d, 0, sizeof(struct le_data));
+
+	d->subsys = debugmsg_register_subsystem("le");
+
+	d->is_bigendian = machine->cpus[0]->byte_order == EMUL_BIG_ENDIAN;
+
+	INTERRUPT_CONNECT(irq_path, d->irq);
+
+	CHECK_ALLOCATION(d->sram = (unsigned char *) malloc(SRAM_SIZE));
+	memset(d->sram, 0, SRAM_SIZE);
+
+	/*  TODO:  Are these actually used yet?  */
+	d->len       = len;
+	d->buf_start = buf_start;
+	d->buf_end   = buf_end;
+
+	/*  Initial register contents:  */
+	d->reg[0] = LE_STOP;
+
+	d->tx_packet = NULL;
+	d->rx_packet = NULL;
+
+	/*  ROM (including the MAC address):  */
+	net_generate_unique_mac(machine, &d->rom[0]);
+
+	/*  Copies of the MAC address and a test pattern:  */
+	d->rom[10] = d->rom[21] = d->rom[5];
+	d->rom[11] = d->rom[20] = d->rom[4];
+	d->rom[12] = d->rom[19] = d->rom[3];
+	d->rom[7] =  d->rom[8]  = d->rom[23] =
+		     d->rom[13] = d->rom[18] = d->rom[2];
+	d->rom[6] =  d->rom[9]  = d->rom[22] =
+		     d->rom[14] = d->rom[17] = d->rom[1];
+	d->rom[15] = d->rom[16] = d->rom[0];
+	d->rom[24] = d->rom[28] = 0xff;
+	d->rom[25] = d->rom[29] = 0x00;
+	d->rom[26] = d->rom[30] = 0x55;
+	d->rom[27] = d->rom[31] = 0xaa;
+
+	memory_device_register(mem, "le_sram", baseaddr,
+	    SRAM_SIZE, dev_le_sram_access, (void *)d,
+	    DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK
+	    | DM_READS_HAVE_NO_SIDE_EFFECTS, d->sram);
+
+	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
+	snprintf(name2, nlen, "le [%02x:%02x:%02x:%02x:%02x:%02x]",
+	    d->rom[0], d->rom[1], d->rom[2], d->rom[3], d->rom[4], d->rom[5]);
+
+	memory_device_register(mem, name2, baseaddr + 0x100000,
+	    len - 0x100000, dev_le_access, (void *)d, DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(machine, dev_le_tick, d, LE_TICK_SHIFT);
+
+	memcpy(d->nic.mac_address, &d->rom[0], sizeof(d->nic.mac_address));
+	net_add_nic(machine->emul->net, &d->nic);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_le.cc gxemul-0.7.0+dfsg/src/devices/dev_le.cc
--- gxemul-0.6.2/src/devices/dev_le.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_le.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,818 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: LANCE ethernet, as used in DECstations
- *
- *  This is based on "PMAD-AA TURBOchannel Ethernet Module Functional
- *  Specification". I've tried to keep symbol names in this file to what
- *  the specs use.
- *
- *  This is what the memory layout looks like on a DECstation 5000/200:
- *
- *	0x000000 - 0x0fffff	Ethernet SRAM buffer  (should be 128KB)
- *	0x100000 - 0x17ffff	LANCE registers
- *	0x1c0000 - 0x1fffff	Ethernet Diagnostic ROM and Station
- *				Address ROM
- *
- *  The length of the device is set to 0x1c0200, however, because Sprite
- *  tries to read TURBOchannel rom data from 0x1c03f0, and that is provided
- *  by the turbochannel device, not this device.
- *
- *
- *  TODO:  Error conditions (such as when there are not enough receive
- *	   buffers) are not emulated yet.
- *
- *	   (Old bug, but probably still valid:  "UDP packets that are too 
- *	   large are not handled well by the Lance device.")
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "devices.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "net.h"
-
-#include "thirdparty/if_lereg.h"
-
-
-#define	LE_TICK_SHIFT		14
-
-/*  #define LE_DEBUG  */
-/*  #define debug fatal  */
-
-extern int quiet_mode;
-
-#define	LE_MODE_LOOP		4
-#define	LE_MODE_DTX		2
-#define	LE_MODE_DRX		1
-
-
-#define	N_REGISTERS		4
-#define	SRAM_SIZE		(128*1024)
-#define	ROM_SIZE		32
-
-
-struct le_data {
-	struct interrupt irq;
-	int		irq_asserted;
-
-	uint64_t	buf_start;
-	uint64_t	buf_end;
-	int		len;
-
-	uint8_t		rom[ROM_SIZE];
-
-	int		reg_select;
-	uint16_t	reg[N_REGISTERS];
-
-	unsigned char	*sram;
-
-	/*  Initialization block:  */
-	uint32_t	init_block_addr;
-
-	uint16_t	mode;
-	uint64_t	padr;	/*  MAC address  */
-	uint64_t	ladrf;
-	uint32_t	rdra;	/*  receive descriptor ring address  */
-	int		rlen;	/*  nr of rx descriptors  */
-	uint32_t	tdra;	/*  transmit descriptor ring address  */
-	int		tlen;	/*  nr ot tx descriptors  */
-
-	/*  Current rx and tx descriptor indices:  */
-	int		rxp;
-	int		txp;
-
-	unsigned char	*tx_packet;
-	int		tx_packet_len;
-
-	unsigned char	*rx_packet;
-	int		rx_packet_len;
-	int		rx_packet_offset;
-	int		rx_middle_bit;
-};
-
-
-/*
- *  le_read_16bit():
- *
- *  Read a 16-bit word from the SRAM.
- */
-static uint64_t le_read_16bit(struct le_data *d, int addr)
-{
-	/*  TODO: This is for little endian only  */
-	int x = d->sram[addr & (SRAM_SIZE-1)] +
-	       (d->sram[(addr+1) & (SRAM_SIZE-1)] << 8);
-	return x;
-}
-
-
-/*
- *  le_write_16bit():
- *
- *  Write a 16-bit word to the SRAM.
- */
-static void le_write_16bit(struct le_data *d, int addr, uint16_t x)
-{
-	/*  TODO: This is for little endian only  */
-	d->sram[addr & (SRAM_SIZE-1)] = x & 0xff;
-	d->sram[(addr+1) & (SRAM_SIZE-1)] = (x >> 8) & 0xff;
-}
-
-
-/*
- *  le_chip_init():
- *
- *  Initialize data structures by reading an 'initialization block' from the
- *  SRAM.
- */
-static void le_chip_init(struct le_data *d)
-{
-	d->init_block_addr = (d->reg[1] & 0xffff) + ((d->reg[2] & 0xff) << 16);
-	if (d->init_block_addr & 1)
-		fatal("[ le: WARNING! initialization block address "
-		    "not word aligned? ]\n");
-
-	debug("[ le: d->init_block_addr = 0x%06x ]\n", d->init_block_addr);
-
-	d->mode = le_read_16bit(d, d->init_block_addr + 0);
-	d->padr = le_read_16bit(d, d->init_block_addr + 2);
-	d->padr += (le_read_16bit(d, d->init_block_addr + 4) << 16);
-	d->padr += (le_read_16bit(d, d->init_block_addr + 6) << 32);
-	d->ladrf = le_read_16bit(d, d->init_block_addr + 8);
-	d->ladrf += (le_read_16bit(d, d->init_block_addr + 10) << 16);
-	d->ladrf += (le_read_16bit(d, d->init_block_addr + 12) << 32);
-	d->ladrf += (le_read_16bit(d, d->init_block_addr + 14) << 48);
-	d->rdra = le_read_16bit(d, d->init_block_addr + 16);
-	d->rdra += ((le_read_16bit(d, d->init_block_addr + 18) & 0xff) << 16);
-	d->rlen = 1 << ((le_read_16bit(d, d->init_block_addr + 18) >> 13) & 7);
-	d->tdra = le_read_16bit(d, d->init_block_addr + 20);
-	d->tdra += ((le_read_16bit(d, d->init_block_addr + 22) & 0xff) << 16);
-	d->tlen = 1 << ((le_read_16bit(d, d->init_block_addr + 22) >> 13) & 7);
-
-	debug("[ le: DEBUG: mode              %04x ]\n", d->mode);
-	debug("[ le: DEBUG: padr  %016llx ]\n", (long long)d->padr);
-	debug("[ le: DEBUG: ladrf %016llx ]\n", (long long)d->ladrf);
-	debug("[ le: DEBUG: rdra            %06llx ]\n", d->rdra);
-	debug("[ le: DEBUG: rlen               %3i ]\n", d->rlen);
-	debug("[ le: DEBUG: tdra            %06llx ]\n", d->tdra);
-	debug("[ le: DEBUG: tlen               %3i ]\n", d->tlen);
-
-	/*  Set TXON and RXON, unless they are disabled by 'mode':  */
-	if (d->mode & LE_MODE_DTX)
-		d->reg[0] &= ~LE_TXON;
-	else
-		d->reg[0] |= LE_TXON;
-
-	if (d->mode & LE_MODE_DRX)
-		d->reg[0] &= ~LE_RXON;
-	else
-		d->reg[0] |= LE_RXON;
-
-	/*  Go to the start of the descriptor rings:  */
-	d->rxp = d->txp = 0;
-
-	/*  Set IDON and reset the INIT bit when we are done.  */
-	d->reg[0] |= LE_IDON;
-	d->reg[0] &= ~LE_INIT;
-
-	/*  Free any old packets:  */
-	if (d->tx_packet != NULL)
-		free(d->tx_packet);
-	d->tx_packet = NULL;
-	d->tx_packet_len = 0;
-
-	if (d->rx_packet != NULL)
-		free(d->rx_packet);
-	d->rx_packet = NULL;
-	d->rx_packet_len = 0;
-	d->rx_packet_offset = 0;
-	d->rx_middle_bit = 0;
-}
-
-
-/*
- *  le_tx():
- *
- *  Check the transmitter descriptor ring for buffers that are owned by the
- *  Lance chip (that is, buffers that are to be transmitted).
- *
- *  This routine should only be called if TXON is enabled.
- */
-static void le_tx(struct net *net, struct le_data *d)
-{
-	int start_txp = d->txp;
-	uint16_t tx_descr[4];
-	int stp, enp, cur_packet_offset;
-	size_t i;
-	uint32_t bufaddr, buflen;
-
-	/*  TODO: This is just a guess:  */
-	d->reg[0] &= ~LE_TDMD;
-
-	do {
-		/*  Load the 8 descriptor bytes:  */
-		tx_descr[0] = le_read_16bit(d, d->tdra + d->txp*8 + 0);
-		tx_descr[1] = le_read_16bit(d, d->tdra + d->txp*8 + 2);
-		tx_descr[2] = le_read_16bit(d, d->tdra + d->txp*8 + 4);
-		tx_descr[3] = le_read_16bit(d, d->tdra + d->txp*8 + 6);
-
-		bufaddr = tx_descr[0] + ((tx_descr[1] & 0xff) << 16);
-		stp = tx_descr[1] & LE_STP? 1 : 0;
-		enp = tx_descr[1] & LE_ENP? 1 : 0;
-		buflen = 4096 - (tx_descr[2] & 0xfff);
-
-		/*
-		 *  Check the OWN bit. If it is zero, then this buffer is
-		 *  not ready to be transmitted yet.  Also check the '1111'
-		 *  mark, and make sure that byte-count is reasonable.
-		 */
-		if (!(tx_descr[1] & LE_OWN))
-			return;
-		if ((tx_descr[2] & 0xf000) != 0xf000)
-			return;
-		if (buflen < 12 || buflen > 1900) {
-			fatal("[ le_tx(): buflen = %i ]\n", buflen);
-			return;
-		}
-
-		debug("[ le_tx(): descr %3i DUMP: 0x%04x 0x%04x 0x%04x 0x%04x "
-		    "=> addr=0x%06x, len=%i bytes, STP=%i ENP=%i ]\n", d->txp,
-		    tx_descr[0], tx_descr[1], tx_descr[2], tx_descr[3],
-		    bufaddr, buflen, stp, enp);
-
-		if (d->tx_packet == NULL && !stp) {
-			fatal("[ le_tx(): !stp but tx_packet == NULL ]\n");
-			return;
-		}
-
-		if (d->tx_packet != NULL && stp) {
-			fatal("[ le_tx(): stp but tx_packet != NULL ]\n");
-			free(d->tx_packet);
-			d->tx_packet = NULL;
-			d->tx_packet_len = 0;
-		}
-
-		/*  Where to write to in the tx_packet:  */
-		cur_packet_offset = d->tx_packet_len;
-
-		/*  Start of a new packet:  */
-		if (stp) {
-			d->tx_packet_len = buflen;
-			CHECK_ALLOCATION(d->tx_packet = (unsigned char *) malloc(buflen));
-		} else {
-			d->tx_packet_len += buflen;
-			CHECK_ALLOCATION(d->tx_packet = (unsigned char *)
-			    realloc(d->tx_packet, d->tx_packet_len));
-		}
-
-		/*  Copy data from SRAM into the tx packet:  */
-		for (i=0; i<buflen; i++) {
-			unsigned char ch;
-			ch = d->sram[(bufaddr + i) & (SRAM_SIZE-1)];
-			d->tx_packet[cur_packet_offset + i] = ch;
-		}
-
-		/*
-		 *  Is this the last buffer in a packet? Then transmit
-		 *  it, cause an interrupt, and free the memory used by
-		 *  the packet.
-		 */
-		if (enp) {
-			net_ethernet_tx(net, d, d->tx_packet, d->tx_packet_len);
-
-			free(d->tx_packet);
-			d->tx_packet = NULL;
-			d->tx_packet_len = 0;
-
-			d->reg[0] |= LE_TINT;
-		}
-
-		/*  Clear the OWN bit:  */
-		tx_descr[1] &= ~LE_OWN;
-
-		/*  Write back the descriptor to SRAM:  */
-		le_write_16bit(d, d->tdra + d->txp*8 + 2, tx_descr[1]);
-		le_write_16bit(d, d->tdra + d->txp*8 + 4, tx_descr[2]);
-		le_write_16bit(d, d->tdra + d->txp*8 + 6, tx_descr[3]);
-
-		/*  Go to the next descriptor:  */
-		d->txp ++;
-		if (d->txp >= d->tlen)
-			d->txp = 0;
-	} while (d->txp != start_txp);
-
-	/*  We are here if all descriptors were taken care of.  */
-	fatal("[ le_tx(): all TX descriptors used up? ]\n");
-}
-
-
-/*
- *  le_rx():
- *
- *  This routine should only be called if RXON is enabled.
- */
-static void le_rx(struct net *net, struct le_data *d)
-{
-	int start_rxp = d->rxp;
-	size_t i;
-	uint16_t rx_descr[4];
-	uint32_t bufaddr, buflen;
-
-	do {
-		if (d->rx_packet == NULL)
-			return;
-
-		/*  Load the 8 descriptor bytes:  */
-		rx_descr[0] = le_read_16bit(d, d->rdra + d->rxp*8 + 0);
-		rx_descr[1] = le_read_16bit(d, d->rdra + d->rxp*8 + 2);
-		rx_descr[2] = le_read_16bit(d, d->rdra + d->rxp*8 + 4);
-		rx_descr[3] = le_read_16bit(d, d->rdra + d->rxp*8 + 6);
-
-		bufaddr = rx_descr[0] + ((rx_descr[1] & 0xff) << 16);
-		buflen = 4096 - (rx_descr[2] & 0xfff);
-
-		/*
-		 *  Check the OWN bit. If it is zero, then this buffer is
-		 *  not ready to receive data yet.  Also check the '1111'
-		 *  mark, and make sure that byte-count is reasonable.
-		 */
-		if (!(rx_descr[1] & LE_OWN))
-			return;
-		if ((rx_descr[2] & 0xf000) != 0xf000)
-			return;
-		if (buflen < 12 || buflen > 1900) {
-			fatal("[ le_rx(): buflen = %i ]\n", buflen);
-			return;
-		}
-
-		debug("[ le_rx(): descr %3i DUMP: 0x%04x 0x%04x 0x%04x 0x%04x "
-		    "=> addr=0x%06x, len=%i bytes ]\n", d->rxp,
-		    rx_descr[0], rx_descr[1], rx_descr[2], rx_descr[3],
-		    bufaddr, buflen);
-
-		/*  Copy data from the packet into SRAM:  */
-		for (i=0; i<buflen; i++) {
-			if (d->rx_packet_offset+(ssize_t)i >= d->rx_packet_len)
-				break;
-			d->sram[(bufaddr + i) & (SRAM_SIZE-1)] =
-			    d->rx_packet[d->rx_packet_offset + i];
-		}
-
-		/*  Here, i is the number of bytes copied.  */
-		d->rx_packet_offset += i;
-
-		/*  Set the ENP bit if this was the end of a packet:  */
-		if (d->rx_packet_offset >= d->rx_packet_len) {
-			rx_descr[1] |= LE_ENP;
-
-			/*
-			 *  NOTE:  The Lance documentation that I have read
-			 *  says _NOTHING_ about the length being 4 more than
-			 *  the length of the data.  You can guess how
-			 *  surprised I was when I saw the following in
-			 *  NetBSD (dev/ic/am7990.c):
-			 *
-			 *	lance_read(sc, LE_RBUFADDR(sc, bix),
-			 *		(int)rmd.rmd3 - 4);
-			 */
-			rx_descr[3] &= ~0xfff;
-			rx_descr[3] |= d->rx_packet_len + 4;
-
-			free(d->rx_packet);
-			d->rx_packet = NULL;
-			d->rx_packet_len = 0;
-			d->rx_packet_offset = 0;
-			d->rx_middle_bit = 0;
-
-			d->reg[0] |= LE_RINT;
-		}
-
-		/*  Set the STP bit if this was the start of a packet:  */
-		if (!d->rx_middle_bit) {
-			rx_descr[1] |= LE_STP;
-
-			/*  Are we continuing on this packet?  */
-			if (d->rx_packet != NULL)
-				d->rx_middle_bit = 1;
-		}
-
-		/*  Clear the OWN bit:  */
-		rx_descr[1] &= ~LE_OWN;
-
-		/*  Write back the descriptor to SRAM:  */
-		le_write_16bit(d, d->rdra + d->rxp*8 + 2, rx_descr[1]);
-		le_write_16bit(d, d->rdra + d->rxp*8 + 4, rx_descr[2]);
-		le_write_16bit(d, d->rdra + d->rxp*8 + 6, rx_descr[3]);
-
-		/*  Go to the next descriptor:  */
-		d->rxp ++;
-		if (d->rxp >= d->rlen)
-			d->rxp = 0;
-	} while (d->rxp != start_rxp);
-
-	/*  We are here if all descriptors were taken care of.  */
-	fatal("[ le_rx(): all RX descriptors used up? ]\n");
-}
-
-
-/*
- *  le_register_fix():
- */
-static void le_register_fix(struct net *net, struct le_data *d)
-{
-	/*  Init with new Initialization block, if needed.  */
-	if (d->reg[0] & LE_INIT)
-		le_chip_init(d);
-
-#ifdef LE_DEBUG
-	{
-		static int x = 1234;
-		if (x != d->reg[0]) {
-			debug("[ le reg[0] = 0x%04x ]\n", d->reg[0]);
-			x = d->reg[0];
-		}
-	}
-#endif
-
-	/*
-	 *  If the receiver is on:
-	 *  If there is a current rx_packet, try to receive it into the
-	 *  Lance buffers.  Then try to receive any additional packets.
-	 */
-	if (d->reg[0] & LE_RXON) {
-		do {
-			if (d->rx_packet != NULL)
-				/*  Try to receive the packet:  */
-				le_rx(net, d);
-
-			if (d->rx_packet != NULL)
-				/*  If the packet wasn't fully received, 
-				    then abort for now.  */
-				break;
-
-			if (d->rx_packet == NULL &&
-			    net_ethernet_rx_avail(net, d))
-				net_ethernet_rx(net, d,
-				    &d->rx_packet, &d->rx_packet_len);
-		} while (d->rx_packet != NULL);
-	}
-
-	/*  If the transmitter is on, check for outgoing buffers:  */
-	if (d->reg[0] & LE_TXON)
-		le_tx(net, d);
-
-	/*  SERR should be the OR of BABL, CERR, MISS, and MERR:  */
-	d->reg[0] &= ~LE_SERR;
-	if (d->reg[0] & (LE_BABL | LE_CERR | LE_MISS | LE_MERR))
-		d->reg[0] |= LE_SERR;
-
-	/*  INTR should be the OR of BABL, MISS, MERR, RINT, TINT, IDON:  */
-	d->reg[0] &= ~LE_INTR;
-	if (d->reg[0] & (LE_BABL | LE_MISS | LE_MERR | LE_RINT |
-	    LE_TINT | LE_IDON))
-		d->reg[0] |= LE_INTR;
-
-	/*  The MERR bit clears some bits:  */
-	if (d->reg[0] & LE_MERR)
-		d->reg[0] &= ~(LE_RXON | LE_TXON);
-
-	/*  The STOP bit clears a lot of stuff:  */
-#if 0
-	/*  According to the LANCE manual: (doesn't work with Ultrix)  */
-	if (d->reg[0] & LE_STOP)
-		d->reg[0] &= ~(LE_SERR | LE_BABL | LE_CERR | LE_MISS | LE_MERR
-		    | LE_RINT | LE_TINT | LE_IDON | LE_INTR | LE_INEA
-		    | LE_RXON | LE_TXON | LE_TDMD);
-#else
-	/*  Works with Ultrix:  */
-	if (d->reg[0] & LE_STOP)
-		d->reg[0] &= ~(LE_IDON);
-#endif
-}
-
-
-DEVICE_TICK(le)
-{
-	struct le_data *d = (struct le_data *) extra;
-	int new_assert;
-
-	le_register_fix(cpu->machine->emul->net, d);
-
-	new_assert = (d->reg[0] & LE_INTR) && (d->reg[0] & LE_INEA);
-
-	if (new_assert && !d->irq_asserted)
-		INTERRUPT_ASSERT(d->irq);
-	if (d->irq_asserted && !new_assert)
-		INTERRUPT_DEASSERT(d->irq);
-
-	d->irq_asserted = new_assert;
-}
-
-
-/*
- *  le_register_write():
- *
- *  This function is called when the value 'x' is written to register 'r'.
- */
-void le_register_write(struct le_data *d, int r, uint32_t x)
-{
-	switch (r) {
-	case 0:	/*  CSR0:  */
-		/*  Some bits are write-one-to-clear:  */
-		if (x & LE_BABL)
-			d->reg[r] &= ~LE_BABL;
-		if (x & LE_CERR)
-			d->reg[r] &= ~LE_CERR;
-		if (x & LE_MISS)
-			d->reg[r] &= ~LE_MISS;
-		if (x & LE_MERR)
-			d->reg[r] &= ~LE_MERR;
-		if (x & LE_RINT)
-			d->reg[r] &= ~LE_RINT;
-		if (x & LE_TINT)
-			d->reg[r] &= ~LE_TINT;
-		if (x & LE_IDON)
-			d->reg[r] &= ~LE_IDON;
-
-		/*  Some bits are write-only settable, not clearable:  */
-		if (x & LE_TDMD)
-			d->reg[r] |= LE_TDMD;
-		if (x & LE_STRT) {
-			d->reg[r] |= LE_STRT;
-			d->reg[r] &= ~LE_STOP;
-		}
-		if (x & LE_INIT) {
-			if (!(d->reg[r] & LE_STOP))
-				fatal("[ le: attempt to INIT before"
-				    " STOPped! ]\n");
-			d->reg[r] |= LE_INIT;
-			d->reg[r] &= ~LE_STOP;
-		}
-		if (x & LE_STOP) {
-			d->reg[r] |= LE_STOP;
-			/*  STOP takes precedence over STRT and INIT:  */
-			d->reg[r] &= ~(LE_STRT | LE_INIT);
-		}
-
-		/*  Some bits get through, both settable and clearable:  */
-		d->reg[r] &= ~LE_INEA;
-		d->reg[r] |= (x & LE_INEA);
-		break;
-
-	default:
-		/*  CSR1, CSR2, and CSR3:  */
-		d->reg[r] = x;
-	}
-}
-
-
-DEVICE_ACCESS(le_sram)
-{
-	struct le_data *d = (struct le_data *) extra;
-	size_t i;
-	int retval;
-
-#ifdef LE_DEBUG
-	if (writeflag == MEM_WRITE) {
-		fatal("[ le_sram: write to addr 0x%06x: ", (int)relative_addr);
-		for (i=0; i<len; i++)
-			fatal("%02x ", data[i]);
-		fatal("]\n");
-	}
-#endif
-
-	/*  Read/write of the SRAM:  */
-	if (relative_addr < SRAM_SIZE && relative_addr + len <= SRAM_SIZE) {
-		if (writeflag == MEM_READ) {
-			memcpy(data, d->sram + relative_addr, len);
-			if (!quiet_mode) {
-				debug("[ le: read from SRAM offset 0x%05x:",
-				    relative_addr);
-				for (i=0; i<len; i++)
-					debug(" %02x", data[i]);
-				debug(" ]\n");
-			}
-			retval = 9;	/*  9 cycles  */
-		} else {
-			memcpy(d->sram + relative_addr, data, len);
-			if (!quiet_mode) {
-				debug("[ le: write to SRAM offset 0x%05x:",
-				    relative_addr);
-				for (i=0; i<len; i++)
-					debug(" %02x", data[i]);
-				debug(" ]\n");
-			}
-			retval = 6;	/*  6 cycles  */
-		}
-		return retval;
-	}
-
-	return 0;
-}
-
-
-DEVICE_ACCESS(le)
-{
-	struct le_data *d = (struct le_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int retval = 1;
-	size_t i;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-#ifdef LE_DEBUG
-	if (writeflag == MEM_WRITE) {
-		fatal("[ le: write to addr 0x%06x: ", (int)relative_addr);
-		for (i=0; i<len; i++)
-			fatal("%02x ", data[i]);
-		fatal("]\n");
-	}
-#endif
-
-	/*  Read from station's ROM (ethernet address):  */
-	if (relative_addr >= 0xc0000 && relative_addr <= 0xfffff) {
-		uint32_t a;
-		int j = (relative_addr & 0xff) / 4;
-		a = d->rom[j & (ROM_SIZE-1)];
-
-		if (writeflag == MEM_READ) {
-			odata = (a << 24) + (a << 16) + (a << 8) + a;
-		} else {
-			fatal("[ le: WRITE to ethernet addr (%08lx):",
-			    (long)relative_addr);
-			for (i=0; i<len; i++)
-				fatal(" %02x", data[i]);
-			fatal(" ]\n");
-		}
-
-		retval = 13;	/*  13 cycles  */
-		goto do_return;
-	}
-
-
-	switch (relative_addr) {
-
-	/*  Register read/write:  */
-	case 0:
-		if (writeflag==MEM_READ) {
-			odata = d->reg[d->reg_select];
-			if (!quiet_mode)
-				debug("[ le: read from register 0x%02x: 0x"
-				    "%02x ]\n", d->reg_select, (int)odata);
-			/*
-			 *  A read from csr1..3 should return "undefined"
-			 *  result if the stop bit is set.  However, Ultrix
-			 *  seems to do just that, so let's _not_ print
-			 *  a warning here.
-			 */
-		} else {
-			if (!quiet_mode)
-				debug("[ le: write to register 0x%02x: 0x"
-				    "%02x ]\n", d->reg_select, (int)idata);
-			/*
-			 *  A write to from csr1..3 when the stop bit is
-			 *  set should be ignored. However, Ultrix writes
-			 *  even if the stop bit is set, so let's _not_
-			 *  print a warning about it.
-			 */
-			le_register_write(d, d->reg_select, idata);
-		}
-		break;
-
-	/*  Register select:  */
-	case 4:
-		if (writeflag==MEM_READ) {
-			odata = d->reg_select;
-			if (!quiet_mode)
-				debug("[ le: read from register select: "
-				    "0x%02x ]\n", (int)odata);
-		} else {
-			if (!quiet_mode)
-				debug("[ le: write to register select: "
-				    "0x%02x ]\n", (int)idata);
-			d->reg_select = idata & (N_REGISTERS - 1);
-			if (idata >= N_REGISTERS)
-				fatal("[ le: WARNING! register select %i "
-				    "(max is %i) ]\n", idata, N_REGISTERS - 1);
-		}
-		break;
-
-	default:
-		if (writeflag==MEM_READ) {
-			fatal("[ le: read from UNIMPLEMENTED addr 0x%06x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ le: write to UNIMPLEMENTED addr 0x%06x: "
-			    "0x%08x ]\n", (int)relative_addr, (int)idata);
-		}
-	}
-
-do_return:
-	if (writeflag == MEM_READ) {
-		memory_writemax64(cpu, data, len, odata);
-#ifdef LE_DEBUG
-		fatal("[ le: read from addr 0x%06x: 0x%08x ]\n",
-		    relative_addr, odata);
-#endif
-	}
-
-	dev_le_tick(cpu, extra);
-
-	return retval;
-}
-
-
-/*
- *  dev_le_init():
- */
-void dev_le_init(struct machine *machine, struct memory *mem, uint64_t baseaddr,
-	uint64_t buf_start, uint64_t buf_end, const char *irq_path, int len)
-{
-	char *name2;
-	size_t nlen = 55;
-	struct le_data *d;
-
-	CHECK_ALLOCATION(d = (struct le_data *) malloc(sizeof(struct le_data)));
-	memset(d, 0, sizeof(struct le_data));
-
-	INTERRUPT_CONNECT(irq_path, d->irq);
-
-	CHECK_ALLOCATION(d->sram = (unsigned char *) malloc(SRAM_SIZE));
-	memset(d->sram, 0, SRAM_SIZE);
-
-	/*  TODO:  Are these actually used yet?  */
-	d->len       = len;
-	d->buf_start = buf_start;
-	d->buf_end   = buf_end;
-
-	/*  Initial register contents:  */
-	d->reg[0] = LE_STOP;
-
-	d->tx_packet = NULL;
-	d->rx_packet = NULL;
-
-	/*  ROM (including the MAC address):  */
-	net_generate_unique_mac(machine, &d->rom[0]);
-
-	/*  Copies of the MAC address and a test pattern:  */
-	d->rom[10] = d->rom[21] = d->rom[5];
-	d->rom[11] = d->rom[20] = d->rom[4];
-	d->rom[12] = d->rom[19] = d->rom[3];
-	d->rom[7] =  d->rom[8]  = d->rom[23] =
-		     d->rom[13] = d->rom[18] = d->rom[2];
-	d->rom[6] =  d->rom[9]  = d->rom[22] =
-		     d->rom[14] = d->rom[17] = d->rom[1];
-	d->rom[15] = d->rom[16] = d->rom[0];
-	d->rom[24] = d->rom[28] = 0xff;
-	d->rom[25] = d->rom[29] = 0x00;
-	d->rom[26] = d->rom[30] = 0x55;
-	d->rom[27] = d->rom[31] = 0xaa;
-
-	memory_device_register(mem, "le_sram", baseaddr,
-	    SRAM_SIZE, dev_le_sram_access, (void *)d,
-	    DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK
-	    | DM_READS_HAVE_NO_SIDE_EFFECTS, d->sram);
-
-	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
-	snprintf(name2, nlen, "le [%02x:%02x:%02x:%02x:%02x:%02x]",
-	    d->rom[0], d->rom[1], d->rom[2], d->rom[3], d->rom[4], d->rom[5]);
-
-	memory_device_register(mem, name2, baseaddr + 0x100000,
-	    len - 0x100000, dev_le_access, (void *)d, DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(machine, dev_le_tick, d, LE_TICK_SHIFT);
-
-	net_add_nic(machine->emul->net, d, &d->rom[0]);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_lpt.c gxemul-0.7.0+dfsg/src/devices/dev_lpt.c
--- gxemul-0.6.2/src/devices/dev_lpt.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_lpt.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,148 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: LPT (parallel printer) controller
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/lptreg.h"
+
+
+/*  #define debug fatal  */
+
+#define	TICK_SHIFT		18
+#define	DEV_LPT_LENGTH		3
+
+struct lpt_data {
+	const char		*name;
+	struct interrupt	irq;
+	int			console_handle;
+
+	uint8_t			data;
+	uint8_t			control;
+};
+
+
+DEVICE_TICK(lpt)
+{
+	/*  struct lpt_data *d = extra;  */
+
+	/*  TODO  */
+}
+
+
+DEVICE_ACCESS(lpt)
+{
+	uint64_t idata = 0, odata=0;
+	struct lpt_data *d = (struct lpt_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case LPT_DATA:
+		if (writeflag == MEM_READ)
+			odata = d->data;
+		else
+			d->data = idata;
+		break;
+
+	case LPT_STATUS:
+		odata = LPS_NBSY | LPS_NACK | LPS_SELECT | LPS_NERR;
+		break;
+
+	case LPT_CONTROL:
+		if (writeflag == MEM_WRITE) {
+			if (idata != d->control) {
+				if (idata & LPC_STROBE) {
+					/*  data strobe  */
+					console_putchar(d->console_handle,
+					    d->data);
+				}
+			}
+			d->control = idata;
+		}
+		break;
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(lpt)
+{
+	struct lpt_data *d;
+	size_t nlen;
+	char *name;
+
+	CHECK_ALLOCATION(d = (struct lpt_data *) malloc(sizeof(struct lpt_data)));
+	memset(d, 0, sizeof(struct lpt_data));
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	d->name		= devinit->name2 != NULL? devinit->name2 : "";
+	d->console_handle = console_start_slave(devinit->machine, devinit->name,
+	    CONSOLE_OUTPUT_ONLY);
+
+	nlen = strlen(devinit->name) + 10;
+	if (devinit->name2 != NULL)
+		nlen += strlen(devinit->name2);
+	CHECK_ALLOCATION(name = (char *) malloc(nlen));
+	if (devinit->name2 != NULL && devinit->name2[0])
+		snprintf(name, nlen, "%s [%s]", devinit->name, devinit->name2);
+	else
+		snprintf(name, nlen, "%s", devinit->name);
+
+	memory_device_register(devinit->machine->memory, name, devinit->addr,
+	    DEV_LPT_LENGTH, dev_lpt_access, d, DM_DEFAULT, NULL);
+	machine_add_tickfunction(devinit->machine, dev_lpt_tick, d,
+	    TICK_SHIFT);
+
+	/*
+	 *  NOTE:  Ugly cast into a pointer, because this is a convenient way
+	 *         to return the console handle to code in src/machine.c.
+	 */
+	devinit->return_ptr = (void *)(size_t)d->console_handle;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_lpt.cc gxemul-0.7.0+dfsg/src/devices/dev_lpt.cc
--- gxemul-0.6.2/src/devices/dev_lpt.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_lpt.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,148 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: LPT (parallel printer) controller
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/lptreg.h"
-
-
-/*  #define debug fatal  */
-
-#define	TICK_SHIFT		18
-#define	DEV_LPT_LENGTH		3
-
-struct lpt_data {
-	const char		*name;
-	struct interrupt	irq;
-	int			console_handle;
-
-	uint8_t			data;
-	uint8_t			control;
-};
-
-
-DEVICE_TICK(lpt)
-{
-	/*  struct lpt_data *d = extra;  */
-
-	/*  TODO  */
-}
-
-
-DEVICE_ACCESS(lpt)
-{
-	uint64_t idata = 0, odata=0;
-	struct lpt_data *d = (struct lpt_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case LPT_DATA:
-		if (writeflag == MEM_READ)
-			odata = d->data;
-		else
-			d->data = idata;
-		break;
-
-	case LPT_STATUS:
-		odata = LPS_NBSY | LPS_NACK | LPS_SELECT | LPS_NERR;
-		break;
-
-	case LPT_CONTROL:
-		if (writeflag == MEM_WRITE) {
-			if (idata != d->control) {
-				if (idata & LPC_STROBE) {
-					/*  data strobe  */
-					console_putchar(d->console_handle,
-					    d->data);
-				}
-			}
-			d->control = idata;
-		}
-		break;
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(lpt)
-{
-	struct lpt_data *d;
-	size_t nlen;
-	char *name;
-
-	CHECK_ALLOCATION(d = (struct lpt_data *) malloc(sizeof(struct lpt_data)));
-	memset(d, 0, sizeof(struct lpt_data));
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	d->name		= devinit->name2 != NULL? devinit->name2 : "";
-	d->console_handle = console_start_slave(devinit->machine, devinit->name,
-	    CONSOLE_OUTPUT_ONLY);
-
-	nlen = strlen(devinit->name) + 10;
-	if (devinit->name2 != NULL)
-		nlen += strlen(devinit->name2);
-	CHECK_ALLOCATION(name = (char *) malloc(nlen));
-	if (devinit->name2 != NULL && devinit->name2[0])
-		snprintf(name, nlen, "%s [%s]", devinit->name, devinit->name2);
-	else
-		snprintf(name, nlen, "%s", devinit->name);
-
-	memory_device_register(devinit->machine->memory, name, devinit->addr,
-	    DEV_LPT_LENGTH, dev_lpt_access, d, DM_DEFAULT, NULL);
-	machine_add_tickfunction(devinit->machine, dev_lpt_tick, d,
-	    TICK_SHIFT);
-
-	/*
-	 *  NOTE:  Ugly cast into a pointer, because this is a convenient way
-	 *         to return the console handle to code in src/machine.c.
-	 */
-	devinit->return_ptr = (void *)(size_t)d->console_handle;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_luna88k.c gxemul-0.7.0+dfsg/src/devices/dev_luna88k.c
--- gxemul-0.6.2/src/devices/dev_luna88k.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_luna88k.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1032 @@
+/*
+ *  Copyright (C) 2018-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: OMRON Luna 88K-specific devices and control registers
+ *
+ *  Almost everything in here is just dummy code which returns nonsense,
+ *  just enough to fake hardware well enough to get OpenBSD/luna88k to
+ *  work to some basic degree.
+ *
+ *  Things that are implemented:
+ *	Interrupt controller (hopefully working with all 4 CPUs)
+ *	Time-of-day clock
+ *	Serial I/O (including Keyboard and Mouse)
+ *	Monochrome framebuffer
+ *	Lance ethernet
+ *	SCSI
+ *
+ *  Things that are NOT implemented yet:
+ *	LUNA-88K2 specifics. (Some registers are at different addresses etc.)
+ *	Parallel I/O
+ *	Front LCD display (half-implemented but output not shown anywhere)
+ *	Color framebuffer
+ *
+ *  TODO: Separate out some devices to their own files:
+ *	x) so that they can potentially be reused for a luna68k mode
+ *	x) sio seems similar to scc?
+ *	x) the clock is similar to other clock chips?
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+#include "cpu.h"
+#include "console.h"
+#include "device.h"
+#include "devices.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/sccreg.h"	// similar to sio?
+#include "thirdparty/hitachi_hm53462_rop.h"
+#include "thirdparty/luna88k_board.h"
+#include "thirdparty/m8820x.h"
+
+#define	TICK_STEPS_SHIFT	14
+
+// TODO: Actually make this configurable. Currently hardcoded to match OpenBSD/luna88k.
+#define	LUNA88K_PSEUDO_TIMER_HZ	100.0
+
+#define	LUNA88K_REGISTERS_BASE		0x3ffffff0UL
+#define	LUNA88K_REGISTERS_END		BMAP_START
+#define	LUNA88K_REGISTERS_LENGTH	(LUNA88K_REGISTERS_END - LUNA88K_REGISTERS_BASE)
+
+#define	MAX_CPUS	4
+
+#define	SIO_QUEUE_SIZE	256
+
+#define	BCD(x) ((((x) / 10) << 4) + ((x) % 10))
+
+
+struct luna88k_data {
+	struct interrupt cpu_irq[MAX_CPUS];
+	int		irqActive[MAX_CPUS];
+	uint32_t	interrupt_enable[MAX_CPUS];
+	uint32_t	interrupt_status;
+	uint32_t	software_interrupt_status[MAX_CPUS];
+
+	/*  Timer stuff  */
+	struct timer	*timer;
+	int		pending_timer_interrupts;
+	struct interrupt timer_irq;
+
+	bool		using_framebuffer;
+
+	/*  LCD at PIO port 1:  */
+	uint8_t		lcd[40 * 2];
+	uint8_t		pio1c;
+	int		lcd_x;
+	int		lcd_y;
+
+	/*  sio: Serial controller, two channels.  */
+	int		console_handle;
+	struct interrupt sio_irq;
+	int		sio_tx_pending[2];
+	int		obio_sio_regno[2];
+	uint8_t		obio_sio_rr[2][8];
+	uint8_t		obio_sio_wr[2][8];
+	uint8_t		sio_queue[2][SIO_QUEUE_SIZE];
+	int		sio_queue_head[2];
+	int		sio_queue_tail[2];
+	int		mouse_enable;
+	int		mouse_buttons;
+
+	/*  ROM and RAM (used by the Ethernet interface)  */
+	uint32_t	fuse_rom[FUSE_ROM_SPACE / sizeof(uint32_t)];
+	uint8_t		nvram[NVRAM_SPACE];
+	uint8_t		tri_port_ram[TRI_PORT_RAM_SPACE];
+};
+
+
+static int anything_in_sio_queue(struct luna88k_data* d, int n)
+{
+	return d->sio_queue_head[n] != d->sio_queue_tail[n];
+}
+
+static int space_available_in_sio_queue(struct luna88k_data* d, int n)
+{
+	int diff = d->sio_queue_head[n] - d->sio_queue_tail[n];
+	if (diff <= 0)
+		diff += SIO_QUEUE_SIZE;
+
+	return diff;
+}
+
+static uint8_t get_from_sio_queue(struct luna88k_data* d, int n)
+{
+	uint8_t result = d->sio_queue[n][d->sio_queue_head[n]++];
+	if (d->sio_queue_head[n] >= SIO_QUEUE_SIZE)
+		d->sio_queue_head[n] = 0;
+
+	return result;
+}
+
+static void add_to_sio_queue(struct luna88k_data* d, int n, uint8_t c)
+{
+	d->sio_queue[n][d->sio_queue_tail[n]++] = c;
+	if (d->sio_queue_tail[n] >= SIO_QUEUE_SIZE)
+		d->sio_queue_tail[n] = 0;
+
+	if (d->sio_queue_tail[n] == d->sio_queue_head[n])
+		fatal("[ luna88k: add_to_sio_queue overrun; increase SIO_QUEUE_SIZE ]\n");
+}
+
+static void reassert_interrupts(struct luna88k_data *d)
+{
+	int cpu;
+
+	for (cpu = 0; cpu < MAX_CPUS; cpu++) {
+		// printf("cpu%i: status = 0x%08x, enable = 0x%08x\n",
+		//	cpu, d->interrupt_status, d->interrupt_enable[0]);
+
+		// General interrupt status is for the entire machine,
+		// but the Software interrupts (IPIs) are per CPU.
+		uint32_t status = d->interrupt_status;
+		uint32_t enable = d->interrupt_enable[cpu];
+
+		if (d->software_interrupt_status[cpu])
+			status |= (1 << 26);
+
+	        if (status & enable) {
+			if (!d->irqActive[cpu])
+		                INTERRUPT_ASSERT(d->cpu_irq[cpu]);
+
+			d->irqActive[cpu] = 1;
+		} else {
+			if (d->irqActive[cpu])
+		                INTERRUPT_DEASSERT(d->cpu_irq[cpu]);
+
+			d->irqActive[cpu] = 0;
+		}
+	}
+
+	// printf("--\n");
+}
+
+static void luna88k_interrupt_assert(struct interrupt *interrupt)
+{
+        struct luna88k_data *d = (struct luna88k_data *) interrupt->extra;
+	d->interrupt_status |= (1 << (interrupt->line + 25));
+	reassert_interrupts(d);
+}
+
+static void luna88k_interrupt_deassert(struct interrupt *interrupt)
+{
+        struct luna88k_data *d = (struct luna88k_data *) interrupt->extra;
+	d->interrupt_status &= ~(1 << (interrupt->line + 25));
+	reassert_interrupts(d);
+}
+
+static void reassert_timer_interrupt(struct luna88k_data* d)
+{
+	if (d->pending_timer_interrupts)
+		INTERRUPT_ASSERT(d->timer_irq);
+	else
+		INTERRUPT_DEASSERT(d->timer_irq);
+}
+
+static void reassert_serial_interrupt(struct luna88k_data* d)
+{
+	int assertSerial = 0;
+	int port;
+
+	for (port = 0; port <= 1; port++) {
+		if ((d->obio_sio_wr[port][SCC_WR1] & SCC_WR1_RXI_ALL_CHAR) ||
+		    (d->obio_sio_wr[port][SCC_WR1] & SCC_WR1_RXI_FIRST_CHAR)) {
+			if (anything_in_sio_queue(d, port))
+				assertSerial = 1;
+		}
+
+		if (d->obio_sio_wr[port][SCC_WR1] & SCC_WR1_TX_IE &&
+		    d->sio_tx_pending[port])
+			assertSerial = 1;
+	}
+
+	if (assertSerial)
+		INTERRUPT_ASSERT(d->sio_irq);
+	else
+		INTERRUPT_DEASSERT(d->sio_irq);
+}
+
+
+/*
+ *  luna88k_timer_tick():
+ *
+ *  This function is called LUNA88K_PSEUDO_TIMER_HZ times per real-world second.
+ */
+static void luna88k_timer_tick(struct timer *t, void *extra)
+{
+	struct luna88k_data* d = (struct luna88k_data*) extra;
+	d->pending_timer_interrupts ++;
+	
+	// More than a second lost? Then restart the nr of pending interrupts.
+	if (d->pending_timer_interrupts > (int)(LUNA88K_PSEUDO_TIMER_HZ)) {
+		d->pending_timer_interrupts = 1;
+
+		debugmsg(SUBSYS_DEVICE, "luna88k", VERBOSITY_DEBUG,
+		    "Timer ticks lost... Host too slow?");
+	}
+}
+
+
+int luna88k_lcd_access(struct luna88k_data *d, int writeflag, int idata)
+{
+	int odata = 0;
+
+	switch (d->pio1c) {
+
+	case 0x00:
+	case 0xb0:
+		// Ignore for now.
+		break;
+
+	case 0x90:	// "control"
+		if (writeflag && ((idata & 0xc0) == 0xc0 || (idata & 0xc0) == 0x80)) {
+			d->lcd_x = idata & 0x0f;
+			d->lcd_y = idata & 0x40 ? 1 : 0;
+		} else if (writeflag) {
+			switch (idata) {
+
+			case 0x01:
+				// CLS
+				memset(d->lcd, ' ', sizeof(d->lcd));
+				d->lcd_x = 0;
+				d->lcd_y = 0;
+				break;
+
+			case 0x02:
+				// HOME
+				d->lcd_x = 0;
+				d->lcd_y = 0;
+				break;
+
+			case 0x06:
+				// ENTRY
+				break;
+
+			case 0x0c:
+				// ON
+				break;
+
+			case 0x38:
+				// INIT
+				break;
+
+			default:
+				debugmsg(SUBSYS_DEVICE, "luna88k", VERBOSITY_WARNING,
+			    	    "unimplemented LCD CONTROL: 0x%x",
+				    (int) idata);
+			}
+		} else {
+			debugmsg(SUBSYS_DEVICE, "luna88k", VERBOSITY_WARNING,
+		    	    "unimplemented READ from PIO1A (pio1c = 0x%02x)",
+			    d->pio1c);
+		}
+		break;
+
+	case 0xd0:	// "data"
+		// I'm not sure if data can be _read_ like this, but at least
+		// writing works as intended.
+		if (writeflag)
+			d->lcd[d->lcd_x + 40 * d->lcd_y] = idata;
+		else
+			odata = d->lcd[d->lcd_x + 40 * d->lcd_y];
+
+		if (++ d->lcd_x == 40) {
+			d->lcd_x = 0;
+			d->lcd_y ^= 1;
+		}
+
+		if (writeflag) {
+			char tmp[100];
+			snprintf(tmp, sizeof(tmp), "LCD: |");
+
+			size_t b = strlen(tmp);
+
+			for (size_t i = 0; i < 16; ++i)
+				tmp[b + i] = d->lcd[i] >= ' ' && d->lcd[i] < 127 ? d->lcd[i] : ' ';
+
+			for (size_t i = 0; i < 16; ++i)
+				tmp[b + i + 16] = d->lcd[i+40] >= ' ' && d->lcd[i+40] < 127 ? d->lcd[i+40] : ' ';
+
+			tmp[b + 16*2] = '|';
+			tmp[b + 16*2 + 1] = 0;
+
+			debugmsg(SUBSYS_DEVICE, "luna88k", VERBOSITY_INFO, tmp);
+		}
+
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE) {
+			debugmsg(SUBSYS_DEVICE, "luna88k", VERBOSITY_WARNING,
+		    	    "unimplemented WRITE to PIO1A: 0x%x (pio1c = 0x%02x)",
+			    (int) idata,
+			    d->pio1c);
+		} else
+			debugmsg(SUBSYS_DEVICE, "luna88k", VERBOSITY_WARNING,
+		    	    "unimplemented READ from PIO1A: 0x%x (pio1c = 0x%02x)",
+			    (int) odata,
+			    d->pio1c);
+	}
+
+	return odata;
+}
+
+
+DEVICE_TICK(luna88k)
+{
+	struct luna88k_data *d = (struct luna88k_data *) extra;
+
+	/*  Serial console:  */
+	if (!d->using_framebuffer) {
+		 while (space_available_in_sio_queue(d, 0) > 2 &&
+		    console_charavail(d->console_handle)) {
+			int c = console_readchar(d->console_handle);
+			add_to_sio_queue(d, 0, c);
+		}
+	}
+
+	/*  Keyboard and mouse:  */
+	if (d->using_framebuffer) {
+		while (space_available_in_sio_queue(d, 1) > 7 &&
+		    console_charavail(d->console_handle)) {
+			int c = console_readchar(d->console_handle);
+			int shifted = 0;
+			int controlled = 0;
+			int sc = 0;
+
+			if (c >= 'A' && c <= 'Z') {
+				shifted = 1;
+				c += 'a' - 'A';
+			}
+			
+			if (c >= 1 && c <= 26) {
+				controlled = 1;
+				c += 'a' - 1;
+			}
+			
+			switch (c) {
+			case 'a':	sc = 0x42;	break;
+			case 'b':	sc = 0x56;	break;
+			case 'c':	sc = 0x54;	break;
+			case 'd':	sc = 0x44;	break;
+			case 'e':	sc = 0x34;	break;
+			case 'f':	sc = 0x45;	break;
+			case 'g':	sc = 0x46;	break;
+			case 'h':	sc = 0x47;	break;
+			case 'i':	sc = 0x39;	break;
+			case 'j':	sc = 0x48;	break;
+			case 'k':	sc = 0x49;	break;
+			case 'l':	sc = 0x4a;	break;
+			case 'm':	sc = 0x58;	break;
+			case 'n':	sc = 0x57;	break;
+			case 'o':	sc = 0x3a;	break;
+			case 'p':	sc = 0x3b;	break;
+			case 'q':	sc = 0x32;	break;
+			case 'r':	sc = 0x35;	break;
+			case 's':	sc = 0x43;	break;
+			case 't':	sc = 0x36;	break;
+			case 'u':	sc = 0x38;	break;
+			case 'v':	sc = 0x55;	break;
+			case 'w':	sc = 0x33;	break;
+			case 'x':	sc = 0x53;	break;
+			case 'y':	sc = 0x37;	break;
+			case 'z':	sc = 0x52;	break;
+
+			case '1':	sc = 0x22;	break;
+			case '2':	sc = 0x23;	break;
+			case '3':	sc = 0x24;	break;
+			case '4':	sc = 0x25;	break;
+			case '5':	sc = 0x26;	break;
+			case '6':	sc = 0x27;	break;
+			case '7':	sc = 0x28;	break;
+			case '8':	sc = 0x29;	break;
+			case '9':	sc = 0x2a;	break;
+			case '0':	sc = 0x2b;	break;
+			case '-':	sc = 0x2c;	break;
+			case '^':	sc = 0x2d;	break;
+			case '\\':	sc = 0x2e;	break;
+
+			case '!':	sc = 0x22; shifted = 1;	break;
+			case '"':	sc = 0x23; shifted = 1;	break;
+			case '#':	sc = 0x24; shifted = 1;	break;
+			case '$':	sc = 0x25; shifted = 1;	break;
+			case '%':	sc = 0x26; shifted = 1;	break;
+			case '&':	sc = 0x27; shifted = 1;	break;
+			case '\'':	sc = 0x28; shifted = 1;	break;
+			case '(':	sc = 0x29; shifted = 1;	break;
+			case ')':	sc = 0x2a; shifted = 1;	break;
+			case '=':	sc = 0x2c; shifted = 1;	break;
+			case '~':	sc = 0x2d; shifted = 1;	break;
+			case '|':	sc = 0x2e; shifted = 1;	break;
+
+			case '@':	sc = 0x3c;	break;
+			case '[':	sc = 0x3d;	break;
+			case ';':	sc = 0x4b;	break;
+			case ':':	sc = 0x4c;	break;
+			case ']':	sc = 0x4d;	break;
+			case ',':	sc = 0x59;	break;
+			case '.':	sc = 0x5a;	break;
+			case '/':	sc = 0x5b;	break;
+			case '_':	sc = 0x5c;	break;
+
+			case '`':	sc = 0x3c; shifted = 1;	break;
+			case '{':	sc = 0x3d; shifted = 1;	break;
+			case '+':	sc = 0x4b; shifted = 1;	break;
+			case '*':	sc = 0x4c; shifted = 1;	break;
+			case '}':	sc = 0x4d; shifted = 1;	break;
+			case '<':	sc = 0x59; shifted = 1;	break;
+			case '>':	sc = 0x5a; shifted = 1;	break;
+			case '?':	sc = 0x5b; shifted = 1;	break;
+
+			case '\t':	sc = 0x09;	break;
+			case 27:	sc = 0x10;	break;
+			case '\b':	sc = 0x11;	break;
+			case '\r':	sc = 0x12;	break;
+			case ' ':	sc = 0x14;	break;
+			case '\x7f':	sc = 0x15;	break;
+			}
+
+			if (sc > 0) {
+				if (sc <= 0x15)
+					controlled = 0;
+
+				if (shifted)
+					add_to_sio_queue(d, 1, 0x0d);
+				if (controlled)
+					add_to_sio_queue(d, 1, 0x0a);
+			
+				add_to_sio_queue(d, 1, sc);
+				add_to_sio_queue(d, 1, sc | 0x80);
+
+				if (controlled)
+					add_to_sio_queue(d, 1, 0x0a | 0x80);
+				if (shifted)
+					add_to_sio_queue(d, 1, 0x0d | 0x80);
+			}
+		}
+
+		if (space_available_in_sio_queue(d, 1) > 4 && d->mouse_enable) {
+			int mouse_buttons, mouse_fb_nr, xdelta, ydelta;
+
+			console_getmouse(&xdelta, &ydelta, &mouse_buttons, &mouse_fb_nr);
+			ydelta = 0 - ydelta;
+
+			const int m = 125;
+
+			if (xdelta > m)
+				xdelta = m;
+			if (xdelta < -m)
+				xdelta = -m;
+			if (ydelta > m)
+				ydelta = m;
+			if (ydelta < -m)
+				ydelta = -m;
+
+			/*  Only send update if there is an actual diff.  */
+			if (xdelta != 0 || ydelta != 0 || d->mouse_buttons != mouse_buttons) {
+				d->mouse_buttons = mouse_buttons;
+
+				// 3-byte protocol according to
+				// OpenBSD/luna88k's lunaws.c.
+				uint8_t b1 = 0x80;
+				int8_t b2 = xdelta;
+				int8_t b3 = ydelta;
+
+				// Buttons are L=4, M=2, R=1, but off means
+				// button down, on means button up! Weird...
+				b1 |= ((~mouse_buttons) & 7);
+
+				//printf("x=%i y=%i b1=%02x %02x %02x\n", xdelta, ydelta, b1,b2,b3);
+				add_to_sio_queue(d, 1, b1);
+				add_to_sio_queue(d, 1, b2);
+				add_to_sio_queue(d, 1, b3);
+			}
+		}
+	}
+
+	reassert_serial_interrupt(d);
+	reassert_timer_interrupt(d);
+}
+
+
+DEVICE_ACCESS(luna88k)
+{
+	struct tm *tmp;
+	time_t timet;
+ 	uint32_t addr = relative_addr + LUNA88K_REGISTERS_BASE;
+	uint64_t idata = 0, odata = 0;
+	struct luna88k_data *d = (struct luna88k_data *) extra;
+	int cpunr;
+	int sio_devnr;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (addr >= FUSE_ROM_ADDR && len == sizeof(uint32_t) &&
+	    addr < FUSE_ROM_ADDR + FUSE_ROM_SPACE) {
+		if (writeflag == MEM_READ) {
+			odata = d->fuse_rom[(addr - FUSE_ROM_ADDR) / sizeof(uint32_t)];
+			memory_writemax64(cpu, data, len, odata);
+		} else {
+			d->fuse_rom[(addr - FUSE_ROM_ADDR) / sizeof(uint32_t)] = idata;
+		}
+		return 1;
+	}
+
+	if (addr >= FUSE_ROM_ADDR && len == sizeof(uint8_t) &&
+	    addr < FUSE_ROM_ADDR + FUSE_ROM_SPACE) {
+		if (writeflag == MEM_READ) {
+			odata = d->fuse_rom[(addr - FUSE_ROM_ADDR) / sizeof(uint32_t)];
+			odata >>= ((3 - (addr & 3)) * 8);
+			memory_writemax64(cpu, data, len, odata);
+		} else {
+			fatal("TODO: luna88k byte write to fuse\n");
+		}
+		return 1;
+	}
+
+	if (addr >= NVRAM_ADDR && addr + len <= NVRAM_ADDR + NVRAM_SPACE) {
+		size_t offset = addr - NVRAM_ADDR;
+		if (writeflag == MEM_READ) {
+			memcpy(data, d->nvram + offset, len);
+		} else {
+			memcpy(d->nvram + offset, data, len);
+		}
+		return 1;
+	}
+
+	if (addr >= NVRAM_ADDR_88K2 && addr < NVRAM_ADDR_88K2 + NVRAM_SPACE && len == sizeof(uint8_t)) {
+		if (writeflag == MEM_READ) {
+			odata = d->nvram[addr - NVRAM_ADDR_88K2];
+			memory_writemax64(cpu, data, len, odata);
+		} else {
+			d->nvram[addr - NVRAM_ADDR_88K2] = idata;
+		}
+		return 1;
+	}
+
+	if (addr >= TRI_PORT_RAM && addr < TRI_PORT_RAM + TRI_PORT_RAM_SPACE) {
+		size_t offset = addr - TRI_PORT_RAM;
+
+		cpu->memory_rw(cpu, cpu->mem, LANCE_ADDR - 0x100000 + offset,
+			data, len, writeflag, NO_EXCEPTIONS | PHYSICAL);
+// if(len==2)
+// printf("OFFSET 0x%06x WRITE=%i 0x%02x%02x\n", (int)offset, (int)writeflag, data[0],data[1]);
+// else
+// printf("OFFSET 0x%06x WRITE=%i 0x%02x\n", (int)offset, (int)writeflag, data[0]);
+		return 1;
+	}
+
+	switch (addr) {
+
+	case 0x3ffffff0:
+		/*  Accessed by OpenBSD/luna88k to trigger an illegal address  */
+		cpu->cd.m88k.cmmu[1]->reg[CMMU_PFSR] = CMMU_PFSR_BERROR << 16;
+		break;
+
+	case PROM_ADDR:		/*  0x41000000  */
+		/*  OpenBSD/luna88k write here during boot. Ignore for now. (?)  */
+		break;
+
+	case OBIO_CAL_CTL:	/*  calendar control register  */
+		// TODO: Freeze bit etc.
+		// Perhaps same as dev_mk48txx.cc?
+		break;
+	case OBIO_CAL_SEC:
+		timet = time(NULL); tmp = gmtime(&timet);
+		odata = BCD(tmp->tm_sec) << 24;
+		break;
+	case OBIO_CAL_MIN:
+		timet = time(NULL); tmp = gmtime(&timet);
+		odata = BCD(tmp->tm_min) << 24;
+		break;
+	case OBIO_CAL_HOUR:
+		timet = time(NULL); tmp = gmtime(&timet);
+		odata = BCD(tmp->tm_hour) << 24;
+		break;
+	case OBIO_CAL_DOW:
+		timet = time(NULL); tmp = gmtime(&timet);
+		odata = BCD(tmp->tm_wday + 0) << 24;
+		break;
+	case OBIO_CAL_DAY:
+		timet = time(NULL); tmp = gmtime(&timet);
+		odata = BCD(tmp->tm_mday) << 24;
+		break;
+	case OBIO_CAL_MON:
+		timet = time(NULL); tmp = gmtime(&timet);
+		odata = BCD(tmp->tm_mon + 1) << 24;
+		break;
+	case OBIO_CAL_YEAR:
+		timet = time(NULL); tmp = gmtime(&timet);
+		// TODO: 1970 for LUNA88K (MK), 1990 for LUNA88K2 (DS)
+		odata = BCD((tmp->tm_year + 1900) - 1970) << 24;
+		break;
+
+	case OBIO_PIO0A:	/*  0x49000000: PIO-0 port A  */
+		/*  OpenBSD reads dipswitch settings from PIO0A and B.  */
+		odata = 0;	// high byte
+		if (cpu->machine->x11_md.in_use)
+			odata |= 0x40;
+		odata |= 0x80;	// multi-user mode
+		odata |= 0x20;	// don't ask name
+		odata |= 0x10;	// don't do manual UKC config
+		break;
+
+	case OBIO_PIO0B:	/*  0x49000004: PIO-0 port B  */
+		/*  OpenBSD reads dipswitch settings from PIO0A and B.  */
+		odata = 0x00;	// low byte
+		break;
+
+	case OBIO_PIO0:		/*  0x4900000C: PIO-0 control  */
+		/*  TODO: Implement for real.  */
+		break;
+
+	case OBIO_PIO1A:	/*  0x4d000000: PIO-1 port A  */
+		odata = luna88k_lcd_access(d, writeflag, idata);
+		break;
+
+	case OBIO_PIO1B:	/*  0x4d000004: PIO-1 port B  */
+	case OBIO_PIO1:		/*  0x4d00000C: PIO-1 control  */
+		/*  Ignore for now. (?)  */
+		break;
+
+	case OBIO_PIO1C:	/*  0x4d000008: PIO-1 port C  */
+		if (writeflag == MEM_WRITE)
+			d->pio1c = idata;
+		else
+			odata = d->pio1c;
+		break;
+
+	case OBIO_SIO + 0:	/*  0x51000000: data channel 0 */
+	case OBIO_SIO + 4:	/*  0x51000004: cmd channel 0 */
+	case OBIO_SIO + 8:	/*  0x51000008: data channel 1 */
+	case OBIO_SIO + 0xc:	/*  0x5100000c: cmd channel 1 */
+		sio_devnr = ((addr - OBIO_SIO) / 8) & 1;
+
+		if ((addr - OBIO_SIO) & 4) {
+			/*  cmd  */
+
+			/*  Similar to dev_scc.cc ?  */
+			if (writeflag == MEM_WRITE) {
+				int old_tx_enable = d->obio_sio_wr[sio_devnr][SCC_WR1] & SCC_WR1_TX_IE;
+				if (d->obio_sio_regno[sio_devnr] == 0) {
+					int regnr = idata & 7;
+					int cmd = idata & ~7;
+
+					// printf("[ sio: cmd=0x%02x, then setting regno for next operation to 0x%02x ]\n", cmd, regnr);
+
+					/*  High bits are command.  */
+					switch (cmd) {
+					case SCC_RESET_TX_IP:
+						d->sio_tx_pending[sio_devnr] = 0;
+						break;
+					}
+
+					d->obio_sio_regno[sio_devnr] = regnr;
+				} else {
+					int regnr = d->obio_sio_regno[sio_devnr] & 7;
+					d->obio_sio_wr[sio_devnr][regnr] = idata;
+
+					// printf("[ sio: setting reg 0x%02x = 0x%02x ]\n", d->obio_sio_regno[sio_devnr], (int)idata);
+
+					d->obio_sio_regno[sio_devnr] = 0;
+				}
+
+				if (d->obio_sio_wr[sio_devnr][SCC_WR1] & SCC_WR1_TX_IE && !old_tx_enable)
+					d->sio_tx_pending[sio_devnr] = 1;
+
+				reassert_serial_interrupt(d);
+			} else {
+				d->obio_sio_rr[sio_devnr][SCC_RR0] = SCC_RR0_TX_EMPTY | SCC_RR0_DCD | SCC_RR0_CTS;
+
+				if (anything_in_sio_queue(d, sio_devnr))
+					d->obio_sio_rr[sio_devnr][SCC_RR0] |= SCC_RR0_RX_AVAIL;
+
+				d->obio_sio_rr[sio_devnr][SCC_RR1] = SCC_RR1_ALL_SENT;
+
+				int regnr = d->obio_sio_regno[sio_devnr] & 7;
+				odata = d->obio_sio_rr[sio_devnr][regnr];
+				// printf("[ sio: reading reg 0x%02x: 0x%02x ]\n", regnr, (int)odata);
+				d->obio_sio_regno[sio_devnr] = 0;
+			}
+		} else {
+			/*  data  */
+			if (writeflag == MEM_WRITE) {
+				// printf("[ sio: writing data 0x%02x to port %i ]\n", (int)idata, sio_devnr);
+				if (sio_devnr == 0) {
+					console_putchar(d->console_handle, idata);
+				} else {
+					/*  Mouse and Keyboard.  */
+					/*  These are according to OpenBSD/luna88k's lunaws.c  */
+					switch (idata) {
+					case 0x00:
+						/*  "kana LED off".  TODO  */
+						break;
+					case 0x01:
+						/*  "caps LED off".  TODO  */
+						break;
+					case 0x10:
+						/*  "kana LED on".  TODO  */
+						break;
+					case 0x11:
+						/*  "caps LED on".  TODO  */
+						break;
+					case 0x20:
+						d->mouse_enable = 0;
+						break;
+					case 0x60:
+						d->mouse_enable = 1;
+						break;
+					default:
+						fatal("[ luna88k: sio write to dev 1 (keyboard/mouse): 0x%02x ]\n", (int)idata);
+					}
+				}
+
+				d->sio_tx_pending[sio_devnr] = 1;
+			} else {
+				if (anything_in_sio_queue(d, sio_devnr)) {
+					odata = get_from_sio_queue(d, sio_devnr);
+				} else {
+					odata = 0;
+				}
+			}
+
+			reassert_serial_interrupt(d);
+		}
+
+		break;
+
+	case OBIO_CLOCK0:	/*  0x63000000: Clock ack?  */
+	case OBIO_CLOCK1:	/*  0x63000004: Clock ack?  */
+	case OBIO_CLOCK2:	/*  0x63000008: Clock ack?  */
+	case OBIO_CLOCK3:	/*  0x6300000c: Clock ack?  */
+		cpunr = (addr - OBIO_CLOCK0) / 4;
+		// TODO: Pending counter per cpu?
+		if (cpunr == 0 && d->pending_timer_interrupts > 0)
+			d->pending_timer_interrupts --;
+
+		reassert_timer_interrupt(d);
+		break;
+
+	case INT_ST_MASK0:	/*  0x65000000: Interrupt status CPU 0.  */
+	case INT_ST_MASK1:	/*  0x65000004: Interrupt status CPU 1.  */
+	case INT_ST_MASK2:	/*  0x65000008: Interrupt status CPU 2.  */
+	case INT_ST_MASK3:	/*  0x6500000c: Interrupt status CPU 3.  */
+		/*
+		 *  From OpenBSD/luna88k machdep.c source code:
+		 *
+		 *  On write: Bits 31..26 are used to enable/disable levels 6..1.
+		 *  On read: Bits 31..29 show value 0-7 of current interrupt.
+		 *           Bits 23..18 show current mask.
+		 */
+		cpunr = (addr - INT_ST_MASK0) / 4;
+		if (writeflag == MEM_WRITE) {
+			if ((idata & 0x03ffffff) != 0x00000000) {
+				fatal("[ TODO: luna88k interrupts, idata = 0x%08x, what to do with low bits? ]\n", (uint32_t)idata);
+				exit(1);
+			}
+
+			d->interrupt_enable[cpunr] = idata;
+			reassert_interrupts(d);
+		} else {
+			uint32_t currentMask = d->interrupt_enable[cpunr];
+			uint32_t status = d->interrupt_status & currentMask;
+			int highestCurrentStatus = 0;
+			odata = currentMask >> 8;
+			
+			for (int i = 1; i <= 6; ++i) {
+				int m = 1 << (25 + i);
+				if (status & m)
+					highestCurrentStatus = i;
+			}
+
+			odata |= (highestCurrentStatus << 29);
+			// printf("highest = %i 0x%08x\n", highestCurrentStatus, (int)odata);
+		}
+
+		break;
+
+	case SOFT_INT0:		/*  0x69000000: Software Interrupt status CPU 0.  */
+	case SOFT_INT1:		/*  0x69000004: Software Interrupt status CPU 1.  */
+	case SOFT_INT2:		/*  0x69000008: Software Interrupt status CPU 2.  */
+	case SOFT_INT3:		/*  0x6900000c: Software Interrupt status CPU 3.  */
+		cpunr = (addr - SOFT_INT0) / 4;
+
+		if (writeflag == MEM_WRITE) {
+			d->software_interrupt_status[cpunr] = idata;
+		} else {
+			// Reading status clears it.
+			odata = d->software_interrupt_status[cpunr];
+			d->software_interrupt_status[cpunr] = 0;
+		}
+
+		reassert_interrupts(d);
+		break;
+
+	case RESET_CPU_ALL:	/*  0x6d000010: Reset all CPUs  */
+		for (int i = 0; i < cpu->machine->ncpus; ++i)
+			cpu->machine->cpus[i]->running = 0;
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			debugmsg_cpu(cpu, SUBSYS_DEVICE, "luna88k", VERBOSITY_ERROR,
+		    	    "unimplemented %i-bit WRITE to address 0x%x: 0x%x",
+		    	    len * 8,
+			    (int) addr,
+			    (int) idata);
+		else
+			debugmsg_cpu(cpu, SUBSYS_DEVICE, "luna88k", VERBOSITY_ERROR,
+		    	    "unimplemented %i-bit READ from address 0x%x",
+		    	    len * 8,
+			    (int) addr);
+
+		// Stop the emulation immediately.
+		cpu->running = 0;
+		return 0;
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+void add_cmmu_for_cpu(struct devinit* devinit, int cpunr, uint32_t iaddr, uint32_t daddr)
+{
+	char tmpstr[300];
+	struct m8820x_cmmu *cmmu;
+
+	if (cpunr >= devinit->machine->ncpus)
+		return;
+
+	/*  Instruction CMMU:  */
+	CHECK_ALLOCATION(cmmu = (struct m8820x_cmmu *) malloc(sizeof(struct m8820x_cmmu)));
+	memset(cmmu, 0, sizeof(struct m8820x_cmmu));
+
+	devinit->machine->cpus[cpunr]->cd.m88k.cmmu[0] = cmmu;
+
+	/*  This is a 88200, revision 9:  */
+	cmmu->reg[CMMU_IDR] = (M88200_ID << 21) | (9 << 16);
+	snprintf(tmpstr, sizeof(tmpstr), "m8820x addr=0x%x addr2=%i", iaddr, 2 * cpunr);
+	device_add(devinit->machine, tmpstr);
+
+	/*  ... and data CMMU:  */
+	CHECK_ALLOCATION(cmmu = (struct m8820x_cmmu *) malloc(sizeof(struct m8820x_cmmu)));
+	memset(cmmu, 0, sizeof(struct m8820x_cmmu));
+
+	devinit->machine->cpus[cpunr]->cd.m88k.cmmu[1] = cmmu;
+
+	/*  This is also a 88200, revision 9:  */
+	cmmu->reg[CMMU_IDR] = (M88200_ID << 21) | (9 << 16);
+	cmmu->batc[8] = BATC8;
+	cmmu->batc[9] = BATC9;
+	snprintf(tmpstr, sizeof(tmpstr), "m8820x addr=0x%x addr2=%i", daddr, 1 + 2 * cpunr);
+	device_add(devinit->machine, tmpstr);
+}
+
+
+DEVINIT(luna88k)
+{
+	char n[100];
+	struct luna88k_data *d;
+
+	CHECK_ALLOCATION(d = (struct luna88k_data *) malloc(sizeof(struct luna88k_data)));
+	memset(d, 0, sizeof(struct luna88k_data));
+
+	// TODO: Values should correspond to the bootable disk id!
+	const int nsymbols = 2;
+	const char *s[2] = { "boot_unit", "boot_partition" };
+	const char *v[2] = { "0", "0" };
+	int base = 0x80; // 0x20 for luna-88k2
+	for (int si = 0; si < nsymbols; ++si) {
+		for (size_t i = 0; i < strlen(s[si]); ++i)
+			d->nvram[base + 4 * (32*si + i)] = s[si][i];
+		for (size_t i = 0; i < strlen(v[si]); ++i)
+			d->nvram[base + 4 * (32*si + 16 +i)] = v[si][i];
+	}
+
+	memset(d->lcd, ' ', sizeof(d->lcd));
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    LUNA88K_REGISTERS_BASE, LUNA88K_REGISTERS_LENGTH, dev_luna88k_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	/*
+	 *  Connect to the CPU's interrupt pin, and register
+	 *  6 hardware interrupts:
+	 */
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq[0]);
+
+	// HACK for trying out CPUs 1, 2 and 3. TODO: Base on devinit->interrupt_path instead.
+	if (devinit->machine->ncpus >= 2)
+		INTERRUPT_CONNECT("machine[0].cpu[1]", d->cpu_irq[1]);
+	if (devinit->machine->ncpus >= 3)
+		INTERRUPT_CONNECT("machine[0].cpu[2]", d->cpu_irq[2]);
+	if (devinit->machine->ncpus >= 4)
+		INTERRUPT_CONNECT("machine[0].cpu[3]", d->cpu_irq[3]);
+
+        for (int i = 1; i <= 6; i++) {
+                struct interrupt templ;
+                snprintf(n, sizeof(n), "%s.luna88k.%i", devinit->interrupt_path, i);
+
+                memset(&templ, 0, sizeof(templ));
+                templ.line = i;
+                templ.name = n;
+                templ.extra = d;
+                templ.interrupt_assert = luna88k_interrupt_assert;
+                templ.interrupt_deassert = luna88k_interrupt_deassert;
+
+		// debug("registering irq: %s\n", n);
+
+                interrupt_handler_register(&templ);
+        }
+
+	/*  Timer.  */
+	snprintf(n, sizeof(n), "%s.luna88k.6", devinit->interrupt_path);
+	INTERRUPT_CONNECT(n, d->timer_irq);
+	d->timer = timer_add(LUNA88K_PSEUDO_TIMER_HZ, luna88k_timer_tick, d);
+
+	machine_add_tickfunction(devinit->machine, dev_luna88k_tick, d, TICK_STEPS_SHIFT);
+
+	/*
+	 *  IRQ 5,4,3 (?): "autovec" according to OpenBSD
+	 *
+	 *  5 = sio0 (serial controller)
+	 *  4 = le0  (lance ethernet)
+	 *  3 = spc0 (SCSI)
+	 */
+	snprintf(n, sizeof(n), "%s.luna88k.5", devinit->interrupt_path);
+	INTERRUPT_CONNECT(n, d->sio_irq);
+
+	d->console_handle = console_start_slave(devinit->machine, "SIO", 1);
+	devinit->machine->main_console_handle = d->console_handle;
+
+	if (devinit->machine->ncpus > 4) {
+		printf("LUNA 88K can't have more than 4 CPUs.\n");
+		exit(1);
+	}
+
+	add_cmmu_for_cpu(devinit, 0, CMMU_I0, CMMU_D0);
+	add_cmmu_for_cpu(devinit, 1, CMMU_I1, CMMU_D1);
+	add_cmmu_for_cpu(devinit, 2, CMMU_I2, CMMU_D2);
+	add_cmmu_for_cpu(devinit, 3, CMMU_I3, CMMU_D3);
+
+	// The address is a hack because dev_le assumes that the data and register ports
+	// are at offset 0x100000 and "ram" (used for packets) is at 0x000000.
+	snprintf(n, sizeof(n), "%s.luna88k.4", devinit->interrupt_path);
+	dev_le_init(devinit->machine, devinit->machine->memory, LANCE_ADDR - 0x100000, 0, 0, n, DEV_LE_LENGTH);
+
+	// TODO: actual address from the le device!
+	// According to OpenBSD's if_le.c, the format for
+	// real Luna machines is 00000Axxxxxx.
+	const char *enaddr = "ENADDR=00000A102030";
+	size_t i = 0;
+	while (enaddr[i]) {
+		d->fuse_rom[i*2+0] = (enaddr[i] & 0xf0) << 24;
+		d->fuse_rom[i*2+1] = (enaddr[i] & 0x0f) << 28;
+		++i;
+	}
+
+	snprintf(n, sizeof(n), "mb89352 addr=0xE1000000 irq=%s.luna88k.3", devinit->interrupt_path);
+	device_add(devinit->machine, n);
+
+	if (devinit->machine->x11_md.in_use) {
+		d->using_framebuffer = true;
+		device_add(devinit->machine, "lunafb addr=0xB1000000");
+	}
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_luna88k.cc gxemul-0.7.0+dfsg/src/devices/dev_luna88k.cc
--- gxemul-0.6.2/src/devices/dev_luna88k.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_luna88k.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,669 +0,0 @@
-/*
- *  Copyright (C) 2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: OMRON Luna 88K-specific devices and control registers
- *
- *  Almost everything in here is just dummy code which returns nonsense,
- *  just enough to fake hardware well enough to get OpenBSD/luna88k to
- *  not stop early during bootup. It does not really work yet.
- *
- *  TODO: Separate out these devices to their own files, so that they can
- *  potentially be reused for a luna68k mode if necessary.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "console.h"
-#include "device.h"
-#include "devices.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/sccreg.h"	// similar to sio?
-#include "thirdparty/hitachi_hm53462_rop.h"
-#include "thirdparty/luna88k_board.h"
-#include "thirdparty/m8820x.h"
-
-#define	TICK_STEPS_SHIFT	14
-
-
-#define	LUNA88K_REGISTERS_BASE		0x3ffffff0UL
-#define	LUNA88K_REGISTERS_END		0xff000000UL
-#define	LUNA88K_REGISTERS_LENGTH	(LUNA88K_REGISTERS_END - LUNA88K_REGISTERS_BASE)
-
-#define	MAX_CPUS	4
-
-
-#define	BCD(x) ((((x) / 10) << 4) + ((x) % 10))
-
-
-struct luna88k_data {
-	struct vfb_data *fb;
-
-	struct interrupt cpu_irq;
-	bool		irqActive;
-	uint32_t	interrupt_enable[MAX_CPUS];
-	uint32_t	interrupt_status[MAX_CPUS];
-
-	uint32_t	software_interrupt_status[MAX_CPUS];
-
-	int		timer_tick_counter_bogus;
-	struct interrupt timer_irq;
-
-	int		console_handle;
-	int		interrupt_delay;
-	struct interrupt irqX;
-
-	/*  Two channels.  */
-	int		obio_sio_regno[2];
-	uint8_t		obio_sio_rr[2][8];
-	uint8_t		obio_sio_wr[2][8];
-
-	uint32_t	fuse_rom[FUSE_ROM_SPACE / sizeof(uint32_t)];
-	uint8_t		nvram[NVRAM_SPACE];
-};
-
-
-static void reassert_interrupts(struct luna88k_data *d)
-{
-	// printf("status = 0x%08x, enable = 0x%08x\n",
-	//	d->interrupt_status[0], d->interrupt_enable[0]);
-
-        if (d->interrupt_status[0] & d->interrupt_enable[0]) {
-		if (!d->irqActive)
-	                INTERRUPT_ASSERT(d->cpu_irq);
-
-		d->irqActive = true;
-	} else {
-		if (d->irqActive)
-	                INTERRUPT_DEASSERT(d->cpu_irq);
-
-		d->irqActive = false;
-	}
-}
-
-static void luna88k_interrupt_assert(struct interrupt *interrupt)
-{
-        struct luna88k_data *d = (struct luna88k_data *) interrupt->extra;
-	d->interrupt_status[0] |= (1 << (interrupt->line + 25));
-	reassert_interrupts(d);
-}
-
-static void luna88k_interrupt_deassert(struct interrupt *interrupt)
-{
-        struct luna88k_data *d = (struct luna88k_data *) interrupt->extra;
-	d->interrupt_status[0] &= ~(1 << (interrupt->line + 25));
-	reassert_interrupts(d);
-}
-
-
-static void reassert_serial_interrupt(struct luna88k_data* d)
-{
-	bool assertSerial = false;
-
-	if (d->fb != NULL) {
-		/*  Workstation keyboard:  */
-		if ((d->obio_sio_wr[1][SCC_WR1] & SCC_WR1_RXI_ALL_CHAR) ||
-		    (d->obio_sio_wr[1][SCC_WR1] & SCC_WR1_RXI_FIRST_CHAR)) {
-			if (console_charavail(d->console_handle))
-				assertSerial = true;
-		}
-	} else {
-		/*  Serial:  */
-		if ((d->obio_sio_wr[0][SCC_WR1] & SCC_WR1_RXI_ALL_CHAR) ||
-		    (d->obio_sio_wr[0][SCC_WR1] & SCC_WR1_RXI_FIRST_CHAR)) {
-			if (console_charavail(d->console_handle))
-				assertSerial = true;
-		}
-	}
-
-	if (d->obio_sio_wr[0][SCC_WR1] & SCC_WR1_TX_IE) {
-		assertSerial = true;
-	}
-
-	if (d->interrupt_delay > 0) {
-		assertSerial = false;
-		d->interrupt_delay --;
-	}
-
-	if (assertSerial) {
-		INTERRUPT_ASSERT(d->irqX);
-		d->interrupt_delay = 130;
-	} else {
-		INTERRUPT_DEASSERT(d->irqX);
-	}
-}
-
-
-DEVICE_TICK(luna88k)
-{
-	struct luna88k_data *d = (struct luna88k_data *) extra;
-
-	/*  TODO: Correct timing.  */
-	if (d->timer_tick_counter_bogus < 3) {
-		if (++d->timer_tick_counter_bogus >= 3)
-			INTERRUPT_ASSERT(d->timer_irq);
-	}
-
-	/*  Serial:  */
-	reassert_serial_interrupt(d);
-}
-
-
-static void swapBitOrder(uint8_t* data, int len)
-{
-	for (int bo = 0; bo < len; bo ++)
-	{
-		uint8_t b = (uint8_t)data[bo];
-		uint8_t c = 0x00;
-		for (int i = 0; i < 8; i++)
-		{
-			if (b & (128 >> i))
-				c |= (1 << i);
-		}
-
-		data[bo] = c;
-	}
-}
-
-
-DEVICE_ACCESS(luna88k)
-{
-	struct tm *tmp;
-	time_t timet;
- 	uint32_t addr = relative_addr + LUNA88K_REGISTERS_BASE;
-	uint64_t idata = 0, odata = 0;
-	struct luna88k_data *d = (struct luna88k_data *) extra;
-	int cpunr;
-	int sio_devnr;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (addr >= FUSE_ROM_ADDR && len == sizeof(uint32_t) &&
-	    addr < FUSE_ROM_ADDR + FUSE_ROM_SPACE) {
-		if (writeflag == MEM_READ) {
-			odata = d->fuse_rom[(addr - FUSE_ROM_ADDR) / sizeof(uint32_t)];
-			memory_writemax64(cpu, data, len, odata);
-		} else {
-			d->fuse_rom[(addr - FUSE_ROM_ADDR) / sizeof(uint32_t)] = idata;
-		}
-		return 1;
-	}
-
-	if (addr >= FUSE_ROM_ADDR && len == sizeof(uint8_t) &&
-	    addr < FUSE_ROM_ADDR + FUSE_ROM_SPACE) {
-		if (writeflag == MEM_READ) {
-			odata = d->fuse_rom[(addr - FUSE_ROM_ADDR) / sizeof(uint32_t)];
-			odata >>= ((3 - (addr & 3)) * 8);
-			memory_writemax64(cpu, data, len, odata);
-		} else {
-			fatal("TODO: luna88k byte write to fuse\n");
-		}
-		return 1;
-	}
-
-	if (addr >= NVRAM_ADDR && addr + len <= NVRAM_ADDR + NVRAM_SPACE) {
-		size_t offset = addr - NVRAM_ADDR;
-		if (writeflag == MEM_READ) {
-			memmove(data, d->nvram + offset, len);
-		} else {
-			memmove(d->nvram + offset, data, len);
-		}
-		return 1;
-	}
-
-	if (addr >= NVRAM_ADDR_88K2 && addr < NVRAM_ADDR_88K2 + NVRAM_SPACE && len == sizeof(uint8_t)) {
-		if (writeflag == MEM_READ) {
-			odata = d->nvram[addr - NVRAM_ADDR_88K2];
-			memory_writemax64(cpu, data, len, odata);
-		} else {
-			d->nvram[addr - NVRAM_ADDR_88K2] = idata;
-		}
-		return 1;
-	}
-
-	if (addr >= BMAP_BMP && addr < BMAP_BMP + 0x40000) {
-		// X resolution is 1280, but stride is 2048.
-		uint32_t s = 2048 * 1024 / 8;
-		addr -= (uint64_t)(uint32_t)(BMAP_BMP);
-		swapBitOrder(data, len);
-		if (addr + len - 1 < s) {
-			if (addr >= 8)
-				addr -= 8;
-			dev_fb_access(cpu, cpu->mem, addr, data, len, writeflag, d->fb);
-			swapBitOrder(data, len);
-			return 1;
-		}
-		else
-			return 1;
-	}
-
-	if (addr >= BMAP_BMAP0 && addr < BMAP_BMAP0 + 0x40000) {
-		// X resolution is 1280, but stride is 2048.
-		uint32_t s = 2048 * 1024 / 8;
-		addr -= (uint64_t)(uint32_t)(BMAP_BMAP0);
-		swapBitOrder(data, len);
-		if (addr + len - 1 < s) {
-			if (addr >= 8)
-				addr -= 8;
-			dev_fb_access(cpu, cpu->mem, addr, data, len, writeflag, d->fb);
-			swapBitOrder(data, len);
-			return 1;
-		}
-		else
-			return 1;
-	}
-
-	if (addr >= BMAP_PALLET2 && addr < BMAP_PALLET2 + 16) {
-		/*  Ignore for now.  */
-		return 1;
-	}
-
-	if (addr >= TRI_PORT_RAM && addr < TRI_PORT_RAM + TRI_PORT_RAM_SPACE) {
-		/*  Ignore for now.  */
-		return 1;
-	}
-
-	switch (addr) {
-
-	case 0x3ffffff0:
-		/*  Accessed by OpenBSD/luna88k to trigger an illegal address  */
-		cpu->cd.m88k.cmmu[1]->reg[CMMU_PFSR] = CMMU_PFSR_BERROR << 16;
-		break;
-
-	case PROM_ADDR:		/*  0x41000000  */
-		/*  OpenBSD/luna88k write here during boot. Ignore for now. (?)  */
-		break;
-
-	case OBIO_CAL_CTL:	/*  calendar control register  */
-		break;
-	case OBIO_CAL_SEC:
-		timet = time(NULL); tmp = gmtime(&timet);
-		odata = BCD(tmp->tm_sec) << 24;
-		break;
-	case OBIO_CAL_MIN:
-		timet = time(NULL); tmp = gmtime(&timet);
-		odata = BCD(tmp->tm_min) << 24;
-		break;
-	case OBIO_CAL_HOUR:
-		timet = time(NULL); tmp = gmtime(&timet);
-		odata = BCD(tmp->tm_hour) << 24;
-		break;
-	case OBIO_CAL_DOW:
-		timet = time(NULL); tmp = gmtime(&timet);
-		odata = BCD(tmp->tm_wday + 0) << 24;
-		break;
-	case OBIO_CAL_DAY:
-		timet = time(NULL); tmp = gmtime(&timet);
-		odata = BCD(tmp->tm_mday) << 24;
-		break;
-	case OBIO_CAL_MON:
-		timet = time(NULL); tmp = gmtime(&timet);
-		odata = BCD(tmp->tm_mon + 1) << 24;
-		break;
-	case OBIO_CAL_YEAR:
-		timet = time(NULL); tmp = gmtime(&timet);
-		odata = BCD(tmp->tm_year - 2000) << 24;  // ?
-		break;
-
-	case OBIO_PIO0A:	/*  0x49000000: PIO-0 port A  */
-		/*  OpenBSD reads dipswitch settings from PIO0A and B.  */
-		odata = 0;	// high byte
-		if (cpu->machine->x11_md.in_use)
-			odata |= 0x40;
-		odata |= 0x80;	// multi-user mode
-		odata |= 0x20;	// don't ask name
-		odata |= 0x10;	// don't do manual UKC config
-		break;
-
-	case OBIO_PIO0B:	/*  0x49000004: PIO-0 port B  */
-		/*  OpenBSD reads dipswitch settings from PIO0A and B.  */
-		odata = 0x00;	// low byte
-		break;
-
-	case OBIO_PIO0:		/*  0x4900000C: PIO-0 control  */
-		/*  TODO: Implement for real.  */
-		break;
-
-	case OBIO_PIO1A:	/*  0x4d000000: PIO-0 port A  */
-	case OBIO_PIO1B:	/*  0x4d000004: PIO-0 port B  */
-	case OBIO_PIO1:		/*  0x4d00000C: PIO-0 control  */
-		/*  Ignore for now. (?)  */
-		break;
-
-	case OBIO_SIO + 0:	/*  0x51000000: data channel 0 */
-	case OBIO_SIO + 4:	/*  0x51000004: cmd channel 0 */
-	case OBIO_SIO + 8:	/*  0x51000008: data channel 1 */
-	case OBIO_SIO + 0xc:	/*  0x5100000c: cmd channel 1 */
-		sio_devnr = ((addr - OBIO_SIO) / 8) & 1;
-
-		if ((addr - OBIO_SIO) & 4) {
-			/*  cmd  */
-
-			/*  Similar to dev_scc.cc ?  */
-			if (writeflag == MEM_WRITE) {
-				if (d->obio_sio_regno[sio_devnr] == 0) {
-					int regnr = idata & 7;
-
-					d->obio_sio_regno[sio_devnr] = regnr;
-
-					// printf("[ sio: setting regno for next operation to 0x%02x ]\n", (int)regnr);
-
-					/*  High bits are command.  */
-				} else {
-					int regnr = d->obio_sio_regno[sio_devnr] & 7;
-					d->obio_sio_wr[sio_devnr][regnr] = idata;
-
-					// printf("[ sio: setting reg 0x%02x = 0x%02x ]\n", d->obio_sio_regno[sio_devnr], (int)idata);
-
-					d->obio_sio_regno[sio_devnr] = 0;
-
-					reassert_serial_interrupt(d);
-				}
-			} else {
-				d->obio_sio_rr[sio_devnr][SCC_RR0] = SCC_RR0_TX_EMPTY | SCC_RR0_DCD | SCC_RR0_CTS;
-
-				if (console_charavail(d->console_handle) &&
-				      ( (d->fb == NULL && sio_devnr == 0) ||
-					(d->fb != NULL && sio_devnr == 1)) )
-					d->obio_sio_rr[sio_devnr][SCC_RR0] |= SCC_RR0_RX_AVAIL;
-
-				d->obio_sio_rr[sio_devnr][SCC_RR1] = SCC_RR1_ALL_SENT;
-
-				int regnr = d->obio_sio_regno[sio_devnr] & 7;
-				odata = d->obio_sio_rr[sio_devnr][regnr];
-				// printf("[ sio: reading reg 0x%02x: 0x%02x ]\n", regnr, (int)odata);
-				d->obio_sio_regno[sio_devnr] = 0;
-			}
-		} else {
-			/*  data  */
-			if (writeflag == MEM_WRITE) {
-				if (sio_devnr == 0) {
-					console_putchar(cpu->machine->main_console_handle, idata);
-				} else
-					fatal("[ luna88k sio dev1 write data: TODO ]\n");
-			} else {
-				if (sio_devnr == 0) {
-					if (d->fb == NULL && console_charavail(d->console_handle)) {
-						odata = console_readchar(d->console_handle);
-					}
-				} else {
-					fatal("[ luna88k sio dev1 read data: TODO ]\n");
-				}
-			}
-
-			INTERRUPT_DEASSERT(d->irqX);
-		}
-
-		break;
-
-	case OBIO_CLOCK0:	/*  0x63000000: Clock ack?  */
-		d->timer_tick_counter_bogus = 0;
-		INTERRUPT_DEASSERT(d->timer_irq);
-		break;
-
-	case INT_ST_MASK0:	/*  0x65000000: Interrupt status CPU 0.  */
-	case INT_ST_MASK1:	/*  0x65000004: Interrupt status CPU 1.  */
-	case INT_ST_MASK2:	/*  0x65000008: Interrupt status CPU 2.  */
-	case INT_ST_MASK3:	/*  0x6500000c: Interrupt status CPU 3.  */
-		/*
-		 *  From OpenBSD/luna88k machdep.c source code:
-		 *
-		 *  On write: Bits 31..26 are used to enable/disable levels 6..1.
-		 *  On read: Bits 31..29 show value 0-7 of current interrupt.
-		 *           Bits 23..18 show current mask.
-		 */
-		cpunr = (addr - INT_ST_MASK0) / 4;
-		if (writeflag == MEM_WRITE) {
-			if ((idata & 0x03ffffff) != 0x00000000) {
-				fatal("[ TODO: luna88k interrupts, idata = 0x%08x, what to do with low bits? ]\n", (uint32_t)idata);
-				exit(1);
-			}
-
-			d->interrupt_enable[cpunr] = idata;
-			reassert_interrupts(d);
-		} else {
-			uint32_t currentMask = d->interrupt_enable[cpunr];
-			int highestCurrentStatus = 0;
-			odata = currentMask >> 8;
-			
-			for (int i = 1; i <= 6; ++i) {
-				int m = 1 << (25 + i);
-				if (d->interrupt_status[cpunr] & m)
-					highestCurrentStatus = i;
-			}
-
-			odata |= (highestCurrentStatus << 29);
-			// printf("highest = %i 0x%08x\n", highestCurrentStatus, (int)odata);
-		}
-
-		break;
-
-	case SOFT_INT0:		/*  0x69000000: Software Interrupt status CPU 0.  */
-	case SOFT_INT1:		/*  0x69000004: Software Interrupt status CPU 1.  */
-	case SOFT_INT2:		/*  0x69000008: Software Interrupt status CPU 2.  */
-	case SOFT_INT3:		/*  0x6900000c: Software Interrupt status CPU 3.  */
-		cpunr = (addr - SOFT_INT0) / 4;
-		odata = d->software_interrupt_status[cpunr];
-
-		// Reading status clears it.
-		d->software_interrupt_status[cpunr] = 0;
-
-		if (writeflag == MEM_WRITE) {
-			fatal("TODO: luna88k write to software interrupts\n");
-			exit(1);
-		}
-		break;
-
-	case RESET_CPU_ALL:	/*  0x6d000010: Reset all CPUs  */
-		cpu->running = 0;
-		break;
-
-	case BMAP_RFCNT:	/*  0xb1000000: RFCNT register  */
-		/*  video h-origin/v-origin, according to OpenBSD  */
-		/*  Ignore for now. (?)  */
-		break;
-
-	case BMAP_BMSEL:	/*  0xb1000000: BMSEL register  */
-		/*  Ignore for now. (?)  */
-		break;
-
-	case BMAP_BMAP1:	/*  0xb1100000: Bitmap plane 1  */
-		odata = 0xc0dec0de;
-		/*  Return dummy value. OpenBSD writes and reads to detect presence
-		    of bitplanes.  */
-		break;
-
-	case BMAP_FN + 4 * ROP_THROUGH:	/*  0xb12c0014: "common bitmap function"  */
-		/*  Function 5 is "ROP copy", according to OpenBSD sources.  */
-		/*  See hitachi_hm53462_rop.h  */
-		if (writeflag == MEM_READ) {
-			fatal("[ TODO: luna88k READ from BMAP_FN ROP register? ]\n");
-			cpu->running = 0;
-			return 0;
-		}
-		if (idata != 0xffffffff) {
-			fatal("[ TODO: luna88k write which does not set ALL bits? ]\n");
-			cpu->running = 0;
-			return 0;
-		}
-		break;
-
-	case SCSI_ADDR + 0x00:	/*  0xe1000000: SCSI ..  */
-	case SCSI_ADDR + 0x04:	/*  0xe1000004: SCSI ..  */
-	case SCSI_ADDR + 0x08:	/*  0xe1000008: SCSI ..  */
-	case SCSI_ADDR + 0x0C:	/*  0xe100000C: SCSI ..  */
-	case SCSI_ADDR + 0x20:	/*  0xe1000020: SCSI ..  */
-	case SCSI_ADDR + 0x2c:	/*  0xe100002c: SCSI ..  */
-	case SCSI_ADDR + 0x30:	/*  0xe1000030: SCSI ..  */
-	case SCSI_ADDR + 0x34:	/*  0xe1000034: SCSI ..  */
-	case SCSI_ADDR + 0x38:	/*  0xe1000038: SCSI ..  */
-	case SCSI_ADDR + 0x40:	/*  0xe1000040: SCSI ..  */
-	case SCSI_ADDR + 0x44:	/*  0xe1000044: SCSI ..  */
-	case SCSI_ADDR + 0x48:	/*  0xe1000048: SCSI ..  */
-	case SCSI_ADDR + 0x4c:	/*  0xe100004c: SCSI ..  */
-	case SCSI_ADDR + 0x50:	/*  0xe1000050: SCSI ..  */
-	case SCSI_ADDR + 0x60:	/*  0xe1000060: SCSI ..  */
-	case SCSI_ADDR + 0x6c:	/*  0xe100006c: SCSI ..  */
-	case SCSI_ADDR + 0x70:	/*  0xe1000070: SCSI ..  */
-	case SCSI_ADDR + 0x74:	/*  0xe1000074: SCSI ..  */
-	case SCSI_ADDR + 0x78:	/*  0xe1000078: SCSI ..  */
-		/*  MB89352 SCSI Protocol Controller  */
-		/*  Ignore for now. (?)  */
-		break;
-
-	case SCSI_ADDR + 0x10:	/*  0xe1000010: SCSI INTS  */
-		odata = 0xffffffff;
-		break;
-
-	case 0xf1000000:	/*  Lance Ethernet. TODO.  */
-	case 0xf1000004:
-	case 0xf1000008:
-		break;
-
-	default:fatal("[ luna88k: unimplemented %s address 0x%x",
-		    writeflag == MEM_WRITE? "write to" : "read from",
-		    (int) addr);
-		if (writeflag == MEM_WRITE)
-			fatal(": 0x%x", (int)idata);
-		fatal(" (%i bits) ]\n", len * 8);
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-void add_cmmu_for_cpu(struct devinit* devinit, int cpunr, uint32_t iaddr, uint32_t daddr)
-{
-	char tmpstr[300];
-	struct m8820x_cmmu *cmmu;
-
-	/*  Instruction CMMU:  */
-	CHECK_ALLOCATION(cmmu = (struct m8820x_cmmu *) malloc(sizeof(struct m8820x_cmmu)));
-	memset(cmmu, 0, sizeof(struct m8820x_cmmu));
-
-	if (cpunr < devinit->machine->ncpus)
-		devinit->machine->cpus[cpunr]->cd.m88k.cmmu[0] = cmmu;
-
-	/*  This is a 88200, revision 9:  */
-	cmmu->reg[CMMU_IDR] = (M88200_ID << 21) | (9 << 16);
-	snprintf(tmpstr, sizeof(tmpstr), "m8820x addr=0x%x addr2=0", iaddr);
-	device_add(devinit->machine, tmpstr);
-
-	/*  ... and data CMMU:  */
-	CHECK_ALLOCATION(cmmu = (struct m8820x_cmmu *) malloc(sizeof(struct m8820x_cmmu)));
-	memset(cmmu, 0, sizeof(struct m8820x_cmmu));
-
-	if (cpunr < devinit->machine->ncpus)
-		devinit->machine->cpus[cpunr]->cd.m88k.cmmu[1] = cmmu;
-
-	/*  This is also a 88200, revision 9:  */
-	cmmu->reg[CMMU_IDR] = (M88200_ID << 21) | (9 << 16);
-	cmmu->batc[8] = BATC8;
-	cmmu->batc[9] = BATC9;
-	snprintf(tmpstr, sizeof(tmpstr), "m8820x addr=0x%x addr2=1", daddr);
-	device_add(devinit->machine, tmpstr);
-}
-
-
-DEVINIT(luna88k)
-{
-	char n[100];
-	struct luna88k_data *d;
-
-	CHECK_ALLOCATION(d = (struct luna88k_data *) malloc(sizeof(struct luna88k_data)));
-	memset(d, 0, sizeof(struct luna88k_data));
-
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    LUNA88K_REGISTERS_BASE, LUNA88K_REGISTERS_LENGTH, dev_luna88k_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	/*
-	 *  Connect to the CPU's interrupt pin, and register
-	 *  6 hardware interrupts:
-	 */
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
-        for (int i = 1; i <= 6; i++) {
-                struct interrupt templ;
-                snprintf(n, sizeof(n), "%s.luna88k.%i", devinit->interrupt_path, i);
-
-                memset(&templ, 0, sizeof(templ));
-                templ.line = i;
-                templ.name = n;
-                templ.extra = d;
-                templ.interrupt_assert = luna88k_interrupt_assert;
-                templ.interrupt_deassert = luna88k_interrupt_deassert;
-
-		// debug("registering irq: %s\n", n);
-
-                interrupt_handler_register(&templ);
-        }
-
-	/*  Timer.  */
-	snprintf(n, sizeof(n), "%s.luna88k.6", devinit->interrupt_path);
-	INTERRUPT_CONNECT(n, d->timer_irq);
-	machine_add_tickfunction(devinit->machine,
-	    dev_luna88k_tick, d, TICK_STEPS_SHIFT);
-
-	/*  IRQ 5,4,3 (?): "autovec" according to OpenBSD  */
-	snprintf(n, sizeof(n), "%s.luna88k.5", devinit->interrupt_path);
-	INTERRUPT_CONNECT(n, d->irqX);
-
-	d->console_handle = console_start_slave(devinit->machine, "SIO", 1);
-
-	if (devinit->machine->x11_md.in_use)
-	{
-		d->fb = dev_fb_init(devinit->machine, devinit->machine->memory,
-			0x100000000ULL + BMAP_BMAP0, VFB_GENERIC,
-			1280, 1024, 2048, 1024, 1, "LUNA 88K");
-	}
-
-	if (devinit->machine->ncpus > 4)
-	{
-		printf("LUNA 88K can't have more than 4 CPUs.\n");
-		exit(1);
-	}
-
-	add_cmmu_for_cpu(devinit, 0, CMMU_I0, CMMU_D0);
-	add_cmmu_for_cpu(devinit, 1, CMMU_I1, CMMU_D1);
-	add_cmmu_for_cpu(devinit, 2, CMMU_I2, CMMU_D2);
-	add_cmmu_for_cpu(devinit, 3, CMMU_I3, CMMU_D3);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_lunafb.c gxemul-0.7.0+dfsg/src/devices/dev_lunafb.c
--- gxemul-0.6.2/src/devices/dev_lunafb.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_lunafb.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,239 @@
+/*
+ *  Copyright (C) 2018-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: LUNA framebuffer
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/hitachi_hm53462_rop.h"
+#include "thirdparty/luna88k_board.h"
+
+
+// Unfortunately, the framebuffer device isn't really meant to have an 8 byte
+// offset into framebuffer memory, which OpenBSD seems to use. So for now,
+// dyntrans access to the framebuffer memory is disabled.
+static bool use_dyntrans = false;
+
+
+
+struct lunafb_data {
+	struct vfb_data *fb;
+};
+
+
+DEVICE_ACCESS(lunafb_a)
+{
+ 	uint32_t addr = relative_addr + BMAP_START;
+	uint64_t idata = 0, odata = 0;
+	// struct lunafb_data *d = (struct lunafb_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (addr) {
+
+	case BMAP_RFCNT:	/*  0xb1000000: RFCNT register  */
+		/*  video h-origin/v-origin, according to OpenBSD  */
+		/*  Ignore for now. (?)  */
+		break;
+
+	case BMAP_BMSEL:	/*  0xb1000000: BMSEL register  */
+		/*  Ignore for now. Used by OpenBSD's omfb_clear_framebuffer.  */
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			debugmsg_cpu(cpu, SUBSYS_DEVICE, "lunafb_a", VERBOSITY_ERROR,
+		    	    "unimplemented %i-bit WRITE to address 0x%x: 0x%x",
+		    	    len * 8,
+			    (int) addr,
+			    (int) idata);
+		else
+			debugmsg_cpu(cpu, SUBSYS_DEVICE, "lunafb_a", VERBOSITY_ERROR,
+		    	    "unimplemented %i-bit READ from address 0x%x",
+		    	    len * 8,
+			    (int) addr);
+
+		// Stop the emulation immediately.
+		cpu->running = 0;
+		return 0;
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(lunafb_bmp)
+{
+	struct lunafb_data *d = (struct lunafb_data *) extra;
+
+	if (!use_dyntrans && relative_addr >= 8)
+		relative_addr -= 8;
+
+	if (relative_addr + len - 1 < 0x40000)
+		dev_fb_access(cpu, cpu->mem, relative_addr, data, len, writeflag, d->fb);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(lunafb_bmap0)
+{
+	struct lunafb_data *d = (struct lunafb_data *) extra;
+
+	if (!use_dyntrans && relative_addr >= 8)
+		relative_addr -= 8;
+
+	if (relative_addr + len - 1 < 0x40000)
+		dev_fb_access(cpu, cpu->mem, relative_addr, data, len, writeflag, d->fb);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(lunafb_b)
+{
+ 	uint32_t addr = relative_addr + BMAP_BMAP1;
+	uint64_t idata = 0, odata = 0;
+	// struct lunafb_data *d = (struct lunafb_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (addr >= BMAP_PALLET2 && addr < BMAP_PALLET2 + 16) {
+		/*  Ignore for now.  */
+		return 1;
+	}
+
+	switch (addr) {
+
+	case BMAP_BMAP1:	/*  0xb1100000: Bitmap plane 1  */
+		/*  Return a dummy value. OpenBSD writes and reads to
+		    detect presence of bitplanes.  */
+		odata = 0;
+		break;
+
+	case BMAP_FN + 4 * ROP_THROUGH:	/*  0xb12c0014: "common bitmap function"  */
+		/*  Function 5 is "ROP copy", according to OpenBSD sources.  */
+		/*  See hitachi_hm53462_rop.h  */
+		if (writeflag == MEM_READ) {
+			debugmsg_cpu(cpu, SUBSYS_DEVICE, "lunafb_b", VERBOSITY_ERROR,
+		    	    "TODO: lunafb READ from BMAP_FN ROP register");
+			cpu->running = 0;
+			return 0;
+		}
+		if (idata != 0xffffffff) {
+			debugmsg_cpu(cpu, SUBSYS_DEVICE, "lunafb_b", VERBOSITY_ERROR,
+		    	    "TODO: lunafb write which does not set ALL bits");
+			cpu->running = 0;
+			return 0;
+		}
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			debugmsg_cpu(cpu, SUBSYS_DEVICE, "lunafb_b", VERBOSITY_ERROR,
+		    	    "unimplemented %i-bit WRITE to address 0x%x: 0x%x",
+		    	    len * 8,
+			    (int) addr,
+			    (int) idata);
+		else
+			debugmsg_cpu(cpu, SUBSYS_DEVICE, "lunafb_b", VERBOSITY_ERROR,
+		    	    "unimplemented %i-bit READ from address 0x%x",
+		    	    len * 8,
+			    (int) addr);
+
+		// Stop the emulation immediately.
+		cpu->running = 0;
+		return 0;
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(lunafb)
+{
+	struct lunafb_data *d;
+
+	CHECK_ALLOCATION(d = (struct lunafb_data *) malloc(sizeof(struct lunafb_data)));
+	memset(d, 0, sizeof(struct lunafb_data));
+
+	/*
+	 *  OpenBSD/luna88k uses both BMAP_BMP _and_ BMAP_BMAP0. During
+	 *  normal bootup, it uses both approximately the same amount.
+	 *  However, when running X11, it seems to use BMAP_BMAP0 more.
+	 *  So, BMAP0 is the one that is used for the actual framebuffer
+	 *  (meaning that fast dyntrans accesses to those pages is possible),
+	 *  and a slow "forwarding device" at BMAP_BMP is also registered.
+	 *
+	 *  Unfortunately, this means that the rest of the registers are
+	 *  split up into two parts, lunafb_a and lunafb_b.
+	 */
+
+	d->fb = dev_fb_init(devinit->machine, devinit->machine->memory,
+		use_dyntrans ? BMAP_BMAP0 : 0x2ff000000, VFB_REVERSEBITS,
+		1280, 1024, 2048, 1024, 1, "LUNA 88K");
+
+	memory_device_register(devinit->machine->memory, "lunafb_a",
+	    devinit->addr, 0x80000, dev_lunafb_a_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	memory_device_register(devinit->machine->memory, "lunafb_bmp",
+	    BMAP_BMP, BMAP_BMAP0 - BMAP_BMP, dev_lunafb_bmp_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	if (!use_dyntrans)
+		memory_device_register(devinit->machine->memory, "lunafb_bmap0",
+		    BMAP_BMAP0, BMAP_BMAP1 - BMAP_BMAP0, dev_lunafb_bmap0_access, (void *)d,
+		    DM_DEFAULT, NULL);
+
+	memory_device_register(devinit->machine->memory, "lunafb_b",
+	    BMAP_BMAP1, SCSI_ADDR - BMAP_BMAP1, dev_lunafb_b_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	return 1;
+}
+
+
diff -Nru gxemul-0.6.2/src/devices/dev_m8820x.c gxemul-0.7.0+dfsg/src/devices/dev_m8820x.c
--- gxemul-0.6.2/src/devices/dev_m8820x.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_m8820x.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,248 @@
+/*
+ *  Copyright (C) 2007-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: M88200/M88204 CMMU (Cache/Memory Management Unit)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/m8820x.h"
+#include "thirdparty/m8820x_pte.h"
+
+
+struct m8820x_data {
+	int		cpu_nr;
+	int		cmmu_nr;
+};
+
+
+/*
+ *  m8820x_command():
+ *
+ *  Handle M8820x commands written to the System Command Register.
+ */
+static void m8820x_command(struct cpu *cpu, struct m8820x_data *d)
+{
+	uint32_t *regs = cpu->cd.m88k.cmmu[d->cmmu_nr]->reg;
+	int cmd = regs[CMMU_SCR];
+	uint32_t sar = regs[CMMU_SAR];
+	size_t i;
+	uint32_t super, all;
+
+	switch (cmd) {
+
+	case CMMU_FLUSH_CACHE_CB_LINE:
+	case CMMU_FLUSH_CACHE_CB_PAGE:
+	case CMMU_FLUSH_CACHE_INV_LINE:
+	case CMMU_FLUSH_CACHE_INV_PAGE:
+	case CMMU_FLUSH_CACHE_INV_ALL:
+	case CMMU_FLUSH_CACHE_CBI_LINE:
+	case CMMU_FLUSH_CACHE_CBI_PAGE:
+	case CMMU_FLUSH_CACHE_CBI_SEGMENT:
+	case CMMU_FLUSH_CACHE_CBI_ALL:
+		/*  TODO  */
+		break;
+
+	case CMMU_FLUSH_USER_ALL:
+	case CMMU_FLUSH_USER_PAGE:
+	case CMMU_FLUSH_SUPER_ALL:
+	case CMMU_FLUSH_SUPER_PAGE:
+		/*  TODO: Segment invalidation.  */
+
+		all = super = 0;
+		if (cmd == CMMU_FLUSH_USER_ALL ||
+		    cmd == CMMU_FLUSH_SUPER_ALL)
+			all = 1;
+		if (cmd == CMMU_FLUSH_SUPER_ALL ||
+		    cmd == CMMU_FLUSH_SUPER_PAGE)
+			super = M8820X_PATC_SUPERVISOR_BIT;
+
+		/*  TODO: Don't invalidate EVERYTHING like this!  */
+		cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
+
+		for (i=0; i<N_M88200_PATC_ENTRIES; i++) {
+			uint32_t v = cpu->cd.m88k.cmmu[d->cmmu_nr]
+			    ->patc_v_and_control[i];
+			uint32_t p = cpu->cd.m88k.cmmu[d->cmmu_nr]
+			    ->patc_p_and_supervisorbit[i];
+
+			/*  Already invalid? Then skip this entry.  */
+			if (!(v & PG_V))
+				continue;
+
+			/*  Super/user mismatch? Then skip the entry.  */
+			if ((p & M8820X_PATC_SUPERVISOR_BIT) != super)
+				continue;
+
+			/*  If not all pages are to be invalidated, there
+			    must be a virtual address match:  */
+			if (!all && (sar & 0xfffff000) != (v & 0xfffff000))
+				continue;
+
+			/*  Finally, invalidate the entry:  */
+			cpu->cd.m88k.cmmu[d->cmmu_nr]->patc_v_and_control[i]
+			    = v & ~PG_V;
+		}
+
+		break;
+
+	default:
+		fatal("[ m8820x_command: FATAL ERROR! unimplemented "
+		    "command 0x%02x ]\n", cmd);
+		exit(1);
+	}
+}
+
+
+DEVICE_ACCESS(m8820x)
+{
+	// NOTE:
+	//	cpu is the struct cpu* of the processor doing the device access.
+	//	c   is the struct cpu* where the M88200 CMMU is located.
+	uint64_t idata = 0, odata = 0;
+	struct m8820x_data *d = (struct m8820x_data *) extra;
+	struct cpu* c = cpu->machine->cpus[d->cpu_nr];
+	uint32_t *regs = c->cd.m88k.cmmu[d->cmmu_nr]->reg;
+	uint32_t *batc = c->cd.m88k.cmmu[d->cmmu_nr]->batc;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (writeflag == MEM_READ)
+		odata = regs[relative_addr / sizeof(uint32_t)];
+
+	switch (relative_addr / sizeof(uint32_t)) {
+
+	case CMMU_IDR:
+		if (writeflag == MEM_WRITE) {
+			fatal("m8820x: write to CMMU_IDR: TODO\n");
+			exit(1);
+		}
+		break;
+
+	case CMMU_SCR:
+		if (writeflag == MEM_READ) {
+			fatal("m8820x: read from CMMU_SCR: TODO\n");
+			exit(1);
+		} else {
+			regs[relative_addr / sizeof(uint32_t)] = idata;
+			m8820x_command(c, d);
+		}
+		break;
+
+	case CMMU_SSR:
+		if (writeflag == MEM_WRITE) {
+			fatal("m8820x: write to CMMU_SSR: TODO\n");
+			exit(1);
+		}
+		break;
+
+	case CMMU_PFSR:
+	case CMMU_PFAR:
+	case CMMU_SAR:
+	case CMMU_SCTR:
+	case CMMU_SAPR:		/*  TODO: Invalidate something for  */
+	case CMMU_UAPR:		/*  SAPR and UAPR writes?  */
+		/*  TODO: Don't invalidate everything.  */
+		c->invalidate_translation_caches(c, 0, INVALIDATE_ALL);
+		if (writeflag == MEM_WRITE)
+			regs[relative_addr / sizeof(uint32_t)] = idata;
+		break;
+
+	case CMMU_BWP0:
+	case CMMU_BWP1:
+	case CMMU_BWP2:
+	case CMMU_BWP3:
+	case CMMU_BWP4:
+	case CMMU_BWP5:
+	case CMMU_BWP6:
+	case CMMU_BWP7:
+		if (writeflag == MEM_WRITE) {
+			uint32_t old;
+			int i = (relative_addr / sizeof(uint32_t)) - CMMU_BWP0;
+
+			regs[relative_addr / sizeof(uint32_t)] = idata;
+
+			/*  Also write to the specific batc registers:  */
+			old = batc[i];
+			batc[i] = idata;
+			if (old != idata) {
+				/*  TODO: Don't invalidate everything?  */
+				c->invalidate_translation_caches(
+				    c, 0, INVALIDATE_ALL);
+			}
+		}
+		break;
+
+	case CMMU_CSSP0:
+		/*  TODO: Actually care about cache details.  */
+		break;
+
+	default:fatal("[ m8820x: unimplemented %s offset 0x%x",
+		    writeflag == MEM_WRITE? "write to" : "read from",
+		    (int) relative_addr);
+		if (writeflag == MEM_WRITE)
+			fatal(": 0x%x", (int)idata);
+		fatal(" ]\n");
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(m8820x)
+{
+	struct m8820x_data *d;
+
+	CHECK_ALLOCATION(d = (struct m8820x_data *) malloc(sizeof(struct m8820x_data)));
+	memset(d, 0, sizeof(struct m8820x_data));
+
+	// Hack: Use the addr2 field to select cpu and cmmu numbers.
+	// cmmu nr 0 = instruction, 1 = data.
+	d->cmmu_nr = devinit->addr2 & 1;
+	d->cpu_nr = devinit->addr2 >> 1;
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, M8820X_LENGTH, dev_m8820x_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_m8820x.cc gxemul-0.7.0+dfsg/src/devices/dev_m8820x.cc
--- gxemul-0.6.2/src/devices/dev_m8820x.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_m8820x.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,240 +0,0 @@
-/*
- *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: M88200/M88204 CMMU (Cache/Memory Management Unit)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/m8820x.h"
-#include "thirdparty/m8820x_pte.h"
-
-
-struct m8820x_data {
-	int		cmmu_nr;
-};
-
-
-/*
- *  m8820x_command():
- *
- *  Handle M8820x commands written to the System Command Register.
- */
-static void m8820x_command(struct cpu *cpu, struct m8820x_data *d)
-{
-	uint32_t *regs = cpu->cd.m88k.cmmu[d->cmmu_nr]->reg;
-	int cmd = regs[CMMU_SCR];
-	uint32_t sar = regs[CMMU_SAR];
-	size_t i;
-	uint32_t super, all;
-
-	switch (cmd) {
-
-	case CMMU_FLUSH_CACHE_CB_LINE:
-	case CMMU_FLUSH_CACHE_CB_PAGE:
-	case CMMU_FLUSH_CACHE_INV_LINE:
-	case CMMU_FLUSH_CACHE_INV_PAGE:
-	case CMMU_FLUSH_CACHE_INV_ALL:
-	case CMMU_FLUSH_CACHE_CBI_LINE:
-	case CMMU_FLUSH_CACHE_CBI_PAGE:
-	case CMMU_FLUSH_CACHE_CBI_SEGMENT:
-	case CMMU_FLUSH_CACHE_CBI_ALL:
-		/*  TODO  */
-		break;
-
-	case CMMU_FLUSH_USER_ALL:
-	case CMMU_FLUSH_USER_PAGE:
-	case CMMU_FLUSH_SUPER_ALL:
-	case CMMU_FLUSH_SUPER_PAGE:
-		/*  TODO: Segment invalidation.  */
-
-		all = super = 0;
-		if (cmd == CMMU_FLUSH_USER_ALL ||
-		    cmd == CMMU_FLUSH_SUPER_ALL)
-			all = 1;
-		if (cmd == CMMU_FLUSH_SUPER_ALL ||
-		    cmd == CMMU_FLUSH_SUPER_PAGE)
-			super = M8820X_PATC_SUPERVISOR_BIT;
-
-		/*  TODO: Don't invalidate EVERYTHING like this!  */
-		cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
-
-		for (i=0; i<N_M88200_PATC_ENTRIES; i++) {
-			uint32_t v = cpu->cd.m88k.cmmu[d->cmmu_nr]
-			    ->patc_v_and_control[i];
-			uint32_t p = cpu->cd.m88k.cmmu[d->cmmu_nr]
-			    ->patc_p_and_supervisorbit[i];
-
-			/*  Already invalid? Then skip this entry.  */
-			if (!(v & PG_V))
-				continue;
-
-			/*  Super/user mismatch? Then skip the entry.  */
-			if ((p & M8820X_PATC_SUPERVISOR_BIT) != super)
-				continue;
-
-			/*  If not all pages are to be invalidated, there
-			    must be a virtual address match:  */
-			if (!all && (sar & 0xfffff000) != (v & 0xfffff000))
-				continue;
-
-			/*  Finally, invalidate the entry:  */
-			cpu->cd.m88k.cmmu[d->cmmu_nr]->patc_v_and_control[i]
-			    = v & ~PG_V;
-		}
-
-		break;
-
-	default:
-		fatal("[ m8820x_command: FATAL ERROR! unimplemented "
-		    "command 0x%02x ]\n", cmd);
-		exit(1);
-	}
-}
-
-
-DEVICE_ACCESS(m8820x)
-{
-	uint64_t idata = 0, odata = 0;
-	struct m8820x_data *d = (struct m8820x_data *) extra;
-	uint32_t *regs = cpu->cd.m88k.cmmu[d->cmmu_nr]->reg;
-	uint32_t *batc = cpu->cd.m88k.cmmu[d->cmmu_nr]->batc;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (writeflag == MEM_READ)
-		odata = regs[relative_addr / sizeof(uint32_t)];
-
-	switch (relative_addr / sizeof(uint32_t)) {
-
-	case CMMU_IDR:
-		if (writeflag == MEM_WRITE) {
-			fatal("m8820x: write to CMMU_IDR: TODO\n");
-			exit(1);
-		}
-		break;
-
-	case CMMU_SCR:
-		if (writeflag == MEM_READ) {
-			fatal("m8820x: read from CMMU_SCR: TODO\n");
-			exit(1);
-		} else {
-			regs[relative_addr / sizeof(uint32_t)] = idata;
-			m8820x_command(cpu, d);
-		}
-		break;
-
-	case CMMU_SSR:
-		if (writeflag == MEM_WRITE) {
-			fatal("m8820x: write to CMMU_SSR: TODO\n");
-			exit(1);
-		}
-		break;
-
-	case CMMU_PFSR:
-	case CMMU_PFAR:
-	case CMMU_SAR:
-	case CMMU_SCTR:
-	case CMMU_SAPR:		/*  TODO: Invalidate something for  */
-	case CMMU_UAPR:		/*  SAPR and UAPR writes?  */
-		/*  TODO: Don't invalidate everything.  */
-		cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
-		if (writeflag == MEM_WRITE)
-			regs[relative_addr / sizeof(uint32_t)] = idata;
-		break;
-
-	case CMMU_BWP0:
-	case CMMU_BWP1:
-	case CMMU_BWP2:
-	case CMMU_BWP3:
-	case CMMU_BWP4:
-	case CMMU_BWP5:
-	case CMMU_BWP6:
-	case CMMU_BWP7:
-		if (writeflag == MEM_WRITE) {
-			uint32_t old;
-			int i = (relative_addr / sizeof(uint32_t)) - CMMU_BWP0;
-
-			regs[relative_addr / sizeof(uint32_t)] = idata;
-
-			/*  Also write to the specific batc registers:  */
-			old = batc[i];
-			batc[i] = idata;
-			if (old != idata) {
-				/*  TODO: Don't invalidate everything?  */
-				cpu->invalidate_translation_caches(
-				    cpu, 0, INVALIDATE_ALL);
-			}
-		}
-		break;
-
-	case CMMU_CSSP0:
-		/*  TODO: Actually care about cache details.  */
-		break;
-
-	default:fatal("[ m8820x: unimplemented %s offset 0x%x",
-		    writeflag == MEM_WRITE? "write to" : "read from",
-		    (int) relative_addr);
-		if (writeflag == MEM_WRITE)
-			fatal(": 0x%x", (int)idata);
-		fatal(" ]\n");
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(m8820x)
-{
-	struct m8820x_data *d;
-
-	CHECK_ALLOCATION(d = (struct m8820x_data *) malloc(sizeof(struct m8820x_data)));
-	memset(d, 0, sizeof(struct m8820x_data));
-
-	d->cmmu_nr = devinit->addr2;
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, M8820X_LENGTH, dev_m8820x_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_malta_lcd.c gxemul-0.7.0+dfsg/src/devices/dev_malta_lcd.c
--- gxemul-0.6.2/src/devices/dev_malta_lcd.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_malta_lcd.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,149 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Malta (evbmips) LCD display
+ *
+ *  TODO: Write output to somewhere else, not just as a debug message.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/maltareg.h"
+
+
+#define	DEV_MALTA_LCD_LENGTH		0x80
+#define	MALTA_LCD_TICK_SHIFT		16
+#define	LCD_LEN				8
+
+struct malta_lcd_data {
+	uint64_t	base_addr;
+
+	int		display_modified;
+	unsigned char	display[LCD_LEN];
+};
+
+
+DEVICE_TICK(malta_lcd)
+{ 
+	struct malta_lcd_data *d = (struct malta_lcd_data *) extra;
+	int i;
+
+	if (d->display_modified == 0)
+		return;
+	if (d->display_modified == 1) {
+		d->display_modified = 2;
+		return;
+	}
+
+	debug("[ malta_lcd: \"");
+	for (i=0; i<LCD_LEN; i++)
+		if (d->display[i] >= ' ')
+			debug("%c", d->display[i]);
+		else
+			debug("?");
+	debug("\" ]\n");
+
+	d->display_modified = 0;
+}
+
+
+DEVICE_ACCESS(malta_lcd)
+{
+	struct malta_lcd_data *d = (struct malta_lcd_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int pos;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	relative_addr += d->base_addr;
+
+	switch (relative_addr) {
+
+	case MALTA_ASCII_BASE + MALTA_ASCIIPOS0:
+	case MALTA_ASCII_BASE + MALTA_ASCIIPOS1:
+	case MALTA_ASCII_BASE + MALTA_ASCIIPOS2:
+	case MALTA_ASCII_BASE + MALTA_ASCIIPOS3:
+	case MALTA_ASCII_BASE + MALTA_ASCIIPOS4:
+	case MALTA_ASCII_BASE + MALTA_ASCIIPOS5:
+	case MALTA_ASCII_BASE + MALTA_ASCIIPOS6:
+	case MALTA_ASCII_BASE + MALTA_ASCIIPOS7:
+		pos = (relative_addr - MALTA_ASCII_BASE) / 8;
+		if (writeflag == MEM_WRITE) {
+			d->display[pos] = idata;
+			d->display_modified = 1;
+		} else {
+			odata = d->display[pos];
+		}
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ malta_lcd: unimplemented write to "
+			    "offset 0x%x: data=0x%02x ]\n", (int)
+			    relative_addr, (int)idata);
+		} else {
+			fatal("[ malta_lcd: unimplemented read from "
+			    "offset 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(malta_lcd)
+{
+	struct malta_lcd_data *d;
+
+	CHECK_ALLOCATION(d = (struct malta_lcd_data *) malloc(sizeof(struct malta_lcd_data)));
+	memset(d, 0, sizeof(struct malta_lcd_data));
+
+	d->base_addr = devinit->addr;
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_MALTA_LCD_LENGTH,
+	    dev_malta_lcd_access, (void *)d, DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(devinit->machine, dev_malta_lcd_tick,
+	    d, MALTA_LCD_TICK_SHIFT);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_malta_lcd.cc gxemul-0.7.0+dfsg/src/devices/dev_malta_lcd.cc
--- gxemul-0.6.2/src/devices/dev_malta_lcd.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_malta_lcd.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,149 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Malta (evbmips) LCD display
- *
- *  TODO: Write output to somewhere else, not just as a debug message.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/maltareg.h"
-
-
-#define	DEV_MALTA_LCD_LENGTH		0x80
-#define	MALTA_LCD_TICK_SHIFT		16
-#define	LCD_LEN				8
-
-struct malta_lcd_data {
-	uint64_t	base_addr;
-
-	int		display_modified;
-	unsigned char	display[LCD_LEN];
-};
-
-
-DEVICE_TICK(malta_lcd)
-{ 
-	struct malta_lcd_data *d = (struct malta_lcd_data *) extra;
-	int i;
-
-	if (d->display_modified == 0)
-		return;
-	if (d->display_modified == 1) {
-		d->display_modified = 2;
-		return;
-	}
-
-	debug("[ malta_lcd: \"");
-	for (i=0; i<LCD_LEN; i++)
-		if (d->display[i] >= ' ')
-			debug("%c", d->display[i]);
-		else
-			debug("?");
-	debug("\" ]\n");
-
-	d->display_modified = 0;
-}
-
-
-DEVICE_ACCESS(malta_lcd)
-{
-	struct malta_lcd_data *d = (struct malta_lcd_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int pos;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	relative_addr += d->base_addr;
-
-	switch (relative_addr) {
-
-	case MALTA_ASCII_BASE + MALTA_ASCIIPOS0:
-	case MALTA_ASCII_BASE + MALTA_ASCIIPOS1:
-	case MALTA_ASCII_BASE + MALTA_ASCIIPOS2:
-	case MALTA_ASCII_BASE + MALTA_ASCIIPOS3:
-	case MALTA_ASCII_BASE + MALTA_ASCIIPOS4:
-	case MALTA_ASCII_BASE + MALTA_ASCIIPOS5:
-	case MALTA_ASCII_BASE + MALTA_ASCIIPOS6:
-	case MALTA_ASCII_BASE + MALTA_ASCIIPOS7:
-		pos = (relative_addr - MALTA_ASCII_BASE) / 8;
-		if (writeflag == MEM_WRITE) {
-			d->display[pos] = idata;
-			d->display_modified = 1;
-		} else {
-			odata = d->display[pos];
-		}
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ malta_lcd: unimplemented write to "
-			    "offset 0x%x: data=0x%02x ]\n", (int)
-			    relative_addr, (int)idata);
-		} else {
-			fatal("[ malta_lcd: unimplemented read from "
-			    "offset 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(malta_lcd)
-{
-	struct malta_lcd_data *d;
-
-	CHECK_ALLOCATION(d = (struct malta_lcd_data *) malloc(sizeof(struct malta_lcd_data)));
-	memset(d, 0, sizeof(struct malta_lcd_data));
-
-	d->base_addr = devinit->addr;
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_MALTA_LCD_LENGTH,
-	    dev_malta_lcd_access, (void *)d, DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(devinit->machine, dev_malta_lcd_tick,
-	    d, MALTA_LCD_TICK_SHIFT);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_mb8696x.c gxemul-0.7.0+dfsg/src/devices/dev_mb8696x.c
--- gxemul-0.6.2/src/devices/dev_mb8696x.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_mb8696x.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,282 @@
+/*
+ *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Fujitsu MB8696x Ethernet interface (used in the Dreamcast)
+ *
+ *  Used as the LAN adapter (MB86967) in the Dreamcast machine mode.
+ *
+ *
+ *  Note: This is just a bogus module so far.
+ *
+ *  (TODO: "Reverse engineer" more of NetBSD's mb86960.c to implement this.)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "net.h"
+
+#include "thirdparty/mb86960reg.h"
+
+
+struct mb8696x_data {
+	int		addr_mult;
+
+	/*
+	 *  Registers:
+	 *
+	 *  reg contains 32 registers. However, registers 8..15 are bank-
+	 *  switched, based on a setting in FE_DLCR7. mar_8_15 are "multicast
+	 *  address registers", and bmpr_8_15 are "buffer memory port
+	 *  registers".
+	 */
+	uint8_t		reg[MB8696X_NREGS];
+	uint8_t		mar_8_15[8];
+	uint8_t		bmpr_8_15[8];
+
+	/*  EEPROM contents and internal state during a read operation:  */
+	uint8_t		eeprom[FE_EEPROM_SIZE];
+	int		eeprom_state;
+	uint8_t		eeprom_bit_count;
+	uint8_t		eeprom_command;
+	uint16_t	eeprom_data;
+};
+
+#define	EEPROM_STATE_NOTHING	0
+#define	EEPROM_STATE_READY	1	/*  Waiting for start bit  */
+#define	EEPROM_STATE_COMMAND	2	/*  Waiting for 8 command bits  */
+#define	EEPROM_STATE_READ	3
+
+
+DEVICE_ACCESS(mb8696x)
+{
+	struct mb8696x_data *d = (struct mb8696x_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	uint8_t *reg_ptr;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	relative_addr /= d->addr_mult;
+
+	/*
+	 *  Default result on reads:  (Note special treatment of banked regs.)
+	 */
+	reg_ptr = &d->reg[relative_addr];
+	if (relative_addr >= 8 && relative_addr <= 15 &&
+	    (d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_MAR)
+		reg_ptr = &d->mar_8_15[relative_addr - 8];
+	if (relative_addr >= 8 && relative_addr <= 15 &&
+	    (d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_BMPR)
+		reg_ptr = &d->bmpr_8_15[relative_addr - 8];
+
+	odata = *reg_ptr;
+
+
+	switch (relative_addr) {
+
+	case FE_DLCR0:	/*  TX interrupt status  */
+	case FE_DLCR1:	/*  RX interrupt status  */
+		/*  Write-1-to-clear:  */
+		if (writeflag == MEM_WRITE)
+			(*reg_ptr) &= ~idata;
+
+/*  TODO: reassert interrupts  */
+
+		break;
+
+	case FE_DLCR2:	/*  TX interrupt control  */
+	case FE_DLCR3:	/*  RX interrupt control  */
+		if (writeflag == MEM_WRITE)
+			(*reg_ptr) = idata;
+
+/*  TODO: reassert interrupts  */
+
+		break;
+
+	case FE_DLCR6:
+	case FE_DLCR8:	/*  Ethernet addr byte 0  */
+	case FE_DLCR9:	/*  Ethernet addr byte 1  */
+	case FE_DLCR10:	/*  Ethernet addr byte 2  */
+	case FE_DLCR11:	/*  Ethernet addr byte 3  */
+	case FE_DLCR12:	/*  Ethernet addr byte 4  */
+	case FE_DLCR13:	/*  Ethernet addr byte 5  */
+		if (writeflag == MEM_WRITE)
+			(*reg_ptr) = idata;
+		break;
+
+	case FE_DLCR7:
+		if (writeflag == MEM_WRITE) {
+			/*  Identification cannot be overwritten:  */
+			(*reg_ptr) &= FE_D7_IDENT;
+			(*reg_ptr) |= (idata & ~FE_D7_IDENT);
+		}
+		break;
+
+	case FE_BMPR16:
+		/*  EEPROM control  */
+		if (writeflag == MEM_WRITE) {
+			if (idata & ~(FE_B16_DOUT | FE_B16_DIN |
+			    FE_B16_SELECT | FE_B16_CLOCK)) {
+				fatal("mb8696x: UNIMPLEMENTED bits when "
+				    "writing to FE_BMPR16: 0x%02x\n",
+				    (int)idata);
+				exit(1);
+			}
+
+			/*  Dropped out of select state?  */
+			if (!(idata & FE_B16_SELECT))
+				d->eeprom_state = EEPROM_STATE_NOTHING;
+
+			/*  Switching to select state?  */
+			if (!((*reg_ptr) & FE_B16_SELECT) &&
+			    idata & FE_B16_SELECT)
+				d->eeprom_state = EEPROM_STATE_READY;
+
+			/*  Bit clock?  */
+			if (!((*reg_ptr) & FE_B16_CLOCK) &&
+			    idata & FE_B16_CLOCK) {
+				int bit = d->reg[FE_BMPR17] & FE_B17_DATA? 1:0;
+				switch (d->eeprom_state) {
+				case EEPROM_STATE_READY:
+					d->eeprom_state = EEPROM_STATE_COMMAND;
+					d->eeprom_bit_count = 0;
+					break;
+				case EEPROM_STATE_COMMAND:
+					d->eeprom_bit_count ++;
+					d->eeprom_command <<= 1;
+					d->eeprom_command |= bit;
+					if (d->eeprom_bit_count == 8) {
+						int addr = (d->eeprom_command
+						    & 0x7f) << 1;
+						/*  printf("COMMAND=%08x\n",
+						    d->eeprom_command);  */
+						if (!(d->eeprom_command&0x80)) {
+							fatal("WRITES to the "
+							    "EEPROM are not yet"
+							    " implemented.\n");
+							exit(1);
+						}
+						/*  This is a read command.  */
+						d->eeprom_bit_count = 0;
+						d->eeprom_state =
+						    EEPROM_STATE_READ;
+						d->eeprom_data = d->eeprom[addr]
+						    * 256 + d->eeprom[addr+1];
+					}
+					break;
+				case EEPROM_STATE_READ:
+					d->reg[FE_BMPR17] = 0;
+					if (d->eeprom_data & 0x8000)
+						d->reg[FE_BMPR17] = FE_B17_DATA;
+					d->eeprom_data <<= 1;
+					d->eeprom_bit_count ++;
+					if (d->eeprom_bit_count > 16)
+						fatal("[ WARNING: more than 16"
+						    " bits of EEPROM data "
+						    "read? ]\n");
+					break;
+				}
+			}
+
+			(*reg_ptr) = idata;
+		}
+		break;
+
+	case FE_BMPR17:
+		/*  EEPROM data  */
+		if (writeflag == MEM_WRITE) {
+			if (idata & ~FE_B17_DATA) {
+				fatal("mb8696x: UNIMPLEMENTED bits when "
+				    "writing to FE_BMPR17: 0x%02x\n",
+				    (int)idata);
+				exit(1);
+			}
+			(*reg_ptr) = idata;
+		}
+		break;
+
+	default:
+		{
+			const char *bank = "";
+			if ((d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_MAR)
+				bank = " (bank MAR)";
+			if ((d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_BMPR)
+				bank = " (bank BMPR)";
+			if (writeflag == MEM_READ) {
+				fatal("[ mb8696x: read from UNIMPLEMENTED reg "
+				    "%i%s ]\n", (int)relative_addr, bank);
+			} else {
+				fatal("[ mb8696x: write to UNIMPLEMENTED reg "
+				    "%i%s: 0x%02x ]\n", (int)relative_addr,
+				    bank, (int)idata);
+			}
+
+			// exit(1);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(mb8696x)
+{
+	struct mb8696x_data *d;
+
+	CHECK_ALLOCATION(d = (struct mb8696x_data *) malloc(sizeof(struct mb8696x_data)));
+	memset(d, 0, sizeof(struct mb8696x_data));
+
+	d->addr_mult = devinit->addr_mult;
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, MB8696X_NREGS * d->addr_mult, dev_mb8696x_access, d,
+	    DM_DEFAULT, NULL);
+
+	/*  NetBSD/dreamcast expects ident = 86967.  */
+	d->reg[FE_DLCR7] = FE_D7_IDENT_86967;
+
+	/*
+	 *  Generate the MAC address, both in the first 6 bytes of the
+	 *  EEPROM, and in DLCR8..13:
+	 */
+	net_generate_unique_mac(devinit->machine, &d->eeprom[0]);
+	memcpy(&d->reg[FE_DLCR8], &d->eeprom[0], 6);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_mb8696x.cc gxemul-0.7.0+dfsg/src/devices/dev_mb8696x.cc
--- gxemul-0.6.2/src/devices/dev_mb8696x.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_mb8696x.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,292 +0,0 @@
-/*
- *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Fujitsu MB8696x Ethernet interface (used in the Dreamcast)
- *
- *  Used as the LAN adapter (MB86967) in the Dreamcast machine mode.
- *
- *
- *  Note: This is just a bogus module so far.
- *
- *  (TODO: "Reverse engineer" more of NetBSD's mb86960.c to implement this.)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/time.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "net.h"
-
-#include "thirdparty/mb86960reg.h"
-
-
-#ifdef UNSTABLE_DEVEL
-#define	MB8696X_DEBUG
-#endif
-
-#ifdef MB8696X_DEBUG
-#define debug fatal
-#endif
-
-struct mb8696x_data {
-	int		addr_mult;
-
-	/*
-	 *  Registers:
-	 *
-	 *  reg contains 32 registers. However, registers 8..15 are bank-
-	 *  switched, based on a setting in FE_DLCR7. mar_8_15 are "multicast
-	 *  address registers", and bmpr_8_15 are "buffer memory port
-	 *  registers".
-	 */
-	uint8_t		reg[MB8696X_NREGS];
-	uint8_t		mar_8_15[8];
-	uint8_t		bmpr_8_15[8];
-
-	/*  EEPROM contents and internal state during a read operation:  */
-	uint8_t		eeprom[FE_EEPROM_SIZE];
-	int		eeprom_state;
-	uint8_t		eeprom_bit_count;
-	uint8_t		eeprom_command;
-	uint16_t	eeprom_data;
-};
-
-#define	EEPROM_STATE_NOTHING	0
-#define	EEPROM_STATE_READY	1	/*  Waiting for start bit  */
-#define	EEPROM_STATE_COMMAND	2	/*  Waiting for 8 command bits  */
-#define	EEPROM_STATE_READ	3
-
-
-DEVICE_ACCESS(mb8696x)
-{
-	struct mb8696x_data *d = (struct mb8696x_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	uint8_t *reg_ptr;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	relative_addr /= d->addr_mult;
-
-	/*
-	 *  Default result on reads:  (Note special treatment of banked regs.)
-	 */
-	reg_ptr = &d->reg[relative_addr];
-	if (relative_addr >= 8 && relative_addr <= 15 &&
-	    (d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_MAR)
-		reg_ptr = &d->mar_8_15[relative_addr - 8];
-	if (relative_addr >= 8 && relative_addr <= 15 &&
-	    (d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_BMPR)
-		reg_ptr = &d->bmpr_8_15[relative_addr - 8];
-
-	odata = *reg_ptr;
-
-
-	switch (relative_addr) {
-
-	case FE_DLCR0:	/*  TX interrupt status  */
-	case FE_DLCR1:	/*  RX interrupt status  */
-		/*  Write-1-to-clear:  */
-		if (writeflag == MEM_WRITE)
-			(*reg_ptr) &= ~idata;
-
-/*  TODO: reassert interrupts  */
-
-		break;
-
-	case FE_DLCR2:	/*  TX interrupt control  */
-	case FE_DLCR3:	/*  RX interrupt control  */
-		if (writeflag == MEM_WRITE)
-			(*reg_ptr) = idata;
-
-/*  TODO: reassert interrupts  */
-
-		break;
-
-	case FE_DLCR6:
-	case FE_DLCR8:	/*  Ethernet addr byte 0  */
-	case FE_DLCR9:	/*  Ethernet addr byte 1  */
-	case FE_DLCR10:	/*  Ethernet addr byte 2  */
-	case FE_DLCR11:	/*  Ethernet addr byte 3  */
-	case FE_DLCR12:	/*  Ethernet addr byte 4  */
-	case FE_DLCR13:	/*  Ethernet addr byte 5  */
-		if (writeflag == MEM_WRITE)
-			(*reg_ptr) = idata;
-		break;
-
-	case FE_DLCR7:
-		if (writeflag == MEM_WRITE) {
-			/*  Identification cannot be overwritten:  */
-			(*reg_ptr) &= FE_D7_IDENT;
-			(*reg_ptr) |= (idata & ~FE_D7_IDENT);
-		}
-		break;
-
-	case FE_BMPR16:
-		/*  EEPROM control  */
-		if (writeflag == MEM_WRITE) {
-			if (idata & ~(FE_B16_DOUT | FE_B16_DIN |
-			    FE_B16_SELECT | FE_B16_CLOCK)) {
-				fatal("mb8696x: UNIMPLEMENTED bits when "
-				    "writing to FE_BMPR16: 0x%02x\n",
-				    (int)idata);
-				exit(1);
-			}
-
-			/*  Dropped out of select state?  */
-			if (!(idata & FE_B16_SELECT))
-				d->eeprom_state = EEPROM_STATE_NOTHING;
-
-			/*  Switching to select state?  */
-			if (!((*reg_ptr) & FE_B16_SELECT) &&
-			    idata & FE_B16_SELECT)
-				d->eeprom_state = EEPROM_STATE_READY;
-
-			/*  Bit clock?  */
-			if (!((*reg_ptr) & FE_B16_CLOCK) &&
-			    idata & FE_B16_CLOCK) {
-				int bit = d->reg[FE_BMPR17] & FE_B17_DATA? 1:0;
-				switch (d->eeprom_state) {
-				case EEPROM_STATE_READY:
-					d->eeprom_state = EEPROM_STATE_COMMAND;
-					d->eeprom_bit_count = 0;
-					break;
-				case EEPROM_STATE_COMMAND:
-					d->eeprom_bit_count ++;
-					d->eeprom_command <<= 1;
-					d->eeprom_command |= bit;
-					if (d->eeprom_bit_count == 8) {
-						int addr = (d->eeprom_command
-						    & 0x7f) << 1;
-						/*  printf("COMMAND=%08x\n",
-						    d->eeprom_command);  */
-						if (!(d->eeprom_command&0x80)) {
-							fatal("WRITES to the "
-							    "EEPROM are not yet"
-							    " implemented.\n");
-							exit(1);
-						}
-						/*  This is a read command.  */
-						d->eeprom_bit_count = 0;
-						d->eeprom_state =
-						    EEPROM_STATE_READ;
-						d->eeprom_data = d->eeprom[addr]
-						    * 256 + d->eeprom[addr+1];
-					}
-					break;
-				case EEPROM_STATE_READ:
-					d->reg[FE_BMPR17] = 0;
-					if (d->eeprom_data & 0x8000)
-						d->reg[FE_BMPR17] = FE_B17_DATA;
-					d->eeprom_data <<= 1;
-					d->eeprom_bit_count ++;
-					if (d->eeprom_bit_count > 16)
-						fatal("[ WARNING: more than 16"
-						    " bits of EEPROM data "
-						    "read? ]\n");
-					break;
-				}
-			}
-
-			(*reg_ptr) = idata;
-		}
-		break;
-
-	case FE_BMPR17:
-		/*  EEPROM data  */
-		if (writeflag == MEM_WRITE) {
-			if (idata & ~FE_B17_DATA) {
-				fatal("mb8696x: UNIMPLEMENTED bits when "
-				    "writing to FE_BMPR17: 0x%02x\n",
-				    (int)idata);
-				exit(1);
-			}
-			(*reg_ptr) = idata;
-		}
-		break;
-
-	default:
-		{
-			const char *bank = "";
-			if ((d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_MAR)
-				bank = " (bank MAR)";
-			if ((d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_BMPR)
-				bank = " (bank BMPR)";
-			if (writeflag == MEM_READ) {
-				fatal("[ mb8696x: read from UNIMPLEMENTED reg "
-				    "%i%s ]\n", (int)relative_addr, bank);
-			} else {
-				fatal("[ mb8696x: write to UNIMPLEMENTED reg "
-				    "%i%s: 0x%02x ]\n", (int)relative_addr,
-				    bank, (int)idata);
-			}
-
-#ifdef MB8696X_DEBUG
-			exit(1);
-#endif
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(mb8696x)
-{
-	struct mb8696x_data *d;
-
-	CHECK_ALLOCATION(d = (struct mb8696x_data *) malloc(sizeof(struct mb8696x_data)));
-	memset(d, 0, sizeof(struct mb8696x_data));
-
-	d->addr_mult = devinit->addr_mult;
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, MB8696X_NREGS * d->addr_mult, dev_mb8696x_access, d,
-	    DM_DEFAULT, NULL);
-
-	/*  NetBSD/dreamcast expects ident = 86967.  */
-	d->reg[FE_DLCR7] = FE_D7_IDENT_86967;
-
-	/*
-	 *  Generate the MAC address, both in the first 6 bytes of the
-	 *  EEPROM, and in DLCR8..13:
-	 */
-	net_generate_unique_mac(devinit->machine, &d->eeprom[0]);
-	memcpy(&d->reg[FE_DLCR8], &d->eeprom[0], 6);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_mb89352.c gxemul-0.7.0+dfsg/src/devices/dev_mb89352.c
--- gxemul-0.6.2/src/devices/dev_mb89352.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_mb89352.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,646 @@
+/*
+ *  Copyright (C) 2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Fujitsu MB89352 SCSI Protocol Controller (SPC)
+ *
+ *  Based on looking at openbsd/sys/arch/luna88k/stand/boot (the OpenBSD boot
+ *  loader), and openbsd/sys/arch/luna88k/dev/mb89352* (the kernel), and
+ *  matching their expectations.
+ *
+ *  TODO: Probably lots of details. Most likely, running anything other than
+ *        OpenBSD/luna88k as a guest OS will trigger unimplemented code
+ *        paths.
+ *
+ *  TODO: OpenBSD complains about
+ *        probe(spc0:0:0): Check Condition (error 0) on opcode 0x0
+ *        during bootup.
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/mb89352reg.h"
+
+#define	TICK_STEPS_SHIFT	14
+
+#define MB89352_NREGS		0x10
+
+const int MB89352_REGISTERS_LENGTH = MB89352_NREGS * 4;
+
+const bool mb89352_abort_on_unimplemented_stuff = true;
+
+static char *regname[16] = {
+	"BDID", "SCTL", "SCMD", "TMOD", "INTS", "PSNS", "SSTS", "SERR",
+	"PCTL", "MBC",  "DREG", "TEMP", "TCH",  "TCM",  "TCL",  "EXBF"
+};
+
+
+#define PH_BUS_FREE		4
+
+
+struct mb89352_data {
+	int			subsys;
+
+	struct interrupt	irq;
+	bool			irq_asserted;
+
+	uint8_t			reg[MB89352_NREGS];
+	
+	int			target;		// target SCSI ID, e.g. 6
+	int			phase;
+
+	struct scsi_transfer	*xferp;
+	size_t			transfer_count;
+	size_t			transfer_bufpos;
+};
+
+
+void reg_debug(struct cpu* cpu, struct mb89352_data *d, int writeflag, int regnr, int data)
+{
+	if (!ENOUGH_VERBOSITY(d->subsys, VERBOSITY_DEBUG))
+		return;
+
+	if (writeflag == MEM_WRITE)
+		debugmsg_cpu(cpu, d->subsys, "",
+		    VERBOSITY_DEBUG, "WRITE to %s: 0x%02x", regname[regnr], data);
+	else
+		debugmsg_cpu(cpu, d->subsys, "",
+		    VERBOSITY_DEBUG, "read from %s", regname[regnr]);
+}			    
+
+
+static void reassert_interrupts(struct mb89352_data *d)
+{
+	bool assert = d->reg[INTS] != 0;
+
+	// TODO: BUS FREE interrupt enable: PCTL_BFINT_ENAB
+
+	if (!(d->reg[SCTL] & SCTL_INTR_ENAB))
+		assert = false;
+	if (d->reg[SCTL] & SCTL_DISABLE)
+		assert = false;
+
+	if (assert && !d->irq_asserted)
+		INTERRUPT_ASSERT(d->irq);
+	else if (!assert && d->irq_asserted)
+		INTERRUPT_DEASSERT(d->irq);
+
+	d->irq_asserted = assert;
+}
+
+
+static void reset_controller(struct mb89352_data *d)
+{
+	memset(d->reg, 0, sizeof(d->reg));
+
+	d->reg[BDID] = 7;
+	d->reg[SCTL] = SCTL_DISABLE;
+}
+
+
+DEVICE_TICK(mb89352)
+{
+	struct mb89352_data *d = (struct mb89352_data *) extra;
+	reassert_interrupts(d);
+}
+
+
+int mb89352_dreg_read(struct cpu* cpu, struct mb89352_data *d, int writeflag)
+{
+	int odata;
+
+	if (d->xferp == NULL) {
+		debugmsg_cpu(cpu, d->subsys, "", VERBOSITY_ERROR,
+	    	    "DREG: no ongoing transfer to read from?");
+	    	cpu->running = 0;
+	    	return 0;
+	}
+	
+	uint8_t *p = d->xferp->data_in;
+	size_t len = d->xferp->data_in_len;
+	
+	switch (d->phase) {
+	case PH_DATAIN:
+		p = d->xferp->data_in;
+		len = d->xferp->data_in_len;
+		break;
+	case PH_STAT:
+		p = d->xferp->status;
+		len = d->xferp->status_len;
+		break;
+	case PH_MSGIN:
+		p = d->xferp->msg_in;
+		len = d->xferp->msg_in_len;
+		break;
+	default:
+		debugmsg_cpu(cpu, d->subsys, "", VERBOSITY_ERROR,
+	    	    "DREG: read in unimplemented phase %i", d->phase);
+	    	cpu->running = 0;
+	    	return 0;
+	}
+
+	if (d->transfer_bufpos >= len) {
+		debugmsg_cpu(cpu, d->subsys, "", VERBOSITY_ERROR,
+	    	    "DREG: read longer than buffer?");
+	    	cpu->running = 0;
+	    	return 0;
+	}
+
+	odata = p[d->transfer_bufpos ++];
+
+	debugmsg_cpu(cpu, d->subsys, "", VERBOSITY_DEBUG,
+    	    "DREG read: 0x%02x", (int)odata);
+
+	if (d->transfer_bufpos < len)
+		return odata;
+
+	debugmsg_cpu(cpu, d->subsys, "", VERBOSITY_DEBUG,
+    	    "DREG read entire result completed.");
+
+	d->reg[SSTS] &= ~SSTS_XFR;
+
+	if (d->phase == PH_DATAIN)
+		d->phase = PH_STAT;
+	else if (d->phase == PH_STAT)
+		d->phase = PH_MSGIN;
+	else if (d->phase == PH_MSGIN)
+		d->phase = PH_BUS_FREE;
+
+	d->reg[PSNS] |= PSNS_REQ;
+
+	if (d->phase == PH_BUS_FREE)
+		d->reg[INTS] |= INTS_DISCON;
+	else
+		d->reg[INTS] |= INTS_CMD_DONE;
+
+	return odata;
+}
+
+
+void mb89352_dreg_write(struct cpu* cpu, struct mb89352_data *d, int writeflag, int idata)
+{
+	if (d->xferp == NULL) {
+		debugmsg_cpu(cpu, d->subsys, "",
+		    mb89352_abort_on_unimplemented_stuff ? VERBOSITY_ERROR : VERBOSITY_WARNING,
+	    	    "DREG: no ongoing transfer to write to?");
+	    	return;
+	}
+	
+	uint8_t *p = d->xferp->data_in;
+	size_t len = d->xferp->data_in_len;
+	
+	switch (d->phase) {
+	case PH_DATAOUT:
+		p = d->xferp->data_out;
+		len = d->xferp->data_out_len;
+		break;
+	case PH_CMD:
+		p = d->xferp->cmd;
+		len = d->xferp->cmd_len;
+		break;
+	default:
+		debugmsg_cpu(cpu, d->subsys, "", VERBOSITY_ERROR,
+	    	    "DREG: write in unimplemented phase %i", d->phase);
+	    	cpu->running = 0;
+	    	return;
+	}
+
+	if (d->transfer_bufpos >= len) {
+		debugmsg_cpu(cpu, d->subsys, "", VERBOSITY_ERROR,
+	    	    "DREG: write longer than buffer?");
+	    	cpu->running = 0;
+	    	return;
+	}
+
+	p[d->transfer_bufpos ++] = idata;
+
+	if (d->transfer_bufpos < len)
+		return;
+
+	debugmsg_cpu(cpu, d->subsys, "",
+	    VERBOSITY_DEBUG,
+    	    "%i bytes written", d->transfer_bufpos);
+
+	int res;
+
+	switch (d->phase) {
+
+	case PH_DATAOUT:
+		res = diskimage_scsicommand(cpu,
+	    	    d->target, DISKIMAGE_SCSI, d->xferp);
+
+		// TODO: How about failure results?
+		d->phase = PH_STAT;
+		break;
+
+	case PH_CMD:
+		res = diskimage_scsicommand(cpu,
+	    	    d->target, DISKIMAGE_SCSI, d->xferp);
+
+		if (res == 2)
+			d->phase = PH_DATAOUT;
+		else if (d->xferp->data_in != NULL)
+			d->phase = PH_DATAIN;
+		else
+			d->phase = PH_STAT;
+		break;
+
+	default:
+		debugmsg_cpu(cpu, d->subsys, "", VERBOSITY_ERROR,
+	    	    "DREG write: UNIMPLEMENTED PHASE %i", d->phase);
+	    	cpu->running = 0;
+	}
+	
+	d->reg[PSNS] |= PSNS_REQ;
+	d->reg[SSTS] &= ~SSTS_XFR;
+	d->reg[INTS] |= INTS_CMD_DONE;
+}
+
+
+DEVICE_ACCESS(mb89352)
+{
+	struct mb89352_data *d = (struct mb89352_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (len != 1) {
+		debugmsg_cpu(cpu, d->subsys, "",
+		    mb89352_abort_on_unimplemented_stuff ? VERBOSITY_ERROR : VERBOSITY_WARNING,
+	    	    "unimplemented LEN: %i-bit access, address 0x%x: 0x%x",
+	    	    len * 8,
+	    	    (int) relative_addr);
+
+		if (mb89352_abort_on_unimplemented_stuff) {
+			cpu->running = 0;
+			return 0;
+		}
+	}
+
+	int regnr = (relative_addr >> 2) & (MB89352_NREGS - 1);
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+	else
+		odata = d->reg[regnr];
+
+	reg_debug(cpu, d, writeflag, regnr, idata);
+
+	switch (regnr) {
+
+	case BDID:
+		if (writeflag == MEM_WRITE) {
+			d->reg[BDID] = idata;
+			if (idata != 7)
+				debugmsg_cpu(cpu, d->subsys, "",
+				    VERBOSITY_INFO, "unimplemented BDID value: 0x%x",
+			    	    (int) idata);
+		} else {
+			odata = (1 << d->reg[BDID]);
+		}
+		break;
+
+	case SCTL:
+		if (writeflag == MEM_WRITE) {
+			d->reg[SCTL] = idata;
+
+			if (idata & SCTL_DIAG)
+				debugmsg_cpu(cpu, d->subsys, "",
+				    VERBOSITY_ERROR,
+			    	    "Diagnostics mode NOT IMPLEMENTED");
+
+			if (idata & SCTL_CTRLRST) {
+				debugmsg(d->subsys, "", VERBOSITY_INFO, "resetting controller");
+				reset_controller(d);
+			}
+		}
+		break;
+
+	case SCMD:
+		if (writeflag == MEM_WRITE) {
+			d->reg[SCMD] = idata;
+			
+			// RST = Reset ?
+			if (idata & SCMD_RST)
+				idata = SCMD_BUS_REL;
+			
+			switch (idata) {
+
+			case SCMD_BUS_REL:	// 0x00
+				d->reg[SSTS] &= ~(SSTS_TARGET | SSTS_INITIATOR | SSTS_XFR);
+				d->phase = PH_BUS_FREE;
+				// TODO: BUS FREE interrupt enable: PCTL_BFINT_ENAB?
+				break;
+
+			case SCMD_SELECT:
+				// Select target in the temp register.
+				{
+					int target = 0;
+					while (target < 8) {
+						int m = 1 << target;
+						if (d->reg[TEMP] & ~(1 << 7) & m)
+							break;
+						target ++;
+					}
+
+					if (target < 8)
+						debugmsg_cpu(cpu, d->subsys, "",
+						    VERBOSITY_DEBUG,
+					    	    "selecting target %i", target);
+					else
+						debugmsg_cpu(cpu, d->subsys, "",
+						    VERBOSITY_WARNING,
+					    	    "SCMD_SELECT with no target?");
+
+					d->target = target;
+					d->reg[INTS] |= INTS_CMD_DONE;
+					d->reg[PSNS] &= ~7;
+					d->phase = PH_CMD;
+					d->reg[PSNS] |= PSNS_REQ;
+
+					if (d->xferp != NULL)
+						scsi_transfer_free(d->xferp);
+
+					d->xferp = scsi_transfer_alloc();
+					d->transfer_bufpos = 0;
+
+					d->reg[SSTS] &= ~SSTS_TARGET;
+					d->reg[SSTS] |= SSTS_BUSY;
+				}
+				break;
+
+			case SCMD_XFR | SCMD_PROG_XFR:
+			case SCMD_XFR | SCMD_PROG_XFR | SCMD_ICPT_XFR:
+				{
+					d->reg[SSTS] |= SSTS_XFR;
+					d->phase = d->reg[PCTL] & 7;
+
+					d->transfer_bufpos = 0;
+
+					debugmsg_cpu(cpu, d->subsys, "",
+					    VERBOSITY_DEBUG,
+				    	    "Transfer command: phase %i, len %i",
+				    	    d->phase, d->transfer_count);
+
+					switch (d->phase) {
+					case PH_DATAOUT:
+						scsi_transfer_allocbuf(&d->xferp->data_out_len,
+						    &d->xferp->data_out, d->transfer_count, 0);
+						d->xferp->data_out_offset = d->transfer_count;
+						break;
+					case PH_DATAIN:
+						break;
+					case PH_CMD:
+						scsi_transfer_allocbuf(&d->xferp->cmd_len,
+						    &d->xferp->cmd, d->transfer_count, 0);
+						break;
+					case PH_STAT:
+						break;
+					case PH_MSGIN:
+						break;
+					default:
+						debugmsg_cpu(cpu, d->subsys, "",
+						    VERBOSITY_ERROR,
+					    	    "Transfer command: unimplemented phase %i",
+					    	    d->phase);
+				    		exit(1);
+					}
+
+					if (!(d->phase & 1))
+						d->reg[INTS] |= INTS_CMD_DONE;
+				}
+				break;
+
+			case SCMD_RST_ACK:
+				d->reg[SSTS] &= ~(SSTS_INITIATOR | SSTS_TARGET);
+				d->reg[PSNS] &= ~PSNS_REQ;
+				break;
+
+			default:
+				debugmsg_cpu(cpu, d->subsys, "",
+				    mb89352_abort_on_unimplemented_stuff ? VERBOSITY_ERROR : VERBOSITY_WARNING,
+			    	    "unimplemented SCMD: 0x%x", (int) idata);
+
+				if (mb89352_abort_on_unimplemented_stuff) {
+					cpu->running = 0;
+					return 0;
+				}
+			}
+		}
+		break;
+
+	case TMOD:
+		if (writeflag == MEM_WRITE) {
+			d->reg[regnr] = idata;
+			if (idata != 0)
+				debugmsg_cpu(cpu, d->subsys, "",
+				    VERBOSITY_WARNING,
+				    "unimplemented write to TMOD: 0x%02x",
+			    	    (int) idata);
+		}
+		break;	
+
+	case INTS:
+		if (writeflag == MEM_WRITE) {
+			int old = d->reg[INTS];
+			d->reg[INTS] &= ~idata;
+			if (old != d->reg[INTS])
+				debugmsg_cpu(cpu, d->subsys, "",
+				    VERBOSITY_INFO, "INTS: 0x%02x -> 0x%02x",
+			    	    old, d->reg[INTS]);
+		}
+		break;	
+
+	case PSNS:
+		if (writeflag == MEM_WRITE) {
+			d->reg[regnr] = idata;
+			debugmsg_cpu(cpu, d->subsys, "",
+			    VERBOSITY_WARNING,
+		    	    "unimplemented write to PSNS/SDGC: 0x%x",
+			    (int) idata);
+		}
+
+		odata &= ~7;
+		odata |= d->phase;
+		break;
+
+	case SSTS:
+		if (writeflag == MEM_WRITE) {
+			d->reg[regnr] = idata;
+			debugmsg_cpu(cpu, d->subsys, "",
+			    VERBOSITY_WARNING,
+		    	    "unimplemented write to SSTS: 0x%x",
+			    (int) idata);
+		}
+
+		if (d->transfer_count == 0)
+			odata |= SSTS_TCZERO;
+		else
+			odata &= ~SSTS_TCZERO;
+
+		odata &= ~(SSTS_DREG_FULL | SSTS_DREG_EMPTY | SSTS_BUSY);
+
+		// Inbound phase, but no more data? Then the dreg is empty.
+		if (d->phase & 1) {
+			if (d->transfer_count == 0)
+				odata |= SSTS_DREG_EMPTY;
+		}
+
+		// Outbound phase, then the dreg is always empty.
+		if (!(d->phase & 1)) {
+			odata |= SSTS_DREG_EMPTY;
+		}
+
+		if (d->phase & 1 && d->transfer_count > 0)
+			odata |= SSTS_BUSY;
+		break;
+
+	case SERR:
+		if (writeflag == MEM_WRITE) {
+			d->reg[regnr] = idata;
+			debugmsg_cpu(cpu, d->subsys, "",
+			    VERBOSITY_WARNING,
+		    	    "unimplemented write to SERR: 0x%x",
+			    (int) idata);
+		}
+		break;
+
+	case PCTL:
+		if (writeflag == MEM_WRITE) {
+			d->reg[regnr] = idata;
+			if (idata & 0x78)
+				debugmsg_cpu(cpu, d->subsys, "",
+				    VERBOSITY_WARNING,
+			    	    "write to read-only bits of PCTL ignored: 0x%x",
+				    (int) idata);
+			d->reg[regnr] &= 0x87;
+		}
+		break;
+
+	case MBC:
+		if (writeflag == MEM_WRITE) {
+			debugmsg_cpu(cpu, d->subsys, "",
+			    VERBOSITY_WARNING,
+		    	    "write to read-only MBC ignored: 0x%x",
+			    (int) idata);
+		}
+		break;
+
+	case DREG:
+		if (d->transfer_count == 0) {
+			debugmsg_cpu(cpu, d->subsys, "",
+			    VERBOSITY_WARNING,
+		    	    "DREG %s, but transfer count = 0!",
+		    	    writeflag == MEM_WRITE ? "WRITE" : "READ");
+		} else {
+			d->transfer_count --;
+
+			if (writeflag == MEM_WRITE)
+				mb89352_dreg_write(cpu, d, writeflag, idata);
+			else
+				odata = mb89352_dreg_read(cpu, d, writeflag);
+		}
+		break;
+
+	case TEMP:
+		if (writeflag == MEM_WRITE)
+			d->reg[regnr] = idata;
+		break;
+
+	case TCH:
+	case TCM:
+	case TCL:
+		if (writeflag == MEM_WRITE) {
+			d->reg[regnr] = idata;
+
+			// Update d->transfer_count to be in sync with the registers.
+			d->transfer_count = (d->reg[TCH] << 16) + (d->reg[TCM] << 8) + d->reg[TCL];
+		} else {
+			d->reg[TCH] = d->transfer_count >> 16;
+			d->reg[TCM] = d->transfer_count >> 8;
+			d->reg[TCL] = d->transfer_count;
+			odata = d->reg[regnr];
+		}
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			debugmsg_cpu(cpu, d->subsys, "",
+			    mb89352_abort_on_unimplemented_stuff ? VERBOSITY_ERROR : VERBOSITY_WARNING,
+		    	    "unimplemented %i-bit WRITE to address 0x%x: 0x%x",
+		    	    len * 8,
+			    (int) relative_addr,
+			    (int) idata);
+		else
+			debugmsg_cpu(cpu, d->subsys, "",
+			    mb89352_abort_on_unimplemented_stuff ? VERBOSITY_ERROR : VERBOSITY_WARNING,
+		    	    "unimplemented %i-bit READ from address 0x%x",
+		    	    len * 8,
+			    (int) relative_addr);
+
+		if (mb89352_abort_on_unimplemented_stuff) {
+			cpu->running = 0;
+			return 0;
+		}
+	}
+
+	reassert_interrupts(d);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(mb89352)
+{
+	struct mb89352_data *d;
+
+	CHECK_ALLOCATION(d = (struct mb89352_data *) malloc(sizeof(struct mb89352_data)));
+	memset(d, 0, sizeof(struct mb89352_data));
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, MB89352_REGISTERS_LENGTH, dev_mb89352_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	d->subsys = debugmsg_register_subsystem("mb89352");
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	machine_add_tickfunction(devinit->machine, dev_mb89352_tick, d, TICK_STEPS_SHIFT);
+
+	reset_controller(d);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_mc146818.c gxemul-0.7.0+dfsg/src/devices/dev_mc146818.c
--- gxemul-0.6.2/src/devices/dev_mc146818.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_mc146818.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,690 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: MC146818 real-time clock
+ *
+ *  (DS1687 as used in some other machines is also similar to the MC146818.)
+ *
+ *  This device contains Date/time, the machine's ethernet address (on
+ *  DECstation 3100), and can cause periodic (hardware) interrupts.
+ *
+ *  NOTE: Many register offsets are multiplied by 4 in this code; this is
+ *  because I originally wrote it for DECstation 3100 emulation, where the
+ *  registered are spaced that way.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "timer.h"
+
+#include "thirdparty/mc146818reg.h"
+
+
+#define	to_bcd(x)	( ((x)/10) * 16 + ((x)%10) )
+#define	from_bcd(x)	( ((x)>>4) * 10 + ((x)&15) )
+
+/*  #define MC146818_DEBUG  */
+
+#define	MC146818_TICK_SHIFT	14
+
+
+/*  256 on DECstation, SGI uses reg at 72*4 as the Century  */
+#define	N_REGISTERS	1024
+struct mc_data {
+	int		access_style;
+	int		last_addr;
+
+	int		register_choice;
+	int		reg[N_REGISTERS];
+	int		addrdiv;
+
+	int		use_bcd;
+
+	int		timebase_hz;
+	int		interrupt_hz;
+	int		old_interrupt_hz;
+	struct interrupt irq;
+	struct timer	*timer;
+	volatile int	pending_timer_interrupts;
+
+	int		previous_second;
+	int		n_seconds_elapsed;
+	int		uip_threshold;
+
+	int		ugly_netbsd_prep_hack_done;
+	int		ugly_netbsd_prep_hack_sec;
+};
+
+
+/*
+ *  Ugly hack to fool NetBSD/prep to accept the clock.  (See mcclock_isa_match
+ *  in NetBSD's arch/prep/isa/mcclock_isa.c for details.)
+ */
+#define	NETBSD_HACK_INIT		0
+#define	NETBSD_HACK_FIRST_1		1
+#define	NETBSD_HACK_FIRST_2		2
+#define	NETBSD_HACK_SECOND_1		3
+#define	NETBSD_HACK_SECOND_2		4
+#define	NETBSD_HACK_DONE		5
+
+
+/*
+ *  timer_tick():
+ *
+ *  Called d->interrupt_hz times per (real-world) second.
+ */
+static void timer_tick(struct timer *timer, void *extra)
+{
+	struct mc_data *d = (struct mc_data *) extra;
+	d->pending_timer_interrupts ++;
+}
+
+
+DEVICE_TICK(mc146818)
+{
+	struct mc_data *d = (struct mc_data *) extra;
+	int pti = d->pending_timer_interrupts;
+
+	if ((d->reg[MC_REGB * 4] & MC_REGB_PIE) && pti > 0) {
+#if 0
+		/*  For debugging, to see how much the interrupts are
+		    lagging behind the real clock:  */
+		{
+			static int x = 0;
+			if (++x == 1) {
+				x = 0;
+				printf("%i ", pti);
+				fflush(stdout);
+			}
+		}
+#endif
+
+		INTERRUPT_ASSERT(d->irq);
+
+		d->reg[MC_REGC * 4] |= MC_REGC_PF;
+	}
+
+	if (d->reg[MC_REGC * 4] & MC_REGC_UF ||
+	    d->reg[MC_REGC * 4] & MC_REGC_AF ||
+	    d->reg[MC_REGC * 4] & MC_REGC_PF)
+		d->reg[MC_REGC * 4] |= MC_REGC_IRQF;
+}
+
+
+/*
+ *  dev_mc146818_jazz_access():
+ *
+ *  It seems like JAZZ machines accesses the mc146818 by writing one byte to
+ *  0x90000070 and then reading or writing another byte at 0x......0004000.
+ */
+DEVICE_ACCESS(mc146818_jazz)
+{
+	struct mc_data *d = (struct mc_data *) extra;
+
+#ifdef MC146818_DEBUG
+	if (writeflag == MEM_WRITE) {
+		int i;
+		fatal("[ mc146818_jazz: write to addr=0x%04x: ",
+		    (int)relative_addr);
+		for (i=0; i<len; i++)
+			fatal("%02x ", data[i]);
+		fatal("]\n");
+	} else
+		fatal("[ mc146818_jazz: read from addr=0x%04x ]\n",
+		    (int)relative_addr);
+#endif
+
+	if (writeflag == MEM_WRITE) {
+		d->last_addr = data[0];
+		return 1;
+	} else {
+		data[0] = d->last_addr;
+		return 1;
+	}
+}
+
+
+/*
+ *  mc146818_update_time():
+ *
+ *  This function updates the MC146818 registers by reading
+ *  the host's clock.
+ */
+static void mc146818_update_time(struct mc_data *d)
+{
+	struct tm *tmp;
+	time_t timet;
+
+	timet = time(NULL);
+	tmp = gmtime(&timet);
+
+	d->reg[4 * MC_SEC]   = tmp->tm_sec;
+	d->reg[4 * MC_MIN]   = tmp->tm_min;
+	d->reg[4 * MC_HOUR]  = tmp->tm_hour;
+	d->reg[4 * MC_DOW]   = tmp->tm_wday + 1;
+	d->reg[4 * MC_DOM]   = tmp->tm_mday;
+	d->reg[4 * MC_MONTH] = tmp->tm_mon + 1;
+	d->reg[4 * MC_YEAR]  = tmp->tm_year;
+
+	/*
+	 *  Special hacks for emulating the behaviour of various machines:
+	 */
+	switch (d->access_style) {
+	case MC146818_ALGOR:
+		/*
+		 *  NetBSD/evbmips sources indicate that the Algor year base
+		 *  is 1920. This makes the time work with NetBSD in Malta
+		 *  emulation. However, for Linux, commenting out this line
+		 *  works better.  (TODO: Find a way to make both work?)
+		 */
+		d->reg[4 * MC_YEAR] += 80;
+		break;
+	case MC146818_ARC_NEC:
+		d->reg[4 * MC_YEAR] += (0x18 - 104);
+		break;
+	case MC146818_CATS:
+		d->reg[4 * MC_YEAR] %= 100;
+		break;
+	case MC146818_SGI:
+		/*
+		 *  NetBSD/sgimips assumes data in BCD format.
+		 *  Also, IRIX stores the year value in a weird
+		 *  format, according to ../arch/sgimips/sgimips/clockvar.h
+		 *  in NetBSD:
+		 *
+		 *  "If year < 1985, store (year - 1970), else
+		 *   (year - 1940). This matches IRIX semantics."
+		 *
+		 *  Another rule: It seems that a real SGI IP32 box
+		 *  uses the value 5 for the year 2005.
+		 */
+		d->reg[4 * MC_YEAR] =
+		    d->reg[4 * MC_YEAR] >= 100 ?
+			(d->reg[4 * MC_YEAR] - 100) :
+		      (
+			d->reg[4 * MC_YEAR] < 85 ?
+			  (d->reg[4 * MC_YEAR] - 30 + 40)
+			: (d->reg[4 * MC_YEAR] - 40)
+		      );
+		/*  Century:  */
+		d->reg[72 * 4] = 19 + (tmp->tm_year / 100);
+		break;
+	case MC146818_DEC:
+		/*
+		 *  DECstations must have 72 or 73 in the Year field, or
+		 *  Ultrix screems. This is also mentioned in NetBSD's
+		 *  mcclock.c.  Unfortunately, this means that NetBSD cannot
+		 *  know what year it actually is, so it has to deduce it
+		 *  from the filesystem.
+		 */
+		d->reg[4 * MC_YEAR] = 72;
+
+		/*
+		 *  Linux on DECstation stores the year in register 63,
+		 *  but no other DECstation OS does? (Hm.)
+		 */
+		d->reg[4 * 63]  = tmp->tm_year - 100;
+		break;
+	}
+
+	if (d->use_bcd) {
+		d->reg[4 * MC_SEC]   = to_bcd(d->reg[4 * MC_SEC]);
+		d->reg[4 * MC_MIN]   = to_bcd(d->reg[4 * MC_MIN]);
+		d->reg[4 * MC_HOUR]  = to_bcd(d->reg[4 * MC_HOUR]);
+		d->reg[4 * MC_DOW]   = to_bcd(d->reg[4 * MC_DOW]);
+		d->reg[4 * MC_DOM]   = to_bcd(d->reg[4 * MC_DOM]);
+		d->reg[4 * MC_MONTH] = to_bcd(d->reg[4 * MC_MONTH]);
+		d->reg[4 * MC_YEAR]  = to_bcd(d->reg[4 * MC_YEAR]);
+
+		/*  Used by Linux on DECstation: (Hm)  */
+		d->reg[4 * 63]       = to_bcd(d->reg[4 * 63]);
+
+		/*  Used on SGI:  */
+		d->reg[4 * 72]       = to_bcd(d->reg[4 * 72]);
+	}
+}
+
+
+DEVICE_ACCESS(mc146818)
+{
+	struct mc_data *d = (struct mc_data *) extra;
+	struct tm *tmp;
+	time_t timet;
+	size_t i;
+
+	/*  NOTE/TODO: This access function only handles 8-bit accesses!  */
+
+	relative_addr /= d->addrdiv;
+
+	/*  Different ways of accessing the registers:  */
+	switch (d->access_style) {
+	case MC146818_ALGOR:
+	case MC146818_CATS:
+	case MC146818_PC_CMOS:
+		if ((relative_addr & 1) == 0x00) {
+			if (writeflag == MEM_WRITE) {
+				d->last_addr = data[0];
+				return 1;
+			} else {
+				data[0] = d->last_addr;
+				return 1;
+			}
+		} else
+			relative_addr = d->last_addr * 4;
+		break;
+	case MC146818_ARC_NEC:
+		if (relative_addr == 0x01) {
+			if (writeflag == MEM_WRITE) {
+				d->last_addr = data[0];
+				return 1;
+			} else {
+				data[0] = d->last_addr;
+				return 1;
+			}
+		} else if (relative_addr == 0x00)
+			relative_addr = d->last_addr * 4;
+		else {
+			fatal("[ mc146818: not accessed as an "
+			    "MC146818_ARC_NEC device! ]\n");
+		}
+		break;
+	case MC146818_ARC_JAZZ:
+		/*  See comment for dev_mc146818_jazz_access().  */
+		relative_addr = d->last_addr * 4;
+		break;
+	case MC146818_DEC:
+	case MC146818_SGI:
+		/*
+		 *  This device was originally written for DECstation
+		 *  emulation, so no changes are necessary for that access
+		 *  style.
+		 *
+		 *  SGI access bytes 0x0..0xd at offsets 0x0yz..0xdyz, where yz
+		 *  should be ignored. It works _almost_ as DEC, if offsets are
+		 *  divided by 0x40.
+		 */
+		break;
+	case MC146818_PMPPC:
+		relative_addr *= 4;
+		break;
+	default:
+		;
+	}
+
+#ifdef MC146818_DEBUG
+	if (writeflag == MEM_WRITE) {
+		fatal("[ mc146818: write to addr=0x%04x (len %i): ",
+		    (int)relative_addr, (int)len);
+		for (i=0; i<len; i++)
+			fatal("0x%02x ", data[i]);
+		fatal("]\n");
+	}
+#endif
+
+	/*
+	 *  Sprite seems to wants UF interrupt status, once every second, or
+	 *  it hangs forever during bootup.  (These do not cause interrupts,
+	 *  but it is good enough... Sprite polls this, iirc.)
+	 *
+	 *  Linux on at least sgimips and evbmips (Malta) wants the UIP bit
+	 *  in REGA to be updated once a second.
+	 */
+	if (relative_addr == MC_REGA*4 || relative_addr == MC_REGC*4) {
+		timet = time(NULL);
+		tmp = gmtime(&timet);
+		d->reg[MC_REGC * 4] &= ~MC_REGC_UF;
+		if (tmp->tm_sec != d->previous_second) {
+			d->n_seconds_elapsed ++;
+			d->previous_second = tmp->tm_sec;
+		}
+		if (d->n_seconds_elapsed > d->uip_threshold) {
+			d->n_seconds_elapsed = 0;
+
+			d->reg[MC_REGA * 4] |= MC_REGA_UIP;
+
+			d->reg[MC_REGC * 4] |= MC_REGC_UF;
+			d->reg[MC_REGC * 4] |= MC_REGC_IRQF;
+
+			/*  For some reason, some Linux/DECstation KN04
+			    kernels want the PF (periodic flag) bit set,
+			    even though interrupts are not enabled?  */
+			d->reg[MC_REGC * 4] |= MC_REGC_PF;
+		} else
+			d->reg[MC_REGA * 4] &= ~MC_REGA_UIP;
+	}
+
+	/*  RTC data is in either BCD format or binary:  */
+	if (d->use_bcd)
+		d->reg[MC_REGB * 4] &= ~(1 << 2);
+	else
+		d->reg[MC_REGB * 4] |= (1 << 2);
+
+	/*  RTC date/time is always Valid:  */
+	d->reg[MC_REGD * 4] |= MC_REGD_VRT;
+
+	if (writeflag == MEM_WRITE) {
+		/*  WRITE:  */
+		switch (relative_addr) {
+		case MC_REGA*4:
+			if ((data[0] & MC_REGA_DVMASK) == MC_BASE_32_KHz)
+				d->timebase_hz = 32000;
+			if ((data[0] & MC_REGA_DVMASK) == MC_BASE_1_MHz)
+				d->timebase_hz = 1000000;
+			if ((data[0] & MC_REGA_DVMASK) == MC_BASE_4_MHz)
+				d->timebase_hz = 4000000;
+			switch (data[0] & MC_REGA_RSMASK) {
+			case MC_RATE_NONE:
+				d->interrupt_hz = 0;
+				break;
+			case MC_RATE_1:
+				if (d->timebase_hz == 32000)
+					d->interrupt_hz = 256;
+				else
+					d->interrupt_hz = 32768;
+				break;
+			case MC_RATE_2:
+				if (d->timebase_hz == 32000)
+					d->interrupt_hz = 128;
+				else
+					d->interrupt_hz = 16384;
+				break;
+			case MC_RATE_8192_Hz:	d->interrupt_hz = 8192;	break;
+			case MC_RATE_4096_Hz:	d->interrupt_hz = 4096;	break;
+			case MC_RATE_2048_Hz:	d->interrupt_hz = 2048;	break;
+			case MC_RATE_1024_Hz:	d->interrupt_hz = 1024;	break;
+			case MC_RATE_512_Hz:	d->interrupt_hz = 512;	break;
+			case MC_RATE_256_Hz:	d->interrupt_hz = 256;	break;
+			case MC_RATE_128_Hz:	d->interrupt_hz = 128;	break;
+			case MC_RATE_64_Hz:	d->interrupt_hz = 64;	break;
+			case MC_RATE_32_Hz:	d->interrupt_hz = 32;	break;
+			case MC_RATE_16_Hz:	d->interrupt_hz = 16;	break;
+			case MC_RATE_8_Hz:	d->interrupt_hz = 8;	break;
+			case MC_RATE_4_Hz:	d->interrupt_hz = 4;	break;
+			case MC_RATE_2_Hz:	d->interrupt_hz = 2;	break;
+			default:/*  debug("[ mc146818: unimplemented "
+				    "MC_REGA RS: %i ]\n",
+				    data[0] & MC_REGA_RSMASK);  */
+				;
+			}
+
+			if (d->interrupt_hz != d->old_interrupt_hz) {
+				debug("[ rtc changed to interrupt at %i Hz ]\n",
+				    d->interrupt_hz);
+
+				d->old_interrupt_hz = d->interrupt_hz;
+
+				if (d->timer == NULL)
+					d->timer = timer_add(d->interrupt_hz,
+					    timer_tick, d);
+				else
+					timer_update_frequency(d->timer,
+					    d->interrupt_hz);
+			}
+
+			d->reg[MC_REGA * 4] =
+			    data[0] & (MC_REGA_RSMASK | MC_REGA_DVMASK);
+			break;
+		case MC_REGB*4:
+			d->reg[MC_REGB*4] = data[0];
+			if (!(data[0] & MC_REGB_PIE)) {
+				INTERRUPT_DEASSERT(d->irq);
+			}
+
+			/*  debug("[ mc146818: write to MC_REGB, data[0] "
+			    "= 0x%02x ]\n", data[0]);  */
+			break;
+		case MC_REGC*4:
+			d->reg[MC_REGC * 4] = data[0];
+			debug("[ mc146818: write to MC_REGC, data[0] = "
+			    "0x%02x ]\n", data[0]);
+			break;
+		case 0x128:
+			d->reg[relative_addr] = data[0];
+			if (data[0] & 8) {
+				int j;
+
+				/*  Used on SGI to power off the machine.  */
+				fatal("[ md146818: power off ]\n");
+				for (j=0; j<cpu->machine->ncpus; j++)
+					cpu->machine->cpus[j]->running = false;
+			}
+			break;
+		default:
+			d->reg[relative_addr] = data[0];
+
+			debug("[ mc146818: unimplemented write to "
+			    "relative_addr = %08lx: ", (long)relative_addr);
+			for (i=0; i<len; i++)
+				debug("%02x ", data[i]);
+			debug("]\n");
+		}
+	} else {
+		/*  READ:  */
+		switch (relative_addr) {
+		case 0x01:	/*  Station's ethernet address (6 bytes)  */
+		case 0x05:	/*  (on DECstation 3100)  */
+		case 0x09:
+		case 0x0d:
+		case 0x11:
+		case 0x15:
+			break;
+		case 4 * MC_SEC:
+			if (d->ugly_netbsd_prep_hack_done < NETBSD_HACK_DONE) {
+				d->ugly_netbsd_prep_hack_done ++;
+				switch (d->ugly_netbsd_prep_hack_done) {
+				case NETBSD_HACK_FIRST_1:
+					d->ugly_netbsd_prep_hack_sec =
+					    from_bcd(d->reg[relative_addr]);
+					break;
+				case NETBSD_HACK_FIRST_2:
+					d->reg[relative_addr] = to_bcd(
+					    d->ugly_netbsd_prep_hack_sec);
+					break;
+				case NETBSD_HACK_SECOND_1:
+				case NETBSD_HACK_SECOND_2:
+					d->reg[relative_addr] = to_bcd((1 +
+					    d->ugly_netbsd_prep_hack_sec) % 60);
+					break;
+				}
+			}
+			// fall through
+		case 4 * MC_MIN:
+		case 4 * MC_HOUR:
+		case 4 * MC_DOW:
+		case 4 * MC_DOM:
+		case 4 * MC_MONTH:
+		case 4 * MC_YEAR:
+		case 4 * 63:	/*  63 is used by Linux on DECstation  */
+		case 4 * 72:	/*  72 is Century, on SGI (DS1687)  */
+			/*
+			 *  If the SET bit is set, then we don't automatically
+			 *  update the values.  Otherwise, we update them by
+			 *  reading from the host's clock:
+			 */
+			if (d->reg[MC_REGB * 4] & MC_REGB_SET)
+				break;
+
+			if (d->ugly_netbsd_prep_hack_done >= NETBSD_HACK_DONE)
+				mc146818_update_time(d);
+			break;
+		case 4 * MC_REGA:
+			break;
+		case 4 * MC_REGC:	/*  Interrupt ack.  */
+			/*  NOTE: Acking is done below, _after_ the
+			    register has been read.  */
+			break;
+		default:debug("[ mc146818: read from relative_addr = "
+			    "%04x ]\n", (int)relative_addr);
+		}
+
+		data[0] = d->reg[relative_addr];
+
+		if (relative_addr == MC_REGC*4) {
+			INTERRUPT_DEASSERT(d->irq);
+
+			/*
+			 *  Acknowledging an interrupt decreases the
+			 *  number of pending "real world" timer ticks.
+			 */
+			if (d->reg[MC_REGC * 4] & MC_REGC_PF &&
+			    d->pending_timer_interrupts > 0)
+				d->pending_timer_interrupts --;
+
+			d->reg[MC_REGC * 4] = 0x00;
+		}
+	}
+
+#ifdef MC146818_DEBUG
+	if (writeflag == MEM_READ) {
+		fatal("[ mc146818: read from addr=0x%04x (len %i): ",
+		    (int)relative_addr, (int)len);
+		for (i=0; i<len; i++)
+			fatal("0x%02x ", data[i]);
+		fatal("]\n");
+	}
+#endif
+
+	return 1;
+}
+
+
+/*
+ *  dev_mc146818_init():
+ *
+ *  This needs to work for both DECstation emulation and other machine types,
+ *  so it contains both rtc related stuff and the station's Ethernet address.
+ */
+void dev_mc146818_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, char *irq_path, int access_style, int addrdiv)
+{
+	unsigned char ether_address[6];
+	int i, dev_len;
+	struct mc_data *d;
+
+	CHECK_ALLOCATION(d = (struct mc_data *) malloc(sizeof(struct mc_data)));
+	memset(d, 0, sizeof(struct mc_data));
+
+	d->access_style  = access_style;
+	d->addrdiv       = addrdiv;
+
+	INTERRUPT_CONNECT(irq_path, d->irq);
+
+	d->use_bcd = 0;
+	switch (access_style) {
+	case MC146818_SGI:
+	case MC146818_PC_CMOS:
+	case MC146818_PMPPC:
+		d->use_bcd = 1;
+	}
+
+	if (machine->machine_type != MACHINE_PREP) {
+		/*  NetBSD/prep has a really ugly clock detection code;
+		    no other machines/OSes don't need this.  */
+		d->ugly_netbsd_prep_hack_done = NETBSD_HACK_DONE;
+	}
+
+	if (access_style == MC146818_DEC) {
+		/*  Station Ethernet Address, on DECstation 3100:  */
+		for (i=0; i<6; i++)
+			ether_address[i] = 0x10 * (i+1);
+
+		d->reg[0x01] = ether_address[0];
+		d->reg[0x05] = ether_address[1];
+		d->reg[0x09] = ether_address[2];
+		d->reg[0x0d] = ether_address[3];
+		d->reg[0x11] = ether_address[4];
+		d->reg[0x15] = ether_address[5];
+		/*  TODO:  19, 1d, 21, 25 = checksum bytes 1,2,2,1 resp. */
+		d->reg[0x29] = ether_address[5];
+		d->reg[0x2d] = ether_address[4];
+		d->reg[0x31] = ether_address[3];
+		d->reg[0x35] = ether_address[2];
+		d->reg[0x39] = ether_address[1];
+		d->reg[0x3d] = ether_address[1];
+		d->reg[0x41] = ether_address[0];
+		d->reg[0x45] = ether_address[1];
+		d->reg[0x49] = ether_address[2];
+		d->reg[0x4d] = ether_address[3];
+		d->reg[0x51] = ether_address[4];
+		d->reg[0x55] = ether_address[5];
+		/*  TODO:  59, 5d = checksum bytes 1,2 resp. */
+		d->reg[0x61] = 0xff;
+		d->reg[0x65] = 0x00;
+		d->reg[0x69] = 0x55;
+		d->reg[0x6d] = 0xaa;
+		d->reg[0x71] = 0xff;
+		d->reg[0x75] = 0x00;
+		d->reg[0x79] = 0x55;
+		d->reg[0x7d] = 0xaa;
+
+		/*  Battery valid, for DECstations  */
+		d->reg[0xf8] = 1;
+	}
+
+	/*
+	 *  uip_threshold should ideally be 1, but when Linux polls the UIP bit
+	 *  it looses speed. This hack gives Linux the impression that the cpu
+	 *  is uip_threshold times faster than the slow clock it would
+	 *  otherwise detect.
+	 *
+	 *  TODO:  Find out if this messes up Sprite emulation; if so, then
+	 *         this hack has to be removed.
+	 */
+	d->uip_threshold = 8;
+
+	if (access_style == MC146818_ARC_JAZZ)
+		memory_device_register(mem, "mc146818_jazz", 0x90000070ULL,
+		    1, dev_mc146818_jazz_access, d, DM_DEFAULT, NULL);
+
+	dev_len = DEV_MC146818_LENGTH;
+	switch (access_style) {
+	case MC146818_CATS:
+	case MC146818_PC_CMOS:
+		dev_len = 2;
+		break;
+	case MC146818_SGI:
+		dev_len = 0x400;
+	}
+
+	memory_device_register(mem, "mc146818", baseaddr,
+	    dev_len * addrdiv, dev_mc146818_access,
+	    d, DM_DEFAULT, NULL);
+
+	mc146818_update_time(d);
+
+	machine_add_tickfunction(machine, dev_mc146818_tick, d,
+	    MC146818_TICK_SHIFT);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_mc146818.cc gxemul-0.7.0+dfsg/src/devices/dev_mc146818.cc
--- gxemul-0.6.2/src/devices/dev_mc146818.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_mc146818.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,688 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: MC146818 real-time clock
- *
- *  (DS1687 as used in some other machines is also similar to the MC146818.)
- *
- *  This device contains Date/time, the machine's ethernet address (on
- *  DECstation 3100), and can cause periodic (hardware) interrupts.
- *
- *  NOTE: Many register offsets are multiplied by 4 in this code; this is
- *  because I originally wrote it for DECstation 3100 emulation, where the
- *  registered are spaced that way.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "timer.h"
-
-#include "thirdparty/mc146818reg.h"
-
-
-#define	to_bcd(x)	( ((x)/10) * 16 + ((x)%10) )
-#define	from_bcd(x)	( ((x)>>4) * 10 + ((x)&15) )
-
-/*  #define MC146818_DEBUG  */
-
-#define	MC146818_TICK_SHIFT	14
-
-
-/*  256 on DECstation, SGI uses reg at 72*4 as the Century  */
-#define	N_REGISTERS	1024
-struct mc_data {
-	int		access_style;
-	int		last_addr;
-
-	int		register_choice;
-	int		reg[N_REGISTERS];
-	int		addrdiv;
-
-	int		use_bcd;
-
-	int		timebase_hz;
-	int		interrupt_hz;
-	int		old_interrupt_hz;
-	struct interrupt irq;
-	struct timer	*timer;
-	volatile int	pending_timer_interrupts;
-
-	int		previous_second;
-	int		n_seconds_elapsed;
-	int		uip_threshold;
-
-	int		ugly_netbsd_prep_hack_done;
-	int		ugly_netbsd_prep_hack_sec;
-};
-
-
-/*
- *  Ugly hack to fool NetBSD/prep to accept the clock.  (See mcclock_isa_match
- *  in NetBSD's arch/prep/isa/mcclock_isa.c for details.)
- */
-#define	NETBSD_HACK_INIT		0
-#define	NETBSD_HACK_FIRST_1		1
-#define	NETBSD_HACK_FIRST_2		2
-#define	NETBSD_HACK_SECOND_1		3
-#define	NETBSD_HACK_SECOND_2		4
-#define	NETBSD_HACK_DONE		5
-
-
-/*
- *  timer_tick():
- *
- *  Called d->interrupt_hz times per (real-world) second.
- */
-static void timer_tick(struct timer *timer, void *extra)
-{
-	struct mc_data *d = (struct mc_data *) extra;
-	d->pending_timer_interrupts ++;
-}
-
-
-DEVICE_TICK(mc146818)
-{
-	struct mc_data *d = (struct mc_data *) extra;
-	int pti = d->pending_timer_interrupts;
-
-	if ((d->reg[MC_REGB * 4] & MC_REGB_PIE) && pti > 0) {
-#if 0
-		/*  For debugging, to see how much the interrupts are
-		    lagging behind the real clock:  */
-		{
-			static int x = 0;
-			if (++x == 1) {
-				x = 0;
-				printf("%i ", pti);
-				fflush(stdout);
-			}
-		}
-#endif
-
-		INTERRUPT_ASSERT(d->irq);
-
-		d->reg[MC_REGC * 4] |= MC_REGC_PF;
-	}
-
-	if (d->reg[MC_REGC * 4] & MC_REGC_UF ||
-	    d->reg[MC_REGC * 4] & MC_REGC_AF ||
-	    d->reg[MC_REGC * 4] & MC_REGC_PF)
-		d->reg[MC_REGC * 4] |= MC_REGC_IRQF;
-}
-
-
-/*
- *  dev_mc146818_jazz_access():
- *
- *  It seems like JAZZ machines accesses the mc146818 by writing one byte to
- *  0x90000070 and then reading or writing another byte at 0x......0004000.
- */
-DEVICE_ACCESS(mc146818_jazz)
-{
-	struct mc_data *d = (struct mc_data *) extra;
-
-#ifdef MC146818_DEBUG
-	if (writeflag == MEM_WRITE) {
-		int i;
-		fatal("[ mc146818_jazz: write to addr=0x%04x: ",
-		    (int)relative_addr);
-		for (i=0; i<len; i++)
-			fatal("%02x ", data[i]);
-		fatal("]\n");
-	} else
-		fatal("[ mc146818_jazz: read from addr=0x%04x ]\n",
-		    (int)relative_addr);
-#endif
-
-	if (writeflag == MEM_WRITE) {
-		d->last_addr = data[0];
-		return 1;
-	} else {
-		data[0] = d->last_addr;
-		return 1;
-	}
-}
-
-
-/*
- *  mc146818_update_time():
- *
- *  This function updates the MC146818 registers by reading
- *  the host's clock.
- */
-static void mc146818_update_time(struct mc_data *d)
-{
-	struct tm *tmp;
-	time_t timet;
-
-	timet = time(NULL);
-	tmp = gmtime(&timet);
-
-	d->reg[4 * MC_SEC]   = tmp->tm_sec;
-	d->reg[4 * MC_MIN]   = tmp->tm_min;
-	d->reg[4 * MC_HOUR]  = tmp->tm_hour;
-	d->reg[4 * MC_DOW]   = tmp->tm_wday + 1;
-	d->reg[4 * MC_DOM]   = tmp->tm_mday;
-	d->reg[4 * MC_MONTH] = tmp->tm_mon + 1;
-	d->reg[4 * MC_YEAR]  = tmp->tm_year;
-
-	/*
-	 *  Special hacks for emulating the behaviour of various machines:
-	 */
-	switch (d->access_style) {
-	case MC146818_ALGOR:
-		/*
-		 *  NetBSD/evbmips sources indicate that the Algor year base
-		 *  is 1920. This makes the time work with NetBSD in Malta
-		 *  emulation. However, for Linux, commenting out this line
-		 *  works better.  (TODO: Find a way to make both work?)
-		 */
-		d->reg[4 * MC_YEAR] += 80;
-		break;
-	case MC146818_ARC_NEC:
-		d->reg[4 * MC_YEAR] += (0x18 - 104);
-		break;
-	case MC146818_CATS:
-		d->reg[4 * MC_YEAR] %= 100;
-		break;
-	case MC146818_SGI:
-		/*
-		 *  NetBSD/sgimips assumes data in BCD format.
-		 *  Also, IRIX stores the year value in a weird
-		 *  format, according to ../arch/sgimips/sgimips/clockvar.h
-		 *  in NetBSD:
-		 *
-		 *  "If year < 1985, store (year - 1970), else
-		 *   (year - 1940). This matches IRIX semantics."
-		 *
-		 *  Another rule: It seems that a real SGI IP32 box
-		 *  uses the value 5 for the year 2005.
-		 */
-		d->reg[4 * MC_YEAR] =
-		    d->reg[4 * MC_YEAR] >= 100 ?
-			(d->reg[4 * MC_YEAR] - 100) :
-		      (
-			d->reg[4 * MC_YEAR] < 85 ?
-			  (d->reg[4 * MC_YEAR] - 30 + 40)
-			: (d->reg[4 * MC_YEAR] - 40)
-		      );
-		/*  Century:  */
-		d->reg[72 * 4] = 19 + (tmp->tm_year / 100);
-		break;
-	case MC146818_DEC:
-		/*
-		 *  DECstations must have 72 or 73 in the
-		 *  Year field, or Ultrix screems.  (Weird.)
-		 */
-		d->reg[4 * MC_YEAR] = 72;
-
-		/*
-		 *  Linux on DECstation stores the year in register 63,
-		 *  but no other DECstation OS does? (Hm.)
-		 */
-		d->reg[4 * 63]  = tmp->tm_year - 100;
-		break;
-	}
-
-	if (d->use_bcd) {
-		d->reg[4 * MC_SEC]   = to_bcd(d->reg[4 * MC_SEC]);
-		d->reg[4 * MC_MIN]   = to_bcd(d->reg[4 * MC_MIN]);
-		d->reg[4 * MC_HOUR]  = to_bcd(d->reg[4 * MC_HOUR]);
-		d->reg[4 * MC_DOW]   = to_bcd(d->reg[4 * MC_DOW]);
-		d->reg[4 * MC_DOM]   = to_bcd(d->reg[4 * MC_DOM]);
-		d->reg[4 * MC_MONTH] = to_bcd(d->reg[4 * MC_MONTH]);
-		d->reg[4 * MC_YEAR]  = to_bcd(d->reg[4 * MC_YEAR]);
-
-		/*  Used by Linux on DECstation: (Hm)  */
-		d->reg[4 * 63]       = to_bcd(d->reg[4 * 63]);
-
-		/*  Used on SGI:  */
-		d->reg[4 * 72]       = to_bcd(d->reg[4 * 72]);
-	}
-}
-
-
-DEVICE_ACCESS(mc146818)
-{
-	struct mc_data *d = (struct mc_data *) extra;
-	struct tm *tmp;
-	time_t timet;
-	size_t i;
-
-	/*  NOTE/TODO: This access function only handles 8-bit accesses!  */
-
-	relative_addr /= d->addrdiv;
-
-	/*  Different ways of accessing the registers:  */
-	switch (d->access_style) {
-	case MC146818_ALGOR:
-	case MC146818_CATS:
-	case MC146818_PC_CMOS:
-		if ((relative_addr & 1) == 0x00) {
-			if (writeflag == MEM_WRITE) {
-				d->last_addr = data[0];
-				return 1;
-			} else {
-				data[0] = d->last_addr;
-				return 1;
-			}
-		} else
-			relative_addr = d->last_addr * 4;
-		break;
-	case MC146818_ARC_NEC:
-		if (relative_addr == 0x01) {
-			if (writeflag == MEM_WRITE) {
-				d->last_addr = data[0];
-				return 1;
-			} else {
-				data[0] = d->last_addr;
-				return 1;
-			}
-		} else if (relative_addr == 0x00)
-			relative_addr = d->last_addr * 4;
-		else {
-			fatal("[ mc146818: not accessed as an "
-			    "MC146818_ARC_NEC device! ]\n");
-		}
-		break;
-	case MC146818_ARC_JAZZ:
-		/*  See comment for dev_mc146818_jazz_access().  */
-		relative_addr = d->last_addr * 4;
-		break;
-	case MC146818_DEC:
-	case MC146818_SGI:
-		/*
-		 *  This device was originally written for DECstation
-		 *  emulation, so no changes are necessary for that access
-		 *  style.
-		 *
-		 *  SGI access bytes 0x0..0xd at offsets 0x0yz..0xdyz, where yz
-		 *  should be ignored. It works _almost_ as DEC, if offsets are
-		 *  divided by 0x40.
-		 */
-		break;
-	case MC146818_PMPPC:
-		relative_addr *= 4;
-		break;
-	default:
-		;
-	}
-
-#ifdef MC146818_DEBUG
-	if (writeflag == MEM_WRITE) {
-		fatal("[ mc146818: write to addr=0x%04x (len %i): ",
-		    (int)relative_addr, (int)len);
-		for (i=0; i<len; i++)
-			fatal("0x%02x ", data[i]);
-		fatal("]\n");
-	}
-#endif
-
-	/*
-	 *  Sprite seems to wants UF interrupt status, once every second, or
-	 *  it hangs forever during bootup.  (These do not cause interrupts,
-	 *  but it is good enough... Sprite polls this, iirc.)
-	 *
-	 *  Linux on at least sgimips and evbmips (Malta) wants the UIP bit
-	 *  in REGA to be updated once a second.
-	 */
-	if (relative_addr == MC_REGA*4 || relative_addr == MC_REGC*4) {
-		timet = time(NULL);
-		tmp = gmtime(&timet);
-		d->reg[MC_REGC * 4] &= ~MC_REGC_UF;
-		if (tmp->tm_sec != d->previous_second) {
-			d->n_seconds_elapsed ++;
-			d->previous_second = tmp->tm_sec;
-		}
-		if (d->n_seconds_elapsed > d->uip_threshold) {
-			d->n_seconds_elapsed = 0;
-
-			d->reg[MC_REGA * 4] |= MC_REGA_UIP;
-
-			d->reg[MC_REGC * 4] |= MC_REGC_UF;
-			d->reg[MC_REGC * 4] |= MC_REGC_IRQF;
-
-			/*  For some reason, some Linux/DECstation KN04
-			    kernels want the PF (periodic flag) bit set,
-			    even though interrupts are not enabled?  */
-			d->reg[MC_REGC * 4] |= MC_REGC_PF;
-		} else
-			d->reg[MC_REGA * 4] &= ~MC_REGA_UIP;
-	}
-
-	/*  RTC data is in either BCD format or binary:  */
-	if (d->use_bcd)
-		d->reg[MC_REGB * 4] &= ~(1 << 2);
-	else
-		d->reg[MC_REGB * 4] |= (1 << 2);
-
-	/*  RTC date/time is always Valid:  */
-	d->reg[MC_REGD * 4] |= MC_REGD_VRT;
-
-	if (writeflag == MEM_WRITE) {
-		/*  WRITE:  */
-		switch (relative_addr) {
-		case MC_REGA*4:
-			if ((data[0] & MC_REGA_DVMASK) == MC_BASE_32_KHz)
-				d->timebase_hz = 32000;
-			if ((data[0] & MC_REGA_DVMASK) == MC_BASE_1_MHz)
-				d->timebase_hz = 1000000;
-			if ((data[0] & MC_REGA_DVMASK) == MC_BASE_4_MHz)
-				d->timebase_hz = 4000000;
-			switch (data[0] & MC_REGA_RSMASK) {
-			case MC_RATE_NONE:
-				d->interrupt_hz = 0;
-				break;
-			case MC_RATE_1:
-				if (d->timebase_hz == 32000)
-					d->interrupt_hz = 256;
-				else
-					d->interrupt_hz = 32768;
-				break;
-			case MC_RATE_2:
-				if (d->timebase_hz == 32000)
-					d->interrupt_hz = 128;
-				else
-					d->interrupt_hz = 16384;
-				break;
-			case MC_RATE_8192_Hz:	d->interrupt_hz = 8192;	break;
-			case MC_RATE_4096_Hz:	d->interrupt_hz = 4096;	break;
-			case MC_RATE_2048_Hz:	d->interrupt_hz = 2048;	break;
-			case MC_RATE_1024_Hz:	d->interrupt_hz = 1024;	break;
-			case MC_RATE_512_Hz:	d->interrupt_hz = 512;	break;
-			case MC_RATE_256_Hz:	d->interrupt_hz = 256;	break;
-			case MC_RATE_128_Hz:	d->interrupt_hz = 128;	break;
-			case MC_RATE_64_Hz:	d->interrupt_hz = 64;	break;
-			case MC_RATE_32_Hz:	d->interrupt_hz = 32;	break;
-			case MC_RATE_16_Hz:	d->interrupt_hz = 16;	break;
-			case MC_RATE_8_Hz:	d->interrupt_hz = 8;	break;
-			case MC_RATE_4_Hz:	d->interrupt_hz = 4;	break;
-			case MC_RATE_2_Hz:	d->interrupt_hz = 2;	break;
-			default:/*  debug("[ mc146818: unimplemented "
-				    "MC_REGA RS: %i ]\n",
-				    data[0] & MC_REGA_RSMASK);  */
-				;
-			}
-
-			if (d->interrupt_hz != d->old_interrupt_hz) {
-				debug("[ rtc changed to interrupt at %i Hz ]\n",
-				    d->interrupt_hz);
-
-				d->old_interrupt_hz = d->interrupt_hz;
-
-				if (d->timer == NULL)
-					d->timer = timer_add(d->interrupt_hz,
-					    timer_tick, d);
-				else
-					timer_update_frequency(d->timer,
-					    d->interrupt_hz);
-			}
-
-			d->reg[MC_REGA * 4] =
-			    data[0] & (MC_REGA_RSMASK | MC_REGA_DVMASK);
-			break;
-		case MC_REGB*4:
-			d->reg[MC_REGB*4] = data[0];
-			if (!(data[0] & MC_REGB_PIE)) {
-				INTERRUPT_DEASSERT(d->irq);
-			}
-
-			/*  debug("[ mc146818: write to MC_REGB, data[0] "
-			    "= 0x%02x ]\n", data[0]);  */
-			break;
-		case MC_REGC*4:
-			d->reg[MC_REGC * 4] = data[0];
-			debug("[ mc146818: write to MC_REGC, data[0] = "
-			    "0x%02x ]\n", data[0]);
-			break;
-		case 0x128:
-			d->reg[relative_addr] = data[0];
-			if (data[0] & 8) {
-				int j;
-
-				/*  Used on SGI to power off the machine.  */
-				fatal("[ md146818: power off ]\n");
-				for (j=0; j<cpu->machine->ncpus; j++)
-					cpu->machine->cpus[j]->running = 0;
-				cpu->machine->
-				    exit_without_entering_debugger = 1;
-			}
-			break;
-		default:
-			d->reg[relative_addr] = data[0];
-
-			debug("[ mc146818: unimplemented write to "
-			    "relative_addr = %08lx: ", (long)relative_addr);
-			for (i=0; i<len; i++)
-				debug("%02x ", data[i]);
-			debug("]\n");
-		}
-	} else {
-		/*  READ:  */
-		switch (relative_addr) {
-		case 0x01:	/*  Station's ethernet address (6 bytes)  */
-		case 0x05:	/*  (on DECstation 3100)  */
-		case 0x09:
-		case 0x0d:
-		case 0x11:
-		case 0x15:
-			break;
-		case 4 * MC_SEC:
-			if (d->ugly_netbsd_prep_hack_done < NETBSD_HACK_DONE) {
-				d->ugly_netbsd_prep_hack_done ++;
-				switch (d->ugly_netbsd_prep_hack_done) {
-				case NETBSD_HACK_FIRST_1:
-					d->ugly_netbsd_prep_hack_sec =
-					    from_bcd(d->reg[relative_addr]);
-					break;
-				case NETBSD_HACK_FIRST_2:
-					d->reg[relative_addr] = to_bcd(
-					    d->ugly_netbsd_prep_hack_sec);
-					break;
-				case NETBSD_HACK_SECOND_1:
-				case NETBSD_HACK_SECOND_2:
-					d->reg[relative_addr] = to_bcd((1 +
-					    d->ugly_netbsd_prep_hack_sec) % 60);
-					break;
-				}
-			}
-		case 4 * MC_MIN:
-		case 4 * MC_HOUR:
-		case 4 * MC_DOW:
-		case 4 * MC_DOM:
-		case 4 * MC_MONTH:
-		case 4 * MC_YEAR:
-		case 4 * 63:	/*  63 is used by Linux on DECstation  */
-		case 4 * 72:	/*  72 is Century, on SGI (DS1687)  */
-			/*
-			 *  If the SET bit is set, then we don't automatically
-			 *  update the values.  Otherwise, we update them by
-			 *  reading from the host's clock:
-			 */
-			if (d->reg[MC_REGB * 4] & MC_REGB_SET)
-				break;
-
-			if (d->ugly_netbsd_prep_hack_done >= NETBSD_HACK_DONE)
-				mc146818_update_time(d);
-			break;
-		case 4 * MC_REGA:
-			break;
-		case 4 * MC_REGC:	/*  Interrupt ack.  */
-			/*  NOTE: Acking is done below, _after_ the
-			    register has been read.  */
-			break;
-		default:debug("[ mc146818: read from relative_addr = "
-			    "%04x ]\n", (int)relative_addr);
-		}
-
-		data[0] = d->reg[relative_addr];
-
-		if (relative_addr == MC_REGC*4) {
-			INTERRUPT_DEASSERT(d->irq);
-
-			/*
-			 *  Acknowledging an interrupt decreases the
-			 *  number of pending "real world" timer ticks.
-			 */
-			if (d->reg[MC_REGC * 4] & MC_REGC_PF &&
-			    d->pending_timer_interrupts > 0)
-				d->pending_timer_interrupts --;
-
-			d->reg[MC_REGC * 4] = 0x00;
-		}
-	}
-
-#ifdef MC146818_DEBUG
-	if (writeflag == MEM_READ) {
-		fatal("[ mc146818: read from addr=0x%04x (len %i): ",
-		    (int)relative_addr, (int)len);
-		for (i=0; i<len; i++)
-			fatal("0x%02x ", data[i]);
-		fatal("]\n");
-	}
-#endif
-
-	return 1;
-}
-
-
-/*
- *  dev_mc146818_init():
- *
- *  This needs to work for both DECstation emulation and other machine types,
- *  so it contains both rtc related stuff and the station's Ethernet address.
- */
-void dev_mc146818_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, char *irq_path, int access_style, int addrdiv)
-{
-	unsigned char ether_address[6];
-	int i, dev_len;
-	struct mc_data *d;
-
-	CHECK_ALLOCATION(d = (struct mc_data *) malloc(sizeof(struct mc_data)));
-	memset(d, 0, sizeof(struct mc_data));
-
-	d->access_style  = access_style;
-	d->addrdiv       = addrdiv;
-
-	INTERRUPT_CONNECT(irq_path, d->irq);
-
-	d->use_bcd = 0;
-	switch (access_style) {
-	case MC146818_SGI:
-	case MC146818_PC_CMOS:
-	case MC146818_PMPPC:
-		d->use_bcd = 1;
-	}
-
-	if (machine->machine_type != MACHINE_PREP) {
-		/*  NetBSD/prep has a really ugly clock detection code;
-		    no other machines/OSes don't need this.  */
-		d->ugly_netbsd_prep_hack_done = NETBSD_HACK_DONE;
-	}
-
-	if (access_style == MC146818_DEC) {
-		/*  Station Ethernet Address, on DECstation 3100:  */
-		for (i=0; i<6; i++)
-			ether_address[i] = 0x10 * (i+1);
-
-		d->reg[0x01] = ether_address[0];
-		d->reg[0x05] = ether_address[1];
-		d->reg[0x09] = ether_address[2];
-		d->reg[0x0d] = ether_address[3];
-		d->reg[0x11] = ether_address[4];
-		d->reg[0x15] = ether_address[5];
-		/*  TODO:  19, 1d, 21, 25 = checksum bytes 1,2,2,1 resp. */
-		d->reg[0x29] = ether_address[5];
-		d->reg[0x2d] = ether_address[4];
-		d->reg[0x31] = ether_address[3];
-		d->reg[0x35] = ether_address[2];
-		d->reg[0x39] = ether_address[1];
-		d->reg[0x3d] = ether_address[1];
-		d->reg[0x41] = ether_address[0];
-		d->reg[0x45] = ether_address[1];
-		d->reg[0x49] = ether_address[2];
-		d->reg[0x4d] = ether_address[3];
-		d->reg[0x51] = ether_address[4];
-		d->reg[0x55] = ether_address[5];
-		/*  TODO:  59, 5d = checksum bytes 1,2 resp. */
-		d->reg[0x61] = 0xff;
-		d->reg[0x65] = 0x00;
-		d->reg[0x69] = 0x55;
-		d->reg[0x6d] = 0xaa;
-		d->reg[0x71] = 0xff;
-		d->reg[0x75] = 0x00;
-		d->reg[0x79] = 0x55;
-		d->reg[0x7d] = 0xaa;
-
-		/*  Battery valid, for DECstations  */
-		d->reg[0xf8] = 1;
-	}
-
-	/*
-	 *  uip_threshold should ideally be 1, but when Linux polls the UIP bit
-	 *  it looses speed. This hack gives Linux the impression that the cpu
-	 *  is uip_threshold times faster than the slow clock it would
-	 *  otherwise detect.
-	 *
-	 *  TODO:  Find out if this messes up Sprite emulation; if so, then
-	 *         this hack has to be removed.
-	 */
-	d->uip_threshold = 8;
-
-	if (access_style == MC146818_ARC_JAZZ)
-		memory_device_register(mem, "mc146818_jazz", 0x90000070ULL,
-		    1, dev_mc146818_jazz_access, d, DM_DEFAULT, NULL);
-
-	dev_len = DEV_MC146818_LENGTH;
-	switch (access_style) {
-	case MC146818_CATS:
-	case MC146818_PC_CMOS:
-		dev_len = 2;
-		break;
-	case MC146818_SGI:
-		dev_len = 0x400;
-	}
-
-	memory_device_register(mem, "mc146818", baseaddr,
-	    dev_len * addrdiv, dev_mc146818_access,
-	    d, DM_DEFAULT, NULL);
-
-	mc146818_update_time(d);
-
-	machine_add_tickfunction(machine, dev_mc146818_tick, d,
-	    MC146818_TICK_SHIFT);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_mk48txx.c gxemul-0.7.0+dfsg/src/devices/dev_mk48txx.c
--- gxemul-0.6.2/src/devices/dev_mk48txx.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_mk48txx.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,144 @@
+/*
+ *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Mostek MK48Txx Real Time Clock
+ *
+ *  TODO:
+ *	Only the MK48T08 is implemented so far.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/mk48txxreg.h"
+
+
+#define	MK48TXX_LEN		MK48T08_CLKSZ
+
+#define	BCD(x)	((((x) / 10) << 4) + ((x) % 10))
+
+struct mk48txx_data {
+	uint8_t		reg[MK48TXX_LEN];
+};
+
+
+void mk48txx_update_regs(struct mk48txx_data *d)
+{
+	struct tm *tmp;
+	time_t timet;
+
+	timet = time(NULL);
+	tmp = gmtime(&timet);
+
+	d->reg[MK48T08_CLKOFF + MK48TXX_ISEC] = BCD(tmp->tm_sec);
+	d->reg[MK48T08_CLKOFF + MK48TXX_IMIN] = BCD(tmp->tm_min);
+	d->reg[MK48T08_CLKOFF + MK48TXX_IHOUR] = BCD(tmp->tm_hour);
+	d->reg[MK48T08_CLKOFF + MK48TXX_IWDAY] = tmp->tm_wday + 1;
+	d->reg[MK48T08_CLKOFF + MK48TXX_IDAY] = BCD(tmp->tm_mday);
+	d->reg[MK48T08_CLKOFF + MK48TXX_IMON] = BCD(tmp->tm_mon + 1);
+	d->reg[MK48T08_CLKOFF + MK48TXX_IYEAR] = BCD(tmp->tm_year % 100);
+}
+
+
+DEVICE_ACCESS(mk48txx)
+{
+	struct mk48txx_data *d = (struct mk48txx_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (writeflag == MEM_READ)
+		odata = d->reg[relative_addr];
+
+	if (relative_addr < MK48T08_CLKOFF ||
+	    relative_addr >= MK48T08_CLKOFF + MK48TXX_ISEC) {
+		/*  Reads and writes to the RAM part of the mk48txx, or
+		    the clock registers, are OK:  */
+		if (writeflag == MEM_WRITE)
+			d->reg[relative_addr] = idata;
+		goto ret;
+	}
+
+	switch (relative_addr) {
+
+	case MK48T08_CLKOFF + MK48TXX_ICSR:
+		if (writeflag == MEM_WRITE) {
+			if ((idata & MK48TXX_CSR_READ) &&
+			    !(d->reg[relative_addr] & MK48TXX_CSR_READ)) {
+				/*  Switching the read bit from 0 to 1 causes
+				    registers to be "froozen". In the emulator,
+				    simply updating them with data from the
+				    host should be good enough.  */
+				mk48txx_update_regs(d);
+			}
+			d->reg[relative_addr] = idata;
+		}
+		break;
+
+	default:if (writeflag == MEM_READ)
+			fatal("[ mk48txx: unimplemented READ from offset 0x%x ]"
+			    "\n", (int)relative_addr);
+		else
+			fatal("[ mk48txx: unimplemented WRITE to offset 0x%x: "
+			    "0x%x ]\n", (int)relative_addr, (int)idata);
+		exit(1);
+	}
+
+ret:
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(mk48txx)
+{
+	struct mk48txx_data *d;
+
+	CHECK_ALLOCATION(d = (struct mk48txx_data *) malloc(sizeof(struct mk48txx_data)));
+	memset(d, 0, sizeof(struct mk48txx_data));
+
+	mk48txx_update_regs(d);
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, MK48TXX_LEN, dev_mk48txx_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_mk48txx.cc gxemul-0.7.0+dfsg/src/devices/dev_mk48txx.cc
--- gxemul-0.6.2/src/devices/dev_mk48txx.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_mk48txx.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,144 +0,0 @@
-/*
- *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Mostek MK48Txx Real Time Clock
- *
- *  TODO:
- *	Only the MK48T08 is implemented so far.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/mk48txxreg.h"
-
-
-#define	MK48TXX_LEN		MK48T08_CLKSZ
-
-#define	BCD(x)	((((x) / 10) << 4) + ((x) % 10))
-
-struct mk48txx_data {
-	uint8_t		reg[MK48TXX_LEN];
-};
-
-
-void mk48txx_update_regs(struct mk48txx_data *d)
-{
-	struct tm *tmp;
-	time_t timet;
-
-	timet = time(NULL);
-	tmp = gmtime(&timet);
-
-	d->reg[MK48T08_CLKOFF + MK48TXX_ISEC] = BCD(tmp->tm_sec);
-	d->reg[MK48T08_CLKOFF + MK48TXX_IMIN] = BCD(tmp->tm_min);
-	d->reg[MK48T08_CLKOFF + MK48TXX_IHOUR] = BCD(tmp->tm_hour);
-	d->reg[MK48T08_CLKOFF + MK48TXX_IWDAY] = tmp->tm_wday + 1;
-	d->reg[MK48T08_CLKOFF + MK48TXX_IDAY] = BCD(tmp->tm_mday);
-	d->reg[MK48T08_CLKOFF + MK48TXX_IMON] = BCD(tmp->tm_mon + 1);
-	d->reg[MK48T08_CLKOFF + MK48TXX_IYEAR] = BCD(tmp->tm_year % 100);
-}
-
-
-DEVICE_ACCESS(mk48txx)
-{
-	struct mk48txx_data *d = (struct mk48txx_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (writeflag == MEM_READ)
-		odata = d->reg[relative_addr];
-
-	if (relative_addr < MK48T08_CLKOFF ||
-	    relative_addr >= MK48T08_CLKOFF + MK48TXX_ISEC) {
-		/*  Reads and writes to the RAM part of the mk48txx, or
-		    the clock registers, are OK:  */
-		if (writeflag == MEM_WRITE)
-			d->reg[relative_addr] = idata;
-		goto ret;
-	}
-
-	switch (relative_addr) {
-
-	case MK48T08_CLKOFF + MK48TXX_ICSR:
-		if (writeflag == MEM_WRITE) {
-			if ((idata & MK48TXX_CSR_READ) &&
-			    !(d->reg[relative_addr] & MK48TXX_CSR_READ)) {
-				/*  Switching the read bit from 0 to 1 causes
-				    registers to be "froozen". In the emulator,
-				    simply updating them with data from the
-				    host should be good enough.  */
-				mk48txx_update_regs(d);
-			}
-			d->reg[relative_addr] = idata;
-		}
-		break;
-
-	default:if (writeflag == MEM_READ)
-			fatal("[ mk48txx: unimplemented READ from offset 0x%x ]"
-			    "\n", (int)relative_addr);
-		else
-			fatal("[ mk48txx: unimplemented WRITE to offset 0x%x: "
-			    "0x%x ]\n", (int)relative_addr, (int)idata);
-		exit(1);
-	}
-
-ret:
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(mk48txx)
-{
-	struct mk48txx_data *d;
-
-	CHECK_ALLOCATION(d = (struct mk48txx_data *) malloc(sizeof(struct mk48txx_data)));
-	memset(d, 0, sizeof(struct mk48txx_data));
-
-	mk48txx_update_regs(d);
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, MK48TXX_LEN, dev_mk48txx_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_mp.c gxemul-0.7.0+dfsg/src/devices/dev_mp.c
--- gxemul-0.6.2/src/devices/dev_mp.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_mp.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,287 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Generic Multi-processor controller for the test machines
+ *
+ *  This is a fake multiprocessor (MP) device. It can be useful for
+ *  theoretical experiments, but probably bares no resemblance to any
+ *  multiprocessor controller used in any real machine.
+ *
+ *  NOTE: The devinit irq string should be the part _after_ "cpu[%i].".
+ *        For MIPS, it will be MIPS_IPI_INT.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "interrupt.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "testmachine/dev_mp.h"
+
+
+struct mp_data {
+	struct cpu	**cpus;
+	uint64_t	startup_addr;
+	uint64_t	stack_addr;
+	uint64_t	pause_addr;
+
+	/*  Each CPU has an array of pending ipis.  */
+	int		*n_pending_ipis;
+	int		**ipi;
+
+	/*  Connections to all CPUs' IPI pins:  */
+	struct interrupt *ipi_irq;
+};
+
+
+DEVICE_ACCESS(mp)
+{
+	struct mp_data *d = (struct mp_data *) extra;
+	int i, which_cpu;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+	        idata = memory_readmax64(cpu, data, len);
+
+	/*
+	 *  NOTE: It is up to the user of this device to read or write
+	 *  correct addresses. (A write to NCPUS is pretty useless,
+	 *  for example.)
+	 */
+
+	switch (relative_addr) {
+
+	case DEV_MP_WHOAMI:
+		odata = cpu->cpu_id;
+		break;
+
+	case DEV_MP_NCPUS:
+		odata = cpu->machine->ncpus;
+		break;
+
+	case DEV_MP_STARTUPCPU:
+		which_cpu = idata;
+		d->cpus[which_cpu]->pc = d->startup_addr;
+		switch (cpu->cpu_family->arch) {
+		case ARCH_MIPS:
+			d->cpus[which_cpu]->cd.mips.gpr[MIPS_GPR_SP] =
+			    d->stack_addr;
+			break;
+		case ARCH_PPC:
+			d->cpus[which_cpu]->cd.ppc.gpr[1] = d->stack_addr;
+			break;
+		default:
+			fatal("dev_mp(): DEV_MP_STARTUPCPU: not for this"
+			    " arch yet!\n");
+			exit(1);
+		}
+		d->cpus[which_cpu]->running = true;
+		/*  debug("[ dev_mp: starting up cpu%i at 0x%llx ]\n", 
+		    which_cpu, (long long)d->startup_addr);  */
+		break;
+
+	case DEV_MP_STARTUPADDR:
+		if (len==4 && (idata >> 32) == 0 && (idata & 0x80000000ULL))
+			idata |= 0xffffffff00000000ULL;
+		d->startup_addr = idata;
+		break;
+
+	case DEV_MP_PAUSE_ADDR:
+		d->pause_addr = idata;
+		break;
+
+	case DEV_MP_PAUSE_CPU:
+		/*  Pause all cpus except a specific CPU:  */
+		which_cpu = idata;
+
+		for (i=0; i<cpu->machine->ncpus; i++)
+			if (i != which_cpu)
+				d->cpus[i]->running = false;
+		break;
+
+	case DEV_MP_UNPAUSE_CPU:
+		/*  Unpause a specific CPU:  */
+		which_cpu = idata;
+
+		if (which_cpu >= 0 && which_cpu <cpu->machine->ncpus)
+			d->cpus[which_cpu]->running = true;
+		break;
+
+	case DEV_MP_STARTUPSTACK:
+		if (len == 4 && (idata >> 32) == 0 && (idata & 0x80000000ULL))
+			idata |= 0xffffffff00000000ULL;
+		d->stack_addr = idata;
+		break;
+
+	case DEV_MP_HARDWARE_RANDOM:
+		/*
+		 *  Return (up to) 64 bits of "hardware random":
+		 *
+		 *  NOTE: Remember that random() is (usually) 31 bits of
+		 *        random data, _NOT_ 32, hence this construction.
+		 */
+		odata = random();
+		odata = (odata << 31) ^ random();
+		odata = (odata << 31) ^ random();
+		break;
+
+	case DEV_MP_MEMORY:
+		/*
+		 *  Return the number of bytes of memory in the system.
+		 *
+		 *  (It is assumed to be located at physical address 0.
+		 *  It is actually located at machine->memory_offset_in_mb
+		 *  but that is only used for SGI emulation so far.)
+		 */
+		odata = cpu->machine->physical_ram_in_mb * 1048576ULL;
+		break;
+
+	case DEV_MP_IPI_ONE:
+	case DEV_MP_IPI_MANY:
+		/*
+		 *  idata should be of the form:
+		 *
+		 *		(IPI_nr << 16) | cpu_id
+		 *
+		 *  This will send an Inter-processor interrupt to a specific
+		 *  CPU. (DEV_MP_IPI_MANY sends to all _except_ the specific
+		 *  CPU.)
+		 *
+		 *  Sending an IPI means adding the IPI last in the list of
+		 *  pending IPIs, and asserting the IPI "pin".
+		 */
+		which_cpu = (idata & 0xffff);
+		for (i=0; i<cpu->machine->ncpus; i++) {
+			int send_it = 0;
+			if (relative_addr == DEV_MP_IPI_ONE && i == which_cpu)
+				send_it = 1;
+			if (relative_addr == DEV_MP_IPI_MANY && i != which_cpu)
+				send_it = 1;
+			if (send_it) {
+				d->n_pending_ipis[i] ++;
+				CHECK_ALLOCATION(d->ipi[i] = (int *) realloc(d->ipi[i],
+				    d->n_pending_ipis[i] * sizeof(int)));
+
+				/*  Add the IPI last in the array:  */
+				d->ipi[i][d->n_pending_ipis[i] - 1] =
+				    idata >> 16;
+
+				INTERRUPT_ASSERT(d->ipi_irq[i]);
+			}
+		}
+		break;
+
+	case DEV_MP_IPI_READ:
+		/*
+		 *  If the current CPU has any IPIs pending, accessing this
+		 *  address reads the IPI value. (Writing to this address
+		 *  discards _all_ pending IPIs.)  If there is no pending
+		 *  IPI, then 0 is returned. Usage of the value 0 for real
+		 *  IPIs should thus be avoided.
+		 */
+		if (writeflag == MEM_WRITE) {
+			d->n_pending_ipis[cpu->cpu_id] = 0;
+		}
+		odata = 0;
+		if (d->n_pending_ipis[cpu->cpu_id] > 0) {
+			odata = d->ipi[cpu->cpu_id][0];
+			if (d->n_pending_ipis[cpu->cpu_id]-- > 1)
+				memmove(&d->ipi[cpu->cpu_id][0],
+				    &d->ipi[cpu->cpu_id][1],
+				    d->n_pending_ipis[cpu->cpu_id]);
+		}
+
+		/*  Deassert the interrupt, if there are no pending IPIs:  */
+		if (d->n_pending_ipis[cpu->cpu_id] == 0)
+			INTERRUPT_DEASSERT(d->ipi_irq[cpu->cpu_id]);
+		break;
+
+	case DEV_MP_NCYCLES:
+		/*
+		 *  Return _approximately_ the number of cycles executed
+		 *  on this CPU.
+		 *
+		 *  (This value is not updated for each instruction.)
+		 */
+		odata = cpu->ninstrs;
+		break;
+
+	default:
+		fatal("[ dev_mp: unimplemented relative addr 0x%x ]\n",
+		    relative_addr);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(mp)
+{
+	struct mp_data *d;
+	int n, i;
+
+	CHECK_ALLOCATION(d = (struct mp_data *) malloc(sizeof(struct mp_data)));
+	memset(d, 0, sizeof(struct mp_data));
+
+	d->cpus = devinit->machine->cpus;
+	d->startup_addr = INITIAL_PC;
+	d->stack_addr = INITIAL_STACK_POINTER;
+
+	n = devinit->machine->ncpus;
+
+	/*  Connect to all CPUs' IPI pins:  */
+	CHECK_ALLOCATION(d->ipi_irq = (struct interrupt *)
+	    malloc(n * sizeof(struct interrupt)));
+
+	for (i=0; i<n; i++) {
+		char tmpstr[200];
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%s",
+		    devinit->machine->path, i, devinit->interrupt_path);
+		INTERRUPT_CONNECT(tmpstr, d->ipi_irq[i]);
+	}
+
+	CHECK_ALLOCATION(d->n_pending_ipis = (int *) malloc(n * sizeof(int)));
+	memset(d->n_pending_ipis, 0, sizeof(int) * n);
+
+	CHECK_ALLOCATION(d->ipi = (int **) malloc(n * sizeof(int *)));
+	memset(d->ipi, 0, sizeof(int *) * n);
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_MP_LENGTH, dev_mp_access, d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_mp.cc gxemul-0.7.0+dfsg/src/devices/dev_mp.cc
--- gxemul-0.6.2/src/devices/dev_mp.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_mp.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,290 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Generic Multi-processor controller for the test machines
- *
- *  This is a fake multiprocessor (MP) device. It can be useful for
- *  theoretical experiments, but probably bares no resemblance to any
- *  multiprocessor controller used in any real machine.
- *
- *  NOTE: The devinit irq string should be the part _after_ "cpu[%i].".
- *        For MIPS, it will be MIPS_IPI_INT.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "interrupt.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "testmachine/dev_mp.h"
-
-
-struct mp_data {
-	struct cpu	**cpus;
-	uint64_t	startup_addr;
-	uint64_t	stack_addr;
-	uint64_t	pause_addr;
-
-	/*  Each CPU has an array of pending ipis.  */
-	int		*n_pending_ipis;
-	int		**ipi;
-
-	/*  Connections to all CPUs' IPI pins:  */
-	struct interrupt *ipi_irq;
-};
-
-
-extern int single_step;
-
-
-DEVICE_ACCESS(mp)
-{
-	struct mp_data *d = (struct mp_data *) extra;
-	int i, which_cpu;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-	        idata = memory_readmax64(cpu, data, len);
-
-	/*
-	 *  NOTE: It is up to the user of this device to read or write
-	 *  correct addresses. (A write to NCPUS is pretty useless,
-	 *  for example.)
-	 */
-
-	switch (relative_addr) {
-
-	case DEV_MP_WHOAMI:
-		odata = cpu->cpu_id;
-		break;
-
-	case DEV_MP_NCPUS:
-		odata = cpu->machine->ncpus;
-		break;
-
-	case DEV_MP_STARTUPCPU:
-		which_cpu = idata;
-		d->cpus[which_cpu]->pc = d->startup_addr;
-		switch (cpu->machine->arch) {
-		case ARCH_MIPS:
-			d->cpus[which_cpu]->cd.mips.gpr[MIPS_GPR_SP] =
-			    d->stack_addr;
-			break;
-		case ARCH_PPC:
-			d->cpus[which_cpu]->cd.ppc.gpr[1] = d->stack_addr;
-			break;
-		default:
-			fatal("dev_mp(): DEV_MP_STARTUPCPU: not for this"
-			    " arch yet!\n");
-			exit(1);
-		}
-		d->cpus[which_cpu]->running = 1;
-		/*  debug("[ dev_mp: starting up cpu%i at 0x%llx ]\n", 
-		    which_cpu, (long long)d->startup_addr);  */
-		break;
-
-	case DEV_MP_STARTUPADDR:
-		if (len==4 && (idata >> 32) == 0 && (idata & 0x80000000ULL))
-			idata |= 0xffffffff00000000ULL;
-		d->startup_addr = idata;
-		break;
-
-	case DEV_MP_PAUSE_ADDR:
-		d->pause_addr = idata;
-		break;
-
-	case DEV_MP_PAUSE_CPU:
-		/*  Pause all cpus except a specific CPU:  */
-		which_cpu = idata;
-
-		for (i=0; i<cpu->machine->ncpus; i++)
-			if (i != which_cpu)
-				d->cpus[i]->running = 0;
-		break;
-
-	case DEV_MP_UNPAUSE_CPU:
-		/*  Unpause a specific CPU:  */
-		which_cpu = idata;
-
-		if (which_cpu >= 0 && which_cpu <cpu->machine->ncpus)
-			d->cpus[which_cpu]->running = 1;
-		break;
-
-	case DEV_MP_STARTUPSTACK:
-		if (len == 4 && (idata >> 32) == 0 && (idata & 0x80000000ULL))
-			idata |= 0xffffffff00000000ULL;
-		d->stack_addr = idata;
-		break;
-
-	case DEV_MP_HARDWARE_RANDOM:
-		/*
-		 *  Return (up to) 64 bits of "hardware random":
-		 *
-		 *  NOTE: Remember that random() is (usually) 31 bits of
-		 *        random data, _NOT_ 32, hence this construction.
-		 */
-		odata = random();
-		odata = (odata << 31) ^ random();
-		odata = (odata << 31) ^ random();
-		break;
-
-	case DEV_MP_MEMORY:
-		/*
-		 *  Return the number of bytes of memory in the system.
-		 *
-		 *  (It is assumed to be located at physical address 0.
-		 *  It is actually located at machine->memory_offset_in_mb
-		 *  but that is only used for SGI emulation so far.)
-		 */
-		odata = cpu->machine->physical_ram_in_mb * 1048576ULL;
-		break;
-
-	case DEV_MP_IPI_ONE:
-	case DEV_MP_IPI_MANY:
-		/*
-		 *  idata should be of the form:
-		 *
-		 *		(IPI_nr << 16) | cpu_id
-		 *
-		 *  This will send an Inter-processor interrupt to a specific
-		 *  CPU. (DEV_MP_IPI_MANY sends to all _except_ the specific
-		 *  CPU.)
-		 *
-		 *  Sending an IPI means adding the IPI last in the list of
-		 *  pending IPIs, and asserting the IPI "pin".
-		 */
-		which_cpu = (idata & 0xffff);
-		for (i=0; i<cpu->machine->ncpus; i++) {
-			int send_it = 0;
-			if (relative_addr == DEV_MP_IPI_ONE && i == which_cpu)
-				send_it = 1;
-			if (relative_addr == DEV_MP_IPI_MANY && i != which_cpu)
-				send_it = 1;
-			if (send_it) {
-				d->n_pending_ipis[i] ++;
-				CHECK_ALLOCATION(d->ipi[i] = (int *) realloc(d->ipi[i],
-				    d->n_pending_ipis[i] * sizeof(int)));
-
-				/*  Add the IPI last in the array:  */
-				d->ipi[i][d->n_pending_ipis[i] - 1] =
-				    idata >> 16;
-
-				INTERRUPT_ASSERT(d->ipi_irq[i]);
-			}
-		}
-		break;
-
-	case DEV_MP_IPI_READ:
-		/*
-		 *  If the current CPU has any IPIs pending, accessing this
-		 *  address reads the IPI value. (Writing to this address
-		 *  discards _all_ pending IPIs.)  If there is no pending
-		 *  IPI, then 0 is returned. Usage of the value 0 for real
-		 *  IPIs should thus be avoided.
-		 */
-		if (writeflag == MEM_WRITE) {
-			d->n_pending_ipis[cpu->cpu_id] = 0;
-		}
-		odata = 0;
-		if (d->n_pending_ipis[cpu->cpu_id] > 0) {
-			odata = d->ipi[cpu->cpu_id][0];
-			if (d->n_pending_ipis[cpu->cpu_id]-- > 1)
-				memmove(&d->ipi[cpu->cpu_id][0],
-				    &d->ipi[cpu->cpu_id][1],
-				    d->n_pending_ipis[cpu->cpu_id]);
-		}
-
-		/*  Deassert the interrupt, if there are no pending IPIs:  */
-		if (d->n_pending_ipis[cpu->cpu_id] == 0)
-			INTERRUPT_DEASSERT(d->ipi_irq[cpu->cpu_id]);
-		break;
-
-	case DEV_MP_NCYCLES:
-		/*
-		 *  Return _approximately_ the number of cycles executed
-		 *  on this CPU.
-		 *
-		 *  (This value is not updated for each instruction.)
-		 */
-		odata = cpu->ninstrs;
-		break;
-
-	default:
-		fatal("[ dev_mp: unimplemented relative addr 0x%x ]\n",
-		    relative_addr);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(mp)
-{
-	struct mp_data *d;
-	int n, i;
-
-	CHECK_ALLOCATION(d = (struct mp_data *) malloc(sizeof(struct mp_data)));
-	memset(d, 0, sizeof(struct mp_data));
-
-	d->cpus = devinit->machine->cpus;
-	d->startup_addr = INITIAL_PC;
-	d->stack_addr = INITIAL_STACK_POINTER;
-
-	n = devinit->machine->ncpus;
-
-	/*  Connect to all CPUs' IPI pins:  */
-	CHECK_ALLOCATION(d->ipi_irq = (struct interrupt *)
-	    malloc(n * sizeof(struct interrupt)));
-
-	for (i=0; i<n; i++) {
-		char tmpstr[200];
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%s",
-		    devinit->machine->path, i, devinit->interrupt_path);
-		INTERRUPT_CONNECT(tmpstr, d->ipi_irq[i]);
-	}
-
-	CHECK_ALLOCATION(d->n_pending_ipis = (int *) malloc(n * sizeof(int)));
-	memset(d->n_pending_ipis, 0, sizeof(int) * n);
-
-	CHECK_ALLOCATION(d->ipi = (int **) malloc(n * sizeof(int *)));
-	memset(d->ipi, 0, sizeof(int *) * n);
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_MP_LENGTH, dev_mp_access, d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_mvme187.c gxemul-0.7.0+dfsg/src/devices/dev_mvme187.c
--- gxemul-0.6.2/src/devices/dev_mvme187.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_mvme187.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,161 @@
+/*
+ *  Copyright (C) 2007-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: MVME187-specific devices and control registers
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/mvme187.h"
+#include "thirdparty/mvme_memcreg.h"
+#include "thirdparty/m8820x.h"
+
+
+struct mvme187_data {
+	struct memcreg		memcreg;
+};
+
+
+DEVICE_ACCESS(mvme187_memc)
+{
+	uint64_t idata = 0, odata = 0;
+	struct mvme187_data *d = (struct mvme187_data *) extra;
+
+	// TODO: not used yet
+	int controller = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (relative_addr & 0x100) {
+		controller = 1;
+		relative_addr &= ~0x100;
+	}
+
+	odata = ((uint8_t*)&d->memcreg)[relative_addr];
+
+	switch (relative_addr) {
+
+	case 0x00:	/* chipid */
+	case 0x04:	/* chiprev */
+		break;
+
+	case 0x08:	/*  memconf  */
+		if (writeflag == MEM_WRITE) {
+			fatal("mvme187_memc: Write to relative_addr %i (controller %i) not yet"
+			    " implemented!\n", (int)relative_addr, controller);
+			exit(1);
+		}
+		break;
+
+	default:fatal("[ mvme187_memc: unimplemented %s offset 0x%x",
+		    writeflag == MEM_WRITE? "write to" : "read from",
+		    (int) relative_addr);
+		if (writeflag == MEM_WRITE)
+			fatal(": 0x%x", (int)idata);
+		fatal(" ]\n");
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(mvme187)
+{
+	struct mvme187_data *d;
+	char tmpstr[300];
+	struct m8820x_cmmu *cmmu;
+	int size_per_memc, r;
+
+	CHECK_ALLOCATION(d = (struct mvme187_data *) malloc(sizeof(struct mvme187_data)));
+	memset(d, 0, sizeof(struct mvme187_data));
+
+
+	/*
+	 *  Two memory controllers per MVME187 machine:
+	 */
+
+	size_per_memc = devinit->machine->physical_ram_in_mb / 2 * 1048576;
+	for (r=0; ; r++) {
+		if (MEMC_MEMCONF_RTOB(r) > size_per_memc) {
+			r--;
+			break;
+		}
+	}
+
+	d->memcreg.memc_chipid = MEMC_CHIPID;
+	d->memcreg.memc_chiprev = 1;
+	d->memcreg.memc_memconf = r;
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    MVME187_MEM_CTLR, 0x200, dev_mvme187_memc_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+
+	/*  Instruction CMMU:  */
+	CHECK_ALLOCATION(cmmu = (struct m8820x_cmmu *) malloc(sizeof(struct m8820x_cmmu)));
+	memset(cmmu, 0, sizeof(struct m8820x_cmmu));
+
+	devinit->machine->cpus[devinit->machine->bootstrap_cpu]->
+	    cd.m88k.cmmu[0] = cmmu;
+	/*  This is a 88200, revision 9:  */
+	cmmu->reg[CMMU_IDR] = (M88200_ID << 21) | (9 << 16);
+	snprintf(tmpstr, sizeof(tmpstr),
+	    "m8820x addr=0x%x addr2=0", MVME187_SBC_CMMU_I);
+	device_add(devinit->machine, tmpstr);
+
+	/*  ... and data CMMU:  */
+	CHECK_ALLOCATION(cmmu = (struct m8820x_cmmu *) malloc(sizeof(struct m8820x_cmmu)));
+	memset(cmmu, 0, sizeof(struct m8820x_cmmu));
+
+	devinit->machine->cpus[devinit->machine->bootstrap_cpu]->
+	    cd.m88k.cmmu[1] = cmmu;
+	/*  This is also a 88200, revision 9:  */
+	cmmu->reg[CMMU_IDR] = (M88200_ID << 21) | (9 << 16);
+	cmmu->batc[8] = BATC8;
+	cmmu->batc[9] = BATC9;
+	snprintf(tmpstr, sizeof(tmpstr),
+	    "m8820x addr=0x%x addr2=1", MVME187_SBC_CMMU_D);
+	device_add(devinit->machine, tmpstr);
+
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_mvme187.cc gxemul-0.7.0+dfsg/src/devices/dev_mvme187.cc
--- gxemul-0.6.2/src/devices/dev_mvme187.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_mvme187.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,159 +0,0 @@
-/*
- *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: MVME187-specific devices and control registers
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/mvme187.h"
-#include "thirdparty/mvme_memcreg.h"
-#include "thirdparty/m8820x.h"
-
-
-struct mvme187_data {
-	struct memcreg		memcreg;
-};
-
-
-DEVICE_ACCESS(mvme187_memc)
-{
-	uint64_t idata = 0, odata = 0;
-	struct mvme187_data *d = (struct mvme187_data *) extra;
-	int controller = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (relative_addr & 0x100) {
-		controller = 1;
-		relative_addr &= ~0x100;
-	}
-
-	odata = ((uint8_t*)&d->memcreg)[relative_addr];
-
-	switch (relative_addr) {
-
-	case 0x00:	/* chipid */
-	case 0x04:	/* chiprev */
-		break;
-
-	case 0x08:	/*  memconf  */
-		if (writeflag == MEM_WRITE) {
-			fatal("mvme187_memc: Write to relative_addr %i not yet"
-			    " implemented!\n");
-			exit(1);
-		}
-		break;
-
-	default:fatal("[ mvme187_memc: unimplemented %s offset 0x%x",
-		    writeflag == MEM_WRITE? "write to" : "read from",
-		    (int) relative_addr);
-		if (writeflag == MEM_WRITE)
-			fatal(": 0x%x", (int)idata);
-		fatal(" ]\n");
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(mvme187)
-{
-	struct mvme187_data *d;
-	char tmpstr[300];
-	struct m8820x_cmmu *cmmu;
-	int size_per_memc, r;
-
-	CHECK_ALLOCATION(d = (struct mvme187_data *) malloc(sizeof(struct mvme187_data)));
-	memset(d, 0, sizeof(struct mvme187_data));
-
-
-	/*
-	 *  Two memory controllers per MVME187 machine:
-	 */
-
-	size_per_memc = devinit->machine->physical_ram_in_mb / 2 * 1048576;
-	for (r=0; ; r++) {
-		if (MEMC_MEMCONF_RTOB(r) > size_per_memc) {
-			r--;
-			break;
-		}
-	}
-
-	d->memcreg.memc_chipid = MEMC_CHIPID;
-	d->memcreg.memc_chiprev = 1;
-	d->memcreg.memc_memconf = r;
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    MVME187_MEM_CTLR, 0x200, dev_mvme187_memc_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-
-	/*  Instruction CMMU:  */
-	CHECK_ALLOCATION(cmmu = (struct m8820x_cmmu *) malloc(sizeof(struct m8820x_cmmu)));
-	memset(cmmu, 0, sizeof(struct m8820x_cmmu));
-
-	devinit->machine->cpus[devinit->machine->bootstrap_cpu]->
-	    cd.m88k.cmmu[0] = cmmu;
-	/*  This is a 88200, revision 9:  */
-	cmmu->reg[CMMU_IDR] = (M88200_ID << 21) | (9 << 16);
-	snprintf(tmpstr, sizeof(tmpstr),
-	    "m8820x addr=0x%x addr2=0", MVME187_SBC_CMMU_I);
-	device_add(devinit->machine, tmpstr);
-
-	/*  ... and data CMMU:  */
-	CHECK_ALLOCATION(cmmu = (struct m8820x_cmmu *) malloc(sizeof(struct m8820x_cmmu)));
-	memset(cmmu, 0, sizeof(struct m8820x_cmmu));
-
-	devinit->machine->cpus[devinit->machine->bootstrap_cpu]->
-	    cd.m88k.cmmu[1] = cmmu;
-	/*  This is also a 88200, revision 9:  */
-	cmmu->reg[CMMU_IDR] = (M88200_ID << 21) | (9 << 16);
-	cmmu->batc[8] = BATC8;
-	cmmu->batc[9] = BATC9;
-	snprintf(tmpstr, sizeof(tmpstr),
-	    "m8820x addr=0x%x addr2=1", MVME187_SBC_CMMU_D);
-	device_add(devinit->machine, tmpstr);
-
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_ns16550.c gxemul-0.7.0+dfsg/src/devices/dev_ns16550.c
--- gxemul-0.6.2/src/devices/dev_ns16550.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ns16550.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,367 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: NS16550 serial controller
+ *
+ *  TODO: Implement the FIFO.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/comreg.h"
+
+
+/*  #define debug fatal  */
+
+#define	TICK_SHIFT		14
+#define	DEV_NS16550_LENGTH	8
+
+struct ns_data {
+	int		addrmult;
+	int		in_use;
+	const char	*name;
+	int		console_handle;
+	int		enable_fifo;
+
+	struct interrupt irq;
+
+	unsigned char	reg[DEV_NS16550_LENGTH];
+	unsigned char	fcr;		/*  FIFO control register  */
+	int		int_asserted;
+	int		dlab;		/*  Divisor Latch Access bit  */
+	int		divisor;
+
+	int		databits;
+	char		parity;
+	const char	*stopbits;
+};
+
+
+DEVICE_TICK(ns16550)
+{
+	/*
+	 *  This function is called at regular intervals. An interrupt is
+	 *  asserted if there is a character available for reading, or if the
+	 *  transmitter slot is empty (i.e. the ns16550 is ready to transmit).
+	 */
+	struct ns_data *d = (struct ns_data *) extra;
+
+	d->reg[com_iir] &= ~IIR_RXRDY;
+	if (console_charavail(d->console_handle))
+		d->reg[com_iir] |= IIR_RXRDY;
+
+	/*
+	 *  If interrupts are enabled, and interrupts are pending, then
+	 *  cause a CPU interrupt.
+ 	 */
+
+	if (((d->reg[com_ier] & IER_ETXRDY) && (d->reg[com_iir] & IIR_TXRDY)) ||
+	    ((d->reg[com_ier] & IER_ERXRDY) && (d->reg[com_iir] & IIR_RXRDY))) {
+		d->reg[com_iir] &= ~IIR_NOPEND;
+		if (d->reg[com_mcr] & MCR_IENABLE) {
+			INTERRUPT_ASSERT(d->irq);
+			d->int_asserted = 1;
+		}
+	} else {
+		d->reg[com_iir] |= IIR_NOPEND;
+		if (d->int_asserted)
+			INTERRUPT_DEASSERT(d->irq);
+		d->int_asserted = 0;
+	}
+}
+
+
+DEVICE_ACCESS(ns16550)
+{
+	uint64_t idata = 0, odata=0;
+	size_t i;
+	struct ns_data *d = (struct ns_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+#if 0
+	/*  The NS16550 should be accessed using byte read/writes:  */
+	if (len != 1)
+		fatal("[ ns16550 (%s): len=%i, idata=0x%16llx! ]\n",
+		    d->name, len, (long long)idata);
+#endif
+
+	/*
+	 *  Always ready to transmit:
+	 */
+	d->reg[com_lsr] |= LSR_TXRDY | LSR_TSRE;
+	d->reg[com_msr] |= MSR_DCD | MSR_DSR | MSR_CTS;
+
+	d->reg[com_iir] &= ~0xf0;
+	if (d->enable_fifo)
+		d->reg[com_iir] |= ((d->fcr << 5) & 0xc0);
+
+	d->reg[com_lsr] &= ~LSR_RXRDY;
+	if (console_charavail(d->console_handle))
+		d->reg[com_lsr] |= LSR_RXRDY;
+
+	relative_addr /= d->addrmult;
+
+	if (relative_addr >= DEV_NS16550_LENGTH) {
+		fatal("[ ns16550 (%s): outside register space? relative_addr="
+		    "0x%llx. bad addrmult? bad device length? ]\n", d->name,
+		    (long long)relative_addr);
+		return 0;
+	}
+
+	switch (relative_addr) {
+
+	case com_data:	/*  data AND low byte of the divisor  */
+		/*  Read/write of the Divisor value:  */
+		if (d->dlab) {
+			/*  Write or read the low byte of the divisor:  */
+			if (writeflag == MEM_WRITE)
+				d->divisor = (d->divisor & 0xff00) | idata;
+			else
+				odata = d->divisor & 0xff;
+			break;
+		}
+
+		/*  Read/write of data:  */
+		if (writeflag == MEM_WRITE) {
+			if (d->reg[com_mcr] & MCR_LOOPBACK)
+				console_makeavail(d->console_handle, idata);
+			else
+				console_putchar(d->console_handle, idata);
+			d->reg[com_iir] |= IIR_TXRDY;
+		} else {
+			int x = console_readchar(d->console_handle);
+			odata = x < 0? 0 : x;
+		}
+		dev_ns16550_tick(cpu, d);
+		break;
+
+	case com_ier:	/*  interrupt enable AND high byte of the divisor  */
+		/*  Read/write of the Divisor value:  */
+		if (d->dlab) {
+			if (writeflag == MEM_WRITE) {
+				/*  Set the high byte of the divisor:  */
+				d->divisor = (d->divisor & 0xff) | (idata << 8);
+				debug("[ ns16550 (%s): speed set to %i bps ]\n",
+				    d->name, (int)(115200 / d->divisor));
+			} else
+				odata = d->divisor >> 8;
+			break;
+		}
+
+		/*  IER:  */
+		if (writeflag == MEM_WRITE) {
+			/*  This is to supress Linux' behaviour  */
+			if (idata != 0)
+				debug("[ ns16550 (%s): write to ier: 0x%02x ]"
+				    "\n", d->name, (int)idata);
+
+			/*  Needed for NetBSD 2.0.x, but not 1.6.2?  */
+			if (!(d->reg[com_ier] & IER_ETXRDY)
+			    && (idata & IER_ETXRDY))
+				d->reg[com_iir] |= IIR_TXRDY;
+
+			d->reg[com_ier] = idata;
+			dev_ns16550_tick(cpu, d);
+		} else
+			odata = d->reg[com_ier];
+		break;
+
+	case com_iir:	/*  interrupt identification (r), fifo control (w)  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ ns16550 (%s): write to fifo control: 0x%02x ]"
+			    "\n", d->name, (int)idata);
+			d->fcr = idata;
+		} else {
+			odata = d->reg[com_iir];
+			if (d->reg[com_iir] & IIR_TXRDY)
+				d->reg[com_iir] &= ~IIR_TXRDY;
+			debug("[ ns16550 (%s): read from iir: 0x%02x ]\n",
+			    d->name, (int)odata);
+			dev_ns16550_tick(cpu, d);
+		}
+		break;
+
+	case com_lsr:
+		if (writeflag == MEM_WRITE) {
+			debug("[ ns16550 (%s): write to lsr: 0x%02x ]\n",
+			    d->name, (int)idata);
+			d->reg[com_lsr] = idata;
+		} else {
+			odata = d->reg[com_lsr];
+			/*  debug("[ ns16550 (%s): read from lsr: 0x%02x ]\n",
+			    d->name, (int)odata);  */
+		}
+		break;
+
+	case com_msr:
+		if (writeflag == MEM_WRITE) {
+			debug("[ ns16550 (%s): write to msr: 0x%02x ]\n",
+			    d->name, (int)idata);
+			d->reg[com_msr] = idata;
+		} else {
+			odata = d->reg[com_msr];
+			debug("[ ns16550 (%s): read from msr: 0x%02x ]\n",
+			    d->name, (int)odata);
+		}
+		break;
+
+	case com_lctl:
+		if (writeflag == MEM_WRITE) {
+			d->reg[com_lctl] = idata;
+			switch (idata & 0x7) {
+			case 0:	d->databits = 5; d->stopbits = "1"; break;
+			case 1:	d->databits = 6; d->stopbits = "1"; break;
+			case 2:	d->databits = 7; d->stopbits = "1"; break;
+			case 3:	d->databits = 8; d->stopbits = "1"; break;
+			case 4:	d->databits = 5; d->stopbits = "1.5"; break;
+			case 5:	d->databits = 6; d->stopbits = "2"; break;
+			case 6:	d->databits = 7; d->stopbits = "2"; break;
+			case 7:	d->databits = 8; d->stopbits = "2"; break;
+			}
+			switch ((idata & 0x38) / 0x8) {
+			case 0:	d->parity = 'N'; break;		/*  none  */
+			case 1:	d->parity = 'O'; break;		/*  odd  */
+			case 2:	d->parity = '?'; break;
+			case 3:	d->parity = 'E'; break;		/*  even  */
+			case 4:	d->parity = '?'; break;
+			case 5:	d->parity = 'Z'; break;		/*  zero  */
+			case 6:	d->parity = '?'; break;
+			case 7:	d->parity = 'o'; break;		/*  one  */
+			}
+
+			d->dlab = idata & 0x80? 1 : 0;
+
+			debug("[ ns16550 (%s): write to lctl: 0x%02x (%s%s"
+			    "setting mode %i%c%s) ]\n", d->name, (int)idata,
+			    d->dlab? "Divisor Latch access, " : "",
+			    idata&0x40? "sending BREAK, " : "",
+			    d->databits, d->parity, d->stopbits);
+		} else {
+			odata = d->reg[com_lctl];
+			debug("[ ns16550 (%s): read from lctl: 0x%02x ]\n",
+			    d->name, (int)odata);
+		}
+		break;
+
+	case com_mcr:
+		if (writeflag == MEM_WRITE) {
+			d->reg[com_mcr] = idata;
+			debug("[ ns16550 (%s): write to mcr: 0x%02x ]\n",
+			    d->name, (int)idata);
+			if (!(d->reg[com_iir] & IIR_TXRDY)
+			    && (idata & MCR_IENABLE))
+				d->reg[com_iir] |= IIR_TXRDY;
+			dev_ns16550_tick(cpu, d);
+		} else {
+			odata = d->reg[com_mcr];
+			debug("[ ns16550 (%s): read from mcr: 0x%02x ]\n",
+			    d->name, (int)odata);
+		}
+		break;
+
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ ns16550 (%s): read from reg %i ]\n",
+			    d->name, (int)relative_addr);
+			odata = d->reg[relative_addr];
+		} else {
+			debug("[ ns16550 (%s): write to reg %i:",
+			    d->name, (int)relative_addr);
+			for (i=0; i<len; i++)
+				debug(" %02x", data[i]);
+			debug(" ]\n");
+			d->reg[relative_addr] = idata;
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(ns16550)
+{
+	struct ns_data *d;
+	size_t nlen;
+	char *name;
+
+	CHECK_ALLOCATION(d = (struct ns_data *) malloc(sizeof(struct ns_data)));
+	memset(d, 0, sizeof(struct ns_data));
+
+	d->addrmult	= devinit->addr_mult;
+	d->in_use	= devinit->in_use;
+	d->enable_fifo	= 1;
+	d->dlab		= 0;
+	d->divisor	= 115200 / 9600;
+	d->databits	= 8;
+	d->parity	= 'N';
+	d->stopbits	= "1";
+	d->name		= devinit->name2 != NULL? devinit->name2 : "";
+	d->console_handle =
+	    console_start_slave(devinit->machine, devinit->name2 != NULL?
+	    devinit->name2 : devinit->name, d->in_use);
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	nlen = strlen(devinit->name) + 10;
+	if (devinit->name2 != NULL)
+		nlen += strlen(devinit->name2);
+	CHECK_ALLOCATION(name = (char *) malloc(nlen));
+	if (devinit->name2 != NULL && devinit->name2[0])
+		snprintf(name, nlen, "%s [%s]", devinit->name, devinit->name2);
+	else
+		snprintf(name, nlen, "%s", devinit->name);
+
+	memory_device_register(devinit->machine->memory, name, devinit->addr,
+	    DEV_NS16550_LENGTH * d->addrmult, dev_ns16550_access, d,
+	    DM_DEFAULT, NULL);
+	machine_add_tickfunction(devinit->machine,
+	    dev_ns16550_tick, d, TICK_SHIFT);
+
+	/*
+	 *  NOTE:  Ugly cast into a pointer, because this is a convenient way
+	 *         to return the console handle to code in src/machines/.
+	 */
+	devinit->return_ptr = (void *)(size_t)d->console_handle;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_ns16550.cc gxemul-0.7.0+dfsg/src/devices/dev_ns16550.cc
--- gxemul-0.6.2/src/devices/dev_ns16550.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ns16550.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,367 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: NS16550 serial controller
- *
- *  TODO: Implement the FIFO.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/comreg.h"
-
-
-/*  #define debug fatal  */
-
-#define	TICK_SHIFT		14
-#define	DEV_NS16550_LENGTH	8
-
-struct ns_data {
-	int		addrmult;
-	int		in_use;
-	const char	*name;
-	int		console_handle;
-	int		enable_fifo;
-
-	struct interrupt irq;
-
-	unsigned char	reg[DEV_NS16550_LENGTH];
-	unsigned char	fcr;		/*  FIFO control register  */
-	int		int_asserted;
-	int		dlab;		/*  Divisor Latch Access bit  */
-	int		divisor;
-
-	int		databits;
-	char		parity;
-	const char	*stopbits;
-};
-
-
-DEVICE_TICK(ns16550)
-{
-	/*
-	 *  This function is called at regular intervals. An interrupt is
-	 *  asserted if there is a character available for reading, or if the
-	 *  transmitter slot is empty (i.e. the ns16550 is ready to transmit).
-	 */
-	struct ns_data *d = (struct ns_data *) extra;
-
-	d->reg[com_iir] &= ~IIR_RXRDY;
-	if (console_charavail(d->console_handle))
-		d->reg[com_iir] |= IIR_RXRDY;
-
-	/*
-	 *  If interrupts are enabled, and interrupts are pending, then
-	 *  cause a CPU interrupt.
- 	 */
-
-	if (((d->reg[com_ier] & IER_ETXRDY) && (d->reg[com_iir] & IIR_TXRDY)) ||
-	    ((d->reg[com_ier] & IER_ERXRDY) && (d->reg[com_iir] & IIR_RXRDY))) {
-		d->reg[com_iir] &= ~IIR_NOPEND;
-		if (d->reg[com_mcr] & MCR_IENABLE) {
-			INTERRUPT_ASSERT(d->irq);
-			d->int_asserted = 1;
-		}
-	} else {
-		d->reg[com_iir] |= IIR_NOPEND;
-		if (d->int_asserted)
-			INTERRUPT_DEASSERT(d->irq);
-		d->int_asserted = 0;
-	}
-}
-
-
-DEVICE_ACCESS(ns16550)
-{
-	uint64_t idata = 0, odata=0;
-	size_t i;
-	struct ns_data *d = (struct ns_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-#if 0
-	/*  The NS16550 should be accessed using byte read/writes:  */
-	if (len != 1)
-		fatal("[ ns16550 (%s): len=%i, idata=0x%16llx! ]\n",
-		    d->name, len, (long long)idata);
-#endif
-
-	/*
-	 *  Always ready to transmit:
-	 */
-	d->reg[com_lsr] |= LSR_TXRDY | LSR_TSRE;
-	d->reg[com_msr] |= MSR_DCD | MSR_DSR | MSR_CTS;
-
-	d->reg[com_iir] &= ~0xf0;
-	if (d->enable_fifo)
-		d->reg[com_iir] |= ((d->fcr << 5) & 0xc0);
-
-	d->reg[com_lsr] &= ~LSR_RXRDY;
-	if (console_charavail(d->console_handle))
-		d->reg[com_lsr] |= LSR_RXRDY;
-
-	relative_addr /= d->addrmult;
-
-	if (relative_addr >= DEV_NS16550_LENGTH) {
-		fatal("[ ns16550 (%s): outside register space? relative_addr="
-		    "0x%llx. bad addrmult? bad device length? ]\n", d->name,
-		    (long long)relative_addr);
-		return 0;
-	}
-
-	switch (relative_addr) {
-
-	case com_data:	/*  data AND low byte of the divisor  */
-		/*  Read/write of the Divisor value:  */
-		if (d->dlab) {
-			/*  Write or read the low byte of the divisor:  */
-			if (writeflag == MEM_WRITE)
-				d->divisor = (d->divisor & 0xff00) | idata;
-			else
-				odata = d->divisor & 0xff;
-			break;
-		}
-
-		/*  Read/write of data:  */
-		if (writeflag == MEM_WRITE) {
-			if (d->reg[com_mcr] & MCR_LOOPBACK)
-				console_makeavail(d->console_handle, idata);
-			else
-				console_putchar(d->console_handle, idata);
-			d->reg[com_iir] |= IIR_TXRDY;
-		} else {
-			int x = console_readchar(d->console_handle);
-			odata = x < 0? 0 : x;
-		}
-		dev_ns16550_tick(cpu, d);
-		break;
-
-	case com_ier:	/*  interrupt enable AND high byte of the divisor  */
-		/*  Read/write of the Divisor value:  */
-		if (d->dlab) {
-			if (writeflag == MEM_WRITE) {
-				/*  Set the high byte of the divisor:  */
-				d->divisor = (d->divisor & 0xff) | (idata << 8);
-				debug("[ ns16550 (%s): speed set to %i bps ]\n",
-				    d->name, (int)(115200 / d->divisor));
-			} else
-				odata = d->divisor >> 8;
-			break;
-		}
-
-		/*  IER:  */
-		if (writeflag == MEM_WRITE) {
-			/*  This is to supress Linux' behaviour  */
-			if (idata != 0)
-				debug("[ ns16550 (%s): write to ier: 0x%02x ]"
-				    "\n", d->name, (int)idata);
-
-			/*  Needed for NetBSD 2.0.x, but not 1.6.2?  */
-			if (!(d->reg[com_ier] & IER_ETXRDY)
-			    && (idata & IER_ETXRDY))
-				d->reg[com_iir] |= IIR_TXRDY;
-
-			d->reg[com_ier] = idata;
-			dev_ns16550_tick(cpu, d);
-		} else
-			odata = d->reg[com_ier];
-		break;
-
-	case com_iir:	/*  interrupt identification (r), fifo control (w)  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ ns16550 (%s): write to fifo control: 0x%02x ]"
-			    "\n", d->name, (int)idata);
-			d->fcr = idata;
-		} else {
-			odata = d->reg[com_iir];
-			if (d->reg[com_iir] & IIR_TXRDY)
-				d->reg[com_iir] &= ~IIR_TXRDY;
-			debug("[ ns16550 (%s): read from iir: 0x%02x ]\n",
-			    d->name, (int)odata);
-			dev_ns16550_tick(cpu, d);
-		}
-		break;
-
-	case com_lsr:
-		if (writeflag == MEM_WRITE) {
-			debug("[ ns16550 (%s): write to lsr: 0x%02x ]\n",
-			    d->name, (int)idata);
-			d->reg[com_lsr] = idata;
-		} else {
-			odata = d->reg[com_lsr];
-			/*  debug("[ ns16550 (%s): read from lsr: 0x%02x ]\n",
-			    d->name, (int)odata);  */
-		}
-		break;
-
-	case com_msr:
-		if (writeflag == MEM_WRITE) {
-			debug("[ ns16550 (%s): write to msr: 0x%02x ]\n",
-			    d->name, (int)idata);
-			d->reg[com_msr] = idata;
-		} else {
-			odata = d->reg[com_msr];
-			debug("[ ns16550 (%s): read from msr: 0x%02x ]\n",
-			    d->name, (int)odata);
-		}
-		break;
-
-	case com_lctl:
-		if (writeflag == MEM_WRITE) {
-			d->reg[com_lctl] = idata;
-			switch (idata & 0x7) {
-			case 0:	d->databits = 5; d->stopbits = "1"; break;
-			case 1:	d->databits = 6; d->stopbits = "1"; break;
-			case 2:	d->databits = 7; d->stopbits = "1"; break;
-			case 3:	d->databits = 8; d->stopbits = "1"; break;
-			case 4:	d->databits = 5; d->stopbits = "1.5"; break;
-			case 5:	d->databits = 6; d->stopbits = "2"; break;
-			case 6:	d->databits = 7; d->stopbits = "2"; break;
-			case 7:	d->databits = 8; d->stopbits = "2"; break;
-			}
-			switch ((idata & 0x38) / 0x8) {
-			case 0:	d->parity = 'N'; break;		/*  none  */
-			case 1:	d->parity = 'O'; break;		/*  odd  */
-			case 2:	d->parity = '?'; break;
-			case 3:	d->parity = 'E'; break;		/*  even  */
-			case 4:	d->parity = '?'; break;
-			case 5:	d->parity = 'Z'; break;		/*  zero  */
-			case 6:	d->parity = '?'; break;
-			case 7:	d->parity = 'o'; break;		/*  one  */
-			}
-
-			d->dlab = idata & 0x80? 1 : 0;
-
-			debug("[ ns16550 (%s): write to lctl: 0x%02x (%s%s"
-			    "setting mode %i%c%s) ]\n", d->name, (int)idata,
-			    d->dlab? "Divisor Latch access, " : "",
-			    idata&0x40? "sending BREAK, " : "",
-			    d->databits, d->parity, d->stopbits);
-		} else {
-			odata = d->reg[com_lctl];
-			debug("[ ns16550 (%s): read from lctl: 0x%02x ]\n",
-			    d->name, (int)odata);
-		}
-		break;
-
-	case com_mcr:
-		if (writeflag == MEM_WRITE) {
-			d->reg[com_mcr] = idata;
-			debug("[ ns16550 (%s): write to mcr: 0x%02x ]\n",
-			    d->name, (int)idata);
-			if (!(d->reg[com_iir] & IIR_TXRDY)
-			    && (idata & MCR_IENABLE))
-				d->reg[com_iir] |= IIR_TXRDY;
-			dev_ns16550_tick(cpu, d);
-		} else {
-			odata = d->reg[com_mcr];
-			debug("[ ns16550 (%s): read from mcr: 0x%02x ]\n",
-			    d->name, (int)odata);
-		}
-		break;
-
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ ns16550 (%s): read from reg %i ]\n",
-			    d->name, (int)relative_addr);
-			odata = d->reg[relative_addr];
-		} else {
-			debug("[ ns16550 (%s): write to reg %i:",
-			    d->name, (int)relative_addr);
-			for (i=0; i<len; i++)
-				debug(" %02x", data[i]);
-			debug(" ]\n");
-			d->reg[relative_addr] = idata;
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(ns16550)
-{
-	struct ns_data *d;
-	size_t nlen;
-	char *name;
-
-	CHECK_ALLOCATION(d = (struct ns_data *) malloc(sizeof(struct ns_data)));
-	memset(d, 0, sizeof(struct ns_data));
-
-	d->addrmult	= devinit->addr_mult;
-	d->in_use	= devinit->in_use;
-	d->enable_fifo	= 1;
-	d->dlab		= 0;
-	d->divisor	= 115200 / 9600;
-	d->databits	= 8;
-	d->parity	= 'N';
-	d->stopbits	= "1";
-	d->name		= devinit->name2 != NULL? devinit->name2 : "";
-	d->console_handle =
-	    console_start_slave(devinit->machine, devinit->name2 != NULL?
-	    devinit->name2 : devinit->name, d->in_use);
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	nlen = strlen(devinit->name) + 10;
-	if (devinit->name2 != NULL)
-		nlen += strlen(devinit->name2);
-	CHECK_ALLOCATION(name = (char *) malloc(nlen));
-	if (devinit->name2 != NULL && devinit->name2[0])
-		snprintf(name, nlen, "%s [%s]", devinit->name, devinit->name2);
-	else
-		snprintf(name, nlen, "%s", devinit->name);
-
-	memory_device_register(devinit->machine->memory, name, devinit->addr,
-	    DEV_NS16550_LENGTH * d->addrmult, dev_ns16550_access, d,
-	    DM_DEFAULT, NULL);
-	machine_add_tickfunction(devinit->machine,
-	    dev_ns16550_tick, d, TICK_SHIFT);
-
-	/*
-	 *  NOTE:  Ugly cast into a pointer, because this is a convenient way
-	 *         to return the console handle to code in src/machines/.
-	 */
-	devinit->return_ptr = (void *)(size_t)d->console_handle;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_ohci.c gxemul-0.7.0+dfsg/src/devices/dev_ohci.c
--- gxemul-0.6.2/src/devices/dev_ohci.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ohci.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,163 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: USB Open Host Controller Interface
+ *
+ *  TODO
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/ohcireg.h"
+
+
+/*  Length is 0x1000 at least on Playstation 2  */
+#define	DEV_OHCI_LENGTH		0x1000
+
+
+#define debug fatal
+
+
+struct ohci_data {
+	struct interrupt	irq;
+
+	int			port1reset;
+};
+
+
+DEVICE_ACCESS(ohci)
+{
+	struct ohci_data *d = (struct ohci_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	const char *name = NULL;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	case OHCI_REVISION:
+		name = "REVISION";
+		if (writeflag == MEM_READ) {
+			odata = 0x10;	/*  Version 1.0.  */
+		}
+		break;
+	case OHCI_COMMAND_STATUS:
+		name = "COMMAND_STATUS";
+		if (idata == 0x2) {
+			fatal("Hm... OHCI COMMAND STATUS\n");
+			INTERRUPT_ASSERT(d->irq);
+		}
+		break;
+	case OHCI_INTERRUPT_STATUS:
+		name = "INTERRUPT_STATUS";
+		odata = OHCI_WDH;
+		break;
+/*
+ *  TODO: It now sleeps at      tsleep(xfer, PRIBIO, "usbsyn", 0);
+ *  in netbsd/src/sys/dev/usb/usbdi.c
+ */
+	case OHCI_RH_DESCRIPTOR_A:
+		name = "RH_DESCRIPTOR_A";
+		odata = 2;	/*  Nr of ports  */
+		break;
+	case OHCI_RH_STATUS:
+		name = "RH_STATUS";
+		/*  TODO  */
+		break;
+	case OHCI_RH_PORT_STATUS(1):	/*  First port  */
+		name = "RH_PORT_STATUS(1)";
+		if (writeflag == MEM_READ) {
+			/*  Status = low 16, Change = top 16  */
+			odata = 0x10101;
+			/*  0x0001 = connected
+			    0x0100 = power  */
+			if (d->port1reset)
+				odata |= (0x10 << 16) | 0x10;
+		} else {
+			/*  0x10 = UPS_C_PORT_RESET  */
+			if (idata & 0x10)
+				d->port1reset = 1;
+			if (idata & 0x100000)
+				d->port1reset = 0;
+		}
+		break;
+	case OHCI_RH_PORT_STATUS(2):	/*  Second port  */
+		name = "RH_PORT_STATUS(2)";
+		/*  TODO  */
+		odata = 0;
+		break;
+	default:
+		if (writeflag == MEM_READ) {
+			debug("[ ohci: read from addr 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)odata);
+		} else {
+			debug("[ ohci: write to addr 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)idata);
+		}
+	}
+
+	if (name != NULL) {
+		if (writeflag == MEM_READ)
+			debug("[ ohci: read from %s: 0x%llx ]\n",
+			    name, (long long)odata);
+		else
+			debug("[ ohci: write to %s: 0x%llx ]\n",
+			    name, (long long)idata);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(ohci)
+{
+	struct ohci_data *d;
+
+	CHECK_ALLOCATION(d = (struct ohci_data *) malloc(sizeof(struct ohci_data)));
+	memset(d, 0, sizeof(struct ohci_data));
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	memory_device_register(devinit->machine->memory,
+	    devinit->name, devinit->addr,
+	    DEV_OHCI_LENGTH, dev_ohci_access, d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_ohci.cc gxemul-0.7.0+dfsg/src/devices/dev_ohci.cc
--- gxemul-0.6.2/src/devices/dev_ohci.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ohci.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,163 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: USB Open Host Controller Interface
- *
- *  TODO
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/ohcireg.h"
-
-
-/*  Length is 0x1000 at least on Playstation 2  */
-#define	DEV_OHCI_LENGTH		0x1000
-
-
-#define debug fatal
-
-
-struct ohci_data {
-	struct interrupt	irq;
-
-	int			port1reset;
-};
-
-
-DEVICE_ACCESS(ohci)
-{
-	struct ohci_data *d = (struct ohci_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	const char *name = NULL;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	case OHCI_REVISION:
-		name = "REVISION";
-		if (writeflag == MEM_READ) {
-			odata = 0x10;	/*  Version 1.0.  */
-		}
-		break;
-	case OHCI_COMMAND_STATUS:
-		name = "COMMAND_STATUS";
-		if (idata == 0x2) {
-			fatal("Hm... OHCI COMMAND STATUS\n");
-			INTERRUPT_ASSERT(d->irq);
-		}
-		break;
-	case OHCI_INTERRUPT_STATUS:
-		name = "INTERRUPT_STATUS";
-		odata = OHCI_WDH;
-		break;
-/*
- *  TODO: It now sleeps at      tsleep(xfer, PRIBIO, "usbsyn", 0);
- *  in netbsd/src/sys/dev/usb/usbdi.c
- */
-	case OHCI_RH_DESCRIPTOR_A:
-		name = "RH_DESCRIPTOR_A";
-		odata = 2;	/*  Nr of ports  */
-		break;
-	case OHCI_RH_STATUS:
-		name = "RH_STATUS";
-		/*  TODO  */
-		break;
-	case OHCI_RH_PORT_STATUS(1):	/*  First port  */
-		name = "RH_PORT_STATUS(1)";
-		if (writeflag == MEM_READ) {
-			/*  Status = low 16, Change = top 16  */
-			odata = 0x10101;
-			/*  0x0001 = connected
-			    0x0100 = power  */
-			if (d->port1reset)
-				odata |= (0x10 << 16) | 0x10;
-		} else {
-			/*  0x10 = UPS_C_PORT_RESET  */
-			if (idata & 0x10)
-				d->port1reset = 1;
-			if (idata & 0x100000)
-				d->port1reset = 0;
-		}
-		break;
-	case OHCI_RH_PORT_STATUS(2):	/*  Second port  */
-		name = "RH_PORT_STATUS(2)";
-		/*  TODO  */
-		odata = 0;
-		break;
-	default:
-		if (writeflag == MEM_READ) {
-			debug("[ ohci: read from addr 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)odata);
-		} else {
-			debug("[ ohci: write to addr 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)idata);
-		}
-	}
-
-	if (name != NULL) {
-		if (writeflag == MEM_READ)
-			debug("[ ohci: read from %s: 0x%llx ]\n",
-			    name, (long long)odata);
-		else
-			debug("[ ohci: write to %s: 0x%llx ]\n",
-			    name, (long long)idata);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(ohci)
-{
-	struct ohci_data *d;
-
-	CHECK_ALLOCATION(d = (struct ohci_data *) malloc(sizeof(struct ohci_data)));
-	memset(d, 0, sizeof(struct ohci_data));
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	memory_device_register(devinit->machine->memory,
-	    devinit->name, devinit->addr,
-	    DEV_OHCI_LENGTH, dev_ohci_access, d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_osiop.c gxemul-0.7.0+dfsg/src/devices/dev_osiop.c
--- gxemul-0.6.2/src/devices/dev_osiop.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_osiop.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1058 @@
+/*
+ *  Copyright (C) 2008-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: NCR 53C710 SCSI I/O Processor (SIOP)
+ *
+ *  Based on reverse-engineering OpenBSD's osiop.c, and a PDF manual:
+ *  "Symbios SYM53C710 SCSI I/O Processor Technical Manual, version 3.1".
+ *
+ *  See e.g. openbsd/sys/dev/microcode/siop/osiop.ss for an example of what
+ *  the SCRIPTS assembly language looks like (or osiop.out for the raw result).
+ *
+ *
+ *  TODOs:
+ *
+ *  o)	Target mode. Right now, only Initiator mode is implemented.
+ *  o)	Errors. Right now, the emulator aborts if there is a SCSI error.
+ *  o)	Allow all phases to do partial transfers. Right now, only data in
+ *	and data out support this (hackish).
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "diskimage.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/osiopreg.h"
+
+
+/*  #define debug fatal  */
+const int osiop_debug = 0;
+
+static const char *phases[8] =
+	{ "DATA_OUT", "DATA_IN", "COMMAND", "STATUS",
+	  "RESERVED_OUT", "RESERVED_IN", "MSG_OUT", "MSG_IN" };
+
+#define	DEV_OSIOP_LENGTH	OSIOP_NREGS
+#define	OSIOP_CHIP_REVISION	2
+
+#define	MAX_SCRIPTS_PER_CHUNK	256	/*  256 may be a reasonable value?  */
+
+#define	OSIOP_TICK_SHIFT	17
+
+struct osiop_data {
+	struct interrupt	irq;
+	int			asserted;
+	
+	int			scripts_running;
+
+	/*  Current transfer:  */
+	int			selected_id;
+	struct scsi_transfer	*xferp;
+	size_t			data_offset;
+
+	/*  Cached emulated physical RAM page lookup:  */
+	uint32_t		last_phys_page;
+	uint8_t			*last_host_page;
+
+	/*  ALU:  */
+	int			carry;
+	
+	/*
+	 *  Most of these are byte-addressed, but some are not. (Note: For
+	 *  convenience, 32-bit words are stored in host byte order!)
+	 */
+	uint8_t			reg[OSIOP_NREGS];
+};
+
+
+static void osiop_free_xfer(struct osiop_data *d)
+{
+	if (d->xferp != NULL)
+		scsi_transfer_free(d->xferp);
+
+	d->xferp = NULL;
+}
+
+
+/*  Allocate memory for a new transfer.  */
+static void osiop_new_xfer(struct osiop_data *d, int target_scsi_id)
+{
+	if (d->xferp != NULL) {
+		fatal("WARNING! osiop_new_xfer(): freeing previous"
+		    " transfer\n");
+		osiop_free_xfer(d);
+	}
+
+	d->selected_id = target_scsi_id;
+	d->xferp = scsi_transfer_alloc();
+}
+
+
+static int osiop_get_scsi_phase(struct osiop_data *d)
+{
+	return OSIOP_PHASE(d->reg[OSIOP_SOCL]);
+}
+
+
+static void osiop_set_scsi_phase(struct osiop_data *d, int phase)
+{
+	int mask = OSIOP_MSG | OSIOP_CD | OSIOP_IO;
+	d->reg[OSIOP_SOCL] &= ~mask;
+	d->reg[OSIOP_SOCL] |= (phase & mask);
+}
+
+
+/*
+ *  osiop_update_sip_and_dip():
+ *
+ *  The SIP bit in ISTAT is basically a "summary" of whether there is
+ *  a non-masked SCSI interrupt. Similarly for DIP, for DMA.
+ *
+ *  However, the SIP and DIP bits are set even if interrupts are
+ *  masked away using DIEN and SIEN. (At least that is how I understood
+ *  things from reading OpenBSD's osiop.c osiop_poll().) 
+ */
+static int osiop_update_sip_and_dip(struct osiop_data *d)
+{
+	int assert = 0;
+
+	/*  First, let's assume no interrupt assertions.  */
+	d->reg[OSIOP_ISTAT] &= ~(OSIOP_ISTAT_SIP | OSIOP_ISTAT_DIP);
+
+	/*  Any enabled SCSI interrupts?  */
+	if (d->reg[OSIOP_SSTAT0])
+		d->reg[OSIOP_ISTAT] |= OSIOP_ISTAT_SIP;
+	if (d->reg[OSIOP_SSTAT0] & d->reg[OSIOP_SIEN])
+		assert = 1;
+
+	/*  Or enabled DMA interrupts?  */
+	if (d->reg[OSIOP_DSTAT] & ~OSIOP_DIEN_RES)
+		d->reg[OSIOP_ISTAT] |= OSIOP_ISTAT_DIP;
+	if (d->reg[OSIOP_DSTAT] & d->reg[OSIOP_DIEN] & ~OSIOP_DIEN_RES)
+		assert = 1;
+
+	return assert;
+}
+
+
+/*
+ *  osiop_reassert_interrupts():
+ *
+ *  Recalculate interrupt assertions; if either of the SIP or DIP bits
+ *  in the ISTAT register is set, then we should cause an interrupt.
+ *
+ *  (The d->asserted stuff is to make sure we don't call INTERRUPT_DEASSERT
+ *  etc. too often when not necessary. Just an optimization.)
+ */
+static void osiop_reassert_interrupts(struct osiop_data *d)
+{
+	int assert = 0;
+
+	if (osiop_update_sip_and_dip(d))
+		assert = 1;
+
+	if (assert && !d->asserted)
+		INTERRUPT_ASSERT(d->irq);
+	if (!assert && d->asserted)
+		INTERRUPT_DEASSERT(d->irq);
+
+	d->asserted = assert;
+}
+
+
+/*  Helper: returns a word in host order, from emulated physical RAM.  */
+static uint32_t read_word(struct osiop_data *d, struct cpu *cpu, uint32_t addr)
+{
+	uint32_t word;
+
+	if (d->last_host_page == NULL ||
+	    d->last_phys_page != (addr & 0xfffff000)) {
+		d->last_phys_page = addr & 0xfffff000;
+		d->last_host_page =
+		    memory_paddr_to_hostaddr(cpu->mem, d->last_phys_page, 0);
+	}
+
+	word = *((uint32_t *) (d->last_host_page + (addr & 0xffc)));
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		word = LE32_TO_HOST(word);
+	else
+		word = BE32_TO_HOST(word);
+
+	return word;
+}
+
+
+/*  Helper: reads/writes single bytes from emulated physical RAM.  */
+static uint8_t read_byte(struct osiop_data *d, struct cpu *cpu, uint32_t addr)
+{
+	if (d->last_host_page == NULL ||
+	    d->last_phys_page != (addr & 0xfffff000)) {
+		d->last_phys_page = addr & 0xfffff000;
+		d->last_host_page =
+		    memory_paddr_to_hostaddr(cpu->mem, d->last_phys_page, 0);
+	}
+
+	return d->last_host_page[addr & 0xfff];
+}
+static void write_byte(struct osiop_data *d, struct cpu *cpu, uint32_t addr, uint8_t byte)
+{
+	if (d->last_host_page == NULL ||
+	    d->last_phys_page != (addr & 0xfffff000)) {
+		d->last_phys_page = addr & 0xfffff000;
+		d->last_host_page =
+		    memory_paddr_to_hostaddr(cpu->mem, d->last_phys_page, 1);
+	}
+
+	d->last_host_page[addr & 0xfff] = byte;
+}
+
+
+/*
+ *  osiop_get_next_scripts_word():
+ *
+ *  Reads a 32-bit word at physical memory location DSP, and returns it
+ *  in host order. DSP is then advanced to point to the next instruction word.
+ *
+ *  (NOTE/TODO: This could be optimized to read from a host page directly,
+ *  but then care must be taken when the instruction pointer (DSP) goes
+ *  over a page boundary to the next page. At least the page lookup
+ *  could be "cached"...)
+ */
+uint32_t osiop_get_next_scripts_word(struct cpu *cpu, struct osiop_data *d)
+{
+	uint32_t *dspp = (uint32_t*) &d->reg[OSIOP_DSP];
+	uint32_t dsp = *dspp;
+	uint32_t instr;
+
+	if (dsp & 3) {
+		fatal("osiop_get_next_scripts_word: unaligned DSP 0x%08x\n",
+		    dsp);
+		exit(1);
+	}
+
+	instr = read_word(d, cpu, dsp);
+
+	dsp += sizeof(instr);
+	*dspp = dsp;
+
+	return instr;
+}
+
+
+/*
+ *  osiop_execute_scripts_instr():
+ *
+ *  Interprets a single SCRIPTS machine code instruction. Returns 1 if
+ *  execution should continue, or 0 if there was an interrupt.
+ *
+ *  See "Symbios SYM53C710 SCSI I/O Processor Technical Manual, version 3.1"
+ *  chapter 5 for details about the instruction set.
+ */
+int osiop_execute_scripts_instr(struct cpu *cpu, struct osiop_data *d)
+{
+	uint32_t *dsap = (uint32_t*) &d->reg[OSIOP_DSA];
+	uint32_t *dnadp = (uint32_t*) &d->reg[OSIOP_DNAD];
+	uint32_t *dbcp = (uint32_t*) &d->reg[OSIOP_DBC];
+	uint32_t *dspsp = (uint32_t*) &d->reg[OSIOP_DSPS];
+	uint32_t *dspp = (uint32_t*) &d->reg[OSIOP_DSP];
+	uint32_t *tempp = (uint32_t*) &d->reg[OSIOP_TEMP];
+
+	uint32_t dspOrig = *dspp;
+	uint32_t instr1 = osiop_get_next_scripts_word(cpu, d);
+	uint32_t instr2 = osiop_get_next_scripts_word(cpu, d);
+	uint32_t dbc, target_addr = 0;
+	uint8_t dcmd;
+	int32_t reladdr;
+	int opcode, phase, relative_addressing, table_indirect_addressing;
+	int select_with_atn, scsi_ids_to_select = -1, scsi_id_to_select;
+	int test_carry, compare_data, compare_phase;
+	int jump_if_true, wait_for_valid_phase;
+	int comparison = 0, interrupt_instead_of_branch = 0;
+	
+	/*
+	 *  According to the 53C710 manual, chapter 5 (introduction): the first
+	 *  32-bit word is always loaded into DCMD and DBC, the second into
+	 *  DSPS, the third (only used by memory move instructions) is loaded
+	 *  into the TEMP register.
+	 */
+
+	dcmd = d->reg[OSIOP_DCMD] = instr1 >> 24;
+	dbc = *dbcp = instr1 & 0x00ffffff;
+	*dspsp = instr2;
+
+	reladdr = (instr2 << 8);
+	reladdr >>= 8;
+
+	opcode = (dcmd >> 3) & 7;
+	phase = dcmd & 7;
+
+	if (osiop_debug)
+		debug("{ SCRIPTS @ 0x%08x:  0x%08x 0x%08x",
+		    (int) dspOrig, (int) instr1, (int) instr2);
+
+	switch (dcmd & 0xc0) {
+
+	case 0x00:
+		{
+			int ofs1 = instr1 & 0x00ffffff;
+			int ofs2 = instr2 & 0x00ffffff;
+			int indirect_addressing = dcmd & 0x20;
+			uint32_t dsa = *dsap;
+			uint32_t addr, xfer_byte_count, xfer_addr;
+			int32_t tmp = ofs2 << 8;
+			int res;
+			size_t i;
+
+			tmp >>= 8;
+			table_indirect_addressing = dcmd & 0x10;
+			
+			opcode = (dcmd >> 3) & 1;
+
+			switch (opcode) {
+			case 0: if (osiop_debug)
+					debug(": CHMOV");
+				break;
+			case 1: if (osiop_debug)
+					debug(": MOVE");
+				break;
+			}
+
+			if (indirect_addressing) {
+				fatal("osiop: TODO: indirect_addressing move\n");
+				exit(1);
+			}
+
+			if (!table_indirect_addressing) {
+				fatal("osiop: TODO: !table_indirect_addressing move\n");
+				exit(1);
+			}
+			
+			if (osiop_debug)
+				debug(" FROM %i", tmp);
+			
+			if (ofs1 != ofs2) {
+				fatal("osiop: TODO: move ofs1!=ofs2\n");
+				exit(1);
+			}
+			
+			if (phase != osiop_get_scsi_phase(d)) {
+				fatal("osiop: TODO: move: wait for phase. "
+				    "phase = %i, osiop_get_scsi_phase = %i\n",
+				    phase, osiop_get_scsi_phase(d));
+				exit(1);
+			}
+
+			if (osiop_debug)			
+				debug(" WHEN %s", phases[phase]);
+
+			addr = dsa + tmp;
+			xfer_byte_count = read_word(d, cpu, addr) & 0x00ffffff;
+			xfer_addr = read_word(d, cpu, addr+4);
+
+			switch (phase) {
+
+			case MSG_OUT_PHASE:
+				scsi_transfer_allocbuf(&d->xferp->msg_out_len,
+				    &d->xferp->msg_out, xfer_byte_count, 0);
+
+				i = 0;
+				while (xfer_byte_count > 0) {
+					uint8_t byte = read_byte(d, cpu, xfer_addr);
+					/*  debug("  reading msg_out byte @ 0x%08x = 0x%02x\n",
+					    xfer_addr, byte);  */
+					d->xferp->msg_out[i++] = byte;
+					xfer_addr ++;
+					xfer_byte_count --;
+				}
+				
+				osiop_set_scsi_phase(d, COMMAND_PHASE);
+				break;
+
+			case COMMAND_PHASE:
+				scsi_transfer_allocbuf(&d->xferp->cmd_len,
+				    &d->xferp->cmd, xfer_byte_count, 0);
+
+				i = 0;
+				while (xfer_byte_count > 0) {
+					uint8_t byte = read_byte(d, cpu, xfer_addr);
+					/*  debug("  reading cmd byte @ 0x%08x = 0x%02x\n",
+					    xfer_addr, byte);  */
+					d->xferp->cmd[i++] = byte;
+					xfer_addr ++;
+					xfer_byte_count --;
+				}
+
+				res = diskimage_scsicommand(cpu,
+				    d->selected_id, DISKIMAGE_SCSI, d->xferp);
+				if (res == 0) {
+					fatal("osiop TODO: error\n");
+					exit(1);
+				}
+
+				d->data_offset = 0;
+				
+				if (res == 2)
+					osiop_set_scsi_phase(d, DATA_OUT_PHASE);
+				else if (d->xferp->data_in_len > 0)
+					osiop_set_scsi_phase(d, DATA_IN_PHASE);
+				else
+					osiop_set_scsi_phase(d, STATUS_PHASE);
+				break;
+
+			case DATA_OUT_PHASE:
+				if (d->xferp->data_out == NULL)
+					scsi_transfer_allocbuf(&d->xferp->data_out_len,
+					    &d->xferp->data_out, d->xferp->data_out_len, 0);
+
+				while (xfer_byte_count > 0) {
+					uint8_t byte = read_byte(d, cpu, xfer_addr);
+					/*  debug("  reading data_out byte @ 0x%08x = 0x%02x\n",
+					    xfer_addr, byte);  */
+					d->xferp->data_out[d->xferp->data_out_offset++] = byte;
+					xfer_addr ++;
+					xfer_byte_count --;
+				}
+
+				/*  Rerun the command to actually write out the data:  */
+				res = diskimage_scsicommand(cpu,
+				    d->selected_id, DISKIMAGE_SCSI, d->xferp);
+				if (res == 0) {
+					fatal("osiop TODO: error on rerun\n");
+					exit(1);
+				} else if (res == 2) {
+					/*  Stay at data out phase.  */
+				} else {
+					osiop_set_scsi_phase(d, STATUS_PHASE);
+				}
+				break;
+
+			case DATA_IN_PHASE:
+				i = 0;
+				while (xfer_byte_count > 0 && i + d->data_offset < d->xferp->data_in_len) {
+					uint8_t byte = d->xferp->data_in[i + d->data_offset];
+					i ++;
+					/*  debug("  writing data_in byte @ 0x%08x = 0x%02x\n",
+					    xfer_addr, byte);  */
+					write_byte(d, cpu, xfer_addr, byte);
+					xfer_addr ++;
+					xfer_byte_count --;
+				}
+
+				d->data_offset += i;
+				if (d->data_offset >= d->xferp->data_in_len)
+					osiop_set_scsi_phase(d, STATUS_PHASE);
+				break;
+
+			case STATUS_PHASE:
+				i = 0;
+				while (xfer_byte_count > 0 && i < d->xferp->status_len) {
+					uint8_t byte = d->xferp->status[i++];
+					/*  debug("  writing status byte @ 0x%08x = 0x%02x\n",
+					    xfer_addr, byte);  */
+					write_byte(d, cpu, xfer_addr, byte);
+					xfer_addr ++;
+					xfer_byte_count --;
+				}
+
+				osiop_set_scsi_phase(d, MSG_IN_PHASE);
+				break;
+
+			case MSG_IN_PHASE:
+				i = 0;
+				while (xfer_byte_count > 0 && i < d->xferp->msg_in_len) {
+					uint8_t byte = d->xferp->msg_in[i++];
+					/*  debug("  writing msg_in byte @ 0x%08x = 0x%02x\n",
+					    xfer_addr, byte);  */
+					write_byte(d, cpu, xfer_addr, byte);
+					xfer_addr ++;
+					xfer_byte_count --;
+				}
+
+				/*  Done.  */
+				osiop_free_xfer(d);
+				break;
+
+			default:fatal("osiop: TODO: unimplemented move, "
+				    "phase=%i\n", phase);
+				exit(1);
+			}
+
+			/*  Transfer complete.  */
+			*dnadp = xfer_addr;
+			*dbcp = xfer_byte_count;
+			
+			d->reg[OSIOP_DFIFO] = 0;	/*  TODO  */
+		}
+		break;
+
+	case 0x40:
+		/*  I/O or Read/Write  */
+		relative_addressing = dcmd & 4;
+		table_indirect_addressing = dcmd & 2;
+		select_with_atn = dcmd & 1;
+		scsi_ids_to_select = (dbc >> 16) & 0xff;
+
+		switch (opcode) {
+		case 0:	if (osiop_debug)
+				debug(": SELECT");
+			if (select_with_atn) {
+				if (osiop_debug)
+					debug(" ATN");
+				d->reg[OSIOP_SOCL] |= OSIOP_ATN;
+			}
+
+			if (table_indirect_addressing) {
+				uint32_t dsa = *dsap;
+				uint32_t addr, word;
+				int32_t tmp = dbc << 8;
+				tmp >>= 8;
+				addr = dsa + tmp;
+
+				if (osiop_debug)
+					debug(" FROM %i", dbc);
+
+				word = read_word(d, cpu, addr);
+				scsi_ids_to_select = (word >> 16) & 0xff;
+			}
+
+			if (scsi_ids_to_select == 0) {
+				fatal("osiop: TODO: scsi_ids_to_select = 0!\n");
+				exit(1);
+			}
+
+			scsi_id_to_select = 0;
+			while (!(scsi_ids_to_select & 1)) {
+				scsi_ids_to_select >>= 1;
+				scsi_id_to_select ++;
+			}
+
+			scsi_ids_to_select &= ~1;
+			if (scsi_ids_to_select != 0) {
+				fatal("osiop: TODO: multiselect?\n");
+				exit(1);
+			}		
+
+			if (osiop_debug)
+				debug(" [SCSI ID %i]", scsi_id_to_select);
+
+			if (relative_addressing) {
+				/*  Note: Relative to _current_ DSP value, not
+				    what the DSP was when the current
+				    instruction was read!  */
+				target_addr = reladdr + *dspp;
+				if (osiop_debug)
+					debug(" REL(%i)", reladdr);
+			} else {
+				target_addr = instr2;
+				if (osiop_debug)
+					debug(" 0x%08x", instr2);
+			}
+
+			if (diskimage_exist(cpu->machine,
+			    scsi_id_to_select, DISKIMAGE_SCSI)) {
+				osiop_new_xfer(d, scsi_id_to_select);
+
+				/*  TODO: Just a guess, so far:  */
+				osiop_set_scsi_phase(d, MSG_OUT_PHASE);
+			} else {
+				d->selected_id = -1;
+
+#if 1
+				/*  TODO: The scsi ID does not exist.
+				    Should we simply timeout:  */
+				d->scripts_running = 0;
+#else
+				/*  or branch to the reselect address?  */
+				*(uint32_t*) &d->reg[OSIOP_DSP] = target_addr;
+#endif
+			}
+
+			break;
+			
+		case 1:	if (osiop_debug)
+				debug(": WAIT DISCONNECT");
+			/*  TODO  */
+			break;
+		case 2:	if (osiop_debug)
+				debug(": WAIT RESELECT");
+			fatal("osiop: TODO: wait reselect\n");
+			exit(1);
+			break;
+	
+		case 3:	if (osiop_debug)
+				debug(": SET");
+			break;
+		case 4:	if (osiop_debug)
+				debug(": CLEAR");
+			break;
+
+		default:fatal(": UNIMPLEMENTED dcmd=0x%02x opcode=%i\n",
+			    dcmd, opcode);
+			exit(1);
+		}
+
+		/*  SET or CLEAR:  */
+		if (opcode == 3 || opcode == 4) {
+			int bit_atn = (dbc >> 3) & 1;
+			int bit_ack = (dbc >> 6) & 1;
+			int bit_target = (dbc >> 9) & 1;
+			int bit_carry = (dbc >> 10) & 1;
+
+			if (osiop_debug) {
+				if (bit_atn)
+					debug(" ATN");
+				if (bit_ack)
+					debug(" ACK");
+				if (bit_target)
+					debug(" TARGET");
+				if (bit_carry)
+					debug(" CARRY");
+			}
+					
+			if (opcode == 3) {
+				d->reg[OSIOP_SOCL] |= (bit_ack * OSIOP_ACK);
+				d->reg[OSIOP_SOCL] |= (bit_atn * OSIOP_ATN);
+				if (bit_carry)
+					d->carry = 1;
+				d->reg[OSIOP_SCNTL0] |=
+				    (bit_target * OSIOP_SCNTL0_TRG);
+			} else {
+				d->reg[OSIOP_SOCL] &= ~(bit_ack * OSIOP_ACK);
+				d->reg[OSIOP_SOCL] &= ~(bit_atn * OSIOP_ATN);
+				if (bit_carry)
+					d->carry = 0;
+				d->reg[OSIOP_SCNTL0] &=
+				    ~(bit_target * OSIOP_SCNTL0_TRG);
+			}
+		}
+
+		break;
+
+	case 0x80:
+		/*  Transfer Control  */
+		relative_addressing = (dbc >> 23) & 1;
+		test_carry = (dbc >> 21) & 1;
+		jump_if_true = (dbc >> 19) & 1;
+		compare_data = (dbc >> 18) & 1;
+		compare_phase = (dbc >> 17) & 1;
+		wait_for_valid_phase = (dbc >> 16) & 1;
+		
+		switch (opcode) {
+		case 0:	if (osiop_debug)
+				debug(": JUMP");
+			break;
+		case 1:	if (osiop_debug)
+				debug(": CALL");
+			break;
+		case 2:	if (osiop_debug)
+				debug(": RETURN");
+			break;
+		case 3:	if (osiop_debug)
+				debug(": INTERRUPT");
+			break;
+		default:fatal(": UNIMPLEMENTED dcmd=0x%02x opcode=%i\n",
+			    dcmd, opcode);
+			exit(1);
+		}
+
+		if (opcode == 0 || opcode == 1) {
+			if (relative_addressing) {
+				/*  Note: Relative to _current_ DSP value,
+				    not what it was when the current instruction
+				    was read!  */
+				target_addr = reladdr + *dspp;
+				if (osiop_debug)
+					debug(" REL(%i)", reladdr);
+			} else {
+				target_addr = instr2;
+				if (osiop_debug)
+					debug(" 0x%08x", instr2);
+			}
+		} else {
+			if (opcode == 2) {
+				/*  Return:  */
+				target_addr = *tempp;
+			} else {
+				/*  Interrupt:  */
+				interrupt_instead_of_branch = 1;
+			}
+		}
+
+		if (test_carry) {
+			if (compare_data || compare_phase) {
+				fatal("osiop: TODO: test_carry cannot be"
+				    " combined with other tests!\n");
+				exit(1);
+			}
+			
+			fatal("osiop: TODO: test_carry\n");
+			exit(1);
+		}
+
+		if (compare_data) {
+			fatal("osiop: TODO: compare_data\n");
+			exit(1);
+		}
+
+		if (compare_phase) {
+			int cur_phase;
+
+			if (osiop_debug)
+				debug(" %s %s%s",
+				    wait_for_valid_phase ? "WHEN" : "IF",
+				    jump_if_true? "" : "NOT ",
+				    phases[phase]);
+
+			/*  TODO: wait for valid phase!  */
+
+			cur_phase = osiop_get_scsi_phase(d);
+			
+			comparison = (phase == cur_phase);
+		}
+
+		if (!test_carry && !compare_data && !compare_phase)
+			jump_if_true = comparison = 1;
+
+		if ((jump_if_true && comparison) ||
+		    (!jump_if_true && !comparison)) {
+			/*  Perform the branch or interrupt.  */
+			if (interrupt_instead_of_branch) {
+				d->scripts_running = 0;
+				d->reg[OSIOP_DSTAT] |= OSIOP_DSTAT_SIR;
+			} else {
+				*dspp = target_addr;
+			}
+		}
+
+		break;
+
+	case 0xc0:
+		if (osiop_debug)
+			debug(": MEMORY MOVE");
+		/*  TODO: third instruction word!  */
+		fatal(": TODO\n");
+		exit(1);
+		break;
+
+	default:fatal(": UNIMPLEMENTED dcmd 0x%02x\n", dcmd);
+		exit(1);
+	}
+
+	if (osiop_debug)
+		debug(" }\n");
+
+	return 1;
+}
+
+
+/*
+ *  osiop_execute_scripts():
+ *
+ *  Interprets SCRIPTS machine code by reading one instruction word at a time,
+ *  and executing it.
+ */
+void osiop_execute_scripts(struct cpu *cpu, struct osiop_data *d)
+{
+	int n = 0;
+
+	if (osiop_debug)
+		debug("{ SCRIPTS start }\n");
+
+	while (d->scripts_running && n < MAX_SCRIPTS_PER_CHUNK &&
+	    osiop_execute_scripts_instr(cpu, d))
+		n++;
+
+	if (osiop_debug)	
+		debug("{ SCRIPTS end }\n");
+}
+
+
+DEVICE_TICK(osiop)
+{
+	struct osiop_data *d = (struct osiop_data *) extra;
+
+	if (d->scripts_running)
+		osiop_execute_scripts(cpu, d);
+
+	osiop_reassert_interrupts(d);
+}
+
+
+DEVICE_ACCESS(osiop)
+{
+	uint64_t idata = 0, odata = 0;
+	uint8_t oldreg = 0;
+	struct osiop_data *d = (struct osiop_data *) extra;
+	int origofs = relative_addr;
+	int non1lenOk = 0;
+
+	idata = memory_readmax64(cpu, data, len);
+
+	/*  Make relative_addr suit addresses in osiopreg.h:  */
+	if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+		relative_addr =
+		    (relative_addr & ~3) |
+		    (3 - (relative_addr & 3));
+	}
+
+	if (len == sizeof(uint32_t)) {
+		/*
+		 *  NOTE: These are stored in HOST byte order!
+		 */
+		switch (origofs) {
+		case OSIOP_DSA:
+		case OSIOP_TEMP:
+		case OSIOP_DBC:
+		case OSIOP_DNAD:
+		case OSIOP_DSP:
+		case OSIOP_DSPS:
+		case OSIOP_SCRATCH:
+		case OSIOP_ADDER:
+			relative_addr = origofs;
+			non1lenOk = 1;
+
+			uint32_t *p = (uint32_t*) &d->reg[origofs];
+
+			if (writeflag == MEM_WRITE)
+				*p = idata;
+			else
+				odata = *p;
+			
+			break;
+		}
+	} else {
+		/*  Byte access:  */
+		oldreg = d->reg[relative_addr];
+
+		if (writeflag == MEM_WRITE)
+			d->reg[relative_addr] = idata;
+		else
+			odata = oldreg;
+	}
+
+	switch (relative_addr) {
+
+	case OSIOP_SCNTL0:
+	case OSIOP_SCNTL1:
+		break;
+
+	case OSIOP_SIEN:
+		/*  Used by OpenBSD/mvme88k during probing:  */
+		if (len == 4)
+			non1lenOk = 1;
+		if (writeflag == MEM_WRITE)
+			osiop_reassert_interrupts(d);
+		break;
+
+	case OSIOP_SCID:
+		if (idata != oldreg) {
+			fatal("osiop TODO: attempt to change SCID?\n");
+			exit(1);
+		}
+		break;
+
+	case OSIOP_SBDL:
+		if (writeflag == MEM_WRITE)
+			fatal("[ osiop: SBDL set to 0x%x, but should be "
+			    "read-only! ]\n", (int) idata);
+		break;
+
+	case OSIOP_SBCL:
+		if (writeflag == MEM_WRITE) {
+			if (osiop_debug)
+				debug("[ osiop: SBCL set to 0x%x ]\n", (int) idata);
+		}
+		break;
+
+	case OSIOP_DSTAT:
+		/*  Cleared when read. Most likely not writable.  */
+		odata = d->reg[OSIOP_DSTAT];
+		d->reg[OSIOP_DSTAT] = OSIOP_DSTAT_DFE;
+		osiop_reassert_interrupts(d);
+		break;
+
+	case OSIOP_SSTAT0:
+		/*  Cleared when read. Most likely not writable.  */
+		odata = d->reg[OSIOP_SSTAT0];
+		d->reg[OSIOP_SSTAT0] = 0;
+		osiop_reassert_interrupts(d);
+		break;
+
+	case OSIOP_SSTAT1:
+	case OSIOP_SSTAT2:
+		break;
+		
+	case OSIOP_DSA:
+		if (writeflag == MEM_WRITE) {
+			if (osiop_debug)
+				debug("[ osiop: DSA set to 0x%x ]\n", (int) idata);
+		}
+		break;
+
+	case OSIOP_CTEST0:
+	case OSIOP_CTEST1:
+	case OSIOP_CTEST2:
+	case OSIOP_CTEST3:
+	case OSIOP_CTEST4:
+	case OSIOP_CTEST5:
+	case OSIOP_CTEST6:
+	case OSIOP_CTEST7:
+		break;
+
+	case OSIOP_TEMP:
+		if (writeflag == MEM_WRITE) {
+			if (osiop_debug)
+				debug("[ osiop: TEMP set to 0x%x ]\n", (int) idata);
+		}
+		break;
+
+	case OSIOP_DFIFO:
+		break;
+
+	case OSIOP_ISTAT:
+		if (writeflag == MEM_WRITE) {
+			if ((idata & 0x3f) != 0x00) {
+				fatal("osiop TODO: istat 0x%x\n", (int) idata);
+				exit(1);
+			}
+
+			d->reg[relative_addr] = idata &
+			    ~(OSIOP_ISTAT_ABRT | OSIOP_ISTAT_RST);
+			osiop_reassert_interrupts(d);
+		}
+		break;
+
+	case OSIOP_CTEST8:
+		odata = (odata & 0xf) | (OSIOP_CHIP_REVISION << 4);
+		break;
+
+	case OSIOP_DBC:
+		break;
+
+	case OSIOP_DSP:
+		if (writeflag == MEM_WRITE) {
+			if (osiop_debug)
+				debug("[ osiop: DSP set to 0x%x ]\n", (int) idata);
+
+			d->scripts_running = 1;
+			osiop_execute_scripts(cpu, d);
+			osiop_reassert_interrupts(d);
+		}
+		break;
+
+	case OSIOP_DSPS:
+	case OSIOP_SCRATCH:
+		break;
+
+	case OSIOP_DMODE:
+		break;
+
+	case OSIOP_DIEN:
+		if (writeflag == MEM_WRITE)
+			osiop_reassert_interrupts(d);
+		break;
+
+	case OSIOP_DWT:
+		break;
+
+	case OSIOP_DCNTL:
+		if (writeflag == MEM_WRITE) {
+			if (idata & OSIOP_DCNTL_SSM) {
+				fatal("osiop TODO: SSM\n");
+				exit(1);
+			}
+			if (idata & OSIOP_DCNTL_LLM) {
+				fatal("osiop TODO: LLM\n");
+				exit(1);
+			}
+			if (idata & OSIOP_DCNTL_STD) {
+				fatal("osiop TODO: STD\n");
+				exit(1);
+			}
+		}
+		break;
+
+	default:
+		if (writeflag == MEM_READ) {
+			fatal("[ osiop: read from 0x%02lx ]\n",
+			    (long)relative_addr);
+		} else {
+			fatal("[ osiop: write to  0x%02lx: 0x%02x ]\n",
+			    (long)relative_addr, (int)idata);
+		}
+
+		exit(1);
+	}
+
+	if (len != 1 && !non1lenOk) {
+		fatal("[ osiop: TODO: len != 1, addr 0x%0x ]\n",
+		    (int)relative_addr);
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(osiop)
+{
+	struct osiop_data *d;
+
+	CHECK_ALLOCATION(d = (struct osiop_data *) malloc(sizeof(struct osiop_data)));
+	memset(d, 0, sizeof(struct osiop_data));
+
+	/*  Set up initial device register values:  */
+	d->reg[OSIOP_SCID] = OSIOP_SCID_VALUE(7);
+
+	/*  OpenBSD's osiop_checkintr needs this:  */
+	d->reg[OSIOP_CTEST1] = OSIOP_CTEST1_FMT;
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	memory_device_register(devinit->machine->memory, "osiop",
+	    devinit->addr, DEV_OSIOP_LENGTH,
+	    dev_osiop_access, d, DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(devinit->machine,
+	    dev_osiop_tick, d, OSIOP_TICK_SHIFT);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_osiop.cc gxemul-0.7.0+dfsg/src/devices/dev_osiop.cc
--- gxemul-0.6.2/src/devices/dev_osiop.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_osiop.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1058 +0,0 @@
-/*
- *  Copyright (C) 2008-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: NCR 53C710 SCSI I/O Processor (SIOP)
- *
- *  Based on reverse-engineering OpenBSD's osiop.c, and a PDF manual:
- *  "Symbios SYM53C710 SCSI I/O Processor Technical Manual, version 3.1".
- *
- *  See e.g. openbsd/sys/dev/microcode/siop/osiop.ss for an example of what
- *  the SCRIPTS assembly language looks like (or osiop.out for the raw result).
- *
- *
- *  TODOs:
- *
- *  o)	Target mode. Right now, only Initiator mode is implemented.
- *  o)	Errors. Right now, the emulator aborts if there is a SCSI error.
- *  o)	Allow all phases to do partial transfers. Right now, only data in
- *	and data out support this (hackish).
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "diskimage.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/osiopreg.h"
-
-
-/*  #define debug fatal  */
-const int osiop_debug = 0;
-
-static const char *phases[8] =
-	{ "DATA_OUT", "DATA_IN", "COMMAND", "STATUS",
-	  "RESERVED_OUT", "RESERVED_IN", "MSG_OUT", "MSG_IN" };
-
-#define	DEV_OSIOP_LENGTH	OSIOP_NREGS
-#define	OSIOP_CHIP_REVISION	2
-
-#define	MAX_SCRIPTS_PER_CHUNK	256	/*  256 may be a reasonable value?  */
-
-#define	OSIOP_TICK_SHIFT	17
-
-struct osiop_data {
-	struct interrupt	irq;
-	int			asserted;
-	
-	int			scripts_running;
-
-	/*  Current transfer:  */
-	int			selected_id;
-	struct scsi_transfer	*xferp;
-	size_t			data_offset;
-
-	/*  Cached emulated physical RAM page lookup:  */
-	uint32_t		last_phys_page;
-	uint8_t			*last_host_page;
-
-	/*  ALU:  */
-	int			carry;
-	
-	/*
-	 *  Most of these are byte-addressed, but some are not. (Note: For
-	 *  convenience, 32-bit words are stored in host byte order!)
-	 */
-	uint8_t			reg[OSIOP_NREGS];
-};
-
-
-static void osiop_free_xfer(struct osiop_data *d)
-{
-	if (d->xferp != NULL)
-		scsi_transfer_free(d->xferp);
-
-	d->xferp = NULL;
-}
-
-
-/*  Allocate memory for a new transfer.  */
-static void osiop_new_xfer(struct osiop_data *d, int target_scsi_id)
-{
-	if (d->xferp != NULL) {
-		fatal("WARNING! osiop_new_xfer(): freeing previous"
-		    " transfer\n");
-		osiop_free_xfer(d);
-	}
-
-	d->selected_id = target_scsi_id;
-	d->xferp = scsi_transfer_alloc();
-}
-
-
-static int osiop_get_scsi_phase(struct osiop_data *d)
-{
-	return OSIOP_PHASE(d->reg[OSIOP_SOCL]);
-}
-
-
-static void osiop_set_scsi_phase(struct osiop_data *d, int phase)
-{
-	int mask = OSIOP_MSG | OSIOP_CD | OSIOP_IO;
-	d->reg[OSIOP_SOCL] &= ~mask;
-	d->reg[OSIOP_SOCL] |= (phase & mask);
-}
-
-
-/*
- *  osiop_update_sip_and_dip():
- *
- *  The SIP bit in ISTAT is basically a "summary" of whether there is
- *  a non-masked SCSI interrupt. Similarly for DIP, for DMA.
- *
- *  However, the SIP and DIP bits are set even if interrupts are
- *  masked away using DIEN and SIEN. (At least that is how I understood
- *  things from reading OpenBSD's osiop.c osiop_poll().) 
- */
-static int osiop_update_sip_and_dip(struct osiop_data *d)
-{
-	int assert = 0;
-
-	/*  First, let's assume no interrupt assertions.  */
-	d->reg[OSIOP_ISTAT] &= ~(OSIOP_ISTAT_SIP | OSIOP_ISTAT_DIP);
-
-	/*  Any enabled SCSI interrupts?  */
-	if (d->reg[OSIOP_SSTAT0])
-		d->reg[OSIOP_ISTAT] |= OSIOP_ISTAT_SIP;
-	if (d->reg[OSIOP_SSTAT0] & d->reg[OSIOP_SIEN])
-		assert = 1;
-
-	/*  Or enabled DMA interrupts?  */
-	if (d->reg[OSIOP_DSTAT] & ~OSIOP_DIEN_RES)
-		d->reg[OSIOP_ISTAT] |= OSIOP_ISTAT_DIP;
-	if (d->reg[OSIOP_DSTAT] & d->reg[OSIOP_DIEN] & ~OSIOP_DIEN_RES)
-		assert = 1;
-
-	return assert;
-}
-
-
-/*
- *  osiop_reassert_interrupts():
- *
- *  Recalculate interrupt assertions; if either of the SIP or DIP bits
- *  in the ISTAT register is set, then we should cause an interrupt.
- *
- *  (The d->asserted stuff is to make sure we don't call INTERRUPT_DEASSERT
- *  etc. too often when not necessary. Just an optimization.)
- */
-static void osiop_reassert_interrupts(struct osiop_data *d)
-{
-	int assert = 0;
-
-	if (osiop_update_sip_and_dip(d))
-		assert = 1;
-
-	if (assert && !d->asserted)
-		INTERRUPT_ASSERT(d->irq);
-	if (!assert && d->asserted)
-		INTERRUPT_DEASSERT(d->irq);
-
-	d->asserted = assert;
-}
-
-
-/*  Helper: returns a word in host order, from emulated physical RAM.  */
-static uint32_t read_word(struct osiop_data *d, struct cpu *cpu, uint32_t addr)
-{
-	uint32_t word;
-
-	if (d->last_host_page == NULL ||
-	    d->last_phys_page != (addr & 0xfffff000)) {
-		d->last_phys_page = addr & 0xfffff000;
-		d->last_host_page =
-		    memory_paddr_to_hostaddr(cpu->mem, d->last_phys_page, 0);
-	}
-
-	word = *((uint32_t *) (d->last_host_page + (addr & 0xffc)));
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		word = LE32_TO_HOST(word);
-	else
-		word = BE32_TO_HOST(word);
-
-	return word;
-}
-
-
-/*  Helper: reads/writes single bytes from emulated physical RAM.  */
-static uint8_t read_byte(struct osiop_data *d, struct cpu *cpu, uint32_t addr)
-{
-	if (d->last_host_page == NULL ||
-	    d->last_phys_page != (addr & 0xfffff000)) {
-		d->last_phys_page = addr & 0xfffff000;
-		d->last_host_page =
-		    memory_paddr_to_hostaddr(cpu->mem, d->last_phys_page, 0);
-	}
-
-	return d->last_host_page[addr & 0xfff];
-}
-static void write_byte(struct osiop_data *d, struct cpu *cpu, uint32_t addr, uint8_t byte)
-{
-	if (d->last_host_page == NULL ||
-	    d->last_phys_page != (addr & 0xfffff000)) {
-		d->last_phys_page = addr & 0xfffff000;
-		d->last_host_page =
-		    memory_paddr_to_hostaddr(cpu->mem, d->last_phys_page, 1);
-	}
-
-	d->last_host_page[addr & 0xfff] = byte;
-}
-
-
-/*
- *  osiop_get_next_scripts_word():
- *
- *  Reads a 32-bit word at physical memory location DSP, and returns it
- *  in host order. DSP is then advanced to point to the next instruction word.
- *
- *  (NOTE/TODO: This could be optimized to read from a host page directly,
- *  but then care must be taken when the instruction pointer (DSP) goes
- *  over a page boundary to the next page. At least the page lookup
- *  could be "cached"...)
- */
-uint32_t osiop_get_next_scripts_word(struct cpu *cpu, struct osiop_data *d)
-{
-	uint32_t *dspp = (uint32_t*) &d->reg[OSIOP_DSP];
-	uint32_t dsp = *dspp;
-	uint32_t instr;
-
-	if (dsp & 3) {
-		fatal("osiop_get_next_scripts_word: unaligned DSP 0x%08x\n",
-		    dsp);
-		exit(1);
-	}
-
-	instr = read_word(d, cpu, dsp);
-
-	dsp += sizeof(instr);
-	*dspp = dsp;
-
-	return instr;
-}
-
-
-/*
- *  osiop_execute_scripts_instr():
- *
- *  Interprets a single SCRIPTS machine code instruction. Returns 1 if
- *  execution should continue, or 0 if there was an interrupt.
- *
- *  See "Symbios SYM53C710 SCSI I/O Processor Technical Manual, version 3.1"
- *  chapter 5 for details about the instruction set.
- */
-int osiop_execute_scripts_instr(struct cpu *cpu, struct osiop_data *d)
-{
-	uint32_t *dsap = (uint32_t*) &d->reg[OSIOP_DSA];
-	uint32_t *dnadp = (uint32_t*) &d->reg[OSIOP_DNAD];
-	uint32_t *dbcp = (uint32_t*) &d->reg[OSIOP_DBC];
-	uint32_t *dspsp = (uint32_t*) &d->reg[OSIOP_DSPS];
-	uint32_t *dspp = (uint32_t*) &d->reg[OSIOP_DSP];
-	uint32_t *tempp = (uint32_t*) &d->reg[OSIOP_TEMP];
-
-	uint32_t dspOrig = *dspp;
-	uint32_t instr1 = osiop_get_next_scripts_word(cpu, d);
-	uint32_t instr2 = osiop_get_next_scripts_word(cpu, d);
-	uint32_t dbc, target_addr = 0;
-	uint8_t dcmd;
-	int32_t reladdr;
-	int opcode, phase, relative_addressing, table_indirect_addressing;
-	int select_with_atn, scsi_ids_to_select = -1, scsi_id_to_select;
-	int test_carry, compare_data, compare_phase;
-	int jump_if_true, wait_for_valid_phase;
-	int comparison = 0, interrupt_instead_of_branch = 0;
-	
-	/*
-	 *  According to the 53C710 manual, chapter 5 (introduction): the first
-	 *  32-bit word is always loaded into DCMD and DBC, the second into
-	 *  DSPS, the third (only used by memory move instructions) is loaded
-	 *  into the TEMP register.
-	 */
-
-	dcmd = d->reg[OSIOP_DCMD] = instr1 >> 24;
-	dbc = *dbcp = instr1 & 0x00ffffff;
-	*dspsp = instr2;
-
-	reladdr = (instr2 << 8);
-	reladdr >>= 8;
-
-	opcode = (dcmd >> 3) & 7;
-	phase = dcmd & 7;
-
-	if (osiop_debug)
-		debug("{ SCRIPTS @ 0x%08x:  0x%08x 0x%08x",
-		    (int) dspOrig, (int) instr1, (int) instr2);
-
-	switch (dcmd & 0xc0) {
-
-	case 0x00:
-		{
-			int ofs1 = instr1 & 0x00ffffff;
-			int ofs2 = instr2 & 0x00ffffff;
-			int indirect_addressing = dcmd & 0x20;
-			uint32_t dsa = *dsap;
-			uint32_t addr, xfer_byte_count, xfer_addr;
-			int32_t tmp = ofs2 << 8;
-			int res;
-			size_t i;
-
-			tmp >>= 8;
-			table_indirect_addressing = dcmd & 0x10;
-			
-			opcode = (dcmd >> 3) & 1;
-
-			switch (opcode) {
-			case 0: if (osiop_debug)
-					debug(": CHMOV");
-				break;
-			case 1: if (osiop_debug)
-					debug(": MOVE");
-				break;
-			}
-
-			if (indirect_addressing) {
-				fatal("osiop: TODO: indirect_addressing move\n");
-				exit(1);
-			}
-
-			if (!table_indirect_addressing) {
-				fatal("osiop: TODO: !table_indirect_addressing move\n");
-				exit(1);
-			}
-			
-			if (osiop_debug)
-				debug(" FROM %i", tmp);
-			
-			if (ofs1 != ofs2) {
-				fatal("osiop: TODO: move ofs1!=ofs2\n");
-				exit(1);
-			}
-			
-			if (phase != osiop_get_scsi_phase(d)) {
-				fatal("osiop: TODO: move: wait for phase. "
-				    "phase = %i, osiop_get_scsi_phase = %i\n",
-				    phase, osiop_get_scsi_phase(d));
-				exit(1);
-			}
-
-			if (osiop_debug)			
-				debug(" WHEN %s", phases[phase]);
-
-			addr = dsa + tmp;
-			xfer_byte_count = read_word(d, cpu, addr) & 0x00ffffff;
-			xfer_addr = read_word(d, cpu, addr+4);
-
-			switch (phase) {
-
-			case MSG_OUT_PHASE:
-				scsi_transfer_allocbuf(&d->xferp->msg_out_len,
-				    &d->xferp->msg_out, xfer_byte_count, 0);
-
-				i = 0;
-				while (xfer_byte_count > 0) {
-					uint8_t byte = read_byte(d, cpu, xfer_addr);
-					/*  debug("  reading msg_out byte @ 0x%08x = 0x%02x\n",
-					    xfer_addr, byte);  */
-					d->xferp->msg_out[i++] = byte;
-					xfer_addr ++;
-					xfer_byte_count --;
-				}
-				
-				osiop_set_scsi_phase(d, COMMAND_PHASE);
-				break;
-
-			case COMMAND_PHASE:
-				scsi_transfer_allocbuf(&d->xferp->cmd_len,
-				    &d->xferp->cmd, xfer_byte_count, 0);
-
-				i = 0;
-				while (xfer_byte_count > 0) {
-					uint8_t byte = read_byte(d, cpu, xfer_addr);
-					/*  debug("  reading cmd byte @ 0x%08x = 0x%02x\n",
-					    xfer_addr, byte);  */
-					d->xferp->cmd[i++] = byte;
-					xfer_addr ++;
-					xfer_byte_count --;
-				}
-
-				res = diskimage_scsicommand(cpu,
-				    d->selected_id, DISKIMAGE_SCSI, d->xferp);
-				if (res == 0) {
-					fatal("osiop TODO: error\n");
-					exit(1);
-				}
-
-				d->data_offset = 0;
-				
-				if (res == 2)
-					osiop_set_scsi_phase(d, DATA_OUT_PHASE);
-				else if (d->xferp->data_in_len > 0)
-					osiop_set_scsi_phase(d, DATA_IN_PHASE);
-				else
-					osiop_set_scsi_phase(d, STATUS_PHASE);
-				break;
-
-			case DATA_OUT_PHASE:
-				if (d->xferp->data_out == NULL)
-					scsi_transfer_allocbuf(&d->xferp->data_out_len,
-					    &d->xferp->data_out, d->xferp->data_out_len, 0);
-
-				while (xfer_byte_count > 0) {
-					uint8_t byte = read_byte(d, cpu, xfer_addr);
-					/*  debug("  reading data_out byte @ 0x%08x = 0x%02x\n",
-					    xfer_addr, byte);  */
-					d->xferp->data_out[d->xferp->data_out_offset++] = byte;
-					xfer_addr ++;
-					xfer_byte_count --;
-				}
-
-				/*  Rerun the command to actually write out the data:  */
-				res = diskimage_scsicommand(cpu,
-				    d->selected_id, DISKIMAGE_SCSI, d->xferp);
-				if (res == 0) {
-					fatal("osiop TODO: error on rerun\n");
-					exit(1);
-				} else if (res == 2) {
-					/*  Stay at data out phase.  */
-				} else {
-					osiop_set_scsi_phase(d, STATUS_PHASE);
-				}
-				break;
-
-			case DATA_IN_PHASE:
-				i = 0;
-				while (xfer_byte_count > 0 && i + d->data_offset < d->xferp->data_in_len) {
-					uint8_t byte = d->xferp->data_in[i + d->data_offset];
-					i ++;
-					/*  debug("  writing data_in byte @ 0x%08x = 0x%02x\n",
-					    xfer_addr, byte);  */
-					write_byte(d, cpu, xfer_addr, byte);
-					xfer_addr ++;
-					xfer_byte_count --;
-				}
-
-				d->data_offset += i;
-				if (d->data_offset >= d->xferp->data_in_len)
-					osiop_set_scsi_phase(d, STATUS_PHASE);
-				break;
-
-			case STATUS_PHASE:
-				i = 0;
-				while (xfer_byte_count > 0 && i < d->xferp->status_len) {
-					uint8_t byte = d->xferp->status[i++];
-					/*  debug("  writing status byte @ 0x%08x = 0x%02x\n",
-					    xfer_addr, byte);  */
-					write_byte(d, cpu, xfer_addr, byte);
-					xfer_addr ++;
-					xfer_byte_count --;
-				}
-
-				osiop_set_scsi_phase(d, MSG_IN_PHASE);
-				break;
-
-			case MSG_IN_PHASE:
-				i = 0;
-				while (xfer_byte_count > 0 && i < d->xferp->msg_in_len) {
-					uint8_t byte = d->xferp->msg_in[i++];
-					/*  debug("  writing msg_in byte @ 0x%08x = 0x%02x\n",
-					    xfer_addr, byte);  */
-					write_byte(d, cpu, xfer_addr, byte);
-					xfer_addr ++;
-					xfer_byte_count --;
-				}
-
-				/*  Done.  */
-				osiop_free_xfer(d);
-				break;
-
-			default:fatal("osiop: TODO: unimplemented move, "
-				    "phase=%i\n", phase);
-				exit(1);
-			}
-
-			/*  Transfer complete.  */
-			*dnadp = xfer_addr;
-			*dbcp = xfer_byte_count;
-			
-			d->reg[OSIOP_DFIFO] = 0;	/*  TODO  */
-		}
-		break;
-
-	case 0x40:
-		/*  I/O or Read/Write  */
-		relative_addressing = dcmd & 4;
-		table_indirect_addressing = dcmd & 2;
-		select_with_atn = dcmd & 1;
-		scsi_ids_to_select = (dbc >> 16) & 0xff;
-
-		switch (opcode) {
-		case 0:	if (osiop_debug)
-				debug(": SELECT");
-			if (select_with_atn) {
-				if (osiop_debug)
-					debug(" ATN");
-				d->reg[OSIOP_SOCL] |= OSIOP_ATN;
-			}
-
-			if (table_indirect_addressing) {
-				uint32_t dsa = *dsap;
-				uint32_t addr, word;
-				int32_t tmp = dbc << 8;
-				tmp >>= 8;
-				addr = dsa + tmp;
-
-				if (osiop_debug)
-					debug(" FROM %i", dbc);
-
-				word = read_word(d, cpu, addr);
-				scsi_ids_to_select = (word >> 16) & 0xff;
-			}
-
-			if (scsi_ids_to_select == 0) {
-				fatal("osiop: TODO: scsi_ids_to_select = 0!\n");
-				exit(1);
-			}
-
-			scsi_id_to_select = 0;
-			while (!(scsi_ids_to_select & 1)) {
-				scsi_ids_to_select >>= 1;
-				scsi_id_to_select ++;
-			}
-
-			scsi_ids_to_select &= ~1;
-			if (scsi_ids_to_select != 0) {
-				fatal("osiop: TODO: multiselect?\n");
-				exit(1);
-			}		
-
-			if (osiop_debug)
-				debug(" [SCSI ID %i]", scsi_id_to_select);
-
-			if (relative_addressing) {
-				/*  Note: Relative to _current_ DSP value, not
-				    what the DSP was when the current
-				    instruction was read!  */
-				target_addr = reladdr + *dspp;
-				if (osiop_debug)
-					debug(" REL(%i)", reladdr);
-			} else {
-				target_addr = instr2;
-				if (osiop_debug)
-					debug(" 0x%08x", instr2);
-			}
-
-			if (diskimage_exist(cpu->machine,
-			    scsi_id_to_select, DISKIMAGE_SCSI)) {
-				osiop_new_xfer(d, scsi_id_to_select);
-
-				/*  TODO: Just a guess, so far:  */
-				osiop_set_scsi_phase(d, MSG_OUT_PHASE);
-			} else {
-				d->selected_id = -1;
-
-#if 1
-				/*  TODO: The scsi ID does not exist.
-				    Should we simply timeout:  */
-				d->scripts_running = 0;
-#else
-				/*  or branch to the reselect address?  */
-				*(uint32_t*) &d->reg[OSIOP_DSP] = target_addr;
-#endif
-			}
-
-			break;
-			
-		case 1:	if (osiop_debug)
-				debug(": WAIT DISCONNECT");
-			/*  TODO  */
-			break;
-		case 2:	if (osiop_debug)
-				debug(": WAIT RESELECT");
-			fatal("osiop: TODO: wait reselect\n");
-			exit(1);
-			break;
-	
-		case 3:	if (osiop_debug)
-				debug(": SET");
-			break;
-		case 4:	if (osiop_debug)
-				debug(": CLEAR");
-			break;
-
-		default:fatal(": UNIMPLEMENTED dcmd=0x%02x opcode=%i\n",
-			    dcmd, opcode);
-			exit(1);
-		}
-
-		/*  SET or CLEAR:  */
-		if (opcode == 3 || opcode == 4) {
-			int bit_atn = (dbc >> 3) & 1;
-			int bit_ack = (dbc >> 6) & 1;
-			int bit_target = (dbc >> 9) & 1;
-			int bit_carry = (dbc >> 10) & 1;
-
-			if (osiop_debug) {
-				if (bit_atn)
-					debug(" ATN");
-				if (bit_ack)
-					debug(" ACK");
-				if (bit_target)
-					debug(" TARGET");
-				if (bit_carry)
-					debug(" CARRY");
-			}
-					
-			if (opcode == 3) {
-				d->reg[OSIOP_SOCL] |= (bit_ack * OSIOP_ACK);
-				d->reg[OSIOP_SOCL] |= (bit_atn * OSIOP_ATN);
-				if (bit_carry)
-					d->carry = 1;
-				d->reg[OSIOP_SCNTL0] |=
-				    (bit_target * OSIOP_SCNTL0_TRG);
-			} else {
-				d->reg[OSIOP_SOCL] &= ~(bit_ack * OSIOP_ACK);
-				d->reg[OSIOP_SOCL] &= ~(bit_atn * OSIOP_ATN);
-				if (bit_carry)
-					d->carry = 0;
-				d->reg[OSIOP_SCNTL0] &=
-				    ~(bit_target * OSIOP_SCNTL0_TRG);
-			}
-		}
-
-		break;
-
-	case 0x80:
-		/*  Transfer Control  */
-		relative_addressing = (dbc >> 23) & 1;
-		test_carry = (dbc >> 21) & 1;
-		jump_if_true = (dbc >> 19) & 1;
-		compare_data = (dbc >> 18) & 1;
-		compare_phase = (dbc >> 17) & 1;
-		wait_for_valid_phase = (dbc >> 16) & 1;
-		
-		switch (opcode) {
-		case 0:	if (osiop_debug)
-				debug(": JUMP");
-			break;
-		case 1:	if (osiop_debug)
-				debug(": CALL");
-			break;
-		case 2:	if (osiop_debug)
-				debug(": RETURN");
-			break;
-		case 3:	if (osiop_debug)
-				debug(": INTERRUPT");
-			break;
-		default:fatal(": UNIMPLEMENTED dcmd=0x%02x opcode=%i\n",
-			    dcmd, opcode);
-			exit(1);
-		}
-
-		if (opcode == 0 || opcode == 1) {
-			if (relative_addressing) {
-				/*  Note: Relative to _current_ DSP value,
-				    not what it was when the current instruction
-				    was read!  */
-				target_addr = reladdr + *dspp;
-				if (osiop_debug)
-					debug(" REL(%i)", reladdr);
-			} else {
-				target_addr = instr2;
-				if (osiop_debug)
-					debug(" 0x%08x", instr2);
-			}
-		} else {
-			if (opcode == 2) {
-				/*  Return:  */
-				target_addr = *tempp;
-			} else {
-				/*  Interrupt:  */
-				interrupt_instead_of_branch = 1;
-			}
-		}
-
-		if (test_carry) {
-			if (compare_data || compare_phase) {
-				fatal("osiop: TODO: test_carry cannot be"
-				    " combined with other tests!\n");
-				exit(1);
-			}
-			
-			fatal("osiop: TODO: test_carry\n");
-			exit(1);
-		}
-
-		if (compare_data) {
-			fatal("osiop: TODO: compare_data\n");
-			exit(1);
-		}
-
-		if (compare_phase) {
-			int cur_phase;
-
-			if (osiop_debug)
-				debug(" %s %s%s",
-				    wait_for_valid_phase ? "WHEN" : "IF",
-				    jump_if_true? "" : "NOT ",
-				    phases[phase]);
-
-			/*  TODO: wait for valid phase!  */
-
-			cur_phase = osiop_get_scsi_phase(d);
-			
-			comparison = (phase == cur_phase);
-		}
-
-		if (!test_carry && !compare_data && !compare_phase)
-			jump_if_true = comparison = 1;
-
-		if ((jump_if_true && comparison) ||
-		    (!jump_if_true && !comparison)) {
-			/*  Perform the branch or interrupt.  */
-			if (interrupt_instead_of_branch) {
-				d->scripts_running = 0;
-				d->reg[OSIOP_DSTAT] |= OSIOP_DSTAT_SIR;
-			} else {
-				*dspp = target_addr;
-			}
-		}
-
-		break;
-
-	case 0xc0:
-		if (osiop_debug)
-			debug(": MEMORY MOVE");
-		/*  TODO: third instruction word!  */
-		fatal(": TODO\n");
-		exit(1);
-		break;
-
-	default:fatal(": UNIMPLEMENTED dcmd 0x%02x\n", dcmd);
-		exit(1);
-	}
-
-	if (osiop_debug)
-		debug(" }\n");
-
-	return 1;
-}
-
-
-/*
- *  osiop_execute_scripts():
- *
- *  Interprets SCRIPTS machine code by reading one instruction word at a time,
- *  and executing it.
- */
-void osiop_execute_scripts(struct cpu *cpu, struct osiop_data *d)
-{
-	int n = 0;
-
-	if (osiop_debug)
-		debug("{ SCRIPTS start }\n");
-
-	while (d->scripts_running && n < MAX_SCRIPTS_PER_CHUNK &&
-	    osiop_execute_scripts_instr(cpu, d))
-		n++;
-
-	if (osiop_debug)	
-		debug("{ SCRIPTS end }\n");
-}
-
-
-DEVICE_TICK(osiop)
-{
-	struct osiop_data *d = (struct osiop_data *) extra;
-
-	if (d->scripts_running)
-		osiop_execute_scripts(cpu, d);
-
-	osiop_reassert_interrupts(d);
-}
-
-
-DEVICE_ACCESS(osiop)
-{
-	uint64_t idata = 0, odata = 0;
-	uint8_t oldreg = 0;
-	struct osiop_data *d = (struct osiop_data *) extra;
-	int origofs = relative_addr;
-	int non1lenOk = 0;
-
-	idata = memory_readmax64(cpu, data, len);
-
-	/*  Make relative_addr suit addresses in osiopreg.h:  */
-	if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-		relative_addr =
-		    (relative_addr & ~3) |
-		    (3 - (relative_addr & 3));
-	}
-
-	if (len == sizeof(uint32_t)) {
-		/*
-		 *  NOTE: These are stored in HOST byte order!
-		 */
-		switch (origofs) {
-		case OSIOP_DSA:
-		case OSIOP_TEMP:
-		case OSIOP_DBC:
-		case OSIOP_DNAD:
-		case OSIOP_DSP:
-		case OSIOP_DSPS:
-		case OSIOP_SCRATCH:
-		case OSIOP_ADDER:
-			relative_addr = origofs;
-			non1lenOk = 1;
-
-			uint32_t *p = (uint32_t*) &d->reg[origofs];
-
-			if (writeflag == MEM_WRITE)
-				*p = idata;
-			else
-				odata = *p;
-			
-			break;
-		}
-	} else {
-		/*  Byte access:  */
-		oldreg = d->reg[relative_addr];
-
-		if (writeflag == MEM_WRITE)
-			d->reg[relative_addr] = idata;
-		else
-			odata = oldreg;
-	}
-
-	switch (relative_addr) {
-
-	case OSIOP_SCNTL0:
-	case OSIOP_SCNTL1:
-		break;
-
-	case OSIOP_SIEN:
-		/*  Used by OpenBSD/mvme88k during probing:  */
-		if (len == 4)
-			non1lenOk = 1;
-		if (writeflag == MEM_WRITE)
-			osiop_reassert_interrupts(d);
-		break;
-
-	case OSIOP_SCID:
-		if (idata != oldreg) {
-			fatal("osiop TODO: attempt to change SCID?\n");
-			exit(1);
-		}
-		break;
-
-	case OSIOP_SBDL:
-		if (writeflag == MEM_WRITE)
-			fatal("[ osiop: SBDL set to 0x%x, but should be "
-			    "read-only! ]\n", (int) idata);
-		break;
-
-	case OSIOP_SBCL:
-		if (writeflag == MEM_WRITE) {
-			if (osiop_debug)
-				debug("[ osiop: SBCL set to 0x%x ]\n", (int) idata);
-		}
-		break;
-
-	case OSIOP_DSTAT:
-		/*  Cleared when read. Most likely not writable.  */
-		odata = d->reg[OSIOP_DSTAT];
-		d->reg[OSIOP_DSTAT] = OSIOP_DSTAT_DFE;
-		osiop_reassert_interrupts(d);
-		break;
-
-	case OSIOP_SSTAT0:
-		/*  Cleared when read. Most likely not writable.  */
-		odata = d->reg[OSIOP_SSTAT0];
-		d->reg[OSIOP_SSTAT0] = 0;
-		osiop_reassert_interrupts(d);
-		break;
-
-	case OSIOP_SSTAT1:
-	case OSIOP_SSTAT2:
-		break;
-		
-	case OSIOP_DSA:
-		if (writeflag == MEM_WRITE) {
-			if (osiop_debug)
-				debug("[ osiop: DSA set to 0x%x ]\n", (int) idata);
-		}
-		break;
-
-	case OSIOP_CTEST0:
-	case OSIOP_CTEST1:
-	case OSIOP_CTEST2:
-	case OSIOP_CTEST3:
-	case OSIOP_CTEST4:
-	case OSIOP_CTEST5:
-	case OSIOP_CTEST6:
-	case OSIOP_CTEST7:
-		break;
-
-	case OSIOP_TEMP:
-		if (writeflag == MEM_WRITE) {
-			if (osiop_debug)
-				debug("[ osiop: TEMP set to 0x%x ]\n", (int) idata);
-		}
-		break;
-
-	case OSIOP_DFIFO:
-		break;
-
-	case OSIOP_ISTAT:
-		if (writeflag == MEM_WRITE) {
-			if ((idata & 0x3f) != 0x00) {
-				fatal("osiop TODO: istat 0x%x\n", (int) idata);
-				exit(1);
-			}
-
-			d->reg[relative_addr] = idata &
-			    ~(OSIOP_ISTAT_ABRT | OSIOP_ISTAT_RST);
-			osiop_reassert_interrupts(d);
-		}
-		break;
-
-	case OSIOP_CTEST8:
-		odata = (odata & 0xf) | (OSIOP_CHIP_REVISION << 4);
-		break;
-
-	case OSIOP_DBC:
-		break;
-
-	case OSIOP_DSP:
-		if (writeflag == MEM_WRITE) {
-			if (osiop_debug)
-				debug("[ osiop: DSP set to 0x%x ]\n", (int) idata);
-
-			d->scripts_running = 1;
-			osiop_execute_scripts(cpu, d);
-			osiop_reassert_interrupts(d);
-		}
-		break;
-
-	case OSIOP_DSPS:
-	case OSIOP_SCRATCH:
-		break;
-
-	case OSIOP_DMODE:
-		break;
-
-	case OSIOP_DIEN:
-		if (writeflag == MEM_WRITE)
-			osiop_reassert_interrupts(d);
-		break;
-
-	case OSIOP_DWT:
-		break;
-
-	case OSIOP_DCNTL:
-		if (writeflag == MEM_WRITE) {
-			if (idata & OSIOP_DCNTL_SSM) {
-				fatal("osiop TODO: SSM\n");
-				exit(1);
-			}
-			if (idata & OSIOP_DCNTL_LLM) {
-				fatal("osiop TODO: LLM\n");
-				exit(1);
-			}
-			if (idata & OSIOP_DCNTL_STD) {
-				fatal("osiop TODO: STD\n");
-				exit(1);
-			}
-		}
-		break;
-
-	default:
-		if (writeflag == MEM_READ) {
-			fatal("[ osiop: read from 0x%02lx ]\n",
-			    (long)relative_addr);
-		} else {
-			fatal("[ osiop: write to  0x%02lx: 0x%02x ]\n",
-			    (long)relative_addr, (int)idata);
-		}
-
-		exit(1);
-	}
-
-	if (len != 1 && !non1lenOk) {
-		fatal("[ osiop: TODO: len != 1, addr 0x%0x ]\n",
-		    (int)relative_addr);
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(osiop)
-{
-	struct osiop_data *d;
-
-	CHECK_ALLOCATION(d = (struct osiop_data *) malloc(sizeof(struct osiop_data)));
-	memset(d, 0, sizeof(struct osiop_data));
-
-	/*  Set up initial device register values:  */
-	d->reg[OSIOP_SCID] = OSIOP_SCID_VALUE(7);
-
-	/*  OpenBSD's osiop_checkintr needs this:  */
-	d->reg[OSIOP_CTEST1] = OSIOP_CTEST1_FMT;
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	memory_device_register(devinit->machine->memory, "osiop",
-	    devinit->addr, DEV_OSIOP_LENGTH,
-	    dev_osiop_access, d, DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(devinit->machine,
-	    dev_osiop_tick, d, OSIOP_TICK_SHIFT);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_palmbus.c gxemul-0.7.0+dfsg/src/devices/dev_palmbus.c
--- gxemul-0.6.2/src/devices/dev_palmbus.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_palmbus.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,121 @@
+/*
+ *  Copyright (C) 2018-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: VoCore Palmbus
+ *
+ *  TODO
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "console.h"
+#include "device.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	DEV_PALMBUS_LENGTH		0x1000
+
+struct palmbus_data {
+	// struct interrupt irq;
+	int console_handle;
+};
+
+
+DEVICE_ACCESS(palmbus)
+{
+	struct palmbus_data *d = (struct palmbus_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case 0x0000:
+		odata = 0x30335452;
+		break;
+	
+	case 0x0004:
+		odata = 0x20203235;
+		break;
+
+	case 0x000c:
+		/*  Linux boot message says "SoC Type: Ralink RT5350 id:1 rev:3"  */
+		odata = 0x00000103;
+		break;
+
+	case 0x0c04:
+		console_putchar(d->console_handle, idata);
+		break;
+
+	case 0x0c1c:
+		odata = 0x20;	// Serial ready (?)
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ palmbus: unimplemented write to address 0x%x"
+			    ", data=0x%02x ]\n",
+			    (int)relative_addr, (int)idata);
+		} else {
+			fatal("[ palmbus: unimplemented read from address 0x%x "
+			    "]\n", (int)relative_addr);
+		}
+		/*  exit(1);  */
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(palmbus)
+{
+	struct palmbus_data *d;
+
+	CHECK_ALLOCATION(d = (struct palmbus_data *) malloc(sizeof(struct palmbus_data)));
+	memset(d, 0, sizeof(struct palmbus_data));
+
+	// INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	d->console_handle = console_start_slave(devinit->machine, "uartlite", 1);
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_PALMBUS_LENGTH,
+	    dev_palmbus_access, (void *)d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_palmbus.cc gxemul-0.7.0+dfsg/src/devices/dev_palmbus.cc
--- gxemul-0.6.2/src/devices/dev_palmbus.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_palmbus.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,122 +0,0 @@
-/*
- *  Copyright (C) 2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: VoCore Palmbus
- *
- *  TODO
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "console.h"
-#include "device.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define	DEV_PALMBUS_LENGTH		0x1000
-
-struct palmbus_data {
-	// struct interrupt irq;
-	int console_handle;
-};
-
-
-DEVICE_ACCESS(palmbus)
-{
-	struct palmbus_data *d = (struct palmbus_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case 0x0000:
-		odata = 0x30335452;
-		break;
-	
-	case 0x0004:
-		odata = 0x20203235;
-		break;
-
-	case 0x000c:
-		/*  Linux boot message says "SoC Type: Ralink RT5350 id:1 rev:3"  */
-		odata = 0x00000103;
-		break;
-
-	case 0x0c04:
-		console_putchar(d->console_handle, idata);
-		break;
-
-	case 0x0c1c:
-		odata = 0x20;	// Serial ready (?)
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ palmbus: unimplemented write to address 0x%x"
-			    ", data=0x%02x ]\n",
-			    (int)relative_addr, (int)idata);
-		} else {
-			fatal("[ palmbus: unimplemented read from address 0x%x "
-			    "]\n", (int)relative_addr);
-		}
-		/*  exit(1);  */
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(palmbus)
-{
-	char *name2;
-	struct palmbus_data *d;
-
-	CHECK_ALLOCATION(d = (struct palmbus_data *) malloc(sizeof(struct palmbus_data)));
-	memset(d, 0, sizeof(struct palmbus_data));
-
-	// INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	d->console_handle = console_start_slave(devinit->machine, "uartlite", 1);
-
-	memory_device_register(devinit->machine->memory, name2,
-	    devinit->addr, DEV_PALMBUS_LENGTH,
-	    dev_palmbus_access, (void *)d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_pcc2.c gxemul-0.7.0+dfsg/src/devices/dev_pcc2.c
--- gxemul-0.6.2/src/devices/dev_pcc2.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pcc2.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,649 @@
+/*
+ *  Copyright (C) 2007-2014  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Peripheral Channel Controller (PCC2) bus (used in MVME machines)
+ *
+ *  See "Single Board Computers Programmer's Reference Guide (Part 2 of 2)",
+ *  "VMESBCA2/PG1" (vmesbcp2.pdf) for more details.
+ *
+ *  Note: This is somewhat MVME187-specific, at the moment.
+ *
+ *  Implemented so far:
+ *	Timers 1 and 2.
+ *	The interrupt controller mechanism (partially!)
+ *
+ *  TODO:
+ *	All devices appart from the timers.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/mvme187.h"
+#include "thirdparty/mvme_pcctworeg.h"
+
+
+#define	INTERRUPT_LEVEL_MASK	0x07
+
+#define	PCC_TIMER_TICK_HZ	100.0
+#define DEV_PCC2_TICK_SHIFT	14
+
+
+// #define	debug fatal
+
+struct pcc2_data {
+	struct interrupt	cpu_irq;
+
+	uint8_t			pcctwo_reg[PCC2_SIZE];
+
+	uint8_t			cur_int_vec[8];
+
+	/*  Timers:  */
+	struct timer		*timer;
+	int			pending_timer1_interrupts;
+	int			pending_timer2_interrupts;
+};
+
+
+static uint32_t read32(unsigned char *p)
+{
+	uint32_t x = 0;
+	size_t i;
+
+	for (i=0; i<sizeof(x); i++) {
+		x <<= 8;
+		x |= p[i];
+	}
+
+	return x;
+}
+
+
+static void write32(unsigned char *p, uint32_t x)
+{
+	size_t i;
+
+	for (i=0; i<sizeof(x); i++) {
+		p[sizeof(x) - 1 - i] = x;
+		x >>= 8;
+	}
+}
+
+
+static void pcc_timer_tick(struct timer *t, void *extra)
+{
+	struct pcc2_data *d = (struct pcc2_data *) extra;
+
+	/*  The PCC2 timers run at 1 MHz.  */
+	int steps = (int) (1000000.0 / PCC_TIMER_TICK_HZ);
+
+	uint32_t count1, count2, compare1, compare2;
+	int interrupt1 = 0, interrupt2 = 0;
+
+	/*  Read values:  */
+	count1 = read32(&d->pcctwo_reg[PCCTWO_T1COUNT]);
+	count2 = read32(&d->pcctwo_reg[PCCTWO_T2COUNT]);
+	compare1 = read32(&d->pcctwo_reg[PCCTWO_T1CMP]);
+	compare2 = read32(&d->pcctwo_reg[PCCTWO_T2CMP]);
+
+	/*  Timer enabled? Then count...  */
+	if (d->pcctwo_reg[PCCTWO_T1CTL] & PCC2_TCTL_CEN) {
+		uint32_t old_count1 = count1;
+		count1 += steps;
+
+		/*  Did we pass the compare value?  */
+		if ((old_count1 < compare1 && count1 >= compare1) ||
+		    (old_count1 < compare1 && count1 < old_count1)) {
+			interrupt1 = 1;
+
+			if (d->pcctwo_reg[PCCTWO_T1CTL] & PCC2_TCTL_COC) {
+				while (count1 >= compare1) {
+					count1 -= compare1;
+					interrupt1 ++;
+				}
+				interrupt1 --;
+			}
+		}
+
+		/*  Overflow?  */
+		if ((int32_t) old_count1 >= 0 && (int32_t) count1 < 0) {
+			int oc = 1 + (d->pcctwo_reg[PCCTWO_T1CTL] >> 4);
+			d->pcctwo_reg[PCCTWO_T1CTL] &= ~PCC2_TCTL_OVF;
+			d->pcctwo_reg[PCCTWO_T1CTL] |= (oc << 4);
+		}
+	}
+
+	/*  ... and the same for timer 2:  */
+	if (d->pcctwo_reg[PCCTWO_T2CTL] & PCC2_TCTL_CEN) {
+		uint32_t old_count2 = count2;
+		count2 += steps;
+
+		if ((old_count2 < compare2 && count2 >= compare2) ||
+		    (old_count2 < compare2 && count2 < old_count2)) {
+			interrupt2 = 1;
+			if (d->pcctwo_reg[PCCTWO_T2CTL] & PCC2_TCTL_COC) {
+				while (count2 >= compare2) {
+					count2 -= compare2;
+					interrupt2 ++;
+				}
+				interrupt2 --;
+			}
+		}
+
+		if ((int32_t) old_count2 >= 0 && (int32_t) count2 < 0) {
+			int oc = 1 + (d->pcctwo_reg[PCCTWO_T2CTL] >> 4);
+			d->pcctwo_reg[PCCTWO_T2CTL] &= ~PCC2_TCTL_OVF;
+			d->pcctwo_reg[PCCTWO_T2CTL] |= (oc << 4);
+		}
+	}
+
+	/*  Should we cause interrupts?  */
+	if (interrupt1 && d->pcctwo_reg[PCCTWO_T1ICR] & PCC2_TTIRQ_IEN)
+		d->pending_timer1_interrupts += interrupt1;
+	if (interrupt2 && d->pcctwo_reg[PCCTWO_T2ICR] & PCC2_TTIRQ_IEN)
+		d->pending_timer2_interrupts += interrupt2;
+
+	/*  Write back values:  */
+	write32(&d->pcctwo_reg[PCCTWO_T1COUNT], count1);
+	write32(&d->pcctwo_reg[PCCTWO_T2COUNT], count2);
+}
+
+
+static void reassert_interrupts(struct pcc2_data *d)
+{
+	int assert = 0;
+
+	if (d->pcctwo_reg[PCCTWO_GENCTL] & PCC2_C040) {
+		/*  The M68000 interrupt mechanism involves outputting
+		    interrupt level on pins EIPL<2..0>. Not implemented
+		    yet.  */
+		fatal("pcc2: C040 interrupt assertions... TODO\n");
+		exit(1);
+	}
+
+	/*
+	 *  Recalculate current interrupt level:
+	 */
+	d->pcctwo_reg[PCCTWO_IPL] = 0;
+
+	/*  Timer interrupts?  */
+	if (d->pending_timer1_interrupts > 0 &&
+	    d->pcctwo_reg[PCCTWO_T1ICR] & PCC2_TTIRQ_IEN)
+		d->pcctwo_reg[PCCTWO_T1ICR] |= PCC2_TTIRQ_INT;
+	if (d->pending_timer2_interrupts > 0 &&
+	    d->pcctwo_reg[PCCTWO_T2ICR] & PCC2_TTIRQ_IEN)
+		d->pcctwo_reg[PCCTWO_T2ICR] |= PCC2_TTIRQ_INT;
+
+	if (d->pcctwo_reg[PCCTWO_T1ICR] & PCC2_TTIRQ_INT) {
+		int intlevel = d->pcctwo_reg[PCCTWO_T1ICR] & PCC2_TTIRQ_IL;
+		d->cur_int_vec[intlevel] = PCC2V_TIMER1;
+		if (d->pcctwo_reg[PCCTWO_IPL] < intlevel)
+			d->pcctwo_reg[PCCTWO_IPL] = intlevel;
+	}
+	if (d->pcctwo_reg[PCCTWO_T2ICR] & PCC2_TTIRQ_INT) {
+		int intlevel = d->pcctwo_reg[PCCTWO_T2ICR] & PCC2_TTIRQ_IL;
+		d->cur_int_vec[intlevel] = PCC2V_TIMER2;
+		if (d->pcctwo_reg[PCCTWO_IPL] < intlevel)
+			d->pcctwo_reg[PCCTWO_IPL] = intlevel;
+	}
+
+	if (d->pcctwo_reg[PCCTWO_SCCTX] & PCC2_IRQ_IEN &&
+	    d->pcctwo_reg[PCCTWO_SCCTX] & PCC2_IRQ_INT) {
+		int intlevel = d->pcctwo_reg[PCCTWO_SCCTX] & PCC2_IRQ_IPL;
+		d->cur_int_vec[intlevel] = PCC2V_SCC_TX;
+		if (d->pcctwo_reg[PCCTWO_IPL] < intlevel)
+			d->pcctwo_reg[PCCTWO_IPL] = intlevel;
+	}
+
+	if (d->pcctwo_reg[PCCTWO_SCCRX] & PCC2_IRQ_IEN &&
+	    d->pcctwo_reg[PCCTWO_SCCRX] & PCC2_IRQ_INT) {
+		int intlevel = d->pcctwo_reg[PCCTWO_SCCRX] & PCC2_IRQ_IPL;
+		d->cur_int_vec[intlevel] = PCC2V_SCC_RX;
+		if (d->pcctwo_reg[PCCTWO_IPL] < intlevel)
+			d->pcctwo_reg[PCCTWO_IPL] = intlevel;
+	}
+
+	if (d->pcctwo_reg[PCCTWO_SCSIICR] & PCC2_IRQ_IEN &&
+	    d->pcctwo_reg[PCCTWO_SCSIICR] & PCC2_IRQ_INT) {
+		int intlevel = d->pcctwo_reg[PCCTWO_SCSIICR] & PCC2_IRQ_IPL;
+		d->cur_int_vec[intlevel] = PCC2V_SCSI;
+		if (d->pcctwo_reg[PCCTWO_IPL] < intlevel)
+			d->pcctwo_reg[PCCTWO_IPL] = intlevel;
+	}
+
+	/*  TODO: Other interrupt sources.  */
+
+	/*  Assert interrupt on the CPU if the IPL is higher than the mask:  */
+	if ((d->pcctwo_reg[PCCTWO_IPL] & INTERRUPT_LEVEL_MASK) >
+	    (d->pcctwo_reg[PCCTWO_MASK] & INTERRUPT_LEVEL_MASK))
+		assert = 1;
+
+	debug("[ pcc2: IPL = %i, MASK = %i => %s ]\n", d->pcctwo_reg[PCCTWO_IPL]& INTERRUPT_LEVEL_MASK,
+		d->pcctwo_reg[PCCTWO_MASK] & INTERRUPT_LEVEL_MASK,
+		assert ? "ASSERT" : "no assert");
+
+	/*  ... but only allow interrupts if Master Interrupt Enable is on:  */
+	if (!(d->pcctwo_reg[PCCTWO_GENCTL] & PCC2_MIEN))
+		assert = 0;
+
+	if (assert)
+		INTERRUPT_ASSERT(d->cpu_irq);
+	else
+		INTERRUPT_DEASSERT(d->cpu_irq);
+}
+
+
+void pcctwo_interrupt_common(struct interrupt *interrupt, int assert)
+{
+	struct pcc2_data *d = (struct pcc2_data *) interrupt->extra;
+
+	switch (interrupt->line) {
+
+	case PCC2V_SCSI:
+		if (assert)
+			d->pcctwo_reg[PCCTWO_SCSIICR] |= PCC2_IRQ_INT;
+		else
+			d->pcctwo_reg[PCCTWO_SCSIICR] &= ~PCC2_IRQ_INT;
+		break;
+
+	case PCC2V_SCC_TX:
+		if (assert)
+			d->pcctwo_reg[PCCTWO_SCCTX] |= PCC2_IRQ_INT;
+		else
+			d->pcctwo_reg[PCCTWO_SCCTX] &= ~PCC2_IRQ_INT;
+		break;
+
+	case PCC2V_SCC_RX:
+		if (assert)
+			d->pcctwo_reg[PCCTWO_SCCRX] |= PCC2_IRQ_INT;
+		else
+			d->pcctwo_reg[PCCTWO_SCCRX] &= ~PCC2_IRQ_INT;
+		break;
+
+	default:fatal("[ pcctwo_interrupt_common: TODO: line = %i ]\n",
+		    interrupt->line);
+		exit(1);
+	}
+
+	reassert_interrupts(d);
+}
+
+
+static void pcctwo_interrupt_assert(struct interrupt *interrupt)
+{
+	pcctwo_interrupt_common(interrupt, 1);
+}
+static void pcctwo_interrupt_deassert(struct interrupt *interrupt)
+{
+	pcctwo_interrupt_common(interrupt, 0);
+}
+
+
+DEVICE_TICK(pcc2)
+{
+	struct pcc2_data *d = (struct pcc2_data *) extra;
+	reassert_interrupts(d);
+}
+
+
+DEVICE_ACCESS(pcc2)
+{
+	uint64_t idata = 0;
+	struct pcc2_data *d = (struct pcc2_data *) extra;
+
+	/*  0xfff42000..0xfff42fff, but only 0x40 unique registers:  */
+	relative_addr %= PCC2_SIZE;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (writeflag == MEM_READ)
+		memcpy(data, d->pcctwo_reg + relative_addr, len);
+
+	switch (relative_addr) {
+
+	case PCCTWO_CHIPID:
+	case PCCTWO_CHIPREV:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ IGNORING write to read-only PCCTWO_CHIPID/"
+			    "CHIPREV register ]\n");
+		}
+		break;
+
+	case PCCTWO_GENCTL:
+		if (len != 1) {
+			fatal("TODO: pcc2: non-byte reads and writes of "
+			    "PCCTWO_GENCTL\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE) {
+			d->pcctwo_reg[relative_addr] = idata;
+			reassert_interrupts(d);
+		}
+		break;
+
+	case PCCTWO_VECBASE:
+		if (len != 1) {
+			fatal("TODO: pcc2: non-byte reads and writes of "
+			    "PCCTWO_VECBASE\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE) {
+			d->pcctwo_reg[relative_addr] = idata & 0xf0;
+			if (idata & ~0xf0)
+				fatal("[ pcc2: HUH? write to PCCTWO_VECBASE"
+				    " with value 0x%02x. ]\n", (int) idata);
+		}
+		break;
+
+	case PCCTWO_T1CMP:
+	case PCCTWO_T2CMP:
+	case PCCTWO_T1COUNT:
+	case PCCTWO_T2COUNT:
+		if (writeflag == MEM_WRITE)
+			memcpy(d->pcctwo_reg + relative_addr, data, len);
+		break;
+
+	case PCCTWO_PSCALEADJ:
+		if (len != 1) {
+			fatal("TODO: pcc2: non-byte reads and writes of "
+			    "PCCTWO_PSCALEADJ\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE) {
+			fatal("[ pcc2: write to PSCALEADJ ignored (value "
+			    "0x%02x) ]\n", (int)idata);
+		}
+		break;
+
+	case PCCTWO_T2CTL:
+	case PCCTWO_T1CTL:
+		if (len != 1) {
+			fatal("TODO: pcc2: non-byte reads and writes of "
+			    "PCCTWO_TxCTL\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE) {
+			/*  PCC2_TCTL_CEN and PCC2_TCTL_COC:  */
+			d->pcctwo_reg[relative_addr] &= 0xfc;
+			d->pcctwo_reg[relative_addr] |= (idata & 3);
+
+			if (idata & PCC2_TCTL_COVF)
+				d->pcctwo_reg[relative_addr] &=
+				    ~(PCC2_TCTL_OVF | PCC2_TCTL_COVF);
+
+			if (idata & ~7)
+				fatal("[ pcc2: HUH? write to PCCTWO_TxCTL"
+				    " with value 0x%02x. ]\n", (int) idata);
+		}
+		break;
+
+	case PCCTWO_T2ICR:
+	case PCCTWO_T1ICR:
+		if (len != 1) {
+			fatal("TODO: pcc2: non-byte reads and writes of "
+			    "PCCTWO_TxICR\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE) {
+			d->pcctwo_reg[relative_addr] &= ~0x17;
+			d->pcctwo_reg[relative_addr] |= (idata & 0x17);
+
+			if (relative_addr == PCCTWO_T1ICR &&
+			    !(idata & PCC2_TTIRQ_IEN))
+				d->pending_timer1_interrupts = 0;
+			if (relative_addr == PCCTWO_T2ICR &&
+			    !(idata & PCC2_TTIRQ_IEN))
+				d->pending_timer2_interrupts = 0;
+
+			if (relative_addr == PCCTWO_T1ICR && (idata & PCC2_TTIRQ_ICLR)
+			    && d->pcctwo_reg[relative_addr] & PCC2_TTIRQ_INT
+			    && d->pending_timer1_interrupts > 0)
+				d->pending_timer1_interrupts --;
+
+			if (relative_addr == PCCTWO_T2ICR && (idata & PCC2_TTIRQ_ICLR)
+			    && d->pcctwo_reg[relative_addr] & PCC2_TTIRQ_INT
+			    && d->pending_timer2_interrupts > 0)
+				d->pending_timer2_interrupts --;
+
+			if (idata & PCC2_TTIRQ_ICLR)
+				d->pcctwo_reg[relative_addr] &= ~PCC2_TTIRQ_INT;
+
+			if (idata & 0xe0)
+				fatal("[ pcc2: HUH? write to PCCTWO_TxICR"
+				    " with value 0x%02x. ]\n", (int) idata);
+
+			reassert_interrupts(d);
+		}
+		break;
+
+	case PCCTWO_SCCERR:
+		if (len != 1) {
+			fatal("TODO: pcc2: non-byte reads and writes of "
+			    "PCCTWO_SCCERR\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE)
+			d->pcctwo_reg[relative_addr] = 0;	/*  clear  */
+		break;
+
+	case PCCTWO_SCCICR:
+		if (len != 1) {
+			fatal("TODO: pcc2: non-byte reads and writes of "
+			    "PCCTWO_SCCICR\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE) {
+			d->pcctwo_reg[relative_addr] = idata & 0x1f;
+			if (idata & ~0x1f)
+				fatal("[ pcc2: HUH? write to PCCTWO_SCCICR"
+				    " with value 0x%02x. ]\n", (int) idata);
+			reassert_interrupts(d);
+		}
+		break;
+
+	case PCCTWO_SCCTX:
+		if (len != 1) {
+			fatal("TODO: pcc2: non-byte reads and writes of "
+			    "PCCTWO_SCCTX\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE) {
+			d->pcctwo_reg[relative_addr] = idata & 0x1f;
+			if (idata & ~0x1f)
+				fatal("[ pcc2: HUH? write to PCCTWO_SCCTX"
+				    " with value 0x%02x. ]\n", (int) idata);
+			reassert_interrupts(d);
+		}
+		break;
+
+	case PCCTWO_SCCRX:
+		if (len != 1) {
+			fatal("TODO: pcc2: non-byte reads and writes of "
+			    "PCCTWO_SCCRX\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE) {
+			d->pcctwo_reg[relative_addr] = idata & 0xdf;
+			if (idata & ~0xdf)
+				fatal("[ pcc2: HUH? write to PCCTWO_SCCRX"
+				    " with value 0x%02x. ]\n", (int) idata);
+			reassert_interrupts(d);
+		}
+		break;
+
+	case PCCTWO_SCCRXIACK:
+		/*  TODO. Hm. Is this enough?  */
+		d->pcctwo_reg[PCCTWO_SCCRX] &= ~PCC2_IRQ_INT;
+		reassert_interrupts(d);
+		break;
+
+	case PCCTWO_SCSIICR:
+		if (len != 1) {
+			fatal("TODO: pcc2: non-byte reads and writes of "
+			    "PCCTWO_SCSIICR\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE) {
+			d->pcctwo_reg[relative_addr] = idata & 0xdf;
+			if (idata & ~0xdf)
+				fatal("[ pcc2: HUH? write to PCCTWO_SCSIICR"
+				    " with value 0x%02x. ]\n", (int) idata);
+			reassert_interrupts(d);
+		}
+		break;
+
+	case PCCTWO_IPL:
+		if (len != 1) {
+			fatal("TODO: pcc2: non-byte reads and writes of "
+			    "PCCTWO_IPL\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE) {
+			fatal("[ pcc2: HUH? Write attempt to PCCTWO_IPL. ]\n");
+			exit(1);
+		} else {
+			if (d->pcctwo_reg[PCCTWO_IPL] == 0) {
+				fatal("pcc2: IPL == 0 on read!\n");
+				exit(1);
+			}
+		}
+		break;
+
+	case PCCTWO_MASK:
+		if (len != 1) {
+			fatal("TODO: pcc2: non-byte reads and writes of "
+			    "PCCTWO_MASK\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE) {
+			d->pcctwo_reg[relative_addr] = idata;
+			reassert_interrupts(d);
+		}
+		break;
+
+	default:
+		debug("[ pcc2: unimplemented %s offset 0x%x",
+		    writeflag == MEM_WRITE? "write to" : "read from",
+		    (int) relative_addr);
+		if (writeflag == MEM_WRITE)
+			debug(": 0x%x", (int)idata);
+		debug(" ]\n");
+		exit(1);
+	}
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(mvme187_iack)
+{
+	uint64_t odata = 0;
+	struct pcc2_data *d = (struct pcc2_data *) extra;
+
+	if (writeflag == MEM_WRITE) {
+		fatal("[ pcc2: write to mvme187_iack? ]\n");
+	} else {
+		odata = d->pcctwo_reg[PCCTWO_VECBASE] + d->cur_int_vec[
+		    (relative_addr >> 2) & INTERRUPT_LEVEL_MASK];
+		debug("[ pcc2: mvme187_iack level %i => vector 0x%02x ]\n",
+		    (int)(relative_addr >> 2), (int)odata);
+
+		memory_writemax64(cpu, data, len, odata);
+	}
+
+	return 1;
+}
+
+
+DEVINIT(pcc2)
+{
+	struct pcc2_data *d;
+	int i;
+
+	CHECK_ALLOCATION(d = (struct pcc2_data *) malloc(sizeof(struct pcc2_data)));
+	memset(d, 0, sizeof(struct pcc2_data));
+
+	/*
+	 *  Initial values, according to the manual:
+	 *
+	 *  VECBASE is 0x0f after a reset, although the lowest four bits
+	 *  cannot be manually written to after startup.
+	 */
+	d->pcctwo_reg[PCCTWO_CHIPID] = PCC2_ID;
+	d->pcctwo_reg[PCCTWO_CHIPREV] = 0x00;
+	d->pcctwo_reg[PCCTWO_GENCTL] = 0x00;
+	d->pcctwo_reg[PCCTWO_VECBASE] = 0x0f;
+	d->pcctwo_reg[PCCTWO_PSCALEADJ] = 256 - 33;	// 256 - MHz (fake)
+
+	/*  Connect to the CPU's interrupt pin:  */
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
+
+	/*
+	 *  Register the 16 PCC2 interrupt vectors:
+	 */
+	for (i=0; i<16; i++) {
+		struct interrupt templ;
+		char n[300];
+		snprintf(n, sizeof(n), "%s.pcc2.%i",
+		    devinit->interrupt_path, i);
+
+		memset(&templ, 0, sizeof(templ));
+		templ.line = i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = pcctwo_interrupt_assert;
+		templ.interrupt_deassert = pcctwo_interrupt_deassert;
+
+		interrupt_handler_register(&templ);
+	}
+
+	memory_device_register(devinit->machine->memory, "pcc2",
+	    devinit->addr, 4096, dev_pcc2_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	memory_device_register(devinit->machine->memory, "mvme187_iack",
+	    M187_IACK, 32, dev_mvme187_iack_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	d->timer = timer_add(PCC_TIMER_TICK_HZ, pcc_timer_tick, d);
+
+	machine_add_tickfunction(devinit->machine,
+	    dev_pcc2_tick, d, DEV_PCC2_TICK_SHIFT);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_pcc2.cc gxemul-0.7.0+dfsg/src/devices/dev_pcc2.cc
--- gxemul-0.6.2/src/devices/dev_pcc2.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pcc2.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,649 +0,0 @@
-/*
- *  Copyright (C) 2007-2014  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Peripheral Channel Controller (PCC2) bus (used in MVME machines)
- *
- *  See "Single Board Computers Programmer's Reference Guide (Part 2 of 2)",
- *  "VMESBCA2/PG1" (vmesbcp2.pdf) for more details.
- *
- *  Note: This is somewhat MVME187-specific, at the moment.
- *
- *  Implemented so far:
- *	Timers 1 and 2.
- *	The interrupt controller mechanism (partially!)
- *
- *  TODO:
- *	All devices appart from the timers.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/mvme187.h"
-#include "thirdparty/mvme_pcctworeg.h"
-
-
-#define	INTERRUPT_LEVEL_MASK	0x07
-
-#define	PCC_TIMER_TICK_HZ	100.0
-#define DEV_PCC2_TICK_SHIFT	14
-
-
-// #define	debug fatal
-
-struct pcc2_data {
-	struct interrupt	cpu_irq;
-
-	uint8_t			pcctwo_reg[PCC2_SIZE];
-
-	uint8_t			cur_int_vec[8];
-
-	/*  Timers:  */
-	struct timer		*timer;
-	int			pending_timer1_interrupts;
-	int			pending_timer2_interrupts;
-};
-
-
-static uint32_t read32(unsigned char *p)
-{
-	uint32_t x = 0;
-	size_t i;
-
-	for (i=0; i<sizeof(x); i++) {
-		x <<= 8;
-		x |= p[i];
-	}
-
-	return x;
-}
-
-
-static void write32(unsigned char *p, uint32_t x)
-{
-	size_t i;
-
-	for (i=0; i<sizeof(x); i++) {
-		p[sizeof(x) - 1 - i] = x;
-		x >>= 8;
-	}
-}
-
-
-static void pcc_timer_tick(struct timer *t, void *extra)
-{
-	struct pcc2_data *d = (struct pcc2_data *) extra;
-
-	/*  The PCC2 timers run at 1 MHz.  */
-	int steps = (int) (1000000.0 / PCC_TIMER_TICK_HZ);
-
-	uint32_t count1, count2, compare1, compare2;
-	int interrupt1 = 0, interrupt2 = 0;
-
-	/*  Read values:  */
-	count1 = read32(&d->pcctwo_reg[PCCTWO_T1COUNT]);
-	count2 = read32(&d->pcctwo_reg[PCCTWO_T2COUNT]);
-	compare1 = read32(&d->pcctwo_reg[PCCTWO_T1CMP]);
-	compare2 = read32(&d->pcctwo_reg[PCCTWO_T2CMP]);
-
-	/*  Timer enabled? Then count...  */
-	if (d->pcctwo_reg[PCCTWO_T1CTL] & PCC2_TCTL_CEN) {
-		uint32_t old_count1 = count1;
-		count1 += steps;
-
-		/*  Did we pass the compare value?  */
-		if ((old_count1 < compare1 && count1 >= compare1) ||
-		    (old_count1 < compare1 && count1 < old_count1)) {
-			interrupt1 = 1;
-
-			if (d->pcctwo_reg[PCCTWO_T1CTL] & PCC2_TCTL_COC) {
-				while (count1 >= compare1) {
-					count1 -= compare1;
-					interrupt1 ++;
-				}
-				interrupt1 --;
-			}
-		}
-
-		/*  Overflow?  */
-		if ((int32_t) old_count1 >= 0 && (int32_t) count1 < 0) {
-			int oc = 1 + (d->pcctwo_reg[PCCTWO_T1CTL] >> 4);
-			d->pcctwo_reg[PCCTWO_T1CTL] &= ~PCC2_TCTL_OVF;
-			d->pcctwo_reg[PCCTWO_T1CTL] |= (oc << 4);
-		}
-	}
-
-	/*  ... and the same for timer 2:  */
-	if (d->pcctwo_reg[PCCTWO_T2CTL] & PCC2_TCTL_CEN) {
-		uint32_t old_count2 = count2;
-		count2 += steps;
-
-		if ((old_count2 < compare2 && count2 >= compare2) ||
-		    (old_count2 < compare2 && count2 < old_count2)) {
-			interrupt2 = 1;
-			if (d->pcctwo_reg[PCCTWO_T2CTL] & PCC2_TCTL_COC) {
-				while (count2 >= compare2) {
-					count2 -= compare2;
-					interrupt2 ++;
-				}
-				interrupt2 --;
-			}
-		}
-
-		if ((int32_t) old_count2 >= 0 && (int32_t) count2 < 0) {
-			int oc = 1 + (d->pcctwo_reg[PCCTWO_T2CTL] >> 4);
-			d->pcctwo_reg[PCCTWO_T2CTL] &= ~PCC2_TCTL_OVF;
-			d->pcctwo_reg[PCCTWO_T2CTL] |= (oc << 4);
-		}
-	}
-
-	/*  Should we cause interrupts?  */
-	if (interrupt1 && d->pcctwo_reg[PCCTWO_T1ICR] & PCC2_TTIRQ_IEN)
-		d->pending_timer1_interrupts += interrupt1;
-	if (interrupt2 && d->pcctwo_reg[PCCTWO_T2ICR] & PCC2_TTIRQ_IEN)
-		d->pending_timer2_interrupts += interrupt2;
-
-	/*  Write back values:  */
-	write32(&d->pcctwo_reg[PCCTWO_T1COUNT], count1);
-	write32(&d->pcctwo_reg[PCCTWO_T2COUNT], count2);
-}
-
-
-static void reassert_interrupts(struct pcc2_data *d)
-{
-	int assert = 0;
-
-	if (d->pcctwo_reg[PCCTWO_GENCTL] & PCC2_C040) {
-		/*  The M68000 interrupt mechanism involves outputting
-		    interrupt level on pins EIPL<2..0>. Not implemented
-		    yet.  */
-		fatal("pcc2: C040 interrupt assertions... TODO\n");
-		exit(1);
-	}
-
-	/*
-	 *  Recalculate current interrupt level:
-	 */
-	d->pcctwo_reg[PCCTWO_IPL] = 0;
-
-	/*  Timer interrupts?  */
-	if (d->pending_timer1_interrupts > 0 &&
-	    d->pcctwo_reg[PCCTWO_T1ICR] & PCC2_TTIRQ_IEN)
-		d->pcctwo_reg[PCCTWO_T1ICR] |= PCC2_TTIRQ_INT;
-	if (d->pending_timer2_interrupts > 0 &&
-	    d->pcctwo_reg[PCCTWO_T2ICR] & PCC2_TTIRQ_IEN)
-		d->pcctwo_reg[PCCTWO_T2ICR] |= PCC2_TTIRQ_INT;
-
-	if (d->pcctwo_reg[PCCTWO_T1ICR] & PCC2_TTIRQ_INT) {
-		int intlevel = d->pcctwo_reg[PCCTWO_T1ICR] & PCC2_TTIRQ_IL;
-		d->cur_int_vec[intlevel] = PCC2V_TIMER1;
-		if (d->pcctwo_reg[PCCTWO_IPL] < intlevel)
-			d->pcctwo_reg[PCCTWO_IPL] = intlevel;
-	}
-	if (d->pcctwo_reg[PCCTWO_T2ICR] & PCC2_TTIRQ_INT) {
-		int intlevel = d->pcctwo_reg[PCCTWO_T2ICR] & PCC2_TTIRQ_IL;
-		d->cur_int_vec[intlevel] = PCC2V_TIMER2;
-		if (d->pcctwo_reg[PCCTWO_IPL] < intlevel)
-			d->pcctwo_reg[PCCTWO_IPL] = intlevel;
-	}
-
-	if (d->pcctwo_reg[PCCTWO_SCCTX] & PCC2_IRQ_IEN &&
-	    d->pcctwo_reg[PCCTWO_SCCTX] & PCC2_IRQ_INT) {
-		int intlevel = d->pcctwo_reg[PCCTWO_SCCTX] & PCC2_IRQ_IPL;
-		d->cur_int_vec[intlevel] = PCC2V_SCC_TX;
-		if (d->pcctwo_reg[PCCTWO_IPL] < intlevel)
-			d->pcctwo_reg[PCCTWO_IPL] = intlevel;
-	}
-
-	if (d->pcctwo_reg[PCCTWO_SCCRX] & PCC2_IRQ_IEN &&
-	    d->pcctwo_reg[PCCTWO_SCCRX] & PCC2_IRQ_INT) {
-		int intlevel = d->pcctwo_reg[PCCTWO_SCCRX] & PCC2_IRQ_IPL;
-		d->cur_int_vec[intlevel] = PCC2V_SCC_RX;
-		if (d->pcctwo_reg[PCCTWO_IPL] < intlevel)
-			d->pcctwo_reg[PCCTWO_IPL] = intlevel;
-	}
-
-	if (d->pcctwo_reg[PCCTWO_SCSIICR] & PCC2_IRQ_IEN &&
-	    d->pcctwo_reg[PCCTWO_SCSIICR] & PCC2_IRQ_INT) {
-		int intlevel = d->pcctwo_reg[PCCTWO_SCSIICR] & PCC2_IRQ_IPL;
-		d->cur_int_vec[intlevel] = PCC2V_SCSI;
-		if (d->pcctwo_reg[PCCTWO_IPL] < intlevel)
-			d->pcctwo_reg[PCCTWO_IPL] = intlevel;
-	}
-
-	/*  TODO: Other interrupt sources.  */
-
-	/*  Assert interrupt on the CPU if the IPL is higher than the mask:  */
-	if ((d->pcctwo_reg[PCCTWO_IPL] & INTERRUPT_LEVEL_MASK) >
-	    (d->pcctwo_reg[PCCTWO_MASK] & INTERRUPT_LEVEL_MASK))
-		assert = 1;
-
-	debug("[ pcc2: IPL = %i, MASK = %i => %s ]\n", d->pcctwo_reg[PCCTWO_IPL]& INTERRUPT_LEVEL_MASK,
-		d->pcctwo_reg[PCCTWO_MASK] & INTERRUPT_LEVEL_MASK,
-		assert ? "ASSERT" : "no assert");
-
-	/*  ... but only allow interrupts if Master Interrupt Enable is on:  */
-	if (!(d->pcctwo_reg[PCCTWO_GENCTL] & PCC2_MIEN))
-		assert = 0;
-
-	if (assert)
-		INTERRUPT_ASSERT(d->cpu_irq);
-	else
-		INTERRUPT_DEASSERT(d->cpu_irq);
-}
-
-
-void pcctwo_interrupt_common(struct interrupt *interrupt, int assert)
-{
-	struct pcc2_data *d = (struct pcc2_data *) interrupt->extra;
-
-	switch (interrupt->line) {
-
-	case PCC2V_SCSI:
-		if (assert)
-			d->pcctwo_reg[PCCTWO_SCSIICR] |= PCC2_IRQ_INT;
-		else
-			d->pcctwo_reg[PCCTWO_SCSIICR] &= ~PCC2_IRQ_INT;
-		break;
-
-	case PCC2V_SCC_TX:
-		if (assert)
-			d->pcctwo_reg[PCCTWO_SCCTX] |= PCC2_IRQ_INT;
-		else
-			d->pcctwo_reg[PCCTWO_SCCTX] &= ~PCC2_IRQ_INT;
-		break;
-
-	case PCC2V_SCC_RX:
-		if (assert)
-			d->pcctwo_reg[PCCTWO_SCCRX] |= PCC2_IRQ_INT;
-		else
-			d->pcctwo_reg[PCCTWO_SCCRX] &= ~PCC2_IRQ_INT;
-		break;
-
-	default:fatal("[ pcctwo_interrupt_common: TODO: line = %i ]\n",
-		    interrupt->line);
-		exit(1);
-	}
-
-	reassert_interrupts(d);
-}
-
-
-static void pcctwo_interrupt_assert(struct interrupt *interrupt)
-{
-	pcctwo_interrupt_common(interrupt, 1);
-}
-static void pcctwo_interrupt_deassert(struct interrupt *interrupt)
-{
-	pcctwo_interrupt_common(interrupt, 0);
-}
-
-
-DEVICE_TICK(pcc2)
-{
-	struct pcc2_data *d = (struct pcc2_data *) extra;
-	reassert_interrupts(d);
-}
-
-
-DEVICE_ACCESS(pcc2)
-{
-	uint64_t idata = 0;
-	struct pcc2_data *d = (struct pcc2_data *) extra;
-
-	/*  0xfff42000..0xfff42fff, but only 0x40 unique registers:  */
-	relative_addr %= PCC2_SIZE;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (writeflag == MEM_READ)
-		memcpy(data, d->pcctwo_reg + relative_addr, len);
-
-	switch (relative_addr) {
-
-	case PCCTWO_CHIPID:
-	case PCCTWO_CHIPREV:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ IGNORING write to read-only PCCTWO_CHIPID/"
-			    "CHIPREV register ]\n");
-		}
-		break;
-
-	case PCCTWO_GENCTL:
-		if (len != 1) {
-			fatal("TODO: pcc2: non-byte reads and writes of "
-			    "PCCTWO_GENCTL\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE) {
-			d->pcctwo_reg[relative_addr] = idata;
-			reassert_interrupts(d);
-		}
-		break;
-
-	case PCCTWO_VECBASE:
-		if (len != 1) {
-			fatal("TODO: pcc2: non-byte reads and writes of "
-			    "PCCTWO_VECBASE\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE) {
-			d->pcctwo_reg[relative_addr] = idata & 0xf0;
-			if (idata & ~0xf0)
-				fatal("[ pcc2: HUH? write to PCCTWO_VECBASE"
-				    " with value 0x%02x. ]\n", (int) idata);
-		}
-		break;
-
-	case PCCTWO_T1CMP:
-	case PCCTWO_T2CMP:
-	case PCCTWO_T1COUNT:
-	case PCCTWO_T2COUNT:
-		if (writeflag == MEM_WRITE)
-			memcpy(d->pcctwo_reg + relative_addr, data, len);
-		break;
-
-	case PCCTWO_PSCALEADJ:
-		if (len != 1) {
-			fatal("TODO: pcc2: non-byte reads and writes of "
-			    "PCCTWO_PSCALEADJ\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE) {
-			fatal("[ pcc2: write to PSCALEADJ ignored (value "
-			    "0x%02x) ]\n", (int)idata);
-		}
-		break;
-
-	case PCCTWO_T2CTL:
-	case PCCTWO_T1CTL:
-		if (len != 1) {
-			fatal("TODO: pcc2: non-byte reads and writes of "
-			    "PCCTWO_TxCTL\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE) {
-			/*  PCC2_TCTL_CEN and PCC2_TCTL_COC:  */
-			d->pcctwo_reg[relative_addr] &= 0xfc;
-			d->pcctwo_reg[relative_addr] |= (idata & 3);
-
-			if (idata & PCC2_TCTL_COVF)
-				d->pcctwo_reg[relative_addr] &=
-				    ~(PCC2_TCTL_OVF | PCC2_TCTL_COVF);
-
-			if (idata & ~7)
-				fatal("[ pcc2: HUH? write to PCCTWO_TxCTL"
-				    " with value 0x%02x. ]\n", (int) idata);
-		}
-		break;
-
-	case PCCTWO_T2ICR:
-	case PCCTWO_T1ICR:
-		if (len != 1) {
-			fatal("TODO: pcc2: non-byte reads and writes of "
-			    "PCCTWO_TxICR\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE) {
-			d->pcctwo_reg[relative_addr] &= ~0x17;
-			d->pcctwo_reg[relative_addr] |= (idata & 0x17);
-
-			if (relative_addr == PCCTWO_T1ICR &&
-			    !(idata & PCC2_TTIRQ_IEN))
-				d->pending_timer1_interrupts = 0;
-			if (relative_addr == PCCTWO_T2ICR &&
-			    !(idata & PCC2_TTIRQ_IEN))
-				d->pending_timer2_interrupts = 0;
-
-			if (relative_addr == PCCTWO_T1ICR && (idata & PCC2_TTIRQ_ICLR)
-			    && d->pcctwo_reg[relative_addr] & PCC2_TTIRQ_INT
-			    && d->pending_timer1_interrupts > 0)
-				d->pending_timer1_interrupts --;
-
-			if (relative_addr == PCCTWO_T2ICR && (idata & PCC2_TTIRQ_ICLR)
-			    && d->pcctwo_reg[relative_addr] & PCC2_TTIRQ_INT
-			    && d->pending_timer2_interrupts > 0)
-				d->pending_timer2_interrupts --;
-
-			if (idata & PCC2_TTIRQ_ICLR)
-				d->pcctwo_reg[relative_addr] &= ~PCC2_TTIRQ_INT;
-
-			if (idata & 0xe0)
-				fatal("[ pcc2: HUH? write to PCCTWO_TxICR"
-				    " with value 0x%02x. ]\n", (int) idata);
-
-			reassert_interrupts(d);
-		}
-		break;
-
-	case PCCTWO_SCCERR:
-		if (len != 1) {
-			fatal("TODO: pcc2: non-byte reads and writes of "
-			    "PCCTWO_SCCERR\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE)
-			d->pcctwo_reg[relative_addr] = 0;	/*  clear  */
-		break;
-
-	case PCCTWO_SCCICR:
-		if (len != 1) {
-			fatal("TODO: pcc2: non-byte reads and writes of "
-			    "PCCTWO_SCCICR\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE) {
-			d->pcctwo_reg[relative_addr] = idata & 0x1f;
-			if (idata & ~0x1f)
-				fatal("[ pcc2: HUH? write to PCCTWO_SCCICR"
-				    " with value 0x%02x. ]\n", (int) idata);
-			reassert_interrupts(d);
-		}
-		break;
-
-	case PCCTWO_SCCTX:
-		if (len != 1) {
-			fatal("TODO: pcc2: non-byte reads and writes of "
-			    "PCCTWO_SCCTX\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE) {
-			d->pcctwo_reg[relative_addr] = idata & 0x1f;
-			if (idata & ~0x1f)
-				fatal("[ pcc2: HUH? write to PCCTWO_SCCTX"
-				    " with value 0x%02x. ]\n", (int) idata);
-			reassert_interrupts(d);
-		}
-		break;
-
-	case PCCTWO_SCCRX:
-		if (len != 1) {
-			fatal("TODO: pcc2: non-byte reads and writes of "
-			    "PCCTWO_SCCRX\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE) {
-			d->pcctwo_reg[relative_addr] = idata & 0xdf;
-			if (idata & ~0xdf)
-				fatal("[ pcc2: HUH? write to PCCTWO_SCCRX"
-				    " with value 0x%02x. ]\n", (int) idata);
-			reassert_interrupts(d);
-		}
-		break;
-
-	case PCCTWO_SCCRXIACK:
-		/*  TODO. Hm. Is this enough?  */
-		d->pcctwo_reg[PCCTWO_SCCRX] &= ~PCC2_IRQ_INT;
-		reassert_interrupts(d);
-		break;
-
-	case PCCTWO_SCSIICR:
-		if (len != 1) {
-			fatal("TODO: pcc2: non-byte reads and writes of "
-			    "PCCTWO_SCSIICR\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE) {
-			d->pcctwo_reg[relative_addr] = idata & 0xdf;
-			if (idata & ~0xdf)
-				fatal("[ pcc2: HUH? write to PCCTWO_SCSIICR"
-				    " with value 0x%02x. ]\n", (int) idata);
-			reassert_interrupts(d);
-		}
-		break;
-
-	case PCCTWO_IPL:
-		if (len != 1) {
-			fatal("TODO: pcc2: non-byte reads and writes of "
-			    "PCCTWO_IPL\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE) {
-			fatal("[ pcc2: HUH? Write attempt to PCCTWO_IPL. ]\n");
-			exit(1);
-		} else {
-			if (d->pcctwo_reg[PCCTWO_IPL] == 0) {
-				fatal("pcc2: IPL == 0 on read!\n");
-				exit(1);
-			}
-		}
-		break;
-
-	case PCCTWO_MASK:
-		if (len != 1) {
-			fatal("TODO: pcc2: non-byte reads and writes of "
-			    "PCCTWO_MASK\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE) {
-			d->pcctwo_reg[relative_addr] = idata;
-			reassert_interrupts(d);
-		}
-		break;
-
-	default:
-		debug("[ pcc2: unimplemented %s offset 0x%x",
-		    writeflag == MEM_WRITE? "write to" : "read from",
-		    (int) relative_addr);
-		if (writeflag == MEM_WRITE)
-			debug(": 0x%x", (int)idata);
-		debug(" ]\n");
-		exit(1);
-	}
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(mvme187_iack)
-{
-	uint64_t odata = 0;
-	struct pcc2_data *d = (struct pcc2_data *) extra;
-
-	if (writeflag == MEM_WRITE) {
-		fatal("[ pcc2: write to mvme187_iack? ]\n");
-	} else {
-		odata = d->pcctwo_reg[PCCTWO_VECBASE] + d->cur_int_vec[
-		    (relative_addr >> 2) & INTERRUPT_LEVEL_MASK];
-		debug("[ pcc2: mvme187_iack level %i => vector 0x%02x ]\n",
-		    (int)(relative_addr >> 2), (int)odata);
-
-		memory_writemax64(cpu, data, len, odata);
-	}
-
-	return 1;
-}
-
-
-DEVINIT(pcc2)
-{
-	struct pcc2_data *d;
-	int i;
-
-	CHECK_ALLOCATION(d = (struct pcc2_data *) malloc(sizeof(struct pcc2_data)));
-	memset(d, 0, sizeof(struct pcc2_data));
-
-	/*
-	 *  Initial values, according to the manual:
-	 *
-	 *  VECBASE is 0x0f after a reset, although the lowest four bits
-	 *  cannot be manually written to after startup.
-	 */
-	d->pcctwo_reg[PCCTWO_CHIPID] = PCC2_ID;
-	d->pcctwo_reg[PCCTWO_CHIPREV] = 0x00;
-	d->pcctwo_reg[PCCTWO_GENCTL] = 0x00;
-	d->pcctwo_reg[PCCTWO_VECBASE] = 0x0f;
-	d->pcctwo_reg[PCCTWO_PSCALEADJ] = 256 - 33;	// 256 - MHz (fake)
-
-	/*  Connect to the CPU's interrupt pin:  */
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
-
-	/*
-	 *  Register the 16 PCC2 interrupt vectors:
-	 */
-	for (i=0; i<16; i++) {
-		struct interrupt templ;
-		char n[300];
-		snprintf(n, sizeof(n), "%s.pcc2.%i",
-		    devinit->interrupt_path, i);
-
-		memset(&templ, 0, sizeof(templ));
-		templ.line = i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = pcctwo_interrupt_assert;
-		templ.interrupt_deassert = pcctwo_interrupt_deassert;
-
-		interrupt_handler_register(&templ);
-	}
-
-	memory_device_register(devinit->machine->memory, "pcc2",
-	    devinit->addr, 4096, dev_pcc2_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	memory_device_register(devinit->machine->memory, "mvme187_iack",
-	    M187_IACK, 32, dev_mvme187_iack_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	d->timer = timer_add(PCC_TIMER_TICK_HZ, pcc_timer_tick, d);
-
-	machine_add_tickfunction(devinit->machine,
-	    dev_pcc2_tick, d, DEV_PCC2_TICK_SHIFT);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_pccmos.c gxemul-0.7.0+dfsg/src/devices/dev_pccmos.c
--- gxemul-0.6.2/src/devices/dev_pccmos.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pccmos.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,158 @@
+/*
+ *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: PC CMOS/RTC device (ISA ports 0x70 and 0x71)
+ *
+ *  The main point of this device is to be a "PC style wrapper" for accessing
+ *  the MC146818 (the RTC). In most other respects, this device is bogus, and
+ *  just acts as a 256-byte RAM device.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	DEV_PCCMOS_LENGTH		2
+#define	PCCMOS_MC146818_FAKE_ADDR	0x1d00000000ULL
+
+struct pccmos_data {
+	unsigned char	select;
+	unsigned char	ram[256];
+};
+
+
+DEVICE_ACCESS(pccmos)
+{
+	struct pccmos_data *d = (struct pccmos_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	unsigned char b = 0;
+	int r = 1;
+
+	if (writeflag == MEM_WRITE)
+		b = idata = memory_readmax64(cpu, data, len);
+
+	/*
+	 *  Accesses to CMOS register 0 .. 0xd are rerouted to the
+	 *  RTC; all other access are treated as CMOS RAM read/writes.
+	 */
+
+	if ((relative_addr & 1) == 0) {
+		if (writeflag == MEM_WRITE) {
+			d->select = idata;
+			if (idata <= 0x0d) {
+				r = cpu->memory_rw(cpu, cpu->mem,
+				    PCCMOS_MC146818_FAKE_ADDR, &b, 1,
+				    MEM_WRITE, PHYSICAL);
+			}
+		} else
+			odata = d->select;
+	} else {
+		if (d->select <= 0x0d) {
+			if (writeflag == MEM_WRITE) {
+				r = cpu->memory_rw(cpu, cpu->mem,
+				    PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1,
+				    MEM_WRITE, PHYSICAL);
+			} else {
+				r = cpu->memory_rw(cpu, cpu->mem,
+				    PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1,
+				    MEM_READ, PHYSICAL);
+				odata = b;
+			}
+		} else {
+			if (writeflag == MEM_WRITE)
+				d->ram[d->select] = idata;
+			else
+				odata = d->ram[d->select];
+		}
+	}
+
+	if (r == 0)
+		fatal("[ pccmos: memory_rw() error! ]\n");
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(pccmos)
+{
+	int type = MC146818_PC_CMOS, len = DEV_PCCMOS_LENGTH;
+	struct pccmos_data *d;
+
+	CHECK_ALLOCATION(d = (struct pccmos_data *) malloc(sizeof(struct pccmos_data)));
+	memset(d, 0, sizeof(struct pccmos_data));
+
+	switch (devinit->machine->machine_type) {
+	case MACHINE_CATS:
+	case MACHINE_NETWINDER:
+		type = MC146818_CATS;
+		d->ram[0x48] = 20;		/*  century  */
+		len = DEV_PCCMOS_LENGTH * 2;
+		break;
+	case MACHINE_ALGOR:
+		type = MC146818_ALGOR;
+		break;
+	case MACHINE_ARC:
+		fatal("\nARC pccmos: TODO\n\n");
+		type = MC146818_ALGOR;
+		break;
+	case MACHINE_EVBMIPS:
+		/*  Malta etc.  */
+		type = MC146818_ALGOR;
+		break;
+	case MACHINE_COBALT:
+	case MACHINE_PREP:
+	case MACHINE_MVMEPPC:
+	case MACHINE_ALPHA:
+	case MACHINE_IYONIX:	// TODO: not sure about exact type.
+		break;
+	default:fatal("devinit_pccmos(): unimplemented machine type"
+		    " %i\n", devinit->machine->machine_type);
+		exit(1);
+	}
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, len, dev_pccmos_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	dev_mc146818_init(devinit->machine, devinit->machine->memory,
+	    PCCMOS_MC146818_FAKE_ADDR, devinit->interrupt_path, type, 1);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_pccmos.cc gxemul-0.7.0+dfsg/src/devices/dev_pccmos.cc
--- gxemul-0.6.2/src/devices/dev_pccmos.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pccmos.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,158 +0,0 @@
-/*
- *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: PC CMOS/RTC device (ISA ports 0x70 and 0x71)
- *
- *  The main point of this device is to be a "PC style wrapper" for accessing
- *  the MC146818 (the RTC). In most other respects, this device is bogus, and
- *  just acts as a 256-byte RAM device.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define	DEV_PCCMOS_LENGTH		2
-#define	PCCMOS_MC146818_FAKE_ADDR	0x1d00000000ULL
-
-struct pccmos_data {
-	unsigned char	select;
-	unsigned char	ram[256];
-};
-
-
-DEVICE_ACCESS(pccmos)
-{
-	struct pccmos_data *d = (struct pccmos_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	unsigned char b = 0;
-	int r = 1;
-
-	if (writeflag == MEM_WRITE)
-		b = idata = memory_readmax64(cpu, data, len);
-
-	/*
-	 *  Accesses to CMOS register 0 .. 0xd are rerouted to the
-	 *  RTC; all other access are treated as CMOS RAM read/writes.
-	 */
-
-	if ((relative_addr & 1) == 0) {
-		if (writeflag == MEM_WRITE) {
-			d->select = idata;
-			if (idata <= 0x0d) {
-				r = cpu->memory_rw(cpu, cpu->mem,
-				    PCCMOS_MC146818_FAKE_ADDR, &b, 1,
-				    MEM_WRITE, PHYSICAL);
-			}
-		} else
-			odata = d->select;
-	} else {
-		if (d->select <= 0x0d) {
-			if (writeflag == MEM_WRITE) {
-				r = cpu->memory_rw(cpu, cpu->mem,
-				    PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1,
-				    MEM_WRITE, PHYSICAL);
-			} else {
-				r = cpu->memory_rw(cpu, cpu->mem,
-				    PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1,
-				    MEM_READ, PHYSICAL);
-				odata = b;
-			}
-		} else {
-			if (writeflag == MEM_WRITE)
-				d->ram[d->select] = idata;
-			else
-				odata = d->ram[d->select];
-		}
-	}
-
-	if (r == 0)
-		fatal("[ pccmos: memory_rw() error! ]\n");
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(pccmos)
-{
-	int type = MC146818_PC_CMOS, len = DEV_PCCMOS_LENGTH;
-	struct pccmos_data *d;
-
-	CHECK_ALLOCATION(d = (struct pccmos_data *) malloc(sizeof(struct pccmos_data)));
-	memset(d, 0, sizeof(struct pccmos_data));
-
-	switch (devinit->machine->machine_type) {
-	case MACHINE_CATS:
-	case MACHINE_NETWINDER:
-		type = MC146818_CATS;
-		d->ram[0x48] = 20;		/*  century  */
-		len = DEV_PCCMOS_LENGTH * 2;
-		break;
-	case MACHINE_ALGOR:
-		type = MC146818_ALGOR;
-		break;
-	case MACHINE_ARC:
-		fatal("\nARC pccmos: TODO\n\n");
-		type = MC146818_ALGOR;
-		break;
-	case MACHINE_EVBMIPS:
-		/*  Malta etc.  */
-		type = MC146818_ALGOR;
-		break;
-	case MACHINE_COBALT:
-	case MACHINE_PREP:
-	case MACHINE_MVMEPPC:
-	case MACHINE_ALPHA:
-	case MACHINE_IYONIX:	// TODO: not sure about exact type.
-		break;
-	default:fatal("devinit_pccmos(): unimplemented machine type"
-		    " %i\n", devinit->machine->machine_type);
-		exit(1);
-	}
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, len, dev_pccmos_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	dev_mc146818_init(devinit->machine, devinit->machine->memory,
-	    PCCMOS_MC146818_FAKE_ADDR, devinit->interrupt_path, type, 1);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_pcic.c gxemul-0.7.0+dfsg/src/devices/dev_pcic.c
--- gxemul-0.6.2/src/devices/dev_pcic.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pcic.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,246 @@
+/*
+ *  Copyright (C) 2005-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Intel 82365SL PC Card Interface Controller
+ *
+ *  (Called "pcic" by NetBSD.)
+ *
+ *  TODO: Lots of stuff. This is just a quick hack. Don't rely on it.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/i82365reg.h"
+#include "thirdparty/pcmciareg.h"
+
+
+/*  #define debug fatal  */
+
+#define	DEV_PCIC_LENGTH		2
+
+struct pcic_data {
+	struct interrupt	irq;
+	int			regnr;
+};
+
+
+DEVICE_ACCESS(pcic_cis)
+{
+	/*  struct pcic_data *d = (struct pcic_data *) extra;  */
+	uint64_t odata = 0;
+
+	// uint64_t idata = memory_readmax64(cpu, data, len);
+
+{
+#if 0
+	/*  SMC, PCM Ethernet Adapter, CIS V1.05 (manufacturer 0x108, 
+	    product 0x105)  */
+	unsigned char x[] = {
+		PCMCIA_CISTPL_DEVICE, 3, PCMCIA_DTYPE_FUNCSPEC, 0xff,0xff,
+		PCMCIA_CISTPL_FUNCID, 2, 0x06, 0x00,
+		PCMCIA_CISTPL_MANFID, 4, 0x08, 0x01, 0x05, 0x01,
+		PCMCIA_CISTPL_VERS_1, 0x26,
+		0x04, 0x01, 0x53, 0x4d, 0x43, 0x00, 0x50, 0x43, 0x4d, 0x20,
+		0x45, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74, 0x20, 0x41,
+		0x64, 0x61, 0x70, 0x74, 0x65, 0x72, 0x00, 0x43, 0x49, 0x53,
+		0x20, 0x56, 0x31, 0x2e, 0x30, 0x35, 0x00, 0xff,
+		PCMCIA_CISTPL_CONFIG, 0x0a,
+		0x02, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0xff,
+		PCMCIA_CISTPL_CFTABLE_ENTRY, 0x0b,
+		0xc1, 0x01, 0x70, 0x50, 0xbc, 0x8e, 0x48, 0x40, 0x00,0x02,0xff,
+		/*  unhandled CISTPL 22  */
+		0x22, 0x02, 0x01, 0x02,
+		/*  unhandled CISTPL 22  */
+		0x22, 0x05, 0x02, 0x80, 0x96, 0x98, 0x00,
+		/*  unhandled CISTPL 22  */
+		0x22, 0x02, 0x03, 0x01,
+		/*  unhandled CISTPL 22  */
+		0x22, 0x08, 0x04, 0x06, 0x00, 0x00, 0xc0, 0x2f, 0x48, 0xd2,
+		/*  unhandled CISTPL 22  */
+		0x22, 0x02, 0x05, 0x01,
+
+		PCMCIA_CISTPL_END, 0
+	};
+#endif
+
+	/*  From http://www.mail-archive.com/freebsd-current@freebsd.
+		org/msg32550.html  */
+	unsigned char x[] = {
+		PCMCIA_CISTPL_DEVICE, 3, 0xdc, 0x00, 0xff,
+		PCMCIA_CISTPL_VERS_1, 0x1a,
+		0x04,0x01,0x20,0x00,0x4e,0x69,0x6e,0x6a,0x61,0x41,0x54,0x41,
+		0x2d,0x00,0x56,0x31,0x2e,0x30,0x00,0x41,0x50,0x30,0x30,0x20,
+		0x00,0xff,
+		PCMCIA_CISTPL_CONFIG, 5,
+		0x01,0x23,0x00,0x02,0x03,
+		PCMCIA_CISTPL_CFTABLE_ENTRY, 0x15,
+		0xe1,0x01,0x3d,0x11,0x55,0x1e,0xfc,0x23,0xf0,0x61,0x80,0x01,
+		0x07,0x86,0x03,0x01,0x30,0x68,0xd0,0x10,0x00,
+#if 0
+		PCMCIA_CISTPL_CFTABLE_ENTRY, 0xf,
+		0x22,0x38,0xf0,0x61,0x90,0x01,0x07,0x96,0x03,0x01,0x30,0x68,
+		0xd0,0x10,0x00,
+		PCMCIA_CISTPL_CFTABLE_ENTRY, 0xf,
+		0x23,0x38,0xf0,0x61,0xa0,0x01,0x07,0xa6,0x03,0x01,0x30,0x68,
+		0xd0,0x10,0x00,
+#endif
+		PCMCIA_CISTPL_NO_LINK, 0,
+
+		PCMCIA_CISTPL_END, 0
+	};
+
+	relative_addr /= 2;
+	if (relative_addr < sizeof(x))
+		odata = x[relative_addr];
+
+	debug("[ dev_pcic_cis_access: blah blah: addr=0x%x ]\n",
+	    (int)relative_addr);
+}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(pcic)
+{
+	struct pcic_data *d = (struct pcic_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int controller_nr, socket_nr;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	controller_nr = d->regnr & 0x80? 1 : 0;
+	socket_nr = d->regnr & 0x40? 1 : 0;
+
+	switch (relative_addr) {
+
+	case 0:	/*  Register select:  */
+		if (writeflag == MEM_WRITE)
+			d->regnr = idata;
+		else
+			odata = d->regnr;
+		break;
+
+	case 1:	/*  Register access:  */
+		switch (d->regnr & 0x3f) {
+
+		case PCIC_IDENT:
+			/*  This causes sockets A and B to be present on
+			    controller 0, and only socket A on controller 1.  */
+			if (controller_nr == 1 && socket_nr == 1)
+				odata = 0;
+			else
+				odata = PCIC_IDENT_IFTYPE_MEM_AND_IO
+				    | PCIC_IDENT_REV_I82365SLR1;
+			break;
+#if 1
+		case PCIC_INTR:
+			odata = PCIC_INTR_IRQ3;
+			break;
+#endif
+
+		case PCIC_CSC:
+			odata = PCIC_CSC_GPI;
+			break;
+
+		case PCIC_IF_STATUS:
+			odata = PCIC_IF_STATUS_READY
+			    | PCIC_IF_STATUS_POWERACTIVE;
+			if (controller_nr == 0 && socket_nr == 0)
+				odata |= PCIC_IF_STATUS_CARDDETECT_PRESENT;
+			break;
+
+		default:
+			if (writeflag == MEM_WRITE) {
+				debug("[ pcic: unimplemented write to "
+				    "controller %i socket %c, regnr %i: "
+				    "data=0x%02x ]\n", controller_nr,
+				    socket_nr? 'B' : 'A',
+				    d->regnr & 0x3f, (int)idata);
+			} else {
+				debug("[ pcic: unimplemented read from "
+				    "controller %i socket %c, regnr %i ]\n",
+				    controller_nr, socket_nr? 'B' : 'A',
+				    d->regnr & 0x3f);
+			}
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(pcic)
+{
+	char tmpstr[200];
+	struct pcic_data *d;
+
+	CHECK_ALLOCATION(d = (struct pcic_data *) malloc(sizeof(struct pcic_data)));
+	memset(d, 0, sizeof(struct pcic_data));
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_PCIC_LENGTH,
+	    dev_pcic_access, (void *)d, DM_DEFAULT, NULL);
+
+	/*  TODO: this shouldn't be hardcoded for hpcmips here!  */
+	memory_device_register(devinit->machine->memory, "pcic_cis",
+	    0x10070000, 0x1000, dev_pcic_cis_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	/*  TODO: find out a good way to specify the address, and the IRQ!  */
+	snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x14000180 irq=%s.giu.9",
+	    devinit->interrupt_path);
+	device_add(devinit->machine, tmpstr);
+
+	/*  TODO: Linux/MobilePro looks at 0x14000170 and 0x1f0...  */
+	/*  Yuck. Now there are two. How should this be solved nicely?  */
+	snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x140001f0 irq=%s.giu.9",
+	    devinit->interrupt_path);
+	device_add(devinit->machine, tmpstr);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_pcic.cc gxemul-0.7.0+dfsg/src/devices/dev_pcic.cc
--- gxemul-0.6.2/src/devices/dev_pcic.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pcic.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,246 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Intel 82365SL PC Card Interface Controller
- *
- *  (Called "pcic" by NetBSD.)
- *
- *  TODO: Lots of stuff. This is just a quick hack. Don't rely on it.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/i82365reg.h"
-#include "thirdparty/pcmciareg.h"
-
-
-/*  #define debug fatal  */
-
-#define	DEV_PCIC_LENGTH		2
-
-struct pcic_data {
-	struct interrupt	irq;
-	int			regnr;
-};
-
-
-DEVICE_ACCESS(pcic_cis)
-{
-	/*  struct pcic_data *d = (struct pcic_data *) extra;  */
-	uint64_t idata = 0, odata = 0;
-
-	idata = memory_readmax64(cpu, data, len);
-
-{
-#if 0
-	/*  SMC, PCM Ethernet Adapter, CIS V1.05 (manufacturer 0x108, 
-	    product 0x105)  */
-	unsigned char x[] = {
-		PCMCIA_CISTPL_DEVICE, 3, PCMCIA_DTYPE_FUNCSPEC, 0xff,0xff,
-		PCMCIA_CISTPL_FUNCID, 2, 0x06, 0x00,
-		PCMCIA_CISTPL_MANFID, 4, 0x08, 0x01, 0x05, 0x01,
-		PCMCIA_CISTPL_VERS_1, 0x26,
-		0x04, 0x01, 0x53, 0x4d, 0x43, 0x00, 0x50, 0x43, 0x4d, 0x20,
-		0x45, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74, 0x20, 0x41,
-		0x64, 0x61, 0x70, 0x74, 0x65, 0x72, 0x00, 0x43, 0x49, 0x53,
-		0x20, 0x56, 0x31, 0x2e, 0x30, 0x35, 0x00, 0xff,
-		PCMCIA_CISTPL_CONFIG, 0x0a,
-		0x02, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0xff,
-		PCMCIA_CISTPL_CFTABLE_ENTRY, 0x0b,
-		0xc1, 0x01, 0x70, 0x50, 0xbc, 0x8e, 0x48, 0x40, 0x00,0x02,0xff,
-		/*  unhandled CISTPL 22  */
-		0x22, 0x02, 0x01, 0x02,
-		/*  unhandled CISTPL 22  */
-		0x22, 0x05, 0x02, 0x80, 0x96, 0x98, 0x00,
-		/*  unhandled CISTPL 22  */
-		0x22, 0x02, 0x03, 0x01,
-		/*  unhandled CISTPL 22  */
-		0x22, 0x08, 0x04, 0x06, 0x00, 0x00, 0xc0, 0x2f, 0x48, 0xd2,
-		/*  unhandled CISTPL 22  */
-		0x22, 0x02, 0x05, 0x01,
-
-		PCMCIA_CISTPL_END, 0
-	};
-#endif
-
-	/*  From http://www.mail-archive.com/freebsd-current@freebsd.
-		org/msg32550.html  */
-	unsigned char x[] = {
-		PCMCIA_CISTPL_DEVICE, 3, 0xdc, 0x00, 0xff,
-		PCMCIA_CISTPL_VERS_1, 0x1a,
-		0x04,0x01,0x20,0x00,0x4e,0x69,0x6e,0x6a,0x61,0x41,0x54,0x41,
-		0x2d,0x00,0x56,0x31,0x2e,0x30,0x00,0x41,0x50,0x30,0x30,0x20,
-		0x00,0xff,
-		PCMCIA_CISTPL_CONFIG, 5,
-		0x01,0x23,0x00,0x02,0x03,
-		PCMCIA_CISTPL_CFTABLE_ENTRY, 0x15,
-		0xe1,0x01,0x3d,0x11,0x55,0x1e,0xfc,0x23,0xf0,0x61,0x80,0x01,
-		0x07,0x86,0x03,0x01,0x30,0x68,0xd0,0x10,0x00,
-#if 0
-		PCMCIA_CISTPL_CFTABLE_ENTRY, 0xf,
-		0x22,0x38,0xf0,0x61,0x90,0x01,0x07,0x96,0x03,0x01,0x30,0x68,
-		0xd0,0x10,0x00,
-		PCMCIA_CISTPL_CFTABLE_ENTRY, 0xf,
-		0x23,0x38,0xf0,0x61,0xa0,0x01,0x07,0xa6,0x03,0x01,0x30,0x68,
-		0xd0,0x10,0x00,
-#endif
-		PCMCIA_CISTPL_NO_LINK, 0,
-
-		PCMCIA_CISTPL_END, 0
-	};
-
-	relative_addr /= 2;
-	if (relative_addr < sizeof(x))
-		odata = x[relative_addr];
-
-	debug("[ dev_pcic_cis_access: blah blah: addr=0x%x ]\n",
-	    (int)relative_addr);
-}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(pcic)
-{
-	struct pcic_data *d = (struct pcic_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int controller_nr, socket_nr;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	controller_nr = d->regnr & 0x80? 1 : 0;
-	socket_nr = d->regnr & 0x40? 1 : 0;
-
-	switch (relative_addr) {
-
-	case 0:	/*  Register select:  */
-		if (writeflag == MEM_WRITE)
-			d->regnr = idata;
-		else
-			odata = d->regnr;
-		break;
-
-	case 1:	/*  Register access:  */
-		switch (d->regnr & 0x3f) {
-
-		case PCIC_IDENT:
-			/*  This causes sockets A and B to be present on
-			    controller 0, and only socket A on controller 1.  */
-			if (controller_nr == 1 && socket_nr == 1)
-				odata = 0;
-			else
-				odata = PCIC_IDENT_IFTYPE_MEM_AND_IO
-				    | PCIC_IDENT_REV_I82365SLR1;
-			break;
-#if 1
-		case PCIC_INTR:
-			odata = PCIC_INTR_IRQ3;
-			break;
-#endif
-
-		case PCIC_CSC:
-			odata = PCIC_CSC_GPI;
-			break;
-
-		case PCIC_IF_STATUS:
-			odata = PCIC_IF_STATUS_READY
-			    | PCIC_IF_STATUS_POWERACTIVE;
-			if (controller_nr == 0 && socket_nr == 0)
-				odata |= PCIC_IF_STATUS_CARDDETECT_PRESENT;
-			break;
-
-		default:
-			if (writeflag == MEM_WRITE) {
-				debug("[ pcic: unimplemented write to "
-				    "controller %i socket %c, regnr %i: "
-				    "data=0x%02x ]\n", controller_nr,
-				    socket_nr? 'B' : 'A',
-				    d->regnr & 0x3f, (int)idata);
-			} else {
-				debug("[ pcic: unimplemented read from "
-				    "controller %i socket %c, regnr %i ]\n",
-				    controller_nr, socket_nr? 'B' : 'A',
-				    d->regnr & 0x3f);
-			}
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(pcic)
-{
-	char tmpstr[200];
-	struct pcic_data *d;
-
-	CHECK_ALLOCATION(d = (struct pcic_data *) malloc(sizeof(struct pcic_data)));
-	memset(d, 0, sizeof(struct pcic_data));
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_PCIC_LENGTH,
-	    dev_pcic_access, (void *)d, DM_DEFAULT, NULL);
-
-	/*  TODO: this shouldn't be hardcoded for hpcmips here!  */
-	memory_device_register(devinit->machine->memory, "pcic_cis",
-	    0x10070000, 0x1000, dev_pcic_cis_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	/*  TODO: find out a good way to specify the address, and the IRQ!  */
-	snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x14000180 irq=%s.giu.9",
-	    devinit->interrupt_path);
-	device_add(devinit->machine, tmpstr);
-
-	/*  TODO: Linux/MobilePro looks at 0x14000170 and 0x1f0...  */
-	/*  Yuck. Now there are two. How should this be solved nicely?  */
-	snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x140001f0 irq=%s.giu.9",
-	    devinit->interrupt_path);
-	device_add(devinit->machine, tmpstr);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_pckbc.c gxemul-0.7.0+dfsg/src/devices/dev_pckbc.c
--- gxemul-0.6.2/src/devices/dev_pckbc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pckbc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1199 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: 8042 PC keyboard controller (+ 8242WB Keyboard/Mouse controller)
+ *
+ *  This module includes emulation of the 8048 keyboard chip too.
+ *
+ *  Quick source of good info: http://my.execpc.com/~geezer/osd/kbd/kbd.txt
+ *
+ *  Some scancode listings for various types:
+ *	http://www.win.tue.nl/~aeb/linux/kbd/scancodes-1.html
+ *	http://www.computer-engineering.org/ps2keyboard/scancodes3.html
+ *	https://www.win.tue.nl/~aeb/linux/kbd/scancodes-10.html#scancodesets
+ *	http://nixdoc.net/man-pages/irix/man7/pckeyboard.7.html
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/kbdreg.h"
+
+
+// #define PCKBC_DEBUG
+// #define debug fatal
+
+
+// Should be 256 to emulate a real 8042? Having a larger value allows
+// pasting of larger text chunks which is useful in the emulator.
+// #define	MAX_8042_QUEUELEN	256
+#define	MAX_8042_QUEUELEN	32768
+
+#define	PC_DATA			0
+#define	PC_CMD			0
+#define	PC_STATUS		1
+
+#define	PS2_TXBUF		0
+#define	PS2_RXBUF		1
+#define	PS2_CONTROL		2
+#define         PS2_CONTROL_TXINTEN   (1 << 2)
+#define         PS2_CONTROL_RXINTEN   (1 << 3)
+#define	PS2_STATUS		3
+#define         PS2_STATUS_TXEMPTY    (1 << 3)
+#define         PS2_STATUS_RXFULL     (1 << 4)
+
+#define	PS2	100	// internal offset
+
+#define	PCKBC_TICKSHIFT		15
+
+
+struct pckbc_data {
+	int		console_handle;
+	int		in_use;
+
+	int		reg[DEV_PCKBC_LENGTH];
+
+	struct interrupt irq_keyboard;
+	struct interrupt irq_mouse;
+	int		currently_asserted[2];
+	int		type;
+	int		pc_style_flag;
+
+	/*  TODO: one of these for each port?  */
+	int		clocksignal;
+	int		rx_int_enable[2];
+	int		tx_int_enable[2];
+
+	int		scanning_enabled[2];
+	int		translation_table;
+	int		state[2];
+	int		cmdbyte;
+	int		output_byte;
+	int		last_scancode;
+
+	unsigned	key_queue[2][MAX_8042_QUEUELEN];
+	int		head[2], tail[2];
+
+	int		mouse_buttons;
+};
+
+#define	STATE_NORMAL			0
+#define	STATE_LDCMDBYTE			1
+#define	STATE_RDCMDBYTE			2
+#define	STATE_WAITING_FOR_TRANSLTABLE	3
+#define	STATE_WAITING_FOR_RATE		4
+#define	STATE_WAITING_FOR_ONEKEY_MB	5
+#define	STATE_WAITING_FOR_AUX		6
+#define	STATE_WAITING_FOR_AUX_OUT	7
+#define	STATE_LDOUTPUT			8
+#define	STATE_RDOUTPUT			9
+
+
+/*
+ *  pckbc_add_code():
+ *
+ *  Adds a byte to the data queue.
+ */
+void pckbc_add_code(struct pckbc_data *d, int code, int port)
+{
+	/*  Add at the head, read at the tail:  */
+	d->head[port] = (d->head[port]+1) % MAX_8042_QUEUELEN;
+	if (d->head[port] == d->tail[port])
+		fatal("[ pckbc: queue overrun, port %i! ]\n", port);
+
+	d->key_queue[port][d->head[port]] = code;
+}
+
+
+/*
+ *  pckbc_get_code():
+ *
+ *  Reads a byte from a data queue.
+ */
+int pckbc_get_code(struct pckbc_data *d, int port)
+{
+	if (d->head[port] == d->tail[port])
+		fatal("[ pckbc: queue empty, port %i! ]\n", port);
+	else
+		d->tail[port] = (d->tail[port]+1) % MAX_8042_QUEUELEN;
+
+	return d->key_queue[port][d->tail[port]];
+}
+
+
+/*
+ *  ascii_to_scancodes_type1():
+ *
+ *  Conversion from ASCII codes to default (US) keyboard scancodes.
+ */
+static void ascii_to_pc_scancodes_type1(int a, struct pckbc_data *d)
+{
+	int old_head;
+	int p = 0;	/*  port  */
+	int shift = 0, ctrl = 0;
+
+	if (a >= 'A' && a <= 'Z') { a += 32; shift = 1; }
+	if ((a >= 1 && a <= 26) && (a!='\n' && a!='\t' && a!='\b' && a!='\r'))
+		{ a += 96; ctrl = 1; }
+
+	if (a=='!')  {	a = '1'; shift = 1; }
+	if (a=='@')  {	a = '2'; shift = 1; }
+	if (a=='#')  {	a = '3'; shift = 1; }
+	if (a=='$')  {	a = '4'; shift = 1; }
+	if (a=='%')  {	a = '5'; shift = 1; }
+	if (a=='^')  {	a = '6'; shift = 1; }
+	if (a=='&')  {	a = '7'; shift = 1; }
+	if (a=='*')  {	a = '8'; shift = 1; }
+	if (a=='(')  {	a = '9'; shift = 1; }
+	if (a==')')  {	a = '0'; shift = 1; }
+	if (a=='_')  {	a = '-'; shift = 1; }
+	if (a=='+')  {	a = '='; shift = 1; }
+	if (a=='{')  {	a = '['; shift = 1; }
+	if (a=='}')  {	a = ']'; shift = 1; }
+	if (a==':')  {	a = ';'; shift = 1; }
+	if (a=='"')  {	a = '\''; shift = 1; }
+	if (a=='|')  {	a = '\\'; shift = 1; }
+	if (a=='<')  {	a = ','; shift = 1; }
+	if (a=='>')  {	a = '.'; shift = 1; }
+	if (a=='?')  {	a = '/'; shift = 1; }
+	if (a=='~')  {	a = '`'; shift = 1; }
+
+	if (shift)
+		pckbc_add_code(d, 0x2a, p);
+	else
+		pckbc_add_code(d, 0x2a + 0x80, p);
+
+	if (ctrl)
+		pckbc_add_code(d, 0x1d, p);
+
+	/*
+	 *  Note: The ugly hack used to add release codes for all of these
+	 *  keys is as follows:  we remember how much of the kbd buf that
+	 *  is in use here, before we add any scancode. After we've added
+	 *  one or more scancodes (ie an optional shift + another key)
+	 *  then we duplicate the last scancode | 0x80 _if_ the kbd buf
+	 *  was altered.
+	 */
+
+	old_head = d->head[p];
+
+	if (a==27)	pckbc_add_code(d, 0x01, p);
+
+	if (a=='1')	pckbc_add_code(d, 0x02, p);
+	if (a=='2')	pckbc_add_code(d, 0x03, p);
+	if (a=='3')	pckbc_add_code(d, 0x04, p);
+	if (a=='4')	pckbc_add_code(d, 0x05, p);
+	if (a=='5')	pckbc_add_code(d, 0x06, p);
+	if (a=='6')	pckbc_add_code(d, 0x07, p);
+	if (a=='7')	pckbc_add_code(d, 0x08, p);
+	if (a=='8')	pckbc_add_code(d, 0x09, p);
+	if (a=='9')	pckbc_add_code(d, 0x0a, p);
+	if (a=='0')	pckbc_add_code(d, 0x0b, p);
+	if (a=='-')	pckbc_add_code(d, 0x0c, p);
+	if (a=='=')	pckbc_add_code(d, 0x0d, p);
+
+	if (a=='!')  {	pckbc_add_code(d, 0x2a, p);
+			pckbc_add_code(d, 0x02, p); }
+	if (a=='@')  {	pckbc_add_code(d, 0x2a, p);
+			pckbc_add_code(d, 0x03, p); }
+	if (a=='#')  {	pckbc_add_code(d, 0x2a, p);
+			pckbc_add_code(d, 0x04, p); }
+	if (a=='$')  {	pckbc_add_code(d, 0x2a, p);
+			pckbc_add_code(d, 0x05, p); }
+	if (a=='%')  {	pckbc_add_code(d, 0x2a, p);
+			pckbc_add_code(d, 0x06, p); }
+	if (a=='^')  {	pckbc_add_code(d, 0x2a, p);
+			pckbc_add_code(d, 0x07, p); }
+	if (a=='&')  {	pckbc_add_code(d, 0x2a, p);
+			pckbc_add_code(d, 0x08, p); }
+	if (a=='*')  {	pckbc_add_code(d, 0x2a, p);
+			pckbc_add_code(d, 0x09, p); }
+	if (a=='(')  {	pckbc_add_code(d, 0x2a, p);
+			pckbc_add_code(d, 0x0a, p); }
+
+	if (a=='\b')	pckbc_add_code(d, 0x0e, p);
+
+	if (a=='\t')	pckbc_add_code(d, 0x0f, p);
+	if (a=='q')	pckbc_add_code(d, 0x10, p);
+	if (a=='w')	pckbc_add_code(d, 0x11, p);
+	if (a=='e')	pckbc_add_code(d, 0x12, p);
+	if (a=='r')	pckbc_add_code(d, 0x13, p);
+	if (a=='t')	pckbc_add_code(d, 0x14, p);
+	if (a=='y')	pckbc_add_code(d, 0x15, p);
+	if (a=='u')	pckbc_add_code(d, 0x16, p);
+	if (a=='i')	pckbc_add_code(d, 0x17, p);
+	if (a=='o')	pckbc_add_code(d, 0x18, p);
+	if (a=='p')	pckbc_add_code(d, 0x19, p);
+
+	if (a=='[')	pckbc_add_code(d, 0x1a, p);
+	if (a==']')	pckbc_add_code(d, 0x1b, p);
+
+	if (a=='\n' || a=='\r')	pckbc_add_code(d, 0x1c, p);
+
+	if (a=='a')	pckbc_add_code(d, 0x1e, p);
+	if (a=='s')	pckbc_add_code(d, 0x1f, p);
+	if (a=='d')	pckbc_add_code(d, 0x20, p);
+	if (a=='f')	pckbc_add_code(d, 0x21, p);
+	if (a=='g')	pckbc_add_code(d, 0x22, p);
+	if (a=='h')	pckbc_add_code(d, 0x23, p);
+	if (a=='j')	pckbc_add_code(d, 0x24, p);
+	if (a=='k')	pckbc_add_code(d, 0x25, p);
+	if (a=='l')	pckbc_add_code(d, 0x26, p);
+
+	if (a==';')	pckbc_add_code(d, 0x27, p);
+	if (a=='\'')	pckbc_add_code(d, 0x28, p);
+	if (a=='`')	pckbc_add_code(d, 0x29, p);
+	if (a=='\\')	pckbc_add_code(d, 0x2b, p);
+
+	if (a=='z')	pckbc_add_code(d, 0x2c, p);
+	if (a=='x')	pckbc_add_code(d, 0x2d, p);
+	if (a=='c')	pckbc_add_code(d, 0x2e, p);
+	if (a=='v')	pckbc_add_code(d, 0x2f, p);
+	if (a=='b')	pckbc_add_code(d, 0x30, p);
+	if (a=='n')	pckbc_add_code(d, 0x31, p);
+	if (a=='m')	pckbc_add_code(d, 0x32, p);
+
+	if (a==',')	pckbc_add_code(d, 0x33, p);
+	if (a=='.')	pckbc_add_code(d, 0x34, p);
+	if (a=='/')	pckbc_add_code(d, 0x35, p);
+
+	if (a==' ')	pckbc_add_code(d, 0x39, p);
+
+	/*  Add release code, if a key was pressed:  */
+	if (d->head[p] != old_head) {
+		int code = d->key_queue[p][d->head[p]] | 0x80;
+		pckbc_add_code(d, code, p);
+	}
+
+	/*  Release ctrl:  */
+	if (ctrl)
+		pckbc_add_code(d, 0x1d + 0x80, p);
+}
+
+
+/*
+ *  ascii_to_scancodes_type2():
+ *
+ *  Conversion from ASCII codes to default (US) keyboard scancodes.
+ */
+static void ascii_to_pc_scancodes_type2(int a, struct pckbc_data *d)
+{
+	int old_head;
+	int p = 0;	/*  port  */
+	int shift = 0, ctrl = 0;
+
+	if (a >= 'A' && a <= 'Z') { a += 32; shift = 1; }
+	if ((a >= 1 && a <= 26) && (a!='\n' && a!='\t' && a!='\b' && a!='\r'))
+		{ a += 96; ctrl = 1; }
+	if (a=='!')  {	a = '1'; shift = 1; }
+	if (a=='@')  {	a = '2'; shift = 1; }
+	if (a=='#')  {	a = '3'; shift = 1; }
+	if (a=='$')  {	a = '4'; shift = 1; }
+	if (a=='%')  {	a = '5'; shift = 1; }
+	if (a=='^')  {	a = '6'; shift = 1; }
+	if (a=='&')  {	a = '7'; shift = 1; }
+	if (a=='*')  {	a = '8'; shift = 1; }
+	if (a=='(')  {	a = '9'; shift = 1; }
+	if (a==')')  {	a = '0'; shift = 1; }
+	if (a=='_')  {	a = '-'; shift = 1; }
+	if (a=='+')  {	a = '='; shift = 1; }
+	if (a=='{')  {	a = '['; shift = 1; }
+	if (a=='}')  {	a = ']'; shift = 1; }
+	if (a==':')  {	a = ';'; shift = 1; }
+	if (a=='"')  {	a = '\''; shift = 1; }
+	if (a=='|')  {	a = '\\'; shift = 1; }
+	if (a=='<')  {	a = ','; shift = 1; }
+	if (a=='>')  {	a = '.'; shift = 1; }
+	if (a=='?')  {	a = '/'; shift = 1; }
+	if (a=='~')  {	a = '`'; shift = 1; }
+
+	if (shift)
+		pckbc_add_code(d, 0x12, p);
+	if (ctrl)
+		pckbc_add_code(d, 0x14, p);
+
+	/*
+	 *  Note: The ugly hack used to add release codes for all of these
+	 *  keys is as follows:  we remember how much of the kbd buf that
+	 *  is in use here, before we add any scancode. After we've added
+	 *  one or more scancodes (ie an optional shift + another key)
+	 *  then we add 0xf0 + the last scancode _if_ the kbd buf was altered.
+	 */
+
+	old_head = d->head[p];
+
+	if (a==27)	pckbc_add_code(d, 0x76, p);
+
+	if (a=='1')	pckbc_add_code(d, 0x16, p);
+	if (a=='2')	pckbc_add_code(d, 0x1e, p);
+	if (a=='3')	pckbc_add_code(d, 0x26, p);
+	if (a=='4')	pckbc_add_code(d, 0x25, p);
+	if (a=='5')	pckbc_add_code(d, 0x2e, p);
+	if (a=='6')	pckbc_add_code(d, 0x36, p);
+	if (a=='7')	pckbc_add_code(d, 0x3d, p);
+	if (a=='8')	pckbc_add_code(d, 0x3e, p);
+	if (a=='9')	pckbc_add_code(d, 0x46, p);
+	if (a=='0')	pckbc_add_code(d, 0x45, p);
+	if (a=='-')	pckbc_add_code(d, 0x4e, p);
+	if (a=='=')	pckbc_add_code(d, 0x55, p);
+
+	if (a=='\b')	pckbc_add_code(d, 0x66, p);
+
+	if (a=='\t')	pckbc_add_code(d, 0x0d, p);
+	if (a=='q')	pckbc_add_code(d, 0x15, p);
+	if (a=='w')	pckbc_add_code(d, 0x1d, p);
+	if (a=='e')	pckbc_add_code(d, 0x24, p);
+	if (a=='r')	pckbc_add_code(d, 0x2d, p);
+	if (a=='t')	pckbc_add_code(d, 0x2c, p);
+	if (a=='y')	pckbc_add_code(d, 0x35, p);
+	if (a=='u')	pckbc_add_code(d, 0x3c, p);
+	if (a=='i')	pckbc_add_code(d, 0x43, p);
+	if (a=='o')	pckbc_add_code(d, 0x44, p);
+	if (a=='p')	pckbc_add_code(d, 0x4d, p);
+
+	if (a=='[')	pckbc_add_code(d, 0x54, p);
+	if (a==']')	pckbc_add_code(d, 0x5b, p);
+
+	if (a=='\n' || a=='\r')	pckbc_add_code(d, 0x5a, p);
+
+	if (a=='a')	pckbc_add_code(d, 0x1c, p);
+	if (a=='s')	pckbc_add_code(d, 0x1b, p);
+	if (a=='d')	pckbc_add_code(d, 0x23, p);
+	if (a=='f')	pckbc_add_code(d, 0x2b, p);
+	if (a=='g')	pckbc_add_code(d, 0x34, p);
+	if (a=='h')	pckbc_add_code(d, 0x33, p);
+	if (a=='j')	pckbc_add_code(d, 0x3b, p);
+	if (a=='k')	pckbc_add_code(d, 0x42, p);
+	if (a=='l')	pckbc_add_code(d, 0x4b, p);
+
+	if (a==';')	pckbc_add_code(d, 0x4c, p);
+	if (a=='\'')	pckbc_add_code(d, 0x52, p);
+	if (a=='`')	pckbc_add_code(d, 0x0e, p);	// ?
+	if (a=='\\')	pckbc_add_code(d, 0x5d, p);	// 0x5c?
+
+	if (a=='z')	pckbc_add_code(d, 0x1a, p);
+	if (a=='x')	pckbc_add_code(d, 0x22, p);
+	if (a=='c')	pckbc_add_code(d, 0x21, p);
+	if (a=='v')	pckbc_add_code(d, 0x2a, p);
+	if (a=='b')	pckbc_add_code(d, 0x32, p);
+	if (a=='n')	pckbc_add_code(d, 0x31, p);
+	if (a=='m')	pckbc_add_code(d, 0x3a, p);
+
+	if (a==',')	pckbc_add_code(d, 0x41, p);
+	if (a=='.')	pckbc_add_code(d, 0x49, p);
+	if (a=='/')	pckbc_add_code(d, 0x4a, p);
+
+	if (a==' ')	pckbc_add_code(d, 0x29, p);
+
+	/*  Add release code, if a key was pressed:  */
+	if (d->head[p] != old_head) {
+		int code = d->key_queue[p][d->head[p]];
+		pckbc_add_code(d, 0xf0, p);
+		pckbc_add_code(d, code, p);
+	}
+
+	/*  Release shift and ctrl:  */
+	if (shift) {
+		pckbc_add_code(d, 0xf0, p);
+		pckbc_add_code(d, 0x12, p);
+	}
+	if (ctrl) {
+		pckbc_add_code(d, 0xf0, p);
+		pckbc_add_code(d, 0x14, p);
+	}
+}
+
+
+/*
+ *  ascii_to_scancodes_type3():
+ *
+ *  Conversion from ASCII codes to default (US) keyboard scancodes.
+ */
+static void ascii_to_pc_scancodes_type3(int a, struct pckbc_data *d)
+{
+	int old_head;
+	int p = 0;	/*  port  */
+	int shift = 0, ctrl = 0;
+
+	if (a >= 'A' && a <= 'Z') { a += 32; shift = 1; }
+	if ((a >= 1 && a <= 26) && (a!='\n' && a!='\t' && a!='\b' && a!='\r'))
+		{ a += 96; ctrl = 1; }
+	if (a=='!')  {	a = '1'; shift = 1; }
+	if (a=='@')  {	a = '2'; shift = 1; }
+	if (a=='#')  {	a = '3'; shift = 1; }
+	if (a=='$')  {	a = '4'; shift = 1; }
+	if (a=='%')  {	a = '5'; shift = 1; }
+	if (a=='^')  {	a = '6'; shift = 1; }
+	if (a=='&')  {	a = '7'; shift = 1; }
+	if (a=='*')  {	a = '8'; shift = 1; }
+	if (a=='(')  {	a = '9'; shift = 1; }
+	if (a==')')  {	a = '0'; shift = 1; }
+	if (a=='_')  {	a = '-'; shift = 1; }
+	if (a=='+')  {	a = '='; shift = 1; }
+	if (a=='{')  {	a = '['; shift = 1; }
+	if (a=='}')  {	a = ']'; shift = 1; }
+	if (a==':')  {	a = ';'; shift = 1; }
+	if (a=='"')  {	a = '\''; shift = 1; }
+	if (a=='|')  {	a = '\\'; shift = 1; }
+	if (a=='<')  {	a = ','; shift = 1; }
+	if (a=='>')  {	a = '.'; shift = 1; }
+	if (a=='?')  {	a = '/'; shift = 1; }
+	if (a=='~')  {	a = '`'; shift = 1; }
+
+	if (shift)
+		pckbc_add_code(d, 0x12, p);
+	if (ctrl)
+		pckbc_add_code(d, 0x11, p);
+
+	/*
+	 *  Note: The ugly hack used to add release codes for all of these
+	 *  keys is as follows:  we remember how much of the kbd buf that
+	 *  is in use here, before we add any scancode. After we've added
+	 *  one or more scancodes (ie an optional shift + another key)
+	 *  then we add 0xf0 + the last scancode _if_ the kbd buf was altered.
+	 */
+
+	old_head = d->head[p];
+
+	if (a==27)	pckbc_add_code(d, 0x08, p);
+
+	if (a=='1')	pckbc_add_code(d, 0x16, p);
+	if (a=='2')	pckbc_add_code(d, 0x1e, p);
+	if (a=='3')	pckbc_add_code(d, 0x26, p);
+	if (a=='4')	pckbc_add_code(d, 0x25, p);
+	if (a=='5')	pckbc_add_code(d, 0x2e, p);
+	if (a=='6')	pckbc_add_code(d, 0x36, p);
+	if (a=='7')	pckbc_add_code(d, 0x3d, p);
+	if (a=='8')	pckbc_add_code(d, 0x3e, p);
+	if (a=='9')	pckbc_add_code(d, 0x46, p);
+	if (a=='0')	pckbc_add_code(d, 0x45, p);
+	if (a=='-')	pckbc_add_code(d, 0x4e, p);
+	if (a=='=')	pckbc_add_code(d, 0x55, p);
+
+	if (a=='\b')	pckbc_add_code(d, 0x66, p);
+
+	if (a=='\t')	pckbc_add_code(d, 0x0d, p);
+	if (a=='q')	pckbc_add_code(d, 0x15, p);
+	if (a=='w')	pckbc_add_code(d, 0x1d, p);
+	if (a=='e')	pckbc_add_code(d, 0x24, p);
+	if (a=='r')	pckbc_add_code(d, 0x2d, p);
+	if (a=='t')	pckbc_add_code(d, 0x2c, p);
+	if (a=='y')	pckbc_add_code(d, 0x35, p);
+	if (a=='u')	pckbc_add_code(d, 0x3c, p);
+	if (a=='i')	pckbc_add_code(d, 0x43, p);
+	if (a=='o')	pckbc_add_code(d, 0x44, p);
+	if (a=='p')	pckbc_add_code(d, 0x4d, p);
+
+	if (a=='[')	pckbc_add_code(d, 0x54, p);
+	if (a==']')	pckbc_add_code(d, 0x5b, p);
+
+	if (a=='\n' || a=='\r')	pckbc_add_code(d, 0x5a, p);
+
+	if (a=='a')	pckbc_add_code(d, 0x1c, p);
+	if (a=='s')	pckbc_add_code(d, 0x1b, p);
+	if (a=='d')	pckbc_add_code(d, 0x23, p);
+	if (a=='f')	pckbc_add_code(d, 0x2b, p);
+	if (a=='g')	pckbc_add_code(d, 0x34, p);
+	if (a=='h')	pckbc_add_code(d, 0x33, p);
+	if (a=='j')	pckbc_add_code(d, 0x3b, p);
+	if (a=='k')	pckbc_add_code(d, 0x42, p);
+	if (a=='l')	pckbc_add_code(d, 0x4b, p);
+
+	if (a==';')	pckbc_add_code(d, 0x4c, p);
+	if (a=='\'')	pckbc_add_code(d, 0x52, p);
+	if (a=='`')	pckbc_add_code(d, 0x0e, p);	// ?
+	if (a=='\\')	pckbc_add_code(d, 0x5d, p);	// 0x5c?
+
+	if (a=='z')	pckbc_add_code(d, 0x1a, p);
+	if (a=='x')	pckbc_add_code(d, 0x22, p);
+	if (a=='c')	pckbc_add_code(d, 0x21, p);
+	if (a=='v')	pckbc_add_code(d, 0x2a, p);
+	if (a=='b')	pckbc_add_code(d, 0x32, p);
+	if (a=='n')	pckbc_add_code(d, 0x31, p);
+	if (a=='m')	pckbc_add_code(d, 0x3a, p);
+
+	if (a==',')	pckbc_add_code(d, 0x41, p);
+	if (a=='.')	pckbc_add_code(d, 0x49, p);
+	if (a=='/')	pckbc_add_code(d, 0x4a, p);
+
+	if (a==' ')	pckbc_add_code(d, 0x29, p);
+
+	/*  Add release code, if a key was pressed:  */
+	if (d->head[p] != old_head) {
+		int code = d->key_queue[p][d->head[p]];
+		pckbc_add_code(d, 0xf0, p);
+		pckbc_add_code(d, code, p);
+	}
+
+	/*  Release shift and ctrl:  */
+	if (shift) {
+		pckbc_add_code(d, 0xf0, p);
+		pckbc_add_code(d, 0x12, p);
+	}
+	if (ctrl) {
+		pckbc_add_code(d, 0xf0, p);
+		pckbc_add_code(d, 0x11, p);
+	}
+}
+
+
+void pckbc_reassert_interrupts(struct pckbc_data *d)
+{
+	int ints_enabled = 1;
+
+	// if (d->cmdbyte & KC8_KDISABLE)
+	//	ints_enabled = 0;
+
+	for (int port_nr = 0; port_nr < 2; port_nr++) {
+		/*
+		 *  Cause receive interrupt, if there's something in the
+		 *  receive buffer: (Otherwise deassert the interrupt.)
+		 */
+		if (d->head[port_nr] != d->tail[port_nr] && ints_enabled && d->rx_int_enable[port_nr]) {
+			if (!d->currently_asserted[port_nr]) {
+				// fatal("[ pckbc: interrupt port %i ]\n", port_nr);
+				if (port_nr == 0)
+					INTERRUPT_ASSERT(d->irq_keyboard);
+				else
+					INTERRUPT_ASSERT(d->irq_mouse);
+			}
+
+			d->currently_asserted[port_nr] = 1;
+		} else {
+			if (d->currently_asserted[port_nr]) {
+				// fatal("[ pckbc: DEASSERT interrupt port %i ]\n", port_nr);
+				if (port_nr == 0)
+					INTERRUPT_DEASSERT(d->irq_keyboard);
+				else
+					INTERRUPT_DEASSERT(d->irq_mouse);
+			}
+
+			d->currently_asserted[port_nr] = 0;
+		}
+	}
+}
+
+
+DEVICE_TICK(pckbc)
+{
+	struct pckbc_data *d = (struct pckbc_data *) extra;
+	int ch;
+
+	// Keyboard input:
+	if (d->in_use) {
+		while (console_charavail(d->console_handle)) {
+			ch = console_readchar(d->console_handle);
+			if (ch >= 0) {
+				switch (d->translation_table) {
+				case 1:	ascii_to_pc_scancodes_type1(ch, d);
+					break;
+				case 2:	ascii_to_pc_scancodes_type2(ch, d);
+					break;
+				case 3:	ascii_to_pc_scancodes_type3(ch, d);
+					break;
+				default:debugmsg(SUBSYS_DEVICE, "pckbc", VERBOSITY_WARNING,
+					    "unimplemented translation table type %i",
+					    d->translation_table);
+				}
+			}
+		}
+	}
+
+	// Mouse input:
+	/*  Don't do mouse updates if we're running in serial console mode:  */
+	if (cpu->machine->x11_md.in_use && d->state[1] == STATE_NORMAL && d->scanning_enabled[1]) {
+		int xdelta, ydelta, mouse_buttons, mouse_fb_nr;
+		console_getmouse(&xdelta, &ydelta, &mouse_buttons, &mouse_fb_nr);
+
+		ydelta = 0 - ydelta;
+
+		const int m = 100;
+
+		if (xdelta > m)
+			xdelta = m;
+		if (xdelta < -m)
+			xdelta = -m;
+		if (ydelta > m)
+			ydelta = m;
+		if (ydelta < -m)
+			ydelta = -m;
+
+		/*  Only send update if there is an actual diff.  */
+		if (xdelta != 0 || ydelta != 0 || d->mouse_buttons != mouse_buttons) {
+			d->mouse_buttons = mouse_buttons;
+
+			// See "The default protocol" at
+			// https://www.win.tue.nl/~aeb/linux/kbd/scancodes-13.html
+			uint8_t b1 = 0x08;
+			uint8_t b2 = xdelta;
+			uint8_t b3 = ydelta;
+
+			b1 |= (mouse_buttons & 4) >> 2;	// Left
+			b1 |= (mouse_buttons & 2) << 1;	// Middle
+			b1 |= (mouse_buttons & 1) << 1;	// Right
+			b1 |= ((xdelta >> 8) & 1) << 4;
+			b1 |= ((ydelta >> 8) & 1) << 5;
+
+			// printf("x=%i y=%i b1=%02x %02x %02x\n", xdelta, ydelta, b1,b2,b3);
+
+			pckbc_add_code(d, b1, 1);
+			pckbc_add_code(d, b2, 1);
+			pckbc_add_code(d, b3, 1);
+		}
+	}
+
+	pckbc_reassert_interrupts(d);
+}
+
+
+/*
+ *  dev_pckbc_command():
+ *
+ *  Handle commands to the 8048 in the emulated keyboard.
+ */
+static void dev_pckbc_command(struct pckbc_data *d, int port_nr)
+{
+	int cmd = d->type == PCKBC_8242 ? d->reg[PS2_TXBUF] : d->reg[PC_CMD];
+
+#if 0
+	// Mouse port debugging:
+	if (port_nr == 1)
+		fatal("[ pckbc: (port %i) command 0x%02x ]\n", port_nr, cmd);
+#endif
+
+	if (d->state[port_nr] == STATE_WAITING_FOR_TRANSLTABLE) {
+		debug("[ pckbc: (port %i) switching to translation table "
+		    "0x%02x ]\n", port_nr, cmd);
+
+		switch (cmd) {
+		case 0:	// TODO. "Writing 0xf0 followed by 0 queries the mode,
+			//  resulting in a scancode byte 43, 41 or 3f from the
+			//  keyboard." according to
+			// https://www.win.tue.nl/~aeb/linux/kbd/scancodes-10.html#scancodesets
+			fatal("[ pckbc: TODO: return current translation table ]\n");
+			break;
+		case 1:	// Fall-through.
+		case 2:	// Fall-through.
+		case 3:	d->translation_table = cmd;
+			break;
+		default:fatal("[ pckbc: (port %i) translation table "
+			    "0x%02x is NOT YET IMPLEMENTED ]\n",
+			    port_nr, cmd);
+		}
+
+		// Hack for OpenBSD/cats and NetBSD/cats:
+		if (d->type != PCKBC_8242) {
+			fatal("[ pckbc: TODO: hack for non-8242. figure out how to deal with this ]\n");
+			d->translation_table = 1;
+		}
+
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		d->state[port_nr] = STATE_NORMAL;
+		return;
+	}
+
+	if (d->state[port_nr] == STATE_WAITING_FOR_RATE) {
+		debug("[ pckbc: (port %i) received Typematic/Sample Rate data: "
+		    "0x%02x ]\n", port_nr, cmd);
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		d->state[port_nr] = STATE_NORMAL;
+		return;
+	}
+
+	if (d->state[port_nr] == STATE_WAITING_FOR_ONEKEY_MB) {
+		debug("[ pckbc: (port %i) received One-key make/break data: "
+		    "0x%02x ]\n", port_nr, cmd);
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		d->state[port_nr] = STATE_NORMAL;
+		return;
+	}
+
+	if (d->state[port_nr] == STATE_WAITING_FOR_AUX) {
+		debug("[ pckbc: (port %i) received aux data: "
+		    "0x%02x ]\n", port_nr, cmd);
+		/*  Echo back.  */
+		pckbc_add_code(d, cmd, port_nr);
+		d->state[port_nr] = STATE_NORMAL;
+		return;
+	}
+
+	if (d->state[port_nr] == STATE_WAITING_FOR_AUX_OUT) {
+		debug("[ pckbc: (port %i) received aux out data: "
+		    "0x%02x ]\n", port_nr, cmd);
+		/*  Echo back.  */
+		pckbc_add_code(d, cmd, port_nr);
+		d->state[port_nr] = STATE_NORMAL;
+		return;
+	}
+
+	switch (cmd) {
+
+	case 0x00:
+		/*
+		 *  TODO: What does this do? This is possibly due to an
+		 *  error in the handling of some other command code.
+		 */
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		break;
+
+	case KBC_MODEIND:	/*  Set LEDs  */
+		/*  Just ACK, no LEDs are actually set.  */
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		break;
+
+	case KBC_ECHO:
+		pckbc_add_code(d, KBR_ECHO, port_nr);
+		break;
+
+	case KBC_SETTABLE:
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		d->state[port_nr] = STATE_WAITING_FOR_TRANSLTABLE;
+		break;
+
+	case KBC_ENABLE:
+		d->scanning_enabled[port_nr] = 1;
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		break;
+
+	case KBC_DISABLE:
+		d->scanning_enabled[port_nr] = 0;
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		break;
+
+	case KBC_SETDEFAULT:
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		break;
+
+	case KBC_GETID:
+		/*  Get keyboard/mouse ID.  NOTE/TODO: Ugly hardcoded answer.  */
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		
+		if (port_nr == 0) {
+			// Keyboard:
+			pckbc_add_code(d, 0xab, port_nr);
+			pckbc_add_code(d, 0x41, port_nr);
+		} else {
+			// Mouse:
+			pckbc_add_code(d, 0x00, port_nr);
+			pckbc_add_code(d, 0x00, port_nr);
+		}
+		break;
+
+	case KBC_TYPEMATIC:
+		/*
+		 *  Keyboard: Set typematic (auto-repeat) delay/speed.
+		 *  PS/2 mouse: Set sample ratre.
+		 */
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		d->state[port_nr] = STATE_WAITING_FOR_RATE;
+		break;
+
+	case KBC_ALLKEYS_TMB:
+		/*  "Make all keys typematic/make/break"  */
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		break;
+
+	case KBC_ONEKEY_MB:
+		/*  "Make one key typematic/make/break"  */
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		d->state[port_nr] = STATE_WAITING_FOR_ONEKEY_MB;
+		break;
+
+	case KBC_RESET:
+		pckbc_add_code(d, KBR_ACK, port_nr);
+		pckbc_add_code(d, KBR_RSTDONE, port_nr);
+
+		if (port_nr == 1) {
+			// Mouse (based on NetBSD's pckbport/pms.c) sends
+			// mouse ID after RSTDONE:
+			pckbc_add_code(d, 0x00, port_nr);
+		}
+
+		/*
+		 *  Disable interrupts during reset, or Linux 2.6
+		 *  prints warnings about spurious interrupts.
+		 */
+		// d->rx_int_enable = 0;
+		d->scanning_enabled[port_nr] = 0;
+		break;
+
+	default:
+		pckbc_add_code(d, KBR_RESEND, port_nr); // Error
+		debugmsg(SUBSYS_DEVICE, "pckbc", VERBOSITY_WARNING,
+		    "UNIMPLEMENTED command 0x%02x (port %i)", cmd, port_nr);
+	}
+}
+
+
+DEVICE_ACCESS(pckbc)
+{
+	struct pckbc_data *d = (struct pckbc_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int port_nr = 0;
+	size_t i;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+#ifdef PCKBC_DEBUG
+	if (writeflag == MEM_WRITE)
+		fatal("[ pckbc: write to addr 0x%x: 0x%x ]\n",
+		    (int)relative_addr, (int)idata);
+	else
+		fatal("[ pckbc: read from addr 0x%x ]\n",
+		    (int)relative_addr);
+#endif
+
+	/*  For JAZZ-based machines:  */
+	if (relative_addr >= 0x60) {
+		relative_addr -= 0x60;
+		if (relative_addr != 0)
+			relative_addr = 1;
+	} else if (d->type == PCKBC_8242) {
+		/*  8242 PS2-style:  */
+		/*  when using 8-byte alignment...  */
+		relative_addr /= sizeof(uint64_t);
+		/*  port_nr = 0 for keyboard, 1 for mouse  */
+		port_nr = (relative_addr >> 2);
+		relative_addr &= 3;
+		relative_addr += PS2;
+	} else if (d->pc_style_flag) {
+		/*  PC-style:  */
+		if (relative_addr != 0 && relative_addr != 4) {
+			/*  TODO (port 0x61)  */
+			odata = 0x21;
+{
+static int x = 0;
+x++;
+if (x&1)
+			odata ^= 0x10;
+}
+			if (writeflag == MEM_READ)
+				memory_writemax64(cpu, data, len, odata);
+			return 1;
+		}
+		if (relative_addr != 0)
+			relative_addr = 1;
+	} else {
+		/*  Others... Non-Jazz ARC-based machines etc.  */
+		if (relative_addr != 0)
+			relative_addr = 1;
+	}
+
+	switch (relative_addr) {
+
+	/*
+	 *  8042 (PC):
+	 */
+
+	case 0:		/*  data  */
+		if (writeflag==MEM_READ) {
+			switch (d->state[port_nr]) {
+			case STATE_RDCMDBYTE:
+				odata = d->cmdbyte;
+				d->state[port_nr] = STATE_NORMAL;
+				break;
+			case STATE_RDOUTPUT:
+				odata = d->output_byte;
+				d->state[port_nr] = STATE_NORMAL;
+				break;
+			default:if (d->head[0] != d->tail[0]) {
+					odata = pckbc_get_code(d, 0);
+					d->last_scancode = odata;
+				} else {
+					odata = d->last_scancode;
+					d->last_scancode |= 0x80;
+				}
+			}
+			/*  debug("[ pckbc: read from DATA: 0x%02x ]\n",
+			    (int)odata);  */
+		} else {
+			if (port_nr == 1) {
+				fatal("[ pckbc: write to DATA:");
+				for (i=0; i<len; i++)
+					fatal(" %02x", data[i]);
+				fatal(" ]\n");
+			}
+			
+			switch (d->state[port_nr]) {
+			case STATE_LDCMDBYTE:
+				d->cmdbyte = idata;
+				d->rx_int_enable[port_nr] = d->cmdbyte &
+				    (KC8_KENABLE | KC8_MENABLE) ? 1 : 0;
+				d->state[port_nr] = STATE_NORMAL;
+				break;
+			case STATE_LDOUTPUT:
+				d->output_byte = idata;
+				d->state[port_nr] = STATE_NORMAL;
+				break;
+			default:d->reg[relative_addr] = idata;
+				dev_pckbc_command(d, port_nr);
+			}
+		}
+		break;
+	case 1:		/*  control  */
+		if (writeflag==MEM_READ) {
+			odata = 0;
+
+			/*  "Data in buffer" bit  */
+			if (d->head[0] != d->tail[0] ||
+			    d->state[port_nr] == STATE_RDCMDBYTE ||
+			    d->state[port_nr] == STATE_RDOUTPUT)
+				odata |= KBS_DIB;
+
+			if (d->state[port_nr] == STATE_RDCMDBYTE)
+				odata |= KBS_OCMD;
+
+			odata |= KBS_NOSEC;
+			/*  debug("[ pckbc: read from CTL status port: "
+			    "0x%02x ]\n", (int)odata);  */
+		} else {
+			debug("[ pckbc: write to CTL:");
+			for (i=0; i<len; i++)
+				debug(" %02x", data[i]);
+			debug(" ]\n");
+			d->reg[relative_addr] = idata;
+
+			switch (idata) {
+			case 0x10:
+			case 0x11:
+				/*  TODO: For now, don't print warnings about
+				    these. NetBSD sends these.  */
+				break;
+			case K_RDCMDBYTE:
+				d->state[port_nr] = STATE_RDCMDBYTE;
+				break;
+			case K_LDCMDBYTE:
+				d->state[port_nr] = STATE_LDCMDBYTE;
+				break;
+			case 0xa7:
+				d->cmdbyte |= KC8_MDISABLE;
+				break;
+			case 0xa8:
+				d->cmdbyte &= ~KC8_MDISABLE;
+				break;
+			case 0xa9:	/*  test auxiliary port  */
+				debug("[ pckbc: CONTROL 0xa9, TODO ]\n");
+				break;
+			case 0xaa:	/*  keyboard self-test  */
+				pckbc_add_code(d, 0x55, port_nr);
+				break;
+			case 0xab:	/*  keyboard interface self-test  */
+				pckbc_add_code(d, 0x00, port_nr);
+				break;
+			case 0xad:
+				d->cmdbyte |= KC8_KDISABLE;
+				break;
+			case 0xae:
+				d->cmdbyte &= ~KC8_KDISABLE;
+				break;
+			case 0xd0:
+				d->state[port_nr] = STATE_RDOUTPUT;
+				break;
+			case 0xd1:
+				d->state[port_nr] = STATE_LDOUTPUT;
+				break;
+			case 0xd3:	/*  write to auxiliary device
+					    output buffer  */
+				debug("[ pckbc: CONTROL 0xd3, TODO ]\n");
+				d->state[port_nr] = STATE_WAITING_FOR_AUX_OUT;
+				break;
+			case 0xd4:	/*  write to auxiliary port  */
+				debug("[ pckbc: CONTROL 0xd4, TODO ]\n");
+				d->state[port_nr] = STATE_WAITING_FOR_AUX;
+				break;
+			default:
+				fatal("[ pckbc: unknown CONTROL 0x%x ]\n",
+				    (int)idata);
+				d->state[port_nr] = STATE_NORMAL;
+			}
+		}
+		break;
+
+	/*
+	 *  8242 (PS2):
+	 */
+
+	case PS2 + PS2_TXBUF:
+		if (writeflag==MEM_READ) {
+			odata = random() & 0xff;
+			debug("[ pckbc: read from port %i, PS2_TXBUF: "
+			    "0x%x ]\n", port_nr, (int)odata);
+		} else {
+			debug("[ pckbc: write to port %i, PS2_TXBUF: "
+			    "0x%llx ]\n", port_nr, (long long)idata);
+
+			/*  Handle keyboard commands:  */
+			d->reg[PS2_TXBUF] = idata;
+			dev_pckbc_command(d, port_nr);
+		}
+		break;
+
+	case PS2 + PS2_RXBUF:
+		if (writeflag==MEM_READ) {
+			/*  TODO: What should be returned if no data 
+			    is available?  */
+			odata = 0;
+			if (d->head[port_nr] != d->tail[port_nr])
+				odata = pckbc_get_code(d, port_nr);
+			debug("[ pckbc: read from port %i, PS2_RXBUF: "
+			    "0x%02x ]\n", port_nr, (int)odata);
+		} else {
+			debug("[ pckbc: write to port %i, PS2_RXBUF: "
+			    "0x%llx ]\n", port_nr, (long long)idata);
+		}
+		break;
+
+	case PS2 + PS2_CONTROL:
+		if (writeflag==MEM_READ) {
+			debug("[ pckbc: read from port %i, PS2_CONTROL"
+			    " ]\n", port_nr);
+		} else {
+			debug("[ pckbc: write to port %i, PS2_CONTROL:"
+			    " 0x%llx ]\n", port_nr, (long long)idata);
+			d->clocksignal = (idata & 0x10) ? 1 : 0;
+			d->rx_int_enable[port_nr] = (idata & PS2_CONTROL_RXINTEN) ? 1 : 0;
+			d->tx_int_enable[port_nr] = (idata & PS2_CONTROL_TXINTEN) ? 1 : 0;
+
+			// HACK/TODO: NetBSD/sgimips' X11 seems to work when
+			// interrupts are enabled, but it seems to not turn
+			// them on. Having this here makes it work, but it not
+			// the correct solution.
+			if (port_nr == 1) {
+				d->rx_int_enable[port_nr] = 1;
+			}
+		}
+		break;
+
+	case PS2 + PS2_STATUS:
+		if (writeflag==MEM_READ) {
+			odata = d->clocksignal + PS2_STATUS_TXEMPTY;
+
+			if (d->head[port_nr] != d->tail[port_nr]) {
+				/*  receiced data available  */
+				odata |= PS2_STATUS_RXFULL;
+			}
+
+			//debug("[ pckbc: read from port %i, PS2_STATUS: "
+			//    "0x%llx ]\n", port_nr, (long long)odata);
+		} else {
+			debug("[ pckbc: write to port %i, PS2_STATUS: "
+			    "0x%llx ]\n", port_nr, (long long)idata);
+		}
+		break;
+
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ pckbc: read from unimplemented reg %i ]\n",
+			    (int)relative_addr);
+			odata = d->reg[relative_addr % DEV_PCKBC_LENGTH];
+		} else {
+			debug("[ pckbc: write to unimplemented reg %i:",
+			    (int)relative_addr);
+			for (i=0; i<len; i++)
+				debug(" %02x", data[i]);
+			debug(" ]\n");
+			d->reg[relative_addr % DEV_PCKBC_LENGTH] = idata;
+		}
+	}
+
+	/*  SGI? TODO: fix  */
+#if 0
+	if (len == 8)
+		odata |= (odata << 8) | (odata << 16) | (odata << 24) |
+		    (odata << 32) | (odata << 40) | (odata << 48) |
+		    (odata << 56);
+#endif
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	pckbc_reassert_interrupts(d);
+
+	return 1;
+}
+
+
+/*
+ *  dev_pckbc_init():
+ *
+ *  Type should be PCKBC_8042 or PCKBC_8242.
+ */
+int dev_pckbc_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, int type, char *keyboard_irqpath,
+	char *mouse_irqpath, int in_use, int pc_style_flag)
+{
+	struct pckbc_data *d;
+	int len = DEV_PCKBC_LENGTH;
+
+	CHECK_ALLOCATION(d = (struct pckbc_data *) malloc(sizeof(struct pckbc_data)));
+	memset(d, 0, sizeof(struct pckbc_data));
+
+	d->translation_table = 2;
+
+	if (type == PCKBC_8242) {
+		len = 0x40;
+		d->translation_table = 3;
+	}
+	
+	if (type == PCKBC_JAZZ) {
+		type = PCKBC_8042;
+		len = DEV_PCKBC_LENGTH + 0x60;
+	}
+
+	INTERRUPT_CONNECT(keyboard_irqpath, d->irq_keyboard);
+	INTERRUPT_CONNECT(mouse_irqpath, d->irq_mouse);
+
+	d->type              = type;
+	d->in_use            = in_use;
+	d->pc_style_flag     = pc_style_flag;
+	d->rx_int_enable[0]  = 1;
+	d->rx_int_enable[1]  = 0;
+	d->output_byte       = 0x02;	/*  A20 enable on PCs  */
+
+	// Default is ENABLE keyboard but DISABLE mouse port:
+	d->scanning_enabled[0] = 1;
+	d->scanning_enabled[1] = 0;
+
+	d->console_handle = console_start_slave_inputonly(
+	    machine, "pckbc", d->in_use);
+
+	memory_device_register(mem, "pckbc", baseaddr,
+	    len, dev_pckbc_access, d, DM_DEFAULT, NULL);
+	machine_add_tickfunction(machine, dev_pckbc_tick, d,
+	    PCKBC_TICKSHIFT);
+
+	return d->console_handle;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_pckbc.cc gxemul-0.7.0+dfsg/src/devices/dev_pckbc.cc
--- gxemul-0.6.2/src/devices/dev_pckbc.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pckbc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1203 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: 8042 PC keyboard controller (+ 8242WB Keyboard/Mouse controller)
- *
- *  This module includes emulation of the 8048 keyboard chip too.
- *
- *  Quick source of good info: http://my.execpc.com/~geezer/osd/kbd/kbd.txt
- *
- *  Some scancode listings for various types:
- *	http://www.win.tue.nl/~aeb/linux/kbd/scancodes-1.html
- *	http://www.computer-engineering.org/ps2keyboard/scancodes3.html
- *	https://www.win.tue.nl/~aeb/linux/kbd/scancodes-10.html#scancodesets
- *	http://nixdoc.net/man-pages/irix/man7/pckeyboard.7.html
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/kbdreg.h"
-
-
-// #define PCKBC_DEBUG
-// #define debug fatal
-
-
-// Should be 256 to emulate a real 8042? Having a larger value allows
-// pasting of larger text chunks which is useful in the emulator.
-// #define	MAX_8042_QUEUELEN	256
-#define	MAX_8042_QUEUELEN	32768
-
-#define	PC_DATA			0
-#define	PC_CMD			0
-#define	PC_STATUS		1
-
-#define	PS2_TXBUF		0
-#define	PS2_RXBUF		1
-#define	PS2_CONTROL		2
-#define         PS2_CONTROL_TXINTEN   (1 << 2)
-#define         PS2_CONTROL_RXINTEN   (1 << 3)
-#define	PS2_STATUS		3
-#define         PS2_STATUS_TXEMPTY    (1 << 3)
-#define         PS2_STATUS_RXFULL     (1 << 4)
-
-#define	PS2	100	// internal offset
-
-#define	PCKBC_TICKSHIFT		15
-
-
-struct pckbc_data {
-	int		console_handle;
-	int		in_use;
-
-	int		reg[DEV_PCKBC_LENGTH];
-
-	struct interrupt irq_keyboard;
-	struct interrupt irq_mouse;
-	int		currently_asserted[2];
-	int		type;
-	int		pc_style_flag;
-
-	/*  TODO: one of these for each port?  */
-	int		clocksignal;
-	int		rx_int_enable[2];
-	int		tx_int_enable[2];
-
-	int		scanning_enabled[2];
-	int		translation_table;
-	int		state[2];
-	int		cmdbyte;
-	int		output_byte;
-	int		last_scancode;
-
-	unsigned	key_queue[2][MAX_8042_QUEUELEN];
-	int		head[2], tail[2];
-
-	int		mouse_x;
-	int		mouse_y;
-	int		mouse_buttons;
-};
-
-#define	STATE_NORMAL			0
-#define	STATE_LDCMDBYTE			1
-#define	STATE_RDCMDBYTE			2
-#define	STATE_WAITING_FOR_TRANSLTABLE	3
-#define	STATE_WAITING_FOR_RATE		4
-#define	STATE_WAITING_FOR_ONEKEY_MB	5
-#define	STATE_WAITING_FOR_AUX		6
-#define	STATE_WAITING_FOR_AUX_OUT	7
-#define	STATE_LDOUTPUT			8
-#define	STATE_RDOUTPUT			9
-
-
-/*
- *  pckbc_add_code():
- *
- *  Adds a byte to the data queue.
- */
-void pckbc_add_code(struct pckbc_data *d, int code, int port)
-{
-	/*  Add at the head, read at the tail:  */
-	d->head[port] = (d->head[port]+1) % MAX_8042_QUEUELEN;
-	if (d->head[port] == d->tail[port])
-		fatal("[ pckbc: queue overrun, port %i! ]\n", port);
-
-	d->key_queue[port][d->head[port]] = code;
-}
-
-
-/*
- *  pckbc_get_code():
- *
- *  Reads a byte from a data queue.
- */
-int pckbc_get_code(struct pckbc_data *d, int port)
-{
-	if (d->head[port] == d->tail[port])
-		fatal("[ pckbc: queue empty, port %i! ]\n", port);
-	else
-		d->tail[port] = (d->tail[port]+1) % MAX_8042_QUEUELEN;
-
-	return d->key_queue[port][d->tail[port]];
-}
-
-
-/*
- *  ascii_to_scancodes_type1():
- *
- *  Conversion from ASCII codes to default (US) keyboard scancodes.
- */
-static void ascii_to_pc_scancodes_type1(int a, struct pckbc_data *d)
-{
-	int old_head;
-	int p = 0;	/*  port  */
-	int shift = 0, ctrl = 0;
-
-	if (a >= 'A' && a <= 'Z') { a += 32; shift = 1; }
-	if ((a >= 1 && a <= 26) && (a!='\n' && a!='\t' && a!='\b' && a!='\r'))
-		{ a += 96; ctrl = 1; }
-
-	if (a=='!')  {	a = '1'; shift = 1; }
-	if (a=='@')  {	a = '2'; shift = 1; }
-	if (a=='#')  {	a = '3'; shift = 1; }
-	if (a=='$')  {	a = '4'; shift = 1; }
-	if (a=='%')  {	a = '5'; shift = 1; }
-	if (a=='^')  {	a = '6'; shift = 1; }
-	if (a=='&')  {	a = '7'; shift = 1; }
-	if (a=='*')  {	a = '8'; shift = 1; }
-	if (a=='(')  {	a = '9'; shift = 1; }
-	if (a==')')  {	a = '0'; shift = 1; }
-	if (a=='_')  {	a = '-'; shift = 1; }
-	if (a=='+')  {	a = '='; shift = 1; }
-	if (a=='{')  {	a = '['; shift = 1; }
-	if (a=='}')  {	a = ']'; shift = 1; }
-	if (a==':')  {	a = ';'; shift = 1; }
-	if (a=='"')  {	a = '\''; shift = 1; }
-	if (a=='|')  {	a = '\\'; shift = 1; }
-	if (a=='<')  {	a = ','; shift = 1; }
-	if (a=='>')  {	a = '.'; shift = 1; }
-	if (a=='?')  {	a = '/'; shift = 1; }
-	if (a=='~')  {	a = '`'; shift = 1; }
-
-	if (shift)
-		pckbc_add_code(d, 0x2a, p);
-	else
-		pckbc_add_code(d, 0x2a + 0x80, p);
-
-	if (ctrl)
-		pckbc_add_code(d, 0x1d, p);
-
-	/*
-	 *  Note: The ugly hack used to add release codes for all of these
-	 *  keys is as follows:  we remember how much of the kbd buf that
-	 *  is in use here, before we add any scancode. After we've added
-	 *  one or more scancodes (ie an optional shift + another key)
-	 *  then we duplicate the last scancode | 0x80 _if_ the kbd buf
-	 *  was altered.
-	 */
-
-	old_head = d->head[p];
-
-	if (a==27)	pckbc_add_code(d, 0x01, p);
-
-	if (a=='1')	pckbc_add_code(d, 0x02, p);
-	if (a=='2')	pckbc_add_code(d, 0x03, p);
-	if (a=='3')	pckbc_add_code(d, 0x04, p);
-	if (a=='4')	pckbc_add_code(d, 0x05, p);
-	if (a=='5')	pckbc_add_code(d, 0x06, p);
-	if (a=='6')	pckbc_add_code(d, 0x07, p);
-	if (a=='7')	pckbc_add_code(d, 0x08, p);
-	if (a=='8')	pckbc_add_code(d, 0x09, p);
-	if (a=='9')	pckbc_add_code(d, 0x0a, p);
-	if (a=='0')	pckbc_add_code(d, 0x0b, p);
-	if (a=='-')	pckbc_add_code(d, 0x0c, p);
-	if (a=='=')	pckbc_add_code(d, 0x0d, p);
-
-	if (a=='!')  {	pckbc_add_code(d, 0x2a, p);
-			pckbc_add_code(d, 0x02, p); }
-	if (a=='@')  {	pckbc_add_code(d, 0x2a, p);
-			pckbc_add_code(d, 0x03, p); }
-	if (a=='#')  {	pckbc_add_code(d, 0x2a, p);
-			pckbc_add_code(d, 0x04, p); }
-	if (a=='$')  {	pckbc_add_code(d, 0x2a, p);
-			pckbc_add_code(d, 0x05, p); }
-	if (a=='%')  {	pckbc_add_code(d, 0x2a, p);
-			pckbc_add_code(d, 0x06, p); }
-	if (a=='^')  {	pckbc_add_code(d, 0x2a, p);
-			pckbc_add_code(d, 0x07, p); }
-	if (a=='&')  {	pckbc_add_code(d, 0x2a, p);
-			pckbc_add_code(d, 0x08, p); }
-	if (a=='*')  {	pckbc_add_code(d, 0x2a, p);
-			pckbc_add_code(d, 0x09, p); }
-	if (a=='(')  {	pckbc_add_code(d, 0x2a, p);
-			pckbc_add_code(d, 0x0a, p); }
-
-	if (a=='\b')	pckbc_add_code(d, 0x0e, p);
-
-	if (a=='\t')	pckbc_add_code(d, 0x0f, p);
-	if (a=='q')	pckbc_add_code(d, 0x10, p);
-	if (a=='w')	pckbc_add_code(d, 0x11, p);
-	if (a=='e')	pckbc_add_code(d, 0x12, p);
-	if (a=='r')	pckbc_add_code(d, 0x13, p);
-	if (a=='t')	pckbc_add_code(d, 0x14, p);
-	if (a=='y')	pckbc_add_code(d, 0x15, p);
-	if (a=='u')	pckbc_add_code(d, 0x16, p);
-	if (a=='i')	pckbc_add_code(d, 0x17, p);
-	if (a=='o')	pckbc_add_code(d, 0x18, p);
-	if (a=='p')	pckbc_add_code(d, 0x19, p);
-
-	if (a=='[')	pckbc_add_code(d, 0x1a, p);
-	if (a==']')	pckbc_add_code(d, 0x1b, p);
-
-	if (a=='\n' || a=='\r')	pckbc_add_code(d, 0x1c, p);
-
-	if (a=='a')	pckbc_add_code(d, 0x1e, p);
-	if (a=='s')	pckbc_add_code(d, 0x1f, p);
-	if (a=='d')	pckbc_add_code(d, 0x20, p);
-	if (a=='f')	pckbc_add_code(d, 0x21, p);
-	if (a=='g')	pckbc_add_code(d, 0x22, p);
-	if (a=='h')	pckbc_add_code(d, 0x23, p);
-	if (a=='j')	pckbc_add_code(d, 0x24, p);
-	if (a=='k')	pckbc_add_code(d, 0x25, p);
-	if (a=='l')	pckbc_add_code(d, 0x26, p);
-
-	if (a==';')	pckbc_add_code(d, 0x27, p);
-	if (a=='\'')	pckbc_add_code(d, 0x28, p);
-	if (a=='`')	pckbc_add_code(d, 0x29, p);
-	if (a=='\\')	pckbc_add_code(d, 0x2b, p);
-
-	if (a=='z')	pckbc_add_code(d, 0x2c, p);
-	if (a=='x')	pckbc_add_code(d, 0x2d, p);
-	if (a=='c')	pckbc_add_code(d, 0x2e, p);
-	if (a=='v')	pckbc_add_code(d, 0x2f, p);
-	if (a=='b')	pckbc_add_code(d, 0x30, p);
-	if (a=='n')	pckbc_add_code(d, 0x31, p);
-	if (a=='m')	pckbc_add_code(d, 0x32, p);
-
-	if (a==',')	pckbc_add_code(d, 0x33, p);
-	if (a=='.')	pckbc_add_code(d, 0x34, p);
-	if (a=='/')	pckbc_add_code(d, 0x35, p);
-
-	if (a==' ')	pckbc_add_code(d, 0x39, p);
-
-	/*  Add release code, if a key was pressed:  */
-	if (d->head[p] != old_head) {
-		int code = d->key_queue[p][d->head[p]] | 0x80;
-		pckbc_add_code(d, code, p);
-	}
-
-	/*  Release ctrl:  */
-	if (ctrl)
-		pckbc_add_code(d, 0x1d + 0x80, p);
-}
-
-
-/*
- *  ascii_to_scancodes_type2():
- *
- *  Conversion from ASCII codes to default (US) keyboard scancodes.
- */
-static void ascii_to_pc_scancodes_type2(int a, struct pckbc_data *d)
-{
-	int old_head;
-	int p = 0;	/*  port  */
-	int shift = 0, ctrl = 0;
-
-	if (a >= 'A' && a <= 'Z') { a += 32; shift = 1; }
-	if ((a >= 1 && a <= 26) && (a!='\n' && a!='\t' && a!='\b' && a!='\r'))
-		{ a += 96; ctrl = 1; }
-	if (a=='!')  {	a = '1'; shift = 1; }
-	if (a=='@')  {	a = '2'; shift = 1; }
-	if (a=='#')  {	a = '3'; shift = 1; }
-	if (a=='$')  {	a = '4'; shift = 1; }
-	if (a=='%')  {	a = '5'; shift = 1; }
-	if (a=='^')  {	a = '6'; shift = 1; }
-	if (a=='&')  {	a = '7'; shift = 1; }
-	if (a=='*')  {	a = '8'; shift = 1; }
-	if (a=='(')  {	a = '9'; shift = 1; }
-	if (a==')')  {	a = '0'; shift = 1; }
-	if (a=='_')  {	a = '-'; shift = 1; }
-	if (a=='+')  {	a = '='; shift = 1; }
-	if (a=='{')  {	a = '['; shift = 1; }
-	if (a=='}')  {	a = ']'; shift = 1; }
-	if (a==':')  {	a = ';'; shift = 1; }
-	if (a=='"')  {	a = '\''; shift = 1; }
-	if (a=='|')  {	a = '\\'; shift = 1; }
-	if (a=='<')  {	a = ','; shift = 1; }
-	if (a=='>')  {	a = '.'; shift = 1; }
-	if (a=='?')  {	a = '/'; shift = 1; }
-	if (a=='~')  {	a = '`'; shift = 1; }
-
-	if (shift)
-		pckbc_add_code(d, 0x12, p);
-	if (ctrl)
-		pckbc_add_code(d, 0x14, p);
-
-	/*
-	 *  Note: The ugly hack used to add release codes for all of these
-	 *  keys is as follows:  we remember how much of the kbd buf that
-	 *  is in use here, before we add any scancode. After we've added
-	 *  one or more scancodes (ie an optional shift + another key)
-	 *  then we add 0xf0 + the last scancode _if_ the kbd buf was altered.
-	 */
-
-	old_head = d->head[p];
-
-	if (a==27)	pckbc_add_code(d, 0x76, p);
-
-	if (a=='1')	pckbc_add_code(d, 0x16, p);
-	if (a=='2')	pckbc_add_code(d, 0x1e, p);
-	if (a=='3')	pckbc_add_code(d, 0x26, p);
-	if (a=='4')	pckbc_add_code(d, 0x25, p);
-	if (a=='5')	pckbc_add_code(d, 0x2e, p);
-	if (a=='6')	pckbc_add_code(d, 0x36, p);
-	if (a=='7')	pckbc_add_code(d, 0x3d, p);
-	if (a=='8')	pckbc_add_code(d, 0x3e, p);
-	if (a=='9')	pckbc_add_code(d, 0x46, p);
-	if (a=='0')	pckbc_add_code(d, 0x45, p);
-	if (a=='-')	pckbc_add_code(d, 0x4e, p);
-	if (a=='=')	pckbc_add_code(d, 0x55, p);
-
-	if (a=='\b')	pckbc_add_code(d, 0x66, p);
-
-	if (a=='\t')	pckbc_add_code(d, 0x0d, p);
-	if (a=='q')	pckbc_add_code(d, 0x15, p);
-	if (a=='w')	pckbc_add_code(d, 0x1d, p);
-	if (a=='e')	pckbc_add_code(d, 0x24, p);
-	if (a=='r')	pckbc_add_code(d, 0x2d, p);
-	if (a=='t')	pckbc_add_code(d, 0x2c, p);
-	if (a=='y')	pckbc_add_code(d, 0x35, p);
-	if (a=='u')	pckbc_add_code(d, 0x3c, p);
-	if (a=='i')	pckbc_add_code(d, 0x43, p);
-	if (a=='o')	pckbc_add_code(d, 0x44, p);
-	if (a=='p')	pckbc_add_code(d, 0x4d, p);
-
-	if (a=='[')	pckbc_add_code(d, 0x54, p);
-	if (a==']')	pckbc_add_code(d, 0x5b, p);
-
-	if (a=='\n' || a=='\r')	pckbc_add_code(d, 0x5a, p);
-
-	if (a=='a')	pckbc_add_code(d, 0x1c, p);
-	if (a=='s')	pckbc_add_code(d, 0x1b, p);
-	if (a=='d')	pckbc_add_code(d, 0x23, p);
-	if (a=='f')	pckbc_add_code(d, 0x2b, p);
-	if (a=='g')	pckbc_add_code(d, 0x34, p);
-	if (a=='h')	pckbc_add_code(d, 0x33, p);
-	if (a=='j')	pckbc_add_code(d, 0x3b, p);
-	if (a=='k')	pckbc_add_code(d, 0x42, p);
-	if (a=='l')	pckbc_add_code(d, 0x4b, p);
-
-	if (a==';')	pckbc_add_code(d, 0x4c, p);
-	if (a=='\'')	pckbc_add_code(d, 0x52, p);
-	if (a=='`')	pckbc_add_code(d, 0x0e, p);	// ?
-	if (a=='\\')	pckbc_add_code(d, 0x5d, p);	// 0x5c?
-
-	if (a=='z')	pckbc_add_code(d, 0x1a, p);
-	if (a=='x')	pckbc_add_code(d, 0x22, p);
-	if (a=='c')	pckbc_add_code(d, 0x21, p);
-	if (a=='v')	pckbc_add_code(d, 0x2a, p);
-	if (a=='b')	pckbc_add_code(d, 0x32, p);
-	if (a=='n')	pckbc_add_code(d, 0x31, p);
-	if (a=='m')	pckbc_add_code(d, 0x3a, p);
-
-	if (a==',')	pckbc_add_code(d, 0x41, p);
-	if (a=='.')	pckbc_add_code(d, 0x49, p);
-	if (a=='/')	pckbc_add_code(d, 0x4a, p);
-
-	if (a==' ')	pckbc_add_code(d, 0x29, p);
-
-	/*  Add release code, if a key was pressed:  */
-	if (d->head[p] != old_head) {
-		int code = d->key_queue[p][d->head[p]];
-		pckbc_add_code(d, 0xf0, p);
-		pckbc_add_code(d, code, p);
-	}
-
-	/*  Release shift and ctrl:  */
-	if (shift) {
-		pckbc_add_code(d, 0xf0, p);
-		pckbc_add_code(d, 0x12, p);
-	}
-	if (ctrl) {
-		pckbc_add_code(d, 0xf0, p);
-		pckbc_add_code(d, 0x14, p);
-	}
-}
-
-
-/*
- *  ascii_to_scancodes_type3():
- *
- *  Conversion from ASCII codes to default (US) keyboard scancodes.
- */
-static void ascii_to_pc_scancodes_type3(int a, struct pckbc_data *d)
-{
-	int old_head;
-	int p = 0;	/*  port  */
-	int shift = 0, ctrl = 0;
-
-	if (a >= 'A' && a <= 'Z') { a += 32; shift = 1; }
-	if ((a >= 1 && a <= 26) && (a!='\n' && a!='\t' && a!='\b' && a!='\r'))
-		{ a += 96; ctrl = 1; }
-	if (a=='!')  {	a = '1'; shift = 1; }
-	if (a=='@')  {	a = '2'; shift = 1; }
-	if (a=='#')  {	a = '3'; shift = 1; }
-	if (a=='$')  {	a = '4'; shift = 1; }
-	if (a=='%')  {	a = '5'; shift = 1; }
-	if (a=='^')  {	a = '6'; shift = 1; }
-	if (a=='&')  {	a = '7'; shift = 1; }
-	if (a=='*')  {	a = '8'; shift = 1; }
-	if (a=='(')  {	a = '9'; shift = 1; }
-	if (a==')')  {	a = '0'; shift = 1; }
-	if (a=='_')  {	a = '-'; shift = 1; }
-	if (a=='+')  {	a = '='; shift = 1; }
-	if (a=='{')  {	a = '['; shift = 1; }
-	if (a=='}')  {	a = ']'; shift = 1; }
-	if (a==':')  {	a = ';'; shift = 1; }
-	if (a=='"')  {	a = '\''; shift = 1; }
-	if (a=='|')  {	a = '\\'; shift = 1; }
-	if (a=='<')  {	a = ','; shift = 1; }
-	if (a=='>')  {	a = '.'; shift = 1; }
-	if (a=='?')  {	a = '/'; shift = 1; }
-	if (a=='~')  {	a = '`'; shift = 1; }
-
-	if (shift)
-		pckbc_add_code(d, 0x12, p);
-	if (ctrl)
-		pckbc_add_code(d, 0x11, p);
-
-	/*
-	 *  Note: The ugly hack used to add release codes for all of these
-	 *  keys is as follows:  we remember how much of the kbd buf that
-	 *  is in use here, before we add any scancode. After we've added
-	 *  one or more scancodes (ie an optional shift + another key)
-	 *  then we add 0xf0 + the last scancode _if_ the kbd buf was altered.
-	 */
-
-	old_head = d->head[p];
-
-	if (a==27)	pckbc_add_code(d, 0x08, p);
-
-	if (a=='1')	pckbc_add_code(d, 0x16, p);
-	if (a=='2')	pckbc_add_code(d, 0x1e, p);
-	if (a=='3')	pckbc_add_code(d, 0x26, p);
-	if (a=='4')	pckbc_add_code(d, 0x25, p);
-	if (a=='5')	pckbc_add_code(d, 0x2e, p);
-	if (a=='6')	pckbc_add_code(d, 0x36, p);
-	if (a=='7')	pckbc_add_code(d, 0x3d, p);
-	if (a=='8')	pckbc_add_code(d, 0x3e, p);
-	if (a=='9')	pckbc_add_code(d, 0x46, p);
-	if (a=='0')	pckbc_add_code(d, 0x45, p);
-	if (a=='-')	pckbc_add_code(d, 0x4e, p);
-	if (a=='=')	pckbc_add_code(d, 0x55, p);
-
-	if (a=='\b')	pckbc_add_code(d, 0x66, p);
-
-	if (a=='\t')	pckbc_add_code(d, 0x0d, p);
-	if (a=='q')	pckbc_add_code(d, 0x15, p);
-	if (a=='w')	pckbc_add_code(d, 0x1d, p);
-	if (a=='e')	pckbc_add_code(d, 0x24, p);
-	if (a=='r')	pckbc_add_code(d, 0x2d, p);
-	if (a=='t')	pckbc_add_code(d, 0x2c, p);
-	if (a=='y')	pckbc_add_code(d, 0x35, p);
-	if (a=='u')	pckbc_add_code(d, 0x3c, p);
-	if (a=='i')	pckbc_add_code(d, 0x43, p);
-	if (a=='o')	pckbc_add_code(d, 0x44, p);
-	if (a=='p')	pckbc_add_code(d, 0x4d, p);
-
-	if (a=='[')	pckbc_add_code(d, 0x54, p);
-	if (a==']')	pckbc_add_code(d, 0x5b, p);
-
-	if (a=='\n' || a=='\r')	pckbc_add_code(d, 0x5a, p);
-
-	if (a=='a')	pckbc_add_code(d, 0x1c, p);
-	if (a=='s')	pckbc_add_code(d, 0x1b, p);
-	if (a=='d')	pckbc_add_code(d, 0x23, p);
-	if (a=='f')	pckbc_add_code(d, 0x2b, p);
-	if (a=='g')	pckbc_add_code(d, 0x34, p);
-	if (a=='h')	pckbc_add_code(d, 0x33, p);
-	if (a=='j')	pckbc_add_code(d, 0x3b, p);
-	if (a=='k')	pckbc_add_code(d, 0x42, p);
-	if (a=='l')	pckbc_add_code(d, 0x4b, p);
-
-	if (a==';')	pckbc_add_code(d, 0x4c, p);
-	if (a=='\'')	pckbc_add_code(d, 0x52, p);
-	if (a=='`')	pckbc_add_code(d, 0x0e, p);	// ?
-	if (a=='\\')	pckbc_add_code(d, 0x5d, p);	// 0x5c?
-
-	if (a=='z')	pckbc_add_code(d, 0x1a, p);
-	if (a=='x')	pckbc_add_code(d, 0x22, p);
-	if (a=='c')	pckbc_add_code(d, 0x21, p);
-	if (a=='v')	pckbc_add_code(d, 0x2a, p);
-	if (a=='b')	pckbc_add_code(d, 0x32, p);
-	if (a=='n')	pckbc_add_code(d, 0x31, p);
-	if (a=='m')	pckbc_add_code(d, 0x3a, p);
-
-	if (a==',')	pckbc_add_code(d, 0x41, p);
-	if (a=='.')	pckbc_add_code(d, 0x49, p);
-	if (a=='/')	pckbc_add_code(d, 0x4a, p);
-
-	if (a==' ')	pckbc_add_code(d, 0x29, p);
-
-	/*  Add release code, if a key was pressed:  */
-	if (d->head[p] != old_head) {
-		int code = d->key_queue[p][d->head[p]];
-		pckbc_add_code(d, 0xf0, p);
-		pckbc_add_code(d, code, p);
-	}
-
-	/*  Release shift and ctrl:  */
-	if (shift) {
-		pckbc_add_code(d, 0xf0, p);
-		pckbc_add_code(d, 0x12, p);
-	}
-	if (ctrl) {
-		pckbc_add_code(d, 0xf0, p);
-		pckbc_add_code(d, 0x11, p);
-	}
-}
-
-
-void pckbc_reassert_interrupts(struct pckbc_data *d)
-{
-	bool ints_enabled = true;
-
-	// if (d->cmdbyte & KC8_KDISABLE)
-	//	ints_enabled = false;
-
-	for (int port_nr = 0; port_nr < 2; port_nr++) {
-		/*
-		 *  Cause receive interrupt, if there's something in the
-		 *  receive buffer: (Otherwise deassert the interrupt.)
-		 */
-		if (d->head[port_nr] != d->tail[port_nr] && ints_enabled && d->rx_int_enable[port_nr]) {
-			if (!d->currently_asserted[port_nr]) {
-				// fatal("[ pckbc: interrupt port %i ]\n", port_nr);
-				if (port_nr == 0)
-					INTERRUPT_ASSERT(d->irq_keyboard);
-				else
-					INTERRUPT_ASSERT(d->irq_mouse);
-			}
-
-			d->currently_asserted[port_nr] = 1;
-		} else {
-			if (d->currently_asserted[port_nr]) {
-				// fatal("[ pckbc: DEASSERT interrupt port %i ]\n", port_nr);
-				if (port_nr == 0)
-					INTERRUPT_DEASSERT(d->irq_keyboard);
-				else
-					INTERRUPT_DEASSERT(d->irq_mouse);
-			}
-
-			d->currently_asserted[port_nr] = 0;
-		}
-	}
-}
-
-
-DEVICE_TICK(pckbc)
-{
-	struct pckbc_data *d = (struct pckbc_data *) extra;
-	int ch;
-
-	// Keyboard input:
-	if (d->in_use) {
-		while (console_charavail(d->console_handle)) {
-			ch = console_readchar(d->console_handle);
-			if (ch >= 0) {
-				switch (d->translation_table) {
-				case 1:	ascii_to_pc_scancodes_type1(ch, d);
-					break;
-				case 2:	ascii_to_pc_scancodes_type2(ch, d);
-					break;
-				case 3:	ascii_to_pc_scancodes_type3(ch, d);
-					break;
-				default:fatal("[ pckbc: unimplemented translation table type %i ]\n",
-						d->translation_table);
-				}
-			}
-		}
-	}
-
-	// Mouse input:
-	/*  Don't do mouse updates if we're running in serial console mode:  */
-	if (cpu->machine->x11_md.in_use && d->state[1] == STATE_NORMAL && d->scanning_enabled[1]) {
-		int mouse_x, mouse_y, mouse_buttons, mouse_fb_nr;
-		console_getmouse(&mouse_x, &mouse_y, &mouse_buttons, &mouse_fb_nr);
-
-		int xdelta = mouse_x - d->mouse_x;
-		int ydelta = d->mouse_y - mouse_y;	// note: inverted
-
-		const int m = 100;
-
-		if (xdelta > m)
-			xdelta = m;
-		if (xdelta < -m)
-			xdelta = -m;
-		if (ydelta > m)
-			ydelta = m;
-		if (ydelta < -m)
-			ydelta = -m;
-
-		/*  Only send update if there is an actual diff.  */
-		if (xdelta != 0 || ydelta != 0 || d->mouse_buttons != mouse_buttons) {
-			d->mouse_x = mouse_x;
-			d->mouse_y = mouse_y;
-			d->mouse_buttons = mouse_buttons;
-
-			// See "The default protocol" at
-			// https://www.win.tue.nl/~aeb/linux/kbd/scancodes-13.html
-			uint8_t b1 = 0x08;
-			uint8_t b2 = xdelta;
-			uint8_t b3 = ydelta;
-
-			b1 |= (mouse_buttons & 4) >> 2;	// Left
-			b1 |= (mouse_buttons & 2) << 1;	// Middle
-			b1 |= (mouse_buttons & 1) << 1;	// Right
-			b1 |= ((xdelta >> 8) & 1) << 4;
-			b1 |= ((ydelta >> 8) & 1) << 5;
-
-			// printf("x=%i y=%i b1=%02x %02x %02x\n", xdelta, ydelta, b1,b2,b3);
-
-			pckbc_add_code(d, b1, 1);
-			pckbc_add_code(d, b2, 1);
-			pckbc_add_code(d, b3, 1);
-		}
-	}
-
-	pckbc_reassert_interrupts(d);
-}
-
-
-/*
- *  dev_pckbc_command():
- *
- *  Handle commands to the 8048 in the emulated keyboard.
- */
-static void dev_pckbc_command(struct pckbc_data *d, int port_nr)
-{
-	int cmd = d->type == PCKBC_8242 ? d->reg[PS2_TXBUF] : d->reg[PC_CMD];
-
-#if 0
-	// Mouse port debugging:
-	if (port_nr == 1)
-		fatal("[ pckbc: (port %i) command 0x%02x ]\n", port_nr, cmd);
-#endif
-
-	if (d->state[port_nr] == STATE_WAITING_FOR_TRANSLTABLE) {
-		debug("[ pckbc: (port %i) switching to translation table "
-		    "0x%02x ]\n", port_nr, cmd);
-
-		switch (cmd) {
-		case 0:	// TODO. "Writing 0xf0 followed by 0 queries the mode,
-			//  resulting in a scancode byte 43, 41 or 3f from the
-			//  keyboard." according to
-			// https://www.win.tue.nl/~aeb/linux/kbd/scancodes-10.html#scancodesets
-			fatal("[ pckbc: TODO: return current translation table ]\n");
-			break;
-		case 1:	// Fall-through.
-		case 2:	// Fall-through.
-		case 3:	d->translation_table = cmd;
-			break;
-		default:fatal("[ pckbc: (port %i) translation table "
-			    "0x%02x is NOT YET IMPLEMENTED ]\n",
-			    port_nr, cmd);
-		}
-
-		// Hack for OpenBSD/cats and NetBSD/cats:
-		if (d->type != PCKBC_8242) {
-			fatal("[ pckbc: TODO: hack for non-8242. figure out how to deal with this ]\n");
-			d->translation_table = 1;
-		}
-
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		d->state[port_nr] = STATE_NORMAL;
-		return;
-	}
-
-	if (d->state[port_nr] == STATE_WAITING_FOR_RATE) {
-		debug("[ pckbc: (port %i) received Typematic/Sample Rate data: "
-		    "0x%02x ]\n", port_nr, cmd);
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		d->state[port_nr] = STATE_NORMAL;
-		return;
-	}
-
-	if (d->state[port_nr] == STATE_WAITING_FOR_ONEKEY_MB) {
-		debug("[ pckbc: (port %i) received One-key make/break data: "
-		    "0x%02x ]\n", port_nr, cmd);
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		d->state[port_nr] = STATE_NORMAL;
-		return;
-	}
-
-	if (d->state[port_nr] == STATE_WAITING_FOR_AUX) {
-		debug("[ pckbc: (port %i) received aux data: "
-		    "0x%02x ]\n", port_nr, cmd);
-		/*  Echo back.  */
-		pckbc_add_code(d, cmd, port_nr);
-		d->state[port_nr] = STATE_NORMAL;
-		return;
-	}
-
-	if (d->state[port_nr] == STATE_WAITING_FOR_AUX_OUT) {
-		debug("[ pckbc: (port %i) received aux out data: "
-		    "0x%02x ]\n", port_nr, cmd);
-		/*  Echo back.  */
-		pckbc_add_code(d, cmd, port_nr);
-		d->state[port_nr] = STATE_NORMAL;
-		return;
-	}
-
-	switch (cmd) {
-
-	case 0x00:
-		/*
-		 *  TODO: What does this do? This is possibly due to an
-		 *  error in the handling of some other command code.
-		 */
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		break;
-
-	case KBC_MODEIND:	/*  Set LEDs  */
-		/*  Just ACK, no LEDs are actually set.  */
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		break;
-
-	case KBC_ECHO:
-		pckbc_add_code(d, KBR_ECHO, port_nr);
-		break;
-
-	case KBC_SETTABLE:
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		d->state[port_nr] = STATE_WAITING_FOR_TRANSLTABLE;
-		break;
-
-	case KBC_ENABLE:
-		d->scanning_enabled[port_nr] = 1;
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		break;
-
-	case KBC_DISABLE:
-		d->scanning_enabled[port_nr] = 0;
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		break;
-
-	case KBC_SETDEFAULT:
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		break;
-
-	case KBC_GETID:
-		/*  Get keyboard/mouse ID.  NOTE/TODO: Ugly hardcoded answer.  */
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		
-		if (port_nr == 0) {
-			// Keyboard:
-			pckbc_add_code(d, 0xab, port_nr);
-			pckbc_add_code(d, 0x41, port_nr);
-		} else {
-			// Mouse:
-			pckbc_add_code(d, 0x00, port_nr);
-			pckbc_add_code(d, 0x00, port_nr);
-		}
-		break;
-
-	case KBC_TYPEMATIC:
-		/*
-		 *  Keyboard: Set typematic (auto-repeat) delay/speed.
-		 *  PS/2 mouse: Set sample ratre.
-		 */
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		d->state[port_nr] = STATE_WAITING_FOR_RATE;
-		break;
-
-	case KBC_ALLKEYS_TMB:
-		/*  "Make all keys typematic/make/break"  */
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		break;
-
-	case KBC_ONEKEY_MB:
-		/*  "Make one key typematic/make/break"  */
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		d->state[port_nr] = STATE_WAITING_FOR_ONEKEY_MB;
-		break;
-
-	case KBC_RESET:
-		pckbc_add_code(d, KBR_ACK, port_nr);
-		pckbc_add_code(d, KBR_RSTDONE, port_nr);
-
-		if (port_nr == 1) {
-			// Mouse (based on NetBSD's pckbport/pms.c) sends
-			// mouse ID after RSTDONE:
-			pckbc_add_code(d, 0x00, port_nr);
-		}
-
-		/*
-		 *  Disable interrupts during reset, or Linux 2.6
-		 *  prints warnings about spurious interrupts.
-		 */
-		// d->rx_int_enable = 0;
-		d->scanning_enabled[port_nr] = 0;
-		break;
-
-	default:
-		pckbc_add_code(d, KBR_RESEND, port_nr); // Error
-		fatal("[ pckbc: UNIMPLEMENTED command"
-		    " 0x%02x (port %i) ]\n", cmd, port_nr);
-	}
-}
-
-
-DEVICE_ACCESS(pckbc)
-{
-	struct pckbc_data *d = (struct pckbc_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int port_nr = 0;
-	size_t i;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-#ifdef PCKBC_DEBUG
-	if (writeflag == MEM_WRITE)
-		fatal("[ pckbc: write to addr 0x%x: 0x%x ]\n",
-		    (int)relative_addr, (int)idata);
-	else
-		fatal("[ pckbc: read from addr 0x%x ]\n",
-		    (int)relative_addr);
-#endif
-
-	/*  For JAZZ-based machines:  */
-	if (relative_addr >= 0x60) {
-		relative_addr -= 0x60;
-		if (relative_addr != 0)
-			relative_addr = 1;
-	} else if (d->type == PCKBC_8242) {
-		/*  8242 PS2-style:  */
-		/*  when using 8-byte alignment...  */
-		relative_addr /= sizeof(uint64_t);
-		/*  port_nr = 0 for keyboard, 1 for mouse  */
-		port_nr = (relative_addr >> 2);
-		relative_addr &= 3;
-		relative_addr += PS2;
-	} else if (d->pc_style_flag) {
-		/*  PC-style:  */
-		if (relative_addr != 0 && relative_addr != 4) {
-			/*  TODO (port 0x61)  */
-			odata = 0x21;
-{
-static int x = 0;
-x++;
-if (x&1)
-			odata ^= 0x10;
-}
-			if (writeflag == MEM_READ)
-				memory_writemax64(cpu, data, len, odata);
-			return 1;
-		}
-		if (relative_addr != 0)
-			relative_addr = 1;
-	} else {
-		/*  Others... Non-Jazz ARC-based machines etc.  */
-		if (relative_addr != 0)
-			relative_addr = 1;
-	}
-
-	switch (relative_addr) {
-
-	/*
-	 *  8042 (PC):
-	 */
-
-	case 0:		/*  data  */
-		if (writeflag==MEM_READ) {
-			switch (d->state[port_nr]) {
-			case STATE_RDCMDBYTE:
-				odata = d->cmdbyte;
-				d->state[port_nr] = STATE_NORMAL;
-				break;
-			case STATE_RDOUTPUT:
-				odata = d->output_byte;
-				d->state[port_nr] = STATE_NORMAL;
-				break;
-			default:if (d->head[0] != d->tail[0]) {
-					odata = pckbc_get_code(d, 0);
-					d->last_scancode = odata;
-				} else {
-					odata = d->last_scancode;
-					d->last_scancode |= 0x80;
-				}
-			}
-			/*  debug("[ pckbc: read from DATA: 0x%02x ]\n",
-			    (int)odata);  */
-		} else {
-			if (port_nr == 1) {
-				fatal("[ pckbc: write to DATA:");
-				for (i=0; i<len; i++)
-					fatal(" %02x", data[i]);
-				fatal(" ]\n");
-			}
-			
-			switch (d->state[port_nr]) {
-			case STATE_LDCMDBYTE:
-				d->cmdbyte = idata;
-				d->rx_int_enable[port_nr] = d->cmdbyte &
-				    (KC8_KENABLE | KC8_MENABLE) ? 1 : 0;
-				d->state[port_nr] = STATE_NORMAL;
-				break;
-			case STATE_LDOUTPUT:
-				d->output_byte = idata;
-				d->state[port_nr] = STATE_NORMAL;
-				break;
-			default:d->reg[relative_addr] = idata;
-				dev_pckbc_command(d, port_nr);
-			}
-		}
-		break;
-	case 1:		/*  control  */
-		if (writeflag==MEM_READ) {
-			odata = 0;
-
-			/*  "Data in buffer" bit  */
-			if (d->head[0] != d->tail[0] ||
-			    d->state[port_nr] == STATE_RDCMDBYTE ||
-			    d->state[port_nr] == STATE_RDOUTPUT)
-				odata |= KBS_DIB;
-
-			if (d->state[port_nr] == STATE_RDCMDBYTE)
-				odata |= KBS_OCMD;
-
-			odata |= KBS_NOSEC;
-			/*  debug("[ pckbc: read from CTL status port: "
-			    "0x%02x ]\n", (int)odata);  */
-		} else {
-			debug("[ pckbc: write to CTL:");
-			for (i=0; i<len; i++)
-				debug(" %02x", data[i]);
-			debug(" ]\n");
-			d->reg[relative_addr] = idata;
-
-			switch (idata) {
-			case 0x10:
-			case 0x11:
-				/*  TODO: For now, don't print warnings about
-				    these. NetBSD sends these.  */
-				break;
-			case K_RDCMDBYTE:
-				d->state[port_nr] = STATE_RDCMDBYTE;
-				break;
-			case K_LDCMDBYTE:
-				d->state[port_nr] = STATE_LDCMDBYTE;
-				break;
-			case 0xa7:
-				d->cmdbyte |= KC8_MDISABLE;
-				break;
-			case 0xa8:
-				d->cmdbyte &= ~KC8_MDISABLE;
-				break;
-			case 0xa9:	/*  test auxiliary port  */
-				debug("[ pckbc: CONTROL 0xa9, TODO ]\n");
-				break;
-			case 0xaa:	/*  keyboard self-test  */
-				pckbc_add_code(d, 0x55, port_nr);
-				break;
-			case 0xab:	/*  keyboard interface self-test  */
-				pckbc_add_code(d, 0x00, port_nr);
-				break;
-			case 0xad:
-				d->cmdbyte |= KC8_KDISABLE;
-				break;
-			case 0xae:
-				d->cmdbyte &= ~KC8_KDISABLE;
-				break;
-			case 0xd0:
-				d->state[port_nr] = STATE_RDOUTPUT;
-				break;
-			case 0xd1:
-				d->state[port_nr] = STATE_LDOUTPUT;
-				break;
-			case 0xd3:	/*  write to auxiliary device
-					    output buffer  */
-				debug("[ pckbc: CONTROL 0xd3, TODO ]\n");
-				d->state[port_nr] = STATE_WAITING_FOR_AUX_OUT;
-				break;
-			case 0xd4:	/*  write to auxiliary port  */
-				debug("[ pckbc: CONTROL 0xd4, TODO ]\n");
-				d->state[port_nr] = STATE_WAITING_FOR_AUX;
-				break;
-			default:
-				fatal("[ pckbc: unknown CONTROL 0x%x ]\n",
-				    (int)idata);
-				d->state[port_nr] = STATE_NORMAL;
-			}
-		}
-		break;
-
-	/*
-	 *  8242 (PS2):
-	 */
-
-	case PS2 + PS2_TXBUF:
-		if (writeflag==MEM_READ) {
-			odata = random() & 0xff;
-			debug("[ pckbc: read from port %i, PS2_TXBUF: "
-			    "0x%x ]\n", port_nr, (int)odata);
-		} else {
-			debug("[ pckbc: write to port %i, PS2_TXBUF: "
-			    "0x%llx ]\n", port_nr, (long long)idata);
-
-			/*  Handle keyboard commands:  */
-			d->reg[PS2_TXBUF] = idata;
-			dev_pckbc_command(d, port_nr);
-		}
-		break;
-
-	case PS2 + PS2_RXBUF:
-		if (writeflag==MEM_READ) {
-			/*  TODO: What should be returned if no data 
-			    is available?  */
-			odata = 0;
-			if (d->head[port_nr] != d->tail[port_nr])
-				odata = pckbc_get_code(d, port_nr);
-			debug("[ pckbc: read from port %i, PS2_RXBUF: "
-			    "0x%02x ]\n", port_nr, (int)odata);
-		} else {
-			debug("[ pckbc: write to port %i, PS2_RXBUF: "
-			    "0x%llx ]\n", port_nr, (long long)idata);
-		}
-		break;
-
-	case PS2 + PS2_CONTROL:
-		if (writeflag==MEM_READ) {
-			debug("[ pckbc: read from port %i, PS2_CONTROL"
-			    " ]\n", port_nr);
-		} else {
-			debug("[ pckbc: write to port %i, PS2_CONTROL:"
-			    " 0x%llx ]\n", port_nr, (long long)idata);
-			d->clocksignal = (idata & 0x10) ? 1 : 0;
-			d->rx_int_enable[port_nr] = (idata & PS2_CONTROL_RXINTEN) ? 1 : 0;
-			d->tx_int_enable[port_nr] = (idata & PS2_CONTROL_TXINTEN) ? 1 : 0;
-
-			// HACK/TODO: NetBSD/sgimips' X11 seems to work when
-			// interrupts are enabled, but it seems to not turn
-			// them on. Having this here makes it work, but it not
-			// the correct solution.
-			if (port_nr == 1) {
-				d->rx_int_enable[port_nr] = 1;
-			}
-		}
-		break;
-
-	case PS2 + PS2_STATUS:
-		if (writeflag==MEM_READ) {
-			odata = d->clocksignal + PS2_STATUS_TXEMPTY;
-
-			if (d->head[port_nr] != d->tail[port_nr]) {
-				/*  receiced data available  */
-				odata |= PS2_STATUS_RXFULL;
-			}
-
-			//debug("[ pckbc: read from port %i, PS2_STATUS: "
-			//    "0x%llx ]\n", port_nr, (long long)odata);
-		} else {
-			debug("[ pckbc: write to port %i, PS2_STATUS: "
-			    "0x%llx ]\n", port_nr, (long long)idata);
-		}
-		break;
-
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ pckbc: read from unimplemented reg %i ]\n",
-			    (int)relative_addr);
-			odata = d->reg[relative_addr % DEV_PCKBC_LENGTH];
-		} else {
-			debug("[ pckbc: write to unimplemented reg %i:",
-			    (int)relative_addr);
-			for (i=0; i<len; i++)
-				debug(" %02x", data[i]);
-			debug(" ]\n");
-			d->reg[relative_addr % DEV_PCKBC_LENGTH] = idata;
-		}
-	}
-
-	/*  SGI? TODO: fix  */
-#if 0
-	if (len == 8)
-		odata |= (odata << 8) | (odata << 16) | (odata << 24) |
-		    (odata << 32) | (odata << 40) | (odata << 48) |
-		    (odata << 56);
-#endif
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	pckbc_reassert_interrupts(d);
-
-	return 1;
-}
-
-
-/*
- *  dev_pckbc_init():
- *
- *  Type should be PCKBC_8042 or PCKBC_8242.
- */
-int dev_pckbc_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, int type, char *keyboard_irqpath,
-	char *mouse_irqpath, int in_use, int pc_style_flag)
-{
-	struct pckbc_data *d;
-	int len = DEV_PCKBC_LENGTH;
-
-	CHECK_ALLOCATION(d = (struct pckbc_data *) malloc(sizeof(struct pckbc_data)));
-	memset(d, 0, sizeof(struct pckbc_data));
-
-	d->translation_table = 2;
-
-	if (type == PCKBC_8242) {
-		len = 0x40;
-		d->translation_table = 3;
-	}
-	
-	if (type == PCKBC_JAZZ) {
-		type = PCKBC_8042;
-		len = DEV_PCKBC_LENGTH + 0x60;
-	}
-
-	INTERRUPT_CONNECT(keyboard_irqpath, d->irq_keyboard);
-	INTERRUPT_CONNECT(mouse_irqpath, d->irq_mouse);
-
-	d->type              = type;
-	d->in_use            = in_use;
-	d->pc_style_flag     = pc_style_flag;
-	d->rx_int_enable[0]  = 1;
-	d->rx_int_enable[1]  = 0;
-	d->output_byte       = 0x02;	/*  A20 enable on PCs  */
-
-	// Default is ENABLE keyboard but DISABLE mouse port:
-	d->scanning_enabled[0] = 1;
-	d->scanning_enabled[1] = 0;
-
-	d->console_handle = console_start_slave_inputonly(
-	    machine, "pckbc", d->in_use);
-
-	memory_device_register(mem, "pckbc", baseaddr,
-	    len, dev_pckbc_access, d, DM_DEFAULT, NULL);
-	machine_add_tickfunction(machine, dev_pckbc_tick, d,
-	    PCKBC_TICKSHIFT);
-
-	return d->console_handle;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_pmagja.c gxemul-0.7.0+dfsg/src/devices/dev_pmagja.c
--- gxemul-0.6.2/src/devices/dev_pmagja.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pmagja.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,229 @@
+/*
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: TURBOchannel PMAG-JA graphics card
+ *
+ *  TODO
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	XSIZE		1280
+#define	YSIZE		1024
+
+#define	PMAGJA_FIRSTOFFSET	0x40030
+
+/*  #define JA_DEBUG  */
+
+struct pmagja_data {
+	struct interrupt	irq;
+	struct memory		*fb_mem;
+	struct vfb_data		*vfb_data;
+
+	unsigned char		pixeldata[XSIZE * YSIZE];
+
+	int			current_r;
+	int			current_g;
+	int			current_b;
+
+	int			pip_offset;
+};
+
+
+DEVICE_ACCESS(pmagja)
+{
+	struct pmagja_data *d = (struct pmagja_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	size_t i, res = 1;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	relative_addr += PMAGJA_FIRSTOFFSET;
+
+#ifdef JA_DEBUG
+{
+size_t i;
+for (i=0; i<len; i++)
+  if (data[i] != 0 && data[i] != 1 && data[i]!=0xff)
+	if (writeflag)
+		fatal("[ pmagja: write to addr 0x%08llx: 0x%08llx ]\n",
+		    (long long)relative_addr, (long long)idata);
+}
+#endif
+
+	switch (relative_addr) {
+	case 0x0800c4:		/*  pip offset  */
+		if (writeflag==MEM_READ) {
+			odata = d->pip_offset;
+			debug("[ pmagja: read from pip offset: 0x%08llx ]\n",
+			    (long long)odata);
+		} else {
+			d->pip_offset = idata;
+			debug("[ px: write to pip offset: 0x%08llx ]\n",
+			    (long long)idata);
+		}
+		break;
+	default:
+		if (relative_addr >= 0x200000) {
+			/*  8-bit access:  */
+			for (i=0; i<len; i++) {
+				int ofs = relative_addr - 0x200000 + i;
+				int x, y;
+				unsigned char newdata[3];
+				y = ofs / XSIZE;
+				x = ofs - y*XSIZE;
+
+				if (writeflag) {
+					d->pixeldata[x + y*XSIZE] = data[i];
+					newdata[0] = d->vfb_data->rgb_palette[
+					    data[i] * 3 + 0];
+					newdata[1] = d->vfb_data->rgb_palette[
+					    data[i] * 3 + 1];
+					newdata[2] = d->vfb_data->rgb_palette[
+					    data[i] * 3 + 2];
+					dev_fb_access(cpu, d->fb_mem, (x +
+					    y * XSIZE) * 3, newdata, 3,
+					    writeflag, d->vfb_data);
+				} else {
+					data[i] = d->pixeldata[x + y*XSIZE];
+				}
+			}
+			/*  Return success.  */
+			return 1;
+		} else if (relative_addr >= 0x100000 &&
+		    relative_addr < 0x200000) {
+			/*  24-bit access:  */
+#if 0
+{
+	if (writeflag)
+	    if (idata != 0)
+		fatal("[ pmagja: write to addr 0x%08llx: 0x%08llx ]\n",
+		    (long long)relative_addr, (long long)idata);
+}
+#endif
+
+#if 0
+			int x, y, ofs;
+
+			ofs = (relative_addr - 0x100000) * 2;
+			y = ofs / XSIZE;
+			x = ofs - y * XSIZE;
+
+			if (writeflag == MEM_WRITE) {
+				int ix;
+				for (ix=0; ix<len*2; ix++) {
+					unsigned char data[3];
+					int ctype;
+
+					data[0] = data[1] = data[2] = 0;
+					ctype = (idata >> (ix*4)) & 0xf;
+					if (ctype == 0)
+						data[0] = 255;
+					if (ctype == 3)
+						data[1] = 255;
+					if (ctype == 0xf)
+						data[2] = 255;
+
+					res = dev_fb_access(cpu, d->fb_mem,
+					    ofs * 3, data, 3, MEM_WRITE,
+					    d->vfb_data);
+					ofs ++;
+				}
+			}
+#endif
+			return 1;
+		} else {
+			/*  Unknown:  */
+			if (writeflag==MEM_READ) {
+				fatal("[ pmagja: read from addr 0x%x: "
+				    "0x%llx ]\n", (int)relative_addr,
+				    (long long)odata);
+			} else {
+				fatal("[ pmagja: write to addr 0x%x: "
+				    "0x%llx ]\n", (int)relative_addr,
+				    (long long)idata);
+			}
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+#ifdef JA_DEBUG
+/*
+	if (!writeflag)
+		fatal("[ pmagja: read from addr 0x%08llx: 0x%08llx ]\n",
+		    (long long)relative_addr, (long long)odata);
+*/
+#endif
+
+	return res;
+}
+
+
+void dev_pmagja_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, const char *irq_path)
+{
+	struct pmagja_data *d;
+
+	CHECK_ALLOCATION(d = (struct pmagja_data *) malloc(sizeof(struct pmagja_data)));
+	memset(d, 0, sizeof(struct pmagja_data));
+
+	INTERRUPT_CONNECT(irq_path, d->irq);
+
+	d->fb_mem = memory_new(XSIZE * YSIZE * 3);
+	if (d->fb_mem == NULL) {
+		fprintf(stderr, "dev_pmagja_init(): out of memory (1)\n");
+		exit(1);
+	}
+	d->vfb_data = dev_fb_init(machine, d->fb_mem, 0, VFB_GENERIC,
+	    XSIZE, YSIZE, XSIZE, YSIZE, 24, "PMAG-JA");
+	if (d->vfb_data == NULL) {
+		fprintf(stderr, "dev_pmagja_init(): out of memory (2)\n");
+		exit(2);
+	}
+
+	/*  TODO: not bt459, but a bt463:  */
+	dev_bt459_init(machine, mem, baseaddr + 0x40000, 0, d->vfb_data, 8,
+	    irq_path, 0);	/*  palette  (TODO: type)  */
+	dev_bt431_init(mem, baseaddr + 0x40010, d->vfb_data, 8);  /*  cursor  */
+
+	memory_device_register(mem, "pmagja", baseaddr + PMAGJA_FIRSTOFFSET,
+	    DEV_PMAGJA_LENGTH - PMAGJA_FIRSTOFFSET, dev_pmagja_access, d,
+	    DM_DEFAULT, NULL);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_pmagja.cc gxemul-0.7.0+dfsg/src/devices/dev_pmagja.cc
--- gxemul-0.6.2/src/devices/dev_pmagja.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pmagja.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,227 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: TURBOchannel PMAG-JA graphics card
- *
- *  TODO
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define	XSIZE		1280
-#define	YSIZE		1024
-
-#define	PMAGJA_FIRSTOFFSET	0x40030
-
-/*  #define JA_DEBUG  */
-
-struct pmagja_data {
-	struct interrupt	irq;
-	struct memory		*fb_mem;
-	struct vfb_data		*vfb_data;
-
-	unsigned char		pixeldata[XSIZE * YSIZE];
-
-	int			current_r;
-	int			current_g;
-	int			current_b;
-
-	int			pip_offset;
-};
-
-
-DEVICE_ACCESS(pmagja)
-{
-	struct pmagja_data *d = (struct pmagja_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	size_t i, res = 1;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	relative_addr += PMAGJA_FIRSTOFFSET;
-
-#ifdef JA_DEBUG
-{
-size_t i;
-for (i=0; i<len; i++)
-  if (data[i] != 0 && data[i] != 1 && data[i]!=0xff)
-	if (writeflag)
-		fatal("[ pmagja: write to addr 0x%08llx: 0x%08llx ]\n",
-		    (long long)relative_addr, (long long)idata);
-}
-#endif
-
-	switch (relative_addr) {
-	case 0x0800c4:		/*  pip offset  */
-		if (writeflag==MEM_READ) {
-			odata = d->pip_offset;
-			debug("[ pmagja: read from pip offset: 0x%08llx ]\n",
-			    (long long)odata);
-		} else {
-			d->pip_offset = idata;
-			debug("[ px: write to pip offset: 0x%08llx ]\n",
-			    (long long)idata);
-		}
-		break;
-	default:
-		if (relative_addr >= 0x200000) {
-			/*  8-bit access:  */
-			for (i=0; i<len; i++) {
-				int ofs = relative_addr - 0x200000 + i;
-				int x, y;
-				unsigned char newdata[3];
-				y = ofs / XSIZE;
-				x = ofs - y*XSIZE;
-
-				if (writeflag) {
-					d->pixeldata[x + y*XSIZE] = data[i];
-					newdata[0] = d->vfb_data->rgb_palette[
-					    data[i] * 3 + 0];
-					newdata[1] = d->vfb_data->rgb_palette[
-					    data[i] * 3 + 1];
-					newdata[2] = d->vfb_data->rgb_palette[
-					    data[i] * 3 + 2];
-					dev_fb_access(cpu, d->fb_mem, (x +
-					    y * XSIZE) * 3, newdata, 3,
-					    writeflag, d->vfb_data);
-				} else {
-					data[i] = d->pixeldata[x + y*XSIZE];
-				}
-			}
-			/*  Return success.  */
-			return 1;
-		} else if (relative_addr >= 0x100000 &&
-		    relative_addr < 0x200000) {
-			/*  24-bit access:  */
-#if 0
-{
-	if (writeflag)
-	    if (idata != 0)
-		fatal("[ pmagja: write to addr 0x%08llx: 0x%08llx ]\n",
-		    (long long)relative_addr, (long long)idata);
-}
-#endif
-			int x, y, ofs;
-
-			ofs = (relative_addr - 0x100000) * 2;
-			y = ofs / XSIZE;
-			x = ofs - y * XSIZE;
-
-#if 0
-			if (writeflag == MEM_WRITE) {
-				int ix;
-				for (ix=0; ix<len*2; ix++) {
-					unsigned char data[3];
-					int ctype;
-
-					data[0] = data[1] = data[2] = 0;
-					ctype = (idata >> (ix*4)) & 0xf;
-					if (ctype == 0)
-						data[0] = 255;
-					if (ctype == 3)
-						data[1] = 255;
-					if (ctype == 0xf)
-						data[2] = 255;
-
-					res = dev_fb_access(cpu, d->fb_mem,
-					    ofs * 3, data, 3, MEM_WRITE,
-					    d->vfb_data);
-					ofs ++;
-				}
-			}
-#endif
-			return 1;
-		} else {
-			/*  Unknown:  */
-			if (writeflag==MEM_READ) {
-				fatal("[ pmagja: read from addr 0x%x: "
-				    "0x%llx ]\n", (int)relative_addr,
-				    (long long)odata);
-			} else {
-				fatal("[ pmagja: write to addr 0x%x: "
-				    "0x%llx ]\n", (int)relative_addr,
-				    (long long)idata);
-			}
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-#ifdef JA_DEBUG
-/*
-	if (!writeflag)
-		fatal("[ pmagja: read from addr 0x%08llx: 0x%08llx ]\n",
-		    (long long)relative_addr, (long long)odata);
-*/
-#endif
-
-	return res;
-}
-
-
-void dev_pmagja_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, const char *irq_path)
-{
-	struct pmagja_data *d;
-
-	CHECK_ALLOCATION(d = (struct pmagja_data *) malloc(sizeof(struct pmagja_data)));
-	memset(d, 0, sizeof(struct pmagja_data));
-
-	INTERRUPT_CONNECT(irq_path, d->irq);
-
-	d->fb_mem = memory_new(XSIZE * YSIZE * 3, machine->arch);
-	if (d->fb_mem == NULL) {
-		fprintf(stderr, "dev_pmagja_init(): out of memory (1)\n");
-		exit(1);
-	}
-	d->vfb_data = dev_fb_init(machine, d->fb_mem, 0, VFB_GENERIC,
-	    XSIZE, YSIZE, XSIZE, YSIZE, 24, "PMAG-JA");
-	if (d->vfb_data == NULL) {
-		fprintf(stderr, "dev_pmagja_init(): out of memory (2)\n");
-		exit(2);
-	}
-
-	/*  TODO: not bt459, but a bt463:  */
-	dev_bt459_init(machine, mem, baseaddr + 0x40000, 0, d->vfb_data, 8,
-	    irq_path, 0);	/*  palette  (TODO: type)  */
-	dev_bt431_init(mem, baseaddr + 0x40010, d->vfb_data, 8);  /*  cursor  */
-
-	memory_device_register(mem, "pmagja", baseaddr + PMAGJA_FIRSTOFFSET,
-	    DEV_PMAGJA_LENGTH - PMAGJA_FIRSTOFFSET, dev_pmagja_access, d,
-	    DM_DEFAULT, NULL);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_pmppc.c gxemul-0.7.0+dfsg/src/devices/dev_pmppc.c
--- gxemul-0.6.2/src/devices/dev_pmppc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pmppc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,161 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Artesyn PM/PPC motherboard registers
+ *
+ *  NOTE/TODO: Only enough to boot NetBSD/pmppc has been implemented.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/pmppc.h"
+
+
+struct pmppc_data {
+	uint8_t		config0;
+	uint8_t		config1;
+
+	uint8_t		reset_reg;
+};
+
+
+DEVICE_ACCESS(pmppc_board)
+{
+	struct pmppc_data *d = (struct pmppc_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	relative_addr += PMPPC_CONFIG0;
+
+	switch (relative_addr) {
+
+	case PMPPC_CONFIG0:
+		if (writeflag==MEM_READ) {
+			odata = d->config0;
+		} else {
+			debug("[ pmppc: UNIMPLEMENTED write to PMPPC_CONFIG0:"
+			    " 0x%02x ]\n", (int)idata);
+		}
+		break;
+
+	case PMPPC_CONFIG1:
+		if (writeflag==MEM_READ) {
+			odata = d->config1;
+		} else {
+			debug("[ pmppc: UNIMPLEMENTED write to PMPPC_CONFIG1:"
+			    " 0x%02x ]\n", (int)idata);
+		}
+		break;
+
+	case PMPPC_RESET:
+		if (writeflag==MEM_READ) {
+			odata = d->reset_reg;
+		} else {
+			if (d->reset_reg == PMPPC_RESET_SEQ_STEP1 &&
+			    idata == PMPPC_RESET_SEQ_STEP2) {
+				cpu->running = 0;
+			}
+			d->reset_reg = idata;
+		}
+		break;
+
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ pmppc: UNIMPLEMENTED read from 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			debug("[ pmppc: UNIMPLEMENTED write to  0x%08lx:"
+			    " 0x%02x ]\n", (long)relative_addr, (int)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(pmppc)
+{
+	struct pmppc_data *d;
+	struct memory *mem = devinit->machine->memory;
+
+	CHECK_ALLOCATION(d = (struct pmppc_data *) malloc(sizeof(struct pmppc_data)));
+	memset(d, 0, sizeof(struct pmppc_data));
+
+	/*
+	 *  Based on how NetBSD/pmppc's pmppc_setup() works:
+	 *
+	 *  config0:
+	 *	bit 7		Is monarch (?).
+	 *	bit 5		Has ethernet.
+	 *	bit 4		1 = No RTC.
+	 *	bits 3..2	Flash size (00 = 256 MB, 01 = 128 MB,
+	 *			10 = 64 MB, 11 = 32 MB).
+	 *	bits 1..0	Flash width (00 = 64, 01 = 32, 10 = 16, 11 = 0).
+	 *
+	 *  config1:
+	 *	bit 7		Boot device is FLASH (1) or ROM (0).
+	 *	bit 6		Has ECC.
+	 *	bits 5..4	Memory size: 00 = 32 MB, 01 = 64 MB,
+	 *			10 = 128 MB, 11 = 256 MB.
+	 *	bits 3..2	L2 cache.
+	 *	bits 1..0	Bus frequency: 00 = 66.66 MHz, 01 = 83.33 MHz,
+	 *			10 = 100.00 MHz, 11 = reserved?
+	 */
+	d->config0 = 0x20;
+	d->config1 = 0;
+
+	if (mem->physical_max == 32*1048576) {
+	} else if (mem->physical_max == 64*1048576) {
+		d->config1 |= 0x01;
+	} else if (mem->physical_max == 128*1048576) {
+		d->config1 |= 0x10;
+	} else if (mem->physical_max == 256*1048576) {
+		d->config1 |= 0x11;
+	} else {
+		fatal("A PM/PPC can have 32, 64, 128, or 256 MB RAM.\n");
+		exit(1);
+	}
+
+	memory_device_register(mem, "pmppc_board",
+	    PMPPC_CONFIG0, 0x10, dev_pmppc_board_access, d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_pmppc.cc gxemul-0.7.0+dfsg/src/devices/dev_pmppc.cc
--- gxemul-0.6.2/src/devices/dev_pmppc.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pmppc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,163 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Artesyn PM/PPC motherboard registers
- *
- *  NOTE/TODO: Only enough to boot NetBSD/pmppc has been implemented.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/pmppc.h"
-
-
-struct pmppc_data {
-	uint8_t		config0;
-	uint8_t		config1;
-
-	uint8_t		reset_reg;
-};
-
-
-DEVICE_ACCESS(pmppc_board)
-{
-	struct pmppc_data *d = (struct pmppc_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	relative_addr += PMPPC_CONFIG0;
-
-	switch (relative_addr) {
-
-	case PMPPC_CONFIG0:
-		if (writeflag==MEM_READ) {
-			odata = d->config0;
-		} else {
-			debug("[ pmppc: UNIMPLEMENTED write to PMPPC_CONFIG0:"
-			    " 0x%02x ]\n", (int)idata);
-		}
-		break;
-
-	case PMPPC_CONFIG1:
-		if (writeflag==MEM_READ) {
-			odata = d->config1;
-		} else {
-			debug("[ pmppc: UNIMPLEMENTED write to PMPPC_CONFIG1:"
-			    " 0x%02x ]\n", (int)idata);
-		}
-		break;
-
-	case PMPPC_RESET:
-		if (writeflag==MEM_READ) {
-			odata = d->reset_reg;
-		} else {
-			if (d->reset_reg == PMPPC_RESET_SEQ_STEP1 &&
-			    idata == PMPPC_RESET_SEQ_STEP2) {
-				cpu->running = 0;
-				cpu->machine->
-				    exit_without_entering_debugger = 1;
-			}
-			d->reset_reg = idata;
-		}
-		break;
-
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ pmppc: UNIMPLEMENTED read from 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			debug("[ pmppc: UNIMPLEMENTED write to  0x%08lx:"
-			    " 0x%02x ]\n", (long)relative_addr, (int)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(pmppc)
-{
-	struct pmppc_data *d;
-	struct memory *mem = devinit->machine->memory;
-
-	CHECK_ALLOCATION(d = (struct pmppc_data *) malloc(sizeof(struct pmppc_data)));
-	memset(d, 0, sizeof(struct pmppc_data));
-
-	/*
-	 *  Based on how NetBSD/pmppc's pmppc_setup() works:
-	 *
-	 *  config0:
-	 *	bit 7		Is monarch (?).
-	 *	bit 5		Has ethernet.
-	 *	bit 4		1 = No RTC.
-	 *	bits 3..2	Flash size (00 = 256 MB, 01 = 128 MB,
-	 *			10 = 64 MB, 11 = 32 MB).
-	 *	bits 1..0	Flash width (00 = 64, 01 = 32, 10 = 16, 11 = 0).
-	 *
-	 *  config1:
-	 *	bit 7		Boot device is FLASH (1) or ROM (0).
-	 *	bit 6		Has ECC.
-	 *	bits 5..4	Memory size: 00 = 32 MB, 01 = 64 MB,
-	 *			10 = 128 MB, 11 = 256 MB.
-	 *	bits 3..2	L2 cache.
-	 *	bits 1..0	Bus frequency: 00 = 66.66 MHz, 01 = 83.33 MHz,
-	 *			10 = 100.00 MHz, 11 = reserved?
-	 */
-	d->config0 = 0x20;
-	d->config1 = 0;
-
-	if (mem->physical_max == 32*1048576) {
-	} else if (mem->physical_max == 64*1048576) {
-		d->config1 |= 0x01;
-	} else if (mem->physical_max == 128*1048576) {
-		d->config1 |= 0x10;
-	} else if (mem->physical_max == 256*1048576) {
-		d->config1 |= 0x11;
-	} else {
-		fatal("A PM/PPC can have 32, 64, 128, or 256 MB RAM.\n");
-		exit(1);
-	}
-
-	memory_device_register(mem, "pmppc_board",
-	    PMPPC_CONFIG0, 0x10, dev_pmppc_board_access, d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_prep.c gxemul-0.7.0+dfsg/src/devices/dev_prep.c
--- gxemul-0.6.2/src/devices/dev_prep.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_prep.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,85 @@
+/*
+ *  Copyright (C) 2005-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: PReP machine mainbus (ISA bus + interrupt controller)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_isa.h"
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+struct prep_data {
+	uint32_t		int_status;
+};
+
+
+DEVICE_ACCESS(prep)
+{
+	/*  struct prep_data *d = extra;  */
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (writeflag == MEM_READ) {
+		odata = cpu->machine->isa_pic_data.last_int;
+	} else {
+		fatal("[ prep: write to interrupt register? idata = 0x%016" PRIx64" ]\n", idata);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(prep)
+{
+	struct prep_data *d;
+
+	CHECK_ALLOCATION(d = (struct prep_data *) malloc(sizeof(struct prep_data)));
+	memset(d, 0, sizeof(struct prep_data));
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    0xbffff000, 0x1000, dev_prep_access, d, DM_DEFAULT, NULL);
+
+	/*  This works for at least the IBM 6050:  */
+	bus_isa_init(devinit->machine, devinit->interrupt_path,
+	    BUS_ISA_IDE0 | BUS_ISA_IDE1, 0x80000000, 0xc0000000);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_prep.cc gxemul-0.7.0+dfsg/src/devices/dev_prep.cc
--- gxemul-0.6.2/src/devices/dev_prep.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_prep.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,85 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: PReP machine mainbus (ISA bus + interrupt controller)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_isa.h"
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-struct prep_data {
-	uint32_t		int_status;
-};
-
-
-DEVICE_ACCESS(prep)
-{
-	/*  struct prep_data *d = extra;  */
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (writeflag == MEM_READ) {
-		odata = cpu->machine->isa_pic_data.last_int;
-	} else {
-		fatal("[ prep: write to interrupt register? ]\n");
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(prep)
-{
-	struct prep_data *d;
-
-	CHECK_ALLOCATION(d = (struct prep_data *) malloc(sizeof(struct prep_data)));
-	memset(d, 0, sizeof(struct prep_data));
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    0xbffff000, 0x1000, dev_prep_access, d, DM_DEFAULT, NULL);
-
-	/*  This works for at least the IBM 6050:  */
-	bus_isa_init(devinit->machine, devinit->interrupt_path,
-	    BUS_ISA_IDE0 | BUS_ISA_IDE1, 0x80000000, 0xc0000000);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_ps2_ether.c gxemul-0.7.0+dfsg/src/devices/dev_ps2_ether.c
--- gxemul-0.6.2/src/devices/dev_ps2_ether.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ps2_ether.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,99 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: PlayStation 2 ethernet (smap and emac3)
+ *
+ *  TODO
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define debug fatal
+
+struct ps2_ether_data {
+	int	dummy;
+};
+
+
+DEVICE_ACCESS(ps2_ether)
+{
+	/*  struct ps2_ether_data *d = extra;  */
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case 0x105c:
+		/*  TODO: make these register accesses nicer  */
+		break;
+
+	case 0x105e:
+		odata = 0x8000;	/*  STACR_OC  */
+		break;
+
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ ps2_ether: read from addr 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)odata);
+		} else {
+			debug("[ ps2_ether: write to addr 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(ps2_ether)
+{
+	struct ps2_ether_data *d;
+
+	CHECK_ALLOCATION(d = (struct ps2_ether_data *) malloc(sizeof(struct ps2_ether_data)));
+	memset(d, 0, sizeof(struct ps2_ether_data));
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, 0x4000,
+	    dev_ps2_ether_access, d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_ps2_ether.cc gxemul-0.7.0+dfsg/src/devices/dev_ps2_ether.cc
--- gxemul-0.6.2/src/devices/dev_ps2_ether.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ps2_ether.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,99 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: PlayStation 2 ethernet (smap and emac3)
- *
- *  TODO
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define debug fatal
-
-struct ps2_ether_data {
-	int	dummy;
-};
-
-
-DEVICE_ACCESS(ps2_ether)
-{
-	/*  struct ps2_ether_data *d = extra;  */
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case 0x105c:
-		/*  TODO: make these register accesses nicer  */
-		break;
-
-	case 0x105e:
-		odata = 0x8000;	/*  STACR_OC  */
-		break;
-
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ ps2_ether: read from addr 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)odata);
-		} else {
-			debug("[ ps2_ether: write to addr 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(ps2_ether)
-{
-	struct ps2_ether_data *d;
-
-	CHECK_ALLOCATION(d = (struct ps2_ether_data *) malloc(sizeof(struct ps2_ether_data)));
-	memset(d, 0, sizeof(struct ps2_ether_data));
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, 0x4000,
-	    dev_ps2_ether_access, d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_ps2_gif.c gxemul-0.7.0+dfsg/src/devices/dev_ps2_gif.c
--- gxemul-0.6.2/src/devices/dev_ps2_gif.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ps2_gif.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,433 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: PlayStation 2 "gif" graphics device
+ *
+ *  TODO:  Convert dev_fb_access() accesses into direct framebuffer reads and
+ *         writes, to improve performance.
+ *
+ *  TODO 2:  The way things are now, rgb bytes are copied from emulated
+ *           space to the framebuffer as rgb, but on X Windows servers on
+ *           big-endian machines that should be bgr.  (?) Hm...
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	DEV_PS2_GIF_LENGTH		0x10000
+
+#define	PS2_FB_ADDR	0x60000000ULL 	/*  hopefully nothing else here  */
+
+
+struct gif_data {
+	struct cpu	*cpu;
+	int		xsize, ysize;
+	int		bytes_per_pixel;
+	int		transparent_text;
+	struct vfb_data *vfb_data;
+};
+
+
+/*
+ *  test_triangle():
+ *
+ *  Draw a triangle:
+ */
+void test_triangle(struct gif_data *d,
+	int x1, int y1, int r1, int g1, int b1,
+	int x2, int y2, int r2, int g2, int b2,
+	int x3, int y3, int r3, int g3, int b3)
+{
+	unsigned char *line;
+	int y, tmp, scale = 32768;
+	int xofs, xlen, savedxlen, xdir, x;
+	int r, g, b;			/*  scaled  */
+	int xstart, xstop;		/*  scaled  */
+	int rstart, rstop;		/*  scaled  */
+	int gstart, gstop;		/*  scaled  */
+	int bstart, bstop;		/*  scaled  */
+	int rpx, gpx, bpx;		/*  scaled  */
+	int xpy12, xpy13, xpy23;
+	int rpy12, rpy13, rpy23;
+	int gpy12, gpy13, gpy23;
+	int bpy12, bpy13, bpy23;
+
+	CHECK_ALLOCATION(line = (unsigned char *) malloc(d->xsize * d->bytes_per_pixel));
+
+	if (y2 > y3) {
+		tmp = x2; x2 = x3; x3 = tmp;
+		tmp = y2; y2 = y3; y3 = tmp;
+		tmp = r2; r2 = r3; r3 = tmp;
+		tmp = g2; g2 = g3; g3 = tmp;
+		tmp = b2; b2 = b3; b3 = tmp;
+	}
+
+	if (y1 > y2) {
+		tmp = x1; x1 = x2; x2 = tmp;
+		tmp = y1; y1 = y2; y2 = tmp;
+		tmp = r1; r1 = r2; r2 = tmp;
+		tmp = g1; g1 = g2; g2 = tmp;
+		tmp = b1; b1 = b2; b2 = tmp;
+	}
+
+	if (y1 > y3) {
+		tmp = x1; x1 = x3; x3 = tmp;
+		tmp = y1; y1 = y3; y3 = tmp;
+		tmp = r1; r1 = r3; r3 = tmp;
+		tmp = g1; g1 = g3; g3 = tmp;
+		tmp = b1; b1 = b3; b3 = tmp;
+	}
+
+	/*  X change per line:  */
+	xpy12 = (y2-y1)? scale*(x2-x1)/(y2-y1) : 0;
+	xpy13 = (y3-y1)? scale*(x3-x1)/(y3-y1) : 0;
+	xpy23 = (y3-y2)? scale*(x3-x2)/(y3-y2) : 0;
+
+	/*  Color change per line:  */
+	rpy12 = (y2-y1)? scale*(r2-r1)/(y2-y1) : 0;
+	rpy13 = (y3-y1)? scale*(r3-r1)/(y3-y1) : 0;
+	rpy23 = (y3-y2)? scale*(r3-r2)/(y3-y2) : 0;
+
+	gpy12 = (y2-y1)? scale*(g2-g1)/(y2-y1) : 0;
+	gpy13 = (y3-y1)? scale*(g3-g1)/(y3-y1) : 0;
+	gpy23 = (y3-y2)? scale*(g3-g2)/(y3-y2) : 0;
+
+	bpy12 = (y2-y1)? scale*(b2-b1)/(y2-y1) : 0;
+	bpy13 = (y3-y1)? scale*(b3-b1)/(y3-y1) : 0;
+	bpy23 = (y3-y2)? scale*(b3-b2)/(y3-y2) : 0;
+
+	xstart = xstop = x1 * scale;
+	rstart = rstop = r1 * scale;
+	gstart = gstop = g1 * scale;
+	bstart = bstop = b1 * scale;
+
+	for (y=y1; y<=y3; y++) {
+		if (xstart < xstop)
+			xofs = xstart/scale, xlen = (xstop-xstart)/scale + 1;
+		else
+			xofs = xstop/scale, xlen = (xstart-xstop)/scale + 1;
+
+		savedxlen = xlen;
+		xdir = (xstart < xstop)? 1 : -1;
+		r = rstart; g = gstart; b = bstart;
+
+		rpx = (xstop-xstart)? (rstop-rstart) / ((xstop-xstart)
+		    / scale) : 0;
+		gpx = (xstop-xstart)? (gstop-gstart) / ((xstop-xstart)
+		    / scale) : 0;
+		bpx = (xstop-xstart)? (bstop-bstart) / ((xstop-xstart)
+		    / scale): 0;
+
+		x = xstart / scale;
+		while (xlen > 0) {
+			if (x>=0 && x<d->xsize) {
+				int c;
+				c = r/scale;
+				line[x * d->bytes_per_pixel + 0] = c<0?
+				    0 : (c > 255? 255 : c);
+				c = g/scale;
+				line[x * d->bytes_per_pixel + 1] = c<0?
+				    0 : (c > 255? 255 : c);
+				c = b/scale;
+				line[x * d->bytes_per_pixel + 2] = c<0?
+				    0 : (c > 255? 255 : c);
+			}
+			r += rpx;
+			g += gpx;
+			b += bpx;
+			x += xdir;
+			xlen --;
+		}
+
+		dev_fb_access(d->cpu, d->cpu->mem,
+		    (y*d->xsize + xofs) * d->bytes_per_pixel,
+		    line + xofs * d->bytes_per_pixel,
+		    savedxlen * d->bytes_per_pixel,
+		    MEM_WRITE, d->vfb_data);
+
+		if (y<y2) {
+			xstart += xpy12;
+			rstart += rpy12;
+			gstart += gpy12;
+			bstart += bpy12;
+		} else {
+			xstart += xpy23;
+			rstart += rpy23;
+			gstart += gpy23;
+			bstart += bpy23;
+		}
+		xstop += xpy13;
+		rstop += rpy13;
+		gstop += gpy13;
+		bstop += bpy13;
+
+		if (y==y2) {
+			xstart = x2 * scale;
+			rstart = r2 * scale;
+			gstart = g2 * scale;
+			bstart = b2 * scale;
+		}
+	}
+}
+
+
+DEVICE_ACCESS(ps2_gif)
+{
+	unsigned int i;
+	struct gif_data *d = (struct gif_data *) extra;
+
+	if (relative_addr + len > DEV_PS2_GIF_LENGTH)
+		return 0;
+
+	if (writeflag==MEM_READ) {
+		debug("[ gif read from addr 0x%x, len=%i ]\n",
+		    (int)relative_addr, (int)len);
+	} else {
+		if (data[0] == 0x08 && data[1] == 0x80) {
+			/*  Possibly "initialize 640x480 mode":  */
+			debug("[ gif: initialize video mode (?) ]\n");
+		} else if (data[0] == 0x04 && data[1] == 0x00 && len > 300) {
+			/*  Possibly "output 8x16 character":  */
+			int xbase, ybase, xsize, ysize, x, y;
+
+			xbase = data[9*4 + 0] + (data[9*4 + 1] << 8);
+			ybase = data[9*4 + 2] + (data[9*4 + 3] << 8);
+
+			xsize = data[12*4 + 0] + (data[12*4 + 1] << 8);
+			ysize = data[13*4 + 0] + (data[13*4 + 1] << 8);
+			ysize &= ~0xf;	/*  multple of 16  */
+
+			/*  debug("[ gif: putchar at (%i,%i), size (%i,%i) "
+			    "]\n", xbase, ybase, xsize, ysize);  */
+
+			/*
+			 *  NetBSD and Linux:
+			 *
+			 *  [ gif write to addr 0x0 (len=608):
+			 *  04 00 00 00 00 00 00 10, 0e 00 00 00 00 00 00 00,
+			 *  00 00 00 00 00 00 0a 00, 50 00 00 00 00 00 00 00,
+			 *  00 00 00 00 00 00 00 00, 51 00 00 00 00 00 00 00,
+			 *  08 00 00 00 16 00 00 00, 52 00 00 00 00 00 00 00,
+			 *  00 00 00 00 00 00 00 00, 53 00 00 00 00 00 00 00,
+			 *  20 80 00 00 00 00 00 08, 00 00 00 00 00 00 00 00,
+			 *  00 00 aa 80 00 00 aa 80, 00 00 aa 80 00 00 aa 80,
+			 *  00 00 aa 80 00 00 aa 80, 00 00 aa 80 00 00 aa 80,
+			 *  aa aa 00 80 aa aa 00 80, 00 00 aa 80 00 00 aa 80,
+			 *  00 00 aa 80 00 00 aa 80, 00 00 aa 80 00 00 aa 80,
+			 */
+
+			/*
+			fatal("[ gif write to addr 0x%x (len=%i):",
+			    (int)relative_addr, (int)len);
+			for (i=0; i<len; i++) {
+				fatal(" %02x", data[i]);
+				if ((i & 7) == 7)
+					fatal(",");
+				if ((i & 31) == 31)
+					fatal("\n");
+			}
+			fatal(" ]\n");
+			*/
+
+			for (y=0; y<ysize; y++) {
+				int fb_addr = (xbase + (ybase+y) * d->xsize)
+				    * d->bytes_per_pixel;
+				int addr = (24 + y*xsize) * 4;
+				for (x=0; x<xsize; x++) {
+					/*  There are three bytes (r,g,b) at
+					    data[addr + 0] .. [addr + 2].
+					    TODO: This should be translated to a
+					    direct update of the framebuffer. */
+
+					dev_fb_access(d->cpu, d->cpu->mem,
+					    fb_addr, data + addr, 3, MEM_WRITE,
+					    d->vfb_data);
+
+					fb_addr += d->bytes_per_pixel;
+					addr += 4;
+				}
+			}
+		} else if (data[0] == 0x04 && data[1] == 0x80 && len == 0x50) {
+			/*  blockcopy  */
+			int y_source, y_dest, x_source, x_dest, x_size, y_size;
+			x_source = data[8*4 + 0] + ((data[8*4 + 1]) << 8);
+			y_source = data[8*4 + 2] + ((data[8*4 + 3]) << 8);
+			x_dest   = data[9*4 + 0] + ((data[9*4 + 1]) << 8);
+			y_dest   = data[9*4 + 2] + ((data[9*4 + 3]) << 8);
+			x_size   = data[12*4 + 0] + ((data[12*4 + 1]) << 8);
+			y_size   = data[13*4 + 0] + ((data[13*4 + 1]) << 8);
+
+			/*  debug("[ gif: blockcopy (%i,%i) -> (%i,%i), size="
+			    "(%i,%i) ]\n", x_source,y_source, x_dest,y_dest,
+			    x_size,y_size);  */
+
+			framebuffer_blockcopyfill(d->vfb_data, 0, 0,0,0,
+			    x_dest, y_dest, x_dest + x_size - 1, y_dest +
+			    y_size - 1, x_source, y_source);
+		} else if (data[8] == 0x10 && data[9] == 0x55 && len == 48) {
+			/*  Linux "clear":  This is used by linux to clear the
+			    lowest 16 pixels of the framebuffer.  */
+			int xbase, ybase, xend, yend;
+
+			xbase = (data[8*4 + 0] + (data[8*4 + 1] << 8)) / 16;
+			ybase = (data[8*4 + 2] + (data[8*4 + 3] << 8)) / 16;
+			xend  = (data[8*5 + 0] + (data[8*5 + 1] << 8)) / 16;
+			yend  = (data[8*5 + 2] + (data[8*5 + 3] << 8)) / 16;
+
+			/*  debug("[ gif: linux \"clear\" (%i,%i)-(%i,%i) ]\n",
+			    xbase, ybase, xend, yend);  */
+
+			framebuffer_blockcopyfill(d->vfb_data, 1, 0,0,0,
+			    xbase, ybase, xend - 1, yend - 1, 0,0);
+		} else if (data[0] == 0x07 && data[1] == 0x80 && len == 128) {
+			/*  NetBSD "output cursor":  */
+			int xbase, ybase, xend, yend, x, y;
+
+			xbase = (data[20*4 + 0] + (data[20*4 + 1] << 8)) / 16;
+			ybase = (data[20*4 + 2] + (data[20*4 + 3] << 8)) / 16;
+			xend  = (data[28*4 + 0] + (data[28*4 + 1] << 8)) / 16;
+			yend  = (data[28*4 + 2] + (data[28*4 + 3] << 8)) / 16;
+
+			/*  debug("[ gif: NETBSD cursor at (%i,%i)-(%i,%i) ]\n",
+			    xbase, ybase, xend, yend);  */
+
+			/*  Output the cursor to framebuffer memory:  */
+
+			for (y=ybase; y<=yend; y++)
+				for (x=xbase; x<=xend; x++) {
+					int fb_addr = (x + y * d->xsize) *
+					    d->bytes_per_pixel;
+					unsigned char pixels[3];
+
+					dev_fb_access(d->cpu, d->cpu->mem,
+					    fb_addr, pixels, sizeof(pixels),
+					    MEM_READ, d->vfb_data);
+
+					pixels[0] = 0xff - pixels[0];
+					pixels[1] = 0xff - pixels[1];
+					pixels[2] = 0xff - pixels[2];
+
+					dev_fb_access(d->cpu, d->cpu->mem,
+					    fb_addr, pixels, sizeof(pixels),
+					    MEM_WRITE, d->vfb_data);
+				}
+		} else if (data[0] == 0x01 && data[1] == 0x00 && len == 80) {
+			/*  Linux "output cursor":  */
+			int xbase, ybase, xend, yend, x, y;
+
+			xbase = (data[7*8 + 0] + (data[7*8 + 1] << 8)) / 16;
+			ybase = (data[7*8 + 2] + (data[7*8 + 3] << 8)) / 16;
+			xend  = (data[8*8 + 0] + (data[8*8 + 1] << 8)) / 16;
+			yend  = (data[8*8 + 2] + (data[8*8 + 3] << 8)) / 16;
+
+			debug("[ gif: LINUX cursor at (%i,%i)-(%i,%i) ]\n",
+			    xbase, ybase, xend, yend);
+
+			/*  Output the cursor to framebuffer memory:  */
+
+			for (y=ybase; y<=yend; y++)
+				for (x=xbase; x<=xend; x++) {
+					int fb_addr = (x + y * d->xsize) *
+					    d->bytes_per_pixel;
+					unsigned char pixels[3];
+
+					dev_fb_access(d->cpu, d->cpu->mem,
+					    fb_addr, pixels, sizeof(pixels),
+					    MEM_READ, d->vfb_data);
+
+					pixels[0] = 0xff - pixels[0];
+					pixels[1] = 0xff - pixels[1];
+					pixels[2] = 0xff - pixels[2];
+
+					dev_fb_access(d->cpu, d->cpu->mem,
+					    fb_addr, pixels, sizeof(pixels),
+					    MEM_WRITE, d->vfb_data);
+				}
+		} else {		/*  Unknown command:  */
+			fatal("[ gif write to addr 0x%x (len=%i):",
+			    (int)relative_addr, len);
+			for (i=0; i<len; i++)
+				fatal(" %02x", data[i]);
+			fatal(" ]\n");
+/*			fatal("Unknown gif command.\n");
+			cpu->running = 0;
+*/		}
+	}
+
+	return 1;
+}
+
+
+/*
+ *  devinit_ps2_gif():
+ *
+ *  Attached to separate memory by devinit_ps2_gs().
+ */
+DEVINIT(ps2_gif)
+{
+	struct gif_data *d;
+
+	CHECK_ALLOCATION(d = (struct gif_data *) malloc(sizeof(struct gif_data)));
+	memset(d, 0, sizeof(struct gif_data));
+
+	d->transparent_text = 0;
+	d->cpu = devinit->machine->cpus[0];		/*  TODO  */
+	d->xsize = 640; d->ysize = 480;
+	d->bytes_per_pixel = 3;
+
+	d->vfb_data = dev_fb_init(devinit->machine, devinit->machine->memory,
+	    PS2_FB_ADDR, VFB_PLAYSTATION2,
+	    d->xsize, d->ysize, d->xsize, d->ysize, 24, "Playstation 2");
+	if (d->vfb_data == NULL) {
+		fprintf(stderr, "could not initialize fb, out of memory\n");
+		exit(1);
+	}
+
+#if 0
+	test_triangle(d, 300,50, 255,0,0,  50,150, 0,255,0,  600,400, 0,0,255);
+	test_triangle(d, 310,210, 128,32,0,  175,410, 0,32,0,
+	    500,470, 125,255,125);
+	test_triangle(d, 100,450, 255,255,0,  250,370, 0,255,255,
+	    400,470, 255,0,255);
+#endif
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_PS2_GIF_LENGTH, dev_ps2_gif_access, d,
+	    DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_ps2_gif.cc gxemul-0.7.0+dfsg/src/devices/dev_ps2_gif.cc
--- gxemul-0.6.2/src/devices/dev_ps2_gif.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ps2_gif.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,433 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: PlayStation 2 "gif" graphics device
- *
- *  TODO:  Convert dev_fb_access() accesses into direct framebuffer reads and
- *         writes, to improve performance.
- *
- *  TODO 2:  The way things are now, rgb bytes are copied from emulated
- *           space to the framebuffer as rgb, but on X Windows servers on
- *           big-endian machines that should be bgr.  (?) Hm...
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define	DEV_PS2_GIF_LENGTH		0x10000
-
-#define	PS2_FB_ADDR	0x60000000ULL 	/*  hopefully nothing else here  */
-
-
-struct gif_data {
-	struct cpu	*cpu;
-	int		xsize, ysize;
-	int		bytes_per_pixel;
-	int		transparent_text;
-	struct vfb_data *vfb_data;
-};
-
-
-/*
- *  test_triangle():
- *
- *  Draw a triangle:
- */
-void test_triangle(struct gif_data *d,
-	int x1, int y1, int r1, int g1, int b1,
-	int x2, int y2, int r2, int g2, int b2,
-	int x3, int y3, int r3, int g3, int b3)
-{
-	unsigned char *line;
-	int y, tmp, scale = 32768;
-	int xofs, xlen, savedxlen, xdir, x;
-	int r, g, b;			/*  scaled  */
-	int xstart, xstop;		/*  scaled  */
-	int rstart, rstop;		/*  scaled  */
-	int gstart, gstop;		/*  scaled  */
-	int bstart, bstop;		/*  scaled  */
-	int rpx, gpx, bpx;		/*  scaled  */
-	int xpy12, xpy13, xpy23;
-	int rpy12, rpy13, rpy23;
-	int gpy12, gpy13, gpy23;
-	int bpy12, bpy13, bpy23;
-
-	CHECK_ALLOCATION(line = (unsigned char *) malloc(d->xsize * d->bytes_per_pixel));
-
-	if (y2 > y3) {
-		tmp = x2; x2 = x3; x3 = tmp;
-		tmp = y2; y2 = y3; y3 = tmp;
-		tmp = r2; r2 = r3; r3 = tmp;
-		tmp = g2; g2 = g3; g3 = tmp;
-		tmp = b2; b2 = b3; b3 = tmp;
-	}
-
-	if (y1 > y2) {
-		tmp = x1; x1 = x2; x2 = tmp;
-		tmp = y1; y1 = y2; y2 = tmp;
-		tmp = r1; r1 = r2; r2 = tmp;
-		tmp = g1; g1 = g2; g2 = tmp;
-		tmp = b1; b1 = b2; b2 = tmp;
-	}
-
-	if (y1 > y3) {
-		tmp = x1; x1 = x3; x3 = tmp;
-		tmp = y1; y1 = y3; y3 = tmp;
-		tmp = r1; r1 = r3; r3 = tmp;
-		tmp = g1; g1 = g3; g3 = tmp;
-		tmp = b1; b1 = b3; b3 = tmp;
-	}
-
-	/*  X change per line:  */
-	xpy12 = (y2-y1)? scale*(x2-x1)/(y2-y1) : 0;
-	xpy13 = (y3-y1)? scale*(x3-x1)/(y3-y1) : 0;
-	xpy23 = (y3-y2)? scale*(x3-x2)/(y3-y2) : 0;
-
-	/*  Color change per line:  */
-	rpy12 = (y2-y1)? scale*(r2-r1)/(y2-y1) : 0;
-	rpy13 = (y3-y1)? scale*(r3-r1)/(y3-y1) : 0;
-	rpy23 = (y3-y2)? scale*(r3-r2)/(y3-y2) : 0;
-
-	gpy12 = (y2-y1)? scale*(g2-g1)/(y2-y1) : 0;
-	gpy13 = (y3-y1)? scale*(g3-g1)/(y3-y1) : 0;
-	gpy23 = (y3-y2)? scale*(g3-g2)/(y3-y2) : 0;
-
-	bpy12 = (y2-y1)? scale*(b2-b1)/(y2-y1) : 0;
-	bpy13 = (y3-y1)? scale*(b3-b1)/(y3-y1) : 0;
-	bpy23 = (y3-y2)? scale*(b3-b2)/(y3-y2) : 0;
-
-	xstart = xstop = x1 * scale;
-	rstart = rstop = r1 * scale;
-	gstart = gstop = g1 * scale;
-	bstart = bstop = b1 * scale;
-
-	for (y=y1; y<=y3; y++) {
-		if (xstart < xstop)
-			xofs = xstart/scale, xlen = (xstop-xstart)/scale + 1;
-		else
-			xofs = xstop/scale, xlen = (xstart-xstop)/scale + 1;
-
-		savedxlen = xlen;
-		xdir = (xstart < xstop)? 1 : -1;
-		r = rstart; g = gstart; b = bstart;
-
-		rpx = (xstop-xstart)? (rstop-rstart) / ((xstop-xstart)
-		    / scale) : 0;
-		gpx = (xstop-xstart)? (gstop-gstart) / ((xstop-xstart)
-		    / scale) : 0;
-		bpx = (xstop-xstart)? (bstop-bstart) / ((xstop-xstart)
-		    / scale): 0;
-
-		x = xstart / scale;
-		while (xlen > 0) {
-			if (x>=0 && x<d->xsize) {
-				int c;
-				c = r/scale;
-				line[x * d->bytes_per_pixel + 0] = c<0?
-				    0 : (c > 255? 255 : c);
-				c = g/scale;
-				line[x * d->bytes_per_pixel + 1] = c<0?
-				    0 : (c > 255? 255 : c);
-				c = b/scale;
-				line[x * d->bytes_per_pixel + 2] = c<0?
-				    0 : (c > 255? 255 : c);
-			}
-			r += rpx;
-			g += gpx;
-			b += bpx;
-			x += xdir;
-			xlen --;
-		}
-
-		dev_fb_access(d->cpu, d->cpu->mem,
-		    (y*d->xsize + xofs) * d->bytes_per_pixel,
-		    line + xofs * d->bytes_per_pixel,
-		    savedxlen * d->bytes_per_pixel,
-		    MEM_WRITE, d->vfb_data);
-
-		if (y<y2) {
-			xstart += xpy12;
-			rstart += rpy12;
-			gstart += gpy12;
-			bstart += bpy12;
-		} else {
-			xstart += xpy23;
-			rstart += rpy23;
-			gstart += gpy23;
-			bstart += bpy23;
-		}
-		xstop += xpy13;
-		rstop += rpy13;
-		gstop += gpy13;
-		bstop += bpy13;
-
-		if (y==y2) {
-			xstart = x2 * scale;
-			rstart = r2 * scale;
-			gstart = g2 * scale;
-			bstart = b2 * scale;
-		}
-	}
-}
-
-
-DEVICE_ACCESS(ps2_gif)
-{
-	unsigned int i;
-	struct gif_data *d = (struct gif_data *) extra;
-
-	if (relative_addr + len > DEV_PS2_GIF_LENGTH)
-		return 0;
-
-	if (writeflag==MEM_READ) {
-		debug("[ gif read from addr 0x%x, len=%i ]\n",
-		    (int)relative_addr, (int)len);
-	} else {
-		if (data[0] == 0x08 && data[1] == 0x80) {
-			/*  Possibly "initialize 640x480 mode":  */
-			debug("[ gif: initialize video mode (?) ]\n");
-		} else if (data[0] == 0x04 && data[1] == 0x00 && len > 300) {
-			/*  Possibly "output 8x16 character":  */
-			int xbase, ybase, xsize, ysize, x, y;
-
-			xbase = data[9*4 + 0] + (data[9*4 + 1] << 8);
-			ybase = data[9*4 + 2] + (data[9*4 + 3] << 8);
-
-			xsize = data[12*4 + 0] + (data[12*4 + 1] << 8);
-			ysize = data[13*4 + 0] + (data[13*4 + 1] << 8);
-			ysize &= ~0xf;	/*  multple of 16  */
-
-			/*  debug("[ gif: putchar at (%i,%i), size (%i,%i) "
-			    "]\n", xbase, ybase, xsize, ysize);  */
-
-			/*
-			 *  NetBSD and Linux:
-			 *
-			 *  [ gif write to addr 0x0 (len=608):
-			 *  04 00 00 00 00 00 00 10, 0e 00 00 00 00 00 00 00,
-			 *  00 00 00 00 00 00 0a 00, 50 00 00 00 00 00 00 00,
-			 *  00 00 00 00 00 00 00 00, 51 00 00 00 00 00 00 00,
-			 *  08 00 00 00 16 00 00 00, 52 00 00 00 00 00 00 00,
-			 *  00 00 00 00 00 00 00 00, 53 00 00 00 00 00 00 00,
-			 *  20 80 00 00 00 00 00 08, 00 00 00 00 00 00 00 00,
-			 *  00 00 aa 80 00 00 aa 80, 00 00 aa 80 00 00 aa 80,
-			 *  00 00 aa 80 00 00 aa 80, 00 00 aa 80 00 00 aa 80,
-			 *  aa aa 00 80 aa aa 00 80, 00 00 aa 80 00 00 aa 80,
-			 *  00 00 aa 80 00 00 aa 80, 00 00 aa 80 00 00 aa 80,
-			 */
-
-			/*
-			fatal("[ gif write to addr 0x%x (len=%i):",
-			    (int)relative_addr, (int)len);
-			for (i=0; i<len; i++) {
-				fatal(" %02x", data[i]);
-				if ((i & 7) == 7)
-					fatal(",");
-				if ((i & 31) == 31)
-					fatal("\n");
-			}
-			fatal(" ]\n");
-			*/
-
-			for (y=0; y<ysize; y++) {
-				int fb_addr = (xbase + (ybase+y) * d->xsize)
-				    * d->bytes_per_pixel;
-				int addr = (24 + y*xsize) * 4;
-				for (x=0; x<xsize; x++) {
-					/*  There are three bytes (r,g,b) at
-					    data[addr + 0] .. [addr + 2].
-					    TODO: This should be translated to a
-					    direct update of the framebuffer. */
-
-					dev_fb_access(d->cpu, d->cpu->mem,
-					    fb_addr, data + addr, 3, MEM_WRITE,
-					    d->vfb_data);
-
-					fb_addr += d->bytes_per_pixel;
-					addr += 4;
-				}
-			}
-		} else if (data[0] == 0x04 && data[1] == 0x80 && len == 0x50) {
-			/*  blockcopy  */
-			int y_source, y_dest, x_source, x_dest, x_size, y_size;
-			x_source = data[8*4 + 0] + ((data[8*4 + 1]) << 8);
-			y_source = data[8*4 + 2] + ((data[8*4 + 3]) << 8);
-			x_dest   = data[9*4 + 0] + ((data[9*4 + 1]) << 8);
-			y_dest   = data[9*4 + 2] + ((data[9*4 + 3]) << 8);
-			x_size   = data[12*4 + 0] + ((data[12*4 + 1]) << 8);
-			y_size   = data[13*4 + 0] + ((data[13*4 + 1]) << 8);
-
-			/*  debug("[ gif: blockcopy (%i,%i) -> (%i,%i), size="
-			    "(%i,%i) ]\n", x_source,y_source, x_dest,y_dest,
-			    x_size,y_size);  */
-
-			framebuffer_blockcopyfill(d->vfb_data, 0, 0,0,0,
-			    x_dest, y_dest, x_dest + x_size - 1, y_dest +
-			    y_size - 1, x_source, y_source);
-		} else if (data[8] == 0x10 && data[9] == 0x55 && len == 48) {
-			/*  Linux "clear":  This is used by linux to clear the
-			    lowest 16 pixels of the framebuffer.  */
-			int xbase, ybase, xend, yend;
-
-			xbase = (data[8*4 + 0] + (data[8*4 + 1] << 8)) / 16;
-			ybase = (data[8*4 + 2] + (data[8*4 + 3] << 8)) / 16;
-			xend  = (data[8*5 + 0] + (data[8*5 + 1] << 8)) / 16;
-			yend  = (data[8*5 + 2] + (data[8*5 + 3] << 8)) / 16;
-
-			/*  debug("[ gif: linux \"clear\" (%i,%i)-(%i,%i) ]\n",
-			    xbase, ybase, xend, yend);  */
-
-			framebuffer_blockcopyfill(d->vfb_data, 1, 0,0,0,
-			    xbase, ybase, xend - 1, yend - 1, 0,0);
-		} else if (data[0] == 0x07 && data[1] == 0x80 && len == 128) {
-			/*  NetBSD "output cursor":  */
-			int xbase, ybase, xend, yend, x, y;
-
-			xbase = (data[20*4 + 0] + (data[20*4 + 1] << 8)) / 16;
-			ybase = (data[20*4 + 2] + (data[20*4 + 3] << 8)) / 16;
-			xend  = (data[28*4 + 0] + (data[28*4 + 1] << 8)) / 16;
-			yend  = (data[28*4 + 2] + (data[28*4 + 3] << 8)) / 16;
-
-			/*  debug("[ gif: NETBSD cursor at (%i,%i)-(%i,%i) ]\n",
-			    xbase, ybase, xend, yend);  */
-
-			/*  Output the cursor to framebuffer memory:  */
-
-			for (y=ybase; y<=yend; y++)
-				for (x=xbase; x<=xend; x++) {
-					int fb_addr = (x + y * d->xsize) *
-					    d->bytes_per_pixel;
-					unsigned char pixels[3];
-
-					dev_fb_access(d->cpu, d->cpu->mem,
-					    fb_addr, pixels, sizeof(pixels),
-					    MEM_READ, d->vfb_data);
-
-					pixels[0] = 0xff - pixels[0];
-					pixels[1] = 0xff - pixels[1];
-					pixels[2] = 0xff - pixels[2];
-
-					dev_fb_access(d->cpu, d->cpu->mem,
-					    fb_addr, pixels, sizeof(pixels),
-					    MEM_WRITE, d->vfb_data);
-				}
-		} else if (data[0] == 0x01 && data[1] == 0x00 && len == 80) {
-			/*  Linux "output cursor":  */
-			int xbase, ybase, xend, yend, x, y;
-
-			xbase = (data[7*8 + 0] + (data[7*8 + 1] << 8)) / 16;
-			ybase = (data[7*8 + 2] + (data[7*8 + 3] << 8)) / 16;
-			xend  = (data[8*8 + 0] + (data[8*8 + 1] << 8)) / 16;
-			yend  = (data[8*8 + 2] + (data[8*8 + 3] << 8)) / 16;
-
-			debug("[ gif: LINUX cursor at (%i,%i)-(%i,%i) ]\n",
-			    xbase, ybase, xend, yend);
-
-			/*  Output the cursor to framebuffer memory:  */
-
-			for (y=ybase; y<=yend; y++)
-				for (x=xbase; x<=xend; x++) {
-					int fb_addr = (x + y * d->xsize) *
-					    d->bytes_per_pixel;
-					unsigned char pixels[3];
-
-					dev_fb_access(d->cpu, d->cpu->mem,
-					    fb_addr, pixels, sizeof(pixels),
-					    MEM_READ, d->vfb_data);
-
-					pixels[0] = 0xff - pixels[0];
-					pixels[1] = 0xff - pixels[1];
-					pixels[2] = 0xff - pixels[2];
-
-					dev_fb_access(d->cpu, d->cpu->mem,
-					    fb_addr, pixels, sizeof(pixels),
-					    MEM_WRITE, d->vfb_data);
-				}
-		} else {		/*  Unknown command:  */
-			fatal("[ gif write to addr 0x%x (len=%i):",
-			    (int)relative_addr, len);
-			for (i=0; i<len; i++)
-				fatal(" %02x", data[i]);
-			fatal(" ]\n");
-/*			fatal("Unknown gif command.\n");
-			cpu->running = 0;
-*/		}
-	}
-
-	return 1;
-}
-
-
-/*
- *  devinit_ps2_gif():
- *
- *  Attached to separate memory by devinit_ps2_gs().
- */
-DEVINIT(ps2_gif)
-{
-	struct gif_data *d;
-
-	CHECK_ALLOCATION(d = (struct gif_data *) malloc(sizeof(struct gif_data)));
-	memset(d, 0, sizeof(struct gif_data));
-
-	d->transparent_text = 0;
-	d->cpu = devinit->machine->cpus[0];		/*  TODO  */
-	d->xsize = 640; d->ysize = 480;
-	d->bytes_per_pixel = 3;
-
-	d->vfb_data = dev_fb_init(devinit->machine, devinit->machine->memory,
-	    PS2_FB_ADDR, VFB_PLAYSTATION2,
-	    d->xsize, d->ysize, d->xsize, d->ysize, 24, "Playstation 2");
-	if (d->vfb_data == NULL) {
-		fprintf(stderr, "could not initialize fb, out of memory\n");
-		exit(1);
-	}
-
-#if 0
-	test_triangle(d, 300,50, 255,0,0,  50,150, 0,255,0,  600,400, 0,0,255);
-	test_triangle(d, 310,210, 128,32,0,  175,410, 0,32,0,
-	    500,470, 125,255,125);
-	test_triangle(d, 100,450, 255,255,0,  250,370, 0,255,255,
-	    400,470, 255,0,255);
-#endif
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_PS2_GIF_LENGTH, dev_ps2_gif_access, d,
-	    DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_ps2_gs.c gxemul-0.7.0+dfsg/src/devices/dev_ps2_gs.c
--- gxemul-0.6.2/src/devices/dev_ps2_gs.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ps2_gs.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,158 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: PlayStation 2 graphics system
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	DEV_PS2_GS_LENGTH		0x2000
+
+/*  NOTE/TODO: This should be the same as in ps2_stuff:  */
+#define	DEV_PS2_GIF_FAKE_BASE		0x50000000
+
+#define	N_GS_REGS	0x108
+
+struct gs_data {
+	uint64_t	reg[N_GS_REGS];		/*  GS registers  */
+};
+
+#define	GS_S_PMODE_REG		0x00
+#define	GS_S_SMODE1_REG		0x01
+#define	GS_S_SMODE2_REG		0x02
+#define	GS_S_SRFSH_REG		0x03
+#define	GS_S_SYNCH1_REG		0x04
+#define	GS_S_SYNCH2_REG		0x05
+#define	GS_S_SYNCV_REG		0x06
+#define	GS_S_DISPFB1_REG	0x07
+#define	GS_S_DISPLAY1_REG	0x08
+#define	GS_S_DISPFB2_REG	0x09
+#define	GS_S_DISPLAY2_REG	0x0a
+#define	GS_S_EXTBUF_REG0	0x0b
+#define	GS_S_EXTDATA_REG	0x0c
+#define	GS_S_EXTWRITE_REG	0x0d
+#define	GS_S_BGCOLOR_REG	0x0e
+
+//static const char *gs_reg_names[15] = {
+//	"PMODE", "SMODE1", "SMODE2", "SRFSH",
+//	"SYNCH1", "SYNCH2", "SYNCV", "DISPFB1",
+//	"DISPLAY1", "DISPFB2", "DISPLAY2", "EXTBUF",
+//	"EXTDATA", "EXTWRITE", "BGCOLOR"  };
+
+#define	GS_S_CSR_REG		0x100
+#define	GS_S_IMR_REG		0x101
+#define	GS_S_BUSDIR_REG		0x104
+#define	GS_S_SIGLBLID_REG	0x108
+
+//static const char *gs_reg_high_names[4] = {
+//	"CSR", "IMR", "BUSDIR", "SIGLBLID"
+//	};
+
+
+DEVICE_ACCESS(ps2_gs)
+{
+	struct gs_data *d = (struct gs_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	size_t i;
+	int regnr;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	regnr = relative_addr / 16;
+	if (relative_addr & 0xf) {
+		debug("[ gs unaligned access, addr 0x%x ]\n",
+		    (int)relative_addr);
+		return 0;
+	}
+
+	/*  Empty the GS FIFO:  */
+	d->reg[GS_S_CSR_REG] &= ~(3 << 14);
+	d->reg[GS_S_CSR_REG] |=  (1 << 14);
+
+	switch (relative_addr) {
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ gs read from addr 0x%x ]\n",
+			    (int)relative_addr);
+			odata = d->reg[regnr];
+		} else {
+			debug("[ gs write to addr 0x%x:", (int)relative_addr);
+			for (i=0; i<len; i++)
+				debug(" %02x", data[i]);
+			debug(" ]\n");
+			d->reg[regnr] = idata;
+			return 1;
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  devinit_ps2_gs():
+ *
+ *  Initialize the Playstation 2 graphics system. This is a bit tricky.
+ *  'gs' is the memory mapped device, as seen by the main processor.
+ *  'gif' is another thing which has its own memory.  DMA is used to
+ *  transfer stuff to the gif from the main memory.
+ *  There is also a framebuffer, which is separated from the main
+ *  memory.
+ *
+ *  TODO:  Make this clearer.
+ */
+DEVINIT(ps2_gs)
+{
+	struct gs_data *d;
+	char str[100];
+
+	CHECK_ALLOCATION(d = (struct gs_data *) malloc(sizeof(struct gs_data)));
+	memset(d, 0, sizeof(struct gs_data));
+
+	snprintf(str, sizeof(str) - 1, "ps2_gif addr=0x%llx",
+	    (long long)DEV_PS2_GIF_FAKE_BASE);
+	device_add(devinit->machine, str);
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_PS2_GS_LENGTH, dev_ps2_gs_access, d,
+	    DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_ps2_gs.cc gxemul-0.7.0+dfsg/src/devices/dev_ps2_gs.cc
--- gxemul-0.6.2/src/devices/dev_ps2_gs.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ps2_gs.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,158 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: PlayStation 2 graphics system
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define	DEV_PS2_GS_LENGTH		0x2000
-
-/*  NOTE/TODO: This should be the same as in ps2_stuff:  */
-#define	DEV_PS2_GIF_FAKE_BASE		0x50000000
-
-#define	N_GS_REGS	0x108
-
-struct gs_data {
-	uint64_t	reg[N_GS_REGS];		/*  GS registers  */
-};
-
-#define	GS_S_PMODE_REG		0x00
-#define	GS_S_SMODE1_REG		0x01
-#define	GS_S_SMODE2_REG		0x02
-#define	GS_S_SRFSH_REG		0x03
-#define	GS_S_SYNCH1_REG		0x04
-#define	GS_S_SYNCH2_REG		0x05
-#define	GS_S_SYNCV_REG		0x06
-#define	GS_S_DISPFB1_REG	0x07
-#define	GS_S_DISPLAY1_REG	0x08
-#define	GS_S_DISPFB2_REG	0x09
-#define	GS_S_DISPLAY2_REG	0x0a
-#define	GS_S_EXTBUF_REG0	0x0b
-#define	GS_S_EXTDATA_REG	0x0c
-#define	GS_S_EXTWRITE_REG	0x0d
-#define	GS_S_BGCOLOR_REG	0x0e
-
-//static const char *gs_reg_names[15] = {
-//	"PMODE", "SMODE1", "SMODE2", "SRFSH",
-//	"SYNCH1", "SYNCH2", "SYNCV", "DISPFB1",
-//	"DISPLAY1", "DISPFB2", "DISPLAY2", "EXTBUF",
-//	"EXTDATA", "EXTWRITE", "BGCOLOR"  };
-
-#define	GS_S_CSR_REG		0x100
-#define	GS_S_IMR_REG		0x101
-#define	GS_S_BUSDIR_REG		0x104
-#define	GS_S_SIGLBLID_REG	0x108
-
-//static const char *gs_reg_high_names[4] = {
-//	"CSR", "IMR", "BUSDIR", "SIGLBLID"
-//	};
-
-
-DEVICE_ACCESS(ps2_gs)
-{
-	struct gs_data *d = (struct gs_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	size_t i;
-	int regnr;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	regnr = relative_addr / 16;
-	if (relative_addr & 0xf) {
-		debug("[ gs unaligned access, addr 0x%x ]\n",
-		    (int)relative_addr);
-		return 0;
-	}
-
-	/*  Empty the GS FIFO:  */
-	d->reg[GS_S_CSR_REG] &= ~(3 << 14);
-	d->reg[GS_S_CSR_REG] |=  (1 << 14);
-
-	switch (relative_addr) {
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ gs read from addr 0x%x ]\n",
-			    (int)relative_addr);
-			odata = d->reg[regnr];
-		} else {
-			debug("[ gs write to addr 0x%x:", (int)relative_addr);
-			for (i=0; i<len; i++)
-				debug(" %02x", data[i]);
-			debug(" ]\n");
-			d->reg[regnr] = idata;
-			return 1;
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  devinit_ps2_gs():
- *
- *  Initialize the Playstation 2 graphics system. This is a bit tricky.
- *  'gs' is the memory mapped device, as seen by the main processor.
- *  'gif' is another thing which has its own memory.  DMA is used to
- *  transfer stuff to the gif from the main memory.
- *  There is also a framebuffer, which is separated from the main
- *  memory.
- *
- *  TODO:  Make this clearer.
- */
-DEVINIT(ps2_gs)
-{
-	struct gs_data *d;
-	char str[100];
-
-	CHECK_ALLOCATION(d = (struct gs_data *) malloc(sizeof(struct gs_data)));
-	memset(d, 0, sizeof(struct gs_data));
-
-	snprintf(str, sizeof(str) - 1, "ps2_gif addr=0x%llx",
-	    (long long)DEV_PS2_GIF_FAKE_BASE);
-	device_add(devinit->machine, str);
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_PS2_GS_LENGTH, dev_ps2_gs_access, d,
-	    DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_ps2_spd.c gxemul-0.7.0+dfsg/src/devices/dev_ps2_spd.c
--- gxemul-0.6.2/src/devices/dev_ps2_spd.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ps2_spd.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,117 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: PlayStation 2 SPD harddisk controller
+ *
+ *  TODO
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	DEV_PS2_SPD_LENGTH		0x800
+
+
+struct ps2_spd_data {
+	uint64_t		wdcaddr;
+};
+
+
+DEVICE_ACCESS(ps2_spd)
+{
+	struct ps2_spd_data *d = (struct ps2_spd_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	case 0x40:
+	case 0x42:
+	case 0x44:
+	case 0x46:
+	case 0x48:
+	case 0x4a:
+	case 0x4c:
+	case 0x4e:
+		debug("[ ps2_spd: wdc access ]\n");
+		cpu->memory_rw(cpu, mem, (relative_addr - 0x40) / 2 +
+		    d->wdcaddr, data, len, writeflag, PHYSICAL);
+		return 1;
+	case 0x5c:	/*  aux control  */
+		debug("[ ps2_spd: wdc access (2) ]\n");
+		cpu->memory_rw(cpu, mem, d->wdcaddr + 0x206, data, len,
+		    writeflag, PHYSICAL);
+		return 1;
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ ps2_spd: read from addr 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)odata);
+		} else {
+			debug("[ ps2_spd: write to addr 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(ps2_spd)
+{
+	struct ps2_spd_data *d;
+	char tmpstr[200];
+
+	CHECK_ALLOCATION(d = (struct ps2_spd_data *) malloc(sizeof(struct ps2_spd_data)));
+	memset(d, 0, sizeof(struct ps2_spd_data));
+
+	d->wdcaddr = devinit->addr + DEV_PS2_SPD_LENGTH;
+
+	memory_device_register(devinit->machine->memory, "ps2_spd",
+	    devinit->addr, DEV_PS2_SPD_LENGTH,
+	    dev_ps2_spd_access, d, DM_DEFAULT, NULL);
+
+	/*  Register a generic wdc device at a bogus address:  */
+	/*  IRQ = PS2 SBUS irq 0  */
+	snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s.ps2_sbus.0",
+	    (long long)d->wdcaddr, devinit->interrupt_path);
+	device_add(devinit->machine, tmpstr);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_ps2_spd.cc gxemul-0.7.0+dfsg/src/devices/dev_ps2_spd.cc
--- gxemul-0.6.2/src/devices/dev_ps2_spd.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ps2_spd.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,117 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: PlayStation 2 SPD harddisk controller
- *
- *  TODO
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define	DEV_PS2_SPD_LENGTH		0x800
-
-
-struct ps2_spd_data {
-	uint64_t		wdcaddr;
-};
-
-
-DEVICE_ACCESS(ps2_spd)
-{
-	struct ps2_spd_data *d = (struct ps2_spd_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	case 0x40:
-	case 0x42:
-	case 0x44:
-	case 0x46:
-	case 0x48:
-	case 0x4a:
-	case 0x4c:
-	case 0x4e:
-		debug("[ ps2_spd: wdc access ]\n");
-		cpu->memory_rw(cpu, mem, (relative_addr - 0x40) / 2 +
-		    d->wdcaddr, data, len, writeflag, PHYSICAL);
-		return 1;
-	case 0x5c:	/*  aux control  */
-		debug("[ ps2_spd: wdc access (2) ]\n");
-		cpu->memory_rw(cpu, mem, d->wdcaddr + 0x206, data, len,
-		    writeflag, PHYSICAL);
-		return 1;
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ ps2_spd: read from addr 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)odata);
-		} else {
-			debug("[ ps2_spd: write to addr 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(ps2_spd)
-{
-	struct ps2_spd_data *d;
-	char tmpstr[200];
-
-	CHECK_ALLOCATION(d = (struct ps2_spd_data *) malloc(sizeof(struct ps2_spd_data)));
-	memset(d, 0, sizeof(struct ps2_spd_data));
-
-	d->wdcaddr = devinit->addr + DEV_PS2_SPD_LENGTH;
-
-	memory_device_register(devinit->machine->memory, "ps2_spd",
-	    devinit->addr, DEV_PS2_SPD_LENGTH,
-	    dev_ps2_spd_access, d, DM_DEFAULT, NULL);
-
-	/*  Register a generic wdc device at a bogus address:  */
-	/*  IRQ = PS2 SBUS irq 0  */
-	snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s.ps2_sbus.0",
-	    (long long)d->wdcaddr, devinit->interrupt_path);
-	device_add(devinit->machine, tmpstr);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_ps2_stuff.c gxemul-0.7.0+dfsg/src/devices/dev_ps2_stuff.c
--- gxemul-0.6.2/src/devices/dev_ps2_stuff.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ps2_stuff.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,472 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: PlayStation 2 misc stuff (timer, DMA, interrupts, ...)
+ *
+ *	offset 0x0000	timer control
+ *	offset 0x8000	DMA controller
+ *	offset 0xf000	Interrupt register
+ *
+ *  The 16 normal PS2 interrupts interrupt at MIPS interrupt 2.
+ *  The 16 DMA interrupts are connected to MIPS interrupt 3.
+ *
+ *  SBUS interrupts go via PS2 interrupt 1.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/ee_timerreg.h"
+#include "thirdparty/ps2_dmacreg.h"
+
+
+#define	TICK_STEPS_SHIFT	14
+
+/*  NOTE/TODO: This should be the same as in ps2_gs:  */
+#define	DEV_PS2_GIF_FAKE_BASE		0x50000000
+
+#define	N_PS2_DMA_CHANNELS		10
+#define	N_PS2_TIMERS			4
+
+struct ps2_data {
+	uint32_t	timer_count[N_PS2_TIMERS];
+	uint32_t	timer_comp[N_PS2_TIMERS];
+	uint32_t	timer_mode[N_PS2_TIMERS];
+	uint32_t	timer_hold[N_PS2_TIMERS];
+				/*  NOTE: only 0 and 1 are valid  */
+	struct interrupt timer_irq[N_PS2_TIMERS];
+
+	uint64_t	dmac_reg[DMAC_REGSIZE / 0x10];
+	struct interrupt dmac_irq;		/*  MIPS irq 3  */
+	struct interrupt dma_channel2_irq;	/*  irq path of channel 2  */
+
+	uint64_t	other_memory_base[N_PS2_DMA_CHANNELS];
+
+	uint32_t	intr;
+	uint32_t	imask;
+	uint32_t	sbus_smflg;
+	struct interrupt intr_irq;		/*  MIPS irq 2  */
+	struct interrupt sbus_irq;		/*  PS2 irq 1  */
+};
+
+#define	DEV_PS2_LENGTH		0x10000
+
+
+void ps2_intr_interrupt_assert(struct interrupt *interrupt)
+{
+	struct ps2_data *d = (struct ps2_data *) interrupt->extra;
+	d->intr |= (1 << interrupt->line);
+	if (d->intr & d->imask)
+		INTERRUPT_ASSERT(d->intr_irq);
+}
+void ps2_intr_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct ps2_data *d = (struct ps2_data *) interrupt->extra;
+	d->intr &= ~(1 << interrupt->line);
+	if (!(d->intr & d->imask))
+		INTERRUPT_DEASSERT(d->intr_irq);
+}
+void ps2_dmac_interrupt_assert(struct interrupt *interrupt)
+{
+	struct ps2_data *d = (struct ps2_data *) interrupt->extra;
+	d->dmac_reg[0x601] |= (1 << interrupt->line);
+	/*  TODO: DMA interrupt mask?  */
+	if (d->dmac_reg[0x601] & 0xffff)
+		INTERRUPT_ASSERT(d->dmac_irq);
+}
+void ps2_dmac_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct ps2_data *d = (struct ps2_data *) interrupt->extra;
+	d->dmac_reg[0x601] &= ~(1 << interrupt->line);
+	/*  TODO: DMA interrupt mask?  */
+	if (!(d->dmac_reg[0x601] & 0xffff))
+		INTERRUPT_DEASSERT(d->dmac_irq);
+}
+void ps2_sbus_interrupt_assert(struct interrupt *interrupt)
+{
+	/*  Note: sbus irq 0 = mask 0x100, sbus irq 1 = mask 0x400  */
+	struct ps2_data *d = (struct ps2_data *) interrupt->extra;
+	d->sbus_smflg |= (1 << (8 + interrupt->line * 2));
+	/*  TODO: SBUS interrupt mask?  */
+	if (d->sbus_smflg != 0)
+		INTERRUPT_ASSERT(d->sbus_irq);
+}
+void ps2_sbus_interrupt_deassert(struct interrupt *interrupt)
+{
+	/*  Note: sbus irq 0 = mask 0x100, sbus irq 1 = mask 0x400  */
+	struct ps2_data *d = (struct ps2_data *) interrupt->extra;
+	d->sbus_smflg &= ~(1 << (8 + interrupt->line * 2));
+	/*  TODO: SBUS interrupt mask?  */
+	if (d->sbus_smflg == 0)
+		INTERRUPT_DEASSERT(d->sbus_irq);
+}
+
+
+DEVICE_TICK(ps2)
+{
+	struct ps2_data *d = (struct ps2_data *) extra;
+	int i;
+
+	/*
+	 *  Right now this interrupts every now and then.
+	 *  The main interrupt in NetBSD should be 100 Hz. TODO.
+	 */
+	for (i=0; i<N_PS2_TIMERS; i++) {
+		/*  Count-up Enable:   TODO: by how much?  */
+		if (d->timer_mode[i] & T_MODE_CUE)
+			d->timer_count[i] ++;
+
+		if (d->timer_mode[i] & (T_MODE_CMPE | T_MODE_OVFE)) {
+			/*  Zero return:  */
+			if (d->timer_mode[i] & T_MODE_ZRET)
+				d->timer_count[i] = 0;
+
+			INTERRUPT_ASSERT(d->timer_irq[i]);
+
+			/*  timer 1..3 are "single-shot"? TODO  */
+			if (i > 0) {
+				d->timer_mode[i] &=
+				    ~(T_MODE_CMPE | T_MODE_OVFF);
+			}
+		}
+	}
+}
+
+
+DEVICE_ACCESS(ps2)
+{
+	uint64_t idata = 0, odata = 0;
+	int regnr = 0;
+	struct ps2_data *d = (struct ps2_data *) extra;
+	int timer_nr = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (relative_addr >= 0x8000 && relative_addr < 0x8000 + DMAC_REGSIZE) {
+		regnr = (relative_addr - 0x8000) / 16;
+		if (writeflag == MEM_READ)
+			odata = d->dmac_reg[regnr];
+		else
+			d->dmac_reg[regnr] = idata;
+	}
+
+	/*
+	 *  Timer control:
+	 *  The four timers are at offsets 0, 0x800, 0x1000, and 0x1800.
+	 */
+	if (relative_addr < TIMER_REGSIZE) {
+		/*  0, 1, 2, or 3  */
+		timer_nr = (relative_addr & 0x1800) >> 11;
+		relative_addr &= (TIMER_OFS-1);
+	}
+
+	switch (relative_addr) {
+	case 0x0000:	/*  timer count  */
+		if (writeflag == MEM_READ) {
+			odata = d->timer_count[timer_nr];
+			if (timer_nr == 0) {
+				/*  :-)  TODO: remove this?  */
+				d->timer_count[timer_nr] ++;
+			}
+			debug("[ ps2: read timer %i count: 0x%llx ]\n",
+			    timer_nr, (long long)odata);
+		} else {
+			d->timer_count[timer_nr] = idata;
+			debug("[ ps2: write timer %i count: 0x%llx ]\n",
+			    timer_nr, (long long)idata);
+		}
+		break;
+	case 0x0010:	/*  timer mode  */
+		if (writeflag == MEM_READ) {
+			odata = d->timer_mode[timer_nr];
+			debug("[ ps2: read timer %i mode: 0x%llx ]\n",
+			    timer_nr, (long long)odata);
+		} else {
+			d->timer_mode[timer_nr] = idata;
+			debug("[ ps2: write timer %i mode: 0x%llx ]\n",
+			    timer_nr, (long long)idata);
+		}
+		break;
+	case 0x0020:	/*  timer comp  */
+		if (writeflag == MEM_READ) {
+			odata = d->timer_comp[timer_nr];
+			debug("[ ps2: read timer %i comp: 0x%llx ]\n",
+			    timer_nr, (long long)odata);
+		} else {
+			d->timer_comp[timer_nr] = idata;
+			debug("[ ps2: write timer %i comp: 0x%llx ]\n",
+			    timer_nr, (long long)idata);
+		}
+		break;
+	case 0x0030:	/*  timer hold  */
+		if (writeflag == MEM_READ) {
+			odata = d->timer_hold[timer_nr];
+			debug("[ ps2: read timer %i hold: 0x%llx ]\n",
+			    timer_nr, (long long)odata);
+			if (timer_nr >= 2)
+				fatal("[ WARNING: ps2: read from non-"
+				    "existant timer %i hold register ]\n");
+		} else {
+			d->timer_hold[timer_nr] = idata;
+			debug("[ ps2: write timer %i hold: 0x%llx ]\n",
+			    timer_nr, (long long)idata);
+			if (timer_nr >= 2)
+				fatal("[ WARNING: ps2: write to "
+				    "non-existant timer %i hold register ]\n",
+				    timer_nr);
+		}
+		break;
+
+	case 0x8000 + D2_CHCR_REG:
+		if (writeflag==MEM_READ) {
+			odata = d->dmac_reg[regnr];
+			/*  debug("[ ps2: dmac read from D2_CHCR "
+			    "(0x%llx) ]\n", (long long)d->dmac_reg[regnr]);  */
+		} else {
+			/*  debug("[ ps2: dmac write to D2_CHCR, "
+			    "data 0x%016llx ]\n", (long long) idata);  */
+			if (idata & D_CHCR_STR) {
+				int length = d->dmac_reg[D2_QWC_REG/0x10] * 16;
+				uint64_t from_addr = d->dmac_reg[
+				    D2_MADR_REG/0x10];
+				uint64_t to_addr   = d->dmac_reg[
+				    D2_TADR_REG/0x10];
+				unsigned char *copy_buf;
+
+				debug("[ ps2: dmac [ch2] transfer addr="
+				    "0x%016llx len=0x%lx ]\n", (long long)
+				    d->dmac_reg[D2_MADR_REG/0x10],
+				    (long)length);
+
+				CHECK_ALLOCATION(copy_buf = (unsigned char *) malloc(length));
+
+				cpu->memory_rw(cpu, cpu->mem, from_addr,
+				    copy_buf, length, MEM_READ,
+				    CACHE_NONE | PHYSICAL);
+				cpu->memory_rw(cpu, cpu->mem,
+				    d->other_memory_base[DMA_CH_GIF] + to_addr,
+				    copy_buf, length, MEM_WRITE,
+				    CACHE_NONE | PHYSICAL);
+				free(copy_buf);
+
+				/*  Done with the transfer:  */
+				d->dmac_reg[D2_QWC_REG/0x10] = 0;
+				idata &= ~D_CHCR_STR;
+
+				/*  interrupt DMA channel 2  */
+				INTERRUPT_ASSERT(d->dma_channel2_irq);
+			} else
+				debug("[ ps2: dmac [ch2] stopping "
+				    "transfer ]\n");
+			d->dmac_reg[regnr] = idata;
+			return 1;
+		}
+		break;
+
+	case 0x8000 + D2_QWC_REG:
+	case 0x8000 + D2_MADR_REG:
+	case 0x8000 + D2_TADR_REG:
+		/*  no debug output  */
+		break;
+
+	case 0xe010:	/*  dmac interrupt status (and mask,  */
+			/*  the upper 16 bits)  */
+		if (writeflag == MEM_WRITE) {
+			uint32_t oldmask = d->dmac_reg[regnr] & 0xffff0000;
+			/*  Clear out those bits that are set in idata:  */
+			d->dmac_reg[regnr] &= ~idata;
+			d->dmac_reg[regnr] &= 0xffff;
+			d->dmac_reg[regnr] |= oldmask;
+			if (((d->dmac_reg[regnr] & 0xffff) &
+			    ((d->dmac_reg[regnr]>>16) & 0xffff)) == 0) {
+				INTERRUPT_DEASSERT(d->dmac_irq);
+			}
+		} else {
+			/*  Hm... make it seem like the mask bits are (at
+			    least as much as) the interrupt assertions:  */
+			odata = d->dmac_reg[regnr];
+			odata |= (odata << 16);
+		}
+		break;
+
+	case 0xf000:	/*  interrupt register  */
+		if (writeflag == MEM_READ) {
+			odata = d->intr;
+			debug("[ ps2: read from Interrupt Register:"
+			    " 0x%llx ]\n", (long long)odata);
+
+			/*  TODO: This is _NOT_ correct behavior:  */
+//			d->intr = 0;
+//			INTERRUPT_DEASSERT(d->intr_irq);
+		} else {
+			debug("[ ps2: write to Interrupt Register: "
+			    "0x%llx ]\n", (long long)idata);
+			/*  Clear out bits that are set in idata:  */
+			d->intr &= ~idata;
+
+			if ((d->intr & d->imask) == 0)
+				INTERRUPT_DEASSERT(d->intr_irq);
+		}
+		break;
+
+	case 0xf010:	/*  interrupt mask  */
+		if (writeflag == MEM_READ) {
+			odata = d->imask;
+			/*  debug("[ ps2: read from Interrupt Mask "
+			    "Register: 0x%llx ]\n", (long long)odata);  */
+		} else {
+			/*  debug("[ ps2: write to Interrupt Mask "
+			    "Register: 0x%llx ]\n", (long long)idata);  */
+			/*  Note: written value indicates which bits
+			    to _toggle_, not which bits to set!  */
+			d->imask ^= idata;
+		}
+		break;
+
+	case 0xf230:	/*  sbus interrupt register?  */
+		if (writeflag == MEM_READ) {
+			odata = d->sbus_smflg;
+			debug("[ ps2: read from SBUS SMFLG:"
+			    " 0x%llx ]\n", (long long)odata);
+		} else {
+			/*  Clear bits on write:  */
+			debug("[ ps2: write to SBUS SMFLG:"
+			    " 0x%llx ]\n", (long long)idata);
+			d->sbus_smflg &= ~idata;
+			/*  irq 1 is SBUS  */
+			if (d->sbus_smflg == 0)
+				INTERRUPT_DEASSERT(d->sbus_irq);
+		}
+		break;
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ ps2: read from addr 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)odata);
+		} else {
+			debug("[ ps2: write to addr 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(ps2)
+{
+	struct ps2_data *d;
+	int i;
+	struct interrupt templ;
+	char n[300];
+
+	CHECK_ALLOCATION(d = (struct ps2_data *) malloc(sizeof(struct ps2_data)));
+	memset(d, 0, sizeof(struct ps2_data));
+
+	d->other_memory_base[DMA_CH_GIF] = DEV_PS2_GIF_FAKE_BASE;
+
+	/*  Connect to MIPS irq 2 (interrupt controller) and 3 (dmac):  */
+	snprintf(n, sizeof(n), "%s.2", devinit->interrupt_path);
+	INTERRUPT_CONNECT(n, d->intr_irq);
+	snprintf(n, sizeof(n), "%s.3", devinit->interrupt_path);
+	INTERRUPT_CONNECT(n, d->dmac_irq);
+
+	/*
+	 *  Register interrupts:
+	 *
+	 *	16 normal IRQs	(machine[x].cpu[x].ps2_intr.%i)
+	 *	16 DMA IRQs	(machine[x].cpu[x].ps2_dmac.%i)
+	 *	 2 sbus IRQs	(machine[x].cpu[x].ps2_sbus.%i)
+	 */
+	for (i=0; i<16; i++) {
+		snprintf(n, sizeof(n), "%s.ps2_intr.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = ps2_intr_interrupt_assert;
+		templ.interrupt_deassert = ps2_intr_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+	for (i=0; i<16; i++) {
+		snprintf(n, sizeof(n), "%s.ps2_dmac.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = ps2_dmac_interrupt_assert;
+		templ.interrupt_deassert = ps2_dmac_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+	for (i=0; i<2; i++) {
+		snprintf(n, sizeof(n), "%s.ps2_sbus.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = ps2_sbus_interrupt_assert;
+		templ.interrupt_deassert = ps2_sbus_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	/*  Connect to DMA channel 2 irq:  */
+	snprintf(n, sizeof(n), "%s.ps2_dmac.2", devinit->interrupt_path);
+	INTERRUPT_CONNECT(n, d->dma_channel2_irq);
+
+	/*  Connect to SBUS interrupt, at ps2 interrupt 1:  */
+	snprintf(n, sizeof(n), "%s.ps2_intr.1", devinit->interrupt_path);
+	INTERRUPT_CONNECT(n, d->sbus_irq);
+
+	/*  Connect to the timers' interrupts:  */
+	for (i=0; i<N_PS2_TIMERS; i++) {
+		/*  PS2 irq 9 is timer0, etc.  */
+		snprintf(n, sizeof(n), "%s.ps2_intr.%i",
+		    devinit->interrupt_path, 9 + i);
+		INTERRUPT_CONNECT(n, d->timer_irq[i]);
+	}
+
+	memory_device_register(devinit->machine->memory, "ps2", devinit->addr,
+	    DEV_PS2_LENGTH, dev_ps2_access, d, DM_DEFAULT, NULL);
+	machine_add_tickfunction(devinit->machine,
+	    dev_ps2_tick, d, TICK_STEPS_SHIFT);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_ps2_stuff.cc gxemul-0.7.0+dfsg/src/devices/dev_ps2_stuff.cc
--- gxemul-0.6.2/src/devices/dev_ps2_stuff.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ps2_stuff.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,472 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: PlayStation 2 misc stuff (timer, DMA, interrupts, ...)
- *
- *	offset 0x0000	timer control
- *	offset 0x8000	DMA controller
- *	offset 0xf000	Interrupt register
- *
- *  The 16 normal PS2 interrupts interrupt at MIPS interrupt 2.
- *  The 16 DMA interrupts are connected to MIPS interrupt 3.
- *
- *  SBUS interrupts go via PS2 interrupt 1.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/ee_timerreg.h"
-#include "thirdparty/ps2_dmacreg.h"
-
-
-#define	TICK_STEPS_SHIFT	14
-
-/*  NOTE/TODO: This should be the same as in ps2_gs:  */
-#define	DEV_PS2_GIF_FAKE_BASE		0x50000000
-
-#define	N_PS2_DMA_CHANNELS		10
-#define	N_PS2_TIMERS			4
-
-struct ps2_data {
-	uint32_t	timer_count[N_PS2_TIMERS];
-	uint32_t	timer_comp[N_PS2_TIMERS];
-	uint32_t	timer_mode[N_PS2_TIMERS];
-	uint32_t	timer_hold[N_PS2_TIMERS];
-				/*  NOTE: only 0 and 1 are valid  */
-	struct interrupt timer_irq[N_PS2_TIMERS];
-
-	uint64_t	dmac_reg[DMAC_REGSIZE / 0x10];
-	struct interrupt dmac_irq;		/*  MIPS irq 3  */
-	struct interrupt dma_channel2_irq;	/*  irq path of channel 2  */
-
-	uint64_t	other_memory_base[N_PS2_DMA_CHANNELS];
-
-	uint32_t	intr;
-	uint32_t	imask;
-	uint32_t	sbus_smflg;
-	struct interrupt intr_irq;		/*  MIPS irq 2  */
-	struct interrupt sbus_irq;		/*  PS2 irq 1  */
-};
-
-#define	DEV_PS2_LENGTH		0x10000
-
-
-void ps2_intr_interrupt_assert(struct interrupt *interrupt)
-{
-	struct ps2_data *d = (struct ps2_data *) interrupt->extra;
-	d->intr |= (1 << interrupt->line);
-	if (d->intr & d->imask)
-		INTERRUPT_ASSERT(d->intr_irq);
-}
-void ps2_intr_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct ps2_data *d = (struct ps2_data *) interrupt->extra;
-	d->intr &= ~(1 << interrupt->line);
-	if (!(d->intr & d->imask))
-		INTERRUPT_DEASSERT(d->intr_irq);
-}
-void ps2_dmac_interrupt_assert(struct interrupt *interrupt)
-{
-	struct ps2_data *d = (struct ps2_data *) interrupt->extra;
-	d->dmac_reg[0x601] |= (1 << interrupt->line);
-	/*  TODO: DMA interrupt mask?  */
-	if (d->dmac_reg[0x601] & 0xffff)
-		INTERRUPT_ASSERT(d->dmac_irq);
-}
-void ps2_dmac_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct ps2_data *d = (struct ps2_data *) interrupt->extra;
-	d->dmac_reg[0x601] &= ~(1 << interrupt->line);
-	/*  TODO: DMA interrupt mask?  */
-	if (!(d->dmac_reg[0x601] & 0xffff))
-		INTERRUPT_DEASSERT(d->dmac_irq);
-}
-void ps2_sbus_interrupt_assert(struct interrupt *interrupt)
-{
-	/*  Note: sbus irq 0 = mask 0x100, sbus irq 1 = mask 0x400  */
-	struct ps2_data *d = (struct ps2_data *) interrupt->extra;
-	d->sbus_smflg |= (1 << (8 + interrupt->line * 2));
-	/*  TODO: SBUS interrupt mask?  */
-	if (d->sbus_smflg != 0)
-		INTERRUPT_ASSERT(d->sbus_irq);
-}
-void ps2_sbus_interrupt_deassert(struct interrupt *interrupt)
-{
-	/*  Note: sbus irq 0 = mask 0x100, sbus irq 1 = mask 0x400  */
-	struct ps2_data *d = (struct ps2_data *) interrupt->extra;
-	d->sbus_smflg &= ~(1 << (8 + interrupt->line * 2));
-	/*  TODO: SBUS interrupt mask?  */
-	if (d->sbus_smflg == 0)
-		INTERRUPT_DEASSERT(d->sbus_irq);
-}
-
-
-DEVICE_TICK(ps2)
-{
-	struct ps2_data *d = (struct ps2_data *) extra;
-	int i;
-
-	/*
-	 *  Right now this interrupts every now and then.
-	 *  The main interrupt in NetBSD should be 100 Hz. TODO.
-	 */
-	for (i=0; i<N_PS2_TIMERS; i++) {
-		/*  Count-up Enable:   TODO: by how much?  */
-		if (d->timer_mode[i] & T_MODE_CUE)
-			d->timer_count[i] ++;
-
-		if (d->timer_mode[i] & (T_MODE_CMPE | T_MODE_OVFE)) {
-			/*  Zero return:  */
-			if (d->timer_mode[i] & T_MODE_ZRET)
-				d->timer_count[i] = 0;
-
-			INTERRUPT_ASSERT(d->timer_irq[i]);
-
-			/*  timer 1..3 are "single-shot"? TODO  */
-			if (i > 0) {
-				d->timer_mode[i] &=
-				    ~(T_MODE_CMPE | T_MODE_OVFF);
-			}
-		}
-	}
-}
-
-
-DEVICE_ACCESS(ps2)
-{
-	uint64_t idata = 0, odata = 0;
-	int regnr = 0;
-	struct ps2_data *d = (struct ps2_data *) extra;
-	int timer_nr = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (relative_addr >= 0x8000 && relative_addr < 0x8000 + DMAC_REGSIZE) {
-		regnr = (relative_addr - 0x8000) / 16;
-		if (writeflag == MEM_READ)
-			odata = d->dmac_reg[regnr];
-		else
-			d->dmac_reg[regnr] = idata;
-	}
-
-	/*
-	 *  Timer control:
-	 *  The four timers are at offsets 0, 0x800, 0x1000, and 0x1800.
-	 */
-	if (relative_addr < TIMER_REGSIZE) {
-		/*  0, 1, 2, or 3  */
-		timer_nr = (relative_addr & 0x1800) >> 11;
-		relative_addr &= (TIMER_OFS-1);
-	}
-
-	switch (relative_addr) {
-	case 0x0000:	/*  timer count  */
-		if (writeflag == MEM_READ) {
-			odata = d->timer_count[timer_nr];
-			if (timer_nr == 0) {
-				/*  :-)  TODO: remove this?  */
-				d->timer_count[timer_nr] ++;
-			}
-			debug("[ ps2: read timer %i count: 0x%llx ]\n",
-			    timer_nr, (long long)odata);
-		} else {
-			d->timer_count[timer_nr] = idata;
-			debug("[ ps2: write timer %i count: 0x%llx ]\n",
-			    timer_nr, (long long)idata);
-		}
-		break;
-	case 0x0010:	/*  timer mode  */
-		if (writeflag == MEM_READ) {
-			odata = d->timer_mode[timer_nr];
-			debug("[ ps2: read timer %i mode: 0x%llx ]\n",
-			    timer_nr, (long long)odata);
-		} else {
-			d->timer_mode[timer_nr] = idata;
-			debug("[ ps2: write timer %i mode: 0x%llx ]\n",
-			    timer_nr, (long long)idata);
-		}
-		break;
-	case 0x0020:	/*  timer comp  */
-		if (writeflag == MEM_READ) {
-			odata = d->timer_comp[timer_nr];
-			debug("[ ps2: read timer %i comp: 0x%llx ]\n",
-			    timer_nr, (long long)odata);
-		} else {
-			d->timer_comp[timer_nr] = idata;
-			debug("[ ps2: write timer %i comp: 0x%llx ]\n",
-			    timer_nr, (long long)idata);
-		}
-		break;
-	case 0x0030:	/*  timer hold  */
-		if (writeflag == MEM_READ) {
-			odata = d->timer_hold[timer_nr];
-			debug("[ ps2: read timer %i hold: 0x%llx ]\n",
-			    timer_nr, (long long)odata);
-			if (timer_nr >= 2)
-				fatal("[ WARNING: ps2: read from non-"
-				    "existant timer %i hold register ]\n");
-		} else {
-			d->timer_hold[timer_nr] = idata;
-			debug("[ ps2: write timer %i hold: 0x%llx ]\n",
-			    timer_nr, (long long)idata);
-			if (timer_nr >= 2)
-				fatal("[ WARNING: ps2: write to "
-				    "non-existant timer %i hold register ]\n",
-				    timer_nr);
-		}
-		break;
-
-	case 0x8000 + D2_CHCR_REG:
-		if (writeflag==MEM_READ) {
-			odata = d->dmac_reg[regnr];
-			/*  debug("[ ps2: dmac read from D2_CHCR "
-			    "(0x%llx) ]\n", (long long)d->dmac_reg[regnr]);  */
-		} else {
-			/*  debug("[ ps2: dmac write to D2_CHCR, "
-			    "data 0x%016llx ]\n", (long long) idata);  */
-			if (idata & D_CHCR_STR) {
-				int length = d->dmac_reg[D2_QWC_REG/0x10] * 16;
-				uint64_t from_addr = d->dmac_reg[
-				    D2_MADR_REG/0x10];
-				uint64_t to_addr   = d->dmac_reg[
-				    D2_TADR_REG/0x10];
-				unsigned char *copy_buf;
-
-				debug("[ ps2: dmac [ch2] transfer addr="
-				    "0x%016llx len=0x%lx ]\n", (long long)
-				    d->dmac_reg[D2_MADR_REG/0x10],
-				    (long)length);
-
-				CHECK_ALLOCATION(copy_buf = (unsigned char *) malloc(length));
-
-				cpu->memory_rw(cpu, cpu->mem, from_addr,
-				    copy_buf, length, MEM_READ,
-				    CACHE_NONE | PHYSICAL);
-				cpu->memory_rw(cpu, cpu->mem,
-				    d->other_memory_base[DMA_CH_GIF] + to_addr,
-				    copy_buf, length, MEM_WRITE,
-				    CACHE_NONE | PHYSICAL);
-				free(copy_buf);
-
-				/*  Done with the transfer:  */
-				d->dmac_reg[D2_QWC_REG/0x10] = 0;
-				idata &= ~D_CHCR_STR;
-
-				/*  interrupt DMA channel 2  */
-				INTERRUPT_ASSERT(d->dma_channel2_irq);
-			} else
-				debug("[ ps2: dmac [ch2] stopping "
-				    "transfer ]\n");
-			d->dmac_reg[regnr] = idata;
-			return 1;
-		}
-		break;
-
-	case 0x8000 + D2_QWC_REG:
-	case 0x8000 + D2_MADR_REG:
-	case 0x8000 + D2_TADR_REG:
-		/*  no debug output  */
-		break;
-
-	case 0xe010:	/*  dmac interrupt status (and mask,  */
-			/*  the upper 16 bits)  */
-		if (writeflag == MEM_WRITE) {
-			uint32_t oldmask = d->dmac_reg[regnr] & 0xffff0000;
-			/*  Clear out those bits that are set in idata:  */
-			d->dmac_reg[regnr] &= ~idata;
-			d->dmac_reg[regnr] &= 0xffff;
-			d->dmac_reg[regnr] |= oldmask;
-			if (((d->dmac_reg[regnr] & 0xffff) &
-			    ((d->dmac_reg[regnr]>>16) & 0xffff)) == 0) {
-				INTERRUPT_DEASSERT(d->dmac_irq);
-			}
-		} else {
-			/*  Hm... make it seem like the mask bits are (at
-			    least as much as) the interrupt assertions:  */
-			odata = d->dmac_reg[regnr];
-			odata |= (odata << 16);
-		}
-		break;
-
-	case 0xf000:	/*  interrupt register  */
-		if (writeflag == MEM_READ) {
-			odata = d->intr;
-			debug("[ ps2: read from Interrupt Register:"
-			    " 0x%llx ]\n", (long long)odata);
-
-			/*  TODO: This is _NOT_ correct behavior:  */
-//			d->intr = 0;
-//			INTERRUPT_DEASSERT(d->intr_irq);
-		} else {
-			debug("[ ps2: write to Interrupt Register: "
-			    "0x%llx ]\n", (long long)idata);
-			/*  Clear out bits that are set in idata:  */
-			d->intr &= ~idata;
-
-			if ((d->intr & d->imask) == 0)
-				INTERRUPT_DEASSERT(d->intr_irq);
-		}
-		break;
-
-	case 0xf010:	/*  interrupt mask  */
-		if (writeflag == MEM_READ) {
-			odata = d->imask;
-			/*  debug("[ ps2: read from Interrupt Mask "
-			    "Register: 0x%llx ]\n", (long long)odata);  */
-		} else {
-			/*  debug("[ ps2: write to Interrupt Mask "
-			    "Register: 0x%llx ]\n", (long long)idata);  */
-			/*  Note: written value indicates which bits
-			    to _toggle_, not which bits to set!  */
-			d->imask ^= idata;
-		}
-		break;
-
-	case 0xf230:	/*  sbus interrupt register?  */
-		if (writeflag == MEM_READ) {
-			odata = d->sbus_smflg;
-			debug("[ ps2: read from SBUS SMFLG:"
-			    " 0x%llx ]\n", (long long)odata);
-		} else {
-			/*  Clear bits on write:  */
-			debug("[ ps2: write to SBUS SMFLG:"
-			    " 0x%llx ]\n", (long long)idata);
-			d->sbus_smflg &= ~idata;
-			/*  irq 1 is SBUS  */
-			if (d->sbus_smflg == 0)
-				INTERRUPT_DEASSERT(d->sbus_irq);
-		}
-		break;
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ ps2: read from addr 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)odata);
-		} else {
-			debug("[ ps2: write to addr 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(ps2)
-{
-	struct ps2_data *d;
-	int i;
-	struct interrupt templ;
-	char n[300];
-
-	CHECK_ALLOCATION(d = (struct ps2_data *) malloc(sizeof(struct ps2_data)));
-	memset(d, 0, sizeof(struct ps2_data));
-
-	d->other_memory_base[DMA_CH_GIF] = DEV_PS2_GIF_FAKE_BASE;
-
-	/*  Connect to MIPS irq 2 (interrupt controller) and 3 (dmac):  */
-	snprintf(n, sizeof(n), "%s.2", devinit->interrupt_path);
-	INTERRUPT_CONNECT(n, d->intr_irq);
-	snprintf(n, sizeof(n), "%s.3", devinit->interrupt_path);
-	INTERRUPT_CONNECT(n, d->dmac_irq);
-
-	/*
-	 *  Register interrupts:
-	 *
-	 *	16 normal IRQs	(machine[x].cpu[x].ps2_intr.%i)
-	 *	16 DMA IRQs	(machine[x].cpu[x].ps2_dmac.%i)
-	 *	 2 sbus IRQs	(machine[x].cpu[x].ps2_sbus.%i)
-	 */
-	for (i=0; i<16; i++) {
-		snprintf(n, sizeof(n), "%s.ps2_intr.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = ps2_intr_interrupt_assert;
-		templ.interrupt_deassert = ps2_intr_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-	for (i=0; i<16; i++) {
-		snprintf(n, sizeof(n), "%s.ps2_dmac.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = ps2_dmac_interrupt_assert;
-		templ.interrupt_deassert = ps2_dmac_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-	for (i=0; i<2; i++) {
-		snprintf(n, sizeof(n), "%s.ps2_sbus.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = ps2_sbus_interrupt_assert;
-		templ.interrupt_deassert = ps2_sbus_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	/*  Connect to DMA channel 2 irq:  */
-	snprintf(n, sizeof(n), "%s.ps2_dmac.2", devinit->interrupt_path);
-	INTERRUPT_CONNECT(n, d->dma_channel2_irq);
-
-	/*  Connect to SBUS interrupt, at ps2 interrupt 1:  */
-	snprintf(n, sizeof(n), "%s.ps2_intr.1", devinit->interrupt_path);
-	INTERRUPT_CONNECT(n, d->sbus_irq);
-
-	/*  Connect to the timers' interrupts:  */
-	for (i=0; i<N_PS2_TIMERS; i++) {
-		/*  PS2 irq 9 is timer0, etc.  */
-		snprintf(n, sizeof(n), "%s.ps2_intr.%i",
-		    devinit->interrupt_path, 9 + i);
-		INTERRUPT_CONNECT(n, d->timer_irq[i]);
-	}
-
-	memory_device_register(devinit->machine->memory, "ps2", devinit->addr,
-	    DEV_PS2_LENGTH, dev_ps2_access, d, DM_DEFAULT, NULL);
-	machine_add_tickfunction(devinit->machine,
-	    dev_ps2_tick, d, TICK_STEPS_SHIFT);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_pvr.c gxemul-0.7.0+dfsg/src/devices/dev_pvr.c
--- gxemul-0.6.2/src/devices/dev_pvr.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pvr.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,2593 @@
+/*
+ *  Copyright (C) 2006-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: PowerVR CLX2 (graphics controller used in the Dreamcast)
+ *
+ *  Implemented by reading http://www.ludd.luth.se/~jlo/dc/powervr-reg.txt and
+ *  http://mc.pp.se/dc/pvr.html, source code of various demos and KallistiOS,
+ *  attempting to run the PROM from my own Dreamcast, and doing a lot of
+ *  guessing.
+ *
+ *  TODO: Almost everything
+ *
+ *	x)  Change resolution during runtime (PAL/NTSC/???)
+ *
+ *	x)  Lots of work on the 3D "Tile Accelerator" engine.
+ *		Recognize commands and turn into OpenGL or similar
+ *		commands on the host?
+ *		Wire-frame when running on a host without XGL?
+ *
+ *  Multiple lists of various kinds (6?).
+ *  Lists growing downwards!
+ *  Pixel clip for rendering.
+ *  Real Rendering, using OpenGL if possible.
+ *  Tile bins... with 6 pointers for each tile (?)
+ *  PVR DMA.
+ *  Textures.
+ *  ...
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "float_emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "timer.h"
+
+#include "thirdparty/dreamcast_pvr.h"
+#include "thirdparty/dreamcast_sysasicvar.h"
+
+
+/* For debugging: */
+//#define DEBUG_RENDER_AS_WIRE_FRAME	// Renders 3-corner textured polygons as wire-frame
+static int ta_debug = 0;		// Dumps TA commands
+//#define debug fatal			// Dumps debug even without -v.
+
+#define	INTERNAL_FB_ADDR	0x300000000ULL
+#define	PVR_FB_TICK_SHIFT	18
+
+#define	PVR_VBLANK_HZ		60.0
+
+#define	PVR_MARGIN		16
+
+#define	VRAM_SIZE		(8*1048576)
+
+/*  DMA:  */
+#define	PVR_DMA_MEMLENGTH	0x100
+#define	N_PVR_DMA_REGS		(PVR_DMA_MEMLENGTH / sizeof(uint32_t))
+
+#define	PVR_ADDR		0x00
+#define	PVR_COUNT		0x04
+#define	PVR_MODE		0x08
+#define	PVR_LMMODE0		0x84  
+#define	PVR_LMMODE1		0x88
+
+
+struct pvr_data {
+	struct vfb_data		*fb;
+	int			fb_update_x1;
+	int			fb_update_y1;
+	int			fb_update_x2;
+	int			fb_update_y2;
+
+	struct timer		*vblank_timer;
+	int			vblank_interrupts_pending;
+
+	/*  PVR registers:  */
+	uint32_t		reg[PVRREG_REGSIZE / sizeof(uint32_t)];
+
+	/*  Calculated by pvr_geometry_updated():  */
+	int			xsize, ysize;
+	int			bytes_per_pixel;
+
+	/*  Cached values (from registers):  */
+	/*  DIWMODE:  */
+	int			clock_double;
+	int			strip_buffer_enabled;
+	int			strip_length;
+	int			argb8888_threshold;
+	int			extend;
+	int			pixelmode;
+	int			line_double;
+	int			display_enabled;
+	/*  BRDCOLR:  */
+	int			border_updated;
+	/*  SYNCCONF:  */
+	int			video_enabled;
+	int			broadcast_standard;
+	int			interlaced;
+	int			h_sync_positive;
+	int			v_sync_positive;
+	/*  TILEBUF_SIZE:  */
+	int			tilebuf_xsize;
+	int			tilebuf_ysize;
+
+	/*  Current Tile Accelerator Command (64 bytes):  */
+	uint32_t		ta[64 / sizeof(uint32_t)];
+
+	/*  Stored list of TA commands:  */
+	int			current_list_type;
+	uint32_t		*ta_commands;
+	size_t			allocated_ta_commands;
+	size_t			n_ta_commands;
+
+	/*  Video RAM and Z information:  */
+	uint8_t			*vram;
+	double			*vram_z;
+
+	/*  DMA registers:  */
+	uint32_t		dma_reg[N_PVR_DMA_REGS];
+	uint32_t		dma_more_reg[N_PVR_DMA_REGS];
+};
+
+struct pvr_data_alt {
+	struct pvr_data		*d;
+};
+
+
+#define	REG(x)		(d->reg[(x)/sizeof(uint32_t)])
+#define	DEFAULT_WRITE	REG(relative_addr) = idata;
+
+
+/*  Forward declaration.  */
+DEVICE_ACCESS(pvr_ta);
+
+
+void pvr_dma_transfer(struct cpu *cpu, struct pvr_data *d)
+{
+	const int channel = 2;
+	uint32_t sar = cpu->cd.sh.dmac_sar[channel] & 0x1fffffff;
+	uint32_t dar = cpu->cd.sh.dmac_dar[channel] & 0x1fffffff;
+	uint32_t count = cpu->cd.sh.dmac_tcr[channel] & 0x1fffffff;
+	uint32_t chcr = cpu->cd.sh.dmac_chcr[channel];
+	int transmit_size = 1;
+	int src_delta = 0, dst_delta = 0;
+	int cause_interrupt = chcr & CHCR_IE;
+
+#if 0
+	// Dump all SH4 DMA channels, for debugging:
+	for (int dmaChannel = 0; dmaChannel < 4; ++dmaChannel)
+	{
+		fatal("{# dma channel %i: sar=%08x dar=%08x count=%08x chcr=%08x #}\n",
+		    dmaChannel,
+		    cpu->cd.sh.dmac_sar[dmaChannel],
+		    cpu->cd.sh.dmac_dar[dmaChannel],
+		    cpu->cd.sh.dmac_tcr[dmaChannel],
+		    cpu->cd.sh.dmac_chcr[dmaChannel]);
+	}
+#endif
+
+	/*  DMAC not enabled?  */
+	if (!(chcr & CHCR_TD)) {
+		fatal("pvr_dma_transfer: SH4 dma not enabled?\n");
+		exit(1);
+	}
+
+	/*  Transfer End already set? Then don't transfer again.  */
+	if (chcr & CHCR_TE)
+		return;
+
+	/*  Special case: 0 means 16777216:  */
+	if (count == 0)
+		count = 16777216;
+
+	switch (chcr & CHCR_TS) {
+	case CHCR_TS_8BYTE: transmit_size = 8; break;
+	case CHCR_TS_1BYTE: transmit_size = 1; break;
+	case CHCR_TS_2BYTE: transmit_size = 2; break;
+	case CHCR_TS_4BYTE: transmit_size = 4; break;
+	case CHCR_TS_32BYTE: transmit_size = 32; break;
+	default: fatal("Unimplemented transmit size?! CHCR[%i] = 0x%08x\n",
+	    channel, chcr);
+	exit(1);
+	}
+
+	switch (chcr & CHCR_DM) {
+	case CHCR_DM_FIXED:       dst_delta = 0; break;
+	case CHCR_DM_INCREMENTED: dst_delta = 1; break;
+	case CHCR_DM_DECREMENTED: dst_delta = -1; break;
+	default: fatal("Unimplemented destination delta?! CHCR[%i] = 0x%08x\n",
+	    channel, chcr);
+	exit(1);
+	}
+
+	switch (chcr & CHCR_SM) {
+	case CHCR_SM_FIXED:       src_delta = 0; break;
+	case CHCR_SM_INCREMENTED: src_delta = 1; break;
+	case CHCR_SM_DECREMENTED: src_delta = -1; break;
+	default: fatal("Unimplemented source delta?! CHCR[%i] = 0x%08x\n",
+	    channel, chcr);
+	exit(1);
+	}
+
+	src_delta *= transmit_size;
+	dst_delta *= transmit_size;
+
+	switch (chcr & CHCR_RS) {
+	case 0x200:
+		dar = d->dma_reg[PVR_ADDR / sizeof(uint32_t)];
+
+		if (dar != 0x10000000) {
+			//fatal("[ NOTE: DMA to non-TA: dar=%08x (delta %i), sar=%08x (delta %i) ]\n",
+			//    (int)dar, (int)dst_delta, (int)sar, (int)src_delta);
+			dar = 0x04000000 | (dar & 0x007fffff);
+			if (dst_delta == 0)
+				dst_delta = src_delta;
+
+			uint8_t *buf = (uint8_t*) malloc(transmit_size);
+			while (count > 0) {
+				// printf("sar = %08x dar = %08x\n", (int)sar, (int)dar);
+				
+				cpu->memory_rw(cpu, cpu->mem, sar, buf,
+				    transmit_size, MEM_READ, NO_EXCEPTIONS | PHYSICAL);
+				// for (int i = 0; i < transmit_size; ++i)
+				// 	printf("%02x ", buf[i]);
+				// printf("\n");
+
+				cpu->memory_rw(cpu, cpu->mem, dar, buf,
+				    transmit_size, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
+
+				count --;
+				sar += src_delta;
+				dar += dst_delta;
+			}
+
+			free(buf);
+
+			break;
+		} else {
+			while (count > 0) {
+				unsigned char buf[sizeof(uint32_t)];
+				int ofs;
+				size_t chunksize = transmit_size;
+
+				if (chunksize > sizeof(uint32_t))
+					chunksize = sizeof(uint32_t);
+
+				for (ofs = 0; ofs < transmit_size; ofs += chunksize) {
+					cpu->memory_rw(cpu, cpu->mem, sar + ofs, buf,
+					    chunksize, MEM_READ, NO_EXCEPTIONS | PHYSICAL);
+
+					dev_pvr_ta_access(cpu, cpu->mem, ofs, buf, chunksize,
+					    MEM_WRITE, d);
+				}
+
+				count --;
+				sar += src_delta;
+			}
+		}
+
+		// Transfer End. TODO: _EXACTLY_ what happens at the end of
+		// a transfer?
+		cpu->cd.sh.dmac_chcr[channel] |= CHCR_TE;
+		cpu->cd.sh.dmac_chcr[channel] &= ~CHCR_TD;
+		cpu->cd.sh.dmac_sar[channel] = sar;
+		cpu->cd.sh.dmac_tcr[channel] = count;
+
+		// d->dma_reg[PVR_ADDR / sizeof(uint32_t)] = ???;
+		d->dma_reg[PVR_COUNT / sizeof(uint32_t)] = 0;
+
+		SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_PVR_DMA);
+
+		break;
+	default:
+		fatal("Unimplemented SH4 RS DMAC: 0x%08x (PVR)\n",
+		    (int) (chcr & CHCR_RS));
+		exit(1);
+	}
+
+	if (cause_interrupt) {
+		fatal("TODO: pvr sh4 dmac interrupt!\n");
+		exit(1);
+	}
+}
+
+
+DEVICE_ACCESS(pvr_dma)
+{
+	struct pvr_data *d = (struct pvr_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  Default read:  */
+	if (writeflag == MEM_READ)
+		odata = d->dma_reg[relative_addr / sizeof(uint32_t)];
+
+	switch (relative_addr) {
+
+	case PVR_ADDR:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr_dma: ADDR set to 0x%08x ]\n",
+			    (int) idata);
+		}
+		break;
+
+	case PVR_COUNT:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr_dma: COUNT set to 0x%08x ]\n",
+			    (int) idata);
+		}
+		break;
+
+	case PVR_MODE:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr_dma: MODE set to 0x%08x ]\n",
+			    (int) idata);
+			if (idata != 0) {
+				pvr_dma_transfer(cpu, d);
+				idata = 0;
+			}
+		}
+		break;
+
+	/*  These are written to by the Dreamcast ROM, but I have not
+	    found them documented anywhere.  */
+	case 0x10:
+	case 0x14:
+		if (writeflag == MEM_WRITE && idata != 0x0cff0000) {
+			fatal("[ pvr_dma: TODO: unknown_0x%02x set to "
+			    "0x%08x ]\n", (int) relative_addr, (int) idata);
+			exit(1);
+		}
+		break;
+
+	case 0x18:
+	case 0x1c:
+	case 0x20:
+	case 0x40:
+	case 0x44:
+	case 0x48:
+	case 0x4c:
+		if (writeflag == MEM_WRITE && idata != 0) {
+			fatal("[ pvr_dma: TODO: unknown_0x%02x set to "
+			    "0x%08x ]\n", (int) relative_addr, (int) idata);
+			exit(1);
+		}
+		break;
+
+	case PVR_LMMODE0:	/*  0x84  */
+		if (writeflag == MEM_WRITE && idata != 0) {
+			fatal("[ pvr_dma: TODO: LMMODE0 set to "
+			    "0x%08x ]\n", (int) idata);
+			exit(1);
+		}
+		break;
+
+	case PVR_LMMODE1:	/*  0x88  */
+		if (writeflag == MEM_WRITE && idata != 0) {
+			fatal("[ pvr_dma: TODO: LMMODE1 set to "
+			    "0x%08x ]\n", (int) idata);
+			exit(1);
+		}
+		break;
+
+	case 0x8c:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ pvr_dma: write to 0x8c: TODO ]\n");
+			exit(1);
+		} else {
+			/*  0x20 means G2 DMA in progress?  */
+			/*  0x11 = mask which has to do with AICA  */
+			odata = 0x11 * (random() & 1);
+		}
+		break;
+
+	case 0x9c:
+		if (writeflag == MEM_WRITE && idata != 0) {
+			fatal("[ pvr_dma: TODO: unknown_0x%02x set to "
+			    "0x%08x ]\n", (int) relative_addr, (int) idata);
+			exit(1);
+		}
+		break;
+
+	case 0xa0:
+		if (writeflag == MEM_WRITE && idata != 0x80000000) {
+			fatal("[ pvr_dma: TODO: unknown_0x%02x set to "
+			    "0x%08x ]\n", (int) relative_addr, (int) idata);
+			exit(1);
+		}
+		break;
+
+	case 0xa4:
+	case 0xac:
+		if (writeflag == MEM_WRITE && idata != 0) {
+			fatal("[ pvr_dma: TODO: unknown_0x%02x set to "
+			    "0x%08x ]\n", (int) relative_addr, (int) idata);
+			exit(1);
+		}
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ pvr_dma: read from addr 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ pvr_dma: write to addr 0x%x: 0x%x ]\n",
+			    (int)relative_addr, (int)idata);
+		}
+
+		exit(1);
+	}
+
+	/*  Default write:  */
+	if (writeflag == MEM_WRITE)
+		d->dma_reg[relative_addr / sizeof(uint32_t)] = idata;
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(pvr_dma_more)
+{
+	struct pvr_data *d = (struct pvr_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  Default read:  */
+	if (writeflag == MEM_READ)
+		odata = d->dma_more_reg[relative_addr / sizeof(uint32_t)];
+
+	switch (relative_addr) {
+
+	case 0x00:	// 0x04ff0000
+	case 0x04:	// 0x0cff0000
+	case 0x08:	// 0x00000020
+	case 0x0c:	// 0x00000000
+	case 0x10:	// 0x00000000
+	case 0x80:	// 0x67027f00
+		break;
+
+	case 0x14:
+	case 0x18:
+		if (writeflag == MEM_WRITE && idata != 0)
+		{
+			fatal("PVR other DMA mode (?):\n");
+			fatal("0x00: %08x\n", d->dma_more_reg[0x00/4]);
+			fatal("0x04: %08x\n", d->dma_more_reg[0x04/4]);
+			fatal("0x08: %08x\n", d->dma_more_reg[0x08/4]);
+			fatal("0x0c: %08x\n", d->dma_more_reg[0x0c/4]);
+			fatal("0x10: %08x\n", d->dma_more_reg[0x10/4]);
+			fatal("0x14: %08x\n", d->dma_more_reg[0x14/4]);
+			exit(1);
+		}
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ pvr_dma_more: read from addr 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ pvr_dma_more: write to addr 0x%x: 0x%x ]\n",
+			    (int)relative_addr, (int)idata);
+		}
+
+		exit(1);
+	}
+
+	/*  Default write:  */
+	if (writeflag == MEM_WRITE)
+		d->dma_more_reg[relative_addr / sizeof(uint32_t)] = idata;
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  pvr_fb_invalidate():
+ */
+void pvr_fb_invalidate(struct pvr_data *d, int start, int stop)
+{
+	d->fb_update_x1 = d->fb_update_y1 = 0;
+	d->fb_update_x2 = d->xsize - 1;
+	d->fb_update_y2 = d->ysize - 1;
+}
+
+
+/*
+ *  pvr_vblank_timer_tick():
+ *
+ *  This function is called PVR_VBLANK_HZ times per real-world second. Its job
+ *  is to fake vertical retrace interrupts.
+ */     
+static void pvr_vblank_timer_tick(struct timer *t, void *extra)
+{
+	struct pvr_data *d = (struct pvr_data *) extra;
+	d->vblank_interrupts_pending ++;
+}
+
+
+/*
+ *  pvr_geometry_updated():
+ *
+ *  This function should be called every time a register is written to which
+ *  affects the framebuffer geometry (size, bit-depth, starting position, etc).
+ */
+void pvr_geometry_updated(struct pvr_data *d)
+{
+	int old_xsize = d->xsize, old_ysize = d->ysize, oldbpp = d->bytes_per_pixel;
+
+	/*  Make sure to redraw border on geometry changes.  */
+	d->border_updated = 1;
+
+	d->xsize = (REG(PVRREG_DIWSIZE) >> DIWSIZE_DPL_SHIFT) & DIWSIZE_MASK;
+	d->ysize = (REG(PVRREG_DIWSIZE) >> DIWSIZE_LPF_SHIFT) & DIWSIZE_MASK;
+
+	/*  E.g. 319x479  =>  320x480  */
+	d->xsize = (d->xsize + 1) * sizeof(uint32_t);
+	d->ysize ++;
+
+	switch (d->pixelmode) {
+	case 0:
+	case 1:	d->bytes_per_pixel = 2; break;
+	case 2:	d->bytes_per_pixel = 3; break;
+	case 3:	d->bytes_per_pixel = 4; break;
+	}
+
+	d->xsize /= d->bytes_per_pixel;
+
+	if (REG(PVRREG_DIWCONF) & DIWCONF_LR)
+		d->xsize /= 2;
+
+	if (d->line_double)
+		d->ysize /= 2;
+
+	{
+		int settingsChanged = d->xsize != old_xsize ||
+		    d->ysize != old_ysize ||
+		    d->bytes_per_pixel != oldbpp;
+
+		if (!settingsChanged)
+			return;
+	}
+
+	/*  Scrap Z buffer if we have one.  */
+	if (d->vram_z == NULL) {
+		free(d->vram_z);
+		d->vram_z = NULL;
+	}
+		
+	/*  Only show geometry debug message if output is enabled:  */
+	if (!d->video_enabled || !d->display_enabled)
+		return;
+
+	debug("[ pvr_geometry_updated: %i x %i, ", d->xsize, d->ysize);
+
+	switch (d->pixelmode) {
+	case 0: debug("RGB0555 (16-bit)"); break;
+	case 1: debug("RGB565 (16-bit)"); break;
+	case 2: debug("RGB888 (24-bit)"); break;
+	case 3: debug("RGB0888 (32-bit)"); break;
+	}
+
+	debug(" ]\n");
+}
+
+
+#ifdef DEBUG_RENDER_AS_WIRE_FRAME
+/*  Ugly quick-hack:  */
+static void line(struct pvr_data *d, int x1, int y1, int x2, int y2)
+{
+	int fb_base = REG(PVRREG_FB_RENDER_ADDR1);
+	int i;
+	for (i=0; i<256; i++) {
+		int px = (i * x2 + (256-i) * x1) >> 8;
+		int py = (i * y2 + (256-i) * y1) >> 8;
+		if (px > 0 && py > 0 && px < d->xsize && py < d->ysize) {
+			int ofs = fb_base + (px + py * d->xsize) *
+                            d->bytes_per_pixel;
+			d->vram[(ofs+0) % VRAM_SIZE] = 255;
+			d->vram[(ofs+1) % VRAM_SIZE] = 255;
+		}
+	}
+}
+#endif
+
+
+// Ugly quick-hack z-buffer line drawer, for triangles.
+// Assumes 16-bit color.
+static void simpleline(struct pvr_data *d, int y, double x1, double x2,
+	double z1, double z2, double r1, double r2, double g1, double g2,
+	double b1, double b2)
+{
+	if (y < 0 || y >= d->ysize || (x1 < 0 && x2 < 0)
+	     || (x1 >= d->xsize && x2 >= d->xsize))
+		return;
+
+	int fb_base = REG(PVRREG_FB_RENDER_ADDR1);
+	if (x1 > x2) {
+		double tmpf = x1; x1 = x2; x2 = tmpf;
+		tmpf = z1; z1 = z2; z2 = tmpf;
+		tmpf = r1; r1 = r2; r2 = tmpf;
+		tmpf = g1; g1 = g2; g2 = tmpf;
+		tmpf = b1; b1 = b2; b2 = tmpf;
+	}
+
+	// uint32_t fogDensity = REG(PVRREG_FOG_DENSITY);
+	// double scale_factor = 255.0;	// TODO: take fogDensity into account.
+	// uint32_t fogColor = REG(PVRREG_FOG_TABLE_COL);
+	// int fog_r = (fogColor >> 16) & 255;
+	// int fog_g = (fogColor >> 8) & 255;
+	// int fog_b = fogColor & 255;
+
+	double dz12 = (x2 - x1 != 0) ? ( (double)(z2 - z1) / (double)(x2 - x1) ) : 0;
+	double dr12 = (x2 - x1 != 0) ? ( (double)(r2 - r1) / (double)(x2 - x1) ) : 0;
+	double dg12 = (x2 - x1 != 0) ? ( (double)(g2 - g1) / (double)(x2 - x1) ) : 0;
+	double db12 = (x2 - x1 != 0) ? ( (double)(b2 - b1) / (double)(x2 - x1) ) : 0;
+	double z = z1, r = r1, g = g1, b = b1;
+	for (int x = x1; x <= x2; ++x) {
+		if (x > 0 && x < d->xsize) {
+			int ofs = x + y * d->xsize;
+			if (d->vram_z[ofs] <= z) {
+				d->vram_z[ofs] = z;
+
+				// z = 1/w
+				// int v = z * scale_factor;
+				// printf("z=%f v=%i\n", z, v);
+				// if (v < 0) v = 0;
+				// if (v > 255) v = 255;
+				// v >>= 1;
+
+				// int fogvalues = d->reg[PVRREG_FOG_TABLE  / sizeof(uint32_t) + v];
+				// printf("fogv = %04x\n", fogvalues);
+
+				// NOTE/TODO: Hardcoded for 565 pixelformat.
+				int ri = r, gi = g, bi = b;
+				// int a = (fogvalues >> 8) & 255;
+				// ri = ((fog_r * a) + (ri * (255 - a))) >> 8;
+				// gi = ((fog_g * a) + (gi * (255 - a))) >> 8;
+				// bi = ((fog_b * a) + (bi * (255 - a))) >> 8;
+
+				if (ri < 0) ri = 0;
+				if (ri > 255) ri = 255;
+				if (gi < 0) gi = 0;
+				if (gi > 255) gi = 255;
+				if (bi < 0) bi = 0;
+				if (bi > 255) bi = 255;
+				int color = ((ri >> 3) << 11) + ((gi >> 2) << 5) + (bi >> 3);
+
+				int fbofs = fb_base + ofs * d->bytes_per_pixel;
+				d->vram[(fbofs+0) % VRAM_SIZE] = color & 255;
+				d->vram[(fbofs+1) % VRAM_SIZE] = color >> 8;
+			}
+		}
+		
+		z += dz12; r += dr12; g += dg12; b += db12;
+	}
+}
+
+static void texturedline(struct pvr_data *d,
+	int texture_pixelformat, int twiddled, int stride,
+	int texture, int texture_xsize, int texture_ysize,
+	int y, int x1, int x2, double z1, double z2,
+	double u1, double u2, double v1, double v2)
+{
+	if (y < 0 || y >= d->ysize || (x1 < 0 && x2 < 0)
+	     || (x1 >= d->xsize && x2 >= d->xsize))
+		return;
+
+	int fb_base = REG(PVRREG_FB_RENDER_ADDR1);
+	if (x1 > x2) {
+		int tmp = x1; x1 = x2; x2 = tmp;
+		double tmpf = z1; z1 = z2; z2 = tmpf;
+		tmpf = u1; u1 = u2; u2 = tmpf;
+		tmpf = v1; v1 = v2; v2 = tmpf;
+	}
+
+	int bytesperpixel = 2;
+
+	switch (texture_pixelformat)
+	{
+	case 0:	// ARGB1555
+	case 1:	// RGB565
+	case 2: // ARGB4444
+		bytesperpixel = 2;
+		break;
+	case 6:	// 8-bit palette
+		bytesperpixel = 1;
+		break;
+	default:
+		// TODO
+		break;
+	}
+
+	int palette_cfg = d->reg[PVRREG_PALETTE_CFG / sizeof(uint32_t)] & PVR_PALETTE_CFG_MODE_MASK;
+
+	double dz12 = (x2 - x1 != 0) ? ( (double)(z2 - z1) / (double)(x2 - x1) ) : 0;
+	double du12 = (x2 - x1 != 0) ? ( (double)(u2 - u1) / (double)(x2 - x1) ) : 0;
+	double dv12 = (x2 - x1 != 0) ? ( (double)(v2 - v1) / (double)(x2 - x1) ) : 0;
+
+	double z = z1, u = u1, v = v1;
+
+	for (int x = x1; x <= x2; ++x) {
+		if (x > 0 && x < d->xsize) {
+			int ofs = x + y * d->xsize;
+			if (d->vram_z[ofs] <= z) {
+				d->vram_z[ofs] = z;
+
+				int fbofs = fb_base + ofs * d->bytes_per_pixel;
+
+				// Get color from texture:
+				int texturex = u * texture_xsize;
+				texturex &= (texture_xsize-1);
+				int texturey = v * texture_ysize;
+				texturey &= (texture_ysize-1);
+
+				int textureofs;
+				if (twiddled) {
+					texturex = 
+					(texturex&1)|((texturex&2)<<1)|((texturex&4)<<2)|((texturex&8)<<3)|((texturex&16)<<4)|
+					      ((texturex&32)<<5)|((texturex&64)<<6)|((texturex&128)<<7)|((texturex&256)<<8)|((texturex&512)<<9);
+					texturey = 
+					(texturey&1)|((texturey&2)<<1)|((texturey&4)<<2)|((texturey&8)<<3)|((texturey&16)<<4)|
+					      ((texturey&32)<<5)|((texturey&64)<<6)|((texturey&128)<<7)|((texturey&256)<<8)|((texturey&512)<<9);
+					textureofs = texturex * 2 + texturey;
+				} else {
+					if (stride > 0)
+						textureofs = texturex + texturey * stride;
+					else
+						textureofs = texturex + texturey * texture_xsize;
+				}
+
+				textureofs *= bytesperpixel;	// 2 bytes per pixel.
+
+				int addr = texture + textureofs;
+				addr = ((addr & 4) << 20) | (addr & 3) | ((addr & 0x7ffff8) >> 1);
+
+				int a = 255, r = 64, g = 64, b = 64;
+				switch (texture_pixelformat)
+				{
+				case 0:	// ARGB1555:
+					{
+						int color = d->vram[addr] + (d->vram[addr+1] << 8);
+						a = (color >> 15) & 0x1 ? 255 : 0;
+						r = (color >> 10) & 0x1f;
+						g = ((color >> 5) & 0x1f) << 1;
+						b = (color) & 0x1f;
+					}
+					break;
+				case 1:	// RGB565:
+					{
+						int color = d->vram[addr] + (d->vram[addr+1] << 8);
+						r = (color >> 11) & 0x1f;
+						g = (color >> 5) & 0x3f;
+						b = (color) & 0x1f;
+					}
+					break;
+				case 2:	// ARGB4444:
+					{
+						int color = d->vram[addr] + (d->vram[addr+1] << 8);
+						a = ((color >> 12) & 15) * 0x11;
+						r = ((color >> 8) & 15) << 1;
+						g = ((color >> 4) & 15) << 2;
+						b = ((color) & 15) << 1;
+					}
+					break;
+				case 6:
+					{
+						// TODO: multiple palette banks? Endianness?
+						int index8bpp = d->vram[addr];
+						char* base = (char*)&d->reg[PVRREG_PALETTE / sizeof(uint32_t)];
+						uint16_t c16 = *((uint16_t*)(void*)base + index8bpp);
+						uint16_t c32 = *((uint32_t*)(void*)base + index8bpp);
+						switch (palette_cfg) {
+						case PVR_PALETTE_CFG_MODE_ARGB1555:
+							a = (c16 >> 15) & 0x1 ? 255 : 0;
+							r = (c16 >> 10) & 0x1f;
+							g = ((c16 >> 5) & 0x1f) << 1;
+							b = (c16) & 0x1f;
+							break;
+						case PVR_PALETTE_CFG_MODE_RGB565:
+							r = (c16 >> 11) & 0x1f;
+							g = (c16 >> 5) & 0x3f;
+							b = (c16) & 0x1f;
+							break;
+						case PVR_PALETTE_CFG_MODE_ARGB4444:
+							a = ((c16 >> 12) & 15) * 0x11;
+							r = ((c16 >> 8) & 15) << 1;
+							g = ((c16 >> 4) & 15) << 2;
+							b = ((c16) & 15) << 1;
+							break;
+						case PVR_PALETTE_CFG_MODE_ARGB8888:
+							a = (c32 >> 24) & 255;
+							r = ((c32 >> 16) & 255) >> 3;
+							g = ((c32 >> 8) & 255) >> 2;
+							b = ((c32) & 255) >> 3;
+							break;
+						}
+					}
+					break;
+				default:
+					fatal("pvr: unimplemented texture_pixelformat %i\n", texture_pixelformat);
+					exit(1);
+				}
+
+				if (a == 255)
+				{
+					// Output as RGB565:
+					// TODO: Support other formats.
+					int color = (r << 11) + (g << 5) + (b);
+					d->vram[(fbofs+0) % VRAM_SIZE] = color & 255;
+					d->vram[(fbofs+1) % VRAM_SIZE] = color >> 8;
+				} else if (a > 0) {
+					int oldcolor = d->vram[(fbofs+0) % VRAM_SIZE];
+					oldcolor += (d->vram[(fbofs+1) % VRAM_SIZE] << 8);
+					int oldr = (oldcolor >> 11) & 0x1f;
+					int oldg = (oldcolor >> 5) & 0x3f;
+					int oldb = (oldcolor) & 0x1f;
+					r = (a * r + oldr * (255 - a)) / 255;
+					g = (a * g + oldg * (255 - a)) / 255;
+					b = (a * b + oldb * (255 - a)) / 255;
+					int color = (r << 11) + (g << 5) + (b);
+					d->vram[(fbofs+0) % VRAM_SIZE] = color & 255;
+					d->vram[(fbofs+1) % VRAM_SIZE] = color >> 8;
+				}
+			}
+		}
+		
+		z += dz12;
+		u += du12;
+		v += dv12;
+	}
+}
+
+
+// Slow software rendering, for debugging:
+static void pvr_render_triangle(struct pvr_data *d,
+	int x1, int y1, double z1, int r1, int g1, int b1,
+	int x2, int y2, double z2, int r2, int g2, int b2,
+	int x3, int y3, double z3, int r3, int g3, int b3)
+{
+	// Easiest if 1, 2, 3 are in order top to bottom.
+	if (y2 < y1) {
+		int tmp = x1; x1 = x2; x2 = tmp;
+		tmp = y1; y1 = y2; y2 = tmp;
+		tmp = r1; r1 = r2; r2 = tmp;
+		tmp = g1; g1 = g2; g2 = tmp;
+		tmp = b1; b1 = b2; b2 = tmp;
+		double tmpf = z1; z1 = z2; z2 = tmpf;
+	}
+
+	if (y3 < y1) {
+		int tmp = x1; x1 = x3; x3 = tmp;
+		tmp = y1; y1 = y3; y3 = tmp;
+		tmp = r1; r1 = r3; r3 = tmp;
+		tmp = g1; g1 = g3; g3 = tmp;
+		tmp = b1; b1 = b3; b3 = tmp;
+		double tmpf = z1; z1 = z3; z3 = tmpf;
+	}
+
+	if (y3 < y2) {
+		int tmp = x2; x2 = x3; x3 = tmp;
+		tmp = y2; y2 = y3; y3 = tmp;
+		tmp = r2; r2 = r3; r3 = tmp;
+		tmp = g2; g2 = g3; g3 = tmp;
+		tmp = b2; b2 = b3; b3 = tmp;
+		double tmpf = z2; z2 = z3; z3 = tmpf;
+	}
+
+	if (y3 < 0 || y1 >= d->ysize)
+		return;
+
+	double dx12 = (y2-y1 != 0) ? ( (x2 - x1) / (double)(y2 - y1) ) : 0.0;
+	double dx13 = (y3-y1 != 0) ? ( (x3 - x1) / (double)(y3 - y1) ) : 0.0;
+	double dx23 = (y3-y2 != 0) ? ( (x3 - x2) / (double)(y3 - y2) ) : 0.0;
+
+	double dz12 = (y2-y1 != 0) ? ( (z2 - z1) / (double)(y2 - y1) ) : 0.0;
+	double dz13 = (y3-y1 != 0) ? ( (z3 - z1) / (double)(y3 - y1) ) : 0.0;
+	double dz23 = (y3-y2 != 0) ? ( (z3 - z2) / (double)(y3 - y2) ) : 0.0;
+
+	double dr12 = (y2-y1 != 0) ? ( (r2 - r1) / (double)(y2 - y1) ) : 0.0;
+	double dr13 = (y3-y1 != 0) ? ( (r3 - r1) / (double)(y3 - y1) ) : 0.0;
+	double dr23 = (y3-y2 != 0) ? ( (r3 - r2) / (double)(y3 - y2) ) : 0.0;
+
+	double dg12 = (y2-y1 != 0) ? ( (g2 - g1) / (double)(y2 - y1) ) : 0.0;
+	double dg13 = (y3-y1 != 0) ? ( (g3 - g1) / (double)(y3 - y1) ) : 0.0;
+	double dg23 = (y3-y2 != 0) ? ( (g3 - g2) / (double)(y3 - y2) ) : 0.0;
+
+	double db12 = (y2-y1 != 0) ? ( (b2 - b1) / (double)(y2 - y1) ) : 0.0;
+	double db13 = (y3-y1 != 0) ? ( (b3 - b1) / (double)(y3 - y1) ) : 0.0;
+	double db23 = (y3-y2 != 0) ? ( (b3 - b2) / (double)(y3 - y2) ) : 0.0;
+
+	double startx = x1, startz = z1, startr = r1, startg = g1, startb = b1;
+	double stopx = x1, stopz = z1, stopr = r1, stopg = g1, stopb = b1;
+	for (int y = y1; y < y2; ++y)
+	{
+		simpleline(d, y, startx, stopx, startz, stopz, startr, stopr, startg, stopg, startb, stopb);
+		startx += dx13; startz += dz13; startr += dr13; startg += dg13; startb += db13;
+		stopx += dx12; stopz += dz12; stopr += dr12; stopg += dg12; stopb += db12;
+	}
+
+	stopx = x2; stopz = z2; stopr = r2; stopg = g2; stopb = b2;
+	for (int y = y2; y < y3; ++y)
+	{
+		simpleline(d, y, startx, stopx, startz, stopz, startr, stopr, startg, stopg, startb, stopb);
+		startx += dx13; startz += dz13; startr += dr13; startg += dg13; startb += db13;
+		stopx += dx23; stopz += dz23; stopr += dr23; stopg += dg23; stopb += db23;
+	}
+
+#ifdef DEBUG_RENDER_AS_WIRE_FRAME
+	// Wire-frame test:
+	line(d, x1, y1, x2, y2);
+	line(d, x1, y1, x3, y3);
+	line(d, x2, y2, x3, y3);
+#endif
+}
+
+
+// Slow software rendering, for debugging:
+static void pvr_render_triangle_textured(struct pvr_data *d,
+	int texture_pixelformat, int twiddled, int stride,
+	int texture, int texture_xsize, int texture_ysize,
+	int x1, int y1, double z1, double u1, double v1,
+	int x2, int y2, double z2, double u2, double v2,
+	int x3, int y3, double z3, double u3, double v3)
+{
+	// Easiest if 1, 2, 3 are in order top to bottom.
+	if (y2 < y1) {
+		int tmp = x1; x1 = x2; x2 = tmp;
+		tmp = y1; y1 = y2; y2 = tmp;
+		double tmpf = z1; z1 = z2; z2 = tmpf;
+		tmpf = u1; u1 = u2; u2 = tmpf;
+		tmpf = v1; v1 = v2; v2 = tmpf;
+	}
+
+	if (y3 < y1) {
+		int tmp = x1; x1 = x3; x3 = tmp;
+		tmp = y1; y1 = y3; y3 = tmp;
+		double tmpf = z1; z1 = z3; z3 = tmpf;
+		tmpf = u1; u1 = u3; u3 = tmpf;
+		tmpf = v1; v1 = v3; v3 = tmpf;
+	}
+
+	if (y3 < y2) {
+		int tmp = x2; x2 = x3; x3 = tmp;
+		tmp = y2; y2 = y3; y3 = tmp;
+		double tmpf = z2; z2 = z3; z3 = tmpf;
+		tmpf = u2; u2 = u3; u3 = tmpf;
+		tmpf = v2; v2 = v3; v3 = tmpf;
+	}
+
+	if (y3 < 0 || y1 >= d->ysize)
+		return;
+
+	double dx12 = (y2-y1 != 0) ? ( (x2 - x1) / (double)(y2 - y1) ) : 0.0;
+	double dx13 = (y3-y1 != 0) ? ( (x3 - x1) / (double)(y3 - y1) ) : 0.0;
+	double dx23 = (y3-y2 != 0) ? ( (x3 - x2) / (double)(y3 - y2) ) : 0.0;
+
+	double dz12 = (y2-y1 != 0) ? ( (z2 - z1) / (double)(y2 - y1) ) : 0.0;
+	double dz13 = (y3-y1 != 0) ? ( (z3 - z1) / (double)(y3 - y1) ) : 0.0;
+	double dz23 = (y3-y2 != 0) ? ( (z3 - z2) / (double)(y3 - y2) ) : 0.0;
+
+	double du12 = (y2-y1 != 0) ? ( (u2 - u1) / (double)(y2 - y1) ) : 0.0;
+	double du13 = (y3-y1 != 0) ? ( (u3 - u1) / (double)(y3 - y1) ) : 0.0;
+	double du23 = (y3-y2 != 0) ? ( (u3 - u2) / (double)(y3 - y2) ) : 0.0;
+
+	double dv12 = (y2-y1 != 0) ? ( (v2 - v1) / (double)(y2 - y1) ) : 0.0;
+	double dv13 = (y3-y1 != 0) ? ( (v3 - v1) / (double)(y3 - y1) ) : 0.0;
+	double dv23 = (y3-y2 != 0) ? ( (v3 - v2) / (double)(y3 - y2) ) : 0.0;
+
+	double startx = x1, startz = z1, startu = u1, startv = v1;
+	double stopx = x1, stopz = z1, stopu = u1, stopv = v1;
+
+	for (int y = y1; y < y2; ++y)
+	{
+		texturedline(d, texture_pixelformat, twiddled, stride, texture, texture_xsize, texture_ysize, y, startx, stopx, startz, stopz, startu, stopu, startv, stopv);
+		startx += dx13; startz += dz13; startu += du13; startv += dv13;
+		stopx += dx12; stopz += dz12; stopu += du12; stopv += dv12;
+	}
+
+	stopx = x2; stopz = z2; stopu = u2; stopv = v2;
+	for (int y = y2; y < y3; ++y)
+	{
+		texturedline(d, texture_pixelformat, twiddled, stride, texture, texture_xsize, texture_ysize, y, startx, stopx, startz, stopz, startu, stopu, startv, stopv);
+		startx += dx13; startz += dz13; startu += du13; startv += dv13;
+		stopx += dx23; stopz += dz23; stopu += du23; stopv += dv23;
+	}
+
+#ifdef DEBUG_RENDER_AS_WIRE_FRAME
+	// Wire-frame test:
+	line(d, x1, y1, x2, y2);
+	line(d, x1, y1, x3, y3);
+	line(d, x2, y2, x3, y3);
+#endif
+}
+
+
+static void pvr_clear_ta_commands(struct pvr_data* d)
+{
+	d->n_ta_commands = 0;
+}
+
+
+/*
+ *  pvr_render():
+ *
+ *  Render from the Object Buffer to the framebuffer.
+ *
+ *  TODO: This function is totally bogus so far, the format of the Object
+ *        Buffer is just a quick made-up hack to see if it works at all.
+ */
+void pvr_render(struct cpu *cpu, struct pvr_data *d)
+{
+	int fb_render_cfg = REG(PVRREG_FB_RENDER_CFG);
+	int fb_base = REG(PVRREG_FB_RENDER_ADDR1);
+
+	if ((fb_render_cfg & FB_RENDER_CFG_RENDER_MODE_MASK) != 0x1) {
+		printf("pvr: only RGB565 rendering has been implemented\n");
+		exit(1);
+	}
+
+	// Settings for the current polygon being rendered:
+	// Word 0:
+	int listtype = 0;
+	int striplength = 0;
+	int clipmode;
+	int modifier;
+	int modifier_mode;
+	int color_type = 0;
+	int texture = 0;
+	int specular;
+	int shading;
+	int uv_format;
+
+	// Word 1:
+	int depthmode;
+	int cullingmode = 0;
+	int zwrite;
+	int texture1;
+	int specular1;
+	int shading1;
+	int uv_format1;
+	int dcalcexact;
+
+	// Word 2:
+	int fog = 0;
+	int texture_usize = 0, texture_vsize = 0;
+
+	// Word 3:
+	int texture_mipmap = 0;
+	int texture_vq_compression = 0;
+	int texture_pixelformat = 0;
+	int texture_twiddled = 0;
+	int texture_stride = 0;
+	uint32_t textureAddr = 0;
+
+	int vertex_index = 0;
+	int wf_x[4], wf_y[4]; double wf_z[4], wf_u[4], wf_v[4];
+	int wf_r[4], wf_g[4], wf_b[4];
+
+	double baseRed = 0.0, baseGreen = 0.0, baseBlue = 0.0;
+
+	debug("[ pvr_render: rendering to FB offset 0x%x, "
+	    "%i Tile Accelerator commands ]\n", fb_base, d->n_ta_commands);
+
+	/*
+	 *  Clear all pixels first.
+	 *  TODO: Maybe only clear the specific tiles that are in use by
+	 *  the tile accelerator?
+	 *  TODO: What background color to use? See KOS' pvr_misc.c for
+	 *  how KOS sets the background.
+	 */
+	memset(d->vram + fb_base, 0x00, d->xsize * d->ysize * d->bytes_per_pixel);
+
+	/*  Clear Z as well:  */
+	if (d->vram_z == NULL) {
+		d->vram_z = (double*) malloc(sizeof(double) * d->xsize * d->ysize);
+	}
+
+	uint32_t bgplaneZ = REG(PVRREG_BGPLANE_Z);
+	struct ieee_float_value backgroundz;
+	ieee_interpret_float_value(bgplaneZ, &backgroundz, IEEE_FMT_S);
+	for (int q = 0; q < d->xsize * d->ysize; ++q)
+		d->vram_z[q] = backgroundz.f;
+
+	// Using names from http://www.ludd.luth.se/~jlo/dc/ta-intro.txt.
+	for (size_t index = 0; index < d->n_ta_commands; ++index) {
+		// list points to 8 or 16 words.
+		uint32_t* list = &d->ta_commands[index * 16];
+		int cmd = (list[0] >> 29) & 7;
+
+		switch (cmd)
+		{
+		case 0:	// END_OF_LIST
+			// Interrupt event already triggered in pvr_ta_command().
+			if (ta_debug)
+				fatal("\nTA end_of_list (list type %i)\n", d->current_list_type);
+			break;
+
+		case 1:	// USER_CLIP
+			// TODO: Ignoring for now.
+			break;
+
+		case 4:	// polygon or modifier volume
+		{
+			vertex_index = 0;
+
+			// List Word 0:
+			listtype = (list[0] >> 24) & 7;
+			striplength = (list[0] >> 18) & 3;
+			striplength = striplength == 2 ? 4 : (
+			    striplength == 3 ? 6 : (striplength + 1));
+			clipmode = (list[0] >> 16) & 3;
+			modifier = (list[0] >> 7) & 1;
+			modifier_mode = (list[0] >> 6) & 1;
+			color_type = (list[0] >> 4) & 3;
+			texture = list[0] & 8;
+			specular = list[0] & 4;
+			shading = list[0] & 2;
+			uv_format = list[0] & 1;
+
+			if (ta_debug) {
+				fatal("\nTA polygon  listtype %i, ", listtype);
+				fatal("striplength %i, ", striplength);
+				fatal("clipmode %i, ", clipmode);
+				fatal("modifier %i, ", modifier);
+				fatal("modifier_mode %i,\n", modifier_mode);
+				fatal("            color_type %i, ", color_type);
+				fatal("texture %s, ", texture ? "TRUE" : "false");
+				fatal("specular %s, ", specular ? "TRUE" : "false");
+				fatal("shading %s, ", shading ? "TRUE" : "false");
+				fatal("uv_format %s\n", uv_format ? "TRUE" : "false");
+			}
+
+			// List Word 1:
+			depthmode = (list[1] >> 29) & 7;
+			cullingmode = (list[1] >> 27) & 3;
+			zwrite = ! ((list[1] >> 26) & 1);
+			texture1 = (list[1] >> 25) & 1;
+			specular1 = (list[1] >> 24) & 1;
+			shading1 = (list[1] >> 23) & 1;
+			uv_format1 = (list[1] >> 22) & 1;
+			dcalcexact = (list[1] >> 20) & 1;
+
+			if (ta_debug) {
+				fatal("            depthmode %i, ", depthmode);
+				fatal("cullingmode %i, ", cullingmode);
+				fatal("zwrite %s, ", zwrite ? "TRUE" : "false");
+				fatal("texture1 %s\n", texture1 ? "TRUE" : "false");
+				fatal("            specular1 %s, ", specular1 ? "TRUE" : "false");
+				fatal("shading1 %s, ", shading1 ? "TRUE" : "false");
+				fatal("uv_format1 %s, ", uv_format1 ? "TRUE" : "false");
+				fatal("dcalcexact %s\n", dcalcexact ? "TRUE" : "false");
+			}
+
+			if (!zwrite) {
+				fatal("pvr: no zwrite? not implemented yet.\n");
+				exit(1);
+			}
+
+			// For now, trust texture and ignore texture1.
+			// if (texture != texture1) {
+			//	fatal("pvr: texture != texture1. what to do?\n");
+			//	exit(1);
+			// }
+
+			// List Word 2:
+			// TODO: srcblend (31-29)
+			// TODO: dstblend (28-26)
+			// TODO: srcmode (25)
+			// TODO: dstmode (24)
+			fog = (list[2] >> 22) & 3;
+			// TODO: clamp (21)
+			// TODO: alpha (20)
+			// TODO: texture alpha (19)
+			// TODO: uv flip (18-17)
+			// TODO: uv clamp (16-15)
+			// TODO: filter (14-12)
+			// TODO: mipmap (11-8)
+			// TODO: texture shading (7-6)
+			texture_usize = 8 << ((list[2] >> 3) & 7);
+			texture_vsize = 8 << (list[2] & 7);
+
+			// List Word 3:
+			texture_mipmap = (list[3] >> 31) & 1;
+			texture_vq_compression = (list[3] >> 30) & 1;
+			texture_pixelformat = (list[3] >> 27) & 7;
+			texture_twiddled = ! ((list[3] >> 26) & 1);
+			texture_stride = (list[3] >> 25) & 1;
+			textureAddr = (list[3] << 3) & 0x7fffff;
+
+			if (ta_debug) {
+				fatal("            texture: mipmap %s, ", texture_mipmap ? "TRUE" : "false");
+				fatal("vq_compression %s, ", texture_vq_compression ? "TRUE" : "false");
+				fatal("pixelformat %i, ", texture_pixelformat);
+				fatal("twiddled %s\n", texture_twiddled ? "TRUE" : "false");
+				fatal("            stride %s, ", texture_stride ? "TRUE" : "false");
+				fatal("textureAddr 0x%08x\n", textureAddr);
+			}
+
+			if (fog != 2)
+				fatal("[ pvr: fog type %i not yet implemented ]\n", fog);
+
+			if (texture_vq_compression) {
+				fatal("pvr: texture_vq_compression not supported yet\n");
+				// exit(1);
+			}
+
+			struct ieee_float_value r, g, b;
+			ieee_interpret_float_value(list[5], &r, IEEE_FMT_S);
+			ieee_interpret_float_value(list[6], &g, IEEE_FMT_S);
+			ieee_interpret_float_value(list[7], &b, IEEE_FMT_S);
+			baseRed = r.f * 255;
+			baseGreen = g.f * 255;
+			baseBlue = b.f * 255;
+			// printf("rgb = %f %f %f\n", r.f, g.f, b.f);
+			break;
+		}
+
+		case 7:	// vertex
+		{
+			// MAJOR TODO:
+			// How to select which one of the 18 (!) types listed
+			// in http://www.ludd.luth.se/~jlo/dc/ta-intro.txt to
+			// use?
+			if (listtype != 0 && listtype != 2 && listtype != 4)
+				break;
+
+			int eos = (list[0] >> 28) & 1;
+
+			struct ieee_float_value fx, fy, fz, u, v, extra1, extra2;
+			ieee_interpret_float_value(list[1], &fx, IEEE_FMT_S);
+			ieee_interpret_float_value(list[2], &fy, IEEE_FMT_S);
+			ieee_interpret_float_value(list[3], &fz, IEEE_FMT_S);
+			wf_x[vertex_index] = fx.f;
+			wf_y[vertex_index] = fy.f;
+			wf_z[vertex_index] = fz.f;
+
+			if (ta_debug)
+				fatal("TA vertex   %f %f %f%s\n", fx.f, fy.f, fz.f, eos ? " end_of_strip" : "");
+
+			if (texture) {
+				ieee_interpret_float_value(list[4], &u, IEEE_FMT_S);
+				ieee_interpret_float_value(list[5], &v, IEEE_FMT_S);
+				wf_u[vertex_index] = u.f;
+				wf_v[vertex_index] = v.f;
+			} else {
+				if (color_type == 0) {
+					wf_r[vertex_index] = (list[6] >> 16) & 255;
+					wf_g[vertex_index] = (list[6] >> 8) & 255;
+					wf_b[vertex_index] = (list[6]) & 255;
+				} else if (color_type == 1) {
+					ieee_interpret_float_value(list[5], &v, IEEE_FMT_S);
+					ieee_interpret_float_value(list[6], &extra1, IEEE_FMT_S);
+					ieee_interpret_float_value(list[7], &extra2, IEEE_FMT_S);
+					wf_r[vertex_index] = v.f * 255;
+					wf_g[vertex_index] = extra1.f * 255;
+					wf_b[vertex_index] = extra2.f * 255;
+				} else if (color_type == 2) {
+					ieee_interpret_float_value(list[6], &extra1, IEEE_FMT_S);
+					wf_r[vertex_index] = extra1.f * baseRed;
+					wf_g[vertex_index] = extra1.f * baseGreen;
+					wf_b[vertex_index] = extra1.f * baseBlue;
+				} else {
+					// "Intensity from previous face". TODO. Red for now.
+					wf_r[vertex_index] = 255;
+					wf_g[vertex_index] = 0;
+					wf_b[vertex_index] = 0;
+				}
+			}
+
+			vertex_index ++;
+
+			if (vertex_index >= 3) {
+				int modulo_mask = REG(PVRREG_TSP_CFG) & TSP_CFG_MODULO_MASK;
+
+				float crossProduct =
+					((wf_x[1] - wf_x[0])*(wf_y[2] - wf_y[0])) -
+					((wf_y[1] - wf_y[0])*(wf_x[2] - wf_x[0]));
+
+				// Hm. TODO: Instead of flipping back and forth between
+				// clockwise and counter-clockwise culling, perhaps there
+				// is some smarter way of assigning the three points
+				// instead of 012 => 12x...?
+				int culled = 0;
+				if (cullingmode == 2) {
+					if (crossProduct < 0)
+						culled = 1;
+					cullingmode = 3;
+				} else if (cullingmode == 3) {
+					if (crossProduct > 0)
+						culled = 1;
+					cullingmode = 2;
+				}
+
+				if (!culled) {
+					if (texture)
+						pvr_render_triangle_textured(d,
+						    texture_pixelformat, texture_twiddled, texture_stride ? (32*modulo_mask) : 0,
+						    textureAddr, texture_usize, texture_vsize,
+						    wf_x[0], wf_y[0], wf_z[0], wf_u[0], wf_v[0],
+						    wf_x[1], wf_y[1], wf_z[1], wf_u[1], wf_v[1],
+						    wf_x[2], wf_y[2], wf_z[2], wf_u[2], wf_v[2]);
+					else
+						pvr_render_triangle(d,
+						    wf_x[0], wf_y[0], wf_z[0], wf_r[0], wf_g[0], wf_b[0],
+						    wf_x[1], wf_y[1], wf_z[1], wf_r[1], wf_g[1], wf_b[1],
+						    wf_x[2], wf_y[2], wf_z[2], wf_r[2], wf_g[2], wf_b[2]);
+				}
+
+				if (eos) {
+					// End of strip.
+					vertex_index = 0;
+				} else {
+					// Not a closing vertex, then move points 1 and 2
+					// into slots 0 and 1, so that the stripe can continue.
+					vertex_index = 2;
+					wf_x[0] = wf_x[1]; wf_y[0] = wf_y[1]; wf_z[0] = wf_z[1];
+					wf_u[0] = wf_u[1]; wf_v[0] = wf_v[1];
+					wf_r[0] = wf_r[1]; wf_g[0] = wf_g[1]; wf_b[0] = wf_b[1];
+					
+					wf_x[1] = wf_x[2]; wf_y[1] = wf_y[2]; wf_z[1] = wf_z[2];
+					wf_u[1] = wf_u[2]; wf_v[1] = wf_v[2];
+					wf_r[1] = wf_r[2]; wf_g[1] = wf_g[2]; wf_b[1] = wf_b[2];
+				}
+			}
+			break;
+		}
+
+		default:
+			fatal("pvr_render: unimplemented list cmd %i\n", cmd);
+			exit(1);
+		}
+	}
+
+	pvr_clear_ta_commands(d);
+	
+	// TODO: RENDERDONE is 2. How about other events?
+	SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_RENDERDONE);
+}
+
+
+/*
+ *  pvr_reset_ta():
+ *
+ *  Reset the Tile Accelerator.
+ */
+static void pvr_reset_ta(struct pvr_data *d)
+{
+	REG(PVRREG_DIWCONF) = DIWCONF_MAGIC;
+	pvr_clear_ta_commands(d);
+}
+
+
+/*
+ *  pvr_reset():
+ *
+ *  Reset the PVR.
+ */
+static void pvr_reset(struct pvr_data *d)
+{
+	/*  TODO  */
+}
+
+
+/*
+ *  pvr_ta_init():
+ *
+ *  Initialize the Tile Accelerator. This makes the TA ready to receive
+ *  commands (via address 0x10000000).
+ */
+void pvr_ta_init(struct cpu *cpu, struct pvr_data *d)
+{
+	REG(PVRREG_TA_OPB_POS) = REG(PVRREG_TA_OPB_START);
+	REG(PVRREG_TA_OB_POS) = REG(PVRREG_TA_OB_START);
+}
+
+
+static void pvr_tilebuf_debugdump(struct pvr_data *d)
+{
+	return;
+
+	// According to Marcus Comstedt's "tatest":
+	// 24 word header (before the TILEBUF_ADDR pointer), followed by
+	// 6 words for each tile.
+	uint32_t tilebuf = REG(PVRREG_TILEBUF_ADDR) & PVR_TILEBUF_ADDR_MASK;
+
+	// TODO: endianness
+	uint32_t *p = (uint32_t*) (d->vram + tilebuf);
+
+	fatal("PVR tile buffer debug dump:\n");
+	p -= 24;
+	for (int i = 0; i < 24; ++i)
+		fatal("  %08x", *p++);
+
+	fatal("\n%i x %i tiles:\n", d->tilebuf_xsize, d->tilebuf_ysize);
+
+	for (int x = 0; x < d->tilebuf_xsize; ++x)
+	{
+		for (int y = 0; y < d->tilebuf_ysize; ++y)
+		{
+			fatal("  Tile %i,%i:", x, y);
+			for (int i = 0; i < 6; ++i)
+				fatal(" %08x", *p++);
+			fatal("\n");
+		}
+	}
+}
+
+
+/*
+ *  pvr_ta_command():
+ *
+ *  Someone has written a [complete] 32-byte or 64-byte command to the Tile
+ *  Accelerator memory area. The real hardware probably outputs
+ *  "compiled commands" into the Object list and Object Pointer list.
+ *  For now, just put all the commands in a plain array, and then later execute
+ *  them in pvr_render().
+ */
+static void pvr_ta_command(struct cpu *cpu, struct pvr_data *d, int list_ofs)
+{
+	uint32_t *ta = &d->ta[list_ofs];
+
+	/*  Dump the Tile Accelerator command for debugging:  */
+	if (ta_debug) {
+		fatal("TA cmd:");
+		for (int i = 0; i < 8; ++i)
+			fatal(" %08x", (int) ta[i]);
+		fatal("\n");
+	}
+
+	// ob_ofs = REG(PVRREG_TA_OB_POS);
+	// REG(PVRREG_TA_OB_POS) = ob_ofs + sizeof(uint64_t);
+
+	if (d->ta_commands == NULL) {
+		d->allocated_ta_commands = 2048;
+		d->ta_commands = (uint32_t *) malloc(64 * d->allocated_ta_commands);
+		d->n_ta_commands = 0;
+	}
+
+	if (d->n_ta_commands + 1 >= d->allocated_ta_commands) {
+		d->allocated_ta_commands *= 2;
+		d->ta_commands = (uint32_t *) realloc(d->ta_commands, 64 * d->allocated_ta_commands);
+	}
+
+	// Hack: I don't understand yet what separates a 32-byte transfer
+	// vs two individual 32-byte transfers vs a 64-byte transfer.
+	// TODO: For now, really only support 32-byte transfers... :(
+	memcpy(d->ta_commands + 16 * d->n_ta_commands, ta, 32);
+	memset(d->ta_commands + 16 * d->n_ta_commands + 8, 0, 32);
+	d->n_ta_commands ++;
+
+	// We need to keep track of the current list type though, and respond
+	// with an event once we reach an end_of_list command. All other
+	// commands are handled in pvr_render() for now.
+	int cmd = (ta[0] >> 29) & 7;
+	if (cmd == 0) {
+		// cmd 0: end of list
+		uint32_t opb_cfg = REG(PVRREG_TA_OPB_CFG);
+
+		if (d->current_list_type == 0 && opb_cfg & TA_OPB_CFG_OPAQUEPOLY_MASK)
+			SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_OPAQUEDONE);
+		if (d->current_list_type == 1 && opb_cfg & TA_OPB_CFG_OPAQUEMOD_MASK)
+			SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_OPAQUEMODDONE);
+		if (d->current_list_type == 2 && opb_cfg & TA_OPB_CFG_TRANSPOLY_MASK)
+			SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_TRANSDONE);
+		if (d->current_list_type == 3 && opb_cfg & TA_OPB_CFG_TRANSMOD_MASK)
+			SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_TRANSMODDONE);
+		if (d->current_list_type == 4 && opb_cfg & TA_OPB_CFG_PUNCHTHROUGH_MASK)
+			SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_PVR_PTDONE);
+	} else if (cmd == 4) {
+		// cmd 4: polygon or modifier volume
+		d->current_list_type = (ta[0] >> 24) & 7;
+	}
+}
+
+
+DEVICE_ACCESS(pvr_ta)
+{
+	struct pvr_data *d = (struct pvr_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (len != sizeof(uint32_t)) {
+		fatal("pvr_ta access len = %i: TODO\n", (int) len);
+		exit(1);
+	}
+
+	// Tile Accelerator commands can be sent to 0x10000000 through
+	// 0x107fffff, it seems, but the SH4 store queues only have 64 bytes.
+	relative_addr &= (sizeof(d->ta) - 1);
+
+	if (writeflag == MEM_WRITE) {
+		idata = memory_readmax64(cpu, data, len);
+#if 0
+		fatal("[ pvr_ta: WRITE addr=%08x value=%08x ]\n",
+		    (int)relative_addr, (int)idata);
+#endif
+
+		/*  Write to the tile accelerator command buffer:  */
+		d->ta[relative_addr / sizeof(uint32_t)] = idata;
+
+		// Execute the command, after a complete write.
+		// (Note: This assumes that commands are written from low
+		// address to high.)
+		if (relative_addr == 0x1c)
+			pvr_ta_command(cpu, d, 0);
+		if (relative_addr == 0x3c)
+			pvr_ta_command(cpu, d, 8);
+	} else {
+		odata = d->ta[relative_addr / sizeof(uint32_t)];
+		memory_writemax64(cpu, data, len, odata);
+#if 1
+		fatal("[ pvr_ta: READ addr=%08x value=%08x ]\n", (int)relative_addr, (int)odata);
+#endif
+	}
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(pvr)
+{
+	struct pvr_data *d = (struct pvr_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  Default read action: Read from reg[]:  */
+	if (writeflag == MEM_READ)
+		odata = d->reg[relative_addr / sizeof(uint32_t)];
+
+	/*  Fog table access:  */
+	if (relative_addr >= PVRREG_FOG_TABLE &&
+	    relative_addr < PVRREG_FOG_TABLE + PVR_FOG_TABLE_SIZE) {
+		if (writeflag == MEM_WRITE)
+			DEFAULT_WRITE;
+		goto return_ok;
+	}
+
+	/*  Palette access:  */
+	if (relative_addr >= PVRREG_PALETTE &&
+	    relative_addr < PVRREG_PALETTE + PVR_PALETTE_SIZE) {
+		if (writeflag == MEM_WRITE)
+			DEFAULT_WRITE;
+		goto return_ok;
+	}
+
+	switch (relative_addr) {
+
+	case PVRREG_ID:
+		/*  ID for Set 5.xx versions of the Dreamcast, according
+		    to http://www.ludd.luth.se/~jlo/dc/powervr-reg.txt:  */
+		odata = 0x17fd11db;
+		break;
+
+	case PVRREG_REVISION:
+		/*  Revision 1.1, for Dreamcast Set 5.2x.  */
+		odata = 0x00000011;
+		break;
+
+	case PVRREG_RESET:
+		if (writeflag == MEM_WRITE) {
+			if (idata != 0) {
+				debug("[ pvr: RESET ");
+				if (idata & PVR_RESET_PVR)
+					pvr_reset(d);
+				if (idata & PVR_RESET_TA)
+					pvr_reset_ta(d);
+				debug("]\n");
+			}
+			idata = 0;
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_STARTRENDER:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: STARTRENDER ]\n");
+			pvr_render(cpu, d);
+		} else {
+			fatal("[ pvr: huh? read from STARTRENDER ]\n");
+			exit(1);
+		}
+		break;
+
+	case PVRREG_OB_ADDR:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: OB_ADDR set to 0x%08" PRIx32" ]\n",
+			    (uint32_t)(idata & PVR_OB_ADDR_MASK));
+			if (idata & ~PVR_OB_ADDR_MASK) {
+				fatal("[ pvr: OB_ADDR: Fatal error: Unknown"
+				    " bits set: 0x%08" PRIx32" ]\n",
+				    (uint32_t)(idata & ~PVR_OB_ADDR_MASK));
+				exit(1);
+			}
+			idata &= PVR_OB_ADDR_MASK;
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TILEBUF_ADDR:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: TILEBUF_ADDR set to 0x%08" PRIx32" ]\n",
+			    (uint32_t)(idata & PVR_TILEBUF_ADDR_MASK));
+			if (idata & ~PVR_TILEBUF_ADDR_MASK) {
+				fatal("[ pvr: TILEBUF_ADDR: Unknown"
+				    " bits set: 0x%08" PRIx32" ]\n",
+				    (uint32_t)(idata & ~PVR_TILEBUF_ADDR_MASK));
+				exit(1);
+			}
+			idata &= PVR_TILEBUF_ADDR_MASK;
+			DEFAULT_WRITE;
+			pvr_tilebuf_debugdump(d);
+		}
+		break;
+
+	case PVRREG_SPANSORT:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: SPANSORT: ");
+			if (idata & PVR_SPANSORT_SPAN0)
+				debug("SPAN0 ");
+			if (idata & PVR_SPANSORT_SPAN1)
+				debug("SPAN1 ");
+			if (idata & PVR_SPANSORT_TSP_CACHE_ENABLE)
+				debug("TSP_CACHE_ENABLE ");
+			debug("]\n");
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_BRDCOLR:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: BRDCOLR set to 0x%06" PRIx32" ]\n",
+			    (int)idata);
+			DEFAULT_WRITE;
+			d->border_updated = 1;
+		}
+		break;
+
+	case PVRREG_DIWMODE:
+		if (writeflag == MEM_WRITE) {
+			d->clock_double = idata & DIWMODE_C_MASK? 1:0;
+			d->strip_buffer_enabled = idata & DIWMODE_SE_MASK? 1:0;
+			d->strip_length = (idata & DIWMODE_SL_MASK)
+			    >> DIWMODE_SL_SHIFT;
+			d->argb8888_threshold = (idata & DIWMODE_TH_MASK)
+			    >> DIWMODE_TH_SHIFT;
+			d->extend = (idata & DIWMODE_EX_MASK)
+			    >> DIWMODE_EX_SHIFT;
+			d->pixelmode = (idata & DIWMODE_COL_MASK)
+			    >> DIWMODE_COL_SHIFT;
+			d->line_double = idata & DIWMODE_SD_MASK? 1:0;
+			d->display_enabled = idata & DIWMODE_DE_MASK? 1:0;
+
+			debug("[ pvr: DIWMODE set to: ");
+			debug("clock_double=%i, ", d->clock_double);
+			debug("strip_buffer_enabled=%i, ",
+			    d->strip_buffer_enabled);
+			debug("strip_length=%i, ", d->strip_length);
+			debug("argb8888_threshold=%i, ", d->argb8888_threshold);
+			debug("extend=0x%x, ", d->extend);
+			debug("pixelmode=");
+			switch (d->pixelmode) {
+			case 0: debug("RGB0555 (16-bit)"); break;
+			case 1: debug("RGB565 (16-bit)"); break;
+			case 2: debug("RGB888 (24-bit)"); break;
+			case 3: debug("RGB0888 (32-bit)"); break;
+			}
+			debug(", line_double=%i, ", d->line_double);
+			debug("display_enabled=%i", d->display_enabled);
+			debug(" ]\n");
+
+			DEFAULT_WRITE;
+			pvr_geometry_updated(d);
+			pvr_fb_invalidate(d, -1, -1);
+		}
+		break;
+
+	case PVRREG_DIWSIZE:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: DIWSIZE set to modulo=%i, "
+			    "width=%i, height=%i ]\n", (int)
+			    ((idata >> DIWSIZE_MODULO_SHIFT) & DIWSIZE_MASK),
+			    (int)((idata >> DIWSIZE_DPL_SHIFT) & DIWSIZE_MASK),
+			    (int)((idata >> DIWSIZE_LPF_SHIFT) & DIWSIZE_MASK));
+			DEFAULT_WRITE;
+			pvr_geometry_updated(d);
+			pvr_fb_invalidate(d, -1, -1);
+		}
+		break;
+
+	case PVRREG_FB_RENDER_ADDR1:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: FB_RENDER_ADDR1 set to 0x%08" PRIx32
+			    " ]\n", (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_FB_RENDER_ADDR2:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: FB_RENDER_ADDR2 set to 0x%08" PRIx32
+			    " ]\n", (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_FB_CLIP_X:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: FB_CLIP_X set to min=%i, "
+			    "max=%i ]\n", (int) (idata & FB_CLIP_XY_MIN_MASK),
+			    (int) ((idata & FB_CLIP_XY_MAX_MASK)
+			    >> FB_CLIP_XY_MAX_SHIFT));
+			DEFAULT_WRITE;
+			pvr_geometry_updated(d);
+			pvr_fb_invalidate(d, -1, -1);
+		}
+		break;
+
+	case PVRREG_FB_CLIP_Y:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: FB_CLIP_Y set to min=%i, "
+			    "max=%i ]\n", (int) (idata & FB_CLIP_XY_MIN_MASK),
+			    (int) ((idata & FB_CLIP_XY_MAX_MASK)
+			    >> FB_CLIP_XY_MAX_SHIFT));
+			DEFAULT_WRITE;
+			pvr_geometry_updated(d);
+			pvr_fb_invalidate(d, -1, -1);
+		}
+		break;
+
+	case PVRREG_SHADOW:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: SHADOW set to enable=%i, "
+			    "intensity=%i ]\n",
+			    (int) (idata & SHADOW_ENABLE? 1 : 0),
+			    (int) (idata & SHADOW_INTENSITY_MASK));
+			DEFAULT_WRITE;
+			pvr_geometry_updated(d);
+			pvr_fb_invalidate(d, -1, -1);
+		}
+		break;
+
+	case PVRREG_OBJECT_CLIP:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: OBJECT_CLIP 0x%08x ]\n", (int)idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_OB_CFG:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: OB_CFG 0x%08x ]\n", (int)idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_UNKNOWN_80:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: UNKNOWN_80 0x%08x ]\n", (int)idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_UNKNOWN_84:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: UNKNOWN_84 0x%08x ]\n", (int)idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_BGPLANE_Z:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: BGPLANE_Z 0x%08x ]\n", (int)idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_BGPLANE_CFG:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: BGPLANE_CFG 0x%08x ]\n", (int)idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_ISP_CFG:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: ISP_CFG 0x%08x ]\n", (int)idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_VRAM_CFG1:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: VRAM_CFG1 set to 0x%08" PRIx32,
+			    (int) idata);
+			if (idata != VRAM_CFG1_GOOD_REFRESH_VALUE)
+				fatal("{ VRAM_CFG1 = 0x%08" PRIx32" is not "
+				    "yet implemented! }", (int) idata);
+			debug(" ]\n");
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_VRAM_CFG2:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: VRAM_CFG2 set to 0x%08" PRIx32,
+			    (int) idata);
+			if (idata != VRAM_CFG2_UNKNOWN_MAGIC)
+				fatal("{ VRAM_CFG2 = 0x%08" PRIx32" is not "
+				    "yet implemented! }", (int) idata);
+			debug(" ]\n");
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_VRAM_CFG3:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: VRAM_CFG3 set to 0x%08" PRIx32,
+			    (int) idata);
+			if (idata != VRAM_CFG3_UNKNOWN_MAGIC)
+				fatal("{ VRAM_CFG3 = 0x%08" PRIx32" is not "
+				    "yet implemented! }", (int) idata);
+			debug(" ]\n");
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_FOG_TABLE_COL:
+		// e.g. 0x007f7f7f
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: FOG_TABLE_COL set to 0x%06" PRIx32" ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_FOG_VERTEX_COL:
+		// e.g. 0x007f7f7f
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: FOG_VERTEX_COL set to 0x%06" PRIx32" ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_FOG_DENSITY:
+		// e.g. 0x0000ff07
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: FOG_DENSITY set to 0x%08" PRIx32" ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_CLAMP_MAX:
+		// e.g. 0xffffffff
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: CLAMP_MAX set to 0x%06" PRIx32" ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_CLAMP_MIN:
+		// e.g. 0x00000000
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: CLAMP_MIN set to 0x%06" PRIx32" ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_FB_RENDER_CFG:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: PVRREG_FB_RENDER_CFG set to 0x%08x ]\n",
+			    (int) idata);
+			/*  TODO  */
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_FB_RENDER_MODULO:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: PVRREG_FB_RENDER_MODULO set to %i ]\n",
+			    (int) idata);
+			/*  TODO  */
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_DIWADDRL:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: DIWADDRL set to 0x%08" PRIx32" ]\n",
+			    (int) idata);
+			pvr_fb_invalidate(d, -1, -1);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_DIWADDRS:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: DIWADDRS set to 0x%08" PRIx32" ]\n",
+			    (int) idata);
+			pvr_fb_invalidate(d, -1, -1);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_HPOS_IRQ:
+		DEFAULT_WRITE;
+		break;
+
+	case PVRREG_RASEVTPOS:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: RASEVTPOS pos1=%i pos2=%i ]\n",
+			    (int)((idata & RASEVTPOS_POS1_MASK)
+			    >> RASEVTPOS_POS1_SHIFT),
+			    (int)(idata & RASEVTPOS_POS2_MASK));
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_SYNCCONF:
+		if (writeflag == MEM_WRITE) {
+			d->video_enabled = idata & SYNCCONF_VO_MASK? 1:0;
+			d->broadcast_standard = (idata & SYNCCONF_BC_MASK)
+			    >> SYNCCONF_BC_SHIFT;
+			d->interlaced = idata & SYNCCONF_I_MASK? 1:0;
+			d->h_sync_positive = idata & SYNCCONF_HP_MASK? 1:0;
+			d->v_sync_positive = idata & SYNCCONF_VP_MASK? 1:0;
+
+			debug("[ pvr: SYNCCONF set to: ");
+			debug("video_enabled=%i, ", d->video_enabled);
+			switch (d->broadcast_standard) {
+			case SYNCCONF_BC_VGA: debug("VGA"); break;
+			case SYNCCONF_BC_NTSC: debug("NTSC"); break;
+			case SYNCCONF_BC_PAL: debug("PAL"); break;
+			default: debug("*UNKNOWN*"); break;
+			}
+			debug(", interlaced=%i, ", d->interlaced);
+			debug("hsync=%i, ", d->h_sync_positive);
+			debug("vsync=%i ]\n", d->v_sync_positive);
+
+			DEFAULT_WRITE;
+			pvr_geometry_updated(d);
+			pvr_fb_invalidate(d, -1, -1);
+		}
+		break;
+
+	case PVRREG_BRDHORZ:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: BRDHORZ start=%i stop=%i ]\n",
+			    (int)((idata & BRDHORZ_START_MASK)
+			    >> BRDHORZ_START_SHIFT),
+			    (int)(idata & BRDHORZ_STOP_MASK));
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_SYNCSIZE:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: SYNCSIZE v=%i h=%i ]\n",
+			    (int)((idata & SYNCSIZE_V_MASK)
+			    >> SYNCSIZE_V_SHIFT),
+			    (int)(idata & SYNCSIZE_H_MASK));
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_BRDVERT:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: BRDVERT start=%i stop=%i ]\n",
+			    (int)((idata & BRDVERT_START_MASK)
+			    >> BRDVERT_START_SHIFT),
+			    (int)(idata & BRDVERT_STOP_MASK));
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_SYNCH_WIDTH:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: SYNCH_WIDTH 0x%08x ]\n", (int)idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TSP_CFG:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: TSP_CFG 0x%08x ]\n", (int)idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_DIWCONF:
+		if (writeflag == MEM_WRITE) {
+			if ((idata & DIWCONF_MAGIC_MASK) !=
+			    DIWCONF_MAGIC && (idata & DIWCONF_MAGIC_MASK)
+			    != 0) {
+				fatal("PVRREG_DIWCONF magic not set to "
+				    "Magic value. 0x%08x\n", (int)idata);
+				exit(1);
+			}
+			if (idata & DIWCONF_BLANK)
+				debug("[ pvr: PVRREG_DIWCONF: BLANK: TODO ]\n");
+
+			DEFAULT_WRITE;
+			pvr_geometry_updated(d);
+		}
+		break;
+
+	case PVRREG_DIWHSTRT:
+		if (writeflag == MEM_WRITE) {
+			int v = idata & DIWVSTRT_HPOS_MASK;
+			debug("[ pvr: DIWHSTRT hpos=%i (%s) ]\n",
+			    v, v == 174? "PAL" :
+			    (v == 164? "NTSC" :
+			    (v == 144? "VGA" : "unknown!")));
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_DIWVSTRT:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: DIWVSTRT v2=%i v1=%i ]\n",
+			    (int)((idata & DIWVSTRT_V2_MASK)
+			    >> DIWVSTRT_V2_SHIFT),
+			    (int)(idata & DIWVSTRT_V1_MASK));
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_SCALER_CFG:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: SCALER_CFG 0x%08x ]\n", (int)idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_PALETTE_CFG:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: PALETTE_CFG 0x%08x ]\n", (int)idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_SYNC_STAT:
+		/*  TODO. Ugly hack, but it works:  */
+		odata = random();
+		break;
+
+	case PVRREG_MAGIC_110:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: MAGIC_110 set to 0x%08" PRIx32,
+			    (int) idata);
+			if (idata != MAGIC_110_VALUE)
+				fatal("{ MAGIC_110 = 0x%08" PRIx32" is not "
+				    "yet implemented! }", (int) idata);
+			debug(" ]\n");
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TA_LUMINANCE:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: TA_LUMINANCE set to 0x%08" PRIx32" ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TA_OPB_START:
+		if (writeflag == MEM_WRITE) {
+			if (idata & ~TA_OPB_START_MASK) {
+				fatal("[ pvr: UNEXPECTED bits in "
+				    "TA_OPB_START: 0x%08x ]\n", (int)idata);
+				exit(1);
+			}
+			idata &= TA_OPB_START_MASK;
+			debug("[ pvr: TA_OPB_START set to 0x%x ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TA_OB_START:
+		if (writeflag == MEM_WRITE) {
+			if (idata & ~TA_OB_START_MASK) {
+				fatal("[ pvr: UNEXPECTED bits in "
+				    "TA_OB_START: 0x%08x ]\n", (int)idata);
+				exit(1);
+			}
+			idata &= TA_OB_START_MASK;
+			debug("[ pvr: TA_OB_START set to 0x%x ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TA_OPB_END:
+		if (writeflag == MEM_WRITE) {
+			idata &= TA_OPB_END_MASK;
+			debug("[ pvr: TA_OPB_END set to 0x%x ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TA_OB_END:
+		if (writeflag == MEM_WRITE) {
+			idata &= TA_OB_END_MASK;
+			debug("[ pvr: TA_OB_END set to 0x%x ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TA_OPB_POS:
+		if (writeflag == MEM_WRITE) {
+			idata &= TA_OPB_POS_MASK;
+			debug("[ pvr: TA_OPB_POS set to 0x%x ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TA_OB_POS:
+		if (writeflag == MEM_WRITE) {
+			idata &= TA_OB_POS_MASK;
+			debug("[ pvr: TA_OB_POS set to 0x%x ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TA_OPL_INIT:
+		if (writeflag == MEM_WRITE) {
+			idata &= PVR_TA_OPL_INIT_MASK;
+			debug("[ pvr: TA_OPL_INIT set to 0x%x ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TILEBUF_SIZE:
+		if (writeflag == MEM_WRITE) {
+			d->tilebuf_ysize = (idata & TILEBUF_SIZE_HEIGHT_MASK)
+			    >> TILEBUF_SIZE_HEIGHT_SHIFT;
+			d->tilebuf_xsize = idata & TILEBUF_SIZE_WIDTH_MASK;
+			d->tilebuf_xsize ++; d->tilebuf_ysize ++;
+			debug("[ pvr: TILEBUF_SIZE set to %i x %i ]\n",
+			    d->tilebuf_xsize, d->tilebuf_ysize);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TA_OPB_CFG:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: TA_OPB_CFG set to 0x%x ]\n",
+			    (int) idata);
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_TA_INIT:
+		if (writeflag == MEM_WRITE) {
+			debug("[ pvr: TA_INIT ]\n");
+
+			if (idata & PVR_TA_INIT)
+				pvr_ta_init(cpu, d);
+
+			if (idata != PVR_TA_INIT && idata != 0)
+				fatal("{ TA_INIT = 0x%08" PRIx32" is not "
+				    "yet implemented! }", (int) idata);
+
+			/*  Always reset to 0.  */
+			idata = 0;
+			DEFAULT_WRITE;
+		}
+		break;
+
+	case PVRREG_YUV_STAT:
+		// TODO. The "luftvarg" demo accesses this register.
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ pvr: read from UNIMPLEMENTED addr 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ pvr: write to UNIMPLEMENTED addr 0x%x: 0x%x"
+			    " ]\n", (int)relative_addr, (int)idata);
+			DEFAULT_WRITE;
+		}
+
+		exit(1);
+	}
+
+return_ok:
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+void pvr_extend_update_region(struct pvr_data *d, uint64_t low, uint64_t high)
+{
+	int vram_ofs = REG(PVRREG_DIWADDRL);
+	int bytes_per_line = d->xsize * d->bytes_per_pixel;
+
+	low -= vram_ofs;
+	high -= vram_ofs;
+
+	/*  Access inside visible part of VRAM?  */
+	if ((int64_t)high >= 0 && (int64_t)low <
+	    bytes_per_line * d->ysize) {
+		int new_y1, new_y2;
+
+		d->fb_update_x1 = 0;
+		d->fb_update_x2 = d->xsize - 1;
+
+		/*  Calculate which line the low and high addresses
+		    correspond to:  */
+		new_y1 = low / bytes_per_line;
+		new_y2 = high / bytes_per_line + 1;
+
+		if (d->fb_update_y1 < 0 || new_y1 < d->fb_update_y1)
+			d->fb_update_y1 = new_y1;
+		if (d->fb_update_y2 < 0 || new_y2 > d->fb_update_y2)
+			d->fb_update_y2 = new_y2;
+
+		if (d->fb_update_y1 < 0)
+			d->fb_update_y1 = 0;
+		if (d->fb_update_y2 >= d->ysize)
+			d->fb_update_y2 = d->ysize - 1;
+	}
+}
+
+
+DEVICE_TICK(pvr_fb)
+{
+	struct pvr_data *d = (struct pvr_data *) extra;
+	uint64_t high, low = (uint64_t)(int64_t) -1;
+	int vram_ofs = REG(PVRREG_DIWADDRL), pixels_to_copy;
+	int bytes_per_line = d->xsize * d->bytes_per_pixel;
+	int fb_ofs, p;
+	uint8_t *fb = (uint8_t *) d->fb->framebuffer;
+	uint8_t *vram = (uint8_t *) d->vram;
+
+
+	/*
+	 *  Vertical retrace interrupts:
+	 *
+	 *  TODO: Maybe it would be even more realistic to have the timer run
+	 *        at, say, 60*4 = 240 Hz, and have the following events:
+	 *
+	 *	  (tick & 3) == 0	SYSASIC_EVENT_VBLINT
+	 *	  (tick & 3) == 1	SYSASIC_EVENT_PVR_SCANINT1
+	 *	  (tick & 3) == 2	nothing
+	 *	  (tick & 3) == 3	SYSASIC_EVENT_PVR_SCANINT2
+	 */
+	if (d->vblank_interrupts_pending > 0) {
+		-- d->vblank_interrupts_pending;
+
+		SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_VBLINT);
+		SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_PVR_SCANINT1);
+		
+		// Is this needed?
+		SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_PVR_SCANINT2);
+
+		/*  TODO: For now, I don't care about missed interrupts:  */
+		d->vblank_interrupts_pending = 0;
+	}
+
+
+	/*
+	 *  Framebuffer update:
+	 */
+
+	/*  Border changed?  */
+	if (d->border_updated) {
+		/*  Fill border with border color:  */
+		int rgb = REG(PVRREG_BRDCOLR), addr = 0;
+		int x, y, b = rgb & 0xff, g = (rgb >> 8) & 0xff, r = rgb >> 16;
+		int skiplen = (d->fb->xsize-2*PVR_MARGIN) * d->fb->bit_depth/8;
+
+		for (y=0; y<d->fb->ysize; y++) {
+			int xskip = y < PVR_MARGIN || y >=
+			    d->fb->ysize - PVR_MARGIN? -1 : PVR_MARGIN;
+			for (x=0; x<d->fb->xsize; x++) {
+				if (x == xskip) {
+					x = d->fb->xsize - PVR_MARGIN;
+					addr += skiplen;
+				}
+				fb[addr] = r;
+				fb[addr+1] = g;
+				fb[addr+2] = b;
+				addr += 3;
+			}
+		}
+
+		/*  Full redraw of the framebuffer:  */
+		d->fb->update_x1 = 0; d->fb->update_x2 = d->fb->xsize - 1;
+		d->fb->update_y1 = 0; d->fb->update_y2 = d->fb->ysize - 1;
+	}
+
+	memory_device_dyntrans_access(cpu, cpu->mem, extra, &low, &high);
+	if ((int64_t)low != -1)
+		pvr_extend_update_region(d, low, high);
+
+	if (d->fb_update_x1 == -1)
+		return;
+
+	/*  Copy (part of) the VRAM to the framebuffer:  */
+	if (d->fb_update_x2 >= d->xsize)
+		d->fb_update_x2 = d->xsize - 1;
+	if (d->fb_update_y2 >= d->ysize)
+		d->fb_update_y2 = d->ysize - 1;
+
+	vram_ofs += d->fb_update_y1 * bytes_per_line;
+	vram_ofs += d->fb_update_x1 * d->bytes_per_pixel;
+	pixels_to_copy = (d->fb_update_x2 - d->fb_update_x1 + 1);
+	fb_ofs = (d->fb_update_y1 + PVR_MARGIN) * d->fb->bytes_per_line;
+	fb_ofs += (d->fb_update_x1 + PVR_MARGIN) * d->fb->bit_depth / 8;
+
+	/*  Copy the actual pixels: (Four manually inlined, for speed.)  */
+
+	switch (d->pixelmode) {
+	case 0:	/*  RGB0555 (16-bit)  */
+		{
+			int y;
+			for (y=d->fb_update_y1; y<=d->fb_update_y2; y++) {
+				int fo = fb_ofs, vo = vram_ofs;
+				for (p=0; p<pixels_to_copy; p++) {
+					/*  0rrrrrgg(high) gggbbbbb(low)  */
+					fb[fo] = (vram[(vo+1)%VRAM_SIZE] << 1) & 0xf8;
+					fb[fo+1] = ((vram[vo%VRAM_SIZE] >> 2) & 0x38) +
+					    (vram[(vo+1)%VRAM_SIZE] << 6);
+					fb[fo+2] = (vram[vo%VRAM_SIZE] & 0x1f) << 3;
+					fo += 3; vo += 2;
+				}
+				
+				vram_ofs += bytes_per_line;
+				fb_ofs += d->fb->bytes_per_line;
+			}
+		}
+		break;
+
+	case 1: /*  RGB565 (16-bit)  */
+		{
+			int y;
+			for (y=d->fb_update_y1; y<=d->fb_update_y2; y++) {
+				int fo = fb_ofs, vo = vram_ofs;
+				for (p=0; p<pixels_to_copy; p++) {
+					/*  rrrrrggg(high) gggbbbbb(low)  */
+					fb[fo] = vram[(vo+1)%VRAM_SIZE] & 0xf8;
+					fb[fo+1] = ((vram[vo%VRAM_SIZE] >> 3) & 0x1c) +
+					    (vram[(vo+1)%VRAM_SIZE] << 5);
+					fb[fo+2] = (vram[vo%VRAM_SIZE] & 0x1f) << 3;
+					fo += 3; vo += 2;
+				}
+				
+				vram_ofs += bytes_per_line;
+				fb_ofs += d->fb->bytes_per_line;
+			}
+		}
+		break;
+
+	case 2: /*  RGB888 (24-bit)  */
+		{
+			int y;
+			for (y=d->fb_update_y1; y<=d->fb_update_y2; y++) {
+				/*  TODO: Reverse colors, like in the 32-bit case?  */
+				memcpy(fb+fb_ofs, vram+(vram_ofs%VRAM_SIZE), 3*pixels_to_copy);
+				vram_ofs += bytes_per_line;
+				fb_ofs += d->fb->bytes_per_line;
+			}
+		}
+		break;
+
+	case 3: /*  RGB0888 (32-bit)  */
+		{
+			int y;
+			for (y=d->fb_update_y1; y<=d->fb_update_y2; y++) {
+				int fo = fb_ofs, vo = vram_ofs;
+				for (p=0; p<pixels_to_copy; p++) {
+					fb[fo] = vram[(vo+2)%VRAM_SIZE];
+					fb[fo+1] = vram[(vo+1)%VRAM_SIZE];
+					fb[fo+2] = vram[(vo+0)%VRAM_SIZE];
+					fo += 3; vo += 4;
+				}
+				
+				vram_ofs += bytes_per_line;
+				fb_ofs += d->fb->bytes_per_line;
+			}
+		}
+		break;
+	}
+
+	/*
+	 *  Extend the real framebuffer to encompass the area
+	 *  just written to:
+	 */
+
+	/*  Offset to take the margin into account first...  */
+	d->fb_update_x1 += PVR_MARGIN; d->fb_update_y1 += PVR_MARGIN;
+	d->fb_update_x2 += PVR_MARGIN; d->fb_update_y2 += PVR_MARGIN;
+
+	if (d->fb_update_x1 < d->fb->update_x1 || d->fb->update_x1 < 0)
+		d->fb->update_x1 = d->fb_update_x1;
+	if (d->fb_update_x2 > d->fb->update_x2 || d->fb->update_x2 < 0)
+		d->fb->update_x2 = d->fb_update_x2;
+	if (d->fb_update_y1 < d->fb->update_y1 || d->fb->update_y1 < 0)
+		d->fb->update_y1 = d->fb_update_y1;
+	if (d->fb_update_y2 > d->fb->update_y2 || d->fb->update_y2 < 0)
+		d->fb->update_y2 = d->fb_update_y2;
+
+	/*  Clear the PVR's update region:  */
+	d->fb_update_x1 = d->fb_update_x2 =
+	    d->fb_update_y1 = d->fb_update_y2 = -1;
+}
+
+
+DEVICE_ACCESS(pvr_vram_alt)
+{
+	struct pvr_data_alt *d_alt = (struct pvr_data_alt *) extra;
+	struct pvr_data *d = d_alt->d;
+	size_t i;
+
+	if (writeflag == MEM_READ) {
+		/*  Copy from real vram:  */
+		for (i=0; i<len; i++) {
+			int addr = relative_addr + i;
+			addr = ((addr & 4) << 20) | (addr & 3)
+			    | ((addr & 0x7ffff8) >> 1);
+			data[i] = d->vram[addr % VRAM_SIZE];
+		}
+		return 1;
+	}
+
+	// Writes are only allowed as 16-bit access or higher.
+	if (len < sizeof(uint16_t))
+		fatal("pvr_vram_alt: write of less than 16 bits attempted?\n");
+
+	/*
+	 *  Convert writes to alternative VRAM, into normal writes:
+	 */
+
+	for (i=0; i<len; i++) {
+		int addr = relative_addr + i;
+		addr = ((addr & 4) << 20) | (addr & 3) | ((addr & 0x7ffff8) >> 1);
+		// printf("  %08x => alt addr %08x: %02x\n", (int)(relative_addr + i), (int)addr, data[i]);
+		d->vram[addr % VRAM_SIZE] = data[i];
+
+		// TODO: This is probably ultra-slow. (Should not be called
+		// for every _byte_.)
+		pvr_extend_update_region(d, addr, addr);
+	}
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(pvr_vram)
+{
+	struct pvr_data *d = (struct pvr_data *) extra;
+
+	// According to http://mc.pp.se/dc/pvr.html, reads of any size are
+	// allowed.
+	if (writeflag == MEM_READ) {
+		memcpy(data, d->vram + relative_addr, len);
+		return 1;
+	}
+
+	// However, writes are only allowed as 16-bit access or higher.
+	if (len < sizeof(uint16_t))
+		fatal("pvr_vram: write of less than 16 bits attempted?\n");
+
+	/*
+	 *  Write to VRAM:
+	 *
+	 *  Calculate which part of the framebuffer this write corresponds to,
+	 *  if any, and increase the update region to encompass the written
+	 *  memory range.
+	 */
+
+	memcpy(d->vram + relative_addr, data, len);
+	pvr_extend_update_region(d, relative_addr, relative_addr + len - 1);
+
+	return 1;
+}
+
+
+DEVINIT(pvr)
+{
+	struct machine *machine = devinit->machine;
+	struct pvr_data *d;
+	struct pvr_data_alt *d_alt;
+
+	CHECK_ALLOCATION(d = (struct pvr_data *) malloc(sizeof(struct pvr_data)));
+	memset(d, 0, sizeof(struct pvr_data));
+
+	CHECK_ALLOCATION(d_alt = (struct pvr_data_alt *) malloc(sizeof(struct pvr_data_alt)));
+	memset(d_alt, 0, sizeof(struct pvr_data_alt));
+
+	d_alt->d = d;
+
+	memory_device_register(machine->memory, devinit->name,
+	    PVRREG_REGSTART, PVRREG_REGSIZE, dev_pvr_access, d,
+	    DM_DEFAULT, NULL);
+
+	/*  8 MB video RAM:  */
+	d->vram = (uint8_t *) zeroed_alloc(VRAM_SIZE);
+	memory_device_register(machine->memory, "pvr_vram", 0x05000000,
+	    VRAM_SIZE, dev_pvr_vram_access, (void *)d,
+	    DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK
+	    | DM_READS_HAVE_NO_SIDE_EFFECTS, d->vram);
+
+	/*  8 MB video RAM, when accessed at 0xa4000000:  */
+	memory_device_register(machine->memory, "pvr_alt_vram", 0x04000000,
+	    VRAM_SIZE, dev_pvr_vram_alt_access, (void *)d_alt,
+	    DM_DEFAULT, NULL);
+
+	/*  Tile Accelerator command area at 0x10000000:  */
+	memory_device_register(machine->memory, "pvr_ta",
+	    0x10000000, 0x800000, dev_pvr_ta_access, d, DM_DEFAULT, NULL);
+
+	/*  PVR2 DMA registers at 0x5f6800:  */
+	memory_device_register(machine->memory, "pvr_dma", 0x005f6800,
+	    PVR_DMA_MEMLENGTH, dev_pvr_dma_access, d, DM_DEFAULT, NULL);
+
+	/*  More DMA registers at 0x5f7c00:  */
+	memory_device_register(machine->memory, "pvr_dma_more", 0x005f7c00,
+	    PVR_DMA_MEMLENGTH, dev_pvr_dma_more_access, d, DM_DEFAULT, NULL);
+
+	d->xsize = 640;
+	d->ysize = 480;
+	d->pixelmode = 1;	/*  RGB565  */
+	d->bytes_per_pixel = 2;
+
+	d->fb = dev_fb_init(machine, machine->memory, INTERNAL_FB_ADDR,
+	    VFB_GENERIC, d->xsize + PVR_MARGIN*2, d->ysize + PVR_MARGIN*2,
+	    d->xsize + PVR_MARGIN*2, d->ysize + PVR_MARGIN*2,
+	    24, "Dreamcast PVR");
+
+	d->vblank_timer = timer_add(PVR_VBLANK_HZ, pvr_vblank_timer_tick, d);
+
+	pvr_reset(d);
+	pvr_reset_ta(d);
+
+	machine_add_tickfunction(machine, dev_pvr_fb_tick, d,
+	    PVR_FB_TICK_SHIFT);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_pvr.cc gxemul-0.7.0+dfsg/src/devices/dev_pvr.cc
--- gxemul-0.6.2/src/devices/dev_pvr.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_pvr.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,2594 +0,0 @@
-/*
- *  Copyright (C) 2006-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: PowerVR CLX2 (graphics controller used in the Dreamcast)
- *
- *  Implemented by reading http://www.ludd.luth.se/~jlo/dc/powervr-reg.txt and
- *  http://mc.pp.se/dc/pvr.html, source code of various demos and KallistiOS,
- *  attempting to run the PROM from my own Dreamcast, and doing a lot of
- *  guessing.
- *
- *  TODO: Almost everything
- *
- *	x)  Change resolution during runtime (PAL/NTSC/???)
- *
- *	x)  Lots of work on the 3D "Tile Accelerator" engine.
- *		Recognize commands and turn into OpenGL or similar
- *		commands on the host?
- *		Wire-frame when running on a host without XGL?
- *
- *  Multiple lists of various kinds (6?).
- *  Lists growing downwards!
- *  Pixel clip for rendering.
- *  Real Rendering, using OpenGL if possible.
- *  Tile bins... with 6 pointers for each tile (?)
- *  PVR DMA.
- *  Textures.
- *  ...
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "float_emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "timer.h"
-
-#include "thirdparty/dreamcast_pvr.h"
-#include "thirdparty/dreamcast_sysasicvar.h"
-
-
-/* For debugging: */
-//#define DEBUG_RENDER_AS_WIRE_FRAME	// Renders 3-corner textured polygons as wire-frame
-//#define	TA_DEBUG		// Dumps TA commands
-//#define debug fatal			// Dumps debug even without -v.
-
-#define	INTERNAL_FB_ADDR	0x300000000ULL
-#define	PVR_FB_TICK_SHIFT	18
-
-#define	PVR_VBLANK_HZ		60.0
-
-#define	PVR_MARGIN		16
-
-#define	VRAM_SIZE		(8*1048576)
-
-/*  DMA:  */
-#define	PVR_DMA_MEMLENGTH	0x100
-#define	N_PVR_DMA_REGS		(PVR_DMA_MEMLENGTH / sizeof(uint32_t))
-
-#define	PVR_ADDR		0x00
-#define	PVR_COUNT		0x04
-#define	PVR_MODE		0x08
-#define	PVR_LMMODE0		0x84  
-#define	PVR_LMMODE1		0x88
-
-
-struct pvr_data {
-	struct vfb_data		*fb;
-	int			fb_update_x1;
-	int			fb_update_y1;
-	int			fb_update_x2;
-	int			fb_update_y2;
-
-	struct timer		*vblank_timer;
-	int			vblank_interrupts_pending;
-
-	/*  PVR registers:  */
-	uint32_t		reg[PVRREG_REGSIZE / sizeof(uint32_t)];
-
-	/*  Calculated by pvr_geometry_updated():  */
-	int			xsize, ysize;
-	int			bytes_per_pixel;
-
-	/*  Cached values (from registers):  */
-	/*  DIWMODE:  */
-	int			clock_double;
-	int			strip_buffer_enabled;
-	int			strip_length;
-	int			argb8888_threshold;
-	int			extend;
-	int			pixelmode;
-	int			line_double;
-	int			display_enabled;
-	/*  BRDCOLR:  */
-	int			border_updated;
-	/*  SYNCCONF:  */
-	int			video_enabled;
-	int			broadcast_standard;
-	int			interlaced;
-	int			h_sync_positive;
-	int			v_sync_positive;
-	/*  TILEBUF_SIZE:  */
-	int			tilebuf_xsize;
-	int			tilebuf_ysize;
-
-	/*  Current Tile Accelerator Command (64 bytes):  */
-	uint32_t		ta[64 / sizeof(uint32_t)];
-
-	/*  Stored list of TA commands:  */
-	int			current_list_type;
-	uint32_t		*ta_commands;
-	size_t			allocated_ta_commands;
-	size_t			n_ta_commands;
-
-	/*  Video RAM and Z information:  */
-	uint8_t			*vram;
-	double			*vram_z;
-
-	/*  DMA registers:  */
-	uint32_t		dma_reg[N_PVR_DMA_REGS];
-	uint32_t		dma_more_reg[N_PVR_DMA_REGS];
-};
-
-struct pvr_data_alt {
-	struct pvr_data		*d;
-};
-
-
-#define	REG(x)		(d->reg[(x)/sizeof(uint32_t)])
-#define	DEFAULT_WRITE	REG(relative_addr) = idata;
-
-
-/*  Forward declaration.  */
-DEVICE_ACCESS(pvr_ta);
-
-
-void pvr_dma_transfer(struct cpu *cpu, struct pvr_data *d)
-{
-	const int channel = 2;
-	uint32_t sar = cpu->cd.sh.dmac_sar[channel] & 0x1fffffff;
-	uint32_t dar = cpu->cd.sh.dmac_dar[channel] & 0x1fffffff;
-	uint32_t count = cpu->cd.sh.dmac_tcr[channel] & 0x1fffffff;
-	uint32_t chcr = cpu->cd.sh.dmac_chcr[channel];
-	int transmit_size = 1;
-	int src_delta = 0, dst_delta = 0;
-	int cause_interrupt = chcr & CHCR_IE;
-
-#if 0
-	// Dump all SH4 DMA channels, for debugging:
-	for (int dmaChannel = 0; dmaChannel < 4; ++dmaChannel)
-	{
-		fatal("{# dma channel %i: sar=%08x dar=%08x count=%08x chcr=%08x #}\n",
-		    dmaChannel,
-		    cpu->cd.sh.dmac_sar[dmaChannel],
-		    cpu->cd.sh.dmac_dar[dmaChannel],
-		    cpu->cd.sh.dmac_tcr[dmaChannel],
-		    cpu->cd.sh.dmac_chcr[dmaChannel]);
-	}
-#endif
-
-	/*  DMAC not enabled?  */
-	if (!(chcr & CHCR_TD)) {
-		fatal("pvr_dma_transfer: SH4 dma not enabled?\n");
-		exit(1);
-	}
-
-	/*  Transfer End already set? Then don't transfer again.  */
-	if (chcr & CHCR_TE)
-		return;
-
-	/*  Special case: 0 means 16777216:  */
-	if (count == 0)
-		count = 16777216;
-
-	switch (chcr & CHCR_TS) {
-	case CHCR_TS_8BYTE: transmit_size = 8; break;
-	case CHCR_TS_1BYTE: transmit_size = 1; break;
-	case CHCR_TS_2BYTE: transmit_size = 2; break;
-	case CHCR_TS_4BYTE: transmit_size = 4; break;
-	case CHCR_TS_32BYTE: transmit_size = 32; break;
-	default: fatal("Unimplemented transmit size?! CHCR[%i] = 0x%08x\n",
-	    channel, chcr);
-	exit(1);
-	}
-
-	switch (chcr & CHCR_DM) {
-	case CHCR_DM_FIXED:       dst_delta = 0; break;
-	case CHCR_DM_INCREMENTED: dst_delta = 1; break;
-	case CHCR_DM_DECREMENTED: dst_delta = -1; break;
-	default: fatal("Unimplemented destination delta?! CHCR[%i] = 0x%08x\n",
-	    channel, chcr);
-	exit(1);
-	}
-
-	switch (chcr & CHCR_SM) {
-	case CHCR_SM_FIXED:       src_delta = 0; break;
-	case CHCR_SM_INCREMENTED: src_delta = 1; break;
-	case CHCR_SM_DECREMENTED: src_delta = -1; break;
-	default: fatal("Unimplemented source delta?! CHCR[%i] = 0x%08x\n",
-	    channel, chcr);
-	exit(1);
-	}
-
-	src_delta *= transmit_size;
-	dst_delta *= transmit_size;
-
-	switch (chcr & CHCR_RS) {
-	case 0x200:
-		dar = d->dma_reg[PVR_ADDR / sizeof(uint32_t)];
-
-		if (dar != 0x10000000) {
-			//fatal("[ NOTE: DMA to non-TA: dar=%08x (delta %i), sar=%08x (delta %i) ]\n",
-			//    (int)dar, (int)dst_delta, (int)sar, (int)src_delta);
-			dar = 0x04000000 | (dar & 0x007fffff);
-			if (dst_delta == 0)
-				dst_delta = src_delta;
-
-			uint8_t *buf = (uint8_t*) malloc(transmit_size);
-			while (count > 0) {
-				// printf("sar = %08x dar = %08x\n", (int)sar, (int)dar);
-				
-				cpu->memory_rw(cpu, cpu->mem, sar, buf,
-				    transmit_size, MEM_READ, NO_EXCEPTIONS | PHYSICAL);
-				// for (int i = 0; i < transmit_size; ++i)
-				// 	printf("%02x ", buf[i]);
-				// printf("\n");
-
-				cpu->memory_rw(cpu, cpu->mem, dar, buf,
-				    transmit_size, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
-
-				count --;
-				sar += src_delta;
-				dar += dst_delta;
-			}
-
-			free(buf);
-
-			break;
-		} else {
-			while (count > 0) {
-				unsigned char buf[sizeof(uint32_t)];
-				int ofs;
-				size_t chunksize = transmit_size;
-
-				if (chunksize > sizeof(uint32_t))
-					chunksize = sizeof(uint32_t);
-
-				for (ofs = 0; ofs < transmit_size; ofs += chunksize) {
-					cpu->memory_rw(cpu, cpu->mem, sar + ofs, buf,
-					    chunksize, MEM_READ, NO_EXCEPTIONS | PHYSICAL);
-
-					dev_pvr_ta_access(cpu, cpu->mem, ofs, buf, chunksize,
-					    MEM_WRITE, d);
-				}
-
-				count --;
-				sar += src_delta;
-			}
-		}
-
-		// Transfer End. TODO: _EXACTLY_ what happens at the end of
-		// a transfer?
-		cpu->cd.sh.dmac_chcr[channel] |= CHCR_TE;
-		cpu->cd.sh.dmac_chcr[channel] &= ~CHCR_TD;
-		cpu->cd.sh.dmac_sar[channel] = sar;
-		cpu->cd.sh.dmac_tcr[channel] = count;
-
-		// d->dma_reg[PVR_ADDR / sizeof(uint32_t)] = ???;
-		d->dma_reg[PVR_COUNT / sizeof(uint32_t)] = 0;
-
-		SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_PVR_DMA);
-
-		break;
-	default:
-		fatal("Unimplemented SH4 RS DMAC: 0x%08x (PVR)\n",
-		    (int) (chcr & CHCR_RS));
-		exit(1);
-	}
-
-	if (cause_interrupt) {
-		fatal("TODO: pvr sh4 dmac interrupt!\n");
-		exit(1);
-	}
-}
-
-
-DEVICE_ACCESS(pvr_dma)
-{
-	struct pvr_data *d = (struct pvr_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  Default read:  */
-	if (writeflag == MEM_READ)
-		odata = d->dma_reg[relative_addr / sizeof(uint32_t)];
-
-	switch (relative_addr) {
-
-	case PVR_ADDR:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr_dma: ADDR set to 0x%08x ]\n",
-			    (int) idata);
-		}
-		break;
-
-	case PVR_COUNT:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr_dma: COUNT set to 0x%08x ]\n",
-			    (int) idata);
-		}
-		break;
-
-	case PVR_MODE:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr_dma: MODE set to 0x%08x ]\n",
-			    (int) idata);
-			if (idata != 0) {
-				pvr_dma_transfer(cpu, d);
-				idata = 0;
-			}
-		}
-		break;
-
-	/*  These are written to by the Dreamcast ROM, but I have not
-	    found them documented anywhere.  */
-	case 0x10:
-	case 0x14:
-		if (writeflag == MEM_WRITE && idata != 0x0cff0000) {
-			fatal("[ pvr_dma: TODO: unknown_0x%02x set to "
-			    "0x%08x ]\n", (int) relative_addr, (int) idata);
-			exit(1);
-		}
-		break;
-
-	case 0x18:
-	case 0x1c:
-	case 0x20:
-	case 0x40:
-	case 0x44:
-	case 0x48:
-	case 0x4c:
-		if (writeflag == MEM_WRITE && idata != 0) {
-			fatal("[ pvr_dma: TODO: unknown_0x%02x set to "
-			    "0x%08x ]\n", (int) relative_addr, (int) idata);
-			exit(1);
-		}
-		break;
-
-	case PVR_LMMODE0:	/*  0x84  */
-		if (writeflag == MEM_WRITE && idata != 0) {
-			fatal("[ pvr_dma: TODO: LMMODE0 set to "
-			    "0x%08x ]\n", (int) idata);
-			exit(1);
-		}
-		break;
-
-	case PVR_LMMODE1:	/*  0x88  */
-		if (writeflag == MEM_WRITE && idata != 0) {
-			fatal("[ pvr_dma: TODO: LMMODE1 set to "
-			    "0x%08x ]\n", (int) idata);
-			exit(1);
-		}
-		break;
-
-	case 0x8c:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ pvr_dma: write to 0x8c: TODO ]\n");
-			exit(1);
-		} else {
-			/*  0x20 means G2 DMA in progress?  */
-			/*  0x11 = mask which has to do with AICA  */
-			odata = 0x11 * (random() & 1);
-		}
-		break;
-
-	case 0x9c:
-		if (writeflag == MEM_WRITE && idata != 0) {
-			fatal("[ pvr_dma: TODO: unknown_0x%02x set to "
-			    "0x%08x ]\n", (int) relative_addr, (int) idata);
-			exit(1);
-		}
-		break;
-
-	case 0xa0:
-		if (writeflag == MEM_WRITE && idata != 0x80000000) {
-			fatal("[ pvr_dma: TODO: unknown_0x%02x set to "
-			    "0x%08x ]\n", (int) relative_addr, (int) idata);
-			exit(1);
-		}
-		break;
-
-	case 0xa4:
-	case 0xac:
-		if (writeflag == MEM_WRITE && idata != 0) {
-			fatal("[ pvr_dma: TODO: unknown_0x%02x set to "
-			    "0x%08x ]\n", (int) relative_addr, (int) idata);
-			exit(1);
-		}
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ pvr_dma: read from addr 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ pvr_dma: write to addr 0x%x: 0x%x ]\n",
-			    (int)relative_addr, (int)idata);
-		}
-
-		exit(1);
-	}
-
-	/*  Default write:  */
-	if (writeflag == MEM_WRITE)
-		d->dma_reg[relative_addr / sizeof(uint32_t)] = idata;
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(pvr_dma_more)
-{
-	struct pvr_data *d = (struct pvr_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  Default read:  */
-	if (writeflag == MEM_READ)
-		odata = d->dma_more_reg[relative_addr / sizeof(uint32_t)];
-
-	switch (relative_addr) {
-
-	case 0x00:	// 0x04ff0000
-	case 0x04:	// 0x0cff0000
-	case 0x08:	// 0x00000020
-	case 0x0c:	// 0x00000000
-	case 0x10:	// 0x00000000
-	case 0x80:	// 0x67027f00
-		break;
-
-	case 0x14:
-	case 0x18:
-		if (writeflag == MEM_WRITE && idata != 0)
-		{
-			fatal("PVR other DMA mode (?):\n");
-			fatal("0x00: %08x\n", d->dma_more_reg[0x00/4]);
-			fatal("0x04: %08x\n", d->dma_more_reg[0x04/4]);
-			fatal("0x08: %08x\n", d->dma_more_reg[0x08/4]);
-			fatal("0x0c: %08x\n", d->dma_more_reg[0x0c/4]);
-			fatal("0x10: %08x\n", d->dma_more_reg[0x10/4]);
-			fatal("0x14: %08x\n", d->dma_more_reg[0x14/4]);
-			exit(1);
-		}
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ pvr_dma_more: read from addr 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ pvr_dma_more: write to addr 0x%x: 0x%x ]\n",
-			    (int)relative_addr, (int)idata);
-		}
-
-		exit(1);
-	}
-
-	/*  Default write:  */
-	if (writeflag == MEM_WRITE)
-		d->dma_more_reg[relative_addr / sizeof(uint32_t)] = idata;
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  pvr_fb_invalidate():
- */
-void pvr_fb_invalidate(struct pvr_data *d, int start, int stop)
-{
-	d->fb_update_x1 = d->fb_update_y1 = 0;
-	d->fb_update_x2 = d->xsize - 1;
-	d->fb_update_y2 = d->ysize - 1;
-}
-
-
-/*
- *  pvr_vblank_timer_tick():
- *
- *  This function is called PVR_VBLANK_HZ times per real-world second. Its job
- *  is to fake vertical retrace interrupts.
- */     
-static void pvr_vblank_timer_tick(struct timer *t, void *extra)
-{
-	struct pvr_data *d = (struct pvr_data *) extra;
-	d->vblank_interrupts_pending ++;
-}
-
-
-/*
- *  pvr_geometry_updated():
- *
- *  This function should be called every time a register is written to which
- *  affects the framebuffer geometry (size, bit-depth, starting position, etc).
- */
-void pvr_geometry_updated(struct pvr_data *d)
-{
-	int old_xsize = d->xsize, old_ysize = d->ysize, oldbpp = d->bytes_per_pixel;
-
-	/*  Make sure to redraw border on geometry changes.  */
-	d->border_updated = 1;
-
-	d->xsize = (REG(PVRREG_DIWSIZE) >> DIWSIZE_DPL_SHIFT) & DIWSIZE_MASK;
-	d->ysize = (REG(PVRREG_DIWSIZE) >> DIWSIZE_LPF_SHIFT) & DIWSIZE_MASK;
-
-	/*  E.g. 319x479  =>  320x480  */
-	d->xsize = (d->xsize + 1) * sizeof(uint32_t);
-	d->ysize ++;
-
-	switch (d->pixelmode) {
-	case 0:
-	case 1:	d->bytes_per_pixel = 2; break;
-	case 2:	d->bytes_per_pixel = 3; break;
-	case 3:	d->bytes_per_pixel = 4; break;
-	}
-
-	d->xsize /= d->bytes_per_pixel;
-
-	if (REG(PVRREG_DIWCONF) & DIWCONF_LR)
-		d->xsize /= 2;
-
-	if (d->line_double)
-		d->ysize /= 2;
-
-	bool settingsChanged = d->xsize != old_xsize ||
-	    d->ysize != old_ysize ||
-	    d->bytes_per_pixel != oldbpp;
-
-	if (!settingsChanged)
-		return;
-
-	/*  Scrap Z buffer if we have one.  */
-	if (d->vram_z == NULL) {
-		free(d->vram_z);
-		d->vram_z = NULL;
-	}
-		
-	/*  Only show geometry debug message if output is enabled:  */
-	if (!d->video_enabled || !d->display_enabled)
-		return;
-
-	debug("[ pvr_geometry_updated: %i x %i, ", d->xsize, d->ysize);
-
-	switch (d->pixelmode) {
-	case 0: debug("RGB0555 (16-bit)"); break;
-	case 1: debug("RGB565 (16-bit)"); break;
-	case 2: debug("RGB888 (24-bit)"); break;
-	case 3: debug("RGB0888 (32-bit)"); break;
-	}
-
-	debug(" ]\n");
-}
-
-
-#ifdef DEBUG_RENDER_AS_WIRE_FRAME
-/*  Ugly quick-hack:  */
-static void line(struct pvr_data *d, int x1, int y1, int x2, int y2)
-{
-	int fb_base = REG(PVRREG_FB_RENDER_ADDR1);
-	int i;
-	for (i=0; i<256; i++) {
-		int px = (i * x2 + (256-i) * x1) >> 8;
-		int py = (i * y2 + (256-i) * y1) >> 8;
-		if (px > 0 && py > 0 && px < d->xsize && py < d->ysize) {
-			int ofs = fb_base + (px + py * d->xsize) *
-                            d->bytes_per_pixel;
-			d->vram[(ofs+0) % VRAM_SIZE] = 255;
-			d->vram[(ofs+1) % VRAM_SIZE] = 255;
-		}
-	}
-}
-#endif
-
-
-// Ugly quick-hack z-buffer line drawer, for triangles.
-// Assumes 16-bit color.
-static void simpleline(struct pvr_data *d, int y, double x1, double x2,
-	double z1, double z2, double r1, double r2, double g1, double g2,
-	double b1, double b2)
-{
-	if (y < 0 || y >= d->ysize || (x1 < 0 && x2 < 0)
-	     || (x1 >= d->xsize && x2 >= d->xsize))
-		return;
-
-	int fb_base = REG(PVRREG_FB_RENDER_ADDR1);
-	if (x1 > x2) {
-		double tmpf = x1; x1 = x2; x2 = tmpf;
-		tmpf = z1; z1 = z2; z2 = tmpf;
-		tmpf = r1; r1 = r2; r2 = tmpf;
-		tmpf = g1; g1 = g2; g2 = tmpf;
-		tmpf = b1; b1 = b2; b2 = tmpf;
-	}
-
-	// uint32_t fogDensity = REG(PVRREG_FOG_DENSITY);
-	// double scale_factor = 255.0;	// TODO: take fogDensity into account.
-	// uint32_t fogColor = REG(PVRREG_FOG_TABLE_COL);
-	// int fog_r = (fogColor >> 16) & 255;
-	// int fog_g = (fogColor >> 8) & 255;
-	// int fog_b = fogColor & 255;
-
-	double dz12 = (x2 - x1 != 0) ? ( (double)(z2 - z1) / (double)(x2 - x1) ) : 0;
-	double dr12 = (x2 - x1 != 0) ? ( (double)(r2 - r1) / (double)(x2 - x1) ) : 0;
-	double dg12 = (x2 - x1 != 0) ? ( (double)(g2 - g1) / (double)(x2 - x1) ) : 0;
-	double db12 = (x2 - x1 != 0) ? ( (double)(b2 - b1) / (double)(x2 - x1) ) : 0;
-	double z = z1, r = r1, g = g1, b = b1;
-	for (int x = x1; x <= x2; ++x) {
-		if (x > 0 && x < d->xsize) {
-			int ofs = x + y * d->xsize;
-			if (d->vram_z[ofs] <= z) {
-				d->vram_z[ofs] = z;
-
-				// z = 1/w
-				// int v = z * scale_factor;
-				// printf("z=%f v=%i\n", z, v);
-				// if (v < 0) v = 0;
-				// if (v > 255) v = 255;
-				// v >>= 1;
-
-				// int fogvalues = d->reg[PVRREG_FOG_TABLE  / sizeof(uint32_t) + v];
-				// printf("fogv = %04x\n", fogvalues);
-
-				// NOTE/TODO: Hardcoded for 565 pixelformat.
-				int ri = r, gi = g, bi = b;
-				// int a = (fogvalues >> 8) & 255;
-				// ri = ((fog_r * a) + (ri * (255 - a))) >> 8;
-				// gi = ((fog_g * a) + (gi * (255 - a))) >> 8;
-				// bi = ((fog_b * a) + (bi * (255 - a))) >> 8;
-
-				if (ri < 0) ri = 0; if (ri > 255) ri = 255;
-				if (gi < 0) gi = 0; if (gi > 255) gi = 255;
-				if (bi < 0) bi = 0; if (bi > 255) bi = 255;
-				int color = ((ri >> 3) << 11) + ((gi >> 2) << 5) + (bi >> 3);
-
-				int fbofs = fb_base + ofs * d->bytes_per_pixel;
-				d->vram[(fbofs+0) % VRAM_SIZE] = color & 255;
-				d->vram[(fbofs+1) % VRAM_SIZE] = color >> 8;
-			}
-		}
-		
-		z += dz12; r += dr12; g += dg12; b += db12;
-	}
-}
-
-static void texturedline(struct pvr_data *d,
-	int texture_pixelformat, bool twiddled, int stride,
-	int texture, int texture_xsize, int texture_ysize,
-	int y, int x1, int x2, double z1, double z2,
-	double u1, double u2, double v1, double v2)
-{
-	if (y < 0 || y >= d->ysize || (x1 < 0 && x2 < 0)
-	     || (x1 >= d->xsize && x2 >= d->xsize))
-		return;
-
-	int fb_base = REG(PVRREG_FB_RENDER_ADDR1);
-	if (x1 > x2) {
-		int tmp = x1; x1 = x2; x2 = tmp;
-		double tmpf = z1; z1 = z2; z2 = tmpf;
-		tmpf = u1; u1 = u2; u2 = tmpf;
-		tmpf = v1; v1 = v2; v2 = tmpf;
-	}
-
-	int bytesperpixel = 2;
-
-	switch (texture_pixelformat)
-	{
-	case 0:	// ARGB1555
-	case 1:	// RGB565
-	case 2: // ARGB4444
-		bytesperpixel = 2;
-		break;
-	case 6:	// 8-bit palette
-		bytesperpixel = 1;
-		break;
-	default:
-		// TODO
-		break;
-	}
-
-	int palette_cfg = d->reg[PVRREG_PALETTE_CFG / sizeof(uint32_t)] & PVR_PALETTE_CFG_MODE_MASK;
-
-	double dz12 = (x2 - x1 != 0) ? ( (double)(z2 - z1) / (double)(x2 - x1) ) : 0;
-	double du12 = (x2 - x1 != 0) ? ( (double)(u2 - u1) / (double)(x2 - x1) ) : 0;
-	double dv12 = (x2 - x1 != 0) ? ( (double)(v2 - v1) / (double)(x2 - x1) ) : 0;
-
-	double z = z1, u = u1, v = v1;
-
-	for (int x = x1; x <= x2; ++x) {
-		if (x > 0 && x < d->xsize) {
-			int ofs = x + y * d->xsize;
-			if (d->vram_z[ofs] <= z) {
-				d->vram_z[ofs] = z;
-
-				int fbofs = fb_base + ofs * d->bytes_per_pixel;
-
-				// Get color from texture:
-				int texturex = u * texture_xsize;
-				texturex &= (texture_xsize-1);
-				int texturey = v * texture_ysize;
-				texturey &= (texture_ysize-1);
-
-				int textureofs;
-				if (twiddled) {
-					texturex = 
-					(texturex&1)|((texturex&2)<<1)|((texturex&4)<<2)|((texturex&8)<<3)|((texturex&16)<<4)|
-					      ((texturex&32)<<5)|((texturex&64)<<6)|((texturex&128)<<7)|((texturex&256)<<8)|((texturex&512)<<9);
-					texturey = 
-					(texturey&1)|((texturey&2)<<1)|((texturey&4)<<2)|((texturey&8)<<3)|((texturey&16)<<4)|
-					      ((texturey&32)<<5)|((texturey&64)<<6)|((texturey&128)<<7)|((texturey&256)<<8)|((texturey&512)<<9);
-					textureofs = texturex * 2 + texturey;
-				} else {
-					if (stride > 0)
-						textureofs = texturex + texturey * stride;
-					else
-						textureofs = texturex + texturey * texture_xsize;
-				}
-
-				textureofs *= bytesperpixel;	// 2 bytes per pixel.
-
-				int addr = texture + textureofs;
-				addr = ((addr & 4) << 20) | (addr & 3) | ((addr & 0x7ffff8) >> 1);
-
-				int a = 255, r = 64, g = 64, b = 64;
-				switch (texture_pixelformat)
-				{
-				case 0:	// ARGB1555:
-					{
-						int color = d->vram[addr] + (d->vram[addr+1] << 8);
-						a = (color >> 15) & 0x1 ? 255 : 0;
-						r = (color >> 10) & 0x1f;
-						g = ((color >> 5) & 0x1f) << 1;
-						b = (color) & 0x1f;
-					}
-					break;
-				case 1:	// RGB565:
-					{
-						int color = d->vram[addr] + (d->vram[addr+1] << 8);
-						r = (color >> 11) & 0x1f;
-						g = (color >> 5) & 0x3f;
-						b = (color) & 0x1f;
-					}
-					break;
-				case 2:	// ARGB4444:
-					{
-						int color = d->vram[addr] + (d->vram[addr+1] << 8);
-						a = ((color >> 12) & 15) * 0x11;
-						r = ((color >> 8) & 15) << 1;
-						g = ((color >> 4) & 15) << 2;
-						b = ((color) & 15) << 1;
-					}
-					break;
-				case 6:
-					{
-						// TODO: multiple palette banks? Endianness?
-						int index8bpp = d->vram[addr];
-						char* base = (char*)&d->reg[PVRREG_PALETTE / sizeof(uint32_t)];
-						uint16_t c16 = *((uint16_t*)(void*)base + index8bpp);
-						uint16_t c32 = *((uint32_t*)(void*)base + index8bpp);
-						switch (palette_cfg) {
-						case PVR_PALETTE_CFG_MODE_ARGB1555:
-							a = (c16 >> 15) & 0x1 ? 255 : 0;
-							r = (c16 >> 10) & 0x1f;
-							g = ((c16 >> 5) & 0x1f) << 1;
-							b = (c16) & 0x1f;
-							break;
-						case PVR_PALETTE_CFG_MODE_RGB565:
-							r = (c16 >> 11) & 0x1f;
-							g = (c16 >> 5) & 0x3f;
-							b = (c16) & 0x1f;
-							break;
-						case PVR_PALETTE_CFG_MODE_ARGB4444:
-							a = ((c16 >> 12) & 15) * 0x11;
-							r = ((c16 >> 8) & 15) << 1;
-							g = ((c16 >> 4) & 15) << 2;
-							b = ((c16) & 15) << 1;
-							break;
-						case PVR_PALETTE_CFG_MODE_ARGB8888:
-							a = (c32 >> 24) & 255;
-							r = ((c32 >> 16) & 255) >> 3;
-							g = ((c32 >> 8) & 255) >> 2;
-							b = ((c32) & 255) >> 3;
-							break;
-						}
-					}
-					break;
-				default:
-					fatal("pvr: unimplemented texture_pixelformat %i\n", texture_pixelformat);
-					exit(1);
-				}
-
-				if (a == 255)
-				{
-					// Output as RGB565:
-					// TODO: Support other formats.
-					int color = (r << 11) + (g << 5) + (b);
-					d->vram[(fbofs+0) % VRAM_SIZE] = color & 255;
-					d->vram[(fbofs+1) % VRAM_SIZE] = color >> 8;
-				} else if (a > 0) {
-					int oldcolor = d->vram[(fbofs+0) % VRAM_SIZE];
-					oldcolor += (d->vram[(fbofs+1) % VRAM_SIZE] << 8);
-					int oldr = (oldcolor >> 11) & 0x1f;
-					int oldg = (oldcolor >> 5) & 0x3f;
-					int oldb = (oldcolor) & 0x1f;
-					r = (a * r + oldr * (255 - a)) / 255;
-					g = (a * g + oldg * (255 - a)) / 255;
-					b = (a * b + oldb * (255 - a)) / 255;
-					int color = (r << 11) + (g << 5) + (b);
-					d->vram[(fbofs+0) % VRAM_SIZE] = color & 255;
-					d->vram[(fbofs+1) % VRAM_SIZE] = color >> 8;
-				}
-			}
-		}
-		
-		z += dz12;
-		u += du12;
-		v += dv12;
-	}
-}
-
-
-// Slow software rendering, for debugging:
-static void pvr_render_triangle(struct pvr_data *d,
-	int x1, int y1, double z1, int r1, int g1, int b1,
-	int x2, int y2, double z2, int r2, int g2, int b2,
-	int x3, int y3, double z3, int r3, int g3, int b3)
-{
-	// Easiest if 1, 2, 3 are in order top to bottom.
-	if (y2 < y1) {
-		int tmp = x1; x1 = x2; x2 = tmp;
-		tmp = y1; y1 = y2; y2 = tmp;
-		tmp = r1; r1 = r2; r2 = tmp;
-		tmp = g1; g1 = g2; g2 = tmp;
-		tmp = b1; b1 = b2; b2 = tmp;
-		double tmpf = z1; z1 = z2; z2 = tmpf;
-	}
-
-	if (y3 < y1) {
-		int tmp = x1; x1 = x3; x3 = tmp;
-		tmp = y1; y1 = y3; y3 = tmp;
-		tmp = r1; r1 = r3; r3 = tmp;
-		tmp = g1; g1 = g3; g3 = tmp;
-		tmp = b1; b1 = b3; b3 = tmp;
-		double tmpf = z1; z1 = z3; z3 = tmpf;
-	}
-
-	if (y3 < y2) {
-		int tmp = x2; x2 = x3; x3 = tmp;
-		tmp = y2; y2 = y3; y3 = tmp;
-		tmp = r2; r2 = r3; r3 = tmp;
-		tmp = g2; g2 = g3; g3 = tmp;
-		tmp = b2; b2 = b3; b3 = tmp;
-		double tmpf = z2; z2 = z3; z3 = tmpf;
-	}
-
-	if (y3 < 0 || y1 >= d->ysize)
-		return;
-
-	double dx12 = (y2-y1 != 0) ? ( (x2 - x1) / (double)(y2 - y1) ) : 0.0;
-	double dx13 = (y3-y1 != 0) ? ( (x3 - x1) / (double)(y3 - y1) ) : 0.0;
-	double dx23 = (y3-y2 != 0) ? ( (x3 - x2) / (double)(y3 - y2) ) : 0.0;
-
-	double dz12 = (y2-y1 != 0) ? ( (z2 - z1) / (double)(y2 - y1) ) : 0.0;
-	double dz13 = (y3-y1 != 0) ? ( (z3 - z1) / (double)(y3 - y1) ) : 0.0;
-	double dz23 = (y3-y2 != 0) ? ( (z3 - z2) / (double)(y3 - y2) ) : 0.0;
-
-	double dr12 = (y2-y1 != 0) ? ( (r2 - r1) / (double)(y2 - y1) ) : 0.0;
-	double dr13 = (y3-y1 != 0) ? ( (r3 - r1) / (double)(y3 - y1) ) : 0.0;
-	double dr23 = (y3-y2 != 0) ? ( (r3 - r2) / (double)(y3 - y2) ) : 0.0;
-
-	double dg12 = (y2-y1 != 0) ? ( (g2 - g1) / (double)(y2 - y1) ) : 0.0;
-	double dg13 = (y3-y1 != 0) ? ( (g3 - g1) / (double)(y3 - y1) ) : 0.0;
-	double dg23 = (y3-y2 != 0) ? ( (g3 - g2) / (double)(y3 - y2) ) : 0.0;
-
-	double db12 = (y2-y1 != 0) ? ( (b2 - b1) / (double)(y2 - y1) ) : 0.0;
-	double db13 = (y3-y1 != 0) ? ( (b3 - b1) / (double)(y3 - y1) ) : 0.0;
-	double db23 = (y3-y2 != 0) ? ( (b3 - b2) / (double)(y3 - y2) ) : 0.0;
-
-	double startx = x1, startz = z1, startr = r1, startg = g1, startb = b1;
-	double stopx = x1, stopz = z1, stopr = r1, stopg = g1, stopb = b1;
-	for (int y = y1; y < y2; ++y)
-	{
-		simpleline(d, y, startx, stopx, startz, stopz, startr, stopr, startg, stopg, startb, stopb);
-		startx += dx13; startz += dz13; startr += dr13; startg += dg13; startb += db13;
-		stopx += dx12; stopz += dz12; stopr += dr12; stopg += dg12; stopb += db12;
-	}
-
-	stopx = x2; stopz = z2; stopr = r2; stopg = g2; stopb = b2;
-	for (int y = y2; y < y3; ++y)
-	{
-		simpleline(d, y, startx, stopx, startz, stopz, startr, stopr, startg, stopg, startb, stopb);
-		startx += dx13; startz += dz13; startr += dr13; startg += dg13; startb += db13;
-		stopx += dx23; stopz += dz23; stopr += dr23; stopg += dg23; stopb += db23;
-	}
-
-#ifdef DEBUG_RENDER_AS_WIRE_FRAME
-	// Wire-frame test:
-	line(d, x1, y1, x2, y2);
-	line(d, x1, y1, x3, y3);
-	line(d, x2, y2, x3, y3);
-#endif
-}
-
-
-// Slow software rendering, for debugging:
-static void pvr_render_triangle_textured(struct pvr_data *d,
-	int texture_pixelformat, bool twiddled, int stride,
-	int texture, int texture_xsize, int texture_ysize,
-	int x1, int y1, double z1, double u1, double v1,
-	int x2, int y2, double z2, double u2, double v2,
-	int x3, int y3, double z3, double u3, double v3)
-{
-	// Easiest if 1, 2, 3 are in order top to bottom.
-	if (y2 < y1) {
-		int tmp = x1; x1 = x2; x2 = tmp;
-		tmp = y1; y1 = y2; y2 = tmp;
-		double tmpf = z1; z1 = z2; z2 = tmpf;
-		tmpf = u1; u1 = u2; u2 = tmpf;
-		tmpf = v1; v1 = v2; v2 = tmpf;
-	}
-
-	if (y3 < y1) {
-		int tmp = x1; x1 = x3; x3 = tmp;
-		tmp = y1; y1 = y3; y3 = tmp;
-		double tmpf = z1; z1 = z3; z3 = tmpf;
-		tmpf = u1; u1 = u3; u3 = tmpf;
-		tmpf = v1; v1 = v3; v3 = tmpf;
-	}
-
-	if (y3 < y2) {
-		int tmp = x2; x2 = x3; x3 = tmp;
-		tmp = y2; y2 = y3; y3 = tmp;
-		double tmpf = z2; z2 = z3; z3 = tmpf;
-		tmpf = u2; u2 = u3; u3 = tmpf;
-		tmpf = v2; v2 = v3; v3 = tmpf;
-	}
-
-	if (y3 < 0 || y1 >= d->ysize)
-		return;
-
-	double dx12 = (y2-y1 != 0) ? ( (x2 - x1) / (double)(y2 - y1) ) : 0.0;
-	double dx13 = (y3-y1 != 0) ? ( (x3 - x1) / (double)(y3 - y1) ) : 0.0;
-	double dx23 = (y3-y2 != 0) ? ( (x3 - x2) / (double)(y3 - y2) ) : 0.0;
-
-	double dz12 = (y2-y1 != 0) ? ( (z2 - z1) / (double)(y2 - y1) ) : 0.0;
-	double dz13 = (y3-y1 != 0) ? ( (z3 - z1) / (double)(y3 - y1) ) : 0.0;
-	double dz23 = (y3-y2 != 0) ? ( (z3 - z2) / (double)(y3 - y2) ) : 0.0;
-
-	double du12 = (y2-y1 != 0) ? ( (u2 - u1) / (double)(y2 - y1) ) : 0.0;
-	double du13 = (y3-y1 != 0) ? ( (u3 - u1) / (double)(y3 - y1) ) : 0.0;
-	double du23 = (y3-y2 != 0) ? ( (u3 - u2) / (double)(y3 - y2) ) : 0.0;
-
-	double dv12 = (y2-y1 != 0) ? ( (v2 - v1) / (double)(y2 - y1) ) : 0.0;
-	double dv13 = (y3-y1 != 0) ? ( (v3 - v1) / (double)(y3 - y1) ) : 0.0;
-	double dv23 = (y3-y2 != 0) ? ( (v3 - v2) / (double)(y3 - y2) ) : 0.0;
-
-	double startx = x1, startz = z1, startu = u1, startv = v1;
-	double stopx = x1, stopz = z1, stopu = u1, stopv = v1;
-
-	for (int y = y1; y < y2; ++y)
-	{
-		texturedline(d, texture_pixelformat, twiddled, stride, texture, texture_xsize, texture_ysize, y, startx, stopx, startz, stopz, startu, stopu, startv, stopv);
-		startx += dx13; startz += dz13; startu += du13; startv += dv13;
-		stopx += dx12; stopz += dz12; stopu += du12; stopv += dv12;
-	}
-
-	stopx = x2; stopz = z2; stopu = u2; stopv = v2;
-	for (int y = y2; y < y3; ++y)
-	{
-		texturedline(d, texture_pixelformat, twiddled, stride, texture, texture_xsize, texture_ysize, y, startx, stopx, startz, stopz, startu, stopu, startv, stopv);
-		startx += dx13; startz += dz13; startu += du13; startv += dv13;
-		stopx += dx23; stopz += dz23; stopu += du23; stopv += dv23;
-	}
-
-#ifdef DEBUG_RENDER_AS_WIRE_FRAME
-	// Wire-frame test:
-	line(d, x1, y1, x2, y2);
-	line(d, x1, y1, x3, y3);
-	line(d, x2, y2, x3, y3);
-#endif
-}
-
-
-static void pvr_clear_ta_commands(struct pvr_data* d)
-{
-	d->n_ta_commands = 0;
-}
-
-
-/*
- *  pvr_render():
- *
- *  Render from the Object Buffer to the framebuffer.
- *
- *  TODO: This function is totally bogus so far, the format of the Object
- *        Buffer is just a quick made-up hack to see if it works at all.
- */
-void pvr_render(struct cpu *cpu, struct pvr_data *d)
-{
-	int fb_render_cfg = REG(PVRREG_FB_RENDER_CFG);
-	int fb_base = REG(PVRREG_FB_RENDER_ADDR1);
-
-	if ((fb_render_cfg & FB_RENDER_CFG_RENDER_MODE_MASK) != 0x1) {
-		printf("pvr: only RGB565 rendering has been implemented\n");
-		exit(1);
-	}
-
-	// Settings for the current polygon being rendered:
-	// Word 0:
-	int listtype = 0;
-	int striplength = 0;
-	int clipmode;
-	int modifier;
-	int modifier_mode;
-	int color_type = 0;
-	bool texture = false;
-	bool specular;
-	bool shading;
-	bool uv_format;
-
-	// Word 1:
-	int depthmode;
-	int cullingmode = 0;
-	bool zwrite;
-	bool texture1;
-	bool specular1;
-	bool shading1;
-	bool uv_format1;
-	bool dcalcexact;
-
-	// Word 2:
-	int fog = 0;
-	int texture_usize = 0, texture_vsize = 0;
-
-	// Word 3:
-	bool texture_mipmap = false;
-	bool texture_vq_compression = false;
-	int texture_pixelformat = 0;
-	bool texture_twiddled = false;
-	bool texture_stride = false;
-	uint32_t textureAddr = 0;
-
-	int vertex_index = 0;
-	int wf_x[4], wf_y[4]; double wf_z[4], wf_u[4], wf_v[4];
-	int wf_r[4], wf_g[4], wf_b[4];
-
-	double baseRed = 0.0, baseGreen = 0.0, baseBlue = 0.0;
-
-	debug("[ pvr_render: rendering to FB offset 0x%x, "
-	    "%i Tile Accelerator commands ]\n", fb_base, d->n_ta_commands);
-
-	/*
-	 *  Clear all pixels first.
-	 *  TODO: Maybe only clear the specific tiles that are in use by
-	 *  the tile accelerator?
-	 *  TODO: What background color to use? See KOS' pvr_misc.c for
-	 *  how KOS sets the background.
-	 */
-	memset(d->vram + fb_base, 0x00, d->xsize * d->ysize * d->bytes_per_pixel);
-
-	/*  Clear Z as well:  */
-	if (d->vram_z == NULL) {
-		d->vram_z = (double*) malloc(sizeof(double) * d->xsize * d->ysize);
-	}
-
-	uint32_t bgplaneZ = REG(PVRREG_BGPLANE_Z);
-	struct ieee_float_value backgroundz;
-	ieee_interpret_float_value(bgplaneZ, &backgroundz, IEEE_FMT_S);
-	for (int q = 0; q < d->xsize * d->ysize; ++q)
-		d->vram_z[q] = backgroundz.f;
-
-	// Using names from http://www.ludd.luth.se/~jlo/dc/ta-intro.txt.
-	for (size_t index = 0; index < d->n_ta_commands; ++index) {
-		// list points to 8 or 16 words.
-		uint32_t* list = &d->ta_commands[index * 16];
-		int cmd = (list[0] >> 29) & 7;
-
-		switch (cmd)
-		{
-		case 0:	// END_OF_LIST
-			// Interrupt event already triggered in pvr_ta_command().
-#ifdef TA_DEBUG
-			fatal("\nTA end_of_list (list type %i)\n", d->current_list_type);
-#endif
-			break;
-
-		case 1:	// USER_CLIP
-			// TODO: Ignoring for now.
-			break;
-
-		case 4:	// polygon or modifier volume
-		{
-			vertex_index = 0;
-
-			// List Word 0:
-			listtype = (list[0] >> 24) & 7;
-			striplength = (list[0] >> 18) & 3;
-			striplength = striplength == 2 ? 4 : (
-			    striplength == 3 ? 6 : (striplength + 1));
-			clipmode = (list[0] >> 16) & 3;
-			modifier = (list[0] >> 7) & 1;
-			modifier_mode = (list[0] >> 6) & 1;
-			color_type = (list[0] >> 4) & 3;
-			texture = list[0] & 8;
-			specular = list[0] & 4;
-			shading = list[0] & 2;
-			uv_format = list[0] & 1;
-
-#ifdef TA_DEBUG
-			fatal("\nTA polygon  listtype %i, ", listtype);
-			fatal("striplength %i, ", striplength);
-			fatal("clipmode %i, ", clipmode);
-			fatal("modifier %i, ", modifier);
-			fatal("modifier_mode %i,\n", modifier_mode);
-			fatal("            color_type %i, ", color_type);
-			fatal("texture %s, ", texture ? "TRUE" : "false");
-			fatal("specular %s, ", specular ? "TRUE" : "false");
-			fatal("shading %s, ", shading ? "TRUE" : "false");
-			fatal("uv_format %s\n", uv_format ? "TRUE" : "false");
-#endif
-
-			// List Word 1:
-			depthmode = (list[1] >> 29) & 7;
-			cullingmode = (list[1] >> 27) & 3;
-			zwrite = ! ((list[1] >> 26) & 1);
-			texture1 = (list[1] >> 25) & 1;
-			specular1 = (list[1] >> 24) & 1;
-			shading1 = (list[1] >> 23) & 1;
-			uv_format1 = (list[1] >> 22) & 1;
-			dcalcexact = (list[1] >> 20) & 1;
-
-#ifdef TA_DEBUG
-			fatal("            depthmode %i, ", depthmode);
-			fatal("cullingmode %i, ", cullingmode);
-			fatal("zwrite %s, ", zwrite ? "TRUE" : "false");
-			fatal("texture1 %s\n", texture1 ? "TRUE" : "false");
-			fatal("            specular1 %s, ", specular1 ? "TRUE" : "false");
-			fatal("shading1 %s, ", shading1 ? "TRUE" : "false");
-			fatal("uv_format1 %s, ", uv_format1 ? "TRUE" : "false");
-			fatal("dcalcexact %s\n", dcalcexact ? "TRUE" : "false");
-#endif
-
-			if (!zwrite) {
-				fatal("pvr: no zwrite? not implemented yet.\n");
-				exit(1);
-			}
-
-			// For now, trust texture and ignore texture1.
-			// if (texture != texture1) {
-			//	fatal("pvr: texture != texture1. what to do?\n");
-			//	exit(1);
-			// }
-
-			// List Word 2:
-			// TODO: srcblend (31-29)
-			// TODO: dstblend (28-26)
-			// TODO: srcmode (25)
-			// TODO: dstmode (24)
-			fog = (list[2] >> 22) & 3;
-			// TODO: clamp (21)
-			// TODO: alpha (20)
-			// TODO: texture alpha (19)
-			// TODO: uv flip (18-17)
-			// TODO: uv clamp (16-15)
-			// TODO: filter (14-12)
-			// TODO: mipmap (11-8)
-			// TODO: texture shading (7-6)
-			texture_usize = 8 << ((list[2] >> 3) & 7);
-			texture_vsize = 8 << (list[2] & 7);
-
-			// List Word 3:
-			texture_mipmap = (list[3] >> 31) & 1;
-			texture_vq_compression = (list[3] >> 30) & 1;
-			texture_pixelformat = (list[3] >> 27) & 7;
-			texture_twiddled = ! ((list[3] >> 26) & 1);
-			texture_stride = (list[3] >> 25) & 1;
-			textureAddr = (list[3] << 3) & 0x7fffff;
-
-#ifdef TA_DEBUG
-			fatal("            texture: mipmap %s, ", texture_mipmap ? "TRUE" : "false");
-			fatal("vq_compression %s, ", texture_vq_compression ? "TRUE" : "false");
-			fatal("pixelformat %i, ", texture_pixelformat);
-			fatal("twiddled %s\n", texture_twiddled ? "TRUE" : "false");
-			fatal("            stride %s, ", texture_stride ? "TRUE" : "false");
-			fatal("textureAddr 0x%08x\n", textureAddr);
-#endif
-
-			if (fog != 2)
-				fatal("[ pvr: fog type %i not yet implemented ]\n", fog);
-
-			if (texture_vq_compression) {
-				fatal("pvr: texture_vq_compression not supported yet\n");
-				// exit(1);
-			}
-
-			struct ieee_float_value r, g, b;
-			ieee_interpret_float_value(list[5], &r, IEEE_FMT_S);
-			ieee_interpret_float_value(list[6], &g, IEEE_FMT_S);
-			ieee_interpret_float_value(list[7], &b, IEEE_FMT_S);
-			baseRed = r.f * 255;
-			baseGreen = g.f * 255;
-			baseBlue = b.f * 255;
-			// printf("rgb = %f %f %f\n", r.f, g.f, b.f);
-			break;
-		}
-
-		case 7:	// vertex
-		{
-			// MAJOR TODO:
-			// How to select which one of the 18 (!) types listed
-			// in http://www.ludd.luth.se/~jlo/dc/ta-intro.txt to
-			// use?
-			if (listtype != 0 && listtype != 2 && listtype != 4)
-				break;
-
-			bool eos = (list[0] >> 28) & 1;
-
-			struct ieee_float_value fx, fy, fz, u, v, extra1, extra2;
-			ieee_interpret_float_value(list[1], &fx, IEEE_FMT_S);
-			ieee_interpret_float_value(list[2], &fy, IEEE_FMT_S);
-			ieee_interpret_float_value(list[3], &fz, IEEE_FMT_S);
-			wf_x[vertex_index] = fx.f;
-			wf_y[vertex_index] = fy.f;
-			wf_z[vertex_index] = fz.f;
-
-#ifdef TA_DEBUG
-			fatal("TA vertex   %f %f %f%s\n", fx.f, fy.f, fz.f,
-				eos ? " end_of_strip" : "");
-#endif
-
-			if (texture) {
-				ieee_interpret_float_value(list[4], &u, IEEE_FMT_S);
-				ieee_interpret_float_value(list[5], &v, IEEE_FMT_S);
-				wf_u[vertex_index] = u.f;
-				wf_v[vertex_index] = v.f;
-			} else {
-				if (color_type == 0) {
-					wf_r[vertex_index] = (list[6] >> 16) & 255;
-					wf_g[vertex_index] = (list[6] >> 8) & 255;
-					wf_b[vertex_index] = (list[6]) & 255;
-				} else if (color_type == 1) {
-					ieee_interpret_float_value(list[5], &v, IEEE_FMT_S);
-					ieee_interpret_float_value(list[6], &extra1, IEEE_FMT_S);
-					ieee_interpret_float_value(list[7], &extra2, IEEE_FMT_S);
-					wf_r[vertex_index] = v.f * 255;
-					wf_g[vertex_index] = extra1.f * 255;
-					wf_b[vertex_index] = extra2.f * 255;
-				} else if (color_type == 2) {
-					ieee_interpret_float_value(list[6], &extra1, IEEE_FMT_S);
-					wf_r[vertex_index] = extra1.f * baseRed;
-					wf_g[vertex_index] = extra1.f * baseGreen;
-					wf_b[vertex_index] = extra1.f * baseBlue;
-				} else {
-					// "Intensity from previous face". TODO. Red for now.
-					wf_r[vertex_index] = 255;
-					wf_g[vertex_index] = 0;
-					wf_b[vertex_index] = 0;
-				}
-			}
-
-			vertex_index ++;
-
-			if (vertex_index >= 3) {
-				int modulo_mask = REG(PVRREG_TSP_CFG) & TSP_CFG_MODULO_MASK;
-
-				float crossProduct =
-					((wf_x[1] - wf_x[0])*(wf_y[2] - wf_y[0])) -
-					((wf_y[1] - wf_y[0])*(wf_x[2] - wf_x[0]));
-
-				// Hm. TODO: Instead of flipping back and forth between
-				// clockwise and counter-clockwise culling, perhaps there
-				// is some smarter way of assigning the three points
-				// instead of 012 => 12x...?
-				bool culled = false;
-				if (cullingmode == 2) {
-					if (crossProduct < 0)
-						culled = true;
-					cullingmode = 3;
-				} else if (cullingmode == 3) {
-					if (crossProduct > 0)
-						culled = true;
-					cullingmode = 2;
-				}
-
-				if (!culled) {
-					if (texture)
-						pvr_render_triangle_textured(d,
-						    texture_pixelformat, texture_twiddled, texture_stride ? (32*modulo_mask) : 0,
-						    textureAddr, texture_usize, texture_vsize,
-						    wf_x[0], wf_y[0], wf_z[0], wf_u[0], wf_v[0],
-						    wf_x[1], wf_y[1], wf_z[1], wf_u[1], wf_v[1],
-						    wf_x[2], wf_y[2], wf_z[2], wf_u[2], wf_v[2]);
-					else
-						pvr_render_triangle(d,
-						    wf_x[0], wf_y[0], wf_z[0], wf_r[0], wf_g[0], wf_b[0],
-						    wf_x[1], wf_y[1], wf_z[1], wf_r[1], wf_g[1], wf_b[1],
-						    wf_x[2], wf_y[2], wf_z[2], wf_r[2], wf_g[2], wf_b[2]);
-				}
-
-				if (eos) {
-					// End of strip.
-					vertex_index = 0;
-				} else {
-					// Not a closing vertex, then move points 1 and 2
-					// into slots 0 and 1, so that the stripe can continue.
-					vertex_index = 2;
-					wf_x[0] = wf_x[1]; wf_y[0] = wf_y[1]; wf_z[0] = wf_z[1];
-					wf_u[0] = wf_u[1]; wf_v[0] = wf_v[1];
-					wf_r[0] = wf_r[1]; wf_g[0] = wf_g[1]; wf_b[0] = wf_b[1];
-					
-					wf_x[1] = wf_x[2]; wf_y[1] = wf_y[2]; wf_z[1] = wf_z[2];
-					wf_u[1] = wf_u[2]; wf_v[1] = wf_v[2];
-					wf_r[1] = wf_r[2]; wf_g[1] = wf_g[2]; wf_b[1] = wf_b[2];
-				}
-			}
-			break;
-		}
-
-		default:
-			fatal("pvr_render: unimplemented list cmd %i\n", cmd);
-			exit(1);
-		}
-	}
-
-	pvr_clear_ta_commands(d);
-	
-	// TODO: RENDERDONE is 2. How about other events?
-	SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_RENDERDONE);
-}
-
-
-/*
- *  pvr_reset_ta():
- *
- *  Reset the Tile Accelerator.
- */
-static void pvr_reset_ta(struct pvr_data *d)
-{
-	REG(PVRREG_DIWCONF) = DIWCONF_MAGIC;
-	pvr_clear_ta_commands(d);
-}
-
-
-/*
- *  pvr_reset():
- *
- *  Reset the PVR.
- */
-static void pvr_reset(struct pvr_data *d)
-{
-	/*  TODO  */
-}
-
-
-/*
- *  pvr_ta_init():
- *
- *  Initialize the Tile Accelerator. This makes the TA ready to receive
- *  commands (via address 0x10000000).
- */
-void pvr_ta_init(struct cpu *cpu, struct pvr_data *d)
-{
-	REG(PVRREG_TA_OPB_POS) = REG(PVRREG_TA_OPB_START);
-	REG(PVRREG_TA_OB_POS) = REG(PVRREG_TA_OB_START);
-}
-
-
-static void pvr_tilebuf_debugdump(struct pvr_data *d)
-{
-	return;
-
-	// According to Marcus Comstedt's "tatest":
-	// 24 word header (before the TILEBUF_ADDR pointer), followed by
-	// 6 words for each tile.
-	uint32_t tilebuf = REG(PVRREG_TILEBUF_ADDR) & PVR_TILEBUF_ADDR_MASK;
-
-	// TODO: endianness
-	uint32_t *p = (uint32_t*) (d->vram + tilebuf);
-
-	fatal("PVR tile buffer debug dump:\n");
-	p -= 24;
-	for (int i = 0; i < 24; ++i)
-		fatal("  %08x", *p++);
-
-	fatal("\n%i x %i tiles:\n", d->tilebuf_xsize, d->tilebuf_ysize);
-
-	for (int x = 0; x < d->tilebuf_xsize; ++x)
-	{
-		for (int y = 0; y < d->tilebuf_ysize; ++y)
-		{
-			fatal("  Tile %i,%i:", x, y);
-			for (int i = 0; i < 6; ++i)
-				fatal(" %08x", *p++);
-			fatal("\n");
-		}
-	}
-}
-
-
-/*
- *  pvr_ta_command():
- *
- *  Someone has written a [complete] 32-byte or 64-byte command to the Tile
- *  Accelerator memory area. The real hardware probably outputs
- *  "compiled commands" into the Object list and Object Pointer list.
- *  For now, just put all the commands in a plain array, and then later execute
- *  them in pvr_render().
- */
-static void pvr_ta_command(struct cpu *cpu, struct pvr_data *d, int list_ofs)
-{
-	uint32_t *ta = &d->ta[list_ofs];
-
-#ifdef TA_DEBUG
-	/*  Dump the Tile Accelerator command for debugging:  */
-	{
-		int i;
-		fatal("TA cmd:");
-		for (i = 0; i < 8; ++i)
-			fatal(" %08x", (int) ta[i]);
-		fatal("\n");
-	}
-#endif
-
-	// ob_ofs = REG(PVRREG_TA_OB_POS);
-	// REG(PVRREG_TA_OB_POS) = ob_ofs + sizeof(uint64_t);
-
-	if (d->ta_commands == NULL) {
-		d->allocated_ta_commands = 2048;
-		d->ta_commands = (uint32_t *) malloc(64 * d->allocated_ta_commands);
-		d->n_ta_commands = 0;
-	}
-
-	if (d->n_ta_commands + 1 >= d->allocated_ta_commands) {
-		d->allocated_ta_commands *= 2;
-		d->ta_commands = (uint32_t *) realloc(d->ta_commands, 64 * d->allocated_ta_commands);
-	}
-
-	// Hack: I don't understand yet what separates a 32-byte transfer
-	// vs two individual 32-byte transfers vs a 64-byte transfer.
-	// TODO: For now, really only support 32-byte transfers... :(
-	memcpy(d->ta_commands + 16 * d->n_ta_commands, ta, 32);
-	memset(d->ta_commands + 16 * d->n_ta_commands + 8, 0, 32);
-	d->n_ta_commands ++;
-
-	// We need to keep track of the current list type though, and respond
-	// with an event once we reach an end_of_list command. All other
-	// commands are handled in pvr_render() for now.
-	int cmd = (ta[0] >> 29) & 7;
-	if (cmd == 0) {
-		// cmd 0: end of list
-		uint32_t opb_cfg = REG(PVRREG_TA_OPB_CFG);
-
-		if (d->current_list_type == 0 && opb_cfg & TA_OPB_CFG_OPAQUEPOLY_MASK)
-			SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_OPAQUEDONE);
-		if (d->current_list_type == 1 && opb_cfg & TA_OPB_CFG_OPAQUEMOD_MASK)
-			SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_OPAQUEMODDONE);
-		if (d->current_list_type == 2 && opb_cfg & TA_OPB_CFG_TRANSPOLY_MASK)
-			SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_TRANSDONE);
-		if (d->current_list_type == 3 && opb_cfg & TA_OPB_CFG_TRANSMOD_MASK)
-			SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_TRANSMODDONE);
-		if (d->current_list_type == 4 && opb_cfg & TA_OPB_CFG_PUNCHTHROUGH_MASK)
-			SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_PVR_PTDONE);
-	} else if (cmd == 4) {
-		// cmd 4: polygon or modifier volume
-		d->current_list_type = (ta[0] >> 24) & 7;
-	}
-}
-
-
-DEVICE_ACCESS(pvr_ta)
-{
-	struct pvr_data *d = (struct pvr_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (len != sizeof(uint32_t)) {
-		fatal("pvr_ta access len = %i: TODO\n", (int) len);
-		exit(1);
-	}
-
-	// Tile Accelerator commands can be sent to 0x10000000 through
-	// 0x107fffff, it seems, but the SH4 store queues only have 64 bytes.
-	relative_addr &= (sizeof(d->ta) - 1);
-
-	if (writeflag == MEM_WRITE) {
-		idata = memory_readmax64(cpu, data, len);
-#if 0
-		fatal("[ pvr_ta: WRITE addr=%08x value=%08x ]\n",
-		    (int)relative_addr, (int)idata);
-#endif
-
-		/*  Write to the tile accelerator command buffer:  */
-		d->ta[relative_addr / sizeof(uint32_t)] = idata;
-
-		// Execute the command, after a complete write.
-		// (Note: This assumes that commands are written from low
-		// address to high.)
-		if (relative_addr == 0x1c)
-			pvr_ta_command(cpu, d, 0);
-		if (relative_addr == 0x3c)
-			pvr_ta_command(cpu, d, 8);
-	} else {
-		odata = d->ta[relative_addr / sizeof(uint32_t)];
-		memory_writemax64(cpu, data, len, odata);
-#if 1
-		fatal("[ pvr_ta: READ addr=%08x value=%08x ]\n", (int)relative_addr, (int)odata);
-#endif
-	}
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(pvr)
-{
-	struct pvr_data *d = (struct pvr_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  Default read action: Read from reg[]:  */
-	if (writeflag == MEM_READ)
-		odata = d->reg[relative_addr / sizeof(uint32_t)];
-
-	/*  Fog table access:  */
-	if (relative_addr >= PVRREG_FOG_TABLE &&
-	    relative_addr < PVRREG_FOG_TABLE + PVR_FOG_TABLE_SIZE) {
-		if (writeflag == MEM_WRITE)
-			DEFAULT_WRITE;
-		goto return_ok;
-	}
-
-	/*  Palette access:  */
-	if (relative_addr >= PVRREG_PALETTE &&
-	    relative_addr < PVRREG_PALETTE + PVR_PALETTE_SIZE) {
-		if (writeflag == MEM_WRITE)
-			DEFAULT_WRITE;
-		goto return_ok;
-	}
-
-	switch (relative_addr) {
-
-	case PVRREG_ID:
-		/*  ID for Set 5.xx versions of the Dreamcast, according
-		    to http://www.ludd.luth.se/~jlo/dc/powervr-reg.txt:  */
-		odata = 0x17fd11db;
-		break;
-
-	case PVRREG_REVISION:
-		/*  Revision 1.1, for Dreamcast Set 5.2x.  */
-		odata = 0x00000011;
-		break;
-
-	case PVRREG_RESET:
-		if (writeflag == MEM_WRITE) {
-			if (idata != 0) {
-				debug("[ pvr: RESET ");
-				if (idata & PVR_RESET_PVR)
-					pvr_reset(d);
-				if (idata & PVR_RESET_TA)
-					pvr_reset_ta(d);
-				debug("]\n");
-			}
-			idata = 0;
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_STARTRENDER:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: STARTRENDER ]\n");
-			pvr_render(cpu, d);
-		} else {
-			fatal("[ pvr: huh? read from STARTRENDER ]\n");
-			exit(1);
-		}
-		break;
-
-	case PVRREG_OB_ADDR:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: OB_ADDR set to 0x%08" PRIx32" ]\n",
-			    (uint32_t)(idata & PVR_OB_ADDR_MASK));
-			if (idata & ~PVR_OB_ADDR_MASK) {
-				fatal("[ pvr: OB_ADDR: Fatal error: Unknown"
-				    " bits set: 0x%08" PRIx32" ]\n",
-				    (uint32_t)(idata & ~PVR_OB_ADDR_MASK));
-				exit(1);
-			}
-			idata &= PVR_OB_ADDR_MASK;
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TILEBUF_ADDR:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: TILEBUF_ADDR set to 0x%08" PRIx32" ]\n",
-			    (uint32_t)(idata & PVR_TILEBUF_ADDR_MASK));
-			if (idata & ~PVR_TILEBUF_ADDR_MASK) {
-				fatal("[ pvr: TILEBUF_ADDR: Unknown"
-				    " bits set: 0x%08" PRIx32" ]\n",
-				    (uint32_t)(idata & ~PVR_TILEBUF_ADDR_MASK));
-				exit(1);
-			}
-			idata &= PVR_TILEBUF_ADDR_MASK;
-			DEFAULT_WRITE;
-			pvr_tilebuf_debugdump(d);
-		}
-		break;
-
-	case PVRREG_SPANSORT:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: SPANSORT: ");
-			if (idata & PVR_SPANSORT_SPAN0)
-				debug("SPAN0 ");
-			if (idata & PVR_SPANSORT_SPAN1)
-				debug("SPAN1 ");
-			if (idata & PVR_SPANSORT_TSP_CACHE_ENABLE)
-				debug("TSP_CACHE_ENABLE ");
-			debug("]\n");
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_BRDCOLR:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: BRDCOLR set to 0x%06" PRIx32" ]\n",
-			    (int)idata);
-			DEFAULT_WRITE;
-			d->border_updated = 1;
-		}
-		break;
-
-	case PVRREG_DIWMODE:
-		if (writeflag == MEM_WRITE) {
-			d->clock_double = idata & DIWMODE_C_MASK? 1:0;
-			d->strip_buffer_enabled = idata & DIWMODE_SE_MASK? 1:0;
-			d->strip_length = (idata & DIWMODE_SL_MASK)
-			    >> DIWMODE_SL_SHIFT;
-			d->argb8888_threshold = (idata & DIWMODE_TH_MASK)
-			    >> DIWMODE_TH_SHIFT;
-			d->extend = (idata & DIWMODE_EX_MASK)
-			    >> DIWMODE_EX_SHIFT;
-			d->pixelmode = (idata & DIWMODE_COL_MASK)
-			    >> DIWMODE_COL_SHIFT;
-			d->line_double = idata & DIWMODE_SD_MASK? 1:0;
-			d->display_enabled = idata & DIWMODE_DE_MASK? 1:0;
-
-			debug("[ pvr: DIWMODE set to: ");
-			debug("clock_double=%i, ", d->clock_double);
-			debug("strip_buffer_enabled=%i, ",
-			    d->strip_buffer_enabled);
-			debug("strip_length=%i, ", d->strip_length);
-			debug("argb8888_threshold=%i, ", d->argb8888_threshold);
-			debug("extend=0x%x, ", d->extend);
-			debug("pixelmode=");
-			switch (d->pixelmode) {
-			case 0: debug("RGB0555 (16-bit)"); break;
-			case 1: debug("RGB565 (16-bit)"); break;
-			case 2: debug("RGB888 (24-bit)"); break;
-			case 3: debug("RGB0888 (32-bit)"); break;
-			}
-			debug(", line_double=%i, ", d->line_double);
-			debug("display_enabled=%i", d->display_enabled);
-			debug(" ]\n");
-
-			DEFAULT_WRITE;
-			pvr_geometry_updated(d);
-			pvr_fb_invalidate(d, -1, -1);
-		}
-		break;
-
-	case PVRREG_DIWSIZE:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: DIWSIZE set to modulo=%i, "
-			    "width=%i, height=%i ]\n", (int)
-			    ((idata >> DIWSIZE_MODULO_SHIFT) & DIWSIZE_MASK),
-			    (int)((idata >> DIWSIZE_DPL_SHIFT) & DIWSIZE_MASK),
-			    (int)((idata >> DIWSIZE_LPF_SHIFT) & DIWSIZE_MASK));
-			DEFAULT_WRITE;
-			pvr_geometry_updated(d);
-			pvr_fb_invalidate(d, -1, -1);
-		}
-		break;
-
-	case PVRREG_FB_RENDER_ADDR1:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: FB_RENDER_ADDR1 set to 0x%08" PRIx32
-			    " ]\n", (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_FB_RENDER_ADDR2:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: FB_RENDER_ADDR2 set to 0x%08" PRIx32
-			    " ]\n", (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_FB_CLIP_X:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: FB_CLIP_X set to min=%i, "
-			    "max=%i ]\n", (int) (idata & FB_CLIP_XY_MIN_MASK),
-			    (int) ((idata & FB_CLIP_XY_MAX_MASK)
-			    >> FB_CLIP_XY_MAX_SHIFT));
-			DEFAULT_WRITE;
-			pvr_geometry_updated(d);
-			pvr_fb_invalidate(d, -1, -1);
-		}
-		break;
-
-	case PVRREG_FB_CLIP_Y:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: FB_CLIP_Y set to min=%i, "
-			    "max=%i ]\n", (int) (idata & FB_CLIP_XY_MIN_MASK),
-			    (int) ((idata & FB_CLIP_XY_MAX_MASK)
-			    >> FB_CLIP_XY_MAX_SHIFT));
-			DEFAULT_WRITE;
-			pvr_geometry_updated(d);
-			pvr_fb_invalidate(d, -1, -1);
-		}
-		break;
-
-	case PVRREG_SHADOW:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: SHADOW set to enable=%i, "
-			    "intensity=%i ]\n",
-			    (int) (idata & SHADOW_ENABLE? 1 : 0),
-			    (int) (idata & SHADOW_INTENSITY_MASK));
-			DEFAULT_WRITE;
-			pvr_geometry_updated(d);
-			pvr_fb_invalidate(d, -1, -1);
-		}
-		break;
-
-	case PVRREG_OBJECT_CLIP:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: OBJECT_CLIP 0x%08x ]\n", (int)idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_OB_CFG:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: OB_CFG 0x%08x ]\n", (int)idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_UNKNOWN_80:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: UNKNOWN_80 0x%08x ]\n", (int)idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_UNKNOWN_84:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: UNKNOWN_84 0x%08x ]\n", (int)idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_BGPLANE_Z:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: BGPLANE_Z 0x%08x ]\n", (int)idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_BGPLANE_CFG:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: BGPLANE_CFG 0x%08x ]\n", (int)idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_ISP_CFG:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: ISP_CFG 0x%08x ]\n", (int)idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_VRAM_CFG1:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: VRAM_CFG1 set to 0x%08" PRIx32,
-			    (int) idata);
-			if (idata != VRAM_CFG1_GOOD_REFRESH_VALUE)
-				fatal("{ VRAM_CFG1 = 0x%08" PRIx32" is not "
-				    "yet implemented! }", (int) idata);
-			debug(" ]\n");
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_VRAM_CFG2:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: VRAM_CFG2 set to 0x%08" PRIx32,
-			    (int) idata);
-			if (idata != VRAM_CFG2_UNKNOWN_MAGIC)
-				fatal("{ VRAM_CFG2 = 0x%08" PRIx32" is not "
-				    "yet implemented! }", (int) idata);
-			debug(" ]\n");
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_VRAM_CFG3:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: VRAM_CFG3 set to 0x%08" PRIx32,
-			    (int) idata);
-			if (idata != VRAM_CFG3_UNKNOWN_MAGIC)
-				fatal("{ VRAM_CFG3 = 0x%08" PRIx32" is not "
-				    "yet implemented! }", (int) idata);
-			debug(" ]\n");
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_FOG_TABLE_COL:
-		// e.g. 0x007f7f7f
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: FOG_TABLE_COL set to 0x%06" PRIx32" ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_FOG_VERTEX_COL:
-		// e.g. 0x007f7f7f
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: FOG_VERTEX_COL set to 0x%06" PRIx32" ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_FOG_DENSITY:
-		// e.g. 0x0000ff07
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: FOG_DENSITY set to 0x%08" PRIx32" ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_CLAMP_MAX:
-		// e.g. 0xffffffff
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: CLAMP_MAX set to 0x%06" PRIx32" ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_CLAMP_MIN:
-		// e.g. 0x00000000
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: CLAMP_MIN set to 0x%06" PRIx32" ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_FB_RENDER_CFG:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: PVRREG_FB_RENDER_CFG set to 0x%08x ]\n",
-			    (int) idata);
-			/*  TODO  */
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_FB_RENDER_MODULO:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: PVRREG_FB_RENDER_MODULO set to %i ]\n",
-			    (int) idata);
-			/*  TODO  */
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_DIWADDRL:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: DIWADDRL set to 0x%08" PRIx32" ]\n",
-			    (int) idata);
-			pvr_fb_invalidate(d, -1, -1);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_DIWADDRS:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: DIWADDRS set to 0x%08" PRIx32" ]\n",
-			    (int) idata);
-			pvr_fb_invalidate(d, -1, -1);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_HPOS_IRQ:
-		DEFAULT_WRITE;
-		break;
-
-	case PVRREG_RASEVTPOS:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: RASEVTPOS pos1=%i pos2=%i ]\n",
-			    (int)((idata & RASEVTPOS_POS1_MASK)
-			    >> RASEVTPOS_POS1_SHIFT),
-			    (int)(idata & RASEVTPOS_POS2_MASK));
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_SYNCCONF:
-		if (writeflag == MEM_WRITE) {
-			d->video_enabled = idata & SYNCCONF_VO_MASK? 1:0;
-			d->broadcast_standard = (idata & SYNCCONF_BC_MASK)
-			    >> SYNCCONF_BC_SHIFT;
-			d->interlaced = idata & SYNCCONF_I_MASK? 1:0;
-			d->h_sync_positive = idata & SYNCCONF_HP_MASK? 1:0;
-			d->v_sync_positive = idata & SYNCCONF_VP_MASK? 1:0;
-
-			debug("[ pvr: SYNCCONF set to: ");
-			debug("video_enabled=%i, ", d->video_enabled);
-			switch (d->broadcast_standard) {
-			case SYNCCONF_BC_VGA: debug("VGA"); break;
-			case SYNCCONF_BC_NTSC: debug("NTSC"); break;
-			case SYNCCONF_BC_PAL: debug("PAL"); break;
-			default: debug("*UNKNOWN*"); break;
-			}
-			debug(", interlaced=%i, ", d->interlaced);
-			debug("hsync=%i, ", d->h_sync_positive);
-			debug("vsync=%i ]\n", d->v_sync_positive);
-
-			DEFAULT_WRITE;
-			pvr_geometry_updated(d);
-			pvr_fb_invalidate(d, -1, -1);
-		}
-		break;
-
-	case PVRREG_BRDHORZ:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: BRDHORZ start=%i stop=%i ]\n",
-			    (int)((idata & BRDHORZ_START_MASK)
-			    >> BRDHORZ_START_SHIFT),
-			    (int)(idata & BRDHORZ_STOP_MASK));
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_SYNCSIZE:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: SYNCSIZE v=%i h=%i ]\n",
-			    (int)((idata & SYNCSIZE_V_MASK)
-			    >> SYNCSIZE_V_SHIFT),
-			    (int)(idata & SYNCSIZE_H_MASK));
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_BRDVERT:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: BRDVERT start=%i stop=%i ]\n",
-			    (int)((idata & BRDVERT_START_MASK)
-			    >> BRDVERT_START_SHIFT),
-			    (int)(idata & BRDVERT_STOP_MASK));
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_SYNCH_WIDTH:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: SYNCH_WIDTH 0x%08x ]\n", (int)idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TSP_CFG:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: TSP_CFG 0x%08x ]\n", (int)idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_DIWCONF:
-		if (writeflag == MEM_WRITE) {
-			if ((idata & DIWCONF_MAGIC_MASK) !=
-			    DIWCONF_MAGIC && (idata & DIWCONF_MAGIC_MASK)
-			    != 0) {
-				fatal("PVRREG_DIWCONF magic not set to "
-				    "Magic value. 0x%08x\n", (int)idata);
-				exit(1);
-			}
-			if (idata & DIWCONF_BLANK)
-				debug("[ pvr: PVRREG_DIWCONF: BLANK: TODO ]\n");
-
-			DEFAULT_WRITE;
-			pvr_geometry_updated(d);
-		}
-		break;
-
-	case PVRREG_DIWHSTRT:
-		if (writeflag == MEM_WRITE) {
-			int v = idata & DIWVSTRT_HPOS_MASK;
-			debug("[ pvr: DIWHSTRT hpos=%i (%s) ]\n",
-			    v, v == 174? "PAL" :
-			    (v == 164? "NTSC" :
-			    (v == 144? "VGA" : "unknown!")));
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_DIWVSTRT:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: DIWVSTRT v2=%i v1=%i ]\n",
-			    (int)((idata & DIWVSTRT_V2_MASK)
-			    >> DIWVSTRT_V2_SHIFT),
-			    (int)(idata & DIWVSTRT_V1_MASK));
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_SCALER_CFG:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: SCALER_CFG 0x%08x ]\n", (int)idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_PALETTE_CFG:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: PALETTE_CFG 0x%08x ]\n", (int)idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_SYNC_STAT:
-		/*  TODO. Ugly hack, but it works:  */
-		odata = random();
-		break;
-
-	case PVRREG_MAGIC_110:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: MAGIC_110 set to 0x%08" PRIx32,
-			    (int) idata);
-			if (idata != MAGIC_110_VALUE)
-				fatal("{ MAGIC_110 = 0x%08" PRIx32" is not "
-				    "yet implemented! }", (int) idata);
-			debug(" ]\n");
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TA_LUMINANCE:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: TA_LUMINANCE set to 0x%08" PRIx32" ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TA_OPB_START:
-		if (writeflag == MEM_WRITE) {
-			if (idata & ~TA_OPB_START_MASK) {
-				fatal("[ pvr: UNEXPECTED bits in "
-				    "TA_OPB_START: 0x%08x ]\n", (int)idata);
-				exit(1);
-			}
-			idata &= TA_OPB_START_MASK;
-			debug("[ pvr: TA_OPB_START set to 0x%x ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TA_OB_START:
-		if (writeflag == MEM_WRITE) {
-			if (idata & ~TA_OB_START_MASK) {
-				fatal("[ pvr: UNEXPECTED bits in "
-				    "TA_OB_START: 0x%08x ]\n", (int)idata);
-				exit(1);
-			}
-			idata &= TA_OB_START_MASK;
-			debug("[ pvr: TA_OB_START set to 0x%x ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TA_OPB_END:
-		if (writeflag == MEM_WRITE) {
-			idata &= TA_OPB_END_MASK;
-			debug("[ pvr: TA_OPB_END set to 0x%x ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TA_OB_END:
-		if (writeflag == MEM_WRITE) {
-			idata &= TA_OB_END_MASK;
-			debug("[ pvr: TA_OB_END set to 0x%x ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TA_OPB_POS:
-		if (writeflag == MEM_WRITE) {
-			idata &= TA_OPB_POS_MASK;
-			debug("[ pvr: TA_OPB_POS set to 0x%x ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TA_OB_POS:
-		if (writeflag == MEM_WRITE) {
-			idata &= TA_OB_POS_MASK;
-			debug("[ pvr: TA_OB_POS set to 0x%x ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TA_OPL_INIT:
-		if (writeflag == MEM_WRITE) {
-			idata &= PVR_TA_OPL_INIT_MASK;
-			debug("[ pvr: TA_OPL_INIT set to 0x%x ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TILEBUF_SIZE:
-		if (writeflag == MEM_WRITE) {
-			d->tilebuf_ysize = (idata & TILEBUF_SIZE_HEIGHT_MASK)
-			    >> TILEBUF_SIZE_HEIGHT_SHIFT;
-			d->tilebuf_xsize = idata & TILEBUF_SIZE_WIDTH_MASK;
-			d->tilebuf_xsize ++; d->tilebuf_ysize ++;
-			debug("[ pvr: TILEBUF_SIZE set to %i x %i ]\n",
-			    d->tilebuf_xsize, d->tilebuf_ysize);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TA_OPB_CFG:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: TA_OPB_CFG set to 0x%x ]\n",
-			    (int) idata);
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_TA_INIT:
-		if (writeflag == MEM_WRITE) {
-			debug("[ pvr: TA_INIT ]\n");
-
-			if (idata & PVR_TA_INIT)
-				pvr_ta_init(cpu, d);
-
-			if (idata != PVR_TA_INIT && idata != 0)
-				fatal("{ TA_INIT = 0x%08" PRIx32" is not "
-				    "yet implemented! }", (int) idata);
-
-			/*  Always reset to 0.  */
-			idata = 0;
-			DEFAULT_WRITE;
-		}
-		break;
-
-	case PVRREG_YUV_STAT:
-		// TODO. The "luftvarg" demo accesses this register.
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ pvr: read from UNIMPLEMENTED addr 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ pvr: write to UNIMPLEMENTED addr 0x%x: 0x%x"
-			    " ]\n", (int)relative_addr, (int)idata);
-			DEFAULT_WRITE;
-		}
-
-		exit(1);
-	}
-
-return_ok:
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-void pvr_extend_update_region(struct pvr_data *d, uint64_t low, uint64_t high)
-{
-	int vram_ofs = REG(PVRREG_DIWADDRL);
-	int bytes_per_line = d->xsize * d->bytes_per_pixel;
-
-	low -= vram_ofs;
-	high -= vram_ofs;
-
-	/*  Access inside visible part of VRAM?  */
-	if ((int64_t)high >= 0 && (int64_t)low <
-	    bytes_per_line * d->ysize) {
-		int new_y1, new_y2;
-
-		d->fb_update_x1 = 0;
-		d->fb_update_x2 = d->xsize - 1;
-
-		/*  Calculate which line the low and high addresses
-		    correspond to:  */
-		new_y1 = low / bytes_per_line;
-		new_y2 = high / bytes_per_line + 1;
-
-		if (d->fb_update_y1 < 0 || new_y1 < d->fb_update_y1)
-			d->fb_update_y1 = new_y1;
-		if (d->fb_update_y2 < 0 || new_y2 > d->fb_update_y2)
-			d->fb_update_y2 = new_y2;
-
-		if (d->fb_update_y1 < 0)
-			d->fb_update_y1 = 0;
-		if (d->fb_update_y2 >= d->ysize)
-			d->fb_update_y2 = d->ysize - 1;
-	}
-}
-
-
-DEVICE_TICK(pvr_fb)
-{
-	struct pvr_data *d = (struct pvr_data *) extra;
-	uint64_t high, low = (uint64_t)(int64_t) -1;
-	int vram_ofs = REG(PVRREG_DIWADDRL), pixels_to_copy;
-	int bytes_per_line = d->xsize * d->bytes_per_pixel;
-	int fb_ofs, p;
-	uint8_t *fb = (uint8_t *) d->fb->framebuffer;
-	uint8_t *vram = (uint8_t *) d->vram;
-
-
-	/*
-	 *  Vertical retrace interrupts:
-	 *
-	 *  TODO: Maybe it would be even more realistic to have the timer run
-	 *        at, say, 60*4 = 240 Hz, and have the following events:
-	 *
-	 *	  (tick & 3) == 0	SYSASIC_EVENT_VBLINT
-	 *	  (tick & 3) == 1	SYSASIC_EVENT_PVR_SCANINT1
-	 *	  (tick & 3) == 2	nothing
-	 *	  (tick & 3) == 3	SYSASIC_EVENT_PVR_SCANINT2
-	 */
-	if (d->vblank_interrupts_pending > 0) {
-		-- d->vblank_interrupts_pending;
-
-		SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_VBLINT);
-		SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_PVR_SCANINT1);
-		
-		// Is this needed?
-		SYSASIC_TRIGGER_EVENT(SYSASIC_EVENT_PVR_SCANINT2);
-
-		/*  TODO: For now, I don't care about missed interrupts:  */
-		d->vblank_interrupts_pending = 0;
-	}
-
-
-	/*
-	 *  Framebuffer update:
-	 */
-
-	/*  Border changed?  */
-	if (d->border_updated) {
-		/*  Fill border with border color:  */
-		int rgb = REG(PVRREG_BRDCOLR), addr = 0;
-		int x, y, b = rgb & 0xff, g = (rgb >> 8) & 0xff, r = rgb >> 16;
-		int skiplen = (d->fb->xsize-2*PVR_MARGIN) * d->fb->bit_depth/8;
-
-		for (y=0; y<d->fb->ysize; y++) {
-			int xskip = y < PVR_MARGIN || y >=
-			    d->fb->ysize - PVR_MARGIN? -1 : PVR_MARGIN;
-			for (x=0; x<d->fb->xsize; x++) {
-				if (x == xskip) {
-					x = d->fb->xsize - PVR_MARGIN;
-					addr += skiplen;
-				}
-				fb[addr] = r;
-				fb[addr+1] = g;
-				fb[addr+2] = b;
-				addr += 3;
-			}
-		}
-
-		/*  Full redraw of the framebuffer:  */
-		d->fb->update_x1 = 0; d->fb->update_x2 = d->fb->xsize - 1;
-		d->fb->update_y1 = 0; d->fb->update_y2 = d->fb->ysize - 1;
-	}
-
-	memory_device_dyntrans_access(cpu, cpu->mem, extra, &low, &high);
-	if ((int64_t)low != -1)
-		pvr_extend_update_region(d, low, high);
-
-	if (d->fb_update_x1 == -1)
-		return;
-
-	/*  Copy (part of) the VRAM to the framebuffer:  */
-	if (d->fb_update_x2 >= d->xsize)
-		d->fb_update_x2 = d->xsize - 1;
-	if (d->fb_update_y2 >= d->ysize)
-		d->fb_update_y2 = d->ysize - 1;
-
-	vram_ofs += d->fb_update_y1 * bytes_per_line;
-	vram_ofs += d->fb_update_x1 * d->bytes_per_pixel;
-	pixels_to_copy = (d->fb_update_x2 - d->fb_update_x1 + 1);
-	fb_ofs = (d->fb_update_y1 + PVR_MARGIN) * d->fb->bytes_per_line;
-	fb_ofs += (d->fb_update_x1 + PVR_MARGIN) * d->fb->bit_depth / 8;
-
-	/*  Copy the actual pixels: (Four manually inlined, for speed.)  */
-
-	switch (d->pixelmode) {
-	case 0:	/*  RGB0555 (16-bit)  */
-		{
-			int y;
-			for (y=d->fb_update_y1; y<=d->fb_update_y2; y++) {
-				int fo = fb_ofs, vo = vram_ofs;
-				for (p=0; p<pixels_to_copy; p++) {
-					/*  0rrrrrgg(high) gggbbbbb(low)  */
-					fb[fo] = (vram[(vo+1)%VRAM_SIZE] << 1) & 0xf8;
-					fb[fo+1] = ((vram[vo%VRAM_SIZE] >> 2) & 0x38) +
-					    (vram[(vo+1)%VRAM_SIZE] << 6);
-					fb[fo+2] = (vram[vo%VRAM_SIZE] & 0x1f) << 3;
-					fo += 3; vo += 2;
-				}
-				
-				vram_ofs += bytes_per_line;
-				fb_ofs += d->fb->bytes_per_line;
-			}
-		}
-		break;
-
-	case 1: /*  RGB565 (16-bit)  */
-		{
-			int y;
-			for (y=d->fb_update_y1; y<=d->fb_update_y2; y++) {
-				int fo = fb_ofs, vo = vram_ofs;
-				for (p=0; p<pixels_to_copy; p++) {
-					/*  rrrrrggg(high) gggbbbbb(low)  */
-					fb[fo] = vram[(vo+1)%VRAM_SIZE] & 0xf8;
-					fb[fo+1] = ((vram[vo%VRAM_SIZE] >> 3) & 0x1c) +
-					    (vram[(vo+1)%VRAM_SIZE] << 5);
-					fb[fo+2] = (vram[vo%VRAM_SIZE] & 0x1f) << 3;
-					fo += 3; vo += 2;
-				}
-				
-				vram_ofs += bytes_per_line;
-				fb_ofs += d->fb->bytes_per_line;
-			}
-		}
-		break;
-
-	case 2: /*  RGB888 (24-bit)  */
-		{
-			int y;
-			for (y=d->fb_update_y1; y<=d->fb_update_y2; y++) {
-				/*  TODO: Reverse colors, like in the 32-bit case?  */
-				memcpy(fb+fb_ofs, vram+(vram_ofs%VRAM_SIZE), 3*pixels_to_copy);
-				vram_ofs += bytes_per_line;
-				fb_ofs += d->fb->bytes_per_line;
-			}
-		}
-		break;
-
-	case 3: /*  RGB0888 (32-bit)  */
-		{
-			int y;
-			for (y=d->fb_update_y1; y<=d->fb_update_y2; y++) {
-				int fo = fb_ofs, vo = vram_ofs;
-				for (p=0; p<pixels_to_copy; p++) {
-					fb[fo] = vram[(vo+2)%VRAM_SIZE];
-					fb[fo+1] = vram[(vo+1)%VRAM_SIZE];
-					fb[fo+2] = vram[(vo+0)%VRAM_SIZE];
-					fo += 3; vo += 4;
-				}
-				
-				vram_ofs += bytes_per_line;
-				fb_ofs += d->fb->bytes_per_line;
-			}
-		}
-		break;
-	}
-
-	/*
-	 *  Extend the real framebuffer to encompass the area
-	 *  just written to:
-	 */
-
-	/*  Offset to take the margin into account first...  */
-	d->fb_update_x1 += PVR_MARGIN; d->fb_update_y1 += PVR_MARGIN;
-	d->fb_update_x2 += PVR_MARGIN; d->fb_update_y2 += PVR_MARGIN;
-
-	if (d->fb_update_x1 < d->fb->update_x1 || d->fb->update_x1 < 0)
-		d->fb->update_x1 = d->fb_update_x1;
-	if (d->fb_update_x2 > d->fb->update_x2 || d->fb->update_x2 < 0)
-		d->fb->update_x2 = d->fb_update_x2;
-	if (d->fb_update_y1 < d->fb->update_y1 || d->fb->update_y1 < 0)
-		d->fb->update_y1 = d->fb_update_y1;
-	if (d->fb_update_y2 > d->fb->update_y2 || d->fb->update_y2 < 0)
-		d->fb->update_y2 = d->fb_update_y2;
-
-	/*  Clear the PVR's update region:  */
-	d->fb_update_x1 = d->fb_update_x2 =
-	    d->fb_update_y1 = d->fb_update_y2 = -1;
-}
-
-
-DEVICE_ACCESS(pvr_vram_alt)
-{
-	struct pvr_data_alt *d_alt = (struct pvr_data_alt *) extra;
-	struct pvr_data *d = d_alt->d;
-	size_t i;
-
-	if (writeflag == MEM_READ) {
-		/*  Copy from real vram:  */
-		for (i=0; i<len; i++) {
-			int addr = relative_addr + i;
-			addr = ((addr & 4) << 20) | (addr & 3)
-			    | ((addr & 0x7ffff8) >> 1);
-			data[i] = d->vram[addr % VRAM_SIZE];
-		}
-		return 1;
-	}
-
-	// Writes are only allowed as 16-bit access or higher.
-	if (len < sizeof(uint16_t))
-		fatal("pvr_vram_alt: write of less than 16 bits attempted?\n");
-
-	/*
-	 *  Convert writes to alternative VRAM, into normal writes:
-	 */
-
-	for (i=0; i<len; i++) {
-		int addr = relative_addr + i;
-		addr = ((addr & 4) << 20) | (addr & 3) | ((addr & 0x7ffff8) >> 1);
-		// printf("  %08x => alt addr %08x: %02x\n", (int)(relative_addr + i), (int)addr, data[i]);
-		d->vram[addr % VRAM_SIZE] = data[i];
-
-		// TODO: This is probably ultra-slow. (Should not be called
-		// for every _byte_.)
-		pvr_extend_update_region(d, addr, addr);
-	}
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(pvr_vram)
-{
-	struct pvr_data *d = (struct pvr_data *) extra;
-
-	// According to http://mc.pp.se/dc/pvr.html, reads of any size are
-	// allowed.
-	if (writeflag == MEM_READ) {
-		memcpy(data, d->vram + relative_addr, len);
-		return 1;
-	}
-
-	// However, writes are only allowed as 16-bit access or higher.
-	if (len < sizeof(uint16_t))
-		fatal("pvr_vram: write of less than 16 bits attempted?\n");
-
-	/*
-	 *  Write to VRAM:
-	 *
-	 *  Calculate which part of the framebuffer this write corresponds to,
-	 *  if any, and increase the update region to encompass the written
-	 *  memory range.
-	 */
-
-	memcpy(d->vram + relative_addr, data, len);
-	pvr_extend_update_region(d, relative_addr, relative_addr + len - 1);
-
-	return 1;
-}
-
-
-DEVINIT(pvr)
-{
-	struct machine *machine = devinit->machine;
-	struct pvr_data *d;
-	struct pvr_data_alt *d_alt;
-
-	CHECK_ALLOCATION(d = (struct pvr_data *) malloc(sizeof(struct pvr_data)));
-	memset(d, 0, sizeof(struct pvr_data));
-
-	CHECK_ALLOCATION(d_alt = (struct pvr_data_alt *) malloc(sizeof(struct pvr_data_alt)));
-	memset(d_alt, 0, sizeof(struct pvr_data_alt));
-
-	d_alt->d = d;
-
-	memory_device_register(machine->memory, devinit->name,
-	    PVRREG_REGSTART, PVRREG_REGSIZE, dev_pvr_access, d,
-	    DM_DEFAULT, NULL);
-
-	/*  8 MB video RAM:  */
-	d->vram = (uint8_t *) zeroed_alloc(VRAM_SIZE);
-	memory_device_register(machine->memory, "pvr_vram", 0x05000000,
-	    VRAM_SIZE, dev_pvr_vram_access, (void *)d,
-	    DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK
-	    | DM_READS_HAVE_NO_SIDE_EFFECTS, d->vram);
-
-	/*  8 MB video RAM, when accessed at 0xa4000000:  */
-	memory_device_register(machine->memory, "pvr_alt_vram", 0x04000000,
-	    VRAM_SIZE, dev_pvr_vram_alt_access, (void *)d_alt,
-	    DM_DEFAULT, NULL);
-
-	/*  Tile Accelerator command area at 0x10000000:  */
-	memory_device_register(machine->memory, "pvr_ta",
-	    0x10000000, 0x800000, dev_pvr_ta_access, d, DM_DEFAULT, NULL);
-
-	/*  PVR2 DMA registers at 0x5f6800:  */
-	memory_device_register(machine->memory, "pvr_dma", 0x005f6800,
-	    PVR_DMA_MEMLENGTH, dev_pvr_dma_access, d, DM_DEFAULT, NULL);
-
-	/*  More DMA registers at 0x5f7c00:  */
-	memory_device_register(machine->memory, "pvr_dma_more", 0x005f7c00,
-	    PVR_DMA_MEMLENGTH, dev_pvr_dma_more_access, d, DM_DEFAULT, NULL);
-
-	d->xsize = 640;
-	d->ysize = 480;
-	d->pixelmode = 1;	/*  RGB565  */
-	d->bytes_per_pixel = 2;
-
-	d->fb = dev_fb_init(machine, machine->memory, INTERNAL_FB_ADDR,
-	    VFB_GENERIC, d->xsize + PVR_MARGIN*2, d->ysize + PVR_MARGIN*2,
-	    d->xsize + PVR_MARGIN*2, d->ysize + PVR_MARGIN*2,
-	    24, "Dreamcast PVR");
-
-	d->vblank_timer = timer_add(PVR_VBLANK_HZ, pvr_vblank_timer_tick, d);
-
-	pvr_reset(d);
-	pvr_reset_ta(d);
-
-	machine_add_tickfunction(machine, dev_pvr_fb_tick, d,
-	    PVR_FB_TICK_SHIFT);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_px.c gxemul-0.7.0+dfsg/src/devices/dev_px.c
--- gxemul-0.6.2/src/devices/dev_px.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_px.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,817 @@
+/*
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: TURBOchannel Pixelstamp graphics card
+ *
+ *	PMAG-CA = PX
+ *	PMAG-DA = PXG
+ *	PMAG-EA = PXG+
+ *	PMAG-FA = PXG+ TURBO
+ *
+ *  See include/pxreg.h (and NetBSD's arch/pmax/dev/px.c) for more information.
+ *
+ *  The emulation of this device is far from complete. Different pixelstamp
+ *  boards are recognizes under different names depending on operating system:
+ *
+ *	NetBSD/pmax:  (works fine both with and without console on framebuffer)
+ *		PMAG-CA:	px0 at tc0 slot 0 offset 0x0: 2D, 4x1 stamp,
+ *				  8 plane
+ *		PMAG-DA:	px0 at tc0 slot 0 offset 0x0: 3D, 4x1 stamp,
+ *				  8 plane, 128KB SRAM
+ *		PMAG-EA:	(not supported)
+ *		PMAG-FA:	px0 at tc0 slot 0 offset 0x0: 3D, 5x2 stamp,
+ *				  24 plane, 128KB SRAM
+ *
+ *	Ultrix 4.2A rev 47:  (usually crashes if the device is installed, but
+ *						serial console is used)
+ *		PMAG-CA:	px0 at ibus0, pa0 (5x1 8+8+0+0)
+ *		PMAG-DA:	px0 at ibus0, pq0 (5x1 16+16+16+0 128KB)
+ *				    or (5x1 0+0+16+0 128KB)
+ *		PMAG-EA:	(not supported)
+ *		PMAG-FA:	px0 at ibus0, pq0 (5x2 24+24+16+16 128KB)
+ *
+ *	Ultrix 4.2 rev 85:  (usually crashes if the device is installed,
+ *					 but serial console is used)
+ *		PMAG-CA:	ga0 at ibus0, ga0 ( 8 planes 4x1 stamp )
+ *		PMAG-DA:	gq0 at ibus0, gq0 ( 8+8+16Z+0X plane 4x1 stamp )
+ *		PMAG-EA:	(not supported)
+ *		PMAG-FA:	gq0 at ibus0, gq0 ( 24+24+24Z+24X plane
+ *				 5x2 stamp )  (crashes in serial console mode)
+ *
+ *  TODO:  A lot of stuff:
+ *
+ *	Read http://www.mit.edu/afs/athena/system/pmax_ul3/srvd.73/sys/
+ *		io/tc/gq.h
+ *	and try to figure out the interrupt and memory management stuff.
+ *
+ *	Color support: foreground, background, 8-bit palette?
+ *	2D and 3D stuff: polygons? shading?
+ *	Don't use so many hardcoded values.
+ *	Actually interpret the values in each command, don't just
+ *		assume NetBSD/Ultrix usage.
+ *	Factor out the DMA read (main memory vs sram).
+ *	Interrupts?
+ *	Make sure that everything works with both NetBSD and Ultrix.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/pxreg.h"
+
+#define	PX_XSIZE	1280
+#define	PX_YSIZE	1024
+
+static int px_debug = 0;
+
+
+DEVICE_TICK(px)
+{
+#if 0
+	struct px_data *d = extra;
+
+	if (d->intr & STIC_INT_P_EN)		/*  or _WE ?  */
+		INTERRUPT_ASSERT(d->irq);
+#endif
+}
+
+
+/*
+ *  px_readword():
+ *
+ *  Helper function to read 32-bit words from DMA memory,
+ *  to allow both little and big endian accesses.
+ *  (DECstations probably only use little endian access,
+ *  but endianness-independance is probably nice to have anyway.)
+ */
+uint32_t px_readword(struct cpu *cpu, unsigned char *dma_buf, int ofs)
+{
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		return dma_buf[ofs+0] + (dma_buf[ofs+1] << 8) +
+		    (dma_buf[ofs+2] << 16) + (dma_buf[ofs+3] << 24);
+	else
+		return dma_buf[ofs+3] + (dma_buf[ofs+2] << 8) +
+		    (dma_buf[ofs+1] << 16) + (dma_buf[ofs+0] << 24);
+}
+
+
+/*
+ *  dev_px_dma():
+ *
+ *  This routine performs a (fake) DMA transfer of STAMP commands
+ *  and executes them.
+ *
+ *  For the "PX" board, read from main memory (cpu->mem). For all other
+ *  boards, read from the i860 SRAM portion of the device (d->sram).
+ */
+void dev_px_dma(struct cpu *cpu, uint32_t sys_addr, struct px_data *d)
+{
+	unsigned char dma_buf[32768];
+	size_t dma_len = sizeof(dma_buf);
+	int bytesperpixel;
+	uint32_t cmdword;
+
+	bytesperpixel = d->bitdepth >> 3;
+
+	dma_len = 56 * 4;	/*  TODO: this is just enough for NetBSD's
+					 putchar  */
+
+	if (d->type == DEV_PX_TYPE_PX) {
+		cpu->memory_rw(cpu, cpu->mem, sys_addr, dma_buf,
+		    dma_len, MEM_READ, NO_EXCEPTIONS | PHYSICAL);
+	} else {
+		/*  TODO:  past end of sram?  */
+		memmove(dma_buf, &d->sram[sys_addr & 0x1ffff], dma_len);
+	}
+
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+		cmdword = dma_buf[0] + (dma_buf[1] << 8) +
+		    (dma_buf[2] << 16) + (dma_buf[3] << 24);
+	else
+		cmdword = dma_buf[3] + (dma_buf[2] << 8) +
+		    (dma_buf[1] << 16) + (dma_buf[0] << 24);
+
+	if (px_debug) {
+		debug("[ px: dma from 0x%08x: ", (int)sys_addr);
+
+		debug("cmd=");
+		switch (cmdword & 0xf) {
+		case STAMP_CMD_POINTS:		debug("points");	break;
+		case STAMP_CMD_LINES:		debug("lines");		break;
+		case STAMP_CMD_TRIANGLES:	debug("triangles");	break;
+		case STAMP_CMD_COPYSPANS:	debug("copyspans");	break;
+		case STAMP_CMD_READSPANS:	debug("readspans");	break;
+		case STAMP_CMD_WRITESPANS:	debug("writespans");	break;
+		case STAMP_CMD_VIDEO:		debug("video");		break;
+		default:
+			debug("0x%x (?)", cmdword & 0xf);
+		}
+
+		debug(",rgb=");
+		switch (cmdword & 0x30) {
+		case STAMP_RGB_NONE:	debug("none");		break;
+		case STAMP_RGB_CONST:	debug("const");		break;
+		case STAMP_RGB_FLAT:	debug("flat");		break;
+		case STAMP_RGB_SMOOTH:	debug("smooth");	break;
+		default:
+			debug("0x%x (?)", cmdword & 0x30);
+		}
+
+		debug(",z=");
+		switch (cmdword & 0xc0) {
+		case STAMP_Z_NONE:	debug("none");		break;
+		case STAMP_Z_CONST:	debug("const");		break;
+		case STAMP_Z_FLAT:	debug("flat");		break;
+		case STAMP_Z_SMOOTH:	debug("smooth");	break;
+		default:
+			debug("0x%x (?)", cmdword & 0xc0);
+		}
+
+		debug(",xy=");
+		switch (cmdword & 0x300) {
+		case STAMP_XY_NONE:		debug("none");		break;
+		case STAMP_XY_PERPACKET:	debug("perpacket");	break;
+		case STAMP_XY_PERPRIMATIVE:	debug("perprimative");	break;
+		default:
+			debug("0x%x (?)", cmdword & 0x300);
+		}
+
+		debug(",lw=");
+		switch (cmdword & 0xc00) {
+		case STAMP_LW_NONE:		debug("none");		break;
+		case STAMP_LW_PERPACKET:	debug("perpacket");	break;
+		case STAMP_LW_PERPRIMATIVE:	debug("perprimative");	break;
+		default:
+			debug("0x%x (?)", cmdword & 0xc00);
+		}
+
+		if (cmdword & STAMP_CLIPRECT)
+			debug(",CLIPRECT");
+		if (cmdword & STAMP_MESH)
+			debug(",MESH");
+		if (cmdword & STAMP_AALINE)
+			debug(",AALINE");
+		if (cmdword & STAMP_HS_EQUALS)
+			debug(",HS_EQUALS");
+
+		for (size_t i=0; i<dma_len; i++)
+			debug(" %02x", dma_buf[i]);
+
+		debug(" ]\n");
+	}
+
+	/*  NetBSD and Ultrix copyspans  */
+	if (cmdword == 0x405) {
+		uint32_t nspans, lw;
+		uint32_t spannr, ofs;
+		uint32_t span_len, span_src, span_dst;
+		/*  unsigned char pixels[PX_XSIZE * 3];  */
+
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			nspans = dma_buf[4] + (dma_buf[5] << 8) +
+			    (dma_buf[6] << 16) + (dma_buf[7] << 24);
+		else
+			nspans = dma_buf[7] + (dma_buf[6] << 8) +
+			    (dma_buf[5] << 16) + (dma_buf[4] << 24);
+
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			lw = dma_buf[16] + (dma_buf[17] << 8) +
+			    (dma_buf[18] << 16) + (dma_buf[19] << 24);
+		else
+			lw = dma_buf[19] + (dma_buf[18] << 8) +
+			    (dma_buf[17] << 16) + (dma_buf[16] << 24);
+
+		nspans >>= 24;
+		/*  Why not this?  lw = (lw + 1) >> 2;  */
+
+		if (px_debug)
+			debug("[ px: copyspans:  nspans = %i, lw = %i ]\n", nspans, lw);
+
+		/*  Reread copyspans command if it wasn't completely read:  */
+		if (dma_len < 4*(5 + nspans*3)) {
+			dma_len = 4 * (5+nspans*3);
+			if (d->type == DEV_PX_TYPE_PX)
+				cpu->memory_rw(cpu, cpu->mem, sys_addr,
+				    dma_buf, dma_len, MEM_READ,
+				    NO_EXCEPTIONS | PHYSICAL);
+			else
+				memmove(dma_buf, &d->sram[sys_addr & 0x1ffff],
+				    dma_len);	/*  TODO:  past end of sram?  */
+		}
+
+		ofs = 4*5;
+		for (spannr=0; spannr<nspans; spannr++) {
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+				span_len = dma_buf[ofs+0] + (dma_buf[ofs+1] <<
+				    8) + (dma_buf[ofs+2] << 16) +
+				    (dma_buf[ofs+3] << 24);
+			else
+				span_len = dma_buf[ofs+3] + (dma_buf[ofs+2] <<
+				    8) + (dma_buf[ofs+1] << 16) +
+				    (dma_buf[ofs+0] << 24);
+			ofs += 4;
+
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+				span_src = dma_buf[ofs+0] + (dma_buf[ofs+1] <<
+				    8) + (dma_buf[ofs+2] << 16) +
+				    (dma_buf[ofs+3] << 24);
+			else
+				span_src = dma_buf[ofs+3] + (dma_buf[ofs+2] <<
+				    8) + (dma_buf[ofs+1] << 16) +
+				    (dma_buf[ofs+0] << 24);
+			ofs += 4;
+
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+				span_dst = dma_buf[ofs+0] + (dma_buf[ofs+1] <<
+				    8) + (dma_buf[ofs+2] << 16) +
+				    (dma_buf[ofs+3] << 24);
+			else
+				span_dst = dma_buf[ofs+3] + (dma_buf[ofs+2] <<
+				    8) + (dma_buf[ofs+1] << 16) +
+				    (dma_buf[ofs+0] << 24);
+			ofs += 4;
+
+			span_len >>= 3;
+			span_dst >>= 3;
+			span_src >>= 3;
+
+			if (span_len > PX_XSIZE)
+				span_len = PX_XSIZE;
+
+			/*  debug("  span %i: len=%i src=%i dst=%i\n",
+			    spannr, span_len, span_src, span_dst);  */
+
+			memmove(d->vfb_data->framebuffer + span_dst *
+			    PX_XSIZE * bytesperpixel, d->vfb_data->framebuffer
+			    + span_src * PX_XSIZE * bytesperpixel, span_len *
+			    bytesperpixel);
+
+			d->vfb_data->update_x1 = 0; d->vfb_data->update_x2 =
+			    PX_XSIZE-1;
+			if ((int32_t)span_dst < d->vfb_data->update_y1)
+				d->vfb_data->update_y1 = span_dst;
+			if ((int32_t)span_dst > d->vfb_data->update_y2)
+				d->vfb_data->update_y2 = span_dst;
+			if ((int32_t)span_src < d->vfb_data->update_y1)
+				d->vfb_data->update_y1 = span_src;
+			if ((int32_t)span_src > d->vfb_data->update_y2)
+				d->vfb_data->update_y2 = span_src;
+		}
+	}
+
+	/*  NetBSD and Ultrix erasecols/eraserows  */
+	if (cmdword == 0x411) {
+		uint32_t v1, v2, attr;
+		int32_t lw;
+		int x,y,x2,y2;
+		int fb_y;
+		int bg_r, bg_g, bg_b;
+		unsigned char pixels[PX_XSIZE * 3];
+
+		lw = px_readword(cpu, dma_buf, 16);
+		attr = px_readword(cpu, dma_buf, 20);
+		v1 = px_readword(cpu, dma_buf, 24);
+		v2 = px_readword(cpu, dma_buf, 28);
+#if 0
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			lw = dma_buf[16] + (dma_buf[17] << 8) +
+			    (dma_buf[18] << 16) + (dma_buf[19] << 24);
+		else
+			lw = dma_buf[19] + (dma_buf[18] << 8) +
+			    (dma_buf[17] << 16) + (dma_buf[16] << 24);
+
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			v1 = dma_buf[24] + (dma_buf[25] << 8) +
+			    (dma_buf[26] << 16) + (dma_buf[27] << 24);
+		else
+			v1 = dma_buf[27] + (dma_buf[26] << 8) +
+			    (dma_buf[25] << 16) + (dma_buf[24] << 24);
+
+		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+			v2 = dma_buf[28] + (dma_buf[29] << 8) +
+			    (dma_buf[30] << 16) + (dma_buf[31] << 24);
+		else
+			v2 = dma_buf[31] + (dma_buf[30] << 8) +
+			    (dma_buf[29] << 16) + (dma_buf[28] << 24);
+#endif
+		bg_r = (attr >> 16) & 255;
+		bg_g = (attr >> 8) & 255;
+		bg_b = attr & 255;
+		if (bg_r == 0)
+			bg_r = bg_g = bg_b = 0;
+		else
+		if (bg_r == 7)
+			bg_r = bg_g = bg_b = 192;
+		else
+			bg_r = bg_g = bg_b = 255;
+
+		v1 -= lw;
+		v2 -= lw;
+
+		x = (v1 >> 19) & 2047;
+		y = (v1 >> 3) & 1023;
+		x2 = (v2 >> 19) & 2047;
+		y2 = (v2 >> 3) & 1023;
+
+		lw = (lw + 1) >> 2;
+
+		if (x2 - x > PX_XSIZE)
+			x2 = PX_XSIZE;
+
+		if (px_debug)
+			debug("[ px: clear/fill: v1 = 0x%08x  v2 = 0x%08x "
+			    "lw=%i x=%i y=%i x2=%i y2=%i ]\n", (int)v1, (int)v2,
+			    lw, x,y, x2,y2);
+
+		if (bytesperpixel == 3) {
+			int xi;
+			for (xi=0; xi<x2-x; xi++) {
+				/*  TODO:  rgb order?  */
+				pixels[xi*3 + 0] = bg_r;
+				pixels[xi*3 + 1] = bg_g;
+				pixels[xi*3 + 2] = bg_b;
+			}
+		} else
+			memset(pixels, attr, (x2 - x) * bytesperpixel);
+
+		if (x < d->vfb_data->update_x1)
+			d->vfb_data->update_x1 = x;
+		if (x2 > d->vfb_data->update_x2)
+			d->vfb_data->update_x2 = x2;
+
+		for (fb_y=y; fb_y < y2 + lw; fb_y ++) {
+			memcpy(d->vfb_data->framebuffer + (fb_y * PX_XSIZE + x)
+			    * bytesperpixel, pixels, (x2-x)*bytesperpixel);
+
+			if (fb_y < d->vfb_data->update_y1)
+				d->vfb_data->update_y1 = fb_y;
+			if (fb_y > d->vfb_data->update_y2)
+				d->vfb_data->update_y2 = fb_y;
+		}
+	}
+
+	/*  NetBSD and Ultrix putchar  */
+	if (cmdword == 0xa21) {
+		/*  Ugly test code:  */
+		unsigned char pixels[16 * 3];
+		int pixels_len = 16;
+		uint32_t v1, v2, fgcolor, bgcolor;
+		int x, y, x2,y2, i, maxi;
+		int xbit;
+		int suby;
+		int fg_r, fg_g, fg_b;
+		int bg_r, bg_g, bg_b;
+
+		v1 = px_readword(cpu, dma_buf, 52);
+		v2 = px_readword(cpu, dma_buf, 56);
+		fgcolor = px_readword(cpu, dma_buf, 16 * 4);
+		bgcolor = px_readword(cpu, dma_buf, 29 * 4);
+
+		/*
+		 *  TODO:  Which one is r, which one is g, and which one is b?
+		 *  TODO 2:  Use the BT459 palette, these values are hardcoded
+		 *  for NetBSD and Ultrix grayscale only.
+		 */
+		fg_r = (fgcolor >> 16) & 255;
+		fg_g = (fgcolor >> 8) & 255;
+		fg_b = fgcolor & 255;
+		if (fg_r == 0)
+			fg_r = fg_g = fg_b = 0;
+		else
+		if (fg_r == 7)
+			fg_r = fg_g = fg_b = 192;
+		else
+			fg_r = fg_g = fg_b = 255;
+
+		bg_r = (bgcolor >> 16) & 255;
+		bg_g = (bgcolor >> 8) & 255;
+		bg_b = bgcolor & 255;
+		if (bg_r == 0)
+			bg_r = bg_g = bg_b = 0;
+		else
+		if (bg_r == 7)
+			bg_r = bg_g = bg_b = 192;
+		else
+			bg_r = bg_g = bg_b = 255;
+
+		x = (v1 >> 19) & 2047;
+		y = ((v1 - 63) >> 3) & 1023;
+		x2 = (v2 >> 19) & 2047;
+		y2 = ((v2 - 63) >> 3) & 1023;
+
+		if (px_debug)
+			debug("[ px putchar: v1 = 0x%08x  v2 = 0x%08x x=%i y=%i ]\n",
+			    (int)v1, (int)v2, x,y, x2,y2);
+
+		x %= PX_XSIZE;
+		y %= PX_YSIZE;
+		x2 %= PX_XSIZE;
+		y2 %= PX_YSIZE;
+
+		pixels_len = x2 - x;
+
+		suby = 0;
+		maxi = 12;
+		maxi = 33;
+
+		for (i=4; i<maxi; i++) {
+			int j;
+
+			if (i == 12)
+				i = 30;
+
+			for (j=0; j<2; j++) {
+				for (xbit = 0; xbit < 8; xbit ++) {
+					if (bytesperpixel == 3) {
+						/*  24-bit:  */
+						/*  TODO:  Which one is r,
+						    which one is g, and b?  */
+						pixels[xbit * 3 + 0] =
+						    (dma_buf[i*4 + j*2 + 0] &
+						    (1 << xbit))? fg_r : bg_r;
+						pixels[xbit * 3 + 1] =
+						    (dma_buf[i*4 + j*2 + 0] &
+						    (1 << xbit))? fg_g : bg_g;
+						pixels[xbit * 3 + 2] =
+						    (dma_buf[i*4 + j*2 + 0] &
+						    (1 << xbit))? fg_b : bg_b;
+						pixels[(xbit + 8) * 3 + 0] =
+						    (dma_buf[i*4 + j*2 + 1] &
+						    (1 << xbit))? fg_r : bg_r;
+						pixels[(xbit + 8) * 3 + 1] =
+						    (dma_buf[i*4 + j*2 + 1] &
+						    (1 << xbit))? fg_g : bg_g;
+						pixels[(xbit + 8) * 3 + 2] =
+						    (dma_buf[i*4 + j*2 + 1] &
+						    (1 << xbit))? fg_b : bg_b;
+					} else {
+						/*  8-bit:  */
+						pixels[xbit] = (dma_buf[i*4 +
+						    j*2 + 0] & (1 << xbit))?
+						    (fgcolor & 255) :
+						    (bgcolor & 255);
+						pixels[xbit + 8] = (dma_buf[i*4
+						    + j*2 + 1] & (1 << xbit))?
+						    (fgcolor & 255) :
+						    (bgcolor & 255);
+					}
+				}
+
+				memcpy(d->vfb_data->framebuffer + ((y+suby)
+				    * PX_XSIZE + x) * bytesperpixel,
+				    pixels, pixels_len * bytesperpixel);
+
+				if (y+suby < d->vfb_data->update_y1)
+					d->vfb_data->update_y1 = y+suby;
+				if (y+suby > d->vfb_data->update_y2)
+					d->vfb_data->update_y2 = y+suby;
+
+				suby ++;
+			}
+
+		if (x < d->vfb_data->update_x1)
+			d->vfb_data->update_x1 = x;
+		if (x2 > d->vfb_data->update_x2)
+			d->vfb_data->update_x2 = x2;
+		}
+	}
+}
+
+
+DEVICE_ACCESS(px)
+{
+	uint64_t idata = 0, odata = 0;
+	struct px_data *d = (struct px_data *) extra;
+	size_t i;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (relative_addr < 0x0c0000) {
+		/*
+		 *  DMA poll:  a read from this address should start a DMA
+		 *  transfer, and return 1 in odata while the DMA is in
+		 *  progress (STAMP_BUSY), and then 0 (STAMP_OK) once we're
+		 *  done.
+		 *
+		 *  According to NetBSD's pxreg.h, the following formula gets
+		 *  us from system address to DMA address:  (v is the system
+		 *  address)
+		 *
+		 *	dma_addr = ( ( ((v & ~0x7fff) << 3) |
+		 *		(v & 0x7fff) ) & 0x1ffff800) >> 9;
+		 *
+		 *  Hopefully, this is a good enough reversal of that formula:
+		 *
+		 *	sys_addr = ((dma_addr << 9) & 0x7800) +
+		 *		   ((dma_addr << 6) & 0xffff8000);
+		 *
+		 *  If the board type is "PX" then the system address is an
+		 *  address in host memory.  Otherwise, it is relative to
+		 *  0x200000 (the i860's memory space on the board).
+		 */
+		uint32_t sys_addr;	/*  system address for DMA transfers  */
+		sys_addr = ((relative_addr << 9) & 0x7800) +
+		    ((relative_addr << 6) & 0xffff8000);
+
+		/*
+		 *  If the system address is sane enough, then start a DMA
+		 *  transfer:  (for the "PX" board type, don't allow obviously
+		 *  too-low physical addresses)
+		 */
+		if (sys_addr >= 0x4000 || d->type != DEV_PX_TYPE_PX)
+			dev_px_dma(cpu, sys_addr, d);
+
+		/*  Pretend that it was always OK:  */
+		odata = STAMP_OK;
+	}
+
+	/*  N10 sram:  */
+	if (relative_addr >= 0x200000 && relative_addr < 0x280000) {
+		if (d->type == DEV_PX_TYPE_PX)
+			fatal("WARNING: the vdac should be at this "
+			    "address. overlap problems?\n");
+
+		if (writeflag == MEM_WRITE) {
+			for (i=0; i<len; i++)
+				d->sram[relative_addr - 0x200000 + i] = data[i];
+			/*  NOTE:  this return here supresses debug output
+			    (which would be printed if we continue)  */
+			return 1;
+		} else {
+			/*
+			 *  Huh? Why have I commented out this? TODO
+			 */
+			/*  for (i=0; i<len; i++)
+				data[i] = d->sram[relative_addr - 0x200000
+			    + i];  */
+			odata = 1;
+		}
+	}
+
+	/*  TODO:  Most of these aren't implemented yet.  */
+
+	switch (relative_addr) {
+
+	case 0x180008:		/*  hsync  */
+		if (writeflag==MEM_READ) {
+			debug("[ px: read from hsync: 0x%08llx ]\n",
+			    (long long)odata);
+		} else {
+			debug("[ px: write to hsync: 0x%08llx ]\n",
+			    (long long)idata);
+		}
+		break;
+
+	case 0x18000c:		/*  hsync2  */
+		if (writeflag==MEM_READ) {
+			debug("[ px: read from hsync2: 0x%08llx ]\n",
+			    (long long)odata);
+		} else {
+			debug("[ px: write to hsync2: 0x%08llx ]\n",
+			    (long long)idata);
+		}
+		break;
+
+	case 0x180010:		/*  hblank  */
+		if (writeflag==MEM_READ) {
+			debug("[ px: read from hblank: 0x%08llx ]\n",
+			    (long long)odata);
+		} else {
+			debug("[ px: write to hblank: 0x%08llx ]\n",
+			    (long long)idata);
+		}
+		break;
+
+	case 0x180014:		/*  vsync  */
+		if (writeflag==MEM_READ) {
+			debug("[ px: read from vsync: 0x%08llx ]\n",
+			    (long long)odata);
+		} else {
+			debug("[ px: write to vsync: 0x%08llx ]\n",
+			    (long long)idata);
+		}
+		break;
+
+	case 0x180018:		/*  vblank  */
+		if (writeflag==MEM_READ) {
+			debug("[ px: read from vblank: 0x%08llx ]\n",
+			    (long long)odata);
+		} else {
+			debug("[ px: write to vblank: 0x%08llx ]\n",
+			    (long long)idata);
+		}
+		break;
+
+	case 0x180020:		/*  ipdvint  */
+		if (writeflag==MEM_READ) {
+			odata = d->intr;
+
+/*  TODO:  how do interrupts work on the pixelstamp boards?  */
+odata = random();
+
+			debug("[ px: read from ipdvint: 0x%08llx ]\n",
+			    (long long)odata);
+		} else {
+			d->intr = idata;
+			if (idata & STIC_INT_E_WE)
+				d->intr &= ~STIC_INT_E;
+			if (idata & STIC_INT_V_WE)
+				d->intr &= ~STIC_INT_V;
+			if (idata & STIC_INT_P_WE)
+				d->intr &= ~STIC_INT_P;
+			debug("[ px: write to ipdvint: 0x%08llx ]\n",
+			    (long long)idata);
+		}
+		break;
+
+	case 0x180028:		/*  sticsr  */
+		if (writeflag==MEM_READ) {
+			debug("[ px: read from sticsr: 0x%08llx ]\n",
+			    (long long)odata);
+		} else {
+			debug("[ px: write to sticsr: 0x%08llx ]\n",
+			    (long long)idata);
+		}
+		break;
+
+	case 0x180038:		/*  buscsr  */
+		if (writeflag==MEM_READ) {
+			debug("[ px: read from buscsr: 0x%08llx ]\n",
+			    (long long)odata);
+		} else {
+			debug("[ px: write to buscsr: 0x%08llx ]\n",
+			    (long long)idata);
+		}
+		break;
+
+	case 0x18003c:		/*  modcl  */
+		if (writeflag==MEM_READ) {
+			odata = (d->type << 12) + (d->xconfig << 11) +
+			    (d->yconfig << 9);
+			debug("[ px: read from modcl: 0x%llx ]\n",
+			    (long long)odata);
+		} else {
+			debug("[ px: write to modcl: 0x%llx ]\n",
+			    (long long)idata);
+		}
+		break;
+
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ px: read from addr 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)odata);
+		} else {
+			debug("[ px: write to addr 0x%x: 0x%llx ]\n",
+			    (int)relative_addr, (long long)idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+void dev_px_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, int px_type, const char *irq_path)
+{
+	struct px_data *d;
+
+	CHECK_ALLOCATION(d = (struct px_data *) malloc(sizeof(struct px_data)));
+	memset(d, 0, sizeof(struct px_data));
+
+	d->type = px_type;
+
+	INTERRUPT_CONNECT(irq_path, d->irq);
+
+	d->xconfig = d->yconfig = 0;	/*  4x1  */
+
+	d->bitdepth = 24;
+	d->px_name = "(invalid)";
+
+	switch (d->type) {
+	case DEV_PX_TYPE_PX:
+		d->bitdepth = 8;
+		d->px_name = "PX";
+		break;
+	case DEV_PX_TYPE_PXG:
+		d->bitdepth = 8;
+		d->px_name = "PXG";
+		break;
+	case DEV_PX_TYPE_PXGPLUS:
+		d->px_name = "PXG+";
+		break;
+	case DEV_PX_TYPE_PXGPLUSTURBO:
+		d->px_name = "PXG+ TURBO";
+		d->xconfig = d->yconfig = 1;	/*  5x2  */
+		break;
+	default:
+		fatal("dev_px_init(): unimplemented px_type\n");
+	}
+
+	d->fb_mem = memory_new(PX_XSIZE * PX_YSIZE * d->bitdepth / 8);
+	if (d->fb_mem == NULL) {
+		fprintf(stderr, "dev_px_init(): out of memory (1)\n");
+		exit(1);
+	}
+
+	d->vfb_data = dev_fb_init(machine, d->fb_mem, 0, VFB_GENERIC,
+	    PX_XSIZE, PX_YSIZE, PX_XSIZE, PX_YSIZE, d->bitdepth, d->px_name);
+	if (d->vfb_data == NULL) {
+		fprintf(stderr, "dev_px_init(): out of memory (2)\n");
+		exit(2);
+	}
+
+	switch (d->type) {
+	case DEV_PX_TYPE_PX:
+		dev_bt459_init(machine, mem, baseaddr + 0x200000, 0,
+		    d->vfb_data, 8, irq_path, BT459_PX);
+		break;
+	case DEV_PX_TYPE_PXG:
+	case DEV_PX_TYPE_PXGPLUS:
+	case DEV_PX_TYPE_PXGPLUSTURBO:
+		dev_bt459_init(machine, mem, baseaddr + 0x300000, 0,
+		    d->vfb_data, d->bitdepth, irq_path, BT459_PX);
+		break;
+	default:
+		fatal("dev_px_init(): unimplemented px_type\n");
+	}
+
+	memory_device_register(mem, "px", baseaddr, DEV_PX_LENGTH,
+	    dev_px_access, d, DM_DEFAULT, NULL);
+	machine_add_tickfunction(machine, dev_px_tick, d, 14);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_px.cc gxemul-0.7.0+dfsg/src/devices/dev_px.cc
--- gxemul-0.6.2/src/devices/dev_px.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_px.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,822 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: TURBOchannel Pixelstamp graphics card
- *
- *	PMAG-CA = PX
- *	PMAG-DA = PXG
- *	PMAG-EA = PXG+
- *	PMAG-FA = PXG+ TURBO
- *
- *  See include/pxreg.h (and NetBSD's arch/pmax/dev/px.c) for more information.
- *
- *  The emulation of this device is far from complete. Different pixelstamp
- *  boards are recognizes under different names depending on operating system:
- *
- *	NetBSD/pmax:  (works fine both with and without console on framebuffer)
- *		PMAG-CA:	px0 at tc0 slot 0 offset 0x0: 2D, 4x1 stamp,
- *				  8 plane
- *		PMAG-DA:	px0 at tc0 slot 0 offset 0x0: 3D, 4x1 stamp,
- *				  8 plane, 128KB SRAM
- *		PMAG-EA:	(not supported)
- *		PMAG-FA:	px0 at tc0 slot 0 offset 0x0: 3D, 5x2 stamp,
- *				  24 plane, 128KB SRAM
- *
- *	Ultrix 4.2A rev 47:  (usually crashes if the device is installed, but
- *						serial console is used)
- *		PMAG-CA:	px0 at ibus0, pa0 (5x1 8+8+0+0)
- *		PMAG-DA:	px0 at ibus0, pq0 (5x1 16+16+16+0 128KB)
- *				    or (5x1 0+0+16+0 128KB)
- *		PMAG-EA:	(not supported)
- *		PMAG-FA:	px0 at ibus0, pq0 (5x2 24+24+16+16 128KB)
- *
- *	Ultrix 4.2 rev 85:  (usually crashes if the device is installed,
- *					 but serial console is used)
- *		PMAG-CA:	ga0 at ibus0, ga0 ( 8 planes 4x1 stamp )
- *		PMAG-DA:	gq0 at ibus0, gq0 ( 8+8+16Z+0X plane 4x1 stamp )
- *		PMAG-EA:	(not supported)
- *		PMAG-FA:	gq0 at ibus0, gq0 ( 24+24+24Z+24X plane
- *				 5x2 stamp )  (crashes in serial console mode)
- *
- *  TODO:  A lot of stuff:
- *
- *	Read http://www.mit.edu/afs/athena/system/pmax_ul3/srvd.73/sys/
- *		io/tc/gq.h
- *	and try to figure out the interrupt and memory management stuff.
- *
- *	Color support: foreground, background, 8-bit palette?
- *	2D and 3D stuff: polygons? shading?
- *	Don't use so many hardcoded values.
- *	Actually interpret the values in each command, don't just
- *		assume NetBSD/Ultrix usage.
- *	Factor out the DMA read (main memory vs sram).
- *	Interrupts?
- *	Make sure that everything works with both NetBSD and Ultrix.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/pxreg.h"
-
-#define	PX_XSIZE	1280
-#define	PX_YSIZE	1024
-
-/* #define PX_DEBUG  */
-
-
-DEVICE_TICK(px)
-{
-#if 0
-	struct px_data *d = extra;
-
-	if (d->intr & STIC_INT_P_EN)		/*  or _WE ?  */
-		INTERRUPT_ASSERT(d->irq);
-#endif
-}
-
-
-/*
- *  px_readword():
- *
- *  Helper function to read 32-bit words from DMA memory,
- *  to allow both little and big endian accesses.
- *  (DECstations probably only use little endian access,
- *  but endianness-independance is probably nice to have anyway.)
- */
-uint32_t px_readword(struct cpu *cpu, unsigned char *dma_buf, int ofs)
-{
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		return dma_buf[ofs+0] + (dma_buf[ofs+1] << 8) +
-		    (dma_buf[ofs+2] << 16) + (dma_buf[ofs+3] << 24);
-	else
-		return dma_buf[ofs+3] + (dma_buf[ofs+2] << 8) +
-		    (dma_buf[ofs+1] << 16) + (dma_buf[ofs+0] << 24);
-}
-
-
-/*
- *  dev_px_dma():
- *
- *  This routine performs a (fake) DMA transfer of STAMP commands
- *  and executes them.
- *
- *  For the "PX" board, read from main memory (cpu->mem). For all other
- *  boards, read from the i860 SRAM portion of the device (d->sram).
- */
-void dev_px_dma(struct cpu *cpu, uint32_t sys_addr, struct px_data *d)
-{
-	unsigned char dma_buf[32768];
-	size_t dma_len = sizeof(dma_buf);
-	int bytesperpixel;
-	uint32_t cmdword;
-
-	bytesperpixel = d->bitdepth >> 3;
-
-	dma_len = 56 * 4;	/*  TODO: this is just enough for NetBSD's
-					 putchar  */
-
-	if (d->type == DEV_PX_TYPE_PX) {
-		cpu->memory_rw(cpu, cpu->mem, sys_addr, dma_buf,
-		    dma_len, MEM_READ, NO_EXCEPTIONS | PHYSICAL);
-	} else {
-		/*  TODO:  past end of sram?  */
-		memmove(dma_buf, &d->sram[sys_addr & 0x1ffff], dma_len);
-	}
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-		cmdword = dma_buf[0] + (dma_buf[1] << 8) +
-		    (dma_buf[2] << 16) + (dma_buf[3] << 24);
-	else
-		cmdword = dma_buf[3] + (dma_buf[2] << 8) +
-		    (dma_buf[1] << 16) + (dma_buf[0] << 24);
-
-#ifdef PX_DEBUG
-	debug("[ px: dma from 0x%08x: ", (int)sys_addr);
-
-	debug("cmd=");
-	switch (cmdword & 0xf) {
-	case STAMP_CMD_POINTS:		debug("points");	break;
-	case STAMP_CMD_LINES:		debug("lines");		break;
-	case STAMP_CMD_TRIANGLES:	debug("triangles");	break;
-	case STAMP_CMD_COPYSPANS:	debug("copyspans");	break;
-	case STAMP_CMD_READSPANS:	debug("readspans");	break;
-	case STAMP_CMD_WRITESPANS:	debug("writespans");	break;
-	case STAMP_CMD_VIDEO:		debug("video");		break;
-	default:
-		debug("0x%x (?)", cmdword & 0xf);
-	}
-
-	debug(",rgb=");
-	switch (cmdword & 0x30) {
-	case STAMP_RGB_NONE:	debug("none");		break;
-	case STAMP_RGB_CONST:	debug("const");		break;
-	case STAMP_RGB_FLAT:	debug("flat");		break;
-	case STAMP_RGB_SMOOTH:	debug("smooth");	break;
-	default:
-		debug("0x%x (?)", cmdword & 0x30);
-	}
-
-	debug(",z=");
-	switch (cmdword & 0xc0) {
-	case STAMP_Z_NONE:	debug("none");		break;
-	case STAMP_Z_CONST:	debug("const");		break;
-	case STAMP_Z_FLAT:	debug("flat");		break;
-	case STAMP_Z_SMOOTH:	debug("smooth");	break;
-	default:
-		debug("0x%x (?)", cmdword & 0xc0);
-	}
-
-	debug(",xy=");
-	switch (cmdword & 0x300) {
-	case STAMP_XY_NONE:		debug("none");		break;
-	case STAMP_XY_PERPACKET:	debug("perpacket");	break;
-	case STAMP_XY_PERPRIMATIVE:	debug("perprimative");	break;
-	default:
-		debug("0x%x (?)", cmdword & 0x300);
-	}
-
-	debug(",lw=");
-	switch (cmdword & 0xc00) {
-	case STAMP_LW_NONE:		debug("none");		break;
-	case STAMP_LW_PERPACKET:	debug("perpacket");	break;
-	case STAMP_LW_PERPRIMATIVE:	debug("perprimative");	break;
-	default:
-		debug("0x%x (?)", cmdword & 0xc00);
-	}
-
-	if (cmdword & STAMP_CLIPRECT)
-		debug(",CLIPRECT");
-	if (cmdword & STAMP_MESH)
-		debug(",MESH");
-	if (cmdword & STAMP_AALINE)
-		debug(",AALINE");
-	if (cmdword & STAMP_HS_EQUALS)
-		debug(",HS_EQUALS");
-
-	{
-		size_t i;
-		for (i=0; i<dma_len; i++)
-			debug(" %02x", dma_buf[i]);
-	}
-
-	debug(" ]\n");
-#endif	/*  PX_DEBUG  */
-
-	/*  NetBSD and Ultrix copyspans  */
-	if (cmdword == 0x405) {
-		uint32_t nspans, lw;
-		uint32_t spannr, ofs;
-		uint32_t span_len, span_src, span_dst;
-		/*  unsigned char pixels[PX_XSIZE * 3];  */
-
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			nspans = dma_buf[4] + (dma_buf[5] << 8) +
-			    (dma_buf[6] << 16) + (dma_buf[7] << 24);
-		else
-			nspans = dma_buf[7] + (dma_buf[6] << 8) +
-			    (dma_buf[5] << 16) + (dma_buf[4] << 24);
-
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			lw = dma_buf[16] + (dma_buf[17] << 8) +
-			    (dma_buf[18] << 16) + (dma_buf[19] << 24);
-		else
-			lw = dma_buf[19] + (dma_buf[18] << 8) +
-			    (dma_buf[17] << 16) + (dma_buf[16] << 24);
-
-		nspans >>= 24;
-		/*  Why not this?  lw = (lw + 1) >> 2;  */
-
-#ifdef PX_DEBUG
-		debug("[ px: copyspans:  nspans = %i, lw = %i ]\n", nspans, lw);
-#endif
-
-		/*  Reread copyspans command if it wasn't completely read:  */
-		if (dma_len < 4*(5 + nspans*3)) {
-			dma_len = 4 * (5+nspans*3);
-			if (d->type == DEV_PX_TYPE_PX)
-				cpu->memory_rw(cpu, cpu->mem, sys_addr,
-				    dma_buf, dma_len, MEM_READ,
-				    NO_EXCEPTIONS | PHYSICAL);
-			else
-				memmove(dma_buf, &d->sram[sys_addr & 0x1ffff],
-				    dma_len);	/*  TODO:  past end of sram?  */
-		}
-
-		ofs = 4*5;
-		for (spannr=0; spannr<nspans; spannr++) {
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-				span_len = dma_buf[ofs+0] + (dma_buf[ofs+1] <<
-				    8) + (dma_buf[ofs+2] << 16) +
-				    (dma_buf[ofs+3] << 24);
-			else
-				span_len = dma_buf[ofs+3] + (dma_buf[ofs+2] <<
-				    8) + (dma_buf[ofs+1] << 16) +
-				    (dma_buf[ofs+0] << 24);
-			ofs += 4;
-
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-				span_src = dma_buf[ofs+0] + (dma_buf[ofs+1] <<
-				    8) + (dma_buf[ofs+2] << 16) +
-				    (dma_buf[ofs+3] << 24);
-			else
-				span_src = dma_buf[ofs+3] + (dma_buf[ofs+2] <<
-				    8) + (dma_buf[ofs+1] << 16) +
-				    (dma_buf[ofs+0] << 24);
-			ofs += 4;
-
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-				span_dst = dma_buf[ofs+0] + (dma_buf[ofs+1] <<
-				    8) + (dma_buf[ofs+2] << 16) +
-				    (dma_buf[ofs+3] << 24);
-			else
-				span_dst = dma_buf[ofs+3] + (dma_buf[ofs+2] <<
-				    8) + (dma_buf[ofs+1] << 16) +
-				    (dma_buf[ofs+0] << 24);
-			ofs += 4;
-
-			span_len >>= 3;
-			span_dst >>= 3;
-			span_src >>= 3;
-
-			if (span_len > PX_XSIZE)
-				span_len = PX_XSIZE;
-
-			/*  debug("  span %i: len=%i src=%i dst=%i\n",
-			    spannr, span_len, span_src, span_dst);  */
-
-			memmove(d->vfb_data->framebuffer + span_dst *
-			    PX_XSIZE * bytesperpixel, d->vfb_data->framebuffer
-			    + span_src * PX_XSIZE * bytesperpixel, span_len *
-			    bytesperpixel);
-
-			d->vfb_data->update_x1 = 0; d->vfb_data->update_x2 =
-			    PX_XSIZE-1;
-			if ((int32_t)span_dst < d->vfb_data->update_y1)
-				d->vfb_data->update_y1 = span_dst;
-			if ((int32_t)span_dst > d->vfb_data->update_y2)
-				d->vfb_data->update_y2 = span_dst;
-			if ((int32_t)span_src < d->vfb_data->update_y1)
-				d->vfb_data->update_y1 = span_src;
-			if ((int32_t)span_src > d->vfb_data->update_y2)
-				d->vfb_data->update_y2 = span_src;
-		}
-	}
-
-	/*  NetBSD and Ultrix erasecols/eraserows  */
-	if (cmdword == 0x411) {
-		uint32_t v1, v2, attr;
-		int32_t lw;
-		int x,y,x2,y2;
-		int fb_y;
-		int bg_r, bg_g, bg_b;
-		unsigned char pixels[PX_XSIZE * 3];
-
-		lw = px_readword(cpu, dma_buf, 16);
-		attr = px_readword(cpu, dma_buf, 20);
-		v1 = px_readword(cpu, dma_buf, 24);
-		v2 = px_readword(cpu, dma_buf, 28);
-#if 0
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			lw = dma_buf[16] + (dma_buf[17] << 8) +
-			    (dma_buf[18] << 16) + (dma_buf[19] << 24);
-		else
-			lw = dma_buf[19] + (dma_buf[18] << 8) +
-			    (dma_buf[17] << 16) + (dma_buf[16] << 24);
-
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			v1 = dma_buf[24] + (dma_buf[25] << 8) +
-			    (dma_buf[26] << 16) + (dma_buf[27] << 24);
-		else
-			v1 = dma_buf[27] + (dma_buf[26] << 8) +
-			    (dma_buf[25] << 16) + (dma_buf[24] << 24);
-
-		if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-			v2 = dma_buf[28] + (dma_buf[29] << 8) +
-			    (dma_buf[30] << 16) + (dma_buf[31] << 24);
-		else
-			v2 = dma_buf[31] + (dma_buf[30] << 8) +
-			    (dma_buf[29] << 16) + (dma_buf[28] << 24);
-#endif
-		bg_r = (attr >> 16) & 255;
-		bg_g = (attr >> 8) & 255;
-		bg_b = attr & 255;
-		if (bg_r == 0)
-			bg_r = bg_g = bg_b = 0;
-		else
-		if (bg_r == 7)
-			bg_r = bg_g = bg_b = 192;
-		else
-			bg_r = bg_g = bg_b = 255;
-
-		v1 -= lw;
-		v2 -= lw;
-
-		x = (v1 >> 19) & 2047;
-		y = (v1 >> 3) & 1023;
-		x2 = (v2 >> 19) & 2047;
-		y2 = (v2 >> 3) & 1023;
-
-		lw = (lw + 1) >> 2;
-
-		if (x2 - x > PX_XSIZE)
-			x2 = PX_XSIZE;
-
-#ifdef PX_DEBUG
-		debug("[ px: clear/fill: v1 = 0x%08x  v2 = 0x%08x "
-		    "lw=%i x=%i y=%i x2=%i y2=%i ]\n", (int)v1, (int)v2,
-		    lw, x,y, x2,y2);
-#endif
-		if (bytesperpixel == 3) {
-			int xi;
-			for (xi=0; xi<x2-x; xi++) {
-				/*  TODO:  rgb order?  */
-				pixels[xi*3 + 0] = bg_r;
-				pixels[xi*3 + 1] = bg_g;
-				pixels[xi*3 + 2] = bg_b;
-			}
-		} else
-			memset(pixels, attr, (x2 - x) * bytesperpixel);
-
-		if (x < d->vfb_data->update_x1)
-			d->vfb_data->update_x1 = x;
-		if (x2 > d->vfb_data->update_x2)
-			d->vfb_data->update_x2 = x2;
-
-		for (fb_y=y; fb_y < y2 + lw; fb_y ++) {
-			memcpy(d->vfb_data->framebuffer + (fb_y * PX_XSIZE + x)
-			    * bytesperpixel, pixels, (x2-x)*bytesperpixel);
-
-			if (fb_y < d->vfb_data->update_y1)
-				d->vfb_data->update_y1 = fb_y;
-			if (fb_y > d->vfb_data->update_y2)
-				d->vfb_data->update_y2 = fb_y;
-		}
-	}
-
-	/*  NetBSD and Ultrix putchar  */
-	if (cmdword == 0xa21) {
-		/*  Ugly test code:  */
-		unsigned char pixels[16 * 3];
-		int pixels_len = 16;
-		uint32_t v1, v2, fgcolor, bgcolor;
-		int x, y, x2,y2, i, maxi;
-		int xbit;
-		int suby;
-		int fg_r, fg_g, fg_b;
-		int bg_r, bg_g, bg_b;
-
-		v1 = px_readword(cpu, dma_buf, 52);
-		v2 = px_readword(cpu, dma_buf, 56);
-		fgcolor = px_readword(cpu, dma_buf, 16 * 4);
-		bgcolor = px_readword(cpu, dma_buf, 29 * 4);
-
-		/*
-		 *  TODO:  Which one is r, which one is g, and which one is b?
-		 *  TODO 2:  Use the BT459 palette, these values are hardcoded
-		 *  for NetBSD and Ultrix grayscale only.
-		 */
-		fg_r = (fgcolor >> 16) & 255;
-		fg_g = (fgcolor >> 8) & 255;
-		fg_b = fgcolor & 255;
-		if (fg_r == 0)
-			fg_r = fg_g = fg_b = 0;
-		else
-		if (fg_r == 7)
-			fg_r = fg_g = fg_b = 192;
-		else
-			fg_r = fg_g = fg_b = 255;
-
-		bg_r = (bgcolor >> 16) & 255;
-		bg_g = (bgcolor >> 8) & 255;
-		bg_b = bgcolor & 255;
-		if (bg_r == 0)
-			bg_r = bg_g = bg_b = 0;
-		else
-		if (bg_r == 7)
-			bg_r = bg_g = bg_b = 192;
-		else
-			bg_r = bg_g = bg_b = 255;
-
-		x = (v1 >> 19) & 2047;
-		y = ((v1 - 63) >> 3) & 1023;
-		x2 = (v2 >> 19) & 2047;
-		y2 = ((v2 - 63) >> 3) & 1023;
-
-#ifdef PX_DEBUG
-		debug("[ px putchar: v1 = 0x%08x  v2 = 0x%08x x=%i y=%i ]\n",
-		    (int)v1, (int)v2, x,y, x2,y2);
-#endif
-		x %= PX_XSIZE;
-		y %= PX_YSIZE;
-		x2 %= PX_XSIZE;
-		y2 %= PX_YSIZE;
-
-		pixels_len = x2 - x;
-
-		suby = 0;
-		maxi = 12;
-		maxi = 33;
-
-		for (i=4; i<maxi; i++) {
-			int j;
-
-			if (i == 12)
-				i = 30;
-
-			for (j=0; j<2; j++) {
-				for (xbit = 0; xbit < 8; xbit ++) {
-					if (bytesperpixel == 3) {
-						/*  24-bit:  */
-						/*  TODO:  Which one is r,
-						    which one is g, and b?  */
-						pixels[xbit * 3 + 0] =
-						    (dma_buf[i*4 + j*2 + 0] &
-						    (1 << xbit))? fg_r : bg_r;
-						pixels[xbit * 3 + 1] =
-						    (dma_buf[i*4 + j*2 + 0] &
-						    (1 << xbit))? fg_g : bg_g;
-						pixels[xbit * 3 + 2] =
-						    (dma_buf[i*4 + j*2 + 0] &
-						    (1 << xbit))? fg_b : bg_b;
-						pixels[(xbit + 8) * 3 + 0] =
-						    (dma_buf[i*4 + j*2 + 1] &
-						    (1 << xbit))? fg_r : bg_r;
-						pixels[(xbit + 8) * 3 + 1] =
-						    (dma_buf[i*4 + j*2 + 1] &
-						    (1 << xbit))? fg_g : bg_g;
-						pixels[(xbit + 8) * 3 + 2] =
-						    (dma_buf[i*4 + j*2 + 1] &
-						    (1 << xbit))? fg_b : bg_b;
-					} else {
-						/*  8-bit:  */
-						pixels[xbit] = (dma_buf[i*4 +
-						    j*2 + 0] & (1 << xbit))?
-						    (fgcolor & 255) :
-						    (bgcolor & 255);
-						pixels[xbit + 8] = (dma_buf[i*4
-						    + j*2 + 1] & (1 << xbit))?
-						    (fgcolor & 255) :
-						    (bgcolor & 255);
-					}
-				}
-
-				memcpy(d->vfb_data->framebuffer + ((y+suby)
-				    * PX_XSIZE + x) * bytesperpixel,
-				    pixels, pixels_len * bytesperpixel);
-
-				if (y+suby < d->vfb_data->update_y1)
-					d->vfb_data->update_y1 = y+suby;
-				if (y+suby > d->vfb_data->update_y2)
-					d->vfb_data->update_y2 = y+suby;
-
-				suby ++;
-			}
-
-		if (x < d->vfb_data->update_x1)
-			d->vfb_data->update_x1 = x;
-		if (x2 > d->vfb_data->update_x2)
-			d->vfb_data->update_x2 = x2;
-		}
-	}
-}
-
-
-DEVICE_ACCESS(px)
-{
-	uint64_t idata = 0, odata = 0;
-	struct px_data *d = (struct px_data *) extra;
-	size_t i;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (relative_addr < 0x0c0000) {
-		/*
-		 *  DMA poll:  a read from this address should start a DMA
-		 *  transfer, and return 1 in odata while the DMA is in
-		 *  progress (STAMP_BUSY), and then 0 (STAMP_OK) once we're
-		 *  done.
-		 *
-		 *  According to NetBSD's pxreg.h, the following formula gets
-		 *  us from system address to DMA address:  (v is the system
-		 *  address)
-		 *
-		 *	dma_addr = ( ( ((v & ~0x7fff) << 3) |
-		 *		(v & 0x7fff) ) & 0x1ffff800) >> 9;
-		 *
-		 *  Hopefully, this is a good enough reversal of that formula:
-		 *
-		 *	sys_addr = ((dma_addr << 9) & 0x7800) +
-		 *		   ((dma_addr << 6) & 0xffff8000);
-		 *
-		 *  If the board type is "PX" then the system address is an
-		 *  address in host memory.  Otherwise, it is relative to
-		 *  0x200000 (the i860's memory space on the board).
-		 */
-		uint32_t sys_addr;	/*  system address for DMA transfers  */
-		sys_addr = ((relative_addr << 9) & 0x7800) +
-		    ((relative_addr << 6) & 0xffff8000);
-
-		/*
-		 *  If the system address is sane enough, then start a DMA
-		 *  transfer:  (for the "PX" board type, don't allow obviously
-		 *  too-low physical addresses)
-		 */
-		if (sys_addr >= 0x4000 || d->type != DEV_PX_TYPE_PX)
-			dev_px_dma(cpu, sys_addr, d);
-
-		/*  Pretend that it was always OK:  */
-		odata = STAMP_OK;
-	}
-
-	/*  N10 sram:  */
-	if (relative_addr >= 0x200000 && relative_addr < 0x280000) {
-		if (d->type == DEV_PX_TYPE_PX)
-			fatal("WARNING: the vdac should be at this "
-			    "address. overlap problems?\n");
-
-		if (writeflag == MEM_WRITE) {
-			for (i=0; i<len; i++)
-				d->sram[relative_addr - 0x200000 + i] = data[i];
-			/*  NOTE:  this return here supresses debug output
-			    (which would be printed if we continue)  */
-			return 1;
-		} else {
-			/*
-			 *  Huh? Why have I commented out this? TODO
-			 */
-			/*  for (i=0; i<len; i++)
-				data[i] = d->sram[relative_addr - 0x200000
-			    + i];  */
-			odata = 1;
-		}
-	}
-
-	/*  TODO:  Most of these aren't implemented yet.  */
-
-	switch (relative_addr) {
-
-	case 0x180008:		/*  hsync  */
-		if (writeflag==MEM_READ) {
-			debug("[ px: read from hsync: 0x%08llx ]\n",
-			    (long long)odata);
-		} else {
-			debug("[ px: write to hsync: 0x%08llx ]\n",
-			    (long long)idata);
-		}
-		break;
-
-	case 0x18000c:		/*  hsync2  */
-		if (writeflag==MEM_READ) {
-			debug("[ px: read from hsync2: 0x%08llx ]\n",
-			    (long long)odata);
-		} else {
-			debug("[ px: write to hsync2: 0x%08llx ]\n",
-			    (long long)idata);
-		}
-		break;
-
-	case 0x180010:		/*  hblank  */
-		if (writeflag==MEM_READ) {
-			debug("[ px: read from hblank: 0x%08llx ]\n",
-			    (long long)odata);
-		} else {
-			debug("[ px: write to hblank: 0x%08llx ]\n",
-			    (long long)idata);
-		}
-		break;
-
-	case 0x180014:		/*  vsync  */
-		if (writeflag==MEM_READ) {
-			debug("[ px: read from vsync: 0x%08llx ]\n",
-			    (long long)odata);
-		} else {
-			debug("[ px: write to vsync: 0x%08llx ]\n",
-			    (long long)idata);
-		}
-		break;
-
-	case 0x180018:		/*  vblank  */
-		if (writeflag==MEM_READ) {
-			debug("[ px: read from vblank: 0x%08llx ]\n",
-			    (long long)odata);
-		} else {
-			debug("[ px: write to vblank: 0x%08llx ]\n",
-			    (long long)idata);
-		}
-		break;
-
-	case 0x180020:		/*  ipdvint  */
-		if (writeflag==MEM_READ) {
-			odata = d->intr;
-
-/*  TODO:  how do interrupts work on the pixelstamp boards?  */
-odata = random();
-
-			debug("[ px: read from ipdvint: 0x%08llx ]\n",
-			    (long long)odata);
-		} else {
-			d->intr = idata;
-			if (idata & STIC_INT_E_WE)
-				d->intr &= ~STIC_INT_E;
-			if (idata & STIC_INT_V_WE)
-				d->intr &= ~STIC_INT_V;
-			if (idata & STIC_INT_P_WE)
-				d->intr &= ~STIC_INT_P;
-			debug("[ px: write to ipdvint: 0x%08llx ]\n",
-			    (long long)idata);
-		}
-		break;
-
-	case 0x180028:		/*  sticsr  */
-		if (writeflag==MEM_READ) {
-			debug("[ px: read from sticsr: 0x%08llx ]\n",
-			    (long long)odata);
-		} else {
-			debug("[ px: write to sticsr: 0x%08llx ]\n",
-			    (long long)idata);
-		}
-		break;
-
-	case 0x180038:		/*  buscsr  */
-		if (writeflag==MEM_READ) {
-			debug("[ px: read from buscsr: 0x%08llx ]\n",
-			    (long long)odata);
-		} else {
-			debug("[ px: write to buscsr: 0x%08llx ]\n",
-			    (long long)idata);
-		}
-		break;
-
-	case 0x18003c:		/*  modcl  */
-		if (writeflag==MEM_READ) {
-			odata = (d->type << 12) + (d->xconfig << 11) +
-			    (d->yconfig << 9);
-			debug("[ px: read from modcl: 0x%llx ]\n",
-			    (long long)odata);
-		} else {
-			debug("[ px: write to modcl: 0x%llx ]\n",
-			    (long long)idata);
-		}
-		break;
-
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ px: read from addr 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)odata);
-		} else {
-			debug("[ px: write to addr 0x%x: 0x%llx ]\n",
-			    (int)relative_addr, (long long)idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-void dev_px_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, int px_type, const char *irq_path)
-{
-	struct px_data *d;
-
-	CHECK_ALLOCATION(d = (struct px_data *) malloc(sizeof(struct px_data)));
-	memset(d, 0, sizeof(struct px_data));
-
-	d->type = px_type;
-
-	INTERRUPT_CONNECT(irq_path, d->irq);
-
-	d->xconfig = d->yconfig = 0;	/*  4x1  */
-
-	d->bitdepth = 24;
-	d->px_name = "(invalid)";
-
-	switch (d->type) {
-	case DEV_PX_TYPE_PX:
-		d->bitdepth = 8;
-		d->px_name = "PX";
-		break;
-	case DEV_PX_TYPE_PXG:
-		d->bitdepth = 8;
-		d->px_name = "PXG";
-		break;
-	case DEV_PX_TYPE_PXGPLUS:
-		d->px_name = "PXG+";
-		break;
-	case DEV_PX_TYPE_PXGPLUSTURBO:
-		d->px_name = "PXG+ TURBO";
-		d->xconfig = d->yconfig = 1;	/*  5x2  */
-		break;
-	default:
-		fatal("dev_px_init(): unimplemented px_type\n");
-	}
-
-	d->fb_mem = memory_new(PX_XSIZE * PX_YSIZE * d->bitdepth / 8,
-	    machine->arch);
-	if (d->fb_mem == NULL) {
-		fprintf(stderr, "dev_px_init(): out of memory (1)\n");
-		exit(1);
-	}
-
-	d->vfb_data = dev_fb_init(machine, d->fb_mem, 0, VFB_GENERIC,
-	    PX_XSIZE, PX_YSIZE, PX_XSIZE, PX_YSIZE, d->bitdepth, d->px_name);
-	if (d->vfb_data == NULL) {
-		fprintf(stderr, "dev_px_init(): out of memory (2)\n");
-		exit(2);
-	}
-
-	switch (d->type) {
-	case DEV_PX_TYPE_PX:
-		dev_bt459_init(machine, mem, baseaddr + 0x200000, 0,
-		    d->vfb_data, 8, irq_path, BT459_PX);
-		break;
-	case DEV_PX_TYPE_PXG:
-	case DEV_PX_TYPE_PXGPLUS:
-	case DEV_PX_TYPE_PXGPLUSTURBO:
-		dev_bt459_init(machine, mem, baseaddr + 0x300000, 0,
-		    d->vfb_data, d->bitdepth, irq_path, BT459_PX);
-		break;
-	default:
-		fatal("dev_px_init(): unimplemented px_type\n");
-	}
-
-	memory_device_register(mem, "px", baseaddr, DEV_PX_LENGTH,
-	    dev_px_access, d, DM_DEFAULT, NULL);
-	machine_add_tickfunction(machine, dev_px_tick, d, 14);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_ram.c gxemul-0.7.0+dfsg/src/devices/dev_ram.c
--- gxemul-0.6.2/src/devices/dev_ram.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ram.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,232 @@
+/*
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: A generic RAM (memory) device
+ *
+ *  Note: This device can also be used to mirror/alias another part of RAM.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/mman.h>
+
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+struct ram_data {
+	uint64_t	baseaddress;
+	const char*	name;
+
+	int		trace;
+	int		mode;
+	uint64_t	otheraddress;
+
+	/*  If mode = DEV_RAM_MIRROR:  */
+	uint64_t	offset;
+
+	/*  If mode = DEV_RAM_RAM:  */
+	unsigned char	*data;
+	uint64_t	length;
+};
+
+
+DEVICE_ACCESS(ram)
+{
+	struct ram_data *d = (struct ram_data *) extra;
+
+	if (cpu->running && d->trace && writeflag == MEM_WRITE) {
+		fatal("[ %s: write %i byte%s from 0x%x:",
+		    d->name, (int)len, len==1? "":"s", (int)relative_addr);
+		for (size_t i=0; i<len; i++)
+			fatal(" %02x", data[i]);
+		fatal(" ]\n");
+	}
+
+	switch (d->mode) {
+
+	case DEV_RAM_MIRROR:
+		/*  TODO:  how about caches?  */
+		{
+			int result = cpu->memory_rw(cpu, mem,
+			    d->otheraddress + relative_addr, data, len,
+			    writeflag, PHYSICAL);
+			    
+			/*  Invalidate any code translations in both the MIRRORED
+			    and the MIRROR address ranges on a write:  */
+			if (writeflag == MEM_WRITE &&
+			    cpu->invalidate_code_translation != NULL) {
+				cpu->invalidate_code_translation(
+				    cpu, d->otheraddress + relative_addr,
+				    INVALIDATE_PADDR);
+				cpu->invalidate_code_translation(
+				    cpu, d->baseaddress + relative_addr,
+				    INVALIDATE_PADDR);
+			}
+
+			if (cpu->running && d->trace && writeflag == MEM_READ) {
+				fatal("[ %s: read %i byte%s from 0x%x:",
+				    d->name, (int)len, len==1? "":"s", (int)relative_addr);
+				for (size_t i=0; i<len; i++)
+					fatal(" %02x", data[i]);
+				fatal(" ]\n");
+			}
+
+			return result;
+		}
+
+	case DEV_RAM_RAM:
+		if (writeflag == MEM_WRITE) {
+			memcpy(&d->data[relative_addr], data, len);
+
+			/*  Invalidate any code translations on a write:  */
+			if (cpu->invalidate_code_translation != NULL) {
+				cpu->invalidate_code_translation(
+				    cpu, d->baseaddress + relative_addr,
+				    INVALIDATE_PADDR);
+			}
+		} else {
+			memcpy(data, &d->data[relative_addr], len);
+
+			if (cpu->running && d->trace) {
+				fatal("[ %s: read %i byte%s from 0x%x:",
+				    d->name, (int)len, len==1? "":"s", (int)relative_addr);
+				for (size_t i=0; i<len; i++)
+					fatal(" %02x", data[i]);
+				fatal(" ]\n");
+			}
+		}
+		break;
+
+	default:
+		fatal("dev_ram_access(): unknown mode %i\n", d->mode);
+		exit(1);
+	}
+
+	return 1;
+}
+
+
+/*
+ *  dev_ram_init():
+ *
+ *  Initializes a RAM or mirror device. Things get a bit complicated because
+ *  of dyntrans (i.e. mirrored memory ranges should be entered into the
+ *  translation arrays just as normal memory and other devices are).
+ */
+void dev_ram_init(struct machine *machine, uint64_t baseaddr, uint64_t length,
+	int mode, uint64_t otheraddress, const char* name)
+{
+	struct ram_data *d;
+	int flags = DM_DEFAULT, points_to_ram = 1;
+
+	CHECK_ALLOCATION(d = (struct ram_data *) malloc(sizeof(struct ram_data)));
+	memset(d, 0, sizeof(struct ram_data));
+
+	d->name = strdup((name == NULL) ? "ram" : name);
+
+	if (mode & DEV_RAM_MIGHT_POINT_TO_DEVICES) {
+		mode &= ~DEV_RAM_MIGHT_POINT_TO_DEVICES;
+		points_to_ram = 0;
+	}
+
+	if (mode & DEV_RAM_TRACE_ALL_ACCESSES) {
+		mode &= ~DEV_RAM_TRACE_ALL_ACCESSES;
+		d->trace = 1;
+	}
+
+	d->mode         = mode;
+	d->baseaddress  = baseaddr;
+	d->otheraddress = otheraddress;
+
+	switch (d->mode) {
+
+	case DEV_RAM_MIRROR:
+		/*
+		 *  Calculate the amount that the mirror memory is offset from
+		 *  the real (physical) memory. This is used in src/memory_rw.c
+		 *  with dyntrans accesses if DM_EMULATED_RAM is set.
+		 */
+		d->offset = baseaddr - otheraddress;
+		
+		{
+			size_t mirrorNameAllocLen = strlen(d->name) + 15;
+			char *mirrorName = (char*) malloc(mirrorNameAllocLen);
+			snprintf(mirrorName, mirrorNameAllocLen, "%s [mirror]", d->name);
+			d->name = mirrorName;
+		}
+
+		/*  Aligned RAM? Then it works with dyntrans.  */
+		if (points_to_ram &&
+		    (baseaddr & (machine->arch_pagesize-1)) == 0 &&
+		    (otheraddress & (machine->arch_pagesize - 1)) == 0 &&
+		    (length & (machine->arch_pagesize - 1)) == 0 &&
+		    !d->trace)
+			flags |= DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK
+			    | DM_EMULATED_RAM;
+
+		memory_device_register(machine->memory, d->name,
+		    baseaddr, length, dev_ram_access, d, flags
+		    | DM_READS_HAVE_NO_SIDE_EFFECTS, (unsigned char*) (void *) &d->offset);
+		break;
+
+	case DEV_RAM_RAM:
+		/*
+		 *  Allocate zero-filled RAM using mmap(). If mmap() failed,
+		 *  try malloc(), but then memset() must also be called, which
+		 *  can be slow for large chunks of memory.
+		 */
+		d->length = length;
+		d->data = (unsigned char *) mmap(NULL, length,
+		    PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
+		if (d->data == NULL) {
+			CHECK_ALLOCATION(d->data = (unsigned char *) malloc(length));
+			memset(d->data, 0, length);
+		}
+
+		/*  Aligned memory? Then it works with dyntrans.  */
+		if ((baseaddr & (machine->arch_pagesize - 1)) == 0 &&
+		    (length & (machine->arch_pagesize - 1)) == 0 &&
+		    !d->trace)
+			flags |= DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK;
+
+		memory_device_register(machine->memory, d->name, baseaddr,
+		    d->length, dev_ram_access, d, flags
+		    | DM_READS_HAVE_NO_SIDE_EFFECTS, d->data);
+		break;
+
+	default:
+		fatal("dev_ram_access(): %s: unknown mode %i\n", d->name, d->mode);
+		exit(1);
+	}
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_ram.cc gxemul-0.7.0+dfsg/src/devices/dev_ram.cc
--- gxemul-0.6.2/src/devices/dev_ram.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ram.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,226 +0,0 @@
-/*
- *  Copyright (C) 2004-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: A generic RAM (memory) device
- *
- *  Note: This device can also be used to mirror/alias another part of RAM.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-#include <sys/mman.h>
-
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-struct ram_data {
-	uint64_t	baseaddress;
-	const char*	name;
-
-	bool		trace;
-	int		mode;
-	uint64_t	otheraddress;
-
-	/*  If mode = DEV_RAM_MIRROR:  */
-	uint64_t	offset;
-
-	/*  If mode = DEV_RAM_RAM:  */
-	unsigned char	*data;
-	uint64_t	length;
-};
-
-
-DEVICE_ACCESS(ram)
-{
-	struct ram_data *d = (struct ram_data *) extra;
-
-	if (cpu->running && d->trace && writeflag == MEM_WRITE) {
-		fatal("[ %s: write %i byte%s from 0x%x:",
-		    d->name, (int)len, len==1? "":"s", (int)relative_addr);
-		for (size_t i=0; i<len; i++)
-			fatal(" %02x", data[i]);
-		fatal(" ]\n");
-	}
-
-	switch (d->mode) {
-
-	case DEV_RAM_MIRROR:
-		/*  TODO:  how about caches?  */
-		{
-			int result = cpu->memory_rw(cpu, mem,
-			    d->otheraddress + relative_addr, data, len,
-			    writeflag, PHYSICAL);
-			    
-			/*  Invalidate any code translations in both the MIRRORED
-			    and the MIRROR address ranges on a write:  */
-			if (writeflag == MEM_WRITE &&
-			    cpu->invalidate_code_translation != NULL) {
-				cpu->invalidate_code_translation(
-				    cpu, d->otheraddress + relative_addr,
-				    INVALIDATE_PADDR);
-				cpu->invalidate_code_translation(
-				    cpu, d->baseaddress + relative_addr,
-				    INVALIDATE_PADDR);
-			}
-
-			if (cpu->running && d->trace && writeflag == MEM_READ) {
-				fatal("[ %s: read %i byte%s from 0x%x:",
-				    d->name, (int)len, len==1? "":"s", (int)relative_addr);
-				for (size_t i=0; i<len; i++)
-					fatal(" %02x", data[i]);
-				fatal(" ]\n");
-			}
-
-			return result;
-		}
-
-	case DEV_RAM_RAM:
-		if (writeflag == MEM_WRITE) {
-			memcpy(&d->data[relative_addr], data, len);
-
-			/*  Invalidate any code translations on a write:  */
-			if (cpu->invalidate_code_translation != NULL) {
-				cpu->invalidate_code_translation(
-				    cpu, d->baseaddress + relative_addr,
-				    INVALIDATE_PADDR);
-			}
-		} else {
-			memcpy(data, &d->data[relative_addr], len);
-
-			if (cpu->running && d->trace && writeflag == MEM_READ) {
-				fatal("[ %s: read %i byte%s from 0x%x:",
-				    d->name, (int)len, len==1? "":"s", (int)relative_addr);
-				for (size_t i=0; i<len; i++)
-					fatal(" %02x", data[i]);
-				fatal(" ]\n");
-			}
-		}
-		break;
-
-	default:
-		fatal("dev_ram_access(): unknown mode %i\n", d->mode);
-		exit(1);
-	}
-
-	return 1;
-}
-
-
-/*
- *  dev_ram_init():
- *
- *  Initializes a RAM or mirror device. Things get a bit complicated because
- *  of dyntrans (i.e. mirrored memory ranges should be entered into the
- *  translation arrays just as normal memory and other devices are).
- */
-void dev_ram_init(struct machine *machine, uint64_t baseaddr, uint64_t length,
-	int mode, uint64_t otheraddress, const char* name)
-{
-	struct ram_data *d;
-	int flags = DM_DEFAULT, points_to_ram = 1;
-
-	CHECK_ALLOCATION(d = (struct ram_data *) malloc(sizeof(struct ram_data)));
-	memset(d, 0, sizeof(struct ram_data));
-
-	d->name = strdup((name == NULL) ? "ram" : name);
-
-	if (mode & DEV_RAM_MIGHT_POINT_TO_DEVICES) {
-		mode &= ~DEV_RAM_MIGHT_POINT_TO_DEVICES;
-		points_to_ram = 0;
-	}
-
-	if (mode & DEV_RAM_TRACE_ALL_ACCESSES) {
-		mode &= ~DEV_RAM_TRACE_ALL_ACCESSES;
-		d->trace = true;
-	}
-
-	d->mode         = mode;
-	d->baseaddress  = baseaddr;
-	d->otheraddress = otheraddress;
-
-	switch (d->mode) {
-
-	case DEV_RAM_MIRROR:
-		/*
-		 *  Calculate the amount that the mirror memory is offset from
-		 *  the real (physical) memory. This is used in src/memory_rw.c
-		 *  with dyntrans accesses if DM_EMULATED_RAM is set.
-		 */
-		d->offset = baseaddr - otheraddress;
-		d->name = (string(d->name) + " [mirror]").c_str();
-
-		/*  Aligned RAM? Then it works with dyntrans.  */
-		if (points_to_ram &&
-		    (baseaddr & (machine->arch_pagesize-1)) == 0 &&
-		    (otheraddress & (machine->arch_pagesize - 1)) == 0 &&
-		    (length & (machine->arch_pagesize - 1)) == 0 &&
-		    !d->trace)
-			flags |= DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK
-			    | DM_EMULATED_RAM;
-
-		memory_device_register(machine->memory, d->name,
-		    baseaddr, length, dev_ram_access, d, flags
-		    | DM_READS_HAVE_NO_SIDE_EFFECTS, (unsigned char*) (void *) &d->offset);
-		break;
-
-	case DEV_RAM_RAM:
-		/*
-		 *  Allocate zero-filled RAM using mmap(). If mmap() failed,
-		 *  try malloc(), but then memset() must also be called, which
-		 *  can be slow for large chunks of memory.
-		 */
-		d->length = length;
-		d->data = (unsigned char *) mmap(NULL, length,
-		    PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
-		if (d->data == NULL) {
-			CHECK_ALLOCATION(d->data = (unsigned char *) malloc(length));
-			memset(d->data, 0, length);
-		}
-
-		/*  Aligned memory? Then it works with dyntrans.  */
-		if ((baseaddr & (machine->arch_pagesize - 1)) == 0 &&
-		    (length & (machine->arch_pagesize - 1)) == 0 &&
-		    !d->trace)
-			flags |= DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK;
-
-		memory_device_register(machine->memory, d->name, baseaddr,
-		    d->length, dev_ram_access, d, flags
-		    | DM_READS_HAVE_NO_SIDE_EFFECTS, d->data);
-		break;
-
-	default:
-		fatal("dev_ram_access(): %s: unknown mode %i\n", d->name, d->mode);
-		exit(1);
-	}
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_random.c gxemul-0.7.0+dfsg/src/devices/dev_random.c
--- gxemul-0.6.2/src/devices/dev_random.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_random.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,61 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: A device which returns random data for reads, discards all writes
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+DEVICE_ACCESS(random)
+{
+	if (writeflag == MEM_READ) {
+		size_t i;
+		for (i=0; i<len; i++)
+			data[i] = random();
+	}
+
+	return 1;
+}
+
+
+DEVINIT(random)
+{
+	memory_device_register(devinit->machine->memory,
+	    devinit->name, devinit->addr, devinit->len,
+	    dev_random_access, NULL, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_random.cc gxemul-0.7.0+dfsg/src/devices/dev_random.cc
--- gxemul-0.6.2/src/devices/dev_random.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_random.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,61 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: A device which returns random data for reads, discards all writes
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-DEVICE_ACCESS(random)
-{
-	if (writeflag == MEM_READ) {
-		size_t i;
-		for (i=0; i<len; i++)
-			data[i] = random();
-	}
-
-	return 1;
-}
-
-
-DEVINIT(random)
-{
-	memory_device_register(devinit->machine->memory,
-	    devinit->name, devinit->addr, devinit->len,
-	    dev_random_access, NULL, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_rs5c313.c gxemul-0.7.0+dfsg/src/devices/dev_rs5c313.c
--- gxemul-0.6.2/src/devices/dev_rs5c313.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_rs5c313.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,127 @@
+/*
+ *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: RICOH RS5C313 Real Time Clock
+ *
+ *  The RS5C313 has 16 registers, see rs5c313reg.h for details. These registers
+ *  are addressed at byte offsets.
+ *
+ *  Note: The only use for this device so far is in the Landisk, connected to
+ *        the SH4 SCI pins. In the Landisk machine, the RS5C313 is placed at
+ *        a fake (high) address in memory.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/rs5c313reg.h"
+
+
+#define	DEV_RS5C313_LENGTH	16
+
+struct rs5c313_data {
+	uint8_t		reg[DEV_RS5C313_LENGTH];
+};
+
+
+/*
+ *  rs5c313_update_time():
+ *
+ *  Set the RS5C313 registers to correspond to the host's clock.
+ */
+static void rs5c313_update_time(struct rs5c313_data *d)
+{
+	struct tm *tmp;
+	time_t timet;
+
+	timet = time(NULL);
+	tmp = gmtime(&timet);
+
+	d->reg[RS5C313_SEC1]   = tmp->tm_sec % 10;
+	d->reg[RS5C313_SEC10]  = tmp->tm_sec / 10;
+	d->reg[RS5C313_MIN1]   = tmp->tm_min % 10;
+	d->reg[RS5C313_MIN10]  = tmp->tm_min / 10;
+	d->reg[RS5C313_HOUR1]  = tmp->tm_hour % 10;
+	d->reg[RS5C313_HOUR10] = tmp->tm_hour / 10;
+
+	/*  WDAY. Zero-based. TODO: Is this correct?  */
+	d->reg[RS5C313_WDAY]   = tmp->tm_wday;
+
+	d->reg[RS5C313_DAY1]   = tmp->tm_mday % 10;
+	d->reg[RS5C313_DAY10]  = tmp->tm_mday / 10;
+	d->reg[RS5C313_MON1]   = (tmp->tm_mon + 1) % 10;
+	d->reg[RS5C313_MON10]  = (tmp->tm_mon + 1) / 10;
+	d->reg[RS5C313_YEAR1]  = tmp->tm_year % 10;
+	d->reg[RS5C313_YEAR10] = (tmp->tm_year / 10) % 10;
+}
+
+
+DEVICE_ACCESS(rs5c313)
+{
+	struct rs5c313_data *d = (struct rs5c313_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	rs5c313_update_time(d);
+
+	/*  Generic register read/write:  */
+	if (writeflag == MEM_WRITE) {
+		idata = memory_readmax64(cpu, data, len);
+		d->reg[relative_addr] = idata & 0x0f;
+	} else {
+		odata = d->reg[relative_addr] & 0x0f;
+		memory_writemax64(cpu, data, len, odata);
+	}
+
+	return 1;
+}
+
+
+DEVINIT(rs5c313)
+{
+	struct rs5c313_data *d;
+
+	CHECK_ALLOCATION(d = (struct rs5c313_data *) malloc(sizeof(struct rs5c313_data)));
+	memset(d, 0, sizeof(struct rs5c313_data));
+
+	/*  Default values:  */
+	d->reg[RS5C313_CTRL] = CTRL_24H;
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_RS5C313_LENGTH,
+	    dev_rs5c313_access, (void *)d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_rs5c313.cc gxemul-0.7.0+dfsg/src/devices/dev_rs5c313.cc
--- gxemul-0.6.2/src/devices/dev_rs5c313.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_rs5c313.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,127 +0,0 @@
-/*
- *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: RICOH RS5C313 Real Time Clock
- *
- *  The RS5C313 has 16 registers, see rs5c313reg.h for details. These registers
- *  are addressed at byte offsets.
- *
- *  Note: The only use for this device so far is in the Landisk, connected to
- *        the SH4 SCI pins. In the Landisk machine, the RS5C313 is placed at
- *        a fake (high) address in memory.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/rs5c313reg.h"
-
-
-#define	DEV_RS5C313_LENGTH	16
-
-struct rs5c313_data {
-	uint8_t		reg[DEV_RS5C313_LENGTH];
-};
-
-
-/*
- *  rs5c313_update_time():
- *
- *  Set the RS5C313 registers to correspond to the host's clock.
- */
-static void rs5c313_update_time(struct rs5c313_data *d)
-{
-	struct tm *tmp;
-	time_t timet;
-
-	timet = time(NULL);
-	tmp = gmtime(&timet);
-
-	d->reg[RS5C313_SEC1]   = tmp->tm_sec % 10;
-	d->reg[RS5C313_SEC10]  = tmp->tm_sec / 10;
-	d->reg[RS5C313_MIN1]   = tmp->tm_min % 10;
-	d->reg[RS5C313_MIN10]  = tmp->tm_min / 10;
-	d->reg[RS5C313_HOUR1]  = tmp->tm_hour % 10;
-	d->reg[RS5C313_HOUR10] = tmp->tm_hour / 10;
-
-	/*  WDAY. Zero-based. TODO: Is this correct?  */
-	d->reg[RS5C313_WDAY]   = tmp->tm_wday;
-
-	d->reg[RS5C313_DAY1]   = tmp->tm_mday % 10;
-	d->reg[RS5C313_DAY10]  = tmp->tm_mday / 10;
-	d->reg[RS5C313_MON1]   = (tmp->tm_mon + 1) % 10;
-	d->reg[RS5C313_MON10]  = (tmp->tm_mon + 1) / 10;
-	d->reg[RS5C313_YEAR1]  = tmp->tm_year % 10;
-	d->reg[RS5C313_YEAR10] = (tmp->tm_year / 10) % 10;
-}
-
-
-DEVICE_ACCESS(rs5c313)
-{
-	struct rs5c313_data *d = (struct rs5c313_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	rs5c313_update_time(d);
-
-	/*  Generic register read/write:  */
-	if (writeflag == MEM_WRITE) {
-		idata = memory_readmax64(cpu, data, len);
-		d->reg[relative_addr] = idata & 0x0f;
-	} else {
-		odata = d->reg[relative_addr] & 0x0f;
-		memory_writemax64(cpu, data, len, odata);
-	}
-
-	return 1;
-}
-
-
-DEVINIT(rs5c313)
-{
-	struct rs5c313_data *d;
-
-	CHECK_ALLOCATION(d = (struct rs5c313_data *) malloc(sizeof(struct rs5c313_data)));
-	memset(d, 0, sizeof(struct rs5c313_data));
-
-	/*  Default values:  */
-	d->reg[RS5C313_CTRL] = CTRL_24H;
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_RS5C313_LENGTH,
-	    dev_rs5c313_access, (void *)d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_rtc.c gxemul-0.7.0+dfsg/src/devices/dev_rtc.c
--- gxemul-0.6.2/src/devices/dev_rtc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_rtc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,178 @@
+/*
+ *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: A generic Real-Time Clock device, for the test machines
+ *
+ *  It can be used to retrieve the current system time, and to cause periodic
+ *  interrupts.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "timer.h"
+
+#include "testmachine/dev_rtc.h"
+
+
+#define	DEV_RTC_TICK_SHIFT	14
+
+struct rtc_data {
+	struct interrupt	irq;
+	int			pending_interrupts;
+
+	int			hz;
+	struct timer		*timer;
+
+	struct timeval		cur_time;	
+};
+
+
+/*
+ *  timer_tick():
+ *
+ *  This function is called d->hz times per second.
+ */
+static void timer_tick(struct timer *t, void *extra)
+{
+        struct rtc_data *d = (struct rtc_data *) extra;
+        d->pending_interrupts ++;
+}
+
+
+DEVICE_TICK(rtc)
+{  
+	struct rtc_data *d = (struct rtc_data *) extra;
+
+	if (d->pending_interrupts > 0)
+		INTERRUPT_ASSERT(d->irq);
+	else
+		INTERRUPT_DEASSERT(d->irq);
+}
+
+
+DEVICE_ACCESS(rtc)
+{
+	struct rtc_data *d = (struct rtc_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case DEV_RTC_TRIGGER_READ:
+		gettimeofday(&d->cur_time, NULL);
+		break;
+
+	case DEV_RTC_SEC:
+		odata = d->cur_time.tv_sec;
+		break;
+
+	case DEV_RTC_USEC:
+		odata = d->cur_time.tv_usec;
+		break;
+
+	case DEV_RTC_HZ:
+		if (writeflag == MEM_READ) {
+			odata = d->hz;
+		} else {
+			d->hz = idata;
+
+			if (d->hz == 0) {
+				/*  Remove the timer, if any:  */
+				if (d->timer != NULL)
+					timer_remove(d->timer);
+
+				d->timer = NULL;
+				d->pending_interrupts = 0;
+			} else {
+				/*  Add a timer, or update the existing one:  */
+				if (d->timer == NULL)
+					d->timer = timer_add(d->hz,
+					    timer_tick, d);
+				else
+					timer_update_frequency(d->timer, d->hz);
+			}
+		}
+		break;
+
+	case DEV_RTC_INTERRUPT_ACK:
+		if (d->pending_interrupts > 0)
+			d->pending_interrupts --;
+
+		INTERRUPT_DEASSERT(d->irq);
+
+		/*  TODO: Reassert the interrupt here, if
+		    d->pending_interrupts is still above zero?  */
+
+		break;
+
+	default:if (writeflag == MEM_WRITE) {
+			fatal("[ rtc: unimplemented write to "
+			    "offset 0x%x: data=0x%x ]\n", (int)
+			    relative_addr, (int)idata);
+		} else {
+			fatal("[ rtc: unimplemented read from "
+			    "offset 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(rtc)
+{
+	struct rtc_data *d;
+
+	CHECK_ALLOCATION(d = (struct rtc_data *) malloc(sizeof(struct rtc_data)));
+	memset(d, 0, sizeof(struct rtc_data));
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_RTC_LENGTH, dev_rtc_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(devinit->machine,
+	    dev_rtc_tick, d, DEV_RTC_TICK_SHIFT);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_rtc.cc gxemul-0.7.0+dfsg/src/devices/dev_rtc.cc
--- gxemul-0.6.2/src/devices/dev_rtc.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_rtc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,178 +0,0 @@
-/*
- *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: A generic Real-Time Clock device, for the test machines
- *
- *  It can be used to retrieve the current system time, and to cause periodic
- *  interrupts.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/time.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "timer.h"
-
-#include "testmachine/dev_rtc.h"
-
-
-#define	DEV_RTC_TICK_SHIFT	14
-
-struct rtc_data {
-	struct interrupt	irq;
-	int			pending_interrupts;
-
-	int			hz;
-	struct timer		*timer;
-
-	struct timeval		cur_time;	
-};
-
-
-/*
- *  timer_tick():
- *
- *  This function is called d->hz times per second.
- */
-static void timer_tick(struct timer *t, void *extra)
-{
-        struct rtc_data *d = (struct rtc_data *) extra;
-        d->pending_interrupts ++;
-}
-
-
-DEVICE_TICK(rtc)
-{  
-	struct rtc_data *d = (struct rtc_data *) extra;
-
-	if (d->pending_interrupts > 0)
-		INTERRUPT_ASSERT(d->irq);
-	else
-		INTERRUPT_DEASSERT(d->irq);
-}
-
-
-DEVICE_ACCESS(rtc)
-{
-	struct rtc_data *d = (struct rtc_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case DEV_RTC_TRIGGER_READ:
-		gettimeofday(&d->cur_time, NULL);
-		break;
-
-	case DEV_RTC_SEC:
-		odata = d->cur_time.tv_sec;
-		break;
-
-	case DEV_RTC_USEC:
-		odata = d->cur_time.tv_usec;
-		break;
-
-	case DEV_RTC_HZ:
-		if (writeflag == MEM_READ) {
-			odata = d->hz;
-		} else {
-			d->hz = idata;
-
-			if (d->hz == 0) {
-				/*  Remove the timer, if any:  */
-				if (d->timer != NULL)
-					timer_remove(d->timer);
-
-				d->timer = NULL;
-				d->pending_interrupts = 0;
-			} else {
-				/*  Add a timer, or update the existing one:  */
-				if (d->timer == NULL)
-					d->timer = timer_add(d->hz,
-					    timer_tick, d);
-				else
-					timer_update_frequency(d->timer, d->hz);
-			}
-		}
-		break;
-
-	case DEV_RTC_INTERRUPT_ACK:
-		if (d->pending_interrupts > 0)
-			d->pending_interrupts --;
-
-		INTERRUPT_DEASSERT(d->irq);
-
-		/*  TODO: Reassert the interrupt here, if
-		    d->pending_interrupts is still above zero?  */
-
-		break;
-
-	default:if (writeflag == MEM_WRITE) {
-			fatal("[ rtc: unimplemented write to "
-			    "offset 0x%x: data=0x%x ]\n", (int)
-			    relative_addr, (int)idata);
-		} else {
-			fatal("[ rtc: unimplemented read from "
-			    "offset 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(rtc)
-{
-	struct rtc_data *d;
-
-	CHECK_ALLOCATION(d = (struct rtc_data *) malloc(sizeof(struct rtc_data)));
-	memset(d, 0, sizeof(struct rtc_data));
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_RTC_LENGTH, dev_rtc_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(devinit->machine,
-	    dev_rtc_tick, d, DEV_RTC_TICK_SHIFT);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_rtl8139c.c gxemul-0.7.0+dfsg/src/devices/dev_rtl8139c.c
--- gxemul-0.6.2/src/devices/dev_rtl8139c.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_rtl8139c.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,232 @@
+/*
+ *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Realtek 8139 ethernet controller
+ *
+ *  TODO: Pretty much everything.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "net.h"
+
+#include "thirdparty/rtl81x9reg.h"
+
+
+#define	DEV_RTL8139C_LENGTH	0x100
+#define	EEPROM_SIZE		0x100
+
+struct rtl8139c_data {
+	struct nic_data		nic;
+
+	struct interrupt	irq;
+
+	/*  Registers:  */
+	uint8_t			rl_command;
+	uint8_t			rl_eecmd;
+
+	/*  EEPROM:  */
+	int			eeprom_address_width;
+	int			eeprom_selected;
+	int8_t			eeprom_cur_cmd_bit;
+	uint16_t		eeprom_cur_cmd;
+	uint16_t		eeprom_cur_data;
+	uint16_t		eeprom_reg[EEPROM_SIZE];
+};
+
+
+/*
+ *  eeprom_clk():
+ *
+ *  Called whenever the eeprom CLK bit is toggled from 0 to 1.
+ */
+static void eeprom_clk(struct rtl8139c_data *d)
+{
+	int data_in = d->rl_eecmd & RL_EE_DATAIN? 1 : 0;
+
+	if (d->eeprom_cur_cmd_bit < d->eeprom_address_width + 4) {
+		d->eeprom_cur_cmd <<= 1;
+		d->eeprom_cur_cmd |= data_in;
+	}
+
+	if (d->eeprom_cur_cmd_bit == d->eeprom_address_width + 3) {
+		int cmd = d->eeprom_cur_cmd >> d->eeprom_address_width;
+		int addr = d->eeprom_cur_cmd & ((1<<d->eeprom_address_width)-1);
+
+		debug("[ rtl8139c eeprom cmd=0x%x addr=0x%02x ]\n", cmd, addr);
+
+		switch (cmd) {
+
+		case RL_9346_READ:
+			d->eeprom_cur_data = d->eeprom_reg[addr % EEPROM_SIZE];
+			break;
+
+		default:fatal("[ rtl8139c eeprom: only the read command has"
+			    " been implemented. sorry. ]\n");
+			exit(1);
+		}
+	}
+
+	/*  Data output: (Note: Only the READ command has been implemented.)  */
+	if (d->eeprom_cur_cmd_bit >= d->eeprom_address_width + 4) {
+		int cur_out_bit = d->eeprom_cur_cmd_bit -
+		    (d->eeprom_address_width + 4);
+		int bit = d->eeprom_cur_data & (1 << (15-cur_out_bit));
+
+		if (bit)
+			d->rl_eecmd |= RL_EE_DATAOUT;
+		else
+			d->rl_eecmd &= ~RL_EE_DATAOUT;
+	}
+
+	d->eeprom_cur_cmd_bit ++;
+
+	if (d->eeprom_cur_cmd_bit >= d->eeprom_address_width + 4 + 16) {
+		d->eeprom_cur_cmd = 0;
+		d->eeprom_cur_cmd_bit = 0;
+	}
+}
+
+
+DEVICE_ACCESS(rtl8139c)
+{
+	struct rtl8139c_data *d = (struct rtl8139c_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case RL_COMMAND:
+		if (writeflag == MEM_WRITE) {
+			if (idata & RL_CMD_RESET) {
+				/*  Reset. TODO  */
+
+				/*  ... and then clear the reset bit:  */
+				idata &= ~RL_CMD_RESET;
+			}
+
+			d->rl_command = idata;
+		} else {
+			odata = d->rl_command;
+		}
+		break;
+
+	case RL_EECMD:
+		if (writeflag == MEM_WRITE) {
+			uint8_t old = d->rl_eecmd;
+			d->rl_eecmd = idata;
+
+			if (!d->eeprom_selected && d->rl_eecmd & RL_EE_SEL) {
+				/*  Reset eeprom cmd bit state:  */
+				d->eeprom_cur_cmd = 0;
+				d->eeprom_cur_cmd_bit = 0;
+			}
+			d->eeprom_selected = d->rl_eecmd & RL_EE_SEL;
+
+			if (idata & RL_EE_CLK && !(old & RL_EE_CLK))
+				eeprom_clk(d);
+		} else {
+			odata = d->rl_eecmd;
+		}
+		break;
+
+	case 0x82:
+		/*  Unknown address, but OpenBSD's re driver writes
+		    a 0x01 to this address, in re_reset().  */
+		if (writeflag == MEM_WRITE) {
+			if (idata != 0x01) {
+				fatal("rtl8139c: unimplemented write to"
+				    " register 0x82.\n");
+				exit(1);
+			}
+		}
+		break;
+
+	default:if (writeflag == MEM_WRITE) {
+			fatal("[ rtl8139c: unimplemented write to "
+			    "offset 0x%x: data=0x%x ]\n", (int)
+			    relative_addr, (int)idata);
+		} else {
+			fatal("[ rtl8139c: unimplemented read from "
+			    "offset 0x%x ]\n", (int)relative_addr);
+		}
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(rtl8139c)
+{
+	char *name2;
+	size_t nlen = 100;
+	struct rtl8139c_data *d;
+
+	CHECK_ALLOCATION(d = (struct rtl8139c_data *) malloc(sizeof(struct rtl8139c_data)));
+	memset(d, 0, sizeof(struct rtl8139c_data));
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	net_generate_unique_mac(devinit->machine, d->nic.mac_address);
+
+	/*  TODO: eeprom address width = 6 on 8129?  */
+	d->eeprom_address_width = 8;
+	d->eeprom_reg[0] = 0x8139;
+	d->eeprom_reg[7] = d->nic.mac_address[0] + (d->nic.mac_address[1] << 8);
+	d->eeprom_reg[8] = d->nic.mac_address[2] + (d->nic.mac_address[3] << 8);
+	d->eeprom_reg[9] = d->nic.mac_address[4] + (d->nic.mac_address[5] << 8);
+
+	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
+	snprintf(name2, nlen, "%s [%02x:%02x:%02x:%02x:%02x:%02x]",
+	    devinit->name, d->nic.mac_address[0], d->nic.mac_address[1],
+	    d->nic.mac_address[2], d->nic.mac_address[3],
+	    d->nic.mac_address[4], d->nic.mac_address[5]);
+
+	memory_device_register(devinit->machine->memory, name2,
+	    devinit->addr, DEV_RTL8139C_LENGTH, dev_rtl8139c_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	net_add_nic(devinit->machine->emul->net, &d->nic);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_rtl8139c.cc gxemul-0.7.0+dfsg/src/devices/dev_rtl8139c.cc
--- gxemul-0.6.2/src/devices/dev_rtl8139c.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_rtl8139c.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,230 +0,0 @@
-/*
- *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Realtek 8139 ethernet controller
- *
- *  TODO: Pretty much everything.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "net.h"
-
-#include "thirdparty/rtl81x9reg.h"
-
-
-#define	DEV_RTL8139C_LENGTH	0x100
-#define	EEPROM_SIZE		0x100
-
-struct rtl8139c_data {
-	struct interrupt	irq;
-	unsigned char		macaddr[6];
-
-	/*  Registers:  */
-	uint8_t			rl_command;
-	uint8_t			rl_eecmd;
-
-	/*  EEPROM:  */
-	int			eeprom_address_width;
-	int			eeprom_selected;
-	int8_t			eeprom_cur_cmd_bit;
-	uint16_t		eeprom_cur_cmd;
-	uint16_t		eeprom_cur_data;
-	uint16_t		eeprom_reg[EEPROM_SIZE];
-};
-
-
-/*
- *  eeprom_clk():
- *
- *  Called whenever the eeprom CLK bit is toggled from 0 to 1.
- */
-static void eeprom_clk(struct rtl8139c_data *d)
-{
-	int data_in = d->rl_eecmd & RL_EE_DATAIN? 1 : 0;
-
-	if (d->eeprom_cur_cmd_bit < d->eeprom_address_width + 4) {
-		d->eeprom_cur_cmd <<= 1;
-		d->eeprom_cur_cmd |= data_in;
-	}
-
-	if (d->eeprom_cur_cmd_bit == d->eeprom_address_width + 3) {
-		int cmd = d->eeprom_cur_cmd >> d->eeprom_address_width;
-		int addr = d->eeprom_cur_cmd & ((1<<d->eeprom_address_width)-1);
-
-		debug("[ rtl8139c eeprom cmd=0x%x addr=0x%02x ]\n", cmd, addr);
-
-		switch (cmd) {
-
-		case RL_9346_READ:
-			d->eeprom_cur_data = d->eeprom_reg[addr % EEPROM_SIZE];
-			break;
-
-		default:fatal("[ rtl8139c eeprom: only the read command has"
-			    " been implemented. sorry. ]\n");
-			exit(1);
-		}
-	}
-
-	/*  Data output: (Note: Only the READ command has been implemented.)  */
-	if (d->eeprom_cur_cmd_bit >= d->eeprom_address_width + 4) {
-		int cur_out_bit = d->eeprom_cur_cmd_bit -
-		    (d->eeprom_address_width + 4);
-		int bit = d->eeprom_cur_data & (1 << (15-cur_out_bit));
-
-		if (bit)
-			d->rl_eecmd |= RL_EE_DATAOUT;
-		else
-			d->rl_eecmd &= ~RL_EE_DATAOUT;
-	}
-
-	d->eeprom_cur_cmd_bit ++;
-
-	if (d->eeprom_cur_cmd_bit >= d->eeprom_address_width + 4 + 16) {
-		d->eeprom_cur_cmd = 0;
-		d->eeprom_cur_cmd_bit = 0;
-	}
-}
-
-
-DEVICE_ACCESS(rtl8139c)
-{
-	struct rtl8139c_data *d = (struct rtl8139c_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case RL_COMMAND:
-		if (writeflag == MEM_WRITE) {
-			if (idata & RL_CMD_RESET) {
-				/*  Reset. TODO  */
-
-				/*  ... and then clear the reset bit:  */
-				idata &= ~RL_CMD_RESET;
-			}
-
-			d->rl_command = idata;
-		} else {
-			odata = d->rl_command;
-		}
-		break;
-
-	case RL_EECMD:
-		if (writeflag == MEM_WRITE) {
-			uint8_t old = d->rl_eecmd;
-			d->rl_eecmd = idata;
-
-			if (!d->eeprom_selected && d->rl_eecmd & RL_EE_SEL) {
-				/*  Reset eeprom cmd bit state:  */
-				d->eeprom_cur_cmd = 0;
-				d->eeprom_cur_cmd_bit = 0;
-			}
-			d->eeprom_selected = d->rl_eecmd & RL_EE_SEL;
-
-			if (idata & RL_EE_CLK && !(old & RL_EE_CLK))
-				eeprom_clk(d);
-		} else {
-			odata = d->rl_eecmd;
-		}
-		break;
-
-	case 0x82:
-		/*  Unknown address, but OpenBSD's re driver writes
-		    a 0x01 to this address, in re_reset().  */
-		if (writeflag == MEM_WRITE) {
-			if (idata != 0x01) {
-				fatal("rtl8139c: unimplemented write to"
-				    " register 0x82.\n");
-				exit(1);
-			}
-		}
-		break;
-
-	default:if (writeflag == MEM_WRITE) {
-			fatal("[ rtl8139c: unimplemented write to "
-			    "offset 0x%x: data=0x%x ]\n", (int)
-			    relative_addr, (int)idata);
-		} else {
-			fatal("[ rtl8139c: unimplemented read from "
-			    "offset 0x%x ]\n", (int)relative_addr);
-		}
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(rtl8139c)
-{
-	char *name2;
-	size_t nlen = 100;
-	struct rtl8139c_data *d;
-
-	CHECK_ALLOCATION(d = (struct rtl8139c_data *) malloc(sizeof(struct rtl8139c_data)));
-	memset(d, 0, sizeof(struct rtl8139c_data));
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	net_generate_unique_mac(devinit->machine, d->macaddr);
-
-	/*  TODO: eeprom address width = 6 on 8129?  */
-	d->eeprom_address_width = 8;
-	d->eeprom_reg[0] = 0x8139;
-	d->eeprom_reg[7] = d->macaddr[0] + (d->macaddr[1] << 8);
-	d->eeprom_reg[8] = d->macaddr[2] + (d->macaddr[3] << 8);
-	d->eeprom_reg[9] = d->macaddr[4] + (d->macaddr[5] << 8);
-
-	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
-	snprintf(name2, nlen, "%s [%02x:%02x:%02x:%02x:%02x:%02x]",
-	    devinit->name, d->macaddr[0], d->macaddr[1], d->macaddr[2],
-	    d->macaddr[3], d->macaddr[4], d->macaddr[5]);
-
-	memory_device_register(devinit->machine->memory, name2,
-	    devinit->addr, DEV_RTL8139C_LENGTH, dev_rtl8139c_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	net_add_nic(devinit->machine->emul->net, d, d->macaddr);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_scc.c gxemul-0.7.0+dfsg/src/devices/dev_scc.c
--- gxemul-0.6.2/src/devices/dev_scc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_scc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,508 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Serial controller used in some DECsystem and SGI machines
+ *
+ *  Hm... Same as Z8530? Most of the code in here is written for DECsystem
+ *  emulation, though.
+ *
+ *  NOTE:
+ *	Each scc device is responsible for two lines; the first scc device
+ *	controls mouse (0) and keyboard (1), and the second device controls
+ *	serial ports (2 and 3).
+ *
+ *  TODO:
+ *	Mouse support!!!  (scc0 and scc1 need to cooperate, in order to
+ *		emulate the same lk201 behaviour as when using the dc device)
+ *	DMA
+ *	More correct interrupt support.
+ *
+ ******************************************************************************
+ *	 _____ ___  ____   ___  _ 
+ *	|_   _/ _ \|  _ \ / _ \| |
+ *	  | || | | | | | | | | | |
+ *	  | || |_| | |_| | |_| |_|
+ *	  |_| \___/|____/ \___/(_)
+ *
+ *	Since this is actually a Z8530, it should be merged with dev_z8530.c!
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/sccreg.h"
+
+
+#define	SCC_TICK_SHIFT		14
+
+#define	N_SCC_PORTS		2
+#define	N_SCC_REGS		16
+#define	MAX_QUEUE_LEN		1024
+
+/*  #define SCC_DEBUG  */
+
+
+struct scc_data {
+	struct interrupt	irq;
+
+	int		use_fb;
+	int		console_handle;
+
+	int		scc_nr;
+	int		addrmul;
+
+	int		register_select_in_progress[N_SCC_PORTS];
+	int		register_selected[N_SCC_PORTS];
+
+	unsigned char	scc_register_r[N_SCC_PORTS * N_SCC_REGS];
+	unsigned char	scc_register_w[N_SCC_PORTS * N_SCC_REGS];
+
+	unsigned char	rx_queue_char[N_SCC_PORTS * MAX_QUEUE_LEN];
+	int		cur_rx_queue_pos_write[N_SCC_PORTS];
+	int		cur_rx_queue_pos_read[N_SCC_PORTS];
+
+	struct lk201_data lk201;
+};
+
+
+/*
+ *  Check if space is available in the receive queue.
+ */
+int dev_scc_space_available_in_queue(void *e, int portnr)
+{
+	struct scc_data *d = (struct scc_data *) e;
+
+	int entries_in_use = d->cur_rx_queue_pos_write[portnr] -
+	    d->cur_rx_queue_pos_read[portnr];
+
+	while (entries_in_use < 0)
+		entries_in_use += MAX_QUEUE_LEN;
+
+	if (entries_in_use < MAX_QUEUE_LEN - 20)
+		return 1;
+
+	return 0;
+}
+
+
+/*
+ *  dev_scc_add_to_rx_queue():
+ *
+ *  Add a character to the receive queue.
+ */
+void dev_scc_add_to_rx_queue(void *e, int ch, int portnr)
+{ 
+	struct scc_data *d = (struct scc_data *) e;
+	int scc_nr;
+
+	/*  DC's keyboard port ==> SCC keyboard port  */
+	if (portnr == 0)
+		portnr = 3;
+
+	scc_nr = portnr / N_SCC_PORTS;
+	if (scc_nr != d->scc_nr)
+		return;
+
+	portnr &= (N_SCC_PORTS - 1);
+
+        d->rx_queue_char[portnr * MAX_QUEUE_LEN +
+	    d->cur_rx_queue_pos_write[portnr]] = ch; 
+        d->cur_rx_queue_pos_write[portnr] ++;
+        if (d->cur_rx_queue_pos_write[portnr] == MAX_QUEUE_LEN)
+                d->cur_rx_queue_pos_write[portnr] = 0;
+
+        if (d->cur_rx_queue_pos_write[portnr] ==
+	    d->cur_rx_queue_pos_read[portnr])
+                fatal("warning: add_to_rx_queue(): rx_queue overrun!\n");
+}
+
+
+static int rx_avail(struct scc_data *d, int portnr)
+{
+	return d->cur_rx_queue_pos_write[portnr] !=
+	    d->cur_rx_queue_pos_read[portnr];
+}
+
+
+static unsigned char rx_nextchar(struct scc_data *d, int portnr)
+{
+	unsigned char ch;
+	ch = d->rx_queue_char[portnr * MAX_QUEUE_LEN +
+	    d->cur_rx_queue_pos_read[portnr]];
+	d->cur_rx_queue_pos_read[portnr]++;
+	if (d->cur_rx_queue_pos_read[portnr] == MAX_QUEUE_LEN)
+		d->cur_rx_queue_pos_read[portnr] = 0;
+	return ch;
+}
+
+
+DEVICE_TICK(scc)
+{
+	struct scc_data *d = (struct scc_data *) extra;
+	int i;
+
+	/*  Add keystrokes to the rx queue:  */
+	if (d->scc_nr == 1) {
+		if (d->use_fb == 0) {
+			if (console_charavail(d->console_handle))
+				dev_scc_add_to_rx_queue(extra, console_readchar(
+			    d->console_handle), 2);
+		} else if (d->use_fb == 1)
+			lk201_tick(cpu->machine, &d->lk201);
+	}
+
+	for (i=0; i<N_SCC_PORTS; i++) {
+		d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |= SCC_RR0_TX_EMPTY;
+		d->scc_register_r[i * N_SCC_REGS + SCC_RR1] = 0;
+		    /*  No receive errors  */
+
+		d->scc_register_r[i * N_SCC_REGS + SCC_RR0] &=
+		    ~SCC_RR0_RX_AVAIL;
+		if (rx_avail(d, i))
+			d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |=
+			    SCC_RR0_RX_AVAIL;
+
+		/*
+		 *  Interrupts:
+		 *  (NOTE: Interrupt enables are always at channel A)
+		 */
+		if (d->scc_register_w[N_SCC_REGS + SCC_WR9] &
+		    SCC_WR9_MASTER_IE) {
+			/*  TX interrupts?  */
+			if (d->scc_register_w[i * N_SCC_REGS + SCC_WR1] &
+			    SCC_WR1_TX_IE) {
+				if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
+				    & SCC_RR3_TX_IP_A ||
+				    d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
+				    & SCC_RR3_TX_IP_B) {
+					INTERRUPT_ASSERT(d->irq);
+				}
+			}
+
+			/*  RX interrupts?  */
+			if (d->scc_register_w[N_SCC_REGS + SCC_WR1] &
+			    (SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_RXI_ALL_CHAR)) {
+				if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0]
+				    & SCC_RR0_RX_AVAIL) {
+					if (i == SCC_CHANNEL_A)
+						d->scc_register_r[N_SCC_REGS +
+						    SCC_RR3] |= SCC_RR3_RX_IP_A;
+					else
+						d->scc_register_r[N_SCC_REGS +
+						    SCC_RR3] |= SCC_RR3_RX_IP_B;
+				}
+
+				if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
+				    & SCC_RR3_RX_IP_A ||
+				    d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
+				    & SCC_RR3_RX_IP_B) {
+					INTERRUPT_ASSERT(d->irq);
+				}
+			}
+
+			if (d->scc_register_w[N_SCC_REGS + SCC_WR1] &
+			    SCC_WR1_DMA_MODE) {
+				if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0]
+				    & SCC_RR0_RX_AVAIL) {
+					if (i == SCC_CHANNEL_A)
+						d->scc_register_r[N_SCC_REGS +
+						    SCC_RR3] |=
+						    SCC_RR3_EXT_IP_A;
+					else
+						d->scc_register_r[N_SCC_REGS +
+						    SCC_RR3] |=
+						    SCC_RR3_EXT_IP_B;
+				}
+
+				if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
+				    & SCC_RR3_EXT_IP_A ||
+				    d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
+				    & SCC_RR3_EXT_IP_B) {
+					INTERRUPT_ASSERT(d->irq);
+				}
+			}
+		}
+	}
+}
+
+
+/*
+ *  dev_scc_dma_func():
+ */
+int dev_scc_dma_func(struct cpu *cpu, void *extra, uint64_t addr,
+	size_t dma_len, int tx)
+{
+	/*  printf("dev_scc_dma_func(): addr = %08x, len = %i\n",
+	    (int)addr, (int)dma_len);  */
+	unsigned char word[4];
+	struct scc_data *d = (struct scc_data *) extra;
+	int n;
+
+	int port = SCC_CHANNEL_A;	/*  TODO  */
+
+	if (tx) {
+		do {
+			cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
+			    sizeof(word), MEM_READ, NO_EXCEPTIONS | PHYSICAL);
+
+			lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, word[1]);
+			/*  Loopback:  */
+			if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14]
+			    & SCC_WR14_LOCAL_LOOPB)
+				dev_scc_add_to_rx_queue(d, word[1],
+				    d->scc_nr * 2 + port);
+
+			addr += sizeof(word);
+		} while ((addr & 0xffc) != 0);
+
+		dev_scc_tick(cpu, extra);
+		return 1;
+	} else {
+		printf("dev_scc_dma_func(): addr = %08x, len = %i\n",
+		    (int)addr, (int)dma_len);
+
+
+/*  TODO: all this is just nonsense  */
+
+		n = 0;
+		while (rx_avail(d, port)) {
+			word[0] = word[1] = word[2] = word[3] = 0;
+			word[0] = word[1] = word[2] = word[3] =
+			    rx_nextchar(d, port);
+			n++;
+			cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
+			    sizeof(word), MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
+
+			addr += sizeof(word);
+			/*  Half-page?  */
+			if ((addr & 0x7fc) == 0)
+				break;
+		}
+		dev_scc_tick(cpu, extra);
+		return n*4;
+	}
+}
+
+
+DEVICE_ACCESS(scc)
+{
+	struct scc_data *d = (struct scc_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int port;
+	int ultrix_mode = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  relative_addr /= d->addrmul;  */
+		/*  See SGI comment below instead.  */
+	/*
+	 *  SGI writes command to 0x0f, and data to 0x1f.
+	 *  (TODO: This works for port nr 0, how about port nr 1?)
+	 */
+	if ((relative_addr & 0x0f) == 0xf) {
+		if (relative_addr == 0x0f)
+			relative_addr = 1;
+		else
+			relative_addr = 5;
+	}
+
+	port = relative_addr / 8;
+	relative_addr &= 7;
+
+	dev_scc_tick(cpu, extra);
+
+	/*
+	 *  Ultrix writes words such as 0x1200 to relative address 0,
+	 *  instead of writing the byte 0x12 directly to address 1.
+	 */
+	if ((relative_addr == 0 || relative_addr == 4) && (idata & 0xff) == 0) {
+		ultrix_mode = 1;
+		relative_addr ++;
+		idata >>= 8;
+	}
+
+	switch (relative_addr) {
+	case 1:		/*  command  */
+		if (writeflag==MEM_READ) {
+			odata = d->scc_register_r[port * N_SCC_REGS +
+			    d->register_selected[port]];
+
+			if (d->register_selected[port] == SCC_RR3) {
+				if (port == SCC_CHANNEL_B)
+					fatal("WARNING! scc channel B has "
+					    "no RR3\n");
+
+				d->scc_register_r[port * N_SCC_REGS +
+				    SCC_RR3] = 0;
+
+				INTERRUPT_DEASSERT(d->irq);
+			}
+
+#ifdef SCC_DEBUG
+			fatal("[ scc: port %i, register %i, read value "
+			    "0x%02x ]\n", port, d->register_selected[port],
+			    (int)odata);
+#endif
+			d->register_select_in_progress[port] = 0;
+			d->register_selected[port] = 0;
+			/*  debug("[ scc: (port %i) read from 0x%08lx ]\n",
+			    port, (long)relative_addr);  */
+		} else {
+			/*  If no register is selected, then select one.
+			    Otherwise, write to the selected register.  */
+			if (d->register_select_in_progress[port] == 0) {
+				d->register_select_in_progress[port] = 1;
+				d->register_selected[port] = idata;
+				d->register_selected[port] &= (N_SCC_REGS-1);
+			} else {
+				d->scc_register_w[port * N_SCC_REGS +
+				    d->register_selected[port]] = idata;
+#ifdef SCC_DEBUG
+				fatal("[ scc: port %i, register %i, write "
+				    "value 0x%02x ]\n", port,
+				    d->register_selected[port], idata);
+#endif
+
+				d->scc_register_r[port * N_SCC_REGS +
+				    SCC_RR12] = d->scc_register_w[port *
+				    N_SCC_REGS + SCC_WR12];
+				d->scc_register_r[port * N_SCC_REGS +
+				    SCC_RR13] = d->scc_register_w[port *
+				    N_SCC_REGS + SCC_WR13];
+
+				d->register_select_in_progress[port] = 0;
+				d->register_selected[port] = 0;
+			}
+		}
+		break;
+	case 5:		/*  data  */
+		if (writeflag==MEM_READ) {
+			if (rx_avail(d, port))
+				odata = rx_nextchar(d, port);
+
+			/*  TODO:  perhaps only clear the RX part of RR3?  */
+			d->scc_register_r[N_SCC_REGS + SCC_RR3] = 0;
+
+			INTERRUPT_DEASSERT(d->irq);
+
+//			debug("[ scc: (port %i) read from 0x%08lx: 0x%02x ]\n",
+//			    port, (long)relative_addr, (int)odata);
+		} else {
+			/*  debug("[ scc: (port %i) write to  0x%08lx: "
+			    "0x%08x ]\n", port, (long)relative_addr,
+			    (int)idata);  */
+
+			/*  Send the character:  */
+			lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, idata);
+
+			/*  Loopback:  */
+			if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14]
+			    & SCC_WR14_LOCAL_LOOPB)
+				dev_scc_add_to_rx_queue(d, idata, d->scc_nr
+				    * 2 + port);
+
+			/*  TX interrupt:  */
+			if (d->scc_register_w[port * N_SCC_REGS + SCC_WR9] &
+			    SCC_WR9_MASTER_IE &&
+			    d->scc_register_w[port * N_SCC_REGS + SCC_WR1] &
+			    SCC_WR1_TX_IE) {
+				if (port == SCC_CHANNEL_A)
+					d->scc_register_r[N_SCC_REGS + SCC_RR3]
+					    |= SCC_RR3_TX_IP_A;
+				else
+					d->scc_register_r[N_SCC_REGS + SCC_RR3]
+					    |= SCC_RR3_TX_IP_B;
+			}
+
+			dev_scc_tick(cpu, extra);
+		}
+		break;
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ scc: (port %i) read from 0x%08lx ]\n",
+			    port, (long)relative_addr);
+		} else {
+			debug("[ scc: (port %i) write to  0x%08lx: 0x%08x ]\n",
+			    port, (long)relative_addr, (int)idata);
+		}
+	}
+
+	if (ultrix_mode && writeflag == MEM_READ) {
+		odata <<= 8;
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_scc_init():
+ *
+ *	use_fb = non-zero when using graphical console + keyboard
+ *	scc_nr = 0 or 1
+ *	addmul = 1 in most cases, 8 on SGI?
+ */
+void *dev_scc_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, char* irq_path, int use_fb, int scc_nr, int addrmul)
+{
+	struct scc_data *d;
+
+	CHECK_ALLOCATION(d = (struct scc_data *) malloc(sizeof(struct scc_data)));
+	memset(d, 0, sizeof(struct scc_data));
+
+	INTERRUPT_CONNECT(irq_path, d->irq);
+	d->scc_nr  = scc_nr;
+	d->use_fb  = use_fb;
+	d->addrmul = addrmul;
+	d->console_handle = console_start_slave(machine, "SCC", 1);
+
+	d->scc_register_r[SCC_RR0] |= SCC_RR0_TX_UNDERRUN;
+
+	lk201_init(&d->lk201, use_fb,
+	    dev_scc_space_available_in_queue,
+	    dev_scc_add_to_rx_queue,
+	    d->console_handle, d);
+
+	memory_device_register(mem, "scc", baseaddr, DEV_SCC_LENGTH,
+	    dev_scc_access, d, DM_DEFAULT, NULL);
+	machine_add_tickfunction(machine, dev_scc_tick, d, SCC_TICK_SHIFT);
+
+	return (void *) d;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_scc.cc gxemul-0.7.0+dfsg/src/devices/dev_scc.cc
--- gxemul-0.6.2/src/devices/dev_scc.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_scc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,486 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Serial controller used in some DECsystem and SGI machines
- *
- *  Hm... Same as Z8530? Most of the code in here is written for DECsystem
- *  emulation, though.
- *
- *  NOTE:
- *	Each scc device is responsible for two lines; the first scc device
- *	controls mouse (0) and keyboard (1), and the second device controls
- *	serial ports (2 and 3).
- *
- *  TODO:
- *	Mouse support!!!  (scc0 and scc1 need to cooperate, in order to
- *		emulate the same lk201 behaviour as when using the dc device)
- *	DMA
- *	More correct interrupt support.
- *
- ******************************************************************************
- *	 _____ ___  ____   ___  _ 
- *	|_   _/ _ \|  _ \ / _ \| |
- *	  | || | | | | | | | | | |
- *	  | || |_| | |_| | |_| |_|
- *	  |_| \___/|____/ \___/(_)
- *
- *	Since this is actually a Z8530, it should be merged with dev_z8530.c!
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/sccreg.h"
-
-
-#define	SCC_TICK_SHIFT		14
-
-#define	N_SCC_PORTS		2
-#define	N_SCC_REGS		16
-#define	MAX_QUEUE_LEN		1024
-
-/*  #define SCC_DEBUG  */
-
-
-struct scc_data {
-	struct interrupt	irq;
-
-	int		use_fb;
-	int		console_handle;
-
-	int		scc_nr;
-	int		addrmul;
-
-	int		register_select_in_progress[N_SCC_PORTS];
-	int		register_selected[N_SCC_PORTS];
-
-	unsigned char	scc_register_r[N_SCC_PORTS * N_SCC_REGS];
-	unsigned char	scc_register_w[N_SCC_PORTS * N_SCC_REGS];
-
-	unsigned char	rx_queue_char[N_SCC_PORTS * MAX_QUEUE_LEN];
-	int		cur_rx_queue_pos_write[N_SCC_PORTS];
-	int		cur_rx_queue_pos_read[N_SCC_PORTS];
-
-	struct lk201_data lk201;
-};
-
-
-/*
- *  dev_scc_add_to_rx_queue():
- *
- *  Add a character to the receive queue.
- */
-void dev_scc_add_to_rx_queue(void *e, int ch, int portnr)
-{ 
-	struct scc_data *d = (struct scc_data *) e;
-	int scc_nr;
-
-	/*  DC's keyboard port ==> SCC keyboard port  */
-	if (portnr == 0)
-		portnr = 3;
-
-	scc_nr = portnr / N_SCC_PORTS;
-	if (scc_nr != d->scc_nr)
-		return;
-
-	portnr &= (N_SCC_PORTS - 1);
-
-        d->rx_queue_char[portnr * MAX_QUEUE_LEN +
-	    d->cur_rx_queue_pos_write[portnr]] = ch; 
-        d->cur_rx_queue_pos_write[portnr] ++;
-        if (d->cur_rx_queue_pos_write[portnr] == MAX_QUEUE_LEN)
-                d->cur_rx_queue_pos_write[portnr] = 0;
-
-        if (d->cur_rx_queue_pos_write[portnr] ==
-	    d->cur_rx_queue_pos_read[portnr])
-                fatal("warning: add_to_rx_queue(): rx_queue overrun!\n");
-}
-
-
-static int rx_avail(struct scc_data *d, int portnr)
-{
-	return d->cur_rx_queue_pos_write[portnr] !=
-	    d->cur_rx_queue_pos_read[portnr];
-}
-
-
-static unsigned char rx_nextchar(struct scc_data *d, int portnr)
-{
-	unsigned char ch;
-	ch = d->rx_queue_char[portnr * MAX_QUEUE_LEN +
-	    d->cur_rx_queue_pos_read[portnr]];
-	d->cur_rx_queue_pos_read[portnr]++;
-	if (d->cur_rx_queue_pos_read[portnr] == MAX_QUEUE_LEN)
-		d->cur_rx_queue_pos_read[portnr] = 0;
-	return ch;
-}
-
-
-DEVICE_TICK(scc)
-{
-	struct scc_data *d = (struct scc_data *) extra;
-	int i;
-
-	/*  Add keystrokes to the rx queue:  */
-	if (d->scc_nr == 1) {
-		if (d->use_fb == 0) {
-			if (console_charavail(d->console_handle))
-				dev_scc_add_to_rx_queue(extra, console_readchar(
-			    d->console_handle), 2);
-		} else if (d->use_fb == 1)
-			lk201_tick(cpu->machine, &d->lk201);
-	}
-
-	for (i=0; i<N_SCC_PORTS; i++) {
-		d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |= SCC_RR0_TX_EMPTY;
-		d->scc_register_r[i * N_SCC_REGS + SCC_RR1] = 0;
-		    /*  No receive errors  */
-
-		d->scc_register_r[i * N_SCC_REGS + SCC_RR0] &=
-		    ~SCC_RR0_RX_AVAIL;
-		if (rx_avail(d, i))
-			d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |=
-			    SCC_RR0_RX_AVAIL;
-
-		/*
-		 *  Interrupts:
-		 *  (NOTE: Interrupt enables are always at channel A)
-		 */
-		if (d->scc_register_w[N_SCC_REGS + SCC_WR9] &
-		    SCC_WR9_MASTER_IE) {
-			/*  TX interrupts?  */
-			if (d->scc_register_w[i * N_SCC_REGS + SCC_WR1] &
-			    SCC_WR1_TX_IE) {
-				if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
-				    & SCC_RR3_TX_IP_A ||
-				    d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
-				    & SCC_RR3_TX_IP_B) {
-					INTERRUPT_ASSERT(d->irq);
-				}
-			}
-
-			/*  RX interrupts?  */
-			if (d->scc_register_w[N_SCC_REGS + SCC_WR1] &
-			    (SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_RXI_ALL_CHAR)) {
-				if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0]
-				    & SCC_RR0_RX_AVAIL) {
-					if (i == SCC_CHANNEL_A)
-						d->scc_register_r[N_SCC_REGS +
-						    SCC_RR3] |= SCC_RR3_RX_IP_A;
-					else
-						d->scc_register_r[N_SCC_REGS +
-						    SCC_RR3] |= SCC_RR3_RX_IP_B;
-				}
-
-				if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
-				    & SCC_RR3_RX_IP_A ||
-				    d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
-				    & SCC_RR3_RX_IP_B) {
-					INTERRUPT_ASSERT(d->irq);
-				}
-			}
-
-			if (d->scc_register_w[N_SCC_REGS + SCC_WR1] &
-			    SCC_WR1_DMA_MODE) {
-				if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0]
-				    & SCC_RR0_RX_AVAIL) {
-					if (i == SCC_CHANNEL_A)
-						d->scc_register_r[N_SCC_REGS +
-						    SCC_RR3] |=
-						    SCC_RR3_EXT_IP_A;
-					else
-						d->scc_register_r[N_SCC_REGS +
-						    SCC_RR3] |=
-						    SCC_RR3_EXT_IP_B;
-				}
-
-				if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
-				    & SCC_RR3_EXT_IP_A ||
-				    d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
-				    & SCC_RR3_EXT_IP_B) {
-					INTERRUPT_ASSERT(d->irq);
-				}
-			}
-		}
-	}
-}
-
-
-/*
- *  dev_scc_dma_func():
- */
-int dev_scc_dma_func(struct cpu *cpu, void *extra, uint64_t addr,
-	size_t dma_len, int tx)
-{
-	/*  printf("dev_scc_dma_func(): addr = %08x, len = %i\n",
-	    (int)addr, (int)dma_len);  */
-	unsigned char word[4];
-	struct scc_data *d = (struct scc_data *) extra;
-	int n;
-
-	int port = SCC_CHANNEL_A;	/*  TODO  */
-
-	if (tx) {
-		do {
-			cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
-			    sizeof(word), MEM_READ, NO_EXCEPTIONS | PHYSICAL);
-
-			lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, word[1]);
-			/*  Loopback:  */
-			if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14]
-			    & SCC_WR14_LOCAL_LOOPB)
-				dev_scc_add_to_rx_queue(d, word[1],
-				    d->scc_nr * 2 + port);
-
-			addr += sizeof(word);
-		} while ((addr & 0xffc) != 0);
-
-		dev_scc_tick(cpu, extra);
-		return 1;
-	} else {
-		printf("dev_scc_dma_func(): addr = %08x, len = %i\n",
-		    (int)addr, (int)dma_len);
-
-
-/*  TODO: all this is just nonsense  */
-
-		n = 0;
-		while (rx_avail(d, port)) {
-			word[0] = word[1] = word[2] = word[3] = 0;
-			word[0] = word[1] = word[2] = word[3] =
-			    rx_nextchar(d, port);
-			n++;
-			cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
-			    sizeof(word), MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
-
-			addr += sizeof(word);
-			/*  Half-page?  */
-			if ((addr & 0x7fc) == 0)
-				break;
-		}
-		dev_scc_tick(cpu, extra);
-		return n*4;
-	}
-}
-
-
-DEVICE_ACCESS(scc)
-{
-	struct scc_data *d = (struct scc_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int port;
-	int ultrix_mode = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  relative_addr /= d->addrmul;  */
-		/*  See SGI comment below instead.  */
-	/*
-	 *  SGI writes command to 0x0f, and data to 0x1f.
-	 *  (TODO: This works for port nr 0, how about port nr 1?)
-	 */
-	if ((relative_addr & 0x0f) == 0xf) {
-		if (relative_addr == 0x0f)
-			relative_addr = 1;
-		else
-			relative_addr = 5;
-	}
-
-	port = relative_addr / 8;
-	relative_addr &= 7;
-
-	dev_scc_tick(cpu, extra);
-
-	/*
-	 *  Ultrix writes words such as 0x1200 to relative address 0,
-	 *  instead of writing the byte 0x12 directly to address 1.
-	 */
-	if ((relative_addr == 0 || relative_addr == 4) && (idata & 0xff) == 0) {
-		ultrix_mode = 1;
-		relative_addr ++;
-		idata >>= 8;
-	}
-
-	switch (relative_addr) {
-	case 1:		/*  command  */
-		if (writeflag==MEM_READ) {
-			odata = d->scc_register_r[port * N_SCC_REGS +
-			    d->register_selected[port]];
-
-			if (d->register_selected[port] == SCC_RR3) {
-				if (port == SCC_CHANNEL_B)
-					fatal("WARNING! scc channel B has "
-					    "no RR3\n");
-
-				d->scc_register_r[port * N_SCC_REGS +
-				    SCC_RR3] = 0;
-
-				INTERRUPT_DEASSERT(d->irq);
-			}
-
-#ifdef SCC_DEBUG
-			fatal("[ scc: port %i, register %i, read value "
-			    "0x%02x ]\n", port, d->register_selected[port],
-			    (int)odata);
-#endif
-			d->register_select_in_progress[port] = 0;
-			d->register_selected[port] = 0;
-			/*  debug("[ scc: (port %i) read from 0x%08lx ]\n",
-			    port, (long)relative_addr);  */
-		} else {
-			/*  If no register is selected, then select one.
-			    Otherwise, write to the selected register.  */
-			if (d->register_select_in_progress[port] == 0) {
-				d->register_select_in_progress[port] = 1;
-				d->register_selected[port] = idata;
-				d->register_selected[port] &= (N_SCC_REGS-1);
-			} else {
-				d->scc_register_w[port * N_SCC_REGS +
-				    d->register_selected[port]] = idata;
-#ifdef SCC_DEBUG
-				fatal("[ scc: port %i, register %i, write "
-				    "value 0x%02x ]\n", port,
-				    d->register_selected[port], idata);
-#endif
-
-				d->scc_register_r[port * N_SCC_REGS +
-				    SCC_RR12] = d->scc_register_w[port *
-				    N_SCC_REGS + SCC_WR12];
-				d->scc_register_r[port * N_SCC_REGS +
-				    SCC_RR13] = d->scc_register_w[port *
-				    N_SCC_REGS + SCC_WR13];
-
-				d->register_select_in_progress[port] = 0;
-				d->register_selected[port] = 0;
-			}
-		}
-		break;
-	case 5:		/*  data  */
-		if (writeflag==MEM_READ) {
-			if (rx_avail(d, port))
-				odata = rx_nextchar(d, port);
-
-			/*  TODO:  perhaps only clear the RX part of RR3?  */
-			d->scc_register_r[N_SCC_REGS + SCC_RR3] = 0;
-
-			INTERRUPT_DEASSERT(d->irq);
-
-//			debug("[ scc: (port %i) read from 0x%08lx: 0x%02x ]\n",
-//			    port, (long)relative_addr, (int)odata);
-		} else {
-			/*  debug("[ scc: (port %i) write to  0x%08lx: "
-			    "0x%08x ]\n", port, (long)relative_addr,
-			    (int)idata);  */
-
-			/*  Send the character:  */
-			lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, idata);
-
-			/*  Loopback:  */
-			if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14]
-			    & SCC_WR14_LOCAL_LOOPB)
-				dev_scc_add_to_rx_queue(d, idata, d->scc_nr
-				    * 2 + port);
-
-			/*  TX interrupt:  */
-			if (d->scc_register_w[port * N_SCC_REGS + SCC_WR9] &
-			    SCC_WR9_MASTER_IE &&
-			    d->scc_register_w[port * N_SCC_REGS + SCC_WR1] &
-			    SCC_WR1_TX_IE) {
-				if (port == SCC_CHANNEL_A)
-					d->scc_register_r[N_SCC_REGS + SCC_RR3]
-					    |= SCC_RR3_TX_IP_A;
-				else
-					d->scc_register_r[N_SCC_REGS + SCC_RR3]
-					    |= SCC_RR3_TX_IP_B;
-			}
-
-			dev_scc_tick(cpu, extra);
-		}
-		break;
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ scc: (port %i) read from 0x%08lx ]\n",
-			    port, (long)relative_addr);
-		} else {
-			debug("[ scc: (port %i) write to  0x%08lx: 0x%08x ]\n",
-			    port, (long)relative_addr, (int)idata);
-		}
-	}
-
-	if (ultrix_mode && writeflag == MEM_READ) {
-		odata <<= 8;
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_scc_init():
- *
- *	use_fb = non-zero when using graphical console + keyboard
- *	scc_nr = 0 or 1
- *	addmul = 1 in most cases, 8 on SGI?
- */
-void *dev_scc_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, char* irq_path, int use_fb, int scc_nr, int addrmul)
-{
-	struct scc_data *d;
-
-	CHECK_ALLOCATION(d = (struct scc_data *) malloc(sizeof(struct scc_data)));
-	memset(d, 0, sizeof(struct scc_data));
-
-	INTERRUPT_CONNECT(irq_path, d->irq);
-	d->scc_nr  = scc_nr;
-	d->use_fb  = use_fb;
-	d->addrmul = addrmul;
-	d->console_handle = console_start_slave(machine, "SCC", 1);
-
-	d->scc_register_r[SCC_RR0] |= SCC_RR0_TX_UNDERRUN;
-
-	lk201_init(&d->lk201, use_fb, dev_scc_add_to_rx_queue,
-	    d->console_handle, d);
-
-	memory_device_register(mem, "scc", baseaddr, DEV_SCC_LENGTH,
-	    dev_scc_access, d, DM_DEFAULT, NULL);
-	machine_add_tickfunction(machine, dev_scc_tick, d, SCC_TICK_SHIFT);
-
-	return (void *) d;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_sfb.c gxemul-0.7.0+dfsg/src/devices/dev_sfb.c
--- gxemul-0.6.2/src/devices/dev_sfb.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sfb.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,110 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: SFB TURBOchannel framebuffer (graphics card)
+ *
+ *  See include/sfbreg.h (and NetBSD's arch/pmax/dev/sfb.c) for more info.
+ *
+ *
+ *  TODO:  This is not really implemented yet. It "happens" to work with
+ *         NetBSD and OpenBSD, but not with Ultrix yet.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "devices.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/sfbreg.h"
+
+
+#define	SFB_XSIZE	1280
+#define	SFB_YSIZE	1024
+
+
+/*  #define debug fatal  */
+
+
+#define	SFB_REG_SIZE	0x80
+#define	N_SFB_REGS	(SFB_REG_SIZE / 4)
+
+
+struct sfb_data {
+	struct vfb_data	*vfb_data;
+
+	uint32_t	reg[N_SFB_REGS];
+};
+
+
+DEVICE_ACCESS(sfb)
+{
+	uint64_t idata = 0, odata = 0;
+	struct sfb_data *d = (struct sfb_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (writeflag==MEM_READ) {
+		odata = d->reg[(relative_addr >> 2) & (N_SFB_REGS - 1)];
+		debug("[ sfb: read from addr 0x%x: 0x%llx ]\n",
+		    (int)relative_addr, (long long)odata);
+	} else {
+		d->reg[(relative_addr >> 2) & (N_SFB_REGS - 1)] = idata;
+		debug("[ sfb: write to addr 0x%x: 0x%llx ]\n",
+		    (int)relative_addr, (long long)idata);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_sfb_init():
+ */
+void dev_sfb_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, struct vfb_data *fb)
+{
+	struct sfb_data *d;
+
+	CHECK_ALLOCATION(d = (struct sfb_data *) malloc(sizeof(struct sfb_data)));
+	memset(d, 0, sizeof(struct sfb_data));
+
+	d->vfb_data = fb;
+
+	d->reg[(SFB_VHORIZONTAL - SFB_ASIC_OFFSET) / 4] = SFB_XSIZE >> 2;
+	d->reg[(SFB_VVERTICAL - SFB_ASIC_OFFSET) / 4]   = SFB_YSIZE;
+
+	memory_device_register(mem, "sfb", baseaddr, SFB_REG_SIZE,
+	    dev_sfb_access, d, DM_DEFAULT, NULL);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_sfb.cc gxemul-0.7.0+dfsg/src/devices/dev_sfb.cc
--- gxemul-0.6.2/src/devices/dev_sfb.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sfb.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,110 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: SFB TURBOchannel framebuffer (graphics card)
- *
- *  See include/sfbreg.h (and NetBSD's arch/pmax/dev/sfb.c) for more info.
- *
- *
- *  TODO:  This is not really implemented yet. It "happens" to work with
- *         NetBSD and OpenBSD, but not with Ultrix yet.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "devices.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/sfbreg.h"
-
-
-#define	SFB_XSIZE	1280
-#define	SFB_YSIZE	1024
-
-
-/*  #define debug fatal  */
-
-
-#define	SFB_REG_SIZE	0x80
-#define	N_SFB_REGS	(SFB_REG_SIZE / 4)
-
-
-struct sfb_data {
-	struct vfb_data	*vfb_data;
-
-	uint32_t	reg[N_SFB_REGS];
-};
-
-
-DEVICE_ACCESS(sfb)
-{
-	uint64_t idata = 0, odata = 0;
-	struct sfb_data *d = (struct sfb_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (writeflag==MEM_READ) {
-		odata = d->reg[(relative_addr >> 2) & (N_SFB_REGS - 1)];
-		debug("[ sfb: read from addr 0x%x: 0x%llx ]\n",
-		    (int)relative_addr, (long long)odata);
-	} else {
-		d->reg[(relative_addr >> 2) & (N_SFB_REGS - 1)] = idata;
-		debug("[ sfb: write to addr 0x%x: 0x%llx ]\n",
-		    (int)relative_addr, (long long)idata);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_sfb_init():
- */
-void dev_sfb_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, struct vfb_data *fb)
-{
-	struct sfb_data *d;
-
-	CHECK_ALLOCATION(d = (struct sfb_data *) malloc(sizeof(struct sfb_data)));
-	memset(d, 0, sizeof(struct sfb_data));
-
-	d->vfb_data = fb;
-
-	d->reg[(SFB_VHORIZONTAL - SFB_ASIC_OFFSET) / 4] = SFB_XSIZE >> 2;
-	d->reg[(SFB_VVERTICAL - SFB_ASIC_OFFSET) / 4]   = SFB_YSIZE;
-
-	memory_device_register(mem, "sfb", baseaddr, SFB_REG_SIZE,
-	    dev_sfb_access, d, DM_DEFAULT, NULL);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_gbe.c gxemul-0.7.0+dfsg/src/devices/dev_sgi_gbe.c
--- gxemul-0.6.2/src/devices/dev_sgi_gbe.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_gbe.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,791 @@
+/*
+ *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: SGI "Graphics Back End", graphics controller + framebuffer
+ *
+ *  Guesswork, based on how Linux, NetBSD, and OpenBSD use the graphics on
+ *  the SGI O2. Using NetBSD terminology (from crmfbreg.h):
+ *
+ *  dev_sgi_re.cc:
+ *	0x15001000	rendering engine (TLBs)
+ *	0x15002000	drawing engine
+ *	0x15003000	memory transfer engine
+ *	0x15004000	status registers for drawing engine
+ *
+ *  dev_sgi_gbe.cc:
+ *	0x16000000	crm (or GBE) framebuffer control / video output
+ *
+ *  According to https://www.linux-mips.org/wiki/GBE, the GBE is also used in
+ *  the SGI Visual Workstation.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/crmfbreg.h"
+
+
+/*  Let's hope nothing is there already...  */
+#define	FAKE_GBE_FB_ADDRESS	0x380000000ULL
+
+
+// #define	GBE_DEBUG
+// #define debug fatal
+
+#define	GBE_DEFAULT_XRES		1280
+#define	GBE_DEFAULT_YRES		1024
+#define	GBE_DEFAULT_BITDEPTH		8
+
+
+struct sgi_gbe_data {
+	// CRM / GBE registers:
+	uint32_t	ctrlstat;		/* 0x00000  */
+	uint32_t	dotclock;		/* 0x00004  */
+	uint32_t	i2c;			/* 0x00008  */
+	uint32_t	i2cfp;			/* 0x00010  */
+
+	uint32_t	freeze;	/* and xy */	/* 0x10000  */
+	uint32_t	y_intr01;		/* 0x10020  */
+	uint32_t	y_intr23;		/* 0x10024  */
+
+	uint32_t	ovr_tilesize;		/* 0x20000  */
+	uint32_t	ovr_control;		/* 0x2000c  */
+
+	uint32_t	tilesize;		/* 0x30000  */
+	uint32_t	frm_control;		/* 0x3000c  */
+
+	uint32_t	palette[32 * 256];	/* 0x50000  */
+
+	uint32_t	cursor_pos;		/* 0x70000  */
+	uint32_t	cursor_control;		/* 0x70004  */
+	uint32_t	cursor_cmap0;		/* 0x70008  */
+	uint32_t	cursor_cmap1;		/* 0x7000c  */
+	uint32_t	cursor_cmap2;		/* 0x70010  */
+	uint32_t	cursor_bitmap[64];	/* 0x78000  */
+
+	// Emulator's representation:
+	int		xres, yres;
+	int 		width_in_tiles;
+	int		partial_pixels;
+	int 		ovr_width_in_tiles;
+	int		ovr_partial_pixels;
+	int		bitdepth;
+	int		color_mode;
+	int		cmap_select;
+	uint32_t	selected_palette[256];
+	struct vfb_data *fb_data;
+};
+
+
+void get_rgb(struct sgi_gbe_data *d, uint32_t color, uint8_t* r, uint8_t* g, uint8_t* b)
+{
+	// TODO: Don't switch on color_mode. For overlays, this is always 
+	// 8-bit index mode!
+	switch (d->color_mode) {
+	case CRMFB_MODE_TYP_I8:
+		color &= 0xff;
+		*r = d->selected_palette[color] >> 24;
+		*g = d->selected_palette[color] >> 16;
+		*b = d->selected_palette[color] >>  8;
+		break;
+	case CRMFB_MODE_TYP_RG3B2:	// Used by NetBSD console mode
+		*r = 255 * ((color >> 5) & 7) / 7;
+		*g = 255 * ((color >> 2) & 7) / 7;
+		*b = (color & 3) * 85;
+		break;
+	case CRMFB_MODE_TYP_RGB8:	// Used by NetBSD's X11 server
+		*r = color >> 24;
+		*g = color >> 16;
+		*b = color >>  8;
+		break;
+	default:fatal("sgi gbe get_rgb(): unimplemented mode %i\n", d->color_mode);
+		exit(1);
+	}
+}
+
+
+void select_palette(struct sgi_gbe_data *d, int palette_nr)
+{
+	memmove(&d->selected_palette[0],
+		&d->palette[256 * palette_nr],
+		256 * sizeof(uint32_t));
+}
+
+
+/*
+ *  dev_sgi_gbe_tick():
+ *
+ *  Every now and then, copy data from the framebuffer in normal ram
+ *  to the actual framebuffer (which will then redraw the window).
+ *
+ *  NOTE: This is very slow, even slower than the normal emulated framebuffer,
+ *  which is already slow as it is.
+ *
+ *  frm_control contains a pointer to an array of uint16_t. These numbers
+ *  (when shifted 16 bits to the left) are pointers to the tiles. Tiles are
+ *  512x128 in 8-bit mode, 256x128 in 16-bit mode, and 128x128 in 32-bit mode.
+ *
+ *  An exception is how Linux/O2 uses the framebuffer, in a "tweaked" mode
+ *  which resembles linear mode. This code attempts to support both.
+ */
+DEVICE_TICK(sgi_gbe)
+{
+	struct sgi_gbe_data *d = (struct sgi_gbe_data *) extra;
+	uint64_t tiletable;
+	unsigned char buf[16384];	/*  must be power of 2, at most 65536 */
+	int bytes_per_pixel = d->bitdepth / 8;
+	int partial_pixels, width_in_tiles;
+
+	if (!cpu->machine->x11_md.in_use)
+		return;
+
+	// If not frozen...
+	if (!(d->freeze & 0x80000000)) {
+		// ... check if the guest OS wants interrupts based on Y:
+		if ((d->y_intr01 & CRMFB_INTR_0_MASK) != 0xfff000 ||
+		    (d->y_intr01 & CRMFB_INTR_1_MASK) != 0xfff ||
+		    (d->y_intr23 & CRMFB_INTR_2_MASK) != 0xfff000 ||
+		    (d->y_intr23 & CRMFB_INTR_3_MASK) != 0xfff) {
+			fatal("[ sgi_gbe: WARNING: Y interrupts not yet implemented. ]\n");
+		}
+	}
+
+	// printf("d->frm_control = %08x  d->ovr_control = %08x\n", d->frm_control,d->ovr_control);
+
+	// NetBSD's crmfbreg.h documents the tileptr as having a "9 bit shift",
+	// but IRIX seems to put a value ending in 0x......80 there, and the
+	// last part of that address seems to matter.
+	// TODO: Double-check this with the real hardware.
+	
+	if (d->ovr_control & CRMFB_DMA_ENABLE) {
+		tiletable = (d->ovr_control & 0xffffff80);
+		bytes_per_pixel = 1;
+		partial_pixels = d->ovr_partial_pixels;
+		width_in_tiles = d->ovr_width_in_tiles;
+		select_palette(d, 17);	// TODO: is it always palette nr 17 for overlays?
+	} else if (d->frm_control & CRMFB_DMA_ENABLE) {
+		tiletable = (d->frm_control & 0xffffff80);
+		partial_pixels = d->partial_pixels;
+		width_in_tiles = d->width_in_tiles;
+		select_palette(d, d->cmap_select);
+	} else {
+		return;
+	}
+
+#ifdef GBE_DEBUG
+	fatal("[ sgi_gbe: dev_sgi_gbe_tick(): tiletable = 0x%llx, bytes_per_pixel = %i ]\n", (long long)tiletable,
+		bytes_per_pixel);
+#endif
+
+	if (tiletable == 0)
+		return;
+
+	// Nr of tiles horizontally:
+	int w = width_in_tiles + (partial_pixels > 0 ? 1 : 0);
+
+	// Actually, the number of tiles vertically is usually very few,
+	// but this algorithm will render "up to" 256 and abort as soon
+	// as the screen is filled instead. This makes it work for both
+	// Linux' "tweaked linear" mode and all the other guest OSes.
+	const int max_nr_of_tiles = 256;
+	
+	uint32_t tile[max_nr_of_tiles];
+	uint8_t alltileptrs[max_nr_of_tiles * sizeof(uint16_t)];
+	
+	cpu->memory_rw(cpu, cpu->mem, tiletable,
+	    alltileptrs, sizeof(alltileptrs), MEM_READ,
+	    NO_EXCEPTIONS | PHYSICAL);
+
+	for (int i = 0; i < 256; ++i) {
+		tile[i] = (256 * alltileptrs[i*2] + alltileptrs[i*2+1]) << 16;
+#ifdef GBE_DEBUG
+		if (tile[i] != 0)
+			printf("tile[%i] = 0x%08x\n", i, tile[i]);
+#endif
+	}
+
+	int screensize = d->xres * d->yres * 3;
+	int x = 0, y = 0;
+
+	for (int tiley = 0; tiley < max_nr_of_tiles; ++tiley) {
+		for (int line = 0; line < 128; ++line) {
+			for (int tilex = 0; tilex < w; ++tilex) {
+				int tilenr = tilex + tiley * w;
+				
+				if (tilenr >= max_nr_of_tiles)
+					continue;
+				
+				uint32_t base = tile[tilenr];
+				
+				if (base == 0)
+					continue;
+				
+				// Read one line of up to 512 bytes from the tile.
+				int len = tilex < width_in_tiles ? 512 : (partial_pixels * bytes_per_pixel);
+
+				cpu->memory_rw(cpu, cpu->mem, base + 512 * line,
+				    buf, len, MEM_READ, NO_EXCEPTIONS | PHYSICAL);
+
+				int fb_offset = (x + y * d->xres) * 3;
+				int fb_len = (len / bytes_per_pixel) * 3;
+
+				if (fb_offset + fb_len > screensize) {
+					fb_len = screensize - fb_offset;
+				}
+				
+				if (fb_len <= 0) {
+					tiley = max_nr_of_tiles;  // to break
+					tilex = w;
+					line = 128;
+				}
+
+				uint8_t fb_buf[512 * 3];
+				int fb_i = 0;
+				for (int i = 0; i < 512; i+=bytes_per_pixel) {
+					uint32_t color;
+					if (bytes_per_pixel == 1)
+						color = buf[i];
+					else if (bytes_per_pixel == 2)
+						color = (buf[i]<<8) + buf[i+1];
+					else // if (bytes_per_pixel == 4)
+						color = (buf[i]<<24) + (buf[i+1]<<16)
+							+ (buf[i+2]<<8)+buf[i+3];
+					get_rgb(d, color,
+					    &fb_buf[fb_i],
+					    &fb_buf[fb_i+1],
+					    &fb_buf[fb_i+2]);
+					fb_i += 3;
+				}
+
+				dev_fb_access(cpu, cpu->mem, fb_offset,
+				    fb_buf, fb_len, MEM_WRITE, d->fb_data);
+
+				x += len / bytes_per_pixel;
+				if (x >= d->xres) {
+					x -= d->xres;
+					++y;
+					if (y >= d->yres) {
+						tiley = max_nr_of_tiles; // to break
+						tilex = w;
+						line = 128;
+					}
+				}
+			}
+		}
+	}
+
+	/*
+	 *  NOTE/TODO: On my O2, if I do:
+	 *
+	 *	put 0xb6070004 0	to disable
+	 *	put 0xb6070004 2	for crosshair
+	 *
+	 *  it is not shown (since it is disabled). BUT! If I then do
+	 *
+	 *	put 0xb6070004 3	to enable with crosshair
+	 *	put 0xb6070004 2	to DISABLE but keep crosshair,
+	 *
+	 *  then the crosshair is still there. (Or so it seems, it feels
+	 *  slightly random.)
+	 *
+	 *  The emulator currently does not emulate that behavior, but requires
+	 *  the "ON" bit to be on in order to show a cursor.
+	 */
+
+	if (d->cursor_control & CRMFB_CURSOR_ON) {
+		int16_t cx = d->cursor_pos & 0xffff;
+		int16_t cy = d->cursor_pos >> 16;
+
+		if (d->cursor_control & CRMFB_CURSOR_CROSSHAIR) {
+			uint8_t pixel[3];
+			pixel[0] = d->cursor_cmap0 >> 24;
+			pixel[1] = d->cursor_cmap0 >> 16;
+			pixel[2] = d->cursor_cmap0 >> 8;
+
+			if (cx >= 0 && cx < d->xres) {
+				for (y = 0; y < d->yres; ++y)
+					dev_fb_access(cpu, cpu->mem, (cx + y * d->xres) * 3,
+					    pixel, 3, MEM_WRITE, d->fb_data);
+			}
+
+			// TODO: Rewrite as a single framebuffer block write?
+			if (cy >= 0 && cy < d->yres) {
+				for (x = 0; x < d->xres; ++x)
+					dev_fb_access(cpu, cpu->mem, (x + cy * d->xres) * 3,
+					    pixel, 3, MEM_WRITE, d->fb_data);
+			}
+		} else {
+			uint8_t pixel[3];
+			int sx, sy;
+
+			for (int dy = 0; dy < 32; ++dy) {
+				for (int dx = 0; dx < 32; ++dx) {
+					sx = cx + dx;
+					sy = cy + dy;
+					
+					if (sx < 0 || sx >= d->xres ||
+					    sy < 0 || sy >= d->yres)
+						continue;
+					
+					int wordindex = dy*2 + (dx>>4);
+					uint32_t word = d->cursor_bitmap[wordindex];
+					
+					int color = (word >> ((15 - (dx&15))*2)) & 3;
+					
+					if (!color)
+						continue;
+
+					if (color == 1) {
+						pixel[0] = d->cursor_cmap0 >> 24;
+						pixel[1] = d->cursor_cmap0 >> 16;
+						pixel[2] = d->cursor_cmap0 >> 8;
+					} else if (color == 2) {
+						pixel[0] = d->cursor_cmap1 >> 24;
+						pixel[1] = d->cursor_cmap1 >> 16;
+						pixel[2] = d->cursor_cmap1 >> 8;
+					} else {
+						pixel[0] = d->cursor_cmap2 >> 24;
+						pixel[1] = d->cursor_cmap2 >> 16;
+						pixel[2] = d->cursor_cmap2 >> 8;
+					}
+
+					dev_fb_access(cpu, cpu->mem, (sx + sy * d->xres) * 3,
+					    pixel, 3, MEM_WRITE, d->fb_data);
+				}
+			}
+		}
+	}
+}
+
+
+DEVICE_ACCESS(sgi_gbe)
+{
+	struct sgi_gbe_data *d = (struct sgi_gbe_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE) {
+		idata = memory_readmax64(cpu, data, len);
+
+#ifdef GBE_DEBUG
+		fatal("[ sgi_gbe: DEBUG: write to address 0x%llx, data"
+		    "=0x%llx ]\n", (long long)relative_addr, (long long)idata);
+#endif
+	}
+
+	switch (relative_addr) {
+
+	case CRMFB_CTRLSTAT:	// 0x0
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_gbe: write to ctrlstat: 0x%08x ]\n", (int)idata);
+			d->ctrlstat = (idata & ~CRMFB_CTRLSTAT_CHIPID_MASK)
+				| (d->ctrlstat & CRMFB_CTRLSTAT_CHIPID_MASK);
+		} else
+			odata = d->ctrlstat;
+		break;
+
+	case CRMFB_DOTCLOCK:	// 0x4
+		if (writeflag == MEM_WRITE)
+			d->dotclock = idata;
+		else
+			odata = d->dotclock;
+		break;
+
+	case CRMFB_I2C_VGA:	// 0x8
+		/*
+		 *  "CRT I2C control".
+		 *
+		 *  I'm not sure what this does. It isn't really commented
+		 *  in the Linux sources.  The IP32 PROM writes the values
+		 *  0x03, 0x01, and then 0x00 to this address, and then
+		 *  reads back a value.
+		 */
+		if (writeflag == MEM_WRITE) {
+			//if (!(d->i2c & CRMFB_I2C_SCL) &&
+			//    (idata & CRMFB_I2C_SCL)) {
+			//	fatal("vga i2c data: %i\n", idata & CRMFB_I2C_SDA);
+			//}
+
+			d->i2c = idata;
+		} else {
+			odata = d->i2c;
+			odata |= 1;	/*  ?  The IP32 prom wants this?  */
+		}
+		break;
+
+	case CRMFB_I2C_FP:	// 0x10, i2cfp, flat panel control
+		if (writeflag == MEM_WRITE) {
+			//if (d->i2c & CRMFB_I2C_SCL &&
+			//    !(idata & CRMFB_I2C_SCL)) {
+			//	fatal("fp i2c data: %i\n", idata & CRMFB_I2C_SDA);
+			//}
+
+			d->i2cfp = idata;
+		} else {
+			odata = d->i2cfp;
+			odata |= 1;	/*  ?  The IP32 prom wants this?  */
+		}
+		break;
+
+	case CRMFB_DEVICE_ID:	// 0x14
+		odata = CRMFB_DEVICE_ID_DEF;
+		break;
+
+	case CRMFB_VT_XY:	// 0x10000
+		if (writeflag == MEM_WRITE)
+			d->freeze = idata & 0x80000000;
+		else {
+			/*
+			 *  vt_xy, according to Linux:
+			 *
+			 * bit 31 = freeze, 23..12 = cury, 11.0 = curx
+			 */
+			/*  odata = ((random() % (d->yres + 10)) << 12)
+			    + (random() % (d->xres + 10)) +
+			    d->freeze;  */
+
+			/*
+			 *  Hack for IRIX/IP32. During startup, it waits for
+			 *  the value to be over 0x400 (in "gbeRun").
+			 *
+			 *  Hack for the IP32 PROM: During startup, it waits
+			 *  for the value to be above 0x500 (I think).
+			 */
+			odata = d->freeze | (random() & 1 ? 0x3ff : 0x501);
+		}
+		break;
+
+	case CRMFB_VT_XYMAX:	// 0x10004, vt_xymax, according to Linux & NetBSD
+		odata = ((d->yres-1) << 12) + d->xres-1;
+		/*  ... 12 bits maxy, 12 bits maxx.  */
+		break;
+
+	case CRMFB_VT_VSYNC:	// 0x10008
+	case CRMFB_VT_HSYNC:	// 0x1000c
+	case CRMFB_VT_VBLANK:	// 0x10010
+	case CRMFB_VT_HBLANK:	// 0x10014
+		// TODO
+		break;
+
+	case CRMFB_VT_FLAGS:	// 0x10018
+		// OpenBSD/sgi writes to this register.
+		break;
+
+	case CRMFB_VT_FRAMELOCK:	// 0x1001c
+		// TODO.
+		break;
+
+	case CRMFB_VT_INTR01:	// 0x10020
+		if (writeflag == MEM_WRITE)
+			d->y_intr01 = idata;
+		break;
+
+	case CRMFB_VT_INTR23:	// 0x10024
+		if (writeflag == MEM_WRITE)
+			d->y_intr23 = idata;
+		break;
+
+	case 0x10028:	// 0x10028
+	case 0x1002c:	// 0x1002c
+	case 0x10030:	// 0x10030
+		// TODO: Unknown, written to by the PROM?
+		break;
+
+	case CRMFB_VT_HPIX_EN:	// 0x10034, vt_hpixen, according to Linux
+		odata = (0 << 12) + d->xres-1;
+		/*  ... 12 bits on, 12 bits off.  */
+		break;
+
+	case CRMFB_VT_VPIX_EN:	// 0x10038, vt_vpixen, according to Linux
+		odata = (0 << 12) + d->yres-1;
+		/*  ... 12 bits on, 12 bits off.  */
+		break;
+
+	case CRMFB_VT_HCMAP:	// 0x1003c
+		if (writeflag == MEM_WRITE) {
+			d->xres = (idata & CRMFB_HCMAP_ON_MASK) >> CRMFB_VT_HCMAP_ON_SHIFT;
+			dev_fb_resize(d->fb_data, d->xres, d->yres);
+		}
+		
+		odata = (d->xres << CRMFB_VT_HCMAP_ON_SHIFT) + d->xres + 100;
+		break;
+
+	case CRMFB_VT_VCMAP:	// 0x10040
+		if (writeflag == MEM_WRITE) {
+			d->yres = (idata & CRMFB_VCMAP_ON_MASK) >> CRMFB_VT_VCMAP_ON_SHIFT;
+			dev_fb_resize(d->fb_data, d->xres, d->yres);
+		}
+
+		odata = (d->yres << CRMFB_VT_VCMAP_ON_SHIFT) + d->yres + 100;
+		break;
+
+	case CRMFB_VT_DID_STARTXY:	// 0x10044
+	case CRMFB_VT_CRS_STARTXY:	// 0x10048
+	case CRMFB_VT_VC_STARTXY:	// 0x1004c
+		// TODO
+		break;
+		
+	case CRMFB_OVR_WIDTH_TILE:	// 0x20000
+		if (writeflag == MEM_WRITE) {
+			d->ovr_tilesize = idata;
+
+			d->ovr_width_in_tiles = (idata >> CRMFB_FRM_TILESIZE_WIDTH_SHIFT) & 0xff;
+			d->ovr_partial_pixels = ((idata >> CRMFB_FRM_TILESIZE_RHS_SHIFT) & 0x1f) * 32;
+
+			debug("[ sgi_gbe: OVR setting width in tiles = %i, partial pixels = %i ]\n",
+			    d->ovr_width_in_tiles, d->ovr_partial_pixels);
+		} else
+			odata = d->ovr_tilesize;
+		break;
+
+	case CRMFB_OVR_TILE_PTR:	// 0x20004
+		odata = d->ovr_control ^ (random() & 1);
+		break;
+
+	case CRMFB_OVR_CONTROL:		// 0x20008
+		if (writeflag == MEM_WRITE)
+			d->ovr_control = idata;
+		else
+			odata = d->ovr_control;
+		break;
+
+	case CRMFB_FRM_TILESIZE:	// 0x30000:
+		if (writeflag == MEM_WRITE) {
+			d->tilesize = idata;
+
+			d->bitdepth = 8 << ((d->tilesize >> CRMFB_FRM_TILESIZE_DEPTH_SHIFT) & 3);
+			d->width_in_tiles = (idata >> CRMFB_FRM_TILESIZE_WIDTH_SHIFT) & 0xff;
+			d->partial_pixels = ((idata >> CRMFB_FRM_TILESIZE_RHS_SHIFT) & 0x1f) * 32 * 8 / d->bitdepth;
+
+			debug("[ sgi_gbe: setting color depth to %i bits, width in tiles = %i, partial pixels = %i ]\n",
+			    d->bitdepth, d->width_in_tiles, d->partial_pixels);
+		} else
+			odata = d->tilesize;
+		break;
+
+	case CRMFB_FRM_PIXSIZE:	// 0x30004
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_gbe: setting PIXSIZE to 0x%08x ]\n", (int)idata);
+		}
+		break;
+		
+	case 0x30008:
+		// TODO: Figure out exactly what the low bits do.
+		// Irix seems to want 0x20 to "sometimes" be on or off here.
+		odata = d->frm_control ^ (random() & 0x20);
+		break;
+
+	case CRMFB_FRM_CONTROL:	// 0x3000c
+		/*
+		 *  Writes to 3000c should be readable back at 30008?
+		 *  At least bit 0 (dma) ctrl 3.
+		 */
+		if (writeflag == MEM_WRITE) {
+			d->frm_control = idata;
+			debug("[ sgi_gbe: frm_control = 0x%08x ]\n", d->frm_control);
+		} else
+			odata = d->frm_control;
+		break;
+
+	case CRMFB_DID_PTR:	// 0x40000
+		odata = random();	/*  IP32 prom test hack. TODO  */
+		/*  IRIX wants 0x20, it seems.  */
+		if (random() & 1)
+			odata = 0x20;
+		break;
+
+	case CRMFB_DID_CONTROL:	// 0x40004
+		// TODO
+		break;
+
+	case CRMFB_CMAP_FIFO:		// 0x58000
+		break;
+
+	case CRMFB_CURSOR_POS:		// 0x70000
+		if (writeflag == MEM_WRITE)
+			d->cursor_pos = idata;
+		else
+			odata = d->cursor_pos;
+		break;
+		
+	case CRMFB_CURSOR_CONTROL:	// 0x70004
+		if (writeflag == MEM_WRITE)
+			d->cursor_control = idata;
+		else
+			odata = d->cursor_control;
+		break;
+		
+	case CRMFB_CURSOR_CMAP0:	// 0x70008
+		if (writeflag == MEM_WRITE)
+			d->cursor_cmap0 = idata;
+		else
+			odata = d->cursor_cmap0;
+		break;
+		
+	case CRMFB_CURSOR_CMAP1:	// 0x7000c
+		if (writeflag == MEM_WRITE)
+			d->cursor_cmap1 = idata;
+		else
+			odata = d->cursor_cmap1;
+		break;
+		
+	case CRMFB_CURSOR_CMAP2:	// 0x70010
+		if (writeflag == MEM_WRITE)
+			d->cursor_cmap2 = idata;
+		else
+			odata = d->cursor_cmap2;
+		break;
+
+	/*
+	 *  Linux/sgimips seems to write color palette data to offset 0x50000
+	 *  to 0x503xx, and gamma correction data to 0x60000 - 0x603ff, as
+	 *  32-bit values at addresses divisible by 4 (formated as 0xrrggbb00).
+	 *
+	 *  "sgio2fb: initializing
+	 *   sgio2fb: I/O at 0xffffffffb6000000
+	 *   sgio2fb: tiles at ffffffffa2ef5000
+	 *   sgio2fb: framebuffer at ffffffffa1000000
+	 *   sgio2fb: 8192kB memory
+	 *   Console: switching to colour frame buffer device 80x30"
+	 *
+	 *  NetBSD's crmfb_set_palette, however, uses values in reverse, like this:
+	 *	val = (r << 8) | (g << 16) | (b << 24);
+	 */
+
+	default:
+		/*  WID at 0x48000 .. 0x48000 + 4*31:  */
+		if (relative_addr >= CRMFB_WID && relative_addr <= CRMFB_WID + 4 * 31) {
+			// TODO: Figure out how this really works. Why are
+			// there 32 such registers?
+			if (writeflag == MEM_WRITE) {
+				d->color_mode = (idata >> CRMFB_MODE_TYP_SHIFT) & 7;
+				d->cmap_select = (idata >> CRMFB_MODE_CMAP_SELECT_SHIFT) & 0x1f;
+			}
+
+			break;
+		}
+
+		/*  RGB Palette at 0x50000 .. 0x57fff:  */
+		if (relative_addr >= CRMFB_CMAP && relative_addr < CRMFB_CMAP + 256 * 32 * sizeof(uint32_t)) {
+			int color_index = (relative_addr - CRMFB_CMAP) >> 2;
+			if (writeflag == MEM_WRITE) {
+				int cmap = color_index >> 8;
+				d->palette[color_index] = idata;
+				if (cmap == d->cmap_select)
+					d->selected_palette[color_index] = idata;
+			} else {
+				odata = d->palette[color_index];
+			}
+			break;
+		}
+
+		/*  Gamma correction at 0x60000 .. 0x603ff:  */
+		if (relative_addr >= CRMFB_GMAP && relative_addr <= CRMFB_GMAP + 0x3ff) {
+			/*  ignore gamma correction for now  */
+			break;
+		}
+
+		/*  Cursor bitmap at 0x78000 ..:  */
+		if (relative_addr >= CRMFB_CURSOR_BITMAP && relative_addr <= CRMFB_CURSOR_BITMAP + 0xff) {
+			if (len != 4) {
+				printf("unimplemented CRMFB_CURSOR_BITMAP len %i\n", (int)len);
+			}
+
+			int index = (relative_addr & 0xff) / 4;
+			if (writeflag == MEM_WRITE)
+				d->cursor_bitmap[index] = idata;
+			else
+				odata = d->cursor_bitmap[index];
+			break;
+		}
+
+		if (writeflag == MEM_WRITE)
+			fatal("[ sgi_gbe: unimplemented write to address "
+			    "0x%llx, data=0x%llx ]\n",
+			    (long long)relative_addr, (long long)idata);
+		else
+			fatal("[ sgi_gbe: unimplemented read from address "
+			    "0x%llx ]\n", (long long)relative_addr);
+	}
+
+	if (writeflag == MEM_READ) {
+#ifdef GBE_DEBUG
+		debug("[ sgi_gbe: DEBUG: read from address 0x%llx: 0x%llx ]\n",
+		    (long long)relative_addr, (long long)odata);
+#endif
+		memory_writemax64(cpu, data, len, odata);
+	}
+
+	return 1;
+}
+
+
+void dev_sgi_gbe_init(struct machine *machine, struct memory *mem, uint64_t baseaddr)
+{
+	struct sgi_gbe_data *d;
+
+	CHECK_ALLOCATION(d = (struct sgi_gbe_data *) malloc(sizeof(struct sgi_gbe_data)));
+	memset(d, 0, sizeof(struct sgi_gbe_data));
+
+	d->xres = GBE_DEFAULT_XRES;
+	d->yres = GBE_DEFAULT_YRES;
+	d->bitdepth = GBE_DEFAULT_BITDEPTH;
+	
+	// My O2 says 0x300ae001 here (while running).
+	d->ctrlstat = CRMFB_CTRLSTAT_INTERNAL_PCLK |
+			CRMFB_CTRLSTAT_GPIO6_INPUT |
+			CRMFB_CTRLSTAT_GPIO5_INPUT |
+			CRMFB_CTRLSTAT_GPIO4_INPUT |
+			CRMFB_CTRLSTAT_GPIO4_SENSE |
+			CRMFB_CTRLSTAT_GPIO3_INPUT |
+			(CRMFB_CTRLSTAT_CHIPID_MASK & 1);
+
+	// Set a value in the interrupt register that will "never happen" by default.
+	d->y_intr01 = (0xfff << 12) | 0xfff;
+	d->y_intr23 = (0xfff << 12) | 0xfff;
+
+	// Grayscale palette, most likely overwritten immediately by the
+	// guest operating system.
+	for (int i = 0; i < 256; ++i)
+		d->palette[i] = i * 0x01010100UL;
+
+	d->fb_data = dev_fb_init(machine, mem, FAKE_GBE_FB_ADDRESS,
+	    VFB_GENERIC, d->xres, d->yres, d->xres, d->yres, 24, "SGI GBE");
+
+	memory_device_register(mem, "sgi_gbe", baseaddr, DEV_SGI_GBE_LENGTH,
+	    dev_sgi_gbe_access, d, DM_DEFAULT, NULL);
+	machine_add_tickfunction(machine, dev_sgi_gbe_tick, d, 19);
+}
+
+
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_gbe.cc gxemul-0.7.0+dfsg/src/devices/dev_sgi_gbe.cc
--- gxemul-0.6.2/src/devices/dev_sgi_gbe.cc	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_gbe.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,773 +0,0 @@
-/*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: SGI "Graphics Back End", graphics controller + framebuffer
- *
- *  Guesswork, based on how Linux, NetBSD, and OpenBSD use the graphics on
- *  the SGI O2. Using NetBSD terminology (from crmfbreg.h):
- *
- *  dev_sgi_re.cc:
- *	0x15001000	rendering engine (TLBs)
- *	0x15002000	drawing engine
- *	0x15003000	memory transfer engine
- *	0x15004000	status registers for drawing engine
- *
- *  dev_sgi_gbe.cc:
- *	0x16000000	crm (or GBE) framebuffer control / video output
- *
- *  According to https://www.linux-mips.org/wiki/GBE, the GBE is also used in
- *  the SGI Visual Workstation.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/crmfbreg.h"
-
-
-/*  Let's hope nothing is there already...  */
-#define	FAKE_GBE_FB_ADDRESS	0x380000000ULL
-
-
-// #define	GBE_DEBUG
-// #define debug fatal
-
-#define	GBE_DEFAULT_XRES		1280
-#define	GBE_DEFAULT_YRES		1024
-#define	GBE_DEFAULT_BITDEPTH		8
-
-
-struct sgi_gbe_data {
-	// CRM / GBE registers:
-	uint32_t	ctrlstat;		/* 0x00000  */
-	uint32_t	dotclock;		/* 0x00004  */
-	uint32_t	i2c;			/* 0x00008  */
-	uint32_t	i2cfp;			/* 0x00010  */
-
-	uint32_t	freeze;	/* and xy */	/* 0x10000  */
-	uint32_t	y_intr01;		/* 0x10020  */
-	uint32_t	y_intr23;		/* 0x10024  */
-
-	uint32_t	ovr_tilesize;		/* 0x20000  */
-	uint32_t	ovr_control;		/* 0x2000c  */
-
-	uint32_t	tilesize;		/* 0x30000  */
-	uint32_t	frm_control;		/* 0x3000c  */
-
-	uint32_t	palette[32 * 256];	/* 0x50000  */
-
-	uint32_t	cursor_pos;		/* 0x70000  */
-	uint32_t	cursor_control;		/* 0x70004  */
-	uint32_t	cursor_cmap0;		/* 0x70008  */
-	uint32_t	cursor_cmap1;		/* 0x7000c  */
-	uint32_t	cursor_cmap2;		/* 0x70010  */
-	uint32_t	cursor_bitmap[64];	/* 0x78000  */
-
-	// Emulator's representation:
-	int		xres, yres;
-	int 		width_in_tiles;
-	int		partial_pixels;
-	int 		ovr_width_in_tiles;
-	int		ovr_partial_pixels;
-	int		bitdepth;
-	int		color_mode;
-	int		cmap_select;
-	uint32_t	selected_palette[256];
-	struct vfb_data *fb_data;
-};
-
-
-void get_rgb(struct sgi_gbe_data *d, uint32_t color, uint8_t* r, uint8_t* g, uint8_t* b)
-{
-	// TODO: Don't switch on color_mode. For overlays, this is always 
-	// 8-bit index mode!
-	switch (d->color_mode) {
-	case CRMFB_MODE_TYP_I8:
-		color &= 0xff;
-		*r = d->selected_palette[color] >> 24;
-		*g = d->selected_palette[color] >> 16;
-		*b = d->selected_palette[color] >>  8;
-		break;
-	case CRMFB_MODE_TYP_RG3B2:	// Used by NetBSD console mode
-		*r = 255 * ((color >> 5) & 7) / 7;
-		*g = 255 * ((color >> 2) & 7) / 7;
-		*b = (color & 3) * 85;
-		break;
-	case CRMFB_MODE_TYP_RGB8:	// Used by NetBSD's X11 server
-		*r = color >> 24;
-		*g = color >> 16;
-		*b = color >>  8;
-		break;
-	default:fatal("sgi gbe get_rgb(): unimplemented mode %i\n", d->color_mode);
-		exit(1);
-	}
-}
-
-
-void select_palette(struct sgi_gbe_data *d, int palette_nr)
-{
-	memmove(&d->selected_palette[0],
-		&d->palette[256 * palette_nr],
-		256 * sizeof(uint32_t));
-}
-
-
-/*
- *  dev_sgi_gbe_tick():
- *
- *  Every now and then, copy data from the framebuffer in normal ram
- *  to the actual framebuffer (which will then redraw the window).
- *
- *  NOTE: This is very slow, even slower than the normal emulated framebuffer,
- *  which is already slow as it is.
- *
- *  frm_control contains a pointer to an array of uint16_t. These numbers
- *  (when shifted 16 bits to the left) are pointers to the tiles. Tiles are
- *  512x128 in 8-bit mode, 256x128 in 16-bit mode, and 128x128 in 32-bit mode.
- *
- *  An exception is how Linux/O2 uses the framebuffer, in a "tweaked" mode
- *  which resembles linear mode. This code attempts to support both.
- */
-DEVICE_TICK(sgi_gbe)
-{
-	struct sgi_gbe_data *d = (struct sgi_gbe_data *) extra;
-	uint64_t tiletable;
-	unsigned char buf[16384];	/*  must be power of 2, at most 65536 */
-	int bytes_per_pixel = d->bitdepth / 8;
-	int partial_pixels, width_in_tiles;
-
-	if (!cpu->machine->x11_md.in_use)
-		return;
-
-	// If not frozen...
-	if (!(d->freeze & 0x80000000)) {
-		// ... check if the guest OS wants interrupts based on Y:
-		if ((d->y_intr01 & CRMFB_INTR_0_MASK) != 0xfff000 ||
-		    (d->y_intr01 & CRMFB_INTR_1_MASK) != 0xfff ||
-		    (d->y_intr23 & CRMFB_INTR_2_MASK) != 0xfff000 ||
-		    (d->y_intr23 & CRMFB_INTR_3_MASK) != 0xfff) {
-			fatal("[ sgi_gbe: WARNING: Y interrupts not yet implemented. ]\n");
-		}
-	}
-
-	// printf("d->frm_control = %08x  d->ovr_control = %08x\n", d->frm_control,d->ovr_control);
-
-	// NetBSD's crmfbreg.h documents the tileptr as having a "9 bit shift",
-	// but IRIX seems to put a value ending in 0x......80 there, and the
-	// last part of that address seems to matter.
-	// TODO: Double-check this with the real hardware.
-	
-	if (d->ovr_control & CRMFB_DMA_ENABLE) {
-		tiletable = (d->ovr_control & 0xffffff80);
-		bytes_per_pixel = 1;
-		partial_pixels = d->ovr_partial_pixels;
-		width_in_tiles = d->ovr_width_in_tiles;
-		select_palette(d, 17);	// TODO: is it always palette nr 17 for overlays?
-	} else if (d->frm_control & CRMFB_DMA_ENABLE) {
-		tiletable = (d->frm_control & 0xffffff80);
-		partial_pixels = d->partial_pixels;
-		width_in_tiles = d->width_in_tiles;
-		select_palette(d, d->cmap_select);
-	} else {
-		return;
-	}
-
-#ifdef GBE_DEBUG
-	fatal("[ sgi_gbe: dev_sgi_gbe_tick(): tiletable = 0x%llx, bytes_per_pixel = %i ]\n", (long long)tiletable,
-		bytes_per_pixel);
-#endif
-
-	if (tiletable == 0)
-		return;
-
-	// Nr of tiles horizontally:
-	int w = width_in_tiles + (partial_pixels > 0 ? 1 : 0);
-
-	// Actually, the number of tiles vertically is usually very few,
-	// but this algorithm will render "up to" 256 and abort as soon
-	// as the screen is filled instead. This makes it work for both
-	// Linux' "tweaked linear" mode and all the other guest OSes.
-	const int max_nr_of_tiles = 256;
-	
-	uint32_t tile[max_nr_of_tiles];
-	uint8_t alltileptrs[max_nr_of_tiles * sizeof(uint16_t)];
-	
-	cpu->memory_rw(cpu, cpu->mem, tiletable,
-	    alltileptrs, sizeof(alltileptrs), MEM_READ,
-	    NO_EXCEPTIONS | PHYSICAL);
-
-	for (int i = 0; i < 256; ++i) {
-		tile[i] = (256 * alltileptrs[i*2] + alltileptrs[i*2+1]) << 16;
-#ifdef GBE_DEBUG
-		if (tile[i] != 0)
-			printf("tile[%i] = 0x%08x\n", i, tile[i]);
-#endif
-	}
-
-	int screensize = d->xres * d->yres * 3;
-	int x = 0, y = 0;
-
-	for (int tiley = 0; tiley < max_nr_of_tiles; ++tiley) {
-		for (int line = 0; line < 128; ++line) {
-			for (int tilex = 0; tilex < w; ++tilex) {
-				int tilenr = tilex + tiley * w;
-				
-				if (tilenr >= max_nr_of_tiles)
-					continue;
-				
-				uint32_t base = tile[tilenr];
-				
-				if (base == 0)
-					continue;
-				
-				// Read one line of up to 512 bytes from the tile.
-				int len = tilex < width_in_tiles ? 512 : (partial_pixels * bytes_per_pixel);
-
-				cpu->memory_rw(cpu, cpu->mem, base + 512 * line,
-				    buf, len, MEM_READ, NO_EXCEPTIONS | PHYSICAL);
-
-				int fb_offset = (x + y * d->xres) * 3;
-				int fb_len = (len / bytes_per_pixel) * 3;
-
-				if (fb_offset + fb_len > screensize) {
-					fb_len = screensize - fb_offset;
-				}
-				
-				if (fb_len <= 0) {
-					tiley = max_nr_of_tiles;  // to break
-					tilex = w;
-					line = 128;
-				}
-
-				uint8_t fb_buf[512 * 3];
-				int fb_i = 0;
-				for (int i = 0; i < 512; i+=bytes_per_pixel) {
-					uint32_t color;
-					if (bytes_per_pixel == 1)
-						color = buf[i];
-					else if (bytes_per_pixel == 2)
-						color = (buf[i]<<8) + buf[i+1];
-					else // if (bytes_per_pixel == 4)
-						color = (buf[i]<<24) + (buf[i+1]<<16)
-							+ (buf[i+2]<<8)+buf[i+3];
-					get_rgb(d, color,
-					    &fb_buf[fb_i],
-					    &fb_buf[fb_i+1],
-					    &fb_buf[fb_i+2]);
-					fb_i += 3;
-				}
-
-				dev_fb_access(cpu, cpu->mem, fb_offset,
-				    fb_buf, fb_len, MEM_WRITE, d->fb_data);
-
-				x += len / bytes_per_pixel;
-				if (x >= d->xres) {
-					x -= d->xres;
-					++y;
-					if (y >= d->yres) {
-						tiley = max_nr_of_tiles; // to break
-						tilex = w;
-						line = 128;
-					}
-				}
-			}
-		}
-	}
-
-	if (d->cursor_control & CRMFB_CURSOR_ON) {
-		int16_t cx = d->cursor_pos & 0xffff;
-		int16_t cy = d->cursor_pos >> 16;
-
-		if (d->cursor_control & CRMFB_CURSOR_CROSSHAIR) {
-			uint8_t pixel[3];
-			pixel[0] = d->cursor_cmap0 >> 24;
-			pixel[1] = d->cursor_cmap0 >> 16;
-			pixel[2] = d->cursor_cmap0 >> 8;
-
-			if (cx >= 0 && cx < d->xres) {
-				for (y = 0; y < d->yres; ++y)
-					dev_fb_access(cpu, cpu->mem, (cx + y * d->xres) * 3,
-					    pixel, 3, MEM_WRITE, d->fb_data);
-			}
-
-			// TODO: Rewrite as a single framebuffer block write?
-			if (cy >= 0 && cy < d->yres) {
-				for (x = 0; x < d->xres; ++x)
-					dev_fb_access(cpu, cpu->mem, (x + cy * d->xres) * 3,
-					    pixel, 3, MEM_WRITE, d->fb_data);
-			}
-		} else {
-			uint8_t pixel[3];
-			int sx, sy;
-
-			for (int dy = 0; dy < 32; ++dy) {
-				for (int dx = 0; dx < 32; ++dx) {
-					sx = cx + dx;
-					sy = cy + dy;
-					
-					if (sx < 0 || sx >= d->xres ||
-					    sy < 0 || sy >= d->yres)
-						continue;
-					
-					int wordindex = dy*2 + (dx>>4);
-					uint32_t word = d->cursor_bitmap[wordindex];
-					
-					int color = (word >> ((15 - (dx&15))*2)) & 3;
-					
-					if (!color)
-						continue;
-
-					if (color == 1) {
-						pixel[0] = d->cursor_cmap0 >> 24;
-						pixel[1] = d->cursor_cmap0 >> 16;
-						pixel[2] = d->cursor_cmap0 >> 8;
-					} else if (color == 2) {
-						pixel[0] = d->cursor_cmap1 >> 24;
-						pixel[1] = d->cursor_cmap1 >> 16;
-						pixel[2] = d->cursor_cmap1 >> 8;
-					} else {
-						pixel[0] = d->cursor_cmap2 >> 24;
-						pixel[1] = d->cursor_cmap2 >> 16;
-						pixel[2] = d->cursor_cmap2 >> 8;
-					}
-
-					dev_fb_access(cpu, cpu->mem, (sx + sy * d->xres) * 3,
-					    pixel, 3, MEM_WRITE, d->fb_data);
-				}
-			}
-		}
-	}
-}
-
-
-DEVICE_ACCESS(sgi_gbe)
-{
-	struct sgi_gbe_data *d = (struct sgi_gbe_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE) {
-		idata = memory_readmax64(cpu, data, len);
-
-#ifdef GBE_DEBUG
-		fatal("[ sgi_gbe: DEBUG: write to address 0x%llx, data"
-		    "=0x%llx ]\n", (long long)relative_addr, (long long)idata);
-#endif
-	}
-
-	switch (relative_addr) {
-
-	case CRMFB_CTRLSTAT:	// 0x0
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_gbe: write to ctrlstat: 0x%08x ]\n", (int)idata);
-			d->ctrlstat = (idata & ~CRMFB_CTRLSTAT_CHIPID_MASK)
-				| (d->ctrlstat & CRMFB_CTRLSTAT_CHIPID_MASK);
-		} else
-			odata = d->ctrlstat;
-		break;
-
-	case CRMFB_DOTCLOCK:	// 0x4
-		if (writeflag == MEM_WRITE)
-			d->dotclock = idata;
-		else
-			odata = d->dotclock;
-		break;
-
-	case CRMFB_I2C_VGA:	// 0x8
-		/*
-		 *  "CRT I2C control".
-		 *
-		 *  I'm not sure what this does. It isn't really commented
-		 *  in the Linux sources.  The IP32 PROM writes the values
-		 *  0x03, 0x01, and then 0x00 to this address, and then
-		 *  reads back a value.
-		 */
-		if (writeflag == MEM_WRITE) {
-			//if (!(d->i2c & CRMFB_I2C_SCL) &&
-			//    (idata & CRMFB_I2C_SCL)) {
-			//	fatal("vga i2c data: %i\n", idata & CRMFB_I2C_SDA);
-			//}
-
-			d->i2c = idata;
-		} else {
-			odata = d->i2c;
-			odata |= 1;	/*  ?  The IP32 prom wants this?  */
-		}
-		break;
-
-	case CRMFB_I2C_FP:	// 0x10, i2cfp, flat panel control
-		if (writeflag == MEM_WRITE) {
-			//if (d->i2c & CRMFB_I2C_SCL &&
-			//    !(idata & CRMFB_I2C_SCL)) {
-			//	fatal("fp i2c data: %i\n", idata & CRMFB_I2C_SDA);
-			//}
-
-			d->i2cfp = idata;
-		} else {
-			odata = d->i2cfp;
-			odata |= 1;	/*  ?  The IP32 prom wants this?  */
-		}
-		break;
-
-	case CRMFB_DEVICE_ID:	// 0x14
-		odata = CRMFB_DEVICE_ID_DEF;
-		break;
-
-	case CRMFB_VT_XY:	// 0x10000
-		if (writeflag == MEM_WRITE)
-			d->freeze = idata & 0x80000000;
-		else {
-			/*
-			 *  vt_xy, according to Linux:
-			 *
-			 * bit 31 = freeze, 23..12 = cury, 11.0 = curx
-			 */
-			/*  odata = ((random() % (d->yres + 10)) << 12)
-			    + (random() % (d->xres + 10)) +
-			    d->freeze;  */
-
-			/*
-			 *  Hack for IRIX/IP32. During startup, it waits for
-			 *  the value to be over 0x400 (in "gbeRun").
-			 *
-			 *  Hack for the IP32 PROM: During startup, it waits
-			 *  for the value to be above 0x500 (I think).
-			 */
-			odata = d->freeze | (random() & 1 ? 0x3ff : 0x501);
-		}
-		break;
-
-	case CRMFB_VT_XYMAX:	// 0x10004, vt_xymax, according to Linux & NetBSD
-		odata = ((d->yres-1) << 12) + d->xres-1;
-		/*  ... 12 bits maxy, 12 bits maxx.  */
-		break;
-
-	case CRMFB_VT_VSYNC:	// 0x10008
-	case CRMFB_VT_HSYNC:	// 0x1000c
-	case CRMFB_VT_VBLANK:	// 0x10010
-	case CRMFB_VT_HBLANK:	// 0x10014
-		// TODO
-		break;
-
-	case CRMFB_VT_FLAGS:	// 0x10018
-		// OpenBSD/sgi writes to this register.
-		break;
-
-	case CRMFB_VT_FRAMELOCK:	// 0x1001c
-		// TODO.
-		break;
-
-	case CRMFB_VT_INTR01:	// 0x10020
-		if (writeflag == MEM_WRITE)
-			d->y_intr01 = idata;
-		break;
-
-	case CRMFB_VT_INTR23:	// 0x10024
-		if (writeflag == MEM_WRITE)
-			d->y_intr23 = idata;
-		break;
-
-	case 0x10028:	// 0x10028
-	case 0x1002c:	// 0x1002c
-	case 0x10030:	// 0x10030
-		// TODO: Unknown, written to by the PROM?
-		break;
-
-	case CRMFB_VT_HPIX_EN:	// 0x10034, vt_hpixen, according to Linux
-		odata = (0 << 12) + d->xres-1;
-		/*  ... 12 bits on, 12 bits off.  */
-		break;
-
-	case CRMFB_VT_VPIX_EN:	// 0x10038, vt_vpixen, according to Linux
-		odata = (0 << 12) + d->yres-1;
-		/*  ... 12 bits on, 12 bits off.  */
-		break;
-
-	case CRMFB_VT_HCMAP:	// 0x1003c
-		if (writeflag == MEM_WRITE) {
-			d->xres = (idata & CRMFB_HCMAP_ON_MASK) >> CRMFB_VT_HCMAP_ON_SHIFT;
-			dev_fb_resize(d->fb_data, d->xres, d->yres);
-		}
-		
-		odata = (d->xres << CRMFB_VT_HCMAP_ON_SHIFT) + d->xres + 100;
-		break;
-
-	case CRMFB_VT_VCMAP:	// 0x10040
-		if (writeflag == MEM_WRITE) {
-			d->yres = (idata & CRMFB_VCMAP_ON_MASK) >> CRMFB_VT_VCMAP_ON_SHIFT;
-			dev_fb_resize(d->fb_data, d->xres, d->yres);
-		}
-
-		odata = (d->yres << CRMFB_VT_VCMAP_ON_SHIFT) + d->yres + 100;
-		break;
-
-	case CRMFB_VT_DID_STARTXY:	// 0x10044
-	case CRMFB_VT_CRS_STARTXY:	// 0x10048
-	case CRMFB_VT_VC_STARTXY:	// 0x1004c
-		// TODO
-		break;
-		
-	case CRMFB_OVR_WIDTH_TILE:	// 0x20000
-		if (writeflag == MEM_WRITE) {
-			d->ovr_tilesize = idata;
-
-			d->ovr_width_in_tiles = (idata >> CRMFB_FRM_TILESIZE_WIDTH_SHIFT) & 0xff;
-			d->ovr_partial_pixels = ((idata >> CRMFB_FRM_TILESIZE_RHS_SHIFT) & 0x1f) * 32;
-
-			debug("[ sgi_gbe: OVR setting width in tiles = %i, partial pixels = %i ]\n",
-			    d->ovr_width_in_tiles, d->ovr_partial_pixels);
-		} else
-			odata = d->ovr_tilesize;
-		break;
-
-	case CRMFB_OVR_TILE_PTR:	// 0x20004
-		odata = d->ovr_control ^ (random() & 1);
-		break;
-
-	case CRMFB_OVR_CONTROL:		// 0x20008
-		if (writeflag == MEM_WRITE)
-			d->ovr_control = idata;
-		else
-			odata = d->ovr_control;
-		break;
-
-	case CRMFB_FRM_TILESIZE:	// 0x30000:
-		if (writeflag == MEM_WRITE) {
-			d->tilesize = idata;
-
-			d->bitdepth = 8 << ((d->tilesize >> CRMFB_FRM_TILESIZE_DEPTH_SHIFT) & 3);
-			d->width_in_tiles = (idata >> CRMFB_FRM_TILESIZE_WIDTH_SHIFT) & 0xff;
-			d->partial_pixels = ((idata >> CRMFB_FRM_TILESIZE_RHS_SHIFT) & 0x1f) * 32 * 8 / d->bitdepth;
-
-			debug("[ sgi_gbe: setting color depth to %i bits, width in tiles = %i, partial pixels = %i ]\n",
-			    d->bitdepth, d->width_in_tiles, d->partial_pixels);
-		} else
-			odata = d->tilesize;
-		break;
-
-	case CRMFB_FRM_PIXSIZE:	// 0x30004
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_gbe: setting PIXSIZE to 0x%08x ]\n", (int)idata);
-		}
-		break;
-		
-	case 0x30008:
-		// TODO: Figure out exactly what the low bits do.
-		// Irix seems to want 0x20 to "sometimes" be on or off here.
-		odata = d->frm_control ^ (random() & 0x20);
-		break;
-
-	case CRMFB_FRM_CONTROL:	// 0x3000c
-		/*
-		 *  Writes to 3000c should be readable back at 30008?
-		 *  At least bit 0 (dma) ctrl 3.
-		 */
-		if (writeflag == MEM_WRITE) {
-			d->frm_control = idata;
-			debug("[ sgi_gbe: frm_control = 0x%08x ]\n", d->frm_control);
-		} else
-			odata = d->frm_control;
-		break;
-
-	case CRMFB_DID_PTR:	// 0x40000
-		odata = random();	/*  IP32 prom test hack. TODO  */
-		/*  IRIX wants 0x20, it seems.  */
-		if (random() & 1)
-			odata = 0x20;
-		break;
-
-	case CRMFB_DID_CONTROL:	// 0x40004
-		// TODO
-		break;
-
-	case CRMFB_CMAP_FIFO:		// 0x58000
-		break;
-
-	case CRMFB_CURSOR_POS:		// 0x70000
-		if (writeflag == MEM_WRITE)
-			d->cursor_pos = idata;
-		else
-			odata = d->cursor_pos;
-		break;
-		
-	case CRMFB_CURSOR_CONTROL:	// 0x70004
-		if (writeflag == MEM_WRITE)
-			d->cursor_control = idata;
-		else
-			odata = d->cursor_control;
-		break;
-		
-	case CRMFB_CURSOR_CMAP0:	// 0x70008
-		if (writeflag == MEM_WRITE)
-			d->cursor_cmap0 = idata;
-		else
-			odata = d->cursor_cmap0;
-		break;
-		
-	case CRMFB_CURSOR_CMAP1:	// 0x7000c
-		if (writeflag == MEM_WRITE)
-			d->cursor_cmap1 = idata;
-		else
-			odata = d->cursor_cmap1;
-		break;
-		
-	case CRMFB_CURSOR_CMAP2:	// 0x70010
-		if (writeflag == MEM_WRITE)
-			d->cursor_cmap2 = idata;
-		else
-			odata = d->cursor_cmap2;
-		break;
-
-	/*
-	 *  Linux/sgimips seems to write color palette data to offset 0x50000
-	 *  to 0x503xx, and gamma correction data to 0x60000 - 0x603ff, as
-	 *  32-bit values at addresses divisible by 4 (formated as 0xrrggbb00).
-	 *
-	 *  "sgio2fb: initializing
-	 *   sgio2fb: I/O at 0xffffffffb6000000
-	 *   sgio2fb: tiles at ffffffffa2ef5000
-	 *   sgio2fb: framebuffer at ffffffffa1000000
-	 *   sgio2fb: 8192kB memory
-	 *   Console: switching to colour frame buffer device 80x30"
-	 *
-	 *  NetBSD's crmfb_set_palette, however, uses values in reverse, like this:
-	 *	val = (r << 8) | (g << 16) | (b << 24);
-	 */
-
-	default:
-		/*  WID at 0x48000 .. 0x48000 + 4*31:  */
-		if (relative_addr >= CRMFB_WID && relative_addr <= CRMFB_WID + 4 * 31) {
-			// TODO: Figure out how this really works. Why are
-			// there 32 such registers?
-			if (writeflag == MEM_WRITE) {
-				d->color_mode = (idata >> CRMFB_MODE_TYP_SHIFT) & 7;
-				d->cmap_select = (idata >> CRMFB_MODE_CMAP_SELECT_SHIFT) & 0x1f;
-			}
-
-			break;
-		}
-
-		/*  RGB Palette at 0x50000 .. 0x57fff:  */
-		if (relative_addr >= CRMFB_CMAP && relative_addr < CRMFB_CMAP + 256 * 32 * sizeof(uint32_t)) {
-			int color_index = (relative_addr - CRMFB_CMAP) >> 2;
-			if (writeflag == MEM_WRITE) {
-				int cmap = color_index >> 8;
-				d->palette[color_index] = idata;
-				if (cmap == d->cmap_select)
-					d->selected_palette[color_index] = idata;
-			} else {
-				odata = d->palette[color_index];
-			}
-			break;
-		}
-
-		/*  Gamma correction at 0x60000 .. 0x603ff:  */
-		if (relative_addr >= CRMFB_GMAP && relative_addr <= CRMFB_GMAP + 0x3ff) {
-			/*  ignore gamma correction for now  */
-			break;
-		}
-
-		/*  Cursor bitmap at 0x78000 ..:  */
-		if (relative_addr >= CRMFB_CURSOR_BITMAP && relative_addr <= CRMFB_CURSOR_BITMAP + 0xff) {
-			if (len != 4) {
-				printf("unimplemented CRMFB_CURSOR_BITMAP len %i\n", (int)len);
-			}
-
-			int index = (relative_addr & 0xff) / 4;
-			if (writeflag == MEM_WRITE)
-				d->cursor_bitmap[index] = idata;
-			else
-				odata = d->cursor_bitmap[index];
-			break;
-		}
-
-		if (writeflag == MEM_WRITE)
-			fatal("[ sgi_gbe: unimplemented write to address "
-			    "0x%llx, data=0x%llx ]\n",
-			    (long long)relative_addr, (long long)idata);
-		else
-			fatal("[ sgi_gbe: unimplemented read from address "
-			    "0x%llx ]\n", (long long)relative_addr);
-	}
-
-	if (writeflag == MEM_READ) {
-#ifdef GBE_DEBUG
-		debug("[ sgi_gbe: DEBUG: read from address 0x%llx: 0x%llx ]\n",
-		    (long long)relative_addr, (long long)odata);
-#endif
-		memory_writemax64(cpu, data, len, odata);
-	}
-
-	return 1;
-}
-
-
-void dev_sgi_gbe_init(struct machine *machine, struct memory *mem, uint64_t baseaddr)
-{
-	struct sgi_gbe_data *d;
-
-	CHECK_ALLOCATION(d = (struct sgi_gbe_data *) malloc(sizeof(struct sgi_gbe_data)));
-	memset(d, 0, sizeof(struct sgi_gbe_data));
-
-	d->xres = GBE_DEFAULT_XRES;
-	d->yres = GBE_DEFAULT_YRES;
-	d->bitdepth = GBE_DEFAULT_BITDEPTH;
-	
-	// My O2 says 0x300ae001 here (while running).
-	d->ctrlstat = CRMFB_CTRLSTAT_INTERNAL_PCLK |
-			CRMFB_CTRLSTAT_GPIO6_INPUT |
-			CRMFB_CTRLSTAT_GPIO5_INPUT |
-			CRMFB_CTRLSTAT_GPIO4_INPUT |
-			CRMFB_CTRLSTAT_GPIO4_SENSE |
-			CRMFB_CTRLSTAT_GPIO3_INPUT |
-			(CRMFB_CTRLSTAT_CHIPID_MASK & 1);
-
-	// Set a value in the interrupt register that will "never happen" by default.
-	d->y_intr01 = (0xfff << 12) | 0xfff;
-	d->y_intr23 = (0xfff << 12) | 0xfff;
-
-	// Grayscale palette, most likely overwritten immediately by the
-	// guest operating system.
-	for (int i = 0; i < 256; ++i)
-		d->palette[i] = i * 0x01010100UL;
-
-	d->fb_data = dev_fb_init(machine, mem, FAKE_GBE_FB_ADDRESS,
-	    VFB_GENERIC, d->xres, d->yres, d->xres, d->yres, 24, "SGI GBE");
-
-	memory_device_register(mem, "sgi_gbe", baseaddr, DEV_SGI_GBE_LENGTH,
-	    dev_sgi_gbe_access, d, DM_DEFAULT, NULL);
-	machine_add_tickfunction(machine, dev_sgi_gbe_tick, d, 19);
-}
-
-
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_ip19.c gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip19.c
--- gxemul-0.6.2/src/devices/dev_sgi_ip19.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip19.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,127 @@
+/*
+ *  Copyright (C) 2004-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: SGI IP19 (and IP25) stuff
+ *
+ *  NOTE/TODO: The stuff in here is mostly guesswork.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	DEV_SGI_IP19_LENGTH	0x100000
+
+struct sgi_ip19_data {
+	uint64_t	cycle_counter;
+};
+
+
+DEVICE_ACCESS(sgi_ip19)
+{
+	struct sgi_ip19_data *d = (struct sgi_ip19_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	// int regnr = relative_addr / sizeof(uint32_t);
+
+	switch (relative_addr) {
+
+	case 0x08:	/*  cpu id  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip19: unimplemented write to address "
+			    "0x%x (cpu id), data=0x%08x ]\n", (int)
+			    relative_addr, (int)idata);
+		} else {
+			odata = cpu->cpu_id;	/*  ?  TODO  */
+		}
+		break;
+
+	case 0x200:	/*  cpu available mask?  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip19: unimplemented write to address "
+			    "0x%x (cpu available mask), data=0x%08x ]\n",
+			    (int)relative_addr, (int)idata);
+		} else {
+			/*  Max 16 cpus?  */
+			odata = ((1 << cpu->machine->ncpus) - 1) << 16;
+		}
+		break;
+
+	case 0x20000:	/*  cycle counter or clock  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip19: unimplemented write to address "
+			    "0x%x (cycle counter), data=0x%08x ]\n",
+			    (int)relative_addr, (int)idata);
+		} else {
+			d->cycle_counter += 100;
+			odata = d->cycle_counter;
+		}
+
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip19: unimplemented write to address "
+			    "0x%x, data=0x%08x ]\n", (int)relative_addr,
+			    (int)idata);
+		} else {
+			debug("[ sgi_ip19: unimplemented read from address "
+			    "0x%x: 0x%08x ]\n", (int)relative_addr, (int)odata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(sgi_ip19)
+{
+	struct sgi_ip19_data *d;
+
+	CHECK_ALLOCATION(d = (struct sgi_ip19_data *) malloc(sizeof(struct sgi_ip19_data)));
+	memset(d, 0, sizeof(struct sgi_ip19_data));
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_SGI_IP19_LENGTH,
+	    dev_sgi_ip19_access, (void *)d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_ip19.cc gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip19.cc
--- gxemul-0.6.2/src/devices/dev_sgi_ip19.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip19.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,128 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: SGI IP19 (and IP25) stuff
- *
- *  NOTE/TODO: The stuff in here is mostly guesswork.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define	DEV_SGI_IP19_LENGTH	0x100000
-
-struct sgi_ip19_data {
-	uint64_t	cycle_counter;
-};
-
-
-DEVICE_ACCESS(sgi_ip19)
-{
-	struct sgi_ip19_data *d = (struct sgi_ip19_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	regnr = relative_addr / sizeof(uint32_t);
-
-	switch (relative_addr) {
-
-	case 0x08:	/*  cpu id  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip19: unimplemented write to address "
-			    "0x%x (cpu id), data=0x%08x ]\n", (int)
-			    relative_addr, (int)idata);
-		} else {
-			odata = cpu->cpu_id;	/*  ?  TODO  */
-		}
-		break;
-
-	case 0x200:	/*  cpu available mask?  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip19: unimplemented write to address "
-			    "0x%x (cpu available mask), data=0x%08x ]\n",
-			    (int)relative_addr, (int)idata);
-		} else {
-			/*  Max 16 cpus?  */
-			odata = ((1 << cpu->machine->ncpus) - 1) << 16;
-		}
-		break;
-
-	case 0x20000:	/*  cycle counter or clock  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip19: unimplemented write to address "
-			    "0x%x (cycle counter), data=0x%08x ]\n",
-			    (int)relative_addr, (int)idata);
-		} else {
-			d->cycle_counter += 100;
-			odata = d->cycle_counter;
-		}
-
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip19: unimplemented write to address "
-			    "0x%x, data=0x%08x ]\n", (int)relative_addr,
-			    (int)idata);
-		} else {
-			debug("[ sgi_ip19: unimplemented read from address "
-			    "0x%x: 0x%08x ]\n", (int)relative_addr, (int)odata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(sgi_ip19)
-{
-	struct sgi_ip19_data *d;
-
-	CHECK_ALLOCATION(d = (struct sgi_ip19_data *) malloc(sizeof(struct sgi_ip19_data)));
-	memset(d, 0, sizeof(struct sgi_ip19_data));
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_SGI_IP19_LENGTH,
-	    dev_sgi_ip19_access, (void *)d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_ip20.c gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip20.c
--- gxemul-0.6.2/src/devices/dev_sgi_ip20.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip20.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,113 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: SGI IP20 stuff
+ *
+ *  TODO.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "devices.h"
+#include "memory.h"
+#include "misc.h"
+
+
+extern int quiet_mode;
+
+
+DEVICE_ACCESS(sgi_ip20)
+{
+	/*  struct sgi_ip20_data *d = extra;  */
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case 0x38:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip20: write to address 0x%x, "
+			    "data=0x%02x ]\n", (int)relative_addr, (int)idata);
+		} else {
+			/*
+			 *  TODO:
+			 *
+			 *  I haven't had time to figure out what values should
+			 *  be returned by this device.  Simple bit patterns
+			 *  don't seem to be enough, but using random() is
+			 *  obviously pretty bad.  This must be fixed some day.
+			 */
+
+			/*  instruction_trace = 1;  quiet_mode = 0;  */
+			odata = random() & 0xff;
+
+			debug("[ sgi_ip20: read from address 0x%x: 0x%x ]\n",
+			    (int)relative_addr, (int)odata);
+		}
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip20: unimplemented write to address "
+			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
+			    (int)idata);
+		} else {
+			debug("[ sgi_ip20: unimplemented read from address "
+			    "0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+struct sgi_ip20_data *dev_sgi_ip20_init(struct cpu *cpu, struct memory *mem,
+	uint64_t baseaddr)
+{
+	struct sgi_ip20_data *d;
+
+	CHECK_ALLOCATION(d = (struct sgi_ip20_data *) malloc(sizeof(struct sgi_ip20_data)));
+	memset(d, 0, sizeof(struct sgi_ip20_data));
+
+	/*
+	 *  This device is detected as int0 by NetBSD 2.0_BETA, so I call it
+	 *  "sgi_ip20_int".
+	 */
+	memory_device_register(mem, "sgi_ip20_int", baseaddr,
+	    DEV_SGI_IP20_LENGTH, dev_sgi_ip20_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	return d;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_ip20.cc gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip20.cc
--- gxemul-0.6.2/src/devices/dev_sgi_ip20.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip20.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,113 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: SGI IP20 stuff
- *
- *  TODO.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "devices.h"
-#include "memory.h"
-#include "misc.h"
-
-
-extern int quiet_mode;
-
-
-DEVICE_ACCESS(sgi_ip20)
-{
-	/*  struct sgi_ip20_data *d = extra;  */
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case 0x38:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip20: write to address 0x%x, "
-			    "data=0x%02x ]\n", (int)relative_addr, (int)idata);
-		} else {
-			/*
-			 *  TODO:
-			 *
-			 *  I haven't had time to figure out what values should
-			 *  be returned by this device.  Simple bit patterns
-			 *  don't seem to be enough, but using random() is
-			 *  obviously pretty bad.  This must be fixed some day.
-			 */
-
-			/*  instruction_trace = 1;  quiet_mode = 0;  */
-			odata = random() & 0xff;
-
-			debug("[ sgi_ip20: read from address 0x%x: 0x%x ]\n",
-			    (int)relative_addr, (int)odata);
-		}
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip20: unimplemented write to address "
-			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
-			    (int)idata);
-		} else {
-			debug("[ sgi_ip20: unimplemented read from address "
-			    "0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-struct sgi_ip20_data *dev_sgi_ip20_init(struct cpu *cpu, struct memory *mem,
-	uint64_t baseaddr)
-{
-	struct sgi_ip20_data *d;
-
-	CHECK_ALLOCATION(d = (struct sgi_ip20_data *) malloc(sizeof(struct sgi_ip20_data)));
-	memset(d, 0, sizeof(struct sgi_ip20_data));
-
-	/*
-	 *  This device is detected as int0 by NetBSD 2.0_BETA, so I call it
-	 *  "sgi_ip20_int".
-	 */
-	memory_device_register(mem, "sgi_ip20_int", baseaddr,
-	    DEV_SGI_IP20_LENGTH, dev_sgi_ip20_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	return d;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_ip22.c gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip22.c
--- gxemul-0.6.2/src/devices/dev_sgi_ip22.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip22.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,437 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: SGI IP22 stuff
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/imcreg.h"
+
+
+#define	SGI_IP22_TICK_SHIFT		14
+
+
+DEVICE_TICK(sgi_ip22)
+{
+	struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
+
+	// TODO: Document this!
+	if (d->reg[0x38 / 4] != 0)
+		d->reg[0x38 / 4] --;
+}
+
+
+/*
+ *  dev_sgi_ip22_imc_access():
+ *
+ *  The memory controller (?).
+ */
+DEVICE_ACCESS(sgi_ip22_imc)
+{
+	struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int regnr;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	regnr = relative_addr / sizeof(uint32_t);
+
+	if (writeflag == MEM_WRITE)
+		d->imc_reg[regnr] = idata;
+	else
+		odata = d->imc_reg[regnr];
+
+	switch (relative_addr) {
+	case (IMC_CPUCTRL0 - IP22_IMC_BASE):
+		if (writeflag == MEM_WRITE) {
+			/*  debug("[ sgi_ip22_imc: write to "
+			    "IMC_CPUCTRL0, data=0x%08x ]\n", (int)idata);  */
+		} else {
+			/*  debug("[ sgi_ip22_imc: read from IMC_CPUCTRL0, "
+			    "data=0x%08x ]\n", (int)odata);  */
+		}
+		break;
+	case (IMC_SYSID - IP22_IMC_BASE):
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22_imc: unimplemented write "
+			    "IMC_SYSID, data=0x%08x ]\n", (int)idata);
+		} else {
+			/*  Lowest 4 bits are the revision bits.  */
+			odata = 3;  /*  + IMC_SYSID_HAVEISA;  */
+			/*  debug("[ sgi_ip22_imc: read from IMC_SYSID, "
+			    "data=0x%08x ]\n", (int)odata);  */
+		}
+		break;
+	case (IMC_WDOG - IP22_IMC_BASE):
+		if (writeflag == MEM_WRITE) {
+			/*  debug("[ sgi_ip22_imc: write to IMC_WDOG, "
+			    "data=0x%08x ]\n", (int)idata);  */
+		} else {
+			/*  debug("[ sgi_ip22_imc: read from IMC_WDOG, "
+			    "data=0x%08x ]\n", (int)odata);  */
+		}
+		break;
+	case (IMC_MEMCFG0 - IP22_IMC_BASE):
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22_imc: unimplemented write "
+			    "IMC_MEMCFG0, data=0x%08x ]\n", (int)idata);
+		} else {
+			odata = 0x3100 + (0x8000000 >> 22);  /*  ? TODO  */
+			/*  debug("[ sgi_ip22_imc: read from IMC_MEMCFG0,"
+			    " data=0x%08x ]\n", (int)odata);  */
+		}
+		break;
+	case (IMC_MEMCFG1 - IP22_IMC_BASE):
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22_imc: unimplemented write "
+			    "IMC_MEMCFG1, data=0x%08x ]\n", (int)idata);
+		} else {
+			odata = 0;
+			/*  debug("[ sgi_ip22_imc: read from IMC_MEMCFG1, "
+			    "data=0x%08x ]\n", (int)odata);  */
+		}
+		break;
+	case (IMC_EEPROM - IP22_IMC_BASE):
+		/*
+		 *  The IP22 prom tries to access this during bootup,
+		 *  but I have no idea how it works.
+		 */
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22_imc: write to IMC_EEPROM, data="
+			    "0x%08x ]\n", (int)idata);
+		} else {
+			odata = random() & 0x1e;
+			debug("[ sgi_ip22_imc: read from IMC_WDOG, "
+			    "data=0x%08x ]\n", (int)odata);
+		}
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22_imc: unimplemented write to "
+			    "address 0x%x, data=0x%08x ]\n",
+			    (int)relative_addr, (int)idata);
+		} else {
+			debug("[ sgi_ip22_imc: unimplemented read from "
+			    "address 0x%x, data=0x%08x ]\n",
+			    (int)relative_addr, (int)odata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_sgi_ip22_unknown_access():
+ *
+ *  A so far unknown device, used by the IP22 prom during startup.
+ */
+DEVICE_ACCESS(sgi_ip22_unknown)
+{
+	struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+	case 0x04:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22_unknown: write to address 0x%x,"
+			    " data=0x%08x ]\n", (int)relative_addr, (int)idata);
+		} else {
+			odata = d->unknown_timer;
+			d->unknown_timer += 100;
+			debug("[ sgi_ip22_unknown: read from address 0x%x, "
+			    "data=0x%08x ]\n", (int)relative_addr, (int)odata);
+		}
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22_unknown: unimplemented write to "
+			    "address 0x%x, data=0x%08x ]\n",
+			    (int)relative_addr, (int)idata);
+		} else {
+			debug("[ sgi_ip22_unknown: unimplemented read from "
+			    "address 0x%x, data=0x%08x ]\n",
+			    (int)relative_addr, (int)odata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_sgi_ip22_unknown2_access():
+ *
+ *  A so far unknown device, used by the IP22 prom during startup.
+ */
+DEVICE_ACCESS(sgi_ip22_unknown2)
+{
+	struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int regnr;
+
+	idata = memory_readmax64(cpu, data, len);
+	regnr = relative_addr / sizeof(uint32_t);
+
+	if (writeflag == MEM_WRITE)
+		d->unknown2_reg[regnr] = idata;
+	else
+		odata = d->unknown2_reg[regnr];
+
+	switch (relative_addr) {
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22_unknown2: unimplemented write "
+			    "to address 0x%x, data=0x%08x ]\n",
+			    (int)relative_addr, (int)idata);
+		} else {
+			debug("[ sgi_ip22_unknown2: unimplemented read from "
+			    "address 0x%x, data=0x%08x ]\n",
+			    (int)relative_addr, (int)odata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(sgi_ip22_sysid)
+{
+	struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	idata = memory_readmax64(cpu, data, len);
+
+	if (writeflag == MEM_WRITE) {
+		debug("[ sgi_ip22_sysid: write to address 0x%x, "
+		    "data=0x%08x ]\n", (int)relative_addr, (int)idata);
+	} else {
+		/*
+		 *  According to NetBSD's sgimips/ip22.c:
+		 *
+		 *  printf("IOC rev %d, machine %s, board rev %d\n",
+		 *	(sysid >> 5) & 0x07,
+		 *	(sysid & 1) ? "Indigo2 (Fullhouse)" : "Indy (Guiness)",
+		 *	(sysid >> 1) & 0x0f);
+		 */
+
+		/*  IOC rev 1, Guiness, board rev 3:  */
+		odata = (1 << 5) + (3 << 1) + (d->guiness_flag? 0 : 1);
+
+		debug("[ sgi_ip22_sysid: read from address 0x%x, data="
+		    "0x%08x ]\n", (int)relative_addr, (int)odata);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(sgi_ip22)
+{
+	struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int regnr;
+
+	idata = memory_readmax64(cpu, data, len);
+	regnr = relative_addr / sizeof(uint32_t);
+
+	if (writeflag == MEM_WRITE)
+		d->reg[regnr] = idata;
+	else
+		odata = d->reg[regnr];
+
+	/*  Read from/write to the sgi_ip22:  */
+	switch (relative_addr) {
+	case 0x00:	/*  local0 irq stat  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22: write to local0 IRQ STAT, "
+			    "data=0x%llx ]\n", (long long)idata);
+		} else {
+			debug("[ sgi_ip22: read from local0 IRQ STAT, "
+			    "data=0x%llx ]\n", (long long)odata);
+		}
+		break;
+	case 0x04:	/*  local0 irq mask  */
+		if (writeflag == MEM_WRITE) {
+			/*
+			 *  Ugly hack: if an interrupt is asserted, and someone
+			 *  writes to this mask register, the interrupt should
+			 *  be masked. That is, sgi_ip22_interrupt() in
+			 *  src/machine.c has to be called to deal with this.
+			 *  The ugly solution I choose here is to deassert
+			 *  some interrupt which should never be used anyway.
+			 *  (TODO: Fix this.)
+			 */
+
+fatal("TODO: ip22 legacy interrupt rewrite!\n");
+abort();
+
+//			cpu_interrupt_ack(cpu, 8 + 63);
+//			debug("[ sgi_ip22: write to local0 IRQ MASK, "
+//			    "data=0x%llx ]\n", (long long)idata);
+		} else {
+			debug("[ sgi_ip22: read from local0 IRQ MASK, "
+			    "data=0x%llx ]\n", (long long)odata);
+		}
+		break;
+	case 0x08:	/*  local1 irq stat  */
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22: write to local1 IRQ STAT, "
+			    "data=0x%llx ]\n", (long long)idata);
+		} else {
+			debug("[ sgi_ip22: read from local1 IRQ STAT, "
+			    "data=0x%llx ]\n", (long long)odata);
+		}
+		break;
+	case 0x0c:	/*  local1 irq mask  */
+		if (writeflag == MEM_WRITE) {
+			/*  See commen above, about local0 irq mask.  */
+
+fatal("TODO: ip22 legacy interrupt rewrite!\n");
+abort();
+//			cpu_interrupt_ack(cpu, 8 + 63);
+//			debug("[ sgi_ip22: write to local1 IRQ MASK, "
+//			    "data=0x%llx ]\n", (long long)idata);
+		} else {
+			debug("[ sgi_ip22: read from local1 IRQ MASK, "
+			    "data=0x%llx ]\n", (long long)odata);
+		}
+		break;
+	case 0x10:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22: write to mappable IRQ STAT, "
+			    "data=0x%llx ]\n", (long long)idata);
+		} else {
+			debug("[ sgi_ip22: read from mappable IRQ STAT, "
+			    "data=0x%llx ]\n", (long long)odata);
+		}
+		break;
+	case 0x14:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22: write to mappable local0 IRQ "
+			    "MASK, data=0x%llx ]\n", (long long)idata);
+		} else {
+			debug("[ sgi_ip22: read from mappable local0 IRQ "
+			    "MASK, data=0x%llx ]\n", (long long)odata);
+		}
+		break;
+	case 0x18:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22: write to mappable local1 IRQ "
+			    "MASK, data=0x%llx ]\n", (long long)idata);
+		} else {
+			debug("[ sgi_ip22: read from mappable local1 IRQ "
+			    "MASK, data=0x%llx ]\n", (long long)odata);
+		}
+		break;
+	case 0x38:	/*  timer count  */
+		if (writeflag == MEM_WRITE) {
+			/*  Two byte values are written to this address,
+			    sequentially...  TODO  */
+		} else {
+			/*  The timer is decreased by the tick function.  */
+		}
+		break;
+	case 0x3b:	/*  ?  */
+		odata = random();
+		break;
+	case 0x3c:	/*  timer control  */
+		break;
+	case 0x3f:	/*  ?  */
+		odata = random();
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip22: unimplemented write to address "
+			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
+			    (int)idata);
+		} else {
+			debug("[ sgi_ip22: unimplemented read from address "
+			    "0x%llx ]\n", (long long)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+struct sgi_ip22_data *dev_sgi_ip22_init(struct machine *machine,
+	struct memory *mem, uint64_t baseaddr, int guiness_flag)
+{
+	struct sgi_ip22_data *d;
+
+	CHECK_ALLOCATION(d = (struct sgi_ip22_data *) malloc(sizeof(struct sgi_ip22_data)));
+	memset(d, 0, sizeof(struct sgi_ip22_data));
+
+	d->guiness_flag = guiness_flag;
+
+	memory_device_register(mem, "sgi_ip22", baseaddr, DEV_SGI_IP22_LENGTH,
+	    dev_sgi_ip22_access, (void *)d, DM_DEFAULT, NULL);
+	memory_device_register(mem, "sgi_ip22_sysid", 0x1fbd9858, 0x8,
+	    dev_sgi_ip22_sysid_access, (void *)d, DM_DEFAULT, NULL);
+	memory_device_register(mem, "sgi_ip22_imc", IP22_IMC_BASE,
+	    DEV_SGI_IP22_IMC_LENGTH, dev_sgi_ip22_imc_access, (void *)d,
+	    DM_DEFAULT, NULL);
+	memory_device_register(mem, "sgi_ip22_unknown", 0x1fa01000, 0x10,
+	    dev_sgi_ip22_unknown_access, (void *)d, DM_DEFAULT, NULL);
+	memory_device_register(mem, "sgi_ip22_unknown2", IP22_UNKNOWN2_BASE,
+	    DEV_SGI_IP22_UNKNOWN2_LENGTH, dev_sgi_ip22_unknown2_access,
+	    (void *)d, DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(machine, dev_sgi_ip22_tick, d,
+	    SGI_IP22_TICK_SHIFT);
+
+	return d;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_ip22.cc gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip22.cc
--- gxemul-0.6.2/src/devices/dev_sgi_ip22.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip22.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,437 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: SGI IP22 stuff
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/imcreg.h"
-
-
-#define	SGI_IP22_TICK_SHIFT		14
-
-
-DEVICE_TICK(sgi_ip22)
-{
-	struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
-
-	// TODO: Document this!
-	if (d->reg[0x38 / 4] != 0)
-		d->reg[0x38 / 4] --;
-}
-
-
-/*
- *  dev_sgi_ip22_imc_access():
- *
- *  The memory controller (?).
- */
-DEVICE_ACCESS(sgi_ip22_imc)
-{
-	struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	regnr = relative_addr / sizeof(uint32_t);
-
-	if (writeflag == MEM_WRITE)
-		d->imc_reg[regnr] = idata;
-	else
-		odata = d->imc_reg[regnr];
-
-	switch (relative_addr) {
-	case (IMC_CPUCTRL0 - IP22_IMC_BASE):
-		if (writeflag == MEM_WRITE) {
-			/*  debug("[ sgi_ip22_imc: write to "
-			    "IMC_CPUCTRL0, data=0x%08x ]\n", (int)idata);  */
-		} else {
-			/*  debug("[ sgi_ip22_imc: read from IMC_CPUCTRL0, "
-			    "data=0x%08x ]\n", (int)odata);  */
-		}
-		break;
-	case (IMC_SYSID - IP22_IMC_BASE):
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22_imc: unimplemented write "
-			    "IMC_SYSID, data=0x%08x ]\n", (int)idata);
-		} else {
-			/*  Lowest 4 bits are the revision bits.  */
-			odata = 3;  /*  + IMC_SYSID_HAVEISA;  */
-			/*  debug("[ sgi_ip22_imc: read from IMC_SYSID, "
-			    "data=0x%08x ]\n", (int)odata);  */
-		}
-		break;
-	case (IMC_WDOG - IP22_IMC_BASE):
-		if (writeflag == MEM_WRITE) {
-			/*  debug("[ sgi_ip22_imc: write to IMC_WDOG, "
-			    "data=0x%08x ]\n", (int)idata);  */
-		} else {
-			/*  debug("[ sgi_ip22_imc: read from IMC_WDOG, "
-			    "data=0x%08x ]\n", (int)odata);  */
-		}
-		break;
-	case (IMC_MEMCFG0 - IP22_IMC_BASE):
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22_imc: unimplemented write "
-			    "IMC_MEMCFG0, data=0x%08x ]\n", (int)idata);
-		} else {
-			odata = 0x3100 + (0x8000000 >> 22);  /*  ? TODO  */
-			/*  debug("[ sgi_ip22_imc: read from IMC_MEMCFG0,"
-			    " data=0x%08x ]\n", (int)odata);  */
-		}
-		break;
-	case (IMC_MEMCFG1 - IP22_IMC_BASE):
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22_imc: unimplemented write "
-			    "IMC_MEMCFG1, data=0x%08x ]\n", (int)idata);
-		} else {
-			odata = 0;
-			/*  debug("[ sgi_ip22_imc: read from IMC_MEMCFG1, "
-			    "data=0x%08x ]\n", (int)odata);  */
-		}
-		break;
-	case (IMC_EEPROM - IP22_IMC_BASE):
-		/*
-		 *  The IP22 prom tries to access this during bootup,
-		 *  but I have no idea how it works.
-		 */
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22_imc: write to IMC_EEPROM, data="
-			    "0x%08x ]\n", (int)idata);
-		} else {
-			odata = random() & 0x1e;
-			debug("[ sgi_ip22_imc: read from IMC_WDOG, "
-			    "data=0x%08x ]\n", (int)odata);
-		}
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22_imc: unimplemented write to "
-			    "address 0x%x, data=0x%08x ]\n",
-			    (int)relative_addr, (int)idata);
-		} else {
-			debug("[ sgi_ip22_imc: unimplemented read from "
-			    "address 0x%x, data=0x%08x ]\n",
-			    (int)relative_addr, (int)odata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_sgi_ip22_unknown_access():
- *
- *  A so far unknown device, used by the IP22 prom during startup.
- */
-DEVICE_ACCESS(sgi_ip22_unknown)
-{
-	struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-	case 0x04:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22_unknown: write to address 0x%x,"
-			    " data=0x%08x ]\n", (int)relative_addr, (int)idata);
-		} else {
-			odata = d->unknown_timer;
-			d->unknown_timer += 100;
-			debug("[ sgi_ip22_unknown: read from address 0x%x, "
-			    "data=0x%08x ]\n", (int)relative_addr, (int)odata);
-		}
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22_unknown: unimplemented write to "
-			    "address 0x%x, data=0x%08x ]\n",
-			    (int)relative_addr, (int)idata);
-		} else {
-			debug("[ sgi_ip22_unknown: unimplemented read from "
-			    "address 0x%x, data=0x%08x ]\n",
-			    (int)relative_addr, (int)odata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_sgi_ip22_unknown2_access():
- *
- *  A so far unknown device, used by the IP22 prom during startup.
- */
-DEVICE_ACCESS(sgi_ip22_unknown2)
-{
-	struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-
-	idata = memory_readmax64(cpu, data, len);
-	regnr = relative_addr / sizeof(uint32_t);
-
-	if (writeflag == MEM_WRITE)
-		d->unknown2_reg[regnr] = idata;
-	else
-		odata = d->unknown2_reg[regnr];
-
-	switch (relative_addr) {
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22_unknown2: unimplemented write "
-			    "to address 0x%x, data=0x%08x ]\n",
-			    (int)relative_addr, (int)idata);
-		} else {
-			debug("[ sgi_ip22_unknown2: unimplemented read from "
-			    "address 0x%x, data=0x%08x ]\n",
-			    (int)relative_addr, (int)odata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(sgi_ip22_sysid)
-{
-	struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	idata = memory_readmax64(cpu, data, len);
-
-	if (writeflag == MEM_WRITE) {
-		debug("[ sgi_ip22_sysid: write to address 0x%x, "
-		    "data=0x%08x ]\n", (int)relative_addr, (int)idata);
-	} else {
-		/*
-		 *  According to NetBSD's sgimips/ip22.c:
-		 *
-		 *  printf("IOC rev %d, machine %s, board rev %d\n",
-		 *	(sysid >> 5) & 0x07,
-		 *	(sysid & 1) ? "Indigo2 (Fullhouse)" : "Indy (Guiness)",
-		 *	(sysid >> 1) & 0x0f);
-		 */
-
-		/*  IOC rev 1, Guiness, board rev 3:  */
-		odata = (1 << 5) + (3 << 1) + (d->guiness_flag? 0 : 1);
-
-		debug("[ sgi_ip22_sysid: read from address 0x%x, data="
-		    "0x%08x ]\n", (int)relative_addr, (int)odata);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(sgi_ip22)
-{
-	struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-
-	idata = memory_readmax64(cpu, data, len);
-	regnr = relative_addr / sizeof(uint32_t);
-
-	if (writeflag == MEM_WRITE)
-		d->reg[regnr] = idata;
-	else
-		odata = d->reg[regnr];
-
-	/*  Read from/write to the sgi_ip22:  */
-	switch (relative_addr) {
-	case 0x00:	/*  local0 irq stat  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22: write to local0 IRQ STAT, "
-			    "data=0x%llx ]\n", (long long)idata);
-		} else {
-			debug("[ sgi_ip22: read from local0 IRQ STAT, "
-			    "data=0x%llx ]\n", (long long)odata);
-		}
-		break;
-	case 0x04:	/*  local0 irq mask  */
-		if (writeflag == MEM_WRITE) {
-			/*
-			 *  Ugly hack: if an interrupt is asserted, and someone
-			 *  writes to this mask register, the interrupt should
-			 *  be masked. That is, sgi_ip22_interrupt() in
-			 *  src/machine.c has to be called to deal with this.
-			 *  The ugly solution I choose here is to deassert
-			 *  some interrupt which should never be used anyway.
-			 *  (TODO: Fix this.)
-			 */
-
-fatal("TODO: ip22 legacy interrupt rewrite!\n");
-abort();
-
-//			cpu_interrupt_ack(cpu, 8 + 63);
-//			debug("[ sgi_ip22: write to local0 IRQ MASK, "
-//			    "data=0x%llx ]\n", (long long)idata);
-		} else {
-			debug("[ sgi_ip22: read from local0 IRQ MASK, "
-			    "data=0x%llx ]\n", (long long)odata);
-		}
-		break;
-	case 0x08:	/*  local1 irq stat  */
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22: write to local1 IRQ STAT, "
-			    "data=0x%llx ]\n", (long long)idata);
-		} else {
-			debug("[ sgi_ip22: read from local1 IRQ STAT, "
-			    "data=0x%llx ]\n", (long long)odata);
-		}
-		break;
-	case 0x0c:	/*  local1 irq mask  */
-		if (writeflag == MEM_WRITE) {
-			/*  See commen above, about local0 irq mask.  */
-
-fatal("TODO: ip22 legacy interrupt rewrite!\n");
-abort();
-//			cpu_interrupt_ack(cpu, 8 + 63);
-//			debug("[ sgi_ip22: write to local1 IRQ MASK, "
-//			    "data=0x%llx ]\n", (long long)idata);
-		} else {
-			debug("[ sgi_ip22: read from local1 IRQ MASK, "
-			    "data=0x%llx ]\n", (long long)odata);
-		}
-		break;
-	case 0x10:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22: write to mappable IRQ STAT, "
-			    "data=0x%llx ]\n", (long long)idata);
-		} else {
-			debug("[ sgi_ip22: read from mappable IRQ STAT, "
-			    "data=0x%llx ]\n", (long long)odata);
-		}
-		break;
-	case 0x14:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22: write to mappable local0 IRQ "
-			    "MASK, data=0x%llx ]\n", (long long)idata);
-		} else {
-			debug("[ sgi_ip22: read from mappable local0 IRQ "
-			    "MASK, data=0x%llx ]\n", (long long)odata);
-		}
-		break;
-	case 0x18:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22: write to mappable local1 IRQ "
-			    "MASK, data=0x%llx ]\n", (long long)idata);
-		} else {
-			debug("[ sgi_ip22: read from mappable local1 IRQ "
-			    "MASK, data=0x%llx ]\n", (long long)odata);
-		}
-		break;
-	case 0x38:	/*  timer count  */
-		if (writeflag == MEM_WRITE) {
-			/*  Two byte values are written to this address,
-			    sequentially...  TODO  */
-		} else {
-			/*  The timer is decreased by the tick function.  */
-		}
-		break;
-	case 0x3b:	/*  ?  */
-		odata = random();
-		break;
-	case 0x3c:	/*  timer control  */
-		break;
-	case 0x3f:	/*  ?  */
-		odata = random();
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip22: unimplemented write to address "
-			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
-			    (int)idata);
-		} else {
-			debug("[ sgi_ip22: unimplemented read from address "
-			    "0x%llx ]\n", (long long)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-struct sgi_ip22_data *dev_sgi_ip22_init(struct machine *machine,
-	struct memory *mem, uint64_t baseaddr, int guiness_flag)
-{
-	struct sgi_ip22_data *d;
-
-	CHECK_ALLOCATION(d = (struct sgi_ip22_data *) malloc(sizeof(struct sgi_ip22_data)));
-	memset(d, 0, sizeof(struct sgi_ip22_data));
-
-	d->guiness_flag = guiness_flag;
-
-	memory_device_register(mem, "sgi_ip22", baseaddr, DEV_SGI_IP22_LENGTH,
-	    dev_sgi_ip22_access, (void *)d, DM_DEFAULT, NULL);
-	memory_device_register(mem, "sgi_ip22_sysid", 0x1fbd9858, 0x8,
-	    dev_sgi_ip22_sysid_access, (void *)d, DM_DEFAULT, NULL);
-	memory_device_register(mem, "sgi_ip22_imc", IP22_IMC_BASE,
-	    DEV_SGI_IP22_IMC_LENGTH, dev_sgi_ip22_imc_access, (void *)d,
-	    DM_DEFAULT, NULL);
-	memory_device_register(mem, "sgi_ip22_unknown", 0x1fa01000, 0x10,
-	    dev_sgi_ip22_unknown_access, (void *)d, DM_DEFAULT, NULL);
-	memory_device_register(mem, "sgi_ip22_unknown2", IP22_UNKNOWN2_BASE,
-	    DEV_SGI_IP22_UNKNOWN2_LENGTH, dev_sgi_ip22_unknown2_access,
-	    (void *)d, DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(machine, dev_sgi_ip22_tick, d,
-	    SGI_IP22_TICK_SHIFT);
-
-	return d;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_ip30.c gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip30.c
--- gxemul-0.6.2/src/devices/dev_sgi_ip30.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip30.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,407 @@
+/*
+ *  Copyright (C) 2004-2018  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: SGI IP30 ("Octane") stuff
+ *
+ *  NOTE/TODO: This is just comprised of hardcoded guesses so far. (Ugly.)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	DEV_SGI_IP30_LENGTH		0x80000
+
+struct sgi_ip30_data {
+	/*  ip30:  */
+	uint64_t                imask0;         /*  0x10000  */
+	uint64_t                reg_0x10018;
+	uint64_t                isr;            /*  0x10030  */
+	uint64_t                reg_0x20000;
+	uint64_t                reg_0x30000;
+
+	/*  ip30_2:  */
+	uint64_t                reg_0x0029c;
+
+	/*  ip30_3:  */
+	uint64_t                reg_0x00284;
+
+	/*  ip30_4:  */
+	uint64_t                reg_0x000b0;
+
+	/*  ip30_5:  */
+	uint64_t                reg_0x00000;
+};
+
+
+DEVICE_TICK(sgi_ip30)
+{
+	struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
+
+	d->reg_0x20000 += 1000;
+
+	if (d->imask0 & ((int64_t)1<<50)) {
+		/*  TODO: Only interrupt if reg 0x20000 (the counter)
+			has passed the compare (0x30000).  */
+fatal("IP30 legacy interrupt rewrite: TODO\n");
+abort();
+//		cpu_interrupt(cpu, 8+1 + 50);
+	}
+}
+
+
+DEVICE_ACCESS(sgi_ip30)
+{
+	struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case 0x20:
+		/*  Memory bank configuration:  */
+		odata = 0x80010000ULL;
+		break;
+
+	case 0x10000:	/*  Interrupt mask register 0:  */
+		if (writeflag == MEM_WRITE) {
+			d->imask0 = idata;
+		} else {
+			odata = d->imask0;
+		}
+		break;
+
+	case 0x10018:
+		/*
+		 *  If this is not implemented, the IP30 PROM complains during
+		 *  bootup:
+		 *
+		 *           *FAILED*
+		 *    Address: 0xffffffffaff10018, Expected:
+		 *        0x0000000000000001, Received: 0x0000000000000000
+		 */
+		if (writeflag == MEM_WRITE) {
+			d->reg_0x10018 = idata;
+		} else {
+			odata = d->reg_0x10018;
+		}
+		break;
+
+	case 0x10020:	/*  Set ISR, according to Linux/IP30  */
+		d->isr = idata;
+		/*  Recalculate CPU interrupt assertions:  */
+fatal("IP30 legacy interrupt rewrite: TODO\n");
+abort();
+//		cpu_interrupt(cpu, 8);
+		break;
+
+	case 0x10028:	/*  Clear ISR, according to Linux/IP30  */
+		d->isr &= ~idata;
+		/*  Recalculate CPU interrupt assertions:  */
+fatal("IP30 legacy interrupt rewrite: TODO\n");
+abort();
+//		cpu_interrupt(cpu, 8);
+		break;
+
+	case 0x10030:	/*  Interrupt Status Register  */
+		if (writeflag == MEM_WRITE) {
+			/*  Clear-on-write  (TODO: is this correct?)  */
+			d->isr &= ~idata;
+			/*  Recalculate CPU interrupt assertions:  */
+fatal("IP30 legacy interrupt rewrite: TODO\n");
+abort();
+//			cpu_interrupt(cpu, 8);
+		} else {
+			odata = d->isr;
+		}
+		break;
+
+	case 0x20000:
+		/*  A counter  */
+		if (writeflag == MEM_WRITE) {
+			d->reg_0x20000 = idata;
+		} else {
+			odata = d->reg_0x20000;
+		}
+		break;
+
+	case 0x30000:
+		if (writeflag == MEM_WRITE) {
+			d->reg_0x30000 = idata;
+		} else {
+			odata = d->reg_0x30000;
+		}
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip30: unimplemented write to address "
+			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
+			    (int)idata);
+		} else {
+			debug("[ sgi_ip30: unimplemented read from address"
+			    " 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(sgi_ip30_2)
+{
+	struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	/*  0x114 + 0x40 * (wid - 8): 0x80000000 for "alive",
+	    according to Linux/IP30  */
+
+	case 0x114 + 0x40 * (12 - 8):
+		fatal("[ IP30: asdvasdvnb ]\n");
+		odata = 0x80000000;
+		break;
+
+	case 0x0029c:
+		/*
+		 *  If this is not implemented, the IP30 PROM complains during
+		 *  bootup:
+		 *
+		 *           *FAILED*
+		 *    Address: 0xffffffffb000029c, Expected:
+		 *	0x0000000000000001, Received: 0x0000000000000000
+		 */
+		if (writeflag == MEM_WRITE) {
+			d->reg_0x0029c = idata;
+		} else {
+			odata = d->reg_0x0029c;
+		}
+		break;
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip30_2: unimplemented write to "
+			    "address 0x%x, data=0x%02x ]\n",
+			    (int)relative_addr, (int)idata);
+		} else {
+			debug("[ sgi_ip30_2: unimplemented read from address "
+			    "0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(sgi_ip30_3)
+{
+	struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case 0xb4:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip30_3: unimplemented write to "
+			    "address 0x%x, data=0x%02x ]\n",
+			    (int)relative_addr, (int)idata);
+		} else {
+			odata = 2;	/*  should be 2, or Irix loops  */
+		}
+		break;
+
+	case 0x00104:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip30_3: unimplemented write to address "
+			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
+			    (int)idata);
+		} else {
+			odata = 64;	/*  should be 64, or the PROM
+					    complains  */
+		}
+		break;
+
+	case 0x00284:
+		/*
+		 *  If this is not implemented, the IP30 PROM complains during
+		 *  bootup:
+		 *
+		 *           *FAILED*
+		 *    Address: 0xffffffffbf000284, Expected:
+		 *	   0x0000000000000001, Received: 0x0000000000000000
+		 */
+		if (writeflag == MEM_WRITE) {
+			d->reg_0x00284 = idata;
+		} else {
+			odata = d->reg_0x00284;
+		}
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip30_3: unimplemented write to address "
+			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
+			    (int)idata);
+		} else {
+			debug("[ sgi_ip30_3: unimplemented read from "
+			    "address 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(sgi_ip30_4)
+{
+	struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case 0x000b0:
+		/*
+		 *  If this is not implemented, the IP30 PROM complains during
+		 *  bootup:
+		 *
+		 *           *FAILED*
+		 *    Address: 0xffffffffbf6000b0, Expected:
+		 *        0x0000000000000001, Received: 0x0000000000000000
+		 */
+		if (writeflag == MEM_WRITE) {
+			d->reg_0x000b0 = idata;
+		} else {
+			odata = d->reg_0x000b0;
+		}
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip30_4: unimplemented write to address"
+			    " 0x%x, data=0x%02x ]\n",
+			    (int)relative_addr, (int)idata);
+		} else {
+			debug("[ sgi_ip30_4: unimplemented read from address"
+			    " 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(sgi_ip30_5)
+{
+	struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case 0x00000:
+		if (writeflag == MEM_WRITE) {
+			d->reg_0x00000 = idata;
+		} else {
+			odata = d->reg_0x00000;
+		}
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sgi_ip30_5: unimplemented write to address "
+			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
+			    (int)idata);
+		} else {
+			debug("[ sgi_ip30_5: unimplemented read from address "
+			    "0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(sgi_ip30)
+{
+	struct sgi_ip30_data *d;
+
+	CHECK_ALLOCATION(d = (struct sgi_ip30_data *) malloc(sizeof(struct sgi_ip30_data)));
+	memset(d, 0, sizeof(struct sgi_ip30_data));
+
+	memory_device_register(devinit->machine->memory, "sgi_ip30_1",
+	    devinit->addr, DEV_SGI_IP30_LENGTH, dev_sgi_ip30_access, (void *)d,
+	    DM_DEFAULT, NULL);
+	memory_device_register(devinit->machine->memory, "sgi_ip30_2", 
+	    0x10000000, 0x10000, dev_sgi_ip30_2_access, (void *)d, DM_DEFAULT,
+	    NULL);
+	memory_device_register(devinit->machine->memory, "sgi_ip30_3",
+	    0x1f000000, 0x10000, dev_sgi_ip30_3_access, (void *)d, DM_DEFAULT,
+	    NULL);
+	memory_device_register(devinit->machine->memory, "sgi_ip30_4",
+	    0x1f600000, 0x10000, dev_sgi_ip30_4_access, (void *)d, DM_DEFAULT,
+	    NULL);
+	memory_device_register(devinit->machine->memory, "sgi_ip30_5",
+	    0x1f6c0000, 0x10000, dev_sgi_ip30_5_access, (void *)d, DM_DEFAULT,
+	    NULL);
+
+	machine_add_tickfunction(devinit->machine,
+	    dev_sgi_ip30_tick, d, 16);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_ip30.cc gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip30.cc
--- gxemul-0.6.2/src/devices/dev_sgi_ip30.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip30.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,407 +0,0 @@
-/*
- *  Copyright (C) 2004-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: SGI IP30 ("Octane") stuff
- *
- *  NOTE/TODO: This is just comprised of hardcoded guesses so far. (Ugly.)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define	DEV_SGI_IP30_LENGTH		0x80000
-
-struct sgi_ip30_data {
-	/*  ip30:  */
-	uint64_t                imask0;         /*  0x10000  */
-	uint64_t                reg_0x10018;
-	uint64_t                isr;            /*  0x10030  */
-	uint64_t                reg_0x20000;
-	uint64_t                reg_0x30000;
-
-	/*  ip30_2:  */
-	uint64_t                reg_0x0029c;
-
-	/*  ip30_3:  */
-	uint64_t                reg_0x00284;
-
-	/*  ip30_4:  */
-	uint64_t                reg_0x000b0;
-
-	/*  ip30_5:  */
-	uint64_t                reg_0x00000;
-};
-
-
-DEVICE_TICK(sgi_ip30)
-{
-	struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
-
-	d->reg_0x20000 += 1000;
-
-	if (d->imask0 & ((int64_t)1<<50)) {
-		/*  TODO: Only interrupt if reg 0x20000 (the counter)
-			has passed the compare (0x30000).  */
-fatal("IP30 legacy interrupt rewrite: TODO\n");
-abort();
-//		cpu_interrupt(cpu, 8+1 + 50);
-	}
-}
-
-
-DEVICE_ACCESS(sgi_ip30)
-{
-	struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case 0x20:
-		/*  Memory bank configuration:  */
-		odata = 0x80010000ULL;
-		break;
-
-	case 0x10000:	/*  Interrupt mask register 0:  */
-		if (writeflag == MEM_WRITE) {
-			d->imask0 = idata;
-		} else {
-			odata = d->imask0;
-		}
-		break;
-
-	case 0x10018:
-		/*
-		 *  If this is not implemented, the IP30 PROM complains during
-		 *  bootup:
-		 *
-		 *           *FAILED*
-		 *    Address: 0xffffffffaff10018, Expected:
-		 *        0x0000000000000001, Received: 0x0000000000000000
-		 */
-		if (writeflag == MEM_WRITE) {
-			d->reg_0x10018 = idata;
-		} else {
-			odata = d->reg_0x10018;
-		}
-		break;
-
-	case 0x10020:	/*  Set ISR, according to Linux/IP30  */
-		d->isr = idata;
-		/*  Recalculate CPU interrupt assertions:  */
-fatal("IP30 legacy interrupt rewrite: TODO\n");
-abort();
-//		cpu_interrupt(cpu, 8);
-		break;
-
-	case 0x10028:	/*  Clear ISR, according to Linux/IP30  */
-		d->isr &= ~idata;
-		/*  Recalculate CPU interrupt assertions:  */
-fatal("IP30 legacy interrupt rewrite: TODO\n");
-abort();
-//		cpu_interrupt(cpu, 8);
-		break;
-
-	case 0x10030:	/*  Interrupt Status Register  */
-		if (writeflag == MEM_WRITE) {
-			/*  Clear-on-write  (TODO: is this correct?)  */
-			d->isr &= ~idata;
-			/*  Recalculate CPU interrupt assertions:  */
-fatal("IP30 legacy interrupt rewrite: TODO\n");
-abort();
-//			cpu_interrupt(cpu, 8);
-		} else {
-			odata = d->isr;
-		}
-		break;
-
-	case 0x20000:
-		/*  A counter  */
-		if (writeflag == MEM_WRITE) {
-			d->reg_0x20000 = idata;
-		} else {
-			odata = d->reg_0x20000;
-		}
-		break;
-
-	case 0x30000:
-		if (writeflag == MEM_WRITE) {
-			d->reg_0x30000 = idata;
-		} else {
-			odata = d->reg_0x30000;
-		}
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip30: unimplemented write to address "
-			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
-			    (int)idata);
-		} else {
-			debug("[ sgi_ip30: unimplemented read from address"
-			    " 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(sgi_ip30_2)
-{
-	struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	/*  0x114 + 0x40 * (wid - 8): 0x80000000 for "alive",
-	    according to Linux/IP30  */
-
-	case 0x114 + 0x40 * (12 - 8):
-		fatal("[ IP30: asdvasdvnb ]\n");
-		odata = 0x80000000;
-		break;
-
-	case 0x0029c:
-		/*
-		 *  If this is not implemented, the IP30 PROM complains during
-		 *  bootup:
-		 *
-		 *           *FAILED*
-		 *    Address: 0xffffffffb000029c, Expected:
-		 *	0x0000000000000001, Received: 0x0000000000000000
-		 */
-		if (writeflag == MEM_WRITE) {
-			d->reg_0x0029c = idata;
-		} else {
-			odata = d->reg_0x0029c;
-		}
-		break;
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip30_2: unimplemented write to "
-			    "address 0x%x, data=0x%02x ]\n",
-			    (int)relative_addr, (int)idata);
-		} else {
-			debug("[ sgi_ip30_2: unimplemented read from address "
-			    "0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(sgi_ip30_3)
-{
-	struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case 0xb4:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip30_3: unimplemented write to "
-			    "address 0x%x, data=0x%02x ]\n",
-			    (int)relative_addr, (int)idata);
-		} else {
-			odata = 2;	/*  should be 2, or Irix loops  */
-		}
-		break;
-
-	case 0x00104:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip30_3: unimplemented write to address "
-			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
-			    (int)idata);
-		} else {
-			odata = 64;	/*  should be 64, or the PROM
-					    complains  */
-		}
-		break;
-
-	case 0x00284:
-		/*
-		 *  If this is not implemented, the IP30 PROM complains during
-		 *  bootup:
-		 *
-		 *           *FAILED*
-		 *    Address: 0xffffffffbf000284, Expected:
-		 *	   0x0000000000000001, Received: 0x0000000000000000
-		 */
-		if (writeflag == MEM_WRITE) {
-			d->reg_0x00284 = idata;
-		} else {
-			odata = d->reg_0x00284;
-		}
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip30_3: unimplemented write to address "
-			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
-			    (int)idata);
-		} else {
-			debug("[ sgi_ip30_3: unimplemented read from "
-			    "address 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(sgi_ip30_4)
-{
-	struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case 0x000b0:
-		/*
-		 *  If this is not implemented, the IP30 PROM complains during
-		 *  bootup:
-		 *
-		 *           *FAILED*
-		 *    Address: 0xffffffffbf6000b0, Expected:
-		 *        0x0000000000000001, Received: 0x0000000000000000
-		 */
-		if (writeflag == MEM_WRITE) {
-			d->reg_0x000b0 = idata;
-		} else {
-			odata = d->reg_0x000b0;
-		}
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip30_4: unimplemented write to address"
-			    " 0x%x, data=0x%02x ]\n",
-			    (int)relative_addr, (int)idata);
-		} else {
-			debug("[ sgi_ip30_4: unimplemented read from address"
-			    " 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(sgi_ip30_5)
-{
-	struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case 0x00000:
-		if (writeflag == MEM_WRITE) {
-			d->reg_0x00000 = idata;
-		} else {
-			odata = d->reg_0x00000;
-		}
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sgi_ip30_5: unimplemented write to address "
-			    "0x%x, data=0x%02x ]\n", (int)relative_addr,
-			    (int)idata);
-		} else {
-			debug("[ sgi_ip30_5: unimplemented read from address "
-			    "0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(sgi_ip30)
-{
-	struct sgi_ip30_data *d;
-
-	CHECK_ALLOCATION(d = (struct sgi_ip30_data *) malloc(sizeof(struct sgi_ip30_data)));
-	memset(d, 0, sizeof(struct sgi_ip30_data));
-
-	memory_device_register(devinit->machine->memory, "sgi_ip30_1",
-	    devinit->addr, DEV_SGI_IP30_LENGTH, dev_sgi_ip30_access, (void *)d,
-	    DM_DEFAULT, NULL);
-	memory_device_register(devinit->machine->memory, "sgi_ip30_2", 
-	    0x10000000, 0x10000, dev_sgi_ip30_2_access, (void *)d, DM_DEFAULT,
-	    NULL);
-	memory_device_register(devinit->machine->memory, "sgi_ip30_3",
-	    0x1f000000, 0x10000, dev_sgi_ip30_3_access, (void *)d, DM_DEFAULT,
-	    NULL);
-	memory_device_register(devinit->machine->memory, "sgi_ip30_4",
-	    0x1f600000, 0x10000, dev_sgi_ip30_4_access, (void *)d, DM_DEFAULT,
-	    NULL);
-	memory_device_register(devinit->machine->memory, "sgi_ip30_5",
-	    0x1f6c0000, 0x10000, dev_sgi_ip30_5_access, (void *)d, DM_DEFAULT,
-	    NULL);
-
-	machine_add_tickfunction(devinit->machine,
-	    dev_sgi_ip30_tick, d, 16);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_ip32.c gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip32.c
--- gxemul-0.6.2/src/devices/dev_sgi_ip32.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip32.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,871 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: SGI IP32 stuff (CRIME, MACE, MACEPCI, ust)
+ *
+ *	o)  CRIME (interrupt controller)
+ *	o)  MACE (Multimedia, Audio and Communications Engine)
+ *	o)  MACE PCI bus
+ *	o)  ust (unknown device)
+ *
+ *  TODO:
+ *	o)  VICE (Video and Image Compression Engine)
+ *		(perhaps best to place in the Graphics Back End?)
+ *
+ *  The GBE graphics (Graphics Back End) is in dev_sgi_gbe.cc.
+ *
+ *  Some info here: http://bukosek.si/hardware/collection/sgi-o2.html
+ *  but mostly based on how NetBSD, OpenBSD, and Linux use the hardware.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+
+#include "bus_pci.h"
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "net.h"
+
+#include "thirdparty/crimereg.h"
+#include "thirdparty/sgi_macereg.h"
+
+// #define debug fatal
+
+// #define MACEPCI_DEBUG
+
+#define	CRIME_TICKSHIFT			14
+
+
+struct macepci_data {
+	struct pci_data *pci_data;
+};
+
+#define	DEV_CRIME_LENGTH		0x280
+struct crime_data {
+	uint64_t		reg[DEV_CRIME_LENGTH / sizeof(uint64_t)];
+
+	uint64_t		last_microseconds;
+
+	struct interrupt	irq;
+	int			prev_asserted;
+
+	int			use_fb;
+};
+
+
+void mips_pc_to_pointers(struct cpu *);
+void mips32_pc_to_pointers(struct cpu *);
+
+
+void crime_interrupt_reassert(struct crime_data *d)
+{
+	uint64_t status =
+		d->reg[CRIME_SOFTINT / sizeof(uint64_t)] |
+		d->reg[CRIME_HARDINT / sizeof(uint64_t)];
+
+	d->reg[CRIME_INTSTAT / sizeof(uint64_t)] = status;
+
+	status &= d->reg[CRIME_INTMASK / sizeof(uint64_t)];
+
+#if 0
+	printf("CRIME SOFTINT=0x%08x HARDINT=0x%08x => 0x%08x, INTMASK=0x%08x\n",
+		(uint32_t)d->reg[CRIME_SOFTINT / sizeof(uint64_t)],
+		(uint32_t)d->reg[CRIME_HARDINT / sizeof(uint64_t)],
+		(uint32_t)status,
+		(uint32_t)d->reg[CRIME_INTMASK / sizeof(uint64_t)]);
+#endif
+	
+	int asserted = !!status;
+
+	if (asserted && !d->prev_asserted)
+		INTERRUPT_ASSERT(d->irq);
+	else if (!asserted && d->prev_asserted)
+		INTERRUPT_DEASSERT(d->irq);
+	
+	d->prev_asserted = asserted;
+}
+
+/*
+ *  crime_interrupt_assert():
+ *  crime_interrupt_deassert():
+ */
+void crime_interrupt_assert(struct interrupt *interrupt)
+{
+	struct crime_data *d = (struct crime_data *) interrupt->extra;
+	d->reg[CRIME_HARDINT / sizeof(uint64_t)] |= interrupt->line;
+	//printf("CRIME asserting 0x%08x\n", interrupt->line);
+	crime_interrupt_reassert(d);
+}
+void crime_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct crime_data *d = (struct crime_data *) interrupt->extra;
+	d->reg[CRIME_HARDINT / sizeof(uint64_t)] &= ~interrupt->line;
+	//printf("CRIME deasserting 0x%08x\n", interrupt->line);
+	crime_interrupt_reassert(d);
+}
+
+
+void crime_update_crime_time(struct crime_data* d)
+{
+	struct timeval tv;
+	
+	gettimeofday(&tv, NULL);
+
+	uint64_t microseconds = tv.tv_sec * 1000000 + tv.tv_usec;
+	if (d->last_microseconds == 0)
+		d->last_microseconds = microseconds;
+
+	int64_t delta = microseconds - d->last_microseconds;
+
+	if (delta < 0) {
+		fatal("[ crime_update_crime_time: host system time went backwards? ]\n");
+		d->last_microseconds = microseconds;
+		delta = 0;
+	}
+
+	// The delta to add is 66 per microsecond.
+	int64_t to_add = delta * 66;
+
+	if (to_add >= 1) {
+		// NetBSD says CRIME_TIME_MASK = 0x0000ffffffffffffULL
+		// but my O2 seems to use only the lower 32 bits as an
+		// _unsigned_ value. (TODO: Double-check this again.)
+		d->reg[CRIME_TIME / sizeof(uint64_t)] =
+			(uint32_t)(d->reg[CRIME_TIME / sizeof(uint64_t)] + to_add);
+
+		d->last_microseconds = microseconds;
+	}
+}
+
+
+/*
+ *  dev_crime_tick():
+ *
+ *  Updates CRIME_TIME (at 66 MHz) and reassert CRIME interrupts.
+ */
+DEVICE_TICK(crime)
+{
+	struct crime_data *d = (struct crime_data *) extra;
+
+	crime_update_crime_time(d);
+	crime_interrupt_reassert(d);
+}
+
+
+DEVICE_ACCESS(crime)
+{
+	/*
+	 *  The CRIME is memory mapped as 0x80 bytes, starting at
+	 *  physical 0x14000000.
+	 *
+	 *  On my real O2:
+	 *
+	 *  0x14000080..0x140000ff is the same as 0x14000000..0x1400007f.
+	 *  0x14000100..0x1400017f is the same as 0x14000000..0x1400007f.
+	 *  0x14000180..0x140001ff is the same as 0x14000000..0x1400007f.
+	 *
+	 *  (I assume that real code will never access the above "mirrors",
+	 *  but it would be trivial to add redirection so that such code
+	 *  would work too.)
+	 *
+	 *  Memory control then starts at 0x14000200.
+	 */
+	struct crime_data *d = (struct crime_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	uint64_t preserved_CRIME_HARDINT = d->reg[CRIME_HARDINT / sizeof(uint64_t)];
+	size_t i;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*
+	 *  Set crime version/revision:
+	 *
+	 *  This might not be the most elegant or correct solution, but it
+	 *  seems that the IP32 PROM likes 0x11 for machines without graphics,
+	 *  and 0xa1 for machines with graphics.
+	 *
+	 *  NetBSD 2.0 complains about "unknown" crime for 0x11, but I guess
+	 *  that's something one has to live with.  (TODO?)
+	 */
+	d->reg[CRIME_REV / sizeof(uint64_t)] = d->use_fb? 0xa1 : 0x11;
+
+	d->reg[CRIME_CONTROL / sizeof(uint64_t)] = CRIME_CONTROL_ENDIANESS;
+
+	d->reg[CRIME_INTSTAT / sizeof(uint64_t)] =
+		(d->reg[CRIME_SOFTINT / sizeof(uint64_t)] |
+		d->reg[CRIME_HARDINT / sizeof(uint64_t)]);
+
+	/*
+	 *  Amount of memory.  Bit 8 of bank control set ==> 128MB instead
+	 *  of 32MB per bank (?)
+	 *
+	 *  According to OpenBSD, "Empty banks are reported as duplicates of
+	 *  bank #0."
+	 */
+	if (cpu->machine->physical_ram_in_mb > 1024) {
+		fatal("[ sgi_crime: SGI O2 can not have more than 1024 MB RAM ]\n");
+		exit(1);
+	}
+
+	int mb_per_bank;
+	if (cpu->machine->physical_ram_in_mb <= 256)
+		mb_per_bank = 32;
+	else
+		mb_per_bank = 128;
+
+	if (cpu->machine->physical_ram_in_mb % mb_per_bank) {
+		fatal("[ sgi_crime: for up to 256 MB RAM, RAM size needs to be divisible "
+			"by 32 MB. for larger RAM sizes (up to 1024 MB), it needs to be "
+			"divisible by 128 MB. ]\n");
+		exit(1);
+	}
+
+	int flag_for_128MB = mb_per_bank == 128 ? 0x100 : 0x000;
+	size_t total_mb = 0;
+	for (int bank = 0; bank < 8; ++bank) {
+		int b = mb_per_bank == 128 ? (bank << 2) : bank;
+		if (total_mb >= cpu->machine->physical_ram_in_mb)
+			d->reg[CRIME_MEM_BANK_CTRL0 / sizeof(uint64_t) + bank] =
+				d->reg[CRIME_MEM_BANK_CTRL0 / sizeof(uint64_t) + 0];
+		else
+			d->reg[CRIME_MEM_BANK_CTRL0 / sizeof(uint64_t) + bank] = flag_for_128MB | b;
+
+		total_mb += mb_per_bank;
+	}
+	
+	if (len == 8) {
+		if (writeflag == MEM_WRITE)
+			d->reg[relative_addr / 8] = idata;
+		else
+			odata = d->reg[relative_addr / 8];
+	} else if (len == 4) {
+		if (writeflag == MEM_WRITE) {
+			if (relative_addr & 4) {
+				d->reg[relative_addr / 8] &= ~0xffffffffULL;
+				d->reg[relative_addr / 8] |= (uint32_t)idata;
+			} else {
+				d->reg[relative_addr / 8] &= 0xffffffffULL;
+				d->reg[relative_addr / 8] |= (uint64_t)(idata << 32ULL);
+			}
+		} else {
+			odata = d->reg[relative_addr / 8];
+			if (relative_addr & 4)
+				odata = (int32_t)odata;
+			else
+				odata = (int32_t)(odata >> 32);
+		}
+	} else {
+		fatal("crime access len = %i!\n", len);
+		exit(1);
+	}
+
+	switch (relative_addr) {
+
+	case CRIME_REV:		/*  0x000  */
+		/*
+		 *  A contender for winning a prize for the worst hack
+		 *  in history:  the IP32 PROM probes the CPU caches during
+		 *  bootup, but they are not really emulated, so it fails.
+		 *  During the probe, the CRIME_REV is read a lot. By
+		 *  "returning" from the probe function, i.e. jumping to ra,
+		 *  when this register is read the second time, the probe
+		 *  can be skipped, and the PROM thus runs further.
+		 *
+		 *  The address where this happens is:
+		 *	0xbfc0517c	PROM v2.3
+		 *	0xbfc051ac	PROM v4.13
+		 *
+		 *  4.18 works too.
+		 *
+		 *  By extrapolating a bit (allowing for variations for other
+		 *  versions of the PROM), let's return if the read of the
+		 *  CRIME_REV register occurs anywhere near 0xbfc051XX.
+		 */
+		if (((uint32_t)cpu->pc & 0xffffff00) == (uint32_t)0xbfc05100) {
+			cpu->pc = cpu->cd.mips.gpr[MIPS_GPR_RA];
+			if (cpu->is_32bit)
+				mips32_pc_to_pointers(cpu);
+			else
+				mips_pc_to_pointers(cpu);
+		}
+		break;
+
+	case CRIME_CONTROL:	/*  0x008  */
+		/*  TODO: 64-bit write to CRIME_CONTROL, but some things
+		    (such as NetBSD 1.6.2) write to 0x00c!  */
+		if (writeflag == MEM_WRITE) {
+			/*
+			 *  0x200 = watchdog timer (according to NetBSD)
+			 *  0x800 = "reboot" used by the IP32 PROM
+			 */
+			if (idata & CRIME_CONTROL_DOG_ENABLE) {
+				idata &= ~CRIME_CONTROL_DOG_ENABLE;
+			}
+			if (idata & CRIME_CONTROL_HARD_RESET) {
+				int j;
+
+				/*  This is used by the IP32 PROM's
+				    "reboot" command:  */
+				for (j=0; j<cpu->machine->ncpus; j++)
+					cpu->machine->cpus[j]->running = 0;
+
+				idata &= ~CRIME_CONTROL_HARD_RESET;
+			}
+
+			idata &= ~CRIME_CONTROL_ENDIANESS;
+
+			if (idata != 0)
+				fatal("[ CRIME_CONTROL: unimplemented "
+				    "control 0x%016llx ]\n", (long long)idata);
+		}
+		break;
+
+	case CRIME_INTSTAT:	/*  0x010, Current interrupt status  */
+	case CRIME_INTMASK:	/*  0x018, Current interrupt mask  */
+		crime_interrupt_reassert(d);
+		break;
+
+	case CRIME_DOG:		/*  0x030  */
+		// No warning.
+		break;
+
+	case CRIME_TIME:	/*  0x038  */
+		crime_update_crime_time(d);
+		break;
+
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ crime: read from 0x%x, len=%i:",
+			    (int)relative_addr, len);
+			for (i=0; i<len; i++)
+				debug(" %02x", data[i]);
+			debug(" ]\n");
+		} else {
+			debug("[ crime: write to 0x%x:", (int)relative_addr);
+			for (i=0; i<len; i++)
+				debug(" %02x", data[i]);
+			debug(" (len=%i) ]\n", len);
+		}
+	}
+
+	d->reg[CRIME_HARDINT / sizeof(uint64_t)] = preserved_CRIME_HARDINT;
+	d->reg[CRIME_INTSTAT / sizeof(uint64_t)] =
+		(d->reg[CRIME_SOFTINT / sizeof(uint64_t)] |
+		d->reg[CRIME_HARDINT / sizeof(uint64_t)]);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_crime_init():
+ */
+void dev_crime_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, char *irq_path, int use_fb)
+{
+	struct crime_data *d;
+	char tmpstr[200];
+	int i;
+
+	CHECK_ALLOCATION(d = (struct crime_data *) malloc(sizeof(struct crime_data)));
+	memset(d, 0, sizeof(struct crime_data));
+
+	d->use_fb = use_fb;
+
+	INTERRUPT_CONNECT(irq_path, d->irq);
+
+	/*  Register 32 crime interrupts (hexadecimal names):  */
+	for (i=0; i<32; i++) {
+		struct interrupt templ;
+		char name[400];
+		snprintf(name, sizeof(name), "%s.crime.0x%x", irq_path, 1 << i);
+		memset(&templ, 0, sizeof(templ));
+                templ.line = 1 << i;
+		templ.name = name;
+		templ.extra = d;
+		templ.interrupt_assert = crime_interrupt_assert;
+		templ.interrupt_deassert = crime_interrupt_deassert;
+		interrupt_handler_register(&templ);
+        }
+
+	memory_device_register(mem, "crime", baseaddr, DEV_CRIME_LENGTH,
+	    dev_crime_access, d, DM_DEFAULT, NULL);
+
+	snprintf(tmpstr, sizeof(tmpstr), "mace addr=0x1f310000 irq=%s.crime",
+	    irq_path);
+	device_add(machine, tmpstr);
+
+	machine_add_tickfunction(machine, dev_crime_tick, d,
+	    CRIME_TICKSHIFT);
+}
+
+
+/****************************************************************************/
+
+
+#define DEV_MACE_LENGTH		0x100
+struct mace_data {
+	unsigned char		reg[DEV_MACE_LENGTH];
+	struct interrupt	irq_periph;
+	struct interrupt	irq_misc;
+	int			prev_assert_periph;
+	int			prev_assert_misc;
+};
+
+
+void mace_interrupt_reassert(struct mace_data *d)
+{
+	uint8_t s4 = d->reg[MACE_ISA_INT_STATUS+4] & d->reg[MACE_ISA_INT_MASK+4];
+	uint8_t s5 = d->reg[MACE_ISA_INT_STATUS+5] & d->reg[MACE_ISA_INT_MASK+5];
+	uint8_t s6 = d->reg[MACE_ISA_INT_STATUS+6] & d->reg[MACE_ISA_INT_MASK+6];
+	uint8_t s7 = d->reg[MACE_ISA_INT_STATUS+7] & d->reg[MACE_ISA_INT_MASK+7];
+
+	int assert_periph = s4 | s5 ? 1 : 0;
+	int assert_misc = s6 | s7 ? 1 : 0;
+
+/*
+printf("status=%02x%02x%02x%02x mask=%02x%02x%02x%02x => periph = %i misc = %i\n",
+d->reg[MACE_ISA_INT_STATUS+4],
+d->reg[MACE_ISA_INT_STATUS+5],
+d->reg[MACE_ISA_INT_STATUS+6],
+d->reg[MACE_ISA_INT_STATUS+7],
+d->reg[MACE_ISA_INT_MASK+4],
+d->reg[MACE_ISA_INT_MASK+5],
+d->reg[MACE_ISA_INT_MASK+6],
+d->reg[MACE_ISA_INT_MASK+7],
+ assert_periph, assert_misc);
+*/
+
+	if (assert_periph != d->prev_assert_periph) {
+		d->prev_assert_periph = assert_periph;
+		if (assert_periph)
+			INTERRUPT_ASSERT(d->irq_periph);
+		else
+			INTERRUPT_DEASSERT(d->irq_periph);
+	}
+
+	if (assert_misc != d->prev_assert_misc) {
+		d->prev_assert_misc = assert_misc;
+		if (assert_misc)
+			INTERRUPT_ASSERT(d->irq_misc);
+		else
+			INTERRUPT_DEASSERT(d->irq_misc);
+	}
+}
+
+
+
+/*
+ *  mace_interrupt_assert():
+ *  mace_interrupt_deassert():
+ */
+void mace_interrupt_assert(struct interrupt *interrupt)
+{
+	struct mace_data *d = (struct mace_data *) interrupt->extra;
+	uint32_t line = 1 << interrupt->line;
+
+	d->reg[MACE_ISA_INT_STATUS + 4] |= ((line >> 24) & 255);
+	d->reg[MACE_ISA_INT_STATUS + 5] |= ((line >> 16) & 255);
+	d->reg[MACE_ISA_INT_STATUS + 6] |= ((line >> 8) & 255);
+	d->reg[MACE_ISA_INT_STATUS + 7] |= (line & 255);
+
+	mace_interrupt_reassert(d);
+}
+void mace_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct mace_data *d = (struct mace_data *) interrupt->extra;
+	uint32_t line = 1 << interrupt->line;
+
+	d->reg[MACE_ISA_INT_STATUS + 4] &= ~((line >> 24) & 255);
+	d->reg[MACE_ISA_INT_STATUS + 5] &= ~((line >> 16) & 255);
+	d->reg[MACE_ISA_INT_STATUS + 6] &= ~((line >> 8) & 255);
+	d->reg[MACE_ISA_INT_STATUS + 7] &= ~(line & 255);
+
+	mace_interrupt_reassert(d);
+}
+
+
+DEVICE_ACCESS(mace)
+{
+	size_t i;
+	struct mace_data *d = (struct mace_data *) extra;
+
+	/*
+	 *  My O2 returns the following when dumping 0xbf310000 and forward:
+	 *
+	 *  +0x00: 0x0000000000000010 0x000000000000001e
+	 *  +0x10: 0x0000000000000000 0x0000000000000000
+	 *
+	 *  and then the following addresses result in the same data as
+	 *  0xbf310000.
+	 */
+	d->reg[MACE_ISA_RINGBASE + 7] = 0x10;
+	d->reg[MACE_ISA_FLASH_NIC_REG + 7] |= MACE_ISA_PWD_CLEAR;
+
+	uint8_t old_mace_isa_flash_nic_reg =
+		d->reg[MACE_ISA_FLASH_NIC_REG + 7];
+
+	if (writeflag == MEM_WRITE)
+		memcpy(&d->reg[relative_addr], data, len);
+	else
+		memcpy(data, &d->reg[relative_addr], len);
+
+	switch (relative_addr & ~7) {
+
+	case MACE_ISA_RINGBASE:
+		break;
+
+	case MACE_ISA_FLASH_NIC_REG:
+		// I think the PROM attempts to read the machine's ethernet
+		// address from a DS2502 EPROM, by writing MACE_ISA_NIC_DEASSERT
+		// to this register in various patterns, and looking at the
+		// resulting MACE_ISA_NIC_DATA (or does it write data as well?)
+		// In any case, onewire is too complicated to implement right
+		// now. TODO.
+		if (writeflag)
+		{
+			/*
+			 *  The NetBSD defines are called "RED" and "GREEN",
+			 *  and are documented like this:
+			 *
+			 *	1=> Illuminate RED LED
+			 *
+			 *  (and similarly for GREEN). But on my O2, it feels
+			 *  like the other way around (i.e. 1 = do NOT illuminate
+			 *  that LED color). Also, having it this way is more
+			 *  compatible with how NetBSD, OpenBSD, and the PROM
+			 *  actually use the LED.
+			 */
+			uint8_t change = (d->reg[MACE_ISA_FLASH_NIC_REG + 7]
+				^ old_mace_isa_flash_nic_reg) &
+				(MACE_ISA_LED_RED | MACE_ISA_LED_GREEN);
+			if (change) {
+				switch (d->reg[MACE_ISA_FLASH_NIC_REG + 7] & (MACE_ISA_LED_RED | MACE_ISA_LED_GREEN)) {
+				case 0:	debugmsg(SUBSYS_DEVICE, "mace", VERBOSITY_INFO, "turning LED WHITE/ORANGE");
+					break;
+				case MACE_ISA_LED_RED:
+					debugmsg(SUBSYS_DEVICE, "mace", VERBOSITY_INFO, "turning LED GREEN");
+					break;
+				case MACE_ISA_LED_GREEN:
+					debugmsg(SUBSYS_DEVICE, "mace", VERBOSITY_INFO, "turning LED RED");
+					break;
+				default:debugmsg(SUBSYS_DEVICE, "mace", VERBOSITY_WARNING, "turning LED OFF");
+					break;
+				}
+			}
+			
+//printf("%02x: MACE_ISA_NIC_DEASSERT = %i, DATA = %i\n",
+	//d->reg[MACE_ISA_FLASH_NIC_REG + 7],
+//d->reg[MACE_ISA_FLASH_NIC_REG + 7] & MACE_ISA_NIC_DEASSERT,
+	//d->reg[MACE_ISA_FLASH_NIC_REG + 7] & MACE_ISA_NIC_DATA);
+		} else {
+//			data[len-1] ^= (random() & MACE_ISA_NIC_DATA);
+//			data[len-1] |= MACE_ISA_NIC_DEASSERT;
+		}
+		break;
+
+	case MACE_ISA_INT_STATUS:	/*  Current interrupt assertions  */
+		/*  don't dump debug info for these  */
+		if (writeflag == MEM_WRITE) {
+			fatal("[ NOTE/TODO: WRITE to mace intr: "
+			    "reladdr=0x%x data=", (int)relative_addr);
+			for (i=0; i<len; i++)
+				fatal(" %02x", data[i]);
+			fatal(" (len=%i) ]\n", len);
+		}
+		break;
+	case MACE_ISA_INT_MASK:		/*  Current interrupt mask  */
+		mace_interrupt_reassert(d);
+		break;
+
+	default:
+		if (writeflag == MEM_READ) {
+			debug("[ mace: read from 0x%x:", (int)relative_addr);
+			for (i=0; i<len; i++)
+				debug(" %02x", data[i]);
+			debug(" (len=%i) ]\n", len);
+		} else {
+			debug("[ mace: write to 0x%x:", (int)relative_addr);
+			for (i=0; i<len; i++)
+				debug(" %02x", data[i]);
+			debug(" (len=%i) ]\n", len);
+		}
+	}
+
+	return 1;
+}
+
+
+DEVINIT(mace)
+{
+	struct mace_data *d;
+	char tmpstr[300];
+	int i;
+
+	CHECK_ALLOCATION(d = (struct mace_data *) malloc(sizeof(struct mace_data)));
+	memset(d, 0, sizeof(struct mace_data));
+
+	snprintf(tmpstr, sizeof(tmpstr), "%s.0x%x",
+	    devinit->interrupt_path, CRIME_INT_PERIPH_SERIAL);
+	INTERRUPT_CONNECT(tmpstr, d->irq_periph);
+
+	snprintf(tmpstr, sizeof(tmpstr), "%s.0x%x",
+	    devinit->interrupt_path, CRIME_INT_PERIPH_MISC);
+	INTERRUPT_CONNECT(tmpstr, d->irq_misc);
+
+	/*
+	 *  For CRIME interrupts PERIPH_SERIAL and PERIPH_MISC,
+	 *  register 32 mace interrupts each.
+	 */
+	for (i=0; i<32; i++) {
+		struct interrupt templ;
+		char name[400];
+		snprintf(name, sizeof(name), "%s.0x%x.mace.%i",
+		    devinit->interrupt_path, CRIME_INT_PERIPH_SERIAL, i);
+		memset(&templ, 0, sizeof(templ));
+                templ.line = i;
+		templ.name = name;
+		templ.extra = d;
+		templ.interrupt_assert = mace_interrupt_assert;
+		templ.interrupt_deassert = mace_interrupt_deassert;
+		interrupt_handler_register(&templ);
+
+		snprintf(name, sizeof(name), "%s.0x%x.mace.%i",
+		    devinit->interrupt_path, CRIME_INT_PERIPH_MISC, i);
+		memset(&templ, 0, sizeof(templ));
+                templ.line = i;
+		templ.name = name;
+		templ.extra = d;
+		templ.interrupt_assert = mace_interrupt_assert;
+		templ.interrupt_deassert = mace_interrupt_deassert;
+		interrupt_handler_register(&templ);
+        }
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_MACE_LENGTH, dev_mace_access, d,
+	    DM_DEFAULT, NULL);
+
+	devinit->return_ptr = d;
+	return 1;
+}
+
+
+/****************************************************************************/
+
+
+DEVICE_ACCESS(macepci)
+{
+	struct macepci_data *d = (struct macepci_data *) extra;
+	uint64_t idata = 0, odata=0;
+	int res = 1, bus, dev, func, pcireg;
+
+	if (len != 4)
+		fatal("[ macepci: unimplemented len %i ]\n", len);
+
+	if (writeflag == MEM_WRITE) {
+		idata = memory_readmax64(cpu, data, len);
+#ifdef MACEPCI_DEBUG
+		fatal("[ macepci: write to address 0x%x, data=0x%02x (len %i) ]\n",
+		    (int)relative_addr, (int)idata, len);
+#endif
+	}
+
+	/*  Read from/write to the macepci:  */
+	switch (relative_addr) {
+
+	case 0x00:	/*  Error address  */
+		if (writeflag == MEM_WRITE) {
+		} else {
+			/*  My real O2 returns 0x4000.  */
+			odata = 0x4000;
+		}
+		break;
+
+	case 0x04:	/*  Error flags  */
+		if (writeflag == MEM_WRITE) {
+		} else {
+			/*  My real O2 returns 0x00100006.  */
+			odata = 0x00100006;
+		}
+		break;
+
+	case 0x08:	/*  TODO: Unknown?  */
+		if (writeflag == MEM_WRITE) {
+		} else {
+			/*  My real O2 returns 0xff000500.  */
+			odata = 0xff000500;
+		}
+		break;
+
+	case 0x0c:	/*  Revision number  */
+		if (writeflag == MEM_WRITE) {
+		} else {
+			/*  My real O2 returns 0x00000001.  */
+			odata = 0x00000001;
+		}
+		break;
+
+	case 0xcf8:	/*  PCI ADDR  */
+		bus_pci_decompose_1(idata, &bus, &dev, &func, &pcireg);
+		bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, pcireg);
+		break;
+
+	case 0xcfc:	/*  PCI DATA  */
+		bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
+		    &odata : &idata, len, writeflag);
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ macepci: unimplemented write to address "
+			    "0x%x, data=0x%02x ]\n",
+			    (int)relative_addr, (int)idata);
+		} else {
+			fatal("[ macepci: unimplemented read from address "
+			    "0x%x ]\n", (int)relative_addr);
+
+			/*  My real O2 returns 0xffffffff for all unimplemented
+				registers.  */
+			odata = 0xffffffff;
+		}
+	}
+
+	if (writeflag == MEM_READ) {
+		memory_writemax64(cpu, data, len, odata);
+#ifdef MACEPCI_DEBUG
+		fatal("[ macepci: read from address 0x%x, data=0x%02x (len %i) ]\n",
+		    (int)relative_addr, (int)odata, len);
+#endif
+	}
+
+	return res;
+}
+
+
+/*
+ *  dev_macepci_init():
+ */
+struct pci_data *dev_macepci_init(struct machine *machine,
+	struct memory *mem, uint64_t baseaddr, char *irq_path)
+{
+	struct macepci_data *d;
+
+	CHECK_ALLOCATION(d = (struct macepci_data *) malloc(sizeof(struct macepci_data)));
+	memset(d, 0, sizeof(struct macepci_data));
+
+	/*  TODO: PCI vs ISA interrupt?  */
+
+	d->pci_data = bus_pci_init(machine,
+	    irq_path,
+	    0,
+	    0,
+	    0,
+	    0,
+	    "TODO: pci irq path",
+	    0x18000003,		/*  ISA portbase  */
+	    0,
+	    irq_path);
+
+	memory_device_register(mem, "macepci", baseaddr, DEV_MACEPCI_LENGTH,
+	    dev_macepci_access, (void *)d, DM_DEFAULT, NULL);
+
+	return d->pci_data;
+}
+
+
+/****************************************************************************/
+
+
+struct sgi_ust_data {
+	uint64_t	reg[DEV_SGI_UST_LENGTH / sizeof(uint64_t)];
+};
+
+
+DEVICE_ACCESS(sgi_ust)
+{
+	struct sgi_ust_data *d = (struct sgi_ust_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int regnr;
+
+	idata = memory_readmax64(cpu, data, len);
+	regnr = relative_addr / sizeof(uint64_t);
+
+	/*  Treat all registers as read/write, by default.  */
+	if (writeflag == MEM_WRITE)
+		d->reg[regnr] = idata;
+	else
+		odata = d->reg[regnr];
+
+	switch (relative_addr) {
+	case 0:
+		d->reg[regnr] += 0x2710;	// HUH?
+		break;
+	default:
+		if (writeflag == MEM_WRITE)
+			debug("[ sgi_ust: unimplemented write to "
+			    "address 0x%llx, data=0x%016llx ]\n",
+			    (long long)relative_addr, (long long)idata);
+		else
+			debug("[ sgi_ust: unimplemented read from address"
+			    " 0x%llx ]\n", (long long)relative_addr);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_sgi_ust_init():
+ */
+void dev_sgi_ust_init(struct memory *mem, uint64_t baseaddr)
+{
+	struct sgi_ust_data *d;
+
+	CHECK_ALLOCATION(d = (struct sgi_ust_data *) malloc(sizeof(struct sgi_ust_data)));
+	memset(d, 0, sizeof(struct sgi_ust_data));
+
+	memory_device_register(mem, "sgi_ust", baseaddr,
+	    DEV_SGI_UST_LENGTH, dev_sgi_ust_access, (void *)d,
+	    DM_DEFAULT, NULL);
+}
+
+
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_ip32.cc gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip32.cc
--- gxemul-0.6.2/src/devices/dev_sgi_ip32.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_ip32.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,872 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: SGI IP32 stuff (CRIME, MACE, MACEPCI, ust)
- *
- *	o)  CRIME (interrupt controller)
- *	o)  MACE (Multimedia, Audio and Communications Engine)
- *	o)  MACE PCI bus
- *	o)  ust (unknown device)
- *
- *  TODO:
- *	o)  VICE (Video and Image Compression Engine)
- *		(perhaps best to place in the Graphics Back End?)
- *
- *  The GBE graphics (Graphics Back End) is in dev_sgi_gbe.cc.
- *
- *  Some info here: http://bukosek.si/hardware/collection/sgi-o2.html
- *  but mostly based on how NetBSD, OpenBSD, and Linux use the hardware.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/time.h>
-
-#include "bus_pci.h"
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "net.h"
-
-#include "thirdparty/crimereg.h"
-#include "thirdparty/sgi_macereg.h"
-
-// #define debug fatal
-
-// #define MACEPCI_DEBUG
-
-#define	CRIME_TICKSHIFT			14
-
-
-struct macepci_data {
-	struct pci_data *pci_data;
-};
-
-#define	DEV_CRIME_LENGTH		0x280
-struct crime_data {
-	uint64_t		reg[DEV_CRIME_LENGTH / sizeof(uint64_t)];
-
-	uint64_t		last_microseconds;
-
-	struct interrupt	irq;
-	int			prev_asserted;
-
-	int			use_fb;
-};
-
-
-void mips_pc_to_pointers(struct cpu *);
-void mips32_pc_to_pointers(struct cpu *);
-
-
-void crime_interrupt_reassert(struct crime_data *d)
-{
-	uint64_t status =
-		d->reg[CRIME_SOFTINT / sizeof(uint64_t)] |
-		d->reg[CRIME_HARDINT / sizeof(uint64_t)];
-
-	d->reg[CRIME_INTSTAT / sizeof(uint64_t)] = status;
-
-	status &= d->reg[CRIME_INTMASK / sizeof(uint64_t)];
-
-#if 0
-	printf("CRIME SOFTINT=0x%08x HARDINT=0x%08x => 0x%08x, INTMASK=0x%08x\n",
-		(uint32_t)d->reg[CRIME_SOFTINT / sizeof(uint64_t)],
-		(uint32_t)d->reg[CRIME_HARDINT / sizeof(uint64_t)],
-		(uint32_t)status,
-		(uint32_t)d->reg[CRIME_INTMASK / sizeof(uint64_t)]);
-#endif
-	
-	int asserted = !!status;
-
-	if (asserted && !d->prev_asserted)
-		INTERRUPT_ASSERT(d->irq);
-	else if (!asserted && d->prev_asserted)
-		INTERRUPT_DEASSERT(d->irq);
-	
-	d->prev_asserted = asserted;
-}
-
-/*
- *  crime_interrupt_assert():
- *  crime_interrupt_deassert():
- */
-void crime_interrupt_assert(struct interrupt *interrupt)
-{
-	struct crime_data *d = (struct crime_data *) interrupt->extra;
-	d->reg[CRIME_HARDINT / sizeof(uint64_t)] |= interrupt->line;
-	//printf("CRIME asserting 0x%08x\n", interrupt->line);
-	crime_interrupt_reassert(d);
-}
-void crime_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct crime_data *d = (struct crime_data *) interrupt->extra;
-	d->reg[CRIME_HARDINT / sizeof(uint64_t)] &= ~interrupt->line;
-	//printf("CRIME deasserting 0x%08x\n", interrupt->line);
-	crime_interrupt_reassert(d);
-}
-
-
-void crime_update_crime_time(struct crime_data* d)
-{
-	struct timeval tv;
-	
-	gettimeofday(&tv, NULL);
-
-	uint64_t microseconds = tv.tv_sec * 1000000 + tv.tv_usec;
-	if (d->last_microseconds == 0)
-		d->last_microseconds = microseconds;
-
-	int64_t delta = microseconds - d->last_microseconds;
-
-	if (delta < 0) {
-		fatal("[ crime_update_crime_time: host system time went backwards? ]\n");
-		d->last_microseconds = microseconds;
-		delta = 0;
-	}
-
-	// The delta to add is 66 per microsecond.
-	int64_t to_add = delta * 66;
-
-	if (to_add >= 1) {
-		// NetBSD says CRIME_TIME_MASK = 0x0000ffffffffffffULL
-		// but my O2 seems to use only the lower 32 bits as an
-		// _unsigned_ value. (TODO: Double-check this again.)
-		d->reg[CRIME_TIME / sizeof(uint64_t)] =
-			(uint32_t)(d->reg[CRIME_TIME / sizeof(uint64_t)] + to_add);
-
-		d->last_microseconds = microseconds;
-	}
-}
-
-
-/*
- *  dev_crime_tick():
- *
- *  Updates CRIME_TIME (at 66 MHz) and reassert CRIME interrupts.
- */
-DEVICE_TICK(crime)
-{
-	struct crime_data *d = (struct crime_data *) extra;
-
-	crime_update_crime_time(d);
-	crime_interrupt_reassert(d);
-}
-
-
-DEVICE_ACCESS(crime)
-{
-	/*
-	 *  The CRIME is memory mapped as 0x80 bytes, starting at
-	 *  physical 0x14000000.
-	 *
-	 *  On my real O2:
-	 *
-	 *  0x14000080..0x140000ff is the same as 0x14000000..0x1400007f.
-	 *  0x14000100..0x1400017f is the same as 0x14000000..0x1400007f.
-	 *  0x14000180..0x140001ff is the same as 0x14000000..0x1400007f.
-	 *
-	 *  (I assume that real code will never access the above "mirrors",
-	 *  but it would be trivial to add redirection so that such code
-	 *  would work too.)
-	 *
-	 *  Memory control then starts at 0x14000200.
-	 */
-	struct crime_data *d = (struct crime_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	uint64_t preserved_CRIME_HARDINT = d->reg[CRIME_HARDINT / sizeof(uint64_t)];
-	size_t i;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*
-	 *  Set crime version/revision:
-	 *
-	 *  This might not be the most elegant or correct solution, but it
-	 *  seems that the IP32 PROM likes 0x11 for machines without graphics,
-	 *  and 0xa1 for machines with graphics.
-	 *
-	 *  NetBSD 2.0 complains about "unknown" crime for 0x11, but I guess
-	 *  that's something one has to live with.  (TODO?)
-	 */
-	d->reg[CRIME_REV / sizeof(uint64_t)] = d->use_fb? 0xa1 : 0x11;
-
-	d->reg[CRIME_CONTROL / sizeof(uint64_t)] = CRIME_CONTROL_ENDIANESS;
-
-	d->reg[CRIME_INTSTAT / sizeof(uint64_t)] =
-		(d->reg[CRIME_SOFTINT / sizeof(uint64_t)] |
-		d->reg[CRIME_HARDINT / sizeof(uint64_t)]);
-
-	/*
-	 *  Amount of memory.  Bit 8 of bank control set ==> 128MB instead
-	 *  of 32MB per bank (?)
-	 *
-	 *  According to OpenBSD, "Empty banks are reported as duplicates of
-	 *  bank #0."
-	 */
-	if (cpu->machine->physical_ram_in_mb > 1024) {
-		fatal("[ sgi_crime: SGI O2 can not have more than 1024 MB RAM ]\n");
-		exit(1);
-	}
-
-	int mb_per_bank;
-	if (cpu->machine->physical_ram_in_mb <= 256)
-		mb_per_bank = 32;
-	else
-		mb_per_bank = 128;
-
-	if (cpu->machine->physical_ram_in_mb % mb_per_bank) {
-		fatal("[ sgi_crime: for up to 256 MB RAM, RAM size needs to be divisible "
-			"by 32 MB. for larger RAM sizes (up to 1024 MB), it needs to be "
-			"divisible by 128 MB. ]\n");
-		exit(1);
-	}
-
-	int flag_for_128MB = mb_per_bank == 128 ? 0x100 : 0x000;
-	int total_mb = 0;
-	for (int bank = 0; bank < 8; ++bank) {
-		int b = mb_per_bank == 128 ? (bank << 2) : bank;
-		if (total_mb >= cpu->machine->physical_ram_in_mb)
-			d->reg[CRIME_MEM_BANK_CTRL0 / sizeof(uint64_t) + bank] =
-				d->reg[CRIME_MEM_BANK_CTRL0 / sizeof(uint64_t) + 0];
-		else
-			d->reg[CRIME_MEM_BANK_CTRL0 / sizeof(uint64_t) + bank] = flag_for_128MB | b;
-
-		total_mb += mb_per_bank;
-	}
-	
-	if (len == 8) {
-		if (writeflag == MEM_WRITE)
-			d->reg[relative_addr / 8] = idata;
-		else
-			odata = d->reg[relative_addr / 8];
-	} else if (len == 4) {
-		if (writeflag == MEM_WRITE) {
-			if (relative_addr & 4) {
-				d->reg[relative_addr / 8] &= ~0xffffffffULL;
-				d->reg[relative_addr / 8] |= (uint32_t)idata;
-			} else {
-				d->reg[relative_addr / 8] &= 0xffffffffULL;
-				d->reg[relative_addr / 8] |= (uint64_t)(idata << 32ULL);
-			}
-		} else {
-			odata = d->reg[relative_addr / 8];
-			if (relative_addr & 4)
-				odata = (int32_t)odata;
-			else
-				odata = (int32_t)(odata >> 32);
-		}
-	} else {
-		fatal("crime access len = %i!\n", len);
-		exit(1);
-	}
-
-	switch (relative_addr) {
-
-	case CRIME_REV:		/*  0x000  */
-		/*
-		 *  A contender for winning a prize for the worst hack
-		 *  in history:  the IP32 PROM probes the CPU caches during
-		 *  bootup, but they are not really emulated, so it fails.
-		 *  During the probe, the CRIME_REV is read a lot. By
-		 *  "returning" from the probe function, i.e. jumping to ra,
-		 *  when this register is read the second time, the probe
-		 *  can be skipped, and the PROM thus runs further.
-		 *
-		 *  The address where this happens is:
-		 *	0xbfc0517c	PROM v2.3
-		 *	0xbfc051ac	PROM v4.13
-		 *
-		 *  4.18 works too.
-		 *
-		 *  By extrapolating a bit (allowing for variations for other
-		 *  versions of the PROM), let's return if the read of the
-		 *  CRIME_REV register occurs anywhere near 0xbfc051XX.
-		 */
-		if (((uint32_t)cpu->pc & 0xffffff00) == (uint32_t)0xbfc05100) {
-			cpu->pc = cpu->cd.mips.gpr[MIPS_GPR_RA];
-			if (cpu->is_32bit)
-				mips32_pc_to_pointers(cpu);
-			else
-				mips_pc_to_pointers(cpu);
-		}
-		break;
-
-	case CRIME_CONTROL:	/*  0x008  */
-		/*  TODO: 64-bit write to CRIME_CONTROL, but some things
-		    (such as NetBSD 1.6.2) write to 0x00c!  */
-		if (writeflag == MEM_WRITE) {
-			/*
-			 *  0x200 = watchdog timer (according to NetBSD)
-			 *  0x800 = "reboot" used by the IP32 PROM
-			 */
-			if (idata & CRIME_CONTROL_DOG_ENABLE) {
-				idata &= ~CRIME_CONTROL_DOG_ENABLE;
-			}
-			if (idata & CRIME_CONTROL_HARD_RESET) {
-				int j;
-
-				/*  This is used by the IP32 PROM's
-				    "reboot" command:  */
-				for (j=0; j<cpu->machine->ncpus; j++)
-					cpu->machine->cpus[j]->running = 0;
-				cpu->machine->
-				    exit_without_entering_debugger = 1;
-				idata &= ~CRIME_CONTROL_HARD_RESET;
-			}
-
-			idata &= ~CRIME_CONTROL_ENDIANESS;
-
-			if (idata != 0)
-				fatal("[ CRIME_CONTROL: unimplemented "
-				    "control 0x%016llx ]\n", (long long)idata);
-		}
-		break;
-
-	case CRIME_INTSTAT:	/*  0x010, Current interrupt status  */
-	case CRIME_INTMASK:	/*  0x018, Current interrupt mask  */
-		crime_interrupt_reassert(d);
-		break;
-
-	case CRIME_DOG:		/*  0x030  */
-		// No warning.
-		break;
-
-	case CRIME_TIME:	/*  0x038  */
-		crime_update_crime_time(d);
-		break;
-
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ crime: read from 0x%x, len=%i:",
-			    (int)relative_addr, len);
-			for (i=0; i<len; i++)
-				debug(" %02x", data[i]);
-			debug(" ]\n");
-		} else {
-			debug("[ crime: write to 0x%x:", (int)relative_addr);
-			for (i=0; i<len; i++)
-				debug(" %02x", data[i]);
-			debug(" (len=%i) ]\n", len);
-		}
-	}
-
-	d->reg[CRIME_HARDINT / sizeof(uint64_t)] = preserved_CRIME_HARDINT;
-	d->reg[CRIME_INTSTAT / sizeof(uint64_t)] =
-		(d->reg[CRIME_SOFTINT / sizeof(uint64_t)] |
-		d->reg[CRIME_HARDINT / sizeof(uint64_t)]);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_crime_init():
- */
-void dev_crime_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, char *irq_path, int use_fb)
-{
-	struct crime_data *d;
-	char tmpstr[200];
-	int i;
-
-	CHECK_ALLOCATION(d = (struct crime_data *) malloc(sizeof(struct crime_data)));
-	memset(d, 0, sizeof(struct crime_data));
-
-	d->use_fb = use_fb;
-
-	INTERRUPT_CONNECT(irq_path, d->irq);
-
-	/*  Register 32 crime interrupts (hexadecimal names):  */
-	for (i=0; i<32; i++) {
-		struct interrupt templ;
-		char name[400];
-		snprintf(name, sizeof(name), "%s.crime.0x%x", irq_path, 1 << i);
-		memset(&templ, 0, sizeof(templ));
-                templ.line = 1 << i;
-		templ.name = name;
-		templ.extra = d;
-		templ.interrupt_assert = crime_interrupt_assert;
-		templ.interrupt_deassert = crime_interrupt_deassert;
-		interrupt_handler_register(&templ);
-        }
-
-	memory_device_register(mem, "crime", baseaddr, DEV_CRIME_LENGTH,
-	    dev_crime_access, d, DM_DEFAULT, NULL);
-
-	snprintf(tmpstr, sizeof(tmpstr), "mace addr=0x1f310000 irq=%s.crime",
-	    irq_path);
-	device_add(machine, tmpstr);
-
-	machine_add_tickfunction(machine, dev_crime_tick, d,
-	    CRIME_TICKSHIFT);
-}
-
-
-/****************************************************************************/
-
-
-#define DEV_MACE_LENGTH		0x100
-struct mace_data {
-	unsigned char		reg[DEV_MACE_LENGTH];
-	struct interrupt	irq_periph;
-	struct interrupt	irq_misc;
-	int			prev_assert_periph;
-	int			prev_assert_misc;
-};
-
-
-void mace_interrupt_reassert(struct mace_data *d)
-{
-	uint8_t s4 = d->reg[MACE_ISA_INT_STATUS+4] & d->reg[MACE_ISA_INT_MASK+4];
-	uint8_t s5 = d->reg[MACE_ISA_INT_STATUS+5] & d->reg[MACE_ISA_INT_MASK+5];
-	uint8_t s6 = d->reg[MACE_ISA_INT_STATUS+6] & d->reg[MACE_ISA_INT_MASK+6];
-	uint8_t s7 = d->reg[MACE_ISA_INT_STATUS+7] & d->reg[MACE_ISA_INT_MASK+7];
-
-	int assert_periph = s4 | s5 ? 1 : 0;
-	int assert_misc = s6 | s7 ? 1 : 0;
-
-/*
-printf("status=%02x%02x%02x%02x mask=%02x%02x%02x%02x => periph = %i misc = %i\n",
-d->reg[MACE_ISA_INT_STATUS+4],
-d->reg[MACE_ISA_INT_STATUS+5],
-d->reg[MACE_ISA_INT_STATUS+6],
-d->reg[MACE_ISA_INT_STATUS+7],
-d->reg[MACE_ISA_INT_MASK+4],
-d->reg[MACE_ISA_INT_MASK+5],
-d->reg[MACE_ISA_INT_MASK+6],
-d->reg[MACE_ISA_INT_MASK+7],
- assert_periph, assert_misc);
-*/
-
-	if (assert_periph != d->prev_assert_periph) {
-		d->prev_assert_periph = assert_periph;
-		if (assert_periph)
-			INTERRUPT_ASSERT(d->irq_periph);
-		else
-			INTERRUPT_DEASSERT(d->irq_periph);
-	}
-
-	if (assert_misc != d->prev_assert_misc) {
-		d->prev_assert_misc = assert_misc;
-		if (assert_misc)
-			INTERRUPT_ASSERT(d->irq_misc);
-		else
-			INTERRUPT_DEASSERT(d->irq_misc);
-	}
-}
-
-
-
-/*
- *  mace_interrupt_assert():
- *  mace_interrupt_deassert():
- */
-void mace_interrupt_assert(struct interrupt *interrupt)
-{
-	struct mace_data *d = (struct mace_data *) interrupt->extra;
-	uint32_t line = 1 << interrupt->line;
-
-	d->reg[MACE_ISA_INT_STATUS + 4] |= ((line >> 24) & 255);
-	d->reg[MACE_ISA_INT_STATUS + 5] |= ((line >> 16) & 255);
-	d->reg[MACE_ISA_INT_STATUS + 6] |= ((line >> 8) & 255);
-	d->reg[MACE_ISA_INT_STATUS + 7] |= (line & 255);
-
-	mace_interrupt_reassert(d);
-}
-void mace_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct mace_data *d = (struct mace_data *) interrupt->extra;
-	uint32_t line = 1 << interrupt->line;
-
-	d->reg[MACE_ISA_INT_STATUS + 4] &= ~((line >> 24) & 255);
-	d->reg[MACE_ISA_INT_STATUS + 5] &= ~((line >> 16) & 255);
-	d->reg[MACE_ISA_INT_STATUS + 6] &= ~((line >> 8) & 255);
-	d->reg[MACE_ISA_INT_STATUS + 7] &= ~(line & 255);
-
-	mace_interrupt_reassert(d);
-}
-
-
-DEVICE_ACCESS(mace)
-{
-	size_t i;
-	struct mace_data *d = (struct mace_data *) extra;
-
-	/*
-	 *  My O2 returns the following when dumping 0xbf310000 and forward:
-	 *
-	 *  +0x00: 0x0000000000000010 0x000000000000001e
-	 *  +0x10: 0x0000000000000000 0x0000000000000000
-	 *
-	 *  and then the following addresses result in the same data as
-	 *  0xbf310000.
-	 */
-	d->reg[MACE_ISA_RINGBASE + 7] = 0x10;
-	d->reg[MACE_ISA_FLASH_NIC_REG + 7] |= MACE_ISA_PWD_CLEAR;
-
-	uint8_t old_mace_isa_flash_nic_reg =
-		d->reg[MACE_ISA_FLASH_NIC_REG + 7];
-
-	if (writeflag == MEM_WRITE)
-		memcpy(&d->reg[relative_addr], data, len);
-	else
-		memcpy(data, &d->reg[relative_addr], len);
-
-	switch (relative_addr & ~7) {
-
-	case MACE_ISA_RINGBASE:
-		break;
-
-	case MACE_ISA_FLASH_NIC_REG:
-		// I think the PROM attempts to read the machine's ethernet
-		// address from a DS2502 EPROM, by writing MACE_ISA_NIC_DEASSERT
-		// to this register in various patterns, and looking at the
-		// resulting MACE_ISA_NIC_DATA (or does it write data as well?)
-		// In any case, onewire is too complicated to implement right
-		// now. TODO.
-		if (writeflag)
-		{
-			/*
-			 *  The NetBSD defines are called "RED" and "GREEN",
-			 *  and are documented like this:
-			 *
-			 *	1=> Illuminate RED LED
-			 *
-			 *  (and similarly for GREEN). But on my O2, it feels
-			 *  like the other way around (i.e. 1 = do NOT illuminate
-			 *  that LED color). Also, having it this way is more
-			 *  compatible with how NetBSD, OpenBSD, and the PROM
-			 *  actually use the LED.
-			 */
-			uint8_t change = (d->reg[MACE_ISA_FLASH_NIC_REG + 7]
-				^ old_mace_isa_flash_nic_reg) &
-				(MACE_ISA_LED_RED | MACE_ISA_LED_GREEN);
-			if (change) {
-				switch (d->reg[MACE_ISA_FLASH_NIC_REG + 7] & (MACE_ISA_LED_RED | MACE_ISA_LED_GREEN)) {
-				case 0:	debug("[ mace: turning LED WHITE/ORANGE ]\n");
-					break;
-				case MACE_ISA_LED_RED:
-					debug("[ mace: turning LED GREEN ]\n");
-					break;
-				case MACE_ISA_LED_GREEN:
-					debug("[ mace: turning LED RED ]\n");
-					break;
-				default:fatal("[ mace: turning LED OFF ]\n");
-					break;
-				}
-			}
-			
-//printf("%02x: MACE_ISA_NIC_DEASSERT = %i, DATA = %i\n",
-	//d->reg[MACE_ISA_FLASH_NIC_REG + 7],
-//d->reg[MACE_ISA_FLASH_NIC_REG + 7] & MACE_ISA_NIC_DEASSERT,
-	//d->reg[MACE_ISA_FLASH_NIC_REG + 7] & MACE_ISA_NIC_DATA);
-		} else {
-//			data[len-1] ^= (random() & MACE_ISA_NIC_DATA);
-//			data[len-1] |= MACE_ISA_NIC_DEASSERT;
-		}
-		break;
-
-	case MACE_ISA_INT_STATUS:	/*  Current interrupt assertions  */
-		/*  don't dump debug info for these  */
-		if (writeflag == MEM_WRITE) {
-			fatal("[ NOTE/TODO: WRITE to mace intr: "
-			    "reladdr=0x%x data=", (int)relative_addr);
-			for (i=0; i<len; i++)
-				fatal(" %02x", data[i]);
-			fatal(" (len=%i) ]\n", len);
-		}
-		break;
-	case MACE_ISA_INT_MASK:		/*  Current interrupt mask  */
-		mace_interrupt_reassert(d);
-		break;
-
-	default:
-		if (writeflag == MEM_READ) {
-			debug("[ mace: read from 0x%x:", (int)relative_addr);
-			for (i=0; i<len; i++)
-				debug(" %02x", data[i]);
-			debug(" (len=%i) ]\n", len);
-		} else {
-			debug("[ mace: write to 0x%x:", (int)relative_addr);
-			for (i=0; i<len; i++)
-				debug(" %02x", data[i]);
-			debug(" (len=%i) ]\n", len);
-		}
-	}
-
-	return 1;
-}
-
-
-DEVINIT(mace)
-{
-	struct mace_data *d;
-	char tmpstr[300];
-	int i;
-
-	CHECK_ALLOCATION(d = (struct mace_data *) malloc(sizeof(struct mace_data)));
-	memset(d, 0, sizeof(struct mace_data));
-
-	snprintf(tmpstr, sizeof(tmpstr), "%s.0x%x",
-	    devinit->interrupt_path, CRIME_INT_PERIPH_SERIAL);
-	INTERRUPT_CONNECT(tmpstr, d->irq_periph);
-
-	snprintf(tmpstr, sizeof(tmpstr), "%s.0x%x",
-	    devinit->interrupt_path, CRIME_INT_PERIPH_MISC);
-	INTERRUPT_CONNECT(tmpstr, d->irq_misc);
-
-	/*
-	 *  For CRIME interrupts PERIPH_SERIAL and PERIPH_MISC,
-	 *  register 32 mace interrupts each.
-	 */
-	for (i=0; i<32; i++) {
-		struct interrupt templ;
-		char name[400];
-		snprintf(name, sizeof(name), "%s.0x%x.mace.%i",
-		    devinit->interrupt_path, CRIME_INT_PERIPH_SERIAL, i);
-		memset(&templ, 0, sizeof(templ));
-                templ.line = i;
-		templ.name = name;
-		templ.extra = d;
-		templ.interrupt_assert = mace_interrupt_assert;
-		templ.interrupt_deassert = mace_interrupt_deassert;
-		interrupt_handler_register(&templ);
-
-		snprintf(name, sizeof(name), "%s.0x%x.mace.%i",
-		    devinit->interrupt_path, CRIME_INT_PERIPH_MISC, i);
-		memset(&templ, 0, sizeof(templ));
-                templ.line = i;
-		templ.name = name;
-		templ.extra = d;
-		templ.interrupt_assert = mace_interrupt_assert;
-		templ.interrupt_deassert = mace_interrupt_deassert;
-		interrupt_handler_register(&templ);
-        }
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_MACE_LENGTH, dev_mace_access, d,
-	    DM_DEFAULT, NULL);
-
-	devinit->return_ptr = d;
-	return 1;
-}
-
-
-/****************************************************************************/
-
-
-DEVICE_ACCESS(macepci)
-{
-	struct macepci_data *d = (struct macepci_data *) extra;
-	uint64_t idata = 0, odata=0;
-	int res = 1, bus, dev, func, pcireg;
-
-	if (len != 4)
-		fatal("[ macepci: unimplemented len %i ]\n", len);
-
-	if (writeflag == MEM_WRITE) {
-		idata = memory_readmax64(cpu, data, len);
-#ifdef MACEPCI_DEBUG
-		fatal("[ macepci: write to address 0x%x, data=0x%02x (len %i) ]\n",
-		    (int)relative_addr, (int)idata, len);
-#endif
-	}
-
-	/*  Read from/write to the macepci:  */
-	switch (relative_addr) {
-
-	case 0x00:	/*  Error address  */
-		if (writeflag == MEM_WRITE) {
-		} else {
-			/*  My real O2 returns 0x4000.  */
-			odata = 0x4000;
-		}
-		break;
-
-	case 0x04:	/*  Error flags  */
-		if (writeflag == MEM_WRITE) {
-		} else {
-			/*  My real O2 returns 0x00100006.  */
-			odata = 0x00100006;
-		}
-		break;
-
-	case 0x08:	/*  TODO: Unknown?  */
-		if (writeflag == MEM_WRITE) {
-		} else {
-			/*  My real O2 returns 0xff000500.  */
-			odata = 0xff000500;
-		}
-		break;
-
-	case 0x0c:	/*  Revision number  */
-		if (writeflag == MEM_WRITE) {
-		} else {
-			/*  My real O2 returns 0x00000001.  */
-			odata = 0x00000001;
-		}
-		break;
-
-	case 0xcf8:	/*  PCI ADDR  */
-		bus_pci_decompose_1(idata, &bus, &dev, &func, &pcireg);
-		bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, pcireg);
-		break;
-
-	case 0xcfc:	/*  PCI DATA  */
-		bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
-		    &odata : &idata, len, writeflag);
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ macepci: unimplemented write to address "
-			    "0x%x, data=0x%02x ]\n",
-			    (int)relative_addr, (int)idata);
-		} else {
-			fatal("[ macepci: unimplemented read from address "
-			    "0x%x ]\n", (int)relative_addr);
-
-			/*  My real O2 returns 0xffffffff for all unimplemented
-				registers.  */
-			odata = 0xffffffff;
-		}
-	}
-
-	if (writeflag == MEM_READ) {
-		memory_writemax64(cpu, data, len, odata);
-#ifdef MACEPCI_DEBUG
-		fatal("[ macepci: read from address 0x%x, data=0x%02x (len %i) ]\n",
-		    (int)relative_addr, (int)odata, len);
-#endif
-	}
-
-	return res;
-}
-
-
-/*
- *  dev_macepci_init():
- */
-struct pci_data *dev_macepci_init(struct machine *machine,
-	struct memory *mem, uint64_t baseaddr, char *irq_path)
-{
-	struct macepci_data *d;
-
-	CHECK_ALLOCATION(d = (struct macepci_data *) malloc(sizeof(struct macepci_data)));
-	memset(d, 0, sizeof(struct macepci_data));
-
-	/*  TODO: PCI vs ISA interrupt?  */
-
-	d->pci_data = bus_pci_init(machine,
-	    irq_path,
-	    0,
-	    0,
-	    0,
-	    0,
-	    "TODO: pci irq path",
-	    0x18000003,		/*  ISA portbase  */
-	    0,
-	    irq_path);
-
-	memory_device_register(mem, "macepci", baseaddr, DEV_MACEPCI_LENGTH,
-	    dev_macepci_access, (void *)d, DM_DEFAULT, NULL);
-
-	return d->pci_data;
-}
-
-
-/****************************************************************************/
-
-
-struct sgi_ust_data {
-	uint64_t	reg[DEV_SGI_UST_LENGTH / sizeof(uint64_t)];
-};
-
-
-DEVICE_ACCESS(sgi_ust)
-{
-	struct sgi_ust_data *d = (struct sgi_ust_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-
-	idata = memory_readmax64(cpu, data, len);
-	regnr = relative_addr / sizeof(uint64_t);
-
-	/*  Treat all registers as read/write, by default.  */
-	if (writeflag == MEM_WRITE)
-		d->reg[regnr] = idata;
-	else
-		odata = d->reg[regnr];
-
-	switch (relative_addr) {
-	case 0:
-		d->reg[regnr] += 0x2710;	// HUH?
-		break;
-	default:
-		if (writeflag == MEM_WRITE)
-			debug("[ sgi_ust: unimplemented write to "
-			    "address 0x%llx, data=0x%016llx ]\n",
-			    (long long)relative_addr, (long long)idata);
-		else
-			debug("[ sgi_ust: unimplemented read from address"
-			    " 0x%llx ]\n", (long long)relative_addr);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_sgi_ust_init():
- */
-void dev_sgi_ust_init(struct memory *mem, uint64_t baseaddr)
-{
-	struct sgi_ust_data *d;
-
-	CHECK_ALLOCATION(d = (struct sgi_ust_data *) malloc(sizeof(struct sgi_ust_data)));
-	memset(d, 0, sizeof(struct sgi_ust_data));
-
-	memory_device_register(mem, "sgi_ust", baseaddr,
-	    DEV_SGI_UST_LENGTH, dev_sgi_ust_access, (void *)d,
-	    DM_DEFAULT, NULL);
-}
-
-
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_mardigras.c gxemul-0.7.0+dfsg/src/devices/dev_sgi_mardigras.c
--- gxemul-0.6.2/src/devices/dev_sgi_mardigras.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_mardigras.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,322 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: MardiGras graphics controller on SGI IP30 (Octane)
+ *
+ *  Most of this is just guesses based on the behaviour of Linux/Octane.
+ *
+ *  TODO
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "memory.h"
+#include "machine.h"
+#include "misc.h"
+
+
+#define debug fatal
+
+
+#define	DEV_SGI_MARDIGRAS_LENGTH	0x800000
+
+#define	MARDIGRAS_FAKE_OFFSET	0x500000000ULL	/*  hopefully available  */
+#define	MARDIGRAS_DEFAULT_XSIZE	1280
+#define	MARDIGRAS_DEFAULT_YSIZE	1024
+
+#define	MICROCODE_START		0x50000
+#define	MICROCODE_END		0x55000
+
+static int mardigras_xsize = MARDIGRAS_DEFAULT_XSIZE;
+static int mardigras_ysize = MARDIGRAS_DEFAULT_YSIZE;
+
+struct sgi_mardigras_data {
+	struct vfb_data		*fb;
+	unsigned char		microcode_ram[MICROCODE_END - MICROCODE_START];
+	uint64_t		palette_reg_select;
+	int			currentx;
+	int			currenty;
+	int			color;
+	int			startx;
+	int			starty;
+	int			stopx;
+	int			stopy;
+	uint64_t		draw_mode;
+};
+
+
+/*
+ *  mardigras_20400():
+ */
+void mardigras_20400(struct cpu *cpu, struct sgi_mardigras_data *d,
+	uint64_t idata)
+{
+	int i, x, y, r,g,b, len, addr;
+	unsigned char pixels[3 * 8000];
+
+	/*  Get rgb from palette:  */
+	r = d->fb->rgb_palette[d->color * 3 + 0];
+	g = d->fb->rgb_palette[d->color * 3 + 1];
+	b = d->fb->rgb_palette[d->color * 3 + 2];
+
+	/*  Set color:  */
+	if ((idata & 0x00ffffff00000000ULL) == 0x00185C0400000000ULL) {
+		int color = (idata >> 12) & 0xff;
+		d->color = color;
+		return;
+	}
+
+	/*  Set start XY:  */
+	if ((idata & 0x00ffffff00000000ULL) == 0x0018460400000000ULL) {
+		d->startx = (idata >> 16) & 0xffff;
+		d->starty = idata & 0xffff;
+		if (d->startx >= mardigras_xsize)
+			d->startx = 0;
+		if (d->starty >= mardigras_ysize)
+			d->starty = 0;
+		d->currentx = d->startx;
+		d->currenty = d->starty;
+		return;
+	}
+
+	/*  Set stop XY:  */
+	if ((idata & 0x00ffffff00000000ULL) == 0x0018470400000000ULL) {
+		d->stopx = (idata >> 16) & 0xffff;
+		d->stopy = idata & 0xffff;
+		if (d->stopx >= mardigras_xsize)
+			d->stopx = 0;
+		if (d->stopy >= mardigras_ysize)
+			d->stopy = 0;
+		return;
+	}
+
+	/*  Draw modes: (Rectangle or Bitmap, respectively)  */
+	if (idata == 0x0019100400018000ULL ||
+	    idata == 0x0019100400418008ULL) {
+		d->draw_mode = idata;
+		return;
+	}
+
+	/*  Send command:  */
+	if (idata == 0x001C130400000018ULL) {
+		switch (d->draw_mode) {
+		/*  Rectangle:  */
+		case 0x0019100400018000ULL:
+			/*  Fill pixels[] with pixels:  */
+			len = 0;
+			for (x=d->startx; x<=d->stopx; x++) {
+				pixels[len + 0] = r;
+				pixels[len + 1] = g;
+				pixels[len + 2] = b;
+				len += 3;
+			}
+			if (len == 0)
+				break;
+			for (y=d->starty; y<=d->stopy; y++) {
+				addr = (mardigras_xsize * (mardigras_ysize -
+				    1 - y) + d->startx) * 3;
+				/*  printf("addr = %i\n", addr);  */
+
+				/*  Write a line:  */
+				dev_fb_access(cpu, cpu->mem,
+				    addr, pixels, len, MEM_WRITE, d->fb);
+			}
+			break;
+		/*  Bitmap:  */
+		case 0x0019100400418008ULL:
+			break;
+		default:
+			fatal("[ sgi_mardigras: unknown draw mode ]\n");
+		}
+		return;
+	}
+
+	/*  Send a line of bitmap data:  */
+	if ((idata & 0x00ffffff00000000ULL) == 0x001C700400000000ULL) {
+		addr = (mardigras_xsize * (mardigras_ysize - 1 - d->currenty)
+		    + d->currentx) * 3;
+/*
+		printf("addr=%08x curx,y=%4i,%4i startx,y=%4i,%4i "
+		    "stopx,y=%4i,%4i\n", addr, d->currentx, d->currenty,
+		    d->startx, d->starty, d->stopx, d->stopy);
+*/
+		len = 8*3;
+
+		if (addr > mardigras_xsize * mardigras_ysize * 3 || addr < 0)
+			return;
+
+		/*  Read a line:  */
+		dev_fb_access(cpu, cpu->mem,
+		    addr, pixels, len, MEM_READ, d->fb);
+
+		i = 0;
+		while (i < 8) {
+			if ((idata >> (24 + (7-i))) & 1) {
+				pixels[i*3 + 0] = r;
+				pixels[i*3 + 1] = g;
+				pixels[i*3 + 2] = b;
+			}
+			i ++;
+
+			d->currentx ++;
+			if (d->currentx > d->stopx) {
+				d->currentx = d->startx;
+				d->currenty ++;
+				if (d->currenty > d->stopy)
+					d->currenty = d->starty;
+			}
+		}
+
+		/*  Write a line:  */
+		dev_fb_access(cpu, cpu->mem,
+		    addr, pixels, len, MEM_WRITE, d->fb);
+
+		return;
+	}
+
+	debug("mardigras_20400(): 0x%016" PRIx64"\n", (uint64_t) idata);
+}
+
+
+DEVICE_ACCESS(sgi_mardigras)
+{
+	uint64_t idata = 0, odata = 0;
+	struct sgi_mardigras_data *d = (struct sgi_mardigras_data *) extra;
+	int i;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  Accessing the microcode_ram works like ordinary ram:  */
+	if (relative_addr >= MICROCODE_START &&
+	    relative_addr <  MICROCODE_END) {
+		relative_addr -= MICROCODE_START;
+		if (writeflag == MEM_WRITE)
+			memcpy(d->microcode_ram + relative_addr, data, len);
+		else
+			memcpy(data, d->microcode_ram + relative_addr, len);
+		return 1;
+	}
+
+	switch (relative_addr) {
+
+	case 0x00004:
+		/*  xtalk data:  (according to Linux/IP30)  */
+		/*  (mfgr & 0x7ff) << 1  */
+		/*  (part & 0xffff) << 12  */
+		/*  (rev  & 0xf) << 28  */
+		odata = (2 << 28) | (0xc003 << 12) | (0x2aa << 1);
+		break;
+
+	case 0x20008:	/*  Fifo status  */
+		break;
+
+	case 0x20200:
+		break;
+
+	case 0x20400:
+		if (writeflag == MEM_WRITE)
+			mardigras_20400(cpu, d, idata);
+		else
+			debug("[ sgi_mardigras: read from 0x20400? ]\n");
+		break;
+
+	case 0x58040:
+		/*  HQ4 microcode stuff  */
+		break;
+
+	case 0x70c30:
+		/*  Palette register select?  */
+		if (writeflag == MEM_WRITE)
+			d->palette_reg_select = idata;
+		else
+			odata = d->palette_reg_select;
+		break;
+
+	case 0x70d18:
+		/*  Palette register read/write?  */
+		i = 3 * ((d->palette_reg_select >> 8) & 0xff);
+		if (writeflag == MEM_WRITE) {
+			d->fb->rgb_palette[i + 0] = (idata >> 24) & 0xff;
+			d->fb->rgb_palette[i + 1] = (idata >> 16) & 0xff;
+			d->fb->rgb_palette[i + 2] = (idata >>  8) & 0xff;
+		} else {
+			odata = (d->fb->rgb_palette[i+0] << 24) +
+				(d->fb->rgb_palette[i+1] << 16) +
+				(d->fb->rgb_palette[i+2] << 8);
+		}
+		break;
+
+	case 0x71208:
+		odata = 8;
+		break;
+
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ sgi_mardigras: read from 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			debug("[ sgi_mardigras: write to  0x%08lx: 0x%016" PRIx64
+			    " ]\n", (long) relative_addr, (uint64_t) idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(sgi_mardigras)
+{
+	struct sgi_mardigras_data *d;
+
+	CHECK_ALLOCATION(d = (struct sgi_mardigras_data *) malloc(sizeof(struct sgi_mardigras_data)));
+	memset(d, 0, sizeof(struct sgi_mardigras_data));
+
+	d->fb = dev_fb_init(devinit->machine, devinit->machine->memory,
+	    MARDIGRAS_FAKE_OFFSET, VFB_GENERIC,
+	    mardigras_xsize, mardigras_ysize,
+	    mardigras_xsize, mardigras_ysize, 24, "SGI MardiGras");
+	if (d->fb == NULL) {
+		fprintf(stderr, "dev_sgi_mardigras_init(): out of memory\n");
+		exit(1);
+	}
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_SGI_MARDIGRAS_LENGTH, dev_sgi_mardigras_access,
+	    d, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_mardigras.cc gxemul-0.7.0+dfsg/src/devices/dev_sgi_mardigras.cc
--- gxemul-0.6.2/src/devices/dev_sgi_mardigras.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_mardigras.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,322 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: MardiGras graphics controller on SGI IP30 (Octane)
- *
- *  Most of this is just guesses based on the behaviour of Linux/Octane.
- *
- *  TODO
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "memory.h"
-#include "machine.h"
-#include "misc.h"
-
-
-#define debug fatal
-
-
-#define	DEV_SGI_MARDIGRAS_LENGTH	0x800000
-
-#define	MARDIGRAS_FAKE_OFFSET	0x500000000ULL	/*  hopefully available  */
-#define	MARDIGRAS_DEFAULT_XSIZE	1280
-#define	MARDIGRAS_DEFAULT_YSIZE	1024
-
-#define	MICROCODE_START		0x50000
-#define	MICROCODE_END		0x55000
-
-static int mardigras_xsize = MARDIGRAS_DEFAULT_XSIZE;
-static int mardigras_ysize = MARDIGRAS_DEFAULT_YSIZE;
-
-struct sgi_mardigras_data {
-	struct vfb_data		*fb;
-	unsigned char		microcode_ram[MICROCODE_END - MICROCODE_START];
-	uint64_t		palette_reg_select;
-	int			currentx;
-	int			currenty;
-	int			color;
-	int			startx;
-	int			starty;
-	int			stopx;
-	int			stopy;
-	uint64_t		draw_mode;
-};
-
-
-/*
- *  mardigras_20400():
- */
-void mardigras_20400(struct cpu *cpu, struct sgi_mardigras_data *d,
-	uint64_t idata)
-{
-	int i, x, y, r,g,b, len, addr;
-	unsigned char pixels[3 * 8000];
-
-	/*  Get rgb from palette:  */
-	r = d->fb->rgb_palette[d->color * 3 + 0];
-	g = d->fb->rgb_palette[d->color * 3 + 1];
-	b = d->fb->rgb_palette[d->color * 3 + 2];
-
-	/*  Set color:  */
-	if ((idata & 0x00ffffff00000000ULL) == 0x00185C0400000000ULL) {
-		int color = (idata >> 12) & 0xff;
-		d->color = color;
-		return;
-	}
-
-	/*  Set start XY:  */
-	if ((idata & 0x00ffffff00000000ULL) == 0x0018460400000000ULL) {
-		d->startx = (idata >> 16) & 0xffff;
-		d->starty = idata & 0xffff;
-		if (d->startx >= mardigras_xsize)
-			d->startx = 0;
-		if (d->starty >= mardigras_ysize)
-			d->starty = 0;
-		d->currentx = d->startx;
-		d->currenty = d->starty;
-		return;
-	}
-
-	/*  Set stop XY:  */
-	if ((idata & 0x00ffffff00000000ULL) == 0x0018470400000000ULL) {
-		d->stopx = (idata >> 16) & 0xffff;
-		d->stopy = idata & 0xffff;
-		if (d->stopx >= mardigras_xsize)
-			d->stopx = 0;
-		if (d->stopy >= mardigras_ysize)
-			d->stopy = 0;
-		return;
-	}
-
-	/*  Draw modes: (Rectangle or Bitmap, respectively)  */
-	if (idata == 0x0019100400018000ULL ||
-	    idata == 0x0019100400418008ULL) {
-		d->draw_mode = idata;
-		return;
-	}
-
-	/*  Send command:  */
-	if (idata == 0x001C130400000018ULL) {
-		switch (d->draw_mode) {
-		/*  Rectangle:  */
-		case 0x0019100400018000ULL:
-			/*  Fill pixels[] with pixels:  */
-			len = 0;
-			for (x=d->startx; x<=d->stopx; x++) {
-				pixels[len + 0] = r;
-				pixels[len + 1] = g;
-				pixels[len + 2] = b;
-				len += 3;
-			}
-			if (len == 0)
-				break;
-			for (y=d->starty; y<=d->stopy; y++) {
-				addr = (mardigras_xsize * (mardigras_ysize -
-				    1 - y) + d->startx) * 3;
-				/*  printf("addr = %i\n", addr);  */
-
-				/*  Write a line:  */
-				dev_fb_access(cpu, cpu->mem,
-				    addr, pixels, len, MEM_WRITE, d->fb);
-			}
-			break;
-		/*  Bitmap:  */
-		case 0x0019100400418008ULL:
-			break;
-		default:
-			fatal("[ sgi_mardigras: unknown draw mode ]\n");
-		}
-		return;
-	}
-
-	/*  Send a line of bitmap data:  */
-	if ((idata & 0x00ffffff00000000ULL) == 0x001C700400000000ULL) {
-		addr = (mardigras_xsize * (mardigras_ysize - 1 - d->currenty)
-		    + d->currentx) * 3;
-/*
-		printf("addr=%08x curx,y=%4i,%4i startx,y=%4i,%4i "
-		    "stopx,y=%4i,%4i\n", addr, d->currentx, d->currenty,
-		    d->startx, d->starty, d->stopx, d->stopy);
-*/
-		len = 8*3;
-
-		if (addr > mardigras_xsize * mardigras_ysize * 3 || addr < 0)
-			return;
-
-		/*  Read a line:  */
-		dev_fb_access(cpu, cpu->mem,
-		    addr, pixels, len, MEM_READ, d->fb);
-
-		i = 0;
-		while (i < 8) {
-			if ((idata >> (24 + (7-i))) & 1) {
-				pixels[i*3 + 0] = r;
-				pixels[i*3 + 1] = g;
-				pixels[i*3 + 2] = b;
-			}
-			i ++;
-
-			d->currentx ++;
-			if (d->currentx > d->stopx) {
-				d->currentx = d->startx;
-				d->currenty ++;
-				if (d->currenty > d->stopy)
-					d->currenty = d->starty;
-			}
-		}
-
-		/*  Write a line:  */
-		dev_fb_access(cpu, cpu->mem,
-		    addr, pixels, len, MEM_WRITE, d->fb);
-
-		return;
-	}
-
-	debug("mardigras_20400(): 0x%016" PRIx64"\n", (uint64_t) idata);
-}
-
-
-DEVICE_ACCESS(sgi_mardigras)
-{
-	uint64_t idata = 0, odata = 0;
-	struct sgi_mardigras_data *d = (struct sgi_mardigras_data *) extra;
-	int i;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  Accessing the microcode_ram works like ordinary ram:  */
-	if (relative_addr >= MICROCODE_START &&
-	    relative_addr <  MICROCODE_END) {
-		relative_addr -= MICROCODE_START;
-		if (writeflag == MEM_WRITE)
-			memcpy(d->microcode_ram + relative_addr, data, len);
-		else
-			memcpy(data, d->microcode_ram + relative_addr, len);
-		return 1;
-	}
-
-	switch (relative_addr) {
-
-	case 0x00004:
-		/*  xtalk data:  (according to Linux/IP30)  */
-		/*  (mfgr & 0x7ff) << 1  */
-		/*  (part & 0xffff) << 12  */
-		/*  (rev  & 0xf) << 28  */
-		odata = (2 << 28) | (0xc003 << 12) | (0x2aa << 1);
-		break;
-
-	case 0x20008:	/*  Fifo status  */
-		break;
-
-	case 0x20200:
-		break;
-
-	case 0x20400:
-		if (writeflag == MEM_WRITE)
-			mardigras_20400(cpu, d, idata);
-		else
-			debug("[ sgi_mardigras: read from 0x20400? ]\n");
-		break;
-
-	case 0x58040:
-		/*  HQ4 microcode stuff  */
-		break;
-
-	case 0x70c30:
-		/*  Palette register select?  */
-		if (writeflag == MEM_WRITE)
-			d->palette_reg_select = idata;
-		else
-			odata = d->palette_reg_select;
-		break;
-
-	case 0x70d18:
-		/*  Palette register read/write?  */
-		i = 3 * ((d->palette_reg_select >> 8) & 0xff);
-		if (writeflag == MEM_WRITE) {
-			d->fb->rgb_palette[i + 0] = (idata >> 24) & 0xff;
-			d->fb->rgb_palette[i + 1] = (idata >> 16) & 0xff;
-			d->fb->rgb_palette[i + 2] = (idata >>  8) & 0xff;
-		} else {
-			odata = (d->fb->rgb_palette[i+0] << 24) +
-				(d->fb->rgb_palette[i+1] << 16) +
-				(d->fb->rgb_palette[i+2] << 8);
-		}
-		break;
-
-	case 0x71208:
-		odata = 8;
-		break;
-
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ sgi_mardigras: read from 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			debug("[ sgi_mardigras: write to  0x%08lx: 0x%016" PRIx64
-			    " ]\n", (long) relative_addr, (uint64_t) idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(sgi_mardigras)
-{
-	struct sgi_mardigras_data *d;
-
-	CHECK_ALLOCATION(d = (struct sgi_mardigras_data *) malloc(sizeof(struct sgi_mardigras_data)));
-	memset(d, 0, sizeof(struct sgi_mardigras_data));
-
-	d->fb = dev_fb_init(devinit->machine, devinit->machine->memory,
-	    MARDIGRAS_FAKE_OFFSET, VFB_GENERIC,
-	    mardigras_xsize, mardigras_ysize,
-	    mardigras_xsize, mardigras_ysize, 24, "SGI MardiGras");
-	if (d->fb == NULL) {
-		fprintf(stderr, "dev_sgi_mardigras_init(): out of memory\n");
-		exit(1);
-	}
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_SGI_MARDIGRAS_LENGTH, dev_sgi_mardigras_access,
-	    d, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_mec.c gxemul-0.7.0+dfsg/src/devices/dev_sgi_mec.c
--- gxemul-0.6.2/src/devices/dev_sgi_mec.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_mec.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,699 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: SGI IP32 "mec" ethernet
+ *
+ *  Used by the SGI O2 emulation mode.
+ *  Based on how NetBSD and OpenBSD use the hardware, just about enough to let
+ *  those OSes boot with root-on-nfs.
+ *
+ *  http://www.openbsd.org/cgi-bin/cvsweb/src/sys/arch/sgi/dev/if_mec.c
+ *
+ *  TODO:
+ *
+ *	x)  tx and rx interrupts/ring/slot stuff
+ *
+ *  A note about word length for reads/writes:
+ *
+ *	NetBSD uses (at least) 64-bit reads/writes.
+ *	OpenBSD uses both 32-bit and 64-bit reads/writes.
+ *	The PROM uses (at least) 32-bit reads/writes and 16-bit reads (from
+ *		offsets 0x34 and 0x36)!
+ *
+ *  Random googling reveals this NetBSD dmesg about the PHYs:
+ *
+ *	https://mail-index.netbsd.org/port-sgimips/2008/01/27/msg000043.html
+ *
+ *	mec0 at mace0 offset 0x280000 intr 3 intrmask 0x0: MAC-110 Ethernet, rev 1
+ *	mec0: Ethernet address 08:00:69:0e:85:21
+ *	nsphy0 at mec0 phy 8: DP83840 10/100 media interface, rev. 1
+ *	nsphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_pci.h"
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "net.h"
+
+#include "thirdparty/if_mecreg.h"
+#include "thirdparty/mii.h"
+
+// #define debug fatal
+// #define MEC_DEBUG
+
+#define	MEC_TICK_SHIFT		14
+
+#define	MAX_TX_PACKET_LEN	1700
+#define	N_RX_ADDRESSES		16
+
+struct sgi_mec_data {
+	struct nic_data	nic;
+
+	uint64_t	reg[DEV_SGI_MEC_LENGTH / sizeof(uint64_t)];
+
+	struct interrupt irq;
+	int		prev_asserted;
+
+	unsigned char	cur_tx_packet[MAX_TX_PACKET_LEN];
+	int		cur_tx_packet_len;
+
+	unsigned char	*cur_rx_packet;
+	int		cur_rx_packet_len;
+
+	uint64_t	rx_addr[N_RX_ADDRESSES];
+	int		cur_rx_addr_index_write;
+	int		cur_rx_addr_index;
+};
+
+
+/*
+ *  mec_reset():
+ */
+static void mec_reset(struct sgi_mec_data *d)
+{
+	if (d->cur_rx_packet != NULL)
+		free(d->cur_rx_packet);
+
+	memset(d->reg, 0, sizeof(d->reg));
+}
+
+
+/*
+ *  mec_control_write():
+ */
+static void mec_control_write(struct cpu *cpu, struct sgi_mec_data *d,
+	uint64_t x)
+{
+	if (x & MEC_MAC_CORE_RESET) {
+		debug("[ sgi_mec: CORE RESET ]\n");
+		mec_reset(d);
+	}
+}
+
+
+/*
+ *  mec_try_rx():
+ */
+static int mec_try_rx(struct cpu *cpu, struct sgi_mec_data *d)
+{
+	uint64_t base;
+	unsigned char data[8];
+	int i, res, retval = 0;
+
+	base = d->rx_addr[d->cur_rx_addr_index];
+	if (base & 0xfff)
+		fatal("[ mec_try_rx(): WARNING! lowest bits of base are "
+		    "non-zero (0x%3x). TODO ]\n", (int)(base & 0xfff));
+	base &= 0xfffff000ULL;
+	if (base == 0)
+		goto skip;
+
+	/*  printf("rx base = 0x%016llx\n", (long long)base);  */
+
+	/*  Read an rx descriptor from memory:  */
+	res = cpu->memory_rw(cpu, cpu->mem, base,
+	    &data[0], sizeof(data), MEM_READ, PHYSICAL);
+	if (!res)
+		return 0;
+
+	/*  Is this descriptor already in use?  */
+	if (data[0] & 0x80) {
+		/*  printf("INTERRUPT for base = 0x%x\n", (int)base);  */
+		goto skip_and_advance;
+	}
+
+	if (d->cur_rx_packet == NULL &&
+	    net_ethernet_rx_avail(cpu->machine->emul->net, &d->nic))
+		net_ethernet_rx(cpu->machine->emul->net, &d->nic,
+		    &d->cur_rx_packet, &d->cur_rx_packet_len);
+
+	if (d->cur_rx_packet == NULL)
+		goto skip;
+
+#if 0
+	printf("{ mec: rxdesc %i: ", d->cur_rx_addr_index);
+	for (i=0; i<sizeof(data); i++) {
+		if ((i & 3) == 0)
+			printf(" ");
+		printf("%02x", data[i]);
+	}
+	printf(" }\n");
+#endif
+
+	/*  Copy the packet data:  */
+	//printf("RX: ");
+	for (i=0; i<d->cur_rx_packet_len; i++) {
+		res = cpu->memory_rw(cpu, cpu->mem, base + 32 + i + 2,
+		    d->cur_rx_packet + i, 1, MEM_WRITE, PHYSICAL);
+		//printf(" %02x", d->cur_rx_packet[i]);
+	}
+	//printf("\n");
+
+#if 0
+	printf("RX: %i bytes, index %i, base = 0x%x\n",
+	    d->cur_rx_packet_len, d->cur_rx_addr_index, (int)base);
+#endif
+
+	/*  4 bytes of CRC at the end. Hm. TODO  */
+	d->cur_rx_packet_len += 4;
+
+	memset(data, 0, sizeof(data));
+	data[6] = (d->cur_rx_packet_len >> 8) & 255;
+	data[7] = d->cur_rx_packet_len & 255;
+	/*  TODO: lots of bits :-)  */
+	data[4] = 0x04;		/*  match MAC  */
+	data[0] = 0x80;		/*  0x80 = received.  */
+	res = cpu->memory_rw(cpu, cpu->mem, base,
+	    &data[0], sizeof(data), MEM_WRITE, PHYSICAL);
+
+	/*  Free the packet from memory:  */
+	free(d->cur_rx_packet);
+	d->cur_rx_packet = NULL;
+
+	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] |= MEC_INT_RX_THRESHOLD;
+skip_and_advance:
+	d->cur_rx_addr_index ++;
+	d->cur_rx_addr_index %= N_RX_ADDRESSES;
+	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] &= ~MEC_INT_RX_MCL_FIFO_ALIAS;
+	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] |=
+	    (d->cur_rx_addr_index & 0x1f) << 8;
+	retval = 1;
+
+skip:
+	return retval;
+}
+
+
+/*
+ *  mec_try_tx():
+ */
+static int mec_try_tx(struct cpu *cpu, struct sgi_mec_data *d)
+{
+	uint64_t base, addr, dma_base;
+	int tx_ring_ptr, ringread, ringwrite, res, i, j;
+	unsigned char data[32];
+	int len, start_offset, dma_ptr_nr, dma_len;
+
+	base = d->reg[MEC_TX_RING_BASE / sizeof(uint64_t)];
+	tx_ring_ptr = d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)];
+
+	if (base == 0)
+		return 0;
+
+	/*  printf("base = 0x%016llx\n", base);  */
+
+	ringread = tx_ring_ptr & MEC_TX_RING_READ_PTR;
+	ringwrite = tx_ring_ptr & MEC_TX_RING_WRITE_PTR;
+	ringread >>= 16;
+	/*  All done? Then abort.  */
+	if (ringread == ringwrite)
+		return 0;
+
+	tx_ring_ptr &= MEC_TX_RING_READ_PTR;
+	tx_ring_ptr >>= 16;
+
+	/*  Each tx descriptor (+ buffer) is 128 bytes:  */
+	addr = base + tx_ring_ptr*128;
+	res = cpu->memory_rw(cpu, cpu->mem, addr,
+	    &data[0], sizeof(data), MEM_READ, PHYSICAL);
+	if (!res)
+		return 0;
+
+	/*  Is this packet transmitted already?  */
+	if (data[0] & 0x80) {
+		fatal("[ mec_try_tx: tx_ring_ptr = %i, already"
+		    " transmitted? ]\n", tx_ring_ptr);
+		goto advance_tx;
+	}
+
+	len = data[6] * 256 + data[7];
+	start_offset = data[5] & 0x7f;
+
+	/*  Is this packet empty? Then don't transmit.  */
+	if (len == 0)
+		return 0;
+
+	/*  Hm. Is len one too little?  TODO  */
+	len ++;
+
+#if 0
+	printf("{ mec: txdesc %i: ", tx_ring_ptr);
+	for (i=0; i<sizeof(data); i++) {
+		if ((i & 3) == 0)
+			printf(" ");
+		printf("%02x", data[i]);
+	}
+	printf(" }\n");
+#endif
+	dma_ptr_nr = 0;
+
+	j = 0;
+	d->cur_tx_packet_len = len;
+
+	//printf("TX: ");
+	for (i=start_offset; i<start_offset+len; i++) {
+		unsigned char ch;
+
+		if ((i & 0x7f) == 0x00)
+			break;
+
+		res = cpu->memory_rw(cpu, cpu->mem, addr + i,
+		    &ch, sizeof(ch), MEM_READ, PHYSICAL);
+		//printf(" %02x", ch);
+
+		d->cur_tx_packet[j++] = ch;
+		if (j >= MAX_TX_PACKET_LEN) {
+			fatal("[ mec_try_tx: packet too large? ]\n");
+			break;
+		}
+	}
+	//printf("\n");
+
+	if (j < len) {
+		/*  Continue with DMA:  */
+		for (;;) {
+			dma_ptr_nr ++;
+			if (dma_ptr_nr >= 4)
+				break;
+			if (!(data[4] & (0x01 << dma_ptr_nr)))
+				break;
+			dma_base = (data[dma_ptr_nr * 8 + 4] << 24)
+			         + (data[dma_ptr_nr * 8 + 5] << 16)
+			         + (data[dma_ptr_nr * 8 + 6] <<  8)
+			         + (data[dma_ptr_nr * 8 + 7]);
+			dma_base &= 0xfffffff8ULL;
+			dma_len = (data[dma_ptr_nr * 8 + 2] << 8)
+			        + (data[dma_ptr_nr * 8 + 3]) + 1;
+
+			/*  printf("dma_base = %08x, dma_len = %i\n",
+			    (int)dma_base, dma_len);  */
+
+			while (dma_len > 0) {
+				unsigned char ch;
+				res = cpu->memory_rw(cpu, cpu->mem, dma_base,
+				    &ch, sizeof(ch), MEM_READ, PHYSICAL);
+				/*  printf(" %02x", ch);  */
+
+				d->cur_tx_packet[j++] = ch;
+				if (j >= MAX_TX_PACKET_LEN) {
+					fatal("[ mec_try_tx: packet too large?"
+					    " ]\n");
+					break;
+				}
+				dma_base ++;
+				dma_len --;
+			}
+		}
+	}
+
+	if (j < len)
+		fatal("[ mec_try_tx: not enough data? ]\n");
+
+	net_ethernet_tx(cpu->machine->emul->net, &d->nic,
+	    d->cur_tx_packet, d->cur_tx_packet_len);
+
+	/*  see openbsd's if_mec.c for details  */
+	if (data[4] & 0x01) {
+		d->reg[MEC_INT_STATUS / sizeof(uint64_t)] |=
+		    MEC_INT_TX_PACKET_SENT;
+	}
+	memset(data, 0, 6);	/*  last 2 bytes are len  */
+	data[0] = 0x80;
+	data[5] = 0x80;
+
+	res = cpu->memory_rw(cpu, cpu->mem, addr,
+	    &data[0], sizeof(data), MEM_WRITE, PHYSICAL);
+
+	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] |= MEC_INT_TX_EMPTY;
+	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] |= MEC_INT_TX_PACKET_SENT;
+
+advance_tx:
+	/*  Advance the ring Read ptr.  */
+	tx_ring_ptr = d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)];
+	ringread = tx_ring_ptr & MEC_TX_RING_READ_PTR;
+	ringwrite = tx_ring_ptr & MEC_TX_RING_WRITE_PTR;
+
+	ringread = (ringread >> 16) + 1;
+	ringread &= 63;
+	ringread <<= 16;
+
+	d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)] =
+	    (ringwrite & MEC_TX_RING_WRITE_PTR) |
+	    (ringread & MEC_TX_RING_READ_PTR);
+
+	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] &=
+	    ~MEC_INT_TX_RING_BUFFER_ALIAS;
+	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] |=
+	    (d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)] &
+	    MEC_INT_TX_RING_BUFFER_ALIAS);
+
+	return 1;
+}
+
+
+DEVICE_TICK(sgi_mec)
+{
+	struct sgi_mec_data *d = (struct sgi_mec_data *) extra;
+	int n = 0;
+
+	while (mec_try_tx(cpu, d))
+		;
+
+	while (mec_try_rx(cpu, d) && n < 16)
+		n++;
+
+	/*  Interrupts:  (TODO: only when enabled)  */
+	int asserted = !!(d->reg[MEC_INT_STATUS / sizeof(uint64_t)] & MEC_INT_STATUS_MASK);
+
+	if (asserted && !d->prev_asserted)
+		INTERRUPT_ASSERT(d->irq);
+	else if (!asserted && d->prev_asserted)
+		INTERRUPT_DEASSERT(d->irq);
+
+	d->prev_asserted = asserted;
+}
+
+
+DEVICE_ACCESS(sgi_mec)
+{
+	struct sgi_mec_data *d = (struct sgi_mec_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int regnr;
+
+	uint64_t old_int_status = d->reg[MEC_INT_STATUS / sizeof(uint64_t)];
+	uint64_t old_tx_ring_ptr = d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)];
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	regnr = relative_addr / sizeof(uint64_t);
+
+	if ((relative_addr & ~7) == MEC_TX_RING_PTR_ALIAS)
+		relative_addr -= 8;
+
+	// Support both 32-bit and 64-bit big-endian loads and stores...
+	if (len == sizeof(uint64_t)) {
+		if (writeflag == MEM_WRITE)
+			d->reg[regnr] = idata;
+		else
+			odata = d->reg[regnr];
+	} else if (len == sizeof(uint32_t)) {
+		if (writeflag == MEM_WRITE) {
+			if (relative_addr & 4)
+				d->reg[regnr] = (d->reg[regnr] & ~0xffffffffULL) | (uint32_t)idata;
+			else
+				d->reg[regnr] = (d->reg[regnr] & 0xffffffffULL) | ((uint64_t)idata << 32ULL);
+		} else {
+			odata = d->reg[regnr];
+			if (relative_addr & 4)
+				odata = (int32_t)odata;
+			else
+				odata = (odata >> 32ULL);
+		}
+	} else if (len == sizeof(uint16_t)) {
+		if (writeflag == MEM_WRITE) {
+			fatal("[ sgi_mec: unimplemented %s len %i (addr 0x%x) ]\n",
+				writeflag ? "write" : "read", len, (long long)relative_addr);
+		} else if ((relative_addr & 7) == 4) {
+			odata = d->reg[regnr];
+			odata = (uint16_t)(odata >> 16);
+		} else if ((relative_addr & 7) == 6) {
+			odata = d->reg[regnr];
+			odata = (uint16_t)odata;
+		} else {
+			fatal("[ sgi_mec: unimplemented %s len %i (addr 0x%x) ]\n",
+				writeflag ? "write" : "read", len, (long long)relative_addr);
+		}
+	} else {
+		fatal("[ sgi_mec: unimplemented %s len %i (addr 0x%x) ]\n",
+			writeflag ? "write" : "read", len, (long long)relative_addr);
+	}
+
+#ifdef MEC_DEBUG
+	if (writeflag == MEM_WRITE)
+		fatal("[ sgi_mec: write to address"
+		    " 0x%llx, len %i, data=0x%016llx ]\n",
+		    (long long)relative_addr, len, (long long)idata);
+#endif
+
+	// ... and then treat the registers as 64-bit aligned:
+	switch (relative_addr & ~7) {
+	case MEC_MAC_CONTROL:	/*  0x00  */
+		if (writeflag)
+			mec_control_write(cpu, d, idata);
+		else {
+			/*  1 means "Revision 2" in hinv output, as per my O2. (1 + value?)  */
+			odata &= ~MEC_MAC_REVISION;
+			odata |= 1 << MEC_MAC_REVISION_SHIFT;
+		}
+		break;
+	case MEC_INT_STATUS:	/*  0x08  */
+		if (writeflag) {
+			/*  Clear bits on write:  (This is just a guess)  */
+			uint64_t writtenvalue = d->reg[MEC_INT_STATUS / sizeof(uint64_t)];
+
+			d->reg[MEC_INT_STATUS / sizeof(uint64_t)] =
+				 old_int_status
+				 & ~(writtenvalue & MEC_INT_STATUS_MASK);
+			debug("[ sgi_mec: write to MEC_INT_STATUS: "
+			    "0x%016llx ]\n", (long long)idata);
+		}
+		break;
+	case MEC_DMA_CONTROL:	/*  0x10  */
+		if (writeflag) {
+			debug("[ sgi_mec: write to MEC_DMA_CONTROL: "
+			    "0x%016llx ]\n", (long long)idata);
+			if (!(idata & MEC_DMA_TX_INT_ENABLE)) {
+				/*  This should apparently stop the
+				    TX Empty interrupt.  */
+				d->reg[MEC_INT_STATUS / sizeof(uint64_t)] &=
+				    ~MEC_INT_TX_EMPTY;
+			}
+		}
+		break;
+	case MEC_TX_ALIAS:	/*  0x20  */
+		if (writeflag) {
+			debug("[ sgi_mec: write to MEC_TX_ALIAS: "
+			    "0x%016llx ]\n", (long long)idata);
+		} else {
+			debug("[ sgi_mec: read from MEC_TX_ALIAS: "
+			    "0x%016llx ]\n", (long long)idata);
+			odata = d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)];
+		}
+		break;
+	case MEC_RX_ALIAS:	/*  0x28  */
+		if (writeflag)
+			debug("[ sgi_mec: write to MEC_RX_ALIAS: "
+			    "0x%016llx ]\n", (long long)idata);
+		break;
+	case MEC_TX_RING_PTR:		/*  0x30  */
+		if (writeflag) {
+			uint64_t writtenvalue = d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)];
+			writtenvalue &= MEC_TX_RING_WRITE_PTR;
+			d->reg[regnr] = (old_tx_ring_ptr & ~MEC_TX_RING_WRITE_PTR) | writtenvalue;
+
+			debug("[ sgi_mec: write to MEC_TX_RING_PTR: "
+			    "0x%016llx ]\n", (long long)idata);
+		}
+		break;
+	case MEC_PHY_DATA:	/*  0x60  */
+		{
+			int dev = (d->reg[MEC_PHY_ADDRESS / sizeof(uint64_t)] & MEC_PHY_ADDR_DEVICE) >> MEC_PHY_ADDR_DEVSHIFT;
+			int reg = d->reg[MEC_PHY_ADDRESS / sizeof(uint64_t)] & MEC_PHY_ADDR_REGISTER;
+
+			if (writeflag) {
+				debug("[ sgi_mec: write to MEC_PHY_DATA (dev %i, reg %i): "
+				    "0x%016llx ]\n",
+				    dev, reg, (long long)idata);
+			}
+			
+			odata = 0;
+
+			if (dev == 8) {
+				// https://dmesgd.nycbug.org/index.cgi?do=view&id=2828 says:
+				//	nsphy0 at mec0 phy 8: DP83840 10/100 media interface, rev. 0
+				//	nsphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
+				switch (reg) {
+				case MII_BMCR:		// 0
+					odata = BMCR_AUTOEN;
+					break;
+				case MII_BMSR:		// 1
+					odata = BMSR_100TXFDX | BMSR_100TXHDX |
+						BMSR_10TFDX | BMSR_10THDX |
+						BMSR_ANEG | BMSR_LINK;	// LINK means cable is connected
+					break;
+				case MII_PHYIDR1:	// 2
+					odata = 0x2000;	// To match NetBSD's "xxNATSEMI" value.
+					break;
+				case MII_PHYIDR2:	// 3
+					odata = 0x5c00;	// To match NetBSD's "xxNATSEMI" value.
+					break;
+				case 23:	// MII_NSPHY_PCR
+					odata = 0x20; // PCR_CIMDIS
+					break;
+				default:debugmsg(SUBSYS_DEVICE, "sgi_mec", VERBOSITY_WARNING,
+					    "UNIMPLEMENTED %s PHY register %i",
+						writeflag ? "write to" : "read from", reg);
+				}
+			}
+
+			if (!writeflag) {
+				debugmsg(SUBSYS_DEVICE, "sgi_mec", VERBOSITY_DEBUG,
+				    "read from MEC_PHY_DATA (dev %i, reg %i): "
+				    "0x%016llx", dev, reg, (long long)odata);
+			}
+		}
+		break;
+	case MEC_PHY_ADDRESS:	/*  0x68  */
+		if (writeflag)
+			debug("[ sgi_mec: write to MEC_PHY_ADDRESS: "
+			    "0x%016llx ]\n", (long long)idata);
+		break;
+	case MEC_PHY_READ_INITIATE:	/*  0x70  */
+		if (writeflag)
+			debug("[ sgi_mec: write to MEC_PHY_READ_INITIATE: "
+			    "0x%016llx ]\n", (long long)idata);
+		break;
+	case MEC_STATION:	/*  0xa0  */
+		if (writeflag)
+			debug("[ sgi_mec: setting the MAC address to "
+			    "%02x:%02x:%02x:%02x:%02x:%02x ]\n",
+			    (idata >> 40) & 255, (idata >> 32) & 255,
+			    (idata >> 24) & 255, (idata >> 16) & 255,
+			    (idata >>  8) & 255, (idata >>  0) & 255);
+		else
+			fatal("[ sgi_mec: reading the MAC address as "
+			    "%02x:%02x:%02x:%02x:%02x:%02x ]\n",
+			    (odata >> 40) & 255, (odata >> 32) & 255,
+			    (odata >> 24) & 255, (odata >> 16) & 255,
+			    (odata >>  8) & 255, (odata >>  0) & 255);
+		break;
+	case MEC_STATION_ALT:	/*  0xa8  */
+		if (writeflag)
+			debug("[ sgi_mec: setting the ALTERNATIVE MAC address"
+			    " to %02x:%02x:%02x:%02x:%02x:%02x ]\n",
+			    (idata >> 40) & 255, (idata >> 32) & 255,
+			    (idata >> 24) & 255, (idata >> 16) & 255,
+			    (idata >>  8) & 255, (idata >>  0) & 255);
+		else
+			debug("[ sgi_mec: reading the ALTERNATIVE MAC address"
+			    " as %02x:%02x:%02x:%02x:%02x:%02x ]\n",
+			    (odata >> 40) & 255, (odata >> 32) & 255,
+			    (odata >> 24) & 255, (odata >> 16) & 255,
+			    (odata >>  8) & 255, (odata >>  0) & 255);
+		break;
+	case MEC_MULTICAST:	/*  0xb0  */
+		if (writeflag)
+			debug("[ sgi_mec: write to MEC_MULTICAST: "
+			    "0x%016llx ]\n", (long long)idata);
+		break;
+	case MEC_TX_RING_BASE:	/*  0xb8  */
+		if (writeflag)
+			debug("[ sgi_mec: write to MEC_TX_RING_BASE: "
+			    "0x%016llx ]\n", (long long)idata);
+		break;
+	case MEC_MCL_RX_FIFO:	/*  0x100  */
+		if (writeflag) {
+			debug("[ sgi_mec: write to MEC_MCL_RX_FIFO: 0x"
+			    "%016llx ]\n", (long long)idata);
+			d->rx_addr[d->cur_rx_addr_index_write] = idata;
+			d->cur_rx_addr_index_write ++;
+			d->cur_rx_addr_index_write %= N_RX_ADDRESSES;
+		}
+		break;
+	default:
+		if (writeflag == MEM_WRITE)
+			debugmsg(SUBSYS_DEVICE, "sgi_mec", VERBOSITY_WARNING,
+			    "unimplemented write to address"
+			    " 0x%llx, data=0x%016llx",
+			    (long long)relative_addr, (long long)idata);
+		else
+			debugmsg(SUBSYS_DEVICE, "sgi_mec", VERBOSITY_WARNING,
+			    "unimplemented read from address"
+			    " 0x%llx", (long long)relative_addr);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+#ifdef MEC_DEBUG
+	if (writeflag == MEM_READ)
+		fatal("[ sgi_mec: read from address"
+		    " 0x%llx, len %i, data=0x%llx ]\n", (long long)relative_addr,
+		    	len, (long long)odata);
+#endif
+
+	dev_sgi_mec_tick(cpu, extra);
+
+	return 1;
+}
+
+
+/*
+ *  dev_sgi_mec_init():
+ */
+void dev_sgi_mec_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, char *irq_path, unsigned char *macaddr)
+{
+	char *name2;
+	size_t nlen = 55;
+	struct sgi_mec_data *d;
+
+	CHECK_ALLOCATION(d = (struct sgi_mec_data *) malloc(sizeof(struct sgi_mec_data)));
+	memset(d, 0, sizeof(struct sgi_mec_data));
+
+	INTERRUPT_CONNECT(irq_path, d->irq);
+	memcpy(d->nic.mac_address, macaddr, 6);
+	mec_reset(d);
+
+	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
+	snprintf(name2, nlen, "mec [%02x:%02x:%02x:%02x:%02x:%02x]",
+	    d->nic.mac_address[0], d->nic.mac_address[1],
+	    d->nic.mac_address[2], d->nic.mac_address[3],
+	    d->nic.mac_address[4], d->nic.mac_address[5]);
+
+	memory_device_register(mem, name2, baseaddr,
+	    DEV_SGI_MEC_LENGTH, dev_sgi_mec_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(machine, dev_sgi_mec_tick, d,
+	    MEC_TICK_SHIFT);
+
+	net_add_nic(machine->emul->net, &d->nic);
+}
+
+
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_mec.cc gxemul-0.7.0+dfsg/src/devices/dev_sgi_mec.cc
--- gxemul-0.6.2/src/devices/dev_sgi_mec.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_mec.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,696 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: SGI IP32 "mec" ethernet
- *
- *  Used by the SGI O2 emulation mode.
- *  Based on how NetBSD and OpenBSD use the hardware, just about enough to let
- *  those OSes boot with root-on-nfs.
- *
- *  http://www.openbsd.org/cgi-bin/cvsweb/src/sys/arch/sgi/dev/if_mec.c
- *
- *  TODO:
- *
- *	x)  tx and rx interrupts/ring/slot stuff
- *
- *  A note about word length for reads/writes:
- *
- *	NetBSD uses (at least) 64-bit reads/writes.
- *	OpenBSD uses both 32-bit and 64-bit reads/writes.
- *	The PROM uses (at least) 32-bit reads/writes and 16-bit reads (from
- *		offsets 0x34 and 0x36)!
- *
- *  Random googling reveals this NetBSD dmesg about the PHYs:
- *
- *	https://mail-index.netbsd.org/port-sgimips/2008/01/27/msg000043.html
- *
- *	mec0 at mace0 offset 0x280000 intr 3 intrmask 0x0: MAC-110 Ethernet, rev 1
- *	mec0: Ethernet address 08:00:69:0e:85:21
- *	nsphy0 at mec0 phy 8: DP83840 10/100 media interface, rev. 1
- *	nsphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_pci.h"
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "net.h"
-
-#include "thirdparty/if_mecreg.h"
-#include "thirdparty/mii.h"
-
-// #define debug fatal
-// #define MEC_DEBUG
-
-#define	MEC_TICK_SHIFT		14
-
-#define	MAX_TX_PACKET_LEN	1700
-#define	N_RX_ADDRESSES		16
-
-struct sgi_mec_data {
-	uint64_t	reg[DEV_SGI_MEC_LENGTH / sizeof(uint64_t)];
-
-	struct interrupt irq;
-	int		prev_asserted;
-
-	unsigned char	macaddr[6];
-
-	unsigned char	cur_tx_packet[MAX_TX_PACKET_LEN];
-	int		cur_tx_packet_len;
-
-	unsigned char	*cur_rx_packet;
-	int		cur_rx_packet_len;
-
-	uint64_t	rx_addr[N_RX_ADDRESSES];
-	int		cur_rx_addr_index_write;
-	int		cur_rx_addr_index;
-};
-
-
-/*
- *  mec_reset():
- */
-static void mec_reset(struct sgi_mec_data *d)
-{
-	if (d->cur_rx_packet != NULL)
-		free(d->cur_rx_packet);
-
-	memset(d->reg, 0, sizeof(d->reg));
-}
-
-
-/*
- *  mec_control_write():
- */
-static void mec_control_write(struct cpu *cpu, struct sgi_mec_data *d,
-	uint64_t x)
-{
-	if (x & MEC_MAC_CORE_RESET) {
-		debug("[ sgi_mec: CORE RESET ]\n");
-		mec_reset(d);
-	}
-}
-
-
-/*
- *  mec_try_rx():
- */
-static int mec_try_rx(struct cpu *cpu, struct sgi_mec_data *d)
-{
-	uint64_t base;
-	unsigned char data[8];
-	int i, res, retval = 0;
-
-	base = d->rx_addr[d->cur_rx_addr_index];
-	if (base & 0xfff)
-		fatal("[ mec_try_rx(): WARNING! lowest bits of base are "
-		    "non-zero (0x%3x). TODO ]\n", (int)(base & 0xfff));
-	base &= 0xfffff000ULL;
-	if (base == 0)
-		goto skip;
-
-	/*  printf("rx base = 0x%016llx\n", (long long)base);  */
-
-	/*  Read an rx descriptor from memory:  */
-	res = cpu->memory_rw(cpu, cpu->mem, base,
-	    &data[0], sizeof(data), MEM_READ, PHYSICAL);
-	if (!res)
-		return 0;
-
-	/*  Is this descriptor already in use?  */
-	if (data[0] & 0x80) {
-		/*  printf("INTERRUPT for base = 0x%x\n", (int)base);  */
-		goto skip_and_advance;
-	}
-
-	if (d->cur_rx_packet == NULL &&
-	    net_ethernet_rx_avail(cpu->machine->emul->net, d))
-		net_ethernet_rx(cpu->machine->emul->net, d,
-		    &d->cur_rx_packet, &d->cur_rx_packet_len);
-
-	if (d->cur_rx_packet == NULL)
-		goto skip;
-
-#if 0
-	printf("{ mec: rxdesc %i: ", d->cur_rx_addr_index);
-	for (i=0; i<sizeof(data); i++) {
-		if ((i & 3) == 0)
-			printf(" ");
-		printf("%02x", data[i]);
-	}
-	printf(" }\n");
-#endif
-
-	/*  Copy the packet data:  */
-	//printf("RX: ");
-	for (i=0; i<d->cur_rx_packet_len; i++) {
-		res = cpu->memory_rw(cpu, cpu->mem, base + 32 + i + 2,
-		    d->cur_rx_packet + i, 1, MEM_WRITE, PHYSICAL);
-		//printf(" %02x", d->cur_rx_packet[i]);
-	}
-	//printf("\n");
-
-#if 0
-	printf("RX: %i bytes, index %i, base = 0x%x\n",
-	    d->cur_rx_packet_len, d->cur_rx_addr_index, (int)base);
-#endif
-
-	/*  4 bytes of CRC at the end. Hm. TODO  */
-	d->cur_rx_packet_len += 4;
-
-	memset(data, 0, sizeof(data));
-	data[6] = (d->cur_rx_packet_len >> 8) & 255;
-	data[7] = d->cur_rx_packet_len & 255;
-	/*  TODO: lots of bits :-)  */
-	data[4] = 0x04;		/*  match MAC  */
-	data[0] = 0x80;		/*  0x80 = received.  */
-	res = cpu->memory_rw(cpu, cpu->mem, base,
-	    &data[0], sizeof(data), MEM_WRITE, PHYSICAL);
-
-	/*  Free the packet from memory:  */
-	free(d->cur_rx_packet);
-	d->cur_rx_packet = NULL;
-
-	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] |= MEC_INT_RX_THRESHOLD;
-skip_and_advance:
-	d->cur_rx_addr_index ++;
-	d->cur_rx_addr_index %= N_RX_ADDRESSES;
-	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] &= ~MEC_INT_RX_MCL_FIFO_ALIAS;
-	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] |=
-	    (d->cur_rx_addr_index & 0x1f) << 8;
-	retval = 1;
-
-skip:
-	return retval;
-}
-
-
-/*
- *  mec_try_tx():
- */
-static int mec_try_tx(struct cpu *cpu, struct sgi_mec_data *d)
-{
-	uint64_t base, addr, dma_base;
-	int tx_ring_ptr, ringread, ringwrite, res, i, j;
-	unsigned char data[32];
-	int len, start_offset, dma_ptr_nr, dma_len;
-
-	base = d->reg[MEC_TX_RING_BASE / sizeof(uint64_t)];
-	tx_ring_ptr = d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)];
-
-	if (base == 0)
-		return 0;
-
-	/*  printf("base = 0x%016llx\n", base);  */
-
-	ringread = tx_ring_ptr & MEC_TX_RING_READ_PTR;
-	ringwrite = tx_ring_ptr & MEC_TX_RING_WRITE_PTR;
-	ringread >>= 16;
-	/*  All done? Then abort.  */
-	if (ringread == ringwrite)
-		return 0;
-
-	tx_ring_ptr &= MEC_TX_RING_READ_PTR;
-	tx_ring_ptr >>= 16;
-
-	/*  Each tx descriptor (+ buffer) is 128 bytes:  */
-	addr = base + tx_ring_ptr*128;
-	res = cpu->memory_rw(cpu, cpu->mem, addr,
-	    &data[0], sizeof(data), MEM_READ, PHYSICAL);
-	if (!res)
-		return 0;
-
-	/*  Is this packet transmitted already?  */
-	if (data[0] & 0x80) {
-		fatal("[ mec_try_tx: tx_ring_ptr = %i, already"
-		    " transmitted? ]\n", tx_ring_ptr);
-		goto advance_tx;
-	}
-
-	len = data[6] * 256 + data[7];
-	start_offset = data[5] & 0x7f;
-
-	/*  Is this packet empty? Then don't transmit.  */
-	if (len == 0)
-		return 0;
-
-	/*  Hm. Is len one too little?  TODO  */
-	len ++;
-
-#if 0
-	printf("{ mec: txdesc %i: ", tx_ring_ptr);
-	for (i=0; i<sizeof(data); i++) {
-		if ((i & 3) == 0)
-			printf(" ");
-		printf("%02x", data[i]);
-	}
-	printf(" }\n");
-#endif
-	dma_ptr_nr = 0;
-
-	j = 0;
-	d->cur_tx_packet_len = len;
-
-	//printf("TX: ");
-	for (i=start_offset; i<start_offset+len; i++) {
-		unsigned char ch;
-
-		if ((i & 0x7f) == 0x00)
-			break;
-
-		res = cpu->memory_rw(cpu, cpu->mem, addr + i,
-		    &ch, sizeof(ch), MEM_READ, PHYSICAL);
-		//printf(" %02x", ch);
-
-		d->cur_tx_packet[j++] = ch;
-		if (j >= MAX_TX_PACKET_LEN) {
-			fatal("[ mec_try_tx: packet too large? ]\n");
-			break;
-		}
-	}
-	//printf("\n");
-
-	if (j < len) {
-		/*  Continue with DMA:  */
-		for (;;) {
-			dma_ptr_nr ++;
-			if (dma_ptr_nr >= 4)
-				break;
-			if (!(data[4] & (0x01 << dma_ptr_nr)))
-				break;
-			dma_base = (data[dma_ptr_nr * 8 + 4] << 24)
-			         + (data[dma_ptr_nr * 8 + 5] << 16)
-			         + (data[dma_ptr_nr * 8 + 6] <<  8)
-			         + (data[dma_ptr_nr * 8 + 7]);
-			dma_base &= 0xfffffff8ULL;
-			dma_len = (data[dma_ptr_nr * 8 + 2] << 8)
-			        + (data[dma_ptr_nr * 8 + 3]) + 1;
-
-			/*  printf("dma_base = %08x, dma_len = %i\n",
-			    (int)dma_base, dma_len);  */
-
-			while (dma_len > 0) {
-				unsigned char ch;
-				res = cpu->memory_rw(cpu, cpu->mem, dma_base,
-				    &ch, sizeof(ch), MEM_READ, PHYSICAL);
-				/*  printf(" %02x", ch);  */
-
-				d->cur_tx_packet[j++] = ch;
-				if (j >= MAX_TX_PACKET_LEN) {
-					fatal("[ mec_try_tx: packet too large?"
-					    " ]\n");
-					break;
-				}
-				dma_base ++;
-				dma_len --;
-			}
-		}
-	}
-
-	if (j < len)
-		fatal("[ mec_try_tx: not enough data? ]\n");
-
-	net_ethernet_tx(cpu->machine->emul->net, d,
-	    d->cur_tx_packet, d->cur_tx_packet_len);
-
-	/*  see openbsd's if_mec.c for details  */
-	if (data[4] & 0x01) {
-		d->reg[MEC_INT_STATUS / sizeof(uint64_t)] |=
-		    MEC_INT_TX_PACKET_SENT;
-	}
-	memset(data, 0, 6);	/*  last 2 bytes are len  */
-	data[0] = 0x80;
-	data[5] = 0x80;
-
-	res = cpu->memory_rw(cpu, cpu->mem, addr,
-	    &data[0], sizeof(data), MEM_WRITE, PHYSICAL);
-
-	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] |= MEC_INT_TX_EMPTY;
-	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] |= MEC_INT_TX_PACKET_SENT;
-
-advance_tx:
-	/*  Advance the ring Read ptr.  */
-	tx_ring_ptr = d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)];
-	ringread = tx_ring_ptr & MEC_TX_RING_READ_PTR;
-	ringwrite = tx_ring_ptr & MEC_TX_RING_WRITE_PTR;
-
-	ringread = (ringread >> 16) + 1;
-	ringread &= 63;
-	ringread <<= 16;
-
-	d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)] =
-	    (ringwrite & MEC_TX_RING_WRITE_PTR) |
-	    (ringread & MEC_TX_RING_READ_PTR);
-
-	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] &=
-	    ~MEC_INT_TX_RING_BUFFER_ALIAS;
-	d->reg[MEC_INT_STATUS / sizeof(uint64_t)] |=
-	    (d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)] &
-	    MEC_INT_TX_RING_BUFFER_ALIAS);
-
-	return 1;
-}
-
-
-DEVICE_TICK(sgi_mec)
-{
-	struct sgi_mec_data *d = (struct sgi_mec_data *) extra;
-	int n = 0;
-
-	while (mec_try_tx(cpu, d))
-		;
-
-	while (mec_try_rx(cpu, d) && n < 16)
-		n++;
-
-	/*  Interrupts:  (TODO: only when enabled)  */
-	int asserted = !!(d->reg[MEC_INT_STATUS / sizeof(uint64_t)] & MEC_INT_STATUS_MASK);
-
-	if (asserted && !d->prev_asserted)
-		INTERRUPT_ASSERT(d->irq);
-	else if (!asserted && d->prev_asserted)
-		INTERRUPT_DEASSERT(d->irq);
-
-	d->prev_asserted = asserted;
-}
-
-
-DEVICE_ACCESS(sgi_mec)
-{
-	struct sgi_mec_data *d = (struct sgi_mec_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-
-	uint64_t old_int_status = d->reg[MEC_INT_STATUS / sizeof(uint64_t)];
-	uint64_t old_tx_ring_ptr = d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)];
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	regnr = relative_addr / sizeof(uint64_t);
-
-	if ((relative_addr & ~7) == MEC_TX_RING_PTR_ALIAS)
-		relative_addr -= 8;
-
-	// Support both 32-bit and 64-bit big-endian loads and stores...
-	if (len == sizeof(uint64_t)) {
-		if (writeflag == MEM_WRITE)
-			d->reg[regnr] = idata;
-		else
-			odata = d->reg[regnr];
-	} else if (len == sizeof(uint32_t)) {
-		if (writeflag == MEM_WRITE) {
-			if (relative_addr & 4)
-				d->reg[regnr] = (d->reg[regnr] & ~0xffffffffULL) | (uint32_t)idata;
-			else
-				d->reg[regnr] = (d->reg[regnr] & 0xffffffffULL) | ((uint64_t)idata << 32ULL);
-		} else {
-			odata = d->reg[regnr];
-			if (relative_addr & 4)
-				odata = (int32_t)odata;
-			else
-				odata = (odata >> 32ULL);
-		}
-	} else if (len == sizeof(uint16_t)) {
-		if (writeflag == MEM_WRITE) {
-			fatal("[ sgi_mec: unimplemented %s len %i (addr 0x%x) ]\n",
-				writeflag ? "write" : "read", len, (long long)relative_addr);
-		} else if ((relative_addr & 7) == 4) {
-			odata = d->reg[regnr];
-			odata = (uint16_t)(odata >> 16);
-		} else if ((relative_addr & 7) == 6) {
-			odata = d->reg[regnr];
-			odata = (uint16_t)odata;
-		} else {
-			fatal("[ sgi_mec: unimplemented %s len %i (addr 0x%x) ]\n",
-				writeflag ? "write" : "read", len, (long long)relative_addr);
-		}
-	} else {
-		fatal("[ sgi_mec: unimplemented %s len %i (addr 0x%x) ]\n",
-			writeflag ? "write" : "read", len, (long long)relative_addr);
-	}
-
-#ifdef MEC_DEBUG
-	if (writeflag == MEM_WRITE)
-		fatal("[ sgi_mec: write to address"
-		    " 0x%llx, len %i, data=0x%016llx ]\n",
-		    (long long)relative_addr, len, (long long)idata);
-#endif
-
-	// ... and then treat the registers as 64-bit aligned:
-	switch (relative_addr & ~7) {
-	case MEC_MAC_CONTROL:	/*  0x00  */
-		if (writeflag)
-			mec_control_write(cpu, d, idata);
-		else {
-			/*  1 means "Revision 2" in hinv output, as per my O2. (1 + value?)  */
-			odata &= ~MEC_MAC_REVISION;
-			odata |= 1 << MEC_MAC_REVISION_SHIFT;
-		}
-		break;
-	case MEC_INT_STATUS:	/*  0x08  */
-		if (writeflag) {
-			/*  Clear bits on write:  (This is just a guess)  */
-			uint64_t writtenvalue = d->reg[MEC_INT_STATUS / sizeof(uint64_t)];
-
-			d->reg[MEC_INT_STATUS / sizeof(uint64_t)] =
-				 old_int_status
-				 & ~(writtenvalue & MEC_INT_STATUS_MASK);
-			debug("[ sgi_mec: write to MEC_INT_STATUS: "
-			    "0x%016llx ]\n", (long long)idata);
-		}
-		break;
-	case MEC_DMA_CONTROL:	/*  0x10  */
-		if (writeflag) {
-			debug("[ sgi_mec: write to MEC_DMA_CONTROL: "
-			    "0x%016llx ]\n", (long long)idata);
-			if (!(idata & MEC_DMA_TX_INT_ENABLE)) {
-				/*  This should apparently stop the
-				    TX Empty interrupt.  */
-				d->reg[MEC_INT_STATUS / sizeof(uint64_t)] &=
-				    ~MEC_INT_TX_EMPTY;
-			}
-		}
-		break;
-	case MEC_TX_ALIAS:	/*  0x20  */
-		if (writeflag) {
-			debug("[ sgi_mec: write to MEC_TX_ALIAS: "
-			    "0x%016llx ]\n", (long long)idata);
-		} else {
-			debug("[ sgi_mec: read from MEC_TX_ALIAS: "
-			    "0x%016llx ]\n", (long long)idata);
-			odata = d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)];
-		}
-		break;
-	case MEC_RX_ALIAS:	/*  0x28  */
-		if (writeflag)
-			debug("[ sgi_mec: write to MEC_RX_ALIAS: "
-			    "0x%016llx ]\n", (long long)idata);
-		break;
-	case MEC_TX_RING_PTR:		/*  0x30  */
-		if (writeflag) {
-			uint64_t writtenvalue = d->reg[MEC_TX_RING_PTR / sizeof(uint64_t)];
-			writtenvalue &= MEC_TX_RING_WRITE_PTR;
-			d->reg[regnr] = (old_tx_ring_ptr & ~MEC_TX_RING_WRITE_PTR) | writtenvalue;
-
-			debug("[ sgi_mec: write to MEC_TX_RING_PTR: "
-			    "0x%016llx ]\n", (long long)idata);
-		}
-		break;
-	case MEC_PHY_DATA:	/*  0x60  */
-		{
-			int dev = (d->reg[MEC_PHY_ADDRESS / sizeof(uint64_t)] & MEC_PHY_ADDR_DEVICE) >> MEC_PHY_ADDR_DEVSHIFT;
-			int reg = d->reg[MEC_PHY_ADDRESS / sizeof(uint64_t)] & MEC_PHY_ADDR_REGISTER;
-
-			if (writeflag) {
-				debug("[ sgi_mec: write to MEC_PHY_DATA (dev %i, reg %i): "
-				    "0x%016llx ]\n",
-				    dev, reg, (long long)idata);
-			}
-			
-			odata = 0;
-
-			if (dev == 8) {
-				// https://dmesgd.nycbug.org/index.cgi?do=view&id=2828 says:
-				//	nsphy0 at mec0 phy 8: DP83840 10/100 media interface, rev. 0
-				//	nsphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
-				switch (reg) {
-				case MII_BMCR:		// 0
-					odata = BMCR_AUTOEN;
-					break;
-				case MII_BMSR:		// 1
-					odata = BMSR_100TXFDX | BMSR_100TXHDX |
-						BMSR_10TFDX | BMSR_10THDX |
-						BMSR_ANEG | BMSR_LINK;	// LINK means cable is connected
-					break;
-				case MII_PHYIDR1:	// 2
-					odata = 0x2000;	// To match NetBSD's "xxNATSEMI" value.
-					break;
-				case MII_PHYIDR2:	// 3
-					odata = 0x5c00;	// To match NetBSD's "xxNATSEMI" value.
-					break;
-				case 23:	// MII_NSPHY_PCR
-					odata = 0x20; // PCR_CIMDIS
-					break;
-				default:
-					fatal("[ sgi_mec: unimplemented %s PHY register %i ]\n",
-						writeflag ? "write to" : "read from", reg);
-				}
-			}
-
-			if (!writeflag) {
-				debug("[ sgi_mec: read from MEC_PHY_DATA (dev %i, reg %i): "
-				    "0x%016llx ]\n",
-				    dev, reg, (long long)odata);
-			}
-		}
-		break;
-	case MEC_PHY_ADDRESS:	/*  0x68  */
-		if (writeflag)
-			debug("[ sgi_mec: write to MEC_PHY_ADDRESS: "
-			    "0x%016llx ]\n", (long long)idata);
-		break;
-	case MEC_PHY_READ_INITIATE:	/*  0x70  */
-		if (writeflag)
-			debug("[ sgi_mec: write to MEC_PHY_READ_INITIATE: "
-			    "0x%016llx ]\n", (long long)idata);
-		break;
-	case MEC_STATION:	/*  0xa0  */
-		if (writeflag)
-			debug("[ sgi_mec: setting the MAC address to "
-			    "%02x:%02x:%02x:%02x:%02x:%02x ]\n",
-			    (idata >> 40) & 255, (idata >> 32) & 255,
-			    (idata >> 24) & 255, (idata >> 16) & 255,
-			    (idata >>  8) & 255, (idata >>  0) & 255);
-		else
-			fatal("[ sgi_mec: reading the MAC address as "
-			    "%02x:%02x:%02x:%02x:%02x:%02x ]\n",
-			    (odata >> 40) & 255, (odata >> 32) & 255,
-			    (odata >> 24) & 255, (odata >> 16) & 255,
-			    (odata >>  8) & 255, (odata >>  0) & 255);
-		break;
-	case MEC_STATION_ALT:	/*  0xa8  */
-		if (writeflag)
-			debug("[ sgi_mec: setting the ALTERNATIVE MAC address"
-			    " to %02x:%02x:%02x:%02x:%02x:%02x ]\n",
-			    (idata >> 40) & 255, (idata >> 32) & 255,
-			    (idata >> 24) & 255, (idata >> 16) & 255,
-			    (idata >>  8) & 255, (idata >>  0) & 255);
-		else
-			debug("[ sgi_mec: reading the ALTERNATIVE MAC address"
-			    " as %02x:%02x:%02x:%02x:%02x:%02x ]\n",
-			    (odata >> 40) & 255, (odata >> 32) & 255,
-			    (odata >> 24) & 255, (odata >> 16) & 255,
-			    (odata >>  8) & 255, (odata >>  0) & 255);
-		break;
-	case MEC_MULTICAST:	/*  0xb0  */
-		if (writeflag)
-			debug("[ sgi_mec: write to MEC_MULTICAST: "
-			    "0x%016llx ]\n", (long long)idata);
-		break;
-	case MEC_TX_RING_BASE:	/*  0xb8  */
-		if (writeflag)
-			debug("[ sgi_mec: write to MEC_TX_RING_BASE: "
-			    "0x%016llx ]\n", (long long)idata);
-		break;
-	case MEC_MCL_RX_FIFO:	/*  0x100  */
-		if (writeflag) {
-			debug("[ sgi_mec: write to MEC_MCL_RX_FIFO: 0x"
-			    "%016llx ]\n", (long long)idata);
-			d->rx_addr[d->cur_rx_addr_index_write] = idata;
-			d->cur_rx_addr_index_write ++;
-			d->cur_rx_addr_index_write %= N_RX_ADDRESSES;
-		}
-		break;
-	default:
-		if (writeflag == MEM_WRITE)
-			fatal("[ sgi_mec: unimplemented write to address"
-			    " 0x%llx, data=0x%016llx ]\n",
-			    (long long)relative_addr, (long long)idata);
-		else
-			fatal("[ sgi_mec: unimplemented read from address"
-			    " 0x%llx ]\n", (long long)relative_addr);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-#ifdef MEC_DEBUG
-	if (writeflag == MEM_READ)
-		fatal("[ sgi_mec: read from address"
-		    " 0x%llx, len %i, data=0x%llx ]\n", (long long)relative_addr,
-		    	len, (long long)odata);
-#endif
-
-	dev_sgi_mec_tick(cpu, extra);
-
-	return 1;
-}
-
-
-/*
- *  dev_sgi_mec_init():
- */
-void dev_sgi_mec_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, char *irq_path, unsigned char *macaddr)
-{
-	char *name2;
-	size_t nlen = 55;
-	struct sgi_mec_data *d;
-
-	CHECK_ALLOCATION(d = (struct sgi_mec_data *) malloc(sizeof(struct sgi_mec_data)));
-	memset(d, 0, sizeof(struct sgi_mec_data));
-
-	INTERRUPT_CONNECT(irq_path, d->irq);
-	memcpy(d->macaddr, macaddr, 6);
-	mec_reset(d);
-
-	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
-	snprintf(name2, nlen, "mec [%02x:%02x:%02x:%02x:%02x:%02x]",
-	    d->macaddr[0], d->macaddr[1], d->macaddr[2],
-	    d->macaddr[3], d->macaddr[4], d->macaddr[5]);
-
-	memory_device_register(mem, name2, baseaddr,
-	    DEV_SGI_MEC_LENGTH, dev_sgi_mec_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(machine, dev_sgi_mec_tick, d,
-	    MEC_TICK_SHIFT);
-
-	net_add_nic(machine->emul->net, d, macaddr);
-}
-
-
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_re.c gxemul-0.7.0+dfsg/src/devices/dev_sgi_re.c
--- gxemul-0.6.2/src/devices/dev_sgi_re.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_re.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1337 @@
+/*
+ *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: SGI O2 "Rendering Engine"
+ *
+ *  Guesswork, based on how Linux, NetBSD, and OpenBSD use the graphics on
+ *  the SGI O2. Using NetBSD terminology (from crmfbreg.h):
+ *
+ *  dev_sgi_re.cc (THIS FILE):
+ *	0x15001000	rendering engine (TLBs)
+ *	0x15002000	drawing engine
+ *	0x15003000	memory transfer engine
+ *	0x15004000	status registers for drawing engine
+ *
+ *  dev_sgi_gbe.cc:
+ *	0x16000000	crm (or GBE) framebuffer control / video output
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/crmfbreg.h"
+#include "thirdparty/sgi_gl.h"
+
+
+struct sgi_re_data {
+	// Rendering engine registers:
+	uint16_t	re_tlb_a[256];
+	uint16_t	re_tlb_b[256];
+	uint16_t	re_tlb_c[256];
+	uint16_t	re_tex[112];
+	// todo: clip_ids registers.
+	uint32_t	re_linear_a[32];
+	uint32_t	re_linear_b[32];
+
+	// Drawing engine registers:
+	uint32_t	de_reg[DEV_SGI_DE_LENGTH / sizeof(uint32_t)];
+
+	// Memory transfer engine registers:
+	uint32_t	mte_reg[DEV_SGI_MTE_LENGTH / sizeof(uint32_t)];
+};
+
+
+/*
+ *  horrible_getputpixel():
+ *
+ *  This routine gets/puts a pixel in one of the tiles, from the perspective of
+ *  the rendering/drawing engine. Given x and y, it figures out which tile
+ *  number it is, and then finally does a slow read/write to get/put the pixel
+ *  at the correct sub-coordinates within the tile.
+ *
+ *  Tiles are always 512 _bytes_ wide, and 128 pixels high. For 32-bit color
+ *  modes, for example, that means 128 x 128 pixels.
+ *
+ *  For "linear" modes, y is ignored and x is an offset to select which linear
+ *  TLB entry to use.
+ */
+void horrible_getputpixel(int put, struct cpu* cpu, struct sgi_re_data* d,
+	int x, int y, uint32_t* color, int mode)
+{
+	uint32_t color_mode = mode & DE_MODE_TYPE_MASK;
+	int bufdepth = 1 << ((mode >> 8) & 3); 
+
+	// dst_mode (see NetBSD's crmfbreg.h):
+	// #define DE_MODE_TLB_A           0x00000000
+	// #define DE_MODE_TLB_B           0x00000400
+	// #define DE_MODE_TLB_C           0x00000800
+	// #define DE_MODE_LIN_A           0x00001000
+	// #define DE_MODE_LIN_B           0x00001400
+	uint32_t tlb_mode = (mode >> 10) & 0x7;
+	int linear = tlb_mode > 3;
+
+	if (!linear && (x < 0 || y < 0 || x >= 2048 || y >= 2048))
+		return;
+
+	int tilewidth_in_pixels = 512 / bufdepth;
+	
+	int tile_nr_x = x / tilewidth_in_pixels;
+	int tile_nr_y = y >> 7;
+
+	unsigned int tile_nr = tile_nr_y * 16 + tile_nr_x;
+
+	y &= 127;
+	int xofs = (x % tilewidth_in_pixels) * bufdepth;
+	int ofs = 512 * y + xofs;
+
+	uint32_t tileptr = 0;
+
+	switch (tlb_mode) {
+	case 0:	tileptr = d->re_tlb_a[tile_nr] << 16;
+		break;
+	case 1:	tileptr = d->re_tlb_b[tile_nr] << 16;
+		break;
+	case 2:	tileptr = d->re_tlb_c[tile_nr] << 16;
+		break;
+	case 4:	tile_nr = x >> 12;
+		if (tile_nr >= 32)
+			return;
+		tileptr = 0x80000000 | (d->re_linear_a[tile_nr] << 12);
+		ofs = x & 4095;
+		// TODO... probably not correct!
+		// printf("tileptr = %08x x = %i y = %i tile_nr = %i ofs = %i\n", tileptr, x, y, tile_nr, ofs);
+		break;
+	default:fatal("unimplemented dst_mode %i for horrible_getputpixel (%s), x=%i y=%i\n",
+			mode, put ? "put" : "get", x, y);
+		// exit(1);
+		*color = random();
+		return;
+	}
+
+	// The highest bit seems to be set for a "valid" tile pointer.
+	if (!(tileptr & 0x80000000)) {
+		//printf("dst_mode %i, tile_nr = %i,  tileptr = 0x%llx\n", dst_mode, tile_nr, (long long)tileptr);
+		//fatal("sgi gbe horrible_getputpixel: unexpected non-set high bit of tileptr?\n");
+		//exit(1);
+		return;
+	}
+	
+	tileptr &= ~0x80000000;
+
+	uint8_t buf[4];
+	if (put) {
+		switch (color_mode) {
+		case DE_MODE_TYPE_CI:
+			buf[0] = *color;
+			break;
+		case DE_MODE_TYPE_RGB:
+			buf[0] = *color >> 24;
+			buf[1] = *color >> 16;
+			buf[2] = *color >> 8;
+			buf[3] = 0;
+			break;
+		case DE_MODE_TYPE_RGBA:
+			buf[0] = *color >> 24;
+			buf[1] = *color >> 16;
+			buf[2] = *color >> 8;
+			buf[3] = *color;
+			break;
+		case DE_MODE_TYPE_ABGR:
+			buf[0] = *color;
+			buf[1] = *color >> 8;
+			buf[2] = *color >> 16;
+			buf[3] = *color >> 24;
+			break;
+		default:buf[0] = random();
+			buf[1] = random();
+			buf[2] = random();
+			buf[3] = random();
+			// TODO.
+			fatal("[ put: color mode = 0x%x ]\n", color_mode);
+		}
+
+		cpu->memory_rw(cpu, cpu->mem, tileptr + ofs,
+		    buf, bufdepth, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
+	} else {
+		cpu->memory_rw(cpu, cpu->mem, tileptr + ofs,
+		    buf, bufdepth, MEM_READ, NO_EXCEPTIONS | PHYSICAL);
+
+		switch (color_mode) {
+		case DE_MODE_TYPE_CI:
+			*color = buf[0];
+			break;
+		case DE_MODE_TYPE_RGB:
+			*color = (buf[1] << 24) + (buf[2] << 16) + (buf[3] << 8);
+			break;
+		case DE_MODE_TYPE_RGBA:
+			*color = (buf[0] << 24) + (buf[1] << 16) + (buf[2] << 8) + buf[3];
+			break;
+		case DE_MODE_TYPE_ABGR:
+			*color = (buf[3] << 24) + (buf[2] << 16) + (buf[1] << 8) + buf[0];
+			break;
+		default:// Read "raw" 32-bit value:
+			*color = (buf[3] << 24) + (buf[2] << 16) + (buf[1] << 8) + buf[0];
+			fatal("[ get: color mode = 0x%x ]\n", color_mode);
+		}
+	}
+}
+
+
+/*
+ *  SGI "re", NetBSD sources describes it as a "rendering engine".
+ */
+
+DEVICE_ACCESS(sgi_re)
+{
+	struct sgi_re_data *d = (struct sgi_re_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	idata = memory_readmax64(cpu, data, len);
+
+	relative_addr += 0x1000;
+
+	if (relative_addr >= CRIME_RE_TLB_A && relative_addr < CRIME_RE_TLB_B) {
+		if (len != 8) {
+			fatal("TODO: unimplemented len=%i for CRIME_RE_TLB_A\n", len);
+			exit(1);
+		}
+
+		if (writeflag == MEM_WRITE) {
+			int tlbi = ((relative_addr & 0x1ff) >> 1) & 0xff;
+			for (size_t hwi = 0; hwi < len; hwi += sizeof(uint16_t)) {
+				d->re_tlb_a[tlbi] = data[hwi]*256 + data[hwi+1];
+				debug("d->re_tlb_a[%i] = 0x%04x\n", tlbi, d->re_tlb_a[tlbi]);
+				tlbi++;
+			}
+		} else {
+			fatal("TODO: read from CRIME_RE_TLB_A\n");
+			exit(1);
+		}
+	} else if (relative_addr >= CRIME_RE_TLB_B && relative_addr < CRIME_RE_TLB_C) {
+		if (len != 8) {
+			fatal("TODO: unimplemented len=%i for CRIME_RE_TLB_B\n", len);
+			exit(1);
+		}
+
+		if (writeflag == MEM_WRITE) {
+			int tlbi = ((relative_addr & 0x1ff) >> 1) & 0xff;
+			for (size_t hwi = 0; hwi < len; hwi += sizeof(uint16_t)) {
+				d->re_tlb_b[tlbi] = data[hwi]*256 + data[hwi+1];
+				debug("d->re_tlb_b[%i] = 0x%04x\n", tlbi, d->re_tlb_b[tlbi]);
+				tlbi++;
+			}
+		} else {
+			fatal("TODO: read from CRIME_RE_TLB_B\n");
+			exit(1);
+		}
+	} else if (relative_addr >= CRIME_RE_TLB_C && relative_addr < CRIME_RE_TLB_C + 0x200) {
+		if (len != 8) {
+			fatal("TODO: unimplemented len=%i for CRIME_RE_TLB_C\n", len);
+			exit(1);
+		}
+
+		if (writeflag == MEM_WRITE) {
+			int tlbi = ((relative_addr & 0x1ff) >> 1) & 0xff;
+			for (size_t hwi = 0; hwi < len; hwi += sizeof(uint16_t)) {
+				d->re_tlb_c[tlbi] = data[hwi]*256 + data[hwi+1];
+				debug("d->re_tlb_c[%i] = 0x%04x\n", tlbi, d->re_tlb_c[tlbi]);
+				tlbi++;
+			}
+		} else {
+			fatal("TODO: read from CRIME_RE_TLB_C\n");
+			exit(1);
+		}
+	} else if (relative_addr >= CRIME_RE_TEX && relative_addr < CRIME_RE_TEX + 0xe0) {
+		if (len != 8) {
+			fatal("TODO: unimplemented len=%i for CRIME_RE_TEX\n", len);
+			exit(1);
+		}
+
+		if (writeflag == MEM_WRITE) {
+			int tlbi = ((relative_addr & 0xff) >> 3) & 0xff;
+			for (size_t hwi = 0; hwi < len; hwi += sizeof(uint16_t)) {
+				d->re_tex[tlbi] = data[hwi]*256 + data[hwi+1];
+				debug("d->re_tex[%i] = 0x%04x\n", tlbi, d->re_tex[tlbi]);
+				tlbi++;
+			}
+		} else {
+			fatal("TODO: read from CRIME_RE_TEX\n");
+			exit(1);
+		}
+	} else if (relative_addr >= CRIME_RE_LINEAR_A && relative_addr < CRIME_RE_LINEAR_A + 0x80) {
+		if (len != 8) {
+			fatal("TODO: unimplemented len=%i for CRIME_RE_LINEAR_A\n", len);
+			exit(1);
+		}
+
+		if (writeflag == MEM_WRITE) {
+			/*
+			 *  Very interesting. NetBSD writes stuff such as:
+			 *
+			 *  CRIME_RE_LINEAR_A IDATA = 8000173080001731
+			 *  CRIME_RE_LINEAR_A IDATA = 8000173280001733
+			 *  CRIME_RE_LINEAR_A IDATA = 8000173480001735
+			 *  ...
+			 *
+			 *  but the PROM writes something which looks like wrongly
+			 *  32-bit sign-extended words:
+			 *
+			 *  CRIME_RE_LINEAR_A IDATA = ffffffff80040001
+			 *  CRIME_RE_LINEAR_A IDATA = ffffffff80040003
+			 *  CRIME_RE_LINEAR_A IDATA = ffffffff80040005
+			 *  ...
+			 *
+			 *  followed by
+			 *  [ sgi_mte: STARTING TRANSFER: mode=0x00000011
+			 *    dst0=0x0000000040000000, dst1=0x0000000040007fff
+			 *    (length 0x8000), dst_y_step=0 bg=0x0, bytemask=0xffffffff ]
+			 *
+			 *  indicating that it really meant to put both 0x80040000
+			 *  and 0x80040001 into the first LINEAR_A entry.
+			 *
+			 *  The first guess would be a bug in the implementation of
+			 *  one or more instructions in the emulator while coming up
+			 *  with those values, but debugging the PROM so far has NOT
+			 *  revealed any such bug. It may even be that the PROM code
+			 *  is buggy (?) and never really set the LINEAR entries
+			 *  correctly. Perhaps the hardware simply ignores the
+			 *  weird values and does not fill it (using the MTE)
+			 *  when asked to.
+			 */
+			// printf("CRIME_RE_LINEAR_A IDATA = %016llx\n", (long long)idata);
+			int tlbi = ((relative_addr & 0x7f) >> 2) & 0x1f;
+			d->re_linear_a[tlbi] = idata >> 32ULL;
+			d->re_linear_a[tlbi+1] = idata;
+			debug("[ d->re_linear_a[%i] = 0x%08x, [%i] = 0x%08x ]\n",
+				tlbi, d->re_linear_a[tlbi], tlbi+1, d->re_linear_a[tlbi+1]);
+		} else {
+			fatal("TODO: read from CRIME_RE_LINEAR_A\n");
+			exit(1);
+		}
+	} else if (relative_addr >= CRIME_RE_LINEAR_B && relative_addr < CRIME_RE_LINEAR_B + 0x80) {
+		if (len != 8) {
+			fatal("TODO: unimplemented len=%i for CRIME_RE_LINEAR_B\n", len);
+			exit(1);
+		}
+
+		if (writeflag == MEM_WRITE) {
+			int tlbi = ((relative_addr & 0x7f) >> 2) & 0x1f;
+			d->re_linear_b[tlbi] = idata >> 32ULL;
+			d->re_linear_b[tlbi+1] = idata;
+			debug("[ d->re_linear_b[%i] = 0x%08x, [%i] = 0x%08x ]\n",
+				tlbi, d->re_linear_b[tlbi], tlbi+1, d->re_linear_b[tlbi+1]);
+		} else {
+			fatal("TODO: read from CRIME_RE_LINEAR_B\n");
+			exit(1);
+		}
+	} else {
+		if (writeflag == MEM_WRITE)
+			fatal("[ sgi_re: unimplemented write to "
+			    "address 0x%llx, data=0x%016llx ]\n",
+			    (long long)relative_addr, (long long)idata);
+		else
+			fatal("[ sgi_re: unimplemented read from address"
+			    " 0x%llx ]\n", (long long)relative_addr);
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_sgi_re_init():
+ */
+void dev_sgi_re_init(struct machine *machine, struct memory *mem, uint64_t baseaddr)
+{
+	struct sgi_re_data *d;
+
+	CHECK_ALLOCATION(d = (struct sgi_re_data *) malloc(sizeof(struct sgi_re_data)));
+	memset(d, 0, sizeof(struct sgi_re_data));
+
+	memory_device_register(mem, "sgi_re", baseaddr + 0x1000, DEV_SGI_RE_LENGTH,
+	    dev_sgi_re_access, d, DM_DEFAULT, NULL);
+
+	dev_sgi_de_init(mem, baseaddr + 0x2000, d);
+	dev_sgi_mte_init(mem, baseaddr + 0x3000, d);
+	dev_sgi_de_status_init(mem, baseaddr + 0x4000, d);
+}
+
+
+
+/****************************************************************************/
+
+/*
+ *  SGI "de", NetBSD sources describes it as a "drawing engine".
+ */
+
+void draw_primitive(struct cpu* cpu, struct sgi_re_data *d)
+{
+	uint32_t op = d->de_reg[(CRIME_DE_PRIMITIVE - 0x2000) / sizeof(uint32_t)];
+	uint32_t drawmode = d->de_reg[(CRIME_DE_DRAWMODE - 0x2000) / sizeof(uint32_t)];
+	uint32_t dst_mode = d->de_reg[(CRIME_DE_MODE_DST - 0x2000) / sizeof(uint32_t)];
+	uint32_t src_mode = d->de_reg[(CRIME_DE_MODE_SRC - 0x2000) / sizeof(uint32_t)];
+	uint32_t fg = d->de_reg[(CRIME_DE_FG - 0x2000) / sizeof(uint32_t)];
+	uint32_t bg = d->de_reg[(CRIME_DE_BG - 0x2000) / sizeof(uint32_t)];
+	uint32_t rop = d->de_reg[(CRIME_DE_ROP - 0x2000) / sizeof(uint32_t)];
+
+	uint32_t stipple_mode = d->de_reg[(CRIME_DE_STIPPLE_MODE - 0x2000) / sizeof(uint32_t)];
+	uint32_t pattern = d->de_reg[(CRIME_DE_STIPPLE_PAT - 0x2000) / sizeof(uint32_t)];
+	int nr_of_bits_to_strip_to_the_left = (stipple_mode >> DE_STIP_STRTIDX_SHIFT) & 31;
+	int nr_of_bits_to_strip_to_the_right = 31 - ((stipple_mode >> DE_STIP_MAXIDX_SHIFT) & 31);
+	pattern >>= nr_of_bits_to_strip_to_the_right;
+	pattern <<= nr_of_bits_to_strip_to_the_right;
+	pattern <<= nr_of_bits_to_strip_to_the_left;
+
+	int nr_of_bits_in_the_middle = 32 - nr_of_bits_to_strip_to_the_left - nr_of_bits_to_strip_to_the_right;
+
+	if (stipple_mode & 0xe0e0ffff)
+		fatal("[ sgi_de: UNIMPLEMENTED stipple_mode bits: 0x%08x ]\n", stipple_mode);
+
+	uint32_t x1 = (d->de_reg[(CRIME_DE_X_VERTEX_0 - 0x2000) / sizeof(uint32_t)] >> 16) & 0x7ff;
+	uint32_t y1 = d->de_reg[(CRIME_DE_X_VERTEX_0 - 0x2000) / sizeof(uint32_t)]& 0x7ff;
+	uint32_t x2 = (d->de_reg[(CRIME_DE_X_VERTEX_1 - 0x2000) / sizeof(uint32_t)] >> 16) & 0x7ff;
+	uint32_t y2 = d->de_reg[(CRIME_DE_X_VERTEX_1 - 0x2000) / sizeof(uint32_t)]& 0x7ff;
+	size_t x, y;
+
+	debug("[ sgi_de: STARTING DRAWING COMMAND: op = 0x%08x,"
+	    " drawmode=0x%x src_mode=0x%x dst_mode=0x%x x1=%i y1=%i"
+	    " x2=%i y2=%i fg=0x%x bg=0x%x pattern=0x%08x ]\n",
+	    op, drawmode, src_mode, dst_mode, x1, y1, x2, y2, fg, bg, pattern);
+
+	// bufdepth = 1, 2, or 4.
+	// int dst_bufdepth = 1 << ((dst_mode >> 8) & 3);
+	int src_bufdepth = 1 << ((src_mode >> 8) & 3);
+
+	int src_is_linear = 0;
+	int src_x = -1, src_y = -1;
+	int32_t step_x = 0;
+	if (drawmode & DE_DRAWMODE_XFER_EN) {
+		uint32_t addr_src = d->de_reg[(CRIME_DE_XFER_ADDR_SRC - 0x2000) / sizeof(uint32_t)];
+		uint32_t strd_src = d->de_reg[(CRIME_DE_XFER_STRD_SRC - 0x2000) / sizeof(uint32_t)];
+		step_x = d->de_reg[(CRIME_DE_XFER_STEP_X - 0x2000) / sizeof(uint32_t)];
+		int32_t step_y = d->de_reg[(CRIME_DE_XFER_STEP_Y - 0x2000) / sizeof(uint32_t)];
+		uint32_t addr_dst = d->de_reg[(CRIME_DE_XFER_ADDR_DST - 0x2000) / sizeof(uint32_t)];
+		uint32_t strd_dst = d->de_reg[(CRIME_DE_XFER_STRD_DST - 0x2000) / sizeof(uint32_t)];
+
+		src_is_linear = ((src_mode & 0x00001c00) >> 10) > 3;
+
+		if (src_is_linear) {
+			src_x = addr_src;
+			src_y = 0;
+		} else {
+			src_x = (addr_src >> 16) & 0x7ff;
+			src_y = addr_src & 0x7ff;
+		}
+
+		if (step_x != src_bufdepth || (step_y != 0 && step_y != 1)) {
+			fatal("[ sgi_de: unimplemented XFER addr_src=0x%x src_bufdepth=%i "
+				"strd_src=0x%x step_x=0x%x step_y=0x%x "
+				"addr_dst=0x%x strd_dst=0x%x ]\n",
+				addr_src, src_bufdepth, strd_src, step_x, step_y, addr_dst, strd_dst);
+
+			// exit(1);
+		}
+	}
+
+	if (!(drawmode & DE_DRAWMODE_PLANEMASK)) {
+		printf("!DE_DRAWMODE_PLANEMASK: TODO\n");
+	}
+	
+	if ((drawmode & DE_DRAWMODE_BYTEMASK) != DE_DRAWMODE_BYTEMASK) {
+		printf("not all DE_DRAWMODE_BYTEMASK set: TODO\n");
+	}
+	
+	// primitive rendering direction (not for Lines? and presumably
+	// not for Points either :-)
+	int dx = op & DE_PRIM_RL ? -1 :  1;
+	int dy = op & DE_PRIM_TB ?  1 : -1;
+
+	uint16_t saved_src_x = src_x;
+
+	/*
+	 *  Drawing is limited to 2048 x 2048 pixel space.
+	 *
+	 *  TODO: MAYBE it is really -2048 to 2027, i.e. 12 bits of
+	 *  pixel space. Perhaps it is possible to figure out
+	 *  experimentally some day, e.g. by drawing lines from
+	 *  -10,10 to 500,20 and see whether the real hardware
+	 *  interprets -10 as -10 or 0x800 - 10.
+	 */
+	uint16_t endx = (x2 + dx) & 0x7ff;
+	uint16_t endy = (y2 + dy) & 0x7ff;
+
+	int lx = abs((int)(x2 - x1)), ly = abs((int)(y2 - y1));
+	int linelen = lx > ly ? lx : ly;
+
+	switch (op & 0xff000000) {
+	case DE_PRIM_LINE:
+		if (drawmode & DE_DRAWMODE_XFER_EN)
+			fatal("[ sgi_de: XFER_EN for LINE op? ]\n");
+
+		// The PROM uses width 32, but NetBSD documents it as "half pixels".
+		// if ((op & DE_PRIM_LINE_WIDTH_MASK) != 2)
+		//	fatal("[ sgi_de: LINE_WIDTH_MASK = %i ]\n", op & DE_PRIM_LINE_WIDTH_MASK);
+
+		if (linelen == 0)
+			linelen ++;
+
+		for (int i = 0; i < ((op & DE_PRIM_LINE_SKIP_END)? linelen : linelen+1); ++i) {
+			x = (x2 * i + x1 * (linelen-i)) / linelen;
+			y = (y2 * i + y1 * (linelen-i)) / linelen;
+
+			uint32_t color = fg;
+			uint32_t oldcolor = fg;
+
+			if (drawmode & DE_DRAWMODE_ROP && rop != OPENGL_LOGIC_OP_COPY)
+				horrible_getputpixel(0, cpu, d, x, y, &oldcolor, dst_mode);
+
+			int draw = 1;
+			if (drawmode & DE_DRAWMODE_LINE_STIP) {
+				if (drawmode & DE_DRAWMODE_OPAQUE_STIP)
+					color = (pattern & 0x80000000UL) ? fg : bg;
+				else
+					draw = (pattern & 0x80000000UL)? 1 : 0;
+			}
+
+			// Raster-OP.
+			// TODO: Other ops.
+			// TODO: Should this be before or after other things?
+			if (drawmode & DE_DRAWMODE_ROP) {
+				switch (rop) {
+				case OPENGL_LOGIC_OP_COPY:
+					// color = color;
+					break;
+				case OPENGL_LOGIC_OP_XOR:
+					color = oldcolor ^ color;
+					break;
+				case OPENGL_LOGIC_OP_COPY_INVERTED:
+					color = 0xffffffff - oldcolor;
+					break;
+				default:{
+						static char rop_used[256];
+						static int first = 1;
+
+						if (first) {
+							memset(rop_used, 0, sizeof(rop_used));
+							first = 0;
+						}
+
+						if (!rop_used[rop & 255]) {
+							rop_used[rop & 255] = 1;
+							fatal("[ sgi_de: LINE: rop[0x%02x] used! ]\n", rop & 255);
+						}
+
+						if (rop >> 8) {
+							fatal("[ sgi_de: LINE: rop > 255: 0x%08x ]\n", rop);
+						}
+					}
+				}
+			}
+
+			if (draw)
+				horrible_getputpixel(1, cpu, d, x, y, &color, dst_mode);
+
+			// Rotate the stipple pattern:
+			pattern = (pattern << 1) | (pattern >> (nr_of_bits_in_the_middle-1));
+		}
+		break;
+
+	case DE_PRIM_RECTANGLE:
+		for (y = y1; y != endy; y = (y + dy) & 0x7ff) {
+			src_x = saved_src_x;
+			for (x = x1; x != endx; x = (x + dx) & 0x7ff) {
+				uint32_t color = fg;
+				uint32_t oldcolor = fg;
+
+				if (drawmode & DE_DRAWMODE_ROP && rop != OPENGL_LOGIC_OP_COPY)
+					horrible_getputpixel(0, cpu, d, x, y, &oldcolor, dst_mode);
+
+				// Pixel colors copied from another source.
+				// (OpenBSD draws characters using this mechanism.)
+				if (drawmode & DE_DRAWMODE_XFER_EN)
+					horrible_getputpixel(0, cpu, d,	src_x, src_y, &color, src_mode);
+
+				int draw = 1;
+				if (drawmode & DE_DRAWMODE_POLY_STIP) {
+					if (drawmode & DE_DRAWMODE_OPAQUE_STIP)
+						color = (pattern & 0x80000000UL) ? fg : bg;
+					else
+						draw = (pattern & 0x80000000UL)? 1 : 0;
+				}
+
+				// Raster-OP.
+				// TODO: Other ops.
+				// TODO: Should this be before or after other things?
+				if (drawmode & DE_DRAWMODE_ROP) {
+					switch (rop) {
+					case OPENGL_LOGIC_OP_COPY:
+						// color = color;
+						break;
+					case OPENGL_LOGIC_OP_XOR:
+						color = oldcolor ^ color;
+						break;
+					case OPENGL_LOGIC_OP_COPY_INVERTED:
+						color = 0xffffffff - oldcolor;
+						break;
+					default:{
+							static char rop_used[256];
+							static int first = 1;
+
+							if (first) {
+								memset(rop_used, 0, sizeof(rop_used));
+								first = 0;
+							}
+
+							if (!rop_used[rop & 255]) {
+								rop_used[rop & 255] = 1;
+								fatal("[ sgi_de: RECT: rop[0x%02x] used! ]\n", rop & 255);
+							}
+
+							if (rop >> 8) {
+								fatal("[ sgi_de: RECT: rop > 255: 0x%08x ]\n", rop);
+							}
+						}
+					}
+				}
+
+				if (draw)
+					horrible_getputpixel(1, cpu, d, x, y, &color, dst_mode);
+
+				// Rotate the stipple pattern:
+				pattern = (pattern << 1) | (pattern >> (nr_of_bits_in_the_middle-1));
+
+				if (src_is_linear)
+					src_x += step_x;
+				else
+					src_x = (src_x + dx) & 0x7ff;
+			}
+			
+			src_y = (src_y + dy) & 0x7ff;
+		}
+		break;
+
+	default:fatal("[ sgi_de: UNIMPLEMENTED drawing op = 0x%08x,"
+		    " x1=%i y1=%i x2=%i y2=%i fg=0x%x bg=0x%x pattern=0x%08x ]\n",
+		    op, x1, y1, x2, y2, fg, bg, pattern);
+		exit(1);
+	}
+}
+
+DEVICE_ACCESS(sgi_de)
+{
+	struct sgi_re_data *d = (struct sgi_re_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int regnr;
+	int startFlag = relative_addr & CRIME_DE_START;
+
+	relative_addr &= ~CRIME_DE_START;
+
+	idata = memory_readmax64(cpu, data, len);
+	regnr = relative_addr / sizeof(uint32_t);
+
+	relative_addr += 0x2000;
+
+	/*
+	 *  Treat all registers as read/write, by default.  Sometimes these
+	 *  are accessed as 32-bit words, sometimes as 64-bit words to access
+	 *  two adjacent registers in one operation.
+	 */
+	if (len == 8) {
+		if (writeflag == MEM_WRITE) {
+			d->de_reg[regnr] = idata >> 32ULL;
+			d->de_reg[regnr+1] = idata;
+		} else
+			odata = ((uint64_t)d->de_reg[regnr] << 32ULL) +
+			    d->de_reg[regnr+1];
+	} else if (len == 4) {
+		if (writeflag == MEM_WRITE)
+			d->de_reg[regnr] = idata;
+		else
+			odata = d->de_reg[regnr];
+	} else {
+		fatal("sgi_de: len = %i not implemented\n", len);
+		exit(1);
+	}
+
+	switch (relative_addr) {
+
+	case CRIME_DE_MODE_SRC:
+		debug("[ sgi_de: %s CRIME_DE_MODE_SRC: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_MODE_DST:
+		debug("[ sgi_de: %s CRIME_DE_MODE_DST: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_CLIPMODE:
+		debug("[ sgi_de: %s CRIME_DE_CLIPMODE: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		if (writeflag == MEM_WRITE && idata != 0)
+			fatal("[ sgi_de: TODO: non-zero CRIME_DE_CLIPMODE: 0x%016llx ]\n", idata);
+		break;
+
+	case CRIME_DE_DRAWMODE:
+		debug("[ sgi_de: %s CRIME_DE_DRAWMODE: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_SCRMASK0:
+		debug("[ sgi_de: %s CRIME_DE_SCRMASK0: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		if (writeflag == MEM_WRITE && idata != 0)
+			fatal("[ sgi_de: TODO: non-zero CRIME_DE_SCRMASK0: 0x%016llx ]\n", idata);
+		break;
+
+	case CRIME_DE_SCRMASK1:
+		debug("[ sgi_de: %s CRIME_DE_SCRMASK1: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		if (writeflag == MEM_WRITE && idata != 0)
+			fatal("[ sgi_de: TODO: non-zero CRIME_DE_SCRMASK1: 0x%016llx ]\n", idata);
+		break;
+
+	case CRIME_DE_SCRMASK2:
+		debug("[ sgi_de: %s CRIME_DE_SCRMASK2: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		if (writeflag == MEM_WRITE && idata != 0)
+			fatal("[ sgi_de: TODO: non-zero CRIME_DE_SCRMASK2: 0x%016llx ]\n", idata);
+		break;
+
+	case CRIME_DE_SCRMASK3:
+		debug("[ sgi_de: %s CRIME_DE_SCRMASK3: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		if (writeflag == MEM_WRITE && idata != 0)
+			fatal("[ sgi_de: TODO: non-zero CRIME_DE_SCRMASK3: 0x%016llx ]\n", idata);
+		break;
+
+	case CRIME_DE_SCRMASK4:
+		debug("[ sgi_de: %s CRIME_DE_SCRMASK4: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		if (writeflag == MEM_WRITE && idata != 0)
+			fatal("[ sgi_de: TODO: non-zero CRIME_DE_SCRMASK4: 0x%016llx ]\n", idata);
+		break;
+
+	case CRIME_DE_SCISSOR:
+		debug("[ sgi_de: %s CRIME_DE_SCISSOR: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		if (writeflag == MEM_WRITE && idata != 0)
+			fatal("[ sgi_de: TODO: non-zero CRIME_DE_SCISSOR: 0x%016llx ]\n", idata);
+		break;
+
+	case CRIME_DE_SCISSOR + 4:
+		// NetBSD writes 0x3fff3fff here. "High" part of SCISSOR register?
+		debug("[ sgi_de: %s CRIME_DE_SCISSOR+4: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		if (writeflag == MEM_WRITE && idata != 0x3fff3fff)
+			fatal("[ sgi_de: TODO: CRIME_DE_SCISSOR+4: 0x%016llx ]\n", idata);
+		break;
+
+	case CRIME_DE_PRIMITIVE:
+		debug("[ sgi_de: %s CRIME_DE_PRIMITIVE: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_WINOFFSET_SRC:
+		debug("[ sgi_de: %s CRIME_DE_WINOFFSET_SRC: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		if (writeflag == MEM_WRITE && idata != 0)
+			fatal("[ sgi_de: TODO: non-zero CRIME_DE_WINOFFSET_SRC: 0x%016llx ]\n", idata);
+		break;
+
+	case CRIME_DE_WINOFFSET_DST:
+		debug("[ sgi_de: %s CRIME_DE_WINOFFSET_DST: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		if (writeflag == MEM_WRITE && idata != 0)
+			fatal("[ sgi_de: TODO: non-zero CRIME_DE_WINOFFSET_DST: 0x%016llx ]\n", idata);
+		break;
+
+	case CRIME_DE_X_VERTEX_0:
+		debug("[ sgi_de: %s CRIME_DE_X_VERTEX_0: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_X_VERTEX_1:
+		debug("[ sgi_de: %s CRIME_DE_X_VERTEX_1: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_XFER_ADDR_SRC:
+		debug("[ sgi_de: %s CRIME_DE_XFER_ADDR_SRC: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_XFER_STRD_SRC:
+		debug("[ sgi_de: %s CRIME_DE_XFER_STRD_SRC: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_XFER_STEP_X:
+		debug("[ sgi_de: %s CRIME_DE_XFER_STEP_X: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_XFER_STEP_Y:
+		debug("[ sgi_de: %s CRIME_DE_XFER_STEP_Y: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_XFER_ADDR_DST:
+		debug("[ sgi_de: %s CRIME_DE_XFER_ADDR_DST: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_XFER_STRD_DST:
+		debug("[ sgi_de: %s CRIME_DE_XFER_STRD_DST: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_STIPPLE_MODE:
+		debug("[ sgi_de: %s CRIME_DE_STIPPLE_MODE: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_STIPPLE_PAT:
+		debug("[ sgi_de: %s CRIME_DE_STIPPLE_PAT: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_FG:
+		debug("[ sgi_de: %s CRIME_DE_FG: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_BG:
+		debug("[ sgi_de: %s CRIME_DE_BG: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_ROP:
+		debug("[ sgi_de: %s CRIME_DE_ROP: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_PLANEMASK:
+		debug("[ sgi_de: %s CRIME_DE_PLANEMASK: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_NULL:
+		debug("[ sgi_de: %s CRIME_DE_NULL: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_DE_FLUSH:
+		debug("[ sgi_de: %s CRIME_DE_FLUSH: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			fatal("[ sgi_de: unimplemented write to "
+			    "address 0x%llx, data=0x%016llx ]\n",
+			    (long long)relative_addr, (long long)idata);
+		else
+			fatal("[ sgi_de: unimplemented read from address"
+			    " 0x%llx ]\n", (long long)relative_addr);
+	}
+
+	if (startFlag)
+		draw_primitive(cpu, d);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_sgi_de_init():
+ */
+void dev_sgi_de_init(struct memory *mem, uint64_t baseaddr, struct sgi_re_data *d)
+{
+	memory_device_register(mem, "sgi_de", baseaddr, DEV_SGI_DE_LENGTH,
+	    dev_sgi_de_access, (void *)d, DM_DEFAULT, NULL);
+}
+
+
+/****************************************************************************/
+
+/*
+ *  SGI "mte", NetBSD sources describes it as a "memory transfer engine".
+ *
+ *  If the relative address has the 0x0800 (CRIME_DE_START) flag set, it means
+ *  "go ahead with the transfer". Otherwise, it is just reads and writes of the
+ *  registers.
+ */
+
+void do_mte_transfer(struct cpu* cpu, struct sgi_re_data *d)
+{
+	uint32_t mode = d->mte_reg[(CRIME_MTE_MODE - 0x3000) / sizeof(uint32_t)];
+	uint32_t src0 = d->mte_reg[(CRIME_MTE_SRC0 - 0x3000) / sizeof(uint32_t)];
+	uint32_t src1 = d->mte_reg[(CRIME_MTE_SRC1 - 0x3000) / sizeof(uint32_t)];
+	uint32_t dst0 = d->mte_reg[(CRIME_MTE_DST0 - 0x3000) / sizeof(uint32_t)];
+	uint32_t dst1 = d->mte_reg[(CRIME_MTE_DST1 - 0x3000) / sizeof(uint32_t)];
+	int32_t src_y_step = d->mte_reg[(CRIME_MTE_SRC_Y_STEP - 0x3000) / sizeof(uint32_t)];
+	int32_t dst_y_step = d->mte_reg[(CRIME_MTE_DST_Y_STEP - 0x3000) / sizeof(uint32_t)];
+	uint32_t dstlen = dst1 - dst0 + 1, fill_addr;
+	unsigned char zerobuf[4096];
+	int depth = 8 << ((mode & MTE_MODE_DEPTH_MASK) >> MTE_DEPTH_SHIFT);
+	int src = (mode & MTE_MODE_SRC_BUF_MASK) >> MTE_SRC_TLB_SHIFT;
+	uint32_t bytemask = d->mte_reg[(CRIME_MTE_BYTEMASK - 0x3000) / sizeof(uint32_t)];
+	uint32_t bg = d->mte_reg[(CRIME_MTE_BG - 0x3000) / sizeof(uint32_t)];
+
+	debug("[ sgi_mte: STARTING: mode=0x%08x src0=0x%08x src1=0x%08x src_y_step=%i dst0=0x%08x,"
+	    " dst1=0x%08x dst_y_step=%i bg=0x%x bytemask=0x%x ]\n",
+	    mode,
+	    src0, src1, src_y_step,
+	    dst0, dst1, dst_y_step,
+	    bg, bytemask);
+
+	if (dst_y_step != 0 && dst_y_step != 1 && dst_y_step != -1) {
+		fatal("[ sgi_mte: TODO! unimplemented dst_y_step %i ]", dst_y_step);
+		// exit(1);
+	}
+
+	if (mode & MTE_MODE_STIPPLE) {
+		fatal("[ sgi_mte: unimplemented MTE_MODE_STIPPLE ]");
+		exit(1);
+	}
+
+	int src_tlb = (mode & MTE_MODE_SRC_BUF_MASK) >> MTE_SRC_TLB_SHIFT;
+	int dst_tlb = (mode & MTE_MODE_DST_BUF_MASK) >> MTE_DST_TLB_SHIFT;
+	
+	if (src > MTE_TLB_C) {
+		fatal("[ sgi_mte: unimplemented SRC ]");
+		exit(1);
+	}
+
+	switch (dst_tlb) {
+	case MTE_TLB_A:
+	case MTE_TLB_B:
+	case MTE_TLB_C:
+		// Used by NetBSD's crmfb_fill_rect. It puts graphical
+		// coordinates in dst0 and dst1.
+		{
+			int x1 = (dst0 >> 16) & 0xfff;
+			int y1 = dst0 & 0xfff;
+			int x2 = (dst1 >> 16) & 0xfff;
+			int y2 = dst1 & 0xfff;
+			x1 /= (depth / 8);
+			x2 /= (depth / 8);
+
+			int src_x1 = (src0 >> 16) & 0xfff;
+			int src_y1 = src0 & 0xfff;
+			// int src_x2 = (src1 >> 16) & 0xfff;
+			// int src_y2 = src1 & 0xfff;
+			src_x1 /= (depth / 8);
+			// src_x2 /= (depth / 8);
+
+			int dx = x1 > x2 ? -1 : 1;
+			int dy = y1 > y2 ? -1 : 1;
+			
+			uint32_t src_mode = (src_tlb << 10) + (((mode & MTE_MODE_DEPTH_MASK) >> MTE_DEPTH_SHIFT) << 8);
+			uint32_t dst_mode = (dst_tlb << 10) + (((mode & MTE_MODE_DEPTH_MASK) >> MTE_DEPTH_SHIFT) << 8);
+
+			// Hack. The MTE perhaps doesn't deal with colors per se,
+			// but this makes sure that we copy 32 bits when doing 32-bit
+			// transfers.
+			if (depth == 4) {
+				src_mode |= DE_MODE_TYPE_RGBA;
+				dst_mode |= DE_MODE_TYPE_RGBA;
+			}
+
+			int src_y = src_y1;
+			for (int y = y1; y != y2+dy; y += dy) {
+				int src_x = src_x1;
+				
+				for  (int x = x1; x != x2+dx; x += dx) {
+					if (mode & MTE_MODE_COPY) {
+						horrible_getputpixel(0, cpu, d,
+							src_x, src_y, &bg, src_mode);
+						src_x += dx;
+					}
+
+					horrible_getputpixel(1, cpu, d, x, y, &bg, dst_mode);
+				}
+				
+				src_y += dy;
+			}
+		}
+		break;
+	case MTE_TLB_LIN_A:
+	case MTE_TLB_LIN_B:
+		// Used by the PROM to zero-fill memory (?).
+		if (mode & MTE_MODE_COPY) {
+			fatal("[ sgi_mte: unimplemented MTE_MODE_COPY ]");
+			exit(1);
+		}
+
+		if (depth != 8) {
+			fatal("[ sgi_mte: unimplemented MTE_DEPTH_x ]");
+			exit(1);
+		}
+
+		debug("[ sgi_mte: LINEAR TRANSFER: mode=0x%08x dst0=0x%016llx,"
+		    " dst1=0x%016llx (length 0x%llx), dst_y_step=%i bg=0x%x, bytemask=0x%x ]\n",
+		    mode,
+		    (long long)dst0, (long long)dst1,
+		    (long long)dstlen, dst_y_step, (int)bg, (int)bytemask);
+
+		if (bytemask != 0xffffffff) {
+			fatal("unimplemented MTE bytemask 0x%08x\n", (int)bytemask);
+			exit(1);
+		}
+
+		/*
+		 *  Horrible hack:
+		 *
+		 *  During bootup, the PROM fills memory at 0x40000000 and
+		 *  forward. This corresponds to the lowest possible RAM address.
+		 *  However, these fills are not going via the CPU's cache,
+		 *  which contains things such as the return address on the
+		 *  stack. If we _really_ write this data in the emulator (which
+		 *  doesn't emulate the cache), it would overwrite the stack.
+		 *
+		 *  So let's not.
+		 *
+		 *  (If some guest OS or firmware variant actually depends on
+		 *  the ability to write to the start of memory this way,
+		 *  it would not work in the emulator.)
+		 */
+		// if (dst0 >= 0x40000000 && dst0 < 0x40004000 && dst1 > 0x40004000) {
+		//	dst0 += 0x4000;
+		//	dstlen -= 0x4000;
+		// }
+
+		/*
+		 *  HUH?
+		 *
+		 *  Note that due to a bug (?) in the PROM firmware when it
+		 *  is setting up the TLB entries, only every _second_ page is
+		 *  actually put correctly in the TLB. This means that even
+		 *  though it then tries to fill 0x40000000 .. 0x40007fff with
+		 *  zeroes, it only fills 0x40001000 .. 0x40001fff,
+		 *  0x40003000 .. 0x40003fff and so on!
+		 *
+		 *  So the Horrible hack above is not needed.
+		 *
+		 *  Ironic.
+		 */
+
+		memset(zerobuf, bg, dstlen < sizeof(zerobuf) ? dstlen : sizeof(zerobuf));
+		fill_addr = dst0;
+		while (dstlen != 0) {
+			uint64_t fill_len;
+			if (dstlen > sizeof(zerobuf))
+				fill_len = sizeof(zerobuf);
+			else
+				fill_len = dstlen;
+
+			uint64_t starting_page = fill_addr & ~0xfff;
+			uint64_t ending_page = (fill_addr + fill_len - 1) & ~0xfff;
+			if (starting_page != ending_page) {
+				fill_len = starting_page + 4096 - fill_addr;
+			}
+
+			// Find starting_page in the TLB in question.
+			starting_page >>= 12;
+			uint32_t *tlb = dst_tlb == MTE_TLB_LIN_A ? d->re_linear_a : d->re_linear_b;
+			int match = 0;
+			for (int i = 0; i < 32; ++i) {
+				uint32_t entry = tlb[i];
+				if (entry & 0x80000000) {
+					entry &= ~0x80000000;
+					if (entry == starting_page) {
+						match = 1;
+						break;
+					}
+				}
+			}
+			
+			if (match) {
+				cpu->memory_rw(cpu, cpu->mem, fill_addr, zerobuf, fill_len,
+					MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
+			} else {
+				debug("[ sgi_mte: WARNING: address 0x%x not found in TLB? Ignoring fill. ]\n",
+					(long long)fill_addr);
+			}
+
+			fill_addr += fill_len;
+			dstlen -= sizeof(zerobuf);
+		}
+		break;
+	default:
+		fatal("[ sgi_mte: TODO! unimplemented dst_tlb 0x%x ]", dst_tlb);
+	}
+}
+
+DEVICE_ACCESS(sgi_mte)
+{
+	struct sgi_re_data *d = (struct sgi_re_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int regnr;
+	int startFlag = relative_addr & CRIME_DE_START;
+
+	relative_addr &= ~CRIME_DE_START;
+
+	idata = memory_readmax64(cpu, data, len);
+	regnr = relative_addr / sizeof(uint32_t);
+
+	relative_addr += 0x3000;
+
+	/*
+	 *  Treat all registers as read/write, by default.  Sometimes these
+	 *  are accessed as 32-bit words, sometimes as 64-bit words.
+	 *
+	 *  NOTE: The lowest bits are internally stored in the "low" (+0)
+	 *  register, and the higher bits are stored in the "+1" word.
+	 */
+	if (len == 4) {
+		if (writeflag == MEM_WRITE)
+			d->mte_reg[regnr] = idata;
+		else
+			odata = d->mte_reg[regnr];
+	} else if (len != 4) {
+		if (writeflag == MEM_WRITE) {
+			d->mte_reg[regnr+1] = idata >> 32;
+			d->mte_reg[regnr] = idata;
+		} else {
+			odata = ((uint64_t)d->mte_reg[regnr+1] << 32) +
+			    d->mte_reg[regnr];
+		}
+	} else {
+		fatal("[ sgi_mte: UNIMPLEMENTED read/write len %i ]\n", len);
+		exit(1);
+	}
+
+	switch (relative_addr) {
+
+	case CRIME_MTE_MODE:
+		debug("[ sgi_mte: %s CRIME_MTE_MODE: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_MTE_BYTEMASK:
+		debug("[ sgi_mte: %s CRIME_MTE_BYTEMASK: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_MTE_STIPPLEMASK:
+		fatal("[ sgi_mte: %s CRIME_MTE_STIPPLEMASK: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_MTE_BG:
+		debug("[ sgi_mte: %s CRIME_MTE_BG: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_MTE_SRC0:
+		debug("[ sgi_mte: %s CRIME_MTE_SRC0: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_MTE_SRC1:
+		debug("[ sgi_mte: %s CRIME_MTE_SRC1: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_MTE_DST0:
+		debug("[ sgi_mte: %s CRIME_MTE_DST0: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_MTE_DST1:
+		debug("[ sgi_mte: %s CRIME_MTE_DST1: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_MTE_SRC_Y_STEP:
+		debug("[ sgi_mte: %s CRIME_MTE_SRC_Y_STEP: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_MTE_DST_Y_STEP:
+		debug("[ sgi_mte: %s CRIME_MTE_DST_Y_STEP: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_MTE_NULL:
+		fatal("[ sgi_mte: %s CRIME_MTE_NULL: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	case CRIME_MTE_FLUSH:
+		fatal("[ sgi_mte: %s CRIME_MTE_FLUSH: 0x%016llx ]\n",
+		    writeflag == MEM_WRITE ? "write to" : "read from",
+		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			fatal("[ sgi_mte: unimplemented write to "
+			    "address 0x%llx, data=0x%016llx ]\n",
+			    (long long)relative_addr, (long long)idata);
+		else
+			fatal("[ sgi_mte: unimplemented read from address"
+			    " 0x%llx ]\n", (long long)relative_addr);
+	}
+
+	if (startFlag)
+		do_mte_transfer(cpu, d);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_sgi_mte_init():
+ */
+void dev_sgi_mte_init(struct memory *mem, uint64_t baseaddr, struct sgi_re_data *d)
+{
+	memory_device_register(mem, "sgi_mte", baseaddr, DEV_SGI_MTE_LENGTH,
+	    dev_sgi_mte_access, (void *)d, DM_DEFAULT, NULL);
+}
+
+
+/****************************************************************************/
+
+/*
+ *  SGI "de_status".
+ */
+
+DEVICE_ACCESS(sgi_de_status)
+{
+	// struct sgi_re_data *d = (struct sgi_re_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	idata = memory_readmax64(cpu, data, len);
+
+	relative_addr += 0x4000;
+
+	switch (relative_addr) {
+
+	case CRIME_DE_STATUS:	// 0x4000
+		odata = CRIME_DE_IDLE |
+			CRIME_DE_SETUP_IDLE |
+			CRIME_DE_PIXPIPE_IDLE |
+			CRIME_DE_MTE_IDLE;
+
+		/*
+		 *  TODO: Actually simulate pipeline of a number of commands?
+		 */
+		break;
+
+	case 0x4008:
+		/*  Unknown. Ignore for now.  */
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			debug("[ sgi_de_status: unimplemented write to "
+			    "address 0x%llx, data=0x%016llx ]\n",
+			    (long long)relative_addr, (long long)idata);
+		else
+			debug("[ sgi_de_status: unimplemented read from address"
+			    " 0x%llx ]\n", (long long)relative_addr);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_sgi_de_status_init():
+ */
+void dev_sgi_de_status_init(struct memory *mem, uint64_t baseaddr, struct sgi_re_data *d)
+{
+	memory_device_register(mem, "sgi_de_status", baseaddr, DEV_SGI_DE_STATUS_LENGTH,
+	    dev_sgi_de_status_access, (void *)d, DM_DEFAULT, NULL);
+}
+
+
diff -Nru gxemul-0.6.2/src/devices/dev_sgi_re.cc gxemul-0.7.0+dfsg/src/devices/dev_sgi_re.cc
--- gxemul-0.6.2/src/devices/dev_sgi_re.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sgi_re.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1340 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: SGI O2 "Rendering Engine"
- *
- *  Guesswork, based on how Linux, NetBSD, and OpenBSD use the graphics on
- *  the SGI O2. Using NetBSD terminology (from crmfbreg.h):
- *
- *  dev_sgi_re.cc (THIS FILE):
- *	0x15001000	rendering engine (TLBs)
- *	0x15002000	drawing engine
- *	0x15003000	memory transfer engine
- *	0x15004000	status registers for drawing engine
- *
- *  dev_sgi_gbe.cc:
- *	0x16000000	crm (or GBE) framebuffer control / video output
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/crmfbreg.h"
-#include "thirdparty/sgi_gl.h"
-
-
-struct sgi_re_data {
-	// Rendering engine registers:
-	uint16_t	re_tlb_a[256];
-	uint16_t	re_tlb_b[256];
-	uint16_t	re_tlb_c[256];
-	uint16_t	re_tex[112];
-	// todo: clip_ids registers.
-	uint32_t	re_linear_a[32];
-	uint32_t	re_linear_b[32];
-
-	// Drawing engine registers:
-	uint32_t	de_reg[DEV_SGI_DE_LENGTH / sizeof(uint32_t)];
-
-	// Memory transfer engine registers:
-	uint32_t	mte_reg[DEV_SGI_MTE_LENGTH / sizeof(uint32_t)];
-};
-
-
-/*
- *  horrible_getputpixel():
- *
- *  This routine gets/puts a pixel in one of the tiles, from the perspective of
- *  the rendering/drawing engine. Given x and y, it figures out which tile
- *  number it is, and then finally does a slow read/write to get/put the pixel
- *  at the correct sub-coordinates within the tile.
- *
- *  Tiles are always 512 _bytes_ wide, and 128 pixels high. For 32-bit color
- *  modes, for example, that means 128 x 128 pixels.
- *
- *  For "linear" modes, y is ignored and x is an offset to select which linear
- *  TLB entry to use.
- */
-void horrible_getputpixel(bool put, struct cpu* cpu, struct sgi_re_data* d,
-	int x, int y, uint32_t* color, int mode)
-{
-	uint32_t color_mode = mode & DE_MODE_TYPE_MASK;
-	int bufdepth = 1 << ((mode >> 8) & 3); 
-
-	// dst_mode (see NetBSD's crmfbreg.h):
-	// #define DE_MODE_TLB_A           0x00000000
-	// #define DE_MODE_TLB_B           0x00000400
-	// #define DE_MODE_TLB_C           0x00000800
-	// #define DE_MODE_LIN_A           0x00001000
-	// #define DE_MODE_LIN_B           0x00001400
-	uint32_t tlb_mode = (mode >> 10) & 0x7;
-	bool linear = tlb_mode > 3;
-
-	if (!linear && (x < 0 || y < 0 || x >= 2048 || y >= 2048))
-		return;
-
-	int tilewidth_in_pixels = 512 / bufdepth;
-	
-	int tile_nr_x = x / tilewidth_in_pixels;
-	int tile_nr_y = y >> 7;
-
-	unsigned int tile_nr = tile_nr_y * 16 + tile_nr_x;
-
-	y &= 127;
-	int xofs = (x % tilewidth_in_pixels) * bufdepth;
-	int ofs = 512 * y + xofs;
-
-	uint32_t tileptr = 0;
-
-	switch (tlb_mode) {
-	case 0:	tileptr = d->re_tlb_a[tile_nr] << 16;
-		break;
-	case 1:	tileptr = d->re_tlb_b[tile_nr] << 16;
-		break;
-	case 2:	tileptr = d->re_tlb_c[tile_nr] << 16;
-		break;
-	case 4:	tile_nr = x >> 12;
-		if (tile_nr >= 32)
-			return;
-		tileptr = 0x80000000 | (d->re_linear_a[tile_nr] << 12);
-		ofs = x & 4095;
-		// TODO... probably not correct!
-		// printf("tileptr = %08x x = %i y = %i tile_nr = %i ofs = %i\n", tileptr, x, y, tile_nr, ofs);
-		break;
-	default:fatal("unimplemented dst_mode %i for horrible_getputpixel (%s), x=%i y=%i\n",
-			mode, put ? "put" : "get", x, y);
-		// exit(1);
-		*color = random();
-		return;
-	}
-
-	// The highest bit seems to be set for a "valid" tile pointer.
-	if (!(tileptr & 0x80000000)) {
-		//printf("dst_mode %i, tile_nr = %i,  tileptr = 0x%llx\n", dst_mode, tile_nr, (long long)tileptr);
-		//fatal("sgi gbe horrible_getputpixel: unexpected non-set high bit of tileptr?\n");
-		//exit(1);
-		return;
-	}
-	
-	tileptr &= ~0x80000000;
-
-	uint8_t buf[4];
-	if (put) {
-		switch (color_mode) {
-		case DE_MODE_TYPE_CI:
-			buf[0] = *color;
-			break;
-		case DE_MODE_TYPE_RGB:
-			buf[0] = *color >> 24;
-			buf[1] = *color >> 16;
-			buf[2] = *color >> 8;
-			buf[3] = 0;
-			break;
-		case DE_MODE_TYPE_RGBA:
-			buf[0] = *color >> 24;
-			buf[1] = *color >> 16;
-			buf[2] = *color >> 8;
-			buf[3] = *color;
-			break;
-		case DE_MODE_TYPE_ABGR:
-			buf[0] = *color;
-			buf[1] = *color >> 8;
-			buf[2] = *color >> 16;
-			buf[3] = *color >> 24;
-			break;
-		default:buf[0] = random();
-			buf[1] = random();
-			buf[2] = random();
-			buf[3] = random();
-			// TODO.
-			fatal("[ put: color mode = 0x%x ]\n", color_mode);
-		}
-
-		cpu->memory_rw(cpu, cpu->mem, tileptr + ofs,
-		    buf, bufdepth, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
-	} else {
-		cpu->memory_rw(cpu, cpu->mem, tileptr + ofs,
-		    buf, bufdepth, MEM_READ, NO_EXCEPTIONS | PHYSICAL);
-
-		switch (color_mode) {
-		case DE_MODE_TYPE_CI:
-			*color = buf[0];
-			break;
-		case DE_MODE_TYPE_RGB:
-			*color = (buf[1] << 24) + (buf[2] << 16) + (buf[3] << 8);
-			break;
-		case DE_MODE_TYPE_RGBA:
-			*color = (buf[0] << 24) + (buf[1] << 16) + (buf[2] << 8) + buf[3];
-			break;
-		case DE_MODE_TYPE_ABGR:
-			*color = (buf[3] << 24) + (buf[2] << 16) + (buf[1] << 8) + buf[0];
-			break;
-		default:// Read "raw" 32-bit value:
-			*color = (buf[3] << 24) + (buf[2] << 16) + (buf[1] << 8) + buf[0];
-			fatal("[ get: color mode = 0x%x ]\n", color_mode);
-		}
-	}
-}
-
-
-/*
- *  SGI "re", NetBSD sources describes it as a "rendering engine".
- */
-
-DEVICE_ACCESS(sgi_re)
-{
-	struct sgi_re_data *d = (struct sgi_re_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	idata = memory_readmax64(cpu, data, len);
-
-	relative_addr += 0x1000;
-
-	if (relative_addr >= CRIME_RE_TLB_A && relative_addr < CRIME_RE_TLB_B) {
-		if (len != 8) {
-			fatal("TODO: unimplemented len=%i for CRIME_RE_TLB_A\n", len);
-			exit(1);
-		}
-
-		if (writeflag == MEM_WRITE) {
-			int tlbi = ((relative_addr & 0x1ff) >> 1) & 0xff;
-			for (size_t hwi = 0; hwi < len; hwi += sizeof(uint16_t)) {
-				d->re_tlb_a[tlbi] = data[hwi]*256 + data[hwi+1];
-				debug("d->re_tlb_a[%i] = 0x%04x\n", tlbi, d->re_tlb_a[tlbi]);
-				tlbi++;
-			}
-		} else {
-			fatal("TODO: read from CRIME_RE_TLB_A\n");
-			exit(1);
-		}
-	} else if (relative_addr >= CRIME_RE_TLB_B && relative_addr < CRIME_RE_TLB_C) {
-		if (len != 8) {
-			fatal("TODO: unimplemented len=%i for CRIME_RE_TLB_B\n", len);
-			exit(1);
-		}
-
-		if (writeflag == MEM_WRITE) {
-			int tlbi = ((relative_addr & 0x1ff) >> 1) & 0xff;
-			for (size_t hwi = 0; hwi < len; hwi += sizeof(uint16_t)) {
-				d->re_tlb_b[tlbi] = data[hwi]*256 + data[hwi+1];
-				debug("d->re_tlb_b[%i] = 0x%04x\n", tlbi, d->re_tlb_b[tlbi]);
-				tlbi++;
-			}
-		} else {
-			fatal("TODO: read from CRIME_RE_TLB_B\n");
-			exit(1);
-		}
-	} else if (relative_addr >= CRIME_RE_TLB_C && relative_addr < CRIME_RE_TLB_C + 0x200) {
-		if (len != 8) {
-			fatal("TODO: unimplemented len=%i for CRIME_RE_TLB_C\n", len);
-			exit(1);
-		}
-
-		if (writeflag == MEM_WRITE) {
-			int tlbi = ((relative_addr & 0x1ff) >> 1) & 0xff;
-			for (size_t hwi = 0; hwi < len; hwi += sizeof(uint16_t)) {
-				d->re_tlb_c[tlbi] = data[hwi]*256 + data[hwi+1];
-				debug("d->re_tlb_c[%i] = 0x%04x\n", tlbi, d->re_tlb_c[tlbi]);
-				tlbi++;
-			}
-		} else {
-			fatal("TODO: read from CRIME_RE_TLB_C\n");
-			exit(1);
-		}
-	} else if (relative_addr >= CRIME_RE_TEX && relative_addr < CRIME_RE_TEX + 0xe0) {
-		if (len != 8) {
-			fatal("TODO: unimplemented len=%i for CRIME_RE_TEX\n", len);
-			exit(1);
-		}
-
-		if (writeflag == MEM_WRITE) {
-			int tlbi = ((relative_addr & 0xff) >> 3) & 0xff;
-			for (size_t hwi = 0; hwi < len; hwi += sizeof(uint16_t)) {
-				d->re_tex[tlbi] = data[hwi]*256 + data[hwi+1];
-				debug("d->re_tex[%i] = 0x%04x\n", tlbi, d->re_tex[tlbi]);
-				tlbi++;
-			}
-		} else {
-			fatal("TODO: read from CRIME_RE_TEX\n");
-			exit(1);
-		}
-	} else if (relative_addr >= CRIME_RE_LINEAR_A && relative_addr < CRIME_RE_LINEAR_A + 0x80) {
-		if (len != 8) {
-			fatal("TODO: unimplemented len=%i for CRIME_RE_LINEAR_A\n", len);
-			exit(1);
-		}
-
-		if (writeflag == MEM_WRITE) {
-			/*
-			 *  Very interesting. NetBSD writes stuff such as:
-			 *
-			 *  CRIME_RE_LINEAR_A IDATA = 8000173080001731
-			 *  CRIME_RE_LINEAR_A IDATA = 8000173280001733
-			 *  CRIME_RE_LINEAR_A IDATA = 8000173480001735
-			 *  ...
-			 *
-			 *  but the PROM writes something which looks like wrongly
-			 *  32-bit sign-extended words:
-			 *
-			 *  CRIME_RE_LINEAR_A IDATA = ffffffff80040001
-			 *  CRIME_RE_LINEAR_A IDATA = ffffffff80040003
-			 *  CRIME_RE_LINEAR_A IDATA = ffffffff80040005
-			 *  ...
-			 *
-			 *  followed by
-			 *  [ sgi_mte: STARTING TRANSFER: mode=0x00000011
-			 *    dst0=0x0000000040000000, dst1=0x0000000040007fff
-			 *    (length 0x8000), dst_y_step=0 bg=0x0, bytemask=0xffffffff ]
-			 *
-			 *  indicating that it really meant to put both 0x80040000
-			 *  and 0x80040001 into the first LINEAR_A entry.
-			 *
-			 *  The first guess would be a bug in the implementation of
-			 *  one or more instructions in the emulator while coming up
-			 *  with those values, but debugging the PROM so far has NOT
-			 *  revealed any such bug. It may even be that the PROM code
-			 *  is buggy (?) and never really set the LINEAR entries
-			 *  correctly. Perhaps the hardware simply ignores the
-			 *  weird values and does not fill it (using the MTE)
-			 *  when asked to.
-			 */
-			// printf("CRIME_RE_LINEAR_A IDATA = %016llx\n", (long long)idata);
-			int tlbi = ((relative_addr & 0x7f) >> 2) & 0x1f;
-			d->re_linear_a[tlbi] = idata >> 32ULL;
-			d->re_linear_a[tlbi+1] = idata;
-			debug("[ d->re_linear_a[%i] = 0x%08x, [%i] = 0x%08x ]\n",
-				tlbi, d->re_linear_a[tlbi], tlbi+1, d->re_linear_a[tlbi+1]);
-		} else {
-			fatal("TODO: read from CRIME_RE_LINEAR_A\n");
-			exit(1);
-		}
-	} else if (relative_addr >= CRIME_RE_LINEAR_B && relative_addr < CRIME_RE_LINEAR_B + 0x80) {
-		if (len != 8) {
-			fatal("TODO: unimplemented len=%i for CRIME_RE_LINEAR_B\n", len);
-			exit(1);
-		}
-
-		if (writeflag == MEM_WRITE) {
-			int tlbi = ((relative_addr & 0x7f) >> 2) & 0x1f;
-			d->re_linear_b[tlbi] = idata >> 32ULL;
-			d->re_linear_b[tlbi+1] = idata;
-			debug("[ d->re_linear_b[%i] = 0x%08x, [%i] = 0x%08x ]\n",
-				tlbi, d->re_linear_b[tlbi], tlbi+1, d->re_linear_b[tlbi+1]);
-		} else {
-			fatal("TODO: read from CRIME_RE_LINEAR_B\n");
-			exit(1);
-		}
-	} else {
-		if (writeflag == MEM_WRITE)
-			fatal("[ sgi_re: unimplemented write to "
-			    "address 0x%llx, data=0x%016llx ]\n",
-			    (long long)relative_addr, (long long)idata);
-		else
-			fatal("[ sgi_re: unimplemented read from address"
-			    " 0x%llx ]\n", (long long)relative_addr);
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_sgi_re_init():
- */
-void dev_sgi_re_init(struct machine *machine, struct memory *mem, uint64_t baseaddr)
-{
-	struct sgi_re_data *d;
-
-	CHECK_ALLOCATION(d = (struct sgi_re_data *) malloc(sizeof(struct sgi_re_data)));
-	memset(d, 0, sizeof(struct sgi_re_data));
-
-	memory_device_register(mem, "sgi_re", baseaddr + 0x1000, DEV_SGI_RE_LENGTH,
-	    dev_sgi_re_access, d, DM_DEFAULT, NULL);
-
-	dev_sgi_de_init(mem, baseaddr + 0x2000, d);
-	dev_sgi_mte_init(mem, baseaddr + 0x3000, d);
-	dev_sgi_de_status_init(mem, baseaddr + 0x4000, d);
-}
-
-
-
-/****************************************************************************/
-
-/*
- *  SGI "de", NetBSD sources describes it as a "drawing engine".
- */
-
-void draw_primitive(struct cpu* cpu, struct sgi_re_data *d)
-{
-	uint32_t op = d->de_reg[(CRIME_DE_PRIMITIVE - 0x2000) / sizeof(uint32_t)];
-	uint32_t drawmode = d->de_reg[(CRIME_DE_DRAWMODE - 0x2000) / sizeof(uint32_t)];
-	uint32_t dst_mode = d->de_reg[(CRIME_DE_MODE_DST - 0x2000) / sizeof(uint32_t)];
-	uint32_t src_mode = d->de_reg[(CRIME_DE_MODE_SRC - 0x2000) / sizeof(uint32_t)];
-	uint32_t fg = d->de_reg[(CRIME_DE_FG - 0x2000) / sizeof(uint32_t)];
-	uint32_t bg = d->de_reg[(CRIME_DE_BG - 0x2000) / sizeof(uint32_t)];
-	uint32_t rop = d->de_reg[(CRIME_DE_ROP - 0x2000) / sizeof(uint32_t)];
-
-	uint32_t stipple_mode = d->de_reg[(CRIME_DE_STIPPLE_MODE - 0x2000) / sizeof(uint32_t)];
-	uint32_t pattern = d->de_reg[(CRIME_DE_STIPPLE_PAT - 0x2000) / sizeof(uint32_t)];
-	int nr_of_bits_to_strip_to_the_left = (stipple_mode >> DE_STIP_STRTIDX_SHIFT) & 31;
-	int nr_of_bits_to_strip_to_the_right = 31 - ((stipple_mode >> DE_STIP_MAXIDX_SHIFT) & 31);
-	pattern >>= nr_of_bits_to_strip_to_the_right;
-	pattern <<= nr_of_bits_to_strip_to_the_right;
-	pattern <<= nr_of_bits_to_strip_to_the_left;
-
-	int nr_of_bits_in_the_middle = 32 - nr_of_bits_to_strip_to_the_left - nr_of_bits_to_strip_to_the_right;
-
-	if (stipple_mode & 0xe0e0ffff)
-		fatal("[ sgi_de: UNIMPLEMENTED stipple_mode bits: 0x%08x ]\n", stipple_mode);
-
-	uint32_t x1 = (d->de_reg[(CRIME_DE_X_VERTEX_0 - 0x2000) / sizeof(uint32_t)] >> 16) & 0x7ff;
-	uint32_t y1 = d->de_reg[(CRIME_DE_X_VERTEX_0 - 0x2000) / sizeof(uint32_t)]& 0x7ff;
-	uint32_t x2 = (d->de_reg[(CRIME_DE_X_VERTEX_1 - 0x2000) / sizeof(uint32_t)] >> 16) & 0x7ff;
-	uint32_t y2 = d->de_reg[(CRIME_DE_X_VERTEX_1 - 0x2000) / sizeof(uint32_t)]& 0x7ff;
-	size_t x, y;
-
-	debug("[ sgi_de: STARTING DRAWING COMMAND: op = 0x%08x,"
-	    " drawmode=0x%x src_mode=0x%x dst_mode=0x%x x1=%i y1=%i"
-	    " x2=%i y2=%i fg=0x%x bg=0x%x pattern=0x%08x ]\n",
-	    op, drawmode, src_mode, dst_mode, x1, y1, x2, y2, fg, bg, pattern);
-
-	// bufdepth = 1, 2, or 4.
-	// int dst_bufdepth = 1 << ((dst_mode >> 8) & 3);
-	int src_bufdepth = 1 << ((src_mode >> 8) & 3);
-
-	bool src_is_linear = false;
-	int src_x = -1, src_y = -1;
-	int32_t step_x = 0;
-	if (drawmode & DE_DRAWMODE_XFER_EN) {
-		uint32_t addr_src = d->de_reg[(CRIME_DE_XFER_ADDR_SRC - 0x2000) / sizeof(uint32_t)];
-		uint32_t strd_src = d->de_reg[(CRIME_DE_XFER_STRD_SRC - 0x2000) / sizeof(uint32_t)];
-		step_x = d->de_reg[(CRIME_DE_XFER_STEP_X - 0x2000) / sizeof(uint32_t)];
-		int32_t step_y = d->de_reg[(CRIME_DE_XFER_STEP_Y - 0x2000) / sizeof(uint32_t)];
-		uint32_t addr_dst = d->de_reg[(CRIME_DE_XFER_ADDR_DST - 0x2000) / sizeof(uint32_t)];
-		uint32_t strd_dst = d->de_reg[(CRIME_DE_XFER_STRD_DST - 0x2000) / sizeof(uint32_t)];
-
-		src_is_linear = ((src_mode & 0x00001c00) >> 10) > 3;
-
-		if (src_is_linear) {
-			src_x = addr_src;
-			src_y = 0;
-		} else {
-			src_x = (addr_src >> 16) & 0x7ff;
-			src_y = addr_src & 0x7ff;
-		}
-
-		if (step_x != src_bufdepth || (step_y != 0 && step_y != 1)) {
-			fatal("[ sgi_de: unimplemented XFER addr_src=0x%x src_bufdepth=%i "
-				"strd_src=0x%x step_x=0x%x step_y=0x%x "
-				"addr_dst=0x%x strd_dst=0x%x ]\n",
-				addr_src, src_bufdepth, strd_src, step_x, step_y, addr_dst, strd_dst);
-
-			// exit(1);
-		}
-	}
-
-	if (!(drawmode & DE_DRAWMODE_PLANEMASK)) {
-		printf("!DE_DRAWMODE_PLANEMASK: TODO\n");
-	}
-	
-	if ((drawmode & DE_DRAWMODE_BYTEMASK) != DE_DRAWMODE_BYTEMASK) {
-		printf("not all DE_DRAWMODE_BYTEMASK set: TODO\n");
-	}
-	
-	// primitive rendering direction (not for Lines? and presumably
-	// not for Points either :-)
-	int dx = op & DE_PRIM_RL ? -1 :  1;
-	int dy = op & DE_PRIM_TB ?  1 : -1;
-
-	uint16_t saved_src_x = src_x;
-
-	/*
-	 *  Drawing is limited to 2048 x 2048 pixel space.
-	 *
-	 *  TODO: MAYBE it is really -2048 to 2027, i.e. 12 bits of
-	 *  pixel space. Perhaps it is possible to figure out
-	 *  experimentally some day, e.g. by drawing lines from
-	 *  -10,10 to 500,20 and see whether the real hardware
-	 *  interprets -10 as -10 or 0x800 - 10.
-	 */
-	uint16_t endx = (x2 + dx) & 0x7ff;
-	uint16_t endy = (y2 + dy) & 0x7ff;
-
-	int lx = abs((int)(x2 - x1)), ly = abs((int)(y2 - y1));
-	int linelen = lx > ly ? lx : ly;
-
-	switch (op & 0xff000000) {
-	case DE_PRIM_LINE:
-		if (drawmode & DE_DRAWMODE_XFER_EN)
-			fatal("[ sgi_de: XFER_EN for LINE op? ]\n");
-
-		// The PROM uses width 32, but NetBSD documents it as "half pixels".
-		// if ((op & DE_PRIM_LINE_WIDTH_MASK) != 2)
-		//	fatal("[ sgi_de: LINE_WIDTH_MASK = %i ]\n", op & DE_PRIM_LINE_WIDTH_MASK);
-
-		if (linelen == 0)
-			linelen ++;
-
-		for (int i = 0; i < ((op & DE_PRIM_LINE_SKIP_END)? linelen : linelen+1); ++i) {
-			x = (x2 * i + x1 * (linelen-i)) / linelen;
-			y = (y2 * i + y1 * (linelen-i)) / linelen;
-
-			uint32_t color = fg;
-			uint32_t oldcolor = fg;
-
-			if (drawmode & DE_DRAWMODE_ROP && rop != OPENGL_LOGIC_OP_COPY)
-				horrible_getputpixel(false, cpu, d,
-					x, y, &oldcolor, dst_mode);
-
-			bool draw = true;
-			if (drawmode & DE_DRAWMODE_LINE_STIP) {
-				if (drawmode & DE_DRAWMODE_OPAQUE_STIP)
-					color = (pattern & 0x80000000UL) ? fg : bg;
-				else
-					draw = (pattern & 0x80000000UL)? true : false;
-			}
-
-			// Raster-OP.
-			// TODO: Other ops.
-			// TODO: Should this be before or after other things?
-			if (drawmode & DE_DRAWMODE_ROP) {
-				switch (rop) {
-				case OPENGL_LOGIC_OP_COPY:
-					// color = color;
-					break;
-				case OPENGL_LOGIC_OP_XOR:
-					color = oldcolor ^ color;
-					break;
-				case OPENGL_LOGIC_OP_COPY_INVERTED:
-					color = 0xffffffff - oldcolor;
-					break;
-				default:{
-						static char rop_used[256];
-						static bool first = true;
-
-						if (first) {
-						memset(rop_used, 0, sizeof(rop_used));
-						first = false;
-						}
-						if (!rop_used[rop & 255]) {
-							rop_used[rop & 255] = 1;
-							fatal("[ sgi_de: LINE: rop[0x%02x] used! ]\n", rop & 255);
-						}
-
-						if (rop >> 8) {
-							fatal("[ sgi_de: LINE: rop > 255: 0x%08x ]\n", rop);
-						}
-					}
-				}
-			}
-
-			if (draw)
-				horrible_getputpixel(true, cpu, d,
-					x, y, &color, dst_mode);
-
-			// Rotate the stipple pattern:
-			pattern = (pattern << 1) | (pattern >> (nr_of_bits_in_the_middle-1));
-		}
-		break;
-
-	case DE_PRIM_RECTANGLE:
-		for (y = y1; y != endy; y = (y + dy) & 0x7ff) {
-			src_x = saved_src_x;
-			for (x = x1; x != endx; x = (x + dx) & 0x7ff) {
-				uint32_t color = fg;
-				uint32_t oldcolor = fg;
-
-				if (drawmode & DE_DRAWMODE_ROP && rop != OPENGL_LOGIC_OP_COPY)
-					horrible_getputpixel(false, cpu, d,
-						x, y, &oldcolor, dst_mode);
-
-				// Pixel colors copied from another source.
-				// (OpenBSD draws characters using this mechanism.)
-				if (drawmode & DE_DRAWMODE_XFER_EN)
-					horrible_getputpixel(false, cpu, d,
-						src_x, src_y, &color, src_mode);
-
-				bool draw = true;
-				if (drawmode & DE_DRAWMODE_POLY_STIP) {
-					if (drawmode & DE_DRAWMODE_OPAQUE_STIP)
-						color = (pattern & 0x80000000UL) ? fg : bg;
-					else
-						draw = (pattern & 0x80000000UL)? true : false;
-				}
-
-				// Raster-OP.
-				// TODO: Other ops.
-				// TODO: Should this be before or after other things?
-				if (drawmode & DE_DRAWMODE_ROP) {
-					switch (rop) {
-					case OPENGL_LOGIC_OP_COPY:
-						// color = color;
-						break;
-					case OPENGL_LOGIC_OP_XOR:
-						color = oldcolor ^ color;
-						break;
-					case OPENGL_LOGIC_OP_COPY_INVERTED:
-						color = 0xffffffff - oldcolor;
-						break;
-					default:{
-							static char rop_used[256];
-							static bool first = true;
-
-							if (first) {
-							memset(rop_used, 0, sizeof(rop_used));
-							first = false;
-							}
-							if (!rop_used[rop & 255]) {
-								rop_used[rop & 255] = 1;
-								fatal("[ sgi_de: RECT: rop[0x%02x] used! ]\n", rop & 255);
-							}
-
-							if (rop >> 8) {
-								fatal("[ sgi_de: RECT: rop > 255: 0x%08x ]\n", rop);
-							}
-						}
-					}
-				}
-
-				if (draw)
-					horrible_getputpixel(true, cpu, d,
-						x, y, &color, dst_mode);
-
-				// Rotate the stipple pattern:
-				pattern = (pattern << 1) | (pattern >> (nr_of_bits_in_the_middle-1));
-
-				if (src_is_linear)
-					src_x += step_x;
-				else
-					src_x = (src_x + dx) & 0x7ff;
-			}
-			
-			src_y = (src_y + dy) & 0x7ff;
-		}
-		break;
-
-	default:fatal("[ sgi_de: UNIMPLEMENTED drawing op = 0x%08x,"
-		    " x1=%i y1=%i x2=%i y2=%i fg=0x%x bg=0x%x pattern=0x%08x ]\n",
-		    op, x1, y1, x2, y2, fg, bg, pattern);
-		exit(1);
-	}
-}
-
-DEVICE_ACCESS(sgi_de)
-{
-	struct sgi_re_data *d = (struct sgi_re_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-	bool startFlag = relative_addr & CRIME_DE_START ? true : false;
-
-	relative_addr &= ~CRIME_DE_START;
-
-	idata = memory_readmax64(cpu, data, len);
-	regnr = relative_addr / sizeof(uint32_t);
-
-	relative_addr += 0x2000;
-
-	/*
-	 *  Treat all registers as read/write, by default.  Sometimes these
-	 *  are accessed as 32-bit words, sometimes as 64-bit words to access
-	 *  two adjacent registers in one operation.
-	 */
-	if (len == 8) {
-		if (writeflag == MEM_WRITE) {
-			d->de_reg[regnr] = idata >> 32ULL;
-			d->de_reg[regnr+1] = idata;
-		} else
-			odata = ((uint64_t)d->de_reg[regnr] << 32ULL) +
-			    d->de_reg[regnr+1];
-	} else if (len == 4) {
-		if (writeflag == MEM_WRITE)
-			d->de_reg[regnr] = idata;
-		else
-			odata = d->de_reg[regnr];
-	} else {
-		fatal("sgi_de: len = %i not implemented\n", len);
-		exit(1);
-	}
-
-	switch (relative_addr) {
-
-	case CRIME_DE_MODE_SRC:
-		debug("[ sgi_de: %s CRIME_DE_MODE_SRC: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_MODE_DST:
-		debug("[ sgi_de: %s CRIME_DE_MODE_DST: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_CLIPMODE:
-		debug("[ sgi_de: %s CRIME_DE_CLIPMODE: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		if (writeflag == MEM_WRITE && idata != 0)
-			fatal("[ sgi_de: TODO: non-zero CRIME_DE_CLIPMODE: 0x%016llx ]\n", idata);
-		break;
-
-	case CRIME_DE_DRAWMODE:
-		debug("[ sgi_de: %s CRIME_DE_DRAWMODE: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_SCRMASK0:
-		debug("[ sgi_de: %s CRIME_DE_SCRMASK0: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		if (writeflag == MEM_WRITE && idata != 0)
-			fatal("[ sgi_de: TODO: non-zero CRIME_DE_SCRMASK0: 0x%016llx ]\n", idata);
-		break;
-
-	case CRIME_DE_SCRMASK1:
-		debug("[ sgi_de: %s CRIME_DE_SCRMASK1: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		if (writeflag == MEM_WRITE && idata != 0)
-			fatal("[ sgi_de: TODO: non-zero CRIME_DE_SCRMASK1: 0x%016llx ]\n", idata);
-		break;
-
-	case CRIME_DE_SCRMASK2:
-		debug("[ sgi_de: %s CRIME_DE_SCRMASK2: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		if (writeflag == MEM_WRITE && idata != 0)
-			fatal("[ sgi_de: TODO: non-zero CRIME_DE_SCRMASK2: 0x%016llx ]\n", idata);
-		break;
-
-	case CRIME_DE_SCRMASK3:
-		debug("[ sgi_de: %s CRIME_DE_SCRMASK3: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		if (writeflag == MEM_WRITE && idata != 0)
-			fatal("[ sgi_de: TODO: non-zero CRIME_DE_SCRMASK3: 0x%016llx ]\n", idata);
-		break;
-
-	case CRIME_DE_SCRMASK4:
-		debug("[ sgi_de: %s CRIME_DE_SCRMASK4: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		if (writeflag == MEM_WRITE && idata != 0)
-			fatal("[ sgi_de: TODO: non-zero CRIME_DE_SCRMASK4: 0x%016llx ]\n", idata);
-		break;
-
-	case CRIME_DE_SCISSOR:
-		debug("[ sgi_de: %s CRIME_DE_SCISSOR: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		if (writeflag == MEM_WRITE && idata != 0)
-			fatal("[ sgi_de: TODO: non-zero CRIME_DE_SCISSOR: 0x%016llx ]\n", idata);
-		break;
-
-	case CRIME_DE_SCISSOR + 4:
-		// NetBSD writes 0x3fff3fff here. "High" part of SCISSOR register?
-		debug("[ sgi_de: %s CRIME_DE_SCISSOR+4: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		if (writeflag == MEM_WRITE && idata != 0x3fff3fff)
-			fatal("[ sgi_de: TODO: CRIME_DE_SCISSOR+4: 0x%016llx ]\n", idata);
-		break;
-
-	case CRIME_DE_PRIMITIVE:
-		debug("[ sgi_de: %s CRIME_DE_PRIMITIVE: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_WINOFFSET_SRC:
-		debug("[ sgi_de: %s CRIME_DE_WINOFFSET_SRC: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		if (writeflag == MEM_WRITE && idata != 0)
-			fatal("[ sgi_de: TODO: non-zero CRIME_DE_WINOFFSET_SRC: 0x%016llx ]\n", idata);
-		break;
-
-	case CRIME_DE_WINOFFSET_DST:
-		debug("[ sgi_de: %s CRIME_DE_WINOFFSET_DST: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		if (writeflag == MEM_WRITE && idata != 0)
-			fatal("[ sgi_de: TODO: non-zero CRIME_DE_WINOFFSET_DST: 0x%016llx ]\n", idata);
-		break;
-
-	case CRIME_DE_X_VERTEX_0:
-		debug("[ sgi_de: %s CRIME_DE_X_VERTEX_0: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_X_VERTEX_1:
-		debug("[ sgi_de: %s CRIME_DE_X_VERTEX_1: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_XFER_ADDR_SRC:
-		debug("[ sgi_de: %s CRIME_DE_XFER_ADDR_SRC: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_XFER_STRD_SRC:
-		debug("[ sgi_de: %s CRIME_DE_XFER_STRD_SRC: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_XFER_STEP_X:
-		debug("[ sgi_de: %s CRIME_DE_XFER_STEP_X: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_XFER_STEP_Y:
-		debug("[ sgi_de: %s CRIME_DE_XFER_STEP_Y: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_XFER_ADDR_DST:
-		debug("[ sgi_de: %s CRIME_DE_XFER_ADDR_DST: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_XFER_STRD_DST:
-		debug("[ sgi_de: %s CRIME_DE_XFER_STRD_DST: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_STIPPLE_MODE:
-		debug("[ sgi_de: %s CRIME_DE_STIPPLE_MODE: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_STIPPLE_PAT:
-		debug("[ sgi_de: %s CRIME_DE_STIPPLE_PAT: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_FG:
-		debug("[ sgi_de: %s CRIME_DE_FG: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_BG:
-		debug("[ sgi_de: %s CRIME_DE_BG: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_ROP:
-		debug("[ sgi_de: %s CRIME_DE_ROP: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_PLANEMASK:
-		debug("[ sgi_de: %s CRIME_DE_PLANEMASK: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_NULL:
-		debug("[ sgi_de: %s CRIME_DE_NULL: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_DE_FLUSH:
-		debug("[ sgi_de: %s CRIME_DE_FLUSH: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE)
-			fatal("[ sgi_de: unimplemented write to "
-			    "address 0x%llx, data=0x%016llx ]\n",
-			    (long long)relative_addr, (long long)idata);
-		else
-			fatal("[ sgi_de: unimplemented read from address"
-			    " 0x%llx ]\n", (long long)relative_addr);
-	}
-
-	if (startFlag)
-		draw_primitive(cpu, d);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_sgi_de_init():
- */
-void dev_sgi_de_init(struct memory *mem, uint64_t baseaddr, struct sgi_re_data *d)
-{
-	memory_device_register(mem, "sgi_de", baseaddr, DEV_SGI_DE_LENGTH,
-	    dev_sgi_de_access, (void *)d, DM_DEFAULT, NULL);
-}
-
-
-/****************************************************************************/
-
-/*
- *  SGI "mte", NetBSD sources describes it as a "memory transfer engine".
- *
- *  If the relative address has the 0x0800 (CRIME_DE_START) flag set, it means
- *  "go ahead with the transfer". Otherwise, it is just reads and writes of the
- *  registers.
- */
-
-void do_mte_transfer(struct cpu* cpu, struct sgi_re_data *d)
-{
-	uint32_t mode = d->mte_reg[(CRIME_MTE_MODE - 0x3000) / sizeof(uint32_t)];
-	uint32_t src0 = d->mte_reg[(CRIME_MTE_SRC0 - 0x3000) / sizeof(uint32_t)];
-	uint32_t src1 = d->mte_reg[(CRIME_MTE_SRC1 - 0x3000) / sizeof(uint32_t)];
-	uint32_t dst0 = d->mte_reg[(CRIME_MTE_DST0 - 0x3000) / sizeof(uint32_t)];
-	uint32_t dst1 = d->mte_reg[(CRIME_MTE_DST1 - 0x3000) / sizeof(uint32_t)];
-	int32_t src_y_step = d->mte_reg[(CRIME_MTE_SRC_Y_STEP - 0x3000) / sizeof(uint32_t)];
-	int32_t dst_y_step = d->mte_reg[(CRIME_MTE_DST_Y_STEP - 0x3000) / sizeof(uint32_t)];
-	uint32_t dstlen = dst1 - dst0 + 1, fill_addr;
-	unsigned char zerobuf[4096];
-	int depth = 8 << ((mode & MTE_MODE_DEPTH_MASK) >> MTE_DEPTH_SHIFT);
-	int src = (mode & MTE_MODE_SRC_BUF_MASK) >> MTE_SRC_TLB_SHIFT;
-	uint32_t bytemask = d->mte_reg[(CRIME_MTE_BYTEMASK - 0x3000) / sizeof(uint32_t)];
-	uint32_t bg = d->mte_reg[(CRIME_MTE_BG - 0x3000) / sizeof(uint32_t)];
-
-	debug("[ sgi_mte: STARTING: mode=0x%08x src0=0x%08x src1=0x%08x src_y_step=%i dst0=0x%08x,"
-	    " dst1=0x%08x dst_y_step=%i bg=0x%x bytemask=0x%x ]\n",
-	    mode,
-	    src0, src1, src_y_step,
-	    dst0, dst1, dst_y_step,
-	    bg, bytemask);
-
-	if (dst_y_step != 0 && dst_y_step != 1 && dst_y_step != -1) {
-		fatal("[ sgi_mte: TODO! unimplemented dst_y_step %i ]", dst_y_step);
-		// exit(1);
-	}
-
-	if (mode & MTE_MODE_STIPPLE) {
-		fatal("[ sgi_mte: unimplemented MTE_MODE_STIPPLE ]");
-		exit(1);
-	}
-
-	int src_tlb = (mode & MTE_MODE_SRC_BUF_MASK) >> MTE_SRC_TLB_SHIFT;
-	int dst_tlb = (mode & MTE_MODE_DST_BUF_MASK) >> MTE_DST_TLB_SHIFT;
-	
-	if (src > MTE_TLB_C) {
-		fatal("[ sgi_mte: unimplemented SRC ]");
-		exit(1);
-	}
-
-	switch (dst_tlb) {
-	case MTE_TLB_A:
-	case MTE_TLB_B:
-	case MTE_TLB_C:
-		// Used by NetBSD's crmfb_fill_rect. It puts graphical
-		// coordinates in dst0 and dst1.
-		{
-			int x1 = (dst0 >> 16) & 0xfff;
-			int y1 = dst0 & 0xfff;
-			int x2 = (dst1 >> 16) & 0xfff;
-			int y2 = dst1 & 0xfff;
-			x1 /= (depth / 8);
-			x2 /= (depth / 8);
-
-			int src_x1 = (src0 >> 16) & 0xfff;
-			int src_y1 = src0 & 0xfff;
-			// int src_x2 = (src1 >> 16) & 0xfff;
-			// int src_y2 = src1 & 0xfff;
-			src_x1 /= (depth / 8);
-			// src_x2 /= (depth / 8);
-
-			int dx = x1 > x2 ? -1 : 1;
-			int dy = y1 > y2 ? -1 : 1;
-			
-			uint32_t src_mode = (src_tlb << 10) + (((mode & MTE_MODE_DEPTH_MASK) >> MTE_DEPTH_SHIFT) << 8);
-			uint32_t dst_mode = (dst_tlb << 10) + (((mode & MTE_MODE_DEPTH_MASK) >> MTE_DEPTH_SHIFT) << 8);
-
-			// Hack. The MTE perhaps doesn't deal with colors per se,
-			// but this makes sure that we copy 32 bits when doing 32-bit
-			// transfers.
-			if (depth == 4) {
-				src_mode |= DE_MODE_TYPE_RGBA;
-				dst_mode |= DE_MODE_TYPE_RGBA;
-			}
-
-			int src_y = src_y1;
-			for (int y = y1; y != y2+dy; y += dy) {
-				int src_x = src_x1;
-				
-				for  (int x = x1; x != x2+dx; x += dx) {
-					if (mode & MTE_MODE_COPY) {
-						horrible_getputpixel(false, cpu, d,
-							src_x, src_y, &bg, src_mode);
-						src_x += dx;
-					}
-
-					horrible_getputpixel(true, cpu, d, x, y, &bg, dst_mode);
-				}
-				
-				src_y += dy;
-			}
-		}
-		break;
-	case MTE_TLB_LIN_A:
-	case MTE_TLB_LIN_B:
-		// Used by the PROM to zero-fill memory (?).
-		if (mode & MTE_MODE_COPY) {
-			fatal("[ sgi_mte: unimplemented MTE_MODE_COPY ]");
-			exit(1);
-		}
-
-		if (depth != 8) {
-			fatal("[ sgi_mte: unimplemented MTE_DEPTH_x ]");
-			exit(1);
-		}
-
-		debug("[ sgi_mte: LINEAR TRANSFER: mode=0x%08x dst0=0x%016llx,"
-		    " dst1=0x%016llx (length 0x%llx), dst_y_step=%i bg=0x%x, bytemask=0x%x ]\n",
-		    mode,
-		    (long long)dst0, (long long)dst1,
-		    (long long)dstlen, dst_y_step, (int)bg, (int)bytemask);
-
-		if (bytemask != 0xffffffff) {
-			fatal("unimplemented MTE bytemask 0x%08x\n", (int)bytemask);
-			exit(1);
-		}
-
-		/*
-		 *  Horrible hack:
-		 *
-		 *  During bootup, the PROM fills memory at 0x40000000 and
-		 *  forward. This corresponds to the lowest possible RAM address.
-		 *  However, these fills are not going via the CPU's cache,
-		 *  which contains things such as the return address on the
-		 *  stack. If we _really_ write this data in the emulator (which
-		 *  doesn't emulate the cache), it would overwrite the stack.
-		 *
-		 *  So let's not.
-		 *
-		 *  (If some guest OS or firmware variant actually depends on
-		 *  the ability to write to the start of memory this way,
-		 *  it would not work in the emulator.)
-		 */
-		// if (dst0 >= 0x40000000 && dst0 < 0x40004000 && dst1 > 0x40004000) {
-		//	dst0 += 0x4000;
-		//	dstlen -= 0x4000;
-		// }
-
-		/*
-		 *  HUH?
-		 *
-		 *  Note that due to a bug (?) in the PROM firmware when it
-		 *  is setting up the TLB entries, only every _second_ page is
-		 *  actually put correctly in the TLB. This means that even
-		 *  though it then tries to fill 0x40000000 .. 0x40007fff with
-		 *  zeroes, it only fills 0x40001000 .. 0x40001fff,
-		 *  0x40003000 .. 0x40003fff and so on!
-		 *
-		 *  So the Horrible hack above is not needed.
-		 *
-		 *  Ironic.
-		 */
-
-		memset(zerobuf, bg, dstlen < sizeof(zerobuf) ? dstlen : sizeof(zerobuf));
-		fill_addr = dst0;
-		while (dstlen != 0) {
-			uint64_t fill_len;
-			if (dstlen > sizeof(zerobuf))
-				fill_len = sizeof(zerobuf);
-			else
-				fill_len = dstlen;
-
-			uint64_t starting_page = fill_addr & ~0xfff;
-			uint64_t ending_page = (fill_addr + fill_len - 1) & ~0xfff;
-			if (starting_page != ending_page) {
-				fill_len = starting_page + 4096 - fill_addr;
-			}
-
-			// Find starting_page in the TLB in question.
-			starting_page >>= 12;
-			uint32_t *tlb = dst_tlb == MTE_TLB_LIN_A ? d->re_linear_a : d->re_linear_b;
-			bool match = false;
-			for (int i = 0; i < 32; ++i) {
-				uint32_t entry = tlb[i];
-				if (entry & 0x80000000) {
-					entry &= ~0x80000000;
-					if (entry == starting_page) {
-						match = true;
-						break;
-					}
-				}
-			}
-			
-			if (match) {
-				cpu->memory_rw(cpu, cpu->mem, fill_addr, zerobuf, fill_len,
-					MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
-			} else {
-				debug("[ sgi_mte: WARNING: address 0x%x not found in TLB? Ignoring fill. ]\n",
-					(long long)fill_addr);
-			}
-
-			fill_addr += fill_len;
-			dstlen -= sizeof(zerobuf);
-		}
-		break;
-	default:
-		fatal("[ sgi_mte: TODO! unimplemented dst_tlb 0x%x ]", dst_tlb);
-	}
-}
-
-DEVICE_ACCESS(sgi_mte)
-{
-	struct sgi_re_data *d = (struct sgi_re_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-	bool startFlag = relative_addr & CRIME_DE_START ? true : false;
-
-	relative_addr &= ~CRIME_DE_START;
-
-	idata = memory_readmax64(cpu, data, len);
-	regnr = relative_addr / sizeof(uint32_t);
-
-	relative_addr += 0x3000;
-
-	/*
-	 *  Treat all registers as read/write, by default.  Sometimes these
-	 *  are accessed as 32-bit words, sometimes as 64-bit words.
-	 *
-	 *  NOTE: The lowest bits are internally stored in the "low" (+0)
-	 *  register, and the higher bits are stored in the "+1" word.
-	 */
-	if (len == 4) {
-		if (writeflag == MEM_WRITE)
-			d->mte_reg[regnr] = idata;
-		else
-			odata = d->mte_reg[regnr];
-	} else if (len != 4) {
-		if (writeflag == MEM_WRITE) {
-			d->mte_reg[regnr+1] = idata >> 32;
-			d->mte_reg[regnr] = idata;
-		} else {
-			odata = ((uint64_t)d->mte_reg[regnr+1] << 32) +
-			    d->mte_reg[regnr];
-		}
-	} else {
-		fatal("[ sgi_mte: UNIMPLEMENTED read/write len %i ]\n", len);
-		exit(1);
-	}
-
-	switch (relative_addr) {
-
-	case CRIME_MTE_MODE:
-		debug("[ sgi_mte: %s CRIME_MTE_MODE: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_MTE_BYTEMASK:
-		debug("[ sgi_mte: %s CRIME_MTE_BYTEMASK: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_MTE_STIPPLEMASK:
-		fatal("[ sgi_mte: %s CRIME_MTE_STIPPLEMASK: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_MTE_BG:
-		debug("[ sgi_mte: %s CRIME_MTE_BG: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_MTE_SRC0:
-		debug("[ sgi_mte: %s CRIME_MTE_SRC0: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_MTE_SRC1:
-		debug("[ sgi_mte: %s CRIME_MTE_SRC1: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_MTE_DST0:
-		debug("[ sgi_mte: %s CRIME_MTE_DST0: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_MTE_DST1:
-		debug("[ sgi_mte: %s CRIME_MTE_DST1: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_MTE_SRC_Y_STEP:
-		debug("[ sgi_mte: %s CRIME_MTE_SRC_Y_STEP: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_MTE_DST_Y_STEP:
-		debug("[ sgi_mte: %s CRIME_MTE_DST_Y_STEP: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_MTE_NULL:
-		fatal("[ sgi_mte: %s CRIME_MTE_NULL: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	case CRIME_MTE_FLUSH:
-		fatal("[ sgi_mte: %s CRIME_MTE_FLUSH: 0x%016llx ]\n",
-		    writeflag == MEM_WRITE ? "write to" : "read from",
-		    writeflag == MEM_WRITE ? (long long)idata : (long long)odata);
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE)
-			fatal("[ sgi_mte: unimplemented write to "
-			    "address 0x%llx, data=0x%016llx ]\n",
-			    (long long)relative_addr, (long long)idata);
-		else
-			fatal("[ sgi_mte: unimplemented read from address"
-			    " 0x%llx ]\n", (long long)relative_addr);
-	}
-
-	if (startFlag)
-		do_mte_transfer(cpu, d);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_sgi_mte_init():
- */
-void dev_sgi_mte_init(struct memory *mem, uint64_t baseaddr, struct sgi_re_data *d)
-{
-	memory_device_register(mem, "sgi_mte", baseaddr, DEV_SGI_MTE_LENGTH,
-	    dev_sgi_mte_access, (void *)d, DM_DEFAULT, NULL);
-}
-
-
-/****************************************************************************/
-
-/*
- *  SGI "de_status".
- */
-
-DEVICE_ACCESS(sgi_de_status)
-{
-	// struct sgi_re_data *d = (struct sgi_re_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	idata = memory_readmax64(cpu, data, len);
-
-	relative_addr += 0x4000;
-
-	switch (relative_addr) {
-
-	case CRIME_DE_STATUS:	// 0x4000
-		odata = CRIME_DE_IDLE |
-			CRIME_DE_SETUP_IDLE |
-			CRIME_DE_PIXPIPE_IDLE |
-			CRIME_DE_MTE_IDLE;
-
-		/*
-		 *  TODO: Actually simulate pipeline of a number of commands?
-		 */
-		break;
-
-	case 0x4008:
-		/*  Unknown. Ignore for now.  */
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE)
-			debug("[ sgi_de_status: unimplemented write to "
-			    "address 0x%llx, data=0x%016llx ]\n",
-			    (long long)relative_addr, (long long)idata);
-		else
-			debug("[ sgi_de_status: unimplemented read from address"
-			    " 0x%llx ]\n", (long long)relative_addr);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_sgi_de_status_init():
- */
-void dev_sgi_de_status_init(struct memory *mem, uint64_t baseaddr, struct sgi_re_data *d)
-{
-	memory_device_register(mem, "sgi_de_status", baseaddr, DEV_SGI_DE_STATUS_LENGTH,
-	    dev_sgi_de_status_access, (void *)d, DM_DEFAULT, NULL);
-}
-
-
diff -Nru gxemul-0.6.2/src/devices/dev_sh4.c gxemul-0.7.0+dfsg/src/devices/dev_sh4.c
--- gxemul-0.6.2/src/devices/dev_sh4.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sh4.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,2051 @@
+/*
+ *  Copyright (C) 2006-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: SH4-specific memory mapped registers (0xf0000000 - 0xffffffff)
+ *
+ *  TODO: Among other things:
+ *
+ *	x)  Interrupt masks (msk register stuff). Are these really correct?
+ *	x)  BSC (Bus state controller).
+ *	x)  DMA: Right now there's a hack for Dreamcast emulation
+ *	x)  UBC (User Break Controller)
+ *	x)  ...
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_pci.h"
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "sh4_dmacreg.h"
+#include "timer.h"
+
+#include "thirdparty/sh4_bscreg.h"
+#include "thirdparty/sh4_cache.h"
+#include "thirdparty/sh4_exception.h"
+#include "thirdparty/sh4_intcreg.h"
+#include "thirdparty/sh4_mmu.h"
+#include "thirdparty/sh4_pcicreg.h"
+#include "thirdparty/sh4_rtcreg.h"
+#include "thirdparty/sh4_scifreg.h"
+#include "thirdparty/sh4_scireg.h"
+#include "thirdparty/sh4_tmureg.h"
+
+
+#define	SH4_REG_BASE		0xff000000
+#define	SH4_TICK_SHIFT		14
+#define	N_SH4_TIMERS		3
+
+/*  PCI stuff:  */
+#define	N_PCIC_REGS			(0x224 / sizeof(uint32_t))
+#define	N_PCIC_IRQS			16
+#define	PCIC_REG(addr)			((addr - SH4_PCIC) / sizeof(uint32_t))
+#define	PCI_VENDOR_HITACHI		0x1054
+#define	PCI_PRODUCT_HITACHI_SH7751	0x3505
+#define	PCI_PRODUCT_HITACHI_SH7751R	0x350e   
+
+#define	SCIF_TX_FIFO_SIZE	16
+#define	SCIF_DELAYED_TX_VALUE	2	/*  2 to be safe, 1 = fast but buggy  */
+
+// Clock/occilation related
+#define SH4_CPG_FRQCR		0xffc00000	/* 16-bit */
+#define SH4_CPG_STBCR 		0xffc00004	/* 8-bit */
+#define SH4_CPG_WTCNT 		0xffc00008	/* 8/16-bit */
+#define SH4_CPG_WTCSR 		0xffc0000c	/* 8/16-bit */
+#define SH4_CPG_STBCR2 		0xffc00010	/* 8-bit */
+
+
+struct sh4_data {
+	/*  Store Queues:  */
+	uint8_t		sq[32 * 2];
+
+	/*  SCIF (Serial controller):  */
+	uint16_t	scif_smr;
+	uint8_t		scif_brr;
+	uint16_t	scif_scr;
+	uint16_t	scif_ssr;
+	uint16_t	scif_fcr;
+	uint16_t	scif_lsr;
+	int		scif_delayed_tx;
+	int		scif_console_handle;
+	uint8_t		scif_tx_fifo[SCIF_TX_FIFO_SIZE + 1];
+	size_t		scif_tx_fifo_cursize;
+	struct interrupt scif_tx_irq;
+	struct interrupt scif_rx_irq;
+	int		scif_tx_irq_asserted;
+	int		scif_rx_irq_asserted;
+
+	/*  Bus State Controller:  */
+	uint32_t	bsc_bcr1;
+	uint16_t	bsc_bcr2;
+	uint16_t	bsc_bcr3;	/*  SH7751R  */
+	uint32_t	bsc_wcr1;
+	uint32_t	bsc_wcr2;
+	uint32_t	bsc_wcr3;
+	uint32_t	bsc_mcr;
+	uint16_t	bsc_pcr;
+	uint16_t	bsc_rtcsr;
+	uint16_t	bsc_rtcor;
+	uint16_t	bsc_rfcr;
+
+	/*  CPG:  */
+	uint16_t	cpg_frqcr;
+	uint8_t		cpg_stbcr;
+	uint16_t	cpg_wtcnt;
+	uint16_t	cpg_wtcsr;
+	uint8_t		cpg_stbcr2;
+
+	/*  GPIO:  */
+	uint32_t	pctra;		/*  Port Control Register A  */
+	uint32_t	pdtra;		/*  Port Data Register A  */
+	uint32_t	pctrb;		/*  Port Control Register B  */
+	uint32_t	pdtrb;		/*  Port Data Register B  */
+	uint16_t	bsc_gpioic;
+
+	/*  PCIC (PCI controller):  */
+	struct pci_data	*pci_data;
+	struct interrupt cpu_pcic_interrupt[N_PCIC_IRQS];
+	uint32_t	pcic_reg[N_PCIC_REGS];
+
+	/*  SCI (serial interface):  */
+	int		sci_bits_outputed;
+	int		sci_bits_read;
+	uint8_t		sci_scsptr;
+	uint8_t		sci_curbyte;
+	uint8_t		sci_cur_addr;
+
+	/*  SD-RAM:  */
+	uint16_t	sdmr2;
+	uint16_t	sdmr3;
+
+	/*  Timer Management Unit:  */
+	struct timer	*sh4_timer;
+	struct interrupt timer_irq[4];
+	uint32_t	tocr;
+	uint32_t	tstr;
+	uint32_t	tcnt[N_SH4_TIMERS];
+	uint32_t	tcor[N_SH4_TIMERS];
+	uint32_t	tcr[N_SH4_TIMERS];
+	int		timer_interrupts_pending[N_SH4_TIMERS];
+	double		timer_hz[N_SH4_TIMERS];
+
+	/*  RTC:  */
+	uint32_t	rtc_reg[14];	/*  Excluding rcr1 and rcr2  */
+	uint8_t		rtc_rcr1;
+	uint8_t		rtc_rcr2;
+};
+
+
+#define	SH4_PSEUDO_TIMER_HZ	110.0
+
+
+/*
+ *  sh4_timer_tick():
+ *
+ *  This function is called SH4_PSEUDO_TIMER_HZ times per real-world second.
+ *  Its job is to update the SH4 timer counters, and if necessary, increase
+ *  the number of pending interrupts.
+ *
+ *  Also, RAM Refresh is also faked here.
+ */
+static void sh4_timer_tick(struct timer *t, void *extra)
+{
+	struct sh4_data *d = (struct sh4_data *) extra;
+	int i;
+
+	/*  Fake RAM refresh:  */
+	d->bsc_rfcr ++;
+	if (d->bsc_rtcsr & (RTCSR_CMIE | RTCSR_OVIE)) {
+		fatal("sh4: RTCSR_CMIE | RTCSR_OVIE: TODO\n");
+		/*  TODO: Implement refresh interrupts etc.  */
+		exit(1);
+	}
+
+	/*  Timer interrupts:  */
+	for (i=0; i<N_SH4_TIMERS; i++) {
+		int32_t old = d->tcnt[i];
+
+		/*  printf("tcnt[%i] = %08x   tcor[%i] = %08x\n",
+		    i, d->tcnt[i], i, d->tcor[i]);  */
+
+		/*  Only update timers that are currently started:  */
+		if (!(d->tstr & (TSTR_STR0 << i)))
+			continue;
+
+		/*  Update the current count:  */
+		d->tcnt[i] -= (uint32_t) (d->timer_hz[i] / SH4_PSEUDO_TIMER_HZ);
+
+		/*  Has the timer underflowed?  */
+		if ((int32_t)d->tcnt[i] < 0 && old >= 0) {
+			d->tcr[i] |= TCR_UNF;
+
+			if (d->tcr[i] & TCR_UNIE)
+				d->timer_interrupts_pending[i] ++;
+
+			/*
+			 *  Set tcnt[i] to tcor[i]. Note: Since this function
+			 *  is only called now and then, adding tcor[i] to
+			 *  tcnt[i] produces more correct values for long
+			 *  running timers.
+			 */
+			d->tcnt[i] += d->tcor[i];
+
+			/*  At least make sure that tcnt is non-negative...  */
+			if ((int32_t)d->tcnt[i] < 0)
+				d->tcnt[i] = 0;
+		}
+	}
+}
+
+
+static void sh4_pcic_interrupt_assert(struct interrupt *interrupt)
+{
+	struct sh4_data *d = (struct sh4_data *) interrupt->extra;
+	INTERRUPT_ASSERT(d->cpu_pcic_interrupt[interrupt->line]);
+}
+static void sh4_pcic_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct sh4_data *d = (struct sh4_data *) interrupt->extra;
+	INTERRUPT_DEASSERT(d->cpu_pcic_interrupt[interrupt->line]);
+}
+
+
+static void scif_reassert_interrupts(struct sh4_data *d)
+{
+	int old_tx_asserted = d->scif_tx_irq_asserted;
+	int old_rx_asserted = d->scif_rx_irq_asserted;
+
+	d->scif_rx_irq_asserted =
+	    d->scif_scr & SCSCR2_RIE && d->scif_ssr & SCSSR2_DR;
+
+	if (d->scif_rx_irq_asserted && !old_rx_asserted)
+		INTERRUPT_ASSERT(d->scif_rx_irq);
+	else if (!d->scif_rx_irq_asserted && old_rx_asserted)
+		INTERRUPT_DEASSERT(d->scif_rx_irq);
+
+	d->scif_tx_irq_asserted =
+	    d->scif_scr & SCSCR2_TIE &&
+	    d->scif_ssr & (SCSSR2_TDFE | SCSSR2_TEND);
+
+	if (d->scif_tx_irq_asserted && !old_tx_asserted)
+		INTERRUPT_ASSERT(d->scif_tx_irq);
+	else if (!d->scif_tx_irq_asserted && old_tx_asserted)
+		INTERRUPT_DEASSERT(d->scif_tx_irq);
+}
+
+
+DEVICE_TICK(sh4)
+{
+	struct sh4_data *d = (struct sh4_data *) extra;
+	unsigned int i;
+
+	/*
+	 *  Serial controller interrupts:
+	 *
+	 *  RX: Cause interrupt if any char is available.
+	 *  TX: Send entire TX FIFO contents, and interrupt.
+	 */
+	if (console_charavail(d->scif_console_handle))
+		d->scif_ssr |= SCSSR2_DR;
+	else
+		d->scif_ssr &= ~SCSSR2_DR;
+
+	if (d->scif_delayed_tx) {
+		if (--d->scif_delayed_tx == 0) {
+			/*  Send TX FIFO contents:  */
+			for (i=0; i<d->scif_tx_fifo_cursize; i++)
+				console_putchar(d->scif_console_handle,
+				    d->scif_tx_fifo[i]);
+
+			/*  Clear FIFO:  */
+			d->scif_tx_fifo_cursize = 0;
+
+			/*  Done sending; cause a transmit end interrupt:  */
+			d->scif_ssr |= SCSSR2_TDFE | SCSSR2_TEND;
+		}
+	}
+
+	scif_reassert_interrupts(d);
+
+	/*  Timer interrupts:  */
+	for (i=0; i<N_SH4_TIMERS; i++)
+		if (d->timer_interrupts_pending[i] > 0) {
+			INTERRUPT_ASSERT(d->timer_irq[i]);
+			d->tcr[i] |= TCR_UNF;
+		}
+}
+
+
+/*
+ *  sh4_dmac_transfer():
+ *
+ *  Called whenever a DMA transfer is to be executed.
+ *  Clears the lowest bit of the corresponding channel's CHCR when done.
+ */
+void sh4_dmac_transfer(struct cpu *cpu, struct sh4_data *d, int channel)
+{
+	/*  According to the SH7760 manual, bits 31..29 are ignored in  */
+	/*  both the SAR and DAR.  */
+	uint32_t sar = cpu->cd.sh.dmac_sar[channel] & 0x1fffffff;
+	uint32_t dar = cpu->cd.sh.dmac_dar[channel] & 0x1fffffff;
+	uint32_t count = cpu->cd.sh.dmac_tcr[channel] & 0x1fffffff;
+	uint32_t chcr = cpu->cd.sh.dmac_chcr[channel];
+	int transmit_size = 1;
+	int src_delta = 0, dst_delta = 0;
+	int cause_interrupt = chcr & CHCR_IE;
+
+	/*  DMAC not enabled? Then just return.  */
+	if (!(chcr & CHCR_TD))
+		return;
+
+	/*  Transfer End already set? Then don't transfer again.  */
+	if (chcr & CHCR_TE)
+		return;
+
+	/*  Special case: 0 means 16777216:  */
+	if (count == 0)
+		count = 16777216;
+
+	switch (chcr & CHCR_TS) {
+	case CHCR_TS_8BYTE: transmit_size = 8; break;
+	case CHCR_TS_1BYTE: transmit_size = 1; break;
+	case CHCR_TS_2BYTE: transmit_size = 2; break;
+	case CHCR_TS_4BYTE: transmit_size = 4; break;
+	case CHCR_TS_32BYTE: transmit_size = 32; break;
+	default: fatal("Unimplemented transmit size?! CHCR[%i] = 0x%08x\n",
+	    channel, chcr);
+	exit(1);
+	}
+
+	switch (chcr & CHCR_DM) {
+	case CHCR_DM_FIXED:       dst_delta = 0; break;
+	case CHCR_DM_INCREMENTED: dst_delta = 1; break;
+	case CHCR_DM_DECREMENTED: dst_delta = -1; break;
+	default: fatal("Unimplemented destination delta?! CHCR[%i] = 0x%08x\n",
+	    channel, chcr);
+	exit(1);
+	}
+
+	switch (chcr & CHCR_SM) {
+	case CHCR_SM_FIXED:       src_delta = 0; break;
+	case CHCR_SM_INCREMENTED: src_delta = 1; break;
+	case CHCR_SM_DECREMENTED: src_delta = -1; break;
+	default: fatal("Unimplemented source delta?! CHCR[%i] = 0x%08x\n",
+	    channel, chcr);
+	exit(1);
+	}
+
+	src_delta *= transmit_size;
+	dst_delta *= transmit_size;
+
+#ifdef SH4_DEBUG
+	fatal("|SH4 DMA transfer, channel %i\n", channel);
+	fatal("|Source addr:      0x%08x (delta %i)\n", (int) sar, src_delta);
+	fatal("|Destination addr: 0x%08x (delta %i)\n", (int) dar, dst_delta);
+	fatal("|Count:            0x%08x\n", (int) count);
+	fatal("|Transmit size:    0x%08x\n", (int) transmit_size);
+	fatal("|Interrupt:        %s\n", cause_interrupt? "yes" : "no");
+#endif
+
+	switch (chcr & CHCR_RS) {
+	case 0x200:
+		/*
+		 *  Single Address Mode
+		 *  External Address Space => external device
+		 */
+
+		// Avoid compiler warnings about unused sar and dar.
+		(void)sar;
+		(void)dar;
+
+		/*  Note: No transfer is done here! It is up to the
+		    external device to do the transfer itself!  */
+		break;
+
+	default:fatal("Unimplemented SH4 RS DMAC: 0x%08x\n",
+		    (int) (chcr & CHCR_RS));
+		exit(1);
+	}
+
+	if (cause_interrupt) {
+		fatal("TODO: sh4 dmac interrupt!\n");
+		exit(1);
+	}
+}
+
+
+/*
+ *  sh4_sci_cmd():
+ *
+ *  Handle a SCI command byte.
+ *
+ *  Bit:   Meaning:
+ *   7      Ignored (usually 1?)
+ *   6      0=Write, 1=Read
+ *   5      AD: Address transfer
+ *   4      DT: Data transfer
+ *   3..0   Data or address bits
+ */
+static void sh4_sci_cmd(struct sh4_data *d, struct cpu *cpu)
+{
+	uint8_t cmd = d->sci_curbyte;
+	int writeflag = cmd & 0x40? 0 : 1;
+	int address_transfer;
+
+	/*  fatal("[ CMD BYTE %02x ]\n", cmd);  */
+
+	if (!(cmd & 0x80)) {
+		fatal("SCI cmd bit 7 not set? TODO\n");
+		exit(1);
+	}
+
+	if ((cmd & 0x30) == 0x20)
+		address_transfer = 1;
+	else if ((cmd & 0x30) == 0x10)
+		address_transfer = 0;
+	else {
+		fatal("SCI: Neither data nor address transfer? TODO\n");
+		exit(1);
+	}
+
+	if (address_transfer)
+		d->sci_cur_addr = cmd & 0x0f;
+
+	if (!writeflag) {
+		/*  Read data from the current address:  */
+		uint8_t data_byte;
+
+		cpu->memory_rw(cpu, cpu->mem, SCI_DEVICE_BASE + d->sci_cur_addr,
+		    &data_byte, 1, MEM_READ, PHYSICAL);
+
+		debug("[ SCI: read addr=%x data=%x ]\n",
+		    d->sci_cur_addr, data_byte);
+
+		d->sci_curbyte = data_byte;
+
+		/*  Set bit 7 right away:  */
+		d->sci_scsptr &= ~SCSPTR_SPB1DT;
+		if (data_byte & 0x80)
+			d->sci_scsptr |= SCSPTR_SPB1DT;
+	}
+
+	if (writeflag && !address_transfer) {
+		/*  Write the 4 data bits to the current address:  */
+		uint8_t data_byte = cmd & 0x0f;
+
+		debug("[ SCI: write addr=%x data=%x ]\n",
+		    d->sci_cur_addr, data_byte);
+
+		cpu->memory_rw(cpu, cpu->mem, SCI_DEVICE_BASE + d->sci_cur_addr,
+		    &data_byte, 1, MEM_WRITE, PHYSICAL);
+	}
+}
+
+
+/*
+ *  sh4_sci_access():
+ *
+ *  Reads or writes a bit via the SH4's serial interface. If writeflag is
+ *  non-zero, input is used. If writeflag is zero, a bit is outputed as
+ *  the return value from this function.
+ */
+static uint8_t sh4_sci_access(struct sh4_data *d, struct cpu *cpu,
+	int writeflag, uint8_t input)
+{
+	if (writeflag) {
+		/*  WRITE:  */
+		int clockpulse;
+		uint8_t old = d->sci_scsptr;
+		d->sci_scsptr = input;
+
+		/*
+		 *  Clock pulse (SCSPTR_SPB0DT going from 0 to 1,
+		 *  when SCSPTR_SPB0IO was already set):
+		 */
+		clockpulse = old & SCSPTR_SPB0IO &&
+		    d->sci_scsptr & SCSPTR_SPB0DT &&
+		    !(old & SCSPTR_SPB0DT);
+
+		if (!clockpulse)
+			return 0;
+
+		/*  Are we in output or input mode?  */
+		if (d->sci_scsptr & SCSPTR_SPB1IO) {
+			/*  Output:  */
+			int bit = d->sci_scsptr & SCSPTR_SPB1DT? 1 : 0;
+			d->sci_curbyte <<= 1;
+			d->sci_curbyte |= bit;
+			d->sci_bits_outputed ++;
+			if (d->sci_bits_outputed == 8) {
+				/*  4 control bits and 4 address/data bits have
+				    been written.  */
+				sh4_sci_cmd(d, cpu);
+				d->sci_bits_outputed = 0;
+			}
+		} else {
+			/*  Input:  */
+			int bit;
+			d->sci_bits_read ++;
+			d->sci_bits_read &= 7;
+
+			bit = d->sci_curbyte & (0x80 >> d->sci_bits_read);
+
+			d->sci_scsptr &= ~SCSPTR_SPB1DT;
+			if (bit)
+				d->sci_scsptr |= SCSPTR_SPB1DT;
+		}
+
+		/*  Return (value doesn't matter).  */
+		return 0;
+	} else {
+		/*  READ:  */
+		return d->sci_scsptr;
+	}
+}
+
+
+DEVICE_ACCESS(sh4_itlb_aa)
+{
+	uint64_t idata = 0, odata = 0;
+	int e = (relative_addr & SH4_ITLB_E_MASK) >> SH4_ITLB_E_SHIFT;
+
+	if (writeflag == MEM_WRITE) {
+		int safe_to_invalidate = 0;
+		uint32_t old_hi = cpu->cd.sh.itlb_hi[e];
+		if ((cpu->cd.sh.itlb_lo[e] & SH4_PTEL_SZ_MASK)==SH4_PTEL_SZ_4K)
+			safe_to_invalidate = 1;
+
+		idata = memory_readmax64(cpu, data, len);
+		cpu->cd.sh.itlb_hi[e] &=
+		    ~(SH4_PTEH_VPN_MASK | SH4_PTEH_ASID_MASK);
+		cpu->cd.sh.itlb_hi[e] |= (idata &
+		    (SH4_ITLB_AA_VPN_MASK | SH4_ITLB_AA_ASID_MASK));
+		cpu->cd.sh.itlb_lo[e] &= ~SH4_PTEL_V;
+		if (idata & SH4_ITLB_AA_V)
+			cpu->cd.sh.itlb_lo[e] |= SH4_PTEL_V;
+
+		/*  Invalidate if this ITLB entry previously belonged to the
+		    currently running process, or if it was shared:  */
+		if (cpu->cd.sh.ptel & SH4_PTEL_SH ||
+		    (old_hi & SH4_ITLB_AA_ASID_MASK) ==
+		    (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) {
+			if (safe_to_invalidate)
+				cpu->invalidate_translation_caches(cpu,
+				    old_hi & ~0xfff, INVALIDATE_VADDR);
+			else
+				cpu->invalidate_translation_caches(cpu,
+				    0, INVALIDATE_ALL);
+		}
+	} else {
+		odata = cpu->cd.sh.itlb_hi[e] &
+		    (SH4_ITLB_AA_VPN_MASK | SH4_ITLB_AA_ASID_MASK);
+		if (cpu->cd.sh.itlb_lo[e] & SH4_PTEL_V)
+			odata |= SH4_ITLB_AA_V;
+		memory_writemax64(cpu, data, len, odata);
+	}
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(sh4_itlb_da1)
+{
+	uint32_t mask = SH4_PTEL_SH | SH4_PTEL_C | SH4_PTEL_SZ_MASK |
+	    SH4_PTEL_PR_MASK | SH4_PTEL_V | 0x1ffffc00;
+	uint64_t idata = 0, odata = 0;
+	int e = (relative_addr & SH4_ITLB_E_MASK) >> SH4_ITLB_E_SHIFT;
+
+	if (relative_addr & 0x800000) {
+		fatal("sh4_itlb_da1: TODO: da2 area\n");
+		exit(1);
+	}
+
+	if (writeflag == MEM_WRITE) {
+		uint32_t old_lo = cpu->cd.sh.itlb_lo[e];
+		int safe_to_invalidate = 0;
+		if ((cpu->cd.sh.itlb_lo[e] & SH4_PTEL_SZ_MASK)==SH4_PTEL_SZ_4K)
+			safe_to_invalidate = 1;
+
+		idata = memory_readmax64(cpu, data, len);
+		cpu->cd.sh.itlb_lo[e] &= ~mask;
+		cpu->cd.sh.itlb_lo[e] |= (idata & mask);
+
+		/*  Invalidate if this ITLB entry belongs to the
+		    currently running process, or if it was shared:  */
+		if (old_lo & SH4_PTEL_SH ||
+		    (cpu->cd.sh.itlb_hi[e] & SH4_ITLB_AA_ASID_MASK) ==
+		    (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) {
+			if (safe_to_invalidate)
+				cpu->invalidate_translation_caches(cpu,
+				    cpu->cd.sh.itlb_hi[e] & ~0xfff,
+				    INVALIDATE_VADDR);
+			else
+				cpu->invalidate_translation_caches(cpu,
+				    0, INVALIDATE_ALL);
+		}
+	} else {
+		odata = cpu->cd.sh.itlb_lo[e] & mask;
+		memory_writemax64(cpu, data, len, odata);
+	}
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(sh4_utlb_aa)
+{
+	uint64_t idata = 0, odata = 0;
+	int i, e = (relative_addr & SH4_UTLB_E_MASK) >> SH4_UTLB_E_SHIFT;
+	int a = relative_addr & SH4_UTLB_A;
+
+	if (writeflag == MEM_WRITE) {
+		int n_hits = 0;
+		int safe_to_invalidate = 0;
+		uint32_t vaddr_to_invalidate = 0;
+
+		idata = memory_readmax64(cpu, data, len);
+		if (a) {
+			for (i=-SH_N_ITLB_ENTRIES; i<SH_N_UTLB_ENTRIES; i++) {
+				uint32_t lo, hi;
+				uint32_t mask = 0xfffff000;
+				int sh;
+
+				if (i < 0) {
+					lo = cpu->cd.sh.itlb_lo[
+					    i + SH_N_ITLB_ENTRIES];
+					hi = cpu->cd.sh.itlb_hi[
+					    i + SH_N_ITLB_ENTRIES];
+				} else {
+					lo = cpu->cd.sh.utlb_lo[i];
+					hi = cpu->cd.sh.utlb_hi[i];
+				}
+
+				sh = lo & SH4_PTEL_SH;
+				if (!(lo & SH4_PTEL_V))
+					continue;
+
+				switch (lo & SH4_PTEL_SZ_MASK) {
+				case SH4_PTEL_SZ_1K:  mask = 0xfffffc00; break;
+				case SH4_PTEL_SZ_64K: mask = 0xffff0000; break;
+				case SH4_PTEL_SZ_1M:  mask = 0xfff00000; break;
+				}
+
+				if ((hi & mask) != (idata & mask))
+					continue;
+
+				if ((lo & SH4_PTEL_SZ_MASK) ==
+				    SH4_PTEL_SZ_4K) {
+					safe_to_invalidate = 1;
+					vaddr_to_invalidate = hi & mask;
+				}
+
+				if (!sh && (hi & SH4_PTEH_ASID_MASK) !=
+				    (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK))
+					continue;
+
+				if (i < 0) {
+					cpu->cd.sh.itlb_lo[i +
+					    SH_N_ITLB_ENTRIES] &= ~SH4_PTEL_V;
+					if (idata & SH4_UTLB_AA_V)
+						cpu->cd.sh.itlb_lo[
+						    i+SH_N_ITLB_ENTRIES] |=
+						    SH4_PTEL_V;
+				} else {
+					cpu->cd.sh.utlb_lo[i] &=
+					    ~(SH4_PTEL_D | SH4_PTEL_V);
+					if (idata & SH4_UTLB_AA_D)
+						cpu->cd.sh.utlb_lo[i] |=
+						    SH4_PTEL_D;
+					if (idata & SH4_UTLB_AA_V)
+						cpu->cd.sh.utlb_lo[i] |=
+						    SH4_PTEL_V;
+				}
+
+				if (i >= 0)
+					n_hits ++;
+			}
+
+			if (n_hits > 1)
+				sh_exception(cpu,
+				    EXPEVT_RESET_TLB_MULTI_HIT, 0, 0);
+		} else {
+			if ((cpu->cd.sh.utlb_lo[e] & SH4_PTEL_SZ_MASK) ==
+			    SH4_PTEL_SZ_4K) {
+				safe_to_invalidate = 1;
+				vaddr_to_invalidate =
+				    cpu->cd.sh.utlb_hi[e] & ~0xfff;
+			}
+
+			cpu->cd.sh.utlb_hi[e] &=
+			    ~(SH4_PTEH_VPN_MASK | SH4_PTEH_ASID_MASK);
+			cpu->cd.sh.utlb_hi[e] |= (idata &
+			    (SH4_UTLB_AA_VPN_MASK | SH4_UTLB_AA_ASID_MASK));
+
+			cpu->cd.sh.utlb_lo[e] &= ~(SH4_PTEL_D | SH4_PTEL_V);
+			if (idata & SH4_UTLB_AA_D)
+				cpu->cd.sh.utlb_lo[e] |= SH4_PTEL_D;
+			if (idata & SH4_UTLB_AA_V)
+				cpu->cd.sh.utlb_lo[e] |= SH4_PTEL_V;
+		}
+
+		if (safe_to_invalidate)
+			cpu->invalidate_translation_caches(cpu,
+			    vaddr_to_invalidate, INVALIDATE_VADDR);
+		else
+			cpu->invalidate_translation_caches(cpu, 0,
+			    INVALIDATE_ALL);
+	} else {
+		odata = cpu->cd.sh.utlb_hi[e] &
+		    (SH4_UTLB_AA_VPN_MASK | SH4_UTLB_AA_ASID_MASK);
+		if (cpu->cd.sh.utlb_lo[e] & SH4_PTEL_D)
+			odata |= SH4_UTLB_AA_D;
+		if (cpu->cd.sh.utlb_lo[e] & SH4_PTEL_V)
+			odata |= SH4_UTLB_AA_V;
+		memory_writemax64(cpu, data, len, odata);
+	}
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(sh4_utlb_da1)
+{
+	uint32_t mask = SH4_PTEL_WT | SH4_PTEL_SH | SH4_PTEL_D | SH4_PTEL_C
+	    | SH4_PTEL_SZ_MASK | SH4_PTEL_PR_MASK | SH4_PTEL_V | 0x1ffffc00;
+	uint64_t idata = 0, odata = 0;
+	int e = (relative_addr & SH4_UTLB_E_MASK) >> SH4_UTLB_E_SHIFT;
+
+	if (relative_addr & 0x800000) {
+		fatal("sh4_utlb_da1: TODO: da2 area\n");
+		exit(1);
+	}
+
+	if (writeflag == MEM_WRITE) {
+		uint32_t old_lo = cpu->cd.sh.utlb_lo[e];
+		int safe_to_invalidate = 0;
+		if ((cpu->cd.sh.utlb_lo[e] & SH4_PTEL_SZ_MASK)==SH4_PTEL_SZ_4K)
+			safe_to_invalidate = 1;
+
+		idata = memory_readmax64(cpu, data, len);
+		cpu->cd.sh.utlb_lo[e] &= ~mask;
+		cpu->cd.sh.utlb_lo[e] |= (idata & mask);
+
+		/*  Invalidate if this UTLB entry belongs to the
+		    currently running process, or if it was shared:  */
+		if (old_lo & SH4_PTEL_SH ||
+		    (cpu->cd.sh.utlb_hi[e] & SH4_ITLB_AA_ASID_MASK) ==
+		    (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) {
+			if (safe_to_invalidate)
+				cpu->invalidate_translation_caches(cpu,
+				    cpu->cd.sh.utlb_hi[e] & ~0xfff,
+				    INVALIDATE_VADDR);
+			else
+				cpu->invalidate_translation_caches(cpu,
+				    0, INVALIDATE_ALL);
+		}
+	} else {
+		odata = cpu->cd.sh.utlb_lo[e] & mask;
+		memory_writemax64(cpu, data, len, odata);
+	}
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(sh4_pcic)
+{
+	struct sh4_data *d = (struct sh4_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	relative_addr += SH4_PCIC;
+
+	/*  Register read/write:  */
+	if (writeflag == MEM_WRITE)
+		d->pcic_reg[PCIC_REG(relative_addr)] = idata;
+	else
+		odata = d->pcic_reg[PCIC_REG(relative_addr)];
+
+	/*  Special cases:  */
+
+	switch (relative_addr) {
+
+	case SH4_PCICONF0:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ sh4_pcic: TODO: Write to SH4_PCICONF0? ]\n");
+			exit(1);
+		} else {
+			if (strcmp(cpu->cd.sh.cpu_type.name, "SH7751") == 0) {
+				odata = PCI_ID_CODE(PCI_VENDOR_HITACHI,
+				    PCI_PRODUCT_HITACHI_SH7751);
+			} else if (strcmp(cpu->cd.sh.cpu_type.name,
+			    "SH7751R") == 0) {
+				odata = PCI_ID_CODE(PCI_VENDOR_HITACHI,
+				    PCI_PRODUCT_HITACHI_SH7751R);
+			} else {
+				fatal("sh4_pcic: TODO: PCICONF0 read for"
+				    " unimplemented CPU type?\n");
+				exit(1);
+			}
+		}
+		break;
+
+	case SH4_PCICONF1:
+	case SH4_PCICONF2:
+	case SH4_PCICR:
+	case SH4_PCIBCR1:
+	case SH4_PCIBCR2:
+	case SH4_PCIBCR3:
+	case SH4_PCIWCR1:
+	case SH4_PCIWCR2:
+	case SH4_PCIWCR3:
+	case SH4_PCIMCR:
+		break;
+
+	case SH4_PCICONF5:
+		/*  Hardcoded to what OpenBSD/landisk uses:  */
+		if (writeflag == MEM_WRITE && idata != 0xac000000) {
+			fatal("sh4_pcic: SH4_PCICONF5 unknown value"
+			    " 0x%" PRIx32"\n", (uint32_t) idata);
+			exit(1);
+		}
+		break;
+
+	case SH4_PCICONF6:
+		/*  Hardcoded to what OpenBSD/landisk uses:  */
+		if (writeflag == MEM_WRITE && idata != 0x8c000000) {
+			fatal("sh4_pcic: SH4_PCICONF6 unknown value"
+			    " 0x%" PRIx32"\n", (uint32_t) idata);
+			exit(1);
+		}
+		break;
+
+	case SH4_PCILSR0:
+		/*  Hardcoded to what OpenBSD/landisk uses:  */
+		if (writeflag == MEM_WRITE && idata != ((64 - 1) << 20)) {
+			fatal("sh4_pcic: SH4_PCILSR0 unknown value"
+			    " 0x%" PRIx32"\n", (uint32_t) idata);
+			exit(1);
+		}
+		break;
+
+	case SH4_PCILAR0:
+		/*  Hardcoded to what OpenBSD/landisk uses:  */
+		if (writeflag == MEM_WRITE && idata != 0xac000000) {
+			fatal("sh4_pcic: SH4_PCILAR0 unknown value"
+			    " 0x%" PRIx32"\n", (uint32_t) idata);
+			exit(1);
+		}
+		break;
+
+	case SH4_PCILSR1:
+		/*  Hardcoded to what OpenBSD/landisk uses:  */
+		if (writeflag == MEM_WRITE && idata != ((64 - 1) << 20)) {
+			fatal("sh4_pcic: SH4_PCILSR1 unknown value"
+			    " 0x%" PRIx32"\n", (uint32_t) idata);
+			exit(1);
+		}
+		break;
+
+	case SH4_PCILAR1:
+		/*  Hardcoded to what OpenBSD/landisk uses:  */
+		if (writeflag == MEM_WRITE && idata != 0xac000000) {
+			fatal("sh4_pcic: SH4_PCILAR1 unknown value"
+			    " 0x%" PRIx32"\n", (uint32_t) idata);
+			exit(1);
+		}
+		break;
+
+	case SH4_PCIMBR:
+		if (writeflag == MEM_WRITE && idata != SH4_PCIC_MEM) {
+			fatal("sh4_pcic: PCIMBR set to 0x%" PRIx32", not"
+			    " 0x%" PRIx32"? TODO\n", (uint32_t) idata,
+			    (uint32_t) SH4_PCIC_MEM);
+			exit(1);
+		}
+		break;
+
+	case SH4_PCIIOBR:
+		if (writeflag == MEM_WRITE && idata != SH4_PCIC_IO) {
+			fatal("sh4_pcic: PCIIOBR set to 0x%" PRIx32", not"
+			    " 0x%" PRIx32"? TODO\n", (uint32_t) idata,
+			    (uint32_t) SH4_PCIC_IO);
+			exit(1);
+		}
+		break;
+
+	case SH4_PCIPAR:
+		/*  PCI bus access Address Register:  */
+		{
+			int bus  = (idata >> 16) & 0xff;
+			int dev  = (idata >> 11) & 0x1f;
+			int func = (idata >>  8) &    7;
+			int reg  =  idata        & 0xff;
+			bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
+		}
+		break;
+
+	case SH4_PCIPDR:
+		/*  PCI bus access Data Register:  */
+		bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
+		    &odata : &idata, len, writeflag);
+		break;
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ sh4_pcic: read from addr 0x%x: TODO ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ sh4_pcic: write to addr 0x%x: 0x%x: TODO ]\n",
+			    (int)relative_addr, (int)idata);
+		}
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(sh4_sq)
+{
+	struct sh4_data *d = (struct sh4_data *) extra;
+	size_t i;
+
+	if (writeflag == MEM_WRITE) {
+		for (i=0; i<len; i++)
+			d->sq[(relative_addr + i) % sizeof(d->sq)] = data[i];
+	} else {
+		for (i=0; i<len; i++)
+			data[i] = d->sq[(relative_addr + i) % sizeof(d->sq)];
+	}
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(sh4)
+{
+	struct sh4_data *d = (struct sh4_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int timer_nr = 0, dma_channel = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	relative_addr += SH4_REG_BASE;
+
+	/*  SD-RAM access uses address only:  */
+	if (relative_addr >= 0xff900000 && relative_addr <= 0xff97ffff) {
+		/*  Possibly not 100% correct... TODO  */
+		int v = (relative_addr >> 2) & 0xffff;
+		if (relative_addr & 0x00040000)
+			d->sdmr3 = v;
+		else
+			d->sdmr2 = v;
+		debug("[ sh4: sdmr%i set to 0x%04" PRIx16" ]\n",
+		    relative_addr & 0x00040000? 3 : 2, v);
+		return 1;
+	}
+
+
+	switch (relative_addr) {
+
+	/*************************************************/
+
+	case SH4_PVR_ADDR:
+		odata = cpu->cd.sh.cpu_type.pvr;
+		break;
+
+	case SH4_PRR_ADDR:
+		odata = cpu->cd.sh.cpu_type.prr;
+		break;
+
+	case SH4_PTEH:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.pteh;
+		else {
+			unsigned int old_asid = cpu->cd.sh.pteh
+			    & SH4_PTEH_ASID_MASK;
+			cpu->cd.sh.pteh = idata;
+
+			if ((idata & SH4_PTEH_ASID_MASK) != old_asid) {
+				/*
+				 *  TODO: Don't invalidate everything,
+				 *  only those pages that belonged to the
+				 *  old asid.
+				 */
+				cpu->invalidate_translation_caches(
+				    cpu, 0, INVALIDATE_ALL);
+			}
+		}
+		break;
+
+	case SH4_PTEL:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.ptel;
+		else
+			cpu->cd.sh.ptel = idata;
+		break;
+
+	case SH4_TTB:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.ttb;
+		else
+			cpu->cd.sh.ttb = idata;
+		break;
+
+	case SH4_TEA:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.tea;
+		else
+			cpu->cd.sh.tea = idata;
+		break;
+
+	case SH4_PTEA:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.ptea;
+		else
+			cpu->cd.sh.ptea = idata;
+		break;
+
+	case SH4_MMUCR:
+		if (writeflag == MEM_READ) {
+			odata = cpu->cd.sh.mmucr;
+		} else {
+			if (idata & SH4_MMUCR_TI) {
+				/*  TLB invalidate.  */
+				int i;
+				for (i = 0; i < SH_N_ITLB_ENTRIES; i++)
+					cpu->cd.sh.itlb_lo[i] &=
+					    ~SH4_PTEL_V;
+
+				for (i = 0; i < SH_N_UTLB_ENTRIES; i++)
+					cpu->cd.sh.utlb_lo[i] &=
+					    ~SH4_PTEL_V;
+
+				cpu->invalidate_translation_caches(cpu,
+				    0, INVALIDATE_ALL);
+
+				/*  The TI bit should always read as 0.  */
+				idata &= ~SH4_MMUCR_TI;
+			}
+
+			cpu->cd.sh.mmucr = idata;
+		}
+		break;
+
+	case SH4_CCR:
+		if (writeflag == MEM_READ) {
+			odata = cpu->cd.sh.ccr;
+		} else {
+			cpu->cd.sh.ccr = idata;
+		}
+		break;
+
+	case SH4_QACR0:
+		if (writeflag == MEM_READ) {
+			odata = cpu->cd.sh.qacr0;
+		} else {
+			cpu->cd.sh.qacr0 = idata;
+		}
+		break;
+
+	case SH4_QACR1:
+		if (writeflag == MEM_READ) {
+			odata = cpu->cd.sh.qacr1;
+		} else {
+			cpu->cd.sh.qacr1 = idata;
+		}
+		break;
+
+	case SH4_TRA:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.tra;
+		else
+			cpu->cd.sh.tra = idata;
+		break;
+
+	case SH4_EXPEVT:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.expevt;
+		else
+			cpu->cd.sh.expevt = idata;
+		break;
+
+	case SH4_INTEVT:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.intevt;
+		else
+			cpu->cd.sh.intevt = idata;
+		break;
+
+
+	/********************************/
+	/*  UBC: User Break Controller  */
+
+	case 0xff000014:    /*  SH4_UBC_BASRA  */
+	case 0xff000018:    /*  SH4_UBC_BASRB  */
+
+	case 0xff200000:    /*  SH4_UBC_BARA  */
+	case 0xff200004:    /*  SH4_UBC_BAMRA  */
+	case 0xff200008:    /*  SH4_UBC_BBRA  */
+	case 0xff20000c:    /*  SH4_UBC_BARB  */
+	case 0xff200010:    /*  SH4_UBC_BAMRB  */
+	case 0xff200014:    /*  SH4_UBC_BBRB  */
+	case 0xff200018:    /*  SH4_UBC_BDRB  */
+	case 0xff20001c:    /*  SH4_UBC_BDMRB  */
+	case 0xff200020:    /*  SH4_UBC_BRCR  */
+		/*  TODO  */
+		break;
+
+
+	/********************************/
+	/*  TMU: Timer Management Unit  */
+
+	case SH4_TOCR:
+		/*  Timer Output Control Register  */
+		if (writeflag == MEM_WRITE) {
+			d->tocr = idata;
+			if (idata & TOCR_TCOE)
+				fatal("[ sh4 timer: TCOE not yet "
+				    "implemented ]\n");
+		} else {
+			odata = d->tocr;
+		}
+		break;
+
+	case SH4_TSTR:
+		/*  Timer Start Register  */
+		if (writeflag == MEM_READ) {
+			odata = d->tstr;
+		} else {
+			if (idata & 1 && !(d->tstr & 1))
+				debug("[ sh4 timer: starting timer 0 ]\n");
+			if (idata & 2 && !(d->tstr & 2))
+				debug("[ sh4 timer: starting timer 1 ]\n");
+			if (idata & 4 && !(d->tstr & 4))
+				debug("[ sh4 timer: starting timer 2 ]\n");
+			if (!(idata & 1) && d->tstr & 1)
+				debug("[ sh4 timer: stopping timer 0 ]\n");
+			if (!(idata & 2) && d->tstr & 2)
+				debug("[ sh4 timer: stopping timer 1 ]\n");
+			if (!(idata & 4) && d->tstr & 4)
+				debug("[ sh4 timer: stopping timer 2 ]\n");
+			d->tstr = idata;
+		}
+		break;
+
+	case SH4_TCOR2:
+		timer_nr ++;
+		// fall through
+	case SH4_TCOR1:
+		timer_nr ++;
+		// fall through
+	case SH4_TCOR0:
+		/*  Timer Constant Register  */
+		if (writeflag == MEM_READ)
+			odata = d->tcor[timer_nr];
+		else
+			d->tcor[timer_nr] = idata;
+		break;
+
+	case SH4_TCNT2:
+		timer_nr ++;
+		// fall through
+	case SH4_TCNT1:
+		timer_nr ++;
+		// fall through
+	case SH4_TCNT0:
+		/*  Timer Counter Register  */
+		if (writeflag == MEM_READ)
+			odata = d->tcnt[timer_nr];
+		else
+			d->tcnt[timer_nr] = idata;
+		break;
+
+	case SH4_TCR2:
+		timer_nr ++;
+		// fall through
+	case SH4_TCR1:
+		timer_nr ++;
+		// fall through
+	case SH4_TCR0:
+		/*  Timer Control Register  */
+		if (writeflag == MEM_READ) {
+			odata = d->tcr[timer_nr];
+		} else {
+			if (cpu->cd.sh.pclock == 0) {
+				fatal("INTERNAL ERROR: pclock must be set"
+				    " for this machine. Aborting.\n");
+				exit(1);
+			}
+
+			switch (idata & 3) {
+			case TCR_TPSC_P4:
+				d->timer_hz[timer_nr] = cpu->cd.sh.pclock/4.0;
+				break;
+			case TCR_TPSC_P16:
+				d->timer_hz[timer_nr] = cpu->cd.sh.pclock/16.0;
+				break;
+			case TCR_TPSC_P64:
+				d->timer_hz[timer_nr] = cpu->cd.sh.pclock/64.0;
+				break;
+			case TCR_TPSC_P256:
+				d->timer_hz[timer_nr] = cpu->cd.sh.pclock/256.0;
+				break;
+			}
+
+			debug("[ sh4 timer %i clock set to %f Hz ]\n",
+			    timer_nr, d->timer_hz[timer_nr]);
+
+			if (idata & (TCR_ICPF | TCR_ICPE1 | TCR_ICPE0 |
+			    TCR_CKEG1 | TCR_CKEG0 | TCR_TPSC2)) {
+				fatal("Unimplemented SH4 timer control"
+				    " bits: 0x%08" PRIx32". Aborting.\n",
+				    (int) idata);
+				exit(1);
+			}
+
+			INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
+
+			if (d->tcr[timer_nr] & TCR_UNF && !(idata & TCR_UNF)) {
+				if (d->timer_interrupts_pending[timer_nr] > 0)
+					d->timer_interrupts_pending[timer_nr]--;
+			}
+
+			d->tcr[timer_nr] = idata;
+		}
+		break;
+
+
+	/*************************************************/
+	/*  DMAC: DMA Controller                         */
+	/*  4 channels on SH7750                         */
+	/*  8 channels on SH7760                         */
+
+	case SH4_SAR7:	dma_channel ++;
+			// fall through
+	case SH4_SAR6:	dma_channel ++;
+			// fall through
+	case SH4_SAR5:	dma_channel ++;
+			// fall through
+	case SH4_SAR4:	dma_channel ++;
+			// fall through
+	case SH4_SAR3:	dma_channel ++;
+			// fall through
+	case SH4_SAR2:	dma_channel ++;
+			// fall through
+	case SH4_SAR1:	dma_channel ++;
+			// fall through
+	case SH4_SAR0:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.dmac_sar[dma_channel];
+		else
+			cpu->cd.sh.dmac_sar[dma_channel] = idata;
+		break;
+
+	case SH4_DAR7:	dma_channel ++;
+			// fall through
+	case SH4_DAR6:	dma_channel ++;
+			// fall through
+	case SH4_DAR5:	dma_channel ++;
+			// fall through
+	case SH4_DAR4:	dma_channel ++;
+			// fall through
+	case SH4_DAR3:	dma_channel ++;
+			// fall through
+	case SH4_DAR2:	dma_channel ++;
+			// fall through
+	case SH4_DAR1:	dma_channel ++;
+			// fall through
+	case SH4_DAR0:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.dmac_dar[dma_channel];
+		else
+			cpu->cd.sh.dmac_dar[dma_channel] = idata;
+		break;
+
+	case SH4_DMATCR7: dma_channel ++;
+			// fall through
+	case SH4_DMATCR6: dma_channel ++;
+			// fall through
+	case SH4_DMATCR5: dma_channel ++;
+			// fall through
+	case SH4_DMATCR4: dma_channel ++;
+			// fall through
+	case SH4_DMATCR3: dma_channel ++;
+			// fall through
+	case SH4_DMATCR2: dma_channel ++;
+			// fall through
+	case SH4_DMATCR1: dma_channel ++;
+			// fall through
+	case SH4_DMATCR0:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.dmac_tcr[dma_channel] & 0x00ffffff;
+		else {
+			if (idata & ~0x00ffffff) {
+				fatal("[ SH4 DMA: Attempt to set top 8 "
+				    "bits of the count register? 0x%08"
+				    PRIx32" ]\n", (uint32_t) idata);
+				exit(1);
+			}
+
+			cpu->cd.sh.dmac_tcr[dma_channel] = idata;
+		}
+		break;
+
+	case SH4_CHCR7:	dma_channel ++;
+			// fall through
+	case SH4_CHCR6:	dma_channel ++;
+			// fall through
+	case SH4_CHCR5:	dma_channel ++;
+			// fall through
+	case SH4_CHCR4:	dma_channel ++;
+			// fall through
+	case SH4_CHCR3:	dma_channel ++;
+			// fall through
+	case SH4_CHCR2:	dma_channel ++;
+			// fall through
+	case SH4_CHCR1:	dma_channel ++;
+			// fall through
+	case SH4_CHCR0:
+		if (writeflag == MEM_READ) {
+			odata = cpu->cd.sh.dmac_chcr[dma_channel];
+		} else {
+			/*  CHCR_CHSET always reads back as 0:  */
+			idata &= ~CHCR_CHSET;
+
+			cpu->cd.sh.dmac_chcr[dma_channel] = idata;
+
+			/*  Perform a transfer?  */
+			if (idata & CHCR_TD)
+				sh4_dmac_transfer(cpu, d, dma_channel);
+		}
+		break;
+
+	case SH4_DMAOR:
+		if (writeflag == MEM_READ) {
+			odata = cpu->cd.sh.dmaor;
+		} else {
+			// Only some bits are writable:
+			idata &= (DMAOR_DDT | DMAOR_PR1 | DMAOR_PR0 | DMAOR_DME);
+			cpu->cd.sh.dmaor = idata;
+		}
+		break;
+
+	/*************************************************/
+	/*  BSC: Bus State Controller                    */
+
+	case SH4_BCR1:
+		if (writeflag == MEM_WRITE)
+			d->bsc_bcr1 = idata & 0x033efffd;
+		else {
+			odata = d->bsc_bcr1;
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+				odata |= BCR1_LITTLE_ENDIAN;
+		}
+		break;
+
+	case SH4_BCR2:
+		if (len != sizeof(uint16_t)) {
+			fatal("Non-16-bit SH4_BCR2 access?\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE)
+			d->bsc_bcr2 = idata & 0x3ffd;
+		else
+			odata = d->bsc_bcr2;
+		break;
+
+	case SH4_BCR3:
+		if (len != sizeof(uint16_t)) {
+			fatal("Non-16-bit SH4_BCR3 access?\n");
+			exit(1);
+		}
+		if (writeflag == MEM_WRITE)
+			d->bsc_bcr3 = idata;
+		else
+			odata = d->bsc_bcr3;
+		break;
+
+	case SH4_WCR1:
+		if (writeflag == MEM_WRITE)
+			d->bsc_wcr1 = idata & 0x77777777;
+		else
+			odata = d->bsc_wcr1;
+		break;
+
+	case SH4_WCR2:
+		if (writeflag == MEM_WRITE)
+			d->bsc_wcr2 = idata & 0xfffeefff;
+		else
+			odata = d->bsc_wcr2;
+		break;
+
+	case SH4_WCR3:
+		if (writeflag == MEM_WRITE)
+			d->bsc_wcr3 = idata & 0x77777777;
+		else
+			odata = d->bsc_wcr3;
+		break;
+
+	case SH4_MCR:
+		if (writeflag == MEM_WRITE)
+			d->bsc_mcr = idata & 0xf8bbffff;
+		else
+			odata = d->bsc_mcr;
+		break;
+
+	case SH4_PCR:
+		if (writeflag == MEM_WRITE)
+			d->bsc_pcr = idata;
+		else
+			odata = d->bsc_pcr;
+		break;
+
+	case SH4_RTCSR:
+		/*
+		 *  Refresh Time Control/Status Register. Called RTCSR in
+		 *  NetBSD, but RTSCR in the SH7750 manual?
+		 */
+		if (writeflag == MEM_WRITE) {
+			idata &= 0x00ff;
+			if (idata & RTCSR_CMF) {
+				idata = (idata & ~RTCSR_CMF)
+				    | (d->bsc_rtcsr & RTCSR_CMF);
+			}
+			d->bsc_rtcsr = idata & 0x00ff;
+		} else
+			odata = d->bsc_rtcsr;
+		break;
+
+	case SH4_RTCOR:
+		/*  Refresh Time Constant Register (8 bits):  */
+		if (writeflag == MEM_WRITE)
+			d->bsc_rtcor = idata & 0x00ff;
+		else
+			odata = d->bsc_rtcor & 0x00ff;
+		break;
+
+	case SH4_RFCR:
+		/*  Refresh Count Register (10 bits):  */
+		if (writeflag == MEM_WRITE)
+			d->bsc_rfcr = idata & 0x03ff;
+		else
+			odata = d->bsc_rfcr & 0x03ff;
+		break;
+
+
+	/*******************************************/
+	/*  GPIO:  General-purpose I/O controller  */
+
+	case SH4_PCTRA:
+		if (writeflag == MEM_WRITE) {
+			d->pctra = idata;
+			
+			// Hack: Makes the Dreamcast BIOS pass "cable select"
+			// detection, it seems, without hanging in an endless
+			// loop.
+			d->pdtra |= 0x03;
+		} else {
+			odata = d->pctra;
+		}
+		break;
+
+	case SH4_PDTRA:
+		if (writeflag == MEM_WRITE) {
+			// debug("[ sh4: pdtra: write 0x%08x (while pctra = 0x%08x) ]\n", (int)idata, (int)d->pctra);
+			d->pdtra = idata;
+
+			// Hack: Makes the Dreamcast BIOS pass "cable select"
+			// detection, it seems, without hanging in an endless
+			// loop.
+			if ((idata & 1) == 0 || (idata & 2) == 0)
+				d->pdtra &= ~3;
+		} else {
+			// debug("[ sh4: pdtra: read ]\n");
+			odata = d->pdtra;
+
+			// bits 8..9 on Dreamcast mean:
+			//  00 = VGA, 10 = RGB, 11 = composite.
+			odata |= (0 << 8);
+		}
+		break;
+
+	case SH4_PCTRB:
+		if (writeflag == MEM_WRITE)
+			d->pctrb = idata;
+		else
+			odata = d->pctrb;
+		break;
+
+	case SH4_PDTRB:
+		if (writeflag == MEM_WRITE) {
+			debug("[ sh4: pdtrb: write: TODO ]\n");
+			d->pdtrb = idata;
+		} else {
+			debug("[ sh4: pdtrb: read: TODO ]\n");
+			odata = d->pdtrb;
+		}
+		break;
+
+	case SH4_GPIOIC:
+		if (writeflag == MEM_WRITE)
+			d->bsc_gpioic = idata;
+		else
+			odata = d->bsc_gpioic;
+		break;
+
+
+	/****************************/
+	/*  SCI:  Serial Interface  */
+
+	case SHREG_SCSPTR:
+		odata = sh4_sci_access(d, cpu,
+		    writeflag == MEM_WRITE? 1 : 0, idata);
+
+		/*
+		 *  TODO
+		 *
+		 *  Find out the REAL way to make OpenBSD/landisk 4.1 run
+		 *  in a stable manner! This is a SUPER-UGLY HACK which
+		 *  just side-steps the real bug.
+		 *
+		 *  NOTE:  Snapshots of OpenBSD/landisk _after_ 4.1 seem
+		 *  to work WITHOUT this hack, but NOT with it!
+		 */
+		cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
+
+		break;
+
+
+	/*********************************/
+	/*  INTC:  Interrupt Controller  */
+
+	case SH4_ICR:
+		if (writeflag == MEM_WRITE) {
+			if (idata & 0x80) {
+				fatal("SH4 INTC: IRLM not yet "
+				    "supported. TODO\n");
+				exit(1);
+			}
+		}
+		break;
+
+	case SH4_IPRA:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.intc_ipra;
+		else {
+			cpu->cd.sh.intc_ipra = idata;
+			sh_update_interrupt_priorities(cpu);
+		}
+		break;
+
+	case SH4_IPRB:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.intc_iprb;
+		else {
+			cpu->cd.sh.intc_iprb = idata;
+			sh_update_interrupt_priorities(cpu);
+		}
+		break;
+
+	case SH4_IPRC:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.intc_iprc;
+		else {
+			cpu->cd.sh.intc_iprc = idata;
+			sh_update_interrupt_priorities(cpu);
+		}
+		break;
+
+	case SH4_IPRD:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.intc_iprd;
+		else {
+			cpu->cd.sh.intc_iprd = idata;
+			sh_update_interrupt_priorities(cpu);
+		}
+		break;
+
+	case SH4_INTPRI00:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.intc_intpri00;
+		else {
+			cpu->cd.sh.intc_intpri00 = idata;
+			sh_update_interrupt_priorities(cpu);
+		}
+		break;
+
+	case SH4_INTPRI00 + 4:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.intc_intpri04;
+		else {
+			cpu->cd.sh.intc_intpri04 = idata;
+			sh_update_interrupt_priorities(cpu);
+		}
+		break;
+
+	case SH4_INTPRI00 + 8:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.intc_intpri08;
+		else {
+			cpu->cd.sh.intc_intpri08 = idata;
+			sh_update_interrupt_priorities(cpu);
+		}
+		break;
+
+	case SH4_INTPRI00 + 0xc:
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.intc_intpri0c;
+		else {
+			cpu->cd.sh.intc_intpri0c = idata;
+			sh_update_interrupt_priorities(cpu);
+		}
+		break;
+
+	case SH4_INTMSK00:
+		/*  Note: Writes can only set bits, not clear them.  */
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.intc_intmsk00;
+		else
+			cpu->cd.sh.intc_intmsk00 |= idata;
+		break;
+
+	case SH4_INTMSK00 + 4:
+		/*  Note: Writes can only set bits, not clear them.  */
+		if (writeflag == MEM_READ)
+			odata = cpu->cd.sh.intc_intmsk04;
+		else
+			cpu->cd.sh.intc_intmsk04 |= idata;
+		break;
+
+	case SH4_INTMSKCLR00:
+		/*  Note: Writes can only clear bits, not set them.  */
+		if (writeflag == MEM_WRITE)
+			cpu->cd.sh.intc_intmsk00 &= ~idata;
+		break;
+
+	case SH4_INTMSKCLR00 + 4:
+		/*  Note: Writes can only clear bits, not set them.  */
+		if (writeflag == MEM_WRITE)
+			cpu->cd.sh.intc_intmsk04 &= ~idata;
+		break;
+
+
+	/*************************************************/
+	/*  SCIF: Serial Controller Interface with FIFO  */
+
+	case SH4_SCIF_BASE + SCIF_SMR:
+		if (writeflag == MEM_WRITE) {
+			d->scif_smr = idata;
+		} else {
+			odata = d->scif_smr;
+		}
+		break;
+
+	case SH4_SCIF_BASE + SCIF_BRR:
+		if (writeflag == MEM_WRITE) {
+			d->scif_brr = idata;
+		} else {
+			odata = d->scif_brr;
+		}
+		break;
+
+	case SH4_SCIF_BASE + SCIF_SCR:
+		if (writeflag == MEM_WRITE) {
+			d->scif_scr = idata;
+			scif_reassert_interrupts(d);
+		} else {
+			odata = d->scif_scr;
+		}
+		break;
+
+	case SH4_SCIF_BASE + SCIF_FTDR:
+		if (writeflag == MEM_WRITE) {
+			/*  Add to TX fifo:  */
+			if (d->scif_tx_fifo_cursize >=
+			    sizeof(d->scif_tx_fifo)) {
+				fatal("[ SCIF TX fifo overrun! ]\n");
+				d->scif_tx_fifo_cursize = 0;
+			}
+
+			d->scif_tx_fifo[d->scif_tx_fifo_cursize++] = idata;
+			d->scif_delayed_tx = SCIF_DELAYED_TX_VALUE;
+		}
+		break;
+
+	case SH4_SCIF_BASE + SCIF_SSR:
+		if (writeflag == MEM_READ) {
+			odata = d->scif_ssr;
+		} else {
+			d->scif_ssr = idata;
+			scif_reassert_interrupts(d);
+		}
+		break;
+
+	case SH4_SCIF_BASE + SCIF_FRDR:
+		{
+			int x = console_readchar(d->scif_console_handle);
+			if (x == 13)
+				x = 10;
+			odata = x < 0? 0 : x;
+			if (console_charavail(d->scif_console_handle))
+				d->scif_ssr |= SCSSR2_DR;
+			else
+				d->scif_ssr &= ~SCSSR2_DR;
+			scif_reassert_interrupts(d);
+		}
+		break;
+
+	case SH4_SCIF_BASE + SCIF_FCR:
+		if (writeflag == MEM_WRITE) {
+			d->scif_fcr = idata;
+		} else {
+			odata = d->scif_fcr;
+		}
+		break;
+
+	case SH4_SCIF_BASE + SCIF_FDR:
+		/*  Nr of bytes in the TX and RX fifos, respectively:  */
+		{
+			int chars_avail = console_charavail(d->scif_console_handle);
+			if (chars_avail > 255) {
+				fatal("[ SH4: Too many chars avail; dropping some ]\n");
+				chars_avail = 255;
+			}
+			
+			odata = chars_avail | (d->scif_tx_fifo_cursize << 8);
+		}
+		break;
+
+	case SH4_SCIF_BASE + SCIF_SPTR:
+		/*  TODO: Implement all bits.  */
+		odata = 0;
+		break;
+
+	case SH4_SCIF_BASE + SCIF_LSR:
+		/*  TODO: Implement all bits.  */
+		odata = 0;
+		break;
+
+
+	/*************************************************/
+
+	case SH4_CPG_FRQCR:	// 0xffc00000	16-bit
+		if (writeflag == MEM_WRITE)
+			d->cpg_frqcr = idata;
+		else
+			odata = d->cpg_frqcr;
+		break;
+
+	case SH4_CPG_STBCR: 	// 0xffc00004	8-bit
+		if (writeflag == MEM_WRITE)
+			d->cpg_stbcr = idata;
+		else
+			odata = d->cpg_stbcr;
+		break;
+
+	case SH4_CPG_WTCNT:	// 0xffc00008	8/16-bit
+		if (writeflag == MEM_WRITE)
+			d->cpg_wtcnt = idata;
+		else
+			odata = d->cpg_wtcnt;
+		break;
+
+	case SH4_CPG_WTCSR:	// 0xffc0000c	8/16-bit
+		if (writeflag == MEM_WRITE)
+			d->cpg_wtcsr = idata;
+		else
+			odata = d->cpg_wtcsr;
+		break;
+
+	case SH4_CPG_STBCR2:	// 0xffc00010	8-bit
+		if (writeflag == MEM_WRITE)
+			d->cpg_stbcr2 = idata;
+		else
+			odata = d->cpg_stbcr2;
+		break;
+
+
+	/*************************************************/
+
+	case SH4_RSECCNT:
+	case SH4_RMINCNT:
+	case SH4_RHRCNT:
+	case SH4_RWKCNT:
+	case SH4_RDAYCNT:
+	case SH4_RMONCNT:
+	case SH4_RYRCNT:
+	case SH4_RSECAR:
+	case SH4_RMINAR:
+	case SH4_RHRAR:
+	case SH4_RWKAR:
+	case SH4_RDAYAR:
+	case SH4_RMONAR:
+		if (writeflag == MEM_WRITE) {
+			d->rtc_reg[(relative_addr - 0xffc80000) / 4] = idata;
+		} else {
+			/*  TODO: Update rtc_reg based on host's date/time.  */
+			odata = d->rtc_reg[(relative_addr - 0xffc80000) / 4];
+		}
+		break;
+
+	case SH4_RCR1:
+		if (writeflag == MEM_READ)
+			odata = d->rtc_rcr1;
+		else {
+			d->rtc_rcr1 = idata;
+			if (idata & 0x18) {
+				fatal("SH4: TODO: RTC interrupt enable\n");
+				exit(1);
+			}
+		}
+		break;
+
+	case SH4_RCR2:
+		if (writeflag == MEM_READ)
+			odata = d->rtc_rcr2;
+		else {
+			d->rtc_rcr2 = idata;
+			// bit 1 (i.e. idata == 0x02) means reset.
+			if (idata != 0x02) {
+				debug("[ SH4: TODO: RTC RCR2 value 0x%02x ignored. ]\n", (int)idata);
+			}
+		}
+		break;
+
+
+	/*************************************************/
+
+	default:if (writeflag == MEM_READ) {
+			fatal("[ sh4: read from addr 0x%x ]\n",
+			    (int)relative_addr);
+		} else {
+			fatal("[ sh4: write to addr 0x%x: 0x%x ]\n",
+			    (int)relative_addr, (int)idata);
+		}
+
+#ifdef SH4_DEBUG
+		exit(1);
+#endif
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(sh4)
+{
+	char tmp[200], n[200];
+	int i;
+	struct machine *machine = devinit->machine;
+	struct sh4_data *d;
+
+	CHECK_ALLOCATION(d = (struct sh4_data *) malloc(sizeof(struct sh4_data)));
+	memset(d, 0, sizeof(struct sh4_data));
+
+
+	/*
+	 *  Main SH4 device, and misc memory stuff:
+	 */
+
+	memory_device_register(machine->memory, devinit->name,
+	    SH4_REG_BASE, 0x01000000, dev_sh4_access, d, DM_DEFAULT, NULL);
+
+	/*  On-chip RAM/cache:  */
+	dev_ram_init(machine, 0x1e000000, 0x8000, DEV_RAM_RAM, 0x0, NULL);
+
+	/*  0xe0000000: Store queues:  */
+	memory_device_register(machine->memory, "sh4_sq",
+	    0xe0000000, 0x04000000, dev_sh4_sq_access, d, DM_DEFAULT, NULL);
+
+
+	/*
+	 *  SCIF (Serial console):
+	 */
+
+	d->scif_console_handle = console_start_slave(devinit->machine,
+	    "SH4 SCIF", 1);
+
+	snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]",
+	    devinit->interrupt_path, SH4_INTEVT_SCIF_RXI);
+	INTERRUPT_CONNECT(tmp, d->scif_rx_irq);
+	snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]",
+	    devinit->interrupt_path, SH4_INTEVT_SCIF_TXI);
+	INTERRUPT_CONNECT(tmp, d->scif_tx_irq);
+
+
+	/*
+	 *  Caches (fake):
+ 	 *
+	 *  0xf0000000	SH4_CCIA	I-Cache address array
+	 *  0xf1000000	SH4_CCID	I-Cache data array
+	 *  0xf4000000	SH4_CCDA	D-Cache address array
+	 *  0xf5000000	SH4_CCDD	D-Cache data array
+	 *
+	 *  TODO: Implement more correct cache behavior?
+	 */
+
+	dev_ram_init(machine, SH4_CCIA, SH4_ICACHE_SIZE * 2, DEV_RAM_RAM, 0x0, NULL);
+	dev_ram_init(machine, SH4_CCID, SH4_ICACHE_SIZE,     DEV_RAM_RAM, 0x0, NULL);
+	dev_ram_init(machine, SH4_CCDA, SH4_DCACHE_SIZE * 2, DEV_RAM_RAM, 0x0, NULL);
+	dev_ram_init(machine, SH4_CCDD, SH4_DCACHE_SIZE,     DEV_RAM_RAM, 0x0, NULL);
+
+	/*  0xf2000000	SH4_ITLB_AA  */
+	memory_device_register(machine->memory, "sh4_itlb_aa", SH4_ITLB_AA,
+	    0x01000000, dev_sh4_itlb_aa_access, d, DM_DEFAULT, NULL);
+
+	/*  0xf3000000	SH4_ITLB_DA1  */
+	memory_device_register(machine->memory, "sh4_itlb_da1", SH4_ITLB_DA1,
+	    0x01000000, dev_sh4_itlb_da1_access, d, DM_DEFAULT, NULL);
+
+	/*  0xf6000000	SH4_UTLB_AA  */
+	memory_device_register(machine->memory, "sh4_utlb_aa", SH4_UTLB_AA,
+	    0x01000000, dev_sh4_utlb_aa_access, d, DM_DEFAULT, NULL);
+
+	/*  0xf7000000	SH4_UTLB_DA1  */
+	memory_device_register(machine->memory, "sh4_utlb_da1", SH4_UTLB_DA1,
+	    0x01000000, dev_sh4_utlb_da1_access, d, DM_DEFAULT, NULL);
+
+
+	/*
+	 *  PCIC (PCI controller) at 0xfe200000:
+	 */
+
+	memory_device_register(machine->memory, "sh4_pcic", SH4_PCIC,
+	    N_PCIC_REGS * sizeof(uint32_t), dev_sh4_pcic_access, d,
+	    DM_DEFAULT, NULL);
+
+	/*  Initial PCI control register contents:  */
+	d->bsc_bcr2 = BCR2_PORTEN;
+	d->pcic_reg[PCIC_REG(SH4_PCICONF2)] = PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
+	    PCI_SUBCLASS_BRIDGE_HOST, 0);
+
+	/*  Register 16 PCIC interrupts:  */
+	for (i=0; i<N_PCIC_IRQS; i++) {
+		struct interrupt templ;
+		snprintf(n, sizeof(n), "%s.pcic.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = sh4_pcic_interrupt_assert;
+		templ.interrupt_deassert = sh4_pcic_interrupt_deassert;
+		interrupt_handler_register(&templ);
+
+		snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]",
+		    devinit->interrupt_path, SH4_INTEVT_IRQ0 + 0x20 * i);
+		INTERRUPT_CONNECT(tmp, d->cpu_pcic_interrupt[i]);
+	}
+
+	/*  Register the PCI bus:  */
+	snprintf(tmp, sizeof(tmp), "%s.pcic", devinit->interrupt_path);
+	d->pci_data = bus_pci_init(
+	    devinit->machine,
+	    tmp,			/*  pciirq  */
+	    0,				/*  pci device io offset  */
+	    0,				/*  pci device mem offset  */
+	    SH4_PCIC_IO,		/*  PCI portbase  */
+	    SH4_PCIC_MEM,		/*  PCI membase  */
+	    tmp,			/*  PCI irqbase  */
+	    0x00000000,			/*  ISA portbase  */
+	    0x00000000,			/*  ISA membase  */
+	    "TODOisaIrqBase");		/*  ISA irqbase  */
+
+	/*  Return PCI bus pointer, to allow per-machine devices
+	    to be added later:  */
+	devinit->return_ptr = d->pci_data;
+
+
+	/*
+	 *  Timer:
+	 */
+
+	d->sh4_timer = timer_add(SH4_PSEUDO_TIMER_HZ, sh4_timer_tick, d);
+	machine_add_tickfunction(devinit->machine, dev_sh4_tick, d,
+	    SH4_TICK_SHIFT);
+
+	/*  Initial Timer values, according to the SH7750 manual:  */
+	d->tcor[0] = 0xffffffff; d->tcnt[0] = 0xffffffff;
+	d->tcor[1] = 0xffffffff; d->tcnt[1] = 0xffffffff;
+	d->tcor[2] = 0xffffffff; d->tcnt[2] = 0xffffffff;
+
+	snprintf(tmp, sizeof(tmp), "machine[0].cpu[0].irq[0x%x]",
+	    SH_INTEVT_TMU0_TUNI0);
+	if (!interrupt_handler_lookup(tmp, &d->timer_irq[0])) {
+		fatal("Could not find interrupt '%s'.\n", tmp);
+		exit(1);
+	}
+	snprintf(tmp, sizeof(tmp), "machine[0].cpu[0].irq[0x%x]",
+	    SH_INTEVT_TMU1_TUNI1);
+	if (!interrupt_handler_lookup(tmp, &d->timer_irq[1])) {
+		fatal("Could not find interrupt '%s'.\n", tmp);
+		exit(1);
+	}
+	snprintf(tmp, sizeof(tmp), "machine[0].cpu[0].irq[0x%x]",
+	    SH_INTEVT_TMU2_TUNI2);
+	if (!interrupt_handler_lookup(tmp, &d->timer_irq[2])) {
+		fatal("Could not find interrupt '%s'.\n", tmp);
+		exit(1);
+	}
+
+
+	// The RTC RCR2 register is "basically" initialized to 0x09, with
+	// some bit undefined. :-) According to the manual.
+	d->rtc_rcr2 = 0x09;
+
+
+	/*
+	 *  Bus State Controller initial values, according to the
+	 *  SH7760 manual:
+	 */
+
+	d->bsc_bcr2 = 0x3ffc;
+	d->bsc_wcr1 = 0x77777777;
+	d->bsc_wcr2 = 0xfffeefff;
+	d->bsc_wcr3 = 0x77777777;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_sh4.cc gxemul-0.7.0+dfsg/src/devices/dev_sh4.cc
--- gxemul-0.6.2/src/devices/dev_sh4.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sh4.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,2022 +0,0 @@
-/*
- *  Copyright (C) 2006-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: SH4-specific memory mapped registers (0xf0000000 - 0xffffffff)
- *
- *  TODO: Among other things:
- *
- *	x)  Interrupt masks (msk register stuff). Are these really correct?
- *	x)  BSC (Bus state controller).
- *	x)  DMA: Right now there's a hack for Dreamcast emulation
- *	x)  UBC (User Break Controller)
- *	x)  ...
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_pci.h"
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "sh4_dmacreg.h"
-#include "timer.h"
-
-#include "thirdparty/sh4_bscreg.h"
-#include "thirdparty/sh4_cache.h"
-#include "thirdparty/sh4_exception.h"
-#include "thirdparty/sh4_intcreg.h"
-#include "thirdparty/sh4_mmu.h"
-#include "thirdparty/sh4_pcicreg.h"
-#include "thirdparty/sh4_rtcreg.h"
-#include "thirdparty/sh4_scifreg.h"
-#include "thirdparty/sh4_scireg.h"
-#include "thirdparty/sh4_tmureg.h"
-
-
-#define	SH4_REG_BASE		0xff000000
-#define	SH4_TICK_SHIFT		14
-#define	N_SH4_TIMERS		3
-
-/*  PCI stuff:  */
-#define	N_PCIC_REGS			(0x224 / sizeof(uint32_t))
-#define	N_PCIC_IRQS			16
-#define	PCIC_REG(addr)			((addr - SH4_PCIC) / sizeof(uint32_t))
-#define	PCI_VENDOR_HITACHI		0x1054
-#define	PCI_PRODUCT_HITACHI_SH7751	0x3505
-#define	PCI_PRODUCT_HITACHI_SH7751R	0x350e   
-
-#define	SCIF_TX_FIFO_SIZE	16
-#define	SCIF_DELAYED_TX_VALUE	2	/*  2 to be safe, 1 = fast but buggy  */
-
-#ifdef UNSTABLE_DEVEL
-// #define SH4_DEBUG
-/*  #define debug fatal  */
-#endif
-
-// Clock/occilation related
-#define SH4_CPG_FRQCR		0xffc00000	/* 16-bit */
-#define SH4_CPG_STBCR 		0xffc00004	/* 8-bit */
-#define SH4_CPG_WTCNT 		0xffc00008	/* 8/16-bit */
-#define SH4_CPG_WTCSR 		0xffc0000c	/* 8/16-bit */
-#define SH4_CPG_STBCR2 		0xffc00010	/* 8-bit */
-
-
-struct sh4_data {
-	/*  Store Queues:  */
-	uint8_t		sq[32 * 2];
-
-	/*  SCIF (Serial controller):  */
-	uint16_t	scif_smr;
-	uint8_t		scif_brr;
-	uint16_t	scif_scr;
-	uint16_t	scif_ssr;
-	uint16_t	scif_fcr;
-	uint16_t	scif_lsr;
-	int		scif_delayed_tx;
-	int		scif_console_handle;
-	uint8_t		scif_tx_fifo[SCIF_TX_FIFO_SIZE + 1];
-	size_t		scif_tx_fifo_cursize;
-	struct interrupt scif_tx_irq;
-	struct interrupt scif_rx_irq;
-	int		scif_tx_irq_asserted;
-	int		scif_rx_irq_asserted;
-
-	/*  Bus State Controller:  */
-	uint32_t	bsc_bcr1;
-	uint16_t	bsc_bcr2;
-	uint16_t	bsc_bcr3;	/*  SH7751R  */
-	uint32_t	bsc_wcr1;
-	uint32_t	bsc_wcr2;
-	uint32_t	bsc_wcr3;
-	uint32_t	bsc_mcr;
-	uint16_t	bsc_pcr;
-	uint16_t	bsc_rtcsr;
-	uint16_t	bsc_rtcor;
-	uint16_t	bsc_rfcr;
-
-	/*  CPG:  */
-	uint16_t	cpg_frqcr;
-	uint8_t		cpg_stbcr;
-	uint16_t	cpg_wtcnt;
-	uint16_t	cpg_wtcsr;
-	uint8_t		cpg_stbcr2;
-
-	/*  GPIO:  */
-	uint32_t	pctra;		/*  Port Control Register A  */
-	uint32_t	pdtra;		/*  Port Data Register A  */
-	uint32_t	pctrb;		/*  Port Control Register B  */
-	uint32_t	pdtrb;		/*  Port Data Register B  */
-	uint16_t	bsc_gpioic;
-
-	/*  PCIC (PCI controller):  */
-	struct pci_data	*pci_data;
-	struct interrupt cpu_pcic_interrupt[N_PCIC_IRQS];
-	uint32_t	pcic_reg[N_PCIC_REGS];
-
-	/*  SCI (serial interface):  */
-	int		sci_bits_outputed;
-	int		sci_bits_read;
-	uint8_t		sci_scsptr;
-	uint8_t		sci_curbyte;
-	uint8_t		sci_cur_addr;
-
-	/*  SD-RAM:  */
-	uint16_t	sdmr2;
-	uint16_t	sdmr3;
-
-	/*  Timer Management Unit:  */
-	struct timer	*sh4_timer;
-	struct interrupt timer_irq[4];
-	uint32_t	tocr;
-	uint32_t	tstr;
-	uint32_t	tcnt[N_SH4_TIMERS];
-	uint32_t	tcor[N_SH4_TIMERS];
-	uint32_t	tcr[N_SH4_TIMERS];
-	int		timer_interrupts_pending[N_SH4_TIMERS];
-	double		timer_hz[N_SH4_TIMERS];
-
-	/*  RTC:  */
-	uint32_t	rtc_reg[14];	/*  Excluding rcr1 and rcr2  */
-	uint8_t		rtc_rcr1;
-	uint8_t		rtc_rcr2;
-};
-
-
-#define	SH4_PSEUDO_TIMER_HZ	110.0
-
-
-/*
- *  sh4_timer_tick():
- *
- *  This function is called SH4_PSEUDO_TIMER_HZ times per real-world second.
- *  Its job is to update the SH4 timer counters, and if necessary, increase
- *  the number of pending interrupts.
- *
- *  Also, RAM Refresh is also faked here.
- */
-static void sh4_timer_tick(struct timer *t, void *extra)
-{
-	struct sh4_data *d = (struct sh4_data *) extra;
-	int i;
-
-	/*  Fake RAM refresh:  */
-	d->bsc_rfcr ++;
-	if (d->bsc_rtcsr & (RTCSR_CMIE | RTCSR_OVIE)) {
-		fatal("sh4: RTCSR_CMIE | RTCSR_OVIE: TODO\n");
-		/*  TODO: Implement refresh interrupts etc.  */
-		exit(1);
-	}
-
-	/*  Timer interrupts:  */
-	for (i=0; i<N_SH4_TIMERS; i++) {
-		int32_t old = d->tcnt[i];
-
-		/*  printf("tcnt[%i] = %08x   tcor[%i] = %08x\n",
-		    i, d->tcnt[i], i, d->tcor[i]);  */
-
-		/*  Only update timers that are currently started:  */
-		if (!(d->tstr & (TSTR_STR0 << i)))
-			continue;
-
-		/*  Update the current count:  */
-		d->tcnt[i] -= (uint32_t) (d->timer_hz[i] / SH4_PSEUDO_TIMER_HZ);
-
-		/*  Has the timer underflowed?  */
-		if ((int32_t)d->tcnt[i] < 0 && old >= 0) {
-			d->tcr[i] |= TCR_UNF;
-
-			if (d->tcr[i] & TCR_UNIE)
-				d->timer_interrupts_pending[i] ++;
-
-			/*
-			 *  Set tcnt[i] to tcor[i]. Note: Since this function
-			 *  is only called now and then, adding tcor[i] to
-			 *  tcnt[i] produces more correct values for long
-			 *  running timers.
-			 */
-			d->tcnt[i] += d->tcor[i];
-
-			/*  At least make sure that tcnt is non-negative...  */
-			if ((int32_t)d->tcnt[i] < 0)
-				d->tcnt[i] = 0;
-		}
-	}
-}
-
-
-static void sh4_pcic_interrupt_assert(struct interrupt *interrupt)
-{
-	struct sh4_data *d = (struct sh4_data *) interrupt->extra;
-	INTERRUPT_ASSERT(d->cpu_pcic_interrupt[interrupt->line]);
-}
-static void sh4_pcic_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct sh4_data *d = (struct sh4_data *) interrupt->extra;
-	INTERRUPT_DEASSERT(d->cpu_pcic_interrupt[interrupt->line]);
-}
-
-
-static void scif_reassert_interrupts(struct sh4_data *d)
-{
-	int old_tx_asserted = d->scif_tx_irq_asserted;
-	int old_rx_asserted = d->scif_rx_irq_asserted;
-
-	d->scif_rx_irq_asserted =
-	    d->scif_scr & SCSCR2_RIE && d->scif_ssr & SCSSR2_DR;
-
-	if (d->scif_rx_irq_asserted && !old_rx_asserted)
-		INTERRUPT_ASSERT(d->scif_rx_irq);
-	else if (!d->scif_rx_irq_asserted && old_rx_asserted)
-		INTERRUPT_DEASSERT(d->scif_rx_irq);
-
-	d->scif_tx_irq_asserted =
-	    d->scif_scr & SCSCR2_TIE &&
-	    d->scif_ssr & (SCSSR2_TDFE | SCSSR2_TEND);
-
-	if (d->scif_tx_irq_asserted && !old_tx_asserted)
-		INTERRUPT_ASSERT(d->scif_tx_irq);
-	else if (!d->scif_tx_irq_asserted && old_tx_asserted)
-		INTERRUPT_DEASSERT(d->scif_tx_irq);
-}
-
-
-DEVICE_TICK(sh4)
-{
-	struct sh4_data *d = (struct sh4_data *) extra;
-	unsigned int i;
-
-	/*
-	 *  Serial controller interrupts:
-	 *
-	 *  RX: Cause interrupt if any char is available.
-	 *  TX: Send entire TX FIFO contents, and interrupt.
-	 */
-	if (console_charavail(d->scif_console_handle))
-		d->scif_ssr |= SCSSR2_DR;
-	else
-		d->scif_ssr &= ~SCSSR2_DR;
-
-	if (d->scif_delayed_tx) {
-		if (--d->scif_delayed_tx == 0) {
-			/*  Send TX FIFO contents:  */
-			for (i=0; i<d->scif_tx_fifo_cursize; i++)
-				console_putchar(d->scif_console_handle,
-				    d->scif_tx_fifo[i]);
-
-			/*  Clear FIFO:  */
-			d->scif_tx_fifo_cursize = 0;
-
-			/*  Done sending; cause a transmit end interrupt:  */
-			d->scif_ssr |= SCSSR2_TDFE | SCSSR2_TEND;
-		}
-	}
-
-	scif_reassert_interrupts(d);
-
-	/*  Timer interrupts:  */
-	for (i=0; i<N_SH4_TIMERS; i++)
-		if (d->timer_interrupts_pending[i] > 0) {
-			INTERRUPT_ASSERT(d->timer_irq[i]);
-			d->tcr[i] |= TCR_UNF;
-		}
-}
-
-
-/*
- *  sh4_dmac_transfer():
- *
- *  Called whenever a DMA transfer is to be executed.
- *  Clears the lowest bit of the corresponding channel's CHCR when done.
- */
-void sh4_dmac_transfer(struct cpu *cpu, struct sh4_data *d, int channel)
-{
-	/*  According to the SH7760 manual, bits 31..29 are ignored in  */
-	/*  both the SAR and DAR.  */
-	uint32_t sar = cpu->cd.sh.dmac_sar[channel] & 0x1fffffff;
-	uint32_t dar = cpu->cd.sh.dmac_dar[channel] & 0x1fffffff;
-	uint32_t count = cpu->cd.sh.dmac_tcr[channel] & 0x1fffffff;
-	uint32_t chcr = cpu->cd.sh.dmac_chcr[channel];
-	int transmit_size = 1;
-	int src_delta = 0, dst_delta = 0;
-	int cause_interrupt = chcr & CHCR_IE;
-
-	/*  DMAC not enabled? Then just return.  */
-	if (!(chcr & CHCR_TD))
-		return;
-
-	/*  Transfer End already set? Then don't transfer again.  */
-	if (chcr & CHCR_TE)
-		return;
-
-	/*  Special case: 0 means 16777216:  */
-	if (count == 0)
-		count = 16777216;
-
-	switch (chcr & CHCR_TS) {
-	case CHCR_TS_8BYTE: transmit_size = 8; break;
-	case CHCR_TS_1BYTE: transmit_size = 1; break;
-	case CHCR_TS_2BYTE: transmit_size = 2; break;
-	case CHCR_TS_4BYTE: transmit_size = 4; break;
-	case CHCR_TS_32BYTE: transmit_size = 32; break;
-	default: fatal("Unimplemented transmit size?! CHCR[%i] = 0x%08x\n",
-	    channel, chcr);
-	exit(1);
-	}
-
-	switch (chcr & CHCR_DM) {
-	case CHCR_DM_FIXED:       dst_delta = 0; break;
-	case CHCR_DM_INCREMENTED: dst_delta = 1; break;
-	case CHCR_DM_DECREMENTED: dst_delta = -1; break;
-	default: fatal("Unimplemented destination delta?! CHCR[%i] = 0x%08x\n",
-	    channel, chcr);
-	exit(1);
-	}
-
-	switch (chcr & CHCR_SM) {
-	case CHCR_SM_FIXED:       src_delta = 0; break;
-	case CHCR_SM_INCREMENTED: src_delta = 1; break;
-	case CHCR_SM_DECREMENTED: src_delta = -1; break;
-	default: fatal("Unimplemented source delta?! CHCR[%i] = 0x%08x\n",
-	    channel, chcr);
-	exit(1);
-	}
-
-	src_delta *= transmit_size;
-	dst_delta *= transmit_size;
-
-#ifdef SH4_DEBUG
-	fatal("|SH4 DMA transfer, channel %i\n", channel);
-	fatal("|Source addr:      0x%08x (delta %i)\n", (int) sar, src_delta);
-	fatal("|Destination addr: 0x%08x (delta %i)\n", (int) dar, dst_delta);
-	fatal("|Count:            0x%08x\n", (int) count);
-	fatal("|Transmit size:    0x%08x\n", (int) transmit_size);
-	fatal("|Interrupt:        %s\n", cause_interrupt? "yes" : "no");
-#endif
-
-	switch (chcr & CHCR_RS) {
-	case 0x200:
-		/*
-		 *  Single Address Mode
-		 *  External Address Space => external device
-		 */
-
-		// Avoid compiler warnings about unused sar and dar.
-		(void)sar;
-		(void)dar;
-
-		/*  Note: No transfer is done here! It is up to the
-		    external device to do the transfer itself!  */
-		break;
-
-	default:fatal("Unimplemented SH4 RS DMAC: 0x%08x\n",
-		    (int) (chcr & CHCR_RS));
-		exit(1);
-	}
-
-	if (cause_interrupt) {
-		fatal("TODO: sh4 dmac interrupt!\n");
-		exit(1);
-	}
-}
-
-
-/*
- *  sh4_sci_cmd():
- *
- *  Handle a SCI command byte.
- *
- *  Bit:   Meaning:
- *   7      Ignored (usually 1?)
- *   6      0=Write, 1=Read
- *   5      AD: Address transfer
- *   4      DT: Data transfer
- *   3..0   Data or address bits
- */
-static void sh4_sci_cmd(struct sh4_data *d, struct cpu *cpu)
-{
-	uint8_t cmd = d->sci_curbyte;
-	int writeflag = cmd & 0x40? 0 : 1;
-	int address_transfer;
-
-	/*  fatal("[ CMD BYTE %02x ]\n", cmd);  */
-
-	if (!(cmd & 0x80)) {
-		fatal("SCI cmd bit 7 not set? TODO\n");
-		exit(1);
-	}
-
-	if ((cmd & 0x30) == 0x20)
-		address_transfer = 1;
-	else if ((cmd & 0x30) == 0x10)
-		address_transfer = 0;
-	else {
-		fatal("SCI: Neither data nor address transfer? TODO\n");
-		exit(1);
-	}
-
-	if (address_transfer)
-		d->sci_cur_addr = cmd & 0x0f;
-
-	if (!writeflag) {
-		/*  Read data from the current address:  */
-		uint8_t data_byte;
-
-		cpu->memory_rw(cpu, cpu->mem, SCI_DEVICE_BASE + d->sci_cur_addr,
-		    &data_byte, 1, MEM_READ, PHYSICAL);
-
-		debug("[ SCI: read addr=%x data=%x ]\n",
-		    d->sci_cur_addr, data_byte);
-
-		d->sci_curbyte = data_byte;
-
-		/*  Set bit 7 right away:  */
-		d->sci_scsptr &= ~SCSPTR_SPB1DT;
-		if (data_byte & 0x80)
-			d->sci_scsptr |= SCSPTR_SPB1DT;
-	}
-
-	if (writeflag && !address_transfer) {
-		/*  Write the 4 data bits to the current address:  */
-		uint8_t data_byte = cmd & 0x0f;
-
-		debug("[ SCI: write addr=%x data=%x ]\n",
-		    d->sci_cur_addr, data_byte);
-
-		cpu->memory_rw(cpu, cpu->mem, SCI_DEVICE_BASE + d->sci_cur_addr,
-		    &data_byte, 1, MEM_WRITE, PHYSICAL);
-	}
-}
-
-
-/*
- *  sh4_sci_access():
- *
- *  Reads or writes a bit via the SH4's serial interface. If writeflag is
- *  non-zero, input is used. If writeflag is zero, a bit is outputed as
- *  the return value from this function.
- */
-static uint8_t sh4_sci_access(struct sh4_data *d, struct cpu *cpu,
-	int writeflag, uint8_t input)
-{
-	if (writeflag) {
-		/*  WRITE:  */
-		int clockpulse;
-		uint8_t old = d->sci_scsptr;
-		d->sci_scsptr = input;
-
-		/*
-		 *  Clock pulse (SCSPTR_SPB0DT going from 0 to 1,
-		 *  when SCSPTR_SPB0IO was already set):
-		 */
-		clockpulse = old & SCSPTR_SPB0IO &&
-		    d->sci_scsptr & SCSPTR_SPB0DT &&
-		    !(old & SCSPTR_SPB0DT);
-
-		if (!clockpulse)
-			return 0;
-
-		/*  Are we in output or input mode?  */
-		if (d->sci_scsptr & SCSPTR_SPB1IO) {
-			/*  Output:  */
-			int bit = d->sci_scsptr & SCSPTR_SPB1DT? 1 : 0;
-			d->sci_curbyte <<= 1;
-			d->sci_curbyte |= bit;
-			d->sci_bits_outputed ++;
-			if (d->sci_bits_outputed == 8) {
-				/*  4 control bits and 4 address/data bits have
-				    been written.  */
-				sh4_sci_cmd(d, cpu);
-				d->sci_bits_outputed = 0;
-			}
-		} else {
-			/*  Input:  */
-			int bit;
-			d->sci_bits_read ++;
-			d->sci_bits_read &= 7;
-
-			bit = d->sci_curbyte & (0x80 >> d->sci_bits_read);
-
-			d->sci_scsptr &= ~SCSPTR_SPB1DT;
-			if (bit)
-				d->sci_scsptr |= SCSPTR_SPB1DT;
-		}
-
-		/*  Return (value doesn't matter).  */
-		return 0;
-	} else {
-		/*  READ:  */
-		return d->sci_scsptr;
-	}
-}
-
-
-DEVICE_ACCESS(sh4_itlb_aa)
-{
-	uint64_t idata = 0, odata = 0;
-	int e = (relative_addr & SH4_ITLB_E_MASK) >> SH4_ITLB_E_SHIFT;
-
-	if (writeflag == MEM_WRITE) {
-		int safe_to_invalidate = 0;
-		uint32_t old_hi = cpu->cd.sh.itlb_hi[e];
-		if ((cpu->cd.sh.itlb_lo[e] & SH4_PTEL_SZ_MASK)==SH4_PTEL_SZ_4K)
-			safe_to_invalidate = 1;
-
-		idata = memory_readmax64(cpu, data, len);
-		cpu->cd.sh.itlb_hi[e] &=
-		    ~(SH4_PTEH_VPN_MASK | SH4_PTEH_ASID_MASK);
-		cpu->cd.sh.itlb_hi[e] |= (idata &
-		    (SH4_ITLB_AA_VPN_MASK | SH4_ITLB_AA_ASID_MASK));
-		cpu->cd.sh.itlb_lo[e] &= ~SH4_PTEL_V;
-		if (idata & SH4_ITLB_AA_V)
-			cpu->cd.sh.itlb_lo[e] |= SH4_PTEL_V;
-
-		/*  Invalidate if this ITLB entry previously belonged to the
-		    currently running process, or if it was shared:  */
-		if (cpu->cd.sh.ptel & SH4_PTEL_SH ||
-		    (old_hi & SH4_ITLB_AA_ASID_MASK) ==
-		    (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) {
-			if (safe_to_invalidate)
-				cpu->invalidate_translation_caches(cpu,
-				    old_hi & ~0xfff, INVALIDATE_VADDR);
-			else
-				cpu->invalidate_translation_caches(cpu,
-				    0, INVALIDATE_ALL);
-		}
-	} else {
-		odata = cpu->cd.sh.itlb_hi[e] &
-		    (SH4_ITLB_AA_VPN_MASK | SH4_ITLB_AA_ASID_MASK);
-		if (cpu->cd.sh.itlb_lo[e] & SH4_PTEL_V)
-			odata |= SH4_ITLB_AA_V;
-		memory_writemax64(cpu, data, len, odata);
-	}
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(sh4_itlb_da1)
-{
-	uint32_t mask = SH4_PTEL_SH | SH4_PTEL_C | SH4_PTEL_SZ_MASK |
-	    SH4_PTEL_PR_MASK | SH4_PTEL_V | 0x1ffffc00;
-	uint64_t idata = 0, odata = 0;
-	int e = (relative_addr & SH4_ITLB_E_MASK) >> SH4_ITLB_E_SHIFT;
-
-	if (relative_addr & 0x800000) {
-		fatal("sh4_itlb_da1: TODO: da2 area\n");
-		exit(1);
-	}
-
-	if (writeflag == MEM_WRITE) {
-		uint32_t old_lo = cpu->cd.sh.itlb_lo[e];
-		int safe_to_invalidate = 0;
-		if ((cpu->cd.sh.itlb_lo[e] & SH4_PTEL_SZ_MASK)==SH4_PTEL_SZ_4K)
-			safe_to_invalidate = 1;
-
-		idata = memory_readmax64(cpu, data, len);
-		cpu->cd.sh.itlb_lo[e] &= ~mask;
-		cpu->cd.sh.itlb_lo[e] |= (idata & mask);
-
-		/*  Invalidate if this ITLB entry belongs to the
-		    currently running process, or if it was shared:  */
-		if (old_lo & SH4_PTEL_SH ||
-		    (cpu->cd.sh.itlb_hi[e] & SH4_ITLB_AA_ASID_MASK) ==
-		    (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) {
-			if (safe_to_invalidate)
-				cpu->invalidate_translation_caches(cpu,
-				    cpu->cd.sh.itlb_hi[e] & ~0xfff,
-				    INVALIDATE_VADDR);
-			else
-				cpu->invalidate_translation_caches(cpu,
-				    0, INVALIDATE_ALL);
-		}
-	} else {
-		odata = cpu->cd.sh.itlb_lo[e] & mask;
-		memory_writemax64(cpu, data, len, odata);
-	}
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(sh4_utlb_aa)
-{
-	uint64_t idata = 0, odata = 0;
-	int i, e = (relative_addr & SH4_UTLB_E_MASK) >> SH4_UTLB_E_SHIFT;
-	int a = relative_addr & SH4_UTLB_A;
-
-	if (writeflag == MEM_WRITE) {
-		int n_hits = 0;
-		int safe_to_invalidate = 0;
-		uint32_t vaddr_to_invalidate = 0;
-
-		idata = memory_readmax64(cpu, data, len);
-		if (a) {
-			for (i=-SH_N_ITLB_ENTRIES; i<SH_N_UTLB_ENTRIES; i++) {
-				uint32_t lo, hi;
-				uint32_t mask = 0xfffff000;
-				int sh;
-
-				if (i < 0) {
-					lo = cpu->cd.sh.itlb_lo[
-					    i + SH_N_ITLB_ENTRIES];
-					hi = cpu->cd.sh.itlb_hi[
-					    i + SH_N_ITLB_ENTRIES];
-				} else {
-					lo = cpu->cd.sh.utlb_lo[i];
-					hi = cpu->cd.sh.utlb_hi[i];
-				}
-
-				sh = lo & SH4_PTEL_SH;
-				if (!(lo & SH4_PTEL_V))
-					continue;
-
-				switch (lo & SH4_PTEL_SZ_MASK) {
-				case SH4_PTEL_SZ_1K:  mask = 0xfffffc00; break;
-				case SH4_PTEL_SZ_64K: mask = 0xffff0000; break;
-				case SH4_PTEL_SZ_1M:  mask = 0xfff00000; break;
-				}
-
-				if ((hi & mask) != (idata & mask))
-					continue;
-
-				if ((lo & SH4_PTEL_SZ_MASK) ==
-				    SH4_PTEL_SZ_4K) {
-					safe_to_invalidate = 1;
-					vaddr_to_invalidate = hi & mask;
-				}
-
-				if (!sh && (hi & SH4_PTEH_ASID_MASK) !=
-				    (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK))
-					continue;
-
-				if (i < 0) {
-					cpu->cd.sh.itlb_lo[i +
-					    SH_N_ITLB_ENTRIES] &= ~SH4_PTEL_V;
-					if (idata & SH4_UTLB_AA_V)
-						cpu->cd.sh.itlb_lo[
-						    i+SH_N_ITLB_ENTRIES] |=
-						    SH4_PTEL_V;
-				} else {
-					cpu->cd.sh.utlb_lo[i] &=
-					    ~(SH4_PTEL_D | SH4_PTEL_V);
-					if (idata & SH4_UTLB_AA_D)
-						cpu->cd.sh.utlb_lo[i] |=
-						    SH4_PTEL_D;
-					if (idata & SH4_UTLB_AA_V)
-						cpu->cd.sh.utlb_lo[i] |=
-						    SH4_PTEL_V;
-				}
-
-				if (i >= 0)
-					n_hits ++;
-			}
-
-			if (n_hits > 1)
-				sh_exception(cpu,
-				    EXPEVT_RESET_TLB_MULTI_HIT, 0, 0);
-		} else {
-			if ((cpu->cd.sh.utlb_lo[e] & SH4_PTEL_SZ_MASK) ==
-			    SH4_PTEL_SZ_4K) {
-				safe_to_invalidate = 1;
-				vaddr_to_invalidate =
-				    cpu->cd.sh.utlb_hi[e] & ~0xfff;
-			}
-
-			cpu->cd.sh.utlb_hi[e] &=
-			    ~(SH4_PTEH_VPN_MASK | SH4_PTEH_ASID_MASK);
-			cpu->cd.sh.utlb_hi[e] |= (idata &
-			    (SH4_UTLB_AA_VPN_MASK | SH4_UTLB_AA_ASID_MASK));
-
-			cpu->cd.sh.utlb_lo[e] &= ~(SH4_PTEL_D | SH4_PTEL_V);
-			if (idata & SH4_UTLB_AA_D)
-				cpu->cd.sh.utlb_lo[e] |= SH4_PTEL_D;
-			if (idata & SH4_UTLB_AA_V)
-				cpu->cd.sh.utlb_lo[e] |= SH4_PTEL_V;
-		}
-
-		if (safe_to_invalidate)
-			cpu->invalidate_translation_caches(cpu,
-			    vaddr_to_invalidate, INVALIDATE_VADDR);
-		else
-			cpu->invalidate_translation_caches(cpu, 0,
-			    INVALIDATE_ALL);
-	} else {
-		odata = cpu->cd.sh.utlb_hi[e] &
-		    (SH4_UTLB_AA_VPN_MASK | SH4_UTLB_AA_ASID_MASK);
-		if (cpu->cd.sh.utlb_lo[e] & SH4_PTEL_D)
-			odata |= SH4_UTLB_AA_D;
-		if (cpu->cd.sh.utlb_lo[e] & SH4_PTEL_V)
-			odata |= SH4_UTLB_AA_V;
-		memory_writemax64(cpu, data, len, odata);
-	}
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(sh4_utlb_da1)
-{
-	uint32_t mask = SH4_PTEL_WT | SH4_PTEL_SH | SH4_PTEL_D | SH4_PTEL_C
-	    | SH4_PTEL_SZ_MASK | SH4_PTEL_PR_MASK | SH4_PTEL_V | 0x1ffffc00;
-	uint64_t idata = 0, odata = 0;
-	int e = (relative_addr & SH4_UTLB_E_MASK) >> SH4_UTLB_E_SHIFT;
-
-	if (relative_addr & 0x800000) {
-		fatal("sh4_utlb_da1: TODO: da2 area\n");
-		exit(1);
-	}
-
-	if (writeflag == MEM_WRITE) {
-		uint32_t old_lo = cpu->cd.sh.utlb_lo[e];
-		int safe_to_invalidate = 0;
-		if ((cpu->cd.sh.utlb_lo[e] & SH4_PTEL_SZ_MASK)==SH4_PTEL_SZ_4K)
-			safe_to_invalidate = 1;
-
-		idata = memory_readmax64(cpu, data, len);
-		cpu->cd.sh.utlb_lo[e] &= ~mask;
-		cpu->cd.sh.utlb_lo[e] |= (idata & mask);
-
-		/*  Invalidate if this UTLB entry belongs to the
-		    currently running process, or if it was shared:  */
-		if (old_lo & SH4_PTEL_SH ||
-		    (cpu->cd.sh.utlb_hi[e] & SH4_ITLB_AA_ASID_MASK) ==
-		    (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) {
-			if (safe_to_invalidate)
-				cpu->invalidate_translation_caches(cpu,
-				    cpu->cd.sh.utlb_hi[e] & ~0xfff,
-				    INVALIDATE_VADDR);
-			else
-				cpu->invalidate_translation_caches(cpu,
-				    0, INVALIDATE_ALL);
-		}
-	} else {
-		odata = cpu->cd.sh.utlb_lo[e] & mask;
-		memory_writemax64(cpu, data, len, odata);
-	}
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(sh4_pcic)
-{
-	struct sh4_data *d = (struct sh4_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	relative_addr += SH4_PCIC;
-
-	/*  Register read/write:  */
-	if (writeflag == MEM_WRITE)
-		d->pcic_reg[PCIC_REG(relative_addr)] = idata;
-	else
-		odata = d->pcic_reg[PCIC_REG(relative_addr)];
-
-	/*  Special cases:  */
-
-	switch (relative_addr) {
-
-	case SH4_PCICONF0:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ sh4_pcic: TODO: Write to SH4_PCICONF0? ]\n");
-			exit(1);
-		} else {
-			if (strcmp(cpu->cd.sh.cpu_type.name, "SH7751") == 0) {
-				odata = PCI_ID_CODE(PCI_VENDOR_HITACHI,
-				    PCI_PRODUCT_HITACHI_SH7751);
-			} else if (strcmp(cpu->cd.sh.cpu_type.name,
-			    "SH7751R") == 0) {
-				odata = PCI_ID_CODE(PCI_VENDOR_HITACHI,
-				    PCI_PRODUCT_HITACHI_SH7751R);
-			} else {
-				fatal("sh4_pcic: TODO: PCICONF0 read for"
-				    " unimplemented CPU type?\n");
-				exit(1);
-			}
-		}
-		break;
-
-	case SH4_PCICONF1:
-	case SH4_PCICONF2:
-	case SH4_PCICR:
-	case SH4_PCIBCR1:
-	case SH4_PCIBCR2:
-	case SH4_PCIBCR3:
-	case SH4_PCIWCR1:
-	case SH4_PCIWCR2:
-	case SH4_PCIWCR3:
-	case SH4_PCIMCR:
-		break;
-
-	case SH4_PCICONF5:
-		/*  Hardcoded to what OpenBSD/landisk uses:  */
-		if (writeflag == MEM_WRITE && idata != 0xac000000) {
-			fatal("sh4_pcic: SH4_PCICONF5 unknown value"
-			    " 0x%" PRIx32"\n", (uint32_t) idata);
-			exit(1);
-		}
-		break;
-
-	case SH4_PCICONF6:
-		/*  Hardcoded to what OpenBSD/landisk uses:  */
-		if (writeflag == MEM_WRITE && idata != 0x8c000000) {
-			fatal("sh4_pcic: SH4_PCICONF6 unknown value"
-			    " 0x%" PRIx32"\n", (uint32_t) idata);
-			exit(1);
-		}
-		break;
-
-	case SH4_PCILSR0:
-		/*  Hardcoded to what OpenBSD/landisk uses:  */
-		if (writeflag == MEM_WRITE && idata != ((64 - 1) << 20)) {
-			fatal("sh4_pcic: SH4_PCILSR0 unknown value"
-			    " 0x%" PRIx32"\n", (uint32_t) idata);
-			exit(1);
-		}
-		break;
-
-	case SH4_PCILAR0:
-		/*  Hardcoded to what OpenBSD/landisk uses:  */
-		if (writeflag == MEM_WRITE && idata != 0xac000000) {
-			fatal("sh4_pcic: SH4_PCILAR0 unknown value"
-			    " 0x%" PRIx32"\n", (uint32_t) idata);
-			exit(1);
-		}
-		break;
-
-	case SH4_PCILSR1:
-		/*  Hardcoded to what OpenBSD/landisk uses:  */
-		if (writeflag == MEM_WRITE && idata != ((64 - 1) << 20)) {
-			fatal("sh4_pcic: SH4_PCILSR1 unknown value"
-			    " 0x%" PRIx32"\n", (uint32_t) idata);
-			exit(1);
-		}
-		break;
-
-	case SH4_PCILAR1:
-		/*  Hardcoded to what OpenBSD/landisk uses:  */
-		if (writeflag == MEM_WRITE && idata != 0xac000000) {
-			fatal("sh4_pcic: SH4_PCILAR1 unknown value"
-			    " 0x%" PRIx32"\n", (uint32_t) idata);
-			exit(1);
-		}
-		break;
-
-	case SH4_PCIMBR:
-		if (writeflag == MEM_WRITE && idata != SH4_PCIC_MEM) {
-			fatal("sh4_pcic: PCIMBR set to 0x%" PRIx32", not"
-			    " 0x%" PRIx32"? TODO\n", (uint32_t) idata,
-			    (uint32_t) SH4_PCIC_MEM);
-			exit(1);
-		}
-		break;
-
-	case SH4_PCIIOBR:
-		if (writeflag == MEM_WRITE && idata != SH4_PCIC_IO) {
-			fatal("sh4_pcic: PCIIOBR set to 0x%" PRIx32", not"
-			    " 0x%" PRIx32"? TODO\n", (uint32_t) idata,
-			    (uint32_t) SH4_PCIC_IO);
-			exit(1);
-		}
-		break;
-
-	case SH4_PCIPAR:
-		/*  PCI bus access Address Register:  */
-		{
-			int bus  = (idata >> 16) & 0xff;
-			int dev  = (idata >> 11) & 0x1f;
-			int func = (idata >>  8) &    7;
-			int reg  =  idata        & 0xff;
-			bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
-		}
-		break;
-
-	case SH4_PCIPDR:
-		/*  PCI bus access Data Register:  */
-		bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
-		    &odata : &idata, len, writeflag);
-		break;
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ sh4_pcic: read from addr 0x%x: TODO ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ sh4_pcic: write to addr 0x%x: 0x%x: TODO ]\n",
-			    (int)relative_addr, (int)idata);
-		}
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(sh4_sq)
-{
-	struct sh4_data *d = (struct sh4_data *) extra;
-	size_t i;
-
-	if (writeflag == MEM_WRITE) {
-		for (i=0; i<len; i++)
-			d->sq[(relative_addr + i) % sizeof(d->sq)] = data[i];
-	} else {
-		for (i=0; i<len; i++)
-			data[i] = d->sq[(relative_addr + i) % sizeof(d->sq)];
-	}
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(sh4)
-{
-	struct sh4_data *d = (struct sh4_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int timer_nr = 0, dma_channel = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	relative_addr += SH4_REG_BASE;
-
-	/*  SD-RAM access uses address only:  */
-	if (relative_addr >= 0xff900000 && relative_addr <= 0xff97ffff) {
-		/*  Possibly not 100% correct... TODO  */
-		int v = (relative_addr >> 2) & 0xffff;
-		if (relative_addr & 0x00040000)
-			d->sdmr3 = v;
-		else
-			d->sdmr2 = v;
-		debug("[ sh4: sdmr%i set to 0x%04" PRIx16" ]\n",
-		    relative_addr & 0x00040000? 3 : 2, v);
-		return 1;
-	}
-
-
-	switch (relative_addr) {
-
-	/*************************************************/
-
-	case SH4_PVR_ADDR:
-		odata = cpu->cd.sh.cpu_type.pvr;
-		break;
-
-	case SH4_PRR_ADDR:
-		odata = cpu->cd.sh.cpu_type.prr;
-		break;
-
-	case SH4_PTEH:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.pteh;
-		else {
-			unsigned int old_asid = cpu->cd.sh.pteh
-			    & SH4_PTEH_ASID_MASK;
-			cpu->cd.sh.pteh = idata;
-
-			if ((idata & SH4_PTEH_ASID_MASK) != old_asid) {
-				/*
-				 *  TODO: Don't invalidate everything,
-				 *  only those pages that belonged to the
-				 *  old asid.
-				 */
-				cpu->invalidate_translation_caches(
-				    cpu, 0, INVALIDATE_ALL);
-			}
-		}
-		break;
-
-	case SH4_PTEL:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.ptel;
-		else
-			cpu->cd.sh.ptel = idata;
-		break;
-
-	case SH4_TTB:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.ttb;
-		else
-			cpu->cd.sh.ttb = idata;
-		break;
-
-	case SH4_TEA:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.tea;
-		else
-			cpu->cd.sh.tea = idata;
-		break;
-
-	case SH4_PTEA:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.ptea;
-		else
-			cpu->cd.sh.ptea = idata;
-		break;
-
-	case SH4_MMUCR:
-		if (writeflag == MEM_READ) {
-			odata = cpu->cd.sh.mmucr;
-		} else {
-			if (idata & SH4_MMUCR_TI) {
-				/*  TLB invalidate.  */
-				int i;
-				for (i = 0; i < SH_N_ITLB_ENTRIES; i++)
-					cpu->cd.sh.itlb_lo[i] &=
-					    ~SH4_PTEL_V;
-
-				for (i = 0; i < SH_N_UTLB_ENTRIES; i++)
-					cpu->cd.sh.utlb_lo[i] &=
-					    ~SH4_PTEL_V;
-
-				cpu->invalidate_translation_caches(cpu,
-				    0, INVALIDATE_ALL);
-
-				/*  The TI bit should always read as 0.  */
-				idata &= ~SH4_MMUCR_TI;
-			}
-
-			cpu->cd.sh.mmucr = idata;
-		}
-		break;
-
-	case SH4_CCR:
-		if (writeflag == MEM_READ) {
-			odata = cpu->cd.sh.ccr;
-		} else {
-			cpu->cd.sh.ccr = idata;
-		}
-		break;
-
-	case SH4_QACR0:
-		if (writeflag == MEM_READ) {
-			odata = cpu->cd.sh.qacr0;
-		} else {
-			cpu->cd.sh.qacr0 = idata;
-		}
-		break;
-
-	case SH4_QACR1:
-		if (writeflag == MEM_READ) {
-			odata = cpu->cd.sh.qacr1;
-		} else {
-			cpu->cd.sh.qacr1 = idata;
-		}
-		break;
-
-	case SH4_TRA:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.tra;
-		else
-			cpu->cd.sh.tra = idata;
-		break;
-
-	case SH4_EXPEVT:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.expevt;
-		else
-			cpu->cd.sh.expevt = idata;
-		break;
-
-	case SH4_INTEVT:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.intevt;
-		else
-			cpu->cd.sh.intevt = idata;
-		break;
-
-
-	/********************************/
-	/*  UBC: User Break Controller  */
-
-	case 0xff000014:    /*  SH4_UBC_BASRA  */
-	case 0xff000018:    /*  SH4_UBC_BASRB  */
-
-	case 0xff200000:    /*  SH4_UBC_BARA  */
-	case 0xff200004:    /*  SH4_UBC_BAMRA  */
-	case 0xff200008:    /*  SH4_UBC_BBRA  */
-	case 0xff20000c:    /*  SH4_UBC_BARB  */
-	case 0xff200010:    /*  SH4_UBC_BAMRB  */
-	case 0xff200014:    /*  SH4_UBC_BBRB  */
-	case 0xff200018:    /*  SH4_UBC_BDRB  */
-	case 0xff20001c:    /*  SH4_UBC_BDMRB  */
-	case 0xff200020:    /*  SH4_UBC_BRCR  */
-		/*  TODO  */
-		break;
-
-
-	/********************************/
-	/*  TMU: Timer Management Unit  */
-
-	case SH4_TOCR:
-		/*  Timer Output Control Register  */
-		if (writeflag == MEM_WRITE) {
-			d->tocr = idata;
-			if (idata & TOCR_TCOE)
-				fatal("[ sh4 timer: TCOE not yet "
-				    "implemented ]\n");
-		} else {
-			odata = d->tocr;
-		}
-		break;
-
-	case SH4_TSTR:
-		/*  Timer Start Register  */
-		if (writeflag == MEM_READ) {
-			odata = d->tstr;
-		} else {
-			if (idata & 1 && !(d->tstr & 1))
-				debug("[ sh4 timer: starting timer 0 ]\n");
-			if (idata & 2 && !(d->tstr & 2))
-				debug("[ sh4 timer: starting timer 1 ]\n");
-			if (idata & 4 && !(d->tstr & 4))
-				debug("[ sh4 timer: starting timer 2 ]\n");
-			if (!(idata & 1) && d->tstr & 1)
-				debug("[ sh4 timer: stopping timer 0 ]\n");
-			if (!(idata & 2) && d->tstr & 2)
-				debug("[ sh4 timer: stopping timer 1 ]\n");
-			if (!(idata & 4) && d->tstr & 4)
-				debug("[ sh4 timer: stopping timer 2 ]\n");
-			d->tstr = idata;
-		}
-		break;
-
-	case SH4_TCOR2:
-		timer_nr ++;
-	case SH4_TCOR1:
-		timer_nr ++;
-	case SH4_TCOR0:
-		/*  Timer Constant Register  */
-		if (writeflag == MEM_READ)
-			odata = d->tcor[timer_nr];
-		else
-			d->tcor[timer_nr] = idata;
-		break;
-
-	case SH4_TCNT2:
-		timer_nr ++;
-	case SH4_TCNT1:
-		timer_nr ++;
-	case SH4_TCNT0:
-		/*  Timer Counter Register  */
-		if (writeflag == MEM_READ)
-			odata = d->tcnt[timer_nr];
-		else
-			d->tcnt[timer_nr] = idata;
-		break;
-
-	case SH4_TCR2:
-		timer_nr ++;
-	case SH4_TCR1:
-		timer_nr ++;
-	case SH4_TCR0:
-		/*  Timer Control Register  */
-		if (writeflag == MEM_READ) {
-			odata = d->tcr[timer_nr];
-		} else {
-			if (cpu->cd.sh.pclock == 0) {
-				fatal("INTERNAL ERROR: pclock must be set"
-				    " for this machine. Aborting.\n");
-				exit(1);
-			}
-
-			switch (idata & 3) {
-			case TCR_TPSC_P4:
-				d->timer_hz[timer_nr] = cpu->cd.sh.pclock/4.0;
-				break;
-			case TCR_TPSC_P16:
-				d->timer_hz[timer_nr] = cpu->cd.sh.pclock/16.0;
-				break;
-			case TCR_TPSC_P64:
-				d->timer_hz[timer_nr] = cpu->cd.sh.pclock/64.0;
-				break;
-			case TCR_TPSC_P256:
-				d->timer_hz[timer_nr] = cpu->cd.sh.pclock/256.0;
-				break;
-			}
-
-			debug("[ sh4 timer %i clock set to %f Hz ]\n",
-			    timer_nr, d->timer_hz[timer_nr]);
-
-			if (idata & (TCR_ICPF | TCR_ICPE1 | TCR_ICPE0 |
-			    TCR_CKEG1 | TCR_CKEG0 | TCR_TPSC2)) {
-				fatal("Unimplemented SH4 timer control"
-				    " bits: 0x%08" PRIx32". Aborting.\n",
-				    (int) idata);
-				exit(1);
-			}
-
-			INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
-
-			if (d->tcr[timer_nr] & TCR_UNF && !(idata & TCR_UNF)) {
-				if (d->timer_interrupts_pending[timer_nr] > 0)
-					d->timer_interrupts_pending[timer_nr]--;
-			}
-
-			d->tcr[timer_nr] = idata;
-		}
-		break;
-
-
-	/*************************************************/
-	/*  DMAC: DMA Controller                         */
-	/*  4 channels on SH7750                         */
-	/*  8 channels on SH7760                         */
-
-	case SH4_SAR7:	dma_channel ++;
-	case SH4_SAR6:	dma_channel ++;
-	case SH4_SAR5:	dma_channel ++;
-	case SH4_SAR4:	dma_channel ++;
-	case SH4_SAR3:	dma_channel ++;
-	case SH4_SAR2:	dma_channel ++;
-	case SH4_SAR1:	dma_channel ++;
-	case SH4_SAR0:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.dmac_sar[dma_channel];
-		else
-			cpu->cd.sh.dmac_sar[dma_channel] = idata;
-		break;
-
-	case SH4_DAR7:	dma_channel ++;
-	case SH4_DAR6:	dma_channel ++;
-	case SH4_DAR5:	dma_channel ++;
-	case SH4_DAR4:	dma_channel ++;
-	case SH4_DAR3:	dma_channel ++;
-	case SH4_DAR2:	dma_channel ++;
-	case SH4_DAR1:	dma_channel ++;
-	case SH4_DAR0:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.dmac_dar[dma_channel];
-		else
-			cpu->cd.sh.dmac_dar[dma_channel] = idata;
-		break;
-
-	case SH4_DMATCR7: dma_channel ++;
-	case SH4_DMATCR6: dma_channel ++;
-	case SH4_DMATCR5: dma_channel ++;
-	case SH4_DMATCR4: dma_channel ++;
-	case SH4_DMATCR3: dma_channel ++;
-	case SH4_DMATCR2: dma_channel ++;
-	case SH4_DMATCR1: dma_channel ++;
-	case SH4_DMATCR0:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.dmac_tcr[dma_channel] & 0x00ffffff;
-		else {
-			if (idata & ~0x00ffffff) {
-				fatal("[ SH4 DMA: Attempt to set top 8 "
-				    "bits of the count register? 0x%08"
-				    PRIx32" ]\n", (uint32_t) idata);
-				exit(1);
-			}
-
-			cpu->cd.sh.dmac_tcr[dma_channel] = idata;
-		}
-		break;
-
-	case SH4_CHCR7:	dma_channel ++;
-	case SH4_CHCR6:	dma_channel ++;
-	case SH4_CHCR5:	dma_channel ++;
-	case SH4_CHCR4:	dma_channel ++;
-	case SH4_CHCR3:	dma_channel ++;
-	case SH4_CHCR2:	dma_channel ++;
-	case SH4_CHCR1:	dma_channel ++;
-	case SH4_CHCR0:
-		if (writeflag == MEM_READ) {
-			odata = cpu->cd.sh.dmac_chcr[dma_channel];
-		} else {
-			/*  CHCR_CHSET always reads back as 0:  */
-			idata &= ~CHCR_CHSET;
-
-			cpu->cd.sh.dmac_chcr[dma_channel] = idata;
-
-			/*  Perform a transfer?  */
-			if (idata & CHCR_TD)
-				sh4_dmac_transfer(cpu, d, dma_channel);
-		}
-		break;
-
-	case SH4_DMAOR:
-		if (writeflag == MEM_READ) {
-			odata = cpu->cd.sh.dmaor;
-		} else {
-			// Only some bits are writable:
-			idata &= (DMAOR_DDT | DMAOR_PR1 | DMAOR_PR0 | DMAOR_DME);
-			cpu->cd.sh.dmaor = idata;
-		}
-		break;
-
-	/*************************************************/
-	/*  BSC: Bus State Controller                    */
-
-	case SH4_BCR1:
-		if (writeflag == MEM_WRITE)
-			d->bsc_bcr1 = idata & 0x033efffd;
-		else {
-			odata = d->bsc_bcr1;
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-				odata |= BCR1_LITTLE_ENDIAN;
-		}
-		break;
-
-	case SH4_BCR2:
-		if (len != sizeof(uint16_t)) {
-			fatal("Non-16-bit SH4_BCR2 access?\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE)
-			d->bsc_bcr2 = idata & 0x3ffd;
-		else
-			odata = d->bsc_bcr2;
-		break;
-
-	case SH4_BCR3:
-		if (len != sizeof(uint16_t)) {
-			fatal("Non-16-bit SH4_BCR3 access?\n");
-			exit(1);
-		}
-		if (writeflag == MEM_WRITE)
-			d->bsc_bcr3 = idata;
-		else
-			odata = d->bsc_bcr3;
-		break;
-
-	case SH4_WCR1:
-		if (writeflag == MEM_WRITE)
-			d->bsc_wcr1 = idata & 0x77777777;
-		else
-			odata = d->bsc_wcr1;
-		break;
-
-	case SH4_WCR2:
-		if (writeflag == MEM_WRITE)
-			d->bsc_wcr2 = idata & 0xfffeefff;
-		else
-			odata = d->bsc_wcr2;
-		break;
-
-	case SH4_WCR3:
-		if (writeflag == MEM_WRITE)
-			d->bsc_wcr3 = idata & 0x77777777;
-		else
-			odata = d->bsc_wcr3;
-		break;
-
-	case SH4_MCR:
-		if (writeflag == MEM_WRITE)
-			d->bsc_mcr = idata & 0xf8bbffff;
-		else
-			odata = d->bsc_mcr;
-		break;
-
-	case SH4_PCR:
-		if (writeflag == MEM_WRITE)
-			d->bsc_pcr = idata;
-		else
-			odata = d->bsc_pcr;
-		break;
-
-	case SH4_RTCSR:
-		/*
-		 *  Refresh Time Control/Status Register. Called RTCSR in
-		 *  NetBSD, but RTSCR in the SH7750 manual?
-		 */
-		if (writeflag == MEM_WRITE) {
-			idata &= 0x00ff;
-			if (idata & RTCSR_CMF) {
-				idata = (idata & ~RTCSR_CMF)
-				    | (d->bsc_rtcsr & RTCSR_CMF);
-			}
-			d->bsc_rtcsr = idata & 0x00ff;
-		} else
-			odata = d->bsc_rtcsr;
-		break;
-
-	case SH4_RTCOR:
-		/*  Refresh Time Constant Register (8 bits):  */
-		if (writeflag == MEM_WRITE)
-			d->bsc_rtcor = idata & 0x00ff;
-		else
-			odata = d->bsc_rtcor & 0x00ff;
-		break;
-
-	case SH4_RFCR:
-		/*  Refresh Count Register (10 bits):  */
-		if (writeflag == MEM_WRITE)
-			d->bsc_rfcr = idata & 0x03ff;
-		else
-			odata = d->bsc_rfcr & 0x03ff;
-		break;
-
-
-	/*******************************************/
-	/*  GPIO:  General-purpose I/O controller  */
-
-	case SH4_PCTRA:
-		if (writeflag == MEM_WRITE) {
-			d->pctra = idata;
-			
-			// Hack: Makes the Dreamcast BIOS pass "cable select"
-			// detection, it seems, without hanging in an endless
-			// loop.
-			d->pdtra |= 0x03;
-		} else {
-			odata = d->pctra;
-		}
-		break;
-
-	case SH4_PDTRA:
-		if (writeflag == MEM_WRITE) {
-			// debug("[ sh4: pdtra: write 0x%08x (while pctra = 0x%08x) ]\n", (int)idata, (int)d->pctra);
-			d->pdtra = idata;
-
-			// Hack: Makes the Dreamcast BIOS pass "cable select"
-			// detection, it seems, without hanging in an endless
-			// loop.
-			if ((idata & 1) == 0 || (idata & 2) == 0)
-				d->pdtra &= ~3;
-		} else {
-			// debug("[ sh4: pdtra: read ]\n");
-			odata = d->pdtra;
-
-			// bits 8..9 on Dreamcast mean:
-			//  00 = VGA, 10 = RGB, 11 = composite.
-			odata |= (0 << 8);
-		}
-		break;
-
-	case SH4_PCTRB:
-		if (writeflag == MEM_WRITE)
-			d->pctrb = idata;
-		else
-			odata = d->pctrb;
-		break;
-
-	case SH4_PDTRB:
-		if (writeflag == MEM_WRITE) {
-			debug("[ sh4: pdtrb: write: TODO ]\n");
-			d->pdtrb = idata;
-		} else {
-			debug("[ sh4: pdtrb: read: TODO ]\n");
-			odata = d->pdtrb;
-		}
-		break;
-
-	case SH4_GPIOIC:
-		if (writeflag == MEM_WRITE)
-			d->bsc_gpioic = idata;
-		else
-			odata = d->bsc_gpioic;
-		break;
-
-
-	/****************************/
-	/*  SCI:  Serial Interface  */
-
-	case SHREG_SCSPTR:
-		odata = sh4_sci_access(d, cpu,
-		    writeflag == MEM_WRITE? 1 : 0, idata);
-
-		/*
-		 *  TODO
-		 *
-		 *  Find out the REAL way to make OpenBSD/landisk 4.1 run
-		 *  in a stable manner! This is a SUPER-UGLY HACK which
-		 *  just side-steps the real bug.
-		 *
-		 *  NOTE:  Snapshots of OpenBSD/landisk _after_ 4.1 seem
-		 *  to work WITHOUT this hack, but NOT with it!
-		 */
-		cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
-
-		break;
-
-
-	/*********************************/
-	/*  INTC:  Interrupt Controller  */
-
-	case SH4_ICR:
-		if (writeflag == MEM_WRITE) {
-			if (idata & 0x80) {
-				fatal("SH4 INTC: IRLM not yet "
-				    "supported. TODO\n");
-				exit(1);
-			}
-		}
-		break;
-
-	case SH4_IPRA:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.intc_ipra;
-		else {
-			cpu->cd.sh.intc_ipra = idata;
-			sh_update_interrupt_priorities(cpu);
-		}
-		break;
-
-	case SH4_IPRB:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.intc_iprb;
-		else {
-			cpu->cd.sh.intc_iprb = idata;
-			sh_update_interrupt_priorities(cpu);
-		}
-		break;
-
-	case SH4_IPRC:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.intc_iprc;
-		else {
-			cpu->cd.sh.intc_iprc = idata;
-			sh_update_interrupt_priorities(cpu);
-		}
-		break;
-
-	case SH4_IPRD:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.intc_iprd;
-		else {
-			cpu->cd.sh.intc_iprd = idata;
-			sh_update_interrupt_priorities(cpu);
-		}
-		break;
-
-	case SH4_INTPRI00:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.intc_intpri00;
-		else {
-			cpu->cd.sh.intc_intpri00 = idata;
-			sh_update_interrupt_priorities(cpu);
-		}
-		break;
-
-	case SH4_INTPRI00 + 4:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.intc_intpri04;
-		else {
-			cpu->cd.sh.intc_intpri04 = idata;
-			sh_update_interrupt_priorities(cpu);
-		}
-		break;
-
-	case SH4_INTPRI00 + 8:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.intc_intpri08;
-		else {
-			cpu->cd.sh.intc_intpri08 = idata;
-			sh_update_interrupt_priorities(cpu);
-		}
-		break;
-
-	case SH4_INTPRI00 + 0xc:
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.intc_intpri0c;
-		else {
-			cpu->cd.sh.intc_intpri0c = idata;
-			sh_update_interrupt_priorities(cpu);
-		}
-		break;
-
-	case SH4_INTMSK00:
-		/*  Note: Writes can only set bits, not clear them.  */
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.intc_intmsk00;
-		else
-			cpu->cd.sh.intc_intmsk00 |= idata;
-		break;
-
-	case SH4_INTMSK00 + 4:
-		/*  Note: Writes can only set bits, not clear them.  */
-		if (writeflag == MEM_READ)
-			odata = cpu->cd.sh.intc_intmsk04;
-		else
-			cpu->cd.sh.intc_intmsk04 |= idata;
-		break;
-
-	case SH4_INTMSKCLR00:
-		/*  Note: Writes can only clear bits, not set them.  */
-		if (writeflag == MEM_WRITE)
-			cpu->cd.sh.intc_intmsk00 &= ~idata;
-		break;
-
-	case SH4_INTMSKCLR00 + 4:
-		/*  Note: Writes can only clear bits, not set them.  */
-		if (writeflag == MEM_WRITE)
-			cpu->cd.sh.intc_intmsk04 &= ~idata;
-		break;
-
-
-	/*************************************************/
-	/*  SCIF: Serial Controller Interface with FIFO  */
-
-	case SH4_SCIF_BASE + SCIF_SMR:
-		if (writeflag == MEM_WRITE) {
-			d->scif_smr = idata;
-		} else {
-			odata = d->scif_smr;
-		}
-		break;
-
-	case SH4_SCIF_BASE + SCIF_BRR:
-		if (writeflag == MEM_WRITE) {
-			d->scif_brr = idata;
-		} else {
-			odata = d->scif_brr;
-		}
-		break;
-
-	case SH4_SCIF_BASE + SCIF_SCR:
-		if (writeflag == MEM_WRITE) {
-			d->scif_scr = idata;
-			scif_reassert_interrupts(d);
-		} else {
-			odata = d->scif_scr;
-		}
-		break;
-
-	case SH4_SCIF_BASE + SCIF_FTDR:
-		if (writeflag == MEM_WRITE) {
-			/*  Add to TX fifo:  */
-			if (d->scif_tx_fifo_cursize >=
-			    sizeof(d->scif_tx_fifo)) {
-				fatal("[ SCIF TX fifo overrun! ]\n");
-				d->scif_tx_fifo_cursize = 0;
-			}
-
-			d->scif_tx_fifo[d->scif_tx_fifo_cursize++] = idata;
-			d->scif_delayed_tx = SCIF_DELAYED_TX_VALUE;
-		}
-		break;
-
-	case SH4_SCIF_BASE + SCIF_SSR:
-		if (writeflag == MEM_READ) {
-			odata = d->scif_ssr;
-		} else {
-			d->scif_ssr = idata;
-			scif_reassert_interrupts(d);
-		}
-		break;
-
-	case SH4_SCIF_BASE + SCIF_FRDR:
-		{
-			int x = console_readchar(d->scif_console_handle);
-			if (x == 13)
-				x = 10;
-			odata = x < 0? 0 : x;
-			if (console_charavail(d->scif_console_handle))
-				d->scif_ssr |= SCSSR2_DR;
-			else
-				d->scif_ssr &= ~SCSSR2_DR;
-			scif_reassert_interrupts(d);
-		}
-		break;
-
-	case SH4_SCIF_BASE + SCIF_FCR:
-		if (writeflag == MEM_WRITE) {
-			d->scif_fcr = idata;
-		} else {
-			odata = d->scif_fcr;
-		}
-		break;
-
-	case SH4_SCIF_BASE + SCIF_FDR:
-		/*  Nr of bytes in the TX and RX fifos, respectively:  */
-		{
-			int chars_avail = console_charavail(d->scif_console_handle);
-			if (chars_avail > 255) {
-				fatal("[ SH4: Too many chars avail; dropping some ]\n");
-				chars_avail = 255;
-			}
-			
-			odata = chars_avail | (d->scif_tx_fifo_cursize << 8);
-		}
-		break;
-
-	case SH4_SCIF_BASE + SCIF_SPTR:
-		/*  TODO: Implement all bits.  */
-		odata = 0;
-		break;
-
-	case SH4_SCIF_BASE + SCIF_LSR:
-		/*  TODO: Implement all bits.  */
-		odata = 0;
-		break;
-
-
-	/*************************************************/
-
-	case SH4_CPG_FRQCR:	// 0xffc00000	16-bit
-		if (writeflag == MEM_WRITE)
-			d->cpg_frqcr = idata;
-		else
-			odata = d->cpg_frqcr;
-		break;
-
-	case SH4_CPG_STBCR: 	// 0xffc00004	8-bit
-		if (writeflag == MEM_WRITE)
-			d->cpg_stbcr = idata;
-		else
-			odata = d->cpg_stbcr;
-		break;
-
-	case SH4_CPG_WTCNT:	// 0xffc00008	8/16-bit
-		if (writeflag == MEM_WRITE)
-			d->cpg_wtcnt = idata;
-		else
-			odata = d->cpg_wtcnt;
-		break;
-
-	case SH4_CPG_WTCSR:	// 0xffc0000c	8/16-bit
-		if (writeflag == MEM_WRITE)
-			d->cpg_wtcsr = idata;
-		else
-			odata = d->cpg_wtcsr;
-		break;
-
-	case SH4_CPG_STBCR2:	// 0xffc00010	8-bit
-		if (writeflag == MEM_WRITE)
-			d->cpg_stbcr2 = idata;
-		else
-			odata = d->cpg_stbcr2;
-		break;
-
-
-	/*************************************************/
-
-	case SH4_RSECCNT:
-	case SH4_RMINCNT:
-	case SH4_RHRCNT:
-	case SH4_RWKCNT:
-	case SH4_RDAYCNT:
-	case SH4_RMONCNT:
-	case SH4_RYRCNT:
-	case SH4_RSECAR:
-	case SH4_RMINAR:
-	case SH4_RHRAR:
-	case SH4_RWKAR:
-	case SH4_RDAYAR:
-	case SH4_RMONAR:
-		if (writeflag == MEM_WRITE) {
-			d->rtc_reg[(relative_addr - 0xffc80000) / 4] = idata;
-		} else {
-			/*  TODO: Update rtc_reg based on host's date/time.  */
-			odata = d->rtc_reg[(relative_addr - 0xffc80000) / 4];
-		}
-		break;
-
-	case SH4_RCR1:
-		if (writeflag == MEM_READ)
-			odata = d->rtc_rcr1;
-		else {
-			d->rtc_rcr1 = idata;
-			if (idata & 0x18) {
-				fatal("SH4: TODO: RTC interrupt enable\n");
-				exit(1);
-			}
-		}
-		break;
-
-	case SH4_RCR2:
-		if (writeflag == MEM_READ)
-			odata = d->rtc_rcr2;
-		else {
-			d->rtc_rcr2 = idata;
-			// bit 1 (i.e. idata == 0x02) means reset.
-			if (idata != 0x02) {
-				debug("[ SH4: TODO: RTC RCR2 value 0x%02x ignored. ]\n", (int)idata);
-			}
-		}
-		break;
-
-
-	/*************************************************/
-
-	default:if (writeflag == MEM_READ) {
-			fatal("[ sh4: read from addr 0x%x ]\n",
-			    (int)relative_addr);
-		} else {
-			fatal("[ sh4: write to addr 0x%x: 0x%x ]\n",
-			    (int)relative_addr, (int)idata);
-		}
-
-#ifdef SH4_DEBUG
-		exit(1);
-#endif
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(sh4)
-{
-	char tmp[200], n[200];
-	int i;
-	struct machine *machine = devinit->machine;
-	struct sh4_data *d;
-
-	CHECK_ALLOCATION(d = (struct sh4_data *) malloc(sizeof(struct sh4_data)));
-	memset(d, 0, sizeof(struct sh4_data));
-
-
-	/*
-	 *  Main SH4 device, and misc memory stuff:
-	 */
-
-	memory_device_register(machine->memory, devinit->name,
-	    SH4_REG_BASE, 0x01000000, dev_sh4_access, d, DM_DEFAULT, NULL);
-
-	/*  On-chip RAM/cache:  */
-	dev_ram_init(machine, 0x1e000000, 0x8000, DEV_RAM_RAM, 0x0);
-
-	/*  0xe0000000: Store queues:  */
-	memory_device_register(machine->memory, "sh4_sq",
-	    0xe0000000, 0x04000000, dev_sh4_sq_access, d, DM_DEFAULT, NULL);
-
-
-	/*
-	 *  SCIF (Serial console):
-	 */
-
-	d->scif_console_handle = console_start_slave(devinit->machine,
-	    "SH4 SCIF", 1);
-
-	snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]",
-	    devinit->interrupt_path, SH4_INTEVT_SCIF_RXI);
-	INTERRUPT_CONNECT(tmp, d->scif_rx_irq);
-	snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]",
-	    devinit->interrupt_path, SH4_INTEVT_SCIF_TXI);
-	INTERRUPT_CONNECT(tmp, d->scif_tx_irq);
-
-
-	/*
-	 *  Caches (fake):
- 	 *
-	 *  0xf0000000	SH4_CCIA	I-Cache address array
-	 *  0xf1000000	SH4_CCID	I-Cache data array
-	 *  0xf4000000	SH4_CCDA	D-Cache address array
-	 *  0xf5000000	SH4_CCDD	D-Cache data array
-	 *
-	 *  TODO: Implement more correct cache behavior?
-	 */
-
-	dev_ram_init(machine, SH4_CCIA, SH4_ICACHE_SIZE * 2, DEV_RAM_RAM, 0x0);
-	dev_ram_init(machine, SH4_CCID, SH4_ICACHE_SIZE,     DEV_RAM_RAM, 0x0);
-	dev_ram_init(machine, SH4_CCDA, SH4_DCACHE_SIZE * 2, DEV_RAM_RAM, 0x0);
-	dev_ram_init(machine, SH4_CCDD, SH4_DCACHE_SIZE,     DEV_RAM_RAM, 0x0);
-
-	/*  0xf2000000	SH4_ITLB_AA  */
-	memory_device_register(machine->memory, "sh4_itlb_aa", SH4_ITLB_AA,
-	    0x01000000, dev_sh4_itlb_aa_access, d, DM_DEFAULT, NULL);
-
-	/*  0xf3000000	SH4_ITLB_DA1  */
-	memory_device_register(machine->memory, "sh4_itlb_da1", SH4_ITLB_DA1,
-	    0x01000000, dev_sh4_itlb_da1_access, d, DM_DEFAULT, NULL);
-
-	/*  0xf6000000	SH4_UTLB_AA  */
-	memory_device_register(machine->memory, "sh4_utlb_aa", SH4_UTLB_AA,
-	    0x01000000, dev_sh4_utlb_aa_access, d, DM_DEFAULT, NULL);
-
-	/*  0xf7000000	SH4_UTLB_DA1  */
-	memory_device_register(machine->memory, "sh4_utlb_da1", SH4_UTLB_DA1,
-	    0x01000000, dev_sh4_utlb_da1_access, d, DM_DEFAULT, NULL);
-
-
-	/*
-	 *  PCIC (PCI controller) at 0xfe200000:
-	 */
-
-	memory_device_register(machine->memory, "sh4_pcic", SH4_PCIC,
-	    N_PCIC_REGS * sizeof(uint32_t), dev_sh4_pcic_access, d,
-	    DM_DEFAULT, NULL);
-
-	/*  Initial PCI control register contents:  */
-	d->bsc_bcr2 = BCR2_PORTEN;
-	d->pcic_reg[PCIC_REG(SH4_PCICONF2)] = PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
-	    PCI_SUBCLASS_BRIDGE_HOST, 0);
-
-	/*  Register 16 PCIC interrupts:  */
-	for (i=0; i<N_PCIC_IRQS; i++) {
-		struct interrupt templ;
-		snprintf(n, sizeof(n), "%s.pcic.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = sh4_pcic_interrupt_assert;
-		templ.interrupt_deassert = sh4_pcic_interrupt_deassert;
-		interrupt_handler_register(&templ);
-
-		snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]",
-		    devinit->interrupt_path, SH4_INTEVT_IRQ0 + 0x20 * i);
-		INTERRUPT_CONNECT(tmp, d->cpu_pcic_interrupt[i]);
-	}
-
-	/*  Register the PCI bus:  */
-	snprintf(tmp, sizeof(tmp), "%s.pcic", devinit->interrupt_path);
-	d->pci_data = bus_pci_init(
-	    devinit->machine,
-	    tmp,			/*  pciirq  */
-	    0,				/*  pci device io offset  */
-	    0,				/*  pci device mem offset  */
-	    SH4_PCIC_IO,		/*  PCI portbase  */
-	    SH4_PCIC_MEM,		/*  PCI membase  */
-	    tmp,			/*  PCI irqbase  */
-	    0x00000000,			/*  ISA portbase  */
-	    0x00000000,			/*  ISA membase  */
-	    "TODOisaIrqBase");		/*  ISA irqbase  */
-
-	/*  Return PCI bus pointer, to allow per-machine devices
-	    to be added later:  */
-	devinit->return_ptr = d->pci_data;
-
-
-	/*
-	 *  Timer:
-	 */
-
-	d->sh4_timer = timer_add(SH4_PSEUDO_TIMER_HZ, sh4_timer_tick, d);
-	machine_add_tickfunction(devinit->machine, dev_sh4_tick, d,
-	    SH4_TICK_SHIFT);
-
-	/*  Initial Timer values, according to the SH7750 manual:  */
-	d->tcor[0] = 0xffffffff; d->tcnt[0] = 0xffffffff;
-	d->tcor[1] = 0xffffffff; d->tcnt[1] = 0xffffffff;
-	d->tcor[2] = 0xffffffff; d->tcnt[2] = 0xffffffff;
-
-	snprintf(tmp, sizeof(tmp), "machine[0].cpu[0].irq[0x%x]",
-	    SH_INTEVT_TMU0_TUNI0);
-	if (!interrupt_handler_lookup(tmp, &d->timer_irq[0])) {
-		fatal("Could not find interrupt '%s'.\n", tmp);
-		exit(1);
-	}
-	snprintf(tmp, sizeof(tmp), "machine[0].cpu[0].irq[0x%x]",
-	    SH_INTEVT_TMU1_TUNI1);
-	if (!interrupt_handler_lookup(tmp, &d->timer_irq[1])) {
-		fatal("Could not find interrupt '%s'.\n", tmp);
-		exit(1);
-	}
-	snprintf(tmp, sizeof(tmp), "machine[0].cpu[0].irq[0x%x]",
-	    SH_INTEVT_TMU2_TUNI2);
-	if (!interrupt_handler_lookup(tmp, &d->timer_irq[2])) {
-		fatal("Could not find interrupt '%s'.\n", tmp);
-		exit(1);
-	}
-
-
-	// The RTC RCR2 register is "basically" initialized to 0x09, with
-	// some bit undefined. :-) According to the manual.
-	d->rtc_rcr2 = 0x09;
-
-
-	/*
-	 *  Bus State Controller initial values, according to the
-	 *  SH7760 manual:
-	 */
-
-	d->bsc_bcr2 = 0x3ffc;
-	d->bsc_wcr1 = 0x77777777;
-	d->bsc_wcr2 = 0xfffeefff;
-	d->bsc_wcr3 = 0x77777777;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_sii.c gxemul-0.7.0+dfsg/src/devices/dev_sii.c
--- gxemul-0.6.2/src/devices/dev_sii.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sii.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,460 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: SII SCSI controller, used in some DECstation systems
+ *
+ *  TODO:  This is huge and ugly. Fix this.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "devices.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/siireg.h"
+
+
+#define	SII_TICK_SHIFT		14
+
+
+struct sii_data {
+	struct interrupt irq;
+
+	uint64_t	buf_start;
+	uint64_t	buf_end;
+
+	int		connected;
+	int		connected_to_id;
+
+	int		register_choice;
+	SIIRegs		siiregs;
+	uint16_t	*regs;
+};
+
+
+/*
+ *  combine_sii_bits():
+ *
+ *  Combines some bits of CSTAT and DSTAT that are connected.
+ */
+void combine_sii_bits(struct sii_data *d)
+{
+	int ci, di;
+
+	di = ((d->siiregs.dstat & SII_MIS) |
+	      (d->siiregs.dstat & SII_IBF) |
+	      (d->siiregs.dstat & SII_TBE) |
+	      (d->siiregs.dstat & SII_DNE))==0? 0 : SII_DI;
+
+	ci = ((d->siiregs.cstat & SII_RST) |
+	      (d->siiregs.cstat & SII_BER) |
+	      (d->siiregs.cstat & SII_OBC) |
+	      (d->siiregs.cstat & SII_BUF) |
+	      (d->siiregs.cstat & SII_LDN) |
+	      (d->siiregs.cstat & SII_SCH))==0? 0 : SII_CI;
+
+	d->siiregs.cstat &= ~(SII_CI | SII_DI);
+	d->siiregs.dstat &= ~(SII_CI | SII_DI);
+
+	d->siiregs.cstat |= (ci | di);
+	d->siiregs.dstat |= (ci | di);
+}
+
+
+DEVICE_TICK(sii)
+{
+	struct sii_data *d = (struct sii_data *) extra;
+
+	/*  ?  */
+	d->siiregs.dstat = (d->siiregs.dstat & ~0x7)
+	    | ((d->siiregs.dstat + 1) & 0x7);
+
+	/*  SCSI Commands:  */
+
+	if (d->siiregs.comm & SII_CHRESET) {		/*  (I,T,D)  */
+		/*  debug("[ sii: command TODO: CHRESET ]\n");  */
+	}
+
+	if (d->siiregs.comm & SII_DISCON) {		/*  (I,T,D)  */
+		/*  debug("[ sii: command TODO: DISCON ]\n");  */
+		d->siiregs.cstat &= ~SII_CON;	/*  Connected  */
+
+		if (d->connected) {
+			d->siiregs.cstat |= SII_SCH;	/*  State change  */
+			d->connected = 0;
+		}
+
+		d->siiregs.cstat &= ~SII_SIP;  	/*  Selection in progress  */
+		d->siiregs.comm  &= ~SII_DISCON;
+	}
+
+	if (d->siiregs.comm & SII_REQDATA) {	/*  (T)  */
+		/*  debug("[ sii: command TODO: REQDATA ]\n");  */
+	}
+
+	if (d->siiregs.comm & SII_SELECT) {		/*  (D)  */
+		/*  debug("[ sii: command SELECT ]\n");  */
+		d->siiregs.comm &= ~SII_SELECT;
+
+		/*  slcsr contains the other target's id  */
+		d->siiregs.cstat |= SII_SIP;	/*  Selection in progress  */
+		d->connected = 0;
+		d->connected_to_id = 0;
+
+		/*  Is the target available for selection?
+		    TODO: make this nicer  */
+#if 0
+		if ((d->siiregs.slcsr & 7) == 0) {
+			d->siiregs.cstat |=  SII_CON;	/*  Connected  */
+			d->siiregs.cstat |=  SII_SCH;	/*  State change  */
+			d->siiregs.cstat &= ~SII_SIP;	/*  Sel. in progress  */
+
+			d->connected = 1;
+			d->connected_to_id = 0;
+		}
+#endif
+	}
+
+	if (d->siiregs.comm & SII_INXFER
+	    && (d->siiregs.comm & 0x70) == (d->siiregs.cstat & 0x70) &&
+	    (d->siiregs.comm & 0x03) == (d->siiregs.dstat & 0x03) &&
+	    !(d->siiregs.cstat & SII_SIP)) {	/*  (I,T)  */
+		debug("[ sii: command INXFER to scsiid=%i ]\n",
+		    d->siiregs.slcsr);
+		if (d->siiregs.comm & SII_DMA)
+			debug("[ sii DMA: TODO ]\n");
+		else {
+			debug("[ sii: transmitting byte 0x%02x using "
+			    "PIO mode ]\n", d->siiregs.data);
+			d->siiregs.comm &= ~SII_INXFER;
+
+/*			d->siiregs.dstat |= SII_DNE; */
+			    /*  Done, only for DMA?  */
+			d->siiregs.dstat |= SII_TBE;	/*  Buffer empty?  */
+		}
+	}
+
+	combine_sii_bits(d);
+
+	if (d->siiregs.csr & SII_IE && d->siiregs.cstat & (SII_CI | SII_DI))
+		INTERRUPT_ASSERT(d->irq);
+	else
+		INTERRUPT_DEASSERT(d->irq);
+}
+
+
+DEVICE_ACCESS(sii)
+{
+	uint64_t idata = 0, odata = 0;
+	int regnr;
+	struct sii_data *d = (struct sii_data *) extra;
+
+	if (relative_addr & 3) {
+		debug("[ sii relative_addr = 0x%x !!! ]\n",
+		    (int) relative_addr);
+		return 0;
+	}
+
+	dev_sii_tick(cpu, extra);
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	regnr = relative_addr / 2;
+	odata = d->regs[regnr];
+
+	switch (relative_addr) {
+	case 0x00:				/*  SII_SDB: Diagnostic  */
+		if (writeflag == MEM_READ) {
+			debug("[ sii: read from SDB (data=0x%04x) ]\n",
+			    d->regs[regnr]);
+		} else {
+			debug("[ sii: write to  SDB (data=0x%04x) ]\n",
+			    (int)idata);
+			d->regs[regnr] = idata;
+			return 1;
+		}
+		break;
+	case 0x0c:				/*  SII_CSR: Control/status  */
+		if (writeflag == MEM_READ) {
+			debug("[ sii: read from CSR (data=0x%04x) ]\n",
+			    d->regs[regnr]);
+		} else {
+			debug("[ sii: write to  CSR (data=0x%04x: %s %s "
+			    "%s %s %s) ]\n", (int)idata,
+			    idata & SII_HPM? "HPM" : "!hpm",
+			    idata & SII_RSE? "RSE" : "!rse",
+			    idata & SII_SLE? "SLE" : "!sle",
+			    idata & SII_PCE? "PCE" : "!pce",
+			    idata & SII_IE?  "IE"  : "!ie");
+			d->regs[regnr] = idata;
+			return 1;
+		}
+		break;
+	case 0x10:				/*  SII_ID: SCSI ID  */
+		if (writeflag == MEM_READ) {
+			debug("[ sii: read from ID (data=0x%04x) ]\n",
+			    d->regs[regnr]);
+		} else {
+			debug("[ sii: write to  ID (data=0x%04x: scsi id %i)"
+			    " ]\n", (int)idata, (int)(idata & 7));
+			if (!(idata & SII_ID_IO))
+				debug("WARNING: sii ID bit SII_ID_IO not "
+				    "set on write!\n");
+			idata &= ~SII_ID_IO;
+			if ((idata & ~0x7) != 0)
+				debug("WARNING: sii ID bits that should "
+				    "be zero are not zero!\n");
+			idata &= 0x7;
+			d->regs[regnr] = idata & 0x7;
+			return 1;
+		}
+		break;
+	case 0x14:			/*  SII_SLCSR: Selector control  */
+		if (writeflag == MEM_READ) {
+			debug("[ sii: read from SLCSR (data=0x%04x: "
+			    "scsi_id=%i) ]\n", d->regs[regnr],
+			    d->regs[regnr] & 7);
+		} else {
+			debug("[ sii: write to  SLCSR (data=0x%04x: "
+			    "scsi_id=%i) ]\n", (int)idata, (int)(idata & 7));
+			if ((idata & ~0x7) != 0)
+				debug("WARNING: sii SLCSR bits that should "
+				    "be zero are not zero!\n");
+			idata &= 0x7;
+			d->regs[regnr] = idata & 0x7;
+			return 1;
+		}
+		break;
+	case 0x18:		/*  SII_DESTAT: Selection detector status  */
+		if (writeflag == MEM_READ) {
+			/*  TODO: set DESTAT from somewhere else?  */
+			debug("[ sii: read from DESTAT (data=0x%04x: "
+			    "scsi_id=%i) ]\n", d->regs[regnr],
+			    d->regs[regnr] & 7);
+		} else {
+			debug("[ sii: write to  DESTAT (data=0x%04x: "
+			    "scsi_id=%i) ]\n", (int)idata, (int)(idata & 7));
+			debug("WARNING: sii DESTAT is read-only!\n");
+			return 1;
+		}
+		break;
+	case 0x20:				/*  SII_DATA: Data register  */
+		if (writeflag == MEM_READ) {
+			/*  TODO  */
+			debug("[ sii: read from DATA (data=0x%04x) ]\n",
+			    d->regs[regnr]);
+		} else {
+			/*  TODO  */
+			debug("[ sii: write to  DATA (data=0x%04x) ]\n",
+			    (int)idata);
+			idata &= 0xff;
+			d->regs[regnr] = idata;
+			return 1;
+		}
+		break;
+	case 0x24:				/*  SII_DMCTRL: DMA control  */
+		if (writeflag == MEM_READ) {
+			debug("[ sii: read from DMCTRL (data=0x%04x) ]\n",
+			    d->regs[regnr]);
+		} else {
+			debug("[ sii: write to  DMCTRL (data=0x%04x: %s) ]\n",
+			    (int)idata, (idata & 3)==0? "async" : "sync");
+			if ((idata & ~0x3) != 0)
+				debug("WARNING: sii DMCTRL bits that "
+				    "should be zero are not zero!\n");
+			idata &= 0x3;
+			d->regs[regnr] = idata;
+			return 1;
+		}
+		break;
+	case 0x48:			/*  SII_CSTAT: Connection status  */
+		if (writeflag == MEM_READ) {
+			debug("[ sii: read from CSTAT (data=0x%04x) ]\n",
+			    d->regs[regnr]);
+		} else {
+			debug("[ sii: write to  CSTAT (data=0x%04x) ]\n",
+			    (int)idata);
+
+			/*  readonly / writeoncetoclear bits according
+			    to page 21 in the DS3100 manual:  */
+			if (idata & (1<<13)) {
+				idata &= ~(1<<13); d->regs[regnr] &= ~(1<<13);
+			}
+			if (idata & (1<<12)) {
+				idata &= ~(1<<12); d->regs[regnr] &= ~(1<<12);
+			}
+			if (idata & (1<<11)) {
+				/*  is this actually write-1-to-clear?  */
+				idata &= ~(1<<11); d->regs[regnr] &= ~(1<<11);
+			}
+			if (idata & (1<<9)) {
+				/*  ?  */
+				idata &= ~(1<<9); d->regs[regnr] &= ~(1<<9);
+			}
+			if (idata & (1<<8)) {
+				/*  ?  */
+				idata &= ~(1<<8); d->regs[regnr] &= ~(1<<8);
+			}
+			if (idata & (1<<7)) {
+				idata &= ~(1<<7); d->regs[regnr] &= ~(1<<7);
+			}
+			if (idata & (1<<3)) {
+				idata &= ~(1<<3); d->regs[regnr] &= ~(1<<3);
+			}
+
+			/*  Read-only bits are taken from the old register:  */
+			idata &= ~0x3bf7;
+			idata |= d->regs[regnr] & 0x3bf7;
+
+			d->regs[regnr] = idata;
+			return 1;
+		}
+		break;
+	case 0x4c:			/*  SII_DSTAT: Data transfer status  */
+		if (writeflag == MEM_READ) {
+			debug("[ sii: read from DSTAT (data=0x%04x) ]\n",
+			    d->regs[regnr]);
+		} else {
+			debug("[ sii: write to  DSTAT (data=0x%04x) ]\n",
+			    (int)idata);
+
+			/*  readonly / writeoncetoclear bits
+			    according to page 22 in the DS3100 manual:  */
+			if (idata & (1<<13)) {
+				idata &= ~(1<<13); d->regs[regnr] &= ~(1<<13);
+			}
+			if (idata & (1<<11)) {
+				/*  is this write-1-to-clear?  */
+				idata &= ~(1<<11); d->regs[regnr] &= ~(1<<11);
+			}
+			if (idata & (1<<10)) {
+				/*  is this write-1-to-clear?  */
+				idata &= ~(1<<10); d->regs[regnr] &= ~(1<<10);
+			}
+			if (idata & (1<<4)) {
+				/*  is this write-1-to-clear?  */
+				idata &= ~(1<<4); d->regs[regnr] &= ~(1<<4);
+			}
+			if (idata & (1<<3)) {
+				idata &= ~(1<<3); d->regs[regnr] &= ~(1<<3);
+			}
+
+			/*  Read-only bits are taken from the old register:  */
+			idata &= ~0x0c17;
+			idata |= d->regs[regnr] & 0x0c17;
+
+			d->regs[regnr] = idata;
+			return 1;
+		}
+		break;
+	case 0x50:				/*  SII_COMM: Command  */
+		if (writeflag == MEM_READ) {
+			debug("[ sii: read from COMM (data=0x%04x) ]\n",
+			    d->regs[regnr]);
+		} else {
+			debug("[ sii: write to  COMM (data=0x%04x: %s %s "
+			    "%s command=0x%02x rest=0x%02x) ]\n", (int)idata,
+			    idata & SII_DMA?    "DMA" : "!dma",
+			    idata & SII_DO_RST? "RST" : "!rst",
+			    idata & SII_RSL?    "RSL" : "!rsl",
+			    /*  command, 5 bits:  */
+			    (int)((idata >> 7) & 0x1f),
+			    /*  rest, 7 bits:  */
+			    (int)(idata & 0x3f));
+
+			if (idata & SII_DO_RST) {
+				/*  Reset: TODO  */
+			}
+
+			idata &= ~SII_DO_RST;
+			d->regs[regnr] = idata;
+
+			dev_sii_tick(cpu, extra);
+			return 1;
+		}
+		break;
+	case 0x54:			/*  SII_DICTRL: Diagnostics control  */
+		if (writeflag == MEM_READ) {
+			debug("[ sii: read from DICTRL (data=0x%04x) ]\n",
+			    d->regs[regnr]);
+		} else {
+			debug("[ sii: write to  DICTRL (data=0x%04x: "
+			    "port=%s) ]\n", (int)idata,
+			    idata & SII_PRE? "enabled" : "disabled");
+			if ((idata & ~0xf) != 0)
+				debug("WARNING: sii DICTRL bits that "
+				    "should be zero are not zero!\n");
+			d->regs[regnr] = idata;
+			return 1;
+		}
+		break;
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ sii: read from %08lx (data=0x%04x) ]\n",
+			    (long)relative_addr, d->regs[regnr]);
+		} else {
+			debug("[ sii: write to  %08lx (data=0x%04x) ]\n",
+			    (long)relative_addr, (int)idata);
+			d->regs[regnr] = idata;
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+void dev_sii_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, uint64_t buf_start, uint64_t buf_end,
+	char *irq_path)
+{
+	struct sii_data *d;
+
+	CHECK_ALLOCATION(d = (struct sii_data *) malloc(sizeof(struct sii_data)));
+	memset(d, 0, sizeof(struct sii_data));
+
+	INTERRUPT_CONNECT(irq_path, d->irq);
+	d->buf_start = buf_start;
+	d->buf_end   = buf_end;
+	d->regs      = (uint16_t *) &d->siiregs;
+
+	memory_device_register(mem, "sii", baseaddr, DEV_SII_LENGTH,
+	    dev_sii_access, (void *)d, DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(machine, dev_sii_tick, d,
+	    SII_TICK_SHIFT);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_sii.cc gxemul-0.7.0+dfsg/src/devices/dev_sii.cc
--- gxemul-0.6.2/src/devices/dev_sii.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sii.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,460 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: SII SCSI controller, used in some DECstation systems
- *
- *  TODO:  This is huge and ugly. Fix this.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "devices.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/siireg.h"
-
-
-#define	SII_TICK_SHIFT		14
-
-
-struct sii_data {
-	struct interrupt irq;
-
-	uint64_t	buf_start;
-	uint64_t	buf_end;
-
-	int		connected;
-	int		connected_to_id;
-
-	int		register_choice;
-	SIIRegs		siiregs;
-	uint16_t	*regs;
-};
-
-
-/*
- *  combine_sii_bits():
- *
- *  Combines some bits of CSTAT and DSTAT that are connected.
- */
-void combine_sii_bits(struct sii_data *d)
-{
-	int ci, di;
-
-	di = ((d->siiregs.dstat & SII_MIS) |
-	      (d->siiregs.dstat & SII_IBF) |
-	      (d->siiregs.dstat & SII_TBE) |
-	      (d->siiregs.dstat & SII_DNE))==0? 0 : SII_DI;
-
-	ci = ((d->siiregs.cstat & SII_RST) |
-	      (d->siiregs.cstat & SII_BER) |
-	      (d->siiregs.cstat & SII_OBC) |
-	      (d->siiregs.cstat & SII_BUF) |
-	      (d->siiregs.cstat & SII_LDN) |
-	      (d->siiregs.cstat & SII_SCH))==0? 0 : SII_CI;
-
-	d->siiregs.cstat &= ~(SII_CI | SII_DI);
-	d->siiregs.dstat &= ~(SII_CI | SII_DI);
-
-	d->siiregs.cstat |= (ci | di);
-	d->siiregs.dstat |= (ci | di);
-}
-
-
-DEVICE_TICK(sii)
-{
-	struct sii_data *d = (struct sii_data *) extra;
-
-	/*  ?  */
-	d->siiregs.dstat = (d->siiregs.dstat & ~0x7)
-	    | ((d->siiregs.dstat + 1) & 0x7);
-
-	/*  SCSI Commands:  */
-
-	if (d->siiregs.comm & SII_CHRESET) {		/*  (I,T,D)  */
-		/*  debug("[ sii: command TODO: CHRESET ]\n");  */
-	}
-
-	if (d->siiregs.comm & SII_DISCON) {		/*  (I,T,D)  */
-		/*  debug("[ sii: command TODO: DISCON ]\n");  */
-		d->siiregs.cstat &= ~SII_CON;	/*  Connected  */
-
-		if (d->connected) {
-			d->siiregs.cstat |= SII_SCH;	/*  State change  */
-			d->connected = 0;
-		}
-
-		d->siiregs.cstat &= ~SII_SIP;  	/*  Selection in progress  */
-		d->siiregs.comm  &= ~SII_DISCON;
-	}
-
-	if (d->siiregs.comm & SII_REQDATA) {	/*  (T)  */
-		/*  debug("[ sii: command TODO: REQDATA ]\n");  */
-	}
-
-	if (d->siiregs.comm & SII_SELECT) {		/*  (D)  */
-		/*  debug("[ sii: command SELECT ]\n");  */
-		d->siiregs.comm &= ~SII_SELECT;
-
-		/*  slcsr contains the other target's id  */
-		d->siiregs.cstat |= SII_SIP;	/*  Selection in progress  */
-		d->connected = 0;
-		d->connected_to_id = 0;
-
-		/*  Is the target available for selection?
-		    TODO: make this nicer  */
-#if 0
-		if ((d->siiregs.slcsr & 7) == 0) {
-			d->siiregs.cstat |=  SII_CON;	/*  Connected  */
-			d->siiregs.cstat |=  SII_SCH;	/*  State change  */
-			d->siiregs.cstat &= ~SII_SIP;	/*  Sel. in progress  */
-
-			d->connected = 1;
-			d->connected_to_id = 0;
-		}
-#endif
-	}
-
-	if (d->siiregs.comm & SII_INXFER
-	    && (d->siiregs.comm & 0x70) == (d->siiregs.cstat & 0x70) &&
-	    (d->siiregs.comm & 0x03) == (d->siiregs.dstat & 0x03) &&
-	    !(d->siiregs.cstat & SII_SIP)) {	/*  (I,T)  */
-		debug("[ sii: command INXFER to scsiid=%i ]\n",
-		    d->siiregs.slcsr);
-		if (d->siiregs.comm & SII_DMA)
-			debug("[ sii DMA: TODO ]\n");
-		else {
-			debug("[ sii: transmitting byte 0x%02x using "
-			    "PIO mode ]\n", d->siiregs.data);
-			d->siiregs.comm &= ~SII_INXFER;
-
-/*			d->siiregs.dstat |= SII_DNE; */
-			    /*  Done, only for DMA?  */
-			d->siiregs.dstat |= SII_TBE;	/*  Buffer empty?  */
-		}
-	}
-
-	combine_sii_bits(d);
-
-	if (d->siiregs.csr & SII_IE && d->siiregs.cstat & (SII_CI | SII_DI))
-		INTERRUPT_ASSERT(d->irq);
-	else
-		INTERRUPT_DEASSERT(d->irq);
-}
-
-
-DEVICE_ACCESS(sii)
-{
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-	struct sii_data *d = (struct sii_data *) extra;
-
-	if (relative_addr & 3) {
-		debug("[ sii relative_addr = 0x%x !!! ]\n",
-		    (int) relative_addr);
-		return 0;
-	}
-
-	dev_sii_tick(cpu, extra);
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	regnr = relative_addr / 2;
-	odata = d->regs[regnr];
-
-	switch (relative_addr) {
-	case 0x00:				/*  SII_SDB: Diagnostic  */
-		if (writeflag == MEM_READ) {
-			debug("[ sii: read from SDB (data=0x%04x) ]\n",
-			    d->regs[regnr]);
-		} else {
-			debug("[ sii: write to  SDB (data=0x%04x) ]\n",
-			    (int)idata);
-			d->regs[regnr] = idata;
-			return 1;
-		}
-		break;
-	case 0x0c:				/*  SII_CSR: Control/status  */
-		if (writeflag == MEM_READ) {
-			debug("[ sii: read from CSR (data=0x%04x) ]\n",
-			    d->regs[regnr]);
-		} else {
-			debug("[ sii: write to  CSR (data=0x%04x: %s %s "
-			    "%s %s %s) ]\n", (int)idata,
-			    idata & SII_HPM? "HPM" : "!hpm",
-			    idata & SII_RSE? "RSE" : "!rse",
-			    idata & SII_SLE? "SLE" : "!sle",
-			    idata & SII_PCE? "PCE" : "!pce",
-			    idata & SII_IE?  "IE"  : "!ie");
-			d->regs[regnr] = idata;
-			return 1;
-		}
-		break;
-	case 0x10:				/*  SII_ID: SCSI ID  */
-		if (writeflag == MEM_READ) {
-			debug("[ sii: read from ID (data=0x%04x) ]\n",
-			    d->regs[regnr]);
-		} else {
-			debug("[ sii: write to  ID (data=0x%04x: scsi id %i)"
-			    " ]\n", (int)idata, (int)(idata & 7));
-			if (!(idata & SII_ID_IO))
-				debug("WARNING: sii ID bit SII_ID_IO not "
-				    "set on write!\n");
-			idata &= ~SII_ID_IO;
-			if ((idata & ~0x7) != 0)
-				debug("WARNING: sii ID bits that should "
-				    "be zero are not zero!\n");
-			idata &= 0x7;
-			d->regs[regnr] = idata & 0x7;
-			return 1;
-		}
-		break;
-	case 0x14:			/*  SII_SLCSR: Selector control  */
-		if (writeflag == MEM_READ) {
-			debug("[ sii: read from SLCSR (data=0x%04x: "
-			    "scsi_id=%i) ]\n", d->regs[regnr],
-			    d->regs[regnr] & 7);
-		} else {
-			debug("[ sii: write to  SLCSR (data=0x%04x: "
-			    "scsi_id=%i) ]\n", (int)idata, (int)(idata & 7));
-			if ((idata & ~0x7) != 0)
-				debug("WARNING: sii SLCSR bits that should "
-				    "be zero are not zero!\n");
-			idata &= 0x7;
-			d->regs[regnr] = idata & 0x7;
-			return 1;
-		}
-		break;
-	case 0x18:		/*  SII_DESTAT: Selection detector status  */
-		if (writeflag == MEM_READ) {
-			/*  TODO: set DESTAT from somewhere else?  */
-			debug("[ sii: read from DESTAT (data=0x%04x: "
-			    "scsi_id=%i) ]\n", d->regs[regnr],
-			    d->regs[regnr] & 7);
-		} else {
-			debug("[ sii: write to  DESTAT (data=0x%04x: "
-			    "scsi_id=%i) ]\n", (int)idata, (int)(idata & 7));
-			debug("WARNING: sii DESTAT is read-only!\n");
-			return 1;
-		}
-		break;
-	case 0x20:				/*  SII_DATA: Data register  */
-		if (writeflag == MEM_READ) {
-			/*  TODO  */
-			debug("[ sii: read from DATA (data=0x%04x) ]\n",
-			    d->regs[regnr]);
-		} else {
-			/*  TODO  */
-			debug("[ sii: write to  DATA (data=0x%04x) ]\n",
-			    (int)idata);
-			idata &= 0xff;
-			d->regs[regnr] = idata;
-			return 1;
-		}
-		break;
-	case 0x24:				/*  SII_DMCTRL: DMA control  */
-		if (writeflag == MEM_READ) {
-			debug("[ sii: read from DMCTRL (data=0x%04x) ]\n",
-			    d->regs[regnr]);
-		} else {
-			debug("[ sii: write to  DMCTRL (data=0x%04x: %s) ]\n",
-			    (int)idata, (idata & 3)==0? "async" : "sync");
-			if ((idata & ~0x3) != 0)
-				debug("WARNING: sii DMCTRL bits that "
-				    "should be zero are not zero!\n");
-			idata &= 0x3;
-			d->regs[regnr] = idata;
-			return 1;
-		}
-		break;
-	case 0x48:			/*  SII_CSTAT: Connection status  */
-		if (writeflag == MEM_READ) {
-			debug("[ sii: read from CSTAT (data=0x%04x) ]\n",
-			    d->regs[regnr]);
-		} else {
-			debug("[ sii: write to  CSTAT (data=0x%04x) ]\n",
-			    (int)idata);
-
-			/*  readonly / writeoncetoclear bits according
-			    to page 21 in the DS3100 manual:  */
-			if (idata & (1<<13)) {
-				idata &= ~(1<<13); d->regs[regnr] &= ~(1<<13);
-			}
-			if (idata & (1<<12)) {
-				idata &= ~(1<<12); d->regs[regnr] &= ~(1<<12);
-			}
-			if (idata & (1<<11)) {
-				/*  is this actually write-1-to-clear?  */
-				idata &= ~(1<<11); d->regs[regnr] &= ~(1<<11);
-			}
-			if (idata & (1<<9)) {
-				/*  ?  */
-				idata &= ~(1<<9); d->regs[regnr] &= ~(1<<9);
-			}
-			if (idata & (1<<8)) {
-				/*  ?  */
-				idata &= ~(1<<8); d->regs[regnr] &= ~(1<<8);
-			}
-			if (idata & (1<<7)) {
-				idata &= ~(1<<7); d->regs[regnr] &= ~(1<<7);
-			}
-			if (idata & (1<<3)) {
-				idata &= ~(1<<3); d->regs[regnr] &= ~(1<<3);
-			}
-
-			/*  Read-only bits are taken from the old register:  */
-			idata &= ~0x3bf7;
-			idata |= d->regs[regnr] & 0x3bf7;
-
-			d->regs[regnr] = idata;
-			return 1;
-		}
-		break;
-	case 0x4c:			/*  SII_DSTAT: Data transfer status  */
-		if (writeflag == MEM_READ) {
-			debug("[ sii: read from DSTAT (data=0x%04x) ]\n",
-			    d->regs[regnr]);
-		} else {
-			debug("[ sii: write to  DSTAT (data=0x%04x) ]\n",
-			    (int)idata);
-
-			/*  readonly / writeoncetoclear bits
-			    according to page 22 in the DS3100 manual:  */
-			if (idata & (1<<13)) {
-				idata &= ~(1<<13); d->regs[regnr] &= ~(1<<13);
-			}
-			if (idata & (1<<11)) {
-				/*  is this write-1-to-clear?  */
-				idata &= ~(1<<11); d->regs[regnr] &= ~(1<<11);
-			}
-			if (idata & (1<<10)) {
-				/*  is this write-1-to-clear?  */
-				idata &= ~(1<<10); d->regs[regnr] &= ~(1<<10);
-			}
-			if (idata & (1<<4)) {
-				/*  is this write-1-to-clear?  */
-				idata &= ~(1<<4); d->regs[regnr] &= ~(1<<4);
-			}
-			if (idata & (1<<3)) {
-				idata &= ~(1<<3); d->regs[regnr] &= ~(1<<3);
-			}
-
-			/*  Read-only bits are taken from the old register:  */
-			idata &= ~0x0c17;
-			idata |= d->regs[regnr] & 0x0c17;
-
-			d->regs[regnr] = idata;
-			return 1;
-		}
-		break;
-	case 0x50:				/*  SII_COMM: Command  */
-		if (writeflag == MEM_READ) {
-			debug("[ sii: read from COMM (data=0x%04x) ]\n",
-			    d->regs[regnr]);
-		} else {
-			debug("[ sii: write to  COMM (data=0x%04x: %s %s "
-			    "%s command=0x%02x rest=0x%02x) ]\n", (int)idata,
-			    idata & SII_DMA?    "DMA" : "!dma",
-			    idata & SII_DO_RST? "RST" : "!rst",
-			    idata & SII_RSL?    "RSL" : "!rsl",
-			    /*  command, 5 bits:  */
-			    (int)((idata >> 7) & 0x1f),
-			    /*  rest, 7 bits:  */
-			    (int)(idata & 0x3f));
-
-			if (idata & SII_DO_RST) {
-				/*  Reset: TODO  */
-			}
-
-			idata &= ~SII_DO_RST;
-			d->regs[regnr] = idata;
-
-			dev_sii_tick(cpu, extra);
-			return 1;
-		}
-		break;
-	case 0x54:			/*  SII_DICTRL: Diagnostics control  */
-		if (writeflag == MEM_READ) {
-			debug("[ sii: read from DICTRL (data=0x%04x) ]\n",
-			    d->regs[regnr]);
-		} else {
-			debug("[ sii: write to  DICTRL (data=0x%04x: "
-			    "port=%s) ]\n", (int)idata,
-			    idata & SII_PRE? "enabled" : "disabled");
-			if ((idata & ~0xf) != 0)
-				debug("WARNING: sii DICTRL bits that "
-				    "should be zero are not zero!\n");
-			d->regs[regnr] = idata;
-			return 1;
-		}
-		break;
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ sii: read from %08lx (data=0x%04x) ]\n",
-			    (long)relative_addr, d->regs[regnr]);
-		} else {
-			debug("[ sii: write to  %08lx (data=0x%04x) ]\n",
-			    (long)relative_addr, (int)idata);
-			d->regs[regnr] = idata;
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-void dev_sii_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, uint64_t buf_start, uint64_t buf_end,
-	char *irq_path)
-{
-	struct sii_data *d;
-
-	CHECK_ALLOCATION(d = (struct sii_data *) malloc(sizeof(struct sii_data)));
-	memset(d, 0, sizeof(struct sii_data));
-
-	INTERRUPT_CONNECT(irq_path, d->irq);
-	d->buf_start = buf_start;
-	d->buf_end   = buf_end;
-	d->regs      = (uint16_t *) &d->siiregs;
-
-	memory_device_register(mem, "sii", baseaddr, DEV_SII_LENGTH,
-	    dev_sii_access, (void *)d, DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(machine, dev_sii_tick, d,
-	    SII_TICK_SHIFT);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_sn.c gxemul-0.7.0+dfsg/src/devices/dev_sn.c
--- gxemul-0.6.2/src/devices/dev_sn.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sn.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,123 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: National Semiconductor SONIC ("sn") DP83932 ethernet controller
+ *
+ *  TODO
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "net.h"
+
+#include "thirdparty/dp83932reg.h"
+
+
+#define	DEV_SN_LENGTH		0x1000
+
+struct sn_data {
+	struct nic_data	nic;
+	struct interrupt irq;
+	uint32_t	reg[SONIC_NREGS];
+};
+
+
+DEVICE_ACCESS(sn)
+{
+	struct sn_data *d = (struct sn_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int regnr;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	regnr = relative_addr / sizeof(uint32_t);
+
+	if (regnr < SONIC_NREGS) {
+		if (writeflag == MEM_WRITE)
+			d->reg[regnr] = idata;
+		else
+			odata = d->reg[regnr];
+	}
+
+	switch (regnr) {
+
+	default:
+		if (writeflag == MEM_WRITE) {
+			fatal("[ sn: unimplemented write to address 0x%x"
+			    " (regnr %i), data=0x%02x ]\n",
+			    (int)relative_addr, regnr, (int)idata);
+		} else {
+			fatal("[ sn: unimplemented read from address 0x%x "
+			    "(regnr %i) ]\n", (int)relative_addr, regnr);
+		}
+		/*  exit(1);  */
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(sn)
+{
+	char *name2;
+	size_t nlen = 55;
+	struct sn_data *d;
+
+	CHECK_ALLOCATION(d = (struct sn_data *) malloc(sizeof(struct sn_data)));
+	memset(d, 0, sizeof(struct sn_data));
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	net_generate_unique_mac(devinit->machine, d->nic.mac_address);
+
+	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
+	snprintf(name2, nlen, "%s [%02x:%02x:%02x:%02x:%02x:%02x]",
+	    devinit->name, d->nic.mac_address[0], d->nic.mac_address[1],
+	    d->nic.mac_address[2], d->nic.mac_address[3],
+	    d->nic.mac_address[4], d->nic.mac_address[5]);
+
+	memory_device_register(devinit->machine->memory, name2,
+	    devinit->addr, DEV_SN_LENGTH,
+	    dev_sn_access, (void *)d, DM_DEFAULT, NULL);
+
+	net_add_nic(devinit->machine->emul->net, &d->nic);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_sn.cc gxemul-0.7.0+dfsg/src/devices/dev_sn.cc
--- gxemul-0.6.2/src/devices/dev_sn.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_sn.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,122 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: National Semiconductor SONIC ("sn") DP83932 ethernet controller
- *
- *  TODO
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "net.h"
-
-#include "thirdparty/dp83932reg.h"
-
-
-#define	DEV_SN_LENGTH		0x1000
-
-struct sn_data {
-	struct interrupt irq;
-	unsigned char	macaddr[6];
-	uint32_t	reg[SONIC_NREGS];
-};
-
-
-DEVICE_ACCESS(sn)
-{
-	struct sn_data *d = (struct sn_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	regnr = relative_addr / sizeof(uint32_t);
-
-	if (regnr < SONIC_NREGS) {
-		if (writeflag == MEM_WRITE)
-			d->reg[regnr] = idata;
-		else
-			odata = d->reg[regnr];
-	}
-
-	switch (regnr) {
-
-	default:
-		if (writeflag == MEM_WRITE) {
-			fatal("[ sn: unimplemented write to address 0x%x"
-			    " (regnr %i), data=0x%02x ]\n",
-			    (int)relative_addr, regnr, (int)idata);
-		} else {
-			fatal("[ sn: unimplemented read from address 0x%x "
-			    "(regnr %i) ]\n", (int)relative_addr, regnr);
-		}
-		/*  exit(1);  */
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(sn)
-{
-	char *name2;
-	size_t nlen = 55;
-	struct sn_data *d;
-
-	CHECK_ALLOCATION(d = (struct sn_data *) malloc(sizeof(struct sn_data)));
-	memset(d, 0, sizeof(struct sn_data));
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	net_generate_unique_mac(devinit->machine, d->macaddr);
-
-	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
-	snprintf(name2, nlen, "%s [%02x:%02x:%02x:%02x:%02x:%02x]",
-	    devinit->name, d->macaddr[0], d->macaddr[1], d->macaddr[2],
-	    d->macaddr[3], d->macaddr[4], d->macaddr[5]);
-
-	memory_device_register(devinit->machine->memory, name2,
-	    devinit->addr, DEV_SN_LENGTH,
-	    dev_sn_access, (void *)d, DM_DEFAULT, NULL);
-
-	net_add_nic(devinit->machine->emul->net, d, d->macaddr);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_ssc.c gxemul-0.7.0+dfsg/src/devices/dev_ssc.c
--- gxemul-0.6.2/src/devices/dev_ssc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ssc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,243 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: System Support Chip serial controller
+ *
+ *  Serial controller on DECsystem 5400 and 5800.
+ *  Known as System Support Chip on VAX 3600 (KA650).
+ *
+ *  Described around page 80 in the kn210tm1.pdf.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+#define	RX_INT_ENABLE	0x40
+#define	RX_AVAIL	0x80
+#define	TX_INT_ENABLE	0x40
+#define	TX_READY	0x80
+
+#define	SSC_TICK_SHIFT	14
+
+/*
+ *  _TXRX is for debugging putchar/getchar. The other
+ *  one is more general.
+ */
+/*  #define SSC_DEBUG_TXRX  */
+#define SSC_DEBUG
+
+struct ssc_data {
+	int		console_handle;
+	int		use_fb;
+
+	int		rx_ctl;
+	int		tx_ctl;
+
+	struct interrupt irq;
+};
+
+
+DEVICE_TICK(ssc)
+{
+	struct ssc_data *d = (struct ssc_data *) extra;
+
+	d->tx_ctl |= TX_READY;	/*  transmitter always ready  */
+
+	d->rx_ctl &= ~RX_AVAIL;
+	if (console_charavail(d->console_handle))
+		d->rx_ctl |= RX_AVAIL;
+
+	/*  rx interrupts enabled, and char avail?  */
+	if (d->rx_ctl & RX_INT_ENABLE && d->rx_ctl & RX_AVAIL) {
+		/*  TODO:  This is for 5800 only!  */
+		unsigned char txvector = 0xf8;
+		cpu->memory_rw(cpu, cpu->mem, 0x40000050, &txvector,
+		    1, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
+		INTERRUPT_ASSERT(d->irq);
+	}
+
+	/*  tx interrupts enabled?  */
+	if (d->tx_ctl & TX_INT_ENABLE) {
+		/*  TODO:  This is for 5800 only!  */
+		unsigned char txvector = 0xfc;
+		cpu->memory_rw(cpu, cpu->mem, 0x40000050, &txvector,
+		    1, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
+		INTERRUPT_ASSERT(d->irq);
+	}
+}
+
+
+DEVICE_ACCESS(ssc)
+{
+	uint64_t idata = 0, odata = 0;
+	struct ssc_data *d = (struct ssc_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	dev_ssc_tick(cpu, extra);
+
+	switch (relative_addr) {
+	case 0x0080:	/*  receive status  */
+		if (writeflag==MEM_READ) {
+			odata = d->rx_ctl;
+#ifdef SSC_DEBUG_TXRX
+			debug("[ ssc: read from 0x%08lx: 0x%02x ]\n",
+			    (long)relative_addr, (int)odata);
+#endif
+		} else {
+			d->rx_ctl = idata;
+
+			INTERRUPT_DEASSERT(d->irq);
+
+#ifdef SSC_DEBUG_TXRX
+			debug("[ ssc: write to  0x%08lx: 0x%02x ]\n",
+			    (long)relative_addr, (int)idata);
+#endif
+		}
+
+		break;
+	case 0x0084:	/*  receive data  */
+		if (writeflag==MEM_READ) {
+#ifdef SSC_DEBUG_TXRX
+			debug("[ ssc: read from 0x%08lx ]\n",
+			    (long)relative_addr);
+#endif
+			if (console_charavail(d->console_handle))
+				odata = console_readchar(d->console_handle);
+		} else {
+#ifdef SSC_DEBUG_TXRX
+			debug("[ ssc: write to 0x%08lx: 0x%02x ]\n",
+			    (long)relative_addr, (int)idata);
+#endif
+		}
+
+		break;
+	case 0x0088:	/*  transmit status  */
+		if (writeflag==MEM_READ) {
+			odata = d->tx_ctl;
+#ifdef SSC_DEBUG_TXRX
+			debug("[ ssc: read from 0x%08lx: 0x%04x ]\n",
+			    (long)relative_addr, (int)odata);
+#endif
+		} else {
+			d->tx_ctl = idata;
+
+			INTERRUPT_DEASSERT(d->irq);
+
+#ifdef SSC_DEBUG_TXRX
+			debug("[ ssc: write to  0x%08lx: 0x%02x ]\n",
+			    (long)relative_addr, (int)idata);
+#endif
+		}
+
+		break;
+	case 0x008c:	/*  transmit data  */
+		if (writeflag==MEM_READ) {
+			debug("[ ssc: read from 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			/*  debug("[ ssc: write to 0x%08lx: 0x%02x ]\n",
+			    (long)relative_addr, (int)idata);  */
+			console_putchar(d->console_handle, idata);
+		}
+
+		break;
+	case 0x0100:
+		if (writeflag==MEM_READ) {
+			odata = 128;
+#ifdef SSC_DEBUG_TXRX
+			debug("[ ssc: read from 0x%08lx: 0x%08lx ]\n",
+			    (long)relative_addr, (long)odata);
+#endif
+		} else {
+#ifdef SSC_DEBUG_TXRX
+			debug("[ ssc: write to  0x%08lx: 0x%08x ]\n",
+			    (long)relative_addr, idata);
+#endif
+		}
+
+		break;
+	case 0x0108:
+		if (writeflag==MEM_READ) {
+			debug("[ ssc: read from 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+#ifdef SSC_DEBUG
+			debug("[ ssc: write to  0x%08lx: 0x%08x ]\n",
+			    (long)relative_addr, (int)idata);
+#endif
+		}
+
+		break;
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ ssc: read from 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			debug("[ ssc: write to  0x%08lx: 0x%08x ]\n",
+			    (long)relative_addr, (int)idata);
+		}
+	}
+
+	dev_ssc_tick(cpu, extra);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+void dev_ssc_init(struct machine *machine, struct memory *mem,
+	uint64_t baseaddr, const char *irq_path, int use_fb)
+{
+	struct ssc_data *d;
+
+	CHECK_ALLOCATION(d = (struct ssc_data *) malloc(sizeof(struct ssc_data)));
+	memset(d, 0, sizeof(struct ssc_data));
+
+	d->use_fb = use_fb;
+	d->console_handle = console_start_slave(machine, "SSC", 1);
+
+	INTERRUPT_CONNECT(irq_path, d->irq);
+
+	memory_device_register(mem, "ssc", baseaddr, DEV_SSC_LENGTH,
+	    dev_ssc_access, d, DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(machine, dev_ssc_tick, d, SSC_TICK_SHIFT);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_ssc.cc gxemul-0.7.0+dfsg/src/devices/dev_ssc.cc
--- gxemul-0.6.2/src/devices/dev_ssc.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_ssc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,243 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: System Support Chip serial controller
- *
- *  Serial controller on DECsystem 5400 and 5800.
- *  Known as System Support Chip on VAX 3600 (KA650).
- *
- *  Described around page 80 in the kn210tm1.pdf.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-#define	RX_INT_ENABLE	0x40
-#define	RX_AVAIL	0x80
-#define	TX_INT_ENABLE	0x40
-#define	TX_READY	0x80
-
-#define	SSC_TICK_SHIFT	14
-
-/*
- *  _TXRX is for debugging putchar/getchar. The other
- *  one is more general.
- */
-/*  #define SSC_DEBUG_TXRX  */
-#define SSC_DEBUG
-
-struct ssc_data {
-	int		console_handle;
-	int		use_fb;
-
-	int		rx_ctl;
-	int		tx_ctl;
-
-	struct interrupt irq;
-};
-
-
-DEVICE_TICK(ssc)
-{
-	struct ssc_data *d = (struct ssc_data *) extra;
-
-	d->tx_ctl |= TX_READY;	/*  transmitter always ready  */
-
-	d->rx_ctl &= ~RX_AVAIL;
-	if (console_charavail(d->console_handle))
-		d->rx_ctl |= RX_AVAIL;
-
-	/*  rx interrupts enabled, and char avail?  */
-	if (d->rx_ctl & RX_INT_ENABLE && d->rx_ctl & RX_AVAIL) {
-		/*  TODO:  This is for 5800 only!  */
-		unsigned char txvector = 0xf8;
-		cpu->memory_rw(cpu, cpu->mem, 0x40000050, &txvector,
-		    1, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
-		INTERRUPT_ASSERT(d->irq);
-	}
-
-	/*  tx interrupts enabled?  */
-	if (d->tx_ctl & TX_INT_ENABLE) {
-		/*  TODO:  This is for 5800 only!  */
-		unsigned char txvector = 0xfc;
-		cpu->memory_rw(cpu, cpu->mem, 0x40000050, &txvector,
-		    1, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
-		INTERRUPT_ASSERT(d->irq);
-	}
-}
-
-
-DEVICE_ACCESS(ssc)
-{
-	uint64_t idata = 0, odata = 0;
-	struct ssc_data *d = (struct ssc_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	dev_ssc_tick(cpu, extra);
-
-	switch (relative_addr) {
-	case 0x0080:	/*  receive status  */
-		if (writeflag==MEM_READ) {
-			odata = d->rx_ctl;
-#ifdef SSC_DEBUG_TXRX
-			debug("[ ssc: read from 0x%08lx: 0x%02x ]\n",
-			    (long)relative_addr, (int)odata);
-#endif
-		} else {
-			d->rx_ctl = idata;
-
-			INTERRUPT_DEASSERT(d->irq);
-
-#ifdef SSC_DEBUG_TXRX
-			debug("[ ssc: write to  0x%08lx: 0x%02x ]\n",
-			    (long)relative_addr, (int)idata);
-#endif
-		}
-
-		break;
-	case 0x0084:	/*  receive data  */
-		if (writeflag==MEM_READ) {
-#ifdef SSC_DEBUG_TXRX
-			debug("[ ssc: read from 0x%08lx ]\n",
-			    (long)relative_addr);
-#endif
-			if (console_charavail(d->console_handle))
-				odata = console_readchar(d->console_handle);
-		} else {
-#ifdef SSC_DEBUG_TXRX
-			debug("[ ssc: write to 0x%08lx: 0x%02x ]\n",
-			    (long)relative_addr, (int)idata);
-#endif
-		}
-
-		break;
-	case 0x0088:	/*  transmit status  */
-		if (writeflag==MEM_READ) {
-			odata = d->tx_ctl;
-#ifdef SSC_DEBUG_TXRX
-			debug("[ ssc: read from 0x%08lx: 0x%04x ]\n",
-			    (long)relative_addr, (int)odata);
-#endif
-		} else {
-			d->tx_ctl = idata;
-
-			INTERRUPT_DEASSERT(d->irq);
-
-#ifdef SSC_DEBUG_TXRX
-			debug("[ ssc: write to  0x%08lx: 0x%02x ]\n",
-			    (long)relative_addr, (int)idata);
-#endif
-		}
-
-		break;
-	case 0x008c:	/*  transmit data  */
-		if (writeflag==MEM_READ) {
-			debug("[ ssc: read from 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			/*  debug("[ ssc: write to 0x%08lx: 0x%02x ]\n",
-			    (long)relative_addr, (int)idata);  */
-			console_putchar(d->console_handle, idata);
-		}
-
-		break;
-	case 0x0100:
-		if (writeflag==MEM_READ) {
-			odata = 128;
-#ifdef SSC_DEBUG_TXRX
-			debug("[ ssc: read from 0x%08lx: 0x%08lx ]\n",
-			    (long)relative_addr, (long)odata);
-#endif
-		} else {
-#ifdef SSC_DEBUG_TXRX
-			debug("[ ssc: write to  0x%08lx: 0x%08x ]\n",
-			    (long)relative_addr, idata);
-#endif
-		}
-
-		break;
-	case 0x0108:
-		if (writeflag==MEM_READ) {
-			debug("[ ssc: read from 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-#ifdef SSC_DEBUG
-			debug("[ ssc: write to  0x%08lx: 0x%08x ]\n",
-			    (long)relative_addr, (int)idata);
-#endif
-		}
-
-		break;
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ ssc: read from 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			debug("[ ssc: write to  0x%08lx: 0x%08x ]\n",
-			    (long)relative_addr, (int)idata);
-		}
-	}
-
-	dev_ssc_tick(cpu, extra);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-void dev_ssc_init(struct machine *machine, struct memory *mem,
-	uint64_t baseaddr, const char *irq_path, int use_fb)
-{
-	struct ssc_data *d;
-
-	CHECK_ALLOCATION(d = (struct ssc_data *) malloc(sizeof(struct ssc_data)));
-	memset(d, 0, sizeof(struct ssc_data));
-
-	d->use_fb = use_fb;
-	d->console_handle = console_start_slave(machine, "SSC", 1);
-
-	INTERRUPT_CONNECT(irq_path, d->irq);
-
-	memory_device_register(mem, "ssc", baseaddr, DEV_SSC_LENGTH,
-	    dev_ssc_access, d, DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(machine, dev_ssc_tick, d, SSC_TICK_SHIFT);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_turbochannel.c gxemul-0.7.0+dfsg/src/devices/dev_turbochannel.c
--- gxemul-0.6.2/src/devices/dev_turbochannel.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_turbochannel.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,328 @@
+/*
+ *  Copyright (C) 2003-2020  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: TURBOchannel bus framework, used in DECstation machines
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/sfbreg.h"
+
+
+#define	DEVICE_MAX_NAMELEN		9
+#define	CARD_NAME_BUFLEN		9
+#define	CARD_FIRMWARE_BUFLEN		5
+
+struct turbochannel_data {
+	int		slot_nr;
+	uint64_t	baseaddr;
+	uint64_t	endaddr;
+
+	int		rom_skip;
+
+	char		device_name[DEVICE_MAX_NAMELEN];  /*  NUL-terminated  */
+
+	/*  These should be terminated with spaces  */
+	char		card_firmware_version[CARD_NAME_BUFLEN];
+	char		card_vendor_name[CARD_NAME_BUFLEN];
+	char		card_module_name[CARD_NAME_BUFLEN];
+	char		card_firmware_type[CARD_FIRMWARE_BUFLEN];
+};
+
+
+DEVICE_ACCESS(turbochannel)
+{
+	struct turbochannel_data *d = (struct turbochannel_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	relative_addr += d->rom_skip;
+
+	if (writeflag == MEM_READ) {
+		debug("[ turbochannel: read from slot %i addr 0x%08lx (",
+		    d->slot_nr, (long)relative_addr);
+
+		relative_addr &= 0x7fff;
+
+		switch (relative_addr) {
+		case 0x3e0:
+			odata = 0x00000001; debug("ROM width");
+			break;
+		case 0x3e4:
+			odata = 0x00000004; debug("ROM stride");
+			break;
+		case 0x3e8:
+			/*  8KB * romsize  */
+			odata = 0x00000001; debug("ROM size");
+			break;
+		case 0x3ec:
+			/*  4MB * slotsize  */
+			odata = 0x00000001; debug("slot size");
+			break;
+		case 0x3f0:
+			odata = 0x55555555; debug("ROM signature byte 0");
+			break;
+		case 0x3f4:
+			odata = 0x00000000; debug("ROM signature byte 1");
+			break;
+		case 0x3f8:
+			odata = 0xaaaaaaaa; debug("ROM signature byte 2");
+			break;
+		case 0x3fc:
+			odata = 0xffffffff; debug("ROM signature byte 3");
+			break;
+		case 0x470:
+			/*  0=nothing, 1=parity  */
+			odata = 0x00000000; debug("flags"); break;
+		default:
+			if (relative_addr >= 0x400 && relative_addr < 0x420)
+				odata = d->card_firmware_version[
+				    (relative_addr-0x400)/4];
+			else if (relative_addr >= 0x420 &&
+			    relative_addr < 0x440)
+				odata = d->card_vendor_name[
+				    (relative_addr-0x420)/4];
+			else if (relative_addr >= 0x440 &&
+			    relative_addr < 0x460)
+				odata = d->card_module_name[
+				    (relative_addr-0x440)/4];
+			else if (relative_addr >= 0x460 &&
+			    relative_addr < 0x470)
+				odata = d->card_firmware_type[
+				    (relative_addr-0x460)/4];
+			else {
+				debug("?");
+			}
+		}
+
+		/*
+		 *  If this slot is empty, return an error so that a DBE
+		 *  exception is caused. (This is the way DECstation operating
+		 *  systems have to detect the absence of cards in a
+		 *  TURBOchannel slot.)
+		 *
+		 *  NOTE:  The Sprite kernel reads from offsets 0x3e0..0x400
+		 *  without handling the DBE exception, and both Ultrix and
+		 *  NetBSD seem to detect the DBE exception using addresses
+		 *  around offset 0x0 or 0x3c0000.  This code seems to work
+		 *  with all of the those OS kernels:
+		 */
+		if (d->card_module_name[0] ==  ' ') {
+			/*  Return no data for empty slot:  */
+			odata = 0;
+
+			/*  Return DBE exception in some cases:  */
+			if (relative_addr < 0x3e0 || relative_addr >= 0x500)
+				return 0;
+		}
+
+		debug(") ]\n");
+	} else {
+		debug("[ turbochannel: write to  0x%08lx: 0x%08x ]\n",
+		    (long)relative_addr, (int)idata);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_turbochannel_init():
+ *
+ *  This is a generic turbochannel card device.  device_name should point
+ *  to a string such as "PMAG-BA".
+ *
+ *  TODO: When running for example dual-head, maybe the name of each
+ *        framebuffer should include the card slot number?
+ */
+void dev_turbochannel_init(struct machine *machine, struct memory *mem,
+	int slot_nr, uint64_t baseaddr, uint64_t endaddr,
+	const char *device_name, const char *irq_path)
+{
+	struct vfb_data *fb;
+	struct turbochannel_data *d;
+	int rom_offset=0x3c0000, rom_length=DEV_TURBOCHANNEL_LEN, rom_skip=0;
+	char *name2;
+	size_t nlen;
+
+	if (device_name == NULL)
+		return;
+
+	if (strlen(device_name) > 8) {
+		fprintf(stderr, "dev_turbochannel_init(): bad device_name\n");
+		exit(1);
+	}
+
+	CHECK_ALLOCATION(d = (struct turbochannel_data *) malloc(sizeof(struct turbochannel_data)));
+	memset(d, 0, sizeof(struct turbochannel_data));
+
+	d->slot_nr  = slot_nr;
+	d->baseaddr = baseaddr;
+	d->endaddr  = endaddr;
+
+	strlcpy(d->device_name, device_name, DEVICE_MAX_NAMELEN);
+
+	strncpy(d->card_firmware_version, "V5.3a   ", CARD_NAME_BUFLEN);
+	strncpy(d->card_vendor_name,      "DEC     ", CARD_NAME_BUFLEN);
+	strncpy(d->card_firmware_type,    "TCF0", CARD_FIRMWARE_BUFLEN);
+
+	memset(d->card_module_name, ' ', 8);
+	memcpy(d->card_module_name, device_name, strlen(device_name));
+
+	/*
+	 *  According to NetBSD/pmax:
+	 *
+	 *  PMAD-AA:  le1 at tc0 slot 2 offset 0x0: address 00:00:00:00:00:00
+	 *  PMAG-AA:  mfb0 at tc0 slot 2 offset 0x0: 1280x1024x8
+	 *  PMAG-BA:  cfb0 at tc0 slot 2 offset 0x0cfb0: 1024x864x8
+	 *  PMAG-CA:  px0 at tc0 slot 2 offset 0x0: 2D, 4x1 stamp, 8 plane
+	 *	(PMAG-DA,EA,FA,FB are also pixelstamps)
+	 *  PMAG-DV:  xcfb0 at tc0 slot 2 offset 0x0: 1024x768x8
+	 *  PMAG-JA:  "truecolor" in Ultrix
+	 *  PMAGB-BA: sfb0 at tc0 slot 0 offset 0x0: 0x0x8
+	 *  PMAGB-VA: sfb0 at tc0 slot 2 offset 0x0: 0x0x8
+	 *  PMAZ-AA:  asc0 at tc0 slot 2 offset 0x0: NCR53C94, 25MHz, SCSI ID 7
+	 *
+	 *  PMAF-FA:  fta0 at tc0 slot 0  (fddi network, "DEC", "V1.0b")
+	 */
+
+	if (strcmp(device_name, "PMAD-AA")==0) {
+		/*  le in NetBSD, Lance ethernet  */
+		dev_le_init(machine, mem, baseaddr, 0, 0,
+		    irq_path, DEV_LE_LENGTH);
+		/*  One ROM at 0x1c03e0, and one at 0x3c0000.  */
+		rom_skip = 0x300;
+		rom_offset = 0x1c0000;
+		rom_length = 0x201000;
+	} else if (strcmp(device_name, "PMAZ-AA")==0) {
+		/*  asc in NetBSD, SCSI  */
+		dev_asc_init(machine, mem, baseaddr, irq_path, d,
+		    DEV_ASC_DEC, NULL, NULL);
+		rom_offset = 0xc0000;
+		/*  There is a copy at 0x0, at least that's where Linux
+		    looks for the rom signature  */
+	} else if (strcmp(device_name, "PMAG-AA")==0) {
+		/*  mfb in NetBSD  */
+		fb = dev_fb_init(machine, mem, baseaddr + VFB_MFB_VRAM,
+		    VFB_GENERIC, 1280, 1024, 2048, 1024, 8, device_name);
+		/*  bt455 = palette, bt431 = cursor  */
+		dev_bt455_init(mem, baseaddr + VFB_MFB_BT455, fb);
+		dev_bt431_init(mem, baseaddr + VFB_MFB_BT431, fb, 8);
+		rom_offset = 0;
+	} else if (strcmp(device_name, "PMAG-BA")==0) {
+		/*  cfb in NetBSD  */
+		fb = dev_fb_init(machine, mem, baseaddr, VFB_GENERIC,
+		    1024,864, 1024,1024,8, device_name);
+		dev_bt459_init(machine, mem, baseaddr + VFB_CFB_BT459,
+		    baseaddr + 0x300000, fb, 8, irq_path, BT459_BA);
+		/*  ROM at both 0x380000 and 0x3c0000?  */
+		rom_offset = 0x380000;
+		rom_length = 0x080000;
+	} else if (strcmp(device_name, "PMAGB-BA")==0) {
+		/*  sfb in NetBSD  */
+		/*  TODO: This is not working with Ultrix yet.  */
+		fb = dev_fb_init(machine, mem, baseaddr + SFB_OFFSET_VRAM,
+		    VFB_GENERIC, 1280,1024, 1280,1024,8, device_name);
+		dev_sfb_init(machine, mem, baseaddr + SFB_ASIC_OFFSET, fb);
+		/*  TODO: the CLEAR doesn't get through, as the address
+			range is already in use by the asic  */
+		dev_bt459_init(machine, mem, baseaddr + SFB_OFFSET_BT459,
+		    baseaddr + SFB_CLEAR, fb, 8, irq_path, BT459_BBA);
+		rom_offset = 0x0;	/*  ? TODO  */
+	} else if (strcmp(device_name, "PMAG-CA")==0) {
+		/*  px in NetBSD  */
+		dev_px_init(machine, mem, baseaddr, DEV_PX_TYPE_PX, irq_path);
+		rom_offset = 0x3c0000;
+	} else if (strcmp(device_name, "PMAG-DA")==0) {
+		/*  pxg in NetBSD  */
+		dev_px_init(machine, mem, baseaddr, DEV_PX_TYPE_PXG, irq_path);
+		rom_offset = 0x3c0000;
+	} else if (strcmp(device_name, "PMAG-EA")==0) {
+		/*  pxg+ in NetBSD: TODO  (not supported by the kernel
+		    I've tried)  */
+		fatal("TODO (see dev_turbochannel.c)\n");
+		rom_offset = 0x3c0000;
+	} else if (strcmp(device_name, "PMAG-FA")==0) {
+		/*  "pxg+ Turbo" in NetBSD  */
+		dev_px_init(machine, mem, baseaddr,
+		    DEV_PX_TYPE_PXGPLUSTURBO, irq_path);
+		rom_offset = 0x3c0000;
+	} else if (strcmp(device_name, "PMAG-DV")==0) {
+		/*  xcfb in NetBSD: TODO  */
+		fb = dev_fb_init(machine, mem, baseaddr + 0x2000000,
+		    VFB_DEC_MAXINE, 0, 0, 0, 0, 0, "PMAG-DV");
+		/*  TODO:  not yet usable, needs a IMS332 vdac  */
+		rom_offset = 0x3c0000;
+	} else if (strcmp(device_name, "PMAG-JA")==0) {
+		/*  "Truecolor", mixed 8- and 24-bit  */
+		dev_pmagja_init(machine, mem, baseaddr, irq_path);
+		rom_offset = 0;		/*  NOTE: 0, not 0x3c0000  */
+	} else if (strcmp(device_name, "PMAG-RO")==0) {
+		/*  This works at least B/W in Ultrix, so far.  */
+		fb = dev_fb_init(machine, mem, baseaddr + 0x200000,
+		    VFB_GENERIC, 1280,1024, 1280,1024, 8, "PMAG-RO");
+		/*  TODO: bt463 at offset 0x040000, not bt459  */
+		dev_bt459_init(machine, mem, baseaddr + 0x40000, 0,
+		    fb, 8, irq_path, 0);		/*  TODO: type  */
+		dev_bt431_init(mem, baseaddr + 0x40010, fb, 8);  /*  cursor  */
+		rom_offset = 0x3c0000;
+	} else if (device_name[0] == '\0') {
+		/*  If this slot is empty, then occupy the entire
+		    4MB slot address range:  */
+		rom_offset = 0;
+		rom_length = 4*1048576;
+	} else {
+		fatal("warning: unknown TURBOchannel device name \"%s\"\n",
+		    device_name);
+	}
+
+	d->rom_skip = rom_skip;
+
+	nlen = strlen(device_name) + 30;
+	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
+
+	if (*device_name)
+		snprintf(name2, nlen, "turbochannel [%s]", device_name);
+	else
+		snprintf(name2, nlen, "turbochannel");
+
+	memory_device_register(mem, name2, baseaddr + rom_offset + rom_skip,
+	    rom_length-rom_skip, dev_turbochannel_access, d, DM_DEFAULT, NULL);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_turbochannel.cc gxemul-0.7.0+dfsg/src/devices/dev_turbochannel.cc
--- gxemul-0.6.2/src/devices/dev_turbochannel.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_turbochannel.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,328 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: TURBOchannel bus framework, used in DECstation machines
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/sfbreg.h"
-
-
-#define	DEVICE_MAX_NAMELEN		9
-#define	CARD_NAME_BUFLEN		9
-#define	CARD_FIRMWARE_BUFLEN		5
-
-struct turbochannel_data {
-	int		slot_nr;
-	uint64_t	baseaddr;
-	uint64_t	endaddr;
-
-	int		rom_skip;
-
-	char		device_name[DEVICE_MAX_NAMELEN];  /*  NUL-terminated  */
-
-	/*  These should be terminated with spaces  */
-	char		card_firmware_version[CARD_NAME_BUFLEN];
-	char		card_vendor_name[CARD_NAME_BUFLEN];
-	char		card_module_name[CARD_NAME_BUFLEN];
-	char		card_firmware_type[CARD_FIRMWARE_BUFLEN];
-};
-
-
-DEVICE_ACCESS(turbochannel)
-{
-	struct turbochannel_data *d = (struct turbochannel_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	relative_addr += d->rom_skip;
-
-	if (writeflag == MEM_READ) {
-		debug("[ turbochannel: read from slot %i addr 0x%08lx (",
-		    d->slot_nr, (long)relative_addr);
-
-		relative_addr &= 0x7fff;
-
-		switch (relative_addr) {
-		case 0x3e0:
-			odata = 0x00000001; debug("ROM width");
-			break;
-		case 0x3e4:
-			odata = 0x00000004; debug("ROM stride");
-			break;
-		case 0x3e8:
-			/*  8KB * romsize  */
-			odata = 0x00000001; debug("ROM size");
-			break;
-		case 0x3ec:
-			/*  4MB * slotsize  */
-			odata = 0x00000001; debug("slot size");
-			break;
-		case 0x3f0:
-			odata = 0x55555555; debug("ROM signature byte 0");
-			break;
-		case 0x3f4:
-			odata = 0x00000000; debug("ROM signature byte 1");
-			break;
-		case 0x3f8:
-			odata = 0xaaaaaaaa; debug("ROM signature byte 2");
-			break;
-		case 0x3fc:
-			odata = 0xffffffff; debug("ROM signature byte 3");
-			break;
-		case 0x470:
-			/*  0=nothing, 1=parity  */
-			odata = 0x00000000; debug("flags"); break;
-		default:
-			if (relative_addr >= 0x400 && relative_addr < 0x420)
-				odata = d->card_firmware_version[
-				    (relative_addr-0x400)/4];
-			else if (relative_addr >= 0x420 &&
-			    relative_addr < 0x440)
-				odata = d->card_vendor_name[
-				    (relative_addr-0x420)/4];
-			else if (relative_addr >= 0x440 &&
-			    relative_addr < 0x460)
-				odata = d->card_module_name[
-				    (relative_addr-0x440)/4];
-			else if (relative_addr >= 0x460 &&
-			    relative_addr < 0x470)
-				odata = d->card_firmware_type[
-				    (relative_addr-0x460)/4];
-			else {
-				debug("?");
-			}
-		}
-
-		/*
-		 *  If this slot is empty, return an error so that a DBE
-		 *  exception is caused. (This is the way DECstation operating
-		 *  systems have to detect the absence of cards in a
-		 *  TURBOchannel slot.)
-		 *
-		 *  NOTE:  The Sprite kernel reads from offsets 0x3e0..0x400
-		 *  without handling the DBE exception, and both Ultrix and
-		 *  NetBSD seem to detect the DBE exception using addresses
-		 *  around offset 0x0 or 0x3c0000.  This code seems to work
-		 *  with all of the those OS kernels:
-		 */
-		if (d->card_module_name[0] ==  ' ') {
-			/*  Return no data for empty slot:  */
-			odata = 0;
-
-			/*  Return DBE exception in some cases:  */
-			if (relative_addr < 0x3e0 || relative_addr >= 0x500)
-				return 0;
-		}
-
-		debug(") ]\n");
-	} else {
-		/*  debug("[ turbochannel: write to  0x%08lx: 0x%08x ]\n",
-		    (long)relative_addr, (int)idata);  */
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_turbochannel_init():
- *
- *  This is a generic turbochannel card device.  device_name should point
- *  to a string such as "PMAG-BA".
- *
- *  TODO: When running for example dual-head, maybe the name of each
- *        framebuffer should include the card slot number?
- */
-void dev_turbochannel_init(struct machine *machine, struct memory *mem,
-	int slot_nr, uint64_t baseaddr, uint64_t endaddr,
-	const char *device_name, const char *irq_path)
-{
-	struct vfb_data *fb;
-	struct turbochannel_data *d;
-	int rom_offset=0x3c0000, rom_length=DEV_TURBOCHANNEL_LEN, rom_skip=0;
-	char *name2;
-	size_t nlen;
-
-	if (device_name == NULL)
-		return;
-
-	if (strlen(device_name) > 8) {
-		fprintf(stderr, "dev_turbochannel_init(): bad device_name\n");
-		exit(1);
-	}
-
-	CHECK_ALLOCATION(d = (struct turbochannel_data *) malloc(sizeof(struct turbochannel_data)));
-	memset(d, 0, sizeof(struct turbochannel_data));
-
-	d->slot_nr  = slot_nr;
-	d->baseaddr = baseaddr;
-	d->endaddr  = endaddr;
-
-	strlcpy(d->device_name, device_name, DEVICE_MAX_NAMELEN);
-
-	strncpy(d->card_firmware_version, "V5.3a   ", CARD_NAME_BUFLEN);
-	strncpy(d->card_vendor_name,      "DEC     ", CARD_NAME_BUFLEN);
-	strncpy(d->card_firmware_type,    "TCF0", CARD_FIRMWARE_BUFLEN);
-
-	memset(d->card_module_name, ' ', 8);
-	memcpy(d->card_module_name, device_name, strlen(device_name));
-
-	/*
-	 *  According to NetBSD/pmax:
-	 *
-	 *  PMAD-AA:  le1 at tc0 slot 2 offset 0x0: address 00:00:00:00:00:00
-	 *  PMAG-AA:  mfb0 at tc0 slot 2 offset 0x0: 1280x1024x8
-	 *  PMAG-BA:  cfb0 at tc0 slot 2 offset 0x0cfb0: 1024x864x8
-	 *  PMAG-CA:  px0 at tc0 slot 2 offset 0x0: 2D, 4x1 stamp, 8 plane
-	 *	(PMAG-DA,EA,FA,FB are also pixelstamps)
-	 *  PMAG-DV:  xcfb0 at tc0 slot 2 offset 0x0: 1024x768x8
-	 *  PMAG-JA:  "truecolor" in Ultrix
-	 *  PMAGB-BA: sfb0 at tc0 slot 0 offset 0x0: 0x0x8
-	 *  PMAGB-VA: sfb0 at tc0 slot 2 offset 0x0: 0x0x8
-	 *  PMAZ-AA:  asc0 at tc0 slot 2 offset 0x0: NCR53C94, 25MHz, SCSI ID 7
-	 *
-	 *  PMAF-FA:  fta0 at tc0 slot 0  (fddi network, "DEC", "V1.0b")
-	 */
-
-	if (strcmp(device_name, "PMAD-AA")==0) {
-		/*  le in NetBSD, Lance ethernet  */
-		dev_le_init(machine, mem, baseaddr, 0, 0,
-		    irq_path, DEV_LE_LENGTH);
-		/*  One ROM at 0x1c03e0, and one at 0x3c0000.  */
-		rom_skip = 0x300;
-		rom_offset = 0x1c0000;
-		rom_length = 0x201000;
-	} else if (strcmp(device_name, "PMAZ-AA")==0) {
-		/*  asc in NetBSD, SCSI  */
-		dev_asc_init(machine, mem, baseaddr, irq_path, d,
-		    DEV_ASC_DEC, NULL, NULL);
-		rom_offset = 0xc0000;
-		/*  There is a copy at 0x0, at least that's where Linux
-		    looks for the rom signature  */
-	} else if (strcmp(device_name, "PMAG-AA")==0) {
-		/*  mfb in NetBSD  */
-		fb = dev_fb_init(machine, mem, baseaddr + VFB_MFB_VRAM,
-		    VFB_GENERIC, 1280, 1024, 2048, 1024, 8, device_name);
-		/*  bt455 = palette, bt431 = cursor  */
-		dev_bt455_init(mem, baseaddr + VFB_MFB_BT455, fb);
-		dev_bt431_init(mem, baseaddr + VFB_MFB_BT431, fb, 8);
-		rom_offset = 0;
-	} else if (strcmp(device_name, "PMAG-BA")==0) {
-		/*  cfb in NetBSD  */
-		fb = dev_fb_init(machine, mem, baseaddr, VFB_GENERIC,
-		    1024,864, 1024,1024,8, device_name);
-		dev_bt459_init(machine, mem, baseaddr + VFB_CFB_BT459,
-		    baseaddr + 0x300000, fb, 8, irq_path, BT459_BA);
-		/*  ROM at both 0x380000 and 0x3c0000?  */
-		rom_offset = 0x380000;
-		rom_length = 0x080000;
-	} else if (strcmp(device_name, "PMAGB-BA")==0) {
-		/*  sfb in NetBSD  */
-		/*  TODO: This is not working with Ultrix yet.  */
-		fb = dev_fb_init(machine, mem, baseaddr + SFB_OFFSET_VRAM,
-		    VFB_GENERIC, 1280,1024, 1280,1024,8, device_name);
-		dev_sfb_init(machine, mem, baseaddr + SFB_ASIC_OFFSET, fb);
-		/*  TODO: the CLEAR doesn't get through, as the address
-			range is already in use by the asic  */
-		dev_bt459_init(machine, mem, baseaddr + SFB_OFFSET_BT459,
-		    baseaddr + SFB_CLEAR, fb, 8, irq_path, BT459_BBA);
-		rom_offset = 0x0;	/*  ? TODO  */
-	} else if (strcmp(device_name, "PMAG-CA")==0) {
-		/*  px in NetBSD  */
-		dev_px_init(machine, mem, baseaddr, DEV_PX_TYPE_PX, irq_path);
-		rom_offset = 0x3c0000;
-	} else if (strcmp(device_name, "PMAG-DA")==0) {
-		/*  pxg in NetBSD  */
-		dev_px_init(machine, mem, baseaddr, DEV_PX_TYPE_PXG, irq_path);
-		rom_offset = 0x3c0000;
-	} else if (strcmp(device_name, "PMAG-EA")==0) {
-		/*  pxg+ in NetBSD: TODO  (not supported by the kernel
-		    I've tried)  */
-		fatal("TODO (see dev_turbochannel.c)\n");
-		rom_offset = 0x3c0000;
-	} else if (strcmp(device_name, "PMAG-FA")==0) {
-		/*  "pxg+ Turbo" in NetBSD  */
-		dev_px_init(machine, mem, baseaddr,
-		    DEV_PX_TYPE_PXGPLUSTURBO, irq_path);
-		rom_offset = 0x3c0000;
-	} else if (strcmp(device_name, "PMAG-DV")==0) {
-		/*  xcfb in NetBSD: TODO  */
-		fb = dev_fb_init(machine, mem, baseaddr + 0x2000000,
-		    VFB_DEC_MAXINE, 0, 0, 0, 0, 0, "PMAG-DV");
-		/*  TODO:  not yet usable, needs a IMS332 vdac  */
-		rom_offset = 0x3c0000;
-	} else if (strcmp(device_name, "PMAG-JA")==0) {
-		/*  "Truecolor", mixed 8- and 24-bit  */
-		dev_pmagja_init(machine, mem, baseaddr, irq_path);
-		rom_offset = 0;		/*  NOTE: 0, not 0x3c0000  */
-	} else if (strcmp(device_name, "PMAG-RO")==0) {
-		/*  This works at least B/W in Ultrix, so far.  */
-		fb = dev_fb_init(machine, mem, baseaddr + 0x200000,
-		    VFB_GENERIC, 1280,1024, 1280,1024, 8, "PMAG-RO");
-		/*  TODO: bt463 at offset 0x040000, not bt459  */
-		dev_bt459_init(machine, mem, baseaddr + 0x40000, 0,
-		    fb, 8, irq_path, 0);		/*  TODO: type  */
-		dev_bt431_init(mem, baseaddr + 0x40010, fb, 8);  /*  cursor  */
-		rom_offset = 0x3c0000;
-	} else if (device_name[0] == '\0') {
-		/*  If this slot is empty, then occupy the entire
-		    4MB slot address range:  */
-		rom_offset = 0;
-		rom_length = 4*1048576;
-	} else {
-		fatal("warning: unknown TURBOchannel device name \"%s\"\n",
-		    device_name);
-	}
-
-	d->rom_skip = rom_skip;
-
-	nlen = strlen(device_name) + 30;
-	CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
-
-	if (*device_name)
-		snprintf(name2, nlen, "turbochannel [%s]", device_name);
-	else
-		snprintf(name2, nlen, "turbochannel");
-
-	memory_device_register(mem, name2, baseaddr + rom_offset + rom_skip,
-	    rom_length-rom_skip, dev_turbochannel_access, d, DM_DEFAULT, NULL);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_uninorth.c gxemul-0.7.0+dfsg/src/devices/dev_uninorth.c
--- gxemul-0.6.2/src/devices/dev_uninorth.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_uninorth.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,148 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Uni-North PCI controller (used by MacPPC machines)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_pci.h"
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+struct uninorth_data {
+	int		pciirq;
+
+	struct pci_data	*pci_data;
+	uint64_t	cur_addr;
+};
+
+
+DEVICE_ACCESS(uninorth_addr)
+{
+	struct uninorth_data *d = (struct uninorth_data *) extra;
+
+	if (writeflag == MEM_WRITE) {
+		uint64_t idata = memory_readmax64(cpu, data, len
+		    | MEM_PCI_LITTLE_ENDIAN);
+		int bus, dev, func, reg;
+
+		d->cur_addr = idata;
+		if (idata == 0)
+			return 0;
+
+		/*  Decompose the Uni-North tag:  */
+		if (idata & 1) {
+			idata &= ~1;
+			bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
+		} else {
+			bus = 0;
+			for (dev=11; dev<32; dev++)
+				if (idata & (1 << dev))
+					break;
+			if (dev == 32)
+				fatal("[ dev_uninorth_addr_access: no dev? "
+				    "idata=0x%08x ]\n", (int)idata);
+
+			func = (idata >> 8) & 7;
+			reg = idata & 0xff;
+		}
+
+		bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
+	} else {
+		/*  TODO: is returning the current address like this
+		    the correct behaviour?  */
+		memory_writemax64(cpu, data, len | MEM_PCI_LITTLE_ENDIAN,
+		    d->cur_addr);
+	}
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(uninorth_data)
+{
+	struct uninorth_data *d = (struct uninorth_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
+
+	bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? &odata :
+	    &idata, len, writeflag);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
+
+	return 1;
+}
+
+
+struct pci_data *dev_uninorth_init(struct machine *machine, struct memory *mem,
+	uint64_t addr, int isa_irqbase, int pciirq)
+{
+	struct uninorth_data *d;
+	uint64_t pci_io_offset, pci_mem_offset;
+	uint64_t isa_portbase = 0, isa_membase = 0;
+	uint64_t pci_portbase = 0, pci_membase = 0;
+
+	CHECK_ALLOCATION(d = (struct uninorth_data *) malloc(sizeof(struct uninorth_data)));
+	memset(d, 0, sizeof(struct uninorth_data));
+
+	d->pciirq = pciirq;
+
+	pci_io_offset  = 0x00000000ULL;
+	pci_mem_offset = 0x00000000ULL;
+	pci_portbase   = 0xd0000000ULL;
+	pci_membase    = 0xd1000000ULL;
+	isa_portbase   = 0xd2000000ULL;
+	isa_membase    = 0xd3000000ULL;
+
+	/*  Create a PCI bus:  */
+	d->pci_data = bus_pci_init(machine, "ZZZ_irq_stuff",
+	    pci_io_offset, pci_mem_offset,
+	    pci_portbase, pci_membase, "XXX_pci_irqbase",
+	    isa_portbase, isa_membase, "YYY_isa_irqbase");
+
+	/*  Add the PCI glue for the controller itself:  */
+	bus_pci_add(machine, d->pci_data, mem, 0, 11, 0, "uninorth");
+
+	/*  ADDR and DATA configuration ports:  */
+	memory_device_register(mem, "uninorth_pci_addr", addr + 0x800000,
+	    4, dev_uninorth_addr_access, d, DM_DEFAULT, NULL);
+	memory_device_register(mem, "uninorth_pci_data", addr + 0xc00000,
+	    8, dev_uninorth_data_access, d, DM_DEFAULT, NULL);
+
+	return d->pci_data;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_uninorth.cc gxemul-0.7.0+dfsg/src/devices/dev_uninorth.cc
--- gxemul-0.6.2/src/devices/dev_uninorth.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_uninorth.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,148 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Uni-North PCI controller (used by MacPPC machines)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_pci.h"
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-struct uninorth_data {
-	int		pciirq;
-
-	struct pci_data	*pci_data;
-	uint64_t	cur_addr;
-};
-
-
-DEVICE_ACCESS(uninorth_addr)
-{
-	struct uninorth_data *d = (struct uninorth_data *) extra;
-
-	if (writeflag == MEM_WRITE) {
-		uint64_t idata = memory_readmax64(cpu, data, len
-		    | MEM_PCI_LITTLE_ENDIAN);
-		int bus, dev, func, reg;
-
-		d->cur_addr = idata;
-		if (idata == 0)
-			return 0;
-
-		/*  Decompose the Uni-North tag:  */
-		if (idata & 1) {
-			idata &= ~1;
-			bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
-		} else {
-			bus = 0;
-			for (dev=11; dev<32; dev++)
-				if (idata & (1 << dev))
-					break;
-			if (dev == 32)
-				fatal("[ dev_uninorth_addr_access: no dev? "
-				    "idata=0x%08x ]\n", (int)idata);
-
-			func = (idata >> 8) & 7;
-			reg = idata & 0xff;
-		}
-
-		bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
-	} else {
-		/*  TODO: is returning the current address like this
-		    the correct behaviour?  */
-		memory_writemax64(cpu, data, len | MEM_PCI_LITTLE_ENDIAN,
-		    d->cur_addr);
-	}
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(uninorth_data)
-{
-	struct uninorth_data *d = (struct uninorth_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
-
-	bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? &odata :
-	    &idata, len, writeflag);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
-
-	return 1;
-}
-
-
-struct pci_data *dev_uninorth_init(struct machine *machine, struct memory *mem,
-	uint64_t addr, int isa_irqbase, int pciirq)
-{
-	struct uninorth_data *d;
-	uint64_t pci_io_offset, pci_mem_offset;
-	uint64_t isa_portbase = 0, isa_membase = 0;
-	uint64_t pci_portbase = 0, pci_membase = 0;
-
-	CHECK_ALLOCATION(d = (struct uninorth_data *) malloc(sizeof(struct uninorth_data)));
-	memset(d, 0, sizeof(struct uninorth_data));
-
-	d->pciirq = pciirq;
-
-	pci_io_offset  = 0x00000000ULL;
-	pci_mem_offset = 0x00000000ULL;
-	pci_portbase   = 0xd0000000ULL;
-	pci_membase    = 0xd1000000ULL;
-	isa_portbase   = 0xd2000000ULL;
-	isa_membase    = 0xd3000000ULL;
-
-	/*  Create a PCI bus:  */
-	d->pci_data = bus_pci_init(machine, "ZZZ_irq_stuff",
-	    pci_io_offset, pci_mem_offset,
-	    pci_portbase, pci_membase, "XXX_pci_irqbase",
-	    isa_portbase, isa_membase, "YYY_isa_irqbase");
-
-	/*  Add the PCI glue for the controller itself:  */
-	bus_pci_add(machine, d->pci_data, mem, 0, 11, 0, "uninorth");
-
-	/*  ADDR and DATA configuration ports:  */
-	memory_device_register(mem, "uninorth_pci_addr", addr + 0x800000,
-	    4, dev_uninorth_addr_access, d, DM_DEFAULT, NULL);
-	memory_device_register(mem, "uninorth_pci_data", addr + 0xc00000,
-	    8, dev_uninorth_data_access, d, DM_DEFAULT, NULL);
-
-	return d->pci_data;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_unreadable.c gxemul-0.7.0+dfsg/src/devices/dev_unreadable.c
--- gxemul-0.6.2/src/devices/dev_unreadable.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_unreadable.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,55 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: A simple device which returns an error for all reads/writes
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+DEVICE_ACCESS(unreadable)
+{
+	return 0;
+}
+
+
+DEVINIT(unreadable)
+{
+	memory_device_register(devinit->machine->memory,
+	    devinit->name, devinit->addr, devinit->len,
+	    dev_unreadable_access, NULL, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_unreadable.cc gxemul-0.7.0+dfsg/src/devices/dev_unreadable.cc
--- gxemul-0.6.2/src/devices/dev_unreadable.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_unreadable.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,55 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: A simple device which returns an error for all reads/writes
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-DEVICE_ACCESS(unreadable)
-{
-	return 0;
-}
-
-
-DEVINIT(unreadable)
-{
-	memory_device_register(devinit->machine->memory,
-	    devinit->name, devinit->addr, devinit->len,
-	    dev_unreadable_access, NULL, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_v3.c gxemul-0.7.0+dfsg/src/devices/dev_v3.c
--- gxemul-0.6.2/src/devices/dev_v3.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_v3.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,347 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: V3 Semiconductor PCI controller
+ *
+ *  The ISA interrupt controller part forwards ISA interrupts as follows
+ *  (on Algor P5064):
+ *
+ *	ISA interrupt 3 and 4		-> MIPS interrupt 4 ("Local")
+ *	All other ISA interrupts	-> MIPS interrupt 2 ("ISA")
+ *
+ *  See NetBSD's src/sys/arch/algor/pci/ for details.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+struct v3_data {
+	struct interrupt	irq_isa;
+	struct interrupt	irq_local;
+	uint8_t			secondary_mask1;
+
+	struct pic8259_data* pic1;
+	struct pic8259_data* pic2;
+	int			*ptr_to_pending_timer_interrupts;
+
+	struct pci_data		*pci_data;
+	uint16_t		lb_map0;
+};
+
+
+/*
+ *  v3_isa_interrupt_common():
+ */
+void v3_isa_interrupt_common(struct v3_data *d, int old_isa_assert)
+{
+	int new_isa_assert;
+
+	/*  Any interrupt assertions on PIC2 go to irq 2 on PIC1  */
+	/*  (TODO: don't hardcode this here)  */
+	if (d->pic2->irr & ~d->pic2->ier)
+		d->pic1->irr |= 0x04;
+	else
+		d->pic1->irr &= ~0x04;
+
+	new_isa_assert = d->pic1->irr & ~d->pic1->ier;
+
+	if (old_isa_assert == new_isa_assert)
+		return;
+
+	if (new_isa_assert & d->secondary_mask1)
+		INTERRUPT_ASSERT(d->irq_local);
+	else
+		INTERRUPT_DEASSERT(d->irq_local);
+
+	if (new_isa_assert & ~d->secondary_mask1)
+		INTERRUPT_ASSERT(d->irq_isa);
+	else
+		INTERRUPT_DEASSERT(d->irq_isa);
+}
+
+
+/*
+ *  v3_isa_interrupt_assert():
+ *
+ *  Called whenever an ISA device asserts an interrupt (0..15).
+ *  If the interrupt number is 16, then it is a re-assert.
+ */
+void v3_isa_interrupt_assert(struct interrupt *interrupt)
+{
+	struct v3_data *d = (struct v3_data *) interrupt->extra;
+	int old_isa_assert, line = interrupt->line;
+	int mask = 1 << (line & 7);
+
+	old_isa_assert = d->pic1->irr & ~d->pic1->ier;
+
+	if (line < 8)
+		d->pic1->irr |= mask;
+	else if (line < 16)
+		d->pic2->irr |= mask;
+
+	v3_isa_interrupt_common(d, old_isa_assert);
+}
+
+
+/*
+ *  v3_isa_interrupt_deassert():
+ *
+ *  Called whenever an ISA device deasserts an interrupt (0..15).
+ *  If the interrupt number is 16, then it is a re-assert.
+ */
+void v3_isa_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct v3_data *d = (struct v3_data *) interrupt->extra;
+	int line = interrupt->line, mask = 1 << (line & 7);
+	int old_irr1 = d->pic1->irr, old_isa_assert;
+
+	old_isa_assert = old_irr1 & ~d->pic1->ier;
+
+	if (line < 8)
+		d->pic1->irr &= ~mask;
+	else if (line < 16)
+		d->pic2->irr &= ~mask;
+
+	/*  If IRQ 0 has been cleared, then this is a timer interrupt.
+	    Let's ack it here:  */
+	if (old_irr1 & 1 && !(d->pic1->irr & 1) &&
+	    d->ptr_to_pending_timer_interrupts != NULL &&
+            (*d->ptr_to_pending_timer_interrupts) > 0)
+                (*d->ptr_to_pending_timer_interrupts) --;
+
+	v3_isa_interrupt_common(d, old_isa_assert);
+}
+
+
+DEVICE_ACCESS(v3_pci)
+{
+	uint64_t idata = 0, odata = 0;
+	int bus, dev, func, reg;
+	struct v3_data *d = (struct v3_data *) extra;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
+
+	/*  Decompose the tag:  */
+	relative_addr &= 0xfffff;
+	relative_addr |= ((d->lb_map0 & 0xfff0) << 16);
+	bus = 0;
+	for (dev=24; dev<32; dev++)
+		if (relative_addr & (1 << dev))
+			break;
+	dev -= 24;
+	if (dev == 8) {
+		fatal("[ v3_pci: NO DEVICE? ]\n");
+		dev = 0;
+	}
+	func = (relative_addr >> 8) & 7;
+	reg  = relative_addr & 0xfc;
+	bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
+
+	/*  Pass semi-direct PCI accesses onto bus_pci:  */
+	bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
+	    &odata : &idata, len, writeflag);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
+
+	return 1;
+}
+
+
+DEVICE_ACCESS(v3)
+{
+	struct v3_data *d = (struct v3_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	switch (relative_addr) {
+
+	case 0x06:	/*  PCI stat  */
+		break;
+
+	case 0x08:	/*  Revision  */
+		odata = 4;
+		break;
+
+	case 0x18:	/*  PCI DMA base 1  */
+		odata = 0x11000000;
+		break;
+
+	case 0x5e:	/*  LB MAP0  */
+		if (writeflag == MEM_READ)
+			odata = d->lb_map0;
+		else
+			d->lb_map0 = idata;
+		break;
+
+	case 0x62:	/*  PCI mem base 1  */
+		odata = 0x1100;
+		break;
+
+	case 0x64:	/*  L2 BASE  */
+		odata = 1;	/*  pci i/o enable  */
+		break;
+
+	case 0x66:	/*  Map 2  */
+		odata = 0x1d00;
+		break;
+
+	default:if (writeflag == MEM_WRITE) {
+			fatal("[ v3: unimplemented write to "
+			    "offset 0x%x: data=0x%x ]\n", (int)
+			    relative_addr, (int)idata);
+		} else {
+			fatal("[ v3: unimplemented read from "
+			    "offset 0x%x ]\n", (int)relative_addr);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(v3)
+{
+	struct v3_data *d;
+	uint32_t isa_port_base = 0x1d000000;
+	char tmpstr[200];
+	char isa_irq_base[200];
+	char pci_irq_base[200];
+	int i;
+
+	CHECK_ALLOCATION(d = (struct v3_data *) malloc(sizeof(struct v3_data)));
+	memset(d, 0, sizeof(struct v3_data));
+
+	switch (devinit->machine->machine_type) {
+	case MACHINE_ALGOR:
+		snprintf(tmpstr, sizeof(tmpstr), "%s.4",
+		    devinit->interrupt_path);
+		INTERRUPT_CONNECT(tmpstr, d->irq_local);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.2",
+		    devinit->interrupt_path);
+		INTERRUPT_CONNECT(tmpstr, d->irq_isa);
+
+		d->secondary_mask1 = 0x18;
+		break;
+
+	default:fatal("!\n! WARNING: v3 for non-implemented machine"
+		    " type %i\n!\n", devinit->machine->machine_type);
+		exit(1);
+	}
+
+	/*
+	 *  Register the 16 possible ISA interrupts, plus a dummy. The
+	 *  dummy is used by re-asserts.
+	 */
+	for (i=0; i<17; i++) {
+		struct interrupt templ;
+		char n[300];
+		snprintf(n, sizeof(n), "%s.v3.isa.%i",
+		    devinit->interrupt_path, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = i;
+		templ.name = n;
+		templ.extra = d;
+		templ.interrupt_assert = v3_isa_interrupt_assert;
+		templ.interrupt_deassert = v3_isa_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	/*  Register two 8259 PICs:  */
+	snprintf(tmpstr, sizeof(tmpstr), "8259 irq=%s.v3.isa.16 addr=0x%llx",
+	    devinit->interrupt_path, (long long)(isa_port_base + 0x20));
+	d->pic1 = devinit->machine->isa_pic_data.pic1 = (struct pic8259_data *)
+	    device_add(devinit->machine, tmpstr);
+	d->ptr_to_pending_timer_interrupts =
+	    devinit->machine->isa_pic_data.pending_timer_interrupts;
+
+	snprintf(tmpstr, sizeof(tmpstr), "8259 irq=%s.v3.isa.2 addr=0x%llx",
+	    devinit->interrupt_path, (long long)(isa_port_base + 0xa0));
+	d->pic2 = devinit->machine->isa_pic_data.pic2 = (struct pic8259_data *)
+	    device_add(devinit->machine, tmpstr);
+
+	snprintf(isa_irq_base, sizeof(isa_irq_base), "%s.v3",
+	    devinit->interrupt_path);
+	snprintf(pci_irq_base, sizeof(pci_irq_base), "%s.v3",
+	    devinit->interrupt_path);
+
+	/*  Register a PCI bus:  */
+	d->pci_data = bus_pci_init(
+	    devinit->machine,
+	    pci_irq_base		/*  pciirq: TODO  */,
+	    0x1d000000,			/*  pci device io offset  */
+	    0x11000000,			/*  pci device mem offset: TODO  */
+	    0x00000000,			/*  PCI portbase: TODO  */
+	    0x00000000,			/*  PCI membase: TODO  */
+	    pci_irq_base,		/*  PCI irqbase  */
+	    isa_port_base,		/*  ISA portbase  */
+	    0x10000000,			/*  ISA membase  */
+	    isa_irq_base);		/*  ISA irqbase  */
+
+	switch (devinit->machine->machine_type) {
+	case MACHINE_ALGOR:
+		bus_pci_add(devinit->machine, d->pci_data,
+		    devinit->machine->memory, 0, 2, 0, "piix3_isa");
+		bus_pci_add(devinit->machine, d->pci_data,
+		    devinit->machine->memory, 0, 2, 1, "piix3_ide");
+		break;
+	default:fatal("!\n! WARNING: v3 for non-implemented machine"
+		    " type %i\n!\n", devinit->machine->machine_type);
+		exit(1);
+	}
+
+	/*  PCI configuration space:  */
+	memory_device_register(devinit->machine->memory, "v3_pci",
+	    0x1ee00000, 0x100000, dev_v3_pci_access, d, DM_DEFAULT, NULL);
+
+	/*  PCI controller:  */
+	memory_device_register(devinit->machine->memory, "v3",
+	    0x1ef00000, 0x1000, dev_v3_access, d, DM_DEFAULT, NULL);
+
+	devinit->return_ptr = d->pci_data;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_v3.cc gxemul-0.7.0+dfsg/src/devices/dev_v3.cc
--- gxemul-0.6.2/src/devices/dev_v3.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_v3.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,347 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: V3 Semiconductor PCI controller
- *
- *  The ISA interrupt controller part forwards ISA interrupts as follows
- *  (on Algor P5064):
- *
- *	ISA interrupt 3 and 4		-> MIPS interrupt 4 ("Local")
- *	All other ISA interrupts	-> MIPS interrupt 2 ("ISA")
- *
- *  See NetBSD's src/sys/arch/algor/pci/ for details.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-struct v3_data {
-	struct interrupt	irq_isa;
-	struct interrupt	irq_local;
-	uint8_t			secondary_mask1;
-
-	struct pic8259_data* pic1;
-	struct pic8259_data* pic2;
-	int			*ptr_to_pending_timer_interrupts;
-
-	struct pci_data		*pci_data;
-	uint16_t		lb_map0;
-};
-
-
-/*
- *  v3_isa_interrupt_common():
- */
-void v3_isa_interrupt_common(struct v3_data *d, int old_isa_assert)
-{
-	int new_isa_assert;
-
-	/*  Any interrupt assertions on PIC2 go to irq 2 on PIC1  */
-	/*  (TODO: don't hardcode this here)  */
-	if (d->pic2->irr & ~d->pic2->ier)
-		d->pic1->irr |= 0x04;
-	else
-		d->pic1->irr &= ~0x04;
-
-	new_isa_assert = d->pic1->irr & ~d->pic1->ier;
-
-	if (old_isa_assert == new_isa_assert)
-		return;
-
-	if (new_isa_assert & d->secondary_mask1)
-		INTERRUPT_ASSERT(d->irq_local);
-	else
-		INTERRUPT_DEASSERT(d->irq_local);
-
-	if (new_isa_assert & ~d->secondary_mask1)
-		INTERRUPT_ASSERT(d->irq_isa);
-	else
-		INTERRUPT_DEASSERT(d->irq_isa);
-}
-
-
-/*
- *  v3_isa_interrupt_assert():
- *
- *  Called whenever an ISA device asserts an interrupt (0..15).
- *  If the interrupt number is 16, then it is a re-assert.
- */
-void v3_isa_interrupt_assert(struct interrupt *interrupt)
-{
-	struct v3_data *d = (struct v3_data *) interrupt->extra;
-	int old_isa_assert, line = interrupt->line;
-	int mask = 1 << (line & 7);
-
-	old_isa_assert = d->pic1->irr & ~d->pic1->ier;
-
-	if (line < 8)
-		d->pic1->irr |= mask;
-	else if (line < 16)
-		d->pic2->irr |= mask;
-
-	v3_isa_interrupt_common(d, old_isa_assert);
-}
-
-
-/*
- *  v3_isa_interrupt_deassert():
- *
- *  Called whenever an ISA device deasserts an interrupt (0..15).
- *  If the interrupt number is 16, then it is a re-assert.
- */
-void v3_isa_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct v3_data *d = (struct v3_data *) interrupt->extra;
-	int line = interrupt->line, mask = 1 << (line & 7);
-	int old_irr1 = d->pic1->irr, old_isa_assert;
-
-	old_isa_assert = old_irr1 & ~d->pic1->ier;
-
-	if (line < 8)
-		d->pic1->irr &= ~mask;
-	else if (line < 16)
-		d->pic2->irr &= ~mask;
-
-	/*  If IRQ 0 has been cleared, then this is a timer interrupt.
-	    Let's ack it here:  */
-	if (old_irr1 & 1 && !(d->pic1->irr & 1) &&
-	    d->ptr_to_pending_timer_interrupts != NULL &&
-            (*d->ptr_to_pending_timer_interrupts) > 0)
-                (*d->ptr_to_pending_timer_interrupts) --;
-
-	v3_isa_interrupt_common(d, old_isa_assert);
-}
-
-
-DEVICE_ACCESS(v3_pci)
-{
-	uint64_t idata = 0, odata = 0;
-	int bus, dev, func, reg;
-	struct v3_data *d = (struct v3_data *) extra;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
-
-	/*  Decompose the tag:  */
-	relative_addr &= 0xfffff;
-	relative_addr |= ((d->lb_map0 & 0xfff0) << 16);
-	bus = 0;
-	for (dev=24; dev<32; dev++)
-		if (relative_addr & (1 << dev))
-			break;
-	dev -= 24;
-	if (dev == 8) {
-		fatal("[ v3_pci: NO DEVICE? ]\n");
-		dev = 0;
-	}
-	func = (relative_addr >> 8) & 7;
-	reg  = relative_addr & 0xfc;
-	bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
-
-	/*  Pass semi-direct PCI accesses onto bus_pci:  */
-	bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
-	    &odata : &idata, len, writeflag);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
-
-	return 1;
-}
-
-
-DEVICE_ACCESS(v3)
-{
-	struct v3_data *d = (struct v3_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	switch (relative_addr) {
-
-	case 0x06:	/*  PCI stat  */
-		break;
-
-	case 0x08:	/*  Revision  */
-		odata = 4;
-		break;
-
-	case 0x18:	/*  PCI DMA base 1  */
-		odata = 0x11000000;
-		break;
-
-	case 0x5e:	/*  LB MAP0  */
-		if (writeflag == MEM_READ)
-			odata = d->lb_map0;
-		else
-			d->lb_map0 = idata;
-		break;
-
-	case 0x62:	/*  PCI mem base 1  */
-		odata = 0x1100;
-		break;
-
-	case 0x64:	/*  L2 BASE  */
-		odata = 1;	/*  pci i/o enable  */
-		break;
-
-	case 0x66:	/*  Map 2  */
-		odata = 0x1d00;
-		break;
-
-	default:if (writeflag == MEM_WRITE) {
-			fatal("[ v3: unimplemented write to "
-			    "offset 0x%x: data=0x%x ]\n", (int)
-			    relative_addr, (int)idata);
-		} else {
-			fatal("[ v3: unimplemented read from "
-			    "offset 0x%x ]\n", (int)relative_addr);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(v3)
-{
-	struct v3_data *d;
-	uint32_t isa_port_base = 0x1d000000;
-	char tmpstr[200];
-	char isa_irq_base[200];
-	char pci_irq_base[200];
-	int i;
-
-	CHECK_ALLOCATION(d = (struct v3_data *) malloc(sizeof(struct v3_data)));
-	memset(d, 0, sizeof(struct v3_data));
-
-	switch (devinit->machine->machine_type) {
-	case MACHINE_ALGOR:
-		snprintf(tmpstr, sizeof(tmpstr), "%s.4",
-		    devinit->interrupt_path);
-		INTERRUPT_CONNECT(tmpstr, d->irq_local);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.2",
-		    devinit->interrupt_path);
-		INTERRUPT_CONNECT(tmpstr, d->irq_isa);
-
-		d->secondary_mask1 = 0x18;
-		break;
-
-	default:fatal("!\n! WARNING: v3 for non-implemented machine"
-		    " type %i\n!\n", devinit->machine->machine_type);
-		exit(1);
-	}
-
-	/*
-	 *  Register the 16 possible ISA interrupts, plus a dummy. The
-	 *  dummy is used by re-asserts.
-	 */
-	for (i=0; i<17; i++) {
-		struct interrupt templ;
-		char n[300];
-		snprintf(n, sizeof(n), "%s.v3.isa.%i",
-		    devinit->interrupt_path, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = i;
-		templ.name = n;
-		templ.extra = d;
-		templ.interrupt_assert = v3_isa_interrupt_assert;
-		templ.interrupt_deassert = v3_isa_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	/*  Register two 8259 PICs:  */
-	snprintf(tmpstr, sizeof(tmpstr), "8259 irq=%s.v3.isa.16 addr=0x%llx",
-	    devinit->interrupt_path, (long long)(isa_port_base + 0x20));
-	d->pic1 = devinit->machine->isa_pic_data.pic1 = (struct pic8259_data *)
-	    device_add(devinit->machine, tmpstr);
-	d->ptr_to_pending_timer_interrupts =
-	    devinit->machine->isa_pic_data.pending_timer_interrupts;
-
-	snprintf(tmpstr, sizeof(tmpstr), "8259 irq=%s.v3.isa.2 addr=0x%llx",
-	    devinit->interrupt_path, (long long)(isa_port_base + 0xa0));
-	d->pic2 = devinit->machine->isa_pic_data.pic2 = (struct pic8259_data *)
-	    device_add(devinit->machine, tmpstr);
-
-	snprintf(isa_irq_base, sizeof(isa_irq_base), "%s.v3",
-	    devinit->interrupt_path);
-	snprintf(pci_irq_base, sizeof(pci_irq_base), "%s.v3",
-	    devinit->interrupt_path);
-
-	/*  Register a PCI bus:  */
-	d->pci_data = bus_pci_init(
-	    devinit->machine,
-	    pci_irq_base		/*  pciirq: TODO  */,
-	    0x1d000000,			/*  pci device io offset  */
-	    0x11000000,			/*  pci device mem offset: TODO  */
-	    0x00000000,			/*  PCI portbase: TODO  */
-	    0x00000000,			/*  PCI membase: TODO  */
-	    pci_irq_base,		/*  PCI irqbase  */
-	    isa_port_base,		/*  ISA portbase  */
-	    0x10000000,			/*  ISA membase  */
-	    isa_irq_base);		/*  ISA irqbase  */
-
-	switch (devinit->machine->machine_type) {
-	case MACHINE_ALGOR:
-		bus_pci_add(devinit->machine, d->pci_data,
-		    devinit->machine->memory, 0, 2, 0, "piix3_isa");
-		bus_pci_add(devinit->machine, d->pci_data,
-		    devinit->machine->memory, 0, 2, 1, "piix3_ide");
-		break;
-	default:fatal("!\n! WARNING: v3 for non-implemented machine"
-		    " type %i\n!\n", devinit->machine->machine_type);
-		exit(1);
-	}
-
-	/*  PCI configuration space:  */
-	memory_device_register(devinit->machine->memory, "v3_pci",
-	    0x1ee00000, 0x100000, dev_v3_pci_access, d, DM_DEFAULT, NULL);
-
-	/*  PCI controller:  */
-	memory_device_register(devinit->machine->memory, "v3",
-	    0x1ef00000, 0x1000, dev_v3_access, d, DM_DEFAULT, NULL);
-
-	devinit->return_ptr = d->pci_data;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_vga.c gxemul-0.7.0+dfsg/src/devices/dev_vga.c
--- gxemul-0.6.2/src/devices/dev_vga.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_vga.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1271 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: VGA framebuffer device (charcell and graphics modes)
+ *
+ *  It should work with 80x25 and 40x25 text modes, and with a few graphics
+ *  modes as long as no fancy VGA features are used.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "../include/vga.h"
+
+/*  These are generated from binary font files:  */
+#include "fonts/font8x8.c"
+#include "fonts/font8x10.c"
+#include "fonts/font8x16.c"
+
+
+/*  For videomem -> framebuffer updates:  */
+#define	VGA_TICK_SHIFT		18
+
+#define	MAX_RETRACE_SCANLINES	420
+#define	N_IS1_READ_THRESHOLD	50
+
+#define	GFX_ADDR_WINDOW		0x18000
+
+#define	VGA_FB_ADDR	0x1c00000000ULL
+
+#define	MODE_CHARCELL		1
+#define	MODE_GRAPHICS		2
+
+#define	GRAPHICS_MODE_8BIT	1
+#define	GRAPHICS_MODE_4BIT	2
+
+struct vga_data {
+	uint64_t	videomem_base;
+	uint64_t	control_base;
+
+	struct vfb_data *fb;
+	uint32_t	fb_size;
+
+	int		fb_max_x;		/*  pixels  */
+	int		fb_max_y;		/*  pixels  */
+	int		max_x;			/*  charcells or pixels  */
+	int		max_y;			/*  charcells or pixels  */
+
+	/*  Selects charcell mode or graphics mode:  */
+	int		cur_mode;
+
+	/*  Common for text and graphics modes:  */
+	int		pixel_repx, pixel_repy;
+
+	/*  Textmode:  */
+	int		font_width;
+	int		font_height;
+	unsigned char	*font;
+	size_t		charcells_size;
+	unsigned char	*charcells;		/*  2 bytes per char  */
+	unsigned char	*charcells_outputed;	/*  text  */
+	unsigned char	*charcells_drawn;	/*  framebuffer  */
+
+	/*  Graphics:  */
+	int		graphics_mode;
+	int		bits_per_pixel;
+	unsigned char	*gfx_mem;
+	uint32_t	gfx_mem_size;
+
+	/*  Registers:  */
+	int		attribute_state;	/*  0 or 1  */
+	unsigned char	attribute_reg_select;
+	unsigned char	attribute_reg[256];
+
+	unsigned char	misc_output_reg;
+
+	unsigned char	sequencer_reg_select;
+	unsigned char	sequencer_reg[256];
+
+	unsigned char	graphcontr_reg_select;
+	unsigned char	graphcontr_reg[256];
+
+	unsigned char	crtc_reg_select;
+	unsigned char	crtc_reg[256];
+
+	unsigned char	palette_read_index;
+	char		palette_read_subindex;
+	unsigned char	palette_write_index;
+	char		palette_write_subindex;
+
+	int		current_retrace_line;
+	int		input_status_1;
+
+	/*  Palette per scanline during retrace:  */
+	unsigned char	*retrace_palette;
+	int		use_palette_per_line;
+	int64_t		n_is1_reads;
+
+	/*  Misc.:  */
+	int		console_handle;
+
+	int		cursor_x;
+	int		cursor_y;
+
+	int		modified;
+	int		palette_modified;
+	int		update_x1;
+	int		update_y1;
+	int		update_x2;
+	int		update_y2;
+};
+
+
+/*
+ *  recalc_cursor_position():
+ *
+ *  Should be called whenever the cursor location _or_ the display
+ *  base has been changed.
+ */
+static void recalc_cursor_position(struct vga_data *d)
+{
+	int base = (d->crtc_reg[VGA_CRTC_START_ADDR_HIGH] << 8)
+	    + d->crtc_reg[VGA_CRTC_START_ADDR_LOW];
+	int ofs = d->crtc_reg[VGA_CRTC_CURSOR_LOCATION_HIGH] * 256 +
+	    d->crtc_reg[VGA_CRTC_CURSOR_LOCATION_LOW];
+	ofs -= base;
+	d->cursor_x = ofs % d->max_x;
+	d->cursor_y = ofs / d->max_x;
+}
+
+
+/*
+ *  register_reset():
+ *
+ *  Resets many registers to sane values.
+ */
+static void register_reset(struct vga_data *d)
+{
+	/*  Home cursor and start at the top:  */
+	d->crtc_reg[VGA_CRTC_CURSOR_LOCATION_HIGH] =
+	    d->crtc_reg[VGA_CRTC_CURSOR_LOCATION_LOW] = 0;
+	d->crtc_reg[VGA_CRTC_START_ADDR_HIGH] =
+	    d->crtc_reg[VGA_CRTC_START_ADDR_LOW] = 0;
+
+	recalc_cursor_position(d);
+
+	/*  Reset cursor scanline stuff:  */
+	d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_START] = d->font_height - 2;
+	d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_END] = d->font_height - 1;
+
+	d->sequencer_reg[VGA_SEQ_MAP_MASK] = 0x0f;
+	d->graphcontr_reg[VGA_GRAPHCONTR_MASK] = 0xff;
+
+	d->misc_output_reg = VGA_MISC_OUTPUT_IOAS;
+	d->n_is1_reads = 0;
+}
+
+
+static void c_putstr(struct vga_data *d, const char *s)
+{
+	while (*s)
+		console_putchar(d->console_handle, *s++);
+}
+
+
+/*
+ *  reset_palette():
+ */
+static void reset_palette(struct vga_data *d, int grayscale)
+{
+	int i, r, g, b;
+
+	/*  TODO: default values for entry 16..255?  */
+	for (i=16; i<256; i++)
+		d->fb->rgb_palette[i*3 + 0] = d->fb->rgb_palette[i*3 + 1] =
+		    d->fb->rgb_palette[i*3 + 2] = (i & 15) * 4;
+	d->palette_modified = 1;
+	i = 0;
+
+	if (grayscale) {
+		for (r=0; r<2; r++)
+		    for (g=0; g<2; g++)
+			for (b=0; b<2; b++) {
+				d->fb->rgb_palette[i + 0] =
+				    d->fb->rgb_palette[i + 1] =
+				    d->fb->rgb_palette[i + 2] =
+				    (r+g+b) * 0xaa / 3;
+				d->fb->rgb_palette[i + 8*3 + 0] =
+				    d->fb->rgb_palette[i + 8*3 + 1] =
+				    d->fb->rgb_palette[i + 8*3 + 2] =
+				    (r+g+b) * 0xaa / 3 + 0x55;
+				i+=3;
+			}
+		return;
+	}
+
+	for (r=0; r<2; r++)
+		for (g=0; g<2; g++)
+			for (b=0; b<2; b++) {
+				d->fb->rgb_palette[i + 0] = r * 0xaa;
+				d->fb->rgb_palette[i + 1] = g * 0xaa;
+				d->fb->rgb_palette[i + 2] = b * 0xaa;
+				i+=3;
+			}
+	for (r=0; r<2; r++)
+		for (g=0; g<2; g++)
+			for (b=0; b<2; b++) {
+				d->fb->rgb_palette[i + 0] = r * 0xaa + 0x55;
+				d->fb->rgb_palette[i + 1] = g * 0xaa + 0x55;
+				d->fb->rgb_palette[i + 2] = b * 0xaa + 0x55;
+				i+=3;
+			}
+}
+
+
+/*
+ *  vga_update_textmode():
+ *
+ *  Called from vga_update() when x11 in_use is false. This causes modified
+ *  character cells to be "simulated" by outputing ANSI escape sequences
+ *  that draw the characters in a terminal window instead.
+ */
+static void vga_update_textmode(struct machine *machine,
+	struct vga_data *d, int base, int start, int end)
+{
+	char s[50];
+	int i, oldcolor = -1, printed_last = 0;
+
+	for (i=start; i<=end; i+=2) {
+		unsigned char ch = d->charcells[base+i];
+		int fg = d->charcells[base+i+1] & 15;
+		int bg = (d->charcells[base+i+1] >> 4) & 15;
+			/*  top bit of bg = blink  */
+		int x = (i/2) % d->max_x;
+		int y = (i/2) / d->max_x;
+
+		if (d->charcells[base+i] == d->charcells_outputed[i] &&
+		    d->charcells[base+i+1] == d->charcells_outputed[i+1]) {
+			printed_last = 0;
+			continue;
+		}
+
+		d->charcells_outputed[i] = d->charcells[base+i];
+		d->charcells_outputed[i+1] = d->charcells[base+i+1];
+
+		if (!printed_last || x == 0) {
+			snprintf(s, sizeof(s), "\033[%i;%iH", y + 1, x + 1);
+			c_putstr(d, s);
+		}
+		if (oldcolor < 0 || (bg<<4)+fg != oldcolor || !printed_last) {
+			snprintf(s, sizeof(s), "\033[0;"); c_putstr(d, s);
+
+			switch (fg & 7) {
+			case 0:	c_putstr(d, "30"); break;
+			case 1:	c_putstr(d, "34"); break;
+			case 2:	c_putstr(d, "32"); break;
+			case 3:	c_putstr(d, "36"); break;
+			case 4:	c_putstr(d, "31"); break;
+			case 5:	c_putstr(d, "35"); break;
+			case 6:	c_putstr(d, "33"); break;
+			case 7:	c_putstr(d, "37"); break;
+			}
+			if (fg & 8)
+				c_putstr(d, ";1");
+			c_putstr(d, ";");
+			switch (bg & 7) {
+			case 0:	c_putstr(d, "40"); break;
+			case 1:	c_putstr(d, "44"); break;
+			case 2:	c_putstr(d, "42"); break;
+			case 3:	c_putstr(d, "46"); break;
+			case 4:	c_putstr(d, "41"); break;
+			case 5:	c_putstr(d, "45"); break;
+			case 6:	c_putstr(d, "43"); break;
+			case 7:	c_putstr(d, "47"); break;
+			}
+			/*  TODO: blink  */
+			c_putstr(d, "m");
+		}
+
+		if (ch >= 0x20 && ch != 127)
+			console_putchar(d->console_handle, ch);
+
+		oldcolor = (bg << 4) + fg;
+		printed_last = 1;
+	}
+
+	/*  Restore the terminal's cursor position:  */
+	snprintf(s, sizeof(s), "\033[%i;%iH", d->cursor_y + 1, d->cursor_x + 1);
+	c_putstr(d, s);
+}
+
+
+/*
+ *  vga_update_graphics():
+ *
+ *  This function should be called whenever any part of d->gfx_mem[] has
+ *  been written to. It will redraw all pixels within the range x1,y1
+ *  .. x2,y2 using the right palette.
+ */
+static void vga_update_graphics(struct machine *machine, struct vga_data *d,
+	int x1, int y1, int x2, int y2)
+{
+	int x, y, ix, iy, c, rx = d->pixel_repx, ry = d->pixel_repy;
+	unsigned char pixel[3];
+
+	for (y=y1; y<=y2; y++)
+		for (x=x1; x<=x2; x++) {
+			/*  addr is where to read from VGA memory, addr2 is
+			    where to write on the 24-bit framebuffer device  */
+			int addr = (y * d->max_x + x) * d->bits_per_pixel;
+			switch (d->bits_per_pixel) {
+			case 8:	addr >>= 3;
+				c = d->gfx_mem[addr];
+				pixel[0] = d->fb->rgb_palette[c*3+0];
+				pixel[1] = d->fb->rgb_palette[c*3+1];
+				pixel[2] = d->fb->rgb_palette[c*3+2];
+				break;
+			case 4:	addr >>= 2;
+				if (addr & 1)
+					c = d->gfx_mem[addr >> 1] >> 4;
+				else
+					c = d->gfx_mem[addr >> 1] & 0xf;
+				pixel[0] = d->fb->rgb_palette[c*3+0];
+				pixel[1] = d->fb->rgb_palette[c*3+1];
+				pixel[2] = d->fb->rgb_palette[c*3+2];
+				break;
+			}
+			for (iy=y*ry; iy<(y+1)*ry; iy++)
+				for (ix=x*rx; ix<(x+1)*rx; ix++) {
+					uint32_t addr2 = (d->fb_max_x * iy
+					    + ix) * 3;
+					if (addr2 < d->fb_size)
+						dev_fb_access(machine->cpus[0],
+						    machine->memory, addr2,
+						    pixel, sizeof(pixel),
+						    MEM_WRITE, d->fb);
+				}
+		}
+}
+
+
+/*
+ *  vga_update_text():
+ *
+ *  This function should be called whenever any part of d->charcells[] has
+ *  been written to. It will redraw all characters within the range x1,y1
+ *  .. x2,y2 using the right palette.
+ */
+static void vga_update_text(struct machine *machine, struct vga_data *d,
+	int x1, int y1, int x2, int y2)
+{
+	int fg, bg, x,y, subx, line;
+	size_t i, start, end, base;
+	int font_size = d->font_height;
+	int font_width = d->font_width;
+	unsigned char *pal = d->fb->rgb_palette;
+
+	if (d->pixel_repx * font_width > 8*8) {
+		fatal("[ too large font ]\n");
+		return;
+	}
+
+	/*  Hm... I'm still using the old start..end code:  */
+	start = (d->max_x * y1 + x1) * 2;
+	end   = (d->max_x * y2 + x2) * 2;
+
+	start &= ~1;
+	end |= 1;
+
+	if (end >= d->charcells_size)
+		end = d->charcells_size - 1;
+
+	base = ((d->crtc_reg[VGA_CRTC_START_ADDR_HIGH] << 8)
+	    + d->crtc_reg[VGA_CRTC_START_ADDR_LOW]) * 2;
+
+	if (!machine->x11_md.in_use)
+		vga_update_textmode(machine, d, base, start, end);
+
+	for (i=start; i<=end; i+=2) {
+		unsigned char ch = d->charcells[i + base];
+
+		if (!d->palette_modified && d->charcells_drawn[i] == ch &&
+		    d->charcells_drawn[i+1] == d->charcells[i+base+1])
+			continue;
+
+		d->charcells_drawn[i] = ch;
+		d->charcells_drawn[i+1] = d->charcells[i + base + 1];
+
+		fg = d->charcells[i+base + 1] & 15;
+		bg = (d->charcells[i+base + 1] >> 4) & 7;
+
+		/*  Blink is hard to do :-), but inversion might be ok too:  */
+		if (d->charcells[i+base + 1] & 128) {
+			int tmp = fg; fg = bg; bg = tmp;
+		}
+
+		x = (i/2) % d->max_x; x *= font_width;
+		y = (i/2) / d->max_x; y *= font_size;
+
+		/*  Draw the character:  */
+		for (line = 0; line < font_size; line++) {
+			/*  hardcoded for max 8 scaleup... :-)  */
+			unsigned char rgb_line[3 * 8 * 8];
+			int iy;
+
+			for (subx = 0; subx < font_width; subx++) {
+				int ix, color_index;
+
+				if (d->use_palette_per_line) {
+					int sline = d->pixel_repy * (line+y);
+					if (sline < MAX_RETRACE_SCANLINES)
+						pal = d->retrace_palette
+						    + sline * 256*3;
+					else
+						pal = d->fb->rgb_palette;
+				}
+
+				if (d->font[ch * font_size + line] &
+				    (128 >> subx))
+					color_index = fg;
+				else
+					color_index = bg;
+
+				for (ix=0; ix<d->pixel_repx; ix++)
+					memcpy(rgb_line + (subx*d->pixel_repx +
+					    ix) * 3, &pal[color_index * 3], 3);
+			}
+
+			for (iy=0; iy<d->pixel_repy; iy++) {
+				uint32_t addr = (d->fb_max_x * (d->pixel_repy *
+				    (line+y) + iy) + x * d->pixel_repx) * 3;
+				if (addr >= d->fb_size)
+					continue;
+				dev_fb_access(machine->cpus[0],
+				    machine->memory, addr, rgb_line,
+				    3 * machine->x11_md.scaleup * font_width,
+				    MEM_WRITE, d->fb);
+			}
+		}
+	}
+}
+
+
+/*
+ *  vga_update_cursor():
+ */
+static void vga_update_cursor(struct machine *machine, struct vga_data *d)
+{
+	int onoff = 1, height = d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_END]
+	    - d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_START] + 1;
+
+	if (d->cur_mode != MODE_CHARCELL)
+		onoff = 0;
+
+	if (d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_START] >
+	    d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_END]) {
+		onoff = 0;
+		height = 1;
+	}
+
+	if (d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_START] >= d->font_height)
+		onoff = 0;
+
+	dev_fb_setcursor(d->fb,
+	    d->cursor_x * d->font_width * d->pixel_repx, (d->cursor_y *
+	    d->font_height + d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_START]) *
+	    d->pixel_repy, onoff, d->font_width * d->pixel_repx, height *
+	    d->pixel_repy);
+}
+
+
+DEVICE_TICK(vga)
+{
+	struct vga_data *d = (struct vga_data *) extra;
+	int64_t low = -1, high;
+
+	vga_update_cursor(cpu->machine, d);
+
+	/*  TODO: text vs graphics tick?  */
+	memory_device_dyntrans_access(cpu, cpu->mem, extra,
+	    (uint64_t *) &low, (uint64_t *) &high);
+
+	if (low != -1) {
+		int base = ((d->crtc_reg[VGA_CRTC_START_ADDR_HIGH] << 8)
+		    + d->crtc_reg[VGA_CRTC_START_ADDR_LOW]) * 2;
+		int new_u_y1, new_u_y2;
+		debug("[ dev_vga_tick: dyntrans access, %" PRIx64" .. %"
+		    PRIx64" ]\n", (uint64_t) low, (uint64_t) high);
+		low -= base;
+		high -= base;
+		d->update_x1 = 0;
+		d->update_x2 = d->max_x - 1;
+		new_u_y1 = (low/2) / d->max_x;
+		new_u_y2 = ((high/2) / d->max_x) + 1;
+		if (new_u_y1 < d->update_y1)
+			d->update_y1 = new_u_y1;
+		if (new_u_y2 > d->update_y2)
+			d->update_y2 = new_u_y2;
+		if (d->update_y1 < 0)
+			d->update_y1 = 0;
+		if (d->update_y2 >= d->max_y)
+			d->update_y2 = d->max_y - 1;
+		d->modified = 1;
+	}
+
+	if (d->n_is1_reads > N_IS1_READ_THRESHOLD &&
+	    d->retrace_palette != NULL) {
+		d->use_palette_per_line = 1;
+		d->update_x1 = 0;
+		d->update_x2 = d->max_x - 1;
+		d->update_y1 = 0;
+		d->update_y2 = d->max_y - 1;
+		d->modified = 1;
+	} else {
+		if (d->use_palette_per_line) {
+			d->use_palette_per_line = 0;
+			d->update_x1 = 0;
+			d->update_x2 = d->max_x - 1;
+			d->update_y1 = 0;
+			d->update_y2 = d->max_y - 1;
+			d->modified = 1;
+		}
+	}
+
+	if (!cpu->machine->x11_md.in_use) {
+		/*  NOTE: 2 > 0, so this only updates the cursor, no
+		    character cells.  */
+		vga_update_textmode(cpu->machine, d, 0, 2, 0);
+	}
+
+	if (d->modified) {
+		if (d->cur_mode == MODE_CHARCELL)
+			vga_update_text(cpu->machine, d, d->update_x1,
+			    d->update_y1, d->update_x2, d->update_y2);
+		else
+			vga_update_graphics(cpu->machine, d, d->update_x1,
+			    d->update_y1, d->update_x2, d->update_y2);
+
+		d->palette_modified = 0;
+		d->modified = 0;
+		d->update_x1 = 999999;
+		d->update_x2 = -1;
+		d->update_y1 = 999999;
+		d->update_y2 = -1;
+	}
+
+	if (d->n_is1_reads > N_IS1_READ_THRESHOLD)
+		d->n_is1_reads = 0;
+}
+
+
+/*
+ *  Reads and writes to the VGA video memory (pixels).
+ */
+DEVICE_ACCESS(vga_graphics)
+{
+	struct vga_data *d = (struct vga_data *) extra;
+	int j, x=0, y=0, x2=0, y2=0, modified = 0;
+	size_t i;
+
+	if (relative_addr + len >= GFX_ADDR_WINDOW)
+		return 0;
+
+	if (d->cur_mode != MODE_GRAPHICS)
+		return 1;
+
+	switch (d->graphics_mode) {
+	case GRAPHICS_MODE_8BIT:
+		y = relative_addr / d->max_x;
+		x = relative_addr % d->max_x;
+		y2 = (relative_addr+len-1) / d->max_x;
+		x2 = (relative_addr+len-1) % d->max_x;
+
+		if (writeflag == MEM_WRITE) {
+			memcpy(d->gfx_mem + relative_addr, data, len);
+			modified = 1;
+		} else
+			memcpy(data, d->gfx_mem + relative_addr, len);
+		break;
+	case GRAPHICS_MODE_4BIT:
+		y = relative_addr * 8 / d->max_x;
+		x = relative_addr * 8 % d->max_x;
+		y2 = ((relative_addr+len)*8-1) / d->max_x;
+		x2 = ((relative_addr+len)*8-1) % d->max_x;
+		/*  TODO: color stuff  */
+
+		/*  Read/write d->gfx_mem in 4-bit color:  */
+		if (writeflag == MEM_WRITE) {
+			/*  i is byte index to write, j is bit index  */
+			for (i=0; i<len; i++)
+				for (j=0; j<8; j++) {
+					int pixelmask = 1 << (7-j);
+					int b = data[i] & pixelmask;
+					int m = d->sequencer_reg[
+					    VGA_SEQ_MAP_MASK] & 0x0f;
+					uint32_t addr = (y * d->max_x + x +
+					    i*8 + j) * d->bits_per_pixel / 8;
+					unsigned char byte;
+					if (!(d->graphcontr_reg[
+					    VGA_GRAPHCONTR_MASK] & pixelmask))
+						continue;
+					if (addr >= d->gfx_mem_size)
+						continue;
+					byte = d->gfx_mem[addr];
+					if (b && j&1)
+						byte |= m << 4;
+					if (b && !(j&1))
+						byte |= m;
+					if (!b && j&1)
+						byte &= ~(m << 4);
+					if (!b && !(j&1))
+						byte &= ~m;
+					d->gfx_mem[addr] = byte;
+				}
+			modified = 1;
+		} else {
+			fatal("TODO: 4 bit graphics read, mask=0x%02x\n",
+			    d->sequencer_reg[VGA_SEQ_MAP_MASK]);
+			for (i=0; i<len; i++)
+				data[i] = random();
+		}
+		break;
+	default:fatal("dev_vga: Unimplemented graphics mode %i\n",
+		    d->graphics_mode);
+		cpu->running = 0;
+	}
+
+	if (modified) {
+		d->modified = 1;
+		if (x < d->update_x1)  d->update_x1 = x;
+		if (x > d->update_x2)  d->update_x2 = x;
+		if (y < d->update_y1)  d->update_y1 = y;
+		if (y > d->update_y2)  d->update_y2 = y;
+		if (x2 < d->update_x1)  d->update_x1 = x2;
+		if (x2 > d->update_x2)  d->update_x2 = x2;
+		if (y2 < d->update_y1)  d->update_y1 = y2;
+		if (y2 > d->update_y2)  d->update_y2 = y2;
+		if (y != y2) {
+			d->update_x1 = 0;
+			d->update_x2 = d->max_x - 1;
+		}
+	}
+	return 1;
+}
+
+
+/*
+ *  Reads and writes the VGA video memory (charcells).
+ */
+DEVICE_ACCESS(vga)
+{
+	struct vga_data *d = (struct vga_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int x, y, x2, y2, r, base;
+	size_t i;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	base = ((d->crtc_reg[VGA_CRTC_START_ADDR_HIGH] << 8)
+	    + d->crtc_reg[VGA_CRTC_START_ADDR_LOW]) * 2;
+	r = relative_addr - base;
+	y = r / (d->max_x * 2);
+	x = (r/2) % d->max_x;
+	y2 = (r+len-1) / (d->max_x * 2);
+	x2 = ((r+len-1)/2) % d->max_x;
+
+	if (relative_addr + len - 1 < d->charcells_size) {
+		if (writeflag == MEM_WRITE) {
+			for (i=0; i<len; i++) {
+				int old = d->charcells[relative_addr + i];
+				if (old != data[i]) {
+					d->charcells[relative_addr + i] =
+					    data[i];
+					d->modified = 1;
+				}
+			}
+
+			if (d->modified) {
+				if (x < d->update_x1)  d->update_x1 = x;
+				if (x > d->update_x2)  d->update_x2 = x;
+				if (y < d->update_y1)  d->update_y1 = y;
+				if (y > d->update_y2)  d->update_y2 = y;
+				if (x2 < d->update_x1)  d->update_x1 = x2;
+				if (x2 > d->update_x2)  d->update_x2 = x2;
+				if (y2 < d->update_y1)  d->update_y1 = y2;
+				if (y2 > d->update_y2)  d->update_y2 = y2;
+
+				if (y != y2) {
+					d->update_x1 = 0;
+					d->update_x2 = d->max_x - 1;
+				}
+			}
+		} else
+			memcpy(data, d->charcells + relative_addr, len);
+		return 1;
+	}
+
+	switch (relative_addr) {
+	default:
+		if (writeflag==MEM_READ) {
+			debug("[ vga: read from 0x%08lx ]\n",
+			    (long)relative_addr);
+		} else {
+			debug("[ vga: write to  0x%08lx: 0x%08x ]\n",
+			    (long)relative_addr, idata);
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  vga_crtc_reg_write():
+ *
+ *  Writes to VGA CRTC registers.
+ */
+static void vga_crtc_reg_write(struct machine *machine, struct vga_data *d,
+	int regnr, int idata)
+{
+	int i, grayscale;
+
+	switch (regnr) {
+	case VGA_CRTC_CURSOR_SCANLINE_START:		/*  0x0a  */
+	case VGA_CRTC_CURSOR_SCANLINE_END:		/*  0x0b  */
+		break;
+	case VGA_CRTC_START_ADDR_HIGH:			/*  0x0c  */
+	case VGA_CRTC_START_ADDR_LOW:			/*  0x0d  */
+		d->update_x1 = 0;
+		d->update_x2 = d->max_x - 1;
+		d->update_y1 = 0;
+		d->update_y2 = d->max_y - 1;
+		d->modified = 1;
+		recalc_cursor_position(d);
+		break;
+	case VGA_CRTC_CURSOR_LOCATION_HIGH:		/*  0x0e  */
+	case VGA_CRTC_CURSOR_LOCATION_LOW:		/*  0x0f  */
+		recalc_cursor_position(d);
+		break;
+	case 0xff:
+		grayscale = 0;
+		switch (d->crtc_reg[0xff]) {
+		case 0x00:
+			grayscale = 1;
+			// fall through
+		case 0x01:
+			d->cur_mode = MODE_CHARCELL;
+			d->max_x = 40; d->max_y = 25;
+			d->pixel_repx = machine->x11_md.scaleup * 2;
+			d->pixel_repy = machine->x11_md.scaleup;
+			d->font_width = 8;
+			d->font_height = 16;
+			d->font = font8x16;
+			break;
+		case 0x02:
+			grayscale = 1;
+			// fall through
+		case 0x03:
+			d->cur_mode = MODE_CHARCELL;
+			d->max_x = 80; d->max_y = 25;
+			d->pixel_repx = d->pixel_repy = machine->x11_md.scaleup;
+			d->font_width = 8;
+			d->font_height = 16;
+			d->font = font8x16;
+			break;
+		case 0x08:
+			d->cur_mode = MODE_GRAPHICS;
+			d->max_x = 160;	d->max_y = 200;
+			d->graphics_mode = GRAPHICS_MODE_4BIT;
+			d->bits_per_pixel = 4;
+			d->pixel_repx = 4 * machine->x11_md.scaleup;
+			d->pixel_repy = 2 * machine->x11_md.scaleup;
+			break;
+		case 0x09:
+		case 0x0d:
+			d->cur_mode = MODE_GRAPHICS;
+			d->max_x = 320;	d->max_y = 200;
+			d->graphics_mode = GRAPHICS_MODE_4BIT;
+			d->bits_per_pixel = 4;
+			d->pixel_repx = d->pixel_repy =
+			    2 * machine->x11_md.scaleup;
+			break;
+		case 0x0e:
+			d->cur_mode = MODE_GRAPHICS;
+			d->max_x = 640;	d->max_y = 200;
+			d->graphics_mode = GRAPHICS_MODE_4BIT;
+			d->bits_per_pixel = 4;
+			d->pixel_repx = machine->x11_md.scaleup;
+			d->pixel_repy = machine->x11_md.scaleup * 2;
+			break;
+		case 0x10:
+			d->cur_mode = MODE_GRAPHICS;
+			d->max_x = 640; d->max_y = 350;
+			d->graphics_mode = GRAPHICS_MODE_4BIT;
+			d->bits_per_pixel = 4;
+			d->pixel_repx = d->pixel_repy = machine->x11_md.scaleup;
+			break;
+		case 0x12:
+			d->cur_mode = MODE_GRAPHICS;
+			d->max_x = 640; d->max_y = 480;
+			d->graphics_mode = GRAPHICS_MODE_4BIT;
+			d->bits_per_pixel = 4;
+			d->pixel_repx = d->pixel_repy = machine->x11_md.scaleup;
+			break;
+		case 0x13:
+			d->cur_mode = MODE_GRAPHICS;
+			d->max_x = 320;	d->max_y = 200;
+			d->graphics_mode = GRAPHICS_MODE_8BIT;
+			d->bits_per_pixel = 8;
+			d->pixel_repx = d->pixel_repy =
+			    2 * machine->x11_md.scaleup;
+			break;
+		default:
+			fatal("TODO! video mode change hack (mode 0x%02x)\n",
+			    d->crtc_reg[0xff]);
+			exit(1);
+		}
+
+		if (d->cur_mode == MODE_CHARCELL) {
+			dev_fb_resize(d->fb, d->max_x * d->font_width *
+			    d->pixel_repx, d->max_y * d->font_height *
+			    d->pixel_repy);
+			d->fb_size = d->max_x * d->pixel_repx * d->font_width *
+			     d->max_y * d->pixel_repy * d->font_height * 3;
+		} else {
+			dev_fb_resize(d->fb, d->max_x * d->pixel_repx,
+			    d->max_y * d->pixel_repy);
+			d->fb_size = d->max_x * d->pixel_repx *
+			     d->max_y * d->pixel_repy * 3;
+		}
+
+		for (i=0; i<machine->ncpus; i++)
+			machine->cpus[i]->invalidate_translation_caches(
+			    machine->cpus[i], 0, INVALIDATE_ALL);
+
+		if (d->gfx_mem != NULL)
+			free(d->gfx_mem);
+		d->gfx_mem_size = 1;
+		if (d->cur_mode == MODE_GRAPHICS)
+			d->gfx_mem_size = d->max_x * d->max_y /
+			    (d->graphics_mode == GRAPHICS_MODE_8BIT? 1 : 2);
+
+		CHECK_ALLOCATION(d->gfx_mem = (unsigned char *) malloc(d->gfx_mem_size));
+
+		/*  Clear screen and reset the palette:  */
+		memset(d->charcells_outputed, 0, d->charcells_size);
+		memset(d->charcells_drawn, 0, d->charcells_size);
+		memset(d->gfx_mem, 0, d->gfx_mem_size);
+		d->update_x1 = 0;
+		d->update_x2 = d->max_x - 1;
+		d->update_y1 = 0;
+		d->update_y2 = d->max_y - 1;
+		d->modified = 1;
+		reset_palette(d, grayscale);
+		register_reset(d);
+		break;
+	default:fatal("[ vga_crtc_reg_write: regnr=0x%02x idata=0x%02x ]\n",
+		    regnr, idata);
+	}
+}
+
+
+/*
+ *  vga_sequencer_reg_write():
+ *
+ *  Writes to VGA Sequencer registers.
+ */
+static void vga_sequencer_reg_write(struct machine *machine, struct vga_data *d,
+	int regnr, int idata)
+{
+	switch (regnr) {
+	case VGA_SEQ_RESET:
+	case VGA_SEQ_MAP_MASK:
+	case VGA_SEQ_SEQUENCER_MEMORY_MODE:
+		debug("[ vga_sequencer_reg_write: select %i: TODO ]\n", regnr);
+		break;
+	default:fatal("[ vga_sequencer_reg_write: select %i ]\n", regnr);
+		/*  cpu->running = 0;  */
+	}
+}
+
+
+/*
+ *  vga_graphcontr_reg_write():
+ *
+ *  Writes to VGA Graphics Controller registers.
+ */
+static void vga_graphcontr_reg_write(struct machine *machine,
+	struct vga_data *d, int regnr, int idata)
+{
+	switch (regnr) {
+	case VGA_GRAPHCONTR_READMAPSELECT:
+	case VGA_GRAPHCONTR_GRAPHICSMODE:
+	case VGA_GRAPHCONTR_MISC:
+	case VGA_GRAPHCONTR_MASK:
+		debug("[ vga_graphcontr_reg_write: select %i: TODO ]\n", regnr);
+		break;
+	default:fatal("[ vga_graphcontr_reg_write: select %i ]\n", regnr);
+		/*  cpu->running = 0;  */
+	}
+}
+
+
+/*
+ *  vga_attribute_reg_write():
+ *
+ *  Writes to VGA Attribute registers.
+ */
+static void vga_attribute_reg_write(struct machine *machine, struct vga_data *d,
+	int regnr, int idata)
+{
+	/*  0-15 are palette registers: TODO  */
+	if (regnr >= 0 && regnr <= 0xf)
+		return;
+
+	switch (regnr) {
+	default:fatal("[ vga_attribute_reg_write: select %i ]\n", regnr);
+		/*  cpu->running = 0;  */
+	}
+}
+
+
+/*
+ *  dev_vga_ctrl_access():
+ *
+ *  Reads and writes of the VGA control registers.
+ */
+DEVICE_ACCESS(vga_ctrl)
+{
+	struct vga_data *d = (struct vga_data *) extra;
+	size_t i;
+	uint64_t idata = 0, odata = 0;
+
+	for (i=0; i<len; i++) {
+		idata = data[i];
+
+		/*  0x3C0 + relative_addr...  */
+
+		switch (relative_addr) {
+
+		case VGA_ATTRIBUTE_ADDR:		/*  0x00  */
+			switch (d->attribute_state) {
+			case 0:	if (writeflag == MEM_READ)
+					odata = d->attribute_reg_select;
+				else {
+					d->attribute_reg_select = 1;
+					d->attribute_state = 1;
+				}
+				break;
+			case 1:	d->attribute_state = 0;
+				d->attribute_reg[d->attribute_reg_select] =
+				    idata;
+				vga_attribute_reg_write(cpu->machine, d,
+				    d->attribute_reg_select, idata);
+				break;
+			}
+			break;
+		case VGA_ATTRIBUTE_DATA_READ:		/*  0x01  */
+			if (writeflag == MEM_WRITE)
+				fatal("[ dev_vga: WARNING: Write to "
+				    "VGA_ATTRIBUTE_DATA_READ? ]\n");
+			else {
+				if (d->attribute_state == 0)
+					fatal("[ dev_vga: WARNING: Read from "
+					    "VGA_ATTRIBUTE_DATA_READ, but no"
+					    " register selected? ]\n");
+				else
+					odata = d->attribute_reg[
+					    d->attribute_reg_select];
+			}
+			break;
+
+		case VGA_MISC_OUTPUT_W:			/*  0x02  */
+			if (writeflag == MEM_WRITE)
+				d->misc_output_reg = idata;
+			else {
+				/*  Reads: Input Status 0  */
+				odata = 0x00;
+			}
+			break;
+
+		case VGA_SEQUENCER_ADDR:		/*  0x04  */
+			if (writeflag == MEM_READ)
+				odata = d->sequencer_reg_select;
+			else
+				d->sequencer_reg_select = idata;
+			break;
+		case VGA_SEQUENCER_DATA:		/*  0x05  */
+			if (writeflag == MEM_READ)
+				odata = d->sequencer_reg[
+				    d->sequencer_reg_select];
+			else {
+				d->sequencer_reg[d->
+				    sequencer_reg_select] = idata;
+				vga_sequencer_reg_write(cpu->machine, d,
+				    d->sequencer_reg_select, idata);
+			}
+			break;
+
+		case VGA_DAC_ADDR_READ:			/*  0x07  */
+			if (writeflag == MEM_WRITE) {
+				d->palette_read_index = idata;
+				d->palette_read_subindex = 0;
+			} else {
+				debug("[ dev_vga: WARNING: Read from "
+				    "VGA_DAC_ADDR_READ? TODO ]\n");
+				/*  TODO  */
+			}
+			break;
+		case VGA_DAC_ADDR_WRITE:		/*  0x08  */
+			if (writeflag == MEM_WRITE) {
+				d->palette_write_index = idata;
+				d->palette_write_subindex = 0;
+
+				/*  TODO: Is this correct?  */
+				d->palette_read_index = idata;
+				d->palette_read_subindex = 0;
+			} else {
+				fatal("[ dev_vga: WARNING: Read from "
+				    "VGA_DAC_ADDR_WRITE? ]\n");
+				odata = d->palette_write_index;
+			}
+			break;
+		case VGA_DAC_DATA:			/*  0x09  */
+			if (writeflag == MEM_WRITE) {
+				int new_ = (idata & 63) << 2;
+				int old = d->fb->rgb_palette[d->
+				    palette_write_index*3+d->
+				    palette_write_subindex];
+				d->fb->rgb_palette[d->palette_write_index * 3 +
+				    d->palette_write_subindex] = new_;
+				/*  Redraw whole screen, if the
+				    palette changed:  */
+				if (new_ != old) {
+					d->modified = 1;
+					d->palette_modified = 1;
+					d->update_x1 = d->update_y1 = 0;
+					d->update_x2 = d->max_x - 1;
+					d->update_y2 = d->max_y - 1;
+				}
+				d->palette_write_subindex ++;
+				if (d->palette_write_subindex == 3) {
+					d->palette_write_index ++;
+					d->palette_write_subindex = 0;
+				}
+			} else {
+				odata = (d->fb->rgb_palette[d->
+				    palette_read_index * 3 +
+				    d->palette_read_subindex] >> 2) & 63;
+				d->palette_read_subindex ++;
+				if (d->palette_read_subindex == 3) {
+					d->palette_read_index ++;
+					d->palette_read_subindex = 0;
+				}
+			}
+			break;
+
+		case VGA_MISC_OUTPUT_R:
+			odata = d->misc_output_reg;
+			break;
+
+		case VGA_GRAPHCONTR_ADDR:		/*  0x0e  */
+			if (writeflag == MEM_READ)
+				odata = d->graphcontr_reg_select;
+			else
+				d->graphcontr_reg_select = idata;
+			break;
+		case VGA_GRAPHCONTR_DATA:		/*  0x0f  */
+			if (writeflag == MEM_READ)
+				odata = d->graphcontr_reg[
+				    d->graphcontr_reg_select];
+			else {
+				d->graphcontr_reg[d->
+				    graphcontr_reg_select] = idata;
+				vga_graphcontr_reg_write(cpu->machine, d,
+				    d->graphcontr_reg_select, idata);
+			}
+			break;
+
+		case VGA_CRTC_ADDR:			/*  0x14  */
+			if (writeflag == MEM_READ)
+				odata = d->crtc_reg_select;
+			else
+				d->crtc_reg_select = idata;
+			break;
+		case VGA_CRTC_DATA:			/*  0x15  */
+			if (writeflag == MEM_READ)
+				odata = d->crtc_reg[d->crtc_reg_select];
+			else {
+				d->crtc_reg[d->crtc_reg_select] = idata;
+				vga_crtc_reg_write(cpu->machine, d,
+				    d->crtc_reg_select, idata);
+			}
+			break;
+
+		case VGA_INPUT_STATUS_1:	/*  0x1A  */
+			odata = 0;
+			d->n_is1_reads ++;
+			d->current_retrace_line ++;
+			d->current_retrace_line %= (MAX_RETRACE_SCANLINES * 8);
+			/*  Whenever we are "inside" a scan line, copy the
+			    current palette into retrace_palette[][]:  */
+			if ((d->current_retrace_line & 7) == 7) {
+				if (d->retrace_palette == NULL &&
+				    d->n_is1_reads > N_IS1_READ_THRESHOLD) {
+					CHECK_ALLOCATION(d->retrace_palette =
+					    (unsigned char *) malloc(
+					    MAX_RETRACE_SCANLINES * 256*3));
+				}
+				if (d->retrace_palette != NULL)
+					memcpy(d->retrace_palette + (d->
+					    current_retrace_line >> 3) * 256*3,
+					    d->fb->rgb_palette, d->cur_mode ==
+					    MODE_CHARCELL? (16*3) : (256*3));
+			}
+			/*  These need to go on and off, to fake the
+			    real vertical and horizontal retrace info.  */
+			if (d->current_retrace_line < 20*8)
+				odata |= VGA_IS1_DISPLAY_VRETRACE;
+			else {
+				if ((d->current_retrace_line & 7) == 0)
+					odata = VGA_IS1_DISPLAY_DISPLAY_DISABLE;
+			}
+			break;
+
+		default:
+			if (writeflag==MEM_READ) {
+				debug("[ vga_ctrl: read from 0x%08lx ]\n",
+				    (long)relative_addr);
+			} else {
+				debug("[ vga_ctrl: write to  0x%08lx: 0x%08x"
+				    " ]\n", (long)relative_addr, (int)idata);
+			}
+		}
+
+		if (writeflag == MEM_READ)
+			data[i] = odata;
+
+		/*  For multi-byte accesses:  */
+		relative_addr ++;
+	}
+
+	return 1;
+}
+
+
+/*
+ *  dev_vga_init():
+ *
+ *  Register a VGA text console device. max_x and max_y could be something
+ *  like 80 and 25, respectively.
+ */
+void dev_vga_init(struct machine *machine, struct memory *mem,
+	uint64_t videomem_base, uint64_t control_base, const char *name)
+{
+	struct vga_data *d;
+	size_t allocsize, i;
+
+	CHECK_ALLOCATION(d = (struct vga_data *) malloc(sizeof(struct vga_data)));
+	memset(d, 0, sizeof(struct vga_data));
+
+	d->console_handle = console_start_slave(machine, "vga",
+	    CONSOLE_OUTPUT_ONLY);
+
+	d->videomem_base  = videomem_base;
+	d->control_base   = control_base;
+	d->max_x          = 80;
+	d->max_y          = 25;
+	d->cur_mode       = MODE_CHARCELL;
+	d->crtc_reg[0xff] = 0x03;
+	d->charcells_size = 0x8000;
+	d->gfx_mem_size   = 64;	/*  Nothing, as we start in text mode,
+			but size large enough to make gfx_mem aligned.  */
+	d->pixel_repx = d->pixel_repy = machine->x11_md.scaleup;
+
+	/*  Allocate in full pages, to make it possible to use dyntrans:  */
+	allocsize = ((d->charcells_size-1) | (machine->arch_pagesize-1)) + 1;
+	CHECK_ALLOCATION(d->charcells = (unsigned char *) malloc(d->charcells_size));
+	CHECK_ALLOCATION(d->charcells_outputed = (unsigned char *) malloc(d->charcells_size));
+	CHECK_ALLOCATION(d->charcells_drawn = (unsigned char *) malloc(d->charcells_size));
+	CHECK_ALLOCATION(d->gfx_mem = (unsigned char *) malloc(d->gfx_mem_size));
+
+	memset(d->charcells_drawn, 0, d->charcells_size);
+
+	for (i=0; i<d->charcells_size; i+=2) {
+		d->charcells[i] = ' ';
+		d->charcells[i+1] = 0x07;  /*  Default color  */
+		d->charcells_drawn[i] = ' ';
+		d->charcells_drawn[i+1] = 0x07;
+	}
+
+	memset(d->charcells_outputed, 0, d->charcells_size);
+	memset(d->gfx_mem, 0, d->gfx_mem_size);
+
+	d->font = font8x16;
+	d->font_width  = 8;
+	d->font_height = 16;
+
+	d->fb_max_x = d->pixel_repx * d->max_x;
+	d->fb_max_y = d->pixel_repy * d->max_y;
+	if (d->cur_mode == MODE_CHARCELL) {
+		d->fb_max_x *= d->font_width;
+		d->fb_max_y *= d->font_height;
+	}
+
+	memory_device_register(mem, "vga_charcells", videomem_base + 0x18000,
+	    allocsize, dev_vga_access, d, DM_DYNTRANS_OK |
+	    DM_DYNTRANS_WRITE_OK | DM_READS_HAVE_NO_SIDE_EFFECTS,
+	    d->charcells);
+	memory_device_register(mem, "vga_gfx", videomem_base, GFX_ADDR_WINDOW,
+	    dev_vga_graphics_access, d, DM_DEFAULT |
+	    DM_READS_HAVE_NO_SIDE_EFFECTS, d->gfx_mem);
+	memory_device_register(mem, "vga_ctrl", control_base,
+	    32, dev_vga_ctrl_access, d, DM_DEFAULT, NULL);
+
+	d->fb = dev_fb_init(machine, mem, VGA_FB_ADDR, VFB_GENERIC,
+	    d->fb_max_x, d->fb_max_y, d->fb_max_x, d->fb_max_y, 24, "VGA");
+	d->fb_size = d->fb_max_x * d->fb_max_y * 3;
+
+	reset_palette(d, 0);
+
+	/*  This will force an initial redraw/resynch:  */
+	d->update_x1 = 0;
+	d->update_x2 = d->max_x - 1;
+	d->update_y1 = 0;
+	d->update_y2 = d->max_y - 1;
+	d->modified = 1;
+
+	machine_add_tickfunction(machine, dev_vga_tick, d, VGA_TICK_SHIFT);
+
+	register_reset(d);
+
+	vga_update_cursor(machine, d);
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_vga.cc gxemul-0.7.0+dfsg/src/devices/dev_vga.cc
--- gxemul-0.6.2/src/devices/dev_vga.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_vga.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1269 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: VGA framebuffer device (charcell and graphics modes)
- *
- *  It should work with 80x25 and 40x25 text modes, and with a few graphics
- *  modes as long as no fancy VGA features are used.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "../include/vga.h"
-
-/*  These are generated from binary font files:  */
-#include "fonts/font8x8.cc"
-#include "fonts/font8x10.cc"
-#include "fonts/font8x16.cc"
-
-
-/*  For videomem -> framebuffer updates:  */
-#define	VGA_TICK_SHIFT		18
-
-#define	MAX_RETRACE_SCANLINES	420
-#define	N_IS1_READ_THRESHOLD	50
-
-#define	GFX_ADDR_WINDOW		0x18000
-
-#define	VGA_FB_ADDR	0x1c00000000ULL
-
-#define	MODE_CHARCELL		1
-#define	MODE_GRAPHICS		2
-
-#define	GRAPHICS_MODE_8BIT	1
-#define	GRAPHICS_MODE_4BIT	2
-
-struct vga_data {
-	uint64_t	videomem_base;
-	uint64_t	control_base;
-
-	struct vfb_data *fb;
-	uint32_t	fb_size;
-
-	int		fb_max_x;		/*  pixels  */
-	int		fb_max_y;		/*  pixels  */
-	int		max_x;			/*  charcells or pixels  */
-	int		max_y;			/*  charcells or pixels  */
-
-	/*  Selects charcell mode or graphics mode:  */
-	int		cur_mode;
-
-	/*  Common for text and graphics modes:  */
-	int		pixel_repx, pixel_repy;
-
-	/*  Textmode:  */
-	int		font_width;
-	int		font_height;
-	unsigned char	*font;
-	size_t		charcells_size;
-	unsigned char	*charcells;		/*  2 bytes per char  */
-	unsigned char	*charcells_outputed;	/*  text  */
-	unsigned char	*charcells_drawn;	/*  framebuffer  */
-
-	/*  Graphics:  */
-	int		graphics_mode;
-	int		bits_per_pixel;
-	unsigned char	*gfx_mem;
-	uint32_t	gfx_mem_size;
-
-	/*  Registers:  */
-	int		attribute_state;	/*  0 or 1  */
-	unsigned char	attribute_reg_select;
-	unsigned char	attribute_reg[256];
-
-	unsigned char	misc_output_reg;
-
-	unsigned char	sequencer_reg_select;
-	unsigned char	sequencer_reg[256];
-
-	unsigned char	graphcontr_reg_select;
-	unsigned char	graphcontr_reg[256];
-
-	unsigned char	crtc_reg_select;
-	unsigned char	crtc_reg[256];
-
-	unsigned char	palette_read_index;
-	char		palette_read_subindex;
-	unsigned char	palette_write_index;
-	char		palette_write_subindex;
-
-	int		current_retrace_line;
-	int		input_status_1;
-
-	/*  Palette per scanline during retrace:  */
-	unsigned char	*retrace_palette;
-	int		use_palette_per_line;
-	int64_t		n_is1_reads;
-
-	/*  Misc.:  */
-	int		console_handle;
-
-	int		cursor_x;
-	int		cursor_y;
-
-	int		modified;
-	int		palette_modified;
-	int		update_x1;
-	int		update_y1;
-	int		update_x2;
-	int		update_y2;
-};
-
-
-/*
- *  recalc_cursor_position():
- *
- *  Should be called whenever the cursor location _or_ the display
- *  base has been changed.
- */
-static void recalc_cursor_position(struct vga_data *d)
-{
-	int base = (d->crtc_reg[VGA_CRTC_START_ADDR_HIGH] << 8)
-	    + d->crtc_reg[VGA_CRTC_START_ADDR_LOW];
-	int ofs = d->crtc_reg[VGA_CRTC_CURSOR_LOCATION_HIGH] * 256 +
-	    d->crtc_reg[VGA_CRTC_CURSOR_LOCATION_LOW];
-	ofs -= base;
-	d->cursor_x = ofs % d->max_x;
-	d->cursor_y = ofs / d->max_x;
-}
-
-
-/*
- *  register_reset():
- *
- *  Resets many registers to sane values.
- */
-static void register_reset(struct vga_data *d)
-{
-	/*  Home cursor and start at the top:  */
-	d->crtc_reg[VGA_CRTC_CURSOR_LOCATION_HIGH] =
-	    d->crtc_reg[VGA_CRTC_CURSOR_LOCATION_LOW] = 0;
-	d->crtc_reg[VGA_CRTC_START_ADDR_HIGH] =
-	    d->crtc_reg[VGA_CRTC_START_ADDR_LOW] = 0;
-
-	recalc_cursor_position(d);
-
-	/*  Reset cursor scanline stuff:  */
-	d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_START] = d->font_height - 2;
-	d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_END] = d->font_height - 1;
-
-	d->sequencer_reg[VGA_SEQ_MAP_MASK] = 0x0f;
-	d->graphcontr_reg[VGA_GRAPHCONTR_MASK] = 0xff;
-
-	d->misc_output_reg = VGA_MISC_OUTPUT_IOAS;
-	d->n_is1_reads = 0;
-}
-
-
-static void c_putstr(struct vga_data *d, const char *s)
-{
-	while (*s)
-		console_putchar(d->console_handle, *s++);
-}
-
-
-/*
- *  reset_palette():
- */
-static void reset_palette(struct vga_data *d, int grayscale)
-{
-	int i, r, g, b;
-
-	/*  TODO: default values for entry 16..255?  */
-	for (i=16; i<256; i++)
-		d->fb->rgb_palette[i*3 + 0] = d->fb->rgb_palette[i*3 + 1] =
-		    d->fb->rgb_palette[i*3 + 2] = (i & 15) * 4;
-	d->palette_modified = 1;
-	i = 0;
-
-	if (grayscale) {
-		for (r=0; r<2; r++)
-		    for (g=0; g<2; g++)
-			for (b=0; b<2; b++) {
-				d->fb->rgb_palette[i + 0] =
-				    d->fb->rgb_palette[i + 1] =
-				    d->fb->rgb_palette[i + 2] =
-				    (r+g+b) * 0xaa / 3;
-				d->fb->rgb_palette[i + 8*3 + 0] =
-				    d->fb->rgb_palette[i + 8*3 + 1] =
-				    d->fb->rgb_palette[i + 8*3 + 2] =
-				    (r+g+b) * 0xaa / 3 + 0x55;
-				i+=3;
-			}
-		return;
-	}
-
-	for (r=0; r<2; r++)
-		for (g=0; g<2; g++)
-			for (b=0; b<2; b++) {
-				d->fb->rgb_palette[i + 0] = r * 0xaa;
-				d->fb->rgb_palette[i + 1] = g * 0xaa;
-				d->fb->rgb_palette[i + 2] = b * 0xaa;
-				i+=3;
-			}
-	for (r=0; r<2; r++)
-		for (g=0; g<2; g++)
-			for (b=0; b<2; b++) {
-				d->fb->rgb_palette[i + 0] = r * 0xaa + 0x55;
-				d->fb->rgb_palette[i + 1] = g * 0xaa + 0x55;
-				d->fb->rgb_palette[i + 2] = b * 0xaa + 0x55;
-				i+=3;
-			}
-}
-
-
-/*
- *  vga_update_textmode():
- *
- *  Called from vga_update() when x11 in_use is false. This causes modified
- *  character cells to be "simulated" by outputing ANSI escape sequences
- *  that draw the characters in a terminal window instead.
- */
-static void vga_update_textmode(struct machine *machine,
-	struct vga_data *d, int base, int start, int end)
-{
-	char s[50];
-	int i, oldcolor = -1, printed_last = 0;
-
-	for (i=start; i<=end; i+=2) {
-		unsigned char ch = d->charcells[base+i];
-		int fg = d->charcells[base+i+1] & 15;
-		int bg = (d->charcells[base+i+1] >> 4) & 15;
-			/*  top bit of bg = blink  */
-		int x = (i/2) % d->max_x;
-		int y = (i/2) / d->max_x;
-
-		if (d->charcells[base+i] == d->charcells_outputed[i] &&
-		    d->charcells[base+i+1] == d->charcells_outputed[i+1]) {
-			printed_last = 0;
-			continue;
-		}
-
-		d->charcells_outputed[i] = d->charcells[base+i];
-		d->charcells_outputed[i+1] = d->charcells[base+i+1];
-
-		if (!printed_last || x == 0) {
-			snprintf(s, sizeof(s), "\033[%i;%iH", y + 1, x + 1);
-			c_putstr(d, s);
-		}
-		if (oldcolor < 0 || (bg<<4)+fg != oldcolor || !printed_last) {
-			snprintf(s, sizeof(s), "\033[0;"); c_putstr(d, s);
-
-			switch (fg & 7) {
-			case 0:	c_putstr(d, "30"); break;
-			case 1:	c_putstr(d, "34"); break;
-			case 2:	c_putstr(d, "32"); break;
-			case 3:	c_putstr(d, "36"); break;
-			case 4:	c_putstr(d, "31"); break;
-			case 5:	c_putstr(d, "35"); break;
-			case 6:	c_putstr(d, "33"); break;
-			case 7:	c_putstr(d, "37"); break;
-			}
-			if (fg & 8)
-				c_putstr(d, ";1");
-			c_putstr(d, ";");
-			switch (bg & 7) {
-			case 0:	c_putstr(d, "40"); break;
-			case 1:	c_putstr(d, "44"); break;
-			case 2:	c_putstr(d, "42"); break;
-			case 3:	c_putstr(d, "46"); break;
-			case 4:	c_putstr(d, "41"); break;
-			case 5:	c_putstr(d, "45"); break;
-			case 6:	c_putstr(d, "43"); break;
-			case 7:	c_putstr(d, "47"); break;
-			}
-			/*  TODO: blink  */
-			c_putstr(d, "m");
-		}
-
-		if (ch >= 0x20 && ch != 127)
-			console_putchar(d->console_handle, ch);
-
-		oldcolor = (bg << 4) + fg;
-		printed_last = 1;
-	}
-
-	/*  Restore the terminal's cursor position:  */
-	snprintf(s, sizeof(s), "\033[%i;%iH", d->cursor_y + 1, d->cursor_x + 1);
-	c_putstr(d, s);
-}
-
-
-/*
- *  vga_update_graphics():
- *
- *  This function should be called whenever any part of d->gfx_mem[] has
- *  been written to. It will redraw all pixels within the range x1,y1
- *  .. x2,y2 using the right palette.
- */
-static void vga_update_graphics(struct machine *machine, struct vga_data *d,
-	int x1, int y1, int x2, int y2)
-{
-	int x, y, ix, iy, c, rx = d->pixel_repx, ry = d->pixel_repy;
-	unsigned char pixel[3];
-
-	for (y=y1; y<=y2; y++)
-		for (x=x1; x<=x2; x++) {
-			/*  addr is where to read from VGA memory, addr2 is
-			    where to write on the 24-bit framebuffer device  */
-			int addr = (y * d->max_x + x) * d->bits_per_pixel;
-			switch (d->bits_per_pixel) {
-			case 8:	addr >>= 3;
-				c = d->gfx_mem[addr];
-				pixel[0] = d->fb->rgb_palette[c*3+0];
-				pixel[1] = d->fb->rgb_palette[c*3+1];
-				pixel[2] = d->fb->rgb_palette[c*3+2];
-				break;
-			case 4:	addr >>= 2;
-				if (addr & 1)
-					c = d->gfx_mem[addr >> 1] >> 4;
-				else
-					c = d->gfx_mem[addr >> 1] & 0xf;
-				pixel[0] = d->fb->rgb_palette[c*3+0];
-				pixel[1] = d->fb->rgb_palette[c*3+1];
-				pixel[2] = d->fb->rgb_palette[c*3+2];
-				break;
-			}
-			for (iy=y*ry; iy<(y+1)*ry; iy++)
-				for (ix=x*rx; ix<(x+1)*rx; ix++) {
-					uint32_t addr2 = (d->fb_max_x * iy
-					    + ix) * 3;
-					if (addr2 < d->fb_size)
-						dev_fb_access(machine->cpus[0],
-						    machine->memory, addr2,
-						    pixel, sizeof(pixel),
-						    MEM_WRITE, d->fb);
-				}
-		}
-}
-
-
-/*
- *  vga_update_text():
- *
- *  This function should be called whenever any part of d->charcells[] has
- *  been written to. It will redraw all characters within the range x1,y1
- *  .. x2,y2 using the right palette.
- */
-static void vga_update_text(struct machine *machine, struct vga_data *d,
-	int x1, int y1, int x2, int y2)
-{
-	int fg, bg, x,y, subx, line;
-	size_t i, start, end, base;
-	int font_size = d->font_height;
-	int font_width = d->font_width;
-	unsigned char *pal = d->fb->rgb_palette;
-
-	if (d->pixel_repx * font_width > 8*8) {
-		fatal("[ too large font ]\n");
-		return;
-	}
-
-	/*  Hm... I'm still using the old start..end code:  */
-	start = (d->max_x * y1 + x1) * 2;
-	end   = (d->max_x * y2 + x2) * 2;
-
-	start &= ~1;
-	end |= 1;
-
-	if (end >= d->charcells_size)
-		end = d->charcells_size - 1;
-
-	base = ((d->crtc_reg[VGA_CRTC_START_ADDR_HIGH] << 8)
-	    + d->crtc_reg[VGA_CRTC_START_ADDR_LOW]) * 2;
-
-	if (!machine->x11_md.in_use)
-		vga_update_textmode(machine, d, base, start, end);
-
-	for (i=start; i<=end; i+=2) {
-		unsigned char ch = d->charcells[i + base];
-
-		if (!d->palette_modified && d->charcells_drawn[i] == ch &&
-		    d->charcells_drawn[i+1] == d->charcells[i+base+1])
-			continue;
-
-		d->charcells_drawn[i] = ch;
-		d->charcells_drawn[i+1] = d->charcells[i + base + 1];
-
-		fg = d->charcells[i+base + 1] & 15;
-		bg = (d->charcells[i+base + 1] >> 4) & 7;
-
-		/*  Blink is hard to do :-), but inversion might be ok too:  */
-		if (d->charcells[i+base + 1] & 128) {
-			int tmp = fg; fg = bg; bg = tmp;
-		}
-
-		x = (i/2) % d->max_x; x *= font_width;
-		y = (i/2) / d->max_x; y *= font_size;
-
-		/*  Draw the character:  */
-		for (line = 0; line < font_size; line++) {
-			/*  hardcoded for max 8 scaleup... :-)  */
-			unsigned char rgb_line[3 * 8 * 8];
-			int iy;
-
-			for (subx = 0; subx < font_width; subx++) {
-				int ix, color_index;
-
-				if (d->use_palette_per_line) {
-					int sline = d->pixel_repy * (line+y);
-					if (sline < MAX_RETRACE_SCANLINES)
-						pal = d->retrace_palette
-						    + sline * 256*3;
-					else
-						pal = d->fb->rgb_palette;
-				}
-
-				if (d->font[ch * font_size + line] &
-				    (128 >> subx))
-					color_index = fg;
-				else
-					color_index = bg;
-
-				for (ix=0; ix<d->pixel_repx; ix++)
-					memcpy(rgb_line + (subx*d->pixel_repx +
-					    ix) * 3, &pal[color_index * 3], 3);
-			}
-
-			for (iy=0; iy<d->pixel_repy; iy++) {
-				uint32_t addr = (d->fb_max_x * (d->pixel_repy *
-				    (line+y) + iy) + x * d->pixel_repx) * 3;
-				if (addr >= d->fb_size)
-					continue;
-				dev_fb_access(machine->cpus[0],
-				    machine->memory, addr, rgb_line,
-				    3 * machine->x11_md.scaleup * font_width,
-				    MEM_WRITE, d->fb);
-			}
-		}
-	}
-}
-
-
-/*
- *  vga_update_cursor():
- */
-static void vga_update_cursor(struct machine *machine, struct vga_data *d)
-{
-	int onoff = 1, height = d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_END]
-	    - d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_START] + 1;
-
-	if (d->cur_mode != MODE_CHARCELL)
-		onoff = 0;
-
-	if (d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_START] >
-	    d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_END]) {
-		onoff = 0;
-		height = 1;
-	}
-
-	if (d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_START] >= d->font_height)
-		onoff = 0;
-
-	dev_fb_setcursor(d->fb,
-	    d->cursor_x * d->font_width * d->pixel_repx, (d->cursor_y *
-	    d->font_height + d->crtc_reg[VGA_CRTC_CURSOR_SCANLINE_START]) *
-	    d->pixel_repy, onoff, d->font_width * d->pixel_repx, height *
-	    d->pixel_repy);
-}
-
-
-DEVICE_TICK(vga)
-{
-	struct vga_data *d = (struct vga_data *) extra;
-	int64_t low = -1, high;
-
-	vga_update_cursor(cpu->machine, d);
-
-	/*  TODO: text vs graphics tick?  */
-	memory_device_dyntrans_access(cpu, cpu->mem, extra,
-	    (uint64_t *) &low, (uint64_t *) &high);
-
-	if (low != -1) {
-		int base = ((d->crtc_reg[VGA_CRTC_START_ADDR_HIGH] << 8)
-		    + d->crtc_reg[VGA_CRTC_START_ADDR_LOW]) * 2;
-		int new_u_y1, new_u_y2;
-		debug("[ dev_vga_tick: dyntrans access, %" PRIx64" .. %"
-		    PRIx64" ]\n", (uint64_t) low, (uint64_t) high);
-		low -= base;
-		high -= base;
-		d->update_x1 = 0;
-		d->update_x2 = d->max_x - 1;
-		new_u_y1 = (low/2) / d->max_x;
-		new_u_y2 = ((high/2) / d->max_x) + 1;
-		if (new_u_y1 < d->update_y1)
-			d->update_y1 = new_u_y1;
-		if (new_u_y2 > d->update_y2)
-			d->update_y2 = new_u_y2;
-		if (d->update_y1 < 0)
-			d->update_y1 = 0;
-		if (d->update_y2 >= d->max_y)
-			d->update_y2 = d->max_y - 1;
-		d->modified = 1;
-	}
-
-	if (d->n_is1_reads > N_IS1_READ_THRESHOLD &&
-	    d->retrace_palette != NULL) {
-		d->use_palette_per_line = 1;
-		d->update_x1 = 0;
-		d->update_x2 = d->max_x - 1;
-		d->update_y1 = 0;
-		d->update_y2 = d->max_y - 1;
-		d->modified = 1;
-	} else {
-		if (d->use_palette_per_line) {
-			d->use_palette_per_line = 0;
-			d->update_x1 = 0;
-			d->update_x2 = d->max_x - 1;
-			d->update_y1 = 0;
-			d->update_y2 = d->max_y - 1;
-			d->modified = 1;
-		}
-	}
-
-	if (!cpu->machine->x11_md.in_use) {
-		/*  NOTE: 2 > 0, so this only updates the cursor, no
-		    character cells.  */
-		vga_update_textmode(cpu->machine, d, 0, 2, 0);
-	}
-
-	if (d->modified) {
-		if (d->cur_mode == MODE_CHARCELL)
-			vga_update_text(cpu->machine, d, d->update_x1,
-			    d->update_y1, d->update_x2, d->update_y2);
-		else
-			vga_update_graphics(cpu->machine, d, d->update_x1,
-			    d->update_y1, d->update_x2, d->update_y2);
-
-		d->palette_modified = 0;
-		d->modified = 0;
-		d->update_x1 = 999999;
-		d->update_x2 = -1;
-		d->update_y1 = 999999;
-		d->update_y2 = -1;
-	}
-
-	if (d->n_is1_reads > N_IS1_READ_THRESHOLD)
-		d->n_is1_reads = 0;
-}
-
-
-/*
- *  Reads and writes to the VGA video memory (pixels).
- */
-DEVICE_ACCESS(vga_graphics)
-{
-	struct vga_data *d = (struct vga_data *) extra;
-	int j, x=0, y=0, x2=0, y2=0, modified = 0;
-	size_t i;
-
-	if (relative_addr + len >= GFX_ADDR_WINDOW)
-		return 0;
-
-	if (d->cur_mode != MODE_GRAPHICS)
-		return 1;
-
-	switch (d->graphics_mode) {
-	case GRAPHICS_MODE_8BIT:
-		y = relative_addr / d->max_x;
-		x = relative_addr % d->max_x;
-		y2 = (relative_addr+len-1) / d->max_x;
-		x2 = (relative_addr+len-1) % d->max_x;
-
-		if (writeflag == MEM_WRITE) {
-			memcpy(d->gfx_mem + relative_addr, data, len);
-			modified = 1;
-		} else
-			memcpy(data, d->gfx_mem + relative_addr, len);
-		break;
-	case GRAPHICS_MODE_4BIT:
-		y = relative_addr * 8 / d->max_x;
-		x = relative_addr * 8 % d->max_x;
-		y2 = ((relative_addr+len)*8-1) / d->max_x;
-		x2 = ((relative_addr+len)*8-1) % d->max_x;
-		/*  TODO: color stuff  */
-
-		/*  Read/write d->gfx_mem in 4-bit color:  */
-		if (writeflag == MEM_WRITE) {
-			/*  i is byte index to write, j is bit index  */
-			for (i=0; i<len; i++)
-				for (j=0; j<8; j++) {
-					int pixelmask = 1 << (7-j);
-					int b = data[i] & pixelmask;
-					int m = d->sequencer_reg[
-					    VGA_SEQ_MAP_MASK] & 0x0f;
-					uint32_t addr = (y * d->max_x + x +
-					    i*8 + j) * d->bits_per_pixel / 8;
-					unsigned char byte;
-					if (!(d->graphcontr_reg[
-					    VGA_GRAPHCONTR_MASK] & pixelmask))
-						continue;
-					if (addr >= d->gfx_mem_size)
-						continue;
-					byte = d->gfx_mem[addr];
-					if (b && j&1)
-						byte |= m << 4;
-					if (b && !(j&1))
-						byte |= m;
-					if (!b && j&1)
-						byte &= ~(m << 4);
-					if (!b && !(j&1))
-						byte &= ~m;
-					d->gfx_mem[addr] = byte;
-				}
-			modified = 1;
-		} else {
-			fatal("TODO: 4 bit graphics read, mask=0x%02x\n",
-			    d->sequencer_reg[VGA_SEQ_MAP_MASK]);
-			for (i=0; i<len; i++)
-				data[i] = random();
-		}
-		break;
-	default:fatal("dev_vga: Unimplemented graphics mode %i\n",
-		    d->graphics_mode);
-		cpu->running = 0;
-	}
-
-	if (modified) {
-		d->modified = 1;
-		if (x < d->update_x1)  d->update_x1 = x;
-		if (x > d->update_x2)  d->update_x2 = x;
-		if (y < d->update_y1)  d->update_y1 = y;
-		if (y > d->update_y2)  d->update_y2 = y;
-		if (x2 < d->update_x1)  d->update_x1 = x2;
-		if (x2 > d->update_x2)  d->update_x2 = x2;
-		if (y2 < d->update_y1)  d->update_y1 = y2;
-		if (y2 > d->update_y2)  d->update_y2 = y2;
-		if (y != y2) {
-			d->update_x1 = 0;
-			d->update_x2 = d->max_x - 1;
-		}
-	}
-	return 1;
-}
-
-
-/*
- *  Reads and writes the VGA video memory (charcells).
- */
-DEVICE_ACCESS(vga)
-{
-	struct vga_data *d = (struct vga_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int x, y, x2, y2, r, base;
-	size_t i;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	base = ((d->crtc_reg[VGA_CRTC_START_ADDR_HIGH] << 8)
-	    + d->crtc_reg[VGA_CRTC_START_ADDR_LOW]) * 2;
-	r = relative_addr - base;
-	y = r / (d->max_x * 2);
-	x = (r/2) % d->max_x;
-	y2 = (r+len-1) / (d->max_x * 2);
-	x2 = ((r+len-1)/2) % d->max_x;
-
-	if (relative_addr + len - 1 < d->charcells_size) {
-		if (writeflag == MEM_WRITE) {
-			for (i=0; i<len; i++) {
-				int old = d->charcells[relative_addr + i];
-				if (old != data[i]) {
-					d->charcells[relative_addr + i] =
-					    data[i];
-					d->modified = 1;
-				}
-			}
-
-			if (d->modified) {
-				if (x < d->update_x1)  d->update_x1 = x;
-				if (x > d->update_x2)  d->update_x2 = x;
-				if (y < d->update_y1)  d->update_y1 = y;
-				if (y > d->update_y2)  d->update_y2 = y;
-				if (x2 < d->update_x1)  d->update_x1 = x2;
-				if (x2 > d->update_x2)  d->update_x2 = x2;
-				if (y2 < d->update_y1)  d->update_y1 = y2;
-				if (y2 > d->update_y2)  d->update_y2 = y2;
-
-				if (y != y2) {
-					d->update_x1 = 0;
-					d->update_x2 = d->max_x - 1;
-				}
-			}
-		} else
-			memcpy(data, d->charcells + relative_addr, len);
-		return 1;
-	}
-
-	switch (relative_addr) {
-	default:
-		if (writeflag==MEM_READ) {
-			debug("[ vga: read from 0x%08lx ]\n",
-			    (long)relative_addr);
-		} else {
-			debug("[ vga: write to  0x%08lx: 0x%08x ]\n",
-			    (long)relative_addr, idata);
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  vga_crtc_reg_write():
- *
- *  Writes to VGA CRTC registers.
- */
-static void vga_crtc_reg_write(struct machine *machine, struct vga_data *d,
-	int regnr, int idata)
-{
-	int i, grayscale;
-
-	switch (regnr) {
-	case VGA_CRTC_CURSOR_SCANLINE_START:		/*  0x0a  */
-	case VGA_CRTC_CURSOR_SCANLINE_END:		/*  0x0b  */
-		break;
-	case VGA_CRTC_START_ADDR_HIGH:			/*  0x0c  */
-	case VGA_CRTC_START_ADDR_LOW:			/*  0x0d  */
-		d->update_x1 = 0;
-		d->update_x2 = d->max_x - 1;
-		d->update_y1 = 0;
-		d->update_y2 = d->max_y - 1;
-		d->modified = 1;
-		recalc_cursor_position(d);
-		break;
-	case VGA_CRTC_CURSOR_LOCATION_HIGH:		/*  0x0e  */
-	case VGA_CRTC_CURSOR_LOCATION_LOW:		/*  0x0f  */
-		recalc_cursor_position(d);
-		break;
-	case 0xff:
-		grayscale = 0;
-		switch (d->crtc_reg[0xff]) {
-		case 0x00:
-			grayscale = 1;
-		case 0x01:
-			d->cur_mode = MODE_CHARCELL;
-			d->max_x = 40; d->max_y = 25;
-			d->pixel_repx = machine->x11_md.scaleup * 2;
-			d->pixel_repy = machine->x11_md.scaleup;
-			d->font_width = 8;
-			d->font_height = 16;
-			d->font = font8x16;
-			break;
-		case 0x02:
-			grayscale = 1;
-		case 0x03:
-			d->cur_mode = MODE_CHARCELL;
-			d->max_x = 80; d->max_y = 25;
-			d->pixel_repx = d->pixel_repy = machine->x11_md.scaleup;
-			d->font_width = 8;
-			d->font_height = 16;
-			d->font = font8x16;
-			break;
-		case 0x08:
-			d->cur_mode = MODE_GRAPHICS;
-			d->max_x = 160;	d->max_y = 200;
-			d->graphics_mode = GRAPHICS_MODE_4BIT;
-			d->bits_per_pixel = 4;
-			d->pixel_repx = 4 * machine->x11_md.scaleup;
-			d->pixel_repy = 2 * machine->x11_md.scaleup;
-			break;
-		case 0x09:
-		case 0x0d:
-			d->cur_mode = MODE_GRAPHICS;
-			d->max_x = 320;	d->max_y = 200;
-			d->graphics_mode = GRAPHICS_MODE_4BIT;
-			d->bits_per_pixel = 4;
-			d->pixel_repx = d->pixel_repy =
-			    2 * machine->x11_md.scaleup;
-			break;
-		case 0x0e:
-			d->cur_mode = MODE_GRAPHICS;
-			d->max_x = 640;	d->max_y = 200;
-			d->graphics_mode = GRAPHICS_MODE_4BIT;
-			d->bits_per_pixel = 4;
-			d->pixel_repx = machine->x11_md.scaleup;
-			d->pixel_repy = machine->x11_md.scaleup * 2;
-			break;
-		case 0x10:
-			d->cur_mode = MODE_GRAPHICS;
-			d->max_x = 640; d->max_y = 350;
-			d->graphics_mode = GRAPHICS_MODE_4BIT;
-			d->bits_per_pixel = 4;
-			d->pixel_repx = d->pixel_repy = machine->x11_md.scaleup;
-			break;
-		case 0x12:
-			d->cur_mode = MODE_GRAPHICS;
-			d->max_x = 640; d->max_y = 480;
-			d->graphics_mode = GRAPHICS_MODE_4BIT;
-			d->bits_per_pixel = 4;
-			d->pixel_repx = d->pixel_repy = machine->x11_md.scaleup;
-			break;
-		case 0x13:
-			d->cur_mode = MODE_GRAPHICS;
-			d->max_x = 320;	d->max_y = 200;
-			d->graphics_mode = GRAPHICS_MODE_8BIT;
-			d->bits_per_pixel = 8;
-			d->pixel_repx = d->pixel_repy =
-			    2 * machine->x11_md.scaleup;
-			break;
-		default:
-			fatal("TODO! video mode change hack (mode 0x%02x)\n",
-			    d->crtc_reg[0xff]);
-			exit(1);
-		}
-
-		if (d->cur_mode == MODE_CHARCELL) {
-			dev_fb_resize(d->fb, d->max_x * d->font_width *
-			    d->pixel_repx, d->max_y * d->font_height *
-			    d->pixel_repy);
-			d->fb_size = d->max_x * d->pixel_repx * d->font_width *
-			     d->max_y * d->pixel_repy * d->font_height * 3;
-		} else {
-			dev_fb_resize(d->fb, d->max_x * d->pixel_repx,
-			    d->max_y * d->pixel_repy);
-			d->fb_size = d->max_x * d->pixel_repx *
-			     d->max_y * d->pixel_repy * 3;
-		}
-
-		for (i=0; i<machine->ncpus; i++)
-			machine->cpus[i]->invalidate_translation_caches(
-			    machine->cpus[i], 0, INVALIDATE_ALL);
-
-		if (d->gfx_mem != NULL)
-			free(d->gfx_mem);
-		d->gfx_mem_size = 1;
-		if (d->cur_mode == MODE_GRAPHICS)
-			d->gfx_mem_size = d->max_x * d->max_y /
-			    (d->graphics_mode == GRAPHICS_MODE_8BIT? 1 : 2);
-
-		CHECK_ALLOCATION(d->gfx_mem = (unsigned char *) malloc(d->gfx_mem_size));
-
-		/*  Clear screen and reset the palette:  */
-		memset(d->charcells_outputed, 0, d->charcells_size);
-		memset(d->charcells_drawn, 0, d->charcells_size);
-		memset(d->gfx_mem, 0, d->gfx_mem_size);
-		d->update_x1 = 0;
-		d->update_x2 = d->max_x - 1;
-		d->update_y1 = 0;
-		d->update_y2 = d->max_y - 1;
-		d->modified = 1;
-		reset_palette(d, grayscale);
-		register_reset(d);
-		break;
-	default:fatal("[ vga_crtc_reg_write: regnr=0x%02x idata=0x%02x ]\n",
-		    regnr, idata);
-	}
-}
-
-
-/*
- *  vga_sequencer_reg_write():
- *
- *  Writes to VGA Sequencer registers.
- */
-static void vga_sequencer_reg_write(struct machine *machine, struct vga_data *d,
-	int regnr, int idata)
-{
-	switch (regnr) {
-	case VGA_SEQ_RESET:
-	case VGA_SEQ_MAP_MASK:
-	case VGA_SEQ_SEQUENCER_MEMORY_MODE:
-		debug("[ vga_sequencer_reg_write: select %i: TODO ]\n", regnr);
-		break;
-	default:fatal("[ vga_sequencer_reg_write: select %i ]\n", regnr);
-		/*  cpu->running = 0;  */
-	}
-}
-
-
-/*
- *  vga_graphcontr_reg_write():
- *
- *  Writes to VGA Graphics Controller registers.
- */
-static void vga_graphcontr_reg_write(struct machine *machine,
-	struct vga_data *d, int regnr, int idata)
-{
-	switch (regnr) {
-	case VGA_GRAPHCONTR_READMAPSELECT:
-	case VGA_GRAPHCONTR_GRAPHICSMODE:
-	case VGA_GRAPHCONTR_MISC:
-	case VGA_GRAPHCONTR_MASK:
-		debug("[ vga_graphcontr_reg_write: select %i: TODO ]\n", regnr);
-		break;
-	default:fatal("[ vga_graphcontr_reg_write: select %i ]\n", regnr);
-		/*  cpu->running = 0;  */
-	}
-}
-
-
-/*
- *  vga_attribute_reg_write():
- *
- *  Writes to VGA Attribute registers.
- */
-static void vga_attribute_reg_write(struct machine *machine, struct vga_data *d,
-	int regnr, int idata)
-{
-	/*  0-15 are palette registers: TODO  */
-	if (regnr >= 0 && regnr <= 0xf)
-		return;
-
-	switch (regnr) {
-	default:fatal("[ vga_attribute_reg_write: select %i ]\n", regnr);
-		/*  cpu->running = 0;  */
-	}
-}
-
-
-/*
- *  dev_vga_ctrl_access():
- *
- *  Reads and writes of the VGA control registers.
- */
-DEVICE_ACCESS(vga_ctrl)
-{
-	struct vga_data *d = (struct vga_data *) extra;
-	size_t i;
-	uint64_t idata = 0, odata = 0;
-
-	for (i=0; i<len; i++) {
-		idata = data[i];
-
-		/*  0x3C0 + relative_addr...  */
-
-		switch (relative_addr) {
-
-		case VGA_ATTRIBUTE_ADDR:		/*  0x00  */
-			switch (d->attribute_state) {
-			case 0:	if (writeflag == MEM_READ)
-					odata = d->attribute_reg_select;
-				else {
-					d->attribute_reg_select = 1;
-					d->attribute_state = 1;
-				}
-				break;
-			case 1:	d->attribute_state = 0;
-				d->attribute_reg[d->attribute_reg_select] =
-				    idata;
-				vga_attribute_reg_write(cpu->machine, d,
-				    d->attribute_reg_select, idata);
-				break;
-			}
-			break;
-		case VGA_ATTRIBUTE_DATA_READ:		/*  0x01  */
-			if (writeflag == MEM_WRITE)
-				fatal("[ dev_vga: WARNING: Write to "
-				    "VGA_ATTRIBUTE_DATA_READ? ]\n");
-			else {
-				if (d->attribute_state == 0)
-					fatal("[ dev_vga: WARNING: Read from "
-					    "VGA_ATTRIBUTE_DATA_READ, but no"
-					    " register selected? ]\n");
-				else
-					odata = d->attribute_reg[
-					    d->attribute_reg_select];
-			}
-			break;
-
-		case VGA_MISC_OUTPUT_W:			/*  0x02  */
-			if (writeflag == MEM_WRITE)
-				d->misc_output_reg = idata;
-			else {
-				/*  Reads: Input Status 0  */
-				odata = 0x00;
-			}
-			break;
-
-		case VGA_SEQUENCER_ADDR:		/*  0x04  */
-			if (writeflag == MEM_READ)
-				odata = d->sequencer_reg_select;
-			else
-				d->sequencer_reg_select = idata;
-			break;
-		case VGA_SEQUENCER_DATA:		/*  0x05  */
-			if (writeflag == MEM_READ)
-				odata = d->sequencer_reg[
-				    d->sequencer_reg_select];
-			else {
-				d->sequencer_reg[d->
-				    sequencer_reg_select] = idata;
-				vga_sequencer_reg_write(cpu->machine, d,
-				    d->sequencer_reg_select, idata);
-			}
-			break;
-
-		case VGA_DAC_ADDR_READ:			/*  0x07  */
-			if (writeflag == MEM_WRITE) {
-				d->palette_read_index = idata;
-				d->palette_read_subindex = 0;
-			} else {
-				debug("[ dev_vga: WARNING: Read from "
-				    "VGA_DAC_ADDR_READ? TODO ]\n");
-				/*  TODO  */
-			}
-			break;
-		case VGA_DAC_ADDR_WRITE:		/*  0x08  */
-			if (writeflag == MEM_WRITE) {
-				d->palette_write_index = idata;
-				d->palette_write_subindex = 0;
-
-				/*  TODO: Is this correct?  */
-				d->palette_read_index = idata;
-				d->palette_read_subindex = 0;
-			} else {
-				fatal("[ dev_vga: WARNING: Read from "
-				    "VGA_DAC_ADDR_WRITE? ]\n");
-				odata = d->palette_write_index;
-			}
-			break;
-		case VGA_DAC_DATA:			/*  0x09  */
-			if (writeflag == MEM_WRITE) {
-				int new_ = (idata & 63) << 2;
-				int old = d->fb->rgb_palette[d->
-				    palette_write_index*3+d->
-				    palette_write_subindex];
-				d->fb->rgb_palette[d->palette_write_index * 3 +
-				    d->palette_write_subindex] = new_;
-				/*  Redraw whole screen, if the
-				    palette changed:  */
-				if (new_ != old) {
-					d->modified = 1;
-					d->palette_modified = 1;
-					d->update_x1 = d->update_y1 = 0;
-					d->update_x2 = d->max_x - 1;
-					d->update_y2 = d->max_y - 1;
-				}
-				d->palette_write_subindex ++;
-				if (d->palette_write_subindex == 3) {
-					d->palette_write_index ++;
-					d->palette_write_subindex = 0;
-				}
-			} else {
-				odata = (d->fb->rgb_palette[d->
-				    palette_read_index * 3 +
-				    d->palette_read_subindex] >> 2) & 63;
-				d->palette_read_subindex ++;
-				if (d->palette_read_subindex == 3) {
-					d->palette_read_index ++;
-					d->palette_read_subindex = 0;
-				}
-			}
-			break;
-
-		case VGA_MISC_OUTPUT_R:
-			odata = d->misc_output_reg;
-			break;
-
-		case VGA_GRAPHCONTR_ADDR:		/*  0x0e  */
-			if (writeflag == MEM_READ)
-				odata = d->graphcontr_reg_select;
-			else
-				d->graphcontr_reg_select = idata;
-			break;
-		case VGA_GRAPHCONTR_DATA:		/*  0x0f  */
-			if (writeflag == MEM_READ)
-				odata = d->graphcontr_reg[
-				    d->graphcontr_reg_select];
-			else {
-				d->graphcontr_reg[d->
-				    graphcontr_reg_select] = idata;
-				vga_graphcontr_reg_write(cpu->machine, d,
-				    d->graphcontr_reg_select, idata);
-			}
-			break;
-
-		case VGA_CRTC_ADDR:			/*  0x14  */
-			if (writeflag == MEM_READ)
-				odata = d->crtc_reg_select;
-			else
-				d->crtc_reg_select = idata;
-			break;
-		case VGA_CRTC_DATA:			/*  0x15  */
-			if (writeflag == MEM_READ)
-				odata = d->crtc_reg[d->crtc_reg_select];
-			else {
-				d->crtc_reg[d->crtc_reg_select] = idata;
-				vga_crtc_reg_write(cpu->machine, d,
-				    d->crtc_reg_select, idata);
-			}
-			break;
-
-		case VGA_INPUT_STATUS_1:	/*  0x1A  */
-			odata = 0;
-			d->n_is1_reads ++;
-			d->current_retrace_line ++;
-			d->current_retrace_line %= (MAX_RETRACE_SCANLINES * 8);
-			/*  Whenever we are "inside" a scan line, copy the
-			    current palette into retrace_palette[][]:  */
-			if ((d->current_retrace_line & 7) == 7) {
-				if (d->retrace_palette == NULL &&
-				    d->n_is1_reads > N_IS1_READ_THRESHOLD) {
-					CHECK_ALLOCATION(d->retrace_palette =
-					    (unsigned char *) malloc(
-					    MAX_RETRACE_SCANLINES * 256*3));
-				}
-				if (d->retrace_palette != NULL)
-					memcpy(d->retrace_palette + (d->
-					    current_retrace_line >> 3) * 256*3,
-					    d->fb->rgb_palette, d->cur_mode ==
-					    MODE_CHARCELL? (16*3) : (256*3));
-			}
-			/*  These need to go on and off, to fake the
-			    real vertical and horizontal retrace info.  */
-			if (d->current_retrace_line < 20*8)
-				odata |= VGA_IS1_DISPLAY_VRETRACE;
-			else {
-				if ((d->current_retrace_line & 7) == 0)
-					odata = VGA_IS1_DISPLAY_DISPLAY_DISABLE;
-			}
-			break;
-
-		default:
-			if (writeflag==MEM_READ) {
-				debug("[ vga_ctrl: read from 0x%08lx ]\n",
-				    (long)relative_addr);
-			} else {
-				debug("[ vga_ctrl: write to  0x%08lx: 0x%08x"
-				    " ]\n", (long)relative_addr, (int)idata);
-			}
-		}
-
-		if (writeflag == MEM_READ)
-			data[i] = odata;
-
-		/*  For multi-byte accesses:  */
-		relative_addr ++;
-	}
-
-	return 1;
-}
-
-
-/*
- *  dev_vga_init():
- *
- *  Register a VGA text console device. max_x and max_y could be something
- *  like 80 and 25, respectively.
- */
-void dev_vga_init(struct machine *machine, struct memory *mem,
-	uint64_t videomem_base, uint64_t control_base, const char *name)
-{
-	struct vga_data *d;
-	size_t allocsize, i;
-
-	CHECK_ALLOCATION(d = (struct vga_data *) malloc(sizeof(struct vga_data)));
-	memset(d, 0, sizeof(struct vga_data));
-
-	d->console_handle = console_start_slave(machine, "vga",
-	    CONSOLE_OUTPUT_ONLY);
-
-	d->videomem_base  = videomem_base;
-	d->control_base   = control_base;
-	d->max_x          = 80;
-	d->max_y          = 25;
-	d->cur_mode       = MODE_CHARCELL;
-	d->crtc_reg[0xff] = 0x03;
-	d->charcells_size = 0x8000;
-	d->gfx_mem_size   = 64;	/*  Nothing, as we start in text mode,
-			but size large enough to make gfx_mem aligned.  */
-	d->pixel_repx = d->pixel_repy = machine->x11_md.scaleup;
-
-	/*  Allocate in full pages, to make it possible to use dyntrans:  */
-	allocsize = ((d->charcells_size-1) | (machine->arch_pagesize-1)) + 1;
-	CHECK_ALLOCATION(d->charcells = (unsigned char *) malloc(d->charcells_size));
-	CHECK_ALLOCATION(d->charcells_outputed = (unsigned char *) malloc(d->charcells_size));
-	CHECK_ALLOCATION(d->charcells_drawn = (unsigned char *) malloc(d->charcells_size));
-	CHECK_ALLOCATION(d->gfx_mem = (unsigned char *) malloc(d->gfx_mem_size));
-
-	memset(d->charcells_drawn, 0, d->charcells_size);
-
-	for (i=0; i<d->charcells_size; i+=2) {
-		d->charcells[i] = ' ';
-		d->charcells[i+1] = 0x07;  /*  Default color  */
-		d->charcells_drawn[i] = ' ';
-		d->charcells_drawn[i+1] = 0x07;
-	}
-
-	memset(d->charcells_outputed, 0, d->charcells_size);
-	memset(d->gfx_mem, 0, d->gfx_mem_size);
-
-	d->font = font8x16;
-	d->font_width  = 8;
-	d->font_height = 16;
-
-	d->fb_max_x = d->pixel_repx * d->max_x;
-	d->fb_max_y = d->pixel_repy * d->max_y;
-	if (d->cur_mode == MODE_CHARCELL) {
-		d->fb_max_x *= d->font_width;
-		d->fb_max_y *= d->font_height;
-	}
-
-	memory_device_register(mem, "vga_charcells", videomem_base + 0x18000,
-	    allocsize, dev_vga_access, d, DM_DYNTRANS_OK |
-	    DM_DYNTRANS_WRITE_OK | DM_READS_HAVE_NO_SIDE_EFFECTS,
-	    d->charcells);
-	memory_device_register(mem, "vga_gfx", videomem_base, GFX_ADDR_WINDOW,
-	    dev_vga_graphics_access, d, DM_DEFAULT |
-	    DM_READS_HAVE_NO_SIDE_EFFECTS, d->gfx_mem);
-	memory_device_register(mem, "vga_ctrl", control_base,
-	    32, dev_vga_ctrl_access, d, DM_DEFAULT, NULL);
-
-	d->fb = dev_fb_init(machine, mem, VGA_FB_ADDR, VFB_GENERIC,
-	    d->fb_max_x, d->fb_max_y, d->fb_max_x, d->fb_max_y, 24, "VGA");
-	d->fb_size = d->fb_max_x * d->fb_max_y * 3;
-
-	reset_palette(d, 0);
-
-	/*  This will force an initial redraw/resynch:  */
-	d->update_x1 = 0;
-	d->update_x2 = d->max_x - 1;
-	d->update_y1 = 0;
-	d->update_y2 = d->max_y - 1;
-	d->modified = 1;
-
-	machine_add_tickfunction(machine, dev_vga_tick, d, VGA_TICK_SHIFT);
-
-	register_reset(d);
-
-	vga_update_cursor(machine, d);
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_vme.c gxemul-0.7.0+dfsg/src/devices/dev_vme.c
--- gxemul-0.6.2/src/devices/dev_vme.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_vme.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,170 @@
+/*
+ *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: VME bus
+ *
+ *  TODO: Probably almost everything.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/mvme88k_vme.h"
+
+
+/*  #define debug fatal  */
+
+
+#define	VME_LEN			0x1000
+
+struct vme_data {
+	uint32_t	reg[VME_LEN / sizeof(uint32_t)];
+};
+
+
+DEVICE_ACCESS(vme)
+{
+	struct vme_data *d = (struct vme_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	if (writeflag == MEM_READ)
+		odata = d->reg[relative_addr / sizeof(uint32_t)];
+
+	switch (relative_addr) {
+
+	case 0:	/*  Used by OpenBSD/mvme88k when probing...  */
+		break;
+
+	case VME2_GCSRCTL:
+		debug("[ vme: unimplemented GCSRCTL ]\n");
+		break;
+
+	case VME2_TCR:
+		if (writeflag == MEM_READ)
+			debug("[ vme: unimplemented READ from TCR ]\n");
+		else
+			debug("[ vme: unimplemented WRITE to TCR: "
+			    "0x%x ]\n", (int)idata);
+		break;
+
+	case VME2_T1CMP:
+		if (writeflag == MEM_WRITE)
+			d->reg[relative_addr / sizeof(uint32_t)] = idata;
+		break;
+
+	case VME2_T1COUNT:
+		if (writeflag == MEM_WRITE)
+			d->reg[relative_addr / sizeof(uint32_t)] = idata;
+		else {
+			/*  NOTE! This is a quick hack. TODO: Fix!  */
+			d->reg[relative_addr / sizeof(uint32_t)] += 100;
+		}
+		break;
+
+	case VME2_TCTL:
+		if (writeflag == MEM_WRITE)
+			d->reg[relative_addr / sizeof(uint32_t)] = idata;
+
+		/*  TODO  */
+		/*  debug("[ vme: unimplemented TCTL ]\n");  */
+		break;
+
+	case VME2_IRQEN:
+		if (writeflag == MEM_READ)
+			debug("[ vme: unimplemented READ from IRQEN ]\n");
+		else
+			debug("[ vme: unimplemented WRITE to IRQEN: "
+			    "0x%x ]\n", (int)idata);
+		break;
+
+	case VME2_IRQL3:
+		if (writeflag == MEM_READ)
+			debug("[ vme: unimplemented READ from IRQL3 ]\n");
+		else
+			debug("[ vme: unimplemented WRITE to IRQL3: "
+			    "0x%x ]\n", (int)idata);
+		break;
+
+	case VME2_IRQL4:
+		if (writeflag == MEM_READ)
+			debug("[ vme: unimplemented READ from IRQL4 ]\n");
+		else
+			debug("[ vme: unimplemented WRITE to IRQL4: "
+			    "0x%x ]\n", (int)idata);
+		break;
+
+	case VME2_VBR:
+		/*  Vector Base Register.  */
+		if (writeflag == MEM_WRITE)
+			d->reg[relative_addr / sizeof(uint32_t)] = idata;
+		break;
+
+	default:if (writeflag == MEM_READ)
+			debug("[ vme: unimplemented READ from offset 0x%x ]"
+			    "\n", (int)relative_addr);
+		else
+			debug("[ vme: unimplemented WRITE to offset 0x%x: "
+			    "0x%x ]\n", (int)relative_addr, (int)idata);
+		exit(1);
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+DEVINIT(vme)
+{
+	struct vme_data *d;
+
+	CHECK_ALLOCATION(d = (struct vme_data *) malloc(sizeof(struct vme_data)));
+	memset(d, 0, sizeof(struct vme_data));
+
+	/*  According to OpenBSD/mvme88k:  */
+	d->reg[VME2_VBR / sizeof(uint32_t)] =
+	    VME2_SET_VBR0(6) + VME2_SET_VBR1(7);
+
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, VME_LEN, dev_vme_access, (void *)d,
+	    DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_vme.cc gxemul-0.7.0+dfsg/src/devices/dev_vme.cc
--- gxemul-0.6.2/src/devices/dev_vme.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_vme.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,170 +0,0 @@
-/*
- *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: VME bus
- *
- *  TODO: Probably almost everything.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/mvme88k_vme.h"
-
-
-/*  #define debug fatal  */
-
-
-#define	VME_LEN			0x1000
-
-struct vme_data {
-	uint32_t	reg[VME_LEN / sizeof(uint32_t)];
-};
-
-
-DEVICE_ACCESS(vme)
-{
-	struct vme_data *d = (struct vme_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	if (writeflag == MEM_READ)
-		odata = d->reg[relative_addr / sizeof(uint32_t)];
-
-	switch (relative_addr) {
-
-	case 0:	/*  Used by OpenBSD/mvme88k when probing...  */
-		break;
-
-	case VME2_GCSRCTL:
-		debug("[ vme: unimplemented GCSRCTL ]\n");
-		break;
-
-	case VME2_TCR:
-		if (writeflag == MEM_READ)
-			debug("[ vme: unimplemented READ from TCR ]\n");
-		else
-			debug("[ vme: unimplemented WRITE to TCR: "
-			    "0x%x ]\n", (int)idata);
-		break;
-
-	case VME2_T1CMP:
-		if (writeflag == MEM_WRITE)
-			d->reg[relative_addr / sizeof(uint32_t)] = idata;
-		break;
-
-	case VME2_T1COUNT:
-		if (writeflag == MEM_WRITE)
-			d->reg[relative_addr / sizeof(uint32_t)] = idata;
-		else {
-			/*  NOTE! This is a quick hack. TODO: Fix!  */
-			d->reg[relative_addr / sizeof(uint32_t)] += 100;
-		}
-		break;
-
-	case VME2_TCTL:
-		if (writeflag == MEM_WRITE)
-			d->reg[relative_addr / sizeof(uint32_t)] = idata;
-
-		/*  TODO  */
-		/*  debug("[ vme: unimplemented TCTL ]\n");  */
-		break;
-
-	case VME2_IRQEN:
-		if (writeflag == MEM_READ)
-			debug("[ vme: unimplemented READ from IRQEN ]\n");
-		else
-			debug("[ vme: unimplemented WRITE to IRQEN: "
-			    "0x%x ]\n", (int)idata);
-		break;
-
-	case VME2_IRQL3:
-		if (writeflag == MEM_READ)
-			debug("[ vme: unimplemented READ from IRQL3 ]\n");
-		else
-			debug("[ vme: unimplemented WRITE to IRQL3: "
-			    "0x%x ]\n", (int)idata);
-		break;
-
-	case VME2_IRQL4:
-		if (writeflag == MEM_READ)
-			debug("[ vme: unimplemented READ from IRQL4 ]\n");
-		else
-			debug("[ vme: unimplemented WRITE to IRQL4: "
-			    "0x%x ]\n", (int)idata);
-		break;
-
-	case VME2_VBR:
-		/*  Vector Base Register.  */
-		if (writeflag == MEM_WRITE)
-			d->reg[relative_addr / sizeof(uint32_t)] = idata;
-		break;
-
-	default:if (writeflag == MEM_READ)
-			debug("[ vme: unimplemented READ from offset 0x%x ]"
-			    "\n", (int)relative_addr);
-		else
-			debug("[ vme: unimplemented WRITE to offset 0x%x: "
-			    "0x%x ]\n", (int)relative_addr, (int)idata);
-		exit(1);
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-DEVINIT(vme)
-{
-	struct vme_data *d;
-
-	CHECK_ALLOCATION(d = (struct vme_data *) malloc(sizeof(struct vme_data)));
-	memset(d, 0, sizeof(struct vme_data));
-
-	/*  According to OpenBSD/mvme88k:  */
-	d->reg[VME2_VBR / sizeof(uint32_t)] =
-	    VME2_SET_VBR0(6) + VME2_SET_VBR1(7);
-
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, VME_LEN, dev_vme_access, (void *)d,
-	    DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_vr41xx.c gxemul-0.7.0+dfsg/src/devices/dev_vr41xx.c
--- gxemul-0.6.2/src/devices/dev_vr41xx.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_vr41xx.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,806 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: VR41xx (VR4122 and VR4131) misc functions
+ *
+ *  This is just a big hack.
+ *
+ *  TODO: Implement more functionality some day.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "timer.h"
+
+#include "thirdparty/bcureg.h"
+#include "thirdparty/vripreg.h"
+#include "thirdparty/vrkiureg.h"
+#include "thirdparty/vr_rtcreg.h"
+
+
+/*  #define debug fatal  */
+
+#define	DEV_VR41XX_TICKSHIFT		14
+
+#define	DEV_VR41XX_LENGTH		0x800	/*  TODO?  */
+struct vr41xx_data {
+	struct interrupt cpu_irq;		/*  Connected to MIPS irq 2  */
+	int		cpumodel;		/*  Model nr, e.g. 4121  */
+
+	/*  KIU:  */
+	int		kiu_console_handle;
+	uint32_t	kiu_offset;
+	struct interrupt kiu_irq;
+	int		kiu_int_assert;
+	int		old_kiu_int_assert;
+
+	int		d0, d1, d2, d3, d4, d5;
+	int		dont_clear_next;
+	int		escape_state;
+
+	/*  Timer:  */
+	int		pending_timer_interrupts;
+	struct interrupt timer_irq;
+	struct timer	*timer;
+
+	/*  See icureg.h in NetBSD for more info.  */
+	uint16_t	sysint1;
+	uint16_t	msysint1;
+	uint16_t	giuint;
+	uint16_t	giumask;
+	uint16_t	sysint2;
+	uint16_t	msysint2;
+	struct interrupt giu_irq;
+};
+
+
+/*
+ *  vr41xx_vrip_interrupt_assert():
+ *  vr41xx_vrip_interrupt_deassert():
+ */ 
+void vr41xx_vrip_interrupt_assert(struct interrupt *interrupt)
+{
+	struct vr41xx_data *d = (struct vr41xx_data *) interrupt->extra;
+	int line = interrupt->line;
+	if (line < 16)
+		d->sysint1 |= (1 << line);
+	else
+		d->sysint2 |= (1 << (line-16));
+	if ((d->sysint1 & d->msysint1) | (d->sysint2 & d->msysint2))
+                INTERRUPT_ASSERT(d->cpu_irq);
+}
+void vr41xx_vrip_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct vr41xx_data *d = (struct vr41xx_data *) interrupt->extra;
+	int line = interrupt->line;
+	if (line < 16)
+		d->sysint1 &= ~(1 << line);
+	else
+		d->sysint2 &= ~(1 << (line-16));
+	if (!(d->sysint1 & d->msysint1) && !(d->sysint2 & d->msysint2))
+                INTERRUPT_DEASSERT(d->cpu_irq);
+}
+
+
+/*
+ *  vr41xx_giu_interrupt_assert():
+ *  vr41xx_giu_interrupt_deassert():
+ */ 
+void vr41xx_giu_interrupt_assert(struct interrupt *interrupt)
+{
+	struct vr41xx_data *d = (struct vr41xx_data *) interrupt->extra;
+	int line = interrupt->line;
+	d->giuint |= (1 << line);
+	if (d->giuint & d->giumask)
+                INTERRUPT_ASSERT(d->giu_irq);
+}
+void vr41xx_giu_interrupt_deassert(struct interrupt *interrupt)
+{
+	struct vr41xx_data *d = (struct vr41xx_data *) interrupt->extra;
+	int line = interrupt->line;
+	d->giuint &= ~(1 << line);
+	if (!(d->giuint & d->giumask))
+                INTERRUPT_DEASSERT(d->giu_irq);
+}
+
+
+static void recalc_kiu_int_assert(struct cpu *cpu, struct vr41xx_data *d)
+{
+	if (d->kiu_int_assert != d->old_kiu_int_assert) {
+		d->old_kiu_int_assert = d->kiu_int_assert;
+		if (d->kiu_int_assert != 0)
+			INTERRUPT_ASSERT(d->kiu_irq);
+		else
+			INTERRUPT_DEASSERT(d->kiu_irq);
+	}
+}
+
+
+/*
+ *  vr41xx_keytick():
+ */
+static void vr41xx_keytick(struct cpu *cpu, struct vr41xx_data *d)
+{
+	int keychange = 0;
+
+	/*
+	 *  Keyboard input:
+	 *
+	 *  Hardcoded for MobilePro. (See NetBSD's hpckbdkeymap.h for
+	 *  info on other keyboard layouts. mobilepro780_keytrans is the
+	 *  one used here.)
+	 *
+	 *  TODO: Make this work with "any" keyboard layout.
+	 *
+	 *  ofs 0:
+	 *	8000='o' 4000='.' 2000=DOWN  1000=UP
+	 *	 800=';'  400='''  200='['    100=?
+	 *	  80='l'   40=CR    20=RIGHT   10=LEFT
+	 *	   8='/'    4='\'    2=']'      1=SPACE
+	 *  ofs 2:
+	 *	8000='a' 4000='s' 2000='d' 1000='f'
+	 *	 800='`'  400='-'  200='='  100=?
+	 *	  80='z'   40='x'   20='c'   10='v'
+	 *	   8=?      4=?      2=?
+	 *  ofs 4:
+	 *	8000='9' 4000='0' 2000=?   1000=?
+	 *	 800='b'  400='n'  200='m'  100=','
+	 *	  80='q'   40='w'   20='e'   10='r'
+	 *	   8='5'    4='6'    2='7'    1='8'
+	 *  ofs 6:
+	 *	8000=ESC 4000=DEL 2000=CAPS 1000=?
+	 *	 800='t'  400='y'  200='u'   100='i'
+	 *	  80='1'   40='2'   20='3'    10='4'
+	 *	   8='g'    4='h'    2='j'     1='k'
+	 *  ofs 8:
+	 *                      200=ALT_L
+	 *	  80=    40=TAB  20='p' 10=BS
+	 *	   8=     4=      2=     1=ALT_R
+	 *  ofs a:
+	 *	800=SHIFT 4=CTRL
+	 *
+	 *
+	 *  The following are for the IBM WorkPad Z50:
+	 *  (Not yet implemented, TODO)
+	 *
+	 *  00    f1      f3      f5      f7      f9      -       -       f11
+	 *  08    f2      f4      f6      f8      f10     -       -       f12
+	 *  10    '       [       -       0       p       ;       up      /
+	 *  18    -       -       -       9       o       l       .       -
+	 *  20    left    ]       =       8       i       k       ,       -
+	 *  28    h       y       6       7       u       j       m       n
+	 *  30    -       bs      num     del     -       \       ent     sp
+	 *  38    g       t       5       4       r       f       v       b
+	 *  40    -       -       -       3       e       d       c       right
+	 *  48    -       -       -       2       w       s       x       down
+	 *  50    esc     tab     ~       1       q       a       z       -
+	 *  58    menu    Ls      Lc      Rc      La      Ra      Rs      -
+	 */
+
+	if (d->d0 != 0 || d->d1 != 0 || d->d2 != 0 ||
+	    d->d3 != 0 || d->d4 != 0 || d->d5 != 0)
+		keychange = 1;
+
+	/*  Release all keys:  */
+	if (!d->dont_clear_next) {
+		d->d0 = d->d1 = d->d2 = d->d3 = d->d4 = d->d5 = 0;
+	} else
+		d->dont_clear_next = 0;
+
+	if (console_charavail(d->kiu_console_handle)) {
+		char ch = console_readchar(d->kiu_console_handle);
+
+		if (d->escape_state > 0) {
+			switch (d->escape_state) {
+			case 1:	/*  expecting a [  */
+				d->escape_state = 0;
+				if (ch == '[')
+					d->escape_state = 2;
+				break;
+			case 2:	/*  cursor keys etc:  */
+				/*  Ugly hack for Mobilepro770:  */
+				if (cpu->machine->machine_subtype ==
+				    MACHINE_HPCMIPS_NEC_MOBILEPRO_770) {
+					switch (ch) {
+					case 'A': d->d0 = 0x2000; break;
+					case 'B': d->d0 = 0x20; break;
+					case 'C': d->d0 = 0x1000; break;
+					case 'D': d->d0 = 0x10; break;
+					default:  fatal("[ vr41xx kiu: unimpl"
+					    "emented escape 0x%02 ]\n", ch);
+					}
+				} else {
+					switch (ch) {
+					case 'A': d->d0 = 0x1000; break;
+					case 'B': d->d0 = 0x2000; break;
+					case 'C': d->d0 = 0x20; break;
+					case 'D': d->d0 = 0x10; break;
+					default:  fatal("[ vr41xx kiu: unimpl"
+					    "emented escape 0x%02 ]\n", ch);
+					}
+				}
+				d->escape_state = 0;
+			}
+		} else switch (ch) {
+		case '+':	console_makeavail(d->kiu_console_handle, '=');
+				d->d5 = 0x800; break;
+		case '_':	console_makeavail(d->kiu_console_handle, '-');
+				d->d5 = 0x800; break;
+		case '<':	console_makeavail(d->kiu_console_handle, ',');
+				d->d5 = 0x800; break;
+		case '>':	console_makeavail(d->kiu_console_handle, '.');
+				d->d5 = 0x800; break;
+		case '{':	console_makeavail(d->kiu_console_handle, '[');
+				d->d5 = 0x800; break;
+		case '}':	console_makeavail(d->kiu_console_handle, ']');
+				d->d5 = 0x800; break;
+		case ':':	console_makeavail(d->kiu_console_handle, ';');
+				d->d5 = 0x800; break;
+		case '"':	console_makeavail(d->kiu_console_handle, '\'');
+				d->d5 = 0x800; break;
+		case '|':	console_makeavail(d->kiu_console_handle, '\\');
+				d->d5 = 0x800; break;
+		case '?':	console_makeavail(d->kiu_console_handle, '/');
+				d->d5 = 0x800; break;
+
+		case '!':	console_makeavail(d->kiu_console_handle, '1');
+				d->d5 = 0x800; break;
+		case '@':	console_makeavail(d->kiu_console_handle, '2');
+				d->d5 = 0x800; break;
+		case '#':	console_makeavail(d->kiu_console_handle, '3');
+				d->d5 = 0x800; break;
+		case '$':	console_makeavail(d->kiu_console_handle, '4');
+				d->d5 = 0x800; break;
+		case '%':	console_makeavail(d->kiu_console_handle, '5');
+				d->d5 = 0x800; break;
+		case '^':	console_makeavail(d->kiu_console_handle, '6');
+				d->d5 = 0x800; break;
+		case '&':	console_makeavail(d->kiu_console_handle, '7');
+				d->d5 = 0x800; break;
+		case '*':	console_makeavail(d->kiu_console_handle, '8');
+				d->d5 = 0x800; break;
+		case '(':	console_makeavail(d->kiu_console_handle, '9');
+				d->d5 = 0x800; break;
+		case ')':	console_makeavail(d->kiu_console_handle, '0');
+				d->d5 = 0x800; break;
+
+		case '1':	d->d3 = 0x80; break;
+		case '2':	d->d3 = 0x40; break;
+		case '3':	d->d3 = 0x20; break;
+		case '4':	d->d3 = 0x10; break;
+		case '5':	d->d2 = 0x08; break;
+		case '6':	d->d2 = 0x04; break;
+		case '7':	d->d2 = 0x02; break;
+		case '8':	d->d2 = 0x01; break;
+		case '9':	d->d2 = 0x8000; break;
+		case '0':	d->d2 = 0x4000; break;
+
+		case ';':	d->d0 = 0x800; break;
+		case '\'':	d->d0 = 0x400; break;
+		case '[':	d->d0 = 0x200; break;
+		case '/':	d->d0 = 0x8; break;
+		case '\\':	d->d0 = 0x4; break;
+		case ']':	d->d0 = 0x2; break;
+
+		case 'a':	d->d1 = 0x8000; break;
+		case 'b':	d->d2 = 0x800; break;
+		case 'c':	d->d1 = 0x20; break;
+		case 'd':	d->d1 = 0x2000; break;
+		case 'e':	d->d2 = 0x20; break;
+		case 'f':	d->d1 = 0x1000; break;
+		case 'g':	d->d3 = 0x8; break;
+		case 'h':	d->d3 = 0x4; break;
+		case 'i':	d->d3 = 0x100; break;
+		case 'j':	d->d3 = 0x2; break;
+		case 'k':	d->d3 = 0x1; break;
+		case 'l':	d->d0 = 0x80; break;
+		case 'm':	d->d2 = 0x200; break;
+		case 'n':	d->d2 = 0x400; break;
+		case 'o':	d->d0 = 0x8000; break;
+		case 'p':	d->d4 = 0x20; break;
+		case 'q':	d->d2 = 0x80; break;
+		case 'r':	d->d2 = 0x10; break;
+		case 's':	d->d1 = 0x4000; break;
+		case 't':	d->d3 = 0x800; break;
+		case 'u':	d->d3 = 0x200; break;
+		case 'v':	d->d1 = 0x10; break;
+		case 'w':	d->d2 = 0x40; break;
+		case 'x':	d->d1 = 0x40; break;
+		case 'y':	d->d3 = 0x400; break;
+		case 'z':	d->d1 = 0x80; break;
+
+		case ',':	d->d2 = 0x100; break;
+		case '.':	d->d0 = 0x4000; break;
+		case '-':	d->d1 = 0x400; break;
+		case '=':	d->d1 = 0x200; break;
+
+		case '\r':
+		case '\n':	d->d0 = 0x40; break;
+		case ' ':	d->d0 = 0x01; break;
+		case '\b':	d->d4 = 0x10; break;
+
+		case 27:	d->escape_state = 1; break;
+
+		default:
+			/*  Shifted:  */
+			if (ch >= 'A' && ch <= 'Z') {
+				console_makeavail(d->kiu_console_handle,
+				    ch + 32);
+				d->d5 = 0x800;
+				d->dont_clear_next = 1;
+				break;
+			}
+
+			/*  CTRLed:  */
+			if (ch >= 1 && ch <= 26) {
+				console_makeavail(d->kiu_console_handle,
+				    ch + 96);
+				d->d5 = 0x4;
+				d->dont_clear_next = 1;
+				break;
+			}
+		}
+
+		if (d->escape_state == 0)
+			keychange = 1;
+	}
+
+	if (keychange) {
+		/*  4=lost data, 2=data complete, 1=key input detected  */
+		d->kiu_int_assert |= 3;
+		recalc_kiu_int_assert(cpu, d);
+	}
+}
+
+
+/*
+ *  timer_tick():
+ */
+static void timer_tick(struct timer *timer, void *extra)
+{
+	struct vr41xx_data *d = (struct vr41xx_data *) extra;
+	d->pending_timer_interrupts ++;
+}
+
+
+DEVICE_TICK(vr41xx)
+{
+	struct vr41xx_data *d = (struct vr41xx_data *) extra;
+
+	if (d->pending_timer_interrupts > 0)
+		INTERRUPT_ASSERT(d->timer_irq);
+
+	if (cpu->machine->x11_md.in_use)
+		vr41xx_keytick(cpu, d);
+}
+
+
+/*
+ *  vr41xx_kiu():
+ *
+ *  Keyboard Interface Unit. Return value is "odata".
+ *  (See NetBSD's vrkiu.c for more info.)
+ */
+static uint64_t vr41xx_kiu(struct cpu *cpu, int ofs, uint64_t idata,
+	int writeflag, struct vr41xx_data *d)
+{
+	uint64_t odata = 0;
+
+	switch (ofs) {
+	case KIUDAT0:
+		odata = d->d0; break;
+	case KIUDAT1:
+		odata = d->d1; break;
+	case KIUDAT2:
+		odata = d->d2; break;
+	case KIUDAT3:
+		odata = d->d3; break;
+	case KIUDAT4:
+		odata = d->d4; break;
+	case KIUDAT5:
+		odata = d->d5; break;
+	case KIUSCANREP:
+		if (writeflag == MEM_WRITE) {
+			debug("[ vr41xx KIU: setting KIUSCANREP to 0x%04x ]\n",
+			    (int)idata);
+			/*  TODO  */
+		} else
+			fatal("[ vr41xx KIU: unimplemented read from "
+			    "KIUSCANREP ]\n");
+		break;
+	case KIUSCANS:
+		if (writeflag == MEM_WRITE) {
+			debug("[ vr41xx KIU: write to KIUSCANS: 0x%04x: TODO"
+			    " ]\n", (int)idata);
+			/*  TODO  */
+		} else
+			debug("[ vr41xx KIU: unimplemented read from "
+			    "KIUSCANS ]\n");
+		break;
+	case KIUINT:
+		/*  Interrupt. A wild guess: zero-on-write  */
+		if (writeflag == MEM_WRITE) {
+			d->kiu_int_assert &= ~idata;
+		} else {
+			odata = d->kiu_int_assert;
+		}
+		recalc_kiu_int_assert(cpu, d);
+		break;
+	case KIURST:
+		/*  Reset.  */
+		break;
+	default:
+		if (writeflag == MEM_WRITE)
+			debug("[ vr41xx KIU: unimplemented write to offset "
+			    "0x%x, data=0x%016" PRIx64" ]\n", ofs,
+			    (uint64_t) idata);
+		else
+			debug("[ vr41xx KIU: unimplemented read from offset "
+			    "0x%x ]\n", ofs);
+	}
+
+	return odata;
+}
+
+
+DEVICE_ACCESS(vr41xx)
+{
+	struct vr41xx_data *d = (struct vr41xx_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int revision = 0;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	// int regnr = relative_addr / sizeof(uint64_t);
+
+	/*  KIU ("Keyboard Interface Unit") is handled separately.  */
+	if (relative_addr >= d->kiu_offset &&
+	    relative_addr < d->kiu_offset + 0x20) {
+		odata = vr41xx_kiu(cpu, relative_addr - d->kiu_offset,
+		    idata, writeflag, d);
+		goto ret;
+	}
+
+	/*  TODO: Maybe these should be handled separately as well?  */
+
+	switch (relative_addr) {
+
+	/*  BCU:  0x00 .. 0x1c  */
+	case BCUREVID_REG_W:	/*  0x010  */
+	case BCU81REVID_REG_W:	/*  0x014  */
+		/*
+		 *  TODO?  Linux seems to read 0x14. The lowest bits are
+		 *  a divisor for PClock, bits 8 and up seem to be a
+		 *  divisor for VTClock (relative to PClock?)...
+		 */
+		switch (d->cpumodel) {
+		case 4131:	revision = BCUREVID_RID_4131; break;
+		case 4122:	revision = BCUREVID_RID_4122; break;
+		case 4121:	revision = BCUREVID_RID_4121; break;
+		case 4111:	revision = BCUREVID_RID_4111; break;
+		case 4102:	revision = BCUREVID_RID_4102; break;
+		case 4101:	revision = BCUREVID_RID_4101; break;
+		case 4181:	revision = BCUREVID_RID_4181; break;
+		}
+		odata = (revision << BCUREVID_RIDSHFT) | 0x020c;
+		break;
+	case BCU81CLKSPEED_REG_W:	/*  0x018  */
+		/*
+		 *  TODO: Implement this for ALL cpu types:
+		 */
+		odata = BCUCLKSPEED_DIVT4 << BCUCLKSPEED_DIVTSHFT;
+		break;
+
+	/*  DMAAU:  0x20 .. 0x3c  */
+
+	/*  DCU:  0x40 .. 0x5c  */
+
+	/*  CMU:  0x60 .. 0x7c  */
+
+	/*  ICU:  0x80 .. 0xbc  */
+	case 0x80:	/*  Level 1 system interrupt reg 1...  */
+		if (writeflag == MEM_READ)
+			odata = d->sysint1;
+		else {
+			/*  TODO: clear-on-write-one?  */
+			d->sysint1 &= ~idata;
+			d->sysint1 &= 0xffff;
+		}
+		break;
+	case 0x88:
+		if (writeflag == MEM_READ)
+			odata = d->giuint;
+		else
+			d->giuint &= ~idata;
+		break;
+	case 0x8c:
+		if (writeflag == MEM_READ)
+			odata = d->msysint1;
+		else
+			d->msysint1 = idata;
+		break;
+	case 0x94:
+		if (writeflag == MEM_READ)
+			odata = d->giumask;
+		else
+			d->giumask = idata;
+		break;
+	case 0xa0:	/*  Level 1 system interrupt reg 2...  */
+		if (writeflag == MEM_READ)
+			odata = d->sysint2;
+		else {
+			/*  TODO: clear-on-write-one?  */
+			d->sysint2 &= ~idata;
+			d->sysint2 &= 0xffff;
+		}
+		break;
+	case 0xa6:
+		if (writeflag == MEM_READ)
+			odata = d->msysint2;
+		else
+			d->msysint2 = idata;
+		break;
+
+	/*  RTC:  */
+	case 0xc0:
+	case 0xc2:
+	case 0xc4:
+		{
+			struct timeval tv;
+			gettimeofday(&tv, NULL);
+			/*  Adjust time by 120 years and 29 days.  */
+			tv.tv_sec += (int64_t) (120*365 + 29) * 24*60*60;
+
+			switch (relative_addr) {
+			case 0xc0:
+				odata = (tv.tv_sec & 1) << 15;
+				odata += (uint64_t)tv.tv_usec * 32768 / 1000000;
+				break;
+			case 0xc2:
+				odata = (tv.tv_sec >> 1) & 0xffff;
+				break;
+			case 0xc4:
+				odata = (tv.tv_sec >> 17) & 0xffff;
+				break;
+			}
+		}
+		break;
+
+	case 0xd0:	/*  RTCL1_L_REG_W  */
+		if (writeflag == MEM_WRITE && idata != 0) {
+			int hz = RTCL1_L_HZ / idata;
+			debug("[ vr41xx: rtc interrupts at %i Hz ]\n", hz);
+			if (d->timer == NULL)
+				d->timer = timer_add(hz, timer_tick, d);
+			else
+				timer_update_frequency(d->timer, hz);
+		}
+		break;
+	case 0xd2:	/*  RTCL1_H_REG_W  */
+		break;
+
+	case 0x108:
+		if (writeflag == MEM_READ)
+			odata = d->giuint;
+		else
+			d->giuint &= ~idata;
+		break;
+	/*  case 0x10a:
+		"High" part of GIU?
+		break;
+	*/
+
+	case 0x13e:	/*  on 4181?  */
+	case 0x1de:	/*  on 4121?  */
+		/*  RTC interrupt register...  */
+		/*  Ack. timer interrupts?  */
+		INTERRUPT_DEASSERT(d->timer_irq);
+		if (d->pending_timer_interrupts > 0)
+			d->pending_timer_interrupts --;
+		break;
+
+	default:
+		if (writeflag == MEM_WRITE)
+			debug("[ vr41xx: unimplemented write to address "
+			    "0x%" PRIx64", data=0x%016" PRIx64" ]\n",
+			    (uint64_t) relative_addr, (uint64_t) idata);
+		else
+			debug("[ vr41xx: unimplemented read from address "
+			    "0x%" PRIx64" ]\n", (uint64_t) relative_addr);
+	}
+
+ret:
+	/*
+	 *  Recalculate interrupt assertions:
+	 */
+	if (d->giuint & d->giumask)
+                INTERRUPT_ASSERT(d->giu_irq);
+	else
+                INTERRUPT_DEASSERT(d->giu_irq);
+	if ((d->sysint1 & d->msysint1) | (d->sysint2 & d->msysint2))
+                INTERRUPT_ASSERT(d->cpu_irq);
+	else
+                INTERRUPT_DEASSERT(d->cpu_irq);
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	return 1;
+}
+
+
+/*
+ *  dev_vr41xx_init():
+ *
+ *  machine->path is something like "machine[0]".
+ */
+struct vr41xx_data *dev_vr41xx_init(struct machine *machine,
+	struct memory *mem, int cpumodel)
+{
+	struct vr41xx_data *d;
+	uint64_t baseaddr = 0;
+	char tmps[300];
+	int i;
+
+	CHECK_ALLOCATION(d = (struct vr41xx_data *) malloc(sizeof(struct vr41xx_data)));
+	memset(d, 0, sizeof(struct vr41xx_data));
+
+	/*  Connect to MIPS irq 2:  */
+	snprintf(tmps, sizeof(tmps), "%s.cpu[%i].2",
+	    machine->path, machine->bootstrap_cpu);
+	INTERRUPT_CONNECT(tmps, d->cpu_irq);
+
+	/*
+	 *  Register VRIP interrupt lines 0..25:
+	 */
+	for (i=0; i<=25; i++) {
+		struct interrupt templ;
+		snprintf(tmps, sizeof(tmps), "%s.cpu[%i].vrip.%i",
+		    machine->path, machine->bootstrap_cpu, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = i;
+		templ.name = tmps;
+		templ.extra = d;
+		templ.interrupt_assert = vr41xx_vrip_interrupt_assert;
+		templ.interrupt_deassert = vr41xx_vrip_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	/*
+	 *  Register GIU interrupt lines 0..31:
+	 */
+	for (i=0; i<32; i++) {
+		struct interrupt templ;
+		snprintf(tmps, sizeof(tmps), "%s.cpu[%i].vrip.%i.giu.%i",
+		    machine->path, machine->bootstrap_cpu, VRIP_INTR_GIU, i);
+		memset(&templ, 0, sizeof(templ));
+		templ.line = i;
+		templ.name = tmps;
+		templ.extra = d;
+		templ.interrupt_assert = vr41xx_giu_interrupt_assert;
+		templ.interrupt_deassert = vr41xx_giu_interrupt_deassert;
+		interrupt_handler_register(&templ);
+	}
+
+	d->cpumodel = cpumodel;
+
+	/*  TODO: VRC4173 has the KIU at offset 0x100?  */
+	d->kiu_offset = 0x180;
+	d->kiu_console_handle = -1;
+	if (machine->x11_md.in_use)
+		d->kiu_console_handle = console_start_slave_inputonly(
+		    machine, "kiu", 1);
+
+	/*  Connect to the KIU and GIU interrupts:  */
+	snprintf(tmps, sizeof(tmps), "%s.cpu[%i].vrip.%i",
+	    machine->path, machine->bootstrap_cpu, VRIP_INTR_GIU);
+	INTERRUPT_CONNECT(tmps, d->giu_irq);
+	snprintf(tmps, sizeof(tmps), "%s.cpu[%i].vrip.%i",
+	    machine->path, machine->bootstrap_cpu, VRIP_INTR_KIU);
+	INTERRUPT_CONNECT(tmps, d->kiu_irq);
+
+	if (machine->x11_md.in_use)
+		machine->main_console_handle = d->kiu_console_handle;  
+
+	switch (cpumodel) {
+	case 4101:
+	case 4102:
+	case 4111:
+	case 4121:
+		baseaddr = 0xb000000;
+		break;
+	case 4181:
+		baseaddr = 0xa000000;
+		dev_ram_init(machine, 0xb000000, 0x1000000, DEV_RAM_MIRROR,
+		    0xa000000, NULL);
+		break;
+	case 4122:
+	case 4131:
+		baseaddr = 0xf000000;
+		break;
+	default:
+		printf("Unimplemented VR cpu model\n");
+		exit(1);
+	}
+
+	if (d->cpumodel == 4121 || d->cpumodel == 4181)
+		snprintf(tmps, sizeof(tmps), "%s.cpu[%i].3",
+		    machine->path, machine->bootstrap_cpu);
+	else
+		snprintf(tmps, sizeof(tmps), "%s.cpu[%i].vrip.%i",
+		    machine->path, machine->bootstrap_cpu, VRIP_INTR_ETIMER);
+	INTERRUPT_CONNECT(tmps, d->timer_irq);
+
+	memory_device_register(mem, "vr41xx", baseaddr, DEV_VR41XX_LENGTH,
+	    dev_vr41xx_access, (void *)d, DM_DEFAULT, NULL);
+
+	/*
+	 *  TODO: Find out which controllers are at which addresses on
+	 *  which chips.
+	 */
+	if (cpumodel == 4131) {
+		snprintf(tmps, sizeof(tmps), "ns16550 irq=%s.cpu[%i].vrip.%i "
+		    "addr=0x%" PRIx64" name2=siu", machine->path,
+		    machine->bootstrap_cpu, VRIP_INTR_SIU,
+		    (uint64_t) (baseaddr+0x800));
+		device_add(machine, tmps);
+	} else {
+		/*  This is used by Linux and NetBSD:  */
+		snprintf(tmps, sizeof(tmps), "ns16550 irq=%s.cpu[%i]."
+		    "vrip.%i addr=0x%x name2=serial", machine->path,
+		    machine->bootstrap_cpu, VRIP_INTR_SIU, 0xc000000);
+		device_add(machine, tmps);
+	}
+
+	/*  Hm... maybe this should not be here.  TODO  */
+	snprintf(tmps, sizeof(tmps), "pcic irq=%s.cpu[%i].vrip.%i addr="
+	    "0x140003e0", machine->path, machine->bootstrap_cpu,
+	    VRIP_INTR_GIU);
+	device_add(machine, tmps);
+
+	machine_add_tickfunction(machine, dev_vr41xx_tick, d,
+	    DEV_VR41XX_TICKSHIFT);
+
+	/*  Some machines (?) use ISA space at 0x15000000 instead of
+	    0x14000000, eg IBM WorkPad Z50.  */
+	dev_ram_init(machine, 0x15000000, 0x1000000, DEV_RAM_MIRROR,
+	    0x14000000, NULL);
+
+	return d;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_vr41xx.cc gxemul-0.7.0+dfsg/src/devices/dev_vr41xx.cc
--- gxemul-0.6.2/src/devices/dev_vr41xx.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_vr41xx.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,807 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: VR41xx (VR4122 and VR4131) misc functions
- *
- *  This is just a big hack.
- *
- *  TODO: Implement more functionality some day.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "timer.h"
-
-#include "thirdparty/bcureg.h"
-#include "thirdparty/vripreg.h"
-#include "thirdparty/vrkiureg.h"
-#include "thirdparty/vr_rtcreg.h"
-
-
-/*  #define debug fatal  */
-
-#define	DEV_VR41XX_TICKSHIFT		14
-
-#define	DEV_VR41XX_LENGTH		0x800	/*  TODO?  */
-struct vr41xx_data {
-	struct interrupt cpu_irq;		/*  Connected to MIPS irq 2  */
-	int		cpumodel;		/*  Model nr, e.g. 4121  */
-
-	/*  KIU:  */
-	int		kiu_console_handle;
-	uint32_t	kiu_offset;
-	struct interrupt kiu_irq;
-	int		kiu_int_assert;
-	int		old_kiu_int_assert;
-
-	int		d0, d1, d2, d3, d4, d5;
-	int		dont_clear_next;
-	int		escape_state;
-
-	/*  Timer:  */
-	int		pending_timer_interrupts;
-	struct interrupt timer_irq;
-	struct timer	*timer;
-
-	/*  See icureg.h in NetBSD for more info.  */
-	uint16_t	sysint1;
-	uint16_t	msysint1;
-	uint16_t	giuint;
-	uint16_t	giumask;
-	uint16_t	sysint2;
-	uint16_t	msysint2;
-	struct interrupt giu_irq;
-};
-
-
-/*
- *  vr41xx_vrip_interrupt_assert():
- *  vr41xx_vrip_interrupt_deassert():
- */ 
-void vr41xx_vrip_interrupt_assert(struct interrupt *interrupt)
-{
-	struct vr41xx_data *d = (struct vr41xx_data *) interrupt->extra;
-	int line = interrupt->line;
-	if (line < 16)
-		d->sysint1 |= (1 << line);
-	else
-		d->sysint2 |= (1 << (line-16));
-	if ((d->sysint1 & d->msysint1) | (d->sysint2 & d->msysint2))
-                INTERRUPT_ASSERT(d->cpu_irq);
-}
-void vr41xx_vrip_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct vr41xx_data *d = (struct vr41xx_data *) interrupt->extra;
-	int line = interrupt->line;
-	if (line < 16)
-		d->sysint1 &= ~(1 << line);
-	else
-		d->sysint2 &= ~(1 << (line-16));
-	if (!(d->sysint1 & d->msysint1) && !(d->sysint2 & d->msysint2))
-                INTERRUPT_DEASSERT(d->cpu_irq);
-}
-
-
-/*
- *  vr41xx_giu_interrupt_assert():
- *  vr41xx_giu_interrupt_deassert():
- */ 
-void vr41xx_giu_interrupt_assert(struct interrupt *interrupt)
-{
-	struct vr41xx_data *d = (struct vr41xx_data *) interrupt->extra;
-	int line = interrupt->line;
-	d->giuint |= (1 << line);
-	if (d->giuint & d->giumask)
-                INTERRUPT_ASSERT(d->giu_irq);
-}
-void vr41xx_giu_interrupt_deassert(struct interrupt *interrupt)
-{
-	struct vr41xx_data *d = (struct vr41xx_data *) interrupt->extra;
-	int line = interrupt->line;
-	d->giuint &= ~(1 << line);
-	if (!(d->giuint & d->giumask))
-                INTERRUPT_DEASSERT(d->giu_irq);
-}
-
-
-static void recalc_kiu_int_assert(struct cpu *cpu, struct vr41xx_data *d)
-{
-	if (d->kiu_int_assert != d->old_kiu_int_assert) {
-		d->old_kiu_int_assert = d->kiu_int_assert;
-		if (d->kiu_int_assert != 0)
-			INTERRUPT_ASSERT(d->kiu_irq);
-		else
-			INTERRUPT_DEASSERT(d->kiu_irq);
-	}
-}
-
-
-/*
- *  vr41xx_keytick():
- */
-static void vr41xx_keytick(struct cpu *cpu, struct vr41xx_data *d)
-{
-	int keychange = 0;
-
-	/*
-	 *  Keyboard input:
-	 *
-	 *  Hardcoded for MobilePro. (See NetBSD's hpckbdkeymap.h for
-	 *  info on other keyboard layouts. mobilepro780_keytrans is the
-	 *  one used here.)
-	 *
-	 *  TODO: Make this work with "any" keyboard layout.
-	 *
-	 *  ofs 0:
-	 *	8000='o' 4000='.' 2000=DOWN  1000=UP
-	 *	 800=';'  400='''  200='['    100=?
-	 *	  80='l'   40=CR    20=RIGHT   10=LEFT
-	 *	   8='/'    4='\'    2=']'      1=SPACE
-	 *  ofs 2:
-	 *	8000='a' 4000='s' 2000='d' 1000='f'
-	 *	 800='`'  400='-'  200='='  100=?
-	 *	  80='z'   40='x'   20='c'   10='v'
-	 *	   8=?      4=?      2=?
-	 *  ofs 4:
-	 *	8000='9' 4000='0' 2000=?   1000=?
-	 *	 800='b'  400='n'  200='m'  100=','
-	 *	  80='q'   40='w'   20='e'   10='r'
-	 *	   8='5'    4='6'    2='7'    1='8'
-	 *  ofs 6:
-	 *	8000=ESC 4000=DEL 2000=CAPS 1000=?
-	 *	 800='t'  400='y'  200='u'   100='i'
-	 *	  80='1'   40='2'   20='3'    10='4'
-	 *	   8='g'    4='h'    2='j'     1='k'
-	 *  ofs 8:
-	 *                      200=ALT_L
-	 *	  80=    40=TAB  20='p' 10=BS
-	 *	   8=     4=      2=     1=ALT_R
-	 *  ofs a:
-	 *	800=SHIFT 4=CTRL
-	 *
-	 *
-	 *  The following are for the IBM WorkPad Z50:
-	 *  (Not yet implemented, TODO)
-	 *
-	 *  00    f1      f3      f5      f7      f9      -       -       f11
-	 *  08    f2      f4      f6      f8      f10     -       -       f12
-	 *  10    '       [       -       0       p       ;       up      /
-	 *  18    -       -       -       9       o       l       .       -
-	 *  20    left    ]       =       8       i       k       ,       -
-	 *  28    h       y       6       7       u       j       m       n
-	 *  30    -       bs      num     del     -       \       ent     sp
-	 *  38    g       t       5       4       r       f       v       b
-	 *  40    -       -       -       3       e       d       c       right
-	 *  48    -       -       -       2       w       s       x       down
-	 *  50    esc     tab     ~       1       q       a       z       -
-	 *  58    menu    Ls      Lc      Rc      La      Ra      Rs      -
-	 */
-
-	if (d->d0 != 0 || d->d1 != 0 || d->d2 != 0 ||
-	    d->d3 != 0 || d->d4 != 0 || d->d5 != 0)
-		keychange = 1;
-
-	/*  Release all keys:  */
-	if (!d->dont_clear_next) {
-		d->d0 = d->d1 = d->d2 = d->d3 = d->d4 = d->d5 = 0;
-	} else
-		d->dont_clear_next = 0;
-
-	if (console_charavail(d->kiu_console_handle)) {
-		char ch = console_readchar(d->kiu_console_handle);
-
-		if (d->escape_state > 0) {
-			switch (d->escape_state) {
-			case 1:	/*  expecting a [  */
-				d->escape_state = 0;
-				if (ch == '[')
-					d->escape_state = 2;
-				break;
-			case 2:	/*  cursor keys etc:  */
-				/*  Ugly hack for Mobilepro770:  */
-				if (cpu->machine->machine_subtype ==
-				    MACHINE_HPCMIPS_NEC_MOBILEPRO_770) {
-					switch (ch) {
-					case 'A': d->d0 = 0x2000; break;
-					case 'B': d->d0 = 0x20; break;
-					case 'C': d->d0 = 0x1000; break;
-					case 'D': d->d0 = 0x10; break;
-					default:  fatal("[ vr41xx kiu: unimpl"
-					    "emented escape 0x%02 ]\n", ch);
-					}
-				} else {
-					switch (ch) {
-					case 'A': d->d0 = 0x1000; break;
-					case 'B': d->d0 = 0x2000; break;
-					case 'C': d->d0 = 0x20; break;
-					case 'D': d->d0 = 0x10; break;
-					default:  fatal("[ vr41xx kiu: unimpl"
-					    "emented escape 0x%02 ]\n", ch);
-					}
-				}
-				d->escape_state = 0;
-			}
-		} else switch (ch) {
-		case '+':	console_makeavail(d->kiu_console_handle, '=');
-				d->d5 = 0x800; break;
-		case '_':	console_makeavail(d->kiu_console_handle, '-');
-				d->d5 = 0x800; break;
-		case '<':	console_makeavail(d->kiu_console_handle, ',');
-				d->d5 = 0x800; break;
-		case '>':	console_makeavail(d->kiu_console_handle, '.');
-				d->d5 = 0x800; break;
-		case '{':	console_makeavail(d->kiu_console_handle, '[');
-				d->d5 = 0x800; break;
-		case '}':	console_makeavail(d->kiu_console_handle, ']');
-				d->d5 = 0x800; break;
-		case ':':	console_makeavail(d->kiu_console_handle, ';');
-				d->d5 = 0x800; break;
-		case '"':	console_makeavail(d->kiu_console_handle, '\'');
-				d->d5 = 0x800; break;
-		case '|':	console_makeavail(d->kiu_console_handle, '\\');
-				d->d5 = 0x800; break;
-		case '?':	console_makeavail(d->kiu_console_handle, '/');
-				d->d5 = 0x800; break;
-
-		case '!':	console_makeavail(d->kiu_console_handle, '1');
-				d->d5 = 0x800; break;
-		case '@':	console_makeavail(d->kiu_console_handle, '2');
-				d->d5 = 0x800; break;
-		case '#':	console_makeavail(d->kiu_console_handle, '3');
-				d->d5 = 0x800; break;
-		case '$':	console_makeavail(d->kiu_console_handle, '4');
-				d->d5 = 0x800; break;
-		case '%':	console_makeavail(d->kiu_console_handle, '5');
-				d->d5 = 0x800; break;
-		case '^':	console_makeavail(d->kiu_console_handle, '6');
-				d->d5 = 0x800; break;
-		case '&':	console_makeavail(d->kiu_console_handle, '7');
-				d->d5 = 0x800; break;
-		case '*':	console_makeavail(d->kiu_console_handle, '8');
-				d->d5 = 0x800; break;
-		case '(':	console_makeavail(d->kiu_console_handle, '9');
-				d->d5 = 0x800; break;
-		case ')':	console_makeavail(d->kiu_console_handle, '0');
-				d->d5 = 0x800; break;
-
-		case '1':	d->d3 = 0x80; break;
-		case '2':	d->d3 = 0x40; break;
-		case '3':	d->d3 = 0x20; break;
-		case '4':	d->d3 = 0x10; break;
-		case '5':	d->d2 = 0x08; break;
-		case '6':	d->d2 = 0x04; break;
-		case '7':	d->d2 = 0x02; break;
-		case '8':	d->d2 = 0x01; break;
-		case '9':	d->d2 = 0x8000; break;
-		case '0':	d->d2 = 0x4000; break;
-
-		case ';':	d->d0 = 0x800; break;
-		case '\'':	d->d0 = 0x400; break;
-		case '[':	d->d0 = 0x200; break;
-		case '/':	d->d0 = 0x8; break;
-		case '\\':	d->d0 = 0x4; break;
-		case ']':	d->d0 = 0x2; break;
-
-		case 'a':	d->d1 = 0x8000; break;
-		case 'b':	d->d2 = 0x800; break;
-		case 'c':	d->d1 = 0x20; break;
-		case 'd':	d->d1 = 0x2000; break;
-		case 'e':	d->d2 = 0x20; break;
-		case 'f':	d->d1 = 0x1000; break;
-		case 'g':	d->d3 = 0x8; break;
-		case 'h':	d->d3 = 0x4; break;
-		case 'i':	d->d3 = 0x100; break;
-		case 'j':	d->d3 = 0x2; break;
-		case 'k':	d->d3 = 0x1; break;
-		case 'l':	d->d0 = 0x80; break;
-		case 'm':	d->d2 = 0x200; break;
-		case 'n':	d->d2 = 0x400; break;
-		case 'o':	d->d0 = 0x8000; break;
-		case 'p':	d->d4 = 0x20; break;
-		case 'q':	d->d2 = 0x80; break;
-		case 'r':	d->d2 = 0x10; break;
-		case 's':	d->d1 = 0x4000; break;
-		case 't':	d->d3 = 0x800; break;
-		case 'u':	d->d3 = 0x200; break;
-		case 'v':	d->d1 = 0x10; break;
-		case 'w':	d->d2 = 0x40; break;
-		case 'x':	d->d1 = 0x40; break;
-		case 'y':	d->d3 = 0x400; break;
-		case 'z':	d->d1 = 0x80; break;
-
-		case ',':	d->d2 = 0x100; break;
-		case '.':	d->d0 = 0x4000; break;
-		case '-':	d->d1 = 0x400; break;
-		case '=':	d->d1 = 0x200; break;
-
-		case '\r':
-		case '\n':	d->d0 = 0x40; break;
-		case ' ':	d->d0 = 0x01; break;
-		case '\b':	d->d4 = 0x10; break;
-
-		case 27:	d->escape_state = 1; break;
-
-		default:
-			/*  Shifted:  */
-			if (ch >= 'A' && ch <= 'Z') {
-				console_makeavail(d->kiu_console_handle,
-				    ch + 32);
-				d->d5 = 0x800;
-				d->dont_clear_next = 1;
-				break;
-			}
-
-			/*  CTRLed:  */
-			if (ch >= 1 && ch <= 26) {
-				console_makeavail(d->kiu_console_handle,
-				    ch + 96);
-				d->d5 = 0x4;
-				d->dont_clear_next = 1;
-				break;
-			}
-		}
-
-		if (d->escape_state == 0)
-			keychange = 1;
-	}
-
-	if (keychange) {
-		/*  4=lost data, 2=data complete, 1=key input detected  */
-		d->kiu_int_assert |= 3;
-		recalc_kiu_int_assert(cpu, d);
-	}
-}
-
-
-/*
- *  timer_tick():
- */
-static void timer_tick(struct timer *timer, void *extra)
-{
-	struct vr41xx_data *d = (struct vr41xx_data *) extra;
-	d->pending_timer_interrupts ++;
-}
-
-
-DEVICE_TICK(vr41xx)
-{
-	struct vr41xx_data *d = (struct vr41xx_data *) extra;
-
-	if (d->pending_timer_interrupts > 0)
-		INTERRUPT_ASSERT(d->timer_irq);
-
-	if (cpu->machine->x11_md.in_use)
-		vr41xx_keytick(cpu, d);
-}
-
-
-/*
- *  vr41xx_kiu():
- *
- *  Keyboard Interface Unit. Return value is "odata".
- *  (See NetBSD's vrkiu.c for more info.)
- */
-static uint64_t vr41xx_kiu(struct cpu *cpu, int ofs, uint64_t idata,
-	int writeflag, struct vr41xx_data *d)
-{
-	uint64_t odata = 0;
-
-	switch (ofs) {
-	case KIUDAT0:
-		odata = d->d0; break;
-	case KIUDAT1:
-		odata = d->d1; break;
-	case KIUDAT2:
-		odata = d->d2; break;
-	case KIUDAT3:
-		odata = d->d3; break;
-	case KIUDAT4:
-		odata = d->d4; break;
-	case KIUDAT5:
-		odata = d->d5; break;
-	case KIUSCANREP:
-		if (writeflag == MEM_WRITE) {
-			debug("[ vr41xx KIU: setting KIUSCANREP to 0x%04x ]\n",
-			    (int)idata);
-			/*  TODO  */
-		} else
-			fatal("[ vr41xx KIU: unimplemented read from "
-			    "KIUSCANREP ]\n");
-		break;
-	case KIUSCANS:
-		if (writeflag == MEM_WRITE) {
-			debug("[ vr41xx KIU: write to KIUSCANS: 0x%04x: TODO"
-			    " ]\n", (int)idata);
-			/*  TODO  */
-		} else
-			debug("[ vr41xx KIU: unimplemented read from "
-			    "KIUSCANS ]\n");
-		break;
-	case KIUINT:
-		/*  Interrupt. A wild guess: zero-on-write  */
-		if (writeflag == MEM_WRITE) {
-			d->kiu_int_assert &= ~idata;
-		} else {
-			odata = d->kiu_int_assert;
-		}
-		recalc_kiu_int_assert(cpu, d);
-		break;
-	case KIURST:
-		/*  Reset.  */
-		break;
-	default:
-		if (writeflag == MEM_WRITE)
-			debug("[ vr41xx KIU: unimplemented write to offset "
-			    "0x%x, data=0x%016" PRIx64" ]\n", ofs,
-			    (uint64_t) idata);
-		else
-			debug("[ vr41xx KIU: unimplemented read from offset "
-			    "0x%x ]\n", ofs);
-	}
-
-	return odata;
-}
-
-
-DEVICE_ACCESS(vr41xx)
-{
-	struct vr41xx_data *d = (struct vr41xx_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int regnr;
-	int revision = 0;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	regnr = relative_addr / sizeof(uint64_t);
-
-	/*  KIU ("Keyboard Interface Unit") is handled separately.  */
-	if (relative_addr >= d->kiu_offset &&
-	    relative_addr < d->kiu_offset + 0x20) {
-		odata = vr41xx_kiu(cpu, relative_addr - d->kiu_offset,
-		    idata, writeflag, d);
-		goto ret;
-	}
-
-	/*  TODO: Maybe these should be handled separately as well?  */
-
-	switch (relative_addr) {
-
-	/*  BCU:  0x00 .. 0x1c  */
-	case BCUREVID_REG_W:	/*  0x010  */
-	case BCU81REVID_REG_W:	/*  0x014  */
-		/*
-		 *  TODO?  Linux seems to read 0x14. The lowest bits are
-		 *  a divisor for PClock, bits 8 and up seem to be a
-		 *  divisor for VTClock (relative to PClock?)...
-		 */
-		switch (d->cpumodel) {
-		case 4131:	revision = BCUREVID_RID_4131; break;
-		case 4122:	revision = BCUREVID_RID_4122; break;
-		case 4121:	revision = BCUREVID_RID_4121; break;
-		case 4111:	revision = BCUREVID_RID_4111; break;
-		case 4102:	revision = BCUREVID_RID_4102; break;
-		case 4101:	revision = BCUREVID_RID_4101; break;
-		case 4181:	revision = BCUREVID_RID_4181; break;
-		}
-		odata = (revision << BCUREVID_RIDSHFT) | 0x020c;
-		break;
-	case BCU81CLKSPEED_REG_W:	/*  0x018  */
-		/*
-		 *  TODO: Implement this for ALL cpu types:
-		 */
-		odata = BCUCLKSPEED_DIVT4 << BCUCLKSPEED_DIVTSHFT;
-		break;
-
-	/*  DMAAU:  0x20 .. 0x3c  */
-
-	/*  DCU:  0x40 .. 0x5c  */
-
-	/*  CMU:  0x60 .. 0x7c  */
-
-	/*  ICU:  0x80 .. 0xbc  */
-	case 0x80:	/*  Level 1 system interrupt reg 1...  */
-		if (writeflag == MEM_READ)
-			odata = d->sysint1;
-		else {
-			/*  TODO: clear-on-write-one?  */
-			d->sysint1 &= ~idata;
-			d->sysint1 &= 0xffff;
-		}
-		break;
-	case 0x88:
-		if (writeflag == MEM_READ)
-			odata = d->giuint;
-		else
-			d->giuint &= ~idata;
-		break;
-	case 0x8c:
-		if (writeflag == MEM_READ)
-			odata = d->msysint1;
-		else
-			d->msysint1 = idata;
-		break;
-	case 0x94:
-		if (writeflag == MEM_READ)
-			odata = d->giumask;
-		else
-			d->giumask = idata;
-		break;
-	case 0xa0:	/*  Level 1 system interrupt reg 2...  */
-		if (writeflag == MEM_READ)
-			odata = d->sysint2;
-		else {
-			/*  TODO: clear-on-write-one?  */
-			d->sysint2 &= ~idata;
-			d->sysint2 &= 0xffff;
-		}
-		break;
-	case 0xa6:
-		if (writeflag == MEM_READ)
-			odata = d->msysint2;
-		else
-			d->msysint2 = idata;
-		break;
-
-	/*  RTC:  */
-	case 0xc0:
-	case 0xc2:
-	case 0xc4:
-		{
-			struct timeval tv;
-			gettimeofday(&tv, NULL);
-			/*  Adjust time by 120 years and 29 days.  */
-			tv.tv_sec += (int64_t) (120*365 + 29) * 24*60*60;
-
-			switch (relative_addr) {
-			case 0xc0:
-				odata = (tv.tv_sec & 1) << 15;
-				odata += (uint64_t)tv.tv_usec * 32768 / 1000000;
-				break;
-			case 0xc2:
-				odata = (tv.tv_sec >> 1) & 0xffff;
-				break;
-			case 0xc4:
-				odata = (tv.tv_sec >> 17) & 0xffff;
-				break;
-			}
-		}
-		break;
-
-	case 0xd0:	/*  RTCL1_L_REG_W  */
-		if (writeflag == MEM_WRITE && idata != 0) {
-			int hz = RTCL1_L_HZ / idata;
-			debug("[ vr41xx: rtc interrupts at %i Hz ]\n", hz);
-			if (d->timer == NULL)
-				d->timer = timer_add(hz, timer_tick, d);
-			else
-				timer_update_frequency(d->timer, hz);
-		}
-		break;
-	case 0xd2:	/*  RTCL1_H_REG_W  */
-		break;
-
-	case 0x108:
-		if (writeflag == MEM_READ)
-			odata = d->giuint;
-		else
-			d->giuint &= ~idata;
-		break;
-	/*  case 0x10a:
-		"High" part of GIU?
-		break;
-	*/
-
-	case 0x13e:	/*  on 4181?  */
-	case 0x1de:	/*  on 4121?  */
-		/*  RTC interrupt register...  */
-		/*  Ack. timer interrupts?  */
-		INTERRUPT_DEASSERT(d->timer_irq);
-		if (d->pending_timer_interrupts > 0)
-			d->pending_timer_interrupts --;
-		break;
-
-	default:
-		if (writeflag == MEM_WRITE)
-			debug("[ vr41xx: unimplemented write to address "
-			    "0x%" PRIx64", data=0x%016" PRIx64" ]\n",
-			    (uint64_t) relative_addr, (uint64_t) idata);
-		else
-			debug("[ vr41xx: unimplemented read from address "
-			    "0x%" PRIx64" ]\n", (uint64_t) relative_addr);
-	}
-
-ret:
-	/*
-	 *  Recalculate interrupt assertions:
-	 */
-	if (d->giuint & d->giumask)
-                INTERRUPT_ASSERT(d->giu_irq);
-	else
-                INTERRUPT_DEASSERT(d->giu_irq);
-	if ((d->sysint1 & d->msysint1) | (d->sysint2 & d->msysint2))
-                INTERRUPT_ASSERT(d->cpu_irq);
-	else
-                INTERRUPT_DEASSERT(d->cpu_irq);
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	return 1;
-}
-
-
-/*
- *  dev_vr41xx_init():
- *
- *  machine->path is something like "machine[0]".
- */
-struct vr41xx_data *dev_vr41xx_init(struct machine *machine,
-	struct memory *mem, int cpumodel)
-{
-	struct vr41xx_data *d;
-	uint64_t baseaddr = 0;
-	char tmps[300];
-	int i;
-
-	CHECK_ALLOCATION(d = (struct vr41xx_data *) malloc(sizeof(struct vr41xx_data)));
-	memset(d, 0, sizeof(struct vr41xx_data));
-
-	/*  Connect to MIPS irq 2:  */
-	snprintf(tmps, sizeof(tmps), "%s.cpu[%i].2",
-	    machine->path, machine->bootstrap_cpu);
-	INTERRUPT_CONNECT(tmps, d->cpu_irq);
-
-	/*
-	 *  Register VRIP interrupt lines 0..25:
-	 */
-	for (i=0; i<=25; i++) {
-		struct interrupt templ;
-		snprintf(tmps, sizeof(tmps), "%s.cpu[%i].vrip.%i",
-		    machine->path, machine->bootstrap_cpu, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = i;
-		templ.name = tmps;
-		templ.extra = d;
-		templ.interrupt_assert = vr41xx_vrip_interrupt_assert;
-		templ.interrupt_deassert = vr41xx_vrip_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	/*
-	 *  Register GIU interrupt lines 0..31:
-	 */
-	for (i=0; i<32; i++) {
-		struct interrupt templ;
-		snprintf(tmps, sizeof(tmps), "%s.cpu[%i].vrip.%i.giu.%i",
-		    machine->path, machine->bootstrap_cpu, VRIP_INTR_GIU, i);
-		memset(&templ, 0, sizeof(templ));
-		templ.line = i;
-		templ.name = tmps;
-		templ.extra = d;
-		templ.interrupt_assert = vr41xx_giu_interrupt_assert;
-		templ.interrupt_deassert = vr41xx_giu_interrupt_deassert;
-		interrupt_handler_register(&templ);
-	}
-
-	d->cpumodel = cpumodel;
-
-	/*  TODO: VRC4173 has the KIU at offset 0x100?  */
-	d->kiu_offset = 0x180;
-	d->kiu_console_handle = -1;
-	if (machine->x11_md.in_use)
-		d->kiu_console_handle = console_start_slave_inputonly(
-		    machine, "kiu", 1);
-
-	/*  Connect to the KIU and GIU interrupts:  */
-	snprintf(tmps, sizeof(tmps), "%s.cpu[%i].vrip.%i",
-	    machine->path, machine->bootstrap_cpu, VRIP_INTR_GIU);
-	INTERRUPT_CONNECT(tmps, d->giu_irq);
-	snprintf(tmps, sizeof(tmps), "%s.cpu[%i].vrip.%i",
-	    machine->path, machine->bootstrap_cpu, VRIP_INTR_KIU);
-	INTERRUPT_CONNECT(tmps, d->kiu_irq);
-
-	if (machine->x11_md.in_use)
-		machine->main_console_handle = d->kiu_console_handle;  
-
-	switch (cpumodel) {
-	case 4101:
-	case 4102:
-	case 4111:
-	case 4121:
-		baseaddr = 0xb000000;
-		break;
-	case 4181:
-		baseaddr = 0xa000000;
-		dev_ram_init(machine, 0xb000000, 0x1000000, DEV_RAM_MIRROR,
-		    0xa000000);
-		break;
-	case 4122:
-	case 4131:
-		baseaddr = 0xf000000;
-		break;
-	default:
-		printf("Unimplemented VR cpu model\n");
-		exit(1);
-	}
-
-	if (d->cpumodel == 4121 || d->cpumodel == 4181)
-		snprintf(tmps, sizeof(tmps), "%s.cpu[%i].3",
-		    machine->path, machine->bootstrap_cpu);
-	else
-		snprintf(tmps, sizeof(tmps), "%s.cpu[%i].vrip.%i",
-		    machine->path, machine->bootstrap_cpu, VRIP_INTR_ETIMER);
-	INTERRUPT_CONNECT(tmps, d->timer_irq);
-
-	memory_device_register(mem, "vr41xx", baseaddr, DEV_VR41XX_LENGTH,
-	    dev_vr41xx_access, (void *)d, DM_DEFAULT, NULL);
-
-	/*
-	 *  TODO: Find out which controllers are at which addresses on
-	 *  which chips.
-	 */
-	if (cpumodel == 4131) {
-		snprintf(tmps, sizeof(tmps), "ns16550 irq=%s.cpu[%i].vrip.%i "
-		    "addr=0x%" PRIx64" name2=siu", machine->path,
-		    machine->bootstrap_cpu, VRIP_INTR_SIU,
-		    (uint64_t) (baseaddr+0x800));
-		device_add(machine, tmps);
-	} else {
-		/*  This is used by Linux and NetBSD:  */
-		snprintf(tmps, sizeof(tmps), "ns16550 irq=%s.cpu[%i]."
-		    "vrip.%i addr=0x%x name2=serial", machine->path,
-		    machine->bootstrap_cpu, VRIP_INTR_SIU, 0xc000000);
-		device_add(machine, tmps);
-	}
-
-	/*  Hm... maybe this should not be here.  TODO  */
-	snprintf(tmps, sizeof(tmps), "pcic irq=%s.cpu[%i].vrip.%i addr="
-	    "0x140003e0", machine->path, machine->bootstrap_cpu,
-	    VRIP_INTR_GIU);
-	device_add(machine, tmps);
-
-	machine_add_tickfunction(machine, dev_vr41xx_tick, d,
-	    DEV_VR41XX_TICKSHIFT);
-
-	/*  Some machines (?) use ISA space at 0x15000000 instead of
-	    0x14000000, eg IBM WorkPad Z50.  */
-	dev_ram_init(machine, 0x15000000, 0x1000000, DEV_RAM_MIRROR,
-	    0x14000000);
-
-	return d;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_wdc.c gxemul-0.7.0+dfsg/src/devices/dev_wdc.c
--- gxemul-0.6.2/src/devices/dev_wdc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_wdc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,966 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Standard "wdc" IDE controller
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/wdcreg.h"
+
+
+#define	DEV_WDC_LENGTH		8
+#define	WDC_TICK_SHIFT		14
+#define	WDC_MAX_SECTORS		512
+#define	WDC_INBUF_SIZE		(512*(WDC_MAX_SECTORS+1))
+
+extern int quiet_mode;
+
+/*  #define debug fatal  */
+
+struct wdc_data {
+	struct interrupt irq;
+	int		addr_mult;
+	int		base_drive;
+	int		data_debug;
+	int		io_enabled;
+
+	/*  Cached values:  */
+	int		cyls[2];
+	int		heads[2];
+	int		sectors_per_track[2];
+
+	unsigned char	*inbuf;
+	int		inbuf_head;
+	int		inbuf_tail;
+
+	int		int_assert;
+
+	int		write_in_progress;
+	int		write_count;
+	int64_t		write_offset;
+
+	int		error;
+	int		precomp;
+	int		seccnt;
+	int		sector;
+	int		cyl_lo;
+	int		cyl_hi;
+	int		sectorsize;
+	int		lba;
+	int		drive;
+	int		head;
+	int		cur_command;
+
+	int		atapi_cmd_in_progress;
+	int		atapi_phase;
+	struct scsi_transfer *atapi_st;
+	int		atapi_len;
+	size_t		atapi_received;
+
+	unsigned char	identify_struct[512];
+};
+
+
+#define COMMAND_RESET	0x100
+
+
+DEVICE_TICK(wdc)
+{ 
+	struct wdc_data *d = (struct wdc_data *) extra;
+
+	if (d->int_assert)
+		INTERRUPT_ASSERT(d->irq);
+}
+
+
+/*
+ *  wdc_set_io_enabled():
+ *
+ *  Set io_enabled to zero to disable the I/O registers temporarily (e.g.
+ *  used by PCI code in NetBSD to detect whether multiple controllers collide
+ *  in I/O space).
+ *
+ *  Return value is old contents of the io_enabled variable.
+ */
+int wdc_set_io_enabled(struct wdc_data *d, int io_enabled)
+{
+	int old = d->io_enabled;
+	d->io_enabled = io_enabled;
+	return old;
+}
+
+
+/*
+ *  wdc_addtoinbuf():
+ *
+ *  Write to the inbuf at its head, read at its tail.
+ */
+static void wdc_addtoinbuf(struct wdc_data *d, int c)
+{
+	d->inbuf[d->inbuf_head] = c;
+
+	d->inbuf_head = (d->inbuf_head + 1) % WDC_INBUF_SIZE;
+	if (d->inbuf_head == d->inbuf_tail)
+		fatal("[ wdc_addtoinbuf(): WARNING! wdc inbuf overrun!"
+		    " Increase WDC_MAX_SECTORS. ]\n");
+}
+
+
+/*
+ *  wdc_get_inbuf():
+ *
+ *  Read from the tail of inbuf.
+ */
+static uint64_t wdc_get_inbuf(struct wdc_data *d)
+{
+	int c = d->inbuf[d->inbuf_tail];
+
+	if (d->inbuf_head == d->inbuf_tail) {
+		fatal("[ wdc: WARNING! someone is reading too much from the "
+		    "wdc inbuf! ]\n");
+		return (uint64_t) -1;
+	}
+
+	d->inbuf_tail = (d->inbuf_tail + 1) % WDC_INBUF_SIZE;
+	return c;
+}
+
+
+/*
+ *  wdc_initialize_identify_struct():
+ */
+static void wdc_initialize_identify_struct(struct cpu *cpu, struct wdc_data *d)
+{
+	uint64_t total_size;
+	int flags, cdrom = 0;
+	char namebuf[40];
+
+	total_size = diskimage_getsize(cpu->machine, d->drive + d->base_drive,
+	    DISKIMAGE_IDE);
+	if (diskimage_is_a_cdrom(cpu->machine, d->drive + d->base_drive,
+	    DISKIMAGE_IDE))
+		cdrom = 1;
+
+	memset(d->identify_struct, 0, sizeof(d->identify_struct));
+
+	/*  Offsets are in 16-bit WORDS!  High byte, then low.  */
+
+	/*  0: general flags  */
+	flags = 1 << 6;	/*  Fixed  */
+	if (cdrom)
+		flags = 0x8580;		/*  ATAPI, CDROM, removable  */
+	d->identify_struct[2 * 0 + 0] = flags >> 8;
+	d->identify_struct[2 * 0 + 1] = flags;
+
+	/*  1: nr of cylinders  */
+	d->identify_struct[2 * 1 + 0] = d->cyls[d->drive] >> 8;
+	d->identify_struct[2 * 1 + 1] = d->cyls[d->drive];
+
+	/*  3: nr of heads  */
+	d->identify_struct[2 * 3 + 0] = d->heads[d->drive] >> 8;
+	d->identify_struct[2 * 3 + 1] = d->heads[d->drive];
+
+	/*  6: sectors per track  */
+	d->identify_struct[2 * 6 + 0] = d->sectors_per_track[d->drive] >> 8;
+	d->identify_struct[2 * 6 + 1] = d->sectors_per_track[d->drive];
+
+	/*  10-19: Serial number  */
+	memcpy(&d->identify_struct[2 * 10], "#0                  ", 20);
+
+	/*  23-26: Firmware version  */
+	memcpy(&d->identify_struct[2 * 23], "1.0     ", 8);
+
+	/*  27-46: Model number  */
+	if (diskimage_getname(cpu->machine, d->drive + d->base_drive,
+	    DISKIMAGE_IDE, namebuf, sizeof(namebuf))) {
+		size_t i;
+		for (i=0; i<sizeof(namebuf); i++)
+			if (namebuf[i] == 0) {
+				for (; i<sizeof(namebuf); i++)
+					namebuf[i] = ' ';
+				break;
+			}
+		memcpy(&d->identify_struct[2 * 27], namebuf, 40);
+	} else
+		memcpy(&d->identify_struct[2 * 27],
+		    "Fake GXemul IDE disk                    ", 40);
+
+	/*  47: max sectors per multitransfer  */
+	d->identify_struct[2 * 47 + 0] = 0x80;
+	d->identify_struct[2 * 47 + 1] = 128;
+
+	/*  49: capabilities:  */
+	/*  (0x200 = LBA, 0x100 = DMA support.)  */
+	d->identify_struct[2 * 49 + 0] = 0;
+	d->identify_struct[2 * 49 + 1] = 0;
+
+	/*  51: PIO timing mode.  */
+	d->identify_struct[2 * 51 + 0] = 0x00;	/*  ?  */
+	d->identify_struct[2 * 51 + 1] = 0x00;
+
+	/*  53: 0x02 = fields 64-70 valid, 0x01 = fields 54-58 valid  */
+	d->identify_struct[2 * 53 + 0] = 0x00;
+	d->identify_struct[2 * 53 + 1] = 0x02;
+
+	/*  57-58: current capacity in sectors  */
+	d->identify_struct[2 * 58 + 0] = ((total_size / 512) >> 24) % 255;
+	d->identify_struct[2 * 58 + 1] = ((total_size / 512) >> 16) % 255;
+	d->identify_struct[2 * 57 + 0] = ((total_size / 512) >> 8) % 255;
+	d->identify_struct[2 * 57 + 1] = (total_size / 512) & 255;
+
+	/*  60-61: total nr of addressable sectors  */
+	d->identify_struct[2 * 61 + 0] = ((total_size / 512) >> 24) % 255;
+	d->identify_struct[2 * 61 + 1] = ((total_size / 512) >> 16) % 255;
+	d->identify_struct[2 * 60 + 0] = ((total_size / 512) >> 8) % 255;
+	d->identify_struct[2 * 60 + 1] = (total_size / 512) & 255;
+
+	/*  64: Advanced PIO mode support. 0x02 = mode4, 0x01 = mode3  */
+	d->identify_struct[2 * 64 + 0] = 0x00;
+	d->identify_struct[2 * 64 + 1] = 0x03;
+
+	/*  67, 68: PIO timing  */
+	d->identify_struct[2 * 67 + 0] = 0;
+	d->identify_struct[2 * 67 + 1] = 120;
+	d->identify_struct[2 * 68 + 0] = 0;
+	d->identify_struct[2 * 68 + 1] = 120;
+}
+
+
+/*
+ *  wdc__read():
+ */
+void wdc__read(struct cpu *cpu, struct wdc_data *d)
+{
+#define MAX_SECTORS_PER_CHUNK	64
+	const int max_sectors_per_chunk = MAX_SECTORS_PER_CHUNK;
+	unsigned char buf[512 * MAX_SECTORS_PER_CHUNK];
+	int i, cyl = d->cyl_hi * 256+ d->cyl_lo;
+	int count = d->seccnt? d->seccnt : 256;
+	uint64_t offset = 512 * (d->sector - 1
+	    + (int64_t)d->head * d->sectors_per_track[d->drive] +
+	    (int64_t)d->heads[d->drive] * d->sectors_per_track[d->drive] * cyl);
+
+#if 0
+	/*  LBA:  */
+	if (d->lba)
+		offset = 512 * (((d->head & 0xf) << 24) + (cyl << 8)
+		    + d->sector);
+	printf("WDC read from offset %lli\n", (long long)offset);
+#endif
+
+	while (count > 0) {
+		int to_read = count > max_sectors_per_chunk?
+		    max_sectors_per_chunk : count;
+
+		/*  TODO: result code from the read?  */
+
+		if (d->inbuf_head + 512 * to_read <= WDC_INBUF_SIZE) {
+			diskimage_access(cpu->machine, d->drive + d->base_drive,
+			    DISKIMAGE_IDE, 0, offset,
+			    d->inbuf + d->inbuf_head, 512 * to_read);
+			d->inbuf_head += 512 * to_read;
+			if (d->inbuf_head == WDC_INBUF_SIZE)
+				d->inbuf_head = 0;
+		} else {
+			diskimage_access(cpu->machine, d->drive + d->base_drive,
+			    DISKIMAGE_IDE, 0, offset, buf, 512 * to_read);
+			for (i=0; i<512 * to_read; i++)
+				wdc_addtoinbuf(d, buf[i]);
+		}
+
+		offset += 512 * to_read;
+		count -= to_read;
+	}
+
+	d->int_assert = 1;
+}
+
+
+/*
+ *  wdc__write():
+ */
+void wdc__write(struct cpu *cpu, struct wdc_data *d)
+{
+	int cyl = d->cyl_hi * 256+ d->cyl_lo;
+	int count = d->seccnt? d->seccnt : 256;
+	uint64_t offset = 512 * (d->sector - 1
+	    + (int64_t)d->head * d->sectors_per_track[d->drive] +
+	    (int64_t)d->heads[d->drive] * d->sectors_per_track[d->drive] * cyl);
+#if 0
+	/*  LBA:  */
+	if (d->lba)
+		offset = 512 * (((d->head & 0xf) << 24) +
+		    (cyl << 8) + d->sector);
+	printf("WDC write to offset %lli\n", (long long)offset);
+#endif
+
+	d->write_in_progress = d->cur_command;
+	d->write_count = count;
+	d->write_offset = offset;
+
+	/*  TODO: result code?  */
+}
+
+
+/*
+ *  status_byte():
+ *
+ *  Return a reasonable status byte corresponding to the controller's current
+ *  state.
+ */
+static int status_byte(struct wdc_data *d, struct cpu *cpu)
+{
+	int odata = 0;
+	if (diskimage_exist(cpu->machine, d->drive + d->base_drive,
+	    DISKIMAGE_IDE))
+		odata |= WDCS_DRDY | WDCS_DSC;
+	if (d->inbuf_head != d->inbuf_tail)
+		odata |= WDCS_DRQ;
+	if (d->write_in_progress)
+		odata |= WDCS_DRQ;
+	if (d->error)
+		odata |= WDCS_ERR;
+	if (d->atapi_cmd_in_progress && (d->atapi_phase & WDCS_DRQ)) {
+		odata |= WDCS_DRQ;
+	}
+	return odata;
+}
+
+
+DEVICE_ACCESS(wdc_altstatus)
+{
+	struct wdc_data *d = (struct wdc_data *) extra;
+	uint64_t idata = 0, odata = 0;
+
+	idata = data[0];
+
+	/*  Same as the normal status byte:  */
+	odata = status_byte(d, cpu);
+
+	if (writeflag==MEM_READ)
+		debug("[ wdc: read from ALTSTATUS: 0x%02x ]\n",
+		    (int)odata);
+	else {
+		debug("[ wdc: write to ALT. CTRL: 0x%02x ]\n",
+		    (int)idata);
+		if (idata & WDCTL_4BIT)
+			d->cur_command = COMMAND_RESET;
+	}
+
+	if (writeflag == MEM_READ)
+		data[0] = odata;
+
+	return 1;
+}
+
+
+/*
+ *  wdc_command():
+ */
+void wdc_command(struct cpu *cpu, struct wdc_data *d, int idata)
+{
+	size_t i;
+
+	d->cur_command = idata;
+	d->atapi_cmd_in_progress = 0;
+	d->error = 0;
+
+	/*
+	 *  Disk images that do not exist return an ABORT error.  This also
+	 *  happens with CDROM images with the WDCC_IDENTIFY command; CDROM
+	 *  images must be detected with ATAPI_IDENTIFY_DEVICE instead.
+	 *
+	 *  TODO:  Is this correct/good behaviour?
+	 */
+	if (!diskimage_exist(cpu->machine, d->drive + d->base_drive,
+	    DISKIMAGE_IDE)) {
+		debug("[ wdc: command 0x%02x drive %i, but no disk image ]\n",
+		    d->cur_command, d->drive + d->base_drive);
+		d->error |= WDCE_ABRT;
+		d->int_assert = 1;
+		return;
+	}
+	if (diskimage_is_a_cdrom(cpu->machine, d->drive + d->base_drive,
+	    DISKIMAGE_IDE) && d->cur_command == WDCC_IDENTIFY) {
+		debug("[ wdc: IDENTIFY drive %i, but it is an ATAPI "
+		    "drive ]\n", d->drive + d->base_drive);
+		d->error |= WDCE_ABRT;
+		d->int_assert = 1;
+		return;
+	}
+
+	/*  Handle the command:  */
+	switch (d->cur_command) {
+
+	case WDCC_READ:
+	case WDCC_READMULTI:
+		if (!quiet_mode)
+			debug("[ wdc: READ from drive %i, head %i, cyl %i, "
+			    "sector %i, nsecs %i ]\n", d->drive, d->head,
+			    d->cyl_hi*256+d->cyl_lo, d->sector, d->seccnt);
+		wdc__read(cpu, d);
+		break;
+
+	case WDCC_WRITE:
+	case WDCC_WRITEMULTI:
+		if (!quiet_mode)
+			debug("[ wdc: WRITE to drive %i, head %i, cyl %i, "
+			    "sector %i, nsecs %i ]\n", d->drive, d->head,
+			    d->cyl_hi*256+d->cyl_lo, d->sector, d->seccnt);
+		wdc__write(cpu, d);
+		break;
+
+	case WDCC_IDP:	/*  Initialize drive parameters  */
+		debug("[ wdc: IDP drive %i (TODO) ]\n", d->drive);
+		/*  TODO  */
+		d->int_assert = 1;
+		break;
+
+	case SET_FEATURES:
+		debug("[ wdc: SET_FEATURES drive %i (TODO), feature 0x%02x ]\n",
+		    d->drive, d->precomp);
+		/*  TODO  */
+		switch (d->precomp) {
+		case WDSF_SET_MODE:
+			debug("[ wdc: WDSF_SET_MODE drive %i, pio/dma flags "
+			    "0x%02x ]\n", d->drive, d->seccnt);
+			break;
+		default:d->error |= WDCE_ABRT;
+		}
+		/*  TODO: always interrupt?  */
+		d->int_assert = 1;
+		break;
+
+	case WDCC_RECAL:
+		debug("[ wdc: RECAL drive %i ]\n", d->drive);
+		d->int_assert = 1;
+		break;
+
+	case WDCC_IDENTIFY:
+	case ATAPI_IDENTIFY_DEVICE:
+		debug("[ wdc: %sIDENTIFY drive %i ]\n", d->cur_command ==
+		    ATAPI_IDENTIFY_DEVICE? "ATAPI " : "", d->drive);
+		wdc_initialize_identify_struct(cpu, d);
+		/*  The IDENTIFY data is sent out in low/high byte order:  */
+		for (i=0; i<sizeof(d->identify_struct); i+=2) {
+			wdc_addtoinbuf(d, d->identify_struct[i+1]);
+			wdc_addtoinbuf(d, d->identify_struct[i+0]);
+		}
+		d->int_assert = 1;
+		break;
+
+	case WDCC_IDLE_IMMED:
+		debug("[ wdc: IDLE_IMMED drive %i ]\n", d->drive);
+		/*  TODO: interrupt here?  */
+		d->int_assert = 1;
+		break;
+
+	case WDCC_SETMULTI:
+		debug("[ wdc: SETMULTI drive %i ]\n", d->drive);
+		/*  TODO: interrupt here?  */
+		d->int_assert = 1;
+		break;
+
+	case ATAPI_SOFT_RESET:
+		debug("[ wdc: ATAPI_SOFT_RESET drive %i ]\n", d->drive);
+		/*  TODO: interrupt here?  */
+		d->int_assert = 1;
+		break;
+
+	case ATAPI_PKT_CMD:
+		debug("[ wdc: ATAPI_PKT_CMD drive %i ]\n", d->drive);
+		/*  TODO: interrupt here?  */
+		/*  d->int_assert = 1;  */
+		d->atapi_cmd_in_progress = 1;
+		d->atapi_phase = PHASE_CMDOUT;
+		break;
+
+	case WDCC_DIAGNOSE:
+		debug("[ wdc: WDCC_DIAGNOSE drive %i: TODO ]\n", d->drive);
+		/*  TODO: interrupt here?  */
+		d->int_assert = 1;
+		d->error = 1;		/*  No error?  */
+		break;
+
+	/*  Unsupported commands, without warning:  */
+	case WDCC_SEC_SET_PASSWORD:
+	case WDCC_SEC_UNLOCK:
+	case WDCC_SEC_ERASE_PREPARE:
+	case WDCC_SEC_ERASE_UNIT:
+	case WDCC_SEC_FREEZE_LOCK:
+	case WDCC_SEC_DISABLE_PASSWORD:
+		d->error |= WDCE_ABRT;
+		break;
+
+	default:/*  TODO  */
+		d->error |= WDCE_ABRT;
+		fatal("[ wdc: WARNING! Unimplemented command 0x%02x (drive %i,"
+		    " head %i, cyl %i, sector %i, nsecs %i) ]\n",
+		    d->cur_command, d->drive, d->head, d->cyl_hi*256+d->cyl_lo,
+		    d->sector, d->seccnt);
+	}
+}
+
+
+DEVICE_ACCESS(wdc)
+{
+	struct wdc_data *d = (struct wdc_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int i;
+
+	relative_addr /= d->addr_mult;
+
+	if (!d->io_enabled)
+		goto ret;
+
+	if (writeflag == MEM_WRITE) {
+		if (relative_addr == wd_data)
+			idata = memory_readmax64(cpu, data, len);
+		else {
+			if (len != 1)
+				fatal("[ wdc: WARNING! non-8-bit access on WRITE! ]\n");
+			idata = data[0];
+		}
+	}
+
+	switch (relative_addr) {
+
+	case wd_data:	/*  0: data  */
+		if (writeflag == MEM_READ) {
+			odata = wdc_get_inbuf(d);
+
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+				if (len >= 2)
+					odata += (wdc_get_inbuf(d) << 8);
+				if (len == 4) {
+					odata += (wdc_get_inbuf(d) << 16);
+					odata += (wdc_get_inbuf(d) << 24);
+				}
+			} else {
+				if (len >= 2)
+					odata = (odata << 8) + wdc_get_inbuf(d);
+				if (len == 4) {
+					odata = (odata << 8) + wdc_get_inbuf(d);
+					odata = (odata << 8) + wdc_get_inbuf(d);
+				}
+			}
+
+			if (d->data_debug) {
+				const char *s = "0x%04" PRIx64" ]\n";
+				if (len == 1)
+					s = "0x%02" PRIx64" ]\n";
+				if (len == 4)
+					s = "0x%08" PRIx64" ]\n";
+				if (len == 8)
+					s = "0x%016" PRIx64" ]\n";
+				debug("[ wdc: read from DATA: ");
+				debug(s, (uint64_t) odata);
+			}
+
+			if (d->atapi_cmd_in_progress) {
+				d->atapi_len -= len;
+				d->atapi_received += len;
+				if (d->atapi_len == 0) {
+					if (d->atapi_received < d->atapi_st->
+					    data_in_len) {
+						d->atapi_phase = PHASE_DATAIN;
+						d->atapi_len = d->atapi_st->
+						    data_in_len -
+						    d->atapi_received;
+						if (d->atapi_len > 32768)
+							d->atapi_len = 0;
+					} else
+						d->atapi_phase =
+						    PHASE_COMPLETED;
+					d->int_assert = 1;
+				}
+			} else {
+#if 0
+				if (d->inbuf_tail != d->inbuf_head)
+#else
+				if (d->inbuf_tail != d->inbuf_head &&
+				    ((d->inbuf_tail - d->inbuf_head) % 512)
+				    == 0)
+#endif
+					d->int_assert = 1;
+			}
+		} else {
+			int inbuf_len;
+			if (d->data_debug) {
+				const char *s = "0x%04" PRIx64" ]\n";
+				if (len == 1)
+					s = "0x%02" PRIx64" ]\n";
+				if (len == 4)
+					s = "0x%08" PRIx64" ]\n";
+				if (len == 8)
+					s = "0x%016" PRIx64" ]\n";
+				debug("[ wdc: write to DATA: ");
+				debug(s, (uint64_t) idata);
+			}
+			if (!d->write_in_progress &&
+			    !d->atapi_cmd_in_progress) {
+				fatal("[ wdc: write to DATA, but not "
+				    "expecting any? (len=%i): 0x%08lx ]\n",
+				    (int)len, (long)idata);
+			}
+
+			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+				switch (len) {
+				case 4:	wdc_addtoinbuf(d, idata & 0xff);
+					wdc_addtoinbuf(d, (idata >> 8) & 0xff);
+					wdc_addtoinbuf(d, (idata >> 16) & 0xff);
+					wdc_addtoinbuf(d, (idata >> 24) & 0xff);
+					break;
+				case 2:	wdc_addtoinbuf(d, idata & 0xff);
+					wdc_addtoinbuf(d, (idata >> 8) & 0xff);
+					break;
+				case 1:	wdc_addtoinbuf(d, idata); break;
+				default:fatal("wdc: unimplemented write "
+					    "len %i\n", len);
+					exit(1);
+				}
+			} else {
+				switch (len) {
+				case 4:	wdc_addtoinbuf(d, (idata >> 24) & 0xff);
+					wdc_addtoinbuf(d, (idata >> 16) & 0xff);
+					wdc_addtoinbuf(d, (idata >> 8) & 0xff);
+					wdc_addtoinbuf(d, idata & 0xff);
+					break;
+				case 2:	wdc_addtoinbuf(d, (idata >> 8) & 0xff);
+					wdc_addtoinbuf(d, idata & 0xff);
+					break;
+				case 1:	wdc_addtoinbuf(d, idata); break;
+				default:fatal("wdc: unimplemented write "
+					    "len %i\n", len);
+					exit(1);
+				}
+			}
+
+			inbuf_len = d->inbuf_head - d->inbuf_tail;
+			while (inbuf_len < 0)
+				inbuf_len += WDC_INBUF_SIZE;
+
+			if (d->atapi_cmd_in_progress && inbuf_len == 12) {
+				unsigned char *scsi_cmd;
+				int x = 0, res;
+
+				CHECK_ALLOCATION(scsi_cmd = (unsigned char *) malloc(12));
+
+				if (d->atapi_st != NULL)
+					scsi_transfer_free(d->atapi_st);
+				d->atapi_st = scsi_transfer_alloc();
+
+				debug("[ wdc: ATAPI command ]\n");
+
+				while (inbuf_len > 0) {
+					scsi_cmd[x++] = wdc_get_inbuf(d);
+					inbuf_len --;
+				}
+
+				d->atapi_st->cmd = scsi_cmd;
+				d->atapi_st->cmd_len = 12;
+
+				if (scsi_cmd[0] == SCSIBLOCKCMD_READ_CAPACITY
+				    || scsi_cmd[0] == SCSICMD_READ_10
+				    || scsi_cmd[0] == SCSICMD_MODE_SENSE10)
+					d->atapi_st->cmd_len = 10;
+
+				res = diskimage_scsicommand(cpu,
+				    d->drive + d->base_drive, DISKIMAGE_IDE,
+				    d->atapi_st);
+
+				if (res == 0) {
+					fatal("WDC: ATAPI scsi error?\n");
+					exit(1);
+				}
+
+				d->atapi_len = 0;
+				d->atapi_received = 0;
+
+				if (res == 1) {
+					if (d->atapi_st->data_in != NULL) {
+						d->atapi_phase = PHASE_DATAIN;
+						d->atapi_len = d->atapi_st->data_in_len;
+						for (int j=0; j<d->atapi_len; j++)
+							wdc_addtoinbuf(d, d->atapi_st->data_in[j]);
+
+						if (d->atapi_len > 32768)
+							d->atapi_len = 32768;
+					} else {
+						d->atapi_phase =
+						    PHASE_COMPLETED;
+					}
+				} else {
+					fatal("wdc atapi Dataout? TODO\n");
+					d->atapi_phase = PHASE_DATAOUT;
+					exit(1);
+				}
+
+				d->int_assert = 1;
+			}
+
+			if (( d->write_in_progress == WDCC_WRITEMULTI &&
+			    inbuf_len % (512 * d->write_count) == 0)
+			    ||
+			    ( d->write_in_progress == WDCC_WRITE &&
+			    inbuf_len % 512 == 0) ) {
+				int count = (d->write_in_progress ==
+				    WDCC_WRITEMULTI)? d->write_count : 1;
+				unsigned char *buf, *b;
+
+				CHECK_ALLOCATION(buf = (unsigned char *) malloc(512 * count));
+				b = buf;
+
+				if (d->inbuf_tail+512*count <= WDC_INBUF_SIZE) {
+					b = d->inbuf + d->inbuf_tail;
+					d->inbuf_tail = (d->inbuf_tail + 512
+					    * count) % WDC_INBUF_SIZE;
+				} else {
+					for (i=0; i<512 * count; i++)
+						buf[i] = wdc_get_inbuf(d);
+				}
+
+				diskimage_access(cpu->machine,
+				    d->drive + d->base_drive, DISKIMAGE_IDE, 1,
+				    d->write_offset, b, 512 * count);
+
+				d->write_count -= count;
+				d->write_offset += 512 * count;
+
+				d->int_assert = 1;
+
+				if (d->write_count == 0)
+					d->write_in_progress = 0;
+
+				free(buf);
+			}
+		}
+		break;
+
+	case wd_error:	/*  1: error (r), precomp (w)  */
+		if (writeflag == MEM_READ) {
+			odata = d->error;
+			debug("[ wdc: read from ERROR: 0x%02x ]\n", (int)odata);
+		} else {
+			d->precomp = idata;
+			debug("[ wdc: write to PRECOMP: 0x%02x ]\n",(int)idata);
+		}
+		break;
+
+	case wd_seccnt:	/*  2: sector count (or "ireason" for ATAPI)  */
+		if (writeflag == MEM_READ) {
+			odata = d->seccnt;
+			if (d->atapi_cmd_in_progress) {
+				odata = d->atapi_phase & (WDCI_CMD | WDCI_IN);
+			}
+			debug("[ wdc: read from SECCNT: 0x%02x ]\n",(int)odata);
+		} else {
+			d->seccnt = idata;
+			debug("[ wdc: write to SECCNT: 0x%02x ]\n", (int)idata);
+		}
+		break;
+
+	case wd_sector:	/*  3: first sector  */
+		if (writeflag == MEM_READ) {
+			odata = d->sector;
+			debug("[ wdc: read from SECTOR: 0x%02x ]\n",(int)odata);
+		} else {
+			d->sector = idata;
+			debug("[ wdc: write to SECTOR: 0x%02x ]\n", (int)idata);
+		}
+		break;
+
+	case wd_cyl_lo:	/*  4: cylinder low  */
+		if (writeflag == MEM_READ) {
+			odata = d->cyl_lo;
+			if (d->cur_command == COMMAND_RESET &&
+			    diskimage_is_a_cdrom(cpu->machine,
+			    d->drive + d->base_drive, DISKIMAGE_IDE))
+				odata = 0x14;
+			if (d->atapi_cmd_in_progress) {
+				int x = d->atapi_len;
+				if (x > 32768)
+					x = 32768;
+				odata = x & 255;
+			}
+			debug("[ wdc: read from CYL_LO: 0x%02x ]\n",(int)odata);
+		} else {
+			d->cyl_lo = idata;
+			debug("[ wdc: write to CYL_LO: 0x%02x ]\n", (int)idata);
+		}
+		break;
+
+	case wd_cyl_hi:	/*  5: cylinder high  */
+		if (writeflag == MEM_READ) {
+			odata = d->cyl_hi;
+			if (d->cur_command == COMMAND_RESET &&
+			    diskimage_is_a_cdrom(cpu->machine,
+			    d->drive + d->base_drive, DISKIMAGE_IDE))
+				odata = 0xeb;
+			if (d->atapi_cmd_in_progress) {
+				int x = d->atapi_len;
+				if (x > 32768)
+					x = 32768;
+				odata = (x >> 8) & 255;
+			}
+			debug("[ wdc: read from CYL_HI: 0x%02x ]\n",(int)odata);
+		} else {
+			d->cyl_hi = idata;
+			debug("[ wdc: write to CYL_HI: 0x%02x ]\n", (int)idata);
+		}
+		break;
+
+	case wd_sdh:	/*  6: sectorsize/drive/head  */
+		if (writeflag==MEM_READ) {
+			odata = (d->sectorsize << 6) + (d->lba << 5) +
+			    (d->drive << 4) + (d->head);
+			debug("[ wdc: read from SDH: 0x%02x (sectorsize %i,"
+			    " lba=%i, drive %i, head %i) ]\n", (int)odata,
+			    d->sectorsize, d->lba, d->drive, d->head);
+		} else {
+			d->sectorsize = (idata >> 6) & 3;
+			d->lba   = (idata >> 5) & 1;
+			d->drive = (idata >> 4) & 1;
+			d->head  = idata & 0xf;
+			debug("[ wdc: write to SDH: 0x%02x (sectorsize %i,"
+			    " lba=%i, drive %i, head %i) ]\n", (int)idata,
+			    d->sectorsize, d->lba, d->drive, d->head);
+		}
+		break;
+
+	case wd_command:	/*  7: command or status  */
+		if (writeflag==MEM_READ) {
+			odata = status_byte(d, cpu);
+			if (!quiet_mode)
+				debug("[ wdc: read from STATUS: 0x%02x ]\n",
+				    (int)odata);
+			INTERRUPT_DEASSERT(d->irq);
+			d->int_assert = 0;
+		} else {
+			debug("[ wdc: write to COMMAND: 0x%02x ]\n",(int)idata);
+			wdc_command(cpu, d, idata);
+		}
+		break;
+
+	default:
+		if (writeflag==MEM_READ)
+			debug("[ wdc: read from 0x%02x ]\n",
+			    (int)relative_addr);
+		else
+			debug("[ wdc: write to  0x%02x: 0x%02x ]\n",
+			    (int)relative_addr, (int)idata);
+	}
+
+	/*  Assert interrupt, if necessary:  */
+	dev_wdc_tick(cpu, extra);
+
+ret:
+	if (writeflag == MEM_READ) {
+		if (relative_addr == wd_data)
+			memory_writemax64(cpu, data, len, odata);
+		else {
+			if (len != 1)
+				fatal("[ wdc: WARNING! non-8-bit access on READ! ]\n");
+			data[0] = odata;
+		}
+	}
+
+	return 1;
+}
+
+
+DEVINIT(wdc)
+{
+	struct wdc_data *d;
+	uint64_t alt_status_addr;
+	int i, tick_shift = WDC_TICK_SHIFT;
+
+	CHECK_ALLOCATION(d = (struct wdc_data *) malloc(sizeof(struct wdc_data)));
+	memset(d, 0, sizeof(struct wdc_data));
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+	d->addr_mult  = devinit->addr_mult;
+	d->data_debug = 1;
+	d->io_enabled = 1;
+	d->error      = 1;
+
+	d->inbuf = (unsigned char *) zeroed_alloc(WDC_INBUF_SIZE);
+
+	/*  base_drive = 0 for the primary controller, 2 for the secondary.  */
+	d->base_drive = 0;
+	if ((devinit->addr & 0xfff) == 0x170)
+		d->base_drive = 2;
+
+	alt_status_addr = devinit->addr + 0x206;
+
+	/*  Special hacks for individual machines:  */
+	switch (devinit->machine->machine_type) {
+	case MACHINE_MACPPC:
+		alt_status_addr = devinit->addr + 0x160;
+		break;
+	case MACHINE_HPCMIPS:
+		/*  TODO: Fix  */
+		if (devinit->addr == 0x14000180)
+			alt_status_addr = 0x14000386;
+		break;
+	case MACHINE_IQ80321:
+		alt_status_addr = devinit->addr + 0x402;
+		break;
+	}
+
+	/*  Get disk geometries:  */
+	for (i=0; i<2; i++)
+		if (diskimage_exist(devinit->machine, d->base_drive +i,
+		    DISKIMAGE_IDE))
+			diskimage_getchs(devinit->machine, d->base_drive + i,
+			    DISKIMAGE_IDE, &d->cyls[i], &d->heads[i],
+			    &d->sectors_per_track[i]);
+
+	memory_device_register(devinit->machine->memory, "wdc_altstatus",
+	    alt_status_addr, 2, dev_wdc_altstatus_access, d, DM_DEFAULT, NULL);
+	memory_device_register(devinit->machine->memory, devinit->name,
+	    devinit->addr, DEV_WDC_LENGTH * devinit->addr_mult, dev_wdc_access,
+	    d, DM_DEFAULT, NULL);
+
+	machine_add_tickfunction(devinit->machine, dev_wdc_tick,
+	    d, tick_shift);
+
+	devinit->return_ptr = d;
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_wdc.cc gxemul-0.7.0+dfsg/src/devices/dev_wdc.cc
--- gxemul-0.6.2/src/devices/dev_wdc.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_wdc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,966 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Standard "wdc" IDE controller
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/wdcreg.h"
-
-
-#define	DEV_WDC_LENGTH		8
-#define	WDC_TICK_SHIFT		14
-#define	WDC_MAX_SECTORS		512
-#define	WDC_INBUF_SIZE		(512*(WDC_MAX_SECTORS+1))
-
-extern int quiet_mode;
-
-/*  #define debug fatal  */
-
-struct wdc_data {
-	struct interrupt irq;
-	int		addr_mult;
-	int		base_drive;
-	int		data_debug;
-	int		io_enabled;
-
-	/*  Cached values:  */
-	int		cyls[2];
-	int		heads[2];
-	int		sectors_per_track[2];
-
-	unsigned char	*inbuf;
-	int		inbuf_head;
-	int		inbuf_tail;
-
-	int		int_assert;
-
-	int		write_in_progress;
-	int		write_count;
-	int64_t		write_offset;
-
-	int		error;
-	int		precomp;
-	int		seccnt;
-	int		sector;
-	int		cyl_lo;
-	int		cyl_hi;
-	int		sectorsize;
-	int		lba;
-	int		drive;
-	int		head;
-	int		cur_command;
-
-	int		atapi_cmd_in_progress;
-	int		atapi_phase;
-	struct scsi_transfer *atapi_st;
-	int		atapi_len;
-	size_t		atapi_received;
-
-	unsigned char	identify_struct[512];
-};
-
-
-#define COMMAND_RESET	0x100
-
-
-DEVICE_TICK(wdc)
-{ 
-	struct wdc_data *d = (struct wdc_data *) extra;
-
-	if (d->int_assert)
-		INTERRUPT_ASSERT(d->irq);
-}
-
-
-/*
- *  wdc_set_io_enabled():
- *
- *  Set io_enabled to zero to disable the I/O registers temporarily (e.g.
- *  used by PCI code in NetBSD to detect whether multiple controllers collide
- *  in I/O space).
- *
- *  Return value is old contents of the io_enabled variable.
- */
-int wdc_set_io_enabled(struct wdc_data *d, int io_enabled)
-{
-	int old = d->io_enabled;
-	d->io_enabled = io_enabled;
-	return old;
-}
-
-
-/*
- *  wdc_addtoinbuf():
- *
- *  Write to the inbuf at its head, read at its tail.
- */
-static void wdc_addtoinbuf(struct wdc_data *d, int c)
-{
-	d->inbuf[d->inbuf_head] = c;
-
-	d->inbuf_head = (d->inbuf_head + 1) % WDC_INBUF_SIZE;
-	if (d->inbuf_head == d->inbuf_tail)
-		fatal("[ wdc_addtoinbuf(): WARNING! wdc inbuf overrun!"
-		    " Increase WDC_MAX_SECTORS. ]\n");
-}
-
-
-/*
- *  wdc_get_inbuf():
- *
- *  Read from the tail of inbuf.
- */
-static uint64_t wdc_get_inbuf(struct wdc_data *d)
-{
-	int c = d->inbuf[d->inbuf_tail];
-
-	if (d->inbuf_head == d->inbuf_tail) {
-		fatal("[ wdc: WARNING! someone is reading too much from the "
-		    "wdc inbuf! ]\n");
-		return (uint64_t) -1;
-	}
-
-	d->inbuf_tail = (d->inbuf_tail + 1) % WDC_INBUF_SIZE;
-	return c;
-}
-
-
-/*
- *  wdc_initialize_identify_struct():
- */
-static void wdc_initialize_identify_struct(struct cpu *cpu, struct wdc_data *d)
-{
-	uint64_t total_size;
-	int flags, cdrom = 0;
-	char namebuf[40];
-
-	total_size = diskimage_getsize(cpu->machine, d->drive + d->base_drive,
-	    DISKIMAGE_IDE);
-	if (diskimage_is_a_cdrom(cpu->machine, d->drive + d->base_drive,
-	    DISKIMAGE_IDE))
-		cdrom = 1;
-
-	memset(d->identify_struct, 0, sizeof(d->identify_struct));
-
-	/*  Offsets are in 16-bit WORDS!  High byte, then low.  */
-
-	/*  0: general flags  */
-	flags = 1 << 6;	/*  Fixed  */
-	if (cdrom)
-		flags = 0x8580;		/*  ATAPI, CDROM, removable  */
-	d->identify_struct[2 * 0 + 0] = flags >> 8;
-	d->identify_struct[2 * 0 + 1] = flags;
-
-	/*  1: nr of cylinders  */
-	d->identify_struct[2 * 1 + 0] = d->cyls[d->drive] >> 8;
-	d->identify_struct[2 * 1 + 1] = d->cyls[d->drive];
-
-	/*  3: nr of heads  */
-	d->identify_struct[2 * 3 + 0] = d->heads[d->drive] >> 8;
-	d->identify_struct[2 * 3 + 1] = d->heads[d->drive];
-
-	/*  6: sectors per track  */
-	d->identify_struct[2 * 6 + 0] = d->sectors_per_track[d->drive] >> 8;
-	d->identify_struct[2 * 6 + 1] = d->sectors_per_track[d->drive];
-
-	/*  10-19: Serial number  */
-	memcpy(&d->identify_struct[2 * 10], "#0                  ", 20);
-
-	/*  23-26: Firmware version  */
-	memcpy(&d->identify_struct[2 * 23], "1.0     ", 8);
-
-	/*  27-46: Model number  */
-	if (diskimage_getname(cpu->machine, d->drive + d->base_drive,
-	    DISKIMAGE_IDE, namebuf, sizeof(namebuf))) {
-		size_t i;
-		for (i=0; i<sizeof(namebuf); i++)
-			if (namebuf[i] == 0) {
-				for (; i<sizeof(namebuf); i++)
-					namebuf[i] = ' ';
-				break;
-			}
-		memcpy(&d->identify_struct[2 * 27], namebuf, 40);
-	} else
-		memcpy(&d->identify_struct[2 * 27],
-		    "Fake GXemul IDE disk                    ", 40);
-
-	/*  47: max sectors per multitransfer  */
-	d->identify_struct[2 * 47 + 0] = 0x80;
-	d->identify_struct[2 * 47 + 1] = 128;
-
-	/*  49: capabilities:  */
-	/*  (0x200 = LBA, 0x100 = DMA support.)  */
-	d->identify_struct[2 * 49 + 0] = 0;
-	d->identify_struct[2 * 49 + 1] = 0;
-
-	/*  51: PIO timing mode.  */
-	d->identify_struct[2 * 51 + 0] = 0x00;	/*  ?  */
-	d->identify_struct[2 * 51 + 1] = 0x00;
-
-	/*  53: 0x02 = fields 64-70 valid, 0x01 = fields 54-58 valid  */
-	d->identify_struct[2 * 53 + 0] = 0x00;
-	d->identify_struct[2 * 53 + 1] = 0x02;
-
-	/*  57-58: current capacity in sectors  */
-	d->identify_struct[2 * 58 + 0] = ((total_size / 512) >> 24) % 255;
-	d->identify_struct[2 * 58 + 1] = ((total_size / 512) >> 16) % 255;
-	d->identify_struct[2 * 57 + 0] = ((total_size / 512) >> 8) % 255;
-	d->identify_struct[2 * 57 + 1] = (total_size / 512) & 255;
-
-	/*  60-61: total nr of addressable sectors  */
-	d->identify_struct[2 * 61 + 0] = ((total_size / 512) >> 24) % 255;
-	d->identify_struct[2 * 61 + 1] = ((total_size / 512) >> 16) % 255;
-	d->identify_struct[2 * 60 + 0] = ((total_size / 512) >> 8) % 255;
-	d->identify_struct[2 * 60 + 1] = (total_size / 512) & 255;
-
-	/*  64: Advanced PIO mode support. 0x02 = mode4, 0x01 = mode3  */
-	d->identify_struct[2 * 64 + 0] = 0x00;
-	d->identify_struct[2 * 64 + 1] = 0x03;
-
-	/*  67, 68: PIO timing  */
-	d->identify_struct[2 * 67 + 0] = 0;
-	d->identify_struct[2 * 67 + 1] = 120;
-	d->identify_struct[2 * 68 + 0] = 0;
-	d->identify_struct[2 * 68 + 1] = 120;
-}
-
-
-/*
- *  wdc__read():
- */
-void wdc__read(struct cpu *cpu, struct wdc_data *d)
-{
-#define MAX_SECTORS_PER_CHUNK	64
-	const int max_sectors_per_chunk = MAX_SECTORS_PER_CHUNK;
-	unsigned char buf[512 * MAX_SECTORS_PER_CHUNK];
-	int i, cyl = d->cyl_hi * 256+ d->cyl_lo;
-	int count = d->seccnt? d->seccnt : 256;
-	uint64_t offset = 512 * (d->sector - 1
-	    + (int64_t)d->head * d->sectors_per_track[d->drive] +
-	    (int64_t)d->heads[d->drive] * d->sectors_per_track[d->drive] * cyl);
-
-#if 0
-	/*  LBA:  */
-	if (d->lba)
-		offset = 512 * (((d->head & 0xf) << 24) + (cyl << 8)
-		    + d->sector);
-	printf("WDC read from offset %lli\n", (long long)offset);
-#endif
-
-	while (count > 0) {
-		int to_read = count > max_sectors_per_chunk?
-		    max_sectors_per_chunk : count;
-
-		/*  TODO: result code from the read?  */
-
-		if (d->inbuf_head + 512 * to_read <= WDC_INBUF_SIZE) {
-			diskimage_access(cpu->machine, d->drive + d->base_drive,
-			    DISKIMAGE_IDE, 0, offset,
-			    d->inbuf + d->inbuf_head, 512 * to_read);
-			d->inbuf_head += 512 * to_read;
-			if (d->inbuf_head == WDC_INBUF_SIZE)
-				d->inbuf_head = 0;
-		} else {
-			diskimage_access(cpu->machine, d->drive + d->base_drive,
-			    DISKIMAGE_IDE, 0, offset, buf, 512 * to_read);
-			for (i=0; i<512 * to_read; i++)
-				wdc_addtoinbuf(d, buf[i]);
-		}
-
-		offset += 512 * to_read;
-		count -= to_read;
-	}
-
-	d->int_assert = 1;
-}
-
-
-/*
- *  wdc__write():
- */
-void wdc__write(struct cpu *cpu, struct wdc_data *d)
-{
-	int cyl = d->cyl_hi * 256+ d->cyl_lo;
-	int count = d->seccnt? d->seccnt : 256;
-	uint64_t offset = 512 * (d->sector - 1
-	    + (int64_t)d->head * d->sectors_per_track[d->drive] +
-	    (int64_t)d->heads[d->drive] * d->sectors_per_track[d->drive] * cyl);
-#if 0
-	/*  LBA:  */
-	if (d->lba)
-		offset = 512 * (((d->head & 0xf) << 24) +
-		    (cyl << 8) + d->sector);
-	printf("WDC write to offset %lli\n", (long long)offset);
-#endif
-
-	d->write_in_progress = d->cur_command;
-	d->write_count = count;
-	d->write_offset = offset;
-
-	/*  TODO: result code?  */
-}
-
-
-/*
- *  status_byte():
- *
- *  Return a reasonable status byte corresponding to the controller's current
- *  state.
- */
-static int status_byte(struct wdc_data *d, struct cpu *cpu)
-{
-	int odata = 0;
-	if (diskimage_exist(cpu->machine, d->drive + d->base_drive,
-	    DISKIMAGE_IDE))
-		odata |= WDCS_DRDY | WDCS_DSC;
-	if (d->inbuf_head != d->inbuf_tail)
-		odata |= WDCS_DRQ;
-	if (d->write_in_progress)
-		odata |= WDCS_DRQ;
-	if (d->error)
-		odata |= WDCS_ERR;
-	if (d->atapi_cmd_in_progress && (d->atapi_phase & WDCS_DRQ)) {
-		odata |= WDCS_DRQ;
-	}
-	return odata;
-}
-
-
-DEVICE_ACCESS(wdc_altstatus)
-{
-	struct wdc_data *d = (struct wdc_data *) extra;
-	uint64_t idata = 0, odata = 0;
-
-	idata = data[0];
-
-	/*  Same as the normal status byte:  */
-	odata = status_byte(d, cpu);
-
-	if (writeflag==MEM_READ)
-		debug("[ wdc: read from ALTSTATUS: 0x%02x ]\n",
-		    (int)odata);
-	else {
-		debug("[ wdc: write to ALT. CTRL: 0x%02x ]\n",
-		    (int)idata);
-		if (idata & WDCTL_4BIT)
-			d->cur_command = COMMAND_RESET;
-	}
-
-	if (writeflag == MEM_READ)
-		data[0] = odata;
-
-	return 1;
-}
-
-
-/*
- *  wdc_command():
- */
-void wdc_command(struct cpu *cpu, struct wdc_data *d, int idata)
-{
-	size_t i;
-
-	d->cur_command = idata;
-	d->atapi_cmd_in_progress = 0;
-	d->error = 0;
-
-	/*
-	 *  Disk images that do not exist return an ABORT error.  This also
-	 *  happens with CDROM images with the WDCC_IDENTIFY command; CDROM
-	 *  images must be detected with ATAPI_IDENTIFY_DEVICE instead.
-	 *
-	 *  TODO:  Is this correct/good behaviour?
-	 */
-	if (!diskimage_exist(cpu->machine, d->drive + d->base_drive,
-	    DISKIMAGE_IDE)) {
-		debug("[ wdc: command 0x%02x drive %i, but no disk image ]\n",
-		    d->cur_command, d->drive + d->base_drive);
-		d->error |= WDCE_ABRT;
-		d->int_assert = 1;
-		return;
-	}
-	if (diskimage_is_a_cdrom(cpu->machine, d->drive + d->base_drive,
-	    DISKIMAGE_IDE) && d->cur_command == WDCC_IDENTIFY) {
-		debug("[ wdc: IDENTIFY drive %i, but it is an ATAPI "
-		    "drive ]\n", d->drive + d->base_drive);
-		d->error |= WDCE_ABRT;
-		d->int_assert = 1;
-		return;
-	}
-
-	/*  Handle the command:  */
-	switch (d->cur_command) {
-
-	case WDCC_READ:
-	case WDCC_READMULTI:
-		if (!quiet_mode)
-			debug("[ wdc: READ from drive %i, head %i, cyl %i, "
-			    "sector %i, nsecs %i ]\n", d->drive, d->head,
-			    d->cyl_hi*256+d->cyl_lo, d->sector, d->seccnt);
-		wdc__read(cpu, d);
-		break;
-
-	case WDCC_WRITE:
-	case WDCC_WRITEMULTI:
-		if (!quiet_mode)
-			debug("[ wdc: WRITE to drive %i, head %i, cyl %i, "
-			    "sector %i, nsecs %i ]\n", d->drive, d->head,
-			    d->cyl_hi*256+d->cyl_lo, d->sector, d->seccnt);
-		wdc__write(cpu, d);
-		break;
-
-	case WDCC_IDP:	/*  Initialize drive parameters  */
-		debug("[ wdc: IDP drive %i (TODO) ]\n", d->drive);
-		/*  TODO  */
-		d->int_assert = 1;
-		break;
-
-	case SET_FEATURES:
-		debug("[ wdc: SET_FEATURES drive %i (TODO), feature 0x%02x ]\n",
-		    d->drive, d->precomp);
-		/*  TODO  */
-		switch (d->precomp) {
-		case WDSF_SET_MODE:
-			debug("[ wdc: WDSF_SET_MODE drive %i, pio/dma flags "
-			    "0x%02x ]\n", d->drive, d->seccnt);
-			break;
-		default:d->error |= WDCE_ABRT;
-		}
-		/*  TODO: always interrupt?  */
-		d->int_assert = 1;
-		break;
-
-	case WDCC_RECAL:
-		debug("[ wdc: RECAL drive %i ]\n", d->drive);
-		d->int_assert = 1;
-		break;
-
-	case WDCC_IDENTIFY:
-	case ATAPI_IDENTIFY_DEVICE:
-		debug("[ wdc: %sIDENTIFY drive %i ]\n", d->cur_command ==
-		    ATAPI_IDENTIFY_DEVICE? "ATAPI " : "", d->drive);
-		wdc_initialize_identify_struct(cpu, d);
-		/*  The IDENTIFY data is sent out in low/high byte order:  */
-		for (i=0; i<sizeof(d->identify_struct); i+=2) {
-			wdc_addtoinbuf(d, d->identify_struct[i+1]);
-			wdc_addtoinbuf(d, d->identify_struct[i+0]);
-		}
-		d->int_assert = 1;
-		break;
-
-	case WDCC_IDLE_IMMED:
-		debug("[ wdc: IDLE_IMMED drive %i ]\n", d->drive);
-		/*  TODO: interrupt here?  */
-		d->int_assert = 1;
-		break;
-
-	case WDCC_SETMULTI:
-		debug("[ wdc: SETMULTI drive %i ]\n", d->drive);
-		/*  TODO: interrupt here?  */
-		d->int_assert = 1;
-		break;
-
-	case ATAPI_SOFT_RESET:
-		debug("[ wdc: ATAPI_SOFT_RESET drive %i ]\n", d->drive);
-		/*  TODO: interrupt here?  */
-		d->int_assert = 1;
-		break;
-
-	case ATAPI_PKT_CMD:
-		debug("[ wdc: ATAPI_PKT_CMD drive %i ]\n", d->drive);
-		/*  TODO: interrupt here?  */
-		/*  d->int_assert = 1;  */
-		d->atapi_cmd_in_progress = 1;
-		d->atapi_phase = PHASE_CMDOUT;
-		break;
-
-	case WDCC_DIAGNOSE:
-		debug("[ wdc: WDCC_DIAGNOSE drive %i: TODO ]\n", d->drive);
-		/*  TODO: interrupt here?  */
-		d->int_assert = 1;
-		d->error = 1;		/*  No error?  */
-		break;
-
-	/*  Unsupported commands, without warning:  */
-	case WDCC_SEC_SET_PASSWORD:
-	case WDCC_SEC_UNLOCK:
-	case WDCC_SEC_ERASE_PREPARE:
-	case WDCC_SEC_ERASE_UNIT:
-	case WDCC_SEC_FREEZE_LOCK:
-	case WDCC_SEC_DISABLE_PASSWORD:
-		d->error |= WDCE_ABRT;
-		break;
-
-	default:/*  TODO  */
-		d->error |= WDCE_ABRT;
-		fatal("[ wdc: WARNING! Unimplemented command 0x%02x (drive %i,"
-		    " head %i, cyl %i, sector %i, nsecs %i) ]\n",
-		    d->cur_command, d->drive, d->head, d->cyl_hi*256+d->cyl_lo,
-		    d->sector, d->seccnt);
-	}
-}
-
-
-DEVICE_ACCESS(wdc)
-{
-	struct wdc_data *d = (struct wdc_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int i;
-
-	relative_addr /= d->addr_mult;
-
-	if (!d->io_enabled)
-		goto ret;
-
-	if (writeflag == MEM_WRITE) {
-		if (relative_addr == wd_data)
-			idata = memory_readmax64(cpu, data, len);
-		else {
-			if (len != 1)
-				fatal("[ wdc: WARNING! non-8-bit access on WRITE! ]\n");
-			idata = data[0];
-		}
-	}
-
-	switch (relative_addr) {
-
-	case wd_data:	/*  0: data  */
-		if (writeflag == MEM_READ) {
-			odata = wdc_get_inbuf(d);
-
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-				if (len >= 2)
-					odata += (wdc_get_inbuf(d) << 8);
-				if (len == 4) {
-					odata += (wdc_get_inbuf(d) << 16);
-					odata += (wdc_get_inbuf(d) << 24);
-				}
-			} else {
-				if (len >= 2)
-					odata = (odata << 8) + wdc_get_inbuf(d);
-				if (len == 4) {
-					odata = (odata << 8) + wdc_get_inbuf(d);
-					odata = (odata << 8) + wdc_get_inbuf(d);
-				}
-			}
-
-			if (d->data_debug) {
-				const char *s = "0x%04" PRIx64" ]\n";
-				if (len == 1)
-					s = "0x%02" PRIx64" ]\n";
-				if (len == 4)
-					s = "0x%08" PRIx64" ]\n";
-				if (len == 8)
-					s = "0x%016" PRIx64" ]\n";
-				debug("[ wdc: read from DATA: ");
-				debug(s, (uint64_t) odata);
-			}
-
-			if (d->atapi_cmd_in_progress) {
-				d->atapi_len -= len;
-				d->atapi_received += len;
-				if (d->atapi_len == 0) {
-					if (d->atapi_received < d->atapi_st->
-					    data_in_len) {
-						d->atapi_phase = PHASE_DATAIN;
-						d->atapi_len = d->atapi_st->
-						    data_in_len -
-						    d->atapi_received;
-						if (d->atapi_len > 32768)
-							d->atapi_len = 0;
-					} else
-						d->atapi_phase =
-						    PHASE_COMPLETED;
-					d->int_assert = 1;
-				}
-			} else {
-#if 0
-				if (d->inbuf_tail != d->inbuf_head)
-#else
-				if (d->inbuf_tail != d->inbuf_head &&
-				    ((d->inbuf_tail - d->inbuf_head) % 512)
-				    == 0)
-#endif
-					d->int_assert = 1;
-			}
-		} else {
-			int inbuf_len;
-			if (d->data_debug) {
-				const char *s = "0x%04" PRIx64" ]\n";
-				if (len == 1)
-					s = "0x%02" PRIx64" ]\n";
-				if (len == 4)
-					s = "0x%08" PRIx64" ]\n";
-				if (len == 8)
-					s = "0x%016" PRIx64" ]\n";
-				debug("[ wdc: write to DATA: ");
-				debug(s, (uint64_t) idata);
-			}
-			if (!d->write_in_progress &&
-			    !d->atapi_cmd_in_progress) {
-				fatal("[ wdc: write to DATA, but not "
-				    "expecting any? (len=%i): 0x%08lx ]\n",
-				    (int)len, (long)idata);
-			}
-
-			if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-				switch (len) {
-				case 4:	wdc_addtoinbuf(d, idata & 0xff);
-					wdc_addtoinbuf(d, (idata >> 8) & 0xff);
-					wdc_addtoinbuf(d, (idata >> 16) & 0xff);
-					wdc_addtoinbuf(d, (idata >> 24) & 0xff);
-					break;
-				case 2:	wdc_addtoinbuf(d, idata & 0xff);
-					wdc_addtoinbuf(d, (idata >> 8) & 0xff);
-					break;
-				case 1:	wdc_addtoinbuf(d, idata); break;
-				default:fatal("wdc: unimplemented write "
-					    "len %i\n", len);
-					exit(1);
-				}
-			} else {
-				switch (len) {
-				case 4:	wdc_addtoinbuf(d, (idata >> 24) & 0xff);
-					wdc_addtoinbuf(d, (idata >> 16) & 0xff);
-					wdc_addtoinbuf(d, (idata >> 8) & 0xff);
-					wdc_addtoinbuf(d, idata & 0xff);
-					break;
-				case 2:	wdc_addtoinbuf(d, (idata >> 8) & 0xff);
-					wdc_addtoinbuf(d, idata & 0xff);
-					break;
-				case 1:	wdc_addtoinbuf(d, idata); break;
-				default:fatal("wdc: unimplemented write "
-					    "len %i\n", len);
-					exit(1);
-				}
-			}
-
-			inbuf_len = d->inbuf_head - d->inbuf_tail;
-			while (inbuf_len < 0)
-				inbuf_len += WDC_INBUF_SIZE;
-
-			if (d->atapi_cmd_in_progress && inbuf_len == 12) {
-				unsigned char *scsi_cmd;
-				int x = 0, res;
-
-				CHECK_ALLOCATION(scsi_cmd = (unsigned char *) malloc(12));
-
-				if (d->atapi_st != NULL)
-					scsi_transfer_free(d->atapi_st);
-				d->atapi_st = scsi_transfer_alloc();
-
-				debug("[ wdc: ATAPI command ]\n");
-
-				while (inbuf_len > 0) {
-					scsi_cmd[x++] = wdc_get_inbuf(d);
-					inbuf_len --;
-				}
-
-				d->atapi_st->cmd = scsi_cmd;
-				d->atapi_st->cmd_len = 12;
-
-				if (scsi_cmd[0] == SCSIBLOCKCMD_READ_CAPACITY
-				    || scsi_cmd[0] == SCSICMD_READ_10
-				    || scsi_cmd[0] == SCSICMD_MODE_SENSE10)
-					d->atapi_st->cmd_len = 10;
-
-				res = diskimage_scsicommand(cpu,
-				    d->drive + d->base_drive, DISKIMAGE_IDE,
-				    d->atapi_st);
-
-				if (res == 0) {
-					fatal("WDC: ATAPI scsi error?\n");
-					exit(1);
-				}
-
-				d->atapi_len = 0;
-				d->atapi_received = 0;
-
-				if (res == 1) {
-					if (d->atapi_st->data_in != NULL) {
-						d->atapi_phase = PHASE_DATAIN;
-						d->atapi_len = d->atapi_st->data_in_len;
-						for (int j=0; j<d->atapi_len; j++)
-							wdc_addtoinbuf(d, d->atapi_st->data_in[j]);
-
-						if (d->atapi_len > 32768)
-							d->atapi_len = 32768;
-					} else {
-						d->atapi_phase =
-						    PHASE_COMPLETED;
-					}
-				} else {
-					fatal("wdc atapi Dataout? TODO\n");
-					d->atapi_phase = PHASE_DATAOUT;
-					exit(1);
-				}
-
-				d->int_assert = 1;
-			}
-
-			if (( d->write_in_progress == WDCC_WRITEMULTI &&
-			    inbuf_len % (512 * d->write_count) == 0)
-			    ||
-			    ( d->write_in_progress == WDCC_WRITE &&
-			    inbuf_len % 512 == 0) ) {
-				int count = (d->write_in_progress ==
-				    WDCC_WRITEMULTI)? d->write_count : 1;
-				unsigned char *buf, *b;
-
-				CHECK_ALLOCATION(buf = (unsigned char *) malloc(512 * count));
-				b = buf;
-
-				if (d->inbuf_tail+512*count <= WDC_INBUF_SIZE) {
-					b = d->inbuf + d->inbuf_tail;
-					d->inbuf_tail = (d->inbuf_tail + 512
-					    * count) % WDC_INBUF_SIZE;
-				} else {
-					for (i=0; i<512 * count; i++)
-						buf[i] = wdc_get_inbuf(d);
-				}
-
-				diskimage_access(cpu->machine,
-				    d->drive + d->base_drive, DISKIMAGE_IDE, 1,
-				    d->write_offset, b, 512 * count);
-
-				d->write_count -= count;
-				d->write_offset += 512 * count;
-
-				d->int_assert = 1;
-
-				if (d->write_count == 0)
-					d->write_in_progress = 0;
-
-				free(buf);
-			}
-		}
-		break;
-
-	case wd_error:	/*  1: error (r), precomp (w)  */
-		if (writeflag == MEM_READ) {
-			odata = d->error;
-			debug("[ wdc: read from ERROR: 0x%02x ]\n", (int)odata);
-		} else {
-			d->precomp = idata;
-			debug("[ wdc: write to PRECOMP: 0x%02x ]\n",(int)idata);
-		}
-		break;
-
-	case wd_seccnt:	/*  2: sector count (or "ireason" for ATAPI)  */
-		if (writeflag == MEM_READ) {
-			odata = d->seccnt;
-			if (d->atapi_cmd_in_progress) {
-				odata = d->atapi_phase & (WDCI_CMD | WDCI_IN);
-			}
-			debug("[ wdc: read from SECCNT: 0x%02x ]\n",(int)odata);
-		} else {
-			d->seccnt = idata;
-			debug("[ wdc: write to SECCNT: 0x%02x ]\n", (int)idata);
-		}
-		break;
-
-	case wd_sector:	/*  3: first sector  */
-		if (writeflag == MEM_READ) {
-			odata = d->sector;
-			debug("[ wdc: read from SECTOR: 0x%02x ]\n",(int)odata);
-		} else {
-			d->sector = idata;
-			debug("[ wdc: write to SECTOR: 0x%02x ]\n", (int)idata);
-		}
-		break;
-
-	case wd_cyl_lo:	/*  4: cylinder low  */
-		if (writeflag == MEM_READ) {
-			odata = d->cyl_lo;
-			if (d->cur_command == COMMAND_RESET &&
-			    diskimage_is_a_cdrom(cpu->machine,
-			    d->drive + d->base_drive, DISKIMAGE_IDE))
-				odata = 0x14;
-			if (d->atapi_cmd_in_progress) {
-				int x = d->atapi_len;
-				if (x > 32768)
-					x = 32768;
-				odata = x & 255;
-			}
-			debug("[ wdc: read from CYL_LO: 0x%02x ]\n",(int)odata);
-		} else {
-			d->cyl_lo = idata;
-			debug("[ wdc: write to CYL_LO: 0x%02x ]\n", (int)idata);
-		}
-		break;
-
-	case wd_cyl_hi:	/*  5: cylinder high  */
-		if (writeflag == MEM_READ) {
-			odata = d->cyl_hi;
-			if (d->cur_command == COMMAND_RESET &&
-			    diskimage_is_a_cdrom(cpu->machine,
-			    d->drive + d->base_drive, DISKIMAGE_IDE))
-				odata = 0xeb;
-			if (d->atapi_cmd_in_progress) {
-				int x = d->atapi_len;
-				if (x > 32768)
-					x = 32768;
-				odata = (x >> 8) & 255;
-			}
-			debug("[ wdc: read from CYL_HI: 0x%02x ]\n",(int)odata);
-		} else {
-			d->cyl_hi = idata;
-			debug("[ wdc: write to CYL_HI: 0x%02x ]\n", (int)idata);
-		}
-		break;
-
-	case wd_sdh:	/*  6: sectorsize/drive/head  */
-		if (writeflag==MEM_READ) {
-			odata = (d->sectorsize << 6) + (d->lba << 5) +
-			    (d->drive << 4) + (d->head);
-			debug("[ wdc: read from SDH: 0x%02x (sectorsize %i,"
-			    " lba=%i, drive %i, head %i) ]\n", (int)odata,
-			    d->sectorsize, d->lba, d->drive, d->head);
-		} else {
-			d->sectorsize = (idata >> 6) & 3;
-			d->lba   = (idata >> 5) & 1;
-			d->drive = (idata >> 4) & 1;
-			d->head  = idata & 0xf;
-			debug("[ wdc: write to SDH: 0x%02x (sectorsize %i,"
-			    " lba=%i, drive %i, head %i) ]\n", (int)idata,
-			    d->sectorsize, d->lba, d->drive, d->head);
-		}
-		break;
-
-	case wd_command:	/*  7: command or status  */
-		if (writeflag==MEM_READ) {
-			odata = status_byte(d, cpu);
-			if (!quiet_mode)
-				debug("[ wdc: read from STATUS: 0x%02x ]\n",
-				    (int)odata);
-			INTERRUPT_DEASSERT(d->irq);
-			d->int_assert = 0;
-		} else {
-			debug("[ wdc: write to COMMAND: 0x%02x ]\n",(int)idata);
-			wdc_command(cpu, d, idata);
-		}
-		break;
-
-	default:
-		if (writeflag==MEM_READ)
-			debug("[ wdc: read from 0x%02x ]\n",
-			    (int)relative_addr);
-		else
-			debug("[ wdc: write to  0x%02x: 0x%02x ]\n",
-			    (int)relative_addr, (int)idata);
-	}
-
-	/*  Assert interrupt, if necessary:  */
-	dev_wdc_tick(cpu, extra);
-
-ret:
-	if (writeflag == MEM_READ) {
-		if (relative_addr == wd_data)
-			memory_writemax64(cpu, data, len, odata);
-		else {
-			if (len != 1)
-				fatal("[ wdc: WARNING! non-8-bit access on READ! ]\n");
-			data[0] = odata;
-		}
-	}
-
-	return 1;
-}
-
-
-DEVINIT(wdc)
-{
-	struct wdc_data *d;
-	uint64_t alt_status_addr;
-	int i, tick_shift = WDC_TICK_SHIFT;
-
-	CHECK_ALLOCATION(d = (struct wdc_data *) malloc(sizeof(struct wdc_data)));
-	memset(d, 0, sizeof(struct wdc_data));
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-	d->addr_mult  = devinit->addr_mult;
-	d->data_debug = 1;
-	d->io_enabled = 1;
-	d->error      = 1;
-
-	d->inbuf = (unsigned char *) zeroed_alloc(WDC_INBUF_SIZE);
-
-	/*  base_drive = 0 for the primary controller, 2 for the secondary.  */
-	d->base_drive = 0;
-	if ((devinit->addr & 0xfff) == 0x170)
-		d->base_drive = 2;
-
-	alt_status_addr = devinit->addr + 0x206;
-
-	/*  Special hacks for individual machines:  */
-	switch (devinit->machine->machine_type) {
-	case MACHINE_MACPPC:
-		alt_status_addr = devinit->addr + 0x160;
-		break;
-	case MACHINE_HPCMIPS:
-		/*  TODO: Fix  */
-		if (devinit->addr == 0x14000180)
-			alt_status_addr = 0x14000386;
-		break;
-	case MACHINE_IQ80321:
-		alt_status_addr = devinit->addr + 0x402;
-		break;
-	}
-
-	/*  Get disk geometries:  */
-	for (i=0; i<2; i++)
-		if (diskimage_exist(devinit->machine, d->base_drive +i,
-		    DISKIMAGE_IDE))
-			diskimage_getchs(devinit->machine, d->base_drive + i,
-			    DISKIMAGE_IDE, &d->cyls[i], &d->heads[i],
-			    &d->sectors_per_track[i]);
-
-	memory_device_register(devinit->machine->memory, "wdc_altstatus",
-	    alt_status_addr, 2, dev_wdc_altstatus_access, d, DM_DEFAULT, NULL);
-	memory_device_register(devinit->machine->memory, devinit->name,
-	    devinit->addr, DEV_WDC_LENGTH * devinit->addr_mult, dev_wdc_access,
-	    d, DM_DEFAULT, NULL);
-
-	machine_add_tickfunction(devinit->machine, dev_wdc_tick,
-	    d, tick_shift);
-
-	devinit->return_ptr = d;
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_z8530.c gxemul-0.7.0+dfsg/src/devices/dev_z8530.c
--- gxemul-0.6.2/src/devices/dev_z8530.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_z8530.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,237 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Zilog Z8530 "zs" serial controller
+ *
+ *  Features:
+ *	o)  Two channels, 0 = "channel B", 1 = "channel A".
+ *	    Normally, only channel B is in use.
+ *
+ *  This is a work in progress... TODOs include:
+ *	o)  Implement more of the register set.
+ *	o)  Verify that it works with other guest OSes than NetBSD and OpenBSD.
+ *	o)  Implement DMA!
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "interrupt.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/z8530reg.h"
+
+
+/*  #define debug fatal  */
+
+#define	ZS_TICK_SHIFT		14
+#define	ZS_N_REGS		16
+#define	ZS_N_CHANNELS		2
+#define	DEV_Z8530_LENGTH	4
+
+struct z8530_data {
+	struct interrupt irq;
+	int		irq_asserted;
+	int		addr_mult;
+
+	int		console_handle[ZS_N_CHANNELS];
+	int		reg_select[ZS_N_CHANNELS];
+	uint8_t		rr[ZS_N_CHANNELS][ZS_N_REGS];
+	uint8_t		wr[ZS_N_CHANNELS][ZS_N_REGS];
+};
+
+
+/*
+ *  check_incoming():
+ *
+ *  Sets the RX interrupt flag for ports B and A, if something there is input
+ *  available on port 0 or 1, respectively.
+ */
+static void check_incoming(struct cpu *cpu, struct z8530_data *d)
+{
+	if (console_charavail(d->console_handle[0])) {
+		d->rr[1][3] |= ZSRR3_IP_B_RX;
+		d->rr[0][0] |= ZSRR0_RX_READY;
+	}
+	if (console_charavail(d->console_handle[1])) {
+		d->rr[1][3] |= ZSRR3_IP_A_RX;
+		d->rr[1][0] |= ZSRR0_RX_READY;
+	}
+}
+
+
+DEVICE_TICK(z8530)
+{
+	/*  Generate transmit and receive interrupts at regular intervals.  */
+	struct z8530_data *d = (struct z8530_data *) extra;
+	int asserted = 0;
+
+	if (d->rr[1][3] & ZSRR3_IP_B_TX && d->wr[0][1] & ZSWR1_TIE)
+		asserted = 1;
+	if (d->rr[1][3] & ZSRR3_IP_A_TX && d->wr[1][1] & ZSWR1_TIE)
+		asserted = 1;
+
+	d->rr[1][3] &= ~(ZSRR3_IP_B_RX | ZSRR3_IP_A_RX);
+	if (!asserted)
+		check_incoming(cpu, d);
+
+	if (d->rr[1][3] & ZSRR3_IP_B_RX && (d->wr[0][1]&0x18) != ZSWR1_RIE_NONE)
+		asserted = 1;
+	if (d->rr[1][3] & ZSRR3_IP_A_RX && (d->wr[1][1]&0x18) != ZSWR1_RIE_NONE)
+		asserted = 1;
+
+	if (!(d->wr[1][9] & ZSWR9_MASTER_IE))
+		asserted = 0;
+
+	if (asserted)
+		INTERRUPT_ASSERT(d->irq);
+
+	if (d->irq_asserted && !asserted)
+		INTERRUPT_DEASSERT(d->irq);
+
+	d->irq_asserted = asserted;
+}
+
+
+DEVICE_ACCESS(z8530)
+{
+	struct z8530_data *d = (struct z8530_data *) extra;
+	uint64_t idata = 0, odata = 0;
+	int port_nr;
+
+	if (writeflag == MEM_WRITE)
+		idata = memory_readmax64(cpu, data, len);
+
+	/*  Both ports are always ready to transmit:  */
+	d->rr[0][0] |= ZSRR0_TX_READY | ZSRR0_DCD | ZSRR0_CTS;
+	d->rr[1][0] |= ZSRR0_TX_READY | ZSRR0_DCD | ZSRR0_CTS;
+
+	relative_addr /= d->addr_mult;
+
+	port_nr = (relative_addr / 2) % ZS_N_CHANNELS;
+	relative_addr &= 1;
+
+	if (relative_addr == 0) {
+		/*  Register access:  */
+		if (writeflag == MEM_READ) {
+			odata = d->rr[port_nr][d->reg_select[port_nr]];
+			debug("[ z8530: read from port %i reg %2i: "
+			    "0x%02x ]\n", port_nr, d->reg_select[
+			    port_nr], (int)odata);
+			d->reg_select[port_nr] = 0;
+		} else {
+			if (d->reg_select[port_nr] == 0) {
+				if (idata < 16)
+					d->reg_select[port_nr] = idata & 15;
+				else
+					d->reg_select[port_nr] = idata & 7;
+				switch (idata & 0xf8) {
+				case ZSWR0_CLR_INTR:	/*  Interrupt ack:  */
+					d->rr[1][3] = 0;
+					break;
+				}
+			} else {
+				d->wr[port_nr][d->reg_select[port_nr]] = idata;
+				switch (d->reg_select[port_nr]) {
+				default:debug("[ z8530: write to  port %i reg "
+					    "%2i: 0x%02x ]\n", port_nr, d->
+					    reg_select[port_nr], (int)idata);
+				}
+				d->reg_select[port_nr] = 0;
+			}
+		}
+	} else {
+		/*  Data access:  */
+		if (writeflag == MEM_READ) {
+			int x = console_readchar(d->console_handle[port_nr]);
+			d->rr[port_nr][0] &= ~ZSRR0_RX_READY;
+			odata = x < 0? 0 : x;
+		} else {
+			idata &= 255;
+			if (idata != 0)
+				console_putchar(d->console_handle[port_nr],
+				    idata);
+			if (1 /* d->wr[port_nr][1] & ZSWR1_TIE */) {
+				if (port_nr == 0)
+					d->rr[1][3] |= ZSRR3_IP_B_TX;
+				else
+					d->rr[1][3] |= ZSRR3_IP_A_TX;
+			}
+		}
+	}
+
+	if (writeflag == MEM_READ)
+		memory_writemax64(cpu, data, len, odata);
+
+	dev_z8530_tick(cpu, extra);
+
+	return 1;
+}
+
+
+DEVINIT(z8530)
+{
+	struct z8530_data *d;
+	char tmp[100];
+
+	CHECK_ALLOCATION(d = (struct z8530_data *) malloc(sizeof(struct z8530_data)));
+	memset(d, 0, sizeof(struct z8530_data));
+
+	d->addr_mult  = devinit->addr_mult;
+
+	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
+
+	snprintf(tmp, sizeof(tmp), "%s [ch-b]", devinit->name);
+	d->console_handle[0] = console_start_slave(devinit->machine, tmp,
+	    devinit->in_use);
+	snprintf(tmp, sizeof(tmp), "%s [ch-a]", devinit->name);
+	d->console_handle[1] = console_start_slave(devinit->machine, tmp, 0);
+
+	if (devinit->name2 != NULL && devinit->name2[0])
+		snprintf(tmp, sizeof(tmp), "%s [%s]", devinit->name,
+		    devinit->name2);
+	else
+		snprintf(tmp, sizeof(tmp), "%s", devinit->name);
+
+	memory_device_register(devinit->machine->memory, tmp, devinit->addr,
+	    DEV_Z8530_LENGTH * d->addr_mult, dev_z8530_access, d, DM_DEFAULT,
+	    NULL);
+
+	machine_add_tickfunction(devinit->machine, dev_z8530_tick, d,
+	    ZS_TICK_SHIFT);
+
+	devinit->return_ptr = (void *)(size_t) d->console_handle[0];
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_z8530.cc gxemul-0.7.0+dfsg/src/devices/dev_z8530.cc
--- gxemul-0.6.2/src/devices/dev_z8530.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_z8530.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,237 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Zilog Z8530 "zs" serial controller
- *
- *  Features:
- *	o)  Two channels, 0 = "channel B", 1 = "channel A".
- *	    Normally, only channel B is in use.
- *
- *  This is a work in progress... TODOs include:
- *	o)  Implement more of the register set.
- *	o)  Verify that it works with other guest OSes than NetBSD and OpenBSD.
- *	o)  Implement DMA!
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "interrupt.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/z8530reg.h"
-
-
-/*  #define debug fatal  */
-
-#define	ZS_TICK_SHIFT		14
-#define	ZS_N_REGS		16
-#define	ZS_N_CHANNELS		2
-#define	DEV_Z8530_LENGTH	4
-
-struct z8530_data {
-	struct interrupt irq;
-	int		irq_asserted;
-	int		addr_mult;
-
-	int		console_handle[ZS_N_CHANNELS];
-	int		reg_select[ZS_N_CHANNELS];
-	uint8_t		rr[ZS_N_CHANNELS][ZS_N_REGS];
-	uint8_t		wr[ZS_N_CHANNELS][ZS_N_REGS];
-};
-
-
-/*
- *  check_incoming():
- *
- *  Sets the RX interrupt flag for ports B and A, if something there is input
- *  available on port 0 or 1, respectively.
- */
-static void check_incoming(struct cpu *cpu, struct z8530_data *d)
-{
-	if (console_charavail(d->console_handle[0])) {
-		d->rr[1][3] |= ZSRR3_IP_B_RX;
-		d->rr[0][0] |= ZSRR0_RX_READY;
-	}
-	if (console_charavail(d->console_handle[1])) {
-		d->rr[1][3] |= ZSRR3_IP_A_RX;
-		d->rr[1][0] |= ZSRR0_RX_READY;
-	}
-}
-
-
-DEVICE_TICK(z8530)
-{
-	/*  Generate transmit and receive interrupts at regular intervals.  */
-	struct z8530_data *d = (struct z8530_data *) extra;
-	int asserted = 0;
-
-	if (d->rr[1][3] & ZSRR3_IP_B_TX && d->wr[0][1] & ZSWR1_TIE)
-		asserted = 1;
-	if (d->rr[1][3] & ZSRR3_IP_A_TX && d->wr[1][1] & ZSWR1_TIE)
-		asserted = 1;
-
-	d->rr[1][3] &= ~(ZSRR3_IP_B_RX | ZSRR3_IP_A_RX);
-	if (!asserted)
-		check_incoming(cpu, d);
-
-	if (d->rr[1][3] & ZSRR3_IP_B_RX && (d->wr[0][1]&0x18) != ZSWR1_RIE_NONE)
-		asserted = 1;
-	if (d->rr[1][3] & ZSRR3_IP_A_RX && (d->wr[1][1]&0x18) != ZSWR1_RIE_NONE)
-		asserted = 1;
-
-	if (!(d->wr[1][9] & ZSWR9_MASTER_IE))
-		asserted = 0;
-
-	if (asserted)
-		INTERRUPT_ASSERT(d->irq);
-
-	if (d->irq_asserted && !asserted)
-		INTERRUPT_DEASSERT(d->irq);
-
-	d->irq_asserted = asserted;
-}
-
-
-DEVICE_ACCESS(z8530)
-{
-	struct z8530_data *d = (struct z8530_data *) extra;
-	uint64_t idata = 0, odata = 0;
-	int port_nr;
-
-	if (writeflag == MEM_WRITE)
-		idata = memory_readmax64(cpu, data, len);
-
-	/*  Both ports are always ready to transmit:  */
-	d->rr[0][0] |= ZSRR0_TX_READY | ZSRR0_DCD | ZSRR0_CTS;
-	d->rr[1][0] |= ZSRR0_TX_READY | ZSRR0_DCD | ZSRR0_CTS;
-
-	relative_addr /= d->addr_mult;
-
-	port_nr = (relative_addr / 2) % ZS_N_CHANNELS;
-	relative_addr &= 1;
-
-	if (relative_addr == 0) {
-		/*  Register access:  */
-		if (writeflag == MEM_READ) {
-			odata = d->rr[port_nr][d->reg_select[port_nr]];
-			debug("[ z8530: read from port %i reg %2i: "
-			    "0x%02x ]\n", port_nr, d->reg_select[
-			    port_nr], (int)odata);
-			d->reg_select[port_nr] = 0;
-		} else {
-			if (d->reg_select[port_nr] == 0) {
-				if (idata < 16)
-					d->reg_select[port_nr] = idata & 15;
-				else
-					d->reg_select[port_nr] = idata & 7;
-				switch (idata & 0xf8) {
-				case ZSWR0_CLR_INTR:	/*  Interrupt ack:  */
-					d->rr[1][3] = 0;
-					break;
-				}
-			} else {
-				d->wr[port_nr][d->reg_select[port_nr]] = idata;
-				switch (d->reg_select[port_nr]) {
-				default:debug("[ z8530: write to  port %i reg "
-					    "%2i: 0x%02x ]\n", port_nr, d->
-					    reg_select[port_nr], (int)idata);
-				}
-				d->reg_select[port_nr] = 0;
-			}
-		}
-	} else {
-		/*  Data access:  */
-		if (writeflag == MEM_READ) {
-			int x = console_readchar(d->console_handle[port_nr]);
-			d->rr[port_nr][0] &= ~ZSRR0_RX_READY;
-			odata = x < 0? 0 : x;
-		} else {
-			idata &= 255;
-			if (idata != 0)
-				console_putchar(d->console_handle[port_nr],
-				    idata);
-			if (1 /* d->wr[port_nr][1] & ZSWR1_TIE */) {
-				if (port_nr == 0)
-					d->rr[1][3] |= ZSRR3_IP_B_TX;
-				else
-					d->rr[1][3] |= ZSRR3_IP_A_TX;
-			}
-		}
-	}
-
-	if (writeflag == MEM_READ)
-		memory_writemax64(cpu, data, len, odata);
-
-	dev_z8530_tick(cpu, extra);
-
-	return 1;
-}
-
-
-DEVINIT(z8530)
-{
-	struct z8530_data *d;
-	char tmp[100];
-
-	CHECK_ALLOCATION(d = (struct z8530_data *) malloc(sizeof(struct z8530_data)));
-	memset(d, 0, sizeof(struct z8530_data));
-
-	d->addr_mult  = devinit->addr_mult;
-
-	INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
-
-	snprintf(tmp, sizeof(tmp), "%s [ch-b]", devinit->name);
-	d->console_handle[0] = console_start_slave(devinit->machine, tmp,
-	    devinit->in_use);
-	snprintf(tmp, sizeof(tmp), "%s [ch-a]", devinit->name);
-	d->console_handle[1] = console_start_slave(devinit->machine, tmp, 0);
-
-	if (devinit->name2 != NULL && devinit->name2[0])
-		snprintf(tmp, sizeof(tmp), "%s [%s]", devinit->name,
-		    devinit->name2);
-	else
-		snprintf(tmp, sizeof(tmp), "%s", devinit->name);
-
-	memory_device_register(devinit->machine->memory, tmp, devinit->addr,
-	    DEV_Z8530_LENGTH * d->addr_mult, dev_z8530_access, d, DM_DEFAULT,
-	    NULL);
-
-	machine_add_tickfunction(devinit->machine, dev_z8530_tick, d,
-	    ZS_TICK_SHIFT);
-
-	devinit->return_ptr = (void *)(size_t) d->console_handle[0];
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/dev_zero.c gxemul-0.7.0+dfsg/src/devices/dev_zero.c
--- gxemul-0.6.2/src/devices/dev_zero.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_zero.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,61 @@
+/*
+ *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: A simple device which returns zero for reads, discards all writes
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "device.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+DEVICE_ACCESS(zero)
+{
+	if (writeflag == MEM_READ) {
+		size_t i;
+		for (i=0; i<len; i++)
+			data[i] = 0;
+	}
+
+	return 1;
+}
+
+
+DEVINIT(zero)
+{
+	memory_device_register(devinit->machine->memory,
+	    devinit->name, devinit->addr, devinit->len,
+	    dev_zero_access, NULL, DM_DEFAULT, NULL);
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/devices/dev_zero.cc gxemul-0.7.0+dfsg/src/devices/dev_zero.cc
--- gxemul-0.6.2/src/devices/dev_zero.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/dev_zero.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,61 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: A simple device which returns zero for reads, discards all writes
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "device.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-DEVICE_ACCESS(zero)
-{
-	if (writeflag == MEM_READ) {
-		size_t i;
-		for (i=0; i<len; i++)
-			data[i] = 0;
-	}
-
-	return 1;
-}
-
-
-DEVINIT(zero)
-{
-	memory_device_register(devinit->machine->memory,
-	    devinit->name, devinit->addr, devinit->len,
-	    dev_zero_access, NULL, DM_DEFAULT, NULL);
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/devices/fb_include.c gxemul-0.7.0+dfsg/src/devices/fb_include.c
--- gxemul-0.6.2/src/devices/fb_include.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/fb_include.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,365 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  Included from dev_fb.c.
+ *
+ *  FB_SCALEDOWN should be defined if d->vfb_scaledown > 1.
+ *  FB_BO for d->fb_window->fb_ximage->byte_order non-zero
+ *  FB_24 for 24-bit X11 color.
+ *  FB_16 for 16-bit X11 color.
+ *  FB_15 for 15-bit X11 color.
+ *  (Default is to fallback to grayscale.)
+ */
+
+
+#ifdef macro_put_pixel1
+#undef macro_put_pixel1
+#endif
+
+/*  Combine the color into an X11 long and display it:  */	\
+/*  TODO:  construct color in a more portable way:  */		\
+
+#ifdef FB_24
+#ifdef FB_BO
+#define macro_put_pixel1 color = (b << 16) + (g << 8) + r
+#else
+#define macro_put_pixel1 color = (r << 16) + (g << 8) + b
+#endif
+
+#else	/*  !24  */
+#ifdef FB_16
+#ifdef FB_BO
+#define macro_put_pixel1 color = ((b >> 3) << 11) + ((g >> 2) << 5) + (r >> 3)
+#else
+#define macro_put_pixel1 color = ((r >> 3) << 11) + ((g >> 2) << 5) + (b >> 3)
+#endif
+
+#else	/*  !16  */
+#ifdef FB_15
+#ifdef FB_BO
+#define macro_put_pixel1 color = ((b >> 3) << 10) + ((g >> 3) << 5) + (r >> 3)
+#else
+#define macro_put_pixel1 color = ((r >> 3) << 10) + ((g >> 3) << 5) + (b >> 3)
+#endif
+
+#else	/*  !15  */
+#define	macro_put_pixel1 color = d->fb_window->x11_graycolor[15 * 	\
+		(r + g + b) / (255 * 3)].pixel
+
+#endif	/*  !15  */
+
+#endif	/*  !16  */
+
+#endif	/*  !24  */
+
+
+#ifdef macro_put_pixel
+#undef macro_put_pixel
+#endif
+
+#define macro_put_pixel		macro_put_pixel1;			\
+	if (x>=0 && x<d->x11_xsize && y>=0 && y<d->x11_ysize)		\
+		XPutPixel(d->fb_window->fb_ximage, x, y, color);	\
+
+
+void REDRAW(struct vfb_data *d, int addr, int len)
+{
+	int x, y, pixel, npixels;
+	long color;
+
+#ifndef FB_SCALEDOWN
+
+	/*  Which framebuffer pixel does addr correspond to?  */
+	pixel = addr * 8 / d->bit_depth;
+	y = pixel / d->xsize;
+	x = pixel % d->xsize;
+
+	/*  How many framebuffer pixels? (len doesn't include the last pixel)  */
+	npixels = len * 8 / d->bit_depth;
+	npixels += d->bit_depth >= 8 ? 1 : (8 / d->bit_depth);
+
+	if (d->bit_depth < 8) {
+		for (pixel=0; pixel<npixels; pixel++) {
+			int c, r, g, b;
+			size_t fb_addr = (y * d->xsize + x) * d->bit_depth;
+			/*  fb_addr is now which _bit_ in the framebuffer  */
+
+			c = d->framebuffer[fb_addr >> 3];
+			fb_addr &= 7;
+
+			/*  HPC is reverse:  */
+			if (d->vfb_type == VFB_HPC || d->vfb_type == VFB_REVERSEBITS)
+				fb_addr = 8 - d->bit_depth - fb_addr;
+
+			c = (c >> fb_addr) & ((1<<d->bit_depth) - 1);
+			/*  c <<= (8 - d->bit_depth);  */
+
+			r = d->rgb_palette[c*3 + 0];
+			g = d->rgb_palette[c*3 + 1];
+			b = d->rgb_palette[c*3 + 2];
+
+			macro_put_pixel;
+			x++;
+		}
+	} else if (d->bit_depth == 8) {
+		for (pixel=0; pixel<npixels; pixel++) {
+			int c, r, g, b;
+			size_t fb_addr = y * d->xsize + x;
+			/*  fb_addr is now which byte in framebuffer  */
+
+			c = d->framebuffer[fb_addr];
+			r = d->rgb_palette[c*3 + 0];
+			g = d->rgb_palette[c*3 + 1];
+			b = d->rgb_palette[c*3 + 2];
+
+			macro_put_pixel;
+			x++;
+		}
+	} else {	/*  d->bit_depth > 8  */
+		for (pixel=0; pixel<npixels; pixel++) {
+			int r, g, b;
+			size_t fb_addr = (y * d->xsize + x) * d->bit_depth;
+			/*  fb_addr is now which byte in framebuffer  */
+
+			/*  > 8 bits color.  */
+			fb_addr >>= 3;
+			switch (d->bit_depth) {
+			case 24:
+			case 32:
+				r = d->framebuffer[fb_addr];
+				g = d->framebuffer[fb_addr + 1];
+				b = d->framebuffer[fb_addr + 2];
+				break;
+			case 16:
+				if (d->vfb_type == VFB_HPC) {
+					b = d->framebuffer[fb_addr] +
+					    (d->framebuffer[fb_addr+1] << 8);
+
+					if (d->color32k) {
+						r = b >> 11;
+						g = b >> 5;
+						r = r & 31;
+						g = (g & 31) * 2;
+						b = b & 31;
+					} else if (d->psp_15bit) {
+						int tmp;
+						r = (b >> 10) & 0x1f;
+						g = (b >>  5) & 0x1f;
+						b = b & 0x1f;
+						g <<= 1;
+						tmp = r; r = b; b = tmp;
+					} else {
+						r = (b >> 11) & 0x1f;
+						g = (b >>  5) & 0x3f;
+						b = b & 0x1f;
+					}
+				} else {
+				    r = d->framebuffer[fb_addr] >> 3;
+/*  HUH? TODO:  */
+				    g = (d->framebuffer[fb_addr] << 5) +
+				      (d->framebuffer[fb_addr + 1] >>5);
+				    b = d->framebuffer[fb_addr + 1]&31;
+				}
+
+				r *= 8;
+				g *= 4;
+				b *= 8;
+				break;
+			default:
+				r = g = b = random() & 255;
+			}
+
+			macro_put_pixel;
+			x++;
+		}
+	}
+
+#else	/*  FB_SCALEDOWN  */
+
+	/*  scaledown > 1:  */
+	int scaledown = d->vfb_scaledown;
+	int scaledownXscaledown = scaledown * scaledown;
+
+	/*  Which framebuffer pixel does addr correspond to?  */
+	pixel = addr * 8 / d->bit_depth;
+	y = pixel / d->xsize;
+	x = pixel % d->xsize;
+
+	/*  How many framebuffer pixels?  */
+	npixels = len * 8 / d->bit_depth;
+
+	/*  Which x11 pixel?  */
+	x /= scaledown;
+	y /= scaledown;
+
+	/*  How many x11 pixels:  */
+	npixels /= scaledown;
+	if (npixels == 0)
+		npixels = 1;
+
+	if (d->bit_depth < 8) {
+		for (pixel=0; pixel<npixels; pixel++) {
+			int subx, suby, r, g, b;
+			int64_t color_r = 0, color_g = 0, color_b = 0;
+			for (suby=0; suby<scaledown; suby++)
+			    for (subx=0; subx<scaledown; subx++) {
+				int fb_x, fb_y, fb_addr, c;
+
+				fb_x = x * scaledown + subx;
+				fb_y = y * scaledown + suby;
+				fb_addr = fb_y * d->xsize + fb_x;
+				fb_addr = fb_addr * d->bit_depth;
+				/*  fb_addr is now which _bit_ in
+				    the framebuffer  */
+
+				c = d->framebuffer[fb_addr >> 3];
+				fb_addr &= 7;
+
+				/*  HPC is reverse:  */
+				if (d->vfb_type == VFB_HPC || d->vfb_type == VFB_REVERSEBITS)
+					fb_addr = 8 - d->bit_depth - fb_addr;
+
+				c = (c >> fb_addr) & ((1<<d->bit_depth) - 1);
+				/*  c <<= (8 - d->bit_depth);  */
+
+				r = d->rgb_palette[c*3 + 0];
+				g = d->rgb_palette[c*3 + 1];
+				b = d->rgb_palette[c*3 + 2];
+
+				color_r += r;
+				color_g += g;
+				color_b += b;
+			    }
+
+			r = color_r / scaledownXscaledown;
+			g = color_g / scaledownXscaledown;
+			b = color_b / scaledownXscaledown;
+			macro_put_pixel;
+			x++;
+		}
+	} else if (d->bit_depth == 8) {
+		for (pixel=0; pixel<npixels; pixel++) {
+			int subx, suby, r, g, b;
+			int64_t color_r = 0, color_g = 0, color_b = 0;
+			for (suby=0; suby<scaledown; suby++)
+			    for (subx=0; subx<scaledown; subx++) {
+				int fb_x, fb_y, fb_addr, c;
+
+				fb_x = x * scaledown + subx;
+				fb_y = y * scaledown + suby;
+				fb_addr = fb_y * d->xsize + fb_x;
+				/*  fb_addr is which _byte_ in framebuffer  */
+				c = d->framebuffer[fb_addr] * 3;
+				r = d->rgb_palette[c + 0];
+				g = d->rgb_palette[c + 1];
+				b = d->rgb_palette[c + 2];
+				color_r += r;
+				color_g += g;
+				color_b += b;
+			    }
+
+			r = color_r / scaledownXscaledown;
+			g = color_g / scaledownXscaledown;
+			b = color_b / scaledownXscaledown;
+			macro_put_pixel;
+			x++;
+		}
+	} else {
+		/*  Generic > 8 bit bit-depth:  */
+		for (pixel=0; pixel<npixels; pixel++) {
+			int subx, suby, r, g, b;
+			int64_t color_r = 0, color_g = 0, color_b = 0;
+			for (suby=0; suby<scaledown; suby++)
+			    for (subx=0; subx<scaledown; subx++) {
+				int fb_x, fb_y, fb_addr;
+
+				fb_x = x * scaledown + subx;
+				fb_y = y * scaledown + suby;
+				fb_addr = fb_y * d->xsize + fb_x;
+				fb_addr = (fb_addr * d->bit_depth) >> 3;
+				/*  fb_addr is which _byte_ in framebuffer  */
+
+				/*  > 8 bits color.  */
+				switch (d->bit_depth) {
+				case 24:
+				case 32:
+					r = d->framebuffer[fb_addr];
+					g = d->framebuffer[fb_addr + 1];
+					b = d->framebuffer[fb_addr + 2];
+					break;
+				case 16:
+					if (d->vfb_type == VFB_HPC) {
+						b = d->framebuffer[fb_addr] +
+						    (d->framebuffer[fb_addr+1] << 8);
+
+						if (d->color32k) {
+							r = b >> 11;
+							g = b >> 5;
+							r = r & 31;
+							g = (g & 31) * 2;
+							b = b & 31;
+						} else if (d->psp_15bit) {
+							int tmp;
+							r = (b >> 10) & 0x1f;
+							g = (b >>  5) & 0x1f;
+							b = b & 0x1f;
+							g <<= 1;
+							tmp = r; r = b; b = tmp;
+						} else {
+							r = (b >> 11) & 0x1f;
+							g = (b >>  5) & 0x3f;
+							b = b & 0x1f;
+						}
+					} else {
+					    r = d->framebuffer[fb_addr] >> 3;
+/*  HUH? TODO:  */
+					    g = (d->framebuffer[fb_addr] << 5) +
+					      (d->framebuffer[fb_addr + 1] >>5);
+					    b = d->framebuffer[fb_addr + 1]&31;
+					}
+
+					r *= 8;
+					g *= 4;
+					b *= 8;
+					break;
+				default:
+					r = g = b = random() & 255;
+				}
+				color_r += r;
+				color_g += g;
+				color_b += b;
+			    }
+			r = color_r / scaledownXscaledown;
+			g = color_g / scaledownXscaledown;
+			b = color_b / scaledownXscaledown;
+			macro_put_pixel;
+			x++;
+		}
+	}
+#endif	/*  FB_SCALEDOWN  */
+}
+
diff -Nru gxemul-0.6.2/src/devices/fb_include.cc gxemul-0.7.0+dfsg/src/devices/fb_include.cc
--- gxemul-0.6.2/src/devices/fb_include.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/fb_include.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,373 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  Included from dev_fb.c.
- *
- *  FB_SCALEDOWN should be defined if d->vfb_scaledown > 1.
- *  FB_BO for d->fb_window->fb_ximage->byte_order non-zero
- *  FB_24 for 24-bit X11 color.
- *  FB_16 for 16-bit X11 color.
- *  FB_15 for 15-bit X11 color.
- *  (Default is to fallback to grayscale.)
- */
-
-
-#ifdef macro_put_pixel1
-#undef macro_put_pixel1
-#endif
-
-/*  Combine the color into an X11 long and display it:  */	\
-/*  TODO:  construct color in a more portable way:  */		\
-
-#ifdef FB_24
-#ifdef FB_BO
-#define macro_put_pixel1 color = (b << 16) + (g << 8) + r
-#else
-#define macro_put_pixel1 color = (r << 16) + (g << 8) + b
-#endif
-
-#else	/*  !24  */
-#ifdef FB_16
-#ifdef FB_BO
-#define macro_put_pixel1 color = ((b >> 3) << 11) + ((g >> 2) << 5) + (r >> 3)
-#else
-#define macro_put_pixel1 color = ((r >> 3) << 11) + ((g >> 2) << 5) + (b >> 3)
-#endif
-
-#else	/*  !16  */
-#ifdef FB_15
-#ifdef FB_BO
-#define macro_put_pixel1 color = ((b >> 3) << 10) + ((g >> 3) << 5) + (r >> 3)
-#else
-#define macro_put_pixel1 color = ((r >> 3) << 10) + ((g >> 3) << 5) + (b >> 3)
-#endif
-
-#else	/*  !15  */
-#define	macro_put_pixel1 color = d->fb_window->x11_graycolor[15 * 	\
-		(r + g + b) / (255 * 3)].pixel
-
-#endif	/*  !15  */
-
-#endif	/*  !16  */
-
-#endif	/*  !24  */
-
-
-#ifdef macro_put_pixel
-#undef macro_put_pixel
-#endif
-
-#define macro_put_pixel		macro_put_pixel1;			\
-	if (x>=0 && x<d->x11_xsize && y>=0 && y<d->x11_ysize)		\
-		XPutPixel(d->fb_window->fb_ximage, x, y, color);	\
-
-
-void REDRAW(struct vfb_data *d, int addr, int len)
-{
-	int x, y, pixel, npixels;
-	long color_r, color_g, color_b;
-	long color;
-
-#ifndef FB_SCALEDOWN
-
-	/*  Which framebuffer pixel does addr correspond to?  */
-	pixel = addr * 8 / d->bit_depth;
-	y = pixel / d->xsize;
-	x = pixel % d->xsize;
-
-	/*  How many framebuffer pixels?  */
-	npixels = len * 8 / d->bit_depth;
-	if (npixels == 0)
-		npixels = 1;
-
-	if (d->bit_depth < 8) {
-		for (pixel=0; pixel<npixels; pixel++) {
-			int fb_addr, c, r, g, b;
-			color_r = color_g = color_b = 0;
-
-			fb_addr = (y * d->xsize + x) * d->bit_depth;
-			/*  fb_addr is now which _bit_ in
-			    the framebuffer  */
-
-			c = d->framebuffer[fb_addr >> 3];
-			fb_addr &= 7;
-
-			/*  HPC is reverse:  */
-			if (d->vfb_type == VFB_HPC)
-				fb_addr = 8 - d->bit_depth - fb_addr;
-
-			c = (c >> fb_addr) & ((1<<d->bit_depth) - 1);
-			/*  c <<= (8 - d->bit_depth);  */
-
-			r = d->rgb_palette[c*3 + 0];
-			g = d->rgb_palette[c*3 + 1];
-			b = d->rgb_palette[c*3 + 2];
-
-			macro_put_pixel;
-			x++;
-		}
-	} else if (d->bit_depth == 8) {
-		for (pixel=0; pixel<npixels; pixel++) {
-			int fb_addr, c, r, g, b;
-			color_r = color_g = color_b = 0;
-
-			fb_addr = y * d->xsize + x;
-			/*  fb_addr is now which byte in framebuffer  */
-			c = d->framebuffer[fb_addr];
-			r = d->rgb_palette[c*3 + 0];
-			g = d->rgb_palette[c*3 + 1];
-			b = d->rgb_palette[c*3 + 2];
-
-			macro_put_pixel;
-			x++;
-		}
-	} else {	/*  d->bit_depth > 8  */
-		for (pixel=0; pixel<npixels; pixel++) {
-			int fb_addr, r, g, b;
-			color_r = color_g = color_b = 0;
-
-			fb_addr = (y * d->xsize + x) * d->bit_depth;
-			/*  fb_addr is now which byte in framebuffer  */
-
-			/*  > 8 bits color.  */
-			fb_addr >>= 3;
-			switch (d->bit_depth) {
-			case 24:
-			case 32:
-				r = d->framebuffer[fb_addr];
-				g = d->framebuffer[fb_addr + 1];
-				b = d->framebuffer[fb_addr + 2];
-				break;
-			case 16:
-				if (d->vfb_type == VFB_HPC) {
-					b = d->framebuffer[fb_addr] +
-					    (d->framebuffer[fb_addr+1] << 8);
-
-					if (d->color32k) {
-						r = b >> 11;
-						g = b >> 5;
-						r = r & 31;
-						g = (g & 31) * 2;
-						b = b & 31;
-					} else if (d->psp_15bit) {
-						int tmp;
-						r = (b >> 10) & 0x1f;
-						g = (b >>  5) & 0x1f;
-						b = b & 0x1f;
-						g <<= 1;
-						tmp = r; r = b; b = tmp;
-					} else {
-						r = (b >> 11) & 0x1f;
-						g = (b >>  5) & 0x3f;
-						b = b & 0x1f;
-					}
-				} else {
-				    r = d->framebuffer[fb_addr] >> 3;
-/*  HUH? TODO:  */
-				    g = (d->framebuffer[fb_addr] << 5) +
-				      (d->framebuffer[fb_addr + 1] >>5);
-				    b = d->framebuffer[fb_addr + 1]&31;
-				}
-
-				r *= 8;
-				g *= 4;
-				b *= 8;
-				break;
-			default:
-				r = g = b = random() & 255;
-			}
-
-			macro_put_pixel;
-			x++;
-		}
-	}
-
-#else	/*  FB_SCALEDOWN  */
-
-	/*  scaledown > 1:  */
-	int scaledown = d->vfb_scaledown;
-	int scaledownXscaledown = scaledown * scaledown;
-
-	/*  Which framebuffer pixel does addr correspond to?  */
-	pixel = addr * 8 / d->bit_depth;
-	y = pixel / d->xsize;
-	x = pixel % d->xsize;
-
-	/*  How many framebuffer pixels?  */
-	npixels = len * 8 / d->bit_depth;
-
-	/*  Which x11 pixel?  */
-	x /= scaledown;
-	y /= scaledown;
-
-	/*  How many x11 pixels:  */
-	npixels /= scaledown;
-	if (npixels == 0)
-		npixels = 1;
-
-	if (d->bit_depth < 8) {
-		for (pixel=0; pixel<npixels; pixel++) {
-			int subx, suby, r, g, b;
-			color_r = color_g = color_b = 0;
-			for (suby=0; suby<scaledown; suby++)
-			    for (subx=0; subx<scaledown; subx++) {
-				int fb_x, fb_y, fb_addr, c;
-
-				fb_x = x * scaledown + subx;
-				fb_y = y * scaledown + suby;
-				fb_addr = fb_y * d->xsize + fb_x;
-				fb_addr = fb_addr * d->bit_depth;
-				/*  fb_addr is now which _bit_ in
-				    the framebuffer  */
-
-				c = d->framebuffer[fb_addr >> 3];
-				fb_addr &= 7;
-
-				/*  HPC is reverse:  */
-				if (d->vfb_type == VFB_HPC)
-					fb_addr = 8 - d->bit_depth - fb_addr;
-
-				c = (c >> fb_addr) & ((1<<d->bit_depth) - 1);
-				/*  c <<= (8 - d->bit_depth);  */
-
-				r = d->rgb_palette[c*3 + 0];
-				g = d->rgb_palette[c*3 + 1];
-				b = d->rgb_palette[c*3 + 2];
-
-				color_r += r;
-				color_g += g;
-				color_b += b;
-			    }
-
-			r = color_r / scaledownXscaledown;
-			g = color_g / scaledownXscaledown;
-			b = color_b / scaledownXscaledown;
-			macro_put_pixel;
-			x++;
-		}
-	} else if (d->bit_depth == 8) {
-		for (pixel=0; pixel<npixels; pixel++) {
-			int subx, suby, r, g, b;
-			color_r = color_g = color_b = 0;
-			for (suby=0; suby<scaledown; suby++)
-			    for (subx=0; subx<scaledown; subx++) {
-				int fb_x, fb_y, fb_addr, c;
-
-				fb_x = x * scaledown + subx;
-				fb_y = y * scaledown + suby;
-				fb_addr = fb_y * d->xsize + fb_x;
-				/*  fb_addr is which _byte_ in framebuffer  */
-				c = d->framebuffer[fb_addr] * 3;
-				r = d->rgb_palette[c + 0];
-				g = d->rgb_palette[c + 1];
-				b = d->rgb_palette[c + 2];
-				color_r += r;
-				color_g += g;
-				color_b += b;
-			    }
-
-			r = color_r / scaledownXscaledown;
-			g = color_g / scaledownXscaledown;
-			b = color_b / scaledownXscaledown;
-			macro_put_pixel;
-			x++;
-		}
-	} else {
-		/*  Generic > 8 bit bit-depth:  */
-		for (pixel=0; pixel<npixels; pixel++) {
-			int subx, suby, r, g, b;
-			color_r = color_g = color_b = 0;
-			for (suby=0; suby<scaledown; suby++)
-			    for (subx=0; subx<scaledown; subx++) {
-				int fb_x, fb_y, fb_addr;
-
-				fb_x = x * scaledown + subx;
-				fb_y = y * scaledown + suby;
-				fb_addr = fb_y * d->xsize + fb_x;
-				fb_addr = (fb_addr * d->bit_depth) >> 3;
-				/*  fb_addr is which _byte_ in framebuffer  */
-
-				/*  > 8 bits color.  */
-				switch (d->bit_depth) {
-				case 24:
-				case 32:
-					r = d->framebuffer[fb_addr];
-					g = d->framebuffer[fb_addr + 1];
-					b = d->framebuffer[fb_addr + 2];
-					break;
-				case 16:
-					if (d->vfb_type == VFB_HPC) {
-						b = d->framebuffer[fb_addr] +
-						    (d->framebuffer[fb_addr+1] << 8);
-
-						if (d->color32k) {
-							r = b >> 11;
-							g = b >> 5;
-							r = r & 31;
-							g = (g & 31) * 2;
-							b = b & 31;
-						} else if (d->psp_15bit) {
-							int tmp;
-							r = (b >> 10) & 0x1f;
-							g = (b >>  5) & 0x1f;
-							b = b & 0x1f;
-							g <<= 1;
-							tmp = r; r = b; b = tmp;
-						} else {
-							r = (b >> 11) & 0x1f;
-							g = (b >>  5) & 0x3f;
-							b = b & 0x1f;
-						}
-					} else {
-					    r = d->framebuffer[fb_addr] >> 3;
-/*  HUH? TODO:  */
-					    g = (d->framebuffer[fb_addr] << 5) +
-					      (d->framebuffer[fb_addr + 1] >>5);
-					    b = d->framebuffer[fb_addr + 1]&31;
-					}
-
-					r *= 8;
-					g *= 4;
-					b *= 8;
-					break;
-				default:
-					r = g = b = random() & 255;
-				}
-				color_r += r;
-				color_g += g;
-				color_b += b;
-			    }
-			r = color_r / scaledownXscaledown;
-			g = color_g / scaledownXscaledown;
-			b = color_b / scaledownXscaledown;
-			macro_put_pixel;
-			x++;
-		}
-	}
-#endif	/*  FB_SCALEDOWN  */
-}
-
diff -Nru gxemul-0.6.2/src/devices/fonts/Makefile.skel gxemul-0.7.0+dfsg/src/devices/fonts/Makefile.skel
--- gxemul-0.6.2/src/devices/fonts/Makefile.skel	2019-06-22 18:23:21.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/fonts/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -1,16 +1,16 @@
-all: font8x8.cc font8x10.cc font8x16.cc
+all: font8x8.c font8x10.c font8x16.c
 
-font8x8.cc: Xconv_raw_to_c
-	./Xconv_raw_to_c vt220l.808 font8x8 > font8x8.cc
+font8x8.c: Xconv_raw_to_c
+	./Xconv_raw_to_c vt220l.808 font8x8 > font8x8.c
 
-font8x10.cc: Xconv_raw_to_c
-	./Xconv_raw_to_c vt220l.810 font8x10 > font8x10.cc
+font8x10.c: Xconv_raw_to_c
+	./Xconv_raw_to_c vt220l.810 font8x10 > font8x10.c
 
-font8x16.cc: Xconv_raw_to_c
-	./Xconv_raw_to_c vt220l.816 font8x16 > font8x16.cc
+font8x16.c: Xconv_raw_to_c
+	./Xconv_raw_to_c vt220l.816 font8x16 > font8x16.c
 
 clean:
-	rm -f Xconv_raw_to_c font8x16.cc font8x8.cc font8x10.cc
+	rm -f Xconv_raw_to_c font8x16.c font8x8.c font8x10.c
 
 clean_all: clean
 	rm -f Makefile
diff -Nru gxemul-0.6.2/src/devices/.index gxemul-0.7.0+dfsg/src/devices/.index
--- gxemul-0.6.2/src/devices/.index	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/.index	2021-11-27 09:42:23.000000000 +0000
@@ -1,107 +1,109 @@
-bus_isa.cc  Generic ISA bus framework
-bus_pci.cc  Generic PCI bus framework
-dev_8253.cc  Intel 8253/8254 Programmable Interval Timer
-dev_8259.cc  Intel 8259 Programmable Interrupt Controller
-dev_adb.cc  Apple Desktop Bus (ADB) controller
-dev_ahc.cc  Adaptec AHC SCSI controller
-dev_algor.cc  Algor P5064 misc. stuff
-dev_asc.cc  NCR53C9X "ASC" SCSI controller
-dev_bebox.cc  BeBox motherboard registers and interrupt controller
-dev_bt431.cc  Brooktree BT431, used by TURBOchannel graphics cards
-dev_bt455.cc  Brooktree BT455, used by TURBOchannel graphics cards
-dev_bt459.cc  Brooktree BT459, used by TURBOchannel graphics cards
-dev_clmpcc.cc  Cirrus Logic 4-Channel Communications Controller (CD2400/CD2401)
-dev_colorplanemask.cc  Color plane mask, used in the DECstation 3100 machine
-dev_cons.cc  A simple console device, for the test machines
-dev_cpc700.cc  IBM CPC700 bridge (PCI and interrupt controller)
-dev_dc7085.cc  DC7085 serial controller, used in some DECstation models
-dev_dec21030.cc  DEC 21030 "TGA" graphics card
-dev_dec21143.cc  DEC 21143 "Tulip" ethernet controller
-dev_dec5800.cc  DECsystem 58x0 devices
-dev_dec_ioasic.cc  IOASIC device used in some DECstation machines
-dev_disk.cc  A simple disk controller device, for the test machines
-dev_dreamcast_asic.cc  Dreamcast-specific ASIC
-dev_dreamcast_g2.cc  Dreamcast G2 bus
-dev_dreamcast_gdrom.cc  Dreamcast GD-ROM
-dev_dreamcast_maple.cc  Dreamcast Maple bus controller
-dev_dreamcast_rtc.cc  Dreamcast Real-Time Clock
-dev_eagle.cc  Motorola MPC105 "Eagle" host bridge
-dev_ether.cc  A simple ethernet controller, for the test machines
-dev_fb.cc  Generic framebuffer device
-dev_fbctrl.cc  Framebuffer controller device (control's dev_fb in test machines)
-dev_fdc.cc  PC-style floppy controller
-dev_footbridge.cc  DC21285 "Footbridge" controller; used in Netwinder and Cats
-dev_gc.cc  Grand Central Interrupt controller (used by MacPPC)
-dev_gt.cc  Galileo Technology GT-64xxx PCI controller
-dev_hammerhead.cc  Hammerhead controller, for the secondary CPU on MacPPC machines
-dev_i80321.cc  Intel i80321 (ARM) core functionality
-dev_igsfb.cc  Integraphics Systems "igsfb" Framebuffer graphics card
-dev_iq80321_7seg.cc  IQ80321 LED device
-dev_irqc.cc  Generic IRQ controller for the test machines
-dev_jazz.cc  Microsoft Jazz-related stuff (Acer PICA-61, etc)
-dev_kn01.cc  DEC KN01 ("PMAX", DECstation type 1) control register and VDAC
-dev_kn02.cc  DEC KN02 mainbus (TurboChannel interrupt controller)
-dev_kn02ba.cc  DEC KN02BA "3min" TurboChannel interrupt controller
-dev_kn220.cc  DEC KN220 (DECsystem 5500) devices
-dev_kn230.cc  DEC KN230 (MIPSMATE 5100) stuff
-dev_lca.cc  LCA PCI bus, for Alpha machines
-dev_le.cc  LANCE ethernet, as used in DECstations
-dev_lpt.cc  LPT (parallel printer) controller
-dev_luna88k.cc  OMRON Luna 88K-specific devices and control registers
-dev_m8820x.cc  M88200/M88204 CMMU (Cache/Memory Management Unit)
-dev_malta_lcd.cc  Malta (evbmips) LCD display
-dev_mb8696x.cc  Fujitsu MB8696x Ethernet interface (used in the Dreamcast)
-dev_mc146818.cc  MC146818 real-time clock
-dev_mk48txx.cc  Mostek MK48Txx Real Time Clock
-dev_mp.cc  Generic Multi-processor controller for the test machines
-dev_mvme187.cc  MVME187-specific devices and control registers
-dev_ns16550.cc  NS16550 serial controller
-dev_ohci.cc  USB Open Host Controller Interface
-dev_osiop.cc  NCR 53C710 SCSI I/O Processor (SIOP)
-dev_palmbus.cc  VoCore Palmbus
-dev_pcc2.cc  Peripheral Channel Controller (PCC2) bus (used in MVME machines)
-dev_pccmos.cc  PC CMOS/RTC device (ISA ports 0x70 and 0x71)
-dev_pcic.cc  Intel 82365SL PC Card Interface Controller
-dev_pckbc.cc  8042 PC keyboard controller (+ 8242WB Keyboard/Mouse controller)
-dev_pmagja.cc  TURBOchannel PMAG-JA graphics card
-dev_pmppc.cc  Artesyn PM/PPC motherboard registers
-dev_prep.cc  PReP machine mainbus (ISA bus + interrupt controller)
-dev_ps2_ether.cc  PlayStation 2 ethernet (smap and emac3)
-dev_ps2_gif.cc  PlayStation 2 "gif" graphics device
-dev_ps2_gs.cc  PlayStation 2 graphics system
-dev_ps2_spd.cc  PlayStation 2 SPD harddisk controller
-dev_ps2_stuff.cc  PlayStation 2 misc stuff (timer, DMA, interrupts, ...)
-dev_pvr.cc  PowerVR CLX2 (graphics controller used in the Dreamcast)
-dev_px.cc  TURBOchannel Pixelstamp graphics card
-dev_ram.cc  A generic RAM (memory) device
-dev_random.cc  A device which returns random data for reads, discards all writes
-dev_rs5c313.cc  RICOH RS5C313 Real Time Clock
-dev_rtc.cc  A generic Real-Time Clock device, for the test machines
-dev_rtl8139c.cc  Realtek 8139 ethernet controller
-dev_scc.cc  Serial controller used in some DECsystem and SGI machines
-dev_sfb.cc  SFB TURBOchannel framebuffer (graphics card)
-dev_sgi_gbe.cc  SGI "Graphics Back End", graphics controller + framebuffer
-dev_sgi_ip19.cc  SGI IP19 (and IP25) stuff
-dev_sgi_ip20.cc  SGI IP20 stuff
-dev_sgi_ip22.cc  SGI IP22 stuff
-dev_sgi_ip30.cc  SGI IP30 ("Octane") stuff
-dev_sgi_ip32.cc  SGI IP32 stuff (CRIME, MACE, MACEPCI, ust)
-dev_sgi_mardigras.cc  MardiGras graphics controller on SGI IP30 (Octane)
-dev_sgi_mec.cc  SGI IP32 "mec" ethernet
-dev_sgi_re.cc  SGI O2 "Rendering Engine"
-dev_sh4.cc  SH4-specific memory mapped registers (0xf0000000 - 0xffffffff)
-dev_sii.cc  SII SCSI controller, used in some DECstation systems
-dev_sn.cc  National Semiconductor SONIC ("sn") DP83932 ethernet controller
-dev_ssc.cc  System Support Chip serial controller
-dev_turbochannel.cc  TURBOchannel bus framework, used in DECstation machines
-dev_uninorth.cc  Uni-North PCI controller (used by MacPPC machines)
-dev_unreadable.cc  A simple device which returns an error for all reads/writes
-dev_v3.cc  V3 Semiconductor PCI controller
-dev_vga.cc  VGA framebuffer device (charcell and graphics modes)
-dev_vme.cc  VME bus
-dev_vr41xx.cc  VR41xx (VR4122 and VR4131) misc functions
-dev_wdc.cc  Standard "wdc" IDE controller
-dev_z8530.cc  Zilog Z8530 "zs" serial controller
-dev_zero.cc  A simple device which returns zero for reads, discards all writes
-device.cc  Device registry framework
-lk201.cc  LK201 keyboard and mouse, used by the dc7085 and scc controllers
+bus_isa.c  Generic ISA bus framework
+bus_pci.c  Generic PCI bus framework
+dev_8253.c  Intel 8253/8254 Programmable Interval Timer
+dev_8259.c  Intel 8259 Programmable Interrupt Controller
+dev_adb.c  Apple Desktop Bus (ADB) controller
+dev_ahc.c  Adaptec AHC SCSI controller
+dev_algor.c  Algor P5064 misc. stuff
+dev_asc.c  NCR53C9X "ASC" SCSI controller
+dev_bebox.c  BeBox motherboard registers and interrupt controller
+dev_bt431.c  Brooktree BT431, used by TURBOchannel graphics cards
+dev_bt455.c  Brooktree BT455, used by TURBOchannel graphics cards
+dev_bt459.c  Brooktree BT459, used by TURBOchannel graphics cards
+dev_clmpcc.c  Cirrus Logic 4-Channel Communications Controller (CD2400/CD2401)
+dev_colorplanemask.c  Color plane mask, used in the DECstation 3100 machine
+dev_cons.c  A simple console device, for the test machines
+dev_cpc700.c  IBM CPC700 bridge (PCI and interrupt controller)
+dev_dc7085.c  DC7085 serial controller, used in some DECstation models
+dev_dec21030.c  DEC 21030 "TGA" graphics card
+dev_dec21143.c  DEC 21143 "Tulip" ethernet controller
+dev_dec5800.c  DECsystem 58x0 devices
+dev_dec_ioasic.c  IOASIC device used in some DECstation machines
+dev_disk.c  A simple disk controller device, for the test machines
+dev_dreamcast_asic.c  Dreamcast-specific ASIC
+dev_dreamcast_g2.c  Dreamcast G2 bus
+dev_dreamcast_gdrom.c  Dreamcast GD-ROM
+dev_dreamcast_maple.c  Dreamcast Maple bus controller
+dev_dreamcast_rtc.c  Dreamcast Real-Time Clock
+dev_eagle.c  Motorola MPC105 "Eagle" host bridge
+dev_ether.c  A simple ethernet controller, for the test machines
+dev_fb.c  Generic framebuffer device
+dev_fbctrl.c  Framebuffer controller device (control's dev_fb in test machines)
+dev_fdc.c  PC-style floppy controller
+dev_footbridge.c  DC21285 "Footbridge" controller; used in Netwinder and Cats
+dev_gc.c  Grand Central Interrupt controller (used by MacPPC)
+dev_gt.c  Galileo Technology GT-64xxx PCI controller
+dev_hammerhead.c  Hammerhead controller, for the secondary CPU on MacPPC machines
+dev_i80321.c  Intel i80321 (ARM) core functionality
+dev_igsfb.c  Integraphics Systems "igsfb" Framebuffer graphics card
+dev_iq80321_7seg.c  IQ80321 LED device
+dev_irqc.c  Generic IRQ controller for the test machines
+dev_jazz.c  Microsoft Jazz-related stuff (Acer PICA-61, etc)
+dev_kn01.c  DEC KN01 ("PMAX", DECstation type 1) control register and VDAC
+dev_kn02.c  DEC KN02 mainbus (TurboChannel interrupt controller)
+dev_kn02ba.c  DEC KN02BA "3min" TurboChannel interrupt controller
+dev_kn220.c  DEC KN220 (DECsystem 5500) devices
+dev_kn230.c  DEC KN230 (MIPSMATE 5100) stuff
+dev_lca.c  LCA PCI bus, for Alpha machines
+dev_le.c  LANCE ethernet, as used in DECstations
+dev_lpt.c  LPT (parallel printer) controller
+dev_luna88k.c  OMRON Luna 88K-specific devices and control registers
+dev_lunafb.c  LUNA framebuffer
+dev_m8820x.c  M88200/M88204 CMMU (Cache/Memory Management Unit)
+dev_malta_lcd.c  Malta (evbmips) LCD display
+dev_mb8696x.c  Fujitsu MB8696x Ethernet interface (used in the Dreamcast)
+dev_mb89352.c  Fujitsu MB89352 SCSI Protocol Controller (SPC)
+dev_mc146818.c  MC146818 real-time clock
+dev_mk48txx.c  Mostek MK48Txx Real Time Clock
+dev_mp.c  Generic Multi-processor controller for the test machines
+dev_mvme187.c  MVME187-specific devices and control registers
+dev_ns16550.c  NS16550 serial controller
+dev_ohci.c  USB Open Host Controller Interface
+dev_osiop.c  NCR 53C710 SCSI I/O Processor (SIOP)
+dev_palmbus.c  VoCore Palmbus
+dev_pcc2.c  Peripheral Channel Controller (PCC2) bus (used in MVME machines)
+dev_pccmos.c  PC CMOS/RTC device (ISA ports 0x70 and 0x71)
+dev_pcic.c  Intel 82365SL PC Card Interface Controller
+dev_pckbc.c  8042 PC keyboard controller (+ 8242WB Keyboard/Mouse controller)
+dev_pmagja.c  TURBOchannel PMAG-JA graphics card
+dev_pmppc.c  Artesyn PM/PPC motherboard registers
+dev_prep.c  PReP machine mainbus (ISA bus + interrupt controller)
+dev_ps2_ether.c  PlayStation 2 ethernet (smap and emac3)
+dev_ps2_gif.c  PlayStation 2 "gif" graphics device
+dev_ps2_gs.c  PlayStation 2 graphics system
+dev_ps2_spd.c  PlayStation 2 SPD harddisk controller
+dev_ps2_stuff.c  PlayStation 2 misc stuff (timer, DMA, interrupts, ...)
+dev_pvr.c  PowerVR CLX2 (graphics controller used in the Dreamcast)
+dev_px.c  TURBOchannel Pixelstamp graphics card
+dev_ram.c  A generic RAM (memory) device
+dev_random.c  A device which returns random data for reads, discards all writes
+dev_rs5c313.c  RICOH RS5C313 Real Time Clock
+dev_rtc.c  A generic Real-Time Clock device, for the test machines
+dev_rtl8139c.c  Realtek 8139 ethernet controller
+dev_scc.c  Serial controller used in some DECsystem and SGI machines
+dev_sfb.c  SFB TURBOchannel framebuffer (graphics card)
+dev_sgi_gbe.c  SGI "Graphics Back End", graphics controller + framebuffer
+dev_sgi_ip19.c  SGI IP19 (and IP25) stuff
+dev_sgi_ip20.c  SGI IP20 stuff
+dev_sgi_ip22.c  SGI IP22 stuff
+dev_sgi_ip30.c  SGI IP30 ("Octane") stuff
+dev_sgi_ip32.c  SGI IP32 stuff (CRIME, MACE, MACEPCI, ust)
+dev_sgi_mardigras.c  MardiGras graphics controller on SGI IP30 (Octane)
+dev_sgi_mec.c  SGI IP32 "mec" ethernet
+dev_sgi_re.c  SGI O2 "Rendering Engine"
+dev_sh4.c  SH4-specific memory mapped registers (0xf0000000 - 0xffffffff)
+dev_sii.c  SII SCSI controller, used in some DECstation systems
+dev_sn.c  National Semiconductor SONIC ("sn") DP83932 ethernet controller
+dev_ssc.c  System Support Chip serial controller
+dev_turbochannel.c  TURBOchannel bus framework, used in DECstation machines
+dev_uninorth.c  Uni-North PCI controller (used by MacPPC machines)
+dev_unreadable.c  A simple device which returns an error for all reads/writes
+dev_v3.c  V3 Semiconductor PCI controller
+dev_vga.c  VGA framebuffer device (charcell and graphics modes)
+dev_vme.c  VME bus
+dev_vr41xx.c  VR41xx (VR4122 and VR4131) misc functions
+dev_wdc.c  Standard "wdc" IDE controller
+dev_z8530.c  Zilog Z8530 "zs" serial controller
+dev_zero.c  A simple device which returns zero for reads, discards all writes
+device.c  Device registry framework
+lk201.c  LK201 keyboard and mouse, used by the dc7085 and scc controllers
diff -Nru gxemul-0.6.2/src/devices/lk201.c gxemul-0.7.0+dfsg/src/devices/lk201.c
--- gxemul-0.6.2/src/devices/lk201.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/lk201.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,411 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: LK201 keyboard and mouse, used by the dc7085 and scc controllers
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "console.h"
+#include "devices.h"
+#include "machine.h"
+#include "misc.h"
+
+#include "thirdparty/dc7085.h"	/*  for port names  */
+#include "thirdparty/lk201.h"
+
+
+// #define debug fatal
+
+
+/*
+ *  lk201_convert_ascii_to_keybcode():
+ *
+ *  Converts ascii console input to LK201 keyboard scan codes, and adds
+ *  those scancodes using the add_to_rx_queue() function.
+ */
+void lk201_convert_ascii_to_keybcode(struct lk201_data *d, unsigned char ch)
+{
+	int i, found=-1, shifted = 0, controlled = 0;
+
+	if (d->keyb_buf_pos > 0 && d->keyb_buf_pos < (int)sizeof(d->keyb_buf)) {
+		/*  Escape sequence:  */
+		d->keyb_buf[d->keyb_buf_pos] = ch;
+		d->keyb_buf_pos ++;
+
+		if (d->keyb_buf_pos == 2) {
+			if (ch == '[')
+				return;
+			d->keyb_buf_pos = 0;
+			/*  not esc+[, output as normal key  */
+		} else {
+			/*  Inside an esc+[ sequence  */
+
+			switch (ch) {
+			case 'A':  found = 0xaa;  /*  Up     */  break;
+			case 'B':  found = 0xa9;  /*  Down   */  break;
+			case 'C':  found = 0xa8;  /*  Right  */  break;
+			case 'D':  found = 0xa7;  /*  Left   */  break;
+			/*  TODO: pageup, pagedown, ...  */
+			default:
+				;
+			}
+
+			d->keyb_buf_pos = 0;
+		}
+	} else
+		d->keyb_buf_pos = 0;
+
+	if (found == -1) {
+		switch (ch) {
+		case '\b':
+			found = 0xbc;
+			break;
+		case '\n':
+		case '\r':
+			found = 0xbd;
+			break;
+		case '\t':
+			found = 0xbe;
+			break;
+		case 27:	/*  esc  */
+			d->keyb_buf[0] = 27;
+			d->keyb_buf_pos = 1;
+			return;
+		default:
+			if (ch >= 1 && ch <= 26) {
+				ch = 'a' + ch - 1;
+				controlled = 1;
+			}
+
+			shifted = 0;
+			for (i=0; i<256; i++) {
+				/*  Skip numeric digits, so that the normal
+					digits are used instead.  */
+				if (i >= 0x92 && i<=0xa0)
+					continue;
+
+				if (unshiftedAscii[i] == ch) {
+					found = i;
+					break;
+				}
+			}
+
+			if (found == -1) {
+				/*  unshift ch:  */
+				if (ch >= 'A' && ch <= 'Z')
+					ch = ch + ('a' - 'A');
+				for (i=0; i<256; i++)
+					if (shiftedAscii[i] == ch) {
+						found = i;
+						shifted = 1;
+						break;
+					}
+			}
+		}
+	}
+
+	if (!shifted)
+		d->add_to_rx_queue(d->add_data, KEY_UP, DCKBD_PORT);
+	else {
+		d->add_to_rx_queue(d->add_data, KEY_UP, DCKBD_PORT);
+		d->add_to_rx_queue(d->add_data, KEY_SHIFT, DCKBD_PORT);
+	}
+
+	if (controlled)
+		d->add_to_rx_queue(d->add_data, KEY_CONTROL, DCKBD_PORT);
+
+	/*  Send the actual scan code:  */
+	d->add_to_rx_queue(d->add_data, found, DCKBD_PORT);
+
+	/*  Release the key:  */
+	d->add_to_rx_queue(d->add_data, KEY_UP, DCKBD_PORT);
+}
+
+
+/*
+ *  lk201_send_mouse_update_sequence():
+ */
+static int lk201_send_mouse_update_sequence(struct lk201_data *d, int xdelta,
+	int ydelta, int mouse_buttons, int mouse_fb_nr)
+{
+	int xsign, ysign, m;
+
+	/*  If no change, then don't send any update!  */
+	if (xdelta == 0 && ydelta == 0 && d->mouse_buttons == mouse_buttons)
+		return 0;
+
+	m = 50;
+
+	if (xdelta > m)
+		xdelta = m;
+	if (xdelta < -m)
+		xdelta = -m;
+	if (ydelta > m)
+		ydelta = m;
+	if (ydelta < -m)
+		ydelta = -m;
+
+	d->mouse_buttons = mouse_buttons;
+
+	/*
+	 *  TODO: Update d->mouse_framebuffer_nr some way!
+	 */
+
+	xsign = xdelta < 0? 1 : 0;
+	ysign = ydelta < 0? 1 : 0;
+
+	switch (d->mouse_mode) {
+
+	case 0:
+		/*  Do nothing (before the mouse is initialized)  */
+		return 0;
+
+	case MOUSE_INCREMENTAL:
+		if (xdelta < 0)
+			xdelta = -xdelta;
+		if (ydelta < 0)
+			ydelta = -ydelta;
+
+		/*  Reverse sign of x:  (this is needed for some reason)  */
+		xsign ^= 1;
+
+		d->add_to_rx_queue(d->add_data, MOUSE_START_FRAME +
+		    MOUSE_X_SIGN*xsign + MOUSE_Y_SIGN*ysign +
+		    (mouse_buttons & 7), DCMOUSE_PORT);
+		d->add_to_rx_queue(d->add_data, xdelta, DCMOUSE_PORT);
+		d->add_to_rx_queue(d->add_data, ydelta, DCMOUSE_PORT);
+		break;
+
+	default:
+		/*  TODO:  prompt mode and perhaps more stuff  */
+		fatal("[ lk201: mouse mode 0x%02x unknown: TODO ]\n",
+		    d->mouse_mode);
+		exit(1);
+	}
+
+	return 1;
+}
+
+
+/*
+ *  lk201_tick():
+ *
+ *  This function should be called "every now and then".
+ *  If keys are available from the keyboard, add them to the rx queue.
+ *  If other bits are set, an interrupt might need to be caused.
+ */
+void lk201_tick(struct machine *machine, struct lk201_data *d)
+{
+	/*
+	 *  Different machines seem to use different ports for their
+	 *  serial console:
+	 *
+	 *  DEC MIPSMATE 5100 uses the keyboard port.
+	 *  DECstation 3100 (PMAX) and 5000/2000 (3MAX) use the printer port.
+	 *  Others seem to use the comm port.
+	 */
+	int port = DCCOMM_PORT;
+
+	if (machine->machine_type == MACHINE_PMAX) {
+		switch (machine->machine_subtype) {
+		case MACHINE_DEC_MIPSMATE_5100:
+			port = DCKBD_PORT;
+			break;
+		case MACHINE_DEC_PMAX_3100:
+		case MACHINE_DEC_3MAX_5000:
+			port = DCPRINTER_PORT;
+			break;
+		default:
+			port = DCCOMM_PORT;
+		}
+	}
+
+	if (d->use_fb)
+		port = DCKBD_PORT;
+
+	while (d->space_available_in_queue(d->add_data, port) &&
+	    console_charavail(d->console_handle)) {
+		unsigned char ch = console_readchar(d->console_handle);
+		if (d->use_fb)
+			lk201_convert_ascii_to_keybcode(d, ch);
+		else
+			d->add_to_rx_queue(d->add_data, ch, port);
+	}
+
+	/*  Don't do mouse updates if we're running in serial console mode:  */
+	if (!d->use_fb)
+		return;
+
+	int dx, dy, mouse_buttons, mouse_fb_nr;
+	console_getmouse(&dx, &dy, &mouse_buttons, &mouse_fb_nr);
+
+	lk201_send_mouse_update_sequence(d, dx, dy, mouse_buttons, mouse_fb_nr);
+}
+
+
+void lk201_tx_data(struct lk201_data *d, int port, int idata)
+{
+	switch (port) {
+	case DCKBD_PORT:		/*  port 0  */
+		if (!d->use_fb) {
+			/*  Simply print the character to stdout:  */
+			console_putchar(d->console_handle, idata);
+		} else {
+			debug("[ lk201: writing data to KBD: 0x%02x ]\n", idata);
+			switch (idata) {
+			case LK_LED_DISABLE:	/*  0x11  */
+				break;
+			case LK_LED_ENABLE:	/*  0x13  */
+				break;
+			case LK_BELL_ENABLE:	/*  0x23  */
+				break;
+			case 0x41:
+				d->add_to_rx_queue(d->add_data, 0xa, DCKBD_PORT);
+				d->add_to_rx_queue(d->add_data, 0xb, DCKBD_PORT);
+				d->add_to_rx_queue(d->add_data, 0xc, DCKBD_PORT);
+				d->add_to_rx_queue(d->add_data, 0xd, DCKBD_PORT);
+				break;
+			case LED_1:
+			case LED_2:
+				break;
+			case LED_3:
+				break;
+			case LED_4:
+				break;
+			case LK_KBD_ENABLE:	/*  0x8b  */
+				break;
+			case LED_ALL:		/*  0x8f  */
+				break;
+			case LK_RING_BELL:	/*  0xa7  */
+				break;
+			case 0xab:	/*  Get Keyboard ID:  */
+				/*
+				 *  First byte:
+				 *	1 = LK201
+				 *	2 = LK401
+				 *	3 = LK443
+				 *	4 = LK421
+				 *
+				 *  TODO: What about the second byte? 0x22 or
+				 *  0x00?
+				 */
+				d->add_to_rx_queue(d->add_data, 0x01, DCKBD_PORT);
+				d->add_to_rx_queue(d->add_data, 0x00, DCKBD_PORT);
+				break;
+			case LK_DEFAULTS:	/*  0xd3  */
+				/*  TODO?  */
+				break;
+			case 0xfd:	/*  Keyboard self-test:  */
+				/*  Suitable return values according to
+				    Mach/PMAX source code:  */
+				d->add_to_rx_queue(d->add_data,
+				    0x01, DCKBD_PORT);
+				d->add_to_rx_queue(d->add_data,
+				    0x00, DCKBD_PORT);
+				d->add_to_rx_queue(d->add_data,
+				    0x00, DCKBD_PORT);
+				d->add_to_rx_queue(d->add_data,
+				    0x00, DCKBD_PORT);
+				break;
+			default:
+				debug("[ lk201: unimplemented keyboard control: 0x%x ]\n",
+				    idata);
+			}
+		}
+		break;
+	case DCMOUSE_PORT:		/*  port 1  */
+		debug("[ lk201: writing data to MOUSE: 0x%x ", idata);
+		switch (idata) {
+		case MOUSE_INCREMENTAL:
+			d->mouse_mode = MOUSE_INCREMENTAL;
+			break;
+		case MOUSE_SELF_TEST:
+			/*
+			 *  Mouse self-test:
+			 *
+			 *  TODO: Find out if this is correct. The lowest
+			 *        four bits of the second byte should be
+			 *        0x2, according to NetBSD/pmax. But the
+			 *        other bits and bytes?
+			 */
+			debug("(mouse self-test request)");
+			d->add_to_rx_queue(d->add_data,
+			    0xa0 | d->mouse_revision, DCMOUSE_PORT);
+			d->add_to_rx_queue(d->add_data, 0x02, DCMOUSE_PORT);
+			d->add_to_rx_queue(d->add_data, 0x00, DCMOUSE_PORT);
+			d->add_to_rx_queue(d->add_data, 0x00, DCMOUSE_PORT);
+			break;
+		default:
+			debug("UNKNOWN byte; TODO");
+		}
+		debug(" ]\n");
+		break;
+	case DCCOMM_PORT:		/*  port 2  */
+	case DCPRINTER_PORT:		/*  port 3  */
+		/*  Simply print the character to stdout:  */
+		console_putchar(d->console_handle, idata);
+	}
+}
+
+
+/*
+ *  lk201_init():
+ *
+ *  Initialize lk201 keyboard/mouse settings.
+ */
+void lk201_init(struct lk201_data *d, int use_fb,
+	int (*space_available_in_queue)(void *,int),
+	void (*add_to_rx_queue)(void *,int,int),
+	int console_handle, void *add_data)
+{
+	memset(d, 0, sizeof(struct lk201_data));
+
+	d->space_available_in_queue = space_available_in_queue;
+	d->add_to_rx_queue = add_to_rx_queue;
+	d->add_data = add_data;
+
+	d->use_fb = use_fb;
+	d->mouse_mode = 0;
+	d->mouse_revision = 0;	/*  0..15  */
+	d->console_handle = console_handle;
+
+	/*
+	 *  Power up self-test result, as per
+	 *  https://www.netbsd.org/docs/Hardware/Machines/DEC/lk201.html#power_up
+	 */
+	if (d->use_fb) {
+		d->add_to_rx_queue(d->add_data, 0x01, DCKBD_PORT);
+		d->add_to_rx_queue(d->add_data, 0x00, DCKBD_PORT);
+		d->add_to_rx_queue(d->add_data, 0x00, DCKBD_PORT);
+		d->add_to_rx_queue(d->add_data, 0x00, DCKBD_PORT);
+	}
+}
+
+
diff -Nru gxemul-0.6.2/src/devices/lk201.cc gxemul-0.7.0+dfsg/src/devices/lk201.cc
--- gxemul-0.6.2/src/devices/lk201.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/lk201.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,424 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: LK201 keyboard and mouse, used by the dc7085 and scc controllers
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "console.h"
-#include "devices.h"
-#include "machine.h"
-#include "misc.h"
-
-#include "thirdparty/dc7085.h"	/*  for port names  */
-#include "thirdparty/lk201.h"
-
-
-// #define debug fatal
-
-
-/*
- *  lk201_convert_ascii_to_keybcode():
- *
- *  Converts ascii console input to LK201 keyboard scan codes, and adds
- *  those scancodes using the add_to_rx_queue() function.
- */
-void lk201_convert_ascii_to_keybcode(struct lk201_data *d, unsigned char ch)
-{
-	int i, found=-1, shifted = 0, controlled = 0;
-
-	if (d->keyb_buf_pos > 0 && d->keyb_buf_pos < (int)sizeof(d->keyb_buf)) {
-		/*  Escape sequence:  */
-		d->keyb_buf[d->keyb_buf_pos] = ch;
-		d->keyb_buf_pos ++;
-
-		if (d->keyb_buf_pos == 2) {
-			if (ch == '[')
-				return;
-			d->keyb_buf_pos = 0;
-			/*  not esc+[, output as normal key  */
-		} else {
-			/*  Inside an esc+[ sequence  */
-
-			switch (ch) {
-			case 'A':  found = 0xaa;  /*  Up     */  break;
-			case 'B':  found = 0xa9;  /*  Down   */  break;
-			case 'C':  found = 0xa8;  /*  Right  */  break;
-			case 'D':  found = 0xa7;  /*  Left   */  break;
-			/*  TODO: pageup, pagedown, ...  */
-			default:
-				;
-			}
-
-			d->keyb_buf_pos = 0;
-		}
-	} else
-		d->keyb_buf_pos = 0;
-
-	if (found == -1) {
-		switch (ch) {
-		case '\b':
-			found = 0xbc;
-			break;
-		case '\n':
-		case '\r':
-			found = 0xbd;
-			break;
-		case '\t':
-			found = 0xbe;
-			break;
-		case 27:	/*  esc  */
-			d->keyb_buf[0] = 27;
-			d->keyb_buf_pos = 1;
-			return;
-		default:
-			if (ch >= 1 && ch <= 26) {
-				ch = 'a' + ch - 1;
-				controlled = 1;
-			}
-
-			shifted = 0;
-			for (i=0; i<256; i++) {
-				/*  Skip numeric digits, so that the normal
-					digits are used instead.  */
-				if (i >= 0x92 && i<=0xa0)
-					continue;
-
-				if (unshiftedAscii[i] == ch) {
-					found = i;
-					break;
-				}
-			}
-
-			if (found == -1) {
-				/*  unshift ch:  */
-				if (ch >= 'A' && ch <= 'Z')
-					ch = ch + ('a' - 'A');
-				for (i=0; i<256; i++)
-					if (shiftedAscii[i] == ch) {
-						found = i;
-						shifted = 1;
-						break;
-					}
-			}
-		}
-	}
-
-	if (!shifted)
-		d->add_to_rx_queue(d->add_data, KEY_UP, DCKBD_PORT);
-	else {
-		d->add_to_rx_queue(d->add_data, KEY_UP, DCKBD_PORT);
-		d->add_to_rx_queue(d->add_data, KEY_SHIFT, DCKBD_PORT);
-	}
-
-	if (controlled)
-		d->add_to_rx_queue(d->add_data, KEY_CONTROL, DCKBD_PORT);
-
-	/*  Send the actual scan code:  */
-	d->add_to_rx_queue(d->add_data, found, DCKBD_PORT);
-
-	/*  Release the key:  */
-	d->add_to_rx_queue(d->add_data, KEY_UP, DCKBD_PORT);
-}
-
-
-/*
- *  lk201_send_mouse_update_sequence():
- *
- *  mouse_x, _y, _buttons contains the coordinates on the host's display, the
- *  "goal" of where we want to move.
- *
- *  d->mouse_x, _y, _buttons contain the last values transmitted to the
- *  emulated machine.
- */
-static int lk201_send_mouse_update_sequence(struct lk201_data *d, int mouse_x,
-	int mouse_y, int mouse_buttons, int mouse_fb_nr)
-{
-	int xsign, xdelta, ysign, ydelta, m;
-
-	xdelta = mouse_x - d->mouse_x;
-	ydelta = mouse_y - d->mouse_y;
-
-	/*  If no change, then don't send any update!  */
-	if (xdelta == 0 && ydelta == 0 && d->mouse_buttons == mouse_buttons)
-		return 0;
-
-	m = 20;
-
-	if (xdelta > m)
-		xdelta = m;
-	if (xdelta < -m)
-		xdelta = -m;
-	if (ydelta > m)
-		ydelta = m;
-	if (ydelta < -m)
-		ydelta = -m;
-
-	d->mouse_x += xdelta;
-	d->mouse_y += ydelta;
-	d->mouse_buttons = mouse_buttons;
-
-	/*
-	 *  TODO: Update d->mouse_framebuffer_nr some way!
-	 */
-
-	xsign = xdelta < 0? 1 : 0;
-	ysign = ydelta < 0? 1 : 0;
-
-	switch (d->mouse_mode) {
-
-	case 0:
-		/*  Do nothing (before the mouse is initialized)  */
-		return 0;
-
-	case MOUSE_INCREMENTAL:
-		if (xdelta < 0)
-			xdelta = -xdelta;
-		if (ydelta < 0)
-			ydelta = -ydelta;
-
-		/*  Reverse sign of x:  (this is needed for some reason)  */
-		xsign ^= 1;
-
-		d->add_to_rx_queue(d->add_data, MOUSE_START_FRAME +
-		    MOUSE_X_SIGN*xsign + MOUSE_Y_SIGN*ysign +
-		    (mouse_buttons & 7), DCMOUSE_PORT);
-		d->add_to_rx_queue(d->add_data, xdelta, DCMOUSE_PORT);
-		d->add_to_rx_queue(d->add_data, ydelta, DCMOUSE_PORT);
-		break;
-
-	default:
-		/*  TODO:  prompt mode and perhaps more stuff  */
-		fatal("[ lk201: mouse mode 0x%02x unknown: TODO ]\n",
-		    d->mouse_mode);
-		exit(1);
-	}
-
-	return 1;
-}
-
-
-/*
- *  lk201_tick():
- *
- *  This function should be called "every now and then".
- *  If a key is available from the keyboard, add it to the rx queue.
- *  If other bits are set, an interrupt might need to be caused.
- */
-void lk201_tick(struct machine *machine, struct lk201_data *d)
-{
-	int mouse_x, mouse_y, mouse_buttons, mouse_fb_nr;
-
-	if (console_charavail(d->console_handle)) {
-		unsigned char ch = console_readchar(d->console_handle);
-		if (d->use_fb)
-			lk201_convert_ascii_to_keybcode(d, ch);
-		else {
-			/*
-			 *  This is ugly, but necessary because different
-			 *  machines seem to use different ports for their
-			 *  serial console:
-			 *
-			 *  DEC MIPSMATE 5100 uses the keyboard port.
-			 *  DECstation 3100 (PMAX) and 5000/2000 (3MAX) use
-			 *  the printer port.
-			 *  Others seem to use the comm port.
-			 */
-			if (machine->machine_type == MACHINE_PMAX) {
-				switch (machine->machine_subtype) {
-				case MACHINE_DEC_MIPSMATE_5100:
-					d->add_to_rx_queue(d->add_data,
-					    ch, DCKBD_PORT);
-					break;
-				case MACHINE_DEC_PMAX_3100:
-				case MACHINE_DEC_3MAX_5000:
-					d->add_to_rx_queue(d->add_data,
-					    ch, DCPRINTER_PORT);
-					break;
-				default:
-					d->add_to_rx_queue(d->add_data,
-					    ch, DCCOMM_PORT);
-				}
-			} else {
-				d->add_to_rx_queue(d->add_data,
-				    ch, DCCOMM_PORT);
-			}
-		}
-	}
-
-	/*  Don't do mouse updates if we're running in serial console mode:  */
-	if (!d->use_fb)
-		return;
-
-	console_getmouse(&mouse_x, &mouse_y, &mouse_buttons,
-	    &mouse_fb_nr);
-
-	lk201_send_mouse_update_sequence(d, mouse_x, mouse_y,
-	    mouse_buttons, mouse_fb_nr);
-}
-
-
-void lk201_tx_data(struct lk201_data *d, int port, int idata)
-{
-	switch (port) {
-	case DCKBD_PORT:		/*  port 0  */
-		if (!d->use_fb) {
-			/*  Simply print the character to stdout:  */
-			console_putchar(d->console_handle, idata);
-		} else {
-			debug("[ lk201: writing data to KBD: 0x%02x ]\n", idata);
-			switch (idata) {
-			case LK_LED_DISABLE:	/*  0x11  */
-				break;
-			case LK_LED_ENABLE:	/*  0x13  */
-				break;
-			case LK_BELL_ENABLE:	/*  0x23  */
-				break;
-			case 0x41:
-				d->add_to_rx_queue(d->add_data, 0xa, DCKBD_PORT);
-				d->add_to_rx_queue(d->add_data, 0xb, DCKBD_PORT);
-				d->add_to_rx_queue(d->add_data, 0xc, DCKBD_PORT);
-				d->add_to_rx_queue(d->add_data, 0xd, DCKBD_PORT);
-				break;
-			case LED_1:
-			case LED_2:
-				break;
-			case LED_3:
-				break;
-			case LED_4:
-				break;
-			case LK_KBD_ENABLE:	/*  0x8b  */
-				break;
-			case LED_ALL:		/*  0x8f  */
-				break;
-			case LK_RING_BELL:	/*  0xa7  */
-				break;
-			case 0xab:	/*  Get Keyboard ID:  */
-				/*
-				 *  First byte:
-				 *	1 = LK201
-				 *	2 = LK401
-				 *	3 = LK443
-				 *	4 = LK421
-				 *
-				 *  TODO: What about the second byte? 0x22 or
-				 *  0x00?
-				 */
-				d->add_to_rx_queue(d->add_data, 0x01, DCKBD_PORT);
-				d->add_to_rx_queue(d->add_data, 0x00, DCKBD_PORT);
-				break;
-			case LK_DEFAULTS:	/*  0xd3  */
-				/*  TODO?  */
-				break;
-			case 0xfd:	/*  Keyboard self-test:  */
-				/*  Suitable return values according to
-				    Mach/PMAX source code:  */
-				d->add_to_rx_queue(d->add_data,
-				    0x01, DCKBD_PORT);
-				d->add_to_rx_queue(d->add_data,
-				    0x00, DCKBD_PORT);
-				d->add_to_rx_queue(d->add_data,
-				    0x00, DCKBD_PORT);
-				d->add_to_rx_queue(d->add_data,
-				    0x00, DCKBD_PORT);
-				break;
-			default:
-				debug("[ lk201: unimplemented keyboard control: 0x%x ]\n",
-				    idata);
-			}
-		}
-		break;
-	case DCMOUSE_PORT:		/*  port 1  */
-		debug("[ lk201: writing data to MOUSE: 0x%x ", idata);
-		switch (idata) {
-		case MOUSE_INCREMENTAL:
-			d->mouse_mode = MOUSE_INCREMENTAL;
-			break;
-		case MOUSE_SELF_TEST:
-			/*
-			 *  Mouse self-test:
-			 *
-			 *  TODO: Find out if this is correct. The lowest
-			 *        four bits of the second byte should be
-			 *        0x2, according to NetBSD/pmax. But the
-			 *        other bits and bytes?
-			 */
-			debug("(mouse self-test request)");
-			d->add_to_rx_queue(d->add_data,
-			    0xa0 | d->mouse_revision, DCMOUSE_PORT);
-			d->add_to_rx_queue(d->add_data, 0x02, DCMOUSE_PORT);
-			d->add_to_rx_queue(d->add_data, 0x00, DCMOUSE_PORT);
-			d->add_to_rx_queue(d->add_data, 0x00, DCMOUSE_PORT);
-			break;
-		default:
-			debug("UNKNOWN byte; TODO");
-		}
-		debug(" ]\n");
-		break;
-	case DCCOMM_PORT:		/*  port 2  */
-	case DCPRINTER_PORT:		/*  port 3  */
-		/*  Simply print the character to stdout:  */
-		console_putchar(d->console_handle, idata);
-	}
-}
-
-
-/*
- *  lk201_init():
- *
- *  Initialize lk201 keyboard/mouse settings.
- */
-void lk201_init(struct lk201_data *d, int use_fb,
-	void (*add_to_rx_queue)(void *,int,int),
-	int console_handle, void *add_data)
-{
-	memset(d, 0, sizeof(struct lk201_data));
-
-	d->add_to_rx_queue = add_to_rx_queue;
-	d->add_data = add_data;
-
-	d->use_fb = use_fb;
-	d->mouse_mode = 0;
-	d->mouse_revision = 0;	/*  0..15  */
-	d->console_handle = console_handle;
-
-	/*
-	 *  Power up self-test result, as per
-	 *  https://www.netbsd.org/docs/Hardware/Machines/DEC/lk201.html#power_up
-	 */
-	if (d->use_fb) {
-		d->add_to_rx_queue(d->add_data, 0x01, DCKBD_PORT);
-		d->add_to_rx_queue(d->add_data, 0x00, DCKBD_PORT);
-		d->add_to_rx_queue(d->add_data, 0x00, DCKBD_PORT);
-		d->add_to_rx_queue(d->add_data, 0x00, DCKBD_PORT);
-	}
-}
-
-
diff -Nru gxemul-0.6.2/src/devices/makeautodev.sh gxemul-0.7.0+dfsg/src/devices/makeautodev.sh
--- gxemul-0.6.2/src/devices/makeautodev.sh	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/makeautodev.sh	2021-11-27 09:42:23.000000000 +0000
@@ -27,17 +27,17 @@
 #  SUCH DAMAGE.
 
 
-printf "Generating autodev.cc... "
+printf "Generating autodev.c... "
 
-rm -f autodev.cc
+rm -f autodev.c
 
-printf "/*\n *  DO NOT EDIT. AUTOMATICALLY CREATED\n */\n\n" >> autodev.cc
+printf "/*\n *  DO NOT EDIT. AUTOMATICALLY CREATED\n */\n\n" >> autodev.c
 
-cat autodev_head.cc >> autodev.cc
+cat autodev_head.c >> autodev.c
 
 printf "5"
 rm -f .index
-for a in *.cc; do
+for a in *.c; do
 	B=`grep COMMENT $a`
 	if [ z"$B" != z ]; then
 		printf "$a " >> .index
@@ -46,54 +46,54 @@
 done
 
 printf "4"
-for a in dev_*.cc; do
+for a in dev_*.c; do
 	B=`grep DEVINIT $a`
 	if [ z"$B" != z ]; then
 		C=`grep DEVINIT $a | cut -d \( -f 2|cut -d \) -f 1`
 		for B in $C; do
-			printf "int devinit_$B(struct devinit *);\n" >> autodev.cc
+			printf "int devinit_$B(struct devinit *);\n" >> autodev.c
 		done
 	fi
 done
 
 printf "3"
-for a in bus_pci.cc; do
+for a in bus_pci.c; do
 	B=`grep PCIINIT $a`
 	if [ z"$B" != z ]; then
 		C=`grep PCIINIT $a | cut -d \( -f 2|cut -d \) -f 1`
 		for B in $C; do
-			printf "void pciinit_$B(struct machine *, " >> autodev.cc
-			printf "struct memory *, struct pci_device *);\n" >> autodev.cc
+			printf "void pciinit_$B(struct machine *, " >> autodev.c
+			printf "struct memory *, struct pci_device *);\n" >> autodev.c
 		done
 	fi
 done
 
-cat autodev_middle.cc >> autodev.cc
+cat autodev_middle.c >> autodev.c
 
 printf "2"
-for a in dev_*.cc; do
+for a in dev_*.c; do
 	B=`grep DEVINIT $a`
 	if [ z"$B" != z ]; then
 		C=`grep DEVINIT $a | cut -d \( -f 2|cut -d \) -f 1`
 		for B in $C; do
-			printf "\tdevice_register(\""$B"\"," >> autodev.cc
-			printf " devinit_$B);\n" >> autodev.cc
+			printf "\tdevice_register(\""$B"\"," >> autodev.c
+			printf " devinit_$B);\n" >> autodev.c
 		done
 	fi
 done
 
 printf "1"
-for a in bus_pci.cc; do
+for a in bus_pci.c; do
 	B=`grep PCIINIT $a`
 	if [ z"$B" != z ]; then
 		C=`grep PCIINIT $a | cut -d \( -f 2|cut -d \) -f 1`
 		for B in $C; do
-			printf "\tpci_register(\""$B"\"," >> autodev.cc
-			printf " pciinit_$B);\n" >> autodev.cc
+			printf "\tpci_register(\""$B"\"," >> autodev.c
+			printf " pciinit_$B);\n" >> autodev.c
 		done
 	fi
 done
 
-cat autodev_tail.cc >> autodev.cc
+cat autodev_tail.c >> autodev.c
 
 printf " done\n"
diff -Nru gxemul-0.6.2/src/devices/Makefile.skel gxemul-0.7.0+dfsg/src/devices/Makefile.skel
--- gxemul-0.6.2/src/devices/Makefile.skel	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/devices/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #  Makefile for GXemul devices
 #
 
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
+CFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
 
 OBJS=device.o bus_isa.o bus_pci.o lk201.o \
 	dev_8253.o dev_8259.o dev_adb.o dev_ahc.o dev_algor.o dev_asc.o \
@@ -15,7 +15,8 @@
 	dev_footbridge.o dev_gc.o dev_gt.o dev_hammerhead.o dev_i80321.o \
 	dev_igsfb.o dev_iq80321_7seg.o dev_irqc.o dev_jazz.o dev_kn01.o \
 	dev_kn02.o dev_kn02ba.o dev_kn220.o dev_kn230.o dev_lca.o dev_le.o \
-	dev_lpt.o dev_luna88k.o dev_m8820x.o dev_malta_lcd.o dev_mb8696x.o dev_mc146818.o \
+	dev_lpt.o dev_luna88k.o dev_lunafb.o dev_m8820x.o dev_malta_lcd.o \
+	dev_mb8696x.o dev_mb89352.o dev_mc146818.o \
 	dev_mk48txx.o dev_mp.o dev_mvme187.o dev_ns16550.o dev_ohci.o \
 	dev_osiop.o dev_palmbus.o dev_pcc2.o dev_pccmos.o dev_pcic.o dev_pckbc.o \
 	dev_pmagja.o dev_pmppc.o dev_prep.o dev_ps2_ether.o dev_ps2_gif.o \
@@ -32,12 +33,12 @@
 	$(MAKE) objs
 
 fonts_done: fonts_made
-	$(MAKE) font8x8.cc font8x10.cc font8x16.cc
+	$(MAKE) font8x8.c font8x10.c font8x16.c
 
 fonts_made:
 	cd fonts; $(MAKE)
 
-autodev.cc: autodev_head.cc autodev_middle.cc autodev_tail.cc makeautodev.sh bus_pci.cc $(OBJS)
+autodev.c: autodev_head.c autodev_middle.c autodev_tail.c makeautodev.sh bus_pci.c $(OBJS)
 	./makeautodev.sh
 
 objs: $(OBJS)
@@ -45,22 +46,22 @@
 
 $(OBJS): Makefile
 
-dev_vga.o: font8x8.cc font8x16.cc font8x10.cc
+dev_vga.o: font8x8.c font8x16.c font8x10.c
 
-dev_fb.o: fb_include.cc dev_fb.cc
+dev_fb.o: fb_include.c dev_fb.c
 
-font8x8.cc:
-	cp -f fonts/font8x8.cc .
+font8x8.c:
+	cp -f fonts/font8x8.c .
 
-font8x10.cc:
-	cp -f fonts/font8x10.cc .
+font8x10.c:
+	cp -f fonts/font8x10.c .
 
-font8x16.cc:
-	cp -f fonts/font8x16.cc .
+font8x16.c:
+	cp -f fonts/font8x16.c .
 
 
 clean:
-	rm -f $(OBJS) *core font8x16.cc font8x10.cc font8x8.cc
+	rm -f $(OBJS) *core font*x*.c*
 	rm -f autodev.[co]*
 	cd fonts; $(MAKE) clean
 
diff -Nru gxemul-0.6.2/src/disk/bootblock_apple.c gxemul-0.7.0+dfsg/src/disk/bootblock_apple.c
--- gxemul-0.6.2/src/disk/bootblock_apple.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/disk/bootblock_apple.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,104 @@
+/*
+ *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Apple bootblock handling.
+ *
+ *  TODO: This is just a quick hack skeleton. Doesn't really work yet.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "diskimage.h"
+#include "misc.h"
+
+
+/*
+ *  apple_load_bootblock():
+ *
+ *  Try to load a kernel from a disk image with an Apple Partition Table.
+ *
+ *  TODO: This function uses too many magic offsets and so on; it should be
+ *  cleaned up some day. See http://www.awprofessional.com/articles/
+ *	article.asp?p=376123&seqNum=3&rl=1  for some info on the Apple
+ *  partition format.
+ *
+ *  Returns 1 on success, 0 on failure.
+ */
+int apple_load_bootblock(struct machine *m, struct cpu *cpu,
+	int disk_id, int disk_type, int *n_loadp, char ***load_namesp)
+{
+	unsigned char buf[0x8000];
+	int res, partnr, n_partitions = 0, n_hfs_partitions = 0;
+
+	res = diskimage_access(m, disk_id, disk_type, 0, 0x0, buf, sizeof(buf));
+	if (!res) {
+		fatal("apple_load_bootblock: couldn't read the disk "
+		    "image. Aborting.\n");
+		return 0;
+	}
+
+	partnr = 0;
+	do {
+		int start, length;
+		int ofs = 0x200 * (partnr + 1);
+		if (partnr == 0)
+			n_partitions = buf[ofs + 7];
+		start = ((uint64_t)buf[ofs + 8] << 24) + (buf[ofs + 9] << 16) +
+		    (buf[ofs + 10] << 8) + buf[ofs + 11];
+		length = ((uint64_t)buf[ofs+12] << 24) + (buf[ofs + 13] << 16) +
+		    (buf[ofs + 14] << 8) + buf[ofs + 15];
+
+		debug("partition %i: '%s', type '%s', start %i, length %i\n",
+		    partnr, buf + ofs + 0x10, buf + ofs + 0x30,
+		    start, length);
+
+		if (strcmp((char *)buf + ofs + 0x30, "Apple_HFS") == 0) {
+			n_hfs_partitions ++;
+			// uint64_t hfs_start = 512 * start;
+			// uint64_t hfs_length = 512 * length;
+			// TODO.
+		}
+
+		/*  Any more partitions?  */
+		partnr ++;
+	} while (partnr < n_partitions);
+
+	if (n_hfs_partitions == 0) {
+		fatal("Error: No HFS partition found! TODO\n");
+		return 0;
+	}
+	if (n_hfs_partitions >= 2) {
+		fatal("Error: Too many HFS partitions found! TODO\n");
+		return 0;
+	}
+
+	return 0;
+}
+
+
diff -Nru gxemul-0.6.2/src/disk/bootblock_apple.cc gxemul-0.7.0+dfsg/src/disk/bootblock_apple.cc
--- gxemul-0.6.2/src/disk/bootblock_apple.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/disk/bootblock_apple.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,104 +0,0 @@
-/*
- *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Apple bootblock handling.
- *
- *  TODO: This is just a quick hack skeleton. Doesn't really work yet.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "diskimage.h"
-#include "misc.h"
-
-
-/*
- *  apple_load_bootblock():
- *
- *  Try to load a kernel from a disk image with an Apple Partition Table.
- *
- *  TODO: This function uses too many magic offsets and so on; it should be
- *  cleaned up some day. See http://www.awprofessional.com/articles/
- *	article.asp?p=376123&seqNum=3&rl=1  for some info on the Apple
- *  partition format.
- *
- *  Returns 1 on success, 0 on failure.
- */
-int apple_load_bootblock(struct machine *m, struct cpu *cpu,
-	int disk_id, int disk_type, int *n_loadp, char ***load_namesp)
-{
-	unsigned char buf[0x8000];
-	int res, partnr, n_partitions = 0, n_hfs_partitions = 0;
-	uint64_t hfs_start, hfs_length;
-
-	res = diskimage_access(m, disk_id, disk_type, 0, 0x0, buf, sizeof(buf));
-	if (!res) {
-		fatal("apple_load_bootblock: couldn't read the disk "
-		    "image. Aborting.\n");
-		return 0;
-	}
-
-	partnr = 0;
-	do {
-		int start, length;
-		int ofs = 0x200 * (partnr + 1);
-		if (partnr == 0)
-			n_partitions = buf[ofs + 7];
-		start = ((uint64_t)buf[ofs + 8] << 24) + (buf[ofs + 9] << 16) +
-		    (buf[ofs + 10] << 8) + buf[ofs + 11];
-		length = ((uint64_t)buf[ofs+12] << 24) + (buf[ofs + 13] << 16) +
-		    (buf[ofs + 14] << 8) + buf[ofs + 15];
-
-		debug("partition %i: '%s', type '%s', start %i, length %i\n",
-		    partnr, buf + ofs + 0x10, buf + ofs + 0x30,
-		    start, length);
-
-		if (strcmp((char *)buf + ofs + 0x30, "Apple_HFS") == 0) {
-			n_hfs_partitions ++;
-			hfs_start = 512 * start;
-			hfs_length = 512 * length;
-		}
-
-		/*  Any more partitions?  */
-		partnr ++;
-	} while (partnr < n_partitions);
-
-	if (n_hfs_partitions == 0) {
-		fatal("Error: No HFS partition found! TODO\n");
-		return 0;
-	}
-	if (n_hfs_partitions >= 2) {
-		fatal("Error: Too many HFS partitions found! TODO\n");
-		return 0;
-	}
-
-	return 0;
-}
-
-
diff -Nru gxemul-0.6.2/src/disk/bootblock.c gxemul-0.7.0+dfsg/src/disk/bootblock.c
--- gxemul-0.6.2/src/disk/bootblock.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/disk/bootblock.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,544 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Bootblock handling:
+ *
+ *	o)  For some machines (e.g. DECstation or the Dreamcast), it is
+ *	    possible to load a bootblock from a fixed location on disk, and
+ *	    simply execute it in memory.
+ *
+ *	o)  For booting from generic CDROM ISO9660 images, a filename of
+ *	    a file to load must be supplied (the kernel filename). It is
+ *	    loaded, possibly gunzipped, and then executed as if it was a
+ *	    separate file.
+ *
+ *  TODO: This module needs some cleanup.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "diskimage.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "netinet/in.h"
+#include "unistd.h"
+
+#include "thirdparty/bootblock.h"
+
+
+static const char *diskimage_types[] = DISKIMAGE_TYPES;
+
+
+/*
+ *  load_bootblock():
+ *
+ *  For some emulation modes, it is possible to boot from a harddisk image by
+ *  loading a bootblock from a specific disk offset into memory, and executing
+ *  that, instead of requiring a separate kernel file.  It is then up to the
+ *  bootblock to load a kernel.
+ *
+ *  Returns 1 on success, 0 on failure.
+ */
+int load_bootblock(struct machine *m, struct cpu *cpu,
+	int *n_loadp, char ***load_namesp)
+{
+	struct sgi_boot_block sgi_boot_block;
+	int boot_disk_type = 0, n_blocks, res, readofs, iso_type, retval = 0;
+	unsigned char minibuf[0x20];
+	unsigned char *bootblock_buf;
+	uint64_t bootblock_offset, base_offset;
+	uint64_t bootblock_loadaddr, bootblock_pc;
+
+	const char *tmpdir = getenv("TMPDIR");
+	if (tmpdir == NULL)
+		tmpdir = DEFAULT_TMP_DIR;
+
+	int boot_disk_id = diskimage_bootdev(m, &boot_disk_type);
+	if (boot_disk_id < 0)
+		return 0;
+
+	base_offset = diskimage_get_baseoffset(m, boot_disk_id, boot_disk_type);
+
+	switch (m->machine_type) {
+
+	case MACHINE_DREAMCAST:
+		if (!diskimage_is_a_cdrom(cpu->machine, boot_disk_id,
+		    boot_disk_type)) {
+			fatal("The Dreamcast emulation mode can only boot"
+			    " from CD images, not from other disk types.\n");
+			exit(1);
+		}
+
+		CHECK_ALLOCATION(bootblock_buf = (unsigned char *) malloc(32768));
+
+		debug("loading Dreamcast IP.BIN from %s id %i to 0x8c008000\n",
+		    diskimage_types[boot_disk_type], boot_disk_id);
+
+		res = diskimage_access(m, boot_disk_id, boot_disk_type,
+		    0, base_offset, bootblock_buf, 0x8000);
+		if (!res) {
+			fatal("Couldn't read the first 32 KB from the disk image. Aborting.\n");
+			return 0;
+		}
+
+		if (strncmp((char *)bootblock_buf, "SEGA ", 5) != 0) {
+			fatal("This is not a Dreamcast IP.BIN header.\n");
+			free(bootblock_buf);
+			return 0;
+		}
+
+		/*
+		 *  Store IP.BIN at 0x8c008000, and set entry point.
+		 *
+		 *  Note: The boot block contains several executable parts:
+		 *    Offset 0x0300-36ff:  SEGA logo code
+		 *    Offset 0x3800-5FFF:  Bootstrap code 1
+		 *    Offset 0x6000-7FFF:  Bootstrap code 2
+		 *
+		 *  (See http://mc.pp.se/dc/ip.bin.html for details.)
+		 *
+		 *  So one way to boot could be to set initial PC to 0x8c008300,
+		 *  but that would only run the SEGA logo code and then return
+		 *  to... well, to nothing.
+		 *
+		 *  Instead, initial PC is set to 0x8c000140, which triggers
+		 *  software PROM emulation, which in turn:
+		 *    a) calls 0x8c008300 to show the logo, and
+		 *    b) calls 0x8c00b800 to set up registers etc and
+		 *       this code will hopefully jump to 0x8c010000.
+		 *
+		 *  This mimics the behavior of the real Dreamcast.
+		 */
+		store_buf(cpu, 0x8c008000, (char *)bootblock_buf, 32768);
+		cpu->pc = 0x8c000140;	// see src/promemul/dreamcast.cc for details
+
+		/*  Remember the name of the file to boot (1ST_READ.BIN):  */
+		if (cpu->machine->boot_kernel_filename == NULL ||
+		    cpu->machine->boot_kernel_filename[0] == '\0') {
+			int i = 0x60;
+			while (i < 0x70) {
+				if (bootblock_buf[i] == ' ')
+					bootblock_buf[i] = 0;
+				i ++;
+			}
+			CHECK_ALLOCATION(cpu->machine->boot_kernel_filename =
+			    strdup((char *)bootblock_buf + 0x60));
+		}
+
+		debug("Dreamcast boot filename: %s (to be loaded to 0x8c010000)\n",
+		    cpu->machine->boot_kernel_filename);
+
+		free(bootblock_buf);
+
+		break;
+
+	case MACHINE_LUNA88K:
+		{
+			const int disklabel_size = 512;
+			uint8_t disklabel[disklabel_size];
+
+			res = diskimage_access(m, boot_disk_id, boot_disk_type,
+			    0, 0x0, disklabel, disklabel_size);
+			if (!res) {
+				debugmsg(SUBSYS_STARTUP, "bootblock", VERBOSITY_ERROR,
+				    "ERROR: could not load disklabel");
+				return 0;
+			}
+
+			debugmsg(SUBSYS_STARTUP, "bootblock", VERBOSITY_INFO, "LUNA88K disklabel");
+			debug_indentation(1);
+
+			for (int i = 0; i < 8; ++i) {
+				int ofs = 0x1bc + 8 * i;
+				uint32_t offset = (disklabel[ofs] << 24) +
+				    (disklabel[ofs+1] << 16) +
+				    (disklabel[ofs+2] << 8) +
+				    (disklabel[ofs+3]);
+				uint32_t nsectors = (disklabel[ofs+4] << 24) +
+				    (disklabel[ofs+5] << 16) +
+				    (disklabel[ofs+6] << 8) +
+				    (disklabel[ofs+7]);
+				if (nsectors > 0) {
+					debug("%c: %i sectors at offset %i\n",
+					    'a' + i, nsectors, offset);
+				}
+			}
+
+			/*
+			 *  It seems that the real LUNA88K PROM is able to load
+			 *  boot programs from (old-style) UFS partitions, thus
+			 *  it does not really have the concept of "boot
+			 *  blocks" or second stage boot loader as on some
+			 *  other machines.
+			 *
+			 *  Try these in order (typically from partition 'a'):
+			 *	vmunix	(OMRON UniOS?)
+			 *	boot	(OpenBSD/luna88k)
+			 */
+
+			// TODO.
+			debugmsg(SUBSYS_STARTUP, "", VERBOSITY_INFO, "TODO: load boot program");
+
+			debug_indentation(-1);
+		}
+		return 1;
+
+	case MACHINE_PMAX:
+		/*
+		 *  The first few bytes of a disk contains information about
+		 *  where the bootblock(s) are located. (These are all 32-bit
+		 *  little-endian words.)
+		 *
+		 *  Offset 0x10 = load address
+		 *         0x14 = initial PC value
+		 *         0x18 = nr of 512-byte blocks to read
+		 *         0x1c = offset on disk to where the bootblocks
+		 *                are (in 512-byte units)
+		 *         0x20 = nr of blocks to read...
+		 *         0x24 = offset...
+		 *
+		 *  nr of blocks to read and offset are repeated until nr of
+		 *  blocks to read is zero.
+		 *
+		 *  TODO: Make use of src/include/thirdparty/bootblock.h now
+		 *  that it is in the tree, rather than using hardcoded numbers.
+		 */
+		res = diskimage_access(m, boot_disk_id, boot_disk_type, 0, 0,
+		    minibuf, sizeof(minibuf));
+
+		bootblock_loadaddr = minibuf[0x10] + (minibuf[0x11] << 8)
+		  + (minibuf[0x12] << 16) + ((uint64_t)minibuf[0x13] << 24);
+
+		/*  Convert loadaddr to uncached:  */
+		if ((bootblock_loadaddr & 0xf0000000ULL) != 0x80000000 &&
+		    (bootblock_loadaddr & 0xf0000000ULL) != 0xa0000000) {
+			fatal("\nWARNING! Weird load address 0x%08" PRIx32
+			    " for SCSI id %i.\n\n",
+			    (uint32_t)bootblock_loadaddr, boot_disk_id);
+			if (bootblock_loadaddr == 0) {
+				fatal("I'm assuming that this is _not_ a "
+				    "DEC bootblock.\nAre you sure you are"
+				    " booting from the correct disk?\n");
+				exit(1);
+			}
+		}
+
+		bootblock_loadaddr &= 0x0fffffffULL;
+		bootblock_loadaddr |= 0xffffffffa0000000ULL;
+
+		bootblock_pc = minibuf[0x14] + (minibuf[0x15] << 8)
+		  + (minibuf[0x16] << 16) + ((uint64_t)minibuf[0x17] << 24);
+
+		bootblock_pc &= 0x0fffffffULL;
+		bootblock_pc |= 0xffffffffa0000000ULL;
+		cpu->pc = bootblock_pc;
+
+		debugmsg(SUBSYS_MACHINE, "DEC boot", VERBOSITY_INFO,
+		    "loadaddr=0x%08" PRIx32", pc=0x%08" PRIx32,
+		    (uint32_t) bootblock_loadaddr, (uint32_t) bootblock_pc);
+
+		debug_indentation(1);
+
+		readofs = 0x18;
+
+		for (;;) {
+			res = diskimage_access(m, boot_disk_id, boot_disk_type,
+			    0, readofs, minibuf, sizeof(minibuf));
+			if (!res) {
+				fatal("Couldn't read the disk image. "
+				    "Aborting.\n");
+				return 0;
+			}
+
+			n_blocks = minibuf[0] + (minibuf[1] << 8)
+			  + (minibuf[2] << 16) + ((uint64_t)minibuf[3] << 24);
+
+			bootblock_offset = (minibuf[4] + (minibuf[5] << 8) +
+			  (minibuf[6]<<16) + ((uint64_t)minibuf[7]<<24)) * 512;
+
+			if (n_blocks < 1)
+				break;
+
+			debug(readofs == 0x18? "%i" : " + %i", n_blocks);
+
+			if (n_blocks * 512 > 65536)
+				fatal("\nWARNING! Unusually large bootblock "
+				    "(%i bytes)\n\n", n_blocks * 512);
+
+			CHECK_ALLOCATION(bootblock_buf = (unsigned char *) malloc(n_blocks*512));
+
+			res = diskimage_access(m, boot_disk_id, boot_disk_type,
+			    0, bootblock_offset, bootblock_buf, n_blocks * 512);
+			if (!res) {
+				fatal("WARNING: could not load bootblocks from"
+				    " disk offset 0x%llx\n",
+				    (long long)bootblock_offset);
+			}
+
+			store_buf(cpu, bootblock_loadaddr,
+			    (char *)bootblock_buf, n_blocks * 512);
+
+			bootblock_loadaddr += 512*n_blocks;
+			free(bootblock_buf);
+			readofs += 8;
+		}
+
+		debug(readofs == 0x18? " no blocks?\n" : " blocks\n");
+		debug_indentation(-1);
+		return 1;
+
+	case MACHINE_SGI:
+		/*
+		 *  The first few bytes of a disk contains an "SGI boot block".
+		 *  The data in the boot block are all big-endian.
+		 *
+		 *  See src/include/thirdparty/bootblock.h (from NetBSD) for
+		 *  details.
+		 */
+
+		res = diskimage_access(m, boot_disk_id, boot_disk_type, 0, 0,
+		    (unsigned char*)&sgi_boot_block, sizeof(sgi_boot_block));
+
+		uint32_t magic = ntohl(sgi_boot_block.magic);
+		if (magic != SGI_BOOT_BLOCK_MAGIC) {
+			fatal("SGI boot block: wrong magic! (Not a SGI bootable disk image?)\n");
+			return 0;
+		}
+
+		uint16_t sgi_root = ntohs(sgi_boot_block.root);
+		uint16_t sgi_swap = ntohs(sgi_boot_block.swap);
+		char sgi_bootfile[sizeof(sgi_boot_block.bootfile) + 1];
+
+		memset(sgi_bootfile, 0, sizeof(sgi_bootfile));
+		{
+			size_t j = 0;
+			for (size_t i = 0; i < sizeof(sgi_boot_block.bootfile); ++i) {
+				char c = sgi_boot_block.bootfile[i];
+				if (c < 32)
+					break;
+				sgi_bootfile[j++] = c;
+			}
+		}
+
+		debug("SGI boot block:\n");
+		debug_indentation(1);
+		debug("root partition: %i\n", sgi_root);
+		debug("swap partition: %i\n", sgi_swap);
+		debug("bootfile: %s\n", sgi_bootfile);
+
+		// TODO: this should be in sync with what's in arcbios.cc,
+		// in one direction or the other. Hardcoded for now...
+		// or sashARCS or sash64? or ip3xboot (for NetBSD)? take from boot arg on command line?
+		// maybe parse arguments:  "sash path()/unix"  <- first arg means OSLoader,
+		// the rest mean argument passed to the OSLoader? When booting from
+		// disk.
+		const char* osloaderA = "sash";
+		const char* osloaderB = "ip3xboot";
+		char* found_osloader = NULL;
+		int32_t found_osloader_block = -1;
+		int32_t found_osloader_bytes = -1;
+
+		debug("voldir:\n");
+		debug_indentation(1);
+		for (size_t vi = 0; vi < SGI_BOOT_BLOCK_MAXVOLDIRS; ++vi) {
+			char voldir_name[sizeof(sgi_boot_block.voldir[0].name) + 1];
+			int32_t voldir_block = ntohl(sgi_boot_block.voldir[vi].block);
+			int32_t voldir_bytes = ntohl(sgi_boot_block.voldir[vi].bytes);
+
+			memset(voldir_name, 0, sizeof(voldir_name));
+			size_t j = 0;
+			for (size_t i = 0; i < sizeof(sgi_boot_block.voldir[vi].name); ++i) {
+				char c = sgi_boot_block.voldir[vi].name[i];
+				if (c < 32)
+					break;
+				voldir_name[j++] = c;
+			}
+
+			if (voldir_name[0]) {
+				int found = 0;
+				if (strcmp(voldir_name, osloaderA) == 0 ||
+				    strcmp(voldir_name, osloaderB) == 0) {
+					found = 1;
+					found_osloader_block = voldir_block;
+					found_osloader_bytes = voldir_bytes;
+					found_osloader = strdup(voldir_name);
+				}
+
+				const char* found_suffix = found? " [FOUND OSLoader]" : "";
+				debug("name: %s (%i bytes, block %i)%s\n",
+					voldir_name, voldir_bytes, voldir_block, found_suffix);
+			}
+		}
+		if (found_osloader_block < 1 || found_osloader_bytes < 512) {
+			fatal("OSLoader \"%s\" (or \"%s\") NOT found in SGI voldir\n", osloaderA, osloaderB);
+			return 0;
+		}
+		if (found_osloader_bytes & 511) {
+			found_osloader_bytes |= 511;
+			found_osloader_bytes++;
+		}
+		debug_indentation(-1);
+
+		debug("partitions:\n");
+		debug_indentation(1);
+		for (size_t pi = 0; pi < SGI_BOOT_BLOCK_MAXPARTITIONS; ++pi) {
+			int32_t partitions_blocks = ntohl(sgi_boot_block.partitions[pi].blocks);
+			int32_t partitions_first = ntohl(sgi_boot_block.partitions[pi].first);
+			int32_t partitions_type = ntohl(sgi_boot_block.partitions[pi].type);
+
+			if (partitions_blocks != 0)
+				debug("partition %i: %i blocks at %i (type %i)\n",
+					pi, partitions_blocks, partitions_first, partitions_type);
+		}
+		debug_indentation(-1);
+
+		// Read OSLoader binary into emulated RAM. (Typically "sash.")
+		uint64_t diskoffset = found_osloader_block * 512;
+		debug("Loading voldir entry \"%s\", 0x%x bytes from disk offset 0x%x\n",
+			found_osloader, found_osloader_bytes, diskoffset);
+
+		CHECK_ALLOCATION(bootblock_buf = (unsigned char *) malloc(found_osloader_bytes));
+
+		res = diskimage_access(m, boot_disk_id, boot_disk_type,
+		    0, diskoffset, bootblock_buf, found_osloader_bytes);
+		if (!res) {
+			fatal("WARNING: could not load \"%s\" from disk offset 0x%llx\n",
+			    found_osloader, (long long)diskoffset);
+		}
+
+		// Put loaded binary into a temp file, and make sure it is
+		// loaded later by the regular file loader.
+		char* tmpfname;
+		CHECK_ALLOCATION(tmpfname = (char *) malloc(300));
+		snprintf(tmpfname, 300, "%s/gxemul.XXXXXXXXXXXX", tmpdir);
+		int tmpfile_handle = mkstemp(tmpfname);
+		if (tmpfile_handle < 0) {
+			fatal("could not create %s\n", tmpfname);
+			exit(1);
+		}
+
+		if (write(tmpfile_handle, bootblock_buf, found_osloader_bytes) != found_osloader_bytes) {
+			fatal("could not write to %s\n", tmpfname);
+			perror("write");
+			exit(1);
+		}
+
+		close(tmpfile_handle);
+		free(bootblock_buf);
+
+		debug("extracted %i bytes into %s\n", found_osloader_bytes, tmpfname);
+
+		/*  Add the temporary filename to the load_namesp array:  */
+		(*n_loadp)++;
+		char **new_array;
+		CHECK_ALLOCATION(new_array = (char **) malloc(sizeof(char *) * (*n_loadp)));
+		memcpy(new_array, *load_namesp, sizeof(char *) * (*n_loadp));
+		*load_namesp = new_array;
+
+		/*  This adds a Backspace char in front of the filename; this
+		    is a special hack which causes the file to be removed once
+		    it has been loaded.  */
+		CHECK_ALLOCATION(tmpfname = (char *) realloc(tmpfname, strlen(tmpfname) + 2));
+		memmove(tmpfname + 1, tmpfname, strlen(tmpfname) + 1);
+		tmpfname[0] = 8;
+
+		(*load_namesp)[*n_loadp - 1] = strdup(tmpfname);
+
+		free(tmpfname);
+
+		debug_indentation(-1);
+		return 1;
+	}
+
+
+	/*
+	 *  Try reading a kernel manually from the disk. The code here
+	 *  does not rely on machine-dependent boot blocks etc.
+	 */
+	/*  ISO9660: (0x800 bytes at 0x8000 + base_offset)  */
+	CHECK_ALLOCATION(bootblock_buf = (unsigned char *) malloc(0x800));
+	res = diskimage_access(m, boot_disk_id, boot_disk_type,
+	    0, base_offset + 0x8000, bootblock_buf, 0x800);
+	if (!res) {
+		fatal("Couldn't read the ISO header from the disk image. Aborting.\n");
+		return 0;
+	}
+
+	iso_type = 0;
+	if (strncmp((char *)bootblock_buf+1, "CD001", 5) == 0)
+		iso_type = 1;
+	if (strncmp((char *)bootblock_buf+1, "CDW01", 5) == 0)
+		iso_type = 2;
+	if (strncmp((char *)bootblock_buf+1, "CDROM", 5) == 0)
+		iso_type = 3;
+
+	if (iso_type != 0) {
+		/*
+		 *  If the user specified a kernel name, then load it from
+		 *  disk.
+		 */
+		if (cpu->machine->boot_kernel_filename == NULL ||
+		    cpu->machine->boot_kernel_filename[0] == '\0')
+			fatal("\nISO9660 filesystem, but no kernel "
+			    "specified? (Use the -j option.)\n");
+		else
+			retval = iso_load_bootblock(m, cpu, boot_disk_id,
+			    boot_disk_type, iso_type, bootblock_buf,
+			    n_loadp, load_namesp);
+	}
+
+	if (retval != 0)
+		goto ret_ok;
+
+	/*  Apple parition table:  */
+	res = diskimage_access(m, boot_disk_id, boot_disk_type,
+	    0, 0x0, bootblock_buf, 0x800);
+	if (!res) {
+		fatal("Couldn't read the disk image. Aborting.\n");
+		return 0;
+	}
+	if (bootblock_buf[0x000] == 'E' && bootblock_buf[0x001] == 'R' &&
+	    bootblock_buf[0x200] == 'P' && bootblock_buf[0x201] == 'M') {
+		if (cpu->machine->boot_kernel_filename == NULL ||
+		    cpu->machine->boot_kernel_filename[0] == '\0')
+			fatal("\nApple partition table, but no kernel "
+			    "specified? (Use the -j option.)\n");
+		else
+			retval = apple_load_bootblock(m, cpu, boot_disk_id,
+			    boot_disk_type, n_loadp, load_namesp);
+	}
+
+ret_ok:
+	free(bootblock_buf);
+	return retval;
+}
+
+
diff -Nru gxemul-0.6.2/src/disk/bootblock.cc gxemul-0.7.0+dfsg/src/disk/bootblock.cc
--- gxemul-0.6.2/src/disk/bootblock.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/disk/bootblock.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,315 +0,0 @@
-/*
- *  Copyright (C) 2003-2011  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Bootblock handling:
- *
- *	o)  For some machines (e.g. DECstation or the Dreamcast), it is
- *	    possible to load a bootblock from a fixed location on disk, and
- *	    simply execute it in memory.
- *
- *	o)  For booting from generic CDROM ISO9660 images, a filename of
- *	    a file to load must be supplied (the kernel filename). It is
- *	    loaded, possibly gunzipped, and then executed as if it was a
- *	    separate file.
- *
- *  TODO: This module needs some cleanup.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "diskimage.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-
-static const char *diskimage_types[] = DISKIMAGE_TYPES;
-
-
-/*
- *  load_bootblock():
- *
- *  For some emulation modes, it is possible to boot from a harddisk image by
- *  loading a bootblock from a specific disk offset into memory, and executing
- *  that, instead of requiring a separate kernel file.  It is then up to the
- *  bootblock to load a kernel.
- *
- *  Returns 1 on success, 0 on failure.
- */
-int load_bootblock(struct machine *m, struct cpu *cpu,
-	int *n_loadp, char ***load_namesp)
-{
-	int boot_disk_id, boot_disk_type = 0, n_blocks, res, readofs,
-	    iso_type, retval = 0;
-	unsigned char minibuf[0x20];
-	unsigned char *bootblock_buf;
-	uint64_t bootblock_offset, base_offset;
-	uint64_t bootblock_loadaddr, bootblock_pc;
-
-	boot_disk_id = diskimage_bootdev(m, &boot_disk_type);
-	if (boot_disk_id < 0)
-		return 0;
-
-	base_offset = diskimage_get_baseoffset(m, boot_disk_id, boot_disk_type);
-
-	switch (m->machine_type) {
-
-	case MACHINE_DREAMCAST:
-		if (!diskimage_is_a_cdrom(cpu->machine, boot_disk_id,
-		    boot_disk_type)) {
-			fatal("The Dreamcast emulation mode can only boot"
-			    " from CD images, not from other disk types.\n");
-			exit(1);
-		}
-
-		CHECK_ALLOCATION(bootblock_buf = (unsigned char *) malloc(32768));
-
-		debug("loading Dreamcast IP.BIN from %s id %i to 0x8c008000\n",
-		    diskimage_types[boot_disk_type], boot_disk_id);
-
-		res = diskimage_access(m, boot_disk_id, boot_disk_type,
-		    0, base_offset, bootblock_buf, 0x8000);
-		if (!res) {
-			fatal("Couldn't read the first 32 KB from the disk image. Aborting.\n");
-			return 0;
-		}
-
-		if (strncmp((char *)bootblock_buf, "SEGA ", 5) != 0) {
-			fatal("This is not a Dreamcast IP.BIN header.\n");
-			free(bootblock_buf);
-			return 0;
-		}
-
-		/*
-		 *  Store IP.BIN at 0x8c008000, and set entry point.
-		 *
-		 *  Note: The boot block contains several executable parts:
-		 *    Offset 0x0300-36ff:  SEGA logo code
-		 *    Offset 0x3800-5FFF:  Bootstrap code 1
-		 *    Offset 0x6000-7FFF:  Bootstrap code 2
-		 *
-		 *  (See http://mc.pp.se/dc/ip.bin.html for details.)
-		 *
-		 *  So one way to boot could be to set initial PC to 0x8c008300,
-		 *  but that would only run the SEGA logo code and then return
-		 *  to... well, to nothing.
-		 *
-		 *  Instead, initial PC is set to 0x8c000140, which triggers
-		 *  software PROM emulation, which in turn:
-		 *    a) calls 0x8c008300 to show the logo, and
-		 *    b) calls 0x8c00b800 to set up registers etc and
-		 *       this code will hopefully jump to 0x8c010000.
-		 *
-		 *  This mimics the behavior of the real Dreamcast.
-		 */
-		store_buf(cpu, 0x8c008000, (char *)bootblock_buf, 32768);
-		cpu->pc = 0x8c000140;	// see src/promemul/dreamcast.cc for details
-
-		/*  Remember the name of the file to boot (1ST_READ.BIN):  */
-		if (cpu->machine->boot_kernel_filename == NULL ||
-		    cpu->machine->boot_kernel_filename[0] == '\0') {
-			int i = 0x60;
-			while (i < 0x70) {
-				if (bootblock_buf[i] == ' ')
-					bootblock_buf[i] = 0;
-				i ++;
-			}
-			CHECK_ALLOCATION(cpu->machine->boot_kernel_filename =
-			    strdup((char *)bootblock_buf + 0x60));
-		}
-
-		debug("Dreamcast boot filename: %s (to be loaded to 0x8c010000)\n",
-		    cpu->machine->boot_kernel_filename);
-
-		free(bootblock_buf);
-
-		break;
-
-	case MACHINE_PMAX:
-		/*
-		 *  The first few bytes of a disk contains information about
-		 *  where the bootblock(s) are located. (These are all 32-bit
-		 *  little-endian words.)
-		 *
-		 *  Offset 0x10 = load address
-		 *         0x14 = initial PC value
-		 *         0x18 = nr of 512-byte blocks to read
-		 *         0x1c = offset on disk to where the bootblocks
-		 *                are (in 512-byte units)
-		 *         0x20 = nr of blocks to read...
-		 *         0x24 = offset...
-		 *
-		 *  nr of blocks to read and offset are repeated until nr of
-		 *  blocks to read is zero.
-		 */
-		res = diskimage_access(m, boot_disk_id, boot_disk_type, 0, 0,
-		    minibuf, sizeof(minibuf));
-
-		bootblock_loadaddr = minibuf[0x10] + (minibuf[0x11] << 8)
-		  + (minibuf[0x12] << 16) + ((uint64_t)minibuf[0x13] << 24);
-
-		/*  Convert loadaddr to uncached:  */
-		if ((bootblock_loadaddr & 0xf0000000ULL) != 0x80000000 &&
-		    (bootblock_loadaddr & 0xf0000000ULL) != 0xa0000000) {
-			fatal("\nWARNING! Weird load address 0x%08" PRIx32
-			    " for SCSI id %i.\n\n",
-			    (uint32_t)bootblock_loadaddr, boot_disk_id);
-			if (bootblock_loadaddr == 0) {
-				fatal("I'm assuming that this is _not_ a "
-				    "DEC bootblock.\nAre you sure you are"
-				    " booting from the correct disk?\n");
-				exit(1);
-			}
-		}
-
-		bootblock_loadaddr &= 0x0fffffffULL;
-		bootblock_loadaddr |= 0xffffffffa0000000ULL;
-
-		bootblock_pc = minibuf[0x14] + (minibuf[0x15] << 8)
-		  + (minibuf[0x16] << 16) + ((uint64_t)minibuf[0x17] << 24);
-
-		bootblock_pc &= 0x0fffffffULL;
-		bootblock_pc |= 0xffffffffa0000000ULL;
-		cpu->pc = bootblock_pc;
-
-		debug("DEC boot: loadaddr=0x%08" PRIx32", pc=0x%08" PRIx32,
-		    (uint32_t) bootblock_loadaddr, (uint32_t) bootblock_pc);
-
-		readofs = 0x18;
-
-		for (;;) {
-			res = diskimage_access(m, boot_disk_id, boot_disk_type,
-			    0, readofs, minibuf, sizeof(minibuf));
-			if (!res) {
-				fatal("Couldn't read the disk image. "
-				    "Aborting.\n");
-				return 0;
-			}
-
-			n_blocks = minibuf[0] + (minibuf[1] << 8)
-			  + (minibuf[2] << 16) + ((uint64_t)minibuf[3] << 24);
-
-			bootblock_offset = (minibuf[4] + (minibuf[5] << 8) +
-			  (minibuf[6]<<16) + ((uint64_t)minibuf[7]<<24)) * 512;
-
-			if (n_blocks < 1)
-				break;
-
-			debug(readofs == 0x18? ": %i" : " + %i", n_blocks);
-
-			if (n_blocks * 512 > 65536)
-				fatal("\nWARNING! Unusually large bootblock "
-				    "(%i bytes)\n\n", n_blocks * 512);
-
-			CHECK_ALLOCATION(bootblock_buf = (unsigned char *) malloc(n_blocks*512));
-
-			res = diskimage_access(m, boot_disk_id, boot_disk_type,
-			    0, bootblock_offset, bootblock_buf, n_blocks * 512);
-			if (!res) {
-				fatal("WARNING: could not load bootblocks from"
-				    " disk offset 0x%llx\n",
-				    (long long)bootblock_offset);
-			}
-
-			store_buf(cpu, bootblock_loadaddr,
-			    (char *)bootblock_buf, n_blocks * 512);
-
-			bootblock_loadaddr += 512*n_blocks;
-			free(bootblock_buf);
-			readofs += 8;
-		}
-
-		debug(readofs == 0x18? ": no blocks?\n" : " blocks\n");
-		return 1;
-	}
-
-
-	/*
-	 *  Try reading a kernel manually from the disk. The code here
-	 *  does not rely on machine-dependent boot blocks etc.
-	 */
-	/*  ISO9660: (0x800 bytes at 0x8000 + base_offset)  */
-	CHECK_ALLOCATION(bootblock_buf = (unsigned char *) malloc(0x800));
-	res = diskimage_access(m, boot_disk_id, boot_disk_type,
-	    0, base_offset + 0x8000, bootblock_buf, 0x800);
-	if (!res) {
-		fatal("Couldn't read the ISO header from the disk image. Aborting.\n");
-		return 0;
-	}
-
-	iso_type = 0;
-	if (strncmp((char *)bootblock_buf+1, "CD001", 5) == 0)
-		iso_type = 1;
-	if (strncmp((char *)bootblock_buf+1, "CDW01", 5) == 0)
-		iso_type = 2;
-	if (strncmp((char *)bootblock_buf+1, "CDROM", 5) == 0)
-		iso_type = 3;
-
-	if (iso_type != 0) {
-		/*
-		 *  If the user specified a kernel name, then load it from
-		 *  disk.
-		 */
-		if (cpu->machine->boot_kernel_filename == NULL ||
-		    cpu->machine->boot_kernel_filename[0] == '\0')
-			fatal("\nISO9660 filesystem, but no kernel "
-			    "specified? (Use the -j option.)\n");
-		else
-			retval = iso_load_bootblock(m, cpu, boot_disk_id,
-			    boot_disk_type, iso_type, bootblock_buf,
-			    n_loadp, load_namesp);
-	}
-
-	if (retval != 0)
-		goto ret_ok;
-
-	/*  Apple parition table:  */
-	res = diskimage_access(m, boot_disk_id, boot_disk_type,
-	    0, 0x0, bootblock_buf, 0x800);
-	if (!res) {
-		fatal("Couldn't read the disk image. Aborting.\n");
-		return 0;
-	}
-	if (bootblock_buf[0x000] == 'E' && bootblock_buf[0x001] == 'R' &&
-	    bootblock_buf[0x200] == 'P' && bootblock_buf[0x201] == 'M') {
-		if (cpu->machine->boot_kernel_filename == NULL ||
-		    cpu->machine->boot_kernel_filename[0] == '\0')
-			fatal("\nApple partition table, but no kernel "
-			    "specified? (Use the -j option.)\n");
-		else
-			retval = apple_load_bootblock(m, cpu, boot_disk_id,
-			    boot_disk_type, n_loadp, load_namesp);
-	}
-
-ret_ok:
-	free(bootblock_buf);
-	return retval;
-}
-
-
diff -Nru gxemul-0.6.2/src/disk/bootblock_iso9660.c gxemul-0.7.0+dfsg/src/disk/bootblock_iso9660.c
--- gxemul-0.6.2/src/disk/bootblock_iso9660.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/disk/bootblock_iso9660.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,419 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  ISO9660 CD-ROM "bootblock" handling.
+ *
+ *  Despite the name, there is actually no bootblock; instead, the file which
+ *  is to be booted is extracted into a temporary file, and started as if it
+ *  was given as a normal file argument on the command line.
+ *
+ *  TODO: This is really ugly. It's a quick hack. All the magic constants
+ *        need to be replaced with real code!
+ *
+ *        Instead of the current "could not find" message, it should really
+ *        be more helpful, and print out the files found in the current
+ *        directory, so that one can more easily choose the correct file.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "cpu.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "misc.h"
+
+
+/*  #define ISO_DEBUG  */
+
+
+static void debug_print_volume_id_and_filename(int iso_type,
+	unsigned char *buf, char *filename)
+{
+	/*  Volume ID:  */
+	char str[35];
+	int i, ofs = iso_type == 3? 48 : 40;
+
+	memcpy(str, buf + ofs, sizeof(str));
+	str[32] = '\0';  i = 31;
+
+	while (i >= 0 && str[i]==' ')
+		str[i--] = '\0';
+	if (str[0])
+		debug("\"%s\"", str);
+	else {
+		/*  System ID:  */
+		ofs = iso_type == 3? 16 : 8;
+		memcpy(str, buf + ofs, sizeof(str));
+		str[32] = '\0';  i = 31;
+		while (i >= 0 && str[i]==' ')
+			str[i--] = '\0';
+		if (str[0])
+			debug("\"%s\"", str);
+		else
+			debug("(no ID)");
+	}
+
+	debug(":%s\n", filename);
+}
+
+
+/*
+ *  iso_load_bootblock():
+ *
+ *  Try to load a kernel from an ISO 9660 disk image. iso_type is 1 for
+ *  "CD001" (standard), 2 for "CDW01" (ECMA), and 3 for "CDROM" (Sierra).
+ *
+ *  TODO: This function uses too many magic offsets and so on; it should be
+ *  cleaned up some day.
+ *
+ *  Returns 1 on success, 0 on failure.
+ */
+int iso_load_bootblock(struct machine *m, struct cpu *cpu,
+	int disk_id, int disk_type, int iso_type, unsigned char *buf,
+	int *n_loadp, char ***load_namesp)
+{
+	int filenr, dirlen, res = 0, res2, found_dir;
+	uint64_t dirofs, fileofs;
+	ssize_t filelen;
+	unsigned char *dirbuf = NULL, *dp, *match_entry = NULL, *filebuf = NULL;
+	char *p, *filename_orig, *filename, *tmpfname = NULL;
+	char **new_array;
+	const char *tmpdir = getenv("TMPDIR");
+	int tmpfile_handle;
+
+	if (tmpdir == NULL)
+		tmpdir = DEFAULT_TMP_DIR;
+
+	CHECK_ALLOCATION(filename = strdup(cpu->machine->boot_kernel_filename));
+	filename_orig = filename;
+
+	debug("ISO9660 boot:\n");
+	debug_indentation(1);
+
+	debug_print_volume_id_and_filename(iso_type, buf, filename);
+
+
+	/*
+	 *  Hack: If there is something like this at offset 0x9000:
+	 *
+	 *  "MKI Wed Nov 29 17:56:55 2000\n"
+	 *  "mkisofs 1.13 -r -l -C 0,11702 /home/LC2000-CDR"
+	 *
+	 *  and the disk offset is zero, then it can PROBABLY be assumed that
+	 *  offset 11702 is better. (This is counted in 2048 byte sectors.)
+	 */
+	{
+		unsigned char tmpbuf[0x800];
+		uint64_t base_offset = diskimage_get_baseoffset(m, disk_id, disk_type);
+		res2 = diskimage_access(m, disk_id, disk_type, 0, base_offset + 0x9000, tmpbuf, 0x800);
+		if (!res2) {
+			fatal("Couldn't read MKI part after the ISO header of the disk image. Aborting.\n");
+			goto ret;
+		}
+
+		int64_t suggestedBaseOffset = 0;
+		tmpbuf[sizeof(tmpbuf)-1] = '\0';
+		char* found = strstr((char*)tmpbuf, "MKI ");
+		if (found != NULL) {
+			found = strstr(found, " -C 0,");
+			if (found != NULL) {
+				suggestedBaseOffset = strtoll(found + 6, NULL, 0);
+			}
+		}
+
+		int64_t currentBaseOffset = diskimage_get_baseoffset(m, disk_id, disk_type);
+		suggestedBaseOffset *= 2048;
+		if (currentBaseOffset == 0 && suggestedBaseOffset != currentBaseOffset) 
+		{
+			debug("NOTE: automagically adjusting to use base offset %lli\n", (long long)suggestedBaseOffset);
+			diskimage_set_baseoffset(m, disk_id, disk_type, suggestedBaseOffset);
+		}
+	}
+	
+
+	/*
+	 *  Traverse the directory structure to find the kernel.
+	 */
+
+	dirlen = buf[0x84] + 256*buf[0x85] + 65536*buf[0x86];
+	if (dirlen != buf[0x8b] + 256*buf[0x8a] + 65536*buf[0x89])
+		fatal("WARNING: Root directory length mismatch?\n");
+
+	dirofs = (int64_t)(buf[0x8c] + (buf[0x8d] << 8) + (buf[0x8e] << 16) +
+	    ((uint64_t)buf[0x8f] << 24)) * 2048;
+
+#ifdef ISO_DEBUG
+	debug("root = %i bytes at 0x%llx\n", dirlen, (long long)dirofs);
+#endif
+
+	CHECK_ALLOCATION(dirbuf = (unsigned char *) malloc(dirlen));
+	res2 = diskimage_access(m, disk_id, disk_type, 0, dirofs, dirbuf,
+	    dirlen);
+	if (!res2) {
+		fatal("Couldn't read the disk image. Aborting.\n");
+		goto ret;
+	}
+
+	found_dir = 1;	/*  Assume root dir  */
+	dp = dirbuf; filenr = 1;
+	p = NULL;
+	while (dp < dirbuf + dirlen) {
+		size_t i, nlen = dp[0];
+		int x = dp[2] + (dp[3] << 8) + (dp[4] << 16) +
+		    ((uint64_t)dp[5] << 24);
+		int y = dp[6] + (dp[7] << 8);
+		char direntry[65];
+
+		dp += 8;
+
+		/*
+		 *  As long as there is an \ or / in the filename, then we
+		 *  have not yet found the directory.
+		 */
+		p = strchr(filename, '/');
+		if (p == NULL)
+			p = strchr(filename, '\\');
+
+#ifdef ISO_DEBUG
+		debug("%i%s: %i, %i, \"", filenr, filenr == found_dir?
+		    " [CURRENT]" : "", x, y);
+#endif
+		for (i=0; i<nlen && i<sizeof(direntry)-1; i++)
+			if (dp[i]) {
+				direntry[i] = dp[i];
+#ifdef ISO_DEBUG
+				debug("%c", dp[i]);
+#endif
+			} else
+				break;
+#ifdef ISO_DEBUG
+		debug("\"\n");
+#endif
+		direntry[i] = '\0';
+
+		/*  A directory name match?  */
+		if ((p != NULL && strncasecmp(filename, direntry, nlen) == 0
+		    && nlen == (size_t)p - (size_t)filename && found_dir == y)
+		    || (p == NULL && direntry[0] == '\0') ) {
+			found_dir = filenr;
+			if (p != NULL)
+				filename = p+1;
+			dirofs = 2048 * (int64_t)x;
+		}
+
+		dp += nlen;
+
+		/*  16-bit aligned length:  */
+		if (nlen & 1)
+			dp ++;
+
+		filenr ++;
+	}
+
+	p = strchr(filename, '/');
+	if (p == NULL)
+		p = strchr(filename, '\\');
+
+	if (p != NULL) {
+		char *blah = filename_orig;
+
+		fatal("could not find '%s' (1) in /", filename);
+
+		/*  Print the first part of the filename:  */
+		while (blah != filename)
+			fatal("%c", *blah++);
+		
+		fatal("\n");
+		goto ret;
+	}
+
+	/*  debug("dirofs = 0x%llx\n", (long long)dirofs);  */
+
+	/*  Free the old dirbuf, and allocate a new one:  */
+	free(dirbuf);
+	CHECK_ALLOCATION(dirbuf = (unsigned char *) malloc(512));
+
+	for (;;) {
+		size_t len, i;
+
+		/*  Too close to another sector? Then realign.  */
+		if ((dirofs & 2047) + 70 > 2047) {
+			dirofs = (dirofs | 2047) + 1;
+			/*  debug("realign dirofs = 0x%llx\n", dirofs);  */
+		}
+
+		// debug("dirofs = %lli\n", (long long)dirofs);
+		res2 = diskimage_access(m, disk_id, disk_type, 0, dirofs,
+		    dirbuf, 256);
+		if (!res2) {
+			fatal("Couldn't read the disk image. Aborting.\n");
+			goto ret;
+		}
+
+		dp = dirbuf;
+		len = dp[0];
+		if (len < 2) {
+			// debug("dir too short\n");
+			break;
+		}
+
+		/*
+		 *  TODO: Actually parse the directory entry!
+		 *
+		 *  Haha, this must be rewritten.
+		 */
+
+#ifdef ISO_DEBUG
+/*  hahahaha  */
+printf("filename = '%s'\n", filename);
+{
+size_t j;
+for (j=32; j<len; j++)
+	printf("%c", dp[j] >= ' ' && dp[j] < 128? dp[j] : '.');
+printf("\n");
+}
+
+// Hahaha. Yes, it's horrible. (Updated 2011-06-09.)
+// Yes it is. (2018-06-18.) :-(
+#endif
+
+		for (i=32; i<len; i++) {
+			if (i < len - strlen(filename))
+				if (strncmp(filename, (char *)dp + i,
+				    strlen(filename)) == 0) {
+					/*  The filename was found somewhere
+					    in the directory entry.  */
+					if (match_entry != NULL) {
+						fatal("TODO: I'm too lazy to"
+						    " implement a correct "
+						    "directory parser right "
+						    "now... (BUG)\n");
+						exit(1);
+					}
+					CHECK_ALLOCATION(match_entry = (unsigned char *)
+					    malloc(512));
+					memcpy(match_entry, dp, 512);
+					break;
+				}
+		}
+
+		if (match_entry != NULL)
+			break;
+
+		dirofs += len;
+	}
+
+	if (match_entry == NULL) {
+		char *blah = filename_orig;
+
+		fatal("could not find '%s' (2) in /", filename);
+
+		/*  Print the first part of the filename:  */
+		while (blah != filename)
+			fatal("%c", *blah++);
+		
+		fatal("\n");
+		goto ret;
+	}
+
+	fileofs = match_entry[2] + (match_entry[3] << 8) +
+	    (match_entry[4] << 16) + ((uint64_t)match_entry[5] << 24);
+	filelen = match_entry[10] + (match_entry[11] << 8) +
+	    (match_entry[12] << 16) + ((uint64_t)match_entry[13] << 24);
+	fileofs *= 2048;
+
+	/*  debug("filelen=%llx fileofs=%llx\n", (long long)filelen,
+	    (long long)fileofs);  */
+
+	CHECK_ALLOCATION(filebuf = (unsigned char *) malloc(filelen));
+
+	CHECK_ALLOCATION(tmpfname = (char *) malloc(300));
+	snprintf(tmpfname, 300, "%s/gxemul.XXXXXXXXXXXX", tmpdir);
+
+	res2 = diskimage_access(m, disk_id, disk_type, 0, fileofs, filebuf,
+	    filelen);
+	if (!res2) {
+		fatal("could not read the file from the disk image!\n");
+		goto ret;
+	}
+
+	tmpfile_handle = mkstemp(tmpfname);
+	if (tmpfile_handle < 0) {
+		fatal("could not create %s\n", tmpfname);
+		goto ret;
+	}
+
+	if (write(tmpfile_handle, filebuf, filelen) != filelen) {
+		fatal("could not write to %s\n", tmpfname);
+		perror("write");
+		goto ret;
+	}
+
+	close(tmpfile_handle);
+
+	debug("extracted %lli bytes into %s\n", (long long)filelen, tmpfname);
+
+	/*  Add the temporary filename to the load_namesp array:  */
+	(*n_loadp)++;
+	CHECK_ALLOCATION(new_array = (char **) malloc(sizeof(char *) * (*n_loadp)));
+	memcpy(new_array, *load_namesp, sizeof(char *) * (*n_loadp));
+	*load_namesp = new_array;
+
+	/*  This adds a Backspace char in front of the filename; this
+	    is a special hack which causes the file to be removed once
+	    it has been loaded.  */
+	CHECK_ALLOCATION(tmpfname = (char *) realloc(tmpfname, strlen(tmpfname) + 2));
+	memmove(tmpfname + 1, tmpfname, strlen(tmpfname) + 1);
+	tmpfname[0] = 8;
+
+	(*load_namesp)[*n_loadp - 1] = strdup(tmpfname);
+
+	res = 1;
+
+ret:
+	if (dirbuf != NULL)
+		free(dirbuf);
+
+	if (filebuf != NULL)
+		free(filebuf);
+
+	if (match_entry != NULL)
+		free(match_entry);
+
+	if (tmpfname != NULL)
+		free(tmpfname);
+
+	free(filename_orig);
+
+	debug_indentation(-1);
+	return res;
+}
+
diff -Nru gxemul-0.6.2/src/disk/bootblock_iso9660.cc gxemul-0.7.0+dfsg/src/disk/bootblock_iso9660.cc
--- gxemul-0.6.2/src/disk/bootblock_iso9660.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/disk/bootblock_iso9660.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,419 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  ISO9660 CD-ROM "bootblock" handling.
- *
- *  Despite the name, there is actually no bootblock; instead, the file which
- *  is to be booted is extracted into a temporary file, and started as if it
- *  was given as a normal file argument on the command line.
- *
- *  TODO: This is really ugly. It's a quick hack. All the magic constants
- *        need to be replaced with real code!
- *
- *        Instead of the current "could not find" message, it should really
- *        be more helpful, and print out the files found in the current
- *        directory, so that one can more easily choose the correct file.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#include "cpu.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "misc.h"
-
-
-/*  #define ISO_DEBUG  */
-
-
-static void debug_print_volume_id_and_filename(int iso_type,
-	unsigned char *buf, char *filename)
-{
-	/*  Volume ID:  */
-	char str[35];
-	int i, ofs = iso_type == 3? 48 : 40;
-
-	memcpy(str, buf + ofs, sizeof(str));
-	str[32] = '\0';  i = 31;
-
-	while (i >= 0 && str[i]==' ')
-		str[i--] = '\0';
-	if (str[0])
-		debug("\"%s\"", str);
-	else {
-		/*  System ID:  */
-		ofs = iso_type == 3? 16 : 8;
-		memcpy(str, buf + ofs, sizeof(str));
-		str[32] = '\0';  i = 31;
-		while (i >= 0 && str[i]==' ')
-			str[i--] = '\0';
-		if (str[0])
-			debug("\"%s\"", str);
-		else
-			debug("(no ID)");
-	}
-
-	debug(":%s\n", filename);
-}
-
-
-/*
- *  iso_load_bootblock():
- *
- *  Try to load a kernel from an ISO 9660 disk image. iso_type is 1 for
- *  "CD001" (standard), 2 for "CDW01" (ECMA), and 3 for "CDROM" (Sierra).
- *
- *  TODO: This function uses too many magic offsets and so on; it should be
- *  cleaned up some day.
- *
- *  Returns 1 on success, 0 on failure.
- */
-int iso_load_bootblock(struct machine *m, struct cpu *cpu,
-	int disk_id, int disk_type, int iso_type, unsigned char *buf,
-	int *n_loadp, char ***load_namesp)
-{
-	int filenr, dirlen, res = 0, res2, iadd = DEBUG_INDENTATION, found_dir;
-	uint64_t dirofs, fileofs;
-	ssize_t filelen;
-	unsigned char *dirbuf = NULL, *dp, *match_entry = NULL, *filebuf = NULL;
-	char *p, *filename_orig, *filename, *tmpfname = NULL;
-	char **new_array;
-	const char *tmpdir = getenv("TMPDIR");
-	int tmpfile_handle;
-
-	if (tmpdir == NULL)
-		tmpdir = DEFAULT_TMP_DIR;
-
-	CHECK_ALLOCATION(filename = strdup(cpu->machine->boot_kernel_filename));
-	filename_orig = filename;
-
-	debug("ISO9660 boot:\n");
-	debug_indentation(iadd);
-
-	debug_print_volume_id_and_filename(iso_type, buf, filename);
-
-
-	/*
-	 *  Hack: If there is something like this at offset 0x9000:
-	 *
-	 *  "MKI Wed Nov 29 17:56:55 2000\n"
-	 *  "mkisofs 1.13 -r -l -C 0,11702 /home/LC2000-CDR"
-	 *
-	 *  and the disk offset is zero, then it can PROBABLY be assumed that
-	 *  offset 11702 is better. (This is counted in 2048 byte sectors.)
-	 */
-	{
-		unsigned char tmpbuf[0x800];
-		uint64_t base_offset = diskimage_get_baseoffset(m, disk_id, disk_type);
-		res2 = diskimage_access(m, disk_id, disk_type, 0, base_offset + 0x9000, tmpbuf, 0x800);
-		if (!res2) {
-			fatal("Couldn't read MKI part after the ISO header of the disk image. Aborting.\n");
-			goto ret;
-		}
-
-		int64_t suggestedBaseOffset = 0;
-		tmpbuf[sizeof(tmpbuf)-1] = '\0';
-		char* found = strstr((char*)tmpbuf, "MKI ");
-		if (found != NULL) {
-			found = strstr(found, " -C 0,");
-			if (found != NULL) {
-				suggestedBaseOffset = strtoll(found + 6, NULL, 0);
-			}
-		}
-
-		int64_t currentBaseOffset = diskimage_get_baseoffset(m, disk_id, disk_type);
-		suggestedBaseOffset *= 2048;
-		if (currentBaseOffset == 0 && suggestedBaseOffset != currentBaseOffset) 
-		{
-			debug("NOTE: automagically adjusting to use base offset %lli\n", (long long)suggestedBaseOffset);
-			diskimage_set_baseoffset(m, disk_id, disk_type, suggestedBaseOffset);
-		}
-	}
-	
-
-	/*
-	 *  Traverse the directory structure to find the kernel.
-	 */
-
-	dirlen = buf[0x84] + 256*buf[0x85] + 65536*buf[0x86];
-	if (dirlen != buf[0x8b] + 256*buf[0x8a] + 65536*buf[0x89])
-		fatal("WARNING: Root directory length mismatch?\n");
-
-	dirofs = (int64_t)(buf[0x8c] + (buf[0x8d] << 8) + (buf[0x8e] << 16) +
-	    ((uint64_t)buf[0x8f] << 24)) * 2048;
-
-#ifdef ISO_DEBUG
-	debug("root = %i bytes at 0x%llx\n", dirlen, (long long)dirofs);
-#endif
-
-	CHECK_ALLOCATION(dirbuf = (unsigned char *) malloc(dirlen));
-	res2 = diskimage_access(m, disk_id, disk_type, 0, dirofs, dirbuf,
-	    dirlen);
-	if (!res2) {
-		fatal("Couldn't read the disk image. Aborting.\n");
-		goto ret;
-	}
-
-	found_dir = 1;	/*  Assume root dir  */
-	dp = dirbuf; filenr = 1;
-	p = NULL;
-	while (dp < dirbuf + dirlen) {
-		size_t i, nlen = dp[0];
-		int x = dp[2] + (dp[3] << 8) + (dp[4] << 16) +
-		    ((uint64_t)dp[5] << 24);
-		int y = dp[6] + (dp[7] << 8);
-		char direntry[65];
-
-		dp += 8;
-
-		/*
-		 *  As long as there is an \ or / in the filename, then we
-		 *  have not yet found the directory.
-		 */
-		p = strchr(filename, '/');
-		if (p == NULL)
-			p = strchr(filename, '\\');
-
-#ifdef ISO_DEBUG
-		debug("%i%s: %i, %i, \"", filenr, filenr == found_dir?
-		    " [CURRENT]" : "", x, y);
-#endif
-		for (i=0; i<nlen && i<sizeof(direntry)-1; i++)
-			if (dp[i]) {
-				direntry[i] = dp[i];
-#ifdef ISO_DEBUG
-				debug("%c", dp[i]);
-#endif
-			} else
-				break;
-#ifdef ISO_DEBUG
-		debug("\"\n");
-#endif
-		direntry[i] = '\0';
-
-		/*  A directory name match?  */
-		if ((p != NULL && strncasecmp(filename, direntry, nlen) == 0
-		    && nlen == (size_t)p - (size_t)filename && found_dir == y)
-		    || (p == NULL && direntry[0] == '\0') ) {
-			found_dir = filenr;
-			if (p != NULL)
-				filename = p+1;
-			dirofs = 2048 * (int64_t)x;
-		}
-
-		dp += nlen;
-
-		/*  16-bit aligned length:  */
-		if (nlen & 1)
-			dp ++;
-
-		filenr ++;
-	}
-
-	p = strchr(filename, '/');
-	if (p == NULL)
-		p = strchr(filename, '\\');
-
-	if (p != NULL) {
-		char *blah = filename_orig;
-
-		fatal("could not find '%s' (1) in /", filename);
-
-		/*  Print the first part of the filename:  */
-		while (blah != filename)
-			fatal("%c", *blah++);
-		
-		fatal("\n");
-		goto ret;
-	}
-
-	/*  debug("dirofs = 0x%llx\n", (long long)dirofs);  */
-
-	/*  Free the old dirbuf, and allocate a new one:  */
-	free(dirbuf);
-	CHECK_ALLOCATION(dirbuf = (unsigned char *) malloc(512));
-
-	for (;;) {
-		size_t len, i;
-
-		/*  Too close to another sector? Then realign.  */
-		if ((dirofs & 2047) + 70 > 2047) {
-			dirofs = (dirofs | 2047) + 1;
-			/*  debug("realign dirofs = 0x%llx\n", dirofs);  */
-		}
-
-		// debug("dirofs = %lli\n", (long long)dirofs);
-		res2 = diskimage_access(m, disk_id, disk_type, 0, dirofs,
-		    dirbuf, 256);
-		if (!res2) {
-			fatal("Couldn't read the disk image. Aborting.\n");
-			goto ret;
-		}
-
-		dp = dirbuf;
-		len = dp[0];
-		if (len < 2) {
-			// debug("dir too short\n");
-			break;
-		}
-
-		/*
-		 *  TODO: Actually parse the directory entry!
-		 *
-		 *  Haha, this must be rewritten.
-		 */
-
-#ifdef ISO_DEBUG
-/*  hahahaha  */
-printf("filename = '%s'\n", filename);
-{
-size_t j;
-for (j=32; j<len; j++)
-	printf("%c", dp[j] >= ' ' && dp[j] < 128? dp[j] : '.');
-printf("\n");
-}
-
-// Hahaha. Yes, it's horrible. (Updated 2011-06-09.)
-// Yes it is. (2018-06-18.) :-(
-#endif
-
-		for (i=32; i<len; i++) {
-			if (i < len - strlen(filename))
-				if (strncmp(filename, (char *)dp + i,
-				    strlen(filename)) == 0) {
-					/*  The filename was found somewhere
-					    in the directory entry.  */
-					if (match_entry != NULL) {
-						fatal("TODO: I'm too lazy to"
-						    " implement a correct "
-						    "directory parser right "
-						    "now... (BUG)\n");
-						exit(1);
-					}
-					CHECK_ALLOCATION(match_entry = (unsigned char *)
-					    malloc(512));
-					memcpy(match_entry, dp, 512);
-					break;
-				}
-		}
-
-		if (match_entry != NULL)
-			break;
-
-		dirofs += len;
-	}
-
-	if (match_entry == NULL) {
-		char *blah = filename_orig;
-
-		fatal("could not find '%s' (2) in /", filename);
-
-		/*  Print the first part of the filename:  */
-		while (blah != filename)
-			fatal("%c", *blah++);
-		
-		fatal("\n");
-		goto ret;
-	}
-
-	fileofs = match_entry[2] + (match_entry[3] << 8) +
-	    (match_entry[4] << 16) + ((uint64_t)match_entry[5] << 24);
-	filelen = match_entry[10] + (match_entry[11] << 8) +
-	    (match_entry[12] << 16) + ((uint64_t)match_entry[13] << 24);
-	fileofs *= 2048;
-
-	/*  debug("filelen=%llx fileofs=%llx\n", (long long)filelen,
-	    (long long)fileofs);  */
-
-	CHECK_ALLOCATION(filebuf = (unsigned char *) malloc(filelen));
-
-	CHECK_ALLOCATION(tmpfname = (char *) malloc(300));
-	snprintf(tmpfname, 300, "%s/gxemul.XXXXXXXXXXXX", tmpdir);
-
-	res2 = diskimage_access(m, disk_id, disk_type, 0, fileofs, filebuf,
-	    filelen);
-	if (!res2) {
-		fatal("could not read the file from the disk image!\n");
-		goto ret;
-	}
-
-	tmpfile_handle = mkstemp(tmpfname);
-	if (tmpfile_handle < 0) {
-		fatal("could not create %s\n", tmpfname);
-		goto ret;
-	}
-
-	if (write(tmpfile_handle, filebuf, filelen) != filelen) {
-		fatal("could not write to %s\n", tmpfname);
-		perror("write");
-		goto ret;
-	}
-
-	close(tmpfile_handle);
-
-	debug("extracted %lli bytes into %s\n", (long long)filelen, tmpfname);
-
-	/*  Add the temporary filename to the load_namesp array:  */
-	(*n_loadp)++;
-	CHECK_ALLOCATION(new_array = (char **) malloc(sizeof(char *) * (*n_loadp)));
-	memcpy(new_array, *load_namesp, sizeof(char *) * (*n_loadp));
-	*load_namesp = new_array;
-
-	/*  This adds a Backspace char in front of the filename; this
-	    is a special hack which causes the file to be removed once
-	    it has been loaded.  */
-	CHECK_ALLOCATION(tmpfname = (char *) realloc(tmpfname, strlen(tmpfname) + 2));
-	memmove(tmpfname + 1, tmpfname, strlen(tmpfname) + 1);
-	tmpfname[0] = 8;
-
-	(*load_namesp)[*n_loadp - 1] = strdup(tmpfname);
-
-	res = 1;
-
-ret:
-	if (dirbuf != NULL)
-		free(dirbuf);
-
-	if (filebuf != NULL)
-		free(filebuf);
-
-	if (match_entry != NULL)
-		free(match_entry);
-
-	if (tmpfname != NULL)
-		free(tmpfname);
-
-	free(filename_orig);
-
-	debug_indentation(-iadd);
-	return res;
-}
-
diff -Nru gxemul-0.6.2/src/disk/diskimage.c gxemul-0.7.0+dfsg/src/disk/diskimage.c
--- gxemul-0.6.2/src/disk/diskimage.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/disk/diskimage.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1299 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Disk image support.
+ *
+ *  TODO:  diskimage_remove()? This would be useful for floppies in PC-style
+ *	   machines, where disks may need to be swapped during boot etc.
+ *
+ *  TODO:  expose do_fsync as a command line option?
+ */
+
+#include <errno.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include "cpu.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "misc.h"
+
+
+int do_fsync = 0;
+
+/*  #define debug fatal  */
+
+static const char *diskimage_types[] = DISKIMAGE_TYPES;
+
+
+/**************************************************************************/
+
+/*
+ *  my_fseek():
+ *
+ *  A helper function, like fseek() but takes off_t.  If the system has
+ *  fseeko, then that is used. Otherwise I try to fake off_t offsets here.
+ *
+ *  The correct position is reached by seeking 2 billion bytes at a time
+ *  (or less).  Note: This method is only used for SEEK_SET, for SEEK_CUR
+ *  and SEEK_END, normal fseek() is used!
+ *
+ *  TODO: It seemed to work on Linux/i386, but not on Solaris/sparc (?).
+ *  Anyway, most modern systems have fseeko(), so it shouldn't be a problem.
+ */
+static int my_fseek(FILE *f, off_t offset, int whence)
+{
+#ifdef HACK_FSEEKO
+	if (whence == SEEK_SET) {
+		int res = 0;
+		off_t curoff = 0;
+		off_t cur_step;
+
+		fseek(f, 0, SEEK_SET);
+		while (curoff < offset) {
+			/*  How far to seek?  */
+			cur_step = offset - curoff;
+			if (cur_step > 2000000000)
+				cur_step = 2000000000;
+			res = fseek(f, cur_step, SEEK_CUR);
+			if (res)
+				return res;
+			curoff += cur_step;
+		}
+		return 0;
+	} else
+		return fseek(f, offset, whence);
+#else
+	return fseeko(f, offset, whence);
+#endif
+}
+
+
+/**************************************************************************/
+
+
+/*
+ *  diskimage_exist():
+ *
+ *  Returns 1 if the specified disk id (for a specific type) exists, 0
+ *  otherwise.
+ */
+int diskimage_exist(struct machine *machine, int id, int type)
+{
+	struct diskimage *d = machine->first_diskimage;
+
+	while (d != NULL) {
+		if (d->type == type && d->id == id)
+			return 1;
+		d = d->next;
+	}
+	return 0;
+}
+
+
+/*
+ *  diskimage_add_overlay():
+ *
+ *  Opens an overlay data file and its corresponding bitmap file, and adds
+ *  the overlay to a disk image.
+ */
+bool diskimage_add_overlay(struct diskimage *d, char *overlay_basename, bool remove_after_open)
+{
+	struct diskimage_overlay overlay;
+	size_t bitmap_name_len = strlen(overlay_basename) + 20;
+	char *bitmap_name;
+
+	CHECK_ALLOCATION(bitmap_name = (char *) malloc(bitmap_name_len));
+	snprintf(bitmap_name, bitmap_name_len, "%s.map", overlay_basename);
+
+	CHECK_ALLOCATION(overlay.overlay_basename = strdup(overlay_basename));
+	overlay.f_data = fopen(overlay_basename, d->writable? "r+" : "r");
+	if (overlay.f_data == NULL) {
+		perror(overlay_basename);
+
+		if (remove_after_open) {
+			unlink(overlay_basename);
+			unlink(bitmap_name);
+		}
+
+		free(bitmap_name);
+		return false;
+	}
+
+	overlay.f_bitmap = fopen(bitmap_name, d->writable? "r+" : "r");
+	if (overlay.f_bitmap == NULL) {
+		perror(bitmap_name);
+		fprintf(stderr, "Please create the map file first.\n");
+		fclose(overlay.f_data);
+
+		if (remove_after_open) {
+			unlink(overlay_basename);
+			unlink(bitmap_name);
+		}
+
+		free(bitmap_name);
+		return false;
+	}
+
+	d->nr_of_overlays ++;
+
+	CHECK_ALLOCATION(d->overlays = (struct diskimage_overlay *) realloc(d->overlays,
+	    sizeof(struct diskimage_overlay) * d->nr_of_overlays));
+
+	d->overlays[d->nr_of_overlays - 1] = overlay;
+
+	if (remove_after_open) {
+		if (unlink(overlay_basename) != 0)
+			perror(overlay_basename);
+
+		if (unlink(bitmap_name) != 0)
+			perror(bitmap_name);
+	}
+
+	free(bitmap_name);
+
+	return true;
+}
+
+
+/*
+ *  diskimage_recalc_size():
+ *
+ *  Recalculate a disk's size by stat()-ing it.
+ *  d is assumed to be non-NULL.
+ */
+bool diskimage_recalc_size(struct diskimage *d)
+{
+	struct stat st;
+	int res;
+	int64_t size = 0;
+
+	res = stat(d->fname, &st);
+	if (res)
+		return false;
+
+	size = st.st_size;
+
+	/*
+	 *  TODO:  CD-ROM devices, such as /dev/cd0c, how can one
+	 *  check how much data is on that cd-rom without reading it?
+	 *  For now, assume some large number, hopefully it will be
+	 *  enough to hold any cd-rom image.
+	 */
+	if (d->is_a_cdrom && size == 0)
+		size = 762048000;
+
+	d->total_size = size;
+
+	if ((d->total_size == 720*1024 || d->total_size == 1474560
+	    || d->total_size == 2949120 || d->total_size == 1228800)
+	    && d->type == DISKIMAGE_UNKNOWN)
+		d->type = DISKIMAGE_FLOPPY;
+
+	switch (d->type) {
+	case DISKIMAGE_FLOPPY:
+		if (d->total_size < 737280) {
+			debugmsg(SUBSYS_DISK, "", VERBOSITY_WARNING,
+			    "TODO: small (non-80-cylinder) floppies?");
+		}
+
+		if (!d->chs_override) {
+			d->cylinders = 80;
+			d->heads = 2;
+			d->sectors_per_track = d->nr_of_logical_blocks * d->logical_block_size
+				/ (d->cylinders * d->heads * 512);
+		}
+		break;
+
+	default:/*  Non-floppies:  */
+		if (!d->chs_override) {
+			d->heads = 16;
+			d->sectors_per_track = 63;
+
+			int64_t bytespercyl = d->heads * d->sectors_per_track * 512;
+			d->cylinders = size / bytespercyl;
+			if (d->cylinders * bytespercyl < size)
+				d->cylinders ++;
+		}
+	}
+
+	// printf("c=%i h=%i s=%i\n", d->cylinders, d->heads, d->sectors_per_track);
+
+	// Update size to full cylinders.
+	size = d->heads * d->sectors_per_track * d->cylinders * 512;
+
+	d->nr_of_logical_blocks = size / d->logical_block_size;
+	if (size & (d->logical_block_size - 1))
+		d->nr_of_logical_blocks ++;
+
+	return true;
+}
+
+
+/*
+ *  diskimage_getsize():
+ *
+ *  Returns -1 if the specified disk id/type does not exists, otherwise
+ *  the size of the disk image is returned.
+ */
+int64_t diskimage_getsize(struct machine *machine, int id, int type)
+{
+	struct diskimage *d = machine->first_diskimage;
+
+	while (d != NULL) {
+		if (d->type == type && d->id == id)
+			return d->nr_of_logical_blocks * d->logical_block_size;
+		d = d->next;
+	}
+	return -1;
+}
+
+
+/*
+ *  diskimage_get_baseoffset():
+ *
+ *  Returns -1 if the specified disk id/type does not exists, otherwise
+ *  the base offset of the disk image is returned.
+ */
+int64_t diskimage_get_baseoffset(struct machine *machine, int id, int type)
+{
+	struct diskimage *d = machine->first_diskimage;
+
+	while (d != NULL) {
+		if (d->type == type && d->id == id)
+			return d->override_base_offset;
+
+		d = d->next;
+	}
+	return -1;
+}
+
+
+/*
+ *  diskimage_set_baseoffset():
+ *
+ *  Sets the base offset for a disk image. Useful e.g. when booting directly
+ *  from NetBSD/dreamcast or Linux/dreamcast ISO images.
+ */
+void diskimage_set_baseoffset(struct machine *machine, int id, int type, int64_t offset)
+{
+	struct diskimage *d = machine->first_diskimage;
+
+	while (d != NULL) {
+		if (d->type == type && d->id == id) {
+			d->override_base_offset = offset;
+			return;
+		}
+		
+		d = d->next;
+	}
+
+	fatal("diskimage_set_baseoffset(): disk id %i (type %i) not found?\n",
+	    id, diskimage_types[type]);
+	exit(1);
+}
+
+
+/*
+ *  diskimage_getchs():
+ *
+ *  Returns the current CHS values of a disk image.
+ */
+void diskimage_getchs(struct machine *machine, int id, int type,
+	int *c, int *h, int *s)
+{
+	struct diskimage *d = machine->first_diskimage;
+
+	while (d != NULL) {
+		if (d->type == type && d->id == id) {
+			*c = d->cylinders;
+			*h = d->heads;
+			*s = d->sectors_per_track;
+			return;
+		}
+		d = d->next;
+	}
+	fatal("diskimage_getchs(): disk id %i (type %i) not found?\n",
+	    id, diskimage_types[type]);
+	exit(1);
+}
+
+
+/*
+ *  diskimage_access__cdrom():
+ *
+ *  This is a special-case function, called from diskimage__internal_access().
+ *  On my FreeBSD 4.9 system, the cdrom device /dev/cd0c seems to not be able
+ *  to handle something like "fseek(512); fread(512);" but it handles
+ *  "fseek(2048); fread(512);" just fine.  So, if diskimage__internal_access()
+ *  fails in reading a block of data, this function is called as an attempt to
+ *  align reads at 2048-byte sectors instead.
+ *
+ *  (Ugly hack.  TODO: how to solve this cleanly?)
+ *
+ *  NOTE:  Returns the number of bytes read, 0 if nothing was successfully
+ *  read. (These are not the same as diskimage_access()).
+ */
+#define	CDROM_SECTOR_SIZE	2048
+static size_t diskimage_access__cdrom(struct diskimage *d, off_t offset,
+	unsigned char *buf, size_t len)
+{
+	off_t aligned_offset;
+	size_t bytes_read, total_copied = 0;
+	unsigned char cdrom_buf[CDROM_SECTOR_SIZE];
+	off_t buf_ofs, i = 0;
+
+	/*  printf("diskimage_access__cdrom(): offset=0x%llx size=%lli\n",
+	    (long long)offset, (long long)len);  */
+
+	aligned_offset = (offset / CDROM_SECTOR_SIZE) * CDROM_SECTOR_SIZE;
+	my_fseek(d->f, aligned_offset, SEEK_SET);
+
+	while (len != 0) {
+		bytes_read = fread(cdrom_buf, 1, CDROM_SECTOR_SIZE, d->f);
+		if (bytes_read != CDROM_SECTOR_SIZE)
+			return 0;
+
+		/*  Copy (part of) cdrom_buf into buf:  */
+		buf_ofs = offset - aligned_offset;
+		while (buf_ofs < CDROM_SECTOR_SIZE && len != 0) {
+			buf[i ++] = cdrom_buf[buf_ofs ++];
+			total_copied ++;
+			len --;
+		}
+
+		aligned_offset += CDROM_SECTOR_SIZE;
+		offset = aligned_offset;
+	}
+
+	return total_copied;
+}
+
+
+/*  Helper function.  */
+static void overlay_set_block_in_use(struct diskimage *d,
+	int overlay_nr, off_t ofs)
+{
+	off_t bit_nr = ofs / OVERLAY_BLOCK_SIZE;
+	off_t bitmap_file_offset = bit_nr / 8;
+	int res;
+	unsigned char data;
+
+	res = my_fseek(d->overlays[overlay_nr].f_bitmap,
+	    bitmap_file_offset, SEEK_SET);
+	if (res) {
+		perror("my_fseek");
+		fprintf(stderr, "Could not seek in bitmap file?"
+		    " offset = %lli, read\n", (long long)bitmap_file_offset);
+		exit(1);
+	}
+
+	/*  Read the original bitmap data, and OR in the new bit:  */
+	res = fread(&data, 1, 1, d->overlays[overlay_nr].f_bitmap);
+	if (res != 1)
+		data = 0x00;
+
+	data |= (1 << (bit_nr & 7));
+
+	/*  Write it back:  */
+	res = my_fseek(d->overlays[overlay_nr].f_bitmap,
+	    bitmap_file_offset, SEEK_SET);
+	if (res) {
+		perror("my_fseek");
+		fprintf(stderr, "Could not seek in bitmap file?"
+		    " offset = %lli, write\n", (long long)bitmap_file_offset);
+		exit(1);
+	}
+	res = fwrite(&data, 1, 1, d->overlays[overlay_nr].f_bitmap);
+	if (res != 1) {
+		fprintf(stderr, "Could not write to bitmap file. Aborting.\n");
+		exit(1);
+	}
+	
+	if (do_fsync)
+		fsync(fileno(d->overlays[overlay_nr].f_bitmap));
+}
+
+
+/*  Helper function.  */
+static int overlay_has_block(struct diskimage *d, int overlay_nr, off_t ofs)
+{
+	off_t bit_nr = ofs / OVERLAY_BLOCK_SIZE;
+	off_t bitmap_file_offset = bit_nr / 8;
+	int res;
+	unsigned char data;
+
+	res = my_fseek(d->overlays[overlay_nr].f_bitmap,
+	    bitmap_file_offset, SEEK_SET);
+	if (res != 0)
+		return 0;
+
+	/*  The seek succeeded, now read the bit:  */
+	res = fread(&data, 1, 1, d->overlays[overlay_nr].f_bitmap);
+	if (res != 1)
+		return 0;
+
+	if (data & (1 << (bit_nr & 7)))
+		return 1;
+
+	return 0;
+}
+
+
+/*
+ *  fwrite_helper():
+ *
+ *  Internal helper function. Writes to a disk image file, or if the
+ *  disk image has overlays, to the last overlay.
+ */
+static size_t fwrite_helper(off_t offset, unsigned char *buf,
+	size_t len, struct diskimage *d)
+{
+	off_t curofs;
+
+	/*  Fast return-path for the case when no overlays are used:  */
+	if (d->nr_of_overlays == 0) {
+		int res = my_fseek(d->f, offset, SEEK_SET);
+		if (res != 0) {
+			fatal("[ diskimage__internal_access(): fseek() failed"
+			    " on disk id %i \n", d->id);
+			return 0;
+		}
+
+		size_t written = fwrite(buf, 1, len, d->f);
+
+		if (do_fsync)
+			fsync(fileno(d->f));
+
+		return written;
+	}
+
+	if ((len & (OVERLAY_BLOCK_SIZE-1)) != 0) {
+		fatal("TODO: overlay access (write), len not multiple of "
+		    "overlay block size. not yet implemented.\n");
+		fatal("len = %lli\n", (long long) len);
+		abort();
+	}
+	if ((offset & (OVERLAY_BLOCK_SIZE-1)) != 0) {
+		fatal("TODO: unaligned overlay access\n");
+		fatal("offset = %lli\n", (long long) offset);
+		abort();
+	}
+
+	/*  Split the write into OVERLAY_BLOCK_SIZE writes:  */
+	for (curofs = offset; curofs < (off_t) (offset+len);
+	     curofs += OVERLAY_BLOCK_SIZE) {
+		/*  Always write to the last overlay:  */
+		int overlay_nr = d->nr_of_overlays-1;
+		off_t lenwritten;
+		int res = my_fseek(d->overlays[overlay_nr].f_data,
+		    curofs, SEEK_SET);
+		if (res != 0) {
+			fatal("[ diskimage: fwrite_helper(): fseek()"
+			    " failed on disk id %i ]\n", d->id);
+			return 0;
+		}
+
+		lenwritten = fwrite(buf, 1, OVERLAY_BLOCK_SIZE,
+		    d->overlays[overlay_nr].f_data);
+		if (lenwritten != OVERLAY_BLOCK_SIZE) {
+			fatal("[ diskimage: fwrite_helper(): fwrite to"
+			    " overlay failed on disk id %i ]\n", d->id);
+			exit(1);
+		}
+
+		buf += OVERLAY_BLOCK_SIZE;
+
+		if (do_fsync)
+			fsync(fileno(d->overlays[overlay_nr].f_data));
+
+		/*  Mark this block in the last overlay as in use:  */
+		overlay_set_block_in_use(d, overlay_nr, curofs);
+	}
+
+	return len;
+}
+
+
+/*
+ *  fread_helper():
+ *
+ *  Internal helper function. Reads from a disk image file, or if the
+ *  disk image has overlays, from the last overlay that has the specific
+ *  data (or the disk image file itself).
+ */
+static size_t fread_helper(off_t offset, unsigned char *buf,
+	size_t len, struct diskimage *d)
+{
+	off_t curofs;
+	size_t totallenread = 0;
+
+	/*  Fast return-path for the case when no overlays are used:  */
+	if (d->nr_of_overlays == 0) {
+		int res = my_fseek(d->f, offset, SEEK_SET);
+		if (res != 0) {
+			fatal("[ diskimage__internal_access(): fseek() failed"
+			    " on disk id %i \n", d->id);
+			return 0;
+		}
+
+		return fread(buf, 1, len, d->f);
+	}
+
+	/*  Split the read into OVERLAY_BLOCK_SIZE reads:  */
+	for (curofs=offset; len != 0;
+	    curofs = (curofs | (OVERLAY_BLOCK_SIZE-1)) + 1) {
+		/*  Find the overlay, if any, that has this block:  */
+		off_t lenread, lentoread;
+		int overlay_nr;
+		for (overlay_nr = d->nr_of_overlays-1;
+		    overlay_nr >= 0; overlay_nr --) {
+			if (overlay_has_block(d, overlay_nr, curofs))
+				break;
+		}
+
+		lentoread = len > OVERLAY_BLOCK_SIZE? OVERLAY_BLOCK_SIZE : len;
+
+		if (overlay_nr >= 0) {
+			/*  Read from overlay:  */
+			int res = my_fseek(d->overlays[overlay_nr].f_data,
+			    curofs, SEEK_SET);
+			if (res != 0) {
+				fatal("[ diskimage__internal_access(): fseek()"
+				    " failed on disk id %i \n", d->id);
+				return 0;
+			}
+			lenread = fread(buf, 1, lentoread,
+			    d->overlays[overlay_nr].f_data);
+		} else {
+			/*  Read from the base disk image:  */
+			int res = my_fseek(d->f, curofs, SEEK_SET);
+			if (res != 0) {
+				fatal("[ diskimage__internal_access(): fseek()"
+				    " failed on disk id %i \n", d->id);
+				return 0;
+			}
+			lenread = fread(buf, 1, lentoread, d->f);
+		}
+
+		if (lenread != lentoread) {
+			fatal("[ INCOMPLETE READ from disk id %i, offset"
+			    " %lli ]\n", d->id, (long long)curofs);
+		}
+
+		len -= lentoread;
+		totallenread += lenread;
+		buf += OVERLAY_BLOCK_SIZE;
+	}
+
+	return totallenread;
+}
+
+
+/*
+ *  diskimage__internal_access():
+ *
+ *  Read from or write to a struct diskimage.
+ *
+ *  Returns 1 if the access completed successfully, 0 otherwise.
+ */
+int diskimage__internal_access(struct diskimage *d, int writeflag,
+	off_t offset, unsigned char *buf, size_t len)
+{
+	ssize_t lendone;
+
+	if (buf == NULL) {
+		fprintf(stderr, "diskimage__internal_access(): buf = NULL\n");
+		exit(1);
+	}
+	if (len == 0)
+		return 1;
+	if (d->f == NULL)
+		return 0;
+
+	if (writeflag) {
+		if (!d->writable)
+			return 0;
+
+		lendone = fwrite_helper(offset, buf, len, d);
+	} else {
+		/*
+		 *  Special case for CD-ROMs. Actually, this is not needed
+		 *  for .iso images, only for physical CDROMS on some OSes,
+		 *  such as FreeBSD.
+		 */
+		if (d->is_a_cdrom)
+			lendone = diskimage_access__cdrom(d, offset, buf, len);
+		else
+			lendone = fread_helper(offset, buf, len, d);
+
+		if (lendone >= 0 && lendone < (ssize_t)len)
+			memset(buf + lendone, 0, len - lendone);
+	}
+
+	/*
+	 *  Incomplete data transfer?
+	 *
+	 *  If we could not read anything at all, then return failure.
+	 *  If we could read a partial block, then return success (with
+	 *  the resulting buffer zero-filled at the end).
+	 */
+#if 0
+// TODO: check against full cylinder-size instead
+	if (lendone <= 0) {
+		fatal("[ diskimage__internal_access(): disk_id %i, offset %lli"
+		    ", transfer not completed. len=%i, len_done=%i ]\n",
+		    d->id, (long long)offset, (int)len, (int)lendone);
+		return 0;
+	}
+#endif
+	return 1;
+}
+
+
+/*
+ *  diskimage_access():
+ *
+ *  Read from or write to a disk image on a machine.
+ *
+ *  Returns 1 if the access completed successfully, 0 otherwise.
+ */
+int diskimage_access(struct machine *machine, int id, int type, int writeflag,
+	off_t offset, unsigned char *buf, size_t len)
+{
+	struct diskimage *d = machine->first_diskimage;
+
+	while (d != NULL) {
+		if (d->type == type && d->id == id)
+			break;
+		d = d->next;
+	}
+
+	if (d == NULL) {
+		fatal("[ diskimage_access(): ERROR: trying to access a "
+		    "non-existant %s disk image (id %i)\n",
+		    diskimage_types[type], id);
+		return 0;
+	}
+
+	offset -= d->override_base_offset;
+	if (offset < 0 && offset + d->override_base_offset >= 0) {
+		debug("[ reading before start of disk image ]\n");
+		/*  Returning zeros.  */
+		memset(buf, 0, len);
+		return 1;
+	}
+
+	return diskimage__internal_access(d, writeflag, offset, buf, len);
+}
+
+
+int get_default_disk_type_for_machine(struct machine *machine)
+{
+	if (machine->machine_type == MACHINE_PMAX ||
+	    machine->machine_type == MACHINE_ARC ||
+	    machine->machine_type == MACHINE_SGI ||
+	    machine->machine_type == MACHINE_LUNA88K ||
+	    machine->machine_type == MACHINE_MVME88K)
+		return DISKIMAGE_SCSI;
+
+	return DISKIMAGE_IDE;
+}
+
+
+/*
+ *  diskimage_add():
+ *
+ *  Add a disk image.  fname is the filename of the disk image.
+ *  The filename may be prefixed with one or more modifiers, followed
+ *  by a colon.
+ *
+ *	b	specifies that this is a bootable device
+ *	c	CD-ROM (instead of a normal DISK)
+ *	d	DISK (this is the default)
+ *	f	FLOPPY (instead of SCSI)
+ *	gH;S;	set geometry (H=heads, S=sectors per track, cylinders are
+ *		automatically calculated). (This is ignored for floppies.)
+ *	i	IDE (instead of SCSI)
+ *	oOFS;	set base offset in bytes, when booting from an ISO9660 fs
+ *	r       read-only (don't allow changes to the file)
+ *	s	SCSI (this is the default)
+ *	t	tape
+ *	V	add an overlay to a disk image
+ *	0-7	force a specific SCSI ID number
+ *
+ *  machine is assumed to be non-NULL.
+ *
+ *  Returns an integer >= 0 identifying the disk image. On error, a value less
+ *  than zero is returned.
+ */
+int diskimage_add(struct machine *machine, char *fname)
+{
+	struct diskimage *d, *d2;
+	int id = 0, override_heads=0, override_spt=0;
+	int64_t override_base_offset=0;
+	char *cp;
+	int prefix_b=0, prefix_c=0, prefix_d=0, prefix_f=0, prefix_g=0;
+	int prefix_i=0, prefix_r=0, prefix_s=0, prefix_t=0, prefix_id=-1;
+	int prefix_o=0, prefix_V=0;
+	bool prefix_R = false;
+
+	if (fname == NULL) {
+		debugmsg(SUBSYS_DISK, "diskimage_add()", VERBOSITY_ERROR,
+		    "NULL ptr");
+		return -1;
+	}
+
+	/*  Get prefix from fname:  */
+	cp = strchr(fname, ':');
+	if (cp != NULL) {
+		while (fname <= cp) {
+			char c = *fname++;
+			switch (c) {
+			case '0':
+			case '1':
+			case '2':
+			case '3':
+			case '4':
+			case '5':
+			case '6':
+			case '7':
+				prefix_id = c - '0';
+				break;
+			case 'b':
+				prefix_b = 1;
+				break;
+			case 'c':
+				prefix_c = 1;
+				break;
+			case 'd':
+				prefix_d = 1;
+				break;
+			case 'f':
+				prefix_f = 1;
+				break;
+			case 'g':
+				prefix_g = 1;
+				override_heads = atoi(fname);
+				while (*fname != '\0' && *fname != ';')
+					fname ++;
+				if (*fname == ';')
+					fname ++;
+				override_spt = atoi(fname);
+				while (*fname != '\0' && *fname != ';' &&
+				    *fname != ':')
+					fname ++;
+				if (*fname == ';')
+					fname ++;
+				if (override_heads < 1 ||
+				    override_spt < 1) {
+					fatal("Bad geometry: heads=%i "
+					    "spt=%i\n", override_heads,
+					    override_spt);
+					return -1;
+				}
+				break;
+			case 'i':
+				prefix_i = 1;
+				break;
+			case 'o':
+				prefix_o = 1;
+				override_base_offset = atoi(fname);
+				while (*fname != '\0' && *fname != ':'
+				    && *fname != ';')
+					fname ++;
+				if (*fname == ':' || *fname == ';')
+					fname ++;
+				if (override_base_offset < 0) {
+					fatal("Bad base offset: %" PRIi64
+					    "\n", override_base_offset);
+					return -1;
+				}
+				break;
+			case 'R':
+				prefix_R = true;
+				break;
+			case 'r':
+				prefix_r = 1;
+				break;
+			case 's':
+				prefix_s = 1;
+				break;
+			case 't':
+				prefix_t = 1;
+				break;
+			case 'V':
+				prefix_V = 1;
+				break;
+			case ':':
+				break;
+			default:
+				fprintf(stderr, "diskimage_add(): invalid "
+				    "prefix char '%c'\n", c);
+				return -1;
+			}
+		}
+	}
+
+	/*  Allocate a new diskimage struct:  */
+	CHECK_ALLOCATION(d = (struct diskimage *) malloc(sizeof(struct diskimage)));
+	memset(d, 0, sizeof(struct diskimage));
+
+	if (prefix_i + prefix_f + prefix_s > 1) {
+		fprintf(stderr, "Invalid disk image prefix(es). You can"
+		    "only use one of i, f, and s\nfor each disk image.\n");
+		exit(1);
+	}
+
+	if (prefix_i)
+		d->type = DISKIMAGE_IDE;
+	if (prefix_f)
+		d->type = DISKIMAGE_FLOPPY;
+	if (prefix_s)
+		d->type = DISKIMAGE_SCSI;
+
+	if (prefix_V && prefix_R) {
+		debugmsg(SUBSYS_DISK, "", VERBOSITY_ERROR,
+		    "'V' and 'R' prefixes can not be combined!");
+		return -1;
+	}
+
+	/*  Special case: Add an overlay for an already added disk image:  */
+	if (prefix_V) {
+		struct diskimage *dx = machine->first_diskimage;
+
+		if (prefix_id < 0) {
+			debugmsg(SUBSYS_DISK, "", VERBOSITY_ERROR,
+			    "The 'V' disk image prefix requires"
+			    " a disk ID to also be supplied.");
+			return -1;
+		}
+
+		if (d->type == DISKIMAGE_UNKNOWN)
+			d->type = get_default_disk_type_for_machine(machine);
+
+		while (dx != NULL) {
+			if (d->type == dx->type && prefix_id == dx->id)
+				break;
+			dx = dx->next;
+		}
+
+		/*  Free the preliminary d struct:  */
+		free(d);
+
+		if (dx == NULL) {
+			fprintf(stderr, "Bad ID supplied for overlay?\n");
+			return -1;
+		}
+
+		if (!diskimage_add_overlay(dx, fname, false)) {
+			debugmsg(SUBSYS_DISK, "", VERBOSITY_ERROR,
+			    "could not add overlay name '%s'",
+			    fname);
+			return -1;
+		}
+
+		/*  Return the ID of the disk image, even though no disk
+		    image was added.  */
+		return dx->id;
+	}
+
+	/*  Add the new disk image in the disk image chain:  */
+	d2 = machine->first_diskimage;
+	if (d2 == NULL) {
+		machine->first_diskimage = d;
+	} else {
+		while (d2->next != NULL)
+			d2 = d2->next;
+		d2->next = d;
+	}
+
+	if (prefix_o)
+		d->override_base_offset = override_base_offset;
+
+	CHECK_ALLOCATION(d->fname = strdup(fname));
+
+	d->logical_block_size = 512;
+
+	/*
+	 *  Is this a tape, CD-ROM or a normal disk?
+	 *
+	 *  An intelligent guess, if no prefixes are used, would be that
+	 *  filenames ending with .iso or .cdr are CD-ROM images.
+	 */
+	if (prefix_t) {
+		d->is_a_tape = 1;
+	} else {
+		if (prefix_c ||
+		    ((strlen(d->fname) > 4 &&
+		    (strcasecmp(d->fname + strlen(d->fname) - 4, ".cdr") == 0 ||
+		    strcasecmp(d->fname + strlen(d->fname) - 4, ".iso") == 0))
+		    && !prefix_d)
+		   ) {
+			d->is_a_cdrom = 1;
+
+			/*
+			 *  This is tricky. Should I use 512 or 2048 here?
+			 *  NetBSD/pmax 1.6.2 and Ultrix likes 512 bytes
+			 *  per sector, but NetBSD 2.0_BETA suddenly ignores
+			 *  this value and uses 2048 instead.
+			 *
+			 *  OpenBSD/arc doesn't like 2048, it requires 512
+			 *  to work correctly.
+			 *
+			 *  TODO
+			 */
+
+#if 0
+			if (machine->machine_type == MACHINE_PMAX)
+				d->logical_block_size = 512;
+			else
+				d->logical_block_size = 2048;
+#endif
+			d->logical_block_size = 512;
+		}
+	}
+
+	if (prefix_g) {
+		d->chs_override = 1;
+		d->heads = override_heads;
+		d->sectors_per_track = override_spt;
+	}
+
+	if (!diskimage_recalc_size(d))
+		debugmsg(SUBSYS_DISK, "", VERBOSITY_WARNING,
+		    "diskimage_recalc_size() failed!");
+
+	if (d->type == DISKIMAGE_UNKNOWN)
+		d->type = get_default_disk_type_for_machine(machine);
+
+	d->rpms = 3600;
+
+	if (prefix_b)
+		d->is_boot_device = 1;
+
+	bool readable = access(fname, R_OK) == 0? 1 : 0;
+	d->writable = access(fname, W_OK) == 0? 1 : 0;
+
+	if (!readable) {
+		debugmsg(SUBSYS_DISK, "", VERBOSITY_ERROR,
+		    "could not access '%s': %s", fname, strerror(errno));
+		return -1;
+	}
+
+	if (d->is_a_cdrom || prefix_r) {
+		d->writable = 0;
+	} else if (!d->writable) {
+		if (prefix_R) {
+			d->writable = 1;
+		} else {
+			debugmsg(SUBSYS_DISK, "", VERBOSITY_ERROR,
+			    "'%s' is read-only in the host file system.\n"
+			    "Use the r: prefix to indicate that the file should be treated\n"
+			    "as read-only, the R: prefix to use a temporary overlay (allowing\n"
+			    "guest operating systems to write to that temporary overlay), or\n"
+			    "make the file writable.",
+			    d->fname);
+			return -1;
+		}
+	}
+
+	d->f = fopen(fname, d->writable && !prefix_R ? "r+" : "r");
+	if (d->f == NULL) {
+		debugmsg(SUBSYS_DISK, "", VERBOSITY_ERROR,
+		    "could not open '%s' for reading%s: %s",
+		    fname,
+		    d->writable? " and writing" : "",
+		    strerror(errno));
+		return -1;
+	}
+
+	/*  Calculate which ID to use:  */
+	if (prefix_id == -1) {
+		int start = 0;
+		int delta = 1;
+		
+		if (machine->machine_type == MACHINE_LUNA88K) {
+			start = 6;
+			delta = -1;
+		}
+		
+		int free = start;
+		
+		bool collision = true;
+
+		while (collision) {
+			collision = false;
+			d2 = machine->first_diskimage;
+			while (d2 != NULL) {
+				/*  (don't compare against ourselves :)  */
+				if (d2 == d) {
+					d2 = d2->next;
+					continue;
+				}
+				if (d2->id == free && d2->type == d->type) {
+					collision = true;
+					break;
+				}
+				d2 = d2->next;
+			}
+			if (!collision)
+				id = free;
+			else
+				free += delta;
+		}
+		
+		if (id < 0) {
+			fprintf(stderr, "Too many IDs used?\n");
+			exit(1);
+		}
+	} else {
+		id = prefix_id;
+		d2 = machine->first_diskimage;
+		while (d2 != NULL) {
+			/*  (don't compare against ourselves :)  */
+			if (d2 == d) {
+				d2 = d2->next;
+				continue;
+			}
+			if (d2->id == id && d2->type == d->type) {
+				fprintf(stderr, "disk image id %i "
+				    "already in use\n", id);
+				exit(1);
+			}
+			d2 = d2->next;
+		}
+	}
+
+	d->id = id;
+
+	if (prefix_R) {
+		char tmpname[1000];
+		const char* tmpdir = getenv("TMPDIR");
+		if (tmpdir == NULL)
+			tmpdir = "/tmp";
+		
+		int old_umask = umask(077);
+
+		// TODO: Not secure. Both the .img and the .img.map file
+		// need to be created by the process itself to avoid a race.
+		// NOTE/TODO: Ideally fopen mode "x" (from C11) for exclusive open.
+		snprintf(tmpname, sizeof(tmpname), "%s/gxemul.%i.temp-diskimage-overlay.%i.img.map",
+		    tmpdir, d->id, getpid());
+
+		FILE* f_img_map = fopen(tmpname, "w");
+		fclose(f_img_map);
+
+		snprintf(tmpname, sizeof(tmpname), "%s/gxemul.%i.temp-diskimage-overlay.%i.img",
+		    tmpdir, d->id, getpid());
+
+		FILE* f_img = fopen(tmpname, "w");
+		fclose(f_img);
+
+		umask(old_umask);
+
+		if (!diskimage_add_overlay(d, tmpname, true)) {
+			debugmsg(SUBSYS_DISK, "", VERBOSITY_ERROR,
+			    "could not add overlay name '%s'",
+			    fname);
+			return -1;
+		}
+	}
+
+	return id;
+}
+
+
+/*
+ *  diskimage_bootdev():
+ *
+ *  Returns the disk id of the device which we're booting from.  If typep is
+ *  non-NULL, the type is returned as well.
+ *
+ *  If no disk was used as boot device, then -1 is returned. (In practice,
+ *  this is used to fake network (tftp) boot.)
+ */
+int diskimage_bootdev(struct machine *machine, int *typep)
+{
+	struct diskimage *d;
+
+	d = machine->first_diskimage;
+	while (d != NULL) {
+		if (d->is_boot_device) {
+			if (typep != NULL)
+				*typep = d->type;
+			return d->id;
+		}
+		d = d->next;
+	}
+
+	d = machine->first_diskimage;
+	if (d != NULL) {
+		if (typep != NULL)
+			*typep = d->type;
+		return d->id;
+	}
+
+	return -1;
+}
+
+
+/*
+ *  diskimage_getname():
+ *
+ *  Returns 1 if a valid disk image name was returned, 0 otherwise.
+ */
+int diskimage_getname(struct machine *machine, int id, int type,
+	char *buf, size_t bufsize)
+{
+	struct diskimage *d = machine->first_diskimage;
+
+	if (buf == NULL)
+		return 0;
+
+	while (d != NULL) {
+		if (d->type == type && d->id == id) {
+			char *p = strrchr(d->fname, '/');
+			if (p == NULL)
+				p = d->fname;
+			else
+				p ++;
+			snprintf(buf, bufsize, "%s", p);
+			return 1;
+		}
+		d = d->next;
+	}
+	return 0;
+}
+
+
+/*
+ *  diskimage_is_a_cdrom():
+ *
+ *  Returns 1 if a disk image is a CDROM, 0 otherwise.
+ */
+int diskimage_is_a_cdrom(struct machine *machine, int id, int type)
+{
+	struct diskimage *d = machine->first_diskimage;
+
+	while (d != NULL) {
+		if (d->type == type && d->id == id)
+			return d->is_a_cdrom;
+		d = d->next;
+	}
+	return 0;
+}
+
+
+/*
+ *  diskimage_is_a_tape():
+ *
+ *  Returns 1 if a disk image is a tape, 0 otherwise.
+ *
+ *  (Used in src/machine.c, to select 'rz' vs 'tz' for DECstation
+ *  boot strings.)
+ */
+int diskimage_is_a_tape(struct machine *machine, int id, int type)
+{
+	struct diskimage *d = machine->first_diskimage;
+
+	while (d != NULL) {
+		if (d->type == type && d->id == id)
+			return d->is_a_tape;
+		d = d->next;
+	}
+	return 0;
+}
+
+
+/*
+ *  diskimage_dump_info():
+ *
+ *  Debug dump of all diskimages that are loaded for a specific machine.
+ */
+void diskimage_dump_info(struct machine *machine)
+{
+	struct diskimage *d = machine->first_diskimage;
+
+	while (d != NULL) {
+		debugmsg(SUBSYS_MACHINE, "diskimage", VERBOSITY_INFO, "%s", d->fname);
+
+		debug_indentation(1);
+
+		switch (d->type) {
+		case DISKIMAGE_SCSI:
+			debug("SCSI");
+			break;
+		case DISKIMAGE_IDE:
+			debug("IDE");
+			break;
+		case DISKIMAGE_FLOPPY:
+			debug("FLOPPY");
+			break;
+		default:
+			debug("UNKNOWN type %i", d->type);
+		}
+
+		debug(" %s", d->is_a_tape? "TAPE" :
+			(d->is_a_cdrom? "CD-ROM" : "DISK"));
+		debug(" id %i, ", d->id);
+		debug("%s, ", d->writable? "read/write" : "read-only");
+
+		int64_t s = d->nr_of_logical_blocks * d->logical_block_size;
+
+		if (d->type == DISKIMAGE_FLOPPY)
+			debug("%lli KB", (long long) (s / 1024));
+		else
+			debug("%lli MB", (long long) (s / 1048576));
+
+		if (d->type == DISKIMAGE_FLOPPY || d->chs_override)
+			debug(" (CHS=%i,%i,%i)", d->cylinders, d->heads,
+			    d->sectors_per_track);
+		else
+			debug(" (%lli %i-byte blocks)", (long long)d->nr_of_logical_blocks, d->logical_block_size);
+
+		if (d->is_boot_device)
+			debug(" (BOOT)");
+		debug("\n");
+
+		debug_indentation(1);
+
+		for (int i=0; i<d->nr_of_overlays; i++) {
+			debug("overlay %i: %s\n",
+			    i, d->overlays[i].overlay_basename);
+		}
+
+		debug_indentation(-2);
+
+		d = d->next;
+	}
+}
+
diff -Nru gxemul-0.6.2/src/disk/diskimage.cc gxemul-0.7.0+dfsg/src/disk/diskimage.cc
--- gxemul-0.6.2/src/disk/diskimage.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/disk/diskimage.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1153 +0,0 @@
-/*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Disk image support.
- *
- *  TODO:  diskimage_remove()? This would be useful for floppies in PC-style
- *	   machines, where disks may need to be swapped during boot etc.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-
-#include "cpu.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "misc.h"
-
-
-bool do_fsync = false;
-
-/*  #define debug fatal  */
-
-static const char *diskimage_types[] = DISKIMAGE_TYPES;
-
-
-/**************************************************************************/
-
-/*
- *  my_fseek():
- *
- *  A helper function, like fseek() but takes off_t.  If the system has
- *  fseeko, then that is used. Otherwise I try to fake off_t offsets here.
- *
- *  The correct position is reached by seeking 2 billion bytes at a time
- *  (or less).  Note: This method is only used for SEEK_SET, for SEEK_CUR
- *  and SEEK_END, normal fseek() is used!
- *
- *  TODO: It seemed to work on Linux/i386, but not on Solaris/sparc (?).
- *  Anyway, most modern systems have fseeko(), so it shouldn't be a problem.
- */
-static int my_fseek(FILE *f, off_t offset, int whence)
-{
-#ifdef HACK_FSEEKO
-	if (whence == SEEK_SET) {
-		int res = 0;
-		off_t curoff = 0;
-		off_t cur_step;
-
-		fseek(f, 0, SEEK_SET);
-		while (curoff < offset) {
-			/*  How far to seek?  */
-			cur_step = offset - curoff;
-			if (cur_step > 2000000000)
-				cur_step = 2000000000;
-			res = fseek(f, cur_step, SEEK_CUR);
-			if (res)
-				return res;
-			curoff += cur_step;
-		}
-		return 0;
-	} else
-		return fseek(f, offset, whence);
-#else
-	return fseeko(f, offset, whence);
-#endif
-}
-
-
-/**************************************************************************/
-
-
-/*
- *  diskimage_exist():
- *
- *  Returns 1 if the specified disk id (for a specific type) exists, 0
- *  otherwise.
- */
-int diskimage_exist(struct machine *machine, int id, int type)
-{
-	struct diskimage *d = machine->first_diskimage;
-
-	while (d != NULL) {
-		if (d->type == type && d->id == id)
-			return 1;
-		d = d->next;
-	}
-	return 0;
-}
-
-
-/*
- *  diskimage_add_overlay():
- *
- *  Opens an overlay data file and its corresponding bitmap file, and adds
- *  the overlay to a disk image.
- */
-void diskimage_add_overlay(struct diskimage *d, char *overlay_basename)
-{
-	struct diskimage_overlay overlay;
-	size_t bitmap_name_len = strlen(overlay_basename) + 20;
-	char *bitmap_name;
-
-	CHECK_ALLOCATION(bitmap_name = (char *) malloc(bitmap_name_len));
-	snprintf(bitmap_name, bitmap_name_len, "%s.map", overlay_basename);
-
-	CHECK_ALLOCATION(overlay.overlay_basename = strdup(overlay_basename));
-	overlay.f_data = fopen(overlay_basename, d->writable? "r+" : "r");
-	if (overlay.f_data == NULL) {
-		perror(overlay_basename);
-		exit(1);
-	}
-
-	overlay.f_bitmap = fopen(bitmap_name, d->writable? "r+" : "r");
-	if (overlay.f_bitmap == NULL) {
-		perror(bitmap_name);
-		fprintf(stderr, "Please create the map file first.\n");
-		exit(1);
-	}
-
-	d->nr_of_overlays ++;
-
-	CHECK_ALLOCATION(d->overlays = (struct diskimage_overlay *) realloc(d->overlays,
-	    sizeof(struct diskimage_overlay) * d->nr_of_overlays));
-
-	d->overlays[d->nr_of_overlays - 1] = overlay;
-
-	free(bitmap_name);
-}
-
-
-/*
- *  diskimage_recalc_size():
- *
- *  Recalculate a disk's size by stat()-ing it.
- *  d is assumed to be non-NULL.
- */
-void diskimage_recalc_size(struct diskimage *d)
-{
-	struct stat st;
-	int res;
-	off_t size = 0;
-
-	res = stat(d->fname, &st);
-	if (res) {
-		fprintf(stderr, "[ diskimage_recalc_size(): could not stat "
-		    "'%s' ]\n", d->fname);
-		return;
-	}
-
-	size = st.st_size;
-
-	/*
-	 *  TODO:  CD-ROM devices, such as /dev/cd0c, how can one
-	 *  check how much data is on that cd-rom without reading it?
-	 *  For now, assume some large number, hopefully it will be
-	 *  enough to hold any cd-rom image.
-	 */
-	if (d->is_a_cdrom && size == 0)
-		size = 762048000;
-
-	d->total_size = size;
-	d->ncyls = d->total_size / 1048576;
-
-	/*  TODO: There is a mismatch between d->ncyls and d->cylinders,
-	    SCSI-based stuff usually doesn't care.  TODO: Fix this.  */
-}
-
-
-/*
- *  diskimage_getsize():
- *
- *  Returns -1 if the specified disk id/type does not exists, otherwise
- *  the size of the disk image is returned.
- */
-int64_t diskimage_getsize(struct machine *machine, int id, int type)
-{
-	struct diskimage *d = machine->first_diskimage;
-
-	while (d != NULL) {
-		if (d->type == type && d->id == id)
-			return d->total_size;
-		d = d->next;
-	}
-	return -1;
-}
-
-
-/*
- *  diskimage_get_baseoffset():
- *
- *  Returns -1 if the specified disk id/type does not exists, otherwise
- *  the base offset of the disk image is returned.
- */
-int64_t diskimage_get_baseoffset(struct machine *machine, int id, int type)
-{
-	struct diskimage *d = machine->first_diskimage;
-
-	while (d != NULL) {
-		if (d->type == type && d->id == id)
-			return d->override_base_offset;
-
-		d = d->next;
-	}
-	return -1;
-}
-
-
-/*
- *  diskimage_set_baseoffset():
- *
- *  Sets the base offset for a disk image. Useful e.g. when booting directly
- *  from NetBSD/dreamcast or Linux/dreamcast ISO images.
- */
-void diskimage_set_baseoffset(struct machine *machine, int id, int type, int64_t offset)
-{
-	struct diskimage *d = machine->first_diskimage;
-
-	while (d != NULL) {
-		if (d->type == type && d->id == id) {
-			d->override_base_offset = offset;
-			return;
-		}
-		
-		d = d->next;
-	}
-
-	fatal("diskimage_set_baseoffset(): disk id %i (type %i) not found?\n",
-	    id, diskimage_types[type]);
-	exit(1);
-}
-
-
-/*
- *  diskimage_getchs():
- *
- *  Returns the current CHS values of a disk image.
- */
-void diskimage_getchs(struct machine *machine, int id, int type,
-	int *c, int *h, int *s)
-{
-	struct diskimage *d = machine->first_diskimage;
-
-	while (d != NULL) {
-		if (d->type == type && d->id == id) {
-			*c = d->cylinders;
-			*h = d->heads;
-			*s = d->sectors_per_track;
-			return;
-		}
-		d = d->next;
-	}
-	fatal("diskimage_getchs(): disk id %i (type %i) not found?\n",
-	    id, diskimage_types[type]);
-	exit(1);
-}
-
-
-/*
- *  diskimage_access__cdrom():
- *
- *  This is a special-case function, called from diskimage__internal_access().
- *  On my FreeBSD 4.9 system, the cdrom device /dev/cd0c seems to not be able
- *  to handle something like "fseek(512); fread(512);" but it handles
- *  "fseek(2048); fread(512);" just fine.  So, if diskimage__internal_access()
- *  fails in reading a block of data, this function is called as an attempt to
- *  align reads at 2048-byte sectors instead.
- *
- *  (Ugly hack.  TODO: how to solve this cleanly?)
- *
- *  NOTE:  Returns the number of bytes read, 0 if nothing was successfully
- *  read. (These are not the same as diskimage_access()).
- */
-#define	CDROM_SECTOR_SIZE	2048
-static size_t diskimage_access__cdrom(struct diskimage *d, off_t offset,
-	unsigned char *buf, size_t len)
-{
-	off_t aligned_offset;
-	size_t bytes_read, total_copied = 0;
-	unsigned char cdrom_buf[CDROM_SECTOR_SIZE];
-	off_t buf_ofs, i = 0;
-
-	/*  printf("diskimage_access__cdrom(): offset=0x%llx size=%lli\n",
-	    (long long)offset, (long long)len);  */
-
-	aligned_offset = (offset / CDROM_SECTOR_SIZE) * CDROM_SECTOR_SIZE;
-	my_fseek(d->f, aligned_offset, SEEK_SET);
-
-	while (len != 0) {
-		bytes_read = fread(cdrom_buf, 1, CDROM_SECTOR_SIZE, d->f);
-		if (bytes_read != CDROM_SECTOR_SIZE)
-			return 0;
-
-		/*  Copy (part of) cdrom_buf into buf:  */
-		buf_ofs = offset - aligned_offset;
-		while (buf_ofs < CDROM_SECTOR_SIZE && len != 0) {
-			buf[i ++] = cdrom_buf[buf_ofs ++];
-			total_copied ++;
-			len --;
-		}
-
-		aligned_offset += CDROM_SECTOR_SIZE;
-		offset = aligned_offset;
-	}
-
-	return total_copied;
-}
-
-
-/*  Helper function.  */
-static void overlay_set_block_in_use(struct diskimage *d,
-	int overlay_nr, off_t ofs)
-{
-	off_t bit_nr = ofs / OVERLAY_BLOCK_SIZE;
-	off_t bitmap_file_offset = bit_nr / 8;
-	int res;
-	unsigned char data;
-
-	res = my_fseek(d->overlays[overlay_nr].f_bitmap,
-	    bitmap_file_offset, SEEK_SET);
-	if (res) {
-		perror("my_fseek");
-		fprintf(stderr, "Could not seek in bitmap file?"
-		    " offset = %lli, read\n", (long long)bitmap_file_offset);
-		exit(1);
-	}
-
-	/*  Read the original bitmap data, and OR in the new bit:  */
-	res = fread(&data, 1, 1, d->overlays[overlay_nr].f_bitmap);
-	if (res != 1)
-		data = 0x00;
-
-	data |= (1 << (bit_nr & 7));
-
-	/*  Write it back:  */
-	res = my_fseek(d->overlays[overlay_nr].f_bitmap,
-	    bitmap_file_offset, SEEK_SET);
-	if (res) {
-		perror("my_fseek");
-		fprintf(stderr, "Could not seek in bitmap file?"
-		    " offset = %lli, write\n", (long long)bitmap_file_offset);
-		exit(1);
-	}
-	res = fwrite(&data, 1, 1, d->overlays[overlay_nr].f_bitmap);
-	if (res != 1) {
-		fprintf(stderr, "Could not write to bitmap file. Aborting.\n");
-		exit(1);
-	}
-	
-	if (do_fsync)
-		fsync(fileno(d->overlays[overlay_nr].f_bitmap));
-}
-
-
-/*  Helper function.  */
-static int overlay_has_block(struct diskimage *d, int overlay_nr, off_t ofs)
-{
-	off_t bit_nr = ofs / OVERLAY_BLOCK_SIZE;
-	off_t bitmap_file_offset = bit_nr / 8;
-	int res;
-	unsigned char data;
-
-	res = my_fseek(d->overlays[overlay_nr].f_bitmap,
-	    bitmap_file_offset, SEEK_SET);
-	if (res != 0)
-		return 0;
-
-	/*  The seek succeeded, now read the bit:  */
-	res = fread(&data, 1, 1, d->overlays[overlay_nr].f_bitmap);
-	if (res != 1)
-		return 0;
-
-	if (data & (1 << (bit_nr & 7)))
-		return 1;
-
-	return 0;
-}
-
-
-/*
- *  fwrite_helper():
- *
- *  Internal helper function. Writes to a disk image file, or if the
- *  disk image has overlays, to the last overlay.
- */
-static size_t fwrite_helper(off_t offset, unsigned char *buf,
-	size_t len, struct diskimage *d)
-{
-	off_t curofs;
-
-	/*  Fast return-path for the case when no overlays are used:  */
-	if (d->nr_of_overlays == 0) {
-		int res = my_fseek(d->f, offset, SEEK_SET);
-		if (res != 0) {
-			fatal("[ diskimage__internal_access(): fseek() failed"
-			    " on disk id %i \n", d->id);
-			return 0;
-		}
-
-		size_t written = fwrite(buf, 1, len, d->f);
-
-		if (do_fsync)
-			fsync(fileno(d->f));
-
-		return written;
-	}
-
-	if ((len & (OVERLAY_BLOCK_SIZE-1)) != 0) {
-		fatal("TODO: overlay access (write), len not multiple of "
-		    "overlay block size. not yet implemented.\n");
-		fatal("len = %lli\n", (long long) len);
-		abort();
-	}
-	if ((offset & (OVERLAY_BLOCK_SIZE-1)) != 0) {
-		fatal("TODO: unaligned overlay access\n");
-		fatal("offset = %lli\n", (long long) offset);
-		abort();
-	}
-
-	/*  Split the write into OVERLAY_BLOCK_SIZE writes:  */
-	for (curofs = offset; curofs < (off_t) (offset+len);
-	     curofs += OVERLAY_BLOCK_SIZE) {
-		/*  Always write to the last overlay:  */
-		int overlay_nr = d->nr_of_overlays-1;
-		off_t lenwritten;
-		int res = my_fseek(d->overlays[overlay_nr].f_data,
-		    curofs, SEEK_SET);
-		if (res != 0) {
-			fatal("[ diskimage__internal_access(): fseek()"
-			    " failed on disk id %i \n", d->id);
-			return 0;
-		}
-
-		lenwritten = fwrite(buf, 1, OVERLAY_BLOCK_SIZE,
-		    d->overlays[overlay_nr].f_data);
-		buf += OVERLAY_BLOCK_SIZE;
-
-		if (do_fsync)
-			fsync(fileno(d->overlays[overlay_nr].f_data));
-
-		/*  Mark this block in the last overlay as in use:  */
-		overlay_set_block_in_use(d, overlay_nr, curofs);
-	}
-
-	return len;
-}
-
-
-/*
- *  fread_helper():
- *
- *  Internal helper function. Reads from a disk image file, or if the
- *  disk image has overlays, from the last overlay that has the specific
- *  data (or the disk image file itself).
- */
-static size_t fread_helper(off_t offset, unsigned char *buf,
-	size_t len, struct diskimage *d)
-{
-	off_t curofs;
-	size_t totallenread = 0;
-
-	/*  Fast return-path for the case when no overlays are used:  */
-	if (d->nr_of_overlays == 0) {
-		int res = my_fseek(d->f, offset, SEEK_SET);
-		if (res != 0) {
-			fatal("[ diskimage__internal_access(): fseek() failed"
-			    " on disk id %i \n", d->id);
-			return 0;
-		}
-
-		return fread(buf, 1, len, d->f);
-	}
-
-	/*  Split the read into OVERLAY_BLOCK_SIZE reads:  */
-	for (curofs=offset; len != 0;
-	    curofs = (curofs | (OVERLAY_BLOCK_SIZE-1)) + 1) {
-		/*  Find the overlay, if any, that has this block:  */
-		off_t lenread, lentoread;
-		int overlay_nr;
-		for (overlay_nr = d->nr_of_overlays-1;
-		    overlay_nr >= 0; overlay_nr --) {
-			if (overlay_has_block(d, overlay_nr, curofs))
-				break;
-		}
-
-		lentoread = len > OVERLAY_BLOCK_SIZE? OVERLAY_BLOCK_SIZE : len;
-
-		if (overlay_nr >= 0) {
-			/*  Read from overlay:  */
-			int res = my_fseek(d->overlays[overlay_nr].f_data,
-			    curofs, SEEK_SET);
-			if (res != 0) {
-				fatal("[ diskimage__internal_access(): fseek()"
-				    " failed on disk id %i \n", d->id);
-				return 0;
-			}
-			lenread = fread(buf, 1, lentoread,
-			    d->overlays[overlay_nr].f_data);
-		} else {
-			/*  Read from the base disk image:  */
-			int res = my_fseek(d->f, curofs, SEEK_SET);
-			if (res != 0) {
-				fatal("[ diskimage__internal_access(): fseek()"
-				    " failed on disk id %i \n", d->id);
-				return 0;
-			}
-			lenread = fread(buf, 1, lentoread, d->f);
-		}
-
-		if (lenread != lentoread) {
-			fatal("[ INCOMPLETE READ from disk id %i, offset"
-			    " %lli ]\n", d->id, (long long)curofs);
-		}
-
-		len -= lentoread;
-		totallenread += lenread;
-		buf += OVERLAY_BLOCK_SIZE;
-	}
-
-	return totallenread;
-}
-
-
-/*
- *  diskimage__internal_access():
- *
- *  Read from or write to a struct diskimage.
- *
- *  Returns 1 if the access completed successfully, 0 otherwise.
- */
-int diskimage__internal_access(struct diskimage *d, int writeflag,
-	off_t offset, unsigned char *buf, size_t len)
-{
-	ssize_t lendone;
-
-	if (buf == NULL) {
-		fprintf(stderr, "diskimage__internal_access(): buf = NULL\n");
-		exit(1);
-	}
-	if (len == 0)
-		return 1;
-	if (d->f == NULL)
-		return 0;
-
-	if (writeflag) {
-		if (!d->writable)
-			return 0;
-
-		lendone = fwrite_helper(offset, buf, len, d);
-	} else {
-		/*
-		 *  Special case for CD-ROMs. Actually, this is not needed
-		 *  for .iso images, only for physical CDROMS on some OSes,
-		 *  such as FreeBSD.
-		 */
-		if (d->is_a_cdrom)
-			lendone = diskimage_access__cdrom(d, offset, buf, len);
-		else
-			lendone = fread_helper(offset, buf, len, d);
-
-		if (lendone >= 0 && lendone < (ssize_t)len)
-			memset(buf + lendone, 0, len - lendone);
-	}
-
-	/*
-	 *  Incomplete data transfer?
-	 *
-	 *  If we could not read anything at all, then return failure.
-	 *  If we could read a partial block, then return success (with
-	 *  the resulting buffer zero-filled at the end).
-	 */
-	if (lendone <= 0) {
-		fatal("[ diskimage__internal_access(): disk_id %i, offset %lli"
-		    ", transfer not completed. len=%i, len_done=%i ]\n",
-		    d->id, (long long)offset, (int)len, (int)lendone);
-		return 0;
-	}
-
-	return 1;
-}
-
-
-/*
- *  diskimage_access():
- *
- *  Read from or write to a disk image on a machine.
- *
- *  Returns 1 if the access completed successfully, 0 otherwise.
- */
-int diskimage_access(struct machine *machine, int id, int type, int writeflag,
-	off_t offset, unsigned char *buf, size_t len)
-{
-	struct diskimage *d = machine->first_diskimage;
-
-	while (d != NULL) {
-		if (d->type == type && d->id == id)
-			break;
-		d = d->next;
-	}
-
-	if (d == NULL) {
-		fatal("[ diskimage_access(): ERROR: trying to access a "
-		    "non-existant %s disk image (id %i)\n",
-		    diskimage_types[type], id);
-		return 0;
-	}
-
-	offset -= d->override_base_offset;
-	if (offset < 0 && offset + d->override_base_offset >= 0) {
-		debug("[ reading before start of disk image ]\n");
-		/*  Returning zeros.  */
-		memset(buf, 0, len);
-		return 1;
-	}
-
-	return diskimage__internal_access(d, writeflag, offset, buf, len);
-}
-
-
-/*
- *  diskimage_add():
- *
- *  Add a disk image.  fname is the filename of the disk image.
- *  The filename may be prefixed with one or more modifiers, followed
- *  by a colon.
- *
- *	b	specifies that this is a bootable device
- *	c	CD-ROM (instead of a normal DISK)
- *	d	DISK (this is the default)
- *	f	FLOPPY (instead of SCSI)
- *	gH;S;	set geometry (H=heads, S=sectors per track, cylinders are
- *		automatically calculated). (This is ignored for floppies.)
- *	i	IDE (instead of SCSI)
- *	oOFS;	set base offset in bytes, when booting from an ISO9660 fs
- *	r       read-only (don't allow changes to the file)
- *	s	SCSI (this is the default)
- *	t	tape
- *	V	add an overlay to a disk image
- *	0-7	force a specific SCSI ID number
- *
- *  machine is assumed to be non-NULL.
- *  Returns an integer >= 0 identifying the disk image.
- */
-int diskimage_add(struct machine *machine, char *fname)
-{
-	struct diskimage *d, *d2;
-	int id = 0, override_heads=0, override_spt=0;
-	int64_t bytespercyl, override_base_offset=0;
-	char *cp;
-	int prefix_b=0, prefix_c=0, prefix_d=0, prefix_f=0, prefix_g=0;
-	int prefix_i=0, prefix_r=0, prefix_s=0, prefix_t=0, prefix_id=-1;
-	int prefix_o=0, prefix_V=0;
-
-	if (fname == NULL) {
-		fprintf(stderr, "diskimage_add(): NULL ptr\n");
-		return 0;
-	}
-
-	/*  Get prefix from fname:  */
-	cp = strchr(fname, ':');
-	if (cp != NULL) {
-		while (fname <= cp) {
-			char c = *fname++;
-			switch (c) {
-			case '0':
-			case '1':
-			case '2':
-			case '3':
-			case '4':
-			case '5':
-			case '6':
-			case '7':
-				prefix_id = c - '0';
-				break;
-			case 'b':
-				prefix_b = 1;
-				break;
-			case 'c':
-				prefix_c = 1;
-				break;
-			case 'd':
-				prefix_d = 1;
-				break;
-			case 'f':
-				prefix_f = 1;
-				break;
-			case 'g':
-				prefix_g = 1;
-				override_heads = atoi(fname);
-				while (*fname != '\0' && *fname != ';')
-					fname ++;
-				if (*fname == ';')
-					fname ++;
-				override_spt = atoi(fname);
-				while (*fname != '\0' && *fname != ';' &&
-				    *fname != ':')
-					fname ++;
-				if (*fname == ';')
-					fname ++;
-				if (override_heads < 1 ||
-				    override_spt < 1) {
-					fatal("Bad geometry: heads=%i "
-					    "spt=%i\n", override_heads,
-					    override_spt);
-					exit(1);
-				}
-				break;
-			case 'i':
-				prefix_i = 1;
-				break;
-			case 'o':
-				prefix_o = 1;
-				override_base_offset = atoi(fname);
-				while (*fname != '\0' && *fname != ':'
-				    && *fname != ';')
-					fname ++;
-				if (*fname == ':' || *fname == ';')
-					fname ++;
-				if (override_base_offset < 0) {
-					fatal("Bad base offset: %" PRIi64
-					    "\n", override_base_offset);
-					exit(1);
-				}
-				break;
-			case 'r':
-				prefix_r = 1;
-				break;
-			case 's':
-				prefix_s = 1;
-				break;
-			case 't':
-				prefix_t = 1;
-				break;
-			case 'V':
-				prefix_V = 1;
-				break;
-			case ':':
-				break;
-			default:
-				fprintf(stderr, "diskimage_add(): invalid "
-				    "prefix char '%c'\n", c);
-				exit(1);
-			}
-		}
-	}
-
-	/*  Allocate a new diskimage struct:  */
-	CHECK_ALLOCATION(d = (struct diskimage *) malloc(sizeof(struct diskimage)));
-	memset(d, 0, sizeof(struct diskimage));
-
-	/*  Default to IDE disks...  */
-	d->type = DISKIMAGE_IDE;
-
-	/*  ... but some machines use SCSI by default:  */
-	if (machine->machine_type == MACHINE_PMAX ||
-	    machine->machine_type == MACHINE_ARC ||
-	    machine->machine_type == MACHINE_SGI ||
-	    machine->machine_type == MACHINE_MVME88K)
-		d->type = DISKIMAGE_SCSI;
-
-	if (prefix_i + prefix_f + prefix_s > 1) {
-		fprintf(stderr, "Invalid disk image prefix(es). You can"
-		    "only use one of i, f, and s\nfor each disk image.\n");
-		exit(1);
-	}
-
-	if (prefix_i)
-		d->type = DISKIMAGE_IDE;
-	if (prefix_f)
-		d->type = DISKIMAGE_FLOPPY;
-	if (prefix_s)
-		d->type = DISKIMAGE_SCSI;
-
-	/*  Special case: Add an overlay for an already added disk image:  */
-	if (prefix_V) {
-		struct diskimage *dx = machine->first_diskimage;
-
-		if (prefix_id < 0) {
-			fprintf(stderr, "The 'V' disk image prefix requires"
-			    " a disk ID to also be supplied.\n");
-			exit(1);
-		}
-
-		while (dx != NULL) {
-			if (d->type == dx->type && prefix_id == dx->id)
-				break;
-			dx = dx->next;
-		}
-
-		if (dx == NULL) {
-			fprintf(stderr, "Bad ID supplied for overlay?\n");
-			exit(1);
-		}
-
-		diskimage_add_overlay(dx, fname);
-
-		/*  Free the preliminary d struct:  */
-		free(d);
-
-		/*  Don't add any disk image. This is an overlay!  */
-		return -1;
-	}
-
-	/*  Add the new disk image in the disk image chain:  */
-	d2 = machine->first_diskimage;
-	if (d2 == NULL) {
-		machine->first_diskimage = d;
-	} else {
-		while (d2->next != NULL)
-			d2 = d2->next;
-		d2->next = d;
-	}
-
-	if (prefix_o)
-		d->override_base_offset = override_base_offset;
-
-	CHECK_ALLOCATION(d->fname = strdup(fname));
-
-	d->logical_block_size = 512;
-
-	/*
-	 *  Is this a tape, CD-ROM or a normal disk?
-	 *
-	 *  An intelligent guess, if no prefixes are used, would be that
-	 *  filenames ending with .iso or .cdr are CD-ROM images.
-	 */
-	if (prefix_t) {
-		d->is_a_tape = 1;
-	} else {
-		if (prefix_c ||
-		    ((strlen(d->fname) > 4 &&
-		    (strcasecmp(d->fname + strlen(d->fname) - 4, ".cdr") == 0 ||
-		    strcasecmp(d->fname + strlen(d->fname) - 4, ".iso") == 0))
-		    && !prefix_d)
-		   ) {
-			d->is_a_cdrom = 1;
-
-			/*
-			 *  This is tricky. Should I use 512 or 2048 here?
-			 *  NetBSD/pmax 1.6.2 and Ultrix likes 512 bytes
-			 *  per sector, but NetBSD 2.0_BETA suddenly ignores
-			 *  this value and uses 2048 instead.
-			 *
-			 *  OpenBSD/arc doesn't like 2048, it requires 512
-			 *  to work correctly.
-			 *
-			 *  TODO
-			 */
-
-#if 0
-			if (machine->machine_type == MACHINE_PMAX)
-				d->logical_block_size = 512;
-			else
-				d->logical_block_size = 2048;
-#endif
-			d->logical_block_size = 512;
-		}
-	}
-
-	diskimage_recalc_size(d);
-
-	if ((d->total_size == 720*1024 || d->total_size == 1474560
-	    || d->total_size == 2949120 || d->total_size == 1228800)
-	    && !prefix_i && !prefix_s)
-		d->type = DISKIMAGE_FLOPPY;
-
-	switch (d->type) {
-	case DISKIMAGE_FLOPPY:
-		if (d->total_size < 737280) {
-			fatal("\nTODO: small (non-80-cylinder) floppies?\n\n");
-			exit(1);
-		}
-		d->cylinders = 80;
-		d->heads = 2;
-		d->sectors_per_track = d->total_size / (d->cylinders *
-		    d->heads * 512);
-		break;
-	default:/*  Non-floppies:  */
-		d->heads = 16;
-		d->sectors_per_track = 63;
-		if (prefix_g) {
-			d->chs_override = 1;
-			d->heads = override_heads;
-			d->sectors_per_track = override_spt;
-		}
-		bytespercyl = d->heads * d->sectors_per_track * 512;
-		d->cylinders = d->total_size / bytespercyl;
-		if (d->cylinders * bytespercyl < d->total_size)
-			d->cylinders ++;
-	}
-
-	d->rpms = 3600;
-
-	if (prefix_b)
-		d->is_boot_device = 1;
-
-	d->writable = access(fname, W_OK) == 0? 1 : 0;
-
-	if (d->is_a_cdrom || prefix_r) {
-		d->writable = 0;
-	} else {
-		if (!d->writable) {
-			debug("NOTE: '%s' is read-only in the host file system, but 'r:' was not used.\n\n", d->fname);
-		}
-	}
-
-	d->f = fopen(fname, d->writable? "r+" : "r");
-	if (d->f == NULL) {
-		char *errmsg = (char *) malloc(200 + strlen(fname));
-		snprintf(errmsg, 200+strlen(fname),
-		    "could not fopen %s for reading%s", fname,
-		    d->writable? " and writing" : "");
-		perror(errmsg);
-		exit(1);
-	}
-
-	/*  Calculate which ID to use:  */
-	if (prefix_id == -1) {
-		int free = 0, collision = 1;
-
-		while (collision) {
-			collision = 0;
-			d2 = machine->first_diskimage;
-			while (d2 != NULL) {
-				/*  (don't compare against ourselves :)  */
-				if (d2 == d) {
-					d2 = d2->next;
-					continue;
-				}
-				if (d2->id == free && d2->type == d->type) {
-					collision = 1;
-					break;
-				}
-				d2 = d2->next;
-			}
-			if (!collision)
-				id = free;
-			else
-				free ++;
-		}
-	} else {
-		id = prefix_id;
-		d2 = machine->first_diskimage;
-		while (d2 != NULL) {
-			/*  (don't compare against ourselves :)  */
-			if (d2 == d) {
-				d2 = d2->next;
-				continue;
-			}
-			if (d2->id == id && d2->type == d->type) {
-				fprintf(stderr, "disk image id %i "
-				    "already in use\n", id);
-				exit(1);
-			}
-			d2 = d2->next;
-		}
-	}
-
-	d->id = id;
-
-	return id;
-}
-
-
-/*
- *  diskimage_bootdev():
- *
- *  Returns the disk id of the device which we're booting from.  If typep is
- *  non-NULL, the type is returned as well.
- *
- *  If no disk was used as boot device, then -1 is returned. (In practice,
- *  this is used to fake network (tftp) boot.)
- */
-int diskimage_bootdev(struct machine *machine, int *typep)
-{
-	struct diskimage *d;
-
-	d = machine->first_diskimage;
-	while (d != NULL) {
-		if (d->is_boot_device) {
-			if (typep != NULL)
-				*typep = d->type;
-			return d->id;
-		}
-		d = d->next;
-	}
-
-	d = machine->first_diskimage;
-	if (d != NULL) {
-		if (typep != NULL)
-			*typep = d->type;
-		return d->id;
-	}
-
-	return -1;
-}
-
-
-/*
- *  diskimage_getname():
- *
- *  Returns 1 if a valid disk image name was returned, 0 otherwise.
- */
-int diskimage_getname(struct machine *machine, int id, int type,
-	char *buf, size_t bufsize)
-{
-	struct diskimage *d = machine->first_diskimage;
-
-	if (buf == NULL)
-		return 0;
-
-	while (d != NULL) {
-		if (d->type == type && d->id == id) {
-			char *p = strrchr(d->fname, '/');
-			if (p == NULL)
-				p = d->fname;
-			else
-				p ++;
-			snprintf(buf, bufsize, "%s", p);
-			return 1;
-		}
-		d = d->next;
-	}
-	return 0;
-}
-
-
-/*
- *  diskimage_is_a_cdrom():
- *
- *  Returns 1 if a disk image is a CDROM, 0 otherwise.
- */
-int diskimage_is_a_cdrom(struct machine *machine, int id, int type)
-{
-	struct diskimage *d = machine->first_diskimage;
-
-	while (d != NULL) {
-		if (d->type == type && d->id == id)
-			return d->is_a_cdrom;
-		d = d->next;
-	}
-	return 0;
-}
-
-
-/*
- *  diskimage_is_a_tape():
- *
- *  Returns 1 if a disk image is a tape, 0 otherwise.
- *
- *  (Used in src/machine.c, to select 'rz' vs 'tz' for DECstation
- *  boot strings.)
- */
-int diskimage_is_a_tape(struct machine *machine, int id, int type)
-{
-	struct diskimage *d = machine->first_diskimage;
-
-	while (d != NULL) {
-		if (d->type == type && d->id == id)
-			return d->is_a_tape;
-		d = d->next;
-	}
-	return 0;
-}
-
-
-/*
- *  diskimage_dump_info():
- *
- *  Debug dump of all diskimages that are loaded for a specific machine.
- */
-void diskimage_dump_info(struct machine *machine)
-{
-	int i, iadd = DEBUG_INDENTATION;
-	struct diskimage *d = machine->first_diskimage;
-
-	while (d != NULL) {
-		debug("diskimage: %s\n", d->fname);
-		debug_indentation(iadd);
-
-		switch (d->type) {
-		case DISKIMAGE_SCSI:
-			debug("SCSI");
-			break;
-		case DISKIMAGE_IDE:
-			debug("IDE");
-			break;
-		case DISKIMAGE_FLOPPY:
-			debug("FLOPPY");
-			break;
-		default:
-			debug("UNKNOWN type %i", d->type);
-		}
-
-		debug(" %s", d->is_a_tape? "TAPE" :
-			(d->is_a_cdrom? "CD-ROM" : "DISK"));
-		debug(" id %i, ", d->id);
-		debug("%s, ", d->writable? "read/write" : "read-only");
-
-		if (d->type == DISKIMAGE_FLOPPY)
-			debug("%lli KB", (long long) (d->total_size / 1024));
-		else
-			debug("%lli MB", (long long) (d->total_size / 1048576));
-
-		if (d->type == DISKIMAGE_FLOPPY || d->chs_override)
-			debug(" (CHS=%i,%i,%i)", d->cylinders, d->heads,
-			    d->sectors_per_track);
-		else
-			debug(" (%lli sectors)", (long long)
-			   (d->total_size / 512));
-
-		if (d->is_boot_device)
-			debug(" (BOOT)");
-		debug("\n");
-
-		for (i=0; i<d->nr_of_overlays; i++) {
-			debug("overlay %i: %s\n",
-			    i, d->overlays[i].overlay_basename);
-		}
-
-		debug_indentation(-iadd);
-
-		d = d->next;
-	}
-}
-
diff -Nru gxemul-0.6.2/src/disk/diskimage_scsicmd.c gxemul-0.7.0+dfsg/src/disk/diskimage_scsicmd.c
--- gxemul-0.6.2/src/disk/diskimage_scsicmd.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/disk/diskimage_scsicmd.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1152 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Disk image support: SCSI command emulation.
+ *
+ *  TODO:  There are LOTS of ugly magic values in this module. These should
+ *         be replaced by proper defines.
+ *
+ *  TODO:  scsi_transfer_free could save away previous allocations, and
+ *         scsi_transfer_allocbuf could reuse them (for given sizes).
+ *
+ *  TODO:  There's probably a bug in the tape support:
+ *         Let's say there are 10240 bytes left in a file, and 10240
+ *         bytes are read. Then feof() is not true yet (?), so the next
+ *         read will also return 10240 bytes (but all zeroes), and then after
+ *         that return feof (which results in a filemark).  This is probably
+ *         trivial to fix, but I don't feel like it right now.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "cpu.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "misc.h"
+
+
+static const char *diskimage_types[] = DISKIMAGE_TYPES;
+static struct scsi_transfer *first_free_scsi_transfer_alloc = NULL;
+
+
+/*
+ *  scsi_transfer_alloc():
+ *
+ *  Allocates memory for a new scsi_transfer struct, and fills it with
+ *  sane data (NULL pointers).
+ *  The return value is a pointer to the new struct.  If allocation
+ *  failed, the program exits.
+ */
+struct scsi_transfer *scsi_transfer_alloc(void)
+{
+	struct scsi_transfer *p;
+
+	if (first_free_scsi_transfer_alloc != NULL) {
+		p = first_free_scsi_transfer_alloc;
+		first_free_scsi_transfer_alloc = p->next_free;
+	} else {
+		p = (struct scsi_transfer *) malloc(sizeof(struct scsi_transfer));
+		if (p == NULL) {
+			fprintf(stderr, "scsi_transfer_alloc(): out "
+			    "of memory\n");
+			exit(1);
+		}
+	}
+
+	memset(p, 0, sizeof(struct scsi_transfer));
+
+	return p;
+}
+
+
+/*
+ *  scsi_transfer_free():
+ *
+ *  Frees the space used by a scsi_transfer struct.  All buffers refered
+ *  to by the scsi_transfer struct are freed.
+ */
+void scsi_transfer_free(struct scsi_transfer *p)
+{
+	if (p == NULL) {
+		fprintf(stderr, "scsi_transfer_free(): p == NULL\n");
+		exit(1);
+	}
+
+	if (p->msg_out != NULL)
+		free(p->msg_out);
+	if (p->cmd != NULL)
+		free(p->cmd);
+	if (p->data_out != NULL)
+		free(p->data_out);
+
+	if (p->data_in != NULL)
+		free(p->data_in);
+	if (p->msg_in != NULL)
+		free(p->msg_in);
+	if (p->status != NULL)
+		free(p->status);
+
+	p->next_free = first_free_scsi_transfer_alloc;
+	first_free_scsi_transfer_alloc = p;
+}
+
+
+/*
+ *  scsi_transfer_allocbuf():
+ *
+ *  Helper function, used by diskimage_scsicommand(), and SCSI controller
+ *  devices.  Example of usage:
+ *
+ *	scsi_transfer_allocbuf(&xferp->msg_in_len, &xferp->msg_in, 1);
+ */
+void scsi_transfer_allocbuf(size_t *lenp, unsigned char **pp, size_t want_len,
+	int clearflag)
+{
+	unsigned char *p = (*pp);
+
+	if (p != NULL) {
+		debugmsg(SUBSYS_DISK, "scsi", VERBOSITY_WARNING,
+		    "WARNING! scsi_transfer_allocbuf(): old pointer "
+		    "was not NULL, freeing it now");
+		free(p);
+	}
+
+	(*lenp) = want_len;
+	if ((p = (unsigned char *) malloc(want_len)) == NULL) {
+		debugmsg(SUBSYS_DISK, "scsi", VERBOSITY_ERROR,
+		    "scsi_transfer_allocbuf(): out of "
+		    "memory trying to allocate %li bytes", (long)want_len);
+		exit(1);
+	}
+
+	if (clearflag)
+		memset(p, 0, want_len);
+
+	(*pp) = p;
+}
+
+
+/**************************************************************************/
+
+
+/*
+ *  diskimage__return_default_status_and_message():
+ *
+ *  Set the status and msg_in parts of a scsi_transfer struct
+ *  to default values (msg_in = 0x00, status = 0x00).
+ */
+static void diskimage__return_default_status_and_message(
+	struct scsi_transfer *xferp)
+{
+	scsi_transfer_allocbuf(&xferp->status_len, &xferp->status, 1, 0);
+	xferp->status[0] = 0x00;
+	scsi_transfer_allocbuf(&xferp->msg_in_len, &xferp->msg_in, 1, 0);
+	xferp->msg_in[0] = 0x00;
+}
+
+
+/*
+ *  diskimage__switch_tape():
+ *
+ *  Used by the SPACE command.  (d is assumed to be non-NULL.)
+ */
+static void diskimage__switch_tape(struct diskimage *d)
+{
+	char tmpfname[1000];
+
+	snprintf(tmpfname, sizeof(tmpfname), "%s.%i",
+	    d->fname, d->tape_filenr);
+	tmpfname[sizeof(tmpfname)-1] = '\0';
+
+	if (d->f != NULL)
+		fclose(d->f);
+
+	d->f = fopen(tmpfname, d->writable? "r+" : "r");
+	if (d->f == NULL) {
+		debugmsg(SUBSYS_DISK, "scsi", VERBOSITY_ERROR,
+		    "diskimage__switch_tape(): could not "
+		    "(re)open '%s'", tmpfname);
+
+		/*  TODO: return error  */
+	}
+	d->tape_offset = 0;
+}
+
+
+/**************************************************************************/
+
+
+/*
+ *  diskimage_scsicommand():
+ *
+ *  Perform a SCSI command on a disk image.
+ *
+ *  The xferp points to a scsi_transfer struct, containing msg_out, command,
+ *  and data_out coming from the SCSI controller device.  This function
+ *  interprets the command, and (if necessary) creates responses in
+ *  data_in, msg_in, and status.
+ *
+ *  Returns:
+ *	2 if the command expects data from the DATA_OUT phase,
+ *	1 if otherwise ok,
+ *	0 on error.
+ */
+int diskimage_scsicommand(struct cpu *cpu, int id, int type,
+	struct scsi_transfer *xferp)
+{
+	char namebuf[16];
+	int retlen, i, q;
+	uint64_t size;
+	int64_t ofs;
+	int pagecode;
+	struct machine *machine = cpu->machine;
+	struct diskimage *d;
+
+	if (machine == NULL) {
+		debugmsg_cpu(cpu, SUBSYS_DISK, "scsi",
+		    VERBOSITY_ERROR, "machine == NULL");
+		return 0;
+	}
+
+	d = machine->first_diskimage;
+	while (d != NULL) {
+		if (d->type == type && d->id == id)
+			break;
+		d = d->next;
+	}
+
+	if (xferp->cmd == NULL) {
+		debugmsg_cpu(cpu, SUBSYS_DISK, "scsi",
+		    VERBOSITY_ERROR, "cmd == NULL");
+		return 0;
+	}
+
+	if (xferp->cmd_len < 1) {
+		debugmsg_cpu(cpu, SUBSYS_DISK, "scsi",
+		    VERBOSITY_ERROR, "cmd_len = %i",
+		    xferp->cmd_len);
+		return 0;
+	}
+
+	if (d == NULL) {
+		debugmsg_cpu(cpu, SUBSYS_DISK, "scsi",
+		    VERBOSITY_INFO, "%s id %i not connected!",
+		    diskimage_types[type], id);
+
+		// TODO: How to return suitable error?
+		diskimage__return_default_status_and_message(xferp);
+		xferp->status[0] = 0x02;	// ?
+		return 0;
+	}
+
+	// TODO: debugmsg:ify the rest of the debug messages...
+	debug("[ diskimage_scsicommand(id=%i) cmd=0x%02x: ", id, xferp->cmd[0]);
+
+#if 0
+	fatal("[ diskimage_scsicommand(id=%i) cmd=0x%02x len=%i:",
+	    id, xferp->cmd[0], xferp->cmd_len);
+	for (i=0; i<xferp->cmd_len; i++)
+		fatal(" %02x", xferp->cmd[i]);
+	fatal("\n");
+if (xferp->cmd_len > 7 && xferp->cmd[5] == 0x11)
+	single_step = true;
+#endif
+
+	switch (xferp->cmd[0]) {
+
+	case SCSICMD_TEST_UNIT_READY:
+		debug("TEST_UNIT_READY");
+		if (xferp->cmd_len != 6)
+			debug(" (weird len=%i)", xferp->cmd_len);
+
+		/*  TODO: bits 765 of buf[1] contains the LUN  */
+		if (xferp->cmd[1] != 0x00)
+			debugmsg(SUBSYS_DISK, "scsi", VERBOSITY_WARNING,
+			    "WARNING: TEST_UNIT_READY with cmd[1]=0x%02x"
+			    " not yet implemented", (int)xferp->cmd[1]);
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICMD_INQUIRY:
+		debug("INQUIRY");
+		if (xferp->cmd_len != 6)
+			debug(" (weird len=%i)", xferp->cmd_len);
+		if (xferp->cmd[1] != 0x00) {
+			debugmsg(SUBSYS_DISK, "scsi", VERBOSITY_WARNING,
+			    "WARNING: INQUIRY with cmd[1]=0x%02x not yet "
+			    "implemented", (int)xferp->cmd[1]);
+		}
+
+		/*  Return values:  */
+		retlen = xferp->cmd[4];
+		if (retlen < 36) {
+			debugmsg(SUBSYS_DISK, "scsi", VERBOSITY_WARNING,
+			    "WARNING: SCSI inquiry len=%i, <36!", retlen);
+			retlen = 36;
+		}
+
+		/*  Return data:  */
+		scsi_transfer_allocbuf(&xferp->data_in_len, &xferp->data_in,
+		    retlen, 1);
+		xferp->data_in[0] = 0x00;  /*  0x00 = Direct-access disk  */
+		xferp->data_in[1] = 0x00;  /*  0x00 = non-removable  */
+		xferp->data_in[2] = 0x02;  /*  SCSI-2  */
+#if 0
+xferp->data_in[3] = 0x02;	/*  Response data format = SCSI-2  */
+#endif
+		xferp->data_in[4] = retlen - 4;	/*  Additional length  */
+xferp->data_in[4] = 0x2c - 4;	/*  Additional length  */
+		xferp->data_in[6] = 0x04;  /*  ACKREQQ  */
+		xferp->data_in[7] = 0x60;  /*  WBus32, WBus16  */
+
+		/*  These are padded with spaces:  */
+
+		memcpy(xferp->data_in+8,  "GXemul  ", 8);
+		if (diskimage_getname(cpu->machine, id,
+		    type, namebuf, sizeof(namebuf))) {
+			for (size_t j=0; j<sizeof(namebuf); j++) {
+				if (namebuf[j] == 0) {
+					for (; j<sizeof(namebuf); j++)
+						namebuf[j] = ' ';
+					break;
+				}
+			}
+			
+			memcpy(xferp->data_in+16, namebuf, 16);
+		} else
+			memcpy(xferp->data_in+16, "DISK            ", 16);
+		memcpy(xferp->data_in+32, "0   ", 4);
+
+		/*
+		 *  Some Ultrix kernels want specific responses from
+		 *  the drives.
+		 */
+
+		if (machine->machine_type == MACHINE_PMAX) {
+			/*  DEC, RZ25 (rev 0900) = 832527 sectors  */
+			/*  DEC, RZ58 (rev 2000) = 2698061 sectors  */
+			memcpy(xferp->data_in+8,  "DEC     ", 8);
+			memcpy(xferp->data_in+16, "RZ58     (C) DEC", 16);
+			memcpy(xferp->data_in+32, "2000", 4);
+		}
+
+		/*  Some data is different for CD-ROM drives:  */
+		if (d->is_a_cdrom) {
+			xferp->data_in[0] = 0x05;  /*  0x05 = CD-ROM  */
+			xferp->data_in[1] = 0x80;  /*  0x80 = removable  */
+			/*  memcpy(xferp->data_in+16, "CD-ROM          ", 16);*/
+
+			if (machine->machine_type == MACHINE_PMAX) {
+				/*  SONY, CD-ROM:  */
+				memcpy(xferp->data_in+8, "SONY    ", 8);
+				memcpy(xferp->data_in+16,
+				    "CD-ROM          ", 16);
+
+				/*  ... or perhaps this:  */
+				memcpy(xferp->data_in+8, "DEC     ", 8);
+				memcpy(xferp->data_in+16,
+				    "RRD42   (C) DEC ", 16);
+				memcpy(xferp->data_in+32, "4.5d", 4);
+			} else if (machine->machine_type == MACHINE_ARC) {
+				/*  NEC, CD-ROM:  */
+				memcpy(xferp->data_in+8, "NEC     ", 8);
+				memcpy(xferp->data_in+16,
+				    "CD-ROM CDR-210P ", 16);
+				memcpy(xferp->data_in+32, "1.0 ", 4);
+			}
+		}
+
+		/*  Data for tape devices:  */
+		if (d->is_a_tape) {
+			xferp->data_in[0] = 0x01;  /*  0x01 = tape  */
+			xferp->data_in[1] = 0x80;  /*  0x80 = removable  */
+			memcpy(xferp->data_in+16, "TAPE            ", 16);
+
+			if (machine->machine_type == MACHINE_PMAX) {
+				/*
+				 *  TODO:  find out if these are correct.
+				 *
+				 *  The name might be TZK10, TSZ07, or TLZ04,
+				 *  or something completely different.
+				 */
+				memcpy(xferp->data_in+8, "DEC     ", 8);
+				memcpy(xferp->data_in+16,
+				    "TK50     (C) DEC", 16);
+				memcpy(xferp->data_in+32, "2000", 4);
+			}
+		}
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSIBLOCKCMD_READ_CAPACITY:
+		debug("READ_CAPACITY");
+
+		if (xferp->cmd_len != 10)
+			fatal(" [ weird READ_CAPACITY len=%i, should be 10 ] ",
+			    xferp->cmd_len);
+		else {
+			if (xferp->cmd[8] & 1) {
+				/*  Partial Medium Indicator bit...  TODO  */
+				fatal("WARNING: READ_CAPACITY with PMI bit"
+				    " set not yet implemented\n");
+			}
+		}
+
+		/*  Return data:  */
+		scsi_transfer_allocbuf(&xferp->data_in_len, &xferp->data_in,
+		    8, 1);
+
+		diskimage_recalc_size(d);
+
+		size = d->nr_of_logical_blocks - 1;
+
+		xferp->data_in[0] = (size >> 24) & 255;
+		xferp->data_in[1] = (size >> 16) & 255;
+		xferp->data_in[2] = (size >> 8) & 255;
+		xferp->data_in[3] = size & 255;
+
+		xferp->data_in[4] = (d->logical_block_size >> 24) & 255;
+		xferp->data_in[5] = (d->logical_block_size >> 16) & 255;
+		xferp->data_in[6] = (d->logical_block_size >> 8) & 255;
+		xferp->data_in[7] = d->logical_block_size & 255;
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICMD_MODE_SENSE:
+	case SCSICMD_MODE_SENSE10:	
+		debug("MODE_SENSE");
+		q = 4; retlen = xferp->cmd[4];
+		switch (xferp->cmd_len) {
+		case 6:	break;
+		case 10:q = 8;
+			retlen = xferp->cmd[7] * 256 + xferp->cmd[8];
+			break;
+		default:fatal(" (unimplemented mode_sense len=%i)",
+			    xferp->cmd_len);
+		}
+
+		/*
+		 *  NOTE/TODO: This code doesn't handle too short retlens
+		 *  very well. A quick hack around this is that I allocate
+		 *  a bit too much memory, so that nothing is actually
+		 *  written outside of xferp->data_in[].
+		 */
+
+		retlen += 100;		/*  Should be enough. (Ugly.)  */
+
+		if ((xferp->cmd[2] & 0xc0) != 0)
+			fatal("WARNING: mode sense, cmd[2] = 0x%02x\n",
+			    xferp->cmd[2]);
+
+		/*  Return data:  */
+		scsi_transfer_allocbuf(&xferp->data_in_len,
+		    &xferp->data_in, retlen, 1);
+
+		xferp->data_in_len -= 100;	/*  Restore size.  */
+
+		pagecode = xferp->cmd[2] & 0x3f;
+
+		debug("[ MODE SENSE id %i, pagecode=%i ]\n", id, pagecode);
+
+		/*  4 bytes of header for 6-byte command,
+		    8 bytes of header for 10-byte command.  */
+		xferp->data_in[0] = retlen;	/*  0: mode data length  */
+		xferp->data_in[1] = d->is_a_cdrom? 0x05 : 0x00;
+				/*  1: medium type  */
+		xferp->data_in[2] = 0x00;	/*  device specific
+						    parameter  */
+		xferp->data_in[3] = 8 * 1;	/*  block descriptor
+						    length: 1 page (?)  */
+
+		xferp->data_in[q+0] = 0x00;	/*  density code  */
+		xferp->data_in[q+1] = 0;	/*  nr of blocks, high  */
+		xferp->data_in[q+2] = 0;	/*  nr of blocks, mid  */
+		xferp->data_in[q+3] = 0;	/*  nr of blocks, low */
+		xferp->data_in[q+4] = 0x00;	/*  reserved  */
+		xferp->data_in[q+5] = (d->logical_block_size >> 16) & 255;
+		xferp->data_in[q+6] = (d->logical_block_size >> 8) & 255;
+		xferp->data_in[q+7] = d->logical_block_size & 255;
+		q += 8;
+
+		diskimage__return_default_status_and_message(xferp);
+
+		/*  descriptors, 8 bytes (each)  */
+
+		/*  page, n bytes (each)  */
+		switch (pagecode) {
+		case 0:
+			/*  TODO: Nothing here?  */
+			break;
+		case 1:		/*  read-write error recovery page  */
+			xferp->data_in[q + 0] = pagecode;
+			xferp->data_in[q + 1] = 10;
+			break;
+		case 3:		/*  format device page  */
+			xferp->data_in[q + 0] = pagecode;
+			xferp->data_in[q + 1] = 22;
+
+			/*  10,11 = sectors per track  */
+			xferp->data_in[q + 10] = 0;
+			xferp->data_in[q + 11] = d->sectors_per_track;
+
+			/*  12,13 = physical sector size  */
+			xferp->data_in[q + 12] =
+			    (d->logical_block_size >> 8) & 255;
+			xferp->data_in[q + 13] = d->logical_block_size & 255;
+			break;
+		case 4:		/*  rigid disk geometry page  */
+			xferp->data_in[q + 0] = pagecode;
+			xferp->data_in[q + 1] = 22;
+			xferp->data_in[q + 2] = (d->cylinders >> 16) & 255;
+			xferp->data_in[q + 3] = (d->cylinders >> 8) & 255;
+			xferp->data_in[q + 4] = d->cylinders & 255;
+			xferp->data_in[q + 5] = d->heads;
+			xferp->data_in[q + 20] = (d->rpms >> 8) & 255;
+			xferp->data_in[q + 21] = d->rpms & 255;
+			break;
+		case 5:		/*  flexible disk page  */
+			xferp->data_in[q + 0] = pagecode;
+			xferp->data_in[q + 1] = 0x1e;
+
+			/*  2,3 = transfer rate  */
+			xferp->data_in[q + 2] = ((5000) >> 8) & 255;
+			xferp->data_in[q + 3] = (5000) & 255;
+
+			xferp->data_in[q + 4] = d->heads;
+			xferp->data_in[q + 5] = d->sectors_per_track;
+
+			/*  6,7 = data bytes per sector  */
+			xferp->data_in[q + 6] = (d->logical_block_size >> 8)
+			    & 255;
+			xferp->data_in[q + 7] = d->logical_block_size & 255;
+
+			xferp->data_in[q + 8] = (d->cylinders >> 8) & 255;
+			xferp->data_in[q + 9] = d->cylinders & 255;
+
+			xferp->data_in[q + 28] = (d->rpms >> 8) & 255;
+			xferp->data_in[q + 29] = d->rpms & 255;
+			break;
+		default:
+			debugmsg(SUBSYS_DISK, "scsi", VERBOSITY_WARNING,
+			    "MODE_SENSE for page %i is not yet "
+			    "implemented!", pagecode);
+		}
+
+		break;
+
+	case SCSICMD_READ:
+	case SCSICMD_READ_10:
+		debug("READ");
+
+		/*
+		 *  For tape devices, read data at the current position.
+		 *  For disk and CDROM devices, the command bytes contain
+		 *  an offset telling us where to read from the device.
+		 */
+
+		if (d->is_a_tape) {
+			/*  bits 7..5 of cmd[1] are the LUN bits... TODO  */
+
+			size = (xferp->cmd[2] << 16) +
+			       (xferp->cmd[3] <<  8) +
+				xferp->cmd[4];
+
+			/*  Bit 1 of cmd[1] is the SILI bit (TODO), and
+			    bit 0 is the "use fixed length" bit.  */
+
+			if (xferp->cmd[1] & 0x01) {
+				/*  Fixed block length:  */
+				size *= d->logical_block_size;
+			}
+
+			if (d->filemark) {
+				/*  At end of file, switch to the next
+				    automagically:  */
+				d->tape_filenr ++;
+				diskimage__switch_tape(d);
+
+				d->filemark = 0;
+			}
+
+			ofs = d->tape_offset;
+
+			fatal("[ READ tape, id=%i file=%i, cmd[1]=%02x size=%i"
+			    ", ofs=%lli ]\n", id, d->tape_filenr,
+			    xferp->cmd[1], (int)size, (long long)ofs);
+		} else {
+			if (xferp->cmd[0] == SCSICMD_READ) {
+				if (xferp->cmd_len != 6)
+					debug(" (weird len=%i)",
+					    xferp->cmd_len);
+
+				/*
+				 *  bits 4..0 of cmd[1], and cmd[2] and cmd[3]
+				 *  hold the logical block address.
+				 *
+				 *  cmd[4] holds the number of logical blocks
+				 *  to transfer. (Special case if the value is
+				 *  0, actually means 256.)
+				 */
+				ofs = ((xferp->cmd[1] & 0x1f) << 16) +
+				      (xferp->cmd[2] << 8) + xferp->cmd[3];
+				retlen = xferp->cmd[4];
+				if (retlen == 0)
+					retlen = 256;
+			} else {
+				if (xferp->cmd_len != 10)
+					debug(" (weird len=%i)",
+					    xferp->cmd_len);
+
+				/*
+				 *  cmd[2..5] hold the logical block address.
+				 *  cmd[7..8] holds the number of logical
+				 *  blocks to transfer. (NOTE: If the value is
+				 *  0, this means 0, not 65536. :-)
+				 */
+				ofs = ((uint64_t)xferp->cmd[2] << 24) +
+				    (xferp->cmd[3] << 16) + (xferp->cmd[4] << 8)
+				    + xferp->cmd[5];
+				retlen = (xferp->cmd[7] << 8) + xferp->cmd[8];
+			}
+
+			size = retlen * d->logical_block_size;
+			ofs *= d->logical_block_size;
+		}
+
+		/*  Return data:  */
+		scsi_transfer_allocbuf(&xferp->data_in_len, &xferp->data_in,
+		    size, 0);
+
+		debug(" READ  ofs=%lli size=%i\n", (long long)ofs, (int)size);
+
+		diskimage__return_default_status_and_message(xferp);
+
+		d->filemark = 0;
+
+		/*
+		 *  Failure? Then set check condition.
+		 *  For tapes, error should only occur at the end of a file.
+		 *
+		 *  "If the logical unit encounters a filemark during
+		 *   a READ command, CHECK CONDITION status shall be
+		 *   returned and the filemark and valid bits shall be
+		 *   set to one in the sense data. The sense key shall
+		 *   be set to NO SENSE"..
+		 */
+		if (d->is_a_tape && d->f != NULL && feof(d->f)) {
+			debug(" feof id=%i\n", id);
+			xferp->status[0] = 0x02;	/*  CHECK CONDITION  */
+
+			d->filemark = 1;
+		} else {
+			/* int result = */  diskimage__internal_access(d, 0, ofs, xferp->data_in, size);
+		}
+
+		if (d->is_a_tape && d->f != NULL)
+			d->tape_offset = ftello(d->f);
+
+		/*  TODO: other errors?  */
+		break;
+
+	case SCSICMD_WRITE:
+	case SCSICMD_WRITE_10:
+		debug("WRITE");
+
+		/*  TODO: tape  */
+
+		if (xferp->cmd[0] == SCSICMD_WRITE) {
+			if (xferp->cmd_len != 6)
+				debug(" (weird len=%i)", xferp->cmd_len);
+
+			/*
+			 *  bits 4..0 of cmd[1], and cmd[2] and cmd[3] hold the
+			 *  logical block address.
+			 *
+			 *  cmd[4] holds the number of logical blocks to
+			 *  transfer. (Special case if the value is 0, actually
+			 *  means 256.)
+			 */
+			ofs = ((xferp->cmd[1] & 0x1f) << 16) +
+			      (xferp->cmd[2] << 8) + xferp->cmd[3];
+			retlen = xferp->cmd[4];
+			if (retlen == 0)
+				retlen = 256;
+		} else {
+			if (xferp->cmd_len != 10)
+				debug(" (weird len=%i)", xferp->cmd_len);
+
+			/*
+			 *  cmd[2..5] hold the logical block address.
+			 *  cmd[7..8] holds the number of logical blocks to
+			 *  transfer. (NOTE: If the value is 0 this means 0,
+			 *  not 65536.)
+			 */
+			ofs = ((uint64_t)xferp->cmd[2] << 24) +
+			    (xferp->cmd[3] << 16) + (xferp->cmd[4] << 8) +
+			    xferp->cmd[5];
+			retlen = (xferp->cmd[7] << 8) + xferp->cmd[8];
+		}
+
+		size = retlen * d->logical_block_size;
+		ofs *= d->logical_block_size;
+
+		if (xferp->data_out_offset != size) {
+			debug(", data_out == NULL, wanting %i bytes, \n\n",
+			    (int)size);
+			xferp->data_out_len = size;
+			return 2;
+		}
+
+		debug("WRITE ofs=%i size=%i offset=%i\n", (int)ofs,
+		    (int)size, (int)xferp->data_out_offset);
+
+		/*  int result = */  diskimage__internal_access(d, 1, ofs, xferp->data_out, size);
+
+		/*  TODO: how about return code?  */
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICMD_SYNCHRONIZE_CACHE:
+		debug("SYNCHRONIZE_CACHE");
+
+		if (xferp->cmd_len != 10)
+			debug(" (weird len=%i)", xferp->cmd_len);
+
+		/*  TODO: actualy care about cmd[]  */
+		/*  TODO: Move to diskimage.cc and make sure that both
+			d->f is fsynced AND any overlays and overlay bitmap
+			files are fsynced too!  */
+		fsync(fileno(d->f));
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICMD_START_STOP_UNIT:
+		debug("START_STOP_UNIT");
+
+		if (xferp->cmd_len != 6)
+			debug(" (weird len=%i)", xferp->cmd_len);
+
+		for (i=0; i<(ssize_t)xferp->cmd_len; i++)
+			debug(" %02x", xferp->cmd[i]);
+
+		/*  TODO: actualy care about cmd[]  */
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICMD_REQUEST_SENSE:
+		debug("REQUEST_SENSE");
+
+		retlen = xferp->cmd[4];
+
+		/*  TODO: bits 765 of buf[1] contains the LUN  */
+		if (xferp->cmd[1] != 0x00)
+			fatal("WARNING: REQUEST_SENSE with cmd[1]=0x%02x not"
+			    " yet implemented\n", (int)xferp->cmd[1]);
+
+		if (retlen < 18) {
+			fatal("WARNING: SCSI request sense len=%i, <18!\n",
+			    (int)retlen);
+			retlen = 18;
+		}
+
+		/*  Return data:  */
+		scsi_transfer_allocbuf(&xferp->data_in_len, &xferp->data_in,
+		    retlen, 1);
+
+		xferp->data_in[0] = 0x80 + 0x70;/*  0x80 = valid,
+						    0x70 = "current errors"  */
+		xferp->data_in[2] = 0x00;	/*  SENSE KEY!  */
+
+		if (d->filemark) {
+			xferp->data_in[2] = 0x80;
+		}
+		debug(": [2]=0x%02x ", xferp->data_in[2]);
+
+		printf(" XXX(!) \n");
+
+		/*  TODO  */
+		xferp->data_in[7] = retlen - 7;	/*  additional sense length  */
+		/*  TODO  */
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICMD_READ_BLOCK_LIMITS:
+		debug("READ_BLOCK_LIMITS");
+
+		retlen = 6;
+
+		/*  TODO: bits 765 of buf[1] contains the LUN  */
+		if (xferp->cmd[1] != 0x00)
+			fatal("WARNING: READ_BLOCK_LIMITS with cmd[1]="
+			    "0x%02x not yet implemented\n", (int)xferp->cmd[1]);
+
+		/*  Return data:  */
+		scsi_transfer_allocbuf(&xferp->data_in_len, &xferp->data_in,
+		    retlen, 1);
+
+		/*
+		 *  data[0] is reserved, data[1..3] contain the maximum block
+		 *  length limit, data[4..5] contain the minimum limit.
+		 */
+
+		{
+			int max_limit = 32768;
+			int min_limit = 128;
+
+			xferp->data_in[1] = (max_limit >> 16) & 255;
+			xferp->data_in[2] = (max_limit >>  8) & 255;
+			xferp->data_in[3] =  max_limit        & 255;
+			xferp->data_in[4] = (min_limit >>  8) & 255;
+			xferp->data_in[5] =  min_limit        & 255;
+		}
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICMD_REWIND:
+		debug("REWIND");
+
+		/*  TODO: bits 765 of buf[1] contains the LUN  */
+		if ((xferp->cmd[1] & 0xe0) != 0x00)
+			fatal("WARNING: REWIND with cmd[1]=0x%02x not yet "
+			    "implemented\n", (int)xferp->cmd[1]);
+
+		/*  Close and reopen.  */
+
+		if (d->f != NULL)
+			fclose(d->f);
+
+		d->f = fopen(d->fname, d->writable? "r+" : "r");
+		if (d->f == NULL) {
+			fprintf(stderr, "[ diskimage: could not (re)open "
+			    "'%s' ]\n", d->fname);
+			/*  TODO: return error  */
+		}
+
+		d->tape_offset = 0;
+		d->tape_filenr = 0;
+		d->filemark = 0;
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICMD_SPACE:
+		debug("SPACE");
+
+		/*  TODO: bits 765 of buf[1] contains the LUN  */
+		if ((xferp->cmd[1] & 0xe0) != 0x00)
+			fatal("WARNING: SPACE with cmd[1]=0x%02x not yet "
+			    "implemented\n", (int)xferp->cmd[1]);
+
+		/*
+		 *  Bits 2..0 of buf[1] contain the 'code' which describes how
+		 *  spacing should be done, and buf[2..4] contain the number of
+		 *  operations.
+		 */
+		debug("[ SPACE: buf[] = %02x %02x %02x %02x %02x %02x ]\n",
+		    xferp->cmd[0],
+		    xferp->cmd[1],
+		    xferp->cmd[2],
+		    xferp->cmd[3],
+		    xferp->cmd[4],
+		    xferp->cmd[5]);
+
+		switch (xferp->cmd[1] & 7) {
+		case 1:	/*  Seek to a different file nr:  */
+			{
+				int diff = (xferp->cmd[2] << 16) +
+				    (xferp->cmd[3] << 8) + xferp->cmd[4];
+
+				/*  Negative seek offset:  */
+				if (diff & (1 << 23))
+					diff = - (16777216 - diff);
+
+				d->tape_filenr += diff;
+			}
+
+			/*  At end of file, switch to the next tape file:  */
+			if (d->filemark) {
+				d->tape_filenr ++;
+				d->filemark = 0;
+			}
+
+			debug("{ switching to tape file %i }", d->tape_filenr);
+			diskimage__switch_tape(d);
+			d->filemark = 0;
+			break;
+		default:
+			fatal("[ diskimage.c: unimplemented SPACE type %i ]\n",
+			    xferp->cmd[1] & 7);
+		}
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICDROM_READ_SUBCHANNEL:
+		/*
+		 *  According to
+		 *  http://mail-index.netbsd.org/port-i386/1997/03/03/0010.html:
+		 *
+		 *  "The READ_CD_CAPACITY, READ_SUBCHANNEL, and MODE_SELECT
+		 *   commands have the same opcode in SCSI or ATAPI, but don't
+		 *   have the same command structure"...
+		 *
+		 *  TODO: This still doesn't work. Hm.
+		 */
+		retlen = 48;
+
+		debug("CDROM_READ_SUBCHANNEL/READ_CD_CAPACITY, cmd[1]=0x%02x",
+		    xferp->cmd[1]);
+
+		/*  Return data:  */
+		scsi_transfer_allocbuf(&xferp->data_in_len,
+		    &xferp->data_in, retlen, 1);
+
+		diskimage_recalc_size(d);
+
+		size = d->nr_of_logical_blocks;
+
+		xferp->data_in[0] = (size >> 24) & 255;
+		xferp->data_in[1] = (size >> 16) & 255;
+		xferp->data_in[2] = (size >> 8) & 255;
+		xferp->data_in[3] = size & 255;
+
+		xferp->data_in[4] = (d->logical_block_size >> 24) & 255;
+		xferp->data_in[5] = (d->logical_block_size >> 16) & 255;
+		xferp->data_in[6] = (d->logical_block_size >> 8) & 255;
+		xferp->data_in[7] = d->logical_block_size & 255;
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICDROM_READ_TOC:
+		debug("(CDROM_READ_TOC: ");
+		debug("lun=%i msf=%i ",
+		    xferp->cmd[1] >> 5, (xferp->cmd[1] >> 1) & 1);
+		debug("starting_track=%i ", xferp->cmd[6]);
+		retlen = xferp->cmd[7] * 256 + xferp->cmd[8];
+		debug("allocation_len=%i)\n", retlen);
+
+		/*  Return data:  */
+		scsi_transfer_allocbuf(&xferp->data_in_len,
+		    &xferp->data_in, retlen, 1);
+
+		xferp->data_in[0] = 0;
+		xferp->data_in[1] = 10;
+		xferp->data_in[2] = 0;		/*  First track.  */
+		xferp->data_in[3] = 0;		/*  Last track.  */
+
+		/*  Track 0 data:  */
+		xferp->data_in[4] = 0x00;	/*  Reserved.  */
+		xferp->data_in[5] = 0x04;	/*  ADR + CTRL:
+						    Data, not audio  */
+		xferp->data_in[6] = 0x00;	/*  Track nr  */
+		xferp->data_in[7] = 0x00;	/*  Reserved  */
+		/*  8..11 = absolute CDROM address  */
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICDROM_READ_DISCINFO:
+		/*  (Patch from Haavard Eidnes.)  */
+		debug("CDROM_READ_DISCINFO, cmd[1]=0x%02x", xferp->cmd[1]);
+		retlen = 34;
+		scsi_transfer_allocbuf(&xferp->data_in_len,
+		    &xferp->data_in, retlen, 1);
+
+		/*  TODO: Make this more generic!  */
+		xferp->data_in[0] = retlen-2;	/*  length of info, excl len  */
+		xferp->data_in[1] = 0;	 /*  length of info-(len field), msb  */
+		xferp->data_in[2] = 0xE; /*  11=complete ses., 10=fin disc  */
+		xferp->data_in[3] = 0;   /*  First track on disc  */
+		xferp->data_in[4] = 1;   /*  Number of sessions, lsb  */
+		xferp->data_in[5] = 0;   /*  first_track_last_session_lsb  */
+		xferp->data_in[6] = 0;   /*  last_track_last_session_lsb  */
+		xferp->data_in[7] = 0x20;/*  various flags  */
+		xferp->data_in[8] = 0;   /*  CD-ROM disc  */
+		xferp->data_in[9] = 1;   /*  num sessions, msb  */
+		xferp->data_in[10] = 0;  /*  first_track_last_session_msb  */
+		xferp->data_in[11] = 0;  /*  last_track_last_session_msb  */
+
+		/*  Lead-in data, for completed cd-rom:  */
+		for (size_t j=16; j<=23; j++)
+			xferp->data_in[j] = 0xff;
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICDROM_READ_TRACKINFO:
+		/*  (Patch from Haavard Eidnes.)  */
+		debug("CDROM_READ_TRACKINFO");
+		retlen = 36;
+		scsi_transfer_allocbuf(&xferp->data_in_len,
+		    &xferp->data_in, retlen, 1);
+
+		diskimage_recalc_size(d);
+
+		size = d->total_size / d->logical_block_size;
+		if (d->total_size & (d->logical_block_size-1))
+			size ++;
+
+		/*  TODO: Make more generic?  */
+		/*  TODO: Don't use magic values.  */
+		xferp->data_in[0] = retlen-2; /*  length of info, excl len  */
+		xferp->data_in[1] = 0;	      /*  length of info, msb  */
+		xferp->data_in[2] = 1;	      /*  track#, lsb  */
+		xferp->data_in[3] = 1;	      /*  session#, lsb  */
+		xferp->data_in[4] = 0;	      /*  reserved  */
+		xferp->data_in[5] = 0x6;      /*  trk mode: unintr. data,
+						  copyable  */
+		xferp->data_in[6] = 0x81;     /*  trk info: RT + trk mode  */
+		xferp->data_in[7] = 0x2;      /*  last rec=valid, next w=not
+						  valid */
+		/*
+		 *  track start, next writable, free blcks,
+		 *  blocking factor
+		 */
+		for(size_t j=8; j<=23; j++)
+			xferp->data_in[j] = 0;
+
+		/*  Track size:  */
+		xferp->data_in[24] = (size >> 24) & 0xff;
+		xferp->data_in[25] = (size >> 16) & 0xff;
+		xferp->data_in[26] = (size >> 8) & 0xff;
+		xferp->data_in[27] = size & 0xff;
+
+		/*  Last recorded address, only for dvd; zero out the rest:  */
+		for (size_t k=28; k<=35; k++)
+			xferp->data_in[k] = 0;
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICMD_MODE_SELECT:
+		debug("[ SCSI MODE_SELECT: ");
+
+		/*
+		 *  TODO:
+		 *
+		 *  This is super-hardcoded for NetBSD's usage of mode_select
+		 *  to set the size of CDROM sectors to 2048.
+		 */
+
+		if (xferp->data_out_offset == 0) {
+			xferp->data_out_len = 12;	/*  TODO  */
+			debug("data_out == NULL, wanting %i bytes ]\n",
+			    (int)xferp->data_out_len);
+			return 2;
+		}
+
+		debug("data_out!=NULL (OK), ");
+
+		/*  TODO:  Care about cmd?  */
+
+		/*  Set sector size to 2048:  */
+		/*  00 05 00 08 00 03 ca 40 00 00 08 00  */
+		if (xferp->data_out[0] == 0x00 &&
+		    xferp->data_out[1] == 0x05 &&
+		    xferp->data_out[2] == 0x00 &&
+		    xferp->data_out[3] == 0x08) {
+			d->logical_block_size =
+			    (xferp->data_out[9] << 16) +
+			    (xferp->data_out[10] << 8) +
+			    xferp->data_out[11];
+			debug("[ setting logical_block_size to %i ]\n",
+			    d->logical_block_size);
+		} else {
+			int j;
+			fatal("[ unknown MODE_SELECT: cmd =");
+			for (j=0; j<(ssize_t)xferp->cmd_len; j++)
+				fatal(" %02x", xferp->cmd[j]);
+			fatal(", data_out =");
+			for (j=0; j<(ssize_t)xferp->data_out_len; j++)
+				fatal(" %02x", xferp->data_out[j]);
+			fatal(" ]");
+		}
+
+		debug(" ]\n");
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case SCSICMD_PREVENT_ALLOW_REMOVE:
+		debug("[ SCSI 0x%02x Prevent/allow medium removal: "
+		    "TODO ]\n", xferp->cmd[0]);
+
+		diskimage__return_default_status_and_message(xferp);
+		break;
+
+	case 0xbd:
+		fatal("[ SCSI 0x%02x (len %i), TODO: ", xferp->cmd[0],
+		    xferp->cmd_len);
+		for (i=0; i<(ssize_t)xferp->cmd_len; i++)
+			fatal(" %02x", xferp->cmd[i]);
+		fatal(" ]\n");
+
+		/*
+		 *  Used by Windows NT?
+		 *
+		 *  Not documented in http://www.danbbs.dk/~dino/
+		 *		SCSI/SCSI2-D.html.
+		 *  Google gave the answer "MECHANISM_STATUS" for ATAPI. Hm.
+		 */
+
+		if (xferp->cmd_len < 12) {
+			fatal("WEIRD LEN?\n");
+			retlen = 8;
+		} else {
+			retlen = xferp->cmd[8] * 256 + xferp->cmd[9];
+		}
+
+		/*  Return data:  */
+		scsi_transfer_allocbuf(&xferp->data_in_len,
+		    &xferp->data_in, retlen, 1);
+
+		diskimage__return_default_status_and_message(xferp);
+
+		break;
+
+	default:
+		debug("[ UNIMPLEMENTED SCSI command 0x%02x, disk id=%i",
+		    xferp->cmd[0], id);
+		// exit(1);
+	}
+
+	debug(" ]\n");
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/disk/diskimage_scsicmd.cc gxemul-0.7.0+dfsg/src/disk/diskimage_scsicmd.cc
--- gxemul-0.6.2/src/disk/diskimage_scsicmd.cc	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/disk/diskimage_scsicmd.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1159 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Disk image support: SCSI command emulation.
- *
- *  TODO:  There are LOTS of ugly magic values in this module. These should
- *         be replaced by proper defines.
- *
- *  TODO:  There's probably a bug in the tape support:
- *         Let's say there are 10240 bytes left in a file, and 10240
- *         bytes are read. Then feof() is not true yet (?), so the next
- *         read will also return 10240 bytes (but all zeroes), and then after
- *         that return feof (which results in a filemark).  This is probably
- *         trivial to fix, but I don't feel like it right now.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "cpu.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "misc.h"
-
-
-static const char *diskimage_types[] = DISKIMAGE_TYPES;
-static struct scsi_transfer *first_free_scsi_transfer_alloc = NULL;
-
-
-/*
- *  scsi_transfer_alloc():
- *
- *  Allocates memory for a new scsi_transfer struct, and fills it with
- *  sane data (NULL pointers).
- *  The return value is a pointer to the new struct.  If allocation
- *  failed, the program exits.
- */
-struct scsi_transfer *scsi_transfer_alloc(void)
-{
-	struct scsi_transfer *p;
-
-	if (first_free_scsi_transfer_alloc != NULL) {
-		p = first_free_scsi_transfer_alloc;
-		first_free_scsi_transfer_alloc = p->next_free;
-	} else {
-		p = (struct scsi_transfer *) malloc(sizeof(struct scsi_transfer));
-		if (p == NULL) {
-			fprintf(stderr, "scsi_transfer_alloc(): out "
-			    "of memory\n");
-			exit(1);
-		}
-	}
-
-	memset(p, 0, sizeof(struct scsi_transfer));
-
-	return p;
-}
-
-
-/*
- *  scsi_transfer_free():
- *
- *  Frees the space used by a scsi_transfer struct.  All buffers refered
- *  to by the scsi_transfer struct are freed.
- */
-void scsi_transfer_free(struct scsi_transfer *p)
-{
-	if (p == NULL) {
-		fprintf(stderr, "scsi_transfer_free(): p == NULL\n");
-		exit(1);
-	}
-
-	if (p->msg_out != NULL)
-		free(p->msg_out);
-	if (p->cmd != NULL)
-		free(p->cmd);
-	if (p->data_out != NULL)
-		free(p->data_out);
-
-	if (p->data_in != NULL)
-		free(p->data_in);
-	if (p->msg_in != NULL)
-		free(p->msg_in);
-	if (p->status != NULL)
-		free(p->status);
-
-	p->next_free = first_free_scsi_transfer_alloc;
-	first_free_scsi_transfer_alloc = p;
-}
-
-
-/*
- *  scsi_transfer_allocbuf():
- *
- *  Helper function, used by diskimage_scsicommand(), and SCSI controller
- *  devices.  Example of usage:
- *
- *	scsi_transfer_allocbuf(&xferp->msg_in_len, &xferp->msg_in, 1);
- */
-void scsi_transfer_allocbuf(size_t *lenp, unsigned char **pp, size_t want_len,
-	int clearflag)
-{
-	unsigned char *p = (*pp);
-
-	if (p != NULL) {
-		printf("WARNING! scsi_transfer_allocbuf(): old pointer "
-		    "was not NULL, freeing it now\n");
-		free(p);
-	}
-
-	(*lenp) = want_len;
-	if ((p = (unsigned char *) malloc(want_len)) == NULL) {
-		fprintf(stderr, "scsi_transfer_allocbuf(): out of "
-		    "memory trying to allocate %li bytes\n", (long)want_len);
-		exit(1);
-	}
-
-	if (clearflag)
-		memset(p, 0, want_len);
-
-	(*pp) = p;
-}
-
-
-/**************************************************************************/
-
-
-/*
- *  diskimage__return_default_status_and_message():
- *
- *  Set the status and msg_in parts of a scsi_transfer struct
- *  to default values (msg_in = 0x00, status = 0x00).
- */
-static void diskimage__return_default_status_and_message(
-	struct scsi_transfer *xferp)
-{
-	scsi_transfer_allocbuf(&xferp->status_len, &xferp->status, 1, 0);
-	xferp->status[0] = 0x00;
-	scsi_transfer_allocbuf(&xferp->msg_in_len, &xferp->msg_in, 1, 0);
-	xferp->msg_in[0] = 0x00;
-}
-
-
-/*
- *  diskimage__switch_tape():
- *
- *  Used by the SPACE command.  (d is assumed to be non-NULL.)
- */
-static void diskimage__switch_tape(struct diskimage *d)
-{
-	char tmpfname[1000];
-
-	snprintf(tmpfname, sizeof(tmpfname), "%s.%i",
-	    d->fname, d->tape_filenr);
-	tmpfname[sizeof(tmpfname)-1] = '\0';
-
-	if (d->f != NULL)
-		fclose(d->f);
-
-	d->f = fopen(tmpfname, d->writable? "r+" : "r");
-	if (d->f == NULL) {
-		fprintf(stderr, "[ diskimage__switch_tape(): could not "
-		    "(re)open '%s' ]\n", tmpfname);
-		/*  TODO: return error  */
-	}
-	d->tape_offset = 0;
-}
-
-
-/**************************************************************************/
-
-
-/*
- *  diskimage_scsicommand():
- *
- *  Perform a SCSI command on a disk image.
- *
- *  The xferp points to a scsi_transfer struct, containing msg_out, command,
- *  and data_out coming from the SCSI controller device.  This function
- *  interprets the command, and (if necessary) creates responses in
- *  data_in, msg_in, and status.
- *
- *  Returns:
- *	2 if the command expects data from the DATA_OUT phase,
- *	1 if otherwise ok,
- *	0 on error.
- */
-int diskimage_scsicommand(struct cpu *cpu, int id, int type,
-	struct scsi_transfer *xferp)
-{
-	char namebuf[16];
-	int retlen, i, q, result;
-	uint64_t size;
-	int64_t ofs;
-	int pagecode;
-	struct machine *machine = cpu->machine;
-	struct diskimage *d;
-
-	if (machine == NULL) {
-		fatal("[ diskimage_scsicommand(): machine == NULL ]\n");
-		return 0;
-	}
-
-	d = machine->first_diskimage;
-	while (d != NULL) {
-		if (d->type == type && d->id == id)
-			break;
-		d = d->next;
-	}
-	if (d == NULL) {
-		fprintf(stderr, "[ diskimage_scsicommand(): %s "
-		    " id %i not connected? ]\n", diskimage_types[type], id);
-	}
-
-	if (xferp->cmd == NULL) {
-		fatal("[ diskimage_scsicommand(): cmd == NULL ]\n");
-		return 0;
-	}
-
-	if (xferp->cmd_len < 1) {
-		fatal("[ diskimage_scsicommand(): cmd_len == %i ]\n",
-		    xferp->cmd_len);
-		return 0;
-	}
-
-	debug("[ diskimage_scsicommand(id=%i) cmd=0x%02x: ",
-	    id, xferp->cmd[0]);
-
-#if 0
-	fatal("[ diskimage_scsicommand(id=%i) cmd=0x%02x len=%i:",
-	    id, xferp->cmd[0], xferp->cmd_len);
-	for (i=0; i<xferp->cmd_len; i++)
-		fatal(" %02x", xferp->cmd[i]);
-	fatal("\n");
-if (xferp->cmd_len > 7 && xferp->cmd[5] == 0x11)
-	single_step = ENTER_SINGLE_STEPPING;
-#endif
-
-#if 0
-{
-	static FILE *f = NULL;
-	if (f == NULL)
-		f = fopen("scsi_log.txt", "w"); 
-	if (f != NULL) {
-		int i;
-		fprintf(f, "id=%i cmd =", id);
-		for (i=0; i<xferp->cmd_len; i++)
-			fprintf(f, " %02x", xferp->cmd[i]);
-		fprintf(f, "\n");
-		fflush(f);
-	}
-}
-#endif
-
-	switch (xferp->cmd[0]) {
-
-	case SCSICMD_TEST_UNIT_READY:
-		debug("TEST_UNIT_READY");
-		if (xferp->cmd_len != 6)
-			debug(" (weird len=%i)", xferp->cmd_len);
-
-		/*  TODO: bits 765 of buf[1] contains the LUN  */
-		if (xferp->cmd[1] != 0x00)
-			fatal("WARNING: TEST_UNIT_READY with cmd[1]=0x%02x"
-			    " not yet implemented\n", (int)xferp->cmd[1]);
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICMD_INQUIRY:
-		debug("INQUIRY");
-		if (xferp->cmd_len != 6)
-			debug(" (weird len=%i)", xferp->cmd_len);
-		if (xferp->cmd[1] != 0x00) {
-			debug("WARNING: INQUIRY with cmd[1]=0x%02x not yet "
-			    "implemented\n", (int)xferp->cmd[1]);
-
-			break;
-		}
-
-		/*  Return values:  */
-		retlen = xferp->cmd[4];
-		if (retlen < 36) {
-			fatal("WARNING: SCSI inquiry len=%i, <36!\n", retlen);
-			retlen = 36;
-		}
-
-		/*  Return data:  */
-		scsi_transfer_allocbuf(&xferp->data_in_len, &xferp->data_in,
-		    retlen, 1);
-		xferp->data_in[0] = 0x00;  /*  0x00 = Direct-access disk  */
-		xferp->data_in[1] = 0x00;  /*  0x00 = non-removable  */
-		xferp->data_in[2] = 0x02;  /*  SCSI-2  */
-#if 0
-xferp->data_in[3] = 0x02;	/*  Response data format = SCSI-2  */
-#endif
-		xferp->data_in[4] = retlen - 4;	/*  Additional length  */
-xferp->data_in[4] = 0x2c - 4;	/*  Additional length  */
-		xferp->data_in[6] = 0x04;  /*  ACKREQQ  */
-		xferp->data_in[7] = 0x60;  /*  WBus32, WBus16  */
-
-		/*  These are padded with spaces:  */
-
-		memcpy(xferp->data_in+8,  "GXemul  ", 8);
-		if (diskimage_getname(cpu->machine, id,
-		    type, namebuf, sizeof(namebuf))) {
-			for (size_t j=0; j<sizeof(namebuf); j++) {
-				if (namebuf[j] == 0) {
-					for (; j<sizeof(namebuf); j++)
-						namebuf[j] = ' ';
-					break;
-				}
-			}
-			
-			memcpy(xferp->data_in+16, namebuf, 16);
-		} else
-			memcpy(xferp->data_in+16, "DISK            ", 16);
-		memcpy(xferp->data_in+32, "0   ", 4);
-
-		/*
-		 *  Some Ultrix kernels want specific responses from
-		 *  the drives.
-		 */
-
-		if (machine->machine_type == MACHINE_PMAX) {
-			/*  DEC, RZ25 (rev 0900) = 832527 sectors  */
-			/*  DEC, RZ58 (rev 2000) = 2698061 sectors  */
-			memcpy(xferp->data_in+8,  "DEC     ", 8);
-			memcpy(xferp->data_in+16, "RZ58     (C) DEC", 16);
-			memcpy(xferp->data_in+32, "2000", 4);
-		}
-
-		/*  Some data is different for CD-ROM drives:  */
-		if (d->is_a_cdrom) {
-			xferp->data_in[0] = 0x05;  /*  0x05 = CD-ROM  */
-			xferp->data_in[1] = 0x80;  /*  0x80 = removable  */
-			/*  memcpy(xferp->data_in+16, "CD-ROM          ", 16);*/
-
-			if (machine->machine_type == MACHINE_PMAX) {
-				/*  SONY, CD-ROM:  */
-				memcpy(xferp->data_in+8, "SONY    ", 8);
-				memcpy(xferp->data_in+16,
-				    "CD-ROM          ", 16);
-
-				/*  ... or perhaps this:  */
-				memcpy(xferp->data_in+8, "DEC     ", 8);
-				memcpy(xferp->data_in+16,
-				    "RRD42   (C) DEC ", 16);
-				memcpy(xferp->data_in+32, "4.5d", 4);
-			} else if (machine->machine_type == MACHINE_ARC) {
-				/*  NEC, CD-ROM:  */
-				memcpy(xferp->data_in+8, "NEC     ", 8);
-				memcpy(xferp->data_in+16,
-				    "CD-ROM CDR-210P ", 16);
-				memcpy(xferp->data_in+32, "1.0 ", 4);
-			}
-		}
-
-		/*  Data for tape devices:  */
-		if (d->is_a_tape) {
-			xferp->data_in[0] = 0x01;  /*  0x01 = tape  */
-			xferp->data_in[1] = 0x80;  /*  0x80 = removable  */
-			memcpy(xferp->data_in+16, "TAPE            ", 16);
-
-			if (machine->machine_type == MACHINE_PMAX) {
-				/*
-				 *  TODO:  find out if these are correct.
-				 *
-				 *  The name might be TZK10, TSZ07, or TLZ04,
-				 *  or something completely different.
-				 */
-				memcpy(xferp->data_in+8, "DEC     ", 8);
-				memcpy(xferp->data_in+16,
-				    "TK50     (C) DEC", 16);
-				memcpy(xferp->data_in+32, "2000", 4);
-			}
-		}
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSIBLOCKCMD_READ_CAPACITY:
-		debug("READ_CAPACITY");
-
-		if (xferp->cmd_len != 10)
-			fatal(" [ weird READ_CAPACITY len=%i, should be 10 ] ",
-			    xferp->cmd_len);
-		else {
-			if (xferp->cmd[8] & 1) {
-				/*  Partial Medium Indicator bit...  TODO  */
-				fatal("WARNING: READ_CAPACITY with PMI bit"
-				    " set not yet implemented\n");
-			}
-		}
-
-		/*  Return data:  */
-		scsi_transfer_allocbuf(&xferp->data_in_len, &xferp->data_in,
-		    8, 1);
-
-		diskimage_recalc_size(d);
-
-		size = d->total_size / d->logical_block_size;
-		if (d->total_size & (d->logical_block_size-1))
-			size ++;
-
-		xferp->data_in[0] = (size >> 24) & 255;
-		xferp->data_in[1] = (size >> 16) & 255;
-		xferp->data_in[2] = (size >> 8) & 255;
-		xferp->data_in[3] = size & 255;
-
-		xferp->data_in[4] = (d->logical_block_size >> 24) & 255;
-		xferp->data_in[5] = (d->logical_block_size >> 16) & 255;
-		xferp->data_in[6] = (d->logical_block_size >> 8) & 255;
-		xferp->data_in[7] = d->logical_block_size & 255;
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICMD_MODE_SENSE:
-	case SCSICMD_MODE_SENSE10:	
-		debug("MODE_SENSE");
-		q = 4; retlen = xferp->cmd[4];
-		switch (xferp->cmd_len) {
-		case 6:	break;
-		case 10:q = 8;
-			retlen = xferp->cmd[7] * 256 + xferp->cmd[8];
-			break;
-		default:fatal(" (unimplemented mode_sense len=%i)",
-			    xferp->cmd_len);
-		}
-
-		/*
-		 *  NOTE/TODO: This code doesn't handle too short retlens
-		 *  very well. A quick hack around this is that I allocate
-		 *  a bit too much memory, so that nothing is actually
-		 *  written outside of xferp->data_in[].
-		 */
-
-		retlen += 100;		/*  Should be enough. (Ugly.)  */
-
-		if ((xferp->cmd[2] & 0xc0) != 0)
-			fatal("WARNING: mode sense, cmd[2] = 0x%02x\n",
-			    xferp->cmd[2]);
-
-		/*  Return data:  */
-		scsi_transfer_allocbuf(&xferp->data_in_len,
-		    &xferp->data_in, retlen, 1);
-
-		xferp->data_in_len -= 100;	/*  Restore size.  */
-
-		pagecode = xferp->cmd[2] & 0x3f;
-
-		debug("[ MODE SENSE id %i, pagecode=%i ]\n", id, pagecode);
-
-		/*  4 bytes of header for 6-byte command,
-		    8 bytes of header for 10-byte command.  */
-		xferp->data_in[0] = retlen;	/*  0: mode data length  */
-		xferp->data_in[1] = d->is_a_cdrom? 0x05 : 0x00;
-				/*  1: medium type  */
-		xferp->data_in[2] = 0x00;	/*  device specific
-						    parameter  */
-		xferp->data_in[3] = 8 * 1;	/*  block descriptor
-						    length: 1 page (?)  */
-
-		xferp->data_in[q+0] = 0x00;	/*  density code  */
-		xferp->data_in[q+1] = 0;	/*  nr of blocks, high  */
-		xferp->data_in[q+2] = 0;	/*  nr of blocks, mid  */
-		xferp->data_in[q+3] = 0;	/*  nr of blocks, low */
-		xferp->data_in[q+4] = 0x00;	/*  reserved  */
-		xferp->data_in[q+5] = (d->logical_block_size >> 16) & 255;
-		xferp->data_in[q+6] = (d->logical_block_size >> 8) & 255;
-		xferp->data_in[q+7] = d->logical_block_size & 255;
-		q += 8;
-
-		diskimage__return_default_status_and_message(xferp);
-
-		/*  descriptors, 8 bytes (each)  */
-
-		/*  page, n bytes (each)  */
-		switch (pagecode) {
-		case 0:
-			/*  TODO: Nothing here?  */
-			break;
-		case 1:		/*  read-write error recovery page  */
-			xferp->data_in[q + 0] = pagecode;
-			xferp->data_in[q + 1] = 10;
-			break;
-		case 3:		/*  format device page  */
-			xferp->data_in[q + 0] = pagecode;
-			xferp->data_in[q + 1] = 22;
-
-			/*  10,11 = sectors per track  */
-			xferp->data_in[q + 10] = 0;
-			xferp->data_in[q + 11] = d->sectors_per_track;
-
-			/*  12,13 = physical sector size  */
-			xferp->data_in[q + 12] =
-			    (d->logical_block_size >> 8) & 255;
-			xferp->data_in[q + 13] = d->logical_block_size & 255;
-			break;
-		case 4:		/*  rigid disk geometry page  */
-			xferp->data_in[q + 0] = pagecode;
-			xferp->data_in[q + 1] = 22;
-			xferp->data_in[q + 2] = (d->ncyls >> 16) & 255;
-			xferp->data_in[q + 3] = (d->ncyls >> 8) & 255;
-			xferp->data_in[q + 4] = d->ncyls & 255;
-			xferp->data_in[q + 5] = d->heads;
-
-			xferp->data_in[q + 20] = (d->rpms >> 8) & 255;
-			xferp->data_in[q + 21] = d->rpms & 255;
-			break;
-		case 5:		/*  flexible disk page  */
-			xferp->data_in[q + 0] = pagecode;
-			xferp->data_in[q + 1] = 0x1e;
-
-			/*  2,3 = transfer rate  */
-			xferp->data_in[q + 2] = ((5000) >> 8) & 255;
-			xferp->data_in[q + 3] = (5000) & 255;
-
-			xferp->data_in[q + 4] = d->heads;
-			xferp->data_in[q + 5] = d->sectors_per_track;
-
-			/*  6,7 = data bytes per sector  */
-			xferp->data_in[q + 6] = (d->logical_block_size >> 8)
-			    & 255;
-			xferp->data_in[q + 7] = d->logical_block_size & 255;
-
-			xferp->data_in[q + 8] = (d->ncyls >> 8) & 255;
-			xferp->data_in[q + 9] = d->ncyls & 255;
-
-			xferp->data_in[q + 28] = (d->rpms >> 8) & 255;
-			xferp->data_in[q + 29] = d->rpms & 255;
-			break;
-		default:
-			fatal("[ MODE_SENSE for page %i is not yet "
-			    "implemented! ]\n", pagecode);
-		}
-
-		break;
-
-	case SCSICMD_READ:
-	case SCSICMD_READ_10:
-		debug("READ");
-
-		/*
-		 *  For tape devices, read data at the current position.
-		 *  For disk and CDROM devices, the command bytes contain
-		 *  an offset telling us where to read from the device.
-		 */
-
-		if (d->is_a_tape) {
-			/*  bits 7..5 of cmd[1] are the LUN bits... TODO  */
-
-			size = (xferp->cmd[2] << 16) +
-			       (xferp->cmd[3] <<  8) +
-				xferp->cmd[4];
-
-			/*  Bit 1 of cmd[1] is the SILI bit (TODO), and
-			    bit 0 is the "use fixed length" bit.  */
-
-			if (xferp->cmd[1] & 0x01) {
-				/*  Fixed block length:  */
-				size *= d->logical_block_size;
-			}
-
-			if (d->filemark) {
-				/*  At end of file, switch to the next
-				    automagically:  */
-				d->tape_filenr ++;
-				diskimage__switch_tape(d);
-
-				d->filemark = 0;
-			}
-
-			ofs = d->tape_offset;
-
-			fatal("[ READ tape, id=%i file=%i, cmd[1]=%02x size=%i"
-			    ", ofs=%lli ]\n", id, d->tape_filenr,
-			    xferp->cmd[1], (int)size, (long long)ofs);
-		} else {
-			if (xferp->cmd[0] == SCSICMD_READ) {
-				if (xferp->cmd_len != 6)
-					debug(" (weird len=%i)",
-					    xferp->cmd_len);
-
-				/*
-				 *  bits 4..0 of cmd[1], and cmd[2] and cmd[3]
-				 *  hold the logical block address.
-				 *
-				 *  cmd[4] holds the number of logical blocks
-				 *  to transfer. (Special case if the value is
-				 *  0, actually means 256.)
-				 */
-				ofs = ((xferp->cmd[1] & 0x1f) << 16) +
-				      (xferp->cmd[2] << 8) + xferp->cmd[3];
-				retlen = xferp->cmd[4];
-				if (retlen == 0)
-					retlen = 256;
-			} else {
-				if (xferp->cmd_len != 10)
-					debug(" (weird len=%i)",
-					    xferp->cmd_len);
-
-				/*
-				 *  cmd[2..5] hold the logical block address.
-				 *  cmd[7..8] holds the number of logical
-				 *  blocks to transfer. (NOTE: If the value is
-				 *  0, this means 0, not 65536. :-)
-				 */
-				ofs = ((uint64_t)xferp->cmd[2] << 24) +
-				    (xferp->cmd[3] << 16) + (xferp->cmd[4] << 8)
-				    + xferp->cmd[5];
-				retlen = (xferp->cmd[7] << 8) + xferp->cmd[8];
-			}
-
-			size = retlen * d->logical_block_size;
-			ofs *= d->logical_block_size;
-		}
-
-		/*  Return data:  */
-		scsi_transfer_allocbuf(&xferp->data_in_len, &xferp->data_in,
-		    size, 0);
-
-		debug(" READ  ofs=%lli size=%i\n", (long long)ofs, (int)size);
-
-		diskimage__return_default_status_and_message(xferp);
-
-		d->filemark = 0;
-
-		/*
-		 *  Failure? Then set check condition.
-		 *  For tapes, error should only occur at the end of a file.
-		 *
-		 *  "If the logical unit encounters a filemark during
-		 *   a READ command, CHECK CONDITION status shall be
-		 *   returned and the filemark and valid bits shall be
-		 *   set to one in the sense data. The sense key shall
-		 *   be set to NO SENSE"..
-		 */
-		if (d->is_a_tape && d->f != NULL && feof(d->f)) {
-			debug(" feof id=%i\n", id);
-			xferp->status[0] = 0x02;	/*  CHECK CONDITION  */
-
-			d->filemark = 1;
-		} else {
-			result = diskimage__internal_access(d, 0, ofs,
-			    xferp->data_in, size);
-		}
-
-		if (d->is_a_tape && d->f != NULL)
-			d->tape_offset = ftello(d->f);
-
-		/*  TODO: other errors?  */
-		break;
-
-	case SCSICMD_WRITE:
-	case SCSICMD_WRITE_10:
-		debug("WRITE");
-
-		/*  TODO: tape  */
-
-		if (xferp->cmd[0] == SCSICMD_WRITE) {
-			if (xferp->cmd_len != 6)
-				debug(" (weird len=%i)", xferp->cmd_len);
-
-			/*
-			 *  bits 4..0 of cmd[1], and cmd[2] and cmd[3] hold the
-			 *  logical block address.
-			 *
-			 *  cmd[4] holds the number of logical blocks to
-			 *  transfer. (Special case if the value is 0, actually
-			 *  means 256.)
-			 */
-			ofs = ((xferp->cmd[1] & 0x1f) << 16) +
-			      (xferp->cmd[2] << 8) + xferp->cmd[3];
-			retlen = xferp->cmd[4];
-			if (retlen == 0)
-				retlen = 256;
-		} else {
-			if (xferp->cmd_len != 10)
-				debug(" (weird len=%i)", xferp->cmd_len);
-
-			/*
-			 *  cmd[2..5] hold the logical block address.
-			 *  cmd[7..8] holds the number of logical blocks to
-			 *  transfer. (NOTE: If the value is 0 this means 0,
-			 *  not 65536.)
-			 */
-			ofs = ((uint64_t)xferp->cmd[2] << 24) +
-			    (xferp->cmd[3] << 16) + (xferp->cmd[4] << 8) +
-			    xferp->cmd[5];
-			retlen = (xferp->cmd[7] << 8) + xferp->cmd[8];
-		}
-
-		size = retlen * d->logical_block_size;
-		ofs *= d->logical_block_size;
-
-		if (xferp->data_out_offset != size) {
-			debug(", data_out == NULL, wanting %i bytes, \n\n",
-			    (int)size);
-			xferp->data_out_len = size;
-			return 2;
-		}
-
-		debug(", data_out != NULL, OK :-)");
-
-		debug("WRITE ofs=%i size=%i offset=%i\n", (int)ofs,
-		    (int)size, (int)xferp->data_out_offset);
-
-		result = diskimage__internal_access(d, 1, ofs,
-		    xferp->data_out, size);
-
-		/*  TODO: how about return code?  */
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICMD_SYNCHRONIZE_CACHE:
-		debug("SYNCHRONIZE_CACHE");
-
-		if (xferp->cmd_len != 10)
-			debug(" (weird len=%i)", xferp->cmd_len);
-
-		/*  TODO: actualy care about cmd[]  */
-		/*  TODO: Move to diskimage.cc and make sure that both
-			d->f is fsynced AND any overlays and overlay bitmap
-			files are fsynced too!  */
-		fsync(fileno(d->f));
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICMD_START_STOP_UNIT:
-		debug("START_STOP_UNIT");
-
-		if (xferp->cmd_len != 6)
-			debug(" (weird len=%i)", xferp->cmd_len);
-
-		for (i=0; i<(ssize_t)xferp->cmd_len; i++)
-			debug(" %02x", xferp->cmd[i]);
-
-		/*  TODO: actualy care about cmd[]  */
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICMD_REQUEST_SENSE:
-		debug("REQUEST_SENSE");
-
-		retlen = xferp->cmd[4];
-
-		/*  TODO: bits 765 of buf[1] contains the LUN  */
-		if (xferp->cmd[1] != 0x00)
-			fatal("WARNING: REQUEST_SENSE with cmd[1]=0x%02x not"
-			    " yet implemented\n", (int)xferp->cmd[1]);
-
-		if (retlen < 18) {
-			fatal("WARNING: SCSI request sense len=%i, <18!\n",
-			    (int)retlen);
-			retlen = 18;
-		}
-
-		/*  Return data:  */
-		scsi_transfer_allocbuf(&xferp->data_in_len, &xferp->data_in,
-		    retlen, 1);
-
-		xferp->data_in[0] = 0x80 + 0x70;/*  0x80 = valid,
-						    0x70 = "current errors"  */
-		xferp->data_in[2] = 0x00;	/*  SENSE KEY!  */
-
-		if (d->filemark) {
-			xferp->data_in[2] = 0x80;
-		}
-		debug(": [2]=0x%02x ", xferp->data_in[2]);
-
-		printf(" XXX(!) \n");
-
-		/*  TODO  */
-		xferp->data_in[7] = retlen - 7;	/*  additional sense length  */
-		/*  TODO  */
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICMD_READ_BLOCK_LIMITS:
-		debug("READ_BLOCK_LIMITS");
-
-		retlen = 6;
-
-		/*  TODO: bits 765 of buf[1] contains the LUN  */
-		if (xferp->cmd[1] != 0x00)
-			fatal("WARNING: READ_BLOCK_LIMITS with cmd[1]="
-			    "0x%02x not yet implemented\n", (int)xferp->cmd[1]);
-
-		/*  Return data:  */
-		scsi_transfer_allocbuf(&xferp->data_in_len, &xferp->data_in,
-		    retlen, 1);
-
-		/*
-		 *  data[0] is reserved, data[1..3] contain the maximum block
-		 *  length limit, data[4..5] contain the minimum limit.
-		 */
-
-		{
-			int max_limit = 32768;
-			int min_limit = 128;
-
-			xferp->data_in[1] = (max_limit >> 16) & 255;
-			xferp->data_in[2] = (max_limit >>  8) & 255;
-			xferp->data_in[3] =  max_limit        & 255;
-			xferp->data_in[4] = (min_limit >>  8) & 255;
-			xferp->data_in[5] =  min_limit        & 255;
-		}
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICMD_REWIND:
-		debug("REWIND");
-
-		/*  TODO: bits 765 of buf[1] contains the LUN  */
-		if ((xferp->cmd[1] & 0xe0) != 0x00)
-			fatal("WARNING: REWIND with cmd[1]=0x%02x not yet "
-			    "implemented\n", (int)xferp->cmd[1]);
-
-		/*  Close and reopen.  */
-
-		if (d->f != NULL)
-			fclose(d->f);
-
-		d->f = fopen(d->fname, d->writable? "r+" : "r");
-		if (d->f == NULL) {
-			fprintf(stderr, "[ diskimage: could not (re)open "
-			    "'%s' ]\n", d->fname);
-			/*  TODO: return error  */
-		}
-
-		d->tape_offset = 0;
-		d->tape_filenr = 0;
-		d->filemark = 0;
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICMD_SPACE:
-		debug("SPACE");
-
-		/*  TODO: bits 765 of buf[1] contains the LUN  */
-		if ((xferp->cmd[1] & 0xe0) != 0x00)
-			fatal("WARNING: SPACE with cmd[1]=0x%02x not yet "
-			    "implemented\n", (int)xferp->cmd[1]);
-
-		/*
-		 *  Bits 2..0 of buf[1] contain the 'code' which describes how
-		 *  spacing should be done, and buf[2..4] contain the number of
-		 *  operations.
-		 */
-		debug("[ SPACE: buf[] = %02x %02x %02x %02x %02x %02x ]\n",
-		    xferp->cmd[0],
-		    xferp->cmd[1],
-		    xferp->cmd[2],
-		    xferp->cmd[3],
-		    xferp->cmd[4],
-		    xferp->cmd[5]);
-
-		switch (xferp->cmd[1] & 7) {
-		case 1:	/*  Seek to a different file nr:  */
-			{
-				int diff = (xferp->cmd[2] << 16) +
-				    (xferp->cmd[3] << 8) + xferp->cmd[4];
-
-				/*  Negative seek offset:  */
-				if (diff & (1 << 23))
-					diff = - (16777216 - diff);
-
-				d->tape_filenr += diff;
-			}
-
-			/*  At end of file, switch to the next tape file:  */
-			if (d->filemark) {
-				d->tape_filenr ++;
-				d->filemark = 0;
-			}
-
-			debug("{ switching to tape file %i }", d->tape_filenr);
-			diskimage__switch_tape(d);
-			d->filemark = 0;
-			break;
-		default:
-			fatal("[ diskimage.c: unimplemented SPACE type %i ]\n",
-			    xferp->cmd[1] & 7);
-		}
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICDROM_READ_SUBCHANNEL:
-		/*
-		 *  According to
-		 *  http://mail-index.netbsd.org/port-i386/1997/03/03/0010.html:
-		 *
-		 *  "The READ_CD_CAPACITY, READ_SUBCHANNEL, and MODE_SELECT
-		 *   commands have the same opcode in SCSI or ATAPI, but don't
-		 *   have the same command structure"...
-		 *
-		 *  TODO: This still doesn't work. Hm.
-		 */
-		retlen = 48;
-
-		debug("CDROM_READ_SUBCHANNEL/READ_CD_CAPACITY, cmd[1]=0x%02x",
-		    xferp->cmd[1]);
-
-		/*  Return data:  */
-		scsi_transfer_allocbuf(&xferp->data_in_len,
-		    &xferp->data_in, retlen, 1);
-
-		diskimage_recalc_size(d);
-
-		size = d->total_size / d->logical_block_size;
-		if (d->total_size & (d->logical_block_size-1))
-			size ++;
-
-		xferp->data_in[0] = (size >> 24) & 255;
-		xferp->data_in[1] = (size >> 16) & 255;
-		xferp->data_in[2] = (size >> 8) & 255;
-		xferp->data_in[3] = size & 255;
-
-		xferp->data_in[4] = (d->logical_block_size >> 24) & 255;
-		xferp->data_in[5] = (d->logical_block_size >> 16) & 255;
-		xferp->data_in[6] = (d->logical_block_size >> 8) & 255;
-		xferp->data_in[7] = d->logical_block_size & 255;
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICDROM_READ_TOC:
-		debug("(CDROM_READ_TOC: ");
-		debug("lun=%i msf=%i ",
-		    xferp->cmd[1] >> 5, (xferp->cmd[1] >> 1) & 1);
-		debug("starting_track=%i ", xferp->cmd[6]);
-		retlen = xferp->cmd[7] * 256 + xferp->cmd[8];
-		debug("allocation_len=%i)\n", retlen);
-
-		/*  Return data:  */
-		scsi_transfer_allocbuf(&xferp->data_in_len,
-		    &xferp->data_in, retlen, 1);
-
-		xferp->data_in[0] = 0;
-		xferp->data_in[1] = 10;
-		xferp->data_in[2] = 0;		/*  First track.  */
-		xferp->data_in[3] = 0;		/*  Last track.  */
-
-		/*  Track 0 data:  */
-		xferp->data_in[4] = 0x00;	/*  Reserved.  */
-		xferp->data_in[5] = 0x04;	/*  ADR + CTRL:
-						    Data, not audio  */
-		xferp->data_in[6] = 0x00;	/*  Track nr  */
-		xferp->data_in[7] = 0x00;	/*  Reserved  */
-		/*  8..11 = absolute CDROM address  */
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICDROM_READ_DISCINFO:
-		/*  (Patch from H�vard Eidnes.)  */
-		debug("CDROM_READ_DISCINFO, cmd[1]=0x%02x", xferp->cmd[1]);
-		retlen = 34;
-		scsi_transfer_allocbuf(&xferp->data_in_len,
-		    &xferp->data_in, retlen, 1);
-
-		/*  TODO: Make this more generic!  */
-		xferp->data_in[0] = retlen-2;	/*  length of info, excl len  */
-		xferp->data_in[1] = 0;	 /*  length of info-(len field), msb  */
-		xferp->data_in[2] = 0xE; /*  11=complete ses., 10=fin disc  */
-		xferp->data_in[3] = 0;   /*  First track on disc  */
-		xferp->data_in[4] = 1;   /*  Number of sessions, lsb  */
-		xferp->data_in[5] = 0;   /*  first_track_last_session_lsb  */
-		xferp->data_in[6] = 0;   /*  last_track_last_session_lsb  */
-		xferp->data_in[7] = 0x20;/*  various flags  */
-		xferp->data_in[8] = 0;   /*  CD-ROM disc  */
-		xferp->data_in[9] = 1;   /*  num sessions, msb  */
-		xferp->data_in[10] = 0;  /*  first_track_last_session_msb  */
-		xferp->data_in[11] = 0;  /*  last_track_last_session_msb  */
-
-		/*  Lead-in data, for completed cd-rom:  */
-		for (size_t j=16; j<=23; j++)
-			xferp->data_in[j] = 0xff;
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICDROM_READ_TRACKINFO:
-		/*  (Patch from H�vard Eidnes.)  */
-		debug("CDROM_READ_TRACKINFO");
-		retlen = 36;
-		scsi_transfer_allocbuf(&xferp->data_in_len,
-		    &xferp->data_in, retlen, 1);
-
-		diskimage_recalc_size(d);
-
-		size = d->total_size / d->logical_block_size;
-		if (d->total_size & (d->logical_block_size-1))
-			size ++;
-
-		/*  TODO: Make more generic?  */
-		/*  TODO: Don't use magic values.  */
-		xferp->data_in[0] = retlen-2; /*  length of info, excl len  */
-		xferp->data_in[1] = 0;	      /*  length of info, msb  */
-		xferp->data_in[2] = 1;	      /*  track#, lsb  */
-		xferp->data_in[3] = 1;	      /*  session#, lsb  */
-		xferp->data_in[4] = 0;	      /*  reserved  */
-		xferp->data_in[5] = 0x6;      /*  trk mode: unintr. data,
-						  copyable  */
-		xferp->data_in[6] = 0x81;     /*  trk info: RT + trk mode  */
-		xferp->data_in[7] = 0x2;      /*  last rec=valid, next w=not
-						  valid */
-		/*
-		 *  track start, next writable, free blcks,
-		 *  blocking factor
-		 */
-		for(size_t j=8; j<=23; j++)
-			xferp->data_in[j] = 0;
-
-		/*  Track size:  */
-		xferp->data_in[24] = (size >> 24) & 0xff;
-		xferp->data_in[25] = (size >> 16) & 0xff;
-		xferp->data_in[26] = (size >> 8) & 0xff;
-		xferp->data_in[27] = size & 0xff;
-
-		/*  Last recorded address, only for dvd; zero out the rest:  */
-		for (size_t k=28; k<=35; k++)
-			xferp->data_in[k] = 0;
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICMD_MODE_SELECT:
-		debug("[ SCSI MODE_SELECT: ");
-
-		/*
-		 *  TODO:
-		 *
-		 *  This is super-hardcoded for NetBSD's usage of mode_select
-		 *  to set the size of CDROM sectors to 2048.
-		 */
-
-		if (xferp->data_out_offset == 0) {
-			xferp->data_out_len = 12;	/*  TODO  */
-			debug("data_out == NULL, wanting %i bytes ]\n",
-			    (int)xferp->data_out_len);
-			return 2;
-		}
-
-		debug("data_out!=NULL (OK), ");
-
-		/*  TODO:  Care about cmd?  */
-
-		/*  Set sector size to 2048:  */
-		/*  00 05 00 08 00 03 ca 40 00 00 08 00  */
-		if (xferp->data_out[0] == 0x00 &&
-		    xferp->data_out[1] == 0x05 &&
-		    xferp->data_out[2] == 0x00 &&
-		    xferp->data_out[3] == 0x08) {
-			d->logical_block_size =
-			    (xferp->data_out[9] << 16) +
-			    (xferp->data_out[10] << 8) +
-			    xferp->data_out[11];
-			debug("[ setting logical_block_size to %i ]\n",
-			    d->logical_block_size);
-		} else {
-			int j;
-			fatal("[ unknown MODE_SELECT: cmd =");
-			for (j=0; j<(ssize_t)xferp->cmd_len; j++)
-				fatal(" %02x", xferp->cmd[j]);
-			fatal(", data_out =");
-			for (j=0; j<(ssize_t)xferp->data_out_len; j++)
-				fatal(" %02x", xferp->data_out[j]);
-			fatal(" ]");
-		}
-
-		debug(" ]\n");
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case SCSICMD_PREVENT_ALLOW_REMOVE:
-		debug("[ SCSI 0x%02x Prevent/allow medium removal: "
-		    "TODO ]\n", xferp->cmd[0]);
-
-		diskimage__return_default_status_and_message(xferp);
-		break;
-
-	case 0xbd:
-		fatal("[ SCSI 0x%02x (len %i), TODO: ", xferp->cmd[0],
-		    xferp->cmd_len);
-		for (i=0; i<(ssize_t)xferp->cmd_len; i++)
-			fatal(" %02x", xferp->cmd[i]);
-		fatal(" ]\n");
-
-		/*
-		 *  Used by Windows NT?
-		 *
-		 *  Not documented in http://www.danbbs.dk/~dino/
-		 *		SCSI/SCSI2-D.html.
-		 *  Google gave the answer "MECHANISM_STATUS" for ATAPI. Hm.
-		 */
-
-		if (xferp->cmd_len < 12) {
-			fatal("WEIRD LEN?\n");
-			retlen = 8;
-		} else {
-			retlen = xferp->cmd[8] * 256 + xferp->cmd[9];
-		}
-
-		/*  Return data:  */
-		scsi_transfer_allocbuf(&xferp->data_in_len,
-		    &xferp->data_in, retlen, 1);
-
-		diskimage__return_default_status_and_message(xferp);
-
-		break;
-
-	default:
-		debug("[ UNIMPLEMENTED SCSI command 0x%02x, disk id=%i",
-		    xferp->cmd[0], id);
-		// exit(1);
-	}
-
-	debug(" ]\n");
-
-	return 1;
-}
-
-
diff -Nru gxemul-0.6.2/src/disk/Makefile.skel gxemul-0.7.0+dfsg/src/disk/Makefile.skel
--- gxemul-0.6.2/src/disk/Makefile.skel	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/disk/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #  Makefile for GXemul src/disk
 #
 
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(DINCLUDE)
+CFLAGS=$(CWARNINGS) $(COPTIM) $(DINCLUDE)
 
 OBJS=bootblock.o bootblock_apple.o bootblock_iso9660.o \
 	diskimage.o diskimage_scsicmd.o
diff -Nru gxemul-0.6.2/src/file/file_android.c gxemul-0.7.0+dfsg/src/file/file_android.c
--- gxemul-0.6.2/src/file/file_android.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_android.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,235 @@
+/*
+ *  Copyright (C) 2018  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Android boot.img file support
+ */
+
+/*  Note: Included from file.c.  */
+
+
+struct android_header {
+	uint8_t		magic[8];
+
+	uint32_t	kernel_size;
+	uint32_t	kernel_addr;
+	uint32_t	ramdisk_size;
+	uint32_t	ramdisk_addr;
+	uint32_t	second_size;
+	uint32_t	second_addr;
+
+	uint32_t	tags_addr;
+	uint32_t	page_size;
+
+	uint32_t	header_version;	/*  0: Pre-Android-9   1: Android 9 or higher  */
+	uint32_t	os_version;
+
+	uint8_t		name[16];
+	uint8_t		cmdline[512];
+	uint32_t	id[8];
+	uint8_t		extra_cmdline[1024];
+
+	/*  Android 9 or higher:  */
+	uint32_t	recovery_dtbo_size;
+	uint64_t	recovery_dtbo_offset;
+	uint32_t	header_size;
+};
+
+
+/*
+ *  file_load_android():
+ *
+ *  Loads an Android boot.img file into the emulated memory.  The entry point
+ *  is stored in the specified CPU's registers.
+ *
+ *  See https://source.android.com/devices/bootloader/recovery-image and
+ *  https://source.android.com/devices/bootloader/boot-image-header for more
+ *  details.
+ */
+static void file_load_android(struct machine *m, struct memory *mem,
+	char *filename, int flags,
+	uint64_t *entrypointp, int arch, int *byte_orderp)
+{
+	FILE *f;
+	int encoding = ELFDATA2LSB;
+	uint32_t page_size;
+	uint32_t kernel_size, kernel_addr, kernel_pages;
+	uint32_t ramdisk_size, ramdisk_addr, ramdisk_pages;
+	uint32_t second_size, second_addr, second_pages;
+	struct android_header android_header;
+	unsigned char buf[65536];
+
+	f = fopen(filename, "r");
+	if (f == NULL) {
+		perror(filename);
+		exit(1);
+	}
+
+	int hlen = fread(&android_header, 1, sizeof(android_header), f);
+	if (hlen != sizeof(android_header)) {
+		fprintf(stderr, "%s: not a complete Android boot.img file\n",
+		    filename);
+		exit(1);
+	}
+
+	unencode(page_size, &android_header.page_size, uint32_t);
+	debug("Android boot.img format, page size 0x%x\n", page_size);
+
+	unencode(kernel_size, &android_header.kernel_size, uint32_t);
+	unencode(kernel_addr, &android_header.kernel_addr, uint32_t);
+	kernel_pages = (kernel_size + (page_size - 1)) / page_size;
+	if (kernel_size > 0) {
+		debug("kernel: 0x%x bytes (%i pages) at addr 0x%08x\n", kernel_size, kernel_pages, kernel_addr);
+
+		fseek(f, page_size * 1, SEEK_SET);
+
+		uint32_t len_to_load = kernel_size;
+		uint32_t vaddr = kernel_addr;
+
+		while (len_to_load != 0) {
+			int len = len_to_load > sizeof(buf) ? sizeof(buf) : len_to_load;
+			int len_read = fread(buf, 1, len, f);
+			if (len != len_read) {
+				fprintf(stderr, "could not read from %s\n", filename);
+				exit(1);
+			}
+
+			/*  printf("fread len=%i vaddr=%x buf[0..]=%02x %02x %02x\n",
+			    (int)len, (int)vaddr, buf[0], buf[1], buf[2]);  */
+
+			int len2 = 0;
+			uint64_t vaddr1 = vaddr &
+			    ((1 << BITS_PER_MEMBLOCK) - 1);
+			uint64_t vaddr2 = (vaddr +
+			    len) & ((1 << BITS_PER_MEMBLOCK) - 1);
+			if (vaddr2 < vaddr1) {
+				len2 = len - vaddr2;
+				m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+				    &buf[0], len2, MEM_WRITE, NO_EXCEPTIONS);
+			}
+			m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr + len2,
+			    &buf[len2], len-len2, MEM_WRITE, NO_EXCEPTIONS);
+
+			vaddr += len;
+			len_to_load -= len;
+		}
+	} else {
+		fatal("kernel_size = 0?\n");
+		exit(1);
+	}
+
+	unencode(ramdisk_size, &android_header.ramdisk_size, uint32_t);
+	unencode(ramdisk_addr, &android_header.ramdisk_addr, uint32_t);
+	ramdisk_pages = (ramdisk_size + (page_size - 1)) / page_size;
+	if (ramdisk_size > 0) {
+		debug("ramdisk: 0x%x bytes (%i pages) at addr 0x%08x\n", ramdisk_size, ramdisk_pages, ramdisk_addr);
+
+		fseek(f, page_size * (1 + kernel_pages), SEEK_SET);
+
+		uint32_t len_to_load = ramdisk_size;
+		uint32_t vaddr = ramdisk_addr;
+
+		while (len_to_load != 0) {
+			int len = len_to_load > sizeof(buf) ? sizeof(buf) : len_to_load;
+			int len_read = fread(buf, 1, len, f);
+			if (len != len_read) {
+				fprintf(stderr, "could not read from %s\n", filename);
+				exit(1);
+			}
+
+			/*  printf("fread len=%i vaddr=%x buf[0..]=%02x %02x %02x\n",
+			    (int)len, (int)vaddr, buf[0], buf[1], buf[2]);  */
+
+			int len2 = 0;
+			uint64_t vaddr1 = vaddr &
+			    ((1 << BITS_PER_MEMBLOCK) - 1);
+			uint64_t vaddr2 = (vaddr +
+			    len) & ((1 << BITS_PER_MEMBLOCK) - 1);
+			if (vaddr2 < vaddr1) {
+				len2 = len - vaddr2;
+				m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+				    &buf[0], len2, MEM_WRITE, NO_EXCEPTIONS);
+			}
+			m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr + len2,
+			    &buf[len2], len-len2, MEM_WRITE, NO_EXCEPTIONS);
+
+			vaddr += len;
+			len_to_load -= len;
+		}
+	}
+
+	unencode(second_size, &android_header.second_size, uint32_t);
+	unencode(second_addr, &android_header.second_addr, uint32_t);
+	second_pages = (second_size + (page_size - 1)) / page_size;
+	if (second_size > 0) {
+		debug("second: 0x%x bytes (%i pages) at addr 0x%08x\n", second_size, second_pages, second_addr);
+
+		fseek(f, page_size * (1 + kernel_pages + ramdisk_pages), SEEK_SET);
+
+		uint32_t len_to_load = second_size;
+		uint32_t vaddr = second_addr;
+
+		while (len_to_load != 0) {
+			int len = len_to_load > sizeof(buf) ? sizeof(buf) : len_to_load;
+			int len_read = fread(buf, 1, len, f);
+			if (len != len_read) {
+				fprintf(stderr, "could not read from %s\n", filename);
+				exit(1);
+			}
+
+			/*  printf("fread len=%i vaddr=%x buf[0..]=%02x %02x %02x\n",
+			    (int)len, (int)vaddr, buf[0], buf[1], buf[2]);  */
+
+			int len2 = 0;
+			uint64_t vaddr1 = vaddr &
+			    ((1 << BITS_PER_MEMBLOCK) - 1);
+			uint64_t vaddr2 = (vaddr +
+			    len) & ((1 << BITS_PER_MEMBLOCK) - 1);
+			if (vaddr2 < vaddr1) {
+				len2 = len - vaddr2;
+				m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+				    &buf[0], len2, MEM_WRITE, NO_EXCEPTIONS);
+			}
+			m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr + len2,
+			    &buf[len2], len-len2, MEM_WRITE, NO_EXCEPTIONS);
+
+			vaddr += len;
+			len_to_load -= len;
+		}
+	}
+
+	fclose(f);
+
+	*entrypointp = (int32_t)kernel_addr;
+
+	if (encoding == ELFDATA2LSB)
+		*byte_orderp = EMUL_LITTLE_ENDIAN;
+	else
+		*byte_orderp = EMUL_BIG_ENDIAN;
+
+	n_executables_loaded ++;
+}
+
diff -Nru gxemul-0.6.2/src/file/file_android.cc gxemul-0.7.0+dfsg/src/file/file_android.cc
--- gxemul-0.6.2/src/file/file_android.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_android.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,235 +0,0 @@
-/*
- *  Copyright (C) 2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Android boot.img file support
- */
-
-/*  Note: Included from file.c.  */
-
-
-struct android_header {
-	uint8_t		magic[8];
-
-	uint32_t	kernel_size;
-	uint32_t	kernel_addr;
-	uint32_t	ramdisk_size;
-	uint32_t	ramdisk_addr;
-	uint32_t	second_size;
-	uint32_t	second_addr;
-
-	uint32_t	tags_addr;
-	uint32_t	page_size;
-
-	uint32_t	header_version;	/*  0: Pre-Android-9   1: Android 9 or higher  */
-	uint32_t	os_version;
-
-	uint8_t		name[16];
-	uint8_t		cmdline[512];
-	uint32_t	id[8];
-	uint8_t		extra_cmdline[1024];
-
-	/*  Android 9 or higher:  */
-	uint32_t	recovery_dtbo_size;
-	uint64_t	recovery_dtbo_offset;
-	uint32_t	header_size;
-};
-
-
-/*
- *  file_load_android():
- *
- *  Loads an Android boot.img file into the emulated memory.  The entry point
- *  is stored in the specified CPU's registers.
- *
- *  See https://source.android.com/devices/bootloader/recovery-image and
- *  https://source.android.com/devices/bootloader/boot-image-header for more
- *  details.
- */
-static void file_load_android(struct machine *m, struct memory *mem,
-	char *filename, int flags,
-	uint64_t *entrypointp, int arch, int *byte_orderp)
-{
-	FILE *f;
-	int encoding = ELFDATA2LSB;
-	uint32_t page_size;
-	uint32_t kernel_size, kernel_addr, kernel_pages;
-	uint32_t ramdisk_size, ramdisk_addr, ramdisk_pages;
-	uint32_t second_size, second_addr, second_pages;
-	struct android_header android_header;
-	unsigned char buf[65536];
-
-	f = fopen(filename, "r");
-	if (f == NULL) {
-		perror(filename);
-		exit(1);
-	}
-
-	int hlen = fread(&android_header, 1, sizeof(android_header), f);
-	if (hlen != sizeof(android_header)) {
-		fprintf(stderr, "%s: not a complete Android boot.img file\n",
-		    filename);
-		exit(1);
-	}
-
-	unencode(page_size, &android_header.page_size, uint32_t);
-	debug("Android boot.img format, page size 0x%x\n", page_size);
-
-	unencode(kernel_size, &android_header.kernel_size, uint32_t);
-	unencode(kernel_addr, &android_header.kernel_addr, uint32_t);
-	kernel_pages = (kernel_size + (page_size - 1)) / page_size;
-	if (kernel_size > 0) {
-		debug("kernel: 0x%x bytes (%i pages) at addr 0x%08x\n", kernel_size, kernel_pages, kernel_addr);
-
-		fseek(f, page_size * 1, SEEK_SET);
-
-		uint32_t len_to_load = kernel_size;
-		uint32_t vaddr = kernel_addr;
-
-		while (len_to_load != 0) {
-			int len = len_to_load > sizeof(buf) ? sizeof(buf) : len_to_load;
-			int len_read = fread(buf, 1, len, f);
-			if (len != len_read) {
-				fprintf(stderr, "could not read from %s\n", filename);
-				exit(1);
-			}
-
-			/*  printf("fread len=%i vaddr=%x buf[0..]=%02x %02x %02x\n",
-			    (int)len, (int)vaddr, buf[0], buf[1], buf[2]);  */
-
-			int len2 = 0;
-			uint64_t vaddr1 = vaddr &
-			    ((1 << BITS_PER_MEMBLOCK) - 1);
-			uint64_t vaddr2 = (vaddr +
-			    len) & ((1 << BITS_PER_MEMBLOCK) - 1);
-			if (vaddr2 < vaddr1) {
-				len2 = len - vaddr2;
-				m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
-				    &buf[0], len2, MEM_WRITE, NO_EXCEPTIONS);
-			}
-			m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr + len2,
-			    &buf[len2], len-len2, MEM_WRITE, NO_EXCEPTIONS);
-
-			vaddr += len;
-			len_to_load -= len;
-		}
-	} else {
-		fatal("kernel_size = 0?\n");
-		exit(1);
-	}
-
-	unencode(ramdisk_size, &android_header.ramdisk_size, uint32_t);
-	unencode(ramdisk_addr, &android_header.ramdisk_addr, uint32_t);
-	ramdisk_pages = (ramdisk_size + (page_size - 1)) / page_size;
-	if (ramdisk_size > 0) {
-		debug("ramdisk: 0x%x bytes (%i pages) at addr 0x%08x\n", ramdisk_size, ramdisk_pages, ramdisk_addr);
-
-		fseek(f, page_size * (1 + kernel_pages), SEEK_SET);
-
-		uint32_t len_to_load = ramdisk_size;
-		uint32_t vaddr = ramdisk_addr;
-
-		while (len_to_load != 0) {
-			int len = len_to_load > sizeof(buf) ? sizeof(buf) : len_to_load;
-			int len_read = fread(buf, 1, len, f);
-			if (len != len_read) {
-				fprintf(stderr, "could not read from %s\n", filename);
-				exit(1);
-			}
-
-			/*  printf("fread len=%i vaddr=%x buf[0..]=%02x %02x %02x\n",
-			    (int)len, (int)vaddr, buf[0], buf[1], buf[2]);  */
-
-			int len2 = 0;
-			uint64_t vaddr1 = vaddr &
-			    ((1 << BITS_PER_MEMBLOCK) - 1);
-			uint64_t vaddr2 = (vaddr +
-			    len) & ((1 << BITS_PER_MEMBLOCK) - 1);
-			if (vaddr2 < vaddr1) {
-				len2 = len - vaddr2;
-				m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
-				    &buf[0], len2, MEM_WRITE, NO_EXCEPTIONS);
-			}
-			m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr + len2,
-			    &buf[len2], len-len2, MEM_WRITE, NO_EXCEPTIONS);
-
-			vaddr += len;
-			len_to_load -= len;
-		}
-	}
-
-	unencode(second_size, &android_header.second_size, uint32_t);
-	unencode(second_addr, &android_header.second_addr, uint32_t);
-	second_pages = (second_size + (page_size - 1)) / page_size;
-	if (second_size > 0) {
-		debug("second: 0x%x bytes (%i pages) at addr 0x%08x\n", second_size, second_pages, second_addr);
-
-		fseek(f, page_size * (1 + kernel_pages + ramdisk_pages), SEEK_SET);
-
-		uint32_t len_to_load = second_size;
-		uint32_t vaddr = second_addr;
-
-		while (len_to_load != 0) {
-			int len = len_to_load > sizeof(buf) ? sizeof(buf) : len_to_load;
-			int len_read = fread(buf, 1, len, f);
-			if (len != len_read) {
-				fprintf(stderr, "could not read from %s\n", filename);
-				exit(1);
-			}
-
-			/*  printf("fread len=%i vaddr=%x buf[0..]=%02x %02x %02x\n",
-			    (int)len, (int)vaddr, buf[0], buf[1], buf[2]);  */
-
-			int len2 = 0;
-			uint64_t vaddr1 = vaddr &
-			    ((1 << BITS_PER_MEMBLOCK) - 1);
-			uint64_t vaddr2 = (vaddr +
-			    len) & ((1 << BITS_PER_MEMBLOCK) - 1);
-			if (vaddr2 < vaddr1) {
-				len2 = len - vaddr2;
-				m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
-				    &buf[0], len2, MEM_WRITE, NO_EXCEPTIONS);
-			}
-			m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr + len2,
-			    &buf[len2], len-len2, MEM_WRITE, NO_EXCEPTIONS);
-
-			vaddr += len;
-			len_to_load -= len;
-		}
-	}
-
-	fclose(f);
-
-	*entrypointp = (int32_t)kernel_addr;
-
-	if (encoding == ELFDATA2LSB)
-		*byte_orderp = EMUL_LITTLE_ENDIAN;
-	else
-		*byte_orderp = EMUL_BIG_ENDIAN;
-
-	n_executables_loaded ++;
-}
-
diff -Nru gxemul-0.6.2/src/file/file_aout.c gxemul-0.7.0+dfsg/src/file/file_aout.c
--- gxemul-0.6.2/src/file/file_aout.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_aout.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,253 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: a.out executable file support
+ *
+ *  Also: b.out was an a.out-like format used by i960 systems.
+ */
+
+/*  Note: Included from file.c.  */
+
+
+#include "thirdparty/exec_aout.h"
+#include "thirdparty/exec_bout.h"
+
+
+#define	AOUT_FLAG_DECOSF1				1
+#define	AOUT_FLAG_FROM_BEGINNING			2
+#define	AOUT_FLAG_VADDR_ZERO_HACK			4
+#define	AOUT_FLAG_NO_SIZES				8
+#define	AOUT_FLAG_DATA_AT_END_MAY_BE_OMITTED		16
+#define	AOUT_FLAG_I960_BOUT				32
+
+struct aout_symbol {
+	uint32_t	strindex;
+	uint32_t	type;
+	uint32_t	addr;
+};
+
+
+/*
+ *  file_load_aout():
+ *
+ *  Loads an a.out binary image into the emulated memory.  The entry point
+ *  (read from the a.out header) is stored in the specified CPU's registers.
+ *
+ *  TODO:  This has to be rewritten / corrected to support multiple a.out
+ *         formats, where text/data are aligned differently.
+ */
+static void file_load_aout(struct machine *m, struct memory *mem,
+	char *filename, int flags,
+	uint64_t *entrypointp, int arch, int *byte_orderp)
+{
+	struct exec aout_header;
+	struct bout_exec bout_header;
+	FILE *f;
+	int len;
+	int encoding = ELFDATA2LSB;
+	uint32_t entry, datasize, textsize;
+	int32_t symbsize = 0;
+	uint32_t vaddr, total_len;
+	unsigned char buf[65536];
+	unsigned char *syms;
+
+	if (m->cpus[0]->byte_order == EMUL_BIG_ENDIAN)
+		encoding = ELFDATA2MSB;
+
+	f = fopen(filename, "r");
+	if (f == NULL) {
+		perror(filename);
+		exit(1);
+	}
+
+	if (flags & AOUT_FLAG_I960_BOUT) {
+		len = fread(&bout_header, 1, sizeof(bout_header), f);
+		if (len != sizeof(bout_header)) {
+			fprintf(stderr, "%s: not a complete b.out image\n",
+			    filename);
+			exit(1);
+		}
+
+		unencode(entry, &bout_header.a_entry, uint32_t);
+		debug("b.out, entry point 0x%08lx\n", (long)entry);
+		vaddr = entry;
+
+		unencode(textsize, &bout_header.a_text, uint32_t);
+		unencode(datasize, &bout_header.a_data, uint32_t);
+		debug("text + data = %i + %i bytes\n", textsize, datasize);
+
+		unencode(symbsize, &bout_header.a_syms, uint32_t);
+	} else if (flags & AOUT_FLAG_DECOSF1) {
+		if (fread(&buf, 1, 32, f) != 32) {
+			perror(filename);
+			exit(1);
+		}
+		vaddr = buf[16] + (buf[17] << 8) +
+		    (buf[18] << 16) + ((uint64_t)buf[19] << 24);
+		entry = buf[20] + (buf[21] << 8) +
+		    (buf[22] << 16) + ((uint64_t)buf[23] << 24);
+		debug("OSF1 a.out, load address 0x%08lx, "
+		    "entry point 0x%08x\n", (long)vaddr, (long)entry);
+		symbsize = 0;
+		fseek(f, 0, SEEK_END);
+		/*  This is of course wrong, but should work anyway:  */
+		textsize = ftello(f) - 512;
+		datasize = 0;
+		fseek(f, 512, SEEK_SET);
+	} else if (flags & AOUT_FLAG_NO_SIZES) {
+		fseek(f, 0, SEEK_END);
+		textsize = ftello(f) - 32;
+		datasize = 0;
+		vaddr = entry = 0;
+		fseek(f, 32, SEEK_SET);
+	} else {
+		len = fread(&aout_header, 1, sizeof(aout_header), f);
+		if (len != sizeof(aout_header)) {
+			fprintf(stderr, "%s: not a complete a.out image\n",
+			    filename);
+			exit(1);
+		}
+
+		unencode(entry, &aout_header.a_entry, uint32_t);
+		debug("a.out, entry point 0x%08lx\n", (long)entry);
+		vaddr = entry;
+
+		if (flags & AOUT_FLAG_VADDR_ZERO_HACK)
+			vaddr = 0;
+
+		unencode(textsize, &aout_header.a_text, uint32_t);
+		unencode(datasize, &aout_header.a_data, uint32_t);
+		debug("text + data = %i + %i bytes\n", textsize, datasize);
+
+		unencode(symbsize, &aout_header.a_syms, uint32_t);
+	}
+
+	if (flags & AOUT_FLAG_FROM_BEGINNING) {
+		fseek(f, 0, SEEK_SET);
+		vaddr &= ~0xfff;
+	}
+
+	/*  Load text and data:  */
+	total_len = textsize + datasize;
+	while (total_len != 0) {
+		len = total_len > sizeof(buf) ? sizeof(buf) : total_len;
+		len = fread(buf, 1, len, f);
+
+		/*  printf("fread len=%i vaddr=%x buf[0..]=%02x %02x %02x\n",
+		    (int)len, (int)vaddr, buf[0], buf[1], buf[2]);  */
+
+		if (len > 0) {
+			int len2 = 0;
+			uint64_t vaddr1 = vaddr &
+			    ((1 << BITS_PER_MEMBLOCK) - 1);
+			uint64_t vaddr2 = (vaddr +
+			    len) & ((1 << BITS_PER_MEMBLOCK) - 1);
+			if (vaddr2 < vaddr1) {
+				len2 = len - vaddr2;
+				m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+				    &buf[0], len2, MEM_WRITE, NO_EXCEPTIONS);
+			}
+			m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr + len2,
+			    &buf[len2], len-len2, MEM_WRITE, NO_EXCEPTIONS);
+		} else {
+			if (flags & AOUT_FLAG_DATA_AT_END_MAY_BE_OMITTED)
+				break;
+			else {
+				fprintf(stderr, "could not read from %s,"
+				    " wanted to read %i bytes\n", filename,
+				    (int) total_len);
+				exit(1);
+			}
+		}
+
+		vaddr += len;
+		total_len -= len;
+	}
+
+	if (symbsize != 0) {
+		struct aout_symbol *aout_symbol_ptr;
+		int i, n_symbols;
+		uint32_t type, addr, str_index;
+		uint32_t strings_len;
+		char *string_symbols;
+		off_t oldpos;
+
+		debug("symbols: %i bytes @ 0x%x\n", symbsize, (int)ftello(f));
+		CHECK_ALLOCATION(syms = (unsigned char *) malloc(symbsize));
+		len = fread(syms, 1, symbsize, f);
+		if (len != symbsize) {
+			fprintf(stderr, "error reading symbols from %s\n",
+			    filename);
+			exit(1);
+		}
+
+		oldpos = ftello(f);
+		fseek(f, 0, SEEK_END);
+		strings_len = ftello(f) - oldpos;
+		fseek(f, oldpos, SEEK_SET);
+		debug("strings: %i bytes @ 0x%x\n", strings_len,(int)ftello(f));
+		CHECK_ALLOCATION(string_symbols = (char *) malloc(strings_len));
+		if (fread(string_symbols, 1, strings_len, f) != strings_len) {
+			fprintf(stderr, "Could not read symbols from %s?\n", filename);
+			perror("fread");
+			exit(1);
+		}
+
+		aout_symbol_ptr = (struct aout_symbol *) (void*) syms;
+		n_symbols = symbsize / sizeof(struct aout_symbol);
+		i = 0;
+		while (i < n_symbols) {
+			unencode(str_index, &aout_symbol_ptr[i].strindex,
+			    uint32_t);
+			unencode(type, &aout_symbol_ptr[i].type, uint32_t);
+			unencode(addr, &aout_symbol_ptr[i].addr, uint32_t);
+
+			/*  debug("symbol type 0x%04x @ 0x%08x: %s\n",
+			    type, addr, string_symbols + str_index);  */
+
+			if (type != 0 && addr != 0)
+				add_symbol_name(&m->symbol_context,
+				    addr, 0, string_symbols + str_index, 0, -1);
+			i++;
+		}
+
+		free(string_symbols);
+		free(syms);
+	}
+
+	fclose(f);
+
+	*entrypointp = (int32_t)entry;
+
+	if (encoding == ELFDATA2LSB)
+		*byte_orderp = EMUL_LITTLE_ENDIAN;
+	else
+		*byte_orderp = EMUL_BIG_ENDIAN;
+
+	n_executables_loaded ++;
+}
+
diff -Nru gxemul-0.6.2/src/file/file_aout.cc gxemul-0.7.0+dfsg/src/file/file_aout.cc
--- gxemul-0.6.2/src/file/file_aout.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_aout.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,230 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: a.out executable file support
- */
-
-/*  Note: Included from file.c.  */
-
-
-#include "thirdparty/exec_aout.h"
-
-
-#define	AOUT_FLAG_DECOSF1		1
-#define	AOUT_FLAG_FROM_BEGINNING	2
-#define	AOUT_FLAG_VADDR_ZERO_HACK	4
-#define	AOUT_FLAG_NO_SIZES		8
-
-struct aout_symbol {
-	uint32_t	strindex;
-	uint32_t	type;
-	uint32_t	addr;
-};
-
-
-/*
- *  file_load_aout():
- *
- *  Loads an a.out binary image into the emulated memory.  The entry point
- *  (read from the a.out header) is stored in the specified CPU's registers.
- *
- *  TODO:  This has to be rewritten / corrected to support multiple a.out
- *         formats, where text/data are aligned differently.
- */
-static void file_load_aout(struct machine *m, struct memory *mem,
-	char *filename, int flags,
-	uint64_t *entrypointp, int arch, int *byte_orderp)
-{
-	struct exec aout_header;
-	FILE *f;
-	int len;
-	int encoding = ELFDATA2LSB;
-	uint32_t entry, datasize, textsize;
-	int32_t symbsize = 0;
-	uint32_t vaddr, total_len;
-	unsigned char buf[65536];
-	unsigned char *syms;
-
-	if (m->cpus[0]->byte_order == EMUL_BIG_ENDIAN)
-		encoding = ELFDATA2MSB;
-
-	f = fopen(filename, "r");
-	if (f == NULL) {
-		perror(filename);
-		exit(1);
-	}
-
-	if (flags & AOUT_FLAG_DECOSF1) {
-		if (fread(&buf, 1, 32, f) != 32) {
-			perror(filename);
-			exit(1);
-		}
-		vaddr = buf[16] + (buf[17] << 8) +
-		    (buf[18] << 16) + ((uint64_t)buf[19] << 24);
-		entry = buf[20] + (buf[21] << 8) +
-		    (buf[22] << 16) + ((uint64_t)buf[23] << 24);
-		debug("OSF1 a.out, load address 0x%08lx, "
-		    "entry point 0x%08x\n", (long)vaddr, (long)entry);
-		symbsize = 0;
-		fseek(f, 0, SEEK_END);
-		/*  This is of course wrong, but should work anyway:  */
-		textsize = ftello(f) - 512;
-		datasize = 0;
-		fseek(f, 512, SEEK_SET);
-	} else if (flags & AOUT_FLAG_NO_SIZES) {
-		fseek(f, 0, SEEK_END);
-		textsize = ftello(f) - 32;
-		datasize = 0;
-		vaddr = entry = 0;
-		fseek(f, 32, SEEK_SET);
-	} else {
-		len = fread(&aout_header, 1, sizeof(aout_header), f);
-		if (len != sizeof(aout_header)) {
-			fprintf(stderr, "%s: not a complete a.out image\n",
-			    filename);
-			exit(1);
-		}
-
-		unencode(entry, &aout_header.a_entry, uint32_t);
-		debug("a.out, entry point 0x%08lx\n", (long)entry);
-		vaddr = entry;
-
-		if (flags & AOUT_FLAG_VADDR_ZERO_HACK)
-			vaddr = 0;
-
-		unencode(textsize, &aout_header.a_text, uint32_t);
-		unencode(datasize, &aout_header.a_data, uint32_t);
-		debug("text + data = %i + %i bytes\n", textsize, datasize);
-
-		unencode(symbsize, &aout_header.a_syms, uint32_t);
-	}
-
-	if (flags & AOUT_FLAG_FROM_BEGINNING) {
-		fseek(f, 0, SEEK_SET);
-		vaddr &= ~0xfff;
-	}
-
-	/*  Load text and data:  */
-	total_len = textsize + datasize;
-	while (total_len != 0) {
-		len = total_len > sizeof(buf) ? sizeof(buf) : total_len;
-		len = fread(buf, 1, len, f);
-
-		/*  printf("fread len=%i vaddr=%x buf[0..]=%02x %02x %02x\n",
-		    (int)len, (int)vaddr, buf[0], buf[1], buf[2]);  */
-
-		if (len > 0) {
-			int len2 = 0;
-			uint64_t vaddr1 = vaddr &
-			    ((1 << BITS_PER_MEMBLOCK) - 1);
-			uint64_t vaddr2 = (vaddr +
-			    len) & ((1 << BITS_PER_MEMBLOCK) - 1);
-			if (vaddr2 < vaddr1) {
-				len2 = len - vaddr2;
-				m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
-				    &buf[0], len2, MEM_WRITE, NO_EXCEPTIONS);
-			}
-			m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr + len2,
-			    &buf[len2], len-len2, MEM_WRITE, NO_EXCEPTIONS);
-		} else {
-			if (flags & AOUT_FLAG_DECOSF1)
-				break;
-			else {
-				fprintf(stderr, "could not read from %s,"
-				    " wanted to read %i bytes\n", filename,
-				    (int) total_len);
-				exit(1);
-			}
-		}
-
-		vaddr += len;
-		total_len -= len;
-	}
-
-	if (symbsize != 0) {
-		struct aout_symbol *aout_symbol_ptr;
-		int i, n_symbols;
-		uint32_t type, addr, str_index;
-		uint32_t strings_len;
-		char *string_symbols;
-		off_t oldpos;
-
-		debug("symbols: %i bytes @ 0x%x\n", symbsize, (int)ftello(f));
-		CHECK_ALLOCATION(syms = (unsigned char *) malloc(symbsize));
-		len = fread(syms, 1, symbsize, f);
-		if (len != symbsize) {
-			fprintf(stderr, "error reading symbols from %s\n",
-			    filename);
-			exit(1);
-		}
-
-		oldpos = ftello(f);
-		fseek(f, 0, SEEK_END);
-		strings_len = ftello(f) - oldpos;
-		fseek(f, oldpos, SEEK_SET);
-		debug("strings: %i bytes @ 0x%x\n", strings_len,(int)ftello(f));
-		CHECK_ALLOCATION(string_symbols = (char *) malloc(strings_len));
-		if (fread(string_symbols, 1, strings_len, f) != strings_len) {
-			fprintf(stderr, "Could not read symbols from %s?\n", filename);
-			perror("fread");
-			exit(1);
-		}
-
-		aout_symbol_ptr = (struct aout_symbol *) (void*) syms;
-		n_symbols = symbsize / sizeof(struct aout_symbol);
-		i = 0;
-		while (i < n_symbols) {
-			unencode(str_index, &aout_symbol_ptr[i].strindex,
-			    uint32_t);
-			unencode(type, &aout_symbol_ptr[i].type, uint32_t);
-			unencode(addr, &aout_symbol_ptr[i].addr, uint32_t);
-
-			/*  debug("symbol type 0x%04x @ 0x%08x: %s\n",
-			    type, addr, string_symbols + str_index);  */
-
-			if (type != 0 && addr != 0)
-				add_symbol_name(&m->symbol_context,
-				    addr, 0, string_symbols + str_index, 0, -1);
-			i++;
-		}
-
-		free(string_symbols);
-		free(syms);
-	}
-
-	fclose(f);
-
-	*entrypointp = (int32_t)entry;
-
-	if (encoding == ELFDATA2LSB)
-		*byte_orderp = EMUL_LITTLE_ENDIAN;
-	else
-		*byte_orderp = EMUL_BIG_ENDIAN;
-
-	n_executables_loaded ++;
-}
-
diff -Nru gxemul-0.6.2/src/file/file.c gxemul-0.7.0+dfsg/src/file/file.c
--- gxemul-0.6.2/src/file/file.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,386 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  This module contains functions which load executable images into (emulated)
+ *  memory. File formats recognized so far are:
+ *
+ *	android		Android boot.img format
+ *	a.out		traditional old-style Unix binary format
+ *	Mach-O		MacOS X format, etc.
+ *	ecoff		old format used by Ultrix, Windows NT, IRIX, etc
+ *	srec		Motorola SREC format
+ *	raw		raw binaries, "address:[skiplen:[entrypoint:]]filename"
+ *	ELF		32-bit and 64-bit ELFs
+ *
+ *  If a file is not of one of the above mentioned formats, it is assumed
+ *  to be symbol data generated by 'nm' or 'nm -S'.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+
+#include "cpu.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "symbol.h"
+
+
+extern int quiet_mode;
+extern int verbose;
+
+
+/*
+ *  This should be increased by every routine here that actually loads an
+ *  executable file into memory.  (For example, loading a symbol file should
+ *  NOT increase this.)
+ */
+static int n_executables_loaded = 0;
+
+
+#include "thirdparty/exec_elf.h"		/*  Ugly; needed for ELFDATA2LSB etc.  */
+
+#define	unencode(var,dataptr,typ)	{				\
+		int Wi;  unsigned char Wb;				\
+		unsigned char *Wp = (unsigned char *) dataptr;		\
+		int Wlen = sizeof(typ);					\
+		var = 0;						\
+		for (Wi=0; Wi<Wlen; Wi++) {				\
+			if (encoding == ELFDATA2LSB)			\
+				Wb = Wp[Wlen-1 - Wi];			\
+			else						\
+				Wb = Wp[Wi];				\
+			if (Wi == 0 && (Wb & 0x80)) {			\
+				var --;	/*  set var to -1 :-)  */	\
+				var <<= 8;				\
+			}						\
+			var |= Wb;					\
+			if (Wi < Wlen-1)				\
+				var <<= 8;				\
+		}							\
+	}
+
+
+#include "file_android.c"
+#include "file_aout.c"
+#include "file_ecoff.c"
+#include "file_elf.c"
+#include "file_macho.c"
+#include "file_raw.c"
+#include "file_srec.c"
+
+
+/*
+ *  file_n_executables_loaded():
+ *
+ *  Returns the number of executable files loaded into emulated memory.
+ */
+int file_n_executables_loaded(void)
+{
+	return n_executables_loaded;
+}
+
+
+/*
+ *  file_load():
+ *
+ *  Sense the file format of a file (ELF, a.out, ecoff), and call the
+ *  right file_load_XXX() function.  If the file isn't of a recognized
+ *  binary format, assume that it contains symbol definitions.
+ *
+ *  If the filename doesn't exist, try to treat the name as
+ *   "address:filename" and load the file as a raw binary.
+ */
+void file_load(struct machine *machine, struct memory *mem,
+	char *filename, uint64_t *entrypointp,
+	int arch, uint64_t *gpp, int *byte_orderp, uint64_t *tocp)
+{
+	int old_quiet_mode;
+	FILE *f;
+	const char *tmpdir = getenv("TMPDIR") == NULL?
+	    DEFAULT_TMP_DIR : getenv("TMPDIR");
+	unsigned char buf[12];
+	unsigned char buf2[2];
+	char tmpname[400];
+	size_t len, len2, i;
+	off_t size;
+
+	if (byte_orderp == NULL) {
+		fprintf(stderr, "file_load(): byte_order == NULL\n");
+		exit(1);
+	}
+
+	if (!arch) {
+		fprintf(stderr, "file_load(): FATAL ERROR: no arch?\n");
+		exit(1);
+	}
+
+	if (mem == NULL || filename == NULL) {
+		fprintf(stderr, "file_load(): mem or filename is NULL\n");
+		exit(1);
+	}
+
+	/*  Skip configuration files:  */
+	if (filename[0] == '@')
+		return;
+
+	debugmsg(SUBSYS_MACHINE, "file", VERBOSITY_INFO, "loading %s%s", filename, verbose >= 2? ":" : "");
+	debug_indentation(1);
+
+	old_quiet_mode = quiet_mode;
+	if (verbose < 1)
+		quiet_mode = 1;
+
+	f = fopen(filename, "r");
+	if (f == NULL) {
+		file_load_raw(machine, mem, filename, entrypointp);
+		goto ret;
+	}
+
+	fseek(f, 0, SEEK_END);
+	size = ftello(f);
+	fseek(f, 0, SEEK_SET);
+
+	memset(buf, 0, sizeof(buf));
+	len = fread(buf, 1, sizeof(buf), f);
+	fseek(f, 510, SEEK_SET);
+	len2 = fread(buf2, 1, sizeof(buf2), f);
+	fclose(f);
+
+	if (len < (signed int)sizeof(buf)) {
+		fprintf(stderr, "\nThis file is too small to contain "
+		    "anything useful\n");
+		exit(1);
+	}
+
+	/*  Is it an ELF?  */
+	if (buf[0] == 0x7f && buf[1]=='E' && buf[2]=='L' && buf[3]=='F') {
+		file_load_elf(machine, mem, filename,
+		    entrypointp, arch, gpp, byte_orderp, tocp);
+		goto ret;
+	}
+
+	/*  Is it an Android boot.img?  */
+	if (memcmp("ANDROID!", &buf[0], 8) == 0) {
+		file_load_android(machine, mem, filename, 0,
+		    entrypointp, arch, byte_orderp);
+		goto ret;
+	}
+
+	/*  Is it an a.out?  */
+	if (buf[0]==0x00 && buf[1]==0x8b && buf[2]==0x01 && buf[3]==0x07) {
+		/*  MIPS a.out  */
+		file_load_aout(machine, mem, filename, 0,
+		    entrypointp, arch, byte_orderp);
+		goto ret;
+	}
+	if ((buf[0]==0x0d && buf[1]==0x01 && buf[2]==0x00 && buf[3]==0x00) ||
+	    (buf[0]==0x00 && buf[1]==0x00 && buf[2]==0x01 && buf[3]==0x0d)) {
+		/*  i960 b.out  */
+		machine->cpus[0]->byte_order = buf[0] == 0x0d ? EMUL_LITTLE_ENDIAN : EMUL_BIG_ENDIAN;
+		file_load_aout(machine, mem, filename,
+		    AOUT_FLAG_I960_BOUT, entrypointp, arch, byte_orderp);
+		goto ret;
+	}
+	if (buf[0]==0x00 && buf[1]==0x87 && buf[2]==0x01 && buf[3]==0x08) {
+		/*  M68K a.out  */
+		file_load_aout(machine, mem, filename,
+		    AOUT_FLAG_VADDR_ZERO_HACK  /*  for OpenBSD/mac68k  */,
+		    entrypointp, arch, byte_orderp);
+		goto ret;
+	}
+	if (buf[0]==0x00 && buf[1]==0x99 && buf[2]==0x01 && buf[3]==0x07) {
+		/*  OpenBSD/M88K a.out  */
+		file_load_aout(machine, mem, filename, AOUT_FLAG_DATA_AT_END_MAY_BE_OMITTED,
+		    entrypointp, arch, byte_orderp);
+		goto ret;
+	}
+	if (buf[0]==0x00 && buf[1]==0x99 && buf[2]==0x01 && buf[3]==0x0b) {
+		/*  OpenBSD/M88K a.out  */
+		file_load_aout(machine, mem, filename, AOUT_FLAG_FROM_BEGINNING,
+		    entrypointp, arch, byte_orderp);
+		goto ret;
+	}
+	if (buf[0]==0x00 && buf[1]==0x8f && buf[2]==0x01 && buf[3]==0x0b) {
+		/*  ARM a.out  */
+		file_load_aout(machine, mem, filename, AOUT_FLAG_FROM_BEGINNING,
+		    entrypointp, arch, byte_orderp);
+		goto ret;
+	}
+	if (buf[0]==0x00 && buf[1]==0x86 && buf[2]==0x01 && buf[3]==0x0b) {
+		/*  i386 a.out (old OpenBSD and NetBSD etc)  */
+		file_load_aout(machine, mem, filename, AOUT_FLAG_FROM_BEGINNING,
+		    entrypointp, arch, byte_orderp);
+		goto ret;
+	}
+	if (buf[0]==0x01 && buf[1]==0x03 && buf[2]==0x01 && buf[3]==0x07) {
+		/*  SPARC a.out (old 32-bit NetBSD etc)  */
+		file_load_aout(machine, mem, filename, AOUT_FLAG_NO_SIZES,
+		    entrypointp, arch, byte_orderp);
+		goto ret;
+	}
+	if (buf[0]==0x00 && buf[2]==0x00 && buf[8]==0x7a && buf[9]==0x75) {
+		/*  DEC OSF1 on MIPS:  */
+		file_load_aout(machine, mem, filename,
+		    AOUT_FLAG_DECOSF1 | AOUT_FLAG_DATA_AT_END_MAY_BE_OMITTED,
+		    entrypointp, arch, byte_orderp);
+		goto ret;
+	}
+
+	/*
+	 *  Is it a Mach-O file?
+	 */
+	if (buf[0] == 0xfe && buf[1] == 0xed && buf[2] == 0xfa &&
+	    (buf[3] == 0xce || buf[3] == 0xcf)) {
+		file_load_macho(machine, mem, filename, entrypointp,
+		    arch, byte_orderp, buf[3] == 0xcf, 0);
+		goto ret;
+	}
+	if ((buf[0] == 0xce || buf[0] == 0xcf) && buf[1] == 0xfa &&
+	    buf[2] == 0xed && buf[3] == 0xfe) {
+		file_load_macho(machine, mem, filename, entrypointp,
+		    arch, byte_orderp, buf[0] == 0xcf, 1);
+		goto ret;
+	}
+
+	/*
+	 *  Is it an ecoff?
+	 *
+	 *  TODO: What's the deal with the magic value's byte order? Sometimes
+	 *  it seems to be reversed for BE when compared to LE, but not always?
+	 */
+	if (buf[0]+256*buf[1] == ECOFF_MAGIC_MIPSEB ||
+	    buf[0]+256*buf[1] == ECOFF_MAGIC_MIPSEL ||
+	    buf[0]+256*buf[1] == ECOFF_MAGIC_MIPSEB2 ||
+	    buf[0]+256*buf[1] == ECOFF_MAGIC_MIPSEL2 ||
+	    buf[0]+256*buf[1] == ECOFF_MAGIC_MIPSEB3 ||
+	    buf[0]+256*buf[1] == ECOFF_MAGIC_MIPSEL3 ||
+	    buf[1]+256*buf[0] == ECOFF_MAGIC_MIPSEB ||
+	    buf[1]+256*buf[0] == ECOFF_MAGIC_MIPSEL ||
+	    buf[1]+256*buf[0] == ECOFF_MAGIC_MIPSEB2 ||
+	    buf[1]+256*buf[0] == ECOFF_MAGIC_MIPSEL2 ||
+	    buf[1]+256*buf[0] == ECOFF_MAGIC_MIPSEB3 ||
+	    buf[1]+256*buf[0] == ECOFF_MAGIC_MIPSEL3) {
+		file_load_ecoff(machine, mem, filename, entrypointp,
+		    arch, gpp, byte_orderp);
+		goto ret;
+	}
+
+	/*  Is it a Motorola SREC file?  */
+	if ((buf[0]=='S' && buf[1]>='0' && buf[1]<='9')) {
+		file_load_srec(machine, mem, filename, entrypointp);
+		goto ret;
+	}
+
+	/*  gzipped files are not supported:  */
+	if (buf[0]==0x1f && buf[1]==0x8b) {
+		fprintf(stderr, "\nYou need to gunzip the file before you"
+		    " try to use it.\n");
+		exit(1);
+	}
+
+	if (size > 24000000) {
+		fprintf(stderr, "\nThis file is very large (%lli bytes)\n",
+		    (long long)size);
+		fprintf(stderr, "Are you sure it is a kernel and not a disk "
+		    "image? (Use the -d option.)\n");
+		exit(1);
+	}
+
+	if (size == 1474560)
+		fprintf(stderr, "Hm... this file is the size of a 1.44 MB "
+		    "floppy image. Maybe you forgot the\n-d switch?\n");
+
+	/*
+	 *  Ugly hack for Dreamcast:  When booting from a Dreamcast CDROM
+	 *  image, a temporary file is extracted into /tmp/gxemul.*, but this
+	 *  is a "scrambled" raw binary. This code unscrambles it, and loads
+	 *  it as a raw binary.
+	 */
+	snprintf(tmpname, sizeof(tmpname), "%s/gxemul.", tmpdir);
+	if (machine->machine_type == MACHINE_DREAMCAST &&
+	    strncmp(filename, tmpname, strlen(tmpname)) == 0) {
+		char *tmp_filename = (char *) malloc(strlen(filename) + 100);
+		snprintf(tmp_filename, strlen(filename) + 100,
+		    "%s.descrambled", filename);
+		debug("descrambling into %s\n", tmp_filename);
+		dreamcast_descramble(filename, tmp_filename);
+
+		snprintf(tmp_filename, strlen(filename) + 100,
+		    "0x8c010000:%s.descrambled", filename);
+		debug("loading descrambled Dreamcast binary\n");
+		file_load_raw(machine, mem, tmp_filename, entrypointp);
+
+		snprintf(tmp_filename, strlen(filename) + 100,
+		    "%s.descrambled", filename);
+		remove(tmp_filename);
+		free(tmp_filename);
+
+		/*  Hack: Start a "boot from CDROM" sequence:  */
+		*entrypointp = 0x8c000140;
+		goto ret;
+	}
+
+	/*
+	 *  Last resort:  symbol definitions from nm (or nm -S):
+	 *
+	 *  If the buf contains typical 'binary' characters, then print
+	 *  an error message and quit instead of assuming that it is a
+	 *  symbol file.
+	 */
+	for (i=0; i<(signed)sizeof(buf); i++)
+		if (buf[i] < 32 && buf[i] != '\t' &&
+		    buf[i] != '\n' && buf[i] != '\r' &&
+		    buf[i] != '\f') {
+			fprintf(stderr, "\nThe file format of '%s' is "
+			    "unknown.\n\n ", filename);
+			for (i=0; i<(signed)sizeof(buf); i++)
+				fprintf(stderr, " %02x", buf[i]);
+
+			if (len2 == 2 && buf2[0] == 0x55 && buf2[1] == 0xaa)
+				fprintf(stderr, "\n\nIt has a PC-style "
+				    "bootsector marker.");
+
+			fprintf(stderr, "\n\nPossible explanations:\n\n"
+			    "  o)  If this is a disk image, you forgot '-d' "
+			    "on the command line.\n"
+			    "  o)  You are attempting to load a raw binary "
+			    "into emulated memory,\n"
+			    "      but forgot to add the address prefix.\n"
+			    "  o)  This is an unsupported binary format.\n\n");
+			exit(1);
+		}
+
+	symbol_readfile(&machine->symbol_context, filename);
+
+ret:
+	debug_indentation(-1);
+	quiet_mode = old_quiet_mode;
+}
+
diff -Nru gxemul-0.6.2/src/file/file.cc gxemul-0.7.0+dfsg/src/file/file.cc
--- gxemul-0.6.2/src/file/file.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,371 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  This module contains functions which load executable images into (emulated)
- *  memory. File formats recognized so far are:
- *
- *	android		Android boot.img format
- *	a.out		traditional old-style Unix binary format
- *	Mach-O		MacOS X format, etc.
- *	ecoff		old format used by Ultrix, Windows NT, etc
- *	srec		Motorola SREC format
- *	raw		raw binaries, "address:[skiplen:[entrypoint:]]filename"
- *	ELF		32-bit and 64-bit ELFs
- *
- *  If a file is not of one of the above mentioned formats, it is assumed
- *  to be symbol data generated by 'nm' or 'nm -S'.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-
-#include "cpu.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "symbol.h"
-
-
-extern int quiet_mode;
-extern int verbose;
-
-
-/*
- *  This should be increased by every routine here that actually loads an
- *  executable file into memory.  (For example, loading a symbol file should
- *  NOT increase this.)
- */
-static int n_executables_loaded = 0;
-
-
-#include "thirdparty/exec_elf.h"		/*  Ugly; needed for ELFDATA2LSB etc.  */
-
-#define	unencode(var,dataptr,typ)	{				\
-		int Wi;  unsigned char Wb;				\
-		unsigned char *Wp = (unsigned char *) dataptr;		\
-		int Wlen = sizeof(typ);					\
-		var = 0;						\
-		for (Wi=0; Wi<Wlen; Wi++) {				\
-			if (encoding == ELFDATA2LSB)			\
-				Wb = Wp[Wlen-1 - Wi];			\
-			else						\
-				Wb = Wp[Wi];				\
-			if (Wi == 0 && (Wb & 0x80)) {			\
-				var --;	/*  set var to -1 :-)  */	\
-				var <<= 8;				\
-			}						\
-			var |= Wb;					\
-			if (Wi < Wlen-1)				\
-				var <<= 8;				\
-		}							\
-	}
-
-
-#include "file_android.cc"
-#include "file_aout.cc"
-#include "file_ecoff.cc"
-#include "file_elf.cc"
-#include "file_macho.cc"
-#include "file_raw.cc"
-#include "file_srec.cc"
-
-
-/*
- *  file_n_executables_loaded():
- *
- *  Returns the number of executable files loaded into emulated memory.
- */
-int file_n_executables_loaded(void)
-{
-	return n_executables_loaded;
-}
-
-
-/*
- *  file_load():
- *
- *  Sense the file format of a file (ELF, a.out, ecoff), and call the
- *  right file_load_XXX() function.  If the file isn't of a recognized
- *  binary format, assume that it contains symbol definitions.
- *
- *  If the filename doesn't exist, try to treat the name as
- *   "address:filename" and load the file as a raw binary.
- */
-void file_load(struct machine *machine, struct memory *mem,
-	char *filename, uint64_t *entrypointp,
-	int arch, uint64_t *gpp, int *byte_orderp, uint64_t *tocp)
-{
-	int iadd = DEBUG_INDENTATION, old_quiet_mode;
-	FILE *f;
-	const char *tmpdir = getenv("TMPDIR") == NULL?
-	    DEFAULT_TMP_DIR : getenv("TMPDIR");
-	unsigned char buf[12];
-	unsigned char buf2[2];
-	char tmpname[400];
-	size_t len, len2, i;
-	off_t size;
-
-	if (byte_orderp == NULL) {
-		fprintf(stderr, "file_load(): byte_order == NULL\n");
-		exit(1);
-	}
-
-	if (arch == ARCH_NOARCH) {
-		fprintf(stderr, "file_load(): FATAL ERROR: no arch?\n");
-		exit(1);
-	}
-
-	if (mem == NULL || filename == NULL) {
-		fprintf(stderr, "file_load(): mem or filename is NULL\n");
-		exit(1);
-	}
-
-	/*  Skip configuration files:  */
-	if (filename[0] == '@')
-		return;
-
-	debug("loading %s%s\n", filename, verbose >= 2? ":" : "");
-	debug_indentation(iadd);
-
-	old_quiet_mode = quiet_mode;
-	if (verbose < 2)
-		quiet_mode = 1;
-
-	f = fopen(filename, "r");
-	if (f == NULL) {
-		file_load_raw(machine, mem, filename, entrypointp);
-		goto ret;
-	}
-
-	fseek(f, 0, SEEK_END);
-	size = ftello(f);
-	fseek(f, 0, SEEK_SET);
-
-	memset(buf, 0, sizeof(buf));
-	len = fread(buf, 1, sizeof(buf), f);
-	fseek(f, 510, SEEK_SET);
-	len2 = fread(buf2, 1, sizeof(buf2), f);
-	fclose(f);
-
-	if (len < (signed int)sizeof(buf)) {
-		fprintf(stderr, "\nThis file is too small to contain "
-		    "anything useful\n");
-		exit(1);
-	}
-
-	/*  Is it an ELF?  */
-	if (buf[0] == 0x7f && buf[1]=='E' && buf[2]=='L' && buf[3]=='F') {
-		file_load_elf(machine, mem, filename,
-		    entrypointp, arch, gpp, byte_orderp, tocp);
-		goto ret;
-	}
-
-	/*  Is it an Android boot.img?  */
-	if (memcmp("ANDROID!", &buf[0], 8) == 0) {
-		file_load_android(machine, mem, filename, 0,
-		    entrypointp, arch, byte_orderp);
-		goto ret;
-	}
-
-	/*  Is it an a.out?  */
-	if (buf[0]==0x00 && buf[1]==0x8b && buf[2]==0x01 && buf[3]==0x07) {
-		/*  MIPS a.out  */
-		file_load_aout(machine, mem, filename, 0,
-		    entrypointp, arch, byte_orderp);
-		goto ret;
-	}
-	if (buf[0]==0x00 && buf[1]==0x87 && buf[2]==0x01 && buf[3]==0x08) {
-		/*  M68K a.out  */
-		file_load_aout(machine, mem, filename,
-		    AOUT_FLAG_VADDR_ZERO_HACK  /*  for OpenBSD/mac68k  */,
-		    entrypointp, arch, byte_orderp);
-		goto ret;
-	}
-	if (buf[0]==0x00 && buf[1]==0x99 && buf[2]==0x01 && buf[3]==0x0b) {
-		/*  OpenBSD/M88K a.out  */
-		file_load_aout(machine, mem, filename, AOUT_FLAG_FROM_BEGINNING,
-		    entrypointp, arch, byte_orderp);
-		goto ret;
-	}
-	if (buf[0]==0x00 && buf[1]==0x8f && buf[2]==0x01 && buf[3]==0x0b) {
-		/*  ARM a.out  */
-		file_load_aout(machine, mem, filename, AOUT_FLAG_FROM_BEGINNING,
-		    entrypointp, arch, byte_orderp);
-		goto ret;
-	}
-	if (buf[0]==0x00 && buf[1]==0x86 && buf[2]==0x01 && buf[3]==0x0b) {
-		/*  i386 a.out (old OpenBSD and NetBSD etc)  */
-		file_load_aout(machine, mem, filename, AOUT_FLAG_FROM_BEGINNING,
-		    entrypointp, arch, byte_orderp);
-		goto ret;
-	}
-	if (buf[0]==0x01 && buf[1]==0x03 && buf[2]==0x01 && buf[3]==0x07) {
-		/*  SPARC a.out (old 32-bit NetBSD etc)  */
-		file_load_aout(machine, mem, filename, AOUT_FLAG_NO_SIZES,
-		    entrypointp, arch, byte_orderp);
-		goto ret;
-	}
-	if (buf[0]==0x00 && buf[2]==0x00 && buf[8]==0x7a && buf[9]==0x75) {
-		/*  DEC OSF1 on MIPS:  */
-		file_load_aout(machine, mem, filename, AOUT_FLAG_DECOSF1,
-		    entrypointp, arch, byte_orderp);
-		goto ret;
-	}
-
-	/*
-	 *  Is it a Mach-O file?
-	 */
-	if (buf[0] == 0xfe && buf[1] == 0xed && buf[2] == 0xfa &&
-	    (buf[3] == 0xce || buf[3] == 0xcf)) {
-		file_load_macho(machine, mem, filename, entrypointp,
-		    arch, byte_orderp, buf[3] == 0xcf, 0);
-		goto ret;
-	}
-	if ((buf[0] == 0xce || buf[0] == 0xcf) && buf[1] == 0xfa &&
-	    buf[2] == 0xed && buf[3] == 0xfe) {
-		file_load_macho(machine, mem, filename, entrypointp,
-		    arch, byte_orderp, buf[0] == 0xcf, 1);
-		goto ret;
-	}
-
-	/*
-	 *  Is it an ecoff?
-	 *
-	 *  TODO: What's the deal with the magic value's byte order? Sometimes
-	 *  it seems to be reversed for BE when compared to LE, but not always?
-	 */
-	if (buf[0]+256*buf[1] == ECOFF_MAGIC_MIPSEB ||
-	    buf[0]+256*buf[1] == ECOFF_MAGIC_MIPSEL ||
-	    buf[0]+256*buf[1] == ECOFF_MAGIC_MIPSEB2 ||
-	    buf[0]+256*buf[1] == ECOFF_MAGIC_MIPSEL2 ||
-	    buf[0]+256*buf[1] == ECOFF_MAGIC_MIPSEB3 ||
-	    buf[0]+256*buf[1] == ECOFF_MAGIC_MIPSEL3 ||
-	    buf[1]+256*buf[0] == ECOFF_MAGIC_MIPSEB ||
-	    buf[1]+256*buf[0] == ECOFF_MAGIC_MIPSEL ||
-	    buf[1]+256*buf[0] == ECOFF_MAGIC_MIPSEB2 ||
-	    buf[1]+256*buf[0] == ECOFF_MAGIC_MIPSEL2 ||
-	    buf[1]+256*buf[0] == ECOFF_MAGIC_MIPSEB3 ||
-	    buf[1]+256*buf[0] == ECOFF_MAGIC_MIPSEL3) {
-		file_load_ecoff(machine, mem, filename, entrypointp,
-		    arch, gpp, byte_orderp);
-		goto ret;
-	}
-
-	/*  Is it a Motorola SREC file?  */
-	if ((buf[0]=='S' && buf[1]>='0' && buf[1]<='9')) {
-		file_load_srec(machine, mem, filename, entrypointp);
-		goto ret;
-	}
-
-	/*  gzipped files are not supported:  */
-	if (buf[0]==0x1f && buf[1]==0x8b) {
-		fprintf(stderr, "\nYou need to gunzip the file before you"
-		    " try to use it.\n");
-		exit(1);
-	}
-
-	if (size > 24000000) {
-		fprintf(stderr, "\nThis file is very large (%lli bytes)\n",
-		    (long long)size);
-		fprintf(stderr, "Are you sure it is a kernel and not a disk "
-		    "image? (Use the -d option.)\n");
-		exit(1);
-	}
-
-	if (size == 1474560)
-		fprintf(stderr, "Hm... this file is the size of a 1.44 MB "
-		    "floppy image. Maybe you forgot the\n-d switch?\n");
-
-	/*
-	 *  Ugly hack for Dreamcast:  When booting from a Dreamcast CDROM
-	 *  image, a temporary file is extracted into /tmp/gxemul.*, but this
-	 *  is a "scrambled" raw binary. This code unscrambles it, and loads
-	 *  it as a raw binary.
-	 */
-	snprintf(tmpname, sizeof(tmpname), "%s/gxemul.", tmpdir);
-	if (machine->machine_type == MACHINE_DREAMCAST &&
-	    strncmp(filename, tmpname, strlen(tmpname)) == 0) {
-		char *tmp_filename = (char *) malloc(strlen(filename) + 100);
-		snprintf(tmp_filename, strlen(filename) + 100,
-		    "%s.descrambled", filename);
-		debug("descrambling into %s\n", tmp_filename);
-		dreamcast_descramble(filename, tmp_filename);
-
-		snprintf(tmp_filename, strlen(filename) + 100,
-		    "0x8c010000:%s.descrambled", filename);
-		debug("loading descrambled Dreamcast binary\n");
-		file_load_raw(machine, mem, tmp_filename, entrypointp);
-
-		snprintf(tmp_filename, strlen(filename) + 100,
-		    "%s.descrambled", filename);
-		remove(tmp_filename);
-		free(tmp_filename);
-
-		/*  Hack: Start a "boot from CDROM" sequence:  */
-		*entrypointp = 0x8c000140;
-		goto ret;
-	}
-
-	/*
-	 *  Last resort:  symbol definitions from nm (or nm -S):
-	 *
-	 *  If the buf contains typical 'binary' characters, then print
-	 *  an error message and quit instead of assuming that it is a
-	 *  symbol file.
-	 */
-	for (i=0; i<(signed)sizeof(buf); i++)
-		if (buf[i] < 32 && buf[i] != '\t' &&
-		    buf[i] != '\n' && buf[i] != '\r' &&
-		    buf[i] != '\f') {
-			fprintf(stderr, "\nThe file format of '%s' is "
-			    "unknown.\n\n ", filename);
-			for (i=0; i<(signed)sizeof(buf); i++)
-				fprintf(stderr, " %02x", buf[i]);
-
-			if (len2 == 2 && buf2[0] == 0x55 && buf2[1] == 0xaa)
-				fprintf(stderr, "\n\nIt has a PC-style "
-				    "bootsector marker.");
-
-			fprintf(stderr, "\n\nPossible explanations:\n\n"
-			    "  o)  If this is a disk image, you forgot '-d' "
-			    "on the command line.\n"
-			    "  o)  You are attempting to load a raw binary "
-			    "into emulated memory,\n"
-			    "      but forgot to add the address prefix.\n"
-			    "  o)  This is an unsupported binary format.\n\n");
-			exit(1);
-		}
-
-	symbol_readfile(&machine->symbol_context, filename);
-
-ret:
-	debug_indentation(-iadd);
-	quiet_mode = old_quiet_mode;
-}
-
diff -Nru gxemul-0.6.2/src/file/file_ecoff.c gxemul-0.7.0+dfsg/src/file/file_ecoff.c
--- gxemul-0.6.2/src/file/file_ecoff.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_ecoff.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,624 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: ECOFF file support
+ */
+
+/*  Note: Included from file.c.  */
+
+
+#include "thirdparty/exec_ecoff.h"
+#include <netinet/in.h>
+
+
+/*  Special symbol format used by Microsoft-ish COFF files:  */
+struct ms_sym {
+	unsigned char	name[8];
+	unsigned char	value[4];
+	unsigned char	section[2];
+	unsigned char	type[2];   
+	unsigned char	storage_class;
+	unsigned char	n_aux_syms;   
+};
+
+/*  Relocation format (wild guess) for ECOFFs such as SGI's sash:  */
+struct mips_ecoff_reloc {
+	uint32_t	vaddr;
+	uint32_t	symbolIndexAndType;
+};
+
+/*
+ *  file_load_ecoff():
+ *
+ *  Loads an ecoff binary image into the emulated memory.  The entry point
+ *  (read from the ecoff header) is stored in the specified CPU's registers.
+ */
+static void file_load_ecoff(struct machine *m, struct memory *mem,
+	char *filename, uint64_t *entrypointp,
+	int arch, uint64_t *gpp, int *byte_orderp)
+{
+	struct ecoff_exechdr exechdr;
+	int f_magic, f_nscns, f_nsyms;
+	int a_magic;
+	off_t f_symptr, a_tsize, a_dsize, a_bsize;
+	uint64_t a_entry, a_tstart, a_dstart, a_bstart, a_gp, end_addr=0;
+	const char *format_name;
+	struct ecoff_scnhdr scnhdr;
+	FILE *f;
+	int len, secn;
+	unsigned int total_len, chunk_size;
+	int encoding = ELFDATA2LSB;	/*  Assume little-endian. See below  */
+	int program_byte_order = -1;
+	unsigned char buf[8192];
+	struct ecoff_extsym *extsyms = NULL;
+	int nsymbols = 0;
+	int relocated = 0;
+	uint32_t relocationOffset = 0; // TODO: separate for text and data?
+
+	f = fopen(filename, "r");
+	if (f == NULL) {
+		perror(filename);
+		exit(1);
+	}
+
+	len = fread(&exechdr, 1, sizeof(exechdr), f);
+	if (len != sizeof(exechdr)) {
+		fprintf(stderr, " not a complete ecoff image\n");
+		exit(1);
+	}
+
+	/*
+	 *  The following code looks a bit ugly, but it should work. The ECOFF
+	 *  16-bit magic value seems to be stored in MSB byte order for
+	 *  big-endian binaries, and LSB byte order for little-endian binaries.
+	 *
+	 *  The unencode() assumes little-endianness by default.
+	 */
+	unencode(f_magic, &exechdr.f.f_magic, uint16_t);
+	switch (f_magic) {
+	case ((ECOFF_MAGIC_MIPSEB & 0xff) << 8) +
+	    ((ECOFF_MAGIC_MIPSEB >> 8) & 0xff):
+		format_name = "MIPS1 BE";
+		encoding = ELFDATA2MSB;
+		break;
+	case ECOFF_MAGIC_MIPSEB:
+		/*  NOTE: Big-endian header, little-endian code!  */
+		format_name = "MIPS1 BE-LE";
+		encoding = ELFDATA2MSB;
+		program_byte_order = ELFDATA2LSB;
+		break;
+	case ECOFF_MAGIC_MIPSEL:
+		format_name = "MIPS1 LE";
+		encoding = ELFDATA2LSB;
+		break;
+	case ((ECOFF_MAGIC_MIPSEB2 & 0xff) << 8) +
+	    ((ECOFF_MAGIC_MIPSEB2 >> 8) & 0xff):
+		format_name = "MIPS2 BE";
+		encoding = ELFDATA2MSB;
+		break;
+	case ECOFF_MAGIC_MIPSEL2:
+		format_name = "MIPS2 LE";
+		encoding = ELFDATA2LSB;
+		break;
+	case ((ECOFF_MAGIC_MIPSEB3 & 0xff) << 8) +
+	    ((ECOFF_MAGIC_MIPSEB3 >> 8) & 0xff):
+		format_name = "MIPS3 BE";
+		encoding = ELFDATA2MSB;
+		break;
+	case ECOFF_MAGIC_MIPSEL3:
+		format_name = "MIPS3 LE";
+		encoding = ELFDATA2LSB;
+		break;
+	default:
+		fprintf(stderr, "%s: unimplemented ECOFF format, magic = "
+		    "0x%04x\n", filename, (int)f_magic);
+		exit(1);
+	}
+
+	/*  Read various header information:  */
+	unencode(f_nscns,  &exechdr.f.f_nscns,  uint16_t);
+	unencode(f_symptr, &exechdr.f.f_symptr, uint32_t);
+	unencode(f_nsyms,  &exechdr.f.f_nsyms,  uint32_t);
+	debug("ECOFF, %s, %i sections, %i symbols @ 0x%lx\n",
+	    format_name, f_nscns, f_nsyms, (long)f_symptr);
+
+	unencode(a_magic, &exechdr.a.magic, uint16_t);
+	unencode(a_tsize, &exechdr.a.tsize, uint32_t);
+	unencode(a_dsize, &exechdr.a.dsize, uint32_t);
+	unencode(a_bsize, &exechdr.a.bsize, uint32_t);
+	debug("magic 0x%04x, tsize 0x%x, dsize 0x%x, bsize 0x%x\n",
+	    a_magic, (int)a_tsize, (int)a_dsize, (int)a_bsize);
+
+	unencode(a_tstart, &exechdr.a.text_start, uint32_t);
+	unencode(a_dstart, &exechdr.a.data_start, uint32_t);
+	unencode(a_bstart, &exechdr.a.bss_start,  uint32_t);
+	debug("text @ 0x%08x, data @ 0x%08x, bss @ 0x%08x\n",
+	    (int)a_tstart, (int)a_dstart, (int)a_bstart);
+
+	unencode(a_entry, &exechdr.a.entry,    uint32_t);
+	unencode(a_gp,    &exechdr.a.gp_value, uint32_t);
+	debug("entrypoint 0x%08x, gp = 0x%08x\n",
+	    (int)a_entry, (int)a_gp);
+
+	/*
+	 *  Special hack for a MACH/pmax kernel, I don't know how applicable
+	 *  this is for other files:
+	 *  there are no sections (!), and a_magic = 0x0108 instead of
+	 *  0x0107 as it is on most other (E)COFF files I've seen.
+	 *
+	 *  Then load everything after the header to the text start address.
+	 */
+	if (f_nscns == 0 && a_magic == 0x108) {
+		uint64_t where = a_tstart;
+		total_len = 0;
+		fseek(f, 0x50, SEEK_SET);
+		while (!feof(f)) {
+			chunk_size = 256;
+			len = fread(buf, 1, chunk_size, f);
+
+			if (len > 0)
+				m->cpus[0]->memory_rw(m->cpus[0], mem, where,
+				    &buf[0], len, MEM_WRITE, NO_EXCEPTIONS);
+			where += len;
+			total_len += len;
+		}
+		debug("MACH/pmax hack (!), read 0x%x bytes\n", total_len);
+	}
+
+	off_t sectionHeadersPos = ftello(f);
+
+	/*  First, dump the section headers, see if Relocation is needed:  */
+	for (secn=0; secn<f_nscns; secn++) {
+		off_t s_scnptr, s_relptr, s_lnnoptr;
+		unsigned int s_nreloc, s_nlnno, s_flags, s_size;
+		uint64_t s_paddr, s_vaddr;
+
+		/*  Read a section header:  */
+		fseek(f, sectionHeadersPos + sizeof(scnhdr) * secn, SEEK_SET);
+		len = fread(&scnhdr, 1, sizeof(scnhdr), f);
+		if (len != sizeof(scnhdr)) {
+			fprintf(stderr, "%s: incomplete section "
+			    "header %i\n", filename, secn);
+			exit(1);
+		}
+
+		debug("section %i: ", secn);
+		for (size_t i=0; i<sizeof(scnhdr.s_name); i++)
+			if (scnhdr.s_name[i] >= 32 && scnhdr.s_name[i] < 127)
+				debug("%c", scnhdr.s_name[i]);
+			else
+				break;
+		debug(" (");
+
+		unencode(s_paddr,   &scnhdr.s_paddr,   uint32_t);
+		unencode(s_vaddr,   &scnhdr.s_vaddr,   uint32_t);
+		unencode(s_size,    &scnhdr.s_size,    uint32_t);
+		unencode(s_scnptr,  &scnhdr.s_scnptr,  uint32_t);
+		unencode(s_relptr,  &scnhdr.s_relptr,  uint32_t);
+		unencode(s_lnnoptr, &scnhdr.s_lnnoptr, uint32_t);
+		unencode(s_nreloc,  &scnhdr.s_nreloc,  uint16_t);
+		unencode(s_nlnno,   &scnhdr.s_nlnno,   uint16_t);
+		unencode(s_flags,   &scnhdr.s_flags,   uint32_t);
+
+		debug("0x%x bytes @ vaddr 0x%08x, file offset 0x%lx, %i relocations @ 0x%lx, flags 0x%x)\n",
+		    (int)s_size, (int)s_vaddr, (long)s_scnptr,
+		    (int)s_nreloc, (long)s_relptr, (int)s_flags);
+
+		if (s_relptr != 0 && s_nreloc == 0) {
+			fprintf(stderr, "%s: relocation info, but 0 relocations, for section  %i\n", filename, secn);
+			exit(1);
+		}
+
+		if (s_relptr == 0 && s_nreloc != 0) {
+			fprintf(stderr, "%s: no relocation info, but >0 relocations, for section  %i\n", filename, secn);
+			exit(1);
+		}
+
+		if (s_relptr != 0 && !relocated) {
+			// TODO: better relocation target. Currently hardcoded to
+			// 1 MB below top of RAM.
+			uint32_t relocationTarget = mem->physical_max < 512 * 1048576
+				? mem->physical_max : 512 * 1048576;
+			relocationTarget -= 1048576;
+			relocationTarget += 0x80000000;	// MIPS kseg0
+			relocationOffset = relocationTarget - a_tstart;
+
+			if (s_vaddr != s_paddr) {
+				fprintf(stderr, "%s: relocated ECOFF, but vaddr (0x%08x) != paddr (0x%08x): TODO, for section  %i\n", filename, (int)s_vaddr, (int)s_paddr, secn);
+				exit(1);
+			}
+			
+			if (!relocated) {
+				debug("relocating from base 0x%08x to 0x%08x\n",
+					a_tstart, relocationTarget);
+				a_tstart += relocationOffset;
+				a_dstart += relocationOffset;
+				a_bstart += relocationOffset;
+				a_entry += relocationOffset;
+				a_gp += relocationOffset;
+
+				relocated = 1;
+			}
+		}
+	}
+
+	// Load symbols, if there are any.
+	if (f_symptr != 0 && f_nsyms != 0) {
+		struct ecoff_symhdr symhdr;
+		int sym_magic, iextMax, issExtMax, issMax, crfd;
+		off_t cbRfdOffset, cbExtOffset, cbSsExtOffset, cbSsOffset;
+		char *symbol_data;
+		int sym_nr;
+
+		fseek(f, f_symptr, SEEK_SET);
+
+		len = fread(&symhdr, 1, sizeof(symhdr), f);
+		if (len != sizeof(symhdr)) {
+			fprintf(stderr, "%s: not a complete "
+			    "ecoff image: symhdr broken\n", filename);
+			exit(1);
+		}
+
+		unencode(sym_magic,     &symhdr.magic,         uint16_t);
+		unencode(crfd,          &symhdr.crfd,          uint32_t);
+		unencode(cbRfdOffset,   &symhdr.cbRfdOffset,   uint32_t);
+		unencode(issMax,        &symhdr.issMax,        uint32_t);
+		unencode(cbSsOffset,    &symhdr.cbSsOffset,    uint32_t);
+		unencode(issExtMax,     &symhdr.issExtMax,     uint32_t);
+		unencode(cbSsExtOffset, &symhdr.cbSsExtOffset, uint32_t);
+		unencode(iextMax,       &symhdr.iextMax,       uint32_t);
+		unencode(cbExtOffset,   &symhdr.cbExtOffset,   uint32_t);
+
+		if (sym_magic != MIPS_MAGIC_SYM) {
+			unsigned char *ms_sym_buf;
+			struct ms_sym *sym;
+			int n_real_symbols = 0;
+
+			debug("bad symbol magic, assuming Microsoft format: ");
+
+			/*
+			 *  See http://www.lisoleg.net/lisoleg/elfandlib/
+			 *    Microsoft%20Portable%20Executable%20COFF%20For
+			 *    mat%20Specification.txt
+			 *  for more details.
+			 */
+			CHECK_ALLOCATION(ms_sym_buf = (unsigned char *)
+			    malloc(sizeof(struct ms_sym) * f_nsyms));
+			fseek(f, f_symptr, SEEK_SET);
+			len = fread(ms_sym_buf, 1,
+			    sizeof(struct ms_sym) * f_nsyms, f);
+			sym = (struct ms_sym *) ms_sym_buf;
+			for (sym_nr=0; sym_nr<f_nsyms; sym_nr++) {
+				char name[300];
+				uint32_t v, t, altname;
+				/*  debug("sym %5i: '", sym_nr);
+				for (i=0; i<8 && sym->name[i]; i++)
+					debug("%c", sym->name[i]);  */
+				v = sym->value[0] + (sym->value[1] << 8)
+				    + (sym->value[2] << 16)
+				    + ((uint64_t)sym->value[3] << 24);
+				altname = sym->name[4] + (sym->name[5] << 8)
+				    + (sym->name[6] << 16)
+				    + ((uint64_t)sym->name[3] << 24);
+				t = (sym->type[1] << 8) + sym->type[0];
+				/*  TODO: big endian COFF?  */
+				/*  debug("' value=0x%x type=0x%04x", v, t);  */
+
+				if (t == 0x20 && sym->name[0]) {
+					memcpy(name, sym->name, 8);
+					name[8] = '\0';
+					add_symbol_name(&m->symbol_context,
+					    v, 0, name, 0, -1);
+					n_real_symbols ++;
+				} else if (t == 0x20 && !sym->name[0]) {
+					off_t ofs;
+					ofs = f_symptr + altname +
+					    sizeof(struct ms_sym) * f_nsyms;
+					fseek(f, ofs, SEEK_SET);
+					if (fread(name, 1, sizeof(name), f) != sizeof(name)) {
+						fprintf(stderr, "error reading symbol from %s\n", filename);
+						exit(1);
+					}
+					name[sizeof(name)-1] = '\0';
+					/*  debug(" [altname=0x%x '%s']",
+					    altname, name);  */
+					add_symbol_name(&m->symbol_context,
+					    v, 0, name, 0, -1);
+					n_real_symbols ++;
+				}
+
+
+				if (sym->n_aux_syms) {
+					int n = sym->n_aux_syms;
+					/*  debug(" aux='");  */
+					while (n-- > 0) {
+						sym ++; sym_nr ++;
+						/*  for (i=0; i<8 &&
+						    sym->name[i]; i++)
+							debug("%c",
+							    sym->name[i]);  */
+					}
+					/*  debug("'");  */
+				}
+				/*  debug("\n");  */
+				sym ++;
+			}
+
+			debug("%i symbols\n", n_real_symbols);
+			free(ms_sym_buf);
+
+			goto skip_normal_coff_symbols;
+		}
+
+		debug("symbol header: magic = 0x%x\n", sym_magic);
+
+		debug("%i symbols @ 0x%08x (strings @ 0x%08x)\n",
+		    iextMax, cbExtOffset, cbSsExtOffset);
+
+		CHECK_ALLOCATION(symbol_data = (char *) malloc(issExtMax + 2));
+		memset(symbol_data, 0, issExtMax + 2);
+		fseek(f, cbSsExtOffset, SEEK_SET);
+		if (fread(symbol_data, 1, issExtMax + 1, f) != (size_t) issExtMax+1) {
+			fprintf(stderr, "error reading symbol data from %s\n", filename);
+			exit(1);
+		}
+
+		nsymbols = iextMax;
+
+		CHECK_ALLOCATION(extsyms = (struct ecoff_extsym *)
+		    malloc(iextMax * sizeof(struct ecoff_extsym)));
+		memset(extsyms, 0, iextMax * sizeof(struct ecoff_extsym));
+		fseek(f, cbExtOffset, SEEK_SET);
+		if (fread(extsyms, 1, iextMax * sizeof(struct ecoff_extsym), f) !=
+		    iextMax * sizeof(struct ecoff_extsym)) {
+			fprintf(stderr, "error reading extsyms from %s\n", filename);
+			exit(1);
+		}
+
+		/*  Unencode the strindex and value first:  */
+		for (sym_nr=0; sym_nr<nsymbols; sym_nr++) {
+			uint64_t value, strindex;
+
+			unencode(strindex, &extsyms[sym_nr].es_strindex,
+			    uint32_t);
+			unencode(value, &extsyms[sym_nr].es_value, uint32_t);
+
+			extsyms[sym_nr].es_strindex = strindex;
+			extsyms[sym_nr].es_value    = value + relocationOffset;
+		}
+
+		for (sym_nr=0; sym_nr<nsymbols; sym_nr++) {
+			/*  debug("symbol%6i: 0x%08x = %s\n",
+			    sym_nr, (int)extsyms[sym_nr].es_value,
+			    symbol_data + extsyms[sym_nr].es_strindex);  */
+
+			add_symbol_name(&m->symbol_context,
+			    extsyms[sym_nr].es_value, 0,
+			    symbol_data + extsyms[sym_nr].es_strindex, 0, -1);
+		}
+
+		free(symbol_data);
+
+skip_normal_coff_symbols:
+		;
+	}
+
+	/*  Then, load the sections that are loadable:  */
+	for (secn=0; secn<f_nscns; secn++) {
+		off_t s_scnptr, s_relptr, s_lnnoptr;
+		unsigned int s_nreloc, s_nlnno, s_flags, s_size;
+		uint64_t s_paddr, s_vaddr;
+
+		/*  Read a section header:  */
+		fseek(f, sectionHeadersPos + sizeof(scnhdr) * secn, SEEK_SET);
+		len = fread(&scnhdr, 1, sizeof(scnhdr), f);
+		if (len != sizeof(scnhdr)) {
+			fprintf(stderr, "%s: incomplete section "
+			    "header %i\n", filename, secn);
+			exit(1);
+		}
+
+		unencode(s_paddr,   &scnhdr.s_paddr,   uint32_t);
+		unencode(s_vaddr,   &scnhdr.s_vaddr,   uint32_t);
+		unencode(s_size,    &scnhdr.s_size,    uint32_t);
+		unencode(s_scnptr,  &scnhdr.s_scnptr,  uint32_t);
+		unencode(s_relptr,  &scnhdr.s_relptr,  uint32_t);
+		unencode(s_lnnoptr, &scnhdr.s_lnnoptr, uint32_t);
+		unencode(s_nreloc,  &scnhdr.s_nreloc,  uint16_t);
+		unencode(s_nlnno,   &scnhdr.s_nlnno,   uint16_t);
+		unencode(s_flags,   &scnhdr.s_flags,   uint32_t);
+
+		s_vaddr += relocationOffset;
+		end_addr = s_vaddr + s_size;
+
+		/*  Loadable? Then load the section:  */
+		if (s_scnptr != 0 && s_size != 0 &&
+		    s_vaddr != 0 && !(s_flags & 0x02)) {
+			/*  Load the section into emulated memory:  */
+			fseek(f, s_scnptr, SEEK_SET);
+			total_len = 0;
+			chunk_size = 1;
+			if ((s_vaddr & 0xf) == 0)	chunk_size = 0x10;
+			if ((s_vaddr & 0xff) == 0)	chunk_size = 0x100;
+			if ((s_vaddr & 0xfff) == 0)	chunk_size = 0x1000;
+			while (total_len < s_size) {
+				len = chunk_size;
+				if (total_len + len > s_size)
+					len = s_size - total_len;
+				len = fread(buf, 1, chunk_size, f);
+				if (len == 0) {
+					debug("!!! total_len = %i, "
+					    "chunk_size = %i, len = %i\n",
+					    total_len, chunk_size, len);
+					break;
+				}
+
+				m->cpus[0]->memory_rw(m->cpus[0], mem, s_vaddr,
+				    &buf[0], len, MEM_WRITE, NO_EXCEPTIONS);
+				s_vaddr += len;
+				total_len += len;
+			}
+
+			if (relocated && s_relptr != 0) {
+				// Relocate.
+				fseek(f, s_relptr, SEEK_SET);
+				struct mips_ecoff_reloc* relocs;
+				CHECK_ALLOCATION(relocs = (struct mips_ecoff_reloc*)
+				    	malloc(s_nreloc * sizeof(struct mips_ecoff_reloc)));
+				len = fread(relocs, 1, s_nreloc * sizeof(struct mips_ecoff_reloc), f);
+				if ((size_t)len != s_nreloc * sizeof(struct mips_ecoff_reloc)) {
+					fprintf(stderr, "%s: could not read relocation entries for section  %i\n", filename, secn);
+					exit(1);
+				}
+				
+				for (size_t ri = 0; ri < s_nreloc; ++ri) {
+					uint32_t vaddr = ntohl(relocs[ri].vaddr);
+					uint32_t symbolIndexAndType = ntohl(relocs[ri].symbolIndexAndType);
+
+					vaddr += relocationOffset;
+
+					int isExternal = symbolIndexAndType & 1;
+					int relType = (symbolIndexAndType >> 1) & 15;
+					int symbolIndex = symbolIndexAndType >> 8;
+
+					if (symbolIndex < 0 || symbolIndex >= nsymbols) {
+						fprintf(stderr, "%s: relocation for out-of-range symbol %i\n", filename, symbolIndex);
+						exit(1);
+					}
+
+					/*
+					 *  This is a wild guess. If isExternal is false,
+					 *  then perhaps different relocations should be
+					 *  used for text, data, rdata, etc. (TODO.)
+					 */
+					uint32_t r;
+					if (isExternal)
+						r = extsyms[symbolIndex].es_value;
+					else
+						r = relocationOffset;
+
+					// printf("symbolIndex = %i: %08x\n", symbolIndex, r);
+
+					uint16_t relHi = r >> 16;
+					uint16_t relLo = r & 0xffff;
+
+					/*
+					 *  Relocation types for MIPS ECOFF:
+					 *
+					 *  REFHALF	1
+					 *  REFWORD	2
+					 *  JMPADDR	3
+					 *  REFHI	4
+					 *  REFLO	5
+					 *  GPREL	6
+					 *  LITERAL	7
+					 *
+					 *
+					 *  SGI's sash uses relocations like these:
+					 *
+					 *  10 00 00 00  00 00 00 07
+					 *  8ff00000: 08000000	j	0x80000000
+					 *
+					 *  10 02 12 b4  00 01 a8 09
+					 *  8ff212b4: 3c1d0000	lui	sp,0x0
+					 *
+					 *  10 02 12 b8  00 01 a8 0b
+					 *  8ff212b8: 27bd0000	addiu	sp,sp,0
+					 */
+					if (relType == 2) {
+						// "REFWORD" relocation.
+						uint32_t data;
+						m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+						    (uint8_t*)&data, sizeof(data), MEM_READ, NO_EXCEPTIONS);
+						data = ntohl(data);
+						// printf("data=%08x ", data);
+						data += r;
+						// printf("=> %08x (symbolIndex %i, r = %08x, relocationOffset= %08x)\n", data, symbolIndex, r, relocationOffset);
+						data = htonl(data);
+						m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+						    (uint8_t*)&data, sizeof(data), MEM_WRITE, NO_EXCEPTIONS);
+					} else if (relType == 3) {
+						// "JMPADDR" relocation.
+						uint32_t data;
+						m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+						    (uint8_t*)&data, sizeof(data), MEM_READ, NO_EXCEPTIONS);
+						data = ntohl(data);
+						data = (data & 0xfc000000) | ((data + (r >> 2)) & 0x03ffffff);
+						data = htonl(data);
+						m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+						    (uint8_t*)&data, sizeof(data), MEM_WRITE, NO_EXCEPTIONS);
+					} else if (relType == 4) {
+						// "REFHI" relocation.
+						uint32_t data;
+						m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+						    (uint8_t*)&data, sizeof(data), MEM_READ, NO_EXCEPTIONS);
+						data = ntohl(data);
+						data = (data & 0xffff0000) | ((data + relHi) & 0xffff);
+						data = htonl(data);
+						m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+						    (uint8_t*)&data, sizeof(data), MEM_WRITE, NO_EXCEPTIONS);
+					} else if (relType == 5) {
+						// "REFLO" relocation.
+						uint32_t data;
+						m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+						    (uint8_t*)&data, sizeof(data), MEM_READ, NO_EXCEPTIONS);
+						data = ntohl(data);
+						data = (data & 0xffff0000) | ((data + relLo) & 0xffff);
+						data = htonl(data);
+						m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+						    (uint8_t*)&data, sizeof(data), MEM_WRITE, NO_EXCEPTIONS);
+					} else {
+						fprintf(stderr, "%s: unimplemented relType %i\n", filename, relType);
+						exit(1);
+					}
+				}
+				
+				free(relocs);
+			}
+		}
+	}
+
+	fclose(f);
+
+	if (extsyms != NULL)
+		free(extsyms);
+
+	*entrypointp = a_entry;
+	*gpp = a_gp;
+	m->file_loaded_end_addr = end_addr;
+
+	if (program_byte_order != -1)
+		encoding = program_byte_order;
+
+	if (encoding == ELFDATA2LSB)
+		*byte_orderp = EMUL_LITTLE_ENDIAN;
+	else
+		*byte_orderp = EMUL_BIG_ENDIAN;
+
+	n_executables_loaded ++;
+}
+
diff -Nru gxemul-0.6.2/src/file/file_ecoff.cc gxemul-0.7.0+dfsg/src/file/file_ecoff.cc
--- gxemul-0.6.2/src/file/file_ecoff.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_ecoff.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,446 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: ECOFF file support
- */
-
-/*  Note: Included from file.c.  */
-
-
-#include "thirdparty/exec_ecoff.h"
-
-
-/*  Special symbol format used by Microsoft-ish COFF files:  */
-struct ms_sym {
-	unsigned char	name[8];
-	unsigned char	value[4];
-	unsigned char	section[2];
-	unsigned char	type[2];   
-	unsigned char	storage_class;
-	unsigned char	n_aux_syms;   
-};
-
-
-/*
- *  file_load_ecoff():
- *
- *  Loads an ecoff binary image into the emulated memory.  The entry point
- *  (read from the ecoff header) is stored in the specified CPU's registers.
- */
-static void file_load_ecoff(struct machine *m, struct memory *mem,
-	char *filename, uint64_t *entrypointp,
-	int arch, uint64_t *gpp, int *byte_orderp)
-{
-	struct ecoff_exechdr exechdr;
-	int f_magic, f_nscns, f_nsyms;
-	int a_magic;
-	off_t f_symptr, a_tsize, a_dsize, a_bsize;
-	uint64_t a_entry, a_tstart, a_dstart, a_bstart, a_gp, end_addr=0;
-	const char *format_name;
-	struct ecoff_scnhdr scnhdr;
-	FILE *f;
-	int len, secn, total_len, chunk_size;
-	int encoding = ELFDATA2LSB;	/*  Assume little-endian. See below  */
-	int program_byte_order = -1;
-	unsigned char buf[8192];
-
-	f = fopen(filename, "r");
-	if (f == NULL) {
-		perror(filename);
-		exit(1);
-	}
-
-	len = fread(&exechdr, 1, sizeof(exechdr), f);
-	if (len != sizeof(exechdr)) {
-		fprintf(stderr, " not a complete ecoff image\n");
-		exit(1);
-	}
-
-	/*
-	 *  The following code looks a bit ugly, but it should work. The ECOFF
-	 *  16-bit magic value seems to be stored in MSB byte order for
-	 *  big-endian binaries, and LSB byte order for little-endian binaries.
-	 *
-	 *  The unencode() assumes little-endianness by default.
-	 */
-	unencode(f_magic, &exechdr.f.f_magic, uint16_t);
-	switch (f_magic) {
-	case ((ECOFF_MAGIC_MIPSEB & 0xff) << 8) +
-	    ((ECOFF_MAGIC_MIPSEB >> 8) & 0xff):
-		format_name = "MIPS1 BE";
-		encoding = ELFDATA2MSB;
-		break;
-	case ECOFF_MAGIC_MIPSEB:
-		/*  NOTE: Big-endian header, little-endian code!  */
-		format_name = "MIPS1 BE-LE";
-		encoding = ELFDATA2MSB;
-		program_byte_order = ELFDATA2LSB;
-		break;
-	case ECOFF_MAGIC_MIPSEL:
-		format_name = "MIPS1 LE";
-		encoding = ELFDATA2LSB;
-		break;
-	case ((ECOFF_MAGIC_MIPSEB2 & 0xff) << 8) +
-	    ((ECOFF_MAGIC_MIPSEB2 >> 8) & 0xff):
-		format_name = "MIPS2 BE";
-		encoding = ELFDATA2MSB;
-		break;
-	case ECOFF_MAGIC_MIPSEL2:
-		format_name = "MIPS2 LE";
-		encoding = ELFDATA2LSB;
-		break;
-	case ((ECOFF_MAGIC_MIPSEB3 & 0xff) << 8) +
-	    ((ECOFF_MAGIC_MIPSEB3 >> 8) & 0xff):
-		format_name = "MIPS3 BE";
-		encoding = ELFDATA2MSB;
-		break;
-	case ECOFF_MAGIC_MIPSEL3:
-		format_name = "MIPS3 LE";
-		encoding = ELFDATA2LSB;
-		break;
-	default:
-		fprintf(stderr, "%s: unimplemented ECOFF format, magic = "
-		    "0x%04x\n", filename, (int)f_magic);
-		exit(1);
-	}
-
-	/*  Read various header information:  */
-	unencode(f_nscns,  &exechdr.f.f_nscns,  uint16_t);
-	unencode(f_symptr, &exechdr.f.f_symptr, uint32_t);
-	unencode(f_nsyms,  &exechdr.f.f_nsyms,  uint32_t);
-	debug("ECOFF, %s, %i sections, %i symbols @ 0x%lx\n",
-	    format_name, f_nscns, f_nsyms, (long)f_symptr);
-
-	unencode(a_magic, &exechdr.a.magic, uint16_t);
-	unencode(a_tsize, &exechdr.a.tsize, uint32_t);
-	unencode(a_dsize, &exechdr.a.dsize, uint32_t);
-	unencode(a_bsize, &exechdr.a.bsize, uint32_t);
-	debug("magic 0x%04x, tsize 0x%x, dsize 0x%x, bsize 0x%x\n",
-	    a_magic, (int)a_tsize, (int)a_dsize, (int)a_bsize);
-
-	unencode(a_tstart, &exechdr.a.text_start, uint32_t);
-	unencode(a_dstart, &exechdr.a.data_start, uint32_t);
-	unencode(a_bstart, &exechdr.a.bss_start,  uint32_t);
-	debug("text @ 0x%08x, data @ 0x%08x, bss @ 0x%08x\n",
-	    (int)a_tstart, (int)a_dstart, (int)a_bstart);
-
-	unencode(a_entry, &exechdr.a.entry,    uint32_t);
-	unencode(a_gp,    &exechdr.a.gp_value, uint32_t);
-	debug("entrypoint 0x%08x, gp = 0x%08x\n",
-	    (int)a_entry, (int)a_gp);
-
-	/*
-	 *  Special hack for a MACH/pmax kernel, I don't know how applicable
-	 *  this is for other files:
-	 *  there are no sections (!), and a_magic = 0x0108 instead of
-	 *  0x0107 as it is on most other (E)COFF files I've seen.
-	 *
-	 *  Then load everything after the header to the text start address.
-	 */
-	if (f_nscns == 0 && a_magic == 0x108) {
-		uint64_t where = a_tstart;
-		total_len = 0;
-		fseek(f, 0x50, SEEK_SET);
-		while (!feof(f)) {
-			chunk_size = 256;
-			len = fread(buf, 1, chunk_size, f);
-
-			if (len > 0)
-				m->cpus[0]->memory_rw(m->cpus[0], mem, where,
-				    &buf[0], len, MEM_WRITE, NO_EXCEPTIONS);
-			where += len;
-			total_len += len;
-		}
-		debug("MACH/pmax hack (!), read 0x%x bytes\n", total_len);
-	}
-
-	/*  Go through all the section headers:  */
-	for (secn=0; secn<f_nscns; secn++) {
-		off_t s_scnptr, s_relptr, s_lnnoptr, oldpos;
-		int s_nreloc, s_nlnno, s_flags;
-		int s_size;
-		unsigned int i;
-		uint64_t s_paddr, s_vaddr;
-
-		/*  Read a section header:  */
-		len = fread(&scnhdr, 1, sizeof(scnhdr), f);
-		if (len != sizeof(scnhdr)) {
-			fprintf(stderr, "%s: incomplete section "
-			    "header %i\n", filename, secn);
-			exit(1);
-		}
-
-		/*  Show the section name:  */
-		debug("section ");
-		for (i=0; i<sizeof(scnhdr.s_name); i++)
-			if (scnhdr.s_name[i] >= 32 && scnhdr.s_name[i] < 127)
-				debug("%c", scnhdr.s_name[i]);
-			else
-				break;
-		debug(" (");
-
-		unencode(s_paddr,   &scnhdr.s_paddr,   uint32_t);
-		unencode(s_vaddr,   &scnhdr.s_vaddr,   uint32_t);
-		unencode(s_size,    &scnhdr.s_size,    uint32_t);
-		unencode(s_scnptr,  &scnhdr.s_scnptr,  uint32_t);
-		unencode(s_relptr,  &scnhdr.s_relptr,  uint32_t);
-		unencode(s_lnnoptr, &scnhdr.s_lnnoptr, uint32_t);
-		unencode(s_nreloc,  &scnhdr.s_nreloc,  uint16_t);
-		unencode(s_nlnno,   &scnhdr.s_nlnno,   uint16_t);
-		unencode(s_flags,   &scnhdr.s_flags,   uint32_t);
-
-		debug("0x%x @ 0x%08x, offset 0x%lx, flags 0x%x)\n",
-		    (int)s_size, (int)s_vaddr, (long)s_scnptr, (int)s_flags);
-
-		end_addr = s_vaddr + s_size;
-
-		if (s_relptr != 0) {
-			/*
-			 *  TODO: Read this url, or similar:
-			 *  http://www.iecc.com/linker/linker07.html
-			 */
-			fprintf(stderr, "%s: relocatable code/data in "
-			    "section nr %i: not yet implemented\n",
-			    filename, secn);
-			exit(1);
-		}
-
-		/*  Loadable? Then load the section:  */
-		if (s_scnptr != 0 && s_size != 0 &&
-		    s_vaddr != 0 && !(s_flags & 0x02)) {
-			/*  Remember the current file offset:  */
-			oldpos = ftello(f);
-
-			/*  Load the section into emulated memory:  */
-			fseek(f, s_scnptr, SEEK_SET);
-			total_len = 0;
-			chunk_size = 1;
-			if ((s_vaddr & 0xf) == 0)	chunk_size = 0x10;
-			if ((s_vaddr & 0xff) == 0)	chunk_size = 0x100;
-			if ((s_vaddr & 0xfff) == 0)	chunk_size = 0x1000;
-			while (total_len < s_size) {
-				len = chunk_size;
-				if (total_len + len > s_size)
-					len = s_size - total_len;
-				len = fread(buf, 1, chunk_size, f);
-				if (len == 0) {
-					debug("!!! total_len = %i, "
-					    "chunk_size = %i, len = %i\n",
-					    total_len, chunk_size, len);
-					break;
-				}
-
-				m->cpus[0]->memory_rw(m->cpus[0], mem, s_vaddr,
-				    &buf[0], len, MEM_WRITE, NO_EXCEPTIONS);
-				s_vaddr += len;
-				total_len += len;
-			}
-
-			/*  Return to position inside the section headers:  */
-			fseek(f, oldpos, SEEK_SET);
-		}
-	}
-
-	if (f_symptr != 0 && f_nsyms != 0) {
-		struct ecoff_symhdr symhdr;
-		int sym_magic, iextMax, issExtMax, issMax, crfd;
-		off_t cbRfdOffset, cbExtOffset, cbSsExtOffset, cbSsOffset;
-		char *symbol_data;
-		struct ecoff_extsym *extsyms;
-		int nsymbols, sym_nr;
-
-		fseek(f, f_symptr, SEEK_SET);
-
-		len = fread(&symhdr, 1, sizeof(symhdr), f);
-		if (len != sizeof(symhdr)) {
-			fprintf(stderr, "%s: not a complete "
-			    "ecoff image: symhdr broken\n", filename);
-			exit(1);
-		}
-
-		unencode(sym_magic,     &symhdr.magic,         uint16_t);
-		unencode(crfd,          &symhdr.crfd,          uint32_t);
-		unencode(cbRfdOffset,   &symhdr.cbRfdOffset,   uint32_t);
-		unencode(issMax,        &symhdr.issMax,        uint32_t);
-		unencode(cbSsOffset,    &symhdr.cbSsOffset,    uint32_t);
-		unencode(issExtMax,     &symhdr.issExtMax,     uint32_t);
-		unencode(cbSsExtOffset, &symhdr.cbSsExtOffset, uint32_t);
-		unencode(iextMax,       &symhdr.iextMax,       uint32_t);
-		unencode(cbExtOffset,   &symhdr.cbExtOffset,   uint32_t);
-
-		if (sym_magic != MIPS_MAGIC_SYM) {
-			unsigned char *ms_sym_buf;
-			struct ms_sym *sym;
-			int n_real_symbols = 0;
-
-			debug("bad symbol magic, assuming Microsoft format: ");
-
-			/*
-			 *  See http://www.lisoleg.net/lisoleg/elfandlib/
-			 *    Microsoft%20Portable%20Executable%20COFF%20For
-			 *    mat%20Specification.txt
-			 *  for more details.
-			 */
-			CHECK_ALLOCATION(ms_sym_buf = (unsigned char *)
-			    malloc(sizeof(struct ms_sym) * f_nsyms));
-			fseek(f, f_symptr, SEEK_SET);
-			len = fread(ms_sym_buf, 1,
-			    sizeof(struct ms_sym) * f_nsyms, f);
-			sym = (struct ms_sym *) ms_sym_buf;
-			for (sym_nr=0; sym_nr<f_nsyms; sym_nr++) {
-				char name[300];
-				uint32_t v, t, altname;
-				/*  debug("sym %5i: '", sym_nr);
-				for (i=0; i<8 && sym->name[i]; i++)
-					debug("%c", sym->name[i]);  */
-				v = sym->value[0] + (sym->value[1] << 8)
-				    + (sym->value[2] << 16)
-				    + ((uint64_t)sym->value[3] << 24);
-				altname = sym->name[4] + (sym->name[5] << 8)
-				    + (sym->name[6] << 16)
-				    + ((uint64_t)sym->name[3] << 24);
-				t = (sym->type[1] << 8) + sym->type[0];
-				/*  TODO: big endian COFF?  */
-				/*  debug("' value=0x%x type=0x%04x", v, t);  */
-
-				if (t == 0x20 && sym->name[0]) {
-					memcpy(name, sym->name, 8);
-					name[8] = '\0';
-					add_symbol_name(&m->symbol_context,
-					    v, 0, name, 0, -1);
-					n_real_symbols ++;
-				} else if (t == 0x20 && !sym->name[0]) {
-					off_t ofs;
-					ofs = f_symptr + altname +
-					    sizeof(struct ms_sym) * f_nsyms;
-					fseek(f, ofs, SEEK_SET);
-					if (fread(name, 1, sizeof(name), f) != sizeof(name)) {
-						fprintf(stderr, "error reading symbol from %s\n", filename);
-						exit(1);
-					}
-					name[sizeof(name)-1] = '\0';
-					/*  debug(" [altname=0x%x '%s']",
-					    altname, name);  */
-					add_symbol_name(&m->symbol_context,
-					    v, 0, name, 0, -1);
-					n_real_symbols ++;
-				}
-
-
-				if (sym->n_aux_syms) {
-					int n = sym->n_aux_syms;
-					/*  debug(" aux='");  */
-					while (n-- > 0) {
-						sym ++; sym_nr ++;
-						/*  for (i=0; i<8 &&
-						    sym->name[i]; i++)
-							debug("%c",
-							    sym->name[i]);  */
-					}
-					/*  debug("'");  */
-				}
-				/*  debug("\n");  */
-				sym ++;
-			}
-
-			debug("%i symbols\n", n_real_symbols);
-			free(ms_sym_buf);
-
-			goto skip_normal_coff_symbols;
-		}
-
-		debug("symbol header: magic = 0x%x\n", sym_magic);
-
-		debug("%i symbols @ 0x%08x (strings @ 0x%08x)\n",
-		    iextMax, cbExtOffset, cbSsExtOffset);
-
-		CHECK_ALLOCATION(symbol_data = (char *) malloc(issExtMax + 2));
-		memset(symbol_data, 0, issExtMax + 2);
-		fseek(f, cbSsExtOffset, SEEK_SET);
-		if (fread(symbol_data, 1, issExtMax + 1, f) != (size_t) issExtMax+1) {
-			fprintf(stderr, "error reading symbol data from %s\n", filename);
-			exit(1);
-		}
-
-		nsymbols = iextMax;
-
-		CHECK_ALLOCATION(extsyms = (struct ecoff_extsym *)
-		    malloc(iextMax * sizeof(struct ecoff_extsym)));
-		memset(extsyms, 0, iextMax * sizeof(struct ecoff_extsym));
-		fseek(f, cbExtOffset, SEEK_SET);
-		if (fread(extsyms, 1, iextMax * sizeof(struct ecoff_extsym), f) !=
-		    iextMax * sizeof(struct ecoff_extsym)) {
-			fprintf(stderr, "error reading extsyms from %s\n", filename);
-			exit(1);
-		}
-
-		/*  Unencode the strindex and value first:  */
-		for (sym_nr=0; sym_nr<nsymbols; sym_nr++) {
-			uint64_t value, strindex;
-
-			unencode(strindex, &extsyms[sym_nr].es_strindex,
-			    uint32_t);
-			unencode(value, &extsyms[sym_nr].es_value, uint32_t);
-
-			extsyms[sym_nr].es_strindex = strindex;
-			extsyms[sym_nr].es_value    = value;
-		}
-
-		for (sym_nr=0; sym_nr<nsymbols; sym_nr++) {
-			/*  debug("symbol%6i: 0x%08x = %s\n",
-			    sym_nr, (int)extsyms[sym_nr].es_value,
-			    symbol_data + extsyms[sym_nr].es_strindex);  */
-
-			add_symbol_name(&m->symbol_context,
-			    extsyms[sym_nr].es_value, 0,
-			    symbol_data + extsyms[sym_nr].es_strindex, 0, -1);
-		}
-
-		free(extsyms);
-		free(symbol_data);
-
-skip_normal_coff_symbols:
-		;
-	}
-
-	fclose(f);
-
-	*entrypointp = a_entry;
-	*gpp = a_gp;
-	m->file_loaded_end_addr = end_addr;
-
-	if (program_byte_order != -1)
-		encoding = program_byte_order;
-
-	if (encoding == ELFDATA2LSB)
-		*byte_orderp = EMUL_LITTLE_ENDIAN;
-	else
-		*byte_orderp = EMUL_BIG_ENDIAN;
-
-	n_executables_loaded ++;
-}
-
diff -Nru gxemul-0.6.2/src/file/file_elf.c gxemul-0.7.0+dfsg/src/file/file_elf.c
--- gxemul-0.6.2/src/file/file_elf.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_elf.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,726 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: ELF file support
+ */
+
+/*  Note: Included from file.c.  */
+
+
+#include "thirdparty/exec_elf.h"
+
+/*  ELF machine types as strings: (same as exec_elf.h)  */
+#define N_ELF_MACHINE_TYPES     89
+static const char *elf_machine_type[N_ELF_MACHINE_TYPES] = {
+        "NONE", "M32", "SPARC", "386",				/*  0..3  */
+        "68K", "88K", "486", "860",				/*  4..7  */  
+        "MIPS", "S370", "MIPS_RS3_LE", "RS6000",		/*  8..11  */
+        "unknown12", "unknown13", "unknown14", "PARISC",	/*  12..15  */
+        "NCUBE", "VPP500", "SPARC32PLUS", "960",		/*  16..19  */
+        "PPC", "PPC64", "unknown22", "unknown23",		/*  20..23  */
+        "unknown24", "unknown25", "unknown26", "unknown27",	/*  24..27  */
+        "unknown28", "unknown29", "unknown30", "unknown31",	/*  28..31  */
+        "unknown32", "unknown33", "unknown34", "unknown35",	/*  32..35  */
+        "V800", "FR20", "RH32", "RCE",				/*  36..39  */
+        "ARM", "ALPHA", "SH", "SPARCV9",			/*  40..43  */
+        "TRICORE", "ARC", "H8_300", "H8_300H",			/*  44..47  */
+        "H8S", "H8_500", "IA_64", "MIPS_X",			/*  48..51  */
+        "COLDFIRE", "68HC12", "unknown54", "unknown55",		/*  52..55  */
+        "unknown56", "unknown57", "unknown58", "unknown59",	/*  56..59  */
+        "unknown60", "unknown61", "AMD64", "unknown63",		/*  60..63  */
+        "unknown64", "unknown65", "unknown66", "unknown67",	/*  64..67  */
+        "unknown68", "unknown69", "unknown70", "unknown71",	/*  68..71  */
+        "unknown72", "unknown73", "unknown74", "unknown75",	/*  72..75  */
+        "unknown76", "unknown77", "unknown78", "unknown79",	/*  76..79  */
+        "unknown80", "unknown81", "unknown82", "AVR",		/*  80..83  */
+        "unknown84", "unknown85", "unknown86", "unknown87",	/*  84..87  */
+        "M32R"							/*  88      */
+};
+
+
+/*
+ *  file_load_elf():
+ *
+ *  Loads an ELF image into the emulated memory.  The entry point (read from
+ *  the ELF header) and the initial value of the gp register (read from the
+ *  ELF symbol table) are stored in the specified CPU's registers.
+ *
+ *  This is pretty heavy stuff, but is needed because of the heaviness of
+ *  ELF files. :-/   Hopefully it will be able to recognize most valid ELFs.
+ */
+static void file_load_elf(struct machine *m, struct memory *mem,
+	char *filename, uint64_t *entrypointp, int arch, uint64_t *gpp,
+	int *byte_order, uint64_t *tocp)
+{
+	Elf32_Ehdr hdr32;
+	Elf64_Ehdr hdr64;
+	FILE *f;
+	uint64_t eentry;
+	int len, i, ok;
+	int elf64, encoding, eflags;
+	int etype, emachine;
+	int ephnum, ephentsize, eshnum, eshentsize;
+	off_t ephoff, eshoff;
+	Elf32_Phdr phdr32;
+	Elf64_Phdr phdr64;
+	Elf32_Shdr shdr32;
+	Elf64_Shdr shdr64;
+	Elf32_Sym sym32;
+	Elf64_Sym sym64;
+	int ofs;
+	int chunk_len = 1024, align_len;
+	char *symbol_strings = NULL;
+	size_t symbol_length = 0;
+	const char *s;
+	int n_symbols = 0;
+	Elf32_Sym *symbols_sym32 = NULL;
+	Elf64_Sym *symbols_sym64 = NULL;
+
+	f = fopen(filename, "r");
+	if (f == NULL) {
+		perror(filename);
+		exit(1);
+	}
+
+	len = fread(&hdr32, 1, sizeof(Elf32_Ehdr), f);
+	if (len < (signed int)sizeof(Elf32_Ehdr)) {
+		fprintf(stderr, "%s: not an ELF file image\n", filename);
+		exit(1);
+	}
+
+	if (memcmp(&hdr32.e_ident[EI_MAG0], ELFMAG, SELFMAG) != 0) {
+		fprintf(stderr, "%s: not an ELF file image\n", filename);
+		exit(1);
+	}
+
+	switch (hdr32.e_ident[EI_CLASS]) {
+	case ELFCLASS32:
+		elf64 = 0;
+		break;
+	case ELFCLASS64:
+		elf64 = 1;
+		fseek(f, 0, SEEK_SET);
+		len = fread(&hdr64, 1, sizeof(Elf64_Ehdr), f);
+		if (len < (signed int)sizeof(Elf64_Ehdr)) {
+			fprintf(stderr, "%s: not an ELF64 file image\n",
+			    filename);
+			exit(1);
+		}
+		break;
+	default:
+		fprintf(stderr, "%s: unknown ELF class '%i'\n",
+		    filename, hdr32.e_ident[EI_CLASS]);
+		exit(1);
+	}
+
+	encoding = hdr32.e_ident[EI_DATA];
+	if (encoding != ELFDATA2LSB && encoding != ELFDATA2MSB) {
+		fprintf(stderr, "%s: unknown data encoding '%i'\n",
+		    filename, hdr32.e_ident[EI_DATA]);
+		exit(1);
+	}
+
+	if (elf64) {
+		unencode(etype,      &hdr64.e_type,      Elf64_Quarter);
+		unencode(eflags,     &hdr64.e_flags,     Elf64_Half);
+		unencode(emachine,   &hdr64.e_machine,   Elf64_Quarter);
+		unencode(eentry,     &hdr64.e_entry,     Elf64_Addr);
+		unencode(ephnum,     &hdr64.e_phnum,     Elf64_Quarter);
+		unencode(ephentsize, &hdr64.e_phentsize, Elf64_Quarter);
+		unencode(ephoff,     &hdr64.e_phoff,     Elf64_Off);
+		unencode(eshnum,     &hdr64.e_shnum,     Elf64_Quarter);
+		unencode(eshentsize, &hdr64.e_shentsize, Elf64_Quarter);
+		unencode(eshoff,     &hdr64.e_shoff,     Elf64_Off);
+		if (ephentsize != sizeof(Elf64_Phdr)) {
+			fprintf(stderr, "%s: incorrect phentsize? %i, should "
+			    "be %i\nPerhaps this is a dynamically linked "
+			    "binary (which isn't supported yet).\n", filename,
+			    (int)ephentsize, (int)sizeof(Elf64_Phdr));
+			exit(1);
+		}
+		if (eshentsize != sizeof(Elf64_Shdr)) {
+			fprintf(stderr, "%s: incorrect shentsize? %i, should "
+			    "be %i\nPerhaps this is a dynamically linked "
+			    "binary (which isn't supported yet).\n", filename,
+			    (int)eshentsize, (int)sizeof(Elf64_Shdr));
+			exit(1);
+		}
+	} else {
+		unencode(etype,      &hdr32.e_type,      Elf32_Half);
+		unencode(eflags,     &hdr32.e_flags,     Elf32_Word);
+		unencode(emachine,   &hdr32.e_machine,   Elf32_Half);
+		unencode(eentry,     &hdr32.e_entry,     Elf32_Addr);
+		unencode(ephnum,     &hdr32.e_phnum,     Elf32_Half);
+		unencode(ephentsize, &hdr32.e_phentsize, Elf32_Half);
+		unencode(ephoff,     &hdr32.e_phoff,     Elf32_Off);
+		unencode(eshnum,     &hdr32.e_shnum,     Elf32_Half);
+		unencode(eshentsize, &hdr32.e_shentsize, Elf32_Half);
+		unencode(eshoff,     &hdr32.e_shoff,     Elf32_Off);
+		if (ephentsize != sizeof(Elf32_Phdr)) {
+			fprintf(stderr, "%s: incorrect phentsize? %i, should "
+			    "be %i\nPerhaps this is a dynamically linked "
+			    "binary (which isn't supported yet).\n", filename,
+			    (int)ephentsize, (int)sizeof(Elf32_Phdr));
+			exit(1);
+		}
+		if (eshentsize != sizeof(Elf32_Shdr)) {
+			fprintf(stderr, "%s: incorrect shentsize? %i, should "
+			    "be %i\nPerhaps this is a dynamically linked "
+			    "binary (which isn't supported yet).\n", filename,
+			    (int)eshentsize, (int)sizeof(Elf32_Shdr));
+			exit(1);
+		}
+	}
+
+	if ( etype != ET_EXEC ) {
+		fprintf(stderr, "%s is not an ELF Executable file, type = %i\n",
+		    filename, etype);
+		exit(1);
+	}
+
+	ok = 0;
+	switch (arch) {
+	case ARCH_M88K:
+		switch (emachine) {
+		case EM_88K:
+			ok = 1;
+		}
+		break;
+	case ARCH_ALPHA:
+		switch (emachine) {
+		case EM_ALPHA:
+		case -28634:
+			ok = 1;
+		}
+		break;
+	case ARCH_ARM:
+		switch (emachine) {
+		case EM_ARM:
+			ok = 1;
+		}
+		break;
+	/*  case ARCH_AVR:
+		switch (emachine) {
+		case EM_AVR:
+			ok = 1;
+		}
+		break;
+	case ARCH_AVR32:
+		switch (emachine) {
+		case 6317:
+			ok = 1;
+		}
+		break;
+	case ARCH_HPPA:
+		switch (emachine) {
+		case EM_PARISC:
+			ok = 1;
+		}
+		break;  */
+	case ARCH_I960:
+		switch (emachine) {
+		case EM_960:
+			ok = 1;
+		}
+		break;
+	/*  case ARCH_IA64:
+		switch (emachine) {
+		case EM_IA_64:
+			ok = 1;
+		}
+		break;
+	case ARCH_M68K:
+		switch (emachine) {
+		case EM_68K:
+			ok = 1;
+		}
+		break;
+	case ARCH_M32R:
+		switch (emachine) {
+		case EM_M32R:
+			ok = 1;
+		}
+		break;*/
+	case ARCH_MIPS:
+		switch (emachine) {
+		case EM_MIPS:
+		case EM_MIPS_RS3_LE:
+			ok = 1;
+		}
+		break;
+	case ARCH_PPC:
+		switch (emachine) {
+		case EM_PPC:
+		case EM_PPC64:
+			ok = 1;
+		}
+		break;
+	case ARCH_RISCV:
+		switch (emachine) {
+		case 243:
+			ok = 1;
+		}
+		break;
+	case ARCH_SH:
+		switch (emachine) {
+		case EM_SH:
+			ok = 1;
+		}
+		break;
+	/*case ARCH_SPARC:
+		switch (emachine) {
+		case EM_SPARC:
+		case EM_SPARCV9:
+			ok = 1;
+		}
+		break;
+	case ARCH_X86:
+		switch (emachine) {
+		case EM_386:
+		case EM_486:
+			*tocp = 1;
+			ok = 1;
+			break;
+		case EM_AMD64:
+			*tocp = 2;
+			ok = 1;
+			break;
+		}
+		break;  */
+	default:
+		fatal("file.c: INTERNAL ERROR: Unimplemented arch %i!\n", arch);
+	}
+	if (!ok) {
+		fprintf(stderr, "%s: this is a ", filename);
+		if (emachine >= 0 && emachine < N_ELF_MACHINE_TYPES)
+			fprintf(stderr, "%s", elf_machine_type[emachine]);
+		else
+			fprintf(stderr, "machine type '%i'", emachine);
+		fprintf(stderr, " ELF binary!\n");
+		exit(1);
+	}
+
+	s = "entry point";
+	if (elf64 && arch == ARCH_PPC)
+		s = "function descriptor at";
+
+	debug("ELF%i %s, %s 0x", elf64? 64 : 32,
+	    encoding == ELFDATA2LSB? "LSB (LE)" : "MSB (BE)", s);
+
+	if (elf64)
+		debug("%016" PRIx64"\n", (uint64_t) eentry);
+	else
+		debug("%08" PRIx32"\n", (uint32_t) eentry);
+
+	/*
+	 *  SH64: 32-bit instruction encoding?
+	 */
+	if (arch == ARCH_SH && (eentry & 1)) {
+		fatal("SH64: 32-bit instruction encoding: TODO\n");
+		/*  m->cpus[0]->cd.sh.compact = 0;  */
+		m->cpus[0]->cd.sh.cpu_type.bits = 64;
+		exit(1);
+	}
+
+	/*  Read the program headers:  */
+
+	for (i=0; i<ephnum; i++) {
+		int p_type;
+		uint64_t p_offset;
+		uint64_t p_vaddr;
+		uint64_t p_paddr;
+		uint64_t p_filesz;
+		uint64_t p_memsz;
+		int p_flags;
+		int p_align;
+		int allRead;
+
+		fseek(f, ephoff + i * ephentsize, SEEK_SET);
+
+		if (elf64) {
+			allRead = fread(&phdr64, 1, sizeof(Elf64_Phdr), f) == sizeof(Elf64_Phdr);
+			unencode(p_type,    &phdr64.p_type,    Elf64_Half);
+			unencode(p_flags,   &phdr64.p_flags,   Elf64_Half);
+			unencode(p_offset,  &phdr64.p_offset,  Elf64_Off);
+			unencode(p_vaddr,   &phdr64.p_vaddr,   Elf64_Addr);
+			unencode(p_paddr,   &phdr64.p_paddr,   Elf64_Addr);
+			unencode(p_filesz,  &phdr64.p_filesz,  Elf64_Xword);
+			unencode(p_memsz,   &phdr64.p_memsz,   Elf64_Xword);
+			unencode(p_align,   &phdr64.p_align,   Elf64_Xword);
+		} else {
+			allRead = fread(&phdr32, 1, sizeof(Elf32_Phdr), f) == sizeof(Elf32_Phdr);
+			unencode(p_type,    &phdr32.p_type,    Elf32_Word);
+			unencode(p_offset,  &phdr32.p_offset,  Elf32_Off);
+			unencode(p_vaddr,   &phdr32.p_vaddr,   Elf32_Addr);
+			unencode(p_paddr,   &phdr32.p_paddr,   Elf32_Addr);
+			unencode(p_filesz,  &phdr32.p_filesz,  Elf32_Word);
+			unencode(p_memsz,   &phdr32.p_memsz,   Elf32_Word);
+			unencode(p_flags,   &phdr32.p_flags,   Elf32_Word);
+			unencode(p_align,   &phdr32.p_align,   Elf32_Word);
+		}
+
+		if (!allRead) {
+			fprintf(stderr, "Could not read Phdr from %s. Aborting.\n", filename);
+			exit(1);
+		}
+
+		/*
+		 *  Hack for loading PPC kernels that are linked to high
+		 *  addresses. (This requires enabling of instruction and
+		 *  data virtual address translation.)
+		 */
+		if (arch == ARCH_PPC) {
+			if ( (elf64 && (p_vaddr >> 60) != 0) ||
+			    (!elf64 && (p_vaddr >> 28) != 0) )
+				m->cpus[m->bootstrap_cpu]->
+				    cd.ppc.msr |= PPC_MSR_IR | PPC_MSR_DR;
+		}
+
+		if (p_memsz != 0 && (p_type == PT_LOAD ||
+		    (p_type & PF_MASKPROC) == PT_MIPS_REGINFO)) {
+			debug("chunk %i (", i);
+			if (p_type == PT_LOAD)
+				debug("load");
+			else
+				debug("0x%08" PRIx32, (uint32_t) p_type);
+
+			debug(") @ 0x%" PRIx64", vaddr 0x", (uint64_t) p_offset);
+
+			if (elf64)
+				debug("%016" PRIx64, (uint64_t) p_vaddr);
+			else
+				debug("%08" PRIx32, (uint32_t) p_vaddr);
+
+			debug(" len=0x%" PRIx64"\n", (uint64_t) p_memsz);
+
+			if (p_vaddr != p_paddr) {
+				if (elf64)
+					debug("NOTE: vaddr (0x%" PRIx64") and "
+					    "paddr (0x%" PRIx64") differ; using "
+					    "vaddr\n", (uint64_t) p_vaddr,
+					    (uint64_t) p_paddr);
+				else
+					debug("NOTE: vaddr (0x%08" PRIx32") and "
+					    "paddr (0x%08" PRIx32") differ; usin"
+					    "g vaddr\n", (uint32_t) p_vaddr,
+					    (uint32_t)p_paddr);
+			}
+
+			if (p_memsz < p_filesz) {
+				fprintf(stderr, "%s: memsz < filesz. TODO: how"
+				    " to handle this? memsz=%016" PRIx64
+				    " filesz=%016" PRIx64"\n", filename,
+				    (uint64_t) p_memsz, (uint64_t) p_filesz);
+				exit(1);
+			}
+
+			fseek(f, p_offset, SEEK_SET);
+			align_len = 1;
+			if ((p_vaddr & 0xf)==0)		align_len = 0x10;
+			if ((p_vaddr & 0x3f)==0)	align_len = 0x40;
+			if ((p_vaddr & 0xff)==0)	align_len = 0x100;
+			if ((p_vaddr & 0xfff)==0)	align_len = 0x1000;
+			if ((p_vaddr & 0x3fff)==0)	align_len = 0x4000;
+			if ((p_vaddr & 0xffff)==0)	align_len = 0x10000;
+			ofs = 0;  len = chunk_len = align_len;
+			while (ofs < (int64_t)p_filesz && len==chunk_len) {
+				unsigned char *ch;
+
+				CHECK_ALLOCATION(ch = (unsigned char *) malloc(chunk_len));
+
+				/*  Switch to larger size, if possible:  */
+				if (align_len < 0x10000 &&
+				    ((p_vaddr + ofs) & 0xffff)==0) {
+					align_len = 0x10000;
+					len = chunk_len = align_len;
+					free(ch);
+					CHECK_ALLOCATION(ch=(unsigned char *)malloc(chunk_len));
+				} else if (align_len < 0x1000 &&
+				    ((p_vaddr + ofs) & 0xfff)==0) {
+					align_len = 0x1000;
+					len = chunk_len = align_len;
+					free(ch);
+					CHECK_ALLOCATION(ch=(unsigned char *)malloc(chunk_len));
+				}
+
+				len = fread(&ch[0], 1, chunk_len, f);
+				if (ofs + len > (int64_t)p_filesz)
+					len = p_filesz - ofs;
+
+				int j = 0;
+				while (j < len) {
+					size_t len_to_copy;
+					len_to_copy = (j + align_len) <= len?
+					    align_len : len - j;
+					m->cpus[0]->memory_rw(m->cpus[0], mem,
+					    p_vaddr + ofs, &ch[j], len_to_copy,
+					    MEM_WRITE, NO_EXCEPTIONS);
+					ofs += align_len;
+					j += align_len;
+				}
+
+				free(ch);
+			}
+		}
+	}
+
+	/*
+	 *  Read the section headers to find the address of the _gp
+	 *  symbol (for MIPS):
+	 */
+
+	for (i=0; i<eshnum; i++) {
+		int sh_name, sh_type, sh_flags, sh_link, sh_info, sh_entsize;
+		uint64_t sh_addr, sh_size, sh_addralign;
+		off_t sh_offset;
+		int n_entries;	/*  for reading the symbol / string tables  */
+
+		/*  debug("section header %i at %016" PRIx64"\n", i,
+		    (uint64_t) eshoff+i*eshentsize);  */
+
+		fseek(f, eshoff + i * eshentsize, SEEK_SET);
+
+		if (elf64) {
+			len = fread(&shdr64, 1, sizeof(Elf64_Shdr), f);
+			if (len != sizeof(Elf64_Shdr)) {
+				fprintf(stderr, "couldn't read header\n");
+				exit(1);
+			}
+			unencode(sh_name,    &shdr64.sh_name, Elf64_Half);
+			unencode(sh_type,    &shdr64.sh_type, Elf64_Half);
+			unencode(sh_flags,   &shdr64.sh_flags, Elf64_Xword);
+			unencode(sh_addr,    &shdr64.sh_addr, Elf64_Addr);
+			unencode(sh_offset,  &shdr64.sh_offset, Elf64_Off);
+			unencode(sh_size,    &shdr64.sh_size, Elf64_Xword);
+			unencode(sh_link,    &shdr64.sh_link, Elf64_Half);
+			unencode(sh_info,    &shdr64.sh_info, Elf64_Half);
+			unencode(sh_addralign, &shdr64.sh_addralign,
+			    Elf64_Xword);
+			unencode(sh_entsize, &shdr64.sh_entsize, Elf64_Xword);
+		} else {
+			len = fread(&shdr32, 1, sizeof(Elf32_Shdr), f);
+			if (len != sizeof(Elf32_Shdr)) {
+				fprintf(stderr, "couldn't read header\n");
+				exit(1);
+			}
+			unencode(sh_name,      &shdr32.sh_name,    Elf32_Word);
+			unencode(sh_type,      &shdr32.sh_type,    Elf32_Word);
+			unencode(sh_flags,     &shdr32.sh_flags,   Elf32_Word);
+			unencode(sh_addr,      &shdr32.sh_addr,    Elf32_Addr);
+			unencode(sh_offset,    &shdr32.sh_offset,  Elf32_Off);
+			unencode(sh_size,      &shdr32.sh_size,    Elf32_Word);
+			unencode(sh_link,      &shdr32.sh_link,    Elf32_Word);
+			unencode(sh_info,      &shdr32.sh_info,    Elf32_Word);
+			unencode(sh_addralign, &shdr32.sh_addralign,Elf32_Word);
+			unencode(sh_entsize,   &shdr32.sh_entsize, Elf32_Word);
+		}
+
+		/*  debug("sh_name=%04lx, sh_type=%08lx, sh_flags=%08lx"
+		    " sh_size=%06lx sh_entsize=%03lx\n",
+		    (long)sh_name, (long)sh_type, (long)sh_flags,
+		    (long)sh_size, (long)sh_entsize);  */
+
+		/*  Perhaps it is bad to reuse sh_entsize like this?  TODO  */
+		if (elf64)
+			sh_entsize = sizeof(Elf64_Sym);
+		else
+			sh_entsize = sizeof(Elf32_Sym);
+
+		if (sh_type == SHT_SYMTAB) {
+			size_t len2;
+			n_entries = sh_size / sh_entsize;
+
+			fseek(f, sh_offset, SEEK_SET);
+
+			if (elf64) {
+				if (symbols_sym64 != NULL)
+					free(symbols_sym64);
+
+				CHECK_ALLOCATION(symbols_sym64 = (Elf64_Sym *)
+				    malloc(sh_size));
+
+				len2 = fread(symbols_sym64, 1, sh_entsize *
+				    n_entries, f);
+			} else {
+				if (symbols_sym32 != NULL)
+					free(symbols_sym32);
+
+				CHECK_ALLOCATION(symbols_sym32 = (Elf32_Sym *)
+				    malloc(sh_size));
+
+				len2 = fread(symbols_sym32, 1,
+				    sh_entsize * n_entries, f);
+			}
+
+			if (len2 != sh_size) {
+				fprintf(stderr, "could not read symbols from "
+				    "%s\n", filename);
+				exit(1);
+			}
+
+			debug("%i symbol entries at 0x%" PRIx64"\n",
+			    (int) n_entries, (uint64_t) sh_offset);
+
+			n_symbols = n_entries;
+		}
+
+		/*
+		 *  TODO:  This is incorrect, there may be several strtab
+		 *         sections.
+		 *
+		 *  For now, the simple/stupid guess that the largest string
+		 *  table is the one to use seems to be good enough.
+		 */
+
+		if (sh_type == SHT_STRTAB && sh_size > symbol_length) {
+			if (symbol_strings != NULL)
+				free(symbol_strings);
+
+			CHECK_ALLOCATION(symbol_strings = (char *) malloc(sh_size + 1));
+
+			fseek(f, sh_offset, SEEK_SET);
+			size_t len2 = fread(symbol_strings, 1, sh_size, f);
+			if (len2 != sh_size) {
+				fprintf(stderr, "could not read symbols from "
+				    "%s\n", filename);
+				exit(1);
+			}
+
+			debug("%i bytes of symbol strings at 0x%" PRIx64"\n",
+			    (int) sh_size, (uint64_t) sh_offset);
+
+			symbol_strings[sh_size] = '\0';
+			symbol_length = sh_size;
+		}
+	}
+
+	fclose(f);
+
+	/*  Decode symbols:  */
+	if (symbol_strings != NULL) {
+		for (i=0; i<n_symbols; i++) {
+			uint64_t st_name, addr, size;
+			int st_info;
+
+			if (elf64) {
+				sym64 = symbols_sym64[i];
+				unencode(st_name, &sym64.st_name,  Elf64_Half);
+				unencode(st_info, &sym64.st_info,  Elf_Byte);
+				unencode(addr,    &sym64.st_value, Elf64_Addr);
+				unencode(size,    &sym64.st_size,  Elf64_Xword);
+			} else {
+				sym32 = symbols_sym32[i];
+				unencode(st_name, &sym32.st_name,  Elf32_Word);
+				unencode(st_info, &sym32.st_info,  Elf_Byte);
+				unencode(addr,    &sym32.st_value, Elf32_Word);
+				unencode(size,    &sym32.st_size, Elf32_Word);
+			}
+
+			/*  debug("symbol info=0x%02x addr=0x%016" PRIx64
+			    " (%i) '%s'\n", st_info, (uint64_t) addr,
+			    st_name, symbol_strings + st_name);  */
+
+			if (size == 0)
+				size ++;
+
+			if (addr != 0) /* && ((st_info >> 4) & 0xf)
+			    >= STB_GLOBAL) */ {
+				/*  debug("symbol info=0x%02x addr=0x%016" PRIx64
+				    " '%s'\n", st_info, (uint64_t) addr,
+				    symbol_strings + st_name);  */
+				add_symbol_name(&m->symbol_context,
+				    addr, size, symbol_strings + st_name,
+				    0, -1);
+			}
+
+			if (strcmp(symbol_strings + st_name, "_gp") == 0) {
+				debug("found _gp address: 0x");
+				if (elf64)
+					debug("%016" PRIx64"\n", (uint64_t)addr);
+				else
+					debug("%08" PRIx32"\n", (uint32_t)addr);
+				*gpp = addr;
+			}
+		}
+	}
+
+	*entrypointp = eentry;
+
+	if (encoding == ELFDATA2LSB)
+		*byte_order = EMUL_LITTLE_ENDIAN;
+	else
+		*byte_order = EMUL_BIG_ENDIAN;
+
+	if (elf64 && arch == ARCH_PPC) {
+		/*
+		 *  Special case for 64-bit PPC ELFs:
+		 *
+		 *  The ELF starting symbol points to a ".opd" section
+		 *  which contains a function descriptor:
+		 *
+		 *      uint64_t  start;
+		 *      uint64_t  toc_base;
+		 *      uint64_t  something_else;       (?)
+		 */
+		int res;
+		unsigned char b[sizeof(uint64_t)];
+		uint64_t toc_base;
+
+		debug("PPC64: ");
+
+		res = m->cpus[0]->memory_rw(m->cpus[0], mem, eentry, b,
+		    sizeof(b), MEM_READ, NO_EXCEPTIONS);
+		if (!res)
+			debug(" [WARNING: could not read memory?] ");
+
+		/*  PPC are always big-endian:  */
+		*entrypointp = ((uint64_t)b[0] << 56) +
+		    ((uint64_t)b[1] << 48) + ((uint64_t)b[2] << 40) +
+		    ((uint64_t)b[3] << 32) + ((uint64_t)b[4] << 24) +
+		    ((uint64_t)b[5] << 16) + ((uint64_t)b[6] << 8) +
+		    (uint64_t)b[7];
+
+		res = m->cpus[0]->memory_rw(m->cpus[0], mem, eentry + 8,
+		    b, sizeof(b), MEM_READ, NO_EXCEPTIONS);
+		if (!res)
+			fatal(" [WARNING: could not read memory?] ");
+
+		toc_base = ((uint64_t)b[0] << 56) +
+		    ((uint64_t)b[1] << 48) + ((uint64_t)b[2] << 40) +
+		    ((uint64_t)b[3] << 32) + ((uint64_t)b[4] << 24) +
+		    ((uint64_t)b[5] << 16) + ((uint64_t)b[6] << 8) +
+		    (uint64_t)b[7];
+
+		debug("entrypoint 0x%016" PRIx64", toc_base 0x%016" PRIx64"\n",
+		    (uint64_t) *entrypointp, (uint64_t) toc_base);
+		if (tocp != NULL)
+			*tocp = toc_base;
+	}
+
+	n_executables_loaded ++;
+}
+
diff -Nru gxemul-0.6.2/src/file/file_elf.cc gxemul-0.7.0+dfsg/src/file/file_elf.cc
--- gxemul-0.6.2/src/file/file_elf.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_elf.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,720 +0,0 @@
-/*
- *  Copyright (C) 2003-2014  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: ELF file support
- */
-
-/*  Note: Included from file.c.  */
-
-
-#include "thirdparty/exec_elf.h"
-
-/*  ELF machine types as strings: (same as exec_elf.h)  */
-#define N_ELF_MACHINE_TYPES     89
-static const char *elf_machine_type[N_ELF_MACHINE_TYPES] = {
-        "NONE", "M32", "SPARC", "386",				/*  0..3  */
-        "68K", "88K", "486", "860",				/*  4..7  */  
-        "MIPS", "S370", "MIPS_RS3_LE", "RS6000",		/*  8..11  */
-        "unknown12", "unknown13", "unknown14", "PARISC",	/*  12..15  */
-        "NCUBE", "VPP500", "SPARC32PLUS", "960",		/*  16..19  */
-        "PPC", "PPC64", "unknown22", "unknown23",		/*  20..23  */
-        "unknown24", "unknown25", "unknown26", "unknown27",	/*  24..27  */
-        "unknown28", "unknown29", "unknown30", "unknown31",	/*  28..31  */
-        "unknown32", "unknown33", "unknown34", "unknown35",	/*  32..35  */
-        "V800", "FR20", "RH32", "RCE",				/*  36..39  */
-        "ARM", "ALPHA", "SH", "SPARCV9",			/*  40..43  */
-        "TRICORE", "ARC", "H8_300", "H8_300H",			/*  44..47  */
-        "H8S", "H8_500", "IA_64", "MIPS_X",			/*  48..51  */
-        "COLDFIRE", "68HC12", "unknown54", "unknown55",		/*  52..55  */
-        "unknown56", "unknown57", "unknown58", "unknown59",	/*  56..59  */
-        "unknown60", "unknown61", "AMD64", "unknown63",		/*  60..63  */
-        "unknown64", "unknown65", "unknown66", "unknown67",	/*  64..67  */
-        "unknown68", "unknown69", "unknown70", "unknown71",	/*  68..71  */
-        "unknown72", "unknown73", "unknown74", "unknown75",	/*  72..75  */
-        "unknown76", "unknown77", "unknown78", "unknown79",	/*  76..79  */
-        "unknown80", "unknown81", "unknown82", "AVR",		/*  80..83  */
-        "unknown84", "unknown85", "unknown86", "unknown87",	/*  84..87  */
-        "M32R"							/*  88      */
-};
-
-
-/*
- *  file_load_elf():
- *
- *  Loads an ELF image into the emulated memory.  The entry point (read from
- *  the ELF header) and the initial value of the gp register (read from the
- *  ELF symbol table) are stored in the specified CPU's registers.
- *
- *  This is pretty heavy stuff, but is needed because of the heaviness of
- *  ELF files. :-/   Hopefully it will be able to recognize most valid ELFs.
- */
-static void file_load_elf(struct machine *m, struct memory *mem,
-	char *filename, uint64_t *entrypointp, int arch, uint64_t *gpp,
-	int *byte_order, uint64_t *tocp)
-{
-	Elf32_Ehdr hdr32;
-	Elf64_Ehdr hdr64;
-	FILE *f;
-	uint64_t eentry;
-	int len, i, ok;
-	int elf64, encoding, eflags;
-	int etype, emachine;
-	int ephnum, ephentsize, eshnum, eshentsize;
-	off_t ephoff, eshoff;
-	Elf32_Phdr phdr32;
-	Elf64_Phdr phdr64;
-	Elf32_Shdr shdr32;
-	Elf64_Shdr shdr64;
-	Elf32_Sym sym32;
-	Elf64_Sym sym64;
-	int ofs;
-	int chunk_len = 1024, align_len;
-	char *symbol_strings = NULL;
-	size_t symbol_length = 0;
-	const char *s;
-	int n_symbols = 0;
-	Elf32_Sym *symbols_sym32 = NULL;
-	Elf64_Sym *symbols_sym64 = NULL;
-
-	f = fopen(filename, "r");
-	if (f == NULL) {
-		perror(filename);
-		exit(1);
-	}
-
-	len = fread(&hdr32, 1, sizeof(Elf32_Ehdr), f);
-	if (len < (signed int)sizeof(Elf32_Ehdr)) {
-		fprintf(stderr, "%s: not an ELF file image\n", filename);
-		exit(1);
-	}
-
-	if (memcmp(&hdr32.e_ident[EI_MAG0], ELFMAG, SELFMAG) != 0) {
-		fprintf(stderr, "%s: not an ELF file image\n", filename);
-		exit(1);
-	}
-
-	switch (hdr32.e_ident[EI_CLASS]) {
-	case ELFCLASS32:
-		elf64 = 0;
-		break;
-	case ELFCLASS64:
-		elf64 = 1;
-		fseek(f, 0, SEEK_SET);
-		len = fread(&hdr64, 1, sizeof(Elf64_Ehdr), f);
-		if (len < (signed int)sizeof(Elf64_Ehdr)) {
-			fprintf(stderr, "%s: not an ELF64 file image\n",
-			    filename);
-			exit(1);
-		}
-		break;
-	default:
-		fprintf(stderr, "%s: unknown ELF class '%i'\n",
-		    filename, hdr32.e_ident[EI_CLASS]);
-		exit(1);
-	}
-
-	encoding = hdr32.e_ident[EI_DATA];
-	if (encoding != ELFDATA2LSB && encoding != ELFDATA2MSB) {
-		fprintf(stderr, "%s: unknown data encoding '%i'\n",
-		    filename, hdr32.e_ident[EI_DATA]);
-		exit(1);
-	}
-
-	if (elf64) {
-		unencode(etype,      &hdr64.e_type,      Elf64_Quarter);
-		unencode(eflags,     &hdr64.e_flags,     Elf64_Half);
-		unencode(emachine,   &hdr64.e_machine,   Elf64_Quarter);
-		unencode(eentry,     &hdr64.e_entry,     Elf64_Addr);
-		unencode(ephnum,     &hdr64.e_phnum,     Elf64_Quarter);
-		unencode(ephentsize, &hdr64.e_phentsize, Elf64_Quarter);
-		unencode(ephoff,     &hdr64.e_phoff,     Elf64_Off);
-		unencode(eshnum,     &hdr64.e_shnum,     Elf64_Quarter);
-		unencode(eshentsize, &hdr64.e_shentsize, Elf64_Quarter);
-		unencode(eshoff,     &hdr64.e_shoff,     Elf64_Off);
-		if (ephentsize != sizeof(Elf64_Phdr)) {
-			fprintf(stderr, "%s: incorrect phentsize? %i, should "
-			    "be %i\nPerhaps this is a dynamically linked "
-			    "binary (which isn't supported yet).\n", filename,
-			    (int)ephentsize, (int)sizeof(Elf64_Phdr));
-			exit(1);
-		}
-		if (eshentsize != sizeof(Elf64_Shdr)) {
-			fprintf(stderr, "%s: incorrect shentsize? %i, should "
-			    "be %i\nPerhaps this is a dynamically linked "
-			    "binary (which isn't supported yet).\n", filename,
-			    (int)eshentsize, (int)sizeof(Elf64_Shdr));
-			exit(1);
-		}
-	} else {
-		unencode(etype,      &hdr32.e_type,      Elf32_Half);
-		unencode(eflags,     &hdr32.e_flags,     Elf32_Word);
-		unencode(emachine,   &hdr32.e_machine,   Elf32_Half);
-		unencode(eentry,     &hdr32.e_entry,     Elf32_Addr);
-		unencode(ephnum,     &hdr32.e_phnum,     Elf32_Half);
-		unencode(ephentsize, &hdr32.e_phentsize, Elf32_Half);
-		unencode(ephoff,     &hdr32.e_phoff,     Elf32_Off);
-		unencode(eshnum,     &hdr32.e_shnum,     Elf32_Half);
-		unencode(eshentsize, &hdr32.e_shentsize, Elf32_Half);
-		unencode(eshoff,     &hdr32.e_shoff,     Elf32_Off);
-		if (ephentsize != sizeof(Elf32_Phdr)) {
-			fprintf(stderr, "%s: incorrect phentsize? %i, should "
-			    "be %i\nPerhaps this is a dynamically linked "
-			    "binary (which isn't supported yet).\n", filename,
-			    (int)ephentsize, (int)sizeof(Elf32_Phdr));
-			exit(1);
-		}
-		if (eshentsize != sizeof(Elf32_Shdr)) {
-			fprintf(stderr, "%s: incorrect shentsize? %i, should "
-			    "be %i\nPerhaps this is a dynamically linked "
-			    "binary (which isn't supported yet).\n", filename,
-			    (int)eshentsize, (int)sizeof(Elf32_Shdr));
-			exit(1);
-		}
-	}
-
-	if ( etype != ET_EXEC ) {
-		fprintf(stderr, "%s is not an ELF Executable file, type = %i\n",
-		    filename, etype);
-		exit(1);
-	}
-
-	ok = 0;
-	switch (arch) {
-	case ARCH_M88K:
-		switch (emachine) {
-		case EM_88K:
-			ok = 1;
-		}
-		break;
-	case ARCH_ALPHA:
-		switch (emachine) {
-		case EM_ALPHA:
-		case -28634:
-			ok = 1;
-		}
-		break;
-	case ARCH_ARM:
-		switch (emachine) {
-		case EM_ARM:
-			ok = 1;
-		}
-		break;
-	/*  case ARCH_AVR:
-		switch (emachine) {
-		case EM_AVR:
-			ok = 1;
-		}
-		break;
-	case ARCH_AVR32:
-		switch (emachine) {
-		case 6317:
-			ok = 1;
-		}
-		break;
-	case ARCH_HPPA:
-		switch (emachine) {
-		case EM_PARISC:
-			ok = 1;
-		}
-		break;
-	case ARCH_I960:
-		switch (emachine) {
-		case EM_960:
-			ok = 1;
-		}
-		break;
-	case ARCH_IA64:
-		switch (emachine) {
-		case EM_IA_64:
-			ok = 1;
-		}
-		break;
-	case ARCH_M68K:
-		switch (emachine) {
-		case EM_68K:
-			ok = 1;
-		}
-		break;
-	case ARCH_M32R:
-		switch (emachine) {
-		case EM_M32R:
-			ok = 1;
-		}
-		break;*/
-	case ARCH_MIPS:
-		switch (emachine) {
-		case EM_MIPS:
-		case EM_MIPS_RS3_LE:
-			ok = 1;
-		}
-		break;
-	case ARCH_PPC:
-		switch (emachine) {
-		case EM_PPC:
-		case EM_PPC64:
-			ok = 1;
-		}
-		break;
-	case ARCH_SH:
-		switch (emachine) {
-		case EM_SH:
-			ok = 1;
-		}
-		break;
-	/*case ARCH_SPARC:
-		switch (emachine) {
-		case EM_SPARC:
-		case EM_SPARCV9:
-			ok = 1;
-		}
-		break;
-	case ARCH_X86:
-		switch (emachine) {
-		case EM_386:
-		case EM_486:
-			*tocp = 1;
-			ok = 1;
-			break;
-		case EM_AMD64:
-			*tocp = 2;
-			ok = 1;
-			break;
-		}
-		break;  */
-	default:
-		fatal("file.c: INTERNAL ERROR: Unimplemented arch!\n");
-	}
-	if (!ok) {
-		fprintf(stderr, "%s: this is a ", filename);
-		if (emachine >= 0 && emachine < N_ELF_MACHINE_TYPES)
-			fprintf(stderr, "%s", elf_machine_type[emachine]);
-		else
-			fprintf(stderr, "machine type '%i'", emachine);
-		fprintf(stderr, " ELF binary!\n");
-		exit(1);
-	}
-
-	s = "entry point";
-	if (elf64 && arch == ARCH_PPC)
-		s = "function descriptor at";
-
-	debug("ELF%i %s, %s 0x", elf64? 64 : 32,
-	    encoding == ELFDATA2LSB? "LSB (LE)" : "MSB (BE)", s);
-
-	if (elf64)
-		debug("%016" PRIx64"\n", (uint64_t) eentry);
-	else
-		debug("%08" PRIx32"\n", (uint32_t) eentry);
-
-	/*
-	 *  SH64: 32-bit instruction encoding?
-	 */
-	if (arch == ARCH_SH && (eentry & 1)) {
-		fatal("SH64: 32-bit instruction encoding: TODO\n");
-		/*  m->cpus[0]->cd.sh.compact = 0;  */
-		m->cpus[0]->cd.sh.cpu_type.bits = 64;
-		exit(1);
-	}
-
-	/*  Read the program headers:  */
-
-	for (i=0; i<ephnum; i++) {
-		int p_type;
-		uint64_t p_offset;
-		uint64_t p_vaddr;
-		uint64_t p_paddr;
-		uint64_t p_filesz;
-		uint64_t p_memsz;
-		int p_flags;
-		int p_align;
-		int allRead;
-
-		fseek(f, ephoff + i * ephentsize, SEEK_SET);
-
-		if (elf64) {
-			allRead = fread(&phdr64, 1, sizeof(Elf64_Phdr), f) == sizeof(Elf64_Phdr);
-			unencode(p_type,    &phdr64.p_type,    Elf64_Half);
-			unencode(p_flags,   &phdr64.p_flags,   Elf64_Half);
-			unencode(p_offset,  &phdr64.p_offset,  Elf64_Off);
-			unencode(p_vaddr,   &phdr64.p_vaddr,   Elf64_Addr);
-			unencode(p_paddr,   &phdr64.p_paddr,   Elf64_Addr);
-			unencode(p_filesz,  &phdr64.p_filesz,  Elf64_Xword);
-			unencode(p_memsz,   &phdr64.p_memsz,   Elf64_Xword);
-			unencode(p_align,   &phdr64.p_align,   Elf64_Xword);
-		} else {
-			allRead = fread(&phdr32, 1, sizeof(Elf32_Phdr), f) == sizeof(Elf32_Phdr);
-			unencode(p_type,    &phdr32.p_type,    Elf32_Word);
-			unencode(p_offset,  &phdr32.p_offset,  Elf32_Off);
-			unencode(p_vaddr,   &phdr32.p_vaddr,   Elf32_Addr);
-			unencode(p_paddr,   &phdr32.p_paddr,   Elf32_Addr);
-			unencode(p_filesz,  &phdr32.p_filesz,  Elf32_Word);
-			unencode(p_memsz,   &phdr32.p_memsz,   Elf32_Word);
-			unencode(p_flags,   &phdr32.p_flags,   Elf32_Word);
-			unencode(p_align,   &phdr32.p_align,   Elf32_Word);
-		}
-
-		if (!allRead) {
-			fprintf(stderr, "Could not read Phdr from %s. Aborting.\n", filename);
-			exit(1);
-		}
-
-		/*
-		 *  Hack for loading PPC kernels that are linked to high
-		 *  addresses. (This requires enabling of instruction and
-		 *  data virtual address translation.)
-		 */
-		if (arch == ARCH_PPC) {
-			if ( (elf64 && (p_vaddr >> 60) != 0) ||
-			    (!elf64 && (p_vaddr >> 28) != 0) )
-				m->cpus[m->bootstrap_cpu]->
-				    cd.ppc.msr |= PPC_MSR_IR | PPC_MSR_DR;
-		}
-
-		if (p_memsz != 0 && (p_type == PT_LOAD ||
-		    (p_type & PF_MASKPROC) == PT_MIPS_REGINFO)) {
-			debug("chunk %i (", i);
-			if (p_type == PT_LOAD)
-				debug("load");
-			else
-				debug("0x%08" PRIx32, (uint32_t) p_type);
-
-			debug(") @ 0x%" PRIx64", vaddr 0x", (uint64_t) p_offset);
-
-			if (elf64)
-				debug("%016" PRIx64, (uint64_t) p_vaddr);
-			else
-				debug("%08" PRIx32, (uint32_t) p_vaddr);
-
-			debug(" len=0x%" PRIx64"\n", (uint64_t) p_memsz);
-
-			if (p_vaddr != p_paddr) {
-				if (elf64)
-					debug("NOTE: vaddr (0x%" PRIx64") and "
-					    "paddr (0x%" PRIx64") differ; using "
-					    "vaddr\n", (uint64_t) p_vaddr,
-					    (uint64_t) p_paddr);
-				else
-					debug("NOTE: vaddr (0x%08" PRIx32") and "
-					    "paddr (0x%08" PRIx32") differ; usin"
-					    "g vaddr\n", (uint32_t) p_vaddr,
-					    (uint32_t)p_paddr);
-			}
-
-			if (p_memsz < p_filesz) {
-				fprintf(stderr, "%s: memsz < filesz. TODO: how"
-				    " to handle this? memsz=%016" PRIx64
-				    " filesz=%016" PRIx64"\n", filename,
-				    (uint64_t) p_memsz, (uint64_t) p_filesz);
-				exit(1);
-			}
-
-			fseek(f, p_offset, SEEK_SET);
-			align_len = 1;
-			if ((p_vaddr & 0xf)==0)		align_len = 0x10;
-			if ((p_vaddr & 0x3f)==0)	align_len = 0x40;
-			if ((p_vaddr & 0xff)==0)	align_len = 0x100;
-			if ((p_vaddr & 0xfff)==0)	align_len = 0x1000;
-			if ((p_vaddr & 0x3fff)==0)	align_len = 0x4000;
-			if ((p_vaddr & 0xffff)==0)	align_len = 0x10000;
-			ofs = 0;  len = chunk_len = align_len;
-			while (ofs < (int64_t)p_filesz && len==chunk_len) {
-				unsigned char *ch;
-
-				CHECK_ALLOCATION(ch = (unsigned char *) malloc(chunk_len));
-
-				/*  Switch to larger size, if possible:  */
-				if (align_len < 0x10000 &&
-				    ((p_vaddr + ofs) & 0xffff)==0) {
-					align_len = 0x10000;
-					len = chunk_len = align_len;
-					free(ch);
-					CHECK_ALLOCATION(ch=(unsigned char *)malloc(chunk_len));
-				} else if (align_len < 0x1000 &&
-				    ((p_vaddr + ofs) & 0xfff)==0) {
-					align_len = 0x1000;
-					len = chunk_len = align_len;
-					free(ch);
-					CHECK_ALLOCATION(ch=(unsigned char *)malloc(chunk_len));
-				}
-
-				len = fread(&ch[0], 1, chunk_len, f);
-				if (ofs + len > (int64_t)p_filesz)
-					len = p_filesz - ofs;
-
-				int j = 0;
-				while (j < len) {
-					size_t len_to_copy;
-					len_to_copy = (j + align_len) <= len?
-					    align_len : len - j;
-					m->cpus[0]->memory_rw(m->cpus[0], mem,
-					    p_vaddr + ofs, &ch[j], len_to_copy,
-					    MEM_WRITE, NO_EXCEPTIONS);
-					ofs += align_len;
-					j += align_len;
-				}
-
-				free(ch);
-			}
-		}
-	}
-
-	/*
-	 *  Read the section headers to find the address of the _gp
-	 *  symbol (for MIPS):
-	 */
-
-	for (i=0; i<eshnum; i++) {
-		int sh_name, sh_type, sh_flags, sh_link, sh_info, sh_entsize;
-		uint64_t sh_addr, sh_size, sh_addralign;
-		off_t sh_offset;
-		int n_entries;	/*  for reading the symbol / string tables  */
-
-		/*  debug("section header %i at %016" PRIx64"\n", i,
-		    (uint64_t) eshoff+i*eshentsize);  */
-
-		fseek(f, eshoff + i * eshentsize, SEEK_SET);
-
-		if (elf64) {
-			len = fread(&shdr64, 1, sizeof(Elf64_Shdr), f);
-			if (len != sizeof(Elf64_Shdr)) {
-				fprintf(stderr, "couldn't read header\n");
-				exit(1);
-			}
-			unencode(sh_name,    &shdr64.sh_name, Elf64_Half);
-			unencode(sh_type,    &shdr64.sh_type, Elf64_Half);
-			unencode(sh_flags,   &shdr64.sh_flags, Elf64_Xword);
-			unencode(sh_addr,    &shdr64.sh_addr, Elf64_Addr);
-			unencode(sh_offset,  &shdr64.sh_offset, Elf64_Off);
-			unencode(sh_size,    &shdr64.sh_size, Elf64_Xword);
-			unencode(sh_link,    &shdr64.sh_link, Elf64_Half);
-			unencode(sh_info,    &shdr64.sh_info, Elf64_Half);
-			unencode(sh_addralign, &shdr64.sh_addralign,
-			    Elf64_Xword);
-			unencode(sh_entsize, &shdr64.sh_entsize, Elf64_Xword);
-		} else {
-			len = fread(&shdr32, 1, sizeof(Elf32_Shdr), f);
-			if (len != sizeof(Elf32_Shdr)) {
-				fprintf(stderr, "couldn't read header\n");
-				exit(1);
-			}
-			unencode(sh_name,      &shdr32.sh_name,    Elf32_Word);
-			unencode(sh_type,      &shdr32.sh_type,    Elf32_Word);
-			unencode(sh_flags,     &shdr32.sh_flags,   Elf32_Word);
-			unencode(sh_addr,      &shdr32.sh_addr,    Elf32_Addr);
-			unencode(sh_offset,    &shdr32.sh_offset,  Elf32_Off);
-			unencode(sh_size,      &shdr32.sh_size,    Elf32_Word);
-			unencode(sh_link,      &shdr32.sh_link,    Elf32_Word);
-			unencode(sh_info,      &shdr32.sh_info,    Elf32_Word);
-			unencode(sh_addralign, &shdr32.sh_addralign,Elf32_Word);
-			unencode(sh_entsize,   &shdr32.sh_entsize, Elf32_Word);
-		}
-
-		/*  debug("sh_name=%04lx, sh_type=%08lx, sh_flags=%08lx"
-		    " sh_size=%06lx sh_entsize=%03lx\n",
-		    (long)sh_name, (long)sh_type, (long)sh_flags,
-		    (long)sh_size, (long)sh_entsize);  */
-
-		/*  Perhaps it is bad to reuse sh_entsize like this?  TODO  */
-		if (elf64)
-			sh_entsize = sizeof(Elf64_Sym);
-		else
-			sh_entsize = sizeof(Elf32_Sym);
-
-		if (sh_type == SHT_SYMTAB) {
-			size_t len2;
-			n_entries = sh_size / sh_entsize;
-
-			fseek(f, sh_offset, SEEK_SET);
-
-			if (elf64) {
-				if (symbols_sym64 != NULL)
-					free(symbols_sym64);
-
-				CHECK_ALLOCATION(symbols_sym64 = (Elf64_Sym *)
-				    malloc(sh_size));
-
-				len2 = fread(symbols_sym64, 1, sh_entsize *
-				    n_entries, f);
-			} else {
-				if (symbols_sym32 != NULL)
-					free(symbols_sym32);
-
-				CHECK_ALLOCATION(symbols_sym32 = (Elf32_Sym *)
-				    malloc(sh_size));
-
-				len2 = fread(symbols_sym32, 1,
-				    sh_entsize * n_entries, f);
-			}
-
-			if (len2 != sh_size) {
-				fprintf(stderr, "could not read symbols from "
-				    "%s\n", filename);
-				exit(1);
-			}
-
-			debug("%i symbol entries at 0x%" PRIx64"\n",
-			    (int) n_entries, (uint64_t) sh_offset);
-
-			n_symbols = n_entries;
-		}
-
-		/*
-		 *  TODO:  This is incorrect, there may be several strtab
-		 *         sections.
-		 *
-		 *  For now, the simple/stupid guess that the largest string
-		 *  table is the one to use seems to be good enough.
-		 */
-
-		if (sh_type == SHT_STRTAB && sh_size > symbol_length) {
-			if (symbol_strings != NULL)
-				free(symbol_strings);
-
-			CHECK_ALLOCATION(symbol_strings = (char *) malloc(sh_size + 1));
-
-			fseek(f, sh_offset, SEEK_SET);
-			size_t len2 = fread(symbol_strings, 1, sh_size, f);
-			if (len2 != sh_size) {
-				fprintf(stderr, "could not read symbols from "
-				    "%s\n", filename);
-				exit(1);
-			}
-
-			debug("%i bytes of symbol strings at 0x%" PRIx64"\n",
-			    (int) sh_size, (uint64_t) sh_offset);
-
-			symbol_strings[sh_size] = '\0';
-			symbol_length = sh_size;
-		}
-	}
-
-	fclose(f);
-
-	/*  Decode symbols:  */
-	if (symbol_strings != NULL) {
-		for (i=0; i<n_symbols; i++) {
-			uint64_t st_name, addr, size;
-			int st_info;
-
-			if (elf64) {
-				sym64 = symbols_sym64[i];
-				unencode(st_name, &sym64.st_name,  Elf64_Half);
-				unencode(st_info, &sym64.st_info,  Elf_Byte);
-				unencode(addr,    &sym64.st_value, Elf64_Addr);
-				unencode(size,    &sym64.st_size,  Elf64_Xword);
-			} else {
-				sym32 = symbols_sym32[i];
-				unencode(st_name, &sym32.st_name,  Elf32_Word);
-				unencode(st_info, &sym32.st_info,  Elf_Byte);
-				unencode(addr,    &sym32.st_value, Elf32_Word);
-				unencode(size,    &sym32.st_size, Elf32_Word);
-			}
-
-			/*  debug("symbol info=0x%02x addr=0x%016" PRIx64
-			    " (%i) '%s'\n", st_info, (uint64_t) addr,
-			    st_name, symbol_strings + st_name);  */
-
-			if (size == 0)
-				size ++;
-
-			if (addr != 0) /* && ((st_info >> 4) & 0xf)
-			    >= STB_GLOBAL) */ {
-				/*  debug("symbol info=0x%02x addr=0x%016" PRIx64
-				    " '%s'\n", st_info, (uint64_t) addr,
-				    symbol_strings + st_name);  */
-				add_symbol_name(&m->symbol_context,
-				    addr, size, symbol_strings + st_name,
-				    0, -1);
-			}
-
-			if (strcmp(symbol_strings + st_name, "_gp") == 0) {
-				debug("found _gp address: 0x");
-				if (elf64)
-					debug("%016" PRIx64"\n", (uint64_t)addr);
-				else
-					debug("%08" PRIx32"\n", (uint32_t)addr);
-				*gpp = addr;
-			}
-		}
-	}
-
-	*entrypointp = eentry;
-
-	if (encoding == ELFDATA2LSB)
-		*byte_order = EMUL_LITTLE_ENDIAN;
-	else
-		*byte_order = EMUL_BIG_ENDIAN;
-
-	if (elf64 && arch == ARCH_PPC) {
-		/*
-		 *  Special case for 64-bit PPC ELFs:
-		 *
-		 *  The ELF starting symbol points to a ".opd" section
-		 *  which contains a function descriptor:
-		 *
-		 *      uint64_t  start;
-		 *      uint64_t  toc_base;
-		 *      uint64_t  something_else;       (?)
-		 */
-		int res;
-		unsigned char b[sizeof(uint64_t)];
-		uint64_t toc_base;
-
-		debug("PPC64: ");
-
-		res = m->cpus[0]->memory_rw(m->cpus[0], mem, eentry, b,
-		    sizeof(b), MEM_READ, NO_EXCEPTIONS);
-		if (!res)
-			debug(" [WARNING: could not read memory?] ");
-
-		/*  PPC are always big-endian:  */
-		*entrypointp = ((uint64_t)b[0] << 56) +
-		    ((uint64_t)b[1] << 48) + ((uint64_t)b[2] << 40) +
-		    ((uint64_t)b[3] << 32) + ((uint64_t)b[4] << 24) +
-		    ((uint64_t)b[5] << 16) + ((uint64_t)b[6] << 8) +
-		    (uint64_t)b[7];
-
-		res = m->cpus[0]->memory_rw(m->cpus[0], mem, eentry + 8,
-		    b, sizeof(b), MEM_READ, NO_EXCEPTIONS);
-		if (!res)
-			fatal(" [WARNING: could not read memory?] ");
-
-		toc_base = ((uint64_t)b[0] << 56) +
-		    ((uint64_t)b[1] << 48) + ((uint64_t)b[2] << 40) +
-		    ((uint64_t)b[3] << 32) + ((uint64_t)b[4] << 24) +
-		    ((uint64_t)b[5] << 16) + ((uint64_t)b[6] << 8) +
-		    (uint64_t)b[7];
-
-		debug("entrypoint 0x%016" PRIx64", toc_base 0x%016" PRIx64"\n",
-		    (uint64_t) *entrypointp, (uint64_t) toc_base);
-		if (tocp != NULL)
-			*tocp = toc_base;
-	}
-
-	n_executables_loaded ++;
-}
-
diff -Nru gxemul-0.6.2/src/file/file_macho.c gxemul-0.7.0+dfsg/src/file/file_macho.c
--- gxemul-0.6.2/src/file/file_macho.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_macho.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,307 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Mach-O file support
+ */
+
+/*  Note: Included from file.c.  */
+
+
+/*
+ *  file_load_macho():
+ *
+ *  Loads a Mach-O binary image into the emulated memory. The entry point
+ *  is stored in the specified CPU's registers.
+ *
+ *  TODO:
+ *
+ *	o)  Almost everything.
+ *
+ *	o)  I haven't had time to look into whether Apple's open source
+ *	    license is BSD-compatible or not. Perhaps it would be possible
+ *	    to use a header file containing symbolic names, and not use
+ *	    hardcoded values.
+ */
+static void file_load_macho(struct machine *m, struct memory *mem,
+	char *filename, uint64_t *entrypointp, int arch, int *byte_orderp,
+	int is_64bit, int is_reversed)
+{
+	FILE *f;
+	uint64_t entry = 0;
+	int entry_set = 0;
+	int encoding = ELFDATA2MSB;
+	unsigned char buf[65536];
+	char *symbols, *strings;
+	uint32_t cputype, cpusubtype, filetype, ncmds, sizeofcmds, flags;
+	uint64_t vmaddr, vmsize, fileoff, filesize;
+	int cmd_type, cmd_len, i, flavor;
+	int32_t symoff, nsyms, stroff, strsize;
+	size_t len, pos;
+
+	if (m->cpus[0]->byte_order == EMUL_BIG_ENDIAN)
+		encoding = ELFDATA2MSB;
+
+	f = fopen(filename, "r");
+	if (f == NULL) {
+		perror(filename);
+		exit(1);
+	}
+
+	if (is_64bit) {
+		fatal("TODO: 64-bit Mach-O. Not supported yet.\n");
+		exit(1);
+	}
+	if (is_reversed) {
+		fatal("TODO: Reversed-endianness. Not supported yet.\n");
+		exit(1);
+	}
+
+	len = fread(buf, 1, sizeof(buf), f);
+	if (len < 100) {
+		fatal("Bad Mach-O file?\n");
+		exit(1);
+	}
+
+	unencode(cputype,    &buf[4], uint32_t);
+	unencode(cpusubtype, &buf[8], uint32_t);
+	unencode(filetype,   &buf[12], uint32_t);
+	unencode(ncmds,      &buf[16], uint32_t);
+	unencode(sizeofcmds, &buf[20], uint32_t);
+	unencode(flags,      &buf[24], uint32_t);
+
+	/*  debug("cputype=0x%x cpusubtype=0x%x filetype=0x%x\n",
+	    cputype, cpusubtype, filetype);
+	    debug("ncmds=%i sizeofcmds=0x%08x flags=0x%08x\n",
+	    ncmds, sizeofcmds, flags);  */
+
+	/*
+	 *  Compare to "normal" values.
+	 *  NOTE/TODO: These were for a Darwin (Macintosh PPC) kernel.
+	 */
+	if (cputype != 0x12) {
+		fatal("Error: Unimplemented cputype 0x%x\n", cputype);
+		exit(1);
+	}
+	if (cpusubtype != 0) {
+		fatal("Error: Unimplemented cpusubtype 0x%x\n", cpusubtype);
+		exit(1);
+	}
+	/*  Filetype 2 means an executable image.  */
+	if (filetype != 2) {
+		fatal("Error: Unimplemented filetype 0x%x\n", filetype);
+		exit(1);
+	}
+	if (!(flags & 1)) {
+		fatal("Error: File has 'undefined references'. Cannot"
+		    " be executed.\n", flags);
+		exit(1);
+	}
+
+	/*  I've only encountered flags == 1 so far.  */
+	if (flags != 1) {
+		fatal("Error: Unimplemented flags 0x%x\n", flags);
+		exit(1);
+	}
+
+	/*
+	 *  Read all load commands:
+	 */
+	pos = is_64bit? 32 : 28;
+	cmd_type = 0;
+	do {
+		/*  Read command type and length:  */
+		unencode(cmd_type, &buf[pos], uint32_t);
+		unencode(cmd_len,  &buf[pos+4], uint32_t);
+
+#if 0
+		debug("cmd %i, len=%i\n", cmd_type, cmd_len);
+		for (i=8; i<cmd_len; i++) {
+			unsigned char ch = buf[pos+i];
+			if (ch >= ' ' && ch < 127)
+				debug("%c", ch);
+			else
+				debug(".");
+		}
+#endif
+		switch (cmd_type) {
+		case 1:	/*  LC_SEGMENT  */
+			debug("seg ");
+			for (i=0; i<16; i++) {
+				if (buf[pos + 8 + i] == 0)
+					break;
+				debug("%c", buf[pos + 8 + i]);
+			}
+			unencode(vmaddr,   &buf[pos+8+16+0], uint32_t);
+			unencode(vmsize,   &buf[pos+8+16+4], uint32_t);
+			unencode(fileoff,  &buf[pos+8+16+8], uint32_t);
+			unencode(filesize, &buf[pos+8+16+12], uint32_t);
+			debug(": vmaddr=0x%x size=0x%x fileoff=0x%x",
+			    (int)vmaddr, (int)vmsize, (int)fileoff);
+
+			if (filesize == 0) {
+				debug("\n");
+				break;
+			}
+
+			fseek(f, fileoff, SEEK_SET);
+
+			/*  Load data from the file:  */
+			while (filesize != 0) {
+				unsigned char buf2[32768];
+				ssize_t lenRead = filesize > sizeof(buf2) ?
+				    sizeof(buf2) : filesize;
+				lenRead = fread(buf2, 1, lenRead, f);
+
+				/*  printf("fread len=%i vmaddr=%x buf[0..]="
+				    "%02x %02x %02x\n", (int)len, (int)vmaddr,
+				    buf2[0], buf2[1], buf2[2]);  */
+
+				if (lenRead > 0) {
+					int len2 = 0;
+					uint64_t vaddr1 = vmaddr &
+					    ((1 << BITS_PER_MEMBLOCK) - 1);
+					uint64_t vaddr2 = (vmaddr +
+					    lenRead) & ((1 << BITS_PER_MEMBLOCK)-1);
+					if (vaddr2 < vaddr1) {
+						len2 = lenRead - vaddr2;
+						m->cpus[0]->memory_rw(m->cpus[
+						    0], mem, vmaddr, &buf2[0],
+						    len2, MEM_WRITE,
+						    NO_EXCEPTIONS);
+					}
+					m->cpus[0]->memory_rw(m->cpus[0], mem,
+					    vmaddr + len2, &buf2[len2], lenRead-len2,
+					    MEM_WRITE, NO_EXCEPTIONS);
+				} else {
+					fprintf(stderr, "error reading\n");
+					exit(1);
+				}
+
+				vmaddr += lenRead;
+				filesize -= lenRead;
+			}
+
+			debug("\n");
+			break;
+
+		case 2:	/*  LC_SYMTAB  */
+			unencode(symoff,  &buf[pos+8], uint32_t);
+			unencode(nsyms,   &buf[pos+12], uint32_t);
+			unencode(stroff,  &buf[pos+16], uint32_t);
+			unencode(strsize, &buf[pos+20], uint32_t);
+			debug("symtable: %i symbols @ 0x%x (strings at "
+			    "0x%x)\n", nsyms, symoff, stroff);
+
+			CHECK_ALLOCATION(symbols = (char *) malloc(12 * nsyms));
+			fseek(f, symoff, SEEK_SET);
+			if (fread(symbols, 1, 12 * nsyms, f) != (size_t) 12*nsyms) {
+				fprintf(stderr, "could not read symbols from %s\n", filename);
+				exit(1);
+			}
+
+			CHECK_ALLOCATION(strings = (char *) malloc(strsize));
+			fseek(f, stroff, SEEK_SET);
+			if (fread(strings, 1, strsize, f) != (size_t) strsize) {
+				fprintf(stderr, "could not read symbol strings from %s\n", filename);
+				exit(1);
+			}
+
+			for (i=0; i<nsyms; i++) {
+				int n_strx, n_type, n_sect, n_desc;
+				uint32_t n_value;
+				unencode(n_strx,  &symbols[i*12+0], int32_t);
+				unencode(n_type,  &symbols[i*12+4], uint8_t);
+				unencode(n_sect,  &symbols[i*12+5], uint8_t);
+				unencode(n_desc,  &symbols[i*12+6], int16_t);
+				unencode(n_value, &symbols[i*12+8], uint32_t);
+				/*  debug("%i: strx=%i type=%i sect=%i desc=%i"
+				    " value=0x%x\n", i, n_strx, n_type,
+				    n_sect, n_desc, n_value);  */
+				add_symbol_name(&m->symbol_context,
+				    n_value, 0, strings + n_strx, 0, -1);
+			}
+
+			free(symbols);
+			free(strings);
+			break;
+
+		case 5:	debug("unix thread context: ");
+			/*  See http://cvs.sf.net/viewcvs.py/hte/
+			    HT%20Editor/machostruc.h or similar for details
+			    on the thread struct.  */
+			unencode(flavor, &buf[pos+8], uint32_t);
+			if (flavor != 1) {
+				fatal("unimplemented flavor %i\n", flavor);
+				exit(1);
+			}
+
+			if (arch != ARCH_PPC) {
+				fatal("non-PPC arch? TODO\n");
+				exit(1);
+			}
+
+			unencode(entry, &buf[pos+16], uint32_t);
+			entry_set = 1;
+			debug("pc=0x%x\n", (int)entry);
+
+			for (i=1; i<40; i++) {
+				uint32_t x;
+				unencode(x, &buf[pos+16+i*4], uint32_t);
+				if (x != 0) {
+					fatal("Entry nr %i in the Mach-O"
+					    " thread struct is non-zero"
+					    " (0x%x). This is not supported"
+					    " yet. TODO\n", i, x);
+					exit(1);
+				}
+			}
+			break;
+
+		default:fatal("WARNING! Unimplemented load command %i!\n",
+			    cmd_type);
+		}
+
+		pos += cmd_len;
+	} while (pos < sizeofcmds && cmd_type != 0);
+
+	fclose(f);
+
+	if (!entry_set) {
+		fatal("No entry point? Aborting.\n");
+		exit(1);
+	}
+
+	*entrypointp = entry;
+
+	if (encoding == ELFDATA2LSB)
+		*byte_orderp = EMUL_LITTLE_ENDIAN;
+	else
+		*byte_orderp = EMUL_BIG_ENDIAN;
+
+	n_executables_loaded ++;
+}
+
diff -Nru gxemul-0.6.2/src/file/file_macho.cc gxemul-0.7.0+dfsg/src/file/file_macho.cc
--- gxemul-0.6.2/src/file/file_macho.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_macho.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,307 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Mach-O file support
- */
-
-/*  Note: Included from file.c.  */
-
-
-/*
- *  file_load_macho():
- *
- *  Loads a Mach-O binary image into the emulated memory. The entry point
- *  is stored in the specified CPU's registers.
- *
- *  TODO:
- *
- *	o)  Almost everything.
- *
- *	o)  I haven't had time to look into whether Apple's open source
- *	    license is BSD-compatible or not. Perhaps it would be possible
- *	    to use a header file containing symbolic names, and not use
- *	    hardcoded values.
- */
-static void file_load_macho(struct machine *m, struct memory *mem,
-	char *filename, uint64_t *entrypointp, int arch, int *byte_orderp,
-	int is_64bit, int is_reversed)
-{
-	FILE *f;
-	uint64_t entry = 0;
-	int entry_set = 0;
-	int encoding = ELFDATA2MSB;
-	unsigned char buf[65536];
-	char *symbols, *strings;
-	uint32_t cputype, cpusubtype, filetype, ncmds, sizeofcmds, flags;
-	uint64_t vmaddr, vmsize, fileoff, filesize;
-	int cmd_type, cmd_len, i, flavor;
-	int32_t symoff, nsyms, stroff, strsize;
-	size_t len, pos;
-
-	if (m->cpus[0]->byte_order == EMUL_BIG_ENDIAN)
-		encoding = ELFDATA2MSB;
-
-	f = fopen(filename, "r");
-	if (f == NULL) {
-		perror(filename);
-		exit(1);
-	}
-
-	if (is_64bit) {
-		fatal("TODO: 64-bit Mach-O. Not supported yet.\n");
-		exit(1);
-	}
-	if (is_reversed) {
-		fatal("TODO: Reversed-endianness. Not supported yet.\n");
-		exit(1);
-	}
-
-	len = fread(buf, 1, sizeof(buf), f);
-	if (len < 100) {
-		fatal("Bad Mach-O file?\n");
-		exit(1);
-	}
-
-	unencode(cputype,    &buf[4], uint32_t);
-	unencode(cpusubtype, &buf[8], uint32_t);
-	unencode(filetype,   &buf[12], uint32_t);
-	unencode(ncmds,      &buf[16], uint32_t);
-	unencode(sizeofcmds, &buf[20], uint32_t);
-	unencode(flags,      &buf[24], uint32_t);
-
-	/*  debug("cputype=0x%x cpusubtype=0x%x filetype=0x%x\n",
-	    cputype, cpusubtype, filetype);
-	    debug("ncmds=%i sizeofcmds=0x%08x flags=0x%08x\n",
-	    ncmds, sizeofcmds, flags);  */
-
-	/*
-	 *  Compare to "normal" values.
-	 *  NOTE/TODO: These were for a Darwin (Macintosh PPC) kernel.
-	 */
-	if (cputype != 0x12) {
-		fatal("Error: Unimplemented cputype 0x%x\n", cputype);
-		exit(1);
-	}
-	if (cpusubtype != 0) {
-		fatal("Error: Unimplemented cpusubtype 0x%x\n", cpusubtype);
-		exit(1);
-	}
-	/*  Filetype 2 means an executable image.  */
-	if (filetype != 2) {
-		fatal("Error: Unimplemented filetype 0x%x\n", filetype);
-		exit(1);
-	}
-	if (!(flags & 1)) {
-		fatal("Error: File has 'undefined references'. Cannot"
-		    " be executed.\n", flags);
-		exit(1);
-	}
-
-	/*  I've only encountered flags == 1 so far.  */
-	if (flags != 1) {
-		fatal("Error: Unimplemented flags 0x%x\n", flags);
-		exit(1);
-	}
-
-	/*
-	 *  Read all load commands:
-	 */
-	pos = is_64bit? 32 : 28;
-	cmd_type = 0;
-	do {
-		/*  Read command type and length:  */
-		unencode(cmd_type, &buf[pos], uint32_t);
-		unencode(cmd_len,  &buf[pos+4], uint32_t);
-
-#if 0
-		debug("cmd %i, len=%i\n", cmd_type, cmd_len);
-		for (i=8; i<cmd_len; i++) {
-			unsigned char ch = buf[pos+i];
-			if (ch >= ' ' && ch < 127)
-				debug("%c", ch);
-			else
-				debug(".");
-		}
-#endif
-		switch (cmd_type) {
-		case 1:	/*  LC_SEGMENT  */
-			debug("seg ");
-			for (i=0; i<16; i++) {
-				if (buf[pos + 8 + i] == 0)
-					break;
-				debug("%c", buf[pos + 8 + i]);
-			}
-			unencode(vmaddr,   &buf[pos+8+16+0], uint32_t);
-			unencode(vmsize,   &buf[pos+8+16+4], uint32_t);
-			unencode(fileoff,  &buf[pos+8+16+8], uint32_t);
-			unencode(filesize, &buf[pos+8+16+12], uint32_t);
-			debug(": vmaddr=0x%x size=0x%x fileoff=0x%x",
-			    (int)vmaddr, (int)vmsize, (int)fileoff);
-
-			if (filesize == 0) {
-				debug("\n");
-				break;
-			}
-
-			fseek(f, fileoff, SEEK_SET);
-
-			/*  Load data from the file:  */
-			while (filesize != 0) {
-				unsigned char buf2[32768];
-				ssize_t lenRead = filesize > sizeof(buf2) ?
-				    sizeof(buf2) : filesize;
-				lenRead = fread(buf2, 1, lenRead, f);
-
-				/*  printf("fread len=%i vmaddr=%x buf[0..]="
-				    "%02x %02x %02x\n", (int)len, (int)vmaddr,
-				    buf2[0], buf2[1], buf2[2]);  */
-
-				if (lenRead > 0) {
-					int len2 = 0;
-					uint64_t vaddr1 = vmaddr &
-					    ((1 << BITS_PER_MEMBLOCK) - 1);
-					uint64_t vaddr2 = (vmaddr +
-					    lenRead) & ((1 << BITS_PER_MEMBLOCK)-1);
-					if (vaddr2 < vaddr1) {
-						len2 = lenRead - vaddr2;
-						m->cpus[0]->memory_rw(m->cpus[
-						    0], mem, vmaddr, &buf2[0],
-						    len2, MEM_WRITE,
-						    NO_EXCEPTIONS);
-					}
-					m->cpus[0]->memory_rw(m->cpus[0], mem,
-					    vmaddr + len2, &buf2[len2], lenRead-len2,
-					    MEM_WRITE, NO_EXCEPTIONS);
-				} else {
-					fprintf(stderr, "error reading\n");
-					exit(1);
-				}
-
-				vmaddr += lenRead;
-				filesize -= lenRead;
-			}
-
-			debug("\n");
-			break;
-
-		case 2:	/*  LC_SYMTAB  */
-			unencode(symoff,  &buf[pos+8], uint32_t);
-			unencode(nsyms,   &buf[pos+12], uint32_t);
-			unencode(stroff,  &buf[pos+16], uint32_t);
-			unencode(strsize, &buf[pos+20], uint32_t);
-			debug("symtable: %i symbols @ 0x%x (strings at "
-			    "0x%x)\n", nsyms, symoff, stroff);
-
-			CHECK_ALLOCATION(symbols = (char *) malloc(12 * nsyms));
-			fseek(f, symoff, SEEK_SET);
-			if (fread(symbols, 1, 12 * nsyms, f) != (size_t) 12*nsyms) {
-				fprintf(stderr, "could not read symbols from %s\n", filename);
-				exit(1);
-			}
-
-			CHECK_ALLOCATION(strings = (char *) malloc(strsize));
-			fseek(f, stroff, SEEK_SET);
-			if (fread(strings, 1, strsize, f) != (size_t) strsize) {
-				fprintf(stderr, "could not read symbol strings from %s\n", filename);
-				exit(1);
-			}
-
-			for (i=0; i<nsyms; i++) {
-				int n_strx, n_type, n_sect, n_desc;
-				uint32_t n_value;
-				unencode(n_strx,  &symbols[i*12+0], int32_t);
-				unencode(n_type,  &symbols[i*12+4], uint8_t);
-				unencode(n_sect,  &symbols[i*12+5], uint8_t);
-				unencode(n_desc,  &symbols[i*12+6], int16_t);
-				unencode(n_value, &symbols[i*12+8], uint32_t);
-				/*  debug("%i: strx=%i type=%i sect=%i desc=%i"
-				    " value=0x%x\n", i, n_strx, n_type,
-				    n_sect, n_desc, n_value);  */
-				add_symbol_name(&m->symbol_context,
-				    n_value, 0, strings + n_strx, 0, -1);
-			}
-
-			free(symbols);
-			free(strings);
-			break;
-
-		case 5:	debug("unix thread context: ");
-			/*  See http://cvs.sf.net/viewcvs.py/hte/
-			    HT%20Editor/machostruc.h or similar for details
-			    on the thread struct.  */
-			unencode(flavor, &buf[pos+8], uint32_t);
-			if (flavor != 1) {
-				fatal("unimplemented flavor %i\n", flavor);
-				exit(1);
-			}
-
-			if (arch != ARCH_PPC) {
-				fatal("non-PPC arch? TODO\n");
-				exit(1);
-			}
-
-			unencode(entry, &buf[pos+16], uint32_t);
-			entry_set = 1;
-			debug("pc=0x%x\n", (int)entry);
-
-			for (i=1; i<40; i++) {
-				uint32_t x;
-				unencode(x, &buf[pos+16+i*4], uint32_t);
-				if (x != 0) {
-					fatal("Entry nr %i in the Mach-O"
-					    " thread struct is non-zero"
-					    " (0x%x). This is not supported"
-					    " yet. TODO\n", i, x);
-					exit(1);
-				}
-			}
-			break;
-
-		default:fatal("WARNING! Unimplemented load command %i!\n",
-			    cmd_type);
-		}
-
-		pos += cmd_len;
-	} while (pos < sizeofcmds && cmd_type != 0);
-
-	fclose(f);
-
-	if (!entry_set) {
-		fatal("No entry point? Aborting.\n");
-		exit(1);
-	}
-
-	*entrypointp = entry;
-
-	if (encoding == ELFDATA2LSB)
-		*byte_orderp = EMUL_LITTLE_ENDIAN;
-	else
-		*byte_orderp = EMUL_BIG_ENDIAN;
-
-	n_executables_loaded ++;
-}
-
diff -Nru gxemul-0.6.2/src/file/file_raw.c gxemul-0.7.0+dfsg/src/file/file_raw.c
--- gxemul-0.6.2/src/file/file_raw.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_raw.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,129 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Raw file support
+ *
+ *  (Simply loads raw data into emulated memory space).
+ */
+
+/*  Note: Included from file.c.  */
+
+
+/*
+ *  file_load_raw():
+ *
+ *  Loads a raw binary into emulated memory. The filename should be
+ *  of the following form:     loadaddress:filename
+ *  or    loadaddress:skiplen:filename
+ *  or    loadaddress:skiplen:pc:filename
+ */
+static void file_load_raw(struct machine *m, struct memory *mem,
+	char *filename, uint64_t *entrypointp)
+{
+	FILE *f;
+	int len, sign3264;
+	unsigned char buf[16384];
+	uint64_t entry, loadaddr, vaddr, skip = 0;
+	char *p, *p2;
+
+	/*  Special case for 32-bit MIPS:  */
+	sign3264 = 0;
+	if (m->cpus[0]->cpu_family->arch == ARCH_MIPS && m->cpus[0]->is_32bit)
+		sign3264 = 1;
+
+	p = strchr(filename, ':');
+	if (p == NULL) {
+		fprintf(stderr, "\n");
+		perror(filename);
+		exit(1);
+	}
+
+	loadaddr = vaddr = entry = strtoull(filename, NULL, 0);
+	p2 = p+1;
+
+	/*  A second value? That's the optional skip value  */
+	p = strchr(p2, ':');
+	if (p != NULL) {
+		skip = strtoull(p2, NULL, 0);
+		p = p+1;
+		/*  A third value? That's the initial pc:  */
+		if (strchr(p, ':') != NULL) {
+			entry = strtoull(p, NULL, 0);
+			p = strchr(p, ':') + 1;
+		}
+	} else
+		p = p2;
+
+	if (sign3264) {
+		loadaddr = (int64_t)(int32_t)loadaddr;
+		entry = (int64_t)(int32_t)entry;
+		vaddr = (int64_t)(int32_t)vaddr;
+		skip = (int64_t)(int32_t)skip;
+	}
+
+	f = fopen(strrchr(filename, ':')+1, "r");
+	if (f == NULL) {
+		perror(p);
+		exit(1);
+	}
+
+	fseek(f, skip, SEEK_SET);
+
+	/*  Load file contents:  */
+	while (!feof(f)) {
+		size_t to_read = sizeof(buf);
+
+		/*  If vaddr isn't buf-size aligned, then start with a
+		    smaller buffer:  */
+		if (vaddr & (sizeof(buf) - 1))
+			to_read = sizeof(buf) - (vaddr & (sizeof(buf)-1));
+
+		len = fread(buf, 1, to_read, f);
+
+		if (len > 0)
+			m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr, &buf[0],
+			    len, MEM_WRITE, NO_EXCEPTIONS);
+
+		vaddr += len;
+	}
+
+	debug("RAW: 0x%" PRIx64" bytes @ 0x%08" PRIx64,
+	    (uint64_t) (ftello(f) - skip), (uint64_t) loadaddr);
+
+	if (skip != 0)
+		debug(" (0x%" PRIx64" bytes of header skipped)",
+		    (uint64_t) skip);
+
+	debug("\n");
+
+	fclose(f);
+
+	*entrypointp = entry;
+
+	n_executables_loaded ++;
+}
+
diff -Nru gxemul-0.6.2/src/file/file_raw.cc gxemul-0.7.0+dfsg/src/file/file_raw.cc
--- gxemul-0.6.2/src/file/file_raw.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_raw.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,129 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Raw file support
- *
- *  (Simply loads raw data into emulated memory space).
- */
-
-/*  Note: Included from file.c.  */
-
-
-/*
- *  file_load_raw():
- *
- *  Loads a raw binary into emulated memory. The filename should be
- *  of the following form:     loadaddress:filename
- *  or    loadaddress:skiplen:filename
- *  or    loadaddress:skiplen:pc:filename
- */
-static void file_load_raw(struct machine *m, struct memory *mem,
-	char *filename, uint64_t *entrypointp)
-{
-	FILE *f;
-	int len, sign3264;
-	unsigned char buf[16384];
-	uint64_t entry, loadaddr, vaddr, skip = 0;
-	char *p, *p2;
-
-	/*  Special case for 32-bit MIPS:  */
-	sign3264 = 0;
-	if (m->arch == ARCH_MIPS && m->cpus[0]->is_32bit)
-		sign3264 = 1;
-
-	p = strchr(filename, ':');
-	if (p == NULL) {
-		fprintf(stderr, "\n");
-		perror(filename);
-		exit(1);
-	}
-
-	loadaddr = vaddr = entry = strtoull(filename, NULL, 0);
-	p2 = p+1;
-
-	/*  A second value? That's the optional skip value  */
-	p = strchr(p2, ':');
-	if (p != NULL) {
-		skip = strtoull(p2, NULL, 0);
-		p = p+1;
-		/*  A third value? That's the initial pc:  */
-		if (strchr(p, ':') != NULL) {
-			entry = strtoull(p, NULL, 0);
-			p = strchr(p, ':') + 1;
-		}
-	} else
-		p = p2;
-
-	if (sign3264) {
-		loadaddr = (int64_t)(int32_t)loadaddr;
-		entry = (int64_t)(int32_t)entry;
-		vaddr = (int64_t)(int32_t)vaddr;
-		skip = (int64_t)(int32_t)skip;
-	}
-
-	f = fopen(strrchr(filename, ':')+1, "r");
-	if (f == NULL) {
-		perror(p);
-		exit(1);
-	}
-
-	fseek(f, skip, SEEK_SET);
-
-	/*  Load file contents:  */
-	while (!feof(f)) {
-		size_t to_read = sizeof(buf);
-
-		/*  If vaddr isn't buf-size aligned, then start with a
-		    smaller buffer:  */
-		if (vaddr & (sizeof(buf) - 1))
-			to_read = sizeof(buf) - (vaddr & (sizeof(buf)-1));
-
-		len = fread(buf, 1, to_read, f);
-
-		if (len > 0)
-			m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr, &buf[0],
-			    len, MEM_WRITE, NO_EXCEPTIONS);
-
-		vaddr += len;
-	}
-
-	debug("RAW: 0x%" PRIx64" bytes @ 0x%08" PRIx64,
-	    (uint64_t) (ftello(f) - skip), (uint64_t) loadaddr);
-
-	if (skip != 0)
-		debug(" (0x%" PRIx64" bytes of header skipped)",
-		    (uint64_t) skip);
-
-	debug("\n");
-
-	fclose(f);
-
-	*entrypointp = entry;
-
-	n_executables_loaded ++;
-}
-
diff -Nru gxemul-0.6.2/src/file/file_srec.c gxemul-0.7.0+dfsg/src/file/file_srec.c
--- gxemul-0.6.2/src/file/file_srec.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_srec.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,185 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: SREC file support
+ */
+
+/*  Note: Included from file.c.  */
+
+
+/*
+ *  file_load_srec():
+ *
+ *  Loads a Motorola SREC file into emulated memory. Description of the SREC
+ *  file format can be found at here:
+ *
+ *      http://www.ndsu.nodak.edu/instruct/tareski/373f98/notes/srecord.htm
+ *  or  http://www.amelek.gda.pl/avr/uisp/srecord.htm
+ */
+static void file_load_srec(struct machine *m, struct memory *mem,
+	char *filename, uint64_t *entrypointp)
+{
+	FILE *f;
+	unsigned char buf[516];
+	unsigned char bytes[270];
+	uint64_t entry = 0, vaddr = 0;
+	int i, j, count;
+	char ch;
+	int buf_len, data_start = 0;
+	int entry_set = 0;
+	int warning = 0;
+	int warning_len = 0;
+	int total_bytes_loaded = 0;
+
+	f = fopen(filename, "r");
+	if (f == NULL) {
+		perror(filename);
+		exit(1);
+	}
+
+	/*  Load file contents:  */
+	while (!feof(f)) {
+		memset(buf, 0, sizeof(buf));
+		if (fgets((char *)buf, sizeof(buf)-1, f) == NULL ||
+		    buf[0] == 0 || buf[0]=='\r' || buf[0]=='\n')
+			continue;
+
+		if (buf[0] != 'S') {
+			if (!warning)
+				debug("WARNING! non-S-record found\n");
+			warning = 1;
+			continue;
+		}
+
+		buf_len = strlen((char *)buf);
+
+		if (buf_len < 10) {
+			if (!warning_len)
+				debug("WARNING! invalid S-record found\n");
+			warning_len = 1;
+			continue;
+		}
+
+		/*
+		 *  Stype count address data checksum
+		 *  01    23    4..     ..   (last 2 bytes)
+		 *
+		 *  TODO: actually check the checksum
+		 */
+
+		j = 0;
+		for (i=1; i<buf_len; i++) {
+			if (buf[i]>='a' && buf[i]<='f')
+				buf[i] += 10 - 'a';
+			else if (buf[i] >= 'A' && buf[i] <= 'F')
+				buf[i] += 10 - 'A';
+			else if (buf[i] >= '0' && buf[i] <= '9')
+				buf[i] -= '0';
+			else if (buf[i] == '\r' || buf[i] == '\n') {
+			} else
+				fatal("invalid characters '%c' in S-record\n",
+				    buf[i]);
+
+			if (i >= 4) {
+				if (i & 1)
+					bytes[j++] += buf[i];
+				else
+					bytes[j] = buf[i] * 16;
+			}
+		}
+
+		count = buf[2] * 16 + buf[3];
+		/*  debug("count=%i j=%i\n", count, j);  */
+		/*  count is j - 1.  */
+
+		switch (buf[1]) {
+		case 0:
+			debug("SREC \"");
+			for (i=2; i<count-1; i++) {
+				ch = bytes[i];
+				if (ch >= ' ' && ch < 127)
+					debug("%c", ch);
+				else
+					debug("?");
+			}
+			debug("\"\n");
+			break;
+		case 1:
+		case 2:
+		case 3:
+			/*  switch again, to get the load address:  */
+			switch (buf[1]) {
+			case 1:	data_start = 2;
+				vaddr = (bytes[0] << 8) + bytes[1];
+				break;
+			case 2:	data_start = 3;
+				vaddr = (bytes[0] << 16) + (bytes[1] << 8) +
+				    bytes[2];
+				break;
+			case 3:	data_start = 4;
+				vaddr = ((uint64_t)bytes[0] << 24) +
+				    (bytes[1] << 16) + (bytes[2]<<8) + bytes[3];
+			}
+			m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
+			    &bytes[data_start], count - 1 - data_start,
+			    MEM_WRITE, NO_EXCEPTIONS);
+			total_bytes_loaded += count - 1 - data_start;
+			break;
+		case 7:
+		case 8:
+		case 9:
+			/*  switch again, to get the entry point:  */
+			switch (buf[1]) {
+			case 7:	entry = ((uint64_t)bytes[0] << 24) +
+				    (bytes[1] << 16) + (bytes[2]<<8) + bytes[3];
+				break;
+			case 8:	entry = (bytes[0] << 16) + (bytes[1] << 8) +
+				    bytes[2];
+				break;
+			case 9:	entry = (bytes[0] << 8) + bytes[1];
+				break;
+			}
+			entry_set = 1;
+			debug("entry point 0x%08x\n", (unsigned int)entry);
+			break;
+		default:
+			debug("unimplemented S-record type %i\n", buf[1]);
+		}
+	}
+
+	debug("0x%x bytes loaded\n", total_bytes_loaded);
+
+	fclose(f);
+
+	if (!entry_set)
+		debug("WARNING! no entrypoint found!\n");
+	else
+		*entrypointp = entry;
+
+	n_executables_loaded ++;
+}
+
diff -Nru gxemul-0.6.2/src/file/file_srec.cc gxemul-0.7.0+dfsg/src/file/file_srec.cc
--- gxemul-0.6.2/src/file/file_srec.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/file_srec.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,185 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: SREC file support
- */
-
-/*  Note: Included from file.c.  */
-
-
-/*
- *  file_load_srec():
- *
- *  Loads a Motorola SREC file into emulated memory. Description of the SREC
- *  file format can be found at here:
- *
- *      http://www.ndsu.nodak.edu/instruct/tareski/373f98/notes/srecord.htm
- *  or  http://www.amelek.gda.pl/avr/uisp/srecord.htm
- */
-static void file_load_srec(struct machine *m, struct memory *mem,
-	char *filename, uint64_t *entrypointp)
-{
-	FILE *f;
-	unsigned char buf[516];
-	unsigned char bytes[270];
-	uint64_t entry = 0, vaddr = 0;
-	int i, j, count;
-	char ch;
-	int buf_len, data_start = 0;
-	int entry_set = 0;
-	int warning = 0;
-	int warning_len = 0;
-	int total_bytes_loaded = 0;
-
-	f = fopen(filename, "r");
-	if (f == NULL) {
-		perror(filename);
-		exit(1);
-	}
-
-	/*  Load file contents:  */
-	while (!feof(f)) {
-		memset(buf, 0, sizeof(buf));
-		if (fgets((char *)buf, sizeof(buf)-1, f) == NULL ||
-		    buf[0] == 0 || buf[0]=='\r' || buf[0]=='\n')
-			continue;
-
-		if (buf[0] != 'S') {
-			if (!warning)
-				debug("WARNING! non-S-record found\n");
-			warning = 1;
-			continue;
-		}
-
-		buf_len = strlen((char *)buf);
-
-		if (buf_len < 10) {
-			if (!warning_len)
-				debug("WARNING! invalid S-record found\n");
-			warning_len = 1;
-			continue;
-		}
-
-		/*
-		 *  Stype count address data checksum
-		 *  01    23    4..     ..   (last 2 bytes)
-		 *
-		 *  TODO: actually check the checksum
-		 */
-
-		j = 0;
-		for (i=1; i<buf_len; i++) {
-			if (buf[i]>='a' && buf[i]<='f')
-				buf[i] += 10 - 'a';
-			else if (buf[i] >= 'A' && buf[i] <= 'F')
-				buf[i] += 10 - 'A';
-			else if (buf[i] >= '0' && buf[i] <= '9')
-				buf[i] -= '0';
-			else if (buf[i] == '\r' || buf[i] == '\n') {
-			} else
-				fatal("invalid characters '%c' in S-record\n",
-				    buf[i]);
-
-			if (i >= 4) {
-				if (i & 1)
-					bytes[j++] += buf[i];
-				else
-					bytes[j] = buf[i] * 16;
-			}
-		}
-
-		count = buf[2] * 16 + buf[3];
-		/*  debug("count=%i j=%i\n", count, j);  */
-		/*  count is j - 1.  */
-
-		switch (buf[1]) {
-		case 0:
-			debug("SREC \"");
-			for (i=2; i<count-1; i++) {
-				ch = bytes[i];
-				if (ch >= ' ' && ch < 127)
-					debug("%c", ch);
-				else
-					debug("?");
-			}
-			debug("\"\n");
-			break;
-		case 1:
-		case 2:
-		case 3:
-			/*  switch again, to get the load address:  */
-			switch (buf[1]) {
-			case 1:	data_start = 2;
-				vaddr = (bytes[0] << 8) + bytes[1];
-				break;
-			case 2:	data_start = 3;
-				vaddr = (bytes[0] << 16) + (bytes[1] << 8) +
-				    bytes[2];
-				break;
-			case 3:	data_start = 4;
-				vaddr = ((uint64_t)bytes[0] << 24) +
-				    (bytes[1] << 16) + (bytes[2]<<8) + bytes[3];
-			}
-			m->cpus[0]->memory_rw(m->cpus[0], mem, vaddr,
-			    &bytes[data_start], count - 1 - data_start,
-			    MEM_WRITE, NO_EXCEPTIONS);
-			total_bytes_loaded += count - 1 - data_start;
-			break;
-		case 7:
-		case 8:
-		case 9:
-			/*  switch again, to get the entry point:  */
-			switch (buf[1]) {
-			case 7:	entry = ((uint64_t)bytes[0] << 24) +
-				    (bytes[1] << 16) + (bytes[2]<<8) + bytes[3];
-				break;
-			case 8:	entry = (bytes[0] << 16) + (bytes[1] << 8) +
-				    bytes[2];
-				break;
-			case 9:	entry = (bytes[0] << 8) + bytes[1];
-				break;
-			}
-			entry_set = 1;
-			debug("entry point 0x%08x\n", (unsigned int)entry);
-			break;
-		default:
-			debug("unimplemented S-record type %i\n", buf[1]);
-		}
-	}
-
-	debug("0x%x bytes loaded\n", total_bytes_loaded);
-
-	fclose(f);
-
-	if (!entry_set)
-		debug("WARNING! no entrypoint found!\n");
-	else
-		*entrypointp = entry;
-
-	n_executables_loaded ++;
-}
-
diff -Nru gxemul-0.6.2/src/file/.index gxemul-0.7.0+dfsg/src/file/.index
--- gxemul-0.6.2/src/file/.index	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/.index	2021-11-27 09:42:23.000000000 +0000
@@ -1,7 +1,7 @@
-file_android.cc  Android boot.img file support
-file_aout.cc  a.out executable file support
-file_ecoff.cc  ECOFF file support
-file_elf.cc  ELF file support
-file_macho.cc  Mach-O file support
-file_raw.cc  Raw file support
-file_srec.cc  SREC file support
+file_android.c  Android boot.img file support
+file_aout.c  a.out executable file support
+file_ecoff.c  ECOFF file support
+file_elf.c  ELF file support
+file_macho.c  Mach-O file support
+file_raw.c  Raw file support
+file_srec.c  SREC file support
diff -Nru gxemul-0.6.2/src/file/Makefile.skel gxemul-0.7.0+dfsg/src/file/Makefile.skel
--- gxemul-0.6.2/src/file/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/file/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #  Makefile for GXemul src/file
 #
 
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(DINCLUDE)
+CFLAGS=$(CWARNINGS) $(COPTIM) $(DINCLUDE)
 
 OBJS=file.o
 
@@ -11,8 +11,8 @@
 
 $(OBJS): Makefile
 
-file.o: file.cc file_android.cc file_aout.cc file_ecoff.cc file_elf.cc \
-	file_macho.cc file_raw.cc file_srec.cc
+file.o: file.c file_android.c file_aout.c file_ecoff.c file_elf.c \
+	file_macho.c file_raw.c file_srec.c
 
 
 clean:
diff -Nru gxemul-0.6.2/src/include/AddressDataBus.h gxemul-0.7.0+dfsg/src/include/AddressDataBus.h
--- gxemul-0.6.2/src/include/AddressDataBus.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/AddressDataBus.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,145 +0,0 @@
-#ifndef ADDRESSDATABUS_H
-#define	ADDRESSDATABUS_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-
-/**
- * \brief An interface for implementing components that read/write data via an
- *	address bus.
- *
- * Any component which allows data to be read or written by using an address
- * as an index/offset should implement this interface.
- *
- * A typical example of a Component which implements the functions
- * of this class is the RAMComponent.
- */
-class AddressDataBus
-{
-public:
-	/**
-	 * \brief Constructs an AddressDataBus instance.
-	 */
-	AddressDataBus() { }
-
-	virtual ~AddressDataBus() { }
-
-	/**
-	 * \brief Place an address on the bus.
-	 *
-	 * \param address The address to select.
-	 */
-	virtual void AddressSelect(uint64_t address) = 0;
-
-	/**
-	 * \brief Reads 8-bit data from the currently selected address.
-	 *
-	 * \param data A reference to a variable which will receive the data.
-	 * \param endianness Selects the endianness of the operation. Ignored
-	 *	for 8-bit reads and writes.
-	 * \return True if the access was successful, false otherwise (e.g.
-	 *	because of a timeout).
-	 */
-	virtual bool ReadData(uint8_t& data, Endianness endianness = BigEndian) = 0;
-
-	/**
-	 * \brief Reads 16-bit data from the currently selected address.
-	 *
-	 * \param data A reference to a variable which will receive the data.
-	 * \param endianness Selects the endianness of the operation.
-	 * \return True if the access was successful, false otherwise (e.g.
-	 *	because of a timeout).
-	 */
-	virtual bool ReadData(uint16_t& data, Endianness endianness) = 0;
-
-	/**
-	 * \brief Reads 32-bit data from the currently selected address.
-	 *
-	 * \param data A reference to a variable which will receive the data.
-	 * \param endianness Selects the endianness of the operation.
-	 * \return True if the access was successful, false otherwise (e.g.
-	 *	because of a timeout).
-	 */
-	virtual bool ReadData(uint32_t& data, Endianness endianness) = 0;
-
-	/**
-	 * \brief Reads 64-bit data from the currently selected address.
-	 *
-	 * \param data A reference to a variable which will receive the data.
-	 * \param endianness Selects the endianness of the operation.
-	 * \return True if the access was successful, false otherwise (e.g.
-	 *	because of a timeout).
-	 */
-	virtual bool ReadData(uint64_t& data, Endianness endianness) = 0;
-
-	/**
-	 * \brief Writes 8-bit data to the currently selected address.
-	 *
-	 * \param data A reference to a variable which contains the data.
-	 * \param endianness Selects the endianness of the operation. Ignored
-	 *	for 8-bit reads and writes.
-	 * \return True if the access was successful, false otherwise (e.g.
-	 *	because of a timeout).
-	 */
-	virtual bool WriteData(const uint8_t& data, Endianness endianness = BigEndian) = 0;
-
-	/**
-	 * \brief Writes 16-bit data to the currently selected address.
-	 *
-	 * \param data A reference to a variable which contains the data.
-	 * \param endianness Selects the endianness of the operation.
-	 * \return True if the access was successful, false otherwise (e.g.
-	 *	because of a timeout).
-	 */
-	virtual bool WriteData(const uint16_t& data, Endianness endianness) = 0;
-
-	/**
-	 * \brief Writes 32-bit data to the currently selected address.
-	 *
-	 * \param data A reference to a variable which contains the data.
-	 * \param endianness Selects the endianness of the operation.
-	 * \return True if the access was successful, false otherwise (e.g.
-	 *	because of a timeout).
-	 */
-	virtual bool WriteData(const uint32_t& data, Endianness endianness) = 0;
-
-	/**
-	 * \brief Writes 64-bit data to the currently selected address.
-	 *
-	 * \param data A reference to a variable which contains the data.
-	 * \param endianness Selects the endianness of the operation.
-	 * \return True if the access was successful, false otherwise (e.g.
-	 *	because of a timeout).
-	 */
-	virtual bool WriteData(const uint64_t& data, Endianness endianness) = 0;
-};
-
-
-#endif	// ADDRESSDATABUS_H
diff -Nru gxemul-0.6.2/src/include/Checksum.h gxemul-0.7.0+dfsg/src/include/Checksum.h
--- gxemul-0.6.2/src/include/Checksum.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/Checksum.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,103 +0,0 @@
-#ifndef CHECKSUM_H
-#define	CHECKSUM_H
-
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "UnitTest.h"
-
-
-/**
- * \brief A checksum accumulator.
- *
- * The main purpose of this class is as a helper in unit tests, where
- * objects such as trees are hard to compare to each other. A checksum
- * of the first tree can then be compared with a checksum of the second
- * tree.
- *
- * Note: This is not scientifically correct in any way. It is just something
- * I made up, for unit testing purposes. (2007-12-27)
- */
-class Checksum
-	: public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs a zeroed checksum.
-	 */
-	Checksum();
-
-	/**
-	 * \brief Retrieves the value of the checksum, as a uint64_t.
-	 *
-	 * @return the checksum value
-	 */
-	uint64_t Value() const;
-
-	/**
-	 * \brief Add a uint64_t to the checksum.
-	 *
-	 * @param x Value to add.
-	 */
-	void Add(uint64_t x);
-
-	/**
-	 * \brief Add a string to the checksum.
-	 *
-	 * @param str The string to add.
-	 */
-	void Add(const string& str);
-
-	/**
-	 * \brief Compares one %Checksum to another for equality.
-	 *
-	 * @param other  The %Checksum to compare to.
-	 * @return true if the checksums match, false otherwise.
-	 */
-	bool operator == (const Checksum& other) const;
-
-	/**
-	 * \brief Compares one %Checksum to another for inequality.
-	 *
-	 * @param other  The %Checksum to compare to.
-	 * @return false if the checksums match, true otherwise.
-	 */
-	bool operator != (const Checksum& other) const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-private:
-	uint64_t	m_value;
-};
-
-
-#endif	// CHECKSUM_H
diff -Nru gxemul-0.6.2/src/include/Command.h gxemul-0.7.0+dfsg/src/include/Command.h
--- gxemul-0.6.2/src/include/Command.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/Command.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,138 +0,0 @@
-#ifndef COMMAND_H
-#define	COMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "UnitTest.h"
-
-class GXemul;
-
-
-/**
- * \brief A %Command is a named function, executed by the CommandInterpreter.
- *
- * To implement a new %Command, simply create the corresponding .h file
- * in src/include/commands/ and a .cc file in src/main/commands/ (e.g. by
- * copying from a similar command), and add the name of the command's .o
- * file to src/main/commands/Makefile.skel. (The configure script takes care
- * of adding all commands to the CommandInterpreter, so there is no need
- * to manually "register" the command anywhere.)
- */
-class Command
-	: public ReferenceCountable
-	, public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs a %Command.
-	 *
-	 * @param name The command's name. This should be a unique lower-case
-	 *	string, consisting only of letters a-z.
-	 * @param argumentFormat A string describing the command's arguments.
-	 *	May be empty, if the command takes no arguments.
-	 */
-	Command(const string& name, const string& argumentFormat);
-
-	virtual ~Command() = 0;
-
-	/**
-	 * \brief Gets the name of the command.
-	 *
-	 * @return The name of the command.
-	 */
-	const string& GetCommandName() const
-	{
-		return m_name;
-	}
-
-	/**
-	 * \brief Gets the argument format for the command.
-	 *
-	 * @return The argument format for the command.
-	 */
-	const string& GetArgumentFormat() const
-	{
-		return m_argumentFormat;
-	}
-
-	/**
-	 * \brief Executes the command on a given GXemul instance.
-	 *
-	 * @param gxemul A reference to the GXemul instance.
-	 * @param arguments A vector of zero or more string arguments.
-	 * @return true if the command succeeded, false if it failed.
-	 */
-	virtual bool Execute(GXemul& gxemul,
-		const vector<string>& arguments) = 0;
-
-	/**
-	 * \brief Returns whether the command can be quickly re-executed using
-	 * an empty command line.
-	 *
-	 * Typical examples are: step, cpu disassembly, and memory dump,
-	 * where re-executing the command without arguments is very natural.
-	 *
-	 * @return true if the command may be re-executed without arguments,
-	 * false otherwise.
-	 */
-	virtual bool MayBeReexecutedWithoutArgs() const
-	{
-		return false;
-	}
-
-	/**
-	 * \brief Returns a short (one-line) description of the command.
-	 *
-	 * @return A short description of the command.
-	 */
-	virtual string GetShortDescription() const = 0;
-
-	/**
-	 * \brief Returns a long description/help message for the command.
-	 *
-	 * @return A long description/help message for the command.
-	 */
-	virtual string GetLongDescription() const = 0;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-private:
-	string		m_name;
-	string		m_argumentFormat;
-};
-
-
-typedef map< string,refcount_ptr<Command> > Commands;
-
-
-#endif	// COMMAND_H
diff -Nru gxemul-0.6.2/src/include/CommandInterpreter.h gxemul-0.7.0+dfsg/src/include/CommandInterpreter.h
--- gxemul-0.6.2/src/include/CommandInterpreter.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/CommandInterpreter.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,264 +0,0 @@
-#ifndef COMMANDINTERPRETER_H
-#define	COMMANDINTERPRETER_H
-
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-class GXemul;
-
-
-/**
- * \brief An interactive command interpreter, which run Commands.
- *
- * A command interpreter can execute commands in the form of complete strings,
- * or it can be given one character (keypress) at a time to build up a command.
- * When given individual keypresses, the command interpreter echoes back
- * what is to be printed. It also supports TAB completion.
- */
-class CommandInterpreter
-	: public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs a %CommandInterpreter.
-	 *
-	 * @param owner the GXemul instance that owns the %CommandInterpreter
-	 */
-	CommandInterpreter(GXemul* owner);
-
-	/**
-	 * \brief Adds a character (keypress) to the current command buffer.
-	 *
-	 * Most normal keys are added at the end of the buffer. Some exceptions
-	 * are:
-	 * <ul>
-	 *	<li>nul char: does not change the input line buffer,
-	 *		but forces it to be visually redrawn/updated
-	 *	<li>backspace: removes the last character (if any)
-	 *	<li>tab: attempts TAB completion of the last word
-	 *	<li>newline or cr: calls RunCommand, and then clears
-	 *		the current buffer
-	 *	<li>escape: special handling
-	 * </ul>
-	 *
-	 * @param key the character/key to add
-	 * @return true if this was a complete command line (i.e. the key
-	 *	was a newline), false otherwise
-	 */
-	bool AddKey(stringchar key);
-
-	/**
-	 * \brief Clears the current command buffer.
-	 */
-	void ClearCurrentCommandBuffer();
-
-	/**
-	 * \brief Re-displays the current command buffer.
-	 *
-	 * Useful e.g. when running in text console mode, and the user has
-	 * pressed CTRL-Z. When returning to %GXemul, the current command
-	 * buffer can be showed again by calling this function.
-	 */
-	void ReshowCurrentCommandBuffer();
-
-	/**
-	 * \brief Runs a command, given as a string.
-	 *
-	 * The return value from the function is true if the command was run.
-	 * However, the command may run and fail, and that's what pSuccess is
-	 * for.
-	 *
-	 * @param command the command to run
-	 * @param pSuccess a pointer to a bool, which (if pSuccess is non-NULL)
-	 *	will be set to whether the command succeeded or not.
-	 * @return true if the command was run, false if the command was
-	 *	not known
-	 */
-	bool RunCommand(const string& command, bool* pSuccess = NULL);
-
-	/**
-	 * \brief Retrieves the current command buffer.
-	 *
-	 * @return a string representing the current command buffer
-	 */
-	const string& GetCurrentCommandBuffer() const;
-
-	/**
-	 * \brief Adds a new Command to the command interpreter.
-	 *
-	 * @param command A reference counter pointer to the Command.
-	 */
-	void AddCommand(refcount_ptr<Command> command);
-
-	/**
-	 * \brief Gets a collection of all commands.
-	 *
-	 * @return A const reference to the collection of commands.
-	 */
-	const Commands& GetCommands() const;
-
-	/**
-	 * \brief Adds a command line to the command history.
-	 *
-	 * If the command is empty, or the same as the last command in the
-	 * command history, it is ignored.
-	 *
-	 * The command history buffer only holds a small fixed number of
-	 * entries.
-	 *
-	 * @param command The command line to add to the command history.
-	 * @return The next insert position in the command history. Useful
-	 *	for unit testing purposes; should otherwise be ignored.
-	 */
-	int AddLineToCommandHistory(const string& command);
-
-	/**
-	 * \brief Retrieves a line from the command history.
-	 *
-	 * @param nStepsBack The number of steps back into the history. 0
-	 *	means return an empty line, 1 means the last history line,
-	 *	2 means the second last, and so on.
-	 * @return The line from the history, or an empty string if
-	 *	nStepsBack was zero.
-	 */
-	string GetHistoryLine(int nStepsBack) const;
-
-private:
-	/**
-	 * \brief Internal helper which clears a line by outputting spaces.
-	 */
-	void ClearCurrentInputLineVisually();
-
-	/**
-	 * \brief Completes the word at the current position in the input line.
-	 *
-	 * @param commandString A reference to the string to
-	 *	tab-complete.
-	 * @param cursorPosition A refernce to a size_t, which
-	 *	indicates the current cursor position within the string.
-	 * @param visibleShowAvailable True if available words should be
-	 *	echoed back via the UI.
-	 * @return True if there was a single match, false otherwise.
-	 */
-	bool TabComplete(string& commandString, size_t& cursorPosition,
-		bool visibleShowAvailable = false);
-
-	/**
-	 * \brief Tab-completes; takes optional method or state variable
-	 *	name into account.
-	 *
-	 * Strings such as "cpu." and "cpu.u" should e.g. be expanded to
-	 * "root.machine0.mainbus0.cpu." and
-	 * "root.machine0.mainbus0.cpu.unassemble", respectively.
-	 *
-	 * @param commandString A reference to the string to
-	 *	tab-complete.
-	 * @param cursorPosition A refernce to a size_t, which
-	 *	indicates the current cursor position within the string.
-	 * @param visibleShowAvailable True if available words should be
-	 *	echoed back via the UI.
-	 * @return True if there was a single match, false otherwise.
-	 */
-	bool TabCompleteWithSubname(string& commandString,
-		size_t& cursorPosition, bool visibleShowAvailable = false);
-
-	/**
-	 * \brief Runs a method on a Component.
-	 *
-	 * Note: The componentPathAndMethod argument may contain an optional
-	 * ".method" suffix. The part before the method may need to be
-	 * tab-completed.
-	 *
-	 * Some examples of componentPathAndMethod:
-	 * <ul>
-	 *	<li>cpu
-	 *	<li>cpu.u
-	 *	<li>cpu.unassemble
-	 *	<li>root.machine0.mainbus0.cpu
-	 *	<li>root.machine0.mainbus0.cpu0
-	 *	<li>root.machine0.mainbus0.cpu.u
-	 *	<li>root.machine0.mainbus0.cpu0.unassemble
-	 * </ul>
-	 *
-	 * If the method name is missing, a default method will be executed.
-	 *
-	 * @param componentPathAndMethod The path to the component, plus a
-	 *	possible ".method" suffix.
-	 * @param arguments A vector of string arguments.
-	 * @return True if a component method was executed, false otherwise.
-	 */
-	bool RunComponentMethod(const string& componentPathAndMethod,
-		const vector<string>& arguments);
-
-	/**
-	 * \brief Prints a list of available words (for tab completion).
-	 *
-	 * @param words A vector of all available words.
-	 */
-	void ShowAvailableWords(const vector<string>& words);
-
-	void VariableAssignment(const string& componentPath,
-	    const string& variableName, const string& expression);
-
-
-	/********************************************************************/
-public:
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-
-private:
-	// Pointer to the owning GXemul instance:
-	GXemul*			m_GXemul;
-
-	// A collection of all available commands that can be executed:
-	Commands		m_commands;
-
-	// The current input line:
-	string			m_currentCommandString;
-	size_t			m_currentCommandCursorPosition;
-	bool			m_inEscapeSequence;
-	string			m_escapeSequence;
-	int			m_historyEntryToCopyFrom;
-	
-	// Command history (usually accessed by cursor up/down keys):
-	vector<string>		m_commandHistory;
-	size_t			m_commandHistoryInsertPosition;
-	size_t			m_commandHistoryMaxSize;
-
-	// If non-empty, a command which may be reexecuted if an empty
-	// command line is given:
-	string			m_mayBeReexecuted;
-};
-
-
-#endif	// COMMANDINTERPRETER_H
diff -Nru gxemul-0.6.2/src/include/commands/AddComponentCommand.h gxemul-0.7.0+dfsg/src/include/commands/AddComponentCommand.h
--- gxemul-0.6.2/src/include/commands/AddComponentCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/AddComponentCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,60 +0,0 @@
-#ifndef ADDCOMPONENTCOMMAND_H
-#define	ADDCOMPONENTCOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which adds a Component to some place in a GXemul
- *	instance' component tree.
- */
-class AddComponentCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs an %AddComponentCommand.
-	 */
-	AddComponentCommand();
-
-	virtual ~AddComponentCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-};
-
-
-#endif	// ADDCOMPONENTCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/BackwardStepCommand.h gxemul-0.7.0+dfsg/src/include/commands/BackwardStepCommand.h
--- gxemul-0.6.2/src/include/commands/BackwardStepCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/BackwardStepCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,69 +0,0 @@
-#ifndef BACKWARDSTEPCOMMAND_H
-#define	BACKWARDSTEPCOMMAND_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which sets the RunState to BackwardsSingleStepping.
- */
-class BackwardStepCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %BackwardStepCommand.
-	 */
-	BackwardStepCommand();
-
-	virtual ~BackwardStepCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual bool MayBeReexecutedWithoutArgs() const
-	{
-		return true;
-	}
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// BACKWARDSTEPCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/CloseCommand.h gxemul-0.7.0+dfsg/src/include/commands/CloseCommand.h
--- gxemul-0.6.2/src/include/commands/CloseCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/CloseCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,59 +0,0 @@
-#ifndef CLOSECOMMAND_H
-#define	CLOSECOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which closes (discards) the current emulation.
- */
-class CloseCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs an %CloseCommand.
-	 */
-	CloseCommand();
-
-	virtual ~CloseCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-};
-
-
-#endif	// CLOSECOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/ContinueBackwardsCommand.h gxemul-0.7.0+dfsg/src/include/commands/ContinueBackwardsCommand.h
--- gxemul-0.6.2/src/include/commands/ContinueBackwardsCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/ContinueBackwardsCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,64 +0,0 @@
-#ifndef CONTINUEBACKWARDSCOMMAND_H
-#define	CONTINUEBACKWARDSCOMMAND_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which sets the RunState to BackwardsRunning.
- */
-class ContinueBackwardsCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %ContinueBackwardsCommand.
-	 */
-	ContinueBackwardsCommand();
-
-	virtual ~ContinueBackwardsCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// CONTINUEBACKWARDSCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/ContinueCommand.h gxemul-0.7.0+dfsg/src/include/commands/ContinueCommand.h
--- gxemul-0.6.2/src/include/commands/ContinueCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/ContinueCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,65 +0,0 @@
-#ifndef CONTINUECOMMAND_H
-#define	CONTINUECOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which continues execution, by changing the
- *	current RunState to Running.
- */
-class ContinueCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %ContinueCommand.
-	 */
-	ContinueCommand();
-
-	virtual ~ContinueCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// CONTINUECOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/CopyComponentCommand.h gxemul-0.7.0+dfsg/src/include/commands/CopyComponentCommand.h
--- gxemul-0.6.2/src/include/commands/CopyComponentCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/CopyComponentCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,65 +0,0 @@
-#ifndef COPYCOMPONENTCOMMAND_H
-#define	COPYCOMPONENTCOMMAND_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which copies (clones) a Component from one location to another in
- *	the component tree.
- */
-class CopyComponentCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %CopyComponentCommand.
-	 */
-	CopyComponentCommand();
-
-	virtual ~CopyComponentCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// COPYCOMPONENTCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/HelpCommand.h gxemul-0.7.0+dfsg/src/include/commands/HelpCommand.h
--- gxemul-0.6.2/src/include/commands/HelpCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/HelpCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,59 +0,0 @@
-#ifndef HELPCOMMAND_H
-#define	HELPCOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which prints help messages for commands.
- */
-class HelpCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %HelpCommand.
-	 */
-	HelpCommand();
-
-	virtual ~HelpCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-};
-
-
-#endif	// HELPCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/ListComponentsCommand.h gxemul-0.7.0+dfsg/src/include/commands/ListComponentsCommand.h
--- gxemul-0.6.2/src/include/commands/ListComponentsCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/ListComponentsCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,59 +0,0 @@
-#ifndef LISTCOMPONENTSCOMMAND_H
-#define	LISTCOMPONENTSCOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which lists all available components.
- */
-class ListComponentsCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %ListComponentsCommand.
-	 */
-	ListComponentsCommand();
-
-	virtual ~ListComponentsCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-};
-
-
-#endif	// LISTCOMPONENTSCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/LoadCommand.h gxemul-0.7.0+dfsg/src/include/commands/LoadCommand.h
--- gxemul-0.6.2/src/include/commands/LoadCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/LoadCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,65 +0,0 @@
-#ifndef LOADCOMMAND_H
-#define	LOADCOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "Component.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which loads a Component tree from a file in the filesystem.
- */
-class LoadCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs an %LoadCommand.
-	 */
-	LoadCommand();
-
-	virtual ~LoadCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-
-private:
-	bool IsComponentTree(GXemul& gxemul, const string& filename) const;
-	bool LoadComponentTree(GXemul& gxemul, const string&filename,
-		refcount_ptr<Component> specifiedComponent) const;
-};
-
-
-#endif	// LOADCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/MoveComponentCommand.h gxemul-0.7.0+dfsg/src/include/commands/MoveComponentCommand.h
--- gxemul-0.6.2/src/include/commands/MoveComponentCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/MoveComponentCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,65 +0,0 @@
-#ifndef MOVECOMPONENTCOMMAND_H
-#define	MOVECOMPONENTCOMMAND_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which moves a Component from one location to another in
- *	the component tree.
- */
-class MoveComponentCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %MoveComponentCommand.
-	 */
-	MoveComponentCommand();
-
-	virtual ~MoveComponentCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// MOVECOMPONENTCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/PauseCommand.h gxemul-0.7.0+dfsg/src/include/commands/PauseCommand.h
--- gxemul-0.6.2/src/include/commands/PauseCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/PauseCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,65 +0,0 @@
-#ifndef PAUSECOMMAND_H
-#define	PAUSECOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which pauses execution, by changing the
- *	current RunState to Paused.
- */
-class PauseCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %PauseCommand.
-	 */
-	PauseCommand();
-
-	virtual ~PauseCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// PAUSECOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/QuitCommand.h gxemul-0.7.0+dfsg/src/include/commands/QuitCommand.h
--- gxemul-0.6.2/src/include/commands/QuitCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/QuitCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,64 +0,0 @@
-#ifndef QUITCOMMAND_H
-#define	QUITCOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which quits the %GXemul application.
- */
-class QuitCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %QuitCommand.
-	 */
-	QuitCommand();
-
-	virtual ~QuitCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// QUITCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/RemoveComponentCommand.h gxemul-0.7.0+dfsg/src/include/commands/RemoveComponentCommand.h
--- gxemul-0.6.2/src/include/commands/RemoveComponentCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/RemoveComponentCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,60 +0,0 @@
-#ifndef REMOVECOMPONENTCOMMAND_H
-#define	REMOVECOMPONENTCOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which removes a Component from a GXemul instance'
- *	component tree.
- */
-class RemoveComponentCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %RemoveComponentCommand.
-	 */
-	RemoveComponentCommand();
-
-	virtual ~RemoveComponentCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-};
-
-
-#endif	// REMOVECOMPONENTCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/ResetCommand.h gxemul-0.7.0+dfsg/src/include/commands/ResetCommand.h
--- gxemul-0.6.2/src/include/commands/ResetCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/ResetCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,67 +0,0 @@
-#ifndef RESETCOMMAND_H
-#define	RESETCOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which resets the current emulation.
- *
- * The emulation is reset by resetting all components' state variables to
- * their initial state, and by changing the current RunState to Paused.
- */
-class ResetCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %ResetCommand.
-	 */
-	ResetCommand();
-
-	virtual ~ResetCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// RESETCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/SaveCommand.h gxemul-0.7.0+dfsg/src/include/commands/SaveCommand.h
--- gxemul-0.6.2/src/include/commands/SaveCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/SaveCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,59 +0,0 @@
-#ifndef SAVECOMMAND_H
-#define	SAVECOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which saves a Component tree to a file in the filesystem.
- */
-class SaveCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs an %SaveCommand.
-	 */
-	SaveCommand();
-
-	virtual ~SaveCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-};
-
-
-#endif	// SAVECOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/StatusCommand.h gxemul-0.7.0+dfsg/src/include/commands/StatusCommand.h
--- gxemul-0.6.2/src/include/commands/StatusCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/StatusCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,61 +0,0 @@
-#ifndef STATUSCOMMAND_H
-#define	STATUSCOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which prints the current status.
- *
- * The status includes the RunState (Running or Paused).
- */
-class StatusCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %StatusCommand.
-	 */
-	StatusCommand();
-
-	virtual ~StatusCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-};
-
-
-#endif	// STATUSCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/StepCommand.h gxemul-0.7.0+dfsg/src/include/commands/StepCommand.h
--- gxemul-0.6.2/src/include/commands/StepCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/StepCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,69 +0,0 @@
-#ifndef STEPCOMMAND_H
-#define	STEPCOMMAND_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which sets the RunState to SingleStepping.
- */
-class StepCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %StepCommand.
-	 */
-	StepCommand();
-
-	virtual ~StepCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual bool MayBeReexecutedWithoutArgs() const
-	{
-		return true;
-	}
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// STEPCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/commands/VersionCommand.h gxemul-0.7.0+dfsg/src/include/commands/VersionCommand.h
--- gxemul-0.6.2/src/include/commands/VersionCommand.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/commands/VersionCommand.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,64 +0,0 @@
-#ifndef VERSIONCOMMAND_H
-#define	VERSIONCOMMAND_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Command.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A Command which prints the version of the application.
- */
-class VersionCommand
-	: public Command
-{
-public:
-	/**
-	 * \brief Constructs a %VersionCommand.
-	 */
-	VersionCommand();
-
-	virtual ~VersionCommand();
-
-	virtual bool Execute(GXemul& gxemul, const vector<string>& arguments);
-
-	virtual string GetShortDescription() const;
-
-	virtual string GetLongDescription() const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// VERSIONCOMMAND_H
diff -Nru gxemul-0.6.2/src/include/ComponentFactory.h gxemul-0.7.0+dfsg/src/include/ComponentFactory.h
--- gxemul-0.6.2/src/include/ComponentFactory.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/ComponentFactory.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,149 +0,0 @@
-#ifndef COMPONENTFACTORY_H
-#define	COMPONENTFACTORY_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Component.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A factory which creates Component objects.
- *
- * The main usage of the %ComponentFactory is simply:
- * "Hey, give me an XYZ component."
- * and the %ComponentFactory returns a reference counted pointer to something.
- * This can be a single Component, or it can be something more complex (a
- * %Component with children, etc).
- *
- * This mechanism is also used for templates. If the user wishes to create
- * a "testmips" machine, what actually happens is that CreateComponent() is
- * called with "testmips" as the argument, and it returns an entire tree,
- * which may contain something like:<pre>
- * machine0  [testmips]
- * |-- cpu0
- * |-- ram0
- * \-- framebuffer0
- * </pre>
- *
- * (The example above is semi-bogus, but should illustrate the point of
- * CreateComponent().)
- */
-class ComponentFactory
-	: public UnitTestable
-{
-public:
-	/**
-	 * \brief Creates a component given a short component name.
-	 *
-	 * componentNameAndOptionalArgs may be e.g.
-	 * <tt>"testmips(cpu=R4400,cpus=4)"</tt>.
-	 *
-	 * @param componentNameAndOptionalArgs The component name, e.g. "dummy",
-	 *	optionally followed by arguments in parentheses.
-	 * @param gxemul A pointer to a GXemul instance. May be NULL.
-	 * @return A reference counted Component pointer. This is set to the
-	 *      newly created component on success. On failure it is set to
-	 *      NULL.
-	 */
-	static refcount_ptr<Component> CreateComponent(
-		const string& componentNameAndOptionalArgs, GXemul* gxemul = NULL);
-
-	/**
-	 * \brief Gets a specific attribute value for a component.
-	 *
-	 * @param name The name of a component, e.g. "testmips".
-	 * @param attributeName The attribute, e.g. "template" or "machine".
-	 * @return A string containing the attribute value. This is an
-	 *	empty string if the component does not exist, or if the
-	 *	attribute was not set for the component.
-	 */
-	static string GetAttribute(const string& name, const string&
-		attributeName);
-
-	/**
-	 * \brief Checks if a component has a specific attribute.
-	 *
-	 * @param name The name of a component, e.g. "testmips".
-	 * @param attributeName The attribute, e.g. "template" or "machine".
-	 * @return True if the name exists and the attribute is not an
-	 *	empty string, false otherwise
-	 *	(both if the name is not known, and if it is known but
-	 *	the attribute was not set).
-	 */
-	static bool HasAttribute(const string& name, const string&
-		attributeName);
-
-	/**
-	 * \brief Returns a vector of all available component names.
-	 *
-	 * @param onlyTemplates If true, only those component names that
-	 *	are templates are returned.
-	 * @return A vector of all available component names.
-	 */
-	static vector<string> GetAllComponentNames(bool onlyTemplates);
-
-	/**
-	 * \brief Adds a new component class to the factory at runtime.
-	 *
-	 * Component classes added using this function are then available
-	 * when using e.g. CreateComponent.
-	 *
-	 * @param name The name of the component class. Must be a const char*
-	 *	which lives for the lifetime of the program.
-	 * @param createFunc A pointer to the component's Create function.
-	 * @param getAttributeFunc A pointer to the component's GetAttribute
-	 *	function.
-	 * @return True if the component class was registered, false
-	 *	if the name was already in use.
-	 */
-	static bool RegisterComponentClass(const char* name,
-		refcount_ptr<Component> (*createFunc)(const ComponentCreateArgs& args),
-		string (*getAttributeFunc)(const string& attributeName));
-
-	/**
-	 * \brief Get override arguments for component creation.
-	 */
-	static bool GetCreationArgOverrides(ComponentCreationSettings& settings,
-		const ComponentCreateArgs& createArgs);
-
-	/**
-	 * \brief Unregisters all manually registered component classes.
-	 */
-	static void UnregisterAllComponentClasses();
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// COMPONENTFACTORY_H
diff -Nru gxemul-0.6.2/src/include/Component.h gxemul-0.7.0+dfsg/src/include/Component.h
--- gxemul-0.6.2/src/include/Component.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/Component.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,745 +0,0 @@
-#ifndef COMPONENT_H
-#define	COMPONENT_H
-
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright 
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE  
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Checksum.h"
-#include "SerializationContext.h"
-#include "StateVariable.h"
-
-
-class AddressDataBus;
-class Component;
-class CPUComponent;
-class GXemul;
-class RootComponent;
-class UI;
-
-typedef vector< refcount_ptr<Component> > Components;
-typedef map< string,string > ComponentCreationSettings;
-
-struct ComponentCreateArgs
-{
-	GXemul*				gxemul;
-	ComponentCreationSettings	componentCreationSettings;
-};
-
-
-/**
- * \brief A %Component is a node in the configuration tree that
- *	makes up an emulation setup.
- *
- * The %Component is the core concept in %GXemul. All devices,
- * CPUs, networks, and so on are components.
- */
-class Component
-	: public ReferenceCountable
-{
-protected:
-	/**
-	 * \brief Base constructor for a %Component.
-	 *
-	 * See also: the Create() function.
-	 *
-	 * @param className	The name of the component class.
-	 *			It should be a short, descriptive name.
-	 *			For e.g. a PCI bus class, it can be "pcibus".
-	 *			For a MIPS CPU, it can be "mips_cpu".
-	 * @param visibleClassName	The visible name of the component class.
-	 *			It should be a short, descriptive name.
-	 *			For e.g. a PCI bus class, it can be "pcibus".
-	 *			For a MIPS CPU, it can be "cpu".
-	 */
-	Component(const string& className, const string& visibleClassName);
-
-public:
-	virtual ~Component() { }
-
-	/**
-	 * \brief Gets the class name of the component.
-	 *
-	 * @return the class name of the component, e.g. "pcibus" for a PCI
-	 *	bus component class, or "mips_cpu" for a MIPS CPU.
-	 */
-	string GetClassName() const;
-
-	/**
-	 * \brief Gets the visible class name of the component.
-	 *
-	 * @return the class name of the component, e.g. "pcibus" for a PCI
-	 *	bus component class, or "cpu" for a MIPS CPU.
-	 */
-	string GetVisibleClassName() const;
-
-	/**
-	 * \brief Creates a Component.
-	 *
-	 * The reason for having this helper, instead of simply calling the
-	 * constructor of a specific %Component, is to make templates work
-	 * in a reasonable and straight-forward manner. (Note: This concept
-	 * of templates is unrelated to the C++ concept of templates. It just
-	 * happens to be the same word.)
-	 *
-	 * E.g. DummyComponent::Create() returns a new DummyComponent, but
-	 * TestMIPSMachine::Create() returns a new MachineComponent
-	 * (with some pre-defined child components), not a TestMIPS component.
-	 */
-//	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	/**
-	 * \brief Get attribute information about a Component.
-	 *
-	 * @param attributeName The attribute name.
-	 * @return A string representing the attribute value. The base
-	 *	implementation returns an empty string; it is up to individual
-	 *	Components to return other values.
-	 */
-	static string GetAttribute(const string& attributeName);
-
-	/**
-	 * \brief Clones the component and all its children.
-	 *
-	 * The new copy is a complete copy; modifying either the copy or the
-	 * original will not affect the other.
-	 *
-	 * @return A reference counted pointer to the clone.
-	 */
-	refcount_ptr<Component> Clone() const;
-
-	/**
-	 * \brief Makes a light clone of the component and all its children.
-	 *
-	 * Modifying the original component will not affect the component
-	 * returned by this function.
-	 *
-	 * The new copy is <i>not</i> a complete copy. Expensive data
-	 * structures are not copied, only "light" data structures. For
-	 * example, RAM memory cell contents is not cloned.
-	 *
-	 * The main purpose of this function is to allow e.g. a single
-	 * stepper to take a light clone, run one step, and the compare
-	 * the current component tree with the light clone, to see what
-	 * was modified in the step.
-	 *
-	 * @return A const reference counted pointer to the light clone.
-	 */
-	const refcount_ptr<Component> LightClone() const;
-
-	/**
-	 * \brief Compare an older clone to the current tree, to find changes.
-	 *
-	 * Any changes found are written as messages to changeMessages.
-	 * Typical use of this function is to input a "light clone" which
-	 * is taken before running a single execution step, to find out
-	 * any side effects of that execution step.
-	 *
-	 * @param oldClone The original component tree to compare to.
-	 * @param changeMessages An output stream where to send messages.
-	 */
-	void DetectChanges(const refcount_ptr<Component>& oldClone,
-		ostream& changeMessages) const;
-
-	/**
-	 * \brief Generates an ASCII tree dump of a component tree.
-	 *
-	 * @param branchTemplate Used for recursion. Start with an empty
-	 *	string ("").
-	 * @param htmlLinksForClassNames Used to generate HTML links
-	 *	by 'make documentation'.
-	 * @param prefixForComponentUrls Placed before
-	 *	component/xyz.html in html links to components.
-	 * @return An ASCII string containing the tree.
-	 */
-	string GenerateTreeDump(const string& branchTemplate,
-		bool htmlLinksForClassNames = false,
-		string prefixForComponentUrls = "") const;
-
-	/**
-	 * \brief Generate details about the component.
-	 *
-	 * @return A string containing details about the component.
-	 */
-	virtual string GenerateDetails() const;
-
-	/**
-	 * \brief Resets the state of this component and all its children.
-	 */
-	void Reset();
-
-	/**
-	 * \brief Checks the state of this component and all its children,
-	 *	before starting execution.
-	 *
-	 * @return true if the component and all its children are ready to run,
-	 *	false otherwise.
-	 */
-	bool PreRunCheck(GXemul* gxemul);
-
-	/**
-	 * \brief Resets the cached state of this component and all its
-	 * children.
-	 *
-	 * For performance reasons, while an emulation is running, it is usually
-	 * a good idea to cache e.g. pointers to various things. However,
-	 * after pausing an emulation, and continuing again, these pointers
-	 * may not be valid. FlushCachedState() should be called before
-	 * Run() is called.
-	 */
-	void FlushCachedState();
-
-	/**
-	 * \brief Execute one or more cycles.
-	 *
-	 * Note 1: A component must attempt to execute exactly the number of
-	 * specified cycles.
-	 *
-	 * Note 2: If e.g. a breakpoint is reached, or some fatal error occurs
-	 * (such as an unimplemented feature in the emulation of the component
-	 * is triggered), then it is ok to return fewer than the requested
-	 * number of cycles. Execution will then stop (or the breakpoint will
-	 * be handled, etc).
-	 *
-	 * Note 3: The framework will only call this function if the component
-	 * has a StateVariable named "frequency". Components that do not have
-	 * any frequency do not execute anything periodically by themselves.
-	 *
-	 * @param gxemul A pointer to the GXemul instance.
-	 * @param nrOfCycles	The requested number of cycles to run.
-	 * @return	The number of cycles actually executed.
-	 */
-	virtual int Execute(GXemul* gxemul, int nrOfCycles);
-
-	/**
-	 * \brief Returns the current frequency (in Hz) that the component
-	 *	runs at.
-	 *
-	 * @return	The component's frequency in Hz.
-	 */
-	virtual double GetCurrentFrequency() const;
-
-	/**
-	 * \brief Returns the component's RootComponent interface.
-	 *
-	 * @return A pointer to the component as a %RootComponent, or
-	 * NULL if the component isn't a %RootComponent.
-	 */
-	virtual RootComponent* AsRootComponent();
-
-	/**
-	 * \brief Returns the component's CPUComponent interface.
-	 *
-	 * @return A pointer to the component as a %CPUComponent, or
-	 * NULL if the component isn't a CPU.
-	 */
-	virtual CPUComponent* AsCPUComponent();
-
-	/**
-	 * \brief Returns the component's AddressDataBus interface, if any.
-	 *
-	 * @return	A pointer to an AddressDataBus, or NULL if the
-	 *	component does not support that interface.
-	 */
-	virtual AddressDataBus* AsAddressDataBus();
-
-	/**
-	 * \brief Sets the parent component of this component.
-	 *
-	 * Note: Not reference counted.
-	 *
-	 * @param parentComponent	a pointer to the parent component.
-	 */
-	void SetParent(Component* parentComponent);
-
-	/**
-	 * \brief Gets this component's parent component, if any.
-	 *
-	 * Note: Not reference counted.
-	 *
-	 * Returns NULL if there is no parent component.
-	 *
-	 * @return the pointer to the parent component, or NULL
-	 */
-	Component* GetParent();
-	const Component* GetParent() const;
-
-	/**
-	 * \brief Retrieves a component's implemented method names.
-	 *
-	 * Note that a component's implementation should call its
-	 * base class' GetMethodNames(vector<string>&) too. However, when
-	 * methods are executed, the most specific implementation (i.e.
-	 * not the base class) will get a chance first to execute the method.
-	 *
-	 * @param names A vector of strings, where method names
-	 *	should be added.
-	 */
-	virtual void GetMethodNames(vector<string>& names) const;
-
-	/**
-	 * \brief Returns whether a method name may be re-executed without args.
-	 *
-	 * Typical examples may be a RAMComponent which has a "dump" method,
-	 * or a CPUComponent which has "dump" and "unassemble" methods.
-	 *
-	 * Note that a component's implementation should call its
-	 * base class' MethodMayBeReexecutedWithoutArgs(cosnt string&) too.
-	 *
-	 * @param methodName The name of the method.
-	 * @return true if the method may be re-executed without arguments,
-	 *	false otherwise.
-	 */
-	virtual bool MethodMayBeReexecutedWithoutArgs(const string& methodName) const;
-
-	/**
-	 * \brief Executes a method on the component.
-	 *
-	 * Note 1: The method name must be one of those returned
-	 *	by GetMethodNames(vector<string>&), either in the class itself
-	 *	or by one of the base implementations.
-	 *
-	 * Note 2: The base class' member function should <i>only</i> be called
-	 *	if this class does not handle the method.
-	 *
-	 * @param gxemul A reference to the GXemul instance.
-	 * @param methodName The name of the method.
-	 * @param arguments A vector of arguments to the method.
-	 */
-	virtual void ExecuteMethod(GXemul* gxemul,
-		const string& methodName,
-		const vector<string>& arguments);
-
-	/**
-	 * \brief Generates a string representation of the path to the
-	 *	%Component.
-	 *
-	 * The path consists of "name.name...name.name" where the last name
-	 * is the name of this component, and the preceding names are names
-	 * of parents.
-	 *
-	 * If a component does not have a "name" state variable, then the
-	 * class name in parentheses is used instead (which may make the path
-	 * non-unique).
-	 *
-	 * @return A path to the component, as a string.
-	 */
-	string GeneratePath() const;
-
-	/**
-	 * \brief Generates a short string representation of the path to the
-	 *	%Component.
-	 *
-	 * This function generates a string which is the shortest possible
-	 * sub-path required to uniqely identify a component in the tree.
-	 * (Actually, not really the shortest. For example if a component is
-	 * called root.machine0.mainbus0.ram0, then the shortest string may
-	 * be "ra". This function will return "ram0".)
-	 *
-	 * If there are components a.b.x, a.b.y, and a.c.x, then the shortest
-	 * possible paths for the three components are "b.x", "y", and "c.x"
-	 * respectively.
-	 *
-	 * @return A string which is part of the path of the component.
-	 */
-	string GenerateShortestPossiblePath() const;
-
-	/**
-	 * \brief Looks up a path from this %Component,
-	 *	and returns a pointer to the found %Component, if any
-	 *
-	 * The first name in the path should match the name of this component.
-	 * If so, this function moves on to the next part of the path (if there
-	 * are more parts) and looks up a child with that name, and so on.
-	 *
-	 * Alternatively, the path may be a partial match.
-	 *
-	 * @param path The path to the component, consisting of names with
-	 *	"." (period) between names.
-	 * @return A reference counted pointer to the looked up component,
-	 *	which is set to NULL if the path was not found.
-	 */
-	const refcount_ptr<Component> LookupPath(string path) const;
-
-	/**
-	 * \brief Finds complete component paths, given a partial path.
-	 *
-	 * E.g. if the following components are available:<pre>
-	 *	root.machine0.isabus0
-	 *	root.machine1.pcibus0
-	 *	root.machine1.pcibus1
-	 *	root.machine2.pcibus0
- 	 *	root.machine3.otherpci
-	 * </pre>
-	 *
-	 * then a search for "pci" would return<pre>
-	 *	root.machine1.pcibus0
-	 *	root.machine1.pcibus1
-	 *	root.machine2.pcibus0
-	 * </pre>
-	 * (note: not otherpci)
-	 *
-	 * A search for machine1 would return<pre>
-	 *	root.machine1
-	 * </pre>
-	 *
-	 * Multiple words separated by "." should also be possible, so
-	 * "machine2.pcibus" will find "root.machine2.pcibus0", but
-	 * "machine.pcibus" will <i>not</i> match anything.
-	 *
-	 * Searching for an empty string ("") returns a vector of <i>all</i>
-	 * component paths.
-	 *
-	 * @param partialPath The partial path to complete.
-	 * @param shortestPossible Return shortest possible paths, instead of
-	 *	full paths.
-	 * @return A vector of possible complete paths.
-	 */
-	vector<string> FindPathByPartialMatch(const string& partialPath,
-		bool shortestPossible = false) const;
-
-	/**
-	 * \brief Adds a reference to a child component.
-	 *
-	 * @param childComponent  A reference counted pointer to the child
-	 *	component to add.
-	 * @param insertPosition  If specified, this is the position in the
-	 *	vector of child components where the child will be inserted.
-	 *	If not specified (or -1), then the child will be added to
-	 *	the end of the vector.
-	 */
-	void AddChild(refcount_ptr<Component> childComponent,
-		size_t insertPosition = (size_t) -1);
-
-	/**
-	 * \brief Removes a reference to a child component.
-	 *
-	 * @param childToRemove  A pointer to the child to remove.
-	 * @return  A zero-based index, which is the position in the vector
-	 *	of children where the child was. (Needed for e.g. Undo
-	 *	functionality.)
-	 */
-	size_t RemoveChild(Component* childToRemove);
-
-	/**
-	 * \brief Gets pointers to child components.
-	 *
-	 * @return Reference counted pointers to child components.
-	 */
-	Components& GetChildren();
-
-	/**
-	 * \brief Gets pointers to child components, as a const reference.
-	 *
-	 * @return Reference counted pointers to child components.
-	 */
-	const Components& GetChildren() const;
-
-	/**
-	 * \brief Retrieves a component's state variable names.
-	 *
-	 * @param names A vector of strings, where method names
-	 *	should be added.
-	 */
-	void GetVariableNames(vector<string>& names) const;
-
-	/**
-	 * \brief Gets a pointer to a state variable.
-	 *
-	 * NOTE: The returned pointer should be used immediately after the
-	 *	call. It will in general not be valid after e.g. an
-	 *	AddVariable call.
-	 *
-	 * @param name The variable name.
-	 * @return A pointer to the variable, it the name was
-	 *	known; NULL otherwise.
-	 */
-	StateVariable* GetVariable(const string& name);
-
-	/**
-	 * \brief Gets a pointer to a state variable.
-	 *
-	 * NOTE: The returned pointer should be used immediately after the
-	 *	call. It will in general not be valid after e.g. an
-	 *	AddVariable call.
-	 *
-	 * @param name The variable name.
-	 * @return A pointer to the variable, it the name was
-	 *	known; NULL otherwise.
-	 */
-	const StateVariable* GetVariable(const string& name) const;
-
-	/**
-	 * \brief Sets a variable to a new value.
-	 *
-	 * @param name The variable name.
-	 * @param expression The new value.
-	 * @return True if the value was set, false otherwise. (E.g. if
-	 *	the name was not known, or if there was a parse error
-	 *	when parsing the value expression.)
-	 */
-	bool SetVariableValue(const string& name, const string& expression);
-
-	/**
-	 * \brief Serializes the %Component into a string stream.
-	 *
-	 * @param ss An ostream which the %Component will be serialized to.
-	 * @param context A serialization context (used for TAB indentation).
-	 */
-	void Serialize(ostream& ss, SerializationContext& context) const;
-
-	/**
-	 * \brief Deserializes a string into a component tree.
-	 *
-	 * @param messages A stream where errors/warnings may be reported.
-	 * @param str The string to deserialize.
-	 * @param pos Initial deserialization position in the string; should
-	 *	be 0 when invoked manually. (Used for recursion, to avoid
-	 *	copying.)
-	 * @return If deserialization was successful, the
-	 *	reference counted pointer will point to a component tree;
-	 *	on error, it will be set to NULL
-	 */
-	static refcount_ptr<Component> Deserialize(ostream& messages,
-	    const string& str, size_t& pos);
-
-	/**
-	 * \brief Checks consistency by serializing and deserializing the
-	 *	component (including all its child components), and comparing
-	 *	the checksum of the original tree with the deserialized tree.
-	 *
-	 * @return true if the serialization/deserialization was correct,
-	 *	false if there was some inconsistency
-	 */
-	bool CheckConsistency() const;
-
-	/**
-	 * \brief Adds this component's state, including children, to
-	 *	a checksum.
-	 *
-	 * @param checksum The checksum to add to.
-	 */
-	void AddChecksum(Checksum& checksum) const;
-
-protected:
-	/**
-	 * \brief Adds a state variable of type T to the %Component.
-	 *
-	 * This function is only meant to be called from the component's
-	 * constructor.
-	 *
-	 * @param name The variable name.
-	 * @param variablePointer A pointer to the variable that the name should
-	 *	be connected to.
-	 * @return True if the state variable was added, false if the name
-	 *	was already in use.
-	 */
-	template<class T>
-	bool AddVariable(const string& name, T* variablePointer)
-	{
-		StateVariableMap::iterator it = m_stateVariables.find(name);
-		if (it != m_stateVariables.end())
-			return false;
-
-		m_stateVariables.insert(pair<string,StateVariable>
-		    (name, StateVariable(name, variablePointer)));
-		return true;
-	}
-
-	/**
-	 * \brief Adds a custom state variable to the %Component.
-	 *
-	 * This function is only meant to be called from the component's
-	 * constructor.
-	 *
-	 * @param name The variable name.
-	 * @param variableHandler A pointer to the handler that knows how
-	 *	to serialize/deserialize the variable.
-	 * @return True if the state variable was added, false if the name
-	 *	was already in use.
-	 */
-	bool AddCustomVariable(const string& name, CustomStateVariableHandler* variableHandler)
-	{
-		StateVariableMap::iterator it = m_stateVariables.find(name);
-		if (it != m_stateVariables.end())
-			return false;
-
-		m_stateVariables.insert(pair<string,StateVariable>
-		    (name, StateVariable(name, variableHandler)));
-		return true;
-	}
-
-	/**
-	 * \brief Checks whether a write to a variable is OK.
-	 *
-	 * This function is called <i>after</i> the variable has been written.
-	 * By returning false, the component indicates that the value which
-	 * was written is invalid, and the write will be undone.
-	 *
-	 * An implementation should first check variables defined for the
-	 * implementation class, and then call its base class' function.
-	 *
-	 * The implementation in the base Component class handles the variables
-	 * that are defined for all components, and returns true for anything
-	 * else.
-	 *
-	 * @param var The variable to check.
-	 * @param oldValue The serialized previous value.
-	 * @return true if the write was ok, false otherwise.
-	 */
-	virtual bool CheckVariableWrite(StateVariable& var, const string& oldValue);
-
-	/**
-	 * \brief Resets the state variables of this component.
-	 *
-	 * Note 1: This function is not recursive, so children should not be
-	 * traversed.
-	 *
-	 * Note 2: After a component's state variables have been reset, the
-	 * base class' ResetState() function should also be called.
-	 *
-	 * The implementation of this function ususally takes the form of a
-	 * number of assignment of values to member variables, and then
-	 * the call to the base class' ResetState() function.
-	 */
-	virtual void ResetState();
-
-	/**
-	 * \brief Checks the state of this component, before starting execution.
-	 *
-	 * Note 1: This function is not recursive, so children should not be
-	 * traversed.
-	 *
-	 * Note 2: After a component's state variables have been checked, the
-	 * base class' PreRunCheckForComponent(GXemul*) function should also be
-	 * called.
-	 *
-	 * The implementation of this function may choose to print warning
-	 * messages but still return true, or it can print error messages and
-	 * return false.
-	 *
-	 * Typical examples of pre-run-check failures are:
-	 * <ul>
-	 *	<li>collision of MemoryMappedComponent on an AddressDataBus
-	 *	<li>a CPUComponent that can not reach any kind of AddressDataBus
-	 * </ul>
-	 *
-	 * @return true if the component is ready to run, false otherwise.
-	 */
-	virtual bool PreRunCheckForComponent(GXemul* gxemul);
-
-	/**
-	 * \brief Resets the cached state of this component.
-	 *
-	 * Note 1: This function is not recursive, so children should not be
-	 * traversed.
-	 *
-	 * Note 2: After a component's state variables have been reset, the
-	 * base class' FlushCachedStateForComponent() function should also be
-	 * called.
-	 *
-	 * The implementation of this function ususally takes the form of
-	 * setting a number of pointers to NULL, and then
-	 * the call to the base class' FlushCachedStateForComponent() function.
-	 */
-	virtual void FlushCachedStateForComponent();
-
-	/**
-	 * \brief Returns a reference to the current GXemul instance.
-	 *
-	 * @return NULL if there was no currently running instance, otherwise
-	 * a pointer to the currently running GXemul instance.
-	 */
-	GXemul* GetRunningGXemulInstance();
-
-	/**
-	 * \brief Gets an UI reference for outputting debug messages during
-	 * runtime.
-	 *
-	 * @return NULL if debug messages are turned off, or if there is no
-	 * owning GXemul instance. Otherwise, a pointer to an UI.
-	 */
-	 UI* GetUI();
-
-private:
-	/**
-	 * \brief Looks up a path from this %Component,
-	 *	and returns a pointer to the found %Component, if any
-	 *
-	 * The first name in the path should match the name of this component.
-	 * If so, this function moves on to the next part of the path (if there
-	 * are more parts) and looks up a child with that name, and so on.
-	 *
-	 * @param path The path to the component, split into separate names.
-	 *	This vector should contain at least 1 element.
-	 * @param index The index into the path vector, where the current
-	 *	lookup should start. (This is to avoid copying.)
-	 * @return A reference counted pointer to the looked up component,
-	 *	which is set to NULL if the path was not found.
-	 */
-	const refcount_ptr<Component> LookupPath(const vector<string>& path,
-		size_t index) const;
-
-	/**
-	 * \brief Internal helper, which gathers a list of all component paths.
-	 *
-	 * @param allComponentPaths A vector which will be filled with all
-	 *	components' paths.
-	 */
-	void AddAllComponentPaths(vector<string>& allComponentPaths) const;
-
-	/**
-	 * \brief Internal helper for LightClone.
-	 *
-	 * See LightClone() for details.
-	 */
-	refcount_ptr<Component> LightCloneInternal() const;
-
-	/**
-	 * \brief Disallow creation of %Component objects using the
-	 * default constructor.
-	 */
-	Component();
-
-private:
-	Component*		m_parentComponent;
-	Components		m_childComponents;
-	string			m_className;
-	string			m_visibleClassName;
-	StateVariableMap	m_stateVariables;
-
-	// The following are this component's variables. Components that
-	// inherit from this class add their own instance variables.
-	string		m_name;		// This Component's instance name.
-	string		m_template;	// Set if this Component
-					// was based on a template.
-	uint64_t	m_step;		// Nr of executed steps.
-};
-
-
-#endif	// COMPONENT_H
diff -Nru gxemul-0.6.2/src/include/components/CacheComponent.h gxemul-0.7.0+dfsg/src/include/components/CacheComponent.h
--- gxemul-0.6.2/src/include/components/CacheComponent.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/CacheComponent.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,137 +0,0 @@
-#ifndef CACHECOMPONENT_H
-#define	CACHECOMPONENT_H
-
-/*
- *  Copyright (C) 2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(cache)
-
-
-#include "AddressDataBus.h"
-#include "MemoryMappedComponent.h"
-
-#include "UnitTest.h"
-
-#include <string.h>
-#include <iomanip>
-
-
-/**
- * \brief A memory Cache Component.
- *
- * TODO
- *
- * Note: This class does <i>not</i> handle unaligned access. It is up to the
- * caller to make sure that e.g. ReadData(uint64_t&, Endianness) is only
- * called when the selected address is 64-bit aligned.
- *
- * (The reason for this is that different emulated components want different
- * semantics for unaligned access. For example, an x86 processor will
- * transparently allow unaligned access, most RISC processors will cause
- * an unaligned address exception, and some old ARM processors may even simply
- * ignore the lowest bits of the address!)
- */
-class CacheComponent
-	: public Component
-	, public AddressDataBus
-	, public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs a CacheComponent.
-	 *
-	 * @param visibleClassName The visible class name. Defaults to
-	 *	"cache". Useful alternatives may be "l1", "l2", or "l3".
-	 */
-	CacheComponent(const string& visibleClassName = "cache");
-
-	virtual ~CacheComponent();
-
-	/**
-	 * \brief Creates a CacheComponent.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	virtual void ResetState();
-
-	string GenerateDetails() const;
-
-	/**
-	 * \brief Get attribute information about the CacheComponent class.
-	 *
-	 * @param attributeName The attribute name.
-	 * @return A string representing the attribute value.
-	 */
-	static string GetAttribute(const string& attributeName);
-
-        virtual void GetMethodNames(vector<string>& names) const;
-
-	virtual bool MethodMayBeReexecutedWithoutArgs(const string& methodName) const;
-
-	virtual void ExecuteMethod(GXemul* gxemul,
-		const string& methodName,
-		const vector<string>& arguments);
-
-	/**
-	 * \brief Returns the component's AddressDataBus interface.
-	 *
-	 * @return	A pointer to an AddressDataBus.
-	 */
-	virtual AddressDataBus* AsAddressDataBus();
-
-	/* Implementation of AddressDataBus: */
-	virtual void AddressSelect(uint64_t address);
-	virtual bool ReadData(uint8_t& data, Endianness endianness);
-	virtual bool ReadData(uint16_t& data, Endianness endianness);
-	virtual bool ReadData(uint32_t& data, Endianness endianness);
-	virtual bool ReadData(uint64_t& data, Endianness endianness);
-	virtual bool WriteData(const uint8_t& data, Endianness endianness);
-	virtual bool WriteData(const uint16_t& data, Endianness endianness);
-	virtual bool WriteData(const uint32_t& data, Endianness endianness);
-	virtual bool WriteData(const uint64_t& data, Endianness endianness);
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-private:
-
-private:
-	// State:
-	uint64_t			m_size;		// total cache size
-	uint64_t			m_lineSize;	// line size, in bytes
-	uint64_t			m_lastDumpAddr;
-	int				m_associativity;// 0 = fully. 1 = direct mapped. n = n-way.
-	// TODO: the actual data (cache lines)
-
-	// Cached/runtime state:
-	uint64_t	m_addressSelect;  // For AddressDataBus read/write
-};
-
-
-#endif	// CACHECOMPONENT_H
diff -Nru gxemul-0.6.2/src/include/components/CPUComponent.h gxemul-0.7.0+dfsg/src/include/components/CPUComponent.h
--- gxemul-0.6.2/src/include/components/CPUComponent.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/CPUComponent.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,235 +0,0 @@
-#ifndef CPUCOMPONENT_H
-#define	CPUCOMPONENT_H
-
-/*
- *  Copyright (C) 2008-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// Note: Not included in the component registry.
-
-
-#include "AddressDataBus.h"
-#include "Component.h"
-#include "SymbolRegistry.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A base-class for processors Component implementations.
- */
-class CPUComponent
-	: public Component
-	, public AddressDataBus
-	, public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs a CPUComponent.
-	 *
-	 * @param className The class name for the component.
-	 * @param cpuKind The CPU kind, e.g. "MIPS R4400" for a
-	 *	MIPS R4400 processor.
-	 */
-	CPUComponent(const string& className, const string& cpuKind);
-
-	/**
-	 * \brief Gets a reference to the CPU's symbol registry.
-	 *
-	 * @return A reference to the symbol registry.
-	 */
-	SymbolRegistry& GetSymbolRegistry()
-	{
-		return m_symbolRegistry;
-	}
-	const SymbolRegistry& GetSymbolRegistry() const
-	{
-		return m_symbolRegistry;
-	}
-
-	virtual void ResetState();
-
-	virtual double GetCurrentFrequency() const;
-
-	virtual CPUComponent* AsCPUComponent();
-
-        virtual void GetMethodNames(vector<string>& names) const;
-
-	virtual bool MethodMayBeReexecutedWithoutArgs(const string& methodName) const;
-
-	virtual void ExecuteMethod(GXemul* gxemul,
-		const string& methodName,
-		const vector<string>& arguments);
-
-	virtual AddressDataBus* AsAddressDataBus();
-
-	/* Implementation of AddressDataBus: */
-	virtual void AddressSelect(uint64_t address);
-	virtual bool ReadData(uint8_t& data, Endianness endianness);
-	virtual bool ReadData(uint16_t& data, Endianness endianness);
-	virtual bool ReadData(uint32_t& data, Endianness endianness);
-	virtual bool ReadData(uint64_t& data, Endianness endianness);
-	virtual bool WriteData(const uint8_t& data, Endianness endianness);
-	virtual bool WriteData(const uint16_t& data, Endianness endianness);
-	virtual bool WriteData(const uint32_t& data, Endianness endianness);
-	virtual bool WriteData(const uint64_t& data, Endianness endianness);
-
-	/**
-	 * \brief Disassembles an instruction into readable strings.
-	 *
-	 * @param vaddr The virtual address of the program counter.
-	 * @param result A vector where the implementation will add:
-	 *	<ol>
-	 *		<li>machine code bytes in a standard notation
-	 *		<li>instruction mnemonic
-	 *		<li>instruction arguments
-	 *		<li>instruction comments
-	 *	</ol>
-	 *	All of the fields above are optional, but they have to be
-	 *	specified in the same order for a particular CPU implementation,
-	 *	so that the fields of the vector can be listed in a tabular
-	 *	format.
-	 * @return The number of bytes that the instruction occupied.
-	 */	
-	virtual size_t DisassembleInstruction(uint64_t vaddr, vector<string>& result) = 0;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-protected:
-	virtual void FlushCachedStateForComponent();
-	virtual bool PreRunCheckForComponent(GXemul* gxemul);
-	virtual void ShowRegisters(GXemul* gxemul, const vector<string>& arguments) const;
-
-	uint64_t Unassemble(int nRows, bool indicatePC, uint64_t vaddr, ostream& output);
-
-	/**
-	 * \brief Virtual to physical address translation (MMU).
-	 *
-	 * This function should be overridden in each CPU implementation.
-	 *
-	 * @param vaddr The virtual address to translate.
-	 * @param paddr The return value; physical address.
-	 * @param writable This is set to true or false by the function,
-	 *	depending on if the memory at the virtual address was
-	 *	writable or not.
-	 * @return True if the translation succeeded, false if there was a
-	 *	translation error.
-	 */
-	virtual bool VirtualToPhysical(uint64_t vaddr, uint64_t& paddr,
-					bool& writable) = 0;
-
-	/**
-	 * \brief Format a virtual address as a displayable string.
-	 *
-	 * This function may be overridden in each CPU implementation.
-	 * The default implementation just uses the stringstream << operator.
-	 *
-	 * @param vaddr The virtual address to translate.
-	 * @return A string rendering of the virtual address, e.g. "0x00100f00"
-	 */
-	virtual string VirtualAddressAsString(uint64_t vaddr)
-	{
-		stringstream ss;
-		ss.flags(std::ios::hex | std::ios::showbase);
-		ss << vaddr;
-		return ss.str();
-	}
-
-	/**
-	 * \brief Convert PC value to instuction address.
-	 *
-	 * Usually, this does not need to be overridden. However, some
-	 * architectures use e.g. the lowest bit of the PC register to indicate
-	 * a different encoding mode (MIPS16), but the instruction is still
-	 * aligned as if the lowest bit was 0.
-	 */
-	virtual uint64_t PCtoInstructionAddress(uint64_t pc)
-	{
-		return pc;
-	}
-
-	// CPUComponent:
-	bool FunctionTraceCall();
-	bool FunctionTraceReturn();
-
-	// Overridden by each CPU architecture:
-	virtual int FunctionTraceArgumentCount() { return 0; }
-	virtual int64_t FunctionTraceArgument(int n) { return 0; }
-	virtual bool FunctionTraceReturnImpl(int64_t& retval) { return false; }
-
-private:
-	bool LookupAddressDataBus(GXemul* gxemul = NULL);
-
-protected:
-	/*
-	 * Variables common to all (or most) kinds of CPUs:
-	 */
-
-	// Framework frequency/runability:
-	double			m_frequency;
-	bool			m_paused;
-
-	// Architecture fundamentals:
-	string			m_cpuArchitecture;
-	int			m_pageSize;
-
-	// Program counter:
-	uint64_t		m_pc;
-
-	// Memory dump and disassembly:
-	uint64_t		m_lastDumpAddr;
-	uint64_t		m_lastUnassembleVaddr;
-	bool			m_hasUsedUnassemble;
-
-	// Endianness:
-	bool			m_isBigEndian;
-
-	// Function call trace:
-	bool			m_showFunctionTraceCall;
-	bool			m_showFunctionTraceReturn;
-	int32_t			m_functionCallTraceDepth;
-	int64_t			m_nrOfTracedFunctionCalls;
-
-	// Delay slot related:
-	bool			m_inDelaySlot;
-	uint64_t		m_delaySlotTarget;
-
-
-	/*
-	 * Cached/volatile state:
-	 */
-	AddressDataBus *	m_addressDataBus;
-	uint64_t		m_addressSelect;
-	bool			m_exceptionOrAbortInDelaySlot;
-
-private:
-	SymbolRegistry		m_symbolRegistry;
-};
-
-
-#endif	// CPUCOMPONENT_H
diff -Nru gxemul-0.6.2/src/include/components/CPUDyntransComponent.h gxemul-0.7.0+dfsg/src/include/components/CPUDyntransComponent.h
--- gxemul-0.6.2/src/include/components/CPUDyntransComponent.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/CPUDyntransComponent.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,633 +0,0 @@
-#ifndef CPUDYNTRANSCOMPONENT_H
-#define	CPUDYNTRANSCOMPONENT_H
-
-/*
- *  Copyright (C) 2008-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// Note: Not included in the component registry.
-
-
-#include "CPUComponent.h"
-#include "UnitTest.h"
-
-#include <assert.h>
-
-
-class CPUDyntransComponent;
-
-
-#define N_DYNTRANS_IC_ARGS	3
-/**
- * \brief A dyntrans instruction call.
- *
- * f points to a function to be executed.
- * arg[] contains arguments, such as pointers to registers, or immediate values.
- */
-class CPUDyntransComponent;
-struct DyntransIC;
-typedef void (*DyntransIC_t)(class CPUDyntransComponent*, struct DyntransIC*);
-
-struct DyntransIC
-{
-	DyntransIC_t f;
-
-	union {
-		void* p;
-		uint32_t u32;
-	} arg[N_DYNTRANS_IC_ARGS];
-};
-
-/*
- * A dyntrans page contains DyntransIC calls for each instruction slot, followed
- * by some special entries, which handle execution going over the end of a page
- * (by changing the PC to the start of the next virtual page).
- */
-#define	DYNTRANS_PAGE_NSPECIALENTRIES	2
-
-
-/*
- * Some helpers for implementing dyntrans instructions.
- */
-#define DECLARE_DYNTRANS_INSTR(name) static void instr_##name(CPUDyntransComponent* cpubase, DyntransIC* ic);
-#define DYNTRANS_INSTR(class,name) void class::instr_##name(CPUDyntransComponent* cpubase, DyntransIC* ic)
-#define DYNTRANS_INSTR_HEAD(class)  class* cpu = (class*) cpubase;
-
-#define REG32(arg)	(*((uint32_t*)((arg).p)))
-#define REG64(arg)	(*((uint64_t*)((arg).p)))
-
-#define DYNTRANS_SYNCH_PC	cpu->m_nextIC = ic; cpu->DyntransResyncPC()
-
-
-/**
- * \brief A base-class for processors Component implementations that
- *	use dynamic translation.
- */
-class CPUDyntransComponent
-	: public CPUComponent
-{
-public:
-	/**
-	 * \brief Constructs a CPUDyntransComponent.
-	 *
-	 * @param className The class name for the component.
-	 * @param cpuKind The CPU kind, e.g. "MIPS R4400" for a
-	 *	MIPS R4400 processor.
-	 */
-	CPUDyntransComponent(const string& className, const string& cpuKind);
-
-	virtual int Execute(GXemul* gxemul, int nrOfCycles);
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-protected:
-	// Implemented by specific CPU families:
-	virtual int GetDyntransICshift() const = 0;
-	virtual DyntransIC_t GetDyntransToBeTranslated() = 0;
-
-	void DyntransToBeTranslatedBegin(struct DyntransIC*);
-	bool DyntransReadInstruction(uint16_t& iword, int offset = 0);
-	bool DyntransReadInstruction(uint32_t& iword, int offset = 0);
-	void DyntransToBeTranslatedDone(struct DyntransIC*);
-
-	/**
-	 * \brief Calculate m_pc based on m_nextIC and m_firstIConPage.
-	 */
-	void DyntransResyncPC();
-
-	/**
-	 * \brief Calculate m_nextIC and m_firstIConPage, based on m_pc.
-	 *
-	 * This function may return pointers to within an existing translation
-	 * page (hopefully the most common case, since it is the fastest), or
-	 * it may allocate a new empty page.
-	 */
-	void DyntransPCtoPointers();
-
-private:
-	void DyntransInit();
-	struct DyntransIC* DyntransGetICPage(uint64_t addr);
-	void DyntransClearICPage(struct DyntransIC* icpage);
-
-protected:
-	/*
-	 * Generic dyntrans instruction implementations, that may be used by
-	 * several different cpu architectures.
-	 */
-	DECLARE_DYNTRANS_INSTR(nop);
-	DECLARE_DYNTRANS_INSTR(abort);
-	DECLARE_DYNTRANS_INSTR(endOfPage);
-	DECLARE_DYNTRANS_INSTR(endOfPage2);
-
-	// Branches.
-	DECLARE_DYNTRANS_INSTR(branch_samepage);
-
-	// Data movement.
-	DECLARE_DYNTRANS_INSTR(set_u64_imms32);
-	DECLARE_DYNTRANS_INSTR(mov_u64_u64);
-
-	// Arithmetic.
-	DECLARE_DYNTRANS_INSTR(add_u32_u32_immu32);
-	DECLARE_DYNTRANS_INSTR(add_u32_u32_u32);
-	DECLARE_DYNTRANS_INSTR(add_u64_u64_imms32_truncS32);
-	DECLARE_DYNTRANS_INSTR(add_u64_u64_u64_truncS32);
-	DECLARE_DYNTRANS_INSTR(add_u64_u64_imms32);
-	DECLARE_DYNTRANS_INSTR(sub_u32_u32_immu32);
-	DECLARE_DYNTRANS_INSTR(sub_u32_u32_u32);
-	DECLARE_DYNTRANS_INSTR(sub_u64_u64_u64_truncS32);
-
-	// Logic.
-	DECLARE_DYNTRANS_INSTR(and_u32_u32_immu32);
-	DECLARE_DYNTRANS_INSTR(and_u64_u64_immu32);
-	DECLARE_DYNTRANS_INSTR(or_u32_u32_immu32);
-	DECLARE_DYNTRANS_INSTR(or_u32_u32_u32);
-	DECLARE_DYNTRANS_INSTR(or_u64_u64_immu32);
-	DECLARE_DYNTRANS_INSTR(xor_u32_u32_immu32);
-	DECLARE_DYNTRANS_INSTR(xor_u32_u32_u32);
-	DECLARE_DYNTRANS_INSTR(xor_u64_u64_immu32);
-	DECLARE_DYNTRANS_INSTR(xor_u64_u64_u64);
-
-	// Shifts, rotates.
-	DECLARE_DYNTRANS_INSTR(shift_left_u64_u64_imm5_truncS32);
-	DECLARE_DYNTRANS_INSTR(shift_right_u64_u64asu32_imm5_truncS32);
-
-private:
-	class DyntransTranslationPage
-	{
-	public:
-		DyntransTranslationPage(int nICentriesPerpage)
-			: m_prev(-1)
-			, m_next(-1)
-			, m_nextCacheEntryForAddr(-1)
-			, m_addr(0)
-			, m_showFunctionTraceCall(false)
-		{
-			m_ic.resize(nICentriesPerpage);
-		}
-
-	public:
-		// Linked list: Freelist or MRU list
-		int				m_prev;
-		int				m_next;
-
-		// Address match:
-		int				m_nextCacheEntryForAddr;
-		uint64_t			m_addr;
-
-		// Flags for this page:
-		// TODO: In the future, this could be stuff like different
-		// instruction encodings (MIPS16/Thumb vs 32-bit encoding),
-		// or other mode switches.
-		bool				m_showFunctionTraceCall;
-
-		// Translated instructions:
-		vector< struct DyntransIC >	m_ic;
-	};
-
-	class DyntransTranslationCache
-	{
-	public:
-		DyntransTranslationCache()
-			: m_nICentriesPerpage(0)
-			, m_pageShift(0)
-			, m_firstFree(-1)
-			, m_lastFree(-1)
-			, m_firstMRU(-1)
-			, m_lastMRU(-1)
-		{
-		}
-
-		void Reinit(size_t approximateSize, int nICentriesPerpage, int pageShift)
-		{
-			size_t approximateSizePerPage = sizeof(struct DyntransIC) * nICentriesPerpage + 64;
-			size_t nrOfPages = approximateSize / approximateSizePerPage;
-
-			if (nrOfPages < 2) {
-				std::cerr << "Too small translation cache!\n";
-				throw std::exception();
-			}
-
-			if (nICentriesPerpage == m_nICentriesPerpage &&
-			    nrOfPages == m_pageCache.size() &&
-			    pageShift == m_pageShift)
-				return;
-
-			m_nICentriesPerpage = nICentriesPerpage;
-			m_pageShift = pageShift;
-
-			// Generate empty pages:
-			m_pageCache.clear();
-			m_pageCache.resize(nrOfPages, DyntransTranslationPage(nICentriesPerpage));
-
-			// Set up the free-list to connect all pages:
-			m_firstFree = 0;
-			m_lastFree = nrOfPages - 1;
-			for (int i=m_firstFree; i<=m_lastFree; i++) {
-				m_pageCache[i].m_prev = i-1;	// note: i=0 (first page)
-								// results in prev = -1.
-
-				if (i == m_lastFree)
-					m_pageCache[i].m_next = -1;
-				else
-					m_pageCache[i].m_next = i+1;
-			}
-
-			// No pages in use yet, so nothing on the MRU list:
-			m_firstMRU = m_lastMRU = -1;
-
-			// Reset the quick lookup table:
-			// (Currently hardcoded to allow the first 1 GB of emulated physical memory
-			// to be looked up with 1 call, if more than 1 GB of RAM is used, the
-			// m_nextCacheEntryForAddr chain must be traversed...)
-			m_addrToFirstPageIndex.resize(1024 * 1048576 >> m_pageShift);
-			for (size_t i=0; i<m_addrToFirstPageIndex.size(); ++i)
-				m_addrToFirstPageIndex[i] = -1;
-
-			ValidateConsistency();
-		}
-
-		void ValidateConsistency()
-		{
-#ifndef NDEBUG
-			vector<bool> pageIsInMRUList;
-			vector<bool> pageIsInFreeList;
-			vector<bool> pageIsInMRUListReverse;
-			vector<bool> pageIsInFreeListReverse;
-
-			pageIsInMRUList.resize(m_pageCache.size(), false);
-			pageIsInFreeList.resize(m_pageCache.size(), false);
-			pageIsInMRUListReverse.resize(m_pageCache.size(), false);
-			pageIsInFreeListReverse.resize(m_pageCache.size(), false);
-
-			// Follow free-list forward:
-			int i = m_firstFree;
-			while (i >= 0) {
-				pageIsInFreeList[i] = true;
-				i = m_pageCache[i].m_next;
-			}
-
-			// Follow free-list backwards:
-			i = m_lastFree;
-			while (i >= 0) {
-				pageIsInFreeListReverse[i] = true;
-				i = m_pageCache[i].m_prev;
-			}
-
-			// Follow MRU-list forward:
-			i = m_firstMRU;
-			while (i >= 0) {
-				pageIsInMRUList[i] = true;
-				i = m_pageCache[i].m_next;
-			}
-
-			// Follow MRU-list backwards:
-			i = m_lastMRU;
-			while (i >= 0) {
-				pageIsInMRUListReverse[i] = true;
-				i = m_pageCache[i].m_prev;
-			}
-
-			// The forward and reverse sets should match:
-			for (size_t j=0; j<m_pageCache.size(); ++j) {
-				if (pageIsInFreeList[j] != pageIsInFreeListReverse[j]) {
-					std::cerr << "Forward and reverse Free-list iteration mismatch, position " << j << "!\n";
-					throw std::exception();
-				}
-
-				if (pageIsInMRUList[j] != pageIsInMRUListReverse[j]) {
-					std::cerr << "Forward and reverse MRU-list iteration mismatch, position " << j << "!\n";
-					throw std::exception();
-				}
-
-				if ((pageIsInMRUList[j] ^ pageIsInFreeList[j]) == false) {
-					std::cerr << "Each page should be in exactly ONE of the two lists, position " << j << "!\n";
-					throw std::exception();
-				}
-			}
-
-			vector<bool> pageIsPointedToByQuickLookupTable;
-			vector<bool> pageIsPointedToByQLTChain;
-			pageIsPointedToByQuickLookupTable.resize(m_pageCache.size(), false);
-			pageIsPointedToByQLTChain.resize(m_pageCache.size(), false);
-
-			for (size_t k=0; k<m_addrToFirstPageIndex.size(); ++k)
-				if (m_addrToFirstPageIndex[k] >= 0)
-					pageIsPointedToByQuickLookupTable[m_addrToFirstPageIndex[k]] = true;
-
-			for (size_t k=0; k<m_pageCache.size(); ++k) {
-				int index = m_pageCache[k].m_nextCacheEntryForAddr;
-				if (index >= 0)
-					pageIsPointedToByQLTChain[index] = true;
-			}
-
-			for (size_t k=0; k<pageIsInFreeList.size(); ++k) {
-				if (!pageIsInFreeList[k])
-					continue;
-
-				if (m_pageCache[k].m_nextCacheEntryForAddr >= 0) {
-					std::cerr << "Pages on the free-list should not have m_nextCacheEntryForAddr set!\n";
-					throw std::exception();
-				}
-
-				if (pageIsPointedToByQuickLookupTable[k]) {
-					std::cerr << "Pages on the free-list should not be pointed to by the quick lookup table!\n";
-					throw std::exception();
-				}
-
-				if (pageIsPointedToByQLTChain[k]) {
-					std::cerr << "Pages on the free-list should not be in the quick lookup table chain!\n";
-					throw std::exception();
-				}
-			}
-
-			for (size_t k=0; k<pageIsInMRUList.size(); ++k) {
-				if (!pageIsInMRUList[k])
-					continue;
-
-				uint64_t addr = m_pageCache[k].m_addr;
-				uint64_t physPageNumber = addr >> m_pageShift;
-				int quickLookupIndex = physPageNumber & (m_addrToFirstPageIndex.size() - 1);
-				int pageIndex = m_addrToFirstPageIndex[quickLookupIndex];
-
-				while (pageIndex >= 0) {
-					if (m_pageCache[pageIndex].m_addr == addr)
-						break;
-
-					pageIndex = m_pageCache[pageIndex].m_nextCacheEntryForAddr;
-				}
-
-				if (pageIndex < 0) {
-					std::cerr << "Pages in the MRU list must be reachable from the quick lookup table!\n";
-					throw std::exception();
-				}
-			}
-#endif
-		}
-
-		void FreeLeastRecentlyUsedPage()
-		{
-			// This function should only be called if it is really necessary to
-			// free a page, i.e. if there is no free page at all.
-			assert(m_firstFree < 0);
-
-			if (m_firstMRU == m_lastMRU) {
-				std::cerr << "Attempt to free a page, but there's only one page in the MRU list. Too small!\n";
-				throw std::exception();
-			}
-
-			// This is the one we will free.
-			int index = m_lastMRU;
-			assert(m_pageCache[index].m_prev >= 0);
-			assert(m_pageCache[index].m_next < 0);
-
-			// Disconnect it from the MRU list...
-			m_lastMRU = m_pageCache[index].m_prev;
-			m_pageCache[m_lastMRU].m_next = -1;
-
-			// ... and add it first in the free-list:
-			if (m_firstFree < 0) {
-				// In fact, the free-list was empty.
-				m_firstFree = m_lastFree = index;
-				m_pageCache[index].m_prev = -1;
-				m_pageCache[index].m_next = -1;
-			} else {
-				m_pageCache[index].m_prev = -1;
-				m_pageCache[index].m_next = m_firstFree;
-				m_pageCache[m_firstFree].m_prev = index;
-				m_firstFree = index;
-			}
-
-			// Remove from the quick lookup chain:
-			uint64_t physPageNumber = m_pageCache[index].m_addr >> m_pageShift;
-			int quickLookupIndex = physPageNumber & (m_addrToFirstPageIndex.size() - 1);
-			int pageIndex = m_addrToFirstPageIndex[quickLookupIndex];
-			if (pageIndex == index) {
-				// Direct hit? Then remove from the base quick look up table...
-				m_addrToFirstPageIndex[quickLookupIndex] = m_pageCache[index].m_nextCacheEntryForAddr;
-			} else {
-				// ... otherwise traverse the chain until the next entry is the one we are removing.
-				while (true) {
-					if (m_pageCache[pageIndex].m_nextCacheEntryForAddr == index) {
-						m_pageCache[pageIndex].m_nextCacheEntryForAddr = m_pageCache[index].m_nextCacheEntryForAddr;
-						break;
-					}
-
-					pageIndex = m_pageCache[pageIndex].m_nextCacheEntryForAddr;
-				}
-			}
-
-			m_pageCache[index].m_nextCacheEntryForAddr = -1;
-
-			ValidateConsistency();
-		}
-
-		struct DyntransIC *AllocateNewPage(uint64_t addr, bool showFunctionTraceCall)
-		{
-			int index = m_firstFree;
-			assert(index >= 0);
-
-			// Let's grab this index for ourselves...
-
-			// Was this the only free page?
-			if (index == m_lastFree) {
-				// Then there will be no more free pages.
-				m_firstFree = m_lastFree = -1;
-			} else {
-				// No, just update the chain:
-				m_firstFree = m_pageCache[index].m_next;
-				m_pageCache[m_firstFree].m_prev = -1;
-			}
-
-			// The page's prev and next fields should be updated to
-			// be part of the MRU list now.
-
-			// Is there nothing in the MRU list?
-			if (m_firstMRU == -1) {
-				// Then we are the only one.
-				m_firstMRU = m_lastMRU = index;
-				m_pageCache[index].m_next = m_pageCache[index].m_prev = -1;
-			} else {
-				// Then we place ourselves first:
-				m_pageCache[m_firstMRU].m_prev = index;
-				m_pageCache[index].m_next = m_firstMRU;
-				m_firstMRU = index;
-				m_pageCache[index].m_prev = -1;
-			}
-
-			// Set attributes for the page: address and other flags.
-			m_pageCache[index].m_addr = addr;
-			m_pageCache[index].m_showFunctionTraceCall = showFunctionTraceCall;
-
-			// Insert into quick lookup table:
-			uint64_t physPageNumber = addr >> m_pageShift;
-			int quickLookupIndex = physPageNumber & (m_addrToFirstPageIndex.size() - 1);
-
-			// Are we the only one? (I.e. the first page for this quick lookup index.)
-			if (m_addrToFirstPageIndex[quickLookupIndex] < 0) {
-				m_addrToFirstPageIndex[quickLookupIndex] = index;
-				m_pageCache[index].m_nextCacheEntryForAddr = -1;
-			} else {
-				// No. Let's add ourselves first in the chain:
-				m_pageCache[index].m_nextCacheEntryForAddr = m_addrToFirstPageIndex[quickLookupIndex];
-				m_addrToFirstPageIndex[quickLookupIndex] = index;
-			}
-
-			ValidateConsistency();
-
-			return &(m_pageCache[index].m_ic[0]);
-		}
-
-		struct DyntransIC *GetICPage(uint64_t addr, bool showFunctionTraceCall, bool& clear)
-		{
-			clear = false;
-
-			// Strip of the low bits:
-			addr >>= m_pageShift;
-			uint64_t physPageNumber = addr;
-			addr <<= m_pageShift;
-
-			int quickLookupIndex = physPageNumber & (m_addrToFirstPageIndex.size() - 1);
-			int pageIndex = m_addrToFirstPageIndex[quickLookupIndex];
-
-			// std::cerr << "addr " << addr << ", physPageNumber " << physPageNumber << ", quickLookupIndex " << quickLookupIndex << ", pageIndex " << pageIndex << "\n";
-
-			// If pageIndex >= 0, then pageIndex points to a page which _may_ be for this addr.
-			while (pageIndex >= 0) {
-				if (m_pageCache[pageIndex].m_addr == addr)
-					break;
-
-				// If the page for pageIndex was for some other address, then
-				// let's continue searching the chain...
-				pageIndex = m_pageCache[pageIndex].m_nextCacheEntryForAddr;
-			}
-
-			// If we have a definite page index, then return a pointer that page's ICs:
-			if (pageIndex >= 0) {
-				// Update the MRU list, unless this page was already first,
-				// so that m_firstMRU points to the page.
-				if (m_firstMRU != pageIndex) {
-					// Disconnect from previous place...
-					int prev = m_pageCache[pageIndex].m_prev;
-					int next = m_pageCache[pageIndex].m_next;
-					if (prev >= 0)
-						m_pageCache[prev].m_next = next;
-					if (next >= 0)
-						m_pageCache[next].m_prev = prev;
-
-					// ... disconnect from "end of list":
-					if (pageIndex == m_lastMRU)
-						m_lastMRU = prev;
-
-					// ... and insert first in list:
-					m_pageCache[pageIndex].m_prev = -1;
-					m_pageCache[pageIndex].m_next = m_firstMRU;
-					m_pageCache[m_firstMRU].m_prev = pageIndex;
-					m_firstMRU = pageIndex;
-				}
-
-				// TODO: Hm... also move to front of the Quick Lookup chain?
-				// Only necessary if more memory is used/emulated than the
-				// size of the quick lookup table, e.g. if 2 GB ram are used,
-				// and the size of the lookup table is 1 GB, and pages
-				// at exactly 0 GB and 1 GB are used in this order:
-				// 1 0 1 1 1 1 1 1 1 1 1 1 1
-				// then 1 would first be placed in the chain, then 0 (which
-				// would insert it first in the chain). But all lookups after
-				// that would have to search the whole chain (0, 1) to find 1.
-
-				ValidateConsistency();
-
-				// If flags are not the same, then let's clear the page:
-				if (m_pageCache[pageIndex].m_showFunctionTraceCall != showFunctionTraceCall) {
-					m_pageCache[pageIndex].m_showFunctionTraceCall = showFunctionTraceCall;
-					clear = true;
-				}
-
-				return &(m_pageCache[pageIndex].m_ic[0]);
-			}
-
-			// The address was NOT in the translation cache at all. So we have
-			// to create a new page.
-
-			// If the free-list is all used up, that means we have to free something
-			// before we can allocate a new page...
-			if (m_firstFree < 0)
-				FreeLeastRecentlyUsedPage();
-
-			// ... and then finally allocate a new page:
-			clear = true;
-			return AllocateNewPage(addr, showFunctionTraceCall);
-		}
-
-	private:
-		// Number of translated instructions per page, and number of bits
-		// to shift to convert address to page number:
-		int				m_nICentriesPerpage;
-		int				m_pageShift;
-
-		// Free-list of pages:
-		int				m_firstFree;
-		int				m_lastFree;
-
-		// Most-Recently-Used list of pages:
-		int				m_firstMRU;
-		int				m_lastMRU;
-
-		// "Usually" quick lookup table, address to page index:
-		vector<int>			m_addrToFirstPageIndex;
-
-		// The actual pages:
-		vector<DyntransTranslationPage>	m_pageCache;
-	};
-
-protected:
-	/*
-	 * Volatile state:
-	 */
-	struct DyntransIC *	m_firstIConPage;
-	struct DyntransIC *	m_nextIC;
-	int			m_dyntransPageMask;
-	int			m_dyntransICentriesPerPage;
-	int			m_dyntransICshift;
-	int			m_executedCycles;
-	int			m_nrOfCyclesToExecute;
-
-	/*
-	 * Translation cache:
-	 */
-	DyntransTranslationCache	m_translationCache;
-
-	/*
-	 * Special always present DyntransIC structs, for aborting emulation:
-	 */
-	struct DyntransIC	m_abortIC;
-};
-
-
-#endif	// CPUDYNTRANSCOMPONENT_H
diff -Nru gxemul-0.6.2/src/include/components/CycloneVHMachine.h gxemul-0.7.0+dfsg/src/include/components/CycloneVHMachine.h
--- gxemul-0.6.2/src/include/components/CycloneVHMachine.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/CycloneVHMachine.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,59 +0,0 @@
-#ifndef CYCLONEVHMACHINE_H
-#define	CYCLONEVHMACHINE_H
-
-/*
- *  Copyright (C) 2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(cyclonevh)
-
-
-#include "Component.h"
-
-/**
- * \brief A template for creating a "cyclonevh" Component.
- *
- * Note: This class does not inherit from the Component class.
- */
-class CycloneVHMachine
-{
-public:
-	/**
-	 * \brief Creates a "cyclonevh" Component tree.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	/**
-	 * \brief Gets a Component attribute value.
-	 */
-	static string GetAttribute(const string& attributeName);
-
-private:
-	CycloneVHMachine();
-};
-
-
-#endif	// CYCLONEVHMACHINE_H
diff -Nru gxemul-0.6.2/src/include/components/DummyComponent.h gxemul-0.7.0+dfsg/src/include/components/DummyComponent.h
--- gxemul-0.6.2/src/include/components/DummyComponent.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/DummyComponent.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,72 +0,0 @@
-#ifndef DUMMYCOMPONENT_H
-#define	DUMMYCOMPONENT_H
-
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(dummy)
-
-
-#include "Component.h"
-
-#include "UnitTest.h"
-
-
-/**
- * \brief A dummy Component, for unit testing purposes.
- */
-class DummyComponent
-	: public Component
-	, public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs a DummyComponent.
-	 */
-	DummyComponent(string className = "dummy");
-
-	/**
-	 * \brief Creates a DummyComponent.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	/**
-	 * \brief Get attribute information about the DummyComponent class.
-	 *
-	 * @param attributeName The attribute name.
-	 * @return A string representing the attribute value.
-	 */
-	static string GetAttribute(const string& attributeName);
-
-
-	/********************************************************************/
-public:
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// DUMMYCOMPONENT_H
diff -Nru gxemul-0.6.2/src/include/components/HP700RXMachine.h gxemul-0.7.0+dfsg/src/include/components/HP700RXMachine.h
--- gxemul-0.6.2/src/include/components/HP700RXMachine.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/HP700RXMachine.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,60 +0,0 @@
-#ifndef HP700RXMACHINE_H
-#define HP700RXMACHINE_H
-
-/*
- *  Copyright (C) 2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(hp700rx)
-
-
-#include "Component.h"
-
-/**
- * \brief A template for creating a "hp700rx" Component.
- *
- * Note: This class does not inherit from the Component class.
- */
-class HP700RXMachine
-{
-public:
-	/**
-	 * \brief Creates a "hp700rx" Component tree.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	/**
-	 * \brief Gets a Component attribute value.
-	 */
-	static string GetAttribute(const string& attributeName);
-
-private:
-	HP700RXMachine();
-};
-
-
-#endif	// HP700RXMACHINE_H
-
diff -Nru gxemul-0.6.2/src/include/components/I960_CPUComponent.h gxemul-0.7.0+dfsg/src/include/components/I960_CPUComponent.h
--- gxemul-0.6.2/src/include/components/I960_CPUComponent.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/I960_CPUComponent.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,153 +0,0 @@
-#ifndef I960_CPUCOMPONENT_H
-#define	I960_CPUCOMPONENT_H
-
-/*
- *  Copyright (C) 2018-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(i960_cpu)
-
-
-#include "CPUDyntransComponent.h"
-
-
-#define	N_I960_REGS		32
-#define	N_I960_SFRS		32
-
-
-/*
-Register conventions according to
-https://people.cs.clemson.edu/~mark/subroutines/i960.html
-*/
-
-static const char* i960_regnames[N_I960_REGS] = {
-	"pfp",		// r0 = previous frame pointer
-	"sp",		// r1 = stack pointer
-	"rip",		// r2 = return instruction pointer
-	"r3", "r4", "r5", "r6", "r7",
-	"r8", "r9", "r10", "r11", "r12",
-	"r13", "r14", "r15",
-
-	"g0", "g1", "g2", "g3",	// parameters 0-3; return words 0-3
-	"g4", "g5", "g6", "g7", // parameters 4-7; temporaries
-	"g8", "g9", "g10", "g11", "g12",	// preserved accross call
-	"g13",		// structure return pointer
-	"g14",		// argument block pointer; leaf return address (HW)
-	"fp" 		// g15 = frame pointer (16-byte aligned HW)
-};
-
-#define	I960_G0		16	// offset to first parameter register
-
-
-/***********************************************************************/
-
-
-/**
- * \brief A Component representing an Intel i960 processor.
- */
-class I960_CPUComponent
-	: public CPUDyntransComponent
-{
-public:
-	/**
-	 * \brief Constructs a I960_CPUComponent.
-	 */
-	I960_CPUComponent();
-
-	/**
-	 * \brief Creates a I960_CPUComponent.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	static string GetAttribute(const string& attributeName);
-
-	virtual void ResetState();
-
-	virtual bool PreRunCheckForComponent(GXemul* gxemul);
-
-	virtual size_t DisassembleInstruction(uint64_t vaddr, vector<string>& result);
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-protected:
-	virtual bool CheckVariableWrite(StateVariable& var, const string& oldValue);
-
-	virtual bool VirtualToPhysical(uint64_t vaddr, uint64_t& paddr, bool& writable);
-
-	virtual string VirtualAddressAsString(uint64_t vaddr)
-	{
-		stringstream ss;
-		ss.flags(std::ios::hex | std::ios::showbase | std::ios::right);
-		ss << (uint32_t)vaddr;
-		return ss.str();
-	}
-
-	virtual uint64_t PCtoInstructionAddress(uint64_t pc);
-
-	virtual int FunctionTraceArgumentCount();
-	virtual int64_t FunctionTraceArgument(int n);
-	virtual bool FunctionTraceReturnImpl(int64_t& retval);
-
-	virtual int GetDyntransICshift() const;
-	virtual void (*GetDyntransToBeTranslated())(CPUDyntransComponent*, DyntransIC*);
-
-	virtual void ShowRegisters(GXemul* gxemul, const vector<string>& arguments) const;
-
-private:
-	DECLARE_DYNTRANS_INSTR(b);
-	DECLARE_DYNTRANS_INSTR(lda_displacement);
-
-	DECLARE_DYNTRANS_INSTR(mov_lit_reg);
-	DECLARE_DYNTRANS_INSTR(mov_reg_reg);
-
-	DECLARE_DYNTRANS_INSTR(sysctl);
-
-	void Translate(uint32_t iword, uint32_t iword2, struct DyntransIC* ic);
-	DECLARE_DYNTRANS_INSTR(ToBeTranslated);
-
-private:
-	/*
-	 * State:
-	 */
-	string		m_model;
-
-	uint32_t	m_r[N_I960_REGS];	// r and g registers
-
-	// NOTE: The i960 "ip" register is m_pc.
-
-	uint32_t	m_i960_ac;		// Arithmetic control
-	uint32_t	m_i960_pc;		// Process control
-	uint32_t	m_i960_tc;		// Trace control
-
-	uint32_t	m_nr_of_valid_sfrs;	// depends on model
-	uint32_t	m_sfr[N_I960_SFRS];
-};
-
-
-#endif	// I960_CPUCOMPONENT_H
diff -Nru gxemul-0.6.2/src/include/components/M88K_CPUComponent.h gxemul-0.7.0+dfsg/src/include/components/M88K_CPUComponent.h
--- gxemul-0.6.2/src/include/components/M88K_CPUComponent.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/M88K_CPUComponent.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,462 +0,0 @@
-#ifndef M88K_CPUCOMPONENT_H
-#define	M88K_CPUCOMPONENT_H
-
-/*
- *  Copyright (C) 2009-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(m88k_cpu)
-
-
-#include "CPUDyntransComponent.h"
-
-#include "thirdparty/m88k_psl.h"
-
-
-/*  M88K CPU types:  */
-struct m88k_cpu_type_def {
-	const char	*name;
-	int		type;
-	uint32_t	pid;
-};
-
-#define M88K_PID(arn,vn) ((arn << M88K_ARN_SHIFT) | (vn << M88K_VN_SHIFT))
-
-#define	M88K_CPU_TYPE_DEFS				{	\
-	{ "88100", 88100, M88K_PID(M88K_ARN_88100,3) },		\
-	{ "88110", 88110, M88K_PID(M88K_ARN_88110,0) },		\
-	{ NULL,        0, 0			     }		\
-	}
-
-/*
- * Opcode names:
- */
-#define	M88K_OPCODE_NAMES {						\
-	"xmem.bu",  "xmem",     "ld.hu",    "ld.bu",			\
-	"ld.d",     "ld",       "ld.h",     "ld.b",			\
-	"st.d",     "st",       "st.h",     "st.b",			\
-	"opcode0c", "opcode0d", "opcode0e", "opcode0f",			\
-	"and",      "and.u",    "mask",     "mask.u",			\
-	"xor",      "xor.u",    "or",       "or.u",			\
-	"addu",     "subu",     "divu",     "mulu",			\
-	"add",      "sub",      "div",      "cmp",			\
-	"c(multi)", "f(multi)", "opcode22", "opcode23",			\
-	"opcode24", "opcode25", "opcode26", "opcode27",			\
-	"opcode28", "opcode29", "opcode2a", "opcode2b",			\
-	"opcode2c", "opcode2d", "opcode2e", "opcode2f",			\
-	"br",       "br.n",     "bsr",      "bsr.n",			\
-	"bb0",      "bb0.n",    "bb1",      "bb1.n",			\
-	"opcode38", "opcode39", "bcnd",     "bcnd.n",			\
-	"opcode3c", "3(multi)", "tbnd",     "opcode3f" }
-
-#define	M88K_3C_OPCODE_NAMES {						\
-	"opcode3c_00", "opcode3c_01", "opcode3c_02", "opcode3c_03",	\
-	"opcode3c_04", "opcode3c_05", "opcode3c_06", "opcode3c_07",	\
-	"opcode3c_08", "opcode3c_09", "opcode3c_0a", "opcode3c_0b",	\
-	"opcode3c_0c", "opcode3c_0d", "opcode3c_0e", "opcode3c_0f",	\
-	"opcode3c_10", "opcode3c_11", "opcode3c_12", "opcode3c_13",	\
-	"opcode3c_14", "opcode3c_15", "opcode3c_16", "opcode3c_17",	\
-	"opcode3c_18", "opcode3c_19", "opcode3c_1a", "opcode3c_1b",	\
-	"opcode3c_1c", "opcode3c_1d", "opcode3c_1e", "opcode3c_1f",	\
-	"clr",         "opcode3c_21", "set",         "opcode3c_23",	\
-	"ext",         "opcode3c_25", "extu",        "opcode3c_27",	\
-	"mak",         "opcode3c_29", "rot",         "opcode3c_2b",	\
-	"opcode3c_2c", "opcode3c_2d", "opcode3c_2e", "opcode3c_2f",	\
-	"opcode3c_30", "opcode3c_31", "opcode3c_32", "opcode3c_33",	\
-	"tb0",         "opcode3c_35", "tb1",         "opcode3c_37",	\
-	"opcode3c_38", "opcode3c_39", "opcode3c_3a", "opcode3c_3b",	\
-	"opcode3c_3c", "opcode3c_3d", "opcode3c_3e", "opcode3c_3f" }
-
-#define	M88K_3D_OPCODE_NAMES {						\
-	"opcode3d_00", "opcode3d_01", "opcode3d_02", "opcode3d_03",	\
-	"opcode3d_04", "opcode3d_05", "opcode3d_06", "opcode3d_07",	\
-	"opcode3d_08", "opcode3d_09", "opcode3d_0a", "opcode3d_0b",	\
-	"opcode3d_0c", "opcode3d_0d", "opcode3d_0e", "opcode3d_0f",	\
-	"opcode3d_10", "opcode3d_11", "opcode3d_12", "opcode3d_13",	\
-	"opcode3d_14", "opcode3d_15", "opcode3d_16", "opcode3d_17",	\
-	"opcode3d_18", "opcode3d_19", "opcode3d_1a", "opcode3d_1b",	\
-	"opcode3d_1c", "opcode3d_1d", "opcode3d_1e", "opcode3d_1f",	\
-	"opcode3d_20", "opcode3d_21", "opcode3d_22", "opcode3d_23",	\
-	"opcode3d_24", "opcode3d_25", "opcode3d_26", "opcode3d_27",	\
-	"opcode3d_28", "opcode3d_29", "opcode3d_2a", "opcode3d_2b",	\
-	"opcode3d_2c", "opcode3d_2d", "opcode3d_2e", "opcode3d_2f",	\
-	"opcode3d_30", "opcode3d_31", "opcode3d_32", "opcode3d_33",	\
-	"opcode3d_34", "opcode3d_35", "opcode3d_36", "opcode3d_37",	\
-	"opcode3d_38", "opcode3d_39", "opcode3d_3a", "opcode3d_3b",	\
-	"opcode3d_3c", "opcode3d_3d", "opcode3d_3e", "opcode3d_3f",	\
-									\
-	"and",         "opcode3d_41", "opcode3d_42", "opcode3d_43",	\
-	"and.c",       "opcode3d_45", "opcode3d_46", "opcode3d_47",	\
-	"opcode3d_48", "opcode3d_49", "opcode3d_4a", "opcode3d_4b",	\
-	"opcode3d_4c", "opcode3d_4d", "opcode3d_4e", "opcode3d_4f",	\
-	"xor",         "opcode3d_51", "opcode3d_52", "opcode3d_53",	\
-	"xor.c",       "opcode3d_55", "opcode3d_56", "opcode3d_57",	\
-	"or",          "opcode3d_59", "opcode3d_5a", "opcode3d_5b",	\
-	"or.c",        "opcode3d_5d", "opcode3d_5e", "opcode3d_5f",	\
-	"addu",        "addu.co",     "addu.ci",     "addu.cio",	\
-	"subu",        "subu.co",     "subu.ci",     "subu.cio",	\
-	"divu",        "divu.d",      "opcode3d_6a", "opcode3d_6b",	\
-	"mul",         "mulu.d",      "muls",        "opcode3d_6f",	\
-	"add",         "add.co",      "add.ci",      "add.cio", 	\
-	"sub",         "sub.co",      "sub.ci",      "sub.cio",		\
-	"div",         "opcode3d_79", "opcode3d_7a", "opcode3d_7b",	\
-	"cmp",         "opcode3d_7d", "opcode3d_7e", "opcode3d_7f",	\
-									\
-	"clr",         "opcode3d_81", "opcode3d_82", "opcode3d_83",	\
-	"opcode3d_84", "opcode3d_85", "opcode3d_86", "opcode3d_87",	\
-	"set",         "opcode3d_89", "opcode3d_8a", "opcode3d_8b",	\
-	"opcode3d_8c", "opcode3d_8d", "opcode3d_8e", "opcode3d_8f",	\
-	"ext",         "opcode3d_91", "opcode3d_92", "opcode3d_93",	\
-	"opcode3d_94", "opcode3d_95", "opcode3d_96", "opcode3d_97",	\
-	"extu",        "opcode3d_99", "opcode3d_9a", "opcode3d_9b",	\
-	"opcode3d_9c", "opcode3d_9d", "opcode3d_9e", "opcode3d_9f",	\
-	"mak",         "opcode3d_a1", "opcode3d_a2", "opcode3d_a3",	\
-	"opcode3d_a4", "opcode3d_a5", "opcode3d_a6", "opcode3d_a7",	\
-	"rot",         "opcode3d_a9", "opcode3d_aa", "opcode3d_ab",	\
-	"opcode3d_ac", "opcode3d_ad", "opcode3d_ae", "opcode3d_af",	\
-	"opcode3d_b0", "opcode3d_b1", "opcode3d_b2", "opcode3d_b3",	\
-	"opcode3d_b4", "opcode3d_b5", "opcode3d_b6", "opcode3d_b7",	\
-	"opcode3d_b8", "opcode3d_b9", "opcode3d_ba", "opcode3d_bb",	\
-	"opcode3d_bc", "opcode3d_bd", "opcode3d_be", "opcode3d_bf",	\
-									\
-	"jmp",         "opcode3d_c1", "opcode3d_c2", "opcode3d_c3",	\
-	"jmp.n",       "opcode3d_c5", "opcode3d_c6", "opcode3d_c7",	\
-	"jsr",         "opcode3d_c9", "opcode3d_ca", "opcode3d_cb",	\
-	"jsr.n",       "opcode3d_cd", "opcode3d_ce", "opcode3d_cf",	\
-	"opcode3d_d0", "opcode3d_d1", "opcode3d_d2", "opcode3d_d3",	\
-	"opcode3d_d4", "opcode3d_d5", "opcode3d_d6", "opcode3d_d7",	\
-	"opcode3d_d8", "opcode3d_d9", "opcode3d_da", "opcode3d_db",	\
-	"opcode3d_dc", "opcode3d_dd", "opcode3d_de", "opcode3d_df",	\
-	"opcode3d_e0", "opcode3d_e1", "opcode3d_e2", "opcode3d_e3",	\
-	"opcode3d_e4", "opcode3d_e5", "opcode3d_e6", "opcode3d_e7",	\
-	"ff1",         "opcode3d_e9", "opcode3d_ea", "opcode3d_eb",	\
-	"ff0",         "opcode3d_ed", "opcode3d_ee", "opcode3d_ef",	\
-	"opcode3d_f0", "opcode3d_f1", "opcode3d_f2", "opcode3d_f3",	\
-	"opcode3d_f4", "opcode3d_f5", "opcode3d_f6", "opcode3d_f7",	\
-	"tbnd",        "opcode3d_f9", "opcode3d_fa", "opcode3d_fb",	\
-	"opcode3d_fc", "opcode3d_fd", "opcode3d_fe", "opcode3d_ff" }
-
-/*  Control register names:  */
-#define	N_M88K_CONTROL_REGS	64
-#define	M88K_CR_NAMES	{						\
-	"PID",  "PSR",  "EPSR", "SSBR",		/*   0 ..  3  */	\
-	"SXIP", "SNIP", "SFIP", "VBR",		/*   4 ..  7  */	\
-	"DMT0", "DMD0", "DMA0", "DMT1",		/*   8 .. 11  */	\
-	"DMD1", "DMA1", "DMT2", "DMD2",		/*  12 .. 15  */	\
-	"DMA2", "SR0",  "SR1",  "SR2",		/*  16 .. 19  */	\
-	"SR3",  "CR21", "CR22", "CR23",		/*  20 .. 23  */	\
-	"CR24", "CR25", "CR26", "CR27",		/*  24 .. 27  */	\
-	"CR28", "CR29", "CR30", "CR31",		/*  28 .. 31  */	\
-	"CR32", "CR33", "CR34", "CR35",		/*  32 .. 35  */	\
-	"CR36", "CR37", "CR38", "CR39",		/*  36 .. 39  */	\
-	"CR40", "CR41", "CR42", "CR43",		/*  40 .. 43  */	\
-	"CR44", "CR45", "CR46", "CR47",		/*  44 .. 47  */	\
-	"CR48", "CR49", "CR50", "CR51",		/*  48 .. 51  */	\
-	"CR52", "CR53", "CR54", "CR55",		/*  52 .. 55  */	\
-	"CR56", "CR57", "CR58", "CR59",		/*  56 .. 59  */	\
-	"CR60", "CR61", "CR62", "CR63"		/*  60 .. 63  */	}
-
-#define M88K_CR_PID	0
-#define M88K_CR_PSR     1 
-#define M88K_CR_EPSR    2 
-#define M88K_CR_SSBR    3 
-#define M88K_CR_SXIP    4 
-#define M88K_CR_SNIP    5 
-#define M88K_CR_SFIP    6 
-#define M88K_CR_VBR     7 
-#define M88K_CR_DMT0    8 
-#define M88K_CR_DMD0    9 
-#define M88K_CR_DMA0    10
-#define M88K_CR_DMT1    11
-#define M88K_CR_DMD1    12
-#define M88K_CR_DMA1    13
-#define M88K_CR_DMT2    14
-#define M88K_CR_DMD2    15
-#define M88K_CR_DMA2    16
-#define M88K_CR_SR0     17
-#define M88K_CR_SR1     18
-#define M88K_CR_SR2     19
-#define M88K_CR_SR3     20
-
-/*  MVME197 extended control registers:  */
-#define	M88K_CR_NAMES_197	{					\
-	"PID",  "PSR",  "EPSR", "SSBR",		/*   0 ..  3  */	\
-	"EXIP", "ENIP", "SFIP", "VBR",		/*   4 ..  7  */	\
-	"DMT0", "DMD0", "DMA0", "DMT1",		/*   8 .. 11  */	\
-	"DMD1", "DMA1", "DMT2", "DMD2",		/*  12 .. 15  */	\
-	"SRX", "SR0",  "SR1",  "SR2",		/*  16 .. 19  */	\
-	"SR3",  "CR21", "CR22", "CR23",		/*  20 .. 23  */	\
-	"CR24", "ICMD", "ICTL", "ISAR",		/*  24 .. 27  */	\
-	"ISAP", "IUAP", "IIR",  "IBP",		/*  28 .. 31  */	\
-	"IPPU", "IPPL", "ISR",  "ILAR",		/*  32 .. 35  */	\
-	"IPAR", "CR37", "CR38", "CR39",		/*  36 .. 39  */	\
-	"DCMD", "DCTL", "DSAR", "DSAP",		/*  40 .. 43  */	\
-	"DUAP", "DIR",  "DBP",  "DPPU",		/*  44 .. 47  */	\
-	"DPPL", "DSR",  "DLAR", "DPAR",		/*  48 .. 51  */	\
-	"CR52", "CR53", "CR54", "CR55",		/*  52 .. 55  */	\
-	"CR56", "CR57", "CR58", "CR59",		/*  56 .. 59  */	\
-	"CR60", "CR61", "CR62", "CR63"		/*  60 .. 63  */	}
-
-#define M88K_CR_EXIP    4
-#define M88K_CR_ENIP    5
-#define M88K_CR_SRX     16
-#define M88K_CR_ICMD    25
-#define M88K_CR_ICTL    26
-#define M88K_CR_ISAR    27
-#define M88K_CR_ISAP    28
-#define M88K_CR_IUAP    29
-#define M88K_CR_IIR     30
-#define M88K_CR_IBP     31
-#define M88K_CR_IPPU    32
-#define M88K_CR_IPPL    33
-#define M88K_CR_ISR     34
-#define M88K_CR_ILAR    35
-#define M88K_CR_IPAR    36
-#define M88K_CR_DCMD    40
-#define M88K_CR_DCTL    41
-#define M88K_CR_DSAR    42
-#define M88K_CR_DSAP    43
-#define M88K_CR_DUAP    44
-#define M88K_CR_DIR     45
-#define M88K_CR_DBP     46
-#define M88K_CR_DPPU    47
-#define M88K_CR_DPPL    48
-#define M88K_CR_DSR     49
-#define M88K_CR_DLAR    50
-#define M88K_CR_DPAR    51
-
-
-#define	N_M88K_FPU_CONTROL_REGS		64
-
-#define M88K_FPCR_FPECR		0
-#define	M88K_FPECR_FDVZ			(1 << 3)
-#define	M88K_FPECR_FUNIMP		(1 << 6)
-/*  ... TODO: more  */
-
-// Dyntrans:
-#define	M88K_INSTR_ALIGNMENT_SHIFT	2
-#define	M88K_IC_ENTRIES_PER_PAGE	1024	// always 4 KB pages
-
-// M88K registers:
-#define	N_M88K_REGS		32
-#define	M88K_ZERO_REG		0	// r0: always zero
-#define	M88K_RETURN_REG		1	// r1: the return address on function calls
-#define	M88K_RETURN_VALUE_REG	2	// r2: the return value, from function calls
-#define	M88K_FIRST_ARG_REG	2	// r2..r9: eight standard arguments to functions
-#define	M88K_STACKPOINTER_REG	31	// r31: commonly used as stack pointer
-
-#define	M88K_CMP_HS	0x00000800
-#define	M88K_CMP_LO	0x00000400
-#define	M88K_CMP_LS	0x00000200
-#define	M88K_CMP_HI	0x00000100
-#define	M88K_CMP_GE	0x00000080
-#define	M88K_CMP_LT	0x00000040
-#define	M88K_CMP_LE	0x00000020
-#define	M88K_CMP_GT	0x00000010
-#define	M88K_CMP_NE	0x00000008
-#define	M88K_CMP_EQ	0x00000004
-
-/*  Exception numbers:  */
-#define	M88K_EXCEPTION_RESET				0
-#define	M88K_EXCEPTION_INTERRUPT			1
-#define	M88K_EXCEPTION_INSTRUCTION_ACCESS		2
-#define	M88K_EXCEPTION_DATA_ACCESS			3
-#define	M88K_EXCEPTION_MISALIGNED_ACCESS		4
-#define	M88K_EXCEPTION_UNIMPLEMENTED_OPCODE		5
-#define	M88K_EXCEPTION_PRIVILEGE_VIOLATION		6
-#define	M88K_EXCEPTION_BOUNDS_CHECK_VIOLATION		7
-#define	M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE		8
-#define	M88K_EXCEPTION_INTEGER_OVERFLOW			9
-#define	M88K_EXCEPTION_ERROR				10
-#define	M88K_EXCEPTION_SFU1_PRECISE			114
-#define	M88K_EXCEPTION_SFU1_IMPRECISE			115
-#define	M88K_EXCEPTION_USER_TRAPS_START			128
-
-
-/*
- *  GXemul-specific instructions:
- */
-
-/*  A reserved/unimplemented instruction, used for PROM calls:  */
-#define	M88K_PROM_INSTR			0xf400fc92
-
-/*  An instruction which aborts before doing anything:  */
-#define	M88K_FAIL_EARLY_INSTR		0xf400fc93
-
-/*  An instruction which aborts after increasing r1:  */
-#define	M88K_FAIL_LATE_INSTR		0xf400fc94
-
-
-/*
- *  M88200/88204 CMMU:
- */
-
-#define	MAX_M8820X_CMMUS		8
-#define	M8820X_LENGTH			0x1000
-#define	N_M88200_BATC_REGS		10
-#define	N_M88200_PATC_ENTRIES		56
-#define	M8820X_PATC_SUPERVISOR_BIT	0x00000001
-
-struct m8820x_cmmu {
-	uint32_t	reg[M8820X_LENGTH / sizeof(uint32_t)];
-	uint32_t	batc[N_M88200_BATC_REGS];
-	uint32_t	patc_v_and_control[N_M88200_PATC_ENTRIES];
-	uint32_t	patc_p_and_supervisorbit[N_M88200_PATC_ENTRIES];
-	int		patc_update_index;
-};
-
-
-
-/***********************************************************************/
-
-/**
- * \brief A Component representing a Motorola 88000 processor.
- *
- * The only two implementations there were of the 88K architecture were
- * 88100 and 88110. GXemul only supports 88100 emulation so far.
- */
-class M88K_CPUComponent
-	: public CPUDyntransComponent
-{
-public:
-	/**
-	 * \brief Constructs a M88K_CPUComponent.
-	 */
-	M88K_CPUComponent();
-
-	/**
-	 * \brief Creates a M88K_CPUComponent.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	static string GetAttribute(const string& attributeName);
-
-	virtual void ResetState();
-
-	virtual bool PreRunCheckForComponent(GXemul* gxemul);
-
-	virtual size_t DisassembleInstruction(uint64_t vaddr, vector<string>& result);
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-protected:
-	virtual bool CheckVariableWrite(StateVariable& var, const string& oldValue);
-
-	virtual bool VirtualToPhysical(uint64_t vaddr, uint64_t& paddr,
-	    bool& writable);
-
-	virtual int FunctionTraceArgumentCount() { return 8; }
-	virtual int64_t FunctionTraceArgument(int n) { return m_r[M88K_FIRST_ARG_REG + n]; }
-	virtual bool FunctionTraceReturnImpl(int64_t& retval) { retval = m_r[M88K_RETURN_VALUE_REG]; return true; }
-
-	virtual int GetDyntransICshift() const;
-	virtual DyntransIC_t GetDyntransToBeTranslated();
-
-	virtual void ShowRegisters(GXemul* gxemul, const vector<string>& arguments) const;
-
-private:
-	void Exception(int vector, int is_trap);
-
-	void stcr(int cr, uint32_t value, bool is_rte);
-
-	void m88k_cmp(struct DyntransIC *ic, uint32_t y);
-	void m88k_extu(struct DyntransIC *ic, int w, int o);
-	void m88k_ext(struct DyntransIC *ic, int w, int o);
-	void m88k_mak(struct DyntransIC *ic, int w, int o);
-
-	DECLARE_DYNTRANS_INSTR(cmp);
-	DECLARE_DYNTRANS_INSTR(cmp_imm);
-	DECLARE_DYNTRANS_INSTR(extu);
-	DECLARE_DYNTRANS_INSTR(extu_imm);
-	DECLARE_DYNTRANS_INSTR(ext);
-	DECLARE_DYNTRANS_INSTR(ext_imm);
-	DECLARE_DYNTRANS_INSTR(mak);
-	DECLARE_DYNTRANS_INSTR(mak_imm);
-	DECLARE_DYNTRANS_INSTR(divu_imm);
-	DECLARE_DYNTRANS_INSTR(mulu_imm);
-	DECLARE_DYNTRANS_INSTR(bsr);
-	DECLARE_DYNTRANS_INSTR(bsr_samepage);
-	DECLARE_DYNTRANS_INSTR(bsr_functioncalltrace);
-	DECLARE_DYNTRANS_INSTR(bsr_n);
-	DECLARE_DYNTRANS_INSTR(bsr_n_functioncalltrace);
-	DECLARE_DYNTRANS_INSTR(bsr_n_functioncalltrace_singlestep);
-	template<bool n, int op, bool singlestep> static void instr_bcnd(CPUDyntransComponent* cpubase, DyntransIC* ic);
-	template<bool one, bool samepage> static void instr_bb(CPUDyntransComponent* cpubase, DyntransIC* ic);
-	template<bool one> static void instr_bb_n(CPUDyntransComponent* cpubase, DyntransIC* ic);
-	template<bool one> static void instr_bb_n_singlestep(CPUDyntransComponent* cpubase, DyntransIC* ic);
-	DECLARE_DYNTRANS_INSTR(jmp);
-	DECLARE_DYNTRANS_INSTR(jmp_n);
-	DECLARE_DYNTRANS_INSTR(jmp_n_functioncalltrace);
-	DECLARE_DYNTRANS_INSTR(jmp_n_functioncalltrace_singlestep);
-	DECLARE_DYNTRANS_INSTR(ldcr);
-	DECLARE_DYNTRANS_INSTR(stcr);
-	template<bool one> static void instr_tb(CPUDyntransComponent* cpubase, DyntransIC* ic);
-	template<bool store, typename T, bool doubleword, bool regofs, bool scaled, bool signedLoad> static void instr_loadstore(CPUDyntransComponent* cpubase, DyntransIC* ic);
-	template<int scaleFactor> static void instr_lda(CPUDyntransComponent* cpubase, DyntransIC* ic);
-
-	void Translate(uint32_t iword, struct DyntransIC* ic);
-	DECLARE_DYNTRANS_INSTR(ToBeTranslated);
-
-	// For unit tests:
-	DECLARE_DYNTRANS_INSTR(fail_early);
-	DECLARE_DYNTRANS_INSTR(fail_late);
-
-private:
-	/*
-	 * State:
-	 */
-	string			m_m88k_type;	// E.g. "88100"
-	uint32_t		m_initial_r31;	// Initial stack pointer.
-
-	// General-Purpose Registers:
-	//
-	// 32 (N_M88K_REGS) registers, plus one which is always zero. (This
-	// is to support st.d with d = r31. ld.d with d=r31 is converted to
-	// just ld.
-	uint32_t		m_r[N_M88K_REGS+1];
-
-	// Destination scratch register for non-nop instructions with d=r0.
-	// (Not serialized.)
-	uint32_t		m_zero_scratch;
-
-	// Control Registers:
-	uint32_t		m_cr[N_M88K_CONTROL_REGS];
-
-	// Floating Point Control registers:
-	uint32_t		m_fcr[N_M88K_FPU_CONTROL_REGS];
-
-	/*
-	 * Cached other state:
-	 */
-	m88k_cpu_type_def	m_type;	// based on m_m88k_type
-};
-
-
-#endif	// M88K_CPUCOMPONENT_H
-
diff -Nru gxemul-0.6.2/src/include/components/MachineComponent.h gxemul-0.7.0+dfsg/src/include/components/MachineComponent.h
--- gxemul-0.6.2/src/include/components/MachineComponent.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/MachineComponent.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,83 +0,0 @@
-#ifndef MACHINECOMPONENT_H
-#define	MACHINECOMPONENT_H
-
-/*
- *  Copyright (C) 2008-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(machine)
-
-
-#include "Component.h"
-
-#include "UnitTest.h"
-
-
-/**
- * \brief A Component representing a machine.
- *
- * A machine is, loosely defined, a box containing e.g.:
- * <ul>
- *	<li>processor(s)
- *	<li>RAM
- *	<li>ROM
- *	<li>interrupt controller
- *	<li>other busses, such as PCI busses (which in turn have things
- *		like network cards and graphics cards on them)
- *	<li>...
- * </ul>
- */
-class MachineComponent
-	: public Component
-	, public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs a MachineComponent.
-	 */
-	MachineComponent();
-
-	/**
-	 * \brief Creates a MachineComponent.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	/**
-	 * \brief Get attribute information about the MachineComponent class.
-	 *
-	 * @param attributeName The attribute name.
-	 * @return A string representing the attribute value.
-	 */
-	static string GetAttribute(const string& attributeName);
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// MACHINECOMPONENT_H
diff -Nru gxemul-0.6.2/src/include/components/MainbusComponent.h gxemul-0.7.0+dfsg/src/include/components/MainbusComponent.h
--- gxemul-0.6.2/src/include/components/MainbusComponent.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/MainbusComponent.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,123 +0,0 @@
-#ifndef MAINBUSCOMPONENT_H
-#define	MAINBUSCOMPONENT_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(mainbus)
-
-
-#include "AddressDataBus.h"
-#include "Component.h"
-
-#include "UnitTest.h"
-
-
-/**
- * \brief Main bus Component.
- *
- * An AddressDataBus Component which forwards reads and writes to
- * MemoryMappedComponent components (which also must implement the
- * AddressDataBus interface), e.g. the RAMComponent.
- */
-class MainbusComponent
-	: public Component
-	, public AddressDataBus
-	, public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs a MainbusComponent.
-	 */
-	MainbusComponent();
-
-	virtual ~MainbusComponent();
-
-	/**
-	 * \brief Creates a MainbusComponent.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	/**
-	 * \brief Get attribute information about the MainbusComponent class.
-	 *
-	 * @param attributeName The attribute name.
-	 * @return A string representing the attribute value.
-	 */
-	static string GetAttribute(const string& attributeName);
-
-	/**
-	 * \brief Returns the component's AddressDataBus interface.
-	 *
-	 * @return	A pointer to an AddressDataBus.
-	 */
-	virtual AddressDataBus* AsAddressDataBus();
-
-	/* Implementation of AddressDataBus: */
-	virtual void AddressSelect(uint64_t address);
-	virtual bool ReadData(uint8_t& data, Endianness endianness);
-	virtual bool ReadData(uint16_t& data, Endianness endianness);
-	virtual bool ReadData(uint32_t& data, Endianness endianness);
-	virtual bool ReadData(uint64_t& data, Endianness endianness);
-	virtual bool WriteData(const uint8_t& data, Endianness endianness);
-	virtual bool WriteData(const uint16_t& data, Endianness endianness);
-	virtual bool WriteData(const uint32_t& data, Endianness endianness);
-	virtual bool WriteData(const uint64_t& data, Endianness endianness);
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-protected:
-	virtual void FlushCachedStateForComponent();
-	virtual bool PreRunCheckForComponent(GXemul* gxemul);
-
-private:
-	bool MakeSureMemoryMapExists(GXemul* gxemul = NULL);
-
-private:
-	struct MemoryMapEntry {
-		uint64_t		base;
-		uint64_t		size;
-		uint64_t		addrMul;
-		AddressDataBus *	addressDataBus;
-	};
-
-	typedef vector<MemoryMapEntry> MemoryMap;
-	MemoryMap			m_memoryMap;
-	bool				m_memoryMapFailed;
-	bool				m_memoryMapValid;
-
-	// For the currently selected address:
-	AddressDataBus *	m_currentAddressDataBus;
-
-	// TODO: direct page access...
-};
-
-
-#endif	// MAINBUSCOMPONENT_H
diff -Nru gxemul-0.6.2/src/include/components/MemoryMappedComponent.h gxemul-0.7.0+dfsg/src/include/components/MemoryMappedComponent.h
--- gxemul-0.6.2/src/include/components/MemoryMappedComponent.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/MemoryMappedComponent.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,71 +0,0 @@
-#ifndef MEMORYMAPPEDCOMPONENT_H
-#define	MEMORYMAPPEDCOMPONENT_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// Note: not included in the component registry. This is simply a base-class.
-
-
-#include "Component.h"
-
-#include "UnitTest.h"
-
-
-/**
- * \brief A base-class for memory-mapped components.
- *
- * A memory-mapped component is a Component which is meant to be mapped
- * into a bus' address space. It has a <b>base offset</b> and a <b>size</b>,
- * which the bus sees. The bus then forwards only those read/write requests
- * to the memory-mapped component that are within that range.
- *
- * There is also an <b>address multiplicator</b>, to handle the common
- * case when a device has, say, N 8-bit registers, but is accessed using
- * memory-mapped addresses that are seen as N 32-bit registers. In this
- * example, the address multiplicator would be 4.
- */
-class MemoryMappedComponent
-	: public Component
-{
-public:
-	/**
-	 * \brief Constructs a MemoryMappedComponent.
-	 */
-	MemoryMappedComponent(const string& className, const string& visibleClassName);
-
-	string GenerateDetails() const;
-
-private:
-	// Variables common to all memory mapped components:
-	uint64_t	m_memoryMappedBase;
-	uint64_t	m_memoryMappedSize;
-	uint64_t	m_memoryMappedAddrMul;
-};
-
-
-#endif	// MEMORYMAPPEDCOMPONENT_H
diff -Nru gxemul-0.6.2/src/include/components/MVME187Machine.h gxemul-0.7.0+dfsg/src/include/components/MVME187Machine.h
--- gxemul-0.6.2/src/include/components/MVME187Machine.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/MVME187Machine.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,59 +0,0 @@
-#ifndef MVME187MACHINE_H
-#define	MVME187MACHINE_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(mvme187)
-
-
-#include "Component.h"
-
-/**
- * \brief A template for creating a MVME187 machine.
- *
- * Note: This class does not inherit from the Component class.
- */
-class MVME187Machine
-{
-public:
-	/**
-	 * \brief Creates a MVME187 Component tree.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	/**
-	 * \brief Gets a Component attribute value.
-	 */
-	static string GetAttribute(const string& attributeName);
-
-private:
-	MVME187Machine();
-};
-
-
-#endif	// MVME187MACHINE_H
diff -Nru gxemul-0.6.2/src/include/components/RAMComponent.h gxemul-0.7.0+dfsg/src/include/components/RAMComponent.h
--- gxemul-0.6.2/src/include/components/RAMComponent.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/RAMComponent.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,313 +0,0 @@
-#ifndef RAMCOMPONENT_H
-#define	RAMCOMPONENT_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(ram)
-
-
-#include "AddressDataBus.h"
-#include "MemoryMappedComponent.h"
-
-#include "UnitTest.h"
-
-#include <string.h>
-#include <iomanip>
-
-
-/**
- * \brief A Random Access Memory Component.
- *
- * RAM is emulated by allocating large blocks of host memory (e.g. 4 MB
- * per block), and simply forwarding all read and write requests to those
- * memory blocks.
- *
- * The host memory blocks are not allocated until they are actually written to.
- * Reading from uninitialized/unwritten emulated memory returns zeros. This
- * allows e.g. an emulated machine to have, say, 1 TB RAM, even if the host
- * only has 1 GB, as long as the emulated guest OS does not touch all of the
- * emulated memory.
- *
- * In addition, host memory blocks are allocated as anonymous zero-filled
- * memory using mmap(), so the blocks do not necessariliy use up host RAM
- * unless they are touched.
- *
- * Note 1: This class does <i>not</i> handle unaligned access. It is up to the
- * caller to make sure that e.g. ReadData(uint64_t&, Endianness) is only
- * called when the selected address is 64-bit aligned.
- *
- * (The reason for this is that different emulated components want different
- * semantics for unaligned access. For example, an x86 processor will
- * transparently allow unaligned access, most RISC processors will cause
- * an unaligned address exception, and some old ARM processors may even simply
- * ignore the lowest bits of the address!)
- *
- * Note 2: The RAM component's size and base offset are defined by state
- * variables in the MemoryMappedComponent base class.
- */
-class RAMComponent
-	: public MemoryMappedComponent
-	, public AddressDataBus
-	, public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs a RAMComponent.
-	 *
-	 * @param visibleClassName The visible class name. Defaults to
-	 *	"ram". Useful alternatives may be "rom" or
-	 *	"vram" for video ram.
-	 */
-	RAMComponent(const string& visibleClassName = "ram");
-
-	virtual ~RAMComponent();
-
-	/**
-	 * \brief Creates a RAMComponent.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	virtual void ResetState();
-
-	/**
-	 * \brief Get attribute information about the RAMComponent class.
-	 *
-	 * @param attributeName The attribute name.
-	 * @return A string representing the attribute value.
-	 */
-	static string GetAttribute(const string& attributeName);
-
-        virtual void GetMethodNames(vector<string>& names) const;
-
-	virtual bool MethodMayBeReexecutedWithoutArgs(const string& methodName) const;
-
-	virtual void ExecuteMethod(GXemul* gxemul,
-		const string& methodName,
-		const vector<string>& arguments);
-
-	/**
-	 * \brief Returns the component's AddressDataBus interface.
-	 *
-	 * @return	A pointer to an AddressDataBus.
-	 */
-	virtual AddressDataBus* AsAddressDataBus();
-
-	/* Implementation of AddressDataBus: */
-	virtual void AddressSelect(uint64_t address);
-	virtual bool ReadData(uint8_t& data, Endianness endianness);
-	virtual bool ReadData(uint16_t& data, Endianness endianness);
-	virtual bool ReadData(uint32_t& data, Endianness endianness);
-	virtual bool ReadData(uint64_t& data, Endianness endianness);
-	virtual bool WriteData(const uint8_t& data, Endianness endianness);
-	virtual bool WriteData(const uint16_t& data, Endianness endianness);
-	virtual bool WriteData(const uint32_t& data, Endianness endianness);
-	virtual bool WriteData(const uint64_t& data, Endianness endianness);
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-private:
-	void ReleaseAllBlocks();
-
-	void* AllocateBlock();
-
-	class RAMDataHandler : public CustomStateVariableHandler
-	{
-	public:
-		RAMDataHandler(RAMComponent& ram)
-			: m_ram(ram)
-		{
-		}
-		
-		virtual ~RAMDataHandler()
-		{
-		}
-	
-		virtual void Serialize(ostream& ss) const
-		{
-			for (size_t i=0; i<m_ram.m_memoryBlocks.size(); ++i)
-				if (m_ram.m_memoryBlocks[i] != NULL)
-					SerializeMemoryBlock(ss, i, m_ram.m_memoryBlocks[i]);
-
-			// End of data.
-			ss << ".";
-		}
-		
-		virtual bool Deserialize(const string& value)
-		{
-			m_ram.ReleaseAllBlocks();
-			
-			size_t p = 0;
-			size_t len = value.length();
-			const char *cstr = value.c_str();
-			
-			while (p < len) {
-				if (cstr[p] == '.') {
-					p++;
-					continue;
-				}
-
-				// xxxxxxxxxxxxxxxx:yyyyyyyy:data.
-				// where x = address in the RAM component,
-				// y = length of data in bytes.
-				// data = hex dump.
-
-				// Some margin... :)  Yuck. This is ugly.
-				if (p + 40 > len) {
-					std::cerr << "deserialize ram: internal error\n";
-					throw std::exception();
-				}
-
-				char s1[17];
-				char s2[9];
-				memcpy(s1, cstr + p, 16);
-				p += 17;
-				memcpy(s2, cstr + p, 8);
-				p += 9;
-				s1[16] = 0;
-				s2[8] = 0;
-				stringstream ss1;
-				ss1.flags(std::ios::hex);
-				ss1 << s1;
-				uint64_t addr;
-				ss1 >> addr;
-				stringstream ss2;
-				ss2.flags(std::ios::hex);
-				ss2 << s2;
-				uint32_t datalen;
-				ss2 >> datalen;
-				// p points to data.
-				if (p + 2*datalen < len) {
-					for (size_t i=0; i<datalen; i++) {
-						char c1 = cstr[p++];
-						char c2 = cstr[p++];
-						
-						if (c1 >= 'a' && c1 <= 'f')
-							c1 = (c1-'a') + 10;
-						else
-							c1 -= '0';
-
-						if (c2 >= 'a' && c2 <= 'f')
-							c2 = (c2-'a') + 10;
-						else
-							c2 -= '0';
-						
-						uint8_t b = c1*16 + c2;
-						
-						m_ram.AddressSelect(i + addr);
-						m_ram.WriteData(b, BigEndian);
-					}
-				} else {
-					std::cerr << "deserialize ram: internal error\n";
-					throw std::exception();
-				}
-				
-				if (cstr[p] != '.') {
-					std::cerr << "deserialize ram: internal error: no dot\n";
-					throw std::exception();
-				}
-			}
-			
-			return true;
-		}
-		
-		virtual void CopyValueFrom(CustomStateVariableHandler* other)
-		{
-			// NOTE/TODO: Not space efficient, but works for now.
-
-			stringstream ss;
-			other->Serialize(ss);
-			Deserialize(ss.str());
-		}
-
-	private:
-		void SerializeMemoryBlock(ostream& ss, size_t blockNr, void *block) const
-		{
-			const size_t rowSize = 1024;
-			uint64_t addr = blockNr << m_ram.m_blockSizeShift;
-			uint64_t addrWithinBlock = 0;
-
-			while (addrWithinBlock < m_ram.m_blockSize) {
-				uint8_t *data = (uint8_t*)block + addrWithinBlock;
-
-				bool allZeroes = true;
-				for (size_t i=0; i<rowSize; i++)
-					if (data[i] != 0x00) {
-						allZeroes = false;
-						break;
-					}
-
-				// Only output the row if it contains something
-				// which is non-zero.
-				if (!allZeroes)
-					SerializeRow(ss, addr, data, rowSize);
-
-				addrWithinBlock += rowSize;
-				addr += rowSize;
-			}
-		}
-
-		// NOTE/TODO: Not space efficient, but works for now.
-		void SerializeRow(ostream& ss, uint64_t addr, uint8_t* data, size_t rowSize) const
-		{
-			ss.flags(std::ios::hex);
-			ss << std::setw(16) << std::setfill('0') << addr << ":";
-			ss << std::setw(8) << std::setfill('0') << rowSize << ":";
-
-			for (size_t i=0; i<rowSize; i++)
-				ss << std::setw(2) << std::setfill('0') << (int)data[i];
-
-			ss << ".";
-		}
-
-	private:
-		RAMComponent& m_ram;
-	};
-
-private:
-	const size_t	m_blockSizeShift;// Host block size, in bit shift steps
-	const size_t	m_blockSize;	 // Host block size, in bytes
-
-	RAMDataHandler m_dataHandler;
-	
-	// State:
-	typedef vector<void *> BlockNrToMemoryBlockVector;
-	BlockNrToMemoryBlockVector	m_memoryBlocks;
-	bool				m_writeProtected;
-	uint64_t			m_lastDumpAddr;
-
-	// Cached/runtime state:
-	uint64_t	m_addressSelect;  // For AddressDataBus read/write
-	void *		m_selectedHostMemoryBlock;
-	size_t		m_selectedOffsetWithinBlock;
-};
-
-
-#endif	// RAMCOMPONENT_H
diff -Nru gxemul-0.6.2/src/include/components/RISCV_CPUComponent.h gxemul-0.7.0+dfsg/src/include/components/RISCV_CPUComponent.h
--- gxemul-0.6.2/src/include/components/RISCV_CPUComponent.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/RISCV_CPUComponent.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,146 +0,0 @@
-#ifndef RISCV_CPUCOMPONENT_H
-#define	RISCV_CPUCOMPONENT_H
-
-/*
- *  Copyright (C) 2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(riscv_cpu)
-
-#include <iomanip>
-#include "CPUDyntransComponent.h"
-
-
-// See https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf for
-// calling convention.
-
-#define	N_RISCV_XREGS		32
-
-static const char* RISCV_regnames[N_RISCV_XREGS] = {
-	"zero",			// x0 = always zero
-	"ra",			// x1 = return address		Caller save
-	"sp",			// x2 = stack pointer		Callee save
-	"gp",			// x3 = global pointer
-	"tp",			// x4 = thread pointer
-	"t0", "t1", "t2",	// x5..x7 = temporaries		Caller save
-	"fp" /* or s0 */,	// x8 = frame pointer		Callee save
-	"s1",			// x9 = saved register		Callee save
-	"a0", "a1",		// x10..x11 = arguments and return values	Caller save
-	"a2", "a3", "a4", "a5",	// x12..x17 = arguments		Caller save
-	"a6", "a7",
-	"s2", "s3", "s4", "s5",	// x18..x27 = saved registers	Callee save
-	"s6", "s7", "s8", "s9",
-	"s10", "s11",
-	"t3", "t4", "t5", "t6",	// x28..x31 = temporaries	Caller save
-};
-
-
-// Each 16-bit part of an instruction is called a "parcel".
-#define	RISCV_MAX_PARCELS	12
-
-
-#define	RISCV_EXTENSION_C	(1 << 1)
-#define	RISCV_EXTENSION_I	(1 << 2)
-
-
-/***********************************************************************/
-
-
-/**
- * \brief A Component representing a RISC-V processor.
- */
-class RISCV_CPUComponent
-	: public CPUDyntransComponent
-{
-public:
-	/**
-	 * \brief Constructs a RISCV_CPUComponent.
-	 */
-	RISCV_CPUComponent();
-
-	/**
-	 * \brief Creates a RISCV_CPUComponent.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	static string GetAttribute(const string& attributeName);
-
-	virtual void ResetState();
-
-	virtual bool PreRunCheckForComponent(GXemul* gxemul);
-
-	virtual size_t DisassembleInstruction(uint64_t vaddr, vector<string>& result);
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-protected:
-	virtual bool CheckVariableWrite(StateVariable& var, const string& oldValue);
-
-	virtual bool VirtualToPhysical(uint64_t vaddr, uint64_t& paddr, bool& writable);
-
-	virtual string VirtualAddressAsString(uint64_t vaddr)
-	{
-		stringstream ss;
-		ss.flags(std::ios::hex | std::ios::right);
-		ss << std::setfill('0') << std::setw(16) << (uint64_t)vaddr;
-		return ss.str();
-	}
-
-	virtual uint64_t PCtoInstructionAddress(uint64_t pc);
-
-	virtual int FunctionTraceArgumentCount();
-	virtual int64_t FunctionTraceArgument(int n);
-	virtual bool FunctionTraceReturnImpl(int64_t& retval);
-
-	virtual int GetDyntransICshift() const;
-	virtual void (*GetDyntransToBeTranslated())(CPUDyntransComponent*, DyntransIC*);
-
-	virtual void ShowRegisters(GXemul* gxemul, const vector<string>& arguments) const;
-
-private:
-	// TODO: Instructions.
-	// DECLARE_DYNTRANS_INSTR(b);
-	// DECLARE_DYNTRANS_INSTR(mov_lit_reg);
-
-	void Translate(uint16_t iwords[], int nparcels, struct DyntransIC* ic);
-	DECLARE_DYNTRANS_INSTR(ToBeTranslated);
-
-private:
-	/*
-	 * State:
-	 */
-	string		m_model;
-
-	uint64_t	m_extensions;
-
-	uint64_t	m_x[N_RISCV_XREGS];
-};
-
-
-#endif	// RISCV_CPUCOMPONENT_H
diff -Nru gxemul-0.6.2/src/include/components/RISCVvirtMachine.h gxemul-0.7.0+dfsg/src/include/components/RISCVvirtMachine.h
--- gxemul-0.6.2/src/include/components/RISCVvirtMachine.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/RISCVvirtMachine.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,59 +0,0 @@
-#ifndef RISCVVIRTMACHINE_H
-#define	RISCVVIRTMACHINE_H
-
-/*
- *  Copyright (C) 2019 Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(riscv-virt)
-
-
-#include "Component.h"
-
-/**
- * \brief A template for creating a "riscv-virt" Component.
- *
- * Note: This class does not inherit from the Component class.
- */
-class RISCVvirtMachine
-{
-public:
-	/**
-	 * \brief Creates a "riscv-virt" Component tree.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	/**
-	 * \brief Gets a Component attribute value.
-	 */
-	static string GetAttribute(const string& attributeName);
-
-private:
-	RISCVvirtMachine();
-};
-
-
-#endif	// RISCVVIRTMACHINE_H
diff -Nru gxemul-0.6.2/src/include/components/RootComponent.h gxemul-0.7.0+dfsg/src/include/components/RootComponent.h
--- gxemul-0.6.2/src/include/components/RootComponent.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/RootComponent.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,98 +0,0 @@
-#ifndef ROOTCOMPONENT_H
-#define	ROOTCOMPONENT_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-/*
- * Note: This is a special component, which cannot be created interactively
- * by the user.
- */
-
-#include "Component.h"
-
-#include "UnitTest.h"
-
-class GXemul;
-
-
-/**
- * \brief A Component which is the default root node in the configuration.
- *
- * This Component is mostly a dummy component, but it holds the 'step'
- * count for the entire emulation (inherited from Component), and the following
- * settings:
- *
- * <ul>
- *	<li>accuracy ("cycle" or "sloppy")
- * </ul>
- *
- * NOTE: A RootComponent is not registered in the component registry, and
- * can thus not be created interactively by the user at runtime.
- */
-class RootComponent
-	: public Component
-	, public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs a RootComponent.
-	 */
-	RootComponent(GXemul* owner = NULL);
-
-	virtual RootComponent* AsRootComponent()
-	{
-		return this;
-	}
-
-	virtual bool PreRunCheckForComponent(GXemul* gxemul);
-
-	GXemul* GetOwner()
-	{
-		return m_gxemul;
-	}
-
-	void SetOwner(GXemul* owner);
-
-
-	/********************************************************************/
-public:
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-protected:
-	virtual bool CheckVariableWrite(StateVariable& var, const string& oldValue);
-
-private:
-	// Pointer to owner (may be NULL):
-	GXemul*		m_gxemul;
-
-	// Model:
-	string		m_accuracy;
-};
-
-
-#endif	// ROOTCOMPONENT_H
diff -Nru gxemul-0.6.2/src/include/components/TestM88KMachine.h gxemul-0.7.0+dfsg/src/include/components/TestM88KMachine.h
--- gxemul-0.6.2/src/include/components/TestM88KMachine.h	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/components/TestM88KMachine.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,59 +0,0 @@
-#ifndef TESTM88KMACHINE_H
-#define	TESTM88KMACHINE_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-// COMPONENT(testm88k)
-
-
-#include "Component.h"
-
-/**
- * \brief A template for creating a "testm88k" Component.
- *
- * Note: This class does not inherit from the Component class.
- */
-class TestM88KMachine
-{
-public:
-	/**
-	 * \brief Creates a "testm88k" Component tree.
-	 */
-	static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
-
-	/**
-	 * \brief Gets a Component attribute value.
-	 */
-	static string GetAttribute(const string& attributeName);
-
-private:
-	TestM88KMachine();
-};
-
-
-#endif	// TESTM88KMACHINE_H
diff -Nru gxemul-0.6.2/src/include/console.h gxemul-0.7.0+dfsg/src/include/console.h
--- gxemul-0.6.2/src/include/console.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/console.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	CONSOLE_H
 
 /*
- *  Copyright (C) 2003-2010  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -38,16 +38,19 @@
 
 #define	CONSOLE_OUTPUT_ONLY	-1
 
+struct emul;
+
 void console_deinit_main(void);
 void console_sigcont(int x);
 void console_makeavail(int handle, char ch);
 int console_charavail(int handle);
+bool console_any_input_available(struct emul *emul);
 int console_readchar(int handle);
 void console_putchar(int handle, int ch);
 void console_flush(void);
-void console_mouse_coordinates(int x, int y, int fb_nr);
+void console_mouse_coordinate_update(int dx, int dy, int fb_nr);
 void console_mouse_button(int, int);
-void console_getmouse(int *x, int *y, int *buttons, int *fb_nr);
+void console_getmouse(int *dx, int *dy, int *buttons, int *fb_nr);
 void console_slave(const char *arg);
 int console_are_slaves_allowed(void);
 int console_warn_if_slaves_are_needed(int init);
diff -Nru gxemul-0.6.2/src/include/ConsoleUI.h gxemul-0.7.0+dfsg/src/include/ConsoleUI.h
--- gxemul-0.6.2/src/include/ConsoleUI.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/ConsoleUI.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,153 +0,0 @@
-#ifndef CONSOLEUI_H
-#define	CONSOLEUI_H
-
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <termios.h>
-
-#include "UI.h"
-
-
-/**
- * \brief Text-terminal based User Interface.
- */
-class ConsoleUI
-	: public UI
-{
-public:
-	/**
-	 * \brief Constructs a text console %UI instance.
-	 *
-	 * @param gxemul Pointer to the owning GXemul instance.
-	 */
-	ConsoleUI(GXemul *gxemul);
-
-	virtual ~ConsoleUI();
-
-	/**
-	 * \brief Initializes the terminal for blocking, non-echo I/O.
-	 */
-	virtual void Initialize();
-
-	/**
-	 * \brief Updates UI items. Not used for %ConsoleUI.
-	 */
-	virtual void UpdateUI();
-
-	/**
-	 * \brief Prints the text console startup banner.
-	 */
-	virtual void ShowStartupBanner();
-
-	/**
-	 * \brief Shows a debug message, by printing it to stdout.
-	 *
-	 * @param msg The message to show.
-	 */
-	virtual void ShowDebugMessage(const string& msg);
-	
-	/**
-	 * \brief Shows a debug message for a Component, by printing it to
-	 * stdout.
-	 *
-	 * See UI::ShowDebugMessage(Component*,const string&) for
-	 * a longer comment.
-	 *
-	 * @param component A pointer to the Component.
-	 * @param msg The message to show.
-	 */
-	virtual void ShowDebugMessage(Component* component, const string& msg);
-
-	/**
-	 * \brief Does nothing for the %ConsoleUI.
-	 *
-	 * @param command The command being executed.
-	 */
-	virtual void ShowCommandMessage(const string& command);
-
-	/**
-	 * \brief Shows a fatal error message, by printing it to stderr.
-	 *
-	 * @param msg The error message to show.
-	 */
-	virtual void FatalError(const string& msg);
-
-	/**
-	 * \brief Redisplays the interactive command input line.
-	 *
-	 * For the %ConsoleUI, this function displays a prompt ("GXemul> ")
-	 * followed by the input line, placing the cursor position at
-	 * the correct position on the input line.
-	 *
-	 * @param inputline The entire input line.
-	 * @param cursorPosition The current cursor position. 0 is at the
-	 *	leftmost position.
-	 */
-	virtual void RedisplayInputLine(const string& inputline,
-	    size_t cursorPosition);
-
-	/**
-	 * \brief Executed by the CommandInterpreter when a line has been
-	 * completed (with a newline).
-	 *
-	 * For the %ConsoleUI, this simply outputs a newline character.
-	 */
-	virtual void InputLineDone();
-
-	/**
-	 * \brief Runs the text console main loop.
-	 *
-	 * As long as the RunState is not Quitting:
-	 * <ul>
-	 *	<li>If an emulation is Running, the main loop lets the
-	 *		emulation run, until Ctrl-C is pressed.
-	 *	<li>Otherwise, if the RunState is Paused, the main loop shows
-	 *		a prompt and lets the user input commands.
-	 * </ul>
-	 */
-	virtual int MainLoop();
-
-	virtual void Shutdown();
-
-private:
-	/**
-	 * \brief Shows the %GXemul&gt; prompt, reads characters from stdin
-	 *	until a newline char, and executes the resulting command.
-	 *
-	 * This function is blocking.
-	 */
-	void ReadAndExecuteCommand();
-
-private:
-	bool		m_consoleIsInitialized;
-	struct termios	m_oldTermios;
-	struct termios	m_currentTermios;
-};
-
-
-#endif	// CONSOLEUI_H
diff -Nru gxemul-0.6.2/src/include/cpu_alpha.h gxemul-0.7.0+dfsg/src/include/cpu_alpha.h
--- gxemul-0.6.2/src/include/cpu_alpha.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/cpu_alpha.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	CPU_ALPHA_H
 
 /*
- *  Copyright (C) 2005-2011  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -190,7 +190,7 @@
 int alpha_run_instr(struct cpu *cpu);
 int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
 	unsigned char *data, size_t len, int writeflag, int cache_flags);
-int alpha_cpu_family_init(struct cpu_family *);
+void alpha_cpu_family_init(struct cpu_family *);
 
 /*  cpu_alpha_palcode.c:  */
 void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen);
diff -Nru gxemul-0.6.2/src/include/cpu_arm.h gxemul-0.7.0+dfsg/src/include/cpu_arm.h
--- gxemul-0.6.2/src/include/cpu_arm.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/cpu_arm.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	CPU_ARM_H
 
 /*
- *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -311,7 +311,7 @@
 void arm_save_register_bank(struct cpu *cpu);
 int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
 	unsigned char *data, size_t len, int writeflag, int cache_flags);
-int arm_cpu_family_init(struct cpu_family *);
+void arm_cpu_family_init(struct cpu_family *);
 
 /*  cpu_arm_coproc.c:  */
 void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
diff -Nru gxemul-0.6.2/src/include/cpu.h gxemul-0.7.0+dfsg/src/include/cpu.h
--- gxemul-0.6.2/src/include/cpu.h	2019-06-22 18:23:25.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/cpu.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	CPU_H
 
 /*
- *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -32,6 +32,7 @@
  */
 
 
+#include <stdbool.h>
 #include <sys/types.h>
 #include <inttypes.h>
 #include <sys/time.h>
@@ -72,7 +73,7 @@
 #define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype)  struct \
 	arch ## _instr_call {					\
 		void	(*f)(struct cpu *, struct arch ## _instr_call *); \
-		size_t	arg[ARCH ## _N_IC_ARGS];			\
+		uintptr_t arg[ARCH ## _N_IC_ARGS];			\
 	};								\
 									\
 	/*  Translation cache struct for each physical page:  */	\
@@ -228,12 +229,28 @@
 	struct arch ## _l2_64_table	*l1_64[1 << DYNTRANS_L1N];
 
 
-/*  Include all CPUs' header files here:  */
+/*  CPU architectures:  */
+#define	ARCH_ALPHA		1
+#define	ARCH_ARM		2
+#define	ARCH_I960		3
+#define	ARCH_M88K		4
+#define	ARCH_MIPS		5
+#define	ARCH_PPC		6
+#define	ARCH_RISCV		7
+#define	ARCH_SH			8
+
+/*
+ *  Include all CPUs' header files here. At the end of the
+ *  cpu struct there is a union of the architecture-specific
+ *  parts (cd).
+ */
 #include "cpu_alpha.h"
 #include "cpu_arm.h"
+#include "cpu_i960.h"
 #include "cpu_m88k.h"
 #include "cpu_mips.h"
 #include "cpu_ppc.h"
+#include "cpu_riscv.h"
 #include "cpu_sh.h"
 
 struct cpu;
@@ -251,10 +268,12 @@
  *  architecture-specific functions.
  *
  *  Except for the next and arch fields at the top, all fields in the
- *  cpu_family struct are filled in by ecah CPU family's init function.
+ *  cpu_family struct are filled in by each CPU family's init function.
  */
 struct cpu_family {
 	struct cpu_family	*next;
+
+	/*  E.g. ARCH_MIPS:  */
 	int			arch;
 
 	/*  Familty name, e.g. "MIPS", "Alpha" etc.  */
@@ -281,11 +300,10 @@
 				    int gprs, int coprocs);
 
 	/*  Dump generic CPU info in readable format.  */
-	void			(*dumpinfo)(struct cpu *cpu);
+	void			(*dumpinfo)(struct cpu *cpu, bool verbose);
 
-	/*  Dump TLB data for CPU id x.  */
-	void			(*tlbdump)(struct machine *m, int x,
-				    int rawflag);
+	/*  Dump TLB data for a CPU.  */
+	void			(*tlbdump)(struct cpu *cpu, int rawflag);
 
 	/*  Print architecture-specific function call arguments.
 	    (This is called for each function call, if running with -t.)  */
@@ -310,6 +328,8 @@
 #define	N_SAFE_DYNTRANS_LIMIT_SHIFT	14
 #define	N_SAFE_DYNTRANS_LIMIT	((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1)
 
+#define	N_DYNTRANS_IDLE_BREAK		N_SAFE_DYNTRANS_LIMIT
+
 #define	MAX_DYNTRANS_READAHEAD		128
 
 #define	DEFAULT_DYNTRANS_CACHE_SIZE	(96*1048576)
@@ -330,6 +350,9 @@
 	/*  Settings:  */
 	struct settings *settings;
 
+	/*  Contains the arch (e.g. ARCH_MIPS), and some function pointers.  */
+	struct cpu_family* cpu_family;
+
 	/*  CPU-specific name, e.g. "R2000", "21164PC", etc.  */
 	char		*name;
 
@@ -349,12 +372,12 @@
 	/*  0 for emulated 64-bit CPUs, 1 for 32-bit.  */
 	uint8_t		is_32bit;
 
-	/*  1 while running, 0 when paused/stopped.  */
-	uint8_t		running;
-
 	/*  See comment further up.  */
 	uint8_t		delay_slot;
 
+	/*  true while running, false when paused/stopped.  */
+	bool		running;
+
 	/*  0-based CPU id, in an emulated SMP system.  */
 	int		cpu_id;
 
@@ -389,6 +412,12 @@
 	int		trace_tree_depth;
 
 	/*
+	 *  If wants_to_idle is true, then N_DYNTRANS_IDLE_BREAK is assumed
+	 *  to have been added to n_translated_instructions and should
+	 *  thus be subtracted when the dyntrans loop exits. An attempt is
+	 *  then made to "idle the host", if all running CPUs in all
+	 *  machines want to idle at the same time.
+	 *
 	 *  If is_halted is true when an interrupt trap occurs, the pointer
 	 *  to the next instruction to execute will be the instruction
 	 *  following the halt instruction, not the halt instrucion itself.
@@ -397,8 +426,9 @@
 	 *  instructions per second, "idling" is printed instead. (The number
 	 *  of instrs per second when idling is meaningless anyway.)
 	 */
-	char		is_halted;
-	char		has_been_idling;
+	bool		wants_to_idle;
+	bool		is_halted;
+	bool		has_been_idling;
 
 	/*
 	 *  Dynamic translation:
@@ -442,9 +472,11 @@
 	union {
 		struct alpha_cpu      alpha;
 		struct arm_cpu        arm;
+		struct i960_cpu       i960;
 		struct m88k_cpu       m88k;
 		struct mips_cpu       mips;
 		struct ppc_cpu        ppc;
+		struct riscv_cpu      riscv;
 		struct sh_cpu         sh;
 	} cd;
 };
@@ -455,7 +487,7 @@
         int cpu_id, char *cpu_type_name);
 void cpu_destroy(struct cpu *cpu);
 
-void cpu_tlbdump(struct machine *m, int x, int rawflag);
+void cpu_tlbdump(struct cpu *cpu, int rawflag);
 void cpu_register_dump(struct machine *m, struct cpu *cpu,
 	int gprs, int coprocs);
 int cpu_disassemble_instr(struct machine *m, struct cpu *cpu,
@@ -469,11 +501,11 @@
 void cpu_run_init(struct machine *machine);
 void cpu_run_deinit(struct machine *machine);
 
-void cpu_dumpinfo(struct machine *m, struct cpu *cpu);
+void cpu_dumpinfo(struct machine *m, struct cpu *cpu, bool verbose);
 void cpu_list_available_types(void);
-void cpu_show_cycles(struct machine *machine, int forced);
+void cpu_show_cycles(struct machine *machine, bool forced);
+void cpu_print_pc_indicator_in_disassembly(struct cpu *cpu, int running, uint64_t dumpaddr);
 
-struct cpu_family *cpu_family_ptr_by_number(int arch);
 void cpu_init(void);
 
 
@@ -501,7 +533,7 @@
 	    SETTINGS_FORMAT_HEX8, (void *) &(var));
 
 
-#define CPU_FAMILY_INIT(n,s)	int n ## _cpu_family_init(		\
+#define CPU_FAMILY_INIT(n,s)	void n ## _cpu_family_init(		\
 	struct cpu_family *fp) {					\
 	/*  Fill in the cpu_family struct with valid data for this arch.  */ \
 	fp->name = strdup(s);						\
@@ -513,7 +545,6 @@
 	fp->functioncall_trace = n ## _cpu_functioncall_trace;		\
 	fp->tlbdump = n ## _cpu_tlbdump;				\
 	fp->init_tables = n ## _cpu_init_tables;			\
-	return 1;							\
 	}
 
 
diff -Nru gxemul-0.6.2/src/include/cpu_i960.h gxemul-0.7.0+dfsg/src/include/cpu_i960.h
--- gxemul-0.6.2/src/include/cpu_i960.h	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/cpu_i960.h	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,111 @@
+#ifndef	CPU_I960_H
+#define	CPU_I960_H
+
+/*
+ *  Copyright (C) 2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Intel 80960 (i960) CPU definitions.
+ */
+
+#include "misc.h"
+#include "interrupt.h"
+
+
+struct cpu_family;
+
+
+#define	I960_N_IC_ARGS			3
+#define	I960_INSTR_ALIGNMENT_SHIFT	2
+#define	I960_IC_ENTRIES_SHIFT		10
+#define	I960_IC_ENTRIES_PER_PAGE	(1 << I960_IC_ENTRIES_SHIFT)
+#define	I960_PC_TO_IC_ENTRY(a)		(((a)>>I960_INSTR_ALIGNMENT_SHIFT) \
+					& (I960_IC_ENTRIES_PER_PAGE-1))
+#define	I960_ADDR_TO_PAGENR(a)		((a) >> (I960_IC_ENTRIES_SHIFT \
+					+ I960_INSTR_ALIGNMENT_SHIFT))
+
+DYNTRANS_MISC_DECLARATIONS(i960,I960,uint32_t)
+
+#define	I960_MAX_VPH_TLB_ENTRIES		128
+
+
+// TODO: differently named registers? (register windows)
+#define	N_I960_REGS		32
+#define	N_I960_SFRS		32
+#define	I960_G0			16	// offset of register g0 (first parameter register)
+
+
+struct i960_cpu {
+	/*
+	 *  Control registers.
+	 *
+	 *  NOTE: The program counter is called "ip" on the i960. The
+	 *  long name for the i960 pc register is to separate it from
+	 *  cpu->pc (the program counter).
+	 */
+	uint32_t		ac;		// Arithmetic control
+	uint32_t		i960_pc;	// Process control
+	uint32_t		tc;		// Trace control
+
+	/*  General purpose registers: r and g registers  */
+	uint32_t		r[N_I960_REGS];
+
+	/*  sfrs:  */
+	int			nr_of_valid_sfrs;
+	uint32_t		sfr[N_I960_SFRS];
+
+	/*  Current interrupt assertion:  */
+	int			irq_asserted;
+
+
+	/*
+	 *  Instruction translation cache, internal TLB structure, and 32-bit
+	 *  virtual -> physical -> host address translation arrays.
+	 */
+	DYNTRANS_ITC(i960)
+	VPH_TLBS(i960,I960)
+	VPH32(i960,I960)
+};
+
+
+/*  cpu_i960.c:  */
+int i960_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
+int i960_run_instr(struct cpu *cpu);
+void i960_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
+	unsigned char *host_page, int writeflag, uint64_t paddr_page);
+void i960_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
+void i960_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
+int i960_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
+	unsigned char *data, size_t len, int writeflag, int cache_flags);
+void i960_cpu_family_init(struct cpu_family *);
+void i960_exception(struct cpu *cpu, int vector, int is_trap);
+
+/*  memory_i960.c:  */
+int i960_translate_v2p(struct cpu *cpu, uint64_t vaddr,
+	uint64_t *return_addr, int flags);
+
+
+#endif	/*  CPU_I960_H  */
diff -Nru gxemul-0.6.2/src/include/cpu_m88k.h gxemul-0.7.0+dfsg/src/include/cpu_m88k.h
--- gxemul-0.6.2/src/include/cpu_m88k.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/cpu_m88k.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	CPU_M88K_H
 
 /*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2007-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -195,8 +195,13 @@
 #define	M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE		8
 #define	M88K_EXCEPTION_INTEGER_OVERFLOW			9
 #define	M88K_EXCEPTION_ERROR				10
+#define	M88K_EXCEPTION_NMI				11
+#define	M88K_EXCEPTION_DATA_MMU_READ_MISS		12
+#define	M88K_EXCEPTION_DATA_MMU_WRITE_MISS		13
+#define	M88K_EXCEPTION_INSTRUCTION_MMU_ATC_MISS		14
 #define	M88K_EXCEPTION_SFU1_PRECISE			114
 #define	M88K_EXCEPTION_SFU1_IMPRECISE			115
+#define	M88K_EXCEPTION_SFU2_GRAPHICS			116
 #define	M88K_EXCEPTION_USER_TRAPS_START			128
 
 /*  A reserved/unimplemented instruction, used for PROM calls:  */
@@ -280,7 +285,7 @@
 void m88k_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
 int m88k_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
 	unsigned char *data, size_t len, int writeflag, int cache_flags);
-int m88k_cpu_family_init(struct cpu_family *);
+void m88k_cpu_family_init(struct cpu_family *);
 void m88k_ldcr(struct cpu *cpu, uint32_t *r32ptr, int cr);
 void m88k_stcr(struct cpu *cpu, uint32_t value, int cr, int rte);
 void m88k_fstcr(struct cpu *cpu, uint32_t value, int fcr);
diff -Nru gxemul-0.6.2/src/include/cpu_mips.h gxemul-0.7.0+dfsg/src/include/cpu_mips.h
--- gxemul-0.6.2/src/include/cpu_mips.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/cpu_mips.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	CPU_MIPS_H
 
 /*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -287,7 +287,7 @@
 void mips_cpu_interrupt_assert(struct interrupt *interrupt);
 void mips_cpu_interrupt_deassert(struct interrupt *interrupt);
 int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
-void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);
+void mips_cpu_tlbdump(struct cpu* cpu, int rawflag);
 void mips_cpu_register_match(struct machine *m, char *name, 
 	int writeflag, uint64_t *valuep, int *match_register);
 void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
@@ -297,9 +297,9 @@
         /*  uint64_t pagemask,  */  int coproc_nr, uint64_t vaddr_vpn2,
         int vaddr_asid, int x_64);
 int mips_cpu_run(struct emul *emul, struct machine *machine);
-void mips_cpu_dumpinfo(struct cpu *cpu);
+void mips_cpu_dumpinfo(struct cpu *cpu, bool verbose);
 void mips_cpu_list_available_types(void);
-int mips_cpu_family_init(struct cpu_family *);
+void mips_cpu_family_init(struct cpu_family *);
 
 
 /*  cpu_mips_coproc.c:  */
diff -Nru gxemul-0.6.2/src/include/cpu_ppc.h gxemul-0.7.0+dfsg/src/include/cpu_ppc.h
--- gxemul-0.6.2/src/include/cpu_ppc.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/cpu_ppc.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	CPU_PPC_H
 
 /*
- *  Copyright (C) 2005-2012  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -214,7 +214,7 @@
 void ppc_init_64bit_dummy_tables(struct cpu *cpu);
 int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
 	unsigned char *data, size_t len, int writeflag, int cache_flags);
-int ppc_cpu_family_init(struct cpu_family *);
+void ppc_cpu_family_init(struct cpu_family *);
 
 /*  memory_ppc.c:  */
 int ppc_translate_v2p(struct cpu *cpu, uint64_t vaddr,
diff -Nru gxemul-0.6.2/src/include/cpu_riscv.h gxemul-0.7.0+dfsg/src/include/cpu_riscv.h
--- gxemul-0.6.2/src/include/cpu_riscv.h	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/cpu_riscv.h	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,142 @@
+#ifndef	CPU_RISCV_H
+#define	CPU_RISCV_H
+
+/*
+ *  Copyright (C) 2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  RISC-V CPU definitions.
+ */
+
+#include "misc.h"
+#include "interrupt.h"
+
+
+struct cpu_family;
+
+// The RISC-V instruction stream is treated as having instructions of variable
+// length, in multiples of 16 bits (RISCV_INSTR_ALIGNMENT_SHIFT = 1).
+#define	RISCV_N_IC_ARGS			3
+#define	RISCV_INSTR_ALIGNMENT_SHIFT	1
+#define	RISCV_IC_ENTRIES_SHIFT		11
+#define	RISCV_IC_ENTRIES_PER_PAGE	(1 << RISCV_IC_ENTRIES_SHIFT)
+#define	RISCV_PC_TO_IC_ENTRY(a)		(((a)>>RISCV_INSTR_ALIGNMENT_SHIFT) \
+					& (RISCV_IC_ENTRIES_PER_PAGE-1))
+#define	RISCV_ADDR_TO_PAGENR(a)		((a) >> (RISCV_IC_ENTRIES_SHIFT \
+					+ RISCV_INSTR_ALIGNMENT_SHIFT))
+
+#define	RISCV_L2N		17
+#define	RISCV_L3N		18
+
+#define	RISCV_MAX_VPH_TLB_ENTRIES	192
+
+DYNTRANS_MISC_DECLARATIONS(riscv,RISCV,uint64_t)
+DYNTRANS_MISC64_DECLARATIONS(riscv,RISCV,uint8_t)
+
+#define	N_RISCV_REGS		32
+
+#define RISCV_REGISTER_NAMES	{ \
+	"zero", "ra", "sp",  "gp",  "tp", "t0", "t1", "t2", \
+	"fp",   "s1", "a0",  "a1",  "a2", "a3", "a4", "a5", \
+	"a6",   "a7", "s2",  "s3",  "s4", "s5", "s6", "s7", \
+	"s8",   "s9", "s10", "s11", "t3", "t4", "t5", "t6"  }
+
+#define	RISCV_REG_SP	2
+
+#define	RISCV_CREGBASE	8
+
+#define	RISCV_EXT_E		(1<<0)
+#define	RISCV_EXT_I		(1<<1)
+#define	RISCV_EXT_M		(1<<2)
+#define	RISCV_EXT_A		(1<<3)
+#define	RISCV_EXT_F		(1<<4)
+#define	RISCV_EXT_D		(1<<5)
+#define	RISCV_EXT_Q		(1<<6)
+#define	RISCV_EXT_L		(1<<7)
+#define	RISCV_EXT_C		(1<<8)
+#define	RISCV_EXT_B		(1<<9)
+#define	RISCV_EXT_J		(1<<10)
+#define	RISCV_EXT_T		(1<<11)
+#define	RISCV_EXT_P		(1<<12)
+#define	RISCV_EXT_V		(1<<13)
+#define	RISCV_EXT_N		(1<<14)
+
+#define	RISCV_EXT_G		(RISCV_EXT_I|RISCV_EXT_M|RISCV_EXT_A|RISCV_EXT_F|RISCV_EXT_D)
+
+#define	RISCV_EXTENSION_NAMES { \
+	"E", "I", "M", "A", "F", "D", "Q", "L", "C", "B", "J", "T", "P", "V", "N", NULL }
+     
+
+struct riscv_cpu {
+	uint64_t		extensions;
+
+	/*  General purpose registers:  */
+	uint64_t		x[N_RISCV_REGS];
+
+	/*  Destination scratch register for non-nop instructions with destination x0:  */
+	uint64_t		zero_scratch;
+
+	/*  Current interrupt assertion:  */
+	int			irq_asserted;
+
+
+	/*
+	 *  Instruction translation cache, internal TLB structure, and 32-bit
+	 *  and 64-bit virtual -> physical -> host address translation arrays.
+	 */
+	DYNTRANS_ITC(riscv)
+	VPH_TLBS(riscv,RISCV)
+	VPH32(riscv,RISCV)
+	VPH64(riscv,RISCV)
+};
+
+
+/*  cpu_riscv.c:  */
+void riscv_cpu_family_init(struct cpu_family *);
+void riscv_exception(struct cpu *cpu, int vector, int is_trap);
+int riscv_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
+	unsigned char *data, size_t len, int writeflag, int cache_flags);
+
+int riscv_run_instr(struct cpu *cpu);
+void riscv_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
+	unsigned char *host_page, int writeflag, uint64_t paddr_page);
+void riscv_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
+void riscv_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
+
+int riscv32_run_instr(struct cpu *cpu);
+void riscv32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
+	unsigned char *host_page, int writeflag, uint64_t paddr_page);
+void riscv32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
+void riscv32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
+
+/*  memory_riscv.c:  */
+int riscv_translate_v2p(struct cpu *cpu, uint64_t vaddr,
+	uint64_t *return_addr, int flags);
+int riscv32_translate_v2p(struct cpu *cpu, uint64_t vaddr,
+	uint64_t *return_addr, int flags);
+
+
+#endif	/*  CPU_RISCV_H  */
diff -Nru gxemul-0.6.2/src/include/cpu_sh.h gxemul-0.7.0+dfsg/src/include/cpu_sh.h
--- gxemul-0.6.2/src/include/cpu_sh.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/cpu_sh.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	CPU_SH_H
 
 /*
- *  Copyright (C) 2005-2011  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -235,7 +235,7 @@
 void sh_init_64bit_dummy_tables(struct cpu *cpu);
 int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
 	unsigned char *data, size_t len, int writeflag, int cache_flags);
-int sh_cpu_family_init(struct cpu_family *);
+void sh_cpu_family_init(struct cpu_family *);
 
 void sh_update_interrupt_priorities(struct cpu *cpu);
 void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
diff -Nru gxemul-0.6.2/src/include/debugger.h gxemul-0.7.0+dfsg/src/include/debugger.h
--- gxemul-0.6.2/src/include/debugger.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/debugger.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	DEBUGGER_H
 
 /*
- *  Copyright (C) 2004-2010  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -43,11 +43,6 @@
 void debugger_reset(void);
 void debugger_init(struct emul *emul);
 
-/*  single_step values:  */
-#define	NOT_SINGLE_STEPPING		0
-#define	ENTER_SINGLE_STEPPING		1
-#define	SINGLE_STEPPING			2
-
 /*  debugger_expr.c:  */
 #define	PARSE_NOMATCH		0
 #define	PARSE_MULTIPLE		1
diff -Nru gxemul-0.6.2/src/include/device.h gxemul-0.7.0+dfsg/src/include/device.h
--- gxemul-0.6.2/src/include/device.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/device.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	DEVICE_H
 
 /*
- *  Copyright (C) 2005-2010  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
diff -Nru gxemul-0.6.2/src/include/devices.h gxemul-0.7.0+dfsg/src/include/devices.h
--- gxemul-0.6.2/src/include/devices.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/devices.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	DEVICES_H
 
 /*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -193,6 +193,7 @@
 #define	VFB_DEC_VFB02		3
 #define	VFB_DEC_MAXINE		4
 #define	VFB_PLAYSTATION2	5
+#define	VFB_REVERSEBITS		6
 /*  Extra flags:  */
 #define	VFB_REVERSE_START	0x10000
 struct vfb_data {
@@ -368,7 +369,7 @@
 int dev_ram_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
 	unsigned char *data, size_t len, int writeflag, void *);
 void dev_ram_init(struct machine *machine, uint64_t baseaddr, uint64_t length,
-	int mode, uint64_t otheraddr, const char* name = NULL);
+	int mode, uint64_t otheraddr, const char* name);
 
 /*  dev_scc.c:  */
 #define	DEV_SCC_LENGTH			0x1000
@@ -406,6 +407,7 @@
 int dev_sgi_de_access(struct cpu *cpu, struct memory *mem,
 	uint64_t relative_addr, unsigned char *data, size_t len,
 	int writeflag, void *);
+struct sgi_re_data;
 void dev_sgi_de_init(struct memory *mem, uint64_t baseaddr, struct sgi_re_data *);
 // SGI O2 Memory Transfer Engine:
 #define	DEV_SGI_MTE_LENGTH		0x1000
@@ -511,6 +513,7 @@
         int                     use_fb;
 	int			console_handle;
 
+        int                     (*space_available_in_queue)(void *,int);
         void                    (*add_to_rx_queue)(void *,int,int);
 	void			*add_data;
                 
@@ -519,12 +522,14 @@
                         
         int                     mouse_mode;
         int                     mouse_revision;         /*  0..15  */  
-        int                     mouse_x, mouse_y, mouse_buttons;
+        int                     mouse_buttons;
 };
 void lk201_tick(struct machine *, struct lk201_data *); 
 void lk201_tx_data(struct lk201_data *, int port, int idata);
 void lk201_init(struct lk201_data *d, int use_fb,
-	void (*add_to_rx_queue)(void *,int,int), int console_handle, void *);
+	int (*space_available_in_queue)(void *,int),
+	void (*add_to_rx_queue)(void *,int,int),
+	int console_handle, void *);
 
 
 #endif	/*  DEVICES_H  */
diff -Nru gxemul-0.6.2/src/include/diskimage.h gxemul-0.7.0+dfsg/src/include/diskimage.h
--- gxemul-0.6.2/src/include/diskimage.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/diskimage.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	DISKIMAGE_H
 
 /*
- *  Copyright (C) 2003-2011  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -31,12 +31,14 @@
  *  Generic disk image functions.  (See diskimage.c for more info.)
  */
 
+#include <stdbool.h>
 #include <stdio.h>
 #include <sys/types.h>
 
 #include "misc.h"
 
 /*  Diskimage types:  */
+#define	DISKIMAGE_UNKNOWN	0
 #define	DISKIMAGE_SCSI		1
 #define	DISKIMAGE_IDE		2
 #define	DISKIMAGE_FLOPPY	3
@@ -67,13 +69,17 @@
 	struct diskimage_overlay *overlays;
 
 	int		chs_override;
-	int		cylinders;
+	int64_t		cylinders;
 	int		heads;
-	int		sectors_per_track;
+	int64_t		sectors_per_track;
 
-	off_t		total_size;
-	int64_t		override_base_offset;
-	int		logical_block_size;
+	int		rpms;
+
+	int64_t		total_size;			// in bytes
+	int64_t		override_base_offset;		// in bytes
+	int		logical_block_size;		// in bytes
+
+	int64_t		nr_of_logical_blocks;		// in logical blocks
 
 	int		writable;
 	int		is_a_cdrom;
@@ -83,9 +89,6 @@
 	uint64_t	tape_offset;
 	int		tape_filenr;
 	int		filemark;
-
-	int		rpms;
-	int		ncyls;
 };
 
 
@@ -137,8 +140,9 @@
 	off_t offset, unsigned char *buf, size_t len);
 int diskimage_access(struct machine *machine, int id, int type, int writeflag,
 	off_t offset, unsigned char *buf, size_t len);
-void diskimage_add_overlay(struct diskimage *d, char *overlay_basename);
-void diskimage_recalc_size(struct diskimage *d);
+bool diskimage_add_overlay(struct diskimage *d, char *overlay_basename,
+	bool remove_after_open);
+bool diskimage_recalc_size(struct diskimage *d);
 int diskimage_exist(struct machine *machine, int id, int type);
 int diskimage_bootdev(struct machine *machine, int *typep);
 int diskimage_add(struct machine *machine, char *fname);
diff -Nru gxemul-0.6.2/src/include/emul.h gxemul-0.7.0+dfsg/src/include/emul.h
--- gxemul-0.6.2/src/include/emul.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/emul.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	EMUL_H
 
 /*
- *  Copyright (C) 2004-2010  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -28,6 +28,7 @@
  *  SUCH DAMAGE.
  */
 
+#include <stdbool.h>
 #include "misc.h"
 
 struct machine;
@@ -57,10 +58,10 @@
 void emul_destroy(struct emul *emul);
 
 struct machine *emul_add_machine(struct emul *e, char *name);
-void emul_machine_setup(struct machine *machine, int n_load, char **load_names,
+bool emul_machine_setup(struct machine *machine, int n_load, char **load_names,
 	int n_devices, char **device_names);
 void emul_dumpinfo(struct emul *e);
-void emul_simple_init(struct emul *emul);
+bool emul_simple_init(struct emul *emul, char* tap_devname);
 struct emul *emul_create_from_configfile(char *fname);
 void emul_run(struct emul *emul);
 
diff -Nru gxemul-0.6.2/src/include/EscapedString.h gxemul-0.7.0+dfsg/src/include/EscapedString.h
--- gxemul-0.6.2/src/include/EscapedString.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/EscapedString.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,83 +0,0 @@
-#ifndef ESCAPEDSTRING_H
-#define	ESCAPEDSTRING_H
-
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "UnitTest.h"
-
-
-/**
- * \brief A helper class for escaping strings using C-style escapes.
- *
- * TODO: It is ugly to use this for conversions in both directions! Should
- *	be fixed some day.
- */
-class EscapedString
-	: public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs an EscapedString helper.
-	 *
-	 * @param str	A string, either escaped or not escaped.
-	 */
-	EscapedString(const string& str);
-
-	/**
-	 * \brief Generates an escaped string, from the original string.
-	 *
-	 * @return	an escaped string
-	 */
-	string Generate() const;
-
-	/**
-	 * \brief Decodes an escaped string, from the original string.
-	 *
-	 * The original string should be a C-style escaped string, with
-	 * or without surrounding quote (") characters.
-	 *
-	 * @param success Set to true if decoding was successful, false
-	 *	if there was an error.
-	 * @return A decoded (unescaped) string. (Only valid if
-	 *	<tt>success</tt> was set to true.)
-	 */
-	string Decode(bool& success) const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-private:
-	string		m_str;
-};
-
-
-#endif	// ESCAPEDSTRING_H
diff -Nru gxemul-0.6.2/src/include/FileLoader_aout.h gxemul-0.7.0+dfsg/src/include/FileLoader_aout.h
--- gxemul-0.6.2/src/include/FileLoader_aout.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/FileLoader_aout.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,65 +0,0 @@
-#ifndef FILELOADER_AOUT_H
-#define	FILELOADER_AOUT_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Component.h"
-#include "FileLoaderImpl.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief a.out binary loader.
- *
- * TODO: Longer comment.
- */
-class FileLoader_aout
-	: public UnitTestable
-	, public FileLoaderImpl
-{
-public:
-	FileLoader_aout(const string& filename);
-
-	~FileLoader_aout()
-	{
-	}
-
-	string DetectFileType(unsigned char *buf, size_t buflen, float& matchness) const;
-
-	bool LoadIntoComponent(refcount_ptr<Component> component, ostream& messages) const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// FILELOADER_AOUT_H
diff -Nru gxemul-0.6.2/src/include/FileLoader_bout.h gxemul-0.7.0+dfsg/src/include/FileLoader_bout.h
--- gxemul-0.6.2/src/include/FileLoader_bout.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/FileLoader_bout.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,65 +0,0 @@
-#ifndef FILELOADER_BOUT_H
-#define	FILELOADER_BOUT_H
-
-/*
- *  Copyright (C) 2009-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Component.h"
-#include "FileLoaderImpl.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief b.out binary loader.
- *
- * This file loader is used for reading i960 binaries.
- */
-class FileLoader_bout
-	: public UnitTestable
-	, public FileLoaderImpl
-{
-public:
-	FileLoader_bout(const string& filename);
-
-	~FileLoader_bout()
-	{
-	}
-
-	string DetectFileType(unsigned char *buf, size_t buflen, float& matchness) const;
-
-	bool LoadIntoComponent(refcount_ptr<Component> component, ostream& messages) const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// FILELOADER_BOUT_H
diff -Nru gxemul-0.6.2/src/include/FileLoader_ELF.h gxemul-0.7.0+dfsg/src/include/FileLoader_ELF.h
--- gxemul-0.6.2/src/include/FileLoader_ELF.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/FileLoader_ELF.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,65 +0,0 @@
-#ifndef FILELOADER_ELF_H
-#define	FILELOADER_ELF_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Component.h"
-#include "FileLoaderImpl.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief ELF binary loader.
- *
- * TODO: Longer comment.
- */
-class FileLoader_ELF
-	: public UnitTestable
-	, public FileLoaderImpl
-{
-public:
-	FileLoader_ELF(const string& filename);
-
-	~FileLoader_ELF()
-	{
-	}
-
-	string DetectFileType(unsigned char *buf, size_t buflen, float& matchness) const;
-
-	bool LoadIntoComponent(refcount_ptr<Component> component, ostream& messages) const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// FILELOADER_ELF_H
diff -Nru gxemul-0.6.2/src/include/FileLoader.h gxemul-0.7.0+dfsg/src/include/FileLoader.h
--- gxemul-0.6.2/src/include/FileLoader.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/FileLoader.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,112 +0,0 @@
-#ifndef FILELOADER_H
-#define	FILELOADER_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Component.h"
-#include "FileLoaderImpl.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A class used to load binary files into emulated memory.
- *
- * A %FileLoader is given a name of a binary file, e.g. an ELF file, and
- * attempts to load it into emulated memory.
- *
- * Binary files may be loaded to either physical or virtual memory addresses.
- * To load to a physical address, we want to write to a component which
- * is an AddressDataBus directly. To load to virtual addresses, we need to go
- * via a particular CPU, because it is the CPU which does the virtual to
- * physical address translation.
- *
- * The type of the file is normally auto-detected by reading magic sequences
- * at the start of the file.
- */
-class FileLoader
-	: public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs a %FileLoader object.
-	 *
-	 * \param filename The name of the file to open.
-	 */
-	FileLoader(const string& filename);
-
-	/**
-	 * \brief Retrieves the filename of this %FileLoader.
-	 *
-	 * \return The filename.
-	 */
-	const string& GetFilename() const;
-
-	/**
-	 * \brief Attempt to detect the file format of the file.
-	 *
-	 * \param loader On return from the function, if the file format has
-	 *	been detected, this is set to a pointer to a FileLoaderImpl.
-	 *	Otherwise (if no format was detected), it is NULL.
-	 * \return A string representing the file format.
-	 */
-	string DetectFileFormat(refcount_ptr<const FileLoaderImpl>& loader) const;
-
-	/**
-	 * \brief Loads the file into a CPU or an AddressDataBus.
-	 *
-	 * Note: The file is usually loaded into a virtual address space.
-	 * It is therefore necessary to load it into a CPU, and not directly
-	 * into RAM.
-	 *
-	 * @param component A CPUComponent (or any other
-	 *	component which implements the AddressDataBus interface),
-	 *	into which the file will be loaded.
-	 * @param messages An output stream where debug messages can be put.
-	 * @return True if loading succeeded, false otherwise.
-	 */
-	bool Load(refcount_ptr<Component> component, ostream& messages) const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-private:
-	// Disallow construction without arguments.
-	FileLoader();
-
-private:
-	typedef vector< refcount_ptr<const FileLoaderImpl> > FileLoaderImplVector;
-	const string		m_filename;
-	FileLoaderImplVector	m_fileLoaders;
-};
-
-
-#endif	// FILELOADER_H
diff -Nru gxemul-0.6.2/src/include/FileLoaderImpl.h gxemul-0.7.0+dfsg/src/include/FileLoaderImpl.h
--- gxemul-0.6.2/src/include/FileLoaderImpl.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/FileLoaderImpl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,90 +0,0 @@
-#ifndef FILELOADERIMPL_H
-#define	FILELOADERIMPL_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Component.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief A file loader.
- */
-class FileLoaderImpl
-	: public ReferenceCountable
-{
-public:
-	/**
-	 * \brief Constructs a file loader.
-	 *
-	 * @param filename The filename to load.
-	 */
-	FileLoaderImpl(const string& filename)
-		: m_filename(filename)
-	{
-	}
-
-	virtual ~FileLoaderImpl()
-	{
-	}
-
-	/**
-	 * \brief Attempt to detect file type.
-	 *
-	 * @param buf A buffer containing the header of the file.
-	 * @param buflen The length of the buffer.
-	 * @param matchness Set to a value between 0.0 and 1.0, indicating the
-	 *	match certainty.
-	 * @return A file type description, if there was a match; otherwise
-	 * an empty string.
-	 */
-	virtual string DetectFileType(unsigned char *buf, size_t buflen, float& matchness) const = 0;
-
-	/**
-	 * \brief Loads the file into a Component.
-	 *
-	 * @param component The AddressDataBus component to load the file
-	 *	into. (This is usually a CPUComponent.)
-	 * @param messages An output stream where debug messages can be put.
-	 * @return True if loading succeeded, false otherwise.
-	 */
-	virtual bool LoadIntoComponent(refcount_ptr<Component> component, ostream& messages) const = 0;
-
-protected:
-	const string& Filename() const
-	{
-		return m_filename;
-	}
-
-private:
-	const string	m_filename;
-};
-
-#endif	// FILELOADERIMPL_H
diff -Nru gxemul-0.6.2/src/include/FileLoader_raw.h gxemul-0.7.0+dfsg/src/include/FileLoader_raw.h
--- gxemul-0.6.2/src/include/FileLoader_raw.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/FileLoader_raw.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,65 +0,0 @@
-#ifndef FILELOADER_RAW_H
-#define	FILELOADER_RAW_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "Component.h"
-#include "FileLoaderImpl.h"
-#include "UnitTest.h"
-
-
-/**
- * \brief Raw binary loader (no specific format).
- *
- * TODO: Longer comment.
- */
-class FileLoader_raw
-	: public UnitTestable
-	, public FileLoaderImpl
-{
-public:
-	FileLoader_raw(const string& filename);
-
-	~FileLoader_raw()
-	{
-	}
-
-	string DetectFileType(unsigned char *buf, size_t buflen, float& matchness) const;
-
-	bool LoadIntoComponent(refcount_ptr<Component> component, ostream& messages) const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// FILELOADER_RAW_H
diff -Nru gxemul-0.6.2/src/include/GXemul.h gxemul-0.7.0+dfsg/src/include/GXemul.h
--- gxemul-0.6.2/src/include/GXemul.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/GXemul.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,347 +0,0 @@
-#ifndef GXEMUL_H
-#define	GXEMUL_H
-
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include <sys/time.h>
-
-#include "CommandInterpreter.h"
-#include "Component.h"
-#include "UI.h"
-
-
-/**
- * \brief The main emulator class.
- *
- * A %GXemul instance basically has the following member variables:
- *
- * <ol>
- *	<li>a tree of components, which make up the full
- *		state of the current emulation setup
- *	<li>a UI, which runs the main [interactive] loop
- *	<li>a CommandInterpreter
- *	<li>a RunState
- *	<li>a list of "on reset commands", which are executed on Reset().
- * </ol>
- */
-class GXemul
-{
-public:
-	enum RunState
-	{
-		Paused,
-		SingleStepping,			// Single-step execution
-		Running,			// Continuous execution
-		Quitting
-	};
-
-public:
-	/**
-	 * \brief Creates a GXemul instance.
-	 */
-	GXemul();
-
-	/**
-	 * \brief Parses command line arguments (file names).
-	 *
-	 * @param templateMachine The template machine to use.
-	 * @param filenameCount for parsing command line options.
-	 * @param filenames for parsing command line options.
-	 * @return true if options were parsable, false if there was
-	 *		some error.
-	 */
-	bool ParseFilenames(string templateMachine, int filenameCount, char *filenames[]);
-
-	/**
-	 * \brief Discards the current emulation, and starts anew with just
-	 *	an empty root component.
-	 */
-	void ClearEmulation();
-
-	/**
-	 * \brief Initializes the %UI.
-	 */
-	void InitUI();
-
-	/**
-	 * \brief Runs GXemul's main loop.
-	 *
-	 * @return Zero on success, non-zero on error.
-	 */
-	int Run();
-
-	/**
-	 * \brief Gets the current emulation setup's filename.
-	 *
-	 * @return The name of the file that is used for the current emulation
-	 *	setup. If no filename is defined yet, this is an empty string.
-	 */
-	const string& GetEmulationFilename() const;
-
-	/**
-	 * \brief Sets the current emulation setup's filename.
-	 *
-	 * @param filename This is the name of the file that is used
-	 *	for the current emulation setup.
-	 */
-	void SetEmulationFilename(const string& filename);
-
-	/**
-	 * \brief Gets a reference to the CommandInterpreter.
-	 *
-	 * @return A reference to the %GXemul instance' CommandInterpreter.
-	 */
-	CommandInterpreter& GetCommandInterpreter();
-
-	/**
-	 * \brief Gets a pointer to the %GXemul instance' active UI.
-	 *
-	 * Note: Never NULL. The UI may be the NullUI, or another UI (such
-	 * as the ConsoleUI).
-	 *
-	 * @return A pointer to the UI in use.
-	 */
-	UI* GetUI();
-
-	/**
-	 * \brief Gets a pointer to the root configuration component.
-	 *
-	 * @return A pointer to the root component. If no configuration tree
-	 *	is loaded, then this is at least an empty dummy component.
-	 *	(The return value is never NULL.)
-	 */
-	refcount_ptr<Component> GetRootComponent();
-	const refcount_ptr<Component> GetRootComponent() const;
-
-	/**
-	 * \brief Sets the root component, discarding the previous one.
-	 *
-	 * This function should not be used to set the root component
-	 * to NULL. Use ClearEmulation() instead.
-	 *
-	 * @param newRootComponent A reference counted pointer to the new
-	 *	root component. It may not be a NULL pointer.
-	 */
-	void SetRootComponent(refcount_ptr<Component> newRootComponent);
-
-	/**
-	 * \brief Resets the emulation.
-	 *
-	 * This function recursively resets all components in the tree, and
-	 * then executes the "on reset" commands (usually commands to load
-	 * files into CPUs).
-	 *
-	 * @return false if any of the reset commands failed.
-	 */
-	bool Reset();
-
-	/**
-	 * \brief Interrupts emulation.
-	 *
-	 * Only meaningful if RunState is Running or SingleStepping.
-	 */
-	void Interrupt();
-
-	/**
-	 * \brief Returns whether or not the current emulation is being
-	 * interrupted.
-	 *
-	 * Only meaningful if RunState is Running or SingleStepping.
-	 */
-	bool IsInterrupting() const
-	{
-		return m_interrupting;
-	}
-
-	/**
-	 * \brief Sets the RunState.
-	 *
-	 * @param newState The new RunState.
-	 */
-	void SetRunState(RunState newState);
-
-	/**
-	 * \brief Gets the current RunState.
-	 *
-	 * @return The current RunState.
-	 */
-	RunState GetRunState() const;
-
-	/**
-	 * \brief Gets the current RunState as a string.
-	 *
-	 * @return The current RunState, formatted as a string.
-	 */
-	string GetRunStateAsString() const;
-
-	/**
-	 * \brief Gets the current step of the emulation.
-	 *
-	 * @return The nr of steps that the emulation has been executing,
-	 *	since the start.
-	 */
-	uint64_t GetStep() const;
-
-	/**
-	 * \brief Checks whether snapshots are currently enabled or not.
-	 *
-	 * @return True if running in quiet mode, false for normal operation.
-	 */
-	bool GetSnapshottingEnabled() const;
-
-	/**
-	 * \brief Sets whether or not to use snapshots.
-	 *
-	 * @param enabled true to enable snapshotting, false to disable it.
-	 */
-	void SetSnapshottingEnabled(bool enabled);
-
-	/**
-	 * \brief Gets the current quiet mode setting.
-	 *
-	 * @return True if running in quiet mode, false for normal operation.
-	 */
-	bool GetQuietMode() const;
-
-	/**
-	 * \brief Sets whether or not to run in quiet mode.
-	 *
-	 * @param quietMode true to run in quiet mode, false otherwise.
-	 */
-	void SetQuietMode(bool quietMode);
-
-	/**
-	 * \brief Sets the nr of single-steps to perform in a row.
-	 *
-	 * @param steps The number of steps, at least 1.
-	 */
-	void SetNrOfSingleStepsInARow(uint64_t steps);
-
-	/**
-	 * \brief Change step either forwards or backwards.
-	 *
-	 * @param oldStep The old step count.
-	 * @param newStep The new step count.
-	 * @return True if changing step worked, false if there was a failure.
-	 */
-	bool ModifyStep(int64_t oldStep, int64_t newStep);
-
-	/**
-	 * \brief Run the emulation for "a while".
-	 *
-	 * When single-stepping, this function will:
-	 * <ul>
-	 *	<li>execute one step,
-	 *	<li>set the run state to Paused,
-	 *	<li>and then return.
-	 * </ul>
-	 *
-	 * When not single-stepping, components will execute multiple steps at
-	 * once, if possible. In the most common case (no breakpoints or other
-	 * special cases), when this function returns, the run state will not
-	 * have been affected.
-	 *
-	 * @param longestTotalRun Maximum number of steps to execute.
-	 */
-	void Execute(const int longestTotalRun = 100000);
-
-	/**
-	 * \brief Dump a list to stdout with all available machine templates.
-	 */
-	static void ListTemplates();
-
-	/**
-	 * \brief Returns the GXemul version string.
-	 *
-	 * @return A string describing the GXemul version.
-	 */
-	static string Version();
-
-	bool IsTemplateMachine(const string& templateName) const;
-	static void DumpMachineAsHTML(const string& machineName);
-	static void GenerateHTMLListOfComponents(bool machines);
-
-private:
-	/**
-	 * \brief Creates an emulation setup from a template machine name.
-	 *
-	 * @param templateName The name of the template machine.
-	 * @return True if the emulation was created, false otherwise.
-	 */
-	bool CreateEmulationFromTemplateMachine(const string& templateName);
-
-	/**
-	 * \brief Prints help message to std::cout.
-	 */
-	void PrintUsage() const;
-
-	/**
-	 * \brief Sets the current step of the emulation.
-	 *
-	 * @param step The number of steps.
-	 */
-	void SetStep(uint64_t step);
-
-	/**
-	 * \brief Takes a snapshot of the full emulation state.
-	 */
-	void TakeSnapshot();
-
-
-	/********************************************************************/
-public:
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-private:
-	// Base:
-	bool			m_quietMode;
-	refcount_ptr<UI>	m_ui;
-	CommandInterpreter	m_commandInterpreter;
-	vector<string>		m_onResetCommands;
-
-	// Runtime:
-	RunState		m_runState;
-	bool			m_interrupting;
-	uint64_t		m_nrOfSingleStepsLeft;
-
-	// Performance measurement:
-	struct timeval		m_lastOutputTime;
-	uint64_t		m_lastOutputStep;
-
-	// Model:
-	string			m_emulationFileName;
-	refcount_ptr<Component>	m_rootComponent;
-
-	// Snapshotting:   TODO: Multiple snapshots!
-	bool			m_snapshottingEnabled;
-	refcount_ptr<Component>	m_snapshot;
-};
-
-#endif	// GXEMUL_H
diff -Nru gxemul-0.6.2/src/include/machine.h gxemul-0.7.0+dfsg/src/include/machine.h
--- gxemul-0.6.2/src/include/machine.h	2019-06-22 18:23:25.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/machine.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	MACHINE_H
 
 /*
- *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -28,6 +28,7 @@
  *  SUCH DAMAGE.
  */
 
+#include <stdbool.h>
 #include <sys/types.h>
 
 #include "symbol.h"
@@ -102,12 +103,11 @@
 	struct settings *settings;
 
 	/*  Name as choosen by the user:  */
-	const char *name;
+	char	*name;
 
 	/*  Full "path" to the machine, e.g. "machine[0]":  */
 	char	*path;
 
-	int	arch;			/*  ARCH_MIPS, ARCH_PPC, ..  */
 	int	machine_type;		/*  MACHINE_PMAX, ..  */
 	int	machine_subtype;	/*  MACHINE_DEC_3MAX_5000, ..  */
 
@@ -120,9 +120,7 @@
 	int	serial_nr;
 	int	nr_of_nics;
 
-	/*  TODO: How about multiple cpu familys in one machine?  */
-	struct cpu_family *cpu_family;
-
+	/*  Main memory:  */
 	struct memory *memory;
 
 	int	main_console_handle;
@@ -135,7 +133,7 @@
 	int	byte_order_override;
 	int	bootstrap_cpu;
 	int	use_random_bootstrap_cpu;
-	int	start_paused;
+	bool	start_paused;
 	int	ncpus;
 	struct cpu **cpus;
 
@@ -165,11 +163,9 @@
 	int	emulated_hz;
 	int	allow_instruction_combinations;
 	int	force_netboot;
-	int	slow_serial_interrupts_hack_for_linux;
 	uint64_t file_loaded_end_addr;
 	char	*boot_kernel_filename;
 	char	*boot_string_argument;
-	int	exit_without_entering_debugger;
 	int	n_gfx_cards;
 
 	/*  Instruction statistics:  */
@@ -199,14 +195,6 @@
  *  Machine emulation types:
  */
 
-#define	ARCH_NOARCH		0
-#define	ARCH_MIPS		1
-#define	ARCH_PPC		2
-#define	ARCH_ALPHA		4
-#define	ARCH_ARM		5
-#define	ARCH_SH			6
-#define	ARCH_M88K		7
-
 /*  MIPS:  */
 #define	MACHINE_BAREMIPS	1000
 #define	MACHINE_TESTMIPS	1001
@@ -257,6 +245,15 @@
 #define	MACHINE_MVME88K		7002
 #define	MACHINE_LUNA88K		7003
 
+/*  i960:  */
+#define	MACHINE_BAREI960	8000
+#define	MACHINE_HP700RX		8001
+#define	MACHINE_CYCLONEVH	8002
+
+/*  RISC-V:  */
+#define	MACHINE_BARERISCV	9000
+#define	MACHINE_TESTRISCV	9001
+
 /*  Other "pseudo"-machines:  */
 #define	MACHINE_NONE		0
 
@@ -349,7 +346,6 @@
 	struct machine_entry	*next;
 
 	/*  Machine type:  */
-	int			arch;
 	int			machine_type;	/*  Old-style type  */
 	const char		*name;		/*  Official name  */
 	int			n_aliases;
@@ -370,36 +366,35 @@
 #define	MACHINE_DEFAULT_CPU(x)	void machine_default_cpu_ ## x(struct machine *machine)
 #define	MACHINE_DEFAULT_RAM(x)	void machine_default_ram_ ## x(struct machine *machine)
 #define	MACHINE_REGISTER(x)	void machine_register_ ## x(void)
-#define	MR_DEFAULT(x,name,arch,type) struct machine_entry 		\
-	    *me = machine_entry_new(name,arch,type);			\
-	me->setup = machine_setup_ ## x;				\
-	me->set_default_cpu = machine_default_cpu_ ## x;		\
-	machine_entry_register(me, arch);
+#define	MR_DEFAULT(x,name,type) struct machine_entry 		\
+	    *me = machine_entry_new(name,type);			\
+	me->setup = machine_setup_ ## x;			\
+	me->set_default_cpu = machine_default_cpu_ ## x;	\
+	machine_entry_register(me);
 void automachine_init(void);
 
 
 /*  machine.c:  */
 struct machine *machine_new(char *name, struct emul *emul, int id);
 void machine_destroy(struct machine *machine);
-int machine_name_to_type(char *stype, char *ssubtype,
-	int *type, int *subtype, int *arch);
+int machine_name_to_type(char *stype, char *ssubtype, int *type, int *subtype);
 void machine_add_breakpoint_string(struct machine *machine, char *str);
 void machine_add_tickfunction(struct machine *machine,
 	void (*func)(struct cpu *, void *), void *extra, int clockshift);
 void machine_statistics_init(struct machine *, char *fname);
 void machine_register(char *name, MACHINE_SETUP_TYPE(setup));
 void machine_setup(struct machine *);
+void machine_add_devices_as_symbols(struct machine *machine, uint64_t offset);
 void machine_memsize_fix(struct machine *);
 void machine_default_cputype(struct machine *);
 void machine_dumpinfo(struct machine *);
-int machine_run(struct machine *machine);
+bool machine_run(struct machine *machine);
 void machine_list_available_types_and_cpus(void);
-struct machine_entry *machine_entry_new(const char *name, 
-	int arch, int oldstyle_type);
+struct machine_entry *machine_entry_new(const char *name, int oldstyle_type);
 void machine_entry_add_alias(struct machine_entry *me, const char *name);
 void machine_entry_add_subtype(struct machine_entry *me, const char *name,
 	int oldstyle_subtype, ...);
-void machine_entry_register(struct machine_entry *me, int arch);
+void machine_entry_register(struct machine_entry *me);
 void machine_init(void);
 
 
diff -Nru gxemul-0.6.2/src/include/memory.h gxemul-0.7.0+dfsg/src/include/memory.h
--- gxemul-0.6.2/src/include/memory.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/memory.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	MEMORY_H
 
 /*
- *  Copyright (C) 2004-2010  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -31,6 +31,7 @@
  *  Memory related functions.
  */
 
+#include <stdbool.h>
 #include <sys/types.h>
 #include <inttypes.h>
 
@@ -101,7 +102,7 @@
 
 void *zeroed_alloc(size_t s);
 
-struct memory *memory_new(uint64_t physical_max, int arch);
+struct memory *memory_new(uint64_t physical_max);
 
 int memory_points_to_string(struct cpu *cpu, struct memory *mem,
 	uint64_t addr, int min_string_length);
@@ -158,8 +159,6 @@
 	void *extra, int flags, unsigned char *dyntrans_data);
 void memory_device_remove(struct memory *mem, int i);
 
-uint64_t memory_checksum(struct memory *mem);
-
 void dump_mem_string(struct cpu *cpu, uint64_t addr);
 void store_string(struct cpu *cpu, uint64_t addr, const char *s);
 int store_64bit_word(struct cpu *cpu, uint64_t addr, uint64_t data64);
@@ -182,8 +181,8 @@
 void store_pointer_and_advance(struct cpu *cpu, uint64_t *addrp,
         uint64_t data, int flag64);
 
-void memory_warn_about_unimplemented_addr(struct cpu *cpu, struct memory *mem,
-	int writeflag, uint64_t paddr, uint8_t *data, size_t len);
+bool memory_warn_about_unimplemented_addr(struct cpu *cpu, struct memory *mem,
+	int writeflag, uint64_t paddr, size_t len);
 
 
 #endif	/*  MEMORY_H  */
diff -Nru gxemul-0.6.2/src/include/misc.h gxemul-0.7.0+dfsg/src/include/misc.h
--- gxemul-0.6.2/src/include/misc.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/misc.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	MISC_H
 
 /*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -32,6 +32,8 @@
  */
 
 
+#include <stdbool.h>
+#include <stdlib.h>
 #include <sys/types.h>
 #include <inttypes.h>
 
@@ -43,7 +45,7 @@
 
 #include "../../config.h"
 
-#define	COPYRIGHT_MSG	"Copyright (C) 2003-2019  Anders Gavare"
+#define	COPYRIGHT_MSG	"Copyright (C) 2003-2021  Anders Gavare"
 
 // The recommended way to add a specific message to the startup banner or
 // about box is to use the SECONDARY_MSG. This should end with a newline
@@ -54,37 +56,6 @@
 #define	SECONDARY_MSG	""
 
 
-#include <string>
-using std::string;
-typedef char stringchar;
-
-#include <map>
-using std::map;
-using std::pair;
-
-#include <list>
-using std::list;
-
-#include <vector>
-using std::vector;
-
-#include <sstream>
-using std::stringstream;
-
-#include <ostream>
-using std::ostream;
-
-#include <iostream>
-using std::cout;
-using std::cerr;
-
-#ifndef NDEBUG
-#include "thirdparty/debug_new.h"
-#endif
-
-#include "refcount_ptr.h"
-
-
 #ifdef NO_C99_PRINTF_DEFINES
 /*
  *  This is a SUPER-UGLY HACK which happens to work on some machines.
@@ -207,35 +178,15 @@
 #endif
 
 
-/*  Debug stuff:  */
-#define	DEBUG_BUFSIZE		1024
-#define	DEBUG_INDENTATION	4
-
-
-#ifdef HAVE___FUNCTION__
-
 #define	FAILURE(error_msg)					{	\
 		char where_msg[400];					\
 		snprintf(where_msg, sizeof(where_msg),			\
 		    "%s, line %i, function %s().\n",			\
-		    __FILE__, __LINE__, __FUNCTION__);			\
+		    __FILE__, __LINE__, __func__);			\
         	fprintf(stderr, "\n%s, in %s\n", error_msg, where_msg);	\
 		exit(1);						\
 	}
 
-#else
-
-#define	FAILURE(error_msg)					{	\
-		char where_msg[400];					\
-		snprintf(where_msg, sizeof(where_msg),			\
-		    "%s, line %i\n", __FILE__, __LINE__);		\
-        	fprintf(stderr, "\n%s, in %s.\n", error_msg, where_msg);\
-		exit(1);						\
-	}
-
-#endif	/*  !HAVE___FUNCTION__  */
-
-
 #define	CHECK_ALLOCATION(ptr)					{	\
 		if ((ptr) == NULL)					\
 			FAILURE("Out of memory");			\
@@ -262,6 +213,38 @@
 int decstation_prom_emul(struct cpu *cpu);
 
 
+/*  debugmsg.c:  */
+#define	SUBSYS_ALL		-1
+#define	SUBSYS_STARTUP		0	/*  Startup messages  */
+#define	SUBSYS_EMUL		1	/*  Emulation setup related  */
+#define	SUBSYS_DISK		2	/*  Disk I/O related  */
+#define	SUBSYS_NET		3	/*  Network related  */
+#define	SUBSYS_MACHINE		4	/*  Machine related  */
+#define	SUBSYS_DEVICE		5	/*  Device specific  */
+#define	SUBSYS_CPU		6	/*  General CPU  */
+#define	SUBSYS_MEMORY		7	/*  Memory related  */
+#define	SUBSYS_EXCEPTION	8	/*  CPU exceptions  */
+#define	SUBSYS_PROMEMUL		9	/*  PROM emulation related  */
+#define	SUBSYS_X11		10	/*  X11 related  */
+#define	VERBOSITY_ERROR		0
+#define	VERBOSITY_WARNING	1
+#define	VERBOSITY_INFO		2
+#define	VERBOSITY_DEBUG		3
+#define	ENOUGH_VERBOSITY(subsys,reqverb)	(debugmsg_current_verbosity[(subsys)] >= (reqverb))
+extern int *debugmsg_current_verbosity;
+void debug_indentation(int diff);
+void debug(const char *fmt, ...);
+void fatal(const char *fmt, ...);
+void debugmsg_init();
+int debugmsg_register_subsystem(const char* name);
+void debugmsg_change_settings(char *subsystem_name, char *n);
+void debugmsg_print_settings(const char *subsystem_name);
+void debugmsg_add_verbosity_level(int subsystem, int verbosity_delta);
+void debugmsg_set_verbosity_level(int subsystem, int verbosity);
+void debugmsg(int subsystem, const char *name, int verbosity_required, const char *fmt, ...);
+void debugmsg_cpu(struct cpu* cpu, int subsystem, const char *name, int verbosity_required, const char *fmt, ...);
+
+
 /*  dreamcast.c:  */
 void dreamcast_machine_setup(struct machine *);
 void dreamcast_emul(struct cpu *cpu);
@@ -283,13 +266,16 @@
 int luna88kprom_emul(struct cpu *cpu);
 
 
-/*  main.c:  */
-void debug_indentation(int diff);
-void debug(const char *fmt, ...);
-void fatal(const char *fmt, ...);
-
-
 /*  misc.c:  */
+void color_prompt();
+void color_normal();
+void color_error(bool bold);
+void color_debugmsg_subsystem();
+void color_debugmsg_name();
+void color_banner();
+void color_pc_indicator();
+const char* color_symbol_ptr();
+const char* color_normal_ptr();
 unsigned long long mystrtoull(const char *s, char **endp, int base);
 int mymkstemp(char *templ);
 #ifdef USE_STRLCPY_REPLACEMENTS
@@ -297,6 +283,7 @@
 size_t mystrlcat(char *dst, const char *src, size_t size);
 #endif
 void print_separator_line(void);
+uint64_t size_to_mask(uint64_t size);
 
 
 /*  mvmeprom.c:  */
diff -Nru gxemul-0.6.2/src/include/net.h gxemul-0.7.0+dfsg/src/include/net.h
--- gxemul-0.6.2/src/include/net.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/net.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	NET_H
 
 /*
- *  Copyright (C) 2004-2010  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -31,6 +31,7 @@
  *  Emulated network support.  (See net.c for more info.)
  */
 
+#include <stdbool.h>
 #include <netinet/in.h>
 #include <arpa/inet.h>
 #include <netdb.h>
@@ -112,6 +113,15 @@
 
 /*****************************************************************************/
 
+/* Common data for emulated Ethernet NICs. */
+
+struct nic_data {
+	struct net	*net;		/* net we belong to */
+	uint8_t		mac_address[6];	/* our MAC address */
+	int		promiscuous_mode;/* receive all packets */
+};
+
+/*****************************************************************************/
 
 #define	MAX_TCP_CONNECTIONS	100
 #define	MAX_UDP_CONNECTIONS	100
@@ -120,20 +130,23 @@
 	/*  The emul struct which this net belong to:  */
 	struct emul	*emul;
 
+	/*  The network's tap device, if we're using tap:  */
+	const char	*tapdev;
+	int		tap_fd;
+
 	/*  The network's addresses:  */
 	struct in_addr	netmask_ipv4;
 	int		netmask_ipv4_len;
 
 	/*  NICs connected to this network:  */
 	int		n_nics;
-	void		**nic_extra;	/*  one void * per NIC  */
+	struct nic_data	**nic_data;	/* one per NIC */
 
 	/*  The "special machine":  */
 	unsigned char	gateway_ipv4_addr[4];
 	unsigned char	gateway_ethernet_addr[6];
 
 	/*  Read from /etc/resolv.conf:  */
-	char		*domain_name;
 	int		nameserver_known;
 	struct in_addr	nameserver_ipv4;
 
@@ -151,6 +164,18 @@
 	struct remote_net *remote_nets;
 };
 
+/*  net_tap.c:  */
+void net_tap_rx_avail(struct net *net);
+void net_tap_tx(struct net *net, struct nic_data *nic, unsigned char *packet,
+	int len);
+bool net_tap_init(struct net *net, const char *tapdev);
+
+/*  net_ether.cc  */
+int net_ether_eq(const uint8_t *a1, const uint8_t *a2);
+int net_ether_broadcast(const uint8_t *a);
+int net_ether_multicast(const uint8_t *a);
+uint32_t net_ether_crc32_le(const uint8_t *buf, size_t len);
+
 /*  net_misc.c:  */
 void net_debugaddr(void *addr, int type);
 void net_generate_unique_mac(struct machine *, unsigned char *macbuf);
@@ -162,25 +187,27 @@
 void net_ip_tcp_checksum(unsigned char *tcp_header, int chksumoffset,
 	int tcp_len, unsigned char *srcaddr, unsigned char *dstaddr,
 	int udpflag);
-void net_ip_tcp_connectionreply(struct net *net, void *extra,
+void net_ip_tcp_connectionreply(struct net *net, struct nic_data *nic,
 	int con_id, int connecting, unsigned char *data, int datalen, int rst);
-void net_ip_broadcast(struct net *net, void *extra,
+void net_ip_broadcast(struct net *net, struct nic_data *nic,
         unsigned char *packet, int len);
-void net_ip(struct net *net, void *extra, unsigned char *packet, int len);
-void net_udp_rx_avail(struct net *net, void *extra);
-void net_tcp_rx_avail(struct net *net, void *extra);
+void net_ip(struct net *net, struct nic_data *nic, unsigned char *packet,
+	int len);
+void net_udp_rx_avail(struct net *net, struct nic_data *nic);
+void net_tcp_rx_avail(struct net *net, struct nic_data *nic);
 
 /*  net.c:  */
 struct ethernet_packet_link *net_allocate_ethernet_packet_link(
-	struct net *net, void *extra, size_t len);
-int net_ethernet_rx_avail(struct net *net, void *extra);
-int net_ethernet_rx(struct net *net, void *extra,
+	struct net *net, struct nic_data *nic, size_t len);
+int net_ethernet_rx_avail(struct net *net, struct nic_data *nic);
+int net_ethernet_rx(struct net *net, struct nic_data *nic,
 	unsigned char **packetp, int *lenp);
-void net_ethernet_tx(struct net *net, void *extra,
+void net_ethernet_tx(struct net *net, struct nic_data *nic,
 	unsigned char *packet, int len);
 void net_dumpinfo(struct net *net);
-void net_add_nic(struct net *net, void *extra, unsigned char *macaddr);
+void net_add_nic(struct net *net, struct nic_data *nic);
 struct net *net_init(struct emul *emul, int init_flags,
+	const char *tapdev,
 	const char *ipv4addr, int netipv4len, char **remote, int n_remote,
 	int local_port, const char *settings_prefix);
 
@@ -195,7 +222,7 @@
 	struct ethernet_packet_link *prev;
 	struct ethernet_packet_link *next;
 
-	void		*extra;
+	struct nic_data	*nic;
 	unsigned char	*data;
 	int		len;
 };
diff -Nru gxemul-0.6.2/src/include/NullUI.h gxemul-0.7.0+dfsg/src/include/NullUI.h
--- gxemul-0.6.2/src/include/NullUI.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/NullUI.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,123 +0,0 @@
-#ifndef NULLUI_H
-#define	NULLUI_H
-
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "UI.h"
-
-
-/**
- * \brief Dummy UI, which does not do anything.
- */
-class NullUI
-	: public UI
-{
-public:
-	/**
-	 * \brief Constructs a %NullUI.
-	 *
-	 * @param gxemul Pointer to the owning GXemul instance.
-	 */
-	NullUI(GXemul *gxemul);
-
-	virtual ~NullUI();
-
-	/**
-	 * \brief Does nothing, for the dummy UI.
-	 */
-	virtual void Initialize();
-
-	/**
-	 * \brief Does nothing, for the dummy UI.
-	 */
-	virtual void UpdateUI();
-
-	/**
-	 * \brief Does nothing, for the dummy UI.
-	 */
-	virtual void ShowStartupBanner();
-
-	/**
-	 * \brief Does nothing, for the dummy UI.
-	 *
-	 * @param msg The message to show. (Ignored.)
-	 */
-	virtual void ShowDebugMessage(const string& msg);
-
-	/**
-	 * \brief Does nothing, for the dummy UI.
-	 *
-	 * @param component A pointer to the Component. (Ignored.)
-	 * @param msg The message to show. (Ignored.)
-	 */
-	virtual void ShowDebugMessage(Component* component, const string& msg);
-
-	/**
-	 * \brief Does nothing, for the dummy UI.
-	 *
-	 * @param command The command to show. (Ignored.)
-	 */
-	virtual void ShowCommandMessage(const string& command);
-
-	/**
-	 * \brief Does nothing, for the dummy UI.
-	 *
-	 * @param msg The error message to show. (Ignored.)
-	 */
-	virtual void FatalError(const string& msg);
-
-	/**
-	 * \brief Does nothing, for the dummy UI.
-	 *
-	 * @param inputline The entire input line. (Ignored.)
-	 * @param cursorPosition The current cursor position. 0 is at the
-	 *	leftmost position. (Ignored.)
-	 */
-	virtual void RedisplayInputLine(const string& inputline,
-	    size_t cursorPosition);
-
-	/**
-	 * \brief Executed by the CommandInterpreter when a line has been
-	 * completed (with a newline).
-	 *
-	 * For the %NullUI, this is ignored.
-	 */
-	virtual void InputLineDone();
-
-	/**
-	 * \brief Runs the main loop. Ignored by the NullUI.
-	 *
-	 * The NullUI returns 0 immediately.
-	 */
-	virtual int MainLoop();
-
-	virtual void Shutdown();
-};
-
-
-#endif	// NULLUI_H
diff -Nru gxemul-0.6.2/src/include/ScopedTemporaryValue.h gxemul-0.7.0+dfsg/src/include/ScopedTemporaryValue.h
--- gxemul-0.6.2/src/include/ScopedTemporaryValue.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/ScopedTemporaryValue.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,106 +0,0 @@
-#ifndef	SCOPEDTEMPORARYVALUE_H
-#define	SCOPEDTEMPORARYVALUE_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-/**
- * \brief Scoped temporary variable template.
- *
- * Usage:<pre>
- * SomeType var = A;
- * {
- *	ScopedTemporaryValue<SomeType> holder(var);
- *	var = B;
- *	...
- * }
- * // var will here be reset to A.
- * </pre>
- * or
- * <pre>
- * SomeType var = A;
- * {
- *	ScopedTemporaryValue<SomeType> holder(var, B);
- *	// Here,  var is B.
- *	...
- * }
- * // var will here be reset to A.
- * </pre>
- *
- * Implementation note: This is just a schoolbook-style implementation
- * of a class which holds a variable, and then restores the original value
- * when going out of scope.
- */
-template <class T>
-class ScopedTemporaryValue
-{
-private:
-	// Prevent construction without reference.
-	ScopedTemporaryValue();
-
-public:
-	/**
-	 * \brief Constructor, which reads the old value from T, but
-	 * does not change it.
-	 *
-	 * @param var The variable.
- 	 */
-	ScopedTemporaryValue(T& var)
-		: m_var(var)
-	{
-		m_origValue = m_var;
-	}
-
-	/**
-	 * \brief Constructor, which reads the old value from T, and sets
-	 * it to a new (temporary) value.
-	 *
-	 * @param var The variable.
-	 * @param newValue The new (temporary) value.
- 	 */
-	ScopedTemporaryValue(T& var, T newValue)
-		: m_var(var)
-	{
-		m_origValue = m_var;
-		m_var = newValue;
-	}
-
-	/**
-	 * \brief Destructor, which restores the original value.
-	 */
-	~ScopedTemporaryValue()
-	{
-		m_var = m_origValue;
-	}
-
-private:
-	T&		m_var;
-	T		m_origValue;
-};
-
-
-#endif	// SCOPEDTEMPORARYVALUE_H
diff -Nru gxemul-0.6.2/src/include/SerializationContext.h gxemul-0.7.0+dfsg/src/include/SerializationContext.h
--- gxemul-0.6.2/src/include/SerializationContext.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/SerializationContext.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,100 +0,0 @@
-#ifndef SERIALIZATIONCONTEXT_H
-#define	SERIALIZATIONCONTEXT_H
-
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-
-/**
- * \brief A context used during serialization of objects.
- */
-class SerializationContext
-{
-public:
-	/**
-	 * \brief Constructs a default SerializationContext.
-	 */
-	SerializationContext()
-		: m_indentation(0)
-	{
-	}
-
-	/**
-	 * \brief Gets the indentation level of the context.
-	 *
- 	 * @return the indentation level
-	 */
-	int GetIndentation() const
-	{
-		return m_indentation;
-	}
-
-	/**
-	 * \brief Sets the indentation level.
-	 *
-	 * @param indentation The new indentation level.
-	 */
-	void SetIndentation(int indentation)
-	{
-		m_indentation = indentation;
-	}
-
-	/**
-	 * \brief Constructs a SerializationContext which is indented (1
-	 *	step) compared to the current context.
-	 *
-	 * @return An indented context.
-	 */
-	SerializationContext Indented()
-	{
-		SerializationContext newContext;
-		newContext.SetIndentation(GetIndentation() + 1);
-		return newContext;
-	}
-
-	/**
-	 * \brief Generates a string of Tab characters, based on the
-	 *	indentation level.
-	 *
-	 * @return a string of tab characters
-	 */
-	string Tabs() const
-	{
-		string retValue;
-		for (int i=0; i<m_indentation; i++)
-			retValue += "\t";
-		return retValue;
-	}
-
-private:
-	int	m_indentation;
-};
-
-
-#endif	// SERIALIZATIONCONTEXT_H
diff -Nru gxemul-0.6.2/src/include/StateVariable.h gxemul-0.7.0+dfsg/src/include/StateVariable.h
--- gxemul-0.6.2/src/include/StateVariable.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/StateVariable.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,332 +0,0 @@
-#ifndef STATEVARIABLE_H
-#define	STATEVARIABLE_H
-
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Note/TODO: This class could perhaps be rewritten in a nicer way by
- *             using C++ templates.
- */
-
-#include "misc.h"
-
-#include "SerializationContext.h"
-#include "UnitTest.h"
-
-
-class StateVariable;
-typedef map<string,StateVariable> StateVariableMap;
-
-
-class CustomStateVariableHandler
-{
-public:
-	CustomStateVariableHandler()
-	{
-	}
-
-	virtual ~CustomStateVariableHandler()
-	{
-	}
-
-	virtual void Serialize(ostream& ss) const = 0;
-	virtual bool Deserialize(const string& value) = 0;
-	virtual void CopyValueFrom(CustomStateVariableHandler* other) = 0;
-};
-
-
-/**
- * \brief StateVariables make up the persistent state of Component objects.
- *
- * A %StateVariable has a name, and a value.
- */
-class StateVariable
-	: public UnitTestable
-{
-public:
-	/**
-	 * \brief An enumeration of the possible types of a %StateVariable.
-	 */
-	enum Type {
-		String = 0,
-		Bool,
-		Double,
-		UInt8,
-		UInt16,
-		UInt32,
-		UInt64,
-		SInt8,
-		SInt16,
-		SInt32,
-		SInt64,
-		Custom
-	};
-
-private:
-	/* Disable construction without name. */
-	StateVariable();
-
-public:
-	/**
-	 * \brief Constructor for a String StateVariable.
-	 *
-	 * @param name The variable's name.
-	 * @param ptrToString A pointer to the string which this
-	 *	variable refers to.
-	 */
-	StateVariable(const string& name, string* ptrToString);
-
-	/**
-	 * \brief Constructor for a Bool StateVariable.
-	 *
-	 * @param name The variable's name.
-	 * @param ptrToVar A pointer to the variable.
-	 */
-	StateVariable(const string& name, bool* ptrToVar);
-
-	/**
-	 * \brief Constructor for a Double StateVariable.
-	 *
-	 * @param name The variable's name.
-	 * @param ptrToVar A pointer to the variable.
-	 */
-	StateVariable(const string& name, double* ptrToVar);
-
-	/**
-	 * \brief Constructor for a UInt8 StateVariable.
-	 *
-	 * @param name The variable's name.
-	 * @param ptrToVar A pointer to the variable.
-	 */
-	StateVariable(const string& name, uint8_t* ptrToVar);
-
-	/**
-	 * \brief Constructor for a UInt16 StateVariable.
-	 *
-	 * @param name The variable's name.
-	 * @param ptrToVar A pointer to the variable.
-	 */
-	StateVariable(const string& name, uint16_t* ptrToVar);
-
-	/**
-	 * \brief Constructor for a UInt32 StateVariable.
-	 *
-	 * @param name The variable's name.
-	 * @param ptrToVar A pointer to the variable.
-	 */
-	StateVariable(const string& name, uint32_t* ptrToVar);
-
-	/**
-	 * \brief Constructor for a UInt64 StateVariable.
-	 *
-	 * @param name The variable's name.
-	 * @param ptrToVar A pointer to the variable.
-	 */
-	StateVariable(const string& name, uint64_t* ptrToVar);
-
-	/**
-	 * \brief Constructor for a SInt8 StateVariable.
-	 *
-	 * @param name The variable's name.
-	 * @param ptrToVar A pointer to the variable.
-	 */
-	StateVariable(const string& name, int8_t* ptrToVar);
-
-	/**
-	 * \brief Constructor for a SInt16 StateVariable.
-	 *
-	 * @param name The variable's name.
-	 * @param ptrToVar A pointer to the variable.
-	 */
-	StateVariable(const string& name, int16_t* ptrToVar);
-
-	/**
-	 * \brief Constructor for a SInt32 StateVariable.
-	 *
-	 * @param name The variable's name.
-	 * @param ptrToVar A pointer to the variable.
-	 */
-	StateVariable(const string& name, int32_t* ptrToVar);
-
-	/**
-	 * \brief Constructor for a SInt64 StateVariable.
-	 *
-	 * @param name The variable's name.
-	 * @param ptrToVar A pointer to the variable.
-	 */
-	StateVariable(const string& name, int64_t* ptrToVar);
-
-	/**
-	 * \brief Constructor for a custom StateVariable.
-	 *
-	 * @param name The variable's name.
-	 * @param ptrToHandler A pointer to the custom handler.
-	 */
-	StateVariable(const string& name, CustomStateVariableHandler* ptrToHandler);
-
-	/**
-	 * \brief Gets the name of the variable.
-	 *
-	 * @return The name of the variable.
-	 */
-	const string& GetName() const;
-
-	/**
-	 * \brief Gets the type of the variable.
-	 *
-	 * @return The type of the variable.
-	 */
-	enum Type GetType() const;
-
-	/**
-	 * \brief Serializes the variable value into a string.
-	 *
-	 * Strings are serialized as quoted strings; most other types without
-	 * quoting.
-	 *
-	 * @param ss A stream where the variable value will be appended.
-	 */
-	void SerializeValue(ostream& ss) const;
-
-	/**
-	 * \brief Serializes the variable into a string.
-	 *
-	 * @param ss A stream where the variable (type, name, and value)
-	 *	will be appended.
-	 * @param context Serialization context (tab indentation, etc).
-	 */
-	void Serialize(ostream& ss, SerializationContext& context) const;
-
-	/**
-	 * \brief Copy the value from another variable into this variable.
-	 *
-	 * @param otherVariable The variable to copy from.
-	 * @return True if the value was copied, false if copying was not
-	 *	possible (i.e. the types differed).
-	 */
-	bool CopyValueFrom(const StateVariable& otherVariable);
-
-	/**
-	 * \brief Returns the variable as a readable string.
-	 *
-	 * @return A string, representing the variable's value.
-	 */
-	string ToString() const;
-
-	/**
-	 * \brief Returns the variable as an unsignedinteger value.
-	 *
-	 * @return A uint64_t, representing the variable's value.
-	 */
-	uint64_t ToInteger() const;
-
-	/**
-	 * \brief Returns the variable as a double value.
-	 *
-	 * @return A double, representing the variable's value.
-	 */
-	double ToDouble() const;
-
-	/**
-	 * \brief Set the variable's value, using a string expression.
-	 *
-	 * Note that the expression may be a single value (e.g. <tt>42</tt>),
-	 * or something more complex (e.g. <tt>123 + cpu0.pc * 4</tt>).
-	 *
-	 * When setting string values, the expression should be a C-style
-	 * escaped string, e.g.: <tt>"This is a string with a \" inside
-	 * it."</tt>
-	 *
-	 * @param expression The new value.
-	 * @return True if the value was set, false if e.g. there was a
-	 *	parse error.
-	 */
-	bool SetValue(const string& expression);
-
-	/**
-	 * \brief Set the variable's value to an integer.
-	 *
-	 * @param value The new value.
-	 * @return True if the value was set, false if e.g. there was a
-	 *	type error.
-	 */
-	bool SetValue(uint64_t value);
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-private:
-	/**
-	 * \brief Evaluates an expression, and returns it as a single value.
-	 *
-	 * @param expression The expression to evaluate.
-	 * @param success Set to true if the expression could be evaluated,
-	 *	false otherwise.
-	 * @return A string representation of the evaluated expression.
-	 *	(Only valid if <tt>success</tt> was set to true.)
-	 */
-	string EvaluateExpression(const string& expression,
-		bool &success) const;
-
-	/**
-	 * \brief Returns the type of the variable, as a string.
-	 *
-	 * @return A string representation of the variable's type.
-	 */
-	string GetTypeString() const;
-
-	/**
-	 * \brief Returns a string representation of the variable's value.
-	 *
-	 * @return A string representation of the variable's value.
-	 */
-	string ValueToString() const;
-
-private:
-	string			m_name;
-	enum Type		m_type;
-	
-	union {
-		string*		pstr;
-		bool*		pbool;
-		double*		pdouble;
-		uint8_t*	puint8;
-		uint16_t*	puint16;
-		uint32_t*	puint32;
-		uint64_t*	puint64;
-		int8_t*		psint8;
-		int16_t*	psint16;
-		int32_t*	psint32;
-		int64_t*	psint64;
-		CustomStateVariableHandler *phandler;
-	} m_value;
-};
-
-
-#endif	// STATEVARIABLE_H
diff -Nru gxemul-0.6.2/src/include/StringHelper.h gxemul-0.7.0+dfsg/src/include/StringHelper.h
--- gxemul-0.6.2/src/include/StringHelper.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/StringHelper.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,80 +0,0 @@
-#ifndef STRINGHELPER_H
-#define	STRINGHELPER_H
-
-/*
- *  Copyright (C) 2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "UnitTest.h"
-
-
-/**
- * \brief A helper class, with static functions for common string operations.
- */
-class StringHelper
-	: public UnitTestable
-{
-private:
-	/**
-	 * \brief No constructor.
-	 */
-	StringHelper();
-
-public:
-	/**
-	 * \brief Parses a string into a 64-bit number.
-	 *
-	 * @param str A pointer to a character string.
-	 * @param error Set to false if a parsed value is returned, true on
-	 *	parse errors.
-	 * @return A uint64_t, representing the parsed value.
-	 */
-	static uint64_t ParseNumber(const char* str, bool& error);
-
-	/**
-	 * \brief Splits a string with a certain delimiter into a vector of strings.
-	 *
-	 * E.g. if the input string is "A:B:C" and the splitter is ':', then
-	 * the resulting vector consists of 3 strings: "A", "B", and "C".
-	 *
-	 * NOTE: The current implementation is very slow, but it at least it works.
-	 *
-	 * @param str A string to split.
-	 * @param splitter Set to false if a parsed value is returned, true on
-	 *	parse errors.
-	 * @return A vector of strings (without the splitter char).
-	 */
-	static vector<string> SplitStringIntoVector(const string &str, const char splitter);
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-#endif	// STRINGHELPER_H
diff -Nru gxemul-0.6.2/src/include/SymbolRegistry.h gxemul-0.7.0+dfsg/src/include/SymbolRegistry.h
--- gxemul-0.6.2/src/include/SymbolRegistry.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/SymbolRegistry.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,87 +0,0 @@
-#ifndef SYMBOLREGISTRY_H
-#define	SYMBOLREGISTRY_H
-
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include "UnitTest.h"
-
-
-/**
- * \brief A registry for loaded symbols.
- */
-class SymbolRegistry
-	: public UnitTestable
-{
-public:
-	/**
-	 * \brief Constructs a SymbolRegistry.
-	 */
-	SymbolRegistry();
-
-	/**
-	 * \brief Clears the registry.
-	 */
-	void Clear();
-
-	/**
-	 * \brief Adds a symbol to the registry.
-	 *
-	 * @param symbol The symbol name.
-	 * @param vaddr The virtual address.
-	 */
-	void AddSymbol(const string& symbol, uint64_t vaddr);
-
-	/**
-	 * \brief Looks up an address.
-	 *
-	 * The returned address may be of the format "symbol+offset", where
-	 * offset is a hexadecimal number, if allowOffset is true.
-	 *
-	 * @param vaddr The virtual address.
-	 * @param allowOffset If false, the address must be found exactly.
-	 *	If true, a symbol which almost matches the address, plus an
-	 *	offset, may be returned.
-	 * @return A string representing the address, or an empty string
-	 *	if no suitable match was found.
-	 */
-	string LookupAddress(uint64_t vaddr, bool allowOffset) const;
-
-
-	/********************************************************************/
-
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-
-private:
-	typedef map<uint64_t,string> SymbolMap;
-	SymbolMap	m_map;
-};
-
-
-#endif	// SYMBOLREGISTRY_H
diff -Nru gxemul-0.6.2/src/include/testmachine/README gxemul-0.7.0+dfsg/src/include/testmachine/README
--- gxemul-0.6.2/src/include/testmachine/README	2019-06-22 18:23:24.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/testmachine/README	2021-11-27 09:42:23.000000000 +0000
@@ -16,10 +16,10 @@
 	ethernet frames on the simulated network.
 
   o)  framebuffer (dev_fb):
-	640 x 480 pixels, 3 bytes per pixel, red-green-blue
+	Defaults to 640 x 480 pixels, 3 bytes per pixel, red-green-blue.
 
   o)  interrupt controller (dev_irqc):
-	A generic interrupt controller. (Not used by the MIPS test machine.)
+	A generic interrupt controller. (Only for non-MIPS test machines.)
 
   o)  mp (dev_mp):
 	A multiprocessor inter-processor communication device.
diff -Nru gxemul-0.6.2/src/include/thirdparty/bootblock.h gxemul-0.7.0+dfsg/src/include/thirdparty/bootblock.h
--- gxemul-0.6.2/src/include/thirdparty/bootblock.h	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/thirdparty/bootblock.h	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1474 @@
+/*	$NetBSD: bootblock.h,v 1.58 2017/04/29 00:05:35 nonaka Exp $	*/
+
+/*-
+ * Copyright (c) 2002-2004 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*-
+ * Copyright (C) 1993	Allen K. Briggs, Chris P. Caputo,
+ *			Michael L. Finch, Bradley A. Grantham, and
+ *			Lawrence A. Kesteloot
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the Alice Group.
+ * 4. The names of the Alice Group or any of its members may not be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ALICE GROUP ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE ALICE GROUP BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+ * Copyright (c) 1994, 1999 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Christopher G. Demetriou
+ *      for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Copyright (c) 1994 Rolf Grossmann
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Rolf Grossmann.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SYS_BOOTBLOCK_H
+#define	_SYS_BOOTBLOCK_H
+
+#ifdef __attribute__
+#undef __attribute__
+#endif
+
+#ifdef __noreturn__
+#undef __noreturn__
+#endif
+
+#define __attribute__(x)  /*  */
+#define __noreturn__  /*  */
+
+#if !defined(__ASSEMBLER__)
+#if defined(_KERNEL) || defined(_STANDALONE)
+#include <sys/stdint.h>
+#else
+#include <stdint.h>
+#endif
+#endif	/* !defined(__ASSEMBLER__) */
+
+/* ------------------------------------------
+ * MBR (Master Boot Record) --
+ *	definitions for systems that use MBRs
+ */
+
+/*
+ * Layout of boot records:
+ *
+ *	Byte range	Use	Description
+ *	----------	---	-----------
+ *
+ *	0 - 2		FMP	JMP xxx, NOP
+ *	3 - 10		FP	OEM Name
+ *
+ *	11 - 61		FMP	FAT12/16 BPB
+ *				Whilst not strictly necessary for MBR,
+ *				GRUB reserves this area
+ *
+ *	11 - 89		P	FAT32 BPB
+ *				(are we ever going to boot off this?)
+ *
+ *
+ *	62 - 217	FMP	Boot code
+ *
+ *	90 - 217	P	FAT32 boot code
+ *
+ *	218 - 223	M	Win95b/98/me "drive time"
+ *		http://www.geocities.com/thestarman3/asm/mbr/95BMEMBR.htm#MYST
+ *				only changed if all 6 bytes are 0
+ *
+ *	224 - 436	FMP	boot code (continued)
+ *
+ *	437 - 439	M	WinNT/2K/XP MBR "boot language"
+ *		http://www.geocities.com/thestarman3/asm/mbr/Win2kmbr.htm
+ *				not needed by us
+ *
+ *	400 - 439	MP	NetBSD: mbr_bootsel
+ *
+ *	424 - 439	M	NetBSD: bootptn_guid (in GPT PMBR only)
+ *
+ *	440 - 443	M	WinNT/2K/XP Drive Serial Number (NT DSN)
+ *		http://www.geocities.com/thestarman3/asm/mbr/Win2kmbr.htm
+ *
+ *	444 - 445	FMP	bootcode or unused
+ *				NetBSD: mbr_bootsel_magic
+ *
+ *	446 - 509	M	partition table
+ *
+ *	510 - 511	FMP	magic number (0xAA55)
+ *
+ *	Use:
+ *	----
+ *	F	Floppy boot sector
+ *	M	Master Boot Record
+ *	P	Partition Boot record
+ *
+ */
+
+/*
+ * MBR (Master Boot Record)
+ */
+#define	MBR_BBSECTOR		0	/* MBR relative sector # */
+#define	MBR_BPB_OFFSET		11	/* offsetof(mbr_sector, mbr_bpb) */
+#define	MBR_BOOTCODE_OFFSET	90	/* offsetof(mbr_sector, mbr_bootcode) */
+#define	MBR_BS_OFFSET		400	/* offsetof(mbr_sector, mbr_bootsel) */
+#define	MBR_BS_OLD_OFFSET	404	/* where mbr_bootsel used to be */
+#define	MBR_GPT_GUID_OFFSET	424	/* location of partition GUID to boot */
+#define	MBR_GPT_GUID_DEFAULT		/* default uninitialized GUID */ \
+	{0xeee69d04,0x02f4,0x11e0,0x8f,0x5d,{0x00,0xe0,0x81,0x52,0x9a,0x6b}}
+#define	MBR_DSN_OFFSET		440	/* offsetof(mbr_sector, mbr_dsn) */
+#define	MBR_BS_MAGIC_OFFSET	444	/* offsetof(mbr_sector, mbr_bootsel_magic) */
+#define	MBR_PART_OFFSET		446	/* offsetof(mbr_sector, mbr_part[0]) */
+#define	MBR_MAGIC_OFFSET	510	/* offsetof(mbr_sector, mbr_magic) */
+#define	MBR_MAGIC		0xaa55	/* MBR magic number */
+#define	MBR_BS_MAGIC		0xb5e1	/* mbr_bootsel magic number */
+#define	MBR_PART_COUNT		4	/* Number of partitions in MBR */
+#define	MBR_BS_PARTNAMESIZE	8	/* Size of name mbr_bootsel nametab */
+					/* (excluding trailing NUL) */
+
+		/* values for mbr_partition.mbrp_flag */
+#define	MBR_PFLAG_ACTIVE	0x80	/* The active partition */
+
+		/* values for mbr_partition.mbrp_type */
+#define	MBR_PTYPE_UNUSED	0x00	/* Unused */
+#define	MBR_PTYPE_FAT12		0x01	/* 12-bit FAT */
+#define	MBR_PTYPE_XENIX_ROOT	0x02	/* XENIX / */
+#define	MBR_PTYPE_XENIX_USR	0x03	/* XENIX /usr */
+#define	MBR_PTYPE_FAT16S	0x04	/* 16-bit FAT, less than 32M */
+#define	MBR_PTYPE_EXT		0x05	/* extended partition */
+#define	MBR_PTYPE_FAT16B	0x06	/* 16-bit FAT, more than 32M */
+#define	MBR_PTYPE_NTFS		0x07	/* OS/2 HPFS, NTFS, QNX2, Adv. UNIX */
+#define	MBR_PTYPE_DELL		0x08	/* AIX or os, or etc. */
+#define MBR_PTYPE_AIX_BOOT	0x09	/* AIX boot partition or Coherent */
+#define MBR_PTYPE_OS2_BOOT	0x0a	/* O/2 boot manager or Coherent swap */
+#define	MBR_PTYPE_FAT32		0x0b	/* 32-bit FAT */
+#define	MBR_PTYPE_FAT32L	0x0c	/* 32-bit FAT, LBA-mapped */
+#define	MBR_PTYPE_7XXX		0x0d	/* 7XXX, LBA-mapped */
+#define	MBR_PTYPE_FAT16L	0x0e	/* 16-bit FAT, LBA-mapped */
+#define	MBR_PTYPE_EXT_LBA	0x0f	/* extended partition, LBA-mapped */
+#define	MBR_PTYPE_OPUS		0x10	/* OPUS */
+#define MBR_PTYPE_OS2_DOS12	0x11 	/* OS/2 DOS 12-bit FAT */
+#define MBR_PTYPE_COMPAQ_DIAG	0x12 	/* Compaq diagnostics */
+#define MBR_PTYPE_OS2_DOS16S	0x14 	/* OS/2 DOS 16-bit FAT <32M */
+#define MBR_PTYPE_OS2_DOS16B	0x16 	/* OS/2 DOS 16-bit FAT >=32M */
+#define MBR_PTYPE_OS2_IFS	0x17 	/* OS/2 hidden IFS */
+#define MBR_PTYPE_AST_SWAP	0x18 	/* AST Windows swapfile */
+#define MBR_PTYPE_WILLOWTECH	0x19 	/* Willowtech Photon coS */
+#define MBR_PTYPE_HID_FAT32	0x1b 	/* hidden win95 fat 32 */
+#define MBR_PTYPE_HID_FAT32_LBA	0x1c 	/* hidden win95 fat 32 lba */
+#define MBR_PTYPE_HID_FAT16_LBA	0x1d	/* hidden win95 fat 16 lba */
+#define MBR_PTYPE_WILLOWSOFT	0x20 	/* Willowsoft OFS1 */
+#define MBR_PTYPE_RESERVED_x21	0x21 	/* reserved */
+#define MBR_PTYPE_RESERVED_x23	0x23 	/* reserved */
+#define MBR_PTYPE_RESERVED_x24	0x24	/* NEC DOS */
+#define MBR_PTYPE_RESERVED_x26	0x26 	/* reserved */
+#define MBR_PTYPE_RESERVED_x31	0x31 	/* reserved */
+#define MBR_PTYPE_NOS		0x32	/* Alien Internet Services NOS */
+#define MBR_PTYPE_RESERVED_x33	0x33 	/* reserved */
+#define MBR_PTYPE_RESERVED_x34	0x34 	/* reserved */
+#define MBR_PTYPE_OS2_JFS	0x35 	/* JFS on OS2 */
+#define MBR_PTYPE_RESERVED_x36	0x36 	/* reserved */
+#define MBR_PTYPE_THEOS		0x38 	/* Theos */
+#define MBR_PTYPE_PLAN9		0x39 	/* Plan 9, or Theos spanned */
+#define MBR_PTYPE_THEOS_4GB	0x3a 	/* Theos ver 4 4gb partition */
+#define MBR_PTYPE_THEOS_EXT	0x3b 	/* Theos ve 4 extended partition */
+#define MBR_PTYPE_PMRECOVERY	0x3c 	/* PartitionMagic recovery */
+#define MBR_PTYPE_HID_NETWARE	0x3d 	/* Hidden Netware */
+#define MBR_PTYPE_VENIX		0x40 	/* VENIX 286 or LynxOS */
+#define	MBR_PTYPE_PREP		0x41	/* PReP */
+#define	MBR_PTYPE_DRDOS_LSWAP	0x42	/* linux swap sharing DRDOS disk */
+#define	MBR_PTYPE_DRDOS_LINUX	0x43	/* linux sharing DRDOS disk */
+#define	MBR_PTYPE_GOBACK	0x44	/* GoBack change utility */
+#define	MBR_PTYPE_BOOT_US	0x45	/* Boot US Boot manager */
+#define	MBR_PTYPE_EUMEL_x46	0x46	/* EUMEL/Elan or Ergos 3 */
+#define	MBR_PTYPE_EUMEL_x47	0x47	/* EUMEL/Elan or Ergos 3 */
+#define	MBR_PTYPE_EUMEL_x48	0x48	/* EUMEL/Elan or Ergos 3 */
+#define	MBR_PTYPE_ALFS_THIN	0x4a	/* ALFX/THIN filesystem for DOS */
+#define	MBR_PTYPE_OBERON	0x4c	/* Oberon partition */
+#define MBR_PTYPE_QNX4X		0x4d 	/* QNX4.x */
+#define MBR_PTYPE_QNX4X_2	0x4e 	/* QNX4.x 2nd part */
+#define MBR_PTYPE_QNX4X_3	0x4f 	/* QNX4.x 3rd part */
+#define MBR_PTYPE_DM		0x50 	/* DM (disk manager) */
+#define MBR_PTYPE_DM6_AUX1	0x51 	/* DM6 Aux1 (or Novell) */
+#define MBR_PTYPE_CPM		0x52 	/* CP/M or Microport SysV/AT */
+#define MBR_PTYPE_DM6_AUX3	0x53 	/* DM6 Aux3 */
+#define	MBR_PTYPE_DM6_DDO	0x54	/* DM6 DDO */
+#define MBR_PTYPE_EZDRIVE	0x55	/* EZ-Drive (disk manager) */
+#define MBR_PTYPE_GOLDEN_BOW	0x56	/* Golden Bow (disk manager) */
+#define MBR_PTYPE_DRIVE_PRO	0x57	/* Drive PRO */
+#define MBR_PTYPE_PRIAM_EDISK	0x5c	/* Priam Edisk (disk manager) */
+#define MBR_PTYPE_SPEEDSTOR	0x61	/* SpeedStor */
+#define MBR_PTYPE_HURD		0x63	/* GNU HURD or Mach or Sys V/386 */
+#define MBR_PTYPE_NOVELL_2XX	0x64	/* Novell Netware 2.xx or Speedstore */
+#define MBR_PTYPE_NOVELL_3XX	0x65	/* Novell Netware 3.xx */
+#define MBR_PTYPE_NOVELL_386	0x66	/* Novell 386 Netware */
+#define MBR_PTYPE_NOVELL_x67	0x67	/* Novell */
+#define MBR_PTYPE_NOVELL_x68	0x68	/* Novell */
+#define MBR_PTYPE_NOVELL_x69	0x69	/* Novell */
+#define MBR_PTYPE_DISKSECURE	0x70	/* DiskSecure Multi-Boot */
+#define MBR_PTYPE_RESERVED_x71	0x71	/* reserved */
+#define MBR_PTYPE_RESERVED_x73	0x73	/* reserved */
+#define MBR_PTYPE_RESERVED_x74	0x74	/* reserved */
+#define MBR_PTYPE_PCIX		0x75	/* PC/IX */
+#define MBR_PTYPE_RESERVED_x76	0x76	/* reserved */
+#define MBR_PTYPE_M2FS_M2CS	0x77	/* M2FS/M2CS partition */
+#define MBR_PTYPE_XOSL_FS	0x78	/* XOSL boot loader filesystem */
+#define MBR_PTYPE_MINIX_14A	0x80	/* MINIX until 1.4a */
+#define MBR_PTYPE_MINIX_14B	0x81	/* MINIX since 1.4b */
+#define	MBR_PTYPE_LNXSWAP	0x82	/* Linux swap or Solaris */
+#define	MBR_PTYPE_LNXEXT2	0x83	/* Linux native */
+#define MBR_PTYPE_OS2_C		0x84	/* OS/2 hidden C: drive */
+#define	MBR_PTYPE_EXT_LNX	0x85	/* Linux extended partition */
+#define	MBR_PTYPE_NTFATVOL 	0x86	/* NT FAT volume set */
+#define	MBR_PTYPE_NTFSVOL	0x87	/* NTFS volume set or HPFS mirrored */
+#define	MBR_PTYPE_LNX_KERNEL	0x8a	/* Linux Kernel AiR-BOOT partition */
+#define	MBR_PTYPE_FT_FAT32	0x8b	/* Legacy Fault tolerant FAT32 */
+#define	MBR_PTYPE_FT_FAT32_EXT	0x8c	/* Legacy Fault tolerant FAT32 ext */
+#define	MBR_PTYPE_HID_FR_FD_12	0x8d	/* Hidden free FDISK FAT12 */
+#define	MBR_PTYPE_LNX_LVM	0x8e	/* Linux Logical Volume Manager */
+#define	MBR_PTYPE_HID_FR_FD_16	0x90	/* Hidden free FDISK FAT16 */
+#define	MBR_PTYPE_HID_FR_FD_EXT	0x91	/* Hidden free FDISK DOS EXT */
+#define	MBR_PTYPE_HID_FR_FD_16B	0x92	/* Hidden free FDISK FAT16 Big */
+#define MBR_PTYPE_AMOEBA_FS 	0x93	/* Amoeba filesystem */
+#define MBR_PTYPE_AMOEBA_BAD 	0x94	/* Amoeba bad block table */
+#define MBR_PTYPE_MIT_EXOPC 	0x95	/* MIT EXOPC native partitions */
+#define	MBR_PTYPE_HID_FR_FD_32	0x97	/* Hidden free FDISK FAT32 */
+#define	MBR_PTYPE_DATALIGHT	0x98	/* Datalight ROM-DOS Super-Boot */
+#define MBR_PTYPE_MYLEX 	0x99	/* Mylex EISA SCSI */
+#define	MBR_PTYPE_HID_FR_FD_16L	0x9a	/* Hidden free FDISK FAT16 LBA */
+#define	MBR_PTYPE_HID_FR_FD_EXL	0x9b	/* Hidden free FDISK EXT LBA */
+#define MBR_PTYPE_BSDI	 	0x9f	/* BSDI? */
+#define MBR_PTYPE_IBM_HIB	0xa0	/* IBM Thinkpad hibernation */
+#define MBR_PTYPE_HP_VOL_xA1	0xa1	/* HP Volume expansion (SpeedStor) */
+#define MBR_PTYPE_HP_VOL_xA3	0xa3	/* HP Volume expansion (SpeedStor) */
+#define MBR_PTYPE_HP_VOL_xA4	0xa4	/* HP Volume expansion (SpeedStor) */
+#define	MBR_PTYPE_386BSD	0xa5	/* 386BSD partition type */
+#define	MBR_PTYPE_OPENBSD	0xa6	/* OpenBSD partition type */
+#define	MBR_PTYPE_NEXTSTEP_486 	0xa7	/* NeXTSTEP 486 */
+#define	MBR_PTYPE_APPLE_UFS 	0xa8	/* Apple UFS */
+#define	MBR_PTYPE_NETBSD	0xa9	/* NetBSD partition type */
+#define MBR_PTYPE_OLIVETTI	0xaa	/* Olivetty Fat12 1.44MB Service part */
+#define MBR_PTYPE_APPLE_BOOT	0xab	/* Apple Boot */
+#define MBR_PTYPE_SHAG_OS	0xae	/* SHAG OS filesystem */
+#define MBR_PTYPE_APPLE_HFS	0xaf	/* Apple HFS */
+#define MBR_PTYPE_BOOTSTAR_DUM	0xb0	/* BootStar Dummy */
+#define MBR_PTYPE_RESERVED_xB1	0xb1	/* reserved */
+#define MBR_PTYPE_RESERVED_xB3	0xb3	/* reserved */
+#define MBR_PTYPE_RESERVED_xB4	0xb4	/* reserved */
+#define MBR_PTYPE_RESERVED_xB6	0xb6	/* reserved */
+#define MBR_PTYPE_BSDI_386	0xb7	/* BSDI BSD/386 filesystem */
+#define MBR_PTYPE_BSDI_SWAP	0xb8	/* BSDI BSD/386 swap */
+#define	MBR_PTYPE_BOOT_WIZARD	0xbb	/* Boot Wizard Hidden */
+#define	MBR_PTYPE_SOLARIS_8	0xbe	/* Solaris 8 partition type */
+#define	MBR_PTYPE_SOLARIS	0xbf	/* Solaris partition type */
+#define MBR_PTYPE_CTOS		0xc0 	/* CTOS */
+#define MBR_PTYPE_DRDOS_FAT12	0xc1 	/* DRDOS/sec (FAT-12) */
+#define MBR_PTYPE_HID_LNX	0xc2 	/* Hidden Linux */
+#define MBR_PTYPE_HID_LNX_SWAP	0xc3 	/* Hidden Linux swap */
+#define MBR_PTYPE_DRDOS_FAT16S	0xc4 	/* DRDOS/sec (FAT-16, < 32M) */
+#define MBR_PTYPE_DRDOS_EXT	0xc5 	/* DRDOS/sec (EXT) */
+#define MBR_PTYPE_DRDOS_FAT16B	0xc6 	/* DRDOS/sec (FAT-16, >= 32M) */
+#define MBR_PTYPE_SYRINX	0xc7 	/* Syrinx (Cyrnix?) or HPFS disabled */
+#define MBR_PTYPE_DRDOS_8_xC8	0xc8 	/* Reserved for DR-DOS 8.0+ */
+#define MBR_PTYPE_DRDOS_8_xC9	0xc9 	/* Reserved for DR-DOS 8.0+ */
+#define MBR_PTYPE_DRDOS_8_xCA	0xca 	/* Reserved for DR-DOS 8.0+ */
+#define MBR_PTYPE_DRDOS_74_CHS	0xcb 	/* DR-DOS 7.04+ Secured FAT32 CHS */
+#define MBR_PTYPE_DRDOS_74_LBA	0xcc 	/* DR-DOS 7.04+ Secured FAT32 LBA */
+#define MBR_PTYPE_CTOS_MEMDUMP	0xcd	/* CTOS Memdump */
+#define MBR_PTYPE_DRDOS_74_16X	0xce 	/* DR-DOS 7.04+ FAT16X LBA */
+#define MBR_PTYPE_DRDOS_74_EXT	0xcf 	/* DR-DOS 7.04+ EXT LBA */
+#define MBR_PTYPE_REAL32	0xd0 	/* REAL/32 secure big partition */
+#define MBR_PTYPE_MDOS_FAT12	0xd1 	/* Old Multiuser DOS FAT12 */
+#define MBR_PTYPE_MDOS_FAT16S	0xd4 	/* Old Multiuser DOS FAT16 Small */
+#define MBR_PTYPE_MDOS_EXT	0xd5 	/* Old Multiuser DOS Extended */
+#define MBR_PTYPE_MDOS_FAT16B	0xd6 	/* Old Multiuser DOS FAT16 Big */
+#define MBR_PTYPE_CPM_86	0xd8 	/* CP/M 86 */
+#define MBR_PTYPE_CONCURRENT	0xdb 	/* CP/M or Concurrent CP/M */
+#define MBR_PTYPE_HID_CTOS_MEM	0xdd 	/* Hidden CTOS Memdump */
+#define MBR_PTYPE_DELL_UTIL	0xde 	/* Dell PowerEdge Server utilities */
+#define MBR_PTYPE_DGUX_VIRTUAL	0xdf 	/* DG/UX virtual disk manager */
+#define MBR_PTYPE_STMICROELEC	0xe0 	/* STMicroelectronics ST AVFS */
+#define MBR_PTYPE_DOS_ACCESS	0xe1 	/* DOS access or SpeedStor 12-bit */
+#define MBR_PTYPE_STORDIM	0xe3 	/* DOS R/O or Storage Dimensions */
+#define MBR_PTYPE_SPEEDSTOR_16S	0xe4 	/* SpeedStor 16-bit FAT < 1024 cyl. */
+#define MBR_PTYPE_RESERVED_xE5	0xe5	/* reserved */
+#define MBR_PTYPE_RESERVED_xE6	0xe6	/* reserved */
+#define MBR_PTYPE_BEOS		0xeb 	/* BeOS */
+#define	MBR_PTYPE_PMBR		0xee	/* GPT Protective MBR */
+#define	MBR_PTYPE_EFI		0xef	/* EFI system partition */
+#define MBR_PTYPE_LNX_PA_RISC	0xf0 	/* Linux PA-RISC boot loader */
+#define MBR_PTYPE_SPEEDSTOR_X	0xf1 	/* SpeedStor or Storage Dimensions */
+#define MBR_PTYPE_DOS33_SEC	0xf2 	/* DOS 3.3+ Secondary */
+#define MBR_PTYPE_RESERVED_xF3	0xf3	/* reserved */
+#define MBR_PTYPE_SPEEDSTOR_L	0xf4	/* SpeedStor large partition */
+#define MBR_PTYPE_PROLOGUE	0xf5	/* Prologue multi-volumen partition */
+#define MBR_PTYPE_RESERVED_xF6	0xf6 	/* reserved */
+#define MBR_PTYPE_PCACHE	0xf9 	/* pCache: ext2/ext3 persistent cache */
+#define MBR_PTYPE_BOCHS		0xfa 	/* Bochs x86 emulator */
+#define MBR_PTYPE_VMWARE	0xfb 	/* VMware File System */
+#define MBR_PTYPE_VMWARE_SWAP	0xfc 	/* VMware Swap */
+#define MBR_PTYPE_LNX_RAID	0xfd 	/* Linux RAID partition persistent sb */
+#define MBR_PTYPE_LANSTEP	0xfe	/* LANstep or IBM PS/2 IML */
+#define MBR_PTYPE_XENIX_BAD	0xff 	/* Xenix Bad Block Table */
+
+#ifdef MBRPTYPENAMES
+static const struct mbr_ptype {
+	int id;
+	const char *name;
+} mbr_ptypes[] = {
+	{ MBR_PTYPE_UNUSED, "<UNUSED>" },
+	{ MBR_PTYPE_FAT12, "Primary DOS with 12 bit FAT" },
+	{ MBR_PTYPE_XENIX_ROOT, "XENIX / filesystem" },
+	{ MBR_PTYPE_XENIX_USR, "XENIX /usr filesystem" },
+	{ MBR_PTYPE_FAT16S, "Primary DOS with 16 bit FAT <32M" },
+	{ MBR_PTYPE_EXT, "Extended partition" },
+	{ MBR_PTYPE_FAT16B, "Primary 'big' DOS, 16-bit FAT (> 32MB)" },
+	{ MBR_PTYPE_NTFS, "NTFS, OS/2 HPFS, QNX2 or Advanced UNIX" },
+	{ MBR_PTYPE_DELL, "AIX filesystem or OS/2 (thru v1.3) or DELL "
+			  "multiple drives or Commodore DOS or SplitDrive" },
+	{ MBR_PTYPE_AIX_BOOT, "AIX boot partition or Coherent" },
+	{ MBR_PTYPE_OS2_BOOT, "OS/2 Boot Manager or Coherent swap or OPUS" },
+	{ MBR_PTYPE_FAT32, "Primary DOS with 32 bit FAT" },
+	{ MBR_PTYPE_FAT32L, "Primary DOS with 32 bit FAT - LBA" },
+	{ MBR_PTYPE_7XXX, "Type 7??? - LBA" },
+	{ MBR_PTYPE_FAT16L, "DOS (16-bit FAT) - LBA" },
+	{ MBR_PTYPE_EXT_LBA, "Ext. partition - LBA" },
+	{ MBR_PTYPE_OPUS, "OPUS" },
+	{ MBR_PTYPE_OS2_DOS12, "OS/2 BM: hidden DOS 12-bit FAT" },
+	{ MBR_PTYPE_COMPAQ_DIAG, "Compaq diagnostics" },
+	{ MBR_PTYPE_OS2_DOS16S, "OS/2 BM: hidden DOS 16-bit FAT <32M "
+				"or Novell DOS 7.0 bug" },
+	{ MBR_PTYPE_OS2_DOS16B, "OS/2 BM: hidden DOS 16-bit FAT >=32M" },
+	{ MBR_PTYPE_OS2_IFS, "OS/2 BM: hidden IFS" },
+	{ MBR_PTYPE_AST_SWAP, "AST Windows swapfile" },
+	{ MBR_PTYPE_WILLOWTECH, "Willowtech Photon coS" },
+	{ MBR_PTYPE_HID_FAT32, "hidden Windows/95 FAT32" },
+	{ MBR_PTYPE_HID_FAT32_LBA, "hidden Windows/95 FAT32 LBA" },
+	{ MBR_PTYPE_HID_FAT16_LBA, "hidden Windows/95 FAT16 LBA" },
+	{ MBR_PTYPE_WILLOWSOFT, "Willowsoft OFS1" },
+	{ MBR_PTYPE_RESERVED_x21, "reserved" },
+	{ MBR_PTYPE_RESERVED_x23, "reserved" },
+	{ MBR_PTYPE_RESERVED_x24, "NEC DOS"},
+	{ MBR_PTYPE_RESERVED_x26, "reserved" },
+	{ MBR_PTYPE_RESERVED_x31, "reserved" },
+	{ MBR_PTYPE_NOS, "Alien Internet Services NOS" },
+	{ MBR_PTYPE_RESERVED_x33, "reserved" },
+	{ MBR_PTYPE_RESERVED_x34, "reserved" },
+	{ MBR_PTYPE_OS2_JFS, "JFS on OS2" },
+	{ MBR_PTYPE_RESERVED_x36, "reserved" },
+	{ MBR_PTYPE_THEOS, "Theos" },
+	{ MBR_PTYPE_PLAN9, "Plan 9" },
+	{ MBR_PTYPE_PLAN9, "Plan 9, or Theos spanned" },
+	{ MBR_PTYPE_THEOS_4GB,	"Theos ver 4 4gb partition" },
+	{ MBR_PTYPE_THEOS_EXT,	"Theos ve 4 extended partition" },
+	{ MBR_PTYPE_PMRECOVERY, "PartitionMagic recovery" },
+	{ MBR_PTYPE_HID_NETWARE, "Hidden Netware" },
+	{ MBR_PTYPE_VENIX, "VENIX 286 or LynxOS" },
+	{ MBR_PTYPE_PREP, "Linux/MINIX (sharing disk with DRDOS) "
+			  "or Personal RISC boot" },
+	{ MBR_PTYPE_DRDOS_LSWAP, "SFS or Linux swap "
+				 "(sharing disk with DRDOS)" },
+	{ MBR_PTYPE_DRDOS_LINUX, "Linux native (sharing disk with DRDOS)" },
+	{ MBR_PTYPE_GOBACK, "GoBack change utility" },
+	{ MBR_PTYPE_BOOT_US, "Boot US Boot manager" },
+	{ MBR_PTYPE_EUMEL_x46, "EUMEL/Elan or Ergos 3" },
+	{ MBR_PTYPE_EUMEL_x47, "EUMEL/Elan or Ergos 3" },
+	{ MBR_PTYPE_EUMEL_x48, "EUMEL/Elan or Ergos 3" },
+	{ MBR_PTYPE_ALFS_THIN, "ALFX/THIN filesystem for DOS" },
+	{ MBR_PTYPE_OBERON, "Oberon partition" },
+	{ MBR_PTYPE_QNX4X, "QNX4.x" },
+	{ MBR_PTYPE_QNX4X_2, "QNX4.x 2nd part" },
+	{ MBR_PTYPE_QNX4X_3, "QNX4.x 3rd part" },
+	{ MBR_PTYPE_DM, "DM (disk manager)" },
+	{ MBR_PTYPE_DM6_AUX1, "DM6 Aux1 (or Novell)" },
+	{ MBR_PTYPE_CPM, "CP/M or Microport SysV/AT" },
+	{ MBR_PTYPE_DM6_AUX3, "DM6 Aux3" },
+	{ MBR_PTYPE_DM6_DDO, "DM6 DDO" },
+	{ MBR_PTYPE_EZDRIVE, "EZ-Drive (disk manager)" },
+	{ MBR_PTYPE_GOLDEN_BOW, "Golden Bow (disk manager)" },
+	{ MBR_PTYPE_DRIVE_PRO, "Drive PRO" },
+	{ MBR_PTYPE_PRIAM_EDISK, "Priam Edisk (disk manager)" },
+	{ MBR_PTYPE_SPEEDSTOR, "SpeedStor" },
+	{ MBR_PTYPE_HURD, "GNU HURD or Mach or Sys V/386 "
+			  "(such as ISC UNIX) or MtXinu" },
+	{ MBR_PTYPE_NOVELL_2XX, "Novell Netware 2.xx or Speedstore" },
+	{ MBR_PTYPE_NOVELL_3XX, "Novell Netware 3.xx" },
+	{ MBR_PTYPE_NOVELL_386, "Novell 386 Netware" },
+	{ MBR_PTYPE_NOVELL_x67, "Novell" },
+	{ MBR_PTYPE_NOVELL_x68, "Novell" },
+	{ MBR_PTYPE_NOVELL_x69, "Novell" },
+	{ MBR_PTYPE_DISKSECURE, "DiskSecure Multi-Boot" },
+	{ MBR_PTYPE_RESERVED_x71, "reserved" },
+	{ MBR_PTYPE_RESERVED_x73, "reserved" },
+	{ MBR_PTYPE_RESERVED_x74, "reserved" },
+	{ MBR_PTYPE_PCIX, "PC/IX" },
+	{ MBR_PTYPE_RESERVED_x76, "reserved" },
+	{ MBR_PTYPE_M2FS_M2CS,	"M2FS/M2CS partition" },
+	{ MBR_PTYPE_XOSL_FS, "XOSL boot loader filesystem" },
+	{ MBR_PTYPE_MINIX_14A, "MINIX until 1.4a" },
+	{ MBR_PTYPE_MINIX_14B, "MINIX since 1.4b, early Linux, Mitac dmgr" },
+	{ MBR_PTYPE_LNXSWAP, "Linux swap or Prime or Solaris" },
+	{ MBR_PTYPE_LNXEXT2, "Linux native" },
+	{ MBR_PTYPE_OS2_C, "OS/2 hidden C: drive" },
+	{ MBR_PTYPE_EXT_LNX, "Linux extended" },
+	{ MBR_PTYPE_NTFATVOL, "NT FAT volume set" },
+	{ MBR_PTYPE_NTFSVOL, "NTFS volume set or HPFS mirrored" },
+	{ MBR_PTYPE_LNX_KERNEL,	"Linux Kernel AiR-BOOT partition" },
+	{ MBR_PTYPE_FT_FAT32, "Legacy Fault tolerant FAT32" },
+	{ MBR_PTYPE_FT_FAT32_EXT, "Legacy Fault tolerant FAT32 ext" },
+	{ MBR_PTYPE_HID_FR_FD_12, "Hidden free FDISK FAT12" },
+	{ MBR_PTYPE_LNX_LVM, "Linux Logical Volume Manager" },
+	{ MBR_PTYPE_HID_FR_FD_16, "Hidden free FDISK FAT16" },
+	{ MBR_PTYPE_HID_FR_FD_EXT, "Hidden free FDISK DOS EXT" },
+	{ MBR_PTYPE_HID_FR_FD_16L, "Hidden free FDISK FAT16 Large" },
+	{ MBR_PTYPE_AMOEBA_FS, "Amoeba filesystem" },
+	{ MBR_PTYPE_AMOEBA_BAD, "Amoeba bad block table" },
+	{ MBR_PTYPE_MIT_EXOPC, "MIT EXOPC native partitions" },
+	{ MBR_PTYPE_HID_FR_FD_32, "Hidden free FDISK FAT32" },
+	{ MBR_PTYPE_DATALIGHT, "Datalight ROM-DOS Super-Boot" },
+	{ MBR_PTYPE_MYLEX, "Mylex EISA SCSI" },
+	{ MBR_PTYPE_HID_FR_FD_16L, "Hidden free FDISK FAT16 LBA" },
+	{ MBR_PTYPE_HID_FR_FD_EXL, "Hidden free FDISK EXT LBA" },
+	{ MBR_PTYPE_BSDI, "BSDI?" },
+	{ MBR_PTYPE_IBM_HIB, "IBM Thinkpad hibernation" },
+	{ MBR_PTYPE_HP_VOL_xA1, "HP Volume expansion (SpeedStor)" },
+	{ MBR_PTYPE_HP_VOL_xA3, "HP Volume expansion (SpeedStor)" },
+	{ MBR_PTYPE_HP_VOL_xA4, "HP Volume expansion (SpeedStor)" },
+	{ MBR_PTYPE_386BSD, "FreeBSD or 386BSD or old NetBSD" },
+	{ MBR_PTYPE_OPENBSD, "OpenBSD" },
+	{ MBR_PTYPE_NEXTSTEP_486, "NeXTSTEP 486" },
+	{ MBR_PTYPE_APPLE_UFS, "Apple UFS" },
+	{ MBR_PTYPE_NETBSD, "NetBSD" },
+	{ MBR_PTYPE_OLIVETTI, "Olivetty Fat12 1.44MB Service part" },
+	{ MBR_PTYPE_SHAG_OS, "SHAG OS filesystem" },
+	{ MBR_PTYPE_BOOTSTAR_DUM, "BootStar Dummy" },
+	{ MBR_PTYPE_BOOT_WIZARD, "Boot Wizard Hidden" },
+	{ MBR_PTYPE_APPLE_BOOT, "Apple Boot" },
+	{ MBR_PTYPE_APPLE_HFS, "Apple HFS" },
+	{ MBR_PTYPE_RESERVED_xB6, "reserved" },
+	{ MBR_PTYPE_RESERVED_xB6, "reserved" },
+	{ MBR_PTYPE_RESERVED_xB6, "reserved" },
+	{ MBR_PTYPE_RESERVED_xB6, "reserved" },
+	{ MBR_PTYPE_BSDI_386, "BSDI BSD/386 filesystem" },
+	{ MBR_PTYPE_BSDI_SWAP, "BSDI BSD/386 swap" },
+	{ MBR_PTYPE_SOLARIS_8, "Solaris 8 boot partition" },
+	{ MBR_PTYPE_SOLARIS, "Solaris boot partition" },
+	{ MBR_PTYPE_CTOS, "CTOS" },
+	{ MBR_PTYPE_DRDOS_FAT12, "DRDOS/sec (FAT-12)" },
+	{ MBR_PTYPE_HID_LNX, "Hidden Linux" },
+	{ MBR_PTYPE_HID_LNX_SWAP, "Hidden Linux Swap" },
+	{ MBR_PTYPE_DRDOS_FAT16S, "DRDOS/sec (FAT-16, < 32M)" },
+	{ MBR_PTYPE_DRDOS_EXT, "DRDOS/sec (EXT)" },
+	{ MBR_PTYPE_DRDOS_FAT16B, "DRDOS/sec (FAT-16, >= 32M)" },
+	{ MBR_PTYPE_SYRINX, "Syrinx (Cyrnix?) or HPFS disabled" },
+	{ MBR_PTYPE_DRDOS_8_xC8, "Reserved for DR-DOS 8.0+" },
+	{ MBR_PTYPE_DRDOS_8_xC9, "Reserved for DR-DOS 8.0+" },
+	{ MBR_PTYPE_DRDOS_8_xCA, "Reserved for DR-DOS 8.0+" },
+	{ MBR_PTYPE_DRDOS_74_CHS, "DR-DOS 7.04+ Secured FAT32 CHS" },
+	{ MBR_PTYPE_DRDOS_74_LBA, "DR-DOS 7.04+ Secured FAT32 LBA" },
+	{ MBR_PTYPE_CTOS_MEMDUMP, "CTOS Memdump" },
+	{ MBR_PTYPE_DRDOS_74_16X, "DR-DOS 7.04+ FAT16X LBA" },
+	{ MBR_PTYPE_DRDOS_74_EXT, "DR-DOS 7.04+ EXT LBA" },
+	{ MBR_PTYPE_REAL32, "REAL/32 secure big partition" },
+	{ MBR_PTYPE_MDOS_FAT12, "Old Multiuser DOS FAT12" },
+	{ MBR_PTYPE_MDOS_FAT16S, "Old Multiuser DOS FAT16 Small" },
+	{ MBR_PTYPE_MDOS_EXT, "Old Multiuser DOS Extended" },
+	{ MBR_PTYPE_MDOS_FAT16B, "Old Multiuser DOS FAT16 Big" },
+	{ MBR_PTYPE_CPM_86, "CP/M 86" },
+	{ MBR_PTYPE_CONCURRENT, "CP/M or Concurrent CP/M or Concurrent DOS "
+				"or CTOS" },
+	{ MBR_PTYPE_HID_CTOS_MEM, "Hidden CTOS Memdump" },
+	{ MBR_PTYPE_DELL_UTIL, "Dell PowerEdge Server utilities" },
+	{ MBR_PTYPE_DGUX_VIRTUAL, "DG/UX virtual disk manager" },
+	{ MBR_PTYPE_STMICROELEC, "STMicroelectronics ST AVFS" },
+	{ MBR_PTYPE_DOS_ACCESS, "DOS access or SpeedStor 12-bit FAT "
+				"extended partition" },
+	{ MBR_PTYPE_STORDIM, "DOS R/O or SpeedStor or Storage Dimensions" },
+	{ MBR_PTYPE_SPEEDSTOR_16S, "SpeedStor 16-bit FAT extended partition "
+				   "< 1024 cyl." },
+	{ MBR_PTYPE_RESERVED_xE5, "reserved" },
+	{ MBR_PTYPE_RESERVED_xE6, "reserved" },
+	{ MBR_PTYPE_BEOS, "BeOS" },
+	{ MBR_PTYPE_PMBR, "GPT Protective MBR" },
+	{ MBR_PTYPE_EFI, "EFI system partition" },
+	{ MBR_PTYPE_LNX_PA_RISC, "Linux PA-RISC boot loader" },
+	{ MBR_PTYPE_SPEEDSTOR_X, "SpeedStor or Storage Dimensions" },
+	{ MBR_PTYPE_DOS33_SEC, "DOS 3.3+ Secondary" },
+	{ MBR_PTYPE_RESERVED_xF3, "reserved" },
+	{ MBR_PTYPE_SPEEDSTOR_L, "SpeedStor large partition or "
+				 "Storage Dimensions" },
+	{ MBR_PTYPE_PROLOGUE, "Prologue multi-volumen partition" },
+	{ MBR_PTYPE_RESERVED_xF6, "reserved" },
+	{ MBR_PTYPE_PCACHE, "pCache: ext2/ext3 persistent cache" },
+	{ MBR_PTYPE_BOCHS, "Bochs x86 emulator" },
+	{ MBR_PTYPE_VMWARE, "VMware File System" },
+	{ MBR_PTYPE_VMWARE_SWAP, "VMware Swap" },
+	{ MBR_PTYPE_LNX_RAID, "Linux RAID partition persistent sb" },
+	{ MBR_PTYPE_LANSTEP, "SpeedStor >1024 cyl. or LANstep "
+			     "or IBM PS/2 IML" },
+	{ MBR_PTYPE_XENIX_BAD, "Xenix Bad Block Table" },
+};
+#endif
+
+#define	MBR_PSECT(s)		((s) & 0x3f)
+#define	MBR_PCYL(c, s)		((c) + (((s) & 0xc0) << 2))
+
+#define	MBR_IS_EXTENDED(x)	((x) == MBR_PTYPE_EXT || \
+				 (x) == MBR_PTYPE_EXT_LBA || \
+				 (x) == MBR_PTYPE_EXT_LNX)
+
+		/* values for mbr_bootsel.mbrbs_flags */
+#define	MBR_BS_ACTIVE	0x01	/* Bootselector active (or code present) */
+#define	MBR_BS_EXTINT13	0x02	/* Set by fdisk if LBA needed (deprecated) */
+#define	MBR_BS_READ_LBA	0x04	/* Force LBA reads (deprecated) */
+#define	MBR_BS_EXTLBA	0x08	/* Extended ptn capable (LBA reads) */
+#define	MBR_BS_ASCII	0x10	/* Bootselect code needs ascii key code */
+/* This is always set, the bootsel is located using the magic number...  */
+#define	MBR_BS_NEWMBR	0x80	/* New bootsel at offset 440 */
+
+#if !defined(__ASSEMBLER__)					/* { */
+
+/*
+ * (x86) BIOS Parameter Block for FAT12
+ */
+struct mbr_bpbFAT12 {
+	uint16_t	bpbBytesPerSec;	/* bytes per sector */
+	uint8_t		bpbSecPerClust;	/* sectors per cluster */
+	uint16_t	bpbResSectors;	/* number of reserved sectors */
+	uint8_t		bpbFATs;	/* number of FATs */
+	uint16_t	bpbRootDirEnts;	/* number of root directory entries */
+	uint16_t	bpbSectors;	/* total number of sectors */
+	uint8_t		bpbMedia;	/* media descriptor */
+	uint16_t	bpbFATsecs;	/* number of sectors per FAT */
+	uint16_t	bpbSecPerTrack;	/* sectors per track */
+	uint16_t	bpbHeads;	/* number of heads */
+	uint16_t	bpbHiddenSecs;	/* # of hidden sectors */
+} __attribute__((__packed__));
+
+/*
+ * (x86) BIOS Parameter Block for FAT16
+ */
+struct mbr_bpbFAT16 {
+	uint16_t	bpbBytesPerSec;	/* bytes per sector */
+	uint8_t		bpbSecPerClust;	/* sectors per cluster */
+	uint16_t	bpbResSectors;	/* number of reserved sectors */
+	uint8_t		bpbFATs;	/* number of FATs */
+	uint16_t	bpbRootDirEnts;	/* number of root directory entries */
+	uint16_t	bpbSectors;	/* total number of sectors */
+	uint8_t		bpbMedia;	/* media descriptor */
+	uint16_t	bpbFATsecs;	/* number of sectors per FAT */
+	uint16_t	bpbSecPerTrack;	/* sectors per track */
+	uint16_t	bpbHeads;	/* number of heads */
+	uint32_t	bpbHiddenSecs;	/* # of hidden sectors */
+	uint32_t	bpbHugeSectors;	/* # of sectors if bpbSectors == 0 */
+	uint8_t		bsDrvNum;	/* Int 0x13 drive number (e.g. 0x80) */
+	uint8_t		bsReserved1;	/* Reserved; set to 0 */
+	uint8_t		bsBootSig;	/* 0x29 if next 3 fields are present */
+	uint8_t		bsVolID[4];	/* Volume serial number */
+	uint8_t		bsVolLab[11];	/* Volume label */
+	uint8_t		bsFileSysType[8];
+					/* "FAT12   ", "FAT16   ", "FAT     " */
+} __attribute__((__packed__));
+
+/*
+ * (x86) BIOS Parameter Block for FAT32
+ */
+struct mbr_bpbFAT32 {
+	uint16_t	bpbBytesPerSec;	/* bytes per sector */
+	uint8_t		bpbSecPerClust;	/* sectors per cluster */
+	uint16_t	bpbResSectors;	/* number of reserved sectors */
+	uint8_t		bpbFATs;	/* number of FATs */
+	uint16_t	bpbRootDirEnts;	/* number of root directory entries */
+	uint16_t	bpbSectors;	/* total number of sectors */
+	uint8_t		bpbMedia;	/* media descriptor */
+	uint16_t	bpbFATsecs;	/* number of sectors per FAT */
+	uint16_t	bpbSecPerTrack;	/* sectors per track */
+	uint16_t	bpbHeads;	/* number of heads */
+	uint32_t	bpbHiddenSecs;	/* # of hidden sectors */
+	uint32_t	bpbHugeSectors;	/* # of sectors if bpbSectors == 0 */
+	uint32_t	bpbBigFATsecs;	/* like bpbFATsecs for FAT32 */
+	uint16_t	bpbExtFlags;	/* extended flags: */
+#define	MBR_FAT32_FATNUM	0x0F	/*   mask for numbering active FAT */
+#define	MBR_FAT32_FATMIRROR	0x80	/*   FAT is mirrored (as previously) */
+	uint16_t	bpbFSVers;	/* filesystem version */
+#define	MBR_FAT32_FSVERS	0	/*   currently only 0 is understood */
+	uint32_t	bpbRootClust;	/* start cluster for root directory */
+	uint16_t	bpbFSInfo;	/* filesystem info structure sector */
+	uint16_t	bpbBackup;	/* backup boot sector */
+	uint8_t		bsReserved[12];	/* Reserved for future expansion */
+	uint8_t		bsDrvNum;	/* Int 0x13 drive number (e.g. 0x80) */
+	uint8_t		bsReserved1;	/* Reserved; set to 0 */
+	uint8_t		bsBootSig;	/* 0x29 if next 3 fields are present */
+	uint8_t		bsVolID[4];	/* Volume serial number */
+	uint8_t		bsVolLab[11];	/* Volume label */
+	uint8_t		bsFileSysType[8]; /* "FAT32   " */
+} __attribute__((__packed__));
+
+/*
+ * (x86) MBR boot selector
+ */
+struct mbr_bootsel {
+	uint8_t		mbrbs_defkey;
+	uint8_t		mbrbs_flags;
+	uint16_t	mbrbs_timeo;
+	char		mbrbs_nametab[MBR_PART_COUNT][MBR_BS_PARTNAMESIZE + 1];
+} __attribute__((__packed__));
+
+/*
+ * MBR partition
+ */
+struct mbr_partition {
+	uint8_t		mbrp_flag;	/* MBR partition flags */
+	uint8_t		mbrp_shd;	/* Starting head */
+	uint8_t		mbrp_ssect;	/* Starting sector */
+	uint8_t		mbrp_scyl;	/* Starting cylinder */
+	uint8_t		mbrp_type;	/* Partition type (see below) */
+	uint8_t		mbrp_ehd;	/* End head */
+	uint8_t		mbrp_esect;	/* End sector */
+	uint8_t		mbrp_ecyl;	/* End cylinder */
+	uint32_t	mbrp_start;	/* Absolute starting sector number */
+	uint32_t	mbrp_size;	/* Partition size in sectors */
+} __attribute__((__packed__));
+
+int xlat_mbr_fstype(int);	/* in sys/lib/libkern/xlat_mbr_fstype.c */
+
+/*
+ * MBR boot sector.
+ * This is used by both the MBR (Master Boot Record) in sector 0 of the disk
+ * and the PBR (Partition Boot Record) in sector 0 of an MBR partition.
+ */
+struct mbr_sector {
+					/* Jump instruction to boot code.  */
+					/* Usually 0xE9nnnn or 0xEBnn90 */
+	uint8_t			mbr_jmpboot[3];
+					/* OEM name and version */
+	uint8_t			mbr_oemname[8];
+	union {				/* BIOS Parameter Block */
+		struct mbr_bpbFAT12	bpb12;
+		struct mbr_bpbFAT16	bpb16;
+		struct mbr_bpbFAT32	bpb32;
+	} mbr_bpb;
+					/* Boot code */
+	uint8_t			mbr_bootcode[310];
+					/* Config for /usr/mdec/mbr_bootsel */
+	struct mbr_bootsel	mbr_bootsel;
+					/* NT Drive Serial Number */
+	uint32_t		mbr_dsn;
+					/* mbr_bootsel magic */
+	uint16_t		mbr_bootsel_magic;
+					/* MBR partition table */
+	struct mbr_partition	mbr_parts[MBR_PART_COUNT];
+					/* MBR magic (0xaa55) */
+	uint16_t		mbr_magic;
+} __attribute__((__packed__));
+
+#endif	/* !defined(__ASSEMBLER__) */				/* } */
+
+
+/* ------------------------------------------
+ * shared --
+ *	definitions shared by many platforms
+ */
+
+#if !defined(__ASSEMBLER__)					/* { */
+
+	/* Maximum # of blocks in bbi_block_table, each bbi_block_size long */
+#define	SHARED_BBINFO_MAXBLOCKS	118	/* so sizeof(shared_bbinfo) == 512 */
+
+struct shared_bbinfo {
+	uint8_t bbi_magic[32];
+	int32_t bbi_block_size;
+	int32_t bbi_block_count;
+	int32_t bbi_block_table[SHARED_BBINFO_MAXBLOCKS];
+};
+
+/* ------------------------------------------
+ * alpha --
+ *	Alpha (disk, but also tape) Boot Block.
+ *
+ *	See Section (III) 3.6.1 of the Alpha Architecture Reference Manual.
+ */
+
+struct alpha_boot_block {
+	uint64_t bb_data[63];		/* data (disklabel, also as below) */
+	uint64_t bb_cksum;		/* checksum of the boot block,
+					 * taken as uint64_t's
+					 */
+};
+#define	bb_secsize	bb_data[60]	/* secondary size (blocks) */
+#define	bb_secstart	bb_data[61]	/* secondary start (blocks) */
+#define	bb_flags	bb_data[62]	/* unknown flags (set to zero) */
+
+#define	ALPHA_BOOT_BLOCK_OFFSET		0	/* offset of boot block. */
+#define	ALPHA_BOOT_BLOCK_BLOCKSIZE	512	/* block size for sector
+						 * size/start, and for boot
+						 * block itself.
+						 */
+
+#define	ALPHA_BOOT_BLOCK_CKSUM(bb,cksum)				\
+	do {								\
+		const struct alpha_boot_block *_bb = (bb);		\
+		uint64_t _cksum;					\
+		size_t _i;						\
+									\
+		_cksum = 0;						\
+		for (_i = 0;						\
+		    _i < (sizeof _bb->bb_data / sizeof _bb->bb_data[0]); \
+		    _i++)						\
+			_cksum += le64toh(_bb->bb_data[_i]);		\
+		*(cksum) = htole64(_cksum);				\
+	} while (/*CONSTCOND*/ 0)
+
+/* ------------------------------------------
+ * apple --
+ *	Apple computers boot block related information
+ */
+
+/*
+ *	Driver Descriptor Map, from Inside Macintosh: Devices, SCSI Manager
+ *	pp 12-13.  The driver descriptor map always resides on physical block 0.
+ */
+struct apple_drvr_descriptor {
+	uint32_t	descBlock;	/* first block of driver */
+	uint16_t	descSize;	/* driver size in blocks */
+	uint16_t	descType;	/* system type */
+} __attribute__((__packed__));
+
+/*
+ *	system types; Apple reserves 0-15
+ */
+#define	APPLE_DRVR_TYPE_MACINTOSH	1
+
+#define	APPLE_DRVR_MAP_MAGIC		0x4552
+#define	APPLE_DRVR_MAP_MAX_DESCRIPTORS	61
+
+struct apple_drvr_map {
+	uint16_t	sbSig;		/* map signature */
+	uint16_t	sbBlockSize;	/* block size of device */
+	uint32_t	sbBlkCount;	/* number of blocks on device */
+	uint16_t	sbDevType;	/* (used internally by ROM) */
+	uint16_t	sbDevID;	/* (used internally by ROM) */
+	uint32_t	sbData;		/* (used internally by ROM) */
+	uint16_t	sbDrvrCount;	/* number of driver descriptors */
+	struct apple_drvr_descriptor sb_dd[APPLE_DRVR_MAP_MAX_DESCRIPTORS];
+	uint16_t	pad[3];
+} __attribute__((__packed__));
+
+/*
+ *	Partition map structure from Inside Macintosh: Devices, SCSI Manager
+ *	pp. 13-14.  The partition map always begins on physical block 1.
+ *
+ *	With the exception of block 0, all blocks on the disk must belong to
+ *	exactly one partition.  The partition map itself belongs to a partition
+ *	of type `APPLE_PARTITION_MAP', and is not limited in size by anything
+ *	other than available disk space.  The partition map is not necessarily
+ *	the first partition listed.
+ */
+#define	APPLE_PART_MAP_ENTRY_MAGIC	0x504d
+
+struct apple_part_map_entry {
+	uint16_t	pmSig;		/* partition signature */
+	uint16_t	pmSigPad;	/* (reserved) */
+	uint32_t	pmMapBlkCnt;	/* number of blocks in partition map */
+	uint32_t	pmPyPartStart;	/* first physical block of partition */
+	uint32_t	pmPartBlkCnt;	/* number of blocks in partition */
+	uint8_t		pmPartName[32];	/* partition name */
+	uint8_t		pmPartType[32];	/* partition type */
+	uint32_t	pmLgDataStart;	/* first logical block of data area */
+	uint32_t	pmDataCnt;	/* number of blocks in data area */
+	uint32_t	pmPartStatus;	/* partition status information */
+/*
+ * Partition Status Information from Apple Tech Note 1189
+ */
+#define	APPLE_PS_VALID		0x00000001	/* Entry is valid */
+#define	APPLE_PS_ALLOCATED	0x00000002	/* Entry is allocated */
+#define	APPLE_PS_IN_USE		0x00000004	/* Entry in use */
+#define	APPLE_PS_BOOT_INFO	0x00000008	/* Entry contains boot info */
+#define	APPLE_PS_READABLE	0x00000010	/* Entry is readable */
+#define	APPLE_PS_WRITABLE	0x00000020	/* Entry is writable */
+#define	APPLE_PS_BOOT_CODE_PIC	0x00000040	/* Boot code has position
+						 * independent code */
+#define	APPLE_PS_CC_DRVR	0x00000100	/* Partition contains chain-
+						 * compatible driver */
+#define	APPLE_PS_RL_DRVR	0x00000200	/* Partition contains real
+						 * driver */
+#define	APPLE_PS_CH_DRVR	0x00000400	/* Partition contains chain
+						 * driver */
+#define	APPLE_PS_AUTO_MOUNT	0x40000000	/* Mount automatically at
+						 * startup */
+#define	APPLE_PS_STARTUP	0x80000000	/* Is the startup partition */
+	uint32_t	pmLgBootStart;	/* first logical block of boot code */
+	uint32_t	pmBootSize;	/* size of boot code, in bytes */
+	uint32_t	pmBootLoad;	/* boot code load address */
+	uint32_t	pmBootLoad2;	/* (reserved) */
+	uint32_t	pmBootEntry;	/* boot code entry point */
+	uint32_t	pmBootEntry2;	/* (reserved) */
+	uint32_t	pmBootCksum;	/* boot code checksum */
+	int8_t		pmProcessor[16]; /* processor type (e.g. "68020") */
+	uint8_t		pmBootArgs[128]; /* A/UX boot arguments */
+	uint8_t		pad[248];	/* pad to end of block */
+};
+
+#define	APPLE_PART_TYPE_DRIVER		"APPLE_DRIVER"
+#define	APPLE_PART_TYPE_DRIVER43	"APPLE_DRIVER43"
+#define	APPLE_PART_TYPE_DRIVERATA	"APPLE_DRIVER_ATA"
+#define	APPLE_PART_TYPE_DRIVERIOKIT	"APPLE_DRIVER_IOKIT"
+#define	APPLE_PART_TYPE_FWDRIVER	"APPLE_FWDRIVER"
+#define	APPLE_PART_TYPE_FWB_COMPONENT	"FWB DRIVER COMPONENTS"
+#define	APPLE_PART_TYPE_FREE		"APPLE_FREE"
+#define	APPLE_PART_TYPE_MAC		"APPLE_HFS"
+#define	APPLE_PART_TYPE_NETBSD		"NETBSD"
+#define	APPLE_PART_TYPE_NBSD_PPCBOOT	"NETBSD/MACPPC"
+#define	APPLE_PART_TYPE_NBSD_68KBOOT	"NETBSD/MAC68K"
+#define	APPLE_PART_TYPE_PATCHES		"APPLE_PATCHES"
+#define	APPLE_PART_TYPE_PARTMAP		"APPLE_PARTITION_MAP"
+#define	APPLE_PART_TYPE_PATCHES		"APPLE_PATCHES"
+#define	APPLE_PART_TYPE_SCRATCH		"APPLE_SCRATCH"
+#define	APPLE_PART_TYPE_UNIX		"APPLE_UNIX_SVR2"
+
+/*
+ * "pmBootArgs" for APPLE_UNIX_SVR2 partition.
+ * NetBSD/mac68k only uses Magic, Cluster, Type, and Flags.
+ */
+struct apple_blockzeroblock {
+	uint32_t       bzbMagic;
+	uint8_t        bzbCluster;
+	uint8_t        bzbType;
+	uint16_t       bzbBadBlockInode;
+	uint16_t       bzbFlags;
+	uint16_t       bzbReserved;
+	uint32_t       bzbCreationTime;
+	uint32_t       bzbMountTime;
+	uint32_t       bzbUMountTime;
+};
+
+#define	APPLE_BZB_MAGIC		0xABADBABE
+#define	APPLE_BZB_TYPEFS	1
+#define	APPLE_BZB_TYPESWAP	3
+#define	APPLE_BZB_ROOTFS	0x8000
+#define	APPLE_BZB_USRFS		0x4000
+
+/* ------------------------------------------
+ * ews4800mips
+ *
+ */
+
+#define	EWS4800MIPS_BBINFO_MAGIC		"NetBSD/ews4800mips     20040611"
+#define	EWS4800MIPS_BOOT_BLOCK_OFFSET		0
+#define	EWS4800MIPS_BOOT_BLOCK_BLOCKSIZE	512
+#define	EWS4800MIPS_BOOT_BLOCK_MAX_SIZE		(512 * 8)
+
+/* ------------------------------------------
+ * hp300
+ *
+ */
+
+/* volume header for "LIF" format volumes */
+
+struct	hp300_lifvol {
+	int16_t	vol_id;
+	char	vol_label[6];
+	int32_t	vol_addr;
+	int16_t	vol_oct;
+	int16_t	vol_dummy;
+	int32_t	vol_dirsize;
+	int16_t	vol_version;
+	int16_t	vol_zero;
+	int32_t	vol_huh1;
+	int32_t	vol_huh2;
+	int32_t	vol_length;
+};
+
+/* LIF directory entry format */
+
+struct	hp300_lifdir {
+	char	dir_name[10];
+	int16_t	dir_type;
+	int32_t	dir_addr;
+	int32_t	dir_length;
+	char	dir_toc[6];
+	int16_t	dir_flag;
+	int32_t	dir_exec;
+};
+
+/* load header for boot rom */
+struct hp300_load {
+	int32_t address;
+	int32_t count;
+};
+
+#define	HP300_VOL_ID		-32768
+#define	HP300_VOL_OCT		4096
+#define	HP300_DIR_TYPE		-5822
+#define	HP300_DIR_FLAG		0x8001	/* dont ask me! */
+#define	HP300_SECTSIZE		256
+
+
+/* ------------------------------------------
+ * hppa
+ *
+ */
+
+/*
+ * volume header for "LIF" format volumes
+ */
+struct	hppa_lifvol {
+	uint16_t	vol_id;
+	uint8_t		vol_label[6];
+	uint32_t	vol_addr;
+	uint16_t	vol_oct;
+	uint16_t	vol_dummy;
+
+	uint32_t	vol_dirsize;
+	uint16_t	vol_version;
+	uint16_t	vol_zero;
+	uint32_t	vol_number;
+	uint32_t	vol_lastvol;
+
+	uint32_t	vol_length;
+	uint8_t		vol_toc[6];
+	uint8_t		vol_dummy1[198];
+
+	uint32_t	ipl_addr;
+	uint32_t	ipl_size;
+	uint32_t	ipl_entry;
+
+	uint32_t	vol_dummy2;
+};
+
+struct	hppa_lifdir {
+	uint8_t		dir_name[10];
+	uint16_t	dir_type;
+	uint32_t	dir_addr;
+	uint32_t	dir_length;
+	uint8_t		dir_toc[6];
+	uint16_t	dir_flag;
+	uint32_t	dir_implement;
+};
+
+struct hppa_lifload {
+	int address;
+	int count;
+};
+
+#define	HPPA_LIF_VOL_ID	0x8000
+#define	HPPA_LIF_VOL_OCT	0x1000
+#define	HPPA_LIF_DIR_SWAP	0x5243
+#define	HPPA_LIF_DIR_FS	0xcd38
+#define	HPPA_LIF_DIR_IOMAP	0xcd60
+#define	HPPA_LIF_DIR_HPUX	0xcd80
+#define	HPPA_LIF_DIR_ISL	0xce00
+#define	HPPA_LIF_DIR_PAD	0xcffe
+#define	HPPA_LIF_DIR_AUTO	0xcfff
+#define	HPPA_LIF_DIR_EST	0xd001
+#define	HPPA_LIF_DIR_TYPE	0xe942
+
+#define	HPPA_LIF_DIR_FLAG	0x8001	/* dont ask me! */
+#define	HPPA_LIF_SECTSIZE	256
+
+#define	HPPA_LIF_NUMDIR	8
+
+#define	HPPA_LIF_VOLSTART	0
+#define	HPPA_LIF_VOLSIZE	sizeof(struct hppa_lifvol)
+#define	HPPA_LIF_DIRSTART	2048
+#define	HPPA_LIF_DIRSIZE	(HPPA_LIF_NUMDIR * sizeof(struct hppa_lifdir))
+#define	HPPA_LIF_FILESTART	4096
+
+#define	hppa_btolifs(b)	(((b) + (HPPA_LIF_SECTSIZE - 1)) / HPPA_LIF_SECTSIZE)
+#define	hppa_lifstob(s)	((s) * HPPA_LIF_SECTSIZE)
+#define	hppa_lifstodb(s)	((s) * HPPA_LIF_SECTSIZE / DEV_BSIZE)
+
+
+/* ------------------------------------------
+ * x86
+ *
+ */
+
+/*
+ * Parameters for NetBSD /boot written to start of pbr code by installboot
+ */
+
+struct x86_boot_params {
+	uint32_t	bp_length;	/* length of patchable data */
+	uint32_t	bp_flags;
+	uint32_t	bp_timeout;	/* boot timeout in seconds */
+	uint32_t	bp_consdev;
+	uint32_t	bp_conspeed;
+	uint8_t		bp_password[16];	/* md5 hash of password */
+	char		bp_keymap[64];	/* keyboard translation map */
+	uint32_t	bp_consaddr;	/* ioaddr for console */
+};
+
+#endif	/* !defined(__ASSEMBLER__) */				/* } */
+
+#define	X86_BOOT_MAGIC(n)	('x' << 24 | 0x86b << 12 | 'm' << 4 | (n))
+#define	X86_BOOT_MAGIC_1	X86_BOOT_MAGIC(1)	/* pbr.S */
+#define	X86_BOOT_MAGIC_2	X86_BOOT_MAGIC(2)	/* bootxx.S */
+#define	X86_BOOT_MAGIC_PXE	X86_BOOT_MAGIC(3)	/* start_pxe.S */
+#define	X86_BOOT_MAGIC_FAT	X86_BOOT_MAGIC(4)	/* fatboot.S */
+#define	X86_BOOT_MAGIC_EFI	X86_BOOT_MAGIC(5)	/* efiboot/start.S */
+#define	X86_MBR_GPT_MAGIC	0xedb88320		/* gpt.S */
+
+		/* values for bp_flags */
+#define	X86_BP_FLAGS_RESET_VIDEO	1
+#define	X86_BP_FLAGS_PASSWORD		2
+#define	X86_BP_FLAGS_NOMODULES		4
+#define	X86_BP_FLAGS_NOBOOTCONF		8
+#define	X86_BP_FLAGS_LBA64VALID		0x10
+
+		/* values for bp_consdev */
+#define	X86_BP_CONSDEV_PC	0
+#define	X86_BP_CONSDEV_COM0	1
+#define	X86_BP_CONSDEV_COM1	2
+#define	X86_BP_CONSDEV_COM2	3
+#define	X86_BP_CONSDEV_COM3	4
+#define	X86_BP_CONSDEV_COM0KBD	5
+#define	X86_BP_CONSDEV_COM1KBD	6
+#define	X86_BP_CONSDEV_COM2KBD	7
+#define	X86_BP_CONSDEV_COM3KBD	8
+
+/* ------------------------------------------
+ * landisk
+ */
+
+#if !defined(__ASSEMBLER__)					/* { */
+
+/*
+ * Parameters for NetBSD /boot written to start of pbr code by installboot
+ */
+struct landisk_boot_params {
+	uint32_t	bp_length;	/* length of patchable data */
+	uint32_t	bp_flags;
+	uint32_t	bp_timeout;	/* boot timeout in seconds */
+	uint32_t	bp_consdev;
+	uint32_t	bp_conspeed;
+};
+
+#endif	/* !defined(__ASSEMBLER__) */				/* } */
+
+#define	LANDISK_BOOT_MAGIC_1	0x20031125
+#define	LANDISK_BOOT_MAGIC_2	0x20041110
+
+#if !defined(__ASSEMBLER__)					/* { */
+
+/* ------------------------------------------
+ * macppc
+ */
+
+#define	MACPPC_BOOT_BLOCK_OFFSET	2048
+#define	MACPPC_BOOT_BLOCK_BLOCKSIZE	512
+#define	MACPPC_BOOT_BLOCK_MAX_SIZE	2048	/* XXX: could be up to 6144 */
+	/* Magic string -- 32 bytes long (including the NUL) */
+#define	MACPPC_BBINFO_MAGIC		"NetBSD/macppc bootxx   20020515"
+
+/* ------------------------------------------
+ * news68k, newsmips
+ */
+
+#define	NEWS_BOOT_BLOCK_LABELOFFSET	64 /* XXX from <machine/disklabel.h> */
+#define	NEWS_BOOT_BLOCK_OFFSET		0
+#define	NEWS_BOOT_BLOCK_BLOCKSIZE	512
+#define	NEWS_BOOT_BLOCK_MAX_SIZE	(512 * 16)
+
+	/* Magic string -- 32 bytes long (including the NUL) */
+#define	NEWS68K_BBINFO_MAGIC		"NetBSD/news68k bootxx  20020518"
+#define	NEWSMIPS_BBINFO_MAGIC		"NetBSD/newsmips bootxx 20020518"
+
+/* ------------------------------------------
+ * next68k
+ */
+
+#define	NEXT68K_LABEL_MAXPARTITIONS	8	/* number of partitions in next68k_disklabel */
+#define	NEXT68K_LABEL_CPULBLLEN		24
+#define	NEXT68K_LABEL_MAXDNMLEN		24
+#define	NEXT68K_LABEL_MAXTYPLEN		24
+#define	NEXT68K_LABEL_MAXBFLEN		24
+#define	NEXT68K_LABEL_MAXHNLEN		32
+#define	NEXT68K_LABEL_MAXMPTLEN		16
+#define	NEXT68K_LABEL_MAXFSTLEN		8
+#define	NEXT68K_LABEL_NBAD		1670	/* sized to make label ~= 8KB */
+
+struct next68k_partition {
+	int32_t	cp_offset;		/* starting sector */
+	int32_t	cp_size;		/* number of sectors in partition */
+	int16_t	cp_bsize;		/* block size in bytes */
+	int16_t	cp_fsize;		/* filesystem basic fragment size */
+	char	cp_opt;			/* optimization type: 's'pace/'t'ime */
+	char	cp_pad1;
+	int16_t	cp_cpg;			/* filesystem cylinders per group */
+	int16_t	cp_density;		/* bytes per inode density */
+	int8_t	cp_minfree;		/* minfree (%) */
+	int8_t	cp_newfs;		/* run newfs during init */
+	char	cp_mountpt[NEXT68K_LABEL_MAXMPTLEN];
+					/* default/standard mount point */
+	int8_t	cp_automnt;		/* auto-mount when inserted */
+	char	cp_type[NEXT68K_LABEL_MAXFSTLEN]; /* file system type name */
+	char	cp_pad2;
+} __attribute__((__packed__));
+
+/* The disklabel the way it is on the disk */
+struct next68k_disklabel {
+	int32_t	cd_version;		/* label version */
+	int32_t	cd_label_blkno;		/* block # of this label */
+	int32_t	cd_size;		/* size of media area (sectors) */
+	char	cd_label[NEXT68K_LABEL_CPULBLLEN]; /* disk name (label) */
+	uint32_t cd_flags;		/* flags */
+	uint32_t cd_tag;		/* volume tag */
+	char	cd_name[NEXT68K_LABEL_MAXDNMLEN]; /* drive (hardware) name */
+	char	cd_type[NEXT68K_LABEL_MAXTYPLEN]; /* drive type */
+	int32_t	cd_secsize;		/* # of bytes per sector */
+	int32_t	cd_ntracks;		/* # of tracks per cylinder */
+	int32_t	cd_nsectors;		/* # of data sectors per track */
+	int32_t	cd_ncylinders;		/* # of data cylinders per unit */
+	int32_t	cd_rpm;			/* rotational speed */
+	int16_t	cd_front;		/* # of sectors in "front porch" */
+	int16_t	cd_back;		/* # of sectors in "back porch" */
+	int16_t	cd_ngroups;		/* # of alt groups */
+	int16_t	cd_ag_size;		/* alt group size (sectors) */
+	int16_t	cd_ag_alts;		/* alternate sectors / alt group */
+	int16_t	cd_ag_off;		/* sector offset to first alternate */
+	int32_t	cd_boot_blkno[2];	/* boot program locations */
+	char	cd_kernel[NEXT68K_LABEL_MAXBFLEN]; /* default kernel name */
+	char	cd_hostname[NEXT68K_LABEL_MAXHNLEN];
+				/* host name (usu. where disk was labeled) */
+	char	cd_rootpartition;	/* root partition letter e.g. 'a' */
+	char	cd_rwpartition;		/* r/w partition letter e.g. 'b' */
+	struct next68k_partition cd_partitions[NEXT68K_LABEL_MAXPARTITIONS];
+
+	union {
+		uint16_t CD_v3_checksum; /* label version 3 checksum */
+		int32_t	CD_bad[NEXT68K_LABEL_NBAD];
+					/* block number that is bad */
+	} cd_un;
+	uint16_t cd_checksum;		/* label version 1 or 2 checksum */
+} __attribute__((__packed__));
+
+#define	NEXT68K_LABEL_cd_checksum	cd_checksum
+#define	NEXT68K_LABEL_cd_v3_checksum	cd_un.CD_v3_checksum
+#define	NEXT68K_LABEL_cd_bad		cd_un.CD_bad
+
+#define	NEXT68K_LABEL_SECTOR		0	/* sector containing label */
+#define	NEXT68K_LABEL_OFFSET		0	/* offset of label in sector */
+#define	NEXT68K_LABEL_SIZE		8192	/* size of label */
+#define	NEXT68K_LABEL_CD_V1		0x4e655854 /* version #1: "NeXT" */
+#define	NEXT68K_LABEL_CD_V2		0x646c5632 /* version #2: "dlV2" */
+#define	NEXT68K_LABEL_CD_V3		0x646c5633 /* version #3: "dlV3" */
+#define	NEXT68K_LABEL_DEFAULTFRONTPORCH	(160 * 2)
+#define	NEXT68K_LABEL_DEFAULTBOOT0_1	(32 * 2)
+#define	NEXT68K_LABEL_DEFAULTBOOT0_2	(96 * 2)
+
+/* ------------------------------------------
+ * pmax --
+ *	PMAX (DECstation / MIPS) boot block information
+ */
+
+/*
+ * If mode is 0, there is just one sequence of blocks and one Dec_BootMap
+ * is used.  If mode is 1, there are multiple sequences of blocks
+ * and multiple Dec_BootMaps are used, the last with numBlocks = 0.
+ */
+struct pmax_boot_map {
+	int32_t	num_blocks;		/* Number of blocks to read. */
+	int32_t	start_block;		/* Starting block on disk. */
+};
+
+/*
+ * This is the structure of a disk or tape boot block.  The boot_map
+ * can either be a single boot count and start block (contiguous mode)
+ * or a list of up to 61 (to fill a 512 byte sector) block count and
+ * start block pairs.  Under NetBSD, contiguous mode is always used.
+ */
+struct pmax_boot_block {
+	uint8_t		pad[8];
+	int32_t		magic;			/* PMAX_BOOT_MAGIC */
+	int32_t		mode;			/* Mode for boot info. */
+	uint32_t	load_addr;		/* Address to start loading. */
+	uint32_t	exec_addr;		/* Address to start execing. */
+	struct		pmax_boot_map map[61];	/* boot program section(s). */
+} __attribute__((__packed__));
+
+#define	PMAX_BOOT_MAGIC			0x0002757a
+#define	PMAX_BOOTMODE_CONTIGUOUS	0
+#define	PMAX_BOOTMODE_SCATTERED		1
+
+#define	PMAX_BOOT_BLOCK_OFFSET		0
+#define	PMAX_BOOT_BLOCK_BLOCKSIZE	512
+
+
+/* ------------------------------------------
+ * sgimips
+ */
+
+/*
+ * Some IRIX man pages refer to the size being a multiple of whole cylinders.
+ * Later ones only refer to the size being "typically" 2MB.  IRIX fx(1)
+ * uses a default drive geometry if one can't be determined, suggesting
+ * that "whole cylinder" multiples are not required.
+ */
+
+#define SGI_BOOT_BLOCK_SIZE_VOLHDR	3135
+#define SGI_BOOT_BLOCK_MAGIC		0xbe5a941
+#define SGI_BOOT_BLOCK_MAXPARTITIONS	16
+#define SGI_BOOT_BLOCK_MAXVOLDIRS	15
+#define SGI_BOOT_BLOCK_BLOCKSIZE	512
+
+/*
+ * SGI partition conventions:
+ *
+ * Partition 0 - root
+ * Partition 1 - swap
+ * Partition 6 - usr
+ * Partition 7 - volume body
+ * Partition 8 - volume header
+ * Partition 10 - whole disk
+ */
+
+struct sgi_boot_devparms {
+	uint8_t		dp_skew;
+	uint8_t		dp_gap1;
+	uint8_t		dp_gap2;
+	uint8_t		dp_spares_cyl;
+	uint16_t	dp_cyls;
+	uint16_t	dp_shd0;
+	uint16_t	dp_trks0;
+	uint8_t		dp_ctq_depth;
+	uint8_t		dp_cylshi;
+	uint16_t	dp_unused;
+	uint16_t	dp_secs;
+	uint16_t	dp_secbytes;
+	uint16_t	dp_interleave;
+	uint32_t	dp_flags;
+	uint32_t	dp_datarate;
+	uint32_t	dp_nretries;
+	uint32_t	dp_mspw;
+	uint16_t	dp_xgap1;
+	uint16_t	dp_xsync;
+	uint16_t	dp_xrdly;
+	uint16_t	dp_xgap2;
+	uint16_t	dp_xrgate;
+	uint16_t	dp_xwcont;
+} __attribute__((__packed__));
+
+struct sgi_boot_block {
+	uint32_t	magic;
+	int16_t		root;
+	int16_t		swap;
+	char		bootfile[16];
+	struct sgi_boot_devparms dp;
+	struct {
+		char		name[8];
+		int32_t		block;
+		int32_t		bytes;
+	}		voldir[SGI_BOOT_BLOCK_MAXVOLDIRS];
+	struct {
+		int32_t		blocks;
+		int32_t		first;
+		int32_t		type;
+	}		partitions[SGI_BOOT_BLOCK_MAXPARTITIONS];
+	int32_t		checksum;
+	int32_t		_pad;
+} __attribute__((__packed__));
+
+#define SGI_PTYPE_VOLHDR	0
+#define SGI_PTYPE_TRKREPL	1
+#define SGI_PTYPE_SECREPL	2
+#define SGI_PTYPE_RAW		3
+#define SGI_PTYPE_BSD		4
+#define SGI_PTYPE_SYSV		5
+#define SGI_PTYPE_VOLUME	6
+#define SGI_PTYPE_EFS		7
+#define SGI_PTYPE_LVOL		8
+#define SGI_PTYPE_RLVOL		9
+#define SGI_PTYPE_XFS		10
+#define SGI_PTYPE_XFSLOG	11
+#define SGI_PTYPE_XLV		12
+#define SGI_PTYPE_XVM		13
+
+/* ------------------------------------------
+ * sparc
+ */
+
+#define	SPARC_BOOT_BLOCK_OFFSET		512
+#define	SPARC_BOOT_BLOCK_BLOCKSIZE	512
+#define	SPARC_BOOT_BLOCK_MAX_SIZE	(512 * 15)
+	/* Magic string -- 32 bytes long (including the NUL) */
+#define	SPARC_BBINFO_MAGIC		"NetBSD/sparc bootxx    20020515"
+
+
+/* ------------------------------------------
+ * sparc64
+ */
+
+#define	SPARC64_BOOT_BLOCK_OFFSET	512
+#define	SPARC64_BOOT_BLOCK_BLOCKSIZE	512
+#define	SPARC64_BOOT_BLOCK_MAX_SIZE	(512 * 15)
+
+
+/* ------------------------------------------
+ * sun68k (sun2, sun3)
+ */
+
+#define	SUN68K_BOOT_BLOCK_OFFSET	512
+#define	SUN68K_BOOT_BLOCK_BLOCKSIZE	512
+#define	SUN68K_BOOT_BLOCK_MAX_SIZE	(512 * 15)
+	/* Magic string -- 32 bytes long (including the NUL) */
+#define	SUN68K_BBINFO_MAGIC		"NetBSD/sun68k bootxx   20020515"
+
+
+/* ------------------------------------------
+ * vax --
+ *	VAX boot block information
+ */
+
+struct vax_boot_block {
+/* Note that these don't overlap any of the pmax boot block */
+	uint8_t		pad0[2];
+	uint8_t		bb_id_offset;	/* offset in words to id (magic1)*/
+	uint8_t		bb_mbone;	/* must be one */
+	uint16_t	bb_lbn_hi;	/* lbn (hi word) of bootstrap */
+	uint16_t	bb_lbn_low;	/* lbn (low word) of bootstrap */
+	uint8_t		pad1[406];
+	/* disklabel offset is 64 from base, or 56 from start of pad1 */
+
+	/* The rest of these fields are identification area and describe
+	 * the secondary block for uVAX VMB.
+	 */
+	uint8_t		bb_magic1;	/* magic number */
+	uint8_t		bb_mbz1;	/* must be zero */
+	uint8_t		bb_pad1;	/* any value */
+	uint8_t		bb_sum1;	/* ~(magic1 + mbz1 + pad1) */
+
+	uint8_t		bb_mbz2;	/* must be zero */
+	uint8_t		bb_volinfo;	/* volinfo */
+	uint8_t		bb_pad2a;	/* any value */
+	uint8_t		bb_pad2b;	/* any value */
+
+	uint32_t	bb_size;	/* size in blocks of bootstrap */
+	uint32_t	bb_load;	/* load offset to bootstrap */
+	uint32_t	bb_entry;	/* byte offset in bootstrap */
+	uint32_t	bb_sum3;	/* sum of previous 3 fields */
+
+	/* The rest is unused.
+	 */
+	uint8_t		pad2[74];
+} __attribute__((__packed__));
+
+#define	VAX_BOOT_MAGIC1			0x18	/* size of BB info? */
+#define	VAX_BOOT_VOLINFO_NONE		0x00	/* no special info */
+#define	VAX_BOOT_VOLINFO_SS		0x01	/* single sided */
+#define	VAX_BOOT_VOLINFO_DS		0x81	/* double sided */
+
+#define	VAX_BOOT_SIZE			15	/* 15 blocks */
+#define	VAX_BOOT_LOAD			0	/* no load offset */
+#define	VAX_BOOT_ENTRY			0x200	/* one block in */
+
+#define	VAX_BOOT_BLOCK_OFFSET		0
+#define	VAX_BOOT_BLOCK_BLOCKSIZE	512
+
+
+/* ------------------------------------------
+ * x68k
+ */
+
+#define	X68K_BOOT_BLOCK_OFFSET		0
+#define	X68K_BOOT_BLOCK_BLOCKSIZE	512
+#define	X68K_BOOT_BLOCK_MAX_SIZE	(512 * 16)
+	/* Magic string -- 32 bytes long (including the NUL) */
+#define	X68K_BBINFO_MAGIC		"NetBSD/x68k bootxx     20020601"
+
+#endif	/* !defined(__ASSEMBLER__) */				/* } */
+
+#endif	/* !_SYS_BOOTBLOCK_H */
diff -Nru gxemul-0.6.2/src/include/thirdparty/debug_new.h gxemul-0.7.0+dfsg/src/include/thirdparty/debug_new.h
--- gxemul-0.6.2/src/include/thirdparty/debug_new.h	2019-06-22 18:23:25.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/thirdparty/debug_new.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,155 +0,0 @@
-/*
- * Modified for GXemul:
- *
- *	1. Better Doxygen comment for class __debug_new_counter.
- */
-
-
-// -*- Mode: C++; tab-width: 4; c-basic-offset: 4; indent-tabs-mode: nil -*-
-// vim:tabstop=4:shiftwidth=4:expandtab:
-
-/*
- * Copyright (C) 2004-2005 Wu Yongwei <adah at users dot sourceforge dot net>
- *
- * This software is provided 'as-is', without any express or implied
- * warranty.  In no event will the authors be held liable for any
- * damages arising from the use of this software.
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute
- * it freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must
- *    not claim that you wrote the original software. If you use this
- *    software in a product, an acknowledgment in the product
- *    documentation would be appreciated but is not required.
- * 2. Altered source versions must be plainly marked as such, and must
- *    not be misrepresented as being the original software.
- * 3. This notice may not be removed or altered from any source
- *    distribution.
- *
- * This file is part of Stones of Nvwa:
- *      http://sourceforge.net/projects/nvwa
- *
- */
-
-/**
- * @file    debug_new.h
- *
- * Header file for checking leaks caused by unmatched new/delete.
- *
- * @version 3.4, 2005/09/13
- * @author  Wu Yongwei
- *
- */
-
-#ifndef _DEBUG_NEW_H
-#define _DEBUG_NEW_H
-
-#include <new>
-#include <stdio.h>
-
-/**
- * @def HAS_PLACEMENT_DELETE
- *
- * Macro to indicate whether placement delete operators are supported on
- * a certain compiler.  Some compilers, like Borland C++ Compiler 5.5.1
- * and Digital Mars Compiler 8.42, do not support them, and the user
- * must define this macro to \c 0 to make the program compile.  Also
- * note that in that case memory leakage will occur if an exception is
- * thrown in the initialization (constructor) of a dynamically created
- * object.
- */
-#ifndef HAS_PLACEMENT_DELETE
-#define HAS_PLACEMENT_DELETE 1
-#endif
-
-/**
- * @def _DEBUG_NEW_REDEFINE_NEW
- *
- * Macro to indicate whether redefinition of \c new is wanted.  If one
- * wants to define one's own <code>operator new</code>, to call
- * <code>operator new</code> directly, or to call placement \c new, it
- * should be defined to \c 0 to alter the default behaviour.  Unless, of
- * course, one is willing to take the trouble to write something like:
- * @code
- * # ifdef new
- * #   define _NEW_REDEFINED
- * #   undef new
- * # endif
- *
- * // Code that uses new is here
- *
- * # ifdef _NEW_REDEFINED
- * #   ifdef DEBUG_NEW
- * #     define new DEBUG_NEW
- * #   endif
- * #   undef _NEW_REDEFINED
- * # endif
- * @endcode
- */
-#ifndef _DEBUG_NEW_REDEFINE_NEW
-#define _DEBUG_NEW_REDEFINE_NEW 1
-#endif
-
-/* Prototypes */
-int check_leaks();
-void* operator new(size_t size, const char* file, int line);
-void* operator new[](size_t size, const char* file, int line);
-#if HAS_PLACEMENT_DELETE
-void operator delete(void* pointer, const char* file, int line) throw();
-void operator delete[](void* pointer, const char* file, int line) throw();
-#endif
-#if defined(_MSC_VER) && _MSC_VER < 1300
-// MSVC 6 requires the following declarations; or the non-placement
-// new[]/delete[] will not compile.
-void* operator new[](size_t) throw(std::bad_alloc);
-void operator delete[](void*) throw();
-#endif
-
-/* Control variables */
-extern bool new_autocheck_flag; // default to true: call check_leaks() on exit
-extern bool new_verbose_flag;   // default to false: no verbose information
-extern FILE* new_output_fp;     // default to stderr: output to console
-extern const char* new_progname;// default to NULL; should be assigned argv[0]
-
-/**
- * @def DEBUG_NEW
- *
- * The macro to catch file/line information on allocation.  If
- * #_DEBUG_NEW_REDEFINE_NEW is not defined, one can use this macro
- * directly; otherwise \c new will be defined to it, and one must use
- * \c new instead.
- */
-#define DEBUG_NEW new(__FILE__, __LINE__)
-
-# if _DEBUG_NEW_REDEFINE_NEW
-#   define new DEBUG_NEW
-# endif
-# ifdef _DEBUG_NEW_EMULATE_MALLOC
-#   include <stdlib.h>
-#   ifdef new
-#     define malloc(s) ((void*)(new char[s]))
-#   else
-#     define malloc(s) ((void*)(DEBUG_NEW char[s]))
-#   endif
-#   define free(p) delete[] (char*)(p)
-# endif
-
-/**
- * \brief Part of Wu Yongwei's new/delete debug
- * memory leak detector.
- *
- * Counter class for on-exit leakage check.
- */
-class __debug_new_counter
-{
-    static int _count;
-public:
-    __debug_new_counter();
-    ~__debug_new_counter();
-};
-/** Counting object for each file including debug_new.h. */
-static __debug_new_counter __debug_new_count;
-
-#endif // _DEBUG_NEW_H
diff -Nru gxemul-0.6.2/src/include/thirdparty/exec_bout.h gxemul-0.7.0+dfsg/src/include/thirdparty/exec_bout.h
--- gxemul-0.6.2/src/include/thirdparty/exec_bout.h	2019-06-22 18:23:25.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/thirdparty/exec_bout.h	2021-11-27 09:42:23.000000000 +0000
@@ -115,20 +115,20 @@
  * macro in cc_info.h .
  */
 
-#define N_MAGIC(x)	((x).a_magic)
-#define N_BADMAG(x)	(((x).a_magic)!=BOUT_BMAGIC)
-#define N_TXTOFF(x)	( sizeof(struct exec) )
-#define N_DATOFF(x)	( N_TXTOFF(x) + (x).a_text )
-#define N_TROFF(x)	( N_DATOFF(x) + (x).a_data )
-#define N_DROFF(x)	( N_TROFF(x) + (x).a_trsize )
-#define N_SYMOFF(x)	( N_DROFF(x) + (x).a_drsize )
-#define N_STROFF(x)	( N_SYMOFF(x) + (x).a_syms )
-#define N_CCINFO	( 0x17 )
-#define N_HAS_CCINFO(x)	(((x).a_ccinfo)==N_CCINFO)
+#define BOUT_N_MAGIC(x)	((x).a_magic)
+#define BOUT_N_BADMAG(x)	(((x).a_magic)!=BOUT_BMAGIC)
+#define BOUT_N_TXTOFF(x)	( sizeof(struct exec) )
+#define BOUT_N_DATOFF(x)	( N_TXTOFF(x) + (x).a_text )
+#define BOUT_N_TROFF(x)	( N_DATOFF(x) + (x).a_data )
+#define BOUT_N_DROFF(x)	( N_TROFF(x) + (x).a_trsize )
+#define BOUT_N_SYMOFF(x)	( N_DROFF(x) + (x).a_drsize )
+#define BOUT_N_STROFF(x)	( N_SYMOFF(x) + (x).a_syms )
+#define BOUT_N_CCINFO	( 0x17 )
+#define BOUT_N_HAS_CCINFO(x)	(((x).a_ccinfo)==N_CCINFO)
 
 /* A single entry in the symbol table
  */
-struct nlist {
+struct bout_nlist {
 	union {
 		char	*n_name;
 		struct nlist *n_next;
@@ -143,16 +143,16 @@
 
 /* Legal values of n_type
  */
-#define N_UNDF	0	/* Undefined symbol	*/
-#define N_ABS	2	/* Absolute symbol	*/
-#define N_TEXT	4	/* Text symbol		*/
-#define N_DATA	6	/* Data symbol		*/
-#define N_BSS	8	/* BSS symbol		*/
-#define N_FN	31	/* Filename symbol	*/
-
-#define N_EXT	1	/* External symbol (OR'd in with one of above)	*/
-#define N_TYPE	036	/* Mask for all the type bits			*/
-#define N_STAB	0340	/* Mask for all bits used for SDB entries 	*/
+#define BOUT_N_UNDF	0	/* Undefined symbol	*/
+#define BOUT_N_ABS	2	/* Absolute symbol	*/
+#define BOUT_N_TEXT	4	/* Text symbol		*/
+#define BOUT_N_DATA	6	/* Data symbol		*/
+#define BOUT_N_BSS	8	/* BSS symbol		*/
+#define BOUT_N_FN	31	/* Filename symbol	*/
+
+#define BOUT_N_EXT	1	/* External symbol (OR'd in with one of above)	*/
+#define BOUT_N_TYPE	036	/* Mask for all the type bits			*/
+#define BOUT_N_STAB	0340	/* Mask for all bits used for SDB entries 	*/
 
 /* MEANING OF 'n_other'
  *
@@ -185,23 +185,23 @@
  * Note that an N_CALLNAME entry *must* have a corresponding N_BALNAME entry,
  * but not every N_BALNAME entry must have an N_CALLNAME entry.
  */
-#define N_ORDINARY       ((unsigned) 0)
+#define BOUT_N_ORDINARY       ((unsigned) 0)
 
-#define N_BALNAME	 ((unsigned) 0xfe)
-#define N_CALLNAME	 ((unsigned) 0xff)
+#define BOUT_N_BALNAME	 ((unsigned) 0xfe)
+#define BOUT_N_CALLNAME	 ((unsigned) 0xff)
 
-#define MASK( V ) ((sizeof(V) == 1) ? 0x000000ff :\
+#define BOUT_MASK( V ) ((sizeof(V) == 1) ? 0x000000ff :\
 		  ((sizeof(V) == 2) ? 0x0000ffff :\
 		                      0x0000ffff))
 
 /* Get unsigned bits: */
-#define GET_UBITS( V ) ((unsigned) (V & MASK( V )))
+#define BOUT_GET_UBITS( V ) ((unsigned) (V & BOUT_MASK( V )))
 
-#define IS_ORDINARY(x)   (GET_UBITS(x) == N_ORDINARY)
-#define IS_CALLNAME(x)	 (GET_UBITS(x) == N_CALLNAME)
-#define IS_BALNAME(x)	 (GET_UBITS(x) == N_BALNAME) 
-#define IS_SYSPROCIDX(x) (GET_UBITS(x) > N_ORDINARY &&\
-			  GET_UBITS(x) < N_BALNAME)
+#define BOUT_IS_ORDINARY(x)   (BOUT_GET_UBITS(x) == BOUT_N_ORDINARY)
+#define BOUT_IS_CALLNAME(x)	 (BOUT_GET_UBITS(x) == BOUT_N_CALLNAME)
+#define BOUT_IS_BALNAME(x)	 (BOUT_GET_UBITS(x) == BOUT_N_BALNAME) 
+#define BOUT_IS_SYSPROCIDX(x) (BOUT_GET_UBITS(x) > BOUT_N_ORDINARY &&\
+			  BOUT_GET_UBITS(x) < BOUT_N_BALNAME)
 
 /*
  * Note that the following data structure won't compile using a 16-bit 
@@ -209,7 +209,7 @@
  * (mondb).  So just ifdef the structure out of existence...
  */
 #ifndef CC_16BIT
-struct relocation_info {
+struct bout_relocation_info {
 	int	 r_address;	/* File address of item to be relocated	*/
 	unsigned
 		r_symbolnum:24,/* Index of symbol on which relocation is based,
diff -Nru gxemul-0.6.2/src/include/thirdparty/fast_mutex.h gxemul-0.7.0+dfsg/src/include/thirdparty/fast_mutex.h
--- gxemul-0.6.2/src/include/thirdparty/fast_mutex.h	2019-06-22 18:23:25.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/thirdparty/fast_mutex.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,332 +0,0 @@
-/*
- * Modified for GXemul:
- *
- *	1. Classes have Doxygen brief sections, indicating that they are
- *	   part of Wu Yongwei's debug new/delete package.
- */
-
-// -*- Mode: C++; tab-width: 4; c-basic-offset: 4; indent-tabs-mode: nil -*-
-// vim:tabstop=4:shiftwidth=4:expandtab:
-
-/*
- * Copyright (C) 2004-2005 Wu Yongwei <adah at users dot sourceforge dot net>
- *
- * This software is provided 'as-is', without any express or implied
- * warranty.  In no event will the authors be held liable for any
- * damages arising from the use of this software.
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute
- * it freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must
- *    not claim that you wrote the original software. If you use this
- *    software in a product, an acknowledgment in the product
- *    documentation would be appreciated but is not required.
- * 2. Altered source versions must be plainly marked as such, and must
- *    not be misrepresented as being the original software.
- * 3. This notice may not be removed or altered from any source
- *    distribution.
- *
- * This file is part of Stones of Nvwa:
- *      http://sourceforge.net/projects/nvwa
- *
- */
-
-/**
- * @file    fast_mutex.h
- *
- * A fast mutex implementation for POSIX and Win32.
- *
- * @version 1.18, 2005/05/06
- * @author  Wu Yongwei
- *
- */
-
-#ifndef _FAST_MUTEX_H
-#define _FAST_MUTEX_H
-
-# if !defined(_NOTHREADS)
-#   if !defined(_WIN32THREADS) && \
-            (defined(_WIN32) && defined(_MT))
-//      Automatically use _WIN32THREADS when specifying -MT/-MD in MSVC,
-//      or -mthreads in MinGW GCC.
-#       define _WIN32THREADS
-#   elif !defined(_PTHREADS) && \
-            defined(_REENTRANT)
-//      Automatically use _PTHREADS when specifying -pthread in GCC.
-//      N.B. I do not detect on _PTHREAD_H since libstdc++-v3 under
-//      Linux will silently include <pthread.h> anyway.
-#       define _PTHREADS
-#   endif
-# endif
-
-# if !defined(_PTHREADS) && !defined(_WIN32THREADS) && !defined(_NOTHREADS)
-#   define _NOTHREADS
-# endif
-
-# if defined(_NOTHREADS)
-#   if defined(_PTHREADS) || defined(_WIN32THREADS)
-#       undef _NOTHREADS
-#       error "Cannot define multi-threaded mode with -D_NOTHREADS"
-#       if defined(__MINGW32__) && defined(_WIN32THREADS) && !defined(_MT)
-#           error "Be sure to specify -mthreads with -D_WIN32THREADS"
-#       endif
-#   endif
-# endif
-
-# ifndef _FAST_MUTEX_CHECK_INITIALIZATION
-/**
- * Macro to control whether to check for initialization status for each
- * lock/unlock operation.  Defining it to a non-zero value will enable
- * the check, so that the construction/destruction of a static object
- * using a static fast_mutex not yet constructed or already destroyed
- * will work (with lock/unlock operations ignored).  Defining it to zero
- * will disable to check.
- */
-#   define _FAST_MUTEX_CHECK_INITIALIZATION 1
-# endif
-
-# if defined(_PTHREADS) && defined(_WIN32THREADS)
-//  Some C++ libraries have _PTHREADS defined even on Win32 platforms.
-//  Thus this hack.
-#   undef _PTHREADS
-# endif
-
-# ifdef _DEBUG
-#   include <stdio.h>
-#   include <stdlib.h>
-/** Macro for fast_mutex assertions.  Real version (for debug mode). */
-#   define _FAST_MUTEX_ASSERT(_Expr, _Msg) \
-        if (!(_Expr)) { \
-            fprintf(stderr, "fast_mutex::%s\n", _Msg); \
-            abort(); \
-        }
-# else
-/** Macro for fast_mutex assertions.  Fake version (for release mode). */
-#   define _FAST_MUTEX_ASSERT(_Expr, _Msg) \
-        ((void)0)
-# endif
-
-# ifdef _PTHREADS
-#   include <pthread.h>
-/**
- * Macro alias to `volatile' semantics.  Here it is truly volatile since
- * it is in a multi-threaded (POSIX threads) environment.
- */
-#   define __VOLATILE volatile
-    /**
-     * \brief Part of Wu Yongwei's new/delete debug
-     * memory leak detector.
-     *
-     * Class for non-reentrant fast mutexes.  This is the implementation
-     * for POSIX threads.
-     */
-    class fast_mutex
-    {
-        pthread_mutex_t _M_mtx_impl;
-#       if _FAST_MUTEX_CHECK_INITIALIZATION
-        bool _M_initialized;
-#       endif
-#       ifdef _DEBUG
-        bool _M_locked;
-#       endif
-    public:
-        fast_mutex()
-#       ifdef _DEBUG
-            : _M_locked(false)
-#       endif
-        {
-            ::pthread_mutex_init(&_M_mtx_impl, NULL);
-#       if _FAST_MUTEX_CHECK_INITIALIZATION
-            _M_initialized = true;
-#       endif
-        }
-        ~fast_mutex()
-        {
-            _FAST_MUTEX_ASSERT(!_M_locked, "~fast_mutex(): still locked");
-#       if _FAST_MUTEX_CHECK_INITIALIZATION
-            _M_initialized = false;
-#       endif
-            ::pthread_mutex_destroy(&_M_mtx_impl);
-        }
-        void lock()
-        {
-#       if _FAST_MUTEX_CHECK_INITIALIZATION
-            if (!_M_initialized)
-                return;
-#       endif
-            ::pthread_mutex_lock(&_M_mtx_impl);
-#       ifdef _DEBUG
-            // The following assertion should _always_ be true for a
-            // real `fast' pthread_mutex.  However, this assertion can
-            // help sometimes, when people forget to use `-lpthread' and
-            // glibc provides an empty implementation.  Having this
-            // assertion is also more consistent.
-            _FAST_MUTEX_ASSERT(!_M_locked, "lock(): already locked");
-            _M_locked = true;
-#       endif
-        }
-        void unlock()
-        {
-#       if _FAST_MUTEX_CHECK_INITIALIZATION
-            if (!_M_initialized)
-                return;
-#       endif
-#       ifdef _DEBUG
-            _FAST_MUTEX_ASSERT(_M_locked, "unlock(): not locked");
-            _M_locked = false;
-#       endif
-            ::pthread_mutex_unlock(&_M_mtx_impl);
-        }
-    private:
-        fast_mutex(const fast_mutex&);
-        fast_mutex& operator=(const fast_mutex&);
-    };
-# endif // _PTHREADS
-
-# ifdef _WIN32THREADS
-#   include <windows.h>
-/**
- * Macro alias to `volatile' semantics.  Here it is truly volatile since
- * it is in a multi-threaded (Win32 threads) environment.
- */
-#   define __VOLATILE volatile
-    /**
-     * \brief Part of Wu Yongwei's new/delete debug
-     * memory leak detector.
-     *
-     * Class for non-reentrant fast mutexes.  This is the implementation
-     * for Win32 threads.
-     */
-    class fast_mutex
-    {
-        CRITICAL_SECTION _M_mtx_impl;
-#       if _FAST_MUTEX_CHECK_INITIALIZATION
-        bool _M_initialized;
-#       endif
-#       ifdef _DEBUG
-        bool _M_locked;
-#       endif
-    public:
-        fast_mutex()
-#       ifdef _DEBUG
-            : _M_locked(false)
-#       endif
-        {
-            ::InitializeCriticalSection(&_M_mtx_impl);
-#       if _FAST_MUTEX_CHECK_INITIALIZATION
-            _M_initialized = true;
-#       endif
-        }
-        ~fast_mutex()
-        {
-            _FAST_MUTEX_ASSERT(!_M_locked, "~fast_mutex(): still locked");
-#       if _FAST_MUTEX_CHECK_INITIALIZATION
-            _M_initialized = false;
-#       endif
-            ::DeleteCriticalSection(&_M_mtx_impl);
-        }
-        void lock()
-        {
-#       if _FAST_MUTEX_CHECK_INITIALIZATION
-            if (!_M_initialized)
-                return;
-#       endif
-            ::EnterCriticalSection(&_M_mtx_impl);
-#       ifdef _DEBUG
-            _FAST_MUTEX_ASSERT(!_M_locked, "lock(): already locked");
-            _M_locked = true;
-#       endif
-        }
-        void unlock()
-        {
-#       if _FAST_MUTEX_CHECK_INITIALIZATION
-            if (!_M_initialized)
-                return;
-#       endif
-#       ifdef _DEBUG
-            _FAST_MUTEX_ASSERT(_M_locked, "unlock(): not locked");
-            _M_locked = false;
-#       endif
-            ::LeaveCriticalSection(&_M_mtx_impl);
-        }
-    private:
-        fast_mutex(const fast_mutex&);
-        fast_mutex& operator=(const fast_mutex&);
-    };
-# endif // _WIN32THREADS
-
-# ifdef _NOTHREADS
-/**
- * Macro alias to `volatile' semantics.  Here it is not truly volatile
- * since it is in a single-threaded environment.
- */
-#   define __VOLATILE
-    /**
-     * \brief Part of Wu Yongwei's new/delete debug
-     * memory leak detector.
-     *
-     * Class for non-reentrant fast mutexes.  This is the null
-     * implementation for single-threaded environments.
-     */
-    class fast_mutex
-    {
-#       ifdef _DEBUG
-        bool _M_locked;
-#       endif
-    public:
-        fast_mutex()
-#       ifdef _DEBUG
-            : _M_locked(false)
-#       endif
-        {
-        }
-        ~fast_mutex()
-        {
-            _FAST_MUTEX_ASSERT(!_M_locked, "~fast_mutex(): still locked");
-        }
-        void lock()
-        {
-#       ifdef _DEBUG
-            _FAST_MUTEX_ASSERT(!_M_locked, "lock(): already locked");
-            _M_locked = true;
-#       endif
-        }
-        void unlock()
-        {
-#       ifdef _DEBUG
-            _FAST_MUTEX_ASSERT(_M_locked, "unlock(): not locked");
-            _M_locked = false;
-#       endif
-        }
-    private:
-        fast_mutex(const fast_mutex&);
-        fast_mutex& operator=(const fast_mutex&);
-    };
-# endif // _NOTHREADS
-
-/**
- * \brief Part of Wu Yongwei's new/delete debug
- * memory leak detector.
- *
- * An acquistion-on-initialization lock class based on fast_mutex.
- */
-class fast_mutex_autolock
-{
-    fast_mutex& _M_mtx;
-public:
-    explicit fast_mutex_autolock(fast_mutex& __mtx) : _M_mtx(__mtx)
-    {
-        _M_mtx.lock();
-    }
-    ~fast_mutex_autolock()
-    {
-        _M_mtx.unlock();
-    }
-private:
-    fast_mutex_autolock(const fast_mutex_autolock&);
-    fast_mutex_autolock& operator=(const fast_mutex_autolock&);
-};
-
-#endif // _FAST_MUTEX_H
diff -Nru gxemul-0.6.2/src/include/thirdparty/mb89352reg.h gxemul-0.7.0+dfsg/src/include/thirdparty/mb89352reg.h
--- gxemul-0.6.2/src/include/thirdparty/mb89352reg.h	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/thirdparty/mb89352reg.h	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,231 @@
+/*	$OpenBSD: mb89352reg.h,v 1.4 2008/10/17 18:30:20 okan Exp $	*/
+/*	$NetBSD: mb89352reg.h,v 1.3 2003/08/07 16:31:02 agc Exp $	*/
+/*	NecBSD: mb89352reg.h,v 1.3 1998/03/14 07:04:34 kmatsuda Exp 	*/
+
+/*-
+ * Copyright (c) 1990, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Van Jacobson of Lawrence Berkeley Laboratory.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)scsireg.h	8.1 (Berkeley) 6/10/93
+ */
+
+/*-
+ * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Van Jacobson of Lawrence Berkeley Laboratory.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)scsireg.h	8.1 (Berkeley) 6/10/93
+ */
+/*
+ * [NetBSD for NEC PC-98 series]
+ *  Copyright (c) 1996, 1997, 1998
+ *	NetBSD/pc98 porting staff. All rights reserved.
+ *  Copyright (c) 1996, 1997, 1998
+ *	Kouichi Matsuda. All rights reserved.
+ */
+
+/*
+ * FUJITSU MB89352A SCSI Protocol Controller Hardware Description.
+ */
+
+/* Definitions, most of them has turned out to be unneccesary, but here they
+ * are anyway.
+ */
+
+#define BDID		0x00	/* Bus Device ID (R/W) */
+#define SCTL		0x01	/* SPC Control register (R/W) */
+#define SCMD		0x02	/* Command Register (R/W) */
+#define TMOD		0x03	/* Transmit Mode Register (synch models) */
+#define INTS		0x04	/* Interrupt sense (R); Interrupt Reset (W) */
+#define PSNS		0x05	/* Phase Sense (R); SPC Diagnostic Control (W) */
+#define SSTS		0x06	/* SPC status (R/O) */
+#define SERR		0x07	/* SPC error status (R/O) */
+#define PCTL		0x08	/* Phase Control (R/W) */
+#define MBC		0x09	/* Modified Byte Counter (R/O) */
+#define DREG		0x0a	/* Data Register (R/W) */
+#define TEMP		0x0b	/* Temporary Register (R/W) */
+#define TCH		0x0c	/* Transfer Counter High (R/W) */
+#define TCM		0x0d	/* Transfer Counter Middle (R/W) */
+#define TCL		0x0e	/* Transfer Counter Low (R/W) */
+#define EXBF		0x0f	/* External Buffer (synch models) */
+
+/* What all the bits do */
+
+/* SCSI_BDID */
+/* SCSI selection/reselection ID (both target *and* initiator) */
+#define SELID7		0x80
+#define SELID6		0x40
+#define SELID5		0x20
+#define SELID4		0x10
+#define SELID3		0x08
+#define SELID2		0x04
+#define SELID1		0x02
+#define SELID0		0x01
+
+/* SCSI_SCTL */
+#define SCTL_DISABLE	0x80
+#define SCTL_CTRLRST	0x40
+#define SCTL_DIAG	0x20
+#define SCTL_ABRT_ENAB	0x10
+#define SCTL_PARITY_ENAB 0x08
+#define SCTL_SEL_ENAB	0x04
+#define SCTL_RESEL_ENAB	0x02
+#define SCTL_INTR_ENAB	0x01
+
+/* SCSI_SCMD */
+#define SCMD_RST	0x10
+#define SCMD_ICPT_XFR	0x08
+#define SCMD_PROG_XFR	0x04
+#define SCMD_PAD	0x01	/* if initiator */
+#define SCMD_PERR_STOP	0x01	/* if target */
+	/* command codes */
+#define SCMD_BUS_REL	0x00
+#define SCMD_SELECT	0x20
+#define SCMD_RST_ATN	0x40
+#define SCMD_SET_ATN	0x60
+#define SCMD_XFR	0x80
+#define SCMD_XFR_PAUSE	0xa0
+#define SCMD_RST_ACK	0xc0
+#define SCMD_SET_ACK	0xe0
+
+/* SCSI_TMOD */
+#define TMOD_SYNC	0x80
+
+/* SCSI_INTS */
+#define INTS_SEL	0x80
+#define INTS_RESEL	0x40
+#define INTS_DISCON	0x20
+#define INTS_CMD_DONE	0x10
+#define INTS_SRV_REQ	0x08
+#define INTS_TIMEOUT	0x04
+#define INTS_HARD_ERR	0x02
+#define INTS_RST	0x01
+
+/* SCSI_PSNS */
+#define PSNS_REQ	0x80
+#define PSNS_ACK	0x40
+#define PSNS_ATN	0x20
+#define PSNS_SEL	0x10
+#define PSNS_BSY	0x08
+
+/* PSNS */
+#define REQI		0x80
+#define ACKI		0x40
+#define ATNI		0x20
+#define SELI		0x10
+#define BSYI		0x08
+#define MSGI		0x04
+#define CDI		0x02
+#define IOI		0x01
+
+/* Important! The 3 most significant bits of this register, in initiator mode,
+ * represents the "expected" SCSI bus phase and can be used to trigger phase
+ * mismatch and phase change interrupts.  But more important:  If there is a
+ * phase mismatch the chip will not transfer any data!  This is actually a nice
+ * feature as it gives us a bit more control over what is happening when we are
+ * bursting data (in) through the FIFOs and the phase suddenly changes from
+ * DATA IN to STATUS or MESSAGE IN.  The transfer will stop and wait for the
+ * proper phase to be set in this register instead of dumping the bits into the
+ * FIFOs.
+ */
+#if 0
+#define REQO		0x80
+#define ACKO		0x40
+#define ATNO		0x20
+#define SELO		0x10
+#define BSYO		0x08
+#endif
+/* PCTL */
+#define MSGO		0x04
+#define CDO		0x02
+#define IOO		0x01
+
+/* Information transfer phases */
+#define PH_DATAOUT	(0)
+#define PH_DATAIN	(IOI)
+#define PH_CMD		(CDI)
+#define PH_STAT		(CDI | IOI)
+#define PH_MSGOUT	(MSGI | CDI)
+#define PH_MSGIN	(MSGI | CDI | IOI)
+
+#define PH_MASK		(MSGI | CDI | IOI)
+
+#define PH_INVALID	0xff
+
+/* SCSI_SSTS */
+#define SSTS_INITIATOR	0x80
+#define SSTS_TARGET	0x40
+#define SSTS_BUSY	0x20
+#define SSTS_XFR	0x10
+#define SSTS_ACTIVE	(SSTS_INITIATOR|SSTS_XFR)
+#define SSTS_RST	0x08
+#define SSTS_TCZERO	0x04
+#define SSTS_DREG_FULL	0x02
+#define SSTS_DREG_EMPTY	0x01
+
+/* SCSI_SERR */
+#define SERR_SCSI_PAR	0x80
+#define SERR_SPC_PAR	0x40
+#define SERR_TC_PAR	0x08
+#define SERR_PHASE_ERR	0x04
+#define SERR_SHORT_XFR	0x02
+#define SERR_OFFSET	0x01
+
+/* SCSI_PCTL */
+#define PCTL_BFINT_ENAB	0x80
diff -Nru gxemul-0.6.2/src/include/thirdparty/sgi_arcbios.h gxemul-0.7.0+dfsg/src/include/thirdparty/sgi_arcbios.h
--- gxemul-0.6.2/src/include/thirdparty/sgi_arcbios.h	2019-06-22 18:23:25.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/thirdparty/sgi_arcbios.h	2021-11-27 09:42:23.000000000 +0000
@@ -117,6 +117,11 @@
 	uint32_t	AdapterType;
 	uint32_t	AdapterVectorLength;
 	uint32_t	AdapterVector;			/*  was void *  */
+
+	/*  GXemul additions, to make the struct the same length as on my real O2:  */
+	uint32_t	unknown0;
+	uint32_t	unknown1;
+	uint32_t	unknown2;
 };
 
 /*
diff -Nru gxemul-0.6.2/src/include/thirdparty/static_assert.h gxemul-0.7.0+dfsg/src/include/thirdparty/static_assert.h
--- gxemul-0.6.2/src/include/thirdparty/static_assert.h	2019-06-22 18:23:25.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/thirdparty/static_assert.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,61 +0,0 @@
-/*
- * Modified for GXemul:
- *
- *      1. Better Doxygen comment for struct __nvwa_compile_time_error.
- */
-
-// -*- Mode: C++; tab-width: 4; c-basic-offset: 4; indent-tabs-mode: nil -*-
-// vim:tabstop=4:shiftwidth=4:expandtab:
-
-/*
- * Copyright (C) 2004-2005 Wu Yongwei <adah at users dot sourceforge dot net>
- *
- * This software is provided 'as-is', without any express or implied
- * warranty.  In no event will the authors be held liable for any
- * damages arising from the use of this software.
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute
- * it freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must
- *    not claim that you wrote the original software. If you use this
- *    software in a product, an acknowledgment in the product
- *    documentation would be appreciated but is not required.
- * 2. Altered source versions must be plainly marked as such, and must
- *    not be misrepresented as being the original software.
- * 3. This notice may not be removed or altered from any source
- *    distribution.
- *
- * This file is part of Stones of Nvwa:
- *      http://sourceforge.net/projects/nvwa
- *
- */
-
-/**
- * @file    static_assert.h
- *
- * Template class to check validity duing compile time (adapted from Loki).
- *
- * @version 1.2, 2005/11/22
- * @author  Wu Yongwei
- *
- */
-
-#ifndef STATIC_ASSERT
-
-template <bool> struct __nvwa_compile_time_error;
-
-/**
- * \brief Part of Wu Yongwei's new/delete debug
- * memory leak detector.
- */
-template <>     struct __nvwa_compile_time_error<true> {};
-
-#define STATIC_ASSERT(_Expr, _Msg) \
-    { \
-        __nvwa_compile_time_error<((_Expr) != 0)> ERROR_##_Msg; \
-        (void)ERROR_##_Msg; \
-    }
-
-#endif // STATIC_ASSERT
diff -Nru gxemul-0.6.2/src/include/UI.h gxemul-0.7.0+dfsg/src/include/UI.h
--- gxemul-0.6.2/src/include/UI.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/UI.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,213 +0,0 @@
-#ifndef UI_H
-#define	UI_H
-
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-class Component;
-class GXemul;
-
-
-/**
- * \brief Base class for a User Interface.
- */
-class UI
-	: public ReferenceCountable
-{
-public:
-	class SetIndentationMessageHelper
-	{
-	public:
-		SetIndentationMessageHelper(UI* ui, const string& msg)
-			: m_UI(ui)
-		{
-			m_oldMsg = m_UI->GetIndentationMessage();
-			m_UI->SetIndentationMessage(msg);
-		}
-
-		~SetIndentationMessageHelper()
-		{
-			m_UI->SetIndentationMessage(m_oldMsg);
-		}
-
-	private:
-		UI *	m_UI;
-		string	m_oldMsg;
-	};
-
-public:
-	/**
-	 * \brief Constructs a User Interface.
-	 *
-	 * @param gxemul A pointer to the GXemul owner instance.
-	 */
-	UI(GXemul* gxemul)
-	    : m_gxemul(gxemul)
-	{
-	}
-
-	virtual ~UI()
-	{
-	}
-
-	/**
-	 * \brief Initializes the UI.
-	 */
-	virtual void Initialize() = 0;
-
-	/**
-	 * \brief Shows a startup banner.
-	 */
-	virtual void ShowStartupBanner() = 0;
-
-	/**
-	 * \brief Updates various UI elements.
-	 *
-	 * Called whenever:
-	 * <ul>
-	 *   <li>the undo/redo-applicability changes
-	 *   <li>the name of the emulation changes
-	 *   <li>the RunState changes
-	 * </ul>
-	 */
-	virtual void UpdateUI() = 0;
-
-	/**
-	 * \brief Sets an indentation message, which indents all debug output.
-	 *
-	 * Note: An UI implementation may change the indentation string. E.g.
-	 * from "step X: " to "        ".
-	 *
-	 * @param msg The indentation message. If the message is an empty
-	 *	string, indentation is not used.
-	 */
-	void SetIndentationMessage(const string& msg)
-	{
-		m_indentationMsg = msg;
-	}
-
-	/**
-	 * \brief Gets the indentation message.
-	 *
-	 * @return The indentation message. If the message is an empty
-	 *	string, indentation is not used.
-	 */
-	string GetIndentationMessage() const
-	{
-		return m_indentationMsg;
-	}
-
-	/**
-	 * \brief Shows a debug message.
-	 *
-	 * @param msg The message to show.
-	 */
-	virtual void ShowDebugMessage(const string& msg) = 0;
-
-	/**
-	 * \brief Shows a debug message for a Component.
-	 *
-	 * Usually, this involves formatting the debug message using
-	 * Component::GenerateShortestPossiblePath().
-	 *
-	 * If the runstate is GXemul::Running, the debug message
-	 * is encapsulated by "[ ]" brackets, making the debug message very
-	 * similar to pre-0.6.0 debug output style.
-	 *
-	 * @param component A pointer to the Component.
-	 * @param msg The message to show.
-	 */
-	virtual void ShowDebugMessage(Component* component, const string& msg) = 0;
-
-	/**
-	 * \brief Shows a command being executed.
-	 *
-	 * @param command The command being executed.
-	 */
-	virtual void ShowCommandMessage(const string& command) = 0;
-
-	/**
-	 * \brief Shows a fatal error message.
-	 *
-	 * After showing the fatal error message, the application
-	 * is expected to terminate. In a GUI implementation, it
-	 * is therefore good to wait for the user to acknowledge
-	 * the error message before returning.
-	 *
-	 * @param msg The message to show.
-	 */
-	virtual void FatalError(const string& msg) = 0;
-
-	/**
-	 * \brief Redisplays the interactive command input line.
-	 *
-	 * This function generally displays a prompt (e.g. "GXemul> ")
-	 * followed by the input line, placing the cursor position at
-	 * the correct position on the input line.
-	 *
-	 * @param inputline The entire input line.
-	 * @param cursorPosition The current cursor position. 0 is at the
-	 *	leftmost position.
-	 */
-	virtual void RedisplayInputLine(const string& inputline,
-	    size_t cursorPosition) = 0;
-
-	/**
-	 * \brief Executed by the CommandInterpreter when a line has been
-	 * completed (with a newline).
-	 *
-	 * Usually this clears the current line, and (if possible) moves
-	 * down to a new line.
-	 */
-	virtual void InputLineDone() = 0;
-
-	/**
-	 * \brief Runs the UI's main loop.
-	 *
-	 * The return code should be the exit code that the gxemul binary
-	 * should return.
- 	 *
-	 * @return 0 on success, non-zero on failure.
-	 */
-	virtual int MainLoop() = 0;
-
-	/**
-	 * \brief Shuts down the UI.
-	 *
-	 * Called from e.g. the "quit" command.
-	 */
-	virtual void Shutdown() = 0;
-
-protected:
-	GXemul*		m_gxemul;
-	string		m_indentationMsg;
-};
-
-
-#endif	// UI_H
diff -Nru gxemul-0.6.2/src/include/UnitTest.h gxemul-0.7.0+dfsg/src/include/UnitTest.h
--- gxemul-0.6.2/src/include/UnitTest.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/UnitTest.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,233 +0,0 @@
-#ifndef UNITTEST_H
-#define	UNITTEST_H
-
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "misc.h"
-
-#include <exception>
-
-
-/**
- * \brief An exception thrown by unit test cases that fail.
- */
-class UnitTestFailedException
-	: public std::exception
-{
-public:
-	UnitTestFailedException(const string& strMessage)
-		: m_strMessage(strMessage)
-	{
-	}
-
-	virtual ~UnitTestFailedException() throw ()
-	{
-	}
-
-	/**
-	 * \brief Retrieves the error message associated with the exception.
-	 *
-	 * @return a const reference to the error message string
-	 */
-	const string& GetMessage() const
-	{
-		return m_strMessage;
-	}
-
-private:
-	string	m_strMessage;
-};
-
-
-/**
- * \brief Base class for unit testable classes.
- *
- * A class which inherits from the UnitTestable class exposes a function,
- * RunUnitTests(int&, int&), which runs unit tests, and returns the number 
- * of failed test cases.
- */
-class UnitTestable
-{
-public:
-	/**
-	 * \brief Runs unit test cases.
-	 *
-	 * @param nSucceeded A reference to a variable which keeps count
-	 *	of the number of succeeded test cases.
-	 * @param nFailures A reference to a variable which keeps count
-	 *	of the number of failed test cases.
-	 */
-	static void RunUnitTests(int& nSucceeded, int& nFailures);
-};
-
-
-/**
- * \brief A collection of helper functions, for writing simple unit tests.
- */
-class UnitTest
-{
-public:
-	/**
-	 * \brief Runs all unit tests in %GXemul.
-	 *
-	 * If WITHUNITTESTS was not defined in config.h, nothing is tested,
-	 * and zero is returned.
-	 *
-	 * Otherwise, unit tests for all classes that the <tt>configure</tt>
-	 * script detected as using UNITTESTS(classname) are executed.
-	 *
-	 * If a test fails, the UNITTEST(testname) macro in the unit testing
-	 * framework takes care of outputting a line identifying that test to
-	 * std::cerr.
-	 *
-	 * @return zero if no unit tests failed, 1 otherwise.
-	 */
-	static int RunTests();
-
-
-	/*******************************************************************/
-	/*            Helper functions, used by unit test cases            */
-	/*******************************************************************/
-
-	/**
-	 * \brief Asserts that a boolean condition is correct.
-	 *
-	 * If the condition is not true, then Fail is called with the failure
-	 * message.
-	 *
-	 * The failure message can be something like "expected xyz",
-	 * or "the list should be empty at this point".
-	 *
-	 * @param strFailMessage failure message to print to std::cerr
-	 * @param condition The result of some operation, which should be true.
-	 */
-	static void Assert(const string& strFailMessage, bool condition);
-
-	/**
-	 * \brief Asserts that two uint64_t values are equal.
-	 *
-	 * If the values are not equal, Fail is called with the failure message.
-	 *
-	 * The failure message can be something like "expected xyz",
-	 * or "the list should be empty at this point".
-	 *
-	 * @param strFailMessage Failure message to print to std::cerr.
-	 * @param actualValue The actual value.
-	 * @param expectedValue The expected value.
-	 */
-	static void Assert(const string& strFailMessage,
-	    uint64_t actualValue, uint64_t expectedValue);
-
-	/**
-	 * \brief Asserts that two string values are equal.
-	 *
-	 * If the values are not equal, Fail is called with the failure message.
-	 *
-	 * The failure message can be something like "expected xyz",
-	 * or "the list should be empty at this point".
-	 *
-	 * @param strFailMessage Failure message to print to std::cerr.
-	 * @param actualValue The actual value.
-	 * @param expectedValue The expected value.
-	 */
-	static void Assert(const string& strFailMessage,
-	    const string& actualValue, const string& expectedValue);
-
-	/**
-	 * \brief Fails a unit test unconditionally, by throwing a
-	 * UnitTestFailedException.
-	 *
-	 * @param strMessage failure message
-	 */
-	static void Fail(const string& strMessage);
-};
-
-
-#ifdef WITHUNITTESTS
-#include <iostream>
-/**
- * \brief Helper for unit test case execution.
- *
- * The main purpose, appart from making the code look more compact,
- * of having a macro for this is that the <tt>configure</tt> script finds
- * all .cc files that use this macro, and generates lists of header files
- * to include and lists of RunUnitTests functions to call. These are then
- * included and run from UnitTest::RunTests.
- *
- * See the comment for UNITTEST for details on how to use it.
- */
-#define UNITTESTS(class) \
-	void class::RunUnitTests(int& nSucceeded, int& nFailures)
-
-/**
- * \brief Helper for unit test case execution.
- *
- * For each test case that throws a UnitTestFailedException, the number
- * of failures is increased. For test cases that don't fail, the number
- * of successful test cases is increased instead.
- *
- * Usage: (usually at the end of a class implementation file)<pre>
- *	\#ifdef WITHUNITTESTS
- *
- *	static void MyClass::Test_MyClass_SomeTest()
- *	{
- *		UnitTest::Assert("expected blah blah", bool_condition);
- *		... more asserts here ...
- *	}
- *
- *	...
- *
- *	UNITTESTS(MyClass)
- *	{
- *		UNITTEST(Test_MyClass_SomeTest);
- *		UNITTEST(Test_MyClass_AnotherTest);
- *		... more test cases here ...
- *	}
- *
- *	\#endif // WITHUNITTESTS</pre>
- *
- * Note that MyClass (in the example above) should inherit from the
- * UnitTestable class.
- */
-#define UNITTEST(functionname)	try {					\
-	std::cout << "### " #functionname "\n";				\
-	(functionname)();						\
-	++ (nSucceeded);						\
-} catch (UnitTestFailedException& ex) {					\
-	std::cout.flush();						\
-	std::cerr << "\n### " #functionname " (" __FILE__ " line "	\
-		<< __LINE__ << ") failed!\n"				\
-		"    > " << ex.GetMessage() << "\n";			\
-	std::cerr.flush();						\
-	++ (nFailures);   						\
-}
-
-#endif
-
-
-#endif	// UNITTEST_H
diff -Nru gxemul-0.6.2/src/include/x11.h gxemul-0.7.0+dfsg/src/include/x11.h
--- gxemul-0.6.2/src/include/x11.h	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/include/x11.h	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #define	X11_H
 
 /*
- *  Copyright (C) 2003-2010  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -31,6 +31,7 @@
  *  Headerfile for src/x11.c.
  */
 
+#include <stdbool.h>
 #include "misc.h"
 
 struct emul;
@@ -49,6 +50,7 @@
 /*  Framebuffer windows:  */
 struct fb_window {
 	int		fb_number;
+	char		*name;
 
 #ifdef WITH_X11
 	/*  x11_fb_winxsize > 0 for a valid fb_window  */
@@ -93,7 +95,7 @@
 #endif
 void x11_init(struct machine *);
 void x11_fb_resize(struct fb_window *win, int new_xsize, int new_ysize);
-void x11_set_standard_properties(struct fb_window *fb_window, char *name);
+void x11_set_standard_properties(struct fb_window *fb_window);
 struct fb_window *x11_fb_init(int xsize, int ysize, char *name,
 	int scaledown, struct machine *);
 void x11_check_event(struct emul *emul);
diff -Nru gxemul-0.6.2/src/machines/automachine_head.c gxemul-0.7.0+dfsg/src/machines/automachine_head.c
--- gxemul-0.6.2/src/machines/automachine_head.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/automachine_head.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,39 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  Automatically register all machines in the src/machines/ subdir.
+ *
+ *  NOTE: automachine_head.c, plus a line for each machine, plus
+ *  automachine_middle.c, plus another line (again) for each machine, plus
+ *  automachine_tail.c should be combined into one. See makeautomachine.sh
+ *  for more info.
+ */
+
+#include <stdio.h>
+
+#include "machine.h"
+
diff -Nru gxemul-0.6.2/src/machines/automachine_head.cc gxemul-0.7.0+dfsg/src/machines/automachine_head.cc
--- gxemul-0.6.2/src/machines/automachine_head.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/automachine_head.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,39 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  Automatically register all machines in the src/machines/ subdir.
- *
- *  NOTE: automachine_head.c, plus a line for each machine, plus
- *  automachine_middle.c, plus another line (again) for each machine, plus
- *  automachine_tail.c should be combined into one. See makeautomachine.sh
- *  for more info.
- */
-
-#include <stdio.h>
-
-#include "machine.h"
-
diff -Nru gxemul-0.6.2/src/machines/automachine_middle.c gxemul-0.7.0+dfsg/src/machines/automachine_middle.c
--- gxemul-0.6.2/src/machines/automachine_middle.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/automachine_middle.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,10 @@
+
+/*
+ *  automachine_init():
+ */
+void automachine_init(void)
+{
+	/*  printf("automachine_init()\n");  */
+
+	/*  automachine_middle.c ends here.  */
+
diff -Nru gxemul-0.6.2/src/machines/automachine_middle.cc gxemul-0.7.0+dfsg/src/machines/automachine_middle.cc
--- gxemul-0.6.2/src/machines/automachine_middle.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/automachine_middle.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,10 +0,0 @@
-
-/*
- *  automachine_init():
- */
-void automachine_init(void)
-{
-	/*  printf("automachine_init()\n");  */
-
-	/*  automachine_middle.c ends here.  */
-
diff -Nru gxemul-0.6.2/src/machines/automachine_tail.c gxemul-0.7.0+dfsg/src/machines/automachine_tail.c
--- gxemul-0.6.2/src/machines/automachine_tail.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/automachine_tail.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,3 @@
+
+}
+
diff -Nru gxemul-0.6.2/src/machines/automachine_tail.cc gxemul-0.7.0+dfsg/src/machines/automachine_tail.cc
--- gxemul-0.6.2/src/machines/automachine_tail.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/automachine_tail.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-
-}
-
diff -Nru gxemul-0.6.2/src/machines/.index gxemul-0.7.0+dfsg/src/machines/.index
--- gxemul-0.6.2/src/machines/.index	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/.index	2021-11-27 09:42:23.000000000 +0000
@@ -1,27 +1,29 @@
-machine_algor.cc  Algorithmic P4032 and P5064 evaluation boards
-machine_alpha.cc  DEC Alpha machines
-machine_androidarm.cc  ARM-based "Android" machines
-machine_arc.cc  ARC (Advanced RISC Computing) machines
-machine_cats.cc  Simtec Electronics' CATS board
-machine_cobalt.cc  Cobalt (MIPS-based)
-machine_dreamcast.cc  SEGA Dreamcast
-machine_evbmips.cc  MIPS evaluation boards (e.g. Malta)
-machine_hpcarm.cc  Handheld ARM-based machines
-machine_hpcmips.cc  Handheld MIPS-based machines
-machine_hpcsh.cc  Handheld SuperH-based machines
-machine_iq80321.cc  Intel IQ80321 (ARM)
-machine_iyonix.cc  A Iyonix machine
-machine_landisk.cc  I-O DATA LanDisk USL-5P
-machine_luna88k.cc  LUNA88K machine
-machine_macppc.cc  Generic PowerPC-based Macintosh machines
-machine_mvme88k.cc  MVME88K machines (MVME187)
-machine_mvmeppc.cc  MVMEPPC machines
-machine_netwinder.cc  NetWinder
-machine_playstation2.cc  Sony PlayStation 2
-machine_pmax.cc  Digital DECstation ("PMAX") machines
-machine_pmppc.cc  Artesyn's PM/PPC board
-machine_prep.cc  Machines conforming to the PowerPC Reference Platform specs
-machine_rpi.cc  Raspberry Pi
-machine_sgi.cc  Silicon Graphics' MIPS-based machines
-machine_test.cc  Various test machines
-machine_vocore.cc  VoCore
+machine_algor.c  Algorithmic P4032 and P5064 evaluation boards
+machine_alpha.c  DEC Alpha machines
+machine_androidarm.c  ARM-based "Android" machines
+machine_arc.c  ARC (Advanced RISC Computing) machines
+machine_cats.c  Simtec Electronics' CATS board
+machine_cobalt.c  Cobalt (MIPS-based)
+machine_cyclonevh.c  Cyclone VH machine
+machine_dreamcast.c  SEGA Dreamcast
+machine_evbmips.c  MIPS evaluation boards (e.g. Malta)
+machine_hp700rx.c  HP 700/RX machine
+machine_hpcarm.c  Handheld ARM-based machines
+machine_hpcmips.c  Handheld MIPS-based machines
+machine_hpcsh.c  Handheld SuperH-based machines
+machine_iq80321.c  Intel IQ80321 (ARM)
+machine_iyonix.c  A Iyonix machine
+machine_landisk.c  I-O DATA LanDisk USL-5P
+machine_luna88k.c  LUNA88K machine
+machine_macppc.c  Generic PowerPC-based Macintosh machines
+machine_mvme88k.c  MVME88K machines (MVME187)
+machine_mvmeppc.c  MVMEPPC machines
+machine_netwinder.c  NetWinder
+machine_playstation2.c  Sony PlayStation 2
+machine_pmax.c  Digital DECstation ("PMAX") machines
+machine_pmppc.c  Artesyn's PM/PPC board
+machine_prep.c  Machines conforming to the PowerPC Reference Platform specs
+machine_rpi.c  Raspberry Pi
+machine_sgi.c  Silicon Graphics' MIPS-based machines
+machine_test.c  Various test machines
+machine_vocore.c  VoCore
diff -Nru gxemul-0.6.2/src/machines/machine_algor.c gxemul-0.7.0+dfsg/src/machines/machine_algor.c
--- gxemul-0.6.2/src/machines/machine_algor.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_algor.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,137 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Algorithmic P4032 and P5064 evaluation boards
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_isa.h"
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+MACHINE_SETUP(algor)
+{
+	char tmpstr[300];
+
+	machine->emulated_hz = 166560000;
+
+	switch (machine->machine_subtype) {
+	case MACHINE_ALGOR_P4032:
+		machine->machine_name = strdup("Algor P4032");
+		break;
+	case MACHINE_ALGOR_P5064:
+		machine->machine_name = strdup("Algor P5064");
+		break;
+	default:fatal("Unimplemented Algor machine.\n");
+		exit(1);
+	}
+
+	/*
+	 *  Algor CPU interrupts:
+	 *
+	 *  7 = CPU count/compare
+	 *  4 = Local
+	 *  3 = PCI
+	 *  2 = ISA
+	 */
+
+	/*  struct pci_data *pci_bus = (struct pci_data *) */  device_add(machine, "v3");
+
+	device_add(machine, "algor addr=0x1ff00000");
+
+	snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].v3",
+	    machine->path, machine->bootstrap_cpu);
+	bus_isa_init(machine, tmpstr, BUS_ISA_EXTERNAL_PIC | BUS_ISA_FDC,
+	    0x1d000000, 0x10000000);
+
+	/*  bus_pci_add(machine, pci_bus, machine->memory, 0, 0, 0,
+	    "dec21143");  */
+
+	if (!machine->prom_emulation)
+		return;
+
+	/*  NetBSD/algor wants these:  */
+
+	/*  a0 = argc  */
+	cpu->cd.mips.gpr[MIPS_GPR_A0] = 2;
+
+	/*  a1 = argv  */
+	cpu->cd.mips.gpr[MIPS_GPR_A1] = (int32_t)0x9fc01000;
+	store_32bit_word(cpu, (int32_t)0x9fc01000, 0x9fc01040);
+	store_32bit_word(cpu, (int32_t)0x9fc01004, 0x9fc01200);
+	store_32bit_word(cpu, (int32_t)0x9fc01008, 0);
+
+	machine->bootstr = strdup(machine->boot_kernel_filename);
+	machine->bootarg = strdup(machine->boot_string_argument);
+	store_string(cpu, (int32_t)0x9fc01040, machine->bootstr);
+	store_string(cpu, (int32_t)0x9fc01200, machine->bootarg);
+
+	/*  a2 = pointer to environment strings  */
+	cpu->cd.mips.gpr[MIPS_GPR_A2] = (int32_t)0x9fc01800;
+	{
+		char tmps[50];
+		store_32bit_word(cpu, (int32_t)0x9fc01800, 0x9fc01900);
+		store_32bit_word(cpu, (int32_t)0x9fc01804, 0x9fc01a00);
+		store_32bit_word(cpu, (int32_t)0x9fc01808, 0);
+
+		snprintf(tmps, sizeof(tmps), "memsize=0x%08x",
+		    machine->physical_ram_in_mb * 1048576);
+		store_string(cpu, (int)0x9fc01900, tmps);
+		store_string(cpu, (int)0x9fc01a00,
+		    "ethaddr=10:20:30:30:20:10");
+	}
+}
+
+
+MACHINE_DEFAULT_CPU(algor)
+{
+	machine->cpu_name = strdup("RM5200");
+}
+
+
+MACHINE_REGISTER(algor)
+{
+	MR_DEFAULT(algor, "Algor evaluation board", MACHINE_ALGOR);
+
+	machine_entry_add_alias(me, "algor");
+
+	machine_entry_add_subtype(me, "P4032", MACHINE_ALGOR_P4032,
+	    "p4032", NULL);
+
+	machine_entry_add_subtype(me, "P5064", MACHINE_ALGOR_P5064,
+	    "p5064", NULL);
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_algor.cc gxemul-0.7.0+dfsg/src/machines/machine_algor.cc
--- gxemul-0.6.2/src/machines/machine_algor.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_algor.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,138 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Algorithmic P4032 and P5064 evaluation boards
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_isa.h"
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-MACHINE_SETUP(algor)
-{
-	struct pci_data *pci_bus;
-	char tmpstr[300];
-
-	machine->emulated_hz = 166560000;
-
-	switch (machine->machine_subtype) {
-	case MACHINE_ALGOR_P4032:
-		machine->machine_name = strdup("Algor P4032");
-		break;
-	case MACHINE_ALGOR_P5064:
-		machine->machine_name = strdup("Algor P5064");
-		break;
-	default:fatal("Unimplemented Algor machine.\n");
-		exit(1);
-	}
-
-	/*
-	 *  Algor CPU interrupts:
-	 *
-	 *  7 = CPU count/compare
-	 *  4 = Local
-	 *  3 = PCI
-	 *  2 = ISA
-	 */
-
-	pci_bus = (struct pci_data *) device_add(machine, "v3");
-
-	device_add(machine, "algor addr=0x1ff00000");
-
-	snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].v3",
-	    machine->path, machine->bootstrap_cpu);
-	bus_isa_init(machine, tmpstr, BUS_ISA_EXTERNAL_PIC | BUS_ISA_FDC,
-	    0x1d000000, 0x10000000);
-
-	/*  bus_pci_add(machine, pci_bus, machine->memory, 0, 0, 0,
-	    "dec21143");  */
-
-	if (!machine->prom_emulation)
-		return;
-
-	/*  NetBSD/algor wants these:  */
-
-	/*  a0 = argc  */
-	cpu->cd.mips.gpr[MIPS_GPR_A0] = 2;
-
-	/*  a1 = argv  */
-	cpu->cd.mips.gpr[MIPS_GPR_A1] = (int32_t)0x9fc01000;
-	store_32bit_word(cpu, (int32_t)0x9fc01000, 0x9fc01040);
-	store_32bit_word(cpu, (int32_t)0x9fc01004, 0x9fc01200);
-	store_32bit_word(cpu, (int32_t)0x9fc01008, 0);
-
-	machine->bootstr = strdup(machine->boot_kernel_filename);
-	machine->bootarg = strdup(machine->boot_string_argument);
-	store_string(cpu, (int32_t)0x9fc01040, machine->bootstr);
-	store_string(cpu, (int32_t)0x9fc01200, machine->bootarg);
-
-	/*  a2 = pointer to environment strings  */
-	cpu->cd.mips.gpr[MIPS_GPR_A2] = (int32_t)0x9fc01800;
-	{
-		char tmps[50];
-		store_32bit_word(cpu, (int32_t)0x9fc01800, 0x9fc01900);
-		store_32bit_word(cpu, (int32_t)0x9fc01804, 0x9fc01a00);
-		store_32bit_word(cpu, (int32_t)0x9fc01808, 0);
-
-		snprintf(tmps, sizeof(tmps), "memsize=0x%08x",
-		    machine->physical_ram_in_mb * 1048576);
-		store_string(cpu, (int)0x9fc01900, tmps);
-		store_string(cpu, (int)0x9fc01a00,
-		    "ethaddr=10:20:30:30:20:10");
-	}
-}
-
-
-MACHINE_DEFAULT_CPU(algor)
-{
-	machine->cpu_name = strdup("RM5200");
-}
-
-
-MACHINE_REGISTER(algor)
-{
-	MR_DEFAULT(algor, "Algor evaluation board", ARCH_MIPS, MACHINE_ALGOR);
-
-	machine_entry_add_alias(me, "algor");
-
-	machine_entry_add_subtype(me, "P4032", MACHINE_ALGOR_P4032,
-	    "p4032", NULL);
-
-	machine_entry_add_subtype(me, "P5064", MACHINE_ALGOR_P5064,
-	    "p5064", NULL);
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_alpha.c gxemul-0.7.0+dfsg/src/machines/machine_alpha.c
--- gxemul-0.6.2/src/machines/machine_alpha.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_alpha.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,256 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: DEC Alpha machines
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/alpha_autoconf.h"
+#include "thirdparty/alpha_rpb.h"
+
+
+MACHINE_SETUP(alpha)
+{
+	struct rpb rpb;
+	struct crb crb;
+	struct ctb ctb;
+	struct mddt mddt;
+	struct pcs *pcs = (struct pcs *) malloc(sizeof(struct pcs) * machine->ncpus);
+	int i;
+
+	switch (machine->machine_subtype) {
+
+	case ST_ALPHABOOK1:
+		machine->machine_name = strdup("AlphaBook 1");
+		if (machine->emulated_hz == 0)
+			machine->emulated_hz = 233000000;
+		device_add(machine, "lca");
+		break;
+
+	case ST_DEC_4100:
+		machine->machine_name = strdup("AlphaServer 4100");
+		break;
+
+	case ST_DEC_3000_300:
+		machine->machine_name = strdup("DEC 3000/300");
+		machine->main_console_handle = (size_t)device_add(machine,
+		    "z8530 addr=0x1b0200000 irq=0 addr_mult=4");
+		break;
+
+	case ST_EB164:
+		machine->machine_name = strdup("EB164");
+		break;
+
+	default:fatal("Unimplemented Alpha machine type %i\n",
+		    machine->machine_subtype);
+		exit(1);
+	}
+
+	if (!machine->prom_emulation)
+		return;
+
+	/*  These are used by NetBSD/alpha:  */
+	/*  a0 = First free Page Frame Number  */
+	/*  a1 = PFN of current Level 1 page table  */
+	/*  a2 = Bootinfo magic  */
+	/*  a3 = Bootinfo pointer  */
+	/*  a4 = Bootinfo version  */
+	cpu->cd.alpha.r[ALPHA_A0] = 16*1024*1024 / 8192;
+	cpu->cd.alpha.r[ALPHA_A1] = 0;	/*  TODO  */
+	cpu->cd.alpha.r[ALPHA_A2] = 0;	/*  Note: NOT ALPHA_BOOTINFO_MAGIC  */
+	cpu->cd.alpha.r[ALPHA_A3] = 0;	/*  TODO  */
+	cpu->cd.alpha.r[ALPHA_A4] = 1;
+
+	/*
+	 *  HWRPB: Hardware Restart Parameter Block
+	 *
+	 *  TODO: Almost everything.
+	 */
+	memset(&rpb, 0, sizeof(struct rpb));
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_phys), 0x14000);
+	strlcpy((char *)&(rpb.rpb_magic), "HWRPB", 8);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_version), HWRPB_DSRDB_MINVERS);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_size), sizeof(struct rpb));
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_page_size), 8192);
+	strlcpy((char *)&(rpb.rpb_ssn), "123456789", 10);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_type), machine->machine_subtype);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_cc_freq), machine->emulated_hz);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_intr_freq), 1024 << 12);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_pcs_cnt), machine->ncpus);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_pcs_size), sizeof(struct pcs));
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_pcs_off), PCS_ADDR - HWRPB_ADDR);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_ctb_off), CTB_ADDR - HWRPB_ADDR);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_crb_off), CRB_ADDR - HWRPB_ADDR);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(rpb.rpb_memdat_off), MEMDAT_ADDR - HWRPB_ADDR);
+
+	/*  CTB: Console Terminal Block  */
+	memset(&ctb, 0, sizeof(struct ctb));
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(ctb.ctb_term_type), machine->x11_md.in_use?
+	    CTB_GRAPHICS : CTB_PRINTERPORT);
+
+	/*  CRB: Console Routine Block  */
+	memset(&crb, 0, sizeof(struct crb));
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(crb.crb_v_dispatch), CRB_ADDR - 0x100);
+	store_64bit_word(cpu, CRB_ADDR - 0x100 + 8, PROM_ENTRY_PADDR);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(crb.crb_v_fixup), CRB_ADDR - 0x80);
+	store_64bit_word(cpu, CRB_ADDR - 0x80 + 8, PROM_ENTRY_PADDR + 0x800);
+
+	/*  PCS: Processor ID etc.  */
+	for (i=0; i<machine->ncpus; i++) {
+		memset(&pcs[i], 0, sizeof(struct pcs));
+		store_64bit_word_in_host(cpu, (unsigned char *)
+		    &(pcs[i].pcs_flags), PCS_RC | PCS_PA | PCS_PP |
+		    PCS_CV | PCS_PV | PCS_PMV | PCS_PL);
+		store_64bit_word_in_host(cpu, (unsigned char *)
+		    &(pcs[i].pcs_proc_type),
+		    machine->cpus[i]->cd.alpha.cpu_type.pcs_type);
+	}
+
+	/*
+	 *  MDDT: Memory Data Descriptor Table. For now, it is a simple
+	 *  two-entry table with half of the available RAM in each entry.
+	 *  (The values are in number of 8K pages.)
+	 *  The first 16 MB are not included (the kernel lives there).
+	 *  The last 1 MB is not included either, it is reserved for bootup
+	 *  and similar.
+	 */
+	memset(&mddt, 0, sizeof(struct mddt));
+	memset(&mddt.mddt_clusters[0], 0, sizeof(struct mddt_cluster));
+	memset(&mddt.mddt_clusters[1], 0, sizeof(struct mddt_cluster));
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(mddt.mddt_cluster_cnt), 2);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(mddt.mddt_clusters[0].mddt_pfn), 16 * 128);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(mddt.mddt_clusters[0].mddt_pg_cnt),
+	    (machine->physical_ram_in_mb/2 - 16) * 128);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(mddt.mddt_clusters[1].mddt_pfn),
+	    machine->physical_ram_in_mb/2 * 128);
+	store_64bit_word_in_host(cpu, (unsigned char *)
+	    &(mddt.mddt_clusters[1].mddt_pg_cnt),
+	    (machine->physical_ram_in_mb/2) * 128);
+
+	/*
+	 *  Place a special "hack" palcode call at PROM_ENTRY_PADDR and
+	 *  PROM_ENTRY_PADDR + 0x800:
+	 *  (Hopefully nothing else will be there.)
+	 */
+	store_32bit_word(cpu, PROM_ENTRY_PADDR, 0x3fffffe);
+	store_32bit_word(cpu, PROM_ENTRY_PADDR + 0x800, 0x3fffffd);
+
+	store_buf(cpu, HWRPB_ADDR, (char *)&rpb, sizeof(struct rpb));
+	store_buf(cpu, CTB_ADDR, (char *)&ctb, sizeof(struct ctb));
+	store_buf(cpu, CRB_ADDR, (char *)&crb, sizeof(struct crb));
+	store_buf(cpu, MEMDAT_ADDR, (char *)&mddt, sizeof(struct mddt));
+	store_buf(cpu, PCS_ADDR, (char *)pcs, sizeof(struct pcs) *
+	    machine->ncpus);
+
+	free(pcs);
+}
+
+
+MACHINE_DEFAULT_CPU(alpha)
+{
+	switch (machine->machine_subtype) {
+
+	case ST_ALPHABOOK1:
+		machine->cpu_name = strdup("21066");
+		break;
+
+	case ST_DEC_4100:
+		machine->cpu_name = strdup("21164A-2");
+		break;
+
+	case ST_DEC_3000_300:
+		machine->cpu_name = strdup("21064");
+		break;
+
+	case ST_EB164:
+		machine->cpu_name = strdup("21164PC");
+		break;
+
+	default:fatal("Unimplemented Alpha machine type %i\n",
+		    machine->machine_subtype);
+		exit(1);
+	}
+}
+
+
+MACHINE_DEFAULT_RAM(alpha)
+{
+	machine->physical_ram_in_mb = 128;
+}
+
+
+MACHINE_REGISTER(alpha)
+{
+	MR_DEFAULT(alpha, "Alpha", MACHINE_ALPHA);
+
+	machine_entry_add_alias(me, "alpha");
+
+	machine_entry_add_subtype(me, "AlphaBook 1", ST_ALPHABOOK1,
+	    "alphabook1", NULL);
+
+	machine_entry_add_subtype(me, "AlphaServer 4100", ST_DEC_4100,
+	    "alphaserver4100", NULL);
+
+	machine_entry_add_subtype(me, "DEC 3000/300", ST_DEC_3000_300,
+	    "3000/300", NULL);
+
+	machine_entry_add_subtype(me, "EB164", ST_EB164,
+	    "eb164", NULL);
+
+	me->set_default_ram = machine_default_ram_alpha;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_alpha.cc gxemul-0.7.0+dfsg/src/machines/machine_alpha.cc
--- gxemul-0.6.2/src/machines/machine_alpha.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_alpha.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,256 +0,0 @@
-/*
- *  Copyright (C) 2005-2011  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: DEC Alpha machines
- */
-
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/alpha_autoconf.h"
-#include "thirdparty/alpha_rpb.h"
-
-
-MACHINE_SETUP(alpha)
-{
-	struct rpb rpb;
-	struct crb crb;
-	struct ctb ctb;
-	struct mddt mddt;
-	struct pcs *pcs = (struct pcs *) malloc(sizeof(struct pcs) * machine->ncpus);
-	int i;
-
-	switch (machine->machine_subtype) {
-
-	case ST_ALPHABOOK1:
-		machine->machine_name = strdup("AlphaBook 1");
-		if (machine->emulated_hz == 0)
-			machine->emulated_hz = 233000000;
-		device_add(machine, "lca");
-		break;
-
-	case ST_DEC_4100:
-		machine->machine_name = strdup("AlphaServer 4100");
-		break;
-
-	case ST_DEC_3000_300:
-		machine->machine_name = strdup("DEC 3000/300");
-		machine->main_console_handle = (size_t)device_add(machine,
-		    "z8530 addr=0x1b0200000 irq=0 addr_mult=4");
-		break;
-
-	case ST_EB164:
-		machine->machine_name = strdup("EB164");
-		break;
-
-	default:fatal("Unimplemented Alpha machine type %i\n",
-		    machine->machine_subtype);
-		exit(1);
-	}
-
-	if (!machine->prom_emulation)
-		return;
-
-	/*  These are used by NetBSD/alpha:  */
-	/*  a0 = First free Page Frame Number  */
-	/*  a1 = PFN of current Level 1 page table  */
-	/*  a2 = Bootinfo magic  */
-	/*  a3 = Bootinfo pointer  */
-	/*  a4 = Bootinfo version  */
-	cpu->cd.alpha.r[ALPHA_A0] = 16*1024*1024 / 8192;
-	cpu->cd.alpha.r[ALPHA_A1] = 0;	/*  TODO  */
-	cpu->cd.alpha.r[ALPHA_A2] = 0;	/*  Note: NOT ALPHA_BOOTINFO_MAGIC  */
-	cpu->cd.alpha.r[ALPHA_A3] = 0;	/*  TODO  */
-	cpu->cd.alpha.r[ALPHA_A4] = 1;
-
-	/*
-	 *  HWRPB: Hardware Restart Parameter Block
-	 *
-	 *  TODO: Almost everything.
-	 */
-	memset(&rpb, 0, sizeof(struct rpb));
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_phys), 0x14000);
-	strlcpy((char *)&(rpb.rpb_magic), "HWRPB", 8);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_version), HWRPB_DSRDB_MINVERS);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_size), sizeof(struct rpb));
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_page_size), 8192);
-	strlcpy((char *)&(rpb.rpb_ssn), "123456789", 10);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_type), machine->machine_subtype);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_cc_freq), machine->emulated_hz);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_intr_freq), 1024 << 12);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_pcs_cnt), machine->ncpus);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_pcs_size), sizeof(struct pcs));
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_pcs_off), PCS_ADDR - HWRPB_ADDR);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_ctb_off), CTB_ADDR - HWRPB_ADDR);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_crb_off), CRB_ADDR - HWRPB_ADDR);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(rpb.rpb_memdat_off), MEMDAT_ADDR - HWRPB_ADDR);
-
-	/*  CTB: Console Terminal Block  */
-	memset(&ctb, 0, sizeof(struct ctb));
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(ctb.ctb_term_type), machine->x11_md.in_use?
-	    CTB_GRAPHICS : CTB_PRINTERPORT);
-
-	/*  CRB: Console Routine Block  */
-	memset(&crb, 0, sizeof(struct crb));
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(crb.crb_v_dispatch), CRB_ADDR - 0x100);
-	store_64bit_word(cpu, CRB_ADDR - 0x100 + 8, PROM_ENTRY_PADDR);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(crb.crb_v_fixup), CRB_ADDR - 0x80);
-	store_64bit_word(cpu, CRB_ADDR - 0x80 + 8, PROM_ENTRY_PADDR + 0x800);
-
-	/*  PCS: Processor ID etc.  */
-	for (i=0; i<machine->ncpus; i++) {
-		memset(&pcs[i], 0, sizeof(struct pcs));
-		store_64bit_word_in_host(cpu, (unsigned char *)
-		    &(pcs[i].pcs_flags), PCS_RC | PCS_PA | PCS_PP |
-		    PCS_CV | PCS_PV | PCS_PMV | PCS_PL);
-		store_64bit_word_in_host(cpu, (unsigned char *)
-		    &(pcs[i].pcs_proc_type),
-		    machine->cpus[i]->cd.alpha.cpu_type.pcs_type);
-	}
-
-	/*
-	 *  MDDT: Memory Data Descriptor Table. For now, it is a simple
-	 *  two-entry table with half of the available RAM in each entry.
-	 *  (The values are in number of 8K pages.)
-	 *  The first 16 MB are not included (the kernel lives there).
-	 *  The last 1 MB is not included either, it is reserved for bootup
-	 *  and similar.
-	 */
-	memset(&mddt, 0, sizeof(struct mddt));
-	memset(&mddt.mddt_clusters[0], 0, sizeof(struct mddt_cluster));
-	memset(&mddt.mddt_clusters[1], 0, sizeof(struct mddt_cluster));
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(mddt.mddt_cluster_cnt), 2);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(mddt.mddt_clusters[0].mddt_pfn), 16 * 128);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(mddt.mddt_clusters[0].mddt_pg_cnt),
-	    (machine->physical_ram_in_mb/2 - 16) * 128);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(mddt.mddt_clusters[1].mddt_pfn),
-	    machine->physical_ram_in_mb/2 * 128);
-	store_64bit_word_in_host(cpu, (unsigned char *)
-	    &(mddt.mddt_clusters[1].mddt_pg_cnt),
-	    (machine->physical_ram_in_mb/2) * 128);
-
-	/*
-	 *  Place a special "hack" palcode call at PROM_ENTRY_PADDR and
-	 *  PROM_ENTRY_PADDR + 0x800:
-	 *  (Hopefully nothing else will be there.)
-	 */
-	store_32bit_word(cpu, PROM_ENTRY_PADDR, 0x3fffffe);
-	store_32bit_word(cpu, PROM_ENTRY_PADDR + 0x800, 0x3fffffd);
-
-	store_buf(cpu, HWRPB_ADDR, (char *)&rpb, sizeof(struct rpb));
-	store_buf(cpu, CTB_ADDR, (char *)&ctb, sizeof(struct ctb));
-	store_buf(cpu, CRB_ADDR, (char *)&crb, sizeof(struct crb));
-	store_buf(cpu, MEMDAT_ADDR, (char *)&mddt, sizeof(struct mddt));
-	store_buf(cpu, PCS_ADDR, (char *)pcs, sizeof(struct pcs) *
-	    machine->ncpus);
-
-	free(pcs);
-}
-
-
-MACHINE_DEFAULT_CPU(alpha)
-{
-	switch (machine->machine_subtype) {
-
-	case ST_ALPHABOOK1:
-		machine->cpu_name = strdup("21066");
-		break;
-
-	case ST_DEC_4100:
-		machine->cpu_name = strdup("21164A-2");
-		break;
-
-	case ST_DEC_3000_300:
-		machine->cpu_name = strdup("21064");
-		break;
-
-	case ST_EB164:
-		machine->cpu_name = strdup("21164PC");
-		break;
-
-	default:fatal("Unimplemented Alpha machine type %i\n",
-		    machine->machine_subtype);
-		exit(1);
-	}
-}
-
-
-MACHINE_DEFAULT_RAM(alpha)
-{
-	machine->physical_ram_in_mb = 128;
-}
-
-
-MACHINE_REGISTER(alpha)
-{
-	MR_DEFAULT(alpha, "Alpha", ARCH_ALPHA, MACHINE_ALPHA);
-
-	machine_entry_add_alias(me, "alpha");
-
-	machine_entry_add_subtype(me, "AlphaBook 1", ST_ALPHABOOK1,
-	    "alphabook1", NULL);
-
-	machine_entry_add_subtype(me, "AlphaServer 4100", ST_DEC_4100,
-	    "alphaserver4100", NULL);
-
-	machine_entry_add_subtype(me, "DEC 3000/300", ST_DEC_3000_300,
-	    "3000/300", NULL);
-
-	machine_entry_add_subtype(me, "EB164", ST_EB164,
-	    "eb164", NULL);
-
-	me->set_default_ram = machine_default_ram_alpha;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_androidarm.c gxemul-0.7.0+dfsg/src/machines/machine_androidarm.c
--- gxemul-0.6.2/src/machines/machine_androidarm.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_androidarm.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,199 @@
+/*
+ *  Copyright (C) 2018-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: ARM-based "Android" machines
+ *
+ *  TODO. This is bogus so far, only enough to see the Linux kernel start
+ *  executing instructions.
+ *
+ *  gxemul -e sony-xperia-mini -tvvK boot.img 
+ *  gxemul -e finow-x5-air -tvvK boot.img 
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+uint32_t swap_if_little_endian(uint32_t v, struct cpu* cpu)
+{
+	if (cpu->byte_order == EMUL_BIG_ENDIAN)
+		return v;
+
+	return (v >> 24) | ((v & 0x00ff0000) >> 8)
+		| ((v & 0x0000ff00) << 8) | ((v & 0xff) << 24);
+}
+
+
+MACHINE_SETUP(androidarm)
+{
+	char tmpstr[1000];
+	int use_atags = 0;
+
+	cpu->byte_order = EMUL_LITTLE_ENDIAN;
+
+	switch (machine->machine_subtype) {
+
+	case MACHINE_ANDROIDARM_FINOWX5AIR:
+		machine->machine_name = strdup("Finow X5 Air");
+
+		// 2 GB ram at 0x80000000? Mirrored at 0 maybe? (But in GXemul's legacy
+		// framework, we have to make the mirror the other way around.)
+		dev_ram_init(machine, 0x80000000, 0x10000000, DEV_RAM_MIRROR, 0x0, NULL);
+		dev_ram_init(machine, 0x90000000, 0x70000000, DEV_RAM_RAM, 0x0, NULL);
+
+		// Yet another mirror at 0x40000000?
+		dev_ram_init(machine, 0x40000000, 0x10000000, DEV_RAM_MIRROR, 0x0, NULL);
+
+		// See https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/mt6580.dtsi
+		//	timer: timer@10008000
+		//	sysirq: interrupt-controller@10200100
+		//	gic: interrupt-controller@10211000
+		//	uart0: serial@11005000
+		//	uart1: serial@11006000
+
+		// "gic" interrupt controller:
+		// See https://github.com/torvalds/linux/blob/master/include/dt-bindings/interrupt-controller/arm-gic.h
+
+		// TODO: interrupt "GIC_SPI 44"
+		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].irq"
+		    " addr=0x11005000 addr_mult=4 in_use=%i",
+		    machine->path, machine->bootstrap_cpu, !machine->x11_md.in_use);
+		machine->main_console_handle = (size_t)
+		    device_add(machine, tmpstr);
+
+		dev_fb_init(machine, machine->memory,
+			0x12340000 /*  TODO addr  */, 
+			VFB_GENERIC,
+			400, 400,
+			400, 400,
+			24, machine->machine_name);
+
+		break;
+
+	case MACHINE_ANDROIDARM_SONYXPERIAMINI:
+		machine->machine_name = strdup("Sony Xperia Mini");
+
+		// Mirror at 0x40000000?
+		dev_ram_init(machine, 0x40000000, 0x20000000, DEV_RAM_MIRROR, 0x0, NULL);
+
+		// Perhaps https://talk.sonymobile.com/t5/Xperia-mini-pro/Sk17i-in-continous-boot-loop/td-p/281671#gref
+		// could be of some help.
+
+		dev_fb_init(machine, machine->memory,
+			0x23450000 /*  TODO addr  */, 
+			VFB_GENERIC,
+			320, 480,
+			320, 480,
+			24, machine->machine_name);
+
+		break;
+
+	default:printf("Unimplemented android-arm machine number.\n");
+		exit(1);
+	}
+
+	// See https://www.kernel.org/doc/Documentation/arm/Booting
+	cpu->cd.arm.r[0] = 0x00000000;
+	cpu->cd.arm.r[1] = 0xffffffff;	// architecture ID. 0xffffffff = use DT (device tree)?
+
+	if (use_atags) {
+		// ATAG list: TODO.
+		cpu->cd.arm.r[2] = 0x00002000;	// ATAGs at 8KB from start of low RAM.
+	} else {
+		// Device Tree:
+		// https://www.kernel.org/doc/Documentation/devicetree/booting-without-of.txt
+		cpu->cd.arm.r[2] = 0x08000000;	// Device Tree at 128 MB from start of RAM.
+		
+		store_32bit_word(cpu, cpu->cd.arm.r[2], swap_if_little_endian(0xd00dfeed, cpu));
+	}
+}
+
+
+MACHINE_DEFAULT_CPU(androidarm)
+{
+	switch (machine->machine_subtype) {
+
+	case MACHINE_ANDROIDARM_FINOWX5AIR:
+		// Cortex-A7?  MTK6580 at 1.3 GHz? Quadcore?
+		machine->cpu_name = strdup("CORTEX-A5");
+		break;
+
+	case MACHINE_ANDROIDARM_SONYXPERIAMINI:
+		// "Qualcomm MSM8255 Snapdragon S2"
+		// My real Xperia Mini says the following when booting the Linux kernel:
+		// [    0.000000] CPU: ARMv7 Processor [511f00f2] revision 2 (ARMv7), cr=10c53c7d
+		machine->cpu_name = strdup("SnapdragonS2");
+		break;
+
+	default:
+		machine->cpu_name = strdup("CORTEX-A5");
+	}
+}
+
+
+MACHINE_DEFAULT_RAM(androidarm)
+{
+	switch (machine->machine_subtype) {
+
+	case MACHINE_ANDROIDARM_FINOWX5AIR:
+		// Ram is at 0x80000000?
+		machine->physical_ram_in_mb = 256;
+		break;
+
+	case MACHINE_ANDROIDARM_SONYXPERIAMINI:
+		machine->physical_ram_in_mb = 512;
+		break;
+
+	default:
+		machine->physical_ram_in_mb = 512;
+	}
+}
+
+
+MACHINE_REGISTER(androidarm)
+{
+	MR_DEFAULT(androidarm, "ARM-based \"Android\" machines", MACHINE_ANDROIDARM);
+
+	machine_entry_add_alias(me, "android-arm");
+
+	machine_entry_add_subtype(me, "Finow X5 Air", MACHINE_ANDROIDARM_FINOWX5AIR,
+	    "finow-x5-air", NULL);
+
+	machine_entry_add_subtype(me, "Sony Xperia Mini", MACHINE_ANDROIDARM_SONYXPERIAMINI,
+	    "sony-xperia-mini", NULL);
+
+	me->set_default_ram = machine_default_ram_androidarm;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_androidarm.cc gxemul-0.7.0+dfsg/src/machines/machine_androidarm.cc
--- gxemul-0.6.2/src/machines/machine_androidarm.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_androidarm.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,199 +0,0 @@
-/*
- *  Copyright (C) 2018-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: ARM-based "Android" machines
- *
- *  TODO. This is bogus so far, only enough to see the Linux kernel start
- *  executing instructions.
- *
- *  gxemul -e sony-xperia-mini -tvvK boot.img 
- *  gxemul -e finow-x5-air -tvvK boot.img 
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-uint32_t swap_if_little_endian(uint32_t v, struct cpu* cpu)
-{
-	if (cpu->byte_order == EMUL_BIG_ENDIAN)
-		return v;
-
-	return (v >> 24) | ((v & 0x00ff0000) >> 8)
-		| ((v & 0x0000ff00) << 8) | ((v & 0xff) << 24);
-}
-
-
-MACHINE_SETUP(androidarm)
-{
-	char tmpstr[1000];
-	bool use_atags = false;
-
-	cpu->byte_order = EMUL_LITTLE_ENDIAN;
-
-	switch (machine->machine_subtype) {
-
-	case MACHINE_ANDROIDARM_FINOWX5AIR:
-		machine->machine_name = strdup("Finow X5 Air");
-
-		// 2 GB ram at 0x80000000? Mirrored at 0 maybe? (But in GXemul's legacy
-		// framework, we have to make the mirror the other way around.)
-		dev_ram_init(machine, 0x80000000, 0x10000000, DEV_RAM_MIRROR, 0x0);
-		dev_ram_init(machine, 0x90000000, 0x70000000, DEV_RAM_RAM, 0x0);
-
-		// Yet another mirror at 0x40000000?
-		dev_ram_init(machine, 0x40000000, 0x10000000, DEV_RAM_MIRROR, 0x0);
-
-		// See https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/mt6580.dtsi
-		//	timer: timer@10008000
-		//	sysirq: interrupt-controller@10200100
-		//	gic: interrupt-controller@10211000
-		//	uart0: serial@11005000
-		//	uart1: serial@11006000
-
-		// "gic" interrupt controller:
-		// See https://github.com/torvalds/linux/blob/master/include/dt-bindings/interrupt-controller/arm-gic.h
-
-		// TODO: interrupt "GIC_SPI 44"
-		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].irq"
-		    " addr=0x11005000 addr_mult=4 in_use=%i",
-		    machine->path, machine->bootstrap_cpu, !machine->x11_md.in_use);
-		machine->main_console_handle = (size_t)
-		    device_add(machine, tmpstr);
-
-		dev_fb_init(machine, machine->memory,
-			0x12340000 /*  TODO addr  */, 
-			VFB_GENERIC,
-			400, 400,
-			400, 400,
-			24, machine->machine_name);
-
-		break;
-
-	case MACHINE_ANDROIDARM_SONYXPERIAMINI:
-		machine->machine_name = strdup("Sony Xperia Mini");
-
-		// Mirror at 0x40000000?
-		dev_ram_init(machine, 0x40000000, 0x20000000, DEV_RAM_MIRROR, 0x0);
-
-		// Perhaps https://talk.sonymobile.com/t5/Xperia-mini-pro/Sk17i-in-continous-boot-loop/td-p/281671#gref
-		// could be of some help.
-
-		dev_fb_init(machine, machine->memory,
-			0x23450000 /*  TODO addr  */, 
-			VFB_GENERIC,
-			320, 480,
-			320, 480,
-			24, machine->machine_name);
-
-		break;
-
-	default:printf("Unimplemented android-arm machine number.\n");
-		exit(1);
-	}
-
-	// See https://www.kernel.org/doc/Documentation/arm/Booting
-	cpu->cd.arm.r[0] = 0x00000000;
-	cpu->cd.arm.r[1] = 0xffffffff;	// architecture ID. 0xffffffff = use DT (device tree)?
-
-	if (use_atags) {
-		// ATAG list: TODO.
-		cpu->cd.arm.r[2] = 0x00002000;	// ATAGs at 8KB from start of low RAM.
-	} else {
-		// Device Tree:
-		// https://www.kernel.org/doc/Documentation/devicetree/booting-without-of.txt
-		cpu->cd.arm.r[2] = 0x08000000;	// Device Tree at 128 MB from start of RAM.
-		
-		store_32bit_word(cpu, cpu->cd.arm.r[2], swap_if_little_endian(0xd00dfeed, cpu));
-	}
-}
-
-
-MACHINE_DEFAULT_CPU(androidarm)
-{
-	switch (machine->machine_subtype) {
-
-	case MACHINE_ANDROIDARM_FINOWX5AIR:
-		// Cortex-A7?  MTK6580 at 1.3 GHz? Quadcore?
-		machine->cpu_name = strdup("CORTEX-A5");
-		break;
-
-	case MACHINE_ANDROIDARM_SONYXPERIAMINI:
-		// "Qualcomm MSM8255 Snapdragon S2"
-		// My real Xperia Mini says the following when booting the Linux kernel:
-		// [    0.000000] CPU: ARMv7 Processor [511f00f2] revision 2 (ARMv7), cr=10c53c7d
-		machine->cpu_name = strdup("SnapdragonS2");
-		break;
-
-	default:
-		machine->cpu_name = strdup("CORTEX-A5");
-	}
-}
-
-
-MACHINE_DEFAULT_RAM(androidarm)
-{
-	switch (machine->machine_subtype) {
-
-	case MACHINE_ANDROIDARM_FINOWX5AIR:
-		// Ram is at 0x80000000?
-		machine->physical_ram_in_mb = 256;
-		break;
-
-	case MACHINE_ANDROIDARM_SONYXPERIAMINI:
-		machine->physical_ram_in_mb = 512;
-		break;
-
-	default:
-		machine->physical_ram_in_mb = 512;
-	}
-}
-
-
-MACHINE_REGISTER(androidarm)
-{
-	MR_DEFAULT(androidarm, "ARM-based \"Android\" machines", ARCH_ARM, MACHINE_ANDROIDARM);
-
-	machine_entry_add_alias(me, "android-arm");
-
-	machine_entry_add_subtype(me, "Finow X5 Air", MACHINE_ANDROIDARM_FINOWX5AIR,
-	    "finow-x5-air", NULL);
-
-	machine_entry_add_subtype(me, "Sony Xperia Mini", MACHINE_ANDROIDARM_SONYXPERIAMINI,
-	    "sony-xperia-mini", NULL);
-
-	me->set_default_ram = machine_default_ram_androidarm;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_arc.c gxemul-0.7.0+dfsg/src/machines/machine_arc.c
--- gxemul-0.6.2/src/machines/machine_arc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_arc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,263 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: ARC (Advanced RISC Computing) machines
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "arcbios.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#define	MACHINE_NAME_MAXBUF	100
+
+
+MACHINE_SETUP(arc)
+{
+	void *jazz_data;
+	struct memory *mem = machine->memory;
+	char tmpstr[1000];
+	char tmpstr2[1000];
+	int i, j;
+	const char *eaddr_string = "10:20:30:40:50:60";		/*  bogus  */
+	unsigned char macaddr[6];
+	char *machineName;
+
+	CHECK_ALLOCATION(machineName = (char *) malloc(MACHINE_NAME_MAXBUF));
+
+	cpu->byte_order = EMUL_LITTLE_ENDIAN;
+	snprintf(machineName, MACHINE_NAME_MAXBUF, "ARC");
+
+	machine->machine_name = machineName;
+
+	switch (machine->machine_subtype) {
+
+	case MACHINE_ARC_JAZZ_PICA:
+	case MACHINE_ARC_JAZZ_MAGNUM:
+		/*
+		 *  "PICA-61"
+		 *
+		 *  According to NetBSD 1.6.2:
+		 *
+		 *  jazzio0 at mainbus0
+		 *  timer0 at jazzio0 addr 0xe0000228
+		 *  mcclock0 at jazzio0 addr 0xe0004000: mc146818 or compatible
+		 *  lpt at jazzio0 addr 0xe0008000 intr 0 not configured
+		 *  fdc at jazzio0 addr 0xe0003000 intr 1 not configured
+		 *  MAGNUM at jazzio0 addr 0xe000c000 intr 2 not configured
+		 *  ALI_S3 at jazzio0 addr 0xe0800000 intr 3 not configured
+		 *  sn0 at jazzio0 addr 0xe0001000 intr 4: SONIC Ethernet
+		 *  sn0: Ethernet address 69:6a:6b:6c:00:00
+		 *  asc0 at jazzio0 addr 0xe0002000 intr 5: NCR53C94, target 0
+		 *  pckbd at jazzio0 addr 0xe0005000 intr 6 not configured
+		 *  pms at jazzio0 addr 0xe0005000 intr 7 not configured
+		 *  com0 at jazzio0 addr 0xe0006000 intr 8: ns16550a,
+		 *	working fifo
+		 *  com at jazzio0 addr 0xe0007000 intr 9 not configured
+		 *  jazzisabr0 at mainbus0
+		 *  isa0 at jazzisabr0 isa_io_base 0xe2000000 isa_mem_base
+		 *	0xe3000000
+		 *
+		 *  "Microsoft-Jazz", "MIPS Magnum"
+		 *
+		 *  timer0 at jazzio0 addr 0xe0000228
+		 *  mcclock0 at jazzio0 addr 0xe0004000: mc146818 or compatible
+		 *  lpt at jazzio0 addr 0xe0008000 intr 0 not configured
+		 *  fdc at jazzio0 addr 0xe0003000 intr 1 not configured
+		 *  MAGNUM at jazzio0 addr 0xe000c000 intr 2 not configured
+		 *  VXL at jazzio0 addr 0xe0800000 intr 3 not configured
+		 *  sn0 at jazzio0 addr 0xe0001000 intr 4: SONIC Ethernet
+		 *  sn0: Ethernet address 69:6a:6b:6c:00:00
+		 *  asc0 at jazzio0 addr 0xe0002000 intr 5: NCR53C94, target 0
+		 *  scsibus0 at asc0: 8 targets, 8 luns per target
+		 *  pckbd at jazzio0 addr 0xe0005000 intr 6 not configured
+		 *  pms at jazzio0 addr 0xe0005000 intr 7 not configured
+		 *  com0 at jazzio0 addr 0xe0006000 intr 8: ns16550a,
+		 *	working fifo
+		 *  com at jazzio0 addr 0xe0007000 intr 9 not configured
+		 *  jazzisabr0 at mainbus0
+		 *  isa0 at jazzisabr0 isa_io_base 0xe2000000 isa_mem_base
+		 *	0xe3000000
+		 */
+
+		switch (machine->machine_subtype) {
+		case MACHINE_ARC_JAZZ_PICA:
+			strlcat(machineName, " (Microsoft Jazz, Acer PICA-61)",
+			    MACHINE_NAME_MAXBUF);
+			break;
+		case MACHINE_ARC_JAZZ_MAGNUM:
+			strlcat(machineName, " (Microsoft Jazz, MIPS Magnum)",
+			    MACHINE_NAME_MAXBUF);
+			break;
+		default:
+			fatal("error in machine.c. jazz\n");
+			exit(1);
+		}
+
+		jazz_data = device_add(machine, "jazz addr=0x80000000");
+
+		/*  Keyboard IRQ is jazz.6, mouse is jazz.7  */
+		snprintf(tmpstr, sizeof(tmpstr),
+		    "%s.cpu[%i].jazz.6", machine->path,
+		    machine->bootstrap_cpu);
+		snprintf(tmpstr2, sizeof(tmpstr2),
+		    "%s.cpu[%i].jazz.7", machine->path,
+		    machine->bootstrap_cpu);
+		i = dev_pckbc_init(machine, mem, 0x80005000ULL,
+		    PCKBC_JAZZ, tmpstr, tmpstr2,
+		    machine->x11_md.in_use, 0);
+
+		/*  Serial controllers at JAZZ irq 8 and 9:  */
+		snprintf(tmpstr, sizeof(tmpstr),
+		    "ns16550 irq=%s.cpu[%i].jazz.8 addr=0x80006000"
+		    " in_use=%i name2=tty0", machine->path,
+		    machine->bootstrap_cpu, machine->x11_md.in_use? 0 : 1);
+		j = (size_t)device_add(machine, tmpstr);
+		snprintf(tmpstr, sizeof(tmpstr),
+		    "ns16550 irq=%s.cpu[%i].jazz.9 addr=0x80007000"
+		    " in_use=0 name2=tty1", machine->path,
+		    machine->bootstrap_cpu);
+		device_add(machine, tmpstr);
+
+		if (machine->x11_md.in_use)
+			machine->main_console_handle = i;
+		else
+			machine->main_console_handle = j;
+
+		switch (machine->machine_subtype) {
+		case MACHINE_ARC_JAZZ_PICA:
+			if (machine->x11_md.in_use) {
+				dev_vga_init(machine, mem, 0x400a0000ULL,
+				    0x600003c0ULL, machine->machine_name);
+				arcbios_console_init(machine,
+				    0x400b8000ULL, 0x600003c0ULL);
+			}
+			break;
+		case MACHINE_ARC_JAZZ_MAGNUM:
+			/*  PROM mirror?  */
+			dev_ram_init(machine, 0xfff00000, 0x100000,
+			    DEV_RAM_MIRROR | DEV_RAM_MIGHT_POINT_TO_DEVICES,
+			    0x1fc00000, NULL);
+
+			/*  VXL. TODO  */
+			/*  control at 0x60100000?  */
+			dev_fb_init(machine, mem, 0x60200000ULL,
+			    VFB_GENERIC, 1024,768, 1024,768, 8, "VXL");
+			break;
+		}
+
+		/*  SN at JAZZ irq 4  */
+		snprintf(tmpstr, sizeof(tmpstr),
+		    "sn addr=0x80001000 irq=%s.cpu[%i].jazz.4",
+		    machine->path, machine->bootstrap_cpu);
+		device_add(machine, tmpstr);
+
+		/*  ASC at JAZZ irq 5  */
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].jazz.5", 
+		    machine->path, machine->bootstrap_cpu);
+		dev_asc_init(machine, mem, 0x80002000ULL, tmpstr, NULL,
+		    DEV_ASC_PICA, dev_jazz_dma_controller, jazz_data);
+
+		/*  FDC at JAZZ irq 1  */
+		snprintf(tmpstr, sizeof(tmpstr),
+		    "fdc addr=0x80003000 irq=%s.cpu[%i].jazz.1",
+		    machine->path, machine->bootstrap_cpu);
+		device_add(machine, tmpstr);
+
+		/*  MC146818 at MIPS irq 2:  */
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2", 
+		    machine->path, machine->bootstrap_cpu);
+		dev_mc146818_init(machine, mem,
+		    0x80004000ULL, tmpstr, MC146818_ARC_JAZZ, 1);
+
+#if 0
+Not yet.
+		/*  WDC at ISA irq 14  */
+		device_add(machine, "wdc addr=0x900001f0, irq=38");
+#endif
+
+		break;
+
+	default:fatal("Unimplemented ARC machine type %i\n",
+		    machine->machine_subtype);
+		exit(1);
+	}
+
+	/*
+	 *  NOTE: ARCBIOS shouldn't be used before this point. (The only
+	 *  exception is that arcbios_console_init() may be called.)
+	 */
+
+	if (!machine->prom_emulation)
+		return;
+
+	arcbios_init(machine, 0, 0, eaddr_string, macaddr);
+}
+
+
+MACHINE_DEFAULT_CPU(arc)
+{
+	switch (machine->machine_subtype) {
+
+	case MACHINE_ARC_JAZZ_PICA:
+		CHECK_ALLOCATION(machine->cpu_name = strdup("R4000"));
+		break;
+
+	default:
+		CHECK_ALLOCATION(machine->cpu_name = strdup("R4400"));
+	}
+}
+
+
+MACHINE_DEFAULT_RAM(arc)
+{
+	machine->physical_ram_in_mb = 64;
+}
+
+
+MACHINE_REGISTER(arc)
+{
+	MR_DEFAULT(arc, "ARC", MACHINE_ARC);
+
+	me->set_default_ram = machine_default_ram_arc;
+
+	machine_entry_add_alias(me, "arc");
+
+	machine_entry_add_subtype(me, "Acer PICA-61", MACHINE_ARC_JAZZ_PICA,
+	    "pica-61", "acer pica", "pica", NULL);
+
+	machine_entry_add_subtype(me, "Jazz Magnum", MACHINE_ARC_JAZZ_MAGNUM,
+	    "magnum", "jazz magnum", NULL);
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_arc.cc gxemul-0.7.0+dfsg/src/machines/machine_arc.cc
--- gxemul-0.6.2/src/machines/machine_arc.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_arc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,263 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: ARC (Advanced RISC Computing) machines
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "arcbios.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#define	MACHINE_NAME_MAXBUF	100
-
-
-MACHINE_SETUP(arc)
-{
-	void *jazz_data;
-	struct memory *mem = machine->memory;
-	char tmpstr[1000];
-	char tmpstr2[1000];
-	int i, j;
-	const char *eaddr_string = "eaddr=10:20:30:40:50:60";		/*  bogus  */
-	unsigned char macaddr[6];
-	char *machineName;
-
-	CHECK_ALLOCATION(machineName = (char *) malloc(MACHINE_NAME_MAXBUF));
-
-	cpu->byte_order = EMUL_LITTLE_ENDIAN;
-	snprintf(machineName, MACHINE_NAME_MAXBUF, "ARC");
-
-	machine->machine_name = machineName;
-
-	switch (machine->machine_subtype) {
-
-	case MACHINE_ARC_JAZZ_PICA:
-	case MACHINE_ARC_JAZZ_MAGNUM:
-		/*
-		 *  "PICA-61"
-		 *
-		 *  According to NetBSD 1.6.2:
-		 *
-		 *  jazzio0 at mainbus0
-		 *  timer0 at jazzio0 addr 0xe0000228
-		 *  mcclock0 at jazzio0 addr 0xe0004000: mc146818 or compatible
-		 *  lpt at jazzio0 addr 0xe0008000 intr 0 not configured
-		 *  fdc at jazzio0 addr 0xe0003000 intr 1 not configured
-		 *  MAGNUM at jazzio0 addr 0xe000c000 intr 2 not configured
-		 *  ALI_S3 at jazzio0 addr 0xe0800000 intr 3 not configured
-		 *  sn0 at jazzio0 addr 0xe0001000 intr 4: SONIC Ethernet
-		 *  sn0: Ethernet address 69:6a:6b:6c:00:00
-		 *  asc0 at jazzio0 addr 0xe0002000 intr 5: NCR53C94, target 0
-		 *  pckbd at jazzio0 addr 0xe0005000 intr 6 not configured
-		 *  pms at jazzio0 addr 0xe0005000 intr 7 not configured
-		 *  com0 at jazzio0 addr 0xe0006000 intr 8: ns16550a,
-		 *	working fifo
-		 *  com at jazzio0 addr 0xe0007000 intr 9 not configured
-		 *  jazzisabr0 at mainbus0
-		 *  isa0 at jazzisabr0 isa_io_base 0xe2000000 isa_mem_base
-		 *	0xe3000000
-		 *
-		 *  "Microsoft-Jazz", "MIPS Magnum"
-		 *
-		 *  timer0 at jazzio0 addr 0xe0000228
-		 *  mcclock0 at jazzio0 addr 0xe0004000: mc146818 or compatible
-		 *  lpt at jazzio0 addr 0xe0008000 intr 0 not configured
-		 *  fdc at jazzio0 addr 0xe0003000 intr 1 not configured
-		 *  MAGNUM at jazzio0 addr 0xe000c000 intr 2 not configured
-		 *  VXL at jazzio0 addr 0xe0800000 intr 3 not configured
-		 *  sn0 at jazzio0 addr 0xe0001000 intr 4: SONIC Ethernet
-		 *  sn0: Ethernet address 69:6a:6b:6c:00:00
-		 *  asc0 at jazzio0 addr 0xe0002000 intr 5: NCR53C94, target 0
-		 *  scsibus0 at asc0: 8 targets, 8 luns per target
-		 *  pckbd at jazzio0 addr 0xe0005000 intr 6 not configured
-		 *  pms at jazzio0 addr 0xe0005000 intr 7 not configured
-		 *  com0 at jazzio0 addr 0xe0006000 intr 8: ns16550a,
-		 *	working fifo
-		 *  com at jazzio0 addr 0xe0007000 intr 9 not configured
-		 *  jazzisabr0 at mainbus0
-		 *  isa0 at jazzisabr0 isa_io_base 0xe2000000 isa_mem_base
-		 *	0xe3000000
-		 */
-
-		switch (machine->machine_subtype) {
-		case MACHINE_ARC_JAZZ_PICA:
-			strlcat(machineName, " (Microsoft Jazz, Acer PICA-61)",
-			    MACHINE_NAME_MAXBUF);
-			break;
-		case MACHINE_ARC_JAZZ_MAGNUM:
-			strlcat(machineName, " (Microsoft Jazz, MIPS Magnum)",
-			    MACHINE_NAME_MAXBUF);
-			break;
-		default:
-			fatal("error in machine.c. jazz\n");
-			exit(1);
-		}
-
-		jazz_data = device_add(machine, "jazz addr=0x80000000");
-
-		/*  Keyboard IRQ is jazz.6, mouse is jazz.7  */
-		snprintf(tmpstr, sizeof(tmpstr),
-		    "%s.cpu[%i].jazz.6", machine->path,
-		    machine->bootstrap_cpu);
-		snprintf(tmpstr2, sizeof(tmpstr2),
-		    "%s.cpu[%i].jazz.7", machine->path,
-		    machine->bootstrap_cpu);
-		i = dev_pckbc_init(machine, mem, 0x80005000ULL,
-		    PCKBC_JAZZ, tmpstr, tmpstr2,
-		    machine->x11_md.in_use, 0);
-
-		/*  Serial controllers at JAZZ irq 8 and 9:  */
-		snprintf(tmpstr, sizeof(tmpstr),
-		    "ns16550 irq=%s.cpu[%i].jazz.8 addr=0x80006000"
-		    " in_use=%i name2=tty0", machine->path,
-		    machine->bootstrap_cpu, machine->x11_md.in_use? 0 : 1);
-		j = (size_t)device_add(machine, tmpstr);
-		snprintf(tmpstr, sizeof(tmpstr),
-		    "ns16550 irq=%s.cpu[%i].jazz.9 addr=0x80007000"
-		    " in_use=0 name2=tty1", machine->path,
-		    machine->bootstrap_cpu);
-		device_add(machine, tmpstr);
-
-		if (machine->x11_md.in_use)
-			machine->main_console_handle = i;
-		else
-			machine->main_console_handle = j;
-
-		switch (machine->machine_subtype) {
-		case MACHINE_ARC_JAZZ_PICA:
-			if (machine->x11_md.in_use) {
-				dev_vga_init(machine, mem, 0x400a0000ULL,
-				    0x600003c0ULL, machine->machine_name);
-				arcbios_console_init(machine,
-				    0x400b8000ULL, 0x600003c0ULL);
-			}
-			break;
-		case MACHINE_ARC_JAZZ_MAGNUM:
-			/*  PROM mirror?  */
-			dev_ram_init(machine, 0xfff00000, 0x100000,
-			    DEV_RAM_MIRROR | DEV_RAM_MIGHT_POINT_TO_DEVICES,
-			    0x1fc00000);
-
-			/*  VXL. TODO  */
-			/*  control at 0x60100000?  */
-			dev_fb_init(machine, mem, 0x60200000ULL,
-			    VFB_GENERIC, 1024,768, 1024,768, 8, "VXL");
-			break;
-		}
-
-		/*  SN at JAZZ irq 4  */
-		snprintf(tmpstr, sizeof(tmpstr),
-		    "sn addr=0x80001000 irq=%s.cpu[%i].jazz.4",
-		    machine->path, machine->bootstrap_cpu);
-		device_add(machine, tmpstr);
-
-		/*  ASC at JAZZ irq 5  */
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].jazz.5", 
-		    machine->path, machine->bootstrap_cpu);
-		dev_asc_init(machine, mem, 0x80002000ULL, tmpstr, NULL,
-		    DEV_ASC_PICA, dev_jazz_dma_controller, jazz_data);
-
-		/*  FDC at JAZZ irq 1  */
-		snprintf(tmpstr, sizeof(tmpstr),
-		    "fdc addr=0x80003000 irq=%s.cpu[%i].jazz.1",
-		    machine->path, machine->bootstrap_cpu);
-		device_add(machine, tmpstr);
-
-		/*  MC146818 at MIPS irq 2:  */
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2", 
-		    machine->path, machine->bootstrap_cpu);
-		dev_mc146818_init(machine, mem,
-		    0x80004000ULL, tmpstr, MC146818_ARC_JAZZ, 1);
-
-#if 0
-Not yet.
-		/*  WDC at ISA irq 14  */
-		device_add(machine, "wdc addr=0x900001f0, irq=38");
-#endif
-
-		break;
-
-	default:fatal("Unimplemented ARC machine type %i\n",
-		    machine->machine_subtype);
-		exit(1);
-	}
-
-	/*
-	 *  NOTE: ARCBIOS shouldn't be used before this point. (The only
-	 *  exception is that arcbios_console_init() may be called.)
-	 */
-
-	if (!machine->prom_emulation)
-		return;
-
-	arcbios_init(machine, 0, 0, eaddr_string, macaddr);
-}
-
-
-MACHINE_DEFAULT_CPU(arc)
-{
-	switch (machine->machine_subtype) {
-
-	case MACHINE_ARC_JAZZ_PICA:
-		CHECK_ALLOCATION(machine->cpu_name = strdup("R4000"));
-		break;
-
-	default:
-		CHECK_ALLOCATION(machine->cpu_name = strdup("R4400"));
-	}
-}
-
-
-MACHINE_DEFAULT_RAM(arc)
-{
-	machine->physical_ram_in_mb = 64;
-}
-
-
-MACHINE_REGISTER(arc)
-{
-	MR_DEFAULT(arc, "ARC", ARCH_MIPS, MACHINE_ARC);
-
-	me->set_default_ram = machine_default_ram_arc;
-
-	machine_entry_add_alias(me, "arc");
-
-	machine_entry_add_subtype(me, "Acer PICA-61", MACHINE_ARC_JAZZ_PICA,
-	    "pica-61", "acer pica", "pica", NULL);
-
-	machine_entry_add_subtype(me, "Jazz Magnum", MACHINE_ARC_JAZZ_MAGNUM,
-	    "magnum", "jazz magnum", NULL);
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine.c gxemul-0.7.0+dfsg/src/machines/machine.c
--- gxemul-0.6.2/src/machines/machine.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,906 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Machine registry.
+ */
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <time.h>
+#include <unistd.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "diskimage.h"
+#include "emul.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "settings.h"
+#include "symbol.h"
+
+
+extern bool debugmsg_executing_noninteractively;
+extern bool single_step;
+
+/*  This is initialized by machine_init():  */
+struct machine_entry *first_machine_entry = NULL;
+
+
+/*
+ *  machine_new():
+ *
+ *  Returns a reasonably initialized struct machine.
+ */
+struct machine *machine_new(char *name, struct emul *emul, int id)
+{
+	struct machine *m;
+
+	CHECK_ALLOCATION(m = (struct machine *) malloc(sizeof(struct machine)));
+	memset(m, 0, sizeof(struct machine));
+
+	/*  Pointer back to the emul object that this machine belongs to:  */
+	m->emul = emul;
+
+	if (name != NULL)
+		CHECK_ALLOCATION(m->name = strdup(name));
+
+	/*  Full path, e.g. "machine[0]":  */
+	CHECK_ALLOCATION(m->path = (char *) malloc(20));
+	snprintf(m->path, 20, "machine[%i]", id);
+
+	/*  Sane default values:  */
+	m->serial_nr = 1;
+	m->machine_type = MACHINE_NONE;
+	m->machine_subtype = MACHINE_NONE;
+	m->arch_pagesize = 4096;	/*  Should be overriden in
+					    emul.c for other pagesizes.  */
+	m->prom_emulation = 1;
+	m->allow_instruction_combinations = 1;
+	m->byte_order_override = NO_BYTE_ORDER_OVERRIDE;
+	m->boot_kernel_filename = strdup("");
+	m->boot_string_argument = NULL;
+	m->x11_md.scaledown = 1;
+	m->x11_md.scaleup = 1;
+	m->n_gfx_cards = 1;
+	symbol_init(&m->symbol_context);
+
+	/*  Settings:  */
+	m->settings = settings_new();
+	settings_add(m->settings, "name", 0,
+	    SETTINGS_TYPE_STRING, SETTINGS_FORMAT_STRING,
+	    (void *) &m->name);
+	settings_add(m->settings, "serial_nr", 0,
+	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_DECIMAL,
+	    (void *) &m->serial_nr);
+	settings_add(m->settings, "arch_pagesize", 0,
+	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_DECIMAL,
+	    (void *) &m->arch_pagesize);
+	settings_add(m->settings, "prom_emulation", 0,
+	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO,
+	    (void *) &m->prom_emulation);
+	settings_add(m->settings, "allow_instruction_combinations", 0,
+	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO,
+	    (void *) &m->allow_instruction_combinations);
+	settings_add(m->settings, "n_gfx_cards", 0,
+	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_DECIMAL,
+	    (void *) &m->n_gfx_cards);
+	settings_add(m->settings, "statistics_enabled", 1,
+	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO,
+	    (void *) &m->statistics.enabled);
+
+	return m;
+}
+
+
+/*
+ *  machine_destroy():
+ *
+ *  Destroys a machine object.
+ */
+void machine_destroy(struct machine *machine)
+{
+	int i;
+
+	for (i=0; i<machine->ncpus; i++)
+		cpu_destroy(machine->cpus[i]);
+
+	if (machine->name != NULL)
+	 	free(machine->name);
+
+	if (machine->path != NULL)
+		free(machine->path);
+
+	/*  Remove any remaining level-1 settings:  */
+	settings_remove_all(machine->settings);
+	settings_destroy(machine->settings);
+
+	free(machine);
+}
+
+
+/*
+ *  machine_name_to_type():
+ *
+ *  Take a type and a subtype as strings, and convert them into numeric
+ *  values used internally throughout the code.
+ *
+ *  Return value is 1 on success, 0 if there was no match.
+ *  Also, any errors/warnings are printed using fatal()/debug().
+ */
+int machine_name_to_type(char *stype, char *ssubtype,
+	int *type, int *subtype)
+{
+	struct machine_entry *me;
+	int i, j, k, nmatches = 0;
+
+	*type = MACHINE_NONE;
+	*subtype = 0;
+
+	/*  Check stype, and optionally ssubtype:  */
+	me = first_machine_entry;
+	while (me != NULL) {
+		for (i=0; i<me->n_aliases; i++)
+			if (strcasecmp(me->aliases[i], stype) == 0) {
+				/*  Found a type:  */
+				*type = me->machine_type;
+
+				if (me->n_subtypes == 0)
+					return 1;
+
+				/*  Check for subtype:  */
+				for (j=0; j<me->n_subtypes; j++)
+					for (k=0; k<me->subtype[j]->n_aliases;
+					    k++)
+						if (strcasecmp(ssubtype,
+						    me->subtype[j]->aliases[k]
+						    ) == 0) {
+							*subtype = me->subtype[
+							    j]->machine_subtype;
+							return 1;
+						}
+
+				fatal("Unknown subtype '%s' for emulation"
+				    " '%s'\n", ssubtype, stype);
+				if (!ssubtype[0])
+					fatal("(Maybe you forgot the -e"
+					    " command line option?)\n");
+				exit(1);
+			}
+
+		me = me->next;
+	}
+
+	/*  Not found? Then just check ssubtype:  */
+	me = first_machine_entry;
+	while (me != NULL) {
+		if (me->n_subtypes == 0) {
+			me = me->next;
+			continue;
+		}
+
+		/*  Check for subtype:  */
+		for (j=0; j<me->n_subtypes; j++)
+			for (k=0; k<me->subtype[j]->n_aliases; k++)
+				if (strcasecmp(ssubtype, me->subtype[j]->
+				    aliases[k]) == 0) {
+					*type = me->machine_type;
+					*subtype = me->subtype[j]->machine_subtype;
+					nmatches ++;
+				}
+
+		me = me->next;
+	}
+
+	switch (nmatches) {
+	case 0:	fatal("\nSorry, emulation \"%s\"", stype);
+		if (ssubtype != NULL && ssubtype[0] != '\0')
+			fatal(" (subtype \"%s\")", ssubtype);
+		fatal(" is unknown.\n");
+		break;
+	case 1:	return 1;
+	default:fatal("\nSorry, multiple matches for \"%s\"", stype);
+		if (ssubtype != NULL && ssubtype[0] != '\0')
+			fatal(" (subtype \"%s\")", ssubtype);
+		fatal(".\n");
+	}
+
+	*type = MACHINE_NONE;
+	*subtype = 0;
+
+	fatal("Use the -H command line option to get a list of "
+	    "available types and subtypes.\n\n");
+
+	return 0;
+}
+
+
+/*
+ *  machine_add_breakpoint_string():
+ *
+ *  Add a breakpoint string to the machine. Later (in emul.c) these will be
+ *  converted to actual breakpoints.
+ */
+void machine_add_breakpoint_string(struct machine *machine, char *str)
+{
+	int n = machine->breakpoints.n + 1;
+
+	CHECK_ALLOCATION(machine->breakpoints.string = (char **)
+	    realloc(machine->breakpoints.string, n * sizeof(char *)));
+	CHECK_ALLOCATION(machine->breakpoints.addr = (uint64_t *)
+	    realloc(machine->breakpoints.addr, n * sizeof(uint64_t)));
+	CHECK_ALLOCATION(machine->breakpoints.string[machine->breakpoints.n] =
+	    strdup(optarg));
+
+	machine->breakpoints.addr[machine->breakpoints.n] = 0;
+	machine->breakpoints.n ++;
+}
+
+
+/*
+ *  machine_add_tickfunction():
+ *
+ *  Adds a tick function (a function called every now and then, depending on
+ *  clock cycle count) to a machine.
+ *
+ *  If tickshift is non-zero, a tick will occur every (1 << tickshift) cycles.
+ *  This is used for the normal (fast dyntrans) emulation modes.
+ *
+ *  If tickshift is zero, then this is a cycle-accurate tick function.
+ *  The hz value is used in this case.
+ */
+void machine_add_tickfunction(struct machine *machine, void (*func)
+	(struct cpu *, void *), void *extra, int tickshift)
+{
+	int n = machine->tick_functions.n_entries;
+
+	CHECK_ALLOCATION(machine->tick_functions.ticks_till_next = (int *) realloc(
+	    machine->tick_functions.ticks_till_next, (n+1) * sizeof(int)));
+	CHECK_ALLOCATION(machine->tick_functions.ticks_reset_value = (int *) realloc(
+	    machine->tick_functions.ticks_reset_value, (n+1) * sizeof(int)));
+	CHECK_ALLOCATION(machine->tick_functions.f = (void (**)(struct cpu*,void*)) realloc(
+	    machine->tick_functions.f, (n+1) * sizeof(void *)));
+	CHECK_ALLOCATION(machine->tick_functions.extra = (void **) realloc(
+	    machine->tick_functions.extra, (n+1) * sizeof(void *)));
+
+	/*
+	 *  The dyntrans subsystem wants to run code in relatively
+	 *  large chunks without checking for external interrupts;
+	 *  too low tickshifts are not allowed.
+	 */
+	if (tickshift < N_SAFE_DYNTRANS_LIMIT_SHIFT) {
+		fatal("ERROR! tickshift = %i, less than "
+		    "N_SAFE_DYNTRANS_LIMIT_SHIFT (%i)\n",
+		    tickshift, N_SAFE_DYNTRANS_LIMIT_SHIFT);
+		exit(1);
+	}
+
+	machine->tick_functions.ticks_till_next[n]   = 0;
+	machine->tick_functions.ticks_reset_value[n] = 1 << tickshift;
+	machine->tick_functions.f[n]                 = func;
+	machine->tick_functions.extra[n]             = extra;
+
+	machine->tick_functions.n_entries = n + 1;
+}
+
+
+/*
+ *  machine_statistics_init():
+ *
+ *  Initialize the parts of a machine struct that deal with instruction
+ *  statistics gathering.
+ *
+ *  Note: The fname argument contains "flags:filename".
+ */
+void machine_statistics_init(struct machine *machine, char *fname)
+{
+	int n_fields = 0;
+	char *pcolon = fname;
+	const char *mode = "a";	/*  Append by default  */
+
+	machine->allow_instruction_combinations = 0;
+
+	if (machine->statistics.fields != NULL) {
+		fprintf(stderr, "Only one -s option is allowed.\n");
+		exit(1);
+	}
+
+	machine->statistics.enabled = 1;
+	CHECK_ALLOCATION(machine->statistics.fields = (char *) malloc(1));
+	machine->statistics.fields[0] = '\0';
+
+	while (*pcolon && *pcolon != ':')
+		pcolon ++;
+
+	if (*pcolon != ':') {
+		fprintf(stderr, "The syntax for the -s option is:    "
+		    "-s flags:filename\nYou omitted the flags. Run g"
+		    "xemul -h for a list of available flags.\n");
+		exit(1);
+	}
+
+	while (*fname != ':') {
+		switch (*fname) {
+
+		/*  Type flags:  */
+		case 'v':
+		case 'i':
+		case 'p':
+			CHECK_ALLOCATION(machine->statistics.fields = (char *) realloc(
+			    machine->statistics.fields, strlen(
+			    machine->statistics.fields) + 2));
+			machine->statistics.fields[n_fields ++] = *fname;
+			machine->statistics.fields[n_fields] = '\0';
+			break;
+
+		/*  Optional flags:  */
+		case 'o':
+			mode = "w";
+			break;
+		case 'd':
+			machine->statistics.enabled = 0;
+			break;
+
+		default:fprintf(stderr, "Unknown flag '%c' used with the"
+			    " -s option. Aborting.\n", *fname);
+			exit(1);
+		}
+		fname ++;
+	}
+
+	fname ++;	/*  point to the filename after the colon  */
+
+	CHECK_ALLOCATION(machine->statistics.filename = strdup(fname));
+	machine->statistics.file = fopen(machine->statistics.filename, mode);
+}
+
+
+/*
+ *  machine_dumpinfo():
+ *
+ *  Dumps info about a machine in some kind of readable format. (Used by
+ *  the 'machine' debugger command.)
+ */
+void machine_dumpinfo(struct machine *m)
+{
+	int i;
+
+	debug("serial nr: %i", m->serial_nr);
+	if (m->nr_of_nics > 0)
+		debug("  (nr of NICs: %i)", m->nr_of_nics);
+	debug("\n");
+
+	char meminfo[2000];
+	snprintf(meminfo, sizeof(meminfo), "%i MB", m->physical_ram_in_mb);
+
+	if (m->memory_offset_in_mb != 0)
+		snprintf(meminfo + strlen(meminfo), sizeof(meminfo) - strlen(meminfo),
+		    " (offset by %i MB)", m->memory_offset_in_mb);
+	if (m->random_mem_contents)
+		snprintf(meminfo + strlen(meminfo), sizeof(meminfo) - strlen(meminfo),
+		    ", randomized content");
+
+	debugmsg(SUBSYS_MACHINE, "memory", VERBOSITY_INFO, "%s", meminfo);
+
+	if (!m->prom_emulation)
+		debug("PROM emulation disabled\n");
+
+	for (i=0; i<m->ncpus; i++)
+		cpu_dumpinfo(m, m->cpus[i], true);
+
+	if (m->ncpus > 1)
+		debug("Bootstrap cpu is nr %i\n", m->bootstrap_cpu);
+
+	if (m->x11_md.in_use) {
+		debug("Using X11");
+		if (m->x11_md.scaledown > 1)
+			debug(", scaledown %i", m->x11_md.scaledown);
+		if (m->x11_md.scaleup > 1)
+			debug(", scaleup %i", m->x11_md.scaleup);
+		if (m->x11_md.n_display_names > 0) {
+			for (i=0; i<m->x11_md.n_display_names; i++) {
+				debug(i? ", " : " (");
+				debug("\"%s\"", m->x11_md.display_names[i]);
+			}
+			debug(")");
+		}
+		debug("\n");
+	}
+
+	diskimage_dump_info(m);
+
+	if (m->force_netboot)
+		debug("Forced netboot\n");
+}
+
+
+/*
+ *  machine_setup():
+ *
+ *  This function initializes memory, registers, and/or devices
+ *  required by specific machine emulations.
+ */
+void machine_setup(struct machine *machine)
+{
+	struct machine_entry *me;
+	struct cpu *cpu = machine->cpus[machine->bootstrap_cpu];
+
+	machine->bootdev_id = diskimage_bootdev(machine, &machine->bootdev_type);
+	machine->machine_name = NULL;
+
+	/*  TODO: Move this somewhere else?  */
+	if (machine->boot_string_argument == NULL) {
+		switch (machine->machine_type) {
+		case MACHINE_ARC:
+			machine->boot_string_argument = strdup("-aN");
+			break;
+		case MACHINE_CATS:
+			machine->boot_string_argument = strdup("-A");
+			break;
+		case MACHINE_PMAX:
+			machine->boot_string_argument = strdup("-a");
+			break;
+		default:
+			/*  Important, because boot_string_argument should
+			    not be set to NULL:  */
+			machine->boot_string_argument = strdup("");
+		}
+	}
+
+	me = first_machine_entry;
+	while (me != NULL) {
+		if (machine->machine_type == me->machine_type &&
+		    me->setup != NULL) {
+			me->setup(machine, cpu);
+			break;
+		}
+
+		me = me->next;
+	}
+
+	if (me == NULL) {
+		fatal("Unknown emulation type %i\n", machine->machine_type);
+		exit(1);
+	}
+
+	switch (cpu->cpu_family->arch) {
+	case ARCH_MIPS:
+		// Register devices at the "typical" kseg1 base:
+		// 0xffffffff80000000 (kseg0) could work too but it is more
+		// likely that devices are accessed using their uncached address.
+		// TODO: How about "high" mapping for 64-bit systems?
+		machine_add_devices_as_symbols(machine, 0xffffffffa0000000);
+		break;
+	}
+	
+	if (machine->machine_name != NULL)
+		debugmsg(SUBSYS_MACHINE, "model", VERBOSITY_INFO, "%s", machine->machine_name);
+
+	if (machine->emulated_hz > 0)
+		debugmsg(SUBSYS_MACHINE, "clock speed", VERBOSITY_INFO,
+		    "%.2f MHz", (float)machine->emulated_hz / 1000000);
+
+	if (machine->bootstr != NULL && machine->bootstr[0]) {
+		bool has_bootarg = machine->bootarg != NULL && machine->bootarg[0];
+		debugmsg(SUBSYS_MACHINE,
+		    has_bootarg ? "bootstring & bootarg" : "bootstring",
+		    VERBOSITY_INFO,
+		    "%s %s",
+		    machine->bootstr,
+		    has_bootarg ? machine->bootarg : "");
+	}
+}
+
+
+/*
+ *  machine_add_devices_as_symbols():
+ *
+ *  Registers device addresses as symbols, to make the debugging experience
+ *  somewhat nicer. offset should be e.g. 0xffffffff80000000 and
+ *  0xffffffffa0000000 on MIPS.
+ */
+void machine_add_devices_as_symbols(struct machine *machine, uint64_t offset)
+{
+	struct memory* mem = machine->cpus[machine->bootstrap_cpu]->mem;
+	int i;
+
+	for (i = 0; i < mem->n_mmapped_devices; ++i) {
+		char name[1000];
+
+		// Hm. Perhaps adding all "ram" devices looks too cluttered.
+		// if (strcmp(mem->devices[i].name, "ram") == 0)
+		//	continue;
+
+		snprintf(name, sizeof(name),
+		    "(%s@0x%llx)", mem->devices[i].name,
+		    (long long)mem->devices[i].baseaddr);
+
+		add_symbol_name(
+		    &machine->symbol_context,
+		    mem->devices[i].baseaddr + offset,
+		    mem->devices[i].length,
+		    name,
+		    0,
+		    0);
+	}
+}
+
+
+/*
+ *  machine_memsize_fix():
+ *
+ *  Sets physical_ram_in_mb (if not already set), and memory_offset_in_mb,
+ *  depending on machine type.
+ */
+void machine_memsize_fix(struct machine *m)
+{
+	if (m == NULL) {
+		fatal("machine_defaultmemsize(): m == NULL?\n");
+		exit(1);
+	}
+
+	if (m->physical_ram_in_mb == 0) {
+		struct machine_entry *me = first_machine_entry;
+		while (me != NULL) {
+			if (m->machine_type == me->machine_type &&
+			    me->set_default_ram != NULL) {
+				me->set_default_ram(m);
+				break;
+			}
+			me = me->next;
+		}
+	}
+
+	/*  Special SGI memory offsets:  (TODO: move this somewhere else)  */
+	if (m->machine_type == MACHINE_SGI) {
+		switch (m->machine_subtype) {
+		case 20:
+		case 22:
+		case 24:
+		case 26:
+			m->memory_offset_in_mb = 128;
+			break;
+		case 28:
+		case 30:
+			m->memory_offset_in_mb = 512;
+			break;
+		}
+	}
+
+	if (m->physical_ram_in_mb == 0)
+		m->physical_ram_in_mb = DEFAULT_RAM_IN_MB;
+}
+
+
+/*
+ *  machine_default_cputype():
+ *
+ *  Sets m->cpu_name, if it isn't already set, depending on the machine type.
+ */
+void machine_default_cputype(struct machine *m)
+{
+	struct machine_entry *me;
+
+	if (m == NULL) {
+		fatal("machine_default_cputype(): m == NULL?\n");
+		exit(1);
+	}
+
+	/*  Already set? Then return.  */
+	if (m->cpu_name != NULL)
+		return;
+
+	me = first_machine_entry;
+	while (me != NULL) {
+		if (m->machine_type == me->machine_type &&
+		    me->set_default_cpu != NULL) {
+			me->set_default_cpu(m);
+			break;
+		}
+		me = me->next;
+	}
+
+	if (m->cpu_name == NULL) {
+		fprintf(stderr, "machine_default_cputype(): no default"
+		    " cpu for machine type %i subtype %i\n",
+		    m->machine_type, m->machine_subtype);
+		exit(1);
+	}
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  machine_run():
+ *
+ *  Run one or more instructions on all CPUs in this machine. (Usually,
+ *  around N_SAFE_DYNTRANS_LIMIT instructions will be run by the dyntrans
+ *  system.)
+ *
+ *  Return value is true if any CPU in this machine is still running,
+ *  false if all CPUs are stopped.
+ */
+bool machine_run(struct machine *machine)
+{
+	struct cpu **cpus = machine->cpus;
+	int ncpus = machine->ncpus;
+	bool any_running = false;
+
+	for (int i=0; i<ncpus; i++) {
+		if (cpus[i]->running) {
+			any_running = true;
+			cpus[i]->run_instr(cpus[i]);
+		}
+	}
+
+	if (!any_running)
+		return false;
+
+	/*
+	 *  Hardware 'ticks':  (clocks, interrupt sources...)
+	 *
+	 *  This assumes that the CPUs ran approximately N_SAFE_DYNTRANS_LIMIT
+	 *  instructions (or "ticks") in the core dyntrans loop.
+	 *
+	 *  TODO: This should be redesigned into some "mainbus" stuff instead!
+	 */
+
+	for (int te=0; te<machine->tick_functions.n_entries; te++) {
+		machine->tick_functions.ticks_till_next[te] -=
+		    single_step ? 1 : N_SAFE_DYNTRANS_LIMIT;
+
+		if (machine->tick_functions.ticks_till_next[te] <= 0) {
+			while (machine->tick_functions.ticks_till_next[te]<=0) {
+				machine->tick_functions.ticks_till_next[te] +=
+				    machine->tick_functions.ticks_reset_value[te];
+
+				machine->tick_functions.f[te](cpus[0],
+			    	    machine->tick_functions.extra[te]);
+			}
+		}
+	}
+
+	/*  Is any CPU still alive?  */
+	for (int i=0; i<ncpus; i++)
+		if (cpus[i]->running)
+			return true;
+
+	return false;
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  machine_entry_new():
+ *
+ *  This function creates a new machine_entry struct, and fills it with some
+ *  valid data; it is up to the caller to add additional data that weren't
+ *  passed as arguments to this function, such as alias names and machine
+ *  subtypes.
+ */
+struct machine_entry *machine_entry_new(const char *name, int oldstyle_type)
+{
+	struct machine_entry *me;
+
+	CHECK_ALLOCATION(me = (struct machine_entry *) malloc(sizeof(struct machine_entry)));
+	memset(me, 0, sizeof(struct machine_entry));
+
+	me->name = name;
+	me->machine_type = oldstyle_type;
+	me->n_aliases = 0;
+	me->aliases = NULL;
+	me->n_subtypes = 0;
+	me->setup = NULL;
+
+	return me;
+}
+
+
+/*
+ *  machine_entry_add_alias():
+ *
+ *  This function adds an "alias" to a machine entry.
+ */
+void machine_entry_add_alias(struct machine_entry *me, const char *name)
+{
+	me->n_aliases ++;
+
+	CHECK_ALLOCATION(me->aliases = (char **) realloc(me->aliases,
+	    sizeof(char *) * me->n_aliases));
+
+	me->aliases[me->n_aliases - 1] = strdup(name);
+}
+
+
+/*
+ *  machine_entry_add_subtype():
+ *
+ *  This function adds a subtype to a machine entry. The argument list after
+ *  oldstyle_subtype is a list of one or more char *, followed by NULL. E.g.:
+ *
+ *	machine_entry_add_subtype(me, "Machine X", MACHINE_X,
+ *	    "machine-x", "x", NULL);
+ */
+void machine_entry_add_subtype(struct machine_entry *me, const char *name,
+	int oldstyle_subtype, ...)
+{
+	va_list argp;
+	struct machine_entry_subtype *mes;
+
+	/*  Allocate a new subtype struct:  */
+	CHECK_ALLOCATION(mes = (struct machine_entry_subtype *)
+	    malloc(sizeof(struct machine_entry_subtype)));
+
+	/*  Add the subtype to the machine entry:  */
+	me->n_subtypes ++;
+	CHECK_ALLOCATION(me->subtype = (struct
+	    machine_entry_subtype **) realloc(me->subtype, sizeof(struct
+	    machine_entry_subtype *) * me->n_subtypes));
+	me->subtype[me->n_subtypes - 1] = mes;
+
+	/*  Fill the struct with subtype data:  */
+	memset(mes, 0, sizeof(struct machine_entry_subtype));
+	mes->name = name;
+	mes->machine_subtype = oldstyle_subtype;
+
+	/*  ... and all aliases:  */
+	mes->n_aliases = 0;
+	mes->aliases = NULL;
+
+	va_start(argp, oldstyle_subtype);
+
+	for (;;) {
+		char *s = va_arg(argp, char *);
+		if (s == NULL)
+			break;
+
+		mes->n_aliases ++;
+		CHECK_ALLOCATION(mes->aliases = (char **)
+		    realloc(mes->aliases, sizeof(char *) * mes->n_aliases));
+
+		mes->aliases[mes->n_aliases - 1] = s;
+	}
+
+	va_end(argp);
+}
+
+
+/*
+ *  machine_entry_register():
+ *
+ *  Inserts a new machine_entry into the machine entries list.
+ */
+void machine_entry_register(struct machine_entry *me)
+{
+	struct machine_entry *prev, *next;
+
+	prev = NULL;
+	next = first_machine_entry;
+
+	for (;;) {
+		if (next == NULL)
+			break;
+		if (strcasecmp(me->name, next->name) < 0)
+			break;
+
+		prev = next;
+		next = next->next;
+	}
+
+	if (prev != NULL)
+		prev->next = me;
+	else
+		first_machine_entry = me;
+	me->next = next;
+}
+
+
+/*
+ *  machine_list_available_types_and_cpus():
+ *
+ *  List all available machine types (for example when running the emulator
+ *  with just -H as command line argument).
+ */
+void machine_list_available_types_and_cpus(void)
+{
+	struct machine_entry *me;
+	int iadd = 2;
+
+	debug("Available CPU types:\n\n");
+
+	debug_indentation(iadd);
+	cpu_list_available_types();
+	debug_indentation(-iadd);  
+
+	debug("\nMost of the CPU types are bogus, and not really implemented."
+	    " The main effect of\nselecting a specific CPU type is to choose "
+	    "what kind of 'id' it will have.\n\nAvailable machine types (with "
+	    "aliases) and their subtypes:\n\n");
+
+	debug_indentation(iadd);
+	me = first_machine_entry;
+
+	if (me == NULL)
+		fatal("No machines defined!\n");
+
+	while (me != NULL) {
+		int i, j, iadd2 = 1;
+
+		debug("%s (", me->name);
+		for (i=0; i<me->n_aliases; i++)
+			debug("%s\"%s\"", i? ", " : "", me->aliases[i]);
+		debug(")\n");
+
+		debug_indentation(iadd2);
+		for (i=0; i<me->n_subtypes; i++) {
+			struct machine_entry_subtype *mes;
+			mes = me->subtype[i];
+			debug("- %s", mes->name);
+			debug(" (");
+			for (j=0; j<mes->n_aliases; j++)
+				debug("%s\"%s\"", j? ", " : "",
+				    mes->aliases[j]);
+			debug(")\n");
+		}
+		debug_indentation(-iadd2);
+
+		me = me->next;
+	}
+	debug_indentation(-iadd);
+
+	debug("\nMost of the machine types are bogus too. Please read the "
+	    "GXemul documentation\nfor information about which machine types "
+	    "that actually work. Use the alias\nwhen selecting a machine type "
+	    "or subtype, not the real name.\n");
+
+	debug("\n");
+}
+
+
+/*
+ *  machine_init():
+ *
+ *  This function should be called before any other machine_*() function
+ *  is used.  automachine_init() registers all machines in src/machines/.
+ */
+void machine_init(void)
+{
+	if (first_machine_entry != NULL) {
+		fatal("machine_init(): already called?\n");
+		exit(1);
+	}
+
+	automachine_init();
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_cats.c gxemul-0.7.0+dfsg/src/machines/machine_cats.c
--- gxemul-0.6.2/src/machines/machine_cats.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_cats.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,155 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Simtec Electronics' CATS board
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_isa.h"
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/cyclone_boot.h"
+
+
+MACHINE_SETUP(cats)
+{
+	struct ebsaboot ebsaboot;
+	struct pci_data *pci_bus;
+	char bs[300], tmpstr[400];
+	int boot_id = machine->bootdev_id >= 0? machine->bootdev_id : 0;
+
+	machine->machine_name = strdup("CATS evaluation board");
+
+	if (machine->emulated_hz == 0)
+		machine->emulated_hz = 50000000;
+
+	if (machine->physical_ram_in_mb > 256)
+		fprintf(stderr, "WARNING! Real CATS machines cannot"
+		    " have more than 256 MB RAM. Continuing anyway.\n");
+
+	snprintf(tmpstr, sizeof(tmpstr), "footbridge irq=%s.cpu[%i].irq"
+	    " addr=0x42000000", machine->path, machine->bootstrap_cpu);
+	pci_bus = (struct pci_data *) device_add(machine, tmpstr);
+
+	/*  DC21285_ROM_BASE (256 KB at 0x41000000)  */
+	dev_ram_init(machine, 0x41000000, 256 * 1024, DEV_RAM_RAM, 0, NULL);
+
+	/*  NetBSD, OpenBSD, and Linux (?) clean their caches here:  */
+	dev_ram_init(machine, 0x50000000, 0x10000, DEV_RAM_RAM, 0, NULL);
+
+	/*  Interrupt ack space?  */
+	dev_ram_init(machine, 0x80000000, 0x1000, DEV_RAM_RAM, 0, NULL);
+
+	/*  Linux uses 0xc0000000 as phys.:  */
+	dev_ram_init(machine, 0xc0000000, 0x20000000, DEV_RAM_MIRROR, 0x0, NULL);
+
+	/*  OpenBSD reboot needs 0xf??????? to be mapped to phys.:  */
+	dev_ram_init(machine, 0xf0000000, 0x1000000, DEV_RAM_MIRROR, 0x0, NULL);
+
+	bus_pci_add(machine, pci_bus, machine->memory, 0xc0, 8, 0, "s3_virge");
+
+	if (!machine->prom_emulation)
+		return;
+
+	/*  See cyclone_boot.h for details.  */
+
+	/*  DC21285_ROM_BASE "reboot" code:  (works with NetBSD)  */
+	store_32bit_word(cpu, 0x41000008ULL, 0xef8c64ebUL);
+
+	cpu->cd.arm.r[0] = /* machine->physical_ram_in_mb */
+	    7 * 1048576 - 0x1000;
+
+	memset(&ebsaboot, 0, sizeof(struct ebsaboot));
+	store_32bit_word_in_host(cpu, (unsigned char *)
+	    &(ebsaboot.bt_magic), BT_MAGIC_NUMBER_CATS);
+	store_32bit_word_in_host(cpu, (unsigned char *)
+	    &(ebsaboot.bt_vargp), 0);
+	store_32bit_word_in_host(cpu, (unsigned char *)
+	    &(ebsaboot.bt_pargp), 0);
+	store_32bit_word_in_host(cpu, (unsigned char *)
+	    &(ebsaboot.bt_args), cpu->cd.arm.r[0]
+	    + sizeof(struct ebsaboot));
+	store_32bit_word_in_host(cpu, (unsigned char *)
+	    &(ebsaboot.bt_l1), 7 * 1048576 - 32768);
+	store_32bit_word_in_host(cpu, (unsigned char *)
+	    &(ebsaboot.bt_memstart), 0);
+	store_32bit_word_in_host(cpu, (unsigned char *)
+	    &(ebsaboot.bt_memend),
+	    machine->physical_ram_in_mb * 1048576);
+	store_32bit_word_in_host(cpu, (unsigned char *)
+	    &(ebsaboot.bt_memavail), 7 * 1048576);
+	store_32bit_word_in_host(cpu, (unsigned char *)
+	    &(ebsaboot.bt_fclk), 50 * 1000000);
+	store_32bit_word_in_host(cpu, (unsigned char *)
+	    &(ebsaboot.bt_pciclk), 66 * 1000000);
+	/*  TODO: bt_vers  */
+	/*  TODO: bt_features  */
+
+	store_buf(cpu, cpu->cd.arm.r[0],
+	    (char *)&ebsaboot, sizeof(struct ebsaboot));
+
+	snprintf(bs, sizeof(bs), "(hd%i)%s root=/dev/wd%i%s%s",
+	    boot_id, machine->boot_kernel_filename, boot_id,
+	    (machine->boot_string_argument[0])? " " : "",
+	    machine->boot_string_argument);
+
+	store_string(cpu, cpu->cd.arm.r[0]+sizeof(struct ebsaboot), bs);
+
+	arm_setup_initial_translation_table(cpu, 7 * 1048576 - 32768);
+}
+
+
+MACHINE_DEFAULT_CPU(cats)
+{
+	machine->cpu_name = strdup("SA110");
+}
+
+
+MACHINE_DEFAULT_RAM(cats)
+{
+	machine->physical_ram_in_mb = 64;
+}
+
+
+MACHINE_REGISTER(cats)
+{
+	MR_DEFAULT(cats, "CATS evaluation board", MACHINE_CATS);
+
+	machine_entry_add_alias(me, "cats");
+
+	me->set_default_ram = machine_default_ram_cats;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_cats.cc gxemul-0.7.0+dfsg/src/machines/machine_cats.cc
--- gxemul-0.6.2/src/machines/machine_cats.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_cats.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,156 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Simtec Electronics' CATS board
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_isa.h"
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/cyclone_boot.h"
-
-
-MACHINE_SETUP(cats)
-{
-	struct ebsaboot ebsaboot;
-	struct pci_data *pci_bus;
-	char bs[300], tmpstr[400];
-	int boot_id = machine->bootdev_id >= 0? machine->bootdev_id : 0;
-
-	machine->machine_name = strdup("CATS evaluation board");
-
-	if (machine->emulated_hz == 0)
-		machine->emulated_hz = 50000000;
-
-	if (machine->physical_ram_in_mb > 256)
-		fprintf(stderr, "WARNING! Real CATS machines cannot"
-		    " have more than 256 MB RAM. Continuing anyway.\n");
-
-	snprintf(tmpstr, sizeof(tmpstr), "footbridge irq=%s.cpu[%i].irq"
-	    " addr=0x42000000", machine->path, machine->bootstrap_cpu);
-	pci_bus = (struct pci_data *) device_add(machine, tmpstr);
-
-	/*  DC21285_ROM_BASE (256 KB at 0x41000000)  */
-	dev_ram_init(machine, 0x41000000, 256 * 1024, DEV_RAM_RAM, 0);
-
-	/*  NetBSD, OpenBSD, and Linux (?) clean their caches here:  */
-	dev_ram_init(machine, 0x50000000, 0x10000, DEV_RAM_RAM, 0);
-
-	/*  Interrupt ack space?  */
-	dev_ram_init(machine, 0x80000000, 0x1000, DEV_RAM_RAM, 0);
-
-	/*  Linux uses 0xc0000000 as phys.:  */
-	dev_ram_init(machine, 0xc0000000, 0x20000000, DEV_RAM_MIRROR, 0x0);
-
-	/*  OpenBSD reboot needs 0xf??????? to be mapped to phys.:  */
-	dev_ram_init(machine, 0xf0000000, 0x1000000, DEV_RAM_MIRROR, 0x0);
-
-	bus_pci_add(machine, pci_bus, machine->memory, 0xc0, 8, 0, "s3_virge");
-
-	if (!machine->prom_emulation)
-		return;
-
-	/*  See cyclone_boot.h for details.  */
-
-	/*  DC21285_ROM_BASE "reboot" code:  (works with NetBSD)  */
-	store_32bit_word(cpu, 0x41000008ULL, 0xef8c64ebUL);
-
-	cpu->cd.arm.r[0] = /* machine->physical_ram_in_mb */
-	    7 * 1048576 - 0x1000;
-
-	memset(&ebsaboot, 0, sizeof(struct ebsaboot));
-	store_32bit_word_in_host(cpu, (unsigned char *)
-	    &(ebsaboot.bt_magic), BT_MAGIC_NUMBER_CATS);
-	store_32bit_word_in_host(cpu, (unsigned char *)
-	    &(ebsaboot.bt_vargp), 0);
-	store_32bit_word_in_host(cpu, (unsigned char *)
-	    &(ebsaboot.bt_pargp), 0);
-	store_32bit_word_in_host(cpu, (unsigned char *)
-	    &(ebsaboot.bt_args), cpu->cd.arm.r[0]
-	    + sizeof(struct ebsaboot));
-	store_32bit_word_in_host(cpu, (unsigned char *)
-	    &(ebsaboot.bt_l1), 7 * 1048576 - 32768);
-	store_32bit_word_in_host(cpu, (unsigned char *)
-	    &(ebsaboot.bt_memstart), 0);
-	store_32bit_word_in_host(cpu, (unsigned char *)
-	    &(ebsaboot.bt_memend),
-	    machine->physical_ram_in_mb * 1048576);
-	store_32bit_word_in_host(cpu, (unsigned char *)
-	    &(ebsaboot.bt_memavail), 7 * 1048576);
-	store_32bit_word_in_host(cpu, (unsigned char *)
-	    &(ebsaboot.bt_fclk), 50 * 1000000);
-	store_32bit_word_in_host(cpu, (unsigned char *)
-	    &(ebsaboot.bt_pciclk), 66 * 1000000);
-	/*  TODO: bt_vers  */
-	/*  TODO: bt_features  */
-
-	store_buf(cpu, cpu->cd.arm.r[0],
-	    (char *)&ebsaboot, sizeof(struct ebsaboot));
-
-	snprintf(bs, sizeof(bs), "(hd%i)%s root=/dev/wd%i%s%s",
-	    boot_id, machine->boot_kernel_filename, boot_id,
-	    (machine->boot_string_argument[0])? " " : "",
-	    machine->boot_string_argument);
-
-	store_string(cpu, cpu->cd.arm.r[0]+sizeof(struct ebsaboot), bs);
-
-	arm_setup_initial_translation_table(cpu, 7 * 1048576 - 32768);
-}
-
-
-MACHINE_DEFAULT_CPU(cats)
-{
-	machine->cpu_name = strdup("SA110");
-}
-
-
-MACHINE_DEFAULT_RAM(cats)
-{
-	machine->physical_ram_in_mb = 64;
-}
-
-
-MACHINE_REGISTER(cats)
-{
-	MR_DEFAULT(cats, "CATS evaluation board", ARCH_ARM,
-	    MACHINE_CATS);
-
-	machine_entry_add_alias(me, "cats");
-
-	me->set_default_ram = machine_default_ram_cats;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine.cc gxemul-0.7.0+dfsg/src/machines/machine.cc
--- gxemul-0.6.2/src/machines/machine.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,874 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Machine registry.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdarg.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "diskimage.h"
-#include "emul.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "settings.h"
-#include "symbol.h"
-
-
-/*  This is initialized by machine_init():  */
-struct machine_entry *first_machine_entry = NULL;
-
-
-/*
- *  machine_new():
- *
- *  Returns a reasonably initialized struct machine.
- */
-struct machine *machine_new(char *name, struct emul *emul, int id)
-{
-	struct machine *m;
-
-	CHECK_ALLOCATION(m = (struct machine *) malloc(sizeof(struct machine)));
-	memset(m, 0, sizeof(struct machine));
-
-	/*  Pointer back to the emul object that this machine belongs to:  */
-	m->emul = emul;
-
-	if (name != NULL)
-		CHECK_ALLOCATION(m->name = strdup(name));
-
-	/*  Full path, e.g. "machine[0]":  */
-	CHECK_ALLOCATION(m->path = (char *) malloc(20));
-	snprintf(m->path, 20, "machine[%i]", id);
-
-	/*  Sane default values:  */
-	m->serial_nr = 1;
-	m->machine_type = MACHINE_NONE;
-	m->machine_subtype = MACHINE_NONE;
-	m->arch_pagesize = 4096;	/*  Should be overriden in
-					    emul.c for other pagesizes.  */
-	m->prom_emulation = 1;
-	m->allow_instruction_combinations = 1;
-	m->byte_order_override = NO_BYTE_ORDER_OVERRIDE;
-	m->boot_kernel_filename = strdup("");
-	m->boot_string_argument = NULL;
-	m->x11_md.scaledown = 1;
-	m->x11_md.scaleup = 1;
-	m->n_gfx_cards = 1;
-	symbol_init(&m->symbol_context);
-
-	/*  Settings:  */
-	m->settings = settings_new();
-	settings_add(m->settings, "name", 0,
-	    SETTINGS_TYPE_STRING, SETTINGS_FORMAT_STRING,
-	    (void *) &m->name);
-	settings_add(m->settings, "serial_nr", 0,
-	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_DECIMAL,
-	    (void *) &m->serial_nr);
-	settings_add(m->settings, "arch_pagesize", 0,
-	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_DECIMAL,
-	    (void *) &m->arch_pagesize);
-	settings_add(m->settings, "prom_emulation", 0,
-	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO,
-	    (void *) &m->prom_emulation);
-	settings_add(m->settings, "allow_instruction_combinations", 0,
-	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO,
-	    (void *) &m->allow_instruction_combinations);
-	settings_add(m->settings, "n_gfx_cards", 0,
-	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_DECIMAL,
-	    (void *) &m->n_gfx_cards);
-	settings_add(m->settings, "statistics_enabled", 1,
-	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO,
-	    (void *) &m->statistics.enabled);
-
-	return m;
-}
-
-
-/*
- *  machine_destroy():
- *
- *  Destroys a machine object.
- */
-void machine_destroy(struct machine *machine)
-{
-	int i;
-
-	for (i=0; i<machine->ncpus; i++)
-		cpu_destroy(machine->cpus[i]);
-
-	// TODO: Memory leak; but it's ok, since the whole legacy thing should
-	// be replaced anyway.
-	// if (machine->name != NULL)
-	// 	free(machine->name);
-
-	if (machine->path != NULL)
-		free(machine->path);
-
-	/*  Remove any remaining level-1 settings:  */
-	settings_remove_all(machine->settings);
-	settings_destroy(machine->settings);
-
-	free(machine);
-}
-
-
-/*
- *  machine_name_to_type():
- *
- *  Take a type and a subtype as strings, and convert them into numeric
- *  values used internally throughout the code.
- *
- *  Return value is 1 on success, 0 if there was no match.
- *  Also, any errors/warnings are printed using fatal()/debug().
- */
-int machine_name_to_type(char *stype, char *ssubtype,
-	int *type, int *subtype, int *arch)
-{
-	struct machine_entry *me;
-	int i, j, k, nmatches = 0;
-
-	*type = MACHINE_NONE;
-	*subtype = 0;
-
-	/*  Check stype, and optionally ssubtype:  */
-	me = first_machine_entry;
-	while (me != NULL) {
-		for (i=0; i<me->n_aliases; i++)
-			if (strcasecmp(me->aliases[i], stype) == 0) {
-				/*  Found a type:  */
-				*type = me->machine_type;
-				*arch = me->arch;
-
-				if (me->n_subtypes == 0)
-					return 1;
-
-				/*  Check for subtype:  */
-				for (j=0; j<me->n_subtypes; j++)
-					for (k=0; k<me->subtype[j]->n_aliases;
-					    k++)
-						if (strcasecmp(ssubtype,
-						    me->subtype[j]->aliases[k]
-						    ) == 0) {
-							*subtype = me->subtype[
-							    j]->machine_subtype;
-							return 1;
-						}
-
-				fatal("Unknown subtype '%s' for emulation"
-				    " '%s'\n", ssubtype, stype);
-				if (!ssubtype[0])
-					fatal("(Maybe you forgot the -e"
-					    " command line option?)\n");
-				exit(1);
-			}
-
-		me = me->next;
-	}
-
-	/*  Not found? Then just check ssubtype:  */
-	me = first_machine_entry;
-	while (me != NULL) {
-		if (me->n_subtypes == 0) {
-			me = me->next;
-			continue;
-		}
-
-		/*  Check for subtype:  */
-		for (j=0; j<me->n_subtypes; j++)
-			for (k=0; k<me->subtype[j]->n_aliases; k++)
-				if (strcasecmp(ssubtype, me->subtype[j]->
-				    aliases[k]) == 0) {
-					*type = me->machine_type;
-					*arch = me->arch;
-					*subtype = me->subtype[j]->
-					    machine_subtype;
-					nmatches ++;
-				}
-
-		me = me->next;
-	}
-
-	switch (nmatches) {
-	case 0:	fatal("\nSorry, emulation \"%s\"", stype);
-		if (ssubtype != NULL && ssubtype[0] != '\0')
-			fatal(" (subtype \"%s\")", ssubtype);
-		fatal(" is unknown.\n");
-		break;
-	case 1:	return 1;
-	default:fatal("\nSorry, multiple matches for \"%s\"", stype);
-		if (ssubtype != NULL && ssubtype[0] != '\0')
-			fatal(" (subtype \"%s\")", ssubtype);
-		fatal(".\n");
-	}
-
-	*type = MACHINE_NONE;
-	*subtype = 0;
-
-	fatal("Use the -H command line option to get a list of "
-	    "available types and subtypes.\n\n");
-
-	return 0;
-}
-
-
-/*
- *  machine_add_breakpoint_string():
- *
- *  Add a breakpoint string to the machine. Later (in emul.c) these will be
- *  converted to actual breakpoints.
- */
-void machine_add_breakpoint_string(struct machine *machine, char *str)
-{
-	int n = machine->breakpoints.n + 1;
-
-	CHECK_ALLOCATION(machine->breakpoints.string = (char **)
-	    realloc(machine->breakpoints.string, n * sizeof(char *)));
-	CHECK_ALLOCATION(machine->breakpoints.addr = (uint64_t *)
-	    realloc(machine->breakpoints.addr, n * sizeof(uint64_t)));
-	CHECK_ALLOCATION(machine->breakpoints.string[machine->breakpoints.n] =
-	    strdup(optarg));
-
-	machine->breakpoints.addr[machine->breakpoints.n] = 0;
-	machine->breakpoints.n ++;
-}
-
-
-/*
- *  machine_add_tickfunction():
- *
- *  Adds a tick function (a function called every now and then, depending on
- *  clock cycle count) to a machine.
- *
- *  If tickshift is non-zero, a tick will occur every (1 << tickshift) cycles.
- *  This is used for the normal (fast dyntrans) emulation modes.
- *
- *  If tickshift is zero, then this is a cycle-accurate tick function.
- *  The hz value is used in this case.
- */
-void machine_add_tickfunction(struct machine *machine, void (*func)
-	(struct cpu *, void *), void *extra, int tickshift)
-{
-	int n = machine->tick_functions.n_entries;
-
-	CHECK_ALLOCATION(machine->tick_functions.ticks_till_next = (int *) realloc(
-	    machine->tick_functions.ticks_till_next, (n+1) * sizeof(int)));
-	CHECK_ALLOCATION(machine->tick_functions.ticks_reset_value = (int *) realloc(
-	    machine->tick_functions.ticks_reset_value, (n+1) * sizeof(int)));
-	CHECK_ALLOCATION(machine->tick_functions.f = (void (**)(cpu*,void*)) realloc(
-	    machine->tick_functions.f, (n+1) * sizeof(void *)));
-	CHECK_ALLOCATION(machine->tick_functions.extra = (void **) realloc(
-	    machine->tick_functions.extra, (n+1) * sizeof(void *)));
-
-	/*
-	 *  The dyntrans subsystem wants to run code in relatively
-	 *  large chunks without checking for external interrupts;
-	 *  too low tickshifts are not allowed.
-	 */
-	if (tickshift < N_SAFE_DYNTRANS_LIMIT_SHIFT) {
-		fatal("ERROR! tickshift = %i, less than "
-		    "N_SAFE_DYNTRANS_LIMIT_SHIFT (%i)\n",
-		    tickshift, N_SAFE_DYNTRANS_LIMIT_SHIFT);
-		exit(1);
-	}
-
-	machine->tick_functions.ticks_till_next[n]   = 0;
-	machine->tick_functions.ticks_reset_value[n] = 1 << tickshift;
-	machine->tick_functions.f[n]                 = func;
-	machine->tick_functions.extra[n]             = extra;
-
-	machine->tick_functions.n_entries = n + 1;
-}
-
-
-/*
- *  machine_statistics_init():
- *
- *  Initialize the parts of a machine struct that deal with instruction
- *  statistics gathering.
- *
- *  Note: The fname argument contains "flags:filename".
- */
-void machine_statistics_init(struct machine *machine, char *fname)
-{
-	int n_fields = 0;
-	char *pcolon = fname;
-	const char *mode = "a";	/*  Append by default  */
-
-	machine->allow_instruction_combinations = 0;
-
-	if (machine->statistics.fields != NULL) {
-		fprintf(stderr, "Only one -s option is allowed.\n");
-		exit(1);
-	}
-
-	machine->statistics.enabled = 1;
-	CHECK_ALLOCATION(machine->statistics.fields = (char *) malloc(1));
-	machine->statistics.fields[0] = '\0';
-
-	while (*pcolon && *pcolon != ':')
-		pcolon ++;
-
-	if (*pcolon != ':') {
-		fprintf(stderr, "The syntax for the -s option is:    "
-		    "-s flags:filename\nYou omitted the flags. Run g"
-		    "xemul -h for a list of available flags.\n");
-		exit(1);
-	}
-
-	while (*fname != ':') {
-		switch (*fname) {
-
-		/*  Type flags:  */
-		case 'v':
-		case 'i':
-		case 'p':
-			CHECK_ALLOCATION(machine->statistics.fields = (char *) realloc(
-			    machine->statistics.fields, strlen(
-			    machine->statistics.fields) + 2));
-			machine->statistics.fields[n_fields ++] = *fname;
-			machine->statistics.fields[n_fields] = '\0';
-			break;
-
-		/*  Optional flags:  */
-		case 'o':
-			mode = "w";
-			break;
-		case 'd':
-			machine->statistics.enabled = 0;
-			break;
-
-		default:fprintf(stderr, "Unknown flag '%c' used with the"
-			    " -s option. Aborting.\n", *fname);
-			exit(1);
-		}
-		fname ++;
-	}
-
-	fname ++;	/*  point to the filename after the colon  */
-
-	CHECK_ALLOCATION(machine->statistics.filename = strdup(fname));
-	machine->statistics.file = fopen(machine->statistics.filename, mode);
-}
-
-
-/*
- *  machine_dumpinfo():
- *
- *  Dumps info about a machine in some kind of readable format. (Used by
- *  the 'machine' debugger command.)
- */
-void machine_dumpinfo(struct machine *m)
-{
-	int i;
-
-	debug("serial nr: %i", m->serial_nr);
-	if (m->nr_of_nics > 0)
-		debug("  (nr of NICs: %i)", m->nr_of_nics);
-	debug("\n");
-
-	debug("memory: %i MB", m->physical_ram_in_mb);
-	if (m->memory_offset_in_mb != 0)
-		debug(" (offset by %i MB)", m->memory_offset_in_mb);
-	if (m->random_mem_contents)
-		debug(", randomized contents");
-	debug("\n");
-
-	if (!m->prom_emulation)
-		debug("PROM emulation disabled\n");
-
-	for (i=0; i<m->ncpus; i++)
-		cpu_dumpinfo(m, m->cpus[i]);
-
-	if (m->ncpus > 1)
-		debug("Bootstrap cpu is nr %i\n", m->bootstrap_cpu);
-
-	if (m->slow_serial_interrupts_hack_for_linux)
-		debug("Using slow_serial_interrupts_hack_for_linux\n");
-
-	if (m->x11_md.in_use) {
-		debug("Using X11");
-		if (m->x11_md.scaledown > 1)
-			debug(", scaledown %i", m->x11_md.scaledown);
-		if (m->x11_md.scaleup > 1)
-			debug(", scaleup %i", m->x11_md.scaleup);
-		if (m->x11_md.n_display_names > 0) {
-			for (i=0; i<m->x11_md.n_display_names; i++) {
-				debug(i? ", " : " (");
-				debug("\"%s\"", m->x11_md.display_names[i]);
-			}
-			debug(")");
-		}
-		debug("\n");
-	}
-
-	diskimage_dump_info(m);
-
-	if (m->force_netboot)
-		debug("Forced netboot\n");
-}
-
-
-/*
- *  machine_setup():
- *
- *  This function initializes memory, registers, and/or devices
- *  required by specific machine emulations.
- */
-void machine_setup(struct machine *machine)
-{
-	struct memory *mem;
-	struct machine_entry *me;
-
-	/*  Abreviation:  :-)  */
-	struct cpu *cpu = machine->cpus[machine->bootstrap_cpu];
-
-	machine->bootdev_id = diskimage_bootdev(machine,
-	    &machine->bootdev_type);
-
-	mem = cpu->mem;
-	machine->machine_name = NULL;
-
-	/*  TODO: Move this somewhere else?  */
-	if (machine->boot_string_argument == NULL) {
-		switch (machine->machine_type) {
-		case MACHINE_ARC:
-			machine->boot_string_argument = strdup("-aN");
-			break;
-		case MACHINE_CATS:
-			machine->boot_string_argument = strdup("-A");
-			break;
-		case MACHINE_PMAX:
-			machine->boot_string_argument = strdup("-a");
-			break;
-		default:
-			/*  Important, because boot_string_argument should
-			    not be set to NULL:  */
-			machine->boot_string_argument = strdup("");
-		}
-	}
-
-
-	/*
-	 *  If the machine has a setup function in src/machines/machine_*.c
-	 *  then use that one, otherwise use the old hardcoded stuff here:
-	 */
-
-	me = first_machine_entry;
-	while (me != NULL) {
-		if (machine->machine_type == me->machine_type &&
-		    me->setup != NULL) {
-			me->setup(machine, cpu);
-			break;
-		}
-		me = me->next;
-	}
-
-	if (me == NULL) {
-		fatal("Unknown emulation type %i\n", machine->machine_type);
-		exit(1);
-	}
-
-	if (machine->machine_name != NULL)
-		debug("machine: %s", machine->machine_name);
-
-	if (machine->emulated_hz > 0)
-		debug(" (%.2f MHz)", (float)machine->emulated_hz / 1000000);
-	debug("\n");
-
-	if (machine->bootstr != NULL) {
-		debug("bootstring%s: %s", (machine->bootarg!=NULL &&
-		    strlen(machine->bootarg) >= 1)? "(+bootarg)" : "",
-		    machine->bootstr);
-		if (machine->bootarg != NULL && strlen(machine->bootarg) >= 1)
-			debug(" %s", machine->bootarg);
-		debug("\n");
-	}
-}
-
-
-/*
- *  machine_memsize_fix():
- *
- *  Sets physical_ram_in_mb (if not already set), and memory_offset_in_mb,
- *  depending on machine type.
- */
-void machine_memsize_fix(struct machine *m)
-{
-	if (m == NULL) {
-		fatal("machine_defaultmemsize(): m == NULL?\n");
-		exit(1);
-	}
-
-	if (m->physical_ram_in_mb == 0) {
-		struct machine_entry *me = first_machine_entry;
-		while (me != NULL) {
-			if (m->machine_type == me->machine_type &&
-			    me->set_default_ram != NULL) {
-				me->set_default_ram(m);
-				break;
-			}
-			me = me->next;
-		}
-	}
-
-	/*  Special SGI memory offsets:  (TODO: move this somewhere else)  */
-	if (m->machine_type == MACHINE_SGI) {
-		switch (m->machine_subtype) {
-		case 20:
-		case 22:
-		case 24:
-		case 26:
-			m->memory_offset_in_mb = 128;
-			break;
-		case 28:
-		case 30:
-			m->memory_offset_in_mb = 512;
-			break;
-		}
-	}
-
-	if (m->physical_ram_in_mb == 0)
-		m->physical_ram_in_mb = DEFAULT_RAM_IN_MB;
-}
-
-
-/*
- *  machine_default_cputype():
- *
- *  Sets m->cpu_name, if it isn't already set, depending on the machine type.
- */
-void machine_default_cputype(struct machine *m)
-{
-	struct machine_entry *me;
-
-	if (m == NULL) {
-		fatal("machine_default_cputype(): m == NULL?\n");
-		exit(1);
-	}
-
-	/*  Already set? Then return.  */
-	if (m->cpu_name != NULL)
-		return;
-
-	me = first_machine_entry;
-	while (me != NULL) {
-		if (m->machine_type == me->machine_type &&
-		    me->set_default_cpu != NULL) {
-			me->set_default_cpu(m);
-			break;
-		}
-		me = me->next;
-	}
-
-	if (m->cpu_name == NULL) {
-		fprintf(stderr, "machine_default_cputype(): no default"
-		    " cpu for machine type %i subtype %i\n",
-		    m->machine_type, m->machine_subtype);
-		exit(1);
-	}
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  machine_run():
- *
- *  Run one or more instructions on all CPUs in this machine. (Usually,
- *  around N_SAFE_DYNTRANS_LIMIT instructions will be run by the dyntrans
- *  system.)
- *
- *  Return value is 1 if any CPU in this machine is still running,
- *  or 0 if all CPUs are stopped.
- */
-int machine_run(struct machine *machine)
-{
-	struct cpu **cpus = machine->cpus;
-	int ncpus = machine->ncpus, cpu0instrs = 0, i, te;
-
-	for (i=0; i<ncpus; i++) {
-		if (cpus[i]->running) {
-			int instrs_run = cpus[i]->run_instr(cpus[i]);
-			if (i == 0)
-				cpu0instrs += instrs_run;
-		}
-	}
-
-	/*
-	 *  Hardware 'ticks':  (clocks, interrupt sources...)
-	 *
-	 *  Here, cpu0instrs is the number of instructions executed on cpu0.
-	 *
-	 *  TODO: This should be redesigned into some "mainbus" stuff instead!
-	 */
-
-	for (te=0; te<machine->tick_functions.n_entries; te++) {
-		machine->tick_functions.ticks_till_next[te] -= cpu0instrs;
-		if (machine->tick_functions.ticks_till_next[te] <= 0) {
-			while (machine->tick_functions.ticks_till_next[te]<=0) {
-				machine->tick_functions.ticks_till_next[te] +=
-				    machine->tick_functions.
-				    ticks_reset_value[te];
-			}
-
-			machine->tick_functions.f[te](cpus[0],
-			    machine->tick_functions.extra[te]);
-		}
-	}
-
-	/*  Is any CPU still alive?  */
-	for (i=0; i<ncpus; i++)
-		if (cpus[i]->running)
-			return 1;
-
-	return 0;
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  machine_entry_new():
- *
- *  This function creates a new machine_entry struct, and fills it with some
- *  valid data; it is up to the caller to add additional data that weren't
- *  passed as arguments to this function, such as alias names and machine
- *  subtypes.
- */
-struct machine_entry *machine_entry_new(const char *name, int arch,
-	int oldstyle_type)
-{
-	struct machine_entry *me;
-
-	CHECK_ALLOCATION(me = (struct machine_entry *) malloc(sizeof(struct machine_entry)));
-	memset(me, 0, sizeof(struct machine_entry));
-
-	me->name = name;
-	me->arch = arch;
-	me->machine_type = oldstyle_type;
-	me->n_aliases = 0;
-	me->aliases = NULL;
-	me->n_subtypes = 0;
-	me->setup = NULL;
-
-	return me;
-}
-
-
-/*
- *  machine_entry_add_alias():
- *
- *  This function adds an "alias" to a machine entry.
- */
-void machine_entry_add_alias(struct machine_entry *me, const char *name)
-{
-	me->n_aliases ++;
-
-	CHECK_ALLOCATION(me->aliases = (char **) realloc(me->aliases,
-	    sizeof(char *) * me->n_aliases));
-
-	me->aliases[me->n_aliases - 1] = strdup(name);
-}
-
-
-/*
- *  machine_entry_add_subtype():
- *
- *  This function adds a subtype to a machine entry. The argument list after
- *  oldstyle_subtype is a list of one or more char *, followed by NULL. E.g.:
- *
- *	machine_entry_add_subtype(me, "Machine X", MACHINE_X,
- *	    "machine-x", "x", NULL);
- */
-void machine_entry_add_subtype(struct machine_entry *me, const char *name,
-	int oldstyle_subtype, ...)
-{
-	va_list argp;
-	struct machine_entry_subtype *mes;
-
-	/*  Allocate a new subtype struct:  */
-	CHECK_ALLOCATION(mes = (struct machine_entry_subtype *)
-	    malloc(sizeof(struct machine_entry_subtype)));
-
-	/*  Add the subtype to the machine entry:  */
-	me->n_subtypes ++;
-	CHECK_ALLOCATION(me->subtype = (struct
-	    machine_entry_subtype **) realloc(me->subtype, sizeof(struct
-	    machine_entry_subtype *) * me->n_subtypes));
-	me->subtype[me->n_subtypes - 1] = mes;
-
-	/*  Fill the struct with subtype data:  */
-	memset(mes, 0, sizeof(struct machine_entry_subtype));
-	mes->name = name;
-	mes->machine_subtype = oldstyle_subtype;
-
-	/*  ... and all aliases:  */
-	mes->n_aliases = 0;
-	mes->aliases = NULL;
-
-	va_start(argp, oldstyle_subtype);
-
-	for (;;) {
-		char *s = va_arg(argp, char *);
-		if (s == NULL)
-			break;
-
-		mes->n_aliases ++;
-		CHECK_ALLOCATION(mes->aliases = (char **)
-		    realloc(mes->aliases, sizeof(char *) * mes->n_aliases));
-
-		mes->aliases[mes->n_aliases - 1] = s;
-	}
-
-	va_end(argp);
-}
-
-
-/*
- *  machine_entry_register():
- *
- *  Inserts a new machine_entry into the machine entries list.
- */
-void machine_entry_register(struct machine_entry *me, int arch)
-{
-	struct machine_entry *prev, *next;
-
-	/*  Only insert it if the architecture is implemented in this
-	    emulator configuration:  */
-	if (cpu_family_ptr_by_number(arch) == NULL)
-		return;
-
-	prev = NULL;
-	next = first_machine_entry;
-
-	for (;;) {
-		if (next == NULL)
-			break;
-		if (strcasecmp(me->name, next->name) < 0)
-			break;
-
-		prev = next;
-		next = next->next;
-	}
-
-	if (prev != NULL)
-		prev->next = me;
-	else
-		first_machine_entry = me;
-	me->next = next;
-}
-
-
-/*
- *  machine_list_available_types_and_cpus():
- *
- *  List all available machine types (for example when running the emulator
- *  with just -H as command line argument).
- */
-void machine_list_available_types_and_cpus(void)
-{
-	struct machine_entry *me;
-	int iadd = DEBUG_INDENTATION * 2;
-
-	debug("Available CPU types:\n\n");
-
-	debug_indentation(iadd);
-	cpu_list_available_types();
-	debug_indentation(-iadd);  
-
-	debug("\nMost of the CPU types are bogus, and not really implemented."
-	    " The main effect of\nselecting a specific CPU type is to choose "
-	    "what kind of 'id' it will have.\n\nAvailable machine types (with "
-	    "aliases) and their subtypes:\n\n");
-
-	debug_indentation(iadd);
-	me = first_machine_entry;
-
-	if (me == NULL)
-		fatal("No machines defined!\n");
-
-	while (me != NULL) {
-		int i, j, iadd2 = DEBUG_INDENTATION;
-
-		debug("%s [%s] (", me->name,
-		    cpu_family_ptr_by_number(me->arch)->name);
-		for (i=0; i<me->n_aliases; i++)
-			debug("%s\"%s\"", i? ", " : "", me->aliases[i]);
-		debug(")\n");
-
-		debug_indentation(iadd2);
-		for (i=0; i<me->n_subtypes; i++) {
-			struct machine_entry_subtype *mes;
-			mes = me->subtype[i];
-			debug("- %s", mes->name);
-			debug(" (");
-			for (j=0; j<mes->n_aliases; j++)
-				debug("%s\"%s\"", j? ", " : "",
-				    mes->aliases[j]);
-			debug(")\n");
-		}
-		debug_indentation(-iadd2);
-
-		me = me->next;
-	}
-	debug_indentation(-iadd);
-
-	debug("\nMost of the machine types are bogus too. Please read the "
-	    "GXemul documentation\nfor information about which machine types "
-	    "that actually work. Use the alias\nwhen selecting a machine type "
-	    "or subtype, not the real name.\n");
-
-	debug("\n");
-}
-
-
-/*
- *  machine_init():
- *
- *  This function should be called before any other machine_*() function
- *  is used.  automachine_init() registers all machines in src/machines/.
- */
-void machine_init(void)
-{
-	if (first_machine_entry != NULL) {
-		fatal("machine_init(): already called?\n");
-		exit(1);
-	}
-
-	automachine_init();
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_cobalt.c gxemul-0.7.0+dfsg/src/machines/machine_cobalt.c
--- gxemul-0.6.2/src/machines/machine_cobalt.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_cobalt.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,147 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Cobalt (MIPS-based)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_isa.h"
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+MACHINE_SETUP(cobalt)
+{
+	char tmpstr[500], tmpstr2[500];
+	struct pci_data *pci_data;
+	struct memory *mem = machine->memory;
+
+	cpu->byte_order = EMUL_LITTLE_ENDIAN;
+	machine->machine_name = strdup("Cobalt");
+
+	/*
+	 *  Interrupts seem to be the following:
+	 *  (according to http://www.funet.fi/pub/Linux/PEOPLE/Linus/v2.4/
+	 *  patch-html/patch-2.4.19/linux-2.4.19_arch_mips_cobalt_irq.c.html)
+	 *
+	 *	2	Galileo chip (timer)
+	 *	3	Tulip 0 + NCR SCSI
+	 *	4	Tulip 1
+	 *	5	16550 UART (serial console)
+	 *	6	VIA southbridge PIC
+	 *	7	PCI  (Note: Not used. The PCI controller
+	 *		interrupts at ISA interrupt 9.)
+	 */
+
+	/*  ISA bus at MIPS irq 6:  */
+	snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].6",
+	    machine->path, machine->bootstrap_cpu);
+	bus_isa_init(machine, tmpstr, 0, 0x10000000, 0x14000000 /* TODO */);
+
+	snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].5"
+	    " addr=0x1c800000 name2=tty0 in_use=1",
+	    machine->path, machine->bootstrap_cpu);
+	machine->main_console_handle = (size_t) device_add(machine, tmpstr);
+
+
+	/*
+	 *  According to NetBSD/cobalt:
+	 *
+	 *  pchb0 at pci0 dev 0 function 0: Galileo GT-64111 System Controller,
+	 *	rev 1   (NOTE: added by dev_gt_init())
+	 *  tlp0 at pci0 dev 7 function 0: DECchip 21143 Ethernet, pass 4.1
+	 *  Symbios Logic 53c860 (SCSI mass storage, revision 0x02) at pci0
+	 *	dev 8
+	 *  pcib0 at pci0 dev 9 function 0, VIA Technologies VT82C586 (Apollo
+	 *	VP) PCI-ISA Bridge, rev 37
+	 *  pciide0 at pci0 dev 9 function 1: VIA Technologies VT82C586 (Apollo
+	 *	VP) ATA33 cr
+	 *  tlp1 at pci0 dev 12 function 0: DECchip 21143 Ethernet, pass 4.1
+	 *
+	 *  The PCI controller interrupts at ISA interrupt 9. (TODO?)
+	 */
+	snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2",
+	    machine->path, machine->bootstrap_cpu);
+	snprintf(tmpstr2, sizeof(tmpstr2), "%s.cpu[%i].6",
+	    machine->path, machine->bootstrap_cpu);
+	pci_data = dev_gt_init(machine, mem, 0x14000000, tmpstr,
+	    tmpstr2, 11);
+	/*  bus_pci_add(machine, pci_data, mem, 0,  7, 0, "dec21143");  */
+	/*  bus_pci_add(machine, pci_data, mem, 0,  8, 0, "symbios_860");
+	    PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_860  */
+	bus_pci_add(machine, pci_data, mem, 0,  9, 0, "vt82c586_isa");
+	bus_pci_add(machine, pci_data, mem, 0,  9, 1, "vt82c586_ide");
+	/*  bus_pci_add(machine, pci_data, mem, 0, 12, 0, "dec21143");  */
+
+	if (!machine->prom_emulation)
+		return;
+
+
+	/*
+	 *  NetBSD/cobalt expects memsize in a0, but it seems that what
+	 *  it really wants is the end of memory + 0x80000000.
+	 *
+	 *  The bootstring is stored 512 bytes before the end of
+	 *  physical ram.
+	 */
+	cpu->cd.mips.gpr[MIPS_GPR_A0] =
+	    machine->physical_ram_in_mb * 1048576 + 0xffffffff80000000ULL;
+	machine->bootstr = strdup("root=/dev/hda1 ro");
+	/*  bootstr = "nfsroot=/usr/cobalt/";  */
+	/*  TODO: bootarg, and/or automagic boot device detection  */
+	store_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0] - 512,
+	    machine->bootstr);
+}
+
+
+MACHINE_DEFAULT_CPU(cobalt)
+{
+	machine->cpu_name = strdup("RM5200");
+}
+
+
+MACHINE_DEFAULT_RAM(cobalt)
+{
+	machine->physical_ram_in_mb = 64;
+}
+
+
+MACHINE_REGISTER(cobalt)
+{
+	MR_DEFAULT(cobalt, "Cobalt", MACHINE_COBALT);
+
+	machine_entry_add_alias(me, "cobalt");
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_cobalt.cc gxemul-0.7.0+dfsg/src/machines/machine_cobalt.cc
--- gxemul-0.6.2/src/machines/machine_cobalt.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_cobalt.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,147 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Cobalt (MIPS-based)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_isa.h"
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-MACHINE_SETUP(cobalt)
-{
-	char tmpstr[500], tmpstr2[500];
-	struct pci_data *pci_data;
-	struct memory *mem = machine->memory;
-
-	cpu->byte_order = EMUL_LITTLE_ENDIAN;
-	machine->machine_name = strdup("Cobalt");
-
-	/*
-	 *  Interrupts seem to be the following:
-	 *  (according to http://www.funet.fi/pub/Linux/PEOPLE/Linus/v2.4/
-	 *  patch-html/patch-2.4.19/linux-2.4.19_arch_mips_cobalt_irq.c.html)
-	 *
-	 *	2	Galileo chip (timer)
-	 *	3	Tulip 0 + NCR SCSI
-	 *	4	Tulip 1
-	 *	5	16550 UART (serial console)
-	 *	6	VIA southbridge PIC
-	 *	7	PCI  (Note: Not used. The PCI controller
-	 *		interrupts at ISA interrupt 9.)
-	 */
-
-	/*  ISA bus at MIPS irq 6:  */
-	snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].6",
-	    machine->path, machine->bootstrap_cpu);
-	bus_isa_init(machine, tmpstr, 0, 0x10000000, 0x14000000 /* TODO */);
-
-	snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].5"
-	    " addr=0x1c800000 name2=tty0 in_use=1",
-	    machine->path, machine->bootstrap_cpu);
-	machine->main_console_handle = (size_t) device_add(machine, tmpstr);
-
-
-	/*
-	 *  According to NetBSD/cobalt:
-	 *
-	 *  pchb0 at pci0 dev 0 function 0: Galileo GT-64111 System Controller,
-	 *	rev 1   (NOTE: added by dev_gt_init())
-	 *  tlp0 at pci0 dev 7 function 0: DECchip 21143 Ethernet, pass 4.1
-	 *  Symbios Logic 53c860 (SCSI mass storage, revision 0x02) at pci0
-	 *	dev 8
-	 *  pcib0 at pci0 dev 9 function 0, VIA Technologies VT82C586 (Apollo
-	 *	VP) PCI-ISA Bridge, rev 37
-	 *  pciide0 at pci0 dev 9 function 1: VIA Technologies VT82C586 (Apollo
-	 *	VP) ATA33 cr
-	 *  tlp1 at pci0 dev 12 function 0: DECchip 21143 Ethernet, pass 4.1
-	 *
-	 *  The PCI controller interrupts at ISA interrupt 9. (TODO?)
-	 */
-	snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2",
-	    machine->path, machine->bootstrap_cpu);
-	snprintf(tmpstr2, sizeof(tmpstr2), "%s.cpu[%i].6",
-	    machine->path, machine->bootstrap_cpu);
-	pci_data = dev_gt_init(machine, mem, 0x14000000, tmpstr,
-	    tmpstr2, 11);
-	/*  bus_pci_add(machine, pci_data, mem, 0,  7, 0, "dec21143");  */
-	/*  bus_pci_add(machine, pci_data, mem, 0,  8, 0, "symbios_860");
-	    PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_860  */
-	bus_pci_add(machine, pci_data, mem, 0,  9, 0, "vt82c586_isa");
-	bus_pci_add(machine, pci_data, mem, 0,  9, 1, "vt82c586_ide");
-	/*  bus_pci_add(machine, pci_data, mem, 0, 12, 0, "dec21143");  */
-
-	if (!machine->prom_emulation)
-		return;
-
-
-	/*
-	 *  NetBSD/cobalt expects memsize in a0, but it seems that what
-	 *  it really wants is the end of memory + 0x80000000.
-	 *
-	 *  The bootstring is stored 512 bytes before the end of
-	 *  physical ram.
-	 */
-	cpu->cd.mips.gpr[MIPS_GPR_A0] =
-	    machine->physical_ram_in_mb * 1048576 + 0xffffffff80000000ULL;
-	machine->bootstr = strdup("root=/dev/hda1 ro");
-	/*  bootstr = "nfsroot=/usr/cobalt/";  */
-	/*  TODO: bootarg, and/or automagic boot device detection  */
-	store_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0] - 512,
-	    machine->bootstr);
-}
-
-
-MACHINE_DEFAULT_CPU(cobalt)
-{
-	machine->cpu_name = strdup("RM5200");
-}
-
-
-MACHINE_DEFAULT_RAM(cobalt)
-{
-	machine->physical_ram_in_mb = 64;
-}
-
-
-MACHINE_REGISTER(cobalt)
-{
-	MR_DEFAULT(cobalt, "Cobalt", ARCH_MIPS, MACHINE_COBALT);
-
-	machine_entry_add_alias(me, "cobalt");
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_cyclonevh.c gxemul-0.7.0+dfsg/src/machines/machine_cyclonevh.c
--- gxemul-0.6.2/src/machines/machine_cyclonevh.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_cyclonevh.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,100 @@
+/*
+ *  Copyright (C) 2018-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Cyclone VH machine
+ *
+ *  For experiments with uClinux/i960.
+ *
+ *  A binary (vmlinux) can be found on this page:
+ *  https://web.archive.org/web/20010417034914/http://www.cse.ogi.edu/~kma/uClinux.html
+ *
+ *  NOTE!!! The binary at http://www.uclinux.org/pub/uClinux/ports/i960/ is corrupt;
+ *          it seems to have been uploaded/encoded with the wrong character encoding.
+ *          (At least it is broken as of 2016-04-18.)
+ *
+ *
+ *	gxemul -vvvKi -E cyclonevh 0xa3c08000:0xb8:0xa3c08020:vmlinux
+ *
+ *
+ *  See the following link for details about the Cyclone VH board:
+ *  
+ *  http://www.nj7p.org/Manuals/PDFs/Intel/273194-003.PDF
+ *  "EVAL80960VH Evaluation Platform Board Manual, December 1998"
+ *
+ *  and for the CPU:
+ *
+ *  http://www.nj7p.info/Manuals/PDFs/Intel/273173-001.PDF
+ *  "i960 VH Processor Developer's Manual, October 1998"
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+MACHINE_SETUP(cyclonevh)
+{
+	machine->machine_name = strdup("Cyclone VH");
+	machine->cpus[0]->byte_order = EMUL_LITTLE_ENDIAN;
+
+	// DRAM is at a3c0 0000 - a3ff ffff according to
+	// https://groups.google.com/forum/#!topic/intel.microprocessors.i960/tgpjDcW5Dxc
+	dev_ram_init(machine, 0xa3c00000, 0x400000, DEV_RAM_RAM, 0, "dram");
+
+	machine_add_devices_as_symbols(machine, 0);
+}
+
+
+MACHINE_DEFAULT_CPU(cyclonevh)
+{
+	// It's a "i960VH", but has a "i960Jx" core?
+	machine->cpu_name = strdup("i960Jx");
+}
+
+
+MACHINE_DEFAULT_RAM(cyclonevh)
+{
+	// TODO. Just 1 KB at offset 0. The "base" and "expanded" RAM are
+	// at higher addresses.
+	machine->physical_ram_in_mb = 1;
+}
+
+
+MACHINE_REGISTER(cyclonevh)
+{
+	MR_DEFAULT(cyclonevh, "cyclonevh", MACHINE_CYCLONEVH);
+	machine_entry_add_alias(me, "cyclonevh");
+	me->set_default_ram = machine_default_ram_cyclonevh;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_dreamcast.c gxemul-0.7.0+dfsg/src/machines/machine_dreamcast.c
--- gxemul-0.6.2/src/machines/machine_dreamcast.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_dreamcast.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,183 @@
+/*
+ *  Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: SEGA Dreamcast
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+MACHINE_SETUP(dreamcast)
+{
+	machine->machine_name = strdup("Dreamcast");
+
+	if (machine->emulated_hz == 0)
+		machine->emulated_hz = 200000000;
+
+	/*  50 MHz SH4 PCLOCK:  */
+	machine->cpus[0]->cd.sh.pclock = 50000000;
+
+	if (!machine->x11_md.in_use)
+		fprintf(stderr, "-------------------------------------"
+		    "------------------------------------------\n"
+		    "\n  WARNING!  You are emulating a Dreamcast without -X."
+		    "\n            You will miss graphical output!\n\n"
+		    "-------------------------------------"
+		    "------------------------------------------\n");
+
+	/*
+	 *  Physical address layout on the Dreamcast, according to a
+	 *  combination of sources:  NetBSD sources, KallistiOS sources,
+	 *  http://www.boob.co.uk/docs/Dreamcast_memory.txt, and
+	 *  http://www.ludd.luth.se/~jlo/dc/memory.txt, and possibly some
+	 *  others:
+	 *
+	 *  0x00000000 - 0x001fffff	Boot ROM (2 MB)
+	 *  0x00200000 - 0x0021ffff	Flash (128 KB) (perhaps multiple images afterwards?)
+	 *				The bytes read by the Dreamcast PROM during
+	 *				boot are:
+	 *				    Offset 0x1a000 .. 0x1a004 = 5 bytes debug/startup state?
+	 *					hex digits (maybe limited to 0x30, 0x31, 0x32, or 0x33)
+	 *				    Offset 0x1a02d .. 0x1a037 = date/time values.
+	 *				    Offset 0x1a056 .. 0x1a05d = 8 bytes serial number / machine ID.
+	 *  0x005f0000 - ...            ???
+	 *  0x005f6800 - ...		PowerVR2 DMA registers
+	 *  0x005f6900 - ...		ASIC registers
+	 *  0x005f6c00 - ...		Maple registers (controller ports)
+	 *  0x005f7000 - ...		GDROM registers
+	 *  0x005f7400 - ...		(G2 External DMA registers? Or GDROM?)
+	 *  0x005f74e4 - ...		GDROM re-enable disabled drive (?)
+	 *  0x005f7800 - ...		G2 External DMA registers
+	 *  0x005f7c00 - ...		DMA (?) for some device (PVR related?)
+	 *  0x005f8000 - 0x005f9fff	PVR registers (graphics)
+	 *  0x00600000 - 0x006007ff	G2 bus: Modem
+	 *  0x00600400 - 0x0060047f	G2 bus: LAN Adapter (MB86967) registers?
+	 *  0x00620000 - 0x00623fff	G2 bus: Expansion port?
+	 *  0x00606900 - ...		???
+	 *  0x00700000 - ...		SPU registers (sound)
+	 *  0x00702800 - 0x007028ff	???
+	 *  0x00702c00 -		Cable select and AICA (?) (*3)
+	 *  0x00703xxx - ...		AICA something
+	 *  0x00710000 - 0x00710007	RTC registers
+	 *  0x00800000 - 0x009fffff	AICA (Sound) RAM (2 MB) (*4)
+	 *  0x01000000 - 0x01ffffff	G2 bus or Parallel port registers?
+	 *  0x02000000 - ...		CD-ROM port registers
+	 *  0x03000000 - 0x03ffffff	G2 bus (?)
+	 *  0x04000000 - 0x047fffff	Video RAM (*)     (64-bit)
+	 *  0x05000000 - 0x057fffff	Video RAM (8 MB)  (32-bit)
+	 *  0x06000000 - 0x067fffff	Video RAM (*)     (64-bit) (copy)
+	 *  0x07000000 - 0x077fffff	Video RAM (8 MB)  (32-bit) (copy)
+	 *  0x0c000000 - 0x0cffffff	RAM (16 MB)
+	 *  0x0e000000 - 0x0effffff	Copy of RAM? (*2)
+	 *  0x10000000 - 0x107fffff	Tile Accelerator: command area
+	 *  0x10800000 - 0x10ffffff	Tile Accelerator: YUV data
+	 *  0x11000000 - 0x11ffffff	Tile Accelerator: Texture data
+	 *  0x14000000 - 0x17ffffff	G2 bus (?)
+	 *
+	 *  (*1) = with banks 0 and 1 switched; 64-bit read/write access...
+	 *  (*2) The "luftvarg" 4KB intro uses memory at paddr 0x0ef00000...
+	 *  (*3) = See VOUTC in Linux' drivers/video/pvr2fb.c.
+	 *  (*4) = It seems that ARM machine code is placed here.
+	 */
+
+	dev_ram_init(machine, 0x00000000, 2 * 1024 * 1024,
+	    DEV_RAM_RAM /* | DEV_RAM_TRACE_ALL_ACCESSES */, 0x0, "bootrom");
+
+	dev_ram_init(machine, 0x00200000, 128 * 1024,
+	    DEV_RAM_RAM /* | DEV_RAM_TRACE_ALL_ACCESSES */, 0x0, "flash");
+
+	dev_ram_init(machine, 0x00600004, 4, DEV_RAM_RAM, 0, NULL);
+	dev_ram_init(machine, 0x00700000, 0x27ff, DEV_RAM_RAM, 0, NULL);
+	dev_ram_init(machine, 0x00702800, 256, DEV_RAM_RAM, 0, NULL);
+	dev_ram_init(machine, 0x00702c00, 4, DEV_RAM_RAM, 0, NULL);
+	dev_ram_init(machine, 0x00703000, 0x1fff, DEV_RAM_RAM, 0, NULL);
+
+	/*  Sound RAM:  */
+	dev_ram_init(machine, 0x00800000, 2 * 1048576, DEV_RAM_RAM, 0, "sound_ram");
+
+	/*
+	 *  HACK!  TODO: Remove this device at 0x00a00000 once NetBSD has
+	 *  been fixed to not clear 6 MB beyound the sound RAM area.
+	 */
+	dev_ram_init(machine, 0x00a00000, 6 * 1048576, DEV_RAM_RAM, 0, "hack_for_netbsd");
+
+	/*  RAM:  */
+	dev_ram_init(machine, 0x0c000000, 16 * 1048576, DEV_RAM_RAM, 0x0, NULL);
+
+	/*  Image of RAM:  */
+	dev_ram_init(machine, 0x0e000000, 16 * 1048576, DEV_RAM_MIRROR
+		| DEV_RAM_MIGHT_POINT_TO_DEVICES, 0x0c000000, "ram_mirror");
+
+	device_add(machine, "pvr");
+/*	device_add(machine, "mb8696x addr=0x600400 addr_mult=4");  */
+	device_add(machine, "dreamcast_asic");
+	device_add(machine, "dreamcast_g2");
+	device_add(machine, "dreamcast_gdrom");
+	device_add(machine, "dreamcast_maple");
+	device_add(machine, "dreamcast_rtc");
+
+	machine_add_devices_as_symbols(machine, 0x80000000U);
+	machine_add_devices_as_symbols(machine, 0xa0000000U);
+
+	if (!machine->prom_emulation)
+		return;
+
+	dreamcast_machine_setup(machine);
+}
+
+
+MACHINE_DEFAULT_CPU(dreamcast)
+{
+	// Hitachi SH4, 200 MHz.  (Or probably an "SH4a".)
+	machine->cpu_name = strdup("SH7750");
+}
+
+
+MACHINE_DEFAULT_RAM(dreamcast)
+{
+	// Note: This is the size of the boot ROM area, since the
+	// Dreamcast's RAM isn't located at physical address zero.
+	machine->physical_ram_in_mb = 2;
+}
+
+
+MACHINE_REGISTER(dreamcast)
+{
+	MR_DEFAULT(dreamcast, "Dreamcast", MACHINE_DREAMCAST);
+	me->set_default_ram = machine_default_ram_dreamcast;
+	machine_entry_add_alias(me, "dreamcast");
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_dreamcast.cc gxemul-0.7.0+dfsg/src/machines/machine_dreamcast.cc
--- gxemul-0.6.2/src/machines/machine_dreamcast.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_dreamcast.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,213 +0,0 @@
-/*
- *  Copyright (C) 2006-2014  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: SEGA Dreamcast
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sstream>
-#include <string>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-using namespace std;
-
-
-MACHINE_SETUP(dreamcast)
-{
-	machine->machine_name = strdup("Dreamcast");
-
-	if (machine->emulated_hz == 0)
-		machine->emulated_hz = 200000000;
-
-	/*  50 MHz SH4 PCLOCK:  */
-	machine->cpus[0]->cd.sh.pclock = 50000000;
-
-	if (!machine->x11_md.in_use)
-		fprintf(stderr, "-------------------------------------"
-		    "------------------------------------------\n"
-		    "\n  WARNING!  You are emulating a Dreamcast without -X."
-		    "\n            You will miss graphical output!\n\n"
-		    "-------------------------------------"
-		    "------------------------------------------\n");
-
-	/*
-	 *  Physical address layout on the Dreamcast, according to a
-	 *  combination of sources:  NetBSD sources, KallistiOS sources,
-	 *  http://www.boob.co.uk/docs/Dreamcast_memory.txt, and
-	 *  http://www.ludd.luth.se/~jlo/dc/memory.txt, and possibly some
-	 *  others:
-	 *
-	 *  0x00000000 - 0x001fffff	Boot ROM (2 MB)
-	 *  0x00200000 - 0x0021ffff	Flash (128 KB) (perhaps multiple images afterwards?)
-	 *				The bytes read by the Dreamcast PROM during
-	 *				boot are:
-	 *				    Offset 0x1a000 .. 0x1a004 = 5 bytes debug/startup state?
-	 *					hex digits (maybe limited to 0x30, 0x31, 0x32, or 0x33)
-	 *				    Offset 0x1a02d .. 0x1a037 = date/time values.
-	 *				    Offset 0x1a056 .. 0x1a05d = 8 bytes serial number / machine ID.
-	 *  0x005f0000 - ...            ???
-	 *  0x005f6800 - ...		PowerVR2 DMA registers
-	 *  0x005f6900 - ...		ASIC registers
-	 *  0x005f6c00 - ...		Maple registers (controller ports)
-	 *  0x005f7000 - ...		GDROM registers
-	 *  0x005f7400 - ...		(G2 External DMA registers? Or GDROM?)
-	 *  0x005f74e4 - ...		GDROM re-enable disabled drive (?)
-	 *  0x005f7800 - ...		G2 External DMA registers
-	 *  0x005f7c00 - ...		DMA (?) for some device (PVR related?)
-	 *  0x005f8000 - 0x005f9fff	PVR registers (graphics)
-	 *  0x00600000 - 0x006007ff	G2 bus: Modem
-	 *  0x00600400 - 0x0060047f	G2 bus: LAN Adapter (MB86967) registers?
-	 *  0x00620000 - 0x00623fff	G2 bus: Expansion port?
-	 *  0x00606900 - ...		???
-	 *  0x00700000 - ...		SPU registers (sound)
-	 *  0x00702800 - 0x007028ff	???
-	 *  0x00702c00 -		Cable select and AICA (?) (*3)
-	 *  0x00703xxx - ...		AICA something
-	 *  0x00710000 - 0x00710007	RTC registers
-	 *  0x00800000 - 0x009fffff	AICA (Sound) RAM (2 MB) (*4)
-	 *  0x01000000 - 0x01ffffff	G2 bus or Parallel port registers?
-	 *  0x02000000 - ...		CD-ROM port registers
-	 *  0x03000000 - 0x03ffffff	G2 bus (?)
-	 *  0x04000000 - 0x047fffff	Video RAM (*)     (64-bit)
-	 *  0x05000000 - 0x057fffff	Video RAM (8 MB)  (32-bit)
-	 *  0x06000000 - 0x067fffff	Video RAM (*)     (64-bit) (copy)
-	 *  0x07000000 - 0x077fffff	Video RAM (8 MB)  (32-bit) (copy)
-	 *  0x0c000000 - 0x0cffffff	RAM (16 MB)
-	 *  0x0e000000 - 0x0effffff	Copy of RAM? (*2)
-	 *  0x10000000 - 0x107fffff	Tile Accelerator: command area
-	 *  0x10800000 - 0x10ffffff	Tile Accelerator: YUV data
-	 *  0x11000000 - 0x11ffffff	Tile Accelerator: Texture data
-	 *  0x14000000 - 0x17ffffff	G2 bus (?)
-	 *
-	 *  (*1) = with banks 0 and 1 switched; 64-bit read/write access...
-	 *  (*2) The "luftvarg" 4KB intro uses memory at paddr 0x0ef00000...
-	 *  (*3) = See VOUTC in Linux' drivers/video/pvr2fb.c.
-	 *  (*4) = It seems that ARM machine code is placed here.
-	 */
-
-	dev_ram_init(machine, 0x00000000, 2 * 1024 * 1024,
-	    DEV_RAM_RAM /* | DEV_RAM_TRACE_ALL_ACCESSES */, 0x0, "bootrom");
-
-	dev_ram_init(machine, 0x00200000, 128 * 1024,
-	    DEV_RAM_RAM /* | DEV_RAM_TRACE_ALL_ACCESSES */, 0x0, "flash");
-
-	dev_ram_init(machine, 0x00600004, 4, DEV_RAM_RAM, 0);
-	dev_ram_init(machine, 0x00700000, 0x27ff, DEV_RAM_RAM, 0);
-	dev_ram_init(machine, 0x00702800, 256, DEV_RAM_RAM, 0);
-	dev_ram_init(machine, 0x00702c00, 4, DEV_RAM_RAM, 0);
-	dev_ram_init(machine, 0x00703000, 0x1fff, DEV_RAM_RAM, 0);
-
-	/*  Sound RAM:  */
-	dev_ram_init(machine, 0x00800000, 2 * 1048576, DEV_RAM_RAM, 0, "sound_ram");
-
-	/*
-	 *  HACK!  TODO: Remove this device at 0x00a00000 once NetBSD has
-	 *  been fixed to not clear 6 MB beyound the sound RAM area.
-	 */
-	dev_ram_init(machine, 0x00a00000, 6 * 1048576, DEV_RAM_RAM, 0, "hack_for_netbsd");
-
-	/*  RAM:  */
-	dev_ram_init(machine, 0x0c000000, 16 * 1048576, DEV_RAM_RAM, 0x0);
-
-	/*  Image of RAM:  */
-	dev_ram_init(machine, 0x0e000000, 16 * 1048576, DEV_RAM_MIRROR
-		| DEV_RAM_MIGHT_POINT_TO_DEVICES, 0x0c000000, "ram_mirror");
-
-	device_add(machine, "pvr");
-/*	device_add(machine, "mb8696x addr=0x600400 addr_mult=4");  */
-	device_add(machine, "dreamcast_asic");
-	device_add(machine, "dreamcast_g2");
-	device_add(machine, "dreamcast_gdrom");
-	device_add(machine, "dreamcast_maple");
-	device_add(machine, "dreamcast_rtc");
-
-	// Add devices as symbols, so that they show up in disassembly/runtime.
-	struct memory *mem = cpu->mem;
-	for (int i = 0; i < mem->n_mmapped_devices; i++) {
-		// Add everything which is not called "ram" (for now).
-		if (strcmp(mem->devices[i].name, "ram") == 0) {
-			continue;
-		}
-		
-		stringstream ss;
-		ss.flags(ios::hex);
-		ss << "(" << mem->devices[i].name << "@0x" << mem->devices[i].baseaddr << ")";
-		string name = ss.str();		
-
-		add_symbol_name(
-		    &machine->symbol_context,
-		    mem->devices[i].baseaddr | 0x80000000U,
-		    mem->devices[i].length,
-		    name.c_str(),
-		    0, 0);
-
-		add_symbol_name(
-		    &machine->symbol_context,
-		    mem->devices[i].baseaddr | 0xa0000000U,
-		    mem->devices[i].length,
-		    name.c_str(),
-		    0, 0);
-	}
-
-	if (!machine->prom_emulation)
-		return;
-
-	dreamcast_machine_setup(machine);
-}
-
-
-MACHINE_DEFAULT_CPU(dreamcast)
-{
-	// Hitachi SH4, 200 MHz.  (Or probably an "SH4a".)
-	machine->cpu_name = strdup("SH7750");
-}
-
-
-MACHINE_DEFAULT_RAM(dreamcast)
-{
-	// Note: This is the size of the boot ROM area, since the
-	// Dreamcast's RAM isn't located at physical address zero.
-	machine->physical_ram_in_mb = 2;
-}
-
-
-MACHINE_REGISTER(dreamcast)
-{
-	MR_DEFAULT(dreamcast, "Dreamcast", ARCH_SH, MACHINE_DREAMCAST);
-	me->set_default_ram = machine_default_ram_dreamcast;
-	machine_entry_add_alias(me, "dreamcast");
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_evbmips.c gxemul-0.7.0+dfsg/src/machines/machine_evbmips.c
--- gxemul-0.6.2/src/machines/machine_evbmips.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_evbmips.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,195 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: MIPS evaluation boards (e.g. Malta)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_isa.h"
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/maltareg.h"
+
+
+MACHINE_SETUP(evbmips)
+{
+	char tmpstr[1000], tmpstr2[1000];
+	struct pci_data *pci_data;
+	int i;
+
+	/*  See http://www.netbsd.org/ports/evbmips/ for more info.  */
+
+	switch (machine->machine_subtype) {
+
+	case MACHINE_EVBMIPS_MALTA:
+	case MACHINE_EVBMIPS_MALTA_BE:
+		if (machine->emulated_hz == 0)
+			machine->emulated_hz = 33000000;
+		cpu->byte_order = EMUL_LITTLE_ENDIAN;
+		machine->machine_name = strdup("MALTA (evbmips, little endian)");
+
+		if (machine->machine_subtype == MACHINE_EVBMIPS_MALTA_BE) {
+			machine->machine_name = strdup("MALTA (evbmips, big endian)");
+			cpu->byte_order = EMUL_BIG_ENDIAN;
+		}
+
+		/*  ISA bus at MIPS irq 2:  */
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2",
+		    machine->path, machine->bootstrap_cpu);
+		bus_isa_init(machine, tmpstr, 0, 0x18000000, 0x10000000);
+
+		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].4 "
+		    "addr=0x%x name2=tty2 in_use=0", machine->path,
+		    machine->bootstrap_cpu, MALTA_CBUSUART);
+		device_add(machine, tmpstr);
+
+		/*  Add a GT controller; timer interrupts at ISA irq 9:  */
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.isa.9",
+		    machine->path, machine->bootstrap_cpu);
+		snprintf(tmpstr2, sizeof(tmpstr2), "%s.cpu[%i].2",
+		    machine->path, machine->bootstrap_cpu);
+		pci_data = dev_gt_init(machine, machine->memory, 0x1be00000,
+		    tmpstr, tmpstr2, 120);
+
+		if (machine->x11_md.in_use) {
+			if (strlen(machine->boot_string_argument) < 3) {
+				fatal("WARNING: remember to use  -o 'console="
+				    "tty0'  if you are emulating Linux. (Not"
+				    " needed for NetBSD.)\n");
+			}
+			bus_pci_add(machine, pci_data, machine->memory,
+			    0, 8, 0, "s3_virge");
+		}
+
+		bus_pci_add(machine, pci_data, machine->memory,
+		    0, 10, 0, "piix4_isa");
+		bus_pci_add(machine, pci_data, machine->memory,
+		    0, 10, 1, "piix4_ide");
+
+		/*  pcn: Not yet, since it is just a bogus device, so far.  */
+		/*  bus_pci_add(machine, pci_data, machine->memory,
+		    0, 11, 0, "pcn");  */
+
+		device_add(machine, "malta_lcd addr=0x1f000400");
+		break;
+
+	default:fatal("Unimplemented EVBMIPS model.\n");
+		exit(1);
+	}
+
+	if (!machine->prom_emulation)
+		return;
+
+
+	/*  NetBSD/evbmips wants these: (at least for Malta)  */
+
+	/*  a0 = argc  */
+	cpu->cd.mips.gpr[MIPS_GPR_A0] = 2;
+
+	/*  a1 = argv  */
+	cpu->cd.mips.gpr[MIPS_GPR_A1] = (int32_t)0x9fc01000;
+	store_32bit_word(cpu, (int32_t)0x9fc01000, 0x9fc01040);
+	store_32bit_word(cpu, (int32_t)0x9fc01004, 0x9fc01200);
+	store_32bit_word(cpu, (int32_t)0x9fc01008, 0);
+
+	machine->bootstr = strdup(machine->boot_kernel_filename);
+	machine->bootarg = strdup(machine->boot_string_argument);
+	store_string(cpu, (int32_t)0x9fc01040, machine->bootstr);
+	store_string(cpu, (int32_t)0x9fc01200, machine->bootarg);
+
+	/*  a2 = (yamon_env_var *)envp  */
+	cpu->cd.mips.gpr[MIPS_GPR_A2] = (int32_t)0x9fc01800;
+
+	yamon_machine_setup(machine, cpu->cd.mips.gpr[MIPS_GPR_A2]);
+
+	/*  a3 = memsize  */
+	cpu->cd.mips.gpr[MIPS_GPR_A3] = machine->physical_ram_in_mb * 1048576;
+	/*  Hm. Linux ignores a3.  */
+
+	/*  Set the Core ID. See maltareg.h for more info.  */
+	store_32bit_word(cpu, (int32_t)(0x80000000 + MALTA_REVISION),
+	    (1 << 10) + 0x26);
+
+	/*  Call vectors at 0x9fc005xx:  */
+	for (i=0; i<0x100; i+=4)
+		store_32bit_word(cpu, (int64_t)(int32_t)0x9fc00500 + i,
+		    (int64_t)(int32_t)0x9fc00800 + i);
+
+	/*  "Magic trap" PROM instructions at 0x9fc008xx:  */
+	for (i=0; i<0x100; i+=4)
+		store_32bit_word(cpu, (int64_t)(int32_t)0x9fc00800 + i,
+		    0x00c0de0c);
+}
+
+
+MACHINE_DEFAULT_CPU(evbmips)
+{
+	switch (machine->machine_subtype) {
+
+	case MACHINE_EVBMIPS_MALTA:
+	case MACHINE_EVBMIPS_MALTA_BE:
+		/*  5Kc = MIPS64 rev 1, 5KE = MIPS64 rev 2  */
+		machine->cpu_name = strdup("5Kc");
+		break;
+
+	default:fatal("Unimplemented evbmips subtype.\n");
+		exit(1);
+	}
+}
+
+
+MACHINE_DEFAULT_RAM(evbmips)
+{
+	machine->physical_ram_in_mb = 128;
+}
+
+
+MACHINE_REGISTER(evbmips)
+{
+	MR_DEFAULT(evbmips, "MIPS evaluation boards (evbmips)",
+	    MACHINE_EVBMIPS);
+
+	machine_entry_add_alias(me, "evbmips");
+
+	machine_entry_add_subtype(me, "Malta", MACHINE_EVBMIPS_MALTA,
+	    "malta", NULL);
+
+	machine_entry_add_subtype(me, "Malta (Big-Endian)",
+	    MACHINE_EVBMIPS_MALTA_BE, "maltabe", NULL);
+
+	me->set_default_ram = machine_default_ram_evbmips;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_evbmips.cc gxemul-0.7.0+dfsg/src/machines/machine_evbmips.cc
--- gxemul-0.6.2/src/machines/machine_evbmips.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_evbmips.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,195 +0,0 @@
-/*
- *  Copyright (C) 2005-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: MIPS evaluation boards (e.g. Malta)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_isa.h"
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/maltareg.h"
-
-
-MACHINE_SETUP(evbmips)
-{
-	char tmpstr[1000], tmpstr2[1000];
-	struct pci_data *pci_data;
-	int i;
-
-	/*  See http://www.netbsd.org/ports/evbmips/ for more info.  */
-
-	switch (machine->machine_subtype) {
-
-	case MACHINE_EVBMIPS_MALTA:
-	case MACHINE_EVBMIPS_MALTA_BE:
-		if (machine->emulated_hz == 0)
-			machine->emulated_hz = 33000000;
-		cpu->byte_order = EMUL_LITTLE_ENDIAN;
-		machine->machine_name = strdup("MALTA (evbmips, little endian)");
-
-		if (machine->machine_subtype == MACHINE_EVBMIPS_MALTA_BE) {
-			machine->machine_name = strdup("MALTA (evbmips, big endian)");
-			cpu->byte_order = EMUL_BIG_ENDIAN;
-		}
-
-		/*  ISA bus at MIPS irq 2:  */
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2",
-		    machine->path, machine->bootstrap_cpu);
-		bus_isa_init(machine, tmpstr, 0, 0x18000000, 0x10000000);
-
-		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].4 "
-		    "addr=0x%x name2=tty2 in_use=0", machine->path,
-		    machine->bootstrap_cpu, MALTA_CBUSUART);
-		device_add(machine, tmpstr);
-
-		/*  Add a GT controller; timer interrupts at ISA irq 9:  */
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.isa.9",
-		    machine->path, machine->bootstrap_cpu);
-		snprintf(tmpstr2, sizeof(tmpstr2), "%s.cpu[%i].2",
-		    machine->path, machine->bootstrap_cpu);
-		pci_data = dev_gt_init(machine, machine->memory, 0x1be00000,
-		    tmpstr, tmpstr2, 120);
-
-		if (machine->x11_md.in_use) {
-			if (strlen(machine->boot_string_argument) < 3) {
-				fatal("WARNING: remember to use  -o 'console="
-				    "tty0'  if you are emulating Linux. (Not"
-				    " needed for NetBSD.)\n");
-			}
-			bus_pci_add(machine, pci_data, machine->memory,
-			    0, 8, 0, "s3_virge");
-		}
-
-		bus_pci_add(machine, pci_data, machine->memory,
-		    0, 10, 0, "piix4_isa");
-		bus_pci_add(machine, pci_data, machine->memory,
-		    0, 10, 1, "piix4_ide");
-
-		/*  pcn: Not yet, since it is just a bogus device, so far.  */
-		/*  bus_pci_add(machine, pci_data, machine->memory,
-		    0, 11, 0, "pcn");  */
-
-		device_add(machine, "malta_lcd addr=0x1f000400");
-		break;
-
-	default:fatal("Unimplemented EVBMIPS model.\n");
-		exit(1);
-	}
-
-	if (!machine->prom_emulation)
-		return;
-
-
-	/*  NetBSD/evbmips wants these: (at least for Malta)  */
-
-	/*  a0 = argc  */
-	cpu->cd.mips.gpr[MIPS_GPR_A0] = 2;
-
-	/*  a1 = argv  */
-	cpu->cd.mips.gpr[MIPS_GPR_A1] = (int32_t)0x9fc01000;
-	store_32bit_word(cpu, (int32_t)0x9fc01000, 0x9fc01040);
-	store_32bit_word(cpu, (int32_t)0x9fc01004, 0x9fc01200);
-	store_32bit_word(cpu, (int32_t)0x9fc01008, 0);
-
-	machine->bootstr = strdup(machine->boot_kernel_filename);
-	machine->bootarg = strdup(machine->boot_string_argument);
-	store_string(cpu, (int32_t)0x9fc01040, machine->bootstr);
-	store_string(cpu, (int32_t)0x9fc01200, machine->bootarg);
-
-	/*  a2 = (yamon_env_var *)envp  */
-	cpu->cd.mips.gpr[MIPS_GPR_A2] = (int32_t)0x9fc01800;
-
-	yamon_machine_setup(machine, cpu->cd.mips.gpr[MIPS_GPR_A2]);
-
-	/*  a3 = memsize  */
-	cpu->cd.mips.gpr[MIPS_GPR_A3] = machine->physical_ram_in_mb * 1048576;
-	/*  Hm. Linux ignores a3.  */
-
-	/*  Set the Core ID. See maltareg.h for more info.  */
-	store_32bit_word(cpu, (int32_t)(0x80000000 + MALTA_REVISION),
-	    (1 << 10) + 0x26);
-
-	/*  Call vectors at 0x9fc005xx:  */
-	for (i=0; i<0x100; i+=4)
-		store_32bit_word(cpu, (int64_t)(int32_t)0x9fc00500 + i,
-		    (int64_t)(int32_t)0x9fc00800 + i);
-
-	/*  "Magic trap" PROM instructions at 0x9fc008xx:  */
-	for (i=0; i<0x100; i+=4)
-		store_32bit_word(cpu, (int64_t)(int32_t)0x9fc00800 + i,
-		    0x00c0de0c);
-}
-
-
-MACHINE_DEFAULT_CPU(evbmips)
-{
-	switch (machine->machine_subtype) {
-
-	case MACHINE_EVBMIPS_MALTA:
-	case MACHINE_EVBMIPS_MALTA_BE:
-		/*  5Kc = MIPS64 rev 1, 5KE = MIPS64 rev 2  */
-		machine->cpu_name = strdup("5Kc");
-		break;
-
-	default:fatal("Unimplemented evbmips subtype.\n");
-		exit(1);
-	}
-}
-
-
-MACHINE_DEFAULT_RAM(evbmips)
-{
-	machine->physical_ram_in_mb = 128;
-}
-
-
-MACHINE_REGISTER(evbmips)
-{
-	MR_DEFAULT(evbmips, "MIPS evaluation boards (evbmips)",
-	    ARCH_MIPS, MACHINE_EVBMIPS);
-
-	machine_entry_add_alias(me, "evbmips");
-
-	machine_entry_add_subtype(me, "Malta", MACHINE_EVBMIPS_MALTA,
-	    "malta", NULL);
-
-	machine_entry_add_subtype(me, "Malta (Big-Endian)",
-	    MACHINE_EVBMIPS_MALTA_BE, "maltabe", NULL);
-
-	me->set_default_ram = machine_default_ram_evbmips;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_hp700rx.c gxemul-0.7.0+dfsg/src/machines/machine_hp700rx.c
--- gxemul-0.6.2/src/machines/machine_hp700rx.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_hp700rx.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,112 @@
+/*
+ *  Copyright (C) 2018-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: HP 700/RX machine
+ *
+ *  This is for experiments with the original firmware from my HP 700/RX
+ *  X-terminal, a diskless i960CA-based machine.
+ *
+ *  As a starting point:
+ *
+ *	gxemul -V -E hp700rx 0xfff80000:0:0xfff8b000:hp700rx-rom.bin
+ *
+ *  Experiments on my machine has resulted in the following approximate
+ *  memory map:
+ *
+ *  0x00000000 .. 0x000003ff	1 KB on-chip RAM (i960CA-specific).
+ *  0x3xxxxxxx			Base RAM, 2 MB in size, repeated.
+ *  0x40000000			Extended RAM, 8 MB, repeated (I think).
+ *  0x41000000			Video RAM, 2 MB. But possibly interleaved/paged.
+ *  0xc0000000			Devices (accessed using 8-bit loads and stores?)
+ *	0xc0000800 .. 0xc0000803
+ *	0xc0001000 .. 0xc0001003
+ *	0xc0001800 .. 0xc0001803
+ *	0xc0002000 .. 0xc0002001
+ *	0xc0003000 && 0xc0003002			  
+ *	0xc0003800
+ *	0xc0004000
+ *	0xc0004800 .. 0xc0004803
+ *	0xc0005800 .. 0xc000580f
+ *  0xfff80000			ROM, 512 KB.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+MACHINE_SETUP(hp700rx)
+{
+	machine->machine_name = strdup("HP 700/RX");
+	machine->cpus[0]->byte_order = EMUL_LITTLE_ENDIAN;
+
+	dev_ram_init(machine, 0x30000000, 2 * 1048576, DEV_RAM_RAM, 0, "baseram");
+
+	// TODO: repeats of Base RAM
+
+	dev_ram_init(machine, 0x40000000, 8 * 1048576, DEV_RAM_RAM, 0, "ram_exp");
+
+	// TODO: repeats of Expansion RAM
+
+	// TODO: This is actually framebuffer memory.
+	dev_ram_init(machine, 0x41000000, 2 * 1048576, DEV_RAM_RAM, 0, "vram");
+
+	// TODO: Not RAM, but ROM.
+	dev_ram_init(machine, 0xfff80000, 512 * 1024, DEV_RAM_RAM, 0, "rom");
+
+	machine_add_devices_as_symbols(machine, 0);
+}
+
+
+MACHINE_DEFAULT_CPU(hp700rx)
+{
+	machine->cpu_name = strdup("i960CA");
+}
+
+
+MACHINE_DEFAULT_RAM(hp700rx)
+{
+	// TODO. Just 1 KB at offset 0. The "base" and "expanded" RAM are
+	// at higher addresses.
+	machine->physical_ram_in_mb = 1;
+}
+
+
+MACHINE_REGISTER(hp700rx)
+{
+	MR_DEFAULT(hp700rx, "hp700rx", MACHINE_HP700RX);
+	machine_entry_add_alias(me, "hp700rx");
+	me->set_default_ram = machine_default_ram_hp700rx;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_hpcarm.c gxemul-0.7.0+dfsg/src/machines/machine_hpcarm.c
--- gxemul-0.6.2/src/machines/machine_hpcarm.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_hpcarm.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,232 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Handheld ARM-based machines
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/hpc_bootinfo.h"
+#include "thirdparty/vripreg.h"
+
+
+MACHINE_SETUP(hpcarm)
+{
+	struct hpc_bootinfo hpc_bootinfo;
+	int hpc_platid_flags = 0, hpc_platid_cpu_submodel = 0,
+	    hpc_platid_cpu_model = 0, hpc_platid_cpu_series = 0,
+	    hpc_platid_cpu_arch = 0,
+	    hpc_platid_submodel = 0, hpc_platid_model = 0,
+	    hpc_platid_series = 0, hpc_platid_vendor = 0;
+	uint64_t hpc_fb_addr = 0;
+	int hpc_fb_bits = 0, hpc_fb_encoding = 0;
+	int hpc_fb_xsize = 0;
+	int hpc_fb_ysize = 0;
+	int hpc_fb_xsize_mem = 0;
+	int hpc_fb_ysize_mem = 0;
+
+	memset(&hpc_bootinfo, 0, sizeof(hpc_bootinfo));
+
+	cpu->byte_order = EMUL_LITTLE_ENDIAN;
+
+	switch (machine->machine_subtype) {
+
+	case MACHINE_HPCARM_IPAQ:
+		/*  SA-1110 206MHz  */
+		machine->machine_name = strdup("Compaq iPAQ H3600");
+		hpc_fb_addr = 0x48200000;	/*  TODO  */
+		hpc_fb_xsize = 240;
+		hpc_fb_ysize = 320;
+		hpc_fb_xsize_mem = 256;
+		hpc_fb_ysize_mem = 320;
+		hpc_fb_bits = 15;
+		hpc_fb_encoding = BIFB_D16_0000;
+		hpc_platid_cpu_arch = 3;	/*  ARM  */
+		hpc_platid_cpu_series = 1;	/*  StrongARM  */
+		hpc_platid_cpu_model = 2;	/*  SA-1110  */
+		hpc_platid_cpu_submodel = 0;
+		hpc_platid_vendor = 7;		/*  Compaq  */
+		hpc_platid_series = 4;		/*  IPAQ  */
+		hpc_platid_model = 2;		/*  H36xx  */
+		hpc_platid_submodel = 1;	/*  H3600  */
+		break;
+
+	case MACHINE_HPCARM_JORNADA720:
+	case MACHINE_HPCARM_JORNADA728:
+		/*  SA-1110 206MHz  */
+		machine->machine_name =
+		    ((machine->machine_subtype == MACHINE_HPCARM_JORNADA720) ?
+		    "Jornada 720" : "Jornada 728");
+		hpc_fb_addr = 0x48200000;
+		hpc_fb_xsize = 640;
+		hpc_fb_ysize = 240;
+		hpc_fb_xsize_mem = 640;
+		hpc_fb_ysize_mem = 240;
+		hpc_fb_bits = 16;
+		hpc_fb_encoding = BIFB_D16_0000;
+		hpc_platid_cpu_arch = 3;	/*  ARM  */
+		hpc_platid_cpu_series = 1;	/*  StrongARM  */
+		hpc_platid_cpu_model = 2;	/*  SA-1110  */
+		hpc_platid_cpu_submodel = 0;
+		hpc_platid_vendor = 11;		/*  HP  */
+		hpc_platid_series = 2;		/*  Jornada  */
+		hpc_platid_model = 2;		/*  7xx  */
+		hpc_platid_submodel = 1;	/*  720  */
+		break;
+
+	default:printf("Unimplemented hpcarm machine number.\n");
+		exit(1);
+	}
+
+	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.platid_cpu,
+	      (hpc_platid_cpu_arch << 26) + (hpc_platid_cpu_series << 20)
+	    + (hpc_platid_cpu_model << 14) + (hpc_platid_cpu_submodel <<  8)
+	    + hpc_platid_flags);
+	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.
+	    platid_machine,(hpc_platid_vendor << 22) + (hpc_platid_series << 16)
+	    + (hpc_platid_model <<  8) + hpc_platid_submodel);
+
+	/*  Physical RAM at 0xc0000000:  */
+	dev_ram_init(machine, 0xc0000000, 0x20000000,
+	    DEV_RAM_MIRROR, 0x0, NULL);
+
+	/*  Cache flush region:  */
+	dev_ram_init(machine, 0xe0000000, 0x10000, DEV_RAM_RAM, 0x0, NULL);
+
+	if (hpc_fb_addr != 0) {
+		dev_fb_init(machine, machine->memory, hpc_fb_addr, VFB_HPC,
+		    hpc_fb_xsize, hpc_fb_ysize,
+		    hpc_fb_xsize_mem, hpc_fb_ysize_mem,
+		    hpc_fb_bits, machine->machine_name);
+	}
+
+	if (!machine->prom_emulation)
+		return;
+
+
+	/*  NetBSD/hpcarm and possibly others expects the following:  */
+
+	cpu->cd.arm.r[0] = 1;	/*  argc  */
+	cpu->cd.arm.r[1] = machine->physical_ram_in_mb * 1048576 - 512;	/*argv*/
+	cpu->cd.arm.r[2] = machine->physical_ram_in_mb * 1048576 - 256;
+		/*  r[2] = ptr to hpc_bootinfo  */
+
+	machine->bootstr = machine->boot_kernel_filename;
+	store_32bit_word(cpu, machine->physical_ram_in_mb * 1048576 - 512,
+	    machine->physical_ram_in_mb * 1048576 - 512 + 16);
+	store_32bit_word(cpu, machine->physical_ram_in_mb * 1048576 - 512 +4,0);
+	store_string(cpu, machine->physical_ram_in_mb * 1048576 - 512 + 16,
+	    machine->bootstr);
+
+	if (machine->boot_string_argument[0]) {
+		cpu->cd.arm.r[0] ++;	/*  argc  */
+
+		store_32bit_word(cpu, machine->physical_ram_in_mb * 1048576 -
+		    512 + 4, machine->physical_ram_in_mb * 1048576 - 512 + 64);
+		store_32bit_word(cpu, machine->physical_ram_in_mb * 1048576 -
+		    512 + 8, 0);
+
+		store_string(cpu, machine->physical_ram_in_mb * 1048576 - 512
+		    + 64, machine->boot_string_argument);
+
+		machine->bootarg = machine->boot_string_argument;
+	}
+
+	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.length,
+	    sizeof(hpc_bootinfo));
+	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.magic,
+	    HPC_BOOTINFO_MAGIC);
+	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_addr,
+	    hpc_fb_addr);
+	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.
+	    fb_line_bytes, hpc_fb_xsize_mem * (((hpc_fb_bits-1)|7)+1) / 8);
+	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_width,
+	    hpc_fb_xsize);
+	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_height,
+	    hpc_fb_ysize);
+	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_type,
+	    hpc_fb_encoding);
+	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.bi_cnuse,
+	    machine->x11_md.in_use? BI_CNUSE_BUILTIN : BI_CNUSE_SERIAL);
+
+	store_32bit_word_in_host(cpu,(unsigned char *)&hpc_bootinfo.timezone,0);
+	store_buf(cpu, machine->physical_ram_in_mb * 1048576 - 256,
+	    (char *)&hpc_bootinfo, sizeof(hpc_bootinfo));
+
+	/*  TODO: What is a good default stack pointer?  */
+	/*  I.e. what does hpcboot.exe for NetBSD/hpcarm usually use?  */
+	cpu->cd.arm.r[ARM_SP] = 0xc02dfff0;
+}
+
+
+MACHINE_DEFAULT_CPU(hpcarm)
+{
+	machine->cpu_name = strdup("SA1110");
+}
+
+
+MACHINE_DEFAULT_RAM(hpcarm)
+{
+	switch (machine->machine_subtype) {
+	case MACHINE_HPCARM_JORNADA728:
+		/*  720 has 32 MB, 728 has 64 MB.  */
+		machine->physical_ram_in_mb = 64;
+		break;
+	default:
+		/*  Most have 32 MB by default.  */
+		machine->physical_ram_in_mb = 32;
+	}
+}
+
+
+MACHINE_REGISTER(hpcarm)
+{
+	MR_DEFAULT(hpcarm, "Handhelp ARM (HPCarm)", MACHINE_HPCARM);
+
+	machine_entry_add_alias(me, "hpcarm");
+
+	machine_entry_add_subtype(me, "Ipaq", MACHINE_HPCARM_IPAQ,
+	    "ipaq", NULL);
+
+	machine_entry_add_subtype(me, "Jornada 720", MACHINE_HPCARM_JORNADA720,
+	    "jornada720", NULL);
+
+	machine_entry_add_subtype(me, "Jornada 728", MACHINE_HPCARM_JORNADA728,
+	    "jornada728", NULL);
+
+	me->set_default_ram = machine_default_ram_hpcarm;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_hpcarm.cc gxemul-0.7.0+dfsg/src/machines/machine_hpcarm.cc
--- gxemul-0.6.2/src/machines/machine_hpcarm.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_hpcarm.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,232 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Handheld ARM-based machines
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/hpc_bootinfo.h"
-#include "thirdparty/vripreg.h"
-
-
-MACHINE_SETUP(hpcarm)
-{
-	struct hpc_bootinfo hpc_bootinfo;
-	int hpc_platid_flags = 0, hpc_platid_cpu_submodel = 0,
-	    hpc_platid_cpu_model = 0, hpc_platid_cpu_series = 0,
-	    hpc_platid_cpu_arch = 0,
-	    hpc_platid_submodel = 0, hpc_platid_model = 0,
-	    hpc_platid_series = 0, hpc_platid_vendor = 0;
-	uint64_t hpc_fb_addr = 0;
-	int hpc_fb_bits = 0, hpc_fb_encoding = 0;
-	int hpc_fb_xsize = 0;
-	int hpc_fb_ysize = 0;
-	int hpc_fb_xsize_mem = 0;
-	int hpc_fb_ysize_mem = 0;
-
-	memset(&hpc_bootinfo, 0, sizeof(hpc_bootinfo));
-
-	cpu->byte_order = EMUL_LITTLE_ENDIAN;
-
-	switch (machine->machine_subtype) {
-
-	case MACHINE_HPCARM_IPAQ:
-		/*  SA-1110 206MHz  */
-		machine->machine_name = strdup("Compaq iPAQ H3600");
-		hpc_fb_addr = 0x48200000;	/*  TODO  */
-		hpc_fb_xsize = 240;
-		hpc_fb_ysize = 320;
-		hpc_fb_xsize_mem = 256;
-		hpc_fb_ysize_mem = 320;
-		hpc_fb_bits = 15;
-		hpc_fb_encoding = BIFB_D16_0000;
-		hpc_platid_cpu_arch = 3;	/*  ARM  */
-		hpc_platid_cpu_series = 1;	/*  StrongARM  */
-		hpc_platid_cpu_model = 2;	/*  SA-1110  */
-		hpc_platid_cpu_submodel = 0;
-		hpc_platid_vendor = 7;		/*  Compaq  */
-		hpc_platid_series = 4;		/*  IPAQ  */
-		hpc_platid_model = 2;		/*  H36xx  */
-		hpc_platid_submodel = 1;	/*  H3600  */
-		break;
-
-	case MACHINE_HPCARM_JORNADA720:
-	case MACHINE_HPCARM_JORNADA728:
-		/*  SA-1110 206MHz  */
-		machine->machine_name =
-		    ((machine->machine_subtype == MACHINE_HPCARM_JORNADA720) ?
-		    "Jornada 720" : "Jornada 728");
-		hpc_fb_addr = 0x48200000;
-		hpc_fb_xsize = 640;
-		hpc_fb_ysize = 240;
-		hpc_fb_xsize_mem = 640;
-		hpc_fb_ysize_mem = 240;
-		hpc_fb_bits = 16;
-		hpc_fb_encoding = BIFB_D16_0000;
-		hpc_platid_cpu_arch = 3;	/*  ARM  */
-		hpc_platid_cpu_series = 1;	/*  StrongARM  */
-		hpc_platid_cpu_model = 2;	/*  SA-1110  */
-		hpc_platid_cpu_submodel = 0;
-		hpc_platid_vendor = 11;		/*  HP  */
-		hpc_platid_series = 2;		/*  Jornada  */
-		hpc_platid_model = 2;		/*  7xx  */
-		hpc_platid_submodel = 1;	/*  720  */
-		break;
-
-	default:printf("Unimplemented hpcarm machine number.\n");
-		exit(1);
-	}
-
-	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.platid_cpu,
-	      (hpc_platid_cpu_arch << 26) + (hpc_platid_cpu_series << 20)
-	    + (hpc_platid_cpu_model << 14) + (hpc_platid_cpu_submodel <<  8)
-	    + hpc_platid_flags);
-	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.
-	    platid_machine,(hpc_platid_vendor << 22) + (hpc_platid_series << 16)
-	    + (hpc_platid_model <<  8) + hpc_platid_submodel);
-
-	/*  Physical RAM at 0xc0000000:  */
-	dev_ram_init(machine, 0xc0000000, 0x20000000,
-	    DEV_RAM_MIRROR, 0x0);
-
-	/*  Cache flush region:  */
-	dev_ram_init(machine, 0xe0000000, 0x10000, DEV_RAM_RAM, 0x0);
-
-	if (hpc_fb_addr != 0) {
-		dev_fb_init(machine, machine->memory, hpc_fb_addr, VFB_HPC,
-		    hpc_fb_xsize, hpc_fb_ysize,
-		    hpc_fb_xsize_mem, hpc_fb_ysize_mem,
-		    hpc_fb_bits, machine->machine_name);
-	}
-
-	if (!machine->prom_emulation)
-		return;
-
-
-	/*  NetBSD/hpcarm and possibly others expects the following:  */
-
-	cpu->cd.arm.r[0] = 1;	/*  argc  */
-	cpu->cd.arm.r[1] = machine->physical_ram_in_mb * 1048576 - 512;	/*argv*/
-	cpu->cd.arm.r[2] = machine->physical_ram_in_mb * 1048576 - 256;
-		/*  r[2] = ptr to hpc_bootinfo  */
-
-	machine->bootstr = machine->boot_kernel_filename;
-	store_32bit_word(cpu, machine->physical_ram_in_mb * 1048576 - 512,
-	    machine->physical_ram_in_mb * 1048576 - 512 + 16);
-	store_32bit_word(cpu, machine->physical_ram_in_mb * 1048576 - 512 +4,0);
-	store_string(cpu, machine->physical_ram_in_mb * 1048576 - 512 + 16,
-	    machine->bootstr);
-
-	if (machine->boot_string_argument[0]) {
-		cpu->cd.arm.r[0] ++;	/*  argc  */
-
-		store_32bit_word(cpu, machine->physical_ram_in_mb * 1048576 -
-		    512 + 4, machine->physical_ram_in_mb * 1048576 - 512 + 64);
-		store_32bit_word(cpu, machine->physical_ram_in_mb * 1048576 -
-		    512 + 8, 0);
-
-		store_string(cpu, machine->physical_ram_in_mb * 1048576 - 512
-		    + 64, machine->boot_string_argument);
-
-		machine->bootarg = machine->boot_string_argument;
-	}
-
-	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.length,
-	    sizeof(hpc_bootinfo));
-	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.magic,
-	    HPC_BOOTINFO_MAGIC);
-	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_addr,
-	    hpc_fb_addr);
-	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.
-	    fb_line_bytes, hpc_fb_xsize_mem * (((hpc_fb_bits-1)|7)+1) / 8);
-	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_width,
-	    hpc_fb_xsize);
-	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_height,
-	    hpc_fb_ysize);
-	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_type,
-	    hpc_fb_encoding);
-	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.bi_cnuse,
-	    machine->x11_md.in_use? BI_CNUSE_BUILTIN : BI_CNUSE_SERIAL);
-
-	store_32bit_word_in_host(cpu,(unsigned char *)&hpc_bootinfo.timezone,0);
-	store_buf(cpu, machine->physical_ram_in_mb * 1048576 - 256,
-	    (char *)&hpc_bootinfo, sizeof(hpc_bootinfo));
-
-	/*  TODO: What is a good default stack pointer?  */
-	/*  I.e. what does hpcboot.exe for NetBSD/hpcarm usually use?  */
-	cpu->cd.arm.r[ARM_SP] = 0xc02dfff0;
-}
-
-
-MACHINE_DEFAULT_CPU(hpcarm)
-{
-	machine->cpu_name = strdup("SA1110");
-}
-
-
-MACHINE_DEFAULT_RAM(hpcarm)
-{
-	switch (machine->machine_subtype) {
-	case MACHINE_HPCARM_JORNADA728:
-		/*  720 has 32 MB, 728 has 64 MB.  */
-		machine->physical_ram_in_mb = 64;
-		break;
-	default:
-		/*  Most have 32 MB by default.  */
-		machine->physical_ram_in_mb = 32;
-	}
-}
-
-
-MACHINE_REGISTER(hpcarm)
-{
-	MR_DEFAULT(hpcarm, "Handhelp ARM (HPCarm)", ARCH_ARM, MACHINE_HPCARM);
-
-	machine_entry_add_alias(me, "hpcarm");
-
-	machine_entry_add_subtype(me, "Ipaq", MACHINE_HPCARM_IPAQ,
-	    "ipaq", NULL);
-
-	machine_entry_add_subtype(me, "Jornada 720", MACHINE_HPCARM_JORNADA720,
-	    "jornada720", NULL);
-
-	machine_entry_add_subtype(me, "Jornada 728", MACHINE_HPCARM_JORNADA728,
-	    "jornada728", NULL);
-
-	me->set_default_ram = machine_default_ram_hpcarm;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_hpcmips.c gxemul-0.7.0+dfsg/src/machines/machine_hpcmips.c
--- gxemul-0.6.2/src/machines/machine_hpcmips.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_hpcmips.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,483 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Handheld MIPS-based machines
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/hpc_bootinfo.h"
+#include "thirdparty/vripreg.h"
+
+
+MACHINE_SETUP(hpcmips)
+{
+	char tmpstr[1000];
+	struct hpc_bootinfo hpc_bootinfo;
+	int hpc_platid_flags = 0, hpc_platid_cpu_submodel = 0,
+	    hpc_platid_cpu_model = 0, hpc_platid_cpu_series = 0,
+	    hpc_platid_cpu_arch = 0,
+	    hpc_platid_submodel = 0, hpc_platid_model = 0,
+	    hpc_platid_series = 0, hpc_platid_vendor = 0;
+	uint64_t hpc_fb_addr = 0;
+	int hpc_fb_bits = 0, hpc_fb_encoding = 0;
+	int hpc_fb_xsize = 0;
+	int hpc_fb_ysize = 0;
+	int hpc_fb_xsize_mem = 0;
+	int hpc_fb_ysize_mem = 0;
+
+	cpu->byte_order = EMUL_LITTLE_ENDIAN;
+	memset(&hpc_bootinfo, 0, sizeof(hpc_bootinfo));
+
+	/*
+	 *  NOTE: See http://forums.projectmayo.com/viewtopic.php?topic=2743&
+	 *	forum=23 for info on framebuffer addresses.
+	 */
+
+	switch (machine->machine_subtype) {
+
+	case MACHINE_HPCMIPS_CASIO_BE300:
+		/*  166MHz VR4131  */
+		machine->machine_name = strdup("Casio Cassiopeia BE-300");
+		hpc_fb_addr = 0x0a200000;
+		hpc_fb_xsize = 240;
+		hpc_fb_ysize = 320;
+		hpc_fb_xsize_mem = 256;
+		hpc_fb_ysize_mem = 320;
+		hpc_fb_bits = 15;
+		hpc_fb_encoding = BIFB_D16_0000;
+
+		/*  TODO: irq?  */
+		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=0 addr=0x"
+		    "0a008680 addr_mult=4 in_use=%i", !machine->x11_md.in_use);
+		machine->main_console_handle = (size_t)
+		    device_add(machine, tmpstr);
+
+		dev_vr41xx_init(machine, machine->memory, 4131);
+
+		hpc_platid_cpu_arch = 1;	/*  MIPS  */
+		hpc_platid_cpu_series = 1;	/*  VR  */
+		hpc_platid_cpu_model = 1;	/*  VR41XX  */
+		hpc_platid_cpu_submodel = 6;	/*  VR4131  */
+		hpc_platid_vendor = 3;		/*  Casio  */
+		hpc_platid_series = 1;		/*  CASSIOPEIAE  */
+		hpc_platid_model = 2;		/*  EXXX  */
+		hpc_platid_submodel = 3;	/*  E500  */
+		/*  TODO: Don't use model number for E500, it's a BE300!  */
+		break;
+
+	case MACHINE_HPCMIPS_CASIO_E105:
+		/*  131MHz VR4121  */
+		machine->machine_name = strdup("Casio Cassiopeia E-105");
+		hpc_fb_addr = 0x0a200000;	/*  TODO?  */
+		hpc_fb_xsize = 240;
+		hpc_fb_ysize = 320;
+		hpc_fb_xsize_mem = 256;
+		hpc_fb_ysize_mem = 320;
+		hpc_fb_bits = 16;
+		hpc_fb_encoding = BIFB_D16_0000;
+
+		/*  TODO: irq?  */
+		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=0 addr=0x"
+		    "0a008680 addr_mult=4 in_use=%i", !machine->x11_md.in_use);
+		machine->main_console_handle = (size_t)
+		    device_add(machine, tmpstr);
+
+		dev_vr41xx_init(machine, machine->memory, 4121);
+
+		hpc_platid_cpu_arch = 1;	/*  MIPS  */
+		hpc_platid_cpu_series = 1;	/*  VR  */
+		hpc_platid_cpu_model = 1;	/*  VR41XX  */
+		hpc_platid_cpu_submodel = 3;	/*  VR4121  */
+		hpc_platid_vendor = 3;		/*  Casio  */
+		hpc_platid_series = 1;		/*  CASSIOPEIAE  */
+		hpc_platid_model = 2;		/*  EXXX  */
+		hpc_platid_submodel = 2;	/*  E105  */
+		break;
+
+	case MACHINE_HPCMIPS_NEC_MOBILEPRO_770:
+		/*  131 MHz VR4121  */
+		machine->machine_name = strdup("NEC MobilePro 770");
+		hpc_fb_addr = 0xa000000;
+		hpc_fb_xsize = 640;
+		hpc_fb_ysize = 240;
+		hpc_fb_xsize_mem = 800;
+		hpc_fb_ysize_mem = 240;
+		hpc_fb_bits = 16;
+		hpc_fb_encoding = BIFB_D16_0000;
+
+		dev_vr41xx_init(machine, machine->memory, 4121);
+
+		hpc_platid_cpu_arch = 1;	/*  MIPS  */
+		hpc_platid_cpu_series = 1;	/*  VR  */
+		hpc_platid_cpu_model = 1;	/*  VR41XX  */
+		hpc_platid_cpu_submodel = 3;	/*  VR4121  */
+		hpc_platid_vendor = 1;		/*  NEC  */
+		hpc_platid_series = 2;		/*  NEC MCR  */
+		hpc_platid_model = 2;		/*  MCR 5XX  */
+		hpc_platid_submodel = 4;	/*  MCR 520A  */
+		break;
+
+	case MACHINE_HPCMIPS_NEC_MOBILEPRO_780:
+		/*  166 (or 168) MHz VR4121  */
+		machine->machine_name = strdup("NEC MobilePro 780");
+		hpc_fb_addr = 0xa180100;
+		hpc_fb_xsize = 640;
+		hpc_fb_ysize = 240;
+		hpc_fb_xsize_mem = 640;
+		hpc_fb_ysize_mem = 240;
+		hpc_fb_bits = 16;
+		hpc_fb_encoding = BIFB_D16_0000;
+
+		dev_vr41xx_init(machine, machine->memory, 4121);
+
+		hpc_platid_cpu_arch = 1;	/*  MIPS  */
+		hpc_platid_cpu_series = 1;	/*  VR  */
+		hpc_platid_cpu_model = 1;	/*  VR41XX  */
+		hpc_platid_cpu_submodel = 3;	/*  VR4121  */
+		hpc_platid_vendor = 1;		/*  NEC  */
+		hpc_platid_series = 2;		/*  NEC MCR  */
+		hpc_platid_model = 2;		/*  MCR 5XX  */
+		hpc_platid_submodel = 8;	/*  MCR 530A  */
+		break;
+
+	case MACHINE_HPCMIPS_NEC_MOBILEPRO_800:
+		/*  131 MHz VR4121  */
+		machine->machine_name = strdup("NEC MobilePro 800");
+		hpc_fb_addr = 0xa000000;
+		hpc_fb_xsize = 800;
+		hpc_fb_ysize = 600;
+		hpc_fb_xsize_mem = 800;
+		hpc_fb_ysize_mem = 600;
+		hpc_fb_bits = 16;
+		hpc_fb_encoding = BIFB_D16_0000;
+
+		dev_vr41xx_init(machine, machine->memory, 4121);
+
+		hpc_platid_cpu_arch = 1;	/*  MIPS  */
+		hpc_platid_cpu_series = 1;	/*  VR  */
+		hpc_platid_cpu_model = 1;	/*  VR41XX  */
+		hpc_platid_cpu_submodel = 3;	/*  VR4121  */
+		hpc_platid_vendor = 1;		/*  NEC  */
+		hpc_platid_series = 2;		/*  NEC MCR  */
+		hpc_platid_model = 3;		/*  MCR 7XX  */
+		hpc_platid_submodel = 2;	/*  MCR 700A  */
+		break;
+
+	case MACHINE_HPCMIPS_NEC_MOBILEPRO_880:
+		/*  168 MHz VR4121  */
+		machine->machine_name = strdup("NEC MobilePro 880");
+		hpc_fb_addr = 0xa0ea600;
+		hpc_fb_xsize = 800;
+		hpc_fb_ysize = 600;
+		hpc_fb_xsize_mem = 800;
+		hpc_fb_ysize_mem = 600;
+		hpc_fb_bits = 16;
+		hpc_fb_encoding = BIFB_D16_0000;
+
+		dev_vr41xx_init(machine, machine->memory, 4121);
+
+		hpc_platid_cpu_arch = 1;	/*  MIPS  */
+		hpc_platid_cpu_series = 1;	/*  VR  */
+		hpc_platid_cpu_model = 1;	/*  VR41XX  */
+		hpc_platid_cpu_submodel = 3;	/*  VR4121  */
+		hpc_platid_vendor = 1;		/*  NEC  */
+		hpc_platid_series = 2;		/*  NEC MCR  */
+		hpc_platid_model = 3;		/*  MCR 7XX  */
+		hpc_platid_submodel = 4;	/*  MCR 730A  */
+		break;
+
+	case MACHINE_HPCMIPS_AGENDA_VR3:
+		/*  66 MHz VR4181  */
+		machine->machine_name = strdup("Agenda VR3");
+		/*  TODO:  */
+		hpc_fb_addr = 0x1000;
+		hpc_fb_xsize = 160;
+		hpc_fb_ysize = 240;
+		hpc_fb_xsize_mem = 160;
+		hpc_fb_ysize_mem = 240;
+		hpc_fb_bits = 4;
+		hpc_fb_encoding = BIFB_D4_M2L_F;
+
+		dev_vr41xx_init(machine, machine->memory, 4181);
+
+		/*  TODO: Hm... irq 17 according to linux, but
+		    VRIP_INTR_SIU (=9) here?  */
+		{
+			int x;
+			snprintf(tmpstr, sizeof(tmpstr),
+			    "ns16550 irq=%i addr=0x0c000010", 8+VRIP_INTR_SIU);
+			x = (size_t)device_add(machine, tmpstr);
+
+			if (!machine->x11_md.in_use)
+				machine->main_console_handle = x;
+		}
+
+		hpc_platid_cpu_arch = 1;	/*  MIPS  */
+		hpc_platid_cpu_series = 1;	/*  VR  */
+		hpc_platid_cpu_model = 1;	/*  VR41XX  */
+		hpc_platid_cpu_submodel = 4;	/*  VR4181  */
+		hpc_platid_vendor = 15;		/*  Agenda  */
+		hpc_platid_series = 1;		/*  VR  */
+		hpc_platid_model = 1;		/*  VR3  */
+		hpc_platid_submodel = 0;	/*  -  */
+
+		dev_ram_init(machine, 0x0f000000, 0x01000000,
+		    DEV_RAM_MIRROR | DEV_RAM_MIGHT_POINT_TO_DEVICES, 0x0, NULL);
+		break;
+
+	case MACHINE_HPCMIPS_IBM_WORKPAD_Z50:
+		/*  131 MHz VR4121  */
+		machine->machine_name = strdup("IBM Workpad Z50");
+		/*  TODO:  */
+		hpc_fb_addr = 0xa000000;
+		hpc_fb_xsize = 640;
+		hpc_fb_ysize = 480;
+		hpc_fb_xsize_mem = 640;
+		hpc_fb_ysize_mem = 480;
+		hpc_fb_bits = 16;
+		hpc_fb_encoding = BIFB_D16_0000;
+
+		dev_vr41xx_init(machine, machine->memory, 4121);
+
+		hpc_platid_cpu_arch = 1;	/*  MIPS  */
+		hpc_platid_cpu_series = 1;	/*  VR  */
+		hpc_platid_cpu_model = 1;	/*  VR41XX  */
+		hpc_platid_cpu_submodel = 3;	/*  VR4121  */
+		hpc_platid_vendor = 9;		/*  IBM  */
+		hpc_platid_series = 1;		/*  WorkPad  */
+		hpc_platid_model = 1;		/*  Z50  */
+		hpc_platid_submodel = 0;	/*  0  */
+		break;
+
+	default:printf("Unimplemented hpcmips machine number.\n");
+		exit(1);
+	}
+
+	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.platid_cpu,
+	      (hpc_platid_cpu_arch << 26) + (hpc_platid_cpu_series << 20)
+	    + (hpc_platid_cpu_model << 14) + (hpc_platid_cpu_submodel <<  8)
+	    + hpc_platid_flags);
+	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.
+	    platid_machine, (hpc_platid_vendor << 22) + (hpc_platid_series<<16)
+	    + (hpc_platid_model <<  8) + hpc_platid_submodel);
+
+	if (hpc_fb_addr != 0) {
+		dev_fb_init(machine, machine->memory, hpc_fb_addr, VFB_HPC,
+		    hpc_fb_xsize, hpc_fb_ysize,
+		    hpc_fb_xsize_mem, hpc_fb_ysize_mem,
+		    hpc_fb_bits, machine->machine_name);
+
+		/*  NetBSD/hpcmips uses framebuffer at physical
+		    address 0x8.......:  */
+		dev_ram_init(machine, 0x80000000, 0x20000000,
+		    DEV_RAM_MIRROR | DEV_RAM_MIGHT_POINT_TO_DEVICES, 0x0, NULL);
+	}
+
+	if (!machine->prom_emulation)
+		return;
+
+
+	/*  NetBSD/hpcmips and possibly others expects the following:  */
+
+	cpu->cd.mips.gpr[MIPS_GPR_A0] = 1;	/*  argc  */
+	cpu->cd.mips.gpr[MIPS_GPR_A1] = machine->physical_ram_in_mb * 1048576
+	    + 0xffffffff80000000ULL - 512;	/*  argv  */
+	cpu->cd.mips.gpr[MIPS_GPR_A2] = machine->physical_ram_in_mb * 1048576
+	    + 0xffffffff80000000ULL - 256;	/*  ptr to hpc_bootinfo  */
+
+	machine->bootstr = machine->boot_kernel_filename;
+	store_32bit_word(cpu, 0x80000000ULL + (machine->physical_ram_in_mb <<
+	    20) - 512, 0x80000000ULL + (machine->physical_ram_in_mb << 20)
+	    - 512 + 16);
+	store_32bit_word(cpu, 0x80000000ULL + (machine->physical_ram_in_mb <<
+	    20) - 512 + 4, 0);
+	store_string(cpu, 0x80000000ULL + (machine->physical_ram_in_mb <<
+	    20) - 512 + 16, machine->bootstr);
+
+	/*  Special case for the Agenda VR3:  */
+	if (machine->machine_subtype == MACHINE_HPCMIPS_AGENDA_VR3) {
+		const int tmplen = 1000;
+		char *tmp = (char *) malloc(tmplen);
+
+		cpu->cd.mips.gpr[MIPS_GPR_A0] = 2;	/*  argc  */
+
+		store_32bit_word(cpu, 0x80000000 + machine->physical_ram_in_mb
+		    * 1048576-512 + 4, 0x80000000 + machine->physical_ram_in_mb
+		    * 1048576 - 512 + 64);
+		store_32bit_word(cpu, 0x80000000 + machine->physical_ram_in_mb
+		    * 1048576 - 512 + 8, 0);
+
+		snprintf(tmp, tmplen, "root=/dev/rom video=vr4181fb:xres:160,y"
+		    "res:240,bpp:4,gray,hpck:3084,inv ether=0,0x03fe0300,eth0");
+		tmp[tmplen-1] = '\0';
+
+		if (!machine->x11_md.in_use)
+			snprintf(tmp+strlen(tmp), tmplen-strlen(tmp),
+			    " console=ttyS0,115200");
+		tmp[tmplen-1] = '\0';
+
+		if (machine->boot_string_argument[0])
+			snprintf(tmp+strlen(tmp), tmplen-strlen(tmp), " %s",
+			    machine->boot_string_argument);
+		tmp[tmplen-1] = '\0';
+
+		store_string(cpu, 0x80000000 + machine->physical_ram_in_mb
+		    * 1048576 - 512 + 64, tmp);
+
+		machine->bootarg = tmp;
+	} else if (machine->boot_string_argument[0]) {
+		cpu->cd.mips.gpr[MIPS_GPR_A0] ++;	/*  argc  */
+
+		store_32bit_word(cpu, 0x80000000 + machine->physical_ram_in_mb
+		    * 1048576-512 + 4, 0x80000000 + machine->physical_ram_in_mb
+		    * 1048576 - 512 + 64);
+		store_32bit_word(cpu, 0x80000000 + machine->physical_ram_in_mb
+		    * 1048576 - 512 + 8, 0);
+
+		store_string(cpu, 0x80000000 + machine->physical_ram_in_mb *
+		    1048576 - 512 + 64, machine->boot_string_argument);
+
+		machine->bootarg = machine->boot_string_argument;
+	}
+
+	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.length,
+	    sizeof(hpc_bootinfo));
+	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.magic,
+	    HPC_BOOTINFO_MAGIC);
+	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_addr,
+	    0x80000000 + hpc_fb_addr);
+	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.
+	    fb_line_bytes, hpc_fb_xsize_mem * (((hpc_fb_bits-1)|7)+1) / 8);
+	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_width,
+	    hpc_fb_xsize);
+	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_height,
+	    hpc_fb_ysize);
+	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_type,
+	    hpc_fb_encoding);
+	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.bi_cnuse,
+	    machine->x11_md.in_use? BI_CNUSE_BUILTIN : BI_CNUSE_SERIAL);
+
+	/*  printf("hpc_bootinfo.platid_cpu     = 0x%08x\n",
+	    hpc_bootinfo.platid_cpu);
+	    printf("hpc_bootinfo.platid_machine = 0x%08x\n",
+	    hpc_bootinfo.platid_machine);  */
+	store_32bit_word_in_host(cpu,(unsigned char *)&hpc_bootinfo.timezone,0);
+	store_buf(cpu, 0x80000000 + machine->physical_ram_in_mb *
+	    1048576 - 256, (char *)&hpc_bootinfo, sizeof(hpc_bootinfo));
+}
+
+
+MACHINE_DEFAULT_CPU(hpcmips)
+{
+	switch (machine->machine_subtype) {
+	case MACHINE_HPCMIPS_CASIO_BE300:
+		machine->cpu_name = strdup("VR4131");
+		break;
+	case MACHINE_HPCMIPS_CASIO_E105:
+		machine->cpu_name = strdup("VR4121");
+		break;
+	case MACHINE_HPCMIPS_NEC_MOBILEPRO_770:
+	case MACHINE_HPCMIPS_NEC_MOBILEPRO_780:
+	case MACHINE_HPCMIPS_NEC_MOBILEPRO_800:
+	case MACHINE_HPCMIPS_NEC_MOBILEPRO_880:
+		machine->cpu_name = strdup("VR4121");
+		break;
+	case MACHINE_HPCMIPS_AGENDA_VR3:
+		machine->cpu_name = strdup("VR4181");
+		break;
+	case MACHINE_HPCMIPS_IBM_WORKPAD_Z50:
+		machine->cpu_name = strdup("VR4121");
+		break;
+	default:printf("Unimplemented HPCMIPS model?\n");
+		exit(1);
+	}
+}
+
+
+MACHINE_DEFAULT_RAM(hpcmips)
+{
+	/*  Most have 32 MB by default.  */
+	machine->physical_ram_in_mb = 32;
+
+	switch (machine->machine_subtype) {
+	case MACHINE_HPCMIPS_CASIO_BE300:
+		machine->physical_ram_in_mb = 16;
+		break;
+	case MACHINE_HPCMIPS_CASIO_E105:
+		machine->physical_ram_in_mb = 32;
+		break;
+	case MACHINE_HPCMIPS_AGENDA_VR3:
+		machine->physical_ram_in_mb = 16;
+		break;
+	}
+}
+
+
+MACHINE_REGISTER(hpcmips)
+{
+	MR_DEFAULT(hpcmips, "Handhelp MIPS (HPCmips)",
+	    MACHINE_HPCMIPS);
+
+	machine_entry_add_alias(me, "hpcmips");
+
+	machine_entry_add_subtype(me, "Casio Cassiopeia BE-300",
+	    MACHINE_HPCMIPS_CASIO_BE300, "be-300", "be300", NULL);
+
+	machine_entry_add_subtype(me, "Casio Cassiopeia E-105",
+	    MACHINE_HPCMIPS_CASIO_E105, "e-105", "e105", NULL);
+
+	machine_entry_add_subtype(me, "Agenda VR3", MACHINE_HPCMIPS_AGENDA_VR3,
+	    "agenda", "vr3", NULL);
+
+	machine_entry_add_subtype(me, "IBM WorkPad Z50",
+	    MACHINE_HPCMIPS_IBM_WORKPAD_Z50, "workpad", "z50", NULL);
+
+	machine_entry_add_subtype(me, "NEC MobilePro 770",
+	    MACHINE_HPCMIPS_NEC_MOBILEPRO_770, "mobilepro770", NULL);
+
+	machine_entry_add_subtype(me, "NEC MobilePro 780",
+	    MACHINE_HPCMIPS_NEC_MOBILEPRO_780, "mobilepro780", NULL);
+
+	machine_entry_add_subtype(me, "NEC MobilePro 800",
+	    MACHINE_HPCMIPS_NEC_MOBILEPRO_800, "mobilepro800", NULL);
+
+	machine_entry_add_subtype(me, "NEC MobilePro 880",
+	    MACHINE_HPCMIPS_NEC_MOBILEPRO_880, "mobilepro880", NULL);
+
+	me->set_default_ram = machine_default_ram_hpcmips;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_hpcmips.cc gxemul-0.7.0+dfsg/src/machines/machine_hpcmips.cc
--- gxemul-0.6.2/src/machines/machine_hpcmips.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_hpcmips.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,483 +0,0 @@
-/*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Handheld MIPS-based machines
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/hpc_bootinfo.h"
-#include "thirdparty/vripreg.h"
-
-
-MACHINE_SETUP(hpcmips)
-{
-	char tmpstr[1000];
-	struct hpc_bootinfo hpc_bootinfo;
-	int hpc_platid_flags = 0, hpc_platid_cpu_submodel = 0,
-	    hpc_platid_cpu_model = 0, hpc_platid_cpu_series = 0,
-	    hpc_platid_cpu_arch = 0,
-	    hpc_platid_submodel = 0, hpc_platid_model = 0,
-	    hpc_platid_series = 0, hpc_platid_vendor = 0;
-	uint64_t hpc_fb_addr = 0;
-	int hpc_fb_bits = 0, hpc_fb_encoding = 0;
-	int hpc_fb_xsize = 0;
-	int hpc_fb_ysize = 0;
-	int hpc_fb_xsize_mem = 0;
-	int hpc_fb_ysize_mem = 0;
-
-	cpu->byte_order = EMUL_LITTLE_ENDIAN;
-	memset(&hpc_bootinfo, 0, sizeof(hpc_bootinfo));
-
-	/*
-	 *  NOTE: See http://forums.projectmayo.com/viewtopic.php?topic=2743&
-	 *	forum=23 for info on framebuffer addresses.
-	 */
-
-	switch (machine->machine_subtype) {
-
-	case MACHINE_HPCMIPS_CASIO_BE300:
-		/*  166MHz VR4131  */
-		machine->machine_name = strdup("Casio Cassiopeia BE-300");
-		hpc_fb_addr = 0x0a200000;
-		hpc_fb_xsize = 240;
-		hpc_fb_ysize = 320;
-		hpc_fb_xsize_mem = 256;
-		hpc_fb_ysize_mem = 320;
-		hpc_fb_bits = 15;
-		hpc_fb_encoding = BIFB_D16_0000;
-
-		/*  TODO: irq?  */
-		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=0 addr=0x"
-		    "0a008680 addr_mult=4 in_use=%i", !machine->x11_md.in_use);
-		machine->main_console_handle = (size_t)
-		    device_add(machine, tmpstr);
-
-		dev_vr41xx_init(machine, machine->memory, 4131);
-
-		hpc_platid_cpu_arch = 1;	/*  MIPS  */
-		hpc_platid_cpu_series = 1;	/*  VR  */
-		hpc_platid_cpu_model = 1;	/*  VR41XX  */
-		hpc_platid_cpu_submodel = 6;	/*  VR4131  */
-		hpc_platid_vendor = 3;		/*  Casio  */
-		hpc_platid_series = 1;		/*  CASSIOPEIAE  */
-		hpc_platid_model = 2;		/*  EXXX  */
-		hpc_platid_submodel = 3;	/*  E500  */
-		/*  TODO: Don't use model number for E500, it's a BE300!  */
-		break;
-
-	case MACHINE_HPCMIPS_CASIO_E105:
-		/*  131MHz VR4121  */
-		machine->machine_name = strdup("Casio Cassiopeia E-105");
-		hpc_fb_addr = 0x0a200000;	/*  TODO?  */
-		hpc_fb_xsize = 240;
-		hpc_fb_ysize = 320;
-		hpc_fb_xsize_mem = 256;
-		hpc_fb_ysize_mem = 320;
-		hpc_fb_bits = 16;
-		hpc_fb_encoding = BIFB_D16_0000;
-
-		/*  TODO: irq?  */
-		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=0 addr=0x"
-		    "0a008680 addr_mult=4 in_use=%i", !machine->x11_md.in_use);
-		machine->main_console_handle = (size_t)
-		    device_add(machine, tmpstr);
-
-		dev_vr41xx_init(machine, machine->memory, 4121);
-
-		hpc_platid_cpu_arch = 1;	/*  MIPS  */
-		hpc_platid_cpu_series = 1;	/*  VR  */
-		hpc_platid_cpu_model = 1;	/*  VR41XX  */
-		hpc_platid_cpu_submodel = 3;	/*  VR4121  */
-		hpc_platid_vendor = 3;		/*  Casio  */
-		hpc_platid_series = 1;		/*  CASSIOPEIAE  */
-		hpc_platid_model = 2;		/*  EXXX  */
-		hpc_platid_submodel = 2;	/*  E105  */
-		break;
-
-	case MACHINE_HPCMIPS_NEC_MOBILEPRO_770:
-		/*  131 MHz VR4121  */
-		machine->machine_name = strdup("NEC MobilePro 770");
-		hpc_fb_addr = 0xa000000;
-		hpc_fb_xsize = 640;
-		hpc_fb_ysize = 240;
-		hpc_fb_xsize_mem = 800;
-		hpc_fb_ysize_mem = 240;
-		hpc_fb_bits = 16;
-		hpc_fb_encoding = BIFB_D16_0000;
-
-		dev_vr41xx_init(machine, machine->memory, 4121);
-
-		hpc_platid_cpu_arch = 1;	/*  MIPS  */
-		hpc_platid_cpu_series = 1;	/*  VR  */
-		hpc_platid_cpu_model = 1;	/*  VR41XX  */
-		hpc_platid_cpu_submodel = 3;	/*  VR4121  */
-		hpc_platid_vendor = 1;		/*  NEC  */
-		hpc_platid_series = 2;		/*  NEC MCR  */
-		hpc_platid_model = 2;		/*  MCR 5XX  */
-		hpc_platid_submodel = 4;	/*  MCR 520A  */
-		break;
-
-	case MACHINE_HPCMIPS_NEC_MOBILEPRO_780:
-		/*  166 (or 168) MHz VR4121  */
-		machine->machine_name = strdup("NEC MobilePro 780");
-		hpc_fb_addr = 0xa180100;
-		hpc_fb_xsize = 640;
-		hpc_fb_ysize = 240;
-		hpc_fb_xsize_mem = 640;
-		hpc_fb_ysize_mem = 240;
-		hpc_fb_bits = 16;
-		hpc_fb_encoding = BIFB_D16_0000;
-
-		dev_vr41xx_init(machine, machine->memory, 4121);
-
-		hpc_platid_cpu_arch = 1;	/*  MIPS  */
-		hpc_platid_cpu_series = 1;	/*  VR  */
-		hpc_platid_cpu_model = 1;	/*  VR41XX  */
-		hpc_platid_cpu_submodel = 3;	/*  VR4121  */
-		hpc_platid_vendor = 1;		/*  NEC  */
-		hpc_platid_series = 2;		/*  NEC MCR  */
-		hpc_platid_model = 2;		/*  MCR 5XX  */
-		hpc_platid_submodel = 8;	/*  MCR 530A  */
-		break;
-
-	case MACHINE_HPCMIPS_NEC_MOBILEPRO_800:
-		/*  131 MHz VR4121  */
-		machine->machine_name = strdup("NEC MobilePro 800");
-		hpc_fb_addr = 0xa000000;
-		hpc_fb_xsize = 800;
-		hpc_fb_ysize = 600;
-		hpc_fb_xsize_mem = 800;
-		hpc_fb_ysize_mem = 600;
-		hpc_fb_bits = 16;
-		hpc_fb_encoding = BIFB_D16_0000;
-
-		dev_vr41xx_init(machine, machine->memory, 4121);
-
-		hpc_platid_cpu_arch = 1;	/*  MIPS  */
-		hpc_platid_cpu_series = 1;	/*  VR  */
-		hpc_platid_cpu_model = 1;	/*  VR41XX  */
-		hpc_platid_cpu_submodel = 3;	/*  VR4121  */
-		hpc_platid_vendor = 1;		/*  NEC  */
-		hpc_platid_series = 2;		/*  NEC MCR  */
-		hpc_platid_model = 3;		/*  MCR 7XX  */
-		hpc_platid_submodel = 2;	/*  MCR 700A  */
-		break;
-
-	case MACHINE_HPCMIPS_NEC_MOBILEPRO_880:
-		/*  168 MHz VR4121  */
-		machine->machine_name = strdup("NEC MobilePro 880");
-		hpc_fb_addr = 0xa0ea600;
-		hpc_fb_xsize = 800;
-		hpc_fb_ysize = 600;
-		hpc_fb_xsize_mem = 800;
-		hpc_fb_ysize_mem = 600;
-		hpc_fb_bits = 16;
-		hpc_fb_encoding = BIFB_D16_0000;
-
-		dev_vr41xx_init(machine, machine->memory, 4121);
-
-		hpc_platid_cpu_arch = 1;	/*  MIPS  */
-		hpc_platid_cpu_series = 1;	/*  VR  */
-		hpc_platid_cpu_model = 1;	/*  VR41XX  */
-		hpc_platid_cpu_submodel = 3;	/*  VR4121  */
-		hpc_platid_vendor = 1;		/*  NEC  */
-		hpc_platid_series = 2;		/*  NEC MCR  */
-		hpc_platid_model = 3;		/*  MCR 7XX  */
-		hpc_platid_submodel = 4;	/*  MCR 730A  */
-		break;
-
-	case MACHINE_HPCMIPS_AGENDA_VR3:
-		/*  66 MHz VR4181  */
-		machine->machine_name = strdup("Agenda VR3");
-		/*  TODO:  */
-		hpc_fb_addr = 0x1000;
-		hpc_fb_xsize = 160;
-		hpc_fb_ysize = 240;
-		hpc_fb_xsize_mem = 160;
-		hpc_fb_ysize_mem = 240;
-		hpc_fb_bits = 4;
-		hpc_fb_encoding = BIFB_D4_M2L_F;
-
-		dev_vr41xx_init(machine, machine->memory, 4181);
-
-		/*  TODO: Hm... irq 17 according to linux, but
-		    VRIP_INTR_SIU (=9) here?  */
-		{
-			int x;
-			snprintf(tmpstr, sizeof(tmpstr),
-			    "ns16550 irq=%i addr=0x0c000010", 8+VRIP_INTR_SIU);
-			x = (size_t)device_add(machine, tmpstr);
-
-			if (!machine->x11_md.in_use)
-				machine->main_console_handle = x;
-		}
-
-		hpc_platid_cpu_arch = 1;	/*  MIPS  */
-		hpc_platid_cpu_series = 1;	/*  VR  */
-		hpc_platid_cpu_model = 1;	/*  VR41XX  */
-		hpc_platid_cpu_submodel = 4;	/*  VR4181  */
-		hpc_platid_vendor = 15;		/*  Agenda  */
-		hpc_platid_series = 1;		/*  VR  */
-		hpc_platid_model = 1;		/*  VR3  */
-		hpc_platid_submodel = 0;	/*  -  */
-
-		dev_ram_init(machine, 0x0f000000, 0x01000000,
-		    DEV_RAM_MIRROR | DEV_RAM_MIGHT_POINT_TO_DEVICES, 0x0);
-		break;
-
-	case MACHINE_HPCMIPS_IBM_WORKPAD_Z50:
-		/*  131 MHz VR4121  */
-		machine->machine_name = strdup("IBM Workpad Z50");
-		/*  TODO:  */
-		hpc_fb_addr = 0xa000000;
-		hpc_fb_xsize = 640;
-		hpc_fb_ysize = 480;
-		hpc_fb_xsize_mem = 640;
-		hpc_fb_ysize_mem = 480;
-		hpc_fb_bits = 16;
-		hpc_fb_encoding = BIFB_D16_0000;
-
-		dev_vr41xx_init(machine, machine->memory, 4121);
-
-		hpc_platid_cpu_arch = 1;	/*  MIPS  */
-		hpc_platid_cpu_series = 1;	/*  VR  */
-		hpc_platid_cpu_model = 1;	/*  VR41XX  */
-		hpc_platid_cpu_submodel = 3;	/*  VR4121  */
-		hpc_platid_vendor = 9;		/*  IBM  */
-		hpc_platid_series = 1;		/*  WorkPad  */
-		hpc_platid_model = 1;		/*  Z50  */
-		hpc_platid_submodel = 0;	/*  0  */
-		break;
-
-	default:printf("Unimplemented hpcmips machine number.\n");
-		exit(1);
-	}
-
-	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.platid_cpu,
-	      (hpc_platid_cpu_arch << 26) + (hpc_platid_cpu_series << 20)
-	    + (hpc_platid_cpu_model << 14) + (hpc_platid_cpu_submodel <<  8)
-	    + hpc_platid_flags);
-	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.
-	    platid_machine, (hpc_platid_vendor << 22) + (hpc_platid_series<<16)
-	    + (hpc_platid_model <<  8) + hpc_platid_submodel);
-
-	if (hpc_fb_addr != 0) {
-		dev_fb_init(machine, machine->memory, hpc_fb_addr, VFB_HPC,
-		    hpc_fb_xsize, hpc_fb_ysize,
-		    hpc_fb_xsize_mem, hpc_fb_ysize_mem,
-		    hpc_fb_bits, machine->machine_name);
-
-		/*  NetBSD/hpcmips uses framebuffer at physical
-		    address 0x8.......:  */
-		dev_ram_init(machine, 0x80000000, 0x20000000,
-		    DEV_RAM_MIRROR | DEV_RAM_MIGHT_POINT_TO_DEVICES, 0x0);
-	}
-
-	if (!machine->prom_emulation)
-		return;
-
-
-	/*  NetBSD/hpcmips and possibly others expects the following:  */
-
-	cpu->cd.mips.gpr[MIPS_GPR_A0] = 1;	/*  argc  */
-	cpu->cd.mips.gpr[MIPS_GPR_A1] = machine->physical_ram_in_mb * 1048576
-	    + 0xffffffff80000000ULL - 512;	/*  argv  */
-	cpu->cd.mips.gpr[MIPS_GPR_A2] = machine->physical_ram_in_mb * 1048576
-	    + 0xffffffff80000000ULL - 256;	/*  ptr to hpc_bootinfo  */
-
-	machine->bootstr = machine->boot_kernel_filename;
-	store_32bit_word(cpu, 0x80000000ULL + (machine->physical_ram_in_mb <<
-	    20) - 512, 0x80000000ULL + (machine->physical_ram_in_mb << 20)
-	    - 512 + 16);
-	store_32bit_word(cpu, 0x80000000ULL + (machine->physical_ram_in_mb <<
-	    20) - 512 + 4, 0);
-	store_string(cpu, 0x80000000ULL + (machine->physical_ram_in_mb <<
-	    20) - 512 + 16, machine->bootstr);
-
-	/*  Special case for the Agenda VR3:  */
-	if (machine->machine_subtype == MACHINE_HPCMIPS_AGENDA_VR3) {
-		const int tmplen = 1000;
-		char *tmp = (char *) malloc(tmplen);
-
-		cpu->cd.mips.gpr[MIPS_GPR_A0] = 2;	/*  argc  */
-
-		store_32bit_word(cpu, 0x80000000 + machine->physical_ram_in_mb
-		    * 1048576-512 + 4, 0x80000000 + machine->physical_ram_in_mb
-		    * 1048576 - 512 + 64);
-		store_32bit_word(cpu, 0x80000000 + machine->physical_ram_in_mb
-		    * 1048576 - 512 + 8, 0);
-
-		snprintf(tmp, tmplen, "root=/dev/rom video=vr4181fb:xres:160,y"
-		    "res:240,bpp:4,gray,hpck:3084,inv ether=0,0x03fe0300,eth0");
-		tmp[tmplen-1] = '\0';
-
-		if (!machine->x11_md.in_use)
-			snprintf(tmp+strlen(tmp), tmplen-strlen(tmp),
-			    " console=ttyS0,115200");
-		tmp[tmplen-1] = '\0';
-
-		if (machine->boot_string_argument[0])
-			snprintf(tmp+strlen(tmp), tmplen-strlen(tmp), " %s",
-			    machine->boot_string_argument);
-		tmp[tmplen-1] = '\0';
-
-		store_string(cpu, 0x80000000 + machine->physical_ram_in_mb
-		    * 1048576 - 512 + 64, tmp);
-
-		machine->bootarg = tmp;
-	} else if (machine->boot_string_argument[0]) {
-		cpu->cd.mips.gpr[MIPS_GPR_A0] ++;	/*  argc  */
-
-		store_32bit_word(cpu, 0x80000000 + machine->physical_ram_in_mb
-		    * 1048576-512 + 4, 0x80000000 + machine->physical_ram_in_mb
-		    * 1048576 - 512 + 64);
-		store_32bit_word(cpu, 0x80000000 + machine->physical_ram_in_mb
-		    * 1048576 - 512 + 8, 0);
-
-		store_string(cpu, 0x80000000 + machine->physical_ram_in_mb *
-		    1048576 - 512 + 64, machine->boot_string_argument);
-
-		machine->bootarg = machine->boot_string_argument;
-	}
-
-	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.length,
-	    sizeof(hpc_bootinfo));
-	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.magic,
-	    HPC_BOOTINFO_MAGIC);
-	store_32bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_addr,
-	    0x80000000 + hpc_fb_addr);
-	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.
-	    fb_line_bytes, hpc_fb_xsize_mem * (((hpc_fb_bits-1)|7)+1) / 8);
-	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_width,
-	    hpc_fb_xsize);
-	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_height,
-	    hpc_fb_ysize);
-	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.fb_type,
-	    hpc_fb_encoding);
-	store_16bit_word_in_host(cpu, (unsigned char *)&hpc_bootinfo.bi_cnuse,
-	    machine->x11_md.in_use? BI_CNUSE_BUILTIN : BI_CNUSE_SERIAL);
-
-	/*  printf("hpc_bootinfo.platid_cpu     = 0x%08x\n",
-	    hpc_bootinfo.platid_cpu);
-	    printf("hpc_bootinfo.platid_machine = 0x%08x\n",
-	    hpc_bootinfo.platid_machine);  */
-	store_32bit_word_in_host(cpu,(unsigned char *)&hpc_bootinfo.timezone,0);
-	store_buf(cpu, 0x80000000 + machine->physical_ram_in_mb *
-	    1048576 - 256, (char *)&hpc_bootinfo, sizeof(hpc_bootinfo));
-}
-
-
-MACHINE_DEFAULT_CPU(hpcmips)
-{
-	switch (machine->machine_subtype) {
-	case MACHINE_HPCMIPS_CASIO_BE300:
-		machine->cpu_name = strdup("VR4131");
-		break;
-	case MACHINE_HPCMIPS_CASIO_E105:
-		machine->cpu_name = strdup("VR4121");
-		break;
-	case MACHINE_HPCMIPS_NEC_MOBILEPRO_770:
-	case MACHINE_HPCMIPS_NEC_MOBILEPRO_780:
-	case MACHINE_HPCMIPS_NEC_MOBILEPRO_800:
-	case MACHINE_HPCMIPS_NEC_MOBILEPRO_880:
-		machine->cpu_name = strdup("VR4121");
-		break;
-	case MACHINE_HPCMIPS_AGENDA_VR3:
-		machine->cpu_name = strdup("VR4181");
-		break;
-	case MACHINE_HPCMIPS_IBM_WORKPAD_Z50:
-		machine->cpu_name = strdup("VR4121");
-		break;
-	default:printf("Unimplemented HPCMIPS model?\n");
-		exit(1);
-	}
-}
-
-
-MACHINE_DEFAULT_RAM(hpcmips)
-{
-	/*  Most have 32 MB by default.  */
-	machine->physical_ram_in_mb = 32;
-
-	switch (machine->machine_subtype) {
-	case MACHINE_HPCMIPS_CASIO_BE300:
-		machine->physical_ram_in_mb = 16;
-		break;
-	case MACHINE_HPCMIPS_CASIO_E105:
-		machine->physical_ram_in_mb = 32;
-		break;
-	case MACHINE_HPCMIPS_AGENDA_VR3:
-		machine->physical_ram_in_mb = 16;
-		break;
-	}
-}
-
-
-MACHINE_REGISTER(hpcmips)
-{
-	MR_DEFAULT(hpcmips, "Handhelp MIPS (HPCmips)",
-	    ARCH_MIPS, MACHINE_HPCMIPS);
-
-	machine_entry_add_alias(me, "hpcmips");
-
-	machine_entry_add_subtype(me, "Casio Cassiopeia BE-300",
-	    MACHINE_HPCMIPS_CASIO_BE300, "be-300", "be300", NULL);
-
-	machine_entry_add_subtype(me, "Casio Cassiopeia E-105",
-	    MACHINE_HPCMIPS_CASIO_E105, "e-105", "e105", NULL);
-
-	machine_entry_add_subtype(me, "Agenda VR3", MACHINE_HPCMIPS_AGENDA_VR3,
-	    "agenda", "vr3", NULL);
-
-	machine_entry_add_subtype(me, "IBM WorkPad Z50",
-	    MACHINE_HPCMIPS_IBM_WORKPAD_Z50, "workpad", "z50", NULL);
-
-	machine_entry_add_subtype(me, "NEC MobilePro 770",
-	    MACHINE_HPCMIPS_NEC_MOBILEPRO_770, "mobilepro770", NULL);
-
-	machine_entry_add_subtype(me, "NEC MobilePro 780",
-	    MACHINE_HPCMIPS_NEC_MOBILEPRO_780, "mobilepro780", NULL);
-
-	machine_entry_add_subtype(me, "NEC MobilePro 800",
-	    MACHINE_HPCMIPS_NEC_MOBILEPRO_800, "mobilepro800", NULL);
-
-	machine_entry_add_subtype(me, "NEC MobilePro 880",
-	    MACHINE_HPCMIPS_NEC_MOBILEPRO_880, "mobilepro880", NULL);
-
-	me->set_default_ram = machine_default_ram_hpcmips;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_hpcsh.c gxemul-0.7.0+dfsg/src/machines/machine_hpcsh.c
--- gxemul-0.6.2/src/machines/machine_hpcsh.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_hpcsh.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,114 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Handheld SuperH-based machines
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/hpc_bootinfo.h"
+#include "thirdparty/vripreg.h"
+
+
+MACHINE_SETUP(hpcsh)
+{
+/*
+	char tmpstr[1000];
+	struct hpc_bootinfo hpc_bootinfo;
+	int hpc_platid_flags = 0, hpc_platid_cpu_submodel = 0,
+	    hpc_platid_cpu_model = 0, hpc_platid_cpu_series = 0,
+	    hpc_platid_cpu_arch = 0,
+	    hpc_platid_submodel = 0, hpc_platid_model = 0,
+	    hpc_platid_series = 0, hpc_platid_vendor = 0;
+	uint64_t hpc_fb_addr = 0;
+	int hpc_fb_bits = 0, hpc_fb_encoding = 0;
+	int hpc_fb_xsize = 0;
+	int hpc_fb_ysize = 0;
+	int hpc_fb_xsize_mem = 0;
+	int hpc_fb_ysize_mem = 0;
+
+	memset(&hpc_bootinfo, 0, sizeof(hpc_bootinfo));
+*/
+	machine->machine_name = strdup("HPCsh");
+	cpu->byte_order = EMUL_LITTLE_ENDIAN;
+
+	if (!machine->x11_md.in_use)
+		fprintf(stderr, "-------------------------------------"
+		    "------------------------------------------\n"
+		    "\n  WARNING!  You are emulating a HPCsh without -X."
+		    "\n            You will miss graphical output!\n\n"
+		    "-------------------------------------"
+		    "------------------------------------------\n");
+
+	/*  32 MB in two parts, each included twice (shadowed):  */
+	dev_ram_init(machine, 0x0c000000, 0x01000000, DEV_RAM_MIRROR, 0x0, NULL);
+	dev_ram_init(machine, 0x0d000000, 0x01000000, DEV_RAM_MIRROR, 0x0, NULL);
+	dev_ram_init(machine, 0x0e000000, 0x01000000, DEV_RAM_MIRROR, 0x01000000, NULL);
+	dev_ram_init(machine, 0x0f000000, 0x01000000, DEV_RAM_MIRROR, 0x01000000, NULL);
+
+	dev_fb_init(machine, machine->memory, 0x10000000,
+	    VFB_HPC, 640,240, 640,240, 16, machine->machine_name);
+}
+
+
+MACHINE_DEFAULT_CPU(hpcsh)
+{
+	machine->cpu_name = strdup("SH7750");
+}
+
+
+MACHINE_DEFAULT_RAM(hpcsh)
+{
+	/*  TODO: Model dependent. */
+	machine->physical_ram_in_mb = 32;
+}
+
+
+MACHINE_REGISTER(hpcsh)
+{
+	MR_DEFAULT(hpcsh, "Handhelp SH (HPCsh)", MACHINE_HPCSH);
+
+	machine_entry_add_alias(me, "hpcsh");
+
+	machine_entry_add_subtype(me, "Jornada 680",
+	    MACHINE_HPCSH_JORNADA680, "jornada680", NULL);
+
+	machine_entry_add_subtype(me, "Jornada 690",
+	    MACHINE_HPCSH_JORNADA690, "jornada690", NULL);
+
+	me->set_default_ram = machine_default_ram_hpcsh;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_hpcsh.cc gxemul-0.7.0+dfsg/src/machines/machine_hpcsh.cc
--- gxemul-0.6.2/src/machines/machine_hpcsh.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_hpcsh.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,116 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Handheld SuperH-based machines
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/hpc_bootinfo.h"
-#include "thirdparty/vripreg.h"
-
-
-MACHINE_SETUP(hpcsh)
-{
-/*
-	char tmpstr[1000];
-	struct hpc_bootinfo hpc_bootinfo;
-	int hpc_platid_flags = 0, hpc_platid_cpu_submodel = 0,
-	    hpc_platid_cpu_model = 0, hpc_platid_cpu_series = 0,
-	    hpc_platid_cpu_arch = 0,
-	    hpc_platid_submodel = 0, hpc_platid_model = 0,
-	    hpc_platid_series = 0, hpc_platid_vendor = 0;
-	uint64_t hpc_fb_addr = 0;
-	int hpc_fb_bits = 0, hpc_fb_encoding = 0;
-	int hpc_fb_xsize = 0;
-	int hpc_fb_ysize = 0;
-	int hpc_fb_xsize_mem = 0;
-	int hpc_fb_ysize_mem = 0;
-
-	memset(&hpc_bootinfo, 0, sizeof(hpc_bootinfo));
-*/
-	machine->machine_name = strdup("HPCsh");
-	cpu->byte_order = EMUL_LITTLE_ENDIAN;
-
-	if (!machine->x11_md.in_use)
-		fprintf(stderr, "-------------------------------------"
-		    "------------------------------------------\n"
-		    "\n  WARNING!  You are emulating a HPCsh without -X."
-		    "\n            You will miss graphical output!\n\n"
-		    "-------------------------------------"
-		    "------------------------------------------\n");
-
-	/*  32 MB in two parts, each included twice (shadowed):  */
-	dev_ram_init(machine, 0x0c000000, 0x01000000, DEV_RAM_MIRROR, 0x0);
-	dev_ram_init(machine, 0x0d000000, 0x01000000, DEV_RAM_MIRROR, 0x0);
-	dev_ram_init(machine, 0x0e000000, 0x01000000, DEV_RAM_MIRROR,
-	    0x01000000);
-	dev_ram_init(machine, 0x0f000000, 0x01000000, DEV_RAM_MIRROR,
-	    0x01000000);
-
-	dev_fb_init(machine, machine->memory, 0x10000000,
-	    VFB_HPC, 640,240, 640,240, 16, machine->machine_name);
-}
-
-
-MACHINE_DEFAULT_CPU(hpcsh)
-{
-	machine->cpu_name = strdup("SH7750");
-}
-
-
-MACHINE_DEFAULT_RAM(hpcsh)
-{
-	/*  TODO: Model dependent. */
-	machine->physical_ram_in_mb = 32;
-}
-
-
-MACHINE_REGISTER(hpcsh)
-{
-	MR_DEFAULT(hpcsh, "Handhelp SH (HPCsh)", ARCH_SH, MACHINE_HPCSH);
-
-	machine_entry_add_alias(me, "hpcsh");
-
-	machine_entry_add_subtype(me, "Jornada 680",
-	    MACHINE_HPCSH_JORNADA680, "jornada680", NULL);
-
-	machine_entry_add_subtype(me, "Jornada 690",
-	    MACHINE_HPCSH_JORNADA690, "jornada690", NULL);
-
-	me->set_default_ram = machine_default_ram_hpcsh;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_iq80321.c gxemul-0.7.0+dfsg/src/machines/machine_iq80321.c
--- gxemul-0.6.2/src/machines/machine_iq80321.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_iq80321.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,109 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Intel IQ80321 (ARM)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+MACHINE_SETUP(iq80321)
+{
+	char tmpstr[300];
+	struct pci_data *pci;
+
+	/*
+	 *  Intel IQ80321. See http://sources.redhat.com/ecos/
+	 *	docs-latest/redboot/iq80321.html
+	 *  for more details about the memory map.
+	 */
+
+	machine->machine_name = strdup("Intel IQ80321");
+
+	cpu->cd.arm.coproc[6] = arm_coproc_i80321_6;
+
+	snprintf(tmpstr, sizeof(tmpstr), "i80321 irq=%s.cpu[%i].irq "
+	    "addr=0xffffe000", machine->path, machine->bootstrap_cpu);
+	pci = (struct pci_data *) device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].irq."
+	    "i80321.%i addr=0xfe800000 name2='serial console'",
+	    machine->path, machine->bootstrap_cpu, 28);
+	device_add(machine, tmpstr);
+
+	/*  0xa0000000 = physical ram, 0xc0000000 = uncached  */
+	dev_ram_init(machine, 0xa0000000, 0x20000000, DEV_RAM_MIRROR, 0x0, NULL);
+	dev_ram_init(machine, 0xc0000000, 0x20000000, DEV_RAM_MIRROR, 0x0, NULL);
+
+	/*  0xe0000000 and 0xff000000 = cache flush regions  */
+	dev_ram_init(machine, 0xe0000000, 0x100000, DEV_RAM_RAM, 0x0, NULL);
+	dev_ram_init(machine, 0xff000000, 0x100000, DEV_RAM_RAM, 0x0, NULL);
+
+	device_add(machine, "iq80321_7seg addr=0xfe840000");
+
+	/*  TODO: "Intel i82546EB 1000BASE-T Ethernet"  */
+
+	/*
+	 *  "Intel 31244 Serial ATA Controller", must be at device 6 according
+	 *  to NetBSD's iq80321/iq80321_pci.c:iq80321_pci_intr_map().
+	 */
+	bus_pci_add(machine, pci, machine->memory, 0, 6, 0, "i31244");
+
+	if (!machine->prom_emulation)
+		return;
+
+	arm_setup_initial_translation_table(cpu, 0x4000);
+	arm_translation_table_set_l1(cpu, 0xa0000000, 0xa0000000);
+	arm_translation_table_set_l1(cpu, 0xc0000000, 0xa0000000);
+	arm_translation_table_set_l1(cpu, 0xe0000000, 0xe0000000);
+	arm_translation_table_set_l1(cpu, 0xf0000000, 0xf0000000);
+}
+
+
+MACHINE_DEFAULT_CPU(iq80321)
+{
+	machine->cpu_name = strdup("80321_600_2");
+}
+
+
+MACHINE_REGISTER(iq80321)
+{
+	MR_DEFAULT(iq80321, "Intel IQ80321", MACHINE_IQ80321);
+
+	machine_entry_add_alias(me, "iq80321");
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_iq80321.cc gxemul-0.7.0+dfsg/src/machines/machine_iq80321.cc
--- gxemul-0.6.2/src/machines/machine_iq80321.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_iq80321.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,109 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Intel IQ80321 (ARM)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-MACHINE_SETUP(iq80321)
-{
-	char tmpstr[300];
-	struct pci_data *pci;
-
-	/*
-	 *  Intel IQ80321. See http://sources.redhat.com/ecos/
-	 *	docs-latest/redboot/iq80321.html
-	 *  for more details about the memory map.
-	 */
-
-	machine->machine_name = strdup("Intel IQ80321");
-
-	cpu->cd.arm.coproc[6] = arm_coproc_i80321_6;
-
-	snprintf(tmpstr, sizeof(tmpstr), "i80321 irq=%s.cpu[%i].irq "
-	    "addr=0xffffe000", machine->path, machine->bootstrap_cpu);
-	pci = (struct pci_data *) device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].irq."
-	    "i80321.%i addr=0xfe800000 name2='serial console'",
-	    machine->path, machine->bootstrap_cpu, 28);
-	device_add(machine, tmpstr);
-
-	/*  0xa0000000 = physical ram, 0xc0000000 = uncached  */
-	dev_ram_init(machine, 0xa0000000, 0x20000000, DEV_RAM_MIRROR, 0x0);
-	dev_ram_init(machine, 0xc0000000, 0x20000000, DEV_RAM_MIRROR, 0x0);
-
-	/*  0xe0000000 and 0xff000000 = cache flush regions  */
-	dev_ram_init(machine, 0xe0000000, 0x100000, DEV_RAM_RAM, 0x0);
-	dev_ram_init(machine, 0xff000000, 0x100000, DEV_RAM_RAM, 0x0);
-
-	device_add(machine, "iq80321_7seg addr=0xfe840000");
-
-	/*  TODO: "Intel i82546EB 1000BASE-T Ethernet"  */
-
-	/*
-	 *  "Intel 31244 Serial ATA Controller", must be at device 6 according
-	 *  to NetBSD's iq80321/iq80321_pci.c:iq80321_pci_intr_map().
-	 */
-	bus_pci_add(machine, pci, machine->memory, 0, 6, 0, "i31244");
-
-	if (!machine->prom_emulation)
-		return;
-
-	arm_setup_initial_translation_table(cpu, 0x4000);
-	arm_translation_table_set_l1(cpu, 0xa0000000, 0xa0000000);
-	arm_translation_table_set_l1(cpu, 0xc0000000, 0xa0000000);
-	arm_translation_table_set_l1(cpu, 0xe0000000, 0xe0000000);
-	arm_translation_table_set_l1(cpu, 0xf0000000, 0xf0000000);
-}
-
-
-MACHINE_DEFAULT_CPU(iq80321)
-{
-	machine->cpu_name = strdup("80321_600_2");
-}
-
-
-MACHINE_REGISTER(iq80321)
-{
-	MR_DEFAULT(iq80321, "Intel IQ80321", ARCH_ARM, MACHINE_IQ80321);
-
-	machine_entry_add_alias(me, "iq80321");
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_iyonix.c gxemul-0.7.0+dfsg/src/machines/machine_iyonix.c
--- gxemul-0.6.2/src/machines/machine_iyonix.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_iyonix.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,136 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: A Iyonix machine
+ *
+ *  According to NetBSD/iyonix, for Tungsten motherboards:
+ *
+ *	0x90000000 (1 MB)	obio
+ *	    0x900002f8 = uart1
+ *	0xa0000000 (8 MB)	Flash memory
+ *	0xfe400000		iopxs vbase
+ *
+ *  A dmesg can be found at the end of the following URL:
+ *  http://www.sarasarado.org/~hatano/diary/d200411.html
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "bus_isa.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/netbsd_iyonix_bootconfig.h"
+#include "thirdparty/i80321reg.h"
+
+
+MACHINE_SETUP(iyonix)
+{
+	char tmpstr[1000];
+	uint32_t bootblock_addr;
+	struct bootconfig bootconfigData;
+
+	machine->machine_name = strdup("Iyonix");
+
+	cpu->cd.arm.coproc[6] = arm_coproc_i80321_6;
+
+	/*  TODO: Is it flash, or just RAM?  */
+	dev_ram_init(machine, 0xa0000000,
+	    machine->physical_ram_in_mb * 1048576, DEV_RAM_MIRROR, 0x0, NULL);
+
+	/*  Uncached RAM?  */
+	dev_ram_init(machine, 0xc0000000,
+	    machine->physical_ram_in_mb * 1048576, DEV_RAM_MIRROR, 0x0, NULL);
+
+	snprintf(tmpstr, sizeof(tmpstr), "i80321 irq=%s.cpu[%i].irq "
+	    "addr=0x%08x", machine->path, machine->bootstrap_cpu,
+	    (int) VERDE_PMMR_BASE);
+	device_add(machine, tmpstr);
+
+	/*  TODO: actual irq on the i80321!  */
+	snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].irq.i80321.1",
+	    machine->path, machine->bootstrap_cpu);
+	bus_isa_init(machine, tmpstr, 0, 0x90000000ULL, 0x98000000ULL);
+
+	if (!machine->prom_emulation)
+		return;
+
+
+	/*
+	 *  Set up suitable virtual memory mappings and bootconfig struct
+	 *  in order to boot a plain NetBSD/iyonix ELF kernel:
+	 *
+	 *  r0 is expected to point to the bootconfig struct.
+	 */
+
+	arm_setup_initial_translation_table(cpu,
+	    machine->physical_ram_in_mb * 1048576 - 65536);
+	arm_translation_table_set_l1(cpu, 0x90000000, 0x90000000);
+	arm_translation_table_set_l1(cpu, 0xf0000000, 0x00000000);
+	arm_translation_table_set_l1_b(cpu, 0xff000000, 0xff000000);
+
+	bootblock_addr = machine->physical_ram_in_mb * 1048576 - 65536 - 16384;
+	cpu->cd.arm.r[0] = bootblock_addr;
+	memset(&bootconfigData, 0, sizeof(bootconfigData));
+
+	store_32bit_word_in_host(cpu, (unsigned char *)
+	    &bootconfigData.magic, BOOTCONFIG_MAGIC);
+	store_32bit_word_in_host(cpu, (unsigned char *)
+	    &bootconfigData.version, BOOTCONFIG_VERSION);
+
+	/*  TODO: More fields.  */
+
+	store_buf(cpu, bootblock_addr, (char *)&bootconfigData, sizeof(bootconfigData));
+}
+
+
+MACHINE_DEFAULT_CPU(iyonix)
+{
+	machine->cpu_name = strdup("80321_600_B0");
+}
+
+
+MACHINE_DEFAULT_RAM(iyonix)
+{
+	machine->physical_ram_in_mb = 64;
+}
+
+
+MACHINE_REGISTER(iyonix)
+{
+	MR_DEFAULT(iyonix, "Iyonix", MACHINE_IYONIX);
+
+	machine_entry_add_alias(me, "iyonix");
+
+	me->set_default_ram = machine_default_ram_iyonix;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_iyonix.cc gxemul-0.7.0+dfsg/src/machines/machine_iyonix.cc
--- gxemul-0.6.2/src/machines/machine_iyonix.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_iyonix.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,136 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: A Iyonix machine
- *
- *  According to NetBSD/iyonix, for Tungsten motherboards:
- *
- *	0x90000000 (1 MB)	obio
- *	    0x900002f8 = uart1
- *	0xa0000000 (8 MB)	Flash memory
- *	0xfe400000		iopxs vbase
- *
- *  A dmesg can be found at the end of the following URL:
- *  http://www.sarasarado.org/~hatano/diary/d200411.html
- */
-
-#include <stdio.h>
-#include <string.h>
-
-#include "bus_isa.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/netbsd_iyonix_bootconfig.h"
-#include "thirdparty/i80321reg.h"
-
-
-MACHINE_SETUP(iyonix)
-{
-	char tmpstr[1000];
-	uint32_t bootblock_addr;
-	struct bootconfig bootconfigData;
-
-	machine->machine_name = strdup("Iyonix");
-
-	cpu->cd.arm.coproc[6] = arm_coproc_i80321_6;
-
-	/*  TODO: Is it flash, or just RAM?  */
-	dev_ram_init(machine, 0xa0000000,
-	    machine->physical_ram_in_mb * 1048576, DEV_RAM_MIRROR, 0x0);
-
-	/*  Uncached RAM?  */
-	dev_ram_init(machine, 0xc0000000,
-	    machine->physical_ram_in_mb * 1048576, DEV_RAM_MIRROR, 0x0);
-
-	snprintf(tmpstr, sizeof(tmpstr), "i80321 irq=%s.cpu[%i].irq "
-	    "addr=0x%08x", machine->path, machine->bootstrap_cpu,
-	    (int) VERDE_PMMR_BASE);
-	device_add(machine, tmpstr);
-
-	/*  TODO: actual irq on the i80321!  */
-	snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].irq.i80321.1",
-	    machine->path, machine->bootstrap_cpu);
-	bus_isa_init(machine, tmpstr, 0, 0x90000000ULL, 0x98000000ULL);
-
-	if (!machine->prom_emulation)
-		return;
-
-
-	/*
-	 *  Set up suitable virtual memory mappings and bootconfig struct
-	 *  in order to boot a plain NetBSD/iyonix ELF kernel:
-	 *
-	 *  r0 is expected to point to the bootconfig struct.
-	 */
-
-	arm_setup_initial_translation_table(cpu,
-	    machine->physical_ram_in_mb * 1048576 - 65536);
-	arm_translation_table_set_l1(cpu, 0x90000000, 0x90000000);
-	arm_translation_table_set_l1(cpu, 0xf0000000, 0x00000000);
-	arm_translation_table_set_l1_b(cpu, 0xff000000, 0xff000000);
-
-	bootblock_addr = machine->physical_ram_in_mb * 1048576 - 65536 - 16384;
-	cpu->cd.arm.r[0] = bootblock_addr;
-	memset(&bootconfigData, 0, sizeof(bootconfigData));
-
-	store_32bit_word_in_host(cpu, (unsigned char *)
-	    &bootconfigData.magic, BOOTCONFIG_MAGIC);
-	store_32bit_word_in_host(cpu, (unsigned char *)
-	    &bootconfigData.version, BOOTCONFIG_VERSION);
-
-	/*  TODO: More fields.  */
-
-	store_buf(cpu, bootblock_addr, (char *)&bootconfigData, sizeof(bootconfigData));
-}
-
-
-MACHINE_DEFAULT_CPU(iyonix)
-{
-	machine->cpu_name = strdup("80321_600_B0");
-}
-
-
-MACHINE_DEFAULT_RAM(iyonix)
-{
-	machine->physical_ram_in_mb = 64;
-}
-
-
-MACHINE_REGISTER(iyonix)
-{
-	MR_DEFAULT(iyonix, "Iyonix", ARCH_ARM, MACHINE_IYONIX);
-
-	machine_entry_add_alias(me, "iyonix");
-
-	me->set_default_ram = machine_default_ram_iyonix;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_landisk.c gxemul-0.7.0+dfsg/src/machines/machine_landisk.c
--- gxemul-0.6.2/src/machines/machine_landisk.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_landisk.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,145 @@
+/*
+ *  Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: I-O DATA LanDisk USL-5P
+ *
+ *  This machine consists of:
+ *
+ *	o)  An SH4 processor, which includes serial console etc,
+ *	o)  64 MB RAM (at 0x0c000000),
+ *	o)  an IDE controller at address 0x14000000 (irq 10),
+ *	o)  a RS5C313 real time clock, connected to the SH4 SCI port,
+ *	o)  a PCI controller (PCIC),
+ *	o)  and a minimal SH-IPL+G PROM emulation layer (required to make
+ *	    OpenBSD/landisk boot).
+ *
+ *  TODO:
+ *	Realtek NIC (irq 5), PCIIDE (irq 6), USB controllers, etc.
+ *
+ *  TODO 2:
+ *	Make it possible to select different landisk models.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/sh4_exception.h"
+#include "thirdparty/sh4_scireg.h"
+
+
+/*  This is not really implemented yet: (experimental)  */
+/*  #define INCLUDE_LANDISK_NIC  */
+
+
+MACHINE_SETUP(landisk)
+{
+#ifdef INCLUDE_LANDISK_NIC
+	struct pci_data *pcibus =
+	    machine->cpus[machine->bootstrap_cpu]->cd.sh.pcic_pcibus;
+#endif
+	char tmpstr[300];
+
+	machine->machine_name = strdup("Landisk USL-5P");
+
+	/*  266.67 MHz SH4 CPU clock:  */
+	if (machine->emulated_hz == 0)
+		machine->emulated_hz = 266666666;
+
+	/*  33.33 MHz SH4 PCLOCK:  */
+	machine->cpus[machine->bootstrap_cpu]->cd.sh.pclock = 33333333;
+
+	/*  Note: 64 MB RAM at 0x0c000000, not at 0x00000000.  */
+	dev_ram_init(machine, 0x0c000000, 64 * 1048576, DEV_RAM_RAM, 0x0, NULL);
+
+	/*  wdc0 at obio0 port 0x14000000-0x1400000f irq 10  */
+	snprintf(tmpstr, sizeof(tmpstr), "wdc irq=%s.cpu[%i].irq[0x%x]"
+	    " addr_mult=2 addr=0x14000000",
+	    machine->path, machine->bootstrap_cpu, SH4_INTEVT_IRQ10);
+	device_add(machine, tmpstr);
+
+	/*  rsclock0 at shb0: RS5C313 real time clock  */
+	snprintf(tmpstr, sizeof(tmpstr), "rs5c313 addr=0x%" PRIx64,
+	    (uint64_t) SCI_DEVICE_BASE);
+	device_add(machine, tmpstr);
+
+#ifdef INCLUDE_LANDISK_NIC
+	/*  Realtek PCI NIC:  */
+	bus_pci_add(machine, pcibus, machine->memory, 0, 0, 0, "rtl8139c");
+#endif
+
+	if (!machine->prom_emulation)
+		return;
+
+	/*
+	 *  Ugly hardcoded register contents at bootup:
+	 *
+	 *  r4 (arg 0) = boot howto flags
+	 *  r5 (arg 1) = bootinfo pointer for NetBSD (?) and
+	 *               symbol end pointer for OpenBSD (?)
+	 *
+	 *  TODO: Make nicer.
+	 */
+	cpu->cd.sh.r[4] = 0;
+	cpu->cd.sh.r[5] = 0x8c000000 + 10 * 1048576;	/*  Note/TODO:
+				Assuming hardcoded 10 MB kernel size!  */
+
+	sh_ipl_g_emul_init(machine);
+}
+
+
+MACHINE_DEFAULT_CPU(landisk)
+{
+	/*  Hitachi SH4 7751R, 266.67 MHz  */
+	machine->cpu_name = strdup("SH7751R");
+}
+
+
+MACHINE_DEFAULT_RAM(landisk)
+{
+	/*  Note: This is the size of the boot ROM area, since the
+	    Landisk's RAM isn't located at physical address zero.  */
+	machine->physical_ram_in_mb = 2;
+}
+
+
+MACHINE_REGISTER(landisk)
+{
+	MR_DEFAULT(landisk, "Landisk", MACHINE_LANDISK);
+	me->set_default_ram = machine_default_ram_landisk;
+
+	machine_entry_add_alias(me, "landisk");
+	machine_entry_add_alias(me, "usl-5p");
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_landisk.cc gxemul-0.7.0+dfsg/src/machines/machine_landisk.cc
--- gxemul-0.6.2/src/machines/machine_landisk.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_landisk.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,145 +0,0 @@
-/*
- *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: I-O DATA LanDisk USL-5P
- *
- *  This machine consists of:
- *
- *	o)  An SH4 processor, which includes serial console etc,
- *	o)  64 MB RAM (at 0x0c000000),
- *	o)  an IDE controller at address 0x14000000 (irq 10),
- *	o)  a RS5C313 real time clock, connected to the SH4 SCI port,
- *	o)  a PCI controller (PCIC),
- *	o)  and a minimal SH-IPL+G PROM emulation layer (required to make
- *	    OpenBSD/landisk boot).
- *
- *  TODO:
- *	Realtek NIC (irq 5), PCIIDE (irq 6), USB controllers, etc.
- *
- *  TODO 2:
- *	Make it possible to select different landisk models.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/sh4_exception.h"
-#include "thirdparty/sh4_scireg.h"
-
-
-/*  This is not really implemented yet: (experimental)  */
-/*  #define INCLUDE_LANDISK_NIC  */
-
-
-MACHINE_SETUP(landisk)
-{
-#ifdef INCLUDE_LANDISK_NIC
-	struct pci_data *pcibus =
-	    machine->cpus[machine->bootstrap_cpu]->cd.sh.pcic_pcibus;
-#endif
-	char tmpstr[300];
-
-	machine->machine_name = strdup("Landisk USL-5P");
-
-	/*  266.67 MHz SH4 CPU clock:  */
-	if (machine->emulated_hz == 0)
-		machine->emulated_hz = 266666666;
-
-	/*  33.33 MHz SH4 PCLOCK:  */
-	machine->cpus[machine->bootstrap_cpu]->cd.sh.pclock = 33333333;
-
-	/*  Note: 64 MB RAM at 0x0c000000, not at 0x00000000.  */
-	dev_ram_init(machine, 0x0c000000, 64 * 1048576, DEV_RAM_RAM, 0x0);
-
-	/*  wdc0 at obio0 port 0x14000000-0x1400000f irq 10  */
-	snprintf(tmpstr, sizeof(tmpstr), "wdc irq=%s.cpu[%i].irq[0x%x]"
-	    " addr_mult=2 addr=0x14000000",
-	    machine->path, machine->bootstrap_cpu, SH4_INTEVT_IRQ10);
-	device_add(machine, tmpstr);
-
-	/*  rsclock0 at shb0: RS5C313 real time clock  */
-	snprintf(tmpstr, sizeof(tmpstr), "rs5c313 addr=0x%" PRIx64,
-	    (uint64_t) SCI_DEVICE_BASE);
-	device_add(machine, tmpstr);
-
-#ifdef INCLUDE_LANDISK_NIC
-	/*  Realtek PCI NIC:  */
-	bus_pci_add(machine, pcibus, machine->memory, 0, 0, 0, "rtl8139c");
-#endif
-
-	if (!machine->prom_emulation)
-		return;
-
-	/*
-	 *  Ugly hardcoded register contents at bootup:
-	 *
-	 *  r4 (arg 0) = boot howto flags
-	 *  r5 (arg 1) = bootinfo pointer for NetBSD (?) and
-	 *               symbol end pointer for OpenBSD (?)
-	 *
-	 *  TODO: Make nicer.
-	 */
-	cpu->cd.sh.r[4] = 0;
-	cpu->cd.sh.r[5] = 0x8c000000 + 10 * 1048576;	/*  Note/TODO:
-				Assuming hardcoded 10 MB kernel size!  */
-
-	sh_ipl_g_emul_init(machine);
-}
-
-
-MACHINE_DEFAULT_CPU(landisk)
-{
-	/*  Hitachi SH4 7751R, 266.67 MHz  */
-	machine->cpu_name = strdup("SH7751R");
-}
-
-
-MACHINE_DEFAULT_RAM(landisk)
-{
-	/*  Note: This is the size of the boot ROM area, since the
-	    Landisk's RAM isn't located at physical address zero.  */
-	machine->physical_ram_in_mb = 2;
-}
-
-
-MACHINE_REGISTER(landisk)
-{
-	MR_DEFAULT(landisk, "Landisk", ARCH_SH, MACHINE_LANDISK);
-	me->set_default_ram = machine_default_ram_landisk;
-
-	machine_entry_add_alias(me, "landisk");
-	machine_entry_add_alias(me, "usl-5p");
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_luna88k.c gxemul-0.7.0+dfsg/src/machines/machine_luna88k.c
--- gxemul-0.6.2/src/machines/machine_luna88k.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_luna88k.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,156 @@
+/*
+ *  Copyright (C) 2008-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: LUNA88K machine
+ *
+ *  This is for experiments with OpenBSD/luna88k. See
+ *  openbsd/sys/arch/luna88k/luna88k/locore0.S for more information about
+ *  how OpenBSD starts up on this platform.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/luna88k_board.h"
+
+
+MACHINE_SETUP(luna88k)
+{
+	const char* luna88k2_fuse_string = "MNAME=LUNA88K+";
+	size_t i;
+
+	device_add(machine, "luna88k");
+
+	if (machine->physical_ram_in_mb > MAXPHYSMEM / 1048576)
+		debugmsg(SUBSYS_MACHINE, "memory", VERBOSITY_WARNING,
+		    "WARNING: %i MB RAM is more than MAXPHYSMEM (%i MB)!",
+		    machine->physical_ram_in_mb,
+		    MAXPHYSMEM / 1048576);
+
+	switch (machine->machine_subtype) {
+
+	case MACHINE_LUNA_88K:
+		machine->machine_name = strdup("LUNA 88K");
+		if (machine->physical_ram_in_mb > 64)
+			debugmsg(SUBSYS_MACHINE, "memory", VERBOSITY_WARNING,
+			    "WARNING: %i MB RAM is more than 64 MB (max on a real LUNA 88K)!",
+			    machine->physical_ram_in_mb);
+		break;
+
+	case MACHINE_LUNA_88K2:
+		machine->machine_name = strdup("LUNA 88K2");
+		if (machine->physical_ram_in_mb > 112)
+			debugmsg(SUBSYS_MACHINE, "memory", VERBOSITY_WARNING,
+			    "WARNING: %i MB RAM is more than 112 MB (max on a real LUNA 88K2)!",
+			    machine->physical_ram_in_mb);
+
+		/*  According to OpenBSD source code,
+		    the string "MNAME=LUNA88K+" in FUSE_ROM_DATA
+		    is used to determine that this is a 88K2, and
+		    not an 88K.
+	                fuse_rom_data[i] =
+	                    (char)((((p->h) >> 24) & 0x000000f0) |
+	                           (((p->l) >> 28) & 0x0000000f));
+		    where h is first 32-bit word, l is second.
+		*/
+
+		for (i = 0; i < strlen(luna88k2_fuse_string); ++i) {
+			uint32_t h = luna88k2_fuse_string[i] & 0xf0;
+			uint32_t l = luna88k2_fuse_string[i] & 0x0f;
+			store_32bit_word(cpu, FUSE_ROM_ADDR + i * 8 + 0, h << 24);
+			store_32bit_word(cpu, FUSE_ROM_ADDR + i * 8 + 4, l << 28);
+		}
+
+		break;
+
+	default:fatal("Unimplemented LUNA88K machine subtype %i\n",
+		    machine->machine_subtype);
+		exit(1);
+	}
+
+	if (machine->ncpus > 4) {
+		fatal("More than 4 CPUs is not supported for LUNA 88K.\n");
+		exit(1);
+	}
+
+	// Unpause all CPUs. (Normally, the emulator only starts with
+	// one CPU running, and it is up to the OS to enable the rest,
+	// but on real LUNA-88K machines, all CPUs are started to run
+	// the OS kernel code simultaneously and it is up to the OS
+	// kernel's initial code to sort things out.)
+	for (i = 0; i < (size_t)machine->ncpus; ++i)
+		machine->cpus[i]->running = true;
+
+	// machine_add_devices_as_symbols(machine, 0);
+
+	if (!machine->prom_emulation)
+		return;
+
+	luna88kprom_init(machine);
+}
+
+
+MACHINE_DEFAULT_CPU(luna88k)
+{
+	machine->cpu_name = strdup("88100");
+}
+
+
+MACHINE_DEFAULT_RAM(luna88k)
+{
+	// Two OpenBSD dmesgs found on the Internet for a LUNA-88K2 showed
+	// 112 MB of real mem. The max for LUNA-88K was probably 64 MB.
+	if (machine->machine_subtype == MACHINE_LUNA_88K2)
+		machine->physical_ram_in_mb = 112;
+	else
+		machine->physical_ram_in_mb = 64;
+}
+
+
+MACHINE_REGISTER(luna88k)
+{
+	MR_DEFAULT(luna88k, "LUNA88K", MACHINE_LUNA88K);
+
+	machine_entry_add_alias(me, "luna88k");
+
+	machine_entry_add_subtype(me, "LUNA-88K", MACHINE_LUNA_88K,
+	    "luna-88k", NULL);
+
+	machine_entry_add_subtype(me, "LUNA-88K2", MACHINE_LUNA_88K2,
+	    "luna-88k2", NULL);
+
+	me->set_default_ram = machine_default_ram_luna88k;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_luna88k.cc gxemul-0.7.0+dfsg/src/machines/machine_luna88k.cc
--- gxemul-0.6.2/src/machines/machine_luna88k.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_luna88k.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,133 +0,0 @@
-/*
- *  Copyright (C) 2008-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: LUNA88K machine
- *
- *  This is for experiments with OpenBSD/luna88k. See
- *  openbsd/sys/arch/luna88k/luna88k/locore0.S for more information about
- *  how OpenBSD starts up on this platform.
- *
- *  RAMDISK kernel used for experiments:
- *
- *	https://ftp.eu.openbsd.org/pub/OpenBSD/6.2/luna88k/bsd.rd
- *
- *  Launch with   gxemul -e luna-88k2 -Ttv bsd.rd
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/luna88k_board.h"
-
-
-MACHINE_SETUP(luna88k)
-{
-	const char* luna88k2_fuse_string = "MNAME=LUNA88K+";
-
-	device_add(machine, "luna88k");
-
-	switch (machine->machine_subtype) {
-
-	case MACHINE_LUNA_88K:
-		machine->machine_name = strdup("LUNA 88K");
-		break;
-
-	case MACHINE_LUNA_88K2:
-		machine->machine_name = strdup("LUNA 88K2");
-
-		/*  According to OpenBSD source code,
-		    the string "MNAME=LUNA88K+" in FUSE_ROM_DATA
-		    is used to determine that this is a 88K2, and
-		    not an 88K.
-	                fuse_rom_data[i] =
-	                    (char)((((p->h) >> 24) & 0x000000f0) |
-	                           (((p->l) >> 28) & 0x0000000f));
-		    where h is first 32-bit word, l is second.
-		*/
-
-		for (size_t i = 0; i < strlen(luna88k2_fuse_string); ++i) {
-			uint32_t h = luna88k2_fuse_string[i] & 0xf0;
-			uint32_t l = luna88k2_fuse_string[i] & 0x0f;
-			store_32bit_word(cpu, FUSE_ROM_ADDR + i * 8 + 0, h << 24);
-			store_32bit_word(cpu, FUSE_ROM_ADDR + i * 8 + 4, l << 28);
-		}
-
-		break;
-
-	default:fatal("Unimplemented LUNA88K machine subtype %i\n",
-		    machine->machine_subtype);
-		exit(1);
-	}
-
-	if (machine->ncpus > 4) {
-		fatal("More than 4 CPUs is not supported for LUNA 88K.\n");
-		exit(1);
-	}
-
-	if (!machine->prom_emulation)
-		return;
-
-	luna88kprom_init(machine);
-}
-
-
-MACHINE_DEFAULT_CPU(luna88k)
-{
-	machine->cpu_name = strdup("88100");
-}
-
-
-MACHINE_DEFAULT_RAM(luna88k)
-{
-	// Two OpenBSD dmesgs found on the Internet for a LUNA-88K2 showed 112 MB of real mem.
-	machine->physical_ram_in_mb = 112;
-}
-
-
-MACHINE_REGISTER(luna88k)
-{
-	MR_DEFAULT(luna88k, "LUNA88K", ARCH_M88K, MACHINE_LUNA88K);
-
-	machine_entry_add_alias(me, "luna88k");
-
-	machine_entry_add_subtype(me, "LUNA-88K", MACHINE_LUNA_88K,
-	    "luna-88k", NULL);
-
-	machine_entry_add_subtype(me, "LUNA-88K2", MACHINE_LUNA_88K2,
-	    "luna-88k2", NULL);
-
-	me->set_default_ram = machine_default_ram_luna88k;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_macppc.c gxemul-0.7.0+dfsg/src/machines/machine_macppc.c
--- gxemul-0.6.2/src/machines/machine_macppc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_macppc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,201 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Generic PowerPC-based Macintosh machines
+ *
+ *  See also:
+ *
+ *	NetBSD/macppc (http://www.netbsd.org/ports/macppc/)
+ *	OpenBSD/macppc (http://www.openbsd.org/macppc.html)
+ *
+ *  Currently, these are skeletons for generic PowerMac G3, G4, and G5 systems.
+ *  They do not model real PowerMacs, but should be enough to begin
+ *  experimenting with running NetBSD/macppc and OpenBSD/macppc.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "of.h"
+
+
+MACHINE_SETUP(macppc)
+{
+	char tmpstr[300];
+	struct pci_data *pci_data;
+	struct vfb_data *fb;
+	uint64_t b, a;
+	int i;
+
+	machine->machine_name = strdup("Macintosh (PPC)");
+	if (machine->emulated_hz == 0)
+		machine->emulated_hz = 40000000;
+
+	device_add(machine, "gc addr=0xf3000000");
+
+	pci_data = dev_uninorth_init(machine, machine->memory, 0xe2000000,
+	    64 /*  isa irq base */, 0 /*  pci irq: TODO */);
+
+	/*  bus_pci_add(
+	    machine, pci_data, machine->memory, 0, 12, 0, "dec21143");  */
+	bus_pci_add(machine, pci_data, machine->memory, 0, 15, 0, "gc_obio");
+
+	if (machine->x11_md.in_use)
+		bus_pci_add(machine, pci_data, machine->memory, 0, 16, 0,
+		    "ati_radeon_9200_2");
+
+	snprintf(tmpstr, sizeof(tmpstr), "z8530 addr=0xf3013000 irq="
+	    "%s.cpu[%i].gc.lo.23 addr_mult=0x10",
+	    machine->path, machine->bootstrap_cpu);
+	machine->main_console_handle = (size_t)device_add(machine, tmpstr);
+
+	fb = dev_fb_init(machine, machine->memory, 0xf1000000,
+	    VFB_GENERIC | VFB_REVERSE_START, 1024,768, 1024,768, 8, "ofb");
+
+	device_add(machine, "hammerhead addr=0xf2800000");
+
+	snprintf(tmpstr, sizeof(tmpstr), "adb addr=0xf3016000 irq="
+	    "%s.cpu[%i].gc.lo.1", machine->path, machine->bootstrap_cpu);
+	device_add(machine, tmpstr);
+
+	if (!machine->prom_emulation)
+		return;
+
+
+	b = 8 * 1048576; a = b - 0x800;
+
+	of_emul_init(machine, fb, 0xf1000000, 1024, 768);
+	of_emul_init_uninorth(machine);
+
+	if (machine->x11_md.in_use)
+		of_emul_init_adb(machine);
+	else
+		of_emul_init_zs(machine);
+
+	/*
+	 *  r3 = pointer to boot_args (for the Mach kernel).
+	 *  See http://darwinsource.opendarwin.org/10.3/
+	 *  BootX-59/bootx.tproj/include.subproj/boot_args.h
+	 *  for more info.
+	 */
+	cpu->cd.ppc.gpr[3] = a;
+	store_16bit_word(cpu, a + 0x0000, 1);	/*  revision  */
+	store_16bit_word(cpu, a + 0x0002, 2);	/*  version  */
+	store_buf(cpu, a + 0x0004, machine->boot_string_argument, 256);
+	/*  26 dram banks; "long base; long size"  */
+	store_32bit_word(cpu, a + 0x0104, 0);	/*  base  */
+	store_32bit_word(cpu, a + 0x0108, machine->physical_ram_in_mb
+	    * 256);		/*  size (in pages)  */
+	for (i=8; i<26*8; i+= 4)
+		store_32bit_word(cpu, a + 0x0104 + i, 0);
+	a += (0x104 + 26 * 8);
+	/*  Video info:  */
+	store_32bit_word(cpu, a+0, 0xf1000000);	/*  video base  */
+	store_32bit_word(cpu, a+4, 0);		/*  display code (?)  */
+	store_32bit_word(cpu, a+8, 1024);	/*  bytes per pixel row  */
+	store_32bit_word(cpu, a+12, 1024);	/*  width  */
+	store_32bit_word(cpu, a+16, 768);	/*  height  */
+	store_32bit_word(cpu, a+20, 8);		/*  pixel depth  */
+	a += 24;
+	store_32bit_word(cpu, a+0, 127);	/*  gestalt number (TODO)  */
+	store_32bit_word(cpu, a+4, 0);		/*  device tree pointer (TODO)*/
+	store_32bit_word(cpu, a+8, 0);		/*  device tree length  */
+	store_32bit_word(cpu, a+12, b);	/*  last address of kernel data area  */
+
+	/*  r4 = "MOSX" (0x4D4F5358)  */
+	cpu->cd.ppc.gpr[4] = 0x4D4F5358;
+
+	/*
+	 *  r5 = OpenFirmware entry point.  NOTE: See
+	 *  cpu_ppc.c for the rest of this semi-ugly hack.
+	 */
+	dev_ram_init(machine, cpu->cd.ppc.of_emul_addr, 0x1000, DEV_RAM_RAM, 0x0, NULL);
+	store_32bit_word(cpu, cpu->cd.ppc.of_emul_addr, 0x44ee0002);
+	cpu->cd.ppc.gpr[5] = cpu->cd.ppc.of_emul_addr;
+
+#if 0
+	/*  r6 = args  */
+	cpu->cd.ppc.gpr[1] -= 516;
+	cpu->cd.ppc.gpr[6] = cpu->cd.ppc.gpr[1] + 4;
+	store_string(cpu, cpu->cd.ppc.gpr[6],
+	    machine->boot_string_argument);
+	/*  should be something like '/controller/disk/bsd'  */
+
+	/*  r7 = length? TODO  */
+	cpu->cd.ppc.gpr[7] = 5;
+#endif
+}
+
+
+MACHINE_DEFAULT_CPU(macppc)
+{
+	switch (machine->machine_subtype) {
+	case MACHINE_MACPPC_G3:
+		machine->cpu_name = strdup("PPC750");
+		break;
+	case MACHINE_MACPPC_G4:
+		machine->cpu_name = strdup("MPC7400");
+		break;
+	case MACHINE_MACPPC_G5:
+		machine->cpu_name = strdup("PPC970");
+		break;
+	}
+}
+
+
+MACHINE_DEFAULT_RAM(macppc)
+{
+	machine->physical_ram_in_mb = 64;
+}
+
+
+MACHINE_REGISTER(macppc)
+{
+	MR_DEFAULT(macppc, "Macintosh", MACHINE_MACPPC);
+
+	machine_entry_add_alias(me, "macppc");
+
+	machine_entry_add_subtype(me, "MacPPC G3", MACHINE_MACPPC_G3,
+	    "g3", NULL);
+
+	machine_entry_add_subtype(me, "MacPPC G4", MACHINE_MACPPC_G4,
+	    "g4", NULL);
+
+	machine_entry_add_subtype(me, "MacPPC G5", MACHINE_MACPPC_G5,
+	    "g5", NULL);
+
+	me->set_default_ram = machine_default_ram_macppc;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_macppc.cc gxemul-0.7.0+dfsg/src/machines/machine_macppc.cc
--- gxemul-0.6.2/src/machines/machine_macppc.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_macppc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,203 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Generic PowerPC-based Macintosh machines
- *
- *  See also:
- *
- *	NetBSD/macppc (http://www.netbsd.org/ports/macppc/)
- *	OpenBSD/macppc (http://www.openbsd.org/macppc.html)
- *
- *  Currently, these are skeletons for generic PowerMac G3, G4, and G5 systems.
- *  They do not model real PowerMacs, but should be enough to begin
- *  experimenting with running NetBSD/macppc and OpenBSD/macppc.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "of.h"
-
-
-MACHINE_SETUP(macppc)
-{
-	char tmpstr[300];
-	struct pci_data *pci_data;
-	struct vfb_data *fb;
-	uint64_t b, a;
-	int i;
-
-	machine->machine_name = strdup("Macintosh (PPC)");
-	if (machine->emulated_hz == 0)
-		machine->emulated_hz = 40000000;
-
-	device_add(machine, "gc addr=0xf3000000");
-
-	pci_data = dev_uninorth_init(machine, machine->memory, 0xe2000000,
-	    64 /*  isa irq base */, 0 /*  pci irq: TODO */);
-
-	/*  bus_pci_add(
-	    machine, pci_data, machine->memory, 0, 12, 0, "dec21143");  */
-	bus_pci_add(machine, pci_data, machine->memory, 0, 15, 0, "gc_obio");
-
-	if (machine->x11_md.in_use)
-		bus_pci_add(machine, pci_data, machine->memory, 0, 16, 0,
-		    "ati_radeon_9200_2");
-
-	snprintf(tmpstr, sizeof(tmpstr), "z8530 addr=0xf3013000 irq="
-	    "%s.cpu[%i].gc.lo.23 addr_mult=0x10",
-	    machine->path, machine->bootstrap_cpu);
-	machine->main_console_handle = (size_t)device_add(machine, tmpstr);
-
-	fb = dev_fb_init(machine, machine->memory, 0xf1000000,
-	    VFB_GENERIC | VFB_REVERSE_START, 1024,768, 1024,768, 8, "ofb");
-
-	device_add(machine, "hammerhead addr=0xf2800000");
-
-	snprintf(tmpstr, sizeof(tmpstr), "adb addr=0xf3016000 irq="
-	    "%s.cpu[%i].gc.lo.1", machine->path, machine->bootstrap_cpu);
-	device_add(machine, tmpstr);
-
-	if (!machine->prom_emulation)
-		return;
-
-
-	b = 8 * 1048576; a = b - 0x800;
-
-	of_emul_init(machine, fb, 0xf1000000, 1024, 768);
-	of_emul_init_uninorth(machine);
-
-	if (machine->x11_md.in_use)
-		of_emul_init_adb(machine);
-	else
-		of_emul_init_zs(machine);
-
-	/*
-	 *  r3 = pointer to boot_args (for the Mach kernel).
-	 *  See http://darwinsource.opendarwin.org/10.3/
-	 *  BootX-59/bootx.tproj/include.subproj/boot_args.h
-	 *  for more info.
-	 */
-	cpu->cd.ppc.gpr[3] = a;
-	store_16bit_word(cpu, a + 0x0000, 1);	/*  revision  */
-	store_16bit_word(cpu, a + 0x0002, 2);	/*  version  */
-	store_buf(cpu, a + 0x0004, machine->boot_string_argument, 256);
-	/*  26 dram banks; "long base; long size"  */
-	store_32bit_word(cpu, a + 0x0104, 0);	/*  base  */
-	store_32bit_word(cpu, a + 0x0108, machine->physical_ram_in_mb
-	    * 256);		/*  size (in pages)  */
-	for (i=8; i<26*8; i+= 4)
-		store_32bit_word(cpu, a + 0x0104 + i, 0);
-	a += (0x104 + 26 * 8);
-	/*  Video info:  */
-	store_32bit_word(cpu, a+0, 0xf1000000);	/*  video base  */
-	store_32bit_word(cpu, a+4, 0);		/*  display code (?)  */
-	store_32bit_word(cpu, a+8, 1024);	/*  bytes per pixel row  */
-	store_32bit_word(cpu, a+12, 1024);	/*  width  */
-	store_32bit_word(cpu, a+16, 768);	/*  height  */
-	store_32bit_word(cpu, a+20, 8);		/*  pixel depth  */
-	a += 24;
-	store_32bit_word(cpu, a+0, 127);	/*  gestalt number (TODO)  */
-	store_32bit_word(cpu, a+4, 0);		/*  device tree pointer (TODO)*/
-	store_32bit_word(cpu, a+8, 0);		/*  device tree length  */
-	store_32bit_word(cpu, a+12, b);	/*  last address of kernel data area  */
-
-	/*  r4 = "MOSX" (0x4D4F5358)  */
-	cpu->cd.ppc.gpr[4] = 0x4D4F5358;
-
-	/*
-	 *  r5 = OpenFirmware entry point.  NOTE: See
-	 *  cpu_ppc.c for the rest of this semi-ugly hack.
-	 */
-	dev_ram_init(machine, cpu->cd.ppc.of_emul_addr,
-	    0x1000, DEV_RAM_RAM, 0x0);
-	store_32bit_word(cpu, cpu->cd.ppc.of_emul_addr,
-	    0x44ee0002);
-	cpu->cd.ppc.gpr[5] = cpu->cd.ppc.of_emul_addr;
-
-#if 0
-	/*  r6 = args  */
-	cpu->cd.ppc.gpr[1] -= 516;
-	cpu->cd.ppc.gpr[6] = cpu->cd.ppc.gpr[1] + 4;
-	store_string(cpu, cpu->cd.ppc.gpr[6],
-	    machine->boot_string_argument);
-	/*  should be something like '/controller/disk/bsd'  */
-
-	/*  r7 = length? TODO  */
-	cpu->cd.ppc.gpr[7] = 5;
-#endif
-}
-
-
-MACHINE_DEFAULT_CPU(macppc)
-{
-	switch (machine->machine_subtype) {
-	case MACHINE_MACPPC_G3:
-		machine->cpu_name = strdup("PPC750");
-		break;
-	case MACHINE_MACPPC_G4:
-		machine->cpu_name = strdup("MPC7400");
-		break;
-	case MACHINE_MACPPC_G5:
-		machine->cpu_name = strdup("PPC970");
-		break;
-	}
-}
-
-
-MACHINE_DEFAULT_RAM(macppc)
-{
-	machine->physical_ram_in_mb = 64;
-}
-
-
-MACHINE_REGISTER(macppc)
-{
-	MR_DEFAULT(macppc, "Macintosh", ARCH_PPC, MACHINE_MACPPC);
-
-	machine_entry_add_alias(me, "macppc");
-
-	machine_entry_add_subtype(me, "MacPPC G3", MACHINE_MACPPC_G3,
-	    "g3", NULL);
-
-	machine_entry_add_subtype(me, "MacPPC G4", MACHINE_MACPPC_G4,
-	    "g4", NULL);
-
-	machine_entry_add_subtype(me, "MacPPC G5", MACHINE_MACPPC_G5,
-	    "g5", NULL);
-
-	me->set_default_ram = machine_default_ram_macppc;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_mvme88k.c gxemul-0.7.0+dfsg/src/machines/machine_mvme88k.c
--- gxemul-0.6.2/src/machines/machine_mvme88k.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_mvme88k.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,217 @@
+/*
+ *  Copyright (C) 2007-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: MVME88K machines (MVME187)
+ *
+ *  This is for experiments with OpenBSD/mvme88k.
+ *
+ *  MVME187 according to http://mcg.motorola.com/us/products/docs/pdf/187igd.pdf
+ *  ("MVME187 RISC Single Board Computer Installation Guide"):
+ *
+ *	88100 MPU, two MC88200 or MC88204 CMMUs (one for data cache and
+ *		one for instruction cache).
+ *	82596CA LAN Ethernet
+ *	53C710 SCSI
+ *	CD2401 SCC SERIAL IO
+ *	PRINTER PORT
+ *	MK48T08 BBRAM & CLOCK
+ *	EPROM
+ *	VME bus
+ *
+ *  ... and more details from OpenBSD/mvme88k sources:
+ *
+ *	0xff800000 .. 0xffbfffff = BUG PROM
+ *	0xffe00000 .. 0xffe1ffff = BUG SRAM
+ *	0xfff00000               = PCCTWO
+ *	  0xfff40000             = VME bus
+ *	  0xfff43000             = MEMC040 (Memory controller)
+ *	  0xfff45000             = CD2401 SCC SERIAL IO (cl0)
+ *	  0xfff46000             = 82596 Ethernet (ie0)
+ *	  0xfff47000             = 53C710 SCSI (osiop0)
+ *	  0xfffc0000             = MK48T08 (nvram0)
+ *
+ *  Note: It may turn out to be easier to support Lance ethernet (via VME)
+ *  than to support the 82596 ethernet controller.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/mvme187.h"
+#include "thirdparty/mvme88k_vme.h"
+#include "thirdparty/mvme_pcctworeg.h"
+
+
+MACHINE_SETUP(mvme88k)
+{
+	char tmpstr[300];
+
+	switch (machine->machine_subtype) {
+
+	case MACHINE_MVME88K_187:
+		machine->machine_name = strdup("MVME187");
+
+		/*  The mvme187 device contains 187-specific stuff, such
+		    as motherboard registers, and the memory controller:  */
+		device_add(machine, "mvme187");
+
+		/*  PCC2 bus at 0xfff00000:  */
+		snprintf(tmpstr, sizeof(tmpstr), "pcc2 addr=0x%x", PCC2_BASE);
+		device_add(machine, tmpstr);
+
+		/*  VME2 bus at 0xfff40000:  */
+		snprintf(tmpstr, sizeof(tmpstr), "vme addr=0x%x", VME2_BASE);
+		device_add(machine, tmpstr);
+
+		/*  Cirrus Logic serial console at 0xfff45000:  */
+		snprintf(tmpstr, sizeof(tmpstr), "clmpcc irq=%s.cpu[%i].pcc2 "
+		    "addr=0x%08x name2=cl0", machine->path,
+		    machine->bootstrap_cpu, 0xfff45000);
+		machine->main_console_handle =
+		    (size_t) device_add(machine, tmpstr);
+
+		/*  ie0 ethernet: TODO  */
+		device_add(machine, "unreadable addr=0xfff46000 len=0x1000");
+
+		/*  53C710 SCSI at 0xfff47000:  */
+		snprintf(tmpstr, sizeof(tmpstr), "osiop irq=%s.cpu[%i].pcc2.%i "
+		    "addr=0x%08x", machine->path,
+		    machine->bootstrap_cpu, PCC2V_SCSI, 0xfff47000);
+		device_add(machine, tmpstr);
+
+		/*  MK48T08 clock/nvram at 0xfffc0000:  */
+		snprintf(tmpstr, sizeof(tmpstr),
+		    "mk48txx addr=0x%x", 0xfffc0000);
+		device_add(machine, tmpstr);
+
+		/*  VMES (?): TODO  */
+		device_add(machine, "unreadable addr=0xff780000 len=0x80000");
+
+		/*  VME devices: TODO  */
+		device_add(machine, "unreadable addr=0xffff0000 len=0x10000");
+
+		break;
+
+	case MACHINE_MVME88K_188:
+		machine->machine_name = strdup("MVME188");
+		/*  TODO  */
+		break;
+
+	case MACHINE_MVME88K_197:
+		machine->machine_name = strdup("MVME197");
+		/*  TODO  */
+		break;
+
+	default:fatal("Unimplemented MVME88K machine subtype %i\n",
+		    machine->machine_subtype);
+		exit(1);
+	}
+
+	if (!machine->prom_emulation)
+		return;
+
+
+	mvmeprom_init(machine);
+
+	/*
+	 *  Boot loader args, according to OpenBSD/mvme88k's locore.S:
+	 *
+	 *  r2 = boot flags
+	 *  r3 = boot controller physical address
+	 *  r4 = esym
+	 *  r5 = start of miniroot
+	 *  r6 = end of miniroot
+	 *  r7 = ((Clun << 8) | Dlun): encoded bootdev
+	 *  r8 = board type (0x187, 0x188, 0x197)
+	 */
+
+	/*  Some address beyond the loaded kernel:  */
+	cpu->cd.m88k.r[4] = 6 * 1048576;
+
+	switch (machine->machine_subtype) {
+	case MACHINE_MVME88K_187:  cpu->cd.m88k.r[8] = 0x187; break;
+	case MACHINE_MVME88K_188:  cpu->cd.m88k.r[8] = 0x188; break;
+	case MACHINE_MVME88K_197:  cpu->cd.m88k.r[8] = 0x197; break;
+	}
+
+	/*  TODO: r3 and r7 must be set correctly to let
+	    OpenBSD/mvme88k detect correct boot device.  */
+}
+
+
+MACHINE_DEFAULT_CPU(mvme88k)
+{
+	switch (machine->machine_subtype) {
+
+	case MACHINE_MVME88K_187:
+	case MACHINE_MVME88K_188:
+		machine->cpu_name = strdup("88100");
+		break;
+
+	case MACHINE_MVME88K_197:
+		machine->cpu_name = strdup("88110");
+		break;
+
+	default:fatal("Unimplemented MVME88K machine subtype %i\n",
+		    machine->machine_subtype);
+		exit(1);
+	}
+}
+
+
+MACHINE_DEFAULT_RAM(mvme88k)
+{
+	machine->physical_ram_in_mb = 64;
+}
+
+
+MACHINE_REGISTER(mvme88k)
+{
+	MR_DEFAULT(mvme88k, "MVME88K", MACHINE_MVME88K);
+
+	machine_entry_add_alias(me, "mvme88k");
+
+	machine_entry_add_subtype(me, "MVME187", MACHINE_MVME88K_187,
+	    "mvme187", NULL);
+
+	machine_entry_add_subtype(me, "MVME188", MACHINE_MVME88K_188,
+	    "mvme188", NULL);
+
+	machine_entry_add_subtype(me, "MVME197", MACHINE_MVME88K_197,
+	    "mvme197", NULL);
+
+	me->set_default_ram = machine_default_ram_mvme88k;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_mvme88k.cc gxemul-0.7.0+dfsg/src/machines/machine_mvme88k.cc
--- gxemul-0.6.2/src/machines/machine_mvme88k.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_mvme88k.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,217 +0,0 @@
-/*
- *  Copyright (C) 2007-2014  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: MVME88K machines (MVME187)
- *
- *  This is for experiments with OpenBSD/mvme88k.
- *
- *  MVME187 according to http://mcg.motorola.com/us/products/docs/pdf/187igd.pdf
- *  ("MVME187 RISC Single Board Computer Installation Guide"):
- *
- *	88100 MPU, two MC88200 or MC88204 CMMUs (one for data cache and
- *		one for instruction cache).
- *	82596CA LAN Ethernet
- *	53C710 SCSI
- *	CD2401 SCC SERIAL IO
- *	PRINTER PORT
- *	MK48T08 BBRAM & CLOCK
- *	EPROM
- *	VME bus
- *
- *  ... and more details from OpenBSD/mvme88k sources:
- *
- *	0xff800000 .. 0xffbfffff = BUG PROM
- *	0xffe00000 .. 0xffe1ffff = BUG SRAM
- *	0xfff00000               = PCCTWO
- *	  0xfff40000             = VME bus
- *	  0xfff43000             = MEMC040 (Memory controller)
- *	  0xfff45000             = CD2401 SCC SERIAL IO (cl0)
- *	  0xfff46000             = 82596 Ethernet (ie0)
- *	  0xfff47000             = 53C710 SCSI (osiop0)
- *	  0xfffc0000             = MK48T08 (nvram0)
- *
- *  Note: It may turn out to be easier to support Lance ethernet (via VME)
- *  than to support the 82596 ethernet controller.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/mvme187.h"
-#include "thirdparty/mvme88k_vme.h"
-#include "thirdparty/mvme_pcctworeg.h"
-
-
-MACHINE_SETUP(mvme88k)
-{
-	char tmpstr[300];
-
-	switch (machine->machine_subtype) {
-
-	case MACHINE_MVME88K_187:
-		machine->machine_name = strdup("MVME187");
-
-		/*  The mvme187 device contains 187-specific stuff, such
-		    as motherboard registers, and the memory controller:  */
-		device_add(machine, "mvme187");
-
-		/*  PCC2 bus at 0xfff00000:  */
-		snprintf(tmpstr, sizeof(tmpstr), "pcc2 addr=0x%x", PCC2_BASE);
-		device_add(machine, tmpstr);
-
-		/*  VME2 bus at 0xfff40000:  */
-		snprintf(tmpstr, sizeof(tmpstr), "vme addr=0x%x", VME2_BASE);
-		device_add(machine, tmpstr);
-
-		/*  Cirrus Logic serial console at 0xfff45000:  */
-		snprintf(tmpstr, sizeof(tmpstr), "clmpcc irq=%s.cpu[%i].pcc2 "
-		    "addr=0x%08x name2=cl0", machine->path,
-		    machine->bootstrap_cpu, 0xfff45000);
-		machine->main_console_handle =
-		    (size_t) device_add(machine, tmpstr);
-
-		/*  ie0 ethernet: TODO  */
-		device_add(machine, "unreadable addr=0xfff46000 len=0x1000");
-
-		/*  53C710 SCSI at 0xfff47000:  */
-		snprintf(tmpstr, sizeof(tmpstr), "osiop irq=%s.cpu[%i].pcc2.%i "
-		    "addr=0x%08x", machine->path,
-		    machine->bootstrap_cpu, PCC2V_SCSI, 0xfff47000);
-		device_add(machine, tmpstr);
-
-		/*  MK48T08 clock/nvram at 0xfffc0000:  */
-		snprintf(tmpstr, sizeof(tmpstr),
-		    "mk48txx addr=0x%x", 0xfffc0000);
-		device_add(machine, tmpstr);
-
-		/*  VMES (?): TODO  */
-		device_add(machine, "unreadable addr=0xff780000 len=0x80000");
-
-		/*  VME devices: TODO  */
-		device_add(machine, "unreadable addr=0xffff0000 len=0x10000");
-
-		break;
-
-	case MACHINE_MVME88K_188:
-		machine->machine_name = strdup("MVME188");
-		/*  TODO  */
-		break;
-
-	case MACHINE_MVME88K_197:
-		machine->machine_name = strdup("MVME197");
-		/*  TODO  */
-		break;
-
-	default:fatal("Unimplemented MVME88K machine subtype %i\n",
-		    machine->machine_subtype);
-		exit(1);
-	}
-
-	if (!machine->prom_emulation)
-		return;
-
-
-	mvmeprom_init(machine);
-
-	/*
-	 *  Boot loader args, according to OpenBSD/mvme88k's locore.S:
-	 *
-	 *  r2 = boot flags
-	 *  r3 = boot controller physical address
-	 *  r4 = esym
-	 *  r5 = start of miniroot
-	 *  r6 = end of miniroot
-	 *  r7 = ((Clun << 8) | Dlun): encoded bootdev
-	 *  r8 = board type (0x187, 0x188, 0x197)
-	 */
-
-	/*  Some address beyond the loaded kernel:  */
-	cpu->cd.m88k.r[4] = 6 * 1048576;
-
-	switch (machine->machine_subtype) {
-	case MACHINE_MVME88K_187:  cpu->cd.m88k.r[8] = 0x187; break;
-	case MACHINE_MVME88K_188:  cpu->cd.m88k.r[8] = 0x188; break;
-	case MACHINE_MVME88K_197:  cpu->cd.m88k.r[8] = 0x197; break;
-	}
-
-	/*  TODO: r3 and r7 must be set correctly to let
-	    OpenBSD/mvme88k detect correct boot device.  */
-}
-
-
-MACHINE_DEFAULT_CPU(mvme88k)
-{
-	switch (machine->machine_subtype) {
-
-	case MACHINE_MVME88K_187:
-	case MACHINE_MVME88K_188:
-		machine->cpu_name = strdup("88100");
-		break;
-
-	case MACHINE_MVME88K_197:
-		machine->cpu_name = strdup("88110");
-		break;
-
-	default:fatal("Unimplemented MVME88K machine subtype %i\n",
-		    machine->machine_subtype);
-		exit(1);
-	}
-}
-
-
-MACHINE_DEFAULT_RAM(mvme88k)
-{
-	machine->physical_ram_in_mb = 64;
-}
-
-
-MACHINE_REGISTER(mvme88k)
-{
-	MR_DEFAULT(mvme88k, "MVME88K", ARCH_M88K, MACHINE_MVME88K);
-
-	machine_entry_add_alias(me, "mvme88k");
-
-	machine_entry_add_subtype(me, "MVME187", MACHINE_MVME88K_187,
-	    "mvme187old", NULL);
-
-	machine_entry_add_subtype(me, "MVME188", MACHINE_MVME88K_188,
-	    "mvme188", NULL);
-
-	machine_entry_add_subtype(me, "MVME197", MACHINE_MVME88K_197,
-	    "mvme197", NULL);
-
-	me->set_default_ram = machine_default_ram_mvme88k;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_mvmeppc.c gxemul-0.7.0+dfsg/src/machines/machine_mvmeppc.c
--- gxemul-0.6.2/src/machines/machine_mvmeppc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_mvmeppc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,208 @@
+/*
+ *  Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: MVMEPPC machines
+ *
+ *  This is for experiments with NetBSD/mvmeppc.
+ *  (ftp://ftp.netbsd.org/pub/NetBSD/arch/mvmeppc/snapshot/20020302/README)
+ *
+ *  Note:  MVME machines that really adhere to the PReP standard should be
+ *         in machine_prep.c instead.
+ *
+ *
+ *  TODO: This is mostly bogus.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_isa.h"
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+MACHINE_SETUP(mvmeppc)
+{
+	char tmpstr[300], tmpstr2[300];;
+	struct pci_data *pci_data = NULL;
+
+	switch (machine->machine_subtype) {
+
+	case MACHINE_MVMEPPC_1600:
+		machine->machine_name = strdup("MVME1600");
+
+		snprintf(tmpstr, sizeof(tmpstr), "eagle irq=%s.cpu[%i]",
+		    machine->path, machine->bootstrap_cpu);
+		device_add(machine, tmpstr);
+
+		bus_pci_add(machine, pci_data, machine->memory,
+		    0, 14, 0, "dec21143");
+
+		device_add(machine, "nvram addr=0x80000074 name2=mvme1600");
+
+		/*
+		 *  "DRAM size register": TODO: turn this into a device?
+		 *  See the definition of p160x_dram_size in NetBSD's
+		 *  .../arch/mvmeppc/platform_160x.c for details.
+		 *
+		 *  0x11 = two banks of 32 MB each.
+		 */
+		dev_ram_init(machine, 0x80000804, 1, DEV_RAM_RAM, 0, NULL);
+		store_byte(cpu, 0x80000804, 0x11);
+
+		break;
+
+	case MACHINE_MVMEPPC_2100:
+		machine->machine_name = strdup("MVME2100");
+
+		/*  0xfe000000 isa bus space  */
+		/*  0xfec00000 pci indirect addr  */
+		/*  0xfee00000 pci indirect data  */
+
+		/*  TODO: irq  */
+		device_add(machine, "ns16550 irq=0 addr=0xffe10000");
+
+		break;
+
+	case MACHINE_MVMEPPC_5500:
+		/*  Could possibly be used for RTEMS experiments some day.  */
+		machine->machine_name = strdup("MVME5500");
+
+		/*  GT64260 interrupt and PCI controller:  */
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i]",
+		    machine->path, machine->bootstrap_cpu);
+		snprintf(tmpstr2, sizeof(tmpstr2), "%s.cpu[%i]",
+		    machine->path, machine->bootstrap_cpu);
+		pci_data = dev_gt_init(machine, machine->memory,
+		    0xf1000000,
+		    tmpstr,		// timer irq path: TODO
+		    tmpstr2,		// ISA irq path: TODO
+		    260);
+
+		/*  TODO: irq  */
+		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i] addr=0xf1120000",
+		    machine->path, machine->bootstrap_cpu);
+		device_add(machine, tmpstr);
+
+		break;
+
+	default:fatal("Unimplemented MVMEPPC machine subtype %i\n",
+		    machine->machine_subtype);
+		exit(1);
+	}
+
+	if (!machine->prom_emulation)
+		return;
+
+	/*  r3 = start of kernel, r4 = end of kernel (for NetBSD/mvmeppc)  */
+	cpu->cd.ppc.gpr[3] = 0;
+	cpu->cd.ppc.gpr[4] = 1048576 * 10;
+	cpu->cd.ppc.gpr[5] = machine->physical_ram_in_mb * 1048576-0x100;
+	store_string(cpu, cpu->cd.ppc.gpr[5]+ 44, "PC16550");
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[5]+ 68, 9600);
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[5]+ 72, 0);
+
+	store_16bit_word(cpu, cpu->cd.ppc.gpr[5]+ 76, 0x1600);
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[5]+ 80,
+	    machine->physical_ram_in_mb * 1048576);
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[5]+ 84, 33 * 1000000);
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[5]+ 88, 33 * 1000000);
+#if 0
+0         u_int32_t       bi_boothowto;
+4         u_int32_t       bi_bootaddr;
+8         u_int16_t       bi_bootclun;
+10        u_int16_t       bi_bootdlun;
+12        char            bi_bootline[BOOTLINE_LEN];  (32)
+44        char            bi_consoledev[CONSOLEDEV_LEN]; (16)
+60        u_int32_t       bi_consoleaddr;
+64        u_int32_t       bi_consolechan;
+68        u_int32_t       bi_consolespeed;
+72        u_int32_t       bi_consolecflag;
+76        u_int16_t       bi_modelnumber;
+80        u_int32_t       bi_memsize;
+84        u_int32_t       bi_mpuspeed;
+88        u_int32_t       bi_busspeed;
+92        u_int32_t       bi_clocktps;
+#endif
+}
+
+
+MACHINE_DEFAULT_CPU(mvmeppc)
+{
+	switch (machine->machine_subtype) {
+
+	case MACHINE_MVMEPPC_1600:
+		/*  Suitable for NetBSD/mvmeppc:  */
+		machine->cpu_name = strdup("PPC603e");
+		break;
+
+	case MACHINE_MVMEPPC_2100:
+		machine->cpu_name = strdup("PPC603e");
+		break;
+
+	case MACHINE_MVMEPPC_5500:
+		machine->cpu_name = strdup("PPC750");
+		break;
+
+	default:fatal("Unimplemented MVMEPPC machine subtype %i\n",
+		    machine->machine_subtype);
+		exit(1);
+	}
+}
+
+
+MACHINE_DEFAULT_RAM(mvmeppc)
+{
+	machine->physical_ram_in_mb = 64;
+}
+
+
+MACHINE_REGISTER(mvmeppc)
+{
+	MR_DEFAULT(mvmeppc, "MVMEPPC", MACHINE_MVMEPPC);
+
+	machine_entry_add_alias(me, "mvmeppc");
+
+	machine_entry_add_subtype(me, "MVME1600", MACHINE_MVMEPPC_1600,
+	    "mvme1600", NULL);
+
+	machine_entry_add_subtype(me, "MVME2100", MACHINE_MVMEPPC_2100,
+	    "mvme2100", NULL);
+
+	machine_entry_add_subtype(me, "MVME5500", MACHINE_MVMEPPC_5500,
+	    "mvme5500", NULL);
+
+	me->set_default_ram = machine_default_ram_mvmeppc;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_mvmeppc.cc gxemul-0.7.0+dfsg/src/machines/machine_mvmeppc.cc
--- gxemul-0.6.2/src/machines/machine_mvmeppc.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_mvmeppc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,208 +0,0 @@
-/*
- *  Copyright (C) 2006-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: MVMEPPC machines
- *
- *  This is for experiments with NetBSD/mvmeppc.
- *  (ftp://ftp.netbsd.org/pub/NetBSD/arch/mvmeppc/snapshot/20020302/README)
- *
- *  Note:  MVME machines that really adhere to the PReP standard should be
- *         in machine_prep.c instead.
- *
- *
- *  TODO: This is mostly bogus.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_isa.h"
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-MACHINE_SETUP(mvmeppc)
-{
-	char tmpstr[300], tmpstr2[300];;
-	struct pci_data *pci_data = NULL;
-
-	switch (machine->machine_subtype) {
-
-	case MACHINE_MVMEPPC_1600:
-		machine->machine_name = strdup("MVME1600");
-
-		snprintf(tmpstr, sizeof(tmpstr), "eagle irq=%s.cpu[%i]",
-		    machine->path, machine->bootstrap_cpu);
-		device_add(machine, tmpstr);
-
-		bus_pci_add(machine, pci_data, machine->memory,
-		    0, 14, 0, "dec21143");
-
-		device_add(machine, "nvram addr=0x80000074 name2=mvme1600");
-
-		/*
-		 *  "DRAM size register": TODO: turn this into a device?
-		 *  See the definition of p160x_dram_size in NetBSD's
-		 *  .../arch/mvmeppc/platform_160x.c for details.
-		 *
-		 *  0x11 = two banks of 32 MB each.
-		 */
-		dev_ram_init(machine, 0x80000804, 1, DEV_RAM_RAM, 0);
-		store_byte(cpu, 0x80000804, 0x11);
-
-		break;
-
-	case MACHINE_MVMEPPC_2100:
-		machine->machine_name = strdup("MVME2100");
-
-		/*  0xfe000000 isa bus space  */
-		/*  0xfec00000 pci indirect addr  */
-		/*  0xfee00000 pci indirect data  */
-
-		/*  TODO: irq  */
-		device_add(machine, "ns16550 irq=0 addr=0xffe10000");
-
-		break;
-
-	case MACHINE_MVMEPPC_5500:
-		/*  Could possibly be used for RTEMS experiments some day.  */
-		machine->machine_name = strdup("MVME5500");
-
-		/*  GT64260 interrupt and PCI controller:  */
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i]",
-		    machine->path, machine->bootstrap_cpu);
-		snprintf(tmpstr2, sizeof(tmpstr2), "%s.cpu[%i]",
-		    machine->path, machine->bootstrap_cpu);
-		pci_data = dev_gt_init(machine, machine->memory,
-		    0xf1000000,
-		    tmpstr,		// timer irq path: TODO
-		    tmpstr2,		// ISA irq path: TODO
-		    260);
-
-		/*  TODO: irq  */
-		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i] addr=0xf1120000",
-		    machine->path, machine->bootstrap_cpu);
-		device_add(machine, tmpstr);
-
-		break;
-
-	default:fatal("Unimplemented MVMEPPC machine subtype %i\n",
-		    machine->machine_subtype);
-		exit(1);
-	}
-
-	if (!machine->prom_emulation)
-		return;
-
-	/*  r3 = start of kernel, r4 = end of kernel (for NetBSD/mvmeppc)  */
-	cpu->cd.ppc.gpr[3] = 0;
-	cpu->cd.ppc.gpr[4] = 1048576 * 10;
-	cpu->cd.ppc.gpr[5] = machine->physical_ram_in_mb * 1048576-0x100;
-	store_string(cpu, cpu->cd.ppc.gpr[5]+ 44, "PC16550");
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[5]+ 68, 9600);
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[5]+ 72, 0);
-
-	store_16bit_word(cpu, cpu->cd.ppc.gpr[5]+ 76, 0x1600);
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[5]+ 80,
-	    machine->physical_ram_in_mb * 1048576);
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[5]+ 84, 33 * 1000000);
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[5]+ 88, 33 * 1000000);
-#if 0
-0         u_int32_t       bi_boothowto;
-4         u_int32_t       bi_bootaddr;
-8         u_int16_t       bi_bootclun;
-10        u_int16_t       bi_bootdlun;
-12        char            bi_bootline[BOOTLINE_LEN];  (32)
-44        char            bi_consoledev[CONSOLEDEV_LEN]; (16)
-60        u_int32_t       bi_consoleaddr;
-64        u_int32_t       bi_consolechan;
-68        u_int32_t       bi_consolespeed;
-72        u_int32_t       bi_consolecflag;
-76        u_int16_t       bi_modelnumber;
-80        u_int32_t       bi_memsize;
-84        u_int32_t       bi_mpuspeed;
-88        u_int32_t       bi_busspeed;
-92        u_int32_t       bi_clocktps;
-#endif
-}
-
-
-MACHINE_DEFAULT_CPU(mvmeppc)
-{
-	switch (machine->machine_subtype) {
-
-	case MACHINE_MVMEPPC_1600:
-		/*  Suitable for NetBSD/mvmeppc:  */
-		machine->cpu_name = strdup("PPC603e");
-		break;
-
-	case MACHINE_MVMEPPC_2100:
-		machine->cpu_name = strdup("PPC603e");
-		break;
-
-	case MACHINE_MVMEPPC_5500:
-		machine->cpu_name = strdup("PPC750");
-		break;
-
-	default:fatal("Unimplemented MVMEPPC machine subtype %i\n",
-		    machine->machine_subtype);
-		exit(1);
-	}
-}
-
-
-MACHINE_DEFAULT_RAM(mvmeppc)
-{
-	machine->physical_ram_in_mb = 64;
-}
-
-
-MACHINE_REGISTER(mvmeppc)
-{
-	MR_DEFAULT(mvmeppc, "MVMEPPC", ARCH_PPC, MACHINE_MVMEPPC);
-
-	machine_entry_add_alias(me, "mvmeppc");
-
-	machine_entry_add_subtype(me, "MVME1600", MACHINE_MVMEPPC_1600,
-	    "mvme1600", NULL);
-
-	machine_entry_add_subtype(me, "MVME2100", MACHINE_MVMEPPC_2100,
-	    "mvme2100", NULL);
-
-	machine_entry_add_subtype(me, "MVME5500", MACHINE_MVMEPPC_5500,
-	    "mvme5500", NULL);
-
-	me->set_default_ram = machine_default_ram_mvmeppc;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_netwinder.c gxemul-0.7.0+dfsg/src/machines/machine_netwinder.c
--- gxemul-0.6.2/src/machines/machine_netwinder.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_netwinder.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: NetWinder
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+MACHINE_SETUP(netwinder)
+{
+	char tmpstr[300];
+	struct pci_data *pci_bus;
+
+	machine->machine_name = strdup("NetWinder");
+
+	if (machine->physical_ram_in_mb > 256)
+		fprintf(stderr, "WARNING! Real NetWinders cannot"
+		    " have more than 256 MB RAM. Continuing anyway.\n");
+
+	/*  CPU at 63.75 MHz, according to NetBSD's netwinder_machdep.c.  */
+	machine->emulated_hz = 63750000;
+
+	snprintf(tmpstr, sizeof(tmpstr), "footbridge irq=%s.cpu[%i].irq"
+	    " addr=0x42000000", machine->path, machine->bootstrap_cpu);
+	pci_bus = (struct pci_data *) device_add(machine, tmpstr);
+
+	if (machine->x11_md.in_use) {
+		bus_pci_add(machine, pci_bus, machine->memory,
+		    0xc0, 8, 0, "igsfb");
+	}
+
+	if (!machine->prom_emulation)
+		return;
+
+	arm_setup_initial_translation_table(cpu, 0x4000);
+}
+
+
+MACHINE_DEFAULT_CPU(netwinder)
+{
+	machine->cpu_name = strdup("SA110");
+}
+
+
+MACHINE_DEFAULT_RAM(netwinder)
+{
+	machine->physical_ram_in_mb = 16;
+}
+
+
+MACHINE_REGISTER(netwinder)
+{
+	MR_DEFAULT(netwinder, "NetWinder", MACHINE_NETWINDER);
+
+	machine_entry_add_alias(me, "netwinder");
+
+	me->set_default_ram = machine_default_ram_netwinder;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_netwinder.cc gxemul-0.7.0+dfsg/src/machines/machine_netwinder.cc
--- gxemul-0.6.2/src/machines/machine_netwinder.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_netwinder.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,94 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: NetWinder
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-MACHINE_SETUP(netwinder)
-{
-	char tmpstr[300];
-	struct pci_data *pci_bus;
-
-	machine->machine_name = strdup("NetWinder");
-
-	if (machine->physical_ram_in_mb > 256)
-		fprintf(stderr, "WARNING! Real NetWinders cannot"
-		    " have more than 256 MB RAM. Continuing anyway.\n");
-
-	/*  CPU at 63.75 MHz, according to NetBSD's netwinder_machdep.c.  */
-	machine->emulated_hz = 63750000;
-
-	snprintf(tmpstr, sizeof(tmpstr), "footbridge irq=%s.cpu[%i].irq"
-	    " addr=0x42000000", machine->path, machine->bootstrap_cpu);
-	pci_bus = (struct pci_data *) device_add(machine, tmpstr);
-
-	if (machine->x11_md.in_use) {
-		bus_pci_add(machine, pci_bus, machine->memory,
-		    0xc0, 8, 0, "igsfb");
-	}
-
-	if (!machine->prom_emulation)
-		return;
-
-	arm_setup_initial_translation_table(cpu, 0x4000);
-}
-
-
-MACHINE_DEFAULT_CPU(netwinder)
-{
-	machine->cpu_name = strdup("SA110");
-}
-
-
-MACHINE_DEFAULT_RAM(netwinder)
-{
-	machine->physical_ram_in_mb = 16;
-}
-
-
-MACHINE_REGISTER(netwinder)
-{
-	MR_DEFAULT(netwinder, "NetWinder", ARCH_ARM, MACHINE_NETWINDER);
-
-	machine_entry_add_alias(me, "netwinder");
-
-	me->set_default_ram = machine_default_ram_netwinder;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_playstation2.c gxemul-0.7.0+dfsg/src/machines/machine_playstation2.c
--- gxemul-0.6.2/src/machines/machine_playstation2.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_playstation2.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,185 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Sony PlayStation 2
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#define PLAYSTATION2_BDA        0xffffffffa0001000ULL
+#define PLAYSTATION2_OPTARGS    0xffffffff81fff100ULL
+#define PLAYSTATION2_SIFBIOS    0xffffffffbfc10000ULL
+
+
+static int int_to_bcd(int i)
+{
+	return (i/10) * 16 + (i % 10);
+}
+
+
+MACHINE_SETUP(playstation2)
+{
+	char tmpstr[200];
+	int tmplen;
+	char *tmp;
+	time_t timet;
+	struct tm *tm_ptr;
+
+	machine->machine_name = strdup("Playstation 2");
+	cpu->byte_order = EMUL_LITTLE_ENDIAN;
+
+	if (machine->physical_ram_in_mb != 32)
+		fprintf(stderr, "WARNING! Playstation 2 machines are supposed "
+		    "to have exactly 32 MB RAM. Continuing anyway.\n");
+	if (!machine->x11_md.in_use)
+		fprintf(stderr, "WARNING! Playstation 2 without -X is pretty "
+		    "meaningless. Continuing anyway.\n");
+
+	/*
+	 *  According to NetBSD:
+	 *
+	 *	Hardware irq 0 is timer/interrupt controller
+	 *	Hardware irq 1 is dma controller
+	 *
+	 *  Some things are not yet emulated (at all), and hence are detected
+	 *  incorrectly:
+	 *
+	 *	sbus0 at mainbus0: controller type 2
+	 *	ohci0 at sbus0		(at 0x1f801600, according to linux)
+	 *	ohci0: OHCI version 1.0
+	 */
+
+	device_add(machine, "ps2 addr=0x10000000");
+	device_add(machine, "ps2_gs addr=0x12000000");
+	device_add(machine, "ps2_ether addr=0x14001000");
+
+	/*  TODO: how much?  */
+	dev_ram_init(machine, 0x1c000000, 4 * 1048576, DEV_RAM_RAM, 0, NULL);
+
+	/*  OHCI at SBUS irq 1:  */
+	snprintf(tmpstr, sizeof(tmpstr), "ohci addr=0x1f801600 irq="
+	    "%s.cpu[%i].ps2_sbus.1", machine->path, machine->bootstrap_cpu);
+	device_add(machine, tmpstr);
+
+	/*  Set the Harddisk controller present flag, if either
+	    disk 0 or 1 is present:  */
+	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
+	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
+		if (machine->prom_emulation)
+			store_32bit_word(cpu, 0xa0000000 + machine->
+			    physical_ram_in_mb*1048576 - 0x1000 + 0x0, 0x100);
+		device_add(machine, "ps2_spd addr=0x14000000");
+	}
+
+	if (!machine->prom_emulation)
+		return;
+
+
+	tmplen = 1000;
+	CHECK_ALLOCATION(tmp = (char *) malloc(tmplen));
+
+	add_symbol_name(&machine->symbol_context,
+	    PLAYSTATION2_SIFBIOS, 0x10000, "[SIFBIOS entry]", 0, 0);
+	store_32bit_word(cpu, PLAYSTATION2_BDA + 0,
+	    PLAYSTATION2_SIFBIOS);
+	store_buf(cpu, PLAYSTATION2_BDA + 4, "PS2b", 4);
+
+	/*  "Magic trap" instruction for software PROM emulation:  */
+	store_32bit_word(cpu, PLAYSTATION2_SIFBIOS, 0x00c0de0c);
+
+	store_32bit_word(cpu, 0xa0000000 + machine->physical_ram_in_mb
+	    * 1048576 - 0x1000 + 0x4, PLAYSTATION2_OPTARGS);
+
+	strlcpy(tmp, "root=/dev/hda1 crtmode=vesa0,60", tmplen);
+
+	if (machine->boot_string_argument[0])
+		snprintf(tmp+strlen(tmp), tmplen-strlen(tmp),
+		    " %s", machine->boot_string_argument);
+	tmp[tmplen-1] = '\0';
+
+	machine->bootstr = tmp;
+	store_string(cpu, PLAYSTATION2_OPTARGS, machine->bootstr);
+
+	/*  TODO:  netbsd's bootinfo.h, for symbolic names  */
+
+	/*  RTC data given by the BIOS:  */
+	timet = time(NULL) + 9*3600;	/*  PS2 uses Japanese time  */
+	tm_ptr = gmtime(&timet);
+	/*  TODO:  are these 0- or 1-based?  */
+	store_byte(cpu, 0xa0000000 + machine->physical_ram_in_mb
+	    * 1048576 - 0x1000 + 0x10 + 1, int_to_bcd(tm_ptr->tm_sec));
+	store_byte(cpu, 0xa0000000 + machine->physical_ram_in_mb
+	    * 1048576 - 0x1000 + 0x10 + 2, int_to_bcd(tm_ptr->tm_min));
+	store_byte(cpu, 0xa0000000 + machine->physical_ram_in_mb
+	    * 1048576 - 0x1000 + 0x10 + 3, int_to_bcd(tm_ptr->tm_hour));
+	store_byte(cpu, 0xa0000000 + machine->physical_ram_in_mb
+	    * 1048576 - 0x1000 + 0x10 + 5, int_to_bcd(tm_ptr->tm_mday));
+	store_byte(cpu, 0xa0000000 + machine->physical_ram_in_mb
+	    * 1048576 - 0x1000 + 0x10 + 6, int_to_bcd(tm_ptr->tm_mon+1));
+	store_byte(cpu, 0xa0000000 + machine->physical_ram_in_mb
+	    * 1048576 - 0x1000 + 0x10 + 7, int_to_bcd(tm_ptr->tm_year-100));
+
+	/*  "BOOTINFO_PCMCIA_TYPE" in NetBSD's bootinfo.h. This
+	    contains the sbus controller type.  */
+	store_32bit_word(cpu, 0xa0000000 + machine->physical_ram_in_mb
+	    * 1048576 - 0x1000 + 0x1c, 2);
+}
+
+
+MACHINE_DEFAULT_CPU(playstation2)
+{
+	machine->cpu_name = strdup("R5900");
+}
+
+
+MACHINE_DEFAULT_RAM(playstation2)
+{
+	machine->physical_ram_in_mb = 32;
+}
+
+
+MACHINE_REGISTER(playstation2)
+{
+	MR_DEFAULT(playstation2, "Playstation 2", MACHINE_PS2);
+
+	machine_entry_add_alias(me, "playstation2");
+	machine_entry_add_alias(me, "ps2");
+
+	me->set_default_ram = machine_default_ram_playstation2;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_playstation2.cc gxemul-0.7.0+dfsg/src/machines/machine_playstation2.cc
--- gxemul-0.6.2/src/machines/machine_playstation2.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_playstation2.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,185 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Sony PlayStation 2
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#define PLAYSTATION2_BDA        0xffffffffa0001000ULL
-#define PLAYSTATION2_OPTARGS    0xffffffff81fff100ULL
-#define PLAYSTATION2_SIFBIOS    0xffffffffbfc10000ULL
-
-
-static int int_to_bcd(int i)
-{
-	return (i/10) * 16 + (i % 10);
-}
-
-
-MACHINE_SETUP(playstation2)
-{
-	char tmpstr[200];
-	int tmplen;
-	char *tmp;
-	time_t timet;
-	struct tm *tm_ptr;
-
-	machine->machine_name = strdup("Playstation 2");
-	cpu->byte_order = EMUL_LITTLE_ENDIAN;
-
-	if (machine->physical_ram_in_mb != 32)
-		fprintf(stderr, "WARNING! Playstation 2 machines are supposed "
-		    "to have exactly 32 MB RAM. Continuing anyway.\n");
-	if (!machine->x11_md.in_use)
-		fprintf(stderr, "WARNING! Playstation 2 without -X is pretty "
-		    "meaningless. Continuing anyway.\n");
-
-	/*
-	 *  According to NetBSD:
-	 *
-	 *	Hardware irq 0 is timer/interrupt controller
-	 *	Hardware irq 1 is dma controller
-	 *
-	 *  Some things are not yet emulated (at all), and hence are detected
-	 *  incorrectly:
-	 *
-	 *	sbus0 at mainbus0: controller type 2
-	 *	ohci0 at sbus0		(at 0x1f801600, according to linux)
-	 *	ohci0: OHCI version 1.0
-	 */
-
-	device_add(machine, "ps2 addr=0x10000000");
-	device_add(machine, "ps2_gs addr=0x12000000");
-	device_add(machine, "ps2_ether addr=0x14001000");
-
-	/*  TODO: how much?  */
-	dev_ram_init(machine, 0x1c000000, 4 * 1048576, DEV_RAM_RAM, 0);
-
-	/*  OHCI at SBUS irq 1:  */
-	snprintf(tmpstr, sizeof(tmpstr), "ohci addr=0x1f801600 irq="
-	    "%s.cpu[%i].ps2_sbus.1", machine->path, machine->bootstrap_cpu);
-	device_add(machine, tmpstr);
-
-	/*  Set the Harddisk controller present flag, if either
-	    disk 0 or 1 is present:  */
-	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
-	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
-		if (machine->prom_emulation)
-			store_32bit_word(cpu, 0xa0000000 + machine->
-			    physical_ram_in_mb*1048576 - 0x1000 + 0x0, 0x100);
-		device_add(machine, "ps2_spd addr=0x14000000");
-	}
-
-	if (!machine->prom_emulation)
-		return;
-
-
-	tmplen = 1000;
-	CHECK_ALLOCATION(tmp = (char *) malloc(tmplen));
-
-	add_symbol_name(&machine->symbol_context,
-	    PLAYSTATION2_SIFBIOS, 0x10000, "[SIFBIOS entry]", 0, 0);
-	store_32bit_word(cpu, PLAYSTATION2_BDA + 0,
-	    PLAYSTATION2_SIFBIOS);
-	store_buf(cpu, PLAYSTATION2_BDA + 4, "PS2b", 4);
-
-	/*  "Magic trap" instruction for software PROM emulation:  */
-	store_32bit_word(cpu, PLAYSTATION2_SIFBIOS, 0x00c0de0c);
-
-	store_32bit_word(cpu, 0xa0000000 + machine->physical_ram_in_mb
-	    * 1048576 - 0x1000 + 0x4, PLAYSTATION2_OPTARGS);
-
-	strlcpy(tmp, "root=/dev/hda1 crtmode=vesa0,60", tmplen);
-
-	if (machine->boot_string_argument[0])
-		snprintf(tmp+strlen(tmp), tmplen-strlen(tmp),
-		    " %s", machine->boot_string_argument);
-	tmp[tmplen-1] = '\0';
-
-	machine->bootstr = tmp;
-	store_string(cpu, PLAYSTATION2_OPTARGS, machine->bootstr);
-
-	/*  TODO:  netbsd's bootinfo.h, for symbolic names  */
-
-	/*  RTC data given by the BIOS:  */
-	timet = time(NULL) + 9*3600;	/*  PS2 uses Japanese time  */
-	tm_ptr = gmtime(&timet);
-	/*  TODO:  are these 0- or 1-based?  */
-	store_byte(cpu, 0xa0000000 + machine->physical_ram_in_mb
-	    * 1048576 - 0x1000 + 0x10 + 1, int_to_bcd(tm_ptr->tm_sec));
-	store_byte(cpu, 0xa0000000 + machine->physical_ram_in_mb
-	    * 1048576 - 0x1000 + 0x10 + 2, int_to_bcd(tm_ptr->tm_min));
-	store_byte(cpu, 0xa0000000 + machine->physical_ram_in_mb
-	    * 1048576 - 0x1000 + 0x10 + 3, int_to_bcd(tm_ptr->tm_hour));
-	store_byte(cpu, 0xa0000000 + machine->physical_ram_in_mb
-	    * 1048576 - 0x1000 + 0x10 + 5, int_to_bcd(tm_ptr->tm_mday));
-	store_byte(cpu, 0xa0000000 + machine->physical_ram_in_mb
-	    * 1048576 - 0x1000 + 0x10 + 6, int_to_bcd(tm_ptr->tm_mon+1));
-	store_byte(cpu, 0xa0000000 + machine->physical_ram_in_mb
-	    * 1048576 - 0x1000 + 0x10 + 7, int_to_bcd(tm_ptr->tm_year-100));
-
-	/*  "BOOTINFO_PCMCIA_TYPE" in NetBSD's bootinfo.h. This
-	    contains the sbus controller type.  */
-	store_32bit_word(cpu, 0xa0000000 + machine->physical_ram_in_mb
-	    * 1048576 - 0x1000 + 0x1c, 2);
-}
-
-
-MACHINE_DEFAULT_CPU(playstation2)
-{
-	machine->cpu_name = strdup("R5900");
-}
-
-
-MACHINE_DEFAULT_RAM(playstation2)
-{
-	machine->physical_ram_in_mb = 32;
-}
-
-
-MACHINE_REGISTER(playstation2)
-{
-	MR_DEFAULT(playstation2, "Playstation 2", ARCH_MIPS, MACHINE_PS2);
-
-	machine_entry_add_alias(me, "playstation2");
-	machine_entry_add_alias(me, "ps2");
-
-	me->set_default_ram = machine_default_ram_playstation2;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_pmax.c gxemul-0.7.0+dfsg/src/machines/machine_pmax.c
--- gxemul-0.6.2/src/machines/machine_pmax.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_pmax.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1018 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Digital DECstation ("PMAX") machines
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "machine_pmax.h"
+#include "memory.h"
+#include "mips_cpu_types.h"
+#include "misc.h"
+
+#include "thirdparty/dec_prom.h"
+#include "thirdparty/dec_bootinfo.h"
+#include "thirdparty/dec_5100.h"
+#include "thirdparty/dec_kn01.h"
+#include "thirdparty/dec_kn02.h"  
+#include "thirdparty/dec_kn03.h"
+#include "thirdparty/dec_kmin.h"
+#include "thirdparty/dec_maxine.h"
+
+#define	BOOTARG_BUFLEN		2000
+
+
+MACHINE_SETUP(pmax)
+{
+	const char *framebuffer_console_name, *serial_console_name;
+	char bootpath[200];
+	char *init_bootpath;
+	int color_fb_flag, i;
+	int boot_scsi_boardnumber = 3, boot_net_boardnumber = 3;
+	const char *turbochannel_default_gfx_card = "PMAG-BA";
+		/*  PMAG-AA, -BA, -CA/DA/EA/FA, -JA, -RO, PMAGB-BA  */
+	struct xx {
+		struct btinfo_magic a;
+		struct btinfo_bootpath b;
+		struct btinfo_symtab c;
+	} xx;
+	char tmpstr[1000];
+	struct vfb_data *fb;
+	struct memory *mem = machine->memory;
+	uint64_t addr;
+
+	cpu->byte_order = EMUL_LITTLE_ENDIAN;
+
+	/*
+	 *  Add an R2020 or R3220 writeback memory thing:
+	 */
+	cpu->cd.mips.coproc[3] = mips_coproc_new(cpu, 3);
+
+	/*  There aren't really any good standard values...  */
+	framebuffer_console_name = "osconsole=0,3";
+	serial_console_name      = "osconsole=1";
+
+	switch (machine->machine_subtype) {
+
+	case MACHINE_DEC_PMAX_3100:		/*  type  1, KN01  */
+		/*  Supposed to have 12MHz or 16.67MHz R2000 CPU, R2010 FPC,
+		    R2020 Memory coprocessor  */
+		machine->machine_name = strdup("DEC PMAX 3100 (KN01)");
+
+		/*  12 MHz for 2100, 16.67 MHz for 3100  */
+		if (machine->emulated_hz == 0)
+			machine->emulated_hz = 16670000;
+
+		if (machine->physical_ram_in_mb > 24)
+			fprintf(stderr, "WARNING! Real DECstation 3100 machines"
+			    " cannot have more than 24MB RAM.\n");
+
+		if ((machine->physical_ram_in_mb % 4) != 0)
+			fprintf(stderr, "WARNING! Real DECstation 3100 machines"
+			    " have an integer multiple of 4 MBs of RAM.\n");
+
+		/*  1 for color, 0 for mono. TODO: command line option?  */
+		color_fb_flag = 1;
+
+		/*
+		 *  According to NetBSD/pmax:
+		 *
+		 *  pm0 at ibus0 addr 0xfc00000: 1024x864x1  (or x8 for color)
+		 *  dc0 at ibus0 addr 0x1c000000
+		 *  le0 at ibus0 addr 0x18000000: address 00:00:00:00:00:00
+		 *  sii0 at ibus0 addr 0x1a000000
+		 *  mcclock0 at ibus0 addr 0x1d000000: mc146818 or compatible
+		 *  0x1e000000 = system status and control register
+		 */
+		fb = dev_fb_init(machine, mem, KN01_PHYS_FBUF_START,
+		    color_fb_flag? VFB_DEC_VFB02 : VFB_DEC_VFB01,
+		    0,0,0,0,0, color_fb_flag? "VFB02":"VFB01");
+		dev_colorplanemask_init(mem, KN01_PHYS_COLMASK_START,
+		    &fb->color_plane_mask);
+		dev_vdac_init(mem, KN01_SYS_VDAC, fb->rgb_palette,
+		    color_fb_flag);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
+		    machine->path, machine->bootstrap_cpu, KN01_INT_LANCE);
+		dev_le_init(machine, mem, KN01_SYS_LANCE,
+		    KN01_SYS_LANCE_B_START, KN01_SYS_LANCE_B_END,
+		    tmpstr, 4*1048576);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
+		    machine->path, machine->bootstrap_cpu, KN01_INT_SII);
+		dev_sii_init(machine, mem, KN01_SYS_SII, KN01_SYS_SII_B_START,
+		    KN01_SYS_SII_B_END, tmpstr);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
+		    machine->path, machine->bootstrap_cpu, KN01_INT_DZ);
+		dev_dc7085_init(machine, mem, KN01_SYS_DZ, tmpstr,
+		    machine->x11_md.in_use);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
+		    machine->path, machine->bootstrap_cpu, KN01_INT_CLOCK);
+		dev_mc146818_init(machine, mem, KN01_SYS_CLOCK, tmpstr,
+		    MC146818_DEC, 1);
+
+		dev_kn01_init(mem, KN01_SYS_CSR, color_fb_flag);
+
+		framebuffer_console_name = "osconsole=0,3";	/*  fb,keyb  */
+		serial_console_name      = "osconsole=3";	/*  3  */
+		break;
+
+	case MACHINE_DEC_3MAX_5000:		/*  type  2, KN02  */
+		/*  Supposed to have 25MHz R3000 CPU, R3010 FPC,  */
+		/*  and a R3220 Memory coprocessor  */
+		machine->machine_name = strdup("DECstation 5000/200 (3MAX, KN02)");
+
+		if (machine->emulated_hz == 0)
+			machine->emulated_hz = 25000000;
+
+		if (machine->physical_ram_in_mb < 8)
+			fprintf(stderr, "WARNING! Real KN02 machines do not "
+			    "have less than 8MB RAM. Continuing anyway.\n");
+		if (machine->physical_ram_in_mb > 480)
+			fprintf(stderr, "WARNING! Real KN02 machines cannot "
+			    "have more than 480MB RAM. Continuing anyway.\n");
+
+		/*  An R3220 memory thingy:  */
+		cpu->cd.mips.coproc[3] = mips_coproc_new(cpu, 3);
+
+		/*
+		 *  According to NetBSD/pmax:
+		 *  asc0 at tc0 slot 5 offset 0x0
+		 *  le0 at tc0 slot 6 offset 0x0
+		 *  ibus0 at tc0 slot 7 offset 0x0
+		 *  dc0 at ibus0 addr 0x1fe00000
+		 *  mcclock0 at ibus0 addr 0x1fe80000: mc146818
+		 */
+
+		/*  KN02 mainbus (TurboChannel interrupt controller):  */
+		snprintf(tmpstr, sizeof(tmpstr), "kn02 addr=0x%x "
+		    "irq=%s.cpu[%i].2", (int) KN02_SYS_CSR,
+		    machine->path, machine->bootstrap_cpu);
+		device_add(machine, tmpstr);
+
+		/*
+		 *  TURBOchannel slots 0, 1, and 2 are free for option cards.
+		 *  Let's put in zero or more graphics boards:
+		 *
+		 *  TODO: It's also possible to have larger graphics cards that
+		 *  occupy several slots. How should this be solved nicely?
+		 */
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.kn02.%i",
+		    machine->path, machine->bootstrap_cpu, 0);
+		dev_turbochannel_init(machine, mem, 0,
+		    KN02_PHYS_TC_0_START, KN02_PHYS_TC_0_END,
+		    machine->n_gfx_cards >= 1?
+			turbochannel_default_gfx_card : "",
+		    tmpstr);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.kn02.%i",
+		    machine->path, machine->bootstrap_cpu, 1);
+		dev_turbochannel_init(machine, mem, 1,
+		    KN02_PHYS_TC_1_START, KN02_PHYS_TC_1_END,
+		    machine->n_gfx_cards >= 2?
+			turbochannel_default_gfx_card : "",
+		    tmpstr);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.kn02.%i",
+		    machine->path, machine->bootstrap_cpu, 2);
+		dev_turbochannel_init(machine, mem, 2,
+		    KN02_PHYS_TC_2_START, KN02_PHYS_TC_2_END,
+		    machine->n_gfx_cards >= 3?
+			turbochannel_default_gfx_card : "",
+		    tmpstr);
+
+		/*  TURBOchannel slots 3 and 4 are reserved.  */
+
+		/*  TURBOchannel slot 5 is PMAZ-AA ("asc" SCSI).  */
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.kn02.%i",
+		    machine->path, machine->bootstrap_cpu, 5);
+		dev_turbochannel_init(machine, mem, 5,
+		    KN02_PHYS_TC_5_START, KN02_PHYS_TC_5_END,
+		    "PMAZ-AA", tmpstr);
+
+		/*  TURBOchannel slot 6 is PMAD-AA ("le" ethernet).  */
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.kn02.%i",
+		    machine->path, machine->bootstrap_cpu, 6);
+		dev_turbochannel_init(machine, mem, 6,
+		    KN02_PHYS_TC_6_START, KN02_PHYS_TC_6_END,
+		    "PMAD-AA", tmpstr);
+
+		/*  TURBOchannel slot 7 is system stuff.  */
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.kn02.%i",
+		    machine->path, machine->bootstrap_cpu, 7);
+		machine->main_console_handle =
+		    dev_dc7085_init(machine, mem,
+		    KN02_SYS_DZ, tmpstr, machine->x11_md.in_use);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
+		    machine->path, machine->bootstrap_cpu, KN02_INT_CLOCK);
+		dev_mc146818_init(machine, mem,
+		    KN02_SYS_CLOCK, tmpstr, MC146818_DEC, 1);
+
+		framebuffer_console_name = "osconsole=0,7";
+								/*  fb,keyb  */
+		serial_console_name      = "osconsole=2";
+		boot_scsi_boardnumber = 5;
+		boot_net_boardnumber = 6;	/*  TODO: 3?  */
+		break;
+
+	case MACHINE_DEC_3MIN_5000:		/*  type 3, KN02BA  */
+		machine->machine_name = strdup("DECstation 5000/112, 125, or 145 (3MIN,"
+		    " KN02BA)");
+		if (machine->emulated_hz == 0)
+			machine->emulated_hz = 33000000;
+		if (machine->physical_ram_in_mb > 128)
+			fprintf(stderr, "WARNING! Real 3MIN machines cannot "
+			    "have more than 128MB RAM. Continuing anyway.\n");
+
+		/*  KN02BA "3min" TurboChannel interrupt controller:  */
+		snprintf(tmpstr, sizeof(tmpstr), "kn02ba irq=%s.cpu[%i].%i",
+		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC3);
+		device_add(machine, tmpstr);
+
+		/*
+		 *  tc0 at mainbus0: 12.5 MHz clock  (0x10000000,slotsize=64MB)
+		 *  tc slot 1:   0x14000000
+		 *  tc slot 2:   0x18000000
+		 *  ioasic0 at tc0 slot 3 offset 0x0	(0x1c000000) slot 0
+		 *  asic regs				(0x1c040000) slot 1
+		 *  station's ether address		(0x1c080000) slot 2
+		 *  le0 at ioasic0 offset 0xc0000: address 00:00:00:00:00:00
+		 *					(0x1c0c0000) slot 3
+		 *  scc0 at ioasic0 offset 0x100000	(0x1c100000) slot 4
+		 *  scc1 at ioasic0 offset 0x180000: console(0x1c180000) slot 6
+		 *  mcclock0 at ioasic0 offset 0x200000: mc146818 or
+		 *	compatible			(0x1c200000) slot 8
+		 *  asc0 at ioasic0 offset 0x300000: NCR53C94, 25MHz,
+		 *	SCSI ID 7			(0x1c300000) slot 12
+		 *  dma for asc0			(0x1c380000) slot 14
+		 */
+
+////fatal("TODO: kmin dev_le_init.\n");
+////abort();
+//		dev_le_init(machine, mem, 0x1c0c0000, 0, 0,
+//		    KMIN_INTR_LANCE + 8, 4 * 65536);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i.kn02ba.0x%x",
+		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC3, KMIN_INTR_SCC_0);
+		dev_scc_init(machine, mem, 0x1c100000, tmpstr,
+		    machine->x11_md.in_use, 0, 1);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i.kn02ba.0x%x",
+		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC3, KMIN_INTR_SCC_1);
+		dev_scc_init(machine, mem, 0x1c180000, tmpstr,
+		    machine->x11_md.in_use, 1, 1);
+
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i.kn02ba.0x%x",
+		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC3, KMIN_INTR_CLOCK);
+		dev_mc146818_init(machine, mem,
+		    KMIN_SYS_CLOCK, tmpstr, MC146818_DEC, 1);
+		    
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i.kn02ba.0x%x",
+		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC3, KMIN_INTR_SCSI);
+		dev_asc_init(machine, mem, 0x1c300000, tmpstr,
+		    NULL, DEV_ASC_DEC, NULL, NULL);
+
+		/*
+		 *  TURBOchannel slots 0, 1, and 2 are free for
+		 *  option cards.  These are by default filled with
+		 *  zero or more graphics boards.
+		 *
+		 *  TODO: irqs 
+		 */
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
+		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC0);
+		dev_turbochannel_init(machine, mem, 0,
+		    KMIN_PHYS_TC_0_START, KMIN_PHYS_TC_0_END,
+		    machine->n_gfx_cards >= 1?
+			turbochannel_default_gfx_card : "",
+		    tmpstr);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
+		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC1);
+		dev_turbochannel_init(machine, mem, 0,
+		    KMIN_PHYS_TC_1_START, KMIN_PHYS_TC_1_END,
+		    machine->n_gfx_cards >= 2?
+			turbochannel_default_gfx_card : "",
+		    tmpstr);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
+		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC2);
+		dev_turbochannel_init(machine, mem, 0,
+		    KMIN_PHYS_TC_2_START, KMIN_PHYS_TC_2_END,
+		    machine->n_gfx_cards >= 3?
+			turbochannel_default_gfx_card : "",
+		    tmpstr);
+
+		/*  (kmin shared irq numbers (IP) are offset by +8 in the
+		    emulator)  */
+		/*  kmin_csr = dev_kmin_init(cpu, mem, KMIN_REG_INTR);  */
+
+		framebuffer_console_name = "osconsole=0,3";	/* fb,keyb(?) */
+		serial_console_name      = "osconsole=3";	/* ? */
+		break;
+
+	case MACHINE_DEC_3MAXPLUS_5000:	/*  type 4, KN03  */
+		machine->machine_name = strdup("DECsystem 5900 or 5000 (3MAX+) (KN03)");
+
+		/*  5000/240 (KN03-GA, R3000): 40 MHz  */
+		/*  5000/260 (KN05-NB, R4000): 60 MHz  */
+		/*  TODO: are both these type 4?  */
+		if (machine->emulated_hz == 0)
+			machine->emulated_hz = 40000000;
+		if (machine->physical_ram_in_mb > 480)
+			fprintf(stderr, "WARNING! Real KN03 machines cannot "
+			    "have more than 480MB RAM. Continuing anyway.\n");
+
+		/*  KN03 interrupts:  */
+fatal("TODO: Legacy rewrite\n");
+abort();
+//		machine->md_interrupt = kn03_interrupt;
+
+		/*
+		 *  tc0 at mainbus0: 25 MHz clock (slot 0)	(0x1e000000)
+		 *  tc0 slot 1					(0x1e800000)
+		 *  tc0 slot 2					(0x1f000000)
+		 *  ioasic0 at tc0 slot 3 offset 0x0		(0x1f800000)
+		 *    something that has to do with interrupts? (?)(0x1f840000?)
+		 *  le0 at ioasic0 offset 0xc0000		(0x1f8c0000)
+		 *  scc0 at ioasic0 offset 0x100000		(0x1f900000)
+		 *  scc1 at ioasic0 offset 0x180000: console	(0x1f980000)
+		 *  mcclock0 at ioasic0 offset 0x200000: mc146818 or
+		 *	compatible				(0x1fa00000)
+		 *  asc0 at ioasic0 offset 0x300000: NCR53C94, 25MHz,
+		 *	SCSI ID 7				(0x1fb00000)
+		 */
+fatal("TODO: dec_ioasic legacy rewrite\n");
+abort();
+//		machine->md_int.dec_ioasic_data = dev_dec_ioasic_init(cpu,
+//		    mem, 0x1f800000, 0);
+
+fatal("TODO: kn03 dev_le_init rewrite\n");
+abort();
+//		dev_le_init(machine, mem, KN03_SYS_LANCE, 0, 0,
+//		    KN03_INTR_LANCE +8, 4 * 65536);
+
+fatal("TODO: dec_ioasic legacy rewrite\n");
+abort();
+//		machine->md_int.dec_ioasic_data->dma_func[3] =
+//		    dev_scc_dma_func;
+//		machine->md_int.dec_ioasic_data->dma_func_extra[2] =
+//		    dev_scc_init(machine, mem, KN03_SYS_SCC_0,
+//		    KN03_INTR_SCC_0 +8, machine->x11_md.in_use, 0, 1);
+//		machine->md_int.dec_ioasic_data->dma_func[2] =
+//		    dev_scc_dma_func;
+//		machine->md_int.dec_ioasic_data->dma_func_extra[3] =
+//		    dev_scc_init(machine, mem, KN03_SYS_SCC_1,
+//		    KN03_INTR_SCC_1 +8, machine->x11_md.in_use, 1, 1);
+
+fatal("TODO: mc146818 irq\n");
+abort();
+//		dev_mc146818_init(machine, mem, KN03_SYS_CLOCK, KN03_INT_RTC,
+//		    MC146818_DEC, 1);
+fatal("TODO: asc init rewrite\n");
+abort();
+//		dev_asc_init(machine, mem, KN03_SYS_SCSI,
+//		    KN03_INTR_SCSI +8, NULL, DEV_ASC_DEC, NULL, NULL);
+
+		/*
+		 *  TURBOchannel slots 0, 1, and 2 are free for
+		 *  option cards.  These are by default filled with
+		 *  zero or more graphics boards.
+		 *
+		 *  TODO: irqs 
+		 */
+fatal("TODO: turbochannel rewrite init\n");
+abort();
+#if 0
+		dev_turbochannel_init(machine, mem, 0,
+		    KN03_PHYS_TC_0_START, KN03_PHYS_TC_0_END,
+		    machine->n_gfx_cards >= 1?
+			turbochannel_default_gfx_card : "",
+		    KN03_INTR_TC_0 +8);
+
+		dev_turbochannel_init(machine, mem, 1,
+		    KN03_PHYS_TC_1_START, KN03_PHYS_TC_1_END,
+		    machine->n_gfx_cards >= 2?
+			turbochannel_default_gfx_card : "",
+		    KN03_INTR_TC_1 +8);
+
+		dev_turbochannel_init(machine, mem, 2,
+		    KN03_PHYS_TC_2_START, KN03_PHYS_TC_2_END,
+		    machine->n_gfx_cards >= 3?
+			turbochannel_default_gfx_card : "",
+		    KN03_INTR_TC_2 +8);
+#endif
+
+		/*  TODO: interrupts  */
+		/*  shared (turbochannel) interrupts are +8  */
+
+		framebuffer_console_name = "osconsole=0,3";	/* fb,keyb(?) */
+		serial_console_name      = "osconsole=3";	/* ? */
+		break;
+
+	case MACHINE_DEC_5800:		/*  type 5, KN5800  */
+		machine->machine_name = strdup("DECsystem 5800");
+
+		/*  TODO: this is incorrect, banks multiply by 8 etc  */
+		if (machine->physical_ram_in_mb < 48)
+			fprintf(stderr, "WARNING! 5800 will probably not run "
+			    "with less than 48MB RAM. Continuing anyway.\n");
+
+		/*
+		 *  According to
+		 *  http://www2.no.netbsd.org/ports/pmax/models.html,
+		 *  the 5800-series is based on VAX 6000/300.
+		 */
+
+		/*
+		 *  Ultrix might support SMP on this machine type.
+		 *
+		 *  Something at 0x10000000.
+		 *  ssc serial console at 0x10140000, interrupt 2 (shared
+		 *  with XMI?).
+		 *  xmi 0 at address 0x11800000   (node x at offset x*0x80000)
+		 *  Clock uses interrupt 3 (shared with XMI?).
+		 */
+
+		device_add(machine, "dec5800 addr=0x10000000");
+		device_add(machine, "decbi addr=0x10000000");
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].dec5800.28",
+		    machine->path, machine->bootstrap_cpu);
+		dev_ssc_init(machine, mem, 0x10140000,
+		    tmpstr, machine->x11_md.in_use);
+
+		dev_decxmi_init(mem, 0x11800000);
+		dev_deccca_init(mem, DEC_DECCCA_BASEADDR);
+
+		break;
+
+	case MACHINE_DEC_5400:		/*  type 6, KN210  */
+		machine->machine_name = strdup("DECsystem 5400 (KN210)");
+		/*
+		 *  Misc. info from the KN210 manual:
+		 *
+		 *  Interrupt lines:
+		 *	irq5	fpu
+		 *	irq4	halt
+		 *	irq3	pwrfl -> mer1 -> mer0 -> wear
+		 *	irq2	100 Hz -> birq7
+		 *	irq1	dssi -> ni -> birq6
+		 *	irq0	birq5 -> console -> timers -> birq4
+		 *
+		 *  Interrupt status register at 0x10048000.
+		 *  Main memory error status register at 0x1008140.
+		 *  Interval Timer Register (ITR) at 0x10084010.
+		 *  Q22 stuff at 0x10088000 - 0x1008ffff.
+		 *  TODR at 0x1014006c.
+		 *  TCR0 (timer control register 0) 0x10140100.
+		 *  TIR0 (timer interval register 0) 0x10140104.
+		 *  TCR1 (timer control register 1) 0x10140110.
+		 *  TIR1 (timer interval register 1) 0x10140114.
+		 *  VRR0 (Vector Read Register 0) at 0x16000050.
+		 *  VRR1 (Vector Read Register 1) at 0x16000054.
+		 *  VRR2 (Vector Read Register 2) at 0x16000058.
+		 *  VRR3 (Vector Read Register 3) at 0x1600005c.
+		 */
+		/*  ln (ethernet) at 0x10084x00 ? and 0x10120000 ?  */
+		/*  error registers (?) at 0x17000000 and 0x10080000  */
+		/*  device_add(machine, "kn210 addr=0x10080000");  */
+		dev_ssc_init(machine, mem, 0x10140000, "irq? TODO",
+		    machine->x11_md.in_use);
+		break;
+
+	case MACHINE_DEC_MAXINE_5000:	/*  type 7, KN02CA  */
+		machine->machine_name = strdup("Personal DECstation 5000/xxx "
+		    "(MAXINE) (KN02CA)");
+		if (machine->emulated_hz == 0)
+			machine->emulated_hz = 33000000;
+
+		if (machine->physical_ram_in_mb < 8)
+			fprintf(stderr, "WARNING! Real KN02CA machines do not "
+			    "have less than 8MB RAM. Continuing anyway.\n");
+		if (machine->physical_ram_in_mb > 40)
+			fprintf(stderr, "WARNING! Real KN02CA machines cannot "
+			    "have more than 40MB RAM. Continuing anyway.\n");
+
+		/*  Maxine interrupts:  */
+fatal("TODO: Legacy rewrite\n");
+abort();
+
+//		machine->md_interrupt = maxine_interrupt;
+
+		/*
+		 *  Something at address 0xca00000. (?)
+		 *  Something at address 0xe000000. (?)
+		 *  tc0 slot 0					(0x10000000)
+		 *  tc0 slot 1					(0x14000000)
+		 *  (tc0 slot 2 used by the framebuffer)
+		 *  ioasic0 at tc0 slot 3 offset 0x0		(0x1c000000)
+		 *  le0 at ioasic0 offset 0xc0000: address 00:00:00:00:00:00
+		 *						(0x1c0c0000)
+		 *  scc0 at ioasic0 offset 0x100000: console  <-- serial
+		 *						(0x1c100000)
+		 *  mcclock0 at ioasic0 offset 0x200000: mc146818 (0x1c200000)
+		 *  isdn at ioasic0 offset 0x240000 not configured (0x1c240000)
+		 *  bba0 at ioasic0 offset 0x240000 (audio0 at bba0)
+		 *	^--- which one of isdn and bba0?
+		 *  dtop0 at ioasic0 offset 0x280000		(0x1c280000)
+		 *  fdc at ioasic0 offset 0x2c0000 not configured
+		 *	^-- floppy				(0x1c2c0000)
+		 *  asc0 at ioasic0 offset 0x300000: NCR53C94, 25MHz, SCSI
+		 *	ID 7					(0x1c300000)
+		 *  xcfb0 at tc0 slot 2 offset 0x0: 1024x768x8
+		 *	built-in framebuffer			(0xa000000)
+		 */
+fatal("TODO: dec_ioasic legacy rewrite\n");
+abort();
+//		machine->md_int.dec_ioasic_data =
+//		    dev_dec_ioasic_init(cpu, mem, 0x1c000000, 0);
+
+fatal("TODO: turbochannel rewrite!\n");
+abort();
+#if 0
+		/*  TURBOchannel slots (0 and 1):  */
+		dev_turbochannel_init(machine, mem, 0,
+		    0x10000000, 0x103fffff,
+		    machine->n_gfx_cards >= 2?
+			turbochannel_default_gfx_card : "",
+		    XINE_INTR_TC_0 +8);
+		dev_turbochannel_init(machine, mem, 1,
+		    0x14000000, 0x143fffff,
+		    machine->n_gfx_cards >= 3?
+			turbochannel_default_gfx_card : "",
+		    XINE_INTR_TC_1 +8);
+
+		/*
+		 *  TURBOchannel slot 2 is hardwired to be used by
+		 *  the framebuffer: (NOTE: 0x8000000, not 0x18000000)
+		 */
+		dev_turbochannel_init(machine, mem, 2,
+		    0x8000000, 0xbffffff, "PMAG-DV", 0);
+#endif
+		/*
+		 *  TURBOchannel slot 3: fixed, ioasic
+		 *  (the system stuff), 0x1c000000
+		 */
+fatal("TODO: xine dev_le_init rewrite\n");
+abort();
+//		dev_le_init(machine, mem, 0x1c0c0000, 0, 0,
+//		    XINE_INTR_LANCE +8, 4*65536);
+//		dev_scc_init(machine, mem, 0x1c100000,
+//		    XINE_INTR_SCC_0 +8, machine->x11_md.in_use, 0, 1);
+fatal("TODO: mc146818 irq\n");
+abort();
+//		dev_mc146818_init(machine, mem, 0x1c200000,
+//		    XINE_INT_TOY, MC146818_DEC, 1);
+fatal("TODO: xine asc init rewrite\n");
+abort();
+//		dev_asc_init(machine, mem, 0x1c300000,
+//		    XINE_INTR_SCSI +8, NULL, DEV_ASC_DEC, NULL, NULL);
+
+		framebuffer_console_name = "osconsole=3,2";	/*  keyb,fb?  */
+		serial_console_name      = "osconsole=3";
+		break;
+
+	case MACHINE_DEC_5500:	/*  type 11, KN220  */
+		machine->machine_name = strdup("DECsystem 5500 (KN220)");
+
+		/*
+		 *  According to NetBSD's pmax ports page:
+		 *  KN220-AA is a "30 MHz R3000 CPU with R3010 FPU"
+		 *  with "512 kBytes of Prestoserve battery backed RAM."
+		 */
+		if (machine->emulated_hz == 0)
+			machine->emulated_hz = 30000000;
+
+		/*
+		 *  See KN220 docs for more info.
+		 *
+		 *  something at 0x10000000
+		 *  something at 0x10001000
+		 *  something at 0x10040000
+		 *  scc at 0x10140000
+		 *  qbus at (or around) 0x10080000
+		 *  dssi (disk controller) buffers at 0x10100000,
+		 *	registers at 0x10160000.
+		 *  sgec (ethernet) registers at 0x10008000, station
+		 *	addresss at 0x10120000.
+		 *  asc (scsi) at 0x17100000.
+		 */
+
+		dev_ssc_init(machine, mem, 0x10140000, "TODO: irq",
+		    machine->x11_md.in_use);
+
+		/*  something at 0x17000000, ultrix says "cpu 0 panic: "
+		    "DS5500 I/O Board is missing" if this is not here  */
+		dev_dec5500_ioboard_init(cpu, mem, 0x17000000);
+
+		dev_sgec_init(mem, 0x10008000, 0);		/*  irq?  */
+
+		/*  The asc controller might be TURBOchannel-ish?  */
+#if 0
+		dev_turbochannel_init(machine, mem, 0, 0x17100000,
+		    0x171fffff, "PMAZ-AA", 0);	/*  irq?  */
+#else
+		dev_asc_init(machine, mem, 0x17100000, 0, NULL,
+		    DEV_ASC_DEC, NULL, NULL);		/*  irq?  */
+#endif
+
+		framebuffer_console_name = "osconsole=0,0";	/*  TODO (?)  */
+		serial_console_name      = "osconsole=0";
+		break;
+
+	case MACHINE_DEC_MIPSMATE_5100:	/*  type 12  */
+		machine->machine_name = strdup("DEC MIPSMATE 5100 (KN230)");
+
+		if (machine->emulated_hz == 0)
+			machine->emulated_hz = 20000000;
+
+		if (machine->physical_ram_in_mb > 128)
+			fprintf(stderr, "WARNING! Real MIPSMATE 5100 machines "
+			    "cannot have more than 128MB RAM. Continuing"
+			    " anyway.\n");
+
+		if (machine->x11_md.in_use)
+			fprintf(stderr, "WARNING! Real MIPSMATE 5100 machines "
+			    "cannot have a graphical framebuffer. "
+			    "Continuing anyway.\n");
+
+		/*  KN230 mainbus / interrupt controller:  */
+		snprintf(tmpstr, sizeof(tmpstr),
+		    "kn230 addr=0x%" PRIx64, (uint64_t) KN230_SYS_ICSR);
+		device_add(machine, tmpstr);
+
+		/*
+		 *  According to NetBSD/pmax:
+		 *  dc0 at ibus0 addr 0x1c000000
+		 *  le0 at ibus0 addr 0x18000000: address 00:00:00:00:00:00
+		 *  sii0 at ibus0 addr 0x1a000000
+		 */
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
+		    machine->path, machine->bootstrap_cpu, 4);
+		dev_mc146818_init(machine, mem, KN230_SYS_CLOCK, tmpstr,
+		    MC146818_DEC, 1);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].kn230.0x%x",
+		    machine->path, machine->bootstrap_cpu, KN230_CSR_INTR_DZ0);
+		dev_dc7085_init(machine, mem, KN230_SYS_DZ0,
+		    tmpstr, machine->x11_md.in_use);
+
+		/* dev_dc7085_init(machine, mem, KN230_SYS_DZ1,
+		    KN230_CSR_INTR_OPT0, machine->x11_md.in_use);  */
+		/* dev_dc7085_init(machine, mem, KN230_SYS_DZ2,
+		    KN230_CSR_INTR_OPT1, machine->x11_md.in_use);  */
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].kn230.0x%x",
+		    machine->path, machine->bootstrap_cpu,
+		    KN230_CSR_INTR_LANCE);
+		dev_le_init(machine, mem, KN230_SYS_LANCE,
+		    KN230_SYS_LANCE_B_START, KN230_SYS_LANCE_B_END,
+		    tmpstr, 4*1048576);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].kn230.0x%x",
+		    machine->path, machine->bootstrap_cpu, KN230_CSR_INTR_SII);
+		dev_sii_init(machine, mem, KN230_SYS_SII,
+		    KN230_SYS_SII_B_START, KN230_SYS_SII_B_END, tmpstr);
+
+		serial_console_name = "osconsole=0";
+		break;
+
+	default:fatal("Unknown DEC machine type: %i\n",
+		    machine->machine_subtype);
+		exit(1);
+	}
+
+	/*
+	 *  Most OSes on DECstation use physical addresses below
+	 *  0x20000000, but both OSF/1 and Sprite use 0xbe...... as if
+	 *  it was 0x1e......, so we need this hack:
+	 */
+	dev_ram_init(machine, 0xa0000000, 0x20000000,
+	    DEV_RAM_MIRROR | DEV_RAM_MIGHT_POINT_TO_DEVICES, 0x0, NULL);
+
+
+	if (machine->machine_type == MACHINE_PMAX &&
+	    cpu->cd.mips.cpu_type.mmu_model == MMU3K)
+		add_symbol_name(&machine->symbol_context,
+		    0x9fff0000, 0x10000, "r2k3k_cache", 0, 0);
+
+
+	if (!machine->prom_emulation)
+		return;
+
+
+	/*  DECstation PROM stuff:  (TODO: endianness)  */
+	for (i=0; i<150; i++)
+		store_32bit_word(cpu, DEC_PROM_CALLBACK_STRUCT + i*4,
+		    DEC_PROM_EMULATION + i*8);
+
+	/*  Fill PROM with special "magic trap" instructions:  */
+	for (i=0; i<150; i++) {
+		store_32bit_word(cpu, DEC_PROM_EMULATION + i*8,
+		    0x00c0de0c);	/*  trap instruction  */
+		store_32bit_word(cpu, DEC_PROM_EMULATION + i*8 + 4,
+		    0x00000000);	/*  nop  */
+	}
+
+	/*  Jumptable at beginning of PROM:  also "magic trap" instructions:  */
+	for (i=0; i<0x180; i+=8) {
+		store_32bit_word(cpu, 0xbfc00000 + i,
+		    0x00c0de0c);	/*  trap instruction  */
+		store_32bit_word(cpu, 0xbfc00000 + i + 4,
+		    0x00000000);	/*  nop  */
+	}
+
+
+	/*
+	 *  According to dec_prom.h from NetBSD:
+	 *
+	 *  "Programs loaded by the new PROMs pass the following arguments:
+	 *	a0	argc
+	 *	a1	argv
+	 *	a2	DEC_PROM_MAGIC
+	 *	a3	The callback vector defined below"
+	 *
+	 *  So we try to emulate a PROM, even though no such thing has been
+	 *  loaded.
+	 */
+
+	cpu->cd.mips.gpr[MIPS_GPR_A0] = 3;
+	cpu->cd.mips.gpr[MIPS_GPR_A1] = DEC_PROM_INITIAL_ARGV;
+	cpu->cd.mips.gpr[MIPS_GPR_A2] = DEC_PROM_MAGIC;
+	cpu->cd.mips.gpr[MIPS_GPR_A3] = DEC_PROM_CALLBACK_STRUCT;
+
+	store_32bit_word(cpu, INITIAL_STACK_POINTER + 0x10, BOOTINFO_MAGIC);
+	store_32bit_word(cpu, INITIAL_STACK_POINTER + 0x14, BOOTINFO_ADDR);
+
+	store_32bit_word(cpu, DEC_PROM_INITIAL_ARGV,
+	    (DEC_PROM_INITIAL_ARGV + 0x10));
+	store_32bit_word(cpu, DEC_PROM_INITIAL_ARGV+4,
+	    (DEC_PROM_INITIAL_ARGV + 0x70));
+	store_32bit_word(cpu, DEC_PROM_INITIAL_ARGV+8,
+	    (DEC_PROM_INITIAL_ARGV + 0xe0));
+	store_32bit_word(cpu, DEC_PROM_INITIAL_ARGV+12, 0);
+
+	/*
+	 *  NetBSD and Ultrix expect the boot args to be like this:
+	 *
+	 *	"boot" "bootdev" [args?]
+	 *
+	 *  where bootdev is supposed to be "rz(0,0,0)netbsd" for
+	 *  3100/2100 (although that crashes Ultrix :-/), and
+	 *  "5/rz0a/netbsd" for all others.  The number '5' is the
+	 *  slot number of the boot device.
+	 *
+	 *  'rz' for disks, 'tz' for tapes.
+	 */
+	{
+#if 0
+		if (machine->machine_subtype == MACHINE_DEC_PMAX_3100)
+			strlcpy(bootpath, "rz(0,0,0)", sizeof(bootpath));
+		else
+#endif
+			strlcpy(bootpath, "X/rzY/", sizeof(bootpath));
+
+		if (machine->bootdev_id < 0 || machine->force_netboot) {
+			/*  tftp boot:  */
+			strlcpy(bootpath, "5/tftp/", sizeof(bootpath));
+			bootpath[0] = '0' + boot_net_boardnumber;
+		} else {
+			/*  disk boot:  */
+			bootpath[0] = '0' + boot_scsi_boardnumber;
+			if (diskimage_is_a_tape(machine, machine->bootdev_id,
+			    machine->bootdev_type))
+				bootpath[2] = 't';
+			bootpath[4] = '0' + machine->bootdev_id;
+		}
+
+		init_bootpath = bootpath;
+	}
+
+	CHECK_ALLOCATION(machine->bootarg = (char *) malloc(BOOTARG_BUFLEN));
+	strlcpy(machine->bootarg, init_bootpath, BOOTARG_BUFLEN);
+	if (strlcat(machine->bootarg, machine->boot_kernel_filename,
+	    BOOTARG_BUFLEN) > BOOTARG_BUFLEN) {
+		fprintf(stderr, "bootarg truncated?\n");
+		exit(1);
+	}
+
+	machine->bootstr = strdup("boot");
+
+	store_string(cpu, DEC_PROM_INITIAL_ARGV+0x10, machine->bootstr);
+	store_string(cpu, DEC_PROM_INITIAL_ARGV+0x70, machine->bootarg);
+	store_string(cpu, DEC_PROM_INITIAL_ARGV+0xe0,
+	    machine->boot_string_argument);
+
+	/*  Decrease the nr of args, if there are no args :-)  */
+	if (machine->boot_string_argument == NULL ||
+	    machine->boot_string_argument[0] == '\0')
+		cpu->cd.mips.gpr[MIPS_GPR_A0] --;
+
+	if (machine->boot_string_argument[0] != '\0') {
+		strlcat(machine->bootarg, " ", BOOTARG_BUFLEN);
+		if (strlcat(machine->bootarg, machine->boot_string_argument,
+		    BOOTARG_BUFLEN) >= BOOTARG_BUFLEN) {
+			fprintf(stderr, "bootstr truncated?\n");
+			exit(1);
+		}
+	}
+
+	xx.a.common.next = (char *)&xx.b - (char *)&xx;
+	xx.a.common.type = BTINFO_MAGIC;
+	xx.a.magic = BOOTINFO_MAGIC;
+
+	xx.b.common.next = (char *)&xx.c - (char *)&xx.b;
+	xx.b.common.type = BTINFO_BOOTPATH;
+	strlcpy(xx.b.bootpath, machine->bootstr, sizeof(xx.b.bootpath));
+
+	xx.c.common.next = 0;
+	xx.c.common.type = BTINFO_SYMTAB;
+	xx.c.nsym = 0;
+	xx.c.ssym = 0;
+	xx.c.esym = machine->file_loaded_end_addr;
+
+	store_buf(cpu, BOOTINFO_ADDR, (char *)&xx, sizeof(xx));
+
+	CHECK_ALLOCATION(machine->md.pmax = (struct machine_pmax *)
+	    malloc(sizeof(struct machine_pmax)));
+	memset(machine->md.pmax, 0, sizeof(struct machine_pmax));
+
+	/*  The system's memmap:  */
+	CHECK_ALLOCATION(machine->md.pmax->memmap = (struct dec_memmap *)
+	    malloc(sizeof(struct dec_memmap)));
+	store_32bit_word_in_host(cpu,
+	    (unsigned char *)&machine->md.pmax->memmap->pagesize, 4096);
+
+	for (unsigned int j=0; j<sizeof(machine->md.pmax->memmap->bitmap); j++)
+		machine->md.pmax->memmap->bitmap[j] = (j * 4096*8 <
+		    1048576*machine->physical_ram_in_mb)? 0xff : 0x00;
+
+	store_buf(cpu, DEC_MEMMAP_ADDR,
+	    (char *)machine->md.pmax->memmap, sizeof(struct dec_memmap));
+
+	/*  Environment variables:  */
+	addr = DEC_PROM_STRINGS;
+
+	if (machine->x11_md.in_use && machine->n_gfx_cards > 0)
+		/*  (0,3)  Keyboard and Framebuffer  */
+		add_environment_string(cpu, framebuffer_console_name, &addr);
+	else
+		/*  Serial console  */
+		add_environment_string(cpu, serial_console_name, &addr);
+
+	/*
+	 *  The KN5800 (SMP system) uses a CCA (console communications
+	 *  area):  (See VAX 6000 documentation for details.)
+	 */
+	{
+		char tmps[300];
+		snprintf(tmps, sizeof(tmps), "cca=%" PRIx32,
+		    (uint32_t) (DEC_DECCCA_BASEADDR + 0xa0000000ULL));
+		add_environment_string(cpu, tmps, &addr);
+	}
+
+	/*  These are needed for Sprite to boot:  */
+	{
+		char tmps[500];
+
+		snprintf(tmps, sizeof(tmps), "boot=%s", machine->bootarg);
+		tmps[sizeof(tmps)-1] = '\0';
+		add_environment_string(cpu, tmps, &addr);
+
+		snprintf(tmps, sizeof(tmps), "bitmap=0x%" PRIx32, (uint32_t)
+		    ( (DEC_MEMMAP_ADDR + sizeof(uint32_t) /* skip the
+			page size and point to the memmap */
+		    ) & 0xffffffffULL) );
+		tmps[sizeof(tmps)-1] = '\0';
+		add_environment_string(cpu, tmps, &addr);
+
+		snprintf(tmps, sizeof(tmps), "bitmaplen=0x%" PRIx32, (uint32_t)
+		    ( machine->physical_ram_in_mb * 1048576 / 4096 / 8) );
+		tmps[sizeof(tmps)-1] = '\0';
+		add_environment_string(cpu, tmps, &addr);
+	}
+
+	add_environment_string(cpu, "scsiid0=7", &addr);
+	add_environment_string(cpu, "bootmode=a", &addr);
+	add_environment_string(cpu, "testaction=q", &addr);
+	add_environment_string(cpu, "haltaction=h", &addr);
+	add_environment_string(cpu, "more=24", &addr);
+
+	/*  Used in at least Ultrix on the 5100:  */
+	add_environment_string(cpu, "scsiid=7", &addr);
+	add_environment_string(cpu, "baud0=9600", &addr);
+	add_environment_string(cpu, "baud1=9600", &addr);
+	add_environment_string(cpu, "baud2=9600", &addr);
+	add_environment_string(cpu, "baud3=9600", &addr);
+	add_environment_string(cpu, "iooption=0x1", &addr);
+
+	/*  The end:  */
+	add_environment_string(cpu, "", &addr);
+}
+
+
+MACHINE_DEFAULT_CPU(pmax)
+{
+	if (machine->machine_subtype > 2)
+		CHECK_ALLOCATION(machine->cpu_name = strdup("R3000A"));
+
+	if (machine->machine_subtype > 1 && machine->cpu_name == NULL)
+		CHECK_ALLOCATION(machine->cpu_name = strdup("R3000"));
+
+	if (machine->cpu_name == NULL)
+		CHECK_ALLOCATION(machine->cpu_name = strdup("R2000"));
+}
+
+
+MACHINE_DEFAULT_RAM(pmax)
+{
+	switch (machine->machine_subtype) {
+	case MACHINE_DEC_PMAX_3100:
+		machine->physical_ram_in_mb = 24;
+		break;
+	case MACHINE_DEC_3MAX_5000:
+		machine->physical_ram_in_mb = 64;
+		break;
+	default:machine->physical_ram_in_mb = 32;
+	}
+}
+
+
+MACHINE_REGISTER(pmax)
+{
+	MR_DEFAULT(pmax, "DECstation/DECsystem", MACHINE_PMAX);
+
+	machine_entry_add_alias(me, "decstation");
+	machine_entry_add_alias(me, "decsystem");
+	machine_entry_add_alias(me, "dec");
+
+	machine_entry_add_subtype(me, "DECstation 3100 (PMAX)",
+	    MACHINE_DEC_PMAX_3100, "pmax", "3100", "2100", NULL);
+
+	machine_entry_add_subtype(me, "DECstation 5000/200 (3MAX)",
+	    MACHINE_DEC_3MAX_5000, "3max", "5000/200", NULL);
+
+	machine_entry_add_subtype(me, "DECstation 5000/1xx (3MIN)",
+	    MACHINE_DEC_3MIN_5000, "3min", "5000/1xx", NULL);
+
+	machine_entry_add_subtype(me, "DECstation 5000 (3MAXPLUS)",
+	    MACHINE_DEC_3MAXPLUS_5000, "3maxplus", "3max+", NULL);
+
+	machine_entry_add_subtype(me, "DECsystem 58x0",
+	    MACHINE_DEC_5800, "5800", "58x0", NULL);
+
+	machine_entry_add_subtype(me, "DECsystem 5400",
+	    MACHINE_DEC_5400, "5400", NULL);
+
+	machine_entry_add_subtype(me, "DECstation Maxine (5000)",
+	    MACHINE_DEC_MAXINE_5000, "maxine", NULL);
+
+	machine_entry_add_subtype(me, "DECsystem 5500",
+	    MACHINE_DEC_5500, "5500", NULL);
+
+	machine_entry_add_subtype(me, "DECstation MipsMate (5100)",
+	    MACHINE_DEC_MIPSMATE_5100, "5100", "mipsmate", NULL);
+
+	me->set_default_ram = machine_default_ram_pmax;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_pmax.cc gxemul-0.7.0+dfsg/src/machines/machine_pmax.cc
--- gxemul-0.6.2/src/machines/machine_pmax.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_pmax.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1010 +0,0 @@
-/*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Digital DECstation ("PMAX") machines
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "machine_pmax.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/dec_prom.h"
-#include "thirdparty/dec_bootinfo.h"
-#include "thirdparty/dec_5100.h"
-#include "thirdparty/dec_kn01.h"
-#include "thirdparty/dec_kn02.h"  
-#include "thirdparty/dec_kn03.h"
-#include "thirdparty/dec_kmin.h"
-#include "thirdparty/dec_maxine.h"
-
-#define	BOOTARG_BUFLEN		2000
-
-
-MACHINE_SETUP(pmax)
-{
-	const char *framebuffer_console_name, *serial_console_name;
-	char bootpath[200];
-	char *init_bootpath;
-	int color_fb_flag, i;
-	int boot_scsi_boardnumber = 3, boot_net_boardnumber = 3;
-	const char *turbochannel_default_gfx_card = "PMAG-BA";
-		/*  PMAG-AA, -BA, -CA/DA/EA/FA, -JA, -RO, PMAGB-BA  */
-	struct xx {
-		struct btinfo_magic a;
-		struct btinfo_bootpath b;
-		struct btinfo_symtab c;
-	} xx;
-	char tmpstr[1000];
-	struct vfb_data *fb;
-	struct memory *mem = machine->memory;
-	uint64_t addr;
-
-	cpu->byte_order = EMUL_LITTLE_ENDIAN;
-
-	/*
-	 *  Add an R2020 or R3220 writeback memory thing:
-	 */
-	cpu->cd.mips.coproc[3] = mips_coproc_new(cpu, 3);
-
-	/*  There aren't really any good standard values...  */
-	framebuffer_console_name = "osconsole=0,3";
-	serial_console_name      = "osconsole=1";
-
-	switch (machine->machine_subtype) {
-
-	case MACHINE_DEC_PMAX_3100:		/*  type  1, KN01  */
-		/*  Supposed to have 12MHz or 16.67MHz R2000 CPU, R2010 FPC,
-		    R2020 Memory coprocessor  */
-		machine->machine_name = strdup("DEC PMAX 3100 (KN01)");
-
-		/*  12 MHz for 2100, 16.67 MHz for 3100  */
-		if (machine->emulated_hz == 0)
-			machine->emulated_hz = 16670000;
-
-		if (machine->physical_ram_in_mb > 24)
-			fprintf(stderr, "WARNING! Real DECstation 3100 machines"
-			    " cannot have more than 24MB RAM.\n");
-
-		if ((machine->physical_ram_in_mb % 4) != 0)
-			fprintf(stderr, "WARNING! Real DECstation 3100 machines"
-			    " have an integer multiple of 4 MBs of RAM.\n");
-
-		/*  1 for color, 0 for mono. TODO: command line option?  */
-		color_fb_flag = 1;
-
-		/*
-		 *  According to NetBSD/pmax:
-		 *
-		 *  pm0 at ibus0 addr 0xfc00000: 1024x864x1  (or x8 for color)
-		 *  dc0 at ibus0 addr 0x1c000000
-		 *  le0 at ibus0 addr 0x18000000: address 00:00:00:00:00:00
-		 *  sii0 at ibus0 addr 0x1a000000
-		 *  mcclock0 at ibus0 addr 0x1d000000: mc146818 or compatible
-		 *  0x1e000000 = system status and control register
-		 */
-		fb = dev_fb_init(machine, mem, KN01_PHYS_FBUF_START,
-		    color_fb_flag? VFB_DEC_VFB02 : VFB_DEC_VFB01,
-		    0,0,0,0,0, color_fb_flag? "VFB02":"VFB01");
-		dev_colorplanemask_init(mem, KN01_PHYS_COLMASK_START,
-		    &fb->color_plane_mask);
-		dev_vdac_init(mem, KN01_SYS_VDAC, fb->rgb_palette,
-		    color_fb_flag);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
-		    machine->path, machine->bootstrap_cpu, KN01_INT_LANCE);
-		dev_le_init(machine, mem, KN01_SYS_LANCE,
-		    KN01_SYS_LANCE_B_START, KN01_SYS_LANCE_B_END,
-		    tmpstr, 4*1048576);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
-		    machine->path, machine->bootstrap_cpu, KN01_INT_SII);
-		dev_sii_init(machine, mem, KN01_SYS_SII, KN01_SYS_SII_B_START,
-		    KN01_SYS_SII_B_END, tmpstr);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
-		    machine->path, machine->bootstrap_cpu, KN01_INT_DZ);
-		dev_dc7085_init(machine, mem, KN01_SYS_DZ, tmpstr,
-		    machine->x11_md.in_use);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
-		    machine->path, machine->bootstrap_cpu, KN01_INT_CLOCK);
-		dev_mc146818_init(machine, mem, KN01_SYS_CLOCK, tmpstr,
-		    MC146818_DEC, 1);
-
-		dev_kn01_init(mem, KN01_SYS_CSR, color_fb_flag);
-
-		framebuffer_console_name = "osconsole=0,3";	/*  fb,keyb  */
-		serial_console_name      = "osconsole=3";	/*  3  */
-		break;
-
-	case MACHINE_DEC_3MAX_5000:		/*  type  2, KN02  */
-		/*  Supposed to have 25MHz R3000 CPU, R3010 FPC,  */
-		/*  and a R3220 Memory coprocessor  */
-		machine->machine_name = strdup("DECstation 5000/200 (3MAX, KN02)");
-
-		if (machine->emulated_hz == 0)
-			machine->emulated_hz = 25000000;
-
-		if (machine->physical_ram_in_mb < 8)
-			fprintf(stderr, "WARNING! Real KN02 machines do not "
-			    "have less than 8MB RAM. Continuing anyway.\n");
-		if (machine->physical_ram_in_mb > 480)
-			fprintf(stderr, "WARNING! Real KN02 machines cannot "
-			    "have more than 480MB RAM. Continuing anyway.\n");
-
-		/*  An R3220 memory thingy:  */
-		cpu->cd.mips.coproc[3] = mips_coproc_new(cpu, 3);
-
-		/*
-		 *  According to NetBSD/pmax:
-		 *  asc0 at tc0 slot 5 offset 0x0
-		 *  le0 at tc0 slot 6 offset 0x0
-		 *  ibus0 at tc0 slot 7 offset 0x0
-		 *  dc0 at ibus0 addr 0x1fe00000
-		 *  mcclock0 at ibus0 addr 0x1fe80000: mc146818
-		 */
-
-		/*  KN02 mainbus (TurboChannel interrupt controller):  */
-		snprintf(tmpstr, sizeof(tmpstr), "kn02 addr=0x%x "
-		    "irq=%s.cpu[%i].2", (int) KN02_SYS_CSR,
-		    machine->path, machine->bootstrap_cpu);
-		device_add(machine, tmpstr);
-
-		/*
-		 *  TURBOchannel slots 0, 1, and 2 are free for option cards.
-		 *  Let's put in zero or more graphics boards:
-		 *
-		 *  TODO: It's also possible to have larger graphics cards that
-		 *  occupy several slots. How should this be solved nicely?
-		 */
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.kn02.%i",
-		    machine->path, machine->bootstrap_cpu, 0);
-		dev_turbochannel_init(machine, mem, 0,
-		    KN02_PHYS_TC_0_START, KN02_PHYS_TC_0_END,
-		    machine->n_gfx_cards >= 1?
-			turbochannel_default_gfx_card : "",
-		    tmpstr);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.kn02.%i",
-		    machine->path, machine->bootstrap_cpu, 1);
-		dev_turbochannel_init(machine, mem, 1,
-		    KN02_PHYS_TC_1_START, KN02_PHYS_TC_1_END,
-		    machine->n_gfx_cards >= 2?
-			turbochannel_default_gfx_card : "",
-		    tmpstr);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.kn02.%i",
-		    machine->path, machine->bootstrap_cpu, 2);
-		dev_turbochannel_init(machine, mem, 2,
-		    KN02_PHYS_TC_2_START, KN02_PHYS_TC_2_END,
-		    machine->n_gfx_cards >= 3?
-			turbochannel_default_gfx_card : "",
-		    tmpstr);
-
-		/*  TURBOchannel slots 3 and 4 are reserved.  */
-
-		/*  TURBOchannel slot 5 is PMAZ-AA ("asc" SCSI).  */
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.kn02.%i",
-		    machine->path, machine->bootstrap_cpu, 5);
-		dev_turbochannel_init(machine, mem, 5,
-		    KN02_PHYS_TC_5_START, KN02_PHYS_TC_5_END,
-		    "PMAZ-AA", tmpstr);
-
-		/*  TURBOchannel slot 6 is PMAD-AA ("le" ethernet).  */
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.kn02.%i",
-		    machine->path, machine->bootstrap_cpu, 6);
-		dev_turbochannel_init(machine, mem, 6,
-		    KN02_PHYS_TC_6_START, KN02_PHYS_TC_6_END,
-		    "PMAD-AA", tmpstr);
-
-		/*  TURBOchannel slot 7 is system stuff.  */
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.kn02.%i",
-		    machine->path, machine->bootstrap_cpu, 7);
-		machine->main_console_handle =
-		    dev_dc7085_init(machine, mem,
-		    KN02_SYS_DZ, tmpstr, machine->x11_md.in_use);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
-		    machine->path, machine->bootstrap_cpu, KN02_INT_CLOCK);
-		dev_mc146818_init(machine, mem,
-		    KN02_SYS_CLOCK, tmpstr, MC146818_DEC, 1);
-
-		framebuffer_console_name = "osconsole=0,7";
-								/*  fb,keyb  */
-		serial_console_name      = "osconsole=2";
-		boot_scsi_boardnumber = 5;
-		boot_net_boardnumber = 6;	/*  TODO: 3?  */
-		break;
-
-	case MACHINE_DEC_3MIN_5000:		/*  type 3, KN02BA  */
-		machine->machine_name = strdup("DECstation 5000/112, 125, or 145 (3MIN,"
-		    " KN02BA)");
-		if (machine->emulated_hz == 0)
-			machine->emulated_hz = 33000000;
-		if (machine->physical_ram_in_mb > 128)
-			fprintf(stderr, "WARNING! Real 3MIN machines cannot "
-			    "have more than 128MB RAM. Continuing anyway.\n");
-
-		/*  KN02BA "3min" TurboChannel interrupt controller:  */
-		snprintf(tmpstr, sizeof(tmpstr), "kn02ba irq=%s.cpu[%i].%i",
-		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC3);
-		device_add(machine, tmpstr);
-
-		/*
-		 *  tc0 at mainbus0: 12.5 MHz clock  (0x10000000,slotsize=64MB)
-		 *  tc slot 1:   0x14000000
-		 *  tc slot 2:   0x18000000
-		 *  ioasic0 at tc0 slot 3 offset 0x0	(0x1c000000) slot 0
-		 *  asic regs				(0x1c040000) slot 1
-		 *  station's ether address		(0x1c080000) slot 2
-		 *  le0 at ioasic0 offset 0xc0000: address 00:00:00:00:00:00
-		 *					(0x1c0c0000) slot 3
-		 *  scc0 at ioasic0 offset 0x100000	(0x1c100000) slot 4
-		 *  scc1 at ioasic0 offset 0x180000: console(0x1c180000) slot 6
-		 *  mcclock0 at ioasic0 offset 0x200000: mc146818 or
-		 *	compatible			(0x1c200000) slot 8
-		 *  asc0 at ioasic0 offset 0x300000: NCR53C94, 25MHz,
-		 *	SCSI ID 7			(0x1c300000) slot 12
-		 *  dma for asc0			(0x1c380000) slot 14
-		 */
-
-////fatal("TODO: kmin dev_le_init.\n");
-////abort();
-//		dev_le_init(machine, mem, 0x1c0c0000, 0, 0,
-//		    KMIN_INTR_LANCE + 8, 4 * 65536);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i.kn02ba.0x%x",
-		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC3, KMIN_INTR_SCC_0);
-		dev_scc_init(machine, mem, 0x1c100000, tmpstr,
-		    machine->x11_md.in_use, 0, 1);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i.kn02ba.0x%x",
-		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC3, KMIN_INTR_SCC_1);
-		dev_scc_init(machine, mem, 0x1c180000, tmpstr,
-		    machine->x11_md.in_use, 1, 1);
-
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i.kn02ba.0x%x",
-		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC3, KMIN_INTR_CLOCK);
-		dev_mc146818_init(machine, mem,
-		    KMIN_SYS_CLOCK, tmpstr, MC146818_DEC, 1);
-		    
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i.kn02ba.0x%x",
-		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC3, KMIN_INTR_SCSI);
-		dev_asc_init(machine, mem, 0x1c300000, tmpstr,
-		    NULL, DEV_ASC_DEC, NULL, NULL);
-
-		/*
-		 *  TURBOchannel slots 0, 1, and 2 are free for
-		 *  option cards.  These are by default filled with
-		 *  zero or more graphics boards.
-		 *
-		 *  TODO: irqs 
-		 */
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
-		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC0);
-		dev_turbochannel_init(machine, mem, 0,
-		    KMIN_PHYS_TC_0_START, KMIN_PHYS_TC_0_END,
-		    machine->n_gfx_cards >= 1?
-			turbochannel_default_gfx_card : "",
-		    tmpstr);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
-		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC1);
-		dev_turbochannel_init(machine, mem, 0,
-		    KMIN_PHYS_TC_1_START, KMIN_PHYS_TC_1_END,
-		    machine->n_gfx_cards >= 2?
-			turbochannel_default_gfx_card : "",
-		    tmpstr);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
-		    machine->path, machine->bootstrap_cpu, KMIN_INT_TC2);
-		dev_turbochannel_init(machine, mem, 0,
-		    KMIN_PHYS_TC_2_START, KMIN_PHYS_TC_2_END,
-		    machine->n_gfx_cards >= 3?
-			turbochannel_default_gfx_card : "",
-		    tmpstr);
-
-		/*  (kmin shared irq numbers (IP) are offset by +8 in the
-		    emulator)  */
-		/*  kmin_csr = dev_kmin_init(cpu, mem, KMIN_REG_INTR);  */
-
-		framebuffer_console_name = "osconsole=0,3";	/* fb,keyb(?) */
-		serial_console_name      = "osconsole=3";	/* ? */
-		break;
-
-	case MACHINE_DEC_3MAXPLUS_5000:	/*  type 4, KN03  */
-		machine->machine_name = strdup("DECsystem 5900 or 5000 (3MAX+) (KN03)");
-
-		/*  5000/240 (KN03-GA, R3000): 40 MHz  */
-		/*  5000/260 (KN05-NB, R4000): 60 MHz  */
-		/*  TODO: are both these type 4?  */
-		if (machine->emulated_hz == 0)
-			machine->emulated_hz = 40000000;
-		if (machine->physical_ram_in_mb > 480)
-			fprintf(stderr, "WARNING! Real KN03 machines cannot "
-			    "have more than 480MB RAM. Continuing anyway.\n");
-
-		/*  KN03 interrupts:  */
-fatal("TODO: Legacy rewrite\n");
-abort();
-//		machine->md_interrupt = kn03_interrupt;
-
-		/*
-		 *  tc0 at mainbus0: 25 MHz clock (slot 0)	(0x1e000000)
-		 *  tc0 slot 1					(0x1e800000)
-		 *  tc0 slot 2					(0x1f000000)
-		 *  ioasic0 at tc0 slot 3 offset 0x0		(0x1f800000)
-		 *    something that has to do with interrupts? (?)(0x1f840000?)
-		 *  le0 at ioasic0 offset 0xc0000		(0x1f8c0000)
-		 *  scc0 at ioasic0 offset 0x100000		(0x1f900000)
-		 *  scc1 at ioasic0 offset 0x180000: console	(0x1f980000)
-		 *  mcclock0 at ioasic0 offset 0x200000: mc146818 or
-		 *	compatible				(0x1fa00000)
-		 *  asc0 at ioasic0 offset 0x300000: NCR53C94, 25MHz,
-		 *	SCSI ID 7				(0x1fb00000)
-		 */
-fatal("TODO: dec_ioasic legacy rewrite\n");
-abort();
-//		machine->md_int.dec_ioasic_data = dev_dec_ioasic_init(cpu,
-//		    mem, 0x1f800000, 0);
-
-fatal("TODO: kn03 dev_le_init rewrite\n");
-abort();
-//		dev_le_init(machine, mem, KN03_SYS_LANCE, 0, 0,
-//		    KN03_INTR_LANCE +8, 4 * 65536);
-
-fatal("TODO: dec_ioasic legacy rewrite\n");
-abort();
-//		machine->md_int.dec_ioasic_data->dma_func[3] =
-//		    dev_scc_dma_func;
-//		machine->md_int.dec_ioasic_data->dma_func_extra[2] =
-//		    dev_scc_init(machine, mem, KN03_SYS_SCC_0,
-//		    KN03_INTR_SCC_0 +8, machine->x11_md.in_use, 0, 1);
-//		machine->md_int.dec_ioasic_data->dma_func[2] =
-//		    dev_scc_dma_func;
-//		machine->md_int.dec_ioasic_data->dma_func_extra[3] =
-//		    dev_scc_init(machine, mem, KN03_SYS_SCC_1,
-//		    KN03_INTR_SCC_1 +8, machine->x11_md.in_use, 1, 1);
-
-fatal("TODO: mc146818 irq\n");
-abort();
-//		dev_mc146818_init(machine, mem, KN03_SYS_CLOCK, KN03_INT_RTC,
-//		    MC146818_DEC, 1);
-fatal("TODO: asc init rewrite\n");
-abort();
-//		dev_asc_init(machine, mem, KN03_SYS_SCSI,
-//		    KN03_INTR_SCSI +8, NULL, DEV_ASC_DEC, NULL, NULL);
-
-		/*
-		 *  TURBOchannel slots 0, 1, and 2 are free for
-		 *  option cards.  These are by default filled with
-		 *  zero or more graphics boards.
-		 *
-		 *  TODO: irqs 
-		 */
-fatal("TODO: turbochannel rewrite init\n");
-abort();
-#if 0
-		dev_turbochannel_init(machine, mem, 0,
-		    KN03_PHYS_TC_0_START, KN03_PHYS_TC_0_END,
-		    machine->n_gfx_cards >= 1?
-			turbochannel_default_gfx_card : "",
-		    KN03_INTR_TC_0 +8);
-
-		dev_turbochannel_init(machine, mem, 1,
-		    KN03_PHYS_TC_1_START, KN03_PHYS_TC_1_END,
-		    machine->n_gfx_cards >= 2?
-			turbochannel_default_gfx_card : "",
-		    KN03_INTR_TC_1 +8);
-
-		dev_turbochannel_init(machine, mem, 2,
-		    KN03_PHYS_TC_2_START, KN03_PHYS_TC_2_END,
-		    machine->n_gfx_cards >= 3?
-			turbochannel_default_gfx_card : "",
-		    KN03_INTR_TC_2 +8);
-#endif
-
-		/*  TODO: interrupts  */
-		/*  shared (turbochannel) interrupts are +8  */
-
-		framebuffer_console_name = "osconsole=0,3";	/* fb,keyb(?) */
-		serial_console_name      = "osconsole=3";	/* ? */
-		break;
-
-	case MACHINE_DEC_5800:		/*  type 5, KN5800  */
-		machine->machine_name = strdup("DECsystem 5800");
-
-		/*  TODO: this is incorrect, banks multiply by 8 etc  */
-		if (machine->physical_ram_in_mb < 48)
-			fprintf(stderr, "WARNING! 5800 will probably not run "
-			    "with less than 48MB RAM. Continuing anyway.\n");
-
-		/*
-		 *  According to
-		 *  http://www2.no.netbsd.org/ports/pmax/models.html,
-		 *  the 5800-series is based on VAX 6000/300.
-		 */
-
-		/*
-		 *  Ultrix might support SMP on this machine type.
-		 *
-		 *  Something at 0x10000000.
-		 *  ssc serial console at 0x10140000, interrupt 2 (shared
-		 *  with XMI?).
-		 *  xmi 0 at address 0x11800000   (node x at offset x*0x80000)
-		 *  Clock uses interrupt 3 (shared with XMI?).
-		 */
-
-		device_add(machine, "dec5800 addr=0x10000000");
-		device_add(machine, "decbi addr=0x10000000");
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].dec5800.28",
-		    machine->path, machine->bootstrap_cpu);
-		dev_ssc_init(machine, mem, 0x10140000,
-		    tmpstr, machine->x11_md.in_use);
-
-		dev_decxmi_init(mem, 0x11800000);
-		dev_deccca_init(mem, DEC_DECCCA_BASEADDR);
-
-		break;
-
-	case MACHINE_DEC_5400:		/*  type 6, KN210  */
-		machine->machine_name = strdup("DECsystem 5400 (KN210)");
-		/*
-		 *  Misc. info from the KN210 manual:
-		 *
-		 *  Interrupt lines:
-		 *	irq5	fpu
-		 *	irq4	halt
-		 *	irq3	pwrfl -> mer1 -> mer0 -> wear
-		 *	irq2	100 Hz -> birq7
-		 *	irq1	dssi -> ni -> birq6
-		 *	irq0	birq5 -> console -> timers -> birq4
-		 *
-		 *  Interrupt status register at 0x10048000.
-		 *  Main memory error status register at 0x1008140.
-		 *  Interval Timer Register (ITR) at 0x10084010.
-		 *  Q22 stuff at 0x10088000 - 0x1008ffff.
-		 *  TODR at 0x1014006c.
-		 *  TCR0 (timer control register 0) 0x10140100.
-		 *  TIR0 (timer interval register 0) 0x10140104.
-		 *  TCR1 (timer control register 1) 0x10140110.
-		 *  TIR1 (timer interval register 1) 0x10140114.
-		 *  VRR0 (Vector Read Register 0) at 0x16000050.
-		 *  VRR1 (Vector Read Register 1) at 0x16000054.
-		 *  VRR2 (Vector Read Register 2) at 0x16000058.
-		 *  VRR3 (Vector Read Register 3) at 0x1600005c.
-		 */
-		/*  ln (ethernet) at 0x10084x00 ? and 0x10120000 ?  */
-		/*  error registers (?) at 0x17000000 and 0x10080000  */
-		/*  device_add(machine, "kn210 addr=0x10080000");  */
-		dev_ssc_init(machine, mem, 0x10140000, "irq? TODO",
-		    machine->x11_md.in_use);
-		break;
-
-	case MACHINE_DEC_MAXINE_5000:	/*  type 7, KN02CA  */
-		machine->machine_name = strdup("Personal DECstation 5000/xxx "
-		    "(MAXINE) (KN02CA)");
-		if (machine->emulated_hz == 0)
-			machine->emulated_hz = 33000000;
-
-		if (machine->physical_ram_in_mb < 8)
-			fprintf(stderr, "WARNING! Real KN02CA machines do not "
-			    "have less than 8MB RAM. Continuing anyway.\n");
-		if (machine->physical_ram_in_mb > 40)
-			fprintf(stderr, "WARNING! Real KN02CA machines cannot "
-			    "have more than 40MB RAM. Continuing anyway.\n");
-
-		/*  Maxine interrupts:  */
-fatal("TODO: Legacy rewrite\n");
-abort();
-
-//		machine->md_interrupt = maxine_interrupt;
-
-		/*
-		 *  Something at address 0xca00000. (?)
-		 *  Something at address 0xe000000. (?)
-		 *  tc0 slot 0					(0x10000000)
-		 *  tc0 slot 1					(0x14000000)
-		 *  (tc0 slot 2 used by the framebuffer)
-		 *  ioasic0 at tc0 slot 3 offset 0x0		(0x1c000000)
-		 *  le0 at ioasic0 offset 0xc0000: address 00:00:00:00:00:00
-		 *						(0x1c0c0000)
-		 *  scc0 at ioasic0 offset 0x100000: console  <-- serial
-		 *						(0x1c100000)
-		 *  mcclock0 at ioasic0 offset 0x200000: mc146818 (0x1c200000)
-		 *  isdn at ioasic0 offset 0x240000 not configured (0x1c240000)
-		 *  bba0 at ioasic0 offset 0x240000 (audio0 at bba0)
-		 *	^--- which one of isdn and bba0?
-		 *  dtop0 at ioasic0 offset 0x280000		(0x1c280000)
-		 *  fdc at ioasic0 offset 0x2c0000 not configured
-		 *	^-- floppy				(0x1c2c0000)
-		 *  asc0 at ioasic0 offset 0x300000: NCR53C94, 25MHz, SCSI
-		 *	ID 7					(0x1c300000)
-		 *  xcfb0 at tc0 slot 2 offset 0x0: 1024x768x8
-		 *	built-in framebuffer			(0xa000000)
-		 */
-fatal("TODO: dec_ioasic legacy rewrite\n");
-abort();
-//		machine->md_int.dec_ioasic_data =
-//		    dev_dec_ioasic_init(cpu, mem, 0x1c000000, 0);
-
-fatal("TODO: turbochannel rewrite!\n");
-abort();
-#if 0
-		/*  TURBOchannel slots (0 and 1):  */
-		dev_turbochannel_init(machine, mem, 0,
-		    0x10000000, 0x103fffff,
-		    machine->n_gfx_cards >= 2?
-			turbochannel_default_gfx_card : "",
-		    XINE_INTR_TC_0 +8);
-		dev_turbochannel_init(machine, mem, 1,
-		    0x14000000, 0x143fffff,
-		    machine->n_gfx_cards >= 3?
-			turbochannel_default_gfx_card : "",
-		    XINE_INTR_TC_1 +8);
-
-		/*
-		 *  TURBOchannel slot 2 is hardwired to be used by
-		 *  the framebuffer: (NOTE: 0x8000000, not 0x18000000)
-		 */
-		dev_turbochannel_init(machine, mem, 2,
-		    0x8000000, 0xbffffff, "PMAG-DV", 0);
-#endif
-		/*
-		 *  TURBOchannel slot 3: fixed, ioasic
-		 *  (the system stuff), 0x1c000000
-		 */
-fatal("TODO: xine dev_le_init rewrite\n");
-abort();
-//		dev_le_init(machine, mem, 0x1c0c0000, 0, 0,
-//		    XINE_INTR_LANCE +8, 4*65536);
-//		dev_scc_init(machine, mem, 0x1c100000,
-//		    XINE_INTR_SCC_0 +8, machine->x11_md.in_use, 0, 1);
-fatal("TODO: mc146818 irq\n");
-abort();
-//		dev_mc146818_init(machine, mem, 0x1c200000,
-//		    XINE_INT_TOY, MC146818_DEC, 1);
-fatal("TODO: xine asc init rewrite\n");
-abort();
-//		dev_asc_init(machine, mem, 0x1c300000,
-//		    XINE_INTR_SCSI +8, NULL, DEV_ASC_DEC, NULL, NULL);
-
-		framebuffer_console_name = "osconsole=3,2";	/*  keyb,fb?  */
-		serial_console_name      = "osconsole=3";
-		break;
-
-	case MACHINE_DEC_5500:	/*  type 11, KN220  */
-		machine->machine_name = strdup("DECsystem 5500 (KN220)");
-
-		/*
-		 *  According to NetBSD's pmax ports page:
-		 *  KN220-AA is a "30 MHz R3000 CPU with R3010 FPU"
-		 *  with "512 kBytes of Prestoserve battery backed RAM."
-		 */
-		if (machine->emulated_hz == 0)
-			machine->emulated_hz = 30000000;
-
-		/*
-		 *  See KN220 docs for more info.
-		 *
-		 *  something at 0x10000000
-		 *  something at 0x10001000
-		 *  something at 0x10040000
-		 *  scc at 0x10140000
-		 *  qbus at (or around) 0x10080000
-		 *  dssi (disk controller) buffers at 0x10100000,
-		 *	registers at 0x10160000.
-		 *  sgec (ethernet) registers at 0x10008000, station
-		 *	addresss at 0x10120000.
-		 *  asc (scsi) at 0x17100000.
-		 */
-
-		dev_ssc_init(machine, mem, 0x10140000, "TODO: irq",
-		    machine->x11_md.in_use);
-
-		/*  something at 0x17000000, ultrix says "cpu 0 panic: "
-		    "DS5500 I/O Board is missing" if this is not here  */
-		dev_dec5500_ioboard_init(cpu, mem, 0x17000000);
-
-		dev_sgec_init(mem, 0x10008000, 0);		/*  irq?  */
-
-		/*  The asc controller might be TURBOchannel-ish?  */
-#if 0
-		dev_turbochannel_init(machine, mem, 0, 0x17100000,
-		    0x171fffff, "PMAZ-AA", 0);	/*  irq?  */
-#else
-		dev_asc_init(machine, mem, 0x17100000, 0, NULL,
-		    DEV_ASC_DEC, NULL, NULL);		/*  irq?  */
-#endif
-
-		framebuffer_console_name = "osconsole=0,0";	/*  TODO (?)  */
-		serial_console_name      = "osconsole=0";
-		break;
-
-	case MACHINE_DEC_MIPSMATE_5100:	/*  type 12  */
-		machine->machine_name = strdup("DEC MIPSMATE 5100 (KN230)");
-
-		if (machine->emulated_hz == 0)
-			machine->emulated_hz = 20000000;
-
-		if (machine->physical_ram_in_mb > 128)
-			fprintf(stderr, "WARNING! Real MIPSMATE 5100 machines "
-			    "cannot have more than 128MB RAM. Continuing"
-			    " anyway.\n");
-
-		if (machine->x11_md.in_use)
-			fprintf(stderr, "WARNING! Real MIPSMATE 5100 machines "
-			    "cannot have a graphical framebuffer. "
-			    "Continuing anyway.\n");
-
-		/*  KN230 mainbus / interrupt controller:  */
-		snprintf(tmpstr, sizeof(tmpstr),
-		    "kn230 addr=0x%" PRIx64, (uint64_t) KN230_SYS_ICSR);
-		device_add(machine, tmpstr);
-
-		/*
-		 *  According to NetBSD/pmax:
-		 *  dc0 at ibus0 addr 0x1c000000
-		 *  le0 at ibus0 addr 0x18000000: address 00:00:00:00:00:00
-		 *  sii0 at ibus0 addr 0x1a000000
-		 */
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%i",
-		    machine->path, machine->bootstrap_cpu, 4);
-		dev_mc146818_init(machine, mem, KN230_SYS_CLOCK, tmpstr,
-		    MC146818_DEC, 1);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].kn230.0x%x",
-		    machine->path, machine->bootstrap_cpu, KN230_CSR_INTR_DZ0);
-		dev_dc7085_init(machine, mem, KN230_SYS_DZ0,
-		    tmpstr, machine->x11_md.in_use);
-
-		/* dev_dc7085_init(machine, mem, KN230_SYS_DZ1,
-		    KN230_CSR_INTR_OPT0, machine->x11_md.in_use);  */
-		/* dev_dc7085_init(machine, mem, KN230_SYS_DZ2,
-		    KN230_CSR_INTR_OPT1, machine->x11_md.in_use);  */
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].kn230.0x%x",
-		    machine->path, machine->bootstrap_cpu,
-		    KN230_CSR_INTR_LANCE);
-		dev_le_init(machine, mem, KN230_SYS_LANCE,
-		    KN230_SYS_LANCE_B_START, KN230_SYS_LANCE_B_END,
-		    tmpstr, 4*1048576);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].kn230.0x%x",
-		    machine->path, machine->bootstrap_cpu, KN230_CSR_INTR_SII);
-		dev_sii_init(machine, mem, KN230_SYS_SII,
-		    KN230_SYS_SII_B_START, KN230_SYS_SII_B_END, tmpstr);
-
-		serial_console_name = "osconsole=0";
-		break;
-
-	default:fatal("Unknown DEC machine type: %i\n",
-		    machine->machine_subtype);
-		exit(1);
-	}
-
-	/*
-	 *  Most OSes on DECstation use physical addresses below
-	 *  0x20000000, but both OSF/1 and Sprite use 0xbe...... as if
-	 *  it was 0x1e......, so we need this hack:
-	 */
-	dev_ram_init(machine, 0xa0000000, 0x20000000,
-	    DEV_RAM_MIRROR | DEV_RAM_MIGHT_POINT_TO_DEVICES, 0x0);
-
-	if (!machine->prom_emulation)
-		return;
-
-
-	/*  DECstation PROM stuff:  (TODO: endianness)  */
-	for (i=0; i<150; i++)
-		store_32bit_word(cpu, DEC_PROM_CALLBACK_STRUCT + i*4,
-		    DEC_PROM_EMULATION + i*8);
-
-	/*  Fill PROM with special "magic trap" instructions:  */
-	for (i=0; i<150; i++) {
-		store_32bit_word(cpu, DEC_PROM_EMULATION + i*8,
-		    0x00c0de0c);	/*  trap instruction  */
-		store_32bit_word(cpu, DEC_PROM_EMULATION + i*8 + 4,
-		    0x00000000);	/*  nop  */
-	}
-
-	/*  Jumptable at beginning of PROM:  also "magic trap" instructions:  */
-	for (i=0; i<0x180; i+=8) {
-		store_32bit_word(cpu, 0xbfc00000 + i,
-		    0x00c0de0c);	/*  trap instruction  */
-		store_32bit_word(cpu, 0xbfc00000 + i + 4,
-		    0x00000000);	/*  nop  */
-	}
-
-
-	/*
-	 *  According to dec_prom.h from NetBSD:
-	 *
-	 *  "Programs loaded by the new PROMs pass the following arguments:
-	 *	a0	argc
-	 *	a1	argv
-	 *	a2	DEC_PROM_MAGIC
-	 *	a3	The callback vector defined below"
-	 *
-	 *  So we try to emulate a PROM, even though no such thing has been
-	 *  loaded.
-	 */
-
-	cpu->cd.mips.gpr[MIPS_GPR_A0] = 3;
-	cpu->cd.mips.gpr[MIPS_GPR_A1] = DEC_PROM_INITIAL_ARGV;
-	cpu->cd.mips.gpr[MIPS_GPR_A2] = DEC_PROM_MAGIC;
-	cpu->cd.mips.gpr[MIPS_GPR_A3] = DEC_PROM_CALLBACK_STRUCT;
-
-	store_32bit_word(cpu, INITIAL_STACK_POINTER + 0x10, BOOTINFO_MAGIC);
-	store_32bit_word(cpu, INITIAL_STACK_POINTER + 0x14, BOOTINFO_ADDR);
-
-	store_32bit_word(cpu, DEC_PROM_INITIAL_ARGV,
-	    (DEC_PROM_INITIAL_ARGV + 0x10));
-	store_32bit_word(cpu, DEC_PROM_INITIAL_ARGV+4,
-	    (DEC_PROM_INITIAL_ARGV + 0x70));
-	store_32bit_word(cpu, DEC_PROM_INITIAL_ARGV+8,
-	    (DEC_PROM_INITIAL_ARGV + 0xe0));
-	store_32bit_word(cpu, DEC_PROM_INITIAL_ARGV+12, 0);
-
-	/*
-	 *  NetBSD and Ultrix expect the boot args to be like this:
-	 *
-	 *	"boot" "bootdev" [args?]
-	 *
-	 *  where bootdev is supposed to be "rz(0,0,0)netbsd" for
-	 *  3100/2100 (although that crashes Ultrix :-/), and
-	 *  "5/rz0a/netbsd" for all others.  The number '5' is the
-	 *  slot number of the boot device.
-	 *
-	 *  'rz' for disks, 'tz' for tapes.
-	 */
-	{
-#if 0
-		if (machine->machine_subtype == MACHINE_DEC_PMAX_3100)
-			strlcpy(bootpath, "rz(0,0,0)", sizeof(bootpath));
-		else
-#endif
-			strlcpy(bootpath, "X/rzY/", sizeof(bootpath));
-
-		if (machine->bootdev_id < 0 || machine->force_netboot) {
-			/*  tftp boot:  */
-			strlcpy(bootpath, "5/tftp/", sizeof(bootpath));
-			bootpath[0] = '0' + boot_net_boardnumber;
-		} else {
-			/*  disk boot:  */
-			bootpath[0] = '0' + boot_scsi_boardnumber;
-			if (diskimage_is_a_tape(machine, machine->bootdev_id,
-			    machine->bootdev_type))
-				bootpath[2] = 't';
-			bootpath[4] = '0' + machine->bootdev_id;
-		}
-
-		init_bootpath = bootpath;
-	}
-
-	CHECK_ALLOCATION(machine->bootarg = (char *) malloc(BOOTARG_BUFLEN));
-	strlcpy(machine->bootarg, init_bootpath, BOOTARG_BUFLEN);
-	if (strlcat(machine->bootarg, machine->boot_kernel_filename,
-	    BOOTARG_BUFLEN) > BOOTARG_BUFLEN) {
-		fprintf(stderr, "bootarg truncated?\n");
-		exit(1);
-	}
-
-	machine->bootstr = strdup("boot");
-
-	store_string(cpu, DEC_PROM_INITIAL_ARGV+0x10, machine->bootstr);
-	store_string(cpu, DEC_PROM_INITIAL_ARGV+0x70, machine->bootarg);
-	store_string(cpu, DEC_PROM_INITIAL_ARGV+0xe0,
-	    machine->boot_string_argument);
-
-	/*  Decrease the nr of args, if there are no args :-)  */
-	if (machine->boot_string_argument == NULL ||
-	    machine->boot_string_argument[0] == '\0')
-		cpu->cd.mips.gpr[MIPS_GPR_A0] --;
-
-	if (machine->boot_string_argument[0] != '\0') {
-		strlcat(machine->bootarg, " ", BOOTARG_BUFLEN);
-		if (strlcat(machine->bootarg, machine->boot_string_argument,
-		    BOOTARG_BUFLEN) >= BOOTARG_BUFLEN) {
-			fprintf(stderr, "bootstr truncated?\n");
-			exit(1);
-		}
-	}
-
-	xx.a.common.next = (char *)&xx.b - (char *)&xx;
-	xx.a.common.type = BTINFO_MAGIC;
-	xx.a.magic = BOOTINFO_MAGIC;
-
-	xx.b.common.next = (char *)&xx.c - (char *)&xx.b;
-	xx.b.common.type = BTINFO_BOOTPATH;
-	strlcpy(xx.b.bootpath, machine->bootstr, sizeof(xx.b.bootpath));
-
-	xx.c.common.next = 0;
-	xx.c.common.type = BTINFO_SYMTAB;
-	xx.c.nsym = 0;
-	xx.c.ssym = 0;
-	xx.c.esym = machine->file_loaded_end_addr;
-
-	store_buf(cpu, BOOTINFO_ADDR, (char *)&xx, sizeof(xx));
-
-	CHECK_ALLOCATION(machine->md.pmax = (struct machine_pmax *)
-	    malloc(sizeof(struct machine_pmax)));
-	memset(machine->md.pmax, 0, sizeof(struct machine_pmax));
-
-	/*  The system's memmap:  */
-	CHECK_ALLOCATION(machine->md.pmax->memmap = (struct dec_memmap *)
-	    malloc(sizeof(struct dec_memmap)));
-	store_32bit_word_in_host(cpu,
-	    (unsigned char *)&machine->md.pmax->memmap->pagesize, 4096);
-
-	for (unsigned int j=0; j<sizeof(machine->md.pmax->memmap->bitmap); j++)
-		machine->md.pmax->memmap->bitmap[j] = (j * 4096*8 <
-		    1048576*machine->physical_ram_in_mb)? 0xff : 0x00;
-
-	store_buf(cpu, DEC_MEMMAP_ADDR,
-	    (char *)machine->md.pmax->memmap, sizeof(struct dec_memmap));
-
-	/*  Environment variables:  */
-	addr = DEC_PROM_STRINGS;
-
-	if (machine->x11_md.in_use && machine->n_gfx_cards > 0)
-		/*  (0,3)  Keyboard and Framebuffer  */
-		add_environment_string(cpu, framebuffer_console_name, &addr);
-	else
-		/*  Serial console  */
-		add_environment_string(cpu, serial_console_name, &addr);
-
-	/*
-	 *  The KN5800 (SMP system) uses a CCA (console communications
-	 *  area):  (See VAX 6000 documentation for details.)
-	 */
-	{
-		char tmps[300];
-		snprintf(tmps, sizeof(tmps), "cca=%" PRIx32,
-		    (uint32_t) (DEC_DECCCA_BASEADDR + 0xa0000000ULL));
-		add_environment_string(cpu, tmps, &addr);
-	}
-
-	/*  These are needed for Sprite to boot:  */
-	{
-		char tmps[500];
-
-		snprintf(tmps, sizeof(tmps), "boot=%s", machine->bootarg);
-		tmps[sizeof(tmps)-1] = '\0';
-		add_environment_string(cpu, tmps, &addr);
-
-		snprintf(tmps, sizeof(tmps), "bitmap=0x%" PRIx32, (uint32_t)
-		    ( (DEC_MEMMAP_ADDR + sizeof(uint32_t) /* skip the
-			page size and point to the memmap */
-		    ) & 0xffffffffULL) );
-		tmps[sizeof(tmps)-1] = '\0';
-		add_environment_string(cpu, tmps, &addr);
-
-		snprintf(tmps, sizeof(tmps), "bitmaplen=0x%" PRIx32, (uint32_t)
-		    ( machine->physical_ram_in_mb * 1048576 / 4096 / 8) );
-		tmps[sizeof(tmps)-1] = '\0';
-		add_environment_string(cpu, tmps, &addr);
-	}
-
-	add_environment_string(cpu, "scsiid0=7", &addr);
-	add_environment_string(cpu, "bootmode=a", &addr);
-	add_environment_string(cpu, "testaction=q", &addr);
-	add_environment_string(cpu, "haltaction=h", &addr);
-	add_environment_string(cpu, "more=24", &addr);
-
-	/*  Used in at least Ultrix on the 5100:  */
-	add_environment_string(cpu, "scsiid=7", &addr);
-	add_environment_string(cpu, "baud0=9600", &addr);
-	add_environment_string(cpu, "baud1=9600", &addr);
-	add_environment_string(cpu, "baud2=9600", &addr);
-	add_environment_string(cpu, "baud3=9600", &addr);
-	add_environment_string(cpu, "iooption=0x1", &addr);
-
-	/*  The end:  */
-	add_environment_string(cpu, "", &addr);
-}
-
-
-MACHINE_DEFAULT_CPU(pmax)
-{
-	if (machine->machine_subtype > 2)
-		CHECK_ALLOCATION(machine->cpu_name = strdup("R3000A"));
-
-	if (machine->machine_subtype > 1 && machine->cpu_name == NULL)
-		CHECK_ALLOCATION(machine->cpu_name = strdup("R3000"));
-
-	if (machine->cpu_name == NULL)
-		CHECK_ALLOCATION(machine->cpu_name = strdup("R2000"));
-}
-
-
-MACHINE_DEFAULT_RAM(pmax)
-{
-	switch (machine->machine_subtype) {
-	case MACHINE_DEC_PMAX_3100:
-		machine->physical_ram_in_mb = 24;
-		break;
-	case MACHINE_DEC_3MAX_5000:
-		machine->physical_ram_in_mb = 64;
-		break;
-	default:machine->physical_ram_in_mb = 32;
-	}
-}
-
-
-MACHINE_REGISTER(pmax)
-{
-	MR_DEFAULT(pmax, "DECstation/DECsystem", ARCH_MIPS, MACHINE_PMAX);
-
-	machine_entry_add_alias(me, "decstation");
-	machine_entry_add_alias(me, "decsystem");
-	machine_entry_add_alias(me, "dec");
-
-	machine_entry_add_subtype(me, "DECstation 3100 (PMAX)",
-	    MACHINE_DEC_PMAX_3100, "pmax", "3100", "2100", NULL);
-
-	machine_entry_add_subtype(me, "DECstation 5000/200 (3MAX)",
-	    MACHINE_DEC_3MAX_5000, "3max", "5000/200", NULL);
-
-	machine_entry_add_subtype(me, "DECstation 5000/1xx (3MIN)",
-	    MACHINE_DEC_3MIN_5000, "3min", "5000/1xx", NULL);
-
-	machine_entry_add_subtype(me, "DECstation 5000 (3MAXPLUS)",
-	    MACHINE_DEC_3MAXPLUS_5000, "3maxplus", "3max+", NULL);
-
-	machine_entry_add_subtype(me, "DECsystem 58x0",
-	    MACHINE_DEC_5800, "5800", "58x0", NULL);
-
-	machine_entry_add_subtype(me, "DECsystem 5400",
-	    MACHINE_DEC_5400, "5400", NULL);
-
-	machine_entry_add_subtype(me, "DECstation Maxine (5000)",
-	    MACHINE_DEC_MAXINE_5000, "maxine", NULL);
-
-	machine_entry_add_subtype(me, "DECsystem 5500",
-	    MACHINE_DEC_5500, "5500", NULL);
-
-	machine_entry_add_subtype(me, "DECstation MipsMate (5100)",
-	    MACHINE_DEC_MIPSMATE_5100, "5100", "mipsmate", NULL);
-
-	me->set_default_ram = machine_default_ram_pmax;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_pmppc.c gxemul-0.7.0+dfsg/src/machines/machine_pmppc.c
--- gxemul-0.6.2/src/machines/machine_pmppc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_pmppc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,88 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Artesyn's PM/PPC board
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+
+MACHINE_SETUP(pmppc)
+{
+	struct pci_data *pci_data;
+	char tmpstr[300];
+
+	/*
+	 *  NetBSD/pmppc (http://www.netbsd.org/ports/pmppc/)
+	 */
+	machine->machine_name = strdup("Artesyn's PM/PPC board");
+
+	/*  Bogus default speed = 33 MHz  */
+	if (machine->emulated_hz == 0)
+		machine->emulated_hz = 33000000;
+
+	/*  PM/PPC specific motherboard registers:  */
+	device_add(machine, "pmppc");
+
+	/*  PCI and Interrupt controller:  */
+	pci_data = (struct pci_data *) device_add(machine, "cpc700");
+
+	/*  RTC at "ext int 5" = "int 25" in IBM jargon, int
+	    31-25 = 6 for the rest of us.  */
+	snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].cpc700.%i",
+	    machine->path, machine->bootstrap_cpu, 31-25);
+	dev_mc146818_init(machine, machine->memory, 0x7ff00000, tmpstr,
+	    MC146818_PMPPC, 1);
+
+	bus_pci_add(machine, pci_data, machine->memory, 0, 8, 0, "dec21143");
+}
+
+
+MACHINE_DEFAULT_CPU(pmppc)
+{
+	machine->cpu_name = strdup("PPC750");
+}
+
+
+MACHINE_REGISTER(pmppc)
+{
+	MR_DEFAULT(pmppc, "Artesyn's PM/PPC board", MACHINE_PMPPC);
+
+	machine_entry_add_alias(me, "pmppc");
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_pmppc.cc gxemul-0.7.0+dfsg/src/machines/machine_pmppc.cc
--- gxemul-0.6.2/src/machines/machine_pmppc.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_pmppc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,88 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Artesyn's PM/PPC board
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-
-MACHINE_SETUP(pmppc)
-{
-	struct pci_data *pci_data;
-	char tmpstr[300];
-
-	/*
-	 *  NetBSD/pmppc (http://www.netbsd.org/ports/pmppc/)
-	 */
-	machine->machine_name = strdup("Artesyn's PM/PPC board");
-
-	/*  Bogus default speed = 33 MHz  */
-	if (machine->emulated_hz == 0)
-		machine->emulated_hz = 33000000;
-
-	/*  PM/PPC specific motherboard registers:  */
-	device_add(machine, "pmppc");
-
-	/*  PCI and Interrupt controller:  */
-	pci_data = (struct pci_data *) device_add(machine, "cpc700");
-
-	/*  RTC at "ext int 5" = "int 25" in IBM jargon, int
-	    31-25 = 6 for the rest of us.  */
-	snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].cpc700.%i",
-	    machine->path, machine->bootstrap_cpu, 31-25);
-	dev_mc146818_init(machine, machine->memory, 0x7ff00000, tmpstr,
-	    MC146818_PMPPC, 1);
-
-	bus_pci_add(machine, pci_data, machine->memory, 0, 8, 0, "dec21143");
-}
-
-
-MACHINE_DEFAULT_CPU(pmppc)
-{
-	machine->cpu_name = strdup("PPC750");
-}
-
-
-MACHINE_REGISTER(pmppc)
-{
-	MR_DEFAULT(pmppc, "Artesyn's PM/PPC board", ARCH_PPC, MACHINE_PMPPC);
-
-	machine_entry_add_alias(me, "pmppc");
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_prep.c gxemul-0.7.0+dfsg/src/machines/machine_prep.c
--- gxemul-0.6.2/src/machines/machine_prep.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_prep.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,190 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Machines conforming to the PowerPC Reference Platform specs
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "bus_isa.h"
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+
+MACHINE_SETUP(prep)
+{
+	char tmpstr[300];
+
+	struct pci_data *pci_data;
+	const char *model_name = "";
+
+	switch (machine->machine_subtype) {
+
+	case MACHINE_PREP_IBM6050:
+		machine->machine_name =
+		    strdup("PowerPC Reference Platform, IBM 6050/6070");
+		model_name = "IBM PPS Model 6050/6070 (E)";
+
+		if (machine->emulated_hz == 0)
+			machine->emulated_hz = 20000000;
+
+		snprintf(tmpstr, sizeof(tmpstr), "prep irq=%s.cpu[%i]",
+		    machine->path, machine->bootstrap_cpu);
+		device_add(machine, tmpstr);
+
+		snprintf(tmpstr, sizeof(tmpstr), "eagle irq=%s.cpu[%i]",
+		    machine->path, machine->bootstrap_cpu);
+		pci_data = (struct pci_data *) device_add(machine, tmpstr);
+
+		bus_pci_add(machine, pci_data, machine->memory,
+		    0, 13, 0, "dec21143");
+
+		if (machine->x11_md.in_use) {
+			bus_pci_add(machine, pci_data, machine->memory,
+			    0, 14, 0, "s3_virge");
+		}
+		break;
+
+	case MACHINE_PREP_MVME2400:
+		machine->machine_name = strdup("PowerPC Reference Platform, MVME2400");
+
+		/*  TODO: _EXACT_ model name for mvme2400?  */
+		model_name = "MOT MVME2400";
+
+		snprintf(tmpstr, sizeof(tmpstr), "prep irq=%s.cpu[%i]",
+		    machine->path, machine->bootstrap_cpu);
+		device_add(machine, tmpstr);
+
+		snprintf(tmpstr, sizeof(tmpstr), "eagle irq=%s.cpu[%i]",
+		    machine->path, machine->bootstrap_cpu);
+		pci_data = (struct pci_data *) device_add(machine, tmpstr);
+
+		break;
+
+	default:fatal("Unimplemented PReP machine subtype %i\n",
+		    machine->machine_subtype);
+		exit(1);
+	}
+
+	if (!machine->prom_emulation)
+		return;
+
+
+	/*  Linux on PReP has 0xdeadc0de at address 0? (See
+	    http://joshua.raleigh.nc.us/docs/linux-2.4.10_html/
+	    113568.html)  */
+	store_32bit_word(cpu, 0, 0xdeadc0de);
+
+	/*
+	 *  r4 should point to first free byte after the loaded kernel.
+	 *  r6 should point to bootinfo.
+	 */
+	cpu->cd.ppc.gpr[4] = 6 * 1048576;
+	cpu->cd.ppc.gpr[6] = machine->physical_ram_in_mb*1048576-0x8000;
+
+	/*
+	 *  (See NetBSD's prep/include/bootinfo.h for details.)
+	 *
+	 *  32-bit "next" offset;
+	 *  32-bit "type";
+	 *  type-specific data...
+	 */
+
+	/*  type: clock  */
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+ 0, 12);
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+ 4, 2);
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+ 8, machine->emulated_hz);
+
+	/*  type: console  */
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+12, 20);
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+16, 1);
+	store_buf(cpu, cpu->cd.ppc.gpr[6]+20,
+	    machine->x11_md.in_use? "vga":"com", 4);
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+24, 0x3f8);/*  addr  */
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+28, 9600);/*  speed  */
+
+	/*  type: residual  */
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+32, 0);
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+36, 0);
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+40,/*  addr of data  */
+	    cpu->cd.ppc.gpr[6] + 0x100);
+
+	/*  Residual data:  (TODO)  */
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+0x100, 0x200);
+	store_string(cpu, cpu->cd.ppc.gpr[6]+0x100+0x8, model_name);
+	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+0x100+0x1f8,
+	    machine->physical_ram_in_mb * 1048576);  /*  memsize  */
+}
+
+
+MACHINE_DEFAULT_CPU(prep)
+{
+	switch (machine->machine_subtype) {
+
+	case MACHINE_PREP_IBM6050:
+		machine->cpu_name = strdup("PPC604");
+		break;
+
+	case MACHINE_PREP_MVME2400:
+		machine->cpu_name = strdup("PPC750");
+		break;
+
+	default:fatal("Unimplemented PReP machine subtype %i\n",
+		    machine->machine_subtype);
+		exit(1);
+	}
+}
+
+
+MACHINE_DEFAULT_RAM(prep)
+{
+	machine->physical_ram_in_mb = 64;
+}
+
+
+MACHINE_REGISTER(prep)
+{
+	MR_DEFAULT(prep, "PowerPC Reference Platform", MACHINE_PREP);
+
+	machine_entry_add_alias(me, "prep");
+	me->set_default_ram = machine_default_ram_prep;
+
+	machine_entry_add_subtype(me, "IBM 6050/6070", MACHINE_PREP_IBM6050,
+	    "ibm6050", "ibm6070", NULL);
+
+	machine_entry_add_subtype(me, "MVME2400", MACHINE_PREP_MVME2400,
+	    "mvme2400", NULL);
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_prep.cc gxemul-0.7.0+dfsg/src/machines/machine_prep.cc
--- gxemul-0.6.2/src/machines/machine_prep.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_prep.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,190 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Machines conforming to the PowerPC Reference Platform specs
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "bus_isa.h"
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-
-MACHINE_SETUP(prep)
-{
-	char tmpstr[300];
-
-	struct pci_data *pci_data;
-	const char *model_name = "";
-
-	switch (machine->machine_subtype) {
-
-	case MACHINE_PREP_IBM6050:
-		machine->machine_name =
-		    strdup("PowerPC Reference Platform, IBM 6050/6070");
-		model_name = "IBM PPS Model 6050/6070 (E)";
-
-		if (machine->emulated_hz == 0)
-			machine->emulated_hz = 20000000;
-
-		snprintf(tmpstr, sizeof(tmpstr), "prep irq=%s.cpu[%i]",
-		    machine->path, machine->bootstrap_cpu);
-		device_add(machine, tmpstr);
-
-		snprintf(tmpstr, sizeof(tmpstr), "eagle irq=%s.cpu[%i]",
-		    machine->path, machine->bootstrap_cpu);
-		pci_data = (struct pci_data *) device_add(machine, tmpstr);
-
-		bus_pci_add(machine, pci_data, machine->memory,
-		    0, 13, 0, "dec21143");
-
-		if (machine->x11_md.in_use) {
-			bus_pci_add(machine, pci_data, machine->memory,
-			    0, 14, 0, "s3_virge");
-		}
-		break;
-
-	case MACHINE_PREP_MVME2400:
-		machine->machine_name = strdup("PowerPC Reference Platform, MVME2400");
-
-		/*  TODO: _EXACT_ model name for mvme2400?  */
-		model_name = "MOT MVME2400";
-
-		snprintf(tmpstr, sizeof(tmpstr), "prep irq=%s.cpu[%i]",
-		    machine->path, machine->bootstrap_cpu);
-		device_add(machine, tmpstr);
-
-		snprintf(tmpstr, sizeof(tmpstr), "eagle irq=%s.cpu[%i]",
-		    machine->path, machine->bootstrap_cpu);
-		pci_data = (struct pci_data *) device_add(machine, tmpstr);
-
-		break;
-
-	default:fatal("Unimplemented PReP machine subtype %i\n",
-		    machine->machine_subtype);
-		exit(1);
-	}
-
-	if (!machine->prom_emulation)
-		return;
-
-
-	/*  Linux on PReP has 0xdeadc0de at address 0? (See
-	    http://joshua.raleigh.nc.us/docs/linux-2.4.10_html/
-	    113568.html)  */
-	store_32bit_word(cpu, 0, 0xdeadc0de);
-
-	/*
-	 *  r4 should point to first free byte after the loaded kernel.
-	 *  r6 should point to bootinfo.
-	 */
-	cpu->cd.ppc.gpr[4] = 6 * 1048576;
-	cpu->cd.ppc.gpr[6] = machine->physical_ram_in_mb*1048576-0x8000;
-
-	/*
-	 *  (See NetBSD's prep/include/bootinfo.h for details.)
-	 *
-	 *  32-bit "next" offset;
-	 *  32-bit "type";
-	 *  type-specific data...
-	 */
-
-	/*  type: clock  */
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+ 0, 12);
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+ 4, 2);
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+ 8, machine->emulated_hz);
-
-	/*  type: console  */
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+12, 20);
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+16, 1);
-	store_buf(cpu, cpu->cd.ppc.gpr[6]+20,
-	    machine->x11_md.in_use? "vga":"com", 4);
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+24, 0x3f8);/*  addr  */
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+28, 9600);/*  speed  */
-
-	/*  type: residual  */
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+32, 0);
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+36, 0);
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+40,/*  addr of data  */
-	    cpu->cd.ppc.gpr[6] + 0x100);
-
-	/*  Residual data:  (TODO)  */
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+0x100, 0x200);
-	store_string(cpu, cpu->cd.ppc.gpr[6]+0x100+0x8, model_name);
-	store_32bit_word(cpu, cpu->cd.ppc.gpr[6]+0x100+0x1f8,
-	    machine->physical_ram_in_mb * 1048576);  /*  memsize  */
-}
-
-
-MACHINE_DEFAULT_CPU(prep)
-{
-	switch (machine->machine_subtype) {
-
-	case MACHINE_PREP_IBM6050:
-		machine->cpu_name = strdup("PPC604");
-		break;
-
-	case MACHINE_PREP_MVME2400:
-		machine->cpu_name = strdup("PPC750");
-		break;
-
-	default:fatal("Unimplemented PReP machine subtype %i\n",
-		    machine->machine_subtype);
-		exit(1);
-	}
-}
-
-
-MACHINE_DEFAULT_RAM(prep)
-{
-	machine->physical_ram_in_mb = 64;
-}
-
-
-MACHINE_REGISTER(prep)
-{
-	MR_DEFAULT(prep, "PowerPC Reference Platform", ARCH_PPC, MACHINE_PREP);
-
-	machine_entry_add_alias(me, "prep");
-	me->set_default_ram = machine_default_ram_prep;
-
-	machine_entry_add_subtype(me, "IBM 6050/6070", MACHINE_PREP_IBM6050,
-	    "ibm6050", "ibm6070", NULL);
-
-	machine_entry_add_subtype(me, "MVME2400", MACHINE_PREP_MVME2400,
-	    "mvme2400", NULL);
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_rpi.c gxemul-0.7.0+dfsg/src/machines/machine_rpi.c
--- gxemul-0.6.2/src/machines/machine_rpi.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_rpi.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,81 @@
+/*
+ *  Copyright (C) 2013-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Raspberry Pi
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+MACHINE_SETUP(rpi)
+{
+	machine->machine_name = strdup("Raspberry Pi");
+
+	if (machine->emulated_hz == 0)
+		machine->emulated_hz = 700000000;
+
+	if (!machine->prom_emulation)
+		return;
+
+	arm_setup_initial_translation_table(cpu, 7 * 1048576 - 32768);
+}
+
+
+MACHINE_DEFAULT_CPU(rpi)
+{
+	// "700 MHz ARM1176JZF-S core (ARM11 family, ARMv6 instruction set)[3]"
+	// according to Wikipedia.
+	// NOTE/TODO: This is wrong, but should be enough for
+	// starting with simple experiments.
+	machine->cpu_name = strdup("ARM1136JSR1");
+}
+
+
+MACHINE_DEFAULT_RAM(rpi)
+{
+	machine->physical_ram_in_mb = 512;
+}
+
+
+MACHINE_REGISTER(rpi)
+{
+	MR_DEFAULT(rpi, "Raspberry Pi", MACHINE_RPI);
+
+	machine_entry_add_alias(me, "rpi");
+
+	me->set_default_ram = machine_default_ram_rpi;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_rpi.cc gxemul-0.7.0+dfsg/src/machines/machine_rpi.cc
--- gxemul-0.6.2/src/machines/machine_rpi.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_rpi.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,81 +0,0 @@
-/*
- *  Copyright (C) 2013  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Raspberry Pi
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-MACHINE_SETUP(rpi)
-{
-	machine->machine_name = strdup("Raspberry Pi");
-
-	if (machine->emulated_hz == 0)
-		machine->emulated_hz = 700000000;
-
-	if (!machine->prom_emulation)
-		return;
-
-	arm_setup_initial_translation_table(cpu, 7 * 1048576 - 32768);
-}
-
-
-MACHINE_DEFAULT_CPU(rpi)
-{
-	// "700 MHz ARM1176JZF-S core (ARM11 family, ARMv6 instruction set)[3]"
-	// according to Wikipedia.
-	// NOTE/TODO: This is wrong, but should be enough for
-	// starting with simple experiments.
-	machine->cpu_name = strdup("ARM1136JSR1");
-}
-
-
-MACHINE_DEFAULT_RAM(rpi)
-{
-	machine->physical_ram_in_mb = 512;
-}
-
-
-MACHINE_REGISTER(rpi)
-{
-	MR_DEFAULT(rpi, "Raspberry Pi", ARCH_ARM, MACHINE_RPI);
-
-	machine_entry_add_alias(me, "rpi");
-
-	me->set_default_ram = machine_default_ram_rpi;
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_sgi.c gxemul-0.7.0+dfsg/src/machines/machine_sgi.c
--- gxemul-0.6.2/src/machines/machine_sgi.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_sgi.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,701 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Silicon Graphics' MIPS-based machines
+ *
+ *  http://obsolete.majix.org/computers/sgi/iptable.shtml contains a
+ *  pretty detailed list of IP ("Inhouse Processor") model numbers.
+ *
+ *  See also: http://hardware.majix.org/computers/sgi/iptable.shtml
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "arcbios.h"
+#include "bus_pci.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "net.h"
+
+#include "thirdparty/sgi_arcbios.h"
+#include "thirdparty/crimereg.h"
+
+
+#define ETHERNET_STRING_MAXLEN  	40
+#define	MACHINE_NAME_MAXBUF		100
+
+
+MACHINE_SETUP(sgi)
+{
+	uint64_t sgi_ram_offset = 0;
+	int arc_wordlen = sizeof(uint32_t);
+	struct memory *mem = machine->memory;
+	char tmpstr[1000];
+	int i, j;
+	unsigned char macaddr[6];
+	char *machineName;
+
+	struct pci_data *pci_data = NULL;
+
+	CHECK_ALLOCATION(machineName = (char *) malloc(MACHINE_NAME_MAXBUF));
+	machine->machine_name = machineName;
+
+	cpu->byte_order = EMUL_BIG_ENDIAN;
+	snprintf(machineName, MACHINE_NAME_MAXBUF,
+	    "SGI-IP%i", machine->machine_subtype);
+
+	sgi_ram_offset = 1048576 * machine->memory_offset_in_mb;
+
+	/*  Special cases for IP20,22,24,26 memory offset:  */
+	if (machine->machine_subtype == 20 || machine->machine_subtype == 22 ||
+	    machine->machine_subtype == 24 || machine->machine_subtype == 26) {
+		dev_ram_init(machine, 0x00000000, 0x10000, DEV_RAM_MIRROR
+		    | DEV_RAM_MIGHT_POINT_TO_DEVICES, sgi_ram_offset, NULL);
+		dev_ram_init(machine, 0x00050000, sgi_ram_offset-0x50000,
+		    DEV_RAM_MIRROR | DEV_RAM_MIGHT_POINT_TO_DEVICES,
+		    sgi_ram_offset + 0x50000, NULL);
+	}
+
+	/*  Special cases for IP28,30 memory offset:  */
+	if (machine->machine_subtype == 28 || machine->machine_subtype == 30) {
+		/*  TODO: length below should maybe not be 128MB?  */
+		dev_ram_init(machine, 0x00000000, 128*1048576, DEV_RAM_MIRROR
+		    | DEV_RAM_MIGHT_POINT_TO_DEVICES, sgi_ram_offset, NULL);
+	}
+
+	net_generate_unique_mac(machine, macaddr);
+
+	char *eaddr_string;
+	CHECK_ALLOCATION(eaddr_string = (char *) malloc(ETHERNET_STRING_MAXLEN));
+
+	switch (machine->machine_subtype) {
+
+	case 10:
+		strlcat(machineName, " (4D/25)", MACHINE_NAME_MAXBUF);
+		/*  TODO  */
+		break;
+
+	case 12:
+		strlcat(machineName, " (Iris Indigo IP12)", MACHINE_NAME_MAXBUF);
+
+		/*  TODO  */
+		/*  33 MHz R3000, according to http://www.irisindigo.com/  */
+		/*  "capable of addressing up to 96MB of memory."  */
+
+		break;
+
+	case 19:
+		strlcat(machineName,
+		    " (Everest IP19)", MACHINE_NAME_MAXBUF);
+		machine->main_console_handle = (size_t)device_add(machine,
+		    "z8530 addr=0x1fbd9830 irq=0 addr_mult=4");
+
+		fatal("TODO ip19 interrupt rewrite\n");
+		abort();
+		//dev_scc_init(machine, mem, 0x10086000, 0,
+		//    machine->x11_md.in_use, 0, 8);	/*  serial? irix?  */
+
+		device_add(machine, "sgi_ip19 addr=0x18000000");
+
+		/*  Irix' <everest_du_init+0x130> reads this device:  */
+		device_add(machine, "random addr=0x10006000 len=16");
+
+		/*  Irix' get_mpconf() looks for this:  (TODO)  */
+		store_32bit_word(cpu, 0xa0000000 + 0x3000,
+		    0xbaddeed2);
+
+		/*  Memory size, not 4096 byte pages, but 256 bytes?
+		    (16 is size of kernel... approx)  */
+		store_32bit_word(cpu, 0xa0000000 + 0x26d0, 30000);
+		  /* (machine->physical_ram_in_mb - 16) * (1048576 / 256));  */
+
+		break;
+
+	case 20:
+		strlcat(machineName, " (Indigo)", MACHINE_NAME_MAXBUF);
+
+		/*
+		 *  Guesses based on NetBSD 2.0 beta, 20040606.
+		 *
+		 *  int0 at mainbus0 addr 0x1fb801c0: bus 1MHz, CPU 2MHz
+		 *  imc0 at mainbus0 addr 0x1fa00000: revision 0
+		 *  gio0 at imc0
+		 *  unknown GIO card (product 0x00 revision 0x00)
+		 *	at gio0 slot 0 addr 0x1f400000 not configured
+		 *  unknown GIO card (product 0x00 revision 0x00)
+		 *	at gio0 slot 1 addr 0x1f600000 not configured
+		 *  unknown GIO card (product 0x00 revision 0x00)
+		 *	at gio0 slot 2 addr 0x1f000000 not configured
+		 *  hpc0 at gio0 addr 0x1fb80000: SGI HPC1
+		 *  zsc0 at hpc0 offset 0xd10   (channels 0 and 1,
+		 *				 channel 1 for console)
+		 *  zsc1 at hpc0 offset 0xd00   (2 channels)
+		 *  sq0 at hpc0 offset 0x100: SGI Seeq 80c03
+		 *  wdsc0 at hpc0 offset 0x11f
+		 *  dpclock0 at hpc0 offset 0xe00
+		 */
+
+		/*  int0 at mainbus0 addr 0x1fb801c0  */
+fatal("TODO: SGI legacy interrupt system rewrite!\n");
+abort();
+//		machine->md_int.sgi_ip20_data = dev_sgi_ip20_init(cpu, mem,
+//		    DEV_SGI_IP20_BASE);
+
+		/*  imc0 at mainbus0 addr 0x1fa00000: revision 0:
+		    TODO (or in dev_sgi_ip20?)  */
+
+		machine->main_console_handle = (size_t)device_add(machine,
+		    "z8530 addr=0x1fbd9830 irq=0 addr_mult=4");
+
+		/*  This is the zsc0 reported by NetBSD:  TODO: irqs  */
+		machine->main_console_handle = (size_t)device_add(machine,
+		    "z8530 addr=0x1fb80d10 irq=0 addr_mult=4");
+		machine->main_console_handle = (size_t)device_add(machine,
+		    "z8530 addr=0x1fb80d00 irq=0 addr_mult=4");
+
+		/*  WDSC SCSI controller:  */
+/*		dev_wdsc_init(machine, mem, 0x1fb8011f, 0, 0);  */
+
+		/*  Return memory read errors so that hpc1
+		    and hpc2 are not detected:  */
+		device_add(machine, "unreadable addr=0x1fb00000 len=0x10000");
+		device_add(machine, "unreadable addr=0x1f980000 len=0x10000");
+
+		/*  Return nothing for gio slots 0, 1, and 2: */
+		device_add(machine, "unreadable addr=0x1f400000 len=0x1000");
+		device_add(machine, "unreadable addr=0x1f600000 len=0x1000");
+		device_add(machine, "unreadable addr=0x1f000000 len=0x1000");
+
+		break;
+
+	case 21:
+		strlcat(machineName,	/*  TODO  */
+		    " (uknown SGI-IP21 ?)", MACHINE_NAME_MAXBUF);
+		/*  NOTE:  Special case for arc_wordlen:  */
+		arc_wordlen = sizeof(uint64_t);
+
+		device_add(machine, "random addr=0x418000200, len=0x20000");
+
+		break;
+
+	case 22:
+	case 24:
+		if (machine->machine_subtype == 22) {
+			strlcat(machineName,
+			    " (Indy, Indigo2, Challenge S; Full-house)",
+			    MACHINE_NAME_MAXBUF);
+fatal("TODO: SGI legacy interrupt system rewrite!\n");
+abort();
+//			machine->md_int.sgi_ip22_data =
+//			    dev_sgi_ip22_init(machine, mem, 0x1fbd9000, 0);
+		} else {
+			strlcat(machineName,
+			    " (Indy, Indigo2, Challenge S; Guiness)",
+			    MACHINE_NAME_MAXBUF);
+fatal("TODO: SGI legacy interrupt system rewrite!\n");
+abort();
+//			machine->md_int.sgi_ip22_data =
+//			    dev_sgi_ip22_init(machine, mem, 0x1fbd9880, 1);
+		}
+
+/*
+Why is this here? TODO
+		dev_ram_init(machine, 0x88000000ULL,
+		    128 * 1048576, DEV_RAM_MIRROR, 0x08000000, NULL);
+*/
+
+fatal("TODO: Legacy rewrite\n");
+abort();
+//		machine->md_interrupt = sgi_ip22_interrupt;
+
+		/*
+		 *  According to NetBSD 1.6.2:
+		 *
+		 *  imc0 at mainbus0 addr 0x1fa00000, Revision 0
+		 *  gio0 at imc0
+		 *  hpc0 at gio0 addr 0x1fb80000: SGI HPC3
+		 *  zsc0 at hpc0 offset 0x59830
+		 *  zstty0 at zsc0 channel 1 (console i/o)
+		 *  zstty1 at zsc0 channel 0
+		 *  sq0 at hpc0 offset 0x54000: SGI Seeq 80c03	(Ethernet)
+		 *  wdsc0 at hpc0 offset 0x44000: WD33C93 SCSI, rev=0, target 7
+		 *  scsibus2 at wdsc0: 8 targets, 8 luns per target
+		 *  dsclock0 at hpc0 offset 0x60000
+		 *
+		 *  According to Linux/IP22:
+		 *  tty00 at 0xbfbd9830 (irq = 45) is a Zilog8530
+		 *  tty01 at 0xbfbd9838 (irq = 45) is a Zilog8530
+		 *
+		 *  and according to NetBSD 2.0_BETA (20040606):
+		 *
+		 *  haltwo0 at hpc0 offset 0x58000: HAL2 revision 0.0.0
+		 *  audio0 at haltwo0: half duplex
+		 *
+		 *  IRQ numbers are of the form 8 + x, where x=0..31 for local0
+		 *  interrupts, and 32..63 for local1.  + y*65 for "mappable".
+		 */
+
+		/*  zsc0 serial console. 8 + 32 + 3 + 64*5 = 43+64*5 = 363 */
+		i = (size_t)device_add(machine,
+		    "z8530 addr=0x1fbd9830 irq=363 addr_mult=4");
+
+		/*  Not supported by NetBSD 1.6.2, but by 2.0_BETA:  */
+fatal("TODO: legacy rewrite\n");
+abort();
+//		j = dev_pckbc_init(machine, mem, 0x1fbd9840, PCKBC_8242,
+//		    0, 0, machine->x11_md.in_use, 0);  /*  TODO: irq numbers  */
+j = 0;
+
+		if (machine->x11_md.in_use)
+			machine->main_console_handle = j;
+
+		/*  sq0: Ethernet.  TODO:  This should have irq_nr = 8 + 3  */
+		/*  dev_sq_init...  */
+
+		/*  wdsc0: SCSI  */
+/*		dev_wdsc_init(machine, mem, 0x1fbc4000, 0, 8 + 1);  */
+
+		/*  wdsc1: SCSI  TODO: irq nr  */
+/*		dev_wdsc_init(machine, mem, 0x1fbcc000, 1, 8 + 1);  */
+
+		/*  dsclock0: TODO:  possibly irq 8 + 33  */
+
+		/*  Return memory read errors so that hpc1 and hpc2 are
+		    not detected:  */
+		device_add(machine, "unreadable addr=0x1fb00000, len=0x10000");
+		device_add(machine, "unreadable addr=0x1f980000, len=0x10000");
+
+		/*  Similarly for gio slots 0, 1, and 2:  */
+		device_add(machine, "unreadable addr=0x1f400000, len=0x1000");
+		device_add(machine, "unreadable addr=0x1f600000, len=0x1000");
+		device_add(machine, "unreadable addr=0x1f000000, len=0x1000");
+
+		break;
+
+	case 25:
+		/*  NOTE:  Special case for arc_wordlen:  */
+		arc_wordlen = sizeof(uint64_t);
+		strlcat(machineName, " (Everest IP25)", MACHINE_NAME_MAXBUF);
+
+		 /*  serial? irix?  */
+		fatal("TODO ip25 interrupt rewrite\n");
+		abort();
+		//dev_scc_init(machine, mem,
+		//    0x400086000ULL, 0, machine->x11_md.in_use, 0, 8);
+
+		/*  NOTE: ip19! (perhaps not really the same  */
+		device_add(machine, "sgi_ip19 addr=0x18000000");
+
+		/*
+		 *  Memory size, not 4096 byte pages, but 256
+		 *  bytes?  (16 is size of kernel... approx)
+		 */
+		store_32bit_word(cpu, 0xa0000000ULL + 0x26d0,
+		    30000);  /* (machine->physical_ram_in_mb - 16)
+				 * (1048576 / 256));  */
+
+		break;
+
+	case 26:
+		/*  NOTE:  Special case for arc_wordlen:  */
+		arc_wordlen = sizeof(uint64_t);
+		strlcat(machineName, " (uknown SGI-IP26 ?)",
+		    MACHINE_NAME_MAXBUF);	/*  TODO  */
+		machine->main_console_handle = (size_t)device_add(machine,
+		    "z8530 addr=0x1fbd9830 irq=0 addr_mult=4");
+		break;
+
+	case 27:
+		strlcat(machineName, " (Origin 200/2000, Onyx2)",
+		    MACHINE_NAME_MAXBUF);
+		arc_wordlen = sizeof(uint64_t);
+		/*  2 cpus per node  */
+
+		machine->main_console_handle = (size_t)device_add(machine,
+		    "z8530 addr=0x1fbd9830 irq=0 addr_mult=4");
+		break;
+
+	case 28:
+		/*  NOTE:  Special case for arc_wordlen:  */
+		arc_wordlen = sizeof(uint64_t);
+		strlcat(machineName, " (Impact Indigo2 ?)", MACHINE_NAME_MAXBUF);
+
+		device_add(machine, "random addr=0x1fbe0000, len=1");
+
+		/*  Something at paddr 0x1880fb0000.  */
+
+		break;
+
+	case 30:
+		/*  NOTE:  Special case for arc_wordlen:  */
+		arc_wordlen = sizeof(uint64_t);
+		strlcat(machineName, " (Octane)",
+		    MACHINE_NAME_MAXBUF);
+
+		// TODO: Interrupts!
+		snprintf(tmpstr, sizeof(tmpstr),
+		    "sgi_ip30 addr=0x0ff00000");
+		device_add(machine, tmpstr);
+
+		dev_ram_init(machine, 0xa0000000ULL, 128 * 1048576,
+		    DEV_RAM_MIRROR | DEV_RAM_MIGHT_POINT_TO_DEVICES,
+		    0x00000000, NULL);
+
+		dev_ram_init(machine,    0x80000000ULL,
+		    32 * 1048576, DEV_RAM_RAM, 0x00000000, NULL);
+
+		/*
+		 *  Something at paddr=1f022004: TODO
+		 *  Something at paddr=813f0510 - paddr=813f0570 ?
+		 *  Something at paddr=813f04b8
+		 *  Something at paddr=f8000003c  used by Linux/Octane
+		 *
+		 *  16550 serial port at paddr=1f620178, addr mul 1
+		 *  (Error messages are printed to this serial port by
+		 *  the PROM.)
+		 *
+		 *  There seems to also be a serial port at 1f620170. The
+		 *  "symmon" program dumps something there, but it doesn't
+		 *  look like readable text.  (TODO)
+		 */
+
+		/*  TODO: irq!  */
+		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].2 addr="
+		    "0x1f620170 name2=tty0 in_use=%i",
+		    machine->path, machine->bootstrap_cpu,
+		    machine->x11_md.in_use? 0 : 1);
+		machine->main_console_handle = (size_t)device_add(machine,
+		    tmpstr);
+		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].2 addr="
+		    "0x1f620178 name2=tty1 in_use=0",
+		    machine->path, machine->bootstrap_cpu);
+		device_add(machine, tmpstr);
+
+		/*  MardiGras graphics:  */
+		device_add(machine, "sgi_mardigras addr=0x1c000000");
+
+		break;
+
+	case 32:
+		strlcat(machineName, " (O2)", MACHINE_NAME_MAXBUF);
+
+		/*
+		 *  The IP32 prom probes "bank 0" with the following
+		 *  TLB entries:
+		 *
+		 *  00: vaddr=0000000000000000 (global):  p0=0x040000000 D p1=0x041000000 D (16MB)
+		 *  01: vaddr=0000000002000000 (global):  p0=0x042000000 D p1=0x043000000 D (16MB)
+		 *  02: vaddr=0000000004000000 (global):  p0=0x044000000 D p1=0x045000000 D (16MB)
+		 *  03: vaddr=0000000006000000 (global):  p0=0x046000000 D p1=0x047000000 D (16MB)
+		 *
+		 *  In other words, it uses real memory at 0x40000000 and up.
+		 *  However, it is _also_ accessible at physical address 0x0.
+		 *
+		 *  Max amount of RAM in an O2 is 1 GB. However, devices start at
+		 *  0x14000000 (or below that), so 256 MB is the most that the legacy GXemul
+		 *  framework can handle. Memory above that must be accessed from 0x40000000 and up.
+ 		 */
+
+		if (machine->physical_ram_in_mb > 1024) {
+			fatal("SGI O2 cannot have more than 1 GB of RAM.\n");
+			exit(1);
+		}
+
+		/*  In the new framework, this would be the other way around :-), i.e.
+		    actual memory at 0x40000000 and the first 256 MB would be mirrored
+		    to address 0.  */
+		{
+			int mirrorInMB = machine->physical_ram_in_mb < 256 ? machine->physical_ram_in_mb : 256;
+			dev_ram_init(machine, 0x40000000ULL, mirrorInMB * 1048576, DEV_RAM_MIRROR, 0, NULL);
+			if (machine->physical_ram_in_mb > 256)
+				dev_ram_init(machine, 0x50000000ULL, (machine->physical_ram_in_mb - 256) * 1048576, DEV_RAM_RAM, 0, NULL);
+		}
+		
+		/*  Connect CRIME (Interrupt Controller) to MIPS irq 2:  */
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2",
+		    machine->path, machine->bootstrap_cpu);
+		dev_crime_init(machine, mem, 0x14000000, tmpstr, machine->x11_md.in_use);
+
+		/*  Rendering Engine  */
+		dev_sgi_re_init(machine, mem, 0x15000000);
+
+		/*  Graphics Back End  */
+		dev_sgi_gbe_init(machine, mem, 0x16000000);
+
+		/*
+		 *  A combination of NetBSD and Linux info:
+		 *
+		 *	14000000	crime (interrupt/memory controller?)
+		 *	15000000	drawing engine, memory transfer engine, rendering engine
+		 *	16000000	gbe (graphics), crm framebuffer control
+		 *      17000000	vice (Video Image Compression Engine)
+		 *	18000000	pci (?)
+		 *	1f000000	mace
+		 *	1f080000	macepci
+		 *	1f100000	vin1
+		 *	1f180000	vin2
+		 *	1f200000	vout
+		 *	1f280000	enet (mec0, MAC-110 Ethernet)
+		 *	1f300000	perif:
+		 *	  1f300000	  audio ("a3"?)
+		 *	  1f310000	  isa
+		 *	    1f318000	    (unknown, accessed by Irix' pciio_pio_write64 and by the PROM during bootup)
+		 *	    1f31c000	    (unknown, accessed by the PROM during bootup)
+		 *	  1f320000	  kbdms
+		 *	  1f330000	  i2c
+		 *	  1f340000	  ust
+		 *	1f380000	isa ext
+		 * 	  1f390000	  com0 (serial)
+		 * 	  1f398000	  com1 (serial)
+		 * 	  1f3a0000	  mcclock0
+		 */
+
+		/*
+		 *  IRQ mapping is really ugly.  TODO: fix
+		 *
+		 *  com0 at mace0 offset 0x390000 intr 4 intrmask
+		 *	0x3f00000: ns16550a, working fifo
+		 *  com1 at mace0 offset 0x398000 intr 4 intrmask
+		 *	0xfc000000: ns16550a, working fifo
+		 *  pckbc0 at mace0 offset 0x320000 intr 5 intrmask 0x0
+		 *  mcclock0 at mace0 offset 0x3a0000 intrmask 0x0
+		 *  macepci0 at mace0 offset 0x80000 intr 7 intrmask 0x0: rev 1
+		 *
+		 *  intr 4 = CRIME_INT_PERIPH_SERIAL
+		 *  intr 5 = CRIME_INT_PERIPH_MISC
+		 *  intr 7 = CRIME_INT_PCI_BRIDGE
+		 */
+
+		snprintf(eaddr_string, ETHERNET_STRING_MAXLEN,
+		    "%02x:%02x:%02x:%02x:%02x:%02x",
+		    macaddr[0], macaddr[1], macaddr[2],
+		    macaddr[3], macaddr[4], macaddr[5]);
+
+		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.crime.0x%x",
+		    machine->path, machine->bootstrap_cpu, CRIME_INT_ETHERNET);
+		dev_sgi_mec_init(machine, mem, 0x1f280000,
+		    tmpstr, macaddr);
+
+		dev_sgi_ust_init(mem, 0x1f340000);  /*  ust?  */
+
+		snprintf(tmpstr, sizeof(tmpstr),
+		    "ns16550 irq=%s.cpu[%i].2.crime.0x%x.mace.%i addr="
+		    "0x1f390000 addr_mult=0x100 in_use=%i name2=tty0",
+		    machine->path, machine->bootstrap_cpu,
+		    CRIME_INT_PERIPH_SERIAL, 20, machine->x11_md.in_use? 0 : 1);
+		j = (size_t)device_add(machine, tmpstr);
+		snprintf(tmpstr, sizeof(tmpstr),
+		    "ns16550 irq=%s.cpu[%i].2.crime.0x%x.mace.%i addr="
+		    "0x1f398000 addr_mult=0x100 in_use=%i name2=tty1",
+		    machine->path, machine->bootstrap_cpu,
+		    CRIME_INT_PERIPH_SERIAL, 26, 0);
+		device_add(machine, tmpstr);
+
+		machine->main_console_handle = j;
+
+		{
+			/*  keyb+mouse (mace irq numbers)  */
+			char tmpstr1[1000];
+			char tmpstr2[1000];
+			snprintf(tmpstr1, sizeof(tmpstr1),
+			    "%s.cpu[%i].2.crime.0x%x.mace.%i",
+			    machine->path, machine->bootstrap_cpu,
+			    CRIME_INT_PERIPH_MISC, 9);
+
+			snprintf(tmpstr2, sizeof(tmpstr2),
+			    "%s.cpu[%i].2.crime.0x%x.mace.%i",
+			    machine->path, machine->bootstrap_cpu,
+			    CRIME_INT_PERIPH_MISC, 11);
+
+			i = dev_pckbc_init(machine, mem, 0x1f320000,
+			    PCKBC_8242, tmpstr1,
+			    tmpstr2, machine->x11_md.in_use,
+			    0);
+
+			if (machine->x11_md.in_use)
+				machine->main_console_handle = i;
+		}
+
+		snprintf(tmpstr, sizeof(tmpstr),
+		    "%s.cpu[%i].2.crime.0x%x.mace.%i",
+		    machine->path, machine->bootstrap_cpu,
+		    CRIME_INT_PERIPH_MISC, 8);
+		dev_mc146818_init(machine, mem, 0x1f3a0000, tmpstr,
+		    MC146818_SGI, 0x40);  /*  mcclock0  */
+
+		/*
+		 *  PCI devices:   (according to NetBSD's GENERIC
+		 *  config file for sgimips)
+		 *
+		 *	ne*             at pci? dev ? function ?
+		 *	ahc0            at pci0 dev 1 function ?
+		 *	ahc1            at pci0 dev 2 function ?
+		 */
+
+		snprintf(tmpstr, sizeof(tmpstr),
+		    "%s.cpu[%i].2.crime.0x%x", machine->path,
+		    machine->bootstrap_cpu, CRIME_INT_PCI_BRIDGE);
+		pci_data = dev_macepci_init(machine, mem, 0x1f080000,
+		    tmpstr);		/*  macepci0  */
+		/*  bus_pci_add(machine, pci_data, mem, 0, 0, 0,
+		    "ne2000");  TODO  */
+
+		/*
+		 *  OpenBSD accesses the SCSI controller at paddr=0x2800010xx.
+		 *  Note that the 2 is above 32-bit range.
+		 *
+		 *  TODO: Investigate what this actually means. Possibly
+		 *  a bug in GXemul's 64-bit instructions? Or perhaps it really
+		 *  is correct.
+		 */
+		dev_ram_init(machine, 0x280000000ULL, 0x01000000, DEV_RAM_MIRROR, 0x18000000, NULL);
+
+
+		// ahc0:
+		/*  TODO: Make it possible to add the controller, regardless of
+			the existence of disks!  */
+		if (diskimage_exist(machine, 0, DISKIMAGE_SCSI) ||
+		    diskimage_exist(machine, 1, DISKIMAGE_SCSI) ||
+		    diskimage_exist(machine, 2, DISKIMAGE_SCSI) ||
+		    diskimage_exist(machine, 3, DISKIMAGE_SCSI) ||
+		    diskimage_exist(machine, 4, DISKIMAGE_SCSI) ||
+		    diskimage_exist(machine, 5, DISKIMAGE_SCSI) ||
+		    diskimage_exist(machine, 6, DISKIMAGE_SCSI) ||
+		    diskimage_exist(machine, 7, DISKIMAGE_SCSI))
+			bus_pci_add(machine, pci_data, mem, 0, 1, 0, "ahc");
+
+		// ahc1:
+		// bus_pci_add(machine, pci_data, mem, 0, 2, 0, "ahc");
+
+		break;
+
+	case 35:
+		strlcat(machineName, " (Origin 3000)", MACHINE_NAME_MAXBUF);
+		/*  4 cpus per node  */
+
+		// TODO: Correct Interrupt!
+		snprintf(tmpstr, sizeof(tmpstr), "z8530 addr=0x1fbd9830 irq=%s.cpu[%i].2",
+		    machine->path, machine->bootstrap_cpu);
+		machine->main_console_handle = (size_t)device_add(machine, tmpstr);
+
+		break;
+
+	case 53:
+		strlcat(machineName, " (Origin 350)",
+		    MACHINE_NAME_MAXBUF);
+
+		/*
+		 *  According to http://kumba.drachentekh.net/xml/myguide.html
+		 *  Origin 350, Tezro IP53 R16000
+		 */
+		break;
+
+	default:
+		fatal("unimplemented SGI machine type IP%i\n",
+		    machine->machine_subtype);
+		exit(1);
+	}
+
+	if (!machine->prom_emulation)
+		return;
+
+	arcbios_init(machine, arc_wordlen == sizeof(uint64_t), sgi_ram_offset,
+	    eaddr_string, macaddr);
+}
+
+
+MACHINE_DEFAULT_CPU(sgi)
+{
+	if (machine->machine_subtype <= 12)
+	        machine->cpu_name = strdup("R3000");
+	if (machine->cpu_name == NULL && machine->machine_subtype == 35)
+	        machine->cpu_name = strdup("R12000");
+	if (machine->cpu_name == NULL && (machine->machine_subtype == 25 ||
+	    machine->machine_subtype == 27 || machine->machine_subtype == 28 ||
+	    machine->machine_subtype == 30 || machine->machine_subtype == 32))
+	        machine->cpu_name = strdup("R10000");
+	if (machine->cpu_name == NULL && (machine->machine_subtype == 21 ||
+	    machine->machine_subtype == 26))
+	        machine->cpu_name = strdup("R8000");
+	if (machine->cpu_name == NULL && machine->machine_subtype == 24)
+	        machine->cpu_name = strdup("R5000");
+                        
+	/*  Other SGIs should probably work with
+	    R4000, R4400 or R5000 or similar:  */
+	if (machine->cpu_name == NULL)
+	        machine->cpu_name = strdup("R4400");
+}
+
+
+MACHINE_DEFAULT_RAM(sgi)
+{
+	// Self-compilation fails with OpenBSD/sgi 6.3 with as low as 128 MB
+	// RAM, so 256 would be better. But my O2 has 128 MB, so this is kept
+	// as 128 to simplify comparison between the real machine and the
+	// emulator.
+	machine->physical_ram_in_mb = 128;
+}
+
+
+MACHINE_REGISTER(sgi)
+{
+	MR_DEFAULT(sgi, "SGI", MACHINE_SGI);
+
+	me->set_default_ram = machine_default_ram_sgi;
+
+	machine_entry_add_alias(me, "silicon graphics");
+	machine_entry_add_alias(me, "sgi");
+
+	machine_entry_add_subtype(me, "IP12", 12, "ip12", NULL);
+
+	machine_entry_add_subtype(me, "IP19", 19, "ip19", NULL);
+
+	machine_entry_add_subtype(me, "IP20", 20, "ip20", NULL);
+
+	machine_entry_add_subtype(me, "IP22", 22, "ip22", "indy", NULL);
+
+	machine_entry_add_subtype(me, "IP24", 24, "ip24", NULL);
+
+	machine_entry_add_subtype(me, "IP27", 27,
+	    "ip27", "origin 200", "origin 2000", NULL);
+
+	machine_entry_add_subtype(me, "IP28", 28, "ip28", NULL);
+
+	machine_entry_add_subtype(me, "IP30", 30, "ip30", "octane", NULL);
+
+	machine_entry_add_subtype(me, "IP32", 32, "ip32", "o2", NULL); 
+
+	machine_entry_add_subtype(me, "IP35", 35, "ip35", NULL); 
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_sgi.cc gxemul-0.7.0+dfsg/src/machines/machine_sgi.cc
--- gxemul-0.6.2/src/machines/machine_sgi.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_sgi.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,700 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Silicon Graphics' MIPS-based machines
- *
- *  http://obsolete.majix.org/computers/sgi/iptable.shtml contains a
- *  pretty detailed list of IP ("Inhouse Processor") model numbers.
- *
- *  See also: http://hardware.majix.org/computers/sgi/iptable.shtml
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "arcbios.h"
-#include "bus_pci.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "net.h"
-
-#include "thirdparty/sgi_arcbios.h"
-#include "thirdparty/crimereg.h"
-
-
-#define ETHERNET_STRING_MAXLEN  	40
-#define	MACHINE_NAME_MAXBUF		100
-
-
-MACHINE_SETUP(sgi)
-{
-	uint64_t sgi_ram_offset = 0;
-	int arc_wordlen = sizeof(uint32_t);
-	struct memory *mem = machine->memory;
-	char tmpstr[1000];
-	int i, j;
-	char *eaddr_string = strdup("eaddr=10:20:30:40:50:60");		/*  bogus  */
-	unsigned char macaddr[6];
-	char *machineName;
-
-	struct pci_data *pci_data = NULL;
-
-	CHECK_ALLOCATION(machineName = (char *) malloc(MACHINE_NAME_MAXBUF));
-	machine->machine_name = machineName;
-
-	cpu->byte_order = EMUL_BIG_ENDIAN;
-	snprintf(machineName, MACHINE_NAME_MAXBUF,
-	    "SGI-IP%i", machine->machine_subtype);
-
-	sgi_ram_offset = 1048576 * machine->memory_offset_in_mb;
-
-	/*  Special cases for IP20,22,24,26 memory offset:  */
-	if (machine->machine_subtype == 20 || machine->machine_subtype == 22 ||
-	    machine->machine_subtype == 24 || machine->machine_subtype == 26) {
-		dev_ram_init(machine, 0x00000000, 0x10000, DEV_RAM_MIRROR
-		    | DEV_RAM_MIGHT_POINT_TO_DEVICES, sgi_ram_offset);
-		dev_ram_init(machine, 0x00050000, sgi_ram_offset-0x50000,
-		    DEV_RAM_MIRROR | DEV_RAM_MIGHT_POINT_TO_DEVICES,
-		    sgi_ram_offset + 0x50000);
-	}
-
-	/*  Special cases for IP28,30 memory offset:  */
-	if (machine->machine_subtype == 28 || machine->machine_subtype == 30) {
-		/*  TODO: length below should maybe not be 128MB?  */
-		dev_ram_init(machine, 0x00000000, 128*1048576, DEV_RAM_MIRROR
-		    | DEV_RAM_MIGHT_POINT_TO_DEVICES, sgi_ram_offset);
-	}
-
-	net_generate_unique_mac(machine, macaddr);
-	CHECK_ALLOCATION(eaddr_string = (char *) malloc(ETHERNET_STRING_MAXLEN));
-
-	switch (machine->machine_subtype) {
-
-	case 10:
-		strlcat(machineName, " (4D/25)", MACHINE_NAME_MAXBUF);
-		/*  TODO  */
-		break;
-
-	case 12:
-		strlcat(machineName, " (Iris Indigo IP12)", MACHINE_NAME_MAXBUF);
-
-		/*  TODO  */
-		/*  33 MHz R3000, according to http://www.irisindigo.com/  */
-		/*  "capable of addressing up to 96MB of memory."  */
-
-		break;
-
-	case 19:
-		strlcat(machineName,
-		    " (Everest IP19)", MACHINE_NAME_MAXBUF);
-		machine->main_console_handle = (size_t)device_add(machine,
-		    "z8530 addr=0x1fbd9830 irq=0 addr_mult=4");
-
-		fatal("TODO ip19 interrupt rewrite\n");
-		abort();
-		//dev_scc_init(machine, mem, 0x10086000, 0,
-		//    machine->x11_md.in_use, 0, 8);	/*  serial? irix?  */
-
-		device_add(machine, "sgi_ip19 addr=0x18000000");
-
-		/*  Irix' <everest_du_init+0x130> reads this device:  */
-		device_add(machine, "random addr=0x10006000 len=16");
-
-		/*  Irix' get_mpconf() looks for this:  (TODO)  */
-		store_32bit_word(cpu, 0xa0000000 + 0x3000,
-		    0xbaddeed2);
-
-		/*  Memory size, not 4096 byte pages, but 256 bytes?
-		    (16 is size of kernel... approx)  */
-		store_32bit_word(cpu, 0xa0000000 + 0x26d0, 30000);
-		  /* (machine->physical_ram_in_mb - 16) * (1048576 / 256));  */
-
-		break;
-
-	case 20:
-		strlcat(machineName, " (Indigo)", MACHINE_NAME_MAXBUF);
-
-		/*
-		 *  Guesses based on NetBSD 2.0 beta, 20040606.
-		 *
-		 *  int0 at mainbus0 addr 0x1fb801c0: bus 1MHz, CPU 2MHz
-		 *  imc0 at mainbus0 addr 0x1fa00000: revision 0
-		 *  gio0 at imc0
-		 *  unknown GIO card (product 0x00 revision 0x00)
-		 *	at gio0 slot 0 addr 0x1f400000 not configured
-		 *  unknown GIO card (product 0x00 revision 0x00)
-		 *	at gio0 slot 1 addr 0x1f600000 not configured
-		 *  unknown GIO card (product 0x00 revision 0x00)
-		 *	at gio0 slot 2 addr 0x1f000000 not configured
-		 *  hpc0 at gio0 addr 0x1fb80000: SGI HPC1
-		 *  zsc0 at hpc0 offset 0xd10   (channels 0 and 1,
-		 *				 channel 1 for console)
-		 *  zsc1 at hpc0 offset 0xd00   (2 channels)
-		 *  sq0 at hpc0 offset 0x100: SGI Seeq 80c03
-		 *  wdsc0 at hpc0 offset 0x11f
-		 *  dpclock0 at hpc0 offset 0xe00
-		 */
-
-		/*  int0 at mainbus0 addr 0x1fb801c0  */
-fatal("TODO: SGI legacy interrupt system rewrite!\n");
-abort();
-//		machine->md_int.sgi_ip20_data = dev_sgi_ip20_init(cpu, mem,
-//		    DEV_SGI_IP20_BASE);
-
-		/*  imc0 at mainbus0 addr 0x1fa00000: revision 0:
-		    TODO (or in dev_sgi_ip20?)  */
-
-		machine->main_console_handle = (size_t)device_add(machine,
-		    "z8530 addr=0x1fbd9830 irq=0 addr_mult=4");
-
-		/*  This is the zsc0 reported by NetBSD:  TODO: irqs  */
-		machine->main_console_handle = (size_t)device_add(machine,
-		    "z8530 addr=0x1fb80d10 irq=0 addr_mult=4");
-		machine->main_console_handle = (size_t)device_add(machine,
-		    "z8530 addr=0x1fb80d00 irq=0 addr_mult=4");
-
-		/*  WDSC SCSI controller:  */
-/*		dev_wdsc_init(machine, mem, 0x1fb8011f, 0, 0);  */
-
-		/*  Return memory read errors so that hpc1
-		    and hpc2 are not detected:  */
-		device_add(machine, "unreadable addr=0x1fb00000 len=0x10000");
-		device_add(machine, "unreadable addr=0x1f980000 len=0x10000");
-
-		/*  Return nothing for gio slots 0, 1, and 2: */
-		device_add(machine, "unreadable addr=0x1f400000 len=0x1000");
-		device_add(machine, "unreadable addr=0x1f600000 len=0x1000");
-		device_add(machine, "unreadable addr=0x1f000000 len=0x1000");
-
-		break;
-
-	case 21:
-		strlcat(machineName,	/*  TODO  */
-		    " (uknown SGI-IP21 ?)", MACHINE_NAME_MAXBUF);
-		/*  NOTE:  Special case for arc_wordlen:  */
-		arc_wordlen = sizeof(uint64_t);
-
-		device_add(machine, "random addr=0x418000200, len=0x20000");
-
-		break;
-
-	case 22:
-	case 24:
-		if (machine->machine_subtype == 22) {
-			strlcat(machineName,
-			    " (Indy, Indigo2, Challenge S; Full-house)",
-			    MACHINE_NAME_MAXBUF);
-fatal("TODO: SGI legacy interrupt system rewrite!\n");
-abort();
-//			machine->md_int.sgi_ip22_data =
-//			    dev_sgi_ip22_init(machine, mem, 0x1fbd9000, 0);
-		} else {
-			strlcat(machineName,
-			    " (Indy, Indigo2, Challenge S; Guiness)",
-			    MACHINE_NAME_MAXBUF);
-fatal("TODO: SGI legacy interrupt system rewrite!\n");
-abort();
-//			machine->md_int.sgi_ip22_data =
-//			    dev_sgi_ip22_init(machine, mem, 0x1fbd9880, 1);
-		}
-
-/*
-Why is this here? TODO
-		dev_ram_init(machine, 0x88000000ULL,
-		    128 * 1048576, DEV_RAM_MIRROR, 0x08000000);
-*/
-
-fatal("TODO: Legacy rewrite\n");
-abort();
-//		machine->md_interrupt = sgi_ip22_interrupt;
-
-		/*
-		 *  According to NetBSD 1.6.2:
-		 *
-		 *  imc0 at mainbus0 addr 0x1fa00000, Revision 0
-		 *  gio0 at imc0
-		 *  hpc0 at gio0 addr 0x1fb80000: SGI HPC3
-		 *  zsc0 at hpc0 offset 0x59830
-		 *  zstty0 at zsc0 channel 1 (console i/o)
-		 *  zstty1 at zsc0 channel 0
-		 *  sq0 at hpc0 offset 0x54000: SGI Seeq 80c03	(Ethernet)
-		 *  wdsc0 at hpc0 offset 0x44000: WD33C93 SCSI, rev=0, target 7
-		 *  scsibus2 at wdsc0: 8 targets, 8 luns per target
-		 *  dsclock0 at hpc0 offset 0x60000
-		 *
-		 *  According to Linux/IP22:
-		 *  tty00 at 0xbfbd9830 (irq = 45) is a Zilog8530
-		 *  tty01 at 0xbfbd9838 (irq = 45) is a Zilog8530
-		 *
-		 *  and according to NetBSD 2.0_BETA (20040606):
-		 *
-		 *  haltwo0 at hpc0 offset 0x58000: HAL2 revision 0.0.0
-		 *  audio0 at haltwo0: half duplex
-		 *
-		 *  IRQ numbers are of the form 8 + x, where x=0..31 for local0
-		 *  interrupts, and 32..63 for local1.  + y*65 for "mappable".
-		 */
-
-		/*  zsc0 serial console. 8 + 32 + 3 + 64*5 = 43+64*5 = 363 */
-		i = (size_t)device_add(machine,
-		    "z8530 addr=0x1fbd9830 irq=363 addr_mult=4");
-
-		/*  Not supported by NetBSD 1.6.2, but by 2.0_BETA:  */
-fatal("TODO: legacy rewrite\n");
-abort();
-//		j = dev_pckbc_init(machine, mem, 0x1fbd9840, PCKBC_8242,
-//		    0, 0, machine->x11_md.in_use, 0);  /*  TODO: irq numbers  */
-j = 0;
-
-		if (machine->x11_md.in_use)
-			machine->main_console_handle = j;
-
-		/*  sq0: Ethernet.  TODO:  This should have irq_nr = 8 + 3  */
-		/*  dev_sq_init...  */
-
-		/*  wdsc0: SCSI  */
-/*		dev_wdsc_init(machine, mem, 0x1fbc4000, 0, 8 + 1);  */
-
-		/*  wdsc1: SCSI  TODO: irq nr  */
-/*		dev_wdsc_init(machine, mem, 0x1fbcc000, 1, 8 + 1);  */
-
-		/*  dsclock0: TODO:  possibly irq 8 + 33  */
-
-		/*  Return memory read errors so that hpc1 and hpc2 are
-		    not detected:  */
-		device_add(machine, "unreadable addr=0x1fb00000, len=0x10000");
-		device_add(machine, "unreadable addr=0x1f980000, len=0x10000");
-
-		/*  Similarly for gio slots 0, 1, and 2:  */
-		device_add(machine, "unreadable addr=0x1f400000, len=0x1000");
-		device_add(machine, "unreadable addr=0x1f600000, len=0x1000");
-		device_add(machine, "unreadable addr=0x1f000000, len=0x1000");
-
-		break;
-
-	case 25:
-		/*  NOTE:  Special case for arc_wordlen:  */
-		arc_wordlen = sizeof(uint64_t);
-		strlcat(machineName, " (Everest IP25)", MACHINE_NAME_MAXBUF);
-
-		 /*  serial? irix?  */
-		fatal("TODO ip25 interrupt rewrite\n");
-		abort();
-		//dev_scc_init(machine, mem,
-		//    0x400086000ULL, 0, machine->x11_md.in_use, 0, 8);
-
-		/*  NOTE: ip19! (perhaps not really the same  */
-		device_add(machine, "sgi_ip19 addr=0x18000000");
-
-		/*
-		 *  Memory size, not 4096 byte pages, but 256
-		 *  bytes?  (16 is size of kernel... approx)
-		 */
-		store_32bit_word(cpu, 0xa0000000ULL + 0x26d0,
-		    30000);  /* (machine->physical_ram_in_mb - 16)
-				 * (1048576 / 256));  */
-
-		break;
-
-	case 26:
-		/*  NOTE:  Special case for arc_wordlen:  */
-		arc_wordlen = sizeof(uint64_t);
-		strlcat(machineName, " (uknown SGI-IP26 ?)",
-		    MACHINE_NAME_MAXBUF);	/*  TODO  */
-		machine->main_console_handle = (size_t)device_add(machine,
-		    "z8530 addr=0x1fbd9830 irq=0 addr_mult=4");
-		break;
-
-	case 27:
-		strlcat(machineName, " (Origin 200/2000, Onyx2)",
-		    MACHINE_NAME_MAXBUF);
-		arc_wordlen = sizeof(uint64_t);
-		/*  2 cpus per node  */
-
-		machine->main_console_handle = (size_t)device_add(machine,
-		    "z8530 addr=0x1fbd9830 irq=0 addr_mult=4");
-		break;
-
-	case 28:
-		/*  NOTE:  Special case for arc_wordlen:  */
-		arc_wordlen = sizeof(uint64_t);
-		strlcat(machineName, " (Impact Indigo2 ?)", MACHINE_NAME_MAXBUF);
-
-		device_add(machine, "random addr=0x1fbe0000, len=1");
-
-		/*  Something at paddr 0x1880fb0000.  */
-
-		break;
-
-	case 30:
-		/*  NOTE:  Special case for arc_wordlen:  */
-		arc_wordlen = sizeof(uint64_t);
-		strlcat(machineName, " (Octane)",
-		    MACHINE_NAME_MAXBUF);
-
-		// TODO: Interrupts!
-		snprintf(tmpstr, sizeof(tmpstr),
-		    "sgi_ip30 addr=0x0ff00000");
-		device_add(machine, tmpstr);
-
-		dev_ram_init(machine, 0xa0000000ULL, 128 * 1048576,
-		    DEV_RAM_MIRROR | DEV_RAM_MIGHT_POINT_TO_DEVICES,
-		    0x00000000);
-
-		dev_ram_init(machine,    0x80000000ULL,
-		    32 * 1048576, DEV_RAM_RAM, 0x00000000);
-
-		/*
-		 *  Something at paddr=1f022004: TODO
-		 *  Something at paddr=813f0510 - paddr=813f0570 ?
-		 *  Something at paddr=813f04b8
-		 *  Something at paddr=f8000003c  used by Linux/Octane
-		 *
-		 *  16550 serial port at paddr=1f620178, addr mul 1
-		 *  (Error messages are printed to this serial port by
-		 *  the PROM.)
-		 *
-		 *  There seems to also be a serial port at 1f620170. The
-		 *  "symmon" program dumps something there, but it doesn't
-		 *  look like readable text.  (TODO)
-		 */
-
-		/*  TODO: irq!  */
-		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].2 addr="
-		    "0x1f620170 name2=tty0 in_use=%i",
-		    machine->path, machine->bootstrap_cpu,
-		    machine->x11_md.in_use? 0 : 1);
-		machine->main_console_handle = (size_t)device_add(machine,
-		    tmpstr);
-		snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].2 addr="
-		    "0x1f620178 name2=tty1 in_use=0",
-		    machine->path, machine->bootstrap_cpu);
-		device_add(machine, tmpstr);
-
-		/*  MardiGras graphics:  */
-		device_add(machine, "sgi_mardigras addr=0x1c000000");
-
-		break;
-
-	case 32:
-		strlcat(machineName, " (O2)", MACHINE_NAME_MAXBUF);
-
-		/*
-		 *  The IP32 prom probes "bank 0" with the following
-		 *  TLB entries:
-		 *
-		 *  00: vaddr=0000000000000000 (global):  p0=0x040000000 D p1=0x041000000 D (16MB)
-		 *  01: vaddr=0000000002000000 (global):  p0=0x042000000 D p1=0x043000000 D (16MB)
-		 *  02: vaddr=0000000004000000 (global):  p0=0x044000000 D p1=0x045000000 D (16MB)
-		 *  03: vaddr=0000000006000000 (global):  p0=0x046000000 D p1=0x047000000 D (16MB)
-		 *
-		 *  In other words, it uses real memory at 0x40000000 and up.
-		 *  However, it is _also_ accessible at physical address 0x0.
-		 *
-		 *  Max amount of RAM in an O2 is 1 GB. However, devices start at
-		 *  0x14000000 (or below that), so 256 MB is the most that the legacy GXemul
-		 *  framework can handle. Memory above that must be accessed from 0x40000000 and up.
- 		 */
-
-		if (machine->physical_ram_in_mb > 1024) {
-			fatal("SGI O2 cannot have more than 1 GB of RAM.\n");
-			exit(1);
-		}
-
-		/*  In the new framework, this would be the other way around :-), i.e.
-		    actual memory at 0x40000000 and the first 256 MB would be mirrored
-		    to address 0.  */
-		{
-			int mirrorInMB = machine->physical_ram_in_mb < 256 ? machine->physical_ram_in_mb : 256;
-			dev_ram_init(machine, 0x40000000ULL, mirrorInMB * 1048576, DEV_RAM_MIRROR, 0);
-			if (machine->physical_ram_in_mb > 256)
-				dev_ram_init(machine, 0x50000000ULL, (machine->physical_ram_in_mb - 256) * 1048576, DEV_RAM_RAM, 0);
-		}
-		
-		/*  Connect CRIME (Interrupt Controller) to MIPS irq 2:  */
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2",
-		    machine->path, machine->bootstrap_cpu);
-		dev_crime_init(machine, mem, 0x14000000, tmpstr, machine->x11_md.in_use);
-
-		/*  Rendering Engine  */
-		dev_sgi_re_init(machine, mem, 0x15000000);
-
-		/*  Graphics Back End  */
-		dev_sgi_gbe_init(machine, mem, 0x16000000);
-
-		/*
-		 *  A combination of NetBSD and Linux info:
-		 *
-		 *	14000000	crime (interrupt/memory controller?)
-		 *	15000000	drawing engine, memory transfer engine, rendering engine
-		 *	16000000	gbe (graphics), crm framebuffer control
-		 *      17000000	vice (Video Image Compression Engine)
-		 *	18000000	pci (?)
-		 *	1f000000	mace
-		 *	1f080000	macepci
-		 *	1f100000	vin1
-		 *	1f180000	vin2
-		 *	1f200000	vout
-		 *	1f280000	enet (mec0, MAC-110 Ethernet)
-		 *	1f300000	perif:
-		 *	  1f300000	  audio ("a3"?)
-		 *	  1f310000	  isa
-		 *	    1f318000	    (unknown, accessed by Irix' pciio_pio_write64 and by the PROM during bootup)
-		 *	    1f31c000	    (unknown, accessed by the PROM during bootup)
-		 *	  1f320000	  kbdms
-		 *	  1f330000	  i2c
-		 *	  1f340000	  ust
-		 *	1f380000	isa ext
-		 * 	  1f390000	  com0 (serial)
-		 * 	  1f398000	  com1 (serial)
-		 * 	  1f3a0000	  mcclock0
-		 */
-
-		/*
-		 *  IRQ mapping is really ugly.  TODO: fix
-		 *
-		 *  com0 at mace0 offset 0x390000 intr 4 intrmask
-		 *	0x3f00000: ns16550a, working fifo
-		 *  com1 at mace0 offset 0x398000 intr 4 intrmask
-		 *	0xfc000000: ns16550a, working fifo
-		 *  pckbc0 at mace0 offset 0x320000 intr 5 intrmask 0x0
-		 *  mcclock0 at mace0 offset 0x3a0000 intrmask 0x0
-		 *  macepci0 at mace0 offset 0x80000 intr 7 intrmask 0x0: rev 1
-		 *
-		 *  intr 4 = CRIME_INT_PERIPH_SERIAL
-		 *  intr 5 = CRIME_INT_PERIPH_MISC
-		 *  intr 7 = CRIME_INT_PCI_BRIDGE
-		 */
-
-		snprintf(eaddr_string, ETHERNET_STRING_MAXLEN,
-		    "eaddr=%02x:%02x:%02x:%02x:%02x:%02x",
-		    macaddr[0], macaddr[1], macaddr[2],
-		    macaddr[3], macaddr[4], macaddr[5]);
-
-		snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].2.crime.0x%x",
-		    machine->path, machine->bootstrap_cpu, CRIME_INT_ETHERNET);
-		dev_sgi_mec_init(machine, mem, 0x1f280000,
-		    tmpstr, macaddr);
-
-		dev_sgi_ust_init(mem, 0x1f340000);  /*  ust?  */
-
-		snprintf(tmpstr, sizeof(tmpstr),
-		    "ns16550 irq=%s.cpu[%i].2.crime.0x%x.mace.%i addr="
-		    "0x1f390000 addr_mult=0x100 in_use=%i name2=tty0",
-		    machine->path, machine->bootstrap_cpu,
-		    CRIME_INT_PERIPH_SERIAL, 20, machine->x11_md.in_use? 0 : 1);
-		j = (size_t)device_add(machine, tmpstr);
-		snprintf(tmpstr, sizeof(tmpstr),
-		    "ns16550 irq=%s.cpu[%i].2.crime.0x%x.mace.%i addr="
-		    "0x1f398000 addr_mult=0x100 in_use=%i name2=tty1",
-		    machine->path, machine->bootstrap_cpu,
-		    CRIME_INT_PERIPH_SERIAL, 26, 0);
-		device_add(machine, tmpstr);
-
-		machine->main_console_handle = j;
-
-		{
-			/*  keyb+mouse (mace irq numbers)  */
-			char tmpstr1[1000];
-			char tmpstr2[1000];
-			snprintf(tmpstr1, sizeof(tmpstr1),
-			    "%s.cpu[%i].2.crime.0x%x.mace.%i",
-			    machine->path, machine->bootstrap_cpu,
-			    CRIME_INT_PERIPH_MISC, 9);
-
-			snprintf(tmpstr2, sizeof(tmpstr2),
-			    "%s.cpu[%i].2.crime.0x%x.mace.%i",
-			    machine->path, machine->bootstrap_cpu,
-			    CRIME_INT_PERIPH_MISC, 11);
-
-			i = dev_pckbc_init(machine, mem, 0x1f320000,
-			    PCKBC_8242, tmpstr1,
-			    tmpstr2, machine->x11_md.in_use,
-			    0);
-
-			if (machine->x11_md.in_use)
-				machine->main_console_handle = i;
-		}
-
-		snprintf(tmpstr, sizeof(tmpstr),
-		    "%s.cpu[%i].2.crime.0x%x.mace.%i",
-		    machine->path, machine->bootstrap_cpu,
-		    CRIME_INT_PERIPH_MISC, 8);
-		dev_mc146818_init(machine, mem, 0x1f3a0000, tmpstr,
-		    MC146818_SGI, 0x40);  /*  mcclock0  */
-
-		/*
-		 *  PCI devices:   (according to NetBSD's GENERIC
-		 *  config file for sgimips)
-		 *
-		 *	ne*             at pci? dev ? function ?
-		 *	ahc0            at pci0 dev 1 function ?
-		 *	ahc1            at pci0 dev 2 function ?
-		 */
-
-		snprintf(tmpstr, sizeof(tmpstr),
-		    "%s.cpu[%i].2.crime.0x%x", machine->path,
-		    machine->bootstrap_cpu, CRIME_INT_PCI_BRIDGE);
-		pci_data = dev_macepci_init(machine, mem, 0x1f080000,
-		    tmpstr);		/*  macepci0  */
-		/*  bus_pci_add(machine, pci_data, mem, 0, 0, 0,
-		    "ne2000");  TODO  */
-
-		/*
-		 *  OpenBSD accesses the SCSI controller at paddr=0x2800010xx.
-		 *  Note that the 2 is above 32-bit range.
-		 *
-		 *  TODO: Investigate what this actually means. Possibly
-		 *  a bug in GXemul's 64-bit instructions? Or perhaps it really
-		 *  is correct.
-		 */
-		dev_ram_init(machine, 0x280000000ULL, 0x01000000, DEV_RAM_MIRROR, 0x18000000);
-
-
-		// ahc0:
-		/*  TODO: Make it possible to add the controller, regardless of
-			the existence of disks!  */
-		if (diskimage_exist(machine, 0, DISKIMAGE_SCSI) ||
-		    diskimage_exist(machine, 1, DISKIMAGE_SCSI) ||
-		    diskimage_exist(machine, 2, DISKIMAGE_SCSI) ||
-		    diskimage_exist(machine, 3, DISKIMAGE_SCSI) ||
-		    diskimage_exist(machine, 4, DISKIMAGE_SCSI) ||
-		    diskimage_exist(machine, 5, DISKIMAGE_SCSI) ||
-		    diskimage_exist(machine, 6, DISKIMAGE_SCSI) ||
-		    diskimage_exist(machine, 7, DISKIMAGE_SCSI))
-			bus_pci_add(machine, pci_data, mem, 0, 1, 0, "ahc");
-
-		// ahc1:
-		// bus_pci_add(machine, pci_data, mem, 0, 2, 0, "ahc");
-
-		break;
-
-	case 35:
-		strlcat(machineName, " (Origin 3000)", MACHINE_NAME_MAXBUF);
-		/*  4 cpus per node  */
-
-		// TODO: Correct Interrupt!
-		snprintf(tmpstr, sizeof(tmpstr), "z8530 addr=0x1fbd9830 irq=%s.cpu[%i].2",
-		    machine->path, machine->bootstrap_cpu);
-		machine->main_console_handle = (size_t)device_add(machine, tmpstr);
-
-		break;
-
-	case 53:
-		strlcat(machineName, " (Origin 350)",
-		    MACHINE_NAME_MAXBUF);
-
-		/*
-		 *  According to http://kumba.drachentekh.net/xml/myguide.html
-		 *  Origin 350, Tezro IP53 R16000
-		 */
-		break;
-
-	default:
-		fatal("unimplemented SGI machine type IP%i\n",
-		    machine->machine_subtype);
-		exit(1);
-	}
-
-	if (!machine->prom_emulation)
-		return;
-
-	arcbios_init(machine, arc_wordlen == sizeof(uint64_t), sgi_ram_offset,
-	    eaddr_string, macaddr);
-}
-
-
-MACHINE_DEFAULT_CPU(sgi)
-{
-	if (machine->machine_subtype <= 12)
-	        machine->cpu_name = strdup("R3000");
-	if (machine->cpu_name == NULL && machine->machine_subtype == 35)
-	        machine->cpu_name = strdup("R12000");
-	if (machine->cpu_name == NULL && (machine->machine_subtype == 25 ||
-	    machine->machine_subtype == 27 || machine->machine_subtype == 28 ||
-	    machine->machine_subtype == 30 || machine->machine_subtype == 32))
-	        machine->cpu_name = strdup("R10000");
-	if (machine->cpu_name == NULL && (machine->machine_subtype == 21 ||
-	    machine->machine_subtype == 26))
-	        machine->cpu_name = strdup("R8000");
-	if (machine->cpu_name == NULL && machine->machine_subtype == 24)
-	        machine->cpu_name = strdup("R5000");
-                        
-	/*  Other SGIs should probably work with
-	    R4000, R4400 or R5000 or similar:  */
-	if (machine->cpu_name == NULL)
-	        machine->cpu_name = strdup("R4400");
-}
-
-
-MACHINE_DEFAULT_RAM(sgi)
-{
-	// Self-compilation fails with OpenBSD/sgi 6.3 with as low as 128 MB
-	// RAM, so 256 would be better. But my O2 has 128 MB, so this is kept
-	// as 128 to simplify comparison between the real machine and the
-	// emulator.
-	machine->physical_ram_in_mb = 128;
-}
-
-
-MACHINE_REGISTER(sgi)
-{
-	MR_DEFAULT(sgi, "SGI", ARCH_MIPS, MACHINE_SGI);
-
-	me->set_default_ram = machine_default_ram_sgi;
-
-	machine_entry_add_alias(me, "silicon graphics");
-	machine_entry_add_alias(me, "sgi");
-
-	machine_entry_add_subtype(me, "IP12", 12, "ip12", NULL);
-
-	machine_entry_add_subtype(me, "IP19", 19, "ip19", NULL);
-
-	machine_entry_add_subtype(me, "IP20", 20, "ip20", NULL);
-
-	machine_entry_add_subtype(me, "IP22", 22, "ip22", "indy", NULL);
-
-	machine_entry_add_subtype(me, "IP24", 24, "ip24", NULL);
-
-	machine_entry_add_subtype(me, "IP27", 27,
-	    "ip27", "origin 200", "origin 2000", NULL);
-
-	machine_entry_add_subtype(me, "IP28", 28, "ip28", NULL);
-
-	machine_entry_add_subtype(me, "IP30", 30, "ip30", "octane", NULL);
-
-	machine_entry_add_subtype(me, "IP32", 32, "ip32", "o2", NULL); 
-
-	machine_entry_add_subtype(me, "IP35", 35, "ip35", NULL); 
-}
-
diff -Nru gxemul-0.6.2/src/machines/machine_test.c gxemul-0.7.0+dfsg/src/machines/machine_test.c
--- gxemul-0.6.2/src/machines/machine_test.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_test.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,488 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: Various test machines
+ *
+ *  Generally, the machines are as follows:
+ *
+ *	bareXYZ:	A bare machine using an XYZ processor.
+ *
+ *	testXYZ:	A machine with an XYZ processor, and some experimental
+ *			devices connected to it.
+ *
+ *  The experimental devices in the test machines are:
+ *
+ *	cons		A serial I/O console device.
+ *	disk		A device for reading/writing (emulated) disk sectors.
+ *	ether		An ethernet device, for sending/receiving ethernet
+ *			frames on an emulated network.
+ *	fb		Framebuffer (24-bit RGB per pixel).
+ *	irqc		A generic interrupt controller.
+ *	mp		A multiprocessor controller.
+ *	rtc		A real-time clock device.
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/sh4_exception.h"
+
+#include "testmachine/dev_cons.h"
+#include "testmachine/dev_disk.h"
+#include "testmachine/dev_ether.h"
+#include "testmachine/dev_fb.h"
+#include "testmachine/dev_irqc.h"
+#include "testmachine/dev_mp.h"
+#include "testmachine/dev_rtc.h"
+
+
+/*
+ *  default_test():
+ *
+ *  Initializes devices for most test machines. (Note: MIPS is different,
+ *  because of legacy reasons.)
+ */
+static void default_test(struct machine *machine, struct cpu *cpu)
+{
+	char tmpstr[2000];
+	char base_irq[1000];
+	char end_of_base_irq[50];
+
+	/*
+	 *  First add the interrupt controller. Most processor architectures
+	 *  in GXemul have only 1 interrupt pin on the CPU, and it is simply
+	 *  called "machine[y].cpu[z]".
+	 *
+	 *  MIPS is an exception, dealt with in a separate setup function.
+	 *  ARM and SH are dealt with here.
+	 */
+
+	switch (cpu->cpu_family->arch) {
+
+	case ARCH_ARM:
+		snprintf(end_of_base_irq, sizeof(end_of_base_irq), ".irq");
+		break;
+
+	case ARCH_SH:
+		snprintf(end_of_base_irq, sizeof(end_of_base_irq),
+		    ".irq[0x%x]", SH4_INTEVT_IRQ15);
+		break;
+
+	default:
+		end_of_base_irq[0] = '\0';
+	}
+
+	snprintf(base_irq, sizeof(base_irq), "%s.cpu[%i]%s",
+	    machine->path, machine->bootstrap_cpu, end_of_base_irq);
+
+	snprintf(tmpstr, sizeof(tmpstr), "irqc addr=0x%" PRIx64" irq=%s",
+	    (uint64_t) DEV_IRQC_ADDRESS, base_irq);
+	device_add(machine, tmpstr);
+
+
+	/*  Now, add the other devices:  */
+
+	snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%" PRIx64
+	    " irq=%s.irqc.2 in_use=%i",
+	    (uint64_t) DEV_CONS_ADDRESS, base_irq, cpu->cpu_family->arch != ARCH_SH);
+	machine->main_console_handle = (size_t)device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%" PRIx64" irq=%s%sirqc.6",
+	    (uint64_t) DEV_MP_ADDRESS,
+	    end_of_base_irq[0]? end_of_base_irq + 1 : "",
+	    end_of_base_irq[0]? "." : "");
+	device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%" PRIx64,
+	    (uint64_t) DEV_FBCTRL_ADDRESS);
+	device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%" PRIx64,
+	    (uint64_t) DEV_DISK_ADDRESS);
+	device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%" PRIx64" irq=%s.irqc.3",
+	    (uint64_t) DEV_ETHER_ADDRESS, base_irq);
+	device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%" PRIx64" irq=%s.irqc.4",
+	    (uint64_t) DEV_RTC_ADDRESS, base_irq);
+	device_add(machine, tmpstr);
+}
+
+
+MACHINE_SETUP(barearm)
+{
+	machine->machine_name = strdup("Generic \"bare\" ARM machine");
+
+#if 1
+	// An experiment with running a particular firmware image on a device;
+	// move some other place when/if it works?
+	cpu->byte_order = EMUL_BIG_ENDIAN;
+
+	dev_ram_init(machine, 0xa0000000, 128 * 1048576, DEV_RAM_MIRROR
+		| DEV_RAM_MIGHT_POINT_TO_DEVICES, 0x00000000, "ram_mirror");
+#endif
+}
+
+
+MACHINE_SETUP(testarm)
+{
+	machine->machine_name = strdup("ARM test machine");
+
+	default_test(machine, cpu);
+
+	/*
+	 *  Place a tiny stub at end of memory, and set the link register to
+	 *  point to it. This stub halts the machine (making it easy to try
+	 *  out simple stand-alone C functions).
+	 */
+	cpu->cd.arm.r[ARM_SP] = machine->physical_ram_in_mb * 1048576 - 4096;
+	cpu->cd.arm.r[ARM_LR] = cpu->cd.arm.r[ARM_SP] + 32;
+	store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 0, 0xe3a00201);
+	store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 4, 0xe5c00010);
+	store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 8, 0xeafffffe);
+}
+
+
+MACHINE_DEFAULT_CPU(barearm)
+{
+	machine->cpu_name = strdup("SA1110");
+}
+
+
+MACHINE_DEFAULT_CPU(testarm)
+{
+	machine->cpu_name = strdup("SA1110");
+}
+
+
+MACHINE_REGISTER(barearm)
+{
+	MR_DEFAULT(barearm, "Generic \"bare\" ARM machine", MACHINE_BAREARM);
+
+	machine_entry_add_alias(me, "barearm");
+}
+
+
+MACHINE_REGISTER(testarm)
+{
+	MR_DEFAULT(testarm, "Test-machine for ARM", MACHINE_TESTARM);
+
+	machine_entry_add_alias(me, "testarm");
+}
+
+
+
+MACHINE_SETUP(barei960)
+{
+	machine->machine_name = strdup("Generic \"bare\" i960 machine");
+}
+
+
+MACHINE_DEFAULT_CPU(barei960)
+{
+	machine->cpu_name = strdup("i960CA");
+}
+
+
+MACHINE_REGISTER(barei960)
+{
+	MR_DEFAULT(barei960, "Generic \"bare\" i960 machine", MACHINE_BAREI960);
+
+	machine_entry_add_alias(me, "barei960");
+}
+
+
+MACHINE_SETUP(barem88k)
+{
+	machine->machine_name = strdup("Generic \"bare\" M88K machine");
+}
+
+
+MACHINE_SETUP(testm88k)
+{
+	machine->machine_name = strdup("M88K test machine");
+
+	default_test(machine, cpu);
+}
+
+
+MACHINE_DEFAULT_CPU(barem88k)
+{
+	machine->cpu_name = strdup("88110");
+}
+
+
+MACHINE_DEFAULT_CPU(testm88k)
+{
+	machine->cpu_name = strdup("88110");
+}
+
+
+MACHINE_REGISTER(barem88k)
+{
+	MR_DEFAULT(barem88k, "Generic \"bare\" M88K machine",
+	    MACHINE_BAREM88K);
+
+	machine_entry_add_alias(me, "barem88k");
+}
+
+
+MACHINE_REGISTER(testm88k)
+{
+	MR_DEFAULT(testm88k, "Test-machine for M88K",
+	    MACHINE_TESTM88K);
+
+	machine_entry_add_alias(me, "testm88k");
+}
+
+
+MACHINE_SETUP(baremips)
+{
+	machine->machine_name = strdup("Generic \"bare\" MIPS machine");
+	cpu->byte_order = EMUL_BIG_ENDIAN;
+}
+
+
+MACHINE_SETUP(testmips)
+{
+	/*
+	 *  A MIPS test machine. Originally, this was created as a way for
+	 *  me to test my master's thesis code; since then it has both
+	 *  evolved to support new things, and suffered bit rot so that it
+	 *  no longer can run my thesis code. Well, well...
+	 *
+	 *  IRQ map:
+	 *      7       CPU counter
+	 *      6       SMP IPIs
+	 *      5       not used yet
+	 *      4       rtc
+	 *      3       ethernet  
+	 *      2       serial console
+	 */
+
+	char tmpstr[300];
+
+	machine->machine_name = strdup("MIPS test machine");
+	cpu->byte_order = EMUL_BIG_ENDIAN;
+
+	snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%" PRIx64" irq=%s."
+	    "cpu[%i].2", (uint64_t) DEV_CONS_ADDRESS, machine->path,
+	    machine->bootstrap_cpu);
+	machine->main_console_handle = (size_t)device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%" PRIx64" irq=6",
+	    (uint64_t) DEV_MP_ADDRESS);
+	device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%" PRIx64,
+	    (uint64_t) DEV_FBCTRL_ADDRESS);
+	device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%" PRIx64,
+	    (uint64_t) DEV_DISK_ADDRESS);
+	device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%" PRIx64" irq=%s."
+	    "cpu[%i].3", (uint64_t) DEV_ETHER_ADDRESS, machine->path,
+	    machine->bootstrap_cpu);
+	device_add(machine, tmpstr);
+
+	snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%" PRIx64" irq=%s."
+	    "cpu[%i].4", (uint64_t) DEV_RTC_ADDRESS, machine->path,
+	    machine->bootstrap_cpu);
+	device_add(machine, tmpstr);
+}
+
+
+MACHINE_DEFAULT_CPU(baremips)
+{
+	machine->cpu_name = strdup("5KE");
+}
+
+
+MACHINE_DEFAULT_CPU(testmips)
+{
+	machine->cpu_name = strdup("5KE");
+}
+
+
+MACHINE_REGISTER(baremips)
+{
+	MR_DEFAULT(baremips, "Generic \"bare\" MIPS machine",
+	    MACHINE_BAREMIPS);
+
+	machine_entry_add_alias(me, "baremips");
+}
+
+
+MACHINE_REGISTER(testmips)
+{
+	MR_DEFAULT(testmips, "Test-machine for MIPS",
+	    MACHINE_TESTMIPS);
+
+	machine_entry_add_alias(me, "testmips");
+}
+
+
+MACHINE_SETUP(bareppc)
+{
+	machine->machine_name = strdup("Generic \"bare\" PPC machine");
+}
+
+
+MACHINE_SETUP(testppc)
+{
+	machine->machine_name = strdup("PPC test machine");
+
+	default_test(machine, cpu);
+}
+
+
+MACHINE_DEFAULT_CPU(bareppc)
+{
+	machine->cpu_name = strdup("PPC970");
+}
+
+
+MACHINE_DEFAULT_CPU(testppc)
+{
+	machine->cpu_name = strdup("PPC970");
+}
+
+
+MACHINE_REGISTER(bareppc)
+{
+	MR_DEFAULT(bareppc, "Generic \"bare\" PPC machine",
+	    MACHINE_BAREPPC);
+
+	machine_entry_add_alias(me, "bareppc");
+}
+
+
+MACHINE_REGISTER(testppc)
+{
+	MR_DEFAULT(testppc, "Test-machine for PPC", MACHINE_TESTPPC);
+
+	machine_entry_add_alias(me, "testppc");
+}
+
+
+MACHINE_SETUP(bareriscv)
+{
+	machine->machine_name = strdup("Generic \"bare\" RISC-V machine");
+}
+
+
+MACHINE_SETUP(testriscv)
+{
+	machine->machine_name = strdup("RISC-V test machine");
+
+	default_test(machine, cpu);
+}
+
+
+MACHINE_DEFAULT_CPU(bareriscv)
+{
+	machine->cpu_name = strdup("RV64GC");
+}
+
+
+MACHINE_DEFAULT_CPU(testriscv)
+{
+	machine->cpu_name = strdup("RV64GC");
+}
+
+
+MACHINE_REGISTER(bareriscv)
+{
+	MR_DEFAULT(bareriscv, "Generic \"bare\" RISC-V machine", MACHINE_BARERISCV);
+
+	machine_entry_add_alias(me, "bareriscv");
+}
+
+
+MACHINE_REGISTER(testriscv)
+{
+	MR_DEFAULT(testriscv, "Test-machine for RISC-V", MACHINE_TESTRISCV);
+
+	machine_entry_add_alias(me, "testriscv");
+}
+
+
+MACHINE_SETUP(baresh)
+{
+	machine->machine_name = strdup("Generic \"bare\" SH machine");
+}
+
+
+MACHINE_SETUP(testsh)
+{
+	machine->machine_name = strdup("SH test machine");
+
+	default_test(machine, cpu);
+}
+
+
+MACHINE_DEFAULT_CPU(baresh)
+{
+	machine->cpu_name = strdup("SH7750");
+}
+
+
+MACHINE_DEFAULT_CPU(testsh)
+{
+	machine->cpu_name = strdup("SH7750");
+}
+
+
+MACHINE_REGISTER(baresh)
+{
+	MR_DEFAULT(baresh, "Generic \"bare\" SH machine",
+	    MACHINE_BARESH);
+
+	machine_entry_add_alias(me, "baresh");
+}
+
+
+MACHINE_REGISTER(testsh)
+{
+	MR_DEFAULT(testsh, "Test-machine for SH", MACHINE_TESTSH);
+
+	machine_entry_add_alias(me, "testsh");
+}
+
+
+
diff -Nru gxemul-0.6.2/src/machines/machine_test.cc gxemul-0.7.0+dfsg/src/machines/machine_test.cc
--- gxemul-0.6.2/src/machines/machine_test.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_test.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,427 +0,0 @@
-/*
- *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: Various test machines
- *
- *  Generally, the machines are as follows:
- *
- *	bareXYZ:	A bare machine using an XYZ processor.
- *
- *	testXYZ:	A machine with an XYZ processor, and some experimental
- *			devices connected to it.
- *
- *  The experimental devices in the test machines are:
- *
- *	cons		A serial I/O console device.
- *	disk		A device for reading/writing (emulated) disk sectors.
- *	ether		An ethernet device, for sending/receiving ethernet
- *			frames on an emulated network.
- *	fb		Framebuffer (24-bit RGB per pixel).
- *	irqc		A generic interrupt controller.
- *	mp		A multiprocessor controller.
- *	rtc		A real-time clock device.
- */
-
-#include <stdio.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/sh4_exception.h"
-
-#include "testmachine/dev_cons.h"
-#include "testmachine/dev_disk.h"
-#include "testmachine/dev_ether.h"
-#include "testmachine/dev_fb.h"
-#include "testmachine/dev_irqc.h"
-#include "testmachine/dev_mp.h"
-#include "testmachine/dev_rtc.h"
-
-
-/*
- *  default_test():
- *
- *  Initializes devices for most test machines. (Note: MIPS is different,
- *  because of legacy reasons.)
- */
-static void default_test(struct machine *machine, struct cpu *cpu)
-{
-	char tmpstr[2000];
-	char base_irq[1000];
-	char end_of_base_irq[50];
-
-	/*
-	 *  First add the interrupt controller. Most processor architectures
-	 *  in GXemul have only 1 interrupt pin on the CPU, and it is simply
-	 *  called "machine[y].cpu[z]".
-	 *
-	 *  MIPS is an exception, dealt with in a separate setup function.
-	 *  ARM and SH are dealt with here.
-	 */
-
-	switch (machine->arch) {
-
-	case ARCH_ARM:
-		snprintf(end_of_base_irq, sizeof(end_of_base_irq), ".irq");
-		break;
-
-	case ARCH_SH:
-		snprintf(end_of_base_irq, sizeof(end_of_base_irq),
-		    ".irq[0x%x]", SH4_INTEVT_IRQ15);
-		break;
-
-	default:
-		end_of_base_irq[0] = '\0';
-	}
-
-	snprintf(base_irq, sizeof(base_irq), "%s.cpu[%i]%s",
-	    machine->path, machine->bootstrap_cpu, end_of_base_irq);
-
-	snprintf(tmpstr, sizeof(tmpstr), "irqc addr=0x%" PRIx64" irq=%s",
-	    (uint64_t) DEV_IRQC_ADDRESS, base_irq);
-	device_add(machine, tmpstr);
-
-
-	/*  Now, add the other devices:  */
-
-	snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%" PRIx64
-	    " irq=%s.irqc.2 in_use=%i",
-	    (uint64_t) DEV_CONS_ADDRESS, base_irq, machine->arch != ARCH_SH);
-	machine->main_console_handle = (size_t)device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%" PRIx64" irq=%s%sirqc.6",
-	    (uint64_t) DEV_MP_ADDRESS,
-	    end_of_base_irq[0]? end_of_base_irq + 1 : "",
-	    end_of_base_irq[0]? "." : "");
-	device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%" PRIx64,
-	    (uint64_t) DEV_FBCTRL_ADDRESS);
-	device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%" PRIx64,
-	    (uint64_t) DEV_DISK_ADDRESS);
-	device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%" PRIx64" irq=%s.irqc.3",
-	    (uint64_t) DEV_ETHER_ADDRESS, base_irq);
-	device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%" PRIx64" irq=%s.irqc.4",
-	    (uint64_t) DEV_RTC_ADDRESS, base_irq);
-	device_add(machine, tmpstr);
-}
-
-
-MACHINE_SETUP(barearm)
-{
-	machine->machine_name = strdup("Generic \"bare\" ARM machine");
-
-#if 1
-	// An experiment with running a particular firmware image on a device;
-	// move some other place when/if it works?
-	cpu->byte_order = EMUL_BIG_ENDIAN;
-
-	dev_ram_init(machine, 0xa0000000, 128 * 1048576, DEV_RAM_MIRROR
-		| DEV_RAM_MIGHT_POINT_TO_DEVICES, 0x00000000, "ram_mirror");
-#endif
-}
-
-
-MACHINE_SETUP(testarm)
-{
-	machine->machine_name = strdup("ARM test machine");
-
-	default_test(machine, cpu);
-
-	/*
-	 *  Place a tiny stub at end of memory, and set the link register to
-	 *  point to it. This stub halts the machine (making it easy to try
-	 *  out simple stand-alone C functions).
-	 */
-	cpu->cd.arm.r[ARM_SP] = machine->physical_ram_in_mb * 1048576 - 4096;
-	cpu->cd.arm.r[ARM_LR] = cpu->cd.arm.r[ARM_SP] + 32;
-	store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 0, 0xe3a00201);
-	store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 4, 0xe5c00010);
-	store_32bit_word(cpu, cpu->cd.arm.r[ARM_LR] + 8, 0xeafffffe);
-}
-
-
-MACHINE_DEFAULT_CPU(barearm)
-{
-	machine->cpu_name = strdup("SA1110");
-}
-
-
-MACHINE_DEFAULT_CPU(testarm)
-{
-	machine->cpu_name = strdup("SA1110");
-}
-
-
-MACHINE_REGISTER(barearm)
-{
-	MR_DEFAULT(barearm, "Generic \"bare\" ARM machine",
-	    ARCH_ARM, MACHINE_BAREARM);
-
-	machine_entry_add_alias(me, "barearm");
-}
-
-
-MACHINE_REGISTER(testarm)
-{
-	MR_DEFAULT(testarm, "Test-machine for ARM", ARCH_ARM, MACHINE_TESTARM);
-
-	machine_entry_add_alias(me, "testarm");
-}
-
-
-
-MACHINE_SETUP(barem88k)
-{
-	machine->machine_name = strdup("Generic \"bare\" M88K machine");
-}
-
-
-MACHINE_SETUP(oldtestm88k)
-{
-	machine->machine_name = strdup("M88K test machine");
-
-	default_test(machine, cpu);
-}
-
-
-MACHINE_DEFAULT_CPU(barem88k)
-{
-	machine->cpu_name = strdup("88110");
-}
-
-
-MACHINE_DEFAULT_CPU(oldtestm88k)
-{
-	machine->cpu_name = strdup("88110");
-}
-
-
-MACHINE_REGISTER(barem88k)
-{
-	MR_DEFAULT(barem88k, "Generic \"bare\" M88K machine",
-	    ARCH_M88K, MACHINE_BAREM88K);
-
-	machine_entry_add_alias(me, "barem88k");
-}
-
-
-MACHINE_REGISTER(oldtestm88k)
-{
-	MR_DEFAULT(oldtestm88k, "Test-machine for M88K",
-	    ARCH_M88K, MACHINE_TESTM88K);
-
-	machine_entry_add_alias(me, "oldtestm88k");
-}
-
-
-MACHINE_SETUP(baremips)
-{
-	machine->machine_name = strdup("Generic \"bare\" MIPS machine");
-	cpu->byte_order = EMUL_BIG_ENDIAN;
-}
-
-
-MACHINE_SETUP(testmips)
-{
-	/*
-	 *  A MIPS test machine. Originally, this was created as a way for
-	 *  me to test my master's thesis code; since then it has both
-	 *  evolved to support new things, and suffered bit rot so that it
-	 *  no longer can run my thesis code. Well, well...
-	 *
-	 *  IRQ map:
-	 *      7       CPU counter
-	 *      6       SMP IPIs
-	 *      5       not used yet
-	 *      4       rtc
-	 *      3       ethernet  
-	 *      2       serial console
-	 */
-
-	char tmpstr[300];
-
-	machine->machine_name = strdup("MIPS test machine");
-	cpu->byte_order = EMUL_BIG_ENDIAN;
-
-	snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%" PRIx64" irq=%s."
-	    "cpu[%i].2", (uint64_t) DEV_CONS_ADDRESS, machine->path,
-	    machine->bootstrap_cpu);
-	machine->main_console_handle = (size_t)device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%" PRIx64" irq=6",
-	    (uint64_t) DEV_MP_ADDRESS);
-	device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%" PRIx64,
-	    (uint64_t) DEV_FBCTRL_ADDRESS);
-	device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%" PRIx64,
-	    (uint64_t) DEV_DISK_ADDRESS);
-	device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%" PRIx64" irq=%s."
-	    "cpu[%i].3", (uint64_t) DEV_ETHER_ADDRESS, machine->path,
-	    machine->bootstrap_cpu);
-	device_add(machine, tmpstr);
-
-	snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%" PRIx64" irq=%s."
-	    "cpu[%i].4", (uint64_t) DEV_RTC_ADDRESS, machine->path,
-	    machine->bootstrap_cpu);
-	device_add(machine, tmpstr);
-}
-
-
-MACHINE_DEFAULT_CPU(baremips)
-{
-	machine->cpu_name = strdup("5KE");
-}
-
-
-MACHINE_DEFAULT_CPU(testmips)
-{
-	machine->cpu_name = strdup("5KE");
-}
-
-
-MACHINE_REGISTER(baremips)
-{
-	MR_DEFAULT(baremips, "Generic \"bare\" MIPS machine",
-	    ARCH_MIPS, MACHINE_BAREMIPS);
-
-	machine_entry_add_alias(me, "baremips");
-}
-
-
-MACHINE_REGISTER(testmips)
-{
-	MR_DEFAULT(testmips, "Test-machine for MIPS",
-	    ARCH_MIPS, MACHINE_TESTMIPS);
-
-	machine_entry_add_alias(me, "testmips");
-}
-
-
-MACHINE_SETUP(bareppc)
-{
-	machine->machine_name = strdup("Generic \"bare\" PPC machine");
-}
-
-
-MACHINE_SETUP(testppc)
-{
-	machine->machine_name = strdup("PPC test machine");
-
-	default_test(machine, cpu);
-}
-
-
-MACHINE_DEFAULT_CPU(bareppc)
-{
-	machine->cpu_name = strdup("PPC970");
-}
-
-
-MACHINE_DEFAULT_CPU(testppc)
-{
-	machine->cpu_name = strdup("PPC970");
-}
-
-
-MACHINE_REGISTER(bareppc)
-{
-	MR_DEFAULT(bareppc, "Generic \"bare\" PPC machine",
-	    ARCH_PPC, MACHINE_BAREPPC);
-
-	machine_entry_add_alias(me, "bareppc");
-}
-
-
-MACHINE_REGISTER(testppc)
-{
-	MR_DEFAULT(testppc, "Test-machine for PPC", ARCH_PPC, MACHINE_TESTPPC);
-
-	machine_entry_add_alias(me, "testppc");
-}
-
-
-MACHINE_SETUP(baresh)
-{
-	machine->machine_name = strdup("Generic \"bare\" SH machine");
-}
-
-
-MACHINE_SETUP(testsh)
-{
-	machine->machine_name = strdup("SH test machine");
-
-	default_test(machine, cpu);
-}
-
-
-MACHINE_DEFAULT_CPU(baresh)
-{
-	machine->cpu_name = strdup("SH7750");
-}
-
-
-MACHINE_DEFAULT_CPU(testsh)
-{
-	machine->cpu_name = strdup("SH7750");
-}
-
-
-MACHINE_REGISTER(baresh)
-{
-	MR_DEFAULT(baresh, "Generic \"bare\" SH machine",
-	    ARCH_SH, MACHINE_BARESH);
-
-	machine_entry_add_alias(me, "baresh");
-}
-
-
-MACHINE_REGISTER(testsh)
-{
-	MR_DEFAULT(testsh, "Test-machine for SH", ARCH_SH, MACHINE_TESTSH);
-
-	machine_entry_add_alias(me, "testsh");
-}
-
-
-
diff -Nru gxemul-0.6.2/src/machines/machine_vocore.c gxemul-0.7.0+dfsg/src/machines/machine_vocore.c
--- gxemul-0.6.2/src/machines/machine_vocore.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_vocore.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,97 @@
+/*
+ *  Copyright (C) 2018-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *   
+ *
+ *  COMMENT: VoCore
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+
+MACHINE_SETUP(vocore)
+{
+	machine->machine_name = strdup("VoCore");
+
+	machine->emulated_hz = 360000000;
+
+	/*  Some devices mentioned in the Linux kernel (as shown using strings):
+
+		i/palmbus@10000000/spi@b00
+		n/palmbus@10000000/spi@b40
+		s/palmbus@10000000/uartlite@c00
+		palmbus@10000000
+		timer@100
+		ethernet@10100000
+		esw@10110000
+		wmac@10180000
+		ehci@101c0000
+		ohci@101c1000
+	*/
+
+	device_add(machine, "palmbus addr=0x10000000");
+
+	if (!machine->prom_emulation)
+		return;
+
+	// TODO: uboot emulation?
+}
+
+
+MACHINE_DEFAULT_CPU(vocore)
+{
+	// According to http://vocore.io/v1d.html: RT5350, 360 MHz, MIPS 24K
+	// According to Linux booting on my real machine:
+	//	CPU revision is: 0001964c (MIPS 24KEc)
+	//	Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
+	//	Primary data cache 16kB, 4-way, VIPT, no aliases, linesize 32 bytes
+	machine->cpu_name = strdup("24KEc");
+}
+
+
+MACHINE_DEFAULT_RAM(vocore)
+{
+	machine->physical_ram_in_mb = 32;
+}
+
+
+MACHINE_REGISTER(vocore)
+{
+	MR_DEFAULT(vocore, "VoCore", MACHINE_VOCORE);
+
+	machine_entry_add_alias(me, "vocore");
+
+	me->set_default_ram = machine_default_ram_vocore;
+}
+
diff -Nru gxemul-0.6.2/src/machines/machine_vocore.cc gxemul-0.7.0+dfsg/src/machines/machine_vocore.cc
--- gxemul-0.6.2/src/machines/machine_vocore.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/machine_vocore.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,97 +0,0 @@
-/*
- *  Copyright (C) 2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *   
- *
- *  COMMENT: VoCore
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-MACHINE_SETUP(vocore)
-{
-	machine->machine_name = strdup("VoCore");
-
-	machine->emulated_hz = 360000000;
-
-	/*  Some devices mentioned in the Linux kernel (as shown using strings):
-
-		i/palmbus@10000000/spi@b00
-		n/palmbus@10000000/spi@b40
-		s/palmbus@10000000/uartlite@c00
-		palmbus@10000000
-		timer@100
-		ethernet@10100000
-		esw@10110000
-		wmac@10180000
-		ehci@101c0000
-		ohci@101c1000
-	*/
-
-	device_add(machine, "palmbus addr=0x10000000");
-
-	if (!machine->prom_emulation)
-		return;
-
-	// TODO: uboot emulation?
-}
-
-
-MACHINE_DEFAULT_CPU(vocore)
-{
-	// According to http://vocore.io/v1d.html: RT5350, 360 MHz, MIPS 24K
-	// According to Linux booting on my real machine:
-	//	CPU revision is: 0001964c (MIPS 24KEc)
-	//	Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
-	//	Primary data cache 16kB, 4-way, VIPT, no aliases, linesize 32 bytes
-	machine->cpu_name = strdup("24KEc");
-}
-
-
-MACHINE_DEFAULT_RAM(vocore)
-{
-	machine->physical_ram_in_mb = 32;
-}
-
-
-MACHINE_REGISTER(vocore)
-{
-	MR_DEFAULT(vocore, "VoCore", ARCH_MIPS, MACHINE_VOCORE);
-
-	machine_entry_add_alias(me, "vocore");
-
-	me->set_default_ram = machine_default_ram_vocore;
-}
-
diff -Nru gxemul-0.6.2/src/machines/makeautomachine.sh gxemul-0.7.0+dfsg/src/machines/makeautomachine.sh
--- gxemul-0.6.2/src/machines/makeautomachine.sh	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/makeautomachine.sh	2021-11-27 09:42:23.000000000 +0000
@@ -27,17 +27,17 @@
 #  SUCH DAMAGE.
 
 
-printf "Generating automachine.cc... "
+printf "Generating automachine.c... "
 
-rm -f automachine.cc
+rm -f automachine.c
 
-printf "/*\n *  DO NOT EDIT. AUTOMATICALLY CREATED\n */\n\n" >> automachine.cc
+printf "/*\n *  DO NOT EDIT. AUTOMATICALLY CREATED\n */\n\n" >> automachine.c
 
-cat automachine_head.cc >> automachine.cc
+cat automachine_head.c >> automachine.c
 
 printf "3"
 rm -f .index
-for a in *.cc; do
+for a in *.c; do
 	B=`grep COMMENT $a`
 	if [ z"$B" != z ]; then
 		printf "$a " >> .index
@@ -46,29 +46,29 @@
 done
 
 printf "2"
-for a in machine_*.cc; do
+for a in machine_*.c; do
 	B=`grep MACHINE_REGISTER $a`
 	if [ z"$B" != z ]; then
 		C=`grep MACHINE_REGISTER $a | cut -d \( -f 2|cut -d \) -f 1`
 		for B in $C; do
-			printf "void machine_register_$B(void);\n" >> automachine.cc
+			printf "void machine_register_$B(void);\n" >> automachine.c
 		done
 	fi
 done
 
-cat automachine_middle.cc >> automachine.cc
+cat automachine_middle.c >> automachine.c
 
 printf "1"
-for a in machine_*.cc; do
+for a in machine_*.c; do
 	B=`grep MACHINE_REGISTER $a`
 	if [ z"$B" != z ]; then
 		C=`grep MACHINE_REGISTER $a | cut -d \( -f 2|cut -d \) -f 1`
 		for B in $C; do
-			printf "\tmachine_register_$B();\n" >> automachine.cc
+			printf "\tmachine_register_$B();\n" >> automachine.c
 		done
 	fi
 done
 
-cat automachine_tail.cc >> automachine.cc
+cat automachine_tail.c >> automachine.c
 
 printf " done\n"
diff -Nru gxemul-0.6.2/src/machines/Makefile.skel gxemul-0.7.0+dfsg/src/machines/Makefile.skel
--- gxemul-0.6.2/src/machines/Makefile.skel	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -2,11 +2,13 @@
 # Makefile for GXemul machines
 #
 
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
+CFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
 
 OBJS=	machine.o machine_algor.o machine_alpha.o \
 	machine_androidarm.o machine_arc.o \
-	machine_cats.o machine_cobalt.o machine_dreamcast.o machine_evbmips.o \
+	machine_cats.o machine_cobalt.o machine_cyclonevh.o \
+	machine_dreamcast.o machine_evbmips.o \
+	machine_hp700rx.o \
 	machine_hpcarm.o machine_hpcmips.o machine_hpcsh.o machine_iq80321.o \
 	machine_iyonix.o machine_landisk.o machine_luna88k.o machine_macppc.o \
 	machine_mvme88k.o machine_mvmeppc.o machine_netwinder.o \
@@ -17,7 +19,7 @@
 	$(MAKE) objs
 	$(MAKE) automachine.o
 
-automachine.cc: $(OBJS) automachine_head.cc automachine_middle.cc automachine_tail.cc makeautomachine.sh
+automachine.c: $(OBJS) automachine_head.c automachine_middle.c automachine_tail.c makeautomachine.sh
 	./makeautomachine.sh
 
 objs: $(OBJS)
@@ -27,7 +29,7 @@
 
 clean:
 	rm -f $(OBJS) *core
-	rm -f automachine.cc automachine.o
+	rm -f automachine.c automachine.o
 
 clean_all: clean
 	rm -f Makefile
diff -Nru gxemul-0.6.2/src/machines/README gxemul-0.7.0+dfsg/src/machines/README
--- gxemul-0.6.2/src/machines/README	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/machines/README	2021-11-27 09:42:23.000000000 +0000
@@ -1,5 +1,5 @@
-How to add new machine types to GXemul (old framework)
-------------------------------------------------------
+How to add new machine types to GXemul
+--------------------------------------
 
 The easiest way is to simply copy an existing machine (e.g. machine_landisk.c)
 into whatever you want the new machine to be called (machine_foo.c), update
diff -Nru gxemul-0.6.2/src/main/Checksum.cc gxemul-0.7.0+dfsg/src/main/Checksum.cc
--- gxemul-0.6.2/src/main/Checksum.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/Checksum.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,220 +0,0 @@
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "Checksum.h"
-
-
-Checksum::Checksum()
-	: m_value(0)
-{
-}
-
-
-uint64_t Checksum::Value() const
-{
-	return m_value;
-}
-
-
-void Checksum::Add(uint64_t x)
-{
-	m_value += x * (((uint64_t)0xc151429 << 32) | 0x517851bf);
-	m_value ^= (((uint64_t)0x9183bfec << 32) | 0x01921947);
-}
-
-
-void Checksum::Add(const string& str)
-{
-	size_t n = str.length();
-	Add(10000 + n);
-	
-	for (size_t i=0; i<n; ++i)
-		Add(str[i]);
-}
-
-
-bool Checksum::operator == (const Checksum& other) const
-{
-	return m_value == other.m_value;
-}
-
-
-bool Checksum::operator != (const Checksum& other) const
-{
-	return m_value != other.m_value;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_Checksum_DefaultValue()
-{
-	Checksum checksum;
-
-	UnitTest::Assert("value should initially be zero",
-	    checksum.Value() == 0);
-}
-
-static void Test_Checksum_Add()
-{
-	Checksum checksum;
-
-	checksum.Add(123);
-	uint64_t v1 = checksum.Value();
-	
-	checksum.Add(123);
-	uint64_t v2 = checksum.Value();
-
-	UnitTest::Assert("v1 should be non-zero", v1 != 0);
-	UnitTest::Assert("v2 should be non-zero", v2 != 0);
-	UnitTest::Assert("v1 and v2 should differ", v1 != v2);
-}
-
-static void Test_Checksum_SameChecksum()
-{
-	Checksum checksumA;
-	Checksum checksumB;
-
-	checksumA.Add("testing");
-	checksumB.Add("testing");
-
-	UnitTest::Assert("checksums should be the same",
-	    checksumA.Value() == checksumB.Value());
-}
-
-static void Test_Checksum_OrderIsSignificant_Numeric()
-{
-	Checksum checksumA;
-	Checksum checksumB;
-
-	checksumA.Add(123);
-	checksumA.Add(234);
-	uint64_t valueA = checksumA.Value();
-	
-	checksumB.Add(234);
-	checksumB.Add(123);
-	uint64_t valueB = checksumB.Value();
-
-	UnitTest::Assert("valueA and valueB should differ", valueA != valueB);
-}
-
-static void Test_Checksum_OrderIsSignificant_String()
-{
-	Checksum checksumA;
-	Checksum checksumB;
-
-	checksumA.Add("123");
-	checksumA.Add("234");
-	uint64_t valueA = checksumA.Value();
-	
-	checksumB.Add("234");
-	checksumB.Add("123");
-	uint64_t valueB = checksumB.Value();
-
-	UnitTest::Assert("valueA and valueB should differ", valueA != valueB);
-}
-
-static void Test_Checksum_OrderIsSignificant_String_1()
-{
-	Checksum checksumA;
-	Checksum checksumB;
-
-	checksumA.Add("abcdef");
-	uint64_t valueA = checksumA.Value();
-	
-	checksumB.Add("abdcef");
-	uint64_t valueB = checksumB.Value();
-
-	UnitTest::Assert("valueA and valueB should differ", valueA != valueB);
-}
-
-static void Test_Checksum_OrderIsSignificant_String_2()
-{
-	Checksum checksumA;
-	Checksum checksumB;
-
-	checksumA.Add("hello ");
-	checksumA.Add("world");
-	uint64_t valueA = checksumA.Value();
-	
-	checksumB.Add("hello");
-	checksumB.Add(" world");
-	uint64_t valueB = checksumB.Value();
-
-	UnitTest::Assert("valueA and valueB should differ", valueA != valueB);
-}
-
-static void Test_Checksum_OrderIsSignificant_String_3()
-{
-	Checksum checksumA;
-	Checksum checksumB;
-
-	checksumA.Add("string x \"modified\"\n");
-	checksumA.Add("string y \"value 2\"\n");
-	checksumA.Add("string x \"value\\nhello\"\n");
-	uint64_t valueA = checksumA.Value();
-
-	checksumB.Add("string x \"value 1\"\n");
-	checksumB.Add("string y \"value 2\"\n");
-	checksumB.Add("string x \"value\\nhello\"\n");
-	uint64_t valueB = checksumB.Value();
-
-	UnitTest::Assert("valueA and valueB should differ", valueA != valueB);
-}
-
-static void Test_Checksum_String_Concatenation()
-{
-	Checksum checksumA;
-	Checksum checksumB;
-
-	checksumA.Add("hello");
-	checksumA.Add(" world");
-	uint64_t valueA = checksumA.Value();
-	
-	checksumB.Add("hello world");
-	uint64_t valueB = checksumB.Value();
-
-	UnitTest::Assert("valueA and valueB should differ", valueA != valueB);
-}
-
-UNITTESTS(Checksum)
-{
-	UNITTEST(Test_Checksum_DefaultValue);
-	UNITTEST(Test_Checksum_Add);
-	UNITTEST(Test_Checksum_SameChecksum);
-	UNITTEST(Test_Checksum_OrderIsSignificant_Numeric);
-	UNITTEST(Test_Checksum_OrderIsSignificant_String);
-	UNITTEST(Test_Checksum_OrderIsSignificant_String_1);
-	UNITTEST(Test_Checksum_OrderIsSignificant_String_2);
-	UNITTEST(Test_Checksum_OrderIsSignificant_String_3);
-	UNITTEST(Test_Checksum_String_Concatenation);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/Command.cc gxemul-0.7.0+dfsg/src/main/Command.cc
--- gxemul-0.6.2/src/main/Command.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/Command.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,110 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "Command.h"
-#include "GXemul.h"
-
-
-Command::Command(const string& name, const string& argumentFormat)
-	: m_name(name)
-	, m_argumentFormat(argumentFormat)
-{
-}
-
-
-Command::~Command()
-{
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-/**
- * \brief A dummy Command, for unit testing purposes
- */
-class DummyCommand
-	: public Command
-{
-public:
-	DummyCommand(int& valueRef)
-		: Command("dummycommand", "[args]")
-		, m_value(valueRef)
-	{
-	}
-
-	~DummyCommand()
-	{
-	}
-
-	bool Execute(GXemul& gxemul, const vector<string>& arguments)
-	{
-		m_value ++;
-		return true;
-	}
-
-	string GetShortDescription() const
-	{
-		return "A dummy command used for unit testing.";
-	}
-
-	string GetLongDescription() const
-	{
-		return "This is just a dummy command used for unit testing.";
-	}
-
-private:
-	int&	m_value;
-};
-
-static void Test_Command_DummyCommand()
-{
-	GXemul gxemulDummy;
-	vector<string> dummyArgs;
-	
-	int dummyInt = 0;
-	refcount_ptr<Command> cmd = new DummyCommand(dummyInt);
-
-	dummyInt = 42;
-
-	UnitTest::Assert("dummyInt should initially be 42", dummyInt == 42);
-
-	UnitTest::Assert("command should have succeeded",
-	    cmd->Execute(gxemulDummy, dummyArgs));
-	
-	UnitTest::Assert("dummyInt should now be 43", dummyInt == 43);
-
-}
-
-UNITTESTS(Command)
-{
-	UNITTEST(Test_Command_DummyCommand);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/CommandInterpreter.cc gxemul-0.7.0+dfsg/src/main/CommandInterpreter.cc
--- gxemul-0.6.2/src/main/CommandInterpreter.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/CommandInterpreter.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,2019 +0,0 @@
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "assert.h"
-#include <iostream>
-
-#include "GXemul.h"
-#include "CommandInterpreter.h"
-
-// Built-in commands (autogenerated list by the configure script):
-#include "../../commands_h.h"
-
-
-CommandInterpreter::CommandInterpreter(GXemul* owner)
-	: m_GXemul(owner)
-	, m_currentCommandCursorPosition(0)
-	, m_inEscapeSequence(false)
-	, m_historyEntryToCopyFrom(0)
-	, m_commandHistoryInsertPosition(0)
-	, m_commandHistoryMaxSize(100)
-{
-	m_commandHistory.resize(m_commandHistoryMaxSize, "");
-
-	// It would be bad to run without a working GXemul instance.
-	assert(m_GXemul != NULL);
-
-	// Add the default built-in commands:
-	// (This list is autogenerated by the configure script.)
-#include "../../commands.h"
-}
-
-
-void CommandInterpreter::AddCommand(refcount_ptr<Command> command)
-{
-	m_commands[command->GetCommandName()] = command;
-}
-
-
-const Commands& CommandInterpreter::GetCommands() const
-{
-	return m_commands;
-}
-
-
-int CommandInterpreter::AddLineToCommandHistory(const string& command)
-{
-	if (command == "")
-		return m_commandHistoryInsertPosition;
-
-	size_t lastInsertedPosition =
-	    (m_commandHistoryInsertPosition - 1 + m_commandHistoryMaxSize)
-	    % m_commandHistoryMaxSize;
-
-	if (m_commandHistory[lastInsertedPosition] == command)
-		return m_commandHistoryInsertPosition;
-
-	m_commandHistory[m_commandHistoryInsertPosition ++] = command;
-	m_commandHistoryInsertPosition %= m_commandHistoryMaxSize;
-
-	return m_commandHistoryInsertPosition;
-}
-
-
-string CommandInterpreter::GetHistoryLine(int nStepsBack) const
-{
-	if (nStepsBack == 0)
-		return "";
-
-	int index = (m_commandHistoryInsertPosition - nStepsBack +
-	    m_commandHistoryMaxSize) % m_commandHistoryMaxSize;
-
-	return m_commandHistory[index];
-}
-
-
-bool CommandInterpreter::TabComplete(string& commandString,
-	size_t& cursorPosition, bool visibleShowAvailable)
-{
-	string wordToComplete;
-	bool firstWordOnLine = true;
-
-	size_t pos = cursorPosition;
-	while (pos > 0) {
-		pos --;
-		if (commandString[pos] == ' ')
-			break;
-		wordToComplete = commandString[pos] + wordToComplete;
-	}
-
-	while (pos > 0) {
-		pos --;
-		if (commandString[pos] != ' ') {
-			firstWordOnLine = false;
-			break;
-		}
-	}
-
-	bool completeCommands = firstWordOnLine;
-
-	if (wordToComplete == "") {
-		if (!visibleShowAvailable)
-			return false;
-
-		// Show all available words:
-
-		if (completeCommands) {
-			// All available commands:
-			vector<string> allCommands;
-			for (Commands::const_iterator it = m_commands.begin();
-			    it != m_commands.end(); ++it)
-				allCommands.push_back(it->first);
-		
-			ShowAvailableWords(allCommands);
-		}
-
-		ShowAvailableWords(m_GXemul->GetRootComponent()->
-		    FindPathByPartialMatch(""));
-
-		return false;
-	}
-
-	vector<string> matches;
-
-	matches = m_GXemul->GetRootComponent()->
-	    FindPathByPartialMatch(wordToComplete, true);
-
-	if (completeCommands) {
-		Commands::const_iterator it = m_commands.begin();
-		for (; it != m_commands.end(); ++it) {
-			const string& commandName = it->first;
-			if (commandName.substr(0, wordToComplete.length())
-			    == wordToComplete) {
-				matches.push_back(commandName);
-			}
-		}
-	}
-
-	if (matches.size() == 0)
-		return false;
-
-	string completedWord;
-
-	// Single match, or multiple matches?
-	if (matches.size() == 1) {
-		// Insert the rest of the command name into the input line:
-		completedWord = matches[0];
-	} else {
-		// Figure out the longest possible match, and add that:
-		size_t i, n = matches.size();
-		for (size_t pos2 = 0; ; pos2 ++) {
-			if (pos2 >= matches[0].length())
-				break;
-			stringchar ch = matches[0][pos2];
-			for (i=1; i<n; i++) {
-				if (matches[i][pos2] != ch)
-					break;
-			}
-			if (i == n)
-				completedWord += ch;
-			else
-				break;
-		}
-		
-		// Show available words, so the user knows what there
-		// is to choose from.
-		if (visibleShowAvailable)
-			ShowAvailableWords(matches);
-	}
-
-	// Erase the old (incomplete) word, and insert the completed word:
-	if (!completedWord.empty()) {
-		cursorPosition -= wordToComplete.length();
-		commandString.erase(cursorPosition, wordToComplete.length());	
-		commandString.insert(cursorPosition, completedWord);
-		cursorPosition += completedWord.length();
-	}
-
-	// Special case: If there was a single match, and we are at the end
-	// of the line, and this was a command, then add a space (" "). This
-	// behaviour feels better, and this is how other tab completors seems
-	// to work.
-	//
-	// NOTE: Don't add a space after component paths. Usually the user
-	// will want to type e.g. "cpu" + TAB, and get
-	// "root.machine0.mainbus0.cpu0" with no space, and then be able to
-	// add ".unassemble" or so manually.
-	if (matches.size() == 1 && cursorPosition == commandString.length()) {
-		bool isCommand = false;
-		Commands::const_iterator it = m_commands.begin();
-		for (; it != m_commands.end(); ++it) {
-			const string& commandName = it->first;
-			if (commandName == matches[0]) {
-				isCommand = true;
-				break;
-			}
-		}
-
-		if (isCommand) {
-			commandString += " ";
-			cursorPosition ++;
-		}
-	}
-
-	return matches.size() == 1;
-}
-
-
-bool CommandInterpreter::TabCompleteWithSubname(string& commandString,
-	size_t& cursorPosition, bool visibleShowAvailable)
-{
-	if (cursorPosition == 0)
-		return false;
-
-	int nStepsBack = 1;
-	size_t pos = cursorPosition - 1;
-
-	while (pos > 0 && commandString[pos] != '.') {
-		pos --;
-		nStepsBack ++;
-	}
-
-	if (pos == 0)
-		return false;
-
-	// Here, pos is the position of the dot:
-	//
-	//	cpu.u
-	//	   ^
-
-	bool success = TabComplete(commandString, pos, visibleShowAvailable);
-	if (!success)
-		return false;
-
-	// pos is now the new position of the dot:
-	//
-	//	root.machine0.mainbus0.cpu.u
-	//	                          ^
-
-	// Look up the component:
-	int startOfComponentName = pos;
-	while (startOfComponentName >= 0 &&
-	    commandString[startOfComponentName] != ' ')
-		-- startOfComponentName;
-
-	if (startOfComponentName < 0)
-		startOfComponentName = 0;
-
-	string componentName = commandString.substr(startOfComponentName,
-	    pos - startOfComponentName);
-
-	// std::cerr << "[" << componentName << "]\n";
-	refcount_ptr<Component> component = m_GXemul->GetRootComponent()->
-	    LookupPath(componentName);
-
-	cursorPosition = pos + nStepsBack;
-
-	if (component.IsNULL())
-		return false;
-
-	// Figure out the method or state name to expand:
-	size_t startOfMethodName = pos + 1;
-	size_t methodNameLen = 0;
-	while (startOfMethodName + methodNameLen < cursorPosition &&
-	    commandString[startOfMethodName+methodNameLen] != ' ')
-		methodNameLen ++;
-
-	string methodName = commandString.substr(startOfMethodName,
-	    methodNameLen);
-
-	// std::cerr << "{" << methodName << "}\n";
-
-	vector<string> names;
-	vector<string> matchingNames;
-	component->GetMethodNames(names);
-	component->GetVariableNames(names);
-	int nrOfMatches = 0;
-	if (methodName.length() != 0) {
-		for (size_t i=0; i<names.size(); ++i) {
-			if (names[i].substr(0, methodName.length()) ==
-			    methodName) {
-				++ nrOfMatches;
-				matchingNames.push_back(names[i]);
-			}
-		}
-	} else {
-		matchingNames = names;
-	}
-
-	if (matchingNames.size() == 0)
-		return false;
-
-	// Replace the short name with a match as long as possible, e.g.
-	// "memo" will be replaced by "memoryMapped", if names
-	// "memoryMappedAddr" and "memoryMappedSize" are available.
-	string longestPossibleMatch = "";
-	size_t i, n = matchingNames.size();
-	for (size_t pos2 = 0; ; pos2 ++) {
-		if (pos2 >= matchingNames[0].length())
-			break;
-		stringchar ch = matchingNames[0][pos2];
-		for (i=1; i<n; i++) {
-			if (matchingNames[i][pos2] != ch)
-				break;
-		}
-		if (i == n)
-			longestPossibleMatch += ch;
-		else
-			break;
-	}
-
-	commandString.replace(startOfMethodName, methodNameLen,
-	    longestPossibleMatch);
-	cursorPosition += longestPossibleMatch.length() - methodNameLen;
-
-	// A single match? Then we succeeded.
-	if (nrOfMatches == 1)
-		return true;
-
-	// Show available methods and variable names:		
-	if (visibleShowAvailable) {
-		vector<string> allNames;
-		vector<string> matchingNames2;
-		
-		component->GetMethodNames(allNames);
-		for (size_t j=0; j<allNames.size(); ++j) {
-			if (methodName.length() == 0 ||
-			    allNames[j].substr(0, methodName.length()) == methodName)
-				matchingNames2.push_back(allNames[j]);
-		}
-
-		if (matchingNames2.size() > 0) {
-			m_GXemul->GetUI()->ShowDebugMessage("\nMethods:");
-			ShowAvailableWords(matchingNames2);
-		}
-	}
-	if (visibleShowAvailable) {
-		vector<string> allNames;
-		vector<string> matchingNames2;
-		
-		component->GetVariableNames(allNames);
-		for (size_t j=0; j<allNames.size(); ++j) {
-			if (methodName.length() == 0 ||
-			    allNames[j].substr(0, methodName.length()) == methodName)
-				matchingNames2.push_back(allNames[j]);
-		}
-
-		if (matchingNames2.size() > 0) {
-			m_GXemul->GetUI()->ShowDebugMessage("\nVariables:");
-			ShowAvailableWords(matchingNames2);
-		}
-	}
-
-	return false;
-}
-
-
-bool CommandInterpreter::AddKey(stringchar key)
-{
-	if (m_inEscapeSequence) {
-		m_escapeSequence += key;
-
-		// Handle some common escape sequences, and convert
-		// them into simpler 1-byte keys/characters:
-
-		if (m_escapeSequence == "[C") {			// right
-			m_inEscapeSequence = false;
-			AddKey('\6');	// CTRL-F
-		} else if (m_escapeSequence == "[D") {		// left
-			m_inEscapeSequence = false;
-			AddKey('\2');	// CTRL-B
-		} else if (m_escapeSequence == "OH") {		// home
-			m_inEscapeSequence = false;
-			AddKey('\1');	// CTRL-A
-		} else if (m_escapeSequence == "[H") {		// home
-			m_inEscapeSequence = false;
-			AddKey('\1');	// CTRL-A
-		} else if (m_escapeSequence == "OF") {		// end
-			m_inEscapeSequence = false;
-			AddKey('\5');	// CTRL-E
-		} else if (m_escapeSequence == "[F") {		// end
-			m_inEscapeSequence = false;
-			AddKey('\5');	// CTRL-E
-		} else if (m_escapeSequence == "[A") {		// up
-			m_inEscapeSequence = false;
-			AddKey('\20');	// CTRL-P
-		} else if (m_escapeSequence == "[B") {		// down
-			m_inEscapeSequence = false;
-			AddKey('\16');	// CTRL-N
-		} else if (m_escapeSequence.length() > 2) {
-			// Let's bail out of escape sequence handling...
-			//
-			// Note: If you trace execution here for some key that
-			// you feel _should_ be handled, please send me a mail
-			// about it.
-			//
-			m_inEscapeSequence = false;
-			AddKey('?');
-		}
-		
-		return false;
-	}
-
-	switch (key) {
-
-	case '\0':
-		// Add nothing, just reshow/update the command buffer.
-		break;
-
-	case '\1':	// CTRL-A: move to start of line
-		m_currentCommandCursorPosition = 0;
-		break;
-
-	case '\2':	// CTRL-B: move back (left)
-		if (m_currentCommandCursorPosition > 0)
-			m_currentCommandCursorPosition --;
-		break;
-
-	case '\4':	// CTRL-D: remove the character to the right
-		if (m_currentCommandCursorPosition <
-		    m_currentCommandString.length())
-			m_currentCommandString.erase(
-			    m_currentCommandCursorPosition, 1);
-		break;
-
-	case '\5':	// CTRL-E: move to end of line
-		m_currentCommandCursorPosition =
-		    m_currentCommandString.length();
-		break;
-
-	case '\6':	// CTRL-F: move forward (right)
-		if (m_currentCommandCursorPosition <
-		    m_currentCommandString.length())
-			m_currentCommandCursorPosition ++;
-		break;
-
-	case '\13':	// CTRL-K: kill to end of line
-		ClearCurrentInputLineVisually();
-		m_currentCommandString.resize(m_currentCommandCursorPosition);
-		break;
-
-	case '\16':	// CTRL-N: next in history (down)
-		ClearCurrentInputLineVisually();
-
-		m_historyEntryToCopyFrom --;
-		if (m_historyEntryToCopyFrom < 0)
-			m_historyEntryToCopyFrom = 0;
-
-		m_currentCommandString =
-		    GetHistoryLine(m_historyEntryToCopyFrom);
-		m_currentCommandCursorPosition =
-		    m_currentCommandString.length();
-		break;
-
-	case '\20':	// CTRL-P: previous in history (up)
-		ClearCurrentInputLineVisually();
-
-		m_historyEntryToCopyFrom ++;
-		m_currentCommandString =
-		    GetHistoryLine(m_historyEntryToCopyFrom);
-
-		// We went too far? Then back down.
-		if (m_currentCommandString == "") {
-			m_historyEntryToCopyFrom --;
-			m_currentCommandString =
-			    GetHistoryLine(m_historyEntryToCopyFrom);
-		}
-		m_currentCommandCursorPosition =
-		    m_currentCommandString.length();
-		break;
-
-	case '\24':	// CTRL-T: show status
-		m_GXemul->GetUI()->ShowDebugMessage("\n");
-		RunCommand("status");
-		break;
-
-	case '\27':	// CTRL-W: remove current word (backspacing)
-		ClearCurrentInputLineVisually();
-
-		// 1. Remove any spaces left to the cursor.
-		while (m_currentCommandCursorPosition > 0) {
-			if (m_currentCommandString[
-			    m_currentCommandCursorPosition-1] == ' ') {
-				m_currentCommandCursorPosition --;
-				m_currentCommandString.erase(
-				    m_currentCommandCursorPosition, 1);
-			} else {
-				break;
-			}
-		}
-
-		// 2. Remove non-spaces left to the cusror, either until
-		//	the cursor is at position 0, or until there is a
-		//	space again.
-		while (m_currentCommandCursorPosition > 0) {
-			if (m_currentCommandString[
-			    m_currentCommandCursorPosition-1] != ' ') {
-				m_currentCommandCursorPosition --;
-				m_currentCommandString.erase(
-				    m_currentCommandCursorPosition, 1);
-			} else {
-				break;
-			}
-		}
-
-		break;
-
-	case '\177':	// ASCII 127 (octal 177) = del
-	case '\b':	// backspace
-		if (m_currentCommandCursorPosition > 0) {
-			m_currentCommandCursorPosition --;
-			m_currentCommandString.erase(
-			    m_currentCommandCursorPosition, 1);
-		}
-		break;
-
-	case '\33':
-		// Escape key handling:
-		m_inEscapeSequence = true;
-		m_escapeSequence = "";
-		break;
-
-	case '\t':
-		// Tab completion, with visible word hints:
-		{
-			bool success = TabComplete(m_currentCommandString,
-			    m_currentCommandCursorPosition, true);
-
-			// Attempt to expand component-name + "." + optional
-			// method or variable name, "cpu.u", if the first
-			// tab-completion failed.
-			if (!success) {
-				TabCompleteWithSubname(m_currentCommandString,
-				    m_currentCommandCursorPosition, true);
-			}
-		}
-		break;
-
-	case '\n':
-	case '\r':
-		// Newline executes the command, if it is non-empty:
-		m_GXemul->GetUI()->InputLineDone();
-
-		if (!m_currentCommandString.empty()) {
-			AddLineToCommandHistory(m_currentCommandString);
-			bool ignoredResult;
-			RunCommand(m_currentCommandString, &ignoredResult);
-			ClearCurrentCommandBuffer();
-		} else if (m_mayBeReexecuted != "") {
-			RunCommand(m_mayBeReexecuted);
-		}
-		break;
-
-	default:
-		// Most other keys just add/insert a character into the command
-		// string:
-		if (key >= ' ') {
-			m_currentCommandString.insert(
-			    m_currentCommandCursorPosition, 1, key);
-			m_currentCommandCursorPosition ++;
-		}
-	}
-
-	if (key != '\n' && key != '\r')
-		ReshowCurrentCommandBuffer();
-
-	// Return value is true for newline/cr, false otherwise:
-	return key == '\n' || key == '\r';
-}
-
-
-void CommandInterpreter::ShowAvailableWords(const vector<string>& words)
-{
-	m_GXemul->GetUI()->ShowDebugMessage("\n");
-
-	const size_t n = words.size();
-	size_t i;
-
-	// Find the longest word first:
-	size_t maxLen = 0;
-	for (i=0; i<n; ++i) {
-		size_t len = words[i].length();
-		if (len > maxLen)
-			maxLen = len;
-	}
-
-	maxLen += 4;
-
-	// Generate msg:
-	std::stringstream msg;
-	size_t lineLen = 0;
-	for (i=0; i<n; ++i) {
-		if (lineLen == 0)
-			msg << "  ";
-
-		size_t len = words[i].length();
-		msg << words[i];
-		lineLen += len;
-
-		for (size_t j=len; j<maxLen; j++) {
-			msg << " ";
-			lineLen ++;
-		}
-
-		if (lineLen >= 77 - maxLen || i == n-1) {
-			msg << "\n";
-			lineLen = 0;
-		}
-	}
-	
-	m_GXemul->GetUI()->ShowDebugMessage(msg.str());
-}
-
-
-void CommandInterpreter::ReshowCurrentCommandBuffer()
-{
-	m_GXemul->GetUI()->RedisplayInputLine(
-	    m_currentCommandString, m_currentCommandCursorPosition);
-}
-
-
-void CommandInterpreter::ClearCurrentInputLineVisually()
-{
-	string clearString = "";
-	clearString.insert((size_t)0, m_currentCommandString.length(), ' ');
-
-	m_GXemul->GetUI()->RedisplayInputLine(
-	    clearString, m_currentCommandCursorPosition);
-}
-
-
-void CommandInterpreter::ClearCurrentCommandBuffer()
-{
-	m_currentCommandString = "";
-	m_currentCommandCursorPosition = 0;
-	m_historyEntryToCopyFrom = 0;
-}
-
-
-static void SplitIntoWords(const string& commandOrig,
-	string& commandName, vector<string>& arguments)
-{
-	string command = commandOrig;
-
-	arguments.clear();
-	commandName = "";
-	size_t pos = 0;
-
-	// Surround '=' with white spaces, except when inside parentheses...
-	// NOTE/TODO: This will not be needed in the future (?), when a real
-	// expression evaluator has been [re]implemented.
-	int insideParenthesesCount = 0;
-	while (pos < command.length()) {
-		if (command[pos] == '(')
-			insideParenthesesCount ++;
-		if (command[pos] == ')')
-			insideParenthesesCount --;
-		if (command[pos] == '=' && insideParenthesesCount == 0) {
-			command.replace(pos, 1, " = ");
-			pos ++;
-		}
-
-		pos ++;
-	}
-
-	// Split command into words, ignoring all whitespace:
-	pos = 0;
-	while (pos < command.length()) {
-		// Skip initial whitespace:
-		while (pos < command.length() && command[pos] == ' ')
-			pos ++;
-		
-		if (pos >= command.length())
-			break;
-		
-		// This is a new word. Add all characters, until
-		// whitespace or end of string:
-		string newWord = "";
-		while (pos < command.length() && command[pos] != ' ') {
-			newWord += command[pos];
-			pos ++;
-		}
-
-		if (commandName.empty())
-			commandName = newWord;
-		else
-			arguments.push_back(newWord);
-	}
-}
-
-
-void CommandInterpreter::VariableAssignment(const string& componentPath,
-	const string& variableName, const string& expression)
-{
-	refcount_ptr<Component> component = m_GXemul->GetRootComponent()->
-	    LookupPath(componentPath);
-
-	StateVariable* var = component->GetVariable(variableName);
-	if (var == NULL) {
-		m_GXemul->GetUI()->ShowDebugMessage("Unknown variable '" +
-		    variableName + "'? (Internal error.)\n");
-		throw std::exception();
-	}
-
-	const refcount_ptr<Component> lightClone =
-	    m_GXemul->GetRootComponent()->LightClone();
-
-	// Attempt to assign the expression to the variable:
-	if (!component->SetVariableValue(variableName, expression))
-		m_GXemul->GetUI()->ShowDebugMessage("Assignment failed.\n");
-
-	// ... and print all state change (in case a write to a variable had
-	// side effects, then this makes sure that the user sees all such side
-	// effects):
-	stringstream changeMessages;
-	m_GXemul->GetRootComponent()->DetectChanges(lightClone, changeMessages);
-
-	string msg = changeMessages.str();
-	if (msg == "")
-		msg = "(No state change.)\n";
-
-	m_GXemul->GetUI()->ShowDebugMessage(msg);
-}
-
-
-bool CommandInterpreter::RunComponentMethod(
-	const string& componentPathAndMethod, const vector<string>& arguments)
-{
-	// Note: componentPathAndMethod may or may not have a method at
-	// the end!
-
-	// Make several "smart" guesses:
-	refcount_ptr<Component> component;
-	string componentPath;
-	string methodName;
-
-	do {
-		// 1. Assume that componentPathAndMethod is a full component
-		// path:
-		component = m_GXemul->GetRootComponent()->
-		    LookupPath(componentPathAndMethod);
-		if (!component.IsNULL())
-			break;
-
-		// 2. Assume that componentPathAndMethod is a component
-		// path, but it is not tab-completed yet:
-		string tabcompleted = componentPathAndMethod;
-		size_t tmpLen = tabcompleted.length();
-		if (TabComplete(tabcompleted, tmpLen)) {
-			component = m_GXemul->GetRootComponent()->
-			    LookupPath(tabcompleted);
-			if (!component.IsNULL())
-				break;
-		}
-		
-		// If there is no period in the name, we can't continue
-		// with the following guesses.
-		if (componentPathAndMethod.find(".") == string::npos)
-			break;
-
-		size_t pos = componentPathAndMethod.find_last_of('.');
-
-		// 3. Assume full component path + ".method":
-		componentPath = componentPathAndMethod.substr(0, pos);
-		component = m_GXemul->GetRootComponent()->
-		    LookupPath(componentPath);
-		if (!component.IsNULL()) {
-			methodName = componentPathAndMethod.substr(pos+1);
-			break;
-		}
-
-		// 4. Assume non-tab-completed component path + ".method":
-		tabcompleted = componentPath;
-		tmpLen = tabcompleted.length();
-		if (TabComplete(tabcompleted, tmpLen)) {
-			component = m_GXemul->GetRootComponent()->
-			    LookupPath(tabcompleted);
-			if (!component.IsNULL()) {
-				methodName =
-				    componentPathAndMethod.substr(pos+1);
-				break;
-			}
-		}
-	} while (false);
-
-	if (component.IsNULL())
-		return false;
-
-	// No method given? Then show the component tree, and the component's
-	// state variables, and return.
-	if (methodName.empty()) {
-		m_GXemul->GetUI()->ShowDebugMessage(
-		    component->GenerateTreeDump(""));
-		
-		// Retrieve the names of all the state variables:
-		vector<string> variableNames;
-		component->GetVariableNames(variableNames);
-
-		stringstream ss;
-		ss << "\n";
-
-		size_t maxLen = 0;
-		size_t i;
-		for (i=0; i<variableNames.size(); i++)
-			if (variableNames[i].length() > maxLen)
-				maxLen = variableNames[i].length();
-
-		for (i=0; i<variableNames.size(); i++) {
-			const string& name = variableNames[i];
-			if (name == "name" || name == "template")
-				continue;
-
-			ss << "  " << name;
-			for (size_t j=name.length(); j<=maxLen; j++)
-				ss << " ";
-
-			const StateVariable* var = component->GetVariable(name);
-			if (var == NULL)
-				ss << "= (unknown?)";
-			else
-				ss << "= " << var->ToString();
-
-			ss << "\n";
-		}
-
-		m_GXemul->GetUI()->ShowDebugMessage(ss.str());
-		
-		return true;
-	}
-
-	// Now, it is possible that methodName is incomplete, so it has to
-	// be looked up as well:
-	vector<string> names;
-	component->GetMethodNames(names);
-	int nrOfMatches = 0;
-	string fullMatch;
-	for (size_t i=0; i<names.size(); ++i) {
-		if (names[i].substr(0, methodName.length()) == methodName) {
-			++ nrOfMatches;
-			fullMatch = names[i];
-		}
-	}
-
-	if (nrOfMatches == 1) {
-		// Execute it!
-		component->ExecuteMethod(m_GXemul, fullMatch, arguments);
-
-		if (component->MethodMayBeReexecutedWithoutArgs(fullMatch))
-			m_mayBeReexecuted = componentPathAndMethod;
-
-		return true;
-	}
-
-	// Try variable names:
-	names.clear();
-	component->GetVariableNames(names);
-	nrOfMatches = 0;
-	fullMatch = "";
-	for (size_t i=0; i<names.size(); ++i) {
-		// Exact match?
-		if (names[i] == methodName) {
-			nrOfMatches = 1;
-			fullMatch = names[i];
-			break;
-		}
-
-		// Partial match?
-		if (names[i].substr(0, methodName.length()) == methodName) {
-			++ nrOfMatches;
-			fullMatch = names[i];
-		}
-	}
-
-	stringstream ss;
-
-	if (nrOfMatches == 1) {
-		if (arguments.size() > 0) {
-			if (arguments.size() == 1 ||
-			    arguments[0] != "=") {
-				// TODO: Printing expressions, such as
-				//	cpu.pc + 4
-
-				m_GXemul->GetUI()->ShowDebugMessage(
-				    "Syntax error. Variable assignment syntax"
-				    " is:\n  <variable> = <expression>\n");
-				return true;
-			}
-
-			const StateVariable* var =
-			    component->GetVariable(fullMatch);
-			if (var == NULL) {
-				m_GXemul->GetUI()->ShowDebugMessage(
-				    "Unknown variable.\n");
-				return true;
-			}
-
-			string assignment;
-			for (size_t i=1; i<arguments.size(); ++i)
-				assignment += arguments[i] + " ";
-
-			VariableAssignment(component->GeneratePath(), fullMatch, assignment);
-
-			return true;
-		}
-
-		// Print the variable's name and value:
-		ss << fullMatch;
-
-		const StateVariable* var = component->GetVariable(fullMatch);
-		if (var == NULL)
-			ss << " = (unknown variable?)";
-		else
-			ss << " = " << var->ToString();
-
-		ss << "\n";
-
-		m_GXemul->GetUI()->ShowDebugMessage(ss.str());
-
-		return true;
-	}
-
-	if (nrOfMatches > 1)
-		ss << methodName << ": ambiguous method or variable name of "
-		    << component->GeneratePath() << ".\n";
-	else
-		ss << methodName << ": not a method or variable of "
-		    << component->GeneratePath() << ".\n";
-
-	m_GXemul->GetUI()->ShowDebugMessage(ss.str());
-
-	return false;
-}
-
-
-bool CommandInterpreter::RunCommand(const string& command, bool* pSuccess)
-{
-	string commandName;
-	vector<string> arguments;
-	SplitIntoWords(command, commandName, arguments);
-
-	m_mayBeReexecuted = "";
-
-	m_GXemul->GetUI()->ShowCommandMessage(command);
-
-	// Find the command...
-	Commands::iterator it = m_commands.find(commandName);
-	if (it == m_commands.end()) {
-		// Not found? Then try to tab-complete the name...
-		string commandTabCompleted = commandName;
-		size_t tmpCursorPos = commandTabCompleted.length();
-		TabComplete(commandTabCompleted, tmpCursorPos);
-
-		// remove any trailing space(s):
-		while (commandTabCompleted.length() > 0 &&
-		    commandTabCompleted[commandTabCompleted.length()-1] == ' ')
-			commandTabCompleted.erase(
-			    commandTabCompleted.length() - 1);
-
-		// ... and try again:
-		it = m_commands.find(commandTabCompleted);
-		if (it == m_commands.end()) {
-			// If this is a component name [with an optional
-			// method name], then execute a method on it.
-			if (RunComponentMethod(commandName, arguments))
-				return true;
-			m_GXemul->GetUI()->ShowDebugMessage(commandName +
-			    ": unknown command. Type  help  for help.\n");
-			return false;
-		}
-	}
-
-	if (arguments.size() != 0 && (it->second)->GetArgumentFormat() == "") {
-		m_GXemul->GetUI()->ShowDebugMessage(commandName +
-		    " takes no arguments. Type  help " + commandName +
-		    "  for help on the syntax.\n");
-		return false;
-	}
-
-	// ... and execute it:
-	bool success = (it->second)->Execute(*m_GXemul, arguments);
-	if (pSuccess != NULL) {
-		*pSuccess = success;
-	} else {
-		if (!success) {
-			throw UnitTestFailedException("apa");
-		}
-	}
-
-	if ((it->second)->MayBeReexecutedWithoutArgs())
-		m_mayBeReexecuted = it->first;
-
-	return true;
-}
-
-
-const string& CommandInterpreter::GetCurrentCommandBuffer() const
-{
-	return m_currentCommandString;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_CommandInterpreter_AddKey_ReturnValue()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	UnitTest::Assert("addkey of regular char should return false",
-	    ci.AddKey('a') == false);
-
-	UnitTest::Assert("addkey of nul char should return false",
-	    ci.AddKey('\0') == false);
-
-	UnitTest::Assert("addkey of newline should return true",
-	    ci.AddKey('\n') == true);
-
-	UnitTest::Assert("addkey of carriage return should return true too",
-	    ci.AddKey('\r') == true);
-}
-
-static void Test_CommandInterpreter_KeyBuffer()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	UnitTest::Assert("buffer should initially be empty",
-	    ci.GetCurrentCommandBuffer() == "");
-
-	ci.AddKey('a');		// normal char
-
-	UnitTest::Assert("buffer should contain 'a'",
-	    ci.GetCurrentCommandBuffer() == "a");
-
-	ci.AddKey('\0');	// nul char should have no effect
-
-	UnitTest::Assert("buffer should still contain only 'a'",
-	    ci.GetCurrentCommandBuffer() == "a");
-
-	ci.AddKey('A');		// multiple chars
-	ci.AddKey('B');
-	UnitTest::Assert("buffer should contain 'aAB'",
-	    ci.GetCurrentCommandBuffer() == "aAB");
-
-	ci.AddKey('\177');	// del
-
-	UnitTest::Assert("buffer should contain 'aA' (del didn't work?)",
-	    ci.GetCurrentCommandBuffer() == "aA");
-
-	ci.AddKey('\b');	// backspace
-
-	UnitTest::Assert("buffer should contain 'a' again (BS didn't work)",
-	    ci.GetCurrentCommandBuffer() == "a");
-
-	ci.AddKey('\b');
-
-	UnitTest::Assert("buffer should now be empty '' again",
-	    ci.GetCurrentCommandBuffer() == "");
-
-	ci.AddKey('\b');	// cannot be emptier than... well... empty :)
-
-	UnitTest::Assert("buffer should still be empty",
-	    ci.GetCurrentCommandBuffer() == "");
-
-	ci.AddKey('a');
-
-	UnitTest::Assert("buffer should contain 'a' again",
-	    ci.GetCurrentCommandBuffer() == "a");
-
-	ci.AddKey('Q');
-
-	UnitTest::Assert("buffer should contain 'aQ'",
-	    ci.GetCurrentCommandBuffer() == "aQ");
-
-	ci.AddKey('\n');	// newline should execute the command
-
-	UnitTest::Assert("buffer should be empty after executing '\\n'",
-	    ci.GetCurrentCommandBuffer() == "");
-
-	ci.AddKey('Z');
-	ci.AddKey('Q');
-
-	UnitTest::Assert("new command should have been possible",
-	    ci.GetCurrentCommandBuffer() == "ZQ");
-
-	ci.AddKey('\r');	// carriage return should work like newline
-
-	UnitTest::Assert("buffer should be empty after executing '\\r'",
-	    ci.GetCurrentCommandBuffer() == "");
-}
-
-static void Test_CommandInterpreter_KeyBuffer_CursorMovement()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.AddKey('A');
-	ci.AddKey('B');
-	ci.AddKey('C');
-	ci.AddKey('D');
-	ci.AddKey('E');
-	UnitTest::Assert("buffer should contain 'ABCDE'",
-	    ci.GetCurrentCommandBuffer(), "ABCDE");
-
-	ci.AddKey('\2');	// CTRL-B should move back (left)
-	ci.AddKey('\2');
-	ci.AddKey('\2');
-	UnitTest::Assert("buffer should still contain 'ABCDE'",
-	    ci.GetCurrentCommandBuffer(), "ABCDE");
-
-	ci.AddKey('\b');
-	UnitTest::Assert("buffer should now contain 'ACDE'",
-	    ci.GetCurrentCommandBuffer(), "ACDE");
-
-	ci.AddKey('\6');	// CTRL-F should move forward (right)
-	ci.AddKey('\6');
-	UnitTest::Assert("buffer should still contain 'ACDE'",
-	    ci.GetCurrentCommandBuffer(), "ACDE");
-
-	ci.AddKey('\b');
-	UnitTest::Assert("buffer should now contain 'ACE'",
-	    ci.GetCurrentCommandBuffer(), "ACE");
-
-	ci.AddKey('\1');	// CTRL-A should move to start of line
-	UnitTest::Assert("buffer should still contain 'ACE'",
-	    ci.GetCurrentCommandBuffer(), "ACE");
-
-	ci.AddKey('1');
-	ci.AddKey('2');
-	UnitTest::Assert("buffer should now contain '12ACE'",
-	    ci.GetCurrentCommandBuffer(), "12ACE");
-
-	ci.AddKey('\5');	// CTRL-E should move to end of line
-	UnitTest::Assert("buffer should still contain '12ACE'",
-	    ci.GetCurrentCommandBuffer(), "12ACE");
-
-	ci.AddKey('x');
-	ci.AddKey('y');
-	UnitTest::Assert("buffer should now contain '12ACExy'",
-	    ci.GetCurrentCommandBuffer(), "12ACExy");
-
-	ci.AddKey('\1');	// CTRL-A move to start of line again
-	ci.AddKey('\6');	// CTRL-F move to the right
-	ci.AddKey('\4');	// CTRL-D should remove character to the right
-	UnitTest::Assert("buffer should now contain '1ACExy'",
-	    ci.GetCurrentCommandBuffer(), "1ACExy");
-}
-
-static void Test_CommandInterpreter_KeyBuffer_CtrlK()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.AddKey('A');
-	ci.AddKey('B');
-	ci.AddKey('C');
-	ci.AddKey('D');
-	ci.AddKey('E');
-	UnitTest::Assert("buffer should contain 'ABCDE'",
-	    ci.GetCurrentCommandBuffer(), "ABCDE");
-
-	ci.AddKey('\2');	// CTRL-B should move back (left)
-	ci.AddKey('\2');
-	UnitTest::Assert("buffer should still contain 'ABCDE'",
-	    ci.GetCurrentCommandBuffer(), "ABCDE");
-
-	ci.AddKey('\13');	// CTRL-K
-	UnitTest::Assert("buffer should now contain 'ABC'",
-	    ci.GetCurrentCommandBuffer(), "ABC");
-
-	ci.AddKey('X');
-	ci.AddKey('\13');	// CTRL-K again, at end of line
-	UnitTest::Assert("buffer should now contain 'ABCX'",
-	    ci.GetCurrentCommandBuffer(), "ABCX");
-
-	ci.AddKey('\1');	// CTRL-A to move to start of line
-	ci.AddKey('\13');	// CTRL-K again, should erase everything
-	UnitTest::Assert("buffer should now be empty",
-	    ci.GetCurrentCommandBuffer(), "");
-}
-
-static void Test_CommandInterpreter_KeyBuffer_CtrlW()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	UnitTest::Assert("buffer should contain ''",
-	    ci.GetCurrentCommandBuffer(), "");
-	ci.AddKey('\27');	// CTRL-W
-	UnitTest::Assert("buffer should still contain ''",
-	    ci.GetCurrentCommandBuffer(), "");
-
-	ci.AddKey('a');
-	ci.AddKey('b');
-	ci.AddKey('c');
-	UnitTest::Assert("buffer should contain abc",
-	    ci.GetCurrentCommandBuffer(), "abc");
-	ci.AddKey('\27');	// CTRL-W
-	UnitTest::Assert("buffer should be empty again",
-	    ci.GetCurrentCommandBuffer(), "");
-
-	ci.AddKey(' ');
-	ci.AddKey(' ');
-	ci.AddKey('a');
-	ci.AddKey('b');
-	ci.AddKey('c');
-	UnitTest::Assert("buffer should contain '  abc'",
-	    ci.GetCurrentCommandBuffer(), "  abc");
-	ci.AddKey('\27');	// CTRL-W
-	UnitTest::Assert("buffer should contain only two spaces",
-	    ci.GetCurrentCommandBuffer(), "  ");
-
-	ci.AddKey('a');
-	ci.AddKey('b');
-	ci.AddKey('c');
-	ci.AddKey(' ');
-	UnitTest::Assert("buffer should contain '  abc '",
-	    ci.GetCurrentCommandBuffer(), "  abc ");
-	ci.AddKey('\27');	// CTRL-W
-	UnitTest::Assert("buffer should again contain only two spaces",
-	    ci.GetCurrentCommandBuffer(), "  ");
-
-	ci.AddKey('a');
-	ci.AddKey('b');
-	ci.AddKey('c');
-	ci.AddKey('d');
-	ci.AddKey(' ');
-	ci.AddKey('e');
-	ci.AddKey('f');
-	ci.AddKey('g');
-	ci.AddKey('h');
-	ci.AddKey('i');
-	ci.AddKey(' ');
-	ci.AddKey('\2');	// CTRL-B = move left
-	ci.AddKey('\2');
-	ci.AddKey('\2');
-	UnitTest::Assert("buffer should contain '  abcd efghi '",
-	    ci.GetCurrentCommandBuffer(), "  abcd efghi ");
-	ci.AddKey('\27');	// CTRL-W
-	UnitTest::Assert("buffer should now contain '  abcd hi '",
-	    ci.GetCurrentCommandBuffer(), "  abcd hi ");
-}
-
-static void Test_CommandInterpreter_CommandHistory()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	UnitTest::Assert("history should still be empty (1)",
-	    ci.AddLineToCommandHistory(""), 0);
-
-	UnitTest::Assert("history should still be empty (2)",
-	    ci.AddLineToCommandHistory(""), 0);
-
-	UnitTest::Assert("A: history line 0",
-	    ci.GetHistoryLine(0), "");
-	UnitTest::Assert("A: history line 1 not set yet",
-	    ci.GetHistoryLine(1), "");
-	UnitTest::Assert("A: history line 2 not set yet",
-	    ci.GetHistoryLine(2), "");
-
-	UnitTest::Assert("history should contain one entry",
-	    ci.AddLineToCommandHistory("hello"), 1);
-
-	UnitTest::Assert("B: history line 0",
-	    ci.GetHistoryLine(0), "");
-	UnitTest::Assert("B: history line 1",
-	    ci.GetHistoryLine(1), "hello");
-	UnitTest::Assert("B: history line 2 not set yet",
-	    ci.GetHistoryLine(2), "");
-
-	UnitTest::Assert("history should contain two entries",
-	    ci.AddLineToCommandHistory("world"), 2);
-
-	UnitTest::Assert("history should still contain two entries",
-	    ci.AddLineToCommandHistory("world"), 2);
-
-	UnitTest::Assert("C: history line 0",
-	    ci.GetHistoryLine(0), "");
-	UnitTest::Assert("C: history line 1",
-	    ci.GetHistoryLine(1), "world");
-	UnitTest::Assert("C: history line 2",
-	    ci.GetHistoryLine(2), "hello");
-
-	UnitTest::Assert("history should contain three entries",
-	    ci.AddLineToCommandHistory("hello"), 3);
-
-	UnitTest::Assert("D: history line 0",
-	    ci.GetHistoryLine(0), "");
-	UnitTest::Assert("D: history line 1",
-	    ci.GetHistoryLine(1), "hello");
-	UnitTest::Assert("D: history line 2",
-	    ci.GetHistoryLine(2), "world");
-
-	UnitTest::Assert("history should still contain three entries",
-	    ci.AddLineToCommandHistory(""), 3);
-}
-
-/**
- * \brief A dummy Command, for unit testing purposes
- */
-class DummyCommand2
-	: public Command
-{
-public:
-	DummyCommand2(int& valueRef)
-		: Command("dummycommand", "[args]")
-		, m_value(valueRef)
-	{
-	}
-
-	~DummyCommand2()
-	{
-	}
-
-	bool Execute(GXemul& gxemul, const vector<string>& arguments)
-	{
-		m_value ++;
-		return true;
-	}
-
-	string GetShortDescription() const
-	{
-		return "A dummy command used for unit testing.";
-	}
-
-	string GetLongDescription() const
-	{
-		return "This is just a dummy command used for unit testing.";
-	}
-
-private:
-	int&	m_value;
-};
-
-/**
- * \brief A dummy Command, for unit testing purposes
- */
-class DummyCommand3
-	: public Command
-{
-public:
-	DummyCommand3(int& valueRef)
-		: Command("dummycmd", "[args]")
-		, m_value(valueRef)
-	{
-	}
-
-	~DummyCommand3()
-	{
-	}
-
-	bool Execute(GXemul& gxemul, const vector<string>& arguments)
-	{
-		m_value ++;
-		return true;
-	}
-
-	string GetShortDescription() const
-	{
-		return "A dummy command used for unit testing.";
-	}
-
-	string GetLongDescription() const
-	{
-		return "This is just a dummy command used for unit testing.";
-	}
-
-private:
-	int&	m_value;
-};
-
-static void Test_CommandInterpreter_AddCommand()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	size_t nCommands = ci.GetCommands().size();
-	UnitTest::Assert("there should be some commands already",
-	    nCommands > 0);
-
-	ci.AddCommand(new VersionCommand);
-
-	UnitTest::Assert("it should not be possible to have multiple commands"
-		" with the same name",
-	    ci.GetCommands().size() == nCommands);
-
-	int dummyInt = 42;
-	ci.AddCommand(new DummyCommand2(dummyInt));
-
-	UnitTest::Assert("it should be possible to add new commands",
-	    ci.GetCommands().size() == nCommands + 1);
-}
-
-static void Test_CommandInterpreter_TabCompletion_EmptyLine()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should not have produced anything",
-	    ci.GetCurrentCommandBuffer(), "");
-}
-
-static void Test_CommandInterpreter_TabCompletion_FullWord()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.AddKey('d');
-	ci.AddKey('u');
-	ci.AddKey('m');
-	ci.AddKey('m');
-	ci.AddKey('Z');
-	ci.AddKey('\2');	// CTRL-B = move left
-	UnitTest::Assert("initial buffer contents mismatch",
-	    ci.GetCurrentCommandBuffer(), "dummZ");
-
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have failed",
-	    ci.GetCurrentCommandBuffer(), "dummZ");
-
-	int dummyInt = 42;
-	ci.AddCommand(new DummyCommand2(dummyInt));
-
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have succeeded",
-	    ci.GetCurrentCommandBuffer(), "dummycommandZ");
-
-	ci.AddKey('X');
-	UnitTest::Assert("tab completion should have placed cursor at end of"
-		" the tab-completed word",
-	    ci.GetCurrentCommandBuffer(), "dummycommandXZ");
-}
-
-static void Test_CommandInterpreter_TabCompletion_SpacesFirstOnLine()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.AddKey(' ');
-	ci.AddKey(' ');
-	ci.AddKey('v');
-	ci.AddKey('e');
-	ci.AddKey('r');
-	ci.AddKey('s');
-	UnitTest::Assert("initial buffer contents mismatch",
-	    ci.GetCurrentCommandBuffer(), "  vers");
-
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have succeeded",
-	    ci.GetCurrentCommandBuffer(), "  version ");
-}
-
-static void Test_CommandInterpreter_TabCompletion_Partial()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.AddKey('d');
-	ci.AddKey('u');
-	ci.AddKey('m');
-	ci.AddKey('m');
-	ci.AddKey('Z');
-	ci.AddKey('\2');	// CTRL-B = move left
-	UnitTest::Assert("initial buffer contents mismatch",
-	    ci.GetCurrentCommandBuffer(), "dummZ");
-
-	int dummyInt = 42;
-	ci.AddCommand(new DummyCommand2(dummyInt));
-	ci.AddCommand(new DummyCommand3(dummyInt));
-
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have partially succeeded",
-	    ci.GetCurrentCommandBuffer(), "dummycZ");
-}
-
-static void Test_CommandInterpreter_TabCompletion_C()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.AddKey('c');
-	UnitTest::Assert("initial buffer contents mismatch",
-	    ci.GetCurrentCommandBuffer(), "c");
-
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should not have modified command",
-	    ci.GetCurrentCommandBuffer(), "c");
-
-	// ... because there are at least two possible commands on the
-	// letter c: close and continue.
-}
-
-static void Test_CommandInterpreter_TabCompletion_OnlyCommandAsFirstWord()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.AddKey('v');
-	ci.AddKey('e');
-	ci.AddKey('r');
-	ci.AddKey('s');
-	UnitTest::Assert("initial buffer contents mismatch",
-	    ci.GetCurrentCommandBuffer(), "vers");
-
-	ci.AddKey('\t');
-	UnitTest::Assert("first tab completion should have succeeded",
-	    ci.GetCurrentCommandBuffer(), "version ");
-
-	ci.AddKey('v');
-	ci.AddKey('e');
-	ci.AddKey('r');
-	ci.AddKey('s');
-	UnitTest::Assert("buffer contents mismatch",
-	    ci.GetCurrentCommandBuffer(), "version vers");
-
-	ci.AddKey('\t');
-	UnitTest::Assert("second tab completion should have failed",
-	    ci.GetCurrentCommandBuffer(), "version vers");
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentName()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add testm88k");
-	UnitTest::Assert("initial buffer should be empty",
-	    ci.GetCurrentCommandBuffer(), "");
-
-	ci.AddKey('c');
-	ci.AddKey('p');
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have completed the "
-		"component name",
-	    ci.GetCurrentCommandBuffer(), "cpu0");
-
-	// Note: No space after component tab completion.
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentNameAlreadyComplete()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add testm88k");
-	UnitTest::Assert("initial buffer should be empty",
-	    ci.GetCurrentCommandBuffer(), "");
-
-	ci.AddKey('c');
-	ci.AddKey('p');
-	ci.AddKey('u');
-	ci.AddKey('0');
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should not have changed anything",
-	    ci.GetCurrentCommandBuffer(), "cpu0");
-
-	// Note: No space after component tab completion.
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentNameMultiple()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add testm88k");
-	ci.RunCommand("add m88k_cpu mainbus0");
-	UnitTest::Assert("initial buffer should be empty",
-	    ci.GetCurrentCommandBuffer(), "");
-
-	ci.AddKey('c');
-	ci.AddKey('p');
-	ci.AddKey('\t');
-	UnitTest::Assert("there are both cpu0 and cpu1, so don't expand all the way",
-	    ci.GetCurrentCommandBuffer(), "cpu");
-
-	// Note: No space after component tab completion.
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentNameMultipleParents()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add testm88k");	// root.machine0
-	ci.RunCommand("add testm88k");	// root.machine1
-	UnitTest::Assert("initial buffer should be empty",
-	    ci.GetCurrentCommandBuffer(), "");
-
-	ci.AddKey('c');
-	ci.AddKey('p');
-	ci.AddKey('\t');
-	UnitTest::Assert("there are cpu0 in both root.machine0 and root.machine1",
-	    ci.GetCurrentCommandBuffer(), "machine");
-
-	// Note: No space after component tab completion.
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentNameNonexist()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add dummy");
-	UnitTest::Assert("initial buffer should be empty",
-	    ci.GetCurrentCommandBuffer(), "");
-
-	ci.AddKey('r');
-	ci.AddKey('o');
-	ci.AddKey('o');
-	ci.AddKey('t');
-	ci.AddKey('.');
-	ci.AddKey('X');
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should not have succeeded",
-	    ci.GetCurrentCommandBuffer(), "root.X");
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentNameAsArgument()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add dummy root");
-	UnitTest::Assert("initial buffer should be empty",
-	    ci.GetCurrentCommandBuffer(), "");
-
-	ci.AddKey('a');
-	ci.AddKey('d');
-	ci.AddKey('d');
-	ci.AddKey(' ');
-	ci.AddKey('d');
-	ci.AddKey('u');
-	ci.AddKey('m');
-	ci.AddKey('m');
-	ci.AddKey('y');
-	ci.AddKey(' ');
-	ci.AddKey('d');
-	ci.AddKey('u');
-	UnitTest::Assert("buffer contents mismatch",
-	    ci.GetCurrentCommandBuffer(), "add dummy du");
-
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have completed the "
-		"component name",
-	    ci.GetCurrentCommandBuffer(), "add dummy dummy0");
-
-	// Note: No space after component tab completion.
-}
-
-static void Test_CommandInterpreter_TabCompletion_CWithComponents()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add testm88k");
-
-	ci.AddKey('c');
-	UnitTest::Assert("initial buffer contents mismatch",
-	    ci.GetCurrentCommandBuffer(), "c");
-
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should not have modified command",
-	    ci.GetCurrentCommandBuffer(), "c");
-
-	// ... because there are at least two possible commands on the
-	// letter c: close and continue.
-}
-
-static void Test_CommandInterpreter_TabCompletion_roWithComponents()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add testm88k");
-
-	ci.AddKey('r');
-	ci.AddKey('o');
-	ci.AddKey('\t');
-	// there are both "rom0" and "root".
-	UnitTest::Assert("tab completion should not have expanded",
-	    ci.GetCurrentCommandBuffer(), "ro");
-
-	ci.AddKey('o');
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have expanded to 'root'",
-	    ci.GetCurrentCommandBuffer(), "root");
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentMethods_Empty()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add testm88k");
-
-	ci.AddKey('c');
-	ci.AddKey('p');
-	ci.AddKey('u');
-	ci.AddKey('.');
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have caused expansion",
-	    ci.GetCurrentCommandBuffer(), "cpu0.");
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentMethods()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add testm88k");
-
-	ci.AddKey('c');
-	ci.AddKey('p');
-	ci.AddKey('u');
-	ci.AddKey('.');
-	ci.AddKey('u');
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have caused expansion",
-	    ci.GetCurrentCommandBuffer(), "cpu0.unassemble");
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentMethods_Middle()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add testm88k");
-
-	ci.AddKey('c');
-	ci.AddKey('p');
-	ci.AddKey('u');
-	ci.AddKey('.');
-	ci.AddKey('u');
-	ci.AddKey('n');
-	ci.AddKey('a');
-	ci.AddKey('b');
-	ci.AddKey('c');
-	ci.AddKey('d');
-	ci.AddKey('\2');
-	ci.AddKey('\2');
-	ci.AddKey('\2');	// cursor placed after "una"
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have caused expansion",
-	    ci.GetCurrentCommandBuffer(), "cpu0.unassemblebcd");
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentMethods_Arg()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add testm88k");
-
-	ci.AddKey('c');
-	ci.AddKey('p');
-	ci.AddKey('u');
-	ci.AddKey('.');
-	ci.AddKey('u');
-	ci.AddKey(' ');
-	ci.AddKey('a');
-	ci.AddKey('d');
-	ci.AddKey('d');
-	ci.AddKey('r');
-	ci.AddKey('\2');
-	ci.AddKey('\2');
-	ci.AddKey('\2');
-	ci.AddKey('\2');
-	ci.AddKey('\2');	// cursor placed after "u"
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have caused expansion",
-	    ci.GetCurrentCommandBuffer(), "cpu0.unassemble addr");
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentVariables()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add testm88k");
-
-	ci.AddKey('c');
-	ci.AddKey('p');
-	ci.AddKey('u');
-	ci.AddKey('.');
-	ci.AddKey('s');
-	ci.AddKey('h');
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have caused expansion cpu -> cpu0",
-	    ci.GetCurrentCommandBuffer(), "cpu0.showFunctionTrace");
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentVariables_Max()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add ram");
-
-	ci.AddKey('r');
-	ci.AddKey('a');
-	ci.AddKey('m');
-	ci.AddKey('.');
-	ci.AddKey('m');
-	ci.AddKey('e');
-	ci.AddKey('m');
-	ci.AddKey('o');
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have caused expansion ram -> ram0",
-	    ci.GetCurrentCommandBuffer(), "ram0.memoryMapped");
-}
-
-static void Test_CommandInterpreter_TabCompletion_ComponentVariables_Max2()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	ci.RunCommand("add ram");
-
-	ci.AddKey('r');
-	ci.AddKey('a');
-	ci.AddKey('m');
-	ci.AddKey('.');
-	ci.AddKey('m');
-	ci.AddKey('e');
-	ci.AddKey('m');
-	ci.AddKey('o');
-	ci.AddKey(' ');
-	ci.AddKey('2');
-	ci.AddKey('\2');
-	ci.AddKey('\2');
-	ci.AddKey('\t');
-	UnitTest::Assert("tab completion should have caused expansion ram -> ram0",
-	    ci.GetCurrentCommandBuffer(), "ram0.memoryMapped 2");
-
-	ci.AddKey('X');
-	UnitTest::Assert("cursor position after tab completion was wrong?",
-	    ci.GetCurrentCommandBuffer(), "ram0.memoryMappedX 2");
-}
-
-static void Test_CommandInterpreter_NonExistingCommand()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	UnitTest::Assert("nonexisting (nonsense) command should fail",
-	    ci.RunCommand("nonexistingcommand") == false);
-}
-
-static void Test_CommandInterpreter_SimpleCommand()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	UnitTest::Assert("simple command should succeed",
-	    ci.RunCommand("version") == true);
-
-	UnitTest::Assert("simple command with whitespace should succeed",
-	    ci.RunCommand("   version   ") == true);
-}
-
-static void Test_CommandInterpreter_SimpleCommand_NoArgsAllowed()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	UnitTest::Assert("simple command should succeed",
-	    ci.RunCommand("version") == true);
-
-	UnitTest::Assert("simple command which does not take arguments should"
-		" fail when attempt is made to execute it with arguments",
-	    ci.RunCommand("version hello") == false);
-}
-
-static void Test_CommandInterpreter_ComponentMethods()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	UnitTest::Assert("Huh? Could not add testm88k.",
-	    ci.RunCommand("add testm88k") == true);
-
-	UnitTest::Assert("component method 1",
-	    ci.RunCommand("cpu") == true);
-	UnitTest::Assert("component method 2",
-	    ci.RunCommand("cpu.u") == true);
-	UnitTest::Assert("component method 3",
-	    ci.RunCommand("cpu.urk") == false);
-	UnitTest::Assert("component method 4",
-	    ci.RunCommand("cpu.unassemble") == true);
-	UnitTest::Assert("component method 5",
-	    ci.RunCommand("root.machine0.mainbus0.cpu") == true);
-	UnitTest::Assert("component method 6",
-	    ci.RunCommand("root.machine0.mainbus0.cpu0") == true);
-	UnitTest::Assert("component method 7",
-	    ci.RunCommand("root.machine0.mainbus0.cpu.u") == true);
-	UnitTest::Assert("component method 8",
-	    ci.RunCommand("root.machine0.mainbus0.cpu0.unassemble") == true);
-}
-
-static void Test_CommandInterpreter_ComponentVariables_NoArgs()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	UnitTest::Assert("Huh? Could not add testm88k.",
-	    ci.RunCommand("add testm88k") == true);
-
-	UnitTest::Assert("component variable 1",
-	    ci.RunCommand("cpu.nonexistant") == false);
-	UnitTest::Assert("component variable 2",
-	    ci.RunCommand("cpu.pau") == true);
-	UnitTest::Assert("component variable 3",
-	    ci.RunCommand("root.machine0.mainbus0.cpu0.pau") == true);
-}
-
-static void Test_CommandInterpreter_ComponentVariables_Ambiguous()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	UnitTest::Assert("Huh? Could not add testmips.",
-	    ci.RunCommand("add testm88k") == true);
-
-	UnitTest::Assert("cpu.f should not work, there should be multiple matches",
-	    ci.RunCommand("cpu.f") == false);
-}
-
-static void Test_CommandInterpreter_ComponentVariables_PartialIsOk()
-{
-	GXemul gxemul;
-	CommandInterpreter& ci = gxemul.GetCommandInterpreter();
-
-	UnitTest::Assert("Huh? Could not add testm88k.",
-	    ci.RunCommand("add testm88k") == true);
-
-	// Make sure that r2 works, and doesn't complain about ambiguity.
-	UnitTest::Assert("gpr 2",
-	    ci.RunCommand("cpu.r2") == true);
-	UnitTest::Assert("gpr 29",
-	    ci.RunCommand("cpu.r29") == true);
-}
-
-UNITTESTS(CommandInterpreter)
-{
-	// Key and current buffer:
-	UNITTEST(Test_CommandInterpreter_AddKey_ReturnValue);
-	UNITTEST(Test_CommandInterpreter_KeyBuffer);
-	UNITTEST(Test_CommandInterpreter_KeyBuffer_CursorMovement);
-	UNITTEST(Test_CommandInterpreter_KeyBuffer_CtrlK);
-	UNITTEST(Test_CommandInterpreter_KeyBuffer_CtrlW);
-
-	// Command History:
-	UNITTEST(Test_CommandInterpreter_CommandHistory);
-
-	// AddCommand / GetCommands:
-	UNITTEST(Test_CommandInterpreter_AddCommand);
-
-	// Tab completion:
-	UNITTEST(Test_CommandInterpreter_TabCompletion_EmptyLine);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_FullWord);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_SpacesFirstOnLine);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_Partial);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_C);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_OnlyCommandAsFirstWord);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentName);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentNameAlreadyComplete);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentNameMultiple);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentNameMultipleParents);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentNameNonexist);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentNameAsArgument);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_CWithComponents);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_roWithComponents);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentMethods_Empty);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentMethods);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentMethods_Middle);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentMethods_Arg);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentVariables);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentVariables_Max);
-	UNITTEST(Test_CommandInterpreter_TabCompletion_ComponentVariables_Max2);
-
-	// RunCommand:
-	UNITTEST(Test_CommandInterpreter_NonExistingCommand);
-	UNITTEST(Test_CommandInterpreter_SimpleCommand);
-	UNITTEST(Test_CommandInterpreter_SimpleCommand_NoArgsAllowed);
-	UNITTEST(Test_CommandInterpreter_ComponentMethods);
-	UNITTEST(Test_CommandInterpreter_ComponentVariables_NoArgs);
-	UNITTEST(Test_CommandInterpreter_ComponentVariables_Ambiguous);
-	UNITTEST(Test_CommandInterpreter_ComponentVariables_PartialIsOk);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/commands/AddComponentCommand.cc gxemul-0.7.0+dfsg/src/main/commands/AddComponentCommand.cc
--- gxemul-0.6.2/src/main/commands/AddComponentCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/AddComponentCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,141 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/AddComponentCommand.h"
-#include "ComponentFactory.h"
-#include "GXemul.h"
-
-
-AddComponentCommand::AddComponentCommand()
-	: Command("add", "component-name [path]")
-{
-}
-
-
-AddComponentCommand::~AddComponentCommand()
-{
-}
-
-
-static void ShowMsg(GXemul& gxemul, const string& msg)
-{
-	gxemul.GetUI()->ShowDebugMessage(msg);
-}
-
-
-bool AddComponentCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	if (arguments.size() < 1) {
-		ShowMsg(gxemul, "No component-name given.\n");
-		return false;
-	}
-
-	if (arguments.size() > 2) {
-		ShowMsg(gxemul, "Too many arguments.\n");
-		return false;
-	}
-
-	string componentName = arguments[0];
-
-	refcount_ptr<Component> componentToAdd =
-	    ComponentFactory::CreateComponent(componentName, &gxemul);
-
-	if (componentToAdd.IsNULL()) {
-		ShowMsg(gxemul, componentName + ": unknown component,"
-		    " or invalid arguments given.\n");
-		return false;
-	}
-
-	string path = "root";
-	if (arguments.size() == 2)
-		path = arguments[1];
-
-	vector<string> matches = gxemul.GetRootComponent()->
-	    FindPathByPartialMatch(path);
-	if (matches.size() == 0) {
-		ShowMsg(gxemul, path +
-		    ": not a path to a known component.\n");
-		return false;
-	}
-	if (matches.size() > 1) {
-		ShowMsg(gxemul, path + " matches multiple components:\n");
-		for (size_t i=0; i<matches.size(); i++)
-			ShowMsg(gxemul, "  " + matches[i] + "\n");
-		return false;
-	}
-
-	refcount_ptr<Component> whereToAddIt =
-	    gxemul.GetRootComponent()->LookupPath(matches[0]);
-	if (whereToAddIt.IsNULL()) {
-		ShowMsg(gxemul, path + ": lookup of path failed.\n");
-		return false;
-	}
-
-	whereToAddIt->AddChild(componentToAdd);
-
-	return true;
-}
-
-
-string AddComponentCommand::GetShortDescription() const
-{
-	return "Adds a component to the emulation.";
-}
-
-
-string AddComponentCommand::GetLongDescription() const
-{
-	return
-	    "Adds a component (given by the component-name) to the current emulation\n"
-	    "setup. If path is omitted, the component is added at the root of the\n"
-	    "component tree. For example:\n"
-	    "\n"
-	    "> add testmips                                  <-- this adds machine0\n"
-	    "> root\n" 
-	    "  root\n"
-	    "  \\-- machine0  [testmips]\n"
-	    "      \\-- mainbus0\n"
-	    "          |-- ram0  (32 MB at offset 0)\n"
-	    "          |-- rom0  (16 MB at offset 0x1fc00000)\n"
-	    "          \\-- cpu0  (5KE, 100 MHz)\n"
-	    "...\n"
-	    "> add mips_cpu(model=R4400) mainbus0            <-- note that arguments\n"
-	    "> root                                              can be given during\n"
-	    "  root                                              component creation\n"
-	    "  \\-- machine0  [testmips]\n"
-	    "      \\-- mainbus0\n"
-	    "          |-- ram0  (32 MB at offset 0)\n"
-	    "          |-- rom0  (16 MB at offset 0x1fc00000)\n"
-	    "          |-- cpu0  (5KE, 100 MHz)\n"
-	    "          \\-- cpu1  (R4400, 100 MHz)\n"
-	    "\n"
-	    "See also:  copy             (to copy/clone a component in the tree)\n"
-	    "           list-components  (to get a list of available component types)\n"
-	    "           remove           (to remove a component from the emulation)\n"
-	    "           root             (to inspect the current emulation setup)\n";
-}
-
diff -Nru gxemul-0.6.2/src/main/commands/BackwardStepCommand.cc gxemul-0.7.0+dfsg/src/main/commands/BackwardStepCommand.cc
--- gxemul-0.6.2/src/main/commands/BackwardStepCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/BackwardStepCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,276 +0,0 @@
-/*
- *  Copyright (C) 2009-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/BackwardStepCommand.h"
-#include "GXemul.h"
-
-
-BackwardStepCommand::BackwardStepCommand()
-	: Command("backward-step", "")
-{
-}
-
-
-BackwardStepCommand::~BackwardStepCommand()
-{
-}
-
-
-bool BackwardStepCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	StateVariable* stepvar = gxemul.GetRootComponent()->GetVariable("step");
-	uint64_t step = stepvar->ToInteger();
-
-	if (step == 0) {
-		gxemul.GetUI()->ShowDebugMessage("Cannot go back further; "
-		    "already at step 0.\n");
-		return false;
-	}
-
-	stringstream stepss;
-	stepss << (step - 1);
-
-	const refcount_ptr<Component> lightClone = gxemul.GetRootComponent()->LightClone();
-
-	if (!gxemul.GetRootComponent()->SetVariableValue("step", stepss.str())) {
-		gxemul.GetUI()->ShowDebugMessage("Failed to set root.step.\n");
-		return false;
-	}
-
-	// Indent all debug output with message header "step X -> step X-1: ":
-	stringstream ss;
-	ss << "step " << step << " -> " << (step-1) <<  ": ";
-	UI::SetIndentationMessageHelper indentationHelper(gxemul.GetUI(), ss.str());
-
-	// Compare the clone of the component tree before changing the step
-	// with what we have now.
-	stringstream changeMessages;
-	gxemul.GetRootComponent()->DetectChanges(lightClone, changeMessages);
-
-	string msg = changeMessages.str();
-	if (msg == "")
-		msg = "No state change.\n";
-
-	gxemul.GetUI()->ShowDebugMessage(msg);
-
-	return true;
-}
-
-
-string BackwardStepCommand::GetShortDescription() const
-{
-	return "Runs one step of the emulation backwards.";
-}
-
-
-string BackwardStepCommand::GetLongDescription() const
-{
-	return
-	    "Runs one step of the emulation backwards. This command does the same as\n"
-	    "manually decreasing root.step by 1, except that all state changes are also\n"
-	    "displayed, e.g.:\n"
-	    "\n"
-	    "> backward-step\n"
-	    "step 3 -> 2: => cpu0.a1: 0 -> 0x2a\n"
-	    "             => cpu0.pc: 0xffffffffbfc0004c -> 0xffffffffbfc00048\n"
-	    "\n"
-	    "This command requires that snapshotting support is enabled (using the\n"
-	    "-B command line option).\n";
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_BackwardStepCommand_AlreadyAtStep0()
-{
-	refcount_ptr<Command> cmd = new BackwardStepCommand;
-	vector<string> dummyArguments;
-	
-	GXemul gxemul;
-
-	UnitTest::Assert("root.step should initially be zero", gxemul.GetStep(), 0);
-
-	cmd->Execute(gxemul, dummyArguments);
-
-	UnitTest::Assert("root.step should still be zero", gxemul.GetStep(), 0);
-}
-
-static void Test_BackwardStepCommand_NotWhenSnapshotsAreDisabled()
-{
-	refcount_ptr<Command> cmd = new BackwardStepCommand;
-	vector<string> dummyArguments;
-	
-	GXemul gxemul;
-
-	char filename[] = "test/FileLoader_ELF_MIPS";
-	char *filenames[] = { filename };
-	gxemul.ParseFilenames("testmips", 1, filenames);
-	gxemul.Reset();
-
-	gxemul.SetSnapshottingEnabled(false);
-
-	gxemul.GetCommandInterpreter().RunCommand("step 3");
-	gxemul.Execute();
-
-	UnitTest::Assert("root.step should initially be 3", gxemul.GetStep(), 3);
-
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("cpu0");
-	UnitTest::Assert("3: cpu0.pc", cpu->GetVariable("pc")->ToString(), "0xffffffff80010104");
-	UnitTest::Assert("3: cpu0.sp", cpu->GetVariable("sp")->ToString(), "0xffffffffa0007ed0");
-	UnitTest::Assert("3: cpu0.v0", cpu->GetVariable("v0")->ToString(), "0xffffffff88880000");
-	UnitTest::Assert("3: cpu0.v1", cpu->GetVariable("v1")->ToString(), "0xffffffffcccc0000");
-
-	// This execute should FAIL, because snapshotting is disabled.
-	cmd->Execute(gxemul, dummyArguments);
-	UnitTest::Assert("root.step should still be 3", gxemul.GetStep(), 3);
-}
-
-static void Test_BackwardStepCommand_Basic()
-{
-	refcount_ptr<Command> cmd = new BackwardStepCommand;
-	vector<string> dummyArguments;
-	
-	GXemul gxemul;
-
-	char filename[] = "test/FileLoader_ELF_MIPS";
-	char *filenames[] = { filename };
-	gxemul.ParseFilenames("testmips", 1, filenames);
-	gxemul.Reset();
-
-	gxemul.SetSnapshottingEnabled(true);
-
-	gxemul.GetCommandInterpreter().RunCommand("step 3");
-	gxemul.Execute();
-
-	UnitTest::Assert("root.step should initially be 3", gxemul.GetStep(), 3);
-
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("cpu0");
-	UnitTest::Assert("3: cpu0.pc", cpu->GetVariable("pc")->ToString(), "0xffffffff80010104");
-	UnitTest::Assert("3: cpu0.sp", cpu->GetVariable("sp")->ToString(), "0xffffffffa0007ed0");
-	UnitTest::Assert("3: cpu0.v0", cpu->GetVariable("v0")->ToString(), "0xffffffff88880000");
-	UnitTest::Assert("3: cpu0.v1", cpu->GetVariable("v1")->ToString(), "0xffffffffcccc0000");
-
-	cmd->Execute(gxemul, dummyArguments);
-	UnitTest::Assert("root.step should be 2", gxemul.GetStep(), 2);
-	cpu = gxemul.GetRootComponent()->LookupPath("cpu0");
-	UnitTest::Assert("2: cpu0.pc", cpu->GetVariable("pc")->ToString(), "0xffffffff80010100");
-	UnitTest::Assert("2: cpu0.sp", cpu->GetVariable("sp")->ToString(), "0xffffffffa0007ed0");
-	UnitTest::Assert("2: cpu0.v0", cpu->GetVariable("v0")->ToString(), "0");
-	UnitTest::Assert("2: cpu0.v1", cpu->GetVariable("v1")->ToString(), "0xffffffffcccc0000");
-
-	cmd->Execute(gxemul, dummyArguments);
-	UnitTest::Assert("root.step should be 1", gxemul.GetStep(), 1);
-	cpu = gxemul.GetRootComponent()->LookupPath("cpu0");
-	UnitTest::Assert("1: cpu0.pc", cpu->GetVariable("pc")->ToString(), "0xffffffff800100fc");
-	UnitTest::Assert("1: cpu0.sp", cpu->GetVariable("sp")->ToString(), "0xffffffffa0007ed0");
-	UnitTest::Assert("1: cpu0.v0", cpu->GetVariable("v0")->ToString(), "0");
-	UnitTest::Assert("1: cpu0.v1", cpu->GetVariable("v1")->ToString(), "0");
-
-	cmd->Execute(gxemul, dummyArguments);
-	UnitTest::Assert("root.step should be 0", gxemul.GetStep(), 0);
-	cpu = gxemul.GetRootComponent()->LookupPath("cpu0");
-	UnitTest::Assert("0: cpu0.pc", cpu->GetVariable("pc")->ToString(), "0xffffffff800100f8");
-	UnitTest::Assert("0: cpu0.sp", cpu->GetVariable("sp")->ToString(), "0xffffffffa0007f00");
-	UnitTest::Assert("0: cpu0.v0", cpu->GetVariable("v0")->ToString(), "0");
-	UnitTest::Assert("0: cpu0.v1", cpu->GetVariable("v1")->ToString(), "0");
-
-	cmd->Execute(gxemul, dummyArguments);
-	UnitTest::Assert("root.step should still be 0", gxemul.GetStep(), 0);
-	cpu = gxemul.GetRootComponent()->LookupPath("cpu0");
-	UnitTest::Assert("X: cpu0.pc", cpu->GetVariable("pc")->ToString(), "0xffffffff800100f8");
-	UnitTest::Assert("X: cpu0.sp", cpu->GetVariable("sp")->ToString(), "0xffffffffa0007f00");
-	UnitTest::Assert("X: cpu0.v0", cpu->GetVariable("v0")->ToString(), "0");
-	UnitTest::Assert("X: cpu0.v1", cpu->GetVariable("v1")->ToString(), "0");
-}
-
-// Reset resets the component tree, but does not load back the binary!
-static void Test_BackwardStepCommand_ManualAddAndLoad()
-{
-	refcount_ptr<Command> cmd = new BackwardStepCommand;
-	vector<string> dummyArguments;
-	
-	GXemul gxemul;
-
-	gxemul.GetCommandInterpreter().RunCommand("add testmips");
-	gxemul.GetCommandInterpreter().RunCommand("load test/FileLoader_ELF_MIPS cpu0");
-	gxemul.SetSnapshottingEnabled(true);
-	gxemul.GetCommandInterpreter().RunCommand("step 3");
-	gxemul.Execute();
-
-	UnitTest::Assert("root.step should initially be 3", gxemul.GetStep(), 3);
-
-	refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("cpu0");
-	UnitTest::Assert("3: cpu0.pc", cpu->GetVariable("pc")->ToString(), "0xffffffff80010104");
-	UnitTest::Assert("3: cpu0.sp", cpu->GetVariable("sp")->ToString(), "0xffffffffa0007ed0");
-	UnitTest::Assert("3: cpu0.v0", cpu->GetVariable("v0")->ToString(), "0xffffffff88880000");
-	UnitTest::Assert("3: cpu0.v1", cpu->GetVariable("v1")->ToString(), "0xffffffffcccc0000");
-
-	cmd->Execute(gxemul, dummyArguments);
-	UnitTest::Assert("root.step should be 2", gxemul.GetStep(), 2);
-	cpu = gxemul.GetRootComponent()->LookupPath("cpu0");
-	UnitTest::Assert("2: cpu0.pc", cpu->GetVariable("pc")->ToString(), "0xffffffff80010100");
-	UnitTest::Assert("2: cpu0.sp", cpu->GetVariable("sp")->ToString(), "0xffffffffa0007ed0");
-	UnitTest::Assert("2: cpu0.v0", cpu->GetVariable("v0")->ToString(), "0");
-	UnitTest::Assert("2: cpu0.v1", cpu->GetVariable("v1")->ToString(), "0xffffffffcccc0000");
-
-	cmd->Execute(gxemul, dummyArguments);
-	UnitTest::Assert("root.step should be 1", gxemul.GetStep(), 1);
-	cpu = gxemul.GetRootComponent()->LookupPath("cpu0");
-	UnitTest::Assert("1: cpu0.pc", cpu->GetVariable("pc")->ToString(), "0xffffffff800100fc");
-	UnitTest::Assert("1: cpu0.sp", cpu->GetVariable("sp")->ToString(), "0xffffffffa0007ed0");
-	UnitTest::Assert("1: cpu0.v0", cpu->GetVariable("v0")->ToString(), "0");
-	UnitTest::Assert("1: cpu0.v1", cpu->GetVariable("v1")->ToString(), "0");
-
-	cmd->Execute(gxemul, dummyArguments);
-	UnitTest::Assert("root.step should be 0", gxemul.GetStep(), 0);
-	cpu = gxemul.GetRootComponent()->LookupPath("cpu0");
-	UnitTest::Assert("0: cpu0.pc", cpu->GetVariable("pc")->ToString(), "0xffffffff800100f8");
-	UnitTest::Assert("0: cpu0.sp", cpu->GetVariable("sp")->ToString(), "0xffffffffa0007f00");
-	UnitTest::Assert("0: cpu0.v0", cpu->GetVariable("v0")->ToString(), "0");
-	UnitTest::Assert("0: cpu0.v1", cpu->GetVariable("v1")->ToString(), "0");
-
-	cmd->Execute(gxemul, dummyArguments);
-	UnitTest::Assert("root.step should still be 0", gxemul.GetStep(), 0);
-	cpu = gxemul.GetRootComponent()->LookupPath("cpu0");
-	UnitTest::Assert("X: cpu0.pc", cpu->GetVariable("pc")->ToString(), "0xffffffff800100f8");
-	UnitTest::Assert("X: cpu0.sp", cpu->GetVariable("sp")->ToString(), "0xffffffffa0007f00");
-	UnitTest::Assert("X: cpu0.v0", cpu->GetVariable("v0")->ToString(), "0");
-	UnitTest::Assert("X: cpu0.v1", cpu->GetVariable("v1")->ToString(), "0");
-}
-
-UNITTESTS(BackwardStepCommand)
-{
-	UNITTEST(Test_BackwardStepCommand_AlreadyAtStep0);
-	UNITTEST(Test_BackwardStepCommand_NotWhenSnapshotsAreDisabled);
-	UNITTEST(Test_BackwardStepCommand_Basic);
-	UNITTEST(Test_BackwardStepCommand_ManualAddAndLoad);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/commands/CloseCommand.cc gxemul-0.7.0+dfsg/src/main/commands/CloseCommand.cc
--- gxemul-0.6.2/src/main/commands/CloseCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/CloseCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,62 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/CloseCommand.h"
-#include "GXemul.h"
-
-
-CloseCommand::CloseCommand()
-	: Command("close", "")
-{
-}
-
-
-CloseCommand::~CloseCommand()
-{
-}
-
-
-bool CloseCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	gxemul.ClearEmulation();
-	return true;
-}
-
-
-string CloseCommand::GetShortDescription() const
-{
-	return "Discards (closes) the current emulation.";
-}
-
-
-string CloseCommand::GetLongDescription() const
-{
-	return "Closes (discards) the current emulation.\n"
-	    "\n"
-	    "See also:  load    (to load an existing emulation)\n";
-}
-
diff -Nru gxemul-0.6.2/src/main/commands/ContinueBackwardsCommand.cc gxemul-0.7.0+dfsg/src/main/commands/ContinueBackwardsCommand.cc
--- gxemul-0.6.2/src/main/commands/ContinueBackwardsCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/ContinueBackwardsCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,77 +0,0 @@
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/ContinueBackwardsCommand.h"
-#include "GXemul.h"
-
-
-ContinueBackwardsCommand::ContinueBackwardsCommand()
-	: Command("continue-backwards", "")
-{
-}
-
-
-ContinueBackwardsCommand::~ContinueBackwardsCommand()
-{
-}
-
-
-bool ContinueBackwardsCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	gxemul.GetUI()->ShowDebugMessage("TODO\n");
-	return false;
-}
-
-
-string ContinueBackwardsCommand::GetShortDescription() const
-{
-	return "Runs the emulation backwards.";
-}
-
-
-string ContinueBackwardsCommand::GetLongDescription() const
-{
-	return "Runs the emulation backwards.";
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_ContinueBackwardsCommand_Test()
-{
-	// TODO
-}
-
-UNITTESTS(ContinueBackwardsCommand)
-{
-	UNITTEST(Test_ContinueBackwardsCommand_Test);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/commands/ContinueCommand.cc gxemul-0.7.0+dfsg/src/main/commands/ContinueCommand.cc
--- gxemul-0.6.2/src/main/commands/ContinueCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/ContinueCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,90 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/ContinueCommand.h"
-#include "GXemul.h"
-
-
-ContinueCommand::ContinueCommand()
-	: Command("continue", "")
-{
-}
-
-
-ContinueCommand::~ContinueCommand()
-{
-}
-
-
-bool ContinueCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	gxemul.SetRunState(GXemul::Running);
-	return true;
-}
-
-
-string ContinueCommand::GetShortDescription() const
-{
-	return "Continues the current emulation.";
-}
-
-
-string ContinueCommand::GetLongDescription() const
-{
-	return "Continues the emulation.\n"
-	    "\n"
-	    "See also:  step      (to single-step forward)\n";
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_ContinueCommand_Affect_RunState()
-{
-	refcount_ptr<Command> cmd = new ContinueCommand;
-	vector<string> dummyArguments;
-	
-	GXemul gxemul;
-
-	UnitTest::Assert("the default GXemul instance should be Paused",
-	    gxemul.GetRunState() == GXemul::Paused);
-
-	cmd->Execute(gxemul, dummyArguments);
-
-	UnitTest::Assert("runstate should have been changed to Running",
-	    gxemul.GetRunState() == GXemul::Running);
-}
-
-UNITTESTS(ContinueCommand)
-{
-	UNITTEST(Test_ContinueCommand_Affect_RunState);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/commands/CopyComponentCommand.cc gxemul-0.7.0+dfsg/src/main/commands/CopyComponentCommand.cc
--- gxemul-0.6.2/src/main/commands/CopyComponentCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/CopyComponentCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,196 +0,0 @@
-/*
- *  Copyright (C) 2009-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/CopyComponentCommand.h"
-#include "GXemul.h"
-
-
-CopyComponentCommand::CopyComponentCommand()
-	: Command("copy", "path-from path-to")
-{
-}
-
-
-CopyComponentCommand::~CopyComponentCommand()
-{
-}
-
-
-static void ShowMsg(GXemul& gxemul, const string& msg)
-{
-	gxemul.GetUI()->ShowDebugMessage(msg);
-}
-
-
-bool CopyComponentCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	if (arguments.size() != 2) {
-		ShowMsg(gxemul, "syntax: copy path-from path-to\n");
-		return false;
-	}
-
-	string pathFrom = arguments[0];
-	string pathTo = arguments[1];
-
-	vector<string> matchesFrom = gxemul.GetRootComponent()->
-	    FindPathByPartialMatch(pathFrom);
-	if (matchesFrom.size() == 0) {
-		ShowMsg(gxemul, pathFrom + " is not a path to a known component.\n");
-		return false;
-	}
-	if (matchesFrom.size() > 1) {
-		ShowMsg(gxemul, pathFrom + " matches multiple components:\n");
-		for (size_t i=0; i<matchesFrom.size(); i++)
-			ShowMsg(gxemul, "  " + matchesFrom[i] + "\n");
-		return false;
-	}
-
-	vector<string> matchesTo = gxemul.GetRootComponent()->
-	    FindPathByPartialMatch(pathTo);
-	if (matchesTo.size() == 0) {
-		ShowMsg(gxemul, pathTo + " is not a path to a known component.\n");
-		return false;
-	}
-	if (matchesTo.size() > 1) {
-		ShowMsg(gxemul, pathTo + " matches multiple components:\n");
-		for (size_t i=0; i<matchesTo.size(); i++)
-			ShowMsg(gxemul, "  " + matchesTo[i] + "\n");
-		return false;
-	}
-
-
-	refcount_ptr<Component> whatToCopy =
-	    gxemul.GetRootComponent()->LookupPath(matchesFrom[0]);
-	if (whatToCopy.IsNULL()) {
-		ShowMsg(gxemul, "Lookup of origin path " + pathFrom + " failed.\n");
-		return false;
-	}
-
-	refcount_ptr<Component> clone = whatToCopy->Clone();
-	if (clone.IsNULL()) {
-		ShowMsg(gxemul, "Failed to clone " + pathFrom + ".\n");
-		return false;
-	}
-
-	refcount_ptr<Component> whereToAddIt =
-	    gxemul.GetRootComponent()->LookupPath(matchesTo[0]);
-	if (whereToAddIt.IsNULL()) {
-		ShowMsg(gxemul, "Lookup of destination path " + pathTo + " failed.\n");
-		return false;
-	}
-
-	whereToAddIt->AddChild(clone);
-
-	return true;
-}
-
-
-string CopyComponentCommand::GetShortDescription() const
-{
-	return "Copies (clones) a component.";
-}
-
-
-string CopyComponentCommand::GetLongDescription() const
-{
-	return
-	    "Copies a component (given a path) from one place in the configuration\n"
-	    "tree to another. The following example duplicates a CPU component:\n"
-	    "\n"
-	    "> root\n" 
-	    "  root\n"
-	    "  \\-- machine0  [testmips]\n"
-	    "      \\-- mainbus0\n"
-	    "          |-- ram0  (32 MB at offset 0)\n"
-	    "          |-- rom0  (16 MB at offset 0x1fc00000)\n"
-	    "          \\-- cpu0  (MIPS, 100 MHz)\n"
-	    "> copy cpu0 mainbus\n" 
-	    "> root\n" 
-	    "  root\n"
-	    "  \\-- machine0  [testmips]\n"
-	    "      \\-- mainbus0\n"
-	    "          |-- ram0  (32 MB at offset 0)\n"
-	    "          |-- rom0  (16 MB at offset 0x1fc00000)\n"
-	    "          |-- cpu0  (MIPS, 100 MHz)\n"
-	    "          \\-- cpu1  (MIPS, 100 MHz)\n"
-	    "\n"
-	    "(Note that the cloned CPU was automatically renamed to cpu1, to avoid a\n"
-	    "collision.)\n"
-	    "\n"
-	    "See also:  add       (to add new components)\n"
-	    "           move      (to move components within the tree)\n"
-	    "           remove    (to remove components)\n"
-	    "           root      (to inspect the current emulation setup)\n";
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_CopyComponentCommand_Copy()
-{
-	GXemul gxemul;
-
-	gxemul.GetCommandInterpreter().RunCommand("add testm88k");
-
-	refcount_ptr<Component> root = gxemul.GetRootComponent();
-	UnitTest::Assert("there should initially be 1 entry under root",
-	    root->GetChildren().size(), 1);
-
-	gxemul.GetCommandInterpreter().RunCommand("copy machine0 root");
-
-	// The tree should now look SOMETHING like:
-	//   root
-	//   |-- machine0  [testm88k]
-	//   |   \-- mainbus0
-	//   |       |-- ram0  (32 MB at offset 0)
-	//   |       |-- rom0  (4 MB at offset 0xff800000)
-	//   |       \-- cpu0  (88100, 50 MHz)
-	//   \-- machine1  [testm88k]
-	//       \-- mainbus0
-	//           |-- ram0  (32 MB at offset 0)
-	//           |-- rom0  (4 MB at offset 0xff800000)
-	//           \-- cpu0  (88100, 50 MHz)
-
-	UnitTest::Assert("there should now be 2 entries (machine0 and machine1) under root",
-	    root->GetChildren().size(), 2);
-
-	refcount_ptr<Component> machine0 = root->GetChildren()[0];
-	refcount_ptr<Component> machine1 = root->GetChildren()[1];
-
-	UnitTest::Assert("name 0 mismatch", machine0->GetVariable("name")->ToString(), "machine0");
-	UnitTest::Assert("name 1 mismatch", machine1->GetVariable("name")->ToString(), "machine1");
-}
-
-UNITTESTS(CopyComponentCommand)
-{
-	UNITTEST(Test_CopyComponentCommand_Copy);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/commands/HelpCommand.cc gxemul-0.7.0+dfsg/src/main/commands/HelpCommand.cc
--- gxemul-0.6.2/src/main/commands/HelpCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/HelpCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,166 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/HelpCommand.h"
-#include "GXemul.h"
-
-
-HelpCommand::HelpCommand()
-	: Command("help", "[command-name]")
-{
-}
-
-
-HelpCommand::~HelpCommand()
-{
-}
-
-
-bool HelpCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	const Commands& commands = gxemul.GetCommandInterpreter().GetCommands();
-	Commands::const_iterator it;
-
-	if (arguments.size() > 1) {
-		gxemul.GetUI()->ShowDebugMessage("usage: help [cmd]\n");
-		return false;
-	}
-
-	if (arguments.size() == 1) {
-		// Special case: root isn't really a command
-		if (arguments[0] == "root") {
-			gxemul.GetUI()->ShowDebugMessage(
-			    "\nroot\n----\n\n"
-			    "Shows the component tree which makes up the current emulation configuration.\n"
-			    "Technically, 'root' is not a command, but the name of the root node. Typing\n"
-			    "the name of any node in the configuration tree will dump the sub-tree starting\n"
-			    "at that node, followed by that node's own variables.\n\n");
-			return true;
-		}
-		
-		it = commands.find(arguments[0]);
-		if (it == commands.end()) {
-			gxemul.GetUI()->ShowDebugMessage(
-			    "Command \"" + arguments[0] + "\" unknown.\n");
-			return false;
-		}
-		
-		// command name + " " + argument format
-		// ------------------------------------
-		//
-		// Long description.
-
-		string longhelp = arguments[0];
-		const string& argumentFormat = it->second->GetArgumentFormat();
-		if (argumentFormat != "")
-			longhelp += " " + argumentFormat;
-		int len = longhelp.length();
-
-		longhelp += "\n";
-		for (int i=0; i<len; i++)
-			longhelp += "-";
-		
-		longhelp += "\n\n" + it->second->GetLongDescription();
-		if (longhelp[longhelp.length() - 1] != '\n')
-			longhelp += '\n';
-		
-		gxemul.GetUI()->ShowDebugMessage("\n" + longhelp + "\n");
-
-		if (it->second->MayBeReexecutedWithoutArgs())
-			gxemul.GetUI()->ShowDebugMessage(
-			    "This command will be re-executed (without "
-			    "arguments), if an empty command\n"
-			    "line is issued.\n\n");
-
-		return true;
-	}
-
-	// Find the longest name + argument:
-	size_t longest = 0;
-	for (it = commands.begin(); it != commands.end(); ++ it) {
-		const Command& command = *it->second;
-		size_t len = command.GetCommandName().length();
-
-		if (command.GetArgumentFormat() != "")
-			len += 1 + command.GetArgumentFormat().length();
-
-		if (len > longest)
-			longest = len;
-	}
-
-	// Show all commands followed by their short descriptions:
-	for (it = commands.begin(); it != commands.end(); ++ it) {
-		const Command& command = *it->second;
-
-		const string leadingSpaces = "  ";
-		const int nLeadingSpaces = 2;
-
-		string str = leadingSpaces + command.GetCommandName();
-		if (command.GetArgumentFormat() != "")
-			str += " " + command.GetArgumentFormat();
-
-		while (str.length() < longest + nLeadingSpaces)
-			str += " ";
-		
-		str += "  " + command.GetShortDescription();
-
-		gxemul.GetUI()->ShowDebugMessage(str + "\n");
-	}
-
-	// ... followed by a short description of other possible commands:
-	gxemul.GetUI()->ShowDebugMessage("  ------------------------------"
-	    "----------------------------------------------\n");
-	gxemul.GetUI()->ShowDebugMessage("  root                    "
-	"Shows the entire component tree.\n");
-	gxemul.GetUI()->ShowDebugMessage("  <name>                  "
-	"Shows the component tree, from the named component.\n");
-	gxemul.GetUI()->ShowDebugMessage("  <name>.<method>         "
-	    "Executes a method of a named component.\n");
-	gxemul.GetUI()->ShowDebugMessage("  <name>.<var>            "
-	    "Prints the value of a variable of a named component.\n");
-	gxemul.GetUI()->ShowDebugMessage("  <name>.<var> = <value>  "
-	    "Assigns a value to a variable of a named component.\n");
-
-	return true;
-}
-
-
-string HelpCommand::GetShortDescription() const
-{
-	return "Shows a help message.";
-}
-
-
-string HelpCommand::GetLongDescription() const
-{
-	return "Shows a summary of all available commands, or, "
-	    "when given a specific command\n"
-	    "name as an argument, shows a detailed description about "
-	    "that command.\n";
-}
-
-
diff -Nru gxemul-0.6.2/src/main/commands/ListComponentsCommand.cc gxemul-0.7.0+dfsg/src/main/commands/ListComponentsCommand.cc
--- gxemul-0.6.2/src/main/commands/ListComponentsCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/ListComponentsCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,88 +0,0 @@
-/*
- *  Copyright (C) 2008-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/ListComponentsCommand.h"
-#include "ComponentFactory.h"
-#include "GXemul.h"
-
-
-ListComponentsCommand::ListComponentsCommand()
-	: Command("list-components", "")
-{
-}
-
-
-ListComponentsCommand::~ListComponentsCommand()
-{
-}
-
-
-bool ListComponentsCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	vector<string> allComponents =
-	    ComponentFactory::GetAllComponentNames(false);
-
-	size_t maxLen = 0;
-	size_t i;
-	for (i=0; i<allComponents.size(); i++)
-		if (allComponents[i].length() > maxLen)
-			maxLen = allComponents[i].length();
-
-	for (i=0; i<allComponents.size(); i++) {
-		stringstream msg;
-		const string& name = allComponents[i];
-		refcount_ptr<Component> creatable =
-		    ComponentFactory::CreateComponent(name);
-		if (creatable.IsNULL()) {
-			// msg << "  (un-creatable)";
-			continue;
-		}
-
-		msg << "  " + name;
-		for (size_t j = 0; j < 3 + maxLen - name.length(); j++)
-			msg << " ";
-		msg << ComponentFactory::GetAttribute(name, "description");
-		msg << "\n";
-
-		gxemul.GetUI()->ShowDebugMessage(msg.str());
-	}
-
-	return true;
-}
-
-
-string ListComponentsCommand::GetShortDescription() const
-{
-	return "Displays all available components.";
-}
-
-
-string ListComponentsCommand::GetLongDescription() const
-{
-	return "Displays a list of all available components.";
-}
-
diff -Nru gxemul-0.6.2/src/main/commands/LoadCommand.cc gxemul-0.7.0+dfsg/src/main/commands/LoadCommand.cc
--- gxemul-0.6.2/src/main/commands/LoadCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/LoadCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,261 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <fstream>
-#include <stdlib.h>
-#include <string.h>
-
-#include "commands/LoadCommand.h"
-#include "FileLoader.h"
-#include "GXemul.h"
-
-
-LoadCommand::LoadCommand()
-	: Command("load", "[filename [component-path]]")
-{
-}
-
-
-LoadCommand::~LoadCommand()
-{
-}
-
-
-static void ShowMsg(GXemul& gxemul, const string& msg)
-{
-	gxemul.GetUI()->ShowDebugMessage(msg);
-}
-
-
-bool LoadCommand::IsComponentTree(GXemul& gxemul, const string& filename) const
-{
-	std::ifstream file(filename.c_str());
-	if (file.fail())
-		return false;
-
-	char buf[256];
-	file.read(buf, sizeof(buf));
-	if (file.gcount() < 10)
-		return false;
-
-	// Saved component trees start with the string "component ".
-	return (strncmp(buf, "component ", 10) == 0);
-}
-
-
-bool LoadCommand::LoadComponentTree(GXemul& gxemul, const string&filename,
-	refcount_ptr<Component> specifiedComponent) const
-{
-	const string extension = ".gxemul";
-	if (filename.length() < extension.length() || filename.substr(
-	    filename.length() - extension.length()) != extension)
-		ShowMsg(gxemul, "Warning: the name " + filename +
-		    " does not have a .gxemul extension. Continuing anyway.\n");
-
-	refcount_ptr<Component> component;
-
-	// Load from the file
-	std::ifstream file(filename.c_str());
-	if (file.fail()) {
-		ShowMsg(gxemul, "Unable to open " + filename + " for reading.\n");
-		return false;
-	}
-
-	// Figure out the file's size:
-	file.seekg(0, std::ios::end);
-	std::streampos fileSize = file.tellg();
-	file.seekg(0, std::ios::beg);
-
-	// Read the entire file into a string.
-	// TODO: This is wasteful, of course. It actually takes twice the
-	// size of the file, since the string constructor generates a _copy_.
-	// But string takes care of unicode and such (if compiled as ustring).
-	vector<char> buf;
-	buf.resize((size_t)fileSize + 1);
-
-	memset(&buf[0], 0, fileSize);
-	file.read(&buf[0], fileSize);
-	if (file.gcount() != fileSize) {
-		ShowMsg(gxemul, "Loading from " + filename + " failed; "
-		    "could not read all of the file?\n");
-		return false;
-	}
-
-	string str(&buf[0], fileSize);
-
-	file.close();
-
-	size_t strPos = 0;
-	stringstream messages;
-	component = Component::Deserialize(messages, str, strPos);
-
-	if (messages.str().length() > 0)
-		ShowMsg(gxemul, messages.str());
-
-	if (component.IsNULL()) {
-		ShowMsg(gxemul, "Loading from " + filename + " failed; "
-		    "no component found?\n");
-		return false;
-	}
-
-	if (specifiedComponent.IsNULL()) {
-		const StateVariable* name = component->GetVariable("name");
-		if (name == NULL || name->ToString() != "root")
-			gxemul.GetRootComponent()->AddChild(component);
-		else
-			gxemul.SetRootComponent(component);
-
-		gxemul.SetEmulationFilename(filename);
-
-		ShowMsg(gxemul, filename + " loaded\n");
-	} else {
-		specifiedComponent->AddChild(component);
-
-		ShowMsg(gxemul, filename + " loaded into " +
-		    specifiedComponent->GenerateShortestPossiblePath() + "\n");
-	}
-
-	return true;
-}
-
-bool LoadCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	string filename = gxemul.GetEmulationFilename();
-	string path = "";
-
-	if (arguments.size() > 2) {
-		ShowMsg(gxemul, "Too many arguments.\n");
-		return false;
-	}
-
-	if (arguments.size() > 0)
-		filename = arguments[0];
-
-	if (filename == "") {
-		ShowMsg(gxemul, "No filename given.\n");
-		return false;
-	}
-
-	if (arguments.size() > 1)
-		path = arguments[1];
-
-	// Figure out the component path, if it was specified.
-	refcount_ptr<Component> specifiedComponent;
-	if (path != "") {
-		vector<string> matches = gxemul.GetRootComponent()->
-		    FindPathByPartialMatch(path);
-		if (matches.size() == 0) {
-			ShowMsg(gxemul, path +
-			    " is not a path to a known component.\n");
-			return false;
-		}
-		if (matches.size() > 1) {
-			ShowMsg(gxemul, path +
-			    " matches multiple components:\n");
-			for (size_t i=0; i<matches.size(); i++)
-				ShowMsg(gxemul, "  " + matches[i] + "\n");
-			return false;
-		}
-
-		specifiedComponent =
-		    gxemul.GetRootComponent()->LookupPath(matches[0]);
-		if (specifiedComponent.IsNULL()) {
-			ShowMsg(gxemul, "Lookup of " + path + " failed.\n");
-			return false;
-		}
-	}
-
-	// 1. Is it a component tree?
-	if (IsComponentTree(gxemul, filename)) {
-		if (specifiedComponent.IsNULL())
-			gxemul.ClearEmulation();
-
-		return LoadComponentTree(gxemul, filename, specifiedComponent);
-	}
-
-	if (specifiedComponent.IsNULL()) {
-		ShowMsg(gxemul, "The specified file to load (" + filename +
-		    ") is not a configuration tree. If it is a binary to load,"
-		    " you need to specify a component path where to load the"
-		    " binary.\n");
-		return false;
-	}
-
-	// 2. Is it a binary (ELF, a.out, ...)?
-	FileLoader fileLoader(filename);
-	stringstream messages;
-	if (fileLoader.Load(specifiedComponent, messages)) {
-		gxemul.GetUI()->ShowDebugMessage(specifiedComponent,
-		    filename + " loaded\n" + messages.str());
-		return true;
-	} else {
-		gxemul.GetUI()->ShowDebugMessage(specifiedComponent,
-		    "FAILED to load " + filename + "\n" + messages.str());
-		return false;
-	}
-}
-
-
-string LoadCommand::GetShortDescription() const
-{
-	return "Loads a file.";
-}
-
-
-string LoadCommand::GetLongDescription() const
-{
-	return 
-	    "Loads a file into a location in the component tree. There are two different\n"
-	    "uses, which all share the same general syntax but differ in meaning.\n"
-	    "\n"
-	    "1. Loads an emulation setup (.gxemul) which was previously saved with the\n"
-	    "   'save' command. For example, if a machine was previously saved into\n"
-	    "   myMachine.gxemul, then\n"
-	    "\n"
-	    "       load myMachine.gxemul root\n"
-	    "\n"
-	    "   will add the machine to the current emulation tree, next to any other\n"
-	    "   machines.\n"
-	    "\n"
-	    "       load myMachine.gxemul\n"
-	    "\n"
-	    "   will instead replace the whole configuration tree with what's in\n"
-	    "   myMachine.gxemul. The filename may be omitted, if it is known from an\n"
-	    "   earlier save or load command.\n"
-	    "\n"
-	    "2. Loads a binary (ELF, a.out, ...) into a CPU or data bus. E.g.:\n"
-	    "\n"
-	    "       load netbsd-RAMDISK cpu0\n"
-	    "\n"
-	    "   will load a NetBSD kernel into cpu0 (assuming that cpu0 is not ambiguous).\n"
-	    "   The reason why files should be loaded into CPUs and not into RAM components\n"
-	    "   is that binaries are often linked to virtual addresses, and the CPU does\n"
-	    "   virtual to physical address translation.\n"
-	    "\n"
-	    "See also:  save    (to save an emulation to a file)\n";
-}
-
diff -Nru gxemul-0.6.2/src/main/commands/Makefile.skel gxemul-0.7.0+dfsg/src/main/commands/Makefile.skel
--- gxemul-0.6.2/src/main/commands/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,25 +0,0 @@
-#
-#  Makefile for GXemul src/main/commands
-#
-
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(CPEDANTIC) $(INCLUDE2)
-LIBS=$(OTHERLIBS)
-
-OBJS=AddComponentCommand.o BackwardStepCommand.o CloseCommand.o \
-	ContinueBackwardsCommand.o ContinueCommand.o CopyComponentCommand.o \
-	HelpCommand.o \
-	LoadCommand.o ListComponentsCommand.o MoveComponentCommand.o \
-	PauseCommand.o \
-	QuitCommand.o RemoveComponentCommand.o ResetCommand.o \
-	SaveCommand.o StatusCommand.o StepCommand.o VersionCommand.o
-
-all: $(OBJS)
-
-$(OBJS): Makefile
-
-clean:
-	rm -f $(OBJS)
-
-clean_all: clean
-	rm -f Makefile
-
diff -Nru gxemul-0.6.2/src/main/commands/MoveComponentCommand.cc gxemul-0.7.0+dfsg/src/main/commands/MoveComponentCommand.cc
--- gxemul-0.6.2/src/main/commands/MoveComponentCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/MoveComponentCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,200 +0,0 @@
-/*
- *  Copyright (C) 2009-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/MoveComponentCommand.h"
-#include "GXemul.h"
-
-
-MoveComponentCommand::MoveComponentCommand()
-	: Command("move", "path-from path-to")
-{
-}
-
-
-MoveComponentCommand::~MoveComponentCommand()
-{
-}
-
-
-static void ShowMsg(GXemul& gxemul, const string& msg)
-{
-	gxemul.GetUI()->ShowDebugMessage(msg);
-}
-
-
-bool MoveComponentCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	if (arguments.size() != 2) {
-		ShowMsg(gxemul, "syntax: move path-from path-to\n");
-		return false;
-	}
-
-	string pathFrom = arguments[0];
-	string pathTo = arguments[1];
-
-	vector<string> matchesFrom = gxemul.GetRootComponent()->
-	    FindPathByPartialMatch(pathFrom);
-	if (matchesFrom.size() == 0) {
-		ShowMsg(gxemul, pathFrom + " is not a path to a known component.\n");
-		return false;
-	}
-	if (matchesFrom.size() > 1) {
-		ShowMsg(gxemul, pathFrom + " matches multiple components:\n");
-		for (size_t i=0; i<matchesFrom.size(); i++)
-			ShowMsg(gxemul, "  " + matchesFrom[i] + "\n");
-		return false;
-	}
-
-	vector<string> matchesTo = gxemul.GetRootComponent()->
-	    FindPathByPartialMatch(pathTo);
-	if (matchesTo.size() == 0) {
-		ShowMsg(gxemul, pathTo + " is not a path to a known component.\n");
-		return false;
-	}
-	if (matchesTo.size() > 1) {
-		ShowMsg(gxemul, pathTo + " matches multiple components:\n");
-		for (size_t i=0; i<matchesTo.size(); i++)
-			ShowMsg(gxemul, "  " + matchesTo[i] + "\n");
-		return false;
-	}
-
-
-	refcount_ptr<Component> whatToMove =
-	    gxemul.GetRootComponent()->LookupPath(matchesFrom[0]);
-	if (whatToMove.IsNULL()) {
-		ShowMsg(gxemul, "Lookup of origin path " + pathFrom + " failed.\n");
-		return false;
-	}
-
-	refcount_ptr<Component> parent = whatToMove->GetParent();
-	if (parent.IsNULL()) {
-		ShowMsg(gxemul, "Cannot find the component's parent.\n");
-		return false;
-	}
-
-	refcount_ptr<Component> whereToAddIt =
-	    gxemul.GetRootComponent()->LookupPath(matchesTo[0]);
-	if (whereToAddIt.IsNULL()) {
-		ShowMsg(gxemul, "Lookup of destination path " + pathTo + " failed.\n");
-		return false;
-	}
-
-	parent->RemoveChild(whatToMove);
-	whereToAddIt->AddChild(whatToMove);
-
-	return true;
-}
-
-
-string MoveComponentCommand::GetShortDescription() const
-{
-	return "Moves a component within the tree.";
-}
-
-
-string MoveComponentCommand::GetLongDescription() const
-{
-	return
-	    "Moves a component (given a path) from one place in the configuration\n"
-	    "tree to another. Example: Let's say a CPU component has by accident\n"
-	    "been added outside of the machine's mainbus0 (where it is supposed to\n"
-	    "be located). The move command fixes the problem:\n"
-	    "\n"
-	    "> add testmips\n"
-	    "> add mips_cpu \n"
-	    "> root\n" 
-	    "  root\n"
-	    "  |-- machine0  [testmips]\n"
-	    "  |   \\-- mainbus0\n"
-	    "  |       |-- ram0  (32 MB at offset 0)\n"
-	    "  |       |-- rom0  (16 MB at offset 0x1fc00000)\n"
-	    "  |       \\-- cpu0  (MIPS, 100 MHz)\n"
-	    "  \\-- cpu0  (MIPS, 100 MHz)\n"
-	    "> move root.cpu0 mainbus0 \n"
-	    "> root\n" 
-	    "  root\n"
-	    "  \\-- machine0  [testmips]\n"
-	    "      \\-- mainbus0\n"
-	    "          |-- ram0  (32 MB at offset 0)\n"
-	    "          |-- rom0  (16 MB at offset 0x1fc00000)\n"
-	    "          |-- cpu0  (MIPS, 100 MHz)\n"
-	    "          \\-- cpu1  (MIPS, 100 MHz)\n"
-	    "\n"
-	    "(Note that the moved cpu was automatically renamed to cpu1, to avoid a\n"
-	    "collision.)\n"
-	    "\n"
-	    "See also:  add     (to add new components)\n"
-	    "           root    (to inspect the current emulation setup)\n";
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_MoveComponentCommand_Move()
-{
-	GXemul gxemul;
-
-	gxemul.GetCommandInterpreter().RunCommand("add testm88k");
-	gxemul.GetCommandInterpreter().RunCommand("add ram");
-
-	refcount_ptr<Component> root = gxemul.GetRootComponent();
-	UnitTest::Assert("there should be 2 entries under root",
-	    root->GetChildren().size(), 2);
-
-	gxemul.GetCommandInterpreter().RunCommand("move root.ram mainbus");
-
-	// The tree should now look like:
-	//   root
-	//   \-- machine0  [testm88k]
-	//       \-- mainbus0
-	//           |-- cpu0  (88100, 50 MHz)
-	//           |-- ram0  (32 MB at offset 0)
-	//           \-- ram1  (0 bytes at offset 0)
-
-	UnitTest::Assert("there should now be 1 entry (machine0) under root",
-	    root->GetChildren().size(), 1);
-
-	refcount_ptr<Component> machine0 = root->GetChildren()[0];
-
-	UnitTest::Assert("there should be 1 entry (mainbus0) under machine0",
-	    machine0->GetChildren().size(), 1);
-
-	refcount_ptr<Component> mainbus0 = machine0->GetChildren()[0];
-
-	UnitTest::Assert("there should be 5 components on mainbus0",
-	    mainbus0->GetChildren().size(), 5);
-}
-
-UNITTESTS(MoveComponentCommand)
-{
-	UNITTEST(Test_MoveComponentCommand_Move);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/commands/PauseCommand.cc gxemul-0.7.0+dfsg/src/main/commands/PauseCommand.cc
--- gxemul-0.6.2/src/main/commands/PauseCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/PauseCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,94 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/PauseCommand.h"
-#include "GXemul.h"
-
-
-PauseCommand::PauseCommand()
-	: Command("pause", "")
-{
-}
-
-
-PauseCommand::~PauseCommand()
-{
-}
-
-
-bool PauseCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	gxemul.SetRunState(GXemul::Paused);
-	return true;
-}
-
-
-string PauseCommand::GetShortDescription() const
-{
-	return "Pauses the current emulation.";
-}
-
-
-string PauseCommand::GetLongDescription() const
-{
-	return "Pauses the emulation, by setting the "
-	    "current RunState to Paused.";
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_PauseCommand_Affect_RunState()
-{
-	refcount_ptr<Command> cmd = new PauseCommand;
-	vector<string> dummyArguments;
-	
-	GXemul gxemul;
-
-	UnitTest::Assert("the default GXemul instance should be Paused",
-	    gxemul.GetRunState() == GXemul::Paused);
-
-	gxemul.SetRunState(GXemul::Running);
-
-	UnitTest::Assert("the runstate should now be Running",
-	    gxemul.GetRunState() == GXemul::Running);
-
-	cmd->Execute(gxemul, dummyArguments);
-
-	UnitTest::Assert("runstate should have been changed to Paused",
-	    gxemul.GetRunState() == GXemul::Paused);
-}
-
-UNITTESTS(PauseCommand)
-{
-	UNITTEST(Test_PauseCommand_Affect_RunState);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/commands/QuitCommand.cc gxemul-0.7.0+dfsg/src/main/commands/QuitCommand.cc
--- gxemul-0.6.2/src/main/commands/QuitCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/QuitCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,90 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/QuitCommand.h"
-#include "GXemul.h"
-
-
-QuitCommand::QuitCommand()
-	: Command("quit", "")
-{
-}
-
-
-QuitCommand::~QuitCommand()
-{
-}
-
-
-bool QuitCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	gxemul.SetRunState(GXemul::Quitting);
-	gxemul.GetUI()->Shutdown();
-	return true;
-}
-
-
-string QuitCommand::GetShortDescription() const
-{
-	return "Quits the application.";
-}
-
-
-string QuitCommand::GetLongDescription() const
-{
-	return "Quits the application.";
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_QuitCommand_Affect_RunState()
-{
-	refcount_ptr<Command> cmd = new QuitCommand;
-	vector<string> dummyArguments;
-	
-	GXemul gxemul;
-
-	UnitTest::Assert(
-	    "the default GXemul instance should be Paused",
-	    gxemul.GetRunState() == GXemul::Paused);
-
-	cmd->Execute(gxemul, dummyArguments);
-
-	UnitTest::Assert("runstate should have been changed to Quitting",
-	    gxemul.GetRunState() == GXemul::Quitting);
-}
-
-UNITTESTS(QuitCommand)
-{
-	UNITTEST(Test_QuitCommand_Affect_RunState);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/commands/RemoveComponentCommand.cc gxemul-0.7.0+dfsg/src/main/commands/RemoveComponentCommand.cc
--- gxemul-0.6.2/src/main/commands/RemoveComponentCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/RemoveComponentCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,127 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/RemoveComponentCommand.h"
-#include "GXemul.h"
-
-
-RemoveComponentCommand::RemoveComponentCommand()
-	: Command("remove", "path")
-{
-}
-
-
-RemoveComponentCommand::~RemoveComponentCommand()
-{
-}
-
-
-static void ShowMsg(GXemul& gxemul, const string& msg)
-{
-	gxemul.GetUI()->ShowDebugMessage(msg);
-}
-
-
-bool RemoveComponentCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	if (arguments.size() < 1) {
-		ShowMsg(gxemul, "No path given.\n");
-		return false;
-	}
-
-	if (arguments.size() > 1) {
-		ShowMsg(gxemul, "Too many arguments.\n");
-		return false;
-	}
-
-	string path = arguments[0];
-
-	vector<string> matches = gxemul.GetRootComponent()->
-	    FindPathByPartialMatch(path);
-	if (matches.size() == 0) {
-		ShowMsg(gxemul, path+" is not a path to a known component.\n");
-		return false;
-	}
-	if (matches.size() > 1) {
-		ShowMsg(gxemul, path+" matches multiple components:\n");
-		for (size_t i=0; i<matches.size(); i++)
-			ShowMsg(gxemul, "  " + matches[i] + "\n");
-		return false;
-	}
-
-	refcount_ptr<Component> whatToRemove =
-	    gxemul.GetRootComponent()->LookupPath(matches[0]);
-	if (whatToRemove.IsNULL()) {
-		ShowMsg(gxemul, "Lookup of " + path + " failed.\n");
-		return false;
-	}
-
-	refcount_ptr<Component> parent = whatToRemove->GetParent();
-	if (parent.IsNULL()) {
-		ShowMsg(gxemul, "Cannot remove the root component.\n");
-		return false;
-	}
-
-	parent->RemoveChild(whatToRemove);
-
-	return true;
-}
-
-
-string RemoveComponentCommand::GetShortDescription() const
-{
-	return "Removes a component from the emulation.";
-}
-
-
-string RemoveComponentCommand::GetLongDescription() const
-{
-	return
-	    "Removes a component (given a path) from the current emulation setup.\n"
-	    "The following example shows how to remove cpu1 from a particular machine:\n"
-	    "\n"
-	    "> root\n"
-	"  root\n"
-	"  \\-- machine0  [testmips]\n"
-	"      \\-- mainbus0\n"
-	"          |-- ram0  (32 MB at offset 0)\n"
-	"          |-- rom0  (16 MB at offset 0x1fc00000)\n"
-	"          |-- cpu0  (MIPS, 100 MHz)\n"
-	"          \\-- cpu1  (MIPS, 100 MHz)\n"
-	"> remove cpu1 \n"
-	"> root\n" 
-	"  root\n"
-	"  \\-- machine0  [testmips]\n"
-	"      \\-- mainbus0\n"
-	"          |-- ram0  (32 MB at offset 0)\n"
-	"          |-- rom0  (16 MB at offset 0x1fc00000)\n"
-	"          \\-- cpu0  (MIPS, 100 MHz)\n"
-	"\n"
-	    "See also:  add     (to add new components)\n"
-	    "           root    (to inspect the current emulation setup)\n";
-}
-
diff -Nru gxemul-0.6.2/src/main/commands/ResetCommand.cc gxemul-0.7.0+dfsg/src/main/commands/ResetCommand.cc
--- gxemul-0.6.2/src/main/commands/ResetCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/ResetCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,96 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/ResetCommand.h"
-#include "GXemul.h"
-
-
-ResetCommand::ResetCommand()
-	: Command("reset", "")
-{
-}
-
-
-ResetCommand::~ResetCommand()
-{
-}
-
-
-bool ResetCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	gxemul.SetRunState(GXemul::Paused);
-	gxemul.Reset();
-
-	return true;
-}
-
-
-string ResetCommand::GetShortDescription() const
-{
-	return "Resets the current emulation.";
-}
-
-
-string ResetCommand::GetLongDescription() const
-{
-	return "Resets the emulation, by:\n\n"
-	    "  1) setting the current run state to Paused,\n"
-	    "  2) clearing the state of all components\n"
-	    "  3) reloading any binaries loaded on the command"
-	    	" line (on-reset commands)\n";
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_ResetCommand_RunState()
-{
-	refcount_ptr<Command> cmd = new ResetCommand;
-	vector<string> dummyArguments;
-	
-	GXemul gxemul;
-
-	UnitTest::Assert("the default GXemul instance should be Paused",
-	    gxemul.GetRunState() == GXemul::Paused);
-
-	gxemul.SetRunState(GXemul::Running);
-
-	cmd->Execute(gxemul, dummyArguments);
-
-	UnitTest::Assert("runstate should now be Paused",
-	    gxemul.GetRunState() == GXemul::Paused);
-}
-
-UNITTESTS(ResetCommand)
-{
-	UNITTEST(Test_ResetCommand_RunState);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/commands/SaveCommand.cc gxemul-0.7.0+dfsg/src/main/commands/SaveCommand.cc
--- gxemul-0.6.2/src/main/commands/SaveCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/SaveCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,148 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/SaveCommand.h"
-#include "GXemul.h"
-
-#include <fstream>
-
-
-SaveCommand::SaveCommand()
-	: Command("save", "[filename [component-path]]")
-{
-}
-
-
-SaveCommand::~SaveCommand()
-{
-}
-
-
-static void ShowMsg(GXemul& gxemul, const string& msg)
-{
-	gxemul.GetUI()->ShowDebugMessage(msg);
-}
-
-
-bool SaveCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	string filename = gxemul.GetEmulationFilename();
-	string path = "root";
-
-	if (arguments.size() > 2) {
-		ShowMsg(gxemul, "Too many arguments.\n");
-		return false;
-	}
-
-	if (arguments.size() > 0)
-		filename = arguments[0];
-
-	if (filename == "") {
-		ShowMsg(gxemul, "No filename given.\n");
-		return false;
-	}
-
-	if (arguments.size() > 1)
-		path = arguments[1];
-
-	vector<string> matches = gxemul.GetRootComponent()->
-	    FindPathByPartialMatch(path);
-	if (matches.size() == 0) {
-		ShowMsg(gxemul, path+" is not a path to a known component.\n");
-		return false;
-	}
-	if (matches.size() > 1) {
-		ShowMsg(gxemul, path+" matches multiple components:\n");
-		for (size_t i=0; i<matches.size(); i++)
-			ShowMsg(gxemul, "  " + matches[i] + "\n");
-		return false;
-	}
-
-	refcount_ptr<Component> component =
-	    gxemul.GetRootComponent()->LookupPath(matches[0]);
-	if (component.IsNULL()) {
-		ShowMsg(gxemul, "Lookup of " + path + " failed.\n");
-		return false;
-	}
-
-	const string extension = ".gxemul";
-	if (filename.length() < extension.length() || filename.substr(
-	    filename.length() - extension.length()) != extension)
-		ShowMsg(gxemul, "Warning: the name "+filename+" does not have"
-		    " a .gxemul extension. Continuing anyway.\n");
-
-	// Write to the file:
-	{
-		std::fstream outputstream(filename.c_str(),
-		    std::ios::out | std::ios::trunc);
-		if (outputstream.fail()) {
-			ShowMsg(gxemul, "Error: Could not open " + filename +
-			    " for writing.\n");
-			return false;
-		}
-
-		SerializationContext context;
-		component->Serialize(outputstream, context);
-	}
-
-	// Check that the file exists:
-	{
-		std::fstream inputstream(filename.c_str(), std::ios::in);
-		if (inputstream.fail()) {
-			ShowMsg(gxemul, "Error: Could not open " + filename +
-			    " for reading after writing to it; saving "
-			    " the emulation setup failed!\n");
-			return false;
-		}
-	}
-
-	ShowMsg(gxemul, "Emulation setup saved to " + filename + "\n");
-	gxemul.SetEmulationFilename(filename);
-
-	return true;
-}
-
-
-string SaveCommand::GetShortDescription() const
-{
-	return "Saves the emulation to a file.";
-}
-
-
-string SaveCommand::GetLongDescription() const
-{
-	return
-	    "Saves the entire emulation setup, or a part of it, to a file in the filesystem.\n"
-	    "The filename may be omitted, if it is known from an earlier save or load\n"
-	    "command. If the component path is omitted, the entire emulation setup, starting\n"
-	    "from the 'root' component, is saved.\n"
-	    "\n"
-	    "The filename extension should usually be .gxemul.\n"
-	    "\n"
-	    "See also:  load    (to load an emulation setup)\n";
-}
-
diff -Nru gxemul-0.6.2/src/main/commands/StatusCommand.cc gxemul-0.7.0+dfsg/src/main/commands/StatusCommand.cc
--- gxemul-0.6.2/src/main/commands/StatusCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/StatusCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,71 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/StatusCommand.h"
-#include "GXemul.h"
-
-
-StatusCommand::StatusCommand()
-	: Command("status", "")
-{
-}
-
-
-StatusCommand::~StatusCommand()
-{
-}
-
-
-bool StatusCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	stringstream ss;
-	ss <<
-	    "step " << gxemul.GetStep() << ", " <<
-	    gxemul.GetRunStateAsString() << "\n";
-
-	gxemul.GetUI()->ShowDebugMessage(ss.str());
-
-	return true;
-}
-
-
-string StatusCommand::GetShortDescription() const
-{
-	return "Shows the current status (runstate etc).";
-}
-
-
-string StatusCommand::GetLongDescription() const
-{
-	return
-	    "Shows the current status, which includes:\n\n"
-	    "  *  Number of emulated step\n"
-	    "  *  Runstate (Running or Paused)\n"
-	    "\n"
-	    "Typing CTRL-T at the command prompt also executes the 'status' command.\n";
-}
-
diff -Nru gxemul-0.6.2/src/main/commands/StepCommand.cc gxemul-0.7.0+dfsg/src/main/commands/StepCommand.cc
--- gxemul-0.6.2/src/main/commands/StepCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/StepCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,163 +0,0 @@
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/StepCommand.h"
-#include "GXemul.h"
-
-
-StepCommand::StepCommand()
-	: Command("step", "[nsteps]")
-{
-}
-
-
-StepCommand::~StepCommand()
-{
-}
-
-
-bool StepCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	int64_t nsteps = 1;
-
-	if (arguments.size() > 1) {
-		gxemul.GetUI()->ShowDebugMessage("step: Too many arguments.\n");
-		return false;
-	}
-
-	if (arguments.size() > 0) {
-		stringstream ss;
-		ss << arguments[0];
-		ss >> nsteps;
-	}
-
-	if (nsteps < 1) {
-		gxemul.GetUI()->ShowDebugMessage("nr of steps must be at least 1\n");
-		return false;
-	}
-
-	gxemul.SetRunState(GXemul::SingleStepping);
-	gxemul.SetNrOfSingleStepsInARow(nsteps);
-
-	return true;
-}
-
-
-string StepCommand::GetShortDescription() const
-{
-	return "Runs one step of the emulation.";
-}
-
-
-string StepCommand::GetLongDescription() const
-{
-	return "Runs one step (or multiple single-steps) in the emulation.\n"
-	    "\n"
-	    "See also:  continue      (to continue without single-stepping)\n";
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_StepCommand_Affect_RunState()
-{
-	refcount_ptr<Command> cmd = new StepCommand;
-	vector<string> dummyArguments;
-	
-	GXemul gxemul;
-
-	UnitTest::Assert("the default GXemul instance should be Paused",
-	    gxemul.GetRunState() == GXemul::Paused);
-
-	cmd->Execute(gxemul, dummyArguments);
-
-	UnitTest::Assert("runstate should have been changed to SingleStepping",
-	    gxemul.GetRunState() == GXemul::SingleStepping);
-}
-
-static void Test_StepCommand_GoodArgs()
-{
-	refcount_ptr<Command> cmd = new StepCommand;
-	vector<string> arguments;
-	
-	GXemul gxemul;
-	arguments.push_back("42");
-
-	UnitTest::Assert("should have succeeded; good arguments",
-	    cmd->Execute(gxemul, arguments));
-}
-
-static void Test_StepCommand_BadArgs_TooMany()
-{
-	refcount_ptr<Command> cmd = new StepCommand;
-	vector<string> arguments;
-	
-	GXemul gxemul;
-	arguments.push_back("42");
-	arguments.push_back("43");
-
-	UnitTest::Assert("should not have succeeded; noo many args",
-	    !cmd->Execute(gxemul, arguments));
-}
-
-static void Test_StepCommand_BadArgs_Zero()
-{
-	refcount_ptr<Command> cmd = new StepCommand;
-	vector<string> arguments;
-	
-	GXemul gxemul;
-	arguments.push_back("0");
-
-	UnitTest::Assert("should not have succeeded; too few steps",
-	    !cmd->Execute(gxemul, arguments));
-}
-
-static void Test_StepCommand_BadArgs_Negative()
-{
-	refcount_ptr<Command> cmd = new StepCommand;
-	vector<string> arguments;
-	
-	GXemul gxemul;
-	arguments.push_back("-42");
-
-	UnitTest::Assert("should not have succeeded; negative nr of steps",
-	    !cmd->Execute(gxemul, arguments));
-}
-
-UNITTESTS(StepCommand)
-{
-	UNITTEST(Test_StepCommand_Affect_RunState);
-	UNITTEST(Test_StepCommand_GoodArgs);
-	UNITTEST(Test_StepCommand_BadArgs_TooMany);
-	UNITTEST(Test_StepCommand_BadArgs_Zero);
-	UNITTEST(Test_StepCommand_BadArgs_Negative);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/commands/VersionCommand.cc gxemul-0.7.0+dfsg/src/main/commands/VersionCommand.cc
--- gxemul-0.6.2/src/main/commands/VersionCommand.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/commands/VersionCommand.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,81 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "commands/VersionCommand.h"
-#include "GXemul.h"
-
-
-VersionCommand::VersionCommand()
-	: Command("version", "")
-{
-}
-
-
-VersionCommand::~VersionCommand()
-{
-}
-
-
-bool VersionCommand::Execute(GXemul& gxemul, const vector<string>& arguments)
-{
-	gxemul.GetUI()->ShowDebugMessage(gxemul.Version() + "\n");
-	return true;
-}
-
-
-string VersionCommand::GetShortDescription() const
-{
-	return "Prints version information.";
-}
-
-
-string VersionCommand::GetLongDescription() const
-{
-	return "Prints version information.";
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_VersionCommand_DontAcceptArgs()
-{
-	refcount_ptr<Command> cmd = new VersionCommand;
-	vector<string> dummyArguments;
-
-	UnitTest::Assert("version should not take any arguments",
-	    cmd->GetArgumentFormat() == "");
-}
-
-UNITTESTS(VersionCommand)
-{
-	UNITTEST(Test_VersionCommand_DontAcceptArgs);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/Component.cc gxemul-0.7.0+dfsg/src/main/Component.cc
--- gxemul-0.6.2/src/main/Component.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/Component.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1286 +0,0 @@
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Note: See DummyComponent.cc for unit tests of the component framework.
- */
-
-#include "assert.h"
-#include <fstream>
-
-#include "components/RootComponent.h"
-#include "Component.h"
-#include "ComponentFactory.h"
-#include "EscapedString.h"
-#include "GXemul.h"
-#include "StringHelper.h"
-
-
-Component::Component(const string& className, const string& visibleClassName)
-	: m_parentComponent(NULL)
-	, m_className(className)
-	, m_visibleClassName(visibleClassName)
-	, m_step(0)
-{
-	AddVariable("name", &m_name);
-	AddVariable("template", &m_template);
-	AddVariable("step", &m_step);
-}
-
-
-string Component::GetClassName() const
-{
-	return m_className;
-}
-
-
-string Component::GetVisibleClassName() const
-{
-	return m_visibleClassName;
-}
-
-
-string Component::GetAttribute(const string& attributeName)
-{
-	// The Component base class always returns an empty string
-	// for all attribute names. It is up to individual Component
-	// implementations to return overrides.
-
-	return "";
-}
-
-
-refcount_ptr<Component> Component::Clone() const
-{
-	refcount_ptr<Component> clone;
-
-	if (GetClassName() == "root")
-		clone = new RootComponent;
-	else
-		clone = ComponentFactory::CreateComponent(GetClassName());
-
-	if (clone.IsNULL()) {
-		std::cerr << "INTERNAL ERROR in Component::Clone(): "
-		    "could not clone a '" << GetClassName() << "'\n";
-		throw std::exception();
-	}
-
-	// Copy the value of each state variable to the clone:
-	StateVariableMap::const_iterator varIt = m_stateVariables.begin();
-	for ( ; varIt != m_stateVariables.end(); ++varIt) {
-		const string& varName = varIt->first;
-		const StateVariable& variable = varIt->second;
-
-		StateVariableMap::iterator cloneVarIt =
-		    clone->m_stateVariables.find(varName);
-
-		if (cloneVarIt == clone->m_stateVariables.end()) {
-			std::cerr << "INTERNAL ERROR in Component::Clone(): "
-			    "could not copy variable " << varName << "'s "
-			    << " value to the clone: clone is missing"
-			    " this variable?\n";
-			assert(false);
-		} else if (!(cloneVarIt->second).CopyValueFrom(variable)) {
-			std::cerr << "INTERNAL ERROR in Component::Clone(): "
-			    "could not copy variable " << varName << "'s "
-			    << " value to the clone.\n";
-			assert(false);
-		}
-	}
-
-	for (Components::const_iterator it = m_childComponents.begin();
-	    it != m_childComponents.end(); ++it) {
-		refcount_ptr<Component> child = (*it)->Clone();
-		if (child.IsNULL()) {
-			std::cerr << "INTERNAL ERROR in Component::Clone(): "
-			    "could not clone child of class '" <<
-			    (*it)->GetClassName() << "'\n";
-			assert(false);
-		} else {
-			clone->AddChild(child);
-		}
-	}
-
-	return clone;
-}
-
-
-refcount_ptr<Component> Component::LightCloneInternal() const
-{
-	refcount_ptr<Component> clone;
-
-	if (GetClassName() == "root")
-		clone = new RootComponent;
-	else
-		clone = ComponentFactory::CreateComponent(GetClassName());
-
-	if (clone.IsNULL()) {
-		std::cerr << "INTERNAL ERROR in Component::LightCloneInternal(): "
-		    "could not clone a '" << GetClassName() << "'\n";
-		throw std::exception();
-	}
-
-	// Copy the value of each state variable to the clone:
-	StateVariableMap::const_iterator varIt = m_stateVariables.begin();
-	for ( ; varIt != m_stateVariables.end(); ++varIt) {
-		const string& varName = varIt->first;
-		const StateVariable& variable = varIt->second;
-
-		StateVariableMap::iterator cloneVarIt =
-		    clone->m_stateVariables.find(varName);
-
-		if (cloneVarIt == clone->m_stateVariables.end()) {
-			std::cerr << "INTERNAL ERROR in Component::LightCloneInternal(): "
-			    "could not copy variable " << varName << "'s "
-			    << " value to the clone: clone is missing"
-			    " this variable?\n";
-			throw std::exception();
-		}
-
-		// Skip custom variables:
-		if (variable.GetType() == StateVariable::Custom)
-			continue;
-
-		if (!(cloneVarIt->second).CopyValueFrom(variable)) {
-			std::cerr << "INTERNAL ERROR in Component::LightCloneInternal(): "
-			    "could not copy variable " << varName << "'s "
-			    << " value to the clone.\n";
-			throw std::exception();
-		}
-	}
-
-	for (Components::const_iterator it = m_childComponents.begin();
-	    it != m_childComponents.end(); ++it) {
-		refcount_ptr<Component> child = (*it)->LightCloneInternal();
-		if (child.IsNULL()) {
-			std::cerr << "INTERNAL ERROR in Component::LightCloneInternal(): "
-			    "could not clone child of class '" <<
-			    (*it)->GetClassName() << "'\n";
-			throw std::exception();
-		} else {
-			clone->AddChild(child);
-		}
-	}
-
-	return clone;
-}
-
-
-const refcount_ptr<Component> Component::LightClone() const
-{
-	return LightCloneInternal();
-}
-
-
-void Component::DetectChanges(const refcount_ptr<Component>& oldClone,
-	ostream& changeMessages) const
-{
-	// Recursively look for changes in state. Compare the
-	// oldClone component with this component first.
-
-	if (oldClone->GetClassName() != GetClassName()) {
-		changeMessages << oldClone->GenerateShortestPossiblePath() <<
-		    " changed class from " << oldClone->GetClassName() <<
-		    " to " << GetClassName() << "?\n";
-		return;
-	}
-
-	// Compare all state variables:
-	StateVariableMap::const_iterator varIt = m_stateVariables.begin();
-	for ( ; varIt != m_stateVariables.end(); ++varIt) {
-		const string& varName = varIt->first;
-
-		// Don't output "step" changes, because they happen all
-		// the time for all executable components.
-		if (varName == "step")
-			continue;
-
-		const StateVariable& variable = varIt->second;
-		const StateVariable* oldVariable = oldClone->GetVariable(varName);
-
-		// NOTE: Custom types have a nonsense tostring, which
-		// usually just says "(custom)" or something, so they
-		// are quickly compared.
-
-		// TODO: In the future, maybe RAM components and such (i.e.
-		// custom data types) can be lazily reference counted or
-		// similar, to detect changes in RAM as well.
-
-		string var = variable.ToString();
-		string varOld = oldVariable->ToString();
-
-		if (var != varOld)
-			changeMessages << "=> " << GenerateShortestPossiblePath() << "."
-			    << varName << ": " << varOld << " -> " << var << "\n";
-	}
-
-	// Compare all children.
-	const Components& oldChildren = oldClone->GetChildren();
-	for (size_t i = 0; i < m_childComponents.size(); ++ i) {
-		string myName = m_childComponents[i]->GetVariable("name")->ToString();
-
-		// Find the corresponding child component in the oldClone:
-		size_t j;
-		bool found = false;
-		for (j=0; j<oldChildren.size(); ++j)
-			if (oldChildren[j]->GetVariable("name")->ToString() == myName) {
-				m_childComponents[i]->DetectChanges(oldChildren[j], changeMessages);
-				found = true;
-				break;
-			}
-
-		if (!found)
-			changeMessages << m_childComponents[i]->
-			    GenerateShortestPossiblePath() << " (appeared)\n";
-	}
-
-	// ... and see if any disappeared (i.e. were in the old clone,
-	// but not in the current tree):
-	for (size_t j=0; j<oldChildren.size(); ++j) {
-		string oldName = oldChildren[j]->GetVariable("name")->ToString();
-
-		bool found = false;
-		for (size_t k=0; k<m_childComponents.size(); ++k) {
-			string newName = m_childComponents[k]->GetVariable("name")->ToString();
-			if (newName == oldName) {
-				found = true;
-				break;
-			}
-		}
-
-		if (!found)
-			changeMessages << oldChildren[j]->
-			    GenerateShortestPossiblePath() << " (disappeared)\n";
-	}
-}
-
-
-void Component::Reset()
-{
-	ResetState();
-
-	// Recurse:
-	for (size_t i = 0; i < m_childComponents.size(); ++ i)
-		m_childComponents[i]->Reset();
-}
-
-
-void Component::ResetState()
-{
-	// Base implementation.
-	m_step = 0;
-}
-
-
-bool Component::PreRunCheck(GXemul* gxemul)
-{
-	bool everythingOk = PreRunCheckForComponent(gxemul);
-
-	// Recurse:
-	for (size_t i = 0; i < m_childComponents.size(); ++ i)
-		everythingOk &= m_childComponents[i]->PreRunCheck(gxemul);
-
-	return everythingOk;
-}
-
-
-bool Component::PreRunCheckForComponent(GXemul* gxemul)
-{
-	// Base implementation: Do nothing. Everything is Ok.
-	return true;
-}
-
-
-void Component::FlushCachedState()
-{
-	FlushCachedStateForComponent();
-
-	// Recurse:
-	for (size_t i = 0; i < m_childComponents.size(); ++ i)
-		m_childComponents[i]->FlushCachedState();
-}
-
-
-void Component::FlushCachedStateForComponent()
-{
-	// Base implementation: Do nothing.
-}
-
-
-int Component::Execute(GXemul* gxemul, int nrOfCycles)
-{
-	// Base implementation: Do nothing, but pretend we executed
-	// the instructions. Actual components that inherit from this
-	// class should of course _do_ something here.
-
-	return nrOfCycles;
-}
-
-
-double Component::GetCurrentFrequency() const
-{
-	// The base component does not run at any frequency. Only components
-	// that actually run something "per cycle" should return values
-	// greater than 0.0.
-
-	return 0.0;
-}
-
-
-RootComponent* Component::AsRootComponent()
-{
-	// Default implementation (the base Component class) is not a RootComponent.
-	return NULL;
-}
-
-
-CPUComponent* Component::AsCPUComponent()
-{
-	// Default implementation (the base Component class) is not a CPU.
-	return NULL;
-}
-
-
-AddressDataBus* Component::AsAddressDataBus()
-{
-	// Default implementation (the base Component class) is not an
-	// address data bus.
-	return NULL;
-}
-
-
-void Component::SetParent(Component* parentComponent)
-{
-	m_parentComponent = parentComponent;
-}
-
-
-Component* Component::GetParent()
-{
-	return m_parentComponent;
-}
-
-
-const Component* Component::GetParent() const
-{
-	return m_parentComponent;
-}
-
-
-void Component::GetMethodNames(vector<string>& names) const
-{
-	// The default component has no implemented methods.
-}
-
-
-bool Component::MethodMayBeReexecutedWithoutArgs(const string& methodName) const
-{
-	// By default, methods are _not_ re-executable without args.
-	return false;
-}
-
-
-void Component::ExecuteMethod(GXemul* gxemul,
-	const string& methodName,
-	const vector<string>& arguments)
-{
-	std::cerr << "Internal error: someone tried to execute "
-	    "method '" << methodName << "' on the Component base"
-	    " class. Perhaps you are missing an override?\n";
-	throw std::exception();
-}
-
-
-string Component::GenerateDetails() const
-{
-	stringstream ss;
-
-	// If this component has a "model", then show that.
-	const StateVariable* model = GetVariable("model");
-	if (model != NULL && !model->ToString().empty()) {
-		if (!ss.str().empty())
-			ss << ", ";
-		ss << model->ToString();
-	}
-
-	// If this component has a frequency (i.e. it is runnable), then
-	// show the frequency:
-	double freq = GetCurrentFrequency();
-	if (freq != 0.0) {
-		if (!ss.str().empty())
-			ss << ", ";
-
-		if (freq >= 1e9)
-			ss << freq/1e9 << " GHz";
-		else if (freq >= 1e6)
-			ss << freq/1e6 << " MHz";
-		else if (freq >= 1e3)
-			ss << freq/1e3 << " kHz";
-		else
-			ss << freq << " Hz";
-	}
-
-	const StateVariable* paused = GetVariable("paused");
-	// TODO: ToBool :)
-	if (paused != NULL && paused->ToInteger() > 0) {
-		if (!ss.str().empty())
-			ss << ", ";
-
-		ss << "paused";
-	}
-
-	return ss.str();
-}
-
-
-string Component::GenerateTreeDump(const string& branchTemplate,
-	bool htmlLinksForClassNames, string prefixForComponentUrls) const
-{
-	// This generates an ASCII string which looks like:
-	//
-	//	root
-	//	|-- child1
-	//	|   |-- child1's child1
-	//	|   \-- child1's child2
-	//	\-- child2
-	//	    \-- child2's child
-
-	string branch;
-	for (size_t pos=0; pos<branchTemplate.length(); pos++) {
-		stringchar ch = branchTemplate[pos];
-		if (ch == '\\') {
-			if (pos < branchTemplate.length() - 4)
-				branch += ' ';
-			else
-				branch += ch;
-		} else {
-			if (pos == branchTemplate.length() - 3 ||
-			    pos == branchTemplate.length() - 2)
-				ch = '-';
-			branch += ch;
-		}
-	}
-
-	// Fallback to showing the component's class name in parentheses...
-	const string className = GetClassName();
-	string name = "(unnamed " + className + ")";
-
-	// ... but prefer the state variable "name" if it is non-empty:
-	const StateVariable* value = GetVariable("name");
-	if (!value->ToString().empty())
-		name = value->ToString();
-
-	string str = branch;
-
-	if (htmlLinksForClassNames) {
-		// See if this class name has its own HTML page.
-		std::ifstream documentationComponentFile((
-		    "doc/components/component_"
-		    + className + ".html").c_str());
-
-		if (documentationComponentFile.is_open())
-			str += "<a href=\"" + prefixForComponentUrls +
-			    "components/component_" +
-			    className + ".html\">" + name + "</a>";
-		else
-			str += name;
-	} else {
-		str += name;
-	}
-
-	// If this component was created by a template, then show the template
-	// type in [ ].
-	const StateVariable* templateName;
-	if ((templateName = GetVariable("template")) != NULL &&
-	    !templateName->ToString().empty())
-	{
-		string tName = templateName->ToString();
-
-		str += "  [";
-
-		if (htmlLinksForClassNames) {
-			// See if this class/template name has its own HTML page.
-			// (Usually machines. TODO: also other components.)
-			std::ifstream documentationMachineFile((
-			    "doc/machines/machine_"
-			    + tName + ".html").c_str());
-
-			if (documentationMachineFile.is_open())
-				str += "<a href=\"" + prefixForComponentUrls +
-				    "machines/machine_" +
-				    tName + ".html\">" + tName + "</a>";
-			else
-				str += tName;
-		} else {
-			str += tName;
-		}
-
-		str += "]";
-	}
-
-	// Get any additional details (CPU model, memory mapped address, etc.):
-	string details = GenerateDetails();
-	if (!details.empty())
-		str += "  (" + details + ")";
-
-	// Show the branch of the tree...
-	string result = "  " + str + "\n";
-
-	// ... and recurse to show children, if there are any:
-	const Components& children = GetChildren();
-	for (size_t i=0, n=children.size(); i<n; ++i) {
-		string subBranch = branchTemplate;
-		if (i == n-1)
-			subBranch += "\\   ";
-		else
-			subBranch += "|   ";
-
-		result += children[i]->GenerateTreeDump(subBranch,
-		    htmlLinksForClassNames, prefixForComponentUrls);
-	}
-
-	return result;
-}
-
-
-GXemul* Component::GetRunningGXemulInstance()
-{
-	Component* root = this;
-	while (root->GetParent() != NULL)
-		root = root->GetParent();
-
-	RootComponent* rootComponent = root->AsRootComponent();
-	if (rootComponent == NULL)
-		return NULL;
-
-	return rootComponent->GetOwner();
-}
-
-
-UI* Component::GetUI()
-{
-	GXemul* gxemul = GetRunningGXemulInstance();
-	if (gxemul == NULL)
-		return NULL;
-
-	// TODO: Return NULL if the UI has debug messages turned off.
-
-	return gxemul->GetUI();
-}
-
-
-void Component::AddChild(refcount_ptr<Component> childComponent,
-	size_t insertPosition)
-{
-	if (insertPosition == (size_t) -1) {
-		insertPosition = m_childComponents.size();
-		m_childComponents.push_back(childComponent);
-	} else {
-		m_childComponents.insert(
-		    m_childComponents.begin() + insertPosition,
-		    childComponent);
-	}
-
-	// A component cannot have two parents.	
-	assert(childComponent->GetParent() == NULL);
-
-	childComponent->SetParent(this);
-
-	// Make sure that the child's "name" state variable is unique among
-	// all children of this component. (Yes, this is O(n^2) and it may
-	// need to be rewritten to cope with _lots_ of components.)
-	size_t postfix = 0;
-	bool collision = false;
-	do {
-		const StateVariable* name =
-		    childComponent->GetVariable("name");
-		if (name->ToString().empty() || collision) {
-			// Set the default name:
-			//	visibleclassname + postfix number
-			stringstream ss;
-			ss << childComponent->GetVisibleClassName() << postfix;
-			EscapedString escaped(ss.str());
-			childComponent->SetVariableValue("name",
-			    escaped.Generate());
-
-			name = childComponent->GetVariable("name");
-		}
-
-		collision = false;
-		for (size_t i=0; i<m_childComponents.size(); ++i) {
-			if (i == insertPosition)
-				continue;
-
-			// Collision?
-			const StateVariable* otherName =
-			    m_childComponents[i]->GetVariable("name");
-			if (otherName != NULL) {
-				if (name->ToString() == otherName->ToString()) {
-					collision = true;
-					++ postfix;
-					break;
-				}
-			} else {
-				// Hm. All components should have a "name".
-				assert(false);
-			}
-		}
-	} while (collision);
-}
-
-
-size_t Component::RemoveChild(Component* childToRemove)
-{
-	size_t index = 0;
-	for (Components::iterator it = m_childComponents.begin();
-	     it != m_childComponents.end(); ++it, ++index) {
-		if (childToRemove == (*it)) {
-			childToRemove->SetParent(NULL);
-			m_childComponents.erase(it);
-			return index;
-		}
-	}
-	
-	// Child not found? Should not happen.
-	assert(false);
-
-	return (size_t) -1;
-}
-
-
-Components& Component::GetChildren()
-{
-	return m_childComponents;
-}
-
-
-const Components& Component::GetChildren() const
-{
-	return m_childComponents;
-}
-
-
-string Component::GeneratePath() const
-{
-	string path = GetVariable("name")->ToString();
-	if (path.empty())
-		path = "(" + GetClassName() + ")";
-
-	if (m_parentComponent != NULL)
-		path = m_parentComponent->GeneratePath() + "." + path;
-
-	return path;
-}
-
-
-static vector<string> SplitPathStringIntoVector(const string &path)
-{
-	// Split the path into a vector. This is slow and hackish, but works.
-	vector<string> pathStrings;
-	string word;
-
-	for (size_t i=0, n=path.length(); i<n; i++) {
-		stringchar ch = path[i];
-		if (ch == '.') {
-			pathStrings.push_back(word);
-			word = "";
-		} else {
-			word += ch;
-		}
-	}
-
-	pathStrings.push_back(word);
-
-	return pathStrings;
-}
-
-
-string Component::GenerateShortestPossiblePath() const
-{
-	string myPath = GeneratePath();
-	vector<string> allComponentPaths;
-
-	const Component* root = this;
-	while (root->GetParent() != NULL)
-		root = root->GetParent();
-
-	root->AddAllComponentPaths(allComponentPaths);
-
-	// Include as few as possible sub-parts of myPath (starting from the
-	// end), to uniqely identify the component.
-	vector<string> myPathParts = SplitPathStringIntoVector(myPath);
-
-	for (size_t n=1; n<=myPathParts.size(); ++n) {
-		string attempt = "";
-		for (size_t i=myPathParts.size()-n; i<myPathParts.size(); i++) {
-			if (attempt.length() > 0)
-				attempt += ".";
-			attempt += myPathParts[i];
-		}
-
-		// std::cerr << "attempt = " << attempt << "\n";
-		// attempt = ram0
-		// attempt = mainbus0.ram0
-		// attempt = machine0.mainbus0.ram0
-		// etc.
-
-		// See if this substring is unique in allComponentPaths.
-		int nHits = 0;
-		string dotAttempt = "." + attempt;
-		size_t dotAttemptLength = dotAttempt.length();
-		for (size_t j=0; j<allComponentPaths.size(); ++j) {
-			const string& s = allComponentPaths[j];
-			if (s.length() < attempt.length())
-				continue;
-				
-			if (s == attempt)
-				nHits ++;
-			else if (s.length() > dotAttemptLength &&
-			    s.substr(s.length() - dotAttemptLength, dotAttemptLength) == dotAttempt)
-				nHits ++;
-		}
-
-		// Unique? Then we found a good short path.
-		if (nHits == 1)
-			return attempt;
-			
-		// Otherwise continue.
-	}
-
-	// Worst case: return full path.
-	return myPath;
-}
-
-
-const refcount_ptr<Component> Component::LookupPath(string path) const
-{
-	// Trim whitespace
-	while (path.length() > 0 && path[path.length() - 1] == ' ')
-		path = path.substr(0, path.length() - 1);
-
-	refcount_ptr<Component> component = LookupPath(SplitPathStringIntoVector(path), 0);
-	
-	if (component.IsNULL()) {
-		// Maybe it was a path starting from somewhere other than the
-		// root. That is, if we find "." + path in the list of all
-		// components' full names exactly 1 time, then we return that.
-		vector<string> allComponentPaths;
-		AddAllComponentPaths(allComponentPaths);
-
-		const Component* root = this;
-		while (root->GetParent() != NULL)
-			root = root->GetParent();
-
-		int nMatches = 0;
-		string strToFind = "." + path;
-		for (size_t i=0, n=allComponentPaths.size(); i<n; i++) {
-			if (allComponentPaths[i].length() > strToFind.length()) {
-				string subs = allComponentPaths[i].substr(
-				    allComponentPaths[i].length() - strToFind.length());
-				if (strToFind == subs) {
-					nMatches ++;
-					component = root->LookupPath(allComponentPaths[i]);
-				}
-			}
-		}
-
-		if (nMatches != 1)
-			return NULL;
-	}
-	
-	return component;
-}
-
-
-const refcount_ptr<Component> Component::LookupPath(const vector<string>& path,
-	size_t index) const
-{
-	refcount_ptr<Component> component;
-
-	if (index > path.size()) {
-		// Huh? Lookup of empty path? Should not usually happen.
-		assert(false);
-		return component;
-	}
-
-	StateVariableMap::const_iterator it = m_stateVariables.find("name");
-	if (it == m_stateVariables.end()) {
-		// Failure (return NULL) if we don't have a name.
-		return component;
-	}
-
-	string nameOfThisComponent = (it->second).ToString();
-	bool match = (path[index] == nameOfThisComponent);
-
-	// No match? Or was it the last part of the path? Then return.
-	if (!match || index == path.size() - 1) {
-		// (Successfully, if there was a match.)
-		if (match)
-			return const_cast<Component*>(this);
-		return component;
-	}
-
-	// If there are still parts left to check, look among all the children:
-	const string& pathPartToLookup = path[index+1];
-	for (size_t i=0, n=m_childComponents.size(); i<n; i++) {
-		const StateVariable* childName =
-		    m_childComponents[i]->GetVariable("name");
-		if (childName != NULL) {
-			if (childName->ToString() == pathPartToLookup) {
-				component = m_childComponents[i]->
-				    LookupPath(path, index+1);
-				break;
-			}
-		}
-	}
-
-	return component;
-}
-
-
-void Component::AddAllComponentPaths(vector<string>& allComponentPaths) const
-{
-	// Add the component itself first:
-	allComponentPaths.push_back(GeneratePath());
-
-	// Then all children:
-	for (size_t i=0, n=m_childComponents.size(); i<n; i++)
-		m_childComponents[i]->AddAllComponentPaths(allComponentPaths);
-}
-
-
-static bool PartialMatch(const string& partialPath, const string& path)
-{
-	if (partialPath.empty())
-		return true;
-
-	const size_t partialPathLength = partialPath.length();
-	const size_t pathLength = path.length();
-	size_t pathPos = 0;
-
-	do {
-		// Partial path too long? Then abort immediately.
-		if (partialPathLength + pathPos > pathLength)
-			break;
-
-		// A substring match? Then we might have found it.
-		if (path.substr(pathPos, partialPathLength) == partialPath) {
-			// If the path has no tail (".subcomponent"), then
-			// we found it:
-			if (path.find('.', pathPos + partialPathLength) ==
-			    string::npos)
-				return true;
-		}
-
-		// Find next place in path to test:
-		do {
-			pathPos ++;
-		} while (pathPos < pathLength && path[pathPos] != '.');
-
-		if (pathPos < pathLength)
-			pathPos ++;
-
-	} while (pathPos < pathLength);
-
-	return false;
-}
-
-
-vector<string> Component::FindPathByPartialMatch(
-	const string& partialPath, bool shortestPossible) const
-{
-	vector<string> allComponentPaths;
-	vector<string> matches;
-
-	AddAllComponentPaths(allComponentPaths);
-
-	for (size_t i=0, n=allComponentPaths.size(); i<n; i++)
-		if (PartialMatch(partialPath, allComponentPaths[i])) {
-			string match = allComponentPaths[i];
-
-			if (shortestPossible) {
-				const Component* root = this;
-				while (root->GetParent() != NULL)
-					root = root->GetParent();
-
-				refcount_ptr<Component> component =
-				    root->LookupPath(match);
-				match = component->GenerateShortestPossiblePath();
-			}
-
-			matches.push_back(match);
-		}
-
-	return matches;
-}
-
-
-void Component::GetVariableNames(vector<string>& names) const
-{
-	for (StateVariableMap::const_iterator it = m_stateVariables.begin();
-	    it != m_stateVariables.end(); ++it)
-		names.push_back(it->first);
-}
-
-
-StateVariable* Component::GetVariable(const string& name)
-{
-	StateVariableMap::iterator it = m_stateVariables.find(name);
-	if (it == m_stateVariables.end())
-		return NULL;
-	else
-		return &(it->second);
-}
-
-
-const StateVariable* Component::GetVariable(const string& name) const
-{
-	StateVariableMap::const_iterator it = m_stateVariables.find(name);
-	if (it == m_stateVariables.end())
-		return NULL;
-	else
-		return &(it->second);
-}
-
-
-bool Component::CheckVariableWrite(StateVariable& var, const string& oldValue)
-{
-	GXemul* gxemul = GetRunningGXemulInstance();
-	UI* ui = GetUI();
-
-	if (gxemul != NULL) {
-		const string& name = var.GetName();
-
-		if (name == "step") {
-			// If we are the root component, then writing to step
-			// has special meaning:
-			if (GetParent() == NULL) {
-				bool error = false;
-				int64_t oldStep = StringHelper::ParseNumber(oldValue.c_str(), error);
-				int64_t newStep = var.ToInteger();
-
-				// 0. Value is the same as before. Simply return.
-				if (newStep == oldStep)
-					return true;
-
-				// 1. The new value is too low (less than 0).
-				if (newStep < 0) {
-					if (ui != NULL)
-						ui->ShowDebugMessage("root.step can"
-						    " not be set to lower than zero.\n");
-					return false;
-				}
-
-				// 2. The value is lower; run backwards if possible.
-				if (newStep < oldStep) {
-					if (!gxemul->GetSnapshottingEnabled()) {
-						if (ui != NULL)
-							ui->ShowDebugMessage("root.step can"
-							    " not be decreased; snapshotting"
-							    " was not enabled prior to\nstarting"
-							    " the emulation. (-B command line"
-							    " option.)\n");
-						return false;
-					}
-
-					return gxemul->ModifyStep(oldStep, newStep);
-				}
-
-				// 3. The value is higher; run forwards.
-				return gxemul->ModifyStep(oldStep, newStep);
-			} else {
-				// We are not the root component. Direct (interactive)
-				// writes to the step variable is not allowed.
-				if (ui != NULL)
-					ui->ShowDebugMessage("The step variable of "
-					    "this component cannot be set manually.\n");
-			}
-
-			return false;
-		}
-	}
-
-	return true;
-}
-
-
-bool Component::SetVariableValue(const string& name, const string& expression)
-{
-	UI* ui = GetUI();
-
-	StateVariableMap::iterator it = m_stateVariables.find(name);
-	if (it == m_stateVariables.end()) {
-		if (ui != NULL)
-			ui->ShowDebugMessage((string) name + ": no such variable\n");
-		return false;
-	}
-
-	StateVariable& var = it->second;
-	
-	stringstream oldValue;
-	var.SerializeValue(oldValue);
-
-	bool success = var.SetValue(expression);
-	if (!success) {
-		if (ui != NULL)
-			ui->ShowDebugMessage((string) name + ": expression could"
-			    " not be assigned; type mismatch?\n");
-		return false;
-	}
-
-	stringstream newValue;
-	var.SerializeValue(newValue);
-
-	if (oldValue.str() != newValue.str()) {
-		success = CheckVariableWrite(var, oldValue.str());
-		if (!success) {
-			// Revert to the previous:
-			var.SetValue(oldValue.str());
-			return false;
-		}
-	}
-
-	return true;
-}
-
-
-void Component::Serialize(ostream& ss, SerializationContext& context) const
-{
-	SerializationContext subContext = context.Indented();
-	string tabs = context.Tabs();
-
-	ss << tabs << "component " << m_className << "\n" << tabs << "{\n";
-	    
-	for (StateVariableMap::const_iterator it = m_stateVariables.begin();
-	    it != m_stateVariables.end(); ++it)
-		(it->second).Serialize(ss, subContext);
-
-	for (size_t i = 0, n = m_childComponents.size(); i < n; ++ i)
-		m_childComponents[i]->Serialize(ss, subContext);
-
-	ss << tabs << "}\n";
-}
-
-
-static bool GetNextToken(const string& str, size_t& pos, string& token)
-{
-	token = "";
-
-	size_t len = str.length();
-	
-	// Skip initial whitespace:
-	while (pos < len &&
-	    (str[pos] == ' '  || str[pos] == '\t' ||
-	     str[pos] == '\r' || str[pos] == '\n'))
-		++ pos;
-
-	if (pos >= len)
-		return false;
-
-	// Get the token, until end-of-string or until whitespace is found:
-	bool quoted = false;
-	do {
-		char ch = str[pos];
-
-		if (!quoted) {
-			if (ch == '"')
-				quoted = true;
-			if (ch == ' '  || ch == '\t' ||
-			    ch == '\r' || ch == '\n')
-				break;
-			token += ch;
-		} else {
-			if (ch == '"')
-				quoted = false;
-			token += ch;
-			if (ch == '\\' && pos < len-1)
-				token += str[++pos];
-		}
-
-		++ pos;
-	} while (pos < len);
-
-	return true;
-}
-
-
-refcount_ptr<Component> Component::Deserialize(ostream& messages, const string& str, size_t& pos)
-{
-	refcount_ptr<Component> deserializedTree = NULL;
-	string token;
-
-	if (!GetNextToken(str, pos, token) || token != "component") {
-		messages << "Expecting \"component\".\n";
-		return deserializedTree;
-	}
-
-	string className;
-	if (!GetNextToken(str, pos, className)) {
-		messages << "Expecting a class name.\n";
-		return deserializedTree;
-	}
-
-	if (!GetNextToken(str, pos, token) || token != "{") {
-		messages << "Expecting {.\n";
-		return deserializedTree;
-	}
-
-	// root is a special case (cannot be created by the factory). All other
-	// class types should be possible to create using the factory.
-	if (className == "root") {
-		deserializedTree = new RootComponent;
-	} else {
-		deserializedTree = ComponentFactory::CreateComponent(className);
-		if (deserializedTree.IsNULL()) {
-			messages << "Could not create a '" << className << "' component.\n";
-			return deserializedTree;
-		}
-	}
-
-	while (pos < str.length()) {
-		size_t savedPos = pos;
-
-		// Either 1)   }     (end of current component)
-		// or     2)   component name { ...
-		// or     3)   variableType name "value"
-
-		if (!GetNextToken(str, pos, token)) {
-			// Failure.
-			messages << "Failure. (0)\n";
-			deserializedTree = NULL;
-			break;
-		}
-
-		// Case 1:
-		if (token == "}")
-			break;
-
-		string name;
-		if (!GetNextToken(str, pos, name)) {
-			// Failure.
-			messages << "Failure. (1)\n";
-			deserializedTree = NULL;
-			break;
-		}
-
-		if (token == "component") {
-			// Case 2:
-			refcount_ptr<Component> child =
-			    Component::Deserialize(messages, str, savedPos);
-			if (child.IsNULL()) {
-				// Failure.
-				messages << "Failure. (2)\n";
-				deserializedTree = NULL;
-				break;
-			}
-			
-			deserializedTree->AddChild(child);
-			pos = savedPos;
-		} else {
-			// Case 3:
-			string varType = token;
-			string varValue;
-			if (!GetNextToken(str, pos, varValue)) {
-				// Failure.
-				messages << "Failure. (3)\n";
-				deserializedTree = NULL;
-				break;
-			}
-
-			if (!deserializedTree->SetVariableValue(name,
-			    varValue)) {
-				messages << "Warning: variable '" << name <<
-				    "' for component class " << className <<
-				    " could not be deserialized; skipping.\n";
-			}
-		}
-	}
-
-	return deserializedTree;
-}
-
-
-bool Component::CheckConsistency() const
-{
-	// Serialize
-	SerializationContext context;
-	stringstream ss;
-	Serialize(ss, context);
-
-	string result = ss.str();
-
-	Checksum checksumOriginal;
-	AddChecksum(checksumOriginal);
-
-	// Deserialize
-	size_t pos = 0;
-	stringstream messages;
-	refcount_ptr<Component> tmpDeserializedTree = Deserialize(messages, result, pos);
-	if (tmpDeserializedTree.IsNULL())
-		return false;
-
-	Checksum checksumDeserialized;
-	tmpDeserializedTree->AddChecksum(checksumDeserialized);
-
-	// ... and compare the checksums:
-	return checksumOriginal == checksumDeserialized;
-}
-
-
-void Component::AddChecksum(Checksum& checksum) const
-{
-	// Some random stuff is added between normal fields to the checksum.
-	// This is to make it harder to get the same checksum for two different
-	// objects, that just have some fields swapped, or such. (Yes, I know,
-	// that is not a very scientific explanation :) but it will have to do.)
-
-	checksum.Add(((uint64_t) 0x12491725 << 32) | 0xabcef011);
-	checksum.Add(m_className);
-	
-	SerializationContext dummyContext;
-
-	// Add all state variables.
-	for (StateVariableMap::const_iterator it = m_stateVariables.begin();
-	    it != m_stateVariables.end();
-	    ++ it) {
-		checksum.Add(((uint64_t) 0x019fb879 << 32) | 0x25addae1);
-
-		stringstream ss;
-		(it->second).Serialize(ss, dummyContext);
-		checksum.Add(ss.str());
-	}
-	
-	// Add all child components.
-	for (size_t i = 0; i < m_childComponents.size(); ++ i) {
-		checksum.Add((((uint64_t) 0xf98a7c7c << 32) | 0x109f0000)
-		    + i * 0x98127417);
-		m_childComponents[i]->AddChecksum(checksum);
-	}
-
-	checksum.Add(((uint64_t) 0x90a10224 << 32) | 0x97defa7a);
-}
-
-
diff -Nru gxemul-0.6.2/src/main/ComponentFactory.cc gxemul-0.7.0+dfsg/src/main/ComponentFactory.cc
--- gxemul-0.6.2/src/main/ComponentFactory.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/ComponentFactory.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,302 +0,0 @@
-/*
- *  Copyright (C) 2008-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <string.h>
-
-#include "ComponentFactory.h"
-#include "GXemul.h"
-#include "StringHelper.h"
-
-
-struct ComponentListEntry {
-	const char* componentName;
-	refcount_ptr<Component> (*Create)(const ComponentCreateArgs& args);
-	string (*GetAttribute)(const string& attributeName);
-};
-
-// Static list of components:
-// (Note: components*.h is autogenerated by the configure script.)
-#include "../../components_h.h"
-static struct ComponentListEntry componentList[] = {
-#include "../../components.h"
-	{ NULL, NULL, NULL }
-};
-
-// List of components that are added dynamically at runtime:
-static vector<ComponentListEntry>* componentListRunTime = NULL;
-
-
-bool ComponentFactory::RegisterComponentClass(const char* name,
-	refcount_ptr<Component> (*createFunc)(const ComponentCreateArgs& args),
-	string (*getAttributeFunc)(const string& attributeName))
-{
-	// Attempt to create a component using this name first.
-	// Don't add the new component class if the name is already in use.
-	refcount_ptr<Component> component = CreateComponent(name);
-	if (!component.IsNULL()) {
-		assert(false);
-		return false;
-	}
-
-	if (componentListRunTime == NULL)
-		componentListRunTime = new vector<ComponentListEntry>();
-
-	ComponentListEntry cle;
-	cle.componentName = name;
-	cle.Create = createFunc;
-	cle.GetAttribute = getAttributeFunc;
-
-	componentListRunTime->push_back(cle);
-
-	return true;
-}
-
-
-void ComponentFactory::UnregisterAllComponentClasses()
-{
-	delete componentListRunTime;
-	componentListRunTime = NULL;
-}
-
-
-refcount_ptr<Component> ComponentFactory::CreateComponent(
-	const string& componentNameAndOptionalArgs, GXemul* gxemul)
-{
-	ComponentCreateArgs args;
-	args.gxemul = gxemul;
-
-	string componentName = componentNameAndOptionalArgs;
-	size_t p = componentName.find('(');
-	if (p != string::npos && p > 0) {
-		componentName = componentName.substr(0, p);
-
-		string argstring = componentNameAndOptionalArgs.substr(p+1);
-
-		// Arguments don't end with a )? Then something's wrong.
-		if (argstring[argstring.length()-1] != ')') {
-			if (gxemul != NULL)
-				gxemul->GetUI()->ShowDebugMessage("Unmatched parenthesis?\n");
-
-			return NULL;
-		}
-
-		argstring = argstring.substr(0, argstring.length()-1);
-		
-		// argstring is now e.g. "cpu=R4400,ncpus=4"
-
-		// Split into assignments:
-		vector<string> assignments = StringHelper::SplitStringIntoVector(argstring, ',');
-
-		// Split each assignment into key and value:
-		for (size_t i=0; i<assignments.size(); ++i) {
-			vector<string> keyAndValue = StringHelper::SplitStringIntoVector(assignments[i], '=');
-			if (keyAndValue.size() != 2) {
-				if (gxemul != NULL)
-					gxemul->GetUI()->ShowDebugMessage("Not a key=value pair: " + assignments[i]);
-
-				return NULL;
-			}
-
-			args.componentCreationSettings[keyAndValue[0]] = keyAndValue[1];
-		}
-	}
-
-	// Find the className in the list of available components, and
-	// call the corresponding create function, if found:
-	size_t i = 0;
-	while (componentList[i].componentName != NULL) {
-		if (componentName == componentList[i].componentName)
-			return componentList[i].Create(args);
-
-		++ i;
-	}
-
-	for (i=0; componentListRunTime != NULL && i<componentListRunTime->size(); ++i) {
-		if (componentName == (*componentListRunTime)[i].componentName)
-			return (*componentListRunTime)[i].Create(args);
-	}
-
-	if (gxemul != NULL)
-		gxemul->GetUI()->ShowDebugMessage("Unknown component: " + componentNameAndOptionalArgs + "\n");
-
-	return NULL;
-}
-
-
-bool ComponentFactory::GetCreationArgOverrides(ComponentCreationSettings& settings, const ComponentCreateArgs& createArgs)
-{
-	// A copy of the default args (for helpful debug output):
-	ComponentCreationSettings defaultSettings = settings;
-
-	// Merge in the overrides:
-	for (ComponentCreationSettings::const_iterator it = createArgs.componentCreationSettings.begin();
-	    it != createArgs.componentCreationSettings.end(); ++it) {
-		const string& key = it->first;
-		const string& value = it->second;
-		
-		if (settings.find(key) == settings.end()) {
-			if (createArgs.gxemul != NULL) {
-				stringstream ss;
-				ss << "Unknown setting '" << key << "'. "
-				    "Available settings (with default values) are:\n";
-				for (ComponentCreationSettings::const_iterator it2 = defaultSettings.begin();
-				    it2 != defaultSettings.end(); ++it2)
-					ss << "  " << it2->first << " = " << it2->second << "\n";
-
-				createArgs.gxemul->GetUI()->ShowDebugMessage(ss.str());
-			}
-
-			return false;
-		}
-
-		settings[key] = value;
-	}
-	
-	return true;
-}
-
-
-string ComponentFactory::GetAttribute(const string& name,
-	const string& attributeName)
-{
-	size_t i = 0;
-	while (componentList[i].componentName != NULL) {
-		if (name == componentList[i].componentName)
-			return componentList[i].GetAttribute(attributeName);
-
-		++ i;
-	}
-	
-	for (i=0; componentListRunTime!=NULL && i<componentListRunTime->size(); ++i) {
-		if (name == (*componentListRunTime)[i].componentName)
-			return (*componentListRunTime)[i].GetAttribute(
-			    attributeName);
-	}
-	
-	return "";
-}
-
-
-bool ComponentFactory::HasAttribute(const string& name,
-	const string& attributeName)
-{
-	return !GetAttribute(name, attributeName).empty();
-}
-
-
-vector<string> ComponentFactory::GetAllComponentNames(bool onlyTemplates)
-{
-	vector<string> result;
-
-	size_t i = 0;
-	while (componentList[i].componentName != NULL) {
-		if ((!onlyTemplates ||
-		    componentList[i].GetAttribute("template") == "yes"))
-			result.push_back(componentList[i].componentName);
-		++ i;
-	}
-
-	for (i=0; componentListRunTime!=NULL && i<componentListRunTime->size(); ++i) {
-		if ((!onlyTemplates ||
-		    (*componentListRunTime)[i].GetAttribute("template") == "yes"))
-			result.push_back((*componentListRunTime)[i].componentName);
-	}
-
-	return result;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_ComponentFactory_Nonexistant()
-{
-	refcount_ptr<Component> component =
-	    ComponentFactory::CreateComponent("NoNeXisT");
-	UnitTest::Assert("nonexistant component should not be created",
-	    component.IsNULL() == true);
-}
-
-static void Test_ComponentFactory_SimpleDummy()
-{
-	refcount_ptr<Component> component =
-	    ComponentFactory::CreateComponent("dummy");
-	UnitTest::Assert("dummy component should be possible to create",
-	    component.IsNULL() == false);
-
-	UnitTest::Assert("the class name should be 'dummy'",
-	    component->GetClassName(), "dummy");
-	UnitTest::Assert("the dummy component should have children",
-	    component->GetChildren().size(), 0);
-}
-
-static void Test_ComponentFactory_FromTemplate()
-{
-	refcount_ptr<Component> component =
-	    ComponentFactory::CreateComponent("testm88k");
-	UnitTest::Assert("component should be possible to create from template",
-	    component.IsNULL() == false);
-
-	UnitTest::Assert("the class name should be 'machine'",
-	    component->GetClassName(), "machine");
-	UnitTest::Assert("the component should have children",
-	    component->GetChildren().size() > 0);
-
-	refcount_ptr<Component> clone = component->Clone();
-	UnitTest::Assert("cloning should have been possible",
-	    clone.IsNULL() == false);
-
-	UnitTest::Assert("clone: the class name should still be 'machine'",
-	    clone->GetClassName(), "machine");
-	UnitTest::Assert("clone: the clone should also have children",
-	    clone->GetChildren().size() > 0);
-}
-
-static void Test_ComponentFactory_HasAttribute()
-{
-	UnitTest::Assert("nonexistantattr should not exist",
-	    !ComponentFactory::HasAttribute("testm88k", "nonexistantattr"));
-
-	UnitTest::Assert("testm88k is a machine",
-	    ComponentFactory::HasAttribute("testm88k", "machine"));
-
-	UnitTest::Assert("testm88k has a description",
-	    ComponentFactory::HasAttribute("testm88k", "description"));
-}
-
-UNITTESTS(ComponentFactory)
-{
-	UNITTEST(Test_ComponentFactory_Nonexistant);
-	UNITTEST(Test_ComponentFactory_SimpleDummy);
-	UNITTEST(Test_ComponentFactory_FromTemplate);
-	UNITTEST(Test_ComponentFactory_HasAttribute);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/debug_new.cc gxemul-0.7.0+dfsg/src/main/debug_new.cc
--- gxemul-0.6.2/src/main/debug_new.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/debug_new.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,733 +0,0 @@
-#include <iostream>
-
-/*
- *  GXemul specific changes to debug_new.cc:
- *
- *   x)	debug_new.cpp renamed debug_new.cc.
- *   x)	#include <alloca.h> commented out.
- *   x)	(unsigned) added in some places to get rid of warnings.
- *   x) a brief Doxygen section added to struct new_ptr_list_t's
- *      comment
- *   x) #print_position changed to print_position (removed the #), to
- *      suppress a Doxygen warning
- *   x) "@file" changed to "@ file" to suppress a Doxygen warning.
- *   x) variable names in local scopes changed to allow usage of GCC's -Wshadow
- *   x) a "catch point" added for catching specific (repeatable) allocations
- */
-
-#ifndef NDEBUG
-
-// -*- Mode: C++; tab-width: 4; c-basic-offset: 4; indent-tabs-mode: nil -*-
-// vim:tabstop=4:shiftwidth=4:expandtab:
-
-/*
- * Copyright (C) 2004-2005 Wu Yongwei <adah at users dot sourceforge dot net>
- *
- * This software is provided 'as-is', without any express or implied
- * warranty.  In no event will the authors be held liable for any
- * damages arising from the use of this software.
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute
- * it freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must
- *    not claim that you wrote the original software. If you use this
- *    software in a product, an acknowledgment in the product
- *    documentation would be appreciated but is not required.
- * 2. Altered source versions must be plainly marked as such, and must
- *    not be misrepresented as being the original software.
- * 3. This notice may not be removed or altered from any source
- *    distribution.
- *
- * This file is part of Stones of Nvwa:
- *      http://sourceforge.net/projects/nvwa
- *
- */
-
-/**
- * @ file    debug_new.cpp
- *
- * Implementation of debug versions of new and delete to check leakage.
- *
- * @version 3.16, 2005/11/22
- * @author  Wu Yongwei
- *
- */
-
-#include <new>
-#include <assert.h>
-#include <limits.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#ifdef __unix__
-// #include <alloca.h>
-#endif
-#ifdef _WIN32
-#include <malloc.h>
-#endif
-#include "thirdparty/fast_mutex.h"
-#include "thirdparty/static_assert.h"
-
-#if !_FAST_MUTEX_CHECK_INITIALIZATION && !defined(_NOTHREADS)
-#error "_FAST_MUTEX_CHECK_INITIALIZATION not set: check_leaks may not work"
-#endif
-
-/**
- * @def _DEBUG_NEW_ALIGNMENT
- *
- * The alignment requirement of allocated memory blocks.  It must be a
- * power of two.
- */
-#ifndef _DEBUG_NEW_ALIGNMENT
-#define _DEBUG_NEW_ALIGNMENT 16
-#endif
-
-/**
- * @def _DEBUG_NEW_CALLER_ADDRESS
- *
- * The expression to return the caller address.  print_position will
- * later on use this address to print the position information of memory
- * operation points.
- */
-#ifndef _DEBUG_NEW_CALLER_ADDRESS
-#ifdef __GNUC__
-#define _DEBUG_NEW_CALLER_ADDRESS __builtin_return_address(0)
-#else
-#define _DEBUG_NEW_CALLER_ADDRESS NULL
-#endif
-#endif
-
-/**
- * @def _DEBUG_NEW_ERROR_ACTION
- *
- * The action to take when an error occurs.  The default behaviour is to
- * call \e abort, unless \c _DEBUG_NEW_ERROR_CRASH is defined, in which
- * case a segmentation fault will be triggered instead (which can be
- * useful on platforms like Windows that do not generate a core dump
- * when \e abort is called).
- */
-#ifndef _DEBUG_NEW_ERROR_ACTION
-#ifndef _DEBUG_NEW_ERROR_CRASH
-#define _DEBUG_NEW_ERROR_ACTION abort()
-#else
-#define _DEBUG_NEW_ERROR_ACTION do { *((char*)0) = 0; abort(); } while (0)
-#endif
-#endif
-
-/**
- * @def _DEBUG_NEW_FILENAME_LEN
- *
- * The length of file name stored if greater than zero.  If it is zero,
- * only a const char pointer will be stored.  Currently the default
- * behaviour is to copy the file name, because I found that the exit
- * leakage check cannot access the address of the file name sometimes
- * (in my case, a core dump will occur when trying to access the file
- * name in a shared library after a \c SIGINT).  If the default value is
- * too small for you, try defining it to \c 52, which makes the size of
- * new_ptr_list_t 64 (it is 32 by default) on 32-bit platforms.
- */
-#ifndef _DEBUG_NEW_FILENAME_LEN
-#define _DEBUG_NEW_FILENAME_LEN 20
-#endif
-
-/**
- * @def _DEBUG_NEW_HASHTABLESIZE
- *
- * The size of the hash bucket for the table to store pointers to
- * allocated memory.  To ensure good performance, always make it a power
- * of two.
- */
-#ifndef _DEBUG_NEW_HASHTABLESIZE
-#define _DEBUG_NEW_HASHTABLESIZE 16384
-#endif
-
-/**
- * @def _DEBUG_NEW_HASH
- *
- * The hash function for the pointers.  This one has good performance in
- * test for me.
- */
-#ifndef _DEBUG_NEW_HASH
-#define _DEBUG_NEW_HASH(p) (((size_t)(p) >> 8) % _DEBUG_NEW_HASHTABLESIZE)
-#endif
-
-/**
- * @def _DEBUG_NEW_PROGNAME
- *
- * The program (executable) name to be set at compile time.  It is
- * better to assign the full program path to #new_progname in \e main
- * (at run time) than to use this (compile-time) macro, but this macro
- * serves well as a quick hack.  Note also that double quotation marks
- * need to be used around the program name, i.e., one should specify a
- * command-line option like <code>-D_DEBUG_NEW_PROGNAME=\"a.out\"</code>
- * in \e bash, or <code>-D_DEBUG_NEW_PROGNAME=\"a.exe\"</code> in the
- * Windows command prompt.
- */
-#ifndef _DEBUG_NEW_PROGNAME
-#define _DEBUG_NEW_PROGNAME NULL
-#endif
-
-/**
- * @def _DEBUG_NEW_USE_ADDR2LINE
- *
- * Whether to use \e addr2line to convert a caller address to file/line
- * information.  Defining it to a non-zero value will enable the
- * conversion (automatically done if GCC is detected).  Defining it to
- * zero will disable the conversion.
- */
-#ifndef _DEBUG_NEW_USE_ADDR2LINE
-#ifdef __GNUC__
-#define _DEBUG_NEW_USE_ADDR2LINE 1
-#else
-#define _DEBUG_NEW_USE_ADDR2LINE 0
-#endif
-#endif
-
-#ifdef _MSC_VER
-#pragma warning(disable: 4073)  // #pragma init_seg(lib) used
-#pragma warning(disable: 4290)  // C++ exception specification ignored
-#pragma init_seg(lib)
-#endif
-
-#undef  _DEBUG_NEW_EMULATE_MALLOC
-#undef  _DEBUG_NEW_REDEFINE_NEW
-/**
- * Macro to indicate whether redefinition of \c new is wanted.  Here it
- * is defined to \c 0 to disable the redefinition of \c new.
- */
-#define _DEBUG_NEW_REDEFINE_NEW 0
-#include "thirdparty/debug_new.h"
-
-/**
- * Gets the aligned value of memory block size.
- */
-#define align(s) \
-        (((s) + _DEBUG_NEW_ALIGNMENT - 1) & ~(_DEBUG_NEW_ALIGNMENT - 1))
-
-/**
- * \brief Part of Wu Yongwei's new/delete debug
- * memory leak detector.
- *
- * Structure to store the position information where \c new occurs.
- */
-struct new_ptr_list_t
-{
-    new_ptr_list_t*     next;
-    union
-    {
-#if _DEBUG_NEW_FILENAME_LEN == 0
-    const char*         file;
-#else
-    char                file[_DEBUG_NEW_FILENAME_LEN];
-#endif
-    void*               addr;
-    };
-    int                 line;
-    size_t              size;
-};
-
-/**
- * The extra memory allocated by <code>operator new</code>.
- */
-const int aligned_list_item_size = align(sizeof(new_ptr_list_t));
-
-/**
- * Array of pointer lists of a hash value.
- */
-static new_ptr_list_t* new_ptr_list[_DEBUG_NEW_HASHTABLESIZE];
-
-/**
- * Array of mutex guards to protect simultaneous access to the pointer
- * lists of a hash value.
- */
-static fast_mutex new_ptr_lock[_DEBUG_NEW_HASHTABLESIZE];
-
-/**
- * The mutex guard to protect simultaneous output to #new_output_fp.
- */
-static fast_mutex new_output_lock;
-
-/**
- * Total memory allocated in bytes.
- */
-static size_t total_mem_alloc = 0;
-
-/**
- * Flag to control whether #check_leaks will be automatically called on
- * program exit.
- */
-bool new_autocheck_flag = true;
-
-/**
- * Flag to control whether verbose messages are output.
- */
-bool new_verbose_flag = false;
-
-/**
- * Pointer to the output stream.  The default output is \e stderr, and
- * one may change it to a user stream if needed (say, #new_verbose_flag
- * is \c true and there are a lot of (de)allocations).
- */
-FILE* new_output_fp = stderr;
-
-/**
- * Pointer to the program name.  Its initial value is the macro
- * #_DEBUG_NEW_PROGNAME.  You should try to assign the program path to
- * it early in your application.  Assigning <code>argv[0]</code> to it
- * in \e main is one way.  If you use \e bash or \e ksh (or similar),
- * the following statement is probably what you want:
- * `<code>new_progname = getenv("_");</code>'.
- */
-const char* new_progname = _DEBUG_NEW_PROGNAME;
-
-#if _DEBUG_NEW_USE_ADDR2LINE
-/**
- * Tries printing the position information from an instruction address.
- * This is the version that uses \e addr2line.
- *
- * @param addr  the instruction address to convert and print
- * @return      \c true if the address is converted successfully (and
- *              the result is printed); \c false if no useful
- *              information is got (and nothing is printed)
- */
-static bool print_position_from_addr(const void* addr)
-{
-    static const void* last_addr = NULL;
-    static char last_info[256] = "";
-    if (addr == last_addr)
-    {
-        if (last_info[0] == '\0')
-            return false;
-        fprintf(new_output_fp, "%s", last_info);
-        return true;
-    }
-    if (new_progname)
-    {
-        const char addr2line_cmd[] = "addr2line -e ";
-#if   defined(__CYGWIN__) || defined(_WIN32)
-        const int  exeext_len = 4;
-#else
-        const int  exeext_len = 0;
-#endif
-#if  !defined(__CYGWIN__) && defined(__unix__)
-        const char ignore_err[] = " 2>/dev/null";
-#elif defined(__CYGWIN__) || \
-        (defined(_WIN32) && defined(WINVER) && WINVER >= 0x0500)
-        const char ignore_err[] = " 2>nul";
-#else
-        const char ignore_err[] = "";
-#endif
-        char* cmd = (char*)alloca(strlen(new_progname)
-                                  + exeext_len
-                                  + sizeof addr2line_cmd - 1
-                                  + sizeof ignore_err - 1
-                                  + sizeof(void*) * 2
-                                  + 4 /* SP + "0x" + null */);
-        strcpy(cmd, addr2line_cmd);
-        strcpy(cmd + sizeof addr2line_cmd - 1, new_progname);
-        size_t len = strlen(cmd);
-#if   defined(__CYGWIN__) || defined(_WIN32)
-        if (len <= 4
-                || (strcmp(cmd + len - 4, ".exe") != 0 &&
-                    strcmp(cmd + len - 4, ".EXE") != 0))
-        {
-            strcpy(cmd + len, ".exe");
-            len += 4;
-        }
-#endif
-        sprintf(cmd + len, " %p%s", addr, ignore_err);
-        FILE* fp = popen(cmd, "r");
-        if (fp)
-        {
-            char buffer[sizeof last_info] = "";
-            len = 0;
-            if (fgets(buffer, sizeof buffer, fp))
-            {
-                len = strlen(buffer);
-                if (buffer[len - 1] == '\n')
-                    buffer[--len] = '\0';
-            }
-            int res = pclose(fp);
-            // Display the file/line information only if the command
-            // is executed successfully and the output points to a
-            // valid position, but the result will be cached if only
-            // the command is executed successfully.
-            if (res == 0 && len > 0)
-            {
-                last_addr = addr;
-                if (buffer[len - 1] == '0' && buffer[len - 2] == ':')
-                    last_info[0] = '\0';
-                else
-                {
-                    fprintf(new_output_fp, "%s", buffer);
-                    strcpy(last_info, buffer);
-                    return true;
-                }
-            }
-        }
-    }
-    return false;
-}
-#else
-/**
- * Tries printing the position information from an instruction address.
- * This is the stub version that does nothing at all.
- *
- * @return      \c false always
- */
-static bool print_position_from_addr(const void*)
-{
-    return false;
-}
-#endif // _DEBUG_NEW_USE_ADDR2LINE
-
-/**
- * Prints the position information of a memory operation point.  When \c
- * _DEBUG_NEW_USE_ADDR2LINE is defined to a non-zero value, this
- * function will try to convert a given caller address to file/line
- * information with \e addr2line.
- *
- * @param ptr   source file name if \e line is non-zero; caller address
- *              otherwise
- * @param line  source line number if non-zero; indication that \e ptr
- *              is the caller address otherwise
- */
-static void print_position(const void* ptr, int line)
-{
-    line &= ~INT_MIN;       // Result from new[] if highest bit set: Ignore
-    if (line != 0)          // Is file/line information present?
-    {
-        fprintf(new_output_fp, "%s:%d", (const char*)ptr, line);
-    }
-    else if (ptr != NULL)   // Is caller address present?
-    {
-        if (!print_position_from_addr(ptr)) // Fail to get source position?
-            fprintf(new_output_fp, "%p", ptr);
-    }
-    else                    // No information is present
-    {
-        fprintf(new_output_fp, "<Unknown>");
-    }
-}
-
-/**
- * Searches for the raw pointer given a user pointer.  The term `raw
- * pointer' here refers to the pointer to the pointer to originally
- * <em>malloc</em>'d memory.
- *
- * @param pointer       user pointer to search for
- * @param hash_index    hash index of the user pointer
- * @return              the raw pointer if searching is successful; or
- *                      \c NULL otherwise
- */
-static new_ptr_list_t** search_pointer(void* pointer, size_t hash_index)
-{
-    new_ptr_list_t** raw_ptr = &new_ptr_list[hash_index];
-    while (*raw_ptr)
-    {
-        if ((char*)*raw_ptr + aligned_list_item_size == pointer)
-        {
-            return raw_ptr;
-        }
-        raw_ptr = &(*raw_ptr)->next;
-    }
-    return NULL;
-}
-
-/**
- * Frees memory and adjusts pointers relating to a raw pointer.  If the
- * highest bit of \c line (set from a previous <code>new[]</code> call)
- * does not agree with \c array_mode, program will abort with an error
- * message.
- *
- * @param raw_ptr       raw pointer to free
- * @param addr          pointer to the caller
- * @param array_mode    flag indicating whether it is invoked by a
- *                      <code>delete[]</code> call
- */
-static void free_pointer(new_ptr_list_t** raw_ptr, void* addr, bool array_mode)
-{
-    new_ptr_list_t* ptr = *raw_ptr;
-    int array_mode_mismatch = array_mode ^ ((ptr->line & INT_MIN) != 0);
-    if (array_mode_mismatch)
-    {
-        const char* msg;
-        if (array_mode)
-            msg = "delete[] after new";
-        else
-            msg = "delete after new[]";
-        fast_mutex_autolock lock(new_output_lock);
-        fprintf(new_output_fp,
-                "%s: pointer %p (size %u)\n\tat ",
-                msg,
-                (char*)ptr + aligned_list_item_size,
-                (unsigned) ptr->size);
-        print_position(addr, 0);
-        fprintf(new_output_fp, "\n\toriginally allocated at ");
-        if ((ptr->line & ~INT_MIN) != 0)
-            print_position(ptr->file, ptr->line);
-        else
-            print_position(ptr->addr, ptr->line);
-        fprintf(new_output_fp, "\n");
-        fflush(new_output_fp);
-        _DEBUG_NEW_ERROR_ACTION;
-    }
-    total_mem_alloc -= ptr->size;
-    if (new_verbose_flag)
-    {
-        fast_mutex_autolock lock(new_output_lock);
-        fprintf(new_output_fp,
-                "delete: freeing  %p (size %u, %u bytes still allocated)\n",
-                (char*)ptr + aligned_list_item_size,
-                (unsigned) ptr->size, (unsigned) total_mem_alloc);
-    }
-    *raw_ptr = ptr->next;
-    memset(ptr, 0xdd, ptr->size + aligned_list_item_size);
-    free(ptr);
-    return;
-}
-
-/**
- * Checks for memory leaks.
- *
- * @return  zero if no leakage is found; the number of leaks otherwise
- */
-int check_leaks()
-{
-    int leak_cnt = 0;
-    for (int i = 0; i < _DEBUG_NEW_HASHTABLESIZE; ++i)
-    {
-        fast_mutex_autolock lock(new_ptr_lock[i]);
-        new_ptr_list_t* ptr = new_ptr_list[i];
-        if (ptr == NULL)
-            continue;
-        while (ptr)
-        {
-            fast_mutex_autolock lock2(new_output_lock);
-            fprintf(new_output_fp,
-                    "Leaked object at %p (size %u, ",
-                    (char*)ptr + aligned_list_item_size,
-                    (unsigned) ptr->size);
-            if ((ptr->line & ~INT_MIN) != 0)
-                print_position(ptr->file, ptr->line);
-            else
-                print_position(ptr->addr, ptr->line);
-            fprintf(new_output_fp, ")\n");
-            ptr = ptr->next;
-            ++leak_cnt;
-        }
-    }
-    return leak_cnt;
-}
-
-void* operator new(size_t size, const char* file, int line)
-{
-    assert((line & INT_MIN) == 0);
-    STATIC_ASSERT((_DEBUG_NEW_ALIGNMENT & (_DEBUG_NEW_ALIGNMENT - 1)) == 0,
-                  Alignment_must_be_power_of_two);
-    size_t s = size + aligned_list_item_size;
-    new_ptr_list_t* ptr = (new_ptr_list_t*)malloc(s);
-    if (ptr == NULL)
-    {
-        fast_mutex_autolock lock(new_output_lock);
-        fprintf(new_output_fp,
-                "new:  out of memory when allocating %u bytes\n",
-                (unsigned) size);
-        fflush(new_output_fp);
-        _DEBUG_NEW_ERROR_ACTION;
-    }
-    void* pointer = (char*)ptr + aligned_list_item_size;
-
-    // GXemul hack/addition: Crash on a specific allocation. Useful
-    // for getting a call stack for a memory leak, at the point where the
-    // actual allocation took place. (Only possible if the address is
-    // stable over multiple runs.)
-    if ((size_t)pointer == 0xfefefefecdcdcdcdULL)
-    {
-	static int counter = 0;
-	counter ++;
-    	std::cerr << "--> MEMORY LEAK CATCH POINT, counter = " << counter << "\n";
-
-	if (counter == -42)
-	{
-	    abort();
-	}
-    }
-
-    size_t hash_index = _DEBUG_NEW_HASH(pointer);
-#if _DEBUG_NEW_FILENAME_LEN == 0
-    ptr->file = file;
-#else
-    if (line)
-        strncpy(ptr->file, file, _DEBUG_NEW_FILENAME_LEN - 1)
-                [_DEBUG_NEW_FILENAME_LEN - 1] = '\0';
-    else
-        ptr->addr = (void*)file;
-#endif
-    ptr->line = line;
-    ptr->size = size;
-    {
-        fast_mutex_autolock lock(new_ptr_lock[hash_index]);
-        ptr->next = new_ptr_list[hash_index];
-        new_ptr_list[hash_index] = ptr;
-    }
-    if (new_verbose_flag)
-    {
-        fast_mutex_autolock lock(new_output_lock);
-        fprintf(new_output_fp,
-                "new:  allocated  %p (size %u, ",
-                pointer, (unsigned) size);
-        if (line != 0)
-            print_position(ptr->file, ptr->line);
-        else
-            print_position(ptr->addr, ptr->line);
-        fprintf(new_output_fp, ")\n");
-    }
-    total_mem_alloc += size;
-    return pointer;
-}
-
-void* operator new[](size_t size, const char* file, int line)
-{
-    void* pointer = operator new(size, file, line);
-    new_ptr_list_t* ptr =
-            (new_ptr_list_t*)((char*)pointer - aligned_list_item_size);
-    assert((ptr->line & INT_MIN) == 0);
-    ptr->line |= INT_MIN;   // Result from new[] if highest bit set: Set
-    return pointer;
-}
-
-void* operator new(size_t size) throw(std::bad_alloc)
-{
-    return operator new(size, (char*)_DEBUG_NEW_CALLER_ADDRESS, 0);
-}
-
-void* operator new[](size_t size) throw(std::bad_alloc)
-{
-    return operator new[](size, (char*)_DEBUG_NEW_CALLER_ADDRESS, 0);
-}
-
-#if !defined(__BORLANDC__) || __BORLANDC__ > 0x551
-void* operator new(size_t size, const std::nothrow_t&) throw()
-{
-    return operator new(size, (char*)_DEBUG_NEW_CALLER_ADDRESS, 0);
-}
-
-void* operator new[](size_t size, const std::nothrow_t&) throw()
-{
-    return operator new[](size, (char*)_DEBUG_NEW_CALLER_ADDRESS, 0);
-}
-#endif
-
-void operator delete(void* pointer) throw()
-{
-    if (pointer == NULL)
-        return;
-    size_t hash_index = _DEBUG_NEW_HASH(pointer);
-    fast_mutex_autolock lock(new_ptr_lock[hash_index]);
-    new_ptr_list_t** raw_ptr = search_pointer(pointer, hash_index);
-    if (raw_ptr == NULL)
-    {
-        fast_mutex_autolock lock2(new_output_lock);
-        fprintf(new_output_fp, "delete: invalid pointer %p at ", pointer);
-        print_position(_DEBUG_NEW_CALLER_ADDRESS, 0);
-        fprintf(new_output_fp, "\n");
-        fflush(new_output_fp);
-        _DEBUG_NEW_ERROR_ACTION;
-    }
-    free_pointer(raw_ptr, _DEBUG_NEW_CALLER_ADDRESS, false);
-}
-
-void operator delete[](void* pointer) throw()
-{
-    if (pointer == NULL)
-        return;
-    size_t hash_index = _DEBUG_NEW_HASH(pointer);
-    fast_mutex_autolock lock(new_ptr_lock[hash_index]);
-    new_ptr_list_t** raw_ptr = search_pointer(pointer, hash_index);
-    if (raw_ptr == NULL)
-    {
-        fast_mutex_autolock lock2(new_output_lock);
-        fprintf(new_output_fp, "delete[]: invalid pointer %p at ", pointer);
-        print_position(_DEBUG_NEW_CALLER_ADDRESS, 0);
-        fprintf(new_output_fp, "\n");
-        fflush(new_output_fp);
-        _DEBUG_NEW_ERROR_ACTION;
-    }
-    free_pointer(raw_ptr, _DEBUG_NEW_CALLER_ADDRESS, true);
-}
-
-#if HAS_PLACEMENT_DELETE
-void operator delete(void* pointer, const char* file, int line) throw()
-{
-    if (new_verbose_flag)
-    {
-        fast_mutex_autolock lock(new_output_lock);
-        fprintf(new_output_fp,
-                "info: exception thrown on initializing object at %p (",
-                pointer);
-        print_position(file, line);
-        fprintf(new_output_fp, ")\n");
-    }
-    operator delete(pointer);
-}
-
-void operator delete[](void* pointer, const char* file, int line) throw()
-{
-    if (new_verbose_flag)
-    {
-        fast_mutex_autolock lock(new_output_lock);
-        fprintf(new_output_fp,
-                "info: exception thrown on initializing objects at %p (",
-                pointer);
-        print_position(file, line);
-        fprintf(new_output_fp, ")\n");
-    }
-    operator delete[](pointer);
-}
-
-void operator delete(void* pointer, const std::nothrow_t&) throw()
-{
-    operator delete(pointer, (char*)_DEBUG_NEW_CALLER_ADDRESS, 0);
-}
-
-void operator delete[](void* pointer, const std::nothrow_t&) throw()
-{
-    operator delete[](pointer, (char*)_DEBUG_NEW_CALLER_ADDRESS, 0);
-}
-#endif // HAS_PLACEMENT_DELETE
-
-int __debug_new_counter::_count = 0;
-
-/**
- * Constructor to increment the count.
- */
-__debug_new_counter::__debug_new_counter()
-{
-    ++_count;
-}
-
-/**
- * Destructor to decrement the count.  When the count is zero,
- * #check_leaks will be called.
- */
-__debug_new_counter::~__debug_new_counter()
-{
-    if (--_count == 0 && new_autocheck_flag)
-        if (check_leaks())
-        {
-            new_verbose_flag = true;
-#if defined(__GNUC__) && __GNUC__ >= 3
-            if (!getenv("GLIBCPP_FORCE_NEW") && !getenv("GLIBCXX_FORCE_NEW"))
-                fprintf(new_output_fp,
-"*** WARNING:  GCC 3 or later is detected, please make sure the\n"
-"    environment variable GLIBCPP_FORCE_NEW (GCC 3.2 and 3.3) or\n"
-"    GLIBCXX_FORCE_NEW (GCC 3.4 and later) is defined.  Check the\n"
-"    README file for details.\n");
-#endif
-        }
-}
-
-#endif	// NDEBUG
diff -Nru gxemul-0.6.2/src/main/EscapedString.cc gxemul-0.7.0+dfsg/src/main/EscapedString.cc
--- gxemul-0.6.2/src/main/EscapedString.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/EscapedString.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,196 +0,0 @@
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "EscapedString.h"
-
-
-EscapedString::EscapedString(const string& str)
-	: m_str(str)
-{
-}
-
-
-string EscapedString::Generate() const
-{
-	string result = "\"";
-
-	for (size_t i=0; i<m_str.length(); i++) {
-		char ch = m_str[i];
-
-		switch (ch) {
-		case '\n':
-			result += "\\n";
-			break;
-		case '\r':
-			result += "\\r";
-			break;
-		case '\t':
-			result += "\\t";
-			break;
-		case '"':
-			result += "\\\"";
-			break;
-		case '\\':
-			result += "\\\\";
-			break;
-		default:
-			result += ch;
-		}
-	}
-
-	result += "\"";
-
-	return result;
-}
-
-
-string EscapedString::Decode(bool& success) const
-{
-	success = false;
-
-	// Not an escaped string? Then return failure.
-	if (m_str.size() < 2 || m_str[0] != '"'
-	    || m_str[m_str.size() - 1] != '"')
-		return "";
-
-	string result = "";
-	size_t i;
-	
-	for (i = 1; i < m_str.length() - 1; i++) {
-		char ch = m_str[i];
-
-		switch (ch) {
-		case '\\':
-			{
-				char ch2 = m_str[++i];
-				switch (ch2) {
-				case 'n':
-					result += '\n';
-					break;
-				case 'r':
-					result += '\r';
-					break;
-				case 't':
-					result += '\t';
-					break;
-				default:
-					result += ch2;
-				}
-				break;
-			}
-		default:
-			result += ch;
-		}
-	}
-
-	if (i == m_str.length() - 1)
-		success = true;
-
-	return result;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_EscapedString_Generate()
-{
-	UnitTest::Assert("trivial escape: normal text",
-	    EscapedString("hello world 123").Generate() ==
-	    "\"hello world 123\"");
-
-	UnitTest::Assert("escape tab",
-	    EscapedString("hi\tworld").Generate() ==
-	    "\"hi\\tworld\"");
-
-	UnitTest::Assert("escape newline and carriage return",
-	    EscapedString("hi\nworld\ragain").Generate() ==
-	    "\"hi\\nworld\\ragain\"");
-
-	UnitTest::Assert("escape quotes",
-	    EscapedString("hi'123\"456\"789").Generate() ==
-	    "\"hi'123\\\"456\\\"789\"");
-
-	UnitTest::Assert("escaped escape char",
-	    EscapedString("Hello\\world").Generate() ==
-	    "\"Hello\\\\world\"");
-}
-
-static void Test_EscapedString_Decode()
-{
-	bool success = false;
-
-	UnitTest::Assert("trivial escape: normal text",
-	    EscapedString("\"hello world 123\"").Decode(success) ==
-	    "hello world 123");
-	UnitTest::Assert("success failed? (1)", success == true);
-
-	success = false;
-	UnitTest::Assert("escape tab",
-	    EscapedString("\"hi\\tworld\"").Decode(success) ==
-	    "hi\tworld");
-	UnitTest::Assert("success failed? (2)", success == true);
-
-	success = false;
-	UnitTest::Assert("escape newline and carriage return",
-	    EscapedString("\"hi\\nworld\\ragain\"").Decode(success) ==
-	    "hi\nworld\ragain");
-	UnitTest::Assert("success failed? (3)", success == true);
-
-	success = false;
-	UnitTest::Assert("escape quotes",
-	    EscapedString("\"hi'123\\\"456\\\"789\"").Decode(success) ==
-	    "hi'123\"456\"789");
-	UnitTest::Assert("success failed? (4)", success == true);
-
-	success = false;
-	UnitTest::Assert("escaped escape char",
-	    EscapedString("\"Hello\\\\world\"").Decode(success) ==
-	    "Hello\\world");
-	UnitTest::Assert("success failed? (5)", success == true);
-}
-
-static void Test_EscapedString_Decode_WithoutQuotes()
-{
-	bool success = true;
-
-	UnitTest::Assert("trivial escape: normal text",
-	    EscapedString("hello world 123").Decode(success) ==
-	    "");
-	UnitTest::Assert("success should have failed", success == false);
-}
-
-UNITTESTS(EscapedString)
-{
-	UNITTEST(Test_EscapedString_Generate);
-	UNITTEST(Test_EscapedString_Decode);
-	UNITTEST(Test_EscapedString_Decode_WithoutQuotes);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/FileLoader.cc gxemul-0.7.0+dfsg/src/main/FileLoader.cc
--- gxemul-0.6.2/src/main/FileLoader.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/FileLoader.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,313 +0,0 @@
-/*
- *  Copyright (C) 2008-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <string.h>
-#include <fstream>
-
-using std::ifstream;
-
-#include "AddressDataBus.h"
-#include "Component.h"
-#include "FileLoader.h"
-#include "FileLoader_aout.h"
-#include "FileLoader_bout.h"
-#include "FileLoader_ELF.h"
-#include "FileLoader_raw.h"
-
-
-FileLoader::FileLoader(const string& filename)
-	: m_filename(filename)
-{
-	m_fileLoaders.push_back(new FileLoader_aout(filename));
-	m_fileLoaders.push_back(new FileLoader_bout(filename));
-	m_fileLoaders.push_back(new FileLoader_ELF(filename));
-	m_fileLoaders.push_back(new FileLoader_raw(filename));
-}
-
-
-const string& FileLoader::GetFilename() const
-{
-	return m_filename;
-}
-
-
-string FileLoader::DetectFileFormat(refcount_ptr<const FileLoaderImpl>& loader) const
-{
-	loader = NULL;
-
-	// TODO: Disk images?
-
-	ifstream file(m_filename.c_str());
-
-	unsigned char buf[512];
-	memset(buf, 0, sizeof(buf));
-	size_t amountRead = 0;
-	if (file.is_open()) {
-		file.read((char *)buf, sizeof(buf));
-		amountRead = file.gcount();
-	}
-
-	// Ask all file loaders about how well they handle the format. Return
-	// the format string from the loader that had the highest score.
-	float bestMatch = 0.0;
-	string bestFormat = "Unknown";
-	FileLoaderImplVector::const_iterator it = m_fileLoaders.begin();
-	for (; it != m_fileLoaders.end(); ++it) {
-		float match;
-		string format = (*it)->DetectFileType(buf, amountRead, match);
-		if (match > bestMatch) {
-			bestMatch = match;
-			bestFormat = format;
-			loader = *it;
-		}
-	}
-
-	if (bestMatch == 0.0 && !file.is_open())
-		return "Not accessible";
-
-	return bestFormat;
-}
-
-
-bool FileLoader::Load(refcount_ptr<Component> component, ostream& messages) const
-{
-	AddressDataBus * bus = component->AsAddressDataBus();
-	if (bus == NULL) {
-		// We cannot load into something that isn't an AddressDataBus.
-		messages << "Error: " << component->GenerateShortestPossiblePath()
-		    << " is not an AddressDataBus.\n";
-		return false;
-	}
-
-	refcount_ptr<const FileLoaderImpl> loaderImpl;
-	string fileFormat = DetectFileFormat(loaderImpl);
-
-	if (!loaderImpl.IsNULL())
-		return loaderImpl->LoadIntoComponent(component, messages);
-
-	messages << "Error: File format '" <<
-	    fileFormat << "' not yet implemented. TODO\n";
-
-	return false;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_FileLoader_Constructor()
-{
-	FileLoader fileLoader("test/FileLoader_ELF_MIPS");
-	UnitTest::Assert("filename mismatch?",
-	    fileLoader.GetFilename(), "test/FileLoader_ELF_MIPS");
-}
-
-static void Test_FileLoader_Constructor_NonExistingFile()
-{
-	FileLoader fileLoader("test/Nonexisting");
-	UnitTest::Assert("filename mismatch?",
-	    fileLoader.GetFilename(), "test/Nonexisting");
-}
-
-static void Test_FileLoader_DetectFileFormat_NonexistingFile()
-{
-	FileLoader fileLoader("test/Nonexisting");
-	refcount_ptr<const FileLoaderImpl> loaderImpl;
-	UnitTest::Assert("file format detection failure?",
-	    fileLoader.DetectFileFormat(loaderImpl), "Not accessible");
-}
-
-static void Test_FileLoader_DetectFileFormat_NonsenseFile()
-{
-	FileLoader fileLoader("test/FileLoader_NonsenseFile");
-	refcount_ptr<const FileLoaderImpl> loaderImpl;
-	UnitTest::Assert("file format detection failure?",
-	    fileLoader.DetectFileFormat(loaderImpl), "Unknown");
-}
-
-static void Test_FileLoader_DetectFileFormat_ELF32()
-{
-	FileLoader fileLoader("test/FileLoader_ELF_MIPS");
-	refcount_ptr<const FileLoaderImpl> loaderImpl;
-	UnitTest::Assert("file format detection failure?",
-	    fileLoader.DetectFileFormat(loaderImpl), "ELF32");
-}
-
-static void Test_FileLoader_DetectFileFormat_ELF64()
-{
-	FileLoader fileLoader("test/FileLoader_ELF_SH5");
-	refcount_ptr<const FileLoaderImpl> loaderImpl;
-	UnitTest::Assert("file format detection failure?",
-	    fileLoader.DetectFileFormat(loaderImpl), "ELF64");
-}
-
-static void Test_FileLoader_DetectFileFormat_aout_88K()
-{
-	FileLoader fileLoader("test/FileLoader_A.OUT_M88K");
-	refcount_ptr<const FileLoaderImpl> loaderImpl;
-	UnitTest::Assert("file format detection failure?",
-	    fileLoader.DetectFileFormat(loaderImpl), "a.out_M88K_fromBeginning");
-}
-
-static void Test_FileLoader_DetectFileFormat_bout_i960()
-{
-	FileLoader fileLoader("test/FileLoader_B.OUT_i960");
-	refcount_ptr<const FileLoaderImpl> loaderImpl;
-	UnitTest::Assert("file format detection failure?",
-	    fileLoader.DetectFileFormat(loaderImpl), "b.out_i960_little");
-}
-
-static refcount_ptr<Component> SetupTestMachineAndLoad(
-	string machineName, string fileName, bool ramAtZero)
-{
-	FileLoader fileLoader(fileName);
-	refcount_ptr<Component> machine =
-	    ComponentFactory::CreateComponent(machineName);
-	UnitTest::Assert("could not add machine type?", !machine.IsNULL());
-
-	machine->SetVariableValue("name", "\"machine\"");
-	refcount_ptr<Component> component =
-	    machine->LookupPath("machine.mainbus0.cpu0");
-	UnitTest::Assert("could not look up CPU to load into?",
-	    !component.IsNULL());
-
-	refcount_ptr<Component> ram = machine->LookupPath("machine.mainbus0.ram0");
-	UnitTest::Assert("could not look up RAM?", !ram.IsNULL());
-	if (ramAtZero)
-		ram->SetVariableValue("memoryMappedBase", "0");
-
-	stringstream messages;
-	UnitTest::Assert("could not load the file " + fileName + " for"
-	    " machine " + machineName, fileLoader.Load(component, messages));
-
-	return machine;
-}
-
-#if 0
-static void Test_FileLoader_Load_ELF32()
-{
-	// Yes, it is odd to load a MIPS binary into a RISC-V machine, but still...
-	refcount_ptr<Component> machine =
-	    SetupTestMachineAndLoad("riscv-virt", "test/FileLoader_ELF_MIPS", false);
-
-	// Read from CPU, to make sure the file was loaded:
-	refcount_ptr<Component> cpu =
-	    machine->LookupPath("machine.mainbus0.cpu0");
-	AddressDataBus * bus = cpu->AsAddressDataBus();
-	bus->AddressSelect((int32_t)0x00010000);
-	uint32_t word = 0x12345678;
-	bus->ReadData(word, BigEndian);
-	UnitTest::Assert("memory (CPU) wasn't filled with data from the file?",
-	    word, 0x8f8b8008);
-
-	// Read directly from RAM too, to make sure the file was loaded:
-	refcount_ptr<Component> ram =
-	    machine->LookupPath("machine.mainbus0.ram0");
-	AddressDataBus * ramBus = ram->AsAddressDataBus();
-	ramBus->AddressSelect(0x1000c);
-	uint32_t word2 = 0x12345678;
-	ramBus->ReadData(word2, BigEndian);
-	UnitTest::Assert("memory (RAM) wasn't filled with data from the file?",
-	    word2, 0x006b7021);
-}
-#endif
-
-static void Test_FileLoader_Load_ELF64()
-{
-	refcount_ptr<Component> machine =
-	    SetupTestMachineAndLoad("riscv-virt", "test/FileLoader_ELF_RISCV64", true);
-
-	// Read from CPU, to make sure the file was loaded:
-	refcount_ptr<Component> cpu =
-	    machine->LookupPath("machine.mainbus0.cpu0");
-	AddressDataBus * bus = cpu->AsAddressDataBus();
-	bus->AddressSelect((int32_t)0x00010078);
-	uint32_t word = 0x12345678;
-	bus->ReadData(word, BigEndian);
-	UnitTest::Assert("memory (CPU) wasn't filled with data from the file?",
-	    word, 0x011122ec);
-
-	// Read directly from RAM too, to make sure the file was loaded:
-	refcount_ptr<Component> ram =
-	    machine->LookupPath("machine.mainbus0.ram0");
-	AddressDataBus * ramBus = ram->AsAddressDataBus();
-	ramBus->AddressSelect(0x1007c);
-	uint32_t word2 = 0x12345678;
-	ramBus->ReadData(word2, BigEndian);
-	UnitTest::Assert("memory (RAM) wasn't filled with data from the file?",
-	    word2, 0x0010aa87);
-}
-
-static void Test_FileLoader_Load_aout()
-{
-	refcount_ptr<Component> machine =
-	    SetupTestMachineAndLoad("testm88k", "test/FileLoader_A.OUT_M88K", true);
-
-	// Read from CPU, to make sure the file was loaded:
-	refcount_ptr<Component> cpu =
-	    machine->LookupPath("machine.mainbus0.cpu0");
-	AddressDataBus * bus = cpu->AsAddressDataBus();
-	bus->AddressSelect((int32_t)0x12b8);
-	uint32_t word = 0x12345678;
-	bus->ReadData(word, BigEndian);
-	UnitTest::Assert("memory (CPU) wasn't filled with data from the file?",
-	    word, 0x67ff0020);
-
-	// Read directly from RAM too, to make sure the file was loaded:
-	refcount_ptr<Component> ram =
-	    machine->LookupPath("machine.mainbus0.ram0");
-	AddressDataBus * ramBus = ram->AsAddressDataBus();
-	ramBus->AddressSelect(0x12e0);
-	uint32_t word2 = 0xfdecba98;
-	ramBus->ReadData(word2, BigEndian);
-	UnitTest::Assert("memory (RAM) wasn't filled with data from the file?",
-	    word2, 0xf6c05802);
-}
-
-UNITTESTS(FileLoader)
-{
-	UNITTEST(Test_FileLoader_Constructor);
-	UNITTEST(Test_FileLoader_Constructor_NonExistingFile);
-	
-	UNITTEST(Test_FileLoader_DetectFileFormat_NonexistingFile);
-	UNITTEST(Test_FileLoader_DetectFileFormat_NonsenseFile);
-	UNITTEST(Test_FileLoader_DetectFileFormat_ELF32);
-	UNITTEST(Test_FileLoader_DetectFileFormat_ELF64);
-	UNITTEST(Test_FileLoader_DetectFileFormat_aout_88K);
-	UNITTEST(Test_FileLoader_DetectFileFormat_bout_i960);
-
-	// UNITTEST(Test_FileLoader_Load_ELF32);
-	UNITTEST(Test_FileLoader_Load_ELF64);
-	UNITTEST(Test_FileLoader_Load_aout);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/fileloaders/FileLoader_aout.cc gxemul-0.7.0+dfsg/src/main/fileloaders/FileLoader_aout.cc
--- gxemul-0.6.2/src/main/fileloaders/FileLoader_aout.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/fileloaders/FileLoader_aout.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,357 +0,0 @@
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <string.h>
-#include <fstream>
-#include <iomanip>
-
-using std::setw;
-using std::setfill;
-using std::ifstream;
-
-#include "AddressDataBus.h"
-#include "components/CPUComponent.h"
-#include "FileLoader_aout.h"
-
-#include "thirdparty/exec_aout.h"
-
-struct aout_symbol {
-	uint32_t	strindex;
-	uint32_t	type;
-	uint32_t	addr;
-};
-
-
-FileLoader_aout::FileLoader_aout(const string& filename)
-	: FileLoaderImpl(filename)
-{
-}
-
-
-string FileLoader_aout::DetectFileType(unsigned char *buf, size_t buflen, float& matchness) const
-{
-	matchness = 0.9;
-
-	if (buf[0]==0x00 && buf[1]==0x8b && buf[2]==0x01 && buf[3]==0x07) {
-		/*  MIPS a.out  */
-		return "a.out_MIPS";
-	}
-	if (buf[0]==0x00 && buf[1]==0x87 && buf[2]==0x01 && buf[3]==0x08) {
-		/*  M68K a.out  */
-		// AOUT_FLAG_VADDR_ZERO_HACK for OpenBSD/mac68k
-		return "a.out_M68K_vaddr0";
-	}
-// Luna88k a.out for OpenBSD is _almost_ like for MVME88K... just a difference
-// of entry point (?)
-//	if (buf[0]==0x00 && buf[1]==0x99 && buf[2]==0x01 && buf[3]==0x07) {
-//		/*  OpenBSD/luna88k a.out  */
-//		return "a.out_M88K_fromBeginningEntryAfterHeader";
-//	}
-	if (buf[0]==0x00 && buf[1]==0x99 && buf[2]==0x01 && buf[3]==0x0b) {
-		/*  OpenBSD/M88K a.out  */
-		return "a.out_M88K_fromBeginning";
-	}
-	if (buf[0]==0x00 && buf[1]==0x8f && buf[2]==0x01 && buf[3]==0x0b) {
-		/*  ARM a.out  */
-		return "a.out_ARM_fromBeginning";
-	}
-	if (buf[0]==0x00 && buf[1]==0x86 && buf[2]==0x01 && buf[3]==0x0b) {
-		/*  i386 a.out (old OpenBSD and NetBSD etc)  */
-		return "a.out_i386_fromBeginning";
-	}
-	if (buf[0]==0x01 && buf[1]==0x03 && buf[2]==0x01 && buf[3]==0x07) {
-		/*  SPARC a.out (old 32-bit NetBSD etc)  */
-		return "a.out_SPARC_noSizes";
-	}
-	if (buf[0]==0x00 && buf[2]==0x00 && buf[8]==0x7a && buf[9]==0x75) {
-		/*  DEC OSF1 on MIPS:  */
-		return "a.out_MIPS_osf1";
-	}
-
-	matchness = 0.0;
-	return "";
-}
-
-
-static uint32_t unencode32(uint8_t *p, Endianness endianness)
-{
-	uint32_t res;
-	
-	if (endianness == BigEndian)
-		res = p[3] + (p[2] << 8) + (p[1] << 16) + (p[0] << 24);
-	else
-		res = p[0] + (p[1] << 8) + (p[2] << 16) + (p[3] << 24);
-
-	return res;
-}
-
-
-bool FileLoader_aout::LoadIntoComponent(refcount_ptr<Component> component, ostream& messages) const
-{
-	AddressDataBus* bus = component->AsAddressDataBus();
-	if (bus == NULL) {
-		messages << "Target is not an AddressDataBus.\n";
-		return false;
-	}
-
-	ifstream file(Filename().c_str());
-	if (!file.is_open()) {
-		messages << "Unable to read file.\n";
-		return false;
-	}
-
-	unsigned char buf[65536];
-
-	memset(buf, 0, sizeof(buf));
-	file.seekg(0, std::ios_base::end);
-	uint64_t totalSize = file.tellg();
-	file.seekg(0, std::ios_base::beg);
-	file.read((char *)buf, totalSize < sizeof(buf)? totalSize : sizeof(buf));
-	size_t amountRead = file.gcount();
-
-	float matchness;
-	string format = DetectFileType(buf, amountRead, matchness);
-
-	if (format == "") {
-		messages << "Unknown a.out format.\n";
-		return false;
-	}
-
-	file.seekg(0, std::ios_base::beg);
-
-	Endianness endianness = BigEndian;
-	StateVariable* var = component->GetVariable("bigendian");
-	if (var == NULL) {
-		messages << "Target does not have the 'bigendian' variable,"
-		    " which is needed to\n"
-		    "load a.out files.\n";
-		return false;
-	}
-
-	endianness = var->ToInteger() == 0? LittleEndian : BigEndian;
-
-	struct exec aout_header;
-	uint32_t entry, datasize, textsize;
-	int32_t symbsize = 0;
-	uint32_t vaddr, total_len;
-
-	if (format.substr(format.length()-5, 5) == "_osf1") {
-		file.read((char *)buf, 32);
-		if (file.gcount() != 32) {
-			messages << "The file is too small to be an OSF1 a.out.\n";
-			return false;
-		}
-
-		vaddr = unencode32(buf + 16, endianness);
-		entry = unencode32(buf + 20, endianness);
-
-		symbsize = 0;
-		file.seekg(0, std::ios_base::end);
-		/*  This is of course wrong, but should work anyway:  */
-		textsize = (uint32_t) file.tellg() - 512;
-		datasize = 0;
-		file.seekg(512, std::ios_base::beg);
-	} else if (format.substr(format.length()-8, 8) == "_noSizes") {
-		file.seekg(0, std::ios_base::end);
-		textsize = (uint32_t) file.tellg() - 32;
-		datasize = 0;
-		vaddr = entry = 0;
-		file.seekg(32, std::ios_base::beg);
-	} else {
-		file.read((char *)&aout_header, sizeof(aout_header));
-		if (file.gcount() != sizeof(aout_header)) {
-			messages << "The file is too small to be an a.out.\n";
-			return false;
-		}
-
-		entry = unencode32((unsigned char*)&aout_header.a_entry, endianness);
-
-		vaddr = entry;
-
-		if (format.substr(format.length()-7, 7) == "_vaddr0")
-			vaddr = 0;
-
-		textsize = unencode32((unsigned char*)&aout_header.a_text, endianness);
-		datasize = unencode32((unsigned char*)&aout_header.a_data, endianness);
-		symbsize = unencode32((unsigned char*)&aout_header.a_syms, endianness);
-	}
-
-	if (format.substr(format.length()-14, 14) == "_fromBeginning") {
-		file.seekg(0, std::ios_base::beg);
-		vaddr &= ~0xfff;
-	}
-
-	messages.flags(std::ios::hex);
-	messages << "a.out: entry point 0x";
-	messages << setw(8) << setfill('0') << (uint32_t) entry << "\n";
-
-	messages.flags(std::ios::dec);
-	messages << "text + data = " << textsize << " + " << datasize << " bytes\n";
-
-	// Load text and data:
-	total_len = textsize + datasize;
-	while (total_len != 0) {
-		int len = total_len > sizeof(buf) ? sizeof(buf) : total_len;
-		file.read((char *)buf, len);
-		len = file.gcount();
-		if (len < 1)
-			break;
-
-		// Write to the bus, one byte at a time.
-		for (int k=0; k<len; ++k) {
-			bus->AddressSelect(vaddr);
-			if (!bus->WriteData(buf[k])) {
-				messages.flags(std::ios::hex);
-				messages << "Failed to write data to virtual "
-				    "address 0x" << vaddr << "\n";
-				return false;
-			}
-			
-			++ vaddr;
-		}
-
-		total_len -= len;
-	}
-
-	if (total_len != 0) {
-		messages << "Failed to read the entire file.\n";
-		return false;
-	}
-
-	SymbolRegistry* symbolRegistry = NULL;
-	CPUComponent* cpu = component->AsCPUComponent();
-	if (cpu != NULL)
-		symbolRegistry = &cpu->GetSymbolRegistry();
-
-	// Symbols:
-	if (symbolRegistry != NULL && symbsize > 0) {
-		messages.flags(std::ios::dec);
-		messages << "symbols: " << symbsize << " bytes at 0x";
-		messages.flags(std::ios::hex);
-		messages << file.tellg() << "\n";
-
-		vector<char> symbolData;
-		symbolData.resize(symbsize);
-		file.read(&symbolData[0], symbsize);
-		if (file.gcount() != symbsize) {
-			messages << "Failed to read all symbols.\n";
-			return false;
-		}
-
-		off_t oldpos = file.tellg();
-		file.seekg(0, std::ios_base::end);
-		size_t strings_len = (off_t)file.tellg() - oldpos;
-		file.seekg(oldpos, std::ios_base::beg);
-
-		messages.flags(std::ios::dec);
-		messages << "strings: " << strings_len << " bytes at 0x";
-		messages.flags(std::ios::hex);
-		messages << file.tellg() << "\n";
-
-		vector<char> symbolStrings;
-		// Note: len + 1 for a nul terminator, for safety.
-		symbolStrings.resize(strings_len + 1);
-		file.read(&symbolStrings[0], strings_len);
-		if ((size_t)file.gcount() != strings_len) {
-			messages << "Failed to read all strings.\n";
-			return false;
-		}
-
-		assert(sizeof(struct aout_symbol) == 12);
-
-		int nsymbols = 0;
-
-		struct aout_symbol* aout_symbol_ptr = (struct aout_symbol *) (void*) &symbolData[0];
-		int n_symbols = symbsize / sizeof(struct aout_symbol);
-		for (int i = 0; i < n_symbols; i++) {
-			uint32_t index = unencode32((unsigned char*)&aout_symbol_ptr[i].strindex, endianness);
-			uint32_t type  = unencode32((unsigned char*)&aout_symbol_ptr[i].type, endianness);
-			uint32_t addr  = unencode32((unsigned char*)&aout_symbol_ptr[i].addr, endianness);
-
-			// TODO: These bits probably mean different things for
-			// different a.out formats. For OpenBSD/m88k at least,
-			// this bit (0x01000000) seems to mean "a normal symbol".
-			if (!(type & 0x01000000))
-				continue;
-
-			// ... and the rectangle drawing demo says
-			// "_my_memset" at addr 1020, type 5020000
-			// "rectangles_m88k_O2.o" at addr 1020, type 1f000000
-			if ((type & 0x1f000000) == 0x1f000000)
-				continue;
-
-			if (index >= (uint32_t)strings_len) {
-				messages << "symbol " << i << " has invalid string index\n";
-				continue;
-			}
-
-			string symbol = ((char*) &symbolStrings[0]) + index;
-			if (symbol == "")
-				continue;
-
-			// messages << "\"" << symbol << "\" at addr " << addr
-			//   << ", type " << type << "\n";
-
-			// Add this symbol to the symbol registry:
-			symbolRegistry->AddSymbol(symbol, addr);
-			++ nsymbols;
-		}
-
-		messages.flags(std::ios::dec);
-		messages << nsymbols << " symbols read\n";
-	}
-
-	// Set the CPU's entry point.
-	stringstream ss;
-	ss << (int64_t)(int32_t)entry;
-	component->SetVariableValue("pc", ss.str());
-
-	return true;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_FileLoader_aout_Constructor()
-{
-	FileLoader_aout aoutLoader("test/FileLoader_A.OUT_M88K");
-}
-
-UNITTESTS(FileLoader_aout)
-{
-	UNITTEST(Test_FileLoader_aout_Constructor);
-
-	// TODO
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/fileloaders/FileLoader_bout.cc gxemul-0.7.0+dfsg/src/main/fileloaders/FileLoader_bout.cc
--- gxemul-0.6.2/src/main/fileloaders/FileLoader_bout.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/fileloaders/FileLoader_bout.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,326 +0,0 @@
-/*
- *  Copyright (C) 2009-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <string.h>
-#include <fstream>
-#include <iomanip>
-
-using std::setw;
-using std::setfill;
-using std::ifstream;
-
-#include "AddressDataBus.h"
-#include "components/CPUComponent.h"
-#include "FileLoader_bout.h"
-
-#include "thirdparty/exec_bout.h"
-
-
-FileLoader_bout::FileLoader_bout(const string& filename)
-	: FileLoaderImpl(filename)
-{
-}
-
-
-string FileLoader_bout::DetectFileType(unsigned char *buf, size_t buflen, float& matchness) const
-{
-	matchness = 0.9;
-
-	if (buflen >= 0x2c && buf[0] == 0x0d && buf[1] == 0x01 && buf[2] == 0x00 && buf[3] == 0x00) {
-		return "b.out_i960_little";
-	}
-
-	if (buflen >= 0x2c && buf[0] == 0x00 && buf[1] == 0x00 && buf[2] == 0x01 && buf[3] == 0x0d) {
-		return "b.out_i960_big";
-	}
-
-	matchness = 0.0;
-	return "";
-}
-
-
-static uint32_t unencode32(uint8_t *p, Endianness endianness)
-{
-	uint32_t res;
-	
-	if (endianness == BigEndian)
-		res = p[3] + (p[2] << 8) + (p[1] << 16) + (p[0] << 24);
-	else
-		res = p[0] + (p[1] << 8) + (p[2] << 16) + (p[3] << 24);
-
-	return res;
-}
-
-
-bool FileLoader_bout::LoadIntoComponent(refcount_ptr<Component> component, ostream& messages) const
-{
-	AddressDataBus* bus = component->AsAddressDataBus();
-	if (bus == NULL) {
-		messages << "Target is not an AddressDataBus.\n";
-		return false;
-	}
-
-	ifstream file(Filename().c_str());
-	if (!file.is_open()) {
-		messages << "Unable to read file.\n";
-		return false;
-	}
-
-	unsigned char buf[65536];
-
-	memset(buf, 0, sizeof(buf));
-	file.seekg(0, std::ios_base::end);
-	uint64_t totalSize = file.tellg();
-	file.seekg(0, std::ios_base::beg);
-	file.read((char *)buf, totalSize < sizeof(buf)? totalSize : sizeof(buf));
-	size_t amountRead = file.gcount();
-
-	float matchness;
-	string format = DetectFileType(buf, amountRead, matchness);
-
-	if (format == "") {
-		messages << "Unknown b.out format.\n";
-		return false;
-	}
-
-	file.seekg(0, std::ios_base::beg);
-
-	StateVariable* var = component->GetVariable("bigendian");
-	if (var == NULL) {
-		messages << "Target does not have the 'bigendian' variable,"
-		    " which is needed to\n"
-		    "load b.out files.\n";
-		return false;
-	}
-
-	Endianness endianness = LittleEndian;
-	if (format == "b.out_i960_big")
-		endianness = BigEndian;
-
-	struct bout_exec header;
-	uint32_t entry;
-
-	file.read((char *)&header, sizeof(header));
-	if (file.gcount() != sizeof(header)) {
-		messages << "The file is too small to be a b.out.\n";
-		return false;
-	}
-
-	entry = unencode32((unsigned char*)&header.a_entry, endianness);
-
-	uint32_t textaddr = unencode32((unsigned char*)&header.a_tload, endianness);
-	uint32_t textsize = unencode32((unsigned char*)&header.a_text, endianness);
-
-	uint32_t dataaddr = unencode32((unsigned char*)&header.a_dload, endianness);
-	uint32_t datasize = unencode32((unsigned char*)&header.a_data, endianness);
-
-	// int32_t symbsize = unencode32((unsigned char*)&header.a_syms, endianness);
-
-	messages.flags(std::ios::hex);
-	messages << "b.out: entry point 0x";
-	messages << setw(8) << setfill('0') << (uint32_t) entry << "\n";
-
-	messages.flags(std::ios::dec);
-	messages << "text + data = " << textsize << " + " << datasize << " bytes\n";
-
-	// Load text:
-	uint32_t vaddr = textaddr;
-	while (textsize != 0) {
-		int len = textsize > sizeof(buf) ? sizeof(buf) : textsize;
-		file.read((char *)buf, len);
-		len = file.gcount();
-		if (len < 1)
-			break;
-
-		// Write to the bus, one byte at a time.
-		for (int k=0; k<len; ++k) {
-			bus->AddressSelect(vaddr);
-			if (!bus->WriteData(buf[k])) {
-				messages.flags(std::ios::hex);
-				messages << "Failed to write data to virtual "
-				    "address 0x" << vaddr << "\n";
-				return false;
-			}
-			
-			++ vaddr;
-		}
-
-		textsize -= len;
-	}
-
-	if (textsize != 0) {
-		messages << "Failed to read the entire file.\n";
-		return false;
-	}
-
-	// Load data:
-	vaddr = dataaddr;
-	while (datasize != 0) {
-		int len = datasize > sizeof(buf) ? sizeof(buf) : datasize;
-		file.read((char *)buf, len);
-		len = file.gcount();
-		if (len < 1)
-			break;
-
-		// Write to the bus, one byte at a time.
-		for (int k=0; k<len; ++k) {
-			bus->AddressSelect(vaddr);
-			if (!bus->WriteData(buf[k])) {
-				messages.flags(std::ios::hex);
-				messages << "Failed to write data to virtual "
-				    "address 0x" << vaddr << "\n";
-				return false;
-			}
-			
-			++ vaddr;
-		}
-
-		datasize -= len;
-	}
-
-	if (datasize != 0) {
-		messages << "Failed to read the entire file.\n";
-		return false;
-	}
-
-#if 0
-	// TODO: Symbols. Similar to a.out?
-
-	SymbolRegistry* symbolRegistry = NULL;
-	CPUComponent* cpu = component->AsCPUComponent();
-	if (cpu != NULL)
-		symbolRegistry = &cpu->GetSymbolRegistry();
-
-	// Symbols:
-	if (symbolRegistry != NULL && symbsize > 0) {
-		messages.flags(std::ios::dec);
-		messages << "symbols: " << symbsize << " bytes at 0x";
-		messages.flags(std::ios::hex);
-		messages << file.tellg() << "\n";
-
-		vector<char> symbolData;
-		symbolData.resize(symbsize);
-		file.read(&symbolData[0], symbsize);
-		if (file.gcount() != symbsize) {
-			messages << "Failed to read all symbols.\n";
-			return false;
-		}
-
-		off_t oldpos = file.tellg();
-		file.seekg(0, std::ios_base::end);
-		size_t strings_len = (off_t)file.tellg() - oldpos;
-		file.seekg(oldpos, std::ios_base::beg);
-
-		messages.flags(std::ios::dec);
-		messages << "strings: " << strings_len << " bytes at 0x";
-		messages.flags(std::ios::hex);
-		messages << file.tellg() << "\n";
-
-		vector<char> symbolStrings;
-		// Note: len + 1 for a nul terminator, for safety.
-		symbolStrings.resize(strings_len + 1);
-		file.read(&symbolStrings[0], strings_len);
-		if (file.gcount() != strings_len) {
-			messages << "Failed to read all strings.\n";
-			return false;
-		}
-
-		assert(sizeof(struct aout_symbol) == 12);
-
-		int nsymbols = 0;
-
-		struct aout_symbol* aout_symbol_ptr = (struct aout_symbol *) (void*) &symbolData[0];
-		int n_symbols = symbsize / sizeof(struct aout_symbol);
-		for (int i = 0; i < n_symbols; i++) {
-			uint32_t index = unencode32((unsigned char*)&aout_symbol_ptr[i].strindex, endianness);
-			uint32_t type  = unencode32((unsigned char*)&aout_symbol_ptr[i].type, endianness);
-			uint32_t addr  = unencode32((unsigned char*)&aout_symbol_ptr[i].addr, endianness);
-
-			// TODO: These bits probably mean different things for
-			// different b.out formats. For OpenBSD/m88k at least,
-			// this bit (0x01000000) seems to mean "a normal symbol".
-			if (!(type & 0x01000000))
-				continue;
-
-			// ... and the rectangle drawing demo says
-			// "_my_memset" at addr 1020, type 5020000
-			// "rectangles_m88k_O2.o" at addr 1020, type 1f000000
-			if ((type & 0x1f000000) == 0x1f000000)
-				continue;
-
-			if (index >= (uint32_t)strings_len) {
-				messages << "symbol " << i << " has invalid string index\n";
-				continue;
-			}
-
-			string symbol = ((char*) &symbolStrings[0]) + index;
-			if (symbol == "")
-				continue;
-
-			// messages << "\"" << symbol << "\" at addr " << addr
-			//   << ", type " << type << "\n";
-
-			// Add this symbol to the symbol registry:
-			symbolRegistry->AddSymbol(symbol, addr);
-			++ nsymbols;
-		}
-
-		messages.flags(std::ios::dec);
-		messages << nsymbols << " symbols read\n";
-	}
-#endif
-
-	// Set the CPU's entry point.
-	stringstream ss;
-	ss << (int64_t)(int32_t)entry;
-	component->SetVariableValue("pc", ss.str());
-
-	return true;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_FileLoader_bout_Constructor()
-{
-	FileLoader_bout boutLoader("test/FileLoader_B.OUT_i960");
-}
-
-UNITTESTS(FileLoader_bout)
-{
-	UNITTEST(Test_FileLoader_bout_Constructor);
-
-	// TODO
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/fileloaders/FileLoader_ELF.cc gxemul-0.7.0+dfsg/src/main/fileloaders/FileLoader_ELF.cc
--- gxemul-0.6.2/src/main/fileloaders/FileLoader_ELF.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/fileloaders/FileLoader_ELF.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,618 +0,0 @@
-/*
- *  Copyright (C) 2008-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <string.h>
-#include <fstream>
-#include <iomanip>
-
-using std::setw;
-using std::setfill;
-using std::ifstream;
-
-#include "AddressDataBus.h"
-#include "components/CPUComponent.h"
-#include "FileLoader_ELF.h"
-
-#include "thirdparty/exec_elf.h"
-
-
-/*  ELF machine types as strings: (same as exec_elf.h)  */
-#define N_ELF_MACHINE_TYPES     244
-static const char *elf_machine_type[N_ELF_MACHINE_TYPES] = {
-        "NONE", "M32", "SPARC", "386",				/*  0..3  */
-        "68K", "88K", "486", "i860",				/*  4..7  */  
-        "MIPS", "S370", "MIPS_RS3_LE", "RS6000",		/*  8..11  */
-        "unknown12", "unknown13", "unknown14", "PARISC",	/*  12..15  */
-        "NCUBE", "VPP500", "SPARC32PLUS", "i960",		/*  16..19  */
-        "PPC", "PPC64", "unknown22", "unknown23",		/*  20..23  */
-        "unknown24", "unknown25", "unknown26", "unknown27",	/*  24..27  */
-        "unknown28", "unknown29", "unknown30", "unknown31",	/*  28..31  */
-        "unknown32", "unknown33", "unknown34", "unknown35",	/*  32..35  */
-        "V800", "FR20", "RH32", "RCE",				/*  36..39  */
-        "ARM", "ALPHA", "SH", "SPARCV9",			/*  40..43  */
-        "TRICORE", "ARC", "H8_300", "H8_300H",			/*  44..47  */
-        "H8S", "H8_500", "IA_64", "MIPS_X",			/*  48..51  */
-        "COLDFIRE", "68HC12", "Fujitsu MMA", "Siemens PCP",	/*  52..55  */
-        "nCPU", "NDR1", "STARCORE", "ME16",			/*  56..59  */
-        "ST100", "TINYJ", "AMD64", "PDSP",			/*  60..63  */
-        "PDP10", "PDP11", "FX66", "ST9PLUS",			/*  64..67  */
-        "ST7", "68HC16", "68HC11", "68HC08",			/*  68..71  */
-        "68HC05", "SVX", "ST19", "VAX",				/*  72..75  */
-        "CRIS", "JAVELIN", "FIREPATH", "ZSP",			/*  76..79  */
-        "MMIX", "HUANY", "PRISM", "AVR",			/*  80..83  */
-        "FR30", "D10V", "D30V", "V850",				/*  84..87  */
-        "M32R", "MN10300", "MN10200", "picoJava",		/*  88..91  */
-        "OR1K", "ARC_A5", "Xtensa", "Alphamosaic VideoCore",	/*  92..95  */
-        "TMM_GPP", "NS32K", "TPC", "SNP1K",			/*  96..99  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  100..103  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  104..107  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  108..111  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  112..115  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  116..119  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  120..123  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  124..127  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  128..131  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  132..135  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  136..139  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  140..143  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  144..147  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  148..151  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  152..155  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  156..159  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  160..163  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  164..167  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  168..171  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  172..175  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  176..179  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  180..183  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "TILE64",	/*  184..187  */
-        "TILEPro", "MicroBlaze", "unknown1xx", "unknown1xx",	/*  188..191  */
-        "TILE-GX", "unknown1xx", "unknown1xx", "unknown1xx",	/*  192..195  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  196..199  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  200..203  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  204..207  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  208..211  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  212..215  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  216..219  */
-        "Zilog Z80", "unknown1xx", "unknown1xx", "unknown1xx",	/*  220..223  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  224..227  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  228..231  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  232..235  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "unknown1xx",	/*  236..239  */
-        "unknown1xx", "unknown1xx", "unknown1xx", "RISC-V",	/*  240..243  */
-};
-
-
-FileLoader_ELF::FileLoader_ELF(const string& filename)
-	: FileLoaderImpl(filename)
-{
-}
-
-
-string FileLoader_ELF::DetectFileType(unsigned char *buf, size_t buflen, float& matchness) const
-{
-	if (buflen < sizeof(Elf32_Ehdr))
-		return "";
-
-	// Note: The e_ident part of the 32-bit and the 64-bit variants have
-	// the same layout, so it is safe to only check the 32-bit variant here.
-	Elf32_Ehdr* elf32_ehdr = (Elf32_Ehdr*) buf;
-	if (elf32_ehdr->e_ident[EI_MAG0] == ELFMAG0 &&
-	    elf32_ehdr->e_ident[EI_MAG1] == ELFMAG1 &&
-	    elf32_ehdr->e_ident[EI_MAG2] == ELFMAG2 &&
-	    elf32_ehdr->e_ident[EI_MAG3] == ELFMAG3) {
-		// We are here if this is either an ELF32 or ELF64.
-		int elfClass = elf32_ehdr->e_ident[EI_CLASS];
-
-		matchness = 1.0;
-		if (elfClass == ELFCLASS32)
-			return "ELF32";
-		if (elfClass == ELFCLASS64)
-			return "ELF64";
-
-		matchness = 0.0;
-		stringstream ss;
-		ss << "ELF Unknown class " << elfClass;
-		return ss.str();
-	}
-
-	return "";
-}
-
-
-bool FileLoader_ELF::LoadIntoComponent(refcount_ptr<Component> component, ostream& messages) const
-{
-	AddressDataBus* bus = component->AsAddressDataBus();
-	if (bus == NULL) {
-		messages << "Target is not an AddressDataBus.\n";
-		return false;
-	}
-
-	ifstream file(Filename().c_str());
-	if (!file.is_open()) {
-		messages << "Unable to read file.\n";
-		return false;
-	}
-
-	char buf[64];
-
-	// buf must be large enough for the largest possible header we wish
-	// to examine to fit.
-	assert(sizeof(buf) >= sizeof(Elf32_Ehdr));
-	assert(sizeof(buf) >= sizeof(Elf64_Ehdr));
-
-	memset(buf, 0, sizeof(buf));
-	file.read(buf, sizeof(buf));
-
-	// Note: The e_ident part of the 32-bit and the 64-bit variants have
-	// the same layout, so it is safe to only use the 32-bit variant here.
-	Elf32_Ehdr* ehdr32 = (Elf32_Ehdr*) buf;
-	Elf64_Ehdr* ehdr64 = (Elf64_Ehdr*) buf;
-	if (ehdr32->e_ident[EI_MAG0] != ELFMAG0 ||
-	    ehdr32->e_ident[EI_MAG1] != ELFMAG1 ||
-	    ehdr32->e_ident[EI_MAG2] != ELFMAG2 ||
-	    ehdr32->e_ident[EI_MAG3] != ELFMAG3) {
-		messages << "Not an ELF.\n";
-		return false;
-	}
-
-	int elfClass = ehdr32->e_ident[EI_CLASS];
-	int elfDataEncoding = ehdr32->e_ident[EI_DATA];
-	int elfVersion = ehdr32->e_ident[EI_VERSION];
-
-	if (elfClass != ELFCLASS32 && elfClass != ELFCLASS64) {
-		messages << "Unknown ELF class.\n";
-		return false;
-	}
-	if (elfDataEncoding != ELFDATA2LSB && elfDataEncoding != ELFDATA2MSB) {
-		messages << "Unknown ELF data encoding.\n";
-		return false;
-	}
-	if (elfVersion != EV_CURRENT) {
-		messages << "Unknown ELF version.\n";
-		return false;
-	}
-
-	bool elf32 = elfClass == ELFCLASS32;
-
-#define ELF_HEADER_VAR(hdr32,hdr64,type,name) type name = elf32? hdr32->name  \
-							       : hdr64->name; \
-	if (elfDataEncoding == ELFDATA2LSB) {				      \
-		int size = elf32? sizeof(hdr32->name) : sizeof(hdr64->name);  \
-		switch (size) {						      \
-		case 2:	name = LE16_TO_HOST(name); break;		      \
-		case 4:	name = LE32_TO_HOST(name); break;		      \
-		case 8:	name = LE64_TO_HOST(name); break;		      \
-		}							      \
-	} else {							      \
-		int size = elf32? sizeof(hdr32->name) : sizeof(hdr64->name);  \
-		switch (size) {						      \
-		case 2:	name = BE16_TO_HOST(name); break;		      \
-		case 4:	name = BE32_TO_HOST(name); break;		      \
-		case 8:	name = BE64_TO_HOST(name); break;		      \
-		}							      \
-	}
-
-	ELF_HEADER_VAR(ehdr32, ehdr64, uint64_t, e_type);
-
-	if (e_type != ET_EXEC) {
-		messages << "ELF file is not an Executable.\n";
-		return false;
-	}
-
-	ELF_HEADER_VAR(ehdr32, ehdr64, uint64_t, e_entry);
-	ELF_HEADER_VAR(ehdr32, ehdr64, uint64_t, e_machine);
-
-	ELF_HEADER_VAR(ehdr32, ehdr64, uint64_t, e_phoff);
-	ELF_HEADER_VAR(ehdr32, ehdr64, uint64_t, e_phentsize);
-	ELF_HEADER_VAR(ehdr32, ehdr64, uint64_t, e_phnum);
-
-	ELF_HEADER_VAR(ehdr32, ehdr64, uint64_t, e_shoff);
-	ELF_HEADER_VAR(ehdr32, ehdr64, uint64_t, e_shentsize);
-	ELF_HEADER_VAR(ehdr32, ehdr64, uint64_t, e_shnum);
-
-	size_t expectedPhentSize = (elf32? sizeof(Elf32_Phdr) : sizeof(Elf64_Phdr));
-	if (e_phentsize != expectedPhentSize) {
-		messages << "Incorrect ELF phentsize? " << e_phentsize << ", should "
-		    "be " << expectedPhentSize << "\n"
-		    "Perhaps this is a dynamically linked "
-		    "binary (which isn't supported yet).\n";
-		return false;
-	}
-
-	size_t expectedShentSize = (elf32? sizeof(Elf32_Shdr) : sizeof(Elf64_Shdr));
-	if (e_shentsize != expectedShentSize) {
-		messages << "Incorrect ELF shentsize? " << e_shentsize << ", should "
-		    "be " << expectedShentSize << "\n"
-		    "Perhaps this is a dynamically linked "
-		    "binary (which isn't supported yet).\n";
-		return false;
-	}
-
-	if (e_machine < N_ELF_MACHINE_TYPES)
-		messages << elf_machine_type[e_machine];
-	else
-		messages << "machine type '" << e_machine << "'";
-	messages << " ELF" << (elf32? 32 : 64) << " ";
-
-	messages << (elfDataEncoding == ELFDATA2LSB? "LSB (LE)" : "MSB (BE)") << ": ";
-
-	if (!elf32 && (e_machine == EM_PPC || e_machine == EM_PPC64))
-		messages << "PPC function descriptor at";
-	else
-		messages << "entry point";
-
-	messages << " 0x";
-	messages.flags(std::ios::hex);
-
-	// Special case for MIPS: 32-bit addresses are sign-extended.
-	if (e_machine == EM_MIPS && elf32)
-		e_entry = (int32_t) e_entry;
-
-	uint64_t display_entry_point = e_entry;
-
-	// MIPS16 encoding (16-bit words) is indicated by the lowest bit of the PC.
-	bool mips16 = false;
-	if (e_machine == EM_MIPS && (e_entry & 1)) {
-		display_entry_point &= ~1;
-		mips16 = true;
-	}
-
-	// SHmedia (SH64) 32-bit encoding is indicated by the lowest bit of the PC.
-	bool shmedia = false;
-	if (e_machine == EM_SH && (e_entry & 1)) {
-		display_entry_point &= ~1;
-		shmedia = true;
-	}
-
-	if (elf32)
-		messages << setw(8) << setfill('0') << (uint32_t) display_entry_point;
-	else
-		messages << setw(16) << setfill('0') << (uint64_t) display_entry_point;
-
-	if (mips16)
-		messages << " (MIPS16 encoding)";
-
-	if (shmedia)
-		messages << " (SHmedia encoding)";
-
-	messages << "\n";
-
-	// PROGRAM HEADERS
-	size_t i;
-	for (i=0; i<e_phnum; ++i) {
-		// Load Phdr number i:
-		file.seekg(e_phoff + i * e_phentsize, std::ios::beg);
-
-		char phdr_buf[64];
-		assert(sizeof(phdr_buf) >= sizeof(Elf32_Phdr));
-		assert(sizeof(phdr_buf) >= sizeof(Elf64_Phdr));
-		Elf32_Phdr* phdr32 = (Elf32_Phdr*) phdr_buf;
-		Elf64_Phdr* phdr64 = (Elf64_Phdr*) phdr_buf;
-
-		memset(phdr_buf, 0, sizeof(phdr_buf));
-
-		int toRead = elf32? sizeof(Elf32_Phdr) : sizeof(Elf64_Phdr);
-		file.read(phdr_buf, toRead);
-		if (file.gcount() != toRead) {
-			messages << "Unable to read Phdr.\n";
-			return false;
-		}
-		
-		ELF_HEADER_VAR(phdr32, phdr64, uint64_t, p_type);
-		ELF_HEADER_VAR(phdr32, phdr64, uint64_t, p_offset);
-		ELF_HEADER_VAR(phdr32, phdr64, uint64_t, p_vaddr);
-		ELF_HEADER_VAR(phdr32, phdr64, uint64_t, p_filesz);
-		ELF_HEADER_VAR(phdr32, phdr64, uint64_t, p_memsz);
-
-		// Skip non-loadable program segments:		
-		if (p_type != PT_LOAD)
-			continue;
-
-		if (p_memsz < p_filesz) {
-			messages << "memsz < filesz. TODO: how"
-			    " to handle this? memsz = " << p_memsz <<
-			    ", filesz = " << p_filesz << "\n";
-			return false;
-		}
-
-		// Special case for MIPS: 32-bit addresses are sign-extended.
-		if (e_machine == EM_MIPS && elf32)
-			p_vaddr = (int32_t) p_vaddr;
-
-		messages.flags(std::ios::hex);
-		messages << "loadable chunk: vaddr 0x";
-
-		if (elf32)
-			messages << setw(8) << setfill('0') << (uint32_t) p_vaddr;
-		else
-			messages << setw(16) << setfill('0') << (uint64_t) p_vaddr;
-
-		messages.flags(std::ios::dec);
-		messages << ", " << p_filesz << " bytes\n";
-
-		file.seekg(p_offset, std::ios::beg);
-		char databuf[65536];
-		uint64_t bytesRead = 0;
-		uint64_t vaddrToWriteTo = p_vaddr;
-
-		while (bytesRead < p_filesz) {
-			int sizeToRead = sizeof(databuf);
-			if (sizeToRead + bytesRead > p_filesz)
-				sizeToRead = p_filesz - bytesRead;
-
-			assert(sizeToRead != 0);
-			memset(databuf, 0, sizeToRead);
-
-			file.read(databuf, sizeToRead);
-			int bytesReadThisTime = file.gcount();
-			bytesRead += bytesReadThisTime;
-
-			// Write to the bus, one byte at a time.
-			for (int k=0; k<bytesReadThisTime; ++k) {
-				bus->AddressSelect(vaddrToWriteTo);
-				if (!bus->WriteData(databuf[k])) {
-					messages.flags(std::ios::hex);
-					messages << "Failed to write data to "
-					    "virtual address 0x"
-					    << vaddrToWriteTo << "\n";
-					return false;
-				}
-
-				++ vaddrToWriteTo;
-			}
-		}
-	}
-
-	// SECTION HEADERS
-	vector<char> symtab;
-	vector<char> symstrings;
-	for (i=0; i<e_shnum; ++i) {
-		// Load Shdr number i:
-		file.seekg(e_shoff + i * e_shentsize, std::ios::beg);
-
-		char shdr_buf[64];
-		assert(sizeof(shdr_buf) >= sizeof(Elf32_Shdr));
-		assert(sizeof(shdr_buf) >= sizeof(Elf64_Shdr));
-		Elf32_Shdr* shdr32 = (Elf32_Shdr*) shdr_buf;
-		Elf64_Shdr* shdr64 = (Elf64_Shdr*) shdr_buf;
-
-		memset(shdr_buf, 0, sizeof(shdr_buf));
-		
-		int toRead = elf32? sizeof(Elf32_Shdr) : sizeof(Elf64_Shdr);
-		file.read(shdr_buf, toRead);
-		if (file.gcount() != toRead) {
-			messages << "Unable to read Shdr.\n";
-			return false;
-		}
-
-		ELF_HEADER_VAR(shdr32, shdr64, uint64_t, sh_name);
-		ELF_HEADER_VAR(shdr32, shdr64, uint64_t, sh_type);
-		ELF_HEADER_VAR(shdr32, shdr64, uint64_t, sh_flags);
-		ELF_HEADER_VAR(shdr32, shdr64, uint64_t, sh_addr);
-		ELF_HEADER_VAR(shdr32, shdr64, uint64_t, sh_offset);
-		ELF_HEADER_VAR(shdr32, shdr64, uint64_t, sh_size);
-		ELF_HEADER_VAR(shdr32, shdr64, uint64_t, sh_link);
-		ELF_HEADER_VAR(shdr32, shdr64, uint64_t, sh_info);
-		ELF_HEADER_VAR(shdr32, shdr64, uint64_t, sh_addralign);
-		ELF_HEADER_VAR(shdr32, shdr64, uint64_t, sh_entsize);
-
-		if (sh_type == SHT_SYMTAB) {
-			if (symtab.size() > 0) {
-				messages << "symtab: another symtab already loaded? TODO\n";
-				return false;
-			}
-			
-			int entrySize = elf32? sizeof(Elf32_Sym) : sizeof(Elf64_Sym);
-			int nEntries = sh_size / entrySize;
-			
-			messages.flags(std::ios::dec);
-			messages << "symtab: " << nEntries << " symbols at 0x";
-			messages.flags(std::ios::hex);
-			messages << sh_offset << "\n";
-			
-			symtab.resize(sh_size);
-			file.seekg(sh_offset, std::ios::beg);
-			file.read(&symtab[0], sh_size);
-			if ((uint64_t) file.gcount() != sh_size) {
-				messages << "Failed to read all " << sh_size << " symbol bytes.\n";
-				return false;
-			}
-		}
-		
-		// TODO/HACK: Figure out which strtab to use. For now, simply
-		// use the largest one!
-		if (sh_type == SHT_STRTAB && sh_size > symstrings.size()) {
-			messages.flags(std::ios::dec);
-			messages << "strtab: " << sh_size << " bytes at 0x";
-			messages.flags(std::ios::hex);
-			messages << sh_offset << "\n";
-
-			symstrings.resize(sh_size);
-			file.seekg(sh_offset, std::ios::beg);
-			file.read(&symstrings[0], sh_size);
-			if ((uint64_t) file.gcount() != sh_size) {
-				messages << "Failed to read all " << sh_size << " symbol string bytes.\n";
-				return false;
-			}
-		}
-	}
-
-	SymbolRegistry* symbolRegistry = NULL;
-	CPUComponent* cpu = component->AsCPUComponent();
-	if (cpu != NULL)
-		symbolRegistry = &cpu->GetSymbolRegistry();
-
-	// Symbols
-	if (symbolRegistry != NULL && symtab.size() > 0 && symstrings.size() > 0) {
-		int entrySize = elf32? sizeof(Elf32_Sym) : sizeof(Elf64_Sym);
-		int nEntries = symtab.size() / entrySize;
-
-		// For safety:
-		symstrings.resize(symstrings.size() + 1);
-		symstrings[symstrings.size() - 1] = '\0';
-
-		int nsymbols = 0;
-		
-		messages.flags(std::ios::hex);
-
-		for (int j=0; j<nEntries; j++) {
-			size_t p = j * entrySize;
-			Elf32_Sym* sym32 = (Elf32_Sym*) &symtab[p];
-			Elf64_Sym* sym64 = (Elf64_Sym*) &symtab[p];
-
-			ELF_HEADER_VAR(sym32, sym64, uint64_t, st_name);
-			ELF_HEADER_VAR(sym32, sym64, uint64_t, st_info);
-			ELF_HEADER_VAR(sym32, sym64, uint64_t, st_value);
-			ELF_HEADER_VAR(sym32, sym64, uint64_t, st_size);
-
-			// TODO: Is this needed?
-			//int bind = elf32? ELF32_ST_BIND(st_info) : ELF64_ST_BIND(st_info);
-			//if (bind == STB_LOCAL)
-			//	continue;
-
-			if (st_size == 0)
-				st_size ++;
-
-			if (st_name >= symstrings.size() - 1) {
-				messages << "symbol pointer mismatch?\n";
-				continue;
-			}
-
-			string symbol = &symstrings[st_name];
-
-			// Special case for MIPS: 32-bit addresses are sign-extended.
-			if (e_machine == EM_MIPS && elf32)
-				st_value = (int32_t) st_value;
-
-			// Special case for MIPS: _gp symbol initiates the GP register.
-			if (e_machine == EM_MIPS && symbol == "_gp") {
-				messages << "found _gp address: 0x";
-				if (elf32)
-					messages << setw(8) << setfill('0') << (uint32_t) st_value << "\n";
-				else
-					messages << setw(16) << setfill('0') << (uint64_t) st_value << "\n";
-
-				stringstream ss;
-				ss << st_value;
-				component->SetVariableValue("gp", ss.str());
-			}
-
-			// FOR DEBUGGING ONLY:
-			//messages << "symbol name '" << symbol << "', addr 0x" <<
-			//   st_value << ", size 0x" << st_size << "\n";
-
-			// Add this symbol to the symbol registry:
-			symbolRegistry->AddSymbol(symbol, st_value);
-			++ nsymbols;
-		}
-
-		messages.flags(std::ios::dec);
-		messages << nsymbols << " symbols read\n";
-	}
-
-	// Set the CPU's entry point.
-
-#if 0
-	if (elf64 && arch == ARCH_PPC) {
-		/*
-		 *  Special case for 64-bit PPC ELFs:
-		 *
-		 *  The ELF starting symbol points to a ".opd" section
-		 *  which contains a function descriptor:
-		 *
-		 *      uint64_t  start;
-		 *      uint64_t  toc_base;
-		 *      uint64_t  something_else;       (?)
-		 */
-		int res;
-		unsigned char b[sizeof(uint64_t)];
-		uint64_t toc_base;
-
-		debug("PPC64: ");
-
-		res = m->cpus[0]->memory_rw(m->cpus[0], mem, eentry, b,
-		    sizeof(b), MEM_READ, NO_EXCEPTIONS);
-		if (!res)
-			debug(" [WARNING: could not read memory?] ");
-
-		/*  PPC are always big-endian:  */
-		*entrypointp = ((uint64_t)b[0] << 56) +
-		    ((uint64_t)b[1] << 48) + ((uint64_t)b[2] << 40) +
-		    ((uint64_t)b[3] << 32) + ((uint64_t)b[4] << 24) +
-		    ((uint64_t)b[5] << 16) + ((uint64_t)b[6] << 8) +
-		    (uint64_t)b[7];
-
-		res = m->cpus[0]->memory_rw(m->cpus[0], mem, eentry + 8,
-		    b, sizeof(b), MEM_READ, NO_EXCEPTIONS);
-		if (!res)
-			fatal(" [WARNING: could not read memory?] ");
-
-		toc_base = ((uint64_t)b[0] << 56) +
-		    ((uint64_t)b[1] << 48) + ((uint64_t)b[2] << 40) +
-		    ((uint64_t)b[3] << 32) + ((uint64_t)b[4] << 24) +
-		    ((uint64_t)b[5] << 16) + ((uint64_t)b[6] << 8) +
-		    (uint64_t)b[7];
-
-		debug("entrypoint 0x%016"PRIx64", toc_base 0x%016"PRIx64"\n",
-		    (uint64_t) *entrypointp, (uint64_t) toc_base);
-		if (tocp != NULL)
-			*tocp = toc_base;
-	}
-#endif
-
-	stringstream ss;
-	ss << e_entry;
-	component->SetVariableValue("pc", ss.str());
-	component->SetVariableValue("bigendian",
-	    elfDataEncoding == ELFDATA2LSB? "false" : "true");
-
-	return true;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_FileLoader_ELF_Constructor()
-{
-	FileLoader_ELF elfLoader("test/FileLoader_ELF_MIPS");
-}
-
-UNITTESTS(FileLoader_ELF)
-{
-	UNITTEST(Test_FileLoader_ELF_Constructor);
-
-	// TODO
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/fileloaders/FileLoader_raw.cc gxemul-0.7.0+dfsg/src/main/fileloaders/FileLoader_raw.cc
--- gxemul-0.6.2/src/main/fileloaders/FileLoader_raw.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/fileloaders/FileLoader_raw.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,197 +0,0 @@
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <string.h>
-#include <fstream>
-#include <iomanip>
-
-using std::setw;
-using std::setfill;
-using std::ifstream;
-
-#include "AddressDataBus.h"
-#include "components/CPUComponent.h"
-#include "FileLoader_raw.h"
-#include "StringHelper.h"
-
-
-FileLoader_raw::FileLoader_raw(const string& filename)
-	: FileLoaderImpl(filename)
-{
-}
-
-
-string FileLoader_raw::DetectFileType(unsigned char *buf, size_t buflen, float& matchness) const
-{
-	matchness = 0.0;
-
-	vector<string> parts = StringHelper::SplitStringIntoVector(Filename(), ':');
-
-	// Possible variants:
-	//
-	// filename			<-- NOT a raw file
-	// raw:vaddr:filename
-	// raw:vaddr:skiplen:filename
-	// raw:vaddr:skiplen:initialpc:filename  e.g. raw:0xbfc00000:0x100:0xbfc00884:rom.bin
-	if (parts.size() < 3)
-		return "";
-
-	if (parts[0] != "raw")
-		return "";
-
-	matchness = 1.0;
-	return "raw";
-}
-
-
-bool FileLoader_raw::LoadIntoComponent(refcount_ptr<Component> component, ostream& messages) const
-{
-	AddressDataBus* bus = component->AsAddressDataBus();
-	if (bus == NULL) {
-		messages << "Target is not an AddressDataBus.\n";
-		return false;
-	}
-
-	// Possible variants:
-	//
-	// raw:vaddr:filename
-	// raw:vaddr:skiplen:filename
-	// raw:vaddr:skiplen:initialpc:filename  e.g. 0xbfc00000:0x100:0xbfc00884:rom.bin
-	vector<string> parts = StringHelper::SplitStringIntoVector(Filename(), ':');
-	if (parts.size() < 3 || parts.size() > 5) {
-		messages << "Syntax is raw:vaddr:[skiplen:[initialpc:]]filename.\n";
-		return false;
-	}
-
-	string strvaddr = parts[1];
-	string strskiplen = (parts.size() >= 4)? parts[2] : "";
-	string strinitialpc = (parts.size() >= 5)? parts[3] : "";
-	string fname = parts[parts.size() - 1];
-
-	bool error;
-	uint64_t vaddr = StringHelper::ParseNumber(strvaddr.c_str(), error);
-	if (error) {
-		messages << "could not parse vaddr.\n";
-		return false;
-	}
-
-	uint64_t skiplen = 0;
-	if (strskiplen != "") {
-		skiplen = StringHelper::ParseNumber(strskiplen.c_str(), error);
-		if (error) {
-			messages << "could not parse skiplen\n";
-			return false;
-		}
-	}
-
-	uint64_t initialpc = vaddr;
-	if (strinitialpc != "") {
-		initialpc = StringHelper::ParseNumber(strinitialpc.c_str(), error);
-		if (error) {
-			messages << "could not parse initialpc\n";
-			return false;
-		}
-	}
-
-	ifstream file(fname.c_str());
-	if (!file.is_open()) {
-		messages << "Unable to read file.\n";
-		return false;
-	}
-
-	file.seekg(0, std::ios_base::end);
-	off_t totalSize = file.tellg();
-	file.seekg(skiplen, std::ios_base::beg);
-	totalSize -= skiplen;
-
-	// Read everything:
-	vector<char> data;
-	data.resize(totalSize);
-	file.read(&data[0], totalSize);
-	if (file.gcount() != totalSize) {
-		messages << "failed to read the whole file\n";
-		return false;
-	}
-
-	messages.flags(std::ios::hex);
-	messages << "Raw file: entry point 0x" << initialpc << "\n";
-	messages << "loadable chunk";
-	if (skiplen != 0) {
-		messages.flags(std::ios::dec);
-		messages << " at offset " << skiplen;
-	}
-
-	messages.flags(std::ios::hex);
-	messages << ": vaddr 0x" << vaddr;
-
-	messages.flags(std::ios::dec);
-	messages << ", " << totalSize << " bytes\n";
-
-	// Write to the bus, one byte at a time.
-	for (size_t k=0; k<(size_t)totalSize; ++k) {
-		bus->AddressSelect(vaddr);
-		if (!bus->WriteData(data[k])) {
-			messages.flags(std::ios::hex);
-			messages << "Failed to write data to "
-			    "virtual address 0x" << vaddr << "\n";
-			return false;
-		}
-
-		++ vaddr;
-	}
-
-	// Set the CPU's entry point.
-	stringstream ss;
-	ss << initialpc;
-	component->SetVariableValue("pc", ss.str());
-
-	return true;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-#include "ComponentFactory.h"
-
-static void Test_FileLoader_raw_Constructor()
-{
-	// TODO: haha, better test.
-	FileLoader_raw rawLoader("test/FileLoader_A.OUT_M88K");
-}
-
-UNITTESTS(FileLoader_raw)
-{
-	UNITTEST(Test_FileLoader_raw_Constructor);
-
-	// TODO
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/fileloaders/Makefile.skel gxemul-0.7.0+dfsg/src/main/fileloaders/Makefile.skel
--- gxemul-0.6.2/src/main/fileloaders/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/fileloaders/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,19 +0,0 @@
-#
-#  Makefile for GXemul src/main/fileloaders
-#
-
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(CPEDANTIC) $(INCLUDE2)
-LIBS=$(OTHERLIBS)
-
-OBJS=FileLoader_aout.o FileLoader_bout.o FileLoader_ELF.o FileLoader_raw.o
-
-all: $(OBJS)
-
-$(OBJS): Makefile
-
-clean:
-	rm -f $(OBJS)
-
-clean_all: clean
-	rm -f Makefile
-
diff -Nru gxemul-0.6.2/src/main/GXemul.cc gxemul-0.7.0+dfsg/src/main/GXemul.cc
--- gxemul-0.6.2/src/main/GXemul.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/GXemul.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1159 +0,0 @@
-/*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  This file contains two things:
- *
- *	1. Doxygen documentation for the general design concepts of the
- *	   emulator. The mainpage documentation written here ends up on
- *	   the "main page" in the generated HTML documentation.
- *
- *	2. The GXemul class implementation.
- */
-
-
-/*! \mainpage Source code documentation
- *
- * \section intro_sec Introduction
- *
- * This is the automatically generated Doxygen documentation for %GXemul,
- * built from comments throughout the source code.
- *
- * See the <a href="../../index.html">main documentation</a> for more
- * information about this version of %GXemul.
- *
- * See GXemul's home page for more information about %GXemul in general:
- * <a href="http://gavare.se/gxemul/">http://gavare.se/gxemul/</a>
- *
- * <b>NOTE:</b> There is a huge portion of code in
- * %GXemul which is legacy code. The documentation you will find on this page
- * is only about the new framework, which is <b><i>still being developed</i></b>.
- *
- * The main program creates a GXemul instance, and does one of two things:
- * <ul>
- *	<li>Starts without any template %machine. (<tt>-V</tt>)
- *	<li>Starts with a template %machine, and a list of additional
- *		components and files
- *		to attempt to attach (usually kernel binary to boot in the
- *		emulated %machine).
- * </ul>
- *
- * After letting the %GXemul instance load the files (or, in the more general
- * case, attach the components), GXemul::Run() is called.
- * This is the main loop. It doesn't really do much, it simply calls the UI's
- * main loop, i.e. ConsoleUI::MainLoop().
- *
- * Most of the source code in %GXemul centers around a few core concepts.
- * An overview of these concepts are given below. Anyone who wishes to
- * delve into the source code should be familiar with them.
- *
- *
- * \section concepts_sec Core concepts
- *
- * See the end-user <a href="../../framework.html">description of the framework</a>
- * for information about how these concepts appear to the actual user. The
- * sections below describe how those concepts are implemented in the code.
- *
- * \subsection components_subsec Components
- *
- * The most important core concept in %GXemul is the Component. Examples of
- * components are processors, networks interface cards, video displays, RAM
- * %memory, busses, %interrupt controllers, and all other kinds of devices.
- *
- * Each component has a parent, so the full set of components in an emulation
- * are in fact a tree. A GXemul instance has one such tree. The root
- * component is a special RootComponent, which holds some basic state about
- * the emulation, such as the number of steps executed.
- * It also contains zero or more sub-components.
- *
- * <center><img src="../../model.png"></center>
- *
- * Starting from the root node, each component has a <i>path</i>, e.g.
- * <tt>root.machine1.mainbus0.ram0</tt> for the RAM component in machine1
- * in the example above.
- *
- * The state of each component is stored within that component. The state
- * consists of a number of variables (see StateVariable) such as strings,
- * integers, bools, and other more high-level types such as zero-filled %memory
- * arrays. Such %memory arrays are used e.g. by the RAMComponent to emulate
- * RAM, and can also be used to emulate video framebuffer %memory.
- *
- * Individual components are implemented in <tt>src/components/</tt>, with
- * header files in <tt>src/include/components/</tt>. The <tt>configure</tt>
- * script looks for the string <tt>COMPONENT(name)</tt> in the header files,
- * and automagically adds those to the list of components that will be
- * available at runtime. In addition, <tt>make documentation</tt> also builds
- * HTML pages with lists of available
- * <a href="../../components.html">components</a>, and as a special case,
- * a list of available
- * <a href="../../machines.html">template machines</a> (because they have
- * special meaning to the end-user).
- *
- * \subsection commandinterpreter_subsec Command interpreter
- *
- * A GXemul instance has a CommandInterpreter, which is the part that parses a
- * command line, figures out which Command is to be executed, and executes it.
- * The %CommandInterpreter can be given a complete command line as a string, or
- * it can be given one character (or keypress) at a time. In the later case,
- * the TAB key either completes the word currently being written, or writes
- * out a list of possible completions.
- *
- * The %CommandInterpreter, via the ConsoleUI, is the user interface as seen
- * by the user.
- *
- * \subsection unittest_subsec Unit tests
- *
- * Wherever it makes sense, unit tests should be written to make sure
- * that the code is correct, and stays correct. The UnitTest class contains
- * static helper functions for writing unit tests, such as UnitTest::Assert.
- * To add unit tests to a class, the class should be UnitTestable, and in
- * particular, it should implement UnitTestable::RunUnitTests by using the
- * UNITTESTS(className) macro. Individual test cases are then called, as
- * static non-member functions, using the UNITTEST(testname) macro.
- *
- * Since test cases are non-member functions, they need to create instances
- * of the class they wish to test, and they can only call public member
- * functions on those objects, not private ones. Thus, the unit tests only
- * test the "public API" of all classes. (If the internal API needs to be
- * tested, then a workaround can be to add a ConsistencyCheck member function
- * which is public, but mentioning in the documentation for that function
- * that it is only meant for internal use and debugging.)
- *
- * Unit tests are normally executed by <tt>make test</tt>. This is implicitly
- * done when doing <tt>make install</tt> as well.
- *
- * It is recommended to run the <tt>configure</tt> script with the
- * <tt>--debug</tt> option during development; among other things, this enables
- * use of <a href="http://wyw.dcweb.cn/">Wu Yongwei</a>'s new/debug %memory
- * leak detector (part of
- * <a href="http://sourceforge.net/projects/nvwa/">Stones of NVWA</a>).
- */
-
-
-/*****************************************************************************/
-
-#include "ConsoleUI.h"
-#include "NullUI.h"
-
-#include "GXemul.h"
-#include "components/RootComponent.h"
-#include "ComponentFactory.h"
-#include "UnitTest.h"
-
-#include <assert.h>
-#include <string.h>
-#include <unistd.h>
-#include <sys/time.h>
-#include <cmath>
-#include <fstream>
-#include <iostream>
-
-
-GXemul::GXemul()
-	: m_quietMode(false)
-	, m_ui(new NullUI(this))
-	, m_commandInterpreter(this)
-	, m_runState(Paused)
-	, m_interrupting(false)
-	, m_nrOfSingleStepsLeft(1)
-	, m_rootComponent(new RootComponent(this))
-	, m_snapshottingEnabled(false)
-{
-	gettimeofday(&m_lastOutputTime, NULL);
-	m_lastOutputStep = 0;
-
-	ClearEmulation();
-}
-
-
-void GXemul::ClearEmulation()
-{
-	if (GetRunState() == Running)
-		SetRunState(Paused);
-
-	m_rootComponent = new RootComponent(this);
-	m_emulationFileName = "";
-
-	GetUI()->UpdateUI();
-}
-
-
-bool GXemul::IsTemplateMachine(const string& templateName) const
-{
-	string nameWithoutArgs = templateName;
-	size_t p = nameWithoutArgs.find('(');
-	if (p > 0)
-		nameWithoutArgs = templateName.substr(0, p);
-
-	if (!ComponentFactory::HasAttribute(nameWithoutArgs, "template"))
-		return false;
-
-	if (!ComponentFactory::HasAttribute(nameWithoutArgs, "machine"))
-		return false;
-
-	return true;
-}
-
-
-bool GXemul::CreateEmulationFromTemplateMachine(const string& templateName)
-{
-	if (!IsTemplateMachine(templateName)) {
-		std::cerr << templateName << " is not a known template machine name.\n"
-		    "Use gxemul -H to get a list of valid machine templates.\n";
-		return false;
-	}
-
-	refcount_ptr<Component> machine =
-	    ComponentFactory::CreateComponent(templateName, this);
-	if (machine.IsNULL())
-		return false;
-
-	GetRootComponent()->AddChild(machine);
-	return true;
-}
-
-
-void GXemul::ListTemplates()
-{
-	std::cout << "Available template machines:\n\n";
-
-	vector<string> names = ComponentFactory::GetAllComponentNames(true);
-
-	size_t maxNameLen = 0;
-	for (size_t i=0; i<names.size(); ++i)
-		if (names[i].length() > maxNameLen)
-			maxNameLen = names[i].length();
-
-	for (size_t i=0; i<names.size(); ++i) {
-		string name = names[i];
-		
-		std::cout << "  " << name;
-		for (size_t j=0; j<maxNameLen - name.length() + 6; ++j)
-			std::cout << " ";
-
-		std::cout << ComponentFactory::GetAttribute(
-		    name, "description");
-		std::cout << "\n";
-	}
-
-	std::cout << "\n";
-}
-
-
-void GXemul::DumpMachineAsHTML(const string& machineName)
-{
-	refcount_ptr<Component> component =
-	    ComponentFactory::CreateComponent(machineName);
-
-	if (!component.IsNULL() &&
-	    component->GetChildren().size() != 0)
-		std::cout << "<pre>" <<
-		    component->GenerateTreeDump("", true, "../")
-		    << "</pre>";
-}
-
-
-void GXemul::GenerateHTMLListOfComponents(bool machines)
-{
-	std::cout <<
-		"Available " <<
-		(machines? "template machines" : "components") << ":\n"
-		"<p><table border=0>\n"
-		"<tr>\n"
-		" <td><b><u>" <<
-		(machines? "Machine&nbsp;name" : "Component&nbsp;name") << ":"
-		"</u></b>&nbsp;&nbsp;</td>\n";
-	if (machines)
-		std::cout << " <td><b><u>Screenshot:</u></b>&nbsp;&nbsp;</td>\n";
-	std::cout <<
-		" <td><b><u>Description:</u></b>&nbsp;&nbsp;</td>\n"
-		" <td><b><u>Comments:</u></b>&nbsp;&nbsp;</td>\n"
-		" <td><b><u>Contributors:</u></b>&nbsp;&nbsp;</td>\n"
-		"</tr>\n";
-
-	bool everyOther = false;
-	vector<string> names = ComponentFactory::GetAllComponentNames(false);
-	for (size_t i=0; i<names.size(); ++i) {
-		const string& componentName = names[i];
-		string treeDump;
-
-		refcount_ptr<Component> creatable =
-		    ComponentFactory::CreateComponent(componentName);
-		if (creatable.IsNULL())
-			continue;
-
-		bool isTemplateMachine = !ComponentFactory::GetAttribute(
-		    componentName, "machine").empty() &&
-		    !ComponentFactory::GetAttribute(
-		    componentName, "template").empty();
-
-		if (machines) {
-			if (!isTemplateMachine)
-				continue;
-		} else {
-			// Other components:  Don't include template machines.
-			if (isTemplateMachine)
-			    	continue;
-		}
-
-		// Include an ASCII tree dump for template components that
-		// have children:
-		if (!ComponentFactory::GetAttribute(
-		    componentName, "template").empty()) {
-			refcount_ptr<Component> component =
-			    ComponentFactory::CreateComponent(componentName);
-
-			if (!component.IsNULL() &&
-			    component->GetChildren().size() != 0)
-				treeDump = "<pre>" +
-				    component->GenerateTreeDump("", true)
-				    + "</pre>";
-		}
-
-		// Some distance between table entries:
-		std::cout <<
-			"<tr>\n"
-			" <td></td>"
-			"</tr>\n";
-
-		std::cout <<
-			"<tr bgcolor=" <<
-			(everyOther? "#f2f2f2" : "#e4e4e4") << ">\n";
-
-		// Include a href link to a "full html page" for a component,
-		// if it exists:
-		std::ifstream documentationComponentFile((
-		    "doc/components/component_"
-		    + componentName + ".html").c_str());
-		std::ifstream documentationMachineFile((
-		    "doc/machines/machine_"
-		    + componentName + ".html").c_str());
-
-		if (documentationComponentFile.is_open())
-			std::cout <<
-				" <td valign=top>"
-				"<a href=\"components/component_" <<
-				componentName
-				<< ".html\"><tt>" << componentName <<
-				"</tt></a></td>\n";
-		else if (documentationMachineFile.is_open())
-			std::cout <<
-				" <td valign=top>"
-				"<a href=\"machines/machine_" <<
-				componentName
-				<< ".html\"><tt>" << componentName <<
-				"</tt></a></td>\n";
-		else
-			std::cout <<
-				" <td valign=top><tt>" << componentName
-				<< "</tt></td>\n";
-
-		if (machines) {
-			// Include an img and a href link to a screenshot for a component,
-			// if it exists:
-			std::ifstream screenshotThumbFile((
-			    "doc/machines/machine_"
-			    + componentName + "-thumb.png").c_str());
-			std::ifstream screenshotLargeFile((
-			    "doc/machines/machine_"
-			    + componentName + ".png").c_str());
-
-			std::cout << " <td valign=top align=center><tt>";
-
-			if (screenshotLargeFile.is_open())
-				std::cout << "<a href=machines/machine_" <<
-				    componentName << ".png>";
-
-			if (screenshotThumbFile.is_open())
-				std::cout << "<img src=machines/machine_" <<
-				    componentName << "-thumb.png>";
-			else if (screenshotLargeFile.is_open())
-				std::cout << "(screenshot)";
-
-			if (screenshotLargeFile.is_open())
-				std::cout << "</a>";
-
-			std::cout << "</tt></td>\n";
-		}
-
-		std::cout <<
-			" <td valign=top>" << ComponentFactory::GetAttribute(
-				componentName, "description") <<
-				treeDump << "</td>\n"
-			" <td valign=top>" << ComponentFactory::GetAttribute(
-				componentName, "comments") << "</td>\n"
-			" <td valign=top>" << ComponentFactory::GetAttribute(
-				componentName, "contributors") << "</td>\n"
-			"</tr>\n";
-
-		everyOther = !everyOther;
-	}
-
-	std::cout << "</table><p>\n";
-}
-
-
-bool GXemul::ParseFilenames(string templateMachine, int filenameCount, char *filenames[])
-{
-	bool optionsEnoughToStartRunning = false;
-
-	if (templateMachine != "") {
-		if (CreateEmulationFromTemplateMachine(templateMachine)) {
-			// A template is now being used.
-		} else {
-			std::cerr << "Failed to create configuration from "
-			    "template: " << templateMachine << "\n" <<
-			    "Aborting." << "\n";
-			return false;
-		}
-	}
-
-	//  1. If a machine template has been selected, then treat the following
-	//     arguments as arguments to the 'add' command.
-	//
-	//  2. Otherwise, treat the argument as a configuration file.
-
-	if (filenameCount > 0) {
-		if (templateMachine != "") {
-			// Machine template.
-			while (filenameCount > 0) {
-				stringstream cmd;
-
-				// TODO: Different syntax!
-				// Use "add" with different syntax here...
-
-				cmd << "load " << filenames[0]
-				    << " root.machine0.mainbus0.cpu0";
-
-				// TODO: Get rid of this onReset mechanism!
-				m_onResetCommands.push_back(cmd.str());
-
-				filenameCount --;
-				filenames ++;
-			}
-
-			optionsEnoughToStartRunning = true;
-		} else {
-			// Config file.
-			if (filenameCount == 1) {
-				string configfileName = filenames[0];
-				optionsEnoughToStartRunning = true;
-
-				string cmd = "load " + configfileName;
-				m_onResetCommands.push_back(cmd);
-			} else {
-				std::cerr << "More than one configfile name "
-				    "supplied on the command line?" << "\n" <<
-				    "Aborting." << "\n";
-				return false;
-			}
-		}
-	}
-
-	if (optionsEnoughToStartRunning) {
-		return true;
-	} else {
-		if (templateMachine != "") {
-			if (GetRunState() == Paused)
-				return true;
-
-			std::cerr << 
-			    "No binary specified. Usually when starting up an emulation based on a template\n"
-			    "machine, you need to supply one or more binaries. This could be an operating\n"
-			    "system kernel, a ROM image, or something similar.\n"
-			    "\n"
-			    "You can also use the -V option to start in paused mode, and load binaries\n"
-			    "interactively.\n"
-			    "\n"
-			    "(Run  gxemul -h  for more help on command line options.)\n";
-			return false;
-		}
-		
-		PrintUsage();
-		return false;
-	}
-}
-
-
-string GXemul::Version()
-{
-	stringstream ss;
-	ss << "GXemul "
-#ifdef VERSION
-	    << VERSION
-#else
-	    << "(unknown version)"
-#endif
-	    << "      " COPYRIGHT_MSG"\n" SECONDARY_MSG;
-
-	return ss.str();
-}
-
-
-void GXemul::PrintUsage() const
-{
-	std::cout << Version() << "\n";
-
-	std::cout << "Insufficient command line arguments given to"
-	    " start an emulation. You have\n"
-	    "the following alternatives:\n" <<
-	    "\n" <<
-	    "  1. Run  gxemul  with the machine selection option "
-	    "(-e), which creates\n"
-	    "     a default emulation from a template machine.\n\n"
-	    "  2. Run  gxemul  with a configuration file (.gxemul).\n"
-	    "     This is useful for more complicated setups.\n\n"
-	    "  3. Run  gxemul -V  with no other options, which causes"
-	    " gxemul to be started\n"
-	    "     with no emulation loaded at all.\n\n" <<
-	    "\n" <<
-	    "Run  gxemul -h  for help on command line options.\n\n";
-}
-
-
-void GXemul::InitUI()
-{
-	// Default to the console UI:
-	m_ui = new ConsoleUI(this);
-
-	// Once a GUI has been implemented, this is the
-	// place to call its constructor. TODO
-
-	GetUI()->Initialize();
-}
-
-
-int GXemul::Run()
-{
-	// Not really running yet:
-	RunState savedRunState = GetRunState();
-	SetRunState(Paused);
-	
-	if (!GetQuietMode()) {
-		GetUI()->ShowStartupBanner();
-
-		// Dump (a suitable part of) the configuration tree at startup.
-		const Component* component = GetRootComponent();
-		if (component->GetChildren().size() > 0) {
-			while (true) {
-				int nChildren = component->GetChildren().size();
-				if (nChildren == 0 || nChildren > 1)
-					break;
-
-				component = component->GetChildren()[0];
-			}
-
-			GetUI()->ShowDebugMessage(component->GenerateTreeDump("") + "\n");
-		}
-	}
-
-	if (!Reset()) {
-		GetUI()->ShowDebugMessage("Aborting.\n");
-		return 1;
-	}
-
-	if (!GetQuietMode()) {
-		// A separator line, if we start emulating directly without dropping
-		// into the interactive debugger. (To mimic pre-0.6.0 appearance.)
-		if (savedRunState == Running)
-			GetUI()->ShowDebugMessage("--------------------------------"
-			    "-----------------------------------------------\n\n");
-	}
-
-	SetRunState(savedRunState);
-
-
-	try {
-		GetUI()->MainLoop();
-	} catch (std::exception& ex) {
-		stringstream ss;
-		ss << "\n### FATAL ERROR ###\n\n" << ex.what() << "\n\n" <<
-		    "If you are able to reproduce this crash, "
-		    "please send detailed repro-steps to\n"
-		    "the author, to the gxemul-devel mailing list, or"
-		    " ask in #GXemul on the\n"
-		    "FreeNode IRC network.\n";
-
-		GetUI()->FatalError(ss.str());
-
-		return 1;
-	}
-
-	return 0;
-}
-
-
-const string& GXemul::GetEmulationFilename() const
-{
-	return m_emulationFileName;
-}
-
-
-void GXemul::SetEmulationFilename(const string& filename)
-{
-	m_emulationFileName = filename;
-
-	GetUI()->UpdateUI();
-}
-
-
-CommandInterpreter& GXemul::GetCommandInterpreter()
-{
-	return m_commandInterpreter;
-}
-
-
-uint64_t GXemul::GetStep() const
-{
-	const StateVariable* step = GetRootComponent()->GetVariable("step");
-	if (step == NULL) {
-		std::cerr << "root component has no 'step' variable? aborting.\n";
-		throw std::exception();
-	}
-
-	return step->ToInteger();
-}
-
-
-void GXemul::SetStep(uint64_t step)
-{
-	StateVariable* stepVariable = GetRootComponent()->GetVariable("step");
-	if (stepVariable == NULL) {
-		std::cerr << "root component has no 'step' variable? aborting.\n";
-		throw std::exception();
-	}
-
-	stepVariable->SetValue(step);
-}
-
-
-UI* GXemul::GetUI()
-{
-	return m_ui;
-}
-
-
-refcount_ptr<Component> GXemul::GetRootComponent()
-{
-	return m_rootComponent;
-}
-
-
-const refcount_ptr<Component> GXemul::GetRootComponent() const
-{
-	return m_rootComponent;
-}
-
-
-void GXemul::SetRootComponent(refcount_ptr<Component> newRootComponent)
-{
-	if (newRootComponent.IsNULL()) {
-		std::cerr << "GXemul::SetRootComponent: NULL\n";
-		throw std::exception();
-	}
-
-	RootComponent* rootComponent = newRootComponent->AsRootComponent();
-	if (rootComponent == NULL) {
-		std::cerr << "GXemul::SetRootComponent: not a RootComponent\n";
-		throw std::exception();
-	}
-
-	rootComponent->SetOwner(this);
-
-	m_rootComponent = newRootComponent;
-
-	GetUI()->UpdateUI();
-}
-
-
-bool GXemul::Reset()
-{
-	// 1. Reset all components in the tree.
-	GetRootComponent()->Reset();
-
-	// 2. Run "on reset" commands. (These are usually commands to load
-	//    binaries into CPUs.)
-	vector<string>::const_iterator it = m_onResetCommands.begin();
-	for (; it != m_onResetCommands.end(); ++it) {
-		string cmd = *it;
-		bool success = false;
-
-		GetCommandInterpreter().RunCommand(cmd, &success);
-
-		if (!GetQuietMode())
-			GetUI()->ShowDebugMessage("\n");
-
-		if (!success) {
-			GetUI()->ShowDebugMessage("Failing on-reset command:\n"
-			    "    " + cmd + "\n");
-			return false;
-		}
-	}
-
-	return true;
-}
-
-
-void GXemul::Interrupt()
-{
-	switch (GetRunState()) {
-	case SingleStepping:
-	case Running:
-		m_interrupting = true;
-		break;
-	default:
-		m_interrupting = false;
-	}
-}
-
-
-void GXemul::SetRunState(RunState newState)
-{
-	m_runState = newState;
-
-	GetUI()->UpdateUI();
-}
-
-
-GXemul::RunState GXemul::GetRunState() const
-{
-	return m_runState;
-}
-
-
-string GXemul::GetRunStateAsString() const
-{
-	switch (m_runState) {
-	case Paused:
-		return "Paused";
-	case SingleStepping:
-		return "Single-stepping";
-	case Running:
-		return "Running";
-	case Quitting:
-		return "Quitting";
-	}
-
-	return "Unknown RunState";
-}
-
-
-bool GXemul::GetSnapshottingEnabled() const
-{
-	return m_snapshottingEnabled;
-}
-
-
-void GXemul::SetSnapshottingEnabled(bool enabled)
-{
-	if (enabled)
-		GetUI()->ShowDebugMessage("(Enabling "
-		    "snapshotting/reverse execution support.)\n");
-
-	m_snapshottingEnabled = enabled;
-}
-
-
-bool GXemul::GetQuietMode() const
-{
-	return m_quietMode;
-}
-
-
-void GXemul::SetQuietMode(bool quietMode)
-{
-	m_quietMode = quietMode;
-}
-
-
-void GXemul::SetNrOfSingleStepsInARow(uint64_t steps)
-{
-	if (steps < 1)
-		steps = 1;
-
-	m_nrOfSingleStepsLeft = steps;
-}
-
-
-bool GXemul::ModifyStep(int64_t oldStep, int64_t newStep)
-{
-	if (!GetSnapshottingEnabled())
-		return false;
-
-	if (oldStep == newStep)
-		return true;
-
-	if (newStep < oldStep) {
-		// Run in reverse, by running forward from the most suitable
-		// snapshot.
-
-		// TODO: Multiple snapshots!
-		refcount_ptr<Component> newRoot = m_snapshot->Clone();
-		SetRootComponent(newRoot);
-
-		// GetStep will now return the step count for the new root.
-		int64_t nrOfStepsToRunFromSnapshot = newStep - GetStep();
-
-		RunState oldRunState = GetRunState();
-		SetRunState(Running);
-
-		Execute(nrOfStepsToRunFromSnapshot);
-
-		SetRunState(oldRunState);
-	} else {
-		// Run forward, by setting a step breakpoint.
-		GetUI()->ShowDebugMessage("TODO: run forward by setting a step breakpoint!\n");
-		return false;
-	}
-
-	return true;
-}
-
-
-void GXemul::TakeSnapshot()
-{
-	// TODO: Multiple snapshots!
-
-	if (m_snapshot.IsNULL()) {
-		stringstream ss;
-		ss << "(snapshot at step " << GetStep() << ")\n";
-		GetUI()->ShowDebugMessage(ss.str());
-
-		m_snapshot = GetRootComponent()->Clone();
-	}
-}
-
-
-struct ComponentAndFrequency
-{
-	refcount_ptr<Component>	component;
-	double			frequency;
-	StateVariable*		step;
-
-	uint64_t		nextTimeToExecute;
-};
-
-
-// Gathers a list of components and their frequencies. (Only components that
-// have a variable named "frequency" are executable.)
-static void GetComponentsAndFrequencies(refcount_ptr<Component> component,
-	vector<ComponentAndFrequency>& componentsAndFrequencies)
-{
-	const StateVariable* paused = component->GetVariable("paused");
-	const StateVariable* freq = component->GetVariable("frequency");
-	StateVariable* step = component->GetVariable("step");
-	if (freq != NULL && step != NULL &&
-	    (paused == NULL || paused->ToInteger() == 0)) {
-		struct ComponentAndFrequency caf;
-
-		caf.component = component;
-		caf.frequency = freq->ToDouble();
-		caf.step      = step;
-		caf.nextTimeToExecute = 0;
-
-		componentsAndFrequencies.push_back(caf);
-	}
-	
-	Components children = component->GetChildren();
-	for (size_t i=0; i<children.size(); ++i)
-		GetComponentsAndFrequencies(children[i], componentsAndFrequencies);
-}
-
-
-void GXemul::Execute(const int longestTotalRun)
-{
-	vector<ComponentAndFrequency> componentsAndFrequencies;
-	GetComponentsAndFrequencies(GetRootComponent(), componentsAndFrequencies);
-
-	if (componentsAndFrequencies.size() == 0) {
-		GetUI()->ShowDebugMessage("No executable components"
-		    " found in the configuration.\n");
-		SetRunState(Paused);
-		return;
-	}
-
-	// Take an initial snapshot at step 0, if snapshotting is enabled:
-	if (m_snapshottingEnabled && GetStep() == 0)
-		TakeSnapshot();
-
-	// Find the fastest component:
-	double fastestFrequency = componentsAndFrequencies[0].frequency;
-	size_t fastestComponentIndex = 0;
-	for (size_t i=0; i<componentsAndFrequencies.size(); ++i)
-		if (componentsAndFrequencies[i].frequency > fastestFrequency) {
-			fastestFrequency = componentsAndFrequencies[i].frequency;
-			fastestComponentIndex = i;
-		}
-
-	bool printEmptyLineBetweenSteps = false;
-
-	switch (GetRunState()) {
-
-	case SingleStepping:
-		if (m_nrOfSingleStepsLeft == 0)
-			m_nrOfSingleStepsLeft = 1;
-
-		// Note that setting run state to something else, OR
-		// decreasing nr of single steps left to 0, will break the loop.
-		while (!m_interrupting && m_nrOfSingleStepsLeft > 0 && GetRunState() == SingleStepping) {
-			uint64_t step = GetStep();
-
-			if (printEmptyLineBetweenSteps)
-				GetUI()->ShowDebugMessage("\n");
-			else
-				printEmptyLineBetweenSteps = true;
-
-			stringstream ss;
-			ss << "step " << step << ": ";
-
-			// Indent all debug output with message header "step X: ":
-			UI::SetIndentationMessageHelper indentationHelper(GetUI(), ss.str());
-
-			++ step;
-
-			// Component X, using frequency fX, should have executed
-			// nstepsX = steps * fX / fastestFrequency  nr of steps.
-			for (size_t k=0; k<componentsAndFrequencies.size(); ++k) {
-				uint64_t nsteps = (k == fastestComponentIndex ? step
-				    : (uint64_t) (step * componentsAndFrequencies[k].frequency / fastestFrequency));
-
-				uint64_t stepsExecutedSoFar = componentsAndFrequencies[k].step->ToInteger();
-
-				if (stepsExecutedSoFar > nsteps) {
-					std::cerr << "Internal error: " <<
-					    componentsAndFrequencies[k].component->GetVariable("name")->ToString() <<
-					    " has executed " << stepsExecutedSoFar << " steps, goal is " << nsteps << ".\n";
-					throw std::exception();
-				}
-
-				if (stepsExecutedSoFar < nsteps) {
-					++ stepsExecutedSoFar;
-
-					const refcount_ptr<Component> lightClone =
-					    GetRootComponent()->LightClone();
-
-					// Execute one step...
-					int n = componentsAndFrequencies[k].component->Execute(this, 1);
-					if (n != 1) {
-						GetUI()->ShowDebugMessage("Single-stepping aborted.\n");
-						SetRunState(Paused);
-						return;
-					}
-					
-					// ... and write back the number of executed steps:
-					componentsAndFrequencies[k].step->SetValue(stepsExecutedSoFar);
-
-					// Now, let's compare the clone of the component tree
-					// before execution with what we have now.
-					stringstream changeMessages;
-					GetRootComponent()->DetectChanges(lightClone, changeMessages);
-					string msg = changeMessages.str();
-					if (msg.length() > 0)
-						GetUI()->ShowDebugMessage(msg);
-				}
-			}
-
-			SetStep(step);
-			-- m_nrOfSingleStepsLeft;
-		}
-
-		// Done. Let's pause again.
-		SetRunState(Paused);
-		m_nrOfSingleStepsLeft = 0;
-		break;
-
-	case Running:
-		{
-			uint64_t step = GetStep();
-			uint64_t startingStep = step;
-
-			// TODO: sloppy vs cycle accuracy.
-			if (GetRootComponent()->GetVariable("accuracy")->ToString() != "cycle") {
-				std::cerr << "GXemul::Execute(): TODO: Only "
-				    "root.accuracy=\"cycle\" is currently supported\n";
-				SetRunState(Paused);
-				return;
-			}
-
-			// The following code is for cycle accurate emulation:
-
-			while (step < startingStep + longestTotalRun) {
-				if (m_interrupting || GetRunState() != Running)
-					break;
-
-				int toExecute = -1;
-				
-				if (componentsAndFrequencies.size() == 1) {
-					toExecute = longestTotalRun;
-					componentsAndFrequencies[0].nextTimeToExecute = step;
-				} else {
-					// First, calculate the next time step when each
-					// component k will execute.
-					//
-					// For n = 0,1,2,3, ...
-					// n * fastestFrequency / componentsAndFrequencies[k].frequency
-					// are the steps at which the component executes
-					// (when rounded UP! i.e. executing at step 4.2 means that it
-					// did not execute at step 4, but will at step 5).
-				
-					for (size_t k=0; k<componentsAndFrequencies.size(); ++k) {
-						double q = (k == fastestComponentIndex ? 1.0
-						    : fastestFrequency / componentsAndFrequencies[k].frequency);
-
-						double c = (componentsAndFrequencies[k].step->ToInteger()+1) * q;
-						componentsAndFrequencies[k].nextTimeToExecute = (uint64_t) ceil(c) - 1;
-					}
-
-					// std::cerr << "step " << step << " debug:\n";
-					for (size_t k=0; k<componentsAndFrequencies.size(); ++k) {
-						// std::cerr << "  next step for component " <<
-						//    componentsAndFrequencies[k].component->GetVariable("name")->ToString()
-						//    << ": " << componentsAndFrequencies[k].nextTimeToExecute << "\n";
-
-						int diff = componentsAndFrequencies[k].nextTimeToExecute -
-						    componentsAndFrequencies[fastestComponentIndex].nextTimeToExecute;
-						if (k != fastestComponentIndex) {
-							if (toExecute == -1 || diff < toExecute)
-								toExecute = diff;
-						}
-					}
-
-					if (toExecute < 1)
-						toExecute = 1;
-				}
-
-				if (step + toExecute > startingStep + longestTotalRun)
-					toExecute = startingStep + longestTotalRun - step;
-
-				// std::cerr << "  toExecute = " << toExecute << "\n";
-
-				// Run the components.
-				// If multiple components are to run at the same time (i.e.
-				// same nextTimeToExecute), toExecute will be exactly 1.
-				int maxExecuted = 0;
-				bool abort = false;
-				for (size_t k=0; k<componentsAndFrequencies.size(); ++k) {
-					if (step != componentsAndFrequencies[k].nextTimeToExecute)
-						continue;
-
-					// Execute the calculated number of steps...
-					int n = componentsAndFrequencies[k].component->Execute(this, toExecute);
-
-					// ... and write back the number of executed steps:
-					uint64_t stepsExecutedSoFar = n +
-					    componentsAndFrequencies[k].step->ToInteger();
-					componentsAndFrequencies[k].step->SetValue(stepsExecutedSoFar);
-
-					if (k == fastestComponentIndex)
-						maxExecuted = n;
-
-					if (n != toExecute) {
-						abort = true;
-
-						if (n > toExecute) {
-							std::cerr << "Internal error: " << n <<
-							    " steps executed, toExecute = " << toExecute << "\n";
-							throw std::exception();
-						}
-
-						stringstream ss;
-						ss << "only " << n << " steps of " << toExecute << " executed.";
-						GetUI()->ShowDebugMessage(componentsAndFrequencies[k].component, ss.str());
-					}
-				}
-
-				if (abort) {
-					GetUI()->ShowDebugMessage("Continuous execution aborted.\n");
-					SetRunState(Paused);
-				}
-
-				if (maxExecuted == 0 && GetRunState() == Running) {
-					std::cerr << "maxExecuted=0. internal error\n";
-					throw std::exception();
-				}
-
-				step += maxExecuted;
-				SetStep(step);
-			}
-
-			// Output nr of steps (and speed) every second:
-			struct timeval tvend;
-			gettimeofday(&tvend, NULL);
-
-			double secondsSinceLastOutput =
-			    ((double)tvend.tv_sec + tvend.tv_usec / 1000000.0)
-			    - ((double)m_lastOutputTime.tv_sec + m_lastOutputTime.tv_usec / 1000000.0);
-
-			if (secondsSinceLastOutput > 1.0 && (step - m_lastOutputStep) > 10000) {
-				m_lastOutputTime = tvend;
-
-				int64_t stepsPerSecond = (int64_t)
-				    ( (double)(step - m_lastOutputStep) / secondsSinceLastOutput );
-				m_lastOutputStep = step;
-
-				stringstream ss;
-				ss << step << " steps";
-				if (stepsPerSecond > 0)
-					ss << " (" << stepsPerSecond << " steps/second)";
-
-				GetUI()->ShowDebugMessage(ss.str());
-			}
-		}
-		break;
-
-	default:
-		std::cerr << "GXemul::Execute() called without being in a"
-		    " running state. Internal error?\n";
-		throw std::exception();
-	}
-
-	if (m_interrupting) {
-		m_interrupting = false;
-		SetRunState(Paused);
-	}
-}
-
-
-/*****************************************************************************/
-
-#ifdef WITHUNITTESTS
-
-static void Test_Construction()
-{
-	GXemul gxemul;
-}
-
-UNITTESTS(GXemul)
-{
-	UNITTEST(Test_Construction);
-
-	// Note: Most execution tests are in DummyComponent.cc, because they
-	// test component behavior. But they also test GXemul::Execute etc.
-}
-
-
-#endif
-
diff -Nru gxemul-0.6.2/src/main/Makefile.skel gxemul-0.7.0+dfsg/src/main/Makefile.skel
--- gxemul-0.6.2/src/main/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,31 +0,0 @@
-#
-#  Makefile for GXemul src/main
-#
-
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(DINCLUDE)
-
-OBJS=Checksum.o Command.o CommandInterpreter.o Component.o ComponentFactory.o \
-	EscapedString.o FileLoader.o GXemul.o StateVariable.o \
-	StringHelper.o SymbolRegistry.o UnitTest.o debug_new.o
-
-all: $(OBJS) do_commands do_fileloaders
-
-$(OBJS): Makefile
-
-do_commands:
-	cd commands; $(MAKE)
-
-do_fileloaders:
-	cd fileloaders; $(MAKE)
-
-clean:
-	cd commands; $(MAKE) clean
-	cd fileloaders; $(MAKE) clean
-	rm -f $(OBJS) *core
-
-clean_all: clean
-	cd commands; $(MAKE) clean_all
-	cd fileloaders; $(MAKE) clean_all
-	rm -f Makefile
-
-
diff -Nru gxemul-0.6.2/src/main/StateVariable.cc gxemul-0.7.0+dfsg/src/main/StateVariable.cc
--- gxemul-0.6.2/src/main/StateVariable.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/StateVariable.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,968 +0,0 @@
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <math.h>
-
-#include "EscapedString.h"
-#include "StateVariable.h"
-#include "StringHelper.h"
-
-
-StateVariable::StateVariable(const string& name, string* ptrToString)
-	: m_name(name)
-	, m_type(String)
-{
-	m_value.pstr = ptrToString;
-}
-
-
-StateVariable::StateVariable(const string& name, bool* ptrToVar)
-	: m_name(name)
-	, m_type(Bool)
-{
-	m_value.pbool = ptrToVar;
-}
-
-
-StateVariable::StateVariable(const string& name, double* ptrToVar)
-	: m_name(name)
-	, m_type(Double)
-{
-	m_value.pdouble = ptrToVar;
-}
-
-
-StateVariable::StateVariable(const string& name, uint8_t* ptrToVar)
-	: m_name(name)
-	, m_type(UInt8)
-{
-	m_value.puint8 = ptrToVar;
-}
-
-
-StateVariable::StateVariable(const string& name, uint16_t* ptrToVar)
-	: m_name(name)
-	, m_type(UInt16)
-{
-	m_value.puint16 = ptrToVar;
-}
-
-
-StateVariable::StateVariable(const string& name, uint32_t* ptrToVar)
-	: m_name(name)
-	, m_type(UInt32)
-{
-	m_value.puint32 = ptrToVar;
-}
-
-
-StateVariable::StateVariable(const string& name, uint64_t* ptrToVar)
-	: m_name(name)
-	, m_type(UInt64)
-{
-	m_value.puint64 = ptrToVar;
-}
-
-
-StateVariable::StateVariable(const string& name, int8_t* ptrToVar)
-	: m_name(name)
-	, m_type(SInt8)
-{
-	m_value.psint8 = ptrToVar;
-}
-
-
-StateVariable::StateVariable(const string& name, int16_t* ptrToVar)
-	: m_name(name)
-	, m_type(SInt16)
-{
-	m_value.psint16 = ptrToVar;
-}
-
-
-StateVariable::StateVariable(const string& name, int32_t* ptrToVar)
-	: m_name(name)
-	, m_type(SInt32)
-{
-	m_value.psint32 = ptrToVar;
-}
-
-
-StateVariable::StateVariable(const string& name, int64_t* ptrToVar)
-	: m_name(name)
-	, m_type(SInt64)
-{
-	m_value.psint64 = ptrToVar;
-}
-
-
-StateVariable::StateVariable(const string& name, CustomStateVariableHandler* ptrToHandler)
-	: m_name(name)
-	, m_type(Custom)
-{
-	m_value.phandler = ptrToHandler;
-}
-
-
-enum StateVariable::Type StateVariable::GetType() const
-{
-	return m_type;
-}
-
-
-const string& StateVariable::GetName() const
-{
-	return m_name;
-}
-
-
-string StateVariable::GetTypeString() const
-{
-	switch (m_type) {
-	case String:
-		return "string";
-	case Bool:
-		return "bool";
-	case Double:
-		return "double";
-	case UInt8:
-		return "uint8";
-	case UInt16:
-		return "uint16";
-	case UInt32:
-		return "uint32";
-	case UInt64:
-		return "uint64";
-	case SInt8:
-		return "sint8";
-	case SInt16:
-		return "sint16";
-	case SInt32:
-		return "sint32";
-	case SInt64:
-		return "sint64";
-	case Custom:
-		return "custom";
-	default:
-		return "unknown";
-	}
-}
-
-
-bool StateVariable::CopyValueFrom(const StateVariable& otherVariable)
-{
-	if (m_type != otherVariable.m_type)
-		return false;
-
-	switch (m_type) {
-	case String:
-		*m_value.pstr = *otherVariable.m_value.pstr;
-		break;
-	case Bool:
-		*m_value.pbool = *otherVariable.m_value.pbool;
-		break;
-	case Double:
-		*m_value.pdouble = *otherVariable.m_value.pdouble;
-		break;
-	case UInt8:
-		*m_value.puint8 = *otherVariable.m_value.puint8;
-		break;
-	case UInt16:
-		*m_value.puint16 = *otherVariable.m_value.puint16;
-		break;
-	case UInt32:
-		*m_value.puint32 = *otherVariable.m_value.puint32;
-		break;
-	case UInt64:
-		*m_value.puint64 = *otherVariable.m_value.puint64;
-		break;
-	case SInt8:
-		*m_value.psint8 = *otherVariable.m_value.psint8;
-		break;
-	case SInt16:
-		*m_value.psint16 = *otherVariable.m_value.psint16;
-		break;
-	case SInt32:
-		*m_value.psint32 = *otherVariable.m_value.psint32;
-		break;
-	case SInt64:
-		*m_value.psint64 = *otherVariable.m_value.psint64;
-		break;
-	case Custom:
-		m_value.phandler->CopyValueFrom(otherVariable.m_value.phandler);
-		break;
-	default:
-		// Unknown type?
-		assert(false);
-		return false;
-	}
-
-	return true;
-}
-
-
-string StateVariable::ToString() const
-{
-	stringstream sstr;
-
-	switch (m_type) {
-	case String:
-		return m_value.pstr == NULL? "" : *m_value.pstr;
-	case Bool:
-		sstr << (*m_value.pbool? "true" : "false");
-		return sstr.str();
-	case Double:
-		sstr << *m_value.pdouble;
-		return sstr.str();
-	case UInt8:
-		sstr << (int) *m_value.puint8;
-		return sstr.str();
-	case UInt16:
-		sstr.flags(std::ios::hex | std::ios::showbase);
-		sstr << *m_value.puint16;
-		return sstr.str();
-	case UInt32:
-		sstr.flags(std::ios::hex | std::ios::showbase);
-		sstr << *m_value.puint32;
-		return sstr.str();
-	case UInt64:
-		sstr.flags(std::ios::hex | std::ios::showbase);
-		sstr << *m_value.puint64;
-		return sstr.str();
-	case SInt8:
-		sstr << (int) *m_value.psint8;
-		return sstr.str();
-	case SInt16:
-		sstr << *m_value.psint16;
-		return sstr.str();
-	case SInt32:
-		sstr << *m_value.psint32;
-		return sstr.str();
-	case SInt64:
-		sstr << *m_value.psint64;
-		return sstr.str();
-	case Custom:
-		return "(custom)";
-	}
-
-	// Unimplemented type?
-	assert(false);
-
-	return "";
-}
-
-
-uint64_t StateVariable::ToInteger() const
-{
-	switch (m_type) {
-	case String:
-		{
-			uint64_t tmp;
-			stringstream ss;
-			ss << *m_value.pstr;
-			ss >> tmp;
-			return tmp;
-		}
-	case Bool:
-		return (*m_value.pbool)? 1 : 0;
-	case Double:
-		return (uint64_t) *m_value.pdouble;
-	case UInt8:
-		return *m_value.puint8;
-	case UInt16:
-		return *m_value.puint16;
-	case UInt32:
-		return *m_value.puint32;
-	case UInt64:
-		return *m_value.puint64;
-	case SInt8:
-		return *m_value.psint8;
-	case SInt16:
-		return *m_value.psint16;
-	case SInt32:
-		return *m_value.psint32;
-	case SInt64:
-		return *m_value.psint64;
-	case Custom:
-		return 0;
-	}
-
-	// Unimplemented type. Let's abort.
-	std::cerr << "StateVariable::ToDouble(): Unimplemented type.\n";
-	throw std::exception();
-}
-
-
-double StateVariable::ToDouble() const
-{
-	switch (m_type) {
-	case String:
-		{
-			double tmp;
-			stringstream ss;
-			ss << *m_value.pstr;
-			ss >> tmp;
-			return tmp;
-		}
-	case Bool:
-		return (*m_value.pbool)? 1.0 : 0.0;
-	case Double:
-		return *m_value.pdouble;
-	case UInt8:
-		return *m_value.puint8;
-	case UInt16:
-		return *m_value.puint16;
-	case UInt32:
-		return *m_value.puint32;
-	case UInt64:
-		return *m_value.puint64;
-	case SInt8:
-		return *m_value.psint8;
-	case SInt16:
-		return *m_value.psint16;
-	case SInt32:
-		return *m_value.psint32;
-	case SInt64:
-		return *m_value.psint64;
-	case Custom:
-		return 0.0;
-	}
-
-	// Unimplemented type. Let's abort.
-	std::cerr << "StateVariable::ToDouble(): Unimplemented type.\n";
-	throw std::exception();
-}
-
-
-void StateVariable::SerializeValue(ostream& ss) const
-{
-	switch (m_type) {
-
-	case String:
-		{
-			EscapedString escaped(ToString());
-			ss << escaped.Generate();
-		}
-		break;
-
-	case Custom:
-		m_value.phandler->Serialize(ss);
-		break;
-
-	default:
-		ss << ToString();
-	}
-}
-
-
-void StateVariable::Serialize(ostream& ss, SerializationContext& context) const
-{
-	ss << context.Tabs() << GetTypeString() << " " << m_name + " ";
-	SerializeValue(ss);
-	ss << "\n";
-}
-
-
-string StateVariable::EvaluateExpression(const string& expression,
-	bool& success) const
-{
-	success = false;
-
-	string result = expression;
-	
-	// Remove leading and trailing spaces:
-	while (result.size() > 0 && result[0] == ' ')
-		result.erase((size_t) 0);
-	while (result.size() > 0 && result[result.size() - 1] == ' ')
-		result.erase(result.size()-1);
-
-// TODO
-success = true;
-return result;
-
-	return "";
-}
-
-
-bool StateVariable::SetValue(const string& expression)
-{
-	// Nothing to assign to?
-	if (m_value.pstr == NULL)
-		return false;
-
-	// Reduce the expression to a single value.
-	bool success = false;
-	string value = EvaluateExpression(expression, success);
-	if (!success)
-		return false;
-
-	switch (m_type) {
-
-	case String:
-		{
-			success = false;
-			string newStr = EscapedString(value).Decode(success);
-			if (success)
-				*m_value.pstr = newStr;
-			else
-				return false;
-		}
-		return true;
-
-	case Bool:
-		{
-			if (value == "true")
-				*m_value.pbool = true;
-			else if (value == "false")
-				*m_value.pbool = false;
-			else
-				return false;
-		}
-		return true;
-
-	case Double:
-		{
-			double doubleTmp;
-			stringstream sstr;
-			sstr << value;
-			sstr >> doubleTmp;
-			if (isnan(doubleTmp) || isinf(doubleTmp))
-				return false;
-			*m_value.pdouble = doubleTmp;
-		}
-		return true;
-
-	case UInt8:
-		{
-			bool error = true;
-			uint64_t tmp64 = StringHelper::ParseNumber(value.c_str(), error);
-			uint8_t tmp = tmp64;
-			if (tmp == tmp64 && !error)
-				*m_value.puint8 = tmp;
-			else
-				return false;
-		}
-		return true;
-
-	case UInt16:
-		{
-			bool error = true;
-			uint64_t tmp64 = StringHelper::ParseNumber(value.c_str(), error);
-			uint16_t tmp = tmp64;
-			if (tmp == tmp64 && !error)
-				*m_value.puint16 = tmp;
-			else
-				return false;
-		}
-		return true;
-		
-	case UInt32:
-		{
-			bool error = true;
-			uint64_t tmp64 = StringHelper::ParseNumber(value.c_str(), error);
-			uint32_t tmp = tmp64;
-			if (tmp == tmp64 && !error)
-				*m_value.puint32 = tmp;
-			else
-				return false;
-		}
-		return true;
-
-	case UInt64:
-		{
-			bool error = true;
-			uint64_t tmp64 = StringHelper::ParseNumber(value.c_str(), error);
-			if (!error)
-				*m_value.puint64 = tmp64;
-			else
-				return false;
-		}
-		return true;
-
-	case SInt8:
-		{
-			bool error = true;
-			int64_t tmp64 = StringHelper::ParseNumber(value.c_str(), error);
-			int8_t tmp = tmp64;
-			if (tmp == tmp64 && !error)
-				*m_value.psint8 = tmp;
-			else
-				return false;
-		}
-		return true;
-
-	case SInt16:
-		{
-			bool error = true;
-			int64_t tmp64 = StringHelper::ParseNumber(value.c_str(), error);
-			int16_t tmp = tmp64;
-			if (tmp == tmp64 && !error)
-				*m_value.psint16 = tmp;
-			else
-				return false;
-		}
-		return true;
-		
-	case SInt32:
-		{
-			bool error = true;
-			int64_t tmp64 = StringHelper::ParseNumber(value.c_str(), error);
-			int32_t tmp = tmp64;
-			if (tmp == tmp64 && !error)
-				*m_value.psint32 = tmp;
-			else
-				return false;
-		}
-		return true;
-
-	case SInt64:
-		{
-			bool error = true;
-			int64_t tmp64 = StringHelper::ParseNumber(value.c_str(), error);
-			if (!error)
-				*m_value.psint64 = tmp64;
-			else
-				return false;
-		}
-		return true;
-
-	case Custom:
-		return m_value.phandler->Deserialize(value);
-
-	default:
-		// Unimplemented type. Let's abort.
-		std::cerr << "StateVariable::SetValue: Unimplemented type.\n";
-		throw std::exception();
-	}
-}
-
-
-bool StateVariable::SetValue(uint64_t value)
-{
-	// Nothing to assign to?
-	if (m_value.pstr == NULL)
-		return false;
-
-	switch (m_type) {
-
-	case String:
-		{
-			stringstream ss;
-			ss << value;
-			*m_value.pstr = ss.str();
-		}
-		return true;
-
-	case Bool:
-		*m_value.pbool = value != 0;
-		return true;
-
-	case Double:
-		*m_value.pdouble = value;
-		return true;
-
-	case UInt8:
-		*m_value.puint8 = value;
-		return true;
-
-	case UInt16:
-		*m_value.puint16 = value;
-		return true;
-		
-	case UInt32:
-		*m_value.puint32 = value;
-		return true;
-
-	case UInt64:
-		*m_value.puint64 = value;
-		return true;
-
-	case SInt8:
-		*m_value.psint8 = value;
-		return true;
-
-	case SInt16:
-		*m_value.psint16 = value;
-		return true;
-		
-	case SInt32:
-		*m_value.psint32 = value;
-		return true;
-
-	case SInt64:
-		*m_value.psint64 = value;
-		return true;
-
-	case Custom:
-		return false;
-
-	default:
-		// Unimplemented type. Let's abort.
-		std::cerr << "StateVariable::SetValue: Unimplemented type.\n";
-		throw std::exception();
-	}
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_StateVariable_String_Construct()
-{
-	string myString = "hi";
-
-	StateVariable var("hello", &myString);
-
-	UnitTest::Assert("name should be hello",
-	    var.GetName(), "hello");
-	UnitTest::Assert("type should be String",
-	    var.GetType() == StateVariable::String);
-	UnitTest::Assert("value should be hi",
-	    var.ToString(), "hi");
-}
-
-static void Test_StateVariable_String_SetValue()
-{
-	string myString = "hi";
-
-	StateVariable var("hello", &myString);
-
-	UnitTest::Assert("setting string value without quotes should not work",
-	    var.SetValue("value2") == false);
-	UnitTest::Assert("setting string value with quotes should work",
-	    var.SetValue("\"value2\"") == true);
-
-	UnitTest::Assert("type should still be String",
-	    var.GetType() == StateVariable::String);
-	UnitTest::Assert("value should now be value2",
-	    var.ToString(), "value2");
-	UnitTest::Assert("myString should have been updated",
-	    myString, "value2");
-}
-
-static void Test_StateVariable_String_CopyValueFrom()
-{
-	string myString1 = "hi";
-	string myString2 = "something";
-
-	StateVariable var1("hello", &myString1);
-	StateVariable var2("world", &myString2);
-
-	UnitTest::Assert("value should initially be hi",
-	    var1.ToString(), "hi");
-
-	var1.CopyValueFrom(var2);
-
-	UnitTest::Assert("name should still be hello",
-	    var1.GetName(), "hello");
-	UnitTest::Assert("type should still be String",
-	    var1.GetType() == StateVariable::String);
-	UnitTest::Assert("value should be changed to something",
-	    var1.ToString(), "something");
-	UnitTest::Assert("myString1 should have been updated",
-	    myString1, "something");
-}
-
-static void Test_StateVariable_String_Serialize()
-{
-	string hi = "value world";
-	StateVariable var("hello", &hi);
-
-	SerializationContext dummyContext;
-	stringstream ss;
-
-	var.Serialize(ss, dummyContext);
-	UnitTest::Assert("variable serialization mismatch?",
-	    ss.str(), "string hello \"value world\"\n");
-}
-
-static void Test_StateVariable_String_Serialize_WithEscapes()
-{
-	string s = "a\\b\tc\nd\re\bf\"g'h";
-	StateVariable var("hello", &s);
-
-	SerializationContext dummyContext;
-	stringstream ss;
-	
-	var.Serialize(ss, dummyContext);
-	UnitTest::Assert("variable serialization mismatch?",
-	    ss.str(),
-	    "string hello " + EscapedString(s).Generate() + "\n");
-}
-
-static void Test_StateVariable_Bool_Construct()
-{
-	bool myBool = true;
-
-	StateVariable var("hello", &myBool);
-
-	UnitTest::Assert("name should be hello",
-	    var.GetName(), "hello");
-	UnitTest::Assert("type should be Bool",
-	    var.GetType() == StateVariable::Bool);
-	UnitTest::Assert("value should be true",
-	    var.ToString(), "true");
-}
-
-static void Test_StateVariable_Bool_SetValue()
-{
-	bool myBool = true;
-
-	StateVariable var("hello", &myBool);
-
-	UnitTest::Assert("changing to false should be possible",
-	    var.SetValue("false") == true);
-
-	UnitTest::Assert("type should still be Bool",
-	    var.GetType() == StateVariable::Bool);
-	UnitTest::Assert("value should now be changed",
-	    var.ToString(), "false");
-	UnitTest::Assert("myBool should have been updated",
-	    myBool == false);
-
-	UnitTest::Assert("changing to true should be possible",
-	    var.SetValue("true") == true);
-
-	UnitTest::Assert("value should now be changed again",
-	    var.ToString(), "true");
-	UnitTest::Assert("myBool should have been updated again",
-	    myBool == true);
-
-	UnitTest::Assert("changing to non-bool value should not be possible",
-	    var.SetValue("hello") == false);
-
-	UnitTest::Assert("value should not be changed",
-	    var.ToString(), "true");
-}
-
-static void Test_StateVariable_Bool_CopyValueFrom()
-{
-	bool myBool1 = false;
-	bool myBool2 = true;
-
-	StateVariable var1("hello", &myBool1);
-	StateVariable var2("world", &myBool2);
-
-	UnitTest::Assert("copying from bool to bool should be possible",
-	    var1.CopyValueFrom(var2) == true);
-
-	UnitTest::Assert("name should still be hello",
-	    var1.GetName(), "hello");
-	UnitTest::Assert("type should still be Bool",
-	    var1.GetType() == StateVariable::Bool);
-	UnitTest::Assert("value should be changed to true",
-	    var1.ToString(), "true");
-	UnitTest::Assert("myBool1 should have been updated",
-	    myBool1 == true);
-
-	string myString = "hm";
-	StateVariable var3("test", &myString);
-
-	UnitTest::Assert("copying from string to bool should not be possible",
-	    var1.CopyValueFrom(var3) == false);
-}
-
-static void Test_StateVariable_Bool_Serialize()
-{
-	bool myBool = true;
-	StateVariable var("hello", &myBool);
-
-	SerializationContext dummyContext;
-	stringstream ss;
-	
-	var.Serialize(ss, dummyContext);
-	UnitTest::Assert("variable serialization mismatch (1)",
-	    ss.str(), "bool hello true\n");
-	
-	myBool = false;
-	stringstream ss2;
-	var.Serialize(ss2, dummyContext);
-
-	UnitTest::Assert("variable serialization mismatch (2)",
-	    ss2.str(), "bool hello false\n");
-}
-
-static void Test_StateVariable_Numeric_Construct()
-{
-	double   varDouble = -12.345;
-	uint8_t  varUInt8  = 223;
-	uint16_t varUInt16 = 55000;
-	uint32_t varUInt32 = 3000000001UL;
-	uint64_t varUInt64 = ((uint64_t) 0xfedc0102 << 32) | 0x03040506;
-	int8_t   varSInt8  = -120;
-	int16_t  varSInt16 = -22000;
-	int32_t  varSInt32 = -1000000001;
-	int64_t  varSInt64 = ((uint64_t) 0xfedc0102 << 32) | 0x03040506;
-
-	StateVariable vdouble("vdouble", &varDouble);
-	StateVariable vuint8 ("vuint8",  &varUInt8);
-	StateVariable vuint16("vuint16", &varUInt16);
-	StateVariable vuint32("vuint32", &varUInt32);
-	StateVariable vuint64("vuint64", &varUInt64);
-	StateVariable vsint8 ("vsint8",  &varSInt8);
-	StateVariable vsint16("vsint16", &varSInt16);
-	StateVariable vsint32("vsint32", &varSInt32);
-	StateVariable vsint64("vsint64", &varSInt64);
-
-	// Types
-	UnitTest::Assert("Double", vdouble.GetType() == StateVariable::Double);
-	UnitTest::Assert("UInt8",  vuint8.GetType()  == StateVariable::UInt8);
-	UnitTest::Assert("UInt16", vuint16.GetType() == StateVariable::UInt16);
-	UnitTest::Assert("UInt32", vuint32.GetType() == StateVariable::UInt32);
-	UnitTest::Assert("UInt64", vuint64.GetType() == StateVariable::UInt64);
-	UnitTest::Assert("SInt8",  vsint8.GetType()  == StateVariable::SInt8);
-	UnitTest::Assert("SInt16", vsint16.GetType() == StateVariable::SInt16);
-	UnitTest::Assert("SInt32", vsint32.GetType() == StateVariable::SInt32);
-	UnitTest::Assert("SInt64", vsint64.GetType() == StateVariable::SInt64);
-
-	// Values
-	UnitTest::Assert("value Double", vdouble.ToString(), "-12.345");
-	UnitTest::Assert("value UInt8",  vuint8.ToString(),  "223");
-	UnitTest::Assert("value UInt16", vuint16.ToString(), "0xd6d8");
-	UnitTest::Assert("value UInt32", vuint32.ToString(), "0xb2d05e01");
-	UnitTest::Assert("value UInt64", vuint64.ToString(),
-	    "0xfedc010203040506");
-	UnitTest::Assert("value SInt8",  vsint8.ToString(),  "-120");
-	UnitTest::Assert("value SInt16", vsint16.ToString(), "-22000");
-	UnitTest::Assert("value SInt32", vsint32.ToString(), "-1000000001");
-	UnitTest::Assert("value SInt64", vsint64.ToString(),
-	    "-82189585047354106");
-}
-
-static void Test_StateVariable_Numeric_SetValue()
-{
-	double   varDouble = -12.345;
-	uint8_t  varUInt8  = 223;
-	uint16_t varUInt16 = 55000;
-	uint32_t varUInt32 = 3000000001UL;
-	uint64_t varUInt64 = ((uint64_t) 0xfedc0102 << 32) | 0x03040506;
-	int8_t   varSInt8  = -120;
-	int16_t  varSInt16 = -22000;
-	int32_t  varSInt32 = -1000000001;
-	int64_t  varSInt64 = ((uint64_t) 0xfedc0102 << 32) | 0x03040506;
-
-	StateVariable vdouble("vdouble", &varDouble);
-	StateVariable vuint8 ("vuint8",  &varUInt8);
-	StateVariable vuint16("vuint16", &varUInt16);
-	StateVariable vuint32("vuint32", &varUInt32);
-	StateVariable vuint64("vuint64", &varUInt64);
-	StateVariable vsint8 ("vsint8",  &varSInt8);
-	StateVariable vsint16("vsint16", &varSInt16);
-	StateVariable vsint32("vsint32", &varSInt32);
-	StateVariable vsint64("vsint64", &varSInt64);
-
-	UnitTest::Assert("changing to 'hello' should not be possible",
-	    vuint8.SetValue("hello") == false);
-
-	// Double
-	UnitTest::Assert("changing to 100 should be possible",
-	    vdouble.SetValue("100") == true);
-	UnitTest::Assert("varDouble should have been updated",
-	    varDouble == 100);
-	UnitTest::Assert("changing to -210.42 should be possible",
-	    vdouble.SetValue("-210.42") == true);
-	UnitTest::Assert("varDouble should not have been updated",
-	    varDouble == -210.42);
-	UnitTest::Assert("changing to 1e-100 should be possible (2)",
-	    vdouble.SetValue("1e-100") == true);
-	UnitTest::Assert("varDouble should have been updated (2)",
-	    varDouble == 1e-100);
-
-	// UInt8
-	UnitTest::Assert("changing to 100 should be possible",
-	    vuint8.SetValue("100") == true);
-	UnitTest::Assert("varUInt8 should have been updated",
-	    varUInt8, 100);
-	UnitTest::Assert("changing to 0x2f should be possible",
-	    vuint8.SetValue("0x2f") == true);
-	UnitTest::Assert("varUInt8 should have been updated to 0x2f",
-	    varUInt8, 0x2f);
-	UnitTest::Assert("changing to 300 should not be possible",
-	    vuint8.SetValue("300") == false);
-	UnitTest::Assert("varUInt8 should not have been updated",
-	    varUInt8, 0x2f);
-	UnitTest::Assert("changing to -110 should not be possible",
-	    vuint8.SetValue("-110") == false);
-	UnitTest::Assert("varUInt8 should not have been updated",
-	    varUInt8, 0x2f);
-
-	// SInt8
-	UnitTest::Assert("changing to 100 should be possible",
-	    vsint8.SetValue("100") == true);
-	UnitTest::Assert("varSInt8 should have been updated",
-	    varSInt8, 100);
-	UnitTest::Assert("changing to 200 should not be possible",
-	    vsint8.SetValue("200") == false);
-	UnitTest::Assert("varSInt8 should not have been updated",
-	    varSInt8, 100);
-	UnitTest::Assert("changing to -210 should not be possible",
-	    vsint8.SetValue("-210") == false);
-	UnitTest::Assert("varSInt8 should not have been updated",
-	    varSInt8, 100);
-	UnitTest::Assert("changing to -110 should be possible",
-	    vsint8.SetValue("-110") == true);
-	UnitTest::Assert("varSInt8 should have been updated",
-	    varSInt8, (uint64_t) -110);
-	UnitTest::Assert("changing to -0x1a should be possible",
-	    vsint8.SetValue("-0x1a") == true);
-	UnitTest::Assert("varSInt8 should have been updated",
-	    varSInt8, (uint64_t) -0x1a);
-
-	// Tests for other numeric types: TODO
-}
-
-UNITTESTS(StateVariable)
-{
-	// String tests
-	UNITTEST(Test_StateVariable_String_Construct);
-	UNITTEST(Test_StateVariable_String_SetValue);
-	UNITTEST(Test_StateVariable_String_CopyValueFrom);
-	UNITTEST(Test_StateVariable_String_Serialize);
-	UNITTEST(Test_StateVariable_String_Serialize_WithEscapes);
-
-	// Bool tests
-	UNITTEST(Test_StateVariable_Bool_Construct);
-	UNITTEST(Test_StateVariable_Bool_SetValue);
-	UNITTEST(Test_StateVariable_Bool_CopyValueFrom);
-	UNITTEST(Test_StateVariable_Bool_Serialize);
-
-	// Numeric tests
-	UNITTEST(Test_StateVariable_Numeric_Construct);
-	UNITTEST(Test_StateVariable_Numeric_SetValue);
-	//UNITTEST(Test_StateVariable_Numeric_CopyValueFrom);
-	//UNITTEST(Test_StateVariable_Numeric_Serialize);
-
-	// TODO: ToInteger tests.
-
-	// TODO: Custom tests.
-}
-
-#endif
-
diff -Nru gxemul-0.6.2/src/main/StringHelper.cc gxemul-0.7.0+dfsg/src/main/StringHelper.cc
--- gxemul-0.6.2/src/main/StringHelper.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/StringHelper.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,338 +0,0 @@
-/*
- *  Copyright (C) 2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "StringHelper.h"
-
-
-// This is basically strtoull(), but it needs to be explicitly implemented
-// since some systems lack it. (Also, compiling with GNU C++ in ANSI mode
-// does not work with strtoull.)
-uint64_t StringHelper::ParseNumber(const char* str, bool& error)
-{
-	bool baseSet = false;
-	int base = 10;
-	uint64_t result = 0;
-	bool negative = false;
-
-	error = false;
-
-	if (str == NULL)
-		return 0;
-
-	while (*str == ' ')
-		++str;
-
-	if (*str == '-') {
-		negative = true;
-		++str;
-	}
-
-	while ((*str == 'x' || *str == 'X') || (*str >= '0' && *str <= '9')
-	    || (*str >= 'a' && *str <= 'f') || (*str >= 'A' && *str <= 'F')) {
-		char c = *str;
-
-		if (c == 'x' || c == 'X') {
-			// Multiple base selections are not allowed.
-			if (baseSet)
-				break;
-
-			// Only 0 prefix before base selection is allowed,
-			// no other values.
-			if (result != 0)
-				break;
-
-			base = 16;
-			baseSet = true;
-		} else {
-			if (base == 10 && (c < '0' || c > '9'))
-				break;
-
-			int n = c - '0';
-			if (c >= 'a' && c <= 'f')
-				n = *str - 'a' + 10;
-			if (c >= 'A' && c <= 'F')
-				n = *str - 'A' + 10;
-
-			if (base == 16 && (n < 0 || n > 15))
-				break;
-
-			result = result * base + n;
-		}
-
-		++str;
-	}
-
-	if (*str)
-		error = true;
-
-	if (negative)
-		return -result;
-	else
-		return result;
-}
-
-
-vector<string> StringHelper::SplitStringIntoVector(const string &str, const char splitter)
-{
-	// This is slow and hackish, but works.
-	vector<string> strings;
-	string word;
-	bool lastWasSplitter = false;
-
-	for (size_t i=0, n=str.length(); i<n; i++) {
-		char ch = str[i];
-		if (ch == splitter) {
-			strings.push_back(word);
-			word = "";
-			lastWasSplitter = true;
-		} else {
-			word += ch;
-			lastWasSplitter = false;
-		}
-	}
-
-	if (word != "" || lastWasSplitter)
-		strings.push_back(word);
-
-	return strings;
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_StringHelper_ParseNumber_Simple()
-{
-	string s = "42";
-	bool error = true;
-
-	uint64_t value = StringHelper::ParseNumber(s.c_str(), error);
-
-	UnitTest::Assert("Should have succeeded with no error", error == false);
-	UnitTest::Assert("Unexpected resulting value", value, 42);
-}
-
-static void Test_StringHelper_ParseNumber_SimpleError()
-{
-	string s = "Q42";
-	bool error = false;
-
-	StringHelper::ParseNumber(s.c_str(), error);
-
-	UnitTest::Assert("Should have resulted in error", error == true);
-}
-
-static void Test_StringHelper_ParseNumber_Negative()
-{
-	string s = "-42";
-	bool error = true;
-
-	uint64_t value = StringHelper::ParseNumber(s.c_str(), error);
-
-	UnitTest::Assert("Should have succeeded with no error", error == false);
-	UnitTest::Assert("Unexpected resulting value", value, (uint64_t) -42);
-}
-
-static void Test_StringHelper_ParseNumber_LeadingSpaces()
-{
-	string s = "        42";
-	bool error = true;
-
-	uint64_t value = StringHelper::ParseNumber(s.c_str(), error);
-
-	UnitTest::Assert("Should have succeeded with no error", error == false);
-	UnitTest::Assert("Unexpected resulting value", value, 42);
-}
-
-static void Test_StringHelper_ParseNumber_LeadingSpacesAndNegative()
-{
-	string s = "        -42";
-	bool error = true;
-
-	uint64_t value = StringHelper::ParseNumber(s.c_str(), error);
-
-	UnitTest::Assert("Should have succeeded with no error", error == false);
-	UnitTest::Assert("Unexpected resulting value", value, (uint64_t) -42);
-}
-
-static void Test_StringHelper_ParseNumber_LeadingSpacesAndErrorNegative()
-{
-	string s = "        - 42";
-	bool error = false;
-
-	StringHelper::ParseNumber(s.c_str(), error);
-
-	UnitTest::Assert("Should have resulted in error", error == true);
-}
-
-static void Test_StringHelper_ParseNumber_SimpleHexLowerCase()
-{
-	string s = "0x42a";
-	bool error = true;
-
-	uint64_t value = StringHelper::ParseNumber(s.c_str(), error);
-
-	UnitTest::Assert("Should have succeeded with no error", error == false);
-	UnitTest::Assert("Unexpected resulting value", value, 0x42a);
-}
-
-static void Test_StringHelper_ParseNumber_SimpleHexUpperCase()
-{
-	string s = "0X42A";
-	bool error = true;
-
-	uint64_t value = StringHelper::ParseNumber(s.c_str(), error);
-
-	UnitTest::Assert("Should have succeeded with no error", error == false);
-	UnitTest::Assert("Unexpected resulting value", value, 0x42a);
-}
-
-static void Test_StringHelper_ParseNumber_HexErrorDoubleX()
-{
-	string s = "0xx42";
-	bool error = false;
-
-	StringHelper::ParseNumber(s.c_str(), error);
-
-	UnitTest::Assert("Should have resulted in error", error == true);
-}
-
-static void Test_StringHelper_ParseNumber_HexErrorNonZeroPrefix()
-{
-	string s = "04x42";
-	bool error = false;
-
-	StringHelper::ParseNumber(s.c_str(), error);
-
-	UnitTest::Assert("Should have resulted in error", error == true);
-}
-
-static void Test_StringHelper_ParseNumber_NumberFollowedByErrorValidHexChar()
-{
-	string s = "42A";	// Note: A is a valid hex char
-	bool error = false;
-
-	StringHelper::ParseNumber(s.c_str(), error);
-
-	UnitTest::Assert("Should have resulted in error", error == true);
-}
-
-static void Test_StringHelper_ParseNumber_NumberFollowedByError()
-{
-	string s = "42Q";
-	bool error = false;
-
-	StringHelper::ParseNumber(s.c_str(), error);
-
-	UnitTest::Assert("Should have resulted in error", error == true);
-}
-
-static void Test_StringHelper_SplitStringIntoVector_Simple()
-{
-	vector<string> v = StringHelper::SplitStringIntoVector("A:B:C", ':');
-
-	UnitTest::Assert("Wrong number of strings?", v.size(), 3);
-	UnitTest::Assert("Wrong string contents?", v[0], "A");
-	UnitTest::Assert("Wrong string contents?", v[1], "B");
-	UnitTest::Assert("Wrong string contents?", v[2], "C");
-}
-
-static void Test_StringHelper_SplitStringIntoVector_EmptyInput()
-{
-	vector<string> v = StringHelper::SplitStringIntoVector("", ':');
-
-	UnitTest::Assert("Wrong number of strings?", v.size(), 0);
-}
-
-static void Test_StringHelper_SplitStringIntoVector_Simple2()
-{
-	vector<string> v = StringHelper::SplitStringIntoVector("A:B:C", 'B');
-
-	UnitTest::Assert("Wrong number of strings?", v.size(), 2);
-	UnitTest::Assert("Wrong string contents?", v[0], "A:");
-	UnitTest::Assert("Wrong string contents?", v[1], ":C");
-}
-
-static void Test_StringHelper_SplitStringIntoVector_WithZeroLengthParts()
-{
-	vector<string> v = StringHelper::SplitStringIntoVector("A::B:::C", ':');
-
-	UnitTest::Assert("Wrong number of strings?", v.size(), 6);
-	UnitTest::Assert("Wrong string contents?", v[0], "A");
-	UnitTest::Assert("Wrong string contents?", v[1], "");
-	UnitTest::Assert("Wrong string contents?", v[2], "B");
-	UnitTest::Assert("Wrong string contents?", v[3], "");
-	UnitTest::Assert("Wrong string contents?", v[4], "");
-	UnitTest::Assert("Wrong string contents?", v[5], "C");
-}
-
-static void Test_StringHelper_SplitStringIntoVector_WithTrailingZeroLengthParts()
-{
-	vector<string> v = StringHelper::SplitStringIntoVector("A::", ':');
-
-	UnitTest::Assert("Wrong number of strings?", v.size(), 3);
-	UnitTest::Assert("Wrong string contents?", v[0], "A");
-	UnitTest::Assert("Wrong string contents?", v[1], "");
-	UnitTest::Assert("Wrong string contents?", v[2], "");
-}
-
-static void Test_StringHelper_SplitStringIntoVector_WithHeadingZeroLengthParts()
-{
-	vector<string> v = StringHelper::SplitStringIntoVector("A::", 'A');
-
-	UnitTest::Assert("Wrong number of strings?", v.size(), 2);
-	UnitTest::Assert("Wrong string contents?", v[0], "");
-	UnitTest::Assert("Wrong string contents?", v[1], "::");
-}
-
-UNITTESTS(StringHelper)
-{
-	UNITTEST(Test_StringHelper_ParseNumber_Simple);
-	UNITTEST(Test_StringHelper_ParseNumber_SimpleError);
-	UNITTEST(Test_StringHelper_ParseNumber_Negative);
-	UNITTEST(Test_StringHelper_ParseNumber_LeadingSpaces);
-	UNITTEST(Test_StringHelper_ParseNumber_LeadingSpacesAndNegative);
-	UNITTEST(Test_StringHelper_ParseNumber_LeadingSpacesAndErrorNegative);
-	UNITTEST(Test_StringHelper_ParseNumber_SimpleHexLowerCase);
-	UNITTEST(Test_StringHelper_ParseNumber_SimpleHexUpperCase);
-	UNITTEST(Test_StringHelper_ParseNumber_HexErrorDoubleX);
-	UNITTEST(Test_StringHelper_ParseNumber_HexErrorNonZeroPrefix);
-	UNITTEST(Test_StringHelper_ParseNumber_NumberFollowedByErrorValidHexChar);
-	UNITTEST(Test_StringHelper_ParseNumber_NumberFollowedByError);
-
-	UNITTEST(Test_StringHelper_SplitStringIntoVector_Simple);
-	UNITTEST(Test_StringHelper_SplitStringIntoVector_EmptyInput);
-	UNITTEST(Test_StringHelper_SplitStringIntoVector_Simple2);
-	UNITTEST(Test_StringHelper_SplitStringIntoVector_WithZeroLengthParts);
-	UNITTEST(Test_StringHelper_SplitStringIntoVector_WithTrailingZeroLengthParts);
-	UNITTEST(Test_StringHelper_SplitStringIntoVector_WithHeadingZeroLengthParts);
-}
-
-#endif
-
diff -Nru gxemul-0.6.2/src/main/SymbolRegistry.cc gxemul-0.7.0+dfsg/src/main/SymbolRegistry.cc
--- gxemul-0.6.2/src/main/SymbolRegistry.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/SymbolRegistry.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,158 +0,0 @@
-/*
- *  Copyright (C) 2009-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "SymbolRegistry.h"
-
-
-SymbolRegistry::SymbolRegistry()
-{
-}
-
-
-void SymbolRegistry::Clear()
-{
-	m_map.clear();
-}
-
-
-void SymbolRegistry::AddSymbol(const string& symbol, uint64_t vaddr)
-{
-	m_map[vaddr] = symbol;
-}
-
-
-string SymbolRegistry::LookupAddress(uint64_t vaddr, bool allowOffset) const
-{
-	// Must be an exact match?
-	if (!allowOffset) {
-		SymbolMap::const_iterator a = m_map.find(vaddr);
-		return a == m_map.end()? "" : a->second;
-	}
-
-	// Try to find the symbol given the address, or at least some
-	// symbol close to it:
-	SymbolMap::const_iterator a = m_map.lower_bound(vaddr);
-	if (a == m_map.end()) {
-		if (m_map.empty())
-			return "";
-
-		a = m_map.end();
-	}
-
-	// Exact match? Then just return the symbol.
-	if (a != m_map.end() && vaddr == a->first)
-		return a->second;
-
-	if (a == m_map.begin())
-		return "";
-
-	// Return the symbol _before_ the address, plus an offset.
-	--a;
-
-	stringstream ss;
-	ss.flags(std::ios::hex);
-	ss << a->second << "+0x" << (vaddr - a->first);
-	return ss.str();
-}
-
-
-/*****************************************************************************/
-
-
-#ifdef WITHUNITTESTS
-
-static void Test_SymbolRegistry_Basic()
-{
-	SymbolRegistry registry;
-
-	registry.AddSymbol("symA", 0x1000);
-	registry.AddSymbol("symB", 0x1020);
-	registry.AddSymbol("symC", 0x1060);
-
-	UnitTest::Assert("lookup failed 1?",
-	    registry.LookupAddress(0x1020, true), "symB");
-
-	UnitTest::Assert("lookup failed 2?",
-	    registry.LookupAddress(0x1020, false), "symB");
-
-	registry.Clear();
-
-	UnitTest::Assert("clear failed?",
-	    registry.LookupAddress(0x1020, true), "");
-}
-
-static void Test_SymbolRegistry_BeforeFirst()
-{
-	SymbolRegistry registry;
-
-	registry.AddSymbol("symA", 0x1000);
-	registry.AddSymbol("symB", 0x1020);
-
-	UnitTest::Assert("lookup should have failed 1",
-	    registry.LookupAddress(0xffc, true), "");
-
-	UnitTest::Assert("lookup should have failed 2",
-	    registry.LookupAddress(0xffc, false), "");
-}
-
-static void Test_SymbolRegistry_WithOffset()
-{
-	SymbolRegistry registry;
-
-	registry.AddSymbol("symA", 0x1000);
-	registry.AddSymbol("symB", 0x1020);
-
-	UnitTest::Assert("lookup failed?",
-	    registry.LookupAddress(0x1006, true), "symA+0x6");
-
-	UnitTest::Assert("lookup should have failed",
-	    registry.LookupAddress(0x1006, false), "");
-}
-
-static void Test_SymbolRegistry_AfterLast()
-{
-	SymbolRegistry registry;
-
-	registry.AddSymbol("symA", 0x1000);
-	registry.AddSymbol("symB", 0x1020);
-
-	UnitTest::Assert("lookup failed?",
-	    registry.LookupAddress(0x1090, true), "symB+0x70");
-
-	UnitTest::Assert("lookup should have failed",
-	    registry.LookupAddress(0x1090, false), "");
-}
-
-UNITTESTS(SymbolRegistry)
-{
-	UNITTEST(Test_SymbolRegistry_Basic);
-	UNITTEST(Test_SymbolRegistry_BeforeFirst);
-	UNITTEST(Test_SymbolRegistry_WithOffset);
-	UNITTEST(Test_SymbolRegistry_AfterLast);
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/main/UnitTest.cc gxemul-0.7.0+dfsg/src/main/UnitTest.cc
--- gxemul-0.6.2/src/main/UnitTest.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/main/UnitTest.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,117 +0,0 @@
-/*
- *  Copyright (C) 2007-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <iostream>
-
-#include "misc.h"
-#include "UnitTest.h"
-
-// The list of classes to test is detected by the configure script, and
-// placed in unittest.h, but the classes corresponding .h files also need
-// to be included. This is done by unittest_h.h (also generated by the
-// configure script).
-#include "../../unittest_h.h"
-
-
-void UnitTest::Assert(const string& strFailMessage, bool condition)
-{
-	if (!condition)
-		Fail(strFailMessage);
-}
-
-
-void UnitTest::Assert(const string& strFailMessage,
-	uint64_t actualValue, uint64_t expectedValue)
-{
-	if (actualValue != expectedValue) {
-		stringstream ss;
-		ss.flags(std::ios::hex | std::ios::showbase);
-		ss << strFailMessage <<
-		    "\n\tExpected: " << expectedValue <<
-		    "\n\tbut was:  " << actualValue;
-		Fail(ss.str());
-	}
-}
-
-
-void UnitTest::Assert(const string& strFailMessage,
-	const string& actualValue, const string& expectedValue)
-{
-	if (actualValue != expectedValue) {
-		size_t pos;
-		for (pos = 0; pos < actualValue.length() && pos < expectedValue.length(); pos++)
-			if (actualValue[pos] != expectedValue[pos])
-				break;
-
-		stringstream mismatchPosition;
-		mismatchPosition << "\n\tMismatch at position " << pos;
-
-		Fail(strFailMessage + mismatchPosition.str() +
-		    "\n\tExpected: \"" + expectedValue + "\"" +
-		    "\n\tbut was:  \"" + actualValue + "\"");
-	}
-}
-
-
-void UnitTest::Fail(const string& strMessage)
-{
-	throw UnitTestFailedException(strMessage);
-}
-
-
-#ifndef WITHUNITTESTS
-
-
-int UnitTest::RunTests()
-{
-	std::cerr << "Skipping unit tests, because WITHUNITTESTS "
-	    "was not defined.\n";
-
-	return 0;
-}
-
-
-#else	// WITHUNITTESTS
-
-
-int UnitTest::RunTests()
-{
-	int nSucceeded = 0, nFailed = 0;
-
-#include "../../unittest.h"
-
-	if (nFailed == 0)
-		std::cerr << nSucceeded << " (all) tests passed.\n";
-	else
-		std::cerr << "\n" << nFailed << " TESTS FAILED!\n";
-
-	// Returns 0 if there were no errors.
-	return nFailed > 0;
-}
-
-
-#endif	// WITHUNITTESTS
diff -Nru gxemul-0.6.2/src/Makefile.skel gxemul-0.7.0+dfsg/src/Makefile.skel
--- gxemul-0.6.2/src/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -5,16 +5,12 @@
 all: do_include
 	$(MAKE) the_rest
 
-the_rest: do_components do_console do_cpus do_debugger do_devices do_disk \
-	do_file do_machines do_main do_net do_old_main \
-	do_promemul do_symbol do_ui
+the_rest: do_console do_cpus do_debugger do_devices do_disk \
+	do_file do_machines do_net do_core do_promemul do_symbol
 
 do_include:
 	cd include; $(MAKE)
 
-do_components:
-	cd components; $(MAKE)
-
 do_console:
 	cd console; $(MAKE)
 
@@ -36,14 +32,11 @@
 do_machines:
 	cd machines; $(MAKE)
 
-do_main:
-	cd main; $(MAKE)
-
 do_net:
 	cd net; $(MAKE)
 
-do_old_main:
-	cd old_main; $(MAKE)
+do_core:
+	cd core; $(MAKE)
 
 do_promemul:
 	cd promemul; $(MAKE)
@@ -51,17 +44,13 @@
 do_symbol:
 	cd symbol; $(MAKE)
 
-do_ui:
-	cd ui; $(MAKE)
-
 
 $(OBJS): Makefile
 
 
 clean:
-	rm -f $(OBJS) *core
+	rm -f $(OBJS) *.core
 	cd include; $(MAKE) clean
-	cd components; $(MAKE) clean
 	cd console; $(MAKE) clean
 	cd cpus; $(MAKE) clean
 	cd debugger; $(MAKE) clean
@@ -69,16 +58,13 @@
 	cd disk; $(MAKE) clean
 	cd file; $(MAKE) clean
 	cd machines; $(MAKE) clean
-	cd main; $(MAKE) clean
 	cd net; $(MAKE) clean
-	cd old_main; $(MAKE) clean
+	cd core; $(MAKE) clean
 	cd promemul; $(MAKE) clean
 	cd symbol; $(MAKE) clean
-	cd ui; $(MAKE) clean
 
 clean_all: clean
 	cd include; $(MAKE) clean_all
-	cd components; $(MAKE) clean_all
 	cd console; $(MAKE) clean_all
 	cd cpus; $(MAKE) clean_all
 	cd debugger; $(MAKE) clean_all
@@ -86,12 +72,10 @@
 	cd disk; $(MAKE) clean_all
 	cd file; $(MAKE) clean_all
 	cd machines; $(MAKE) clean_all
-	cd main; $(MAKE) clean_all
 	cd net; $(MAKE) clean_all
-	cd old_main; $(MAKE) clean_all
+	cd core; $(MAKE) clean_all
 	cd promemul; $(MAKE) clean_all
 	cd symbol; $(MAKE) clean_all
-	cd ui; $(MAKE) clean_all
 	rm -f Makefile
 
 
diff -Nru gxemul-0.6.2/src/net/Makefile.skel gxemul-0.7.0+dfsg/src/net/Makefile.skel
--- gxemul-0.6.2/src/net/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/net/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -2,9 +2,9 @@
 #  Makefile for GXemul src/net
 #
 
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
+CFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
 
-OBJS=net.o net_ip.o net_misc.o
+OBJS=net.o net_ip.o net_misc.o net_tap.o net_ether.o
 
 all: $(OBJS)
 
diff -Nru gxemul-0.6.2/src/net/net.c gxemul-0.7.0+dfsg/src/net/net.c
--- gxemul-0.6.2/src/net/net.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/net/net.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,870 @@
+/*
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Emulated network.
+ *
+ *  (Read the README file in this directory for more details.)
+ *
+ *
+ *  NOTE: The 'nic' argument used in many functions in this file is a pointer
+ *  to the nic_data for each NIC, so that if multiple NICs are emulated
+ *  concurrently, they will not get packets that are meant for some other
+ *  controller.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <errno.h>
+#include <sys/types.h>
+#include <sys/socket.h>
+#include <netinet/in.h>
+#include <arpa/inet.h>
+#include <netdb.h>
+#include <fcntl.h>
+#include <signal.h>
+
+#include "machine.h"
+#include "misc.h"
+#include "net.h"
+
+
+/*
+ *  net_allocate_ethernet_packet_link():
+ *
+ *  This routine allocates an ethernet_packet_link struct, and adds it at
+ *  the end of the packet chain.  A data buffer is allocated, and the data,
+ *  nic, and len fields of the link are set.
+ *
+ *  Note: The data buffer is not zeroed.
+ *
+ *  Return value is a pointer to the link on success. It doesn't return on
+ *  failure.
+ */
+struct ethernet_packet_link *net_allocate_ethernet_packet_link(
+	struct net *net, struct nic_data *nic, size_t len)
+{
+	struct ethernet_packet_link *lp;
+
+	CHECK_ALLOCATION(lp = (struct ethernet_packet_link *)
+	    malloc(sizeof(struct ethernet_packet_link)));
+
+	lp->len = len;
+	lp->nic = nic;
+	CHECK_ALLOCATION(lp->data = (unsigned char *) malloc(len));
+
+	lp->next = NULL;
+
+	/*  Add last in the link chain:  */
+	lp->prev = net->last_ethernet_packet;
+	if (lp->prev != NULL)
+		lp->prev->next = lp;
+	else
+		net->first_ethernet_packet = lp;
+	net->last_ethernet_packet = lp;
+
+	return lp;
+}
+
+
+/*
+ *  net_arp():
+ *
+ *  Handle an ARP (or RARP) packet, coming from the emulated NIC.
+ *
+ *  An ARP packet might look like this:
+ *
+ *	ARP header:
+ *	    ARP hardware addr family:	0001
+ *	    ARP protocol addr family:	0800
+ *	    ARP addr lengths:		06 04
+ *	    ARP request:		0001
+ *	    ARP from:			112233445566 01020304
+ *	    ARP to:			000000000000 01020301
+ *
+ *  An ARP request with a 'to' IP value of the gateway should cause an
+ *  ARP response packet to be created.
+ *
+ *  An ARP request with the same from and to IP addresses should be ignored.
+ *  (This would be a host testing to see if there is an IP collision.)
+ */
+static void net_arp(struct net *net, struct nic_data *nic,
+	unsigned char *packet, int len, int reverse)
+{
+	int q;
+	int i;
+
+	/*  TODO: This debug dump assumes ethernet->IPv4 translation:  */
+	if (reverse)
+		debug("[ net: RARP: ");
+	else
+		debug("[ net: ARP: ");
+	for (i=0; i<2; i++)
+		debug("%02x", packet[i]);
+	debug(" ");
+	for (i=2; i<4; i++)
+		debug("%02x", packet[i]);
+	debug(" ");
+	debug("%02x", packet[4]);
+	debug(" ");
+	debug("%02x", packet[5]);
+	debug(" req=");
+	debug("%02x", packet[6]);	/*  Request type  */
+	debug("%02x", packet[7]);
+	debug(" from=");
+	for (i=8; i<18; i++)
+		debug("%02x", packet[i]);
+	debug(" to=");
+	for (i=18; i<28; i++)
+		debug("%02x", packet[i]);
+	debug(" ]\n");
+
+	if (packet[0] == 0x00 && packet[1] == 0x01 &&
+	    packet[2] == 0x08 && packet[3] == 0x00 &&
+	    packet[4] == 0x06 && packet[5] == 0x04) {
+		int r = (packet[6] << 8) + packet[7];
+		struct ethernet_packet_link *lp;
+
+		switch (r) {
+		case 1:		/*  Request  */
+			/*  Only create a reply if this was meant for the
+			    gateway:  */
+			if (memcmp(packet+24, net->gateway_ipv4_addr, 4) != 0)
+				break;
+
+			lp = net_allocate_ethernet_packet_link(
+			    net, nic, 60 + 14);
+
+			/*  Copy the old packet first:  */
+			memset(lp->data, 0, 60 + 14);
+			memcpy(lp->data + 14, packet, len);
+
+			/*  Add ethernet ARP header:  */
+			memcpy(lp->data + 0, lp->data + 8 + 14, 6);
+			memcpy(lp->data + 6, net->gateway_ethernet_addr, 6);
+			lp->data[12] = 0x08; lp->data[13] = 0x06;
+
+			/*  Address of the emulated machine:  */
+			memcpy(lp->data + 18 + 14, lp->data + 8 + 14, 10);
+
+			/*  Address of the gateway:  */
+			memcpy(lp->data +  8 + 14, net->gateway_ethernet_addr,
+			    6);
+			memcpy(lp->data + 14 + 14, net->gateway_ipv4_addr, 4);
+
+			/*  This is a Reply:  */
+			lp->data[6 + 14] = 0x00; lp->data[7 + 14] = 0x02;
+
+			break;
+		case 3:		/*  Reverse Request  */
+			lp = net_allocate_ethernet_packet_link(
+			    net, nic, 60 + 14);
+
+			/*  Copy the old packet first:  */
+			memset(lp->data, 0, 60 + 14);
+			memcpy(lp->data + 14, packet, len);
+
+			/*  Add ethernet RARP header:  */
+			memcpy(lp->data + 0, packet + 8, 6);
+			memcpy(lp->data + 6, net->gateway_ethernet_addr, 6);
+			lp->data[12] = 0x80; lp->data[13] = 0x35;
+
+			/*  This is a RARP reply:  */
+			lp->data[6 + 14] = 0x00; lp->data[7 + 14] = 0x04;
+
+			/*  Address of the gateway:  */
+			memcpy(lp->data +  8 + 14, net->gateway_ethernet_addr,
+			    6);
+			memcpy(lp->data + 14 + 14, net->gateway_ipv4_addr, 4);
+
+			/*  MAC address of emulated machine:  */
+			memcpy(lp->data + 18 + 14, packet + 8, 6);
+
+			/*
+			 *  IP address of the emulated machine:  Automagically
+			 *  generated from the MAC address. :-)
+			 *
+			 *  packet+8 points to the client's mac address,
+			 *  for example 10:20:30:00:00:z0, where z is 0..15.
+			 *  10:20:30:00:00:10 results in 10.0.0.1.
+			 */
+			/*  q = (packet[8 + 3]) >> 4;  */
+			/*  q = q*15 + ((packet[8 + 4]) >> 4);  */
+			q = (packet[8 + 5]) >> 4;
+			lp->data[24 + 14] = 10;
+			lp->data[25 + 14] =  0;
+			lp->data[26 + 14] =  0;
+			lp->data[27 + 14] =  q;
+			break;
+		case 2:		/*  Reply  */
+		case 4:		/*  Reverse Reply  */
+		default:
+			debugmsg(SUBSYS_NET, "ARP", VERBOSITY_WARNING,
+	    		    "UNIMPLEMENTED request type 0x%04x", r);
+		}
+	} else {
+		if (len >= 6)
+			debugmsg(SUBSYS_NET, "ARP", VERBOSITY_WARNING,
+	   		    "UNIMPLEMENTED arp packet type: "
+	   		    "0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x ...",
+	   		    packet[0], packet[1], packet[2], packet[3],
+	   		    packet[4], packet[5]);
+	}
+}
+
+
+/*
+ *  net_ethernet_rx_avail():
+ *
+ *  Return 1 if there is a packet available for this nic, otherwise
+ *  return 0.
+ *
+ *  Appart from actually checking for incoming packets from the outside world,
+ *  this function basically works like net_ethernet_rx() but it only receives
+ *  a return value telling us whether there is a packet or not, we don't
+ *  actually get the packet.
+ */
+int net_ethernet_rx_avail(struct net *net, struct nic_data *nic)
+{
+	if (net == NULL)
+		return 0;
+
+	/*
+	 *  If we're using a tap device, check in with that and
+	 *  that's it.
+	 */
+	if (net->tapdev) {
+		net_tap_rx_avail(net);
+		return net_ethernet_rx(net, nic, NULL, NULL);
+	}
+
+	/*
+	 *  If the network is distributed across multiple emulator processes,
+	 *  then receive incoming packets from those processes.
+	 */
+	if (net->local_port != 0) {
+		struct sockaddr_in si;
+		socklen_t si_len = sizeof(si);
+		int res, i, nreceived = 0;
+		unsigned char buf[60000];
+
+		do {
+			res = recvfrom(net->local_port_socket, buf,
+			    sizeof(buf), 0, (struct sockaddr *)&si, &si_len);
+
+			if (res != -1) {
+				nreceived ++;
+
+				debugmsg(SUBSYS_NET, "RX avail", VERBOSITY_DEBUG,
+    				    "incoming DISTRIBUTED packet, %i "
+				    "bytes from %s:%d\n", res,
+				    inet_ntoa(si.sin_addr),
+				    ntohs(si.sin_port));
+
+				/*  Add the packet to all "our" NICs on this
+				    network:  */
+				for (i=0; i<net->n_nics; i++) {
+					struct ethernet_packet_link *lp;
+					lp = net_allocate_ethernet_packet_link(
+					    net, net->nic_data[i], res);
+					memcpy(lp->data, buf, res);
+				}
+			}
+		} while (res != -1 && nreceived < 100);
+	}
+
+	/*  IP protocol specific:  */
+	net_udp_rx_avail(net, nic);
+	net_tcp_rx_avail(net, nic);
+
+	return net_ethernet_rx(net, nic, NULL, NULL);
+}
+
+
+/*
+ *  net_ethernet_rx():
+ *
+ *  Receive an ethernet packet. (This means handing over an already prepared
+ *  packet from this module to a specific ethernet controller device.)
+ *
+ *  Return value is 1 if there was a packet available. *packetp and *lenp
+ *  will be set to the packet's data pointer and length, respectively, and
+ *  the packet will be removed from the linked list). If there was no packet
+ *  available, 0 is returned.
+ *
+ *  If packetp is NULL, then the search is aborted as soon as a packet with
+ *  the correct 'nic' field is found, and a 1 is returned, but as packetp
+ *  is NULL we can't return the actual packet. (This is the internal form
+ *  if net_ethernet_rx_avail().)
+ */
+int net_ethernet_rx(struct net *net, struct nic_data *nic,
+	unsigned char **packetp, int *lenp)
+{
+	struct ethernet_packet_link *lp, *prev;
+
+	if (net == NULL)
+		return 0;
+
+	/*  Find the first packet which has the right 'nic' field.  */
+
+	lp = net->first_ethernet_packet;
+	prev = NULL;
+	while (lp != NULL) {
+		if (lp->nic == nic) {
+			/*  We found a packet for this controller!  */
+			if (packetp == NULL || lenp == NULL)
+				return 1;
+
+			/*  Let's return it:  */
+			(*packetp) = lp->data;
+			(*lenp) = lp->len;
+
+			/*  Remove this link from the linked list:  */
+			if (prev == NULL)
+				net->first_ethernet_packet = lp->next;
+			else
+				prev->next = lp->next;
+
+			if (lp->next == NULL)
+				net->last_ethernet_packet = prev;
+			else
+				lp->next->prev = prev;
+
+			free(lp);
+
+			/*  ... and return successfully:  */
+			return 1;
+		}
+
+		prev = lp;
+		lp = lp->next;
+	}
+
+	/*  No packet found. :-(  */
+	return 0;
+}
+
+
+/*
+ *  net_ethernet_tx():
+ *
+ *  Transmit an ethernet packet, as seen from the emulated ethernet controller.
+ *  If the packet can be handled here, it will not necessarily be transmitted
+ *  to the outside world.
+ */
+void net_ethernet_tx(struct net *net, struct nic_data *nic,
+	unsigned char *packet, int len)
+{
+	int i, eth_type, for_the_gateway;
+
+	if (net == NULL)
+		return;
+
+	/*  Drop too small packets:  */
+	if (len < 20) {
+		debugmsg(SUBSYS_NET, "TX", VERBOSITY_WARNING,
+    		    "Warning: dropping tiny packet (%i bytes) ]\n", len);
+		return;
+	}
+
+	/*
+	 * If we're using a tap device, we send the packet that way
+	 * and that's it.
+	 */
+	if (net->tapdev) {
+		net_tap_tx(net, nic, packet, len);
+		return;
+	}
+
+	for_the_gateway = !memcmp(packet, net->gateway_ethernet_addr, 6);
+
+	/*
+	 *  Copy this packet to all other NICs on this network (except if
+	 *  it is aimed specifically at the gateway's ethernet address):
+	 */
+	if (!for_the_gateway && nic != NULL && net->n_nics > 0) {
+		for (i=0; i<net->n_nics; i++)
+			if (nic != net->nic_data[i]) {
+				struct ethernet_packet_link *lp;
+				lp = net_allocate_ethernet_packet_link(net,
+				    net->nic_data[i], len);
+
+				/*  Copy the entire packet:  */
+				memcpy(lp->data, packet, len);
+			}
+	}
+
+	/*
+	 *  If this network is distributed across multiple emulator processes,
+	 *  then transmit the packet to those other processes.
+	 */
+	if (!for_the_gateway && net->remote_nets != NULL) {
+		struct remote_net *rnp = net->remote_nets;
+		while (rnp != NULL) {
+			send_udp(&rnp->ipv4_addr, rnp->portnr, packet, len);
+			rnp = rnp->next;
+		}
+	}
+
+
+	/*
+	 *  The code below simulates the behaviour of a "NAT"-style gateway.
+	 *
+	 *  Packets that are not destined for the gateway are dropped first:
+	 *  (DHCP packets are let through, though.)
+	 */
+
+	if (!for_the_gateway && packet[0] != 0xff &&
+	    !(packet[0] == 0x00 && packet[5] == 0x00))
+		return;
+
+	eth_type = (packet[12] << 8) + packet[13];
+
+	/*  IP:  */
+	if (eth_type == ETHERTYPE_IP) {
+		/*  Routed via the gateway?  */
+		if (for_the_gateway) {
+			net_ip(net, nic, packet, len);
+			return;
+		}
+
+		/*  Broadcast? (DHCP does this.)  */
+		if (packet[0] == 0xff && packet[1] == 0xff &&
+		    packet[2] == 0xff && packet[3] == 0xff &&
+		    packet[4] == 0xff && packet[5] == 0xff) {
+			net_ip_broadcast(net, nic, packet, len);
+			return;
+		}
+
+		if (net->n_nics < 2) {
+			debugmsg(SUBSYS_NET, "TX", VERBOSITY_WARNING,
+	    		    "IP packet not for gateway, "
+			    "and not broadcast: %02x %02x %02x %02x "
+			    "%02x %02x %02x %02x %02x "
+			    "%02x %02x %02x %02x %02x ",
+			    packet[0], packet[1], packet[2], packet[3],
+			    packet[4], packet[5], packet[6], packet[7],
+			    packet[8], packet[9],
+			    packet[10], packet[11], packet[12], packet[13]);
+		}
+		return;
+	}
+
+	/*  ARP:  */
+	if (eth_type == ETHERTYPE_ARP) {
+		if (len != 42 && len != 60)
+			debugmsg(SUBSYS_NET, "TX", VERBOSITY_WARNING,
+	    		    "unusual ARP len (%i)", len);
+		net_arp(net, nic, packet + 14, len - 14, 0);
+		return;
+	}
+
+	/*  RARP:  */
+	if (eth_type == ETHERTYPE_REVARP) {
+		net_arp(net, nic, packet + 14, len - 14, 1);
+		return;
+	}
+
+	/*  Sprite:  */
+	if (eth_type == ETHERTYPE_SPRITE) {
+		/*  TODO.  */
+		debugmsg(SUBSYS_NET, "TX", VERBOSITY_WARNING,
+		    "UNIMPLEMENTED Sprite packet");
+		return;
+	}
+
+	/*  IPv6:  */
+	if (eth_type == ETHERTYPE_IPV6) {
+		/*  TODO.  */
+		debugmsg(SUBSYS_NET, "TX", VERBOSITY_WARNING,
+		    "IPv6 is not yet implemented!");
+		return;
+	}
+
+	debugmsg(SUBSYS_NET, "TX", VERBOSITY_WARNING,
+	    "ethernet packet type 0x%04x not yet implemented", eth_type);
+}
+
+
+/*
+ *  parse_resolvconf():
+ *
+ *  This function parses "/etc/resolv.conf" to figure out the nameserver
+ *  and domain used by the host.
+ */
+static void parse_resolvconf(struct net *net)
+{
+	FILE *f;
+	char buf[8000];
+	size_t len;
+	int res;
+	unsigned int i, start;
+
+	/*
+	 *  This is a very ugly hack, which tries to figure out which
+	 *  nameserver the host uses by looking for the string 'nameserver'
+	 *  in /etc/resolv.conf.
+	 *
+	 *  This can later on be used for DHCP autoconfiguration.  (TODO)
+	 *
+	 *  TODO: This is hardcoded to use /etc/resolv.conf. Not all
+	 *        operating systems use that filename.
+	 *
+	 *  TODO: This is hardcoded for AF_INET (that is, IPv4).
+	 *
+	 *  TODO: This assumes that the first nameserver listed is the
+	 *        one to use.
+	 */
+	f = fopen("/etc/resolv.conf", "r");
+	if (f == NULL)
+		return;
+
+	/*  TODO: get rid of the hardcoded values  */
+	memset(buf, 0, sizeof(buf));
+	len = fread(buf, 1, sizeof(buf) - 100, f);
+	fclose(f);
+	buf[sizeof(buf) - 1] = '\0';
+
+	for (i=0; i<len; i++)
+		if (strncmp(buf+i, "nameserver", 10) == 0) {
+			char *p;
+
+			/*
+			 *  "nameserver" (1 or more whitespace)
+			 *  "x.y.z.w" (non-digit)
+			 */
+
+			/*  debug("found nameserver at offset %i\n", i);  */
+			i += 10;
+			while (i<len && (buf[i]==' ' || buf[i]=='\t'))
+				i++;
+			if (i >= len)
+				break;
+			start = i;
+
+			p = buf+start;
+			while ((*p >= '0' && *p <= '9') || *p == '.')
+				p++;
+			*p = '\0';
+
+#ifdef HAVE_INET_PTON
+			res = inet_pton(AF_INET, buf + start,
+			    &net->nameserver_ipv4);
+#else
+			res = inet_aton(buf + start, &net->nameserver_ipv4);
+#endif
+			if (res < 1)
+				break;
+
+			net->nameserver_known = 1;
+			break;
+		}
+}
+
+
+/*
+ *  net_add_nic():
+ *
+ *  Add a NIC to a network. (All NICs on a network will see each other's
+ *  packets.)
+ */
+void net_add_nic(struct net *net, struct nic_data *nic)
+{
+	if (net == NULL)
+		return;
+
+	if (nic == NULL) {
+		fprintf(stderr, "net_add_nic(): nic = NULL\n");
+		exit(1);
+	}
+
+	/*
+	 *  Set up some of the basics for this NIC.  We assume the
+	 *  device has set up all of the other fields.
+	 */
+	nic->net = net;
+	nic->promiscuous_mode = 0;
+
+	net->n_nics++;
+	CHECK_ALLOCATION(net->nic_data = (struct nic_data **)
+	    realloc(net->nic_data, sizeof(struct nic_data *) * net->n_nics));
+
+	net->nic_data[net->n_nics - 1] = nic;
+}
+
+
+/*
+ *  net_gateway_init():
+ *
+ *  This function creates a "gateway" machine (for example at IPv4 address
+ *  10.0.0.254, if the net is 10.0.0.0/8), which acts as a gateway/router/
+ *  nameserver etc.
+ */
+static void net_gateway_init(struct net *net)
+{
+	unsigned char *p = (unsigned char *) &net->netmask_ipv4;
+	uint32_t x;
+	int xl;
+
+	x = (p[0] << 24) + (p[1] << 16) + (p[2] << 8) + p[3];
+	xl = 32 - net->netmask_ipv4_len;
+	if (xl > 8)
+		xl = 8;
+	x |= ((1 << xl) - 1) & ~1;
+
+	net->gateway_ipv4_addr[0] = x >> 24;
+	net->gateway_ipv4_addr[1] = x >> 16;
+	net->gateway_ipv4_addr[2] = x >> 8;
+	net->gateway_ipv4_addr[3] = x;
+
+	net->gateway_ethernet_addr[0] = 0x60;
+	net->gateway_ethernet_addr[1] = 0x50;
+	net->gateway_ethernet_addr[2] = 0x40;
+	net->gateway_ethernet_addr[3] = 0x30;
+	net->gateway_ethernet_addr[4] = 0x20;
+	net->gateway_ethernet_addr[5] = 0x10;
+}
+
+
+/*
+ *  net_dumpinfo():
+ *
+ *  Called from the debugger's "machine" command, to print some info about
+ *  a network.
+ */
+void net_dumpinfo(struct net *net)
+{
+	int iadd = 1;
+	struct remote_net *rnp;
+
+	debugmsg(SUBSYS_NET, "", VERBOSITY_INFO, "");
+
+	debug_indentation(iadd);
+
+	if (net->tapdev) {
+		debugmsg(SUBSYS_NET, "tap", VERBOSITY_INFO,
+		    "using device %s", net->tapdev);
+		debug_indentation(-iadd);
+		return;
+	}
+
+	debugmsg(SUBSYS_NET, "simulated network", VERBOSITY_INFO, "");
+
+	debug_indentation(iadd);
+
+	net_debugaddr(&net->netmask_ipv4, NET_ADDR_IPV4);
+	debug("/%i", net->netmask_ipv4_len);
+
+	debug(" (max outgoing: TCP=%i, UDP=%i)\n",
+	    MAX_TCP_CONNECTIONS, MAX_UDP_CONNECTIONS);
+
+	debug("gateway+nameserver: ");
+	net_debugaddr(&net->gateway_ipv4_addr, NET_ADDR_IPV4);
+	debug(" (");
+	net_debugaddr(&net->gateway_ethernet_addr, NET_ADDR_ETHERNET);
+	debug(")\n");
+
+	if (!net->nameserver_known) {
+		debug("(could not determine real nameserver from /etc/resolv.conf)\n");
+	} else {
+		debug("nameserver uses real nameserver ");
+		net_debugaddr(&net->nameserver_ipv4, NET_ADDR_IPV4);
+		debug("\n");
+	}
+
+	rnp = net->remote_nets;
+	if (net->local_port != 0)
+		debug("distributed network: local port = %i\n",
+		    net->local_port);
+	debug_indentation(iadd);
+	while (rnp != NULL) {
+		debug("remote \"%s\": ", rnp->name);
+		net_debugaddr(&rnp->ipv4_addr, NET_ADDR_IPV4);
+		debug(" port %i\n", rnp->portnr);
+		rnp = rnp->next;
+	}
+	debug_indentation(-iadd);
+
+	debug_indentation(-iadd);
+	debug_indentation(-iadd);
+}
+
+
+/*
+ *  net_init():
+ *
+ *  This function creates a network, and returns a pointer to it.
+ *
+ *  ipv4addr should be something like "10.0.0.0", netipv4len = 8.
+ *
+ *  If n_remote is more than zero, remote should be a pointer to an array
+ *  of strings of the following format: "host:portnr".
+ *
+ *  Network settings are registered if settings_prefix is non-NULL.
+ *  (The one calling net_init() is also responsible for calling net_deinit().)
+ *
+ *  On failure, NULL is returned.
+ */
+struct net *net_init(struct emul *emul, int init_flags,
+	const char *tapdev,
+	const char *ipv4addr, int netipv4len,
+	char **remote, int n_remote, int local_port,
+	const char *settings_prefix)
+{
+	struct net *net;
+	int res;
+
+	CHECK_ALLOCATION(net = (struct net *) malloc(sizeof(struct net)));
+	memset(net, 0, sizeof(struct net));
+
+	/*  Set the back pointer:  */
+	net->emul = emul;
+
+	/*  Sane defaults:  */
+	net->timestamp = 0;
+	net->first_ethernet_packet = net->last_ethernet_packet = NULL;
+	net->tapdev = NULL;
+	net->tap_fd = -1;
+
+	/*
+	 *  If we're using a tap device, attempt to initialize it and
+	 *  none of the other stuff.
+	 */
+	if (tapdev) {
+		if (!net_tap_init(net, tapdev)) {
+			free(net);
+			return NULL;
+		}
+
+		net_dumpinfo(net);
+		return net;
+	}
+
+#ifdef HAVE_INET_PTON
+	res = inet_pton(AF_INET, ipv4addr, &net->netmask_ipv4);
+#else
+	res = inet_aton(ipv4addr, &net->netmask_ipv4);
+#endif
+	if (res < 1) {
+		fprintf(stderr, "net_init(): could not parse IPv4 address"
+		    " '%s'\n", ipv4addr);
+		free(net);
+		return NULL;
+	}
+
+	if (netipv4len < 1 || netipv4len > 30) {
+		fprintf(stderr, "net_init(): extremely weird ipv4 "
+		    "network length (%i)\n", netipv4len);
+		free(net);
+		return NULL;
+	}
+
+	net->netmask_ipv4_len = netipv4len;
+
+	net->nameserver_known = 0;
+	parse_resolvconf(net);
+
+	/*  Distributed network? Then add remote hosts:  */
+	if (local_port != 0) {
+		struct sockaddr_in si_self;
+
+		net->local_port = local_port;
+		net->local_port_socket = socket(AF_INET, SOCK_DGRAM, 0);
+		if (net->local_port_socket < 0) {
+			perror("socket");
+			free(net);
+			return NULL;
+		}
+
+		memset((char *)&si_self, 0, sizeof(si_self));
+		si_self.sin_family = AF_INET;
+		si_self.sin_port = htons(local_port);
+		si_self.sin_addr.s_addr = htonl(INADDR_ANY);
+		if (bind(net->local_port_socket, (struct sockaddr *)&si_self,
+		    sizeof(si_self)) < 0) {
+			perror("bind");
+			free(net);
+			return NULL;
+		}
+
+		/*  Set the socket to non-blocking:  */
+		res = fcntl(net->local_port_socket, F_GETFL);
+		fcntl(net->local_port_socket, F_SETFL, res | O_NONBLOCK);
+	}
+	if (n_remote != 0) {
+		struct remote_net *rnp;
+		while ((n_remote--) != 0) {
+			struct hostent *hp;
+
+			/*  debug("adding '%s'\n", remote[n_remote]);  */
+			CHECK_ALLOCATION(rnp = (struct remote_net *)
+			    malloc(sizeof(struct remote_net)));
+			memset(rnp, 0, sizeof(struct remote_net));
+
+			rnp->next = net->remote_nets;
+			net->remote_nets = rnp;
+
+			CHECK_ALLOCATION(rnp->name = strdup(remote[n_remote]));
+			if (strchr(rnp->name, ':') != NULL)
+				strchr(rnp->name, ':')[0] = '\0';
+
+			hp = gethostbyname(rnp->name);
+			if (hp == NULL) {
+				fprintf(stderr, "could not resolve '%s'\n",
+				    rnp->name);
+				free(net);
+				return NULL;
+			}
+
+			memcpy(&rnp->ipv4_addr, hp->h_addr, hp->h_length);
+			free(rnp->name);
+
+			/*  And again:  */
+			CHECK_ALLOCATION(rnp->name = strdup(remote[n_remote]));
+			if (strchr(rnp->name, ':') == NULL) {
+				fprintf(stderr, "Remote network '%s' is not "
+				    "'host:portnr'?\n", rnp->name);
+				free(net);
+				return NULL;
+			}
+
+			rnp->portnr = atoi(strchr(rnp->name, ':') + 1);
+		}
+	}
+
+	if (init_flags & NET_INIT_FLAG_GATEWAY)
+		net_gateway_init(net);
+
+	net_dumpinfo(net);
+
+	/*  This is necessary when using the real network:  */
+	signal(SIGPIPE, SIG_IGN);
+
+	return net;
+}
+
diff -Nru gxemul-0.6.2/src/net/net.cc gxemul-0.7.0+dfsg/src/net/net.cc
--- gxemul-0.6.2/src/net/net.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/net/net.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,832 +0,0 @@
-/*
- *  Copyright (C) 2004-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Emulated network.
- *
- *  (Read the README file in this directory for more details.)
- *
- *
- *  NOTE: The 'extra' argument used in many functions in this file is a pointer
- *  to something unique for each NIC (i.e. the NIC itself :-), so that if
- *  multiple NICs are emulated concurrently, they will not get packets that
- *  are meant for some other controller.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <errno.h>
-#include <sys/types.h>
-#include <sys/socket.h>
-#include <netinet/in.h>
-#include <arpa/inet.h>
-#include <netdb.h>
-#include <fcntl.h>
-#include <signal.h>
-
-#include "machine.h"
-#include "misc.h"
-#include "net.h"
-
-
-/*  #define debug fatal  */
-
-
-/*
- *  net_allocate_ethernet_packet_link():
- *
- *  This routine allocates an ethernet_packet_link struct, and adds it at
- *  the end of the packet chain.  A data buffer is allocated, and the data,
- *  extra, and len fields of the link are set.
- *
- *  Note: The data buffer is not zeroed.
- *
- *  Return value is a pointer to the link on success. It doesn't return on
- *  failure.
- */
-struct ethernet_packet_link *net_allocate_ethernet_packet_link(
-	struct net *net, void *extra, size_t len)
-{
-	struct ethernet_packet_link *lp;
-
-	CHECK_ALLOCATION(lp = (struct ethernet_packet_link *)
-	    malloc(sizeof(struct ethernet_packet_link)));
-
-	lp->len = len;
-	lp->extra = extra;
-	CHECK_ALLOCATION(lp->data = (unsigned char *) malloc(len));
-
-	lp->next = NULL;
-
-	/*  Add last in the link chain:  */
-	lp->prev = net->last_ethernet_packet;
-	if (lp->prev != NULL)
-		lp->prev->next = lp;
-	else
-		net->first_ethernet_packet = lp;
-	net->last_ethernet_packet = lp;
-
-	return lp;
-}
-
-
-/*
- *  net_arp():
- *
- *  Handle an ARP (or RARP) packet, coming from the emulated NIC.
- *
- *  An ARP packet might look like this:
- *
- *	ARP header:
- *	    ARP hardware addr family:	0001
- *	    ARP protocol addr family:	0800
- *	    ARP addr lengths:		06 04
- *	    ARP request:		0001
- *	    ARP from:			112233445566 01020304
- *	    ARP to:			000000000000 01020301
- *
- *  An ARP request with a 'to' IP value of the gateway should cause an
- *  ARP response packet to be created.
- *
- *  An ARP request with the same from and to IP addresses should be ignored.
- *  (This would be a host testing to see if there is an IP collision.)
- */
-static void net_arp(struct net *net, void *extra,
-	unsigned char *packet, int len, int reverse)
-{
-	int q;
-	int i;
-
-	/*  TODO: This debug dump assumes ethernet->IPv4 translation:  */
-	if (reverse)
-		debug("[ net: RARP: ");
-	else
-		debug("[ net: ARP: ");
-	for (i=0; i<2; i++)
-		debug("%02x", packet[i]);
-	debug(" ");
-	for (i=2; i<4; i++)
-		debug("%02x", packet[i]);
-	debug(" ");
-	debug("%02x", packet[4]);
-	debug(" ");
-	debug("%02x", packet[5]);
-	debug(" req=");
-	debug("%02x", packet[6]);	/*  Request type  */
-	debug("%02x", packet[7]);
-	debug(" from=");
-	for (i=8; i<18; i++)
-		debug("%02x", packet[i]);
-	debug(" to=");
-	for (i=18; i<28; i++)
-		debug("%02x", packet[i]);
-	debug(" ]\n");
-
-	if (packet[0] == 0x00 && packet[1] == 0x01 &&
-	    packet[2] == 0x08 && packet[3] == 0x00 &&
-	    packet[4] == 0x06 && packet[5] == 0x04) {
-		int r = (packet[6] << 8) + packet[7];
-		struct ethernet_packet_link *lp;
-
-		switch (r) {
-		case 1:		/*  Request  */
-			/*  Only create a reply if this was meant for the
-			    gateway:  */
-			if (memcmp(packet+24, net->gateway_ipv4_addr, 4) != 0)
-				break;
-
-			lp = net_allocate_ethernet_packet_link(
-			    net, extra, 60 + 14);
-
-			/*  Copy the old packet first:  */
-			memset(lp->data, 0, 60 + 14);
-			memcpy(lp->data + 14, packet, len);
-
-			/*  Add ethernet ARP header:  */
-			memcpy(lp->data + 0, lp->data + 8 + 14, 6);
-			memcpy(lp->data + 6, net->gateway_ethernet_addr, 6);
-			lp->data[12] = 0x08; lp->data[13] = 0x06;
-
-			/*  Address of the emulated machine:  */
-			memcpy(lp->data + 18 + 14, lp->data + 8 + 14, 10);
-
-			/*  Address of the gateway:  */
-			memcpy(lp->data +  8 + 14, net->gateway_ethernet_addr,
-			    6);
-			memcpy(lp->data + 14 + 14, net->gateway_ipv4_addr, 4);
-
-			/*  This is a Reply:  */
-			lp->data[6 + 14] = 0x00; lp->data[7 + 14] = 0x02;
-
-			break;
-		case 3:		/*  Reverse Request  */
-			lp = net_allocate_ethernet_packet_link(
-			    net, extra, 60 + 14);
-
-			/*  Copy the old packet first:  */
-			memset(lp->data, 0, 60 + 14);
-			memcpy(lp->data + 14, packet, len);
-
-			/*  Add ethernet RARP header:  */
-			memcpy(lp->data + 0, packet + 8, 6);
-			memcpy(lp->data + 6, net->gateway_ethernet_addr, 6);
-			lp->data[12] = 0x80; lp->data[13] = 0x35;
-
-			/*  This is a RARP reply:  */
-			lp->data[6 + 14] = 0x00; lp->data[7 + 14] = 0x04;
-
-			/*  Address of the gateway:  */
-			memcpy(lp->data +  8 + 14, net->gateway_ethernet_addr,
-			    6);
-			memcpy(lp->data + 14 + 14, net->gateway_ipv4_addr, 4);
-
-			/*  MAC address of emulated machine:  */
-			memcpy(lp->data + 18 + 14, packet + 8, 6);
-
-			/*
-			 *  IP address of the emulated machine:  Automagically
-			 *  generated from the MAC address. :-)
-			 *
-			 *  packet+8 points to the client's mac address,
-			 *  for example 10:20:30:00:00:z0, where z is 0..15.
-			 *  10:20:30:00:00:10 results in 10.0.0.1.
-			 */
-			/*  q = (packet[8 + 3]) >> 4;  */
-			/*  q = q*15 + ((packet[8 + 4]) >> 4);  */
-			q = (packet[8 + 5]) >> 4;
-			lp->data[24 + 14] = 10;
-			lp->data[25 + 14] =  0;
-			lp->data[26 + 14] =  0;
-			lp->data[27 + 14] =  q;
-			break;
-		case 2:		/*  Reply  */
-		case 4:		/*  Reverse Reply  */
-		default:
-			fatal("[ net: ARP: UNIMPLEMENTED request type "
-			    "0x%04x ]\n", r);
-		}
-	} else {
-		fatal("[ net: ARP: UNIMPLEMENTED arp packet type: ");
-		for (i=0; i<len; i++)
-			fatal("%02x", packet[i]);
-		fatal(" ]\n");
-	}
-}
-
-
-/*
- *  net_ethernet_rx_avail():
- *
- *  Return 1 if there is a packet available for this 'extra' pointer, otherwise
- *  return 0.
- *
- *  Appart from actually checking for incoming packets from the outside world,
- *  this function basically works like net_ethernet_rx() but it only receives
- *  a return value telling us whether there is a packet or not, we don't
- *  actually get the packet.
- */
-int net_ethernet_rx_avail(struct net *net, void *extra)
-{
-	if (net == NULL)
-		return 0;
-
-	/*
-	 *  If the network is distributed across multiple emulator processes,
-	 *  then receive incoming packets from those processes.
-	 */
-	if (net->local_port != 0) {
-		struct sockaddr_in si;
-		socklen_t si_len = sizeof(si);
-		int res, i, nreceived = 0;
-		unsigned char buf[60000];
-
-		do {
-			res = recvfrom(net->local_port_socket, buf,
-			    sizeof(buf), 0, (struct sockaddr *)&si, &si_len);
-
-			if (res != -1) {
-				nreceived ++;
-
-				/*  fatal("[ incoming DISTRIBUTED packet, %i "
-				    "bytes from %s:%d\n", res,
-				    inet_ntoa(si.sin_addr),
-				    ntohs(si.sin_port));  */
-
-				/*  Add the packet to all "our" NICs on this
-				    network:  */
-				for (i=0; i<net->n_nics; i++) {
-					struct ethernet_packet_link *lp;
-					lp = net_allocate_ethernet_packet_link(
-					    net, net->nic_extra[i], res);
-					memcpy(lp->data, buf, res);
-				}
-			}
-		} while (res != -1 && nreceived < 100);
-	}
-
-	/*  IP protocol specific:  */
-	net_udp_rx_avail(net, extra);
-	net_tcp_rx_avail(net, extra);
-
-	return net_ethernet_rx(net, extra, NULL, NULL);
-}
-
-
-/*
- *  net_ethernet_rx():
- *
- *  Receive an ethernet packet. (This means handing over an already prepared
- *  packet from this module to a specific ethernet controller device.)
- *
- *  Return value is 1 if there was a packet available. *packetp and *lenp
- *  will be set to the packet's data pointer and length, respectively, and
- *  the packet will be removed from the linked list). If there was no packet
- *  available, 0 is returned.
- *
- *  If packetp is NULL, then the search is aborted as soon as a packet with
- *  the correct 'extra' field is found, and a 1 is returned, but as packetp
- *  is NULL we can't return the actual packet. (This is the internal form
- *  if net_ethernet_rx_avail().)
- */
-int net_ethernet_rx(struct net *net, void *extra,
-	unsigned char **packetp, int *lenp)
-{
-	struct ethernet_packet_link *lp, *prev;
-
-	if (net == NULL)
-		return 0;
-
-	/*  Find the first packet which has the right 'extra' field.  */
-
-	lp = net->first_ethernet_packet;
-	prev = NULL;
-	while (lp != NULL) {
-		if (lp->extra == extra) {
-			/*  We found a packet for this controller!  */
-			if (packetp == NULL || lenp == NULL)
-				return 1;
-
-			/*  Let's return it:  */
-			(*packetp) = lp->data;
-			(*lenp) = lp->len;
-
-			/*  Remove this link from the linked list:  */
-			if (prev == NULL)
-				net->first_ethernet_packet = lp->next;
-			else
-				prev->next = lp->next;
-
-			if (lp->next == NULL)
-				net->last_ethernet_packet = prev;
-			else
-				lp->next->prev = prev;
-
-			free(lp);
-
-			/*  ... and return successfully:  */
-			return 1;
-		}
-
-		prev = lp;
-		lp = lp->next;
-	}
-
-	/*  No packet found. :-(  */
-	return 0;
-}
-
-
-/*
- *  net_ethernet_tx():
- *
- *  Transmit an ethernet packet, as seen from the emulated ethernet controller.
- *  If the packet can be handled here, it will not necessarily be transmitted
- *  to the outside world.
- */
-void net_ethernet_tx(struct net *net, void *extra,
-	unsigned char *packet, int len)
-{
-	int i, eth_type, for_the_gateway;
-
-	if (net == NULL)
-		return;
-
-	for_the_gateway = !memcmp(packet, net->gateway_ethernet_addr, 6);
-
-	/*  Drop too small packets:  */
-	if (len < 20) {
-		fatal("[ net_ethernet_tx: Warning: dropping tiny packet "
-		    "(%i bytes) ]\n", len);
-		return;
-	}
-
-	/*
-	 *  Copy this packet to all other NICs on this network (except if
-	 *  it is aimed specifically at the gateway's ethernet address):
-	 */
-	if (!for_the_gateway && extra != NULL && net->n_nics > 0) {
-		for (i=0; i<net->n_nics; i++)
-			if (extra != net->nic_extra[i]) {
-				struct ethernet_packet_link *lp;
-				lp = net_allocate_ethernet_packet_link(net,
-				    net->nic_extra[i], len);
-
-				/*  Copy the entire packet:  */
-				memcpy(lp->data, packet, len);
-			}
-	}
-
-	/*
-	 *  If this network is distributed across multiple emulator processes,
-	 *  then transmit the packet to those other processes.
-	 */
-	if (!for_the_gateway && net->remote_nets != NULL) {
-		struct remote_net *rnp = net->remote_nets;
-		while (rnp != NULL) {
-			send_udp(&rnp->ipv4_addr, rnp->portnr, packet, len);
-			rnp = rnp->next;
-		}
-	}
-
-
-	/*
-	 *  The code below simulates the behaviour of a "NAT"-style gateway.
-	 *
-	 *  Packets that are not destined for the gateway are dropped first:
-	 *  (DHCP packets are let through, though.)
-	 */
-
-	if (!for_the_gateway && packet[0] != 0xff && packet[0] != 0x00)
-		return;
-
-#if 0
-	fatal("[ net: ethernet: ");
-	for (i=0; i<6; i++)	fatal("%02x", packet[i]); fatal(" ");
-	for (i=6; i<12; i++)	fatal("%02x", packet[i]); fatal(" ");
-	for (i=12; i<14; i++)	fatal("%02x", packet[i]); fatal(" ");
-	for (i=14; i<len; i++)	fatal("%02x", packet[i]); fatal(" ]\n");
-#endif
-
-	eth_type = (packet[12] << 8) + packet[13];
-
-	/*  IP:  */
-	if (eth_type == ETHERTYPE_IP) {
-		/*  Routed via the gateway?  */
-		if (for_the_gateway) {
-			net_ip(net, extra, packet, len);
-			return;
-		}
-
-		/*  Broadcast? (DHCP does this.)  */
-		if (packet[0] == 0xff && packet[1] == 0xff &&
-		    packet[2] == 0xff && packet[3] == 0xff &&
-		    packet[4] == 0xff && packet[5] == 0xff) {
-			net_ip_broadcast(net, extra, packet, len);
-			return;
-		}
-
-		if (net->n_nics < 2) {
-			fatal("[ net_ethernet_tx: IP packet not for gateway, "
-			    "and not broadcast: ");
-			for (i=0; i<14; i++)
-				fatal("%02x", packet[i]);
-			fatal(" ]\n");
-		}
-		return;
-	}
-
-	/*  ARP:  */
-	if (eth_type == ETHERTYPE_ARP) {
-		if (len != 42 && len != 60)
-			fatal("[ net_ethernet_tx: WARNING! unusual "
-			    "ARP len (%i) ]\n", len);
-		net_arp(net, extra, packet + 14, len - 14, 0);
-		return;
-	}
-
-	/*  RARP:  */
-	if (eth_type == ETHERTYPE_REVARP) {
-		net_arp(net, extra, packet + 14, len - 14, 1);
-		return;
-	}
-
-	/*  Sprite:  */
-	if (eth_type == ETHERTYPE_SPRITE) {
-		/*  TODO.  */
-		fatal("[ net: TX: UNIMPLEMENTED Sprite packet ]\n");
-		return;
-	}
-
-	/*  IPv6:  */
-	if (eth_type == ETHERTYPE_IPV6) {
-		/*  TODO.  */
-		fatal("[ net_ethernet_tx: IPv6 is not implemented yet! ]\n");
-		return;
-	}
-
-	fatal("[ net_ethernet_tx: ethernet packet type 0x%04x not yet "
-	    "implemented ]\n", eth_type);
-}
-
-
-/*
- *  parse_resolvconf():
- *
- *  This function parses "/etc/resolv.conf" to figure out the nameserver
- *  and domain used by the host.
- */
-static void parse_resolvconf(struct net *net)
-{
-	FILE *f;
-	char buf[8000];
-	size_t len;
-	int res;
-	unsigned int i, start;
-
-	/*
-	 *  This is a very ugly hack, which tries to figure out which
-	 *  nameserver the host uses by looking for the string 'nameserver'
-	 *  in /etc/resolv.conf.
-	 *
-	 *  This can later on be used for DHCP autoconfiguration.  (TODO)
-	 *
-	 *  TODO: This is hardcoded to use /etc/resolv.conf. Not all
-	 *        operating systems use that filename.
-	 *
-	 *  TODO: This is hardcoded for AF_INET (that is, IPv4).
-	 *
-	 *  TODO: This assumes that the first nameserver listed is the
-	 *        one to use.
-	 */
-	f = fopen("/etc/resolv.conf", "r");
-	if (f == NULL)
-		return;
-
-	/*  TODO: get rid of the hardcoded values  */
-	memset(buf, 0, sizeof(buf));
-	len = fread(buf, 1, sizeof(buf) - 100, f);
-	fclose(f);
-	buf[sizeof(buf) - 1] = '\0';
-
-	for (i=0; i<len; i++)
-		if (strncmp(buf+i, "nameserver", 10) == 0) {
-			char *p;
-
-			/*
-			 *  "nameserver" (1 or more whitespace)
-			 *  "x.y.z.w" (non-digit)
-			 */
-
-			/*  debug("found nameserver at offset %i\n", i);  */
-			i += 10;
-			while (i<len && (buf[i]==' ' || buf[i]=='\t'))
-				i++;
-			if (i >= len)
-				break;
-			start = i;
-
-			p = buf+start;
-			while ((*p >= '0' && *p <= '9') || *p == '.')
-				p++;
-			*p = '\0';
-
-#ifdef HAVE_INET_PTON
-			res = inet_pton(AF_INET, buf + start,
-			    &net->nameserver_ipv4);
-#else
-			res = inet_aton(buf + start, &net->nameserver_ipv4);
-#endif
-			if (res < 1)
-				break;
-
-			net->nameserver_known = 1;
-			break;
-		}
-
-	for (i=0; i<len; i++)
-		if (strncmp(buf+i, "domain", 6) == 0) {
-			/*  "domain" (1 or more whitespace) domain_name  */
-			i += 6;
-			while (i<len && (buf[i]==' ' || buf[i]=='\t'))
-				i++;
-			if (i >= len)
-				break;
-
-			start = i;
-			while (i<len && buf[i]!='\n' && buf[i]!='\r')
-				i++;
-			if (i < len)
-				buf[i] = '\0';
-			/*  fatal("DOMAIN='%s'\n", buf + start);  */
-			CHECK_ALLOCATION(net->domain_name = strdup(buf+start));
-			break;
-		}
-}
-
-
-/*
- *  net_add_nic():
- *
- *  Add a NIC to a network. (All NICs on a network will see each other's
- *  packets.)
- */
-void net_add_nic(struct net *net, void *extra, unsigned char *macaddr)
-{
-	if (net == NULL)
-		return;
-
-	if (extra == NULL) {
-		fprintf(stderr, "net_add_nic(): extra = NULL\n");
-		exit(1);
-	}
-
-	net->n_nics ++;
-	CHECK_ALLOCATION(net->nic_extra = (void **)
-	    realloc(net->nic_extra, sizeof(void *) * net->n_nics));
-
-	net->nic_extra[net->n_nics - 1] = extra;
-}
-
-
-/*
- *  net_gateway_init():
- *
- *  This function creates a "gateway" machine (for example at IPv4 address
- *  10.0.0.254, if the net is 10.0.0.0/8), which acts as a gateway/router/
- *  nameserver etc.
- */
-static void net_gateway_init(struct net *net)
-{
-	unsigned char *p = (unsigned char *) &net->netmask_ipv4;
-	uint32_t x;
-	int xl;
-
-	x = (p[0] << 24) + (p[1] << 16) + (p[2] << 8) + p[3];
-	xl = 32 - net->netmask_ipv4_len;
-	if (xl > 8)
-		xl = 8;
-	x |= ((1 << xl) - 1) & ~1;
-
-	net->gateway_ipv4_addr[0] = x >> 24;
-	net->gateway_ipv4_addr[1] = x >> 16;
-	net->gateway_ipv4_addr[2] = x >> 8;
-	net->gateway_ipv4_addr[3] = x;
-
-	net->gateway_ethernet_addr[0] = 0x60;
-	net->gateway_ethernet_addr[1] = 0x50;
-	net->gateway_ethernet_addr[2] = 0x40;
-	net->gateway_ethernet_addr[3] = 0x30;
-	net->gateway_ethernet_addr[4] = 0x20;
-	net->gateway_ethernet_addr[5] = 0x10;
-}
-
-
-/*
- *  net_dumpinfo():
- *
- *  Called from the debugger's "machine" command, to print some info about
- *  a network.
- */
-void net_dumpinfo(struct net *net)
-{
-	int iadd = DEBUG_INDENTATION;
-	struct remote_net *rnp;
-
-	debug("net:\n");
-
-	debug_indentation(iadd);
-
-	debug("simulated network: ");
-	net_debugaddr(&net->netmask_ipv4, NET_ADDR_IPV4);
-	debug("/%i", net->netmask_ipv4_len);
-
-	debug(" (max outgoing: TCP=%i, UDP=%i)\n",
-	    MAX_TCP_CONNECTIONS, MAX_UDP_CONNECTIONS);
-
-	debug("simulated gateway+nameserver: ");
-	net_debugaddr(&net->gateway_ipv4_addr, NET_ADDR_IPV4);
-	debug(" (");
-	net_debugaddr(&net->gateway_ethernet_addr, NET_ADDR_ETHERNET);
-	debug(")\n");
-
-	if (!net->nameserver_known) {
-		debug("(could not determine nameserver)\n");
-	} else {
-		debug("simulated nameserver uses real nameserver ");
-		net_debugaddr(&net->nameserver_ipv4, NET_ADDR_IPV4);
-		debug("\n");
-	}
-
-	if (net->domain_name != NULL && net->domain_name[0])
-		debug("domain: %s\n", net->domain_name);
-
-	rnp = net->remote_nets;
-	if (net->local_port != 0)
-		debug("distributed network: local port = %i\n",
-		    net->local_port);
-	debug_indentation(iadd);
-	while (rnp != NULL) {
-		debug("remote \"%s\": ", rnp->name);
-		net_debugaddr(&rnp->ipv4_addr, NET_ADDR_IPV4);
-		debug(" port %i\n", rnp->portnr);
-		rnp = rnp->next;
-	}
-	debug_indentation(-iadd);
-
-	debug_indentation(-iadd);
-}
-
-
-/*
- *  net_init():
- *
- *  This function creates a network, and returns a pointer to it.
- *
- *  ipv4addr should be something like "10.0.0.0", netipv4len = 8.
- *
- *  If n_remote is more than zero, remote should be a pointer to an array
- *  of strings of the following format: "host:portnr".
- *
- *  Network settings are registered if settings_prefix is non-NULL.
- *  (The one calling net_init() is also responsible for calling net_deinit().)
- *
- *  On failure, exit() is called.
- */
-struct net *net_init(struct emul *emul, int init_flags,
-	const char *ipv4addr, int netipv4len,
-	char **remote, int n_remote, int local_port,
-	const char *settings_prefix)
-{
-	struct net *net;
-	int res;
-
-	CHECK_ALLOCATION(net = (struct net *) malloc(sizeof(struct net)));
-	memset(net, 0, sizeof(struct net));
-
-	/*  Set the back pointer:  */
-	net->emul = emul;
-
-	/*  Sane defaults:  */
-	net->timestamp = 0;
-	net->first_ethernet_packet = net->last_ethernet_packet = NULL;
-
-#ifdef HAVE_INET_PTON
-	res = inet_pton(AF_INET, ipv4addr, &net->netmask_ipv4);
-#else
-	res = inet_aton(ipv4addr, &net->netmask_ipv4);
-#endif
-	if (res < 1) {
-		fprintf(stderr, "net_init(): could not parse IPv4 address"
-		    " '%s'\n", ipv4addr);
-		exit(1);
-	}
-
-	if (netipv4len < 1 || netipv4len > 30) {
-		fprintf(stderr, "net_init(): extremely weird ipv4 "
-		    "network length (%i)\n", netipv4len);
-		exit(1);
-	}
-	net->netmask_ipv4_len = netipv4len;
-
-	net->nameserver_known = 0;
-	net->domain_name = strdup("");
-	parse_resolvconf(net);
-
-	/*  Distributed network? Then add remote hosts:  */
-	if (local_port != 0) {
-		struct sockaddr_in si_self;
-
-		net->local_port = local_port;
-		net->local_port_socket = socket(AF_INET, SOCK_DGRAM, 0);
-		if (net->local_port_socket < 0) {
-			perror("socket");
-			exit(1);
-		}
-
-		memset((char *)&si_self, 0, sizeof(si_self));
-		si_self.sin_family = AF_INET;
-		si_self.sin_port = htons(local_port);
-		si_self.sin_addr.s_addr = htonl(INADDR_ANY);
-		if (bind(net->local_port_socket, (struct sockaddr *)&si_self,
-		    sizeof(si_self)) < 0) {
-			perror("bind");
-			exit(1);
-		}
-
-		/*  Set the socket to non-blocking:  */
-		res = fcntl(net->local_port_socket, F_GETFL);
-		fcntl(net->local_port_socket, F_SETFL, res | O_NONBLOCK);
-	}
-	if (n_remote != 0) {
-		struct remote_net *rnp;
-		while ((n_remote--) != 0) {
-			struct hostent *hp;
-
-			/*  debug("adding '%s'\n", remote[n_remote]);  */
-			CHECK_ALLOCATION(rnp = (struct remote_net *)
-			    malloc(sizeof(struct remote_net)));
-			memset(rnp, 0, sizeof(struct remote_net));
-
-			rnp->next = net->remote_nets;
-			net->remote_nets = rnp;
-
-			CHECK_ALLOCATION(rnp->name = strdup(remote[n_remote]));
-			if (strchr(rnp->name, ':') != NULL)
-				strchr(rnp->name, ':')[0] = '\0';
-
-			hp = gethostbyname(rnp->name);
-			if (hp == NULL) {
-				fprintf(stderr, "could not resolve '%s'\n",
-				    rnp->name);
-				exit(1);
-			}
-			memcpy(&rnp->ipv4_addr, hp->h_addr, hp->h_length);
-			free(rnp->name);
-
-			/*  And again:  */
-			CHECK_ALLOCATION(rnp->name = strdup(remote[n_remote]));
-			if (strchr(rnp->name, ':') == NULL) {
-				fprintf(stderr, "Remote network '%s' is not "
-				    "'host:portnr'?\n", rnp->name);
-				exit(1);
-			}
-			rnp->portnr = atoi(strchr(rnp->name, ':') + 1);
-		}
-	}
-
-	if (init_flags & NET_INIT_FLAG_GATEWAY)
-		net_gateway_init(net);
-
-	net_dumpinfo(net);
-
-	/*  This is necessary when using the real network:  */
-	signal(SIGPIPE, SIG_IGN);
-
-	return net;
-}
-
diff -Nru gxemul-0.6.2/src/net/net_ether.c gxemul-0.7.0+dfsg/src/net/net_ether.c
--- gxemul-0.6.2/src/net/net_ether.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/net/net_ether.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,143 @@
+/*  
+ *  Copyright (C) 2020 Jason R. Thorpe.  All rights reserved.
+ * 
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *      
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ */
+
+/*
+ *  Common Ethernet support routines.
+ */
+
+#include <sys/types.h>
+#include <string.h>
+
+#include "misc.h"
+#include "net.h"
+
+
+/*
+ *  net_ether_eq():
+ *
+ *  Compare two Ethernet addresses for equality.
+ */
+int net_ether_eq(const uint8_t *a1, const uint8_t *a2)
+{
+
+	return a1[5] == a2[5] &&
+	       a1[4] == a2[4] &&
+	       a1[3] == a2[3] &&
+	       a1[2] == a2[2] &&
+	       a1[1] == a2[1] &&
+	       a1[0] == a2[0];
+}
+
+
+/*
+ *  net_ether_broadcast():
+ *
+ *  Returns 1 if the specified destination address is the Ethernet
+ *  broadcast address.
+ */
+int net_ether_broadcast(const uint8_t *a)
+{
+	static const uint8_t ether_broadcast[6] =
+	    { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+
+	return net_ether_eq(a, ether_broadcast);
+}
+
+
+/*
+ *  net_ether_multicast():
+ *
+ *  Returns 1 if the specfied destination address is an Ethernet
+ *  multicast address.
+ *
+ *  Note that this also matches Ethernet broadcast, which is just
+ *  a special case of multicast.
+ */
+int net_ether_multicast(const uint8_t *a)
+{
+	return (*a & 0x01);
+}
+
+
+/*
+ * Copyright (c) 1982, 1989, 1993
+ *      The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *      @(#)if_ethersubr.c      8.2 (Berkeley) 4/4/96
+ */
+
+
+/*
+ *  net_ether_crc32_le():
+ *
+ *  Fast table-driven little-endian Ethernet CRC generator.
+ */
+uint32_t net_ether_crc32_le(const uint8_t *buf, size_t len)
+{
+	static const uint32_t crctab[] = {
+		0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac,
+		0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c,
+		0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c,
+		0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c
+	};
+	uint32_t crc;
+	size_t i;
+
+	crc = 0xffffffffU;	/* initial value */
+
+	for (i = 0; i < len; i++) {
+		crc ^= buf[i];
+		crc = (crc >> 4) ^ crctab[crc & 0xf];
+		crc = (crc >> 4) ^ crctab[crc & 0xf];
+	}
+
+	return crc;
+}
diff -Nru gxemul-0.6.2/src/net/net_ip.c gxemul-0.7.0+dfsg/src/net/net_ip.c
--- gxemul-0.6.2/src/net/net_ip.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/net/net_ip.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1586 @@
+/*
+ *  Copyright (C) 2004-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Internet Protocol related networking stuff.
+ */
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/socket.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <errno.h>
+#include <fcntl.h>
+
+#include "misc.h"
+#include "net.h"
+
+
+/*  #define debug fatal  */
+static int net_ip_debug = 0;	// replace by debugmsg(....)
+
+
+
+/*
+ *  net_ip_checksum():
+ *
+ *  Fill in an IP header checksum. (This works for ICMP too.)
+ *  chksumoffset should be 10 for IP headers, and len = 20.
+ *  For ICMP packets, chksumoffset = 2 and len = length of the ICMP packet.
+ */
+void net_ip_checksum(unsigned char *ip_header, int chksumoffset, int len)
+{
+	int i;
+	uint32_t sum = 0;
+
+	for (i=0; i<len; i+=2)
+		if (i != chksumoffset) {
+			uint16_t w = (ip_header[i] << 8) + ip_header[i+1];
+			sum += w;
+			while (sum > 65535) {
+				int to_add = sum >> 16;
+				sum = (sum & 0xffff) + to_add;
+			}
+		}
+
+	sum ^= 0xffff;
+	ip_header[chksumoffset + 0] = sum >> 8;
+	ip_header[chksumoffset + 1] = sum & 0xff;
+}
+
+
+/*
+ *  net_ip_tcp_checksum():
+ *
+ *  Fill in a TCP header checksum. This differs slightly from the IP
+ *  checksum. The checksum is calculated on a pseudo header, the actual
+ *  TCP header, and the data.  This is what the pseudo header looks like:
+ *
+ *	uint32_t srcaddr;
+ *	uint32_t dstaddr;
+ *	uint16_t protocol; (= 6 for tcp)
+ *	uint16_t tcp_len;
+ *
+ *  tcp_len is length of header PLUS data.  The psedo header is created
+ *  internally here, and does not need to be supplied by the caller.
+ */
+void net_ip_tcp_checksum(unsigned char *tcp_header, int chksumoffset,
+	int tcp_len, unsigned char *srcaddr, unsigned char *dstaddr,
+	int udpflag)
+{
+	int i, pad = 0;
+	unsigned char pseudoh[12];
+	uint32_t sum = 0;
+
+	memcpy(pseudoh + 0, srcaddr, 4);
+	memcpy(pseudoh + 4, dstaddr, 4);
+	pseudoh[8] = 0x00;
+	pseudoh[9] = udpflag? 17 : 6;
+	pseudoh[10] = tcp_len >> 8;
+	pseudoh[11] = tcp_len & 255;
+
+	for (i=0; i<12; i+=2) {
+		uint16_t w = (pseudoh[i] << 8) + pseudoh[i+1];
+		sum += w;
+		while (sum > 65535) {
+			int to_add = sum >> 16;
+			sum = (sum & 0xffff) + to_add;
+		}
+	}
+
+	if (tcp_len & 1) {
+		tcp_len ++;
+		pad = 1;
+	}
+
+	for (i=0; i<tcp_len; i+=2)
+		if (i != chksumoffset) {
+			uint16_t w;
+			if (!pad || i < tcp_len-2)
+				w = (tcp_header[i] << 8) + tcp_header[i+1];
+			else
+				w = (tcp_header[i] << 8) + 0x00;
+			sum += w;
+			while (sum > 65535) {
+				int to_add = sum >> 16;
+				sum = (sum & 0xffff) + to_add;
+			}
+		}
+
+	sum ^= 0xffff;
+	tcp_header[chksumoffset + 0] = sum >> 8;
+	tcp_header[chksumoffset + 1] = sum & 0xff;
+}
+
+
+/*
+ *  net_ip_icmp():
+ *
+ *  Handle an ICMP packet.
+ *
+ *  The IP header (at offset 14) could look something like
+ *
+ *	ver=45 tos=00 len=0054 id=001a ofs=0000 ttl=ff p=01 sum=a87e
+ *	src=0a000005 dst=03050607
+ *
+ *  and the ICMP specific data (beginning at offset 34):
+ *
+ *	type=08 code=00 chksum=b8bf
+ *	000c0008d5cee94089190c0008090a0b
+ *	0c0d0e0f101112131415161718191a1b
+ *	1c1d1e1f202122232425262728292a2b
+ *	2c2d2e2f3031323334353637
+ */
+static void net_ip_icmp(struct net *net, struct nic_data *nic,
+	unsigned char *packet, int len)
+{
+	int type;
+	struct ethernet_packet_link *lp;
+
+	type = packet[34];
+
+	switch (type) {
+	case 8:	/*  ECHO request  */
+		debugmsg(SUBSYS_NET, "ICMP", VERBOSITY_DEBUG, "ECHO request");
+
+		lp = net_allocate_ethernet_packet_link(net, nic, len);
+
+		/*  Copy the old packet first:  */
+		memcpy(lp->data + 12, packet + 12, len - 12);
+
+		/*  Switch to and from ethernet addresses:  */
+		memcpy(lp->data + 0, packet + 6, 6);
+		memcpy(lp->data + 6, packet + 0, 6);
+
+		/*  Switch to and from IP addresses:  */
+		memcpy(lp->data + 26, packet + 30, 4);
+		memcpy(lp->data + 30, packet + 26, 4);
+
+		/*  Change from echo REQUEST to echo REPLY:  */
+		lp->data[34] = 0x00;
+
+		/*  Decrease the TTL to a low value:  */
+		lp->data[22] = 2;
+
+		/*  Recalculate ICMP checksum:  */
+		net_ip_checksum(lp->data + 34, 2, len - 34);
+
+		/*  Recalculate IP header checksum:  */
+		net_ip_checksum(lp->data + 14, 10, 20);
+
+		break;
+	default:
+		debugmsg(SUBSYS_NET, "ICMP", VERBOSITY_WARNING, "type %i not yet implemented", type);
+	}
+}
+
+
+/*
+ *  tcp_closeconnection():
+ *
+ *  Helper function which closes down a TCP connection completely.
+ */
+static void tcp_closeconnection(struct net *net, int con_id)
+{
+	close(net->tcp_connections[con_id].socket);
+	net->tcp_connections[con_id].state = TCP_OUTSIDE_DISCONNECTED;
+	net->tcp_connections[con_id].in_use = 0;
+	net->tcp_connections[con_id].incoming_buf_len = 0;
+}
+
+
+/*
+ *  net_ip_tcp_connectionreply():
+ *
+ *  When changing from state _TRYINGTOCONNECT to _CONNECTED, then this
+ *  function should be called with connecting set to 1.
+ *
+ *  To send a generic ack reply, set connecting to 0.
+ *
+ *  To send data (PSH), set data to non-NULL and datalen to the length.
+ *
+ *  This creates an ethernet packet for the guest OS with an ACK to the
+ *  initial SYN packet.
+ */
+void net_ip_tcp_connectionreply(struct net *net, struct nic_data *nic,
+	int con_id, int connecting, unsigned char *data, int datalen, int rst)
+{
+	struct ethernet_packet_link *lp;
+	int tcp_length, ip_len, option_len = 20;
+
+	if (connecting)
+		net->tcp_connections[con_id].outside_acknr =
+		    net->tcp_connections[con_id].inside_seqnr + 1;
+
+	net->tcp_connections[con_id].tcp_id ++;
+	tcp_length = 20 + option_len + datalen;
+	ip_len = 20 + tcp_length;
+	lp = net_allocate_ethernet_packet_link(net, nic, 14 + ip_len);
+
+	/*  Ethernet header:  */
+	memcpy(lp->data + 0, net->tcp_connections[con_id].ethernet_address, 6);
+	memcpy(lp->data + 6, net->gateway_ethernet_addr, 6);
+	lp->data[12] = 0x08;	/*  IP = 0x0800  */
+	lp->data[13] = 0x00;
+
+	/*  IP header:  */
+	lp->data[14] = 0x45;	/*  ver  */
+	lp->data[15] = 0x10;	/*  tos  */
+	lp->data[16] = ip_len >> 8;
+	lp->data[17] = ip_len & 0xff;
+	lp->data[18] = net->tcp_connections[con_id].tcp_id >> 8;
+	lp->data[19] = net->tcp_connections[con_id].tcp_id & 0xff;
+	lp->data[20] = 0x40;	/*  don't fragment  */
+	lp->data[21] = 0x00;
+	lp->data[22] = 0x40;	/*  ttl  */
+	lp->data[23] = 6;	/*  p = TCP  */
+	memcpy(lp->data + 26, net->tcp_connections[con_id].
+	    outside_ip_address, 4);
+	memcpy(lp->data + 30, net->tcp_connections[con_id].
+	    inside_ip_address, 4);
+	net_ip_checksum(lp->data + 14, 10, 20);
+
+	/*  TCP header and options at offset 34:  */
+	lp->data[34] = net->tcp_connections[con_id].outside_tcp_port >> 8;
+	lp->data[35] = net->tcp_connections[con_id].outside_tcp_port & 0xff;
+	lp->data[36] = net->tcp_connections[con_id].inside_tcp_port >> 8;
+	lp->data[37] = net->tcp_connections[con_id].inside_tcp_port & 0xff;
+	lp->data[38] = (net->tcp_connections[con_id].
+	    outside_seqnr >> 24) & 0xff;
+	lp->data[39] = (net->tcp_connections[con_id].
+	    outside_seqnr >> 16) & 0xff;
+	lp->data[40] = (net->tcp_connections[con_id].
+	    outside_seqnr >>  8) & 0xff;
+	lp->data[41] = net->tcp_connections[con_id].
+	    outside_seqnr & 0xff;
+	lp->data[42] = (net->tcp_connections[con_id].
+	    outside_acknr >> 24) & 0xff;
+	lp->data[43] = (net->tcp_connections[con_id].
+	    outside_acknr >> 16) & 0xff;
+	lp->data[44] = (net->tcp_connections[con_id].
+	    outside_acknr >>  8) & 0xff;
+	lp->data[45] = net->tcp_connections[con_id].outside_acknr & 0xff;
+
+	/*  Control  */
+	lp->data[46] = (option_len + 20) / 4 * 0x10;
+	lp->data[47] = 0x10;	/*  ACK  */
+	if (connecting)
+		lp->data[47] |= 0x02;	/*  SYN  */
+	if (net->tcp_connections[con_id].state == TCP_OUTSIDE_CONNECTED)
+		lp->data[47] |= 0x08;	/*  PSH  */
+	if (rst)
+		lp->data[47] |= 0x04;	/*  RST  */
+	if (net->tcp_connections[con_id].state >= TCP_OUTSIDE_DISCONNECTED)
+		lp->data[47] |= 0x01;	/*  FIN  */
+
+	/*  Window  */
+	lp->data[48] = 0x10;
+	lp->data[49] = 0x00;
+
+	/*  no urgent ptr  */
+
+	/*  options  */
+	/*  TODO:  HAHA, this is ugly  */
+	lp->data[54] = 0x02;
+	lp->data[55] = 0x04;
+	lp->data[56] = 0x05;
+	lp->data[57] = 0xb4;
+	lp->data[58] = 0x01;
+	lp->data[59] = 0x03;
+	lp->data[60] = 0x03;
+	lp->data[61] = 0x00;
+	lp->data[62] = 0x01;
+	lp->data[63] = 0x01;
+	lp->data[64] = 0x08;
+	lp->data[65] = 0x0a;
+	lp->data[66] = (net->timestamp >> 24) & 0xff;
+	lp->data[67] = (net->timestamp >> 16) & 0xff;
+	lp->data[68] = (net->timestamp >> 8) & 0xff;
+	lp->data[69] = net->timestamp & 0xff;
+	lp->data[70] = (net->tcp_connections[con_id].
+	    inside_timestamp >> 24) & 0xff;
+	lp->data[71] = (net->tcp_connections[con_id].
+	    inside_timestamp >> 16) & 0xff;
+	lp->data[72] = (net->tcp_connections[con_id].
+	    inside_timestamp >> 8) & 0xff;
+	lp->data[73] = net->tcp_connections[con_id].
+	    inside_timestamp & 0xff;
+
+	/*  data:  */
+	if (data != NULL) {
+		memcpy(lp->data + 74, data, datalen);
+		net->tcp_connections[con_id].outside_seqnr += datalen;
+	}
+
+	/*  Checksum:  */
+	net_ip_tcp_checksum(lp->data + 34, 16, tcp_length,
+	    lp->data + 26, lp->data + 30, 0);
+
+	if (net_ip_debug) {
+		fatal("[ net_ip_tcp_connectionreply(%i): ", connecting);
+		for (int i=0; i<ip_len+14; i++)
+			fatal("%02x", lp->data[i]);
+		fatal(" ]\n");
+	}
+
+	if (connecting)
+		net->tcp_connections[con_id].outside_seqnr ++;
+}
+
+
+/*
+ *  net_ip_tcp():
+ *
+ *  Handle a TCP packet comming from the emulated OS.
+ *
+ *  The IP header (at offset 14) could look something like
+ *
+ *	ver=45 tos=00 len=003c id=0006 ofs=0000 ttl=40 p=11 sum=b798
+ *	src=0a000001 dst=c1abcdef
+ *
+ *  TCP header, at offset 34:
+ *
+ *	srcport=fffe dstport=0015 seqnr=af419a1d acknr=00000000
+ *	control=a002 window=4000 checksum=fe58 urgent=0000
+ *	and then "options and padding" and then data.
+ *	(020405b4010303000101080a0000000000000000)
+ *
+ *  See the following URLs for good descriptions of TCP:
+ *
+ *	http://www.networksorcery.com/enp/protocol/tcp.htm
+ *	http://www.tcpipguide.com/free/t_TCPIPTransmissionControlProtocolTCP.htm
+ */
+static void net_ip_tcp(struct net *net, struct nic_data *nic,
+	unsigned char *packet, int len)
+{
+	int con_id, free_con_id, i, res;
+	int srcport, dstport, data_offset, window, checksum, urgptr;
+	int syn, ack, psh, rst, urg, fin;
+	uint32_t seqnr, acknr;
+	struct sockaddr_in remote_ip;
+	fd_set rfds;
+	struct timeval tv;
+	int send_ofs;
+
+	if (net_ip_debug) {
+		fatal("[ net: TCP: ");
+		for (i=0; i<26; i++)
+			fatal("%02x", packet[i]);
+		fatal(" ");
+	}
+
+	srcport = (packet[34] << 8) + packet[35];
+	dstport = (packet[36] << 8) + packet[37];
+
+	seqnr   = (packet[38] << 24) + (packet[39] << 16)
+		+ (packet[40] << 8) + packet[41];
+	acknr   = (packet[42] << 24) + (packet[43] << 16)
+		+ (packet[44] << 8) + packet[45];
+
+	if (net_ip_debug)
+		fatal("%i.%i.%i.%i:%i -> %i.%i.%i.%i:%i, seqnr=%lli acknr=%lli ",
+		    packet[26], packet[27], packet[28], packet[29], srcport,
+		    packet[30], packet[31], packet[32], packet[33], dstport,
+		    (long long)seqnr, (long long)acknr);
+
+	data_offset = (packet[46] >> 4) * 4 + 34;
+	/*  data_offset is now data offset within packet :-)  */
+
+	urg = packet[47] & 32;
+	ack = packet[47] & 16;
+	psh = packet[47] &  8;
+	rst = packet[47] &  4;
+	syn = packet[47] &  2;
+	fin = packet[47] &  1;
+	window   = (packet[48] << 8) + packet[49];
+	checksum = (packet[50] << 8) + packet[51];
+	urgptr   = (packet[52] << 8) + packet[53];
+
+	if (net_ip_debug) {
+		fatal(urg? "URG " : "");
+		fatal(ack? "ACK " : "");
+		fatal(psh? "PSH " : "");
+		fatal(rst? "RST " : "");
+		fatal(syn? "SYN " : "");
+		fatal(fin? "FIN " : "");
+
+		fatal("window=0x%04x checksum=0x%04x urgptr=0x%04x ", window, checksum, urgptr);
+
+		fatal("options=");
+		for (i=34+20; i<data_offset; i++)
+			fatal("%02x", packet[i]);
+
+		fatal(" data=");
+		for (i=data_offset; i<len; i++)
+			fatal("%02x", packet[i]);
+
+		fatal(" ]\n");
+	}
+
+	net_ip_tcp_checksum(packet + 34, 16, len - 34,
+		packet + 26, packet + 30, 0);
+	if (packet[50] * 256 + packet[51] != checksum) {
+		debug("TCP: dropping packet because of checksum mismatch "
+		    "(0x%04x != 0x%04x)\n", packet[50] * 256 + packet[51],
+		    checksum);
+
+		return;
+	}
+
+	/*  Does this packet belong to a current connection?  */
+	con_id = free_con_id = -1;
+	for (i=0; i<MAX_TCP_CONNECTIONS; i++) {
+		if (!net->tcp_connections[i].in_use)
+			free_con_id = i;
+		if (net->tcp_connections[i].in_use &&
+		    net->tcp_connections[i].inside_tcp_port == srcport &&
+		    net->tcp_connections[i].outside_tcp_port == dstport &&
+		    memcmp(net->tcp_connections[i].inside_ip_address,
+			packet + 26, 4) == 0 &&
+		    memcmp(net->tcp_connections[i].outside_ip_address,
+			packet + 30, 4) == 0) {
+			con_id = i;
+			break;
+		}
+	}
+
+	/*
+	 *  Unknown connection, and not SYN? Then drop the packet.
+	 *  TODO:  Send back RST?
+	 */
+	if (con_id < 0 && !syn) {
+		debug("[ net: TCP: dropping packet from unknown connection,"
+		    " %i.%i.%i.%i:%i -> %i.%i.%i.%i:%i %s%s%s%s%s]\n",
+		    packet[26], packet[27], packet[28], packet[29], srcport,
+		    packet[30], packet[31], packet[32], packet[33], dstport,
+		    fin? "FIN ": "", syn? "SYN ": "", ack? "ACK ": "",
+		    psh? "PSH ": "", rst? "RST ": "");
+		return;
+	}
+
+	/*  Known connection, and SYN? Then ignore the packet.  */
+	if (con_id >= 0 && syn) {
+		debug("[ net: TCP: ignoring redundant SYN packet from known"
+		    " connection, %i.%i.%i.%i:%i -> %i.%i.%i.%i:%i ]\n",
+		    packet[26], packet[27], packet[28], packet[29], srcport,
+		    packet[30], packet[31], packet[32], packet[33], dstport);
+		return;
+	}
+
+	/*
+	 *  A new outgoing connection?
+	 */
+	if (con_id < 0 && syn) {
+		debug("[ net: TCP: new outgoing connection, %i.%i.%i.%i:%i"
+		    " -> %i.%i.%i.%i:%i ]\n",
+		    packet[26], packet[27], packet[28], packet[29], srcport,
+		    packet[30], packet[31], packet[32], packet[33], dstport);
+
+		/*  Find a free connection id to use:  */
+		if (free_con_id < 0) {
+#if 1
+			/*
+			 *  TODO:  Reuse the oldest one currently in use, or
+			 *  just drop the new connection attempt? Drop for now.
+			 */
+			fatal("[ TOO MANY TCP CONNECTIONS IN USE! "
+			    "Increase MAX_TCP_CONNECTIONS! ]\n");
+			return;
+#else
+			int i;
+			int64_t oldest = net->
+			    tcp_connections[0].last_used_timestamp;
+			free_con_id = 0;
+
+			fatal("[ NO FREE TCP SLOTS, REUSING OLDEST ONE ]\n");
+			for (i=0; i<MAX_TCP_CONNECTIONS; i++)
+				if (net->tcp_connections[i].
+				    last_used_timestamp < oldest) {
+					oldest = net->tcp_connections[i].
+					    last_used_timestamp;
+					free_con_id = i;
+				}
+			tcp_closeconnection(net, free_con_id);
+#endif
+		}
+
+		con_id = free_con_id;
+		memset(&net->tcp_connections[con_id], 0,
+		    sizeof(struct tcp_connection));
+
+		memcpy(net->tcp_connections[con_id].ethernet_address,
+		    packet + 6, 6);
+		memcpy(net->tcp_connections[con_id].inside_ip_address,
+		    packet + 26, 4);
+		net->tcp_connections[con_id].inside_tcp_port = srcport;
+		memcpy(net->tcp_connections[con_id].outside_ip_address,
+		    packet + 30, 4);
+		net->tcp_connections[con_id].outside_tcp_port = dstport;
+
+		net->tcp_connections[con_id].socket =
+		    socket(AF_INET, SOCK_STREAM, 0);
+		if (net->tcp_connections[con_id].socket < 0) {
+			fatal("[ net: TCP: socket() returned %i ]\n",
+			    net->tcp_connections[con_id].socket);
+			return;
+		}
+
+		debug("[ new tcp outgoing socket=%i ]\n",
+		    net->tcp_connections[con_id].socket);
+
+		net->tcp_connections[con_id].in_use = 1;
+
+		/*  Set the socket to non-blocking:  */
+		res = fcntl(net->tcp_connections[con_id].socket, F_GETFL);
+		fcntl(net->tcp_connections[con_id].socket, F_SETFL,
+		    res | O_NONBLOCK);
+
+		remote_ip.sin_family = AF_INET;
+		memcpy((unsigned char *)&remote_ip.sin_addr,
+		    net->tcp_connections[con_id].outside_ip_address, 4);
+		remote_ip.sin_port = htons(
+		    net->tcp_connections[con_id].outside_tcp_port);
+
+		res = connect(net->tcp_connections[con_id].socket,
+		    (struct sockaddr *)&remote_ip, sizeof(remote_ip));
+
+		/*  connect can return -1, and errno = EINPROGRESS
+		    as we might not have connected right away.  */
+
+		net->tcp_connections[con_id].state =
+		    TCP_OUTSIDE_TRYINGTOCONNECT;
+
+		net->tcp_connections[con_id].outside_acknr = 0;
+		net->tcp_connections[con_id].outside_seqnr =
+		    ((random() & 0xffff) << 16) + (random() & 0xffff);
+	}
+
+	if (rst) {
+		debug("[ 'rst': disconnecting TCP connection %i ]\n", con_id);
+		net_ip_tcp_connectionreply(net, nic, con_id, 0, NULL, 0, 1);
+		tcp_closeconnection(net, con_id);
+		return;
+	}
+
+	if (ack && net->tcp_connections[con_id].state
+	    == TCP_OUTSIDE_DISCONNECTED2) {
+		debug("[ 'ack': guestOS's final termination of TCP "
+		    "connection %i ]\n", con_id);
+
+		/*  Send an RST?  (TODO, this is wrong...)  */
+		net_ip_tcp_connectionreply(net, nic, con_id, 0, NULL, 0, 1);
+
+		/*  ... and forget about this connection:  */
+		tcp_closeconnection(net, con_id);
+		return;
+	}
+
+	if (fin && net->tcp_connections[con_id].state
+	    == TCP_OUTSIDE_DISCONNECTED) {
+		debug("[ 'fin': response to outside's disconnection of "
+		    "TCP connection %i ]\n", con_id);
+
+		/*  Send an ACK:  */
+		net->tcp_connections[con_id].state = TCP_OUTSIDE_CONNECTED;
+		net_ip_tcp_connectionreply(net, nic, con_id, 0, NULL, 0, 0);
+		net->tcp_connections[con_id].state = TCP_OUTSIDE_DISCONNECTED2;
+		return;
+	}
+
+	if (fin) {
+		debug("[ 'fin': guestOS disconnecting TCP connection %i ]\n",
+		    con_id);
+
+		/*  Send ACK:  */
+		net_ip_tcp_connectionreply(net, nic, con_id, 0, NULL, 0, 0);
+		net->tcp_connections[con_id].state = TCP_OUTSIDE_DISCONNECTED2;
+
+		/*  Return and send FIN:  */
+		goto ret;
+	}
+
+	if (ack) {
+debug("ACK %i bytes, inside_acknr=%u outside_seqnr=%u\n",
+ net->tcp_connections[con_id].incoming_buf_len,
+ net->tcp_connections[con_id].inside_acknr,
+ net->tcp_connections[con_id].outside_seqnr);
+		net->tcp_connections[con_id].inside_acknr = acknr;
+		if (net->tcp_connections[con_id].inside_acknr ==
+		    net->tcp_connections[con_id].outside_seqnr &&
+		    net->tcp_connections[con_id].incoming_buf_len != 0) {
+debug("  all acked\n");
+			net->tcp_connections[con_id].incoming_buf_len = 0;
+		}
+	}
+
+	net->tcp_connections[con_id].inside_seqnr = seqnr;
+
+	/*  TODO: This is hardcoded for a specific NetBSD packet:  */
+	if (packet[34 + 30] == 0x08 && packet[34 + 31] == 0x0a)
+		net->tcp_connections[con_id].inside_timestamp =
+		    (packet[34 + 32 + 0] << 24) +
+		    (packet[34 + 32 + 1] << 16) +
+		    (packet[34 + 32 + 2] <<  8) +
+		    (packet[34 + 32 + 3] <<  0);
+
+
+	net->timestamp ++;
+	net->tcp_connections[con_id].last_used_timestamp = net->timestamp;
+
+
+	if (net->tcp_connections[con_id].state != TCP_OUTSIDE_CONNECTED) {
+		debug("[ not connected to outside ]\n");
+		return;
+	}
+
+
+	if (data_offset >= len)
+		return;
+
+
+	/*
+	 *  We are here if this is a known connection, and data is to be
+	 *  transmitted to the outside world.
+	 */
+
+	send_ofs = data_offset;
+	send_ofs += ((int32_t)net->tcp_connections[con_id].outside_acknr
+	    - (int32_t)seqnr);
+#if 1
+	debug("[ %i bytes of tcp data to be sent, beginning at seqnr %u, ",
+	    len - data_offset, seqnr);
+	debug("outside is at acknr %u ==> %i actual bytes to be sent ]\n",
+	    net->tcp_connections[con_id].outside_acknr, len - send_ofs);
+#endif
+
+	/*  Drop outgoing packet if the guest OS' seqnr is not
+	    the same as we have acked. (We have missed something, perhaps.)  */
+	if (seqnr != net->tcp_connections[con_id].outside_acknr) {
+		debug("!! outgoing TCP packet dropped (seqnr = %u, "
+		    "outside_acknr = %u)\n", seqnr,
+		    net->tcp_connections[con_id].outside_acknr);
+		goto ret;
+	}
+
+	if (len - send_ofs > 0) {
+		/*  Is the socket available for output?  */
+		FD_ZERO(&rfds);		/*  write  */
+		FD_SET(net->tcp_connections[con_id].socket, &rfds);
+		tv.tv_sec = tv.tv_usec = 0;
+		errno = 0;
+		res = select(net->tcp_connections[con_id].socket+1,
+		    NULL, &rfds, NULL, &tv);
+		if (res < 1) {
+			net->tcp_connections[con_id].state =
+			    TCP_OUTSIDE_DISCONNECTED;
+			debug("[ TCP: disconnect on select for writing ]\n");
+			goto ret;
+		}
+
+		res = write(net->tcp_connections[con_id].socket,
+		    packet + send_ofs, len - send_ofs);
+
+		if (res > 0) {
+			net->tcp_connections[con_id].outside_acknr += res;
+		} else if (errno == EAGAIN) {
+			/*  Just ignore this attempt.  */
+			return;
+		} else {
+			debug("[ error writing %i bytes to TCP connection %i:"
+			    " errno = %i ]\n", len - send_ofs, con_id, errno);
+			net->tcp_connections[con_id].state =
+			    TCP_OUTSIDE_DISCONNECTED;
+			debug("[ TCP: disconnect on write() ]\n");
+			goto ret;
+		}
+	}
+
+ret:
+	/*  Send an ACK (or FIN) to the guest OS:  */
+	net_ip_tcp_connectionreply(net, nic, con_id, 0, NULL, 0, 0);
+}
+
+
+/*
+ *  net_ip_udp():
+ *
+ *  Handle a UDP packet.
+ *
+ *  (See http://www.networksorcery.com/enp/protocol/udp.htm.)
+ *
+ *  The IP header (at offset 14) could look something like
+ *
+ *	ver=45 tos=00 len=003c id=0006 ofs=0000 ttl=40 p=11 sum=b798
+ *	src=0a000001 dst=c1abcdef
+ *
+ *  and the UDP data (beginning at offset 34):
+ *
+ *	srcport=fffc dstport=0035 length=0028 chksum=76b6
+ *	43e20100000100000000000003667470066e6574627364036f726700001c0001
+ */
+static void net_ip_udp(struct net *net, struct nic_data *nic,
+	unsigned char *packet, int len)
+{
+	int con_id, free_con_id, i, srcport, dstport, udp_len;
+	ssize_t res;
+	struct sockaddr_in remote_ip;
+
+	if ((packet[20] & 0x3f) != 0) {
+		fatal("[ net_ip_udp(): WARNING! fragmented UDP "
+		    "packet, TODO ]\n");
+		return;
+	}
+
+	srcport = (packet[34] << 8) + packet[35];
+	dstport = (packet[36] << 8) + packet[37];
+	udp_len = (packet[38] << 8) + packet[39];
+	/*  chksum at offset 40 and 41  */
+
+	debug("[ net: UDP: ");
+	debug("srcport=%i dstport=%i len=%i ", srcport, dstport, udp_len);
+	for (i=42; i<len; i++) {
+		if (packet[i] >= ' ' && packet[i] < 127)
+			debug("%c", packet[i]);
+		else
+			debug("[%02x]", packet[i]);
+	}
+	debug(" ]\n");
+
+	/*  Is this "connection" new, or a currently ongoing one?  */
+	con_id = free_con_id = -1;
+	for (i=0; i<MAX_UDP_CONNECTIONS; i++) {
+		if (!net->udp_connections[i].in_use)
+			free_con_id = i;
+		if (net->udp_connections[i].in_use &&
+		    net->udp_connections[i].inside_udp_port == srcport &&
+		    net->udp_connections[i].outside_udp_port == dstport &&
+		    memcmp(net->udp_connections[i].inside_ip_address,
+			packet + 26, 4) == 0 &&
+		    memcmp(net->udp_connections[i].outside_ip_address,
+			packet + 30, 4) == 0) {
+			con_id = i;
+			break;
+		}
+	}
+
+	debug("&& UDP connection is ");
+	if (con_id >= 0)
+		debug("ONGOING");
+	else {
+		debug("NEW");
+		if (free_con_id < 0) {
+			int64_t oldest = net->
+			    udp_connections[0].last_used_timestamp;
+			free_con_id = 0;
+
+			debug(", NO FREE SLOTS, REUSING OLDEST ONE");
+			for (int j=0; j<MAX_UDP_CONNECTIONS; j++)
+				if (net->udp_connections[j].last_used_timestamp < oldest) {
+					oldest = net->udp_connections[j].last_used_timestamp;
+					free_con_id = j;
+				}
+
+			close(net->udp_connections[free_con_id].socket);
+		}
+		con_id = free_con_id;
+		memset(&net->udp_connections[con_id], 0,
+		    sizeof(struct udp_connection));
+
+		memcpy(net->udp_connections[con_id].ethernet_address,
+		    packet + 6, 6);
+		memcpy(net->udp_connections[con_id].inside_ip_address,
+		    packet + 26, 4);
+		net->udp_connections[con_id].inside_udp_port = srcport;
+		memcpy(net->udp_connections[con_id].outside_ip_address,
+		    packet + 30, 4);
+		net->udp_connections[con_id].outside_udp_port = dstport;
+
+		net->udp_connections[con_id].socket = socket(AF_INET,
+		    SOCK_DGRAM, 0);
+		if (net->udp_connections[con_id].socket < 0) {
+			fatal("[ net: UDP: socket() returned %i ]\n",
+			    net->udp_connections[con_id].socket);
+			return;
+		}
+
+		debug(" {socket=%i}", net->udp_connections[con_id].socket);
+
+		net->udp_connections[con_id].in_use = 1;
+
+		/*  Set the socket to non-blocking:  */
+		res = fcntl(net->udp_connections[con_id].socket, F_GETFL);
+		fcntl(net->udp_connections[con_id].socket, F_SETFL,
+		    res | O_NONBLOCK);
+	}
+
+	debug(", connection id %i\n", con_id);
+
+	net->timestamp ++;
+	net->udp_connections[con_id].last_used_timestamp = net->timestamp;
+
+	remote_ip.sin_family = AF_INET;
+	memcpy((unsigned char *)&remote_ip.sin_addr,
+	    net->udp_connections[con_id].outside_ip_address, 4);
+
+	/*
+	 *  Special case for the nameserver:  If a UDP packet is sent to
+	 *  the gateway, it will be forwarded to the nameserver, if it is
+	 *  known.
+	 */
+	if (net->nameserver_known &&
+	    memcmp(net->udp_connections[con_id].outside_ip_address,
+	    &net->gateway_ipv4_addr[0], 4) == 0) {
+		memcpy((unsigned char *)&remote_ip.sin_addr,
+		    &net->nameserver_ipv4, 4);
+		net->udp_connections[con_id].fake_ns = 1;
+	}
+
+	remote_ip.sin_port = htons(
+	    net->udp_connections[con_id].outside_udp_port);
+
+	res = sendto(net->udp_connections[con_id].socket, packet + 42,
+	    len - 42, 0, (const struct sockaddr *)&remote_ip,
+	    sizeof(remote_ip));
+
+	if (res != len-42)
+		debug("[ net: UDP: unable to send %i bytes ]\n", len-42);
+	else
+		debug("[ net: UDP: OK!!! ]\n");
+}
+
+
+/*
+ *  net_ip():
+ *
+ *  Handle an IP packet, coming from the emulated NIC.
+ */
+void net_ip(struct net *net, struct nic_data *nic, unsigned char *packet,
+	int len)
+{
+	int i;
+
+	if (ENOUGH_VERBOSITY(SUBSYS_NET, VERBOSITY_DEBUG)) {
+		char s[2000];
+		
+		snprintf(s, sizeof(s), "ver=%02x ", packet[14]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "tos=%02x ", packet[15]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "len=%02x%02x ", packet[16], packet[17]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "id=%02x%02x ",  packet[18], packet[19]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "ofs=%02x%02x ", packet[20], packet[21]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "ttl=%02x ", packet[22]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "p=%02x ", packet[23]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "sum=%02x%02x ", packet[24], packet[25]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "src=%02x%02x%02x%02x ",
+		    packet[26], packet[27], packet[28], packet[29]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "dst=%02x%02x%02x%02x ",
+		    packet[30], packet[31], packet[32], packet[33]);
+		for (i=34; i<len; i++) {
+			if (strlen(s) > sizeof(s) - 5)
+				break;
+			snprintf(s+strlen(s), sizeof(s)-strlen(s), "%02x", packet[i]);
+		}
+
+		debugmsg(SUBSYS_NET, "IP", VERBOSITY_DEBUG, "%s", s);
+	}
+
+	/*  Cut off overflowing tail data:  */
+	if (len > 14 + packet[16]*256 + packet[17])
+		len = 14 + packet[16]*256 + packet[17];
+
+	if (packet[14] == 0x45) {
+		/*  IPv4:  */
+		switch (packet[23]) {
+		case 1:	/*  ICMP  */
+			net_ip_icmp(net, nic, packet, len);
+			break;
+		case 6:	/*  TCP  */
+			net_ip_tcp(net, nic, packet, len);
+			break;
+		case 17:/*  UDP  */
+			net_ip_udp(net, nic, packet, len);
+			break;
+		default:debugmsg(SUBSYS_NET, "IP", VERBOSITY_WARNING,
+			    "UNIMPLEMENTED protocol %i",
+			    packet[23]);
+		}
+	} else {
+		debugmsg(SUBSYS_NET, "IP", VERBOSITY_WARNING,
+		    "UNIMPLEMENTED ip version, first byte = 0x%02x",
+		    packet[14]);
+	}
+}
+
+
+/*
+ *  net_ip_broadcast_dhcp():
+ *
+ *  Handle an IPv4 DHCP broadcast packet, coming from the emulated NIC.
+ *
+ *  Read http://tools.ietf.org/html/rfc2131 for details on DHCP.
+ *  (And http://users.telenet.be/mydotcom/library/network/dhcp.htm.)
+ */
+static void net_ip_broadcast_dhcp(struct net *net, struct nic_data *nic,
+	unsigned char *packet, int len)
+{
+	struct ethernet_packet_link *lp;
+        int i, reply_len;
+
+	if (ENOUGH_VERBOSITY(SUBSYS_NET, VERBOSITY_DEBUG)) {
+		char s[4000];
+		
+		snprintf(s, sizeof(s), "ver=%02x ", packet[14]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "tos=%02x ", packet[15]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "len=%02x%02x ", packet[16], packet[17]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "id=%02x%02x ",  packet[18], packet[19]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "ofs=%02x%02x ", packet[20], packet[21]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "ttl=%02x ", packet[22]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "p=%02x ", packet[23]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "sum=%02x%02x ", packet[24], packet[25]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "src=%02x%02x%02x%02x ",
+		    packet[26], packet[27], packet[28], packet[29]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "dst=%02x%02x%02x%02x ",
+		    packet[30], packet[31], packet[32], packet[33]);
+		for (i=34; i<len; i++) {
+			if (strlen(s) > sizeof(s) - 5)
+				break;
+			snprintf(s+strlen(s), sizeof(s)-strlen(s), "%02x", packet[i]);
+		}
+
+		debugmsg(SUBSYS_NET, "IPv4 DHCP", VERBOSITY_DEBUG, "%s", s);
+	}
+
+	if (len < 34 + 8 + 236) {
+		debugmsg(SUBSYS_NET, "IPv4 DHCP", VERBOSITY_ERROR, "packet too short? len=%i", len);
+		return;
+	}
+
+	/*
+	 *  UDP data (at offset 34):
+	 *
+	 *  srcport=0044 dstport=0043 length=0134 chksum=a973
+	 *  data = 01010600d116d276000000000000000000000000000000
+	 *         0000000000102030405060...0000...638253633501...000
+	 */
+
+#if 0
+	fatal("op=%02x ", packet[42]);
+	fatal("htype=%02x ", packet[43]);
+	fatal("hlen=%02x ", packet[44]);
+	fatal("hops=%02x ", packet[45]);
+	fatal("xid=%02x%02x%02x%02x ", packet[46], packet[47],
+	    packet[48], packet[49]);
+	fatal("secs=%02x%02x ", packet[50], packet[51]);
+	fatal("flags=%02x%02x ", packet[52], packet[53]);
+	fatal("ciaddr=%02x%02x%02x%02x ", packet[54], packet[55],
+	    packet[56], packet[57]);
+	fatal("yiaddr=%02x%02x%02x%02x ", packet[58], packet[59],
+	    packet[60], packet[61]);
+	fatal("siaddr=%02x%02x%02x%02x ", packet[62], packet[63],
+	    packet[64], packet[65]);
+	fatal("giaddr=%02x%02x%02x%02x ", packet[66], packet[67],
+	    packet[68], packet[69]);
+	fatal("chaddr=");
+	for (i=70; i<70+16; i++)
+		fatal("%02x", packet[i]);
+	/*
+	   |                          sname   (64)                         |
+	   |                          file    (128)                        |
+	 */
+	fatal(" ]\n");
+#endif
+
+        reply_len = 307;
+        lp = net_allocate_ethernet_packet_link(net, nic, reply_len);
+
+        /*  From old packet, copy everything before options field:  */
+        memcpy(lp->data, packet, 278);
+
+	/*  We are sending to the client, from the gateway:  */
+	memcpy(lp->data + 0, packet + 6, 6);
+	memcpy(lp->data + 6, net->gateway_ethernet_addr, 6);
+
+	/*  Set IP length:  */
+	lp->data[16] = (reply_len - 14) >> 8;
+	lp->data[17] = (reply_len - 14) & 0xff;
+
+        /*  Set IP addresses:  */
+	memcpy(lp->data + 26, &net->gateway_ipv4_addr[0], 4);
+	lp->data[30] = 0xff;
+	lp->data[31] = 0xff;
+	lp->data[32] = 0xff;
+	lp->data[33] = 0xff;
+
+	/*  Switch src and dst ports:  */
+	memcpy(lp->data + 34, packet + 36, 2);
+	memcpy(lp->data + 36, packet + 34, 2);
+
+	/*  Set UDP length:  */
+	lp->data[38] = (reply_len - 34) >> 8;
+	lp->data[39] = (reply_len - 34) & 0xff;
+
+	/*  Client's (yiaddr) IPv4 address:  */
+	lp->data[58] = 10;
+	lp->data[59] = 0;
+	lp->data[60] = 0;
+	lp->data[61] = 1;	/*  TODO  */
+
+	/*  Server's IPv4 address:  (giaddr)  */
+	memcpy(lp->data + 66, &net->gateway_ipv4_addr[0], 4);
+
+	/*  This is a Reply:  */
+	lp->data[42] = 0x02;
+
+	snprintf((char *)lp->data + 70+16+64, 8, "gxemul");
+
+	/*  Options field at offset 278:  */
+	lp->data[278] = 99;
+	lp->data[279] = 130;
+	lp->data[280] = 83;
+	lp->data[281] = 99;
+
+	/*  DHCP options, http://tools.ietf.org/html/rfc1533  */
+	lp->data[282] = 1; /* subnet mask */
+	lp->data[283] = 4;
+	lp->data[284] = 255;
+	lp->data[285] = 0;
+	lp->data[286] = 0;
+	lp->data[287] = 0;
+	lp->data[288] = 3; /* router */
+	lp->data[289] = 4;
+	memcpy(lp->data + 290, &net->gateway_ipv4_addr[0], 4);
+	lp->data[294] = 6; /* domain name server */
+	lp->data[295] = 4;
+	memcpy(lp->data + 296, &net->gateway_ipv4_addr[0], 4);
+	lp->data[300] = 54; /* server identifier */
+	lp->data[301] = 4;
+	memcpy(lp->data + 302, &net->gateway_ipv4_addr[0], 4);
+	lp->data[306] = 255; /* end */
+
+	/*  Recalculate IP header checksum:  */
+	net_ip_checksum(lp->data + 14, 10, 20);
+
+	/*  ... and the UDP checksum:  */
+        net_ip_tcp_checksum(lp->data + 34, 6, reply_len - 34,
+	    lp->data + 26, lp->data + 30, 1);
+
+	if (ENOUGH_VERBOSITY(SUBSYS_NET, VERBOSITY_DEBUG)) {
+		char s[4000];
+		s[0] = '\0';
+
+		packet = lp->data;
+
+		for (i=0; i<14; i++) {
+			if (strlen(s) > sizeof(s) - 5)
+				break;
+			snprintf(s+strlen(s), sizeof(s)-strlen(s), "%02x", packet[i]);
+		}
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "ver=%02x ", packet[14]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "tos=%02x ", packet[15]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "len=%02x%02x ", packet[16], packet[17]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "id=%02x%02x ",  packet[18], packet[19]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "ofs=%02x%02x ", packet[20], packet[21]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "ttl=%02x ", packet[22]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "p=%02x ", packet[23]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "sum=%02x%02x ", packet[24], packet[25]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "src=%02x%02x%02x%02x ",
+		    packet[26], packet[27], packet[28], packet[29]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "dst=%02x%02x%02x%02x ",
+		    packet[30], packet[31], packet[32], packet[33]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "op=%02x ", packet[42]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "htype=%02x ", packet[43]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "hlen=%02x ", packet[44]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "hops=%02x ", packet[45]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "xid=%02x%02x%02x%02x ",
+			packet[46], packet[47], packet[48], packet[49]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "secs=%02x%02x ", packet[50], packet[51]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "flags=%02x%02x ", packet[52], packet[53]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "ciaddr=%02x%02x%02x%02x ",
+			packet[54], packet[55], packet[56], packet[57]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "yiaddr=%02x%02x%02x%02x ",
+			packet[58], packet[59], packet[60], packet[61]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "siaddr=%02x%02x%02x%02x ",
+			packet[62], packet[63], packet[64], packet[65]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "giaddr=%02x%02x%02x%02x ",
+			packet[66], packet[67], packet[68], packet[69]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "chaddr=");
+		for (i=70; i<70+16; i++) {
+			if (strlen(s) > sizeof(s) - 5)
+				break;
+
+			snprintf(s+strlen(s), sizeof(s)-strlen(s), "%02x", packet[i]);
+		}
+
+		debugmsg(SUBSYS_NET, "IPv4 DHCP REPLY", VERBOSITY_DEBUG, "%s", s);
+	}
+}
+
+
+/*
+ *  net_ip_broadcast():
+ *
+ *  Handle an IP broadcast packet, coming from the emulated NIC.
+ *  (This is usually a DHCP request, or similar.)
+ */
+void net_ip_broadcast(struct net *net, struct nic_data *nic,
+	unsigned char *packet, int len)
+{
+	unsigned char *p = (unsigned char *) &net->netmask_ipv4;
+	uint32_t x, y;
+	int i, xl, warning = 0, match = 0;
+
+	if (ENOUGH_VERBOSITY(SUBSYS_NET, VERBOSITY_DEBUG)) {
+		char s[4000];
+		
+		snprintf(s, sizeof(s), "ver=%02x ", packet[14]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "tos=%02x ", packet[15]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "len=%02x%02x ", packet[16], packet[17]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "id=%02x%02x ",  packet[18], packet[19]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "ofs=%02x%02x ", packet[20], packet[21]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "ttl=%02x ", packet[22]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "p=%02x ", packet[23]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "sum=%02x%02x ", packet[24], packet[25]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "src=%02x%02x%02x%02x ",
+		    packet[26], packet[27], packet[28], packet[29]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "dst=%02x%02x%02x%02x ",
+		    packet[30], packet[31], packet[32], packet[33]);
+		for (i=34; i<len; i++) {
+			if (strlen(s) > sizeof(s) - 5)
+				break;
+			snprintf(s+strlen(s), sizeof(s)-strlen(s), "%02x", packet[i]);
+		}
+
+		debugmsg(SUBSYS_NET, "ip BROADCAST", VERBOSITY_DEBUG, "%s", s);
+	}
+
+	/*  Check for 10.0.0.255 first, maybe some guest OSes think that
+	    it's a /24 network, regardless of what it actually is.  */
+	y = (packet[30] << 24) + (packet[31] << 16) +
+	    (packet[32] << 8) + packet[33];
+
+	x = (p[0] << 24) + (p[1] << 16) + (p[2] << 8) + p[3];
+	/*  Example: x = 10.0.0.0  */
+	x |= 255;
+
+	if (x == y) {
+		warning = 1;
+		match = 1;
+	}
+
+	xl = 32 - net->netmask_ipv4_len;
+	x |= (1 << xl) - 1;
+	/*  x = 10.255.255.255  */
+
+	if (x == y)
+		match = 1;
+	if (y == 0xffffffff)
+		match = 1;
+
+	if (warning)
+		fatal("[ net_ip_broadcast(): warning: broadcast to "
+		    "0x%08x, expecting broadcast to 0x%08x or "
+		    "0xffffffff ]\n", y, x);
+
+	/*  Cut off overflowing tail data:  */
+	if (len > 14 + packet[16]*256 + packet[17])
+		len = 14 + packet[16]*256 + packet[17];
+
+	/*  Check for known packets:  */
+	if (packet[14] == 0x45 &&			/*  IPv4  */
+	    packet[23] == 0x11 &&			/*  UDP  */
+	    packet[34] == 0 && packet[35] == 68 &&	/*  DHCP client  */
+	    packet[36] == 0 && packet[37] == 67) {	/*  DHCP server  */
+		net_ip_broadcast_dhcp(net, nic, packet, len);
+		return;
+	}
+
+	/*  NetBSD seems to send this during shutdown:  */
+	if (packet[14] == 0x45 &&			/*  IPv4  */
+	    packet[23] == 0x11 &&			/*  UDP  */
+	    packet[34] == 0xff && packet[35] == 0xff &&	/*  0xffff  */
+	    packet[36] == 0x00 && packet[37] == 0x6f) {	/*  ipx-in-ip  */
+		// Let's ignore for now.
+		return;
+	}
+
+	/*  Unknown packet:  */
+	if (ENOUGH_VERBOSITY(SUBSYS_NET, VERBOSITY_ERROR)) {
+		char s[4000];
+		
+		snprintf(s, sizeof(s), "ver=%02x ", packet[14]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "tos=%02x ", packet[15]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "len=%02x%02x ", packet[16], packet[17]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "id=%02x%02x ",  packet[18], packet[19]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "ofs=%02x%02x ", packet[20], packet[21]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "ttl=%02x ", packet[22]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "p=%02x ", packet[23]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "sum=%02x%02x ", packet[24], packet[25]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "src=%02x%02x%02x%02x ",
+		    packet[26], packet[27], packet[28], packet[29]);
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), "dst=%02x%02x%02x%02x ",
+		    packet[30], packet[31], packet[32], packet[33]);
+		for (i=34; i<len; i++) {
+			if (strlen(s) > sizeof(s) - 50)
+				break;
+			snprintf(s+strlen(s), sizeof(s)-strlen(s), "%02x", packet[i]);
+		}
+		snprintf(s+strlen(s), sizeof(s)-strlen(s), " (match=%i)", match);
+
+		debugmsg(SUBSYS_NET, "ip UNIMPLEMENTED BROADCAST", VERBOSITY_ERROR, "%s", s);
+	}
+}
+
+
+/*
+ *  net_udp_rx_avail():
+ *
+ *  Receive any available UDP packets (from the outside world).
+ */
+void net_udp_rx_avail(struct net *net, struct nic_data *nic)
+{
+	int received_packets_this_tick = 0;
+	int max_packets_this_tick = 200;
+	int con_id;
+
+	for (con_id=0; con_id<MAX_UDP_CONNECTIONS; con_id++) {
+		ssize_t res;
+		unsigned char buf[66000];
+		unsigned char udp_data[66008];
+		struct sockaddr_in from;
+		socklen_t from_len = sizeof(from);
+		int ip_len, udp_len;
+		struct ethernet_packet_link *lp;
+		int max_per_packet;
+		int bytes_converted = 0;
+		int this_packets_data_length;
+		int fragment_ofs = 0;
+
+		if (received_packets_this_tick > max_packets_this_tick)
+			break;
+
+		if (!net->udp_connections[con_id].in_use)
+			continue;
+
+		if (net->udp_connections[con_id].socket < 0) {
+			fatal("INTERNAL ERROR in net.c, udp socket < 0 "
+			    "but in use?\n");
+			continue;
+		}
+
+		res = recvfrom(net->udp_connections[con_id].socket, buf,
+		    sizeof(buf), 0, (struct sockaddr *)&from, &from_len);
+
+		/*  No more incoming UDP on this connection?  */
+		if (res < 0)
+			continue;
+
+		net->timestamp ++;
+		net->udp_connections[con_id].last_used_timestamp =
+		    net->timestamp;
+
+		net->udp_connections[con_id].udp_id ++;
+
+		/*
+		 *  Special case for the nameserver:  If a UDP packet is
+		 *  received from the nameserver (if the nameserver's IP is
+		 *  known), fake it so that it comes from the gateway instead.
+		 */
+		if (net->udp_connections[con_id].fake_ns)
+			memcpy(((unsigned char *)(&from))+4,
+			    &net->gateway_ipv4_addr[0], 4);
+
+		/*
+		 *  We now have a UDP packet of size 'res' which we need
+		 *  turn into one or more ethernet packets for the emulated
+		 *  operating system.  Ethernet packets are at most 1518
+		 *  bytes long. With some margin, that means we can have
+		 *  about 1500 bytes per packet.
+		 *
+		 *	Ethernet = 14 bytes
+		 *	IP = 20 bytes
+		 *	(UDP = 8 bytes + data)
+		 *
+		 *  So data can be at most max_per_packet - 34. For UDP
+		 *  fragments, each multiple should (?) be a multiple of
+		 *  8 bytes, except the last which doesn't have any such
+		 *  restriction.
+		 */
+		max_per_packet = 1500;
+
+		/*  UDP:  */
+		udp_len = res + 8;
+		/*  from[2..3] = outside_udp_port  */
+		udp_data[0] = ((unsigned char *)&from)[2];
+		udp_data[1] = ((unsigned char *)&from)[3];
+		udp_data[2] = (net->udp_connections[con_id].
+		    inside_udp_port >> 8) & 0xff;
+		udp_data[3] = net->udp_connections[con_id].
+		    inside_udp_port & 0xff;
+		udp_data[4] = udp_len >> 8;
+		udp_data[5] = udp_len & 0xff;
+		udp_data[6] = 0;
+		udp_data[7] = 0;
+		memcpy(udp_data + 8, buf, res);
+		/*
+		 *  TODO:  UDP checksum, if necessary. At least NetBSD
+		 *  and OpenBSD accept UDP packets with 0x0000 in the
+		 *  checksum field anyway.
+		 */
+
+		while (bytes_converted < udp_len) {
+			this_packets_data_length = udp_len - bytes_converted;
+
+			/*  Do we need to fragment?  */
+			if (this_packets_data_length > max_per_packet-34) {
+				this_packets_data_length =
+				    max_per_packet - 34;
+				while (this_packets_data_length & 7)
+					this_packets_data_length --;
+			}
+
+			ip_len = 20 + this_packets_data_length;
+
+			lp = net_allocate_ethernet_packet_link(net, nic,
+			    14 + 20 + this_packets_data_length);
+
+			/*  Ethernet header:  */
+			memcpy(lp->data + 0, net->udp_connections[con_id].
+			    ethernet_address, 6);
+			memcpy(lp->data + 6, net->gateway_ethernet_addr, 6);
+			lp->data[12] = 0x08;	/*  IP = 0x0800  */
+			lp->data[13] = 0x00;
+
+			/*  IP header:  */
+			lp->data[14] = 0x45;	/*  ver  */
+			lp->data[15] = 0x00;	/*  tos  */
+			lp->data[16] = ip_len >> 8;
+			lp->data[17] = ip_len & 0xff;
+			lp->data[18] = net->udp_connections[con_id].udp_id >> 8;
+			lp->data[19] = net->udp_connections[con_id].udp_id
+			    & 0xff;
+			lp->data[20] = (fragment_ofs >> 8);
+			if (bytes_converted + this_packets_data_length
+			    < udp_len)
+				lp->data[20] |= 0x20;	/*  More fragments  */
+			lp->data[21] = fragment_ofs & 0xff;
+			lp->data[22] = 0x40;	/*  ttl  */
+			lp->data[23] = 17;	/*  p = UDP  */
+			lp->data[26] = ((unsigned char *)&from)[4];
+			lp->data[27] = ((unsigned char *)&from)[5];
+			lp->data[28] = ((unsigned char *)&from)[6];
+			lp->data[29] = ((unsigned char *)&from)[7];
+			memcpy(lp->data + 30, net->udp_connections[con_id].
+			    inside_ip_address, 4);
+			net_ip_checksum(lp->data + 14, 10, 20);
+
+			memcpy(lp->data+34, udp_data + bytes_converted,
+			    this_packets_data_length);
+
+			bytes_converted += this_packets_data_length;
+			fragment_ofs = bytes_converted / 8;
+
+			received_packets_this_tick ++;
+		}
+
+		/*  This makes sure we check this connection AGAIN
+		    for more incoming UDP packets, before moving to the
+		    next connection:  */
+		con_id --;
+	}
+}
+
+
+/*
+ *  net_tcp_rx_avail():
+ *
+ *  Receive any available TCP packets (from the outside world).
+ */
+void net_tcp_rx_avail(struct net *net, struct nic_data *nic)
+{
+	int received_packets_this_tick = 0;
+	int max_packets_this_tick = 200;
+	int con_id;
+
+	for (con_id=0; con_id<MAX_TCP_CONNECTIONS; con_id++) {
+		unsigned char buf[66000];
+		ssize_t res, res2;
+		fd_set rfds;
+		struct timeval tv;
+
+		if (received_packets_this_tick > max_packets_this_tick)
+			break;
+
+		if (!net->tcp_connections[con_id].in_use)
+			continue;
+
+		if (net->tcp_connections[con_id].socket < 0) {
+			fatal("INTERNAL ERROR in net.c, tcp socket < 0"
+			    " but in use?\n");
+			continue;
+		}
+
+		if (net->tcp_connections[con_id].incoming_buf == NULL)
+			CHECK_ALLOCATION(net->tcp_connections[con_id].
+			    incoming_buf = (unsigned char *) malloc(TCP_INCOMING_BUF_LEN));
+
+		if (net->tcp_connections[con_id].state >=
+		    TCP_OUTSIDE_DISCONNECTED)
+			continue;
+
+		/*  Is the socket available for output?  */
+		FD_ZERO(&rfds);		/*  write  */
+		FD_SET(net->tcp_connections[con_id].socket, &rfds);
+		tv.tv_sec = tv.tv_usec = 0;
+		errno = 0;
+		res = select(net->tcp_connections[con_id].socket+1,
+		    NULL, &rfds, NULL, &tv);
+
+		if (errno == ECONNREFUSED) {
+			fatal("[ ECONNREFUSED: TODO ]\n");
+			net->tcp_connections[con_id].state =
+			    TCP_OUTSIDE_DISCONNECTED;
+			fatal("CHANGING TO TCP_OUTSIDE_DISCONNECTED "
+			    "(refused connection)\n");
+			continue;
+		}
+
+		if (errno == ETIMEDOUT) {
+			fatal("[ ETIMEDOUT: TODO ]\n");
+			/*  TODO  */
+			net->tcp_connections[con_id].state =
+			    TCP_OUTSIDE_DISCONNECTED;
+			fatal("CHANGING TO TCP_OUTSIDE_DISCONNECTED "
+			    "(timeout)\n");
+			continue;
+		}
+
+		if (net->tcp_connections[con_id].state ==
+		    TCP_OUTSIDE_TRYINGTOCONNECT && res > 0) {
+			net->tcp_connections[con_id].state =
+			    TCP_OUTSIDE_CONNECTED;
+			debug("CHANGING TO TCP_OUTSIDE_CONNECTED\n");
+			net_ip_tcp_connectionreply(net, nic, con_id, 1,
+			    NULL, 0, 0);
+		}
+
+		if (net->tcp_connections[con_id].state ==
+		    TCP_OUTSIDE_CONNECTED && res < 1) {
+			continue;
+		}
+
+		/*
+		 *  Does this connection have unacknowledged data?  Then, if
+		 *  enough number of rounds have passed, try to resend it using
+		 *  the old value of seqnr.
+		 */
+		if (net->tcp_connections[con_id].incoming_buf_len != 0) {
+			net->tcp_connections[con_id].incoming_buf_rounds ++;
+			if (net->tcp_connections[con_id].incoming_buf_rounds >
+			    10000) {
+				debug("  at seqnr %u but backing back to %u,"
+				    " resending %i bytes\n",
+				    net->tcp_connections[con_id].outside_seqnr,
+				    net->tcp_connections[con_id].
+				    incoming_buf_seqnr,
+				    net->tcp_connections[con_id].
+				    incoming_buf_len);
+
+				net->tcp_connections[con_id].
+				    incoming_buf_rounds = 0;
+				net->tcp_connections[con_id].outside_seqnr =
+				    net->tcp_connections[con_id].
+				    incoming_buf_seqnr;
+
+				net_ip_tcp_connectionreply(net, nic, con_id,
+				    0, net->tcp_connections[con_id].
+				    incoming_buf,
+				    net->tcp_connections[con_id].
+				    incoming_buf_len, 0);
+			}
+			continue;
+		}
+
+		/*  Don't receive unless the guest OS is ready!  */
+		if (((int32_t)net->tcp_connections[con_id].outside_seqnr -
+		    (int32_t)net->tcp_connections[con_id].inside_acknr) > 0) {
+/*			fatal("YOYO 1! outside_seqnr - inside_acknr = %i\n",
+			    net->tcp_connections[con_id].outside_seqnr -
+			    net->tcp_connections[con_id].inside_acknr);  */
+			continue;
+		}
+
+		/*  Is there incoming data available on the socket?  */
+		FD_ZERO(&rfds);		/*  read  */
+		FD_SET(net->tcp_connections[con_id].socket, &rfds);
+		tv.tv_sec = tv.tv_usec = 0;
+		res2 = select(net->tcp_connections[con_id].socket+1, &rfds,
+		    NULL, NULL, &tv);
+
+		/*  No more incoming TCP data on this connection?  */
+		if (res2 < 1)
+			continue;
+
+		res = read(net->tcp_connections[con_id].socket, buf, 1400);
+		if (res > 0) {
+			/*  debug("\n -{- %lli -}-\n", (long long)res);  */
+			net->tcp_connections[con_id].incoming_buf_len = res;
+			net->tcp_connections[con_id].incoming_buf_rounds = 0;
+			net->tcp_connections[con_id].incoming_buf_seqnr = 
+			    net->tcp_connections[con_id].outside_seqnr;
+			debug("  putting %i bytes (seqnr %u) in the incoming "
+			    "buf\n", res, net->tcp_connections[con_id].
+			    incoming_buf_seqnr);
+			memcpy(net->tcp_connections[con_id].incoming_buf,
+			    buf, res);
+
+			net_ip_tcp_connectionreply(net, nic, con_id, 0,
+			    buf, res, 0);
+		} else if (res == 0) {
+			net->tcp_connections[con_id].state =
+			    TCP_OUTSIDE_DISCONNECTED;
+			debug("CHANGING TO TCP_OUTSIDE_DISCONNECTED, read"
+			    " res=0\n");
+			net_ip_tcp_connectionreply(net, nic, con_id, 0,
+			    NULL, 0, 0);
+		} else {
+			net->tcp_connections[con_id].state =
+			    TCP_OUTSIDE_DISCONNECTED;
+			fatal("CHANGING TO TCP_OUTSIDE_DISCONNECTED, "
+			    "read res<=0, errno = %i\n", errno);
+			net_ip_tcp_connectionreply(net, nic, con_id, 0,
+			    NULL, 0, 0);
+		}
+
+		net->timestamp ++;
+		net->tcp_connections[con_id].last_used_timestamp =
+		    net->timestamp;
+	}
+}
+
+
diff -Nru gxemul-0.6.2/src/net/net_ip.cc gxemul-0.7.0+dfsg/src/net/net_ip.cc
--- gxemul-0.6.2/src/net/net_ip.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/net/net_ip.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1546 +0,0 @@
-/*
- *  Copyright (C) 2004-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Internet Protocol related networking stuff.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <sys/socket.h>
-#include <sys/time.h>
-#include <sys/types.h>
-#include <errno.h>
-#include <fcntl.h>
-
-#include "misc.h"
-#include "net.h"
-
-
-/*  #define debug fatal  */
-
-
-/*
- *  net_ip_checksum():
- *
- *  Fill in an IP header checksum. (This works for ICMP too.)
- *  chksumoffset should be 10 for IP headers, and len = 20.
- *  For ICMP packets, chksumoffset = 2 and len = length of the ICMP packet.
- */
-void net_ip_checksum(unsigned char *ip_header, int chksumoffset, int len)
-{
-	int i;
-	uint32_t sum = 0;
-
-	for (i=0; i<len; i+=2)
-		if (i != chksumoffset) {
-			uint16_t w = (ip_header[i] << 8) + ip_header[i+1];
-			sum += w;
-			while (sum > 65535) {
-				int to_add = sum >> 16;
-				sum = (sum & 0xffff) + to_add;
-			}
-		}
-
-	sum ^= 0xffff;
-	ip_header[chksumoffset + 0] = sum >> 8;
-	ip_header[chksumoffset + 1] = sum & 0xff;
-}
-
-
-/*
- *  net_ip_tcp_checksum():
- *
- *  Fill in a TCP header checksum. This differs slightly from the IP
- *  checksum. The checksum is calculated on a pseudo header, the actual
- *  TCP header, and the data.  This is what the pseudo header looks like:
- *
- *	uint32_t srcaddr;
- *	uint32_t dstaddr;
- *	uint16_t protocol; (= 6 for tcp)
- *	uint16_t tcp_len;
- *
- *  tcp_len is length of header PLUS data.  The psedo header is created
- *  internally here, and does not need to be supplied by the caller.
- */
-void net_ip_tcp_checksum(unsigned char *tcp_header, int chksumoffset,
-	int tcp_len, unsigned char *srcaddr, unsigned char *dstaddr,
-	int udpflag)
-{
-	int i, pad = 0;
-	unsigned char pseudoh[12];
-	uint32_t sum = 0;
-
-	memcpy(pseudoh + 0, srcaddr, 4);
-	memcpy(pseudoh + 4, dstaddr, 4);
-	pseudoh[8] = 0x00;
-	pseudoh[9] = udpflag? 17 : 6;
-	pseudoh[10] = tcp_len >> 8;
-	pseudoh[11] = tcp_len & 255;
-
-	for (i=0; i<12; i+=2) {
-		uint16_t w = (pseudoh[i] << 8) + pseudoh[i+1];
-		sum += w;
-		while (sum > 65535) {
-			int to_add = sum >> 16;
-			sum = (sum & 0xffff) + to_add;
-		}
-	}
-
-	if (tcp_len & 1) {
-		tcp_len ++;
-		pad = 1;
-	}
-
-	for (i=0; i<tcp_len; i+=2)
-		if (i != chksumoffset) {
-			uint16_t w;
-			if (!pad || i < tcp_len-2)
-				w = (tcp_header[i] << 8) + tcp_header[i+1];
-			else
-				w = (tcp_header[i] << 8) + 0x00;
-			sum += w;
-			while (sum > 65535) {
-				int to_add = sum >> 16;
-				sum = (sum & 0xffff) + to_add;
-			}
-		}
-
-	sum ^= 0xffff;
-	tcp_header[chksumoffset + 0] = sum >> 8;
-	tcp_header[chksumoffset + 1] = sum & 0xff;
-}
-
-
-/*
- *  net_ip_icmp():
- *
- *  Handle an ICMP packet.
- *
- *  The IP header (at offset 14) could look something like
- *
- *	ver=45 tos=00 len=0054 id=001a ofs=0000 ttl=ff p=01 sum=a87e
- *	src=0a000005 dst=03050607
- *
- *  and the ICMP specific data (beginning at offset 34):
- *
- *	type=08 code=00 chksum=b8bf
- *	000c0008d5cee94089190c0008090a0b
- *	0c0d0e0f101112131415161718191a1b
- *	1c1d1e1f202122232425262728292a2b
- *	2c2d2e2f3031323334353637
- */
-static void net_ip_icmp(struct net *net, void *extra,
-	unsigned char *packet, int len)
-{
-	int type;
-	struct ethernet_packet_link *lp;
-
-	type = packet[34];
-
-	switch (type) {
-	case 8:	/*  ECHO request  */
-		debug("[ ICMP echo ]\n");
-		lp = net_allocate_ethernet_packet_link(net, extra, len);
-
-		/*  Copy the old packet first:  */
-		memcpy(lp->data + 12, packet + 12, len - 12);
-
-		/*  Switch to and from ethernet addresses:  */
-		memcpy(lp->data + 0, packet + 6, 6);
-		memcpy(lp->data + 6, packet + 0, 6);
-
-		/*  Switch to and from IP addresses:  */
-		memcpy(lp->data + 26, packet + 30, 4);
-		memcpy(lp->data + 30, packet + 26, 4);
-
-		/*  Change from echo REQUEST to echo REPLY:  */
-		lp->data[34] = 0x00;
-
-		/*  Decrease the TTL to a low value:  */
-		lp->data[22] = 2;
-
-		/*  Recalculate ICMP checksum:  */
-		net_ip_checksum(lp->data + 34, 2, len - 34);
-
-		/*  Recalculate IP header checksum:  */
-		net_ip_checksum(lp->data + 14, 10, 20);
-
-		break;
-	default:
-		fatal("[ net: ICMP type %i not yet implemented ]\n", type);
-	}
-}
-
-
-/*
- *  tcp_closeconnection():
- *
- *  Helper function which closes down a TCP connection completely.
- */
-static void tcp_closeconnection(struct net *net, int con_id)
-{
-	close(net->tcp_connections[con_id].socket);
-	net->tcp_connections[con_id].state = TCP_OUTSIDE_DISCONNECTED;
-	net->tcp_connections[con_id].in_use = 0;
-	net->tcp_connections[con_id].incoming_buf_len = 0;
-}
-
-
-/*
- *  net_ip_tcp_connectionreply():
- *
- *  When changing from state _TRYINGTOCONNECT to _CONNECTED, then this
- *  function should be called with connecting set to 1.
- *
- *  To send a generic ack reply, set connecting to 0.
- *
- *  To send data (PSH), set data to non-NULL and datalen to the length.
- *
- *  This creates an ethernet packet for the guest OS with an ACK to the
- *  initial SYN packet.
- */
-void net_ip_tcp_connectionreply(struct net *net, void *extra,
-	int con_id, int connecting, unsigned char *data, int datalen, int rst)
-{
-	struct ethernet_packet_link *lp;
-	int tcp_length, ip_len, option_len = 20;
-
-	if (connecting)
-		net->tcp_connections[con_id].outside_acknr =
-		    net->tcp_connections[con_id].inside_seqnr + 1;
-
-	net->tcp_connections[con_id].tcp_id ++;
-	tcp_length = 20 + option_len + datalen;
-	ip_len = 20 + tcp_length;
-	lp = net_allocate_ethernet_packet_link(net, extra, 14 + ip_len);
-
-	/*  Ethernet header:  */
-	memcpy(lp->data + 0, net->tcp_connections[con_id].ethernet_address, 6);
-	memcpy(lp->data + 6, net->gateway_ethernet_addr, 6);
-	lp->data[12] = 0x08;	/*  IP = 0x0800  */
-	lp->data[13] = 0x00;
-
-	/*  IP header:  */
-	lp->data[14] = 0x45;	/*  ver  */
-	lp->data[15] = 0x10;	/*  tos  */
-	lp->data[16] = ip_len >> 8;
-	lp->data[17] = ip_len & 0xff;
-	lp->data[18] = net->tcp_connections[con_id].tcp_id >> 8;
-	lp->data[19] = net->tcp_connections[con_id].tcp_id & 0xff;
-	lp->data[20] = 0x40;	/*  don't fragment  */
-	lp->data[21] = 0x00;
-	lp->data[22] = 0x40;	/*  ttl  */
-	lp->data[23] = 6;	/*  p = TCP  */
-	memcpy(lp->data + 26, net->tcp_connections[con_id].
-	    outside_ip_address, 4);
-	memcpy(lp->data + 30, net->tcp_connections[con_id].
-	    inside_ip_address, 4);
-	net_ip_checksum(lp->data + 14, 10, 20);
-
-	/*  TCP header and options at offset 34:  */
-	lp->data[34] = net->tcp_connections[con_id].outside_tcp_port >> 8;
-	lp->data[35] = net->tcp_connections[con_id].outside_tcp_port & 0xff;
-	lp->data[36] = net->tcp_connections[con_id].inside_tcp_port >> 8;
-	lp->data[37] = net->tcp_connections[con_id].inside_tcp_port & 0xff;
-	lp->data[38] = (net->tcp_connections[con_id].
-	    outside_seqnr >> 24) & 0xff;
-	lp->data[39] = (net->tcp_connections[con_id].
-	    outside_seqnr >> 16) & 0xff;
-	lp->data[40] = (net->tcp_connections[con_id].
-	    outside_seqnr >>  8) & 0xff;
-	lp->data[41] = net->tcp_connections[con_id].
-	    outside_seqnr & 0xff;
-	lp->data[42] = (net->tcp_connections[con_id].
-	    outside_acknr >> 24) & 0xff;
-	lp->data[43] = (net->tcp_connections[con_id].
-	    outside_acknr >> 16) & 0xff;
-	lp->data[44] = (net->tcp_connections[con_id].
-	    outside_acknr >>  8) & 0xff;
-	lp->data[45] = net->tcp_connections[con_id].outside_acknr & 0xff;
-
-	/*  Control  */
-	lp->data[46] = (option_len + 20) / 4 * 0x10;
-	lp->data[47] = 0x10;	/*  ACK  */
-	if (connecting)
-		lp->data[47] |= 0x02;	/*  SYN  */
-	if (net->tcp_connections[con_id].state == TCP_OUTSIDE_CONNECTED)
-		lp->data[47] |= 0x08;	/*  PSH  */
-	if (rst)
-		lp->data[47] |= 0x04;	/*  RST  */
-	if (net->tcp_connections[con_id].state >= TCP_OUTSIDE_DISCONNECTED)
-		lp->data[47] |= 0x01;	/*  FIN  */
-
-	/*  Window  */
-	lp->data[48] = 0x10;
-	lp->data[49] = 0x00;
-
-	/*  no urgent ptr  */
-
-	/*  options  */
-	/*  TODO:  HAHA, this is ugly  */
-	lp->data[54] = 0x02;
-	lp->data[55] = 0x04;
-	lp->data[56] = 0x05;
-	lp->data[57] = 0xb4;
-	lp->data[58] = 0x01;
-	lp->data[59] = 0x03;
-	lp->data[60] = 0x03;
-	lp->data[61] = 0x00;
-	lp->data[62] = 0x01;
-	lp->data[63] = 0x01;
-	lp->data[64] = 0x08;
-	lp->data[65] = 0x0a;
-	lp->data[66] = (net->timestamp >> 24) & 0xff;
-	lp->data[67] = (net->timestamp >> 16) & 0xff;
-	lp->data[68] = (net->timestamp >> 8) & 0xff;
-	lp->data[69] = net->timestamp & 0xff;
-	lp->data[70] = (net->tcp_connections[con_id].
-	    inside_timestamp >> 24) & 0xff;
-	lp->data[71] = (net->tcp_connections[con_id].
-	    inside_timestamp >> 16) & 0xff;
-	lp->data[72] = (net->tcp_connections[con_id].
-	    inside_timestamp >> 8) & 0xff;
-	lp->data[73] = net->tcp_connections[con_id].
-	    inside_timestamp & 0xff;
-
-	/*  data:  */
-	if (data != NULL) {
-		memcpy(lp->data + 74, data, datalen);
-		net->tcp_connections[con_id].outside_seqnr += datalen;
-	}
-
-	/*  Checksum:  */
-	net_ip_tcp_checksum(lp->data + 34, 16, tcp_length,
-	    lp->data + 26, lp->data + 30, 0);
-
-#if 0
-	{
-		int i;
-		fatal("[ net_ip_tcp_connectionreply(%i): ", connecting);
-		for (i=0; i<ip_len+14; i++)
-			fatal("%02x", lp->data[i]);
-		fatal(" ]\n");
-	}
-#endif
-
-	if (connecting)
-		net->tcp_connections[con_id].outside_seqnr ++;
-}
-
-
-/*
- *  net_ip_tcp():
- *
- *  Handle a TCP packet comming from the emulated OS.
- *
- *  The IP header (at offset 14) could look something like
- *
- *	ver=45 tos=00 len=003c id=0006 ofs=0000 ttl=40 p=11 sum=b798
- *	src=0a000001 dst=c1abcdef
- *
- *  TCP header, at offset 34:
- *
- *	srcport=fffe dstport=0015 seqnr=af419a1d acknr=00000000
- *	control=a002 window=4000 checksum=fe58 urgent=0000
- *	and then "options and padding" and then data.
- *	(020405b4010303000101080a0000000000000000)
- *
- *  See the following URLs for good descriptions of TCP:
- *
- *	http://www.networksorcery.com/enp/protocol/tcp.htm
- *	http://www.tcpipguide.com/free/t_TCPIPTransmissionControlProtocolTCP.htm
- */
-static void net_ip_tcp(struct net *net, void *extra,
-	unsigned char *packet, int len)
-{
-	int con_id, free_con_id, i, res;
-	int srcport, dstport, data_offset, window, checksum, urgptr;
-	int syn, ack, psh, rst, urg, fin;
-	uint32_t seqnr, acknr;
-	struct sockaddr_in remote_ip;
-	fd_set rfds;
-	struct timeval tv;
-	int send_ofs;
-
-#if 0
-	fatal("[ net: TCP: ");
-	for (i=0; i<26; i++)
-		fatal("%02x", packet[i]);
-	fatal(" ");
-#endif
-
-	srcport = (packet[34] << 8) + packet[35];
-	dstport = (packet[36] << 8) + packet[37];
-
-	seqnr   = (packet[38] << 24) + (packet[39] << 16)
-		+ (packet[40] << 8) + packet[41];
-	acknr   = (packet[42] << 24) + (packet[43] << 16)
-		+ (packet[44] << 8) + packet[45];
-
-#if 0
-	fatal("%i.%i.%i.%i:%i -> %i.%i.%i.%i:%i, seqnr=%lli acknr=%lli ",
-	    packet[26], packet[27], packet[28], packet[29], srcport,
-	    packet[30], packet[31], packet[32], packet[33], dstport,
-	    (long long)seqnr, (long long)acknr);
-#endif
-
-	data_offset = (packet[46] >> 4) * 4 + 34;
-	/*  data_offset is now data offset within packet :-)  */
-
-	urg = packet[47] & 32;
-	ack = packet[47] & 16;
-	psh = packet[47] &  8;
-	rst = packet[47] &  4;
-	syn = packet[47] &  2;
-	fin = packet[47] &  1;
-	window   = (packet[48] << 8) + packet[49];
-	checksum = (packet[50] << 8) + packet[51];
-	urgptr   = (packet[52] << 8) + packet[53];
-
-#if 0
-	fatal(urg? "URG " : "");
-	fatal(ack? "ACK " : "");
-	fatal(psh? "PSH " : "");
-	fatal(rst? "RST " : "");
-	fatal(syn? "SYN " : "");
-	fatal(fin? "FIN " : "");
-
-	fatal("window=0x%04x checksum=0x%04x urgptr=0x%04x ",
-	    window, checksum, urgptr);
-
-	fatal("options=");
-	for (i=34+20; i<data_offset; i++)
-		fatal("%02x", packet[i]);
-
-	fatal(" data=");
-	for (i=data_offset; i<len; i++)
-		fatal("%02x", packet[i]);
-
-	fatal(" ]\n");
-#endif
-
-	net_ip_tcp_checksum(packet + 34, 16, len - 34,
-		packet + 26, packet + 30, 0);
-	if (packet[50] * 256 + packet[51] != checksum) {
-		debug("TCP: dropping packet because of checksum mismatch "
-		    "(0x%04x != 0x%04x)\n", packet[50] * 256 + packet[51],
-		    checksum);
-
-		return;
-	}
-
-	/*  Does this packet belong to a current connection?  */
-	con_id = free_con_id = -1;
-	for (i=0; i<MAX_TCP_CONNECTIONS; i++) {
-		if (!net->tcp_connections[i].in_use)
-			free_con_id = i;
-		if (net->tcp_connections[i].in_use &&
-		    net->tcp_connections[i].inside_tcp_port == srcport &&
-		    net->tcp_connections[i].outside_tcp_port == dstport &&
-		    memcmp(net->tcp_connections[i].inside_ip_address,
-			packet + 26, 4) == 0 &&
-		    memcmp(net->tcp_connections[i].outside_ip_address,
-			packet + 30, 4) == 0) {
-			con_id = i;
-			break;
-		}
-	}
-
-	/*
-	 *  Unknown connection, and not SYN? Then drop the packet.
-	 *  TODO:  Send back RST?
-	 */
-	if (con_id < 0 && !syn) {
-		debug("[ net: TCP: dropping packet from unknown connection,"
-		    " %i.%i.%i.%i:%i -> %i.%i.%i.%i:%i %s%s%s%s%s]\n",
-		    packet[26], packet[27], packet[28], packet[29], srcport,
-		    packet[30], packet[31], packet[32], packet[33], dstport,
-		    fin? "FIN ": "", syn? "SYN ": "", ack? "ACK ": "",
-		    psh? "PSH ": "", rst? "RST ": "");
-		return;
-	}
-
-	/*  Known connection, and SYN? Then ignore the packet.  */
-	if (con_id >= 0 && syn) {
-		debug("[ net: TCP: ignoring redundant SYN packet from known"
-		    " connection, %i.%i.%i.%i:%i -> %i.%i.%i.%i:%i ]\n",
-		    packet[26], packet[27], packet[28], packet[29], srcport,
-		    packet[30], packet[31], packet[32], packet[33], dstport);
-		return;
-	}
-
-	/*
-	 *  A new outgoing connection?
-	 */
-	if (con_id < 0 && syn) {
-		debug("[ net: TCP: new outgoing connection, %i.%i.%i.%i:%i"
-		    " -> %i.%i.%i.%i:%i ]\n",
-		    packet[26], packet[27], packet[28], packet[29], srcport,
-		    packet[30], packet[31], packet[32], packet[33], dstport);
-
-		/*  Find a free connection id to use:  */
-		if (free_con_id < 0) {
-#if 1
-			/*
-			 *  TODO:  Reuse the oldest one currently in use, or
-			 *  just drop the new connection attempt? Drop for now.
-			 */
-			fatal("[ TOO MANY TCP CONNECTIONS IN USE! "
-			    "Increase MAX_TCP_CONNECTIONS! ]\n");
-			return;
-#else
-			int i;
-			int64_t oldest = net->
-			    tcp_connections[0].last_used_timestamp;
-			free_con_id = 0;
-
-			fatal("[ NO FREE TCP SLOTS, REUSING OLDEST ONE ]\n");
-			for (i=0; i<MAX_TCP_CONNECTIONS; i++)
-				if (net->tcp_connections[i].
-				    last_used_timestamp < oldest) {
-					oldest = net->tcp_connections[i].
-					    last_used_timestamp;
-					free_con_id = i;
-				}
-			tcp_closeconnection(net, free_con_id);
-#endif
-		}
-
-		con_id = free_con_id;
-		memset(&net->tcp_connections[con_id], 0,
-		    sizeof(struct tcp_connection));
-
-		memcpy(net->tcp_connections[con_id].ethernet_address,
-		    packet + 6, 6);
-		memcpy(net->tcp_connections[con_id].inside_ip_address,
-		    packet + 26, 4);
-		net->tcp_connections[con_id].inside_tcp_port = srcport;
-		memcpy(net->tcp_connections[con_id].outside_ip_address,
-		    packet + 30, 4);
-		net->tcp_connections[con_id].outside_tcp_port = dstport;
-
-		net->tcp_connections[con_id].socket =
-		    socket(AF_INET, SOCK_STREAM, 0);
-		if (net->tcp_connections[con_id].socket < 0) {
-			fatal("[ net: TCP: socket() returned %i ]\n",
-			    net->tcp_connections[con_id].socket);
-			return;
-		}
-
-		debug("[ new tcp outgoing socket=%i ]\n",
-		    net->tcp_connections[con_id].socket);
-
-		net->tcp_connections[con_id].in_use = 1;
-
-		/*  Set the socket to non-blocking:  */
-		res = fcntl(net->tcp_connections[con_id].socket, F_GETFL);
-		fcntl(net->tcp_connections[con_id].socket, F_SETFL,
-		    res | O_NONBLOCK);
-
-		remote_ip.sin_family = AF_INET;
-		memcpy((unsigned char *)&remote_ip.sin_addr,
-		    net->tcp_connections[con_id].outside_ip_address, 4);
-		remote_ip.sin_port = htons(
-		    net->tcp_connections[con_id].outside_tcp_port);
-
-		res = connect(net->tcp_connections[con_id].socket,
-		    (struct sockaddr *)&remote_ip, sizeof(remote_ip));
-
-		/*  connect can return -1, and errno = EINPROGRESS
-		    as we might not have connected right away.  */
-
-		net->tcp_connections[con_id].state =
-		    TCP_OUTSIDE_TRYINGTOCONNECT;
-
-		net->tcp_connections[con_id].outside_acknr = 0;
-		net->tcp_connections[con_id].outside_seqnr =
-		    ((random() & 0xffff) << 16) + (random() & 0xffff);
-	}
-
-	if (rst) {
-		debug("[ 'rst': disconnecting TCP connection %i ]\n", con_id);
-		net_ip_tcp_connectionreply(net, extra, con_id, 0, NULL, 0, 1);
-		tcp_closeconnection(net, con_id);
-		return;
-	}
-
-	if (ack && net->tcp_connections[con_id].state
-	    == TCP_OUTSIDE_DISCONNECTED2) {
-		debug("[ 'ack': guestOS's final termination of TCP "
-		    "connection %i ]\n", con_id);
-
-		/*  Send an RST?  (TODO, this is wrong...)  */
-		net_ip_tcp_connectionreply(net, extra, con_id, 0, NULL, 0, 1);
-
-		/*  ... and forget about this connection:  */
-		tcp_closeconnection(net, con_id);
-		return;
-	}
-
-	if (fin && net->tcp_connections[con_id].state
-	    == TCP_OUTSIDE_DISCONNECTED) {
-		debug("[ 'fin': response to outside's disconnection of "
-		    "TCP connection %i ]\n", con_id);
-
-		/*  Send an ACK:  */
-		net->tcp_connections[con_id].state = TCP_OUTSIDE_CONNECTED;
-		net_ip_tcp_connectionreply(net, extra, con_id, 0, NULL, 0, 0);
-		net->tcp_connections[con_id].state = TCP_OUTSIDE_DISCONNECTED2;
-		return;
-	}
-
-	if (fin) {
-		debug("[ 'fin': guestOS disconnecting TCP connection %i ]\n",
-		    con_id);
-
-		/*  Send ACK:  */
-		net_ip_tcp_connectionreply(net, extra, con_id, 0, NULL, 0, 0);
-		net->tcp_connections[con_id].state = TCP_OUTSIDE_DISCONNECTED2;
-
-		/*  Return and send FIN:  */
-		goto ret;
-	}
-
-	if (ack) {
-debug("ACK %i bytes, inside_acknr=%u outside_seqnr=%u\n",
- net->tcp_connections[con_id].incoming_buf_len,
- net->tcp_connections[con_id].inside_acknr,
- net->tcp_connections[con_id].outside_seqnr);
-		net->tcp_connections[con_id].inside_acknr = acknr;
-		if (net->tcp_connections[con_id].inside_acknr ==
-		    net->tcp_connections[con_id].outside_seqnr &&
-		    net->tcp_connections[con_id].incoming_buf_len != 0) {
-debug("  all acked\n");
-			net->tcp_connections[con_id].incoming_buf_len = 0;
-		}
-	}
-
-	net->tcp_connections[con_id].inside_seqnr = seqnr;
-
-	/*  TODO: This is hardcoded for a specific NetBSD packet:  */
-	if (packet[34 + 30] == 0x08 && packet[34 + 31] == 0x0a)
-		net->tcp_connections[con_id].inside_timestamp =
-		    (packet[34 + 32 + 0] << 24) +
-		    (packet[34 + 32 + 1] << 16) +
-		    (packet[34 + 32 + 2] <<  8) +
-		    (packet[34 + 32 + 3] <<  0);
-
-
-	net->timestamp ++;
-	net->tcp_connections[con_id].last_used_timestamp = net->timestamp;
-
-
-	if (net->tcp_connections[con_id].state != TCP_OUTSIDE_CONNECTED) {
-		debug("[ not connected to outside ]\n");
-		return;
-	}
-
-
-	if (data_offset >= len)
-		return;
-
-
-	/*
-	 *  We are here if this is a known connection, and data is to be
-	 *  transmitted to the outside world.
-	 */
-
-	send_ofs = data_offset;
-	send_ofs += ((int32_t)net->tcp_connections[con_id].outside_acknr
-	    - (int32_t)seqnr);
-#if 1
-	debug("[ %i bytes of tcp data to be sent, beginning at seqnr %u, ",
-	    len - data_offset, seqnr);
-	debug("outside is at acknr %u ==> %i actual bytes to be sent ]\n",
-	    net->tcp_connections[con_id].outside_acknr, len - send_ofs);
-#endif
-
-	/*  Drop outgoing packet if the guest OS' seqnr is not
-	    the same as we have acked. (We have missed something, perhaps.)  */
-	if (seqnr != net->tcp_connections[con_id].outside_acknr) {
-		debug("!! outgoing TCP packet dropped (seqnr = %u, "
-		    "outside_acknr = %u)\n", seqnr,
-		    net->tcp_connections[con_id].outside_acknr);
-		goto ret;
-	}
-
-	if (len - send_ofs > 0) {
-		/*  Is the socket available for output?  */
-		FD_ZERO(&rfds);		/*  write  */
-		FD_SET(net->tcp_connections[con_id].socket, &rfds);
-		tv.tv_sec = tv.tv_usec = 0;
-		errno = 0;
-		res = select(net->tcp_connections[con_id].socket+1,
-		    NULL, &rfds, NULL, &tv);
-		if (res < 1) {
-			net->tcp_connections[con_id].state =
-			    TCP_OUTSIDE_DISCONNECTED;
-			debug("[ TCP: disconnect on select for writing ]\n");
-			goto ret;
-		}
-
-		res = write(net->tcp_connections[con_id].socket,
-		    packet + send_ofs, len - send_ofs);
-
-		if (res > 0) {
-			net->tcp_connections[con_id].outside_acknr += res;
-		} else if (errno == EAGAIN) {
-			/*  Just ignore this attempt.  */
-			return;
-		} else {
-			debug("[ error writing %i bytes to TCP connection %i:"
-			    " errno = %i ]\n", len - send_ofs, con_id, errno);
-			net->tcp_connections[con_id].state =
-			    TCP_OUTSIDE_DISCONNECTED;
-			debug("[ TCP: disconnect on write() ]\n");
-			goto ret;
-		}
-	}
-
-ret:
-	/*  Send an ACK (or FIN) to the guest OS:  */
-	net_ip_tcp_connectionreply(net, extra, con_id, 0, NULL, 0, 0);
-}
-
-
-/*
- *  net_ip_udp():
- *
- *  Handle a UDP packet.
- *
- *  (See http://www.networksorcery.com/enp/protocol/udp.htm.)
- *
- *  The IP header (at offset 14) could look something like
- *
- *	ver=45 tos=00 len=003c id=0006 ofs=0000 ttl=40 p=11 sum=b798
- *	src=0a000001 dst=c1abcdef
- *
- *  and the UDP data (beginning at offset 34):
- *
- *	srcport=fffc dstport=0035 length=0028 chksum=76b6
- *	43e20100000100000000000003667470066e6574627364036f726700001c0001
- */
-static void net_ip_udp(struct net *net, void *extra,
-	unsigned char *packet, int len)
-{
-	int con_id, free_con_id, i, srcport, dstport, udp_len;
-	ssize_t res;
-	struct sockaddr_in remote_ip;
-
-	if ((packet[20] & 0x3f) != 0) {
-		fatal("[ net_ip_udp(): WARNING! fragmented UDP "
-		    "packet, TODO ]\n");
-		return;
-	}
-
-	srcport = (packet[34] << 8) + packet[35];
-	dstport = (packet[36] << 8) + packet[37];
-	udp_len = (packet[38] << 8) + packet[39];
-	/*  chksum at offset 40 and 41  */
-
-	debug("[ net: UDP: ");
-	debug("srcport=%i dstport=%i len=%i ", srcport, dstport, udp_len);
-	for (i=42; i<len; i++) {
-		if (packet[i] >= ' ' && packet[i] < 127)
-			debug("%c", packet[i]);
-		else
-			debug("[%02x]", packet[i]);
-	}
-	debug(" ]\n");
-
-	/*  Is this "connection" new, or a currently ongoing one?  */
-	con_id = free_con_id = -1;
-	for (i=0; i<MAX_UDP_CONNECTIONS; i++) {
-		if (!net->udp_connections[i].in_use)
-			free_con_id = i;
-		if (net->udp_connections[i].in_use &&
-		    net->udp_connections[i].inside_udp_port == srcport &&
-		    net->udp_connections[i].outside_udp_port == dstport &&
-		    memcmp(net->udp_connections[i].inside_ip_address,
-			packet + 26, 4) == 0 &&
-		    memcmp(net->udp_connections[i].outside_ip_address,
-			packet + 30, 4) == 0) {
-			con_id = i;
-			break;
-		}
-	}
-
-	debug("&& UDP connection is ");
-	if (con_id >= 0)
-		debug("ONGOING");
-	else {
-		debug("NEW");
-		if (free_con_id < 0) {
-			int64_t oldest = net->
-			    udp_connections[0].last_used_timestamp;
-			free_con_id = 0;
-
-			debug(", NO FREE SLOTS, REUSING OLDEST ONE");
-			for (int j=0; j<MAX_UDP_CONNECTIONS; j++)
-				if (net->udp_connections[j].last_used_timestamp < oldest) {
-					oldest = net->udp_connections[j].last_used_timestamp;
-					free_con_id = j;
-				}
-
-			close(net->udp_connections[free_con_id].socket);
-		}
-		con_id = free_con_id;
-		memset(&net->udp_connections[con_id], 0,
-		    sizeof(struct udp_connection));
-
-		memcpy(net->udp_connections[con_id].ethernet_address,
-		    packet + 6, 6);
-		memcpy(net->udp_connections[con_id].inside_ip_address,
-		    packet + 26, 4);
-		net->udp_connections[con_id].inside_udp_port = srcport;
-		memcpy(net->udp_connections[con_id].outside_ip_address,
-		    packet + 30, 4);
-		net->udp_connections[con_id].outside_udp_port = dstport;
-
-		net->udp_connections[con_id].socket = socket(AF_INET,
-		    SOCK_DGRAM, 0);
-		if (net->udp_connections[con_id].socket < 0) {
-			fatal("[ net: UDP: socket() returned %i ]\n",
-			    net->udp_connections[con_id].socket);
-			return;
-		}
-
-		debug(" {socket=%i}", net->udp_connections[con_id].socket);
-
-		net->udp_connections[con_id].in_use = 1;
-
-		/*  Set the socket to non-blocking:  */
-		res = fcntl(net->udp_connections[con_id].socket, F_GETFL);
-		fcntl(net->udp_connections[con_id].socket, F_SETFL,
-		    res | O_NONBLOCK);
-	}
-
-	debug(", connection id %i\n", con_id);
-
-	net->timestamp ++;
-	net->udp_connections[con_id].last_used_timestamp = net->timestamp;
-
-	remote_ip.sin_family = AF_INET;
-	memcpy((unsigned char *)&remote_ip.sin_addr,
-	    net->udp_connections[con_id].outside_ip_address, 4);
-
-	/*
-	 *  Special case for the nameserver:  If a UDP packet is sent to
-	 *  the gateway, it will be forwarded to the nameserver, if it is
-	 *  known.
-	 */
-	if (net->nameserver_known &&
-	    memcmp(net->udp_connections[con_id].outside_ip_address,
-	    &net->gateway_ipv4_addr[0], 4) == 0) {
-		memcpy((unsigned char *)&remote_ip.sin_addr,
-		    &net->nameserver_ipv4, 4);
-		net->udp_connections[con_id].fake_ns = 1;
-	}
-
-	remote_ip.sin_port = htons(
-	    net->udp_connections[con_id].outside_udp_port);
-
-	res = sendto(net->udp_connections[con_id].socket, packet + 42,
-	    len - 42, 0, (const struct sockaddr *)&remote_ip,
-	    sizeof(remote_ip));
-
-	if (res != len-42)
-		debug("[ net: UDP: unable to send %i bytes ]\n", len-42);
-	else
-		debug("[ net: UDP: OK!!! ]\n");
-}
-
-
-/*
- *  net_ip():
- *
- *  Handle an IP packet, coming from the emulated NIC.
- */
-void net_ip(struct net *net, void *extra, unsigned char *packet, int len)
-{
-#if 1
-	int i;
-
-	debug("[ net: IP: ");
-	debug("ver=%02x ", packet[14]);
-	debug("tos=%02x ", packet[15]);
-	debug("len=%02x%02x ", packet[16], packet[17]);
-	debug("id=%02x%02x ",  packet[18], packet[19]);
-	debug("ofs=%02x%02x ", packet[20], packet[21]);
-	debug("ttl=%02x ", packet[22]);
-	debug("p=%02x ", packet[23]);
-	debug("sum=%02x%02x ", packet[24], packet[25]);
-	debug("src=%02x%02x%02x%02x ",
-	    packet[26], packet[27], packet[28], packet[29]);
-	debug("dst=%02x%02x%02x%02x ",
-	    packet[30], packet[31], packet[32], packet[33]);
-	for (i=34; i<len; i++)
-		debug("%02x", packet[i]);
-	debug(" ]\n");
-#endif
-
-	/*  Cut off overflowing tail data:  */
-	if (len > 14 + packet[16]*256 + packet[17])
-		len = 14 + packet[16]*256 + packet[17];
-
-	if (packet[14] == 0x45) {
-		/*  IPv4:  */
-		switch (packet[23]) {
-		case 1:	/*  ICMP  */
-			net_ip_icmp(net, extra, packet, len);
-			break;
-		case 6:	/*  TCP  */
-			net_ip_tcp(net, extra, packet, len);
-			break;
-		case 17:/*  UDP  */
-			net_ip_udp(net, extra, packet, len);
-			break;
-		default:
-			fatal("[ net: IP: UNIMPLEMENTED protocol %i ]\n",
-			    packet[23]);
-		}
-	} else
-		fatal("[ net: IP: UNIMPLEMENTED ip, first byte = 0x%02x ]\n",
-		    packet[14]);
-}
-
-
-/*
- *  net_ip_broadcast_dhcp():
- *
- *  Handle an IPv4 DHCP broadcast packet, coming from the emulated NIC.
- *
- *  Read http://tools.ietf.org/html/rfc2131 for details on DHCP.
- *  (And http://users.telenet.be/mydotcom/library/network/dhcp.htm.)
- */
-static void net_ip_broadcast_dhcp(struct net *net, void *extra,
-	unsigned char *packet, int len)
-{
-	/*
-	 *  TODO
-	 */
-#if 1
-	struct ethernet_packet_link *lp;
-        int i, reply_len;
-
-	fatal("[ net: IPv4 DHCP: ");
-#if 1
-	fatal("ver=%02x ", packet[14]);
-	fatal("tos=%02x ", packet[15]);
-	fatal("len=%02x%02x ", packet[16], packet[17]);
-	fatal("id=%02x%02x ",  packet[18], packet[19]);
-	fatal("ofs=%02x%02x ", packet[20], packet[21]);
-	fatal("ttl=%02x ", packet[22]);
-	fatal("p=%02x ", packet[23]);
-	fatal("sum=%02x%02x ", packet[24], packet[25]);
-#endif
-	fatal("src=%02x%02x%02x%02x ",
-	    packet[26], packet[27], packet[28], packet[29]);
-	fatal("dst=%02x%02x%02x%02x ",
-	    packet[30], packet[31], packet[32], packet[33]);
-#if 0
-	for (i=34; i<len; i++)
-		fatal("%02x", packet[i]);
-#endif
-
-	if (len < 34 + 8 + 236) {
-		fatal("[ DHCP packet too short? Len=%i ]\n", len);
-		return;
-	}
-
-	/*
-	 *  UDP data (at offset 34):
-	 *
-	 *  srcport=0044 dstport=0043 length=0134 chksum=a973
-	 *  data = 01010600d116d276000000000000000000000000000000
-	 *         0000000000102030405060...0000...638253633501...000
-	 */
-
-	fatal("op=%02x ", packet[42]);
-	fatal("htype=%02x ", packet[43]);
-	fatal("hlen=%02x ", packet[44]);
-	fatal("hops=%02x ", packet[45]);
-	fatal("xid=%02x%02x%02x%02x ", packet[46], packet[47],
-	    packet[48], packet[49]);
-	fatal("secs=%02x%02x ", packet[50], packet[51]);
-	fatal("flags=%02x%02x ", packet[52], packet[53]);
-	fatal("ciaddr=%02x%02x%02x%02x ", packet[54], packet[55],
-	    packet[56], packet[57]);
-	fatal("yiaddr=%02x%02x%02x%02x ", packet[58], packet[59],
-	    packet[60], packet[61]);
-	fatal("siaddr=%02x%02x%02x%02x ", packet[62], packet[63],
-	    packet[64], packet[65]);
-	fatal("giaddr=%02x%02x%02x%02x ", packet[66], packet[67],
-	    packet[68], packet[69]);
-	fatal("chaddr=");
-	for (i=70; i<70+16; i++)
-		fatal("%02x", packet[i]);
-	/*
-   |                          sname   (64)                         |
-   |                          file    (128)                        |
-	 */
-	fatal(" ]\n");
-
-        reply_len = 307;
-        lp = net_allocate_ethernet_packet_link(net, extra, reply_len);
-
-        /*  From old packet, copy everything before options field:  */
-        memcpy(lp->data, packet, 278);
-
-	/*  We are sending to the client, from the gateway:  */
-	memcpy(lp->data + 0, packet + 6, 6);
-	memcpy(lp->data + 6, net->gateway_ethernet_addr, 6);
-
-	/*  Set IP length:  */
-	lp->data[16] = (reply_len - 14) >> 8;
-	lp->data[17] = (reply_len - 14) & 0xff;
-
-        /*  Set IP addresses:  */
-	memcpy(lp->data + 26, &net->gateway_ipv4_addr[0], 4);
-	lp->data[30] = 0xff;
-	lp->data[31] = 0xff;
-	lp->data[32] = 0xff;
-	lp->data[33] = 0xff;
-
-	/*  Switch src and dst ports:  */
-	memcpy(lp->data + 34, packet + 36, 2);
-	memcpy(lp->data + 36, packet + 34, 2);
-
-	/*  Set UDP length:  */
-	lp->data[38] = (reply_len - 34) >> 8;
-	lp->data[39] = (reply_len - 34) & 0xff;
-
-	/*  Client's (yiaddr) IPv4 address:  */
-	lp->data[58] = 10;
-	lp->data[59] = 0;
-	lp->data[60] = 0;
-	lp->data[61] = 1;
-
-	/*  Server's IPv4 address:  (giaddr)  */
-	memcpy(lp->data + 66, &net->gateway_ipv4_addr[0], 4);
-
-	/*  This is a Reply:  */
-	lp->data[42] = 0x02;
-
-	snprintf((char *)lp->data + 70+16+64, 8, "gxemul");
-
-	/*  Options field at offset 278:  */
-	lp->data[278] = 99;
-	lp->data[279] = 130;
-	lp->data[280] = 83;
-	lp->data[281] = 99;
-
-	/*  DHCP options, http://tools.ietf.org/html/rfc1533  */
-	lp->data[282] = 1; /* subnet mask */
-	lp->data[283] = 4;
-	lp->data[284] = 255;
-	lp->data[285] = 0;
-	lp->data[286] = 0;
-	lp->data[287] = 0;
-	lp->data[288] = 3; /* router */
-	lp->data[289] = 4;
-	memcpy(lp->data + 290, &net->gateway_ipv4_addr[0], 4);
-	lp->data[294] = 6; /* domain name server */
-	lp->data[295] = 4;
-	memcpy(lp->data + 296, &net->gateway_ipv4_addr[0], 4);
-	lp->data[300] = 54; /* server identifier */
-	lp->data[301] = 4;
-	memcpy(lp->data + 302, &net->gateway_ipv4_addr[0], 4);
-	lp->data[306] = 255; /* end */
-
-	/*  Recalculate IP header checksum:  */
-	net_ip_checksum(lp->data + 14, 10, 20);
-
-	/*  ... and the UDP checksum:  */
-        net_ip_tcp_checksum(lp->data + 34, 6, reply_len - 34,
-	    lp->data + 26, lp->data + 30, 1);
-
-
-/*  Debug dump:  */
-packet = lp->data;
-	fatal("[ net: IPv4 DHCP REPLY: ");
-	for (i=0; i<14; i++)
-		fatal("%02x", packet[i]);
-	fatal("ver=%02x ", packet[14]);
-	fatal("tos=%02x ", packet[15]);
-	fatal("len=%02x%02x ", packet[16], packet[17]);
-	fatal("id=%02x%02x ",  packet[18], packet[19]);
-	fatal("ofs=%02x%02x ", packet[20], packet[21]);
-	fatal("ttl=%02x ", packet[22]);
-	fatal("p=%02x ", packet[23]);
-	fatal("sum=%02x%02x ", packet[24], packet[25]);
-	fatal("src=%02x%02x%02x%02x ",
-	    packet[26], packet[27], packet[28], packet[29]);
-	fatal("dst=%02x%02x%02x%02x ",
-	    packet[30], packet[31], packet[32], packet[33]);
-	fatal("op=%02x ", packet[42]);
-	fatal("htype=%02x ", packet[43]);
-	fatal("hlen=%02x ", packet[44]);
-	fatal("hops=%02x ", packet[45]);
-	fatal("xid=%02x%02x%02x%02x ", packet[46], packet[47],
-	    packet[48], packet[49]);
-	fatal("secs=%02x%02x ", packet[50], packet[51]);
-	fatal("flags=%02x%02x ", packet[52], packet[53]);
-	fatal("ciaddr=%02x%02x%02x%02x ", packet[54], packet[55],
-	    packet[56], packet[57]);
-	fatal("yiaddr=%02x%02x%02x%02x ", packet[58], packet[59],
-	    packet[60], packet[61]);
-	fatal("siaddr=%02x%02x%02x%02x ", packet[62], packet[63],
-	    packet[64], packet[65]);
-	fatal("giaddr=%02x%02x%02x%02x ", packet[66], packet[67],
-	    packet[68], packet[69]);
-	fatal("chaddr=");
-	for (i=70; i<70+16; i++)
-		fatal("%02x", packet[i]);
-	fatal(" ]\n");
-
-#endif
-}
-
-
-/*
- *  net_ip_broadcast():
- *
- *  Handle an IP broadcast packet, coming from the emulated NIC.
- *  (This is usually a DHCP request, or similar.)
- */
-void net_ip_broadcast(struct net *net, void *extra,
-	unsigned char *packet, int len)
-{
-	unsigned char *p = (unsigned char *) &net->netmask_ipv4;
-	uint32_t x, y;
-	int i, xl, warning = 0, match = 0;
-
-#if 0
-	fatal("[ net: IP BROADCAST: ");
-	fatal("ver=%02x ", packet[14]);
-	fatal("tos=%02x ", packet[15]);
-	fatal("len=%02x%02x ", packet[16], packet[17]);
-	fatal("id=%02x%02x ",  packet[18], packet[19]);
-	fatal("ofs=%02x%02x ", packet[20], packet[21]);
-	fatal("ttl=%02x ", packet[22]);
-	fatal("p=%02x ", packet[23]);
-	fatal("sum=%02x%02x ", packet[24], packet[25]);
-	fatal("src=%02x%02x%02x%02x ",
-	    packet[26], packet[27], packet[28], packet[29]);
-	fatal("dst=%02x%02x%02x%02x ",
-	    packet[30], packet[31], packet[32], packet[33]);
-	for (i=34; i<len; i++)
-		fatal("%02x", packet[i]);
-	fatal(" ]\n");
-#endif
-
-	/*  Check for 10.0.0.255 first, maybe some guest OSes think that
-	    it's a /24 network, regardless of what it actually is.  */
-	y = (packet[30] << 24) + (packet[31] << 16) +
-	    (packet[32] << 8) + packet[33];
-
-	x = (p[0] << 24) + (p[1] << 16) + (p[2] << 8) + p[3];
-	/*  Example: x = 10.0.0.0  */
-	x |= 255;
-
-	if (x == y) {
-		warning = 1;
-		match = 1;
-	}
-
-	xl = 32 - net->netmask_ipv4_len;
-	x |= (1 << xl) - 1;
-	/*  x = 10.255.255.255  */
-
-	if (x == y)
-		match = 1;
-	if (y == 0xffffffff)
-		match = 1;
-
-	if (warning)
-		fatal("[ net_ip_broadcast(): warning: broadcast to "
-		    "0x%08x, expecting broadcast to 0x%08x or "
-		    "0xffffffff ]\n", y, x);
-
-	/*  Cut off overflowing tail data:  */
-	if (len > 14 + packet[16]*256 + packet[17])
-		len = 14 + packet[16]*256 + packet[17];
-
-	/*  Check for known packets:  */
-	if (packet[14] == 0x45 &&			/*  IPv4  */
-	    packet[23] == 0x11 &&			/*  UDP  */
-	    packet[34] == 0 && packet[35] == 68 &&	/*  DHCP client  */
-	    packet[36] == 0 && packet[37] == 67) {	/*  DHCP server  */
-		net_ip_broadcast_dhcp(net, extra, packet, len);
-		return;
-	}
-
-	/*  Unknown packet:  */
-	fatal("[ net: UNIMPLEMENTED IP BROADCAST: ");
-	fatal("ver=%02x ", packet[14]);
-	fatal("tos=%02x ", packet[15]);
-	fatal("len=%02x%02x ", packet[16], packet[17]);
-	fatal("id=%02x%02x ",  packet[18], packet[19]);
-	fatal("ofs=%02x%02x ", packet[20], packet[21]);
-	fatal("ttl=%02x ", packet[22]);
-	fatal("p=%02x ", packet[23]);
-	fatal("sum=%02x%02x ", packet[24], packet[25]);
-	fatal("src=%02x%02x%02x%02x ",
-	    packet[26], packet[27], packet[28], packet[29]);
-	fatal("dst=%02x%02x%02x%02x ",
-	    packet[30], packet[31], packet[32], packet[33]);
-	for (i=34; i<len; i++)
-		fatal("%02x", packet[i]);
-	fatal(" ]\n");
-}
-
-
-/*
- *  net_udp_rx_avail():
- *
- *  Receive any available UDP packets (from the outside world).
- */
-void net_udp_rx_avail(struct net *net, void *extra)
-{
-	int received_packets_this_tick = 0;
-	int max_packets_this_tick = 200;
-	int con_id;
-
-	for (con_id=0; con_id<MAX_UDP_CONNECTIONS; con_id++) {
-		ssize_t res;
-		unsigned char buf[66000];
-		unsigned char udp_data[66008];
-		struct sockaddr_in from;
-		socklen_t from_len = sizeof(from);
-		int ip_len, udp_len;
-		struct ethernet_packet_link *lp;
-		int max_per_packet;
-		int bytes_converted = 0;
-		int this_packets_data_length;
-		int fragment_ofs = 0;
-
-		if (received_packets_this_tick > max_packets_this_tick)
-			break;
-
-		if (!net->udp_connections[con_id].in_use)
-			continue;
-
-		if (net->udp_connections[con_id].socket < 0) {
-			fatal("INTERNAL ERROR in net.c, udp socket < 0 "
-			    "but in use?\n");
-			continue;
-		}
-
-		res = recvfrom(net->udp_connections[con_id].socket, buf,
-		    sizeof(buf), 0, (struct sockaddr *)&from, &from_len);
-
-		/*  No more incoming UDP on this connection?  */
-		if (res < 0)
-			continue;
-
-		net->timestamp ++;
-		net->udp_connections[con_id].last_used_timestamp =
-		    net->timestamp;
-
-		net->udp_connections[con_id].udp_id ++;
-
-		/*
-		 *  Special case for the nameserver:  If a UDP packet is
-		 *  received from the nameserver (if the nameserver's IP is
-		 *  known), fake it so that it comes from the gateway instead.
-		 */
-		if (net->udp_connections[con_id].fake_ns)
-			memcpy(((unsigned char *)(&from))+4,
-			    &net->gateway_ipv4_addr[0], 4);
-
-		/*
-		 *  We now have a UDP packet of size 'res' which we need
-		 *  turn into one or more ethernet packets for the emulated
-		 *  operating system.  Ethernet packets are at most 1518
-		 *  bytes long. With some margin, that means we can have
-		 *  about 1500 bytes per packet.
-		 *
-		 *	Ethernet = 14 bytes
-		 *	IP = 20 bytes
-		 *	(UDP = 8 bytes + data)
-		 *
-		 *  So data can be at most max_per_packet - 34. For UDP
-		 *  fragments, each multiple should (?) be a multiple of
-		 *  8 bytes, except the last which doesn't have any such
-		 *  restriction.
-		 */
-		max_per_packet = 1500;
-
-		/*  UDP:  */
-		udp_len = res + 8;
-		/*  from[2..3] = outside_udp_port  */
-		udp_data[0] = ((unsigned char *)&from)[2];
-		udp_data[1] = ((unsigned char *)&from)[3];
-		udp_data[2] = (net->udp_connections[con_id].
-		    inside_udp_port >> 8) & 0xff;
-		udp_data[3] = net->udp_connections[con_id].
-		    inside_udp_port & 0xff;
-		udp_data[4] = udp_len >> 8;
-		udp_data[5] = udp_len & 0xff;
-		udp_data[6] = 0;
-		udp_data[7] = 0;
-		memcpy(udp_data + 8, buf, res);
-		/*
-		 *  TODO:  UDP checksum, if necessary. At least NetBSD
-		 *  and OpenBSD accept UDP packets with 0x0000 in the
-		 *  checksum field anyway.
-		 */
-
-		while (bytes_converted < udp_len) {
-			this_packets_data_length = udp_len - bytes_converted;
-
-			/*  Do we need to fragment?  */
-			if (this_packets_data_length > max_per_packet-34) {
-				this_packets_data_length =
-				    max_per_packet - 34;
-				while (this_packets_data_length & 7)
-					this_packets_data_length --;
-			}
-
-			ip_len = 20 + this_packets_data_length;
-
-			lp = net_allocate_ethernet_packet_link(net, extra,
-			    14 + 20 + this_packets_data_length);
-
-			/*  Ethernet header:  */
-			memcpy(lp->data + 0, net->udp_connections[con_id].
-			    ethernet_address, 6);
-			memcpy(lp->data + 6, net->gateway_ethernet_addr, 6);
-			lp->data[12] = 0x08;	/*  IP = 0x0800  */
-			lp->data[13] = 0x00;
-
-			/*  IP header:  */
-			lp->data[14] = 0x45;	/*  ver  */
-			lp->data[15] = 0x00;	/*  tos  */
-			lp->data[16] = ip_len >> 8;
-			lp->data[17] = ip_len & 0xff;
-			lp->data[18] = net->udp_connections[con_id].udp_id >> 8;
-			lp->data[19] = net->udp_connections[con_id].udp_id
-			    & 0xff;
-			lp->data[20] = (fragment_ofs >> 8);
-			if (bytes_converted + this_packets_data_length
-			    < udp_len)
-				lp->data[20] |= 0x20;	/*  More fragments  */
-			lp->data[21] = fragment_ofs & 0xff;
-			lp->data[22] = 0x40;	/*  ttl  */
-			lp->data[23] = 17;	/*  p = UDP  */
-			lp->data[26] = ((unsigned char *)&from)[4];
-			lp->data[27] = ((unsigned char *)&from)[5];
-			lp->data[28] = ((unsigned char *)&from)[6];
-			lp->data[29] = ((unsigned char *)&from)[7];
-			memcpy(lp->data + 30, net->udp_connections[con_id].
-			    inside_ip_address, 4);
-			net_ip_checksum(lp->data + 14, 10, 20);
-
-			memcpy(lp->data+34, udp_data + bytes_converted,
-			    this_packets_data_length);
-
-			bytes_converted += this_packets_data_length;
-			fragment_ofs = bytes_converted / 8;
-
-			received_packets_this_tick ++;
-		}
-
-		/*  This makes sure we check this connection AGAIN
-		    for more incoming UDP packets, before moving to the
-		    next connection:  */
-		con_id --;
-	}
-}
-
-
-/*
- *  net_tcp_rx_avail():
- *
- *  Receive any available TCP packets (from the outside world).
- */
-void net_tcp_rx_avail(struct net *net, void *extra)
-{
-	int received_packets_this_tick = 0;
-	int max_packets_this_tick = 200;
-	int con_id;
-
-	for (con_id=0; con_id<MAX_TCP_CONNECTIONS; con_id++) {
-		unsigned char buf[66000];
-		ssize_t res, res2;
-		fd_set rfds;
-		struct timeval tv;
-
-		if (received_packets_this_tick > max_packets_this_tick)
-			break;
-
-		if (!net->tcp_connections[con_id].in_use)
-			continue;
-
-		if (net->tcp_connections[con_id].socket < 0) {
-			fatal("INTERNAL ERROR in net.c, tcp socket < 0"
-			    " but in use?\n");
-			continue;
-		}
-
-		if (net->tcp_connections[con_id].incoming_buf == NULL)
-			CHECK_ALLOCATION(net->tcp_connections[con_id].
-			    incoming_buf = (unsigned char *) malloc(TCP_INCOMING_BUF_LEN));
-
-		if (net->tcp_connections[con_id].state >=
-		    TCP_OUTSIDE_DISCONNECTED)
-			continue;
-
-		/*  Is the socket available for output?  */
-		FD_ZERO(&rfds);		/*  write  */
-		FD_SET(net->tcp_connections[con_id].socket, &rfds);
-		tv.tv_sec = tv.tv_usec = 0;
-		errno = 0;
-		res = select(net->tcp_connections[con_id].socket+1,
-		    NULL, &rfds, NULL, &tv);
-
-		if (errno == ECONNREFUSED) {
-			fatal("[ ECONNREFUSED: TODO ]\n");
-			net->tcp_connections[con_id].state =
-			    TCP_OUTSIDE_DISCONNECTED;
-			fatal("CHANGING TO TCP_OUTSIDE_DISCONNECTED "
-			    "(refused connection)\n");
-			continue;
-		}
-
-		if (errno == ETIMEDOUT) {
-			fatal("[ ETIMEDOUT: TODO ]\n");
-			/*  TODO  */
-			net->tcp_connections[con_id].state =
-			    TCP_OUTSIDE_DISCONNECTED;
-			fatal("CHANGING TO TCP_OUTSIDE_DISCONNECTED "
-			    "(timeout)\n");
-			continue;
-		}
-
-		if (net->tcp_connections[con_id].state ==
-		    TCP_OUTSIDE_TRYINGTOCONNECT && res > 0) {
-			net->tcp_connections[con_id].state =
-			    TCP_OUTSIDE_CONNECTED;
-			debug("CHANGING TO TCP_OUTSIDE_CONNECTED\n");
-			net_ip_tcp_connectionreply(net, extra, con_id, 1,
-			    NULL, 0, 0);
-		}
-
-		if (net->tcp_connections[con_id].state ==
-		    TCP_OUTSIDE_CONNECTED && res < 1) {
-			continue;
-		}
-
-		/*
-		 *  Does this connection have unacknowledged data?  Then, if
-		 *  enough number of rounds have passed, try to resend it using
-		 *  the old value of seqnr.
-		 */
-		if (net->tcp_connections[con_id].incoming_buf_len != 0) {
-			net->tcp_connections[con_id].incoming_buf_rounds ++;
-			if (net->tcp_connections[con_id].incoming_buf_rounds >
-			    10000) {
-				debug("  at seqnr %u but backing back to %u,"
-				    " resending %i bytes\n",
-				    net->tcp_connections[con_id].outside_seqnr,
-				    net->tcp_connections[con_id].
-				    incoming_buf_seqnr,
-				    net->tcp_connections[con_id].
-				    incoming_buf_len);
-
-				net->tcp_connections[con_id].
-				    incoming_buf_rounds = 0;
-				net->tcp_connections[con_id].outside_seqnr =
-				    net->tcp_connections[con_id].
-				    incoming_buf_seqnr;
-
-				net_ip_tcp_connectionreply(net, extra, con_id,
-				    0, net->tcp_connections[con_id].
-				    incoming_buf,
-				    net->tcp_connections[con_id].
-				    incoming_buf_len, 0);
-			}
-			continue;
-		}
-
-		/*  Don't receive unless the guest OS is ready!  */
-		if (((int32_t)net->tcp_connections[con_id].outside_seqnr -
-		    (int32_t)net->tcp_connections[con_id].inside_acknr) > 0) {
-/*			fatal("YOYO 1! outside_seqnr - inside_acknr = %i\n",
-			    net->tcp_connections[con_id].outside_seqnr -
-			    net->tcp_connections[con_id].inside_acknr);  */
-			continue;
-		}
-
-		/*  Is there incoming data available on the socket?  */
-		FD_ZERO(&rfds);		/*  read  */
-		FD_SET(net->tcp_connections[con_id].socket, &rfds);
-		tv.tv_sec = tv.tv_usec = 0;
-		res2 = select(net->tcp_connections[con_id].socket+1, &rfds,
-		    NULL, NULL, &tv);
-
-		/*  No more incoming TCP data on this connection?  */
-		if (res2 < 1)
-			continue;
-
-		res = read(net->tcp_connections[con_id].socket, buf, 1400);
-		if (res > 0) {
-			/*  debug("\n -{- %lli -}-\n", (long long)res);  */
-			net->tcp_connections[con_id].incoming_buf_len = res;
-			net->tcp_connections[con_id].incoming_buf_rounds = 0;
-			net->tcp_connections[con_id].incoming_buf_seqnr = 
-			    net->tcp_connections[con_id].outside_seqnr;
-			debug("  putting %i bytes (seqnr %u) in the incoming "
-			    "buf\n", res, net->tcp_connections[con_id].
-			    incoming_buf_seqnr);
-			memcpy(net->tcp_connections[con_id].incoming_buf,
-			    buf, res);
-
-			net_ip_tcp_connectionreply(net, extra, con_id, 0,
-			    buf, res, 0);
-		} else if (res == 0) {
-			net->tcp_connections[con_id].state =
-			    TCP_OUTSIDE_DISCONNECTED;
-			debug("CHANGING TO TCP_OUTSIDE_DISCONNECTED, read"
-			    " res=0\n");
-			net_ip_tcp_connectionreply(net, extra, con_id, 0,
-			    NULL, 0, 0);
-		} else {
-			net->tcp_connections[con_id].state =
-			    TCP_OUTSIDE_DISCONNECTED;
-			fatal("CHANGING TO TCP_OUTSIDE_DISCONNECTED, "
-			    "read res<=0, errno = %i\n", errno);
-			net_ip_tcp_connectionreply(net, extra, con_id, 0,
-			    NULL, 0, 0);
-		}
-
-		net->timestamp ++;
-		net->tcp_connections[con_id].last_used_timestamp =
-		    net->timestamp;
-	}
-}
-
-
diff -Nru gxemul-0.6.2/src/net/net_misc.c gxemul-0.7.0+dfsg/src/net/net_misc.c
--- gxemul-0.6.2/src/net/net_misc.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/net/net_misc.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,145 @@
+/*
+ *  Copyright (C) 2004-2018  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Misc. helper functions.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/socket.h>
+#include <netinet/in.h>
+#include <arpa/inet.h>
+#include <unistd.h>
+
+#include "machine.h"
+#include "misc.h"
+#include "net.h"
+
+
+/*
+ *  net_debugaddr():
+ *
+ *  Print an address using debug().
+ */
+void net_debugaddr(void *addr, int type)
+{
+	int i;
+	unsigned char *p = (unsigned char *) addr;
+
+	switch (type) {
+
+	case NET_ADDR_IPV4:
+		for (i=0; i<4; i++)
+			debug("%s%i", i? "." : "", p[i]);
+		break;
+
+	case NET_ADDR_IPV6:
+		for (i=0; i<16; i+=2)
+			debug("%s%4x", i? ":" : "", p[i] * 256 + p[i+1]);
+		break;
+
+	case NET_ADDR_ETHERNET:
+		for (i=0; i<6; i++)
+			debug("%s%02x", i? ":" : "", p[i]);
+		break;
+
+	default:
+		fatal("net_debugaddr(): UNIMPLEMTED type %i\n", type);
+		exit(1);
+	}
+}
+
+
+/*
+ *  net_generate_unique_mac():
+ *
+ *  Generate a "unique" serial number for a machine. The machine's serial
+ *  number is combined with the machine's current number of NICs to form a
+ *  more-or-less valid MAC address.
+ *
+ *  The return value (6 bytes) are written to macbuf.
+ */
+void net_generate_unique_mac(struct machine *machine, unsigned char *macbuf)
+{
+	if (macbuf == NULL || machine == NULL) {
+		fatal("**\n**  net_generate_unique_mac(): NULL ptr\n**\n");
+		return;
+	}
+
+	// Special case: real SGI machines have 0x08 as their first
+	// byte, so let's mimic that.
+	macbuf[0] = machine->machine_type == MACHINE_SGI ? 0x08 : 0x10;
+	macbuf[1] = 0x20;
+	macbuf[2] = 0x30;
+	macbuf[3] = 0;
+	macbuf[4] = 0;
+	/*  NOTE/TODO: This only allows 8 nics per machine!  */
+	macbuf[5] = (machine->serial_nr << 4) + (machine->nr_of_nics << 1);
+
+	if (macbuf[0] & 1 || macbuf[5] & 1) {
+		fatal("Internal error in net_generate_unique_mac().\n");
+		exit(1);
+	}
+
+	/*  TODO: Remember the mac addresses somewhere?  */
+	machine->nr_of_nics ++;
+}
+
+
+/*
+ *  send_udp():
+ *
+ *  Send a simple UDP packet to a real (physical) host. Used for distributed
+ *  network simulations.
+ */
+void send_udp(struct in_addr *addrp, int portnr, unsigned char *packet, size_t len)
+{
+	int s;
+	struct sockaddr_in si;
+
+	s = socket(AF_INET, SOCK_DGRAM, 0);
+	if (s < 0) {
+		perror("send_udp(): socket");
+		return;
+	}
+
+	/*  fatal("send_udp(): sending to port %i\n", portnr);  */
+
+	si.sin_family = AF_INET;
+	si.sin_addr = *addrp;
+	si.sin_port = htons(portnr);
+
+	if (sendto(s, packet, len, 0, (struct sockaddr *)&si,
+	    sizeof(si)) != (ssize_t)len) {
+		perror("send_udp(): sendto");
+	}
+
+	close(s);
+}
+
diff -Nru gxemul-0.6.2/src/net/net_misc.cc gxemul-0.7.0+dfsg/src/net/net_misc.cc
--- gxemul-0.6.2/src/net/net_misc.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/net/net_misc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,150 +0,0 @@
-/*
- *  Copyright (C) 2004-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Misc. helper functions.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-#include <sys/socket.h>
-#include <netinet/in.h>
-#include <arpa/inet.h>
-#include <unistd.h>
-
-#include "machine.h"
-#include "misc.h"
-#include "net.h"
-
-
-/*
- *  net_debugaddr():
- *
- *  Print an address using debug().
- */
-void net_debugaddr(void *addr, int type)
-{
-	int i;
-	unsigned char *p = (unsigned char *) addr;
-
-	switch (type) {
-
-	case NET_ADDR_IPV4:
-		for (i=0; i<4; i++)
-			debug("%s%i", i? "." : "", p[i]);
-		break;
-
-	case NET_ADDR_IPV6:
-		for (i=0; i<16; i+=2)
-			debug("%s%4x", i? ":" : "", p[i] * 256 + p[i+1]);
-		break;
-
-	case NET_ADDR_ETHERNET:
-		for (i=0; i<6; i++)
-			debug("%s%02x", i? ":" : "", p[i]);
-		break;
-
-	default:
-		fatal("net_debugaddr(): UNIMPLEMTED type %i\n", type);
-		exit(1);
-	}
-}
-
-
-/*
- *  net_generate_unique_mac():
- *
- *  Generate a "unique" serial number for a machine. The machine's serial
- *  number is combined with the machine's current number of NICs to form a
- *  more-or-less valid MAC address.
- *
- *  The return value (6 bytes) are written to macbuf.
- */
-void net_generate_unique_mac(struct machine *machine, unsigned char *macbuf)
-{
-	int x, y;
-
-	if (macbuf == NULL || machine == NULL) {
-		fatal("**\n**  net_generate_unique_mac(): NULL ptr\n**\n");
-		return;
-	}
-
-	x = machine->serial_nr;
-	y = machine->nr_of_nics;
-
-	// Special case: SGI machines have 0x08 as their first byte?
-	macbuf[0] = machine->machine_type == MACHINE_SGI ? 0x08 : 0x10;
-	macbuf[1] = 0x20;
-	macbuf[2] = 0x30;
-	macbuf[3] = 0;
-	macbuf[4] = 0;
-	/*  NOTE/TODO: This only allows 8 nics per machine!  */
-	macbuf[5] = (machine->serial_nr << 4) + (machine->nr_of_nics << 1);
-
-	if (macbuf[0] & 1 || macbuf[5] & 1) {
-		fatal("Internal error in net_generate_unique_mac().\n");
-		exit(1);
-	}
-
-	/*  TODO: Remember the mac addresses somewhere?  */
-	machine->nr_of_nics ++;
-}
-
-
-/*
- *  send_udp():
- *
- *  Send a simple UDP packet to a real (physical) host. Used for distributed
- *  network simulations.
- */
-void send_udp(struct in_addr *addrp, int portnr, unsigned char *packet,
-	size_t len)
-{
-	int s;
-	struct sockaddr_in si;
-
-	s = socket(AF_INET, SOCK_DGRAM, 0);
-	if (s < 0) {
-		perror("send_udp(): socket");
-		return;
-	}
-
-	/*  fatal("send_udp(): sending to port %i\n", portnr);  */
-
-	si.sin_family = AF_INET;
-	si.sin_addr = *addrp;
-	si.sin_port = htons(portnr);
-
-	if (sendto(s, packet, len, 0, (struct sockaddr *)&si,
-	    sizeof(si)) != (ssize_t)len) {
-		perror("send_udp(): sendto");
-	}
-
-	close(s);
-}
-
diff -Nru gxemul-0.6.2/src/net/net_tap.c gxemul-0.7.0+dfsg/src/net/net_tap.c
--- gxemul-0.6.2/src/net/net_tap.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/net/net_tap.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,190 @@
+/*  
+ *  Copyright (C) 2020 Jason R. Thorpe.  All rights reserved.
+ * 
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *      
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ */
+
+/*
+ *  Support for Ethernet tap interfaces.
+ *
+ *  A single tap instance is used for the entire simulated network.
+ *  We treat this as sort of virtual Ethernet switch, with the tap
+ *  being the upstream port.  This is very simple, conceptually, and
+ *  fits in nicely with the rest of the network simulation model in
+ *  GXemul.
+ *
+ *  Use of the tap interface is completely optional, but if it is used
+ *  then all of the virtual IP network support is bypassed completely.
+ */
+
+#include <sys/types.h>
+#include <sys/ioctl.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <string.h>
+#include <unistd.h> 
+
+#include "misc.h"
+#include "net.h"
+
+/*
+ *  net_tap_rx_for_nic():
+ *
+ *  Receive a packet from the virtual Ethernet switch for this NIC.
+ */
+static void net_tap_rx_for_nic(struct net *net, struct nic_data *nic,
+	unsigned char *buf, ssize_t size)
+{
+	struct ethernet_packet_link *lp;
+
+	/*
+	 * We should deliver to the interface if:
+	 *
+	 * ==> The interface is in promiscuous mode.
+	 *  -- or --
+	 * ==> The packet is broadcast or multicast (the emulated device
+	 *     can further apply a multicast filter if it wishes).
+	 *  -- or --
+	 * ==> The destination MAC address matches the NIC MAC address.
+	 *
+	 * Note that normally a switch would not know if an interface
+	 * is in promiscuous mode, but this is a bit of extra magic
+	 * we implement because we can for the sake of convenience.
+	 * Also, some emulated interfaces may want to see all packets
+	 * so as to implement their own filtering logic.
+	 *
+	 * Also note that testing for multicast also catches the broadcast
+	 * case.
+	 */
+
+	if (nic->promiscuous_mode ||
+	    net_ether_multicast(buf) || net_ether_eq(nic->mac_address, buf)) {
+		lp = net_allocate_ethernet_packet_link(net, nic, (int)size);
+		memcpy(lp->data, buf, size);
+	}
+}
+
+/*
+ *  net_tap_rx_avail():
+ *
+ *  We poll the net-shared tap device and link up any available packets to
+ *  their destination interfaces, acting like a virtual Ethernet switch.
+ */
+void net_tap_rx_avail(struct net *net)
+{
+	int received_packets_this_tick = 0;
+	int max_packets_this_tick = 200;
+
+	for (;;) {
+		unsigned char buf[1518];
+		ssize_t bytes_read;
+		int i;
+
+		if (received_packets_this_tick > max_packets_this_tick)
+			break;
+
+		/* Read one packet from the tap device. */
+		bytes_read = read(net->tap_fd, buf, sizeof(buf));
+
+		if (bytes_read < 0) {
+			/* No more packets available on the tap. */
+			break;
+		}
+
+		/*
+		 * Drop runt packets now; allow other layers to assume
+		 * valid Ethernet frames.  This really should be 64, but
+		 * 20 is used in the transmit path.
+		 */
+		if (bytes_read < 20)
+			continue;
+
+		for (i = 0; i < net->n_nics; i++) {
+			net_tap_rx_for_nic(net, net->nic_data[i],
+			    buf, bytes_read);
+		}
+	}
+}
+
+/*
+ *  net_tap_tx():
+ *
+ *  Transmit an ethernet packet, as seen from the emulated ethernet controller,
+ *  to the net-shared tap device.  Even if the packet is destined only for
+ *  a NIC on the local virtual Ethernet switch, we always send it to the
+ *  tap device so that the host system can monitor traffic by running tcpdump
+ *  on its view of the tap.
+ */
+void net_tap_tx(struct net *net, struct nic_data *nic,
+	unsigned char *packet, int len)
+{
+	int i;
+
+	for (i = 0; i < net->n_nics; i++) {
+		if (nic == net->nic_data[i])
+			continue;
+		net_tap_rx_for_nic(net, net->nic_data[i], packet, len);
+	}
+
+	/*
+	 * Don't bother checking for errors here.  The tap driver in the
+	 * kernel will either take the entire packet or none of it, and
+	 * there isn't any useful error recovery for us anyway.
+	 */
+	int ignored = write(net->tap_fd, packet, len);
+	(void)ignored;
+}
+
+/*
+ *  net_tap_init():
+ *
+ *  Initialize the tap interface.  Returns true if successful, false otherwise.
+ */
+bool net_tap_init(struct net *net, const char *tapdev)
+{
+	int fd;
+	int one = 1;
+
+	fd = open(tapdev, O_RDWR);
+	if (fd < 0) {
+		debugmsg(SUBSYS_NET, "tap", VERBOSITY_ERROR,
+		    "unable to open tap device '%s': %s",
+		    tapdev, strerror(errno));
+		return false;
+	}
+
+	if (ioctl(fd, FIONBIO, &one) < 0) {
+		debugmsg(SUBSYS_NET, "tap", VERBOSITY_ERROR,
+		    "unable to set non-blocking mode on "
+		    "tap device '%s': %s", tapdev, strerror(errno));
+		close(fd);
+		return false;
+	}
+
+	net->tapdev = strdup(tapdev);
+	net->tap_fd = fd;
+
+	return true;
+}
+
diff -Nru gxemul-0.6.2/src/net/README gxemul-0.7.0+dfsg/src/net/README
--- gxemul-0.6.2/src/net/README	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/net/README	2021-11-27 09:42:23.000000000 +0000
@@ -1,7 +1,12 @@
 Emulated (ethernet / internet) network support.
 
-NOTE:  This is just an ugly hack, and just barely enough to get some
-       Internet networking up and running for the guest OS.
+The emulated internet gateway support is just an ugly hack, just barely
+enough to get some Internet networking up and running for the guest OS.
+
+(The emulated internet support can be bypassed by using TAP networking.
+In that case, packets from the emulated network are passed to a TAP
+device, and it is up to you to make sure that any DNS hosts or other
+servers are reachable.)
 
 TODO:
 	o)  TCP: fin/ack stuff, and connection time-outs and
diff -Nru gxemul-0.6.2/src/old_main/emul.cc gxemul-0.7.0+dfsg/src/old_main/emul.cc
--- gxemul-0.6.2/src/old_main/emul.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/old_main/emul.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,938 +0,0 @@
-/*
- *  Copyright (C) 2003-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  LEGACY emulation startup and misc. routines.
- */
-
-#include <signal.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <limits.h>
-#include <stdarg.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "arcbios.h"
-#include "cpu.h"
-#include "emul.h"
-#include "console.h"
-#include "debugger.h"
-#include "device.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "memory.h"
-#include "mips_cpu_types.h"
-#include "misc.h"
-#include "net.h"
-#include "settings.h"
-#include "timer.h"
-#include "x11.h"
-
-#include "thirdparty/exec_elf.h"
-
-
-extern int extra_argc;
-extern char **extra_argv;
-
-extern int verbose;
-extern int quiet_mode;
-extern int force_debugger_at_exit;
-extern int single_step;
-extern int old_show_trace_tree;
-extern int old_instruction_trace;
-extern int old_quiet_mode;
-extern int quiet_mode;
-
-
-/*
- *  add_breakpoints():
- *
- *  Take the strings breakpoint_string[] and convert to addresses
- *  (and store them in breakpoint_addr[]).
- *
- *  TODO: This function should be moved elsewhere.
- */
-static void add_breakpoints(struct machine *m)
-{
-	int i;
-	int string_flag;
-	uint64_t dp;
-
-	for (i=0; i<m->breakpoints.n; i++) {
-		string_flag = 0;
-		dp = strtoull(m->breakpoints.string[i], NULL, 0);
-
-		/*
-		 *  If conversion resulted in 0, then perhaps it is a
-		 *  symbol:
-		 */
-		if (dp == 0) {
-			uint64_t addr;
-			int res = get_symbol_addr(&m->symbol_context,
-			    m->breakpoints.string[i], &addr);
-			if (!res) {
-				fprintf(stderr,
-				    "ERROR! Breakpoint '%s' could not be"
-					" parsed\n",
-				    m->breakpoints.string[i]);
-				exit(1);
-			} else {
-				dp = addr;
-				string_flag = 1;
-			}
-		}
-
-		/*
-		 *  TODO:  It would be nice if things like   symbolname+0x1234
-		 *  were automatically converted into the correct address.
-		 */
-
-		if (m->arch == ARCH_MIPS) {
-			if ((dp >> 32) == 0 && ((dp >> 31) & 1))
-				dp |= 0xffffffff00000000ULL;
-		}
-
-		m->breakpoints.addr[i] = dp;
-
-		debug("breakpoint %i: 0x%" PRIx64, i, dp);
-		if (string_flag)
-			debug(" (%s)", m->breakpoints.string[i]);
-		debug("\n");
-	}
-}
-
-
-/*
- *  fix_console():
- */
-static void fix_console(void)
-{
-	console_deinit_main();
-}
-
-
-/*
- *  emul_new():
- *
- *  Returns a reasonably initialized struct emul.
- */
-struct emul *emul_new(char *name)
-{
-	struct emul *e;
-
-	CHECK_ALLOCATION(e = (struct emul *) malloc(sizeof(struct emul)));
-	memset(e, 0, sizeof(struct emul));
-
-	e->settings = settings_new();
-
-	settings_add(e->settings, "n_machines", 0,
-	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_DECIMAL,
-	    (void *) &e->n_machines);
-
-	/*  TODO: More settings?  */
-
-	/*  Sane default values:  */
-	e->n_machines = 0;
-	e->next_serial_nr = 1;
-
-	if (name != NULL) {
-		CHECK_ALLOCATION(e->name = strdup(name));
-		settings_add(e->settings, "name", 0,
-		    SETTINGS_TYPE_STRING, SETTINGS_FORMAT_STRING,
-		    (void *) &e->name);
-	}
-
-	return e;
-}
-
-
-/*
- *  emul_destroy():
- *
- *  Destroys a previously created emul object.
- */
-void emul_destroy(struct emul *emul)
-{
-	int i;
-
-	if (emul->name != NULL) {
-		settings_remove(emul->settings, "name");
-		free(emul->name);
-	}
-
-	for (i=0; i<emul->n_machines; i++)
-		machine_destroy(emul->machines[i]);
-
-	if (emul->machines != NULL)
-		free(emul->machines);
-
-	/*  Remove any remaining level-1 settings:  */
-	settings_remove_all(emul->settings);
-	settings_destroy(emul->settings);
-
-	free(emul);
-}
-
-
-/*
- *  emul_add_machine():
- *
- *  Calls machine_new(), adds the new machine into the emul struct, and
- *  returns a pointer to the new machine.
- *
- *  This function should be used instead of manually calling machine_new().
- */
-struct machine *emul_add_machine(struct emul *e, char *name)
-{
-	struct machine *m;
-	char tmpstr[20];
-	int i;
-
-	m = machine_new(name, e, e->n_machines);
-	m->serial_nr = (e->next_serial_nr ++);
-
-	i = e->n_machines ++;
-
-	CHECK_ALLOCATION(e->machines = (struct machine **) realloc(e->machines,
-	    sizeof(struct machine *) * e->n_machines));
-
-	e->machines[i] = m;
-
-	snprintf(tmpstr, sizeof(tmpstr), "machine[%i]", i);
-	settings_add(e->settings, tmpstr, 1, SETTINGS_TYPE_SUBSETTINGS, 0,
-	    e->machines[i]->settings);
-
-	return m;
-}
-
-
-/*
- *  add_arc_components():
- *
- *  This function adds ARCBIOS memory descriptors for the loaded program,
- *  and ARCBIOS components for SCSI devices.
- */
-static void add_arc_components(struct machine *m)
-{
-	struct cpu *cpu = m->cpus[m->bootstrap_cpu];
-	uint64_t start = cpu->pc & 0x1fffffff;
-	uint64_t len = 0xc00000 - start;
-	struct diskimage *d;
-	uint64_t scsicontroller, scsidevice, scsidisk;
-
-	if ((cpu->pc >> 60) != 0xf) {
-		start = cpu->pc & 0xffffffffffULL;
-		len = 0xc00000 - start;
-	}
-
-	len += 1048576 * m->memory_offset_in_mb;
-
-	/*
-	 *  NOTE/TODO: magic 12MB end of load program area
-	 *
-	 *  Hm. This breaks the old FreeBSD/MIPS snapshots...
-	 */
-#if 0
-	arcbios_add_memory_descriptor(cpu,
-	    0x60000 + m->memory_offset_in_mb * 1048576,
-	    start-0x60000 - m->memory_offset_in_mb * 1048576,
-	    ARCBIOS_MEM_FreeMemory);
-#endif
-	arcbios_add_memory_descriptor(cpu,
-	    start, len, ARCBIOS_MEM_LoadedProgram);
-
-	scsicontroller = arcbios_get_scsicontroller(m);
-	if (scsicontroller == 0)
-		return;
-
-	/*  TODO: The device 'name' should defined be somewhere else.  */
-
-	d = m->first_diskimage;
-	while (d != NULL) {
-		if (d->type == DISKIMAGE_SCSI) {
-			int a, b, flags = COMPONENT_FLAG_Input;
-			char component_string[100];
-			const char *name = "DEC     RZ58     (C) DEC2000";
-
-			/*  Read-write, or read-only?  */
-			if (d->writable)
-				flags |= COMPONENT_FLAG_Output;
-			else
-				flags |= COMPONENT_FLAG_ReadOnly;
-
-			a = COMPONENT_TYPE_DiskController;
-			b = COMPONENT_TYPE_DiskPeripheral;
-
-			if (d->is_a_cdrom) {
-				flags |= COMPONENT_FLAG_Removable;
-				a = COMPONENT_TYPE_CDROMController;
-				b = COMPONENT_TYPE_FloppyDiskPeripheral;
-				name = "NEC     CD-ROM CDR-210P 1.0 ";
-			}
-
-			scsidevice = arcbios_addchild_manual(cpu,
-			    COMPONENT_CLASS_ControllerClass,
-			    a, flags, 1, 2, d->id, 0xffffffff,
-			    name, scsicontroller, NULL, 0);
-
-			scsidisk = arcbios_addchild_manual(cpu,
-			    COMPONENT_CLASS_PeripheralClass,
-			    b, flags, 1, 2, 0, 0xffffffff, NULL,
-			    scsidevice, NULL, 0);
-
-			/*
-			 *  Add device string to component address mappings:
-			 *  "scsi(0)disk(0)rdisk(0)partition(0)"
-			 */
-
-			if (d->is_a_cdrom) {
-				snprintf(component_string,
-				    sizeof(component_string),
-				    "scsi(0)cdrom(%i)", d->id);
-				arcbios_add_string_to_component(m,
-				    component_string, scsidevice);
-
-				snprintf(component_string,
-				    sizeof(component_string),
-				    "scsi(0)cdrom(%i)fdisk(0)", d->id);
-				arcbios_add_string_to_component(m,
-				    component_string, scsidisk);
-			} else {
-				snprintf(component_string,
-				    sizeof(component_string),
-				    "scsi(0)disk(%i)", d->id);
-				arcbios_add_string_to_component(m,
-				    component_string, scsidevice);
-
-				snprintf(component_string,
-				    sizeof(component_string),
-				    "scsi(0)disk(%i)rdisk(0)", d->id);
-				arcbios_add_string_to_component(m,
-				    component_string, scsidisk);
-			}
-		}
-
-		d = d->next;
-	}
-}
-
-
-/*
- *  emul_machine_setup():
- *
- *	o)  Initialize the hardware (RAM, devices, CPUs, ...) which
- *	    will be emulated in this machine.
- *
- *	o)  Load ROM code and/or other programs into emulated memory.
- *
- *	o)  Special hacks needed after programs have been loaded.
- */
-void emul_machine_setup(struct machine *m, int n_load, char **load_names,
-	int n_devices, char **device_names)
-{
-	struct cpu *cpu;
-	int i, iadd = DEBUG_INDENTATION;
-	uint64_t memory_amount, entrypoint = 0, gp = 0, toc = 0;
-	int byte_order;
-
-	if (m->name != NULL)
-		debug("machine \"%s\":\n", m->name);
-	else
-		debug("machine:\n");
-
-	debug_indentation(iadd);
-
-	if (m->machine_type == MACHINE_NONE) {
-		fatal("No machine type specified?\n");
-		exit(1);
-	}
-
-	m->cpu_family = cpu_family_ptr_by_number(m->arch);
-
-	if (m->arch == ARCH_ALPHA)
-		m->arch_pagesize = 8192;
-
-	machine_memsize_fix(m);
-
-	/*
-	 *  Create the system's memory:
-	 */
-	debug("memory: %i MB", m->physical_ram_in_mb);
-	memory_amount = (uint64_t)m->physical_ram_in_mb * 1048576;
-	if (m->memory_offset_in_mb > 0) {
-		/*
-		 *  A special hack is used for some SGI models,
-		 *  where memory is offset by 128MB to leave room for
-		 *  EISA space and other things.
-		 */
-		debug(" (offset by %iMB)", m->memory_offset_in_mb);
-		memory_amount += 1048576 * m->memory_offset_in_mb;
-	}
-	if (m->machine_type == MACHINE_SGI && m->machine_subtype == 32) {
-		if (memory_amount > 0x10000000) {
-			memory_amount = 0x10000000;
-			debug(" (SGI O2 hack: %i MB at offset 0)", 0x10000000 / 1048576);
-		}
-	}
-	m->memory = memory_new(memory_amount, m->arch);
-	debug("\n");
-
-	/*  Create CPUs:  */
-	if (m->cpu_name == NULL)
-		machine_default_cputype(m);
-	if (m->ncpus == 0)
-		m->ncpus = 1;
-
-	CHECK_ALLOCATION(m->cpus = (struct cpu **) malloc(sizeof(struct cpu *) * m->ncpus));
-	memset(m->cpus, 0, sizeof(struct cpu *) * m->ncpus);
-
-	debug("cpu0");
-	if (m->ncpus > 1)
-		debug(" .. cpu%i", m->ncpus - 1);
-	debug(": ");
-	for (i=0; i<m->ncpus; i++) {
-		m->cpus[i] = cpu_new(m->memory, m, i, m->cpu_name);
-		if (m->cpus[i] == NULL) {
-			fprintf(stderr, "Unable to create CPU object. "
-			    "Aborting.");
-			exit(1);
-		}
-	}
-	debug("\n");
-
-	if (m->use_random_bootstrap_cpu)
-		m->bootstrap_cpu = random() % m->ncpus;
-	else
-		m->bootstrap_cpu = 0;
-
-	cpu = m->cpus[m->bootstrap_cpu];
-
-	if (m->x11_md.in_use)
-		x11_init(m);
-
-	/*  Fill the directly addressable memory with random bytes:  */
-	if (m->random_mem_contents) {
-		for (i=0; i<(int)memory_amount; i+=256) {
-			unsigned char data[256];
-			unsigned int j;
-			for (j=0; j<sizeof(data); j++)
-				data[j] = random() & 255;
-			cpu->memory_rw(cpu, m->memory, i, data, sizeof(data),
-			    MEM_WRITE, CACHE_NONE | NO_EXCEPTIONS | PHYSICAL);
-		}
-	}
-
-	for (i=0; i<n_devices; i++)
-		device_add(m, device_names[i]);
-
-	machine_setup(m);
-
-	diskimage_dump_info(m);
-	console_debug_dump(m);
-
-	/*  Load files (ROM code, boot code, ...) into memory:  */
-	if (n_load == 0) {
-		if (m->first_diskimage != NULL) {
-			if (!load_bootblock(m, cpu, &n_load, &load_names)) {
-				fprintf(stderr, "\nNo executable files were"
-				    " specified, and booting directly from disk"
-				    " failed.\n");
-				exit(1);
-			}
-		} else {
-			fprintf(stderr, "No executable file(s) loaded, and "
-			    "we are not booting directly from a disk image."
-			    "\nAborting.\n");
-			exit(1);
-		}
-	}
-
-	while (n_load > 0) {
-		FILE *tmp_f;
-		char *name_to_load = *load_names;
-		int remove_after_load = 0;
-
-		/*  Special hack for removing temporary files:  */
-		if (name_to_load[0] == 8) {
-			name_to_load ++;
-			remove_after_load = 1;
-		}
-
-		/*
-		 *  gzipped files are automagically gunzipped:
-		 *  NOTE/TODO: This isn't secure. system() is used.
-		 */
-		tmp_f = fopen(name_to_load, "r");
-		if (tmp_f != NULL) {
-			unsigned char buf[2];		/*  gzip header  */
-			size_t res;
-
-			memset(buf, 0, sizeof(buf));
-			res = fread(buf, 1, sizeof(buf), tmp_f);
-
-			if (res == sizeof(buf) &&
-			    buf[0] == 0x1f && buf[1] == 0x8b) {
-				size_t zzlen = strlen(name_to_load)*2 + 100;
-				char *zz;
-
-				CHECK_ALLOCATION(zz = (char*) malloc(zzlen));
-				debug("gunziping %s\n", name_to_load);
-
-				/*
-				 *  gzip header found.  If this was a file
-				 *  extracted from, say, a CDROM image, then it
-				 *  already has a temporary name. Otherwise we
-				 *  have to gunzip into a temporary file.
-				 */
-				if (remove_after_load) {
-					snprintf(zz, zzlen, "mv %s %s.gz",
-					    name_to_load, name_to_load);
-					if (system(zz) != 0)
-						perror(zz);
-					snprintf(zz, zzlen, "gunzip %s.gz",
-					    name_to_load);
-					if (system(zz) != 0)
-						perror(zz);
-				} else {
-					/*  gunzip into new temp file:  */
-					int tmpfile_handle;
-					char *new_temp_name;
-					const char *tmpdir = getenv("TMPDIR");
-
-					if (tmpdir == NULL)
-						tmpdir = DEFAULT_TMP_DIR;
-
-					CHECK_ALLOCATION(new_temp_name =
-					    (char*) malloc(300));
-					snprintf(new_temp_name, 300,
-					    "%s/gxemul.XXXXXXXXXXXX", tmpdir);
-
-					tmpfile_handle = mkstemp(new_temp_name);
-					close(tmpfile_handle);
-					snprintf(zz, zzlen, "gunzip -c '%s' > "
-					    "%s", name_to_load, new_temp_name);
-					if (system(zz) != 0)
-						perror(zz);
-					name_to_load = new_temp_name;
-					remove_after_load = 1;
-				}
-				free(zz);
-			}
-			fclose(tmp_f);
-		}
-
-		byte_order = NO_BYTE_ORDER_OVERRIDE;
-
-		/*
-		 *  Load the file:  :-)
-		 */
-		file_load(m, m->memory, name_to_load, &entrypoint,
-		    m->arch, &gp, &byte_order, &toc);
-
-		if (remove_after_load) {
-			debug("removing %s\n", name_to_load);
-			unlink(name_to_load);
-		}
-
-		if (byte_order != NO_BYTE_ORDER_OVERRIDE)
-			cpu->byte_order = byte_order;
-
-		cpu->pc = entrypoint;
-
-		switch (m->arch) {
-
-		case ARCH_ALPHA:
-			/*  For position-independent code:  */
-			cpu->cd.alpha.r[ALPHA_T12] = cpu->pc;
-			break;
-
-		case ARCH_ARM:
-			if (cpu->pc & 2) {
-				fatal("ARM: misaligned pc: TODO\n");
-				exit(1);
-			}
-
-			cpu->pc = (uint32_t)cpu->pc;
-
-			// Lowest bit of PC indicates THUMB mode.
-			if (cpu->pc & 1)
-				cpu->cd.arm.cpsr |= ARM_FLAG_T;
-			break;
-
-		case ARCH_M88K:
-			if (cpu->pc & 3) {
-				fatal("M88K: lowest bits of pc set: TODO\n");
-				exit(1);
-			}
-			cpu->pc &= 0xfffffffc;
-			break;
-
-		case ARCH_MIPS:
-			if ((cpu->pc >> 32) == 0 && (cpu->pc & 0x80000000ULL))
-				cpu->pc |= 0xffffffff00000000ULL;
-
-			cpu->cd.mips.gpr[MIPS_GPR_GP] = gp;
-
-			if ((cpu->cd.mips.gpr[MIPS_GPR_GP] >> 32) == 0 &&
-			    (cpu->cd.mips.gpr[MIPS_GPR_GP] & 0x80000000ULL))
-				cpu->cd.mips.gpr[MIPS_GPR_GP] |=
-				    0xffffffff00000000ULL;
-			break;
-
-		case ARCH_PPC:
-			/*  See http://www.linuxbase.org/spec/ELF/ppc64/
-			    spec/x458.html for more info.  */
-			cpu->cd.ppc.gpr[2] = toc;
-			/*  TODO  */
-			if (cpu->cd.ppc.bits == 32)
-				cpu->pc &= 0xffffffffULL;
-			break;
-
-		case ARCH_SH:
-			if (cpu->cd.sh.cpu_type.bits == 32)
-				cpu->pc &= 0xffffffffULL;
-			cpu->pc &= ~1;
-			break;
-
-		default:
-			fatal("emul_machine_setup(): Internal error: "
-			    "Unimplemented arch %i\n", m->arch);
-			exit(1);
-		}
-
-		n_load --;
-		load_names ++;
-	}
-
-	if (m->byte_order_override != NO_BYTE_ORDER_OVERRIDE)
-		cpu->byte_order = m->byte_order_override;
-
-	/*  Same byte order and entrypoint for all CPUs:  */
-	for (i=0; i<m->ncpus; i++)
-		if (i != m->bootstrap_cpu) {
-			m->cpus[i]->byte_order = cpu->byte_order;
-			m->cpus[i]->pc = cpu->pc;
-		}
-
-	/*  Startup the bootstrap CPU:  */
-	cpu->running = 1;
-
-	/*  ... or pause all CPUs, if start_paused is set:  */
-	if (m->start_paused) {
-		for (i=0; i<m->ncpus; i++)
-			m->cpus[i]->running = 0;
-	}
-
-	/*  Parse and add breakpoints:  */
-	add_breakpoints(m);
-
-	/*  TODO: This is MIPS-specific!  */
-	if (m->machine_type == MACHINE_PMAX &&
-	    cpu->cd.mips.cpu_type.mmu_model == MMU3K)
-		add_symbol_name(&m->symbol_context,
-		    0x9fff0000, 0x10000, "r2k3k_cache", 0, 0);
-
-	symbol_recalc_sizes(&m->symbol_context);
-
-	/*  Special hack for ARC/SGI emulation:  */
-	if ((m->machine_type == MACHINE_ARC ||
-	    m->machine_type == MACHINE_SGI) && m->prom_emulation)
-		add_arc_components(m);
-
-	debug("cpu%i: starting at ", m->bootstrap_cpu);
-
-	switch (m->arch) {
-
-	case ARCH_MIPS:
-		if (cpu->is_32bit) {
-			debug("0x%08" PRIx32, (uint32_t)
-			    m->cpus[m->bootstrap_cpu]->pc);
-			if (cpu->cd.mips.gpr[MIPS_GPR_GP] != 0)
-				debug(" (gp=0x%08" PRIx32")", (uint32_t)
-				    m->cpus[m->bootstrap_cpu]->cd.mips.gpr[
-				    MIPS_GPR_GP]);
-		} else {
-			debug("0x%016" PRIx64, (uint64_t)
-			    m->cpus[m->bootstrap_cpu]->pc);
-			if (cpu->cd.mips.gpr[MIPS_GPR_GP] != 0)
-				debug(" (gp=0x%016" PRIx64")", (uint64_t)
-				    cpu->cd.mips.gpr[MIPS_GPR_GP]);
-		}
-		break;
-
-	default:
-		if (cpu->is_32bit)
-			debug("0x%08" PRIx32, (uint32_t) cpu->pc);
-		else
-			debug("0x%016" PRIx64, (uint64_t) cpu->pc);
-	}
-	debug("\n");
-
-	debug_indentation(-iadd);
-}
-
-
-/*
- *  emul_dumpinfo():
- *
- *  Dump info about all machines in an emul.
- */
-void emul_dumpinfo(struct emul *e)
-{
-	int i;
-
-	if (e->net != NULL)
-		net_dumpinfo(e->net);
-
-	for (i = 0; i < e->n_machines; i++) {
-		if (e->n_machines > 1)
-			debug("machine %i: \"%s\"\n", i, e->machines[i]->name);
-		else
-			debug("machine:\n");
-
-		debug_indentation(DEBUG_INDENTATION);
-
-		machine_dumpinfo(e->machines[i]);
-
-		debug_indentation(-DEBUG_INDENTATION);
-	}
-}
-
-
-/*
- *  emul_simple_init():
- *
- *  For a normal setup:
- *
- *	o)  Initialize a network.
- *	o)  Initialize one machine.
- */
-void emul_simple_init(struct emul *emul)
-{
-	int iadd = DEBUG_INDENTATION;
-	struct machine *m;
-
-	if (emul->n_machines != 1) {
-		fprintf(stderr, "emul_simple_init(): n_machines != 1\n");
-		exit(1);
-	}
-
-	m = emul->machines[0];
-
-	debug("Simple setup...\n");
-	debug_indentation(iadd);
-
-	/*  Create a simple network:  */
-	emul->net = net_init(emul, NET_INIT_FLAG_GATEWAY,
-	    NET_DEFAULT_IPV4_MASK,
-	    NET_DEFAULT_IPV4_LEN,
-	    NULL, 0, 0, NULL);
-
-	/*  Create the machine:  */
-	emul_machine_setup(m, extra_argc, extra_argv, 0, NULL);
-
-	debug_indentation(-iadd);
-}
-
-
-/*
- *  emul_create_from_configfile():
- *
- *  Create an emul struct by reading settings from a configuration file.
- */
-struct emul *emul_create_from_configfile(char *fname)
-{
-	int iadd = DEBUG_INDENTATION;
-	struct emul *e = emul_new(fname);
-
-	debug("Creating emulation from configfile \"%s\":\n", fname);
-	debug_indentation(iadd);
-
-	emul_parse_config(e, fname);
-
-	debug_indentation(-iadd);
-	return e;
-}
-
-
-/*
- *  emul_run():
- *
- *	o)  Set up things needed before running an emulation.
- *
- *	o)  Run instructions in all machines.
- *
- *	o)  De-initialize things.
- */
-void emul_run(struct emul *emul)
-{
-	int i = 0, j, go = 1, n, anything;
-
-	atexit(fix_console);
-
-	if (emul == NULL) {
-		fatal("No emulation defined. Aborting.\n");
-		return;
-	}
-
-	if (emul->n_machines == 0) {
-		fatal("No machine(s) defined. Aborting.\n");
-		return;
-	}
-
-	/*  Initialize the interactive debugger:  */
-	debugger_init(emul);
-
-	/*  Run any additional debugger commands before starting:  */
-	if (emul->n_debugger_cmds > 0) {
-		if (i == 0)
-			print_separator_line();
-		for (int k = 0; k < emul->n_debugger_cmds; k ++) {
-			debug("> %s\n", emul->debugger_cmds[k]);
-			debugger_execute_cmd(emul->debugger_cmds[k],
-			    strlen(emul->debugger_cmds[k]));
-		}
-	}
-
-	print_separator_line();
-	debug("\n");
-
-
-	/*
-	 *  console_init_main() makes sure that the terminal is in a
-	 *  reasonable state.
-	 *
-	 *  The SIGINT handler is for CTRL-C  (enter the interactive debugger).
-	 *
-	 *  The SIGCONT handler is invoked whenever the user presses CTRL-Z
-	 *  (or sends SIGSTOP) and then continues. It makes sure that the
-	 *  terminal is in an expected state.
-	 */
-	console_init_main(emul);
-
-	signal(SIGINT, debugger_activate);
-	signal(SIGCONT, console_sigcont);
-
-	/*  Not in verbose mode? Then set quiet_mode.  */
-	if (!verbose)
-		quiet_mode = 1;
-
-
-	/*  Initialize all CPUs in all machines:  */
-	for (j=0; j<emul->n_machines; j++)
-		cpu_run_init(emul->machines[j]);
-
-	/*  TODO: Generalize:  */
-	if (emul->machines[0]->show_trace_tree)
-		cpu_functioncall_trace(emul->machines[0]->cpus[0],
-		    emul->machines[0]->cpus[0]->pc);
-
-	/*  Start emulated clocks:  */
-	timer_start();
-
-
-	/*
-	 *  MAIN LOOP:
-	 *
-	 *  Run all emulations in parallel, running instructions from each
-	 *  cpu in each machine.
-	 */
-	while (go) {
-		struct cpu *bootcpu = emul->machines[0]->cpus[
-		    emul->machines[0]->bootstrap_cpu];
-
-		go = 0;
-
-		/*  Flush X11 and serial console output every now and then:  */
-		if (bootcpu->ninstrs > bootcpu->ninstrs_flush + (1<<19)) {
-			x11_check_event(emul);
-			console_flush();
-			bootcpu->ninstrs_flush = bootcpu->ninstrs;
-		}
-
-		if (bootcpu->ninstrs > bootcpu->ninstrs_show + (1<<25)) {
-			bootcpu->ninstrs_since_gettimeofday +=
-			    (bootcpu->ninstrs - bootcpu->ninstrs_show);
-			cpu_show_cycles(emul->machines[0], 0);
-			bootcpu->ninstrs_show = bootcpu->ninstrs;
-		}
-
-		if (single_step == ENTER_SINGLE_STEPPING) {
-			/*  TODO: Cleanup!  */
-			old_instruction_trace =
-			    emul->machines[0]->instruction_trace;
-			old_quiet_mode = quiet_mode;
-			old_show_trace_tree =
-			    emul->machines[0]->show_trace_tree;
-			emul->machines[0]->instruction_trace = 1;
-			emul->machines[0]->show_trace_tree = 1;
-			quiet_mode = 0;
-			single_step = SINGLE_STEPPING;
-		}
-
-		if (single_step == SINGLE_STEPPING)
-			debugger();
-
-		for (j=0; j<emul->n_machines; j++) {
-			anything = machine_run(emul->machines[j]);
-			if (anything)
-				go = 1;
-		}
-	}
-
-	/*  Stop any running timers:  */
-	timer_stop();
-
-	/*  Deinitialize all CPUs in all machines:  */
-	for (j=0; j<emul->n_machines; j++)
-		cpu_run_deinit(emul->machines[j]);
-
-	/*  force_debugger_at_exit flag set? Then enter the debugger:  */
-	if (force_debugger_at_exit) {
-		quiet_mode = 0;
-		debugger_reset();
-		debugger();
-	}
-
-	/*  Any machine using X11? Then wait before exiting:  */
-	n = 0;
-	for (j=0; j<emul->n_machines; j++)
-		if (emul->machines[j]->x11_md.in_use)
-			n++;
-
-	if (n > 0) {
-		printf("Press enter to quit.\n");
-		while (!console_charavail(MAIN_CONSOLE)) {
-			x11_check_event(emul);
-			usleep(10000);
-		}
-		console_readchar(MAIN_CONSOLE);
-	}
-
-	console_deinit_main();
-}
-
diff -Nru gxemul-0.6.2/src/old_main/emul_parse.cc gxemul-0.7.0+dfsg/src/old_main/emul_parse.cc
--- gxemul-0.6.2/src/old_main/emul_parse.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/old_main/emul_parse.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,751 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Set up an emulation by parsing a config file.
- *
- *  TODO: REWRITE THIS FROM SCRATCH! :-)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "diskimage.h"
-#include "emul.h"
-#include "machine.h"
-#include "misc.h"
-#include "net.h"
-
-
-#define is_word_char(ch)	( \
-	(ch >= 'a' && ch <= 'z') || (ch >= 'A' && ch <= 'Z') || \
-	ch == '_' || ch == '$' || (ch >= '0' && ch <= '9') )
-
-#define	MAX_WORD_LEN		200
-
-#define	EXPECT_WORD			1
-#define	EXPECT_LEFT_PARENTHESIS		2
-#define	EXPECT_RIGHT_PARENTHESIS	4
-
-static int parenthesis_level = 0;
-
-
-/*
- *  read_one_word():
- *
- *  Reads the file f until it has read a complete word. Whitespace is ignored,
- *  and also any exclamation mark ('!') and anything following an exclamation
- *  mark on a line.
- *
- *  Used internally by emul_parse_config().
- */
-static void read_one_word(FILE *f, char *buf, int buflen, int *line,
-	int expect)
-{
-	int ch;
-	int done = 0;
-	int curlen = 0;
-	int in_word = 0;
-
-	while (!done) {
-		if (curlen >= buflen - 1)
-			break;
-
-		ch = fgetc(f);
-		if (ch == EOF)
-			break;
-
-		if (in_word) {
-			if (is_word_char(ch)) {
-				buf[curlen++] = ch;
-				if (curlen == buflen - 1)
-					done = 1;
-				continue;
-			} else {
-				if (ungetc(ch, f) == EOF) {
-					fatal("ungetc() failed?\n");
-					exit(1);
-				}
-				break;
-			}
-		}
-
-		if (ch == '\n') {
-			(*line) ++;
-			continue;
-		}
-
-		if (ch == '\r')
-			continue;
-
-		if (ch == '!') {
-			/*  Skip until newline:  */
-			while (ch != '\n' && ch != EOF)
-				ch = fgetc(f);
-			if (ch == '\n')
-				(*line) ++;
-			continue;
-		}
-
-		if (ch == '{') {
-			int depth = 1;
-
-			/*  Skip until '}':  */
-			while (depth > 0) {
-				ch = fgetc(f);
-				if (ch == '\n')
-					(*line) ++;
-				if (ch == '{')
-					depth ++;
-				if (ch == '}')
-					depth --;
-				if (ch == EOF) {
-					fatal("line %i: unexpected EOF inside"
-					    " a nested comment\n", *line);
-					exit(1);
-				}
-			}
-			continue;
-		}
-
-		/*  Whitespace?  */
-		if (ch <= ' ')
-			continue;
-
-		if (ch == '"' || ch == '\'') {
-			/*  This is a quoted word.  */
-			int start_ch = ch;
-
-			if (expect & EXPECT_LEFT_PARENTHESIS) {
-				fatal("unexpected character '%c', line %i\n",
-				    ch, *line);
-				exit(1);
-			}
-
-			while (curlen < buflen - 1) {
-				ch = fgetc(f);
-				if (ch == '\n') {
-					fatal("line %i: newline inside"
-					    " quotes?\n", *line);
-					exit(1);
-				}
-				if (ch == EOF) {
-					fatal("line %i: EOF inside a quoted"
-					    " string?\n", *line);
-					exit(1);
-				}
-				if (ch == start_ch)
-					break;
-				buf[curlen++] = ch;
-			}
-			break;
-		}
-
-		if ((expect & EXPECT_WORD) && is_word_char(ch)) {
-			buf[curlen++] = ch;
-			in_word = 1;
-			if (curlen == buflen - 1)
-				done = 1;
-		} else {
-			if ((expect & EXPECT_LEFT_PARENTHESIS) && ch == '(') {
-				parenthesis_level ++;
-				buf[curlen++] = ch;
-				break;
-			}
-			if ((expect & EXPECT_RIGHT_PARENTHESIS) && ch == ')') {
-				parenthesis_level --;
-				buf[curlen++] = ch;
-				break;
-			}
-
-			fatal("unexpected character '%c', line %i\n",
-			    ch, *line);
-			exit(1);
-		}
-	}
-
-	buf[curlen] = '\0';
-}
-
-
-#define	PARSESTATE_NONE			0
-#define	PARSESTATE_EMUL			1
-#define	PARSESTATE_NET			2
-#define	PARSESTATE_MACHINE		3
-
-static char cur_net_ipv4net[50];
-static char cur_net_ipv4len[50];
-static char cur_net_local_port[10];
-#define	MAX_N_REMOTE		20
-#define	MAX_REMOTE_LEN		100
-static char *cur_net_remote[MAX_N_REMOTE];
-static int cur_net_n_remote;
-
-static char cur_machine_name[50];
-static char cur_machine_cpu[50];
-static char cur_machine_type[50];
-static char cur_machine_subtype[50];
-static char cur_machine_bootname[150];
-static char cur_machine_bootarg[250];
-static char cur_machine_slowsi[10];
-static char cur_machine_prom_emulation[10];
-static char cur_machine_use_x11[10];
-static char cur_machine_x11_scaledown[10];
-static char cur_machine_byte_order[20];
-static char cur_machine_random_mem[10];
-static char cur_machine_random_cpu[10];
-static char cur_machine_force_netboot[10];
-static char cur_machine_start_paused[10];
-static char cur_machine_ncpus[10];
-static char cur_machine_n_gfx_cards[10];
-static char cur_machine_serial_nr[10];
-static char cur_machine_emulated_hz[10];
-static char cur_machine_memory[10];
-#define	MAX_N_LOAD		15
-#define	MAX_LOAD_LEN		2000
-static char *cur_machine_load[MAX_N_LOAD];
-static int cur_machine_n_load;
-#define	MAX_N_DISK		10
-#define	MAX_DISK_LEN		2000
-static char *cur_machine_disk[MAX_N_DISK];
-static int cur_machine_n_disk;
-#define	MAX_N_DEVICE		20
-#define	MAX_DEVICE_LEN		400
-static char *cur_machine_device[MAX_N_DISK];
-static int cur_machine_n_device;
-#define	MAX_N_X11_DISP		5
-#define	MAX_X11_DISP_LEN	1000
-static char *cur_machine_x11_disp[MAX_N_X11_DISP];
-static int cur_machine_n_x11_disp;
-
-#define WORD(w,var) {						\
-		if (strcmp(word, w) == 0) {			\
-			read_one_word(f, word, maxbuflen,	\
-			    line, EXPECT_LEFT_PARENTHESIS);	\
-			read_one_word(f, var, sizeof(var),	\
-			    line, EXPECT_WORD);			\
-			read_one_word(f, word, maxbuflen,	\
-			    line, EXPECT_RIGHT_PARENTHESIS);	\
-			return;					\
-		}						\
-	}
-
-static void parse__machine(struct emul *e, FILE *f, int *in_emul, int *line,
-	int *parsestate, char *word, size_t maxbuflen);
-
-
-/*
- *  parse_on_off():
- *
- *  Returns 1 for "on", "yes", "enable", or "1".
- *  Returns 0 for "off", "no", "disable", or "0".
- *  Prints a fatal warning and exit()s for other values.
- */
-int parse_on_off(char *s)
-{
-	if (strcasecmp(s, "on") == 0 || strcasecmp(s, "yes") == 0 ||
-	    strcasecmp(s, "enable") == 0 || strcasecmp(s, "1") == 0)
-		return 1;
-	if (strcasecmp(s, "off") == 0 || strcasecmp(s, "no") == 0 ||
-	    strcasecmp(s, "disable") == 0 || strcasecmp(s, "0") == 0)
-		return 0;
-
-	fprintf(stderr, "parse_on_off(): WARNING: unknown value '%s'\n", s);
-
-	return 0;
-}
-
-
-/*
- *  parse__emul():
- *
- *  name, net, machine
- */
-static void parse__emul(struct emul *e, FILE *f, int *in_emul, int *line,
-	int *parsestate, char *word, size_t maxbuflen)
-{
-	if (word[0] == ')') {
-		*parsestate = PARSESTATE_NONE;
-		return;
-	}
-
-	if (strcmp(word, "name") == 0) {
-		char tmp[200];
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_LEFT_PARENTHESIS);
-		read_one_word(f, tmp, sizeof(tmp), line, EXPECT_WORD);
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_RIGHT_PARENTHESIS);
-		if (e->name != NULL) {
-			free(e->name);
-			e->name = NULL;
-		}
-		CHECK_ALLOCATION(e->name = strdup(tmp));
-		debug("name: \"%s\"\n", e->name);
-		return;
-	}
-
-	if (strcmp(word, "net") == 0) {
-		*parsestate = PARSESTATE_NET;
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_LEFT_PARENTHESIS);
-
-		/*  Default net:  */
-		strlcpy(cur_net_ipv4net, NET_DEFAULT_IPV4_MASK,
-		    sizeof(cur_net_ipv4net));
-		snprintf(cur_net_ipv4len, sizeof(cur_net_ipv4len), "%i",
-		    NET_DEFAULT_IPV4_LEN);
-		strlcpy(cur_net_local_port, "", sizeof(cur_net_local_port));
-		cur_net_n_remote = 0;
-		return;
-	}
-
-	if (strcmp(word, "machine") == 0) {
-		*parsestate = PARSESTATE_MACHINE;
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_LEFT_PARENTHESIS);
-
-		/*  A "zero state":  */
-		cur_machine_name[0] = '\0';
-		cur_machine_cpu[0] = '\0';
-		cur_machine_type[0] = '\0';
-		cur_machine_subtype[0] = '\0';
-		cur_machine_bootname[0] = '\0';
-		cur_machine_bootarg[0] = '\0';
-		cur_machine_n_load = 0;
-		cur_machine_n_disk = 0;
-		cur_machine_n_device = 0;
-		cur_machine_n_x11_disp = 0;
-		cur_machine_slowsi[0] = '\0';
-		cur_machine_prom_emulation[0] = '\0';
-		cur_machine_use_x11[0] = '\0';
-		cur_machine_x11_scaledown[0] = '\0';
-		cur_machine_byte_order[0] = '\0';
-		cur_machine_random_mem[0] = '\0';
-		cur_machine_random_cpu[0] = '\0';
-		cur_machine_force_netboot[0] = '\0';
-		cur_machine_start_paused[0] = '\0';
-		cur_machine_ncpus[0] = '\0';
-		cur_machine_n_gfx_cards[0] = '\0';
-		cur_machine_serial_nr[0] = '\0';
-		cur_machine_emulated_hz[0] = '\0';
-		cur_machine_memory[0] = '\0';
-		return;
-	}
-
-	fatal("line %i: not expecting '%s' in an 'emul' section\n",
-	    *line, word);
-	exit(1);
-}
-
-
-/*
- *  parse__net():
- *
- *  Simple words: ipv4net, ipv4len, local_port
- *
- *  Complex: add_remote
- *
- *  TODO: more words? for example an option to disable the gateway? that would
- *  have to be implemented correctly in src/net.c first.
- */
-static void parse__net(struct emul *e, FILE *f, int *in_emul, int *line,
-	int *parsestate, char *word, size_t maxbuflen)
-{
-	int i;
-
-	if (word[0] == ')') {
-		/*  Finished with the 'net' section. Let's create the net:  */
-		if (e->net != NULL) {
-			fatal("line %i: more than one net isn't really "
-			    "supported yet\n", *line);
-			exit(1);
-		}
-
-		if (!cur_net_local_port[0])
-			strlcpy(cur_net_local_port, "0",
-			    sizeof(cur_net_local_port));
-
-		e->net = net_init(e, NET_INIT_FLAG_GATEWAY,
-		    cur_net_ipv4net, atoi(cur_net_ipv4len),
-		    cur_net_remote, cur_net_n_remote,
-		    atoi(cur_net_local_port), NULL);
-
-		if (e->net == NULL) {
-			fatal("line %i: fatal error: could not create"
-			    " the net (?)\n", *line);
-			exit(1);
-		}
-
-		for (i=0; i<cur_net_n_remote; i++) {
-			free(cur_net_remote[i]);
-			cur_net_remote[i] = NULL;
-		}
-
-		*parsestate = PARSESTATE_EMUL;
-		return;
-	}
-
-	WORD("ipv4net", cur_net_ipv4net);
-	WORD("ipv4len", cur_net_ipv4len);
-	WORD("local_port", cur_net_local_port);
-
-	if (strcmp(word, "add_remote") == 0) {
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_LEFT_PARENTHESIS);
-		if (cur_net_n_remote >= MAX_N_REMOTE) {
-			fprintf(stderr, "too many remote networks\n");
-			exit(1);
-		}
-
-		CHECK_ALLOCATION(cur_net_remote[cur_net_n_remote] =
-		    (char *) malloc(MAX_REMOTE_LEN));
-		read_one_word(f, cur_net_remote[cur_net_n_remote],
-		    MAX_REMOTE_LEN, line, EXPECT_WORD);
-		cur_net_n_remote ++;
-		read_one_word(f, word, maxbuflen, line,
-		    EXPECT_RIGHT_PARENTHESIS);
-		return;
-	}
-
-	fatal("line %i: not expecting '%s' in a 'net' section\n", *line, word);
-	exit(1);
-}
-
-
-/*
- *  parse__machine():
- */
-static void parse__machine(struct emul *e, FILE *f, int *in_emul, int *line,
-	int *parsestate, char *word, size_t maxbuflen)
-{
-	int r, i;
-
-	if (word[0] == ')') {
-		/*  Finished with the 'machine' section.  */
-		struct machine *m;
-
-		if (!cur_machine_name[0])
-			strlcpy(cur_machine_name, "no_name",
-			    sizeof(cur_machine_name));
-
-		m = emul_add_machine(e, cur_machine_name);
-
-		r = machine_name_to_type(cur_machine_type, cur_machine_subtype,
-		    &m->machine_type, &m->machine_subtype, &m->arch);
-		if (!r)
-			exit(1);
-
-		if (cur_machine_cpu[0])
-			CHECK_ALLOCATION(m->cpu_name = strdup(cur_machine_cpu));
-
-		if (!cur_machine_use_x11[0])
-			strlcpy(cur_machine_use_x11, "no",
-			    sizeof(cur_machine_use_x11));
-		m->x11_md.in_use = parse_on_off(cur_machine_use_x11);
-
-		if (!cur_machine_slowsi[0])
-			strlcpy(cur_machine_slowsi, "no",
-			    sizeof(cur_machine_slowsi));
-		m->slow_serial_interrupts_hack_for_linux =
-		    parse_on_off(cur_machine_slowsi);
-
-		if (!cur_machine_prom_emulation[0])
-			strlcpy(cur_machine_prom_emulation, "yes",
-			    sizeof(cur_machine_prom_emulation));
-		m->prom_emulation = parse_on_off(cur_machine_prom_emulation);
-
-		if (!cur_machine_random_mem[0])
-			strlcpy(cur_machine_random_mem, "no",
-			    sizeof(cur_machine_random_mem));
-		m->random_mem_contents =
-		    parse_on_off(cur_machine_random_mem);
-
-		if (!cur_machine_random_cpu[0])
-			strlcpy(cur_machine_random_cpu, "no",
-			    sizeof(cur_machine_random_cpu));
-		m->use_random_bootstrap_cpu =
-		    parse_on_off(cur_machine_random_cpu);
-
-		m->byte_order_override = NO_BYTE_ORDER_OVERRIDE;
-		if (cur_machine_byte_order[0]) {
-			if (strncasecmp(cur_machine_byte_order, "big", 3) == 0)
-				m->byte_order_override = EMUL_BIG_ENDIAN;
-			else if (strncasecmp(cur_machine_byte_order, "little",
-			    6) == 0)
-				m->byte_order_override = EMUL_LITTLE_ENDIAN;
-			else {
-				fatal("Byte order must be big-endian or"
-				    " little-endian\n");
-				exit(1);
-			}
-		}
-
-		if (!cur_machine_force_netboot[0])
-			strlcpy(cur_machine_force_netboot, "no",
-			    sizeof(cur_machine_force_netboot));
-		m->force_netboot = parse_on_off(cur_machine_force_netboot);
-
-		if (!cur_machine_start_paused[0])
-			strlcpy(cur_machine_start_paused, "no",
-			    sizeof(cur_machine_start_paused));
-		m->start_paused = parse_on_off(cur_machine_start_paused);
-
-		/*  NOTE: Default nr of CPUs is 0:  */
-		if (!cur_machine_ncpus[0])
-			strlcpy(cur_machine_ncpus, "0",
-			    sizeof(cur_machine_ncpus));
-		m->ncpus = atoi(cur_machine_ncpus);
-
-		if (cur_machine_n_gfx_cards[0])
-			m->n_gfx_cards = atoi(cur_machine_n_gfx_cards);
-
-		if (cur_machine_serial_nr[0]) {
-			m->serial_nr = atoi(cur_machine_serial_nr);
-			e->next_serial_nr = m->serial_nr+1;
-		}
-
-		if (cur_machine_emulated_hz[0]) {
-			m->emulated_hz = mystrtoull(cur_machine_emulated_hz,
-			    NULL, 0);
-		}
-
-		/*  NOTE: Default nr of CPUs is 0:  */
-		if (!cur_machine_memory[0])
-			strlcpy(cur_machine_memory, "0",
-			    sizeof(cur_machine_memory));
-		m->physical_ram_in_mb = atoi(cur_machine_memory);
-
-		if (!cur_machine_x11_scaledown[0])
-			m->x11_md.scaledown = 1;
-		else {
-			m->x11_md.scaledown = atoi(cur_machine_x11_scaledown);
-			if (m->x11_md.scaledown < 0) {
-				m->x11_md.scaleup = 0 - m->x11_md.scaledown;
-				m->x11_md.scaledown = 1;
-			}
-			if (m->x11_md.scaledown < 1) {
-				fprintf(stderr, "Invalid scaledown value"
-				    " (%i)\n", m->x11_md.scaledown);
-				exit(1);
-			}
-		}
-
-		for (i=0; i<cur_machine_n_disk; i++) {
-			diskimage_add(m, cur_machine_disk[i]);
-			free(cur_machine_disk[i]);
-			cur_machine_disk[i] = NULL;
-		}
-
-		m->boot_kernel_filename = strdup(cur_machine_bootname);
-
-		if (cur_machine_bootarg[0])
-			m->boot_string_argument = strdup(cur_machine_bootarg);
-
-		for (i=0; i<cur_machine_n_x11_disp; i++) {
-			m->x11_md.n_display_names ++;
-			CHECK_ALLOCATION(m->x11_md.display_names = (char **) realloc(
-			    m->x11_md.display_names, m->x11_md.n_display_names
-			    * sizeof(char *)));
-			CHECK_ALLOCATION(m->x11_md.display_names[
-			    m->x11_md.n_display_names-1] =
-			    strdup(cur_machine_x11_disp[i]));
-			free(cur_machine_x11_disp[i]);
-			cur_machine_x11_disp[i] = NULL;
-		}
-
-		emul_machine_setup(m,
-		    cur_machine_n_load, cur_machine_load,
-		    cur_machine_n_device, cur_machine_device);
-
-		for (i=0; i<cur_machine_n_device; i++) {
-			free(cur_machine_device[i]);
-			cur_machine_device[i] = NULL;
-		}
-
-		for (i=0; i<cur_machine_n_load; i++) {
-			free(cur_machine_load[i]);
-			cur_machine_load[i] = NULL;
-		}
-
-		*parsestate = PARSESTATE_EMUL;
-		return;
-	}
-
-	WORD("name", cur_machine_name);
-	WORD("cpu", cur_machine_cpu);
-	WORD("type", cur_machine_type);
-	WORD("subtype", cur_machine_subtype);
-	WORD("bootname", cur_machine_bootname);
-	WORD("bootarg", cur_machine_bootarg);
-	WORD("slow_serial_interrupts_hack_for_linux", cur_machine_slowsi);
-	WORD("prom_emulation", cur_machine_prom_emulation);
-	WORD("use_x11", cur_machine_use_x11);
-	WORD("x11_scaledown", cur_machine_x11_scaledown);
-	WORD("byte_order", cur_machine_byte_order);
-	WORD("random_mem_contents", cur_machine_random_mem);
-	WORD("use_random_bootstrap_cpu", cur_machine_random_cpu);
-	WORD("force_netboot", cur_machine_force_netboot);
-	WORD("ncpus", cur_machine_ncpus);
-	WORD("serial_nr", cur_machine_serial_nr);
-	WORD("n_gfx_cards", cur_machine_n_gfx_cards);
-	WORD("emulated_hz", cur_machine_emulated_hz);
-	WORD("memory", cur_machine_memory);
-	WORD("start_paused", cur_machine_start_paused);
-
-	if (strcmp(word, "load") == 0) {
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_LEFT_PARENTHESIS);
-		if (cur_machine_n_load >= MAX_N_LOAD) {
-			fprintf(stderr, "too many loads\n");
-			exit(1);
-		}
-		CHECK_ALLOCATION(cur_machine_load[cur_machine_n_load] =
-		    (char*) malloc(MAX_LOAD_LEN));
-		read_one_word(f, cur_machine_load[cur_machine_n_load],
-		    MAX_LOAD_LEN, line, EXPECT_WORD);
-		cur_machine_n_load ++;
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_RIGHT_PARENTHESIS);
-		return;
-	}
-
-	if (strcmp(word, "disk") == 0) {
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_LEFT_PARENTHESIS);
-		if (cur_machine_n_disk >= MAX_N_DISK) {
-			fprintf(stderr, "too many disks\n");
-			exit(1);
-		}
-		CHECK_ALLOCATION(cur_machine_disk[cur_machine_n_disk] =
-		    (char*) malloc(MAX_DISK_LEN));
-		read_one_word(f, cur_machine_disk[cur_machine_n_disk],
-		    MAX_DISK_LEN, line, EXPECT_WORD);
-		cur_machine_n_disk ++;
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_RIGHT_PARENTHESIS);
-		return;
-	}
-
-	if (strcmp(word, "device") == 0) {
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_LEFT_PARENTHESIS);
-		if (cur_machine_n_device >= MAX_N_DEVICE) {
-			fprintf(stderr, "too many devices\n");
-			exit(1);
-		}
-		CHECK_ALLOCATION(cur_machine_device[cur_machine_n_device] =
-		    (char*) malloc(MAX_DEVICE_LEN));
-		read_one_word(f, cur_machine_device[cur_machine_n_device],
-		    MAX_DEVICE_LEN, line, EXPECT_WORD);
-		cur_machine_n_device ++;
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_RIGHT_PARENTHESIS);
-		return;
-	}
-
-	if (strcmp(word, "add_x11_display") == 0) {
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_LEFT_PARENTHESIS);
-		if (cur_machine_n_x11_disp >= MAX_N_X11_DISP) {
-			fprintf(stderr, "too many x11 displays\n");
-			exit(1);
-		}
-		CHECK_ALLOCATION(cur_machine_x11_disp[cur_machine_n_x11_disp] =
-		    (char*) malloc(MAX_X11_DISP_LEN));
-		read_one_word(f, cur_machine_x11_disp[cur_machine_n_x11_disp],
-		    MAX_X11_DISP_LEN, line, EXPECT_WORD);
-		cur_machine_n_x11_disp ++;
-		read_one_word(f, word, maxbuflen,
-		    line, EXPECT_RIGHT_PARENTHESIS);
-		return;
-	}
-
-	fatal("line %i: not expecting '%s' in a 'machine' section\n",
-	    *line, word);
-	exit(1);
-}
-
-
-/*
- *  emul_parse_config():
- *
- *  Set up an emulation by parsing a config file.
- */
-void emul_parse_config(struct emul *e, char *fname)
-{
-	FILE *f = fopen(fname, "r");
-	char word[MAX_WORD_LEN];
-	int in_emul = 0;
-	int line = 1;
-	int parsestate = PARSESTATE_EMUL;
-
-	/*  debug("emul_parse_config()\n");  */
-	if (f == NULL) {
-		perror(fname);
-		exit(1);
-	}
-
-	while (!feof(f)) {
-		read_one_word(f, word, sizeof(word), &line,
-		    EXPECT_WORD | EXPECT_RIGHT_PARENTHESIS);
-		if (!word[0])
-			break;
-
-		/*  debug("word = '%s'\n", word);  */
-
-		switch (parsestate) {
-		case PARSESTATE_EMUL:
-			parse__emul(e, f, &in_emul, &line, &parsestate,
-			    word, sizeof(word));
-			break;
-		case PARSESTATE_NET:
-			parse__net(e, f, &in_emul, &line, &parsestate,
-			    word, sizeof(word));
-			break;
-		case PARSESTATE_MACHINE:
-			parse__machine(e, f, &in_emul, &line, &parsestate,
-			    word, sizeof(word));
-			break;
-		case PARSESTATE_NONE:
-			break;
-		default:
-			fatal("INTERNAL ERROR in emul_parse.c ("
-			    "parsestate %i is not imlemented yet?)\n",
-			    parsestate);
-			exit(1);
-		}
-	}
-
-	if (parenthesis_level != 0) {
-		fatal("EOF but not enough right parentheses?\n");
-		exit(1);
-	}
-
-	fclose(f);
-}
-
diff -Nru gxemul-0.6.2/src/old_main/float_emul.cc gxemul-0.7.0+dfsg/src/old_main/float_emul.cc
--- gxemul-0.6.2/src/old_main/float_emul.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/old_main/float_emul.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,350 +0,0 @@
-/*
- *  Copyright (C) 2004-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Floating point emulation routines.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#include "float_emul.h"
-#include "misc.h"
-
-
-/*  #define IEEE_DEBUG  */
-
-
-/*
- *  ieee_interpret_float_value():
- *
- *  Interprets a float value from binary IEEE format into an ieee_float_value
- *  struct.
- */
-void ieee_interpret_float_value(uint64_t x, struct ieee_float_value *fvp,
-	int fmt)
-{
-	memset(fvp, 0, sizeof(struct ieee_float_value));
-
-#if 0
-	// HACK: Use the host's float/double representation:
-	switch (fmt) {
-	case IEEE_FMT_S:
-		{
-			uint32_t x2 = x;
-			void* p = (void*) &x2;
-			float *pf = (float*) p;
-			fvp->f = *pf;
-		}
-		break;
-
-	case IEEE_FMT_D:
-		{
-			void* p = (void*) &x;
-			double *pf = (double*) p;
-			fvp->f = *pf;
-		}
-		break;
-
-	case IEEE_FMT_W:
-	case IEEE_FMT_L:
-		{
-			fvp->f = x;
-		}
-		break;
-
-	default:fatal("ieee_interpret_float_value(): "
-		    "unimplemented format %i\n", fmt);
-	}
-
-	fvp->nan = isnan(fvp->f);
-#else
-	int n_frac = 0, n_exp = 0;
-	int i, nan, sign = 0, exponent;
-	double fraction;
-
-	/*  n_frac and n_exp:  */
-	switch (fmt) {
-	case IEEE_FMT_S:	n_frac = 23; n_exp = 8; break;
-	case IEEE_FMT_W:	n_frac = 31; n_exp = 0; break;
-	case IEEE_FMT_D:	n_frac = 52; n_exp = 11; break;
-	case IEEE_FMT_L:	n_frac = 63; n_exp = 0; break;
-	default:fatal("ieee_interpret_float_value(): "
-		    "unimplemented format %i\n", fmt);
-	}
-
-	/*  Get the Exponent:  */
-	exponent = 0;
-	switch (fmt) {
-	case IEEE_FMT_W:
-		x &= 0xffffffffULL;
-	case IEEE_FMT_L:
-		break;
-	case IEEE_FMT_S:
-		x &= 0xffffffffULL;
-	case IEEE_FMT_D:
-		exponent = (x >> n_frac) & ((1 << n_exp) - 1);
-		exponent -= (1 << (n_exp-1)) - 1;
-		break;
-	default:fatal("ieee_interpret_float_value(): unimplemented "
-		    "format %i\n", fmt);
-	}
-
-	/*  Is this a Not-A-Number?  */
-	nan = 0;
-	switch (fmt) {
-	case IEEE_FMT_S:
-		sign = (x >> 31) & 1;
-		if ((x & ~0x80000000ULL) == 0x7f800000ULL) {
-			fvp->f = 1.0 / 0.0;
-			goto zero_or_no_reasonable_result;
-		}
-		if ((x & 0x7f800000ULL) == 0x7f800000ULL)
-			nan = 1;
-		break;
-	case IEEE_FMT_D:
-		sign = (x >> 63) & 1;
-		if ((x & ~0x8000000000000000ULL) == 0x7ff0000000000000ULL) {
-			fvp->f = 1.0 / 0.0;
-			goto zero_or_no_reasonable_result;
-		}
-		if ((x & 0x7ff0000000000000ULL) == 0x7ff0000000000000ULL)
-			nan = 1;
-		break;
-	}
-
-	if (nan) {
-		fvp->f = NAN;
-		goto no_reasonable_result;
-	}
-
-	/*  Calculate the fraction:  */
-	fraction = 0.0;
-
-	switch (fmt) {
-
-	case IEEE_FMT_W:
-		{
-			int32_t r_int = x;
-			fraction = r_int;
-		}
-		break;
-
-	case IEEE_FMT_L:
-		{
-			int64_t r_int = x;
-			fraction = r_int;
-		}
-		break;
-
-	case IEEE_FMT_S:
-	case IEEE_FMT_D:
-		if (x == 0 ||
-		    (fmt == IEEE_FMT_D && x == 0x8000000000000000ULL) ||
-		    (fmt == IEEE_FMT_S && x == 0x80000000ULL)) {
-			fvp->f = 0.0;
-			goto zero_or_no_reasonable_result;
-		}
-
-		fraction = 0.0;
-		for (i=0; i<n_frac; i++) {
-			int bit = (x >> i) & 1;
-			fraction /= 2.0;
-			if (bit)
-				fraction += 1.0;
-		}
-
-		/*  Add implicit bit 0:  */
-		fraction = (fraction / 2.0) + 1.0;
-		break;
-
-	default:fatal("ieee_interpret_float_value(): "
-		    "unimplemented format %i\n", fmt);
-	}
-
-	/*  form the value:  */
-	fvp->f = fraction;
-
-#ifdef IEEE_DEBUG
-	fatal("{ ieee: x=%016"PRIx64" => sign=%i exponent=%i frac=%f ",
-	    (uint64_t) x, sign, exponent, fraction);
-#endif
-
-	/*  TODO: this is awful for exponents of large magnitude.  */
-	if (exponent > 0) {
-		/*
-		 *  NOTE / TODO:
-		 *
-		 *  This is an ulgy workaround on Alpha, where it seems that
-		 *  multiplying by 2, 1024 times causes a floating point
-		 *  exception. (Triggered by running for example NetBSD/pmax
-		 *  2.0 emulated on an Alpha host.)
-		 */
-		if (exponent == 1024)
-			exponent = 1023;
-
-		while (exponent-- > 0)
-			fvp->f *= 2.0;
-	} else if (exponent < 0) {
-		while (exponent++ < 0)
-			fvp->f /= 2.0;
-	}
-
-zero_or_no_reasonable_result:
-	if (sign)
-		fvp->f = -fvp->f;
-
-no_reasonable_result:
-	fvp->nan = nan;
-
-#ifdef IEEE_DEBUG
-	fatal("nan=%i (f=%f) }\n", nan, fvp->f);
-#endif
-
-#endif
-}
-
-
-/*
- *  ieee_store_float_value():
- *
- *  Generates a 64-bit IEEE-formated value in a specific format.
- */
-uint64_t ieee_store_float_value(double nf, int fmt)
-{
-	int n_frac = 0, n_exp = 0, signofs = 0, i, exponent;
-	uint64_t r = 0, r2;
-	int64_t r3;
-
-	/*  n_frac and n_exp:  */
-	switch (fmt) {
-	case IEEE_FMT_S:	n_frac = 23; n_exp = 8; signofs = 31; break;
-	case IEEE_FMT_W:	n_frac = 31; n_exp = 0; signofs = 31; break;
-	case IEEE_FMT_D:	n_frac = 52; n_exp = 11; signofs = 63; break;
-	case IEEE_FMT_L:	n_frac = 63; n_exp = 0; signofs = 63; break;
-	default:fatal("ieee_store_float_value(): unimplemented format"
-		    " %i\n", fmt);
-	}
-
-	switch (fmt) {
-	case IEEE_FMT_W:
-	case IEEE_FMT_L:
-		/*
-		 *  This causes an implicit conversion of double to integer.
-		 *  If nf < 0.0, then r2 will begin with a sequence of binary
-		 *  1's, which is ok.
-		 */
-		r3 = (int64_t) nf;
-		r2 = r3;
-		r |= r2;
-		break;
-	case IEEE_FMT_S:
-	case IEEE_FMT_D:
-		/*  sign bit:  */
-		if (signbit(nf)) {
-			r |= ((uint64_t)1 << signofs);
-		}
-
-		// printf("fpclassify(nf) = %i\n", fpclassify(nf));
-		switch (fpclassify(nf)) {
-		case FP_INFINITE:
-			if (fmt == IEEE_FMT_D)
-				r |= 0x7ff0000000000000ULL;
-			else
-				r |= 0x7f800000ULL;
-			break;
-		case FP_NAN:
-			if (fmt == IEEE_FMT_D)
-				r |= 0x7fffffffffffffffULL;
-			else
-				r |= 0x7fffffffULL;
-			break;
-		case FP_NORMAL:
-			if (signbit(nf))
-				nf = -nf;
-
-			/*
-			 *  How to convert back from double to exponent + fraction:
-			 *  The fraction should be 1.xxx, that is
-			 *  1.0 <= fraction < 2.0
-			 *
-			 *  This method is very slow but should work:
-			 *  (TODO: Fix the performance problem!)
-			 */
-			exponent = 0;
-			while (nf < 1.0 && exponent > -1023) {
-				nf *= 2.0;
-				exponent --;
-			}
-			while (nf >= 2.0 && exponent < 1023) {
-				nf /= 2.0;
-				exponent ++;
-			}
-
-			/*  Here:   1.0 <= nf < 2.0  */
-			nf -= 1.0;	/*  remove implicit first bit  */
-			for (i=n_frac-1; i>=0; i--) {
-				nf *= 2.0;
-				if (nf >= 1.0) {
-					r |= ((uint64_t)1 << i);
-					nf -= 1.0;
-				}
-			}
-
-			/*  Insert the exponent into the resulting word:  */
-			/*  (First bias, then make sure it's within range)  */
-			exponent += (((uint64_t)1 << (n_exp-1)) - 1);
-			if (exponent < 0)
-				exponent = 0;
-			if (exponent >= ((int64_t)1 << n_exp))
-				exponent = ((int64_t)1 << n_exp) - 1;
-			r |= (uint64_t)exponent << n_frac;
-
-			/*  Special case for 0.0:  */
-			if (exponent == 0)
-				r = 0;
-			break;
-		case FP_SUBNORMAL:
-			// TODO
-			break;
-		case FP_ZERO:
-			// r already has zeros in the lowest bits. Done.
-			break;
-		}
-		break;
-	default:/*  TODO  */
-		fatal("ieee_store_float_value(): unimplemented format %i\n",
-		    fmt);
-	}
-
-	if (fmt == IEEE_FMT_S || fmt == IEEE_FMT_W)
-		r = (uint32_t) r;
-
-	return r;
-}
-
diff -Nru gxemul-0.6.2/src/old_main/interrupt.cc gxemul-0.7.0+dfsg/src/old_main/interrupt.cc
--- gxemul-0.6.2/src/old_main/interrupt.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/old_main/interrupt.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,286 +0,0 @@
-/*
- *  Copyright (C) 2006-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  The interrupt subsystem.
- *
- *  Interrupts have a "path", e.g. "machine[0].cpu.5". A device which
- *  wishes to cause this interrupt needs to connect to it.
- *
- *  The possible interrupt paths are registered by CPUs, interrupt controllers,
- *  etc., that have a way of receiving interrupt requests. The physical
- *  version of an interrupt path is usually a "pin" on the CPU, or similar.
- *
- *  Once connected, the interrupt can be asserted or deasserted.
- *
- *  For examples on how it is used, see the various devices in src/devices/.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "interrupt.h"
-#include "misc.h"
-
-
-/*  #define INTERRUPT_DEBUG  */
-
-
-struct interrupt_handler {
-	struct interrupt	templ;
-	int			nr_of_exclusive_users;
-	int			nr_of_nonexclusive_users;
-};
-
-
-static int nr_of_interrupt_handlers = 0;
-static struct interrupt_handler *interrupt_handlers = NULL;
-
-
-/*
- *  Dummy interrupt assert/deassert for "no interrupt" interrupts:
- */
-static void no_interrupt_assert(struct interrupt *i) { }
-static void no_interrupt_deassert(struct interrupt *i) { }
-
-
-/*
- *  interrupt_handler_register():
- *
- *  Add an interrupt handler to the interrupt subsystem. The template
- *  needs to have all members set.
- *
- *  Name is of the form "machine[0].cpu[0].irq[3].isa[14]" etc.
- *
- *  If there already is a handler with this name, the emulator aborts.
- */
-void interrupt_handler_register(struct interrupt *templ)
-{
-	int i;
-
-#ifdef INTERRUPT_DEBUG
-	printf("interrupt_handler_register(\"%s\")\n", templ->name);
-#endif
-
-	/*  See if the name is already registered:  */
-	for (i=0; i<nr_of_interrupt_handlers; i++) {
-		if (strcmp(templ->name,
-		    interrupt_handlers[i].templ.name) != 0)
-			continue;
-
-		fatal("\ninterrupt_handler_register(): An interrupt handler"
-		    " using the name '%s' is already registered.\n",
-		    templ->name);
-		exit(1);
-	}
-
-	nr_of_interrupt_handlers ++;
-	CHECK_ALLOCATION(interrupt_handlers = 
-	    (struct interrupt_handler *) realloc(interrupt_handlers,
-	    nr_of_interrupt_handlers * sizeof(struct interrupt_handler)));
-
-	interrupt_handlers[nr_of_interrupt_handlers-1].templ = *templ;
-	CHECK_ALLOCATION(interrupt_handlers[nr_of_interrupt_handlers-1].
-	    templ.name = strdup(templ->name));
-}
-
-
-/*
- *  interrupt_handler_remove():
- *
- *  Remove an interrupt handler from the interrupt subsystem. If there are
- *  still connected users of this interrupt, then an error message is printed
- *  and the emulator aborts.
- */
-void interrupt_handler_remove(const char *name)
-{
-	int i;
-
-#ifdef INTERRUPT_DEBUG
-	printf("interrupt_handler_remove(\"%s\")\n", name);
-#endif
-
-	for (i=0; i<nr_of_interrupt_handlers; i++) {
-		if (strcmp(name, interrupt_handlers[i].templ.name) != 0)
-			continue;
-
-		/*
-		 *  Remove handler i, and return:
-		 */
-		if (interrupt_handlers[i].nr_of_exclusive_users > 0 ||
-		    interrupt_handlers[i].nr_of_nonexclusive_users > 0) {
-			fatal("interrupt_handler_remove(): Attempt to "
-			    "remove interrupt handler '%s' which has %i "
-			    "exclusive and %i non-exclusive users. Aborting.\n",
-			    name, interrupt_handlers[i].nr_of_exclusive_users,
-			    interrupt_handlers[i].nr_of_nonexclusive_users);
-			exit(1);
-		}
-
-		if (i != nr_of_interrupt_handlers-1)
-			memcpy(&interrupt_handlers[i],
-			    &interrupt_handlers[i + 1],
-			    nr_of_interrupt_handlers - i - 1);
-
-		nr_of_interrupt_handlers --;
-
-		return;
-	}
-
-	fatal("interrupt_handler_remove(): '%s' not found? Aborting.\n", name);
-	exit(1);
-}
-
-
-/*
- *  interrupt_handler_lookup():
- *
- *  Scans the list of registered interrupt handlers for a given name. If the
- *  name is found, the template is filled with valid data, and 1 is returned.
- *  If the name is not found, 0 is returned.
- */
-int interrupt_handler_lookup(const char *name, struct interrupt *templ)
-{
-	int i;
-
-#ifdef INTERRUPT_DEBUG
-	printf("interrupt_handler_lookup(\"%s\")\n", name);
-#endif
-
-	if (name[0] == '\0') {
-		/*  No interrupt:  */
-		memset(templ, 0, sizeof(struct interrupt));
-		templ->interrupt_assert = no_interrupt_assert;
-		templ->interrupt_deassert = no_interrupt_deassert;
-	}
-
-	for (i=0; i<nr_of_interrupt_handlers; i++) {
-		if (strcmp(name, interrupt_handlers[i].templ.name) != 0)
-			continue;
-
-		*templ = interrupt_handlers[i].templ;
-		return 1;
-	}
-
-	/*  The 'if' is an ugly hack to prevent a Compaq CC warning.  */
-	if (i >= nr_of_interrupt_handlers) {
-		printf("interrupt_handler_lookup(\"%s\") failed.\n", name);
-
-		printf("Available handler paths are:\n");
-		for (i=0; i<nr_of_interrupt_handlers; i++)
-			printf("    %s\n", interrupt_handlers[i].templ.name);
-
-		printf("Aborting.\n");
-		abort();
-	}
-
-	return 0;
-}
-
-
-/*
- *  interrupt_connect():
- *
- *  Increases the exclusive or nonexclusive nr or users of an interrupt.
- */
-void interrupt_connect(struct interrupt *in, int exclusive)
-{
-	int i;
-
-#ifdef INTERRUPT_DEBUG
-	printf("interrupt_connect(\"%s\")\n", in->name);
-#endif
-
-	if (in->name == NULL || in->name[0] == '\0')
-		return;
-
-	for (i=0; i<nr_of_interrupt_handlers; i++) {
-		if (strcmp(in->name, interrupt_handlers[i].templ.name) != 0)
-			continue;
-
-		if (exclusive) {
-			interrupt_handlers[i].nr_of_exclusive_users ++;
-			if (interrupt_handlers[i].nr_of_exclusive_users > 1) {
-				fatal("Fatal error in interrupt_connect(): "
-				    "more than 1 exclusive user. Dumping "
-				    "core for backtrace.\n");
-				abort();
-			}
-		} else {
-			interrupt_handlers[i].nr_of_nonexclusive_users ++;
-		}
-
-		return;
-	}
-
-	fatal("Internal error in interrupt_connect(): name '%s' not "
-	    "found? Dumping core for debugging.\n", in->name);
-	abort();
-}
-
-
-/*
- *  interrupt_disconnect():
- *
- *  Decreases the exclusive or nonexclusive nr or users of an interrupt.
- */
-void interrupt_disconnect(struct interrupt *in, int exclusive)
-{
-	int i;
-
-	if (in->name == NULL || in->name[0] == '\0')
-		return;
-
-	for (i=0; i<nr_of_interrupt_handlers; i++) {
-		if (strcmp(in->name, interrupt_handlers[i].templ.name) != 0)
-			continue;
-
-		if (exclusive) {
-			interrupt_handlers[i].nr_of_exclusive_users --;
-			if (interrupt_handlers[i].nr_of_exclusive_users < 0) {
-				fatal("Fatal error in interrupt_disconnect():"
-				    "nr of exclusive users < 0?\n");
-				exit(1);
-			}
-		} else {
-			interrupt_handlers[i].nr_of_nonexclusive_users --;
-			if (interrupt_handlers[i].nr_of_nonexclusive_users<0) {
-				fatal("Fatal error in interrupt_disconnect():"
-				    "nr of non-exclusive users < 0?\n");
-				exit(1);
-			}
-		}
-
-		return;
-	}
-
-	fatal("Internal error in interrupt_disconnect(): name '%s' not "
-	    "found?\n", in->name);
-	exit(1);
-}
-
-
diff -Nru gxemul-0.6.2/src/old_main/main.cc gxemul-0.7.0+dfsg/src/old_main/main.cc
--- gxemul-0.6.2/src/old_main/main.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/old_main/main.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,924 +0,0 @@
-/*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  GXemul's main entry point.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdarg.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-
-#include "ComponentFactory.h"
-#include "console.h"
-#include "cpu.h"
-#include "debugger.h"
-#include "device.h"
-#include "diskimage.h"
-#include "emul.h"
-#include "GXemul.h"
-#include "machine.h"
-#include "misc.h"
-#include "settings.h"
-#include "timer.h"
-#include "UnitTest.h"
-
-
-extern int single_step;
-extern int force_debugger_at_exit;
-
-extern int optind;
-extern char *optarg;
-
-struct settings *global_settings;
-
-int extra_argc;
-char **extra_argv;
-char *progname;
-
-size_t dyntrans_cache_size = DEFAULT_DYNTRANS_CACHE_SIZE;
-static int skip_srandom_call = 0;
-
-
-/*****************************************************************************
- *
- *  NOTE:  debug(), fatal(), and debug_indentation() are not re-entrant.
- *         The global variable quiet_mode can be used to suppress the output
- *         of debug(), but not the output of fatal().
- *
- *****************************************************************************/
-
-int verbose = 0;
-int quiet_mode = 0;
-
-static int debug_indent = 0;
-static int debug_currently_at_start_of_line = 1;
-
-
-/*
- *  va_debug():
- *
- *  Used internally by debug() and fatal().
- */
-static void va_debug(va_list argp, const char *fmt)
-{
-	char buf[DEBUG_BUFSIZE + 1];
-	char *s;
-	int i;
-
-	buf[0] = buf[DEBUG_BUFSIZE] = 0;
-	vsnprintf(buf, DEBUG_BUFSIZE, fmt, argp);
-
-	s = buf;
-	while (*s) {
-		if (debug_currently_at_start_of_line) {
-			for (i=0; i<debug_indent; i++)
-				printf(" ");
-		}
-
-		printf("%c", *s);
-
-		debug_currently_at_start_of_line = 0;
-		if (*s == '\n' || *s == '\r')
-			debug_currently_at_start_of_line = 1;
-		s++;
-	}
-}
-
-
-/*
- *  debug_indentation():
- *
- *  Modify the debug indentation.
- */
-void debug_indentation(int diff)
-{
-	debug_indent += diff;
-	if (debug_indent < 0)
-		fprintf(stderr, "WARNING: debug_indent less than 0!\n");
-}
-
-
-/*
- *  debug():
- *
- *  Debug output (ignored if quiet_mode is set).
- */
-void debug(const char *fmt, ...)
-{
-	va_list argp;
-
-	if (quiet_mode)
-		return;
-
-	va_start(argp, fmt);
-	va_debug(argp, fmt);
-	va_end(argp);
-}
-
-
-/*
- *  fatal():
- *
- *  Fatal works like debug(), but doesn't care about the quiet_mode
- *  setting.
- */
-void fatal(const char *fmt, ...)
-{
-	va_list argp;
-
-	va_start(argp, fmt);
-	va_debug(argp, fmt);
-	va_end(argp);
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  internal_w():
- *
- *  For internal use by gxemul itself.
- */
-void internal_w(char *arg)
-{
-	if (arg == NULL || strncmp(arg, "W@", 2) != 0) {
-		fprintf(stderr, "-W is for internal use by gxemul,"
-		    " not for manual use.\n");
-		exit(1);
-	}
-
-	arg += 2;
-
-	switch (arg[0]) {
-	case 'C':
-		GXemul::GenerateHTMLListOfComponents(false);
-		exit(0);
-		break;
-	case 'D':
-		GXemul::DumpMachineAsHTML(arg + 1);
-		break;
-	case 'S':
-		console_slave(arg + 1);
-		break;
-	case 'M':
-		GXemul::GenerateHTMLListOfComponents(true);
-		exit(0);
-		break;
-	case 'U':
-		{
-			int result = UnitTest::RunTests();
-
-			// Hack to prevent leaks:
-			ComponentFactory::UnregisterAllComponentClasses();
-
-#ifndef NDEBUG
-			int leaks = check_leaks();
-			if (leaks > 0) {
-				cerr << "Having memory leaks counts as failure to run the tests!\n";
-				exit(1);
-			}
-#endif
-
-			exit(result);
-		}
-		break;
-	default:
-		fprintf(stderr, "internal_w(): UNIMPLEMENTED arg = '%s'\n",
-		    arg);
-	}
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  usage():
- *
- *  Prints program usage to stdout.
- */
-static void usage(int longusage)
-{
-
-	printf("GXemul " VERSION"    " COPYRIGHT_MSG"\n" SECONDARY_MSG);
-	printf("Read the source code and/or documentation for other Copyright messages.\n");
-
-	printf("\nUsage: %s [machine, other, and general options] [file [...]]\n", progname);
-	printf("   or  %s [general options] @configfile\n", progname);
-
-	if (!longusage) {
-		printf("\nRun  %s -h  for help on command line options.\n", progname);
-		return;
-	}
-
-	printf("\nMachine selection options:\n");
-	printf("  -E t      try to emulate machine type t. (Use -H to get "
-	    "a list of types.)\n");
-	printf("  -e st     try to emulate machine subtype st. (Use this "
-	    "with -E.)\n");
-
-	printf("\nOther options:\n");
-	printf("  -C x      try to emulate a specific CPU. (Use -H to get a "
-	    "list of types.)\n");
-	printf("  -d fname  add fname as a disk image. You can add \"xxx:\""
-	    " as a prefix\n");
-	printf("            where xxx is one or more of the following:\n");
-	printf("                b      specifies that this is the boot"
-	    " device\n");
-	printf("                c      CD-ROM\n");
-	printf("                d      DISK\n");
-	printf("                f      FLOPPY\n");
-	printf("                gH;S;  set geometry to H heads and S"
-	    " sectors-per-track\n");
-	printf("                i      IDE\n");
-	printf("                oOFS;  set base offset to OFS (for ISO9660"
-	    " filesystems)\n");
-	printf("                r      read-only (don't allow changes to the"
-	    " file)\n");
-	printf("                s      SCSI\n");
-	printf("                t      tape\n");
-	printf("                V      add an overlay\n");
-	printf("                0-7    force a specific ID\n");
-	printf("  -I hz     set the main cpu frequency to hz (not used by "
-	    "all combinations\n            of machines and guest OSes)\n");
-	printf("  -i        display each instruction as it is executed\n");
-	printf("  -J        disable dyntrans instruction combinations\n");
-	printf("  -j name   set the name of the kernel; for DECstation "
-	    "emulation, this passes\n            the name to the bootloader,"
-	    " for example:\n");
-	printf("                -j netbsd     (NetBSD/pmax)      "
-	    "-j bsd      (OpenBSD/pmax)\n");
-	printf("                -j vmsprite   (Sprite/pmax)      "
-	    "-j vmunix   (Ultrix/RISC)\n");
-	printf("            For other emulation modes, if the boot disk is an"
-	    " ISO9660\n            filesystem, -j sets the name of the"
-	    " kernel to load.\n");
-	printf("  -M m      emulate m MBs of physical RAM\n");
-	printf("  -N        display nr of instructions/second average, at"
-	    " regular intervals\n");
-	printf("  -n nr     set nr of CPUs (for SMP experiments)\n");
-	printf("  -O        force netboot (tftp instead of disk), even when"
-	    " a disk image is\n"
-	    "            present (for DECstation, SGI, and ARC emulation)\n");
-	printf("  -o arg    set the boot argument, for DEC, ARC, or SGI"
-	    " emulation\n");
-	printf("            (default arg for DEC is -a, for ARC/SGI -aN)\n");
-	printf("  -p pc     add a breakpoint (remember to use the '0x' "
-	    "prefix for hex!)\n");
-	printf("  -Q        no built-in PROM emulation  (use this for "
-	    "running ROM images)\n");
-	printf("  -R        use random bootstrap cpu, instead of nr 0\n");
-	printf("  -r        register dumps before every instruction\n");
-	printf("  -S        initialize emulated RAM to random bytes, "
-	    "instead of zeroes\n");
-	printf("  -s f:name write statistics to file 'name', "
-	    "f is one or more of the following:\n");
-	printf("                v    virtual program counter\n");
-	printf("                p    physical equivalent of program counter\n");
-	printf("                i    internal ic->f representation of "
-	    "the program counter\n");
-	printf("            and optionally:\n");
-	printf("                d    disable statistics gathering at "
-	    "startup\n");
-	printf("                o    overwrite instead of append\n");
-	printf("  -T        halt on non-existant memory accesses\n");
-	printf("  -t        show function trace tree\n");
-	printf("  -U        enable slow_serial_interrupts_hack_for_linux\n");
-#ifdef WITH_X11
-	printf("  -X        use X11\n");
-	printf("  -x        open up new xterms for emulated serial ports "
-	    "(default is on when\n            using configuration files or"
-	    " when X11 is used, off otherwise)\n");
-	printf("  -Y n      scale down framebuffer windows by n x n times\n");
-#endif /*  WITH_X11  */
-	printf("  -Z n      set nr of graphics cards, for emulating a "
-	    "dual-head or tripple-head\n"
-	    "            environment (only for DECstation emulation)\n");
-	printf("  -z disp   add disp as an X11 display to use for "
-	    "framebuffers\n");
-
-	printf("\nGeneral options:\n");
-	printf("  -c cmd    add cmd as a command to run before starting "
-	    "the simulation\n");
-	printf("  -D        skip the srandom call at startup\n");
-	printf("  -H        display a list of possible CPU and "
-	    "machine types\n");
-	printf("  -h        display this help message\n");
-	printf("  -k n      set dyntrans translation caches to n MB (default"
-	    " size is %i MB)\n", DEFAULT_DYNTRANS_CACHE_SIZE / 1048576);
-	printf("  -K        force the debugger to be entered at the end "
-	    "of a simulation\n");
-	printf("  -q        quiet mode (don't print startup messages)\n");
-	printf("  -V        start up in the single-step debugger, paused\n");
-	printf("  -v        increase debug message verbosity\n");
-	printf("\n");
-	printf("If you are selecting a machine type to emulate directly "
-	    "on the command line,\nthen you must specify one or more names"
-	    " of files that you wish to load into\n"
-	    "memory. Supported formats are:   ELF a.out ecoff srec syms raw\n"
-	    "where syms is the text produced by running 'nm' (or 'nm -S') "
-	    "on a binary.\n"
-	    "To load a raw binary into memory, add \"address:\" in front "
-	    "of the filename,\n"
-	    "or \"address:skiplen:\" or \"address:skiplen:initialpc:\".\n"
-	    "\nExamples:\n"
-	    "    0xbfc00000:rom.bin                    for a raw ROM image\n"
-	    "    0xbfc00000:0x100:rom.bin              for an image with "
-	    "0x100 bytes header\n"
-	    "    0xbfc00000:0x100:0xbfc00884:rom.bin   "
-	    "start with pc=0xbfc00884\n\n");
-
-	printf("\n\"New framework\" options (experimental):\n");
-	printf("\nUsage: %s [options] -e name [additional components and files [...]]\n", progname);
-	printf("   or  %s [options] configfile\n", progname);
-	printf("   or  %s -H\n", progname);
-	printf("   or  %s -V\n", progname);
-	printf("\n");
-	printf("  -B           Enable snapshotting (reverse stepping support).\n");
-	printf("  -H           Display a list of available machine templates.\n");
-	printf("  -e name      Start with a machine based on template 'name'.\n");
-	printf("  -q           Quiet mode (suppress debug messages).\n");
-	printf("  -V           Start up in interactive debugging mode, paused.\n");
-	printf("\n");
-}
-
-
-/*
- *  get_cmd_args():
- *
- *  Reads command line arguments.
- */
-int get_cmd_args(int argc, char *argv[], struct emul *emul,
-	char ***diskimagesp, int *n_diskimagesp)
-{
-	int ch, res, using_switch_d = 0, using_switch_Z = 0;
-	int using_switch_e = 0, using_switch_E = 0;
-	bool using_switch_B = false;
-	char *type = NULL, *subtype = NULL;
-	int n_cpus_set = 0;
-	int msopts = 0;		/*  Machine-specific options used  */
-	struct machine *m = emul_add_machine(emul, NULL);
-
-	const char *opts =
-	    "BC:c:Dd:E:e:HhI:iJj:k:KM:Nn:Oo:p:QqRrSs:TtUVvW:"
-#ifdef WITH_X11
-	    "XxY:"
-#endif
-	    "Z:z:";
-
-	while ((ch = getopt(argc, argv, opts)) != -1) {
-		switch (ch) {
-		case 'B':
-			using_switch_B = true;
-			break;
-		case 'C':
-			CHECK_ALLOCATION(m->cpu_name = strdup(optarg));
-			msopts = 1;
-			break;
-		case 'c':
-			emul->n_debugger_cmds ++;
-			CHECK_ALLOCATION(emul->debugger_cmds = (char **)
-			    realloc(emul->debugger_cmds,
-			    emul->n_debugger_cmds * sizeof(char *)));
-			CHECK_ALLOCATION(emul->debugger_cmds[emul->
-			    n_debugger_cmds-1] = strdup(optarg));
-			break;
-		case 'D':
-			skip_srandom_call = 1;
-			break;
-		case 'd':
-			/*  diskimage_add() is called further down  */
-			(*n_diskimagesp) ++;
-			CHECK_ALLOCATION( (*diskimagesp) = (char **)
-			    realloc(*diskimagesp,
-			    sizeof(char *) * (*n_diskimagesp)) );
-			CHECK_ALLOCATION( (*diskimagesp)[(*n_diskimagesp) - 1] =
-			    strdup(optarg) );
-			using_switch_d = 1;
-			msopts = 1;
-			break;
-		case 'E':
-			if (using_switch_E ++ > 0) {
-				fprintf(stderr, "-E already used.\n");
-				exit(1);
-			}
-			type = optarg;
-			msopts = 1;
-			break;
-		case 'e':
-			if (using_switch_e ++ > 0) {
-				fprintf(stderr, "-e already used.\n");
-				exit(1);
-			}
-			subtype = optarg;
-			msopts = 1;
-			break;
-		case 'H':
-			GXemul::ListTemplates();
-			printf("--------------------------------------------------------------------------\n\n");
-			printf("The following applies to the LEGACY modes only:\n\n");
-			machine_list_available_types_and_cpus();
-			exit(1);
-		case 'h':
-			usage(1);
-			exit(1);
-		case 'I':
-			m->emulated_hz = atoi(optarg);
-			msopts = 1;
-			break;
-		case 'i':
-			m->instruction_trace = 1;
-			msopts = 1;
-			break;
-		case 'J':
-			m->allow_instruction_combinations = 0;
-			msopts = 1;
-			break;
-		case 'j':
-			CHECK_ALLOCATION(m->boot_kernel_filename =
-			    strdup(optarg));
-			msopts = 1;
-			break;
-		case 'k':
-			dyntrans_cache_size = atoi(optarg) * 1048576;
-			if (dyntrans_cache_size < 1) {
-				fprintf(stderr, "The dyntrans cache size must"
-				    " be at least 1 MB.\n");
-				exit(1);
-			}
-			break;
-		case 'K':
-			force_debugger_at_exit = 1;
-			break;
-		case 'M':
-			m->physical_ram_in_mb = atoi(optarg);
-			msopts = 1;
-			break;
-		case 'N':
-			m->show_nr_of_instructions = 1;
-			msopts = 1;
-			break;
-		case 'n':
-			m->ncpus = atoi(optarg);
-			n_cpus_set = 1;
-			msopts = 1;
-			break;
-		case 'O':
-			m->force_netboot = 1;
-			msopts = 1;
-			break;
-		case 'o':
-			CHECK_ALLOCATION(m->boot_string_argument =
-			    strdup(optarg));
-			msopts = 1;
-			break;
-		case 'p':
-			machine_add_breakpoint_string(m, optarg);
-			msopts = 1;
-			break;
-		case 'Q':
-			m->prom_emulation = 0;
-			msopts = 1;
-			break;
-		case 'q':
-			quiet_mode = 1;
-			break;
-		case 'R':
-			m->use_random_bootstrap_cpu = 1;
-			msopts = 1;
-			break;
-		case 'r':
-			m->register_dump = 1;
-			msopts = 1;
-			break;
-		case 'S':
-			m->random_mem_contents = 1;
-			msopts = 1;
-			break;
-		case 's':
-			machine_statistics_init(m, optarg);
-			msopts = 1;
-			break;
-		case 'T':
-			m->halt_on_nonexistant_memaccess = 1;
-			msopts = 1;
-			break;
-		case 't':
-			m->show_trace_tree = 1;
-			msopts = 1;
-			break;
-		case 'U':
-			m->slow_serial_interrupts_hack_for_linux = 1;
-			msopts = 1;
-			break;
-		case 'V':
-			single_step = ENTER_SINGLE_STEPPING;
-			break;
-		case 'v':
-			verbose ++;
-			break;
-		case 'W':
-			internal_w(optarg);
-			exit(0);
-		case 'X':
-			m->x11_md.in_use = 1;
-			msopts = 1;
-			/*  FALL-THROUGH  */
-		case 'x':
-			console_allow_slaves(1);
-			break;
-		case 'Y':
-			m->x11_md.scaledown = atoi(optarg);
-			if (m->x11_md.scaledown < -1) {
-				m->x11_md.scaleup = - m->x11_md.scaledown;
-				m->x11_md.scaledown = 1;
-			}
-			if (m->x11_md.scaledown < 1) {
-				fprintf(stderr, "Invalid scaledown value.\n");
-				exit(1);
-			}
-			msopts = 1;
-			break;
-		case 'Z':
-			m->n_gfx_cards = atoi(optarg);
-			using_switch_Z = 1;
-			msopts = 1;
-			break;
-		case 'z':
-			m->x11_md.n_display_names ++;
-			CHECK_ALLOCATION(m->x11_md.display_names = (char **) realloc(
-			    m->x11_md.display_names,
-			    m->x11_md.n_display_names * sizeof(char *)));
-			CHECK_ALLOCATION(m->x11_md.display_names[
-			    m->x11_md.n_display_names-1] = strdup(optarg));
-			msopts = 1;
-			break;
-		default:
-			fprintf(stderr, "Run  %s -h  for help on command "
-			    "line options.\n", progname);
-			exit(1);
-		}
-	}
-
-	argc -= optind;
-	argv += optind;
-
-	extra_argc = argc;
-	extra_argv = argv;
-
-	// If -V is used, -q is ignored.
-	if (single_step == ENTER_SINGLE_STEPPING)
-		quiet_mode = 0;
-
-	if (type == NULL && subtype == NULL &&
-	    (single_step == ENTER_SINGLE_STEPPING || (argc > 0 && argv[0][0] != '@'))) {
-		int res2 = 0;
-		{
-			GXemul gxemul;
-			gxemul.InitUI();
-
-			if (single_step == ENTER_SINGLE_STEPPING)
-				gxemul.SetRunState(GXemul::Paused);
-			else
-				gxemul.SetRunState(GXemul::Running);
-
-			gxemul.SetSnapshottingEnabled(using_switch_B);
-
-			if (quiet_mode)
-				gxemul.SetQuietMode(true);
-
-			if (argc > 0 && !gxemul.ParseFilenames("", argc, argv))
-				res = 1;
-
-			if (res2 == 0)
-				res2 = gxemul.Run();
-		}
-
-		// Note: exit() is outside the GXemul scope, so that GXemul's
-		// destructor runs.
-		exit(res2);
-	}
-
-	if (type != NULL || subtype != NULL) {
-		if (type == NULL)
-			type = strdup("");
-		if (subtype == NULL)
-			subtype = strdup("");
-
-		/*  Is it a new machine mode?  */
-		if (subtype[0] != '\0') {
-			int res2 = 0;
-			bool doExit = false;
-			
-			{
-				GXemul gxemul;
-				gxemul.InitUI();
-
-				if (single_step == ENTER_SINGLE_STEPPING)
-					gxemul.SetRunState(GXemul::Paused);
-				else
-					gxemul.SetRunState(GXemul::Running);
-
-				gxemul.SetSnapshottingEnabled(using_switch_B);
-
-				if (quiet_mode)
-					gxemul.SetQuietMode(true);
-
-				if (gxemul.IsTemplateMachine(subtype)) {
-					if (!gxemul.ParseFilenames(subtype, argc, argv))
-						res2 = 1;
-
-					if (res2 == 0)
-						res2 = gxemul.Run();
-
-					doExit = true;
-				}
-			}
-			
-			if (doExit)
-				exit(res2);
-		}
-
-		/*  Legacy mode?  */
-		res = machine_name_to_type(type, subtype,
-		    &m->machine_type, &m->machine_subtype, &m->arch);
-		if (!res)
-			exit(1);
-	}
-
-	if (m->machine_type == MACHINE_NONE && msopts) {
-		fprintf(stderr, "Machine specific options used directly on "
-		    "the command line, but no machine\nemulation specified?\n");
-		exit(1);
-	}
-
-
-	/*  -i and -r are pretty verbose:  */
-
-	if (m->instruction_trace && !verbose) {
-		fprintf(stderr, "Implicitly %sturning on -v, because"
-		    " of -i\n", quiet_mode? "turning off -q and " : "");
-		verbose = 1;
-		quiet_mode = 0;
-	}
-
-	if (m->register_dump && !verbose) {
-		fprintf(stderr, "Implicitly %sturning on -v, because"
-		    " of -r\n", quiet_mode? "turning off -q and " : "");
-		verbose = 1;
-		quiet_mode = 0;
-	}
-
-
-	/*
-	 *  Usually, an executable filename must be supplied.
-	 *
-	 *  However, it is possible to boot directly from a harddisk image
-	 *  file. If no kernel is supplied, but a diskimage is being used,
-	 *  then try to boot from disk.
-	 */
-	if (extra_argc == 0) {
-		if (using_switch_d) {
-			/*  Booting directly from a disk image...  */
-		} else {
-			usage(0);
-			fprintf(stderr, "\nNo filename given. Aborting.\n");
-			exit(1);
-		}
-	} else if (m->boot_kernel_filename[0] == '\0') {
-		/*
-		 *  Default boot_kernel_filename is "", which can be overriden
-		 *  by the -j command line option.  If it is still "" here,
-		 *  and we're not booting directly from a disk image, then
-		 *  try to set it to the last part of the last file name
-		 *  given on the command line. (Last part = the stuff after
-		 *  the last slash.)
-		 */
-		char *s = extra_argv[extra_argc - 1];
-		char *s2;
-
-		s2 = strrchr(s, '/');
-		if (s2 == NULL)
-			s2 = s;
-		else
-			s2 ++;
-
-		CHECK_ALLOCATION(m->boot_kernel_filename = strdup(s2));
-	}
-
-	if (m->n_gfx_cards < 0 || m->n_gfx_cards > 3) {
-		fprintf(stderr, "Bad number of gfx cards (-Z).\n");
-		exit(1);
-	}
-
-	if (!using_switch_Z && !m->x11_md.in_use)
-		m->n_gfx_cards = 0;
-
-	return 0;
-}
-
-
-/*
- *  main():
- *
- *  Two kinds of emulations are started from here:
- *
- *	o)  Simple emulations, using command line arguments, compatible with
- *	    earlier version of GXemul/mips64emul.
- *
- *	o)  Emulations set up by parsing special config files. (0 or more.)
- */
-int main(int argc, char *argv[])
-{
-	/*  Setting constants:  */
-	int constant_yes = 1;
-	int constant_true = 1;
-	int constant_no = 0;
-	int constant_false = 0;
-
-	struct emul *emul;
-	int config_file = 0;
-
-	char **diskimages = NULL;
-	int n_diskimages = 0;
-	int i;
-
-
-	progname = argv[0];
-
-
-	/*
-	 *  Create the settings object, and add global settings to it:
-	 *
-	 *  Read-only "constants":     yes, no, true, false.
-	 *  Global emulator settings:  verbose, single_step, ...
-	 */
-	global_settings = settings_new();
-
-	settings_add(global_settings, "yes", 0, SETTINGS_TYPE_INT,
-	    SETTINGS_FORMAT_YESNO, (void *)&constant_yes);
-	settings_add(global_settings, "no", 0, SETTINGS_TYPE_INT,
-	    SETTINGS_FORMAT_YESNO, (void *)&constant_no);
-	settings_add(global_settings, "true", 0, SETTINGS_TYPE_INT,
-	    SETTINGS_FORMAT_BOOL, (void *)&constant_true);
-	settings_add(global_settings, "false", 0, SETTINGS_TYPE_INT,
-	    SETTINGS_FORMAT_BOOL, (void *)&constant_false);
-
-	/*  Read-only settings:  */
-	settings_add(global_settings, "single_step", 0,
-	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO, (void *)&single_step);
-
-	/*  Read/write settings:  */
-	settings_add(global_settings, "force_debugger_at_exit", 1,
-	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO,
-	    (void *)&force_debugger_at_exit);
-	settings_add(global_settings, "verbose", 1,
-	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO, (void *)&verbose);
-	settings_add(global_settings, "quiet_mode", 1,
-	    SETTINGS_TYPE_INT, SETTINGS_FORMAT_YESNO, (void *)&quiet_mode);
-
-	/*  Initialize all emulator subsystems:  */
-	console_init();
-	cpu_init();
-	device_init();
-	machine_init();
-	timer_init();
-
-	/*  Create a simple emulation setup:  */
-	emul = emul_new(NULL);
-	settings_add(global_settings, "emul", 1,
-	    SETTINGS_TYPE_SUBSETTINGS, 0, emul->settings);
-
-	get_cmd_args(argc, argv, emul, &diskimages, &n_diskimages);
-
-	if (!skip_srandom_call) {
-		struct timeval tv;
-		gettimeofday(&tv, NULL);
-		srandom(tv.tv_sec ^ getpid() ^ tv.tv_usec);
-	}
-
-	/*  Print startup message:  */
-	debug("GXemul " VERSION"    " COPYRIGHT_MSG"\n" SECONDARY_MSG
-	    "Read the source code and/or documentation for other Copyright "
-	    "messages.\n\n");
-
-	/*  Simple initialization, from command line arguments:  */
-	if (emul->machines[0]->machine_type != MACHINE_NONE) {
-		for (i=0; i<n_diskimages; i++)
-			diskimage_add(emul->machines[0], diskimages[i]);
-
-		/*  Make sure that there are no configuration files as well:  */
-		for (i=1; i<argc; i++)
-			if (argv[i][0] == '@') {
-				fprintf(stderr, "You can either start one "
-				    "emulation with one machine directly from "
-				    "the command\nline, or start one or more "
-				    "emulations using configuration files."
-				    " Not both.\n");
-				exit(1);
-			}
-
-		/*  Initialize one emul:  */
-		emul_simple_init(emul);
-	}
-
-	/*  Initialize an emulation from a config file:  */
-	for (i=1; i<argc; i++) {
-		if (argv[i][0] == '@') {
-			char *s = argv[i] + 1;
-
-			if (config_file) {
-				fprintf(stderr, "More than one configuration "
-				    "file cannot be used.\n");
-				exit(1);
-			}
-
-			if (strlen(s) == 0 && i+1 < argc && *argv[i+1] != '@')
-				s = argv[++i];
-
-			/*  Always allow slave xterms:  */
-			console_allow_slaves(1);
-
-			/*  Destroy the temporary emul, since it will
-			    be overwritten:  */
-			if (emul != NULL) {
-				emul_destroy(emul);
-				settings_remove(global_settings, "emul");
-				emul = NULL;
-			}
-
-			emul = emul_create_from_configfile(s);
-
-			settings_add(global_settings, "emul", 1,
-			    SETTINGS_TYPE_SUBSETTINGS, 0, emul->settings);
-
-			config_file = 1;
-		}
-	}
-
-	if (emul->n_machines == 0) {
-		fprintf(stderr, "No emulations defined. Maybe you forgot to "
-		    "use -E xx and/or -e yy, to specify\nthe machine type."
-		    " For example:\n\n    %s -e 3max -d disk.img\n\n"
-		    "to boot an emulated DECstation 5000/200 with a disk "
-		    "image.\n", progname);
-		exit(1);
-	}
-
-	if (emul->machines[0]->machine_type == MACHINE_NONE) {
-		printf("No machine type specified? Run  gxemul -H  for a list\n"
-		    "of available machine types. Use the -e or -E option(s)\n"
-		    "to specify the machine type.\n");
-		exit(1);
-	}
-
-	device_set_exit_on_error(0);
-	console_warn_if_slaves_are_needed(1);
-
-
-	/*  Run the emulation:  */
-	emul_run(emul);
-
-
-	/*
-	 *  Deinitialize everything:
-	 */
-
-	console_deinit();
-
-	emul_destroy(emul);
-
-	settings_remove_all(global_settings);
-	settings_destroy(global_settings);
-
-	return 0;
-}
-
diff -Nru gxemul-0.6.2/src/old_main/Makefile.skel gxemul-0.7.0+dfsg/src/old_main/Makefile.skel
--- gxemul-0.6.2/src/old_main/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/old_main/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,20 +0,0 @@
-#
-#  Makefile for GXemul src/old_main (from GXemul 0.4.x)
-#
-
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(XINCLUDE) $(DINCLUDE)
-
-OBJS=emul.o emul_parse.o float_emul.o interrupt.o main.o memory.o misc.o \
-	settings.o timer.o
-
-all: $(OBJS)
-
-$(OBJS): Makefile
-
-clean:
-	rm -f $(OBJS) *core
-
-clean_all: clean
-	rm -f Makefile
-
-
diff -Nru gxemul-0.6.2/src/old_main/memory.cc gxemul-0.7.0+dfsg/src/old_main/memory.cc
--- gxemul-0.6.2/src/old_main/memory.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/old_main/memory.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1001 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Functions for handling the memory of an emulated machine.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-#include <sys/mman.h>
-
-#include "cpu.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-
-extern int verbose;
-extern int quiet_mode;
-
-
-/*
- *  memory_readmax64():
- *
- *  Read at most 64 bits of data from a buffer.  Length is given by
- *  len, and the byte order by cpu->byte_order.
- *
- *  This function should not be called with cpu == NULL.
- */
-uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
-{
-	int i, byte_order = cpu->byte_order;
-	uint64_t x = 0;
-
-	if (len & MEM_PCI_LITTLE_ENDIAN) {
-		len &= ~MEM_PCI_LITTLE_ENDIAN;
-		byte_order = EMUL_LITTLE_ENDIAN;
-	}
-
-	/*  Switch byte order for incoming data, if necessary:  */
-	if (byte_order == EMUL_BIG_ENDIAN)
-		for (i=0; i<len; i++) {
-			x <<= 8;
-			x |= buf[i];
-		}
-	else
-		for (i=len-1; i>=0; i--) {
-			x <<= 8;
-			x |= buf[i];
-		}
-
-	return x;
-}
-
-
-/*
- *  memory_writemax64():
- *
- *  Write at most 64 bits of data to a buffer.  Length is given by
- *  len, and the byte order by cpu->byte_order.
- *
- *  This function should not be called with cpu == NULL.
- */
-void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len,
-	uint64_t data)
-{
-	int i, byte_order = cpu->byte_order;
-
-	if (len & MEM_PCI_LITTLE_ENDIAN) {
-		len &= ~MEM_PCI_LITTLE_ENDIAN;
-		byte_order = EMUL_LITTLE_ENDIAN;
-	}
-
-	if (byte_order == EMUL_LITTLE_ENDIAN)
-		for (i=0; i<len; i++) {
-			buf[i] = data & 255;
-			data >>= 8;
-		}
-	else
-		for (i=0; i<len; i++) {
-			buf[len - 1 - i] = data & 255;
-			data >>= 8;
-		}
-}
-
-
-/*
- *  zeroed_alloc():
- *
- *  Allocates a block of memory using mmap(), and if that fails, try
- *  malloc() + memset(). The returned memory block contains only zeroes.
- */
-void *zeroed_alloc(size_t s)
-{
-	void *p = mmap(NULL, s, PROT_READ | PROT_WRITE,
-	    MAP_ANON | MAP_PRIVATE, -1, 0);
-
-	if (p == NULL) {
-#if 1
-		fprintf(stderr, "zeroed_alloc(): mmap() failed. This should"
-		    " not usually happen. If you can reproduce this, then"
-		    " please contact me with details about your run-time"
-		    " environment.\n");
-		exit(1);
-#else
-		CHECK_ALLOCATION(p = malloc(s));
-		memset(p, 0, s);
-#endif
-	}
-
-	return p;
-}
-
-
-/*
- *  memory_new():
- *
- *  This function creates a new memory object. An emulated machine needs one
- *  of these.
- */
-struct memory *memory_new(uint64_t physical_max, int arch)
-{
-	struct memory *mem;
-	int bits_per_pagetable = BITS_PER_PAGETABLE;
-	int bits_per_memblock = BITS_PER_MEMBLOCK;
-	int entries_per_pagetable = 1 << BITS_PER_PAGETABLE;
-	int max_bits = MAX_BITS;
-	size_t s;
-
-	CHECK_ALLOCATION(mem = (struct memory *) malloc(sizeof(struct memory)));
-	memset(mem, 0, sizeof(struct memory));
-
-	/*  Check bits_per_pagetable and bits_per_memblock for sanity:  */
-	if (bits_per_pagetable + bits_per_memblock != max_bits) {
-		fprintf(stderr, "memory_new(): bits_per_pagetable and "
-		    "bits_per_memblock mismatch\n");
-		exit(1);
-	}
-
-	mem->physical_max = physical_max;
-	mem->dev_dyntrans_alignment = 4095;
-
-	s = entries_per_pagetable * sizeof(void *);
-
-	mem->pagetable = (unsigned char *) mmap(NULL, s,
-	    PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
-	if (mem->pagetable == NULL) {
-		CHECK_ALLOCATION(mem->pagetable = malloc(s));
-		memset(mem->pagetable, 0, s);
-	}
-
-	mem->mmap_dev_minaddr = 0xffffffffffffffffULL;
-	mem->mmap_dev_maxaddr = 0;
-
-	return mem;
-}
-
-
-/*
- *  memory_points_to_string():
- *
- *  Returns 1 if there's something string-like in emulated memory at address
- *  addr, otherwise 0.
- */
-int memory_points_to_string(struct cpu *cpu, struct memory *mem, uint64_t addr,
-	int min_string_length)
-{
-	int cur_length = 0;
-	unsigned char c;
-
-	for (;;) {
-		c = '\0';
-		cpu->memory_rw(cpu, mem, addr+cur_length,
-		    &c, sizeof(c), MEM_READ, CACHE_NONE | NO_EXCEPTIONS);
-		if (c=='\n' || c=='\t' || c=='\r' || (c>=' ' && c<127)) {
-			cur_length ++;
-			if (cur_length >= min_string_length)
-				return 1;
-		} else {
-			if (cur_length >= min_string_length)
-				return 1;
-			else
-				return 0;
-		}
-	}
-}
-
-
-/*
- *  memory_conv_to_string():
- *
- *  Convert emulated memory contents to a string, placing it in a buffer
- *  provided by the caller.
- */
-char *memory_conv_to_string(struct cpu *cpu, struct memory *mem, uint64_t addr,
-	char *buf, int bufsize)
-{
-	int len = 0;
-	int output_index = 0;
-	unsigned char c, p='\0';
-
-	while (output_index < bufsize-1) {
-		c = '\0';
-		cpu->memory_rw(cpu, mem, addr+len, &c, sizeof(c), MEM_READ,
-		    CACHE_NONE | NO_EXCEPTIONS);
-		buf[output_index] = c;
-		if (c>=' ' && c<127) {
-			len ++;
-			output_index ++;
-		} else if (c=='\n' || c=='\r' || c=='\t') {
-			len ++;
-			buf[output_index] = '\\';
-			output_index ++;
-			switch (c) {
-			case '\n':	p = 'n'; break;
-			case '\r':	p = 'r'; break;
-			case '\t':	p = 't'; break;
-			}
-			if (output_index < bufsize-1) {
-				buf[output_index] = p;
-				output_index ++;
-			}
-		} else {
-			buf[output_index] = '\0';
-			return buf;
-		}
-	}
-
-	buf[bufsize-1] = '\0';
-	return buf;
-}
-
-
-/*
- *  memory_device_dyntrans_access():
- *
- *  Get the lowest and highest dyntrans access since last time.
- */
-void memory_device_dyntrans_access(struct cpu *cpu, struct memory *mem,
-	void *extra, uint64_t *low, uint64_t *high)
-{
-	size_t s;
-	int i, need_inval = 0;
-
-	/*  TODO: This is O(n), so it might be good to rewrite it some day.
-	    For now, it will be enough, as long as this function is not
-	    called too often.  */
-
-	for (i=0; i<mem->n_mmapped_devices; i++) {
-		if (mem->devices[i].extra == extra &&
-		    mem->devices[i].flags & DM_DYNTRANS_WRITE_OK &&
-		    mem->devices[i].dyntrans_data != NULL) {
-			if (mem->devices[i].dyntrans_write_low != (uint64_t) -1)
-				need_inval = 1;
-			if (low != NULL)
-				*low = mem->devices[i].dyntrans_write_low;
-			mem->devices[i].dyntrans_write_low = (uint64_t) -1;
-
-			if (high != NULL)
-				*high = mem->devices[i].dyntrans_write_high;
-			mem->devices[i].dyntrans_write_high = 0;
-
-			if (!need_inval)
-				return;
-
-			/*  Invalidate any pages of this device that might
-			    be in the dyntrans load/store cache, by marking
-			    the pages read-only.  */
-			if (cpu->invalidate_translation_caches != NULL) {
-				for (s = *low; s <= *high;
-				    s += cpu->machine->arch_pagesize)
-					cpu->invalidate_translation_caches
-					    (cpu, mem->devices[i].baseaddr + s,
-					    JUST_MARK_AS_NON_WRITABLE
-					    | INVALIDATE_PADDR);
-			}
-
-			return;
-		}
-	}
-}
-
-
-/*
- *  memory_device_update_data():
- *
- *  Update a device' dyntrans data pointer.
- *
- *  SUPER-IMPORTANT NOTE: Anyone who changes a dyntrans data pointer while
- *  things are running also needs to invalidate all CPUs' address translation
- *  caches!  Otherwise, these may contain old pointers to the old data.
- */
-void memory_device_update_data(struct memory *mem, void *extra,
-	unsigned char *data)
-{
-	int i;
-
-	for (i=0; i<mem->n_mmapped_devices; i++) {
-		if (mem->devices[i].extra != extra)
-			continue;
-
-		mem->devices[i].dyntrans_data = data;
-		mem->devices[i].dyntrans_write_low = (uint64_t)-1;
-		mem->devices[i].dyntrans_write_high = 0;
-	}
-}
-
-
-/*
- *  memory_device_register():
- *
- *  Register a memory mapped device.
- */
-void memory_device_register(struct memory *mem, const char *device_name,
-	uint64_t baseaddr, uint64_t len,
-	int (*f)(struct cpu *,struct memory *,uint64_t,unsigned char *,
-		size_t,int,void *),
-	void *extra, int flags, unsigned char *dyntrans_data)
-{
-	int i, newi = 0;
-
-	/*
-	 *  Figure out at which index to insert this device, and simultaneously
-	 *  check for collisions:
-	 */
-	newi = -1;
-	for (i=0; i<mem->n_mmapped_devices; i++) {
-		if (i == 0 && baseaddr + len <= mem->devices[i].baseaddr)
-			newi = i;
-		if (i > 0 && baseaddr + len <= mem->devices[i].baseaddr &&
-		    baseaddr >= mem->devices[i-1].endaddr)
-			newi = i;
-		if (i == mem->n_mmapped_devices - 1 &&
-		    baseaddr >= mem->devices[i].endaddr)
-			newi = i + 1;
-
-		/*  If this is not colliding with device i, then continue:  */
-		if (baseaddr + len <= mem->devices[i].baseaddr)
-			continue;
-		if (baseaddr >= mem->devices[i].endaddr)
-			continue;
-
-		fatal("\nERROR! \"%s\" collides with device %i (\"%s\")!\n",
-		    device_name, i, mem->devices[i].name);
-		exit(1);
-	}
-	if (mem->n_mmapped_devices == 0)
-		newi = 0;
-	if (newi == -1) {
-		fatal("INTERNAL ERROR\n");
-		exit(1);
-	}
-
-	if (verbose >= 2) {
-		/*  (40 bits of physical address is displayed)  */
-		debug("device at 0x%010" PRIx64": %s", (uint64_t) baseaddr,
-		    device_name);
-
-		if (flags & (DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK)
-		    && (baseaddr & mem->dev_dyntrans_alignment) != 0) {
-			fatal("\nWARNING: Device dyntrans access, but unaligned"
-			    " baseaddr 0x%" PRIx64".\n", (uint64_t) baseaddr);
-		}
-
-		if (flags & (DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK)) {
-			debug(" (dyntrans %s)",
-			    (flags & DM_DYNTRANS_WRITE_OK)? "R/W" : "R");
-		}
-		debug("\n");
-	}
-
-	for (i=0; i<mem->n_mmapped_devices; i++) {
-		if (dyntrans_data == mem->devices[i].dyntrans_data &&
-		    mem->devices[i].flags&(DM_DYNTRANS_OK|DM_DYNTRANS_WRITE_OK)
-		    && flags & (DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK)) {
-			fatal("ERROR: the data pointer used for dyntrans "
-			    "accesses must only be used once!\n");
-			fatal("(%p cannot be used by '%s'; already in use by '"
-			    "%s')\n", dyntrans_data, device_name,
-			    mem->devices[i].name);
-			exit(1);
-		}
-	}
-
-	mem->n_mmapped_devices++;
-
-	CHECK_ALLOCATION(mem->devices = (struct memory_device *) realloc(mem->devices,
-	    sizeof(struct memory_device) * mem->n_mmapped_devices));
-
-	/*  Make space for the new entry:  */
-	if (newi + 1 != mem->n_mmapped_devices)
-		memmove(&mem->devices[newi+1], &mem->devices[newi],
-		    sizeof(struct memory_device)
-		    * (mem->n_mmapped_devices - newi - 1));
-
-	CHECK_ALLOCATION(mem->devices[newi].name = strdup(device_name));
-	mem->devices[newi].baseaddr = baseaddr;
-	mem->devices[newi].endaddr = baseaddr + len;
-	mem->devices[newi].length = len;
-	mem->devices[newi].flags = flags;
-	mem->devices[newi].dyntrans_data = dyntrans_data;
-
-	if (flags & (DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK)
-	    && !(flags & DM_EMULATED_RAM) && dyntrans_data == NULL) {
-		fatal("\nERROR: Device dyntrans access, but dyntrans_data"
-		    " = NULL!\n");
-		exit(1);
-	}
-
-	if ((size_t)dyntrans_data & (sizeof(void *) - 1)) {
-		fprintf(stderr, "memory_device_register():"
-		    " dyntrans_data not aligned correctly (%p)\n",
-		    dyntrans_data);
-		abort();
-	}
-
-	mem->devices[newi].dyntrans_write_low = (uint64_t)-1;
-	mem->devices[newi].dyntrans_write_high = 0;
-	mem->devices[newi].f = f;
-	mem->devices[newi].extra = extra;
-
-	if (baseaddr < mem->mmap_dev_minaddr)
-		mem->mmap_dev_minaddr = baseaddr & ~mem->dev_dyntrans_alignment;
-	if (baseaddr + len > mem->mmap_dev_maxaddr)
-		mem->mmap_dev_maxaddr = (((baseaddr + len) - 1) |
-		    mem->dev_dyntrans_alignment) + 1;
-
-	if (newi < mem->last_accessed_device)
-		mem->last_accessed_device ++;
-}
-
-
-/*
- *  memory_device_remove():
- *
- *  Unregister a memory mapped device from a memory object.
- */
-void memory_device_remove(struct memory *mem, int i)
-{
-	if (i < 0 || i >= mem->n_mmapped_devices) {
-		fatal("memory_device_remove(): invalid device number %i\n", i);
-		exit(1);
-	}
-
-	mem->n_mmapped_devices --;
-
-	if (i == mem->n_mmapped_devices)
-		return;
-
-	memmove(&mem->devices[i], &mem->devices[i+1],
-	    sizeof(struct memory_device) * (mem->n_mmapped_devices - i));
-
-	if (i <= mem->last_accessed_device)
-		mem->last_accessed_device --;
-	if (mem->last_accessed_device < 0)
-		mem->last_accessed_device = 0;
-}
-
-
-/*
- *  memory_paddr_to_hostaddr():
- *
- *  Translate a physical address into a host address. The usual way to call
- *  this function is to make sure that paddr is page aligned, which will result
- *  in the host _page_ corresponding to that address.
- *
- *  Return value is a pointer to the address in the host, or NULL on failure.
- *  On reads, a NULL return value should be interpreted as reading all zeroes.
- */
-unsigned char *memory_paddr_to_hostaddr(struct memory *mem,
-	uint64_t paddr, int writeflag)
-{
-	void **table;
-	int entry;
-	const int mask = (1 << BITS_PER_PAGETABLE) - 1;
-	const int shrcount = MAX_BITS - BITS_PER_PAGETABLE;
-	unsigned char *hostptr;
-
-	table = (void **) mem->pagetable;
-	entry = (paddr >> shrcount) & mask;
-
-	/*  printf("memory_paddr_to_hostaddr(): p=%16" PRIx64
-	    " w=%i => entry=0x%x\n", (uint64_t) paddr, writeflag, entry);  */
-
-	if (table[entry] == NULL) {
-		size_t alloclen;
-
-		/*
-		 *  Special case:  reading from a nonexistant memblock
-		 *  returns all zeroes, and doesn't allocate anything.
-		 *  (If any intermediate pagetable is nonexistant, then
-		 *  the same thing happens):
-		 */
-		if (writeflag == MEM_READ)
-			return NULL;
-
-		/*  Allocate a memblock:  */
-		alloclen = 1 << BITS_PER_MEMBLOCK;
-
-		/*  printf("  allocating for entry %i, len=%i\n",
-		    entry, alloclen);  */
-
-		/*  Anonymous mmap() should return zero-filled memory,
-		    try malloc + memset if mmap failed.  */
-		table[entry] = (void *) mmap(NULL, alloclen,
-		    PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
-		if (table[entry] == NULL) {
-			CHECK_ALLOCATION(table[entry] = malloc(alloclen));
-			memset(table[entry], 0, alloclen);
-		}
-	}
-
-	hostptr = (unsigned char *) table[entry];
-
-	if (hostptr != NULL)
-		hostptr += (paddr & ((1 << BITS_PER_MEMBLOCK) - 1));
-
-	return hostptr;
-}
-
-
-#define	UPDATE_CHECKSUM(value) {					\
-		internal_state -= 0x118c7771c0c0a77fULL;		\
-		internal_state = ((internal_state + (value)) << 7) ^	\
-		    (checksum >> 11) ^ ((checksum - (value)) << 3) ^	\
-		    (internal_state - checksum) ^ ((value) - internal_state); \
-		checksum ^= internal_state;				\
-	}
-
-
-/*
- *  memory_checksum():
- *
- *  Calculate a 64-bit checksum of everything in a struct memory. This is
- *  useful for tracking down bugs; an old (presumably working) version of
- *  the emulator can be compared to a newer (buggy) version.
- */
-uint64_t memory_checksum(struct memory *mem)
-{
-	uint64_t internal_state = 0x80624185376feff2ULL;
-	uint64_t checksum = 0xcb9a87d5c010072cULL;
-	const size_t n_entries = (1 << BITS_PER_PAGETABLE) - 1;
-	const size_t len = (1 << BITS_PER_MEMBLOCK) / sizeof(uint64_t);
-	size_t entry, i;
-
-	for (entry=0; entry<=n_entries; entry++) {
-		uint64_t **table = (uint64_t **) mem->pagetable;
-		uint64_t *memblock = table[entry];
-
-		if (memblock == NULL) {
-			UPDATE_CHECKSUM(0x1198ab7c8174a76fULL);
-			continue;
-		}
-
-		for (i=0; i<len; i++)
-			UPDATE_CHECKSUM(memblock[i]);
-	}
-
-	return checksum;
-}
-
-
-/*
- *  memory_warn_about_unimplemented_addr():
- *
- *  Called from memory_rw whenever memory outside of the physical address space
- *  is accessed (and quiet_mode isn't set).
- */
-void memory_warn_about_unimplemented_addr(struct cpu *cpu, struct memory *mem,
-	int writeflag, uint64_t paddr, uint8_t *data, size_t len)
-{
-	uint64_t offset, old_pc = cpu->pc;
-	char *symbol;
-
-	/*
-	 *  This allows guest OS kernels to probe memory a few KBs past the
-	 *  end of memory, without giving too many warnings.
-	 */
-	if (paddr < mem->physical_max + 0x40000)
-		return;
-
-	if (!cpu->machine->halt_on_nonexistant_memaccess && quiet_mode)
-		return;
-
-	fatal("[ memory_rw(): %s ", writeflag? "write":"read");
-
-	if (writeflag) {
-		unsigned int i;
-		debug("data={", writeflag);
-		if (len > 16) {
-			int start2 = len-16;
-			for (i=0; i<16; i++)
-				debug("%s%02x", i?",":"", data[i]);
-			debug(" .. ");
-			if (start2 < 16)
-				start2 = 16;
-			for (i=start2; i<len; i++)
-				debug("%s%02x", i?",":"", data[i]);
-		} else
-			for (i=0; i<len; i++)
-				debug("%s%02x", i?",":"", data[i]);
-		debug("} ");
-	}
-
-	fatal("paddr=0x%" PRIx64" >= physical_max; pc=", paddr);
-	if (cpu->is_32bit)
-		fatal("0x%08" PRIx32, (uint32_t) old_pc);
-	else
-		fatal("0x%016" PRIx64, (uint64_t) old_pc);
-	symbol = get_symbol_name(&cpu->machine->symbol_context,
-	    old_pc, &offset);
-	fatal(" <%s> ]\n", symbol? symbol : " no symbol ");
-
-	if (cpu->machine->halt_on_nonexistant_memaccess) {
-		/*  TODO: Halt in a nicer way. Not possible with the
-		    current dyntrans system...  */
-		exit(1);
-	}
-}
-
-
-/*
- *  dump_mem_string():
- *
- *  Dump the contents of emulated RAM as readable text.  Bytes that aren't
- *  readable are dumped in [xx] notation, where xx is in hexadecimal.
- *  Dumping ends after DUMP_MEM_STRING_MAX bytes, or when a terminating
- *  zero byte is found.
- */
-#define DUMP_MEM_STRING_MAX	45
-void dump_mem_string(struct cpu *cpu, uint64_t addr)
-{
-	int i;
-	for (i=0; i<DUMP_MEM_STRING_MAX; i++) {
-		unsigned char ch = '\0';
-
-		cpu->memory_rw(cpu, cpu->mem, addr + i, &ch, sizeof(ch),
-		    MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
-		if (ch == '\0')
-			return;
-		if (ch >= ' ' && ch < 126)
-			debug("%c", ch);  
-		else
-			debug("[%02x]", ch);
-	}
-}
-
-
-/*
- *  store_byte():
- *
- *  Stores a byte in emulated ram. (Helper function.)
- */
-void store_byte(struct cpu *cpu, uint64_t addr, uint8_t data)
-{
-	if ((addr >> 32) == 0)
-		addr = (int64_t)(int32_t)addr;
-	cpu->memory_rw(cpu, cpu->mem,
-	    addr, &data, sizeof(data), MEM_WRITE, CACHE_DATA);
-}
-
-
-/*
- *  store_string():
- *
- *  Stores chars into emulated RAM until a zero byte (string terminating
- *  character) is found. The zero byte is also copied.
- *  (strcpy()-like helper function, host-RAM-to-emulated-RAM.)
- */
-void store_string(struct cpu *cpu, uint64_t addr, const char *s)
-{
-	do {
-		store_byte(cpu, addr++, *s);
-	} while (*s++);
-}
-
-
-/*
- *  add_environment_string():
- *
- *  Like store_string(), but advances the pointer afterwards. The most
- *  obvious use is to place a number of strings (such as environment variable
- *  strings) after one-another in emulated memory.
- */
-void add_environment_string(struct cpu *cpu, const char *s, uint64_t *addr)
-{
-	store_string(cpu, *addr, s);
-	(*addr) += strlen(s) + 1;
-}
-
-
-/*
- *  add_environment_string_dual():
- *
- *  Add "dual" environment strings, one for the variable name and one for the
- *  value, and update pointers afterwards.
- */
-void add_environment_string_dual(struct cpu *cpu,
-	uint64_t *ptrp, uint64_t *addrp, const char *s1, const char *s2)
-{
-	uint64_t ptr = *ptrp, addr = *addrp;
-
-	store_32bit_word(cpu, ptr, addr);
-	ptr += sizeof(uint32_t);
-	if (addr != 0) {
-		store_string(cpu, addr, s1);
-		addr += strlen(s1) + 1;
-	}
-	store_32bit_word(cpu, ptr, addr);
-	ptr += sizeof(uint32_t);
-	if (addr != 0) {
-		store_string(cpu, addr, s2);
-		addr += strlen(s2) + 1;
-	}
-
-	*ptrp = ptr;
-	*addrp = addr;
-}
-
-
-/*
- *  store_64bit_word():
- *
- *  Stores a 64-bit word in emulated RAM.  Byte order is taken into account.
- *  Helper function.
- */
-int store_64bit_word(struct cpu *cpu, uint64_t addr, uint64_t data64)
-{
-	unsigned char data[8];
-	if ((addr >> 32) == 0)
-		addr = (int64_t)(int32_t)addr;
-	data[0] = (data64 >> 56) & 255;
-	data[1] = (data64 >> 48) & 255;
-	data[2] = (data64 >> 40) & 255;
-	data[3] = (data64 >> 32) & 255;
-	data[4] = (data64 >> 24) & 255;
-	data[5] = (data64 >> 16) & 255;
-	data[6] = (data64 >> 8) & 255;
-	data[7] = (data64) & 255;
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		int tmp = data[0]; data[0] = data[7]; data[7] = tmp;
-		tmp = data[1]; data[1] = data[6]; data[6] = tmp;
-		tmp = data[2]; data[2] = data[5]; data[5] = tmp;
-		tmp = data[3]; data[3] = data[4]; data[4] = tmp;
-	}
-	return cpu->memory_rw(cpu, cpu->mem,
-	    addr, data, sizeof(data), MEM_WRITE, CACHE_DATA);
-}
-
-
-/*
- *  store_32bit_word():
- *
- *  Stores a 32-bit word in emulated RAM.  Byte order is taken into account.
- *  (This function takes a 64-bit word as argument, to suppress some
- *  warnings, but only the lowest 32 bits are used.)
- */
-int store_32bit_word(struct cpu *cpu, uint64_t addr, uint64_t data32)
-{
-	unsigned char data[4];
-
-	data[0] = (data32 >> 24) & 255;
-	data[1] = (data32 >> 16) & 255;
-	data[2] = (data32 >> 8) & 255;
-	data[3] = (data32) & 255;
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		int tmp = data[0]; data[0] = data[3]; data[3] = tmp;
-		tmp = data[1]; data[1] = data[2]; data[2] = tmp;
-	}
-	return cpu->memory_rw(cpu, cpu->mem,
-	    addr, data, sizeof(data), MEM_WRITE, CACHE_DATA);
-}
-
-
-/*
- *  store_16bit_word():
- *
- *  Stores a 16-bit word in emulated RAM.  Byte order is taken into account.
- *  (This function takes a 64-bit word as argument, to suppress some
- *  warnings, but only the lowest 16 bits are used.)
- */
-int store_16bit_word(struct cpu *cpu, uint64_t addr, uint64_t data16)
-{
-	unsigned char data[2];
-
-	data[0] = (data16 >> 8) & 255;
-	data[1] = (data16) & 255;
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		int tmp = data[0]; data[0] = data[1]; data[1] = tmp;
-	}
-	return cpu->memory_rw(cpu, cpu->mem,
-	    addr, data, sizeof(data), MEM_WRITE, CACHE_DATA);
-}
-
-
-/*
- *  store_buf():
- *
- *  memcpy()-like helper function, from host RAM to emulated RAM.
- */
-void store_buf(struct cpu *cpu, uint64_t addr, const char *s, size_t len)
-{
-	size_t psize = 1024;	/*  1024 256 64 16 4 1  */
-
-	while (len != 0) {
-		if ((addr & (psize-1)) == 0) {
-			while (len >= psize) {
-				cpu->memory_rw(cpu, cpu->mem, addr,
-				    (unsigned char *)s, psize, MEM_WRITE,
-				    CACHE_DATA);
-				addr += psize;
-				s += psize;
-				len -= psize;
-			}
-		}
-		psize >>= 2;
-	}
-
-	while (len-- != 0)
-		store_byte(cpu, addr++, *s++);
-}
-
-
-/*
- *  store_pointer_and_advance():
- *
- *  Stores a 32-bit or 64-bit pointer in emulated RAM, and advances the
- *  target address. (Useful for e.g. ARCBIOS environment initialization.)
- */
-void store_pointer_and_advance(struct cpu *cpu, uint64_t *addrp,
-	uint64_t data, int flag64)
-{
-	uint64_t addr = *addrp;
-	if (flag64) {
-		store_64bit_word(cpu, addr, data);
-		addr += 8;
-	} else {
-		store_32bit_word(cpu, addr, data);
-		addr += 4;
-	}
-	*addrp = addr;
-}
-
-
-/*
- *  load_64bit_word():
- *
- *  Helper function. Emulated byte order is taken into account.
- */
-uint64_t load_64bit_word(struct cpu *cpu, uint64_t addr)
-{
-	unsigned char data[8];
-
-	cpu->memory_rw(cpu, cpu->mem,
-	    addr, data, sizeof(data), MEM_READ, CACHE_DATA);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		int tmp = data[0]; data[0] = data[7]; data[7] = tmp;
-		tmp = data[1]; data[1] = data[6]; data[6] = tmp;
-		tmp = data[2]; data[2] = data[5]; data[5] = tmp;
-		tmp = data[3]; data[3] = data[4]; data[4] = tmp;
-	}
-
-	return
-	    ((uint64_t)data[0] << 56) + ((uint64_t)data[1] << 48) +
-	    ((uint64_t)data[2] << 40) + ((uint64_t)data[3] << 32) +
-	    ((uint64_t)data[4] << 24) + ((uint64_t)data[5] << 16) +
-	    ((uint64_t)data[6] << 8) + (uint64_t)data[7];
-}
-
-
-/*
- *  load_32bit_word():
- *
- *  Helper function. Emulated byte order is taken into account.
- */
-uint32_t load_32bit_word(struct cpu *cpu, uint64_t addr)
-{
-	unsigned char data[4];
-
-	cpu->memory_rw(cpu, cpu->mem,
-	    addr, data, sizeof(data), MEM_READ, CACHE_DATA);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		int tmp = data[0]; data[0] = data[3]; data[3] = tmp;
-		tmp = data[1]; data[1] = data[2]; data[2] = tmp;
-	}
-
-	return (data[0] << 24) + (data[1] << 16) + (data[2] << 8) + data[3];
-}
-
-
-/*
- *  load_16bit_word():
- *
- *  Helper function. Emulated byte order is taken into account.
- */
-uint16_t load_16bit_word(struct cpu *cpu, uint64_t addr)
-{
-	unsigned char data[2];
-
-	cpu->memory_rw(cpu, cpu->mem,
-	    addr, data, sizeof(data), MEM_READ, CACHE_DATA);
-
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		int tmp = data[0]; data[0] = data[1]; data[1] = tmp;
-	}
-
-	return (data[0] << 8) + data[1];
-}
-
-
-/*
- *  store_64bit_word_in_host():
- *
- *  Stores a 64-bit word in the _host's_ RAM.  Emulated byte order is taken
- *  into account.  This is useful when building structs in the host's RAM
- *  which will later be copied into emulated RAM.
- */
-void store_64bit_word_in_host(struct cpu *cpu,
-	unsigned char *data, uint64_t data64)
-{
-	data[0] = (data64 >> 56) & 255;
-	data[1] = (data64 >> 48) & 255;
-	data[2] = (data64 >> 40) & 255;
-	data[3] = (data64 >> 32) & 255;
-	data[4] = (data64 >> 24) & 255;
-	data[5] = (data64 >> 16) & 255;
-	data[6] = (data64 >> 8) & 255;
-	data[7] = (data64) & 255;
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		int tmp = data[0]; data[0] = data[7]; data[7] = tmp;
-		tmp = data[1]; data[1] = data[6]; data[6] = tmp;
-		tmp = data[2]; data[2] = data[5]; data[5] = tmp;
-		tmp = data[3]; data[3] = data[4]; data[4] = tmp;
-	}
-}
-
-
-/*
- *  store_32bit_word_in_host():
- *
- *  See comment for store_64bit_word_in_host().
- *
- *  (Note:  The data32 parameter is a uint64_t. This is done to suppress
- *  some warnings.)
- */
-void store_32bit_word_in_host(struct cpu *cpu,
-	unsigned char *data, uint64_t data32)
-{
-	data[0] = (data32 >> 24) & 255;
-	data[1] = (data32 >> 16) & 255;
-	data[2] = (data32 >> 8) & 255;
-	data[3] = (data32) & 255;
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		int tmp = data[0]; data[0] = data[3]; data[3] = tmp;
-		tmp = data[1]; data[1] = data[2]; data[2] = tmp;
-	}
-}
-
-
-/*
- *  store_16bit_word_in_host():
- *
- *  See comment for store_64bit_word_in_host().
- */
-void store_16bit_word_in_host(struct cpu *cpu,
-	unsigned char *data, uint16_t data16)
-{
-	data[0] = (data16 >> 8) & 255;
-	data[1] = (data16) & 255;
-	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
-		int tmp = data[0]; data[0] = data[1]; data[1] = tmp;
-	}
-}
-
diff -Nru gxemul-0.6.2/src/old_main/misc.cc gxemul-0.7.0+dfsg/src/old_main/misc.cc
--- gxemul-0.6.2/src/old_main/misc.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/old_main/misc.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,171 +0,0 @@
-/*
- *  Copyright (C) 2005-2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  This file contains things that don't fit anywhere else, and fake/dummy
- *  implementations of libc functions that are missing on some systems.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <fcntl.h>
-
-#include "cpu.h"
-#include "misc.h"
-
-
-/*
- *  mystrtoull():
- *
- *  This function is used on OSes that don't have strtoull() in libc.
- */
-unsigned long long mystrtoull(const char *s, char **endp, int base)
-{
-	unsigned long long res = 0;
-	int minus_sign = 0;
-
-	if (s == NULL)
-		return 0;
-
-	/*  TODO: Implement endp?  */
-	if (endp != NULL) {
-		fprintf(stderr, "mystrtoull(): endp isn't implemented\n");
-		exit(1);
-	}
-
-	if (s[0] == '-') {
-		minus_sign = 1;
-		s++;
-	}
-
-	/*  Guess base:  */
-	if (base == 0) {
-		if (s[0] == '0') {
-			/*  Just "0"? :-)  */
-			if (!s[1])
-				return 0;
-			if (s[1] == 'x' || s[1] == 'X') {
-				base = 16;
-				s += 2;
-			} else {
-				base = 8;
-				s ++;
-			}
-		} else if (s[0] >= '1' && s[0] <= '9')
-			base = 10;
-	}
-
-	while (s[0]) {
-		int c = s[0];
-		if (c >= '0' && c <= '9')
-			c -= '0';
-		else if (c >= 'a' && c <= 'f')
-			c = c - 'a' + 10;
-		else if (c >= 'A' && c <= 'F')
-			c = c - 'A' + 10;
-		else
-			break;
-		switch (base) {
-		case 8:	res = (res << 3) | c;
-			break;
-		case 16:res = (res << 4) | c;
-			break;
-		default:res = (res * base) + c;
-		}
-		s++;
-	}
-
-	if (minus_sign)
-		res = (uint64_t) -(int64_t)res;
-	return res;
-}
-
-
-/*
- *  mymkstemp():
- *
- *  mkstemp() replacement for systems that lack that function. This is NOT
- *  really safe, but should at least allow the emulator to build and run.
- */
-int mymkstemp(char *templ)
-{
-	int h = 0;
-	char *p = templ;
-
-	while (*p) {
-		if (*p == 'X')
-			*p = 48 + random() % 10;
-		p++;
-	}
-
-	h = open(templ, O_RDWR | O_CREAT | O_EXCL, 0600);
-	return h;
-}
-
-
-#ifdef USE_STRLCPY_REPLACEMENTS
-/*
- *  mystrlcpy():
- *
- *  Quick hack strlcpy() replacement for systems that lack that function.
- *  NOTE: No length checking is done.
- */
-size_t mystrlcpy(char *dst, const char *src, size_t size)
-{
-	strcpy(dst, src);
-	return strlen(src);
-}
-
-
-/*
- *  mystrlcat():
- *
- *  Quick hack strlcat() replacement for systems that lack that function.
- *  NOTE: No length checking is done.
- */
-size_t mystrlcat(char *dst, const char *src, size_t size)
-{
-	size_t orig_dst_len = strlen(dst);
-	strcat(dst, src);
-	return strlen(src) + orig_dst_len;
-}
-#endif
-
-
-/*
- *  print_separator_line():
- *
- *  Prints a line of "----------".
- */
-void print_separator_line(void)
-{
-        int i = 79; 
-        while (i-- > 0)
-                debug("-");
-        debug("\n");
-}
-
diff -Nru gxemul-0.6.2/src/old_main/settings.cc gxemul-0.7.0+dfsg/src/old_main/settings.cc
--- gxemul-0.6.2/src/old_main/settings.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/old_main/settings.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,506 +0,0 @@
-/*
- *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  A generic settings object. (This module should be 100% indepedent of GXemul
- *  and hence easily reusable.)  It is basically a tree structure of nodes,
- *  where each node has a name and a few properties. The main property is
- *  a pointer, which can either point to other settings ("sub-settings"),
- *  or to a variable in memory.
- *
- *  Appart from the pointer, the other properties are a definition of the
- *  type being pointed to (int, int32_t, int64_t, char*, etc), how it should be
- *  presented (e.g. it may be an int value in memory, but it should be
- *  presented as a boolean "true/false" value), and a flag which tells us
- *  whether the setting is directly writable or not.
- *
- *  If UNSTABLE_DEVEL is defined, then warnings are printed when
- *  settings_destroy() is called if individual settings have not yet been
- *  deleted. (This is to help making sure that code which uses the settings
- *  subsystem correctly un-initializes stuff.)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-/*  Including misc.h should ONLY be necessary to work around the fact that
-    many systems don't have PRIx64 etc defined.  */
-#include "misc.h"
-
-#include "settings.h"
-
-
-struct settings {
-	struct settings		*parent;
-	char			*name_in_parent;
-
-	int			n_settings;
-
-	/*
-	 *  Each setting has a name, a writable flag, a storage type, a
-	 *  presentation format, and a pointer.
-	 *
-	 *  For subsettings, the pointer points to the subsettings object;
-	 *  for other settings, the pointer points to a variable.
-	 *
-	 *  These pointers point to simple linear arrays, containing n_settings
-	 *  entries each.
-	 */
-
-	char			**name;
-	int			*writable;
-	int			*storage_type;
-	int			*presentation_format;
-	void			**ptr;
-};
-
-
-/*
- *  settings_new():
- *
- *  Create a new settings object. Return value is a pointer to the newly
- *  created object. The function does not return on failure.
- */
-struct settings *settings_new(void)
-{
-	struct settings *settings;
-
-	CHECK_ALLOCATION(settings = (struct settings *) malloc(sizeof(struct settings)));
-	memset(settings, 0, sizeof(struct settings));
-
-	return settings;
-}
-
-
-/*
- *  settings_destroy():
- *
- *  Frees all resources occupied by a settings object. Also, if this settings
- *  object has a parent, then remove it from the parent.
- */
-void settings_destroy(struct settings *settings)
-{
-	int i;
-
-	if (settings == NULL) {
-		fprintf(stderr, "settings_destroy(): internal error, "
-		    "settings = NULL!\n");
-		exit(1);
-	}
-
-#ifdef UNSTABLE_DEVEL
-	if (settings->n_settings > 0)
-		printf("settings_destroy(): there are remaining settings!\n");
-#endif
-
-	if (settings->name != NULL) {
-		for (i=0; i<settings->n_settings; i++) {
-			if (settings->name[i] != NULL) {
-#ifdef UNSTABLE_DEVEL
-				printf("settings_destroy(): setting '%s'"
-				    " was not properly deleted before "
-				    "exiting!\n", settings->name[i]);
-#endif
-				free(settings->name[i]);
-			}
-		}
-
-		free(settings->name);
-	} else if (settings->n_settings != 0) {
-		fprintf(stderr, "settings_destroy(): internal error, "
-		    "settings->name = NULL, but there were settings?"
-		    " (n_settings = %i)\n", settings->n_settings);
-		exit(1);
-	}
-
-	if (settings->writable != NULL)
-		free(settings->writable);
-
-	if (settings->storage_type != NULL)
-		free(settings->storage_type);
-
-	if (settings->presentation_format != NULL)
-		free(settings->presentation_format);
-
-	if (settings->ptr != NULL)
-		free(settings->ptr);
-
-	if (settings->parent != NULL) {
-		settings_remove(settings->parent, settings->name_in_parent);
-		free(settings->name_in_parent);
-	}
-
-	free(settings);
-}
-
-
-/*
- *  settings_read():
- *
- *  Used internally by settings_access() and settings_debugdump().
- */
-static int settings_read(struct settings *settings, int i, uint64_t *valuep)
-{
-	*valuep = 0;
-
-	switch (settings->storage_type[i]) {
-	case SETTINGS_TYPE_INT:
-		*valuep = *((int *) settings->ptr[i]);
-		break;
-	case SETTINGS_TYPE_INT8:
-		*valuep = *((int8_t *) settings->ptr[i]);
-		break;
-	case SETTINGS_TYPE_INT16:
-		*valuep = *((int16_t *) settings->ptr[i]);
-		break;
-	case SETTINGS_TYPE_INT32:
-		*valuep = *((int32_t *) settings->ptr[i]);
-		break;
-	case SETTINGS_TYPE_INT64:
-		*valuep = *((int64_t *) settings->ptr[i]);
-		break;
-	case SETTINGS_TYPE_UINT:
-		*valuep = *((uint *) settings->ptr[i]);
-		break;
-	case SETTINGS_TYPE_UINT8:
-		*valuep = *((uint8_t *) settings->ptr[i]);
-		break;
-	case SETTINGS_TYPE_UINT16:
-		*valuep = *((uint16_t *) settings->ptr[i]);
-		break;
-	case SETTINGS_TYPE_UINT32:
-		*valuep = *((uint32_t *) settings->ptr[i]);
-		break;
-	case SETTINGS_TYPE_UINT64:
-		*valuep = *((uint64_t *) settings->ptr[i]);
-		break;
-	case SETTINGS_TYPE_STRING:
-		/*  Note: Strings cannot be read like this.  */
-		break;
-	default:printf("settings_read(): FATAL ERROR! Unknown storage type"
-		    ": %i\n", settings->storage_type[i]);
-		exit(1);
-	}
-
-	return SETTINGS_OK;
-}
-
-
-/*
- *  settings_write():
- *
- *  Used internally by settings_access().
- */
-static int settings_write(struct settings *settings, int i, uint64_t *valuep)
-{
-	if (!settings->writable[i])
-		return SETTINGS_READONLY;
-
-	switch (settings->storage_type[i]) {
-	case SETTINGS_TYPE_INT:
-	case SETTINGS_TYPE_UINT:
-		*((int *) settings->ptr[i]) = *valuep;
-		break;
-	case SETTINGS_TYPE_INT8:
-	case SETTINGS_TYPE_UINT8:
-		*((int8_t *) settings->ptr[i]) = *valuep;
-		break;
-	case SETTINGS_TYPE_INT16:
-	case SETTINGS_TYPE_UINT16:
-		*((int16_t *) settings->ptr[i]) = *valuep;
-		break;
-	case SETTINGS_TYPE_INT32:
-	case SETTINGS_TYPE_UINT32:
-		*((int32_t *) settings->ptr[i]) = *valuep;
-		break;
-	case SETTINGS_TYPE_INT64:
-	case SETTINGS_TYPE_UINT64:
-		*((int64_t *) settings->ptr[i]) = *valuep;
-		break;
-	case SETTINGS_TYPE_STRING:
-		/*  Note: Strings cannot be read like this.  */
-		printf("settings_write(): ERROR! Strings cannot be "
-		    "written like this.\n");
-		break;
-	default:printf("settings_read(): FATAL ERROR! Unknown storage type"
-		    ": %i\n", settings->storage_type[i]);
-		exit(1);
-	}
-
-	return SETTINGS_OK;
-}
-
-
-/*
- *  settings_debugdump():
- *
- *  Dump settings in a settings object to stdout.
- *  If recurse is non-zero, all subsetting objects are also dumped.
- */
-void settings_debugdump(struct settings *settings, const char *prefix,
-	int recurse)
-{
-	size_t name_buflen = strlen(prefix) + 100;
-	char *name;
-	int i;
-	uint64_t value = 0;
-
-	CHECK_ALLOCATION(name = (char *) malloc(name_buflen));
-
-	for (i=0; i<settings->n_settings; i++) {
-		snprintf(name, name_buflen, "%s.%s", prefix, settings->name[i]);
-
-		if (settings->storage_type[i] == SETTINGS_TYPE_SUBSETTINGS) {
-			/*  Subsettings:  */
-			if (recurse)
-				settings_debugdump((struct settings *)settings->ptr[i], name, 1);
-		} else {
-			/*  Normal value:  */
-			printf("%s = ", name);
-
-			settings_read(settings, i, &value);
-
-			switch (settings->presentation_format[i]) {
-			case SETTINGS_FORMAT_DECIMAL:
-				printf("%" PRIi64, value);
-				break;
-			case SETTINGS_FORMAT_HEX8:
-				printf("0x%02" PRIx8, (int8_t) value);
-				break;
-			case SETTINGS_FORMAT_HEX16:
-				printf("0x%04" PRIx16, (int16_t) value);
-				break;
-			case SETTINGS_FORMAT_HEX32:
-				printf("0x%08" PRIx32, (int32_t) value);
-				break;
-			case SETTINGS_FORMAT_HEX64:
-				printf("0x%016" PRIx64, (int64_t) value);
-				break;
-			case SETTINGS_FORMAT_BOOL:
-				printf(value? "true" : "false");
-				break;
-			case SETTINGS_FORMAT_YESNO:
-				printf(value? "yes" : "no");
-				break;
-			case SETTINGS_FORMAT_STRING:
-				printf("\"%s\"", *((char **)settings->ptr[i]));
-				break;
-			default:printf("FATAL ERROR! Unknown presentation "
-				    "format: %i\n",
-				    settings->presentation_format[i]);
-				exit(1);
-			}
-
-			if (!settings->writable[i])
-				printf("  (R/O)");
-
-			printf("\n");
-		}
-	}
-
-	free(name);
-}
-
-
-/*
- *  settings_add():
- *
- *  Add a setting to a settings object.
- */
-void settings_add(struct settings *settings, const char *name, int writable,
-	int type, int format, void *ptr)
-{
-	int i;
-
-	for (i=0; i<settings->n_settings; i++) {
-		if (strcmp(settings->name[i], name) == 0)
-			break;
-	}
-
-	if (i < settings->n_settings) {
-		fprintf(stderr, "settings_add(): name '%s' is already"
-		    " in use\n", name);
-		exit(1);
-	}
-
-	settings->n_settings ++;
-
-	CHECK_ALLOCATION(settings->name = (char **) realloc(settings->name, 
-	    settings->n_settings * sizeof(char *)));
-	CHECK_ALLOCATION(settings->writable = (int *) realloc(settings->writable,
-	    settings->n_settings * sizeof(int)));
-	CHECK_ALLOCATION(settings->storage_type = (int *) realloc(
-	    settings->storage_type, settings->n_settings * sizeof(int)));
-	CHECK_ALLOCATION(settings->presentation_format = (int *) realloc(settings->
-	    presentation_format, settings->n_settings * sizeof(int)));
-	CHECK_ALLOCATION(settings->ptr = (void **) realloc(settings->ptr,
-	    settings->n_settings * sizeof(void *)));
-
-	CHECK_ALLOCATION(settings->name[settings->n_settings - 1] =
-	    strdup(name));
-	settings->writable[settings->n_settings - 1] = writable;
-	settings->storage_type[settings->n_settings - 1] = type;
-	settings->presentation_format[settings->n_settings - 1] = format;
-	settings->ptr[settings->n_settings - 1] = ptr;
-
-	if (type == SETTINGS_TYPE_SUBSETTINGS) {
-		((struct settings *)ptr)->parent = settings;
-		CHECK_ALLOCATION( ((struct settings *)ptr)->name_in_parent =
-		    strdup(name) );
-	}
-}
-
-
-/*
- *  settings_remove():
- *
- *  Remove a setting from a settings object.
- */
-void settings_remove(struct settings *settings, const char *name)
-{
-	int i, m;
-
-	for (i=0; i<settings->n_settings; i++) {
-		if (strcmp(settings->name[i], name) == 0)
-			break;
-	}
-
-	if (i >= settings->n_settings) {
-#ifdef UNSTABLE_DEVEL
-		fprintf(stderr, "settings_remove(): attempting to remove"
-		    " non-existant setting '%s'\n", name);
-#endif
-		return;
-	}
-
-	/*  Check subsettings specifically:  */
-	if (settings->storage_type[i] == SETTINGS_TYPE_SUBSETTINGS &&
-	    settings->ptr[i] != NULL) {
-		struct settings *subsettings = (struct settings *) settings->ptr[i];
-		if (subsettings->n_settings != 0) {
-			fprintf(stderr, "settings_remove(): attempting to "
-			    "remove non-emtpy setting '%s'\n", name);
-			fprintf(stderr, "Remaining settings are:\n");
-			for (i=0; i<subsettings->n_settings; i++)
-				fprintf(stderr, "\t%s\n", subsettings->name[i]);
-			exit(1);
-		}
-	}
-
-	settings->n_settings --;
-	free(settings->name[i]);
-
-	m = settings->n_settings - i;
-	if (m == 0)
-		return;
-
-	memmove(&settings->name[i], &settings->name[i+1],
-	    m * sizeof(settings->name[0]));
-	memmove(&settings->writable[i], &settings->writable[i+1],
-	    m * sizeof(settings->writable[0]));
-	memmove(&settings->storage_type[i], &settings->storage_type[i+1],
-	    m * sizeof(settings->storage_type[0]));
-	memmove(&settings->presentation_format[i],
-	    &settings->presentation_format[i+1],
-	    m * sizeof(settings->presentation_format[0]));
-	memmove(&settings->ptr[i], &settings->ptr[i+1],
-	    m * sizeof(settings->ptr[0]));
-}
-
-
-/*
- *  settings_remove_all():
- *
- *  Remove all (level-1) settings from a settings object. By level-1, I mean
- *  all settings that do not contain subsettings.
- */
-void settings_remove_all(struct settings *settings)
-{
-	while (settings->n_settings > 0)
-		settings_remove(settings, settings->name[0]);
-}
-
-
-/*
- *  settings_access():
- *
- *  Read or write a setting. fullname may be something like "settings.x.y".
- *  When writing a value, valuebuf should point to a uint64_t containing the
- *  new value (note: always a uint64_t). When reading a value, valuebuf should
- *  point to a uint64_t where the value will be stored.
- *
- *  The return value is one of the following:
- *
- *	SETTINGS_OK
- *		The value was read or written.
- *
- *	SETTINGS_NAME_NOT_FOUND
- *		The name was not found in the settings object.
- *
- *	SETTINGS_READONLY
- *		The name was found, but it was marked as read-only, and
- *		an attempt was made to write to it.
- */
-int settings_access(struct settings *settings, const char *fullname,
-        int writeflag, uint64_t *valuep)
-{
-	int i;
-
-	/*  printf("settings_access(fullname='%s')\n", fullname);  */
-
-	if (strncmp(fullname, GLOBAL_SETTINGS_NAME".",
-	    strlen(GLOBAL_SETTINGS_NAME) + 1) == 0)
-		fullname += strlen(GLOBAL_SETTINGS_NAME) + 1;
-
-	for (i=0; i<settings->n_settings; i++) {
-		size_t settings_name_len = strlen(settings->name[i]);
-
-		if (strncmp(fullname, settings->name[i],
-		    settings_name_len) != 0)
-			continue;
-
-		/*  Found the correct setting?  */
-		if (fullname[settings_name_len] == '\0') {
-			if (writeflag)
-				return settings_write(settings, i, valuep);
-			else
-				return settings_read(settings, i, valuep);
-		}
-
-		/*  Found a setting which has sub-settings?  */
-		if (fullname[settings_name_len] == '.') {
-			/*  Recursive search:  */
-			return settings_access(
-			    (struct settings *)settings->ptr[i],
-			    fullname + settings_name_len + 1,
-			    writeflag, valuep);
-		}
-	}
-
-	return SETTINGS_NAME_NOT_FOUND;
-}
-
diff -Nru gxemul-0.6.2/src/old_main/timer.cc gxemul-0.7.0+dfsg/src/old_main/timer.cc
--- gxemul-0.6.2/src/old_main/timer.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/old_main/timer.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,301 +0,0 @@
-/*
- *  Copyright (C) 2006-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Timer framework. This is used by emulated clocks.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <signal.h>
-#include <string.h>
-#include <unistd.h>
-#include <sys/time.h>
-
-#include "misc.h"
-#include "timer.h"
-
-
-/*  #define TEST  */
-
-
-struct timer {
-	struct timer	*next;
-
-	double		freq;
-	void		(*timer_tick)(struct timer *timer, void *extra);
-	void		*extra;
-
-	double		interval;
-	double		next_tick_at;
-};
-
-static struct timer *first_timer = NULL;
-struct timeval timer_start_tv;
-static double timer_freq;
-static int timer_countdown_to_next_gettimeofday;
-static double timer_current_time;
-static double timer_current_time_step;
-
-static int timer_is_running;
-
-#define	SECONDS_BETWEEN_GETTIMEOFDAY_SYNCH	1.65
-
-
-/*
- *  timer_add():
- *
- *  Adds a virtual timer to the list of timers.
- *
- *  Return value is a pointer to a timer struct.
- */
-struct timer *timer_add(double freq, void (*timer_tick)(struct timer *timer,
-	void *extra), void *extra)
-{
-	struct timer *newtimer;
-
-	CHECK_ALLOCATION(newtimer = (struct timer *) malloc(sizeof(struct timer)));
-
-	if (freq <= 0.00000001)
-		freq = 0.00000001;
-
-	newtimer->freq = freq;
-	newtimer->timer_tick = timer_tick;
-	newtimer->extra = extra;
-
-	newtimer->interval = 1.0 / freq;
-	newtimer->next_tick_at = timer_current_time + newtimer->interval;
-
-	newtimer->next = first_timer;
-	first_timer = newtimer;
-
-	return newtimer;
-}
-
-
-/*
- *  timer_remove():
- *
- *  Removes a virtual timer from the list of timers.
- */
-void timer_remove(struct timer *t)
-{
-	struct timer *prev = NULL, *cur = first_timer;
-
-	while (cur != NULL && cur != t) {
-		prev = cur;
-		cur = cur->next;
-	}
-
-	if (cur == t) {
-		if (prev == NULL)
-			first_timer = cur->next;
-		else
-			prev->next = cur->next;
-		free(cur);
-	} else {
-		fprintf(stderr, "attempt to remove timer %p which "
-		    "doesn't exist. aborting\n", t);
-		exit(1);
-	}
-}
-
-
-/*
- *  timer_update_frequency():
- *
- *  Changes the frequency of an existing timer.
- */
-void timer_update_frequency(struct timer *t, double new_freq)
-{
-	if (t->freq == new_freq)
-		return;
-
-	t->freq = new_freq;
-
-	if (new_freq <= 0.00000001)
-		new_freq = 0.00000001;
-
-	t->interval = 1.0 / new_freq;
-	t->next_tick_at = timer_current_time + t->interval;
-}
-
-
-/*
- *  timer_tick():
- *
- *  Timer tick handler. This is where the interesting stuff happens.
- */
-static void timer_tick(int signal_nr)
-{
-	struct timer *timer = first_timer;
-	struct timeval tv;
-
-	timer_current_time += timer_current_time_step;
-
-	if ((--timer_countdown_to_next_gettimeofday) < 0) {
-		gettimeofday(&tv, NULL);
-		tv.tv_sec -= timer_start_tv.tv_sec;
-		tv.tv_usec -= timer_start_tv.tv_usec;
-		if (tv.tv_usec < 0) {
-			tv.tv_usec += 1000000;
-			tv.tv_sec --;
-		}
-
-#ifdef TIMER_DEBUG
-		/*  For debugging/testing:  */
-		{
-			double diff = tv.tv_usec * 0.000001 + tv.tv_sec
-			    - timer_current_time;
-			printf("timer: lagging behind %f seconds\n", diff);
-		}
-#endif
-
-		/*  Get exponentially closer to the real time, instead of
-		    just changing to it directly:  */
-		timer_current_time = ( (tv.tv_usec * 0.000001 + tv.tv_sec) +
-		    timer_current_time ) / 2;
-
-		timer_countdown_to_next_gettimeofday = (int64_t) (timer_freq *
-		    SECONDS_BETWEEN_GETTIMEOFDAY_SYNCH);
-	}
-
-	while (timer != NULL) {
-		while (timer_current_time >= timer->next_tick_at) {
-			timer->timer_tick(timer, timer->extra);
-			timer->next_tick_at += timer->interval;
-		}
-
-		timer = timer->next;
-	}
-
-#ifdef TEST
-	printf("T"); fflush(stdout);
-#endif
-}
-
-
-/*
- *  timer_start():
- *
- *  Set the interval timer to timer_freq Hz, and install the signal handler.
- */
-void timer_start(void)
-{
-	struct timer *timer = first_timer;
-	struct itimerval val;
-	struct sigaction saction;
-
-	if (timer_is_running)
-		return;
-
-	timer_is_running = 1;
-
-	gettimeofday(&timer_start_tv, NULL);
-	timer_current_time = 0.0;
-
-	/*  Reset all timers:  */
-	while (timer != NULL) {
-		timer->next_tick_at = timer->interval;
-		timer = timer->next;
-	}
-	val.it_interval.tv_sec = 0;
-	val.it_interval.tv_usec = (int) (1000000.0 / timer_freq);
-	val.it_value.tv_sec = 0;
-	val.it_value.tv_usec = (int) (1000000.0 / timer_freq);
-
-	memset(&saction, 0, sizeof(saction));
-	saction.sa_handler = timer_tick;
-	saction.sa_flags = SA_RESTART;
-
-	sigaction(SIGALRM, &saction, NULL);
-
-	setitimer(ITIMER_REAL, &val, NULL);
-}
-
-
-/*
- *  timer_stop():
- *
- *  Deinstall the signal handler, and disable the interval timer.
- */
-void timer_stop(void)
-{
-	struct itimerval val;
-	struct sigaction saction;
-
-	if (!timer_is_running)
-		return;
-
-	timer_is_running = 0;
-
-	val.it_interval.tv_sec = 0;
-	val.it_interval.tv_usec = 0;
-	val.it_value.tv_sec = 0;
-	val.it_value.tv_usec = 0;
-
-	setitimer(ITIMER_REAL, &val, NULL);
-
-	memset(&saction, 0, sizeof(saction));
-	saction.sa_handler = NULL;
-
-	sigaction(SIGALRM, &saction, NULL);
-}
-
-
-#ifdef TEST
-static void timer_tick_test(struct timer *t, void *extra)
-{
-	printf((char *) extra); fflush(stdout);
-}
-#endif
-
-
-/*
- *  timer_init():
- *
- *  Initialize the timer framework.
- */
-void timer_init(void)
-{
-	first_timer = NULL;
-	timer_current_time = 0.0;
-	timer_is_running = 0;
-	timer_countdown_to_next_gettimeofday = 0;
-
-	timer_freq = TIMER_BASE_FREQUENCY;
-	timer_current_time_step = 1.0 / timer_freq;
-
-#ifdef TEST
-	timer_add(0.5, timer_tick_test, "X");
-	timer_add(10.0, timer_tick_test, ".");
-	timer_add(200.0, timer_tick_test, " ");
-	timer_start();
-	while (1)
-		sleep(999999);
-#endif
-}
-
diff -Nru gxemul-0.6.2/src/promemul/arcbios.c gxemul-0.7.0+dfsg/src/promemul/arcbios.c
--- gxemul-0.6.2/src/promemul/arcbios.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/arcbios.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,3162 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: ARCBIOS and ARCS emulation
+ *
+ *  Some good info here:
+ *	https://www.linux-mips.org/wiki/ARC
+ *	
+ */
+
+#include <ctype.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include <unistd.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <sys/resource.h>
+
+#include "arcbios.h"
+#include "console.h"
+#include "cpu.h"
+#include "cpu_mips.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "machine_arc.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/arcbios_other.h"
+
+
+extern int quiet_mode;
+extern int verbose;
+
+
+/*
+ *  arcbios_add_string_to_component():
+ */
+void arcbios_add_string_to_component(struct machine *machine,
+	char *str, uint64_t component)
+{
+	if (machine->md.arc->n_string_to_components
+	    >= MAX_STRING_TO_COMPONENT) {
+		printf("Too many string-to-component mappings.\n");
+		exit(1);
+	}
+
+	CHECK_ALLOCATION(machine->md.arc->string_to_component[machine->
+	    md.arc->n_string_to_components] = strdup(str));
+
+	debug("adding ARC component mapping: 0x%08x = %s\n",
+	    (int)component, str);
+
+	machine->md.arc->string_to_component_value[
+	    machine->md.arc->n_string_to_components] = component;
+
+	machine->md.arc->n_string_to_components ++;
+}
+
+
+/*
+ *  arcbios_get_dsp_stat():
+ *
+ *  Fills in an arcbios_dsp_stat struct with valid data.
+ */
+static void arcbios_get_dsp_stat(struct cpu *cpu,
+	struct arcbios_dsp_stat *dspstat)
+{
+	memset(dspstat, 0, sizeof(struct arcbios_dsp_stat));
+
+	store_16bit_word_in_host(cpu, (unsigned char *)&dspstat->
+	    CursorXPosition, cpu->machine->md.arc->console_curx + 1);
+	store_16bit_word_in_host(cpu, (unsigned char *)&dspstat->
+	    CursorYPosition, cpu->machine->md.arc->console_cury + 1);
+	store_16bit_word_in_host(cpu, (unsigned char *)&dspstat->
+	    CursorMaxXPosition, ARC_CONSOLE_MAX_X);
+	store_16bit_word_in_host(cpu, (unsigned char *)&dspstat->
+	    CursorMaxYPosition, ARC_CONSOLE_MAX_Y);
+	dspstat->ForegroundColor = cpu->machine->md.arc->console_curcolor;
+	dspstat->HighIntensity = cpu->machine->md.arc->console_curcolor ^ 0x08;
+}
+
+
+/*
+ *  arcbios_putcell():
+ */
+static void arcbios_putcell(struct cpu *cpu, int ch, int x, int y)
+{
+	unsigned char buf[2];
+	buf[0] = ch;
+	buf[1] = cpu->machine->md.arc->console_curcolor;
+	if (cpu->machine->md.arc->console_reverse)
+		buf[1] = ((buf[1] & 0x70) >> 4) | ((buf[1] & 7) << 4)
+		    | (buf[1] & 0x88);
+	cpu->memory_rw(cpu, cpu->mem, cpu->machine->md.arc->console_vram +
+	    2*(x + cpu->machine->md.arc->console_maxx * y),
+	    &buf[0], sizeof(buf), MEM_WRITE,
+	    CACHE_NONE | PHYSICAL);
+}
+
+
+/*
+ *  handle_esc_seq():
+ *
+ *  Used by arcbios_putchar().
+ */
+static void handle_esc_seq(struct cpu *cpu)
+{
+	int i, len = strlen(cpu->machine->md.arc->escape_sequence);
+	int row, col, color, code, start, stop;
+	char *p;
+
+	if (cpu->machine->md.arc->escape_sequence[0] != '[')
+		return;
+
+	code = cpu->machine->md.arc->escape_sequence[len-1];
+	cpu->machine->md.arc->escape_sequence[len-1] = '\0';
+
+	switch (code) {
+	case 'm':
+		color = atoi(cpu->machine->md.arc->escape_sequence + 1);
+		switch (color) {
+		case 0:	/*  Default.  */
+			cpu->machine->md.arc->console_curcolor = 0x1f;
+			cpu->machine->md.arc->console_reverse = 0; break;
+		case 1:	/*  "Bold".  */
+			cpu->machine->md.arc->console_curcolor |= 0x08; break;
+		case 7:	/*  "Reverse".  */
+			cpu->machine->md.arc->console_reverse = 1; break;
+		case 30: /*  Black foreground.  */
+			cpu->machine->md.arc->console_curcolor &= 0xf0;
+			cpu->machine->md.arc->console_curcolor |= 0x00; break;
+		case 31: /*  Red foreground.  */
+			cpu->machine->md.arc->console_curcolor &= 0xf0;
+			cpu->machine->md.arc->console_curcolor |= 0x04; break;
+		case 32: /*  Green foreground.  */
+			cpu->machine->md.arc->console_curcolor &= 0xf0;
+			cpu->machine->md.arc->console_curcolor |= 0x02; break;
+		case 33: /*  Yellow foreground.  */
+			cpu->machine->md.arc->console_curcolor &= 0xf0;
+			cpu->machine->md.arc->console_curcolor |= 0x06; break;
+		case 34: /*  Blue foreground.  */
+			cpu->machine->md.arc->console_curcolor &= 0xf0;
+			cpu->machine->md.arc->console_curcolor |= 0x01; break;
+		case 35: /*  Red-blue foreground.  */
+			cpu->machine->md.arc->console_curcolor &= 0xf0;
+			cpu->machine->md.arc->console_curcolor |= 0x05; break;
+		case 36: /*  Green-blue foreground.  */
+			cpu->machine->md.arc->console_curcolor &= 0xf0;
+			cpu->machine->md.arc->console_curcolor |= 0x03; break;
+		case 37: /*  White foreground.  */
+			cpu->machine->md.arc->console_curcolor &= 0xf0;
+			cpu->machine->md.arc->console_curcolor |= 0x07; break;
+		case 40: /*  Black background.  */
+			cpu->machine->md.arc->console_curcolor &= 0x0f;
+			cpu->machine->md.arc->console_curcolor |= 0x00; break;
+		case 41: /*  Red background.  */
+			cpu->machine->md.arc->console_curcolor &= 0x0f;
+			cpu->machine->md.arc->console_curcolor |= 0x40; break;
+		case 42: /*  Green background.  */
+			cpu->machine->md.arc->console_curcolor &= 0x0f;
+			cpu->machine->md.arc->console_curcolor |= 0x20; break;
+		case 43: /*  Yellow background.  */
+			cpu->machine->md.arc->console_curcolor &= 0x0f;
+			cpu->machine->md.arc->console_curcolor |= 0x60; break;
+		case 44: /*  Blue background.  */
+			cpu->machine->md.arc->console_curcolor &= 0x0f;
+			cpu->machine->md.arc->console_curcolor |= 0x10; break;
+		case 45: /*  Red-blue background.  */
+			cpu->machine->md.arc->console_curcolor &= 0x0f;
+			cpu->machine->md.arc->console_curcolor |= 0x50; break;
+		case 46: /*  Green-blue background.  */
+			cpu->machine->md.arc->console_curcolor &= 0x0f;
+			cpu->machine->md.arc->console_curcolor |= 0x30; break;
+		case 47: /*  White background.  */
+			cpu->machine->md.arc->console_curcolor &= 0x0f;
+			cpu->machine->md.arc->console_curcolor |= 0x70; break;
+		default:fatal("{ handle_esc_seq: color %i }\n", color);
+		}
+		return;
+	case 'H':
+		p = strchr(cpu->machine->md.arc->escape_sequence, ';');
+		if (p == NULL)
+			return;		/*  TODO  */
+		row = atoi(cpu->machine->md.arc->escape_sequence + 1);
+		col = atoi(p + 1);
+		if (col < 1)
+			col = 1;
+		if (row < 1)
+			row = 1;
+		cpu->machine->md.arc->console_curx = col - 1;
+		cpu->machine->md.arc->console_cury = row - 1;
+		return;
+	case 'J':
+		/*
+		 *  J = clear screen below cursor, and the rest of the
+		 *      current line,
+		 *  2J = clear whole screen.
+		 */
+		i = atoi(cpu->machine->md.arc->escape_sequence + 1);
+		if (i != 0 && i != 2)
+			fatal("{ handle_esc_seq(): %iJ }\n", i);
+		if (i == 0)
+			for (col = cpu->machine->md.arc->console_curx;
+			    col < cpu->machine->md.arc->console_maxx; col++)
+				arcbios_putcell(cpu, ' ', col,
+				    cpu->machine->md.arc->console_cury);
+		for (col = 0; col < cpu->machine->md.arc->console_maxx; col++)
+			for (row = i? 0 : cpu->machine->md.arc->console_cury+1;
+			    row < cpu->machine->md.arc->console_maxy; row++)
+				arcbios_putcell(cpu, ' ', col, row);
+		return;
+	case 'K':
+		col = atoi(cpu->machine->md.arc->escape_sequence + 1);
+		/*  2 = clear line to the right. 1 = to the left (?)  */
+		start = 0; stop = cpu->machine->md.arc->console_curx;
+		if (col == 2) {
+			start = cpu->machine->md.arc->console_curx;
+			stop = cpu->machine->md.arc->console_maxx - 1;
+		}
+		for (i=start; i<=stop; i++)
+			arcbios_putcell(cpu, ' ', i,
+			    cpu->machine->md.arc->console_cury);
+
+		return;
+	}
+
+	fatal("{ handle_esc_seq(): unimplemented escape sequence: ");
+	for (i=0; i<len; i++) {
+		int x = cpu->machine->md.arc->escape_sequence[i];
+		if (i == len-1)
+			x = code;
+
+		if (x >= ' ' && x < 127)
+			fatal("%c", x);
+		else
+			fatal("[0x%02x]", x);
+	}
+	fatal(" }\n");
+}
+
+
+/*
+ *  scroll_if_necessary():
+ */
+static void scroll_if_necessary(struct cpu *cpu)
+{
+	/*  Scroll?  */
+	if (cpu->machine->md.arc->console_cury >=
+	    cpu->machine->md.arc->console_maxy) {
+		unsigned char buf[2];
+		int x, y;
+		for (y=0; y<cpu->machine->md.arc->console_maxy-1; y++)
+			for (x=0; x<cpu->machine->md.arc->console_maxx;
+			    x++) {
+				cpu->memory_rw(cpu, cpu->mem,
+				    cpu->machine->md.arc->console_vram +
+				    2*(x + cpu->machine->md.arc->
+					console_maxx * (y+1)),
+				    &buf[0], sizeof(buf), MEM_READ,
+				    CACHE_NONE | PHYSICAL);
+				cpu->memory_rw(cpu, cpu->mem,
+				    cpu->machine->md.arc->console_vram +
+				    2*(x + cpu->machine->md.arc->
+					console_maxx * y),
+				    &buf[0], sizeof(buf), MEM_WRITE,
+				    CACHE_NONE | PHYSICAL);
+			}
+
+		cpu->machine->md.arc->console_cury =
+		    cpu->machine->md.arc->console_maxy - 1;
+
+		for (x=0; x<cpu->machine->md.arc->console_maxx; x++)
+			arcbios_putcell(cpu, ' ', x,
+			    cpu->machine->md.arc->console_cury);
+	}
+}
+
+
+/*
+ *  arcbios_putchar():
+ *
+ *  If we're using X11 with VGA-style console, then output to that console.
+ *  Otherwise, use console_putchar().
+ */
+static void arcbios_putchar(struct cpu *cpu, int ch)
+{
+	int addr;
+	unsigned char byte;
+
+	if (!cpu->machine->md.arc->vgaconsole) {
+		/*  Text console output:  */
+
+		/*  Hack for Windows NT, which uses 0x9b instead of ESC + [  */
+		if (ch == 0x9b) {
+			console_putchar(cpu->machine->main_console_handle, 27);
+			ch = '[';
+		}
+		console_putchar(cpu->machine->main_console_handle, ch);
+		return;
+	}
+
+	if (cpu->machine->md.arc->in_escape_sequence) {
+		int len = strlen(cpu->machine->md.arc->escape_sequence);
+		cpu->machine->md.arc->escape_sequence[len] = ch;
+		len++;
+		if (len >= ARC_MAX_ESC)
+			len = ARC_MAX_ESC;
+		cpu->machine->md.arc->escape_sequence[len] = '\0';
+		if ((ch >= 'a' && ch <= 'z') ||
+		    (ch >= 'A' && ch <= 'Z') || len >= ARC_MAX_ESC) {
+			handle_esc_seq(cpu);
+			cpu->machine->md.arc->in_escape_sequence = 0;
+		}
+	} else {
+		if (ch == 27) {
+			cpu->machine->md.arc->in_escape_sequence = 1;
+			cpu->machine->md.arc->escape_sequence[0] = '\0';
+		} else if (ch == 0x9b) {
+			cpu->machine->md.arc->in_escape_sequence = 1;
+			cpu->machine->md.arc->escape_sequence[0] = '[';
+			cpu->machine->md.arc->escape_sequence[1] = '\0';
+		} else if (ch == '\b') {
+			if (cpu->machine->md.arc->console_curx > 0)
+				cpu->machine->md.arc->console_curx --;
+		} else if (ch == '\r') {
+			cpu->machine->md.arc->console_curx = 0;
+		} else if (ch == '\n') {
+			cpu->machine->md.arc->console_cury ++;
+		} else if (ch == '\t') {
+			cpu->machine->md.arc->console_curx =
+			    ((cpu->machine->md.arc->console_curx - 1)
+			    | 7) + 1;
+			/*  TODO: Print spaces?  */
+		} else {
+			/*  Put char:  */
+			if (cpu->machine->md.arc->console_curx >=
+			    cpu->machine->md.arc->console_maxx) {
+				cpu->machine->md.arc->console_curx = 0;
+				cpu->machine->md.arc->console_cury ++;
+				scroll_if_necessary(cpu);
+			}
+			arcbios_putcell(cpu, ch,
+			    cpu->machine->md.arc->console_curx,
+			    cpu->machine->md.arc->console_cury);
+			cpu->machine->md.arc->console_curx ++;
+		}
+	}
+
+	scroll_if_necessary(cpu);
+
+	/*  Update cursor position:  */
+	addr = (cpu->machine->md.arc->console_curx >=
+	    cpu->machine->md.arc->console_maxx?
+	    cpu->machine->md.arc->console_maxx - 1 :
+		cpu->machine->md.arc->console_curx) +
+	    cpu->machine->md.arc->console_cury *
+	    cpu->machine->md.arc->console_maxx;
+	byte = 0x0e;
+	cpu->memory_rw(cpu, cpu->mem, cpu->machine->md.arc->
+	    console_ctrlregs + 0x14,
+	    &byte, sizeof(byte), MEM_WRITE, CACHE_NONE | PHYSICAL);
+	byte = (addr >> 8) & 255;
+	cpu->memory_rw(cpu, cpu->mem, cpu->machine->md.arc->
+	    console_ctrlregs + 0x15,
+	    &byte, sizeof(byte), MEM_WRITE, CACHE_NONE | PHYSICAL);
+	byte = 0x0f;
+	cpu->memory_rw(cpu, cpu->mem, cpu->machine->md.arc->
+	    console_ctrlregs + 0x14,
+	    &byte, sizeof(byte), MEM_WRITE, CACHE_NONE | PHYSICAL);
+	byte = addr & 255;
+	cpu->memory_rw(cpu, cpu->mem, cpu->machine->md.arc->
+	    console_ctrlregs + 0x15,
+	    &byte, sizeof(byte), MEM_WRITE, CACHE_NONE | PHYSICAL);
+}
+
+
+/*
+ *  arcbios_putstring():
+ */
+static void arcbios_putstring(struct cpu *cpu, const char *s)
+{
+	while (*s) {
+		if (*s == '\n')
+			arcbios_putchar(cpu, '\r');
+		arcbios_putchar(cpu, *s++);
+	}
+}
+
+
+/*
+ *  arcbios_register_scsicontroller():
+ */
+void arcbios_register_scsicontroller(struct machine *machine,
+	uint64_t scsicontroller_component)
+{
+	machine->md.arc->scsicontroller = scsicontroller_component;
+}
+
+
+/*
+ *  arcbios_get_scsicontroller():
+ */
+uint64_t arcbios_get_scsicontroller(struct machine *machine)
+{
+	return machine->md.arc->scsicontroller;
+}
+
+
+/*
+ *  arcbios_add_memory_descriptor():
+ *
+ *  NOTE: arctype is the ARC type, not the SGI type. This function takes
+ *  care of converting, when necessary.
+ */
+void arcbios_add_memory_descriptor(struct cpu *cpu,
+	uint64_t base, uint64_t len, int arctype)
+{
+	uint64_t memdesc_addr;
+	int s;
+	struct arcbios_mem arcbios_mem;
+	struct arcbios_mem64 arcbios_mem64;
+
+	if (verbose >= 2)
+		debug("arcbios_add_memory_descriptor: base=0x%llx len=0x%llx arctype=%i\n",
+			(long long)base, (long long)len, arctype);
+
+	base /= 4096;
+	len /= 4096;
+
+	/*
+	 *  TODO: Huh? Why isn't it necessary to convert from arc to sgi types?
+	 *
+	 *  TODO 2: It seems that it _is_ necessary, but NetBSD's arcdiag
+	 *  doesn't handle the sgi case separately.
+	 */
+#if 1
+	if (cpu->machine->machine_type == MACHINE_SGI) {
+		/*  arctype is SGI style  */
+		/*  printf("%i => ", arctype); */
+		switch (arctype) {
+		case 0:	arctype = 0; break;
+		case 1:	arctype = 1; break;
+		case 2:	arctype = 3; break;
+		case 3:	arctype = 4; break;
+		case 4:	arctype = 5; break;
+		case 5:	arctype = 6; break;
+		case 6:	arctype = 7; break;
+		case 7:	arctype = 2; break;
+		}
+		/*  printf("%i\n", arctype);  */
+	}
+#endif
+	if (cpu->machine->md.arc->arc_64bit)
+		s = sizeof(arcbios_mem64);
+	else
+		s = sizeof(arcbios_mem);
+
+	memdesc_addr = cpu->machine->md.arc->memdescriptor_base +
+	    cpu->machine->md.arc->n_memdescriptors * s;
+
+	if (cpu->machine->md.arc->arc_64bit) {
+		memset(&arcbios_mem64, 0, s);
+		store_32bit_word_in_host(cpu,
+		    (unsigned char *)&arcbios_mem64.Type, arctype);
+		store_64bit_word_in_host(cpu,
+		    (unsigned char *)&arcbios_mem64.BasePage, base);
+		store_64bit_word_in_host(cpu,
+		    (unsigned char *)&arcbios_mem64.PageCount, len);
+		store_buf(cpu, memdesc_addr, (char *)&arcbios_mem64, s);
+	} else {
+		memset(&arcbios_mem, 0, s);
+		store_32bit_word_in_host(cpu,
+		    (unsigned char *)&arcbios_mem.Type, arctype);
+		store_32bit_word_in_host(cpu,
+		    (unsigned char *)&arcbios_mem.BasePage, base);
+		store_32bit_word_in_host(cpu,
+		    (unsigned char *)&arcbios_mem.PageCount, len);
+		store_buf(cpu, memdesc_addr, (char *)&arcbios_mem, s);
+	}
+
+	cpu->machine->md.arc->n_memdescriptors ++;
+}
+
+
+/*
+ *  arcbios_addchild():
+ *
+ *  host_tmp_component is a temporary component, with data formated for
+ *  the host system.  It needs to be translated/copied into emulated RAM.
+ *
+ *  Return value is the virtual (emulated) address of the added component.
+ *
+ *  TODO:  This function doesn't care about memory management, but simply
+ *         stores the new child after the last stored child.
+ *  TODO:  This stuff is really ugly.
+ */
+static uint64_t arcbios_addchild(struct cpu *cpu,
+	struct arcbios_component *host_tmp_component,
+	const char *identifier, uint32_t parent)
+{
+	struct machine *machine = cpu->machine;
+	uint64_t a = machine->md.arc->next_component_address;
+	uint32_t peer=0;
+	uint32_t child=0;
+	int n_left;
+	uint64_t peeraddr = FIRST_ARC_COMPONENT;
+
+	/*
+	 *  This component has no children yet, but it may have peers (that is,
+	 *  other components that share this component's parent) so we have to
+	 *  set the peer value correctly.
+	 *
+	 *  Also, if this is the first child of some parent, the parent's child
+	 *  pointer should be set to point to this component.  (But only if it
+	 *  is the first.)
+	 *
+	 *  This is really ugly:  scan through all components, starting from
+	 *  FIRST_ARC_COMPONENT, to find a component with the same parent as
+	 *  this component will have.  If such a component is found, and its
+	 *  'peer' value is NULL, then set it to this component's address (a).
+	 *
+	 *  TODO:  make this nicer
+	 */
+
+	n_left = machine->md.arc->n_components;
+	while (n_left > 0) {
+		/*  Load parent, child, and peer values:  */
+		uint32_t eparent, echild, epeer, tmp;
+		unsigned char buf[4];
+
+		/*  debug("[ addchild: peeraddr = 0x%08x ]\n",
+		    (int)peeraddr);  */
+
+		cpu->memory_rw(cpu, cpu->mem,
+		    peeraddr + 0 * machine->md.arc->wordlen, &buf[0],
+		    sizeof(eparent), MEM_READ, CACHE_NONE);
+		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+			unsigned char tmp2;
+			tmp2 = buf[0]; buf[0] = buf[3]; buf[3] = tmp2;
+			tmp2 = buf[1]; buf[1] = buf[2]; buf[2] = tmp2;
+		}
+		epeer   = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
+
+		cpu->memory_rw(cpu, cpu->mem, peeraddr + 1 *
+		    machine->md.arc->wordlen,
+		    &buf[0], sizeof(eparent), MEM_READ, CACHE_NONE);
+		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+			unsigned char tmp2;
+			tmp2 = buf[0]; buf[0] = buf[3]; buf[3] = tmp2;
+			tmp2 = buf[1]; buf[1] = buf[2]; buf[2] = tmp2;
+		}
+		echild  = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
+
+		cpu->memory_rw(cpu, cpu->mem, peeraddr + 2 *
+		    machine->md.arc->wordlen,
+		    &buf[0], sizeof(eparent), MEM_READ, CACHE_NONE);
+		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+			unsigned char tmp2;
+			tmp2 = buf[0]; buf[0] = buf[3]; buf[3] = tmp2;
+			tmp2 = buf[1]; buf[1] = buf[2]; buf[2] = tmp2;
+		}
+		eparent = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
+
+		/*  debug("  epeer=%x echild=%x eparent=%x\n",
+		    (int)epeer,(int)echild,(int)eparent);  */
+
+		if ((uint32_t)eparent == (uint32_t)parent &&
+		    (uint32_t)epeer == 0) {
+			epeer = a;
+			store_32bit_word(cpu, peeraddr + 0x00, epeer);
+			/*  debug("[ addchild: adding 0x%08x as peer "
+			    "to 0x%08x ]\n", (int)a, (int)peeraddr);  */
+		}
+		if ((uint32_t)peeraddr == (uint32_t)parent &&
+		    (uint32_t)echild == 0) {
+			echild = a;
+			store_32bit_word(cpu, peeraddr + 0x04, echild);
+			/*  debug("[ addchild: adding 0x%08x as "
+			    "child to 0x%08x ]\n", (int)a, (int)peeraddr);  */
+		}
+
+		/*  Go to the next component:  */
+		cpu->memory_rw(cpu, cpu->mem, peeraddr + 0x28, &buf[0],
+		    sizeof(eparent), MEM_READ, CACHE_NONE);
+		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+			unsigned char tmp2;
+			tmp2 = buf[0]; buf[0] = buf[3]; buf[3] = tmp2;
+			tmp2 = buf[1]; buf[1] = buf[2]; buf[2] = tmp2;
+		}
+		
+		tmp = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
+		peeraddr += 0x30;
+		peeraddr += tmp + 1;
+		peeraddr = ((peeraddr - 1) | 3) + 1;
+
+		n_left --;
+	}
+
+	store_32bit_word(cpu, a + 0x00, peer);
+	store_32bit_word(cpu, a + 0x04, child);
+	store_32bit_word(cpu, a + 0x08, parent);
+	store_32bit_word(cpu, a+  0x0c, host_tmp_component->Class);
+	store_32bit_word(cpu, a+  0x10, host_tmp_component->Type);
+	store_32bit_word(cpu, a+  0x14, host_tmp_component->Flags +
+	    65536 * host_tmp_component->Version);
+	store_32bit_word(cpu, a+  0x18, host_tmp_component->Revision);
+	store_32bit_word(cpu, a+  0x1c, host_tmp_component->Key);
+	store_32bit_word(cpu, a+  0x20, host_tmp_component->AffinityMask);
+	store_32bit_word(cpu, a+  0x24, host_tmp_component->
+	    ConfigurationDataSize);
+	store_32bit_word(cpu, a+  0x28, host_tmp_component->IdentifierLength);
+	store_32bit_word(cpu, a+  0x2c, host_tmp_component->Identifier);
+
+	machine->md.arc->next_component_address += 0x30;
+
+	if (host_tmp_component->IdentifierLength != 0) {
+		store_32bit_word(cpu, a + 0x2c, a + 0x30);
+		store_string(cpu, a + 0x30, identifier);
+		if (identifier != NULL)
+			machine->md.arc->next_component_address +=
+			    strlen(identifier) + 1;
+	}
+
+	machine->md.arc->next_component_address ++;
+
+	/*  Round up to next 0x4 bytes:  */
+	machine->md.arc->next_component_address =
+	    ((machine->md.arc->next_component_address - 1) | 3) + 1;
+
+	machine->md.arc->n_components ++;
+
+	return a;
+}
+
+
+/*
+ *  arcbios_addchild64():
+ *
+ *  host_tmp_component is a temporary component, with data formated for
+ *  the host system.  It needs to be translated/copied into emulated RAM.
+ *
+ *  Return value is the virtual (emulated) address of the added component.
+ *
+ *  TODO:  This function doesn't care about memory management, but simply
+ *         stores the new child after the last stored child.
+ *  TODO:  This stuff is really ugly.
+ */
+static uint64_t arcbios_addchild64(struct cpu *cpu,
+	struct arcbios_component64 *host_tmp_component,
+	const char *identifier, uint64_t parent)
+{
+	struct machine *machine = cpu->machine;
+	uint64_t a = machine->md.arc->next_component_address;
+	uint64_t peer=0;
+	uint64_t child=0;
+	int n_left;
+	uint64_t peeraddr = FIRST_ARC_COMPONENT;
+
+	/*
+	 *  This component has no children yet, but it may have peers (that is,
+	 *  other components that share this component's parent) so we have to
+	 *  set the peer value correctly.
+	 *
+	 *  Also, if this is the first child of some parent, the parent's child
+	 *  pointer should be set to point to this component.  (But only if it
+	 *  is the first.)
+	 *
+	 *  This is really ugly:  scan through all components, starting from
+	 *  FIRST_ARC_COMPONENT, to find a component with the same parent as
+	 *  this component will have.  If such a component is found, and its
+	 *  'peer' value is NULL, then set it to this component's address (a).
+	 *
+	 *  TODO:  make this nicer
+	 */
+
+	n_left = machine->md.arc->n_components;
+	while (n_left > 0) {
+		/*  Load parent, child, and peer values:  */
+		uint64_t eparent, echild, epeer, tmp;
+		unsigned char buf[8];
+
+		/*  debug("[ addchild: peeraddr = 0x%016" PRIx64" ]\n",
+		    (uint64_t) peeraddr);  */
+
+		cpu->memory_rw(cpu, cpu->mem,
+		    peeraddr + 0 * machine->md.arc->wordlen, &buf[0],
+		    sizeof(eparent), MEM_READ, CACHE_NONE);
+		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+			unsigned char tmp2;
+			tmp2 = buf[0]; buf[0] = buf[7]; buf[7] = tmp2;
+			tmp2 = buf[1]; buf[1] = buf[6]; buf[6] = tmp2;
+			tmp2 = buf[2]; buf[2] = buf[5]; buf[5] = tmp2;
+			tmp2 = buf[3]; buf[3] = buf[4]; buf[4] = tmp2;
+		}
+		epeer   = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24)
+		    + ((uint64_t)buf[4] << 32) + ((uint64_t)buf[5] << 40)
+		    + ((uint64_t)buf[6] << 48) + ((uint64_t)buf[7] << 56);
+
+		cpu->memory_rw(cpu, cpu->mem, peeraddr + 1 *
+		    machine->md.arc->wordlen,
+		    &buf[0], sizeof(eparent), MEM_READ, CACHE_NONE);
+		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+			unsigned char tmp2;
+			tmp2 = buf[0]; buf[0] = buf[7]; buf[7] = tmp2;
+			tmp2 = buf[1]; buf[1] = buf[6]; buf[6] = tmp2;
+			tmp2 = buf[2]; buf[2] = buf[5]; buf[5] = tmp2;
+			tmp2 = buf[3]; buf[3] = buf[4]; buf[4] = tmp2;
+		}
+		echild  = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24)
+		    + ((uint64_t)buf[4] << 32) + ((uint64_t)buf[5] << 40)
+		    + ((uint64_t)buf[6] << 48) + ((uint64_t)buf[7] << 56);
+
+		cpu->memory_rw(cpu, cpu->mem, peeraddr + 2 *
+		    machine->md.arc->wordlen,
+		    &buf[0], sizeof(eparent), MEM_READ, CACHE_NONE);
+		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+			unsigned char tmp2;
+			tmp2 = buf[0]; buf[0] = buf[7]; buf[7] = tmp2;
+			tmp2 = buf[1]; buf[1] = buf[6]; buf[6] = tmp2;
+			tmp2 = buf[2]; buf[2] = buf[5]; buf[5] = tmp2;
+			tmp2 = buf[3]; buf[3] = buf[4]; buf[4] = tmp2;
+		}
+		eparent = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24)
+		    + ((uint64_t)buf[4] << 32) + ((uint64_t)buf[5] << 40)
+		    + ((uint64_t)buf[6] << 48) + ((uint64_t)buf[7] << 56);
+
+		/*  debug("  epeer=%" PRIx64" echild=%" PRIx64" eparent=%" PRIx64
+		    "\n", (uint64_t) epeer, (uint64_t) echild,
+		    (uint64_t) eparent);  */
+
+		if (eparent == parent && epeer == 0) {
+			epeer = a;
+			store_64bit_word(cpu, peeraddr + 0 *
+			    machine->md.arc->wordlen, epeer);
+			/*  debug("[ addchild: adding 0x%016" PRIx64" as peer "
+			    "to 0x%016" PRIx64" ]\n", (uint64_t) a,
+			    (uint64_t) peeraddr);  */
+		}
+		if (peeraddr == parent && echild == 0) {
+			echild = a;
+			store_64bit_word(cpu, peeraddr + 1 *
+			    machine->md.arc->wordlen, echild);
+			/*  debug("[ addchild: adding 0x%016" PRIx64" as child "
+			    "to 0x%016" PRIx64" ]\n", (uint64_t) a,
+			    (uint64_t) peeraddr);  */
+		}
+
+		/*  Go to the next component:  */
+		cpu->memory_rw(cpu, cpu->mem, peeraddr + 0x34,
+		    &buf[0], sizeof(uint32_t), MEM_READ, CACHE_NONE);
+		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+			unsigned char tmp2;
+			tmp2 = buf[0]; buf[0] = buf[3]; buf[3] = tmp2;
+			tmp2 = buf[1]; buf[1] = buf[2]; buf[2] = tmp2;
+		}
+		tmp = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
+
+		tmp &= 0xfffff;
+
+		peeraddr += 0x50;
+		peeraddr += tmp + 1;
+		peeraddr = ((peeraddr - 1) | 3) + 1;
+
+		n_left --;
+	}
+
+	store_64bit_word(cpu, a + 0x00, peer);
+	store_64bit_word(cpu, a + 0x08, child);
+	store_64bit_word(cpu, a + 0x10, parent);
+	store_32bit_word(cpu, a+  0x18, host_tmp_component->Class);
+	store_32bit_word(cpu, a+  0x1c, host_tmp_component->Type);
+	store_32bit_word(cpu, a+  0x20, host_tmp_component->Flags);
+	store_32bit_word(cpu, a+  0x24, host_tmp_component->Version +
+	    ((uint64_t)host_tmp_component->Revision << 16));
+	store_32bit_word(cpu, a+  0x28, host_tmp_component->Key);
+	store_64bit_word(cpu, a+  0x30, host_tmp_component->AffinityMask);
+	store_64bit_word(cpu, a+  0x38, host_tmp_component->
+	    ConfigurationDataSize);
+	store_64bit_word(cpu, a+  0x40, host_tmp_component->IdentifierLength);
+	store_64bit_word(cpu, a+  0x48, host_tmp_component->Identifier);
+
+	/*  TODO: Find out how a REAL ARCS64 implementation does it.  */
+
+	machine->md.arc->next_component_address += 0x50;
+
+	if (host_tmp_component->IdentifierLength != 0) {
+		store_64bit_word(cpu, a + 0x48, a + 0x50);
+		store_string(cpu, a + 0x50, identifier);
+		if (identifier != NULL)
+			machine->md.arc->next_component_address +=
+			    strlen(identifier) + 1;
+	}
+
+	machine->md.arc->next_component_address ++;
+
+	/*  Round up to next 0x8 bytes:  */
+	machine->md.arc->next_component_address =
+	    ((machine->md.arc->next_component_address - 1) | 7) + 1;
+
+	machine->md.arc->n_components ++;
+	return a;
+}
+
+
+/*
+ *  arcbios_addchild_manual():
+ *
+ *  Used internally to set up component structures.
+ *  Parent may only be NULL for the first (system) component.
+ *
+ *  Return value is the virtual (emulated) address of the added component.
+ */
+uint64_t arcbios_addchild_manual(struct cpu *cpu,
+	uint64_t cclass, uint64_t type, uint64_t flags,
+	uint64_t version, uint64_t revision, uint64_t key,
+	uint64_t affinitymask, const char *identifier, uint64_t parent,
+	void *config_data, size_t config_len)
+{
+	struct machine *machine = cpu->machine;
+	/*  This component is only for temporary use:  */
+	struct arcbios_component component;
+	struct arcbios_component64 component64;
+
+	if (config_data != NULL) {
+		unsigned char *p = (unsigned char *) config_data;
+		size_t i;
+
+		if (machine->md.arc->n_configuration_data >= MAX_CONFIG_DATA) {
+			printf("fatal error: you need to increase "
+			    "MAX_CONFIG_DATA\n");
+			exit(1);
+		}
+
+		for (i=0; i<config_len; i++) {
+			unsigned char ch = p[i];
+			cpu->memory_rw(cpu, cpu->mem,
+			    machine->md.arc->configuration_data_next_addr + i,
+			    &ch, 1, MEM_WRITE, CACHE_NONE);
+		}
+
+		machine->md.arc->configuration_data_len[
+		    machine->md.arc->n_configuration_data] = config_len;
+		machine->md.arc->configuration_data_configdata[
+		    machine->md.arc->n_configuration_data] =
+		    machine->md.arc->configuration_data_next_addr;
+		machine->md.arc->configuration_data_next_addr += config_len;
+		machine->md.arc->configuration_data_component[
+		    machine->md.arc->n_configuration_data] =
+		    machine->md.arc->next_component_address +
+		    (cpu->machine->md.arc->arc_64bit? 0x18 : 0x0c);
+
+		/*  printf("& ADDING %i: configdata=0x%016" PRIx64" "
+		    "component=0x%016" PRIx64"\n",
+		     machine->md.arc->n_configuration_data,
+		    (uint64_t) machine->md.arc->configuration_data_configdata[
+			machine->md.arc->n_configuration_data],
+		    (uint64_t) machine->md.arc->configuration_data_component[
+			machine->md.arc->n_configuration_data]);  */
+
+		machine->md.arc->n_configuration_data ++;
+	}
+
+	if (!cpu->machine->md.arc->arc_64bit) {
+		component.Class                 = cclass;
+		component.Type                  = type;
+		component.Flags                 = flags;
+		component.Version               = version;
+		component.Revision              = revision;
+		component.Key                   = key;
+		component.AffinityMask          = affinitymask;
+		component.ConfigurationDataSize = config_len;
+		component.IdentifierLength      = 0;
+		component.Identifier            = 0;
+		if (identifier != NULL) {
+			component.IdentifierLength = strlen(identifier) + 1;
+		}
+
+		return arcbios_addchild(cpu, &component, identifier, parent);
+	} else {
+		component64.Class                 = cclass;
+		component64.Type                  = type;
+		component64.Flags                 = flags;
+		component64.Version               = version;
+		component64.Revision              = revision;
+		component64.Key                   = key;
+		component64.AffinityMask          = affinitymask;
+		component64.ConfigurationDataSize = config_len;
+		component64.IdentifierLength      = 0;
+		component64.Identifier            = 0;
+		if (identifier != NULL) {
+			component64.IdentifierLength = strlen(identifier) + 1;
+		}
+
+		return arcbios_addchild64(cpu, &component64, identifier,
+		    parent);
+	}
+}
+
+
+/*
+ *  arcbios_get_msdos_partition_size():
+ *
+ *  This function tries to parse MSDOS-style partition tables on a disk
+ *  image, and return the starting offset (counted in bytes), and the
+ *  size, of a specific partition.
+ *
+ *  NOTE: partition_nr is 1-based!
+ *
+ *  TODO: This is buggy, it doesn't really handle extended partitions.
+ *
+ *  See http://www.nondot.org/sabre/os/files/Partitions/Partitions.html
+ *  for more info.
+ */
+static void arcbios_get_msdos_partition_size(struct machine *machine,
+	int disk_id, int disk_type, int partition_nr, uint64_t *start,
+	uint64_t *size)
+{
+	int res, i, partition_type, cur_partition = 0;
+	unsigned char sector[512];
+	unsigned char buf[16];
+	uint64_t offset = 0, st;
+
+	/*  Partition 0 is the entire disk image:  */
+	*start = 0;
+	*size = diskimage_getsize(machine, disk_id, disk_type);
+	if (partition_nr == 0)
+		return;
+
+ugly_goto:
+	*start = 0; *size = 0;
+
+	/*  printf("reading MSDOS partition from offset 0x%" PRIx64"\n",
+	    (uint64_t) offset);  */
+
+	res = diskimage_access(machine, disk_id, disk_type, 0, offset,
+	    sector, sizeof(sector));
+	if (!res) {
+		fatal("[ arcbios_get_msdos_partition_size(): couldn't "
+		    "read the disk image, id %i, offset 0x%" PRIx64" ]\n",
+		    disk_id, (uint64_t) offset);
+		return;
+	}
+
+	if (sector[510] != 0x55 || sector[511] != 0xaa) {
+		fatal("[ arcbios_get_msdos_partition_size(): not an "
+		    "MSDOS partition table ]\n");
+	}
+
+#if 0
+	/*  Debug dump:  */
+	for (i=0; i<4; i++) {
+		int j;
+		printf("  partition %i: ", i+1);
+		for (j=0; j<16; j++)
+			printf(" %02x", sector[446 + i*16 + j]);
+		printf("\n");
+	}
+#endif
+
+	for (i=0; i<4; i++) {
+		memmove(buf, sector + 446 + 16*i, 16);
+
+		partition_type = buf[4];
+
+		if (partition_type == 0)
+			continue;
+
+		st = (buf[8] + (buf[9] << 8) + (buf[10] << 16) +
+		    (buf[11] << 24)) * 512;
+
+		if (start != NULL)
+			*start = st;
+		if (size != NULL)
+			*size = (buf[12] + (buf[13] << 8) + (buf[14] << 16) +
+			    (buf[15] << 24)) * 512;
+
+		/*  Extended DOS partition:  */
+		if (partition_type == 5) {
+			offset += st;
+			goto ugly_goto;
+		}
+
+		/*  Found the right partition? Then return.  */
+		cur_partition ++;
+		if (cur_partition == partition_nr)
+			return;
+	}
+
+	fatal("[ partition(%i) NOT found ]\n", partition_nr);
+}
+
+
+/*
+ *  arcbios_handle_to_disk_id_and_type():
+ */
+static int arcbios_handle_to_disk_id_and_type(struct machine *machine, int handle, int *typep)
+{
+	const char *s;
+
+	if (handle < 0 || handle >= ARC_MAX_HANDLES)
+		return -1;
+
+	s = machine->md.arc->file_handle_string[handle];
+	if (s == NULL)
+		return -1;
+
+	/*
+	 *  s is something like "scsi(0)disk(0)rdisk(0)partition(0)".
+	 *  TODO: This is really ugly and hardcoded.
+	 */
+
+	if (strncmp(s, "pci(0)", 6) == 0)
+		s += 6;
+
+	if (strncmp(s, "scsi(0)", 7) == 0) {
+		*typep = DISKIMAGE_SCSI;
+		s += 7;
+	} else {
+		return -1;
+	}
+
+	if (strncmp(s, "disk(", 5) == 0) {
+		return atoi(s + 5);
+	}
+
+	if (strncmp(s, "cdrom(", 6) == 0) {
+		return atoi(s + 6);
+	}
+
+	return -1;
+}
+
+
+/*
+ *  arcbios_handle_to_start_and_size():
+ */
+static void arcbios_handle_to_start_and_size(struct machine *machine,
+	int handle, uint64_t *start, uint64_t *size)
+{
+	const char *s = machine->md.arc->file_handle_string[handle];
+	const char *s2;
+	int disk_id, disk_type;
+
+	disk_id = arcbios_handle_to_disk_id_and_type(machine, handle, &disk_type);
+
+	if (disk_id < 0)
+		return;
+
+	// Default to "full disk":
+	*start = 0;
+	*size = diskimage_getsize(machine, disk_id, disk_type);
+
+	if (machine->machine_type == MACHINE_SGI) {
+		/*
+		 *  TODO:
+		 *
+		 *  Read the SGI volume header / disk label. e.g.:
+		 *
+		 *  partitions:
+		 *	partition 0: 592820 blocks at 4096 (type 4)
+		 *	partition 8: 4096 blocks at 0 (type 0)
+		 *	partition 10: 596916 blocks at 0 (type 6)
+		 *
+		 *  Warn about accessing partitions that are not specified
+		 *  with a size > 0.
+		 */
+		debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_WARNING, "TODO: sgi partition");
+		return;
+	}
+
+	s2 = strstr(s, "partition(");
+	if (s2 != NULL) {
+		int partition_nr = atoi(s2 + 10);
+		/*  printf("partition_nr = %i\n", partition_nr);  */
+		if (partition_nr != 0)
+			arcbios_get_msdos_partition_size(machine,
+			    disk_id, disk_type, partition_nr, start, size);
+	}
+}
+
+
+/*
+ *  arcbios_getfileinformation():
+ *
+ *  Fill in a GetFileInformation struct in emulated memory,
+ *  for a specific file handle. (This is used to get the size
+ *  and offsets of partitions on disk images.)
+ */
+static int arcbios_getfileinformation(struct cpu *cpu)
+{
+	int handle = cpu->cd.mips.gpr[MIPS_GPR_A0];
+	uint64_t addr = cpu->cd.mips.gpr[MIPS_GPR_A1];
+	uint64_t start, size;
+
+	arcbios_handle_to_start_and_size(cpu->machine, handle, &start, &size);
+
+	store_64bit_word(cpu, addr + 0, 0);
+	store_64bit_word(cpu, addr + 8, size);
+	store_64bit_word(cpu, addr + 16, 0);
+	store_32bit_word(cpu, addr + 24, 1);
+	store_32bit_word(cpu, addr + 28, 0);
+	store_32bit_word(cpu, addr + 32, 0);
+
+	/*  printf("\n!!! size=0x%x start=0x%x\n", (int)size, (int)start);  */
+
+	return ARCBIOS_ESUCCESS;
+}
+
+
+/*
+ *  arcbios_private_emul():
+ *
+ *  The "normal" vector entries are probably from the ARC standard, whereas
+ *  the "private" entries are unknown SGI specific entries. In the emulator,
+ *  these are dummy implementations, just enough to fool IRIX to continue
+ *  past these calls.
+ *
+ *  These names are guesses based on symbols on the callstack when "sash"
+ *  calls these entries, perhaps the real function is something completely
+ *  different.
+ *
+ *	0x00	ioctl (?)
+ *	0x04	get nvram table (?)
+ *	0x14	fs_register (?)
+ *	0x1c	Signal (?)
+ *	0x20	initGfxGui (?)
+ *	0x24	sgivers (get version?)
+ *	0x30	cpufreq (?)
+ */
+void arcbios_sgi_emul(struct cpu *cpu)
+{
+	int vector = cpu->pc & 0xfff;
+
+	switch (vector) {
+
+	case 0x00:
+		debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_WARNING, "SGI: ioctl? TODO");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+/*
+	case 0x04:
+		debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_WARNING, "SGI: get nvram table(): TODO");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+*/
+	case 0x14:
+		debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_WARNING, "SGI: fs_register? TODO");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+
+	case 0x1c:
+		debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_WARNING, "SGI: Signal? TODO");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+
+	case 0x20:
+		debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_WARNING, "SGI: initGfxGui? TODO");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+
+	case 0x24:
+		debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_WARNING, "SGI: sgivers? TODO");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+
+	case 0x30:
+		// This value is displayed by hinv (in sash) as "Processor: xxx MHz"
+		debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_DEBUG, "SGI: cpufreq");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 175;
+		break;
+
+	default:
+		cpu_register_dump(cpu->machine, cpu, 1, 0x1);
+		debug("a0 points to: ");
+		dump_mem_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0]);
+		debug("\n");
+		fatal("ARCBIOS: unimplemented SGI vector 0x%x\n", vector);
+		cpu->running = 0;
+	}
+}
+
+
+/*
+ *  arcbios_emul():  ARCBIOS emulation
+ *
+ *	0x0c	Halt()
+ *	0x10	PowerDown()
+ *	0x14	Restart()
+ *	0x18	Reboot()
+ *	0x1c	EnterInteractiveMode()
+ *	0x20	ReturnFromMain()
+ *	0x24	GetPeer(node)
+ *	0x28	GetChild(node)
+ *	0x2c	GetParent(node)
+ *	0x30	GetConfigurationData(config_data, node)
+ *	0x3c	GetComponent(name)
+ *	0x44	GetSystemId()
+ *	0x48	GetMemoryDescriptor(void *)
+ *	0x50	GetTime()
+ *	0x54	GetRelativeTime()
+ *	0x5c	Open(path, mode, &fileid)
+ *	0x60	Close(handle)
+ *	0x64	Read(handle, &buf, len, &actuallen)
+ *	0x6c	Write(handle, buf, len, &returnlen)
+ *	0x70	Seek(handle, &offset, len)
+ *	0x78	GetEnvironmentVariable(char *)
+ *	0x7c	SetEnvironmentVariable(char *, char *)
+ *	0x80	GetFileInformation(handle, buf)
+ *	0x88	FlushAllCaches()
+ *	0x90	GetDisplayStatus(uint32_t handle)
+ *	0x100	undocumented IRIX (?)
+ */
+int arcbios_emul(struct cpu *cpu)
+{
+	struct machine *machine = cpu->machine;
+	int vector = cpu->pc & 0xfff;
+	int i, j, handle;
+	unsigned char ch2;
+	unsigned char buf[40];
+
+	if (cpu->pc >= ARC_PRIVATE_ENTRIES &&
+	    cpu->pc < ARC_PRIVATE_ENTRIES + 100*sizeof(uint32_t)) {
+		if (machine->machine_type == MACHINE_SGI)
+			arcbios_sgi_emul(cpu);
+		else {
+			fatal("[ ARCBIOS private call for non-SGI. ]\n");
+			exit(1);
+		}
+
+		return 1;
+	}
+
+	if (machine->md.arc->arc_64bit)
+		vector /= 2;
+
+	/*  Special case for reboot by jumping to 0xbfc00000:  */
+	if (vector == 0 && (cpu->pc & 0xffffffffULL) == 0xbfc00000ULL)
+		vector = 0x18;
+
+	switch (vector) {
+	case 0x0c:		/*  Halt()  */
+	case 0x10:		/*  PowerDown()  */
+	case 0x14:		/*  Restart()  */
+	case 0x18:		/*  Reboot()  */
+	case 0x1c:		/*  EnterInteractiveMode()  */
+	case 0x20:		/*  ReturnFromMain()  */
+		switch (vector) {
+		case 0x0c:
+			debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_DEBUG, "Halt()");
+			break;
+		case 0x10:
+			debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_DEBUG, "PowerDown()");
+			break;
+		case 0x14:
+			debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_DEBUG, "Restart()");
+			break;
+		case 0x18:
+			debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_DEBUG, "Reboot()");
+			break;
+		case 0x1c:
+			debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_DEBUG, "EnterInteractiveMode()");
+			break;
+		case 0x20:
+			debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_DEBUG, "ReturnFromMain()");
+			break;
+		}
+
+		/*  Halt all CPUs.  */
+		for (i=0; i<machine->ncpus; i++) {
+			machine->cpus[i]->running = 0;
+		}
+
+		break;
+	case 0x24:		/*  GetPeer(node)  */
+		if (cpu->cd.mips.gpr[MIPS_GPR_A0] == 0) {
+			/*  NULL ptr argument: return NULL.  */
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		} else {
+			uint64_t peer;
+			cpu->memory_rw(cpu, cpu->mem,
+			    cpu->cd.mips.gpr[MIPS_GPR_A0] - 3 *
+			    machine->md.arc->wordlen, &buf[0],
+			    machine->md.arc->wordlen, MEM_READ, CACHE_NONE);
+			if (machine->md.arc->arc_64bit) {
+				if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+					unsigned char tmp; tmp = buf[0];
+					buf[0] = buf[7]; buf[7] = tmp;
+					tmp = buf[1]; buf[1] = buf[6];
+					buf[6] = tmp;
+					tmp = buf[2]; buf[2] = buf[5];
+					buf[5] = tmp;
+					tmp = buf[3]; buf[3] = buf[4];
+					buf[4] = tmp;
+				}
+				peer = (uint64_t)buf[0] + ((uint64_t)buf[1]<<8)
+				    + ((uint64_t)buf[2]<<16)
+				    + ((uint64_t)buf[3]<<24)
+				    + ((uint64_t)buf[4]<<32)
+				    + ((uint64_t)buf[5]<<40)
+				    + ((uint64_t)buf[6]<<48)
+				    + ((uint64_t)buf[7]<<56);
+			} else {
+				if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+					unsigned char tmp; tmp = buf[0];
+					buf[0] = buf[3]; buf[3] = tmp;
+					tmp = buf[1]; buf[1] = buf[2];
+					buf[2] = tmp;
+				}
+				peer = buf[0] + (buf[1]<<8) + (buf[2]<<16)
+				    + (buf[3]<<24);
+			}
+
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = peer?
+			    (peer + 3 * machine->md.arc->wordlen) : 0;
+			if (!machine->md.arc->arc_64bit)
+				cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)
+				    (int32_t) cpu->cd.mips.gpr[MIPS_GPR_V0];
+		}
+		debug("[ ARCBIOS GetPeer(node 0x%016" PRIx64"): 0x%016" PRIx64
+		    " ]\n", (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
+		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_V0]);
+		break;
+	case 0x28:		/*  GetChild(node)  */
+		/*  0 for the root, non-0 for children:  */
+		if (cpu->cd.mips.gpr[MIPS_GPR_A0] == 0)
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = FIRST_ARC_COMPONENT
+			    + machine->md.arc->wordlen * 3;
+		else {
+			uint64_t child = 0;
+			cpu->memory_rw(cpu, cpu->mem,
+			    cpu->cd.mips.gpr[MIPS_GPR_A0] - 2 *
+			    machine->md.arc->wordlen, &buf[0], machine->
+			    md.arc->wordlen, MEM_READ, CACHE_NONE);
+			if (machine->md.arc->arc_64bit) {
+				if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+					unsigned char tmp; tmp = buf[0];
+					buf[0] = buf[7]; buf[7] = tmp;
+					tmp = buf[1]; buf[1] = buf[6];
+					buf[6] = tmp;
+					tmp = buf[2]; buf[2] = buf[5];
+					buf[5] = tmp;
+					tmp = buf[3]; buf[3] = buf[4];
+					buf[4] = tmp;
+				}
+				child = (uint64_t)buf[0] +
+				    ((uint64_t)buf[1]<<8) +
+				    ((uint64_t)buf[2]<<16) +
+				    ((uint64_t)buf[3]<<24) +
+				    ((uint64_t)buf[4]<<32) +
+				    ((uint64_t)buf[5]<<40) +
+				    ((uint64_t)buf[6]<<48) +
+				    ((uint64_t)buf[7]<<56);
+			} else {
+				if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+					unsigned char tmp; tmp = buf[0];
+					buf[0] = buf[3]; buf[3] = tmp;
+					tmp = buf[1]; buf[1] = buf[2];
+					buf[2] = tmp;
+				}
+				child = buf[0] + (buf[1]<<8) + (buf[2]<<16) +
+				    (buf[3]<<24);
+			}
+
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = child?
+			    (child + 3 * machine->md.arc->wordlen) : 0;
+			if (!machine->md.arc->arc_64bit)
+				cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)
+				    (int32_t)cpu->cd.mips.gpr[MIPS_GPR_V0];
+		}
+		debug("[ ARCBIOS GetChild(node 0x%016" PRIx64"): 0x%016"
+		    PRIx64" ]\n", (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
+		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_V0]);
+		break;
+	case 0x2c:		/*  GetParent(node)  */
+		{
+			uint64_t parent;
+
+			cpu->memory_rw(cpu, cpu->mem,
+			    cpu->cd.mips.gpr[MIPS_GPR_A0] - 1 * machine->
+			    md.arc->wordlen, &buf[0], machine->md.arc->wordlen,
+			    MEM_READ, CACHE_NONE);
+
+			if (machine->md.arc->arc_64bit) {
+				if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+					unsigned char tmp; tmp = buf[0];
+					buf[0] = buf[7]; buf[7] = tmp;
+					tmp = buf[1]; buf[1] = buf[6];
+					buf[6] = tmp;
+					tmp = buf[2]; buf[2] = buf[5];
+					buf[5] = tmp;
+					tmp = buf[3]; buf[3] = buf[4];
+					buf[4] = tmp;
+				}
+				parent = (uint64_t)buf[0] +
+				    ((uint64_t)buf[1]<<8) +
+				    ((uint64_t)buf[2]<<16) +
+				    ((uint64_t)buf[3]<<24) +
+				    ((uint64_t)buf[4]<<32) +
+				    ((uint64_t)buf[5]<<40) +
+				    ((uint64_t)buf[6]<<48) +
+				    ((uint64_t)buf[7]<<56);
+			} else {
+				if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+					unsigned char tmp; tmp = buf[0];
+					buf[0] = buf[3]; buf[3] = tmp;
+					tmp = buf[1]; buf[1] = buf[2];
+					buf[2] = tmp;
+				}
+				parent = buf[0] + (buf[1]<<8) +
+				    (buf[2]<<16) + (buf[3]<<24);
+			}
+
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = parent?
+			    (parent + 3 * machine->md.arc->wordlen) : 0;
+			if (!machine->md.arc->arc_64bit)
+				cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)
+				    (int32_t) cpu->cd.mips.gpr[MIPS_GPR_V0];
+		}
+		debug("[ ARCBIOS GetParent(node 0x%016" PRIx64"): 0x%016"
+		    PRIx64" ]\n", (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
+		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_V0]);
+		break;
+	case 0x30:  /*  GetConfigurationData(void *configdata, void *node)  */
+		/*  fatal("[ ARCBIOS GetConfigurationData(0x%016" PRIx64","
+		    "0x%016" PRIx64") ]\n",
+		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
+		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1]);  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EINVAL;
+		for (i=0; i<machine->md.arc->n_configuration_data; i++) {
+			/*  fatal("configuration_data_component[%i] = "
+			    "0x%016" PRIx64"\n", i, (uint64_t) machine->
+			    md.arc->configuration_data_component[i]);  */
+			if (cpu->cd.mips.gpr[MIPS_GPR_A1] ==
+			    machine->md.arc->configuration_data_component[i]) {
+				cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+				for (j=0; j<machine->
+				    md.arc->configuration_data_len[i]; j++) {
+					unsigned char ch;
+					cpu->memory_rw(cpu, cpu->mem,
+					    machine->md.arc->
+					    configuration_data_configdata[i] +
+					    j, &ch, 1, MEM_READ, CACHE_NONE);
+					cpu->memory_rw(cpu, cpu->mem,
+					    cpu->cd.mips.gpr[MIPS_GPR_A0] + j,
+					    &ch, 1, MEM_WRITE, CACHE_NONE);
+				}
+				break;
+			}
+		}
+		break;
+	case 0x3c:		/*  GetComponent(char *name)  */
+		debug("[ ARCBIOS GetComponent(\"");
+		dump_mem_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0]);
+		debug("\") ]\n");
+
+		if (cpu->cd.mips.gpr[MIPS_GPR_A0] == 0) {
+			fatal("[ ARCBIOS GetComponent: NULL ptr ]\n");
+		} else {
+			unsigned char buf2[500];
+			int match_index = -1;
+			int match_len = 0;
+
+			memset(buf2, 0, sizeof(buf2));
+			for (i=0; i<(ssize_t)sizeof(buf2); i++) {
+				cpu->memory_rw(cpu, cpu->mem,
+				    cpu->cd.mips.gpr[MIPS_GPR_A0] + i,
+				    &buf2[i], 1, MEM_READ, CACHE_NONE);
+				if (buf2[i] == '\0')
+					i = sizeof(buf);
+			}
+			buf2[sizeof(buf2) - 1] = '\0';
+
+			/*  "scsi(0)disk(0)rdisk(0)partition(0)" and such.  */
+			/*  printf("GetComponent(\"%s\")\n", buf2);  */
+
+			/*  Default to NULL return value.  */
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+
+			/*  Scan the string to component table:  */
+			for (i=0; i<machine->md.arc->n_string_to_components;
+			    i++) {
+				int m = 0;
+				while (buf2[m] && machine->md.arc->
+				    string_to_component[i][m] &&
+				    machine->md.arc->string_to_component[i][m]
+				    == buf2[m])
+					m++;
+				if (m > match_len) {
+					match_len = m;
+					match_index = i;
+				}
+			}
+
+			if (match_index >= 0) {
+				/*  printf("Longest match: '%s'\n",
+				    machine->md.arc->string_to_component[
+				    match_index]);  */
+				cpu->cd.mips.gpr[MIPS_GPR_V0] =
+				    machine->md.arc->string_to_component_value[
+				    match_index];
+			}
+		}
+		break;
+	case 0x44:		/*  GetSystemId()  */
+		debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_DEBUG, "GetSystemId()");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = SGI_SYSID_ADDR;
+		break;
+	case 0x48:		/*  void *GetMemoryDescriptor(void *ptr)  */
+		debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_DEBUG, "GetMemoryDescriptor(0x%08x)",
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
+
+		/*  If a0=NULL, then return the first descriptor:  */
+		if ((uint32_t)cpu->cd.mips.gpr[MIPS_GPR_A0] == 0)
+			cpu->cd.mips.gpr[MIPS_GPR_V0] =
+			    machine->md.arc->memdescriptor_base;
+		else {
+			int s = machine->md.arc->arc_64bit?
+			    sizeof(struct arcbios_mem64)
+			    : sizeof(struct arcbios_mem);
+			int nr = cpu->cd.mips.gpr[MIPS_GPR_A0] -
+			    machine->md.arc->memdescriptor_base;
+			nr /= s;
+			nr ++;
+			cpu->cd.mips.gpr[MIPS_GPR_V0] =
+			    machine->md.arc->memdescriptor_base + s * nr;
+			if (nr >= machine->md.arc->n_memdescriptors)
+				cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		}
+		break;
+	case 0x50:		/*  GetTime()  */
+		debug("[ ARCBIOS GetTime() ]\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0xffffffff80001000ULL;
+		/*  TODO!  */
+		break;
+	case 0x54:		/*  GetRelativeTime()  */
+		debug("[ ARCBIOS GetRelativeTime() ]\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)(int32_t)time(NULL);
+		break;
+	case 0x5c:  /*  Open(char *path, uint32_t mode, uint32_t *fileID)  */
+		debug("[ ARCBIOS Open(\"");
+		dump_mem_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0]);
+		debug("\",0x%x,0x%x)", (int)cpu->cd.mips.gpr[MIPS_GPR_A0],
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A1],
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A2]);
+
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_ENOENT;
+
+		handle = 3;
+		/*  TODO: Starting at 0 would require some updates...  */
+		while (machine->md.arc->file_handle_in_use[handle]) {
+			handle ++;
+			if (handle >= ARC_MAX_HANDLES) {
+				cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EMFILE;
+				break;
+			}
+		}
+
+		if (handle >= ARC_MAX_HANDLES) {
+			fatal("[ ARCBIOS Open: out of file handles ]\n");
+		} else if (cpu->cd.mips.gpr[MIPS_GPR_A0] == 0) {
+			fatal("[ ARCBIOS Open: NULL ptr ]\n");
+		} else {
+			/*
+			 *  TODO: This is hardcoded to successfully open
+			 *  anything. It is used by the Windows NT SETUPLDR
+			 *  program to load stuff from the boot partition.
+			 */
+			unsigned char *buf2;
+			CHECK_ALLOCATION(buf2 = (unsigned char *) malloc(MAX_OPEN_STRINGLEN));
+			memset(buf2, 0, MAX_OPEN_STRINGLEN);
+			for (i=0; i<MAX_OPEN_STRINGLEN; i++) {
+				cpu->memory_rw(cpu, cpu->mem,
+				    cpu->cd.mips.gpr[MIPS_GPR_A0] + i,
+				    &buf2[i], 1, MEM_READ, CACHE_NONE);
+				if (buf2[i] == '\0')
+					i = MAX_OPEN_STRINGLEN;
+			}
+			buf2[MAX_OPEN_STRINGLEN - 1] = '\0';
+			machine->md.arc->file_handle_string[handle] =
+			    (char *)buf2;
+			machine->md.arc->current_seek_offset[handle] = 0;
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_ESUCCESS;
+		}
+
+		if (cpu->cd.mips.gpr[MIPS_GPR_V0] == ARCBIOS_ESUCCESS) {
+			debug(" = handle %i ]\n", (int)handle);
+			store_32bit_word(cpu, cpu->cd.mips.gpr[MIPS_GPR_A2],
+			    handle);
+			machine->md.arc->file_handle_in_use[handle] = 1;
+		} else
+			debug(" = ERROR %i ]\n",
+			    (int)cpu->cd.mips.gpr[MIPS_GPR_V0]);
+		break;
+	case 0x60:		/*  Close(uint32_t handle)  */
+		debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_DEBUG, "Close(%i)",
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
+		if (!machine->md.arc->file_handle_in_use[cpu->cd.mips.gpr[
+		    MIPS_GPR_A0]]) {
+			fatal("ARCBIOS Close(%i): bad handle\n",
+			    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EBADF;
+		} else {
+			machine->md.arc->file_handle_in_use[
+			    cpu->cd.mips.gpr[MIPS_GPR_A0]] = 0;
+			// TODO: Yes, this is a memory leak. But it will be
+			// scrapped in favor of real code after the rewrite (I
+			// hope).
+			//if (machine->md.arc->file_handle_string[
+			//    cpu->cd.mips.gpr[MIPS_GPR_A0]] != NULL)
+			//	free(machine->md.arc->file_handle_string[
+			//	    cpu->cd.mips.gpr[MIPS_GPR_A0]]);
+			machine->md.arc->file_handle_string[cpu->cd.mips.
+			    gpr[MIPS_GPR_A0]] = NULL;
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_ESUCCESS;
+		}
+		break;
+	case 0x64:  /*  Read(handle, void *buf, length, uint32_t *count)  */
+		if (cpu->cd.mips.gpr[MIPS_GPR_A0] == ARCBIOS_STDIN) {
+			int j2, nread = 0, a2;
+
+			/*
+			 *  Before going into the loop, make sure stdout
+			 *  is flushed.  If we're using an X11 VGA console,
+			 *  then it needs to be flushed as well.
+			 */
+			fflush(stdin);
+			fflush(stdout);
+			/*  NOTE/TODO: This gives a tick to _everything_  */
+			for (j2=0; j2<machine->tick_functions.n_entries; j2++)
+				machine->tick_functions.f[j2](cpu,
+				    machine->tick_functions.extra[j2]);
+
+			a2 = cpu->cd.mips.gpr[MIPS_GPR_A2];
+			for (j2=0; j2<a2; j2++) {
+				int x;
+				unsigned char ch;
+
+				/*  Read from STDIN is blocking (at least
+				    that seems to be how NetBSD's arcdiag
+				    wants it)  */
+				x = console_readchar(
+				    machine->main_console_handle);
+				if (x < 0)
+					return 0;
+
+				/*
+				 *  ESC + '[' should be transformed into 0x9b:
+				 *
+				 *  NOTE/TODO: This makes the behaviour of just
+				 *  pressing ESC a bit harder to define.
+				 */
+				if (x == 27) {
+					x = console_readchar(cpu->
+					    machine->main_console_handle);
+					if (x == '[' || x == 'O')
+						x = 0x9b;
+				}
+
+				ch = x;
+				nread ++;
+				cpu->memory_rw(cpu, cpu->mem,
+				    cpu->cd.mips.gpr[MIPS_GPR_A1] + j2,
+				    &ch, 1, MEM_WRITE, CACHE_NONE);
+
+				/*  NOTE: Only one char, from STDIN:  */
+				j2 = cpu->cd.mips.gpr[MIPS_GPR_A2];  /*  :-)  */
+			}
+			
+			store_32bit_word(cpu, cpu->cd.mips.gpr[MIPS_GPR_A3],
+			    nread);
+			/*  TODO: not EAGAIN?  */
+			cpu->cd.mips.gpr[MIPS_GPR_V0] =
+			    nread? ARCBIOS_ESUCCESS: ARCBIOS_EAGAIN;
+		} else {
+			int handleTmp = cpu->cd.mips.gpr[MIPS_GPR_A0];
+			int disk_type = 0;
+			int disk_id = arcbios_handle_to_disk_id_and_type(
+			    machine, handleTmp, &disk_type);
+			uint64_t partition_offset = 0;
+			int res;
+			uint64_t size;		/*  dummy  */
+			unsigned char *tmp_buf;
+
+			arcbios_handle_to_start_and_size(machine, handleTmp,
+			    &partition_offset, &size);
+
+			debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_DEBUG, "Read(%i,0x%08x,0x%08x,0x%08x)",
+			    (int)cpu->cd.mips.gpr[MIPS_GPR_A0],
+			    (int)cpu->cd.mips.gpr[MIPS_GPR_A1],
+			    (int)cpu->cd.mips.gpr[MIPS_GPR_A2],
+			    (int)cpu->cd.mips.gpr[MIPS_GPR_A3]);
+
+			CHECK_ALLOCATION(tmp_buf = (unsigned char *)
+			    malloc(cpu->cd.mips.gpr[MIPS_GPR_A2]));
+
+			res = diskimage_access(machine, disk_id, disk_type,
+			    0, partition_offset + machine->md.arc->
+			    current_seek_offset[handleTmp], tmp_buf,
+			    cpu->cd.mips.gpr[MIPS_GPR_A2]);
+
+			/*  If the transfer was successful, transfer the
+			    data to emulated memory:  */
+			if (res) {
+				uint64_t dst = cpu->cd.mips.gpr[MIPS_GPR_A1];
+				store_buf(cpu, dst, (char *)tmp_buf,
+				    cpu->cd.mips.gpr[MIPS_GPR_A2]);
+				store_32bit_word(cpu,
+				    cpu->cd.mips.gpr[MIPS_GPR_A3],
+				    cpu->cd.mips.gpr[MIPS_GPR_A2]);
+				machine->md.arc->current_seek_offset[handleTmp] +=
+				    cpu->cd.mips.gpr[MIPS_GPR_A2];
+				cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+			} else {
+				debug("[ ... res = %i ]\n", res);
+				cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EIO;
+			}
+			free(tmp_buf);
+		}
+		break;
+	case 0x68:		/*  GetReadStatus(handle)  */
+		/*
+		 *  According to arcbios_tty_getchar() in NetBSD's
+		 *  dev/arcbios/arcbios_tty.c, GetReadStatus should
+		 *  return 0 if there is something available.
+		 *
+		 *  TODO: Error codes are things like ARCBIOS_EAGAIN.
+		 */
+		if (cpu->cd.mips.gpr[MIPS_GPR_A0] == ARCBIOS_STDIN) {
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = console_charavail(
+			    machine->main_console_handle)? 0 : 1;
+		} else {
+			fatal("[ ARCBIOS GetReadStatus(%i) from "
+			    "something other than STDIN: TODO ]\n",
+			    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
+			/*  TODO  */
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = 1;
+		}
+		break;
+	case 0x6c:		/*  Write(handle, buf, len, &returnlen)  */
+		if (cpu->cd.mips.gpr[MIPS_GPR_A0] != ARCBIOS_STDOUT) {
+			/*
+			 *  TODO: this is just a test
+			 */
+			int handleTmp = cpu->cd.mips.gpr[MIPS_GPR_A0];
+			int disk_type = 0;
+			int disk_id = arcbios_handle_to_disk_id_and_type(
+			    machine, handleTmp, &disk_type);
+			uint64_t partition_offset = 0;
+			int res, tmpi;
+			uint64_t size;		/*  dummy  */
+			unsigned char *tmp_buf;
+
+			arcbios_handle_to_start_and_size(machine,
+			    handleTmp, &partition_offset, &size);
+
+			debug("[ ARCBIOS Write(%i,0x%08" PRIx64",%i,0x%08"
+			    PRIx64") ]\n", (int) cpu->cd.mips.gpr[MIPS_GPR_A0],
+			    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1],
+			    (int) cpu->cd.mips.gpr[MIPS_GPR_A2],
+			    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A3]);
+
+			CHECK_ALLOCATION(tmp_buf = (unsigned char *)
+			    malloc(cpu->cd.mips.gpr[MIPS_GPR_A2]));
+
+			for (tmpi=0; tmpi<(int32_t)cpu->cd.mips.gpr[MIPS_GPR_A2]; tmpi++)
+				cpu->memory_rw(cpu, cpu->mem,
+				    cpu->cd.mips.gpr[MIPS_GPR_A1] + tmpi,
+				    &tmp_buf[tmpi], sizeof(char), MEM_READ,
+				    CACHE_NONE);
+
+			res = diskimage_access(machine, disk_id, disk_type,
+			    1, partition_offset + machine->md.arc->
+			    current_seek_offset[handleTmp], tmp_buf,
+			    cpu->cd.mips.gpr[MIPS_GPR_A2]);
+
+			if (res) {
+				store_32bit_word(cpu,
+				    cpu->cd.mips.gpr[MIPS_GPR_A3],
+				    cpu->cd.mips.gpr[MIPS_GPR_A2]);
+				machine->md.arc->current_seek_offset[handleTmp] +=
+				    cpu->cd.mips.gpr[MIPS_GPR_A2];
+				cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+			} else
+				cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EIO;
+			free(tmp_buf);
+		} else {
+			for (i=0; i<(int32_t)cpu->cd.mips.gpr[MIPS_GPR_A2];
+			    i++) {
+				unsigned char ch = '\0';
+				cpu->memory_rw(cpu, cpu->mem,
+				    cpu->cd.mips.gpr[MIPS_GPR_A1] + i,
+				    &ch, sizeof(ch), MEM_READ, CACHE_NONE);
+
+				arcbios_putchar(cpu, ch);
+			}
+		}
+		store_32bit_word(cpu, cpu->cd.mips.gpr[MIPS_GPR_A3],
+		    cpu->cd.mips.gpr[MIPS_GPR_A2]);
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;	/*  Success.  */
+		break;
+	case 0x70:	/*  Seek(uint32_t handle, int64_t *ofs,
+				 uint32_t whence): uint32_t  */
+		debug("[ ARCBIOS Seek(%i,0x%08" PRIx64",%i): ",
+		    (int) cpu->cd.mips.gpr[MIPS_GPR_A0],
+		    (uint64_t)cpu->cd.mips.gpr[MIPS_GPR_A1],
+		    (int) cpu->cd.mips.gpr[MIPS_GPR_A2]);
+
+		if (cpu->cd.mips.gpr[MIPS_GPR_A2] != 0) {
+			fatal("[ ARCBIOS Seek(%i,0x%08" PRIx64",%i): "
+			    "UNIMPLEMENTED whence=%i ]\n",
+			    (int) cpu->cd.mips.gpr[MIPS_GPR_A0],
+			    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1],
+			    (int) cpu->cd.mips.gpr[MIPS_GPR_A2],
+			    (int) cpu->cd.mips.gpr[MIPS_GPR_A2]);
+		}
+
+		{
+			unsigned char bufTmp[8];
+			uint64_t ofs;
+			cpu->memory_rw(cpu, cpu->mem,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1], &bufTmp[0],
+			    sizeof(bufTmp), MEM_READ, CACHE_NONE);
+			if (cpu->byte_order == EMUL_BIG_ENDIAN) {
+				unsigned char tmp;
+				tmp = bufTmp[0]; bufTmp[0] = bufTmp[7]; bufTmp[7] = tmp;
+				tmp = bufTmp[1]; bufTmp[1] = bufTmp[6]; bufTmp[6] = tmp;
+				tmp = bufTmp[2]; bufTmp[2] = bufTmp[5]; bufTmp[5] = tmp;
+				tmp = bufTmp[3]; bufTmp[3] = bufTmp[4]; bufTmp[4] = tmp;
+			}
+			ofs = bufTmp[0] + (bufTmp[1] << 8) + (bufTmp[2] << 16) +
+			    (bufTmp[3] << 24) + ((uint64_t)bufTmp[4] << 32) +
+			    ((uint64_t)bufTmp[5] << 40) + ((uint64_t)bufTmp[6] << 48)
+			    + ((uint64_t)bufTmp[7] << 56);
+			    
+			machine->md.arc->current_seek_offset[
+			    cpu->cd.mips.gpr[MIPS_GPR_A0]] = ofs;
+			debug("%016" PRIx64" ]\n", (uint64_t) ofs);
+		}
+
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;	/*  Success.  */
+
+		break;
+	case 0x78:		/*  GetEnvironmentVariable(char *)  */
+		/*  Find the environment variable given by a0:  */
+		for (i=0; i<(ssize_t)sizeof(buf); i++)
+			cpu->memory_rw(cpu, cpu->mem,
+			    cpu->cd.mips.gpr[MIPS_GPR_A0] + i,
+			    &buf[i], sizeof(char), MEM_READ, CACHE_NONE);
+		buf[sizeof(buf)-1] = '\0';
+		debugmsg(SUBSYS_PROMEMUL, "arcbios", VERBOSITY_DEBUG, "GetEnvironmentVariable(\"%s\")", buf);
+		for (i=0; i<0x1000; i++) {
+			/*  Matching string at offset i?  */
+			int nmatches = 0;
+			uint64_t envptr = machine->machine_type == MACHINE_SGI ? ARC_ENV_STRINGS_SGI : ARC_ENV_STRINGS;
+			for (j=0; j<(ssize_t)strlen((char *)buf); j++) {
+				cpu->memory_rw(cpu, cpu->mem,
+				    (uint64_t)(envptr + i + j),
+				    &ch2, sizeof(char), MEM_READ, CACHE_NONE);
+				if (ch2 == buf[j])
+					nmatches++;
+			}
+			cpu->memory_rw(cpu, cpu->mem,
+			    (uint64_t)(envptr + i +
+			    strlen((char *)buf)), &ch2, sizeof(char),
+			    MEM_READ, CACHE_NONE);
+			if (nmatches == (int)strlen((char *)buf) && ch2=='=') {
+				cpu->cd.mips.gpr[MIPS_GPR_V0] =
+				    envptr + i +
+				    strlen((char *)buf) + 1;
+				return 1;
+			}
+		}
+		/*  Return NULL if string wasn't found.  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0x7c:		/*  SetEnvironmentVariable(char *, char *)  */
+		debug("[ ARCBIOS SetEnvironmentVariable(\"");
+		dump_mem_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0]);
+		debug("\",\"");
+		dump_mem_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A1]);
+		debug("\") ]\n");
+		/*  TODO: This is a dummy.  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_ESUCCESS;
+		break;
+	case 0x80:		/*  GetFileInformation()  */
+		debug("[ ARCBIOS GetFileInformation(%i,0x%x): ",
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0],
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A1]);
+
+		if (cpu->cd.mips.gpr[MIPS_GPR_A0] >= ARC_MAX_HANDLES) {
+			debug("invalid file handle ]\n");
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EINVAL;
+		} else if (!machine->md.arc->file_handle_in_use[cpu->cd.
+		    mips.gpr[MIPS_GPR_A0]]) {
+			debug("file handle not in use! ]\n");
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EBADF;
+		} else {
+			debug("'%s' ]\n", machine->md.arc->file_handle_string[
+			    cpu->cd.mips.gpr[MIPS_GPR_A0]]);
+			cpu->cd.mips.gpr[MIPS_GPR_V0] =
+			    arcbios_getfileinformation(cpu);
+		}
+		break;
+	case 0x88:		/*  FlushAllCaches()  */
+		debug("[ ARCBIOS FlushAllCaches(): TODO ]\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0x90:		/*  void *GetDisplayStatus(handle)  */
+		debug("[ ARCBIOS GetDisplayStatus(%i) ]\n",
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
+		/*  TODO:  handle different values of 'handle'?  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = ARC_DSPSTAT_ADDR;
+		break;
+	case 0x100:
+		/*
+		 *  Undocumented, used by IRIX.
+		 */
+		debug("[ ARCBIOS: IRIX 0x100 (?) ]\n");
+		/*  TODO  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0x888:
+		/*
+		 *  Magical crash if there is no exception handling code.
+		 */
+		fatal("EXCEPTION, but no exception handler installed yet.\n");
+		quiet_mode = 0;
+		cpu_register_dump(machine, cpu, 1, 0x1);
+		cpu->running = 0;
+		break;
+	default:
+		quiet_mode = 0;
+		cpu_register_dump(machine, cpu, 1, 0x1);
+		debug("a0 points to: ");
+		dump_mem_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0]);
+		debug("\n");
+		fatal("ARCBIOS: unimplemented vector 0x%x\n", vector);
+		cpu->running = 0;
+	}
+
+	return 1;
+}
+
+
+/*
+ *  arcbios_set_default_exception_handler():
+ */
+void arcbios_set_default_exception_handler(struct cpu *cpu)
+{
+	/*
+	 *  The default exception handlers simply jump to 0xbfc88888,
+	 *  which is then taken care of in arcbios_emul() above.
+	 *
+	 *  3c1abfc8        lui     k0,0xbfc8
+	 *  375a8888        ori     k0,k0,0x8888
+	 *  03400008        jr      k0
+	 *  00000000        nop
+	 */
+	store_32bit_word(cpu, 0xffffffff80000000ULL, 0x3c1abfc8);
+	store_32bit_word(cpu, 0xffffffff80000004ULL, 0x375a8888);
+	store_32bit_word(cpu, 0xffffffff80000008ULL, 0x03400008);
+	store_32bit_word(cpu, 0xffffffff8000000cULL, 0x00000000);
+
+	store_32bit_word(cpu, 0xffffffff80000080ULL, 0x3c1abfc8);
+	store_32bit_word(cpu, 0xffffffff80000084ULL, 0x375a8888);
+	store_32bit_word(cpu, 0xffffffff80000088ULL, 0x03400008);
+	store_32bit_word(cpu, 0xffffffff8000008cULL, 0x00000000);
+
+	store_32bit_word(cpu, 0xffffffff80000180ULL, 0x3c1abfc8);
+	store_32bit_word(cpu, 0xffffffff80000184ULL, 0x375a8888);
+	store_32bit_word(cpu, 0xffffffff80000188ULL, 0x03400008);
+	store_32bit_word(cpu, 0xffffffff8000018cULL, 0x00000000);
+}
+
+
+/*
+ *  arcbios_add_other_components():
+ *
+ *  TODO: How should this be synched with the hardware devices
+ *  added in machine.c?
+ */
+static void arcbios_add_other_components(struct machine *machine,
+	uint64_t system)
+{
+	struct cpu *cpu = machine->cpus[0];
+
+	if (machine->machine_type == MACHINE_ARC &&
+	    (machine->machine_subtype == MACHINE_ARC_JAZZ_PICA
+	    || machine->machine_subtype == MACHINE_ARC_JAZZ_MAGNUM)) {
+		uint64_t jazzbus, ali_s3, vxl;
+		uint64_t diskcontroller, kbdctl, ptrctl, scsi;
+		/*  uint64_t serial1, serial2;  */
+
+		jazzbus = arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_AdapterClass,
+		    COMPONENT_TYPE_MultiFunctionAdapter,
+		    0, 1, 2, 0, 0xffffffff, "Jazz-Internal Bus",
+		    system, NULL, 0);
+
+		/*
+		 *  DisplayController, needed by NetBSD:
+		 *  TODO: NetBSD still doesn't use it :(
+		 */
+		switch (machine->machine_subtype) {
+		case MACHINE_ARC_JAZZ_PICA:
+			/*  Default TLB entries on PICA-61:  */
+
+			/* 7: 256K, asid: 0x0, v: 0xe1000000,
+			   p0: 0xfff00000(2.VG), p1: 0x0(0..G)  */
+			mips_coproc_tlb_set_entry(cpu, 7, 262144,
+			    0xffffffffe1000000ULL,
+			    0x0fff00000ULL, 0, 1, 0, 0, 0, 1, 0, 2, 0);
+
+			/* 8: 64K, asid: 0x0, v: 0xe0000000,
+			   p0: 0x80000000(2DVG), p1: 0x0(0..G) */
+			mips_coproc_tlb_set_entry(cpu, 8, 65536,
+			    0xffffffffe0000000ULL,
+			    0x080000000ULL, 0, 1, 0, 1, 0, 1, 0, 2, 0);
+
+			/* 9: 64K, asid: 0x0, v: 0xe00e0000,
+			   p0: 0x800e0000(2DVG), p1: 0x800f0000(2DVG) */
+			mips_coproc_tlb_set_entry(cpu, 9, 65536,
+			    (uint64_t)0xffffffffe00e0000ULL,
+			    (uint64_t)0x0800e0000ULL,
+			    (uint64_t)0x0800f0000ULL, 1, 1, 1, 1, 1, 0, 2, 2);
+
+			/* 10: 4K, asid: 0x0, v: 0xe0100000,
+			   p0: 0xf0000000(2DVG), p1: 0x0(0..G) */
+			mips_coproc_tlb_set_entry(cpu, 10, 4096,
+			    (uint64_t)0xffffffffe0100000ULL,
+			    (uint64_t)0x0f0000000ULL, 0,1, 0, 1, 0, 1, 0, 2, 0);
+
+			/* 11: 1M, asid: 0x0, v: 0xe0200000,
+			   p0: 0x60000000(2DVG), p1: 0x60100000(2DVG) */
+			mips_coproc_tlb_set_entry(cpu, 11, 1048576,
+			    0xffffffffe0200000ULL,
+			    0x060000000ULL, 0x060100000ULL,1,1,1,1,1, 0, 2, 2);
+
+			/* 12: 1M, asid: 0x0, v: 0xe0400000,
+			   p0: 0x60200000(2DVG), p1: 0x60300000(2DVG) */
+			mips_coproc_tlb_set_entry(cpu, 12, 1048576,
+			    0xffffffffe0400000ULL, 0x060200000ULL,
+			    0x060300000ULL, 1, 1, 1, 1, 1, 0, 2, 2);
+
+			/* 13: 4M, asid: 0x0, v: 0xe0800000,
+			   p0: 0x40000000(2DVG), p1: 0x40400000(2DVG) */
+			mips_coproc_tlb_set_entry(cpu, 13, 1048576*4,
+			    0xffffffffe0800000ULL, 0x040000000ULL,
+			    0x040400000ULL, 1, 1, 1, 1, 1, 0, 2, 2);
+
+			/* 14: 16M, asid: 0x0, v: 0xe2000000,
+			   p0: 0x90000000(2DVG), p1: 0x91000000(2DVG) */
+			mips_coproc_tlb_set_entry(cpu, 14, 1048576*16,
+			    0xffffffffe2000000ULL, 0x090000000ULL,
+			    0x091000000ULL, 1, 1, 1, 1, 1, 0, 2, 2);
+
+			if (machine->x11_md.in_use) {
+				ali_s3 = arcbios_addchild_manual(cpu,
+				    COMPONENT_CLASS_ControllerClass,
+				    COMPONENT_TYPE_DisplayController,
+				    COMPONENT_FLAG_ConsoleOut |
+					COMPONENT_FLAG_Output,
+				    1, 2, 0, 0xffffffff, "ALI_S3",
+				    jazzbus, NULL, 0);
+
+				arcbios_addchild_manual(cpu,
+				    COMPONENT_CLASS_PeripheralClass,
+				    COMPONENT_TYPE_MonitorPeripheral,
+				    COMPONENT_FLAG_ConsoleOut |
+					COMPONENT_FLAG_Output,
+				    1, 2, 0, 0xffffffff, "1024x768",
+				    ali_s3, NULL, 0);
+			}
+			break;
+		case MACHINE_ARC_JAZZ_MAGNUM:
+			if (machine->x11_md.in_use) {
+				vxl = arcbios_addchild_manual(cpu,
+				    COMPONENT_CLASS_ControllerClass,
+				    COMPONENT_TYPE_DisplayController,
+				    COMPONENT_FLAG_ConsoleOut |
+					COMPONENT_FLAG_Output,
+				    1, 2, 0, 0xffffffff, "VXL",
+				    jazzbus, NULL, 0);
+
+				arcbios_addchild_manual(cpu,
+				    COMPONENT_CLASS_PeripheralClass,
+				    COMPONENT_TYPE_MonitorPeripheral,
+				    COMPONENT_FLAG_ConsoleOut |
+					COMPONENT_FLAG_Output,
+				    1, 2, 0, 0xffffffff, "1024x768",
+				    vxl, NULL, 0);
+			}
+			break;
+		}
+
+		diskcontroller = arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_ControllerClass,
+		    COMPONENT_TYPE_DiskController,
+			COMPONENT_FLAG_Input | COMPONENT_FLAG_Output,
+		    1, 2, 0, 0xffffffff, "I82077", jazzbus, NULL, 0);
+
+		/* uint64_t floppy = */ arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_PeripheralClass,
+		    COMPONENT_TYPE_FloppyDiskPeripheral,
+			COMPONENT_FLAG_Removable |
+			COMPONENT_FLAG_Input | COMPONENT_FLAG_Output,
+		    1, 2, 0, 0xffffffff, NULL, diskcontroller, NULL, 0);
+
+		kbdctl = arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_ControllerClass,
+		    COMPONENT_TYPE_KeyboardController,
+			COMPONENT_FLAG_ConsoleIn | COMPONENT_FLAG_Input,
+		    1, 2, 0, 0xffffffff, "I8742", jazzbus, NULL, 0);
+
+		/* uint64_t kbd = */ arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_PeripheralClass,
+		    COMPONENT_TYPE_KeyboardPeripheral,
+			COMPONENT_FLAG_ConsoleIn | COMPONENT_FLAG_Input,
+		    1, 2, 0, 0xffffffff, "PCAT_ENHANCED", kbdctl, NULL, 0);
+
+		ptrctl = arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_ControllerClass,
+		    COMPONENT_TYPE_PointerController, COMPONENT_FLAG_Input,
+		    1, 2, 0, 0xffffffff, "I8742", jazzbus, NULL, 0);
+
+		/* uint64_t ptr = */ arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_PeripheralClass,
+		    COMPONENT_TYPE_PointerPeripheral, COMPONENT_FLAG_Input,
+		    1, 2, 0, 0xffffffff, "PS2 MOUSE", ptrctl, NULL, 0);
+
+/*  These cause Windows NT to bug out.  */
+#if 0
+		serial1 = arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_ControllerClass,
+		    COMPONENT_TYPE_SerialController,
+			COMPONENT_FLAG_Input | COMPONENT_FLAG_Output,
+		    1, 2, 0, 0xffffffff, "COM1", jazzbus, NULL, 0);
+
+		serial2 = arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_ControllerClass,
+		    COMPONENT_TYPE_SerialController,
+			COMPONENT_FLAG_Input | COMPONENT_FLAG_Output,
+		    1, 2, 0, 0xffffffff, "COM1", jazzbus, NULL, 0);
+#endif
+
+		/* uint64_t paral = */ arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_ControllerClass,
+		    COMPONENT_TYPE_ParallelController,
+			COMPONENT_FLAG_Input | COMPONENT_FLAG_Output,
+		    1, 2, 0, 0xffffffff, "LPT1", jazzbus, NULL, 0);
+
+		/* uint64_t audio = */ arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_ControllerClass,
+		    COMPONENT_TYPE_AudioController,
+			COMPONENT_FLAG_Input | COMPONENT_FLAG_Output,
+		    1, 2, 0, 0xffffffff, "MAGNUM", jazzbus, NULL, 0);
+
+		/* uint64_t eisa = */ arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_AdapterClass, COMPONENT_TYPE_EISAAdapter,
+		    0, 1, 2, 0, 0xffffffff, "EISA", system, NULL, 0);
+
+		{
+			unsigned char config[78];
+			memset(config, 0, sizeof(config));
+
+/*  config data version: 1, revision: 2, count: 4  */
+config[0] = 0x01; config[1] = 0x00;
+config[2] = 0x02; config[3] = 0x00;
+config[4] = 0x04; config[5] = 0x00; config[6] = 0x00; config[7] = 0x00;
+
+/*
+          type: Interrupt
+           share_disposition: DeviceExclusive, flags: LevelSensitive
+           level: 4, vector: 22, reserved1: 0
+*/
+			config[8] = arc_CmResourceTypeInterrupt;
+			config[9] = arc_CmResourceShareDeviceExclusive;
+			config[10] = arc_CmResourceInterruptLevelSensitive;
+			config[12] = 4;
+			config[16] = 22;
+			config[20] = 0;
+
+/*
+          type: Memory
+           share_disposition: DeviceExclusive, flags: ReadWrite
+           start: 0x 0 80002000, length: 0x1000
+*/
+			config[24] = arc_CmResourceTypeMemory;
+			config[25] = arc_CmResourceShareDeviceExclusive;
+			config[26] = arc_CmResourceMemoryReadWrite;
+config[28] = 0x00; config[29] = 0x20; config[30] = 0x00; config[31] = 0x80;
+  config[32] = 0x00; config[33] = 0x00; config[34] = 0x00; config[35] = 0x00;
+config[36] = 0x00; config[37] = 0x10; config[38] = 0x00; config[39] = 0x00;
+
+/*
+          type: DMA
+           share_disposition: DeviceExclusive, flags: 0x0
+           channel: 0, port: 0, reserved1: 0
+*/
+			config[40] = arc_CmResourceTypeDMA;
+			config[41] = arc_CmResourceShareDeviceExclusive;
+/*  42..43 = flags, 44,45,46,47 = channel, 48,49,50,51 = port, 52,53,54,55
+ = reserved  */
+
+/*          type: DeviceSpecific
+           share_disposition: DeviceExclusive, flags: 0x0
+           datasize: 6, reserved1: 0, reserved2: 0
+           data: [0x1:0x0:0x2:0x0:0x7:0x30]
+*/
+			config[56] = arc_CmResourceTypeDeviceSpecific;
+			config[57] = arc_CmResourceShareDeviceExclusive;
+/*  58,59 = flags  60,61,62,63 = data size, 64..71 = reserved  */
+			config[60] = 6;
+/*  72..77 = the data  */
+			config[72] = 0x01; config[73] = 0x00; config[74] = 0x02;
+			config[75] = 0x00; config[76] = 0x07; config[77] = 0x30;
+			scsi = arcbios_addchild_manual(cpu,
+			    COMPONENT_CLASS_AdapterClass,
+			    COMPONENT_TYPE_SCSIAdapter,
+			    0, 1, 2, 0, 0xffffffff, "ESP216",
+			    system, config, sizeof(config));
+
+			arcbios_register_scsicontroller(machine, scsi);
+		}
+	}
+}
+
+
+/*
+ *  arcbios_console_init():
+ *
+ *  Called from machine.c whenever an ARC-based machine is running with
+ *  a graphical VGA-style framebuffer, which can be used as console.
+ */
+void arcbios_console_init(struct machine *machine,
+	uint64_t vram, uint64_t ctrlregs)
+{
+	if (machine->md.arc == NULL) {
+		CHECK_ALLOCATION(machine->md.arc = (struct machine_arcbios *)
+		    malloc(sizeof(struct machine_arcbios)));
+		memset(machine->md.arc, 0, sizeof(struct machine_arcbios));
+	}
+
+	machine->md.arc->vgaconsole = 1;
+
+	machine->md.arc->console_vram = vram;
+	machine->md.arc->console_ctrlregs = ctrlregs;
+	machine->md.arc->console_maxx = ARC_CONSOLE_MAX_X;
+	machine->md.arc->console_maxy = ARC_CONSOLE_MAX_Y;
+	machine->md.arc->in_escape_sequence = 0;
+	machine->md.arc->escape_sequence[0] = '\0';
+}
+
+
+struct envstrings
+{
+	int	n;
+	
+	char	**name;
+	char	**value;
+};
+
+void set_env(struct envstrings* env, const char* name, const char* value)
+{
+	int found = -1;
+
+	// Linear search. Slow but it works.
+	for (int i = 0; i < env->n; ++i) {
+		if (strcasecmp(env->name[i], name) == 0) {
+			found = i;
+			break;
+		}
+	}
+
+	if (found >= 0) {
+		free(env->value[found]);
+		env->value[found] = strdup(value);
+	} else {
+		if (env->n == 0) {
+			env->name = malloc(0);
+			env->value = malloc(0);
+		}
+
+		env->n ++;
+
+		env->name = realloc(env->name, sizeof(const char*) * env->n);
+		env->value = realloc(env->value, sizeof(const char*) * env->n);
+
+		env->name[env->n - 1] = strdup(name);
+		env->value[env->n - 1] = strdup(value);
+	}
+}
+
+
+static char* environment_string(struct machine *machine, struct envstrings* env, const char* variable_name, bool name_and_value)
+{
+	size_t len = strlen(variable_name);
+	int found = -1;
+
+	// Linear search. Slow but it works.
+	for (int i = 0; i < env->n; ++i) {
+		if (strcasecmp(env->name[i], variable_name) == 0) {
+			found = i;
+			break;
+		}
+	}
+
+	size_t len_with_value = len + 1;
+	if (found >= 0)
+		len_with_value += strlen(env->value[found]);
+
+	char* s = malloc(len_with_value + 1);
+
+	if (name_and_value) {
+		if (found < 0)
+			snprintf(s, len_with_value + 1, "%s=", variable_name);
+		else
+			snprintf(s, len_with_value + 1, "%s=%s", variable_name, env->value[found]);
+	} else {
+		// Value only.
+		if (found < 0)
+			s[0] = '\0';
+		else
+			snprintf(s, len_with_value + 1, "%s", env->value[found]);
+	}
+
+	if (machine->machine_type == MACHINE_ARC) {
+		for (size_t i = 0; i < len; ++i)
+			s[i] = toupper(s[i]);
+	}
+
+	return s;
+}
+
+
+/*
+ *  arc_environment_setup():
+ *
+ *  Initialize the emulated environment variables.
+ */
+static void arc_environment_setup(struct machine *machine, int is64bit,
+	const char *primary_ether_addr)
+{
+	struct envstrings* env = malloc(sizeof(struct envstrings));
+	memset(env, 0, sizeof(struct envstrings));
+
+	uint64_t addr, addr2;
+	struct cpu *cpu = machine->cpus[0];
+
+	/*
+	 *  Boot string in ARC format:
+	 *
+	 *  TODO: How about floppies? multi()disk()fdisk()
+	 *        Is tftp() good for netbooting?
+	 */
+	char *boot_device;
+
+	if (machine->bootdev_id < 0 || machine->force_netboot) {
+		boot_device = "tftp()";
+	} else {
+		char* prefix = "";
+
+		if (machine->machine_type == MACHINE_SGI) {
+			switch (machine->machine_subtype) {
+			case 30:
+				prefix = "xio(0)pci(15)";
+				break;
+			case 32:
+				prefix = "pci(0)";
+				break;
+			default:
+				fprintf(stderr, "TODO: prefix for SGI IP%i\n", machine->machine_subtype);
+				exit(1);
+			}
+		}
+
+		boot_device = prefix;
+
+		if (diskimage_is_a_cdrom(machine, machine->bootdev_id, machine->bootdev_type)) {
+			size_t len = strlen(boot_device) + 50;
+			char* cdrom = malloc(len);
+			snprintf(cdrom, len, "%sscsi(0)cdrom(%i)", boot_device, machine->bootdev_id);
+			boot_device = cdrom;
+		} else {
+			size_t len = strlen(boot_device) + 50;
+			char* disk = malloc(len);
+			snprintf(disk, len, "%sscsi(0)disk(%i)rdisk(0)", boot_device, machine->bootdev_id);
+			boot_device = disk;
+		}
+
+		char *systempartition;
+		if (machine->machine_type == MACHINE_SGI || !diskimage_is_a_cdrom(machine, machine->bootdev_id, machine->bootdev_type)) {
+			int partition = 1;	// default ARC partition?
+			if (machine->machine_type == MACHINE_SGI)
+				partition = 8;
+
+			size_t len = strlen(boot_device) + 50;
+			systempartition = malloc(len);
+			snprintf(systempartition, len, "%spartition(%i)", boot_device, partition);
+		} else {
+			size_t len = strlen(boot_device) + 50;
+			systempartition = malloc(len);
+			snprintf(systempartition, len, "%sfdisk(0)", boot_device);
+		}
+
+		set_env(env, "SystemPartition", systempartition);
+
+		char *osloadpartition;
+		if (machine->machine_type == MACHINE_SGI || !diskimage_is_a_cdrom(machine, machine->bootdev_id, machine->bootdev_type)) {
+			int partition = 1;	// default ARC partition?
+			if (machine->machine_type == MACHINE_SGI)
+				partition = 0;
+
+			size_t len = strlen(boot_device) + 50;
+			osloadpartition = malloc(len);
+			snprintf(osloadpartition, len, "%spartition(%i)", boot_device, partition);
+		} else {
+			size_t len = strlen(boot_device) + 50;
+			osloadpartition = malloc(len);
+			snprintf(osloadpartition, len, "%sfdisk(0)", boot_device);
+		}
+
+		set_env(env, "OSLoadPartition", osloadpartition);
+	}
+
+	if (machine->machine_type == MACHINE_ARC) {
+		set_env(env, "OSLoader", "\\os\\nt\\osloader.exe");
+		set_env(env, "OSLoadFilename", "\\todo");
+	} else {
+		set_env(env, "OSLoader", "sash");
+		set_env(env, "OSLoadFilename", "/unix");
+	}
+
+	if (machine->boot_kernel_filename[0] != '\0') {
+		size_t len = strlen(machine->boot_kernel_filename) + 10;
+		char* s = malloc(len);
+		snprintf(s, len, "/%s", machine->boot_kernel_filename);
+		set_env(env, "OSLoadFilename", s);
+	}
+
+	if (machine->machine_type == MACHINE_SGI) {
+		/*  g for graphical mode. G for graphical mode with SGI logo visible on Irix?  */
+		if (machine->x11_md.in_use) {
+			set_env(env, "ConsoleIn", "keyboard()");
+			set_env(env, "ConsoleOut", "video()");
+			set_env(env, "console", "g");
+			set_env(env, "gfx", "alive");
+		} else {
+			/*  'd' or 'd2' in Irix, 'ttyS0' in Linux?  */
+			set_env(env, "ConsoleIn", "serial(0)");
+			set_env(env, "ConsoleOut", "serial(0)");
+			set_env(env, "console", "d");
+			set_env(env, "gfx", "dead");
+		}
+
+		set_env(env, "AutoLoad", "No");
+		
+		if (machine->bootdev_id < 0 || machine->force_netboot) {
+			/*
+			 *  diskless=1 means boot from network disk? (nfs?)
+			 *  diskless=2 means boot from network tape? TODO
+			 */
+			set_env(env, "diskless", "1");
+
+			// store_pointer_and_advance(cpu, &addr2, addr, is64bit);
+			// add_environment_string(cpu, "tapedevice=bootp()10.0.0.2:/dev/tape", &addr);
+
+			set_env(env, "root", "xyz");	// TODO
+
+			set_env(env, "bootfile", "bootp()10.0.0.2:/var/boot/client/unix");
+			set_env(env, "SystemPartition", "bootp()10.0.0.2:/var/boot/client");
+			set_env(env, "OSLoadPartition", "bootp()10.0.0.2:/var/boot/client");
+		} else {
+			set_env(env, "diskless", "0");
+		}
+
+		/*  TODO: Keep these variables in sync with bootblock loading,
+			i.e. OSLoader is the name of the voldir entry to boot
+			with.  */
+
+		set_env(env, "kernname", "unix");	// TODO: like OSLoadFilename?
+
+		set_env(env, "volume", "80");
+		set_env(env, "sgilogo", "y");
+		set_env(env, "monitor", "h");
+		set_env(env, "TimeZone", "GMT");
+		set_env(env, "nogfxkbd", "1");
+		set_env(env, "keybd", "US");
+		set_env(env, "cpufreq", "123");
+		set_env(env, "dbaud", "9600");
+		set_env(env, "rbaud", "9600");
+		set_env(env, "rebound", "y");
+		set_env(env, "crt_option", "1");
+		set_env(env, "netaddr", "10.0.0.1");
+		set_env(env, "netmask", "255.0.0.0");
+		set_env(env, "dlserver", "10.0.0.2");
+		set_env(env, "srvaddr", "10.0.0.2");
+		set_env(env, "eaddr", primary_ether_addr);
+
+		// showconfig 0 means don't show. 1 means show some.
+		// 2 means show more. TODO: higher values?
+		set_env(env, "showconfig", "255");
+
+		set_env(env, "verbose", "1");
+		set_env(env, "diagmode", "v");
+		set_env(env, "debug_bigmem", "1");
+	} else {
+		//  General ARC:
+		if (machine->x11_md.in_use) {
+			set_env(env, "ConsoleIn", "multi()key()keyboard()console()");
+			set_env(env, "ConsoleOut", "multi()video()monitor()console()");
+		} else {
+			/*  TODO: serial console for ARC?  */
+			set_env(env, "ConsoleIn", "multi()serial(0)");
+			set_env(env, "ConsoleOut", "multi()serial(0)");
+		}
+	}
+
+	/*  Boot string is either:
+		SystemPartition + OSLoader	  (e.g. sash)
+	    or
+	    	OSLoadPartition + OSLoadFilename  (e.g. /unix)  */
+
+	char* s1 = environment_string(machine, env, "SystemPartition", true);
+	char* s2 = environment_string(machine, env, "OSLoader", true);
+	size_t s3len = strlen(s1) + strlen(s2) + 100;
+	char* boot_string = malloc(s3len);
+	snprintf(boot_string, s3len, "%s%s%s", s1, machine->machine_type == MACHINE_SGI ? "/" : "\\", s2);
+	free(s2);
+	free(s1);
+
+	// boot_string = env["OSLoadPartition"] + env["OSLoadFilename"];
+
+	/*  Boot args., eg "-a"  */
+	machine->bootarg = machine->boot_string_argument;
+
+	if (machine->machine_type == MACHINE_SGI) {
+		set_env(env, "OSLoadOptions", "auto");
+	} else {
+		set_env(env, "OSLoadOptions", machine->bootarg);
+	}
+
+	/*  a0 = argc:  */
+	cpu->cd.mips.gpr[MIPS_GPR_A0] = 0; /*  note: argc is increased later  */
+
+	/*  sp = just below top of RAM. (TODO: not needed?)  */
+	cpu->cd.mips.gpr[MIPS_GPR_SP] = (int64_t)(int32_t)
+	    (machine->physical_ram_in_mb * 1048576 + 0x80000000 - 0x2080);
+
+	/*  a1 = argv:  */
+	addr = ARC_ENV_STRINGS;
+	addr2 = ARC_ARGV_START;
+	cpu->cd.mips.gpr[MIPS_GPR_A1] = addr2;
+
+	CHECK_ALLOCATION(machine->bootstr = strdup(boot_string));
+
+	/*  bootstr:  */
+	store_pointer_and_advance(cpu, &addr2, addr, is64bit);
+	add_environment_string(cpu, machine->bootstr, &addr);
+	cpu->cd.mips.gpr[MIPS_GPR_A0] ++;
+
+	/*  bootarg:  */
+	if (machine->bootarg[0] != '\0') {
+		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
+		add_environment_string(cpu, machine->bootarg, &addr);
+		cpu->cd.mips.gpr[MIPS_GPR_A0] ++;
+	}
+
+	/*  A few of the environment variables are also included as regular
+	    arguments, as per
+	    https://misc.openbsd.narkive.com/6hkw57ju/openbsd-sgi-snapshot-fails-to-boot-from-harddisk#post2  */
+	store_pointer_and_advance(cpu, &addr2, addr, is64bit);
+	char* ev = environment_string(machine, env, "OSLoadOptions", true);
+	add_environment_string(cpu, ev, &addr);
+	free(ev);
+	cpu->cd.mips.gpr[MIPS_GPR_A0] ++;
+
+	store_pointer_and_advance(cpu, &addr2, addr, is64bit);
+	ev = environment_string(machine, env, "ConsoleIn", true);
+	add_environment_string(cpu, ev, &addr);
+	free(ev);
+	cpu->cd.mips.gpr[MIPS_GPR_A0] ++;
+
+	store_pointer_and_advance(cpu, &addr2, addr, is64bit);
+	ev = environment_string(machine, env, "ConsoleOut", true);
+	add_environment_string(cpu, ev, &addr);
+	free(ev);
+	cpu->cd.mips.gpr[MIPS_GPR_A0] ++;
+
+	store_pointer_and_advance(cpu, &addr2, addr, is64bit);
+	ev = environment_string(machine, env, "SystemPartition", true);
+	add_environment_string(cpu, ev, &addr);
+	free(ev);
+	cpu->cd.mips.gpr[MIPS_GPR_A0] ++;
+
+	store_pointer_and_advance(cpu, &addr2, addr, is64bit);
+	ev = environment_string(machine, env, "OSLoader", true);
+	add_environment_string(cpu, ev, &addr);
+	free(ev);
+	cpu->cd.mips.gpr[MIPS_GPR_A0] ++;
+
+	store_pointer_and_advance(cpu, &addr2, addr, is64bit);
+	ev = environment_string(machine, env, "OSLoadPartition", true);
+	add_environment_string(cpu, ev, &addr);
+	free(ev);
+	cpu->cd.mips.gpr[MIPS_GPR_A0] ++;
+
+	store_pointer_and_advance(cpu, &addr2, addr, is64bit);
+	ev = environment_string(machine, env, "OSLoadFilename", true);
+	add_environment_string(cpu, ev, &addr);
+	free(ev);
+	cpu->cd.mips.gpr[MIPS_GPR_A0] ++;
+
+	/*  a2 = envp:  */
+	cpu->cd.mips.gpr[MIPS_GPR_A2] = addr2;
+
+	if (machine->machine_type == MACHINE_SGI) {
+		/*
+		 *  The SGI O2 PROM contains an "env" section header like this:
+		 *
+		 *  00004000  00 00 00 00 00 00 00 00  53 48 44 52 00 00 04 00  |........SHDR....|
+		 *  00004010  03 03 00 00 65 6e 76 00  00 00 00 00 00 00 00 00  |....env.........|
+		 *  00004020  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
+		 *  00004030  00 00 00 00 31 2e 30 00  00 00 00 00 13 18 11 ae  |....1.0.........|
+		 *
+		 *  followed by environment variables at 0x4040. It is not required
+		 *  by NetBSD/OpenBSD/Linux, but Irix seems to hardcodedly look into
+		 *  the PROM address space for this header.
+		 */
+		store_32bit_word(cpu, ARC_ENV_SGI + 0x08, 0x53484452);
+		store_32bit_word(cpu, ARC_ENV_SGI + 0x0c, 0x00000400);
+		store_32bit_word(cpu, ARC_ENV_SGI + 0x10, 0x03030000);
+		store_32bit_word(cpu, ARC_ENV_SGI + 0x14, 0x656e7600);
+		store_32bit_word(cpu, ARC_ENV_SGI + 0x34, 0x312e3000);
+		store_32bit_word(cpu, ARC_ENV_SGI + 0x3c, 0x131811ae);
+		addr = ARC_ENV_STRINGS_SGI;
+	}
+
+	/*
+	 *  Add environment variables.  For each variable, add it as a string
+	 *  using add_environment_string(), and add a pointer to it to the
+	 *  pointer array.
+	 */
+	for (int i = 0; i < env->n; ++i) {
+		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
+		char* s = environment_string(machine, env, env->name[i], true);
+		add_environment_string(cpu, s, &addr);
+		free(s);
+	}
+
+	/*  End the environment strings with an empty zero-terminated
+	    string, and the envp array with a NULL pointer.  */
+	add_environment_string(cpu, "", &addr);	/*  the end  */
+	store_pointer_and_advance(cpu, &addr2, 0, is64bit);
+
+	/*  Return address:  (0x20 = ReturnFromMain())  */
+	cpu->cd.mips.gpr[MIPS_GPR_RA] = ARC_FIRMWARE_ENTRIES + 0x20;
+}
+
+
+/*
+ *  arcbios_init():
+ *
+ *  Should be called before any other arcbios function is used. An exception
+ *  is arcbios_console_init(), which may be called before this function.
+ *
+ *  TODO: Refactor; this is too long.
+ */
+void arcbios_init(struct machine *machine, int is64bit, uint64_t sgi_ram_offset,
+	const char *primary_ether_addr, uint8_t *primary_ether_macaddr)
+{
+	int i, alloclen = 20;
+	char *name;
+	uint64_t arc_reserved, mem_base;
+	struct cpu *cpu = machine->cpus[0];
+	struct arcbios_dsp_stat arcbios_dsp_stat;
+	uint64_t system = 0;
+
+	if (machine->md.arc == NULL) {
+		CHECK_ALLOCATION(machine->md.arc = (struct machine_arcbios *)
+		    malloc(sizeof(struct machine_arcbios)));
+		memset(machine->md.arc, 0, sizeof(struct machine_arcbios));
+	}
+
+	machine->md.arc->arc_64bit = is64bit;
+	machine->md.arc->wordlen = is64bit? sizeof(uint64_t) : sizeof(uint32_t);
+
+	machine->md.arc->next_component_address = FIRST_ARC_COMPONENT;
+	machine->md.arc->configuration_data_next_addr = ARC_CONFIG_DATA_ADDR;
+
+	if (machine->physical_ram_in_mb < 16)
+		fprintf(stderr, "WARNING! The ARC platform specification "
+		    "doesn't allow less than 16 MB of RAM. Continuing "
+		    "anyway.\n");
+
+	/*  File handles 0, 1, and 2 are stdin, stdout, and stderr.  */
+	for (i=0; i<ARC_MAX_HANDLES; i++) {
+		machine->md.arc->file_handle_in_use[i] = i<3? 1 : 0;
+		machine->md.arc->file_handle_string[i] = i>=3? NULL :
+		    (i==0? "(stdin)" : (i==1? "(stdout)" : "(stderr)"));
+		machine->md.arc->current_seek_offset[i] = 0;
+	}
+
+	if (!machine->x11_md.in_use)
+		machine->md.arc->vgaconsole = 0;
+
+	if (machine->md.arc->vgaconsole) {
+		char tmpstr[100];
+		int x, y;
+
+		machine->md.arc->console_curcolor = 0x1f;
+		for (y=0; y<machine->md.arc->console_maxy; y++)
+			for (x=0; x<machine->md.arc->console_maxx; x++)
+				arcbios_putcell(cpu, ' ', x, y);
+
+		machine->md.arc->console_curx = 0;
+		machine->md.arc->console_cury = 0;
+
+		arcbios_putstring(cpu, "GXemul " VERSION"  ARCBIOS emulation\n");
+
+		snprintf(tmpstr, sizeof(tmpstr), "%i cpu%s (%s), %i MB "
+		    "memory\n\n", machine->ncpus, machine->ncpus > 1? "s" : "",
+		    cpu->cd.mips.cpu_type.name,
+		    machine->physical_ram_in_mb);
+		arcbios_putstring(cpu, tmpstr);
+	}
+
+	arcbios_set_default_exception_handler(cpu);
+
+	struct arcbios_sysid arcbios_sysid;
+	memset(&arcbios_sysid, 0, sizeof(arcbios_sysid));
+	if (machine->machine_type == MACHINE_SGI) {
+		/*  Vendor ID, max 8 chars:  */
+		memcpy(arcbios_sysid.VendorId, "SGI", 3);
+
+		switch (machine->machine_subtype) {
+		case 22:
+			memcpy(arcbios_sysid.ProductId, "87654321", 8);	/*  some kind of ID?  */
+			break;
+		case 32:
+			memcpy(arcbios_sysid.ProductId, "f", 1);    /*  "6", "8", of "f"? It's "f" on my O2.  */
+			break;
+		default:
+			snprintf(arcbios_sysid.ProductId, 8, "IP%i", machine->machine_subtype);
+		}
+	} else {
+		switch (machine->machine_subtype) {
+		case MACHINE_ARC_JAZZ_PICA:
+			memcpy(arcbios_sysid.VendorId,  "MIPS MAG", 8);
+			memcpy(arcbios_sysid.ProductId, "ijkl", 4);
+			break;
+		case MACHINE_ARC_JAZZ_MAGNUM:
+			memcpy(arcbios_sysid.VendorId,  "MIPS MAG", 8);
+			memcpy(arcbios_sysid.ProductId, "ijkl", 4);
+			break;
+		default:
+			fatal("error in machine.c sysid\n");
+			exit(1);
+		}
+	}
+
+	store_buf(cpu, SGI_SYSID_ADDR, (char *)&arcbios_sysid, sizeof(arcbios_sysid));
+
+	arcbios_get_dsp_stat(cpu, &arcbios_dsp_stat);
+	store_buf(cpu, ARC_DSPSTAT_ADDR, (char *)&arcbios_dsp_stat, sizeof(arcbios_dsp_stat));
+
+	/*
+	 *  The first 12 MBs of RAM are simply reserved... this simplifies
+	 *  things a lot.  If there's more than 512MB of RAM, it has to be
+	 *  split in two, according to the ARC spec.
+	 *
+	 *  However, the region of physical address space between 0x10000000
+	 *  and 0x1fffffff (256 - 512 MB) is sometimes occupied by memory
+	 *  mapped devices, for example in the SGI O2, so that portion can not
+	 *  be used.
+	 *
+	 *  Instead, any high memory needs to be added using a machine-specific
+	 *  high address.
+	 */
+	int reserved_bottom_mem_in_mb = 12;
+	int free_type = ARCBIOS_MEM_FreeMemory;
+	
+	machine->md.arc->memdescriptor_base = ARC_MEMDESC_ADDR;
+
+	arc_reserved = 0x2000;
+	if (machine->machine_type == MACHINE_SGI)
+		arc_reserved = 0x4000;
+
+	arcbios_add_memory_descriptor(cpu, 0, arc_reserved,
+	    ARCBIOS_MEM_FirmwarePermanent);
+	arcbios_add_memory_descriptor(cpu, sgi_ram_offset + arc_reserved,
+	    0x60000-arc_reserved, ARCBIOS_MEM_FirmwareTemporary);
+
+	uint64_t ram = 0;
+
+	// Default is to use a physical memory base around zero (0).
+	mem_base = sgi_ram_offset / 1048576;
+
+	while (ram < machine->physical_ram_in_mb) {
+		uint64_t to_add = machine->physical_ram_in_mb - ram;
+
+		if (to_add > 256)
+			to_add = 256;
+
+		if (ram == 0) {
+			// Skip first few MB of RAM, for reserved structures.
+			ram += reserved_bottom_mem_in_mb;
+			mem_base += reserved_bottom_mem_in_mb;
+			to_add -= reserved_bottom_mem_in_mb;
+		}
+
+		arcbios_add_memory_descriptor(cpu, mem_base * 1048576,
+		    to_add * 1048576, free_type);
+
+		ram += to_add;
+		mem_base += to_add;
+
+		if (mem_base == 256) {
+			if (machine->machine_type == MACHINE_SGI &&
+			    machine->machine_subtype == 32) {
+				// mem_base = 0x50000000 / 1048576;
+				// Actually, the above does not seem to work.
+				// Perhaps the ARCS in the O2 simply says
+				// 256 MB regardless of how much more there
+				// is in the machine?
+				break;
+			} else {
+				fatal("Ignoring RAM above 256 MB! (Not yet "
+					"implemented for this machine type.)\n");
+				break;
+			}
+		}
+	}
+
+	/*
+	 *  Components:   (this is an example of what a system could look like)
+	 *
+	 *  [System]
+	 *	[CPU]  (one for each cpu)
+	 *	    [FPU]  (one for each cpu)
+	 *	    [CPU Caches]
+	 *	[Memory]
+	 *	[Ethernet]
+	 *	[Serial]
+	 *	[SCSI]
+	 *	    [Disk]
+	 *
+	 *  Here's a good list of what hardware is in different IP-models:
+	 *  http://www.linux-mips.org/archives/linux-mips/2001-03/msg00101.html
+	 */
+
+	if (machine->machine_name == NULL)
+		fatal("ERROR: machine_name == NULL\n");
+
+	/*  Add the root node:  */
+	switch (machine->machine_type) {
+
+	case MACHINE_SGI:
+		debug("ARCS:\n");
+		debug_indentation(1);
+
+		CHECK_ALLOCATION(name = (char *) malloc(alloclen));
+		snprintf(name, alloclen, "SGI-IP%i", machine->machine_subtype);
+
+		/*  A very special case for IP24 (which identifies itself
+		    as an IP22):  */
+		if (machine->machine_subtype == 24)
+			snprintf(name, alloclen, "SGI-IP22");
+		break;
+
+	case MACHINE_ARC:
+		debug("ARC:\n");
+		debug_indentation(1);
+
+		switch (machine->machine_subtype) {
+		case MACHINE_ARC_JAZZ_PICA:
+			name = strdup("PICA-61");
+			break;
+		case MACHINE_ARC_JAZZ_MAGNUM:
+			name = strdup("Microsoft-Jazz");
+			break;
+		default:
+			fatal("Unimplemented ARC machine type %i\n",
+			    machine->machine_subtype);
+			exit(1);
+		}
+		break;
+
+	default:
+		fatal("ERROR: non-SGI and non-ARC?\n");
+		exit(1);
+	}
+
+	system = arcbios_addchild_manual(cpu, COMPONENT_CLASS_SystemClass,
+	    COMPONENT_TYPE_ARC, 0,1,2,0, 0xffffffff, name, 0/*ROOT*/, NULL, 0);
+	debug("system @ 0x%" PRIx64" (\"%s\")\n", (uint64_t) system, name);
+
+
+	/*
+	 *  Add tree nodes for CPUs and their caches:
+	 */
+
+	for (i=0; i<machine->ncpus; i++) {
+		uint64_t cpuaddr, fpu=0, picache, pdcache, sdcache=0;
+		int cache_size, cache_line_size;
+		unsigned int jj;
+		char arc_cpu_name[100];
+		char arc_fpc_name[105];
+
+		snprintf(arc_cpu_name, sizeof(arc_cpu_name),
+		    "MIPS-%s", machine->cpu_name);
+
+		arc_cpu_name[sizeof(arc_cpu_name)-1] = 0;
+		for (jj=0; jj<strlen(arc_cpu_name); jj++)
+			if (arc_cpu_name[jj] >= 'a' && arc_cpu_name[jj] <= 'z')
+				arc_cpu_name[jj] += ('A' - 'a');
+
+		strlcpy(arc_fpc_name, arc_cpu_name, sizeof(arc_fpc_name));
+		strlcat(arc_fpc_name, "FPC", sizeof(arc_fpc_name));
+
+		cpuaddr = arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_ProcessorClass, COMPONENT_TYPE_CPU,
+		    0, 1, 2, i, 0xffffffff, arc_cpu_name, system, NULL, 0);
+
+		/*
+		 *  TODO: This was in the ARC specs, but it isn't really used
+		 *  by ARC implementations?   At least SGI-IP32 uses it.
+		 */
+		if (machine->machine_type == MACHINE_SGI)
+			fpu = arcbios_addchild_manual(cpu,
+			    COMPONENT_CLASS_ProcessorClass, COMPONENT_TYPE_FPU,
+			    0, 1, 2, 0, 0xffffffff, arc_fpc_name, cpuaddr,
+			    NULL, 0);
+
+		cache_size = DEFAULT_PCACHE_SIZE - 12;
+		if (cpu->cd.mips.cache_picache)
+			cache_size = cpu->cd.mips.cache_picache - 12;
+		if (cache_size < 0)
+			cache_size = 0;
+
+		cache_line_size = DEFAULT_PCACHE_LINESIZE;
+		if (cpu->cd.mips.cache_picache_linesize)
+			cache_line_size = cpu->cd.mips.cache_picache_linesize;
+		if (cache_line_size < 0)
+			cache_line_size = 0;
+
+		picache = arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_CacheClass, COMPONENT_TYPE_PrimaryICache,
+		    0, 1, 2,
+		    /*
+		     *  Key bits:  0xXXYYZZZZ
+		     *  XX is refill-size.
+		     *  Cache line size is 1 << YY,
+		     *  Cache size is 4KB << ZZZZ.
+		     */
+		    0x01000000 + (cache_line_size << 16) + cache_size,
+			/*  32 bytes per line, default = 32 KB total  */
+		    0xffffffff, NULL, cpuaddr, NULL, 0);
+
+		cache_size = DEFAULT_PCACHE_SIZE - 12;
+		if (cpu->cd.mips.cache_pdcache)
+			cache_size = cpu->cd.mips.cache_pdcache - 12;
+		if (cache_size < 0)
+			cache_size = 0;
+
+		cache_line_size = DEFAULT_PCACHE_LINESIZE;
+		if (cpu->cd.mips.cache_pdcache_linesize)
+			cache_line_size = cpu->cd.mips.cache_pdcache_linesize;
+		if (cache_line_size < 0)
+			cache_line_size = 0;
+
+		pdcache = arcbios_addchild_manual(cpu,
+		    COMPONENT_CLASS_CacheClass,
+		    COMPONENT_TYPE_PrimaryDCache, 0, 1, 2,
+		    /*
+		     *  Key bits:  0xYYZZZZ
+		     *  Cache line size is 1 << YY,
+		     *  Cache size is 4KB << ZZZZ.
+		     */
+		    0x01000000 + (cache_line_size << 16) + cache_size,
+			/*  32 bytes per line, default = 32 KB total  */
+		    0xffffffff, NULL, cpuaddr, NULL, 0);
+
+		if (cpu->cd.mips.cache_secondary >= 12) {
+			cache_size = cpu->cd.mips.cache_secondary - 12;
+
+			cache_line_size = 6;	/*  64 bytes default  */
+			if (cpu->cd.mips.cache_secondary_linesize)
+				cache_line_size = cpu->cd.mips.
+				    cache_secondary_linesize;
+			if (cache_line_size < 0)
+				cache_line_size = 0;
+
+			sdcache = arcbios_addchild_manual(cpu,
+			    COMPONENT_CLASS_CacheClass,
+			    COMPONENT_TYPE_SecondaryDCache, 0, 1, 2,
+			    /*
+			     *  Key bits:  0xYYZZZZ
+			     *  Cache line size is 1 << YY,
+			     *  Cache size is 4KB << ZZZZ.
+			     */
+			    0x01000000 + (cache_line_size << 16) + cache_size,
+				/*  64 bytes per line, default = 1 MB total  */
+			    0xffffffff, NULL, cpuaddr, NULL, 0);
+		}
+
+		debug("cpu%i @ 0x%" PRIx64, i, (uint64_t) cpuaddr);
+
+		if (fpu != 0)
+			debug(" (fpu @ 0x%" PRIx64")\n", (uint64_t) fpu);
+		else
+			debug("\n");
+
+		debug("    picache @ 0x%" PRIx64", pdcache @ 0x%" PRIx64"\n",
+		    (uint64_t) picache, (uint64_t) pdcache);
+
+		if (cpu->cd.mips.cache_secondary >= 12)
+			debug("    sdcache @ 0x%" PRIx64"\n",
+			    (uint64_t) sdcache);
+
+		if (machine->machine_type == MACHINE_SGI) {
+			/*  TODO:  Memory amount (and base address?)!  */
+			uint64_t memory = arcbios_addchild_manual(cpu,
+			    COMPONENT_CLASS_MemoryClass,
+			    COMPONENT_TYPE_MemoryUnit, 0, 1, 2, 0,
+			    0xffffffff, "memory", cpuaddr, NULL, 0);
+			debug("memory @ 0x%" PRIx64"\n", (uint64_t) memory);
+		}
+	}
+
+
+	/*
+	 *  Add other components:
+	 *
+	 *  TODO: How should this be synched with the hardware devices
+	 *  added in machine.c?
+	 */
+
+	arcbios_add_other_components(machine, system);
+
+
+	/*
+	 *  Defalt TLB entry for 64-bit SGI machines:
+	 */
+	if (machine->machine_type == MACHINE_SGI) {
+		switch (machine->machine_subtype) {
+		case 12:
+			/*  TODO: Not on 12?  */
+			break;
+		case 32:
+			/*  Not needed for SGI O2?  */
+			break;
+		default:
+			mips_coproc_tlb_set_entry(cpu, 0, 1048576*16,
+			    0xc000000000000000ULL, 0, 1048576*16, 1,1,1,1,1, 0, 2, 2);
+		}
+	}
+
+
+	/*
+	 *  Set up Firmware Vectors:
+	 */
+	add_symbol_name(&machine->symbol_context, ARC_FIRMWARE_ENTRIES, 0x10000, "[ARCBIOS entry]", 0, 1);
+
+	for (i=0; i<100; i++) {
+		if (is64bit) {
+			store_64bit_word(cpu, ARC_FIRMWARE_VECTORS + i*8, ARC_FIRMWARE_ENTRIES + i*8);
+			store_64bit_word(cpu, ARC_PRIVATE_VECTORS + i*8, ARC_PRIVATE_ENTRIES + i*8);
+
+			/*  "Magic trap" instruction:  */
+			store_32bit_word(cpu, ARC_FIRMWARE_ENTRIES + i*8, 0x00c0de0c);
+			store_32bit_word(cpu, ARC_PRIVATE_ENTRIES + i*8, 0x00c0de0c);
+		} else {
+			store_32bit_word(cpu, ARC_FIRMWARE_VECTORS + i*4, ARC_FIRMWARE_ENTRIES + i*4);
+			store_32bit_word(cpu, ARC_PRIVATE_VECTORS + i*4, ARC_PRIVATE_ENTRIES + i*4);
+
+			/*  "Magic trap" instruction:  */
+			store_32bit_word(cpu, ARC_FIRMWARE_ENTRIES + i*4, 0x00c0de0c);
+			store_32bit_word(cpu, ARC_PRIVATE_ENTRIES + i*4, 0x00c0de0c);
+		}
+	}
+
+
+	/*
+	 *  Set up the ARC SPD:
+	 */
+	if (is64bit) {
+		/*  ARCS64 SPD (TODO: This is just a guess)  */
+		struct arcbios_spb_64 arcbios_spb_64;
+		memset(&arcbios_spb_64, 0, sizeof(arcbios_spb_64));
+		store_64bit_word_in_host(cpu, (unsigned char *) &arcbios_spb_64.SPBSignature, ARCBIOS_SPB_SIGNATURE);
+		store_16bit_word_in_host(cpu, (unsigned char *) &arcbios_spb_64.Version, 64);
+		store_16bit_word_in_host(cpu, (unsigned char *) &arcbios_spb_64.Revision, 0);
+		store_64bit_word_in_host(cpu, (unsigned char *) &arcbios_spb_64.FirmwareVector, ARC_FIRMWARE_VECTORS);
+		store_buf(cpu, SGI_SPB_ADDR, (char *)&arcbios_spb_64, sizeof(arcbios_spb_64));
+	} else {
+		/*  ARCBIOS SPB:  (For ARC and 32-bit SGI modes)  */
+		struct arcbios_spb arcbios_spb;
+		memset(&arcbios_spb, 0, sizeof(arcbios_spb));
+		store_32bit_word_in_host(cpu, (unsigned char *) &arcbios_spb.SPBSignature, ARCBIOS_SPB_SIGNATURE);
+		store_32bit_word_in_host(cpu, (unsigned char *) &arcbios_spb.SPBLength, sizeof(arcbios_spb));     
+		store_16bit_word_in_host(cpu, (unsigned char *) &arcbios_spb.Version, 1);
+		store_16bit_word_in_host(cpu, (unsigned char *) &arcbios_spb.Revision, machine->machine_type == MACHINE_SGI? 10 : 2);
+		store_32bit_word_in_host(cpu, (unsigned char *) &arcbios_spb.FirmwareVector, ARC_FIRMWARE_VECTORS);
+		store_32bit_word_in_host(cpu, (unsigned char *) &arcbios_spb.FirmwareVectorLength, 35 * sizeof(uint32_t));
+		store_32bit_word_in_host(cpu, (unsigned char *) &arcbios_spb.PrivateVector, ARC_PRIVATE_VECTORS);
+		store_32bit_word_in_host(cpu, (unsigned char *) &arcbios_spb.PrivateVectorLength, 13 * sizeof(uint32_t));
+
+		if (machine->machine_type == MACHINE_SGI) {
+			// Mimic the "BTSR" Restart block struct on my real O2:
+			// "sash" clears the lowest bit of the word at offset 0x1c, which
+			// is the "Boot Status" word according to the ARC spec.
+			// The lowest bit means "boot started".
+			const uint64_t btsr_addr = SGI_SPB_ADDR + 0x80;
+			store_32bit_word_in_host(cpu, (unsigned char *) &arcbios_spb.RestartBlock, btsr_addr);
+			
+			store_32bit_word(cpu, btsr_addr + 0x00, 0x42545352);
+			store_32bit_word(cpu, btsr_addr + 0x1c, 0x40);	// 0x40 means "Processor Ready"
+		}
+
+		store_buf(cpu, SGI_SPB_ADDR, (char *)&arcbios_spb, sizeof(arcbios_spb));
+	}
+
+
+	/*
+	 *  TODO: How to build the component tree intermixed with
+	 *  the rest of device initialization?
+	 */
+
+	arc_environment_setup(machine, is64bit, primary_ether_addr);
+
+	debug_indentation(-1);
+}
+
diff -Nru gxemul-0.6.2/src/promemul/arcbios.cc gxemul-0.7.0+dfsg/src/promemul/arcbios.cc
--- gxemul-0.6.2/src/promemul/arcbios.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/arcbios.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,2952 +0,0 @@
-/*
- *  Copyright (C) 2003-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: ARCBIOS and ARCS emulation
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-#include <sys/time.h>
-#include <sys/types.h>
-#include <sys/resource.h>
-
-#include "arcbios.h"
-#include "console.h"
-#include "cpu.h"
-#include "cpu_mips.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "machine_arc.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/arcbios_other.h"
-
-
-extern int quiet_mode;
-extern int verbose;
-
-
-/*
- *  arcbios_add_string_to_component():
- */
-void arcbios_add_string_to_component(struct machine *machine,
-	char *str, uint64_t component)
-{
-	if (machine->md.arc->n_string_to_components
-	    >= MAX_STRING_TO_COMPONENT) {
-		printf("Too many string-to-component mappings.\n");
-		exit(1);
-	}
-
-	CHECK_ALLOCATION(machine->md.arc->string_to_component[machine->
-	    md.arc->n_string_to_components] = strdup(str));
-
-	debug("adding ARC component mapping: 0x%08x = %s\n",
-	    (int)component, str);
-
-	machine->md.arc->string_to_component_value[
-	    machine->md.arc->n_string_to_components] = component;
-
-	machine->md.arc->n_string_to_components ++;
-}
-
-
-/*
- *  arcbios_get_dsp_stat():
- *
- *  Fills in an arcbios_dsp_stat struct with valid data.
- */
-static void arcbios_get_dsp_stat(struct cpu *cpu,
-	struct arcbios_dsp_stat *dspstat)
-{
-	memset(dspstat, 0, sizeof(struct arcbios_dsp_stat));
-
-	store_16bit_word_in_host(cpu, (unsigned char *)&dspstat->
-	    CursorXPosition, cpu->machine->md.arc->console_curx + 1);
-	store_16bit_word_in_host(cpu, (unsigned char *)&dspstat->
-	    CursorYPosition, cpu->machine->md.arc->console_cury + 1);
-	store_16bit_word_in_host(cpu, (unsigned char *)&dspstat->
-	    CursorMaxXPosition, ARC_CONSOLE_MAX_X);
-	store_16bit_word_in_host(cpu, (unsigned char *)&dspstat->
-	    CursorMaxYPosition, ARC_CONSOLE_MAX_Y);
-	dspstat->ForegroundColor = cpu->machine->md.arc->console_curcolor;
-	dspstat->HighIntensity = cpu->machine->md.arc->console_curcolor ^ 0x08;
-}
-
-
-/*
- *  arcbios_putcell():
- */
-static void arcbios_putcell(struct cpu *cpu, int ch, int x, int y)
-{
-	unsigned char buf[2];
-	buf[0] = ch;
-	buf[1] = cpu->machine->md.arc->console_curcolor;
-	if (cpu->machine->md.arc->console_reverse)
-		buf[1] = ((buf[1] & 0x70) >> 4) | ((buf[1] & 7) << 4)
-		    | (buf[1] & 0x88);
-	cpu->memory_rw(cpu, cpu->mem, cpu->machine->md.arc->console_vram +
-	    2*(x + cpu->machine->md.arc->console_maxx * y),
-	    &buf[0], sizeof(buf), MEM_WRITE,
-	    CACHE_NONE | PHYSICAL);
-}
-
-
-/*
- *  handle_esc_seq():
- *
- *  Used by arcbios_putchar().
- */
-static void handle_esc_seq(struct cpu *cpu)
-{
-	int i, len = strlen(cpu->machine->md.arc->escape_sequence);
-	int row, col, color, code, start, stop;
-	char *p;
-
-	if (cpu->machine->md.arc->escape_sequence[0] != '[')
-		return;
-
-	code = cpu->machine->md.arc->escape_sequence[len-1];
-	cpu->machine->md.arc->escape_sequence[len-1] = '\0';
-
-	switch (code) {
-	case 'm':
-		color = atoi(cpu->machine->md.arc->escape_sequence + 1);
-		switch (color) {
-		case 0:	/*  Default.  */
-			cpu->machine->md.arc->console_curcolor = 0x1f;
-			cpu->machine->md.arc->console_reverse = 0; break;
-		case 1:	/*  "Bold".  */
-			cpu->machine->md.arc->console_curcolor |= 0x08; break;
-		case 7:	/*  "Reverse".  */
-			cpu->machine->md.arc->console_reverse = 1; break;
-		case 30: /*  Black foreground.  */
-			cpu->machine->md.arc->console_curcolor &= 0xf0;
-			cpu->machine->md.arc->console_curcolor |= 0x00; break;
-		case 31: /*  Red foreground.  */
-			cpu->machine->md.arc->console_curcolor &= 0xf0;
-			cpu->machine->md.arc->console_curcolor |= 0x04; break;
-		case 32: /*  Green foreground.  */
-			cpu->machine->md.arc->console_curcolor &= 0xf0;
-			cpu->machine->md.arc->console_curcolor |= 0x02; break;
-		case 33: /*  Yellow foreground.  */
-			cpu->machine->md.arc->console_curcolor &= 0xf0;
-			cpu->machine->md.arc->console_curcolor |= 0x06; break;
-		case 34: /*  Blue foreground.  */
-			cpu->machine->md.arc->console_curcolor &= 0xf0;
-			cpu->machine->md.arc->console_curcolor |= 0x01; break;
-		case 35: /*  Red-blue foreground.  */
-			cpu->machine->md.arc->console_curcolor &= 0xf0;
-			cpu->machine->md.arc->console_curcolor |= 0x05; break;
-		case 36: /*  Green-blue foreground.  */
-			cpu->machine->md.arc->console_curcolor &= 0xf0;
-			cpu->machine->md.arc->console_curcolor |= 0x03; break;
-		case 37: /*  White foreground.  */
-			cpu->machine->md.arc->console_curcolor &= 0xf0;
-			cpu->machine->md.arc->console_curcolor |= 0x07; break;
-		case 40: /*  Black background.  */
-			cpu->machine->md.arc->console_curcolor &= 0x0f;
-			cpu->machine->md.arc->console_curcolor |= 0x00; break;
-		case 41: /*  Red background.  */
-			cpu->machine->md.arc->console_curcolor &= 0x0f;
-			cpu->machine->md.arc->console_curcolor |= 0x40; break;
-		case 42: /*  Green background.  */
-			cpu->machine->md.arc->console_curcolor &= 0x0f;
-			cpu->machine->md.arc->console_curcolor |= 0x20; break;
-		case 43: /*  Yellow background.  */
-			cpu->machine->md.arc->console_curcolor &= 0x0f;
-			cpu->machine->md.arc->console_curcolor |= 0x60; break;
-		case 44: /*  Blue background.  */
-			cpu->machine->md.arc->console_curcolor &= 0x0f;
-			cpu->machine->md.arc->console_curcolor |= 0x10; break;
-		case 45: /*  Red-blue background.  */
-			cpu->machine->md.arc->console_curcolor &= 0x0f;
-			cpu->machine->md.arc->console_curcolor |= 0x50; break;
-		case 46: /*  Green-blue background.  */
-			cpu->machine->md.arc->console_curcolor &= 0x0f;
-			cpu->machine->md.arc->console_curcolor |= 0x30; break;
-		case 47: /*  White background.  */
-			cpu->machine->md.arc->console_curcolor &= 0x0f;
-			cpu->machine->md.arc->console_curcolor |= 0x70; break;
-		default:fatal("{ handle_esc_seq: color %i }\n", color);
-		}
-		return;
-	case 'H':
-		p = strchr(cpu->machine->md.arc->escape_sequence, ';');
-		if (p == NULL)
-			return;		/*  TODO  */
-		row = atoi(cpu->machine->md.arc->escape_sequence + 1);
-		col = atoi(p + 1);
-		if (col < 1)
-			col = 1;
-		if (row < 1)
-			row = 1;
-		cpu->machine->md.arc->console_curx = col - 1;
-		cpu->machine->md.arc->console_cury = row - 1;
-		return;
-	case 'J':
-		/*
-		 *  J = clear screen below cursor, and the rest of the
-		 *      current line,
-		 *  2J = clear whole screen.
-		 */
-		i = atoi(cpu->machine->md.arc->escape_sequence + 1);
-		if (i != 0 && i != 2)
-			fatal("{ handle_esc_seq(): %iJ }\n", i);
-		if (i == 0)
-			for (col = cpu->machine->md.arc->console_curx;
-			    col < cpu->machine->md.arc->console_maxx; col++)
-				arcbios_putcell(cpu, ' ', col,
-				    cpu->machine->md.arc->console_cury);
-		for (col = 0; col < cpu->machine->md.arc->console_maxx; col++)
-			for (row = i? 0 : cpu->machine->md.arc->console_cury+1;
-			    row < cpu->machine->md.arc->console_maxy; row++)
-				arcbios_putcell(cpu, ' ', col, row);
-		return;
-	case 'K':
-		col = atoi(cpu->machine->md.arc->escape_sequence + 1);
-		/*  2 = clear line to the right. 1 = to the left (?)  */
-		start = 0; stop = cpu->machine->md.arc->console_curx;
-		if (col == 2) {
-			start = cpu->machine->md.arc->console_curx;
-			stop = cpu->machine->md.arc->console_maxx - 1;
-		}
-		for (i=start; i<=stop; i++)
-			arcbios_putcell(cpu, ' ', i,
-			    cpu->machine->md.arc->console_cury);
-
-		return;
-	}
-
-	fatal("{ handle_esc_seq(): unimplemented escape sequence: ");
-	for (i=0; i<len; i++) {
-		int x = cpu->machine->md.arc->escape_sequence[i];
-		if (i == len-1)
-			x = code;
-
-		if (x >= ' ' && x < 127)
-			fatal("%c", x);
-		else
-			fatal("[0x%02x]", x);
-	}
-	fatal(" }\n");
-}
-
-
-/*
- *  scroll_if_necessary():
- */
-static void scroll_if_necessary(struct cpu *cpu)
-{
-	/*  Scroll?  */
-	if (cpu->machine->md.arc->console_cury >=
-	    cpu->machine->md.arc->console_maxy) {
-		unsigned char buf[2];
-		int x, y;
-		for (y=0; y<cpu->machine->md.arc->console_maxy-1; y++)
-			for (x=0; x<cpu->machine->md.arc->console_maxx;
-			    x++) {
-				cpu->memory_rw(cpu, cpu->mem,
-				    cpu->machine->md.arc->console_vram +
-				    2*(x + cpu->machine->md.arc->
-					console_maxx * (y+1)),
-				    &buf[0], sizeof(buf), MEM_READ,
-				    CACHE_NONE | PHYSICAL);
-				cpu->memory_rw(cpu, cpu->mem,
-				    cpu->machine->md.arc->console_vram +
-				    2*(x + cpu->machine->md.arc->
-					console_maxx * y),
-				    &buf[0], sizeof(buf), MEM_WRITE,
-				    CACHE_NONE | PHYSICAL);
-			}
-
-		cpu->machine->md.arc->console_cury =
-		    cpu->machine->md.arc->console_maxy - 1;
-
-		for (x=0; x<cpu->machine->md.arc->console_maxx; x++)
-			arcbios_putcell(cpu, ' ', x,
-			    cpu->machine->md.arc->console_cury);
-	}
-}
-
-
-/*
- *  arcbios_putchar():
- *
- *  If we're using X11 with VGA-style console, then output to that console.
- *  Otherwise, use console_putchar().
- */
-static void arcbios_putchar(struct cpu *cpu, int ch)
-{
-	int addr;
-	unsigned char byte;
-
-	if (!cpu->machine->md.arc->vgaconsole) {
-		/*  Text console output:  */
-
-		/*  Hack for Windows NT, which uses 0x9b instead of ESC + [  */
-		if (ch == 0x9b) {
-			console_putchar(cpu->machine->main_console_handle, 27);
-			ch = '[';
-		}
-		console_putchar(cpu->machine->main_console_handle, ch);
-		return;
-	}
-
-	if (cpu->machine->md.arc->in_escape_sequence) {
-		int len = strlen(cpu->machine->md.arc->escape_sequence);
-		cpu->machine->md.arc->escape_sequence[len] = ch;
-		len++;
-		if (len >= ARC_MAX_ESC)
-			len = ARC_MAX_ESC;
-		cpu->machine->md.arc->escape_sequence[len] = '\0';
-		if ((ch >= 'a' && ch <= 'z') ||
-		    (ch >= 'A' && ch <= 'Z') || len >= ARC_MAX_ESC) {
-			handle_esc_seq(cpu);
-			cpu->machine->md.arc->in_escape_sequence = 0;
-		}
-	} else {
-		if (ch == 27) {
-			cpu->machine->md.arc->in_escape_sequence = 1;
-			cpu->machine->md.arc->escape_sequence[0] = '\0';
-		} else if (ch == 0x9b) {
-			cpu->machine->md.arc->in_escape_sequence = 1;
-			cpu->machine->md.arc->escape_sequence[0] = '[';
-			cpu->machine->md.arc->escape_sequence[1] = '\0';
-		} else if (ch == '\b') {
-			if (cpu->machine->md.arc->console_curx > 0)
-				cpu->machine->md.arc->console_curx --;
-		} else if (ch == '\r') {
-			cpu->machine->md.arc->console_curx = 0;
-		} else if (ch == '\n') {
-			cpu->machine->md.arc->console_cury ++;
-		} else if (ch == '\t') {
-			cpu->machine->md.arc->console_curx =
-			    ((cpu->machine->md.arc->console_curx - 1)
-			    | 7) + 1;
-			/*  TODO: Print spaces?  */
-		} else {
-			/*  Put char:  */
-			if (cpu->machine->md.arc->console_curx >=
-			    cpu->machine->md.arc->console_maxx) {
-				cpu->machine->md.arc->console_curx = 0;
-				cpu->machine->md.arc->console_cury ++;
-				scroll_if_necessary(cpu);
-			}
-			arcbios_putcell(cpu, ch,
-			    cpu->machine->md.arc->console_curx,
-			    cpu->machine->md.arc->console_cury);
-			cpu->machine->md.arc->console_curx ++;
-		}
-	}
-
-	scroll_if_necessary(cpu);
-
-	/*  Update cursor position:  */
-	addr = (cpu->machine->md.arc->console_curx >=
-	    cpu->machine->md.arc->console_maxx?
-	    cpu->machine->md.arc->console_maxx - 1 :
-		cpu->machine->md.arc->console_curx) +
-	    cpu->machine->md.arc->console_cury *
-	    cpu->machine->md.arc->console_maxx;
-	byte = 0x0e;
-	cpu->memory_rw(cpu, cpu->mem, cpu->machine->md.arc->
-	    console_ctrlregs + 0x14,
-	    &byte, sizeof(byte), MEM_WRITE, CACHE_NONE | PHYSICAL);
-	byte = (addr >> 8) & 255;
-	cpu->memory_rw(cpu, cpu->mem, cpu->machine->md.arc->
-	    console_ctrlregs + 0x15,
-	    &byte, sizeof(byte), MEM_WRITE, CACHE_NONE | PHYSICAL);
-	byte = 0x0f;
-	cpu->memory_rw(cpu, cpu->mem, cpu->machine->md.arc->
-	    console_ctrlregs + 0x14,
-	    &byte, sizeof(byte), MEM_WRITE, CACHE_NONE | PHYSICAL);
-	byte = addr & 255;
-	cpu->memory_rw(cpu, cpu->mem, cpu->machine->md.arc->
-	    console_ctrlregs + 0x15,
-	    &byte, sizeof(byte), MEM_WRITE, CACHE_NONE | PHYSICAL);
-}
-
-
-/*
- *  arcbios_putstring():
- */
-static void arcbios_putstring(struct cpu *cpu, const char *s)
-{
-	while (*s) {
-		if (*s == '\n')
-			arcbios_putchar(cpu, '\r');
-		arcbios_putchar(cpu, *s++);
-	}
-}
-
-
-/*
- *  arcbios_register_scsicontroller():
- */
-void arcbios_register_scsicontroller(struct machine *machine,
-	uint64_t scsicontroller_component)
-{
-	machine->md.arc->scsicontroller = scsicontroller_component;
-}
-
-
-/*
- *  arcbios_get_scsicontroller():
- */
-uint64_t arcbios_get_scsicontroller(struct machine *machine)
-{
-	return machine->md.arc->scsicontroller;
-}
-
-
-/*
- *  arcbios_add_memory_descriptor():
- *
- *  NOTE: arctype is the ARC type, not the SGI type. This function takes
- *  care of converting, when necessary.
- */
-void arcbios_add_memory_descriptor(struct cpu *cpu,
-	uint64_t base, uint64_t len, int arctype)
-{
-	uint64_t memdesc_addr;
-	int s;
-	struct arcbios_mem arcbios_mem;
-	struct arcbios_mem64 arcbios_mem64;
-
-	if (verbose >= 2)
-		debug("arcbios_add_memory_descriptor: base=0x%llx len=0x%llx arctype=%i\n",
-			(long long)base, (long long)len, arctype);
-
-	base /= 4096;
-	len /= 4096;
-
-	/*
-	 *  TODO: Huh? Why isn't it necessary to convert from arc to sgi types?
-	 *
-	 *  TODO 2: It seems that it _is_ necessary, but NetBSD's arcdiag
-	 *  doesn't handle the sgi case separately.
-	 */
-#if 1
-	if (cpu->machine->machine_type == MACHINE_SGI) {
-		/*  arctype is SGI style  */
-		/*  printf("%i => ", arctype); */
-		switch (arctype) {
-		case 0:	arctype = 0; break;
-		case 1:	arctype = 1; break;
-		case 2:	arctype = 3; break;
-		case 3:	arctype = 4; break;
-		case 4:	arctype = 5; break;
-		case 5:	arctype = 6; break;
-		case 6:	arctype = 7; break;
-		case 7:	arctype = 2; break;
-		}
-		/*  printf("%i\n", arctype);  */
-	}
-#endif
-	if (cpu->machine->md.arc->arc_64bit)
-		s = sizeof(arcbios_mem64);
-	else
-		s = sizeof(arcbios_mem);
-
-	memdesc_addr = cpu->machine->md.arc->memdescriptor_base +
-	    cpu->machine->md.arc->n_memdescriptors * s;
-
-	if (cpu->machine->md.arc->arc_64bit) {
-		memset(&arcbios_mem64, 0, s);
-		store_32bit_word_in_host(cpu,
-		    (unsigned char *)&arcbios_mem64.Type, arctype);
-		store_64bit_word_in_host(cpu,
-		    (unsigned char *)&arcbios_mem64.BasePage, base);
-		store_64bit_word_in_host(cpu,
-		    (unsigned char *)&arcbios_mem64.PageCount, len);
-		store_buf(cpu, memdesc_addr, (char *)&arcbios_mem64, s);
-	} else {
-		memset(&arcbios_mem, 0, s);
-		store_32bit_word_in_host(cpu,
-		    (unsigned char *)&arcbios_mem.Type, arctype);
-		store_32bit_word_in_host(cpu,
-		    (unsigned char *)&arcbios_mem.BasePage, base);
-		store_32bit_word_in_host(cpu,
-		    (unsigned char *)&arcbios_mem.PageCount, len);
-		store_buf(cpu, memdesc_addr, (char *)&arcbios_mem, s);
-	}
-
-	cpu->machine->md.arc->n_memdescriptors ++;
-}
-
-
-/*
- *  arcbios_addchild():
- *
- *  host_tmp_component is a temporary component, with data formated for
- *  the host system.  It needs to be translated/copied into emulated RAM.
- *
- *  Return value is the virtual (emulated) address of the added component.
- *
- *  TODO:  This function doesn't care about memory management, but simply
- *         stores the new child after the last stored child.
- *  TODO:  This stuff is really ugly.
- */
-static uint64_t arcbios_addchild(struct cpu *cpu,
-	struct arcbios_component *host_tmp_component,
-	const char *identifier, uint32_t parent)
-{
-	struct machine *machine = cpu->machine;
-	uint64_t a = machine->md.arc->next_component_address;
-	uint32_t peer=0;
-	uint32_t child=0;
-	int n_left;
-	uint64_t peeraddr = FIRST_ARC_COMPONENT;
-
-	/*
-	 *  This component has no children yet, but it may have peers (that is,
-	 *  other components that share this component's parent) so we have to
-	 *  set the peer value correctly.
-	 *
-	 *  Also, if this is the first child of some parent, the parent's child
-	 *  pointer should be set to point to this component.  (But only if it
-	 *  is the first.)
-	 *
-	 *  This is really ugly:  scan through all components, starting from
-	 *  FIRST_ARC_COMPONENT, to find a component with the same parent as
-	 *  this component will have.  If such a component is found, and its
-	 *  'peer' value is NULL, then set it to this component's address (a).
-	 *
-	 *  TODO:  make this nicer
-	 */
-
-	n_left = machine->md.arc->n_components;
-	while (n_left > 0) {
-		/*  Load parent, child, and peer values:  */
-		uint32_t eparent, echild, epeer, tmp;
-		unsigned char buf[4];
-
-		/*  debug("[ addchild: peeraddr = 0x%08x ]\n",
-		    (int)peeraddr);  */
-
-		cpu->memory_rw(cpu, cpu->mem,
-		    peeraddr + 0 * machine->md.arc->wordlen, &buf[0],
-		    sizeof(eparent), MEM_READ, CACHE_NONE);
-		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-			unsigned char tmp2;
-			tmp2 = buf[0]; buf[0] = buf[3]; buf[3] = tmp2;
-			tmp2 = buf[1]; buf[1] = buf[2]; buf[2] = tmp2;
-		}
-		epeer   = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
-
-		cpu->memory_rw(cpu, cpu->mem, peeraddr + 1 *
-		    machine->md.arc->wordlen,
-		    &buf[0], sizeof(eparent), MEM_READ, CACHE_NONE);
-		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-			unsigned char tmp2;
-			tmp2 = buf[0]; buf[0] = buf[3]; buf[3] = tmp2;
-			tmp2 = buf[1]; buf[1] = buf[2]; buf[2] = tmp2;
-		}
-		echild  = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
-
-		cpu->memory_rw(cpu, cpu->mem, peeraddr + 2 *
-		    machine->md.arc->wordlen,
-		    &buf[0], sizeof(eparent), MEM_READ, CACHE_NONE);
-		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-			unsigned char tmp2;
-			tmp2 = buf[0]; buf[0] = buf[3]; buf[3] = tmp2;
-			tmp2 = buf[1]; buf[1] = buf[2]; buf[2] = tmp2;
-		}
-		eparent = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
-
-		/*  debug("  epeer=%x echild=%x eparent=%x\n",
-		    (int)epeer,(int)echild,(int)eparent);  */
-
-		if ((uint32_t)eparent == (uint32_t)parent &&
-		    (uint32_t)epeer == 0) {
-			epeer = a;
-			store_32bit_word(cpu, peeraddr + 0x00, epeer);
-			/*  debug("[ addchild: adding 0x%08x as peer "
-			    "to 0x%08x ]\n", (int)a, (int)peeraddr);  */
-		}
-		if ((uint32_t)peeraddr == (uint32_t)parent &&
-		    (uint32_t)echild == 0) {
-			echild = a;
-			store_32bit_word(cpu, peeraddr + 0x04, echild);
-			/*  debug("[ addchild: adding 0x%08x as "
-			    "child to 0x%08x ]\n", (int)a, (int)peeraddr);  */
-		}
-
-		/*  Go to the next component:  */
-		cpu->memory_rw(cpu, cpu->mem, peeraddr + 0x28, &buf[0],
-		    sizeof(eparent), MEM_READ, CACHE_NONE);
-		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-			unsigned char tmp2;
-			tmp2 = buf[0]; buf[0] = buf[3]; buf[3] = tmp2;
-			tmp2 = buf[1]; buf[1] = buf[2]; buf[2] = tmp2;
-		}
-		
-		tmp = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
-		peeraddr += 0x30;
-		peeraddr += tmp + 1;
-		peeraddr = ((peeraddr - 1) | 3) + 1;
-
-		n_left --;
-	}
-
-	store_32bit_word(cpu, a + 0x00, peer);
-	store_32bit_word(cpu, a + 0x04, child);
-	store_32bit_word(cpu, a + 0x08, parent);
-	store_32bit_word(cpu, a+  0x0c, host_tmp_component->Class);
-	store_32bit_word(cpu, a+  0x10, host_tmp_component->Type);
-	store_32bit_word(cpu, a+  0x14, host_tmp_component->Flags +
-	    65536 * host_tmp_component->Version);
-	store_32bit_word(cpu, a+  0x18, host_tmp_component->Revision);
-	store_32bit_word(cpu, a+  0x1c, host_tmp_component->Key);
-	store_32bit_word(cpu, a+  0x20, host_tmp_component->AffinityMask);
-	store_32bit_word(cpu, a+  0x24, host_tmp_component->
-	    ConfigurationDataSize);
-	store_32bit_word(cpu, a+  0x28, host_tmp_component->IdentifierLength);
-	store_32bit_word(cpu, a+  0x2c, host_tmp_component->Identifier);
-
-	machine->md.arc->next_component_address += 0x30;
-
-	if (host_tmp_component->IdentifierLength != 0) {
-		store_32bit_word(cpu, a + 0x2c, a + 0x30);
-		store_string(cpu, a + 0x30, identifier);
-		if (identifier != NULL)
-			machine->md.arc->next_component_address +=
-			    strlen(identifier) + 1;
-	}
-
-	machine->md.arc->next_component_address ++;
-
-	/*  Round up to next 0x4 bytes:  */
-	machine->md.arc->next_component_address =
-	    ((machine->md.arc->next_component_address - 1) | 3) + 1;
-
-	machine->md.arc->n_components ++;
-
-	return a;
-}
-
-
-/*
- *  arcbios_addchild64():
- *
- *  host_tmp_component is a temporary component, with data formated for
- *  the host system.  It needs to be translated/copied into emulated RAM.
- *
- *  Return value is the virtual (emulated) address of the added component.
- *
- *  TODO:  This function doesn't care about memory management, but simply
- *         stores the new child after the last stored child.
- *  TODO:  This stuff is really ugly.
- */
-static uint64_t arcbios_addchild64(struct cpu *cpu,
-	struct arcbios_component64 *host_tmp_component,
-	const char *identifier, uint64_t parent)
-{
-	struct machine *machine = cpu->machine;
-	uint64_t a = machine->md.arc->next_component_address;
-	uint64_t peer=0;
-	uint64_t child=0;
-	int n_left;
-	uint64_t peeraddr = FIRST_ARC_COMPONENT;
-
-	/*
-	 *  This component has no children yet, but it may have peers (that is,
-	 *  other components that share this component's parent) so we have to
-	 *  set the peer value correctly.
-	 *
-	 *  Also, if this is the first child of some parent, the parent's child
-	 *  pointer should be set to point to this component.  (But only if it
-	 *  is the first.)
-	 *
-	 *  This is really ugly:  scan through all components, starting from
-	 *  FIRST_ARC_COMPONENT, to find a component with the same parent as
-	 *  this component will have.  If such a component is found, and its
-	 *  'peer' value is NULL, then set it to this component's address (a).
-	 *
-	 *  TODO:  make this nicer
-	 */
-
-	n_left = machine->md.arc->n_components;
-	while (n_left > 0) {
-		/*  Load parent, child, and peer values:  */
-		uint64_t eparent, echild, epeer, tmp;
-		unsigned char buf[8];
-
-		/*  debug("[ addchild: peeraddr = 0x%016" PRIx64" ]\n",
-		    (uint64_t) peeraddr);  */
-
-		cpu->memory_rw(cpu, cpu->mem,
-		    peeraddr + 0 * machine->md.arc->wordlen, &buf[0],
-		    sizeof(eparent), MEM_READ, CACHE_NONE);
-		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-			unsigned char tmp2;
-			tmp2 = buf[0]; buf[0] = buf[7]; buf[7] = tmp2;
-			tmp2 = buf[1]; buf[1] = buf[6]; buf[6] = tmp2;
-			tmp2 = buf[2]; buf[2] = buf[5]; buf[5] = tmp2;
-			tmp2 = buf[3]; buf[3] = buf[4]; buf[4] = tmp2;
-		}
-		epeer   = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24)
-		    + ((uint64_t)buf[4] << 32) + ((uint64_t)buf[5] << 40)
-		    + ((uint64_t)buf[6] << 48) + ((uint64_t)buf[7] << 56);
-
-		cpu->memory_rw(cpu, cpu->mem, peeraddr + 1 *
-		    machine->md.arc->wordlen,
-		    &buf[0], sizeof(eparent), MEM_READ, CACHE_NONE);
-		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-			unsigned char tmp2;
-			tmp2 = buf[0]; buf[0] = buf[7]; buf[7] = tmp2;
-			tmp2 = buf[1]; buf[1] = buf[6]; buf[6] = tmp2;
-			tmp2 = buf[2]; buf[2] = buf[5]; buf[5] = tmp2;
-			tmp2 = buf[3]; buf[3] = buf[4]; buf[4] = tmp2;
-		}
-		echild  = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24)
-		    + ((uint64_t)buf[4] << 32) + ((uint64_t)buf[5] << 40)
-		    + ((uint64_t)buf[6] << 48) + ((uint64_t)buf[7] << 56);
-
-		cpu->memory_rw(cpu, cpu->mem, peeraddr + 2 *
-		    machine->md.arc->wordlen,
-		    &buf[0], sizeof(eparent), MEM_READ, CACHE_NONE);
-		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-			unsigned char tmp2;
-			tmp2 = buf[0]; buf[0] = buf[7]; buf[7] = tmp2;
-			tmp2 = buf[1]; buf[1] = buf[6]; buf[6] = tmp2;
-			tmp2 = buf[2]; buf[2] = buf[5]; buf[5] = tmp2;
-			tmp2 = buf[3]; buf[3] = buf[4]; buf[4] = tmp2;
-		}
-		eparent = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24)
-		    + ((uint64_t)buf[4] << 32) + ((uint64_t)buf[5] << 40)
-		    + ((uint64_t)buf[6] << 48) + ((uint64_t)buf[7] << 56);
-
-		/*  debug("  epeer=%" PRIx64" echild=%" PRIx64" eparent=%" PRIx64
-		    "\n", (uint64_t) epeer, (uint64_t) echild,
-		    (uint64_t) eparent);  */
-
-		if (eparent == parent && epeer == 0) {
-			epeer = a;
-			store_64bit_word(cpu, peeraddr + 0 *
-			    machine->md.arc->wordlen, epeer);
-			/*  debug("[ addchild: adding 0x%016" PRIx64" as peer "
-			    "to 0x%016" PRIx64" ]\n", (uint64_t) a,
-			    (uint64_t) peeraddr);  */
-		}
-		if (peeraddr == parent && echild == 0) {
-			echild = a;
-			store_64bit_word(cpu, peeraddr + 1 *
-			    machine->md.arc->wordlen, echild);
-			/*  debug("[ addchild: adding 0x%016" PRIx64" as child "
-			    "to 0x%016" PRIx64" ]\n", (uint64_t) a,
-			    (uint64_t) peeraddr);  */
-		}
-
-		/*  Go to the next component:  */
-		cpu->memory_rw(cpu, cpu->mem, peeraddr + 0x34,
-		    &buf[0], sizeof(uint32_t), MEM_READ, CACHE_NONE);
-		if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-			unsigned char tmp2;
-			tmp2 = buf[0]; buf[0] = buf[3]; buf[3] = tmp2;
-			tmp2 = buf[1]; buf[1] = buf[2]; buf[2] = tmp2;
-		}
-		tmp = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
-
-		tmp &= 0xfffff;
-
-		peeraddr += 0x50;
-		peeraddr += tmp + 1;
-		peeraddr = ((peeraddr - 1) | 3) + 1;
-
-		n_left --;
-	}
-
-	store_64bit_word(cpu, a + 0x00, peer);
-	store_64bit_word(cpu, a + 0x08, child);
-	store_64bit_word(cpu, a + 0x10, parent);
-	store_32bit_word(cpu, a+  0x18, host_tmp_component->Class);
-	store_32bit_word(cpu, a+  0x1c, host_tmp_component->Type);
-	store_32bit_word(cpu, a+  0x20, host_tmp_component->Flags);
-	store_32bit_word(cpu, a+  0x24, host_tmp_component->Version +
-	    ((uint64_t)host_tmp_component->Revision << 16));
-	store_32bit_word(cpu, a+  0x28, host_tmp_component->Key);
-	store_64bit_word(cpu, a+  0x30, host_tmp_component->AffinityMask);
-	store_64bit_word(cpu, a+  0x38, host_tmp_component->
-	    ConfigurationDataSize);
-	store_64bit_word(cpu, a+  0x40, host_tmp_component->IdentifierLength);
-	store_64bit_word(cpu, a+  0x48, host_tmp_component->Identifier);
-
-	/*  TODO: Find out how a REAL ARCS64 implementation does it.  */
-
-	machine->md.arc->next_component_address += 0x50;
-
-	if (host_tmp_component->IdentifierLength != 0) {
-		store_64bit_word(cpu, a + 0x48, a + 0x50);
-		store_string(cpu, a + 0x50, identifier);
-		if (identifier != NULL)
-			machine->md.arc->next_component_address +=
-			    strlen(identifier) + 1;
-	}
-
-	machine->md.arc->next_component_address ++;
-
-	/*  Round up to next 0x8 bytes:  */
-	machine->md.arc->next_component_address =
-	    ((machine->md.arc->next_component_address - 1) | 7) + 1;
-
-	machine->md.arc->n_components ++;
-	return a;
-}
-
-
-/*
- *  arcbios_addchild_manual():
- *
- *  Used internally to set up component structures.
- *  Parent may only be NULL for the first (system) component.
- *
- *  Return value is the virtual (emulated) address of the added component.
- */
-uint64_t arcbios_addchild_manual(struct cpu *cpu,
-	uint64_t cclass, uint64_t type, uint64_t flags,
-	uint64_t version, uint64_t revision, uint64_t key,
-	uint64_t affinitymask, const char *identifier, uint64_t parent,
-	void *config_data, size_t config_len)
-{
-	struct machine *machine = cpu->machine;
-	/*  This component is only for temporary use:  */
-	struct arcbios_component component;
-	struct arcbios_component64 component64;
-
-	if (config_data != NULL) {
-		unsigned char *p = (unsigned char *) config_data;
-		size_t i;
-
-		if (machine->md.arc->n_configuration_data >= MAX_CONFIG_DATA) {
-			printf("fatal error: you need to increase "
-			    "MAX_CONFIG_DATA\n");
-			exit(1);
-		}
-
-		for (i=0; i<config_len; i++) {
-			unsigned char ch = p[i];
-			cpu->memory_rw(cpu, cpu->mem,
-			    machine->md.arc->configuration_data_next_addr + i,
-			    &ch, 1, MEM_WRITE, CACHE_NONE);
-		}
-
-		machine->md.arc->configuration_data_len[
-		    machine->md.arc->n_configuration_data] = config_len;
-		machine->md.arc->configuration_data_configdata[
-		    machine->md.arc->n_configuration_data] =
-		    machine->md.arc->configuration_data_next_addr;
-		machine->md.arc->configuration_data_next_addr += config_len;
-		machine->md.arc->configuration_data_component[
-		    machine->md.arc->n_configuration_data] =
-		    machine->md.arc->next_component_address +
-		    (cpu->machine->md.arc->arc_64bit? 0x18 : 0x0c);
-
-		/*  printf("& ADDING %i: configdata=0x%016" PRIx64" "
-		    "component=0x%016" PRIx64"\n",
-		     machine->md.arc->n_configuration_data,
-		    (uint64_t) machine->md.arc->configuration_data_configdata[
-			machine->md.arc->n_configuration_data],
-		    (uint64_t) machine->md.arc->configuration_data_component[
-			machine->md.arc->n_configuration_data]);  */
-
-		machine->md.arc->n_configuration_data ++;
-	}
-
-	if (!cpu->machine->md.arc->arc_64bit) {
-		component.Class                 = cclass;
-		component.Type                  = type;
-		component.Flags                 = flags;
-		component.Version               = version;
-		component.Revision              = revision;
-		component.Key                   = key;
-		component.AffinityMask          = affinitymask;
-		component.ConfigurationDataSize = config_len;
-		component.IdentifierLength      = 0;
-		component.Identifier            = 0;
-		if (identifier != NULL) {
-			component.IdentifierLength = strlen(identifier) + 1;
-		}
-
-		return arcbios_addchild(cpu, &component, identifier, parent);
-	} else {
-		component64.Class                 = cclass;
-		component64.Type                  = type;
-		component64.Flags                 = flags;
-		component64.Version               = version;
-		component64.Revision              = revision;
-		component64.Key                   = key;
-		component64.AffinityMask          = affinitymask;
-		component64.ConfigurationDataSize = config_len;
-		component64.IdentifierLength      = 0;
-		component64.Identifier            = 0;
-		if (identifier != NULL) {
-			component64.IdentifierLength = strlen(identifier) + 1;
-		}
-
-		return arcbios_addchild64(cpu, &component64, identifier,
-		    parent);
-	}
-}
-
-
-/*
- *  arcbios_get_msdos_partition_size():
- *
- *  This function tries to parse MSDOS-style partition tables on a disk
- *  image, and return the starting offset (counted in bytes), and the
- *  size, of a specific partition.
- *
- *  NOTE: partition_nr is 1-based!
- *
- *  TODO: This is buggy, it doesn't really handle extended partitions.
- *
- *  See http://www.nondot.org/sabre/os/files/Partitions/Partitions.html
- *  for more info.
- */
-static void arcbios_get_msdos_partition_size(struct machine *machine,
-	int disk_id, int disk_type, int partition_nr, uint64_t *start,
-	uint64_t *size)
-{
-	int res, i, partition_type, cur_partition = 0;
-	unsigned char sector[512];
-	unsigned char buf[16];
-	uint64_t offset = 0, st;
-
-	/*  Partition 0 is the entire disk image:  */
-	*start = 0;
-	*size = diskimage_getsize(machine, disk_id, disk_type);
-	if (partition_nr == 0)
-		return;
-
-ugly_goto:
-	*start = 0; *size = 0;
-
-	/*  printf("reading MSDOS partition from offset 0x%" PRIx64"\n",
-	    (uint64_t) offset);  */
-
-	res = diskimage_access(machine, disk_id, disk_type, 0, offset,
-	    sector, sizeof(sector));
-	if (!res) {
-		fatal("[ arcbios_get_msdos_partition_size(): couldn't "
-		    "read the disk image, id %i, offset 0x%" PRIx64" ]\n",
-		    disk_id, (uint64_t) offset);
-		return;
-	}
-
-	if (sector[510] != 0x55 || sector[511] != 0xaa) {
-		fatal("[ arcbios_get_msdos_partition_size(): not an "
-		    "MSDOS partition table ]\n");
-	}
-
-#if 0
-	/*  Debug dump:  */
-	for (i=0; i<4; i++) {
-		int j;
-		printf("  partition %i: ", i+1);
-		for (j=0; j<16; j++)
-			printf(" %02x", sector[446 + i*16 + j]);
-		printf("\n");
-	}
-#endif
-
-	for (i=0; i<4; i++) {
-		memmove(buf, sector + 446 + 16*i, 16);
-
-		partition_type = buf[4];
-
-		if (partition_type == 0)
-			continue;
-
-		st = (buf[8] + (buf[9] << 8) + (buf[10] << 16) +
-		    (buf[11] << 24)) * 512;
-
-		if (start != NULL)
-			*start = st;
-		if (size != NULL)
-			*size = (buf[12] + (buf[13] << 8) + (buf[14] << 16) +
-			    (buf[15] << 24)) * 512;
-
-		/*  Extended DOS partition:  */
-		if (partition_type == 5) {
-			offset += st;
-			goto ugly_goto;
-		}
-
-		/*  Found the right partition? Then return.  */
-		cur_partition ++;
-		if (cur_partition == partition_nr)
-			return;
-	}
-
-	fatal("[ partition(%i) NOT found ]\n", partition_nr);
-}
-
-
-/*
- *  arcbios_handle_to_disk_id_and_type():
- */
-static int arcbios_handle_to_disk_id_and_type(struct machine *machine,
-	int handle, int *typep)
-{
-	int id, cdrom;
-	const char *s;
-
-	if (handle < 0 || handle >= ARC_MAX_HANDLES)
-		return -1;
-
-	s = machine->md.arc->file_handle_string[handle];
-	if (s == NULL)
-		return -1;
-
-	/*
-	 *  s is something like "scsi(0)disk(0)rdisk(0)partition(0)".
-	 *  TODO: This is really ugly and hardcoded.
-	 */
-
-	if (strncmp(s, "scsi(", 5) != 0 || strlen(s) < 13)
-		return -1;
-
-	*typep = DISKIMAGE_SCSI;
-
-	cdrom = (s[7] == 'c');
-	id = cdrom? atoi(s + 13) : atoi(s + 12);
-
-	return id;
-}
-
-
-/*
- *  arcbios_handle_to_start_and_size():
- */
-static void arcbios_handle_to_start_and_size(struct machine *machine,
-	int handle, uint64_t *start, uint64_t *size)
-{
-	const char *s = machine->md.arc->file_handle_string[handle];
-	const char *s2;
-	int disk_id, disk_type;
-
-	disk_id = arcbios_handle_to_disk_id_and_type(machine,
-	    handle, &disk_type);
-
-	if (disk_id < 0)
-		return;
-
-	/*  This works for "partition(0)":  */
-	*start = 0;
-	*size = diskimage_getsize(machine, disk_id, disk_type);
-
-	s2 = strstr(s, "partition(");
-	if (s2 != NULL) {
-		int partition_nr = atoi(s2 + 10);
-		/*  printf("partition_nr = %i\n", partition_nr);  */
-		if (partition_nr != 0)
-			arcbios_get_msdos_partition_size(machine,
-			    disk_id, disk_type, partition_nr, start, size);
-	}
-}
-
-
-/*
- *  arcbios_getfileinformation():
- *
- *  Fill in a GetFileInformation struct in emulated memory,
- *  for a specific file handle. (This is used to get the size
- *  and offsets of partitions on disk images.)
- */
-static int arcbios_getfileinformation(struct cpu *cpu)
-{
-	int handle = cpu->cd.mips.gpr[MIPS_GPR_A0];
-	uint64_t addr = cpu->cd.mips.gpr[MIPS_GPR_A1];
-	uint64_t start, size;
-
-	arcbios_handle_to_start_and_size(cpu->machine, handle, &start, &size);
-
-	store_64bit_word(cpu, addr + 0, 0);
-	store_64bit_word(cpu, addr + 8, size);
-	store_64bit_word(cpu, addr + 16, 0);
-	store_32bit_word(cpu, addr + 24, 1);
-	store_32bit_word(cpu, addr + 28, 0);
-	store_32bit_word(cpu, addr + 32, 0);
-
-	/*  printf("\n!!! size=0x%x start=0x%x\n", (int)size, (int)start);  */
-
-	return ARCBIOS_ESUCCESS;
-}
-
-
-/*
- *  arcbios_private_emul():
- *
- *  TODO:  This is probably SGI specific. (?)
- *
- *	0x04	get nvram table
- */
-void arcbios_private_emul(struct cpu *cpu)
-{
-	int vector = cpu->pc & 0xfff;
-
-	switch (vector) {
-	case 0x04:
-		debug("[ ARCBIOS PRIVATE get nvram table(): TODO ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	default:
-		cpu_register_dump(cpu->machine, cpu, 1, 0x1);
-		debug("a0 points to: ");
-		dump_mem_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0]);
-		debug("\n");
-		fatal("ARCBIOS: unimplemented PRIVATE vector 0x%x\n", vector);
-		cpu->running = 0;
-	}
-}
-
-
-/*
- *  arcbios_emul():  ARCBIOS emulation
- *
- *	0x0c	Halt()
- *	0x10	PowerDown()
- *	0x14	Restart()
- *	0x18	Reboot()
- *	0x1c	EnterInteractiveMode()
- *	0x20	ReturnFromMain()
- *	0x24	GetPeer(node)
- *	0x28	GetChild(node)
- *	0x2c	GetParent(node)
- *	0x30	GetConfigurationData(config_data, node)
- *	0x3c	GetComponent(name)
- *	0x44	GetSystemId()
- *	0x48	GetMemoryDescriptor(void *)
- *	0x50	GetTime()
- *	0x54	GetRelativeTime()
- *	0x5c	Open(path, mode, &fileid)
- *	0x60	Close(handle)
- *	0x64	Read(handle, &buf, len, &actuallen)
- *	0x6c	Write(handle, buf, len, &returnlen)
- *	0x70	Seek(handle, &offset, len)
- *	0x78	GetEnvironmentVariable(char *)
- *	0x7c	SetEnvironmentVariable(char *, char *)
- *	0x80	GetFileInformation(handle, buf)
- *	0x88	FlushAllCaches()
- *	0x90	GetDisplayStatus(uint32_t handle)
- *	0x100	undocumented IRIX (?)
- */
-int arcbios_emul(struct cpu *cpu)
-{
-	struct machine *machine = cpu->machine;
-	int vector = cpu->pc & 0xfff;
-	int i, j, handle;
-	unsigned char ch2;
-	unsigned char buf[40];
-
-	if (cpu->pc >= ARC_PRIVATE_ENTRIES &&
-	    cpu->pc < ARC_PRIVATE_ENTRIES + 100*sizeof(uint32_t)) {
-		arcbios_private_emul(cpu);
-		return 1;
-	}
-
-	if (machine->md.arc->arc_64bit)
-		vector /= 2;
-
-	/*  Special case for reboot by jumping to 0xbfc00000:  */
-	if (vector == 0 && (cpu->pc & 0xffffffffULL) == 0xbfc00000ULL)
-		vector = 0x18;
-
-	switch (vector) {
-	case 0x0c:		/*  Halt()  */
-	case 0x10:		/*  PowerDown()  */
-	case 0x14:		/*  Restart()  */
-	case 0x18:		/*  Reboot()  */
-	case 0x1c:		/*  EnterInteractiveMode()  */
-	case 0x20:		/*  ReturnFromMain()  */
-		debug("[ ARCBIOS Halt() or similar ]\n");
-		/*  Halt all CPUs.  */
-		for (i=0; i<machine->ncpus; i++) {
-			machine->cpus[i]->running = 0;
-		}
-		machine->exit_without_entering_debugger = 1;
-		break;
-	case 0x24:		/*  GetPeer(node)  */
-		if (cpu->cd.mips.gpr[MIPS_GPR_A0] == 0) {
-			/*  NULL ptr argument: return NULL.  */
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		} else {
-			uint64_t peer;
-			cpu->memory_rw(cpu, cpu->mem,
-			    cpu->cd.mips.gpr[MIPS_GPR_A0] - 3 *
-			    machine->md.arc->wordlen, &buf[0],
-			    machine->md.arc->wordlen, MEM_READ, CACHE_NONE);
-			if (machine->md.arc->arc_64bit) {
-				if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-					unsigned char tmp; tmp = buf[0];
-					buf[0] = buf[7]; buf[7] = tmp;
-					tmp = buf[1]; buf[1] = buf[6];
-					buf[6] = tmp;
-					tmp = buf[2]; buf[2] = buf[5];
-					buf[5] = tmp;
-					tmp = buf[3]; buf[3] = buf[4];
-					buf[4] = tmp;
-				}
-				peer = (uint64_t)buf[0] + ((uint64_t)buf[1]<<8)
-				    + ((uint64_t)buf[2]<<16)
-				    + ((uint64_t)buf[3]<<24)
-				    + ((uint64_t)buf[4]<<32)
-				    + ((uint64_t)buf[5]<<40)
-				    + ((uint64_t)buf[6]<<48)
-				    + ((uint64_t)buf[7]<<56);
-			} else {
-				if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-					unsigned char tmp; tmp = buf[0];
-					buf[0] = buf[3]; buf[3] = tmp;
-					tmp = buf[1]; buf[1] = buf[2];
-					buf[2] = tmp;
-				}
-				peer = buf[0] + (buf[1]<<8) + (buf[2]<<16)
-				    + (buf[3]<<24);
-			}
-
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = peer?
-			    (peer + 3 * machine->md.arc->wordlen) : 0;
-			if (!machine->md.arc->arc_64bit)
-				cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)
-				    (int32_t) cpu->cd.mips.gpr[MIPS_GPR_V0];
-		}
-		debug("[ ARCBIOS GetPeer(node 0x%016" PRIx64"): 0x%016" PRIx64
-		    " ]\n", (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
-		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_V0]);
-		break;
-	case 0x28:		/*  GetChild(node)  */
-		/*  0 for the root, non-0 for children:  */
-		if (cpu->cd.mips.gpr[MIPS_GPR_A0] == 0)
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = FIRST_ARC_COMPONENT
-			    + machine->md.arc->wordlen * 3;
-		else {
-			uint64_t child = 0;
-			cpu->memory_rw(cpu, cpu->mem,
-			    cpu->cd.mips.gpr[MIPS_GPR_A0] - 2 *
-			    machine->md.arc->wordlen, &buf[0], machine->
-			    md.arc->wordlen, MEM_READ, CACHE_NONE);
-			if (machine->md.arc->arc_64bit) {
-				if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-					unsigned char tmp; tmp = buf[0];
-					buf[0] = buf[7]; buf[7] = tmp;
-					tmp = buf[1]; buf[1] = buf[6];
-					buf[6] = tmp;
-					tmp = buf[2]; buf[2] = buf[5];
-					buf[5] = tmp;
-					tmp = buf[3]; buf[3] = buf[4];
-					buf[4] = tmp;
-				}
-				child = (uint64_t)buf[0] +
-				    ((uint64_t)buf[1]<<8) +
-				    ((uint64_t)buf[2]<<16) +
-				    ((uint64_t)buf[3]<<24) +
-				    ((uint64_t)buf[4]<<32) +
-				    ((uint64_t)buf[5]<<40) +
-				    ((uint64_t)buf[6]<<48) +
-				    ((uint64_t)buf[7]<<56);
-			} else {
-				if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-					unsigned char tmp; tmp = buf[0];
-					buf[0] = buf[3]; buf[3] = tmp;
-					tmp = buf[1]; buf[1] = buf[2];
-					buf[2] = tmp;
-				}
-				child = buf[0] + (buf[1]<<8) + (buf[2]<<16) +
-				    (buf[3]<<24);
-			}
-
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = child?
-			    (child + 3 * machine->md.arc->wordlen) : 0;
-			if (!machine->md.arc->arc_64bit)
-				cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)
-				    (int32_t)cpu->cd.mips.gpr[MIPS_GPR_V0];
-		}
-		debug("[ ARCBIOS GetChild(node 0x%016" PRIx64"): 0x%016"
-		    PRIx64" ]\n", (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
-		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_V0]);
-		break;
-	case 0x2c:		/*  GetParent(node)  */
-		{
-			uint64_t parent;
-
-			cpu->memory_rw(cpu, cpu->mem,
-			    cpu->cd.mips.gpr[MIPS_GPR_A0] - 1 * machine->
-			    md.arc->wordlen, &buf[0], machine->md.arc->wordlen,
-			    MEM_READ, CACHE_NONE);
-
-			if (machine->md.arc->arc_64bit) {
-				if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-					unsigned char tmp; tmp = buf[0];
-					buf[0] = buf[7]; buf[7] = tmp;
-					tmp = buf[1]; buf[1] = buf[6];
-					buf[6] = tmp;
-					tmp = buf[2]; buf[2] = buf[5];
-					buf[5] = tmp;
-					tmp = buf[3]; buf[3] = buf[4];
-					buf[4] = tmp;
-				}
-				parent = (uint64_t)buf[0] +
-				    ((uint64_t)buf[1]<<8) +
-				    ((uint64_t)buf[2]<<16) +
-				    ((uint64_t)buf[3]<<24) +
-				    ((uint64_t)buf[4]<<32) +
-				    ((uint64_t)buf[5]<<40) +
-				    ((uint64_t)buf[6]<<48) +
-				    ((uint64_t)buf[7]<<56);
-			} else {
-				if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-					unsigned char tmp; tmp = buf[0];
-					buf[0] = buf[3]; buf[3] = tmp;
-					tmp = buf[1]; buf[1] = buf[2];
-					buf[2] = tmp;
-				}
-				parent = buf[0] + (buf[1]<<8) +
-				    (buf[2]<<16) + (buf[3]<<24);
-			}
-
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = parent?
-			    (parent + 3 * machine->md.arc->wordlen) : 0;
-			if (!machine->md.arc->arc_64bit)
-				cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)
-				    (int32_t) cpu->cd.mips.gpr[MIPS_GPR_V0];
-		}
-		debug("[ ARCBIOS GetParent(node 0x%016" PRIx64"): 0x%016"
-		    PRIx64" ]\n", (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
-		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_V0]);
-		break;
-	case 0x30:  /*  GetConfigurationData(void *configdata, void *node)  */
-		/*  fatal("[ ARCBIOS GetConfigurationData(0x%016" PRIx64","
-		    "0x%016" PRIx64") ]\n",
-		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
-		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1]);  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EINVAL;
-		for (i=0; i<machine->md.arc->n_configuration_data; i++) {
-			/*  fatal("configuration_data_component[%i] = "
-			    "0x%016" PRIx64"\n", i, (uint64_t) machine->
-			    md.arc->configuration_data_component[i]);  */
-			if (cpu->cd.mips.gpr[MIPS_GPR_A1] ==
-			    machine->md.arc->configuration_data_component[i]) {
-				cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-				for (j=0; j<machine->
-				    md.arc->configuration_data_len[i]; j++) {
-					unsigned char ch;
-					cpu->memory_rw(cpu, cpu->mem,
-					    machine->md.arc->
-					    configuration_data_configdata[i] +
-					    j, &ch, 1, MEM_READ, CACHE_NONE);
-					cpu->memory_rw(cpu, cpu->mem,
-					    cpu->cd.mips.gpr[MIPS_GPR_A0] + j,
-					    &ch, 1, MEM_WRITE, CACHE_NONE);
-				}
-				break;
-			}
-		}
-		break;
-	case 0x3c:		/*  GetComponent(char *name)  */
-		debug("[ ARCBIOS GetComponent(\"");
-		dump_mem_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0]);
-		debug("\") ]\n");
-
-		if (cpu->cd.mips.gpr[MIPS_GPR_A0] == 0) {
-			fatal("[ ARCBIOS GetComponent: NULL ptr ]\n");
-		} else {
-			unsigned char buf2[500];
-			int match_index = -1;
-			int match_len = 0;
-
-			memset(buf2, 0, sizeof(buf2));
-			for (i=0; i<(ssize_t)sizeof(buf2); i++) {
-				cpu->memory_rw(cpu, cpu->mem,
-				    cpu->cd.mips.gpr[MIPS_GPR_A0] + i,
-				    &buf2[i], 1, MEM_READ, CACHE_NONE);
-				if (buf2[i] == '\0')
-					i = sizeof(buf);
-			}
-			buf2[sizeof(buf2) - 1] = '\0';
-
-			/*  "scsi(0)disk(0)rdisk(0)partition(0)" and such.  */
-			/*  printf("GetComponent(\"%s\")\n", buf2);  */
-
-			/*  Default to NULL return value.  */
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-
-			/*  Scan the string to component table:  */
-			for (i=0; i<machine->md.arc->n_string_to_components;
-			    i++) {
-				int m = 0;
-				while (buf2[m] && machine->md.arc->
-				    string_to_component[i][m] &&
-				    machine->md.arc->string_to_component[i][m]
-				    == buf2[m])
-					m++;
-				if (m > match_len) {
-					match_len = m;
-					match_index = i;
-				}
-			}
-
-			if (match_index >= 0) {
-				/*  printf("Longest match: '%s'\n",
-				    machine->md.arc->string_to_component[
-				    match_index]);  */
-				cpu->cd.mips.gpr[MIPS_GPR_V0] =
-				    machine->md.arc->string_to_component_value[
-				    match_index];
-			}
-		}
-		break;
-	case 0x44:		/*  GetSystemId()  */
-		debug("[ ARCBIOS GetSystemId() ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = SGI_SYSID_ADDR;
-		break;
-	case 0x48:		/*  void *GetMemoryDescriptor(void *ptr)  */
-		debug("[ ARCBIOS GetMemoryDescriptor(0x%08x) ]\n",
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
-
-		/*  If a0=NULL, then return the first descriptor:  */
-		if ((uint32_t)cpu->cd.mips.gpr[MIPS_GPR_A0] == 0)
-			cpu->cd.mips.gpr[MIPS_GPR_V0] =
-			    machine->md.arc->memdescriptor_base;
-		else {
-			int s = machine->md.arc->arc_64bit?
-			    sizeof(struct arcbios_mem64)
-			    : sizeof(struct arcbios_mem);
-			int nr = cpu->cd.mips.gpr[MIPS_GPR_A0] -
-			    machine->md.arc->memdescriptor_base;
-			nr /= s;
-			nr ++;
-			cpu->cd.mips.gpr[MIPS_GPR_V0] =
-			    machine->md.arc->memdescriptor_base + s * nr;
-			if (nr >= machine->md.arc->n_memdescriptors)
-				cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		}
-		break;
-	case 0x50:		/*  GetTime()  */
-		debug("[ ARCBIOS GetTime() ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0xffffffff80001000ULL;
-		/*  TODO!  */
-		break;
-	case 0x54:		/*  GetRelativeTime()  */
-		debug("[ ARCBIOS GetRelativeTime() ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)(int32_t)time(NULL);
-		break;
-	case 0x5c:  /*  Open(char *path, uint32_t mode, uint32_t *fileID)  */
-		debug("[ ARCBIOS Open(\"");
-		dump_mem_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0]);
-		debug("\",0x%x,0x%x)", (int)cpu->cd.mips.gpr[MIPS_GPR_A0],
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A1],
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A2]);
-
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_ENOENT;
-
-		handle = 3;
-		/*  TODO: Starting at 0 would require some updates...  */
-		while (machine->md.arc->file_handle_in_use[handle]) {
-			handle ++;
-			if (handle >= ARC_MAX_HANDLES) {
-				cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EMFILE;
-				break;
-			}
-		}
-
-		if (handle >= ARC_MAX_HANDLES) {
-			fatal("[ ARCBIOS Open: out of file handles ]\n");
-		} else if (cpu->cd.mips.gpr[MIPS_GPR_A0] == 0) {
-			fatal("[ ARCBIOS Open: NULL ptr ]\n");
-		} else {
-			/*
-			 *  TODO: This is hardcoded to successfully open
-			 *  anything. It is used by the Windows NT SETUPLDR
-			 *  program to load stuff from the boot partition.
-			 */
-			unsigned char *buf2;
-			CHECK_ALLOCATION(buf2 = (unsigned char *) malloc(MAX_OPEN_STRINGLEN));
-			memset(buf2, 0, MAX_OPEN_STRINGLEN);
-			for (i=0; i<MAX_OPEN_STRINGLEN; i++) {
-				cpu->memory_rw(cpu, cpu->mem,
-				    cpu->cd.mips.gpr[MIPS_GPR_A0] + i,
-				    &buf2[i], 1, MEM_READ, CACHE_NONE);
-				if (buf2[i] == '\0')
-					i = MAX_OPEN_STRINGLEN;
-			}
-			buf2[MAX_OPEN_STRINGLEN - 1] = '\0';
-			machine->md.arc->file_handle_string[handle] =
-			    (char *)buf2;
-			machine->md.arc->current_seek_offset[handle] = 0;
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_ESUCCESS;
-		}
-
-		if (cpu->cd.mips.gpr[MIPS_GPR_V0] == ARCBIOS_ESUCCESS) {
-			debug(" = handle %i ]\n", (int)handle);
-			store_32bit_word(cpu, cpu->cd.mips.gpr[MIPS_GPR_A2],
-			    handle);
-			machine->md.arc->file_handle_in_use[handle] = 1;
-		} else
-			debug(" = ERROR %i ]\n",
-			    (int)cpu->cd.mips.gpr[MIPS_GPR_V0]);
-		break;
-	case 0x60:		/*  Close(uint32_t handle)  */
-		debug("[ ARCBIOS Close(%i) ]\n",
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
-		if (!machine->md.arc->file_handle_in_use[cpu->cd.mips.gpr[
-		    MIPS_GPR_A0]]) {
-			fatal("ARCBIOS Close(%i): bad handle\n",
-			    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EBADF;
-		} else {
-			machine->md.arc->file_handle_in_use[
-			    cpu->cd.mips.gpr[MIPS_GPR_A0]] = 0;
-			// TODO: Yes, this is a memory leak. But it will be
-			// scrapped in favor of real code after the rewrite (I
-			// hope).
-			//if (machine->md.arc->file_handle_string[
-			//    cpu->cd.mips.gpr[MIPS_GPR_A0]] != NULL)
-			//	free(machine->md.arc->file_handle_string[
-			//	    cpu->cd.mips.gpr[MIPS_GPR_A0]]);
-			machine->md.arc->file_handle_string[cpu->cd.mips.
-			    gpr[MIPS_GPR_A0]] = NULL;
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_ESUCCESS;
-		}
-		break;
-	case 0x64:  /*  Read(handle, void *buf, length, uint32_t *count)  */
-		if (cpu->cd.mips.gpr[MIPS_GPR_A0] == ARCBIOS_STDIN) {
-			int j2, nread = 0, a2;
-
-			/*
-			 *  Before going into the loop, make sure stdout
-			 *  is flushed.  If we're using an X11 VGA console,
-			 *  then it needs to be flushed as well.
-			 */
-			fflush(stdin);
-			fflush(stdout);
-			/*  NOTE/TODO: This gives a tick to _everything_  */
-			for (j2=0; j2<machine->tick_functions.n_entries; j2++)
-				machine->tick_functions.f[j2](cpu,
-				    machine->tick_functions.extra[j2]);
-
-			a2 = cpu->cd.mips.gpr[MIPS_GPR_A2];
-			for (j2=0; j2<a2; j2++) {
-				int x;
-				unsigned char ch;
-
-				/*  Read from STDIN is blocking (at least
-				    that seems to be how NetBSD's arcdiag
-				    wants it)  */
-				x = console_readchar(
-				    machine->main_console_handle);
-				if (x < 0)
-					return 0;
-
-				/*
-				 *  ESC + '[' should be transformed into 0x9b:
-				 *
-				 *  NOTE/TODO: This makes the behaviour of just
-				 *  pressing ESC a bit harder to define.
-				 */
-				if (x == 27) {
-					x = console_readchar(cpu->
-					    machine->main_console_handle);
-					if (x == '[' || x == 'O')
-						x = 0x9b;
-				}
-
-				ch = x;
-				nread ++;
-				cpu->memory_rw(cpu, cpu->mem,
-				    cpu->cd.mips.gpr[MIPS_GPR_A1] + j2,
-				    &ch, 1, MEM_WRITE, CACHE_NONE);
-
-				/*  NOTE: Only one char, from STDIN:  */
-				j2 = cpu->cd.mips.gpr[MIPS_GPR_A2];  /*  :-)  */
-			}
-			
-			store_32bit_word(cpu, cpu->cd.mips.gpr[MIPS_GPR_A3],
-			    nread);
-			/*  TODO: not EAGAIN?  */
-			cpu->cd.mips.gpr[MIPS_GPR_V0] =
-			    nread? ARCBIOS_ESUCCESS: ARCBIOS_EAGAIN;
-		} else {
-			int handleTmp = cpu->cd.mips.gpr[MIPS_GPR_A0];
-			int disk_type = 0;
-			int disk_id = arcbios_handle_to_disk_id_and_type(
-			    machine, handleTmp, &disk_type);
-			uint64_t partition_offset = 0;
-			int res;
-			uint64_t size;		/*  dummy  */
-			unsigned char *tmp_buf;
-
-			arcbios_handle_to_start_and_size(machine, handleTmp,
-			    &partition_offset, &size);
-
-			debug("[ ARCBIOS Read(%i,0x%08x,0x%08x,0x%08x) ]\n",
-			    (int)cpu->cd.mips.gpr[MIPS_GPR_A0],
-			    (int)cpu->cd.mips.gpr[MIPS_GPR_A1],
-			    (int)cpu->cd.mips.gpr[MIPS_GPR_A2],
-			    (int)cpu->cd.mips.gpr[MIPS_GPR_A3]);
-
-			CHECK_ALLOCATION(tmp_buf = (unsigned char *)
-			    malloc(cpu->cd.mips.gpr[MIPS_GPR_A2]));
-
-			res = diskimage_access(machine, disk_id, disk_type,
-			    0, partition_offset + machine->md.arc->
-			    current_seek_offset[handleTmp], tmp_buf,
-			    cpu->cd.mips.gpr[MIPS_GPR_A2]);
-
-			/*  If the transfer was successful, transfer the
-			    data to emulated memory:  */
-			if (res) {
-				uint64_t dst = cpu->cd.mips.gpr[MIPS_GPR_A1];
-				store_buf(cpu, dst, (char *)tmp_buf,
-				    cpu->cd.mips.gpr[MIPS_GPR_A2]);
-				store_32bit_word(cpu,
-				    cpu->cd.mips.gpr[MIPS_GPR_A3],
-				    cpu->cd.mips.gpr[MIPS_GPR_A2]);
-				machine->md.arc->current_seek_offset[handleTmp] +=
-				    cpu->cd.mips.gpr[MIPS_GPR_A2];
-				cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-			} else
-				cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EIO;
-			free(tmp_buf);
-		}
-		break;
-	case 0x68:		/*  GetReadStatus(handle)  */
-		/*
-		 *  According to arcbios_tty_getchar() in NetBSD's
-		 *  dev/arcbios/arcbios_tty.c, GetReadStatus should
-		 *  return 0 if there is something available.
-		 *
-		 *  TODO: Error codes are things like ARCBIOS_EAGAIN.
-		 */
-		if (cpu->cd.mips.gpr[MIPS_GPR_A0] == ARCBIOS_STDIN) {
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = console_charavail(
-			    machine->main_console_handle)? 0 : 1;
-		} else {
-			fatal("[ ARCBIOS GetReadStatus(%i) from "
-			    "something other than STDIN: TODO ]\n",
-			    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
-			/*  TODO  */
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = 1;
-		}
-		break;
-	case 0x6c:		/*  Write(handle, buf, len, &returnlen)  */
-		if (cpu->cd.mips.gpr[MIPS_GPR_A0] != ARCBIOS_STDOUT) {
-			/*
-			 *  TODO: this is just a test
-			 */
-			int handleTmp = cpu->cd.mips.gpr[MIPS_GPR_A0];
-			int disk_type = 0;
-			int disk_id = arcbios_handle_to_disk_id_and_type(
-			    machine, handleTmp, &disk_type);
-			uint64_t partition_offset = 0;
-			int res, tmpi;
-			uint64_t size;		/*  dummy  */
-			unsigned char *tmp_buf;
-
-			arcbios_handle_to_start_and_size(machine,
-			    handleTmp, &partition_offset, &size);
-
-			debug("[ ARCBIOS Write(%i,0x%08" PRIx64",%i,0x%08"
-			    PRIx64") ]\n", (int) cpu->cd.mips.gpr[MIPS_GPR_A0],
-			    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1],
-			    (int) cpu->cd.mips.gpr[MIPS_GPR_A2],
-			    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A3]);
-
-			CHECK_ALLOCATION(tmp_buf = (unsigned char *)
-			    malloc(cpu->cd.mips.gpr[MIPS_GPR_A2]));
-
-			for (tmpi=0; tmpi<(int32_t)cpu->cd.mips.gpr[MIPS_GPR_A2]; tmpi++)
-				cpu->memory_rw(cpu, cpu->mem,
-				    cpu->cd.mips.gpr[MIPS_GPR_A1] + tmpi,
-				    &tmp_buf[tmpi], sizeof(char), MEM_READ,
-				    CACHE_NONE);
-
-			res = diskimage_access(machine, disk_id, disk_type,
-			    1, partition_offset + machine->md.arc->
-			    current_seek_offset[handleTmp], tmp_buf,
-			    cpu->cd.mips.gpr[MIPS_GPR_A2]);
-
-			if (res) {
-				store_32bit_word(cpu,
-				    cpu->cd.mips.gpr[MIPS_GPR_A3],
-				    cpu->cd.mips.gpr[MIPS_GPR_A2]);
-				machine->md.arc->current_seek_offset[handleTmp] +=
-				    cpu->cd.mips.gpr[MIPS_GPR_A2];
-				cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-			} else
-				cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EIO;
-			free(tmp_buf);
-		} else {
-			for (i=0; i<(int32_t)cpu->cd.mips.gpr[MIPS_GPR_A2];
-			    i++) {
-				unsigned char ch = '\0';
-				cpu->memory_rw(cpu, cpu->mem,
-				    cpu->cd.mips.gpr[MIPS_GPR_A1] + i,
-				    &ch, sizeof(ch), MEM_READ, CACHE_NONE);
-
-				arcbios_putchar(cpu, ch);
-			}
-		}
-		store_32bit_word(cpu, cpu->cd.mips.gpr[MIPS_GPR_A3],
-		    cpu->cd.mips.gpr[MIPS_GPR_A2]);
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;	/*  Success.  */
-		break;
-	case 0x70:	/*  Seek(uint32_t handle, int64_t *ofs,
-				 uint32_t whence): uint32_t  */
-		debug("[ ARCBIOS Seek(%i,0x%08" PRIx64",%i): ",
-		    (int) cpu->cd.mips.gpr[MIPS_GPR_A0],
-		    (uint64_t)cpu->cd.mips.gpr[MIPS_GPR_A1],
-		    (int) cpu->cd.mips.gpr[MIPS_GPR_A2]);
-
-		if (cpu->cd.mips.gpr[MIPS_GPR_A2] != 0) {
-			fatal("[ ARCBIOS Seek(%i,0x%08" PRIx64",%i): "
-			    "UNIMPLEMENTED whence=%i ]\n",
-			    (int) cpu->cd.mips.gpr[MIPS_GPR_A0],
-			    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1],
-			    (int) cpu->cd.mips.gpr[MIPS_GPR_A2],
-			    (int) cpu->cd.mips.gpr[MIPS_GPR_A2]);
-		}
-
-		{
-			unsigned char bufTmp[8];
-			uint64_t ofs;
-			cpu->memory_rw(cpu, cpu->mem,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1], &bufTmp[0],
-			    sizeof(bufTmp), MEM_READ, CACHE_NONE);
-			if (cpu->byte_order == EMUL_BIG_ENDIAN) {
-				unsigned char tmp;
-				tmp = bufTmp[0]; bufTmp[0] = bufTmp[7]; bufTmp[7] = tmp;
-				tmp = bufTmp[1]; bufTmp[1] = bufTmp[6]; bufTmp[6] = tmp;
-				tmp = bufTmp[2]; bufTmp[2] = bufTmp[5]; bufTmp[5] = tmp;
-				tmp = bufTmp[3]; bufTmp[3] = bufTmp[4]; bufTmp[4] = tmp;
-			}
-			ofs = bufTmp[0] + (bufTmp[1] << 8) + (bufTmp[2] << 16) +
-			    (bufTmp[3] << 24) + ((uint64_t)bufTmp[4] << 32) +
-			    ((uint64_t)bufTmp[5] << 40) + ((uint64_t)bufTmp[6] << 48)
-			    + ((uint64_t)bufTmp[7] << 56);
-			    
-			machine->md.arc->current_seek_offset[
-			    cpu->cd.mips.gpr[MIPS_GPR_A0]] = ofs;
-			debug("%016" PRIx64" ]\n", (uint64_t) ofs);
-		}
-
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;	/*  Success.  */
-
-		break;
-	case 0x78:		/*  GetEnvironmentVariable(char *)  */
-		/*  Find the environment variable given by a0:  */
-		for (i=0; i<(ssize_t)sizeof(buf); i++)
-			cpu->memory_rw(cpu, cpu->mem,
-			    cpu->cd.mips.gpr[MIPS_GPR_A0] + i,
-			    &buf[i], sizeof(char), MEM_READ, CACHE_NONE);
-		buf[sizeof(buf)-1] = '\0';
-		debug("[ ARCBIOS GetEnvironmentVariable(\"%s\") ]\n", buf);
-		for (i=0; i<0x1000; i++) {
-			/*  Matching string at offset i?  */
-			int nmatches = 0;
-			uint64_t envptr = machine->machine_type == MACHINE_SGI ? ARC_ENV_STRINGS_SGI : ARC_ENV_STRINGS;
-			for (j=0; j<(ssize_t)strlen((char *)buf); j++) {
-				cpu->memory_rw(cpu, cpu->mem,
-				    (uint64_t)(envptr + i + j),
-				    &ch2, sizeof(char), MEM_READ, CACHE_NONE);
-				if (ch2 == buf[j])
-					nmatches++;
-			}
-			cpu->memory_rw(cpu, cpu->mem,
-			    (uint64_t)(envptr + i +
-			    strlen((char *)buf)), &ch2, sizeof(char),
-			    MEM_READ, CACHE_NONE);
-			if (nmatches == (int)strlen((char *)buf) && ch2=='=') {
-				cpu->cd.mips.gpr[MIPS_GPR_V0] =
-				    envptr + i +
-				    strlen((char *)buf) + 1;
-				return 1;
-			}
-		}
-		/*  Return NULL if string wasn't found.  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0x7c:		/*  SetEnvironmentVariable(char *, char *)  */
-		debug("[ ARCBIOS SetEnvironmentVariable(\"");
-		dump_mem_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0]);
-		debug("\",\"");
-		dump_mem_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A1]);
-		debug("\") ]\n");
-		/*  TODO: This is a dummy.  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_ESUCCESS;
-		break;
-	case 0x80:		/*  GetFileInformation()  */
-		debug("[ ARCBIOS GetFileInformation(%i,0x%x): ",
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0],
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A1]);
-
-		if (cpu->cd.mips.gpr[MIPS_GPR_A0] >= ARC_MAX_HANDLES) {
-			debug("invalid file handle ]\n");
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EINVAL;
-		} else if (!machine->md.arc->file_handle_in_use[cpu->cd.
-		    mips.gpr[MIPS_GPR_A0]]) {
-			debug("file handle not in use! ]\n");
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EBADF;
-		} else {
-			debug("'%s' ]\n", machine->md.arc->file_handle_string[
-			    cpu->cd.mips.gpr[MIPS_GPR_A0]]);
-			cpu->cd.mips.gpr[MIPS_GPR_V0] =
-			    arcbios_getfileinformation(cpu);
-		}
-		break;
-	case 0x88:		/*  FlushAllCaches()  */
-		debug("[ ARCBIOS FlushAllCaches(): TODO ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0x90:		/*  void *GetDisplayStatus(handle)  */
-		debug("[ ARCBIOS GetDisplayStatus(%i) ]\n",
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
-		/*  TODO:  handle different values of 'handle'?  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = ARC_DSPSTAT_ADDR;
-		break;
-	case 0x100:
-		/*
-		 *  Undocumented, used by IRIX.
-		 */
-		debug("[ ARCBIOS: IRIX 0x100 (?) ]\n");
-		/*  TODO  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0x888:
-		/*
-		 *  Magical crash if there is no exception handling code.
-		 */
-		fatal("EXCEPTION, but no exception handler installed yet.\n");
-		quiet_mode = 0;
-		cpu_register_dump(machine, cpu, 1, 0x1);
-		cpu->running = 0;
-		break;
-	default:
-		quiet_mode = 0;
-		cpu_register_dump(machine, cpu, 1, 0x1);
-		debug("a0 points to: ");
-		dump_mem_string(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0]);
-		debug("\n");
-		fatal("ARCBIOS: unimplemented vector 0x%x\n", vector);
-		cpu->running = 0;
-	}
-
-	return 1;
-}
-
-
-/*
- *  arcbios_set_default_exception_handler():
- */
-void arcbios_set_default_exception_handler(struct cpu *cpu)
-{
-	/*
-	 *  The default exception handlers simply jump to 0xbfc88888,
-	 *  which is then taken care of in arcbios_emul() above.
-	 *
-	 *  3c1abfc8        lui     k0,0xbfc8
-	 *  375a8888        ori     k0,k0,0x8888
-	 *  03400008        jr      k0
-	 *  00000000        nop
-	 */
-	store_32bit_word(cpu, 0xffffffff80000000ULL, 0x3c1abfc8);
-	store_32bit_word(cpu, 0xffffffff80000004ULL, 0x375a8888);
-	store_32bit_word(cpu, 0xffffffff80000008ULL, 0x03400008);
-	store_32bit_word(cpu, 0xffffffff8000000cULL, 0x00000000);
-
-	store_32bit_word(cpu, 0xffffffff80000080ULL, 0x3c1abfc8);
-	store_32bit_word(cpu, 0xffffffff80000084ULL, 0x375a8888);
-	store_32bit_word(cpu, 0xffffffff80000088ULL, 0x03400008);
-	store_32bit_word(cpu, 0xffffffff8000008cULL, 0x00000000);
-
-	store_32bit_word(cpu, 0xffffffff80000180ULL, 0x3c1abfc8);
-	store_32bit_word(cpu, 0xffffffff80000184ULL, 0x375a8888);
-	store_32bit_word(cpu, 0xffffffff80000188ULL, 0x03400008);
-	store_32bit_word(cpu, 0xffffffff8000018cULL, 0x00000000);
-}
-
-
-/*
- *  arcbios_add_other_components():
- *
- *  TODO: How should this be synched with the hardware devices
- *  added in machine.c?
- */
-static void arcbios_add_other_components(struct machine *machine,
-	uint64_t system)
-{
-	struct cpu *cpu = machine->cpus[0];
-
-	if (machine->machine_type == MACHINE_ARC &&
-	    (machine->machine_subtype == MACHINE_ARC_JAZZ_PICA
-	    || machine->machine_subtype == MACHINE_ARC_JAZZ_MAGNUM)) {
-		uint64_t jazzbus, ali_s3, vxl;
-		uint64_t diskcontroller, floppy, kbdctl, kbd;
-		uint64_t ptrctl, ptr, paral, audio;
-		uint64_t eisa, scsi;
-		/*  uint64_t serial1, serial2;  */
-
-		jazzbus = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_AdapterClass,
-		    COMPONENT_TYPE_MultiFunctionAdapter,
-		    0, 1, 2, 0, 0xffffffff, "Jazz-Internal Bus",
-		    system, NULL, 0);
-
-		/*
-		 *  DisplayController, needed by NetBSD:
-		 *  TODO: NetBSD still doesn't use it :(
-		 */
-		switch (machine->machine_subtype) {
-		case MACHINE_ARC_JAZZ_PICA:
-			/*  Default TLB entries on PICA-61:  */
-
-			/* 7: 256K, asid: 0x0, v: 0xe1000000,
-			   p0: 0xfff00000(2.VG), p1: 0x0(0..G)  */
-			mips_coproc_tlb_set_entry(cpu, 7, 262144,
-			    0xffffffffe1000000ULL,
-			    0x0fff00000ULL, 0, 1, 0, 0, 0, 1, 0, 2, 0);
-
-			/* 8: 64K, asid: 0x0, v: 0xe0000000,
-			   p0: 0x80000000(2DVG), p1: 0x0(0..G) */
-			mips_coproc_tlb_set_entry(cpu, 8, 65536,
-			    0xffffffffe0000000ULL,
-			    0x080000000ULL, 0, 1, 0, 1, 0, 1, 0, 2, 0);
-
-			/* 9: 64K, asid: 0x0, v: 0xe00e0000,
-			   p0: 0x800e0000(2DVG), p1: 0x800f0000(2DVG) */
-			mips_coproc_tlb_set_entry(cpu, 9, 65536,
-			    (uint64_t)0xffffffffe00e0000ULL,
-			    (uint64_t)0x0800e0000ULL,
-			    (uint64_t)0x0800f0000ULL, 1, 1, 1, 1, 1, 0, 2, 2);
-
-			/* 10: 4K, asid: 0x0, v: 0xe0100000,
-			   p0: 0xf0000000(2DVG), p1: 0x0(0..G) */
-			mips_coproc_tlb_set_entry(cpu, 10, 4096,
-			    (uint64_t)0xffffffffe0100000ULL,
-			    (uint64_t)0x0f0000000ULL, 0,1, 0, 1, 0, 1, 0, 2, 0);
-
-			/* 11: 1M, asid: 0x0, v: 0xe0200000,
-			   p0: 0x60000000(2DVG), p1: 0x60100000(2DVG) */
-			mips_coproc_tlb_set_entry(cpu, 11, 1048576,
-			    0xffffffffe0200000ULL,
-			    0x060000000ULL, 0x060100000ULL,1,1,1,1,1, 0, 2, 2);
-
-			/* 12: 1M, asid: 0x0, v: 0xe0400000,
-			   p0: 0x60200000(2DVG), p1: 0x60300000(2DVG) */
-			mips_coproc_tlb_set_entry(cpu, 12, 1048576,
-			    0xffffffffe0400000ULL, 0x060200000ULL,
-			    0x060300000ULL, 1, 1, 1, 1, 1, 0, 2, 2);
-
-			/* 13: 4M, asid: 0x0, v: 0xe0800000,
-			   p0: 0x40000000(2DVG), p1: 0x40400000(2DVG) */
-			mips_coproc_tlb_set_entry(cpu, 13, 1048576*4,
-			    0xffffffffe0800000ULL, 0x040000000ULL,
-			    0x040400000ULL, 1, 1, 1, 1, 1, 0, 2, 2);
-
-			/* 14: 16M, asid: 0x0, v: 0xe2000000,
-			   p0: 0x90000000(2DVG), p1: 0x91000000(2DVG) */
-			mips_coproc_tlb_set_entry(cpu, 14, 1048576*16,
-			    0xffffffffe2000000ULL, 0x090000000ULL,
-			    0x091000000ULL, 1, 1, 1, 1, 1, 0, 2, 2);
-
-			if (machine->x11_md.in_use) {
-				ali_s3 = arcbios_addchild_manual(cpu,
-				    COMPONENT_CLASS_ControllerClass,
-				    COMPONENT_TYPE_DisplayController,
-				    COMPONENT_FLAG_ConsoleOut |
-					COMPONENT_FLAG_Output,
-				    1, 2, 0, 0xffffffff, "ALI_S3",
-				    jazzbus, NULL, 0);
-
-				arcbios_addchild_manual(cpu,
-				    COMPONENT_CLASS_PeripheralClass,
-				    COMPONENT_TYPE_MonitorPeripheral,
-				    COMPONENT_FLAG_ConsoleOut |
-					COMPONENT_FLAG_Output,
-				    1, 2, 0, 0xffffffff, "1024x768",
-				    ali_s3, NULL, 0);
-			}
-			break;
-		case MACHINE_ARC_JAZZ_MAGNUM:
-			if (machine->x11_md.in_use) {
-				vxl = arcbios_addchild_manual(cpu,
-				    COMPONENT_CLASS_ControllerClass,
-				    COMPONENT_TYPE_DisplayController,
-				    COMPONENT_FLAG_ConsoleOut |
-					COMPONENT_FLAG_Output,
-				    1, 2, 0, 0xffffffff, "VXL",
-				    jazzbus, NULL, 0);
-
-				arcbios_addchild_manual(cpu,
-				    COMPONENT_CLASS_PeripheralClass,
-				    COMPONENT_TYPE_MonitorPeripheral,
-				    COMPONENT_FLAG_ConsoleOut |
-					COMPONENT_FLAG_Output,
-				    1, 2, 0, 0xffffffff, "1024x768",
-				    vxl, NULL, 0);
-			}
-			break;
-		}
-
-		diskcontroller = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_ControllerClass,
-		    COMPONENT_TYPE_DiskController,
-			COMPONENT_FLAG_Input | COMPONENT_FLAG_Output,
-		    1, 2, 0, 0xffffffff, "I82077", jazzbus, NULL, 0);
-
-		floppy = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_PeripheralClass,
-		    COMPONENT_TYPE_FloppyDiskPeripheral,
-			COMPONENT_FLAG_Removable |
-			COMPONENT_FLAG_Input | COMPONENT_FLAG_Output,
-		    1, 2, 0, 0xffffffff, NULL, diskcontroller, NULL, 0);
-
-		kbdctl = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_ControllerClass,
-		    COMPONENT_TYPE_KeyboardController,
-			COMPONENT_FLAG_ConsoleIn | COMPONENT_FLAG_Input,
-		    1, 2, 0, 0xffffffff, "I8742", jazzbus, NULL, 0);
-
-		kbd = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_PeripheralClass,
-		    COMPONENT_TYPE_KeyboardPeripheral,
-			COMPONENT_FLAG_ConsoleIn | COMPONENT_FLAG_Input,
-		    1, 2, 0, 0xffffffff, "PCAT_ENHANCED", kbdctl, NULL, 0);
-
-		ptrctl = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_ControllerClass,
-		    COMPONENT_TYPE_PointerController, COMPONENT_FLAG_Input,
-		    1, 2, 0, 0xffffffff, "I8742", jazzbus, NULL, 0);
-
-		ptr = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_PeripheralClass,
-		    COMPONENT_TYPE_PointerPeripheral, COMPONENT_FLAG_Input,
-		    1, 2, 0, 0xffffffff, "PS2 MOUSE", ptrctl, NULL, 0);
-
-/*  These cause Windows NT to bug out.  */
-#if 0
-		serial1 = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_ControllerClass,
-		    COMPONENT_TYPE_SerialController,
-			COMPONENT_FLAG_Input | COMPONENT_FLAG_Output,
-		    1, 2, 0, 0xffffffff, "COM1", jazzbus, NULL, 0);
-
-		serial2 = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_ControllerClass,
-		    COMPONENT_TYPE_SerialController,
-			COMPONENT_FLAG_Input | COMPONENT_FLAG_Output,
-		    1, 2, 0, 0xffffffff, "COM1", jazzbus, NULL, 0);
-#endif
-
-		paral = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_ControllerClass,
-		    COMPONENT_TYPE_ParallelController,
-			COMPONENT_FLAG_Input | COMPONENT_FLAG_Output,
-		    1, 2, 0, 0xffffffff, "LPT1", jazzbus, NULL, 0);
-
-		audio = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_ControllerClass,
-		    COMPONENT_TYPE_AudioController,
-			COMPONENT_FLAG_Input | COMPONENT_FLAG_Output,
-		    1, 2, 0, 0xffffffff, "MAGNUM", jazzbus, NULL, 0);
-
-		eisa = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_AdapterClass, COMPONENT_TYPE_EISAAdapter,
-		    0, 1, 2, 0, 0xffffffff, "EISA", system, NULL, 0);
-
-		{
-			unsigned char config[78];
-			memset(config, 0, sizeof(config));
-
-/*  config data version: 1, revision: 2, count: 4  */
-config[0] = 0x01; config[1] = 0x00;
-config[2] = 0x02; config[3] = 0x00;
-config[4] = 0x04; config[5] = 0x00; config[6] = 0x00; config[7] = 0x00;
-
-/*
-          type: Interrupt
-           share_disposition: DeviceExclusive, flags: LevelSensitive
-           level: 4, vector: 22, reserved1: 0
-*/
-			config[8] = arc_CmResourceTypeInterrupt;
-			config[9] = arc_CmResourceShareDeviceExclusive;
-			config[10] = arc_CmResourceInterruptLevelSensitive;
-			config[12] = 4;
-			config[16] = 22;
-			config[20] = 0;
-
-/*
-          type: Memory
-           share_disposition: DeviceExclusive, flags: ReadWrite
-           start: 0x 0 80002000, length: 0x1000
-*/
-			config[24] = arc_CmResourceTypeMemory;
-			config[25] = arc_CmResourceShareDeviceExclusive;
-			config[26] = arc_CmResourceMemoryReadWrite;
-config[28] = 0x00; config[29] = 0x20; config[30] = 0x00; config[31] = 0x80;
-  config[32] = 0x00; config[33] = 0x00; config[34] = 0x00; config[35] = 0x00;
-config[36] = 0x00; config[37] = 0x10; config[38] = 0x00; config[39] = 0x00;
-
-/*
-          type: DMA
-           share_disposition: DeviceExclusive, flags: 0x0
-           channel: 0, port: 0, reserved1: 0
-*/
-			config[40] = arc_CmResourceTypeDMA;
-			config[41] = arc_CmResourceShareDeviceExclusive;
-/*  42..43 = flags, 44,45,46,47 = channel, 48,49,50,51 = port, 52,53,54,55
- = reserved  */
-
-/*          type: DeviceSpecific
-           share_disposition: DeviceExclusive, flags: 0x0
-           datasize: 6, reserved1: 0, reserved2: 0
-           data: [0x1:0x0:0x2:0x0:0x7:0x30]
-*/
-			config[56] = arc_CmResourceTypeDeviceSpecific;
-			config[57] = arc_CmResourceShareDeviceExclusive;
-/*  58,59 = flags  60,61,62,63 = data size, 64..71 = reserved  */
-			config[60] = 6;
-/*  72..77 = the data  */
-			config[72] = 0x01; config[73] = 0x00; config[74] = 0x02;
-			config[75] = 0x00; config[76] = 0x07; config[77] = 0x30;
-			scsi = arcbios_addchild_manual(cpu,
-			    COMPONENT_CLASS_AdapterClass,
-			    COMPONENT_TYPE_SCSIAdapter,
-			    0, 1, 2, 0, 0xffffffff, "ESP216",
-			    system, config, sizeof(config));
-
-			arcbios_register_scsicontroller(machine, scsi);
-		}
-	}
-}
-
-
-/*
- *  arcbios_console_init():
- *
- *  Called from machine.c whenever an ARC-based machine is running with
- *  a graphical VGA-style framebuffer, which can be used as console.
- */
-void arcbios_console_init(struct machine *machine,
-	uint64_t vram, uint64_t ctrlregs)
-{
-	if (machine->md.arc == NULL) {
-		CHECK_ALLOCATION(machine->md.arc = (struct machine_arcbios *)
-		    malloc(sizeof(struct machine_arcbios)));
-		memset(machine->md.arc, 0, sizeof(struct machine_arcbios));
-	}
-
-	machine->md.arc->vgaconsole = 1;
-
-	machine->md.arc->console_vram = vram;
-	machine->md.arc->console_ctrlregs = ctrlregs;
-	machine->md.arc->console_maxx = ARC_CONSOLE_MAX_X;
-	machine->md.arc->console_maxy = ARC_CONSOLE_MAX_Y;
-	machine->md.arc->in_escape_sequence = 0;
-	machine->md.arc->escape_sequence[0] = '\0';
-}
-
-
-/*
- *  arc_environment_setup():
- *
- *  Initialize the emulated environment variables.
- */
-static void arc_environment_setup(struct machine *machine, int is64bit,
-	const char *primary_ether_addr)
-{
-	size_t bootpath_len = 500;
-	char *init_bootpath;
-	uint64_t addr, addr2;
-	struct cpu *cpu = machine->cpus[0];
-
-	/*
-	 *  Boot string in ARC format:
-	 *
-	 *  TODO: How about floppies? multi()disk()fdisk()
-	 *        Is tftp() good for netbooting?
-	 */
-	CHECK_ALLOCATION(init_bootpath = (char *) malloc(bootpath_len));
-	init_bootpath[0] = '\0';
-
-	if (machine->bootdev_id < 0 || machine->force_netboot) {
-		snprintf(init_bootpath, bootpath_len, "tftp()");
-	} else {
-		/*  TODO: Make this nicer.  */
-		if (machine->machine_type == MACHINE_SGI) {
-			if (machine->machine_subtype == 30)
-				strlcat(init_bootpath, "xio(0)pci(15)",
-				    bootpath_len);
-			if (machine->machine_subtype == 32)
-				strlcat(init_bootpath, "pci(0)",
-				    bootpath_len);
-		}
-
-		if (diskimage_is_a_cdrom(machine, machine->bootdev_id,
-		    machine->bootdev_type))
-			snprintf(init_bootpath + strlen(init_bootpath),
-			    bootpath_len - strlen(init_bootpath),
-			    "scsi(0)cdrom(%i)fdisk(0)", machine->bootdev_id);
-		else
-			snprintf(init_bootpath + strlen(init_bootpath),
-			    bootpath_len - strlen(init_bootpath),
-			    "scsi(0)disk(%i)rdisk(0)partition(1)",
-			    machine->bootdev_id);
-	}
-
-	if (machine->machine_type == MACHINE_ARC)
-		strlcat(init_bootpath, "\\", bootpath_len);
-
-	CHECK_ALLOCATION(machine->bootstr = (char *) malloc(ARC_BOOTSTR_BUFLEN));
-
-	strlcpy(machine->bootstr, init_bootpath, ARC_BOOTSTR_BUFLEN);
-	if (strlcat(machine->bootstr, machine->boot_kernel_filename,
-	    ARC_BOOTSTR_BUFLEN) >= ARC_BOOTSTR_BUFLEN) {
-		fprintf(stderr, "boot string too long?\n");
-		exit(1);
-	}
-
-	/*  Boot args., eg "-a"  */
-	machine->bootarg = machine->boot_string_argument;
-
-	/*  argc, argv, envp in a0, a1, a2:  */
-	cpu->cd.mips.gpr[MIPS_GPR_A0] = 0; /*  note: argc is increased later  */
-
-	/*  TODO:  not needed?  */
-	cpu->cd.mips.gpr[MIPS_GPR_SP] = (int64_t)(int32_t)
-	    (machine->physical_ram_in_mb * 1048576 + 0x80000000 - 0x2080);
-
-	/*  Set up argc/argv:  */
-	addr = ARC_ENV_STRINGS;
-	addr2 = ARC_ARGV_START;
-	cpu->cd.mips.gpr[MIPS_GPR_A1] = addr2;
-
-	/*  bootstr:  */
-	store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-	add_environment_string(cpu, machine->bootstr, &addr);
-	cpu->cd.mips.gpr[MIPS_GPR_A0] ++;
-
-	/*  bootarg:  */
-	if (machine->bootarg[0] != '\0') {
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, machine->bootarg, &addr);
-		cpu->cd.mips.gpr[MIPS_GPR_A0] ++;
-	}
-
-	store_pointer_and_advance(cpu, &addr2, 0, is64bit);
-
-	cpu->cd.mips.gpr[MIPS_GPR_A2] = addr2;
-
-	if (machine->machine_type == MACHINE_SGI) {
-		/*
-		 *  The SGI O2 PROM contains an "env" section header like this:
-		 *
-		 *  00004000  00 00 00 00 00 00 00 00  53 48 44 52 00 00 04 00  |........SHDR....|
-		 *  00004010  03 03 00 00 65 6e 76 00  00 00 00 00 00 00 00 00  |....env.........|
-		 *  00004020  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
-		 *  00004030  00 00 00 00 31 2e 30 00  00 00 00 00 13 18 11 ae  |....1.0.........|
-		 *
-		 *  followed by environment variables at 0x4000. It is not required
-		 *  by NetBSD/OpenBSD/Linux, but Irix seems to hardcodedly look into
-		 *  the PROM address space for this header.
-		 */
-		store_32bit_word(cpu, ARC_ENV_SGI + 0x08, 0x53484452);
-		store_32bit_word(cpu, ARC_ENV_SGI + 0x0c, 0x00000400);
-		store_32bit_word(cpu, ARC_ENV_SGI + 0x10, 0x03030000);
-		store_32bit_word(cpu, ARC_ENV_SGI + 0x14, 0x656e7600);
-		store_32bit_word(cpu, ARC_ENV_SGI + 0x34, 0x312e3000);
-		store_32bit_word(cpu, ARC_ENV_SGI + 0x3c, 0x131811ae);
-		addr = ARC_ENV_STRINGS_SGI;
-	}
-
-	/*
-	 *  Add environment variables.  For each variable, add it
-	 *  as a string using add_environment_string(), and add a
-	 *  pointer to it to the ARC_ENV_POINTERS array.
-	 */
-	if (machine->machine_type == MACHINE_SGI) {
-		if (machine->x11_md.in_use) {
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu, "ConsoleIn=keyboard()",
-			    &addr);
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu, "ConsoleOut=video()",
-			    &addr);
-
-			/*  g for graphical mode. G for graphical mode
-			    with SGI logo visible on Irix?  */
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu, "console=g", &addr);
-
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu, "gfx=alive", &addr);
-		} else {
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu, "ConsoleIn=serial(0)",
-			    &addr);
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu, "ConsoleOut=serial(0)",
-			    &addr);
-
-			/*  'd' or 'd2' in Irix, 'ttyS0' in Linux?  */
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu, "console=d", &addr);
-
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu, "gfx=dead", &addr);
-		}
-
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "AutoLoad=No", &addr);
-		
-		if (machine->bootdev_id < 0 || machine->force_netboot) {
-			/*
-			 *  diskless=1 means boot from network disk? (nfs?)
-			 *  diskless=2 means boot from network tape?
-			 */
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu, "diskless=1", &addr);
-
-			// store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			// add_environment_string(cpu, "tapedevice=bootp()10.0.0.2:/dev/tape", &addr);
-
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu, "bootfile=bootp()10.0.0.2:/var/boot/client/unix", &addr);
-
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu,
-			    "SystemPartition=bootp()10.0.0.2:/var/boot/client",
-			    &addr);
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu,
-			    "root=xyz",
-			    &addr);
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu,
-			    "OSLoadPartition=bootp()10.0.0.2:/var/boot/client",
-			    &addr);
-		} else {
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu, "diskless=0", &addr);
-
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu,
-			    "SystemPartition=pci(0)scsi(0)disk(2)rdisk(0)partition(8)",
-			    &addr);
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu,
-			    "OSLoadPartition=pci(0)scsi(0)disk(2)rdisk(0)partition(0)",
-			    &addr);
-		}
-
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "volume=80", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "sgilogo=y", &addr);
-
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "monitor=h", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "TimeZone=GMT", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "nogfxkbd=1", &addr);
-
-		/*  TODO IP30: 'xio(0)pci(15)scsi(0)disk(1)rdisk(0)partition(0)'  */
-
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "OSLoadFilename=/unix", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "OSLoader=sash", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "kernname=unix", &addr);
-
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "rbaud=9600", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "rebound=y", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "crt_option=1", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "netaddr=10.0.0.1", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "netmask=255.0.0.0", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "dlserver=10.0.0.2", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "srvaddr=10.0.0.2", &addr);
-
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "keybd=US", &addr);
-
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "cpufreq=3", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "dbaud=9600", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, primary_ether_addr, &addr);
-
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "verbose=1", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		// showconfig 0 means don't show. 1 means show some.
-		// 2 means show more. TODO: higher values?
-		add_environment_string(cpu, "showconfig=255", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "diagmode=v", &addr);
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, "debug_bigmem=1", &addr);
-	} else {
-		char *tmp;
-		size_t mlen = ARC_BOOTSTR_BUFLEN;
-		CHECK_ALLOCATION(tmp = (char *) malloc(mlen));
-		snprintf(tmp, mlen, "OSLOADOPTIONS=%s", machine->bootarg);
-
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		add_environment_string(cpu, tmp, &addr);
-
-		store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-		snprintf(tmp, mlen,
-		    "OSLOADPARTITION=scsi(0)disk(%d)rdisk(0)partition(1)",
-		    machine->bootdev_id);
-		add_environment_string(cpu, tmp, &addr);
-		free(tmp);
-
-		if (machine->x11_md.in_use) {
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu,
-			    "CONSOLEIN=multi()key()keyboard()console()", &addr);
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu,
-			    "CONSOLEOUT=multi()video()monitor()console()",
-			    &addr);
-		} else {
-			/*  TODO: serial console for ARC?  */
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu,
-			    "CONSOLEIN=multi()serial(0)", &addr);
-			store_pointer_and_advance(cpu, &addr2, addr, is64bit);
-			add_environment_string(cpu,
-			    "CONSOLEOUT=multi()serial(0)", &addr);
-		}
-	}
-
-	/*  End the environment strings with an empty zero-terminated
-	    string, and the envp array with a NULL pointer.  */
-	add_environment_string(cpu, "", &addr);	/*  the end  */
-	store_pointer_and_advance(cpu, &addr2, 0, is64bit);
-
-	/*  Return address:  (0x20 = ReturnFromMain())  */
-	cpu->cd.mips.gpr[MIPS_GPR_RA] = ARC_FIRMWARE_ENTRIES + 0x20;
-}
-
-
-/*
- *  arcbios_init():
- *
- *  Should be called before any other arcbios function is used. An exception
- *  is arcbios_console_init(), which may be called before this function.
- *
- *  TODO: Refactor; this is too long.
- */
-void arcbios_init(struct machine *machine, int is64bit, uint64_t sgi_ram_offset,
-	const char *primary_ether_addr, uint8_t *primary_ether_macaddr)
-{
-	int i, alloclen = 20;
-	char *name;
-	uint64_t arc_reserved, mem_base;
-	struct cpu *cpu = machine->cpus[0];
-	struct arcbios_sysid arcbios_sysid;
-	struct arcbios_dsp_stat arcbios_dsp_stat;
-	uint64_t system = 0;
-	struct arcbios_spb arcbios_spb;
-	struct arcbios_spb_64 arcbios_spb_64;
-
-	if (machine->md.arc == NULL) {
-		CHECK_ALLOCATION(machine->md.arc = (struct machine_arcbios *)
-		    malloc(sizeof(struct machine_arcbios)));
-		memset(machine->md.arc, 0, sizeof(struct machine_arcbios));
-	}
-
-	machine->md.arc->arc_64bit = is64bit;
-	machine->md.arc->wordlen = is64bit? sizeof(uint64_t) : sizeof(uint32_t);
-
-	machine->md.arc->next_component_address = FIRST_ARC_COMPONENT;
-	machine->md.arc->configuration_data_next_addr = ARC_CONFIG_DATA_ADDR;
-
-	if (machine->physical_ram_in_mb < 16)
-		fprintf(stderr, "WARNING! The ARC platform specification "
-		    "doesn't allow less than 16 MB of RAM. Continuing "
-		    "anyway.\n");
-
-	/*  File handles 0, 1, and 2 are stdin, stdout, and stderr.  */
-	for (i=0; i<ARC_MAX_HANDLES; i++) {
-		machine->md.arc->file_handle_in_use[i] = i<3? 1 : 0;
-		machine->md.arc->file_handle_string[i] = i>=3? NULL :
-		    (i==0? "(stdin)" : (i==1? "(stdout)" : "(stderr)"));
-		machine->md.arc->current_seek_offset[i] = 0;
-	}
-
-	if (!machine->x11_md.in_use)
-		machine->md.arc->vgaconsole = 0;
-
-	if (machine->md.arc->vgaconsole) {
-		char tmpstr[100];
-		int x, y;
-
-		machine->md.arc->console_curcolor = 0x1f;
-		for (y=0; y<machine->md.arc->console_maxy; y++)
-			for (x=0; x<machine->md.arc->console_maxx; x++)
-				arcbios_putcell(cpu, ' ', x, y);
-
-		machine->md.arc->console_curx = 0;
-		machine->md.arc->console_cury = 0;
-
-		arcbios_putstring(cpu, "GXemul " VERSION"  ARCBIOS emulation\n");
-
-		snprintf(tmpstr, sizeof(tmpstr), "%i cpu%s (%s), %i MB "
-		    "memory\n\n", machine->ncpus, machine->ncpus > 1? "s" : "",
-		    cpu->cd.mips.cpu_type.name,
-		    machine->physical_ram_in_mb);
-		arcbios_putstring(cpu, tmpstr);
-	}
-
-	arcbios_set_default_exception_handler(cpu);
-
-	memset(&arcbios_sysid, 0, sizeof(arcbios_sysid));
-	if (machine->machine_type == MACHINE_SGI) {
-		/*  Vendor ID, max 8 chars:  */
-		strncpy(arcbios_sysid.VendorId,  "SGI", 3);
-		switch (machine->machine_subtype) {
-		case 22:
-			strncpy(arcbios_sysid.ProductId,
-			    "87654321", 8);	/*  some kind of ID?  */
-			break;
-		case 32:
-			strncpy(arcbios_sysid.ProductId, "8", 1);
-			    /*  6 or 8 (?)  */
-			break;
-		default:
-			snprintf(arcbios_sysid.ProductId, 8, "IP%i",
-			    machine->machine_subtype);
-		}
-	} else {
-		switch (machine->machine_subtype) {
-		case MACHINE_ARC_JAZZ_PICA:
-			strncpy(arcbios_sysid.VendorId,  "MIPS MAG", 8);
-			strncpy(arcbios_sysid.ProductId, "ijkl", 4);
-			break;
-		case MACHINE_ARC_JAZZ_MAGNUM:
-			strncpy(arcbios_sysid.VendorId,  "MIPS MAG", 8);
-			strncpy(arcbios_sysid.ProductId, "ijkl", 4);
-			break;
-		default:
-			fatal("error in machine.c sysid\n");
-			exit(1);
-		}
-	}
-
-	store_buf(cpu, SGI_SYSID_ADDR, (char *)&arcbios_sysid,
-	    sizeof(arcbios_sysid));
-
-	arcbios_get_dsp_stat(cpu, &arcbios_dsp_stat);
-	store_buf(cpu, ARC_DSPSTAT_ADDR, (char *)&arcbios_dsp_stat,
-	    sizeof(arcbios_dsp_stat));
-
-	/*
-	 *  The first 12 MBs of RAM are simply reserved... this simplifies
-	 *  things a lot.  If there's more than 512MB of RAM, it has to be
-	 *  split in two, according to the ARC spec.
-	 *
-	 *  However, the region of physical address space between 0x10000000
-	 *  and 0x1fffffff (256 - 512 MB) is sometimes occupied by memory
-	 *  mapped devices, for example in the SGI O2, so that portion can not
-	 *  be used.
-	 *
-	 *  Instead, any high memory needs to be added using a machine-specific
-	 *  high address.
-	 */
-	int reserved_bottom_mem_in_mb = 12;
-	int free_type = ARCBIOS_MEM_FreeMemory;
-	
-	machine->md.arc->memdescriptor_base = ARC_MEMDESC_ADDR;
-
-	arc_reserved = 0x2000;
-	if (machine->machine_type == MACHINE_SGI)
-		arc_reserved = 0x4000;
-
-	arcbios_add_memory_descriptor(cpu, 0, arc_reserved,
-	    ARCBIOS_MEM_FirmwarePermanent);
-	arcbios_add_memory_descriptor(cpu, sgi_ram_offset + arc_reserved,
-	    0x60000-arc_reserved, ARCBIOS_MEM_FirmwareTemporary);
-
-	uint64_t ram = 0;
-
-	// Default is to use a physical memory base around zero (0).
-	mem_base = sgi_ram_offset / 1048576;
-
-	while (ram < machine->physical_ram_in_mb) {
-		uint64_t to_add = machine->physical_ram_in_mb - ram;
-
-		if (to_add > 256)
-			to_add = 256;
-
-		if (ram == 0) {
-			// Skip first few MB of RAM, for reserved structures.
-			ram += reserved_bottom_mem_in_mb;
-			mem_base += reserved_bottom_mem_in_mb;
-			to_add -= reserved_bottom_mem_in_mb;
-		}
-
-		arcbios_add_memory_descriptor(cpu, mem_base * 1048576,
-		    to_add * 1048576, free_type);
-
-		ram += to_add;
-		mem_base += to_add;
-
-		if (mem_base == 256) {
-			if (machine->machine_type == MACHINE_SGI &&
-			    machine->machine_subtype == 32) {
-				// mem_base = 0x50000000 / 1048576;
-				// Actually, the above does not seem to work.
-				// Perhaps the ARCS in the O2 simply says
-				// 256 MB regardless of how much more there
-				// is in the machine?
-				break;
-			} else {
-				fatal("Ignoring RAM above 256 MB! (Not yet "
-					"implemented for this machine type.)\n");
-				break;
-			}
-		}
-	}
-
-	/*
-	 *  Components:   (this is an example of what a system could look like)
-	 *
-	 *  [System]
-	 *	[CPU]  (one for each cpu)
-	 *	    [FPU]  (one for each cpu)
-	 *	    [CPU Caches]
-	 *	[Memory]
-	 *	[Ethernet]
-	 *	[Serial]
-	 *	[SCSI]
-	 *	    [Disk]
-	 *
-	 *  Here's a good list of what hardware is in different IP-models:
-	 *  http://www.linux-mips.org/archives/linux-mips/2001-03/msg00101.html
-	 */
-
-	if (machine->machine_name == NULL)
-		fatal("ERROR: machine_name == NULL\n");
-
-	/*  Add the root node:  */
-	switch (machine->machine_type) {
-	case MACHINE_SGI:
-		CHECK_ALLOCATION(name = (char *) malloc(alloclen));
-		snprintf(name, alloclen, "SGI-IP%i",
-		    machine->machine_subtype);
-
-		/*  A very special case for IP24 (which identifies itself
-		    as an IP22):  */
-		if (machine->machine_subtype == 24)
-			snprintf(name, alloclen, "SGI-IP22");
-		break;
-	case MACHINE_ARC:
-		/*  ARC:  */
-		switch (machine->machine_subtype) {
-		case MACHINE_ARC_JAZZ_PICA:
-			name = strdup("PICA-61");
-			break;
-		case MACHINE_ARC_JAZZ_MAGNUM:
-			name = strdup("Microsoft-Jazz");
-			break;
-		default:
-			fatal("Unimplemented ARC machine type %i\n",
-			    machine->machine_subtype);
-			exit(1);
-		}
-		break;
-	default:
-		fatal("ERROR: non-SGI and non-ARC?\n");
-		exit(1);
-	}
-
-	system = arcbios_addchild_manual(cpu, COMPONENT_CLASS_SystemClass,
-	    COMPONENT_TYPE_ARC, 0,1,2,0, 0xffffffff, name, 0/*ROOT*/, NULL, 0);
-	debug("ARC system @ 0x%" PRIx64" (\"%s\")\n", (uint64_t) system, name);
-
-
-	/*
-	 *  Add tree nodes for CPUs and their caches:
-	 */
-
-	for (i=0; i<machine->ncpus; i++) {
-		uint64_t cpuaddr, fpu=0, picache, pdcache, sdcache=0;
-		int cache_size, cache_line_size;
-		unsigned int jj;
-		char arc_cpu_name[100];
-		char arc_fpc_name[105];
-
-		snprintf(arc_cpu_name, sizeof(arc_cpu_name),
-		    "MIPS-%s", machine->cpu_name);
-
-		arc_cpu_name[sizeof(arc_cpu_name)-1] = 0;
-		for (jj=0; jj<strlen(arc_cpu_name); jj++)
-			if (arc_cpu_name[jj] >= 'a' && arc_cpu_name[jj] <= 'z')
-				arc_cpu_name[jj] += ('A' - 'a');
-
-		strlcpy(arc_fpc_name, arc_cpu_name, sizeof(arc_fpc_name));
-		strlcat(arc_fpc_name, "FPC", sizeof(arc_fpc_name));
-
-		cpuaddr = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_ProcessorClass, COMPONENT_TYPE_CPU,
-		    0, 1, 2, i, 0xffffffff, arc_cpu_name, system, NULL, 0);
-
-		/*
-		 *  TODO: This was in the ARC specs, but it isn't really used
-		 *  by ARC implementations?   At least SGI-IP32 uses it.
-		 */
-		if (machine->machine_type == MACHINE_SGI)
-			fpu = arcbios_addchild_manual(cpu,
-			    COMPONENT_CLASS_ProcessorClass, COMPONENT_TYPE_FPU,
-			    0, 1, 2, 0, 0xffffffff, arc_fpc_name, cpuaddr,
-			    NULL, 0);
-
-		cache_size = DEFAULT_PCACHE_SIZE - 12;
-		if (cpu->cd.mips.cache_picache)
-			cache_size = cpu->cd.mips.cache_picache - 12;
-		if (cache_size < 0)
-			cache_size = 0;
-
-		cache_line_size = DEFAULT_PCACHE_LINESIZE;
-		if (cpu->cd.mips.cache_picache_linesize)
-			cache_line_size = cpu->cd.mips.cache_picache_linesize;
-		if (cache_line_size < 0)
-			cache_line_size = 0;
-
-		picache = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_CacheClass, COMPONENT_TYPE_PrimaryICache,
-		    0, 1, 2,
-		    /*
-		     *  Key bits:  0xXXYYZZZZ
-		     *  XX is refill-size.
-		     *  Cache line size is 1 << YY,
-		     *  Cache size is 4KB << ZZZZ.
-		     */
-		    0x01000000 + (cache_line_size << 16) + cache_size,
-			/*  32 bytes per line, default = 32 KB total  */
-		    0xffffffff, NULL, cpuaddr, NULL, 0);
-
-		cache_size = DEFAULT_PCACHE_SIZE - 12;
-		if (cpu->cd.mips.cache_pdcache)
-			cache_size = cpu->cd.mips.cache_pdcache - 12;
-		if (cache_size < 0)
-			cache_size = 0;
-
-		cache_line_size = DEFAULT_PCACHE_LINESIZE;
-		if (cpu->cd.mips.cache_pdcache_linesize)
-			cache_line_size = cpu->cd.mips.cache_pdcache_linesize;
-		if (cache_line_size < 0)
-			cache_line_size = 0;
-
-		pdcache = arcbios_addchild_manual(cpu,
-		    COMPONENT_CLASS_CacheClass,
-		    COMPONENT_TYPE_PrimaryDCache, 0, 1, 2,
-		    /*
-		     *  Key bits:  0xYYZZZZ
-		     *  Cache line size is 1 << YY,
-		     *  Cache size is 4KB << ZZZZ.
-		     */
-		    0x01000000 + (cache_line_size << 16) + cache_size,
-			/*  32 bytes per line, default = 32 KB total  */
-		    0xffffffff, NULL, cpuaddr, NULL, 0);
-
-		if (cpu->cd.mips.cache_secondary >= 12) {
-			cache_size = cpu->cd.mips.cache_secondary - 12;
-
-			cache_line_size = 6;	/*  64 bytes default  */
-			if (cpu->cd.mips.cache_secondary_linesize)
-				cache_line_size = cpu->cd.mips.
-				    cache_secondary_linesize;
-			if (cache_line_size < 0)
-				cache_line_size = 0;
-
-			sdcache = arcbios_addchild_manual(cpu,
-			    COMPONENT_CLASS_CacheClass,
-			    COMPONENT_TYPE_SecondaryDCache, 0, 1, 2,
-			    /*
-			     *  Key bits:  0xYYZZZZ
-			     *  Cache line size is 1 << YY,
-			     *  Cache size is 4KB << ZZZZ.
-			     */
-			    0x01000000 + (cache_line_size << 16) + cache_size,
-				/*  64 bytes per line, default = 1 MB total  */
-			    0xffffffff, NULL, cpuaddr, NULL, 0);
-		}
-
-		debug("ARC cpu%i @ 0x%" PRIx64, i, (uint64_t) cpuaddr);
-
-		if (fpu != 0)
-			debug(" (fpu @ 0x%" PRIx64")\n", (uint64_t) fpu);
-		else
-			debug("\n");
-
-		debug("    picache @ 0x%" PRIx64", pdcache @ 0x%" PRIx64"\n",
-		    (uint64_t) picache, (uint64_t) pdcache);
-
-		if (cpu->cd.mips.cache_secondary >= 12)
-			debug("    sdcache @ 0x%" PRIx64"\n",
-			    (uint64_t) sdcache);
-
-		if (machine->machine_type == MACHINE_SGI) {
-			/*  TODO:  Memory amount (and base address?)!  */
-			uint64_t memory = arcbios_addchild_manual(cpu,
-			    COMPONENT_CLASS_MemoryClass,
-			    COMPONENT_TYPE_MemoryUnit, 0, 1, 2, 0,
-			    0xffffffff, "memory", cpuaddr, NULL, 0);
-			debug("ARC memory @ 0x%" PRIx64"\n", (uint64_t) memory);
-		}
-	}
-
-
-	/*
-	 *  Add other components:
-	 *
-	 *  TODO: How should this be synched with the hardware devices
-	 *  added in machine.c?
-	 */
-
-	arcbios_add_other_components(machine, system);
-
-
-	/*
-	 *  Defalt TLB entry for 64-bit SGI machines:
-	 */
-	if (machine->machine_type == MACHINE_SGI) {
-		switch (machine->machine_subtype) {
-		case 12:
-			/*  TODO: Not on 12?  */
-			break;
-		case 32:
-			/*  Not needed for SGI O2?  */
-			break;
-		default:
-			mips_coproc_tlb_set_entry(cpu, 0, 1048576*16,
-			    0xc000000000000000ULL, 0, 1048576*16, 1,1,1,1,1, 0, 2, 2);
-		}
-	}
-
-
-	/*
-	 *  Set up Firmware Vectors:
-	 */
-	add_symbol_name(&machine->symbol_context,
-	    ARC_FIRMWARE_ENTRIES, 0x10000, "[ARCBIOS entry]", 0, 1);
-
-	for (i=0; i<100; i++) {
-		if (is64bit) {
-			store_64bit_word(cpu, ARC_FIRMWARE_VECTORS + i*8,
-			    ARC_FIRMWARE_ENTRIES + i*8);
-			store_64bit_word(cpu, ARC_PRIVATE_VECTORS + i*8,
-			    ARC_PRIVATE_ENTRIES + i*8);
-
-			/*  "Magic trap" instruction:  */
-			store_32bit_word(cpu, ARC_FIRMWARE_ENTRIES + i*8,
-			    0x00c0de0c);
-			store_32bit_word(cpu, ARC_PRIVATE_ENTRIES + i*8,
-			    0x00c0de0c);
-		} else {
-			store_32bit_word(cpu, ARC_FIRMWARE_VECTORS + i*4,
-			    ARC_FIRMWARE_ENTRIES + i*4);
-			store_32bit_word(cpu, ARC_PRIVATE_VECTORS + i*4,
-			    ARC_PRIVATE_ENTRIES + i*4);
-
-			/*  "Magic trap" instruction:  */
-			store_32bit_word(cpu, ARC_FIRMWARE_ENTRIES + i*4,
-			    0x00c0de0c);
-			store_32bit_word(cpu, ARC_PRIVATE_ENTRIES + i*4,
-			    0x00c0de0c);
-		}
-	}
-
-
-	/*
-	 *  Set up the ARC SPD:
-	 */
-	if (is64bit) {
-		/*  ARCS64 SPD (TODO: This is just a guess)  */
-		memset(&arcbios_spb_64, 0, sizeof(arcbios_spb_64));
-		store_64bit_word_in_host(cpu, (unsigned char *)
-		    &arcbios_spb_64.SPBSignature, ARCBIOS_SPB_SIGNATURE);
-		store_16bit_word_in_host(cpu, (unsigned char *)
-		    &arcbios_spb_64.Version, 64);
-		store_16bit_word_in_host(cpu, (unsigned char *)
-		    &arcbios_spb_64.Revision, 0);
-		store_64bit_word_in_host(cpu, (unsigned char *)
-		    &arcbios_spb_64.FirmwareVector, ARC_FIRMWARE_VECTORS);
-		store_buf(cpu, SGI_SPB_ADDR, (char *)&arcbios_spb_64, 
-		    sizeof(arcbios_spb_64));
-	} else {
-		/*  ARCBIOS SPB:  (For ARC and 32-bit SGI modes)  */
-		memset(&arcbios_spb, 0, sizeof(arcbios_spb));
-		store_32bit_word_in_host(cpu, (unsigned char *)
-		    &arcbios_spb.SPBSignature, ARCBIOS_SPB_SIGNATURE);
-		store_32bit_word_in_host(cpu, (unsigned char *)   
-		    &arcbios_spb.SPBLength, sizeof(arcbios_spb));     
-		store_16bit_word_in_host(cpu, (unsigned char *)   
-		    &arcbios_spb.Version, 1);
-		store_16bit_word_in_host(cpu, (unsigned char *)
-		    &arcbios_spb.Revision, machine->machine_type ==
-		    MACHINE_SGI? 10 : 2);
-		store_32bit_word_in_host(cpu, (unsigned char *)
-		    &arcbios_spb.FirmwareVector, ARC_FIRMWARE_VECTORS);
-		store_32bit_word_in_host(cpu, (unsigned char *)
-		    &arcbios_spb.FirmwareVectorLength, 100 * 4);    /*  ?  */
-		store_32bit_word_in_host(cpu, (unsigned char *)
-		    &arcbios_spb.PrivateVector, ARC_PRIVATE_VECTORS);
-		store_32bit_word_in_host(cpu, (unsigned char *)  
-		    &arcbios_spb.PrivateVectorLength, 100 * 4);     /*  ?  */
-		store_buf(cpu, SGI_SPB_ADDR, (char *)&arcbios_spb,
-		    sizeof(arcbios_spb));
-	}
-
-
-	/*
-	 *  TODO: How to build the component tree intermixed with
-	 *  the rest of device initialization?
-	 */
-
-	arc_environment_setup(machine, is64bit, primary_ether_addr);
-}
-
diff -Nru gxemul-0.6.2/src/promemul/dec_prom.c gxemul-0.7.0+dfsg/src/promemul/dec_prom.c
--- gxemul-0.6.2/src/promemul/dec_prom.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/dec_prom.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,657 @@
+/*
+ *  Copyright (C) 2003-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: DECstation PROM emulation
+ *
+ *  Implementation note: Remember that only the lowest 32 bits of GPRs are
+ *  actually valid when using dyntrans with e.g. R3000 CPUs.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/time.h>
+#include <sys/resource.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "cpu_mips.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "machine_pmax.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/dec_prom.h"
+#include "thirdparty/dec_5100.h"
+#include "thirdparty/dec_kn01.h"
+#include "thirdparty/dec_kn02.h"
+#include "thirdparty/dec_kn03.h"
+
+
+extern int quiet_mode;
+
+
+/*
+ *  mem_readchar():
+ *
+ *  Reads a byte from emulated RAM, using a MIPS register as a base address.
+ *  (Helper function.)
+ */
+static unsigned char mem_readchar(struct cpu *cpu, int regbase, int offset)
+{
+	unsigned char ch;
+	cpu->memory_rw(cpu, cpu->mem, (int32_t)cpu->cd.mips.gpr[regbase] +
+	    offset, &ch, sizeof(ch), MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
+	return ch;
+}
+
+
+/*
+ *  dec_jumptable_func():
+ *
+ *  The jumptable is located at the beginning of the PROM, at 0xbfc00000 + i*8,
+ *  where i is the decimal function number. Many of these can be converted to
+ *  an identical callback function.
+ *
+ *  Return value is non-zero if the vector number was converted into a callback
+ *  function number, otherwise 0.
+ *
+ *	Vector	(dec)	Function
+ *	0x0	0	reset()
+ *	0x10	2	restart()
+ *	0x18	3	reinit()
+ *	0x30	6	open()
+ *	0x38	7	read()
+ *	0x58	11	lseek()
+ *	0x68	13	putchar()
+ *	0x88	17	printf()
+ *	0x108	33	getenv2()
+ */
+int dec_jumptable_func(struct cpu *cpu, int vector)
+{
+	int i;
+	static int file_opened = 0;
+	static int current_file_offset = 0;
+
+	switch (vector) {
+	case 0x0:	/*  reset()  */
+		/*  TODO  */
+		cpu->running = 0;
+		break;
+	case 0x10:	/*  restart()  */
+		/*  TODO  */
+		cpu->running = 0;
+		break;
+	case 0x18:	/*  reinit()  */
+		/*  TODO  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0x30:	/*  open()  */
+		/*
+		 *  TODO: This is just a hack to allow Sprite/pmax' bootblock
+		 *  code to load /vmsprite. The filename argument (in A0)
+		 *  is ignored, and a file handle value of 1 is returned.
+		 */
+		if (file_opened) {
+			fatal("\ndec_jumptable_func(): opening more than one "
+			    "file isn't supported yet.\n");
+			cpu->running = 0;
+		}
+		file_opened = 1;
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 1;
+		break;
+	case 0x38:	/*  read(handle, ptr, length)  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = (uint64_t) -1;
+		if ((int32_t)cpu->cd.mips.gpr[MIPS_GPR_A2] > 0) {
+			int disk_id = diskimage_bootdev(cpu->machine, NULL);
+			int res;
+			unsigned char *tmp_buf;
+
+			CHECK_ALLOCATION(tmp_buf = (unsigned char *)
+			    malloc(cpu->cd.mips.gpr[MIPS_GPR_A2]));
+
+			res = diskimage_access(cpu->machine, disk_id,
+			    DISKIMAGE_SCSI, 0, current_file_offset, tmp_buf,
+			    cpu->cd.mips.gpr[MIPS_GPR_A2]);
+
+			/*  If the transfer was successful, transfer the data
+			    to emulated memory:  */
+			if (res) {
+				uint64_t dst = cpu->cd.mips.gpr[MIPS_GPR_A1];
+				store_buf(cpu, dst, (char *)tmp_buf,
+				    cpu->cd.mips.gpr[MIPS_GPR_A2]);
+				cpu->cd.mips.gpr[MIPS_GPR_V0] =
+				    cpu->cd.mips.gpr[MIPS_GPR_A2];
+				current_file_offset +=
+				    cpu->cd.mips.gpr[MIPS_GPR_A2];
+			}
+
+			free(tmp_buf);
+		}
+		break;
+	case 0x58:	/*  lseek(handle, offset[, whence])  */
+		/*  TODO  */
+		if (cpu->cd.mips.gpr[MIPS_GPR_A2] == 0)
+			current_file_offset = cpu->cd.mips.gpr[MIPS_GPR_A1];
+		else
+			fatal("WARNING! Unimplemented whence in "
+			    "dec_jumptable_func()\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0x68:	/*  putchar()  */
+		console_putchar(cpu->machine->main_console_handle,
+		    cpu->cd.mips.gpr[MIPS_GPR_A0]);
+		break;
+	case 0x88:	/*  printf()  */
+		return 0x30;
+	case 0x108:	/*  getenv2()  */
+		return 0x64;
+	default:
+		cpu_register_dump(cpu->machine, cpu, 1, 0x1);
+		printf("a0 points to: ");
+		for (i=0; i<40; i++) {
+			unsigned char ch = '\0';
+			cpu->memory_rw(cpu, cpu->mem,
+			    (int32_t)cpu->cd.mips.gpr[MIPS_GPR_A0] + i, &ch,
+			    sizeof(ch), MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
+			if (ch >= ' ' && ch < 126)
+				printf("%c", ch);
+			else
+				printf("[%02x]", ch);
+		}
+		printf("\n");
+		fatal("PROM emulation: unimplemented JUMP TABLE vector "
+		    "0x%x (decimal function %i)\n", vector, vector/8);
+		cpu->running = 0;
+	}
+
+	return 0;
+}
+
+
+/*
+ *  decstation_prom_emul():
+ *
+ *  DECstation PROM emulation.
+ *
+ *  Callback functions:
+ *	0x0c	strcmp()
+ *	0x14	strlen()
+ *	0x24	getchar()
+ *	0x28	gets()
+ *	0x2c	puts()
+ *	0x30	printf()
+ *	0x38	iopoll()
+ *	0x54	bootinit()
+ *	0x58	bootread()
+ *	0x64	getenv()
+ *	0x6c	slot_address()
+ *	0x70	wbflush()
+ *	0x7c	clear_cache()
+ *	0x80	getsysid()
+ *	0x84	getbitmap()
+ *	0x88	disableintr()
+ *	0x8c	enableintr()
+ *	0x9c	halt()
+ *	0xa4	gettcinfo()
+ *	0xa8	execute_cmd()
+ *	0xac	rex()
+ */
+int decstation_prom_emul(struct cpu *cpu)
+{
+	int i, j, ch, argreg, argdata;
+	int vector = cpu->pc & 0xfff;
+	int callback = (cpu->pc & 0xf000)? 1 : 0;
+	unsigned char buf[100];
+	unsigned char ch1, ch2;
+	uint64_t slot_base = 0x10000000, slot_size = 0;
+
+	if (!callback) {
+		vector = dec_jumptable_func(cpu, vector);
+		if (vector == 0)
+			return 1;
+	} else {
+		/*  Vector number is n*4, PC points to n*8.  */
+		vector /= 2;
+	}
+
+	switch (vector) {
+	case 0x0c:		/*  strcmp():  */
+		i = j = 0;
+		do {
+			ch1 = mem_readchar(cpu, MIPS_GPR_A0, i++);
+			ch2 = mem_readchar(cpu, MIPS_GPR_A1, j++);
+		} while (ch1 == ch2 && ch1 != '\0');
+
+		/*  If ch1=='\0', then strings are equal.  */
+		if (ch1 == '\0')
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		if ((signed char)ch1 > (signed char)ch2)
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = 1;
+		if ((signed char)ch1 < (signed char)ch2)
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = (uint64_t) -1;
+		break;
+	case 0x14:		/*  strlen():  */
+		i = 0;
+		do {
+			ch2 = mem_readchar(cpu, MIPS_GPR_A0, i++);
+		} while (ch2 != 0);
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = i - 1;
+		break;
+	case 0x24:		/*  getchar()  */
+		/*  debug("[ DEC PROM getchar() ]\n");  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = console_readchar(
+		    cpu->machine->main_console_handle);
+		break;
+	case 0x28:		/*  gets()  */
+		/*  debug("[ DEC PROM gets() ]\n");  */
+		// tmpaddr = cpu->cd.mips.gpr[MIPS_GPR_A0];
+		i = 0;
+
+		do {
+			/*  TODO: Make this not hang (block) the entire emulator  */
+			while ((ch = console_readchar(cpu->machine->main_console_handle)) < 1)
+				;
+
+			if (ch == '\r')
+				ch = '\n';
+
+			ch2 = ch;
+
+			if (ch == '\b') {
+				if (i > 0) {
+					console_putchar(cpu->machine->main_console_handle, ch2);
+					console_putchar(cpu->machine->main_console_handle, ' ');
+					console_putchar(cpu->machine->main_console_handle, ch2);
+				}
+			} else
+				console_putchar(cpu->machine->main_console_handle, ch2);
+
+			fflush(stdout);
+
+			if (ch == '\n') {
+				/*  It seems that trailing newlines are not included in the buffer.  */
+			} else if (ch != '\b') {
+				cpu->memory_rw(cpu, cpu->mem, (int32_t)
+				    cpu->cd.mips.gpr[MIPS_GPR_A0] + i,
+				    &ch2, sizeof(ch2), MEM_WRITE,
+				    CACHE_DATA | NO_EXCEPTIONS);
+				i++;
+			} else {
+				if (i > 0)
+					i--;
+			}
+		} while (ch2 != '\n');
+
+		/*  Trailing nul-byte:  */
+		ch2 = '\0';
+		cpu->memory_rw(cpu, cpu->mem, (int32_t)
+		    cpu->cd.mips.gpr[MIPS_GPR_A0] + i, &ch2, sizeof(ch2),
+		    MEM_WRITE, CACHE_DATA | NO_EXCEPTIONS);
+
+		/*  Return the input argument:  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = cpu->cd.mips.gpr[MIPS_GPR_A0];
+		break;
+	case 0x2c:		/*  puts()  */
+		i = 0;
+		while ((ch = mem_readchar(cpu, MIPS_GPR_A0, i++)) != '\0')
+			console_putchar(cpu->machine->main_console_handle, ch);
+		console_putchar(cpu->machine->main_console_handle, '\n');
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0x30:		/*  printf()  */
+		if (cpu->machine->register_dump ||
+		    cpu->machine->instruction_trace)
+			debug("PROM printf(0x%08lx): \n",
+			    (long)cpu->cd.mips.gpr[MIPS_GPR_A0]);
+
+		i = 0; ch = -1; argreg = MIPS_GPR_A1;
+		while (ch != '\0') {
+			char printfbuf[8000];
+			size_t x;
+
+			printfbuf[0] = printfbuf[sizeof(printfbuf)-1] = '\0';
+
+			ch = mem_readchar(cpu, MIPS_GPR_A0, i++);
+			switch (ch) {
+			case '%':
+				ch = '0';
+				while (ch >= '0' && ch <= '9')
+					ch = mem_readchar(cpu,
+					    MIPS_GPR_A0, i++);
+
+				switch (ch) {
+				case '%':
+					strlcpy(printfbuf, "%%",
+					    sizeof(printfbuf));
+					break;
+				case 'c':
+				case 'd':
+				case 's':
+				case 'x':
+					/*  Get argument:  */
+					if (argreg > MIPS_GPR_A3) {
+#if 1
+						/*  Linux booters seem to go
+						    over the edge sometimes: */
+						ch = '\0';
+						strlcpy(printfbuf, "[...]\n",
+						    sizeof(printfbuf));
+#else
+						printf("[ decstation_prom_emul"
+						    "(): too many arguments ]");
+						/*  This reuses the last arg,
+						    which is utterly incorrect.
+						    (TODO)  */
+						argreg = MIPS_GPR_A3;
+#endif
+					}
+
+					ch2 = argdata = cpu->cd.mips.gpr[argreg];
+
+					switch (ch) {
+					case 'c':
+						snprintf(printfbuf, sizeof(
+						    printfbuf), "%c", ch2);
+						break;
+					case 'd':
+						snprintf(printfbuf, sizeof(
+						    printfbuf), "%d", argdata);
+						break;
+					case 'x':
+						snprintf(printfbuf, sizeof(
+						    printfbuf), "%x", argdata);
+						break;
+					case 's':
+						/*  Print a "%s" string.  */
+						j = 0;
+						while (ch2) {
+							ch2 = mem_readchar(cpu, argreg, j++);
+							if (ch2) {
+								snprintf(
+								    printfbuf + strlen(printfbuf),
+								    sizeof(printfbuf) - 1 - strlen(printfbuf),
+								    "%c",
+								    ch2);
+							}
+						}
+						break;
+					}
+					argreg ++;
+					break;
+				default:
+					printf("[ unknown printf format char '%c' ]", ch);
+				}
+				break;
+			case '\0':
+				break;
+			default:
+				snprintf(printfbuf, sizeof(printfbuf),
+				    "%c", ch);
+			}
+
+			printfbuf[sizeof(printfbuf)-1] = '\0';
+
+			for (x=0; x<strlen(printfbuf); x++)
+				console_putchar(cpu->machine->
+				    main_console_handle, printfbuf[x]);
+		}
+		if (cpu->machine->register_dump ||
+		    cpu->machine->instruction_trace)
+			debug("\n");
+		fflush(stdout);
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0x54:		/*  bootinit()  */
+		/*  debug("[ DEC PROM bootinit(0x%08x): TODO ]\n",
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0x58:		/*  bootread(int b, void *buffer, int n)  */
+		/*
+		 *  Read data from the boot device.
+		 *  b is a sector number (512 bytes per sector),
+		 *  buffer is the destination address, and n
+		 *  is the number of _bytes_ to read.
+		 *
+		 *  TODO: Return value? NetBSD thinks that 0 is ok.
+		 */
+		debug("[ DEC PROM bootread(0x%x, 0x%08x, 0x%x) ]\n",
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0],
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A1],
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A2]);
+
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+
+		if ((int32_t)cpu->cd.mips.gpr[MIPS_GPR_A2] > 0) {
+			int disk_id = diskimage_bootdev(cpu->machine, NULL);
+			int res;
+			unsigned char *tmp_buf;
+
+			CHECK_ALLOCATION(tmp_buf = (unsigned char *)
+			    malloc(cpu->cd.mips.gpr[MIPS_GPR_A2]));
+
+			res = diskimage_access(cpu->machine, disk_id,
+			    DISKIMAGE_SCSI, 0,
+			    cpu->cd.mips.gpr[MIPS_GPR_A0] * 512, tmp_buf,
+			    cpu->cd.mips.gpr[MIPS_GPR_A2]);
+
+			/*  If the transfer was successful, transfer the data
+			    to emulated memory:  */
+			if (res) {
+				uint64_t dst = cpu->cd.mips.gpr[MIPS_GPR_A1];
+				if (dst < 0x80000000ULL)
+					dst |= 0x80000000;
+
+				store_buf(cpu, dst, (char *)tmp_buf,
+				    cpu->cd.mips.gpr[MIPS_GPR_A2]);
+				cpu->cd.mips.gpr[MIPS_GPR_V0] =
+				    cpu->cd.mips.gpr[MIPS_GPR_A2];
+			}
+
+			free(tmp_buf);
+		}
+		break;
+	case 0x64:		/*  getenv()  */
+		/*  Find the environment variable given by a0:  */
+		for (i=0; i<(int)sizeof(buf); i++)
+			cpu->memory_rw(cpu, cpu->mem, (int32_t)
+			    cpu->cd.mips.gpr[MIPS_GPR_A0] + i, &buf[i],
+			    sizeof(char), MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
+		buf[sizeof(buf)-1] = '\0';
+		debug("[ DEC PROM getenv(\"%s\") ]\n", buf);
+		for (i=0; i<0x1000; i++) {
+			/*  Matching string at offset i?  */
+			int nmatches = 0;
+			for (j=0; j<(int32_t)strlen((char *)buf); j++) {
+				cpu->memory_rw(cpu, cpu->mem, (int32_t)
+				    (DEC_PROM_STRINGS + i + j), &ch2,
+				    sizeof(char), MEM_READ, CACHE_DATA |
+				    NO_EXCEPTIONS);
+				if (ch2 == buf[j])
+					nmatches++;
+			}
+			cpu->memory_rw(cpu, cpu->mem, (int32_t)(DEC_PROM_STRINGS
+			    + i + strlen((char *)buf)), &ch2, sizeof(char),
+			    MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
+			if (nmatches == (int)strlen((char *)buf) && ch2=='=') {
+				cpu->cd.mips.gpr[MIPS_GPR_V0] =
+				    DEC_PROM_STRINGS + i +
+				    strlen((char *)buf) + 1;
+				return 1;
+			}
+		}
+		/*  Return NULL if string wasn't found.  */
+		fatal("[ DEC PROM getenv(\"%s\"): WARNING: Not in "
+		    "environment! ]\n", buf);
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0x6c:		/*  ulong slot_address(int sn)  */
+		debug("[ DEC PROM slot_address(%i) ]\n",
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
+		/*  TODO:  This is too hardcoded.  */
+		/*  TODO 2:  Should these be physical or virtual addresses?  */
+		switch (cpu->machine->machine_subtype) {
+		case MACHINE_DEC_3MAX_5000:
+			slot_base = KN02_PHYS_TC_0_START;/*  0x1e000000  */
+			slot_size = 4*1048576;		 /*  4 MB  */
+			break;
+		case MACHINE_DEC_3MIN_5000:
+			slot_base = 0x10000000;
+			slot_size = 0x4000000;		/*  64 MB  */
+			break;
+		case MACHINE_DEC_3MAXPLUS_5000:
+			slot_base = 0x1e000000;
+			slot_size = 0x800000;		/*  8 MB  */
+			break;
+		case MACHINE_DEC_MAXINE_5000:
+			slot_base = 0x10000000;
+			slot_size = 0x4000000;		/*  64 MB  */
+			break;
+		default:
+			fatal("warning: DEC PROM slot_address() "
+			    "unimplemented for this machine type\n");
+		}
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)(int32_t)
+		    (0x80000000 + slot_base + slot_size *
+		    cpu->cd.mips.gpr[MIPS_GPR_A0]);
+		break;
+	case 0x70:		/*  wbflush()  */
+		debug("[ DEC PROM wbflush(): TODO ]\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0x7c:		/*  clear_cache(addr, len)  */
+		debug("[ DEC PROM clear_cache(0x%x,%i) ]\n",
+		    (uint32_t)cpu->cd.mips.gpr[MIPS_GPR_A0],
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A1]);
+		/*  TODO  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;	/*  ?  */
+		break;
+	case 0x80:		/*  getsysid()  */
+		/*  debug("[ DEC PROM getsysid() ]\n");  */
+		/*  TODO:  why did I add the 0x82 stuff???  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = ((uint32_t)0x82 << 24)
+		    + (cpu->machine->machine_subtype << 16) + (0x3 << 8);
+		cpu->cd.mips.gpr[MIPS_GPR_V0] =
+		    (int64_t)(int32_t)cpu->cd.mips.gpr[MIPS_GPR_V0];
+		break;
+	case 0x84:		/*  getbitmap()  */
+		debug("[ DEC PROM getbitmap(0x%08x) ]\n",
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
+		store_buf(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0],
+		    (char *)cpu->machine->md.pmax->memmap,
+		    sizeof(struct dec_memmap));
+		cpu->cd.mips.gpr[MIPS_GPR_V0] =
+		    sizeof(cpu->machine->md.pmax->memmap->bitmap);
+		break;
+	case 0x88:		/*  disableintr()  */
+		debug("[ DEC PROM disableintr(): TODO ]\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0x8c:		/*  enableintr()  */
+		debug("[ DEC PROM enableintr(): TODO ]\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0x9c:		/*  halt()  */
+		debug("[ DEC PROM halt() ]\n");
+		cpu->running = 0;
+		break;
+	case 0xa4:		/*  gettcinfo()  */
+		/*
+		 *  These are just bogus values...  TODO
+		 *
+		 *   0:  revision
+		 *   4:  clock period in nano seconds
+		 *   8:  slot size in megabytes  TODO: not same for all models!
+		 *  12:  I/O timeout in cycles
+		 *  16:  DMA address range in megabytes
+		 *  20:  maximum DMA burst length
+		 *  24:  turbochannel parity (yes = 1)
+		 *  28:  reserved
+		 */
+		store_32bit_word(cpu, DEC_PROM_TCINFO +  0, 0);
+		store_32bit_word(cpu, DEC_PROM_TCINFO +  4, 50);
+		store_32bit_word(cpu, DEC_PROM_TCINFO +  8, 4);
+		store_32bit_word(cpu, DEC_PROM_TCINFO + 12, 10);
+		store_32bit_word(cpu, DEC_PROM_TCINFO + 16, 1);
+		store_32bit_word(cpu, DEC_PROM_TCINFO + 20, 100);
+		store_32bit_word(cpu, DEC_PROM_TCINFO + 24, 0);
+		store_32bit_word(cpu, DEC_PROM_TCINFO + 28, 0);
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = DEC_PROM_TCINFO;
+		break;
+	case 0xa8:		/*  int execute_cmd(char *)  */
+		i = 0;
+		while ((ch = mem_readchar(cpu, MIPS_GPR_A0, i++)) != '\0')
+			console_putchar(cpu->machine->main_console_handle, ch);
+		console_putchar(cpu->machine->main_console_handle, '\n');
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 0xac:		/*  rex()  */
+		debug("[ DEC PROM rex('%c') ]\n",
+		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
+		switch ((int32_t)cpu->cd.mips.gpr[MIPS_GPR_A0]) {
+		case 'h':
+			debug("DEC PROM: rex('h') ==> halt\n");
+			cpu->running = 0;
+			break;
+		case 'b':
+			debug("DEC PROM: rex('b') ==> reboot: TODO "
+			    "(halting CPU instead)\n");
+			cpu->running = 0;
+			break;
+		default:
+			fatal("DEC prom emulation: unknown rex() a0=0x%" PRIx64
+			    " ('%c')\n",
+			    (int64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
+			    (char) cpu->cd.mips.gpr[MIPS_GPR_A0]);
+			cpu->running = 0;
+		}
+		break;
+	default:
+		cpu_register_dump(cpu->machine, cpu, 1, 0x1);
+		printf("a0 points to: ");
+		for (i=0; i<40; i++) {
+			unsigned char chTmp = '\0';
+			cpu->memory_rw(cpu, cpu->mem, (int32_t)
+			    cpu->cd.mips.gpr[MIPS_GPR_A0] + i, &chTmp,
+			    sizeof(chTmp), MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
+			if (chTmp >= ' ' && chTmp < 126)
+				printf("%c", chTmp);
+			else
+				printf("[%02x]", chTmp);
+		}
+		printf("\n");
+		fatal("PROM emulation: unimplemented callback vector 0x%x\n",
+		    vector);
+		cpu->running = 0;
+	}
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/promemul/dec_prom.cc gxemul-0.7.0+dfsg/src/promemul/dec_prom.cc
--- gxemul-0.6.2/src/promemul/dec_prom.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/dec_prom.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,676 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: DECstation PROM emulation
- *
- *  Implementation note: Remember that only the lowest 32 bits of GPRs are
- *  actually valid when using dyntrans with e.g. R3000 CPUs.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-#include <sys/time.h>
-#include <sys/resource.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "cpu_mips.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "machine_pmax.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/dec_prom.h"
-#include "thirdparty/dec_5100.h"
-#include "thirdparty/dec_kn01.h"
-#include "thirdparty/dec_kn02.h"
-#include "thirdparty/dec_kn03.h"
-
-
-extern int quiet_mode;
-
-
-/*
- *  mem_readchar():
- *
- *  Reads a byte from emulated RAM, using a MIPS register as a base address.
- *  (Helper function.)
- */
-static unsigned char mem_readchar(struct cpu *cpu, int regbase, int offset)
-{
-	unsigned char ch;
-	cpu->memory_rw(cpu, cpu->mem, (int32_t)cpu->cd.mips.gpr[regbase] +
-	    offset, &ch, sizeof(ch), MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
-	return ch;
-}
-
-
-/*
- *  dec_jumptable_func():
- *
- *  The jumptable is located at the beginning of the PROM, at 0xbfc00000 + i*8,
- *  where i is the decimal function number. Many of these can be converted to
- *  an identical callback function.
- *
- *  Return value is non-zero if the vector number was converted into a callback
- *  function number, otherwise 0.
- *
- *	Vector	(dec)	Function
- *	0x0	0	reset()
- *	0x10	2	restart()
- *	0x18	3	reinit()
- *	0x30	6	open()
- *	0x38	7	read()
- *	0x58	11	lseek()
- *	0x68	13	putchar()
- *	0x88	17	printf()
- *	0x108	33	getenv2()
- */
-int dec_jumptable_func(struct cpu *cpu, int vector)
-{
-	int i;
-	static int file_opened = 0;
-	static int current_file_offset = 0;
-
-	switch (vector) {
-	case 0x0:	/*  reset()  */
-		/*  TODO  */
-		cpu->machine->exit_without_entering_debugger = 1;
-		cpu->running = 0;
-		break;
-	case 0x10:	/*  restart()  */
-		/*  TODO  */
-		cpu->machine->exit_without_entering_debugger = 1;
-		cpu->running = 0;
-		break;
-	case 0x18:	/*  reinit()  */
-		/*  TODO  */
-		cpu->machine->exit_without_entering_debugger = 1;
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0x30:	/*  open()  */
-		/*
-		 *  TODO: This is just a hack to allow Sprite/pmax' bootblock
-		 *  code to load /vmsprite. The filename argument (in A0)
-		 *  is ignored, and a file handle value of 1 is returned.
-		 */
-		if (file_opened) {
-			fatal("\ndec_jumptable_func(): opening more than one "
-			    "file isn't supported yet.\n");
-			cpu->running = 0;
-		}
-		file_opened = 1;
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 1;
-		break;
-	case 0x38:	/*  read(handle, ptr, length)  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = (uint64_t) -1;
-		if ((int32_t)cpu->cd.mips.gpr[MIPS_GPR_A2] > 0) {
-			int disk_id = diskimage_bootdev(cpu->machine, NULL);
-			int res;
-			unsigned char *tmp_buf;
-
-			CHECK_ALLOCATION(tmp_buf = (unsigned char *)
-			    malloc(cpu->cd.mips.gpr[MIPS_GPR_A2]));
-
-			res = diskimage_access(cpu->machine, disk_id,
-			    DISKIMAGE_SCSI, 0, current_file_offset, tmp_buf,
-			    cpu->cd.mips.gpr[MIPS_GPR_A2]);
-
-			/*  If the transfer was successful, transfer the data
-			    to emulated memory:  */
-			if (res) {
-				uint64_t dst = cpu->cd.mips.gpr[MIPS_GPR_A1];
-				store_buf(cpu, dst, (char *)tmp_buf,
-				    cpu->cd.mips.gpr[MIPS_GPR_A2]);
-				cpu->cd.mips.gpr[MIPS_GPR_V0] =
-				    cpu->cd.mips.gpr[MIPS_GPR_A2];
-				current_file_offset +=
-				    cpu->cd.mips.gpr[MIPS_GPR_A2];
-			}
-
-			free(tmp_buf);
-		}
-		break;
-	case 0x58:	/*  lseek(handle, offset[, whence])  */
-		/*  TODO  */
-		if (cpu->cd.mips.gpr[MIPS_GPR_A2] == 0)
-			current_file_offset = cpu->cd.mips.gpr[MIPS_GPR_A1];
-		else
-			fatal("WARNING! Unimplemented whence in "
-			    "dec_jumptable_func()\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0x68:	/*  putchar()  */
-		console_putchar(cpu->machine->main_console_handle,
-		    cpu->cd.mips.gpr[MIPS_GPR_A0]);
-		break;
-	case 0x88:	/*  printf()  */
-		return 0x30;
-	case 0x108:	/*  getenv2()  */
-		return 0x64;
-	default:
-		cpu_register_dump(cpu->machine, cpu, 1, 0x1);
-		printf("a0 points to: ");
-		for (i=0; i<40; i++) {
-			unsigned char ch = '\0';
-			cpu->memory_rw(cpu, cpu->mem,
-			    (int32_t)cpu->cd.mips.gpr[MIPS_GPR_A0] + i, &ch,
-			    sizeof(ch), MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
-			if (ch >= ' ' && ch < 126)
-				printf("%c", ch);
-			else
-				printf("[%02x]", ch);
-		}
-		printf("\n");
-		fatal("PROM emulation: unimplemented JUMP TABLE vector "
-		    "0x%x (decimal function %i)\n", vector, vector/8);
-		cpu->running = 0;
-	}
-
-	return 0;
-}
-
-
-/*
- *  decstation_prom_emul():
- *
- *  DECstation PROM emulation.
- *
- *  Callback functions:
- *	0x0c	strcmp()
- *	0x14	strlen()
- *	0x24	getchar()
- *	0x28	gets()
- *	0x2c	puts()
- *	0x30	printf()
- *	0x38	iopoll()
- *	0x54	bootinit()
- *	0x58	bootread()
- *	0x64	getenv()
- *	0x6c	slot_address()
- *	0x70	wbflush()
- *	0x7c	clear_cache()
- *	0x80	getsysid()
- *	0x84	getbitmap()
- *	0x88	disableintr()
- *	0x8c	enableintr()
- *	0x9c	halt()
- *	0xa4	gettcinfo()
- *	0xa8	execute_cmd()
- *	0xac	rex()
- */
-int decstation_prom_emul(struct cpu *cpu)
-{
-	int i, j, ch, argreg, argdata;
-	int vector = cpu->pc & 0xfff;
-	int callback = (cpu->pc & 0xf000)? 1 : 0;
-	unsigned char buf[100];
-	unsigned char ch1, ch2, ch3;
-	uint64_t tmpaddr, slot_base = 0x10000000, slot_size = 0;
-
-	if (!callback) {
-		vector = dec_jumptable_func(cpu, vector);
-		if (vector == 0)
-			return 1;
-	} else {
-		/*  Vector number is n*4, PC points to n*8.  */
-		vector /= 2;
-	}
-
-	switch (vector) {
-	case 0x0c:		/*  strcmp():  */
-		i = j = 0;
-		do {
-			ch1 = mem_readchar(cpu, MIPS_GPR_A0, i++);
-			ch2 = mem_readchar(cpu, MIPS_GPR_A1, j++);
-		} while (ch1 == ch2 && ch1 != '\0');
-
-		/*  If ch1=='\0', then strings are equal.  */
-		if (ch1 == '\0')
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		if ((signed char)ch1 > (signed char)ch2)
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = 1;
-		if ((signed char)ch1 < (signed char)ch2)
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = (uint64_t) -1;
-		break;
-	case 0x14:		/*  strlen():  */
-		i = 0;
-		do {
-			ch2 = mem_readchar(cpu, MIPS_GPR_A0, i++);
-		} while (ch2 != 0);
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = i - 1;
-		break;
-	case 0x24:		/*  getchar()  */
-		/*  debug("[ DEC PROM getchar() ]\n");  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = console_readchar(
-		    cpu->machine->main_console_handle);
-		break;
-	case 0x28:		/*  gets()  */
-		/*  debug("[ DEC PROM gets() ]\n");  */
-		tmpaddr = cpu->cd.mips.gpr[MIPS_GPR_A0];
-		i = 0;
-
-		/*  TODO: Make this not hang (block) the entire emulator  */
-
-		do {
-			while ((ch = console_readchar(
-			    cpu->machine->main_console_handle)) < 1)
-				;
-			if (ch == '\r')
-				ch = '\n';
-			ch2 = ch;
-
-			if (ch == '\b') {
-				if (i > 0) {
-					console_putchar(cpu->machine->
-					    main_console_handle, ch2);
-					console_putchar(cpu->machine->
-					    main_console_handle, ' ');
-					console_putchar(cpu->machine->
-					    main_console_handle, ch2);
-				}
-			} else
-				console_putchar(cpu->machine->
-				    main_console_handle, ch2);
-
-			fflush(stdout);
-
-			if (ch == '\n') {
-				/*  It seems that trailing newlines
-				    are not included in the buffer.  */
-			} else if (ch != '\b') {
-				cpu->memory_rw(cpu, cpu->mem, (int32_t)
-				    cpu->cd.mips.gpr[MIPS_GPR_A0] + i,
-				    &ch2, sizeof(ch2), MEM_WRITE,
-				    CACHE_DATA | NO_EXCEPTIONS);
-				i++;
-			} else {
-				if (i > 0)
-					i--;
-			}
-		} while (ch2 != '\n');
-
-		/*  Trailing nul-byte:  */
-		ch2 = '\0';
-		cpu->memory_rw(cpu, cpu->mem, (int32_t)
-		    cpu->cd.mips.gpr[MIPS_GPR_A0] + i, &ch2, sizeof(ch2),
-		    MEM_WRITE, CACHE_DATA | NO_EXCEPTIONS);
-
-		/*  Return the input argument:  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = cpu->cd.mips.gpr[MIPS_GPR_A0];
-		break;
-	case 0x2c:		/*  puts()  */
-		i = 0;
-		while ((ch = mem_readchar(cpu, MIPS_GPR_A0, i++)) != '\0')
-			console_putchar(cpu->machine->main_console_handle, ch);
-		console_putchar(cpu->machine->main_console_handle, '\n');
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0x30:		/*  printf()  */
-		if (cpu->machine->register_dump ||
-		    cpu->machine->instruction_trace)
-			debug("PROM printf(0x%08lx): \n",
-			    (long)cpu->cd.mips.gpr[MIPS_GPR_A0]);
-
-		i = 0; ch = -1; argreg = MIPS_GPR_A1;
-		while (ch != '\0') {
-			char printfbuf[8000];
-			size_t x;
-
-			printfbuf[0] = printfbuf[sizeof(printfbuf)-1] = '\0';
-
-			ch = mem_readchar(cpu, MIPS_GPR_A0, i++);
-			switch (ch) {
-			case '%':
-				ch = '0';
-				while (ch >= '0' && ch <= '9')
-					ch = mem_readchar(cpu,
-					    MIPS_GPR_A0, i++);
-
-				switch (ch) {
-				case '%':
-					strlcpy(printfbuf, "%%",
-					    sizeof(printfbuf));
-					break;
-				case 'c':
-				case 'd':
-				case 's':
-				case 'x':
-					/*  Get argument:  */
-					if (argreg > MIPS_GPR_A3) {
-#if 1
-						/*  Linux booters seem to go
-						    over the edge sometimes: */
-						ch = '\0';
-						strlcpy(printfbuf, "[...]\n",
-						    sizeof(printfbuf));
-#else
-						printf("[ decstation_prom_emul"
-						    "(): too many arguments ]");
-						/*  This reuses the last arg,
-						    which is utterly incorrect.
-						    (TODO)  */
-						argreg = MIPS_GPR_A3;
-#endif
-					}
-
-					ch2 = argdata =
-					    cpu->cd.mips.gpr[argreg];
-
-					switch (ch) {
-					case 'c':
-						snprintf(printfbuf, sizeof(
-						    printfbuf), "%c", ch2);
-						break;
-					case 'd':
-						snprintf(printfbuf, sizeof(
-						    printfbuf), "%d", argdata);
-						break;
-					case 'x':
-						snprintf(printfbuf, sizeof(
-						    printfbuf), "%x", argdata);
-						break;
-					case 's':
-						/*  Print a "%s" string.  */
-						j = 0; ch3 = '\n';
-						while (ch2) {
-							ch2 = mem_readchar(cpu,
-							    argreg, j++);
-							if (ch2) {
-								snprintf(
-								    printfbuf +
-								    strlen(
-								    printfbuf),
-								    sizeof(
-								    printfbuf)-
-								    1-strlen(
-								    printfbuf),
-								    "%c", ch2);
-								ch3 = ch2;
-							}
-						}
-						break;
-					}
-					argreg ++;
-					break;
-				default:
-					printf("[ unknown printf format char"
-					    " '%c' ]", ch);
-				}
-				break;
-			case '\0':
-				break;
-			default:
-				snprintf(printfbuf, sizeof(printfbuf),
-				    "%c", ch);
-			}
-
-			printfbuf[sizeof(printfbuf)-1] = '\0';
-
-			for (x=0; x<strlen(printfbuf); x++)
-				console_putchar(cpu->machine->
-				    main_console_handle, printfbuf[x]);
-		}
-		if (cpu->machine->register_dump ||
-		    cpu->machine->instruction_trace)
-			debug("\n");
-		fflush(stdout);
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0x54:		/*  bootinit()  */
-		/*  debug("[ DEC PROM bootinit(0x%08x): TODO ]\n",
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0x58:		/*  bootread(int b, void *buffer, int n)  */
-		/*
-		 *  Read data from the boot device.
-		 *  b is a sector number (512 bytes per sector),
-		 *  buffer is the destination address, and n
-		 *  is the number of _bytes_ to read.
-		 *
-		 *  TODO: Return value? NetBSD thinks that 0 is ok.
-		 */
-		debug("[ DEC PROM bootread(0x%x, 0x%08x, 0x%x) ]\n",
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0],
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A1],
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A2]);
-
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-
-		if ((int32_t)cpu->cd.mips.gpr[MIPS_GPR_A2] > 0) {
-			int disk_id = diskimage_bootdev(cpu->machine, NULL);
-			int res;
-			unsigned char *tmp_buf;
-
-			CHECK_ALLOCATION(tmp_buf = (unsigned char *)
-			    malloc(cpu->cd.mips.gpr[MIPS_GPR_A2]));
-
-			res = diskimage_access(cpu->machine, disk_id,
-			    DISKIMAGE_SCSI, 0,
-			    cpu->cd.mips.gpr[MIPS_GPR_A0] * 512, tmp_buf,
-			    cpu->cd.mips.gpr[MIPS_GPR_A2]);
-
-			/*  If the transfer was successful, transfer the data
-			    to emulated memory:  */
-			if (res) {
-				uint64_t dst = cpu->cd.mips.gpr[MIPS_GPR_A1];
-				if (dst < 0x80000000ULL)
-					dst |= 0x80000000;
-
-				store_buf(cpu, dst, (char *)tmp_buf,
-				    cpu->cd.mips.gpr[MIPS_GPR_A2]);
-				cpu->cd.mips.gpr[MIPS_GPR_V0] =
-				    cpu->cd.mips.gpr[MIPS_GPR_A2];
-			}
-
-			free(tmp_buf);
-		}
-		break;
-	case 0x64:		/*  getenv()  */
-		/*  Find the environment variable given by a0:  */
-		for (i=0; i<(int)sizeof(buf); i++)
-			cpu->memory_rw(cpu, cpu->mem, (int32_t)
-			    cpu->cd.mips.gpr[MIPS_GPR_A0] + i, &buf[i],
-			    sizeof(char), MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
-		buf[sizeof(buf)-1] = '\0';
-		debug("[ DEC PROM getenv(\"%s\") ]\n", buf);
-		for (i=0; i<0x1000; i++) {
-			/*  Matching string at offset i?  */
-			int nmatches = 0;
-			for (j=0; j<(int32_t)strlen((char *)buf); j++) {
-				cpu->memory_rw(cpu, cpu->mem, (int32_t)
-				    (DEC_PROM_STRINGS + i + j), &ch2,
-				    sizeof(char), MEM_READ, CACHE_DATA |
-				    NO_EXCEPTIONS);
-				if (ch2 == buf[j])
-					nmatches++;
-			}
-			cpu->memory_rw(cpu, cpu->mem, (int32_t)(DEC_PROM_STRINGS
-			    + i + strlen((char *)buf)), &ch2, sizeof(char),
-			    MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
-			if (nmatches == (int)strlen((char *)buf) && ch2=='=') {
-				cpu->cd.mips.gpr[MIPS_GPR_V0] =
-				    DEC_PROM_STRINGS + i +
-				    strlen((char *)buf) + 1;
-				return 1;
-			}
-		}
-		/*  Return NULL if string wasn't found.  */
-		fatal("[ DEC PROM getenv(\"%s\"): WARNING: Not in "
-		    "environment! ]\n", buf);
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0x6c:		/*  ulong slot_address(int sn)  */
-		debug("[ DEC PROM slot_address(%i) ]\n",
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
-		/*  TODO:  This is too hardcoded.  */
-		/*  TODO 2:  Should these be physical or virtual addresses?  */
-		switch (cpu->machine->machine_subtype) {
-		case MACHINE_DEC_3MAX_5000:
-			slot_base = KN02_PHYS_TC_0_START;/*  0x1e000000  */
-			slot_size = 4*1048576;		 /*  4 MB  */
-			break;
-		case MACHINE_DEC_3MIN_5000:
-			slot_base = 0x10000000;
-			slot_size = 0x4000000;		/*  64 MB  */
-			break;
-		case MACHINE_DEC_3MAXPLUS_5000:
-			slot_base = 0x1e000000;
-			slot_size = 0x800000;		/*  8 MB  */
-			break;
-		case MACHINE_DEC_MAXINE_5000:
-			slot_base = 0x10000000;
-			slot_size = 0x4000000;		/*  64 MB  */
-			break;
-		default:
-			fatal("warning: DEC PROM slot_address() "
-			    "unimplemented for this machine type\n");
-		}
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)(int32_t)
-		    (0x80000000 + slot_base + slot_size *
-		    cpu->cd.mips.gpr[MIPS_GPR_A0]);
-		break;
-	case 0x70:		/*  wbflush()  */
-		debug("[ DEC PROM wbflush(): TODO ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0x7c:		/*  clear_cache(addr, len)  */
-		debug("[ DEC PROM clear_cache(0x%x,%i) ]\n",
-		    (uint32_t)cpu->cd.mips.gpr[MIPS_GPR_A0],
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A1]);
-		/*  TODO  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;	/*  ?  */
-		break;
-	case 0x80:		/*  getsysid()  */
-		/*  debug("[ DEC PROM getsysid() ]\n");  */
-		/*  TODO:  why did I add the 0x82 stuff???  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = ((uint32_t)0x82 << 24)
-		    + (cpu->machine->machine_subtype << 16) + (0x3 << 8);
-		cpu->cd.mips.gpr[MIPS_GPR_V0] =
-		    (int64_t)(int32_t)cpu->cd.mips.gpr[MIPS_GPR_V0];
-		break;
-	case 0x84:		/*  getbitmap()  */
-		debug("[ DEC PROM getbitmap(0x%08x) ]\n",
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
-		store_buf(cpu, cpu->cd.mips.gpr[MIPS_GPR_A0],
-		    (char *)cpu->machine->md.pmax->memmap,
-		    sizeof(struct dec_memmap));
-		cpu->cd.mips.gpr[MIPS_GPR_V0] =
-		    sizeof(cpu->machine->md.pmax->memmap->bitmap);
-		break;
-	case 0x88:		/*  disableintr()  */
-		debug("[ DEC PROM disableintr(): TODO ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0x8c:		/*  enableintr()  */
-		debug("[ DEC PROM enableintr(): TODO ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0x9c:		/*  halt()  */
-		debug("[ DEC PROM halt() ]\n");
-		cpu->machine->exit_without_entering_debugger = 1;
-		cpu->running = 0;
-		break;
-	case 0xa4:		/*  gettcinfo()  */
-		/*
-		 *  These are just bogus values...  TODO
-		 *
-		 *   0:  revision
-		 *   4:  clock period in nano seconds
-		 *   8:  slot size in megabytes  TODO: not same for all models!
-		 *  12:  I/O timeout in cycles
-		 *  16:  DMA address range in megabytes
-		 *  20:  maximum DMA burst length
-		 *  24:  turbochannel parity (yes = 1)
-		 *  28:  reserved
-		 */
-		store_32bit_word(cpu, DEC_PROM_TCINFO +  0, 0);
-		store_32bit_word(cpu, DEC_PROM_TCINFO +  4, 50);
-		store_32bit_word(cpu, DEC_PROM_TCINFO +  8, 4);
-		store_32bit_word(cpu, DEC_PROM_TCINFO + 12, 10);
-		store_32bit_word(cpu, DEC_PROM_TCINFO + 16, 1);
-		store_32bit_word(cpu, DEC_PROM_TCINFO + 20, 100);
-		store_32bit_word(cpu, DEC_PROM_TCINFO + 24, 0);
-		store_32bit_word(cpu, DEC_PROM_TCINFO + 28, 0);
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = DEC_PROM_TCINFO;
-		break;
-	case 0xa8:		/*  int execute_cmd(char *)  */
-		i = 0;
-		while ((ch = mem_readchar(cpu, MIPS_GPR_A0, i++)) != '\0')
-			console_putchar(cpu->machine->main_console_handle, ch);
-		console_putchar(cpu->machine->main_console_handle, '\n');
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 0xac:		/*  rex()  */
-		debug("[ DEC PROM rex('%c') ]\n",
-		    (int)cpu->cd.mips.gpr[MIPS_GPR_A0]);
-		switch ((int32_t)cpu->cd.mips.gpr[MIPS_GPR_A0]) {
-		case 'h':
-			debug("DEC PROM: rex('h') ==> halt\n");
-			cpu->machine->exit_without_entering_debugger = 1;
-			cpu->running = 0;
-			break;
-		case 'b':
-			debug("DEC PROM: rex('b') ==> reboot: TODO "
-			    "(halting CPU instead)\n");
-			cpu->machine->exit_without_entering_debugger = 1;
-			cpu->running = 0;
-			break;
-		default:
-			fatal("DEC prom emulation: unknown rex() a0=0x%" PRIx64
-			    " ('%c')\n",
-			    (int64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
-			    (char) cpu->cd.mips.gpr[MIPS_GPR_A0]);
-			cpu->running = 0;
-		}
-		break;
-	default:
-		cpu_register_dump(cpu->machine, cpu, 1, 0x1);
-		printf("a0 points to: ");
-		for (i=0; i<40; i++) {
-			unsigned char chTmp = '\0';
-			cpu->memory_rw(cpu, cpu->mem, (int32_t)
-			    cpu->cd.mips.gpr[MIPS_GPR_A0] + i, &chTmp,
-			    sizeof(chTmp), MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
-			if (chTmp >= ' ' && chTmp < 126)
-				printf("%c", chTmp);
-			else
-				printf("[%02x]", chTmp);
-		}
-		printf("\n");
-		fatal("PROM emulation: unimplemented callback vector 0x%x\n",
-		    vector);
-		cpu->running = 0;
-	}
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/promemul/dreamcast.c gxemul-0.7.0+dfsg/src/promemul/dreamcast.c
--- gxemul-0.6.2/src/promemul/dreamcast.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/dreamcast.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,390 @@
+/*
+ *  Copyright (C) 2006-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Dreamcast PROM emulation
+ *
+ *  NOTE: This module probably only emulates enough system/BIOS calls to let
+ *  NetBSD/dreamcast, Linux/dreamcast, and various KOS demos run. Don't expect
+ *  it do be fully functional.
+ *
+ *  Dreamcast memory layout during startup:
+ *
+ *  0xa0000000: 2 MB ROM/BIOS. This is copied into RAM (0x8c000000) during
+ *              bootup by the real BIOS. In GXemul's fake PROM implementation,
+ *              the only thing present at 0xa0000000 is an opcode which
+ *              triggers a reboot/shutdown of the emulator.
+ *
+ *  0x8c000000 - 0x8c0000ff: Various variables and vectors.
+ *	  pointer (32-bit word) at 0x8c0000b0: SYSINFO
+ *	  pointer (32-bit word) at 0x8c0000b4: ROMFONT
+ *	  pointer (32-bit word) at 0x8c0000b8: FLASHROM
+ *	  pointer (32-bit word) at 0x8c0000bc: GDROM
+ *	  pointer (32-bit word) at 0x8c0000c0: (?) something
+ *	  pointer (32-bit word) at 0x8c0000e0: "main menu" call, or "continue
+ *					       booting" (?) or something.
+ *
+ *  0x8c000100: Not on a real Dreamcast, but in GXemul: This area is filled with
+ *              a special invalid instruction. Each instruction slot corresponds
+ *              to one of the pointers above (SYSINFO, ROMFONT, etc).
+ *
+ *  0x8c008000: This is where the first 32KB of the data track of a CDROM
+ *              gets loaded, also known as the "IP.BIN" part.
+ *
+ *  0x8c010000: This is where the first binary executable gets loaded. The name
+ *              of the executable is given in IP.BIN, and refers to the ISO9660
+ *              filename on the CDROM. A common file name is "1ST_READ.BIN".
+ *
+ *  See http://mc.pp.se/dc/syscalls.html for a description of what the
+ *  PROM syscalls do. The symbolic names in this module are the same as on
+ *  that page.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+
+#include "cpu.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "thirdparty/dreamcast_pvr.h"
+
+/*  The ROM FONT seems to be located just after 1MB, in a real Dreamcast:  */
+#define	DREAMCAST_ROMFONT_BASE		0x80100020
+extern unsigned char font8x16[];
+
+/*  Where the machine ID (64-bit) is stored.  */
+#define	DREAMCAST_MACHINE_ID_ADDRESS	0x80000068
+
+
+static int booting_from_cdrom = 0;
+
+
+/*
+ *  dreamcast_romfont_init()
+ *
+ *  Initialize the ROM font.
+ */
+static void dreamcast_romfont_init(struct machine *machine)
+{
+	struct cpu *cpu = machine->cpus[0];
+	int i, y, v;
+	uint64_t d = DREAMCAST_ROMFONT_BASE;
+
+	/*
+	 *  288 narrow glyphs (12 x 24 pixels):
+	 *
+	 *  Glyphs 1-94 are ASCII characters 33-126, according to
+	 *  http://mc.pp.se/dc/syscalls.html#vecB4
+	 *
+	 *  syscalls.html says "(As there is no glyph for ASCII space, use
+	 *  glyph 96 = ISO-8859-1 unbreakable space instead.)", but this does
+	 *  not seem to work. Marcus Comstedt's own example (video.s) uses
+	 *  char 288 for space instead (but the comment says char 72).
+	 *
+	 *  TODO: A better looking font. This simply reuses the standard 8x16
+	 *  font, which looks odd in Dreamcast programs.
+	 */
+	for (i=0; i<288; i++) {
+		for (y=0; y<24; y+=2) {
+			if (y <= 1 || y >= 22)
+				v = 0;
+			else
+				v = random();
+			store_byte(cpu, d++, v & 0x3f);
+			store_byte(cpu, d++, v & 0xc3);
+			store_byte(cpu, d++, v & 0xfc);
+		}
+	}
+
+	for (i=1; i<=94; i++) {
+		d = DREAMCAST_ROMFONT_BASE + i * (24 * 3 / 2);
+		int c = 32 + i;
+		int u;
+		for (y=0; y<24; y+=2) {
+			if (y < 4 || y >= 20)
+				u = v = 0x00;
+			else
+				u = font8x16[c*16 + (y-4)], v = font8x16[c*16 + (y-4+1)];
+
+			//  00 00 u7 u6 u5 u4 u3 u2 u1 u0 00 00
+			//  00 00 v7 v6 v5 v4 v3 v2 v1 v0 00 00
+			//  becomes:
+			//  first byte:   00 00 u7 u6 u5 u4 u3 u2
+			//  second byte:  u1 u0 00 00 00 00 v7 v6
+			//  third byte:   v5 v4 v3 v2 v1 v0 00 00
+			store_byte(cpu, d++, u >> 2);
+			store_byte(cpu, d++, (u << 6) | (v >> 6));
+			store_byte(cpu, d++, v << 2);
+		}
+	}
+	
+	// "ISO-8859-1 characters 160-255" (at pos 96..191):
+	for (i=96; i<=191; i++) {
+		d = DREAMCAST_ROMFONT_BASE + i * (24 * 3 / 2);
+		int c = i - 96 + 160;
+		int u;
+		for (y=0; y<24; y+=2) {
+			if (y < 4 || y >= 20)
+				u = v = 0;
+			else
+				u = font8x16[c*16 + (y-4)], v = font8x16[c*16 + (y-4+1)];
+
+			store_byte(cpu, d++, u >> 2);
+			store_byte(cpu, d++, (u << 6) | (v >> 6));
+			store_byte(cpu, d++, v << 2);
+		}
+	}
+
+	d = DREAMCAST_ROMFONT_BASE + 289 * (24 * 3 / 2);
+
+	/*  7078 wide glyphs (24 x 24 pixels):  */
+	for (i=1; i<7078; i++) {
+		for (y=0; y<24; y++) {
+			if (y <= 1 || y >= 22)
+				v = 0;
+			else
+				v = 0xff;
+			store_byte(cpu, d++, v & 0x3f);
+			store_byte(cpu, d++, v);
+			store_byte(cpu, d++, v & 0xfc);
+		}
+	}
+
+	/*  129 VME icons (32 x 32 pixels):  */
+	for (i=0; i<129; i++) {
+		for (y=0; y<32; y++) {
+			if (y <= 1 || y >= 30)
+				v = 0;
+			else
+				v = random();
+			store_byte(cpu, d++, v & 0x3f);
+			store_byte(cpu, d++, v);
+			store_byte(cpu, d++, v);
+			store_byte(cpu, d++, v & 0xfc);
+		}
+	}
+}
+
+
+/*
+ *  dreamcast_machine_setup():
+ *
+ *  Initializes pointers to Dreamcast PROM syscalls.
+ */
+void dreamcast_machine_setup(struct machine *machine)
+{
+	int i;
+	struct cpu *cpu = machine->cpus[0];
+
+	for (i=0; i<0x50; i+=sizeof(uint32_t)) {
+		/*  Store pointer to PROM routine...  */
+		store_32bit_word(cpu, 0x8c0000b0 + i, 0x8c000100 + i);
+
+		/*  ... which contains only 1 instruction, a special
+		    opcode which triggers PROM emulation:  */
+		store_16bit_word(cpu, 0x8c000100 + i, SH_INVALID_INSTR);
+	}
+
+	/*  PROM reboot, in case someone jumps to 0xa0000000:  */
+	store_16bit_word(cpu, 0xa0000000, SH_INVALID_INSTR);
+
+	/*  Machine ID (64-bit):  */
+	store_64bit_word(cpu, DREAMCAST_MACHINE_ID_ADDRESS, 0x0000000000000000ULL);
+
+	dreamcast_romfont_init(machine);
+
+	/*  Return address, if the user program returns: exit.  */
+	cpu->cd.sh.pr = 0x8c0000e0 + (0x100 - 0xb0);
+
+	/*  Stack starting at end of RAM.  */
+	cpu->cd.sh.r[15] = 0x8c000000 + 16 * 1048576;
+}
+
+
+/*
+ *  dreamcast_emul():
+ *
+ *  We end up here if someone branched or called to 0x8c000100 + ofs,
+ *  where ofs is a small number. These addresses correspond to the code reading
+ *  a pointer from 0x8c0000b0 + ofs and calling it.
+ *
+ *  See http://mc.pp.se/dc/syscalls.html for more details.
+ */
+void dreamcast_emul(struct cpu *cpu)
+{
+	// cpu->pc is the address where PROM emulation was triggered, but
+	// what we are after is the indirect vector that was used to fetch
+	// that address.
+	uint32_t vectorAddr = ((cpu->pc & 0x00ffffff) - 0x100 + 0xb0) | 0x8c000000;
+
+	int r1 = cpu->cd.sh.r[1];
+	int r6 = cpu->cd.sh.r[6];
+	int r7 = cpu->cd.sh.r[7];
+
+	/*  Special case: Reboot  */
+	if ((uint32_t)cpu->pc == 0x80000000 || (uint32_t)cpu->pc == 0xa0000000) {
+		debugmsg(SUBSYS_PROMEMUL, "dreamcast", VERBOSITY_WARNING, "rebooting");
+		cpu->running = 0;
+		return;
+	}
+
+	switch (vectorAddr) {
+
+	case 0x8c0000b0:
+		/*  SYSINFO  */
+		switch (r7) {
+		case 0:	/*  SYSINFO_INIT: Ignored for now.  */
+			debugmsg(SUBSYS_PROMEMUL, "dreamcast", VERBOSITY_INFO, "SYSINFO_INIT: ignored for now");
+			break;
+		case 3:	/*  SYSINFO_ID:  */
+			cpu->cd.sh.r[0] = (uint32_t)DREAMCAST_MACHINE_ID_ADDRESS;
+			break;
+		default:debugmsg(SUBSYS_PROMEMUL, "dreamcast", VERBOSITY_ERROR, "SYSINFO: Unimplemented r7=%i", r7);
+			goto bad;
+		}
+		break;
+
+	case 0x8c0000b4:
+		/*  ROMFONT  */
+		switch (r1) {
+		case 0:	/*  ROMFONT_ADDRESS  */
+			cpu->cd.sh.r[0] = DREAMCAST_ROMFONT_BASE;
+			break;
+		default:debugmsg(SUBSYS_PROMEMUL, "dreamcast", VERBOSITY_ERROR, "ROMFONT: Unimplemented r1=%i", r1);
+			goto bad;
+		}
+		break;
+
+	case 0x8c0000b8:
+		/*  FLASHROM  */
+		switch (r7) {
+		case 0:	/*  FLASHROM_INFO  */
+			/*  TODO  */
+			cpu->cd.sh.r[0] = (uint32_t) -1;
+			break;
+		case 1:	/*  FLASHROM_READ  */
+			/*  TODO  */
+			cpu->cd.sh.r[0] = (uint32_t) -1;
+			break;
+		default:debugmsg(SUBSYS_PROMEMUL, "dreamcast", VERBOSITY_ERROR, "FLASHROM: Unimplemented r7=%i", r7);
+			goto bad;
+		}
+		break;
+
+	case 0x8c0000bc:
+		switch ((int32_t)r6) {
+		case 0:	/*  GD-ROM emulation  */
+			switch (r7) {
+			case 0:	/*  GDROM_SEND_COMMAND  */
+				/*  TODO  */
+				cpu->cd.sh.r[0] = (uint32_t) -1;
+				break;
+			case 1:	/*  GDROM_CHECK_COMMAND  */
+				/*  TODO  */
+				cpu->cd.sh.r[0] = 0;
+				break;
+			case 2:	/*  GDROM_MAINLOOP  */
+				/*  TODO  */
+				break;
+			case 3:	/*  GDROM_INIT  */
+				/*  TODO: Do something here?  */
+				break;
+			case 4:	/*  GDROM_CHECK_DRIVE  */
+				/*  TODO: Return status words  */
+				break;
+			default:debugmsg(SUBSYS_PROMEMUL, "dreamcast", VERBOSITY_ERROR, "GDROM: Unimplemented r7=%i", r7);
+				goto bad;
+			}
+			break;
+		default:debugmsg(SUBSYS_PROMEMUL, "dreamcast", VERBOSITY_ERROR, "0xbc: Unimplemented r6=%i", r6);
+			goto bad;
+		}
+		break;
+
+	case 0x8c0000e0:
+		/*
+		 *  This seems to have two uses:
+		 *
+		 *  1. KallistiOS calls this from arch_menu(), i.e. to return
+		 *     from a running program.
+		 *  2. The "licence code" in the IP.BIN code when booting from
+		 *     a bootable CD image calls this once the license screen
+		 *     has been displayed, and it wants the ROM to jump to
+		 *     0x8c00b800 ("Bootstrap 1").
+		 *
+		 *  The easiest way to support both is probably to keep track
+		 *  of whether the IP.BIN code was started by the (software)
+		 *  ROM emulation code, or not.
+		 */
+		if (booting_from_cdrom) {
+			debugmsg(SUBSYS_PROMEMUL, "dreamcast", VERBOSITY_INFO, "Switching to bootstrap 1");
+
+			booting_from_cdrom = 0;
+
+			// Jump to bootstrap 1
+			cpu->pc = 0x8c00b800;
+			return;
+		} else {
+			debugmsg(SUBSYS_PROMEMUL, "dreamcast", VERBOSITY_WARNING, "Returning to main menu.");
+			cpu->running = 0;
+		}
+		break;
+
+	case 0x8c0000f0:
+		/*
+		 *  GXemul hack:
+		 *
+		 *  The vector (word) at 0x8c0000f0 contains the value 0x8c000140.
+		 *
+		 *  By jumping to this address (0x8c000140), a "boot from
+		 *  CDROM" is simulated. Control is transfered to the license
+		 *  code in the loaded IP.BIN file.
+		 */
+		debugmsg(SUBSYS_PROMEMUL, "dreamcast", VERBOSITY_INFO, "boot from CDROM");
+		booting_from_cdrom = 1;
+		cpu->pc = 0x8c008300;
+		return;
+
+	default:goto bad;
+	}
+
+	/*  Return from subroutine:  */
+	cpu->pc = cpu->cd.sh.pr;
+
+	return;
+
+bad:
+	cpu_register_dump(cpu->machine, cpu, 1, 0);
+	printf("\n");
+	fatal("[ dreamcast_emul(): unimplemented dreamcast PROM call, "
+	    "pc=0x%08" PRIx32" (vectorAddr=0x%08" PRIx32") ]\n", (uint32_t)cpu->pc, vectorAddr);
+	cpu->running = 0;
+	return;
+}
+
diff -Nru gxemul-0.6.2/src/promemul/dreamcast.cc gxemul-0.7.0+dfsg/src/promemul/dreamcast.cc
--- gxemul-0.6.2/src/promemul/dreamcast.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/dreamcast.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,389 +0,0 @@
-/*
- *  Copyright (C) 2006-2014  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Dreamcast PROM emulation
- *
- *  NOTE: This module probably only emulates enough system/BIOS calls to let
- *  NetBSD/dreamcast, Linux/dreamcast, and various KOS demos run. Don't expect
- *  it do be fully functional.
- *
- *  Dreamcast memory layout during startup:
- *
- *  0xa0000000: 2 MB ROM/BIOS. This is copied into RAM (0x8c000000) during
- *              bootup by the real BIOS. In GXemul's fake PROM implementation,
- *              the only thing present at 0xa0000000 is an opcode which
- *              triggers a reboot/shutdown of the emulator.
- *
- *  0x8c000000 - 0x8c0000ff: Various variables and vectors.
- *	  pointer (32-bit word) at 0x8c0000b0: SYSINFO
- *	  pointer (32-bit word) at 0x8c0000b4: ROMFONT
- *	  pointer (32-bit word) at 0x8c0000b8: FLASHROM
- *	  pointer (32-bit word) at 0x8c0000bc: GDROM
- *	  pointer (32-bit word) at 0x8c0000c0: (?) something
- *	  pointer (32-bit word) at 0x8c0000e0: "main menu" call, or "continue
- *					       booting" (?) or something.
- *
- *  0x8c000100: Not on a real Dreamcast, but in GXemul: This area is filled with
- *              a special invalid instruction. Each instruction slot corresponds
- *              to one of the pointers above (SYSINFO, ROMFONT, etc).
- *
- *  0x8c008000: This is where the first 32KB of the data track of a CDROM
- *              gets loaded, also known as the "IP.BIN" part.
- *
- *  0x8c010000: This is where the first binary executable gets loaded. The name
- *              of the executable is given in IP.BIN, and refers to the ISO9660
- *              filename on the CDROM. A common file name is "1ST_READ.BIN".
- *
- *  See http://mc.pp.se/dc/syscalls.html for a description of what the
- *  PROM syscalls do. The symbolic names in this module are the same as on
- *  that page.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-
-#include "cpu.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "thirdparty/dreamcast_pvr.h"
-
-/*  The ROM FONT seems to be located just after 1MB, in a real Dreamcast:  */
-#define	DREAMCAST_ROMFONT_BASE		0x80100020
-extern unsigned char font8x16[];
-
-/*  Where the machine ID (64-bit) is stored.  */
-#define	DREAMCAST_MACHINE_ID_ADDRESS	0x80000068
-
-
-static int booting_from_cdrom = 0;
-
-
-/*
- *  dreamcast_romfont_init()
- *
- *  Initialize the ROM font.
- */
-static void dreamcast_romfont_init(struct machine *machine)
-{
-	struct cpu *cpu = machine->cpus[0];
-	int i, y, v;
-	uint64_t d = DREAMCAST_ROMFONT_BASE;
-
-	/*
-	 *  288 narrow glyphs (12 x 24 pixels):
-	 *
-	 *  Glyphs 1-94 are ASCII characters 33-126, according to
-	 *  http://mc.pp.se/dc/syscalls.html#vecB4
-	 *
-	 *  syscalls.html says "(As there is no glyph for ASCII space, use
-	 *  glyph 96 = ISO-8859-1 unbreakable space instead.)", but this does
-	 *  not seem to work. Marcus Comstedt's own example (video.s) uses
-	 *  char 288 for space instead (but the comment says char 72).
-	 *
-	 *  TODO: A better looking font. This simply reuses the standard 8x16
-	 *  font, which looks odd in Dreamcast programs.
-	 */
-	for (i=0; i<288; i++) {
-		for (y=0; y<24; y+=2) {
-			if (y <= 1 || y >= 22)
-				v = 0;
-			else
-				v = random();
-			store_byte(cpu, d++, v & 0x3f);
-			store_byte(cpu, d++, v & 0xc3);
-			store_byte(cpu, d++, v & 0xfc);
-		}
-	}
-
-	for (i=1; i<=94; i++) {
-		d = DREAMCAST_ROMFONT_BASE + i * (24 * 3 / 2);
-		int c = 32 + i;
-		int u;
-		for (y=0; y<24; y+=2) {
-			if (y < 4 || y >= 20)
-				u = v = 0x00;
-			else
-				u = font8x16[c*16 + (y-4)], v = font8x16[c*16 + (y-4+1)];
-
-			//  00 00 u7 u6 u5 u4 u3 u2 u1 u0 00 00
-			//  00 00 v7 v6 v5 v4 v3 v2 v1 v0 00 00
-			//  becomes:
-			//  first byte:   00 00 u7 u6 u5 u4 u3 u2
-			//  second byte:  u1 u0 00 00 00 00 v7 v6
-			//  third byte:   v5 v4 v3 v2 v1 v0 00 00
-			store_byte(cpu, d++, u >> 2);
-			store_byte(cpu, d++, (u << 6) | (v >> 6));
-			store_byte(cpu, d++, v << 2);
-		}
-	}
-	
-	// "ISO-8859-1 characters 160-255" (at pos 96..191):
-	for (i=96; i<=191; i++) {
-		d = DREAMCAST_ROMFONT_BASE + i * (24 * 3 / 2);
-		int c = i - 96 + 160;
-		int u;
-		for (y=0; y<24; y+=2) {
-			if (y < 4 || y >= 20)
-				u = v = 0;
-			else
-				u = font8x16[c*16 + (y-4)], v = font8x16[c*16 + (y-4+1)];
-
-			store_byte(cpu, d++, u >> 2);
-			store_byte(cpu, d++, (u << 6) | (v >> 6));
-			store_byte(cpu, d++, v << 2);
-		}
-	}
-
-	d = DREAMCAST_ROMFONT_BASE + 289 * (24 * 3 / 2);
-
-	/*  7078 wide glyphs (24 x 24 pixels):  */
-	for (i=1; i<7078; i++) {
-		for (y=0; y<24; y++) {
-			if (y <= 1 || y >= 22)
-				v = 0;
-			else
-				v = 0xff;
-			store_byte(cpu, d++, v & 0x3f);
-			store_byte(cpu, d++, v);
-			store_byte(cpu, d++, v & 0xfc);
-		}
-	}
-
-	/*  129 VME icons (32 x 32 pixels):  */
-	for (i=0; i<129; i++) {
-		for (y=0; y<32; y++) {
-			if (y <= 1 || y >= 30)
-				v = 0;
-			else
-				v = random();
-			store_byte(cpu, d++, v & 0x3f);
-			store_byte(cpu, d++, v);
-			store_byte(cpu, d++, v);
-			store_byte(cpu, d++, v & 0xfc);
-		}
-	}
-}
-
-
-/*
- *  dreamcast_machine_setup():
- *
- *  Initializes pointers to Dreamcast PROM syscalls.
- */
-void dreamcast_machine_setup(struct machine *machine)
-{
-	int i;
-	struct cpu *cpu = machine->cpus[0];
-
-	for (i=0; i<0x50; i+=sizeof(uint32_t)) {
-		/*  Store pointer to PROM routine...  */
-		store_32bit_word(cpu, 0x8c0000b0 + i, 0x8c000100 + i);
-
-		/*  ... which contains only 1 instruction, a special
-		    opcode which triggers PROM emulation:  */
-		store_16bit_word(cpu, 0x8c000100 + i, SH_INVALID_INSTR);
-	}
-
-	/*  PROM reboot, in case someone jumps to 0xa0000000:  */
-	store_16bit_word(cpu, 0xa0000000, SH_INVALID_INSTR);
-
-	/*  Machine ID (64-bit):  */
-	store_64bit_word(cpu, DREAMCAST_MACHINE_ID_ADDRESS, 0x0000000000000000ULL);
-
-	dreamcast_romfont_init(machine);
-
-	/*  Return address, if the user program returns: exit.  */
-	cpu->cd.sh.pr = 0x8c0000e0 + (0x100 - 0xb0);
-
-	/*  Stack starting at end of RAM.  */
-	cpu->cd.sh.r[15] = 0x8c000000 + 16 * 1048576;
-}
-
-
-/*
- *  dreamcast_emul():
- *
- *  We end up here if someone branched or called to 0x8c000100 + ofs,
- *  where ofs is a small number. These addresses correspond to the code reading
- *  a pointer from 0x8c0000b0 + ofs and calling it.
- *
- *  See http://mc.pp.se/dc/syscalls.html for more details.
- */
-void dreamcast_emul(struct cpu *cpu)
-{
-	// cpu->pc is the address where PROM emulation was triggered, but
-	// what we are after is the indirect vector that was used to fetch
-	// that address.
-	uint32_t vectorAddr = ((cpu->pc & 0x00ffffff) - 0x100 + 0xb0) | 0x8c000000;
-
-	int r1 = cpu->cd.sh.r[1];
-	int r6 = cpu->cd.sh.r[6];
-	int r7 = cpu->cd.sh.r[7];
-
-	/*  Special case: Reboot  */
-	if ((uint32_t)cpu->pc == 0x80000000 || (uint32_t)cpu->pc == 0xa0000000) {
-	 	fatal("[ dreamcast reboot ]\n");
-		cpu->running = 0;
-		return;
-	}
-
-	switch (vectorAddr) {
-
-	case 0x8c0000b0:
-		/*  SYSINFO  */
-		switch (r7) {
-		case 0:	/*  SYSINFO_INIT: Ignored for now.  */
-			break;
-		case 3:	/*  SYSINFO_ID:  */
-			cpu->cd.sh.r[0] = (uint32_t)DREAMCAST_MACHINE_ID_ADDRESS;
-			break;
-		default:fatal("[ SYSINFO: Unimplemented r7=%i ]\n", r7);
-			goto bad;
-		}
-		break;
-
-	case 0x8c0000b4:
-		/*  ROMFONT  */
-		switch (r1) {
-		case 0:	/*  ROMFONT_ADDRESS  */
-			cpu->cd.sh.r[0] = DREAMCAST_ROMFONT_BASE;
-			break;
-		default:fatal("[ ROMFONT: Unimplemented r1=%i ]\n", r1);
-			goto bad;
-		}
-		break;
-
-	case 0x8c0000b8:
-		/*  FLASHROM  */
-		switch (r7) {
-		case 0:	/*  FLASHROM_INFO  */
-			/*  TODO  */
-			cpu->cd.sh.r[0] = (uint32_t) -1;
-			break;
-		case 1:	/*  FLASHROM_READ  */
-			/*  TODO  */
-			cpu->cd.sh.r[0] = (uint32_t) -1;
-			break;
-		default:fatal("[ FLASHROM: Unimplemented r7=%i ]\n", r7);
-			goto bad;
-		}
-		break;
-
-	case 0x8c0000bc:
-		switch ((int32_t)r6) {
-		case 0:	/*  GD-ROM emulation  */
-			switch (r7) {
-			case 0:	/*  GDROM_SEND_COMMAND  */
-				/*  TODO  */
-				cpu->cd.sh.r[0] = (uint32_t) -1;
-				break;
-			case 1:	/*  GDROM_CHECK_COMMAND  */
-				/*  TODO  */
-				cpu->cd.sh.r[0] = 0;
-				break;
-			case 2:	/*  GDROM_MAINLOOP  */
-				/*  TODO  */
-				break;
-			case 3:	/*  GDROM_INIT  */
-				/*  TODO: Do something here?  */
-				break;
-			case 4:	/*  GDROM_CHECK_DRIVE  */
-				/*  TODO: Return status words  */
-				break;
-			default:fatal("[ GDROM: Unimplemented r7=%i ]\n", r7);
-				goto bad;
-			}
-			break;
-		default:fatal("[ 0xbc: Unimplemented r6=0x%x ]\n", r6);
-			goto bad;
-		}
-		break;
-
-	case 0x8c0000e0:
-		/*
-		 *  This seems to have two uses:
-		 *
-		 *  1. KallistiOS calls this from arch_menu(), i.e. to return
-		 *     from a running program.
-		 *  2. The "licence code" in the IP.BIN code when booting from
-		 *     a bootable CD image calls this once the license screen
-		 *     has been displayed, and it wants the ROM to jump to
-		 *     0x8c00b800 ("Bootstrap 1").
-		 *
-		 *  The easiest way to support both is probably to keep track
-		 *  of whether the IP.BIN code was started by the (software)
-		 *  ROM emulation code, or not.
-		 */
-		if (booting_from_cdrom) {
-			debug("[ dreamcast: Switching to bootstrap 1 ]\n");
-
-			booting_from_cdrom = 0;
-
-			// Jump to bootstrap 1
-			cpu->pc = 0x8c00b800;
-			return;
-		} else {
-			fatal("[ dreamcast: Returning to main menu. ]\n");
-			cpu->running = 0;
-		}
-		break;
-
-	case 0x8c0000f0:
-		/*
-		 *  GXemul hack:
-		 *
-		 *  The vector (word) at 0x8c0000f0 contains the value 0x8c000140.
-		 *
-		 *  By jumping to this address (0x8c000140), a "boot from
-		 *  CDROM" is simulated. Control is transfered to the license
-		 *  code in the loaded IP.BIN file.
-		 */
-		debug("[ dreamcast boot from CDROM ]\n");
-		booting_from_cdrom = 1;
-		cpu->pc = 0x8c008300;
-		return;
-
-	default:goto bad;
-	}
-
-	/*  Return from subroutine:  */
-	cpu->pc = cpu->cd.sh.pr;
-
-	return;
-
-bad:
-	cpu_register_dump(cpu->machine, cpu, 1, 0);
-	printf("\n");
-	fatal("[ dreamcast_emul(): unimplemented dreamcast PROM call, "
-	    "pc=0x%08" PRIx32" (vectorAddr=0x%08" PRIx32") ]\n", (uint32_t)cpu->pc, vectorAddr);
-	cpu->running = 0;
-	return;
-}
-
diff -Nru gxemul-0.6.2/src/promemul/dreamcast_scramble.c gxemul-0.7.0+dfsg/src/promemul/dreamcast_scramble.c
--- gxemul-0.6.2/src/promemul/dreamcast_scramble.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/dreamcast_scramble.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,278 @@
+/*
+ *  COMMENT: Dreamcast emulation (helper module)
+ *
+ *  This is from Marcus Comstedt's Dreamcast development files
+ *  (http://mc.pp.se/dc/files/scramble.c). Public Domain, according to
+ *  Marcus software page.
+ *
+ *  The only modification done to make it fit into the emulator is that
+ *  it is executed internally from src/file.c.
+ */
+
+/*  #define STAND_ALONE  */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#define MAXCHUNK (2048*1024)
+
+static unsigned int seed;
+
+void my_srand(unsigned int n)
+{
+  seed = n & 0xffff;
+}
+
+unsigned int my_rand(void)
+{
+  seed = (seed * 2109 + 9273) & 0x7fff;
+  return (seed + 0xc000) & 0xffff;
+}
+
+void load(FILE *fh, unsigned char *ptr, unsigned long sz)
+{
+  if(fread(ptr, 1, sz, fh) != sz)
+    {
+      fprintf(stderr, "Read error!\n");
+      exit(1);
+    }
+}
+
+void load_chunk(FILE *fh, unsigned char *ptr, unsigned long sz)
+{
+  static int idx[MAXCHUNK/32];
+  int i;
+
+  /* Convert chunk size to number of slices */
+  sz /= 32;
+
+  /* Initialize index table with unity,
+     so that each slice gets loaded exactly once */
+  for(i = 0; i < (int)sz; i++)
+    idx[i] = i;
+
+  for(i = sz-1; i >= 0; --i)
+    {
+      /* Select a replacement index */
+      int x = (my_rand() * i) >> 16;
+
+      /* Swap */
+      int tmp = idx[i];
+      idx[i] = idx[x];
+      idx[x] = tmp;
+
+      /* Load resulting slice */
+      load(fh, ptr+32*idx[i], 32);
+    }
+}
+
+void load_file(FILE *fh, unsigned char *ptr, unsigned long filesz)
+{
+  unsigned long chunksz;
+
+  my_srand(filesz);
+
+  /* Descramble 2 meg blocks for as long as possible, then
+     gradually reduce the window down to 32 bytes (1 slice) */
+  for(chunksz = MAXCHUNK; chunksz >= 32; chunksz >>= 1)
+    while(filesz >= chunksz)
+      {
+	load_chunk(fh, ptr, chunksz);
+	filesz -= chunksz;
+	ptr += chunksz;
+      }
+
+  /* Load final incomplete slice */
+  if(filesz)
+    load(fh, ptr, filesz);
+}
+
+void read_file(char *filename, unsigned char **ptr, unsigned long *sz)
+{
+  FILE *fh = fopen(filename, "rb");
+  if(fh == NULL)
+    {
+      fprintf(stderr, "Can't open \"%s\".\n", filename);
+      exit(1);
+    }
+  if(fseek(fh, 0, SEEK_END)<0)
+    {
+      fprintf(stderr, "Seek error.\n");
+      exit(1);
+    }
+  *sz = ftell(fh);
+  *ptr = (unsigned char *) malloc(*sz);
+  if( *ptr == NULL )
+    {
+      fprintf(stderr, "Out of memory.\n");
+      exit(1);
+    }
+  if(fseek(fh, 0, SEEK_SET)<0)
+    {
+      fprintf(stderr, "Seek error.\n");
+      exit(1);
+    }
+  load_file(fh, *ptr, *sz);
+  fclose(fh);
+}
+
+void save(FILE *fh, unsigned char *ptr, unsigned long sz)
+{
+  if(fwrite(ptr, 1, sz, fh) != sz)
+    {
+      fprintf(stderr, "Write error!\n");
+      exit(1);
+    }
+}
+
+void save_chunk(FILE *fh, unsigned char *ptr, unsigned long sz)
+{
+  static int idx[MAXCHUNK/32];
+  int i;
+
+  /* Convert chunk size to number of slices */
+  sz /= 32;
+
+  /* Initialize index table with unity,
+     so that each slice gets saved exactly once */
+  for(i = 0; i < (int)sz; i++)
+    idx[i] = i;
+
+  for(i = sz-1; i >= 0; --i)
+    {
+      /* Select a replacement index */
+      int x = (my_rand() * i) >> 16;
+
+      /* Swap */
+      int tmp = idx[i];
+      idx[i] = idx[x];
+      idx[x] = tmp;
+
+      /* Save resulting slice */
+      save(fh, ptr+32*idx[i], 32);
+    }
+}
+
+void save_file(FILE *fh, unsigned char *ptr, unsigned long filesz)
+{
+  unsigned long chunksz;
+
+  my_srand(filesz);
+
+  /* Descramble 2 meg blocks for as long as possible, then
+     gradually reduce the window down to 32 bytes (1 slice) */
+  for(chunksz = MAXCHUNK; chunksz >= 32; chunksz >>= 1)
+    while(filesz >= chunksz)
+      {
+	save_chunk(fh, ptr, chunksz);
+	filesz -= chunksz;
+	ptr += chunksz;
+      }
+
+  /* Save final incomplete slice */
+  if(filesz)
+    save(fh, ptr, filesz);
+}
+
+void write_file(char *filename, unsigned char *ptr, unsigned long sz)
+{
+  FILE *fh = fopen(filename, "wb");
+  if(fh == NULL)
+    {
+      fprintf(stderr, "Can't open \"%s\".\n", filename);
+      exit(1);
+    }
+  save_file(fh, ptr, sz);
+  fclose(fh);
+}
+
+void dreamcast_descramble(char *src, char *dst)
+{
+  unsigned char *ptr = NULL;
+  unsigned long sz = 0;
+  FILE *fh;
+
+  read_file(src, &ptr, &sz);
+
+  fh = fopen(dst, "wb");
+  if(fh == NULL)
+    {
+      fprintf(stderr, "Can't open \"%s\".\n", dst);
+      exit(1);
+    }
+  if( fwrite(ptr, 1, sz, fh) != sz )
+    {
+      fprintf(stderr, "Write error.\n");
+      exit(1);
+    }
+  fclose(fh);
+  free(ptr);
+}
+
+void scramble(char *src, char *dst)
+{
+  unsigned char *ptr = NULL;
+  unsigned long sz = 0;
+  FILE *fh;
+
+  fh = fopen(src, "rb");
+  if(fh == NULL)
+    {
+      fprintf(stderr, "Can't open \"%s\".\n", src);
+      exit(1);
+    }
+  if(fseek(fh, 0, SEEK_END)<0)
+    {
+      fprintf(stderr, "Seek error.\n");
+      exit(1);
+    }
+  sz = ftell(fh);
+  ptr = (unsigned char *) malloc(sz);
+  if( ptr == NULL )
+    {
+      fprintf(stderr, "Out of memory.\n");
+      exit(1);
+    }
+  if(fseek(fh, 0, SEEK_SET)<0)
+    {
+      fprintf(stderr, "Seek error.\n");
+      exit(1);
+    }
+  if( fread(ptr, 1, sz, fh) != sz )
+    {
+      fprintf(stderr, "Read error.\n");
+      exit(1);
+    }
+  fclose(fh);
+
+  write_file(dst, ptr, sz);
+
+  free(ptr);
+}
+
+
+#ifdef STAND_ALONE
+
+int main(int argc, char *argv[])
+{
+  int opt = 0;
+
+  if(argc > 1 && !strcmp(argv[1], "-d"))
+    opt ++;
+
+  if(argc != 3+opt)
+    {
+      fprintf(stderr, "Usage: %s [-d] from to\n", argv[0]);
+      exit(1);
+    }
+  
+  if(opt)
+    dreamcast_descramble(argv[2], argv[3]);
+  else
+    scramble(argv[1], argv[2]);
+
+  return 0;
+}
+
+#endif
diff -Nru gxemul-0.6.2/src/promemul/dreamcast_scramble.cc gxemul-0.7.0+dfsg/src/promemul/dreamcast_scramble.cc
--- gxemul-0.6.2/src/promemul/dreamcast_scramble.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/dreamcast_scramble.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,278 +0,0 @@
-/*
- *  COMMENT: Dreamcast emulation (helper module)
- *
- *  This is from Marcus Comstedt's Dreamcast development files
- *  (http://mc.pp.se/dc/files/scramble.c). Public Domain, according to
- *  Marcus software page.
- *
- *  The only modification done to make it fit into the emulator is that
- *  it is executed internally from src/file.c.
- */
-
-/*  #define STAND_ALONE  */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#define MAXCHUNK (2048*1024)
-
-static unsigned int seed;
-
-void my_srand(unsigned int n)
-{
-  seed = n & 0xffff;
-}
-
-unsigned int my_rand(void)
-{
-  seed = (seed * 2109 + 9273) & 0x7fff;
-  return (seed + 0xc000) & 0xffff;
-}
-
-void load(FILE *fh, unsigned char *ptr, unsigned long sz)
-{
-  if(fread(ptr, 1, sz, fh) != sz)
-    {
-      fprintf(stderr, "Read error!\n");
-      exit(1);
-    }
-}
-
-void load_chunk(FILE *fh, unsigned char *ptr, unsigned long sz)
-{
-  static int idx[MAXCHUNK/32];
-  int i;
-
-  /* Convert chunk size to number of slices */
-  sz /= 32;
-
-  /* Initialize index table with unity,
-     so that each slice gets loaded exactly once */
-  for(i = 0; i < (int)sz; i++)
-    idx[i] = i;
-
-  for(i = sz-1; i >= 0; --i)
-    {
-      /* Select a replacement index */
-      int x = (my_rand() * i) >> 16;
-
-      /* Swap */
-      int tmp = idx[i];
-      idx[i] = idx[x];
-      idx[x] = tmp;
-
-      /* Load resulting slice */
-      load(fh, ptr+32*idx[i], 32);
-    }
-}
-
-void load_file(FILE *fh, unsigned char *ptr, unsigned long filesz)
-{
-  unsigned long chunksz;
-
-  my_srand(filesz);
-
-  /* Descramble 2 meg blocks for as long as possible, then
-     gradually reduce the window down to 32 bytes (1 slice) */
-  for(chunksz = MAXCHUNK; chunksz >= 32; chunksz >>= 1)
-    while(filesz >= chunksz)
-      {
-	load_chunk(fh, ptr, chunksz);
-	filesz -= chunksz;
-	ptr += chunksz;
-      }
-
-  /* Load final incomplete slice */
-  if(filesz)
-    load(fh, ptr, filesz);
-}
-
-void read_file(char *filename, unsigned char **ptr, unsigned long *sz)
-{
-  FILE *fh = fopen(filename, "rb");
-  if(fh == NULL)
-    {
-      fprintf(stderr, "Can't open \"%s\".\n", filename);
-      exit(1);
-    }
-  if(fseek(fh, 0, SEEK_END)<0)
-    {
-      fprintf(stderr, "Seek error.\n");
-      exit(1);
-    }
-  *sz = ftell(fh);
-  *ptr = (unsigned char *) malloc(*sz);
-  if( *ptr == NULL )
-    {
-      fprintf(stderr, "Out of memory.\n");
-      exit(1);
-    }
-  if(fseek(fh, 0, SEEK_SET)<0)
-    {
-      fprintf(stderr, "Seek error.\n");
-      exit(1);
-    }
-  load_file(fh, *ptr, *sz);
-  fclose(fh);
-}
-
-void save(FILE *fh, unsigned char *ptr, unsigned long sz)
-{
-  if(fwrite(ptr, 1, sz, fh) != sz)
-    {
-      fprintf(stderr, "Write error!\n");
-      exit(1);
-    }
-}
-
-void save_chunk(FILE *fh, unsigned char *ptr, unsigned long sz)
-{
-  static int idx[MAXCHUNK/32];
-  int i;
-
-  /* Convert chunk size to number of slices */
-  sz /= 32;
-
-  /* Initialize index table with unity,
-     so that each slice gets saved exactly once */
-  for(i = 0; i < (int)sz; i++)
-    idx[i] = i;
-
-  for(i = sz-1; i >= 0; --i)
-    {
-      /* Select a replacement index */
-      int x = (my_rand() * i) >> 16;
-
-      /* Swap */
-      int tmp = idx[i];
-      idx[i] = idx[x];
-      idx[x] = tmp;
-
-      /* Save resulting slice */
-      save(fh, ptr+32*idx[i], 32);
-    }
-}
-
-void save_file(FILE *fh, unsigned char *ptr, unsigned long filesz)
-{
-  unsigned long chunksz;
-
-  my_srand(filesz);
-
-  /* Descramble 2 meg blocks for as long as possible, then
-     gradually reduce the window down to 32 bytes (1 slice) */
-  for(chunksz = MAXCHUNK; chunksz >= 32; chunksz >>= 1)
-    while(filesz >= chunksz)
-      {
-	save_chunk(fh, ptr, chunksz);
-	filesz -= chunksz;
-	ptr += chunksz;
-      }
-
-  /* Save final incomplete slice */
-  if(filesz)
-    save(fh, ptr, filesz);
-}
-
-void write_file(char *filename, unsigned char *ptr, unsigned long sz)
-{
-  FILE *fh = fopen(filename, "wb");
-  if(fh == NULL)
-    {
-      fprintf(stderr, "Can't open \"%s\".\n", filename);
-      exit(1);
-    }
-  save_file(fh, ptr, sz);
-  fclose(fh);
-}
-
-void dreamcast_descramble(char *src, char *dst)
-{
-  unsigned char *ptr = NULL;
-  unsigned long sz = 0;
-  FILE *fh;
-
-  read_file(src, &ptr, &sz);
-
-  fh = fopen(dst, "wb");
-  if(fh == NULL)
-    {
-      fprintf(stderr, "Can't open \"%s\".\n", dst);
-      exit(1);
-    }
-  if( fwrite(ptr, 1, sz, fh) != sz )
-    {
-      fprintf(stderr, "Write error.\n");
-      exit(1);
-    }
-  fclose(fh);
-  free(ptr);
-}
-
-void scramble(char *src, char *dst)
-{
-  unsigned char *ptr = NULL;
-  unsigned long sz = 0;
-  FILE *fh;
-
-  fh = fopen(src, "rb");
-  if(fh == NULL)
-    {
-      fprintf(stderr, "Can't open \"%s\".\n", src);
-      exit(1);
-    }
-  if(fseek(fh, 0, SEEK_END)<0)
-    {
-      fprintf(stderr, "Seek error.\n");
-      exit(1);
-    }
-  sz = ftell(fh);
-  ptr = (unsigned char *) malloc(sz);
-  if( ptr == NULL )
-    {
-      fprintf(stderr, "Out of memory.\n");
-      exit(1);
-    }
-  if(fseek(fh, 0, SEEK_SET)<0)
-    {
-      fprintf(stderr, "Seek error.\n");
-      exit(1);
-    }
-  if( fread(ptr, 1, sz, fh) != sz )
-    {
-      fprintf(stderr, "Read error.\n");
-      exit(1);
-    }
-  fclose(fh);
-
-  write_file(dst, ptr, sz);
-
-  free(ptr);
-}
-
-
-#ifdef STAND_ALONE
-
-int main(int argc, char *argv[])
-{
-  int opt = 0;
-
-  if(argc > 1 && !strcmp(argv[1], "-d"))
-    opt ++;
-
-  if(argc != 3+opt)
-    {
-      fprintf(stderr, "Usage: %s [-d] from to\n", argv[0]);
-      exit(1);
-    }
-  
-  if(opt)
-    dreamcast_descramble(argv[2], argv[3]);
-  else
-    scramble(argv[1], argv[2]);
-
-  return 0;
-}
-
-#endif
diff -Nru gxemul-0.6.2/src/promemul/.index gxemul-0.7.0+dfsg/src/promemul/.index
--- gxemul-0.6.2/src/promemul/.index	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/.index	2021-11-27 09:42:23.000000000 +0000
@@ -1,10 +1,10 @@
-arcbios.cc  ARCBIOS and ARCS emulation
-dec_prom.cc  DECstation PROM emulation
-dreamcast.cc  Dreamcast PROM emulation
-dreamcast_scramble.cc  Dreamcast emulation (helper module)
-luna88kprom.cc  LUNA 88K PROM emulation
-mvmeprom.cc  MVME PROM emulation
-of.cc  OpenFirmware emulation
-ps2_bios.cc  Playstation 2 SIFBIOS emulation
-sh_ipl_g.cc  SH-IPL+G emulation
-yamon.cc  YAMON emulation
+arcbios.c  ARCBIOS and ARCS emulation
+dec_prom.c  DECstation PROM emulation
+dreamcast.c  Dreamcast PROM emulation
+dreamcast_scramble.c  Dreamcast emulation (helper module)
+luna88kprom.c  LUNA 88K PROM emulation
+mvmeprom.c  MVME PROM emulation
+of.c  OpenFirmware emulation
+ps2_bios.c  Playstation 2 SIFBIOS emulation
+sh_ipl_g.c  SH-IPL+G emulation
+yamon.c  YAMON emulation
diff -Nru gxemul-0.6.2/src/promemul/luna88kprom.c gxemul-0.7.0+dfsg/src/promemul/luna88kprom.c
--- gxemul-0.6.2/src/promemul/luna88kprom.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/luna88kprom.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,111 @@
+/*
+ *  Copyright (C) 2018-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: LUNA 88K PROM emulation
+ *
+ *  For LUNA 88K emulation.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/luna88k_board.h"
+
+
+/*
+ *  luna88kprom_init():
+ */
+void luna88kprom_init(struct machine *machine)
+{
+	struct cpu *cpu = machine->cpus[0];
+
+        /*
+         *  Memory layout according to OpenBSD's locore0.S:
+         *
+         *      0x00000 - 0x00fff = trap vectors
+         *      0x01000 - 0x1ffff = ROM monitor work area
+         *      0x20000 - ...     = Boot loader jumps here
+	 *
+	 *  The boot loader stage before loading OpenBSD's kernel seems
+	 *  to be loaded at 0x00700000.
+         */
+ 
+        /*  0x00001100: ROM function table. See OpenBSD's machdep.c  */
+        store_32bit_word(cpu, 0x1100 + sizeof(uint32_t) * 3, 0x2030);       /*  ROM console getch  */
+        store_32bit_word(cpu, 0x1100 + sizeof(uint32_t) * 4, 0x2040);       /*  ROM console putch  */
+
+        store_32bit_word(cpu, 0x2030, M88K_PROM_INSTR);
+        store_32bit_word(cpu, 0x2034, 0xf400c001);	/*  jmp (r1)  */
+
+        store_32bit_word(cpu, 0x2040, M88K_PROM_INSTR);
+        store_32bit_word(cpu, 0x2044, 0xf400c001);	/*  jmp (r1)  */
+  
+        /*  0x00001114: Framebuffer depth  */
+        store_32bit_word(cpu, 0x1114, machine->x11_md.in_use ? 1 : 0);
+}
+
+
+/*
+ *  luna88kprom_emul():
+ *
+ *  Input:
+ *	pc is used to figure out function number
+ *	r2 = first argument (for functions that take arguments)
+ *
+ *  Output:
+ *	r2 = result
+ */
+int luna88kprom_emul(struct cpu *cpu)
+{
+	int func = (cpu->pc & 0xf0) >> 4;
+
+	switch (func) {
+
+	case 4:
+		debugmsg(SUBSYS_PROMEMUL, "luna88k", VERBOSITY_DEBUG, "putchar 0x%02x", cpu->cd.m88k.r[2]);
+		console_putchar(cpu->machine->main_console_handle, cpu->cd.m88k.r[2]);
+		break;
+
+	default:
+		cpu_register_dump(cpu->machine, cpu, 1, 0);
+		cpu_register_dump(cpu->machine, cpu, 0, 1);
+		debugmsg(SUBSYS_PROMEMUL, "luna88k", VERBOSITY_ERROR, "unimplemented function 0x%" PRIx32, func);
+		cpu->running = 0;
+		return 0;
+	}
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/promemul/luna88kprom.cc gxemul-0.7.0+dfsg/src/promemul/luna88kprom.cc
--- gxemul-0.6.2/src/promemul/luna88kprom.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/luna88kprom.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,110 +0,0 @@
-/*
- *  Copyright (C) 2018  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: LUNA 88K PROM emulation
- *
- *  For LUNA 88K emulation.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/luna88k_board.h"
-
-
-/*
- *  luna88kprom_init():
- */
-void luna88kprom_init(struct machine *machine)
-{
-	struct cpu *cpu = machine->cpus[0];
-
-        /*
-         *  Memory layout according to OpenBSD's locore0.S:
-         *
-         *      0x00000 - 0x00fff = trap vectors
-         *      0x01000 - 0x1ffff = ROM monitor work area
-         *      0x20000 - ...     = Boot loader jumps here
-	 *
-	 *  The boot loader stage before loading OpenBSD's kernel seems
-	 *  to be loaded at 0x00700000.
-         */
- 
-        /*  0x00001100: ROM function table. See OpenBSD's machdep.c  */
-        store_32bit_word(cpu, 0x1100 + sizeof(uint32_t) * 3, 0x2030);       /*  ROM console getch  */
-        store_32bit_word(cpu, 0x1100 + sizeof(uint32_t) * 4, 0x2040);       /*  ROM console putch  */
-
-        store_32bit_word(cpu, 0x2030, M88K_PROM_INSTR);
-        store_32bit_word(cpu, 0x2034, 0xf400c001);	/*  jmp (r1)  */
-
-        store_32bit_word(cpu, 0x2040, M88K_PROM_INSTR);
-        store_32bit_word(cpu, 0x2044, 0xf400c001);	/*  jmp (r1)  */
-  
-        /*  0x00001114: Framebuffer depth  */
-        store_32bit_word(cpu, 0x1114, machine->x11_md.in_use ? 8 : 0);
-}
-
-
-/*
- *  luna88kprom_emul():
- *
- *  Input:
- *	pc is used to figure out function number
- *	r2 = first argument (for functions that take arguments)
- *
- *  Output:
- *	r2 = result
- */
-int luna88kprom_emul(struct cpu *cpu)
-{
-	int func = (cpu->pc & 0xf0) >> 4;
-
-	switch (func) {
-
-	case 4:
-		console_putchar(cpu->machine->main_console_handle, cpu->cd.m88k.r[2]);
-		break;
-
-	default:
-		cpu_register_dump(cpu->machine, cpu, 1, 0);
-		cpu_register_dump(cpu->machine, cpu, 0, 1);
-		fatal("[ LUNA88K PROM emulation: unimplemented function 0x%" PRIx32" ]\n", func);
-		cpu->running = 0;
-		return 0;
-	}
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/promemul/Makefile.skel gxemul-0.7.0+dfsg/src/promemul/Makefile.skel
--- gxemul-0.6.2/src/promemul/Makefile.skel	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -2,7 +2,7 @@
 #  Makefile for GXemul src/promemul
 #
 
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(DINCLUDE)
+CFLAGS=$(CWARNINGS) $(COPTIM) $(DINCLUDE)
 
 OBJS=arcbios.o dec_prom.o dreamcast.o dreamcast_scramble.o \
 	luna88kprom.o mvmeprom.o of.o ps2_bios.o sh_ipl_g.o yamon.o
diff -Nru gxemul-0.6.2/src/promemul/mvmeprom.c gxemul-0.7.0+dfsg/src/promemul/mvmeprom.c
--- gxemul-0.6.2/src/promemul/mvmeprom.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/mvmeprom.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,135 @@
+/*
+ *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: MVME PROM emulation
+ *
+ *  For mvme88k emulation.
+ *
+ *  TODO: Perhaps this could be reused for mvme68k emulation too?
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/mvmeprom.h"
+
+
+#define	MVMEPROM_BRDID_ADDR	0x1100
+
+
+/*
+ *  mvmeprom_init():
+ */
+void mvmeprom_init(struct machine *machine)
+{
+	struct cpu *cpu = machine->cpus[0];
+	struct mvmeprom_brdid mvmeprom_brdid;
+	uint32_t vbr = 0x00000000;
+	int model = 0x187;
+
+	switch (machine->machine_subtype) {
+	case MACHINE_MVME88K_187:  model = 0x187; break;
+	case MACHINE_MVME88K_188:  model = 0x188; break;
+	case MACHINE_MVME88K_197:  model = 0x197; break;
+	}
+
+	cpu->cd.m88k.cr[M88K_CR_VBR] = vbr;
+
+	/*  A magic prom call instruction, followed by an 'rte':  */
+	store_32bit_word(cpu, vbr + 8 * MVMEPROM_VECTOR, M88K_PROM_INSTR);
+	store_32bit_word(cpu, vbr + 8 * MVMEPROM_VECTOR + 4, 0xf400fc00);
+
+	/*  brdid struct:  */
+	memset(&mvmeprom_brdid, 0, sizeof(mvmeprom_brdid));
+	store_16bit_word_in_host(cpu, (unsigned char *)
+	    &(mvmeprom_brdid.model), model);
+	mvmeprom_brdid.speed[0] = '3';	/*  33 MHz, for now  */
+	mvmeprom_brdid.speed[1] = '3';
+	mvmeprom_brdid.speed[2] = '0';
+	mvmeprom_brdid.speed[3] = '0';
+	store_buf(cpu, MVMEPROM_BRDID_ADDR,
+	    (char *)&mvmeprom_brdid, sizeof(struct mvmeprom_brdid));
+}
+
+
+/*
+ *  mvmeprom_emul():
+ *
+ *  For MVME88K:
+ *
+ *  Input:
+ *	r9 = requested function number
+ *	r2 = first argument (for functions that take arguments)
+ *
+ *  Output:
+ *	r2 = result
+ */
+int mvmeprom_emul(struct cpu *cpu)
+{
+	int func = cpu->cd.m88k.r[9];
+
+	switch (func) {
+
+	case MVMEPROM_OUTCHR:
+		console_putchar(cpu->machine->main_console_handle,
+		    cpu->cd.m88k.r[2]);
+		break;
+
+	case MVMEPROM_OUTCRLF:
+		console_putchar(cpu->machine->main_console_handle, '\n');
+		break;
+
+	case MVMEPROM_EXIT:
+		fatal("[ MVME PROM: exit ]\n");
+		cpu->running = 0;
+		break;
+
+	case MVMEPROM_GETBRDID:
+		/*  Return a pointer in r2 to a mvmeprom_brdid struct.  */
+		cpu->cd.m88k.r[2] = MVMEPROM_BRDID_ADDR;
+		break;
+
+	default:
+		cpu_register_dump(cpu->machine, cpu, 1, 0);
+		cpu_register_dump(cpu->machine, cpu, 0, 1);
+		fatal("[ MVME PROM emulation: unimplemented function 0x%"
+		    PRIx32" ]\n", func);
+		cpu->running = 0;
+		return 0;
+	}
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/promemul/mvmeprom.cc gxemul-0.7.0+dfsg/src/promemul/mvmeprom.cc
--- gxemul-0.6.2/src/promemul/mvmeprom.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/mvmeprom.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,135 +0,0 @@
-/*
- *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: MVME PROM emulation
- *
- *  For mvme88k emulation.
- *
- *  TODO: Perhaps this could be reused for mvme68k emulation too?
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/mvmeprom.h"
-
-
-#define	MVMEPROM_BRDID_ADDR	0x1100
-
-
-/*
- *  mvmeprom_init():
- */
-void mvmeprom_init(struct machine *machine)
-{
-	struct cpu *cpu = machine->cpus[0];
-	struct mvmeprom_brdid mvmeprom_brdid;
-	uint32_t vbr = 0x00000000;
-	int model = 0x187;
-
-	switch (machine->machine_subtype) {
-	case MACHINE_MVME88K_187:  model = 0x187; break;
-	case MACHINE_MVME88K_188:  model = 0x188; break;
-	case MACHINE_MVME88K_197:  model = 0x197; break;
-	}
-
-	cpu->cd.m88k.cr[M88K_CR_VBR] = vbr;
-
-	/*  A magic prom call instruction, followed by an 'rte':  */
-	store_32bit_word(cpu, vbr + 8 * MVMEPROM_VECTOR, M88K_PROM_INSTR);
-	store_32bit_word(cpu, vbr + 8 * MVMEPROM_VECTOR + 4, 0xf400fc00);
-
-	/*  brdid struct:  */
-	memset(&mvmeprom_brdid, 0, sizeof(mvmeprom_brdid));
-	store_16bit_word_in_host(cpu, (unsigned char *)
-	    &(mvmeprom_brdid.model), model);
-	mvmeprom_brdid.speed[0] = '3';	/*  33 MHz, for now  */
-	mvmeprom_brdid.speed[1] = '3';
-	mvmeprom_brdid.speed[2] = '0';
-	mvmeprom_brdid.speed[3] = '0';
-	store_buf(cpu, MVMEPROM_BRDID_ADDR,
-	    (char *)&mvmeprom_brdid, sizeof(struct mvmeprom_brdid));
-}
-
-
-/*
- *  mvmeprom_emul():
- *
- *  For MVME88K:
- *
- *  Input:
- *	r9 = requested function number
- *	r2 = first argument (for functions that take arguments)
- *
- *  Output:
- *	r2 = result
- */
-int mvmeprom_emul(struct cpu *cpu)
-{
-	int func = cpu->cd.m88k.r[9];
-
-	switch (func) {
-
-	case MVMEPROM_OUTCHR:
-		console_putchar(cpu->machine->main_console_handle,
-		    cpu->cd.m88k.r[2]);
-		break;
-
-	case MVMEPROM_OUTCRLF:
-		console_putchar(cpu->machine->main_console_handle, '\n');
-		break;
-
-	case MVMEPROM_EXIT:
-		fatal("[ MVME PROM: exit ]\n");
-		cpu->running = 0;
-		break;
-
-	case MVMEPROM_GETBRDID:
-		/*  Return a pointer in r2 to a mvmeprom_brdid struct.  */
-		cpu->cd.m88k.r[2] = MVMEPROM_BRDID_ADDR;
-		break;
-
-	default:
-		cpu_register_dump(cpu->machine, cpu, 1, 0);
-		cpu_register_dump(cpu->machine, cpu, 0, 1);
-		fatal("[ MVME PROM emulation: unimplemented function 0x%"
-		    PRIx32" ]\n", func);
-		cpu->running = 0;
-		return 0;
-	}
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/promemul/of.c gxemul-0.7.0+dfsg/src/promemul/of.c
--- gxemul-0.6.2/src/promemul/of.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/of.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,1191 @@
+/*
+ *  Copyright (C) 2005-2021  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: OpenFirmware emulation
+ *
+ *  NOTE: This module is/was a quick hack, with the purpose of getting
+ *        NetBSD/macppc to boot. If anything else boots using this hackish
+ *        implementation of OpenFirmware, then that is a bonus.
+ *
+ ******************************************************************************
+ *
+ *  NOTE: OpenFirmware is used on quite a variety of different hardware archs,
+ *        at least POWER/PowerPC, ARM, and SPARC, so the code in this module
+ *        must always remain architecture agnostic.
+ *
+ *  NOTE: Some things, e.g. 32-bit integers as returned by the "getprop"
+ *        service, are always fixed to big-endian. (According to the standard.)
+ *
+ *  TODO: o) 64-bit OpenFirmware?
+ *        o) More devices...
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+
+#define OF_C
+
+#include "console.h"
+#include "cpu.h"
+#include "device.h"
+#include "devices.h"
+#include "diskimage.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "of.h"
+
+
+/*  #define debug fatal  */
+
+extern int quiet_mode;
+extern int verbose;
+
+
+/*
+ *  readstr():
+ *
+ *  Helper function to read a string from emulated memory.
+ */
+static void readstr(struct cpu *cpu, uint64_t addr, char *strbuf,
+	int bufsize)
+{
+	int i;
+	for (i=0; i<bufsize; i++) {
+		unsigned char ch;
+		cpu->memory_rw(cpu, cpu->mem, addr + i,
+		    &ch, sizeof(ch), MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
+		strbuf[i] = '\0';
+		if (ch >= 1 && ch < 32)
+			ch = 0;
+		strbuf[i] = ch;
+		if (strbuf[i] == '\0')
+			break;
+	}
+
+	strbuf[bufsize - 1] = '\0';
+}
+
+
+/*
+ *  of_store_32bit_in_host():
+ *
+ *  Store big-endian. OpenFirmware properties returned by getprop etc are
+ *  always big-endian, even on little-endian machines.
+ */
+static void of_store_32bit_in_host(unsigned char *d, uint32_t x)
+{
+	d[0] = x >> 24; d[1] = x >> 16;
+	d[2] = x >>  8; d[3] = x;
+}
+
+
+/*
+ *  find_device_handle():
+ *
+ *  name may consist of multiple names, separated with slashes.
+ */
+static int find_device_handle(struct of_data *ofd, const char *name)
+{
+	int handle = 1, cur_parent = 1;
+
+	if (name[0] == 0)
+		return 0;
+
+	for (;;) {
+		struct of_device *od = ofd->of_devices;
+		char tmp[200];
+		int i;
+
+		while (name[0] == '/')
+			name++;
+		if (name[0] == '\0')
+			break;
+		snprintf(tmp, sizeof(tmp), "%s", name);
+		i = 0;
+		while (tmp[i] != '\0' && tmp[i] != '/')
+			i++;
+		tmp[i] = '\0';
+
+		OF_FIND(od, strcmp(od->name, tmp) == 0 &&
+		    od->parent == cur_parent);
+		if (od == NULL)
+			return -1;
+
+		handle = cur_parent = od->handle;
+		name += strlen(tmp);
+	}
+
+	return handle;
+}
+
+
+/*****************************************************************************/
+
+
+OF_SERVICE(call_method_2_2)
+{
+	fatal("[ of: call_method_2_2('%s'): TODO ]\n", arg[0]);
+	return -1;
+}
+
+
+OF_SERVICE(call_method_3_4)
+{
+	fatal("[ of: call_method_3_4('%s'): TODO ]\n", arg[0]);
+	return -1;
+}
+
+
+OF_SERVICE(call_method_5_2)
+{
+	if (strcmp(arg[0], "set-colors") == 0) {
+		/*  Used by OpenBSD/macppc:  */
+		struct vfb_data *v = cpu->machine->md.of_data->vfb_data;
+		int color = OF_GET_ARG(3);
+		uint64_t ptr = OF_GET_ARG(4);
+		unsigned char rgb[3];
+		cpu->memory_rw(cpu, cpu->mem, ptr, rgb, 3, MEM_READ,
+		    CACHE_DATA | NO_EXCEPTIONS);
+		if (v != NULL) {
+			memcpy(v->rgb_palette + 3 * color, rgb, 3);
+			v->update_x1 = v->update_y1 = 0;
+			v->update_x2 = v->xsize - 1;
+			v->update_y2 = v->ysize - 1;
+		}
+	} else {
+		fatal("[ of: call_method_5_2('%s'): TODO ]\n", arg[0]);
+		return -1;
+	}
+	return 0;
+}
+
+
+OF_SERVICE(call_method_6_1)
+{
+	fatal("[ of: call_method_6_1('%s'): TODO ]\n", arg[0]);
+	return -1;
+}
+
+
+OF_SERVICE(call_method_6_2)
+{
+	fatal("[ of: call_method_6_2('%s'): TODO ]\n", arg[0]);
+	return -1;
+}
+
+
+OF_SERVICE(child)
+{
+	struct of_device *od = cpu->machine->md.of_data->of_devices;
+	int handle = OF_GET_ARG(0);
+	OF_FIND(od, od->parent == handle);
+	store_32bit_word(cpu, base + retofs, od == NULL? 0 : od->handle);
+	return 0;
+}
+
+
+OF_SERVICE(claim)
+{
+	// Arguments:  virtualaddr, size, alignment
+	// Returns:    pointer to claimed memory
+
+	// TODO: This is just a dummy.
+	fatal("[ of: claim(0x%x,0x%x,0x%x): TODO ]\n",
+	    OF_GET_ARG(0), OF_GET_ARG(1), OF_GET_ARG(2));
+
+	store_32bit_word(cpu, base + retofs, OF_GET_ARG(0));
+	return 0;
+}
+
+
+OF_SERVICE(exit)
+{
+	cpu->running = 0;
+	return 0;
+}
+
+
+OF_SERVICE(finddevice)
+{
+	int h = find_device_handle(cpu->machine->md.of_data, arg[0]);
+	store_32bit_word(cpu, base + retofs, h);
+	return h>0? 0 : -1;
+}
+
+
+OF_SERVICE(getprop)
+{
+	struct of_device *od = cpu->machine->md.of_data->of_devices;
+	struct of_device_property *pr;
+	int handle = OF_GET_ARG(0), i, len_returned = 0;
+	uint64_t buf = OF_GET_ARG(2);
+	uint64_t max = OF_GET_ARG(3);
+
+	OF_FIND(od, od->handle == handle);
+	if (od == NULL) {
+		fatal("[ of: WARNING: getprop handle=%i; no such handle ]\n",
+		    handle);
+		return -1;
+	}
+
+	pr = od->properties;
+	OF_FIND(pr, strcmp(pr->name, arg[1]) == 0);
+	if (pr == NULL) {
+		fatal("[ of: WARNING: getprop: no property '%s' at handle"
+		    " %i (device '%s') ]\n", arg[1], handle, od->name);
+		return -1;
+	}
+
+	if (pr->data == NULL) {
+		fatal("[ of: WARNING: property '%s' of '%s' has no data! ]\n",
+		    arg[1], od->name);
+		goto ret;
+	}
+
+	/*  Return the property into emulated RAM:  */
+	len_returned = pr->len <= max? pr->len : max;
+
+	for (i=0; i<len_returned; i++) {
+		if (!cpu->memory_rw(cpu, cpu->mem, buf + i, pr->data + i,
+		    1, MEM_WRITE, CACHE_DATA | NO_EXCEPTIONS)) {
+			fatal("[ of: getprop memory_rw() error ]\n");
+			exit(1);
+		}
+	}
+
+ret:
+	store_32bit_word(cpu, base + retofs, len_returned);
+	return 0;
+}
+
+
+OF_SERVICE(getproplen)
+{
+	struct of_device *od = cpu->machine->md.of_data->of_devices;
+	struct of_device_property *pr;
+	int handle = OF_GET_ARG(0);
+
+	OF_FIND(od, od->handle == handle);
+	if (od == NULL) {
+		fatal("[ of: TODO: getproplen handle=%i; no such handle ]\n",
+		    handle);
+		return -1;
+	}
+
+	pr = od->properties;
+	OF_FIND(pr, strcmp(pr->name, arg[1]) == 0);
+	if (pr == NULL) {
+		fatal("[ of: TODO: getproplen: no property '%s' at handle"
+		    " %i (device '%s') ]\n", arg[1], handle, od->name);
+		return -1;
+	}
+
+	store_32bit_word(cpu, base + retofs, pr->len);
+	return 0;
+}
+
+
+OF_SERVICE(instance_to_package)
+{
+	int handle = OF_GET_ARG(0);
+	/*  TODO: actually do something here? :-)  */
+	store_32bit_word(cpu, base + retofs, handle);
+	return 0;
+}
+
+
+OF_SERVICE(interpret_1)
+{
+	if (strcmp(arg[0], "#lines 2 - to line#") == 0) {
+	} else {
+		fatal("[ of: interpret_1('%s'): TODO ]\n", arg[0]);
+		return -1;
+	}
+	return 0;
+}
+
+
+OF_SERVICE(interpret_2)
+{
+	store_32bit_word(cpu, base + retofs, 0);	/*  ?  TODO  */
+	if (strcmp(arg[0], "#columns") == 0) {
+		store_32bit_word(cpu, base + retofs + 4, 80);
+	} else if (strcmp(arg[0], "#lines") == 0) {
+		store_32bit_word(cpu, base + retofs + 4, 40);
+	} else if (strcmp(arg[0], "char-height") == 0) {
+		store_32bit_word(cpu, base + retofs + 4, 15);
+	} else if (strcmp(arg[0], "char-width") == 0) {
+		store_32bit_word(cpu, base + retofs + 4, 10);
+	} else if (strcmp(arg[0], "line#") == 0) {
+		store_32bit_word(cpu, base + retofs + 4, 0);
+	} else if (strcmp(arg[0], "font-adr") == 0) {
+		store_32bit_word(cpu, base + retofs + 4, 0);
+	} else {
+		fatal("[ of: interpret_2('%s'): TODO ]\n", arg[0]);
+		return -1;
+	}
+	return 0;
+}
+
+
+OF_SERVICE(package_to_path)
+{
+	fatal("[ of: package-to-path: TODO ]\n");
+	return -1;
+}
+
+
+OF_SERVICE(parent)
+{
+	struct of_device *od = cpu->machine->md.of_data->of_devices;
+	int handle = OF_GET_ARG(0);
+	OF_FIND(od, od->handle == handle);
+	store_32bit_word(cpu, base + retofs, od == NULL? 0 : od->parent);
+	return 0;
+}
+
+
+OF_SERVICE(peer)
+{
+	struct of_device *od = cpu->machine->md.of_data->of_devices;
+	int handle = OF_GET_ARG(0), parent = 0, peer = 0, seen_self = 1;
+
+	if (handle == 0) {
+		/*  Return the handle of the root node (1):  */
+		store_32bit_word(cpu, base + retofs, 1);
+		return 0;
+	}
+
+	OF_FIND(od, od->handle == handle);
+	if (od == NULL) {
+		fatal("[ of: TODO: peer(): can't find handle %i ]\n", handle);
+		exit(1);
+	}
+	parent = od->parent;
+	seen_self = 0;
+
+	od = cpu->machine->md.of_data->of_devices;
+
+	while (od != NULL) {
+		if (od->parent == parent) {
+			if (seen_self) {
+				peer = od->handle;
+				break;
+			}
+			if (od->handle == handle)
+				seen_self = 1;
+		}
+		od = od->next;
+	}
+	store_32bit_word(cpu, base + retofs, peer);
+	return 0;
+}
+
+
+OF_SERVICE(open)
+{
+	// TODO.
+	uint64_t ptr = OF_GET_ARG(0);
+
+	unsigned char s[2000];
+	int s_len = 0;
+
+	int i = 0;
+	for (;;) {
+		unsigned char ch;
+		if (!cpu->memory_rw(cpu, cpu->mem, ptr + i, &ch,
+		    1, MEM_READ, CACHE_DATA | NO_EXCEPTIONS)) {
+			fatal("[ of: TODO: write: memory_rw() error ]\n");
+			exit(1);
+		}
+
+		if (ch == 0)
+			break;
+
+		s[s_len++] = ch;
+			if (s_len == sizeof(s) - 1)
+				break;
+		++ i;
+	}
+
+	s[s_len] = 0;
+
+	if (s[0]) {
+		printf("Unimplemented OF_SERVICE(open) with name: '%s'\n", s);
+		exit(1);
+	}
+
+	return 0;
+}
+
+
+OF_SERVICE(read)
+{
+	/*  int handle = OF_GET_ARG(0);  */
+	uint64_t ptr = OF_GET_ARG(1);
+	/*  int len = OF_GET_ARG(2);  */
+	int c;
+	unsigned char ch;
+
+	/*  TODO: check handle! This just reads chars from the console!  */
+	/*  TODO: This is blocking!  */
+
+	c = console_readchar(cpu->machine->main_console_handle);
+	ch = c;
+	if (!cpu->memory_rw(cpu, cpu->mem, ptr, &ch, 1, MEM_WRITE,
+	    CACHE_DATA | NO_EXCEPTIONS)) {
+		fatal("[ of: TODO: read: memory_rw() error ]\n");
+		exit(1);
+	}
+
+	store_32bit_word(cpu, base + retofs, c == -1? 0 : 1);
+	return c == -1? -1 : 0;
+}
+
+
+OF_SERVICE(write)
+{
+	/*  int handle = OF_GET_ARG(0);  */
+	uint64_t ptr = OF_GET_ARG(1);
+	int n_written = 0, i, len = OF_GET_ARG(2);
+
+	/*  TODO: check handle! This just dumps the data to the console!  */
+
+	for (i=0; i<len; i++) {
+		unsigned char ch;
+		if (!cpu->memory_rw(cpu, cpu->mem, ptr + i, &ch,
+		    1, MEM_READ, CACHE_DATA | NO_EXCEPTIONS)) {
+			fatal("[ of: TODO: write: memory_rw() error ]\n");
+			exit(1);
+		}
+		if (ch != 7)
+			console_putchar(cpu->machine->main_console_handle, ch);
+		n_written ++;
+	}
+
+	store_32bit_word(cpu, base + retofs, n_written);
+	return 0;
+}
+
+
+/*****************************************************************************/
+
+
+/*
+ *  of_get_unused_device_handle():
+ *
+ *  Returns an unused device handle number (1 or higher).
+ */
+static int of_get_unused_device_handle(struct of_data *of_data)
+{
+	int max_handle = 0;
+	struct of_device *od = of_data->of_devices;
+
+	while (od != NULL) {
+		if (od->handle > max_handle)
+			max_handle = od->handle;
+		od = od->next;
+	}
+
+	return max_handle + 1;
+}
+
+
+/*
+ *  of_add_device():
+ *
+ *  Adds a device.
+ */
+static struct of_device *of_add_device(struct of_data *of_data, const char *name,
+	const char *parentname)
+{
+	struct of_device *od;
+
+	CHECK_ALLOCATION(od = (struct of_device *) malloc(sizeof(struct of_device)));
+	memset(od, 0, sizeof(struct of_device));
+
+	CHECK_ALLOCATION(od->name = strdup(name));
+
+	od->handle = of_get_unused_device_handle(of_data);
+	od->parent = find_device_handle(of_data, parentname);
+	if (od->parent < 0) {
+		fatal("of_add_device(): adding '%s' to parent '%s' failed: "
+		    "parent not found!\n", name, parentname);
+		exit(1);
+	}
+
+	od->next = of_data->of_devices;
+	of_data->of_devices = od;
+
+	return od;
+}
+
+
+/*
+ *  of_add_prop():
+ *
+ *  Adds a property to a device.
+ */
+static void of_add_prop(struct of_data *of_data, const char *devname,
+	const char *propname, unsigned char *data, uint32_t len, int flags)
+{
+	struct of_device_property *pr;
+	struct of_device *od = of_data->of_devices;
+	int h = find_device_handle(of_data, devname);
+
+	CHECK_ALLOCATION(pr = (struct of_device_property *) malloc(sizeof(struct of_device_property)));
+	memset(pr, 0, sizeof(struct of_device_property));
+
+	OF_FIND(od, od->handle == h);
+	if (od == NULL) {
+		fatal("of_add_prop(): device '%s' not registered\n", devname);
+		exit(1);
+	}
+
+	CHECK_ALLOCATION(pr->name = strdup(propname));
+	pr->data = data;
+	pr->len = len;
+	pr->flags = flags;
+
+	pr->next = od->properties;
+	od->properties = pr;
+}
+
+
+/*
+ *  of_add_service():
+ *
+ *  Adds a service.
+ */
+static void of_add_service(struct of_data *of_data, const char *name,
+	int (*f)(OF_SERVICE_ARGS), int n_args, int n_ret_args)
+{
+	struct of_service *os;
+
+	CHECK_ALLOCATION(os = (struct of_service *) malloc(sizeof(struct of_service)));
+	memset(os, 0, sizeof(struct of_service));
+
+	CHECK_ALLOCATION(os->name = strdup(name));
+
+	os->f = f;
+	os->n_args = n_args;
+	os->n_ret_args = n_ret_args;
+
+	os->next = of_data->of_services;
+	of_data->of_services = os;
+}
+
+
+/*
+ *  of_dump_devices():
+ *
+ *  Debug dump helper.
+ */
+static void of_dump_devices(struct of_data *ofd, int parent)
+{
+	struct of_device *od = ofd->of_devices;
+
+	while (od != NULL) {
+		struct of_device_property *pr = od->properties;
+		if (od->parent != parent) {
+			od = od->next;
+			continue;
+		}
+		
+		debug("\"%s\"", od->name);
+		debug(" (handle %i)\n", od->handle);
+		debug_indentation(1);
+		
+		while (pr != NULL) {
+			debug("(%s: ", pr->name);
+			if (pr->flags == OF_PROP_STRING)
+				debug("\"%s\"", pr->data);
+			else
+				debug("%i bytes", pr->len);
+			debug(")\n");
+			pr = pr->next;
+		}
+		
+		of_dump_devices(ofd, od->handle);
+		debug_indentation(-1);
+		od = od->next;
+	}
+}
+
+
+/*
+ *  of_dump_all():
+ *
+ *  Debug dump.
+ */
+static void of_dump_all(struct of_data *ofd)
+{
+	struct of_service *os;
+
+	debug("openfirmware debug dump:\n");
+	debug_indentation(1);
+
+	/*  Devices:  */
+	of_dump_devices(ofd, 0);
+
+	/*  Services:  */
+	os = ofd->of_services;
+	while (os != NULL) {
+		debug("service '%s'", os->name);
+		if (os->n_ret_args > 0 || os->n_args > 0) {
+			debug(" (");
+			if (os->n_args > 0) {
+				debug("%i arg%s", os->n_args,
+				    os->n_args > 1? "s" : "");
+				if (os->n_ret_args > 0)
+					debug(", ");
+			}
+			if (os->n_ret_args > 0)
+				debug("%i return value%s", os->n_ret_args,
+				    os->n_ret_args > 1? "s" : "");
+			debug(")");
+		}
+		debug("\n");
+		os = os->next;
+	}
+
+	debug_indentation(-1);
+}
+
+
+/*
+ *  of_add_prop_int32():
+ *
+ *  Helper function.
+ */
+static void of_add_prop_int32(struct of_data *ofd,
+	const char *devname, const char *propname, uint32_t x)
+{
+	unsigned char *p;
+
+	CHECK_ALLOCATION(p = (unsigned char *) malloc(sizeof(int32_t)));
+
+	of_store_32bit_in_host(p, x);
+	of_add_prop(ofd, devname, propname, p, sizeof(int32_t),
+	    OF_PROP_INT);
+}
+
+
+/*
+ *  of_add_prop_str():
+ *
+ *  Helper function.
+ */
+static void of_add_prop_str(struct machine *machine, struct of_data *ofd,
+	const char *devname, const char *propname, const char *data)
+{
+	char *p;
+
+	CHECK_ALLOCATION(p = strdup(data));
+
+	of_add_prop(ofd, devname, propname, (unsigned char *)p, strlen(p) + 1,
+	    OF_PROP_STRING);
+}
+
+
+/*
+ *  of_emul_init_isa():
+ */
+void of_emul_init_isa(struct machine *machine)
+{
+	struct of_data *ofd = machine->md.of_data;
+	unsigned char *isa_ranges;
+
+	of_add_device(ofd, "isa", "/");
+
+	CHECK_ALLOCATION(isa_ranges = (unsigned char *) malloc(32));
+	memset(isa_ranges, 0, 32);
+
+	/*  2 *: isa_phys_hi, isa_phys_lo, parent_phys_start, size  */
+	/*  MEM space:  */
+	of_store_32bit_in_host(isa_ranges + 0, 0);
+	of_store_32bit_in_host(isa_ranges + 4, 0xc0000000);
+	/*  I/O space: low bit if isa_phys_hi set  */
+	of_store_32bit_in_host(isa_ranges + 16, 1);
+	of_store_32bit_in_host(isa_ranges + 20, 0xd0000000);
+
+	of_add_prop(ofd, "/isa", "ranges", isa_ranges, 32, 0);
+}
+
+
+/*
+ *  of_emul_init_adb():
+ */
+void of_emul_init_adb(struct machine *machine)
+{
+	struct of_data *ofd = machine->md.of_data;
+	unsigned char *adb_interrupts, *adb_reg;
+
+	CHECK_ALLOCATION(adb_interrupts = (unsigned char *) malloc(4 * sizeof(uint32_t)));
+	CHECK_ALLOCATION(adb_reg = (unsigned char *) malloc(8 * sizeof(uint32_t)));
+
+	of_add_device(ofd, "adb", "/bandit/gc");
+	of_add_prop_str(machine, ofd, "/bandit/gc/adb", "name", "via-cuda");
+	of_store_32bit_in_host(adb_interrupts + 0, 25);
+	of_store_32bit_in_host(adb_interrupts + 4, 0);
+	of_store_32bit_in_host(adb_interrupts + 8, 0);
+	of_store_32bit_in_host(adb_interrupts + 12, 0);
+	of_add_prop(ofd, "/bandit/gc/adb", "interrupts", adb_interrupts,
+	    4*sizeof(uint32_t), 0);
+	of_store_32bit_in_host(adb_reg + 0, 0x16000);
+	of_store_32bit_in_host(adb_reg + 4, 0x2000);
+	of_store_32bit_in_host(adb_reg + 8, 0);
+	of_store_32bit_in_host(adb_reg + 12, 0);
+	of_store_32bit_in_host(adb_reg + 16, 0);
+	of_store_32bit_in_host(adb_reg + 20, 0);
+	of_store_32bit_in_host(adb_reg + 24, 0);
+	of_store_32bit_in_host(adb_reg + 28, 0);
+	of_add_prop(ofd, "/bandit/gc/adb", "reg", adb_reg,
+	    8*sizeof(uint32_t), 0);
+}
+
+
+/*
+ *  of_emul_init_zs():
+ */
+void of_emul_init_zs(struct machine *machine)
+{
+	struct of_data *ofd = machine->md.of_data;
+	unsigned char *zs_interrupts, *zs_reg;
+
+	CHECK_ALLOCATION(zs_reg = (unsigned char *) malloc(6 * sizeof(uint32_t)));
+
+	/*  The controller:  */
+	of_add_device(ofd, "zs", "/bandit/gc");
+	of_add_prop_str(machine, ofd, "/bandit/gc/zs", "device_type", "serial");
+	of_add_prop_str(machine, ofd, "/bandit/gc/zs", "name", "escc");
+	of_store_32bit_in_host(zs_reg + 0, 0x13000);
+	of_store_32bit_in_host(zs_reg + 4, 0x40);
+	of_store_32bit_in_host(zs_reg + 8, 0x100);
+	of_store_32bit_in_host(zs_reg + 12, 0x100);
+	of_store_32bit_in_host(zs_reg + 16, 0x200);
+	of_store_32bit_in_host(zs_reg + 20, 0x100);
+	of_add_prop(ofd, "/bandit/gc/zs", "reg", zs_reg, 6*sizeof(uint32_t), 0);
+
+	/*  Port 1:  */
+	CHECK_ALLOCATION(zs_interrupts = (unsigned char *) malloc(3 * sizeof(uint32_t)));
+	CHECK_ALLOCATION(zs_reg = (unsigned char *) malloc(6 * sizeof(uint32_t)));
+
+	of_add_device(ofd, "zstty1", "/bandit/gc/zs");
+	of_add_prop_str(machine, ofd, "/bandit/gc/zs/zstty1", "name", "ch-a");
+	of_store_32bit_in_host(zs_interrupts + 0, 16);
+	of_store_32bit_in_host(zs_interrupts + 4, 0);
+	of_store_32bit_in_host(zs_interrupts + 8, 0);
+	of_add_prop(ofd, "/bandit/gc/zs/zstty1", "interrupts", zs_interrupts,
+	    3*sizeof(uint32_t), 0);
+	of_store_32bit_in_host(zs_reg + 0, 0x13800);
+	of_store_32bit_in_host(zs_reg + 4, 0x100);
+	of_store_32bit_in_host(zs_reg + 8, 0x100);
+	of_store_32bit_in_host(zs_reg + 12, 0x100);
+	of_store_32bit_in_host(zs_reg + 16, 0x200);
+	of_store_32bit_in_host(zs_reg + 20, 0x100);
+	of_add_prop(ofd, "/bandit/gc/zs/zstty1",
+	    "reg", zs_reg, 6*sizeof(uint32_t), 0);
+
+	/*  Port 0:  */
+	CHECK_ALLOCATION(zs_interrupts = (unsigned char *) malloc(3 * sizeof(uint32_t)));
+	CHECK_ALLOCATION(zs_reg = (unsigned char *) malloc(6 * sizeof(uint32_t)));
+
+	of_add_device(ofd, "zstty0", "/bandit/gc/zs");
+	of_add_prop_str(machine, ofd, "/bandit/gc/zs/zstty0", "name", "ch-b");
+	of_store_32bit_in_host(zs_interrupts + 0, 15);
+	of_store_32bit_in_host(zs_interrupts + 4, 0);
+	of_store_32bit_in_host(zs_interrupts + 8, 0);
+	of_add_prop(ofd, "/bandit/gc/zs/zstty0", "interrupts", zs_interrupts,
+	    3*sizeof(uint32_t), 0);
+	of_store_32bit_in_host(zs_reg + 0, 0x13400);
+	of_store_32bit_in_host(zs_reg + 4, 0x100);
+	of_store_32bit_in_host(zs_reg + 8, 0x100);
+	of_store_32bit_in_host(zs_reg + 12, 0x100);
+	of_store_32bit_in_host(zs_reg + 16, 0x200);
+	of_store_32bit_in_host(zs_reg + 20, 0x100);
+	of_add_prop(ofd, "/bandit/gc/zs/zstty0",
+	    "reg", zs_reg, 6*sizeof(uint32_t), 0);
+}
+
+
+/*
+ *  of_emul_init_uninorth():
+ */
+void of_emul_init_uninorth(struct machine *machine)
+{
+	struct of_data *ofd = machine->md.of_data;
+	unsigned char *uninorth_reg, *uninorth_bus_range, *uninorth_ranges;
+	unsigned char *macio_aa, *ata_interrupts, *ata_reg;
+	struct of_device *ic;
+	const char *n = "pci@e2000000";
+	const char *macio = "mac-io";
+
+	of_add_device(ofd, n, "/");
+	of_add_prop_str(machine, ofd, n, "name", "pci");
+	of_add_prop_str(machine, ofd, n, "device_type", "pci");
+	of_add_prop_str(machine, ofd, n, "compatible", "uni-north");
+
+	CHECK_ALLOCATION(uninorth_reg = (unsigned char *) malloc(2 * sizeof(uint32_t)));
+	CHECK_ALLOCATION(uninorth_bus_range = (unsigned char *) malloc(2 * sizeof(uint32_t)));
+	CHECK_ALLOCATION(uninorth_ranges = (unsigned char *) malloc(12 * sizeof(uint32_t)));
+	CHECK_ALLOCATION(macio_aa = (unsigned char *) malloc(5 * sizeof(uint32_t)));
+	CHECK_ALLOCATION(ata_interrupts = (unsigned char *) malloc(6 * sizeof(uint32_t)));
+	CHECK_ALLOCATION(ata_reg = (unsigned char *) malloc(8 * sizeof(uint32_t)));
+
+	of_store_32bit_in_host(uninorth_reg + 0, 0xe2000000);
+	of_store_32bit_in_host(uninorth_reg + 4, 0);	/*  not used?  */
+	of_add_prop(ofd, n, "reg", uninorth_reg, 2*sizeof(uint32_t), 0);
+
+	of_store_32bit_in_host(uninorth_bus_range + 0, 0);
+	of_store_32bit_in_host(uninorth_bus_range + 4, 0);
+	of_add_prop(ofd, n, "bus-range", uninorth_bus_range,
+	    2*sizeof(uint32_t), 0);
+
+	/*  MEM:  */
+	of_store_32bit_in_host(uninorth_ranges + 0, 0x02000000);
+	of_store_32bit_in_host(uninorth_ranges + 4, 0);
+	of_store_32bit_in_host(uninorth_ranges + 8, 0);
+	of_store_32bit_in_host(uninorth_ranges + 12, 0xd0000000);
+	of_store_32bit_in_host(uninorth_ranges + 16, 0);
+	of_store_32bit_in_host(uninorth_ranges + 20, 0x04000000);
+	/*  IO:  */
+	of_store_32bit_in_host(uninorth_ranges + 24, 0x01000000);
+	of_store_32bit_in_host(uninorth_ranges + 28, 0);
+	of_store_32bit_in_host(uninorth_ranges + 32, 0);
+	of_store_32bit_in_host(uninorth_ranges + 36, 0xe2000000);
+	of_store_32bit_in_host(uninorth_ranges + 40, 0);
+	of_store_32bit_in_host(uninorth_ranges + 44, 0x01000000);
+	of_add_prop(ofd, n, "ranges", uninorth_ranges,
+	    12*sizeof(uint32_t), 0);
+
+	ic = of_add_device(ofd, macio, "/");
+	memset(macio_aa, 0, 20);
+	of_store_32bit_in_host(macio_aa + 0, 15 << 11); /* pci tag */
+	of_store_32bit_in_host(macio_aa + 8, 0xf3000000);
+	of_add_prop(ofd, macio, "assigned-addresses", macio_aa,
+	    5*sizeof(uint32_t), 0);
+/*	of_add_prop(ofd, n, "assigned-addresses", macio_aa,
+	    5*sizeof(uint32_t), 0); */
+	of_add_prop_int32(ofd, "/chosen", "interrupt-controller", ic->handle);
+
+	of_add_device(ofd, "bandit", "/");
+	of_add_device(ofd, "gc", "/bandit");
+	of_add_prop(ofd, "/bandit/gc", "assigned-addresses", macio_aa,
+	    5*sizeof(uint32_t), 0);
+
+	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
+	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
+		char tmpstr[400];
+		of_add_device(ofd, "ata", "/bandit/gc");
+		of_add_prop_str(machine, ofd, "/bandit/gc/ata", "name", "ata");
+		of_add_prop_str(machine, ofd, "/bandit/gc/ata", "compatible",
+		    "heathrow-ata");
+		of_store_32bit_in_host(ata_interrupts + 0, 13);
+		of_store_32bit_in_host(ata_interrupts + 4, 0);
+		of_store_32bit_in_host(ata_interrupts + 8, 0);
+		of_store_32bit_in_host(ata_interrupts + 12, 0);
+		of_store_32bit_in_host(ata_interrupts + 16, 0);
+		of_store_32bit_in_host(ata_interrupts + 20, 0);
+		of_add_prop(ofd, "/bandit/gc/ata", "interrupts", ata_interrupts,
+		    6*sizeof(uint32_t), 0);
+		of_store_32bit_in_host(ata_reg + 0, 0x20000);
+		of_store_32bit_in_host(ata_reg + 4, 0);
+		of_store_32bit_in_host(ata_reg + 8, 0x21000);
+		of_store_32bit_in_host(ata_reg + 12, 0x22000);
+		of_store_32bit_in_host(ata_reg + 16, 0);
+		of_store_32bit_in_host(ata_reg + 20, 0);
+		of_store_32bit_in_host(ata_reg + 24, 0);
+		of_store_32bit_in_host(ata_reg + 28, 0);
+		of_add_prop(ofd, "/bandit/gc/ata", "reg", ata_reg,
+		    8*sizeof(uint32_t), 0);
+
+		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0xf3020000 "
+		    "irq=%s.cpu[%i].gc.lo.21 addr_mult=0x10", machine->path,
+		    machine->bootstrap_cpu);
+		device_add(machine, tmpstr);
+	}
+}
+
+
+/*
+ *  of_emul_init():
+ *
+ *  This function creates an OpenFirmware emulation instance.
+ */
+struct of_data *of_emul_init(struct machine *machine, struct vfb_data *vfb_data,
+	uint64_t fb_addr, int fb_xsize, int fb_ysize)
+{
+	unsigned char *memory_reg, *memory_av;
+	unsigned char *root_address_cells, *root_size_cells;
+	unsigned char *zs_assigned_addresses;
+	struct of_device *memory_dev, *mmu, *devstdout, *devstdin;
+	struct of_data *ofd;
+	int i;
+
+	CHECK_ALLOCATION(ofd = (struct of_data *) malloc(sizeof(struct of_data)));
+	memset(ofd, 0, sizeof(struct of_data));
+
+	ofd->vfb_data = vfb_data;
+
+	/*  Devices:  */
+
+	/*  Root = device 1  */
+	of_add_device(ofd, "", "");
+	of_add_prop_str(machine, ofd, "/", "model", "GXemul OpenFirmware machine");
+
+	CHECK_ALLOCATION(root_address_cells = (unsigned char *) malloc(1 * sizeof(uint32_t)));
+	of_store_32bit_in_host(root_address_cells, 0);
+	of_add_prop(ofd, "/", "#address-cells", root_address_cells, 1 * sizeof(uint32_t), 0);
+
+	CHECK_ALLOCATION(root_size_cells = (unsigned char *) malloc(1 * sizeof(uint32_t)));
+	of_store_32bit_in_host(root_size_cells, 0);
+	of_add_prop(ofd, "/", "#size-cells", root_size_cells, 1 * sizeof(uint32_t), 0);
+
+	of_add_device(ofd, "io", "/");
+	devstdin  = of_add_device(ofd, "stdin", "/io");
+	devstdout = of_add_device(ofd, "stdout", "/io");
+
+	if (machine->x11_md.in_use) {
+		fatal("!\n!  TODO: keyboard + framebuffer for MacPPC\n!\n");
+
+		of_add_prop_str(machine, ofd, "/io/stdin", "name",
+		    "keyboard");
+		of_add_prop_str(machine, ofd, "/io", "name", "adb");
+
+		of_add_prop_str(machine, ofd, "/io/stdout", "device_type",
+		    "display");
+		of_add_prop_int32(ofd, "/io/stdout", "width", fb_xsize);
+		of_add_prop_int32(ofd, "/io/stdout", "height", fb_ysize);
+		of_add_prop_int32(ofd, "/io/stdout", "linebytes", fb_xsize * 1);
+		of_add_prop_int32(ofd, "/io/stdout", "depth", 8);
+		of_add_prop_int32(ofd, "/io/stdout", "address", fb_addr);
+	} else {
+		CHECK_ALLOCATION(zs_assigned_addresses = (unsigned char *) malloc(12));
+		memset(zs_assigned_addresses, 0, 12);
+
+		of_add_prop_str(machine, ofd, "/io/stdin", "name", "ch-b");
+		of_add_prop_str(machine, ofd, "/io/stdin", "device_type",
+		    "serial");
+		of_add_prop_int32(ofd, "/io/stdin", "reg", 0xf3013000);
+		of_add_prop(ofd, "/io/stdin", "assigned-addresses",
+		    zs_assigned_addresses, 12, 0);
+
+		of_add_prop_str(machine, ofd, "/io/stdout", "device_type",
+		    "serial");
+	}
+
+	of_add_device(ofd, "cpus", "/");
+	for (i=0; i<machine->ncpus; i++) {
+		char tmp[50];
+		snprintf(tmp, sizeof(tmp), "@%x", i);
+		of_add_device(ofd, tmp, "/cpus");
+		snprintf(tmp, sizeof(tmp), "/cpus/@%x", i);
+		of_add_prop_str(machine, ofd, tmp, "device_type", "cpu");
+		of_add_prop_int32(ofd, tmp, "timebase-frequency",
+		    machine->emulated_hz / 4);
+		of_add_prop_int32(ofd, tmp, "clock-frequency",
+		    machine->emulated_hz);
+		of_add_prop_int32(ofd, tmp, "reg", i);
+	}
+
+	mmu = of_add_device(ofd, "mmu", "/");
+
+	/*  TODO:  */
+	of_add_prop(ofd, "/mmu", "translations", NULL, 0, 0);
+
+	of_add_device(ofd, "chosen", "/");
+	of_add_prop_int32(ofd, "/chosen", "mmu", mmu->handle);
+	of_add_prop_int32(ofd, "/chosen", "stdin", devstdin->handle);
+	of_add_prop_int32(ofd, "/chosen", "stdout", devstdout->handle);
+
+	memory_dev = of_add_device(ofd, "memory", "/");
+	CHECK_ALLOCATION(memory_reg = (unsigned char *) malloc(2 * sizeof(uint32_t)));
+	CHECK_ALLOCATION(memory_av = (unsigned char *) malloc(2 * sizeof(uint32_t)));
+
+	of_store_32bit_in_host(memory_reg + 0, 0);
+	of_store_32bit_in_host(memory_reg + 4, machine->physical_ram_in_mb<<20);
+	of_store_32bit_in_host(memory_av + 0, 10 << 20);
+	of_store_32bit_in_host(memory_av + 4, (machine->physical_ram_in_mb - 10) << 20);
+	of_add_prop(ofd, "/memory", "reg", memory_reg, 2 * sizeof(uint32_t), 0);
+	of_add_prop(ofd, "/memory", "available", memory_av, 2*sizeof(uint32_t),0);
+	of_add_prop_str(machine, ofd, "/memory", "name", "memory");
+	of_add_prop_str(machine, ofd, "/memory","device_type","memory"/*?*/);
+
+	of_add_prop_int32(ofd, "/chosen", "memory", memory_dev->handle);
+
+	/*  Services:  */
+	of_add_service(ofd, "call-method", of__call_method_2_2, 2, 2);
+	of_add_service(ofd, "call-method", of__call_method_3_4, 3, 4);
+	of_add_service(ofd, "call-method", of__call_method_5_2, 5, 2);
+	of_add_service(ofd, "call-method", of__call_method_6_1, 6, 1);
+	of_add_service(ofd, "call-method", of__call_method_6_2, 6, 2);
+	of_add_service(ofd, "child", of__child, 1, 1);
+	of_add_service(ofd, "claim", of__claim, 3, 1);
+	of_add_service(ofd, "exit", of__exit, 0, 0);
+	of_add_service(ofd, "finddevice", of__finddevice, 1, 1);
+	of_add_service(ofd, "getprop", of__getprop, 4, 1);
+	of_add_service(ofd, "getproplen", of__getproplen, 2, 1);
+	of_add_service(ofd, "instance-to-package",
+	    of__instance_to_package, 1, 1);
+	of_add_service(ofd, "interpret", of__interpret_1, 1, 1);
+	of_add_service(ofd, "interpret", of__interpret_2, 1, 2);
+	of_add_service(ofd, "package-to-path", of__package_to_path, 3, 1);
+	of_add_service(ofd, "parent", of__parent, 1, 1);
+	of_add_service(ofd, "peer", of__peer, 1, 1);
+	of_add_service(ofd, "open", of__open, 1, 1);
+	of_add_service(ofd, "read", of__read, 3, 1);
+	of_add_service(ofd, "write", of__write, 3, 1);
+
+	if (verbose >= 2)
+		of_dump_all(ofd);
+
+	machine->md.of_data = ofd;
+
+	return ofd;
+}
+
+
+/*
+ *  of_emul():
+ *
+ *  OpenFirmware call emulation.
+ */
+int of_emul(struct cpu *cpu)
+{
+	int i, nargs, nret, ofs, retval = 0;
+	char service[50];
+	char *arg[OF_N_MAX_ARGS];
+	uint64_t base, ptr;
+	struct of_service *os;
+	struct of_data *of_data = cpu->machine->md.of_data;
+
+	if (of_data == NULL) {
+		fatal("of_emul(): no of_data struct?\n");
+		exit(1);
+	}
+
+	/*
+	 *  The first argument register points to "prom_args":
+	 *
+	 *	char *service;		(probably 32 bit)
+	 *	int nargs;
+	 *	int nret;
+	 *	char *args[10];
+	 */
+
+	switch (cpu->cpu_family->arch) {
+	case ARCH_ARM:
+		base = cpu->cd.arm.r[0];
+		break;
+	case ARCH_PPC:
+		base = cpu->cd.ppc.gpr[3];
+		break;
+	default:fatal("of_emul(): unimplemented arch (TODO)\n");
+		exit(1);
+	}
+
+	/*  TODO: how about 64-bit OpenFirmware?  */
+	ptr   = load_32bit_word(cpu, base);
+	nargs = load_32bit_word(cpu, base + 4);
+	nret  = load_32bit_word(cpu, base + 8);
+
+	readstr(cpu, ptr, service, sizeof(service));
+
+	debug("[ of: %s(", service);
+	ofs = 12;
+	for (i=0; i<nargs; i++) {
+		int x;
+		if (i > 0)
+			debug(", ");
+		if (i >= OF_N_MAX_ARGS) {
+			fatal("TOO MANY ARGS!");
+			continue;
+		}
+
+		ptr = load_32bit_word(cpu, base + ofs);
+
+		CHECK_ALLOCATION(arg[i] = (char *) malloc(OF_ARG_MAX_LEN + 1));
+		memset(arg[i], 0, OF_ARG_MAX_LEN + 1);
+
+		x = ptr;
+		if (x > -256 && x < 256) {
+			debug("%i", x);
+		} else {
+			readstr(cpu, ptr, arg[i], OF_ARG_MAX_LEN);
+			if (arg[i][0])
+				debug("\"%s\"", arg[i]);
+			else
+				debug("0x%x", x);
+		}
+		ofs += sizeof(uint32_t);
+	}
+	debug(") ]\n");
+
+	/*  Note: base + ofs points to the first return slot.  */
+
+	os = of_data->of_services;
+	while (os != NULL) {
+		if (strcmp(service, os->name) == 0 &&
+		    nargs == os->n_args && nret == os->n_ret_args) {
+			retval = os->f(cpu, arg, base, ofs);
+			break;
+		}
+		os = os->next;
+	}
+
+	if (os == NULL) {
+		quiet_mode = 0;
+		cpu_register_dump(cpu->machine, cpu, 1, 0);
+		printf("\n");
+		fatal("[ of: unimplemented service \"%s\" with %i input "
+		    "args and %i output values ]\n", service, nargs, nret);
+		cpu->running = 0;
+		exit(1);
+	}
+
+	for (i=0; i<nargs; i++)
+		free(arg[i]);
+
+	/*  Return:  */
+	switch (cpu->cpu_family->arch) {
+	case ARCH_ARM:
+		cpu->cd.arm.r[0] = retval;
+		break;
+	case ARCH_PPC:
+		cpu->cd.ppc.gpr[3] = retval;
+		break;
+	default:fatal("of_emul(): TODO: unimplemented arch (Retval)\n");
+		exit(1);
+	}
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/promemul/of.cc gxemul-0.7.0+dfsg/src/promemul/of.cc
--- gxemul-0.6.2/src/promemul/of.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/of.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1188 +0,0 @@
-/*
- *  Copyright (C) 2005-2012  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: OpenFirmware emulation
- *
- *  NOTE: This module is/was a quick hack, with the purpose of getting
- *        NetBSD/macppc to boot. If anything else boots using this hackish
- *        implementation of OpenFirmware, then that is a bonus.
- *
- ******************************************************************************
- *
- *  NOTE: OpenFirmware is used on quite a variety of different hardware archs,
- *        at least POWER/PowerPC, ARM, and SPARC, so the code in this module
- *        must always remain architecture agnostic.
- *
- *  NOTE: Some things, e.g. 32-bit integers as returned by the "getprop"
- *        service, are always fixed to big-endian. (According to the standard.)
- *
- *  TODO: o) 64-bit OpenFirmware?
- *        o) More devices...
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-
-#define OF_C
-
-#include "console.h"
-#include "cpu.h"
-#include "device.h"
-#include "devices.h"
-#include "diskimage.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "of.h"
-
-
-/*  #define debug fatal  */
-
-extern int quiet_mode;
-extern int verbose;
-
-
-/*
- *  readstr():
- *
- *  Helper function to read a string from emulated memory.
- */
-static void readstr(struct cpu *cpu, uint64_t addr, char *strbuf,
-	int bufsize)
-{
-	int i;
-	for (i=0; i<bufsize; i++) {
-		unsigned char ch;
-		cpu->memory_rw(cpu, cpu->mem, addr + i,
-		    &ch, sizeof(ch), MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
-		strbuf[i] = '\0';
-		if (ch >= 1 && ch < 32)
-			ch = 0;
-		strbuf[i] = ch;
-		if (strbuf[i] == '\0')
-			break;
-	}
-
-	strbuf[bufsize - 1] = '\0';
-}
-
-
-/*
- *  of_store_32bit_in_host():
- *
- *  Store big-endian. OpenFirmware properties returned by getprop etc are
- *  always big-endian, even on little-endian machines.
- */
-static void of_store_32bit_in_host(unsigned char *d, uint32_t x)
-{
-	d[0] = x >> 24; d[1] = x >> 16;
-	d[2] = x >>  8; d[3] = x;
-}
-
-
-/*
- *  find_device_handle():
- *
- *  name may consist of multiple names, separated with slashes.
- */
-static int find_device_handle(struct of_data *ofd, const char *name)
-{
-	int handle = 1, cur_parent = 1;
-
-	if (name[0] == 0)
-		return 0;
-
-	for (;;) {
-		struct of_device *od = ofd->of_devices;
-		char tmp[200];
-		int i;
-
-		while (name[0] == '/')
-			name++;
-		if (name[0] == '\0')
-			break;
-		snprintf(tmp, sizeof(tmp), "%s", name);
-		i = 0;
-		while (tmp[i] != '\0' && tmp[i] != '/')
-			i++;
-		tmp[i] = '\0';
-
-		OF_FIND(od, strcmp(od->name, tmp) == 0 &&
-		    od->parent == cur_parent);
-		if (od == NULL)
-			return -1;
-
-		handle = cur_parent = od->handle;
-		name += strlen(tmp);
-	}
-
-	return handle;
-}
-
-
-/*****************************************************************************/
-
-
-OF_SERVICE(call_method_2_2)
-{
-	fatal("[ of: call_method_2_2('%s'): TODO ]\n", arg[0]);
-	return -1;
-}
-
-
-OF_SERVICE(call_method_3_4)
-{
-	fatal("[ of: call_method_3_4('%s'): TODO ]\n", arg[0]);
-	return -1;
-}
-
-
-OF_SERVICE(call_method_5_2)
-{
-	if (strcmp(arg[0], "set-colors") == 0) {
-		/*  Used by OpenBSD/macppc:  */
-		struct vfb_data *v = cpu->machine->md.of_data->vfb_data;
-		int color = OF_GET_ARG(3);
-		uint64_t ptr = OF_GET_ARG(4);
-		unsigned char rgb[3];
-		cpu->memory_rw(cpu, cpu->mem, ptr, rgb, 3, MEM_READ,
-		    CACHE_DATA | NO_EXCEPTIONS);
-		if (v != NULL) {
-			memcpy(v->rgb_palette + 3 * color, rgb, 3);
-			v->update_x1 = v->update_y1 = 0;
-			v->update_x2 = v->xsize - 1;
-			v->update_y2 = v->ysize - 1;
-		}
-	} else {
-		fatal("[ of: call_method_5_2('%s'): TODO ]\n", arg[0]);
-		return -1;
-	}
-	return 0;
-}
-
-
-OF_SERVICE(call_method_6_1)
-{
-	fatal("[ of: call_method_6_1('%s'): TODO ]\n", arg[0]);
-	return -1;
-}
-
-
-OF_SERVICE(call_method_6_2)
-{
-	fatal("[ of: call_method_6_2('%s'): TODO ]\n", arg[0]);
-	return -1;
-}
-
-
-OF_SERVICE(child)
-{
-	struct of_device *od = cpu->machine->md.of_data->of_devices;
-	int handle = OF_GET_ARG(0);
-	OF_FIND(od, od->parent == handle);
-	store_32bit_word(cpu, base + retofs, od == NULL? 0 : od->handle);
-	return 0;
-}
-
-
-OF_SERVICE(claim)
-{
-	// Arguments:  virtualaddr, size, alignment
-	// Returns:    pointer to claimed memory
-
-	// TODO: This is just a dummy.
-	fatal("[ of: claim(0x%x,0x%x,0x%x): TODO ]\n",
-	    OF_GET_ARG(0), OF_GET_ARG(1), OF_GET_ARG(2));
-
-	store_32bit_word(cpu, base + retofs, OF_GET_ARG(0));
-	return 0;
-}
-
-
-OF_SERVICE(exit)
-{
-	cpu->running = 0;
-	return 0;
-}
-
-
-OF_SERVICE(finddevice)
-{
-	int h = find_device_handle(cpu->machine->md.of_data, arg[0]);
-	store_32bit_word(cpu, base + retofs, h);
-	return h>0? 0 : -1;
-}
-
-
-OF_SERVICE(getprop)
-{
-	struct of_device *od = cpu->machine->md.of_data->of_devices;
-	struct of_device_property *pr;
-	int handle = OF_GET_ARG(0), i, len_returned = 0;
-	uint64_t buf = OF_GET_ARG(2);
-	uint64_t max = OF_GET_ARG(3);
-
-	OF_FIND(od, od->handle == handle);
-	if (od == NULL) {
-		fatal("[ of: WARNING: getprop handle=%i; no such handle ]\n",
-		    handle);
-		return -1;
-	}
-
-	pr = od->properties;
-	OF_FIND(pr, strcmp(pr->name, arg[1]) == 0);
-	if (pr == NULL) {
-		fatal("[ of: WARNING: getprop: no property '%s' at handle"
-		    " %i (device '%s') ]\n", arg[1], handle, od->name);
-		return -1;
-	}
-
-	if (pr->data == NULL) {
-		fatal("[ of: WARNING: property '%s' of '%s' has no data! ]\n",
-		    arg[1], od->name);
-		goto ret;
-	}
-
-	/*  Return the property into emulated RAM:  */
-	len_returned = pr->len <= max? pr->len : max;
-
-	for (i=0; i<len_returned; i++) {
-		if (!cpu->memory_rw(cpu, cpu->mem, buf + i, pr->data + i,
-		    1, MEM_WRITE, CACHE_DATA | NO_EXCEPTIONS)) {
-			fatal("[ of: getprop memory_rw() error ]\n");
-			exit(1);
-		}
-	}
-
-ret:
-	store_32bit_word(cpu, base + retofs, len_returned);
-	return 0;
-}
-
-
-OF_SERVICE(getproplen)
-{
-	struct of_device *od = cpu->machine->md.of_data->of_devices;
-	struct of_device_property *pr;
-	int handle = OF_GET_ARG(0);
-
-	OF_FIND(od, od->handle == handle);
-	if (od == NULL) {
-		fatal("[ of: TODO: getproplen handle=%i; no such handle ]\n",
-		    handle);
-		return -1;
-	}
-
-	pr = od->properties;
-	OF_FIND(pr, strcmp(pr->name, arg[1]) == 0);
-	if (pr == NULL) {
-		fatal("[ of: TODO: getproplen: no property '%s' at handle"
-		    " %i (device '%s') ]\n", arg[1], handle, od->name);
-		return -1;
-	}
-
-	store_32bit_word(cpu, base + retofs, pr->len);
-	return 0;
-}
-
-
-OF_SERVICE(instance_to_package)
-{
-	int handle = OF_GET_ARG(0);
-	/*  TODO: actually do something here? :-)  */
-	store_32bit_word(cpu, base + retofs, handle);
-	return 0;
-}
-
-
-OF_SERVICE(interpret_1)
-{
-	if (strcmp(arg[0], "#lines 2 - to line#") == 0) {
-	} else {
-		fatal("[ of: interpret_1('%s'): TODO ]\n", arg[0]);
-		return -1;
-	}
-	return 0;
-}
-
-
-OF_SERVICE(interpret_2)
-{
-	store_32bit_word(cpu, base + retofs, 0);	/*  ?  TODO  */
-	if (strcmp(arg[0], "#columns") == 0) {
-		store_32bit_word(cpu, base + retofs + 4, 80);
-	} else if (strcmp(arg[0], "#lines") == 0) {
-		store_32bit_word(cpu, base + retofs + 4, 40);
-	} else if (strcmp(arg[0], "char-height") == 0) {
-		store_32bit_word(cpu, base + retofs + 4, 15);
-	} else if (strcmp(arg[0], "char-width") == 0) {
-		store_32bit_word(cpu, base + retofs + 4, 10);
-	} else if (strcmp(arg[0], "line#") == 0) {
-		store_32bit_word(cpu, base + retofs + 4, 0);
-	} else if (strcmp(arg[0], "font-adr") == 0) {
-		store_32bit_word(cpu, base + retofs + 4, 0);
-	} else {
-		fatal("[ of: interpret_2('%s'): TODO ]\n", arg[0]);
-		return -1;
-	}
-	return 0;
-}
-
-
-OF_SERVICE(package_to_path)
-{
-	fatal("[ of: package-to-path: TODO ]\n");
-	return -1;
-}
-
-
-OF_SERVICE(parent)
-{
-	struct of_device *od = cpu->machine->md.of_data->of_devices;
-	int handle = OF_GET_ARG(0);
-	OF_FIND(od, od->handle == handle);
-	store_32bit_word(cpu, base + retofs, od == NULL? 0 : od->parent);
-	return 0;
-}
-
-
-OF_SERVICE(peer)
-{
-	struct of_device *od = cpu->machine->md.of_data->of_devices;
-	int handle = OF_GET_ARG(0), parent = 0, peer = 0, seen_self = 1;
-
-	if (handle == 0) {
-		/*  Return the handle of the root node (1):  */
-		store_32bit_word(cpu, base + retofs, 1);
-		return 0;
-	}
-
-	OF_FIND(od, od->handle == handle);
-	if (od == NULL) {
-		fatal("[ of: TODO: peer(): can't find handle %i ]\n", handle);
-		exit(1);
-	}
-	parent = od->parent;
-	seen_self = 0;
-
-	od = cpu->machine->md.of_data->of_devices;
-
-	while (od != NULL) {
-		if (od->parent == parent) {
-			if (seen_self) {
-				peer = od->handle;
-				break;
-			}
-			if (od->handle == handle)
-				seen_self = 1;
-		}
-		od = od->next;
-	}
-	store_32bit_word(cpu, base + retofs, peer);
-	return 0;
-}
-
-
-OF_SERVICE(open)
-{
-	// TODO.
-	uint64_t ptr = OF_GET_ARG(0);
-
-	string s;
-
-	int i = 0;
-	while (true) {
-		unsigned char ch;
-		if (!cpu->memory_rw(cpu, cpu->mem, ptr + i, &ch,
-		    1, MEM_READ, CACHE_DATA | NO_EXCEPTIONS)) {
-			fatal("[ of: TODO: write: memory_rw() error ]\n");
-			exit(1);
-		}
-
-		if (ch == 0)
-			break;
-
-		s += ch;
-		++ i;
-	}
-
-	if (s != "") {
-		cout << "Unimplemented OF_SERVICE(open) with name: '" << s << "'\n";
-		exit(1);
-	}
-
-	return 0;
-}
-
-
-OF_SERVICE(read)
-{
-	/*  int handle = OF_GET_ARG(0);  */
-	uint64_t ptr = OF_GET_ARG(1);
-	/*  int len = OF_GET_ARG(2);  */
-	int c;
-	unsigned char ch;
-
-	/*  TODO: check handle! This just reads chars from the console!  */
-	/*  TODO: This is blocking!  */
-
-	c = console_readchar(cpu->machine->main_console_handle);
-	ch = c;
-	if (!cpu->memory_rw(cpu, cpu->mem, ptr, &ch, 1, MEM_WRITE,
-	    CACHE_DATA | NO_EXCEPTIONS)) {
-		fatal("[ of: TODO: read: memory_rw() error ]\n");
-		exit(1);
-	}
-
-	store_32bit_word(cpu, base + retofs, c == -1? 0 : 1);
-	return c == -1? -1 : 0;
-}
-
-
-OF_SERVICE(write)
-{
-	/*  int handle = OF_GET_ARG(0);  */
-	uint64_t ptr = OF_GET_ARG(1);
-	int n_written = 0, i, len = OF_GET_ARG(2);
-
-	/*  TODO: check handle! This just dumps the data to the console!  */
-
-	for (i=0; i<len; i++) {
-		unsigned char ch;
-		if (!cpu->memory_rw(cpu, cpu->mem, ptr + i, &ch,
-		    1, MEM_READ, CACHE_DATA | NO_EXCEPTIONS)) {
-			fatal("[ of: TODO: write: memory_rw() error ]\n");
-			exit(1);
-		}
-		if (ch != 7)
-			console_putchar(cpu->machine->main_console_handle, ch);
-		n_written ++;
-	}
-
-	store_32bit_word(cpu, base + retofs, n_written);
-	return 0;
-}
-
-
-/*****************************************************************************/
-
-
-/*
- *  of_get_unused_device_handle():
- *
- *  Returns an unused device handle number (1 or higher).
- */
-static int of_get_unused_device_handle(struct of_data *of_data)
-{
-	int max_handle = 0;
-	struct of_device *od = of_data->of_devices;
-
-	while (od != NULL) {
-		if (od->handle > max_handle)
-			max_handle = od->handle;
-		od = od->next;
-	}
-
-	return max_handle + 1;
-}
-
-
-/*
- *  of_add_device():
- *
- *  Adds a device.
- */
-static struct of_device *of_add_device(struct of_data *of_data, const char *name,
-	const char *parentname)
-{
-	struct of_device *od;
-
-	CHECK_ALLOCATION(od = (struct of_device *) malloc(sizeof(struct of_device)));
-	memset(od, 0, sizeof(struct of_device));
-
-	CHECK_ALLOCATION(od->name = strdup(name));
-
-	od->handle = of_get_unused_device_handle(of_data);
-	od->parent = find_device_handle(of_data, parentname);
-	if (od->parent < 0) {
-		fatal("of_add_device(): adding '%s' to parent '%s' failed: "
-		    "parent not found!\n", name, parentname);
-		exit(1);
-	}
-
-	od->next = of_data->of_devices;
-	of_data->of_devices = od;
-
-	return od;
-}
-
-
-/*
- *  of_add_prop():
- *
- *  Adds a property to a device.
- */
-static void of_add_prop(struct of_data *of_data, const char *devname,
-	const char *propname, unsigned char *data, uint32_t len, int flags)
-{
-	struct of_device_property *pr;
-	struct of_device *od = of_data->of_devices;
-	int h = find_device_handle(of_data, devname);
-
-	CHECK_ALLOCATION(pr = (struct of_device_property *) malloc(sizeof(struct of_device_property)));
-	memset(pr, 0, sizeof(struct of_device_property));
-
-	OF_FIND(od, od->handle == h);
-	if (od == NULL) {
-		fatal("of_add_prop(): device '%s' not registered\n", devname);
-		exit(1);
-	}
-
-	CHECK_ALLOCATION(pr->name = strdup(propname));
-	pr->data = data;
-	pr->len = len;
-	pr->flags = flags;
-
-	pr->next = od->properties;
-	od->properties = pr;
-}
-
-
-/*
- *  of_add_service():
- *
- *  Adds a service.
- */
-static void of_add_service(struct of_data *of_data, const char *name,
-	int (*f)(OF_SERVICE_ARGS), int n_args, int n_ret_args)
-{
-	struct of_service *os;
-
-	CHECK_ALLOCATION(os = (struct of_service *) malloc(sizeof(struct of_service)));
-	memset(os, 0, sizeof(struct of_service));
-
-	CHECK_ALLOCATION(os->name = strdup(name));
-
-	os->f = f;
-	os->n_args = n_args;
-	os->n_ret_args = n_ret_args;
-
-	os->next = of_data->of_services;
-	of_data->of_services = os;
-}
-
-
-/*
- *  of_dump_devices():
- *
- *  Debug dump helper.
- */
-static void of_dump_devices(struct of_data *ofd, int parent)
-{
-	int iadd = DEBUG_INDENTATION;
-	struct of_device *od = ofd->of_devices;
-
-	while (od != NULL) {
-		struct of_device_property *pr = od->properties;
-		if (od->parent != parent) {
-			od = od->next;
-			continue;
-		}
-		
-		debug("\"%s\"", od->name);
-		debug(" (handle %i)\n", od->handle);
-		debug_indentation(iadd);
-		
-		while (pr != NULL) {
-			debug("(%s: ", pr->name);
-			if (pr->flags == OF_PROP_STRING)
-				debug("\"%s\"", pr->data);
-			else
-				debug("%i bytes", pr->len);
-			debug(")\n");
-			pr = pr->next;
-		}
-		
-		of_dump_devices(ofd, od->handle);
-		debug_indentation(-iadd);
-		od = od->next;
-	}
-}
-
-
-/*
- *  of_dump_all():
- *
- *  Debug dump.
- */
-static void of_dump_all(struct of_data *ofd)
-{
-	int iadd = DEBUG_INDENTATION;
-	struct of_service *os;
-
-	debug("openfirmware debug dump:\n");
-	debug_indentation(iadd);
-
-	/*  Devices:  */
-	of_dump_devices(ofd, 0);
-
-	/*  Services:  */
-	os = ofd->of_services;
-	while (os != NULL) {
-		debug("service '%s'", os->name);
-		if (os->n_ret_args > 0 || os->n_args > 0) {
-			debug(" (");
-			if (os->n_args > 0) {
-				debug("%i arg%s", os->n_args,
-				    os->n_args > 1? "s" : "");
-				if (os->n_ret_args > 0)
-					debug(", ");
-			}
-			if (os->n_ret_args > 0)
-				debug("%i return value%s", os->n_ret_args,
-				    os->n_ret_args > 1? "s" : "");
-			debug(")");
-		}
-		debug("\n");
-		os = os->next;
-	}
-
-	debug_indentation(-iadd);
-}
-
-
-/*
- *  of_add_prop_int32():
- *
- *  Helper function.
- */
-static void of_add_prop_int32(struct of_data *ofd,
-	const char *devname, const char *propname, uint32_t x)
-{
-	unsigned char *p;
-
-	CHECK_ALLOCATION(p = (unsigned char *) malloc(sizeof(int32_t)));
-
-	of_store_32bit_in_host(p, x);
-	of_add_prop(ofd, devname, propname, p, sizeof(int32_t),
-	    OF_PROP_INT);
-}
-
-
-/*
- *  of_add_prop_str():
- *
- *  Helper function.
- */
-static void of_add_prop_str(struct machine *machine, struct of_data *ofd,
-	const char *devname, const char *propname, const char *data)
-{
-	char *p;
-
-	CHECK_ALLOCATION(p = strdup(data));
-
-	of_add_prop(ofd, devname, propname, (unsigned char *)p, strlen(p) + 1,
-	    OF_PROP_STRING);
-}
-
-
-/*
- *  of_emul_init_isa():
- */
-void of_emul_init_isa(struct machine *machine)
-{
-	struct of_data *ofd = machine->md.of_data;
-	unsigned char *isa_ranges;
-
-	of_add_device(ofd, "isa", "/");
-
-	CHECK_ALLOCATION(isa_ranges = (unsigned char *) malloc(32));
-	memset(isa_ranges, 0, 32);
-
-	/*  2 *: isa_phys_hi, isa_phys_lo, parent_phys_start, size  */
-	/*  MEM space:  */
-	of_store_32bit_in_host(isa_ranges + 0, 0);
-	of_store_32bit_in_host(isa_ranges + 4, 0xc0000000);
-	/*  I/O space: low bit if isa_phys_hi set  */
-	of_store_32bit_in_host(isa_ranges + 16, 1);
-	of_store_32bit_in_host(isa_ranges + 20, 0xd0000000);
-
-	of_add_prop(ofd, "/isa", "ranges", isa_ranges, 32, 0);
-}
-
-
-/*
- *  of_emul_init_adb():
- */
-void of_emul_init_adb(struct machine *machine)
-{
-	struct of_data *ofd = machine->md.of_data;
-	unsigned char *adb_interrupts, *adb_reg;
-
-	CHECK_ALLOCATION(adb_interrupts = (unsigned char *) malloc(4 * sizeof(uint32_t)));
-	CHECK_ALLOCATION(adb_reg = (unsigned char *) malloc(8 * sizeof(uint32_t)));
-
-	of_add_device(ofd, "adb", "/bandit/gc");
-	of_add_prop_str(machine, ofd, "/bandit/gc/adb", "name", "via-cuda");
-	of_store_32bit_in_host(adb_interrupts + 0, 25);
-	of_store_32bit_in_host(adb_interrupts + 4, 0);
-	of_store_32bit_in_host(adb_interrupts + 8, 0);
-	of_store_32bit_in_host(adb_interrupts + 12, 0);
-	of_add_prop(ofd, "/bandit/gc/adb", "interrupts", adb_interrupts,
-	    4*sizeof(uint32_t), 0);
-	of_store_32bit_in_host(adb_reg + 0, 0x16000);
-	of_store_32bit_in_host(adb_reg + 4, 0x2000);
-	of_store_32bit_in_host(adb_reg + 8, 0);
-	of_store_32bit_in_host(adb_reg + 12, 0);
-	of_store_32bit_in_host(adb_reg + 16, 0);
-	of_store_32bit_in_host(adb_reg + 20, 0);
-	of_store_32bit_in_host(adb_reg + 24, 0);
-	of_store_32bit_in_host(adb_reg + 28, 0);
-	of_add_prop(ofd, "/bandit/gc/adb", "reg", adb_reg,
-	    8*sizeof(uint32_t), 0);
-}
-
-
-/*
- *  of_emul_init_zs():
- */
-void of_emul_init_zs(struct machine *machine)
-{
-	struct of_data *ofd = machine->md.of_data;
-	unsigned char *zs_interrupts, *zs_reg;
-
-	CHECK_ALLOCATION(zs_reg = (unsigned char *) malloc(6 * sizeof(uint32_t)));
-
-	/*  The controller:  */
-	of_add_device(ofd, "zs", "/bandit/gc");
-	of_add_prop_str(machine, ofd, "/bandit/gc/zs", "device_type", "serial");
-	of_add_prop_str(machine, ofd, "/bandit/gc/zs", "name", "escc");
-	of_store_32bit_in_host(zs_reg + 0, 0x13000);
-	of_store_32bit_in_host(zs_reg + 4, 0x40);
-	of_store_32bit_in_host(zs_reg + 8, 0x100);
-	of_store_32bit_in_host(zs_reg + 12, 0x100);
-	of_store_32bit_in_host(zs_reg + 16, 0x200);
-	of_store_32bit_in_host(zs_reg + 20, 0x100);
-	of_add_prop(ofd, "/bandit/gc/zs", "reg", zs_reg, 6*sizeof(uint32_t), 0);
-
-	/*  Port 1:  */
-	CHECK_ALLOCATION(zs_interrupts = (unsigned char *) malloc(3 * sizeof(uint32_t)));
-	CHECK_ALLOCATION(zs_reg = (unsigned char *) malloc(6 * sizeof(uint32_t)));
-
-	of_add_device(ofd, "zstty1", "/bandit/gc/zs");
-	of_add_prop_str(machine, ofd, "/bandit/gc/zs/zstty1", "name", "ch-a");
-	of_store_32bit_in_host(zs_interrupts + 0, 16);
-	of_store_32bit_in_host(zs_interrupts + 4, 0);
-	of_store_32bit_in_host(zs_interrupts + 8, 0);
-	of_add_prop(ofd, "/bandit/gc/zs/zstty1", "interrupts", zs_interrupts,
-	    3*sizeof(uint32_t), 0);
-	of_store_32bit_in_host(zs_reg + 0, 0x13800);
-	of_store_32bit_in_host(zs_reg + 4, 0x100);
-	of_store_32bit_in_host(zs_reg + 8, 0x100);
-	of_store_32bit_in_host(zs_reg + 12, 0x100);
-	of_store_32bit_in_host(zs_reg + 16, 0x200);
-	of_store_32bit_in_host(zs_reg + 20, 0x100);
-	of_add_prop(ofd, "/bandit/gc/zs/zstty1",
-	    "reg", zs_reg, 6*sizeof(uint32_t), 0);
-
-	/*  Port 0:  */
-	CHECK_ALLOCATION(zs_interrupts = (unsigned char *) malloc(3 * sizeof(uint32_t)));
-	CHECK_ALLOCATION(zs_reg = (unsigned char *) malloc(6 * sizeof(uint32_t)));
-
-	of_add_device(ofd, "zstty0", "/bandit/gc/zs");
-	of_add_prop_str(machine, ofd, "/bandit/gc/zs/zstty0", "name", "ch-b");
-	of_store_32bit_in_host(zs_interrupts + 0, 15);
-	of_store_32bit_in_host(zs_interrupts + 4, 0);
-	of_store_32bit_in_host(zs_interrupts + 8, 0);
-	of_add_prop(ofd, "/bandit/gc/zs/zstty0", "interrupts", zs_interrupts,
-	    3*sizeof(uint32_t), 0);
-	of_store_32bit_in_host(zs_reg + 0, 0x13400);
-	of_store_32bit_in_host(zs_reg + 4, 0x100);
-	of_store_32bit_in_host(zs_reg + 8, 0x100);
-	of_store_32bit_in_host(zs_reg + 12, 0x100);
-	of_store_32bit_in_host(zs_reg + 16, 0x200);
-	of_store_32bit_in_host(zs_reg + 20, 0x100);
-	of_add_prop(ofd, "/bandit/gc/zs/zstty0",
-	    "reg", zs_reg, 6*sizeof(uint32_t), 0);
-}
-
-
-/*
- *  of_emul_init_uninorth():
- */
-void of_emul_init_uninorth(struct machine *machine)
-{
-	struct of_data *ofd = machine->md.of_data;
-	unsigned char *uninorth_reg, *uninorth_bus_range, *uninorth_ranges;
-	unsigned char *macio_aa, *ata_interrupts, *ata_reg;
-	struct of_device *ic;
-	const char *n = "pci@e2000000";
-	const char *macio = "mac-io";
-
-	of_add_device(ofd, n, "/");
-	of_add_prop_str(machine, ofd, n, "name", "pci");
-	of_add_prop_str(machine, ofd, n, "device_type", "pci");
-	of_add_prop_str(machine, ofd, n, "compatible", "uni-north");
-
-	CHECK_ALLOCATION(uninorth_reg = (unsigned char *) malloc(2 * sizeof(uint32_t)));
-	CHECK_ALLOCATION(uninorth_bus_range = (unsigned char *) malloc(2 * sizeof(uint32_t)));
-	CHECK_ALLOCATION(uninorth_ranges = (unsigned char *) malloc(12 * sizeof(uint32_t)));
-	CHECK_ALLOCATION(macio_aa = (unsigned char *) malloc(5 * sizeof(uint32_t)));
-	CHECK_ALLOCATION(ata_interrupts = (unsigned char *) malloc(6 * sizeof(uint32_t)));
-	CHECK_ALLOCATION(ata_reg = (unsigned char *) malloc(8 * sizeof(uint32_t)));
-
-	of_store_32bit_in_host(uninorth_reg + 0, 0xe2000000);
-	of_store_32bit_in_host(uninorth_reg + 4, 0);	/*  not used?  */
-	of_add_prop(ofd, n, "reg", uninorth_reg, 2*sizeof(uint32_t), 0);
-
-	of_store_32bit_in_host(uninorth_bus_range + 0, 0);
-	of_store_32bit_in_host(uninorth_bus_range + 4, 0);
-	of_add_prop(ofd, n, "bus-range", uninorth_bus_range,
-	    2*sizeof(uint32_t), 0);
-
-	/*  MEM:  */
-	of_store_32bit_in_host(uninorth_ranges + 0, 0x02000000);
-	of_store_32bit_in_host(uninorth_ranges + 4, 0);
-	of_store_32bit_in_host(uninorth_ranges + 8, 0);
-	of_store_32bit_in_host(uninorth_ranges + 12, 0xd0000000);
-	of_store_32bit_in_host(uninorth_ranges + 16, 0);
-	of_store_32bit_in_host(uninorth_ranges + 20, 0x04000000);
-	/*  IO:  */
-	of_store_32bit_in_host(uninorth_ranges + 24, 0x01000000);
-	of_store_32bit_in_host(uninorth_ranges + 28, 0);
-	of_store_32bit_in_host(uninorth_ranges + 32, 0);
-	of_store_32bit_in_host(uninorth_ranges + 36, 0xe2000000);
-	of_store_32bit_in_host(uninorth_ranges + 40, 0);
-	of_store_32bit_in_host(uninorth_ranges + 44, 0x01000000);
-	of_add_prop(ofd, n, "ranges", uninorth_ranges,
-	    12*sizeof(uint32_t), 0);
-
-	ic = of_add_device(ofd, macio, "/");
-	memset(macio_aa, 0, 20);
-	of_store_32bit_in_host(macio_aa + 0, 15 << 11); /* pci tag */
-	of_store_32bit_in_host(macio_aa + 8, 0xf3000000);
-	of_add_prop(ofd, macio, "assigned-addresses", macio_aa,
-	    5*sizeof(uint32_t), 0);
-/*	of_add_prop(ofd, n, "assigned-addresses", macio_aa,
-	    5*sizeof(uint32_t), 0); */
-	of_add_prop_int32(ofd, "/chosen", "interrupt-controller", ic->handle);
-
-	of_add_device(ofd, "bandit", "/");
-	of_add_device(ofd, "gc", "/bandit");
-	of_add_prop(ofd, "/bandit/gc", "assigned-addresses", macio_aa,
-	    5*sizeof(uint32_t), 0);
-
-	if (diskimage_exist(machine, 0, DISKIMAGE_IDE) ||
-	    diskimage_exist(machine, 1, DISKIMAGE_IDE)) {
-		char tmpstr[400];
-		of_add_device(ofd, "ata", "/bandit/gc");
-		of_add_prop_str(machine, ofd, "/bandit/gc/ata", "name", "ata");
-		of_add_prop_str(machine, ofd, "/bandit/gc/ata", "compatible",
-		    "heathrow-ata");
-		of_store_32bit_in_host(ata_interrupts + 0, 13);
-		of_store_32bit_in_host(ata_interrupts + 4, 0);
-		of_store_32bit_in_host(ata_interrupts + 8, 0);
-		of_store_32bit_in_host(ata_interrupts + 12, 0);
-		of_store_32bit_in_host(ata_interrupts + 16, 0);
-		of_store_32bit_in_host(ata_interrupts + 20, 0);
-		of_add_prop(ofd, "/bandit/gc/ata", "interrupts", ata_interrupts,
-		    6*sizeof(uint32_t), 0);
-		of_store_32bit_in_host(ata_reg + 0, 0x20000);
-		of_store_32bit_in_host(ata_reg + 4, 0);
-		of_store_32bit_in_host(ata_reg + 8, 0x21000);
-		of_store_32bit_in_host(ata_reg + 12, 0x22000);
-		of_store_32bit_in_host(ata_reg + 16, 0);
-		of_store_32bit_in_host(ata_reg + 20, 0);
-		of_store_32bit_in_host(ata_reg + 24, 0);
-		of_store_32bit_in_host(ata_reg + 28, 0);
-		of_add_prop(ofd, "/bandit/gc/ata", "reg", ata_reg,
-		    8*sizeof(uint32_t), 0);
-
-		snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0xf3020000 "
-		    "irq=%s.cpu[%i].gc.lo.21 addr_mult=0x10", machine->path,
-		    machine->bootstrap_cpu);
-		device_add(machine, tmpstr);
-	}
-}
-
-
-/*
- *  of_emul_init():
- *
- *  This function creates an OpenFirmware emulation instance.
- */
-struct of_data *of_emul_init(struct machine *machine, struct vfb_data *vfb_data,
-	uint64_t fb_addr, int fb_xsize, int fb_ysize)
-{
-	unsigned char *memory_reg, *memory_av;
-	unsigned char *root_address_cells, *root_size_cells;
-	unsigned char *zs_assigned_addresses;
-	struct of_device *memory_dev, *mmu, *devstdout, *devstdin;
-	struct of_data *ofd;
-	int i;
-
-	CHECK_ALLOCATION(ofd = (struct of_data *) malloc(sizeof(struct of_data)));
-	memset(ofd, 0, sizeof(struct of_data));
-
-	ofd->vfb_data = vfb_data;
-
-	/*  Devices:  */
-
-	/*  Root = device 1  */
-	of_add_device(ofd, "", "");
-	of_add_prop_str(machine, ofd, "/", "model", "GXemul OpenFirmware machine");
-
-	CHECK_ALLOCATION(root_address_cells = (unsigned char *) malloc(1 * sizeof(uint32_t)));
-	of_store_32bit_in_host(root_address_cells, 0);
-	of_add_prop(ofd, "/", "#address-cells", root_address_cells, 1 * sizeof(uint32_t), 0);
-
-	CHECK_ALLOCATION(root_size_cells = (unsigned char *) malloc(1 * sizeof(uint32_t)));
-	of_store_32bit_in_host(root_size_cells, 0);
-	of_add_prop(ofd, "/", "#size-cells", root_size_cells, 1 * sizeof(uint32_t), 0);
-
-	of_add_device(ofd, "io", "/");
-	devstdin  = of_add_device(ofd, "stdin", "/io");
-	devstdout = of_add_device(ofd, "stdout", "/io");
-
-	if (machine->x11_md.in_use) {
-		fatal("!\n!  TODO: keyboard + framebuffer for MacPPC\n!\n");
-
-		of_add_prop_str(machine, ofd, "/io/stdin", "name",
-		    "keyboard");
-		of_add_prop_str(machine, ofd, "/io", "name", "adb");
-
-		of_add_prop_str(machine, ofd, "/io/stdout", "device_type",
-		    "display");
-		of_add_prop_int32(ofd, "/io/stdout", "width", fb_xsize);
-		of_add_prop_int32(ofd, "/io/stdout", "height", fb_ysize);
-		of_add_prop_int32(ofd, "/io/stdout", "linebytes", fb_xsize * 1);
-		of_add_prop_int32(ofd, "/io/stdout", "depth", 8);
-		of_add_prop_int32(ofd, "/io/stdout", "address", fb_addr);
-	} else {
-		CHECK_ALLOCATION(zs_assigned_addresses = (unsigned char *) malloc(12));
-		memset(zs_assigned_addresses, 0, 12);
-
-		of_add_prop_str(machine, ofd, "/io/stdin", "name", "ch-b");
-		of_add_prop_str(machine, ofd, "/io/stdin", "device_type",
-		    "serial");
-		of_add_prop_int32(ofd, "/io/stdin", "reg", 0xf3013000);
-		of_add_prop(ofd, "/io/stdin", "assigned-addresses",
-		    zs_assigned_addresses, 12, 0);
-
-		of_add_prop_str(machine, ofd, "/io/stdout", "device_type",
-		    "serial");
-	}
-
-	of_add_device(ofd, "cpus", "/");
-	for (i=0; i<machine->ncpus; i++) {
-		char tmp[50];
-		snprintf(tmp, sizeof(tmp), "@%x", i);
-		of_add_device(ofd, tmp, "/cpus");
-		snprintf(tmp, sizeof(tmp), "/cpus/@%x", i);
-		of_add_prop_str(machine, ofd, tmp, "device_type", "cpu");
-		of_add_prop_int32(ofd, tmp, "timebase-frequency",
-		    machine->emulated_hz / 4);
-		of_add_prop_int32(ofd, tmp, "clock-frequency",
-		    machine->emulated_hz);
-		of_add_prop_int32(ofd, tmp, "reg", i);
-	}
-
-	mmu = of_add_device(ofd, "mmu", "/");
-
-	/*  TODO:  */
-	of_add_prop(ofd, "/mmu", "translations", NULL, 0, 0);
-
-	of_add_device(ofd, "chosen", "/");
-	of_add_prop_int32(ofd, "/chosen", "mmu", mmu->handle);
-	of_add_prop_int32(ofd, "/chosen", "stdin", devstdin->handle);
-	of_add_prop_int32(ofd, "/chosen", "stdout", devstdout->handle);
-
-	memory_dev = of_add_device(ofd, "memory", "/");
-	CHECK_ALLOCATION(memory_reg = (unsigned char *) malloc(2 * sizeof(uint32_t)));
-	CHECK_ALLOCATION(memory_av = (unsigned char *) malloc(2 * sizeof(uint32_t)));
-
-	of_store_32bit_in_host(memory_reg + 0, 0);
-	of_store_32bit_in_host(memory_reg + 4, machine->physical_ram_in_mb<<20);
-	of_store_32bit_in_host(memory_av + 0, 10 << 20);
-	of_store_32bit_in_host(memory_av + 4, (machine->physical_ram_in_mb - 10) << 20);
-	of_add_prop(ofd, "/memory", "reg", memory_reg, 2 * sizeof(uint32_t), 0);
-	of_add_prop(ofd, "/memory", "available", memory_av, 2*sizeof(uint32_t),0);
-	of_add_prop_str(machine, ofd, "/memory", "name", "memory");
-	of_add_prop_str(machine, ofd, "/memory","device_type","memory"/*?*/);
-
-	of_add_prop_int32(ofd, "/chosen", "memory", memory_dev->handle);
-
-	/*  Services:  */
-	of_add_service(ofd, "call-method", of__call_method_2_2, 2, 2);
-	of_add_service(ofd, "call-method", of__call_method_3_4, 3, 4);
-	of_add_service(ofd, "call-method", of__call_method_5_2, 5, 2);
-	of_add_service(ofd, "call-method", of__call_method_6_1, 6, 1);
-	of_add_service(ofd, "call-method", of__call_method_6_2, 6, 2);
-	of_add_service(ofd, "child", of__child, 1, 1);
-	of_add_service(ofd, "claim", of__claim, 3, 1);
-	of_add_service(ofd, "exit", of__exit, 0, 0);
-	of_add_service(ofd, "finddevice", of__finddevice, 1, 1);
-	of_add_service(ofd, "getprop", of__getprop, 4, 1);
-	of_add_service(ofd, "getproplen", of__getproplen, 2, 1);
-	of_add_service(ofd, "instance-to-package",
-	    of__instance_to_package, 1, 1);
-	of_add_service(ofd, "interpret", of__interpret_1, 1, 1);
-	of_add_service(ofd, "interpret", of__interpret_2, 1, 2);
-	of_add_service(ofd, "package-to-path", of__package_to_path, 3, 1);
-	of_add_service(ofd, "parent", of__parent, 1, 1);
-	of_add_service(ofd, "peer", of__peer, 1, 1);
-	of_add_service(ofd, "open", of__open, 1, 1);
-	of_add_service(ofd, "read", of__read, 3, 1);
-	of_add_service(ofd, "write", of__write, 3, 1);
-
-	if (verbose >= 2)
-		of_dump_all(ofd);
-
-	machine->md.of_data = ofd;
-
-	return ofd;
-}
-
-
-/*
- *  of_emul():
- *
- *  OpenFirmware call emulation.
- */
-int of_emul(struct cpu *cpu)
-{
-	int i, nargs, nret, ofs, retval = 0;
-	char service[50];
-	char *arg[OF_N_MAX_ARGS];
-	uint64_t base, ptr;
-	struct of_service *os;
-	struct of_data *of_data = cpu->machine->md.of_data;
-
-	if (of_data == NULL) {
-		fatal("of_emul(): no of_data struct?\n");
-		exit(1);
-	}
-
-	/*
-	 *  The first argument register points to "prom_args":
-	 *
-	 *	char *service;		(probably 32 bit)
-	 *	int nargs;
-	 *	int nret;
-	 *	char *args[10];
-	 */
-
-	switch (cpu->machine->arch) {
-	case ARCH_ARM:
-		base = cpu->cd.arm.r[0];
-		break;
-	case ARCH_PPC:
-		base = cpu->cd.ppc.gpr[3];
-		break;
-	default:fatal("of_emul(): unimplemented arch (TODO)\n");
-		exit(1);
-	}
-
-	/*  TODO: how about 64-bit OpenFirmware?  */
-	ptr   = load_32bit_word(cpu, base);
-	nargs = load_32bit_word(cpu, base + 4);
-	nret  = load_32bit_word(cpu, base + 8);
-
-	readstr(cpu, ptr, service, sizeof(service));
-
-	debug("[ of: %s(", service);
-	ofs = 12;
-	for (i=0; i<nargs; i++) {
-		int x;
-		if (i > 0)
-			debug(", ");
-		if (i >= OF_N_MAX_ARGS) {
-			fatal("TOO MANY ARGS!");
-			continue;
-		}
-
-		ptr = load_32bit_word(cpu, base + ofs);
-
-		CHECK_ALLOCATION(arg[i] = (char *) malloc(OF_ARG_MAX_LEN + 1));
-		memset(arg[i], 0, OF_ARG_MAX_LEN + 1);
-
-		x = ptr;
-		if (x > -256 && x < 256) {
-			debug("%i", x);
-		} else {
-			readstr(cpu, ptr, arg[i], OF_ARG_MAX_LEN);
-			if (arg[i][0])
-				debug("\"%s\"", arg[i]);
-			else
-				debug("0x%x", x);
-		}
-		ofs += sizeof(uint32_t);
-	}
-	debug(") ]\n");
-
-	/*  Note: base + ofs points to the first return slot.  */
-
-	os = of_data->of_services;
-	while (os != NULL) {
-		if (strcmp(service, os->name) == 0 &&
-		    nargs == os->n_args && nret == os->n_ret_args) {
-			retval = os->f(cpu, arg, base, ofs);
-			break;
-		}
-		os = os->next;
-	}
-
-	if (os == NULL) {
-		quiet_mode = 0;
-		cpu_register_dump(cpu->machine, cpu, 1, 0);
-		printf("\n");
-		fatal("[ of: unimplemented service \"%s\" with %i input "
-		    "args and %i output values ]\n", service, nargs, nret);
-		cpu->running = 0;
-		exit(1);
-	}
-
-	for (i=0; i<nargs; i++)
-		free(arg[i]);
-
-	/*  Return:  */
-	switch (cpu->machine->arch) {
-	case ARCH_ARM:
-		cpu->cd.arm.r[0] = retval;
-		break;
-	case ARCH_PPC:
-		cpu->cd.ppc.gpr[3] = retval;
-		break;
-	default:fatal("of_emul(): TODO: unimplemented arch (Retval)\n");
-		exit(1);
-	}
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/promemul/ps2_bios.c gxemul-0.7.0+dfsg/src/promemul/ps2_bios.c
--- gxemul-0.6.2/src/promemul/ps2_bios.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/ps2_bios.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,235 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: Playstation 2 SIFBIOS emulation
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/time.h>
+#include <sys/resource.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "cpu_mips.h"
+#include "machine.h"
+#include "memory.h"
+
+
+extern int quiet_mode;
+
+
+/*
+ *  playstation2_sifbios_emul():
+ */
+int playstation2_sifbios_emul(struct cpu *cpu)
+{
+	int callnr;
+
+	callnr = cpu->cd.mips.gpr[MIPS_GPR_A0];
+
+	switch (callnr) {
+	case 0:			/*  getver()  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0x200;		/*  TODO  */
+		break;
+	case 1:			/*  halt(int mode)  */
+		debug("[ SIFBIOS halt(0x%" PRIx64") ]\n",
+		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1]);
+		cpu->running = 0;
+		break;
+	case 2:			/*  setdve(int mode)  */
+		debug("[ SIFBIOS setdve(0x%" PRIx64") ]\n",
+		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1]);
+		break;
+	case 3:			/*  putchar(int ch)  */
+		/*  debug("[ SIFBIOS putchar(0x%x) ]\n",
+		    (char)cpu->cd.mips.gpr[MIPS_GPR_A1]);  */
+		console_putchar(cpu->machine->main_console_handle,
+		    cpu->cd.mips.gpr[MIPS_GPR_A1]);
+		break;
+	case 4:			/*  getchar()  */
+		/*  This is untested. TODO  */
+		/*  debug("[ SIFBIOS getchar() ]\n";  */
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		if (console_charavail(cpu->machine->main_console_handle))
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = console_readchar(
+			    cpu->machine->main_console_handle);
+		break;
+	case 16:		/*  dma_init()  */
+		debug("[ SIFBIOS dma_init() ]\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;		/*  TODO  */
+		break;
+	case 17:		/*  dma_exit()  */
+		debug("[ SIFBIOS dma_exit() ]\n");
+		break;
+	case 32:		/*  cmd_init()  */
+		debug("[ SIFBIOS cmd_init() ]\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;		/*  TODO  */
+		break;
+	case 33:		/*  cmd_exit()  */
+		debug("[ SIFBIOS cmd_exit() ]\n");
+		break;
+	case 48:
+		debug("[ SIFBIOS rpc_init(): TODO ]\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;		/*  TODO  */
+		break;
+	case 49:
+		debug("[ SIFBIOS rpc_exit(): TODO ]\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;		/*  TODO  */
+		break;
+	case 51:
+		debug("[ SIFBIOS rpc_bind(): TODO ]\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 1;		/*  TODO  */
+		break;
+	case 64:
+		fatal("[ SIFBIOS SBR_IOPH_INIT(0x%" PRIx32",0x%" PRIx32",0x%"
+		    PRIx32"): TODO ]\n",
+		    (uint32_t) cpu->cd.mips.gpr[MIPS_GPR_A1],
+		    (uint32_t) cpu->cd.mips.gpr[MIPS_GPR_A2],
+		    (uint32_t) cpu->cd.mips.gpr[MIPS_GPR_A3]);
+
+		/*
+		 *  This is really really ugly:   TODO
+		 *
+		 *  Linux and NetBSD seem to work, but it's an ugly hack.
+		 *  This should really be a callback thingy...
+		 *
+		 *  NetBSD has a done-word which should be set to 1.
+		 *  Linux has one done-word which should be set to 1, and
+		 *  one which should be set to 0.
+		 *
+		 *  The code as it is right now probably overwrites stuff in
+		 *  memory that shouldn't be touched. Not good.
+		 *
+		 *  Linux: err = sbios_rpc(SBR_IOPH_INIT, NULL, &result);
+		 *         err should be 0 (just as NetBSD),
+		 *         and result should be set to 0 as well.
+		 */
+		{
+			uint32_t tmpaddr;
+
+			tmpaddr = load_32bit_word(cpu,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 0);
+			fatal("  +0: %08x\n", tmpaddr);
+			tmpaddr = load_32bit_word(cpu,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 4);
+			fatal("  +4: %08x\n", tmpaddr);
+			tmpaddr = load_32bit_word(cpu,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 8);
+			fatal("  +8: %08x\n", tmpaddr);
+			tmpaddr = load_32bit_word(cpu,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 12);
+			fatal(" +12: %08x\n", tmpaddr);
+
+			/*  TODO: This is probably netbsd specific  */
+			tmpaddr = load_32bit_word(cpu,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 12);
+			fatal("tmpaddr 1 = 0x%08x\n", tmpaddr);
+
+			/*  "done" word for NetBSD:  */
+			store_32bit_word(cpu, tmpaddr, 1);
+			/*  "done" word A for Linux:  */
+			store_32bit_word(cpu, tmpaddr + 4, 1);
+			/*  "done" word B for Linux:  */
+			store_32bit_word(cpu,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 0, 0);
+		}
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 65:
+		fatal("[ SIFBIOS alloc iop heap(0x" PRIx32") ]\n",
+		    (uint32_t)cpu->cd.mips.gpr[MIPS_GPR_A1]);
+
+		/*
+		 *  Linux uses this to allocate "heap" for the OHCI USB
+		 *  controller.
+		 *
+		 *  TODO:  This na�ve implementation does not allow for a
+		 *  "free iop heap" function: :-/
+		 */
+
+		{
+			uint32_t tmpaddr;
+			static uint32_t return_addr = 0x1000;
+				/*  0xbc000000;  */
+			uint32_t size;
+
+			tmpaddr = load_32bit_word(cpu,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 0);
+			fatal("  +0: %08x (result should be placed here)\n",
+			    tmpaddr);
+			tmpaddr = load_32bit_word(cpu,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 4);
+			fatal("  +4: %08x (*arg)\n", tmpaddr);
+			size = load_32bit_word(cpu, tmpaddr + 0);
+			fatal("      size = %08x\n", size);
+			tmpaddr = load_32bit_word(cpu,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 8);
+			fatal("  +8: %08x (*func (void *, int))\n", tmpaddr);
+			tmpaddr = load_32bit_word(cpu,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 12);
+			fatal(" +12: %08x (*para)\n", tmpaddr);
+
+			/*  TODO: This is probably netbsd specific  */
+			tmpaddr = load_32bit_word(cpu,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 12);
+			fatal("tmpaddr 1 = 0x%08x\n", tmpaddr);
+
+			/*  "done" word for NetBSD:  */
+			store_32bit_word(cpu, tmpaddr, 1);
+			/*  "done" word A for Linux:  */
+			store_32bit_word(cpu, tmpaddr + 4, 1);
+
+			/*  Result:  */
+			store_32bit_word(cpu,
+			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 0, return_addr);
+
+			return_addr += size;
+			/*  Round up to next page:  */
+			return_addr += 4095;
+			return_addr &= ~4095;
+		}
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+		break;
+	case 66:
+		debug("[ SIFBIOS iopmem_free(): TODO ]\n");
+		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;		/*  TODO  */
+		break;
+	default:
+		quiet_mode = 0;
+		cpu_register_dump(cpu->machine, cpu, 1, 0x1);
+		printf("\n");
+		fatal("Playstation 2 SIFBIOS emulation: "
+		    "unimplemented call nr 0x%x\n", callnr);
+		cpu->running = 0;
+	}
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/promemul/ps2_bios.cc gxemul-0.7.0+dfsg/src/promemul/ps2_bios.cc
--- gxemul-0.6.2/src/promemul/ps2_bios.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/ps2_bios.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,235 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: Playstation 2 SIFBIOS emulation
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-#include <sys/time.h>
-#include <sys/resource.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "cpu_mips.h"
-#include "machine.h"
-#include "memory.h"
-
-
-extern int quiet_mode;
-
-
-/*
- *  playstation2_sifbios_emul():
- */
-int playstation2_sifbios_emul(struct cpu *cpu)
-{
-	int callnr;
-
-	callnr = cpu->cd.mips.gpr[MIPS_GPR_A0];
-
-	switch (callnr) {
-	case 0:			/*  getver()  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0x200;		/*  TODO  */
-		break;
-	case 1:			/*  halt(int mode)  */
-		debug("[ SIFBIOS halt(0x%" PRIx64") ]\n",
-		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1]);
-		cpu->running = 0;
-		break;
-	case 2:			/*  setdve(int mode)  */
-		debug("[ SIFBIOS setdve(0x%" PRIx64") ]\n",
-		    (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1]);
-		break;
-	case 3:			/*  putchar(int ch)  */
-		/*  debug("[ SIFBIOS putchar(0x%x) ]\n",
-		    (char)cpu->cd.mips.gpr[MIPS_GPR_A1]);  */
-		console_putchar(cpu->machine->main_console_handle,
-		    cpu->cd.mips.gpr[MIPS_GPR_A1]);
-		break;
-	case 4:			/*  getchar()  */
-		/*  This is untested. TODO  */
-		/*  debug("[ SIFBIOS getchar() ]\n";  */
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		if (console_charavail(cpu->machine->main_console_handle))
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = console_readchar(
-			    cpu->machine->main_console_handle);
-		break;
-	case 16:		/*  dma_init()  */
-		debug("[ SIFBIOS dma_init() ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;		/*  TODO  */
-		break;
-	case 17:		/*  dma_exit()  */
-		debug("[ SIFBIOS dma_exit() ]\n");
-		break;
-	case 32:		/*  cmd_init()  */
-		debug("[ SIFBIOS cmd_init() ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;		/*  TODO  */
-		break;
-	case 33:		/*  cmd_exit()  */
-		debug("[ SIFBIOS cmd_exit() ]\n");
-		break;
-	case 48:
-		debug("[ SIFBIOS rpc_init(): TODO ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;		/*  TODO  */
-		break;
-	case 49:
-		debug("[ SIFBIOS rpc_exit(): TODO ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;		/*  TODO  */
-		break;
-	case 51:
-		debug("[ SIFBIOS rpc_bind(): TODO ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 1;		/*  TODO  */
-		break;
-	case 64:
-		fatal("[ SIFBIOS SBR_IOPH_INIT(0x%" PRIx32",0x%" PRIx32",0x%"
-		    PRIx32"): TODO ]\n",
-		    (uint32_t) cpu->cd.mips.gpr[MIPS_GPR_A1],
-		    (uint32_t) cpu->cd.mips.gpr[MIPS_GPR_A2],
-		    (uint32_t) cpu->cd.mips.gpr[MIPS_GPR_A3]);
-
-		/*
-		 *  This is really really ugly:   TODO
-		 *
-		 *  Linux and NetBSD seem to work, but it's an ugly hack.
-		 *  This should really be a callback thingy...
-		 *
-		 *  NetBSD has a done-word which should be set to 1.
-		 *  Linux has one done-word which should be set to 1, and
-		 *  one which should be set to 0.
-		 *
-		 *  The code as it is right now probably overwrites stuff in
-		 *  memory that shouldn't be touched. Not good.
-		 *
-		 *  Linux: err = sbios_rpc(SBR_IOPH_INIT, NULL, &result);
-		 *         err should be 0 (just as NetBSD),
-		 *         and result should be set to 0 as well.
-		 */
-		{
-			uint32_t tmpaddr;
-
-			tmpaddr = load_32bit_word(cpu,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 0);
-			fatal("  +0: %08x\n", tmpaddr);
-			tmpaddr = load_32bit_word(cpu,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 4);
-			fatal("  +4: %08x\n", tmpaddr);
-			tmpaddr = load_32bit_word(cpu,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 8);
-			fatal("  +8: %08x\n", tmpaddr);
-			tmpaddr = load_32bit_word(cpu,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 12);
-			fatal(" +12: %08x\n", tmpaddr);
-
-			/*  TODO: This is probably netbsd specific  */
-			tmpaddr = load_32bit_word(cpu,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 12);
-			fatal("tmpaddr 1 = 0x%08x\n", tmpaddr);
-
-			/*  "done" word for NetBSD:  */
-			store_32bit_word(cpu, tmpaddr, 1);
-			/*  "done" word A for Linux:  */
-			store_32bit_word(cpu, tmpaddr + 4, 1);
-			/*  "done" word B for Linux:  */
-			store_32bit_word(cpu,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 0, 0);
-		}
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 65:
-		fatal("[ SIFBIOS alloc iop heap(0x" PRIx32") ]\n",
-		    (uint32_t)cpu->cd.mips.gpr[MIPS_GPR_A1]);
-
-		/*
-		 *  Linux uses this to allocate "heap" for the OHCI USB
-		 *  controller.
-		 *
-		 *  TODO:  This na�ve implementation does not allow for a
-		 *  "free iop heap" function: :-/
-		 */
-
-		{
-			uint32_t tmpaddr;
-			static uint32_t return_addr = 0x1000;
-				/*  0xbc000000;  */
-			uint32_t size;
-
-			tmpaddr = load_32bit_word(cpu,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 0);
-			fatal("  +0: %08x (result should be placed here)\n",
-			    tmpaddr);
-			tmpaddr = load_32bit_word(cpu,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 4);
-			fatal("  +4: %08x (*arg)\n", tmpaddr);
-			size = load_32bit_word(cpu, tmpaddr + 0);
-			fatal("      size = %08x\n", size);
-			tmpaddr = load_32bit_word(cpu,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 8);
-			fatal("  +8: %08x (*func (void *, int))\n", tmpaddr);
-			tmpaddr = load_32bit_word(cpu,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 12);
-			fatal(" +12: %08x (*para)\n", tmpaddr);
-
-			/*  TODO: This is probably netbsd specific  */
-			tmpaddr = load_32bit_word(cpu,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 12);
-			fatal("tmpaddr 1 = 0x%08x\n", tmpaddr);
-
-			/*  "done" word for NetBSD:  */
-			store_32bit_word(cpu, tmpaddr, 1);
-			/*  "done" word A for Linux:  */
-			store_32bit_word(cpu, tmpaddr + 4, 1);
-
-			/*  Result:  */
-			store_32bit_word(cpu,
-			    cpu->cd.mips.gpr[MIPS_GPR_A1] + 0, return_addr);
-
-			return_addr += size;
-			/*  Round up to next page:  */
-			return_addr += 4095;
-			return_addr &= ~4095;
-		}
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-		break;
-	case 66:
-		debug("[ SIFBIOS iopmem_free(): TODO ]\n");
-		cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;		/*  TODO  */
-		break;
-	default:
-		quiet_mode = 0;
-		cpu_register_dump(cpu->machine, cpu, 1, 0x1);
-		printf("\n");
-		fatal("Playstation 2 SIFBIOS emulation: "
-		    "unimplemented call nr 0x%x\n", callnr);
-		cpu->running = 0;
-	}
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/promemul/sh_ipl_g.c gxemul-0.7.0+dfsg/src/promemul/sh_ipl_g.c
--- gxemul-0.6.2/src/promemul/sh_ipl_g.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/sh_ipl_g.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,114 @@
+/*
+ *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: SH-IPL+G emulation
+ *
+ *  Very basic, only what is needed to get OpenBSD/landisk booting.
+ *  (SH-IPL+G stands for SuperH Initial Program Loader + GDB stub.)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+
+#include "cpu.h"
+#include "cpu_sh.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+
+#include "thirdparty/sh4_exception.h"
+
+
+/*
+ *  sh_ipl_g_emul_init():
+ */
+void sh_ipl_g_emul_init(struct machine *machine)
+{
+	struct cpu *cpu = machine->cpus[0];
+
+	cpu->cd.sh.vbr = 0x8c000000;
+	store_16bit_word(cpu, 0x8c000100, SH_INVALID_INSTR);
+	store_16bit_word(cpu, 0x8c000102, 0x002b);  	/*  rte  */
+	store_16bit_word(cpu, 0x8c000104, 0x0009);  	/*  nop  */
+}
+
+
+/*
+ *  sh_ipl_g_promcall():
+ *
+ *  SH-IPL+G PROM call emulation.
+ */
+static int sh_ipl_g_promcall(struct cpu *cpu)
+{
+	/*
+	 *  SH-IPL+G call numbers are in R0:
+	 *
+	 *  NOTE: r_bank[0], since this is in a trap handler!
+	 */
+	switch (cpu->cd.sh.r_bank[0]) {
+
+	case 4:	/*  Get memory size.  */
+		cpu->cd.sh.r_bank[0] = 64 * 1048576;
+		/*  Note: cpu->machine->physical_ram_in_mb * 1048576
+		    would be more correct, but physical_ram_in_mb is
+		    set to 2 for landisk emulation...  */
+		break;
+
+	default:cpu_register_dump(cpu->machine, cpu, 1, 0);
+		printf("\n");
+		fatal("[ SH-IPL+G PROM emulation: unimplemented function 0x%"
+		    PRIx32" ]\n", cpu->cd.sh.r_bank[0]);
+		cpu->running = 0;
+		return 0;
+	}
+
+	return 1;
+}
+
+
+/*
+ *  sh_ipl_g_emul():
+ */
+int sh_ipl_g_emul(struct cpu *cpu)
+{
+	/*  SH-IPL+G calls are "trapa #63":  */
+	if (cpu->cd.sh.expevt == EXPEVT_TRAPA &&
+	    cpu->cd.sh.tra == 0xfc) {
+		return sh_ipl_g_promcall(cpu);
+	} else {
+		cpu_register_dump(cpu->machine, cpu, 1, 0);
+		printf("\n");
+		fatal("[ SH-IPL+G PROM emulation: expevt=0x%x, "
+		    " tra=0x%x ]\n", (int)cpu->cd.sh.expevt,
+		    (int)cpu->cd.sh.tra);
+		cpu->running = 0;
+		return 0;
+	}
+}
+
diff -Nru gxemul-0.6.2/src/promemul/sh_ipl_g.cc gxemul-0.7.0+dfsg/src/promemul/sh_ipl_g.cc
--- gxemul-0.6.2/src/promemul/sh_ipl_g.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/sh_ipl_g.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,114 +0,0 @@
-/*
- *  Copyright (C) 2007-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: SH-IPL+G emulation
- *
- *  Very basic, only what is needed to get OpenBSD/landisk booting.
- *  (SH-IPL+G stands for SuperH Initial Program Loader + GDB stub.)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-
-#include "cpu.h"
-#include "cpu_sh.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-
-#include "thirdparty/sh4_exception.h"
-
-
-/*
- *  sh_ipl_g_emul_init():
- */
-void sh_ipl_g_emul_init(struct machine *machine)
-{
-	struct cpu *cpu = machine->cpus[0];
-
-	cpu->cd.sh.vbr = 0x8c000000;
-	store_16bit_word(cpu, 0x8c000100, SH_INVALID_INSTR);
-	store_16bit_word(cpu, 0x8c000102, 0x002b);  	/*  rte  */
-	store_16bit_word(cpu, 0x8c000104, 0x0009);  	/*  nop  */
-}
-
-
-/*
- *  sh_ipl_g_promcall():
- *
- *  SH-IPL+G PROM call emulation.
- */
-static int sh_ipl_g_promcall(struct cpu *cpu)
-{
-	/*
-	 *  SH-IPL+G call numbers are in R0:
-	 *
-	 *  NOTE: r_bank[0], since this is in a trap handler!
-	 */
-	switch (cpu->cd.sh.r_bank[0]) {
-
-	case 4:	/*  Get memory size.  */
-		cpu->cd.sh.r_bank[0] = 64 * 1048576;
-		/*  Note: cpu->machine->physical_ram_in_mb * 1048576
-		    would be more correct, but physical_ram_in_mb is
-		    set to 2 for landisk emulation...  */
-		break;
-
-	default:cpu_register_dump(cpu->machine, cpu, 1, 0);
-		printf("\n");
-		fatal("[ SH-IPL+G PROM emulation: unimplemented function 0x%"
-		    PRIx32" ]\n", cpu->cd.sh.r_bank[0]);
-		cpu->running = 0;
-		return 0;
-	}
-
-	return 1;
-}
-
-
-/*
- *  sh_ipl_g_emul():
- */
-int sh_ipl_g_emul(struct cpu *cpu)
-{
-	/*  SH-IPL+G calls are "trapa #63":  */
-	if (cpu->cd.sh.expevt == EXPEVT_TRAPA &&
-	    cpu->cd.sh.tra == 0xfc) {
-		return sh_ipl_g_promcall(cpu);
-	} else {
-		cpu_register_dump(cpu->machine, cpu, 1, 0);
-		printf("\n");
-		fatal("[ SH-IPL+G PROM emulation: expevt=0x%x, "
-		    " tra=0x%x ]\n", (int)cpu->cd.sh.expevt,
-		    (int)cpu->cd.sh.tra);
-		cpu->running = 0;
-		return 0;
-	}
-}
-
diff -Nru gxemul-0.6.2/src/promemul/yamon.c gxemul-0.7.0+dfsg/src/promemul/yamon.c
--- gxemul-0.6.2/src/promemul/yamon.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/yamon.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,241 @@
+/*
+ *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  COMMENT: YAMON emulation
+ *
+ *  (Very basic, only what is needed to get NetBSD booting.)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+
+#include "console.h"
+#include "cpu.h"
+#include "cpu_mips.h"
+#include "machine.h"
+#include "memory.h"
+#include "misc.h"
+#include "net.h"
+
+#include "thirdparty/yamon.h"
+
+
+/*
+ *  yamon_machine_setup():
+ */
+void yamon_machine_setup(struct machine *machine, uint64_t env)
+{
+	char tmps[200];
+	char macaddr[6];
+	uint64_t tmpptr = env + 0x400;
+	struct cpu *cpu = machine->cpus[0];
+
+	/*
+	 *  Standard YAMON environment variables:
+	 *
+	 *	baseboardserial
+	 *	bootfile		TODO
+	 *	bootprot		TODO: Non-tftp boot
+	 *	bootserport
+	 *	bootserver
+	 *	cpuconfig		TODO
+	 *	ethaddr
+	 *	fpu			TODO
+	 *	gateway
+	 *	ipaddr			TODO: Don't hardcode!
+	 *	memsize
+	 *	modetty0
+	 *	modetty1
+	 *	prompt
+	 *	start			TODO
+	 *	startdelay		TODO
+	 *	subnetmask		TODO: Real subnet mask
+	 *	yamonrev
+	 */
+
+	add_environment_string_dual(cpu, &env, &tmpptr,
+	    "baseboardserial", "0000000000");
+
+	/*  TODO: Disk boot!  */
+	add_environment_string_dual(cpu, &env, &tmpptr, "bootprot", "tftp");
+
+	add_environment_string_dual(cpu, &env, &tmpptr, "bootserport", "tty0");
+
+	add_environment_string_dual(cpu, &env, &tmpptr,
+	    "bootserver", "10.0.0.254");
+
+	net_generate_unique_mac(machine, (unsigned char *) macaddr);
+	snprintf(tmps, sizeof(tmps), "%02x.%02x.%02x.%02x.%02x.%02x",
+	    macaddr[0], macaddr[1], macaddr[2],
+	    macaddr[3], macaddr[4], macaddr[5]);
+	add_environment_string_dual(cpu, &env, &tmpptr, "ethaddr", tmps);
+
+	add_environment_string_dual(cpu, &env, &tmpptr,
+	    "gateway", "10.0.0.254");
+
+	/*  TODO: Don't hardcode!  */
+	add_environment_string_dual(cpu, &env, &tmpptr,
+	    "ipaddr", "10.0.0.1");
+
+	snprintf(tmps, sizeof(tmps), "0x%08x", machine->physical_ram_in_mb<<20);
+	add_environment_string_dual(cpu, &env, &tmpptr, "memsize", tmps);
+
+	add_environment_string_dual(cpu, &env, &tmpptr,
+	    "modetty0", "38400,n,8,1,none");
+
+	add_environment_string_dual(cpu, &env, &tmpptr,
+	    "modetty1", "38400,n,8,1,none");
+
+	add_environment_string_dual(cpu, &env, &tmpptr, "prompt", "YAMON");
+
+	add_environment_string_dual(cpu, &env, &tmpptr, "yamonrev", "02.06");
+
+	/*  TODO: Real subnet mask:  */
+	add_environment_string_dual(cpu, &env, &tmpptr,
+	    "subnetmask", "255.0.0.0");
+
+
+	/*  FreeBSD development specific:  */
+	snprintf(tmps, sizeof(tmps), "%i", machine->emulated_hz / 1000);
+	add_environment_string_dual(cpu, &env, &tmpptr, "khz", tmps);
+
+	/*  NULL terminate:  */
+	tmpptr = 0;
+	add_environment_string_dual(cpu, &env, &tmpptr, NULL, NULL);
+}
+
+
+/*
+ *  yamon_emul():
+ *
+ *  YAMON emulation (for evbmips).
+ */
+int yamon_emul(struct cpu *cpu)
+{
+	uint32_t ofs = (cpu->pc & 0xff) + YAMON_FUNCTION_BASE;
+	uint8_t ch;
+	int n;
+	uint32_t oid;
+	uint64_t paddr, psize;
+
+	switch (ofs) {
+
+	case YAMON_PRINT_COUNT_OFS:
+		/*
+		 *  print count:
+		 *	a1 = string
+		 *	a2 = count
+		 */
+		n = 0;
+		while (n < (int32_t)cpu->cd.mips.gpr[MIPS_GPR_A2]) {
+			cpu->memory_rw(cpu, cpu->mem, (int32_t)cpu->cd.mips.gpr
+			    [MIPS_GPR_A1] + n, &ch, sizeof(ch), MEM_READ,
+			    CACHE_DATA | NO_EXCEPTIONS);
+			console_putchar(cpu->machine->main_console_handle, ch);
+			n++;
+		}
+		break;
+
+	case YAMON_EXIT_OFS:
+		/*
+		 *  exit
+		 */
+		debug("[ yamon_emul(): exit ]\n");
+		cpu->running = 0;
+		break;
+
+	/*  YAMON_FLUSH_CACHE_OFS: TODO  */
+	/*  YAMON_PRINT_OFS: TODO  */
+	/*  YAMON_REG_CPU_ISR_OFS: TODO  */
+	/*  YAMON_DEREG_CPU_ISR_OFS: TODO  */
+	/*  YAMON_REG_IC_ISR_OFS: TODO  */
+	/*  YAMON_DEREG_IC_ISR_OFS: TODO  */
+	/*  YAMON_REG_ESR_OFS: TODO  */
+	/*  YAMON_DEREG_ESR_OFS: TODO  */
+
+	case YAMON_GETCHAR_OFS:
+		n = console_readchar(cpu->machine->main_console_handle);
+		/*  Note: -1 (if no char was available) becomes 0xff:  */
+		ch = n;
+		cpu->memory_rw(cpu, cpu->mem, (int32_t)cpu->cd.mips.gpr[
+		    MIPS_GPR_A1], &ch, sizeof(ch), MEM_WRITE,
+		    CACHE_DATA | NO_EXCEPTIONS);
+		break;
+
+	case YAMON_SYSCON_READ_OFS:
+		/*
+		 *  syscon_read(oid [a0], addr [a1], size [a2])
+		 */
+
+		oid = cpu->cd.mips.gpr[MIPS_GPR_A0];
+		paddr = cpu->cd.mips.gpr[MIPS_GPR_A1];
+		psize = cpu->cd.mips.gpr[MIPS_GPR_A2];
+
+		switch (oid) {
+		case SYSCON_BOARD_CPU_CLOCK_FREQ_ID:
+			if (psize == sizeof(uint32_t)) {
+				uint32_t freq = cpu->machine->emulated_hz;
+
+				debug("[ yamon_emul(): reporting CPU "
+				    "frequency of %u ]\n", (unsigned int)
+				    freq);
+
+				if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
+					freq = LE32_TO_HOST(freq);
+				else
+					freq = BE32_TO_HOST(freq);
+
+				cpu->memory_rw(cpu, cpu->mem, (int32_t)paddr,
+				    (unsigned char *) (void *) &freq, sizeof(freq), MEM_WRITE,
+				    CACHE_DATA | NO_EXCEPTIONS);
+
+				cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+			} else {
+				cpu->cd.mips.gpr[MIPS_GPR_V0] = 1;
+			}
+			break;
+
+		default:
+			fatal("[ yamon_emul(): unimplemented object id 0x%"
+			    PRIx32" ]\n", oid);
+			cpu->cd.mips.gpr[MIPS_GPR_V0] = 1;
+		}
+		break;
+
+	default:
+		cpu_register_dump(cpu->machine, cpu, 1, 0);
+		printf("\n");
+		fatal("[ yamon_emul(): unimplemented yamon function 0x%"
+		    PRIx32" ]\n", ofs);
+		cpu->running = 0;
+	}
+
+	return 1;
+}
+
diff -Nru gxemul-0.6.2/src/promemul/yamon.cc gxemul-0.7.0+dfsg/src/promemul/yamon.cc
--- gxemul-0.6.2/src/promemul/yamon.cc	2019-06-22 18:23:26.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/promemul/yamon.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,241 +0,0 @@
-/*
- *  Copyright (C) 2005-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  COMMENT: YAMON emulation
- *
- *  (Very basic, only what is needed to get NetBSD booting.)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-
-#include "console.h"
-#include "cpu.h"
-#include "cpu_mips.h"
-#include "machine.h"
-#include "memory.h"
-#include "misc.h"
-#include "net.h"
-
-#include "thirdparty/yamon.h"
-
-
-/*
- *  yamon_machine_setup():
- */
-void yamon_machine_setup(struct machine *machine, uint64_t env)
-{
-	char tmps[200];
-	char macaddr[6];
-	uint64_t tmpptr = env + 0x400;
-	struct cpu *cpu = machine->cpus[0];
-
-	/*
-	 *  Standard YAMON environment variables:
-	 *
-	 *	baseboardserial
-	 *	bootfile		TODO
-	 *	bootprot		TODO: Non-tftp boot
-	 *	bootserport
-	 *	bootserver
-	 *	cpuconfig		TODO
-	 *	ethaddr
-	 *	fpu			TODO
-	 *	gateway
-	 *	ipaddr			TODO: Don't hardcode!
-	 *	memsize
-	 *	modetty0
-	 *	modetty1
-	 *	prompt
-	 *	start			TODO
-	 *	startdelay		TODO
-	 *	subnetmask		TODO: Real subnet mask
-	 *	yamonrev
-	 */
-
-	add_environment_string_dual(cpu, &env, &tmpptr,
-	    "baseboardserial", "0000000000");
-
-	/*  TODO: Disk boot!  */
-	add_environment_string_dual(cpu, &env, &tmpptr, "bootprot", "tftp");
-
-	add_environment_string_dual(cpu, &env, &tmpptr, "bootserport", "tty0");
-
-	add_environment_string_dual(cpu, &env, &tmpptr,
-	    "bootserver", "10.0.0.254");
-
-	net_generate_unique_mac(machine, (unsigned char *) macaddr);
-	snprintf(tmps, sizeof(tmps), "%02x.%02x.%02x.%02x.%02x.%02x",
-	    macaddr[0], macaddr[1], macaddr[2],
-	    macaddr[3], macaddr[4], macaddr[5]);
-	add_environment_string_dual(cpu, &env, &tmpptr, "ethaddr", tmps);
-
-	add_environment_string_dual(cpu, &env, &tmpptr,
-	    "gateway", "10.0.0.254");
-
-	/*  TODO: Don't hardcode!  */
-	add_environment_string_dual(cpu, &env, &tmpptr,
-	    "ipaddr", "10.0.0.1");
-
-	snprintf(tmps, sizeof(tmps), "0x%08x", machine->physical_ram_in_mb<<20);
-	add_environment_string_dual(cpu, &env, &tmpptr, "memsize", tmps);
-
-	add_environment_string_dual(cpu, &env, &tmpptr,
-	    "modetty0", "38400,n,8,1,none");
-
-	add_environment_string_dual(cpu, &env, &tmpptr,
-	    "modetty1", "38400,n,8,1,none");
-
-	add_environment_string_dual(cpu, &env, &tmpptr, "prompt", "YAMON");
-
-	add_environment_string_dual(cpu, &env, &tmpptr, "yamonrev", "02.06");
-
-	/*  TODO: Real subnet mask:  */
-	add_environment_string_dual(cpu, &env, &tmpptr,
-	    "subnetmask", "255.0.0.0");
-
-
-	/*  FreeBSD development specific:  */
-	snprintf(tmps, sizeof(tmps), "%i", machine->emulated_hz / 1000);
-	add_environment_string_dual(cpu, &env, &tmpptr, "khz", tmps);
-
-	/*  NULL terminate:  */
-	tmpptr = 0;
-	add_environment_string_dual(cpu, &env, &tmpptr, NULL, NULL);
-}
-
-
-/*
- *  yamon_emul():
- *
- *  YAMON emulation (for evbmips).
- */
-int yamon_emul(struct cpu *cpu)
-{
-	uint32_t ofs = (cpu->pc & 0xff) + YAMON_FUNCTION_BASE;
-	uint8_t ch;
-	int n;
-	uint32_t oid;
-	uint64_t paddr, psize;
-
-	switch (ofs) {
-
-	case YAMON_PRINT_COUNT_OFS:
-		/*
-		 *  print count:
-		 *	a1 = string
-		 *	a2 = count
-		 */
-		n = 0;
-		while (n < (int32_t)cpu->cd.mips.gpr[MIPS_GPR_A2]) {
-			cpu->memory_rw(cpu, cpu->mem, (int32_t)cpu->cd.mips.gpr
-			    [MIPS_GPR_A1] + n, &ch, sizeof(ch), MEM_READ,
-			    CACHE_DATA | NO_EXCEPTIONS);
-			console_putchar(cpu->machine->main_console_handle, ch);
-			n++;
-		}
-		break;
-
-	case YAMON_EXIT_OFS:
-		/*
-		 *  exit
-		 */
-		debug("[ yamon_emul(): exit ]\n");
-		cpu->running = 0;
-		break;
-
-	/*  YAMON_FLUSH_CACHE_OFS: TODO  */
-	/*  YAMON_PRINT_OFS: TODO  */
-	/*  YAMON_REG_CPU_ISR_OFS: TODO  */
-	/*  YAMON_DEREG_CPU_ISR_OFS: TODO  */
-	/*  YAMON_REG_IC_ISR_OFS: TODO  */
-	/*  YAMON_DEREG_IC_ISR_OFS: TODO  */
-	/*  YAMON_REG_ESR_OFS: TODO  */
-	/*  YAMON_DEREG_ESR_OFS: TODO  */
-
-	case YAMON_GETCHAR_OFS:
-		n = console_readchar(cpu->machine->main_console_handle);
-		/*  Note: -1 (if no char was available) becomes 0xff:  */
-		ch = n;
-		cpu->memory_rw(cpu, cpu->mem, (int32_t)cpu->cd.mips.gpr[
-		    MIPS_GPR_A1], &ch, sizeof(ch), MEM_WRITE,
-		    CACHE_DATA | NO_EXCEPTIONS);
-		break;
-
-	case YAMON_SYSCON_READ_OFS:
-		/*
-		 *  syscon_read(oid [a0], addr [a1], size [a2])
-		 */
-
-		oid = cpu->cd.mips.gpr[MIPS_GPR_A0];
-		paddr = cpu->cd.mips.gpr[MIPS_GPR_A1];
-		psize = cpu->cd.mips.gpr[MIPS_GPR_A2];
-
-		switch (oid) {
-		case SYSCON_BOARD_CPU_CLOCK_FREQ_ID:
-			if (psize == sizeof(uint32_t)) {
-				uint32_t freq = cpu->machine->emulated_hz;
-
-				debug("[ yamon_emul(): reporting CPU "
-				    "frequency of %u ]\n", (unsigned int)
-				    freq);
-
-				if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
-					freq = LE32_TO_HOST(freq);
-				else
-					freq = BE32_TO_HOST(freq);
-
-				cpu->memory_rw(cpu, cpu->mem, (int32_t)paddr,
-				    (unsigned char *) (void *) &freq, sizeof(freq), MEM_WRITE,
-				    CACHE_DATA | NO_EXCEPTIONS);
-
-				cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
-			} else {
-				cpu->cd.mips.gpr[MIPS_GPR_V0] = 1;
-			}
-			break;
-
-		default:
-			fatal("[ yamon_emul(): unimplemented object id 0x%"
-			    PRIx32" ]\n", oid);
-			cpu->cd.mips.gpr[MIPS_GPR_V0] = 1;
-		}
-		break;
-
-	default:
-		cpu_register_dump(cpu->machine, cpu, 1, 0);
-		printf("\n");
-		fatal("[ yamon_emul(): unimplemented yamon function 0x%"
-		    PRIx32" ]\n", ofs);
-		cpu->running = 0;
-	}
-
-	return 1;
-}
-
diff -Nru gxemul-0.6.2/src/README gxemul-0.7.0+dfsg/src/README
--- gxemul-0.6.2/src/README	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/README	1970-01-01 00:00:00.000000000 +0000
@@ -1,37 +0,0 @@
-GXemul's source code contains code from two trees;
-the largest portion is the original emulator code written in plain C,
-and the smaller (newer) portion is written in C++. All files have been
-converted to a .cc (C++) extension, however, and C++ features may be
-used by both the older and newer parts of the code.
-
-
-NEW CODE
---------
-
-	components
-	main
-	plugins
-	ui
-
-
-SHARED
-------
-
-	include
-
-
-ORIGINAL EMULATOR CODE
-----------------------
-
-	console
-	cpus		(new cpus are in components/cpu/)
-	debugger	(corresponds to main/CommandInterpreter.cc)
-	devices		(corresponds to components/)
-	disk
-	file		(new file loaders are in main/fileloaders/)
-	machines	(new machines are in components/machines/)
-	net
-	old_main
-	promemul
-	symbol
-
diff -Nru gxemul-0.6.2/src/symbol/Makefile.skel gxemul-0.7.0+dfsg/src/symbol/Makefile.skel
--- gxemul-0.6.2/src/symbol/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/symbol/Makefile.skel	2021-11-27 09:42:23.000000000 +0000
@@ -4,7 +4,7 @@
 #  Symbol handling support.
 #
 
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(DINCLUDE)
+CFLAGS=$(CWARNINGS) $(COPTIM) $(DINCLUDE)
 
 OBJS=symbol.o symbol_demangle.o
 
diff -Nru gxemul-0.6.2/src/symbol/symbol.c gxemul-0.7.0+dfsg/src/symbol/symbol.c
--- gxemul-0.6.2/src/symbol/symbol.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/symbol/symbol.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,427 @@
+/*
+ *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  Address to symbol translation routines.
+ *
+ *  This module is (probably) independent from the rest of the emulator.
+ *  symbol_init() must be called before any other function in this file is used.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "symbol.h"
+
+
+#define	SYMBOLBUF_MAX	100
+
+
+/*
+ *  symbol_nsymbols():
+ *
+ *  Return n_symbols.
+ */
+int symbol_nsymbols(struct symbol_context *sc)
+{
+	return sc->n_symbols;
+}
+
+
+/*
+ *  get_symbol_addr():
+ *
+ *  Find a symbol by name. If addr is non-NULL, *addr is set to the symbol's
+ *  address. Return value is 1 if the symbol is found, 0 otherwise.
+ *
+ *  NOTE:  This is O(n).
+ */
+int get_symbol_addr(struct symbol_context *sc, const char *symbol, uint64_t *addr)
+{
+	struct symbol *s;
+
+	if (sc->sorted_array) {
+		int i;
+		for (i=0; i<sc->n_symbols; i++)
+			if (strcmp(symbol, sc->first_symbol[i].name) == 0) {
+				if (addr != NULL)
+					*addr = sc->first_symbol[i].addr;
+				return 1;
+			}
+	} else {
+		s = sc->first_symbol;
+		while (s != NULL) {
+			if (strcmp(symbol, s->name) == 0) {
+				if (addr != NULL)
+					*addr = s->addr;
+				return 1;
+			}
+			s = s->next;
+		}
+	}
+
+	return 0;
+}
+
+
+/*
+ *  get_symbol_name_and_n_args():
+ *
+ *  Translate an address into a symbol name.  The return value is a pointer
+ *  to a static char array, containing the symbol name.  (In other words,
+ *  this function is not reentrant. This removes the need for memory allocation
+ *  at the caller's side.)
+ *
+ *  If offset is not a NULL pointer, *offset is set to the offset within
+ *  the symbol. For example, if there is a symbol at address 0x1000 with
+ *  length 0x100, and a caller wants to know the symbol name of address
+ *  0x1008, the symbol's name will be found in the static char array, and
+ *  *offset will be set to 0x8.
+ *
+ *  If n_argsp is non-NULL, *n_argsp is set to the symbol's n_args value.
+ *
+ *  If no symbol was found, NULL is returned instead.
+ */
+static char symbol_buf[SYMBOLBUF_MAX+1];
+char *get_symbol_name_and_n_args(struct symbol_context *sc, uint64_t addr,
+	uint64_t *offset, int *n_argsp)
+{
+	struct symbol *s;
+
+	if (sc->n_symbols == 0)
+		return NULL;
+
+	if ((addr >> 32) == 0 && (addr & 0x80000000ULL))
+		addr |= 0xffffffff00000000ULL;
+
+	symbol_buf[0] = symbol_buf[SYMBOLBUF_MAX] = '\0';
+	if (offset != NULL)
+		*offset = 0;
+
+	if (!sc->sorted_array) {
+		/*  Slow, linear O(n) search:  */
+		s = sc->first_symbol;
+		while (s != NULL) {
+			/*  Found a match?  */
+			if (addr >= s->addr && addr < s->addr + s->len) {
+				if (addr == s->addr)
+					snprintf(symbol_buf, SYMBOLBUF_MAX,
+					    "%s", s->name);
+				else
+					snprintf(symbol_buf, SYMBOLBUF_MAX,
+					    "%s+0x%" PRIx64, s->name, (uint64_t)
+					    (addr - s->addr));
+				if (offset != NULL)
+					*offset = addr - s->addr;
+				if (n_argsp != NULL)
+					*n_argsp = s->n_args;
+				return symbol_buf;
+			}
+			s = s->next;
+		}
+	} else {
+		/*  Faster, O(log n) search:  */
+		int lowest = 0, highest = sc->n_symbols - 1;
+		while (lowest <= highest) {
+			int ofs = (lowest + highest) / 2;
+			s = sc->first_symbol + ofs;
+
+			/*  Found a match?  */
+			if (addr >= s->addr && addr <= s->addr + (s->len - 1)) {
+				if (addr == s->addr)
+					snprintf(symbol_buf, SYMBOLBUF_MAX,
+					    "%s%s%s",
+					    color_symbol_ptr(),
+					    s->name,
+					    color_normal_ptr());
+				else
+					snprintf(symbol_buf, SYMBOLBUF_MAX,
+					    "%s%s%s+0x%" PRIx64,
+					    color_symbol_ptr(),
+					    s->name,
+					    color_normal_ptr(),
+					    (uint64_t) (addr - s->addr));
+
+				if (offset != NULL)
+					*offset = addr - s->addr;
+				if (n_argsp != NULL)
+					*n_argsp = s->n_args;
+
+				return symbol_buf;
+			}
+
+			if (addr < s->addr)
+				highest = ofs - 1;
+			else
+				lowest = ofs + 1;
+		}
+	}
+
+	/*  Not found? Then return NULL.  */
+	return NULL;
+}
+
+
+/*
+ *  get_symbol_name():
+ *
+ *  See get_symbol_name_and_n_args().
+ */
+char *get_symbol_name(struct symbol_context *sc, uint64_t addr, uint64_t *offs)
+{
+	return get_symbol_name_and_n_args(sc, addr, offs, NULL);
+}
+
+
+/*
+ *  add_symbol_name():
+ *
+ *  Add a symbol to the symbol list.
+ */
+void add_symbol_name(struct symbol_context *sc,
+	uint64_t addr, uint64_t len, const char *name, int type, int n_args)
+{
+	struct symbol *s;
+
+	if (sc->sorted_array) {
+		fprintf(stderr, "add_symbol_name(): Internal error: the "
+		    "symbol array is already sorted\n");
+		exit(1);
+	}
+
+	if (name == NULL) {
+		fprintf(stderr, "add_symbol_name(): name = NULL\n");
+		exit(1);
+	}
+
+	if (addr == 0 && strcmp(name, "_DYNAMIC_LINK") == 0)
+		return;
+
+	if (name[0] == '\0')
+		return;
+
+	/*  TODO: Maybe this should be optional?  */
+	if (name[0] == '.' || name[0] == '$')
+		return;
+
+	/*  Quick test-hack:  */
+	if (n_args < 0) {
+		if (strcmp(name, "strlen") == 0)
+			n_args = 1;
+		if (strcmp(name, "strcmp") == 0)
+			n_args = 2;
+		if (strcmp(name, "strcpy") == 0)
+			n_args = 2;
+		if (strcmp(name, "strncpy") == 0)
+			n_args = 3;
+		if (strcmp(name, "strlcpy") == 0)
+			n_args = 3;
+		if (strcmp(name, "strlcat") == 0)
+			n_args = 3;
+		if (strcmp(name, "strncmp") == 0)
+			n_args = 3;
+		if (strcmp(name, "memset") == 0)
+			n_args = 3;
+		if (strcmp(name, "memcpy") == 0)
+			n_args = 3;
+		if (strcmp(name, "bzero") == 0)
+			n_args = 2;
+		if (strcmp(name, "bcopy") == 0)
+			n_args = 3;
+	}
+
+	if ((addr >> 32) == 0 && (addr & 0x80000000ULL))
+		addr |= 0xffffffff00000000ULL;
+
+	CHECK_ALLOCATION(s = (struct symbol *) malloc(sizeof(struct symbol)));
+	memset(s, 0, sizeof(struct symbol));
+
+	s->name = symbol_demangle_cplusplus(name);
+
+	if (s->name == NULL)
+		CHECK_ALLOCATION(s->name = strdup(name));
+
+	s->addr   = addr;
+	s->len    = len;
+	s->type   = type;
+	s->n_args = n_args;
+
+	sc->n_symbols ++;
+
+	/*  Add first in list:  */
+	s->next = sc->first_symbol;
+	sc->first_symbol = s;
+}
+
+
+/*
+ *  symbol_readfile():
+ *
+ *  Read 'nm -S' style symbols from a file.
+ *
+ *  TODO: This function is an ugly hack, and should be replaced
+ *  with something that reads symbols directly from the executable
+ *  images.
+ */
+void symbol_readfile(struct symbol_context *sc, char *fname)
+{
+	FILE *f;
+	char b1[80]; uint64_t addr;
+	char b2[80]; uint64_t len;
+	char b3[80]; int type;
+	char b4[80];
+	int cur_n_symbols = sc->n_symbols;
+
+	f = fopen(fname, "r");
+	if (f == NULL) {
+		perror(fname);
+		exit(1);
+	}
+
+	while (!feof(f)) {
+		memset(b1, 0, sizeof(b1));
+		memset(b2, 0, sizeof(b2));
+		memset(b3, 0, sizeof(b3));
+		memset(b4, 0, sizeof(b4));
+		if (fscanf(f, "%s %s\n", b1,b2) != 2)
+			fprintf(stderr, "warning: symbol file parse error\n");
+		if (strlen(b2) < 2 && !(b2[0]>='0' && b2[0]<='9')) {
+			strlcpy(b3, b2, sizeof(b3));
+			strlcpy(b2, "0", sizeof(b2));
+			if (fscanf(f, "%s\n", b4) != 1)
+				fprintf(stderr, "warning: symbol file parse error\n");
+		} else {
+			if (fscanf(f, "%s %s\n", b3,b4) != 2)
+				fprintf(stderr, "warning: symbol file parse error\n");
+		}
+
+		/*  printf("b1='%s' b2='%s' b3='%s' b4='%s'\n",
+		    b1,b2,b3,b4);  */
+		addr = strtoull(b1, NULL, 16);
+		len  = strtoull(b2, NULL, 16);
+		type = b3[0];
+		/*  printf("addr=%016" PRIx64" len=%016" PRIx64" type=%i\n",
+		    addr, len, type);  */
+
+		if (type == 't' || type == 'r' || type == 'g')
+			continue;
+
+		add_symbol_name(sc, addr, len, b4, type, -1);
+	}
+
+	fclose(f);
+
+	debug("%i symbols\n", sc->n_symbols - cur_n_symbols);
+}
+
+
+/*
+ *  sym_addr_compare():
+ *
+ *  Helper function for sorting symbols according to their address.
+ */
+int sym_addr_compare(const void *a, const void *b)
+{
+	struct symbol *p1 = (struct symbol *) a;
+	struct symbol *p2 = (struct symbol *) b;
+
+	if (p1->addr < p2->addr)
+		return -1;
+	if (p1->addr > p2->addr)
+		return 1;
+
+	return 0;
+}
+
+
+/*
+ *  symbol_recalc_sizes():
+ *
+ *  Recalculate sizes of symbols that have size = 0, by creating an array
+ *  containing all symbols, qsort()-ing that array according to address, and
+ *  recalculating the size fields if necessary.
+ */
+void symbol_recalc_sizes(struct symbol_context *sc)
+{
+	struct symbol *tmp_array;
+	struct symbol *last_ptr;
+	struct symbol *tmp_ptr;
+	int i;
+
+	CHECK_ALLOCATION(tmp_array = (struct symbol *) malloc(sizeof (struct symbol) *
+	    sc->n_symbols));
+
+	/*  Copy first_symbol --> tmp_array, and remove the old
+		first_symbol at the same time:  */
+	tmp_ptr = sc->first_symbol;
+	i = 0;
+	while (tmp_ptr != NULL) {
+		tmp_array[i] = *tmp_ptr;
+		last_ptr = tmp_ptr;
+		tmp_ptr = tmp_ptr->next;
+		free(last_ptr);
+		i++;
+	}
+
+	qsort(tmp_array, sc->n_symbols, sizeof(struct symbol),
+	    sym_addr_compare);
+	sc->sorted_array = 1;
+
+	/*  Recreate the first_symbol chain:  */
+	sc->first_symbol = NULL;
+	for (i=0; i<sc->n_symbols; i++) {
+		/*  Recalculate size, if 0:  */
+		if (tmp_array[i].len == 0) {
+			uint64_t len;
+			if (i != sc->n_symbols-1)
+				len = tmp_array[i+1].addr
+				    - tmp_array[i].addr;
+			else
+				len = 1;
+
+			tmp_array[i].len = len;
+		}
+
+		tmp_array[i].next = &tmp_array[i+1];
+	}
+
+	sc->first_symbol = tmp_array;
+}
+
+
+/*
+ *  symbol_init():
+ *
+ *  Initialize the symbol hashtables.
+ */
+void symbol_init(struct symbol_context *sc)
+{
+	sc->first_symbol = NULL;
+	sc->sorted_array = 0;
+	sc->n_symbols = 0;
+}
+
diff -Nru gxemul-0.6.2/src/symbol/symbol.cc gxemul-0.7.0+dfsg/src/symbol/symbol.cc
--- gxemul-0.6.2/src/symbol/symbol.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/symbol/symbol.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,421 +0,0 @@
-/*
- *  Copyright (C) 2003-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  Address to symbol translation routines.
- *
- *  This module is (probably) independent from the rest of the emulator.
- *  symbol_init() must be called before any other function in this file is used.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "symbol.h"
-
-
-#define	SYMBOLBUF_MAX	100
-
-
-/*
- *  symbol_nsymbols():
- *
- *  Return n_symbols.
- */
-int symbol_nsymbols(struct symbol_context *sc)
-{
-	return sc->n_symbols;
-}
-
-
-/*
- *  get_symbol_addr():
- *
- *  Find a symbol by name. If addr is non-NULL, *addr is set to the symbol's
- *  address. Return value is 1 if the symbol is found, 0 otherwise.
- *
- *  NOTE:  This is O(n).
- */
-int get_symbol_addr(struct symbol_context *sc, const char *symbol, uint64_t *addr)
-{
-	struct symbol *s;
-
-	if (sc->sorted_array) {
-		int i;
-		for (i=0; i<sc->n_symbols; i++)
-			if (strcmp(symbol, sc->first_symbol[i].name) == 0) {
-				if (addr != NULL)
-					*addr = sc->first_symbol[i].addr;
-				return 1;
-			}
-	} else {
-		s = sc->first_symbol;
-		while (s != NULL) {
-			if (strcmp(symbol, s->name) == 0) {
-				if (addr != NULL)
-					*addr = s->addr;
-				return 1;
-			}
-			s = s->next;
-		}
-	}
-
-	return 0;
-}
-
-
-/*
- *  get_symbol_name_and_n_args():
- *
- *  Translate an address into a symbol name.  The return value is a pointer
- *  to a static char array, containing the symbol name.  (In other words,
- *  this function is not reentrant. This removes the need for memory allocation
- *  at the caller's side.)
- *
- *  If offset is not a NULL pointer, *offset is set to the offset within
- *  the symbol. For example, if there is a symbol at address 0x1000 with
- *  length 0x100, and a caller wants to know the symbol name of address
- *  0x1008, the symbol's name will be found in the static char array, and
- *  *offset will be set to 0x8.
- *
- *  If n_argsp is non-NULL, *n_argsp is set to the symbol's n_args value.
- *
- *  If no symbol was found, NULL is returned instead.
- */
-static char symbol_buf[SYMBOLBUF_MAX+1];
-char *get_symbol_name_and_n_args(struct symbol_context *sc, uint64_t addr,
-	uint64_t *offset, int *n_argsp)
-{
-	struct symbol *s;
-
-	if (sc->n_symbols == 0)
-		return NULL;
-
-	if ((addr >> 32) == 0 && (addr & 0x80000000ULL))
-		addr |= 0xffffffff00000000ULL;
-
-	symbol_buf[0] = symbol_buf[SYMBOLBUF_MAX] = '\0';
-	if (offset != NULL)
-		*offset = 0;
-
-	if (!sc->sorted_array) {
-		/*  Slow, linear O(n) search:  */
-		s = sc->first_symbol;
-		while (s != NULL) {
-			/*  Found a match?  */
-			if (addr >= s->addr && addr < s->addr + s->len) {
-				if (addr == s->addr)
-					snprintf(symbol_buf, SYMBOLBUF_MAX,
-					    "%s", s->name);
-				else
-					snprintf(symbol_buf, SYMBOLBUF_MAX,
-					    "%s+0x%" PRIx64, s->name, (uint64_t)
-					    (addr - s->addr));
-				if (offset != NULL)
-					*offset = addr - s->addr;
-				if (n_argsp != NULL)
-					*n_argsp = s->n_args;
-				return symbol_buf;
-			}
-			s = s->next;
-		}
-	} else {
-		/*  Faster, O(log n) search:  */
-		int lowest = 0, highest = sc->n_symbols - 1;
-		while (lowest <= highest) {
-			int ofs = (lowest + highest) / 2;
-			s = sc->first_symbol + ofs;
-
-			/*  Found a match?  */
-			if (addr >= s->addr && addr <= s->addr + (s->len - 1)) {
-				if (addr == s->addr)
-					snprintf(symbol_buf, SYMBOLBUF_MAX,
-					    "%s", s->name);
-				else
-					snprintf(symbol_buf, SYMBOLBUF_MAX,
-					    "%s+0x%" PRIx64, s->name, (uint64_t)
-					    (addr - s->addr));
-
-				if (offset != NULL)
-					*offset = addr - s->addr;
-				if (n_argsp != NULL)
-					*n_argsp = s->n_args;
-
-				return symbol_buf;
-			}
-
-			if (addr < s->addr)
-				highest = ofs - 1;
-			else
-				lowest = ofs + 1;
-		}
-	}
-
-	/*  Not found? Then return NULL.  */
-	return NULL;
-}
-
-
-/*
- *  get_symbol_name():
- *
- *  See get_symbol_name_and_n_args().
- */
-char *get_symbol_name(struct symbol_context *sc, uint64_t addr, uint64_t *offs)
-{
-	return get_symbol_name_and_n_args(sc, addr, offs, NULL);
-}
-
-
-/*
- *  add_symbol_name():
- *
- *  Add a symbol to the symbol list.
- */
-void add_symbol_name(struct symbol_context *sc,
-	uint64_t addr, uint64_t len, const char *name, int type, int n_args)
-{
-	struct symbol *s;
-
-	if (sc->sorted_array) {
-		fprintf(stderr, "add_symbol_name(): Internal error: the "
-		    "symbol array is already sorted\n");
-		exit(1);
-	}
-
-	if (name == NULL) {
-		fprintf(stderr, "add_symbol_name(): name = NULL\n");
-		exit(1);
-	}
-
-	if (addr == 0 && strcmp(name, "_DYNAMIC_LINK") == 0)
-		return;
-
-	if (name[0] == '\0')
-		return;
-
-	/*  TODO: Maybe this should be optional?  */
-	if (name[0] == '.' || name[0] == '$')
-		return;
-
-	/*  Quick test-hack:  */
-	if (n_args < 0) {
-		if (strcmp(name, "strlen") == 0)
-			n_args = 1;
-		if (strcmp(name, "strcmp") == 0)
-			n_args = 2;
-		if (strcmp(name, "strcpy") == 0)
-			n_args = 2;
-		if (strcmp(name, "strncpy") == 0)
-			n_args = 3;
-		if (strcmp(name, "strlcpy") == 0)
-			n_args = 3;
-		if (strcmp(name, "strlcat") == 0)
-			n_args = 3;
-		if (strcmp(name, "strncmp") == 0)
-			n_args = 3;
-		if (strcmp(name, "memset") == 0)
-			n_args = 3;
-		if (strcmp(name, "memcpy") == 0)
-			n_args = 3;
-		if (strcmp(name, "bzero") == 0)
-			n_args = 2;
-		if (strcmp(name, "bcopy") == 0)
-			n_args = 3;
-	}
-
-	if ((addr >> 32) == 0 && (addr & 0x80000000ULL))
-		addr |= 0xffffffff00000000ULL;
-
-	CHECK_ALLOCATION(s = (struct symbol *) malloc(sizeof(struct symbol)));
-	memset(s, 0, sizeof(struct symbol));
-
-	s->name = symbol_demangle_cplusplus(name);
-
-	if (s->name == NULL)
-		CHECK_ALLOCATION(s->name = strdup(name));
-
-	s->addr   = addr;
-	s->len    = len;
-	s->type   = type;
-	s->n_args = n_args;
-
-	sc->n_symbols ++;
-
-	/*  Add first in list:  */
-	s->next = sc->first_symbol;
-	sc->first_symbol = s;
-}
-
-
-/*
- *  symbol_readfile():
- *
- *  Read 'nm -S' style symbols from a file.
- *
- *  TODO: This function is an ugly hack, and should be replaced
- *  with something that reads symbols directly from the executable
- *  images.
- */
-void symbol_readfile(struct symbol_context *sc, char *fname)
-{
-	FILE *f;
-	char b1[80]; uint64_t addr;
-	char b2[80]; uint64_t len;
-	char b3[80]; int type;
-	char b4[80];
-	int cur_n_symbols = sc->n_symbols;
-
-	f = fopen(fname, "r");
-	if (f == NULL) {
-		perror(fname);
-		exit(1);
-	}
-
-	while (!feof(f)) {
-		memset(b1, 0, sizeof(b1));
-		memset(b2, 0, sizeof(b2));
-		memset(b3, 0, sizeof(b3));
-		memset(b4, 0, sizeof(b4));
-		if (fscanf(f, "%s %s\n", b1,b2) != 2)
-			fprintf(stderr, "warning: symbol file parse error\n");
-		if (strlen(b2) < 2 && !(b2[0]>='0' && b2[0]<='9')) {
-			strlcpy(b3, b2, sizeof(b3));
-			strlcpy(b2, "0", sizeof(b2));
-			if (fscanf(f, "%s\n", b4) != 1)
-				fprintf(stderr, "warning: symbol file parse error\n");
-		} else {
-			if (fscanf(f, "%s %s\n", b3,b4) != 2)
-				fprintf(stderr, "warning: symbol file parse error\n");
-		}
-
-		/*  printf("b1='%s' b2='%s' b3='%s' b4='%s'\n",
-		    b1,b2,b3,b4);  */
-		addr = strtoull(b1, NULL, 16);
-		len  = strtoull(b2, NULL, 16);
-		type = b3[0];
-		/*  printf("addr=%016" PRIx64" len=%016" PRIx64" type=%i\n",
-		    addr, len, type);  */
-
-		if (type == 't' || type == 'r' || type == 'g')
-			continue;
-
-		add_symbol_name(sc, addr, len, b4, type, -1);
-	}
-
-	fclose(f);
-
-	debug("%i symbols\n", sc->n_symbols - cur_n_symbols);
-}
-
-
-/*
- *  sym_addr_compare():
- *
- *  Helper function for sorting symbols according to their address.
- */
-int sym_addr_compare(const void *a, const void *b)
-{
-	struct symbol *p1 = (struct symbol *) a;
-	struct symbol *p2 = (struct symbol *) b;
-
-	if (p1->addr < p2->addr)
-		return -1;
-	if (p1->addr > p2->addr)
-		return 1;
-
-	return 0;
-}
-
-
-/*
- *  symbol_recalc_sizes():
- *
- *  Recalculate sizes of symbols that have size = 0, by creating an array
- *  containing all symbols, qsort()-ing that array according to address, and
- *  recalculating the size fields if necessary.
- */
-void symbol_recalc_sizes(struct symbol_context *sc)
-{
-	struct symbol *tmp_array;
-	struct symbol *last_ptr;
-	struct symbol *tmp_ptr;
-	int i;
-
-	CHECK_ALLOCATION(tmp_array = (struct symbol *) malloc(sizeof (struct symbol) *
-	    sc->n_symbols));
-
-	/*  Copy first_symbol --> tmp_array, and remove the old
-		first_symbol at the same time:  */
-	tmp_ptr = sc->first_symbol;
-	i = 0;
-	while (tmp_ptr != NULL) {
-		tmp_array[i] = *tmp_ptr;
-		last_ptr = tmp_ptr;
-		tmp_ptr = tmp_ptr->next;
-		free(last_ptr);
-		i++;
-	}
-
-	qsort(tmp_array, sc->n_symbols, sizeof(struct symbol),
-	    sym_addr_compare);
-	sc->sorted_array = 1;
-
-	/*  Recreate the first_symbol chain:  */
-	sc->first_symbol = NULL;
-	for (i=0; i<sc->n_symbols; i++) {
-		/*  Recalculate size, if 0:  */
-		if (tmp_array[i].len == 0) {
-			uint64_t len;
-			if (i != sc->n_symbols-1)
-				len = tmp_array[i+1].addr
-				    - tmp_array[i].addr;
-			else
-				len = 1;
-
-			tmp_array[i].len = len;
-		}
-
-		tmp_array[i].next = &tmp_array[i+1];
-	}
-
-	sc->first_symbol = tmp_array;
-}
-
-
-/*
- *  symbol_init():
- *
- *  Initialize the symbol hashtables.
- */
-void symbol_init(struct symbol_context *sc)
-{
-	sc->first_symbol = NULL;
-	sc->sorted_array = 0;
-	sc->n_symbols = 0;
-}
-
diff -Nru gxemul-0.6.2/src/symbol/symbol_demangle.c gxemul-0.7.0+dfsg/src/symbol/symbol_demangle.c
--- gxemul-0.6.2/src/symbol/symbol_demangle.c	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/symbol/symbol_demangle.c	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,292 @@
+/*
+ *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright  
+ *     notice, this list of conditions and the following disclaimer in the 
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
+ *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ *  SUCH DAMAGE.
+ *
+ *
+ *  C++ symbol name demangling.
+ *
+ *  For obvious performance reasons, the external c++filt utility cannot be
+ *  used. Also, the host's version of this utility might be incompatible with
+ *  the binary being emulated.
+ *
+ *  TODO: Constructors, destructors, and lots of other stuff. See
+ *  http://www.codesourcery.com/cxx-abi/abi.html#mangling for details.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+
+#include "symbol.h"
+
+
+#define	MAXLEN		1000
+
+
+static void add_string(char *p, size_t *curlenp, const char *to_add)
+{
+	size_t curlen = *curlenp;
+	while (curlen < MAXLEN && *to_add)
+		p[curlen++] = *to_add++;
+	*curlenp = curlen;
+}
+
+
+/*
+ *  symbol_demangle_cplusplus_nested():
+ *
+ *  Try to demangle a nested cplusplus name. name points to the first character
+ *  after "_ZN".
+ */
+static char *symbol_demangle_cplusplus_nested(const char *name)
+{
+	char *result;
+	size_t result_len = 0, len;
+	int first = 1, type_added = 0, pointercounter, reference;
+
+	CHECK_ALLOCATION(result = (char *) malloc(MAXLEN + 1));
+	result[0] = '\0';
+
+	while (name[0] && name[0] != 'E' && result_len < MAXLEN) {
+		/*  Read length of the next part:  */
+		len = 0;
+		if (*name == '0') {
+			name ++;
+		} else {
+			while (isdigit((int)*name)) {
+				len *= 10;
+				len += (*name - '0');
+				name ++;
+			}
+		}
+
+		/*  Add ::  */
+		if (!first)
+			add_string(result, &result_len, "::");
+
+		/*  Read the part itself:  */
+		while (len-- >= 1 && result_len < MAXLEN)
+			result[result_len ++] = *name++;
+
+		first = 0;
+	}
+
+	if (name[0] != 'E')
+		goto fail;
+
+	name ++;
+
+	if (*name)
+		add_string(result, &result_len, "{");
+
+	/*  Type:  */
+	pointercounter = reference = 0;
+	while (*name) {
+		int argument_done = 0;
+		char t = *name++;
+		switch (t) {
+		case 'c':
+			add_string(result, &result_len, "char");
+			argument_done = 1;
+			break;
+		case 'a':
+			add_string(result, &result_len, "signed char");
+			argument_done = 1;
+			break;
+		case 'h':
+			add_string(result, &result_len, "unsigned char");
+			argument_done = 1;
+			break;
+		case 'i':
+			add_string(result, &result_len, "int");
+			argument_done = 1;
+			break;
+		case 'j':
+			add_string(result, &result_len, "unsigned int");
+			argument_done = 1;
+			break;
+		case 'w':
+			add_string(result, &result_len, "wchar_t");
+			argument_done = 1;
+			break;
+		case 'b':
+			add_string(result, &result_len, "bool");
+			argument_done = 1;
+			break;
+		case 's':
+			add_string(result, &result_len, "short");
+			argument_done = 1;
+			break;
+		case 't':
+			add_string(result, &result_len, "unsigned short");
+			argument_done = 1;
+			break;
+		case 'l':
+			add_string(result, &result_len, "long");
+			argument_done = 1;
+			break;
+		case 'm':
+			add_string(result, &result_len, "unsigned long");
+			argument_done = 1;
+			break;
+		case 'x':
+			add_string(result, &result_len, "long long");
+			argument_done = 1;
+			break;
+		case 'y':
+			add_string(result, &result_len, "unsigned long long");
+			argument_done = 1;
+			break;
+		case 'n':
+			add_string(result, &result_len, "__int128");
+			argument_done = 1;
+			break;
+		case 'o':
+			add_string(result, &result_len, "unsigned __int128");
+			argument_done = 1;
+			break;
+		case 'f':
+			add_string(result, &result_len, "float");
+			argument_done = 1;
+			break;
+		case 'd':
+			add_string(result, &result_len, "double");
+			argument_done = 1;
+			break;
+		case 'e':
+			add_string(result, &result_len, "__float80");
+			argument_done = 1;
+			break;
+		case 'g':
+			add_string(result, &result_len, "__float128");
+			argument_done = 1;
+			break;
+		case 'z':
+			add_string(result, &result_len, "...");
+			argument_done = 1;
+			break;
+		case 'P':
+			pointercounter ++;
+			break;
+		case 'R':
+			reference ++;
+			break;
+		case 'v':	/*  void  */
+			break;
+		default:/*  Unknown  */
+			goto fail;
+		}
+		if (argument_done) {
+			while (pointercounter-- > 0)
+				add_string(result, &result_len, "*");
+			while (reference-- > 0)
+				add_string(result, &result_len, "&");
+			if (*name)
+				add_string(result, &result_len, ",");
+		}
+		type_added = 1;
+	}
+
+	if (type_added)
+		add_string(result, &result_len, "}");
+
+	if (result_len == MAXLEN)
+		goto fail;
+
+	result[result_len] = '\0';
+
+	return result;
+
+fail:
+	free(result);
+	return NULL;
+}
+
+
+/*
+ *  symbol_demangle_cplusplus():
+ *
+ *  Try to demangle name. If name was not a valid/known C++ symbol, then NULL
+ *  is returned. Otherwise, a newly allocated string is returned, containing
+ *  the demangled name.
+ */
+char *symbol_demangle_cplusplus(const char *name)
+{
+	/*  Only support _Z-style mangled names, for now:  */
+	if (strlen(name) < 2 || name[0] != '_' || name[1] != 'Z')
+		return NULL;
+
+	name += 2;
+
+	switch (name[0]) {
+	case 'N':
+		return symbol_demangle_cplusplus_nested(name + 1);
+		break;
+	}
+
+	return NULL;
+}
+
+
+
+#ifdef TEST
+
+void test(char *mangled, char *result)
+{
+	char *p = symbol_demangle_cplusplus(mangled);
+	if (p == NULL) {
+		if (result == NULL) {
+			return;
+		} else {
+			printf("FAILURE for %s!\n", mangled);
+			exit(1);
+		}
+	}
+	if (strcmp(p, result) == 0)
+		return;
+	printf("FAILURE for %s! (result = %s)\n", mangled, p);
+	exit(1);
+}
+
+int main(int argc, char *argv[])
+{
+	test("monkey", NULL);
+	test("_monkey", NULL);
+	test("_zmonkey", NULL);
+	test("_Zmonkey", NULL);
+	test("_ZQ5abcde", NULL);
+	test("_ZN3abc5defghE", "abc::defgh");
+	test("_ZN05defghEv", "::defgh{}");
+	test("_ZN5defghEv", "defgh{}");
+	test("_ZN3abc5defghEv", "abc::defgh{}");
+	test("_ZN3abc5defghEc", "abc::defgh{char}");
+	test("_ZN1a2bcEjij", "a::bc{unsigned int,int,unsigned int}");
+	printf("OK\n");
+	return 0;
+}
+
+#endif
+
diff -Nru gxemul-0.6.2/src/symbol/symbol_demangle.cc gxemul-0.7.0+dfsg/src/symbol/symbol_demangle.cc
--- gxemul-0.6.2/src/symbol/symbol_demangle.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/symbol/symbol_demangle.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,292 +0,0 @@
-/*
- *  Copyright (C) 2006-2009  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- *
- *
- *  C++ symbol name demangling.
- *
- *  For obvious performance reasons, the external c++filt utility cannot be
- *  used. Also, the host's version of this utility might be incompatible with
- *  the binary being emulated.
- *
- *  TODO: Constructors, destructors, and lots of other stuff. See
- *  http://www.codesourcery.com/cxx-abi/abi.html#mangling for details.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <ctype.h>
-
-#include "symbol.h"
-
-
-#define	MAXLEN		1000
-
-
-static void add_string(char *p, size_t *curlenp, const char *to_add)
-{
-	size_t curlen = *curlenp;
-	while (curlen < MAXLEN && *to_add)
-		p[curlen++] = *to_add++;
-	*curlenp = curlen;
-}
-
-
-/*
- *  symbol_demangle_cplusplus_nested():
- *
- *  Try to demangle a nested cplusplus name. name points to the first character
- *  after "_ZN".
- */
-static char *symbol_demangle_cplusplus_nested(const char *name)
-{
-	char *result;
-	size_t result_len = 0, len;
-	int first = 1, type_added = 0, pointercounter, reference;
-
-	CHECK_ALLOCATION(result = (char *) malloc(MAXLEN + 1));
-	result[0] = '\0';
-
-	while (name[0] && name[0] != 'E' && result_len < MAXLEN) {
-		/*  Read length of the next part:  */
-		len = 0;
-		if (*name == '0') {
-			name ++;
-		} else {
-			while (isdigit((int)*name)) {
-				len *= 10;
-				len += (*name - '0');
-				name ++;
-			}
-		}
-
-		/*  Add ::  */
-		if (!first)
-			add_string(result, &result_len, "::");
-
-		/*  Read the part itself:  */
-		while (len-- >= 1 && result_len < MAXLEN)
-			result[result_len ++] = *name++;
-
-		first = 0;
-	}
-
-	if (name[0] != 'E')
-		goto fail;
-
-	name ++;
-
-	if (*name)
-		add_string(result, &result_len, "{");
-
-	/*  Type:  */
-	pointercounter = reference = 0;
-	while (*name) {
-		int argument_done = 0;
-		char t = *name++;
-		switch (t) {
-		case 'c':
-			add_string(result, &result_len, "char");
-			argument_done = 1;
-			break;
-		case 'a':
-			add_string(result, &result_len, "signed char");
-			argument_done = 1;
-			break;
-		case 'h':
-			add_string(result, &result_len, "unsigned char");
-			argument_done = 1;
-			break;
-		case 'i':
-			add_string(result, &result_len, "int");
-			argument_done = 1;
-			break;
-		case 'j':
-			add_string(result, &result_len, "unsigned int");
-			argument_done = 1;
-			break;
-		case 'w':
-			add_string(result, &result_len, "wchar_t");
-			argument_done = 1;
-			break;
-		case 'b':
-			add_string(result, &result_len, "bool");
-			argument_done = 1;
-			break;
-		case 's':
-			add_string(result, &result_len, "short");
-			argument_done = 1;
-			break;
-		case 't':
-			add_string(result, &result_len, "unsigned short");
-			argument_done = 1;
-			break;
-		case 'l':
-			add_string(result, &result_len, "long");
-			argument_done = 1;
-			break;
-		case 'm':
-			add_string(result, &result_len, "unsigned long");
-			argument_done = 1;
-			break;
-		case 'x':
-			add_string(result, &result_len, "long long");
-			argument_done = 1;
-			break;
-		case 'y':
-			add_string(result, &result_len, "unsigned long long");
-			argument_done = 1;
-			break;
-		case 'n':
-			add_string(result, &result_len, "__int128");
-			argument_done = 1;
-			break;
-		case 'o':
-			add_string(result, &result_len, "unsigned __int128");
-			argument_done = 1;
-			break;
-		case 'f':
-			add_string(result, &result_len, "float");
-			argument_done = 1;
-			break;
-		case 'd':
-			add_string(result, &result_len, "double");
-			argument_done = 1;
-			break;
-		case 'e':
-			add_string(result, &result_len, "__float80");
-			argument_done = 1;
-			break;
-		case 'g':
-			add_string(result, &result_len, "__float128");
-			argument_done = 1;
-			break;
-		case 'z':
-			add_string(result, &result_len, "...");
-			argument_done = 1;
-			break;
-		case 'P':
-			pointercounter ++;
-			break;
-		case 'R':
-			reference ++;
-			break;
-		case 'v':	/*  void  */
-			break;
-		default:/*  Unknown  */
-			goto fail;
-		}
-		if (argument_done) {
-			while (pointercounter-- > 0)
-				add_string(result, &result_len, "*");
-			while (reference-- > 0)
-				add_string(result, &result_len, "&");
-			if (*name)
-				add_string(result, &result_len, ",");
-		}
-		type_added = 1;
-	}
-
-	if (type_added)
-		add_string(result, &result_len, "}");
-
-	if (result_len == MAXLEN)
-		goto fail;
-
-	result[result_len] = '\0';
-
-	return result;
-
-fail:
-	free(result);
-	return NULL;
-}
-
-
-/*
- *  symbol_demangle_cplusplus():
- *
- *  Try to demangle name. If name was not a valid/known C++ symbol, then NULL
- *  is returned. Otherwise, a newly allocated string is returned, containing
- *  the demangled name.
- */
-char *symbol_demangle_cplusplus(const char *name)
-{
-	/*  Only support _Z-style mangled names, for now:  */
-	if (strlen(name) < 2 || name[0] != '_' || name[1] != 'Z')
-		return NULL;
-
-	name += 2;
-
-	switch (name[0]) {
-	case 'N':
-		return symbol_demangle_cplusplus_nested(name + 1);
-		break;
-	}
-
-	return NULL;
-}
-
-
-
-#ifdef TEST
-
-void test(char *mangled, char *result)
-{
-	char *p = symbol_demangle_cplusplus(mangled);
-	if (p == NULL) {
-		if (result == NULL) {
-			return;
-		} else {
-			printf("FAILURE for %s!\n", mangled);
-			exit(1);
-		}
-	}
-	if (strcmp(p, result) == 0)
-		return;
-	printf("FAILURE for %s! (result = %s)\n", mangled, p);
-	exit(1);
-}
-
-int main(int argc, char *argv[])
-{
-	test("monkey", NULL);
-	test("_monkey", NULL);
-	test("_zmonkey", NULL);
-	test("_Zmonkey", NULL);
-	test("_ZQ5abcde", NULL);
-	test("_ZN3abc5defghE", "abc::defgh");
-	test("_ZN05defghEv", "::defgh{}");
-	test("_ZN5defghEv", "defgh{}");
-	test("_ZN3abc5defghEv", "abc::defgh{}");
-	test("_ZN3abc5defghEc", "abc::defgh{char}");
-	test("_ZN1a2bcEjij", "a::bc{unsigned int,int,unsigned int}");
-	printf("OK\n");
-	return 0;
-}
-
-#endif
-
diff -Nru gxemul-0.6.2/src/ui/console/ConsoleUI.cc gxemul-0.7.0+dfsg/src/ui/console/ConsoleUI.cc
--- gxemul-0.6.2/src/ui/console/ConsoleUI.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/ui/console/ConsoleUI.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,318 +0,0 @@
-/*
- *  Copyright (C) 2007-2019  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include <signal.h>
-#include <unistd.h>
-#include <iostream>
-
-#include "misc.h"
-#include "ConsoleUI.h"
-#include "GXemul.h"
-
-
-ConsoleUI::ConsoleUI(GXemul *gxemul)
-	: UI(gxemul)
-	, m_consoleIsInitialized(false)
-{
-}
-
-
-ConsoleUI::~ConsoleUI()
-{
-	// Restore the terminal mode:
-	if (m_consoleIsInitialized)
-		tcsetattr(STDIN_FILENO, TCSANOW, &m_oldTermios);
-}
-
-
-// Note: Use of global GXemul pointer!
-static GXemul* g_GXemul;
-static struct termios g_curTermios;
-
-static void ReshowCurrentCommandBuffer()
-{
-	if (g_GXemul->GetRunState() == GXemul::Paused) {
-		// Reshow the prompt and the current command line:
-		g_GXemul->GetCommandInterpreter().ReshowCurrentCommandBuffer();
-		std::cout.flush();
-	}
-}
-
-/**
- * \brief CTRL-C handler which sets the run state to Paused.
- */
-extern "C" void ConsoleUI_SIGINT_Handler(int n)
-{
-	if (g_GXemul->IsInterrupting())
-		std::cout << "^C (already attempting to interrupt, please wait)\n";
-	else
-		std::cout << "^C\n";
-
-	g_GXemul->Interrupt();
-
-	g_GXemul->GetCommandInterpreter().ClearCurrentCommandBuffer();
-	ReshowCurrentCommandBuffer();
-
-	signal(SIGINT, ConsoleUI_SIGINT_Handler);
-}
-
-/**
- * \brief Restore terminal settings after a CTRL-Z.
- *
- * If the user presses CTRL-Z (to stop the emulator process) and then
- * continues, the termios settings might have been invalidated. This
- * function restores them.
- */
-extern "C" void ConsoleUI_SIGCONT_Handler(int n)
-{
-	tcsetattr(STDIN_FILENO, TCSANOW, &g_curTermios);
-	ReshowCurrentCommandBuffer();
-	signal(SIGCONT, ConsoleUI_SIGCONT_Handler);
-}
-
-
-void ConsoleUI::Initialize()
-{
-	if (m_consoleIsInitialized)
-		return;
-
-	tcgetattr(STDIN_FILENO, &m_oldTermios);
-	m_currentTermios = m_oldTermios;
-
-	// Set the terminal mode:
-	m_currentTermios.c_lflag &= ~ICANON;
-	m_currentTermios.c_cc[VTIME] = 0;
-	m_currentTermios.c_cc[VMIN] = 1;
-	m_currentTermios.c_lflag &= ~ECHO;
-
-	tcsetattr(STDIN_FILENO, TCSANOW, &m_currentTermios);
-
-	// Signal handlers for CTRL-C and CTRL-Z.
-	// Note: Using a global GXemul instance pointer!
-	g_GXemul = m_gxemul;
-	g_curTermios = m_currentTermios;
-	signal(SIGINT, ConsoleUI_SIGINT_Handler);
-	signal(SIGCONT, ConsoleUI_SIGCONT_Handler);
-
-	m_consoleIsInitialized = true;
-}
-
-
-void ConsoleUI::UpdateUI()
-{
-	// Empty.
-}
-
-
-void ConsoleUI::ShowStartupBanner()
-{
-	std::cout << GXemul::Version() << "\n";
-}
-
-
-static vector<string> SplitIntoRows(const string &msg, bool addEmptyLines)
-{
-	// This is slow and hackish, but works.
-	vector<string> result;
-	string line;
-
-	for (size_t i=0, n=msg.length(); i<n; i++) {
-		stringchar ch = msg[i];
-		if (ch == '\n') {
-			if (line.length() > 0 || addEmptyLines)
-				result.push_back(line);
-			line = "";
-		} else {
-			line += ch;
-		}
-	}
-
-	if (line.length() > 0)
-		result.push_back(line);
-
-	return result;
-}
-
-
-void ConsoleUI::ShowDebugMessage(const string& msg)
-{
-	vector<string> lines = SplitIntoRows(msg, true);
-
-	for (size_t i=0; i<lines.size(); ++i) {
-		if (m_gxemul->GetRunState() == GXemul::Running) {
-			if (isatty(fileno(stdout)))
-				std::cout << "\e[1m" << m_indentationMsg << lines[i] << "\e[0m\n";
-			else
-				std::cout << "[ " << m_indentationMsg << lines[i] << " ]\n";
-		} else {
-			std::cout << m_indentationMsg << lines[i] << "\n";
-		}
-		
-		// Replace indentation string with spaces after first
-		// line of output:
-		for (size_t j=m_indentationMsg.length(); j>0; --j)
-			m_indentationMsg[j-1] = ' ';
-	}
-
-	std::cout.flush();
-}
-
-
-void ConsoleUI::ShowDebugMessage(Component* component, const string& msg)
-{
-	if (m_gxemul->GetQuietMode())
-		return;
-
-	stringstream ss;
-	string componentName = component->GenerateShortestPossiblePath();
-
-	vector<string> lines = SplitIntoRows(msg, false);
-
-	// cpu0: blahlonger
-	//       blahshort
-	size_t i;
-	string spaces = "";
-	for (i=0; i<componentName.length() + 2; i++)
-		spaces += " ";
-	
-	ss << componentName << ": " << lines[0] << "\n";
-
-	for (i=1; i<lines.size(); ++i)
-		ss << spaces << lines[i] << "\n";
-
-	ShowDebugMessage(ss.str());
-}
-
-
-void ConsoleUI::ShowCommandMessage(const string& command)
-{
-	// Not for ConsoleUI; commands entered by the user are
-	// displayed anyway (echoing characters while the command
-	// was entered).
-}
-
-
-void ConsoleUI::FatalError(const string& msg)
-{
-	std::cerr << msg;
-	std::cerr.flush();
-}
-
-
-void ConsoleUI::RedisplayInputLine(const string& inputline,
-    size_t cursorPosition)
-{
-	std::cout << "\rGXemul> " << inputline << " \rGXemul> ";
-
-	for (size_t pos = 0; pos < cursorPosition; pos++)
-		std::cout << (string() + inputline[pos]);
-
-	std::cout.flush();
-}
-
-
-/**
- * \brief Read a key from stdin, blocking.
- *
- * @return The key read from stdin.
- */
-static stringchar ReadKey()
-{
-	return std::cin.get();
-}
-
-
-void ConsoleUI::ReadAndExecuteCommand()
-{
-	// Initial dummy addkey, to show the input line with the prompt, etc.:
-	m_gxemul->GetCommandInterpreter().AddKey('\0');
-
-	while (!m_gxemul->GetCommandInterpreter().AddKey(ReadKey()))
-		;
-}
-
-
-void ConsoleUI::InputLineDone()
-{
-	std::cout << "\n";
-	std::cout.flush();
-}
-
-
-void ConsoleUI::Shutdown() 
-{
-}
-
-
-int ConsoleUI::MainLoop()
-{
-	GXemul::RunState oldRunState = m_gxemul->GetRunState();
-
-	while (m_gxemul->GetRunState() != GXemul::Quitting) {
-		GXemul::RunState runState = m_gxemul->GetRunState();
-
-		switch (runState) {
-
-		case GXemul::SingleStepping:
-		case GXemul::Running:
-			// Switching from Paused state to running? Then
-			// we need to:
-			// 1) flush old cached state
-			// 2) perform pre-run checks.
-			if (oldRunState == GXemul::Paused) {
-				m_gxemul->GetRootComponent()->FlushCachedState();
-
-				if (!m_gxemul->GetRootComponent()->PreRunCheck(m_gxemul)) {
-					FatalError("Pre-run check failed.\n");
-					m_gxemul->SetRunState(GXemul::Paused);
-					runState = m_gxemul->GetRunState();
-					break;
-				}
-			}
-
-			m_gxemul->Execute();
-			break;
-
-		case GXemul::Quitting:
-			break;
-
-		case GXemul::Paused:
-			// When issuing interactive commands, "anything" can
-			// happen to the component tree, and thus any cached
-			// state quickly becomes untrustworthy. Let's flush it.
-			m_gxemul->GetRootComponent()->FlushCachedState();
-
-			ReadAndExecuteCommand();
-			break;
-		}
-
-		oldRunState = runState;
-	}
-
-	return 0;
-}
-
diff -Nru gxemul-0.6.2/src/ui/console/Makefile.skel gxemul-0.7.0+dfsg/src/ui/console/Makefile.skel
--- gxemul-0.6.2/src/ui/console/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/ui/console/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,19 +0,0 @@
-#
-#  Makefile for GXemul src/ui/console
-#
-
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(CPEDANTIC) $(INCLUDE2)
-LIBS=$(OTHERLIBS)
-
-OBJS=ConsoleUI.o
-
-all: $(OBJS)
-
-$(OBJS): Makefile
-
-clean:
-	rm -f $(OBJS) *core
-
-clean_all: clean
-	rm -f Makefile
-
diff -Nru gxemul-0.6.2/src/ui/Makefile.skel gxemul-0.7.0+dfsg/src/ui/Makefile.skel
--- gxemul-0.6.2/src/ui/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/ui/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,24 +0,0 @@
-#
-#  Makefile for GXemul src/ui
-#
-
-all: do_console do_nullui
-
-$(OBJS): Makefile
-
-do_console:
-	cd console; $(MAKE)
-
-do_nullui:
-	cd nullui; $(MAKE)
-
-clean:
-	cd console; $(MAKE) clean
-	cd nullui; $(MAKE) clean
-	rm -f $(OBJS) *core
-
-clean_all: clean
-	cd console; $(MAKE) clean_all
-	cd nullui; $(MAKE) clean_all
-	rm -f Makefile
-
diff -Nru gxemul-0.6.2/src/ui/nullui/Makefile.skel gxemul-0.7.0+dfsg/src/ui/nullui/Makefile.skel
--- gxemul-0.6.2/src/ui/nullui/Makefile.skel	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/ui/nullui/Makefile.skel	1970-01-01 00:00:00.000000000 +0000
@@ -1,19 +0,0 @@
-#
-#  Makefile for GXemul src/ui/nullui
-#
-
-CXXFLAGS=$(CWARNINGS) $(COPTIM) $(CPEDANTIC) $(INCLUDE2)
-LIBS=$(OTHERLIBS)
-
-OBJS=NullUI.o
-
-all: $(OBJS)
-
-$(OBJS): Makefile
-
-clean:
-	rm -f $(OBJS) *core
-
-clean_all: clean
-	rm -f Makefile
-
diff -Nru gxemul-0.6.2/src/ui/nullui/NullUI.cc gxemul-0.7.0+dfsg/src/ui/nullui/NullUI.cc
--- gxemul-0.6.2/src/ui/nullui/NullUI.cc	2019-06-22 18:23:27.000000000 +0000
+++ gxemul-0.7.0+dfsg/src/ui/nullui/NullUI.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,97 +0,0 @@
-/*
- *  Copyright (C) 2008-2010  Anders Gavare.  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  1. Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *  2. Redistributions in binary form must reproduce the above copyright  
- *     notice, this list of conditions and the following disclaimer in the 
- *     documentation and/or other materials provided with the distribution.
- *  3. The name of the author may not be used to endorse or promote products
- *     derived from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
- *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGE.
- */
-
-#include "NullUI.h"
-#include "GXemul.h"
-
-
-NullUI::NullUI(GXemul *gxemul)
-	: UI(gxemul)
-{
-}
-
-
-NullUI::~NullUI()
-{
-}
-
-
-void NullUI::Initialize()
-{
-}
-
-
-void NullUI::ShowStartupBanner()
-{
-}
-
-
-void NullUI::UpdateUI()
-{
-}
-
-
-void NullUI::ShowDebugMessage(const string& msg)
-{
-}
-
-
-void NullUI::ShowDebugMessage(Component* component, const string& msg)
-{
-}
-
-
-void NullUI::ShowCommandMessage(const string& command)
-{
-}
-
-
-void NullUI::FatalError(const string& msg)
-{
-}
-
-
-void NullUI::RedisplayInputLine(const string& inputline, size_t cursorPosition)
-{
-}
-
-
-void NullUI::InputLineDone()
-{
-}
-
-
-void NullUI::Shutdown()
-{
-}
-
-
-int NullUI::MainLoop()
-{
-	return 0;
-}
-
Binary files /tmp/tmpaarp4e17/pWfV7dXnD4/gxemul-0.6.2/test/FileLoader_A.OUT_M88K and /tmp/tmpaarp4e17/9kW3MclFqY/gxemul-0.7.0+dfsg/test/FileLoader_A.OUT_M88K differ
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Binary files /tmp/tmpaarp4e17/pWfV7dXnD4/gxemul-0.6.2/test/FileLoader_ELF_MIPS and /tmp/tmpaarp4e17/9kW3MclFqY/gxemul-0.7.0+dfsg/test/FileLoader_ELF_MIPS differ
Binary files /tmp/tmpaarp4e17/pWfV7dXnD4/gxemul-0.6.2/test/FileLoader_ELF_MIPS16 and /tmp/tmpaarp4e17/9kW3MclFqY/gxemul-0.7.0+dfsg/test/FileLoader_ELF_MIPS16 differ
Binary files /tmp/tmpaarp4e17/pWfV7dXnD4/gxemul-0.6.2/test/FileLoader_ELF_RISCV64 and /tmp/tmpaarp4e17/9kW3MclFqY/gxemul-0.7.0+dfsg/test/FileLoader_ELF_RISCV64 differ
Binary files /tmp/tmpaarp4e17/pWfV7dXnD4/gxemul-0.6.2/test/FileLoader_ELF_SH5 and /tmp/tmpaarp4e17/9kW3MclFqY/gxemul-0.7.0+dfsg/test/FileLoader_ELF_SH5 differ
diff -Nru gxemul-0.6.2/test/FileLoader_NonsenseFile gxemul-0.7.0+dfsg/test/FileLoader_NonsenseFile
--- gxemul-0.6.2/test/FileLoader_NonsenseFile	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/test/FileLoader_NonsenseFile	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-This is a nonsense file.
diff -Nru gxemul-0.6.2/test/floatingpoint/Makefile gxemul-0.7.0+dfsg/test/floatingpoint/Makefile
--- gxemul-0.6.2/test/floatingpoint/Makefile	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/test/floatingpoint/Makefile	2021-11-27 09:42:23.000000000 +0000
@@ -1,15 +1,61 @@
 CFLAGS=-DHOSTNATIVE -I../../src/include/testmachine
 
 all:
-	@echo Read the README file for instructions on how to build
-	@echo the floatingpoint test program for various targets.
+	@echo Read the Makefile to see which targets are available.
 	@echo To build for the host, type \"make native\"
 
-native: fptest.o fpconst.o
+fptest: fptest.o fpconst.o
 	$(CC) fptest.o fpconst.o -o fptest
+
+native: clean fptest
 	./fptest > fptest_hostnative.output
 	cat fptest_hostnative.output
 
 clean:
 	rm -f *.o fptest fptest.output *core
 
+
+##############################################################################
+
+
+arm: clean
+	arm-unknown-elf-gcc -I../../src/include/testmachine -g fptest.c -O2 -c -mhard-float
+	arm-unknown-elf-gcc -I../../src/include/testmachine -g fpconst.c -O2 -c -mhard-float
+	arm-unknown-elf-ld -e f fptest.o fpconst.o -o fptest
+	file fptest
+	../../gxemul -qE testarm fptest > fptest_arm.output
+	diff fptest_hostnative.output fptest_arm.output
+
+mips32: clean
+	mips64-unknown-elf-gcc -DMIPS -I../../src/include/testmachine -g fptest.c -O0 -mips1 -mabi=32 -c -G 0
+	mips64-unknown-elf-gcc -DMIPS -I../../src/include/testmachine -g fpconst.c -O0 -mips1 -mabi=32 -c -G 0
+	mips64-unknown-elf-ld -Ttext 0x80030000 -e f fptest.o fpconst.o -o fptest
+	file fptest
+	../../gxemul -C 4Kc -qE testmips fptest > fptest_mips32.output
+	diff fptest_hostnative.output fptest_mips32.output
+
+mips64: clean
+	mips64-unknown-elf-gcc -DMIPS -I../../src/include/testmachine -g fptest.c -O0 -mips4 -mabi=64 -c -G 0
+	mips64-unknown-elf-gcc -DMIPS -I../../src/include/testmachine -g fpconst.c -O0 -mips4 -mabi=64 -c -G 0
+	mips64-unknown-elf-ld -Ttext 0xa800000000030000 -e f fptest.o fpconst.o -o fptest --oformat=elf64-bigmips
+	file fptest
+	../../gxemul -qE testmips fptest > fptest_mips64.output
+	diff fptest_hostnative.output fptest_mips64.output
+
+riscv: clean
+	riscv64-unknown-elf-gcc -I../../src/include/testmachine -O2 -g fptest.c -c
+	riscv64-unknown-elf-gcc -I../../src/include/testmachine -O2 -g fpconst.c -c
+	riscv64-unknown-elf-ld -e _f fptest.o fpconst.o -o fptest
+	file fptest
+	../../gxemul -qE testriscv fptest > fptest_riscv.output
+	diff fptest_hostnative.output fptest_riscv.output
+
+sh4: clean
+	sh4-unknown-elf-gcc -I../../src/include/testmachine -O2 -g fptest.c -c
+	sh4-unknown-elf-gcc -I../../src/include/testmachine -O2 -g fpconst.c -c
+	sh4-unknown-elf-ld -e _f fptest.o fpconst.o -o fptest
+	file fptest
+	../../gxemul -qE testsh fptest > fptest_sh4.output
+	diff fptest_hostnative.output fptest_sh4.output
+
+
diff -Nru gxemul-0.6.2/test/floatingpoint/README gxemul-0.7.0+dfsg/test/floatingpoint/README
--- gxemul-0.6.2/test/floatingpoint/README	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/test/floatingpoint/README	1970-01-01 00:00:00.000000000 +0000
@@ -1,41 +0,0 @@
-ARM
----
-arm-unknown-elf-gcc -I../../src/include/testmachine -g fptest.c -O2 -c -mhard-float
-arm-unknown-elf-gcc -I../../src/include/testmachine -g fpconst.c -O2 -c -mhard-float
-arm-unknown-elf-ld -e f fptest.o fpconst.o -o fptest
-file fptest
-../../gxemul -E testarm fptest > fptest.output
-diff fptest_hostnative.output fptest.output
-
-
-
-MIPS (64-bit)
--------------
-mips64-unknown-elf-gcc -DMIPS -I../../src/include/testmachine -g fptest.c -O0 -mips4 -mabi=64 -c -G 0
-mips64-unknown-elf-gcc -DMIPS -I../../src/include/testmachine -g fpconst.c -O0 -mips4 -mabi=64 -c -G 0
-mips64-unknown-elf-ld -Ttext 0xa800000000030000 -e f fptest.o fpconst.o -o fptest --oformat=elf64-bigmips
-file fptest
-../../gxemul -qE oldtestmips fptest > fptest.output
-diff fptest_hostnative.output fptest.output
-
-
-MIPS (32-bit)
--------------
-mips64-unknown-elf-gcc -DMIPS -I../../src/include/testmachine -g fptest.c -O0 -mips1 -mabi=32 -c -G 0
-mips64-unknown-elf-gcc -DMIPS -I../../src/include/testmachine -g fpconst.c -O0 -mips1 -mabi=32 -c -G 0
-mips64-unknown-elf-ld -Ttext 0x80030000 -e f fptest.o fpconst.o -o fptest
-file fptest
-../../gxemul -C 4Kc -qE oldtestmips fptest > fptest.output
-diff fptest_hostnative.output fptest.output
-
-
-SH
---
-sh4-unknown-elf-gcc -I../../src/include/testmachine -O2 -g fptest.c -c
-sh4-unknown-elf-gcc -I../../src/include/testmachine -O2 -g fpconst.c -c
-sh4-unknown-elf-ld -e _f fptest.o fpconst.o -o fptest
-file fptest
-../../gxemul -E testsh fptest > fptest.output
-diff fptest_hostnative.output fptest.output
-// TODO: undefined reference to `__fpscr_values'
-
diff -Nru gxemul-0.6.2/test/test_netbsd8.1_hpcmips_install.expect gxemul-0.7.0+dfsg/test/test_netbsd8.1_hpcmips_install.expect
--- gxemul-0.6.2/test/test_netbsd8.1_hpcmips_install.expect	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/test/test_netbsd8.1_hpcmips_install.expect	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,66 @@
+#!/usr/local/bin/expect
+
+set timeout 4000
+spawn ./gxemul -e mobilepro770 -q -d nbsd8.1_hpcmips.img -d b:../../emul/mips/netbsd-hpcmips-8.1/NetBSD-8.1-hpcmips.iso ../../emul/mips/netbsd-hpcmips-8.1/netbsd.gz
+
+expect " in English"
+send "\r"
+expect "Install NetBSD to"
+send "\r"
+expect "b: Yes"
+send "b\r"
+expect "wd0"
+send "\r"
+expect "The number of cylinders"
+send "\r\r"
+expect "Use the entire disk"
+send "b\r"
+expect "Set sizes of NetBSD partitions"
+send "\r"
+expect "Accept partition sizes"
+send "x\r"
+expect "Partition sizes ok"
+send "\r"
+expect "Please enter a name for"
+send "\r"
+expect "b: Yes"
+send "b\r"
+expect "Hit enter to continue"
+send "\r"
+expect "a: Full installation"
+send "\r"
+expect "a: CD-ROM"
+send "\r"
+expect "cd0a"
+send "a\r"
+expect "device"
+send "cd0d\r"
+expect "x: Continue"
+send "x\r"
+expect "Hit enter to continue"
+send "\r"
+expect "Finished configuring"
+send "\r"
+expect "Hit enter to continue"
+send "\r"
+expect "Exit Install System"
+send "x\r"
+expect "#"
+send "mount /dev/wd0a /mnt\r"
+expect "#"
+send "echo 'console \"/usr/libexec/getty std.9600\" vt100 on secure' >> /mnt/etc/ttys\r"
+expect "#"
+send "sync\r"
+expect "#"
+send "sleep 2\r"
+expect "#"
+send "umount /mnt\r"
+expect "#"
+send "sync\r"
+expect "#"
+send "sleep 2\r"
+expect "#"
+send "halt -p\r"
+
+close
+
diff -Nru gxemul-0.6.2/test/test_netbsd8.1_hpcmips_install.sh gxemul-0.7.0+dfsg/test/test_netbsd8.1_hpcmips_install.sh
--- gxemul-0.6.2/test/test_netbsd8.1_hpcmips_install.sh	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/test/test_netbsd8.1_hpcmips_install.sh	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,26 @@
+#!/bin/sh
+#
+#  Regression test:
+#
+#  Automated full install of NetBSD/hpcmips, using serial console.
+#
+#
+#  1. Place the iso here:
+#
+#	../../emul/mips/netbsd-hpcmips-8.1/NetBSD-8.1-hpcmips.iso
+#
+#  2. Start the regression test with:
+#
+#	test/test_netbsd8.1_hpcmips_install.sh
+#
+
+rm -f nbsd8.1_hpcmips.img
+dd if=/dev/zero of=nbsd8.1_hpcmips.img bs=1024 count=1 seek=5000000
+
+time test/test_netbsd8.1_hpcmips_install.expect 2> /tmp/gxemul_result
+
+echo
+echo
+echo
+cat /tmp/gxemul_result
+
diff -Nru gxemul-0.6.2/test/test_openbsd_luna88k_bootup.expect gxemul-0.7.0+dfsg/test/test_openbsd_luna88k_bootup.expect
--- gxemul-0.6.2/test/test_openbsd_luna88k_bootup.expect	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/test/test_openbsd_luna88k_bootup.expect	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,14 @@
+#!/usr/local/bin/expect
+
+set timeout 4000
+spawn ./gxemul -e luna-88k -q -d R:liveimage-luna88k-raw-20201206.img boot
+
+set  send_slow  {1 .5}
+
+expect " starting in"
+send -s "\r"
+
+expect "login:"
+
+close
+
diff -Nru gxemul-0.6.2/test/test_openbsd_luna88k_bootup.sh gxemul-0.7.0+dfsg/test/test_openbsd_luna88k_bootup.sh
--- gxemul-0.6.2/test/test_openbsd_luna88k_bootup.sh	1970-01-01 00:00:00.000000000 +0000
+++ gxemul-0.7.0+dfsg/test/test_openbsd_luna88k_bootup.sh	2021-11-27 09:42:23.000000000 +0000
@@ -0,0 +1,30 @@
+#!/bin/sh
+#
+#  A small test to measure how long time it takes (real time) to boot
+#  OpenBSD/luna88k up to the login prompt.
+#
+#  Start with:
+#
+#	test/test_openbsd_luna88k_bootup.sh
+#
+#  after making sure that you have 'liveimage-luna88k-raw-20201206.img' and
+#  'boot' in the current directory.
+#
+#
+#  2021-04-22 baseline:
+#	71.10 seconds: ./configure gcc8 --debug
+#	36.70 seconds: ./configure (clang 10.0.1)
+#
+#  M88K_MAX_VPH_TLB_ENTRIES:
+#	 32	37.21 seconds
+#	 64	36.76 seconds
+#	128	36.70 seconds
+#	192	36.67 seconds
+
+
+time test/test_openbsd_luna88k_bootup.expect 2> /tmp/gxemul_result
+
+echo "-------------------------------------------------"
+echo
+cat /tmp/gxemul_result
+
diff -Nru gxemul-0.6.2/test/test_openbsd_mvme88k_install.expect gxemul-0.7.0+dfsg/test/test_openbsd_mvme88k_install.expect
--- gxemul-0.6.2/test/test_openbsd_mvme88k_install.expect	2019-06-22 18:23:30.000000000 +0000
+++ gxemul-0.7.0+dfsg/test/test_openbsd_mvme88k_install.expect	2021-11-27 09:42:23.000000000 +0000
@@ -1,7 +1,7 @@
 #!/usr/local/bin/expect
 
 set timeout 4000
-spawn ./gxemul -e mvme187old -q -d obsd_mvme88k.img -d b:../../emul/m88k/openbsd_mvme88k_4.5.iso -j 4.5/mvme88k/bsd.rd
+spawn ./gxemul -e mvme187 -q -d obsd_mvme88k.img -d b:../../emul/m88k/openbsd_mvme88k_4.5.iso -j 4.5/mvme88k/bsd.rd
 
 set  send_slow  {1 .5}