diff -Nru qemu-2.11+dfsg/debian/changelog qemu-2.11+dfsg/debian/changelog --- qemu-2.11+dfsg/debian/changelog 2018-05-16 18:14:20.000000000 +0000 +++ qemu-2.11+dfsg/debian/changelog 2018-05-22 13:34:52.000000000 +0000 @@ -1,3 +1,17 @@ +qemu (1:2.11+dfsg-1ubuntu10) cosmic; urgency=medium + + * SECURITY UPDATE: Speculative Store Bypass + - debian/patches/ubuntu/CVE-2018-3639/0001*.patch: define the 'ssbd' + CPUID feature bit in target/i386/cpu.*. + - debian/patches/ubuntu/CVE-2018-3639/0002*.patch: define the AMD + 'virt-ssbd' CPUID feature bit in target/i386/cpu.c. + - debian/patches/ubuntu/CVE-2018-3639/0003*.patch: define the Virt SSBD + MSR and handling of it in target/i386/cpu.h, target/i386/kvm.c, + target/i386/machine.c. + - CVE-2018-3639 + + -- Marc Deslauriers Tue, 22 May 2018 09:34:52 -0400 + qemu (1:2.11+dfsg-1ubuntu9) cosmic; urgency=medium * SECURITY UPDATE: out-of-bounds access during migration via ps2 diff -Nru qemu-2.11+dfsg/debian/patches/series qemu-2.11+dfsg/debian/patches/series --- qemu-2.11+dfsg/debian/patches/series 2018-05-16 18:14:02.000000000 +0000 +++ qemu-2.11+dfsg/debian/patches/series 2018-05-22 13:34:52.000000000 +0000 @@ -34,3 +34,6 @@ ubuntu/CVE-2017-16845.patch ubuntu/CVE-2018-7550.patch ubuntu/CVE-2018-7858.patch +ubuntu/CVE-2018-3639/0001-i386-define-the-ssbd-CPUID-feature-bit-CVE-2018-3639.patch +ubuntu/CVE-2018-3639/0002-i386-define-the-AMD-virt-ssbd-CPUID-feature-bit-CVE-.patch +ubuntu/CVE-2018-3639/0003-i386-Define-the-Virt-SSBD-MSR-and-handling-of-it-CVE.patch diff -Nru qemu-2.11+dfsg/debian/patches/ubuntu/CVE-2018-3639/0001-i386-define-the-ssbd-CPUID-feature-bit-CVE-2018-3639.patch qemu-2.11+dfsg/debian/patches/ubuntu/CVE-2018-3639/0001-i386-define-the-ssbd-CPUID-feature-bit-CVE-2018-3639.patch --- qemu-2.11+dfsg/debian/patches/ubuntu/CVE-2018-3639/0001-i386-define-the-ssbd-CPUID-feature-bit-CVE-2018-3639.patch 1970-01-01 00:00:00.000000000 +0000 +++ qemu-2.11+dfsg/debian/patches/ubuntu/CVE-2018-3639/0001-i386-define-the-ssbd-CPUID-feature-bit-CVE-2018-3639.patch 2018-05-18 18:06:15.000000000 +0000 @@ -0,0 +1,46 @@ +From bbc99c0cb5c674389876a11f6f1788c867bb4fea Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= +Date: Wed, 9 May 2018 09:06:29 +0100 +Subject: [PATCH v3 1/5] i386: define the 'ssbd' CPUID feature bit + (CVE-2018-3639) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +New microcode introduces the "Speculative Store Bypass Disable" +CPUID feature bit. This needs to be exposed to guest OS to allow +them to protect against CVE-2018-3639. + +Signed-off-by: Daniel P. Berrangé +Reviewed-by: Konrad Rzeszutek Wilk +Signed-off-by: Konrad Rzeszutek Wilk +--- + target/i386/cpu.c | 2 +- + target/i386/cpu.h | 1 + + 2 files changed, 2 insertions(+), 1 deletion(-) + +Index: qemu-2.11+dfsg/target/i386/cpu.c +=================================================================== +--- qemu-2.11+dfsg.orig/target/i386/cpu.c 2018-05-18 14:06:13.147016560 -0400 ++++ qemu-2.11+dfsg/target/i386/cpu.c 2018-05-18 14:06:13.143016565 -0400 +@@ -459,7 +459,7 @@ static FeatureWordInfo feature_word_info + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, "spec-ctrl", NULL, +- NULL, NULL, NULL, NULL, ++ NULL, NULL, NULL, "ssbd", + }, + .cpuid_eax = 7, + .cpuid_needs_ecx = true, .cpuid_ecx = 0, +Index: qemu-2.11+dfsg/target/i386/cpu.h +=================================================================== +--- qemu-2.11+dfsg.orig/target/i386/cpu.h 2018-05-18 14:06:13.147016560 -0400 ++++ qemu-2.11+dfsg/target/i386/cpu.h 2018-05-18 14:06:13.143016565 -0400 +@@ -650,6 +650,7 @@ typedef uint32_t FeatureWordArray[FEATUR + #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ + #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ + #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ ++#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ + + #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ + diff -Nru qemu-2.11+dfsg/debian/patches/ubuntu/CVE-2018-3639/0002-i386-define-the-AMD-virt-ssbd-CPUID-feature-bit-CVE-.patch qemu-2.11+dfsg/debian/patches/ubuntu/CVE-2018-3639/0002-i386-define-the-AMD-virt-ssbd-CPUID-feature-bit-CVE-.patch --- qemu-2.11+dfsg/debian/patches/ubuntu/CVE-2018-3639/0002-i386-define-the-AMD-virt-ssbd-CPUID-feature-bit-CVE-.patch 1970-01-01 00:00:00.000000000 +0000 +++ qemu-2.11+dfsg/debian/patches/ubuntu/CVE-2018-3639/0002-i386-define-the-AMD-virt-ssbd-CPUID-feature-bit-CVE-.patch 2018-05-18 18:06:24.000000000 +0000 @@ -0,0 +1,32 @@ +From 6cf7cfef30a220709a13b987fc9aca0bd3d63110 Mon Sep 17 00:00:00 2001 +From: Konrad Rzeszutek Wilk +Date: Wed, 16 May 2018 21:37:31 -0400 +Subject: [PATCH v3 2/5] i386: define the AMD 'virt-ssbd' CPUID feature bit + (CVE-2018-3639) + +AMD Zen expose the Intel equivalant to Speculative Store Bypass Disable +via the 0x80000008_EBX[25] CPUID feature bit. + +This needs to be exposed to guest OS to allow them to protect +against CVE-2018-3639. + +Signed-off-by: Konrad Rzeszutek Wilk +--- +v2: Wrong bit position. +--- + target/i386/cpu.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +Index: qemu-2.11+dfsg/target/i386/cpu.c +=================================================================== +--- qemu-2.11+dfsg.orig/target/i386/cpu.c 2018-05-18 14:06:21.995005774 -0400 ++++ qemu-2.11+dfsg/target/i386/cpu.c 2018-05-18 14:06:21.991005779 -0400 +@@ -490,7 +490,7 @@ static FeatureWordInfo feature_word_info + "ibpb", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +- NULL, NULL, NULL, NULL, ++ NULL, "virt-ssbd", NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid_eax = 0x80000008, diff -Nru qemu-2.11+dfsg/debian/patches/ubuntu/CVE-2018-3639/0003-i386-Define-the-Virt-SSBD-MSR-and-handling-of-it-CVE.patch qemu-2.11+dfsg/debian/patches/ubuntu/CVE-2018-3639/0003-i386-Define-the-Virt-SSBD-MSR-and-handling-of-it-CVE.patch --- qemu-2.11+dfsg/debian/patches/ubuntu/CVE-2018-3639/0003-i386-Define-the-Virt-SSBD-MSR-and-handling-of-it-CVE.patch 1970-01-01 00:00:00.000000000 +0000 +++ qemu-2.11+dfsg/debian/patches/ubuntu/CVE-2018-3639/0003-i386-Define-the-Virt-SSBD-MSR-and-handling-of-it-CVE.patch 2018-05-18 18:08:09.000000000 +0000 @@ -0,0 +1,139 @@ +Backport of: + +From 80efc2c39c6b30aa077771903e87f8636af90605 Mon Sep 17 00:00:00 2001 +From: Konrad Rzeszutek Wilk +Date: Wed, 16 May 2018 22:27:11 -0400 +Subject: [PATCH v3 3/5] i386: Define the Virt SSBD MSR and handling of it + (CVE-2018-3639) + +"Some AMD processors only support a non-architectural means of enabling +speculative store bypass disable (SSBD). To allow a simplified view of +this to a guest, an architectural definition has been created through a new +CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f. With this, a +hypervisor can virtualize the existence of this definition and provide an +architectural method for using SSBD to a guest. + +Add the new CPUID feature, the new MSR and update the existing SSBD +support to use this MSR when present." (from x86/speculation: Add virtualized +speculative store bypass disable support in Linux). + +Signed-off-by: Konrad Rzeszutek Wilk +--- + target/i386/cpu.h | 2 ++ + target/i386/kvm.c | 16 ++++++++++++++-- + target/i386/machine.c | 20 ++++++++++++++++++++ + 3 files changed, 36 insertions(+), 2 deletions(-) + +Index: qemu-2.11+dfsg/target/i386/cpu.h +=================================================================== +--- qemu-2.11+dfsg.orig/target/i386/cpu.h 2018-05-18 14:06:32.450993530 -0400 ++++ qemu-2.11+dfsg/target/i386/cpu.h 2018-05-18 14:06:32.450993530 -0400 +@@ -336,6 +336,7 @@ + #define MSR_IA32_FEATURE_CONTROL 0x0000003a + #define MSR_TSC_ADJUST 0x0000003b + #define MSR_IA32_SPEC_CTRL 0x48 ++#define MSR_VIRT_SSBD 0xc001011f + #define MSR_IA32_TSCDEADLINE 0x6e0 + + #define FEATURE_CONTROL_LOCKED (1<<0) +@@ -1095,6 +1096,7 @@ typedef struct CPUX86State { + uint32_t pkru; + + uint64_t spec_ctrl; ++ uint64_t virt_ssbd; + + /* End of state preserved by INIT (dummy marker). */ + struct {} end_init_save; +Index: qemu-2.11+dfsg/target/i386/kvm.c +=================================================================== +--- qemu-2.11+dfsg.orig/target/i386/kvm.c 2018-05-18 14:06:32.450993530 -0400 ++++ qemu-2.11+dfsg/target/i386/kvm.c 2018-05-18 14:07:25.070939783 -0400 +@@ -92,6 +92,7 @@ static bool has_msr_hv_stimer; + static bool has_msr_hv_frequencies; + static bool has_msr_xss; + static bool has_msr_spec_ctrl; ++static bool has_msr_virt_ssbd; + + static bool has_msr_architectural_pmu; + static uint32_t num_architectural_pmu_counters; +@@ -1148,6 +1149,9 @@ static int kvm_get_supported_msrs(KVMSta + case MSR_IA32_SPEC_CTRL: + has_msr_spec_ctrl = true; + break; ++ case MSR_VIRT_SSBD: ++ has_msr_virt_ssbd = true; ++ break; + } + } + } +@@ -1633,6 +1637,10 @@ static int kvm_put_msrs(X86CPU *cpu, int + if (has_msr_spec_ctrl) { + kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl); + } ++ if (has_msr_virt_ssbd) { ++ kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd); ++ } ++ + #ifdef TARGET_X86_64 + if (lm_capable_kernel) { + kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar); +@@ -2009,8 +2017,9 @@ static int kvm_get_msrs(X86CPU *cpu) + if (has_msr_spec_ctrl) { + kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0); + } +- +- ++ if (has_msr_virt_ssbd) { ++ kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0); ++ } + if (!env->tsc_valid) { + kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0); + env->tsc_valid = !runstate_is_running(); +@@ -2361,6 +2370,9 @@ static int kvm_get_msrs(X86CPU *cpu) + case MSR_IA32_SPEC_CTRL: + env->spec_ctrl = msrs[i].data; + break; ++ case MSR_VIRT_SSBD: ++ env->virt_ssbd = msrs[i].data; ++ break; + } + } + +Index: qemu-2.11+dfsg/target/i386/machine.c +=================================================================== +--- qemu-2.11+dfsg.orig/target/i386/machine.c 2018-05-18 14:06:32.450993530 -0400 ++++ qemu-2.11+dfsg/target/i386/machine.c 2018-05-18 14:07:42.658924596 -0400 +@@ -837,6 +837,25 @@ static const VMStateDescription vmstate_ + } + }; + ++static bool virt_ssbd_needed(void *opaque) ++{ ++ X86CPU *cpu = opaque; ++ CPUX86State *env = &cpu->env; ++ ++ return env->virt_ssbd != 0; ++} ++ ++static const VMStateDescription vmstate_msr_virt_ssbd = { ++ .name = "cpu/virt_ssbd", ++ .version_id = 1, ++ .minimum_version_id = 1, ++ .needed = virt_ssbd_needed, ++ .fields = (VMStateField[]){ ++ VMSTATE_UINT64(env.virt_ssbd, X86CPU), ++ VMSTATE_END_OF_LIST() ++ } ++}; ++ + VMStateDescription vmstate_x86_cpu = { + .name = "cpu", + .version_id = 12, +@@ -957,6 +976,7 @@ VMStateDescription vmstate_x86_cpu = { + #endif + &vmstate_spec_ctrl, + &vmstate_mcg_ext_ctl, ++ &vmstate_msr_virt_ssbd, + NULL + } + };